code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright 2008 Cavium Networks
 */

#ifndef __MACH_BOARD_CNS3XXXH
#define __MACH_BOARD_CNS3XXXH

/*
 * Memory map
 */
#define CNS3XXX_FLASH_BASE			0x10000000	/* Flash/SRAM Memory Bank 0 */
#define CNS3XXX_FLASH_SIZE			SZ_256M

#define CNS3XXX_DDR2SDRAM_BASE			0x20000000	/* DDR2 SDRAM Memory */

#define CNS3XXX_SPI_FLASH_BASE			0x60000000	/* SPI Serial Flash Memory */

#define CNS3XXX_SWITCH_BASE			0x70000000	/* Switch and HNAT Control */

#define CNS3XXX_PPE_BASE			0x70001000	/* HANT	*/

#define CNS3XXX_EMBEDDED_SRAM_BASE		0x70002000	/* HANT Embedded SRAM */

#define CNS3XXX_SSP_BASE			0x71000000	/* Synchronous Serial Port - SPI/PCM/I2C */

#define CNS3XXX_DMC_BASE			0x72000000	/* DMC Control (DDR2 SDRAM) */

#define CNS3XXX_SMC_BASE			0x73000000	/* SMC Control */

#define SMC_MEMC_STATUS_OFFSET			0x000
#define SMC_MEMIF_CFG_OFFSET			0x004
#define SMC_MEMC_CFG_SET_OFFSET			0x008
#define SMC_MEMC_CFG_CLR_OFFSET			0x00C
#define SMC_DIRECT_CMD_OFFSET			0x010
#define SMC_SET_CYCLES_OFFSET			0x014
#define SMC_SET_OPMODE_OFFSET			0x018
#define SMC_REFRESH_PERIOD_0_OFFSET		0x020
#define SMC_REFRESH_PERIOD_1_OFFSET		0x024
#define SMC_SRAM_CYCLES0_0_OFFSET		0x100
#define SMC_NAND_CYCLES0_0_OFFSET		0x100
#define SMC_OPMODE0_0_OFFSET			0x104
#define SMC_SRAM_CYCLES0_1_OFFSET		0x120
#define SMC_NAND_CYCLES0_1_OFFSET		0x120
#define SMC_OPMODE0_1_OFFSET			0x124
#define SMC_USER_STATUS_OFFSET			0x200
#define SMC_USER_CONFIG_OFFSET			0x204
#define SMC_ECC_STATUS_OFFSET			0x300
#define SMC_ECC_MEMCFG_OFFSET			0x304
#define SMC_ECC_MEMCOMMAND1_OFFSET		0x308
#define SMC_ECC_MEMCOMMAND2_OFFSET		0x30C
#define SMC_ECC_ADDR0_OFFSET			0x310
#define SMC_ECC_ADDR1_OFFSET			0x314
#define SMC_ECC_VALUE0_OFFSET			0x318
#define SMC_ECC_VALUE1_OFFSET			0x31C
#define SMC_ECC_VALUE2_OFFSET			0x320
#define SMC_ECC_VALUE3_OFFSET			0x324
#define SMC_PERIPH_ID_0_OFFSET			0xFE0
#define SMC_PERIPH_ID_1_OFFSET			0xFE4
#define SMC_PERIPH_ID_2_OFFSET			0xFE8
#define SMC_PERIPH_ID_3_OFFSET			0xFEC
#define SMC_PCELL_ID_0_OFFSET			0xFF0
#define SMC_PCELL_ID_1_OFFSET			0xFF4
#define SMC_PCELL_ID_2_OFFSET			0xFF8
#define SMC_PCELL_ID_3_OFFSET			0xFFC

#define CNS3XXX_GPIOA_BASE			0x74000000	/* GPIO port A */

#define CNS3XXX_GPIOB_BASE			0x74800000	/* GPIO port B */

#define CNS3XXX_RTC_BASE			0x75000000	/* Real Time Clock */

#define RTC_SEC_OFFSET				0x00
#define RTC_MIN_OFFSET				0x04
#define RTC_HOUR_OFFSET				0x08
#define RTC_DAY_OFFSET				0x0C
#define RTC_SEC_ALM_OFFSET			0x10
#define RTC_MIN_ALM_OFFSET			0x14
#define RTC_HOUR_ALM_OFFSET			0x18
#define RTC_REC_OFFSET				0x1C
#define RTC_CTRL_OFFSET				0x20
#define RTC_INTR_STS_OFFSET			0x34

#define CNS3XXX_MISC_BASE			0x76000000	/* Misc Control */
#define CNS3XXX_MISC_BASE_VIRT			0xFB000000	/* Misc Control */

#define CNS3XXX_PM_BASE				0x77000000	/* Power Management Control */
#define CNS3XXX_PM_BASE_VIRT			0xFB001000

#define PM_CLK_GATE_OFFSET			0x00
#define PM_SOFT_RST_OFFSET			0x04
#define PM_HS_CFG_OFFSET			0x08
#define PM_CACTIVE_STA_OFFSET			0x0C
#define PM_PWR_STA_OFFSET			0x10
#define PM_SYS_CLK_CTRL_OFFSET			0x14
#define PM_PLL_LCD_I2S_CTRL_OFFSET		0x18
#define PM_PLL_HM_PD_OFFSET			0x1C

#define CNS3XXX_UART0_BASE			0x78000000	/* UART 0 */
#define CNS3XXX_UART0_BASE_VIRT			0xFB002000

#define CNS3XXX_UART1_BASE			0x78400000	/* UART 1 */

#define CNS3XXX_UART2_BASE			0x78800000	/* UART 2 */

#define CNS3XXX_DMAC_BASE			0x79000000	/* Generic DMA Control */

#define CNS3XXX_CORESIGHT_BASE			0x7A000000	/* CoreSight */

#define CNS3XXX_CRYPTO_BASE			0x7B000000	/* Crypto */

#define CNS3XXX_I2S_BASE			0x7C000000	/* I2S */

#define CNS3XXX_TIMER1_2_3_BASE			0x7C800000	/* Timer */
#define CNS3XXX_TIMER1_2_3_BASE_VIRT		0xFB003000

#define TIMER1_COUNTER_OFFSET			0x00
#define TIMER1_AUTO_RELOAD_OFFSET		0x04
#define TIMER1_MATCH_V1_OFFSET			0x08
#define TIMER1_MATCH_V2_OFFSET			0x0C

#define TIMER2_COUNTER_OFFSET			0x10
#define TIMER2_AUTO_RELOAD_OFFSET		0x14
#define TIMER2_MATCH_V1_OFFSET			0x18
#define TIMER2_MATCH_V2_OFFSET			0x1C

#define TIMER1_2_CONTROL_OFFSET			0x30
#define TIMER1_2_INTERRUPT_STATUS_OFFSET	0x34
#define TIMER1_2_INTERRUPT_MASK_OFFSET		0x38

#define TIMER_FREERUN_OFFSET			0x40
#define TIMER_FREERUN_CONTROL_OFFSET		0x44

#define CNS3XXX_HCIE_BASE			0x7D000000	/* HCIE Control */

#define CNS3XXX_RAID_BASE			0x7E000000	/* RAID Control */

#define CNS3XXX_AXI_IXC_BASE			0x7F000000	/* AXI IXC */

#define CNS3XXX_CLCD_BASE			0x80000000	/* LCD Control */

#define CNS3XXX_USBOTG_BASE			0x81000000	/* USB OTG Control */

#define CNS3XXX_USB_BASE			0x82000000	/* USB Host Control */

#define CNS3XXX_SATA2_BASE			0x83000000	/* SATA */
#define CNS3XXX_SATA2_SIZE			SZ_16M

#define CNS3XXX_CAMERA_BASE			0x84000000	/* Camera Interface */

#define CNS3XXX_SDIO_BASE			0x85000000	/* SDIO */

#define CNS3XXX_I2S_TDM_BASE			0x86000000	/* I2S TDM */

#define CNS3XXX_2DG_BASE			0x87000000	/* 2D Graphic Control */

#define CNS3XXX_USB_OHCI_BASE			0x88000000	/* USB OHCI */

#define CNS3XXX_L2C_BASE			0x92000000	/* L2 Cache Control */

#define CNS3XXX_PCIE0_MEM_BASE			0xA0000000	/* PCIe Port 0 IO/Memory Space */

#define CNS3XXX_PCIE0_HOST_BASE			0xAB000000	/* PCIe Port 0 RC Base */
#define CNS3XXX_PCIE0_HOST_BASE_VIRT		0xE1000000

#define CNS3XXX_PCIE0_IO_BASE			0xAC000000	/* PCIe Port 0 */

#define CNS3XXX_PCIE0_CFG0_BASE			0xAD000000	/* PCIe Port 0 CFG Type 0 */
#define CNS3XXX_PCIE0_CFG0_BASE_VIRT		0xE3000000

#define CNS3XXX_PCIE0_CFG1_BASE			0xAE000000	/* PCIe Port 0 CFG Type 1 */
#define CNS3XXX_PCIE0_CFG1_BASE_VIRT		0xE4000000

#define CNS3XXX_PCIE0_MSG_BASE			0xAF000000	/* PCIe Port 0 Message Space */

#define CNS3XXX_PCIE1_MEM_BASE			0xB0000000	/* PCIe Port 1 IO/Memory Space */

#define CNS3XXX_PCIE1_HOST_BASE			0xBB000000	/* PCIe Port 1 RC Base */
#define CNS3XXX_PCIE1_HOST_BASE_VIRT		0xE9000000

#define CNS3XXX_PCIE1_IO_BASE			0xBC000000	/* PCIe Port 1 */

#define CNS3XXX_PCIE1_CFG0_BASE			0xBD000000	/* PCIe Port 1 CFG Type 0 */
#define CNS3XXX_PCIE1_CFG0_BASE_VIRT		0xEB000000

#define CNS3XXX_PCIE1_CFG1_BASE			0xBE000000	/* PCIe Port 1 CFG Type 1 */
#define CNS3XXX_PCIE1_CFG1_BASE_VIRT		0xEC000000

#define CNS3XXX_PCIE1_MSG_BASE			0xBF000000	/* PCIe Port 1 Message Space */

/*
 * Testchip peripheral and fpga gic regions
 */
#define CNS3XXX_TC11MP_SCU_BASE			0x90000000	/* IRQ, Test chip */
#define CNS3XXX_TC11MP_SCU_BASE_VIRT		0xFB004000

#define CNS3XXX_TC11MP_GIC_CPU_BASE		0x90000100	/* Test chip interrupt controller CPU interface */
#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT	(CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)

#define CNS3XXX_TC11MP_TWD_BASE			0x90000600
#define CNS3XXX_TC11MP_TWD_BASE_VIRT		(CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)

#define CNS3XXX_TC11MP_GIC_DIST_BASE		0x90001000	/* Test chip interrupt controller distributor */
#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT	(CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)

#define CNS3XXX_TC11MP_L220_BASE		0x92002000	/* L220 registers */

/*
 * Misc block
 */
#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))

#define MISC_MEMORY_REMAP_REG			MISC_MEM_MAP(0x00)
#define MISC_CHIP_CONFIG_REG			MISC_MEM_MAP(0x04)
#define MISC_DEBUG_PROBE_DATA_REG		MISC_MEM_MAP(0x08)
#define MISC_DEBUG_PROBE_SELECTION_REG		MISC_MEM_MAP(0x0C)
#define MISC_IO_PIN_FUNC_SELECTION_REG		MISC_MEM_MAP(0x10)
#define MISC_GPIOA_PIN_ENABLE_REG		MISC_MEM_MAP(0x14)
#define MISC_GPIOB_PIN_ENABLE_REG		MISC_MEM_MAP(0x18)
#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A	MISC_MEM_MAP(0x1C)
#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B	MISC_MEM_MAP(0x20)
#define MISC_GPIOA_15_0_PULL_CTRL_REG		MISC_MEM_MAP(0x24)
#define MISC_GPIOA_16_31_PULL_CTRL_REG		MISC_MEM_MAP(0x28)
#define MISC_GPIOB_15_0_PULL_CTRL_REG		MISC_MEM_MAP(0x2C)
#define MISC_GPIOB_16_31_PULL_CTRL_REG		MISC_MEM_MAP(0x30)
#define MISC_IO_PULL_CTRL_REG			MISC_MEM_MAP(0x34)
#define MISC_E_FUSE_31_0_REG			MISC_MEM_MAP(0x40)
#define MISC_E_FUSE_63_32_REG			MISC_MEM_MAP(0x44)
#define MISC_E_FUSE_95_64_REG			MISC_MEM_MAP(0x48)
#define MISC_E_FUSE_127_96_REG			MISC_MEM_MAP(0x4C)
#define MISC_SOFTWARE_TEST_1_REG		MISC_MEM_MAP(0x50)
#define MISC_SOFTWARE_TEST_2_REG		MISC_MEM_MAP(0x54)

#define MISC_SATA_POWER_MODE			MISC_MEM_MAP(0x310)

#define MISC_USB_CFG_REG			MISC_MEM_MAP(0x800)
#define MISC_USB_STS_REG			MISC_MEM_MAP(0x804)
#define MISC_USBPHY00_CFG_REG			MISC_MEM_MAP(0x808)
#define MISC_USBPHY01_CFG_REG			MISC_MEM_MAP(0x80c)
#define MISC_USBPHY10_CFG_REG			MISC_MEM_MAP(0x810)
#define MISC_USBPHY11_CFG_REG			MISC_MEM_MAP(0x814)

#define MISC_PCIEPHY_CMCTL(x)			MISC_MEM_MAP(0x900 + (x) * 0x004)
#define MISC_PCIEPHY_CTL(x)			MISC_MEM_MAP(0x940 + (x) * 0x100)
#define MISC_PCIE_AXIS_AWMISC(x)		MISC_MEM_MAP(0x944 + (x) * 0x100)
#define MISC_PCIE_AXIS_ARMISC(x)		MISC_MEM_MAP(0x948 + (x) * 0x100)
#define MISC_PCIE_AXIS_RMISC(x)			MISC_MEM_MAP(0x94C + (x) * 0x100)
#define MISC_PCIE_AXIS_BMISC(x)			MISC_MEM_MAP(0x950 + (x) * 0x100)
#define MISC_PCIE_AXIM_RMISC(x)			MISC_MEM_MAP(0x954 + (x) * 0x100)
#define MISC_PCIE_AXIM_BMISC(x)			MISC_MEM_MAP(0x958 + (x) * 0x100)
#define MISC_PCIE_CTRL(x)			MISC_MEM_MAP(0x95C + (x) * 0x100)
#define MISC_PCIE_PM_DEBUG(x)			MISC_MEM_MAP(0x960 + (x) * 0x100)
#define MISC_PCIE_RFC_DEBUG(x)			MISC_MEM_MAP(0x964 + (x) * 0x100)
#define MISC_PCIE_CXPL_DEBUGL(x)		MISC_MEM_MAP(0x968 + (x) * 0x100)
#define MISC_PCIE_CXPL_DEBUGH(x)		MISC_MEM_MAP(0x96C + (x) * 0x100)
#define MISC_PCIE_DIAG_DEBUGH(x)		MISC_MEM_MAP(0x970 + (x) * 0x100)
#define MISC_PCIE_W1CLR(x)			MISC_MEM_MAP(0x974 + (x) * 0x100)
#define MISC_PCIE_INT_MASK(x)			MISC_MEM_MAP(0x978 + (x) * 0x100)
#define MISC_PCIE_INT_STATUS(x)			MISC_MEM_MAP(0x97C + (x) * 0x100)

/*
 * Power management and clock control
 */
#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))

#define PM_CLK_GATE_REG					PMU_MEM_MAP(0x000)
#define PM_SOFT_RST_REG					PMU_MEM_MAP(0x004)
#define PM_HS_CFG_REG					PMU_MEM_MAP(0x008)
#define PM_CACTIVE_STA_REG				PMU_MEM_MAP(0x00C)
#define PM_PWR_STA_REG					PMU_MEM_MAP(0x010)
#define PM_CLK_CTRL_REG					PMU_MEM_MAP(0x014)
#define PM_PLL_LCD_I2S_CTRL_REG				PMU_MEM_MAP(0x018)
#define PM_PLL_HM_PD_CTRL_REG				PMU_MEM_MAP(0x01C)
#define PM_REGULAT_CTRL_REG				PMU_MEM_MAP(0x020)
#define PM_WDT_CTRL_REG					PMU_MEM_MAP(0x024)
#define PM_WU_CTRL0_REG					PMU_MEM_MAP(0x028)
#define PM_WU_CTRL1_REG					PMU_MEM_MAP(0x02C)
#define PM_CSR_REG					PMU_MEM_MAP(0x030)

/* PM_CLK_GATE_REG */
#define PM_CLK_GATE_REG_OFFSET_SDIO			(25)
#define PM_CLK_GATE_REG_OFFSET_GPU			(24)
#define PM_CLK_GATE_REG_OFFSET_CIM			(23)
#define PM_CLK_GATE_REG_OFFSET_LCDC			(22)
#define PM_CLK_GATE_REG_OFFSET_I2S			(21)
#define PM_CLK_GATE_REG_OFFSET_RAID			(20)
#define PM_CLK_GATE_REG_OFFSET_SATA			(19)
#define PM_CLK_GATE_REG_OFFSET_PCIE(x)			(17 + (x))
#define PM_CLK_GATE_REG_OFFSET_USB_HOST			(16)
#define PM_CLK_GATE_REG_OFFSET_USB_OTG			(15)
#define PM_CLK_GATE_REG_OFFSET_TIMER			(14)
#define PM_CLK_GATE_REG_OFFSET_CRYPTO			(13)
#define PM_CLK_GATE_REG_OFFSET_HCIE			(12)
#define PM_CLK_GATE_REG_OFFSET_SWITCH			(11)
#define PM_CLK_GATE_REG_OFFSET_GPIO			(10)
#define PM_CLK_GATE_REG_OFFSET_UART3			(9)
#define PM_CLK_GATE_REG_OFFSET_UART2			(8)
#define PM_CLK_GATE_REG_OFFSET_UART1			(7)
#define PM_CLK_GATE_REG_OFFSET_RTC			(5)
#define PM_CLK_GATE_REG_OFFSET_GDMA			(4)
#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C		(3)
#define PM_CLK_GATE_REG_OFFSET_SMC_NFI			(1)
#define PM_CLK_GATE_REG_MASK				(0x03FFFFBA)

/* PM_SOFT_RST_REG */
#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG		(31)
#define PM_SOFT_RST_REG_OFFST_CPU1			(29)
#define PM_SOFT_RST_REG_OFFST_CPU0			(28)
#define PM_SOFT_RST_REG_OFFST_SDIO			(25)
#define PM_SOFT_RST_REG_OFFST_GPU			(24)
#define PM_SOFT_RST_REG_OFFST_CIM			(23)
#define PM_SOFT_RST_REG_OFFST_LCDC			(22)
#define PM_SOFT_RST_REG_OFFST_I2S			(21)
#define PM_SOFT_RST_REG_OFFST_RAID			(20)
#define PM_SOFT_RST_REG_OFFST_SATA			(19)
#define PM_SOFT_RST_REG_OFFST_PCIE(x)			(17 + (x))
#define PM_SOFT_RST_REG_OFFST_USB_HOST			(16)
#define PM_SOFT_RST_REG_OFFST_USB_OTG			(15)
#define PM_SOFT_RST_REG_OFFST_TIMER			(14)
#define PM_SOFT_RST_REG_OFFST_CRYPTO			(13)
#define PM_SOFT_RST_REG_OFFST_HCIE			(12)
#define PM_SOFT_RST_REG_OFFST_SWITCH			(11)
#define PM_SOFT_RST_REG_OFFST_GPIO			(10)
#define PM_SOFT_RST_REG_OFFST_UART3			(9)
#define PM_SOFT_RST_REG_OFFST_UART2			(8)
#define PM_SOFT_RST_REG_OFFST_UART1			(7)
#define PM_SOFT_RST_REG_OFFST_RTC			(5)
#define PM_SOFT_RST_REG_OFFST_GDMA			(4)
#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C		(3)
#define PM_SOFT_RST_REG_OFFST_DMC			(2)
#define PM_SOFT_RST_REG_OFFST_SMC_NFI			(1)
#define PM_SOFT_RST_REG_OFFST_GLOBAL			(0)
#define PM_SOFT_RST_REG_MASK				(0xF3FFFFBF)

/* PMHS_CFG_REG */
#define PM_HS_CFG_REG_OFFSET_SDIO			(25)
#define PM_HS_CFG_REG_OFFSET_GPU			(24)
#define PM_HS_CFG_REG_OFFSET_CIM			(23)
#define PM_HS_CFG_REG_OFFSET_LCDC			(22)
#define PM_HS_CFG_REG_OFFSET_I2S			(21)
#define PM_HS_CFG_REG_OFFSET_RAID			(20)
#define PM_HS_CFG_REG_OFFSET_SATA			(19)
#define PM_HS_CFG_REG_OFFSET_PCIE1			(18)
#define PM_HS_CFG_REG_OFFSET_PCIE0			(17)
#define PM_HS_CFG_REG_OFFSET_USB_HOST			(16)
#define PM_HS_CFG_REG_OFFSET_USB_OTG			(15)
#define PM_HS_CFG_REG_OFFSET_TIMER			(14)
#define PM_HS_CFG_REG_OFFSET_CRYPTO			(13)
#define PM_HS_CFG_REG_OFFSET_HCIE			(12)
#define PM_HS_CFG_REG_OFFSET_SWITCH			(11)
#define PM_HS_CFG_REG_OFFSET_GPIO			(10)
#define PM_HS_CFG_REG_OFFSET_UART3			(9)
#define PM_HS_CFG_REG_OFFSET_UART2			(8)
#define PM_HS_CFG_REG_OFFSET_UART1			(7)
#define PM_HS_CFG_REG_OFFSET_RTC			(5)
#define PM_HS_CFG_REG_OFFSET_GDMA			(4)
#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S		(3)
#define PM_HS_CFG_REG_OFFSET_DMC			(2)
#define PM_HS_CFG_REG_OFFSET_SMC_NFI			(1)
#define PM_HS_CFG_REG_MASK				(0x03FFFFBE)
#define PM_HS_CFG_REG_MASK_SUPPORT			(0x01100806)

/* PM_CACTIVE_STA_REG */
#define PM_CACTIVE_STA_REG_OFFSET_SDIO			(25)
#define PM_CACTIVE_STA_REG_OFFSET_GPU			(24)
#define PM_CACTIVE_STA_REG_OFFSET_CIM			(23)
#define PM_CACTIVE_STA_REG_OFFSET_LCDC			(22)
#define PM_CACTIVE_STA_REG_OFFSET_I2S			(21)
#define PM_CACTIVE_STA_REG_OFFSET_RAID			(20)
#define PM_CACTIVE_STA_REG_OFFSET_SATA			(19)
#define PM_CACTIVE_STA_REG_OFFSET_PCIE1			(18)
#define PM_CACTIVE_STA_REG_OFFSET_PCIE0			(17)
#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST		(16)
#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG		(15)
#define PM_CACTIVE_STA_REG_OFFSET_TIMER			(14)
#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO		(13)
#define PM_CACTIVE_STA_REG_OFFSET_HCIE			(12)
#define PM_CACTIVE_STA_REG_OFFSET_SWITCH		(11)
#define PM_CACTIVE_STA_REG_OFFSET_GPIO			(10)
#define PM_CACTIVE_STA_REG_OFFSET_UART3			(9)
#define PM_CACTIVE_STA_REG_OFFSET_UART2			(8)
#define PM_CACTIVE_STA_REG_OFFSET_UART1			(7)
#define PM_CACTIVE_STA_REG_OFFSET_RTC			(5)
#define PM_CACTIVE_STA_REG_OFFSET_GDMA			(4)
#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S		(3)
#define PM_CACTIVE_STA_REG_OFFSET_DMC			(2)
#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI		(1)
#define PM_CACTIVE_STA_REG_MASK				(0x03FFFFBE)

/* PM_PWR_STA_REG */
#define PM_PWR_STA_REG_REG_OFFSET_SDIO			(25)
#define PM_PWR_STA_REG_REG_OFFSET_GPU			(24)
#define PM_PWR_STA_REG_REG_OFFSET_CIM			(23)
#define PM_PWR_STA_REG_REG_OFFSET_LCDC			(22)
#define PM_PWR_STA_REG_REG_OFFSET_I2S			(21)
#define PM_PWR_STA_REG_REG_OFFSET_RAID			(20)
#define PM_PWR_STA_REG_REG_OFFSET_SATA			(19)
#define PM_PWR_STA_REG_REG_OFFSET_PCIE1			(18)
#define PM_PWR_STA_REG_REG_OFFSET_PCIE0			(17)
#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST		(16)
#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG		(15)
#define PM_PWR_STA_REG_REG_OFFSET_TIMER			(14)
#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO		(13)
#define PM_PWR_STA_REG_REG_OFFSET_HCIE			(12)
#define PM_PWR_STA_REG_REG_OFFSET_SWITCH		(11)
#define PM_PWR_STA_REG_REG_OFFSET_GPIO			(10)
#define PM_PWR_STA_REG_REG_OFFSET_UART3			(9)
#define PM_PWR_STA_REG_REG_OFFSET_UART2			(8)
#define PM_PWR_STA_REG_REG_OFFSET_UART1			(7)
#define PM_PWR_STA_REG_REG_OFFSET_RTC			(5)
#define PM_PWR_STA_REG_REG_OFFSET_GDMA			(4)
#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S		(3)
#define PM_PWR_STA_REG_REG_OFFSET_DMC			(2)
#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI		(1)
#define PM_PWR_STA_REG_REG_MASK				(0x03FFFFBE)

/* PM_CLK_CTRL_REG */
#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK			(31)
#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN		(30)
#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN		(29)
#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN		(28)
#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE		(27)
#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV		(24)
#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL		(22)
#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV		(20)
#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL		(16)
#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV			(14)
#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL		(12)
#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE		(9)
#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL		(7)
#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE		(6)
#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV		(4)
#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL		(0)

#define PM_CPU_CLK_DIV(DIV) { \
	PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
	PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
}

#define PM_PLL_CPU_SEL(CPU) { \
	PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
	PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
}

/* PM_PLL_LCD_I2S_CTRL_REG */
#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV	(22)
#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL		(17)
#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P	(11)
#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M	(3)
#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S	(0)

/* PM_PLL_HM_PD_CTRL_REG */
#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1		(11)
#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0		(10)
#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD		(6)
#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S		(5)
#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD		(4)
#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB		(3)
#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII		(2)
#define PM_PLL_HM_PD_CTRL_REG_MASK			(0x00000C7C)

/* PM_WDT_CTRL_REG */
#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY		(0)

/* PM_CSR_REG - Clock Scaling Register*/
#define PM_CSR_REG_OFFSET_CSR_EN			(30)
#define PM_CSR_REG_OFFSET_CSR_NUM			(0)

#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK)

/* Software reset*/
#define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK)

/*
 * CNS3XXX support several power saving mode as following,
 * DFS, IDLE, HALT, DOZE, SLEEP, Hibernate
 */
#define CNS3XXX_PWR_CPU_MODE_DFS			(0)
#define CNS3XXX_PWR_CPU_MODE_IDLE			(1)
#define CNS3XXX_PWR_CPU_MODE_HALT			(2)
#define CNS3XXX_PWR_CPU_MODE_DOZE			(3)
#define CNS3XXX_PWR_CPU_MODE_SLEEP			(4)
#define CNS3XXX_PWR_CPU_MODE_HIBERNATE			(5)

#define CNS3XXX_PWR_PLL(BLOCK)	(0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK)
#define CNS3XXX_PWR_PLL_ALL	PM_PLL_HM_PD_CTRL_REG_MASK

/* Change CPU frequency and divider */
#define CNS3XXX_PWR_PLL_CPU_300MHZ			(0)
#define CNS3XXX_PWR_PLL_CPU_333MHZ			(1)
#define CNS3XXX_PWR_PLL_CPU_366MHZ			(2)
#define CNS3XXX_PWR_PLL_CPU_400MHZ			(3)
#define CNS3XXX_PWR_PLL_CPU_433MHZ			(4)
#define CNS3XXX_PWR_PLL_CPU_466MHZ			(5)
#define CNS3XXX_PWR_PLL_CPU_500MHZ			(6)
#define CNS3XXX_PWR_PLL_CPU_533MHZ			(7)
#define CNS3XXX_PWR_PLL_CPU_566MHZ			(8)
#define CNS3XXX_PWR_PLL_CPU_600MHZ			(9)
#define CNS3XXX_PWR_PLL_CPU_633MHZ			(10)
#define CNS3XXX_PWR_PLL_CPU_666MHZ			(11)
#define CNS3XXX_PWR_PLL_CPU_700MHZ			(12)

#define CNS3XXX_PWR_CPU_CLK_DIV_BY1			(0)
#define CNS3XXX_PWR_CPU_CLK_DIV_BY2			(1)
#define CNS3XXX_PWR_CPU_CLK_DIV_BY4			(2)

/* Change DDR2 frequency */
#define CNS3XXX_PWR_PLL_DDR2_200MHZ			(0)
#define CNS3XXX_PWR_PLL_DDR2_266MHZ			(1)
#define CNS3XXX_PWR_PLL_DDR2_333MHZ			(2)
#define CNS3XXX_PWR_PLL_DDR2_400MHZ			(3)

void cns3xxx_pwr_soft_rst(unsigned int block);
void cns3xxx_pwr_clk_en(unsigned int block);
int cns3xxx_cpu_clock(void);

/*
 * ARM11 MPCore interrupt sources (primary GIC)
 */
#define IRQ_TC11MP_GIC_START	32

#define IRQ_CNS3XXX_PMU			(IRQ_TC11MP_GIC_START + 0)
#define IRQ_CNS3XXX_SDIO		(IRQ_TC11MP_GIC_START + 1)
#define IRQ_CNS3XXX_L2CC		(IRQ_TC11MP_GIC_START + 2)
#define IRQ_CNS3XXX_RTC			(IRQ_TC11MP_GIC_START + 3)
#define IRQ_CNS3XXX_I2S			(IRQ_TC11MP_GIC_START + 4)
#define IRQ_CNS3XXX_PCM			(IRQ_TC11MP_GIC_START + 5)
#define IRQ_CNS3XXX_SPI			(IRQ_TC11MP_GIC_START + 6)
#define IRQ_CNS3XXX_I2C			(IRQ_TC11MP_GIC_START + 7)
#define IRQ_CNS3XXX_CIM			(IRQ_TC11MP_GIC_START + 8)
#define IRQ_CNS3XXX_GPU			(IRQ_TC11MP_GIC_START + 9)
#define IRQ_CNS3XXX_LCD			(IRQ_TC11MP_GIC_START + 10)
#define IRQ_CNS3XXX_GPIOA		(IRQ_TC11MP_GIC_START + 11)
#define IRQ_CNS3XXX_GPIOB		(IRQ_TC11MP_GIC_START + 12)
#define IRQ_CNS3XXX_UART0		(IRQ_TC11MP_GIC_START + 13)
#define IRQ_CNS3XXX_UART1		(IRQ_TC11MP_GIC_START + 14)
#define IRQ_CNS3XXX_UART2		(IRQ_TC11MP_GIC_START + 15)
#define IRQ_CNS3XXX_ARM11		(IRQ_TC11MP_GIC_START + 16)

#define IRQ_CNS3XXX_SW_STATUS		(IRQ_TC11MP_GIC_START + 17)
#define IRQ_CNS3XXX_SW_R0TXC		(IRQ_TC11MP_GIC_START + 18)
#define IRQ_CNS3XXX_SW_R0RXC		(IRQ_TC11MP_GIC_START + 19)
#define IRQ_CNS3XXX_SW_R0QE		(IRQ_TC11MP_GIC_START + 20)
#define IRQ_CNS3XXX_SW_R0QF		(IRQ_TC11MP_GIC_START + 21)
#define IRQ_CNS3XXX_SW_R1TXC		(IRQ_TC11MP_GIC_START + 22)
#define IRQ_CNS3XXX_SW_R1RXC		(IRQ_TC11MP_GIC_START + 23)
#define IRQ_CNS3XXX_SW_R1QE		(IRQ_TC11MP_GIC_START + 24)
#define IRQ_CNS3XXX_SW_R1QF		(IRQ_TC11MP_GIC_START + 25)
#define IRQ_CNS3XXX_SW_PPE		(IRQ_TC11MP_GIC_START + 26)

#define IRQ_CNS3XXX_CRYPTO		(IRQ_TC11MP_GIC_START + 27)
#define IRQ_CNS3XXX_HCIE		(IRQ_TC11MP_GIC_START + 28)
#define IRQ_CNS3XXX_PCIE0_DEVICE	(IRQ_TC11MP_GIC_START + 29)
#define IRQ_CNS3XXX_PCIE1_DEVICE	(IRQ_TC11MP_GIC_START + 30)
#define IRQ_CNS3XXX_USB_OTG		(IRQ_TC11MP_GIC_START + 31)
#define IRQ_CNS3XXX_USB_EHCI		(IRQ_TC11MP_GIC_START + 32)
#define IRQ_CNS3XXX_SATA		(IRQ_TC11MP_GIC_START + 33)
#define IRQ_CNS3XXX_RAID		(IRQ_TC11MP_GIC_START + 34)
#define IRQ_CNS3XXX_SMC			(IRQ_TC11MP_GIC_START + 35)

#define IRQ_CNS3XXX_DMAC_ABORT		(IRQ_TC11MP_GIC_START + 36)
#define IRQ_CNS3XXX_DMAC0		(IRQ_TC11MP_GIC_START + 37)
#define IRQ_CNS3XXX_DMAC1		(IRQ_TC11MP_GIC_START + 38)
#define IRQ_CNS3XXX_DMAC2		(IRQ_TC11MP_GIC_START + 39)
#define IRQ_CNS3XXX_DMAC3		(IRQ_TC11MP_GIC_START + 40)
#define IRQ_CNS3XXX_DMAC4		(IRQ_TC11MP_GIC_START + 41)
#define IRQ_CNS3XXX_DMAC5		(IRQ_TC11MP_GIC_START + 42)
#define IRQ_CNS3XXX_DMAC6		(IRQ_TC11MP_GIC_START + 43)
#define IRQ_CNS3XXX_DMAC7		(IRQ_TC11MP_GIC_START + 44)
#define IRQ_CNS3XXX_DMAC8		(IRQ_TC11MP_GIC_START + 45)
#define IRQ_CNS3XXX_DMAC9		(IRQ_TC11MP_GIC_START + 46)
#define IRQ_CNS3XXX_DMAC10		(IRQ_TC11MP_GIC_START + 47)
#define IRQ_CNS3XXX_DMAC11		(IRQ_TC11MP_GIC_START + 48)
#define IRQ_CNS3XXX_DMAC12		(IRQ_TC11MP_GIC_START + 49)
#define IRQ_CNS3XXX_DMAC13		(IRQ_TC11MP_GIC_START + 50)
#define IRQ_CNS3XXX_DMAC14		(IRQ_TC11MP_GIC_START + 51)
#define IRQ_CNS3XXX_DMAC15		(IRQ_TC11MP_GIC_START + 52)
#define IRQ_CNS3XXX_DMAC16		(IRQ_TC11MP_GIC_START + 53)
#define IRQ_CNS3XXX_DMAC17		(IRQ_TC11MP_GIC_START + 54)

#define IRQ_CNS3XXX_PCIE0_RC		(IRQ_TC11MP_GIC_START + 55)
#define IRQ_CNS3XXX_PCIE1_RC		(IRQ_TC11MP_GIC_START + 56)
#define IRQ_CNS3XXX_TIMER0		(IRQ_TC11MP_GIC_START + 57)
#define IRQ_CNS3XXX_TIMER1		(IRQ_TC11MP_GIC_START + 58)
#define IRQ_CNS3XXX_USB_OHCI		(IRQ_TC11MP_GIC_START + 59)
#define IRQ_CNS3XXX_TIMER2		(IRQ_TC11MP_GIC_START + 60)
#define IRQ_CNS3XXX_EXTERNAL_PIN0	(IRQ_TC11MP_GIC_START + 61)
#define IRQ_CNS3XXX_EXTERNAL_PIN1	(IRQ_TC11MP_GIC_START + 62)
#define IRQ_CNS3XXX_EXTERNAL_PIN2	(IRQ_TC11MP_GIC_START + 63)

#define NR_IRQS_CNS3XXX			(IRQ_TC11MP_GIC_START + 64)

#endif	/* __MACH_BOARD_CNS3XXX_H */


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 1999 - 2003 ARM Limited
 * Copyright 2000 Deep Blue Solutions Ltd
 * Copyright 2008 Cavium Networks
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/usb/ehci_pdriver.h>
#include <linux/usb/ohci_pdriver.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/hardware/cache-l2x0.h>
#include "cns3xxx.h"
#include "core.h"
#include "pm.h"

static struct map_desc cns3xxx_io_desc[] __initdata = {
	{
		.virtual	= CNS3XXX_TC11MP_SCU_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
		.length		= SZ_8K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_TIMER1_2_3_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_MISC_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_MISC_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_PM_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_PM_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
#ifdef CONFIG_PCI
	}, {
		.virtual	= CNS3XXX_PCIE0_HOST_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_PCIE0_CFG0_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
		.length		= SZ_64K, /* really 4 KiB at offset 32 KiB */
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_PCIE0_CFG1_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_PCIE1_HOST_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_PCIE1_CFG0_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
		.length		= SZ_64K, /* really 4 KiB at offset 32 KiB */
		.type		= MT_DEVICE,
	}, {
		.virtual	= CNS3XXX_PCIE1_CFG1_BASE_VIRT,
		.pfn		= __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
		.length		= SZ_16M,
		.type		= MT_DEVICE,
#endif
	},
};

void __init cns3xxx_map_io(void)
{
	iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
}

/* used by entry-macro.S */
void __init cns3xxx_init_irq(void)
{
	gic_init(IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
		 IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
}

void cns3xxx_power_off(void)
{
	u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT);
	u32 clkctrl;

	printk(KERN_INFO "powering system down...\n");

	clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
	clkctrl &= 0xfffff1ff;
	clkctrl |= (0x5 << 9);		/* Hibernate */
	writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);

}

/*
 * Timer
 */
static void __iomem *cns3xxx_tmr1;

static int cns3xxx_shutdown(struct clock_event_device *clk)
{
	writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	return 0;
}

static int cns3xxx_set_oneshot(struct clock_event_device *clk)
{
	unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);

	/* period set, and timer enabled in 'next_event' hook */
	ctrl |= (1 << 2) | (1 << 9);
	writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	return 0;
}

static int cns3xxx_set_periodic(struct clock_event_device *clk)
{
	unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	int pclk = cns3xxx_cpu_clock() / 8;
	int reload;

	reload = pclk * 20 / (3 * HZ) * 0x25000;
	writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
	ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
	writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	return 0;
}

static int cns3xxx_timer_set_next_event(unsigned long evt,
					struct clock_event_device *unused)
{
	unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);

	writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
	writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);

	return 0;
}

static struct clock_event_device cns3xxx_tmr1_clockevent = {
	.name			= "cns3xxx timer1",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown	= cns3xxx_shutdown,
	.set_state_periodic	= cns3xxx_set_periodic,
	.set_state_oneshot	= cns3xxx_set_oneshot,
	.tick_resume		= cns3xxx_shutdown,
	.set_next_event		= cns3xxx_timer_set_next_event,
	.rating			= 350,
	.cpumask		= cpu_all_mask,
};

static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
{
	cns3xxx_tmr1_clockevent.irq = timer_irq;
	clockevents_config_and_register(&cns3xxx_tmr1_clockevent,
					(cns3xxx_cpu_clock() >> 3) * 1000000,
					0xf, 0xffffffff);
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
	u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
	u32 val;

	/* Clear the interrupt */
	val = readl(stat);
	writel(val & ~(1 << 2), stat);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

/*
 * Set up the clock source and clock events devices
 */
static void __init __cns3xxx_timer_init(unsigned int timer_irq)
{
	u32 val;
	u32 irq_mask;

	/*
	 * Initialise to a known state (all timers off)
	 */

	/* disable timer1 and timer2 */
	writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	/* stop free running timer3 */
	writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);

	/* timer1 */
	writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
	writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);

	writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
	writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);

	/* mask irq, non-mask timer1 overflow */
	irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
	irq_mask &= ~(1 << 2);
	irq_mask |= 0x03;
	writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);

	/* down counter */
	val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	val |= (1 << 9);
	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);

	/* timer2 */
	writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
	writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);

	/* mask irq */
	irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
	irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
	writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);

	/* down counter */
	val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
	val |= (1 << 10);
	writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);

	/* Make irqs happen for the system timer */
	if (request_irq(timer_irq, cns3xxx_timer_interrupt,
			IRQF_TIMER | IRQF_IRQPOLL, "timer", NULL))
		pr_err("Failed to request irq %d (timer)\n", timer_irq);

	cns3xxx_clockevents_init(timer_irq);
}

void __init cns3xxx_timer_init(void)
{
	cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT);

	__cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
}

#ifdef CONFIG_CACHE_L2X0

void __init cns3xxx_l2x0_init(void)
{
	void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
	u32 val;

	if (WARN_ON(!base))
		return;

	/*
	 * Tag RAM Control register
	 *
	 * bit[10:8]	- 1 cycle of write accesses latency
	 * bit[6:4]	- 1 cycle of read accesses latency
	 * bit[3:0]	- 1 cycle of setup latency
	 *
	 * 1 cycle of latency for setup, read and write accesses
	 */
	val = readl(base + L310_TAG_LATENCY_CTRL);
	val &= 0xfffff888;
	writel(val, base + L310_TAG_LATENCY_CTRL);

	/*
	 * Data RAM Control register
	 *
	 * bit[10:8]	- 1 cycles of write accesses latency
	 * bit[6:4]	- 1 cycles of read accesses latency
	 * bit[3:0]	- 1 cycle of setup latency
	 *
	 * 1 cycle of latency for setup, read and write accesses
	 */
	val = readl(base + L310_DATA_LATENCY_CTRL);
	val &= 0xfffff888;
	writel(val, base + L310_DATA_LATENCY_CTRL);

	/* 32 KiB, 8-way, parity disable */
	l2x0_init(base, 0x00500000, 0xfe0f0fff);
}

#endif /* CONFIG_CACHE_L2X0 */

static int csn3xxx_usb_power_on(struct platform_device *pdev)
{
	/*
	 * EHCI and OHCI share the same clock and power,
	 * resetting twice would cause the 1st controller been reset.
	 * Therefore only do power up  at the first up device, and
	 * power down at the last down device.
	 *
	 * Set USB AHB INCR length to 16
	 */
	if (atomic_inc_return(&usb_pwr_ref) == 1) {
		cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
		cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
		cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
		__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
			MISC_CHIP_CONFIG_REG);
	}

	return 0;
}

static void csn3xxx_usb_power_off(struct platform_device *pdev)
{
	/*
	 * EHCI and OHCI share the same clock and power,
	 * resetting twice would cause the 1st controller been reset.
	 * Therefore only do power up  at the first up device, and
	 * power down at the last down device.
	 */
	if (atomic_dec_return(&usb_pwr_ref) == 0)
		cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
}

static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
	.power_on	= csn3xxx_usb_power_on,
	.power_off	= csn3xxx_usb_power_off,
};

static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
	.num_ports	= 1,
	.power_on	= csn3xxx_usb_power_on,
	.power_off	= csn3xxx_usb_power_off,
};

static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
	{ "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
	{ "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
	{ "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
	{ "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL },
	{},
};

static void __init cns3xxx_init(void)
{
	struct device_node *dn;

	cns3xxx_l2x0_init();

	dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci");
	if (of_device_is_available(dn)) {
		u32 tmp;

		tmp = __raw_readl(MISC_SATA_POWER_MODE);
		tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
		tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
		__raw_writel(tmp, MISC_SATA_POWER_MODE);

		/* Enable SATA PHY */
		cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
		cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);

		/* Enable SATA Clock */
		cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);

		/* De-Asscer SATA Reset */
		cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
	}
	of_node_put(dn);

	dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
	if (of_device_is_available(dn)) {
		u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
		u32 gpioa_pins = __raw_readl(gpioa);

		/* MMC/SD pins share with GPIOA */
		gpioa_pins |= 0x1fff0004;
		__raw_writel(gpioa_pins, gpioa);

		cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
		cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
	}
	of_node_put(dn);

	pm_power_off = cns3xxx_power_off;

	of_platform_default_populate(NULL, cns3xxx_auxdata, NULL);
}

static const char *const cns3xxx_dt_compat[] __initconst = {
	"cavium,cns3410",
	"cavium,cns3420",
	NULL,
};

DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
	.dt_compat	= cns3xxx_dt_compat,
	.map_io		= cns3xxx_map_io,
	.init_irq	= cns3xxx_init_irq,
	.init_time	= cns3xxx_timer_init,
	.init_machine	= cns3xxx_init,
	.init_late	= cns3xxx_pcie_init_late,
	.restart	= cns3xxx_restart,
MACHINE_END

repo_name: angery/linux


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright 2000 Deep Blue Solutions Ltd
 * Copyright 2004 ARM Limited
 * Copyright 2008 Cavium Networks
 */

#ifndef __CNS3XXX_CORE_H
#define __CNS3XXX_CORE_H

#include <linux/reboot.h>

extern void cns3xxx_timer_init(void);

#ifdef CONFIG_CACHE_L2X0
void __init cns3xxx_l2x0_init(void);
#else
static inline void cns3xxx_l2x0_init(void) {}
#endif /* CONFIG_CACHE_L2X0 */

#ifdef CONFIG_PCI
extern void __init cns3xxx_pcie_init_late(void);
#else
static inline void __init cns3xxx_pcie_init_late(void) {}
#endif

void __init cns3xxx_map_io(void);
void __init cns3xxx_init_irq(void);
void cns3xxx_power_off(void);
void cns3xxx_restart(enum reboot_mode, const char *);

#endif /* __CNS3XXX_CORE_H */


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * CNS3xxx common devices
 *
 * Copyright 2008 Cavium Networks
 *		  Scott Shu
 * Copyright 2010 MontaVista Software, LLC.
 *		  Anton Vorontsov <avorontsov@mvista.com>
 */

#include <linux/io.h>
#include <linux/init.h>
#include <linux/compiler.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include "cns3xxx.h"
#include "pm.h"
#include "core.h"
#include "devices.h"

/*
 * AHCI
 */
static struct resource cns3xxx_ahci_resource[] = {
	[0] = {
		.start	= CNS3XXX_SATA2_BASE,
		.end	= CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_CNS3XXX_SATA,
		.end	= IRQ_CNS3XXX_SATA,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);

static struct platform_device cns3xxx_ahci_pdev = {
	.name		= "ahci",
	.id		= 0,
	.resource	= cns3xxx_ahci_resource,
	.num_resources	= ARRAY_SIZE(cns3xxx_ahci_resource),
	.dev		= {
		.dma_mask		= &cns3xxx_ahci_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
};

void __init cns3xxx_ahci_init(void)
{
	u32 tmp;

	tmp = __raw_readl(MISC_SATA_POWER_MODE);
	tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
	tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
	__raw_writel(tmp, MISC_SATA_POWER_MODE);

	/* Enable SATA PHY */
	cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
	cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);

	/* Enable SATA Clock */
	cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);

	/* De-Asscer SATA Reset */
	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));

	platform_device_register(&cns3xxx_ahci_pdev);
}

/*
 * SDHCI
 */
static struct resource cns3xxx_sdhci_resources[] = {
	[0] = {
		.start = CNS3XXX_SDIO_BASE,
		.end   = CNS3XXX_SDIO_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = IRQ_CNS3XXX_SDIO,
		.end   = IRQ_CNS3XXX_SDIO,
		.flags = IORESOURCE_IRQ,
	},
};

static struct platform_device cns3xxx_sdhci_pdev = {
	.name		= "sdhci-cns3xxx",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(cns3xxx_sdhci_resources),
	.resource	= cns3xxx_sdhci_resources,
};

void __init cns3xxx_sdhci_init(void)
{
	u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
	u32 gpioa_pins = __raw_readl(gpioa);

	/* MMC/SD pins share with GPIOA */
	gpioa_pins |= 0x1fff0004;
	__raw_writel(gpioa_pins, gpioa);

	cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));

	platform_device_register(&cns3xxx_sdhci_pdev);
}


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * CNS3xxx common devices
 *
 * Copyright 2008 Cavium Networks
 *		  Scott Shu
 * Copyright 2010 MontaVista Software, LLC.
 *		  Anton Vorontsov <avorontsov@mvista.com>
 */

#ifndef __CNS3XXX_DEVICES_H_
#define __CNS3XXX_DEVICES_H_

void __init cns3xxx_ahci_init(void);
void __init cns3xxx_sdhci_init(void);

#endif /* __CNS3XXX_DEVICES_H_ */


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * PCI-E support for CNS3xxx
 *
 * Copyright 2008 Cavium Networks
 *		  Richard Liu <richard.liu@caviumnetworks.com>
 * Copyright 2010 MontaVista Software, LLC.
 *		  Anton Vorontsov <avorontsov@mvista.com>
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/bug.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <asm/mach/map.h>
#include "cns3xxx.h"
#include "core.h"

struct cns3xxx_pcie {
	void __iomem *host_regs; /* PCI config registers for host bridge */
	void __iomem *cfg0_regs; /* PCI Type 0 config registers */
	void __iomem *cfg1_regs; /* PCI Type 1 config registers */
	unsigned int irqs[2];
	struct resource res_io;
	struct resource res_mem;
	int port;
	bool linked;
};

static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
{
	struct pci_sys_data *root = sysdata;

	return root->private_data;
}

static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
{
	return sysdata_to_cnspci(dev->sysdata);
}

static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
{
	return sysdata_to_cnspci(bus->sysdata);
}

static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus,
					 unsigned int devfn, int where)
{
	struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
	int busno = bus->number;
	int slot = PCI_SLOT(devfn);
	void __iomem *base;

	/* If there is no link, just show the CNS PCI bridge. */
	if (!cnspci->linked && busno > 0)
		return NULL;

	/*
	 * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
	 * we still want to access it.
	 * We place the host bridge on bus 0, and the directly connected
	 * device on bus 1, slot 0.
	 */
	if (busno == 0) { /* internal PCIe bus, host bridge device */
		if (devfn == 0) /* device# and function# are ignored by hw */
			base = cnspci->host_regs;
		else
			return NULL; /* no such device */

	} else if (busno == 1) { /* directly connected PCIe device */
		if (slot == 0) /* device# is ignored by hw */
			base = cnspci->cfg0_regs;
		else
			return NULL; /* no such device */
	} else /* remote PCI bus */
		base = cnspci->cfg1_regs + ((busno & 0xf) << 20);

	return base + where + (devfn << 12);
}

static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
				   int where, int size, u32 *val)
{
	int ret;
	u32 mask = (0x1ull << (size * 8)) - 1;
	int shift = (where % 4) * 8;

	ret = pci_generic_config_read(bus, devfn, where, size, val);

	if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
	    (where & 0xffc) == PCI_CLASS_REVISION)
		/*
		 * RC's class is 0xb, but Linux PCI driver needs 0x604
		 * for a PCIe bridge. So we must fixup the class code
		 * to 0x604 here.
		 */
		*val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask;

	return ret;
}

static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
{
	struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
	struct resource *res_io = &cnspci->res_io;
	struct resource *res_mem = &cnspci->res_mem;

	BUG_ON(request_resource(&iomem_resource, res_io) ||
	       request_resource(&iomem_resource, res_mem));

	pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
	pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);

	return 1;
}

static struct pci_ops cns3xxx_pcie_ops = {
	.map_bus = cns3xxx_pci_map_bus,
	.read = cns3xxx_pci_read_config,
	.write = pci_generic_config_write,
};

static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
	int irq = cnspci->irqs[!!dev->bus->number];

	pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
		pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
		PCI_FUNC(dev->devfn), slot, pin, irq);

	return irq;
}

static struct cns3xxx_pcie cns3xxx_pcie[] = {
	[0] = {
		.host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT,
		.cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT,
		.cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT,
		.res_io = {
			.name = "PCIe0 I/O space",
			.start = CNS3XXX_PCIE0_IO_BASE,
			.end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */
			.flags = IORESOURCE_IO,
		},
		.res_mem = {
			.name = "PCIe0 non-prefetchable",
			.start = CNS3XXX_PCIE0_MEM_BASE,
			.end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */
			.flags = IORESOURCE_MEM,
		},
		.irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
		.port = 0,
	},
	[1] = {
		.host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT,
		.cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT,
		.cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT,
		.res_io = {
			.name = "PCIe1 I/O space",
			.start = CNS3XXX_PCIE1_IO_BASE,
			.end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */
			.flags = IORESOURCE_IO,
		},
		.res_mem = {
			.name = "PCIe1 non-prefetchable",
			.start = CNS3XXX_PCIE1_MEM_BASE,
			.end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */
			.flags = IORESOURCE_MEM,
		},
		.irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
		.port = 1,
	},
};

static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
{
	int port = cnspci->port;
	u32 reg;
	unsigned long time;

	reg = __raw_readl(MISC_PCIE_CTRL(port));
	/*
	 * Enable Application Request to 1, it will exit L1 automatically,
	 * but when chip back, it will use another clock, still can use 0x1.
	 */
	reg |= 0x3;
	__raw_writel(reg, MISC_PCIE_CTRL(port));

	pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
	pr_info("PCIe: Port[%d] Check data link layer...", port);

	time = jiffies;
	while (1) {
		reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
		if (reg & 0x1) {
			pr_info("Link up.\n");
			cnspci->linked = 1;
			break;
		} else if (time_after(jiffies, time + 50)) {
			pr_info("Device not found.\n");
			break;
		}
	}
}

static void cns3xxx_write_config(struct cns3xxx_pcie *cnspci,
					 int where, int size, u32 val)
{
	void __iomem *base = cnspci->host_regs + (where & 0xffc);
	u32 v;
	u32 mask = (0x1ull << (size * 8)) - 1;
	int shift = (where % 4) * 8;

	v = readl_relaxed(base);

	v &= ~(mask << shift);
	v |= (val & mask) << shift;

	writel_relaxed(v, base);
	readl_relaxed(base);
}

static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
{
	u16 mem_base  = cnspci->res_mem.start >> 16;
	u16 mem_limit = cnspci->res_mem.end   >> 16;
	u16 io_base   = cnspci->res_io.start  >> 16;
	u16 io_limit  = cnspci->res_io.end    >> 16;

	cns3xxx_write_config(cnspci, PCI_PRIMARY_BUS, 1, 0);
	cns3xxx_write_config(cnspci, PCI_SECONDARY_BUS, 1, 1);
	cns3xxx_write_config(cnspci, PCI_SUBORDINATE_BUS, 1, 1);
	cns3xxx_write_config(cnspci, PCI_MEMORY_BASE, 2, mem_base);
	cns3xxx_write_config(cnspci, PCI_MEMORY_LIMIT, 2, mem_limit);
	cns3xxx_write_config(cnspci, PCI_IO_BASE_UPPER16, 2, io_base);
	cns3xxx_write_config(cnspci, PCI_IO_LIMIT_UPPER16, 2, io_limit);

	if (!cnspci->linked)
		return;

	/* Set Device Max_Read_Request_Size to 128 byte */
	pcie_bus_config = PCIE_BUS_PEER2PEER;

	/* Disable PCIe0 Interrupt Mask INTA to INTD */
	__raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(cnspci->port));
}

static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
				      struct pt_regs *regs)
{
	if (fsr & (1 << 10))
		regs->ARM_pc += 4;
	return 0;
}

void __init cns3xxx_pcie_init_late(void)
{
	int i;
	void *private_data;
	struct hw_pci hw_pci = {
	       .nr_controllers = 1,
	       .ops = &cns3xxx_pcie_ops,
	       .setup = cns3xxx_pci_setup,
	       .map_irq = cns3xxx_pcie_map_irq,
	       .private_data = &private_data,
	};

	pcibios_min_io = 0;
	pcibios_min_mem = 0;

	hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
			"imprecise external abort");

	for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
		cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
		cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
		cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
		cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
		private_data = &cns3xxx_pcie[i];
		pci_common_init(&hw_pci);
	}

	pci_assign_unassigned_resources();
}


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2008 Cavium Networks
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/atomic.h>
#include "cns3xxx.h"
#include "pm.h"
#include "core.h"

void cns3xxx_pwr_clk_en(unsigned int block)
{
	u32 reg = __raw_readl(PM_CLK_GATE_REG);

	reg |= (block & PM_CLK_GATE_REG_MASK);
	__raw_writel(reg, PM_CLK_GATE_REG);
}
EXPORT_SYMBOL(cns3xxx_pwr_clk_en);

void cns3xxx_pwr_clk_dis(unsigned int block)
{
	u32 reg = __raw_readl(PM_CLK_GATE_REG);

	reg &= ~(block & PM_CLK_GATE_REG_MASK);
	__raw_writel(reg, PM_CLK_GATE_REG);
}
EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);

void cns3xxx_pwr_power_up(unsigned int block)
{
	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);

	reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);

	/* Wait for 300us for the PLL output clock locked. */
	udelay(300);
};
EXPORT_SYMBOL(cns3xxx_pwr_power_up);

void cns3xxx_pwr_power_down(unsigned int block)
{
	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);

	/* write '1' to power down */
	reg |= (block & CNS3XXX_PWR_PLL_ALL);
	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
};
EXPORT_SYMBOL(cns3xxx_pwr_power_down);

static void cns3xxx_pwr_soft_rst_force(unsigned int block)
{
	u32 reg = __raw_readl(PM_SOFT_RST_REG);

	/*
	 * bit 0, 28, 29 => program low to reset,
	 * the other else program low and then high
	 */
	if (block & 0x30000001) {
		reg &= ~(block & PM_SOFT_RST_REG_MASK);
	} else {
		reg &= ~(block & PM_SOFT_RST_REG_MASK);
		__raw_writel(reg, PM_SOFT_RST_REG);
		reg |= (block & PM_SOFT_RST_REG_MASK);
	}

	__raw_writel(reg, PM_SOFT_RST_REG);
}

void cns3xxx_pwr_soft_rst(unsigned int block)
{
	static unsigned int soft_reset;

	if (soft_reset & block) {
		/* SPI/I2C/GPIO use the same block, reset once. */
		return;
	} else {
		soft_reset |= block;
	}
	cns3xxx_pwr_soft_rst_force(block);
}
EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);

void cns3xxx_restart(enum reboot_mode mode, const char *cmd)
{
	/*
	 * To reset, we hit the on-board reset register
	 * in the system FPGA.
	 */
	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
}

/*
 * cns3xxx_cpu_clock - return CPU/L2 clock
 *  aclk: cpu clock/2
 *  hclk: cpu clock/4
 *  pclk: cpu clock/8
 */
int cns3xxx_cpu_clock(void)
{
	u32 reg = __raw_readl(PM_CLK_CTRL_REG);
	int cpu;
	int cpu_sel;
	int div_sel;

	cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
	div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;

	cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;

	return cpu;
}
EXPORT_SYMBOL(cns3xxx_cpu_clock);

atomic_t usb_pwr_ref = ATOMIC_INIT(0);
EXPORT_SYMBOL(usb_pwr_ref);


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright 2000 Deep Blue Solutions Ltd
 * Copyright 2004 ARM Limited
 * Copyright 2008 Cavium Networks
 */

#ifndef __CNS3XXX_PM_H
#define __CNS3XXX_PM_H

#include <linux/atomic.h>

void cns3xxx_pwr_clk_en(unsigned int block);
void cns3xxx_pwr_clk_dis(unsigned int block);
void cns3xxx_pwr_power_up(unsigned int block);
void cns3xxx_pwr_power_down(unsigned int block);

extern atomic_t usb_pwr_ref;

#endif /* __CNS3XXX_PM_H */


code:
# SPDX-License-Identifier: GPL-2.0

menuconfig ARCH_DAVINCI
	bool "TI DaVinci"
	depends on ARCH_MULTI_V5
	depends on CPU_LITTLE_ENDIAN
	select DAVINCI_TIMER
	select ZONE_DMA
	select PM_GENERIC_DOMAINS if PM
	select PM_GENERIC_DOMAINS_OF if PM && OF
	select REGMAP_MMIO
	select RESET_CONTROLLER
	select PINCTRL_SINGLE

if ARCH_DAVINCI

config ARCH_DAVINCI_DMx
	bool

comment "DaVinci Core Type"

config ARCH_DAVINCI_DM355
	bool "DaVinci 355 based system"
	depends on ATAGS && UNUSED_BOARD_FILES
	select DAVINCI_AINTC
	select ARCH_DAVINCI_DMx

config ARCH_DAVINCI_DA830
	bool "DA830/OMAP-L137/AM17x based system"
	depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT)
	depends on ATAGS
	select ARCH_DAVINCI_DA8XX
	# needed on silicon revs 1.0, 1.1:
	select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE
	select DAVINCI_CP_INTC

config ARCH_DAVINCI_DA850
	bool "DA850/OMAP-L138/AM18x based system"
	depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT)
	depends on ATAGS
	select ARCH_DAVINCI_DA8XX
	select DAVINCI_CP_INTC

config ARCH_DAVINCI_DA8XX
	bool

config ARCH_DAVINCI_DM365
	bool "DaVinci 365 based system"
	depends on ATAGS && UNUSED_BOARD_FILES
	select DAVINCI_AINTC
	select ARCH_DAVINCI_DMx

comment "DaVinci Board Type"

config MACH_DA8XX_DT
	bool "Support DA8XX platforms using device tree"
	default y
	depends on ARCH_DAVINCI_DA850
	select PINCTRL
	help
	  Say y here to include support for TI DaVinci DA850 based using
	  Flattened Device Tree. More information at Documentation/devicetree

config MACH_DAVINCI_DM355_EVM
	bool "TI DM355 EVM"
	default ARCH_DAVINCI_DM355
	depends on ARCH_DAVINCI_DM355
	help
	  Configure this option to specify the whether the board used
	  for development is a DM355 EVM

config MACH_DM355_LEOPARD
	bool "DM355 Leopard board"
	depends on ARCH_DAVINCI_DM355
	help
	  Configure this option to specify the whether the board used
	  for development is a DM355 Leopard board.

config MACH_DAVINCI_DM365_EVM
	bool "TI DM365 EVM"
	default ARCH_DAVINCI_DM365
	depends on ARCH_DAVINCI_DM365
	help
	  Configure this option to specify whether the board used
	  for development is a DM365 EVM

config MACH_DAVINCI_DA830_EVM
	bool "TI DA830/OMAP-L137/AM17x Reference Platform"
	default ARCH_DAVINCI_DA830
	depends on ATAGS && UNUSED_BOARD_FILES
	depends on ARCH_DAVINCI_DA830
	select GPIO_PCF857X if I2C
	help
	  Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module.

choice
	prompt "Select DA830/OMAP-L137/AM17x UI board peripheral"
	depends on MACH_DAVINCI_DA830_EVM
	help
	  The presence of UI card on the DA830/OMAP-L137/AM17x EVM is
	  detected automatically based on successful probe of the I2C
	  based GPIO expander on that board. This option selected in this
	  menu has an effect only in case of a successful UI card detection.

config DA830_UI_LCD
	bool "LCD"
	help
	  Say Y here to use the LCD as a framebuffer or simple character
	  display.

config DA830_UI_NAND
	bool "NAND flash"
	help
	  Say Y here to use the NAND flash. Do not forget to setup
	  the switch correctly.
endchoice

config MACH_DAVINCI_DA850_EVM
	bool "TI DA850/OMAP-L138/AM18x Reference Platform"
	depends on ATAGS && UNUSED_BOARD_FILES
	default ARCH_DAVINCI_DA850
	depends on ARCH_DAVINCI_DA850
	help
	  Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module.

choice
	prompt "Select peripherals connected to expander on UI board"
	depends on MACH_DAVINCI_DA850_EVM
	help
	  The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x
	  EVM is detected automatically based on successful probe of the I2C
	  based GPIO expander on that card. This option selected in this
	  menu has an effect only in case of a successful UI card detection.

config DA850_UI_NONE
	bool "No peripheral is enabled"
	help
	  Say Y if you do not want to enable any of the peripherals connected
	  to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card

config DA850_UI_RMII
	bool "RMII Ethernet PHY"
	help
	  Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x
	  EVM. This PHY is found on the UI daughter card that is supplied with
	  the EVM.
	  NOTE: Please take care while choosing this option, MII PHY will
	  not be functional if RMII mode is selected.

config DA850_UI_SD_VIDEO_PORT
	bool "Video Port Interface"
	help
	  Say Y if you want to use Video Port Interface (VPIF) on the
	  DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the
	  UI daughter card that is supplied with the EVM.

endchoice

config MACH_MITYOMAPL138
	bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
	depends on ARCH_DAVINCI_DA850
	depends on ATAGS && UNUSED_BOARD_FILES
	help
	  Say Y here to select the Critical Link MityDSP-L138/MityARM-1808
	  System on Module.  Information on this SoM may be found at
	  https://www.mitydsp.com

config MACH_OMAPL138_HAWKBOARD
	bool "TI AM1808 / OMAPL-138 Hawkboard platform"
	depends on ARCH_DAVINCI_DA850
	depends on ATAGS && UNUSED_BOARD_FILES
	help
	  Say Y here to select the TI AM1808 / OMAPL-138 Hawkboard platform .

config DAVINCI_MUX
	bool "DAVINCI multiplexing support"
	depends on ARCH_DAVINCI
	default y
	help
	  Pin multiplexing support for DAVINCI boards. If your bootloader
	  sets the multiplexing correctly, say N. Otherwise, or if unsure,
	  say Y.

config DAVINCI_MUX_DEBUG
	bool "Multiplexing debug output"
	depends on DAVINCI_MUX
	help
	  Makes the multiplexing functions print out a lot of debug info.
	  This is useful if you want to find out the correct values of the
	  multiplexing registers.

config DAVINCI_MUX_WARNINGS
	bool "Warn about pins the bootloader didn't set up"
	depends on DAVINCI_MUX
	help
	  Choose Y here to warn whenever driver initialization logic needs
	  to change the pin multiplexing setup. When there are no warnings
	  printed, it's safe to deselect DAVINCI_MUX for your product.

endif

path: arch/arm/mach-davinci/Kconfig


code:
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the linux kernel.
#
#
#
# Common objects
obj-y 					:= serial.o usb.o common.o sram.o

obj-$(CONFIG_DAVINCI_MUX)		+= mux.o

# Chip specific
obj-$(CONFIG_ARCH_DAVINCI_DM355)        += dm355.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= dm365.o devices.o
obj-$(CONFIG_ARCH_DAVINCI_DA830)	+= da830.o devices-da8xx.o usb-da8xx.o
obj-$(CONFIG_ARCH_DAVINCI_DA850)	+= da850.o devices-da8xx.o usb-da8xx.o

# Board specific
obj-$(CONFIG_MACH_DA8XX_DT)		+= da8xx-dt.o pdata-quirks.o
obj-$(CONFIG_MACH_DAVINCI_DM355_EVM)	+= board-dm355-evm.o
obj-$(CONFIG_MACH_DM355_LEOPARD)	+= board-dm355-leopard.o
obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)	+= board-dm365-evm.o
obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)	+= board-da830-evm.o
obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= board-da850-evm.o
obj-$(CONFIG_MACH_MITYOMAPL138)		+= board-mityomapl138.o
obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD)	+= board-omapl138-hawk.o

# Power Management
obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
obj-$(CONFIG_HAVE_CLK)			+= pm_domain.o
ifeq ($(CONFIG_SUSPEND),y)
obj-$(CONFIG_ARCH_DAVINCI_DA850)	+= pm.o sleep.o
endif

path: arch/arm/mach-davinci/Makefile


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * TI DaVinci Audio definitions
 */
#ifndef __ASM_ARCH_DAVINCI_ASP_H
#define __ASM_ARCH_DAVINCI_ASP_H

/* Bases of dm644x and dm355 register banks */
#define DAVINCI_ASP0_BASE	0x01E02000
#define DAVINCI_ASP1_BASE	0x01E04000

/* Bases of dm365 register banks */
#define DAVINCI_DM365_ASP0_BASE	0x01D02000

/* Bases of dm646x register banks */
#define DAVINCI_DM646X_MCASP0_REG_BASE		0x01D01000
#define DAVINCI_DM646X_MCASP1_REG_BASE		0x01D01800

/* Bases of da850/da830 McASP0  register banks */
#define DAVINCI_DA8XX_MCASP0_REG_BASE	0x01D00000

/* Bases of da830 McASP1 register banks */
#define DAVINCI_DA830_MCASP1_REG_BASE	0x01D04000

/* Bases of da830 McASP2 register banks */
#define DAVINCI_DA830_MCASP2_REG_BASE	0x01D08000

/* EDMA channels of dm644x and dm355 */
#define DAVINCI_DMA_ASP0_TX	2
#define DAVINCI_DMA_ASP0_RX	3
#define DAVINCI_DMA_ASP1_TX	8
#define DAVINCI_DMA_ASP1_RX	9

/* EDMA channels of dm646x */
#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0	6
#define DAVINCI_DM646X_DMA_MCASP0_AREVT0	9
#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1	12

/* EDMA channels of da850/da830 McASP0 */
#define DAVINCI_DA8XX_DMA_MCASP0_AREVT	0
#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT	1

/* EDMA channels of da830 McASP1 */
#define DAVINCI_DA830_DMA_MCASP1_AREVT	2
#define DAVINCI_DA830_DMA_MCASP1_AXEVT	3

/* EDMA channels of da830 McASP2 */
#define DAVINCI_DA830_DMA_MCASP2_AREVT	4
#define DAVINCI_DA830_DMA_MCASP2_AXEVT	5

/* Interrupts */
#define DAVINCI_ASP0_RX_INT	DAVINCI_INTC_IRQ(IRQ_MBRINT)
#define DAVINCI_ASP0_TX_INT	DAVINCI_INTC_IRQ(IRQ_MBXINT)
#define DAVINCI_ASP1_RX_INT	DAVINCI_INTC_IRQ(IRQ_MBRINT)
#define DAVINCI_ASP1_TX_INT	DAVINCI_INTC_IRQ(IRQ_MBXINT)

#endif /* __ASM_ARCH_DAVINCI_ASP_H */


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * TI DA830/OMAP L137 EVM board
 *
 * Author: Mark A. Greer <mgreer@mvista.com>
 * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c
 *
 * 2007, 2009 (c) MontaVista Software, Inc.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/platform_data/pcf857x.h>
#include <linux/property.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_data/mtd-davinci.h>
#include <linux/platform_data/mtd-davinci-aemif.h>
#include <linux/platform_data/spi-davinci.h>
#include <linux/platform_data/usb-davinci.h>
#include <linux/platform_data/ti-aemif.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/nvmem-provider.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>

#include "common.h"
#include "mux.h"
#include "da8xx.h"
#include "irqs.h"

#define DA830_EVM_PHY_ID		""
/*
 * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
 */
#define ON_BD_USB_DRV	GPIO_TO_PIN(1, 15)
#define ON_BD_USB_OVC	GPIO_TO_PIN(2, 4)

static const short da830_evm_usb11_pins[] = {
	DA830_GPIO1_15, DA830_GPIO2_4,
	-1
};

static struct regulator_consumer_supply da830_evm_usb_supplies[] = {
	REGULATOR_SUPPLY("vbus", NULL),
};

static struct regulator_init_data da830_evm_usb_vbus_data = {
	.consumer_supplies	= da830_evm_usb_supplies,
	.num_consumer_supplies	= ARRAY_SIZE(da830_evm_usb_supplies),
	.constraints    = {
		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
	},
};

static struct fixed_voltage_config da830_evm_usb_vbus = {
	.supply_name		= "vbus",
	.microvolts		= 33000000,
	.init_data		= &da830_evm_usb_vbus_data,
};

static struct platform_device da830_evm_usb_vbus_device = {
	.name		= "reg-fixed-voltage",
	.id		= 0,
	.dev		= {
		.platform_data = &da830_evm_usb_vbus,
	},
};

static struct gpiod_lookup_table da830_evm_usb_oc_gpio_lookup = {
	.dev_id		= "ohci-da8xx",
	.table = {
		GPIO_LOOKUP("davinci_gpio", ON_BD_USB_OVC, "oc", 0),
		{ }
	},
};

static struct gpiod_lookup_table da830_evm_usb_vbus_gpio_lookup = {
	.dev_id		= "reg-fixed-voltage.0",
	.table = {
		GPIO_LOOKUP("davinci_gpio", ON_BD_USB_DRV, NULL, 0),
		{ }
	},
};

static struct gpiod_lookup_table *da830_evm_usb_gpio_lookups[] = {
	&da830_evm_usb_oc_gpio_lookup,
	&da830_evm_usb_vbus_gpio_lookup,
};

static struct da8xx_ohci_root_hub da830_evm_usb11_pdata = {
	/* TPS2065 switch @ 5V */
	.potpgt		= (3 + 1) / 2,	/* 3 ms max */
};

static __init void da830_evm_usb_init(void)
{
	int ret;

	ret = da8xx_register_usb_phy_clocks();
	if (ret)
		pr_warn("%s: USB PHY CLK registration failed: %d\n",
			__func__, ret);

	gpiod_add_lookup_tables(da830_evm_usb_gpio_lookups,
				ARRAY_SIZE(da830_evm_usb_gpio_lookups));

	ret = da8xx_register_usb_phy();
	if (ret)
		pr_warn("%s: USB PHY registration failed: %d\n",
			__func__, ret);

	ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
	if (ret)
		pr_warn("%s: USB 2.0 PinMux setup failed: %d\n", __func__, ret);
	else {
		/*
		 * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A),
		 * with the power on to power good time of 3 ms.
		 */
		ret = da8xx_register_usb20(1000, 3);
		if (ret)
			pr_warn("%s: USB 2.0 registration failed: %d\n",
				__func__, ret);
	}

	ret = davinci_cfg_reg_list(da830_evm_usb11_pins);
	if (ret) {
		pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret);
		return;
	}

	ret = platform_device_register(&da830_evm_usb_vbus_device);
	if (ret) {
		pr_warn("%s: Unable to register the vbus supply\n", __func__);
		return;
	}

	ret = da8xx_register_usb11(&da830_evm_usb11_pdata);
	if (ret)
		pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret);
}

static const short da830_evm_mcasp1_pins[] = {
	DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1,
	DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5,
	DA830_ACLKR1, DA830_AXR1_6, DA830_AXR1_7, DA830_AXR1_8, DA830_AXR1_10,
	DA830_AXR1_11,
	-1
};

static u8 da830_iis_serializer_direction[] = {
	RX_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
	INACTIVE_MODE,	TX_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
};

static struct snd_platform_data da830_evm_snd_data = {
	.tx_dma_offset  = 0x2000,
	.rx_dma_offset  = 0x2000,
	.op_mode        = DAVINCI_MCASP_IIS_MODE,
	.num_serializer = ARRAY_SIZE(da830_iis_serializer_direction),
	.tdm_slots      = 2,
	.serial_dir     = da830_iis_serializer_direction,
	.asp_chan_q     = EVENTQ_0,
	.version	= MCASP_VERSION_2,
	.txnumevt	= 1,
	.rxnumevt	= 1,
};

/*
 * GPIO2[1] is used as MMC_SD_WP and GPIO2[2] as MMC_SD_INS.
 */
static const short da830_evm_mmc_sd_pins[] = {
	DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
	DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
	DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
	DA830_MMCSD_CMD,   DA830_GPIO2_1,     DA830_GPIO2_2,
	-1
};

#define DA830_MMCSD_WP_PIN		GPIO_TO_PIN(2, 1)
#define DA830_MMCSD_CD_PIN		GPIO_TO_PIN(2, 2)

static struct gpiod_lookup_table mmc_gpios_table = {
	.dev_id = "da830-mmc.0",
	.table = {
		/* gpio chip 1 contains gpio range 32-63 */
		GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_CD_PIN, "cd",
			    GPIO_ACTIVE_LOW),
		GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_WP_PIN, "wp",
			    GPIO_ACTIVE_LOW),
		{ }
	},
};

static struct davinci_mmc_config da830_evm_mmc_config = {
	.wires			= 8,
	.max_freq		= 50000000,
	.caps			= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
};

static inline void da830_evm_init_mmc(void)
{
	int ret;

	ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins);
	if (ret) {
		pr_warn("%s: mmc/sd mux setup failed: %d\n", __func__, ret);
		return;
	}

	gpiod_add_lookup_table(&mmc_gpios_table);

	ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
	if (ret) {
		pr_warn("%s: mmc/sd registration failed: %d\n", __func__, ret);
		gpiod_remove_lookup_table(&mmc_gpios_table);
	}
}

#define HAS_MMC		IS_ENABLED(CONFIG_MMC_DAVINCI)

#ifdef CONFIG_DA830_UI_NAND
static struct mtd_partition da830_evm_nand_partitions[] = {
	/* bootloader (U-Boot, etc) in first sector */
	[0] = {
		.name		= "bootloader",
		.offset		= 0,
		.size		= SZ_128K,
		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
	},
	/* bootloader params in the next sector */
	[1] = {
		.name		= "params",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_128K,
		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
	},
	/* kernel */
	[2] = {
		.name		= "kernel",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_2M,
		.mask_flags	= 0,
	},
	/* file system */
	[3] = {
		.name		= "filesystem",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0,
	}
};

/* flash bbt descriptors */
static uint8_t da830_evm_nand_bbt_pattern[] = { 'B', 'b', 't', '0' };
static uint8_t da830_evm_nand_mirror_pattern[] = { '1', 't', 'b', 'B' };

static struct nand_bbt_descr da830_evm_nand_bbt_main_descr = {
	.options	= NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
			  NAND_BBT_WRITE | NAND_BBT_2BIT |
			  NAND_BBT_VERSION | NAND_BBT_PERCHIP,
	.offs		= 2,
	.len		= 4,
	.veroffs	= 16,
	.maxblocks	= 4,
	.pattern	= da830_evm_nand_bbt_pattern
};

static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = {
	.options	= NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
			  NAND_BBT_WRITE | NAND_BBT_2BIT |
			  NAND_BBT_VERSION | NAND_BBT_PERCHIP,
	.offs		= 2,
	.len		= 4,
	.veroffs	= 16,
	.maxblocks	= 4,
	.pattern	= da830_evm_nand_mirror_pattern
};

static struct davinci_aemif_timing da830_evm_nandflash_timing = {
	.wsetup         = 24,
	.wstrobe        = 21,
	.whold          = 14,
	.rsetup         = 19,
	.rstrobe        = 50,
	.rhold          = 0,
	.ta             = 20,
};

static struct davinci_nand_pdata da830_evm_nand_pdata = {
	.core_chipsel	= 1,
	.parts		= da830_evm_nand_partitions,
	.nr_parts	= ARRAY_SIZE(da830_evm_nand_partitions),
	.engine_type	= NAND_ECC_ENGINE_TYPE_ON_HOST,
	.ecc_bits	= 4,
	.bbt_options	= NAND_BBT_USE_FLASH,
	.bbt_td		= &da830_evm_nand_bbt_main_descr,
	.bbt_md		= &da830_evm_nand_bbt_mirror_descr,
	.timing         = &da830_evm_nandflash_timing,
};

static struct resource da830_evm_nand_resources[] = {
	[0] = {		/* First memory resource is NAND I/O window */
		.start	= DA8XX_AEMIF_CS3_BASE,
		.end	= DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {		/* Second memory resource is AEMIF control registers */
		.start	= DA8XX_AEMIF_CTL_BASE,
		.end	= DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device da830_evm_aemif_devices[] = {
	{
		.name		= "davinci_nand",
		.id		= 1,
		.dev		= {
			.platform_data	= &da830_evm_nand_pdata,
		},
		.num_resources	= ARRAY_SIZE(da830_evm_nand_resources),
		.resource	= da830_evm_nand_resources,
	},
};

static struct resource da830_evm_aemif_resource[] = {
	{
		.start	= DA8XX_AEMIF_CTL_BASE,
		.end	= DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct aemif_abus_data da830_evm_aemif_abus_data[] = {
	{
		.cs	= 3,
	},
};

static struct aemif_platform_data da830_evm_aemif_pdata = {
	.abus_data		= da830_evm_aemif_abus_data,
	.num_abus_data		= ARRAY_SIZE(da830_evm_aemif_abus_data),
	.sub_devices		= da830_evm_aemif_devices,
	.num_sub_devices	= ARRAY_SIZE(da830_evm_aemif_devices),
	.cs_offset		= 2,
};

static struct platform_device da830_evm_aemif_device = {
	.name		= "ti-aemif",
	.id		= -1,
	.dev = {
		.platform_data = &da830_evm_aemif_pdata,
	},
	.resource	= da830_evm_aemif_resource,
	.num_resources	= ARRAY_SIZE(da830_evm_aemif_resource),
};

/*
 * UI board NAND/NOR flashes only use 8-bit data bus.
 */
static const short da830_evm_emif25_pins[] = {
	DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
	DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
	DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
	DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
	DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
	DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE,
	DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0,
	-1
};

static inline void da830_evm_init_nand(int mux_mode)
{
	int ret;

	if (HAS_MMC) {
		pr_warn("WARNING: both MMC/SD and NAND are enabled, but they share AEMIF pins\n"
			"\tDisable MMC/SD for NAND support\n");
		return;
	}

	ret = davinci_cfg_reg_list(da830_evm_emif25_pins);
	if (ret)
		pr_warn("%s: emif25 mux setup failed: %d\n", __func__, ret);

	ret = platform_device_register(&da830_evm_aemif_device);
	if (ret)
		pr_warn("%s: AEMIF device not registered\n", __func__);

	gpio_direction_output(mux_mode, 1);
}
#else
static inline void da830_evm_init_nand(int mux_mode) { }
#endif

#ifdef CONFIG_DA830_UI_LCD
static inline void da830_evm_init_lcdc(int mux_mode)
{
	int ret;

	ret = davinci_cfg_reg_list(da830_lcdcntl_pins);
	if (ret)
		pr_warn("%s: lcdcntl mux setup failed: %d\n", __func__, ret);

	ret = da8xx_register_lcdc(&sharp_lcd035q3dg01_pdata);
	if (ret)
		pr_warn("%s: lcd setup failed: %d\n", __func__, ret);

	gpio_direction_output(mux_mode, 0);
}
#else
static inline void da830_evm_init_lcdc(int mux_mode) { }
#endif

static struct nvmem_cell_info da830_evm_nvmem_cells[] = {
	{
		.name		= "macaddr",
		.offset		= 0x7f00,
		.bytes		= ETH_ALEN,
	}
};

static struct nvmem_cell_table da830_evm_nvmem_cell_table = {
	.nvmem_name	= "1-00500",
	.cells		= da830_evm_nvmem_cells,
	.ncells		= ARRAY_SIZE(da830_evm_nvmem_cells),
};

static struct nvmem_cell_lookup da830_evm_nvmem_cell_lookup = {
	.nvmem_name	= "1-00500",
	.cell_name	= "macaddr",
	.dev_id		= "davinci_emac.1",
	.con_id		= "mac-address",
};

static const struct property_entry da830_evm_i2c_eeprom_properties[] = {
	PROPERTY_ENTRY_U32("pagesize", 64),
	{ }
};

static const struct software_node da830_evm_i2c_eeprom_node = {
	.properties = da830_evm_i2c_eeprom_properties,
};

static int __init da830_evm_ui_expander_setup(struct i2c_client *client,
		int gpio, unsigned ngpio, void *context)
{
	gpio_request(gpio + 6, "UI MUX_MODE");

	/* Drive mux mode low to match the default without UI card */
	gpio_direction_output(gpio + 6, 0);

	da830_evm_init_lcdc(gpio + 6);

	da830_evm_init_nand(gpio + 6);

	return 0;
}

static void da830_evm_ui_expander_teardown(struct i2c_client *client, int gpio,
		unsigned ngpio, void *context)
{
	gpio_free(gpio + 6);
}

static struct pcf857x_platform_data __initdata da830_evm_ui_expander_info = {
	.gpio_base	= DAVINCI_N_GPIO,
	.setup		= da830_evm_ui_expander_setup,
	.teardown	= da830_evm_ui_expander_teardown,
};

static struct i2c_board_info __initdata da830_evm_i2c_devices[] = {
	{
		I2C_BOARD_INFO("24c256", 0x50),
		.swnode = &da830_evm_i2c_eeprom_node,
	},
	{
		I2C_BOARD_INFO("tlv320aic3x", 0x18),
	},
	{
		I2C_BOARD_INFO("pcf8574", 0x3f),
		.platform_data	= &da830_evm_ui_expander_info,
	},
};

static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = {
	.bus_freq	= 100,	/* kHz */
	.bus_delay	= 0,	/* usec */
};

/*
 * The following EDMA channels/slots are not being used by drivers (for
 * example: Timer, GPIO, UART events etc) on da830/omap-l137 EVM, hence
 * they are being reserved for codecs on the DSP side.
 */
static const s16 da830_dma_rsv_chans[][2] = {
	/* (offset, number) */
	{ 8,  2},
	{12,  2},
	{24,  4},
	{30,  2},
	{-1, -1}
};

static const s16 da830_dma_rsv_slots[][2] = {
	/* (offset, number) */
	{ 8,  2},
	{12,  2},
	{24,  4},
	{30, 26},
	{-1, -1}
};

static struct edma_rsv_info da830_edma_rsv[] = {
	{
		.rsv_chans	= da830_dma_rsv_chans,
		.rsv_slots	= da830_dma_rsv_slots,
	},
};

static struct mtd_partition da830evm_spiflash_part[] = {
	[0] = {
		.name = "DSP-UBL",
		.offset = 0,
		.size = SZ_8K,
		.mask_flags = MTD_WRITEABLE,
	},
	[1] = {
		.name = "ARM-UBL",
		.offset = MTDPART_OFS_APPEND,
		.size = SZ_16K + SZ_8K,
		.mask_flags = MTD_WRITEABLE,
	},
	[2] = {
		.name = "U-Boot",
		.offset = MTDPART_OFS_APPEND,
		.size = SZ_256K - SZ_32K,
		.mask_flags = MTD_WRITEABLE,
	},
	[3] = {
		.name = "U-Boot-Environment",
		.offset = MTDPART_OFS_APPEND,
		.size = SZ_16K,
		.mask_flags = 0,
	},
	[4] = {
		.name = "Kernel",
		.offset = MTDPART_OFS_APPEND,
		.size = MTDPART_SIZ_FULL,
		.mask_flags = 0,
	},
};

static struct flash_platform_data da830evm_spiflash_data = {
	.name		= "m25p80",
	.parts		= da830evm_spiflash_part,
	.nr_parts	= ARRAY_SIZE(da830evm_spiflash_part),
	.type		= "w25x32",
};

static struct davinci_spi_config da830evm_spiflash_cfg = {
	.io_type	= SPI_IO_TYPE_DMA,
	.c2tdelay	= 8,
	.t2cdelay	= 8,
};

static struct spi_board_info da830evm_spi_info[] = {
	{
		.modalias		= "m25p80",
		.platform_data		= &da830evm_spiflash_data,
		.controller_data	= &da830evm_spiflash_cfg,
		.mode			= SPI_MODE_0,
		.max_speed_hz		= 30000000,
		.bus_num		= 0,
		.chip_select		= 0,
	},
};

static __init void da830_evm_init(void)
{
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	int ret;

	da830_register_clocks();

	ret = da830_register_gpio();
	if (ret)
		pr_warn("%s: GPIO init failed: %d\n", __func__, ret);

	ret = da830_register_edma(da830_edma_rsv);
	if (ret)
		pr_warn("%s: edma registration failed: %d\n", __func__, ret);

	ret = davinci_cfg_reg_list(da830_i2c0_pins);
	if (ret)
		pr_warn("%s: i2c0 mux setup failed: %d\n", __func__, ret);

	ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata);
	if (ret)
		pr_warn("%s: i2c0 registration failed: %d\n", __func__, ret);

	da830_evm_usb_init();

	soc_info->emac_pdata->rmii_en = 1;
	soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID;

	ret = davinci_cfg_reg_list(da830_cpgmac_pins);
	if (ret)
		pr_warn("%s: cpgmac mux setup failed: %d\n", __func__, ret);

	ret = da8xx_register_emac();
	if (ret)
		pr_warn("%s: emac registration failed: %d\n", __func__, ret);

	ret = da8xx_register_watchdog();
	if (ret)
		pr_warn("%s: watchdog registration failed: %d\n",
			__func__, ret);

	davinci_serial_init(da8xx_serial_device);

	nvmem_add_cell_table(&da830_evm_nvmem_cell_table);
	nvmem_add_cell_lookups(&da830_evm_nvmem_cell_lookup, 1);

	i2c_register_board_info(1, da830_evm_i2c_devices,
			ARRAY_SIZE(da830_evm_i2c_devices));

	ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins);
	if (ret)
		pr_warn("%s: mcasp1 mux setup failed: %d\n", __func__, ret);

	da8xx_register_mcasp(1, &da830_evm_snd_data);

	da830_evm_init_mmc();

	ret = da8xx_register_rtc();
	if (ret)
		pr_warn("%s: rtc setup failed: %d\n", __func__, ret);

	ret = spi_register_board_info(da830evm_spi_info,
				      ARRAY_SIZE(da830evm_spi_info));
	if (ret)
		pr_warn("%s: spi info registration failed: %d\n",
			__func__, ret);

	ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info));
	if (ret)
		pr_warn("%s: spi 0 registration failed: %d\n", __func__, ret);

	regulator_has_full_constraints();
}

#ifdef CONFIG_SERIAL_8250_CONSOLE
static int __init da830_evm_console_init(void)
{
	if (!machine_is_davinci_da830_evm())
		return 0;

	return add_preferred_console("ttyS", 2, "115200");
}
console_initcall(da830_evm_console_init);
#endif

static void __init da830_evm_map_io(void)
{
	da830_init();
}

MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
	.atag_offset	= 0x100,
	.map_io		= da830_evm_map_io,
	.init_irq	= da830_init_irq,
	.init_time	= da830_init_time,
	.init_machine	= da830_evm_init,
	.init_late	= davinci_init_late,
	.dma_zone_size	= SZ_128M,
MACHINE_END