code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/cdns,usb3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence USBSS-DRD controller bindings

maintainers:
  - Pawel Laszczak <pawell@cadence.com>

properties:
  compatible:
    const: cdns,usb3

  reg:
    items:
      - description: OTG controller registers
      - description: XHCI Host controller registers
      - description: DEVICE controller registers

  reg-names:
    items:
      - const: otg
      - const: xhci
      - const: dev

  interrupts:
    minItems: 3
    items:
      - description: XHCI host controller interrupt
      - description: Device controller interrupt
      - description: OTG/DRD controller interrupt
      - description: interrupt used to wake up core, e.g when usbcmd.rs is
                     cleared by xhci core, this interrupt is optional

  interrupt-names:
    minItems: 3
    items:
      - const: host
      - const: peripheral
      - const: otg
      - const: wakeup

  dr_mode:
    enum: [host, otg, peripheral]

  maximum-speed:
    enum: [super-speed, high-speed, full-speed]

  phys:
    minItems: 1
    maxItems: 2

  phy-names:
    minItems: 1
    maxItems: 2
    items:
      anyOf:
        - const: cdns3,usb2-phy
        - const: cdns3,usb3-phy

  cdns,on-chip-buff-size:
    description:
      size of memory intended as internal memory for endpoints
      buffers expressed in KB
    $ref: /schemas/types.yaml#/definitions/uint32

  cdns,phyrst-a-enable:
    description: Enable resetting of PHY if Rx fail is detected
    type: boolean

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        usb@6000000 {
            compatible = "cdns,usb3";
            reg = <0x00 0x6000000 0x00 0x10000>,
                  <0x00 0x6010000 0x00 0x10000>,
                  <0x00 0x6020000 0x00 0x10000>;
            reg-names = "otg", "xhci", "dev";
            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "host", "peripheral", "otg";
            maximum-speed = "super-speed";
            dr_mode = "otg";
        };
    };


code:
* USB2 ChipIdea USB controller for ci13xxx

Required properties:
- compatible: should be one of:
	"fsl,imx23-usb"
	"fsl,imx27-usb"
	"fsl,imx28-usb"
	"fsl,imx6q-usb"
	"fsl,imx6sl-usb"
	"fsl,imx6sx-usb"
	"fsl,imx6ul-usb"
	"fsl,imx7d-usb"
	"fsl,imx7ulp-usb"
	"lsi,zevio-usb"
	"qcom,ci-hdrc"
	"chipidea,usb2"
	"xlnx,zynq-usb-2.20a"
	"nvidia,tegra20-udc"
	"nvidia,tegra30-udc"
	"nvidia,tegra114-udc"
	"nvidia,tegra124-udc"
- reg: base address and length of the registers
- interrupts: interrupt for the USB controller

Recommended properies:
- phy_type: the type of the phy connected to the core. Should be one
  of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
  property the PORTSC register won't be touched.
- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"

Deprecated properties:
- usb-phy:      phandle for the PHY device. Use "phys" instead.
- fsl,usbphy: phandle of usb phy that connects to the port. Use "phys" instead.

Optional properties:
- clocks: reference to the USB clock
- phys: reference to the USB PHY
- phy-names: should be "usb-phy"
- vbus-supply: reference to the VBUS regulator
- maximum-speed: limit the maximum connection speed to "full-speed".
- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
- itc-setting: interrupt threshold control register control, the setting
  should be aligned with ITC bits at register USBCMD.
- ahb-burst-config: it is vendor dependent, the required value should be
  aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This
  property is used to change AHB burst configuration, check the chipidea
  spec for meaning of each value. If this property is not existed, it
  will use the reset value.
- tx-burst-size-dword: it is vendor dependent, the tx burst size in dword
  (4 bytes), This register represents the maximum length of a the burst
  in 32-bit words while moving data from system memory to the USB
  bus, the value of this property will only take effect if property
  "ahb-burst-config" is set to 0, if this property is missing the reset
  default of the hardware implementation will be used.
- rx-burst-size-dword: it is vendor dependent, the rx burst size in dword
  (4 bytes), This register represents the maximum length of a the burst
  in 32-bit words while moving data from the USB bus to system memory,
  the value of this property will only take effect if property
  "ahb-burst-config" is set to 0, if this property is missing the reset
  default of the hardware implementation will be used.
- extcon: phandles to external connector devices. First phandle should point to
  external connector, which provide "USB" cable events, the second should point
  to external connector device, which provide "USB-HOST" cable events. If one
  of the external connector devices is not required, empty <0> phandle should
  be specified.
- phy-clkgate-delay-us: the delay time (us) between putting the PHY into
  low power mode and gating the PHY clock.
- non-zero-ttctrl-ttha: after setting this property, the value of register
  ttctrl.ttha will be 0x7f; if not, the value will be 0x0, this is the default
  value. It needs to be very carefully for setting this property, it is
  recommended that consult with your IC engineer before setting this value.
  On the most of chipidea platforms, the "usage_tt" flag at RTL is 0, so this
  property only affects siTD.
  If this property is not set, the max packet size is 1023 bytes, and if
  the total of packet size for pervious transactions are more than 256 bytes,
  it can't accept any transactions within this frame. The use case is single
  transaction, but higher frame rate.
  If this property is set, the max packet size is 188 bytes, it can handle
  more transactions than above case, it can accept transactions until it
  considers the left room size within frame is less than 188 bytes, software
  needs to make sure it does not send more than 90%
  maximum_periodic_data_per_frame. The use case is multiple transactions, but
  less frame rate.
- mux-controls: The mux control for toggling host/device output of this
  controller. It's expected that a mux state of 0 indicates device mode and a
  mux state of 1 indicates host mode.
- mux-control-names: Shall be "usb_switch" if mux-controls is specified.
- pinctrl-names: Names for optional pin modes in "default", "host", "device".
  In case of HSIC-mode, "idle" and "active" pin modes are mandatory. In this
  case, the "idle" state needs to pull down the data and strobe pin
  and the "active" state needs to pull up the strobe pin.
- pinctrl-n: alternate pin modes

i.mx specific properties
- fsl,usbmisc: phandler of non-core register device, with one
  argument that indicate usb controller index
- disable-over-current: disable over current detect
- over-current-active-low: over current signal polarity is active low.
- over-current-active-high: over current signal polarity is active high.
  It's recommended to specify the over current polarity.
- power-active-high: power signal polarity is active high
- external-vbus-divider: enables off-chip resistor divider for Vbus
- samsung,picophy-pre-emp-curr-control: HS Transmitter Pre-Emphasis Current
  Control. This signal controls the amount of current sourced to the
  USB_OTG*_DP and USB_OTG*_DN pins after a J-to-K or K-to-J transition.
  The range is from 0x0 to 0x3, the default value is 0x1.
  Details can refer to TXPREEMPAMPTUNE0 bits of USBNC_n_PHY_CFG1.
- samsung,picophy-dc-vol-level-adjust: HS DC Voltage Level Adjustment.
  Adjust the high-speed transmitter DC level voltage.
  The range is from 0x0 to 0xf, the default value is 0x3.
  Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1.

Example:

	usb@f7ed0000 {
		compatible = "chipidea,usb2";
		reg = <0xf7ed0000 0x10000>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&chip CLKID_USB0>;
		phys = <&usb_phy0>;
		phy-names = "usb-phy";
		vbus-supply = <&reg_usb0_vbus>;
		itc-setting = <0x4>; /* 4 micro-frames */
		 /* Incremental burst of unspecified length */
		ahb-burst-config = <0x0>;
		tx-burst-size-dword = <0x10>; /* 64 bytes */
		rx-burst-size-dword = <0x10>;
		extcon = <0>, <&usb_id>;
		phy-clkgate-delay-us = <400>;
		mux-controls = <&usb_switch>;
		mux-control-names = "usb_switch";
	};

Example for HSIC:

	usb@2184400 {
		compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
		reg = <0x02184400 0x200>;
		interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX6QDL_CLK_USBOH3>;
		fsl,usbphy = <&usbphynop1>;
		fsl,usbmisc = <&usbmisc 2>;
		phy_type = "hsic";
		dr_mode = "host";
		ahb-burst-config = <0x0>;
		tx-burst-size-dword = <0x10>;
		rx-burst-size-dword = <0x10>;
		pinctrl-names = "idle", "active";
		pinctrl-0 = <&pinctrl_usbh2_idle>;
		pinctrl-1 = <&pinctrl_usbh2_active>;
		#address-cells = <1>;
		#size-cells = <0>;

		usbnet: ethernet@1 {
			compatible = "usb424,9730";
			reg = <1>;
		};
	};

repo_name: angery/linux


code:
TI DA8xx MUSB
~~~~~~~~~~~~~
For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms.

Required properties:
~~~~~~~~~~~~~~~~~~~~
 - compatible : Should be set to "ti,da830-musb".

 - reg: Offset and length of the USB controller register set.

 - interrupts: The USB interrupt number.

 - interrupt-names: Should be set to "mc".

 - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg".

 - phys: Phandle for the PHY device

 - phy-names: Should be "usb-phy"

 - dmas: specifies the dma channels

 - dma-names: specifies the names of the channels. Use "rxN" for receive
   and "txN" for transmit endpoints. N specifies the endpoint number.

Optional properties:
~~~~~~~~~~~~~~~~~~~~
 - vbus-supply: Phandle to a regulator providing the USB bus power.

DMA
~~~
- compatible: ti,da830-cppi41
- reg: offset and length of the following register spaces: CPPI DMA Controller,
  CPPI DMA Scheduler, Queue Manager
- reg-names: "controller", "scheduler", "queuemgr"
- #dma-cells: should be set to 2. The first number represents the
  channel number (0 … 3 for endpoints 1 … 4).
  The second number is 0 for RX and 1 for TX transfers.
- dma-channels: should be set to 4 representing the 4 endpoints.
- #dma-channels: deprecated

Example:
	usb_phy: usb-phy {
		compatible = "ti,da830-usb-phy";
		#phy-cells = <0>;
	};
	usb0: usb@200000 {
		compatible = "ti,da830-musb";
		reg = <0x00200000 0x1000>;
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupts = <58>;
		interrupt-names = "mc";

		dr_mode = "host";
		vbus-supply = <&usb_vbus>;
		phys = <&usb_phy 0>;
		phy-names = "usb-phy";

		dmas = <&cppi41dma 0 0 &cppi41dma 1 0
			&cppi41dma 2 0 &cppi41dma 3 0
			&cppi41dma 0 1 &cppi41dma 1 1
			&cppi41dma 2 1 &cppi41dma 3 1>;
		dma-names =
			"rx1", "rx2", "rx3", "rx4",
			"tx1", "tx2", "tx3", "tx4";

		cppi41dma: dma-controller@201000 {
			compatible = "ti,da830-cppi41";
			reg =  <0x201000 0x1000
				0x202000 0x1000
				0x204000 0x4000>;
			reg-names = "controller", "scheduler", "queuemgr";
			interrupts = <58>;
			#dma-cells = <2>;
			dma-channels = <4>;
		};

	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/dwc2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DesignWare HS OTG USB 2.0 controller Bindings

maintainers:
  - Rob Herring <robh@kernel.org>

allOf:
  - $ref: usb-drd.yaml#
  - $ref: usb-hcd.yaml#

properties:
  compatible:
    oneOf:
      - const: brcm,bcm2835-usb
      - const: hisilicon,hi6220-usb
      - const: ingenic,jz4775-otg
      - const: ingenic,jz4780-otg
      - const: ingenic,x1000-otg
      - const: ingenic,x1600-otg
      - const: ingenic,x1700-otg
      - const: ingenic,x1830-otg
      - const: ingenic,x2000-otg
      - items:
          - const: rockchip,rk3066-usb
          - const: snps,dwc2
      - items:
          - enum:
              - rockchip,px30-usb
              - rockchip,rk3036-usb
              - rockchip,rk3128-usb
              - rockchip,rk3188-usb
              - rockchip,rk3228-usb
              - rockchip,rk3288-usb
              - rockchip,rk3308-usb
              - rockchip,rk3328-usb
              - rockchip,rk3368-usb
              - rockchip,rv1108-usb
          - const: rockchip,rk3066-usb
          - const: snps,dwc2
      - const: lantiq,arx100-usb
      - const: lantiq,ase-usb
      - const: lantiq,danube-usb
      - const: lantiq,xrx200-usb
      - const: lantiq,xrx300-usb
      - items:
          - enum:
              - amlogic,meson8-usb
              - amlogic,meson8b-usb
              - amlogic,meson-gxbb-usb
              - amlogic,meson-g12a-usb
              - intel,socfpga-agilex-hsotg
          - const: snps,dwc2
      - const: amcc,dwc-otg
      - const: apm,apm82181-dwc-otg
      - const: snps,dwc2
      - const: st,stm32f4x9-fsotg
      - const: st,stm32f4x9-hsotg
      - const: st,stm32f7-hsotg
      - const: st,stm32mp15-fsotg
      - items:
          - const: st,stm32mp15-hsotg
          - const: snps,dwc2
      - const: samsung,s3c6400-hsotg
      - const: intel,socfpga-agilex-hsotg

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: otg

  disable-over-current:
    type: boolean
    description: whether to disable detection of over-current condition.

  iommus:
    maxItems: 1

  resets:
    items:
      - description: common reset
      - description: ecc reset
    minItems: 1

  reset-names:
    items:
      - const: dwc2
      - const: dwc2-ecc
    minItems: 1

  phys:
    maxItems: 1

  phy-names:
    const: usb2-phy

  power-domains:
    maxItems: 1

  vbus-supply:
    description: reference to the VBUS regulator. Depending on the current mode
      this is enabled (in "host" mode") or disabled (in "peripheral" mode). The
      regulator is updated if the controller is configured in "otg" mode and the
      status changes between "host" and "peripheral".

  vusb_d-supply:
    description: phandle to voltage regulator of digital section,

  vusb_a-supply:
    description: phandle to voltage regulator of analog section.

  usb33d-supply:
    description: reference to the VBUS and ID sensing comparators supply, in
      order to perform OTG operation, used on STM32MP15 SoCs.

  dr_mode: true

  otg-rev: true

  hnp-disable: true

  srp-disable: true

  usb-role-switch: true

  role-switch-default-mode: true

  g-rx-fifo-size:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: size of rx fifo size in gadget mode.

  g-np-tx-fifo-size:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: size of non-periodic tx fifo size in gadget mode.

  g-tx-fifo-size:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: size of periodic tx fifo per endpoint (except ep0) in gadget mode.

  snps,need-phy-for-wake:
    $ref: /schemas/types.yaml#/definitions/flag
    description: If present indicates that the phy needs to be left on for
      remote wakeup during suspend.

  snps,reset-phy-on-wake:
    $ref: /schemas/types.yaml#/definitions/flag
    description: If present indicates that we need to reset the PHY when we
      detect a wakeup. This is due to a hardware errata.

  port:
    description:
      Any connector to the data bus of this controller should be modelled
      using the OF graph bindings specified, if the "usb-role-switch"
      property is used.
    $ref: /schemas/graph.yaml#/properties/port

  tpl-support: true

dependencies:
  port: [ usb-role-switch ]
  role-switch-default-mode: [ usb-role-switch ]

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
      usb@101c0000 {
        compatible = "rockchip,rk3066-usb", "snps,dwc2";
        reg = <0x10180000 0x40000>;
        interrupts = <18>;
        clocks = <&usb_otg_ahb_clk>;
        clock-names = "otg";
        phys = <&usbphy>;
        phy-names = "usb2-phy";
      };

...


code:
Cavium SuperSpeed DWC3 USB SoC controller

Required properties:
- compatible:	Should contain "cavium,octeon-7130-usb-uctl"

Required child node:
A child node must exist to represent the core DWC3 IP block. The name of
the node is not important. The content of the node is defined in dwc3.txt.

Example device node:

		    uctl@1180069000000 {
			    compatible = "cavium,octeon-7130-usb-uctl";
			    reg = <0x00011800 0x69000000 0x00000000 0x00000100>;
			    ranges;
			    #address-cells = <0x00000002>;
			    #size-cells = <0x00000002>;
			    refclk-frequency = <0x05f5e100>;
			    refclk-type-ss = "dlmc_ref_clk0";
			    refclk-type-hs = "dlmc_ref_clk0";
			    power = <0x00000002 0x00000002 0x00000001>;
			    xhci@1690000000000 {
				    compatible = "cavium,octeon-7130-xhci", "snps,dwc3";
				    reg = <0x00016900 0x00000000 0x00000010 0x00000000>;
				    interrupt-parent = <0x00000010>;
				    interrupts = <0x00000009 0x00000004>;
			    };
		    };


code:
ST DWC3 glue logic

This file documents the parameters for the dwc3-st driver.
This driver controls the glue logic used to configure the dwc3 core on
STiH407 based platforms.

Required properties:
 - compatible	: must be "st,stih407-dwc3"
 - reg		: glue logic base address and USB syscfg ctrl register offset
 - reg-names	: should be "reg-glue" and "syscfg-reg"
 - st,syscon	: should be phandle to system configuration node which
		  encompasses the glue registers
 - resets	: list of phandle and reset specifier pairs. There should be two entries, one
		  for the powerdown and softreset lines of the usb3 IP
 - reset-names	: list of reset signal names. Names should be "powerdown" and "softreset"
See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
See: Documentation/devicetree/bindings/reset/reset.txt

 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
   with 'reg' property

 - pinctl-names	: A pinctrl state named "default" must be defined
See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

 - pinctrl-0	: Pin control group
See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

 - ranges	: allows valid 1:1 translation between child's address space and
		  parent's address space

Sub-nodes:
The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
example below. The DT binding details of dwc3 can be found in:
Documentation/devicetree/bindings/usb/snps,dwc3.yaml

NB: The dr_mode property described in [1] is NOT optional for this driver, as the default value
is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
or "device".

[1] Documentation/devicetree/bindings/usb/usb-drd.yaml

Example:

st_dwc3: dwc3@8f94000 {
	compatible	= "st,stih407-dwc3";
	reg		= <0x08f94000 0x1000>, <0x110 0x4>;
	reg-names	= "reg-glue", "syscfg-reg";
	st,syscfg	= <&syscfg_core>;
	resets		= <&powerdown STIH407_USB3_POWERDOWN>,
			  <&softreset STIH407_MIPHY2_SOFTRESET>;
	reset-names	= "powerdown", "softreset";
	#address-cells	= <1>;
	#size-cells	= <1>;
	pinctrl-names	= "default";
	pinctrl-0	= <&pinctrl_usb3>;
	ranges;

	dwc3: dwc3@9900000 {
		compatible	= "snps,dwc3";
		reg		= <0x09900000 0x100000>;
		interrupts	= <GIC_SPI 155 IRQ_TYPE_NONE>;
		dr_mode		= "host";
		phy-names	= "usb2-phy", "usb3-phy";
		phys		= <&usb2_picophy2>, <&phy_port2 PHY_TYPE_USB3>;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx SuperSpeed DWC3 USB SoC controller

maintainers:
  - Manish Narani <manish.narani@xilinx.com>

properties:
  compatible:
    items:
      - enum:
          - xlnx,zynqmp-dwc3
          - xlnx,versal-dwc3
  reg:
    maxItems: 1

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

  ranges: true

  power-domains:
    description: specifies a phandle to PM domain provider node
    maxItems: 1

  clocks:
    description:
      A list of phandle and clock-specifier pairs for the clocks
      listed in clock-names.
    items:
      - description: Master/Core clock, has to be >= 125 MHz
          for SS operation and >= 60MHz for HS operation.
      - description: Clock source to core during PHY power down.

  clock-names:
    items:
      - const: bus_clk
      - const: ref_clk

  resets:
    description:
      A list of phandles for resets listed in reset-names.

    items:
      - description: USB core reset
      - description: USB hibernation reset
      - description: USB APB reset

  reset-names:
    items:
      - const: usb_crst
      - const: usb_hibrst
      - const: usb_apbrst

  phys:
    minItems: 1
    maxItems: 2

  phy-names:
    minItems: 1
    maxItems: 2
    items:
      enum:
        - usb2-phy
        - usb3-phy

  reset-gpios:
    description: GPIO used for the reset ulpi-phy
    maxItems: 1

# Required child node:

patternProperties:
  "^usb@[0-9a-f]+$":
    $ref: snps,dwc3.yaml#

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - power-domains
  - clocks
  - clock-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
    #include <dt-bindings/power/xlnx-zynqmp-power.h>
    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
    #include <dt-bindings/phy/phy.h>
    axi {
        #address-cells = <2>;
        #size-cells = <2>;

        usb@0 {
            #address-cells = <0x2>;
            #size-cells = <0x2>;
            compatible = "xlnx,zynqmp-dwc3";
            reg = <0x0 0xff9d0000 0x0 0x100>;
            clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
            clock-names = "bus_clk", "ref_clk";
            power-domains = <&zynqmp_firmware PD_USB_0>;
            resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
                     <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
                     <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
            reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
            phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
            phy-names = "usb3-phy";
            ranges;

            usb@fe200000 {
                compatible = "snps,dwc3";
                reg = <0x0 0xfe200000 0x0 0x40000>;
                interrupt-names = "host", "otg";
                interrupts = <0 65 4>, <0 69 4>;
                dr_mode = "host";
                dma-coherent;
            };
        };
    };


code:
OMAP HS USB EHCI controller

This device is usually the child of the omap-usb-host
Documentation/devicetree/bindings/mfd/omap-usb-host.txt

Required properties:

- compatible: should be "ti,ehci-omap"
- reg: should contain one register range i.e. start and length
- interrupts: description of the interrupt line

Optional properties:

- phys: list of phandles to PHY nodes.
  This property is required if at least one of the ports are in
  PHY mode i.e. OMAP_EHCI_PORT_MODE_PHY

To specify the port mode, see
Documentation/devicetree/bindings/mfd/omap-usb-host.txt

Example for OMAP4:

usbhsehci: ehci@4a064c00 {
	compatible = "ti,ehci-omap";
	reg = <0x4a064c00 0x400>;
	interrupts = <0 77 0x4>;
};

&usbhsehci {
	phys = <&hsusb1_phy 0 &hsusb3_phy>;
};


code:
* EHCI controller, Orion Marvell variants

Required properties:
- compatible: must be one of the following
	"marvell,orion-ehci"
	"marvell,armada-3700-ehci"
- reg: physical base address of the controller and length of memory mapped
  region.
- interrupts: The EHCI interrupt

Optional properties:
- clocks: reference to the clock
- phys: reference to the USB PHY
- phy-names: name of the USB PHY, should be "usb"

Example:

	ehci@50000 {
		compatible = "marvell,orion-ehci";
		reg = <0x50000 0x1000>;
		interrupts = <19>;
	};


code:
ST USB EHCI controller

Required properties:
 - compatible		: must be "st,st-ehci-300x"
 - reg			: physical base addresses of the controller and length of memory mapped
			  region
 - interrupts		: one EHCI interrupt should be described here
 - pinctrl-names	: a pinctrl state named "default" must be defined
 - pinctrl-0		: phandle referencing pin configuration of the USB controller
See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
 - clocks		: phandle list of usb clocks
 - clock-names		: should be "ic" for interconnect clock and "clk48"
See: Documentation/devicetree/bindings/clock/clock-bindings.txt

 - phys			: phandle for the PHY device
 - phy-names		: should be "usb"
 - resets		: phandle + reset specifier pairs to the powerdown and softreset lines
			  of the USB IP
 - reset-names		: should be "power" and "softreset"
See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
See: Documentation/devicetree/bindings/reset/reset.txt

Example:

	ehci1: usb@fe203e00 {
		compatible = "st,st-ehci-300x";
		reg = <0xfe203e00 0x100>;
		interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1>;
		clocks = <&clk_s_a1_ls 0>;
		phys = <&usb2_phy>;
		phy-names = "usb";

		resets = <&powerdown STIH416_USB1_POWERDOWN>,
			 <&softreset STIH416_USB1_SOFTRESET>;
		reset-names = "power", "softreset";
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2022 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/faraday,fotg210.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Faraday Technology FOTG210 HS OTG USB 2.0 controller Bindings

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

allOf:
  - $ref: usb-drd.yaml#
  - $ref: usb-hcd.yaml#

properties:
  compatible:
    oneOf:
      - const: faraday,fotg210
      - items:
          - const: cortina,gemini-usb
          - const: faraday,fotg210

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: PCLK

  resets:
    maxItems: 1

  syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: a phandle to the global Gemini system controller on
      Gemini systems

  dr_mode: true

  phys:
    maxItems: 1

  phy-names:
    const: usb2-phy

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/cortina,gemini-clock.h>
    #include <dt-bindings/reset/cortina,gemini-reset.h>
    usb0: usb@68000000 {
        compatible = "cortina,gemini-usb", "faraday,fotg210";
        reg = <0x68000000 0x1000>;
        interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
        resets = <&syscon GEMINI_RESET_USB0>;
        clocks = <&syscon GEMINI_CLK_GATE_USB0>;
        clock-names = "PCLK";
        syscon = <&syscon>;
        dr_mode = "host";
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: "http://devicetree.org/schemas/usb/fcs,fsa4480.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: ON Semiconductor Analog Audio Switch

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

properties:
  compatible:
    enum:
      - fcs,fsa4480

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  vcc-supply:
    description: power supply (2.7V-5.5V)

  mode-switch:
    description: Flag the port as possible handle of altmode switching
    type: boolean

  orientation-switch:
    description: Flag the port as possible handler of orientation switching
    type: boolean

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      A port node to link the FSA4480 to a TypeC controller for the purpose of
      handling altmode muxing and orientation switching.

required:
  - compatible
  - reg
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c13 {
        #address-cells = <1>;
        #size-cells = <0>;

        fsa4480@42 {
          compatible = "fcs,fsa4480";
          reg = <0x42>;

          interrupts-extended = <&tlmm 2 IRQ_TYPE_LEVEL_LOW>;

          vcc-supply = <&vreg_bob>;

          mode-switch;
          orientation-switch;

          port {
            fsa4480_ept: endpoint {
              remote-endpoint = <&typec_controller>;
            };
          };
        };
    };
...


code:
Fairchild FUSB302 Type-C Port controllers

Required properties :
- compatible             : "fcs,fusb302"
- reg                    : I2C slave address
- interrupts             : Interrupt specifier

Required sub-node:
- connector : The "usb-c-connector" attached to the FUSB302 IC. The bindings
  of the connector node are specified in:

	Documentation/devicetree/bindings/connector/usb-connector.yaml

Example:

fusb302: typec-portc@54 {
	compatible = "fcs,fusb302";
	reg = <0x54>;
	interrupt-parent = <&nmi_intc>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;

	usb_con: connector {
		compatible = "usb-c-connector";
		label = "USB-C";
		power-role = "dual";
		try-power-role = "sink";
		source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
		sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
			     PDO_VAR(3000, 12000, 3000)
			     PDO_PPS_APDO(3000, 11000, 3000)>;
		op-sink-microwatt = <10000000>;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP iMX8MP Soc USB Controller

maintainers:
  - Li Jun <jun.li@nxp.com>

properties:
  compatible:
    const: fsl,imx8mp-dwc3

  reg:
    items:
      - description: Address and length of the register set for HSIO Block Control
      - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

  dma-ranges:
    description:
      See section 2.3.9 of the DeviceTree Specification.

  ranges: true

  interrupts:
    maxItems: 1
    description: The interrupt that is asserted when a wakeup event is
      received.

  clocks:
    description:
      A list of phandle and clock-specifier pairs for the clocks
      listed in clock-names.
    items:
      - description: system hsio root clock.
      - description: suspend clock, used for usb wakeup logic.

  clock-names:
    items:
      - const: hsio
      - const: suspend

  fsl,permanently-attached:
    type: boolean
    description:
      Indicates if the device atached to a downstream port is
      permanently attached.

  fsl,disable-port-power-control:
    type: boolean
    description:
      Indicates whether the host controller implementation includes port
      power control. Defines Bit 3 in capability register (HCCPARAMS).

  fsl,over-current-active-low:
    type: boolean
    description:
      Over current signal polarity is active low.

  fsl,power-active-low:
    type: boolean
    description:
      Power pad (PWR) polarity is active low.

# Required child node:

patternProperties:
  "^usb@[0-9a-f]+$":
    $ref: snps,dwc3.yaml#

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - dma-ranges
  - ranges
  - clocks
  - clock-names
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mp-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    usb3_0: usb@32f10100 {
      compatible = "fsl,imx8mp-dwc3";
      reg = <0x32f10100 0x8>,
            <0x381f0000 0x20>;
      clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
               <&clk IMX8MP_CLK_USB_ROOT>;
      clock-names = "hsio", "suspend";
      interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
      #address-cells = <1>;
      #size-cells = <1>;
      dma-ranges = <0x40000000 0x40000000 0xc0000000>;
      ranges;

      usb@38100000 {
        compatible = "snps,dwc3";
        reg = <0x38100000 0x10000>;
        clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
                 <&clk IMX8MP_CLK_USB_CORE_REF>,
                 <&clk IMX8MP_CLK_USB_ROOT>;
        clock-names = "bus_early", "ref", "suspend";
        assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
        assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
        assigned-clock-rates = <500000000>;
        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
        phys = <&usb3_phy0>, <&usb3_phy0>;
        phy-names = "usb2-phy", "usb3-phy";
        snps,dis-u2-freeclk-exists-quirk;
      };
    };


code:
Freescale SOC USB controllers

The device node for a USB controller that is part of a Freescale
SOC is as described in the document "Open Firmware Recommended
Practice : Universal Serial Bus" with the following modifications
and additions :

Required properties :
 - compatible : Should be "fsl-usb2-mph" for multi port host USB
   controllers, or "fsl-usb2-dr" for dual role USB controllers
   or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121.
   Wherever applicable, the IP version of the USB controller should
   also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132).
 - phy_type : For multi port host USB controllers, should be one of
   "ulpi", or "serial". For dual role USB controllers, should be
   one of "ulpi", "utmi", "utmi_wide", or "serial".
 - reg : Offset and length of the register set for the device
 - port0 : boolean; if defined, indicates port0 is connected for
   fsl-usb2-mph compatible controllers.  Either this property or
   "port1" (or both) must be defined for "fsl-usb2-mph" compatible
   controllers.
 - port1 : boolean; if defined, indicates port1 is connected for
   fsl-usb2-mph compatible controllers.  Either this property or
   "port0" (or both) must be defined for "fsl-usb2-mph" compatible
   controllers.
 - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
   controllers.  Can be "host", "peripheral", or "otg".  Default to
   "host" if not defined for backward compatibility.

Recommended properties :
 - interrupts : <a b> where a is the interrupt number and b is a
   field that represents an encoding of the sense and level
   information for the interrupt.  This should be encoded based on
   the information in section 2) depending on the type of interrupt
   controller you have.

Optional properties :
 - fsl,invert-drvvbus : boolean; for MPC5121 USB0 only. Indicates the
   port power polarity of internal PHY signal DRVVBUS is inverted.
 - fsl,invert-pwr-fault : boolean; for MPC5121 USB0 only. Indicates
   the PWR_FAULT signal polarity is inverted.

Example multi port host USB controller device node :
	usb@22000 {
		compatible = "fsl-usb2-mph";
		reg = <22000 1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupt-parent = <700>;
		interrupts = <27 1>;
		phy_type = "ulpi";
		port0;
		port1;
	};

Example dual role USB controller device node :
	usb@23000 {
		compatible = "fsl-usb2-dr";
		reg = <23000 1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupt-parent = <700>;
		interrupts = <26 1>;
		dr_mode = "otg";
		phy = "ulpi";
	};

Example dual role USB controller device node for MPC5121ADS:

	usb@4000 {
		compatible = "fsl,mpc5121-usb2-dr";
		reg = <0x4000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupt-parent = < &ipic >;
		interrupts = <44 0x8>;
		dr_mode = "otg";
		phy_type = "utmi_wide";
		fsl,invert-drvvbus;
		fsl,invert-pwr-fault;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/generic-ehci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: USB EHCI Controller

maintainers:
  - Greg Kroah-Hartman <gregkh@linuxfoundation.org>

allOf:
  - $ref: "usb-hcd.yaml"
  - if:
      properties:
        compatible:
          not:
            contains:
              const: ibm,usb-ehci-440epx
    then:
      properties:
        reg:
          maxItems: 1

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - allwinner,sun4i-a10-ehci
              - allwinner,sun50i-a64-ehci
              - allwinner,sun50i-h6-ehci
              - allwinner,sun50i-h616-ehci
              - allwinner,sun5i-a13-ehci
              - allwinner,sun6i-a31-ehci
              - allwinner,sun7i-a20-ehci
              - allwinner,sun8i-a23-ehci
              - allwinner,sun8i-a83t-ehci
              - allwinner,sun8i-h3-ehci
              - allwinner,sun8i-r40-ehci
              - allwinner,sun9i-a80-ehci
              - allwinner,sun20i-d1-ehci
              - aspeed,ast2400-ehci
              - aspeed,ast2500-ehci
              - aspeed,ast2600-ehci
              - brcm,bcm3384-ehci
              - brcm,bcm63268-ehci
              - brcm,bcm6328-ehci
              - brcm,bcm6358-ehci
              - brcm,bcm6362-ehci
              - brcm,bcm6368-ehci
              - brcm,bcm7125-ehci
              - brcm,bcm7346-ehci
              - brcm,bcm7358-ehci
              - brcm,bcm7360-ehci
              - brcm,bcm7362-ehci
              - brcm,bcm7420-ehci
              - brcm,bcm7425-ehci
              - brcm,bcm7435-ehci
              - hpe,gxp-ehci
              - ibm,476gtr-ehci
              - nxp,lpc1850-ehci
              - qca,ar7100-ehci
              - snps,hsdk-v1.0-ehci
              - socionext,uniphier-ehci
          - const: generic-ehci
      - items:
          - enum:
              - cavium,octeon-6335-ehci
              - ibm,usb-ehci-440epx
              - ibm,usb-ehci-460ex
              - nintendo,hollywood-usb-ehci
              - st,spear600-ehci
          - const: usb-ehci
      - enum:
          - generic-ehci
          - usb-ehci

  reg:
    minItems: 1
    maxItems: 2

  interrupts:
    maxItems: 1

  resets:
    minItems: 1
    maxItems: 4

  clocks:
    minItems: 1
    maxItems: 4
    description: |
      In case the Renesas R-Car Gen3 SoCs:
        - if a host only channel: first clock should be host.
        - if a USB DRD channel: first clock should be host and second
          one should be peripheral

  power-domains:
    maxItems: 1

  big-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set this flag for HCDs with big endian descriptors and big
      endian registers.

  big-endian-desc:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set this flag for HCDs with big endian descriptors.

  big-endian-regs:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set this flag for HCDs with big endian registers.

  has-transaction-translator:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set this flag if EHCI has a Transaction Translator built into
      the root hub.

  needs-reset-on-resume:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set this flag to force EHCI reset after resume.

  spurious-oc:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set this flag to indicate that the hardware sometimes turns on
      the OC bit when an over-current isn't actually present.

  phys:
    minItems: 1
    maxItems: 3

  phy-names:
    const: usb

  iommus:
    maxItems: 1

  dr_mode:
    enum:
      - host
      - otg

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    usb@e0000300 {
        compatible = "ibm,usb-ehci-440epx", "usb-ehci";
        interrupt-parent = <&UIC0>;
        interrupts = <0x1a 4>;
        reg = <0xe0000300 90>, <0xe0000390 70>;
        big-endian;
    };

  - |
    ehci0: usb@1c14000 {
        compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
        reg = <0x01c14000 0x100>;
        interrupts = <39>;
        clocks = <&ahb_gates 1>;
        phys = <&usbphy 1>;
        phy-names = "usb";
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/generic-ohci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: USB OHCI Controller

allOf:
  - $ref: "usb-hcd.yaml"

maintainers:
  - Greg Kroah-Hartman <gregkh@linuxfoundation.org>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - allwinner,sun4i-a10-ohci
              - allwinner,sun50i-a64-ohci
              - allwinner,sun50i-h6-ohci
              - allwinner,sun50i-h616-ohci
              - allwinner,sun5i-a13-ohci
              - allwinner,sun6i-a31-ohci
              - allwinner,sun7i-a20-ohci
              - allwinner,sun8i-a23-ohci
              - allwinner,sun8i-a83t-ohci
              - allwinner,sun8i-h3-ohci
              - allwinner,sun8i-r40-ohci
              - allwinner,sun9i-a80-ohci
              - allwinner,sun20i-d1-ohci
              - brcm,bcm3384-ohci
              - brcm,bcm63268-ohci
              - brcm,bcm6328-ohci
              - brcm,bcm6358-ohci
              - brcm,bcm6362-ohci
              - brcm,bcm6368-ohci
              - brcm,bcm7125-ohci
              - brcm,bcm7346-ohci
              - brcm,bcm7358-ohci
              - brcm,bcm7360-ohci
              - brcm,bcm7362-ohci
              - brcm,bcm7420-ohci
              - brcm,bcm7425-ohci
              - brcm,bcm7435-ohci
              - hpe,gxp-ohci
              - ibm,476gtr-ohci
              - ingenic,jz4740-ohci
              - snps,hsdk-v1.0-ohci
          - const: generic-ohci
      - const: generic-ohci

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  resets:
    minItems: 1
    maxItems: 2

  clocks:
    minItems: 1
    maxItems: 3
    description: |
      In case the Renesas R-Car Gen3 SoCs:
        - if a host only channel: first clock should be host.
        - if a USB DRD channel: first clock should be host and second
          one should be peripheral

  power-domains:
    maxItems: 1

  big-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set this flag for HCDs with big endian descriptors and big
      endian registers.

  big-endian-desc:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set this flag for HCDs with big endian descriptors.

  big-endian-regs:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set this flag for HCDs with big endian registers.

  remote-wakeup-connected:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Remote wakeup is wired on the platform.

  no-big-frame-no:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set if frame_no lives in bits [15:0] of HCCA

  num-ports:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Overrides the detected port count

  phys:
    minItems: 1
    maxItems: 3

  phy-names:
    const: usb

  iommus:
    maxItems: 1

  dr_mode:
    enum:
      - host
      - otg

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
      ohci0: usb@1c14400 {
          compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
          reg = <0x01c14400 0x100>;
          interrupts = <64>;
          clocks = <&usb_clk 6>, <&ahb_gates 2>;
          phys = <&usbphy 1>;
          phy-names = "usb";
      };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/generic-xhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: USB xHCI Controller

maintainers:
  - Mathias Nyman <mathias.nyman@intel.com>

allOf:
  - $ref: "usb-xhci.yaml#"

properties:
  compatible:
    oneOf:
      - description: Generic xHCI device
        const: generic-xhci
      - description: Armada 37xx/375/38x/8k SoCs
        items:
          - enum:
              - marvell,armada3700-xhci
              - marvell,armada-375-xhci
              - marvell,armada-380-xhci
              - marvell,armada-8k-xhci
          - const: generic-xhci
      - description: Broadcom STB SoCs with xHCI
        enum:
          - brcm,xhci-brcm-v2
          - brcm,bcm7445-xhci
      - description: Generic xHCI device
        const: xhci-platform
        deprecated: true

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: core
      - const: reg

unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts

examples:
  - |
    usb@f0931000 {
      compatible = "generic-xhci";
      reg = <0xf0931000 0x8c8>;
      interrupts = <0x0 0x4e 0x0>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/genesys,gl850g.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Genesys Logic GL850G USB 2.0 hub controller

maintainers:
  - Icenowy Zheng <uwu@icenowy.me>

allOf:
  - $ref: usb-device.yaml#

properties:
  compatible:
    enum:
      - usb5e3,608

  reg: true

  reset-gpios:
    description: GPIO controlling the RESET# pin.

  vdd-supply:
    description:
      the regulator that provides 3.3V core power to the hub.

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    usb {
        dr_mode = "host";
        #address-cells = <1>;
        #size-cells = <0>;

        hub: hub@1 {
            compatible = "usb5e3,608";
            reg = <1>;
            reset-gpios = <&pio 7 2 GPIO_ACTIVE_LOW>;
        };
    };


code:
USB Peripheral Controller driver for Aeroflex Gaisler GRUSBDC.

The GRUSBDC USB Device Controller core is available in the GRLIB VHDL
IP core library.

Note: In the ordinary environment for the core, a Leon SPARC system,
these properties are built from information in the AMBA plug&play.

Required properties:

- name : Should be "GAISLER_USBDC" or "01_021"

- reg : Address and length of the register set for the device

- interrupts : Interrupt numbers for this device. Either one interrupt number
	for all interrupts, or one for status related interrupts, one for IN
	endpoint related interrupts and one for OUT endpoint related interrupts.

Optional properties:

- epobufsizes : Array of buffer sizes for OUT endpoints when they differ
	from the default size of 1024. The array is indexed by the OUT endpoint
	number. If the property is present it typically contains one entry for
	each OUT endpoint of the core. Fewer entries overrides the default sizes
	only for as many endpoints as the array contains.

- epibufsizes : Array of buffer sizes for IN endpoints when they differ
	from the default size of 1024. The array is indexed by the IN endpoint
	number. If the property is present it typically contains one entry for
	each IN endpoint of the core. Fewer entries overrides the default sizes
	only for as many endpoints as the array contains.

For further information look in the documentation for the GLIB IP core library:
http://www.gaisler.com/products/grlib/grip.pdf


code:
HiSilicon STB xHCI

The device node for HiSilicon STB xHCI host controller

Required properties:
 - compatible: should be "hisilicon,hi3798cv200-xhci"
 - reg: specifies physical base address and size of the registers
 - interrupts : interrupt used by the controller
 - clocks: a list of phandle + clock-specifier pairs, one for each
	entry in clock-names
 - clock-names: must contain
	"bus": for bus clock
	"utmi": for utmi clock
	"pipe": for pipe clock
	"suspend": for suspend clock
 - resets: a list of phandle and reset specifier pairs as listed in
	reset-names property.
 - reset-names: must contain
	"soft": for soft reset
 - phys: a list of phandle + phy specifier pairs
 - phy-names: must contain at least one of following:
	"inno": for inno phy
	"combo": for combo phy

Optional properties:
  - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
  - usb3-lpm-capable: determines if platform is USB3 LPM capable
  - imod-interval-ns: default interrupt moderation interval is 40000ns

Example:

xhci0: xchi@f98a0000 {
	compatible = "hisilicon,hi3798cv200-xhci";
	reg = <0xf98a0000 0x10000>;
	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&crg HISTB_USB3_BUS_CLK>,
		 <&crg HISTB_USB3_UTMI_CLK>,
		 <&crg HISTB_USB3_PIPE_CLK>,
		 <&crg HISTB_USB3_SUSPEND_CLK>;
	clock-names = "bus", "utmi", "pipe", "suspend";
	resets = <&crg 0xb0 12>;
	reset-names = "soft";
	phys = <&usb2_phy1_port1 0>, <&combphy0 PHY_TYPE_USB3>;
	phy-names = "inno", "combo";
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/ingenic,musb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic JZ47xx USB IP DT bindings

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

properties:
  $nodename:
    pattern: '^usb@.*'

  compatible:
    oneOf:
      - enum:
          - ingenic,jz4770-musb
          - ingenic,jz4740-musb
      - items:
          - const: ingenic,jz4725b-musb
          - const: ingenic,jz4740-musb

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: udc

  interrupts:
    maxItems: 1

  interrupt-names:
    items:
      - const: mc

  phys:
    maxItems: 1

  usb-role-switch:
    type: boolean

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts
  - interrupt-names
  - phys

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
    usb_phy: usb-phy {
      compatible = "usb-nop-xceiv";
      #phy-cells = <0>;
    };

    udc: usb@13040000 {
      compatible = "ingenic,jz4740-musb";
      reg = <0x13040000 0x10000>;

      interrupt-parent = <&intc>;
      interrupts = <24>;
      interrupt-names = "mc";

      clocks = <&cgu JZ4740_CLK_UDC>;
      clock-names = "udc";

      phys = <&usb_phy>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/intel,keembay-dwc3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Keem Bay DWC3 USB controller

maintainers:
  - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>

properties:
  compatible:
    const: intel,keembay-dwc3

  reg:
    maxItems: 1

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: async_master
      - const: ref
      - const: alt_ref
      - const: suspend

  ranges: true

  '#address-cells':
    enum: [ 1, 2 ]

  '#size-cells':
    enum: [ 1, 2 ]

# Required child node:

patternProperties:
  "^usb@[0-9a-f]+$":
    $ref: snps,dwc3.yaml#

required:
  - compatible
  - clocks
  - clock-names
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #define KEEM_BAY_A53_AUX_USB
    #define KEEM_BAY_A53_AUX_USB_REF
    #define KEEM_BAY_A53_AUX_USB_ALT_REF
    #define KEEM_BAY_A53_AUX_USB_SUSPEND

    usb {
          compatible = "intel,keembay-dwc3";
          clocks = <&scmi_clk KEEM_BAY_A53_AUX_USB>,
                   <&scmi_clk KEEM_BAY_A53_AUX_USB_REF>,
                   <&scmi_clk KEEM_BAY_A53_AUX_USB_ALT_REF>,
                   <&scmi_clk KEEM_BAY_A53_AUX_USB_SUSPEND>;
          clock-names = "async_master", "ref", "alt_ref", "suspend";
          ranges;
          #address-cells = <1>;
          #size-cells = <1>;

          usb@34000000 {
                compatible = "snps,dwc3";
                reg = <0x34000000 0x10000>;
                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                dr_mode = "peripheral";
          };
    };


code:
Broadcom IPROC USB Device controller.

The device node is used for UDCs integrated into Broadcom's
iProc family (Northstar2, Cygnus) of SoCs'. The UDC is based
on Synopsys Designware Cores AHB Subsystem Device Controller
IP.

Required properties:
 - compatible: Add the compatibility strings for supported platforms.
   For Broadcom NS2 platform, add "brcm,ns2-udc","brcm,iproc-udc".
   For Broadcom Cygnus platform, add "brcm,cygnus-udc", "brcm,iproc-udc".
 - reg: Offset and length of UDC register set
 - interrupts: description of interrupt line
 - phys: phandle to phy node.

Example:
	udc_dwc: usb@664e0000 {
		compatible = "brcm,ns2-udc", "brcm,iproc-udc";
		reg = <0x664e0000 0x2000>;
		interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&usbdrd_phy>;


code:
* NXP ISP1301 USB transceiver

Required properties:
- compatible: must be "nxp,isp1301"
- reg: I2C address of the ISP1301 device

Optional properties of devices using ISP1301:
- transceiver: phandle of isp1301 - this helps the ISP1301 driver to find the
               ISP1301 instance associated with the respective USB driver

Example:

	isp1301: usb-transceiver@2c {
		compatible = "nxp,isp1301";
		reg = <0x2c>;
	};

	usbd@31020000 {
		compatible = "nxp,lpc3220-udc";
		reg = <0x31020000 0x300>;
		interrupt-parent = <&mic>;
		interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
		transceiver = <&isp1301>;
	};


code:
* NXP LPC32xx SoC USB Device Controller (UDC)

Required properties:
- compatible: Must be "nxp,lpc3220-udc"
- reg: Physical base address of the controller and length of memory mapped
  region.
- interrupts: The USB interrupts:
              * USB Device Low Priority Interrupt
              * USB Device High Priority Interrupt
              * USB Device DMA Interrupt
              * External USB Transceiver Interrupt (OTG ATX)
- transceiver: phandle of the associated ISP1301 device - this is necessary for
               the UDC controller for connecting to the USB physical layer

Example:

	isp1301: usb-transceiver@2c {
		compatible = "nxp,isp1301";
		reg = <0x2c>;
	};

	usbd@31020000 {
		compatible = "nxp,lpc3220-udc";
		reg = <0x31020000 0x300>;
		interrupt-parent = <&mic>;
		interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
		transceiver = <&isp1301>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2019,2020 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/marvell,pxau2o-ehci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell PXA/MMP EHCI bindings

maintainers:
  - Lubomir Rintel <lkundrak@v3.sk>

allOf:
  - $ref: usb-hcd.yaml#

properties:
  compatible:
    const: marvell,pxau2o-ehci

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: USBCLK

  phys:
    maxItems: 1

  phy-names:
    const: usb

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - phys
  - phy-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/marvell,mmp2.h>
    usb@d4208000 {
        compatible = "marvell,pxau2o-ehci";
        reg = <0xd4208000 0x200>;
        interrupts = <44>;
        clocks = <&soc_clocks MMP2_CLK_USB>;
        clock-names = "USBCLK";
        phys = <&usb_otg_phy>;
        phy-names = "usb";
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/usb/maxim,max33359.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Maxim TCPCI Type-C PD controller DT bindings

maintainers:
  - Badhri Jagan Sridharan <badhri@google.com>

description: Maxim TCPCI Type-C PD controller

properties:
  compatible:
    enum:
      - maxim,max33359

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  connector:
    type: object
    $ref: ../connector/usb-connector.yaml#
    description:
      Properties for usb c connector.

required:
  - compatible
  - reg
  - interrupts
  - connector

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/usb/pd.h>
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        maxtcpc@25 {
            compatible = "maxim,max33359";
            reg = <0x25>;
            interrupt-parent = <&gpa8>;
            interrupts = <2 IRQ_TYPE_LEVEL_LOW>;

            connector {
                compatible = "usb-c-connector";
                label = "USB-C";
                data-role = "dual";
                power-role = "dual";
                try-power-role = "sink";
                self-powered;
                op-sink-microwatt = <2600000>;
                new-source-frs-typec-current = <FRS_5V_1P5A>;
                source-pdos = <PDO_FIXED(5000, 900,
                                         PDO_FIXED_SUSPEND |
                                         PDO_FIXED_USB_COMM |
                                         PDO_FIXED_DATA_SWAP |
                                         PDO_FIXED_DUAL_ROLE)>;
                sink-pdos = <PDO_FIXED(5000, 3000,
                                       PDO_FIXED_USB_COMM |
                                       PDO_FIXED_DATA_SWAP |
                                       PDO_FIXED_DUAL_ROLE)
                                       PDO_FIXED(9000, 2000, 0)>;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/maxim,max3420-udc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MAXIM MAX3420/1 USB Peripheral Controller

maintainers:
  - Jassi Brar <jaswinder.singh@linaro.org>

description: |
  The controller provices USB2.0 compliant FullSpeed peripheral
  implementation over the SPI interface.

  Specifications about the part can be found at:
    http://datasheets.maximintegrated.com/en/ds/MAX3420E.pdf

properties:
  compatible:
    enum:
      - maxim,max3420-udc
      - maxim,max3421-udc

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: usb irq from max3420
      - description: vbus detection irq
    minItems: 1

  interrupt-names:
    items:
      - const: udc
      - const: vbus
    minItems: 1

  spi-max-frequency:
    maximum: 26000000

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
      #include <dt-bindings/gpio/gpio.h>
      #include <dt-bindings/interrupt-controller/irq.h>
      spi0 {
            #address-cells = <1>;
            #size-cells = <0>;

            udc@0 {
                  compatible = "maxim,max3420-udc";
                  reg = <0>;
                  interrupt-parent = <&gpio>;
                  interrupts = <0 IRQ_TYPE_EDGE_FALLING>, <10 IRQ_TYPE_EDGE_BOTH>;
                  interrupt-names = "udc", "vbus";
                  spi-max-frequency = <12500000>;
            };
      };


code:
Maxim Integrated SPI-based USB 2.0 host controller MAX3421E

Required properties:
 - compatible: Should be "maxim,max3421"
 - spi-max-frequency: maximum frequency for this device must not exceed 26 MHz.
 - reg: chip select number to which this device is connected.
 - maxim,vbus-en-pin: <GPOUTx ACTIVE_LEVEL>
   GPOUTx is the number (1-8) of the GPOUT pin of MAX3421E to drive Vbus.
   ACTIVE_LEVEL is 0 or 1.
 - interrupts: the interrupt line description for the interrupt controller.
   The driver configures MAX3421E for active low level triggered interrupts,
   configure your interrupt line accordingly.

Example:

	usb@0 {
		compatible = "maxim,max3421";
		reg = <0>;
		maxim,vbus-en-pin = <3 1>;
		spi-max-frequency = <26000000>;
		interrupt-parent = <&PIC>;
		interrupts = <42>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/usb/mediatek,mt6360-tcpc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Mediatek MT6360 Type-C Port Switch and Power Delivery controller DT bindings

maintainers:
  - ChiYuan Huang <cy_huang@richtek.com>

description: |
  Mediatek MT6360 is a multi-functional device. It integrates charger, ADC, flash, RGB indicators,
  regulators (BUCKs/LDOs), and TypeC Port Switch with Power Delivery controller.
  This document only describes MT6360 Type-C Port Switch and Power Delivery controller.

properties:
  compatible:
    enum:
      - mediatek,mt6360-tcpc

  interrupts:
    maxItems: 1

  interrupt-names:
    items:
      - const: PD_IRQB

  connector:
    type: object
    $ref: ../connector/usb-connector.yaml#
    description:
      Properties for usb c connector.

additionalProperties: false

required:
  - compatible
  - interrupts
  - interrupt-names

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/usb/pd.h>
    i2c0 {
      #address-cells = <1>;
      #size-cells = <0>;

      mt6360@34 {
        compatible = "mediatek,mt6360";
        reg = <0x34>;
        interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;
        interrupt-names = "IRQB";
        interrupt-controller;
        #interrupt-cells = <1>;

        tcpc {
          compatible = "mediatek,mt6360-tcpc";
          interrupts-extended = <&gpio26 3 IRQ_TYPE_LEVEL_LOW>;
          interrupt-names = "PD_IRQB";

          connector {
            compatible = "usb-c-connector";
            label = "USB-C";
            data-role = "dual";
            power-role = "dual";
            try-power-role = "sink";
            source-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
            sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
            op-sink-microwatt = <10000000>;

            ports {
              #address-cells = <1>;
              #size-cells = <0>;

              port@0 {
                reg = <0>;
                endpoint {
                  remote-endpoint = <&usb_hs>;
                };
              };
              port@1 {
                reg = <1>;
                endpoint {
                  remote-endpoint = <&usb_ss>;
                };
              };
              port@2 {
                reg = <2>;
                endpoint {
                  remote-endpoint = <&dp_aux>;
                };
              };
            };
          };
        };
      };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/usb/mediatek,mt6370-tcpc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediatTek MT6370 Type-C Port Switch and Power Delivery controller

maintainers:
  - ChiYuan Huang <cy_huang@richtek.com>

description: |
  MediaTek MT6370 is a multi-functional device.
  It integrates charger, ADC, flash, RGB indicators,
  regulators (DSV/VIBLDO), and TypeC Port Switch with Power Delivery controller.
  This document only describes MT6370 Type-C Port Switch and
  Power Delivery controller.

properties:
  compatible:
    enum:
      - mediatek,mt6370-tcpc

  interrupts:
    maxItems: 1

  connector:
    type: object
    $ref: /schemas/connector/usb-connector.yaml#
    unevaluatedProperties: false

additionalProperties: false

required:
  - compatible
  - interrupts


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek USB3 xHCI

maintainers:
  - Chunfeng Yun <chunfeng.yun@mediatek.com>

allOf:
  - $ref: "usb-xhci.yaml"

description: |
  There are two scenarios:
  case 1: only supports xHCI driver;
  case 2: supports dual-role mode, and the host is based on xHCI driver.

properties:
  # common properties for both case 1 and case 2
  compatible:
    items:
      - enum:
          - mediatek,mt2701-xhci
          - mediatek,mt2712-xhci
          - mediatek,mt7622-xhci
          - mediatek,mt7623-xhci
          - mediatek,mt7629-xhci
          - mediatek,mt7986-xhci
          - mediatek,mt8173-xhci
          - mediatek,mt8183-xhci
          - mediatek,mt8186-xhci
          - mediatek,mt8188-xhci
          - mediatek,mt8192-xhci
          - mediatek,mt8195-xhci
      - const: mediatek,mtk-xhci

  reg:
    minItems: 1
    items:
      - description: the registers of xHCI MAC
      - description: the registers of IP Port Control

  reg-names:
    minItems: 1
    items:
      - const: mac
      - const: ippc  # optional, only needed for case 1.

  interrupts:
    description:
      use "interrupts-extended" when the interrupts are connected to the
      separate interrupt controllers
    minItems: 1
    items:
      - description: xHCI host controller interrupt
      - description: optional, wakeup interrupt used to support runtime PM

  interrupt-names:
    minItems: 1
    items:
      - const: host
      - const: wakeup

  power-domains:
    description: A phandle to USB power domain node to control USB's MTCMOS
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: Controller clock used by normal mode
      - description: Reference clock used by low power mode etc
      - description: Mcu bus clock for register access
      - description: DMA bus clock for data transfer
      - description: controller clock

  clock-names:
    minItems: 1
    items:
      - const: sys_ck  # required, the following ones are optional
      - const: ref_ck
      - const: mcu_ck
      - const: dma_ck
      - const: xhci_ck

  assigned-clocks:
    minItems: 1
    maxItems: 5

  assigned-clock-parents:
    minItems: 1
    maxItems: 5

  phys:
    description:
      List of all PHYs used on this HCD, it's better to keep PHYs in order
      as the hardware layout
    minItems: 1
    items:
      - description: USB2/HS PHY    # required, others are optional
      - description: USB3/SS(P) PHY
      - description: USB2/HS PHY
      - description: USB3/SS(P) PHY
      - description: USB2/HS PHY
      - description: USB3/SS(P) PHY
      - description: USB2/HS PHY
      - description: USB3/SS(P) PHY
      - description: USB2/HS PHY

  vusb33-supply:
    description: Regulator of USB AVDD3.3v

  vbus-supply:
    description: Regulator of USB VBUS5v

  resets:
    maxItems: 1

  usb3-lpm-capable: true

  usb2-lpm-disable: true

  imod-interval-ns:
    description:
      Interrupt moderation interval value, it is 8 times as much as that
      defined in the xHCI spec on MTK's controller.
    default: 5000

  # the following properties are only used for case 1
  wakeup-source:
    description: enable USB remote wakeup, see power/wakeup-source.txt
    type: boolean

  mediatek,syscon-wakeup:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1
    description:
      A phandle to syscon used to access the register of the USB wakeup glue
      layer between xHCI and SPM, the field should always be 3 cells long.
    items:
      items:
        - description:
            The first cell represents a phandle to syscon
        - description:
            The second cell represents the register base address of the glue
            layer in syscon
        - description: |
            The third cell represents the hardware version of the glue layer,
            1 - used by mt8173 etc, revision 1 without following IPM rule;
            2 - used by mt2712 etc, revision 2 following IPM rule;
            101 - used by mt8183, specific 1.01;
            102 - used by mt8192, specific 1.02;
            103 - used by mt8195, IP0, specific 1.03;
            104 - used by mt8195, IP1, specific 1.04;
            105 - used by mt8195, IP2, specific 1.05;
            106 - used by mt8195, IP3, specific 1.06;
          enum: [1, 2, 101, 102, 103, 104, 105, 106]

  mediatek,u3p-dis-msk:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The mask to disable u3ports, bit0 for u3port0,
      bit1 for u3port1, ... etc

  mediatek,u2p-dis-msk:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The mask to disable u2ports, bit0 for u2port0,
      bit1 for u2port1, ... etc

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

patternProperties:
  "@[0-9a-f]{1}$":
    type: object
    description: The hard wired USB devices.

dependencies:
  wakeup-source: [ 'mediatek,syscon-wakeup' ]

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/power/mt8173-power.h>

    usb@11270000 {
        compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
        reg = <0x11270000 0x1000>, <0x11280700 0x0100>;
        reg-names = "mac", "ippc";
        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
        power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
        clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
        clock-names = "sys_ck", "ref_ck";
        phys = <&u3port0 PHY_TYPE_USB3>, <&u2port1 PHY_TYPE_USB2>;
        vusb33-supply = <&mt6397_vusb_reg>;
        vbus-supply = <&usb_p1_vbus>;
        imod-interval-ns = <10000>;
        mediatek,syscon-wakeup = <&pericfg 0x400 1>;
        wakeup-source;
        usb3-lpm-capable;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/mediatek,mtu3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek USB3 DRD Controller

maintainers:
  - Chunfeng Yun <chunfeng.yun@mediatek.com>

allOf:
  - $ref: "usb-drd.yaml"

description: |
  The DRD controller has a glue layer IPPC (IP Port Control), and its host is
  based on xHCI.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt2712-mtu3
          - mediatek,mt8173-mtu3
          - mediatek,mt8183-mtu3
          - mediatek,mt8186-mtu3
          - mediatek,mt8188-mtu3
          - mediatek,mt8192-mtu3
          - mediatek,mt8195-mtu3
      - const: mediatek,mtu3

  reg:
    items:
      - description: the registers of device MAC
      - description: the registers of IP Port Control

  reg-names:
    items:
      - const: mac
      - const: ippc

  interrupts:
    description:
      use "interrupts-extended" when the interrupts are connected to the
      separate interrupt controllers
    minItems: 1
    items:
      - description: SSUSB device controller interrupt
      - description: optional, wakeup interrupt used to support runtime PM

  interrupt-names:
    items:
      - const: device
      - const: wakeup

  power-domains:
    description: A phandle to USB power domain node to control USB's MTCMOS
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: Controller clock used by normal mode
      - description: Reference clock used by low power mode etc
      - description: Mcu bus clock for register access
      - description: DMA bus clock for data transfer

  clock-names:
    minItems: 1
    items:
      - const: sys_ck  # required, others are optional
      - const: ref_ck
      - const: mcu_ck
      - const: dma_ck

  phys:
    description:
      List of all the USB PHYs used, it's better to keep the sequence
      as the hardware layout.
    minItems: 1
    items:
      - description: USB2/HS PHY    # required, others are optional
      - description: USB3/SS(P) PHY
      - description: USB2/HS PHY    # the following for backward compatible
      - description: USB3/SS(P) PHY
      - description: USB2/HS PHY
      - description: USB3/SS(P) PHY
      - description: USB2/HS PHY
      - description: USB3/SS(P) PHY
      - description: USB2/HS PHY

  vusb33-supply:
    description: Regulator of USB AVDD3.3v

  vbus-supply:
    deprecated: true
    description: |
      Regulator of USB VBUS5v, needed when supports dual-role mode.
      Particularly, if use an output GPIO to control a VBUS regulator, should
      model it as a regulator. See bindings/regulator/fixed-regulator.yaml
      It's considered valid for compatibility reasons, not allowed for
      new bindings, and put into a usb-connector node.

  dr_mode:
    enum: [host, peripheral, otg]
    default: otg

  maximum-speed:
    enum: [super-speed-plus, super-speed, high-speed, full-speed]

  resets:
    maxItems: 1

  "#address-cells":
    enum: [1, 2]

  "#size-cells":
    enum: [1, 2]

  ranges: true

  extcon:
    deprecated: true
    description: |
      Phandle to the extcon device detecting the IDDIG state, needed
      when supports dual-role mode.
      It's considered valid for compatibility reasons, not allowed for
      new bindings, and use "usb-role-switch" property instead.

  usb-role-switch:
    $ref: /schemas/types.yaml#/definitions/flag
    description: Support role switch.
    type: boolean

  role-switch-default-mode:
    enum: [host, peripheral]
    default: host

  connector:
    $ref: /schemas/connector/usb-connector.yaml#
    description:
      Connector for dual role switch, especially for "gpio-usb-b-connector"
    type: object

  port:
    description:
      Any connector to the data bus of this controller should be modelled
      using the OF graph bindings specified, if the "usb-role-switch"
      property is used. See graph.txt
    $ref: /schemas/graph.yaml#/properties/port

  enable-manual-drd:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      supports manual dual-role switch via debugfs; usually used when
      receptacle is TYPE-A and also wants to support dual-role mode.
    type: boolean

  wakeup-source:
    description: enable USB remote wakeup, see power/wakeup-source.txt
    type: boolean

  mediatek,syscon-wakeup:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1
    description:
      A phandle to syscon used to access the register of the USB wakeup glue
      layer between xHCI and SPM, the field should always be 3 cells long.
    items:
      items:
        - description:
            The first cell represents a phandle to syscon
        - description:
            The second cell represents the register base address of the glue
            layer in syscon
        - description: |
            The third cell represents the hardware version of the glue layer,
            1 - used by mt8173 etc, revision 1 without following IPM rule;
            2 - used by mt2712 etc, revision 2 with following IPM rule;
            101 - used by mt8183, specific 1.01;
            102 - used by mt8192, specific 1.02;
          enum: [1, 2, 101, 102]

  mediatek,u3p-dis-msk:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The mask to disable u3ports, bit0 for u3port0,
      bit1 for u3port1, ... etc

  mediatek,u2p-dis-msk:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The mask to disable u2ports, bit0 for u2port0,
      bit1 for u2port1, ... etc; but can't disable u2port0 if dual role mode
      is enabled, so will be skipped in this case.

# Required child node when support dual-role
patternProperties:
  "^usb@[0-9a-f]+$":
    type: object
    $ref: /schemas/usb/mediatek,mtk-xhci.yaml#
    description:
      The xhci should be added as subnode to mtu3 as shown in the following
      example if the host mode is enabled.

dependencies:
  connector: [ 'usb-role-switch' ]
  port: [ 'usb-role-switch' ]
  role-switch-default-mode: [ 'usb-role-switch' ]
  wakeup-source: [ 'mediatek,syscon-wakeup' ]

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  # Dual role switch by extcon
  - |
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/power/mt8173-power.h>

    usb@11271000 {
        compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
        reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
        reg-names = "mac", "ippc";
        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
        phys = <&phy_port0 PHY_TYPE_USB3>, <&phy_port1 PHY_TYPE_USB2>;
        power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
        clocks = <&topckgen CLK_TOP_USB30_SEL>;
        clock-names = "sys_ck";
        vusb33-supply = <&mt6397_vusb_reg>;
        vbus-supply = <&usb_p0_vbus>;
        extcon = <&extcon_usb>;
        dr_mode = "otg";
        wakeup-source;
        mediatek,syscon-wakeup = <&pericfg 0x400 1>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        xhci: usb@11270000 {
            compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
            reg = <0x11270000 0x1000>;
            reg-names = "mac";
            interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
            clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
            clock-names = "sys_ck", "ref_ck";
            vusb33-supply = <&mt6397_vusb_reg>;
        };
    };

  # Dual role switch by gpio-usb-b-connector
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/power/mt2712-power.h>

    usb@112c1000 {
        compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
        reg = <0x112c1000 0x3000>, <0x112d0700 0x0100>;
        reg-names = "mac", "ippc";
        interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>;
        phys = <&u2port2 PHY_TYPE_USB2>;
        power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
        clocks = <&topckgen CLK_TOP_USB30_SEL>;
        clock-names = "sys_ck";
        dr_mode = "otg";
        usb-role-switch;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        host0: usb@11270000 {
            compatible = "mediatek,mt2712-xhci", "mediatek,mtk-xhci";
            reg = <0x11270000 0x1000>;
            reg-names = "mac";
            interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
            clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
            clock-names = "sys_ck", "ref_ck";
        };

        connector {
            compatible = "gpio-usb-b-connector", "usb-b-connector";
            type = "micro";
            id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
            vbus-supply = <&usb_p0_vbus>;
        };
    };

  # Dual role switch with type-c
  - |
    usb@11201000 {
        compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
        reg = <0x11201000 0x2e00>, <0x11203e00 0x0100>;
        reg-names = "mac", "ippc";
        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
        phys = <&u2port0 PHY_TYPE_USB2>;
        clocks = <&clk26m>;
        clock-names = "sys_ck";
        mediatek,syscon-wakeup = <&pericfg 0x400 1>;
        wakeup-source;
        dr_mode = "otg";
        usb-role-switch;
        role-switch-default-mode = "host";
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        host: usb@11200000 {
            compatible = "mediatek,mt8183-xhci", "mediatek,mtk-xhci";
            reg = <0x11200000 0x1000>;
            reg-names = "mac";
            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
            clocks = <&clk26m>;
            clock-names = "sys_ck";
        };

        port {
            usb_role_sw: endpoint {
                remote-endpoint = <&hs_ep>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/mediatek,musb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek MUSB DRD/OTG Controller

maintainers:
  - Min Guo <min.guo@mediatek.com>

properties:
  $nodename:
    pattern: '^usb@[0-9a-f]+$'

  compatible:
    items:
      - enum:
          - mediatek,mt8516-musb
          - mediatek,mt2701-musb
          - mediatek,mt7623-musb
      - const: mediatek,mtk-musb

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-names:
    items:
      - const: mc

  clocks:
    items:
      - description: The main/core clock
      - description: The system bus clock
      - description: The 48Mhz clock

  clock-names:
    items:
      - const: main
      - const: mcu
      - const: univpll

  phys:
    maxItems: 1

  usb-role-switch:
    $ref: /schemas/types.yaml#/definitions/flag
    description: Support role switch. See usb/generic.txt
    type: boolean

  dr_mode:
    enum:
      - host
      - otg
      - peripheral

  power-domains:
    description: A phandle to USB power domain node to control USB's MTCMOS
    maxItems: 1

  connector:
    $ref: /schemas/connector/usb-connector.yaml#
    description: Connector for dual role switch
    type: object

dependencies:
  usb-role-switch: [ 'connector' ]
  connector: [ 'usb-role-switch' ]

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - phys
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt2701-clk.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/power/mt2701-power.h>

    usb@11200000 {
        compatible = "mediatek,mt2701-musb", "mediatek,mtk-musb";
        reg = <0x11200000 0x1000>;
        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
        interrupt-names = "mc";
        phys = <&u2port2 PHY_TYPE_USB2>;
        dr_mode = "otg";
        clocks = <&pericfg CLK_PERI_USB0>,
                 <&pericfg CLK_PERI_USB0_MCU>,
                 <&pericfg CLK_PERI_USB_SLV>;
        clock-names = "main","mcu","univpll";
        power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
        usb-role-switch;

        connector {
            compatible = "gpio-usb-b-connector", "usb-b-connector";
            type = "micro";
            id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
            vbus-supply = <&usb_vbus>;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip MPFS USB Controller

allOf:
  - $ref: usb-drd.yaml#

maintainers:
  - Conor Dooley <conor.dooley@microchip.com>

properties:
  compatible:
    enum:
      - microchip,mpfs-musb

  dr_mode: true

  reg:
    maxItems: 1

  interrupts:
    minItems: 2
    maxItems: 2

  interrupt-names:
    items:
      - const: dma
      - const: mc

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks

additionalProperties: false

examples:
  - |
    #include "dt-bindings/clock/microchip,mpfs-clock.h"
    usb@20201000 {
        compatible = "microchip,mpfs-musb";
        reg = <0x20201000 0x1000>;
        clocks = <&clkcfg CLK_USB>;
        interrupt-parent = <&plic>;
        interrupts = <86>, <87>;
        interrupt-names = "dma", "mc";
        dr_mode = "host";
    };

...


code:
MSM SoC HSUSB controllers

EHCI

Required properties:
- compatible:	Should contain "qcom,ehci-host"
- regs:			offset and length of the register set in the memory map
- usb-phy:		phandle for the PHY device

Example EHCI controller device node:

	ehci: ehci@f9a55000 {
		compatible = "qcom,ehci-host";
		reg = <0xf9a55000 0x400>;
		usb-phy = <&usb_otg>;
	};

USB PHY with optional OTG:

Required properties:
- compatible:   Should contain:
  "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
  "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY

- regs:         Offset and length of the register set in the memory map
- interrupts:   interrupt-specifier for the OTG interrupt.

- clocks:       A list of phandle + clock-specifier pairs for the
                clocks listed in clock-names
- clock-names:  Should contain the following:
  "phy"         USB PHY reference clock
  "core"        Protocol engine clock
  "iface"       Interface bus clock
  "alt_core"    Protocol engine clock for targets with asynchronous
                reset methodology. (optional)

- vdccx-supply: phandle to the regulator for the vdd supply for
                digital circuit operation.
- v1p8-supply:  phandle to the regulator for the 1.8V supply
- v3p3-supply:  phandle to the regulator for the 3.3V supply

- resets:       A list of phandle + reset-specifier pairs for the
                resets listed in reset-names
- reset-names:  Should contain the following:
  "phy"         USB PHY controller reset
  "link"        USB LINK controller reset

- qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
                1 - PHY control
                2 - PMIC control

Optional properties:
- dr_mode:      One of "host", "peripheral" or "otg". Defaults to "otg"

- switch-gpio:  A phandle + gpio-specifier pair. Some boards are using Dual
                SPDT USB Switch, witch is cotrolled by GPIO to de/multiplex
                D+/D- USB lines between connectors.

- qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
                Mode Eye Diagram test. Start address at which these values will be
                written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as
                "do not overwrite default value at this address".
                For example: qcom,phy-init-sequence = < -1 0x63 >;
                Will update only value at address ULPI_EXT_VENDOR_SPECIFIC + 1.

- qcom,phy-num: Select number of pyco-phy to use, can be one of
                0 - PHY one, default
                1 - Second PHY
                Some platforms may have configuration to allow USB
                controller work with any of the two HSPHYs present.

- qcom,vdd-levels: This property must be a list of three integer values
                (no, min, max) where each value represents either a voltage
                in microvolts or a value corresponding to voltage corner.

- qcom,manual-pullup: If present, vbus is not routed to USB controller/phy
                and controller driver therefore enables pull-up explicitly
                before starting controller using usbcmd run/stop bit.

- extcon:       phandles to external connector devices. First phandle
                should point to external connector, which provide "USB"
                cable events, the second should point to external connector
                device, which provide "USB-HOST" cable events. If one of
                the external connector devices is not required empty <0>
                phandle should be specified.

Example HSUSB OTG controller device node:

    usb@f9a55000 {
        compatible = "qcom,usb-otg-snps";
        reg = <0xf9a55000 0x400>;
        interrupts = <0 134 0>;
        dr_mode = "peripheral";

        clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
                <&gcc GCC_USB_HS_AHB_CLK>;

        clock-names = "phy", "core", "iface";

        vddcx-supply = <&pm8841_s2_corner>;
        v1p8-supply = <&pm8941_l6>;
        v3p3-supply = <&pm8941_l24>;

        resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
        reset-names = "phy", "link";

        qcom,otg-control = <1>;
        qcom,phy-init-sequence = < -1 0x63 >;
        qcom,vdd-levels = <1 5 7>;
	};


code:
Nuvoton NPCM7XX SoC USB controllers:
-----------------------------

EHCI:
-----

Required properties:
- compatible: should be one of
    "nuvoton,npcm750-ehci"
    "nuvoton,npcm845-ehci"
- interrupts: Should contain the EHCI interrupt
- reg:        Physical address and length of the register set for the device

Example:

	ehci1: usb@f0806000 {
		compatible = "nuvoton,npcm750-ehci";
		reg = <0xf0806000 0x1000>;
		interrupts = <0 61 4>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Device tree binding for NVIDIA Tegra XUSB device mode controller (XUDC)

description:
  The Tegra XUDC controller supports both USB 2.0 HighSpeed/FullSpeed and
  USB 3.0 SuperSpeed protocols.

maintainers:
  - Nagarjuna Kristam <nkristam@nvidia.com>
  - JC Kuo <jckuo@nvidia.com>
  - Thierry Reding <treding@nvidia.com>

properties:
  compatible:
    items:
      - enum:
          - nvidia,tegra210-xudc # For Tegra210
          - nvidia,tegra186-xudc # For Tegra186
          - nvidia,tegra194-xudc # For Tegra194

  reg:
    minItems: 2
    items:
      - description: XUSB device controller registers
      - description: XUSB device PCI Config registers
      - description: XUSB device registers.

  reg-names:
    minItems: 2
    items:
      - const: base
      - const: fpci
      - const: ipfs

  interrupts:
    maxItems: 1
    description: Must contain the XUSB device interrupt.

  clocks:
    minItems: 4
    items:
      - description: Clock to enable core XUSB dev clock.
      - description: Clock to enable XUSB super speed clock.
      - description: Clock to enable XUSB super speed dev clock.
      - description: Clock to enable XUSB high speed dev clock.
      - description: Clock to enable XUSB full speed dev clock.

  clock-names:
    minItems: 4
    items:
      - const: dev
      - const: ss
      - const: ss_src
      - const: fs_src
      - const: hs_src

  interconnects:
    items:
      - description: memory read client
      - description: memory write client

  interconnect-names:
    items:
      - const: dma-mem # read
      - const: write

  iommus:
    maxItems: 1

  power-domains:
    items:
      - description: XUSBB(device) power-domain
      - description: XUSBA(superspeed) power-domain

  power-domain-names:
    items:
      - const: dev
      - const: ss

  nvidia,xusb-padctl:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle to the XUSB pad controller that is used to configure the USB pads
      used by the XUDC controller.

  phys:
    minItems: 1
    description:
      Must contain an entry for each entry in phy-names.
      See ../phy/phy-bindings.txt for details.

  phy-names:
    minItems: 1
    items:
      - const: usb2-0
      - const: usb2-1
      - const: usb2-2
      - const: usb2-3
      - const: usb3-0
      - const: usb3-1
      - const: usb3-2
      - const: usb3-3

  avddio-usb-supply:
    description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.

  hvdd-usb-supply:
    description: USB controller power supply. Must supply 3.3 V.

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names
  - power-domains
  - power-domain-names
  - nvidia,xusb-padctl
  - phys
  - phy-names

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra210-xudc
    then:
      properties:
        reg:
          minItems: 3
        reg-names:
          minItems: 3
        clocks:
          minItems: 5
        clock-names:
          minItems: 5
      required:
        - avddio-usb-supply
        - hvdd-usb-supply

  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra186-xudc
              - nvidia,tegra194-xudc
    then:
      properties:
        reg:
          maxItems: 2
        reg-names:
          maxItems: 2
        clocks:
          maxItems: 4
        clock-names:
          maxItems: 4

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/gpio/tegra-gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    usb@700d0000 {
        compatible = "nvidia,tegra210-xudc";
        reg = <0x700d0000 0x8000>,
              <0x700d8000 0x1000>,
              <0x700d9000 0x1000>;
        reg-names = "base", "fpci", "ipfs";

        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
                 <&tegra_car TEGRA210_CLK_XUSB_SS>,
                 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
                 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
                 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
        clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";

        power-domains = <&pd_xusbdev>, <&pd_xusbss>;
        power-domain-names = "dev", "ss";

        nvidia,xusb-padctl = <&padctl>;

        phys = <&micro_b>;
        phy-names = "usb2-0";

        avddio-usb-supply = <&vdd_pex_1v05>;
        hvdd-usb-supply = <&vdd_3v3_sys>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra124 xHCI controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
  exposed by the Tegra XUSB pad controller.

properties:
  # required
  compatible:
    oneOf:
      - description: NVIDIA Tegra124
        const: nvidia,tegra124-xusb

      - description: NVIDIA Tegra132
        items:
          - const: nvidia,tegra132-xusb
          - const: nvidia,tegra124-xusb

  reg:
    items:
      - description: base and length of the xHCI host registers
      - description: base and length of the XUSB FPCI registers
      - description: base and length of the XUSB IPFS registers

  reg-names:
    items:
      - const: hcd
      - const: fpci
      - const: ipfs

  interrupts:
    items:
      - description: xHCI host interrupt
      - description: mailbox interrupt

  clocks:
    items:
      - description: XUSB host clock
      - description: XUSB host source clock
      - description: XUSB Falcon source clock
      - description: XUSB SuperSpeed clock
      - description: XUSB SuperSpeed clock divider
      - description: XUSB SuperSpeed source clock
      - description: XUSB HighSpeed clock source
      - description: XUSB FullSpeed clock source
      - description: USB PLL
      - description: reference clock
      - description: I/O PLL

  clock-names:
    items:
      - const: xusb_host
      - const: xusb_host_src
      - const: xusb_falcon_src
      - const: xusb_ss
      - const: xusb_ss_div2
      - const: xusb_ss_src
      - const: xusb_hs_src
      - const: xusb_fs_src
      - const: pll_u_480m
      - const: clk_m
      - const: pll_e

  resets:
    items:
      - description: reset for the XUSB host controller
      - description: reset for the SuperSpeed logic
      - description: shared reset for xusb_{ss,hs,fs,falcon,host}_src.

  reset-names:
    items:
      - const: xusb_host
      - const: xusb_ss
      - const: xusb_src

  nvidia,xusb-padctl:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle to the XUSB pad controller that is used to configure
      the USB pads used by the XHCI controller

  # optional
  phys:
    minItems: 1
    maxItems: 7

  phy-names:
    minItems: 1
    maxItems: 7
    items:
      enum:
        - usb2-0
        - usb2-1
        - usb2-2
        - hsic-0
        - hsic-1
        - usb3-0
        - usb3-1

  avddio-pex-supply:
    description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.

  dvddio-pex-supply:
    description: PCIe/USB3 digital logic power supply. Must supply 1.05 V.

  avdd-usb-supply:
    description: USB controller power supply. Must supply 3.3 V.

  avdd-pll-utmip-supply:
    description: UTMI PLL power supply. Must supply 1.8 V.

  avdd-pll-erefe-supply:
    description: PLLE reference PLL power supply. Must supply 1.05 V.

  avdd-usb-ss-pll-supply:
    description: PCIe/USB3 PLL power supply. Must supply 1.05 V.

  hvdd-usb-ss-supply:
    description: High-voltage PCIe/USB3 power supply. Must supply 3.3 V.

  hvdd-usb-ss-pll-e-supply:
    description: High-voltage PLLE power supply. Must supply 3.3 V.

allOf:
  - $ref: usb-xhci.yaml

unevaluatedProperties: false

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names
  - resets
  - reset-names
  - nvidia,xusb-padctl
  - phys
  - phy-names
  - avddio-pex-supply
  - dvddio-pex-supply
  - avdd-usb-supply
  - hvdd-usb-ss-supply

examples:
  - |
    #include <dt-bindings/clock/tegra124-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    usb@70090000 {
        compatible = "nvidia,tegra124-xusb";
        reg = <0x70090000 0x8000>,
              <0x70098000 0x1000>,
              <0x70099000 0x1000>;
        reg-names = "hcd", "fpci", "ipfs";

        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
                 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
                 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
                 <&tegra_car TEGRA124_CLK_XUSB_SS>,
                 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
                 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
                 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
                 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
                 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
                 <&tegra_car TEGRA124_CLK_CLK_M>,
                 <&tegra_car TEGRA124_CLK_PLL_E>;
        clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src",
                      "xusb_ss", "xusb_ss_div2", "xusb_ss_src",
                      "xusb_hs_src", "xusb_fs_src", "pll_u_480m",
                      "clk_m", "pll_e";
        resets = <&tegra_car 89>, <&tegra_car 156>, <&tegra_car 143>;
        reset-names = "xusb_host", "xusb_ss", "xusb_src";

        nvidia,xusb-padctl = <&padctl>;

        phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* mini-PCIe USB */
               <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB A */
               <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB A */
        phy-names = "usb2-1", "usb2-2", "usb3-0";

        avddio-pex-supply = <&vdd_1v05_run>;
        dvddio-pex-supply = <&vdd_1v05_run>;
        avdd-usb-supply = <&vdd_3v3_lp0>;
        avdd-pll-utmip-supply = <&vddio_1v8>;
        avdd-pll-erefe-supply = <&avdd_1v05_run>;
        avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
        hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
        hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
    };