code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,gpmc-onenand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: OneNAND over Texas Instruments GPMC bus.

maintainers:
  - Tony Lindgren <tony@atomide.com>
  - Roger Quadros <rogerq@kernel.org>

description:
  GPMC connected OneNAND (found on OMAP boards) are represented
  as child nodes of the GPMC controller.

properties:
  $nodename:
    pattern: "^onenand@[0-9],[0,9]$"

  compatible:
    const: ti,omap2-onenand

  reg:
    items:
      - description: |
          Chip Select number, register offset and size of
          OneNAND register window.

  "#address-cells": true

  "#size-cells": true

  int-gpios:
    description: GPIO specifier for the INT pin.

patternProperties:
  "@[0-9a-f]+$":
    $ref: "/schemas/mtd/partitions/partition.yaml"

allOf:
  - $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml"

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"

unevaluatedProperties: false

examples:
  - |
    gpmc: memory-controller@6e000000 {
      compatible = "ti,omap3430-gpmc";
      reg = <0x6e000000 0x02d0>;
      interrupts = <20>;
      gpmc,num-cs = <8>;
      gpmc,num-waitpins = <4>;
      clocks = <&l3s_clkctrl>;
      clock-names = "fck";
      #address-cells = <2>;
      #size-cells = <1>;

      ranges = <0 0 0x01000000 0x01000000>,   /* 16 MB for OneNAND */
               <1 0 0x02000000 0x01000000>;   /* 16 MB for smc91c96 */

      onenand@0,0 {
        compatible = "ti,omap2-onenand";
        reg = <0 0 0x20000>;    /* CS0, offset 0, IO size 128K */
        #address-cells = <1>;
        #size-cells = <1>;

        partition@0 {
          label = "bootloader";
          reg = <0x00000000 0x00100000>;
        };

        partition@100000 {
          label = "config";
          reg = <0x00100000 0x002c0000>;
        };
      };
    };


code:
Freescale's NAND flash controller (NFC)

This variant of the Freescale NAND flash controller (NFC) can be found on
Vybrid (vf610), MPC5125, MCF54418 and Kinetis K70.

Required properties:
- compatible: Should be set to "fsl,vf610-nfc".
- reg: address range of the NFC.
- interrupts: interrupt of the NFC.
- #address-cells: shall be set to 1. Encode the nand CS.
- #size-cells : shall be set to 0.
- assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
- assigned-clock-rates: The NAND bus timing is derived from this clock
    rate and should not exceed maximum timing for any NAND memory chip
    in a board stuffing. Typical NAND memory timings derived from this
    clock are found in the SoC hardware reference manual. Furthermore,
    there might be restrictions on maximum rates when using hardware ECC.

- #address-cells, #size-cells : Must be present if the device has sub-nodes
  representing partitions.

Required children nodes:
Children nodes represent the available nand chips. Currently the driver can
only handle one NAND chip.

Required properties:
- compatible: Should be set to "fsl,vf610-nfc-cs".
- nand-bus-width: see nand-controller.yaml
- nand-ecc-mode: see nand-controller.yaml

Required properties for hardware ECC:
- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
- nand-ecc-step-size: step size equals page size, currently only 2k pages are
    supported
- nand-on-flash-bbt: see nand-controller.yaml

Example:

	nfc: nand@400e0000 {
		compatible = "fsl,vf610-nfc";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x400e0000 0x4000>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks VF610_CLK_NFC>;
		clock-names = "nfc";
		assigned-clocks = <&clks VF610_CLK_NFC>;
		assigned-clock-rates = <33000000>;

		nand@0 {
			compatible = "fsl,vf610-nfc-nandcs";
			reg = <0>;
			nand-bus-width = <8>;
			nand-ecc-mode = "hw";
			nand-ecc-strength = <32>;
			nand-ecc-step-size = <2048>;
			nand-on-flash-bbt;
		};
	};

repo_name: angery/linux


code:
Bindings for Analog Devices ADG792A/G Triple 4:1 Multiplexers

Required properties:
- compatible : "adi,adg792a" or "adi,adg792g"
- #mux-control-cells : <0> if parallel (the three muxes are bound together
  with a single mux controller controlling all three muxes), or <1> if
  not (one mux controller for each mux).
* Standard mux-controller bindings as described in mux-controller.yaml

Optional properties for ADG792G:
- gpio-controller : if present, #gpio-cells below is required.
- #gpio-cells : should be <2>
			  - First cell is the GPO line number, i.e. 0 or 1
			  - Second cell is used to specify active high (0)
			    or active low (1)

Optional properties:
- idle-state : if present, array of states that the mux controllers will have
  when idle. The special state MUX_IDLE_AS_IS is the default and
  MUX_IDLE_DISCONNECT is also supported.

States 0 through 3 correspond to signals A through D in the datasheet.

Example:

	/*
	 * Three independent mux controllers (of which one is used).
	 * Mux 0 is disconnected when idle, mux 1 idles in the previously
	 * selected state and mux 2 idles with signal B.
	 */
	&i2c0 {
		mux: mux-controller@50 {
			compatible = "adi,adg792a";
			reg = <0x50>;
			#mux-control-cells = <1>;

			idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 1>;
		};
	};

	adc-mux {
		compatible = "io-channel-mux";
		io-channels = <&adc 0>;
		io-channel-names = "parent";

		mux-controls = <&mux 2>;

		channels = "sync-1", "", "out";
	};

	/*
	 * Three parallel muxes with one mux controller, useful e.g. if
	 * the adc is differential, thus needing two signals to be muxed
	 * simultaneously for correct operation.
	 */
	&i2c0 {
		pmux: mux-controller@50 {
			compatible = "adi,adg792a";
			reg = <0x50>;
			#mux-control-cells = <0>;

			idle-state = <1>;
		};
	};

	diff-adc-mux {
		compatible = "io-channel-mux";
		io-channels = <&adc 0>;
		io-channel-names = "parent";

		mux-controls = <&pmux>;

		channels = "sync-1", "", "out";
	};


code:
Bindings for Analog Devices ADGS1408/1409 8:1/Dual 4:1 Mux

Required properties:
- compatible : Should be one of
	* "adi,adgs1408"
	* "adi,adgs1409"
* Standard mux-controller bindings as described in mux-controller.yaml

Optional properties for ADGS1408/1409:
- gpio-controller : if present, #gpio-cells is required.
- #gpio-cells : should be <2>
			- First cell is the GPO line number, i.e. 0 to 3
			for ADGS1408 and 0 to 4 for ADGS1409
			- Second cell is used to specify active high (0)
			or active low (1)

Optional properties:
- idle-state : if present, the state that the mux controller will have
  when idle. The special state MUX_IDLE_AS_IS is the default and
  MUX_IDLE_DISCONNECT is also supported.

States 0 through 7 correspond to signals S1 through S8 in the datasheet.
For ADGS1409 only states 0 to 3 are available.

Example:

	/*
	 * One mux controller.
	 * Mux state set to idle as is (no idle-state declared)
	 */
	&spi0 {
		mux: mux-controller@0 {
			compatible = "adi,adgs1408";
			reg = <0>;
			spi-max-frequency = <1000000>;
			#mux-control-cells = <0>;
		};
	}

	adc-mux {
		compatible = "io-channel-mux";
		io-channels = <&adc 1>;
		io-channel-names = "parent";
		mux-controls = <&mux>;

		channels = "out_a0", "out_a1", "test0", "test1",
			"out_b0", "out_b1", "testb0", "testb1";
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: GPIO-based multiplexer controller bindings

maintainers:
  - Peter Rosin <peda@axentia.se>

description: |+
  Define what GPIO pins are used to control a multiplexer. Or several
  multiplexers, if the same pins control more than one multiplexer.

  The multiplexer state is defined as the number represented by the
  multiplexer GPIO pins, where the first pin is the least significant
  bit. An active pin is a binary 1, an inactive pin is a binary 0.

properties:
  compatible:
    const: gpio-mux

  mux-gpios:
    description:
      List of gpios used to control the multiplexer, least significant bit first.

  '#mux-control-cells':
    enum: [ 0, 1 ]

  '#mux-state-cells':
    enum: [ 1, 2 ]

  idle-state:
    default: -1

required:
  - compatible
  - mux-gpios
anyOf:
  - required:
      - "#mux-control-cells"
  - required:
      - "#mux-state-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    mux: mux-controller {
        compatible = "gpio-mux";
        #mux-control-cells = <0>;

        mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
              <&pioA 1 GPIO_ACTIVE_HIGH>;
    };

    adc-mux {
        compatible = "io-channel-mux";
        io-channels = <&adc 0>;
        io-channel-names = "parent";

        mux-controls = <&mux>;

        channels = "sync-1", "in", "out", "sync-2";
    };

    i2c-mux {
        compatible = "i2c-mux";
        i2c-parent = <&i2c1>;

        mux-controls = <&mux>;

        #address-cells = <1>;
        #size-cells = <0>;

        i2c@0 {
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <0>;

            ssd1307: oled@3c {
                reg = <0x3c>;
            };
        };

        i2c@3 {
            reg = <3>;
            #address-cells = <1>;
            #size-cells = <0>;

            pca9555: pca9555@20 {
                reg = <0x20>;
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mux/mux-consumer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common multiplexer controller consumer bindings

maintainers:
  - Peter Rosin <peda@axentia.se>

description: |
  Mux controller consumers should specify a list of mux controllers that they
  want to use with a property containing a 'mux-ctrl-list':

    mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
    single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
    mux-ctrl-phandle : phandle to mux controller node
    mux-ctrl-specifier : array of #mux-control-cells specifying the
                         given mux controller (controller specific)

  Mux controller properties should be named "mux-controls". The exact meaning of
  each mux controller property must be documented in the device tree binding for
  each consumer. An optional property "mux-control-names" may contain a list of
  strings to label each of the mux controllers listed in the "mux-controls"
  property.

  If it is required to provide the state that the mux controller needs to
  be set to, the property "mux-states" must be used. An optional property
  "mux-state-names" can be used to provide a list of strings, to label
  each of the multiplixer states listed in the "mux-states" property.

  Properties "mux-controls" and "mux-states" can be used depending on how
  the consumers want to control the mux controller. If the consumer needs
  needs to set multiple states in a mux controller, then property
  "mux-controls" can be used. If the consumer needs to set the mux
  controller to a given state then property "mux-states" can be used.

  mux-ctrl-specifier typically encodes the chip-relative mux controller number.
  If the mux controller chip only provides a single mux controller, the
  mux-ctrl-specifier can typically be left out.

select: true

properties:
  mux-controls:
    $ref: /schemas/types.yaml#/definitions/phandle-array

  mux-states:
    $ref: /schemas/types.yaml#/definitions/phandle-array

  mux-control-names:
    description:
      Devices that use more than a single mux controller can use the
      "mux-control-names" property to map the name of the requested mux
      controller to an index into the list given by the "mux-controls" property.

  mux-state-names:
    description:
      Devices that use more than a single multiplexer state can use the
      "mux-state-names" property to map the name of the requested mux
      controller to an index into the list given by the "mux-states"
      property.

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mux/mux-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common multiplexer controller provider bindings

maintainers:
  - Peter Rosin <peda@axentia.se>

description: |
  A multiplexer (or mux) controller will have one, or several, consumer devices
  that uses the mux controller. Thus, a mux controller can possibly control
  several parallel multiplexers. Presumably there will be at least one
  multiplexer needed by each consumer, but a single mux controller can of course
  control several multiplexers for a single consumer.

  A mux controller provides a number of states to its consumers, and the state
  space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
  0-7 for an 8-way multiplexer, etc.

  Mux controller nodes
  --------------------

  Mux controller nodes must specify the number of cells used for the
  specifier using the '#mux-control-cells' or '#mux-state-cells' property.
  The value of '#mux-state-cells' will always be one greater than the value
  of '#mux-control-cells'.

  Optionally, mux controller nodes can also specify the state the mux should
  have when it is idle. The idle-state property is used for this. If the
  idle-state is not present, the mux controller is typically left as is when
  it is idle. For multiplexer chips that expose several mux controllers, the
  idle-state property is an array with one idle state for each mux controller.

  The special value (-1) may be used to indicate that the mux should be left
  as is when it is idle. This is the default, but can still be useful for
  mux controller chips with more than one mux controller, particularly when
  there is a need to "step past" a mux controller and set some other idle
  state for a mux controller with a higher index.

  Some mux controllers have the ability to disconnect the input/output of the
  multiplexer. Using this disconnected high-impedance state as the idle state
  is indicated with idle state (-2).

  These constants are available in

        #include <dt-bindings/mux/mux.h>

  as MUX_IDLE_AS_IS (-1) and MUX_IDLE_DISCONNECT (-2).

  An example mux controller node look like this (the adg972a chip is a triple
  4-way multiplexer):

    mux: mux-controller@50 {
      compatible = "adi,adg792a";
      reg = <0x50>;
      #mux-control-cells = <1>;

      idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 2>;
    };

select:
  anyOf:
    - properties:
        $nodename:
          pattern: '^mux-controller'
    - required:
        - '#mux-control-cells'
    - required:
        - '#mux-state-cells'

properties:
  $nodename:
    pattern: '^mux-controller(@.*|-[0-9a-f]+)?$'

  '#mux-control-cells':
    enum: [ 0, 1 ]

  '#mux-state-cells':
    enum: [ 1, 2 ]

  idle-state:
    $ref: /schemas/types.yaml#/definitions/int32
    minimum: -2

  idle-states:
    description: |
      Mux controller nodes can specify the state the mux should have when it is
      idle. If the idle-state is not present, the mux controller is typically
      left as is when it is idle. For multiplexer chips that expose several mux
      controllers, the idle-state property is an array with one idle state for
      each mux controller.

      The special value (-1) may be used to indicate that the mux should be left
      as is when it is idle. This is the default, but can still be useful for
      mux controller chips with more than one mux controller, particularly when
      there is a need to "step past" a mux controller and set some other idle
      state for a mux controller with a higher index.

      Some mux controllers have the ability to disconnect the input/output of the
      multiplexer. Using this disconnected high-impedance state as the idle state
      is indicated with idle state (-2).
    $ref: /schemas/types.yaml#/definitions/int32-array
    items:
      minimum: -2

additionalProperties: true

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    /* One consumer of a 2-way mux controller (one GPIO-line) */
    mux: mux-controller {
        compatible = "gpio-mux";
        #mux-control-cells = <0>;

        mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>;
    };

    adc-mux {
        compatible = "io-channel-mux";
        io-channels = <&adc 0>;
        io-channel-names = "parent";

        mux-controls = <&mux>;
        mux-control-names = "adc";

        channels = "sync", "in";
    };

  - |
    #include <dt-bindings/gpio/gpio.h>

    /*
     * Two consumers (one for an ADC line and one for an i2c bus) of
     * parallel 4-way multiplexers controlled by the same two GPIO-lines.
     */
    mux2: mux-controller {
        compatible = "gpio-mux";
        #mux-control-cells = <0>;

        mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
              <&pioA 1 GPIO_ACTIVE_HIGH>;
    };

    adc-mux {
        compatible = "io-channel-mux";
        io-channels = <&adc 0>;
        io-channel-names = "parent";

        mux-controls = <&mux2>;

        channels = "sync-1", "in", "out", "sync-2";
    };

    i2c-mux {
        compatible = "i2c-mux";
        i2c-parent = <&i2c1>;

        mux-controls = <&mux2>;

        #address-cells = <1>;
        #size-cells = <0>;

        i2c@0 {
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <0>;

            ssd1307: oled@3c {
                reg = <0x3c>;
            };
        };

        i2c@3 {
            reg = <3>;
            #address-cells = <1>;
            #size-cells = <0>;

            pca9555: pca9555@20 {
                reg = <0x20>;
            };
        };
    };

  - |
    #include <dt-bindings/gpio/gpio.h>

    mux1: mux-controller {
        compatible = "gpio-mux";
        #mux-state-cells = <1>;
        mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
    };

    transceiver4: can-phy4 {
        compatible = "ti,tcan1042";
        #phy-cells = <0>;
        max-bitrate = <5000000>;
        standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>;
        mux-states = <&mux1 1>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mux/reg-mux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic register bitfield-based multiplexer controller bindings

maintainers:
  - Peter Rosin <peda@axentia.se>

description: |+
  Define register bitfields to be used to control multiplexers. The parent
  device tree node must be a device node to provide register r/w access.

properties:
  compatible:
    enum:
      - reg-mux   # parent device of mux controller is not syscon device
      - mmio-mux  # parent device of mux controller is syscon device

  reg: true

  '#mux-control-cells':
    const: 1

  mux-reg-masks:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    items:
      items:
        - description: register offset
        - description: pre-shifted bitfield mask
    description: Each entry pair describes a single mux control.

  idle-states: true

required:
  - compatible
  - mux-reg-masks
  - '#mux-control-cells'

additionalProperties: false

examples:
  - |
    /* The parent device of mux controller is not a syscon device. */

    #include <dt-bindings/mux/mux.h>

    mux-controller {
        compatible = "reg-mux";
        #mux-control-cells = <1>;
        mux-reg-masks =
            <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
            <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
    };

    mdio-mux-1 {
        compatible = "mdio-mux-multiplexer";
        mux-controls = <&mux1 0>;
        mdio-parent-bus = <&emdio1>;
        #address-cells = <1>;
        #size-cells = <0>;

        mdio@0 {
            reg = <0x0>;
            #address-cells = <1>;
            #size-cells = <0>;
        };

        mdio@8 {
            reg = <0x8>;
            #address-cells = <1>;
            #size-cells = <0>;
        };
    };

    mdio-mux-2 {
        compatible = "mdio-mux-multiplexer";
        mux-controls = <&mux1 1>;
        mdio-parent-bus = <&emdio2>;
        #address-cells = <1>;
        #size-cells = <0>;

        mdio@0 {
            reg = <0x0>;
            #address-cells = <1>;
            #size-cells = <0>;
        };

        mdio@1 {
            reg = <0x1>;
            #address-cells = <1>;
            #size-cells = <0>;
        };
    };

  - |
    /* The parent device of mux controller is syscon device. */

    #include <dt-bindings/mux/mux.h>
    syscon@1000 {
        reg = <0x1000 0x100>;

        mux2: mux-controller {
            compatible = "mmio-mux";
            #mux-control-cells = <1>;

            mux-reg-masks =
                <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
                <0x3 0x40>; /* 1: reg 0x3, bit 6 */
            idle-states = <MUX_IDLE_AS_IS>, <0>;
        };
    };

    video-mux {
        compatible = "video-mux";
        mux-controls = <&mux2 0>;
        #address-cells = <1>;
        #size-cells = <0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            /* inputs 0..3 */
            port@0 {
                reg = <0>;
            };
            port@1 {
                reg = <1>;
            };
            port@2 {
                reg = <2>;
            };
            port@3 {
                reg = <3>;
            };

            /* output */
            port@4 {
                reg = <4>;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/actions,owl-emac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Actions Semi Owl SoCs Ethernet MAC Controller

maintainers:
  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

description: |
  This Ethernet MAC is used on the Owl family of SoCs from Actions Semi.
  It provides the RMII and SMII interfaces and is compliant with the
  IEEE 802.3 CSMA/CD standard, supporting both half-duplex and full-duplex
  operation modes at 10/100 Mb/s data transfer rates.

allOf:
  - $ref: "ethernet-controller.yaml#"

properties:
  compatible:
    oneOf:
      - const: actions,owl-emac
      - items:
          - enum:
              - actions,s500-emac
          - const: actions,owl-emac

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 2

  clock-names:
    additionalItems: false
    items:
      - const: eth
      - const: rmii

  resets:
    maxItems: 1

  actions,ethcfg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the device containing custom config.

  mdio:
    $ref: mdio.yaml#
    unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - phy-mode
  - phy-handle

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/actions,s500-cmu.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/reset/actions,s500-reset.h>

    ethernet@b0310000 {
        compatible = "actions,s500-emac", "actions,owl-emac";
        reg = <0xb0310000 0x10000>;
        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cmu 59 /*CLK_ETHERNET*/>, <&cmu CLK_RMII_REF>;
        clock-names = "eth", "rmii";
        resets = <&cmu RESET_ETHERNET>;
        phy-mode = "rmii";
        phy-handle = <&eth_phy>;

        mdio {
            #address-cells = <1>;
            #size-cells = <0>;

            eth_phy: ethernet-phy@3 {
                reg = <0x3>;
                interrupt-parent = <&sirq>;
                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/adi,adin.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices ADIN1200/ADIN1300 PHY

maintainers:
  - Alexandru Tachici <alexandru.tachici@analog.com>

description: |
  Bindings for Analog Devices Industrial Ethernet PHYs

allOf:
  - $ref: ethernet-phy.yaml#

properties:
  adi,rx-internal-delay-ps:
    description: |
      RGMII RX Clock Delay used only when PHY operates in RGMII mode with
      internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
    enum: [ 1600, 1800, 2000, 2200, 2400 ]
    default: 2000

  adi,tx-internal-delay-ps:
    description: |
      RGMII TX Clock Delay used only when PHY operates in RGMII mode with
      internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
    enum: [ 1600, 1800, 2000, 2200, 2400 ]
    default: 2000

  adi,fifo-depth-bits:
    description: |
      When operating in RMII mode, this option configures the FIFO depth.
    enum: [ 4, 8, 12, 16, 20, 24 ]
    default: 8

  adi,phy-output-clock:
    description: |
      Select clock output on GP_CLK pin. Two clocks are available:
      A 25MHz reference and a free-running 125MHz.
      The phy can alternatively automatically switch between the reference and
      the 125MHz clocks based on its internal state.
    $ref: /schemas/types.yaml#/definitions/string
    enum:
      - 25mhz-reference
      - 125mhz-free-running
      - adaptive-free-running

  adi,phy-output-reference-clock:
    description: Enable 25MHz reference clock output on CLK25_REF pin.
    type: boolean

unevaluatedProperties: false

examples:
  - |
    ethernet {
        #address-cells = <1>;
        #size-cells = <0>;

        phy-mode = "rgmii-id";

        ethernet-phy@0 {
            reg = <0>;

            adi,rx-internal-delay-ps = <1800>;
            adi,tx-internal-delay-ps = <2200>;
        };
    };
  - |
    ethernet {
        #address-cells = <1>;
        #size-cells = <0>;

        phy-mode = "rmii";

        ethernet-phy@1 {
            reg = <1>;

            adi,fifo-depth-bits = <16>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/adi,adin1110.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ADI ADIN1110 MAC-PHY

maintainers:
  - Alexandru Tachici <alexandru.tachici@analog.com>

description: |
  The ADIN1110 is a low power single port 10BASE-T1L MAC-
  PHY designed for industrial Ethernet applications. It integrates
  an Ethernet PHY core with a MAC and all the associated analog
  circuitry, input and output clock buffering.

  The ADIN2111 is a low power, low complexity, two-Ethernet ports
  switch with integrated 10BASE-T1L PHYs and one serial peripheral
  interface (SPI) port. The device is designed for industrial Ethernet
  applications using low power constrained nodes and is compliant
  with the IEEE 802.3cg-2019 Ethernet standard for long reach
  10 Mbps single pair Ethernet (SPE).

  The device has a 4-wire SPI interface for communication
  between the MAC and host processor.

allOf:
  - $ref: ethernet-controller.yaml#
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

properties:
  compatible:
    enum:
      - adi,adin1110
      - adi,adin2111

  reg:
    maxItems: 1

  adi,spi-crc:
    description: |
      Enable CRC8 checks on SPI read/writes.
    type: boolean

  interrupts:
    maxItems: 1

  reset-gpios:
    maxItems: 1
    description: GPIO connected to active low reset

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    spi {

        #address-cells = <1>;
        #size-cells = <0>;

        ethernet@0 {
            compatible = "adi,adin2111";
            reg = <0>;
            spi-max-frequency = <24500000>;

            adi,spi-crc;

            interrupt-parent = <&gpio>;
            interrupts = <25 IRQ_TYPE_LEVEL_LOW>;

            local-mac-address = [ 00 11 22 33 44 55 ];
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/allwinner,sun4i-a10-emac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 EMAC Ethernet Controller

allOf:
  - $ref: "ethernet-controller.yaml#"

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    const: allwinner,sun4i-a10-emac

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  allwinner,sram:
    description: Phandle to the device SRAM
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to SRAM
          - description: register value for device

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - phy-handle
  - allwinner,sram

unevaluatedProperties: false

examples:
  - |
    emac: ethernet@1c0b000 {
        compatible = "allwinner,sun4i-a10-emac";
        reg = <0x01c0b000 0x1000>;
        interrupts = <55>;
        clocks = <&ahb_gates 17>;
        phy-handle = <&phy0>;
        allwinner,sram = <&emac_sram 1>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/allwinner,sun4i-a10-mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 MDIO Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

allOf:
  - $ref: "mdio.yaml#"

# Select every compatible, including the deprecated ones. This way, we
# will be able to report a warning when we have that compatible, since
# we will validate the node thanks to the select, but won't report it
# as a valid value in the compatible property description
select:
  properties:
    compatible:
      enum:
        - allwinner,sun4i-a10-mdio

        # Deprecated
        - allwinner,sun4i-mdio

  required:
    - compatible

properties:
  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  compatible:
    const: allwinner,sun4i-a10-mdio

  reg:
    maxItems: 1

  phy-supply:
    description: PHY regulator

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    mdio@1c0b080 {
        compatible = "allwinner,sun4i-a10-mdio";
        reg = <0x01c0b080 0x14>;
        #address-cells = <1>;
        #size-cells = <0>;
        phy-supply = <&reg_emac_3v3>;

        phy0: ethernet-phy@0 {
            reg = <0>;
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/allwinner,sun7i-a20-gmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A20 GMAC

allOf:
  - $ref: "snps,dwmac.yaml#"

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    const: allwinner,sun7i-a20-gmac

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-names:
    const: macirq

  clocks:
    items:
      - description: GMAC main clock
      - description: TX clock

  clock-names:
    items:
      - const: stmmaceth
      - const: allwinner_gmac_tx

  phy-supply:
    description:
      PHY regulator

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - phy-mode

unevaluatedProperties: false

examples:
  - |
    gmac: ethernet@1c50000 {
        compatible = "allwinner,sun7i-a20-gmac";
        reg = <0x01c50000 0x10000>;
        interrupts = <0 85 1>;
        interrupt-names = "macirq";
        clocks = <&ahb_gates 49>, <&gmac_tx>;
        clock-names = "stmmaceth", "allwinner_gmac_tx";
        phy-mode = "mii";
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A83t EMAC

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    oneOf:
      - const: allwinner,sun8i-a83t-emac
      - const: allwinner,sun8i-h3-emac
      - const: allwinner,sun8i-r40-gmac
      - const: allwinner,sun8i-v3s-emac
      - const: allwinner,sun50i-a64-emac
      - items:
          - enum:
              - allwinner,sun20i-d1-emac
              - allwinner,sun50i-h6-emac
              - allwinner,sun50i-h616-emac0
          - const: allwinner,sun50i-a64-emac

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-names:
    const: macirq

  clocks:
    maxItems: 1

  clock-names:
    const: stmmaceth

  syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the device containing the EMAC or GMAC clock
      register

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - resets
  - reset-names
  - phy-handle
  - phy-mode
  - syscon

allOf:
  - $ref: "snps,dwmac.yaml#"
  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun8i-a83t-emac
              - allwinner,sun8i-h3-emac
              - allwinner,sun8i-v3s-emac
              - allwinner,sun50i-a64-emac

    then:
      properties:
        allwinner,tx-delay-ps:
          default: 0
          minimum: 0
          maximum: 700
          multipleOf: 100
          description:
            External RGMII PHY TX clock delay chain value in ps.

        allwinner,rx-delay-ps:
          default: 0
          minimum: 0
          maximum: 3100
          multipleOf: 100
          description:
            External RGMII PHY TX clock delay chain value in ps.

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun8i-r40-gmac

    then:
      properties:
        allwinner,rx-delay-ps:
          default: 0
          minimum: 0
          maximum: 700
          multipleOf: 100
          description:
            External RGMII PHY TX clock delay chain value in ps.

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun8i-h3-emac
              - allwinner,sun8i-v3s-emac

    then:
      properties:
        allwinner,leds-active-low:
          $ref: /schemas/types.yaml#/definitions/flag
          description:
            EPHY LEDs are active low.

        mdio-mux:
          type: object
          unevaluatedProperties: false

          properties:
            compatible:
              const: allwinner,sun8i-h3-mdio-mux

            mdio-parent-bus:
              $ref: /schemas/types.yaml#/definitions/phandle
              description:
                Phandle to EMAC MDIO.

            "#address-cells":
              const: 1

            "#size-cells":
              const: 0

            mdio@1:
              $ref: mdio.yaml#
              unevaluatedProperties: false
              description: Internal MDIO Bus

              properties:
                compatible:
                  const: allwinner,sun8i-h3-mdio-internal

                reg:
                  const: 1

              patternProperties:
                "^ethernet-phy@[0-9a-f]$":
                  type: object
                  description:
                    Integrated PHY node

                  properties:
                    clocks:
                      maxItems: 1

                    resets:
                      maxItems: 1

                  required:
                    - clocks
                    - resets

            mdio@2:
              $ref: mdio.yaml#
              unevaluatedProperties: false
              description: External MDIO Bus (H3 only)

              properties:
                reg:
                  const: 2

          required:
            - compatible
            - mdio-parent-bus
            - mdio@1

unevaluatedProperties: false

examples:
  - |
    ethernet@1c0b000 {
        compatible = "allwinner,sun8i-h3-emac";
        syscon = <&syscon>;
        reg = <0x01c0b000 0x104>;
        interrupts = <0 82 1>;
        interrupt-names = "macirq";
        resets = <&ccu 12>;
        reset-names = "stmmaceth";
        clocks = <&ccu 27>;
        clock-names = "stmmaceth";

        phy-handle = <&int_mii_phy>;
        phy-mode = "mii";
        allwinner,leds-active-low;

        mdio1: mdio {
            #address-cells = <1>;
            #size-cells = <0>;
            compatible = "snps,dwmac-mdio";
        };

        mdio-mux {
            compatible = "allwinner,sun8i-h3-mdio-mux";
            #address-cells = <1>;
            #size-cells = <0>;

            mdio-parent-bus = <&mdio1>;

            int_mii_phy: mdio@1 {
                compatible = "allwinner,sun8i-h3-mdio-internal";
                reg = <1>;
                #address-cells = <1>;
                #size-cells = <0>;

                ethernet-phy@1 {
                    reg = <1>;
                    clocks = <&ccu 67>;
                    resets = <&ccu 39>;
                    phy-is-integrated;
                };
            };

            mdio@2 {
                reg = <2>;
                #address-cells = <1>;
                #size-cells = <0>;
            };
        };
    };

  - |
    ethernet@1c0b000 {
        compatible = "allwinner,sun8i-h3-emac";
        syscon = <&syscon>;
        reg = <0x01c0b000 0x104>;
        interrupts = <0 82 1>;
        interrupt-names = "macirq";
        resets = <&ccu 12>;
        reset-names = "stmmaceth";
        clocks = <&ccu 27>;
        clock-names = "stmmaceth";

        phy-handle = <&ext_rgmii_phy>;
        phy-mode = "rgmii";
        allwinner,leds-active-low;

        mdio2: mdio {
            #address-cells = <1>;
            #size-cells = <0>;
            compatible = "snps,dwmac-mdio";
        };

        mdio-mux {
            compatible = "allwinner,sun8i-h3-mdio-mux";
            #address-cells = <1>;
            #size-cells = <0>;
            mdio-parent-bus = <&mdio2>;

            mdio@1 {
                compatible = "allwinner,sun8i-h3-mdio-internal";
                reg = <1>;
                #address-cells = <1>;
                #size-cells = <0>;

                ethernet-phy@1 {
                    reg = <1>;
                    clocks = <&ccu 67>;
                    resets = <&ccu 39>;
                };
            };

            mdio@2 {
                reg = <2>;
                #address-cells = <1>;
                #size-cells = <0>;

                ext_rgmii_phy: ethernet-phy@1 {
                    reg = <1>;
                };
            };
        };
    };

  - |
    ethernet@1c0b000 {
        compatible = "allwinner,sun8i-a83t-emac";
        syscon = <&syscon>;
        reg = <0x01c0b000 0x104>;
        interrupts = <0 82 1>;
        interrupt-names = "macirq";
        resets = <&ccu 13>;
        reset-names = "stmmaceth";
        clocks = <&ccu 27>;
        clock-names = "stmmaceth";
        phy-handle = <&ext_rgmii_phy1>;
        phy-mode = "rgmii";

        mdio {
            compatible = "snps,dwmac-mdio";
            #address-cells = <1>;
            #size-cells = <0>;

            ext_rgmii_phy1: ethernet-phy@1 {
                reg = <1>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/altr,tse.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Altera Triple Speed Ethernet MAC driver (TSE)

maintainers:
  - Maxime Chevallier <maxime.chevallier@bootlin.com>

properties:
  compatible:
    oneOf:
      - const: altr,tse-1.0
      - const: ALTR,tse-1.0
        deprecated: true
      - const: altr,tse-msgdma-1.0

  interrupts:
    minItems: 2

  interrupt-names:
    items:
      - const: rx_irq
      - const: tx_irq

  rx-fifo-depth:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Depth in bytes of the RX FIFO

  tx-fifo-depth:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Depth in bytes of the TX FIFO

  altr,has-supplementary-unicast:
    type: boolean
    description:
      If present, TSE supports additional unicast addresses.

  altr,has-hash-multicast-filter:
    type: boolean
    description:
      If present, TSE supports hash based multicast filter.

  mdio:
    $ref: mdio.yaml#
    unevaluatedProperties: false
    description:
      Creates and registers an MDIO bus.

    properties:
      compatible:
        const: altr,tse-mdio

    required:
      - compatible

required:
  - compatible
  - reg
  - interrupts
  - rx-fifo-depth
  - tx-fifo-depth

allOf:
  - $ref: "ethernet-controller.yaml#"
  - if:
      properties:
        compatible:
          contains:
            enum:
              - const: altr,tse-1.0
              - const: ALTR,tse-1.0
    then:
      properties:
        reg:
          minItems: 4
        reg-names:
          items:
            - const: control_port
            - const: rx_csr
            - const: tx_csr
            - const: s1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - altr,tse-msgdma-1.0
    then:
      properties:
        reg:
          minItems: 6
          maxItems: 7
        reg-names:
          minItems: 6
          items:
            - const: control_port
            - const: rx_csr
            - const: rx_desc
            - const: rx_resp
            - const: tx_csr
            - const: tx_desc
            - const: pcs

unevaluatedProperties: false

examples:
  - |
    tse_sub_0: ethernet@c0100000 {
        compatible = "altr,tse-msgdma-1.0";
        reg = <0xc0100000 0x00000400>,
              <0xc0101000 0x00000020>,
              <0xc0102000 0x00000020>,
              <0xc0103000 0x00000008>,
              <0xc0104000 0x00000020>,
              <0xc0105000 0x00000020>,
              <0xc0106000 0x00000100>;
        reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc", "pcs";
        interrupt-parent = <&intc>;
        interrupts = <0 44 4>,<0 45 4>;
        interrupt-names = "rx_irq","tx_irq";
        rx-fifo-depth = <2048>;
        tx-fifo-depth = <2048>;
        max-frame-size = <1500>;
        local-mac-address = [ 00 00 00 00 00 00 ];
        altr,has-supplementary-unicast;
        altr,has-hash-multicast-filter;
        sfp = <&sfp0>;
        phy-mode = "sgmii";
        managed = "in-band-status";
    };
  - |
    tse_sub_1_eth_tse_0: ethernet@1,00001000 {
        compatible = "altr,tse-msgdma-1.0";
        reg = <0x00001000 0x00000400>,
              <0x00001460 0x00000020>,
              <0x00001480 0x00000020>,
              <0x000014A0 0x00000008>,
              <0x00001400 0x00000020>,
              <0x00001420 0x00000020>;
        reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
        interrupt-parent = <&hps_0_arm_gic_0>;
        interrupts = <0 43 4>, <0 42 4>;
        interrupt-names = "rx_irq", "tx_irq";
        rx-fifo-depth = <2048>;
        tx-fifo-depth = <2048>;
        max-frame-size = <1500>;
        local-mac-address = [ 00 00 00 00 00 00 ];
        phy-mode = "gmii";
        altr,has-supplementary-unicast;
        altr,has-hash-multicast-filter;
        phy-handle = <&phy1>;
        mdio {
            compatible = "altr,tse-mdio";
            #address-cells = <1>;
            #size-cells = <0>;
            phy1: ethernet-phy@1 {
                reg = <0x1>;
            };
        };
    };

...


code:
* AMD 10GbE driver (amd-xgbe)

Required properties:
- compatible: Should be "amd,xgbe-seattle-v1a"
- reg: Address and length of the register sets for the device
   - MAC registers
   - PCS registers
   - SerDes Rx/Tx registers
   - SerDes integration registers (1/2)
   - SerDes integration registers (2/2)
- interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
  listed is required and is the general device interrupt. If the optional
  amd,per-channel-interrupt property is specified, then one additional
  interrupt for each DMA channel supported by the device should be specified.
  The last interrupt listed should be the PCS auto-negotiation interrupt.
- clocks:
   - DMA clock for the amd-xgbe device (used for calculating the
     correct Rx interrupt watchdog timer value on a DMA channel
     for coalescing)
   - PTP clock for the amd-xgbe device
- clock-names: Should be the names of the clocks
   - "dma_clk" for the DMA clock
   - "ptp_clk" for the PTP clock
- phy-mode: See ethernet.txt file in the same directory

Optional properties:
- dma-coherent: Present if dma operations are coherent
- amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate
  a unique interrupt for each DMA channel - this requires an additional
  interrupt be configured for each DMA channel
- amd,speed-set: Speed capabilities of the device
    0 - 1GbE and 10GbE (default)
    1 - 2.5GbE and 10GbE

The MAC address will be determined using the optional properties defined in
ethernet.txt.

The following optional properties are represented by an array with each
value corresponding to a particular speed. The first array value represents
the setting for the 1GbE speed, the second value for the 2.5GbE speed and
the third value for the 10GbE speed.  All three values are required if the
property is used.
- amd,serdes-blwc: Baseline wandering correction enablement
    0 - Off
    1 - On
- amd,serdes-cdr-rate: CDR rate speed selection
- amd,serdes-pq-skew: PQ (data sampling) skew
- amd,serdes-tx-amp: TX amplitude boost
- amd,serdes-dfe-tap-config: DFE taps available to run
- amd,serdes-dfe-tap-enable: DFE taps to enable

Example:
	xgbe@e0700000 {
		compatible = "amd,xgbe-seattle-v1a";
		reg = <0 0xe0700000 0 0x80000>,
		      <0 0xe0780000 0 0x80000>,
		      <0 0xe1240800 0 0x00400>,
		      <0 0xe1250000 0 0x00060>,
		      <0 0xe1250080 0 0x00004>;
		interrupt-parent = <&gic>;
		interrupts = <0 325 4>,
			     <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>,
			     <0 323 4>;
		amd,per-channel-interrupt;
		clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>;
		clock-names = "dma_clk", "ptp_clk";
		phy-mode = "xgmii";
		mac-address = [ 02 a1 a2 a3 a4 a5 ];
		amd,speed-set = <0>;
		amd,serdes-blwc = <1>, <1>, <0>;
		amd,serdes-cdr-rate = <2>, <2>, <7>;
		amd,serdes-pq-skew = <10>, <10>, <30>;
		amd,serdes-tx-amp = <15>, <15>, <10>;
		amd,serdes-dfe-tap-config = <3>, <3>, <1>;
		amd,serdes-dfe-tap-enable = <0>, <0>, <127>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Meson DWMAC Ethernet controller

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>
  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>

# We need a select here so we don't match all nodes with 'snps,dwmac'
select:
  properties:
    compatible:
      contains:
        enum:
          - amlogic,meson6-dwmac
          - amlogic,meson8b-dwmac
          - amlogic,meson8m2-dwmac
          - amlogic,meson-gxbb-dwmac
          - amlogic,meson-axg-dwmac
          - amlogic,meson-g12a-dwmac
  required:
    - compatible

allOf:
  - $ref: "snps,dwmac.yaml#"
  - if:
      properties:
        compatible:
          contains:
            enum:
              - amlogic,meson8b-dwmac
              - amlogic,meson8m2-dwmac
              - amlogic,meson-gxbb-dwmac
              - amlogic,meson-axg-dwmac
              - amlogic,meson-g12a-dwmac

    then:
      properties:
        clocks:
          minItems: 3
          items:
            - description: GMAC main clock
            - description: First parent clock of the internal mux
            - description: Second parent clock of the internal mux
            - description: The clock which drives the timing adjustment logic

        clock-names:
          minItems: 3
          items:
            - const: stmmaceth
            - const: clkin0
            - const: clkin1
            - const: timing-adjustment

        amlogic,tx-delay-ns:
          $ref: /schemas/types.yaml#/definitions/uint32
          description:
            The internal RGMII TX clock delay (provided by this driver) in
            nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns.
            When phy-mode is set to "rgmii" then the TX delay should be
            explicitly configured. When not configured a fallback of 2ns is
            used. When the phy-mode is set to either "rgmii-id" or "rgmii-txid"
            the TX clock delay is already provided by the PHY. In that case
            this property should be set to 0ns (which disables the TX clock
            delay in the MAC to prevent the clock from going off because both
            PHY and MAC are adding a delay).
            Any configuration is ignored when the phy-mode is set to "rmii".

        amlogic,rx-delay-ns:
          deprecated: true
          enum:
            - 0
            - 2
          default: 0
          description:
            The internal RGMII RX clock delay in nanoseconds. Deprecated, use
            rx-internal-delay-ps instead.

        rx-internal-delay-ps:
          default: 0

  - if:
      properties:
        compatible:
          contains:
            enum:
              - amlogic,meson8b-dwmac
              - amlogic,meson8m2-dwmac
              - amlogic,meson-gxbb-dwmac
              - amlogic,meson-axg-dwmac
    then:
      properties:
        rx-internal-delay-ps:
          enum:
            - 0
            - 2000

  - if:
      properties:
        compatible:
          contains:
            enum:
              - amlogic,meson-g12a-dwmac
    then:
      properties:
        rx-internal-delay-ps:
          enum:
            - 0
            - 200
            - 400
            - 600
            - 800
            - 1000
            - 1200
            - 1400
            - 1600
            - 1800
            - 2000
            - 2200
            - 2400
            - 2600
            - 2800
            - 3000

properties:
  compatible:
    additionalItems: true
    maxItems: 3
    items:
      - enum:
          - amlogic,meson6-dwmac
          - amlogic,meson8b-dwmac
          - amlogic,meson8m2-dwmac
          - amlogic,meson-gxbb-dwmac
          - amlogic,meson-axg-dwmac
          - amlogic,meson-g12a-dwmac
    contains:
      enum:
        - snps,dwmac-3.70a
        - snps,dwmac

  reg:
    items:
      - description:
          The first register range should be the one of the DWMAC controller
      - description:
          The second range is is for the Amlogic specific configuration
          (for example the PRG_ETHERNET register range on Meson8b and newer)

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - phy-mode

unevaluatedProperties: false

examples:
  - |
    ethmac: ethernet@c9410000 {
         compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
         reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
         interrupts = <8>;
         interrupt-names = "macirq";
         clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
         clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
         phy-mode = "rgmii";
    };


code:
*  Adaptrum Anarion ethernet controller

This device is a platform glue layer for stmmac.
Please see stmmac.txt for the other unchanged properties.

Required properties:
 - compatible:  Should be "adaptrum,anarion-gmac", "snps,dwmac"
 - phy-mode:    Should be "rgmii". Other modes are not currently supported.

Examples:

	gmac1: ethernet@f2014000 {
		compatible = "adaptrum,anarion-gmac", "snps,dwmac";
		reg = <0xf2014000 0x4000>, <0xf2018100 8>;

		interrupt-parent = <&core_intc>;
		interrupts = <21>;
		interrupt-names = "macirq";

		clocks = <&core_clk>;
		clock-names = "stmmaceth";

		phy-mode = "rgmii";
	};


code:
APM X-Gene SoC Ethernet nodes

Ethernet nodes are defined to describe on-chip ethernet interfaces in
APM X-Gene SoC.

Required properties for all the ethernet interfaces:
- compatible: Should state binding information from the following list,
  - "apm,xgene-enet":    RGMII based 1G interface
  - "apm,xgene1-sgenet": SGMII based 1G interface
  - "apm,xgene1-xgenet": XFI based 10G interface
- reg: Address and length of the register set for the device. It contains the
  information of registers in the same order as described by reg-names
- reg-names: Should contain the register set names
  - "enet_csr": Ethernet control and status register address space
  - "ring_csr": Descriptor ring control and status register address space
  - "ring_cmd": Descriptor ring command register address space
- interrupts: Two interrupt specifiers can be specified.
  - First is the Rx interrupt.  This irq is mandatory.
  - Second is the Tx completion interrupt.
    This is supported only on SGMII based 1GbE and 10GbE interfaces.
- channel: Ethernet to CPU, start channel (prefetch buffer) number
  - Must map to the first irq and irqs must be sequential
- port-id: Port number (0 or 1)
- clocks: Reference to the clock entry.
- local-mac-address: MAC address assigned to this device
- phy-connection-type: Interface type between ethernet device and PHY device

Required properties for ethernet interfaces that have external PHY:
- phy-handle: Reference to a PHY node connected to this device

- mdio: Device tree subnode with the following required properties:
  - compatible: Must be "apm,xgene-mdio".
  - #address-cells: Must be <1>.
  - #size-cells: Must be <0>.

  For the phy on the mdio bus, there must be a node with the following fields:
  - compatible: PHY identifier.  Please refer ./phy.txt for the format.
  - reg: The ID number for the phy.

Optional properties:
- status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok".
- tx-delay: Delay value for RGMII bridge TX clock.
	    Valid values are between 0 to 7, that maps to
	    417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps
	    Default value is 4, which corresponds to 1611 ps
- rx-delay: Delay value for RGMII bridge RX clock.
	    Valid values are between 0 to 7, that maps to
	    273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps
	    Default value is 2, which corresponds to 899 ps
- rxlos-gpios: Input gpio from SFP+ module to indicate availability of
	       incoming signal.

Example:
	menetclk: menetclk {
		compatible = "apm,xgene-device-clock";
		clock-output-names = "menetclk";
		status = "ok";
	};

	menet: ethernet@17020000 {
		compatible = "apm,xgene-enet";
		status = "disabled";
		reg = <0x0 0x17020000 0x0 0xd100>,
		      <0x0 0x17030000 0x0 0x400>,
		      <0x0 0x10000000 0x0 0x200>;
		reg-names = "enet_csr", "ring_csr", "ring_cmd";
		interrupts = <0x0 0x3c 0x4>;
		port-id = <0>;
		clocks = <&menetclk 0>;
		local-mac-address = [00 01 73 00 00 01];
		phy-connection-type = "rgmii";
		phy-handle = <&menetphy>;
		mdio {
			compatible = "apm,xgene-mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			menetphy: menetphy@3 {
				compatible = "ethernet-phy-id001c.c915";
				reg = <0x3>;
			};

		};
	};

/* Board-specific peripheral configurations */
&menet {
	tx-delay = <4>;
	rx-delay = <2>;
        status = "ok";
};


code:
APM X-Gene SoC MDIO node

MDIO node is defined to describe on-chip MDIO controller.

Required properties:
	- compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi"
	- #address-cells: Must be <1>.
	- #size-cells: Must be <0>.
	- reg: Address and length of the register set
	- clocks: Reference to the clock entry

For the phys on the mdio bus, there must be a node with the following fields:
	- compatible: PHY identifier.  Please refer ./phy.txt for the format.
	- reg: The ID number for the phy.

Example:

	mdio: mdio@17020000 {
		compatible = "apm,xgene-mdio-rgmii";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x0 0x17020000 0x0 0xd100>;
		clocks = <&menetclk 0>;
	};

	/* Board-specific peripheral configurations */
	&mdio {
		menetphy: phy@3 {
			reg = <0x3>;
		};
		sgenet0phy: phy@4 {
			reg = <0x4>;
		};
		sgenet1phy: phy@5 {
			reg = <0x5>;
		};
	};


code:
* Synopsys ARC EMAC 10/100 Ethernet driver (EMAC)

Required properties:
- compatible: Should be "snps,arc-emac"
- reg: Address and length of the register set for the device
- interrupts: Should contain the EMAC interrupts
- max-speed: see ethernet.txt file in the same directory.
- phy: see ethernet.txt file in the same directory.

Optional properties:
- phy-reset-gpios : Should specify the gpio for phy reset
- phy-reset-duration : Reset duration in milliseconds.  Should present
  only if property "phy-reset-gpios" is available.  Missing the property
  will have the duration be 1 millisecond.  Numbers greater than 1000 are
  invalid and 1 millisecond will be used instead.

Clock handling:
The clock frequency is needed to calculate and set polling period of EMAC.
It must be provided by one of:
- clock-frequency: CPU frequency.
- clocks: reference to the clock supplying the EMAC.

Child nodes of the driver are the individual PHY devices connected to the
MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.

Examples:

	ethernet@c0fc2000 {
		compatible = "snps,arc-emac";
		reg = <0xc0fc2000 0x3c>;
		interrupts = <6>;
		mac-address = [ 00 11 22 33 44 55 ];

		clock-frequency = <80000000>;
		/* or */
		clocks = <&emac_clock>;

		max-speed = <100>;
		phy = <&phy0>;

		#address-cells = <1>;
		#size-cells = <0>;
		phy0: ethernet-phy@0 {
			reg = <1>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/asix,ax88178.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: The device tree bindings for the USB Ethernet controllers

maintainers:
  - Oleksij Rempel <o.rempel@pengutronix.de>

description: |
  Device tree properties for hard wired USB Ethernet devices.

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - usbb95,1720   # ASIX AX88172
          - usbb95,172a   # ASIX AX88172A
          - usbb95,1780   # ASIX AX88178
          - usbb95,7720   # ASIX AX88772
          - usbb95,772a   # ASIX AX88772A
          - usbb95,772b   # ASIX AX88772B
          - usbb95,7e2b   # ASIX AX88772B

  reg:
    maxItems: 1

  local-mac-address: true
  mac-address: true

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    usb {
        #address-cells = <1>;
        #size-cells = <0>;

        ethernet@1 {
            compatible = "usbb95,7e2b";
            reg = <1>;
            local-mac-address = [00 00 00 00 00 00];
        };
    };
  - |
    usb {
        #address-cells = <1>;
        #size-cells = <0>;

        usb1@1 {
            compatible = "usb1234,5678";
            reg = <1>;
            #address-cells = <1>;
            #size-cells = <0>;

            ethernet@1 {
               compatible = "usbb95,772b";
               reg = <1>;
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/asix,ax88796c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASIX AX88796C SPI Ethernet Adapter

maintainers:
  - Łukasz Stelmach <l.stelmach@samsung.com>

description: |
  ASIX AX88796C is an Ethernet controller with a built in PHY. This
  describes SPI mode of the chip.

  The node for this driver must be a child node of an SPI controller,
  hence all mandatory properties described in
  ../spi/spi-controller.yaml must be specified.

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    const: asix,ax88796c

  reg:
    maxItems: 1

  spi-max-frequency:
    maximum: 40000000

  interrupts:
    maxItems: 1

  reset-gpios:
    description:
      A GPIO line handling reset of the chip. As the line is active low,
      it should be marked GPIO_ACTIVE_LOW.
    maxItems: 1

  local-mac-address: true

  mac-address: true

required:
  - compatible
  - reg
  - spi-max-frequency
  - interrupts
  - reset-gpios

additionalProperties: false

examples:
  # Artik5 eval board
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>
    spi0 {
        #address-cells = <1>;
        #size-cells = <0>;

        ethernet@0 {
            compatible = "asix,ax88796c";
            reg = <0x0>;
            local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */
            interrupt-parent = <&gpx2>;
            interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
            spi-max-frequency = <40000000>;
            reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-or-later
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/aspeed,ast2600-mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED AST2600 MDIO Controller

maintainers:
  - Andrew Jeffery <andrew@aj.id.au>

description: |+
  The ASPEED AST2600 MDIO controller is the third iteration of ASPEED's MDIO
  bus register interface, this time also separating out the controller from the
  MAC.

allOf:
  - $ref: "mdio.yaml#"

properties:
  compatible:
    const: aspeed,ast2600-mdio

  reg:
    maxItems: 1
    description: The register range of the MDIO controller instance

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/ast2600-clock.h>
    mdio0: mdio@1e650000 {
            compatible = "aspeed,ast2600-mdio";
            reg = <0x1e650000 0x8>;
            #address-cells = <1>;
            #size-cells = <0>;
            resets = <&syscon ASPEED_RESET_MII>;

            ethphy0: ethernet-phy@0 {
                    compatible = "ethernet-phy-ieee802.3-c22";
                    reg = <0>;
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/bluetooth/bluetooth-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Bluetooth Controller Generic Binding

maintainers:
  - Marcel Holtmann <marcel@holtmann.org>
  - Johan Hedberg <johan.hedberg@gmail.com>
  - Luiz Augusto von Dentz <luiz.dentz@gmail.com>

properties:
  $nodename:
    pattern: "^bluetooth(@.*)?$"

  local-bd-address:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    maxItems: 6
    description:
      Specifies the BD address that was uniquely assigned to the Bluetooth
      device. Formatted with least significant byte first (little-endian), e.g.
      in order to assign the address 00:11:22:33:44:55 this property must have
      the value [55 44 33 22 11 00].

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/bluetooth/brcm,bcm4377-bluetooth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM4377 family PCIe Bluetooth Chips

maintainers:
  - Sven Peter <sven@svenpeter.dev>

description:
  This binding describes Broadcom BCM4377 family PCIe-attached bluetooth chips
  usually found in Apple machines. The Wi-Fi part of the chip is described in
  bindings/net/wireless/brcm,bcm4329-fmac.yaml.

allOf:
  - $ref: bluetooth-controller.yaml#

properties:
  compatible:
    enum:
      - pci14e4,5fa0 # BCM4377
      - pci14e4,5f69 # BCM4378
      - pci14e4,5f71 # BCM4387

  reg:
    maxItems: 1

  brcm,board-type:
    $ref: /schemas/types.yaml#/definitions/string
    description: Board type of the Bluetooth chip. This is used to decouple
      the overall system board from the Bluetooth module and used to construct
      firmware and calibration data filenames.
      On Apple platforms, this should be the Apple module-instance codename
      prefixed by "apple,", e.g. "apple,atlantisb".
    pattern: '^apple,.*'

  brcm,taurus-cal-blob:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    description: A per-device calibration blob for the Bluetooth radio. This
      should be filled in by the bootloader from platform configuration
      data, if necessary, and will be uploaded to the device.
      This blob is used if the chip stepping of the Bluetooth module does not
      support beamforming.

  brcm,taurus-bf-cal-blob:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    description: A per-device calibration blob for the Bluetooth radio. This
      should be filled in by the bootloader from platform configuration
      data, if necessary, and will be uploaded to the device.
      This blob is used if the chip stepping of the Bluetooth module supports
      beamforming.

  local-bd-address: true

required:
  - compatible
  - reg
  - local-bd-address
  - brcm,board-type

additionalProperties: false

examples:
  - |
    pcie@a0000000 {
      #address-cells = <3>;
      #size-cells = <2>;
      reg = <0xa0000000 0x1000000>;
      device_type = "pci";
      ranges = <0x43000000 0x6 0xa0000000 0xa0000000 0x0 0x20000000>;

      bluetooth@0,1 {
        compatible = "pci14e4,5f69";
        reg = <0x100 0x0 0x0 0x0 0x0>;
        brcm,board-type = "apple,honshu";
        /* To be filled by the bootloader */
        local-bd-address = [00 00 00 00 00 00];
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/bluetooth/qualcomm-bluetooth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Bluetooth Chips

maintainers:
  - Balakrishna Godavarthi <bgodavar@codeaurora.org>
  - Rocky Liao <rjliao@codeaurora.org>

description:
  This binding describes Qualcomm UART-attached bluetooth chips.

properties:
  compatible:
    enum:
      - qcom,qca6174-bt
      - qcom,qca9377-bt
      - qcom,wcn3990-bt
      - qcom,wcn3991-bt
      - qcom,wcn3998-bt
      - qcom,qca6390-bt
      - qcom,wcn6750-bt

  enable-gpios:
    maxItems: 1
    description: gpio specifier used to enable chip

  swctrl-gpios:
    maxItems: 1
    description: gpio specifier is used to find status
                 of clock supply to SoC

  clocks:
    maxItems: 1
    description: clock provided to the controller (SUSCLK_32KHZ)

  vddio-supply:
    description: VDD_IO supply regulator handle

  vddxo-supply:
    description: VDD_XO supply regulator handle

  vddrf-supply:
    description: VDD_RF supply regulator handle

  vddch0-supply:
    description: VDD_CH0 supply regulator handle

  vddaon-supply:
    description: VDD_AON supply regulator handle

  vddbtcxmx-supply:
    description: VDD_BT_CXMX supply regulator handle

  vddrfacmn-supply:
    description: VDD_RFA_CMN supply regulator handle

  vddrfa0p8-supply:
    description: VDD_RFA_0P8 suppply regulator handle

  vddrfa1p7-supply:
    description: VDD_RFA_1P7 supply regulator handle

  vddrfa1p2-supply:
    description: VDD_RFA_1P2 supply regulator handle

  vddrfa2p2-supply:
    description: VDD_RFA_2P2 supply regulator handle

  vddasd-supply:
    description: VDD_ASD supply regulator handle

  max-speed:
    description: see Documentation/devicetree/bindings/serial/serial.yaml

  firmware-name:
    description: specify the name of nvm firmware to load

  local-bd-address: true

required:
  - compatible

additionalProperties: false

allOf:
  - $ref: bluetooth-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,qca6174-bt
    then:
      required:
        - enable-gpios
        - clocks

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,wcn3990-bt
              - qcom,wcn3991-bt
              - qcom,wcn3998-bt
    then:
      required:
        - vddio-supply
        - vddxo-supply
        - vddrf-supply
        - vddch0-supply

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,wcn6750-bt
    then:
      required:
        - enable-gpios
        - swctrl-gpios
        - vddio-supply
        - vddaon-supply
        - vddbtcxmx-supply
        - vddrfacmn-supply
        - vddrfa0p8-supply
        - vddrfa1p7-supply
        - vddrfa1p2-supply
        - vddasd-supply

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    serial {

        bluetooth {
            compatible = "qcom,qca6174-bt";
            enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
            clocks = <&divclk4>;
            firmware-name = "nvm_00440302.bin";
        };
    };
  - |
    serial {

        bluetooth {
            compatible = "qcom,wcn3990-bt";
            vddio-supply = <&vreg_s4a_1p8>;
            vddxo-supply = <&vreg_l7a_1p8>;
            vddrf-supply = <&vreg_l17a_1p3>;
            vddch0-supply = <&vreg_l25a_3p3>;
            max-speed = <3200000>;
            firmware-name = "crnv21.bin";
        };
    };
  - |
    serial {

        bluetooth {
            compatible = "qcom,wcn6750-bt";
            pinctrl-names = "default";
            pinctrl-0 = <&bt_en_default>;
            enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
            swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
            vddio-supply = <&vreg_l19b_1p8>;
            vddaon-supply = <&vreg_s7b_0p9>;
            vddbtcxmx-supply = <&vreg_s7b_0p9>;
            vddrfacmn-supply = <&vreg_s7b_0p9>;
            vddrfa0p8-supply = <&vreg_s7b_0p9>;
            vddrfa1p7-supply = <&vreg_s1b_1p8>;
            vddrfa1p2-supply = <&vreg_s8b_1p2>;
            vddrfa2p2-supply = <&vreg_s1c_2p2>;
            vddasd-supply = <&vreg_l11c_2p8>;
            max-speed = <3200000>;
            firmware-name = "msnv11.bin";
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/brcm,amac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom AMAC Ethernet Controller

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

allOf:
  - $ref: "ethernet-controller.yaml#"
  - if:
      properties:
        compatible:
          contains:
            enum:
              - brcm,amac
    then:
      properties:
        reg:
          maxItems: 2
        reg-names:
          maxItems: 2

  - if:
      properties:
        compatible:
          contains:
            enum:
              - brcm,nsp-amac
    then:
      properties:
        reg:
          minItems: 2
          maxItems: 2
        reg-names:
          minItems: 2
          maxItems: 2

  - if:
      properties:
        compatible:
          contains:
            enum:
              - brcm,ns2-amac
    then:
      properties:
        reg:
          minItems: 3
        reg-names:
          minItems: 3

properties:
  compatible:
    enum:
      - brcm,amac
      - brcm,nsp-amac
      - brcm,ns2-amac

  interrupts:
    maxItems: 1

  reg:
    minItems: 1
    maxItems: 3

  reg-names:
    minItems: 1
    items:
      - const: amac_base
      - const: idm_base
      - const: nicpm_base

unevaluatedProperties: false

examples:
  - |
   #include <dt-bindings/interrupt-controller/arm-gic.h>

   amac0: ethernet@18022000 {
      compatible = "brcm,nsp-amac";
      reg = <0x18022000 0x1000>,
            <0x18110000 0x1000>;
      reg-names = "amac_base", "idm_base";
      interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
   };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/brcm,bcm4908-enet.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM4908 Ethernet controller

description: Broadcom's Ethernet controller integrated into BCM4908 family SoCs

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    const: brcm,bcm4908-enet

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    items:
      - description: RX interrupt
      - description: TX interrupt

  interrupt-names:
    minItems: 1
    items:
      - const: rx
      - const: tx

required:
  - reg
  - interrupts
  - interrupt-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    ethernet@80002000 {
        compatible = "brcm,bcm4908-enet";
        reg = <0x80002000 0x1000>;

        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "rx", "tx";
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/brcm,bcm6368-mdio-mux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6368 MDIO bus multiplexer

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>

description:
  This MDIO bus multiplexer defines buses that could be internal as well as
  external to SoCs. When child bus is selected, one needs to select these two
  properties as well to generate desired MDIO transaction on appropriate bus.

allOf:
  - $ref: mdio-mux.yaml#

properties:
  compatible:
    const: brcm,bcm6368-mdio-mux

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    mdio0: mdio@10e000b0 {
      #address-cells = <1>;
      #size-cells = <0>;
      compatible = "brcm,bcm6368-mdio-mux";
      reg = <0x10e000b0 0x6>;

      mdio_int: mdio@0 {
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0>;
      };

      mdio_ext: mdio@1 {
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <1>;
      };
    };


code:
* Broadcom Starfighter 2 integrated swich

See dsa/brcm,bcm7445-switch-v4.0.yaml for the documentation.

*Deprecated* binding required properties:

- dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt
- dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt
- #address-cells: must be 2, see dsa/dsa.txt

Example using the old DSA DeviceTree binding:

switch_top@f0b00000 {
	compatible = "simple-bus";
	#size-cells = <1>;
	#address-cells = <1>;
	ranges = <0 0xf0b00000 0x40804>;

	ethernet_switch@0 {
		compatible = "brcm,bcm7445-switch-v4.0";
		#size-cells = <0>;
		#address-cells = <2>;
		reg = <0x0 0x40000
			0x40000 0x110
			0x40340 0x30
			0x40380 0x30
			0x40400 0x34
			0x40600 0x208>;
		interrupts = <0 0x18 0
				0 0x19 0>;
		brcm,num-gphy = <1>;
		brcm,num-rgmii-ports = <2>;
		brcm,fcb-pause-override;
		brcm,acb-packets-inflight;

		...
		switch@0 {
			reg = <0 0>;
			#size-cells = <0>;
			#address-cells = <1>;

			port@0 {
				label = "gphy";
				reg = <0>;
				brcm,use-bcm-hdr;
			};
			...
		};
	};
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/brcm,bcmgenet.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM7xxx Ethernet Controller (GENET) binding

maintainers:
  - Doug Berger <opendmb@gmail.com>
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  compatible:
    enum:
      - brcm,genet-v1
      - brcm,genet-v2
      - brcm,genet-v3
      - brcm,genet-v4
      - brcm,genet-v5
      - brcm,bcm2711-genet-v5
      - brcm,bcm7712-genet-v5

  reg:
    maxItems: 1

  interrupts:
    minItems: 2
    items:
      - description: general purpose interrupt line
      - description: RX and TX rings interrupt line
      - description: Wake-on-LAN interrupt line

  clocks:
    minItems: 1
    items:
      - description: main clock
      - description: EEE clock
      - description: Wake-on-LAN clock

  clock-names:
    minItems: 1
    items:
      - const: enet
      - const: enet-eee
      - const: enet-wol

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

patternProperties:
  "^mdio@[0-9a-f]+$":
    type: object
    $ref: "brcm,unimac-mdio.yaml"

    description:
      GENET internal UniMAC MDIO bus

required:
  - reg
  - interrupts
  - phy-mode
  - "#address-cells"
  - "#size-cells"

allOf:
  - $ref: ethernet-controller.yaml

unevaluatedProperties: false

examples:
  #include <dt-bindings/interrupt-controller/arm-gic.h>

  - |
    ethernet@f0b60000 {
        phy-mode = "internal";
        phy-handle = <&phy1>;
        mac-address = [ 00 10 18 36 23 1a ];
        compatible = "brcm,genet-v4";
        reg = <0xf0b60000 0xfc4c>;
        interrupts = <0x0 0x14 0x0>, <0x0 0x15 0x0>;
        #address-cells = <1>;
        #size-cells = <1>;

        mdio0: mdio@e14 {
           compatible = "brcm,genet-mdio-v4";
           #address-cells = <1>;
           #size-cells = <0>;
           reg = <0xe14 0x8>;

           phy1: ethernet-phy@1 {
                max-speed = <1000>;
                reg = <1>;
                compatible = "ethernet-phy-ieee802.3-c22";
           };
        };
    };

  - |
    ethernet@f0b80000 {
        phy-mode = "moca";
        fixed-link = <1 0 1000 0 0>;
        mac-address = [ 00 10 18 36 24 1a ];
        compatible = "brcm,genet-v4";
        #address-cells = <1>;
        #size-cells = <1>;
        reg = <0xf0b80000 0xfc4c>;
        interrupts = <0x0 0x16 0x0>, <0x0 0x17 0x0>;

        mdio1: mdio@e14 {
           compatible = "brcm,genet-mdio-v4";
           #address-cells = <1>;
           #size-cells = <0>;
           reg = <0xe14 0x8>;
        };
    };

  - |
    ethernet@f0ba0000 {
        phy-mode = "rgmii";
        phy-handle = <&phy0>;
        mac-address = [ 00 10 18 36 26 1a ];
        compatible = "brcm,genet-v4";
        #address-cells = <1>;
        #size-cells = <1>;
        reg = <0xf0ba0000 0xfc4c>;
        interrupts = <0x0 0x18 0x0>, <0x0 0x19 0x0>;

        mdio2: mdio@e14 {
           compatible = "brcm,genet-mdio-v4";
           #address-cells = <1>;
           #size-cells = <0>;
           reg = <0xe14 0x8>;

           phy0: ethernet-phy@0 {
                max-speed = <1000>;
                reg = <0>;
                compatible = "ethernet-phy-ieee802.3-c22";
           };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/brcm,iproc-mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom iProc MDIO bus controller

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

allOf:
  - $ref: mdio.yaml#

properties:
  compatible:
    const: brcm,iproc-mdio

  reg:
    maxItems: 1

unevaluatedProperties: false

required:
  - reg

examples:
  - |
    mdio@18002000 {
        compatible = "brcm,iproc-mdio";
        reg = <0x18002000 0x8>;
        #address-cells = <1>;
        #size-cells = <0>;

        ethernet-phy@0 {
            reg = <0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/brcm,mdio-mux-iproc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MDIO bus multiplexer found in Broadcom iProc based SoCs.

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

description:
  This MDIO bus multiplexer defines buses that could be internal as well as
  external to SoCs and could accept MDIO transaction compatible to C-22 or
  C-45 Clause. When child bus is selected, one needs to select these two
  properties as well to generate desired MDIO transaction on appropriate bus.

allOf:
  - $ref: /schemas/net/mdio-mux.yaml#

properties:
  compatible:
    const: brcm,mdio-mux-iproc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1
    description: core clock driving the MDIO block

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    mdio_mux_iproc: mdio-mux@66020000 {
        compatible = "brcm,mdio-mux-iproc";
        reg = <0x66020000 0x250>;
        #address-cells = <1>;
        #size-cells = <0>;

        mdio@0 {
           reg = <0x0>;
           #address-cells = <1>;
           #size-cells = <0>;

           pci_phy0: pci-phy@0 {
              compatible = "brcm,ns2-pcie-phy";
              reg = <0x0>;
              #phy-cells = <0>;
           };
        };

        mdio@7 {
           reg = <0x7>;
           #address-cells = <1>;
           #size-cells = <0>;

           pci_phy1: pci-phy@0 {
              compatible = "brcm,ns2-pcie-phy";
              reg = <0x0>;
              #phy-cells = <0>;
           };
        };

        mdio@10 {
           reg = <0x10>;
           #address-cells = <1>;
           #size-cells = <0>;

           gphy0: eth-phy@10 {
              reg = <0x10>;
           };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/brcm,systemport.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM7xxx Ethernet Systemport Controller (SYSTEMPORT)

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  compatible:
    enum:
      - brcm,systemport-v1.00
      - brcm,systemportlite-v1.00
      - brcm,systemport

  reg:
    maxItems: 1

  interrupts:
    minItems: 2
    items:
      - description: interrupt line for RX queues
      - description: interrupt line for TX queues
      - description: interrupt line for Wake-on-LAN

  clocks:
    items:
      - description: main clock
      - description: Wake-on-LAN clock

  clock-names:
    items:
      - const: sw_sysport
      - const: sw_sysportwol

  systemport,num-tier2-arb:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Number of tier 2 arbiters

  systemport,num-tier1-arb:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Number of tier 2 arbiters

  systemport,num-txq:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 32
    description:
      Number of HW transmit queues

  systemport,num-rxq:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 32
    description:
      Number of HW receive queues

required:
  - reg
  - interrupts
  - phy-mode

allOf:
  - $ref: "ethernet-controller.yaml#"

unevaluatedProperties: false

examples:
  - |
    ethernet@f04a0000 {
        compatible = "brcm,systemport-v1.00";
        reg = <0xf04a0000 0x4650>;
        local-mac-address = [ 00 11 22 33 44 55 ];
        phy-mode = "gmii";
        interrupts = <0x0 0x16 0x0>,
                     <0x0 0x17 0x0>;
        fixed-link {
            speed = <1000>;
            full-duplex;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/brcm,unimac-mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom UniMAC MDIO bus controller

maintainers:
  - Doug Berger <opendmb@gmail.com>
  - Florian Fainelli <f.fainelli@gmail.com>
  - Rafał Miłecki <rafal@milecki.pl>

allOf:
  - $ref: mdio.yaml#

properties:
  compatible:
    enum:
      - brcm,genet-mdio-v1
      - brcm,genet-mdio-v2
      - brcm,genet-mdio-v3
      - brcm,genet-mdio-v4
      - brcm,genet-mdio-v5
      - brcm,unimac-mdio

  reg:
    minItems: 1
    items:
      - description: base register
      - description: indirect accesses to larger than 16-bits MDIO transactions

  reg-names:
    minItems: 1
    items:
      - const: mdio
      - const: mdio_indir_rw

  interrupts:
    oneOf:
      - description: >
          Interrupt shared with the Ethernet MAC or Ethernet switch this MDIO
          block is integrated from
      - items:
          - description: |
              "mdio done" interrupt
          - description: |
              "mdio error" interrupt

  interrupt-names:
    oneOf:
      - const: mdio_done_error
      - items:
          - const: mdio_done
          - const: mdio_error

  clocks:
    description: A reference to the clock supplying the MDIO bus controller

  clock-frequency:
    description: >
      The MDIO bus clock that must be output by the MDIO bus hardware, if
      absent, the default hardware values are used

unevaluatedProperties: false

required:
  - reg
  - '#address-cells'
  - '#size-cells'

examples:
  - |
    mdio@403c0 {
        compatible = "brcm,unimac-mdio";
        reg = <0x403c0 0x8>, <0x40300 0x18>;
        reg-names = "mdio", "mdio_indir_rw";
        #address-cells = <1>;
        #size-cells = <0>;

        ethernet-phy@0 {
            compatible = "ethernet-phy-ieee802.3-c22";
            reg = <0>;
        };
    };


code:
The Broadcom BCM87XX devices are a family of 10G Ethernet PHYs.  They
have these bindings in addition to the standard PHY bindings.

Compatible: Should contain "broadcom,bcm8706" or "broadcom,bcm8727" and
            "ethernet-phy-ieee802.3-c45"

Optional Properties:

- broadcom,c45-reg-init : one of more sets of 4 cells.  The first cell
  is the MDIO Manageable Device (MMD) address, the second a register
  address within the MMD, the third cell contains a mask to be ANDed
  with the existing register value, and the fourth cell is ORed with
  he result to yield the new register value.  If the third cell has a
  value of zero, no read of the existing value is performed.

Example:

	ethernet-phy@5 {
		reg = <5>;
		compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45";
		interrupt-parent = <&gpio>;
		interrupts = <12 8>; /* Pin 12, active low */
		/*
		 * Set PMD Digital Control Register for
		 * GPIO[1] Tx/Rx
		 * GPIO[0] R64 Sync Acquired
		 */
		broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/broadcom-bluetooth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Bluetooth Chips

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description:
  This binding describes Broadcom UART-attached bluetooth chips.

properties:
  compatible:
    enum:
      - brcm,bcm20702a1
      - brcm,bcm4329-bt
      - brcm,bcm4330-bt
      - brcm,bcm4334-bt
      - brcm,bcm43430a0-bt
      - brcm,bcm43430a1-bt
      - brcm,bcm43438-bt
      - brcm,bcm4345c5
      - brcm,bcm43540-bt
      - brcm,bcm4335a0
      - brcm,bcm4349-bt
      - cypress,cyw4373a0-bt
      - infineon,cyw55572-bt

  shutdown-gpios:
    maxItems: 1
    description: GPIO specifier for the line BT_REG_ON used to
      power on the BT module

  reset-gpios:
    maxItems: 1
    description: GPIO specifier for the line BT_RST_N used to
      reset the BT module. This should be marked as
      GPIO_ACTIVE_LOW.

  device-wakeup-gpios:
    maxItems: 1
    description: GPIO specifier for the line BT_WAKE used to
      wakeup the controller. This is using the BT_GPIO_0
      pin on the chip when in use.

  host-wakeup-gpios:
    maxItems: 1
    deprecated: true
    description: GPIO specifier for the line HOST_WAKE used
      to wakeup the host processor. This is using he BT_GPIO_1
      pin on the chip when in use. This is deprecated and replaced
      by interrupts and "host-wakeup" interrupt-names

  clocks:
    minItems: 1
    maxItems: 2
    description: 1 or 2 clocks as defined in clock-names below,
      in that order

  clock-names:
    description: Names of the 1 to 2 supplied clocks
    oneOf:
      - const: extclk
        deprecated: true
        description: Deprecated in favor of txco

      - const: txco
        description: >
          external reference clock (not a standalone crystal)

      - const: lpo
        description: >
          external low power 32.768 kHz clock

      - items:
          - const: txco
          - const: lpo

  vbat-supply:
    description: phandle to regulator supply for VBAT

  vddio-supply:
    description: phandle to regulator supply for VDDIO

  brcm,bt-pcm-int-params:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    minItems: 5
    maxItems: 5
    description: |-
      configure PCM parameters via a 5-byte array:
       sco-routing: 0 = PCM, 1 = Transport, 2 = Codec, 3 = I2S
       pcm-interface-rate: 128KBps, 256KBps, 512KBps, 1024KBps, 2048KBps
       pcm-frame-type: short, long
       pcm-sync-mode: slave, master
       pcm-clock-mode: slave, master

  brcm,requires-autobaud-mode:
    type: boolean
    description:
      Set this property if autobaud mode is required. Autobaud mode is required
      if the device's initial baud rate in normal mode is not supported by the
      host or if the device requires autobaud mode startup before loading FW.

  interrupts:
    items:
      - description: Handle to the line HOST_WAKE used to wake
          up the host processor. This uses the BT_GPIO_1 pin on
          the chip when in use.

  interrupt-names:
    items:
      - const: host-wakeup

  max-speed: true
  current-speed: true

required:
  - compatible

dependencies:
  brcm,requires-autobaud-mode: [ 'shutdown-gpios' ]

if:
  not:
    properties:
      compatible:
        contains:
          enum:
            - brcm,bcm20702a1
            - brcm,bcm4329-bt
            - brcm,bcm4330-bt
then:
  properties:
    reset-gpios: false

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    uart {
        uart-has-rtscts;

        bluetooth {
            compatible = "brcm,bcm4330-bt";
            max-speed = <921600>;
            brcm,bt-pcm-int-params = [01 02 00 01 01];
            shutdown-gpios = <&gpio 30 GPIO_ACTIVE_HIGH>;
            device-wakeup-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
            reset-gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
            interrupt-parent = <&gpio>;
            interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
        };
    };


code:
Generic Bluetooth controller over USB (btusb driver)
---------------------------------------------------

Required properties:

  - compatible : should comply with the format "usbVID,PID" specified in
		 Documentation/devicetree/bindings/usb/usb-device.yaml
		 At the time of writing, the only OF supported devices
		 (more may be added later) are:

		  "usb1286,204e" (Marvell 8997)
		  "usbcf3,e300" (Qualcomm QCA6174A)
		  "usb4ca,301a" (Qualcomm QCA6174A (Lite-On))

Also, vendors that use btusb may have device additional properties, e.g:
Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt

Optional properties:

  - interrupt-names: (see below)
  - interrupts : The interrupt specified by the name "wakeup" is the interrupt
		 that shall be used for out-of-band wake-on-bt. Driver will
		 request this interrupt for wakeup. During system suspend, the
		 irq will be enabled so that the bluetooth chip can wakeup host
		 platform out of band. During system resume, the irq will be
		 disabled to make sure unnecessary interrupt is not received.

Example:

Following example uses irq pin number 3 of gpio0 for out of band wake-on-bt:

&usb_host1_ehci {
    #address-cells = <1>;
    #size-cells = <0>;

    mvl_bt1: bt@1 {
	compatible = "usb1286,204e";
	reg = <1>;
	interrupt-parent = <&gpio0>;
	interrupt-names = "wakeup";
	interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
    };
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/calxeda-xgmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Calxeda Highbank 10Gb XGMAC Ethernet controller

description: |
  The Calxeda XGMAC Ethernet controllers are directly connected to the
  internal machine "network fabric", which is set up, initialised and
  managed by the firmware. So there are no PHY properties in this
  binding. Switches in the fabric take care of routing and mapping the
  traffic to external network ports.

maintainers:
  - Andre Przywara <andre.przywara@arm.com>

properties:
  compatible:
    const: calxeda,hb-xgmac

  reg:
    maxItems: 1

  interrupts:
    description: |
      Can point to at most 3 xgmac interrupts. The 1st one is the main
      interrupt, the 2nd one is used for power management. The optional
      3rd one is the low power state interrupt.
    minItems: 2
    maxItems: 3

  dma-coherent: true

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    ethernet@fff50000 {
        compatible = "calxeda,hb-xgmac";
        reg = <0xfff50000 0x1000>;
        interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/allwinner,sun4i-a10-can.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 CAN Controller Device Tree Bindings

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

allOf:
  - $ref: can-controller.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - const: allwinner,sun7i-a20-can
          - const: allwinner,sun4i-a10-can
      - const: allwinner,sun4i-a10-can
      - const: allwinner,sun8i-r40-can

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

if:
  properties:
    compatible:
      contains:
        const: allwinner,sun8i-r40-can

then:
  required:
    - resets

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun7i-a20-ccu.h>

    can0: can@1c2bc00 {
        compatible = "allwinner,sun7i-a20-can",
                     "allwinner,sun4i-a10-can";
        reg = <0x01c2bc00 0x400>;
        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_APB1_CAN>;
    };
  - |
    #define RST_BUS_CAN		68
    #define CLK_BUS_CAN		91
    can1: can@1c2bc00 {
        compatible = "allwinner,sun8i-r40-can";
        reg = <0x01c2bc00 0x400>;
        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_CAN>;
        resets = <&ccu RST_BUS_CAN>;
    };

...


code:
* AT91 CAN *

Required properties:
  - compatible: Should be "atmel,at91sam9263-can", "atmel,at91sam9x5-can" or
    "microchip,sam9x60-can"
  - reg: Should contain CAN controller registers location and length
  - interrupts: Should contain IRQ line for the CAN controller

Example:

	can0: can@f000c000 {
		compatible = "atmel,at91sam9x5-can";
		reg = <0xf000c000 0x300>;
		interrupts = <40 4 5>
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/bosch,c_can.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Bosch C_CAN/D_CAN controller Device Tree Bindings

description: Bosch C_CAN/D_CAN controller for CAN bus

maintainers:
  - Dario Binacchi <dariobin@libero.it>

allOf:
  - $ref: can-controller.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - bosch,c_can
          - bosch,d_can
          - ti,dra7-d_can
          - ti,am3352-d_can
      - items:
          - enum:
              - ti,am4372-d_can
          - const: ti,am3352-d_can

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 4

  power-domains:
    description: |
      Should contain a phandle to a PM domain provider node and an args
      specifier containing the DCAN device id value. It's mandatory for
      Keystone 2 66AK2G SoCs only.
    maxItems: 1

  clocks:
    description: |
      CAN functional clock phandle.
    maxItems: 1

  clock-names:
    maxItems: 1

  syscon-raminit:
    description: |
      Handle to system control region that contains the RAMINIT register,
      register offset to the RAMINIT register and the CAN instance number (0
      offset).
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: The phandle to the system control region.
          - description: The register offset.
          - description: The CAN instance number.

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

if:
  properties:
    compatible:
      contains:
        enum:
          - bosch,d_can

then:
  properties:
    interrupts:
      items:
        - description: Error and status IRQ
        - description: Message object IRQ
        - description: RAM ECC correctable error IRQ
        - description: RAM ECC non-correctable error IRQ

else:
  properties:
    interrupts:
      items:
        - description: Error and status IRQ

additionalProperties: false

examples:
  - |
    #include <dt-bindings/reset/altr,rst-mgr.h>

    can@ffc00000 {
       compatible = "bosch,d_can";
       reg = <0xffc00000 0x1000>;
       interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
       clocks = <&can0_clk>;
       resets = <&rst CAN0_RESET>;
    };
  - |
    can@0 {
        compatible = "ti,am3352-d_can";
        reg = <0x0 0x2000>;
        clocks = <&dcan1_fck>;
        clock-names = "fck";
        syscon-raminit = <&scm_conf 0x644 1>;
        interrupts = <55>;
    };