code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/allwinner,sun4i-a10-ts.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 Resistive Touchscreen Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#thermal-sensor-cells":
    const: 0

  compatible:
    enum:
      - allwinner,sun4i-a10-ts
      - allwinner,sun5i-a13-ts
      - allwinner,sun6i-a31-ts

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  allwinner,ts-attached:
    $ref: /schemas/types.yaml#/definitions/flag
    description: A touchscreen is attached to the controller

  allwinner,tp-sensitive-adjust:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 15
    default: 15

    description: Sensitivity of pen down detection

  allwinner,filter-type:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 3
    default: 1

    description: |
      Select median and averaging filter. Sample used for median /
      averaging filter:
        0: 4/2
        1: 5/3
        2: 8/4
        3: 16/8

required:
  - "#thermal-sensor-cells"
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    rtp: rtp@1c25000 {
        compatible = "allwinner,sun4i-a10-ts";
        reg = <0x01c25000 0x100>;
        interrupts = <29>;
        allwinner,ts-attached;
        #thermal-sensor-cells = <0>;
        /* sensitive/noisy touch panel */
        allwinner,tp-sensitive-adjust = <0>;
        allwinner,filter-type = <3>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/allwinner,sun6i-a31-prcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 PRCM

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

deprecated: true

properties:
  compatible:
    const: allwinner,sun6i-a31-prcm

  reg:
    maxItems: 1

patternProperties:
  "^.*_(clk|rst)$":
    type: object
    unevaluatedProperties: false

    properties:
      compatible:
        enum:
          - allwinner,sun4i-a10-mod0-clk
          - allwinner,sun6i-a31-apb0-clk
          - allwinner,sun6i-a31-apb0-gates-clk
          - allwinner,sun6i-a31-ar100-clk
          - allwinner,sun6i-a31-clock-reset
          - fixed-factor-clock

    allOf:
      - if:
          properties:
            compatible:
              contains:
                const: fixed-factor-clock

        then:
          $ref: /schemas/clock/fixed-factor-clock.yaml#

      - if:
          properties:
            compatible:
              contains:
                const: allwinner,sun4i-a10-mod0-clk

        then:
          properties:
            "#clock-cells":
              const: 0

            # Already checked in the main schema
            compatible: true

            clocks:
              maxItems: 2

            clock-output-names:
              maxItems: 1

            phandle: true

          required:
            - "#clock-cells"
            - compatible
            - clocks
            - clock-output-names

          additionalProperties: false

      - if:
          properties:
            compatible:
              contains:
                const: allwinner,sun6i-a31-apb0-clk

        then:
          properties:
            "#clock-cells":
              const: 0

            # Already checked in the main schema
            compatible: true

            clocks:
              maxItems: 1

            clock-output-names:
              maxItems: 1

            phandle: true

          required:
            - "#clock-cells"
            - compatible
            - clocks
            - clock-output-names

          additionalProperties: false

      - if:
          properties:
            compatible:
              contains:
                const: allwinner,sun6i-a31-apb0-gates-clk

        then:
          properties:
            "#clock-cells":
              const: 1
              description: >
                This additional argument passed to that clock is the
                offset of the bit controlling this particular gate in
                the register.

            # Already checked in the main schema
            compatible: true

            clocks:
              maxItems: 1

            clock-output-names:
              minItems: 1
              maxItems: 32

            phandle: true

          required:
            - "#clock-cells"
            - compatible
            - clocks
            - clock-output-names

          additionalProperties: false

      - if:
          properties:
            compatible:
              contains:
                const: allwinner,sun6i-a31-ar100-clk

        then:
          properties:
            "#clock-cells":
              const: 0

            # Already checked in the main schema
            compatible: true

            clocks:
              maxItems: 4
              description: >
                The parent order must match the hardware programming
                order.

            clock-output-names:
              maxItems: 1

            phandle: true

          required:
            - "#clock-cells"
            - compatible
            - clocks
            - clock-output-names

          additionalProperties: false

      - if:
          properties:
            compatible:
              contains:
                const: allwinner,sun6i-a31-clock-reset

        then:
          properties:
            "#reset-cells":
              const: 1

            # Already checked in the main schema
            compatible: true

            phandle: true

          required:
            - "#reset-cells"
            - compatible

          additionalProperties: false

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/sun6i-a31-ccu.h>

    prcm@1f01400 {
        compatible = "allwinner,sun6i-a31-prcm";
        reg = <0x01f01400 0x200>;

        ar100: ar100_clk {
            compatible = "allwinner,sun6i-a31-ar100-clk";
            #clock-cells = <0>;
            clocks = <&rtc 0>, <&osc24M>,
                     <&ccu CLK_PLL_PERIPH>,
                     <&ccu CLK_PLL_PERIPH>;
            clock-output-names = "ar100";
        };

        ahb0: ahb0_clk {
            compatible = "fixed-factor-clock";
            #clock-cells = <0>;
            clock-div = <1>;
            clock-mult = <1>;
            clocks = <&ar100>;
            clock-output-names = "ahb0";
        };

        apb0: apb0_clk {
            compatible = "allwinner,sun6i-a31-apb0-clk";
            #clock-cells = <0>;
            clocks = <&ahb0>;
            clock-output-names = "apb0";
        };

        apb0_gates: apb0_gates_clk {
            compatible = "allwinner,sun6i-a31-apb0-gates-clk";
            #clock-cells = <1>;
            clocks = <&apb0>;
            clock-output-names = "apb0_pio", "apb0_ir",
                                 "apb0_timer", "apb0_p2wi",
                                 "apb0_uart", "apb0_1wire",
                                 "apb0_i2c";
        };

        ir_clk: ir_clk {
            #clock-cells = <0>;
            compatible = "allwinner,sun4i-a10-mod0-clk";
            clocks = <&rtc 0>, <&osc24M>;
            clock-output-names = "ir";
        };

        apb0_rst: apb0_rst {
            compatible = "allwinner,sun6i-a31-clock-reset";
            #reset-cells = <1>;
        };
    };

...

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/allwinner,sun8i-a23-prcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A23 PRCM

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

deprecated: true

properties:
  compatible:
    const: allwinner,sun8i-a23-prcm

  reg:
    maxItems: 1

patternProperties:
  "^.*(clk|rst|codec).*$":
    type: object
    unevaluatedProperties: false

    properties:
      compatible:
        enum:
          - fixed-factor-clock
          - allwinner,sun8i-a23-apb0-clk
          - allwinner,sun8i-a23-apb0-gates-clk
          - allwinner,sun6i-a31-clock-reset
          - allwinner,sun8i-a23-codec-analog

    required:
      - compatible

    allOf:
      - if:
          properties:
            compatible:
              contains:
                const: fixed-factor-clock

        then:
          $ref: /schemas/clock/fixed-factor-clock.yaml#

      - if:
          properties:
            compatible:
              contains:
                const: allwinner,sun8i-a23-apb0-clk

        then:
          properties:
            "#clock-cells":
              const: 0

            # Already checked in the main schema
            compatible: true

            clocks:
              maxItems: 1

            clock-output-names:
              maxItems: 1

            phandle: true

          required:
            - "#clock-cells"
            - compatible
            - clocks
            - clock-output-names

          additionalProperties: false

      - if:
          properties:
            compatible:
              contains:
                const: allwinner,sun8i-a23-apb0-gates-clk

        then:
          properties:
            "#clock-cells":
              const: 1
              description: >
                This additional argument passed to that clock is the
                offset of the bit controlling this particular gate in
                the register.

            # Already checked in the main schema
            compatible: true

            clocks:
              maxItems: 1

            clock-output-names:
              minItems: 1
              maxItems: 32

            phandle: true

          required:
            - "#clock-cells"
            - compatible
            - clocks
            - clock-output-names

          additionalProperties: false

      - if:
          properties:
            compatible:
              contains:
                const: allwinner,sun6i-a31-clock-reset

        then:
          properties:
            "#reset-cells":
              const: 1

            # Already checked in the main schema
            compatible: true

            phandle: true

          required:
            - "#reset-cells"
            - compatible

          additionalProperties: false

      - if:
          properties:
            compatible:
              contains:
                const: allwinner,sun8i-a23-codec-analog

        then:
          properties:
            # Already checked in the main schema
            compatible: true

            phandle: true

          required:
            - compatible

          additionalProperties: false

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    prcm@1f01400 {
        compatible = "allwinner,sun8i-a23-prcm";
        reg = <0x01f01400 0x200>;

        ar100: ar100_clk {
            compatible = "fixed-factor-clock";
            #clock-cells = <0>;
            clock-div = <1>;
            clock-mult = <1>;
            clocks = <&osc24M>;
            clock-output-names = "ar100";
        };

        ahb0: ahb0_clk {
            compatible = "fixed-factor-clock";
            #clock-cells = <0>;
            clock-div = <1>;
            clock-mult = <1>;
            clocks = <&ar100>;
            clock-output-names = "ahb0";
        };

        apb0: apb0_clk {
            compatible = "allwinner,sun8i-a23-apb0-clk";
            #clock-cells = <0>;
            clocks = <&ahb0>;
            clock-output-names = "apb0";
        };

        apb0_gates: apb0_gates_clk {
            compatible = "allwinner,sun8i-a23-apb0-gates-clk";
            #clock-cells = <1>;
            clocks = <&apb0>;
            clock-output-names = "apb0_pio", "apb0_timer",
                                 "apb0_rsb", "apb0_uart",
                                 "apb0_i2c";
        };

        apb0_rst: apb0_rst {
            compatible = "allwinner,sun6i-a31-clock-reset";
            #reset-cells = <1>;
        };

        codec_analog: codec-analog {
            compatible = "allwinner,sun8i-a23-codec-analog";
        };
    };

...


code:
* Altera Arria10 Development Kit System Resource Chip

Required parent device properties:
- compatible		: "altr,a10sr"
- spi-max-frequency	: Maximum SPI frequency.
- reg			: The SPI Chip Select address for the Arria10
			  System Resource chip
- interrupts		: The interrupt line the device is connected to.
- interrupt-controller	: Marks the device node as an interrupt controller.
- #interrupt-cells	: The number of cells to describe an IRQ, should be 2.
			    The first cell is the IRQ number.
			    The second cell is the flags, encoded as trigger
			    masks from ../interrupt-controller/interrupts.txt.

The A10SR consists of these sub-devices:

Device                   Description
------                   ----------
a10sr_gpio               GPIO Controller
a10sr_rst                Reset Controller

Arria10 GPIO
Required Properties:
- compatible        : Should be "altr,a10sr-gpio"
- gpio-controller   : Marks the device node as a GPIO Controller.
- #gpio-cells       : Should be two.  The first cell is the pin number and
                      the second cell is used to specify flags.
                      See ../gpio/gpio.txt for more information.

Arria10 Peripheral PHY Reset
Required Properties:
- compatible        : Should be "altr,a10sr-reset"
- #reset-cells      : Should be one.

Example:

        resource-manager@0 {
		compatible = "altr,a10sr";
		reg = <0>;
		spi-max-frequency = <100000>;
		interrupt-parent = <&portb>;
		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <2>;

		a10sr_gpio: gpio-controller {
			compatible = "altr,a10sr-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		a10sr_rst: reset-controller {
			compatible = "altr,a10sr-reset";
			#reset-cells = <1>;
		};
	};


code:
AS3711 is an I2C PMIC from Austria MicroSystems with multiple DCDC and LDO power
supplies, a battery charger and an RTC. So far only bindings for the two stepup
DCDC converters are defined. Other DCDC and LDO supplies are configured, using
standard regulator properties, they must belong to a sub-node, called
"regulators" and be called "sd1" to "sd4" and "ldo1" to "ldo8." Stepup converter
configuration should be placed in a subnode, called "backlight."

Compulsory properties:
- compatible		: must be "ams,as3711"
- reg			: specifies the I2C address

To use the SU1 converter as a backlight source the following two properties must
be provided:
- su1-dev		: framebuffer phandle
- su1-max-uA		: maximum current

To use the SU2 converter as a backlight source the following two properties must
be provided:
- su2-dev		: framebuffer phandle
- su1-max-uA		: maximum current

Additionally one of these properties must be provided to select the type of
feedback used:
- su2-feedback-voltage	: voltage feedback is used
- su2-feedback-curr1	: CURR1 input used for current feedback
- su2-feedback-curr2	: CURR2 input used for current feedback
- su2-feedback-curr3	: CURR3 input used for current feedback
- su2-feedback-curr-auto: automatic current feedback selection

and one of these to select the over-voltage protection pin
- su2-fbprot-lx-sd4	: LX_SD4 is used for over-voltage protection
- su2-fbprot-gpio2	: GPIO2 is used for over-voltage protection
- su2-fbprot-gpio3	: GPIO3 is used for over-voltage protection
- su2-fbprot-gpio4	: GPIO4 is used for over-voltage protection

If "su2-feedback-curr-auto" is selected, one or more of the following properties
have to be specified:
- su2-auto-curr1	: use CURR1 input for current feedback
- su2-auto-curr2	: use CURR2 input for current feedback
- su2-auto-curr3	: use CURR3 input for current feedback

Example:

as3711@40 {
	compatible = "ams,as3711";
	reg = <0x40>;

	regulators {
		sd4 {
			regulator-name = "1.215V";
			regulator-min-microvolt = <1215000>;
			regulator-max-microvolt = <1235000>;
		};
		ldo2 {
			regulator-name = "2.8V CPU";
			regulator-min-microvolt = <2800000>;
			regulator-max-microvolt = <2800000>;
			regulator-always-on;
			regulator-boot-on;
		};
	};

	backlight {
		compatible = "ams,as3711-bl";
		su2-dev = <&lcdc>;
		su2-max-uA = <36000>;
		su2-feedback-curr-auto;
		su2-fbprot-gpio4;
		su2-auto-curr1;
		su2-auto-curr2;
		su2-auto-curr3;
	};
};


code:
* ams AS3722 Power management IC.

Required properties:
-------------------
- compatible: Must be "ams,as3722".
- reg: I2C device address.
- interrupt-controller: AS3722 has internal interrupt controller which takes the
  interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well
  as external input.
- #interrupt-cells: Should be set to 2 for IRQ number and flags.
  The first cell is the IRQ number. IRQ numbers for different interrupt source
  of AS3722 are defined at dt-bindings/mfd/as3722.h
  The second cell is the flags, encoded as the trigger masks from binding document
	interrupts.txt, using dt-bindings/irq.

Optional properties:
--------------------
- ams,enable-internal-int-pullup: Boolean property, to enable internal pullup on
	interrupt pin. Missing this will disable internal pullup on INT pin.
- ams,enable-internal-i2c-pullup: Boolean property, to enable internal pullup on
	i2c scl/sda pins. Missing this will disable internal pullup on i2c
	scl/sda lines.
- ams,enable-ac-ok-power-on: Boolean property, to enable exit out of power off
	mode with AC_OK pin (pin enabled in power off mode).

Optional submodule and their properties:
=======================================

Pinmux and GPIO:
===============
Device has 8 GPIO pins which can be configured as GPIO as well as the special IO
functions.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

Following are properties which is needed if GPIO and pinmux functionality
is required:
    Required properties:
    -------------------
	- gpio-controller: Marks the device node as a GPIO controller.
	- #gpio-cells: Number of GPIO cells. Refer to binding document
			gpio/gpio.txt

    Optional properties:
    --------------------
	Following properties are require if pin control setting is required
	at boot.
	- pinctrl-names: A pinctrl state named "default" be defined, using the
		bindings in pinctrl/pinctrl-bindings.txt.
	- pinctrl[0...n]: Properties to contain the phandle that refer to
		different nodes of pin control settings. These nodes represents
		the pin control setting of state 0 to state n. Each of these
		nodes contains different subnodes to represents some desired
		configuration for a list of pins. This configuration can
		include the mux function to select on those pin(s), and
		various pin configuration parameters, such as pull-up,
		open drain.

		Each subnode have following properties:
		Required properties:
		    - pins: List of pins. Valid values of pins properties are:
				gpio0, gpio1, gpio2, gpio3, gpio4, gpio5,
				gpio6, gpio7

		Optional properties:
			function, bias-disable, bias-pull-up, bias-pull-down,
			bias-high-impedance, drive-open-drain.

			Valid values for function properties are:
				gpio, interrupt-out, gpio-in-interrupt,
				vsup-vbat-low-undebounce-out,
				vsup-vbat-low-debounce-out,
				voltage-in-standby, oc-pg-sd0, oc-pg-sd6,
				powergood-out, pwm-in, pwm-out, clk32k-out,
				watchdog-in, soft-reset-in

Regulators:
===========
Device has multiple DCDC and LDOs. The node "regulators" is require if regulator
functionality is needed.

Following are properties of regulator subnode.

    Optional properties:
    -------------------
	The input supply of regulators are the optional properties on the
	regulator node. The input supply of these regulators are provided
	through following properties:
		vsup-sd2-supply: Input supply for SD2.
		vsup-sd3-supply: Input supply for SD3.
		vsup-sd4-supply: Input supply for SD4.
		vsup-sd5-supply: Input supply for SD5.
		vin-ldo0-supply: Input supply for LDO0.
		vin-ldo1-6-supply: Input supply for LDO1 and LDO6.
		vin-ldo2-5-7-supply: Input supply for LDO2, LDO5 and LDO7.
		vin-ldo3-4-supply: Input supply for LDO3 and LDO4.
		vin-ldo9-10-supply: Input supply for LDO9 and LDO10.
		vin-ldo11-supply: Input supply for LDO11.

    Optional sub nodes for regulators:
    ---------------------------------
	The subnodes name is the name of regulator and it must be one of:
	sd[0-6], ldo[0-7], ldo[9-11]

	Each sub-node should contain the constraints and initialization
	information for that regulator. See regulator.txt for a description
	of standard properties for these sub-nodes.
	Additional optional custom properties  are listed below.
		ams,ext-control: External control of the rail. The option of
			this properties will tell which external input is
			controlling this rail. Valid values are 0, 1, 2 ad 3.
			0: There is no external control of this rail.
			1: Rail is controlled by ENABLE1 input pin.
			2: Rail is controlled by ENABLE2 input pin.
			3: Rail is controlled by ENABLE3 input pin.
			Missing this property on DT will be assume as no
			external control. The external control pin macros
			are defined @dt-bindings/mfd/as3722.h

		ams,enable-tracking: Enable tracking with SD1, only supported
			by LDO3.

Power-off:
=========
AS3722 supports the system power off by turning off all its rails.
The device node should have the following properties to enable this
functionality
ams,system-power-controller: Boolean, to enable the power off functionality
        through this device.

Example:
--------
#include <dt-bindings/mfd/as3722.h>
...
ams3722 {
	compatible = "ams,as3722";
	reg = <0x48>;

	ams,system-power-controller;

	interrupt-parent = <&intc>;
	interrupt-controller;
	#interrupt-cells = <2>;

	gpio-controller;
	#gpio-cells = <2>;

	pinctrl-names = "default";
	pinctrl-0 = <&as3722_default>;

	as3722_default: pinmux {
			gpio0 {
				pins = "gpio0";
				function = "gpio";
				bias-pull-down;
			};

			gpio1_2_4_7 {
				pins = "gpio1", "gpio2", "gpio4", "gpio7";
				function = "gpio";
				bias-pull-up;
			};

			gpio5 {
				pins = "gpio5";
				function = "clk32k_out";
			};
	}

	regulators {
			vsup-sd2-supply = <...>;
			...

			sd0 {
				regulator-name = "vdd_cpu";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1400000>;
				regulator-always-on;
				ams,ext-control = <2>;
			};

			sd1 {
				regulator-name = "vdd_core";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1400000>;
				regulator-always-on;
				ams,ext-control = <1>;
			};

			sd2 {
				regulator-name = "vddio_ddr";
				regulator-min-microvolt = <1350000>;
				regulator-max-microvolt = <1350000>;
				regulator-always-on;
			};

			sd4 {
				regulator-name = "avdd-hdmi-pex";
				regulator-min-microvolt = <1050000>;
				regulator-max-microvolt = <1050000>;
				regulator-always-on;
			};

			sd5 {
				regulator-name = "vdd-1v8";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};
			....
	};
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Aspeed System Control Unit

description:
  The Aspeed System Control Unit manages the global behaviour of the SoC,
  configuring elements such as clocks, pinmux, and reset.

maintainers:
  - Joel Stanley <joel@jms.id.au>
  - Andrew Jeffery <andrew@aj.id.au>

properties:
  compatible:
    items:
      - enum:
          - aspeed,ast2400-scu
          - aspeed,ast2500-scu
          - aspeed,ast2600-scu
      - const: syscon
      - const: simple-mfd

  reg:
    maxItems: 1

  ranges: true

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

patternProperties:
  '^p2a-control@[0-9a-f]+$':
    description: See Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt
    type: object

  '^pinctrl(@[0-9a-f]+)?$':
    oneOf:
      - $ref: /schemas/pinctrl/aspeed,ast2400-pinctrl.yaml
      - $ref: /schemas/pinctrl/aspeed,ast2500-pinctrl.yaml
      - $ref: /schemas/pinctrl/aspeed,ast2600-pinctrl.yaml

  '^interrupt-controller@[0-9a-f]+$':
    description: See Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2xxx-scu-ic.txt
    type: object

  '^silicon-id@[0-9a-f]+$':
    description: Unique hardware silicon identifiers within the SoC
    type: object
    additionalProperties: false

    properties:
      compatible:
        items:
          - enum:
              - aspeed,ast2400-silicon-id
              - aspeed,ast2500-silicon-id
              - aspeed,ast2600-silicon-id
          - const: aspeed,silicon-id

      reg:
        description:
          The reg should be the unique silicon id register, and not backwards
          compatible one in eg. the 2600.
        minItems: 1
        items:
          - description: silicon id information registers
          - description: unique chip id registers

required:
  - compatible
  - reg
  - ranges
  - '#address-cells'
  - '#size-cells'
  - '#clock-cells'
  - '#reset-cells'

additionalProperties: false

examples:
  - |
    syscon@1e6e2000 {
        compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
        reg = <0x1e6e2000 0x1a8>;
        #clock-cells = <1>;
        #reset-cells = <1>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x1e6e2000 0x1000>;

        silicon-id@7c {
            compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
            reg = <0x7c 0x4>, <0x150 0x8>;
        };
    };
...


code:
* Device tree bindings for Aspeed SoC Display Controller (GFX)

The Aspeed SoC Display Controller primarily does as its name suggests, but also
participates in pinmux requests on the g5 SoCs. It is therefore considered a
syscon device.

Required properties:
- compatible:		"aspeed,ast2500-gfx", "syscon"
- reg:			contains offset/length value of the GFX memory
			region.

Example:

gfx: display@1e6e6000 {
	compatible = "aspeed,ast2500-gfx", "syscon";
	reg = <0x1e6e6000 0x1000>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# # Copyright (c) 2021 Aspeed Tehchnology Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Aspeed Low Pin Count (LPC) Bus Controller

maintainers:
  - Andrew Jeffery <andrew@aj.id.au>
  - Chia-Wei Wang <chiawei_wang@aspeedtech.com>

description:
  The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
  peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
  primary use case of the Aspeed LPC controller is as a slave on the bus
  (typically in a Baseboard Management Controller SoC), but under certain
  conditions it can also take the role of bus master.

  The LPC controller is represented as a multi-function device to account for the
  mix of functionality, which includes, but is not limited to

  * An IPMI Block Transfer[2] Controller

  * An LPC Host Interface Controller manages functions exposed to the host such
    as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
    management and bus snoop configuration.

  * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom
    hardware management protocols for handover between the host and baseboard
    management controller.

  Additionally the state of the LPC controller influences the pinmux
  configuration, therefore the host portion of the controller is exposed as a
  syscon as a means to arbitrate access.

properties:
  compatible:
    items:
      - enum:
          - aspeed,ast2400-lpc-v2
          - aspeed,ast2500-lpc-v2
          - aspeed,ast2600-lpc-v2
      - const: simple-mfd
      - const: syscon

  reg:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  ranges: true

patternProperties:
  "^lpc-ctrl@[0-9a-f]+$":
    type: object
    additionalProperties: false

    description: |
      The LPC Host Interface Controller manages functions exposed to the host such as
      LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
      and bus snoop configuration.

    properties:
      compatible:
        items:
          - enum:
              - aspeed,ast2400-lpc-ctrl
              - aspeed,ast2500-lpc-ctrl
              - aspeed,ast2600-lpc-ctrl

      reg:
        maxItems: 1

      clocks:
        maxItems: 1

      memory-region:
        maxItems: 1
        description: handle to memory reservation for the LPC to AHB mapping region

      flash:
        $ref: /schemas/types.yaml#/definitions/phandle
        description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping

    required:
      - compatible
      - clocks

  "^reset-controller@[0-9a-f]+$":
    type: object
    additionalProperties: false

    description:
      The UARTs present in the ASPEED SoC can have their resets tied to the reset
      state of the LPC bus. Some systems may chose to modify this configuration

    properties:
      compatible:
        items:
          - enum:
              - aspeed,ast2400-lpc-reset
              - aspeed,ast2500-lpc-reset
              - aspeed,ast2600-lpc-reset

      reg:
        maxItems: 1

      '#reset-cells':
        const: 1

    required:
      - compatible
      - '#reset-cells'

  "^lpc-snoop@[0-9a-f]+$":
    type: object
    additionalProperties: false

    description:
      The LPC snoop interface allows the BMC to listen on and record the data
      bytes written by the Host to the targeted LPC I/O pots.

    properties:
      compatible:
        items:
          - enum:
              - aspeed,ast2400-lpc-snoop
              - aspeed,ast2500-lpc-snoop
              - aspeed,ast2600-lpc-snoop

      reg:
        maxItems: 1

      interrupts:
        maxItems: 1

      snoop-ports:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        description: The LPC I/O ports to snoop

    required:
      - compatible
      - interrupts
      - snoop-ports

  "^uart-routing@[0-9a-f]+$":
    $ref: /schemas/soc/aspeed/uart-routing.yaml#
    description: The UART routing control under LPC register space

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges

additionalProperties:
  type: object

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/ast2600-clock.h>

    lpc: lpc@1e789000 {
        compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
        reg = <0x1e789000 0x1000>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x1e789000 0x1000>;

        lpc_ctrl: lpc-ctrl@80 {
            compatible = "aspeed,ast2600-lpc-ctrl";
            reg = <0x80 0x80>;
            clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
            memory-region = <&flash_memory>;
            flash = <&spi>;
        };

        lpc_reset: reset-controller@98 {
            compatible = "aspeed,ast2600-lpc-reset";
            reg = <0x98 0x4>;
            #reset-cells = <1>;
        };

        lpc_snoop: lpc-snoop@90 {
            compatible = "aspeed,ast2600-lpc-snoop";
            reg = <0x90 0x8>;
            interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
            snoop-ports = <0x80>;
        };
    };


code:
* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit)

The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C
controller and an USART. Only one function can be used at a time and is chosen
at boot time according to the device tree.

Required properties:
- compatible:		Should be "atmel,sama5d2-flexcom"
- reg:			Should be the offset/length value for Flexcom dedicated
			I/O registers (without USART, TWI or SPI registers).
- clocks:		Should be the Flexcom peripheral clock from PMC.
- #address-cells:	Should be <1>
- #size-cells:		Should be <1>
- ranges:		Should be one range for the full I/O register region
			(including USART, TWI and SPI registers).
- atmel,flexcom-mode:	Should be one of the following values:
			- <1> for USART
			- <2> for SPI
			- <3> for I2C

Required child:
A single available child device of type matching the "atmel,flexcom-mode"
property.

The phandle provided by the clocks property of the child is the same as one for
the Flexcom parent.

For other properties, please refer to the documentations of the respective
device:
- ../serial/atmel-usart.txt
- ../spi/spi_atmel.txt
- ../i2c/i2c-at91.txt

Example:

flexcom@f8034000 {
	compatible = "atmel,sama5d2-flexcom";
	reg = <0xf8034000 0x200>;
	clocks = <&flx0_clk>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0xf8034000 0x800>;
	atmel,flexcom-mode = <2>;

	spi@400 {
		compatible = "atmel,at91rm9200-spi";
		reg = <0x400 0x200>;
		interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_flx0_default>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&flx0_clk>;
		clock-names = "spi_clk";
		atmel,fifo-size = <32>;

		flash@0 {
			compatible = "atmel,at25f512b";
			reg = <0>;
			spi-max-frequency = <20000000>;
		};
	};
};


code:
* Device tree bindings for Atmel GPBR (General Purpose Backup Registers)

The GPBR are a set of battery-backed registers.

Required properties:
- compatible:		Should be one of the following:
			"atmel,at91sam9260-gpbr", "syscon"
			"microchip,sam9x60-gpbr", "syscon"
- reg:			contains offset/length value of the GPBR memory
			region.

Example:

gpbr: gpbr@fffffd50 {
	compatible = "atmel,at91sam9260-gpbr", "syscon";
	reg = <0xfffffd50 0x10>;
};


code:
Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver

Required properties:
 - compatible: value should be one of the following:
   "atmel,at91sam9n12-hlcdc"
   "atmel,at91sam9x5-hlcdc"
   "atmel,sama5d2-hlcdc"
   "atmel,sama5d3-hlcdc"
   "atmel,sama5d4-hlcdc"
   "microchip,sam9x60-hlcdc"
 - reg: base address and size of the HLCDC device registers.
 - clock-names: the name of the 3 clocks requested by the HLCDC device.
   Should contain "periph_clk", "sys_clk" and "slow_clk".
 - clocks: should contain the 3 clocks requested by the HLCDC device.
 - interrupts: should contain the description of the HLCDC interrupt line

The HLCDC IP exposes two subdevices:
 - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt
 - a Display Controller: see ../display/atmel/hlcdc-dc.txt

Example:

	hlcdc: hlcdc@f0030000 {
		compatible = "atmel,sama5d3-hlcdc";
		reg = <0xf0030000 0x2000>;
		clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
		clock-names = "periph_clk","sys_clk", "slow_clk";
		interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;

		hlcdc-display-controller {
			compatible = "atmel,hlcdc-display-controller";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;

				hlcdc_panel_output: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&panel_input>;
				};
			};
		};

		hlcdc_pwm: hlcdc-pwm {
			compatible = "atmel,hlcdc-pwm";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_lcd_pwm>;
			#pwm-cells = <3>;
		};
	};


code:
* Device tree bindings for Atmel Bus Matrix

The Bus Matrix registers are used to configure Atmel SoCs internal bus
behavior (master/slave priorities, undefined burst length type, ...)

Required properties:
- compatible:		Should be one of the following
			"atmel,at91sam9260-matrix", "syscon"
			"atmel,at91sam9261-matrix", "syscon"
			"atmel,at91sam9263-matrix", "syscon"
			"atmel,at91sam9rl-matrix", "syscon"
			"atmel,at91sam9g45-matrix", "syscon"
			"atmel,at91sam9n12-matrix", "syscon"
			"atmel,at91sam9x5-matrix", "syscon"
			"atmel,sama5d3-matrix", "syscon"
			"microchip,sam9x60-matrix", "syscon"
- reg:			Contains offset/length value of the Bus Matrix
			memory region.

Example:

matrix: matrix@ffffec00 {
	compatible = "atmel,sama5d3-matrix", "syscon";
	reg = <0xffffec00 0x200>;
};


code:
* Device tree bindings for Atmel SMC (Static Memory Controller)

The SMC registers are used to configure Atmel EBI (External Bus Interface)
to interface with standard memory devices (NAND, NOR, SRAM or specialized
devices like FPGAs).

Required properties:
- compatible:		Should be one of the following
			"atmel,at91sam9260-smc", "syscon"
			"atmel,sama5d3-smc", "syscon"
			"atmel,sama5d2-smc", "syscon"
			"microchip,sam9x60-smc", "syscon"
- reg:			Contains offset/length value of the SMC memory
			region.

Example:

smc: smc@ffffc000 {
	compatible = "atmel,sama5d3-smc", "syscon";
	reg = <0xffffc000 0x1000>;
};


code:
KEYMILE bfticu Chassis Management FPGA

The bfticu is a multifunction device that manages the whole chassis.
Its main functionality is to collect IRQs from the whole chassis and signals
them to a single controller.

Required properties:
- compatible: "keymile,bfticu"
- interrupt-controller: the bfticu FPGA is an interrupt controller
- interrupts: the main IRQ line to signal the collected IRQs
- #interrupt-cells : is 2 and their usage is compliant to the 2 cells variant
  of Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- reg: access on the parent local bus (chip select, offset in chip select, size)

Example:

	chassis-mgmt@3,0 {
		compatible = "keymile,bfticu";
		interrupt-controller;
		#interrupt-cells = <2>;
		reg = <3 0 0x100>;
		interrupt-parent = <&mpic>;
		interrupts = <6 1 0 0>;
	};


code:
-------------------------------
BCM590xx Power Management Units
-------------------------------

Required properties:
- compatible: "brcm,bcm59056"
- reg: I2C slave address
- interrupts: interrupt for the PMU. Generic interrupt client node bindings
  are described in interrupt-controller/interrupts.txt

------------------
Voltage Regulators
------------------

Optional child nodes:
- regulators: container node for regulators following the generic
  regulator binding in regulator/regulator.txt

  The valid regulator node names for BCM59056 are:
  	rfldo, camldo1, camldo2, simldo1, simldo2, sdldo, sdxldo,
	mmcldo1, mmcldo2, audldo, micldo, usbldo, vibldo,
	csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr,
	gpldo1, gpldo2, gpldo3, gpldo4, gpldo5, gpldo6,
	vbus

Example:
	pmu: bcm59056@8 {
		compatible = "brcm,bcm59056";
		reg = <0x08>;
		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
		regulators {
			rfldo_reg: rfldo {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
			};

			...
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6318 GPIO System Controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description:
  Broadcom BCM6318 SoC GPIO system controller which provides a register map
  for controlling the GPIO and pins of the SoC.

properties:
  "#address-cells": true

  "#size-cells": true

  compatible:
    items:
      - const: brcm,bcm6318-gpio-sysctl
      - const: syscon
      - const: simple-mfd

  ranges:
    maxItems: 1

  reg:
    maxItems: 1

patternProperties:
  "^gpio@[0-9a-f]+$":
    # Child node
    type: object
    $ref: "../gpio/brcm,bcm6345-gpio.yaml"
    description:
      GPIO controller for the SoC GPIOs. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.

  "^pinctrl@[0-9a-f]+$":
    # Child node
    type: object
    $ref: "../pinctrl/brcm,bcm6318-pinctrl.yaml"
    description:
      Pin controller for the SoC pins. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml.

required:
  - "#address-cells"
  - compatible
  - ranges
  - reg
  - "#size-cells"

additionalProperties: false

examples:
  - |
    syscon@10000080 {
      #address-cells = <1>;
      #size-cells = <1>;
      compatible = "brcm,bcm6318-gpio-sysctl", "syscon", "simple-mfd";
      reg = <0x10000080 0x80>;
      ranges = <0 0x10000080 0x80>;

      gpio@0 {
        compatible = "brcm,bcm6318-gpio";
        reg-names = "dirout", "dat";
        reg = <0x0 0x8>, <0x8 0x8>;

        gpio-controller;
        gpio-ranges = <&pinctrl 0 0 50>;
        #gpio-cells = <2>;
      };

      pinctrl: pinctrl@10 {
        compatible = "brcm,bcm6318-pinctrl";
        reg = <0x18 0x10>, <0x54 0x18>;

        pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
          function = "ephy0_spd_led";
          pins = "gpio0";
        };

        pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
          function = "ephy1_spd_led";
          pins = "gpio1";
        };

        pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
          function = "ephy2_spd_led";
          pins = "gpio2";
        };

        pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
          function = "ephy3_spd_led";
          pins = "gpio3";
        };

        pinctrl_ephy0_act_led: ephy0_act_led-pins {
          function = "ephy0_act_led";
          pins = "gpio4";
        };

        pinctrl_ephy1_act_led: ephy1_act_led-pins {
          function = "ephy1_act_led";
          pins = "gpio5";
        };

        pinctrl_ephy2_act_led: ephy2_act_led-pins {
          function = "ephy2_act_led";
          pins = "gpio6";
        };

        pinctrl_ephy3_act_led: ephy3_act_led-pins {
          function = "ephy3_act_led";
          pins = "gpio7";
        };

        pinctrl_serial_led: serial_led-pins {
          pinctrl_serial_led_data: serial_led_data-pins {
            function = "serial_led_data";
            pins = "gpio6";
          };

          pinctrl_serial_led_clk: serial_led_clk-pins {
            function = "serial_led_clk";
            pins = "gpio7";
          };
        };

        pinctrl_inet_act_led: inet_act_led-pins {
          function = "inet_act_led";
          pins = "gpio8";
        };

        pinctrl_inet_fail_led: inet_fail_led-pins {
          function = "inet_fail_led";
          pins = "gpio9";
        };

        pinctrl_dsl_led: dsl_led-pins {
          function = "dsl_led";
          pins = "gpio10";
        };

        pinctrl_post_fail_led: post_fail_led-pins {
          function = "post_fail_led";
          pins = "gpio11";
        };

        pinctrl_wlan_wps_led: wlan_wps_led-pins {
          function = "wlan_wps_led";
          pins = "gpio12";
        };

        pinctrl_usb_pwron: usb_pwron-pins {
          function = "usb_pwron";
          pins = "gpio13";
        };

        pinctrl_usb_device_led: usb_device_led-pins {
          function = "usb_device_led";
          pins = "gpio13";
        };

        pinctrl_usb_active: usb_active-pins {
          function = "usb_active";
          pins = "gpio40";
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM63268 GPIO System Controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description:
  Broadcom BCM63268 SoC GPIO system controller which provides a register map
  for controlling the GPIO and pins of the SoC.

properties:
  "#address-cells": true

  "#size-cells": true

  compatible:
    items:
      - const: brcm,bcm63268-gpio-sysctl
      - const: syscon
      - const: simple-mfd

  ranges:
    maxItems: 1

  reg:
    maxItems: 1

patternProperties:
  "^gpio@[0-9a-f]+$":
    # Child node
    type: object
    $ref: "../gpio/brcm,bcm6345-gpio.yaml"
    description:
      GPIO controller for the SoC GPIOs. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.

  "^pinctrl@[0-9a-f]+$":
    # Child node
    type: object
    $ref: "../pinctrl/brcm,bcm63268-pinctrl.yaml"
    description:
      Pin controller for the SoC pins. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml.

required:
  - "#address-cells"
  - compatible
  - ranges
  - reg
  - "#size-cells"

additionalProperties: false

examples:
  - |
    syscon@100000c0 {
      #address-cells = <1>;
      #size-cells = <1>;
      compatible = "brcm,bcm63268-gpio-sysctl", "syscon", "simple-mfd";
      reg = <0x100000c0 0x80>;
      ranges = <0 0x100000c0 0x80>;

      gpio@0 {
        compatible = "brcm,bcm63268-gpio";
        reg-names = "dirout", "dat";
        reg = <0x0 0x8>, <0x8 0x8>;

        gpio-controller;
        gpio-ranges = <&pinctrl 0 0 52>;
        #gpio-cells = <2>;
      };

      pinctrl: pinctrl@10 {
        compatible = "brcm,bcm63268-pinctrl";
        reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;

        pinctrl_serial_led: serial_led-pins {
          pinctrl_serial_led_clk: serial_led_clk-pins {
            function = "serial_led_clk";
            pins = "gpio0";
          };

          pinctrl_serial_led_data: serial_led_data-pins {
            function = "serial_led_data";
            pins = "gpio1";
          };
        };

        pinctrl_hsspi_cs4: hsspi_cs4-pins {
          function = "hsspi_cs4";
          pins = "gpio16";
        };

        pinctrl_hsspi_cs5: hsspi_cs5-pins {
          function = "hsspi_cs5";
          pins = "gpio17";
        };

        pinctrl_hsspi_cs6: hsspi_cs6-pins {
          function = "hsspi_cs6";
          pins = "gpio8";
        };

        pinctrl_hsspi_cs7: hsspi_cs7-pins {
          function = "hsspi_cs7";
          pins = "gpio9";
        };

        pinctrl_adsl_spi: adsl_spi-pins {
          pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
            function = "adsl_spi_miso";
            pins = "gpio18";
          };

          pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
            function = "adsl_spi_mosi";
            pins = "gpio19";
          };
        };

        pinctrl_vreq_clk: vreq_clk-pins {
          function = "vreq_clk";
          pins = "gpio22";
        };

        pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
          function = "pcie_clkreq_b";
          pins = "gpio23";
        };

        pinctrl_robosw_led_clk: robosw_led_clk-pins {
          function = "robosw_led_clk";
          pins = "gpio30";
        };

        pinctrl_robosw_led_data: robosw_led_data-pins {
          function = "robosw_led_data";
          pins = "gpio31";
        };

        pinctrl_nand: nand-pins {
          function = "nand";
          group = "nand_grp";
        };

        pinctrl_gpio35_alt: gpio35_alt-pins {
          function = "gpio35_alt";
          pin = "gpio35";
        };

        pinctrl_dectpd: dectpd-pins {
          function = "dectpd";
          group = "dectpd_grp";
        };

        pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
          function = "vdsl_phy_override_0";
          group = "vdsl_phy_override_0_grp";
        };

        pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
          function = "vdsl_phy_override_1";
          group = "vdsl_phy_override_1_grp";
        };

        pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
          function = "vdsl_phy_override_2";
          group = "vdsl_phy_override_2_grp";
        };

        pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
          function = "vdsl_phy_override_3";
          group = "vdsl_phy_override_3_grp";
        };

        pinctrl_dsl_gpio8: dsl_gpio8-pins {
          function = "dsl_gpio8";
          group = "dsl_gpio8";
        };

        pinctrl_dsl_gpio9: dsl_gpio9-pins {
          function = "dsl_gpio9";
          group = "dsl_gpio9";
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6328-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6328 GPIO System Controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description:
  Broadcom BCM6328 SoC GPIO system controller which provides a register map
  for controlling the GPIO and pins of the SoC.

properties:
  "#address-cells": true

  "#size-cells": true

  compatible:
    items:
      - const: brcm,bcm6328-gpio-sysctl
      - const: syscon
      - const: simple-mfd

  ranges:
    maxItems: 1

  reg:
    maxItems: 1

patternProperties:
  "^gpio@[0-9a-f]+$":
    # Child node
    type: object
    $ref: "../gpio/brcm,bcm6345-gpio.yaml"
    description:
      GPIO controller for the SoC GPIOs. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.

  "^pinctrl@[0-9a-f]+$":
    # Child node
    type: object
    $ref: "../pinctrl/brcm,bcm6328-pinctrl.yaml"
    description:
      Pin controller for the SoC pins. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml.

required:
  - "#address-cells"
  - compatible
  - ranges
  - reg
  - "#size-cells"

additionalProperties: false

examples:
  - |
    syscon@10000080 {
      #address-cells = <1>;
      #size-cells = <1>;
      compatible = "brcm,bcm6328-gpio-sysctl", "syscon", "simple-mfd";
      reg = <0x10000080 0x80>;
      ranges = <0 0x10000080 0x80>;

      gpio@0 {
        compatible = "brcm,bcm6328-gpio";
        reg-names = "dirout", "dat";
        reg = <0x0 0x8>, <0x8 0x8>;

        gpio-controller;
        gpio-ranges = <&pinctrl 0 0 32>;
        #gpio-cells = <2>;
      };

      pinctrl: pinctrl@18 {
        compatible = "brcm,bcm6328-pinctrl";
        reg = <0x18 0x10>;

        pinctrl_serial_led: serial_led-pins {
          pinctrl_serial_led_data: serial_led_data-pins {
            function = "serial_led_data";
            pins = "gpio6";
          };

          pinctrl_serial_led_clk: serial_led_clk-pins {
            function = "serial_led_clk";
            pins = "gpio7";
          };
        };

        pinctrl_inet_act_led: inet_act_led-pins {
          function = "inet_act_led";
          pins = "gpio11";
        };

        pinctrl_pcie_clkreq: pcie_clkreq-pins {
          function = "pcie_clkreq";
          pins = "gpio16";
        };

        pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
          function = "led";
          pins = "gpio17";
        };

        pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
          function = "led";
          pins = "gpio18";
        };

        pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
          function = "led";
          pins = "gpio19";
        };

        pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
          function = "led";
          pins = "gpio20";
        };

        pinctrl_ephy0_act_led: ephy0_act_led-pins {
          function = "ephy0_act_led";
          pins = "gpio25";
        };

        pinctrl_ephy1_act_led: ephy1_act_led-pins {
          function = "ephy1_act_led";
          pins = "gpio26";
        };

        pinctrl_ephy2_act_led: ephy2_act_led-pins {
          function = "ephy2_act_led";
          pins = "gpio27";
        };

        pinctrl_ephy3_act_led: ephy3_act_led-pins {
          function = "ephy3_act_led";
          pins = "gpio28";
        };

        pinctrl_hsspi_cs1: hsspi_cs1-pins {
          function = "hsspi_cs1";
          pins = "hsspi_cs1";
        };

        pinctrl_usb_port1_device: usb_port1_device-pins {
          function = "usb_device_port";
          pins = "usb_port1";
        };

        pinctrl_usb_port1_host: usb_port1_host-pins {
          function = "usb_host_port";
          pins = "usb_port1";
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6358-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6358 GPIO System Controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description:
  Broadcom BCM6358 SoC GPIO system controller which provides a register map
  for controlling the GPIO and pins of the SoC.

properties:
  "#address-cells": true

  "#size-cells": true

  compatible:
    items:
      - const: brcm,bcm6358-gpio-sysctl
      - const: syscon
      - const: simple-mfd

  ranges:
    maxItems: 1

  reg:
    maxItems: 1

patternProperties:
  "^gpio@[0-9a-f]+$":
    # Child node
    type: object
    $ref: "../gpio/brcm,bcm6345-gpio.yaml"
    description:
      GPIO controller for the SoC GPIOs. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.

  "^pinctrl@[0-9a-f]+$":
    # Child node
    type: object
    $ref: "../pinctrl/brcm,bcm6358-pinctrl.yaml"
    description:
      Pin controller for the SoC pins. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml.

required:
  - "#address-cells"
  - compatible
  - ranges
  - reg
  - "#size-cells"

additionalProperties: false

examples:
  - |
    syscon@fffe0080 {
      #address-cells = <1>;
      #size-cells = <1>;
      compatible = "brcm,bcm6358-gpio-sysctl", "syscon", "simple-mfd";
      reg = <0xfffe0080 0x80>;
      ranges = <0 0xfffe0080 0x80>;

      gpio@0 {
        compatible = "brcm,bcm6358-gpio";
        reg-names = "dirout", "dat";
        reg = <0x0 0x8>, <0x8 0x8>;

        gpio-controller;
        gpio-ranges = <&pinctrl 0 0 40>;
        #gpio-cells = <2>;
      };

      pinctrl: pinctrl@18 {
        compatible = "brcm,bcm6358-pinctrl";
        reg = <0x18 0x4>;

        pinctrl_ebi_cs: ebi_cs-pins {
          function = "ebi_cs";
          groups = "ebi_cs_grp";
        };

        pinctrl_uart1: uart1-pins {
          function = "uart1";
          groups = "uart1_grp";
        };

        pinctrl_serial_led: serial_led-pins {
          function = "serial_led";
          groups = "serial_led_grp";
        };

        pinctrl_legacy_led: legacy_led-pins {
          function = "legacy_led";
          groups = "legacy_led_grp";
        };

        pinctrl_led: led-pins {
          function = "led";
          groups = "led_grp";
        };

        pinctrl_spi_cs_23: spi_cs-pins {
          function = "spi_cs";
          groups = "spi_cs_grp";
        };

        pinctrl_utopia: utopia-pins {
          function = "utopia";
          groups = "utopia_grp";
        };

        pinctrl_pwm_syn_clk: pwm_syn_clk-pins {
          function = "pwm_syn_clk";
          groups = "pwm_syn_clk_grp";
        };

        pinctrl_sys_irq: sys_irq-pins {
          function = "sys_irq";
          groups = "sys_irq_grp";
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6362 GPIO System Controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description:
  Broadcom BCM6362 SoC GPIO system controller which provides a register map
  for controlling the GPIO and pins of the SoC.

properties:
  "#address-cells": true

  "#size-cells": true

  compatible:
    items:
      - const: brcm,bcm6362-gpio-sysctl
      - const: syscon
      - const: simple-mfd

  ranges:
    maxItems: 1

  reg:
    maxItems: 1

patternProperties:
  "^gpio@[0-9a-f]+$":
    # Child node
    type: object
    $ref: "../gpio/brcm,bcm6345-gpio.yaml"
    description:
      GPIO controller for the SoC GPIOs. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.

  "^pinctrl@[0-9a-f]+$":
    # Child node
    type: object
    $ref: "../pinctrl/brcm,bcm6362-pinctrl.yaml"
    description:
      Pin controller for the SoC pins. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml.

required:
  - "#address-cells"
  - compatible
  - ranges
  - reg
  - "#size-cells"

additionalProperties: false

examples:
  - |
    syscon@10000080 {
      #address-cells = <1>;
      #size-cells = <1>;
      compatible = "brcm,bcm6362-gpio-sysctl", "syscon", "simple-mfd";
      reg = <0x10000080 0x80>;
      ranges = <0 0x10000080 0x80>;

      gpio@0 {
        compatible = "brcm,bcm6362-gpio";
        reg-names = "dirout", "dat";
        reg = <0x0 0x8>, <0x8 0x8>;

        gpio-controller;
        gpio-ranges = <&pinctrl 0 0 48>;
        #gpio-cells = <2>;
      };

      pinctrl: pinctrl@18 {
        compatible = "brcm,bcm6362-pinctrl";
        reg = <0x18 0x10>, <0x38 0x4>;

        pinctrl_usb_device_led: usb_device_led-pins {
          function = "usb_device_led";
          pins = "gpio0";
        };

        pinctrl_sys_irq: sys_irq-pins {
          function = "sys_irq";
          pins = "gpio1";
        };

        pinctrl_serial_led: serial_led-pins {
          pinctrl_serial_led_clk: serial_led_clk-pins {
            function = "serial_led_clk";
            pins = "gpio2";
          };

          pinctrl_serial_led_data: serial_led_data-pins {
            function = "serial_led_data";
            pins = "gpio3";
          };
        };

        pinctrl_robosw_led_data: robosw_led_data-pins {
          function = "robosw_led_data";
          pins = "gpio4";
        };

        pinctrl_robosw_led_clk: robosw_led_clk-pins {
          function = "robosw_led_clk";
          pins = "gpio5";
        };

        pinctrl_robosw_led0: robosw_led0-pins {
          function = "robosw_led0";
          pins = "gpio6";
        };

        pinctrl_robosw_led1: robosw_led1-pins {
          function = "robosw_led1";
          pins = "gpio7";
        };

        pinctrl_inet_led: inet_led-pins {
          function = "inet_led";
          pins = "gpio8";
        };

        pinctrl_spi_cs2: spi_cs2-pins {
          function = "spi_cs2";
          pins = "gpio9";
        };

        pinctrl_spi_cs3: spi_cs3-pins {
          function = "spi_cs3";
          pins = "gpio10";
        };

        pinctrl_ntr_pulse: ntr_pulse-pins {
          function = "ntr_pulse";
          pins = "gpio11";
        };

        pinctrl_uart1_scts: uart1_scts-pins {
          function = "uart1_scts";
          pins = "gpio12";
        };

        pinctrl_uart1_srts: uart1_srts-pins {
          function = "uart1_srts";
          pins = "gpio13";
        };

        pinctrl_uart1: uart1-pins {
          pinctrl_uart1_sdin: uart1_sdin-pins {
            function = "uart1_sdin";
            pins = "gpio14";
          };

          pinctrl_uart1_sdout: uart1_sdout-pins {
            function = "uart1_sdout";
            pins = "gpio15";
          };
        };

        pinctrl_adsl_spi: adsl_spi-pins {
          pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
            function = "adsl_spi_miso";
            pins = "gpio16";
          };

          pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
            function = "adsl_spi_mosi";
            pins = "gpio17";
          };

          pinctrl_adsl_spi_clk: adsl_spi_clk-pins {
            function = "adsl_spi_clk";
            pins = "gpio18";
          };

          pinctrl_adsl_spi_cs: adsl_spi_cs-pins {
            function = "adsl_spi_cs";
            pins = "gpio19";
          };
        };

        pinctrl_ephy0_led: ephy0_led-pins {
          function = "ephy0_led";
          pins = "gpio20";
        };

        pinctrl_ephy1_led: ephy1_led-pins {
          function = "ephy1_led";
          pins = "gpio21";
        };

        pinctrl_ephy2_led: ephy2_led-pins {
          function = "ephy2_led";
          pins = "gpio22";
        };

        pinctrl_ephy3_led: ephy3_led-pins {
          function = "ephy3_led";
          pins = "gpio23";
        };

        pinctrl_ext_irq0: ext_irq0-pins {
          function = "ext_irq0";
          pins = "gpio24";
        };

        pinctrl_ext_irq1: ext_irq1-pins {
          function = "ext_irq1";
          pins = "gpio25";
        };

        pinctrl_ext_irq2: ext_irq2-pins {
          function = "ext_irq2";
          pins = "gpio26";
        };

        pinctrl_ext_irq3: ext_irq3-pins {
          function = "ext_irq3";
          pins = "gpio27";
        };

        pinctrl_nand: nand-pins {
          function = "nand";
          group = "nand_grp";
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6368 GPIO System Controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description:
  Broadcom BCM6368 SoC GPIO system controller which provides a register map
  for controlling the GPIO and pins of the SoC.

properties:
  "#address-cells": true

  "#size-cells": true

  compatible:
    items:
      - const: brcm,bcm6368-gpio-sysctl
      - const: syscon
      - const: simple-mfd

  ranges:
    maxItems: 1

  reg:
    maxItems: 1

patternProperties:
  "^gpio@[0-9a-f]+$":
    # Child node
    type: object
    $ref: "../gpio/brcm,bcm6345-gpio.yaml"
    description:
      GPIO controller for the SoC GPIOs. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.

  "^pinctrl@[0-9a-f]+$":
    # Child node
    type: object
    $ref: "../pinctrl/brcm,bcm6368-pinctrl.yaml"
    description:
      Pin controller for the SoC pins. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml.

required:
  - "#address-cells"
  - compatible
  - ranges
  - reg
  - "#size-cells"

additionalProperties: false

examples:
  - |
    syscon@10000080 {
      #address-cells = <1>;
      #size-cells = <1>;
      compatible = "brcm,bcm6368-gpio-sysctl", "syscon", "simple-mfd";
      reg = <0x10000080 0x80>;
      ranges = <0 0x10000080 0x80>;

      gpio@0 {
        compatible = "brcm,bcm6368-gpio";
        reg-names = "dirout", "dat";
        reg = <0x0 0x8>, <0x8 0x8>;

        gpio-controller;
        gpio-ranges = <&pinctrl 0 0 38>;
        #gpio-cells = <2>;
      };

      pinctrl: pinctrl@18 {
        compatible = "brcm,bcm6368-pinctrl";
        reg = <0x18 0x4>, <0x38 0x4>;

        pinctrl_analog_afe_0: analog_afe_0-pins {
          function = "analog_afe_0";
          pins = "gpio0";
        };

        pinctrl_analog_afe_1: analog_afe_1-pins {
          function = "analog_afe_1";
          pins = "gpio1";
        };

        pinctrl_sys_irq: sys_irq-pins {
          function = "sys_irq";
          pins = "gpio2";
        };

        pinctrl_serial_led: serial_led-pins {
          pinctrl_serial_led_data: serial_led_data-pins {
            function = "serial_led_data";
            pins = "gpio3";
          };

          pinctrl_serial_led_clk: serial_led_clk-pins {
            function = "serial_led_clk";
            pins = "gpio4";
          };
        };

        pinctrl_inet_led: inet_led-pins {
          function = "inet_led";
          pins = "gpio5";
        };

        pinctrl_ephy0_led: ephy0_led-pins {
          function = "ephy0_led";
          pins = "gpio6";
        };

        pinctrl_ephy1_led: ephy1_led-pins {
          function = "ephy1_led";
          pins = "gpio7";
        };

        pinctrl_ephy2_led: ephy2_led-pins {
          function = "ephy2_led";
          pins = "gpio8";
        };

        pinctrl_ephy3_led: ephy3_led-pins {
          function = "ephy3_led";
          pins = "gpio9";
        };

        pinctrl_robosw_led_data: robosw_led_data-pins {
          function = "robosw_led_data";
          pins = "gpio10";
        };

        pinctrl_robosw_led_clk: robosw_led_clk-pins {
          function = "robosw_led_clk";
          pins = "gpio11";
        };

        pinctrl_robosw_led0: robosw_led0-pins {
          function = "robosw_led0";
          pins = "gpio12";
        };

        pinctrl_robosw_led1: robosw_led1-pins {
          function = "robosw_led1";
          pins = "gpio13";
        };

        pinctrl_usb_device_led: usb_device_led-pins {
          function = "usb_device_led";
          pins = "gpio14";
        };

        pinctrl_pci: pci-pins {
          pinctrl_pci_req1: pci_req1-pins {
            function = "pci_req1";
            pins = "gpio16";
          };

          pinctrl_pci_gnt1: pci_gnt1-pins {
            function = "pci_gnt1";
            pins = "gpio17";
          };

          pinctrl_pci_intb: pci_intb-pins {
            function = "pci_intb";
            pins = "gpio18";
          };

          pinctrl_pci_req0: pci_req0-pins {
            function = "pci_req0";
            pins = "gpio19";
          };

          pinctrl_pci_gnt0: pci_gnt0-pins {
            function = "pci_gnt0";
            pins = "gpio20";
          };
        };

        pinctrl_pcmcia: pcmcia-pins {
          pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
            function = "pcmcia_cd1";
            pins = "gpio22";
          };

          pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
            function = "pcmcia_cd2";
            pins = "gpio23";
          };

          pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
            function = "pcmcia_vs1";
            pins = "gpio24";
          };

          pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
            function = "pcmcia_vs2";
            pins = "gpio25";
          };
        };

        pinctrl_ebi_cs2: ebi_cs2-pins {
          function = "ebi_cs2";
          pins = "gpio26";
        };

        pinctrl_ebi_cs3: ebi_cs3-pins {
          function = "ebi_cs3";
          pins = "gpio27";
        };

        pinctrl_spi_cs2: spi_cs2-pins {
          function = "spi_cs2";
          pins = "gpio28";
        };

        pinctrl_spi_cs3: spi_cs3-pins {
          function = "spi_cs3";
          pins = "gpio29";
        };

        pinctrl_spi_cs4: spi_cs4-pins {
          function = "spi_cs4";
          pins = "gpio30";
        };

        pinctrl_spi_cs5: spi_cs5-pins {
          function = "spi_cs5";
          pins = "gpio31";
        };

        pinctrl_uart1: uart1-pins {
          function = "uart1";
          group = "uart1_grp";
        };
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom CRU

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

description: |
  Broadcom CRU ("Clock and Reset Unit" or "Central Resource Unit") is a hardware
  block grouping smaller blocks. On Broadcom Northstar platform it contains e.g.
  clocks, pinctrl, USB PHY and thermal.

properties:
  compatible:
    items:
      - enum:
          - brcm,ns-cru
      - const: simple-mfd

  reg:
    description: CRU registers

  ranges: true

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

patternProperties:
  '^clock-controller@[a-f0-9]+$':
    $ref: ../clock/brcm,iproc-clocks.yaml

  '^phy@[a-f0-9]+$':
    $ref: ../phy/bcm-ns-usb2-phy.yaml

  '^pinctrl@[a-f0-9]+$':
    $ref: ../pinctrl/brcm,ns-pinmux.yaml

  '^syscon@[a-f0-9]+$':
    $ref: syscon.yaml

  '^thermal@[a-f0-9]+$':
    $ref: ../thermal/brcm,ns-thermal.yaml

additionalProperties: false

required:
  - reg

examples:
  - |
    #include <dt-bindings/clock/bcm-nsp.h>
    cru-bus@1800c100 {
        compatible = "brcm,ns-cru", "simple-mfd";
        reg = <0x1800c100 0x1d0>;
        ranges;
        #address-cells = <1>;
        #size-cells = <1>;

        clock-controller@100 {
            #clock-cells = <1>;
            compatible = "brcm,nsp-lcpll0";
            reg = <0x100 0x14>;
            clocks = <&osc>;
            clock-output-names = "lcpll0", "pcie_phy", "sdio", "ddr_phy";
        };

        clock-controller@140 {
            #clock-cells = <1>;
            compatible = "brcm,nsp-genpll";
            reg = <0x140 0x24>;
            clocks = <&osc>;
            clock-output-names = "genpll", "phy", "ethernetclk", "usbclk",
                                 "iprocfast", "sata1", "sata2";
        };

        phy@164 {
            compatible = "brcm,ns-usb2-phy";
            reg = <0x164 0x4>;
            brcm,syscon-clkset = <&clkset>;
            clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
            clock-names = "phy-ref-clk";
            #phy-cells = <0>;
        };

        clkset: syscon@180 {
            compatible = "brcm,cru-clkset", "syscon";
            reg = <0x180 0x4>;
        };

        pinctrl@1c0 {
            compatible = "brcm,bcm4708-pinmux";
            reg = <0x1c0 0x24>;
            reg-names = "cru_gpio_control";
        };

        thermal@2c0 {
            compatible = "brcm,ns-thermal";
            reg = <0x2c0 0x10>;
            #thermal-sensor-cells = <0>;
        };
    };


code:
Broadcom iProc Chip Device Resource Unit (CDRU)

Various Broadcom iProc SoCs have a set of registers that provide various
chip specific device and resource configurations. This node allows access to
these CDRU registers via syscon.

Required properties:
- compatible: should contain:
		"brcm,sr-cdru", "syscon" for Stingray
- reg: base address and range of the CDRU registers

Example:
	cdru: syscon@6641d000 {
		compatible = "brcm,sr-cdru", "syscon";
		reg = <0 0x6641d000 0 0x400>;
	};


code:
Broadcom iProc Multi Host Bridge (MHB)

Certain Broadcom iProc SoCs have a multi host bridge (MHB) block that controls
the connection and configuration of 1) internal PCIe serdes; 2) PCIe endpoint
interface; 3) access to the Nitro (network processing) engine

This node allows access to these MHB registers via syscon.

Required properties:
- compatible: should contain:
		"brcm,sr-mhb", "syscon" for Stingray
- reg: base address and range of the MHB registers

Example:
	mhb: syscon@60401000 {
		compatible = "brcm,sr-mhb", "syscon";
		reg = <0 0x60401000 0 0x38c>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,misc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom's MISC block

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

description: |
  Broadcom's MISC is a hardware block used on some SoCs (e.g. bcm63xx and
  bcm4908). It's used to implement some simple functions like a watchdog, PCIe
  reset, UniMAC control and more.

properties:
  compatible:
    items:
      - const: brcm,misc
      - const: simple-mfd

  reg:
    description: MISC block registers

  ranges: true

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

patternProperties:
  '^reset-controller@[a-f0-9]+$':
    $ref: ../reset/brcm,bcm4908-misc-pcie-reset.yaml

additionalProperties: false

required:
  - reg
  - '#address-cells'
  - '#size-cells'

examples:
  - |
    misc@ff802600 {
        compatible = "brcm,misc", "simple-mfd";
        reg = <0xff802600 0xe4>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x0 0xe4>;

        reset-controller@44 {
            compatible = "brcm,bcm4908-misc-pcie-reset";
            reg = <0x44 0x4>;
            #reset-cells = <1>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,twd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom's Timer-Watchdog (aka TWD)

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

description: |
  Broadcom has a Timer-Watchdog block used in multiple SoCs (e.g., BCM4908,
  BCM63xx, BCM7038). There are few variants available (they differ slightly in
  registers layout). This block consists of: timers, watchdog and optionally a
  software reset handler.

properties:
  compatible:
    items:
      - enum:
          - brcm,bcm4908-twd
          - brcm,bcm7038-twd
      - const: simple-mfd
      - const: syscon

  reg:
    maxItems: 1

  ranges: true

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

patternProperties:
  '^watchdog@[a-f0-9]+$':
    $ref: /schemas/watchdog/brcm,bcm7038-wdt.yaml

additionalProperties: false

required:
  - reg

examples:
  - |
    timer-mfd@ff800400 {
        compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
        reg = <0xff800400 0x4c>;
        ranges = <0x00000000 0xff800400 0x4c>;

        #address-cells = <1>;
        #size-cells = <1>;

        watchdog@28 {
            compatible = "brcm,bcm7038-wdt";
            reg = <0x28 0x8>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Canaan Kendryte K210 System Controller

maintainers:
  - Damien Le Moal <damien.lemoal@wdc.com>

description:
  Canaan Inc. Kendryte K210 SoC system controller which provides a
  register map for controlling the clocks, reset signals and pin power
  domains of the SoC.

properties:
  compatible:
    items:
      - const: canaan,k210-sysctl
      - const: syscon
      - const: simple-mfd

  clocks:
    maxItems: 1
    description:
      System controller Advanced Power Bus (APB) interface clock source.

  clock-names:
    items:
      - const: pclk

  reg:
    maxItems: 1

  clock-controller:
    # Child node
    type: object
    $ref: "../clock/canaan,k210-clk.yaml"
    description:
      Clock controller for the SoC clocks. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml.

  reset-controller:
    # Child node
    type: object
    $ref: "../reset/canaan,k210-rst.yaml"
    description:
      Reset controller for the SoC. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml.

  syscon-reboot:
    # Child node
    type: object
    $ref: "../power/reset/syscon-reboot.yaml"
    description:
      Reboot method for the SoC. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml.

required:
  - compatible
  - clocks
  - reg
  - clock-controller

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/k210-clk.h>
    #include <dt-bindings/reset/k210-rst.h>

    clocks {
      in0: oscllator {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <26000000>;
      };
    };

    sysctl: syscon@50440000 {
      compatible = "canaan,k210-sysctl",
                   "syscon", "simple-mfd";
      reg = <0x50440000 0x100>;
      clocks = <&sysclk K210_CLK_APB1>;
      clock-names = "pclk";

      sysclk: clock-controller {
        #clock-cells = <1>;
        compatible = "canaan,k210-clk";
        clocks = <&in0>;
      };

      sysrst: reset-controller {
        compatible = "canaan,k210-rst";
        #reset-cells = <1>;
      };

      reboot: syscon-reboot {
        compatible = "syscon-reboot";
        regmap = <&sysctl>;
        offset = <48>;
        mask = <1>;
        value = <1>;
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/cirrus,lochnagar.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cirrus Logic Lochnagar Audio Development Board

maintainers:
  - patches@opensource.cirrus.com

description: |
  Lochnagar is an evaluation and development board for Cirrus Logic
  Smart CODEC and Amp devices. It allows the connection of most Cirrus
  Logic devices on mini-cards, as well as allowing connection of
  various application processor systems to provide a full evaluation
  platform.  Audio system topology, clocking and power can all be
  controlled through the Lochnagar, allowing the device under test
  to be used in a variety of possible use cases.

  Also see these documents for generic binding information:
    [1] GPIO : ../gpio/gpio.txt

  And these for relevant defines:
    [2] include/dt-bindings/pinctrl/lochnagar.h
    [3] include/dt-bindings/clock/lochnagar.h

  And these documents for the required sub-node binding details:
    [4] Clock: ../clock/cirrus,lochnagar.yaml
    [5] Pinctrl: ../pinctrl/cirrus,lochnagar.yaml
    [6] Sound: ../sound/cirrus,lochnagar.yaml
    [7] Hardware Monitor: ../hwmon/cirrus,lochnagar.yaml

allOf:
  - if:
      properties:
        compatible:
          enum:
            - cirrus,lochnagar2
    then:
      properties:
        lochnagar-hwmon:
          type: object
          $ref: /schemas/hwmon/cirrus,lochnagar.yaml#

        lochnagar-sc:
          type: object
          $ref: /schemas/sound/cirrus,lochnagar.yaml#

properties:
  compatible:
    enum:
      - cirrus,lochnagar1
      - cirrus,lochnagar2

  reg:
    const: 0x22

  reset-gpios:
    maxItems: 1

  present-gpios:
    description: |
      Host present line, indicating the presence of a
      host system, see [1]. This can be omitted if the present line is
      tied in hardware.
    maxItems: 1

  lochnagar-clk:
    type: object
    $ref: /schemas/clock/cirrus,lochnagar.yaml#

  lochnagar-pmic32k:
    type: object
    $ref: /schemas/clock/fixed-clock.yaml#
    properties:
      clock-frequency:
        const: 32768

  lochnagar-clk12m:
    type: object
    $ref: /schemas/clock/fixed-clock.yaml#
    properties:
      clock-frequency:
        const: 12288000

  lochnagar-clk11m:
    type: object
    $ref: /schemas/clock/fixed-clock.yaml#
    properties:
      clock-frequency:
        const: 11298600

  lochnagar-clk24m:
    type: object
    $ref: /schemas/clock/fixed-clock.yaml#
    properties:
      clock-frequency:
        const: 24576000

  lochnagar-clk22m:
    type: object
    $ref: /schemas/clock/fixed-clock.yaml#
    properties:
      clock-frequency:
        const: 22579200

  lochnagar-clk8m:
    type: object
    $ref: /schemas/clock/fixed-clock.yaml#
    properties:
      clock-frequency:
        const: 8192000

  lochnagar-usb24m:
    type: object
    $ref: /schemas/clock/fixed-clock.yaml#
    properties:
      clock-frequency:
        const: 24576000

  lochnagar-usb12m:
    type: object
    $ref: /schemas/clock/fixed-clock.yaml#
    properties:
      clock-frequency:
        const: 12288000

  pinctrl:
    type: object
    $ref: /schemas/pinctrl/cirrus,lochnagar.yaml#

  lochnagar-hwmon:
    type: object
    $ref: /schemas/hwmon/cirrus,lochnagar.yaml#

  lochnagar-sc:
    type: object
    $ref: /schemas/sound/cirrus,lochnagar.yaml#

  VDDCORE:
    description:
      Initialisation data for the VDDCORE regulator, which supplies the
      CODECs digital core if not being provided by an internal regulator.
    type: object
    $ref: /schemas/regulator/regulator.yaml#
    unevaluatedProperties: false
    properties:
      compatible:
        enum:
          - cirrus,lochnagar2-vddcore

      SYSVDD-supply:
        description:
          Primary power supply for the Lochnagar.
    required:
      - compatible

  MICVDD:
    description:
      Initialisation data for the MICVDD regulator, which supplies the
      CODECs MICVDD.
    type: object
    $ref: /schemas/regulator/regulator.yaml#
    unevaluatedProperties: false
    properties:
      compatible:
        enum:
          - cirrus,lochnagar2-micvdd

      SYSVDD-supply:
        description:
          Primary power supply for the Lochnagar.
    required:
      - compatible

  MIC1VDD:
    description:
      Initialisation data for the MIC1VDD supplies.
    type: object
    $ref: /schemas/regulator/regulator.yaml#
    unevaluatedProperties: false
    properties:
      compatible:
        enum:
          - cirrus,lochnagar2-mic1vdd

      cirrus,micbias-input:
        description:
          A property selecting which of the CODEC minicard micbias outputs
          should be used.
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 4

      MICBIAS1-supply:
        description:
          Regulator supplies for the MIC1VDD outputs, supplying the digital
          microphones, normally supplied from the attached CODEC.
    required:
      - compatible

  MIC2VDD:
    description:
      Initialisation data for the MIC2VDD supplies.
    type: object
    $ref: /schemas/regulator/regulator.yaml#
    unevaluatedProperties: false
    properties:
      compatible:
        enum:
          - cirrus,lochnagar2-mic2vdd

      cirrus,micbias-input:
        description:
          A property selecting which of the CODEC minicard micbias outputs
          should be used.
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 4

      MICBIAS2-supply:
        description:
          Regulator supplies for the MIC2VDD outputs, supplying the digital
          microphones, normally supplied from the attached CODEC.
    required:
      - compatible

  VDD1V8:
    description:
      Recommended fixed regulator for the VDD1V8 regulator, which supplies
      the CODECs analog and 1.8V digital supplies.
    type: object
    $ref: /schemas/regulator/regulator.yaml#
    unevaluatedProperties: false
    properties:
      compatible:
        enum:
          - regulator-fixed

      regulator-min-microvolt:
        const: 1800000

      regulator-max-microvolt:
        const: 1800000

      vin-supply:
        description:
          Should be set to same supply as SYSVDD
    required:
      - compatible
      - regulator-min-microvolt
      - regulator-max-microvolt
      - regulator-boot-on
      - regulator-always-on
      - vin-supply

required:
  - compatible
  - reg
  - reset-gpios
  - lochnagar-clk
  - pinctrl

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/lochnagar.h>
    #include <dt-bindings/pinctrl/lochnagar.h>
    i2c@e0004000 {
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0xe0004000 0x1000>;

        lochnagar: lochnagar@22 {
            compatible = "cirrus,lochnagar2";
            reg = <0x22>;

            reset-gpios = <&gpio0 55 0>;
            present-gpios = <&gpio0 60 0>;

            lochnagarclk: lochnagar-clk {
                compatible = "cirrus,lochnagar2-clk";

                #clock-cells = <1>;
                clocks = <&clkaudio>, <&clkpmic>;
                clock-names = "ln-gf-mclk2", "ln-pmic-32k";

                assigned-clocks = <&lochnagarclk LOCHNAGAR_CDC_MCLK1>,
                                  <&lochnagarclk LOCHNAGAR_CDC_MCLK2>;
                assigned-clock-parents = <&clkaudio>, <&clkpmic>;
            };

            clkpmic: lochnagar-pmic32k {
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <32768>;
            };

            pinctrl {
                compatible = "cirrus,lochnagar-pinctrl";

                gpio-controller;
                #gpio-cells = <2>;
                gpio-ranges = <&lochnagar 0 0 LOCHNAGAR2_PIN_NUM_GPIOS>;

                pinctrl-names = "default";
                pinctrl-0 = <&pinsettings>;

                pinsettings: pin-settings {
                    ap2aif-pins {
                        input-enable;
                        groups = "gf-aif1";
                        function = "codec-aif3";
                    };
                    codec2aif-pins {
                        output-enable;
                        groups = "codec-aif3";
                        function = "gf-aif1";
                    };
                };
            };

            lochnagar-sc {
                compatible = "cirrus,lochnagar2-soundcard";

                #sound-dai-cells = <1>;

                clocks = <&lochnagarclk LOCHNAGAR_SOUNDCARD_MCLK>;
                clock-names = "mclk";
            };

            lochnagar-hwmon {
                compatible = "cirrus,lochnagar2-hwmon";
            };

            MIC1VDD {
                compatible = "cirrus,lochnagar2-mic1vdd";

                cirrus,micbias-input = <3>;
            };

            MICVDD {
                compatible = "cirrus,lochnagar2-micvdd";

                SYSVDD-supply = <&wallvdd>;

                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
            };

            VDD1V8 {
                compatible = "regulator-fixed";

                regulator-name = "VDD1V8";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
                regulator-boot-on;
                regulator-always-on;

                vin-supply = <&wallvdd>;
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/cirrus,madera.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cirrus Logic Madera class audio CODECs Multi-Functional Device

maintainers:
  - patches@opensource.cirrus.com

description: |
  These devices are audio SoCs with extensive digital capabilities and a range
  of analogue I/O.

  See also the child driver bindings in:

    bindings/pinctrl/cirrus,madera.yaml
    bindings/regulator/wlf,arizona.yaml
    bindings/sound/cirrus,madera.yaml

allOf:
  - $ref: /schemas/pinctrl/cirrus,madera.yaml#
  - $ref: /schemas/regulator/wlf,arizona.yaml#
  - $ref: /schemas/sound/cirrus,madera.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - cirrus,cs47l85
              - wlf,wm1840
    then:
      properties:
        SPKVDDL-supply:
          description:
            Left speaker driver power supply.

        SPKVDDR-supply:
          description:
            Right speaker driver power supply.

      required:
        - SPKVDDL-supply
        - SPKVDDR-supply
    else:
      required:
        - DCVDD-supply
  - if:
      properties:
        compatible:
          contains:
            enum:
              - cirrus,cs47l15
              - cirrus,cs47l35
    then:
      properties:
        SPKVDD-supply:
          description:
            Mono speaker driver power supply.

      required:
        - SPKVDD-supply
  - if:
      properties:
        compatible:
          contains:
            enum:
              - cirrus,cs47l35
              - cirrus,cs47l85
              - cirrus,cs47l90
              - cirrus,cs47l91
              - wlf,wm1840
    then:
      properties:
        DBVDD2-supply:
          description:
            Databus power supply.

      required:
        - DBVDD2-supply
  - if:
      properties:
        compatible:
          contains:
            enum:
              - cirrus,cs47l85
              - cirrus,cs47l90
              - cirrus,cs47l91
              - wlf,wm1840
    then:
      properties:
        DBVDD3-supply:
          description:
            Databus power supply.

        DBVDD4-supply:
          description:
            Databus power supply.
  - if:
      properties:
        compatible:
          contains:
            enum:
              - cirrus,cs47l15
    then:
      required:
        - MICVDD-supply
    else:
      properties:
        CPVDD2-supply:
          description:
            Secondary charge pump power supply.

      required:
        - CPVDD2-supply

properties:
  compatible:
    enum:
      - cirrus,cs47l15
      - cirrus,cs47l35
      - cirrus,cs47l85
      - cirrus,cs47l90
      - cirrus,cs47l91
      - cirrus,cs42l92
      - cirrus,cs47l92
      - cirrus,cs47l93
      - cirrus,wm1840

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    description:
      The first cell is the pin number. The second cell is reserved for
      future use and must be zero
    const: 2

  interrupt-controller: true

  '#interrupt-cells':
    description:
      The first cell is the IRQ number.
      The second cell is the flags, encoded as the trigger masks from
      bindings/interrupt-controller/interrupts.txt
    const: 2

  interrupts:
    maxItems: 1

  reset-gpios:
    description:
      One entry specifying the GPIO controlling /RESET.  As defined in
      bindings/gpio.txt.  Although optional, it is strongly recommended
      to use a hardware reset.
    maxItems: 1

  clocks:
    description:
      Should reference the clocks supplied on MCLK1, MCLK2 and MCLK3.
    minItems: 1
    maxItems: 3

  clock-names:
    description: |
      May contain up to three strings:
        "mclk1" For the clock supplied on MCLK1, recommended to be a
                high quality audio reference clock.
        "mclk2" For the clock supplied on MCLK2, required to be an
                always on 32k clock.
        "mclk3" For the clock supplied on MCLK3.
    oneOf:
      - items:
          - const: mclk1
      - items:
          - const: mclk2
      - items:
          - const: mclk3
      - items:
          - const: mclk1
          - const: mclk2
      - items:
          - const: mclk1
          - const: mclk3
      - items:
          - const: mclk2
          - const: mclk3
      - items:
          - const: mclk1
          - const: mclk2
          - const: mclk3

  AVDD-supply:
    description:
      Analogue power supply.

  DBVDD1-supply:
    description:
      Databus power supply.

  CPVDD1-supply:
    description:
      Charge pump power supply.

  DCVDD-supply:
    description:
      Digital power supply, optional on CS47L85, WM1840 where it can
      be supplied internally.

  MICVDD-supply:
    description:
      Microphone power supply, normally supplied internally except on
      cs47l24, wm1831 where it is mandatory.

required:
  - compatible
  - gpio-controller
  - '#gpio-cells'
  - interrupt-controller
  - '#interrupt-cells'
  - interrupts
  - AVDD-supply
  - DBVDD1-supply
  - CPVDD1-supply

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/sound/madera.h>
    i2c@e0004000 {
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0xe0004000 0x1000>;

        cs47l85: codec@1a {
            compatible = "cirrus,cs47l85";
            reg = <0x1a>;

            reset-gpios = <&gpio 0>;
            wlf,ldoena = <&gpio 1>;

            interrupt-controller;
            #interrupt-cells = <2>;
            interrupts = <4 1 0>;

            gpio-controller;
            #gpio-cells = <2>;

            AVDD-supply = <&vdd1v8>;
            DBVDD1-supply = <&vdd1v8>;
            DBVDD2-supply = <&vdd1v8>;
            DBVDD3-supply = <&vdd1v8>;
            DBVDD4-supply = <&vdd1v8>;
            CPVDD1-supply = <&vdd1v8>;
            CPVDD2-supply = <&vdd1v2>;
            SPKVDDL-supply = <&vdd5v>;
            SPKVDDR-supply = <&vdd5v>;

            clocks = <&clks 0>, <&clks 1>, <&clks 2>;
            clock-names = "mclk1", "mclk2", "mclk3";

            cirrus,dmic-ref = <0 0 MADERA_DMIC_REF_MICBIAS1>;
            cirrus,inmode = <
                MADERA_INMODE_SE   MADERA_INMODE_SE
                MADERA_INMODE_SE   MADERA_INMODE_SE
                MADERA_INMODE_DIFF MADERA_INMODE_DIFF
            >;
            cirrus,max-channels-clocked = <2 0 0>;

            pinctrl-names = "default";
            pinctrl-0 = <&pinsettings>;

            pinsettings: pin-settings {
                aif1-pins {
                    groups = "aif1";
                    function = "aif1";
                    bias-bus-hold;
                };

                aif2-pins {
                    groups = "aif2";
                    function = "aif2";
                    bias-bus-hold;
                };

                aif3-pins {
                    groups = "aif3";
                    function = "aif3";
                    bias-bus-hold;
                };
            };
        };
    };


code:
* Dialog DA9052/53 Power Management Integrated Circuit (PMIC)

Required properties:
- compatible : Should be "dlg,da9052", "dlg,da9053-aa",
			 "dlg,da9053-ab", or "dlg,da9053-bb"

Optional properties:
- dlg,tsi-as-adc : Boolean, if set the X+, X-, Y+, Y- touchscreen
                    input lines are used as general purpose analogue
					input.
- tsiref-supply: Phandle to the regulator, which provides the reference
                 voltage for the TSIREF pin. Must be provided when the
			     touchscreen pins are used for ADC purposes.

Sub-nodes:
- regulators : Contain the regulator nodes. The DA9052/53 regulators are
  bound using their names as listed below:

    buck1     : regulator BUCK CORE
    buck2     : regulator BUCK PRO
    buck3     : regulator BUCK MEM
    buck4     : regulator BUCK PERI
    ldo1      : regulator LDO1
    ldo2      : regulator LDO2
    ldo3      : regulator LDO3
    ldo4      : regulator LDO4
    ldo5      : regulator LDO5
    ldo6      : regulator LDO6
    ldo7      : regulator LDO7
    ldo8      : regulator LDO8
    ldo9      : regulator LDO9
    ldo10     : regulator LDO10

  The bindings details of individual regulator device can be found in:
  Documentation/devicetree/bindings/regulator/regulator.txt

Examples:

i2c@63fc8000 { /* I2C1 */

	pmic: dialog@48 {
		compatible = "dlg,da9053-aa";
		reg = <0x48>;

		regulators {
			buck1 {
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <2075000>;
			};

			buck2 {
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <2075000>;
			};

			buck3 {
				regulator-min-microvolt = <925000>;
				regulator-max-microvolt = <2500000>;
			};

			buck4 {
				regulator-min-microvolt = <925000>;
				regulator-max-microvolt = <2500000>;
			};
		};
	};
};


code:
* Dialog DA9055 Power Management Integrated Circuit (PMIC)

DA9055 consists of a large and varied group of sub-devices (I2C Only):

Device			 Supply Names	 Description
------			 ------------	 -----------
da9055-gpio		:		: GPIOs
da9055-regulator	:		: Regulators
da9055-onkey		:		: On key
da9055-rtc		:		: RTC
da9055-hwmon		:		: ADC
da9055-watchdog		:		: Watchdog

The CODEC device in DA9055 has a separate, configurable I2C address and so
is instantiated separately from the PMIC.

For details on accompanying CODEC I2C device, see the following:
Documentation/devicetree/bindings/sound/da9055.txt

======

Required properties:
- compatible : Should be "dlg,da9055-pmic"
- reg: Specifies the I2C slave address (defaults to 0x5a but can be modified)
- interrupts: IRQ line info for da9055 chip.
- interrupt-controller: da9055 has internal IRQs (has own IRQ domain).
- #interrupt-cells: Should be 1, is the local IRQ number for da9055.

Sub-nodes:
- regulators : Contain the regulator nodes. The DA9055 regulators are
  bound using their names as listed below:

    buck1     : regulator BUCK1
    buck2     : regulator BUCK2
    ldo1      : regulator LDO1
    ldo2      : regulator LDO2
    ldo3      : regulator LDO3
    ldo4      : regulator LDO4
    ldo5      : regulator LDO5
    ldo6      : regulator LDO6

  The bindings details of individual regulator device can be found in:
  Documentation/devicetree/bindings/regulator/regulator.txt

Example:

	pmic: da9055-pmic@5a {
		compatible = "dlg,da9055-pmic";
		reg = <0x5a>;
		interrupt-parent = <&intc>;
		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <1>;

		regulators {
			buck1: BUCK1 {
				regulator-min-microvolt = <725000>;
				regulator-max-microvolt = <2075000>;
			};
			buck2: BUCK2 {
				regulator-min-microvolt = <925000>;
				regulator-max-microvolt = <2500000>;
			};
			ldo1: LDO1 {
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};