code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018 Nuvoton Technology

/ {
	pinctrl: pinctrl@f0800000 {
		pin8_input: pin8-input {
			pins = "GPIO8/LKGPO1";
			bias-disable;
			input-enable;
		};
		pin9_output_high: pin9-output-high {
			pins = "GPIO9/LKGPO2";
			bias-disable;
			output-high;
		};
		pin10_input: pin10-input {
			pins = "GPIO10/IOXHLD";
			bias-disable;
			input-enable;
		};
		pin11_output_high: pin11-output-high {
			pins = "GPIO11/IOXHCK";
			bias-disable;
			output-high;
		};
		pin16_input: pin16-input {
			pins = "GPIO16/LKGPO0";
			bias-disable;
			input-enable;
		};
		pin24_output_high: pin24-output-high {
			pins = "GPIO24/IOXHDO";
			bias-disable;
			output-high;
		};
		pin25_output_low: pin25-output-low {
			pins = "GPIO25/IOXHDI";
			bias-disable;
			output-low;
		};
		pin32_output_high: pin32-output-high {
			pins = "GPIO32/nSPI0CS1";
			bias-disable;
			output-high;
		};
		pin61_output_high: pin61-output-high {
			pins = "GPO61/nDTR1_BOUT1/STRAP6";
			bias-disable;
			output-high;
		};
		pin62_output_high: pin62-output-high {
			pins = "GPO62/nRTST1/STRAP5";
			bias-disable;
			output-high;
		};
		pin63_output_high: pin63-output-high {
			pins = "GPO63/TXD1/STRAP4";
			bias-disable;
			output-high;
		};
		pin160_input: pin160-input {
			pins = "GPIO160/CLKOUT/RNGOSCOUT";
			bias-disable;
			input-enable;
		};
		pin162_input: pin162-input {
			pins = "GPIO162/SERIRQ";
			bias-disable;
			input-enable;
		};
		pin168_input: pin168-input {
			pins = "GPIO168/nCLKRUN/nESPIALERT";
			bias-disable;
			input-enable;
		};
		pin169_input: pin169-input {
			pins = "GPIO169/nSCIPME";
			bias-disable;
			input-enable;
		};
		pin170_input: pin170-input {
			pins = "GPIO170/nSMI";
			bias-disable;
			input-enable;
		};
		pin187_output_high: pin187-output-high {
			pins = "GPIO187/nSPI3CS1";
			bias-disable;
			output-high;
		};
		pin190_input: pin190-input {
			pins = "GPIO190/nPRD_SMI";
			bias-disable;
			input-enable;
		};
		pin191_output_high: pin191-output-high {
			pins = "GPIO191";
			bias-disable;
			output-high;
		};
		pin192_output_high: pin192-output-high {
			pins = "GPIO192";
			bias-disable;
			output-high;
		};
		pin197_output_low: pin197-output-low {
			pins = "GPIO197/SMB0DEN";
			bias-disable;
			output-low;
		};
		pin218_input: pin218-input {
			pins = "GPIO218/nWDO1";
			bias-disable;
			input-enable;
		};
		pin219_output_low: pin219-output-low {
			pins = "GPIO219/nWDO2";
			bias-disable;
			output-low;
		};
		pin220_output_low: pin220-output-low {
			pins = "GPIO220/SMB12SCL";
			bias-disable;
			output-low;
		};
		pin221_output_high: pin221-output-high {
			pins = "GPIO221/SMB12SDA";
			bias-disable;
			output-high;
		};
		pin222_input: pin222-input {
			pins = "GPIO222/SMB13SCL";
			bias-disable;
			input-enable;
		};
		pin223_output_low: pin223-output-low {
			pins = "GPIO223/SMB13SDA";
			bias-disable;
			output-low;
		};
		pin228_output_low: pin228-output-low {
			pins = "GPIO228/nSPIXCS1";
			bias-disable;
			output-low;
		};
		pin231_output_high: pin231-output-high {
			pins = "GPIO230/SPIXD3";
			bias-disable;
			output-high;
		};
		pin255_input: pin255-input {
			pins = "GPI255/DACOSEL";
			bias-disable;
			input-enable;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019 Quanta Computer Inc. Samuel.Jiang@quantatw.com

/ {
	pinctrl: pinctrl@f0800000 {
		gpio0ol_pins: gpio0ol-pins {
			pins = "GPIO0/IOX1DI";
			bias-disable;
			output-low;
		};
		gpio1ol_pins: gpio1ol-pins {
			pins = "GPIO1/IOX1LD";
			bias-disable;
			output-low;
		};
		gpio2ol_pins: gpio2ol-pins {
			pins = "GPIO2/IOX1CK";
			bias-disable;
			output-low;
		};
		gpio3ol_pins: gpio3ol-pins {
			pins = "GPIO3/IOX1D0";
			bias-disable;
			output-low;
		};
		gpio5_pins: gpio5-pins {
			pins = "GPIO5/IOX2LD/SMB1DSCL";
			bias-disable;
			input-enable;
		};
		gpio6_pins: gpio6-pins {
			pins = "GPIO6/IOX2CK/SMB2DSDA";
			bias-disable;
			input-enable;
		};
		gpio7_pins: gpio7-pins {
			pins = "GPIO7/IOX2D0/SMB2DSCL";
			bias-disable;
			input-enable;
		};
		gpio8o_pins: gpio8o-pins {
			pins = "GPIO8/LKGPO1";
			bias-disable;
			output-high;
		};
		gpio9ol_pins: gpio9ol-pins {
			pins = "GPIO9/LKGPO2";
			bias-disable;
			output-low;
		};
		gpio10_pins: gpio10-pins {
			pins = "GPIO10/IOXHLD";
			bias-disable;
			input-enable;
		};
		gpio11_pins: gpio11-pins {
			pins = "GPIO11/IOXHCK";
			bias-disable;
			input-enable;
		};
		gpio12ol_pins: gpio12ol-pins {
			pins = "GPIO12/GSPICK/SMB5BSCL";
			bias-disable;
			output-low;
		};
		gpio13ol_pins: gpio13ol-pins {
			pins = "GPIO13/GSPIDO/SMB5BSDA";
			bias-disable;
			output-low;
		};
		gpio14ol_pins: gpio14ol-pins {
			pins = "GPIO14/GSPIDI/SMB5CSCL";
			bias-disable;
			output-low;
		};
		gpio15ol_pins: gpio15ol-pins {
			pins = "GPIO15/GSPICS/SMB5CSDA";
			bias-disable;
			output-low;
		};
		gpio20_pins: gpio20-pins {
			pins = "GPIO20/SMB4CSDA/SMB15SDA";
			bias-disable;
			input-enable;
		};
		gpio21_pins: gpio21-pins {
			pins = "GPIO21/SMB4CSCL/SMB15SCL";
			bias-disable;
			input-enable;
		};
		gpio22o_pins: gpio22o-pins {
			pins = "GPIO22/SMB4DSDA/SMB14SDA";
			bias-disable;
			output-high;
		};
		gpio23_pins: gpio23-pins {
			pins = "GPIO23/SMB4DSCL/SMB14SCL";
			bias-disable;
			input-enable;
		};
		gpio24_pins: gpio24-pins {
			pins = "GPIO24/IOXHDO";
			bias-disable;
			input-enable;
		};
		gpio25_pins: gpio25-pins {
			pins = "GPIO25/IOXHDI";
			bias-disable;
			input-enable;
		};
		gpio30_pins: gpio30-pins {
			pins = "GPIO30/SMB3SDA";
			bias-disable;
			input-enable;
		};
		gpio31_pins: gpio31-pins {
			pins = "GPIO31/SMB3SCL";
			bias-disable;
			input-enable;
		};
		gpio37o_pins: gpio37o-pins {
			pins = "GPIO37/SMB3CSDA";
			bias-disable;
			output-high;
		};
		gpio38_pins: gpio38-pins {
			pins = "GPIO38/SMB3CSCL";
			bias-disable;
			input-enable;
		};
		gpio39_pins: gpio39-pins {
			pins = "GPIO39/SMB3BSDA";
			bias-disable;
			input-enable;
		};
		gpio40o_pins: gpio40o-pins {
			pins = "GPIO40/SMB3BSCL";
			bias-disable;
			output-high;
		};
		gpio59_pins: gpio59-pins {
			pins = "GPIO59/SMB3DSDA";
			bias-disable;
			input-enable;
		};
		gpio76_pins: gpio76-pins {
			pins = "GPIO76/FANIN12";
			bias-disable;
			input-enable;
		};
		gpio77_pins: gpio77-pins {
			pins = "GPIO77/FANIN13";
			bias-disable;
			input-enable;
		};
		gpio78o_pins: gpio78o-pins {
			pins = "GPIO78/FANIN14";
			bias-disable;
			output-high;
		};
		gpio79_pins: gpio79-pins {
			pins = "GPIO79/FANIN15";
			bias-disable;
			input-enable;
		};
		gpio82_pins: gpio82-pins {
			pins = "GPIO82/PWM2";
			bias-disable;
			input-enable;
		};
		gpio83_pins: gpio83-pins {
			pins = "GPIO83/PWM3";
			bias-disable;
			input-enable;
		};
		gpio84_pins: gpio84-pins {
			pins = "GPIO84/R2TXD0";
			bias-disable;
			input-enable;
		};
		gpio85o_pins: gpio85o-pins {
			pins = "GPIO85/R2TXD1";
			bias-disable;
			output-high;
		};
		gpio86ol_pins: gpio86ol-pins {
			pins = "GPIO86/R2TXEN";
			bias-disable;
			output-low;
		};
		gpio87_pins: gpio87-pins {
			pins = "GPIO87/R2RXD0";
			bias-disable;
			input-enable;
		};
		gpio88_pins: gpio88-pins {
			pins = "GPIO88/R2RXD1";
			bias-disable;
			input-enable;
		};
		gpio89_pins: gpio89-pins {
			pins = "GPIO89/R2CRSDV";
			bias-disable;
			input-enable;
		};
		gpio90_pins: gpio90-pins {
			pins = "GPIO90/R2RXERR";
			bias-disable;
			input-enable;
		};
		gpio93_pins: gpio93-pins {
			pins = "GPIO93/GA20/SMB5DSCL";
			bias-disable;
			input-enable;
		};
		gpio94ol_pins: gpio94ol-pins {
			pins = "GPIO94/nKBRST/SMB5DSDA";
			bias-disable;
			output-low;
		};
		gpio108ol_pins: gpio108ol-pins {
			pins = "GPIO108/RG1MDC";
			bias-disable;
			output-low;
		};
		gpio109ol_pins: gpio109ol-pins {
			pins = "GPIO109/RG1MDIO";
			bias-disable;
			output-low;
		};
		gpio110ol_pins: gpio110ol-pins {
			pins = "GPIO110/RG2TXD0/DDRV0";
			bias-disable;
			output-low;
		};
		gpio111ol_pins: gpio111ol-pins {
			pins = "GPIO111/RG2TXD1/DDRV1";
			bias-disable;
			output-low;
		};
		gpio112ol_pins: gpio112ol-pins {
			pins = "GPIO112/RG2TXD2/DDRV2";
			bias-disable;
			output-low;
		};
		gpio113ol_pins: gpio113ol-pins {
			pins = "GPIO113/RG2TXD3/DDRV3";
			bias-disable;
			output-low;
		};
		gpio114o_pins: gpio114o-pins {
			pins = "GPIO114/SMB0SCL";
			bias-disable;
			output-high;
		};
		gpio115_pins: gpio115-pins {
			pins = "GPIO115/SMB0SDA";
			bias-disable;
			input-enable;
		};
		gpio120_pins: gpio120-pins {
			pins = "GPIO120/SMB2CSDA";
			bias-disable;
			input-enable;
		};
		gpio121_pins: gpio121-pins {
			pins = "GPIO121/SMB2CSCL";
			bias-disable;
			input-enable;
		};
		gpio122_pins: gpio122-pins {
			pins = "GPIO122/SMB2BSDA";
			bias-disable;
			input-enable;
		};
		gpio123_pins: gpio123-pins {
			pins = "GPIO123/SMB2BSCL";
			bias-disable;
			input-enable;
		};
		gpio124_pins: gpio124-pins {
			pins = "GPIO124/SMB1CSDA";
			bias-disable;
			input-enable;
		};
		gpio125_pins: gpio125-pins {
			pins = "GPIO125/SMB1CSCL";
			bias-disable;
			input-enable;
		};
		gpio126_pins: gpio126-pins {
			pins = "GPIO126/SMB1BSDA";
			bias-disable;
			input-enable;
		};
		gpio127o_pins: gpio127o-pins {
			pins = "GPIO127/SMB1BSCL";
			bias-disable;
			output-high;
		};
		gpio136_pins: gpio136-pins {
			pins = "GPIO136/SD1DT0";
			bias-disable;
			input-enable;
		};
		gpio137_pins: gpio137-pins {
			pins = "GPIO137/SD1DT1";
			bias-disable;
			input-enable;
		};
		gpio138_pins: gpio138-pins {
			pins = "GPIO138/SD1DT2";
			bias-disable;
			input-enable;
		};
		gpio139_pins: gpio139-pins {
			pins = "GPIO139/SD1DT3";
			bias-disable;
			input-enable;
		};
		gpio140_pins: gpio140-pins {
			pins = "GPIO140/SD1CLK";
			bias-disable;
			input-enable;
		};
		gpio141_pins: gpio141-pins {
			pins = "GPIO141/SD1WP";
			bias-disable;
			input-enable;
		};
		gpio142_pins: gpio142-pins {
			pins = "GPIO142/SD1CMD";
			bias-disable;
			input-enable;
		};
		gpio143_pins: gpio143-pins {
			pins = "GPIO143/SD1CD/SD1PWR";
			bias-disable;
			input-enable;
		};
		gpio144_pins: gpio144-pins {
			pins = "GPIO144/PWM4";
			bias-disable;
			input-enable;
		};
		gpio145_pins: gpio145-pins {
			pins = "GPIO145/PWM5";
			bias-disable;
			input-enable;
		};
		gpio146_pins: gpio146-pins {
			pins = "GPIO146/PWM6";
			bias-disable;
			input-enable;
		};
		gpio147_pins: gpio147-pins {
			pins = "GPIO147/PWM7";
			bias-disable;
			input-enable;
		};
		gpio153o_pins: gpio153o-pins {
			pins = "GPIO153/MMCWP";
			bias-disable;
			output-high;
		};
		gpio155_pins: gpio155-pins {
			pins = "GPIO155/nMMCCD/nMMCRST";
			bias-disable;
			input-enable;
		};
		gpio160o_pins: gpio160o-pins {
			pins = "GPIO160/CLKOUT/RNGOSCOUT";
			bias-disable;
			output-high;
		};
		gpio169o_pins: gpio169o-pins {
			pins = "GPIO169/nSCIPME";
			bias-disable;
			output-high;
		};
		gpio188o_pins: gpio188o-pins {
			pins = "GPIO188/SPI3D2/nSPI3CS2";
			bias-disable;
			output-high;
		};
		gpio189_pins: gpio189-pins {
			pins = "GPIO189/SPI3D3/nSPI3CS3";
			bias-disable;
			input-enable;
		};
		gpio196_pins: gpio196-pins {
			pins = "GPIO196/SMB0CSCL";
			bias-disable;
			input-enable;
		};
		gpio197_pins: gpio197-pins {
			pins = "GPIO197/SMB0DEN";
			bias-disable;
			input-enable;
		};
		gpio198o_pins: gpio198o-pins {
			pins = "GPIO198/SMB0DSDA";
			bias-disable;
			output-high;
		};
		gpio199o_pins: gpio199o-pins {
			pins = "GPIO199/SMB0DSCL";
			bias-disable;
			output-high;
		};
		gpio200_pins: gpio200-pins {
			pins = "GPIO200/R2CK";
			input-enable;
			bias-disable;
		};
		gpio202_pins: gpio202-pins {
			pins = "GPIO202/SMB0CSDA";
			bias-disable;
			input-enable;
		};
		gpio203o_pins: gpio203o-pins {
			pins = "GPIO203/FANIN16";
			bias-disable;
			output-high;
		};
		gpio208_pins: gpio208-pins {
			pins = "GPIO208/RG2TXC/DVCK";
			bias-disable;
			input-enable;
		};
		gpio209ol_pins: gpio209ol-pins {
			pins = "GPIO209/RG2TXCTL/DDRV4";
			bias-disable;
			output-low;
		};
		gpio210ol_pins: gpio210ol-pins {
			pins = "GPIO210/RG2RXD0/DDRV5";
			bias-disable;
			output-low;
		};
		gpio211ol_pins: gpio211ol-pins {
			pins = "GPIO211/RG2RXD1/DDRV6";
			bias-disable;
			output-low;
		};
		gpio212ol_pins: gpio212ol-pins {
			pins = "GPIO212/RG2RXD2/DDRV7";
			bias-disable;
			output-low;
		};
		gpio213ol_pins: gpio213ol-pins {
			pins = "GPIO213/RG2RXD3/DDRV8";
			bias-disable;
			output-low;
		};
		gpio214ol_pins: gpio214ol-pins {
			pins = "GPIO214/RG2RXC/DDRV9";
			bias-disable;
			output-low;
		};
		gpio215ol_pins: gpio215ol-pins {
			pins = "GPIO215/RG2RXCTL/DDRV10";
			bias-disable;
			output-low;
		};
		gpio216ol_pins: gpio216ol-pins {
			pins = "GPIO216/RG2MDC/DDRV11";
			bias-disable;
			output-low;
		};
		gpio217ol_pins: gpio217ol-pins {
			pins = "GPIO217/RG2MDIO/DVHSYNC";
			bias-disable;
			output-low;
		};
		gpio224_pins: gpio224-pins {
			pins = "GPIO224/SPIXCK";
			bias-disable;
			input-enable;
		};
		gpio225ol_pins: gpio225ol-pins {
			pins = "GPO225/SPIXD0/STRAP12";
			bias-disable;
			output-low;
		};
		gpio226ol_pins: gpio226ol-pins {
			pins = "GPO226/SPIXD1/STRAP13";
			bias-disable;
			output-low;
		};
		gpio227ol_pins: gpio227ol-pins {
			pins = "GPIO227/nSPIXCS0";
			bias-disable;
			output-low;
		};
		gpio228o_pins: gpio228ol-pins {
			pins = "GPIO228/nSPIXCS1";
			bias-disable;
			output-high;
		};
		gpio229o_pins: gpio229o-pins {
			pins = "GPO229/SPIXD2/STRAP3";
			bias-disable;
			output-high;
		};
		gpio230_pins: gpio230-pins {
			pins = "GPIO230/SPIXD3";
			bias-disable;
			input-enable;
		};
		gpio231o_pins: gpio231o-pins {
			pins = "GPIO231/nCLKREQ";
			bias-disable;
			output-high;
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019 Nuvoton Technology <kwliu@nuvoton.com>
// Copyright (c) 2019 Quanta Computer Inc. <Samuel.Jiang@quantatw.com>

/dts-v1/;
#include "nuvoton-npcm750.dtsi"
#include "nuvoton-npcm750-runbmc-olympus-pincfg.dtsi"

#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Nuvoton npcm750 RunBMC Olympus";
	compatible = "nuvoton,npcm750";

	aliases {
		ethernet1 = &gmac0;
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serial3;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c7;
		i2c8 = &i2c8;
		i2c9 = &i2c9;
		i2c10 = &i2c10;
		i2c11 = &i2c11;
		i2c12 = &i2c12;
		i2c13 = &i2c13;
		spi0 = &spi0;
		spi1 = &spi1;
		fiu0 = &fiu0;
		fiu1 = &fiu3;
	};

	chosen {
		stdout-path = &serial3;
	};

	memory {
		reg = <0 0x40000000>;
	};

	iio-hwmon {
		compatible = "iio-hwmon";
		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
			<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>;
	};

	leds {
		compatible = "gpio-leds";
		heartbeat {
		label = "heartbeat";
			gpios = <&gpio3 14 1>;
		};

		identify {
			label = "identify";
			gpios = <&gpio3 15 1>;
		};
	};

	jtag {
		compatible = "nuvoton,npcm750-jtag";
		enable_pspi_jtag = <1>;
		pspi-index = <2>;
		tck {
			label = "tck";
			gpios = <&gpio0 19 0>; /* gpio19 */
			regbase = <0xf0010000 0x1000>;
		};

		tdi {
			label = "tdi";
			gpios = <&gpio0 18 0>; /* gpio18 */
			regbase = <0xf0010000 0x1000>;
		};

		tdo {
			label = "tdo";
			gpios = <&gpio0 17 0>; /* gpio17 */
			regbase = <0xf0010000 0x1000>;
		};
		tms {
			label = "tms";
			gpios = <&gpio0 16 0>; /* gpio16 */
			regbase = <0xf0010000 0x1000>;
		};
	};
};

&fiu0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0cs1_pins>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		spi-rx-bus-width = <2>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			bmc@0{
				label = "bmc";
				reg = <0x000000 0x2000000>;
			};
			u-boot@0 {
				label = "u-boot";
				reg = <0x0000000 0x80000>;
				read-only;
			};
			u-boot-env@100000{
				label = "u-boot-env";
				reg = <0x00100000 0x40000>;
			};
			kernel@200000 {
				label = "kernel";
				reg = <0x0200000 0x600000>;
			};
			rofs@800000 {
				label = "rofs";
				reg = <0x800000 0x1500000>;
			};
			rwfs@1d00000 {
				label = "rwfs";
				reg = <0x1d00000 0x300000>;
			};
		};
	};

	flash@1 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <1>;
		npcm,fiu-rx-bus-width = <2>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			spare1@0 {
				label = "spi0-cs1-spare1";
				reg = <0x0 0x800000>;
			};
			spare2@800000 {
				label = "spi0-cs1-spare2";
				reg = <0x800000 0x0>;
			};
		};
	};
};

&fiu3 {
	pinctrl-0 = <&spi3_pins>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		spi-rx-bus-width = <2>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			system1@0 {
				label = "spi3-system1";
				reg = <0x0 0x800000>;
			};
			system2@800000 {
				label = "spi3-system2";
				reg = <0x800000 0x0>;
			};
		};
	};
};

&gcr {
	mux-controller {
		compatible = "mmio-mux";
		#mux-control-cells = <1>;

		mux-reg-masks = <0x38 0x07>;
		idle-states = <6>;
	};
};

&gmac0 {
	phy-mode = "rgmii-id";
	snps,eee-force-disable;
	status = "okay";
};

&i2c1 {
	status = "okay";

	i2c-switch@70 {
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;
		i2c-mux-idle-disconnect;

		i2c_slot1a: i2c-bus@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		i2c_slot1b: i2c-bus@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};

		i2c_slot2a: i2c-bus@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};

		i2c_slot2b: i2c-bus@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};

		i2c_slot3: i2c-bus@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
		};

		i2c_slot4: i2c-bus@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
		};

		i2c_slot5: i2c-bus@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
		};
	};

	i2c-switch@71 {
		compatible = "nxp,pca9546";
		reg = <0x71>;
		#address-cells = <1>;
		#size-cells = <0>;
		i2c-mux-idle-disconnect;

		i2c_m2_s1: i2c-bus@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		i2c_m2_s2: i2c-bus@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
		i2c_m2_s3: i2c-bus@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};

		i2c_m2_s4: i2c-bus@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};
	};
};

&i2c2 {
	status = "okay";

	tmp421@4c {
		compatible = "ti,tmp421";
		reg = <0x4c>;
	};

	power-supply@58 {
		compatible = "delta,dps800";
		reg = <0x58>;
	};
};

&i2c3 {
	status = "okay";
};

&i2c4 {
	status = "okay";

	eeprom@54 {
		compatible = "atmel,24c64";
		reg = <0x54>;
	};
};

&i2c5 {
	status = "okay";

	i2c-slave-mqueue@10 {
		compatible = "i2c-slave-mqueue";
		reg = <(I2C_OWN_SLAVE_ADDRESS | 0x10)>;
	};
};

&i2c6 {
	status = "okay";

	ina219@40 {
		compatible = "ti,ina219";
		reg = <0x40>;
	};
	ina219@41 {
		compatible = "ti,ina219";
		reg = <0x41>;
	};
	ina219@44 {
		compatible = "ti,ina219";
		reg = <0x44>;
	};
	ina219@45 {
		compatible = "ti,ina219";
		reg = <0x45>;
	};
	tps53679@60 {
		compatible = "ti,tps53679";
		reg = <0x60>;
	};
	tps53659@62 {
		compatible = "ti,tps53659";
		reg = <0x62>;
	};
	tps53659@64 {
		compatible = "ti,tps53659";
		reg = <0x64>;
	};
	tps53622@67 {
		compatible = "ti,tps53622";
		reg = <0x67>;
	};
	tps53622@69 {
		compatible = "ti,tps53622";
		reg = <0x69>;
	};
	tps53679@70 {
		compatible = "ti,tps53679";
		reg = <0x70>;
	};
	tps53659@72 {
		compatible = "ti,tps53659";
		reg = <0x72>;
	};
	tps53659@74 {
		compatible = "ti,tps53659";
		reg = <0x74>;
	};
	tps53622@77 {
		compatible = "ti,tps53622";
		reg = <0x77>;
	};
};

&i2c7 {
	status = "okay";

	tmp421@4c {
		compatible = "ti,tmp421";
		reg = <0x4c>;
	};
};

&i2c8 {
	status = "okay";

	adm1278@11 {
		compatible = "adm1278";
		reg = <0x11>;
		Rsense = <500>;
	};
};

&i2c9 {
	status = "okay";
};

&i2c10 {
	status = "okay";

	gpio: pca9555@27 {
		compatible = "nxp,pca9555";
		reg = <0x27>;

		gpio-controller;
		#gpio-cells = <2>;
	};
};

&i2c11 {
	status = "okay";

	pca9539_g1a: pca9539-g1a@74 {
		compatible = "nxp,pca9539";
		reg = <0x74>;
		gpio-controller;
		#gpio-cells = <2>;
		reset-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
		G1A_P0_0 {
			gpio-hog;
			gpios = <0 0>;
			output-high;
			line-name = "TPM_BMC_ALERT_N";
		};
		G1A_P0_1 {
			gpio-hog;
			gpios = <1 0>;
			input;
			line-name = "FM_BIOS_TOP_SWAP";
		};
		G1A_P0_2 {
			gpio-hog;
			gpios = <2 0>;
			input;
			line-name = "FM_BIOS_PREFRB2_GOOD";
		};
		G1A_P0_3 {
			gpio-hog;
			gpios = <3 0>;
			input;
			line-name = "BMC_SATAXPCIE_0TO3_SEL";
		};
		G1A_P0_4 {
			gpio-hog;
			gpios = <4 0>;
			input;
			line-name = "BMC_SATAXPCIE_4TO7_SEL";
		};
		G1A_P0_5 {
			gpio-hog;
			gpios = <5 0>;
			output-low;
			line-name = "FM_UV_ADR_TRIGGER_EN_N";
		};
		G1A_P0_6 {
			gpio-hog;
			gpios = <6 0>;
			input;
			line-name = "RM_THROTTLE_EN_N";
		};
		G1A_P1_0 {
			gpio-hog;
			gpios = <8 0>;
			input;
			line-name = "FM_BMC_TPM_PRES_N";
		};
		G1A_P1_1 {
			gpio-hog;
			gpios = <9 0>;
			input;
			line-name = "FM_CPU0_SKTOCC_LVT3_N";
		};
		G1A_P1_2 {
			gpio-hog;
			gpios = <10 0>;
			input;
			line-name = "FM_CPU1_SKTOCC_LVT3_N";
		};
		G1A_P1_3 {
			gpio-hog;
			gpios = <11 0>;
			input;
			line-name = "PSU1_ALERT_N";
		};
		G1A_P1_4 {
			gpio-hog;
			gpios = <12 0>;
			input;
			line-name = "PSU2_ALERT_N";
		};
		G1A_P1_5 {
			gpio-hog;
			gpios = <13 0>;
			input;
			line-name = "H_CPU0_FAST_WAKE_LVT3_N";
		};
		G1A_P1_6 {
			gpio-hog;
			gpios = <14 0>;
			output-high;
			line-name = "I2C_MUX1_RESET_N";
		};
		G1A_P1_7 {
			gpio-hog;
			gpios = <15 0>;
			input;
			line-name = "FM_CPU_CATERR_LVT3_N";
		};
	};

	pca9539_g1b: pca9539-g1b@75 {
		compatible = "nxp,pca9539";
		reg = <0x75>;
		gpio-controller;
		#gpio-cells = <2>;
		G1B_P0_0 {
			gpio-hog;
			gpios = <0 0>;
			input;
			line-name = "PVDDQ_ABC_PINALERT_N";
		};
		G1B_P0_1 {
			gpio-hog;
			gpios = <1 0>;
			input;
			line-name = "PVDDQ_DEF_PINALERT_N";
		};
		G1B_P0_2 {
			gpio-hog;
			gpios = <2 0>;
			input;
			line-name = "PVDDQ_GHJ_PINALERT_N";
		};
		G1B_P0_3 {
			gpio-hog;
			gpios = <3 0>;
			input;
			line-name = "PVDDQ_KLM_PINALERT_N";
		};
		G1B_P0_5 {
			gpio-hog;
			gpios = <5 0>;
			input;
			line-name = "FM_BOARD_REV_ID0";
		};
		G1B_P0_6 {
			gpio-hog;
			gpios = <6 0>;
			input;
			line-name = "FM_BOARD_REV_ID1";
		};
		G1B_P0_7 {
			gpio-hog;
			gpios = <7 0>;
			input;
			line-name = "FM_BOARD_REV_ID2";
		};
		G1B_P1_0 {
			gpio-hog;
			gpios = <8 0>;
			input;
			line-name = "FM_OC_DETECT_EN_N";
		};
		G1B_P1_1 {
			gpio-hog;
			gpios = <9 0>;
			input;
			line-name = "FM_FLASH_DESC_OVERRIDE";
		};
		G1B_P1_2 {
			gpio-hog;
			gpios = <10 0>;
			output-low;
			line-name = "FP_PWR_ID_LED_N";
		};
		G1B_P1_3 {
			gpio-hog;
			gpios = <11 0>;
			output-low;
			line-name = "BMC_LED_PWR_GRN";
		};
		G1B_P1_4 {
			gpio-hog;
			gpios = <12 0>;
			output-low;
			line-name = "BMC_LED_PWR_AMBER";
		};
		G1B_P1_5 {
			gpio-hog;
			gpios = <13 0>;
			output-high;
			line-name = "FM_BMC_FAULT_LED_N";
		};
		G1B_P1_6 {
			gpio-hog;
			gpios = <14 0>;
			output-high;
			line-name = "FM_CPLD_BMC_PWRDN_N";
		};
		G1B_P1_7 {
			gpio-hog;
			gpios = <15 0>;
			output-high;
			line-name = "BMC_LED_CATERR_N";
		};
	};
};

&i2c12 {
	status = "okay";

	pca9539_g2a: pca9539-g2a@74 {
		compatible = "nxp,pca9539";
		reg = <0x74>;
		gpio-controller;
		#gpio-cells = <2>;
		reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
		G2A_P0_0 {
			gpio-hog;
			gpios = <0 0>;
			output-high;
			line-name = "BMC_PON_RST_REQ_N";
		};
		G2A_P0_1 {
			gpio-hog;
			gpios = <1 0>;
			output-high;
			line-name = "BMC_RST_IND_REQ_N";
		};
		G2A_P0_2 {
			gpio-hog;
			gpios = <2 0>;
			input;
			line-name = "RST_BMC_RTCRST";
		};
		G2A_P0_3 {
			gpio-hog;
			gpios = <3 0>;
			output-high;
			line-name = "FM_BMC_PWRBTN_OUT_N";
		};
		G2A_P0_4 {
			gpio-hog;
			gpios = <4 0>;
			output-high;
			line-name = "RST_BMC_SYSRST_BTN_OUT_N";
		};
		G2A_P0_5 {
			gpio-hog;
			gpios = <5 0>;
			output-high;
			line-name = "FM_BATTERY_SENSE_EN_N";
		};
		G2A_P0_6 {
			gpio-hog;
			gpios = <6 0>;
			output-high;
			line-name = "FM_BMC_READY_N";
		};
		G2A_P0_7 {
			gpio-hog;
			gpios = <7 0>;
			input;
			line-name = "IRQ_BMC_PCH_SMI_LPC_N";
		};
		G2A_P1_0 {
			gpio-hog;
			gpios = <8 0>;
			input;
			line-name = "FM_SLOT4_CFG0";
		};
		G2A_P1_1 {
			gpio-hog;
			gpios = <9 0>;
			input;
			line-name = "FM_SLOT4_CFG1";
		};
		G2A_P1_2 {
			gpio-hog;
			gpios = <10 0>;
			input;
			line-name = "FM_NVDIMM_EVENT_N";
		};
		G2A_P1_3 {
			gpio-hog;
			gpios = <11 0>;
			input;
			line-name = "PSU1_BLADE_EN_N";
		};
		G2A_P1_4 {
			gpio-hog;
			gpios = <12 0>;
			input;
			line-name = "BMC_PCH_FNM";
		};
		G2A_P1_5 {
			gpio-hog;
			gpios = <13 0>;
			input;
			line-name = "FM_SOL_UART_CH_SEL";
		};
		G2A_P1_6 {
			gpio-hog;
			gpios = <14 0>;
			input;
			line-name = "FM_BIOS_POST_CMPLT_N";
		};
	};

	pca9539_g2b: pca9539-g2b@75 {
		compatible = "nxp,pca9539";
		reg = <0x75>;
		gpio-controller;
		#gpio-cells = <2>;
		G2B_P0_0 {
			gpio-hog;
			gpios = <0 0>;
			input;
			line-name = "FM_CPU_MSMI_LVT3_N";
		};
		G2B_P0_1 {
			gpio-hog;
			gpios = <1 0>;
			input;
			line-name = "FM_BIOS_MRC_DEBUG_MSG_DIS";
		};
		G2B_P0_2 {
			gpio-hog;
			gpios = <2 0>;
			input;
			line-name = "FM_CPU1_DISABLE_BMC_N";
		};
		G2B_P0_3 {
			gpio-hog;
			gpios = <3 0>;
			output-low;
			line-name = "BMC_JTAG_SELECT";
		};
		G2B_P0_4 {
			gpio-hog;
			gpios = <4 0>;
			output-high;
			line-name = "PECI_MUX_SELECT";
		};
		G2B_P0_5 {
			gpio-hog;
			gpios = <5 0>;
			output-high;
			line-name = "I2C_MUX2_RESET_N";
		};
		G2B_P0_6 {
			gpio-hog;
			gpios = <6 0>;
			input;
			line-name = "FM_BMC_CPLD_PSU2_ON";
		};
		G2B_P0_7 {
			gpio-hog;
			gpios = <7 0>;
			output-high;
			line-name = "PSU2_ALERT_EN_N";
		};
		G2B_P1_0 {
			gpio-hog;
			gpios = <8 0>;
			output-high;
			line-name = "FM_CPU_BMC_INIT";
		};
		G2B_P1_1 {
			gpio-hog;
			gpios = <9 0>;
			output-high;
			line-name = "IRQ_BMC_PCH_SCI_LPC_N";
		};
		G2B_P1_2 {
			gpio-hog;
			gpios = <10 0>;
			output-low;
			line-name = "PMB_ALERT_EN_N";
		};
		G2B_P1_3 {
			gpio-hog;
			gpios = <11 0>;
			output-high;
			line-name = "FM_FAST_PROCHOT_EN_N";
		};
		G2B_P1_4 {
			gpio-hog;
			gpios = <12 0>;
			output-high;
			line-name = "BMC_NVDIMM_PRSNT_N";
		};
		G2B_P1_5 {
			gpio-hog;
			gpios = <13 0>;
			output-low;
			line-name = "FM_BACKUP_BIOS_SEL_H_BMC";
		};
		G2B_P1_6 {
			gpio-hog;
			gpios = <14 0>;
			output-high;
			line-name = "FM_PWRBRK_N";
		};
	};
};

&i2c13 {
	status = "okay";

	tmp75@4a {
		compatible = "ti,tmp75";
		reg = <0x4a>;
		status = "okay";
	};
	m24128_fru@51 {
		compatible = "atmel,24c128";
		reg = <0x51>;
		pagesize = <64>;
		status = "okay";
	};
};

&pwm_fan {
	pinctrl-names = "default";
	pinctrl-0 = <   &pwm0_pins &pwm1_pins
			&fanin0_pins &fanin1_pins
			&fanin2_pins &fanin3_pins
			&fanin4_pins &fanin5_pins
			&fanin6_pins &fanin7_pins
			&fanin8_pins &fanin9_pins
			&fanin10_pins &fanin11_pins>;
	status = "okay";

	fan@0 {
		reg = <0x00>;
		fan-tach-ch = /bits/ 8 <0x00 0x01>;
		cooling-levels = <127 255>;
	};
	fan@1 {
		reg = <0x01>;
		fan-tach-ch = /bits/ 8 <0x02 0x03>;
		cooling-levels = /bits/ 8 <127 255>;
	};
	fan@2 {
		reg = <0x02>;
		fan-tach-ch = /bits/ 8 <0x04 0x05>;
		cooling-levels = /bits/ 8 <127 255>;
	};
	fan@3 {
		reg = <0x03>;
		fan-tach-ch = /bits/ 8 <0x06 0x07>;
		cooling-levels = /bits/ 8 <127 255>;
	};
	fan@4 {
		reg = <0x04>;
		fan-tach-ch = /bits/ 8 <0x08 0x09>;
		cooling-levels = /bits/ 8 <127 255>;
	};
	fan@5 {
		reg = <0x05>;
		fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
		cooling-levels = /bits/ 8 <127 255>;
	};
	fan@6 {
		reg = <0x06>;
		fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
		cooling-levels = /bits/ 8 <127 255>;
	};
	fan@7 {
		reg = <0x07>;
		fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
		cooling-levels = /bits/ 8 <127 255>;
	};
};

&ehci1 {
	status = "okay";
};

&watchdog1 {
	status = "okay";
};

&rng {
	status = "okay";
};

&serial0 {
	status = "okay";
};

&serial1 {
	status = "okay";
};

&serial2 {
	status = "okay";
};

&serial3 {
	status = "okay";
};

&adc {
	#io-channel-cells = <1>;
	status = "okay";
};

&kcs1 {
	status = "okay";
};

&kcs2 {
	status = "okay";
};

&kcs3 {
	status = "okay";
};

&spi0 {
	cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&spi1 {
	status = "okay";
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <
			/******* RunBMC inside Module pins *******/
			&gpio0ol_pins
			&gpio1ol_pins
			&gpio2ol_pins
			&gpio3ol_pins
			&gpio8o_pins
			&gpio9ol_pins
			&gpio12ol_pins
			&gpio13ol_pins
			&gpio14ol_pins
			&gpio15ol_pins
			&gpio37o_pins
			&gpio38_pins
			&gpio39_pins
			&gpio94ol_pins
			&gpio108ol_pins
			&gpio109ol_pins
			&gpio111ol_pins
			&gpio112ol_pins
			&gpio113ol_pins
			&gpio208_pins
			&gpio209ol_pins
			&gpio210ol_pins
			&gpio211ol_pins
			&gpio212ol_pins
			&gpio213ol_pins
			&gpio214ol_pins
			&gpio215ol_pins
			&gpio216ol_pins
			&gpio217ol_pins
			/******* RunBMC outside Connector pins *******/
			&gpio5_pins
			&gpio6_pins
			&gpio7_pins
			&gpio10_pins
			&gpio11_pins
			&gpio20_pins
			&gpio21_pins
			&gpio22o_pins
			&gpio23_pins
			&gpio24_pins
			&gpio25_pins
			&gpio30_pins
			&gpio31_pins
			&gpio40o_pins
			&gpio59_pins
			&gpio76_pins
			&gpio77_pins
			&gpio78o_pins
			&gpio79_pins
			&gpio82_pins
			&gpio83_pins
			&gpio84_pins
			&gpio85o_pins
			&gpio86ol_pins
			&gpio87_pins
			&gpio88_pins
			&gpio89_pins
			&gpio90_pins
			&gpio93_pins
			&gpio114o_pins
			&gpio115_pins
			&gpio120_pins
			&gpio121_pins
			&gpio122_pins
			&gpio123_pins
			&gpio124_pins
			&gpio125_pins
			&gpio126_pins
			&gpio127o_pins
			&gpio136_pins
			&gpio137_pins
			&gpio138_pins
			&gpio139_pins
			&gpio140_pins
			&gpio141_pins
			&gpio142_pins
			&gpio143_pins
			&gpio144_pins
			&gpio146_pins
			&gpio145_pins
			&gpio147_pins
			&gpio153o_pins
			&gpio155_pins
			&gpio160o_pins
			&gpio169o_pins
			&gpio188o_pins
			&gpio189_pins
			&gpio196_pins
			&gpio197_pins
			&gpio198o_pins
			&gpio199o_pins
			&gpio200_pins
			&gpio202_pins
			&gpio203o_pins
			&gpio224_pins
			&gpio225ol_pins
			&gpio226ol_pins
			&gpio227ol_pins
			&gpio228o_pins
			&gpio229o_pins
			&gpio230_pins
			&gpio231o_pins
			&ddc_pins
			&wdog1_pins
			&wdog2_pins
			>;
};


code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
// Copyright 2018 Google, Inc.

#include "nuvoton-common-npcm7xx.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "nuvoton,npcm750-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			clocks = <&clk NPCM7XX_CLK_CPU>;
			clock-names = "clk_cpu";
			reg = <0>;
			next-level-cache = <&l2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			clocks = <&clk NPCM7XX_CLK_CPU>;
			clock-names = "clk_cpu";
			reg = <1>;
			next-level-cache = <&l2>;
		};
	};

	soc {
		timer@3fe600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x3fe600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&clk NPCM7XX_CLK_AHB>;
		};
	};

	ahb {
		gmac1: eth@f0804000 {
			device_type = "network";
			compatible = "snps,dwmac";
			reg = <0xf0804000 0x2000>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			ethernet = <1>;
			clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
			clock-names = "stmmaceth", "clk_gmac";
			pinctrl-names = "default";
			pinctrl-0 = <&rg2_pins
					&rg2mdio_pins>;
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
// Copyright 2021 Jonathan Neuschäfer

/dts-v1/;

/* The last 16 MiB are dedicated to the GPU */
/memreserve/ 0x07000000 0x01000000;

#include "nuvoton-wpcm450.dtsi"

#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Supermicro X9SCi-LN4F BMC";
	compatible = "supermicro,x9sci-ln4f-bmc", "nuvoton,wpcm450";

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0 0x08000000>; /* 128 MiB */
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&key_pins>;

		uid {
			label = "UID button";
			linux,code = <KEY_HOME>;
			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&led_pins>;

		uid {
			label = "UID";
			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
		};

		heartbeat {
			label = "heartbeat";
			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
		};
	};
};

&fiu {
	status = "okay";

	flash@0 {
		reg = <0>;
		compatible = "jedec,spi-nor";
	};
};

&gpio0 {
	gpio-line-names =
		/* 0 */ "", "host-reset-control-n", "", "", "", "", "", "",
		/* 8 */ "", "", "", "", "power-chassis-control-n", "", "uid-button", "";
};

&gpio1 {
	gpio-line-names =
		/* 0 */ "", "", "", "", "led-heartbeat", "", "", "led-uid",
		/* 8 */ "", "", "", "", "", "", "", "";
};

&gpio4 {
	gpio-line-names =
		/* 0 */ "", "", "", "", "", "", "", "",
		/* 8 */ "", "", "", "", "", "", "", "power-chassis-good";
};

&pinctrl {
	key_pins: mux-keys {
		groups = "gspi", "sspi";
		function = "gpio";
	};

	led_pins: mux-leds {
		groups = "hg3", "hg0", "pwm4";
		function = "gpio";
	};
};

&serial0 {
	/*
	 * Debug serial port. TX is exposed on the right pad of unpopulated
	 * resistor R1247, RX on the right pad of R1162.
	 */
	status = "okay";
};

&serial1 {
	/* "Serial over LAN" port. Connected to ttyS2 of the host system. */
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
// Copyright 2021 Jonathan Neuschäfer

#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "nuvoton,wpcm450";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		gpio4 = &gpio4;
		gpio5 = &gpio5;
		gpio6 = &gpio6;
		gpio7 = &gpio7;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,arm926ej-s";
			device_type = "cpu";
			reg = <0>;
		};
	};

	clk24m: clock-24mhz {
		/* 24 MHz dummy clock */
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		#clock-cells = <0>;
	};

	refclk: clock-48mhz {
		/* 48 MHz reference oscillator */
		compatible = "fixed-clock";
		clock-output-names = "ref";
		clock-frequency = <48000000>;
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&aic>;
		ranges;

		gcr: syscon@b0000000 {
			compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd";
			reg = <0xb0000000 0x200>;
		};

		clk: clock-controller@b0000200 {
			compatible = "nuvoton,wpcm450-clk";
			reg = <0xb0000200 0x100>;
			clocks = <&refclk>;
			clock-names = "ref";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		serial0: serial@b8000000 {
			compatible = "nuvoton,wpcm450-uart";
			reg = <0xb8000000 0x20>;
			reg-shift = <2>;
			interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk24m>;
			pinctrl-names = "default";
			pinctrl-0 = <&bsp_pins>;
			status = "disabled";
		};

		serial1: serial@b8000100 {
			compatible = "nuvoton,wpcm450-uart";
			reg = <0xb8000100 0x20>;
			reg-shift = <2>;
			interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk24m>;
			status = "disabled";
		};

		timer0: timer@b8001000 {
			compatible = "nuvoton,wpcm450-timer";
			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0xb8001000 0x1c>;
			clocks = <&clk24m>;
		};

		watchdog0: watchdog@b800101c {
			compatible = "nuvoton,wpcm450-wdt";
			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0xb800101c 0x4>;
			clocks = <&clk24m>;
		};

		aic: interrupt-controller@b8002000 {
			compatible = "nuvoton,wpcm450-aic";
			reg = <0xb8002000 0x1000>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pinctrl: pinctrl@b8003000 {
			compatible = "nuvoton,wpcm450-pinctrl";
			reg = <0xb8003000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			gpio0: gpio@0 {
				reg = <0>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
					     <3 IRQ_TYPE_LEVEL_HIGH>,
					     <4 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
			};

			gpio1: gpio@1 {
				reg = <1>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
			};

			gpio2: gpio@2 {
				reg = <2>;
				gpio-controller;
				#gpio-cells = <2>;
			};

			gpio3: gpio@3 {
				reg = <3>;
				gpio-controller;
				#gpio-cells = <2>;
			};

			gpio4: gpio@4 {
				reg = <4>;
				gpio-controller;
				#gpio-cells = <2>;
			};

			gpio5: gpio@5 {
				reg = <5>;
				gpio-controller;
				#gpio-cells = <2>;
			};

			gpio6: gpio@6 {
				reg = <6>;
				gpio-controller;
				#gpio-cells = <2>;
			};

			gpio7: gpio@7 {
				reg = <7>;
				gpio-controller;
				#gpio-cells = <2>;
			};

			smb3_pins: mux-smb3 {
				groups = "smb3";
				function = "smb3";
			};

			smb4_pins: mux-smb4 {
				groups = "smb4";
				function = "smb4";
			};

			smb5_pins: mux-smb5 {
				groups = "smb5";
				function = "smb5";
			};

			scs1_pins: mux-scs1 {
				groups = "scs1";
				function = "scs1";
			};

			scs2_pins: mux-scs2 {
				groups = "scs2";
				function = "scs2";
			};

			scs3_pins: mux-scs3 {
				groups = "scs3";
				function = "scs3";
			};

			smb0_pins: mux-smb0 {
				groups = "smb0";
				function = "smb0";
			};

			smb1_pins: mux-smb1 {
				groups = "smb1";
				function = "smb1";
			};

			smb2_pins: mux-smb2 {
				groups = "smb2";
				function = "smb2";
			};

			bsp_pins: mux-bsp {
				groups = "bsp";
				function = "bsp";
			};

			hsp1_pins: mux-hsp1 {
				groups = "hsp1";
				function = "hsp1";
			};

			hsp2_pins: mux-hsp2 {
				groups = "hsp2";
				function = "hsp2";
			};

			r1err_pins: mux-r1err {
				groups = "r1err";
				function = "r1err";
			};

			r1md_pins: mux-r1md {
				groups = "r1md";
				function = "r1md";
			};

			rmii2_pins: mux-rmii2 {
				groups = "rmii2";
				function = "rmii2";
			};

			r2err_pins: mux-r2err {
				groups = "r2err";
				function = "r2err";
			};

			r2md_pins: mux-r2md {
				groups = "r2md";
				function = "r2md";
			};

			kbcc_pins: mux-kbcc {
				groups = "kbcc";
				function = "kbcc";
			};

			dvo0_pins: mux-dvo0 {
				groups = "dvo";
				function = "dvo0";
			};

			dvo3_pins: mux-dvo3 {
				groups = "dvo";
				function = "dvo3";
			};

			clko_pins: mux-clko {
				groups = "clko";
				function = "clko";
			};

			smi_pins: mux-smi {
				groups = "smi";
				function = "smi";
			};

			uinc_pins: mux-uinc {
				groups = "uinc";
				function = "uinc";
			};

			gspi_pins: mux-gspi {
				groups = "gspi";
				function = "gspi";
			};

			mben_pins: mux-mben {
				groups = "mben";
				function = "mben";
			};

			xcs2_pins: mux-xcs2 {
				groups = "xcs2";
				function = "xcs2";
			};

			xcs1_pins: mux-xcs1 {
				groups = "xcs1";
				function = "xcs1";
			};

			sdio_pins: mux-sdio {
				groups = "sdio";
				function = "sdio";
			};

			sspi_pins: mux-sspi {
				groups = "sspi";
				function = "sspi";
			};

			fi0_pins: mux-fi0 {
				groups = "fi0";
				function = "fi0";
			};

			fi1_pins: mux-fi1 {
				groups = "fi1";
				function = "fi1";
			};

			fi2_pins: mux-fi2 {
				groups = "fi2";
				function = "fi2";
			};

			fi3_pins: mux-fi3 {
				groups = "fi3";
				function = "fi3";
			};

			fi4_pins: mux-fi4 {
				groups = "fi4";
				function = "fi4";
			};

			fi5_pins: mux-fi5 {
				groups = "fi5";
				function = "fi5";
			};

			fi6_pins: mux-fi6 {
				groups = "fi6";
				function = "fi6";
			};

			fi7_pins: mux-fi7 {
				groups = "fi7";
				function = "fi7";
			};

			fi8_pins: mux-fi8 {
				groups = "fi8";
				function = "fi8";
			};

			fi9_pins: mux-fi9 {
				groups = "fi9";
				function = "fi9";
			};

			fi10_pins: mux-fi10 {
				groups = "fi10";
				function = "fi10";
			};

			fi11_pins: mux-fi11 {
				groups = "fi11";
				function = "fi11";
			};

			fi12_pins: mux-fi12 {
				groups = "fi12";
				function = "fi12";
			};

			fi13_pins: mux-fi13 {
				groups = "fi13";
				function = "fi13";
			};

			fi14_pins: mux-fi14 {
				groups = "fi14";
				function = "fi14";
			};

			fi15_pins: mux-fi15 {
				groups = "fi15";
				function = "fi15";
			};

			pwm0_pins: mux-pwm0 {
				groups = "pwm0";
				function = "pwm0";
			};

			pwm1_pins: mux-pwm1 {
				groups = "pwm1";
				function = "pwm1";
			};

			pwm2_pins: mux-pwm2 {
				groups = "pwm2";
				function = "pwm2";
			};

			pwm3_pins: mux-pwm3 {
				groups = "pwm3";
				function = "pwm3";
			};

			pwm4_pins: mux-pwm4 {
				groups = "pwm4";
				function = "pwm4";
			};

			pwm5_pins: mux-pwm5 {
				groups = "pwm5";
				function = "pwm5";
			};

			pwm6_pins: mux-pwm6 {
				groups = "pwm6";
				function = "pwm6";
			};

			pwm7_pins: mux-pwm7 {
				groups = "pwm7";
				function = "pwm7";
			};

			hg0_pins: mux-hg0 {
				groups = "hg0";
				function = "hg0";
			};

			hg1_pins: mux-hg1 {
				groups = "hg1";
				function = "hg1";
			};

			hg2_pins: mux-hg2 {
				groups = "hg2";
				function = "hg2";
			};

			hg3_pins: mux-hg3 {
				groups = "hg3";
				function = "hg3";
			};

			hg4_pins: mux-hg4 {
				groups = "hg4";
				function = "hg4";
			};

			hg5_pins: mux-hg5 {
				groups = "hg5";
				function = "hg5";
			};

			hg6_pins: mux-hg6 {
				groups = "hg6";
				function = "hg6";
			};

			hg7_pins: mux-hg7 {
				groups = "hg7";
				function = "hg7";
			};
		};

		fiu: spi-controller@c8000000 {
			compatible = "nuvoton,wpcm450-fiu";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>;
			reg-names = "control", "memory";
			clocks = <&clk 0>;
			status = "disabled";
		};

		shm: syscon@c8001000 {
			compatible = "nuvoton,wpcm450-shm", "syscon";
			reg = <0xc8001000 0x1000>;
			reg-io-width = <1>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Common file for GPMC connected smsc911x on omaps
 *
 * Note that the board specifc DTS file needs to specify
 * ranges, pinctrl, reg, interrupt parent and interrupts.
 */

/ {
	vddvario: regulator-vddvario {
		compatible = "regulator-fixed";
		regulator-name = "vddvario";
		regulator-always-on;
	};

	vdd33a: regulator-vdd33a {
		compatible = "regulator-fixed";
		regulator-name = "vdd33a";
		regulator-always-on;
	};
};

&gpmc {
	ethernet@gpmc {
		compatible = "smsc,lan9221", "smsc,lan9115";
		bank-width = <2>;
		gpmc,device-width = <1>;
		gpmc,cycle2cycle-samecsen;
		gpmc,cycle2cycle-diffcsen;
		gpmc,cs-on-ns = <5>;
		gpmc,cs-rd-off-ns = <150>;
		gpmc,cs-wr-off-ns = <150>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <15>;
		gpmc,adv-wr-off-ns = <40>;
		gpmc,oe-on-ns = <45>;
		gpmc,oe-off-ns = <140>;
		gpmc,we-on-ns = <45>;
		gpmc,we-off-ns = <140>;
		gpmc,rd-cycle-ns = <155>;
		gpmc,wr-cycle-ns = <155>;
		gpmc,access-ns = <120>;
		gpmc,page-burst-access-ns = <20>;
		gpmc,bus-turnaround-ns = <75>;
		gpmc,cycle2cycle-delay-ns = <75>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;
		gpmc,wr-access-ns = <0>;
		vddvario-supply = <&vddvario>;
		vdd33a-supply = <&vdd33a>;
		reg-io-width = <4>;
		smsc,save-mac-address;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Common file for GPMC connected smsc9221 on omaps
 *
 * Compared to smsc911x, smsc9221 (and others like smsc9217
 * or smsc 9218) has faster timings, leading to higher
 * bandwidth.
 *
 * Note that the board specifc DTS file needs to specify
 * ranges, pinctrl, reg, interrupt parent and interrupts.
 */

/ {
	vddvario: regulator-vddvario {
		compatible = "regulator-fixed";
		regulator-name = "vddvario";
		regulator-always-on;
	};

	vdd33a: regulator-vdd33a {
		compatible = "regulator-fixed";
		regulator-name = "vdd33a";
		regulator-always-on;
	};
};

&gpmc {
	ethernet@gpmc {
		compatible = "smsc,lan9221","smsc,lan9115";
		bank-width = <2>;

		gpmc,mux-add-data = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <42>;
		gpmc,cs-wr-off-ns = <36>;
		gpmc,adv-on-ns = <6>;
		gpmc,adv-rd-off-ns = <12>;
		gpmc,adv-wr-off-ns = <12>;
		gpmc,oe-on-ns = <0>;
		gpmc,oe-off-ns = <42>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <36>;
		gpmc,rd-cycle-ns = <60>;
		gpmc,wr-cycle-ns = <54>;
		gpmc,access-ns = <36>;
		gpmc,page-burst-access-ns = <0>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <18>;
		gpmc,wr-access-ns = <42>;
		gpmc,cycle2cycle-samecsen;
		gpmc,cycle2cycle-diffcsen;

		vddvario-supply = <&vddvario>;
		vdd33a-supply = <&vdd33a>;
		reg-io-width = <4>;
		smsc,save-mac-address;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Common features on the Zoom debug board
 */

#include "omap-gpmc-smsc911x.dtsi"

&gpmc {
	ranges = <3 0 0x10000000 0x1000000>,	/* CS3: 16MB for UART */
		 <7 0 0x2c000000 0x01000000>;

	/*
	 * Four port TL16CP754C serial port on GPMC,
	 * they probably share the same GPIO IRQ
	 * REVISIT: Add timing support from slls644g.pdf
	 */
	uart@3,0 {
		compatible = "ns16550a";
		reg = <3 0 8>;	/* CS3, offset 0, IO size 8 */
		bank-width = <2>;
		reg-shift = <1>;
		reg-io-width = <1>;
		interrupt-parent = <&gpio4>;
		interrupts = <6 IRQ_TYPE_EDGE_RISING>;	/* gpio102 */
		clock-frequency = <1843200>;
		current-speed = <115200>;
		gpmc,mux-add-data = <0>;
		gpmc,device-width = <1>;
		gpmc,wait-pin = <1>;
		gpmc,cycle2cycle-samecsen;
		gpmc,cycle2cycle-diffcsen;
		gpmc,cs-on-ns = <5>;
		gpmc,cs-rd-off-ns = <155>;
		gpmc,cs-wr-off-ns = <155>;
		gpmc,adv-on-ns = <15>;
		gpmc,adv-rd-off-ns = <40>;
		gpmc,adv-wr-off-ns = <40>;
		gpmc,oe-on-ns = <45>;
		gpmc,oe-off-ns = <145>;
		gpmc,we-on-ns = <45>;
		gpmc,we-off-ns = <145>;
		gpmc,rd-cycle-ns = <155>;
		gpmc,wr-cycle-ns = <155>;
		gpmc,access-ns = <145>;
		gpmc,page-burst-access-ns = <20>;
		gpmc,bus-turnaround-ns = <20>;
		gpmc,cycle2cycle-delay-ns = <20>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <45>;
		gpmc,wr-access-ns = <145>;
	};
	uart@3,1 {
		compatible = "ns16550a";
		reg = <3 0x100 8>;	/* CS3, offset 0x100, IO size 8 */
		bank-width = <2>;
		reg-shift = <1>;
		reg-io-width = <1>;
		interrupt-parent = <&gpio4>;
		interrupts = <6 IRQ_TYPE_EDGE_RISING>;	/* gpio102 */
		clock-frequency = <1843200>;
		current-speed = <115200>;
	};
	uart@3,2 {
		compatible = "ns16550a";
		reg = <3 0x200 8>;	/* CS3, offset 0x200, IO size 8 */
		bank-width = <2>;
		reg-shift = <1>;
		reg-io-width = <1>;
		interrupt-parent = <&gpio4>;
		interrupts = <6 IRQ_TYPE_EDGE_RISING>;	/* gpio102 */
		clock-frequency = <1843200>;
		current-speed = <115200>;
	};
	uart@3,3 {
		compatible = "ns16550a";
		reg = <3 0x300 8>;	/* CS3, offset 0x300, IO size 8 */
		bank-width = <2>;
		reg-shift = <1>;
		reg-io-width = <1>;
		interrupt-parent = <&gpio4>;
		interrupts = <6 IRQ_TYPE_EDGE_RISING>;	/* gpio102 */
		clock-frequency = <1843200>;
		current-speed = <115200>;
	};

	ethernet@gpmc {
		reg = <7 0 0xff>;
		interrupt-parent = <&gpio5>;
		interrupts = <30 IRQ_TYPE_LEVEL_LOW>;	/* gpio158 */
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP2 SoC
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/omap.h>

/ {
	compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
	};

	cpus {
		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			compatible = "arm,arm1136jf-s";
			device_type = "cpu";
		};
	};

	pmu {
		compatible = "arm,arm1136-pmu";
		interrupts = <3>;
	};

	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap2-mpu";
			ti,hwmods = "mpu";
		};
	};

	ocp {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		aes: aes@480a6000 {
			compatible = "ti,omap2-aes";
			ti,hwmods = "aes";
			reg = <0x480a6000 0x50>;
			dmas = <&sdma 9 &sdma 10>;
			dma-names = "tx", "rx";
		};

		hdq1w: 1w@480b2000 {
			compatible = "ti,omap2420-1w";
			ti,hwmods = "hdq1w";
			reg = <0x480b2000 0x1000>;
			interrupts = <58>;
		};

		intc: interrupt-controller@1 {
			compatible = "ti,omap2-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x480FE000 0x1000>;
		};

		target-module@48056000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x48056000 0x4>,
			      <0x4805602c 0x4>,
			      <0x48056028 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_EMUFREE |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			clocks = <&core_l3_ck>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x48056000 0x1000>;

			sdma: dma-controller@0 {
				compatible = "ti,omap2420-sdma", "ti,omap-sdma";
				reg = <0 0x1000>;
				interrupts = <12>,
					     <13>,
					     <14>,
					     <15>;
				#dma-cells = <1>;
				dma-channels = <32>;
				dma-requests = <64>;
			};
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap2-i2c";
			ti,hwmods = "i2c1";
			reg = <0x48070000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <56>;
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap2-i2c";
			ti,hwmods = "i2c2";
			reg = <0x48072000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <57>;
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap2-mcspi";
			ti,hwmods = "mcspi1";
			reg = <0x48098000 0x100>;
			interrupts = <65>;
			dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
				&sdma 39 &sdma 40 &sdma 41 &sdma 42>;
			dma-names = "tx0", "rx0", "tx1", "rx1",
				    "tx2", "rx2", "tx3", "rx3";
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap2-mcspi";
			ti,hwmods = "mcspi2";
			reg = <0x4809a000 0x100>;
			interrupts = <66>;
			dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
		};

		rng: rng@480a0000 {
			compatible = "ti,omap2-rng";
			ti,hwmods = "rng";
			reg = <0x480a0000 0x50>;
			interrupts = <52>;
		};

		sham: sham@480a4000 {
			compatible = "ti,omap2-sham";
			ti,hwmods = "sham";
			reg = <0x480a4000 0x64>;
			interrupts = <51>;
			dmas = <&sdma 13>;
			dma-names = "rx";
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap2-uart";
			ti,hwmods = "uart1";
			reg = <0x4806a000 0x2000>;
			interrupts = <72>;
			dmas = <&sdma 49 &sdma 50>;
			dma-names = "tx", "rx";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap2-uart";
			ti,hwmods = "uart2";
			reg = <0x4806c000 0x400>;
			interrupts = <73>;
			dmas = <&sdma 51 &sdma 52>;
			dma-names = "tx", "rx";
			clock-frequency = <48000000>;
		};

		uart3: serial@4806e000 {
			compatible = "ti,omap2-uart";
			ti,hwmods = "uart3";
			reg = <0x4806e000 0x400>;
			interrupts = <74>;
			dmas = <&sdma 53 &sdma 54>;
			dma-names = "tx", "rx";
			clock-frequency = <48000000>;
		};

		timer2_target: target-module@4802a000 {
			compatible = "ti,sysc-omap2-timer", "ti,sysc";
			reg = <0x4802a000 0x4>,
			      <0x4802a010 0x4>,
			      <0x4802a014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_EMUFREE |
					 SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			clocks = <&gpt2_fck>, <&gpt2_ick>;
			clock-names = "fck", "ick";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4802a000 0x1000>;

			timer2: timer@0 {
				compatible = "ti,omap2420-timer";
				reg = <0 0x400>;
				interrupts = <38>;
			};
		};

		timer3: timer@48078000 {
			compatible = "ti,omap2420-timer";
			reg = <0x48078000 0x400>;
			interrupts = <39>;
			ti,hwmods = "timer3";
		};

		timer4: timer@4807a000 {
			compatible = "ti,omap2420-timer";
			reg = <0x4807a000 0x400>;
			interrupts = <40>;
			ti,hwmods = "timer4";
		};

		timer5: timer@4807c000 {
			compatible = "ti,omap2420-timer";
			reg = <0x4807c000 0x400>;
			interrupts = <41>;
			ti,hwmods = "timer5";
			ti,timer-dsp;
		};

		timer6: timer@4807e000 {
			compatible = "ti,omap2420-timer";
			reg = <0x4807e000 0x400>;
			interrupts = <42>;
			ti,hwmods = "timer6";
			ti,timer-dsp;
		};

		timer7: timer@48080000 {
			compatible = "ti,omap2420-timer";
			reg = <0x48080000 0x400>;
			interrupts = <43>;
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@48082000 {
			compatible = "ti,omap2420-timer";
			reg = <0x48082000 0x400>;
			interrupts = <44>;
			ti,hwmods = "timer8";
			ti,timer-dsp;
		};

		timer9: timer@48084000 {
			compatible = "ti,omap2420-timer";
			reg = <0x48084000 0x400>;
			interrupts = <45>;
			ti,hwmods = "timer9";
			ti,timer-pwm;
		};

		timer10: timer@48086000 {
			compatible = "ti,omap2420-timer";
			reg = <0x48086000 0x400>;
			interrupts = <46>;
			ti,hwmods = "timer10";
			ti,timer-pwm;
		};

		timer11: timer@48088000 {
			compatible = "ti,omap2420-timer";
			reg = <0x48088000 0x400>;
			interrupts = <47>;
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};

		timer12: timer@4808a000 {
			compatible = "ti,omap2420-timer";
			reg = <0x4808a000 0x400>;
			interrupts = <48>;
			ti,hwmods = "timer12";
			ti,timer-pwm;
		};

		dss: dss@48050000 {
			compatible = "ti,omap2-dss";
			reg = <0x48050000 0x400>;
			status = "disabled";
			ti,hwmods = "dss_core";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			dispc@48050400 {
				compatible = "ti,omap2-dispc";
				reg = <0x48050400 0x400>;
				interrupts = <25>;
				ti,hwmods = "dss_dispc";
			};

			rfbi: encoder@48050800 {
				compatible = "ti,omap2-rfbi";
				reg = <0x48050800 0x400>;
				status = "disabled";
				ti,hwmods = "dss_rfbi";
			};

			venc: encoder@48050c00 {
				compatible = "ti,omap2-venc";
				reg = <0x48050c00 0x400>;
				status = "disabled";
				ti,hwmods = "dss_venc";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP2420 clock data
 *
 * Copyright (C) 2014 Texas Instruments, Inc.
 */

&prcm_clocks {
	sys_clkout2_src_gate: sys_clkout2_src_gate@70 {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <15>;
		reg = <0x0070>;
	};

	sys_clkout2_src_mux: sys_clkout2_src_mux@70 {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
		ti,bit-shift = <8>;
		reg = <0x0070>;
	};

	sys_clkout2_src: sys_clkout2_src {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
	};

	sys_clkout2: sys_clkout2@70 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&sys_clkout2_src>;
		ti,bit-shift = <11>;
		ti,max-div = <64>;
		reg = <0x0070>;
		ti,index-power-of-two;
	};

	dsp_gate_ick: dsp_gate_ick@810 {
		#clock-cells = <0>;
		compatible = "ti,composite-interface-clock";
		clocks = <&dsp_fck>;
		ti,bit-shift = <1>;
		reg = <0x0810>;
	};

	dsp_div_ick: dsp_div_ick@840 {
		#clock-cells = <0>;
		compatible = "ti,composite-divider-clock";
		clocks = <&dsp_fck>;
		ti,bit-shift = <5>;
		ti,max-div = <3>;
		reg = <0x0840>;
		ti,index-starts-at-one;
	};

	dsp_ick: dsp_ick {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
	};

	iva1_gate_ifck: iva1_gate_ifck@800 {
		#clock-cells = <0>;
		compatible = "ti,composite-gate-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <10>;
		reg = <0x0800>;
	};

	iva1_div_ifck: iva1_div_ifck@840 {
		#clock-cells = <0>;
		compatible = "ti,composite-divider-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <8>;
		reg = <0x0840>;
		ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
	};

	iva1_ifck: iva1_ifck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
	};

	iva1_ifck_div: iva1_ifck_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&iva1_ifck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&iva1_ifck_div>;
		ti,bit-shift = <8>;
		reg = <0x0800>;
	};

	wdt3_ick: wdt3_ick@210 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <28>;
		reg = <0x0210>;
	};

	wdt3_fck: wdt3_fck@200 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_32k_ck>;
		ti,bit-shift = <28>;
		reg = <0x0200>;
	};

	mmc_ick: mmc_ick@210 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <26>;
		reg = <0x0210>;
	};

	mmc_fck: mmc_fck@200 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_96m_ck>;
		ti,bit-shift = <26>;
		reg = <0x0200>;
	};

	eac_ick: eac_ick@210 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <24>;
		reg = <0x0210>;
	};

	eac_fck: eac_fck@200 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_96m_ck>;
		ti,bit-shift = <24>;
		reg = <0x0200>;
	};

	i2c1_fck: i2c1_fck@200 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_12m_ck>;
		ti,bit-shift = <19>;
		reg = <0x0200>;
	};

	i2c2_fck: i2c2_fck@200 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_12m_ck>;
		ti,bit-shift = <20>;
		reg = <0x0200>;
	};

	vlynq_ick: vlynq_ick@210 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&core_l3_ck>;
		ti,bit-shift = <3>;
		reg = <0x0210>;
	};

	vlynq_gate_fck: vlynq_gate_fck@200 {
		#clock-cells = <0>;
		compatible = "ti,composite-gate-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <3>;
		reg = <0x0200>;
	};

	core_d18_ck: core_d18_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&core_ck>;
		clock-mult = <1>;
		clock-div = <18>;
	};

	vlynq_mux_fck: vlynq_mux_fck@240 {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
		ti,bit-shift = <15>;
		reg = <0x0240>;
	};

	vlynq_fck: vlynq_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
	};
};

&prcm_clockdomains {
	gfx_clkdm: gfx_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&gfx_ick>;
	};

	core_l3_clkdm: core_l3_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
	};

	wkup_clkdm: wkup_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
			 <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
			 <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
	};

	iva1_clkdm: iva1_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&iva1_mpu_int_ifck>;
	};

	dss_clkdm: dss_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dss_ick>, <&dss_54m_fck>;
	};

	core_l4_clkdm: core_l4_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
			 <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
			 <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
			 <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
			 <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
			 <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
			 <&uart3_ick>, <&uart3_fck>, <&cam_ick>,
			 <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
			 <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
			 <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
			 <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
			 <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
			 <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
			 <&pka_ick>;
	};
};

&func_96m_ck {
	compatible = "fixed-factor-clock";
	clocks = <&apll96_ck>;
	clock-mult = <1>;
	clock-div = <1>;
};

&dsp_div_fck {
	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
};

&ssi_ssr_sst_div_fck {
	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 */
/dts-v1/;

#include "omap2420.dtsi"

/ {
	model = "TI OMAP2420 H4 board";
	compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x4000000>; /* 64 MB */
	};
};

&gpmc {
	ranges = <0 0 0x08000000 0x04000000>;

	nor@0,0 {
		compatible = "cfi-flash";
		linux,mtd-name = "intel,ge28f256l18b85";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0 0 0x04000000>;
		bank-width = <2>;

		gpmc,mux-add-data = <2>;
		gpmc,cs-on-ns = <10>;
		gpmc,cs-rd-off-ns = <160>;
		gpmc,cs-wr-off-ns = <160>;
		gpmc,adv-on-ns = <20>;
		gpmc,adv-rd-off-ns = <50>;
		gpmc,adv-wr-off-ns = <50>;
		gpmc,oe-on-ns = <60>;
		gpmc,oe-off-ns = <120>;
		gpmc,we-on-ns = <60>;
		gpmc,we-off-ns = <120>;
		gpmc,rd-cycle-ns = <170>;
		gpmc,wr-cycle-ns = <170>;
		gpmc,access-ns = <150>;
		gpmc,page-burst-access-ns = <10>;

		partition@0 {
			label = "bootloader";
			reg = <0 0x20000>;
		};
		partition@20000 {
			label = "params";
			reg = <0x20000 0x20000>;
		};
		partition@40000 {
			label = "kernel";
			reg = <0x40000 0x200000>;
		};
		partition@240000 {
			label = "file-system";
			reg = <0x240000 0x3dc0000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include "omap2420-n8x0-common.dtsi"

/ {
	model = "Nokia N800";
	compatible = "nokia,n800", "nokia,n8x0", "ti,omap2420", "ti,omap2";
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include "omap2420-n8x0-common.dtsi"

/ {
	model = "Nokia N810 WiMax";
	compatible = "nokia,n810-wimax", "nokia,n8x0", "ti,omap2420", "ti,omap2";
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include "omap2420-n8x0-common.dtsi"

/ {
	model = "Nokia N810";
	compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2";

	vio_ape: vio_ape {
		compatible = "regulator-fixed";
		regulator-name = "vio_ape";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	v28_aic: v28_aic {
		compatible = "regulator-fixed";
		regulator-name = "v28_aic";
		regulator-min-microvolt = <2800000>;
		regulator-max-microvolt = <2800000>;
	};
};

&omap2420_pmx {
	mcbsp2_pins: mcbsp2_pins {
		pinctrl-single,pins = <
			OMAP2420_CORE_IOPAD(0x0124, PIN_INPUT | MUX_MODE1)	/* eac_ac_sclk.mcbsp2_clkx */
			OMAP2420_CORE_IOPAD(0x0125, PIN_INPUT | MUX_MODE1)	/* eac_ac_fs.mcbsp2_fsx */
			OMAP2420_CORE_IOPAD(0x0126, PIN_INPUT | MUX_MODE1)	/* eac_ac_din.mcbsp2_dr */
			OMAP2420_CORE_IOPAD(0x0127, PIN_OUTPUT | MUX_MODE1)	/* eac_ac_dout.mcbsp2_dx */
		>;
	};

	aic33_pins: aic33_pins {
		pinctrl-single,pins = <
			OMAP2420_CORE_IOPAD(0x0129, PIN_OUTPUT | MUX_MODE3)	/* eac_ac_rst.gpio118 */
			OMAP2420_CORE_IOPAD(0x00e8, PIN_OUTPUT | MUX_MODE2)	/* vlynq_tx1.sys_clkout2 */
		>;
	};
};

&i2c2 {
	aic33@18 {
		compatible = "ti,tlv320aic33";
		reg = <0x18>;

		pinctrl-names = "default";
		pinctrl-0 = <&aic33_pins>;

		reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */

		ai3x-gpio-func = <
			10 /* AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK */
			5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
		>;
		ai3x-micbias-vg = <1>; /* 2V */

		AVDD-supply = <&v28_aic>;
		DRVDD-supply = <&v28_aic>;
		IOVDD-supply = <&vio_ape>;
		DVDD-supply = <&vio_ape>;

		assigned-clocks = <&sys_clkout2_src>, <&sys_clkout2>;
		assigned-clock-parents = <&func_96m_ck>;
		assigned-clock-rates = <0>, <12000000>;
	};
};

&mcbsp2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcbsp2_pins>;

	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
#include "omap2420.dtsi"

/ {
	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x8000000>; /* 128 MB */
	};

	chosen {
		stdout-path = &uart3;
	};

	ocp {
		i2c0 {
			compatible = "i2c-cbus-gpio";
			gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */
				 &gpio3 1 GPIO_ACTIVE_HIGH /* gpio65 dat */
				 &gpio3 0 GPIO_ACTIVE_HIGH /* gpio64 sel */
				>;
			#address-cells = <1>;
			#size-cells = <0>;
			retu: retu@1 {
				compatible = "nokia,retu";
				interrupt-parent = <&gpio4>;
				interrupts = <12 IRQ_TYPE_EDGE_RISING>;
				reg = <0x1>;
			};
		};
	};
};

&i2c1 {
	clock-frequency = <400000>;

	pmic@72 {
		compatible = "menelaus";
		reg = <0x72>;
		interrupts = <7 IRQ_TYPE_EDGE_RISING>;
	};
};

&i2c2 {
	clock-frequency = <400000>;
};

&gpmc {
	ranges = <0 0 0x04000000 0x1000000>;	/* CS0: 16MB for OneNAND */

	/* gpio-irq for dma: 26 */

	onenand@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "ti,omap2-onenand";
		reg = <0 0 0x20000>;	/* CS0, offset 0, IO size 128K */

		gpmc,sync-read;
		gpmc,burst-length = <16>;
		gpmc,burst-read;
		gpmc,burst-wrap;
		gpmc,device-width = <2>;
		gpmc,mux-add-data = <2>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <127>;
		gpmc,cs-wr-off-ns = <109>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <18>;
		gpmc,adv-wr-off-ns = <18>;
		gpmc,oe-on-ns = <27>;
		gpmc,oe-off-ns = <127>;
		gpmc,we-on-ns = <27>;
		gpmc,we-off-ns = <72>;
		gpmc,rd-cycle-ns = <145>;
		gpmc,wr-cycle-ns = <136>;
		gpmc,access-ns = <118>;
		gpmc,page-burst-access-ns = <27>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,clk-activation-ns = <9>;
		gpmc,sync-clk-ps = <27000>;

		/* MTD partition table corresponding to old board-n8x0 file. */
		partition@0 {
			label = "bootloader";
			reg = <0x00000000 0x00020000>;
			read-only;
		};
		partition@1 {
			label = "config";
			reg = <0x00020000 0x00060000>;
		};
		partition@2 {
			label = "kernel";
			reg = <0x00080000 0x00200000>;
		};
		partition@3 {
			label = "initfs";
			reg = <0x00280000 0x00400000>;
		};
		partition@4 {
			label = "rootfs";
			reg = <0x00680000 0x0f980000>;
		};
		partition@5 {
			label = "omap2-onenand";
			reg = <0x00000000 0x10000000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP2420 SoC
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "omap2.dtsi"

/ {
	compatible = "ti,omap2420", "ti,omap2";

	ocp {
		l4: l4@48000000 {
			compatible = "ti,omap2-l4", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x48000000 0x100000>;

			prcm: prcm@8000 {
				compatible = "ti,omap2-prcm";
				reg = <0x8000 0x1000>;

				prcm_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};

				prcm_clockdomains: clockdomains {
				};
			};

			scm: scm@0 {
				compatible = "ti,omap2-scm", "simple-bus";
				reg = <0x0 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				#pinctrl-cells = <1>;
				ranges = <0 0x0 0x1000>;

				omap2420_pmx: pinmux@30 {
					compatible = "ti,omap2420-padconf",
						     "pinctrl-single";
					reg = <0x30 0x0113>;
					#address-cells = <1>;
					#size-cells = <0>;
					#pinctrl-cells = <1>;
					pinctrl-single,register-width = <8>;
					pinctrl-single,function-mask = <0x3f>;
				};

				scm_conf: scm_conf@270 {
					compatible = "syscon";
					reg = <0x270 0x100>;
					#address-cells = <1>;
					#size-cells = <1>;

					scm_clocks: clocks {
						#address-cells = <1>;
						#size-cells = <0>;
					};
				};

				scm_clockdomains: clockdomains {
				};
			};

			target-module@4000 {
				compatible = "ti,sysc-omap2", "ti,sysc";
				reg = <0x4000 0x4>,
				      <0x4004 0x4>;
				reg-names = "rev", "sysc";
				ti,sysc-sidle = <SYSC_IDLE_FORCE>,
						<SYSC_IDLE_NO>;
				clocks = <&func_32k_ck>;
				clock-names = "fck";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x4000 0x1000>;

				counter32k: counter@0 {
					compatible = "ti,omap-counter32k";
					reg = <0 0x20>;
				};
			};
		};

		gpio1: gpio@48018000 {
			compatible = "ti,omap2-gpio";
			reg = <0x48018000 0x200>;
			interrupts = <29>;
			ti,hwmods = "gpio1";
			ti,gpio-always-on;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpio2: gpio@4801a000 {
			compatible = "ti,omap2-gpio";
			reg = <0x4801a000 0x200>;
			interrupts = <30>;
			ti,hwmods = "gpio2";
			ti,gpio-always-on;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpio3: gpio@4801c000 {
			compatible = "ti,omap2-gpio";
			reg = <0x4801c000 0x200>;
			interrupts = <31>;
			ti,hwmods = "gpio3";
			ti,gpio-always-on;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpio4: gpio@4801e000 {
			compatible = "ti,omap2-gpio";
			reg = <0x4801e000 0x200>;
			interrupts = <32>;
			ti,hwmods = "gpio4";
			ti,gpio-always-on;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpmc: gpmc@6800a000 {
			compatible = "ti,omap2420-gpmc";
			reg = <0x6800a000 0x1000>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupts = <20>;
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			ti,hwmods = "gpmc";
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		mcbsp1: mcbsp@48074000 {
			compatible = "ti,omap2420-mcbsp";
			reg = <0x48074000 0xff>;
			reg-names = "mpu";
			interrupts = <59>, /* TX interrupt */
				     <60>; /* RX interrupt */
			interrupt-names = "tx", "rx";
			ti,hwmods = "mcbsp1";
			dmas = <&sdma 31>,
			       <&sdma 32>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcbsp2: mcbsp@48076000 {
			compatible = "ti,omap2420-mcbsp";
			reg = <0x48076000 0xff>;
			reg-names = "mpu";
			interrupts = <62>, /* TX interrupt */
				     <63>; /* RX interrupt */
			interrupt-names = "tx", "rx";
			ti,hwmods = "mcbsp2";
			dmas = <&sdma 33>,
			       <&sdma 34>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		msdi1: mmc@4809c000 {
			compatible = "ti,omap2420-mmc";
			ti,hwmods = "msdi1";
			reg = <0x4809c000 0x80>;
			interrupts = <83>;
			dmas = <&sdma 61 &sdma 62>;
			dma-names = "tx", "rx";
		};

		mailbox: mailbox@48094000 {
			compatible = "ti,omap2-mailbox";
			reg = <0x48094000 0x200>;
			interrupts = <26>, <34>;
			ti,hwmods = "mailbox";
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <6>;
			mbox_dsp: mbox-dsp {
				ti,mbox-tx = <0 0 0>;
				ti,mbox-rx = <1 0 0>;
			};
			mbox_iva: mbox-iva {
				ti,mbox-tx = <2 1 3>;
				ti,mbox-rx = <3 1 3>;
			};
		};

		timer1_target: target-module@48028000 {
			compatible = "ti,sysc-omap2-timer", "ti,sysc";
			reg = <0x48028000 0x4>,
			      <0x48028010 0x4>,
			      <0x48028014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_EMUFREE |
					 SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			clocks = <&gpt1_fck>, <&gpt1_ick>;
			clock-names = "fck", "ick";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x48028000 0x1000>;

			timer1: timer@0 {
				compatible = "ti,omap2420-timer";
				reg = <0 0x400>;
				interrupts = <37>;
				ti,timer-alwon;
			};
		};

		wd_timer2: wdt@48022000 {
			compatible = "ti,omap2-wdt";
			ti,hwmods = "wd_timer2";
			reg = <0x48022000 0x80>;
		};
	};
};

&i2c1 {
	compatible = "ti,omap2420-i2c";
};

&i2c2 {
	compatible = "ti,omap2420-i2c";
};

#include "omap24xx-clocks.dtsi"
#include "omap2420-clocks.dtsi"

/* Preferred always-on timer for clockevent */
&timer1_target {
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&gpt1_fck>;
		assigned-clock-parents = <&func_32k_ck>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP2430 clock data
 *
 * Copyright (C) 2014 Texas Instruments, Inc.
 */

&scm_clocks {
	mcbsp3_mux_fck: mcbsp3_mux_fck@78 {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&func_96m_ck>, <&mcbsp_clks>;
		reg = <0x78>;
	};

	mcbsp3_fck: mcbsp3_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
	};

	mcbsp4_mux_fck: mcbsp4_mux_fck@78 {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&func_96m_ck>, <&mcbsp_clks>;
		ti,bit-shift = <2>;
		reg = <0x78>;
	};

	mcbsp4_fck: mcbsp4_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
	};

	mcbsp5_mux_fck: mcbsp5_mux_fck@78 {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&func_96m_ck>, <&mcbsp_clks>;
		ti,bit-shift = <4>;
		reg = <0x78>;
	};

	mcbsp5_fck: mcbsp5_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
	};
};

&prcm_clocks {
	iva2_1_gate_ick: iva2_1_gate_ick@800 {
		#clock-cells = <0>;
		compatible = "ti,composite-gate-clock";
		clocks = <&dsp_fck>;
		ti,bit-shift = <0>;
		reg = <0x0800>;
	};

	iva2_1_div_ick: iva2_1_div_ick@840 {
		#clock-cells = <0>;
		compatible = "ti,composite-divider-clock";
		clocks = <&dsp_fck>;
		ti,bit-shift = <5>;
		ti,max-div = <3>;
		reg = <0x0840>;
		ti,index-starts-at-one;
	};

	iva2_1_ick: iva2_1_ick {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
	};

	mdm_gate_ick: mdm_gate_ick@c10 {
		#clock-cells = <0>;
		compatible = "ti,composite-interface-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <0>;
		reg = <0x0c10>;
	};

	mdm_div_ick: mdm_div_ick@c40 {
		#clock-cells = <0>;
		compatible = "ti,composite-divider-clock";
		clocks = <&core_ck>;
		reg = <0x0c40>;
		ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
	};

	mdm_ick: mdm_ick {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
	};

	mdm_osc_ck: mdm_osc_ck@c00 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&osc_ck>;
		ti,bit-shift = <1>;
		reg = <0x0c00>;
	};

	mcbsp3_ick: mcbsp3_ick@214 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <3>;
		reg = <0x0214>;
	};

	mcbsp3_gate_fck: mcbsp3_gate_fck@204 {
		#clock-cells = <0>;
		compatible = "ti,composite-gate-clock";
		clocks = <&mcbsp_clks>;
		ti,bit-shift = <3>;
		reg = <0x0204>;
	};

	mcbsp4_ick: mcbsp4_ick@214 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <4>;
		reg = <0x0214>;
	};

	mcbsp4_gate_fck: mcbsp4_gate_fck@204 {
		#clock-cells = <0>;
		compatible = "ti,composite-gate-clock";
		clocks = <&mcbsp_clks>;
		ti,bit-shift = <4>;
		reg = <0x0204>;
	};

	mcbsp5_ick: mcbsp5_ick@214 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <5>;
		reg = <0x0214>;
	};

	mcbsp5_gate_fck: mcbsp5_gate_fck@204 {
		#clock-cells = <0>;
		compatible = "ti,composite-gate-clock";
		clocks = <&mcbsp_clks>;
		ti,bit-shift = <5>;
		reg = <0x0204>;
	};

	mcspi3_ick: mcspi3_ick@214 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <9>;
		reg = <0x0214>;
	};

	mcspi3_fck: mcspi3_fck@204 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_48m_ck>;
		ti,bit-shift = <9>;
		reg = <0x0204>;
	};

	icr_ick: icr_ick@410 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&sys_ck>;
		ti,bit-shift = <6>;
		reg = <0x0410>;
	};

	i2chs1_fck: i2chs1_fck@204 {
		#clock-cells = <0>;
		compatible = "ti,omap2430-interface-clock";
		clocks = <&func_96m_ck>;
		ti,bit-shift = <19>;
		reg = <0x0204>;
	};

	i2chs2_fck: i2chs2_fck@204 {
		#clock-cells = <0>;
		compatible = "ti,omap2430-interface-clock";
		clocks = <&func_96m_ck>;
		ti,bit-shift = <20>;
		reg = <0x0204>;
	};

	usbhs_ick: usbhs_ick@214 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&core_l3_ck>;
		ti,bit-shift = <6>;
		reg = <0x0214>;
	};

	mmchs1_ick: mmchs1_ick@214 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <7>;
		reg = <0x0214>;
	};

	mmchs1_fck: mmchs1_fck@204 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_96m_ck>;
		ti,bit-shift = <7>;
		reg = <0x0204>;
	};

	mmchs2_ick: mmchs2_ick@214 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <8>;
		reg = <0x0214>;
	};

	mmchs2_fck: mmchs2_fck@204 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_96m_ck>;
		ti,bit-shift = <8>;
		reg = <0x0204>;
	};

	gpio5_ick: gpio5_ick@214 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <10>;
		reg = <0x0214>;
	};

	gpio5_fck: gpio5_fck@204 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_32k_ck>;
		ti,bit-shift = <10>;
		reg = <0x0204>;
	};

	mdm_intc_ick: mdm_intc_ick@214 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&l4_ck>;
		ti,bit-shift = <11>;
		reg = <0x0214>;
	};

	mmchsdb1_fck: mmchsdb1_fck@204 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_32k_ck>;
		ti,bit-shift = <16>;
		reg = <0x0204>;
	};

	mmchsdb2_fck: mmchsdb2_fck@204 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&func_32k_ck>;
		ti,bit-shift = <17>;
		reg = <0x0204>;
	};
};

&prcm_clockdomains {
	gfx_clkdm: gfx_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&gfx_ick>;
	};

	core_l3_clkdm: core_l3_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
	};

	wkup_clkdm: wkup_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
			 <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
			 <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
			 <&icr_ick>;
	};

	dss_clkdm: dss_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dss_ick>, <&dss_54m_fck>;
	};

	core_l4_clkdm: core_l4_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
			 <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
			 <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
			 <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
			 <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
			 <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
			 <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
			 <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
			 <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
			 <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
			 <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
			 <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
			 <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
			 <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
			 <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
			 <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
			 <&mmchsdb2_fck>;
	};

	mdm_clkdm: mdm_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&mdm_osc_ck>;
	};
};

&func_96m_ck {
	compatible = "ti,mux-clock";
	clocks = <&apll96_ck>, <&alt_ck>;
	ti,bit-shift = <4>;
	reg = <0x0540>;
};

&dsp_div_fck {
	ti,max-div = <4>;
	ti,index-starts-at-one;
};

&ssi_ssr_sst_div_fck {
	ti,max-div = <5>;
	ti,index-starts-at-one;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 */
/dts-v1/;

#include "omap2430.dtsi"

/ {
	model = "TI OMAP2430 SDP";
	compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x8000000>; /* 128 MB */
	};
};

&i2c2 {
	clock-frequency = <100000>;

	twl: twl@48 {
		reg = <0x48>;
		interrupts = <7>; /* SYS_NIRQ cascaded to intc */
	};
};

#include "twl4030.dtsi"

&mmc1 {
	vmmc-supply = <&vmmc1>;
	bus-width = <4>;
};

&gpmc {
	ranges = <5 0 0x08000000 0x01000000>;
	ethernet@gpmc {
		compatible = "smsc,lan91c94";
		interrupt-parent = <&gpio5>;
		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;	/* gpio149 */
		reg = <5 0x300 0xf>;
		bank-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,mux-add-data = <2>;
		gpmc,device-width = <1>;
		gpmc,cycle2cycle-samecsen;
		gpmc,cycle2cycle-diffcsen;
		gpmc,cs-on-ns = <6>;
		gpmc,cs-rd-off-ns = <187>;
		gpmc,cs-wr-off-ns = <187>;
		gpmc,adv-on-ns = <18>;
		gpmc,adv-rd-off-ns = <48>;
		gpmc,adv-wr-off-ns = <48>;
		gpmc,oe-on-ns = <60>;
		gpmc,oe-off-ns = <169>;
		gpmc,we-on-ns = <66>;
		gpmc,we-off-ns = <169>;
		gpmc,rd-cycle-ns = <187>;
		gpmc,wr-cycle-ns = <187>;
		gpmc,access-ns = <187>;
		gpmc,page-burst-access-ns = <24>;
		gpmc,bus-turnaround-ns = <24>;
		gpmc,cycle2cycle-delay-ns = <24>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;
		gpmc,wr-access-ns = <0>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP243x SoC
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "omap2.dtsi"

/ {
	compatible = "ti,omap2430", "ti,omap2";

	ocp {
		l4_wkup: l4_wkup@49000000 {
			compatible = "ti,omap2-l4-wkup", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x49000000 0x31000>;

			prcm: prcm@6000 {
				compatible = "ti,omap2-prcm";
				reg = <0x6000 0x1000>;

				prcm_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};

				prcm_clockdomains: clockdomains {
				};
			};

			scm: scm@2000 {
				compatible = "ti,omap2-scm", "simple-bus";
				reg = <0x2000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				#pinctrl-cells = <1>;
				ranges = <0 0x2000 0x1000>;

				omap2430_pmx: pinmux@30 {
					compatible = "ti,omap2430-padconf",
						     "pinctrl-single";
					reg = <0x30 0x0154>;
					#address-cells = <1>;
					#size-cells = <0>;
					#pinctrl-cells = <1>;
					pinctrl-single,register-width = <8>;
					pinctrl-single,function-mask = <0x3f>;
				};

				scm_conf: scm_conf@270 {
					compatible = "syscon",
						     "simple-bus";
					reg = <0x270 0x240>;
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0 0x270 0x240>;

					scm_clocks: clocks {
						#address-cells = <1>;
						#size-cells = <0>;
					};

					pbias_regulator: pbias_regulator@230 {
						compatible = "ti,pbias-omap2", "ti,pbias-omap";
						reg = <0x230 0x4>;
						syscon = <&scm_conf>;
						pbias_mmc_reg: pbias_mmc_omap2430 {
							regulator-name = "pbias_mmc_omap2430";
							regulator-min-microvolt = <1800000>;
							regulator-max-microvolt = <3000000>;
						};
					};
				};

				scm_clockdomains: clockdomains {
				};
			};

			target-module@20000 {
				compatible = "ti,sysc-omap2", "ti,sysc";
				reg = <0x20000 0x4>,
				      <0x20004 0x4>;
				reg-names = "rev", "sysc";
				ti,sysc-sidle = <SYSC_IDLE_FORCE>,
						<SYSC_IDLE_NO>;
				clocks = <&func_32k_ck>;
				clock-names = "fck";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x20000 0x1000>;

				counter32k: counter@0 {
					compatible = "ti,omap-counter32k";
					reg = <0 0x20>;
				};
			};
		};

		gpio1: gpio@4900c000 {
			compatible = "ti,omap2-gpio";
			reg = <0x4900c000 0x200>;
			interrupts = <29>;
			ti,hwmods = "gpio1";
			ti,gpio-always-on;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpio2: gpio@4900e000 {
			compatible = "ti,omap2-gpio";
			reg = <0x4900e000 0x200>;
			interrupts = <30>;
			ti,hwmods = "gpio2";
			ti,gpio-always-on;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpio3: gpio@49010000 {
			compatible = "ti,omap2-gpio";
			reg = <0x49010000 0x200>;
			interrupts = <31>;
			ti,hwmods = "gpio3";
			ti,gpio-always-on;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpio4: gpio@49012000 {
			compatible = "ti,omap2-gpio";
			reg = <0x49012000 0x200>;
			interrupts = <32>;
			ti,hwmods = "gpio4";
			ti,gpio-always-on;
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpio5: gpio@480b6000 {
			compatible = "ti,omap2-gpio";
			reg = <0x480b6000 0x200>;
			interrupts = <33>;
			ti,hwmods = "gpio5";
			#gpio-cells = <2>;
			gpio-controller;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		gpmc: gpmc@6e000000 {
			compatible = "ti,omap2430-gpmc";
			reg = <0x6e000000 0x1000>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupts = <20>;
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			ti,hwmods = "gpmc";
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		mcbsp1: mcbsp@48074000 {
			compatible = "ti,omap2430-mcbsp";
			reg = <0x48074000 0xff>;
			reg-names = "mpu";
			interrupts = <64>, /* OCP compliant interrupt */
				     <59>, /* TX interrupt */
				     <60>, /* RX interrupt */
				     <61>; /* RX overflow interrupt */
			interrupt-names = "common", "tx", "rx", "rx_overflow";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
			dmas = <&sdma 31>,
			       <&sdma 32>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcbsp2: mcbsp@48076000 {
			compatible = "ti,omap2430-mcbsp";
			reg = <0x48076000 0xff>;
			reg-names = "mpu";
			interrupts = <16>, /* OCP compliant interrupt */
				     <62>, /* TX interrupt */
				     <63>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp2";
			dmas = <&sdma 33>,
			       <&sdma 34>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcbsp3: mcbsp@4808c000 {
			compatible = "ti,omap2430-mcbsp";
			reg = <0x4808c000 0xff>;
			reg-names = "mpu";
			interrupts = <17>, /* OCP compliant interrupt */
				     <89>, /* TX interrupt */
				     <90>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
			dmas = <&sdma 17>,
			       <&sdma 18>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcbsp4: mcbsp@4808e000 {
			compatible = "ti,omap2430-mcbsp";
			reg = <0x4808e000 0xff>;
			reg-names = "mpu";
			interrupts = <18>, /* OCP compliant interrupt */
				     <54>, /* TX interrupt */
				     <55>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp4";
			dmas = <&sdma 19>,
			       <&sdma 20>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mcbsp5: mcbsp@48096000 {
			compatible = "ti,omap2430-mcbsp";
			reg = <0x48096000 0xff>;
			reg-names = "mpu";
			interrupts = <19>, /* OCP compliant interrupt */
				     <81>, /* TX interrupt */
				     <82>; /* RX interrupt */
			interrupt-names = "common", "tx", "rx";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp5";
			dmas = <&sdma 21>,
			       <&sdma 22>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap2-hsmmc";
			reg = <0x4809c000 0x200>;
			interrupts = <83>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			dmas = <&sdma 61>, <&sdma 62>;
			dma-names = "tx", "rx";
			pbias-supply = <&pbias_mmc_reg>;
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap2-hsmmc";
			reg = <0x480b4000 0x200>;
			interrupts = <86>;
			ti,hwmods = "mmc2";
			dmas = <&sdma 47>, <&sdma 48>;
			dma-names = "tx", "rx";
		};

		mailbox: mailbox@48094000 {
			compatible = "ti,omap2-mailbox";
			reg = <0x48094000 0x200>;
			interrupts = <26>;
			ti,hwmods = "mailbox";
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <6>;
			mbox_dsp: mbox-dsp {
				ti,mbox-tx = <0 0 0>;
				ti,mbox-rx = <1 0 0>;
			};
		};

		timer1_target: target-module@49018000 {
			compatible = "ti,sysc-omap2-timer", "ti,sysc";
			reg = <0x49018000 0x4>,
			      <0x49018010 0x4>,
			      <0x49018014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_EMUFREE |
					 SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			clocks = <&gpt1_fck>, <&gpt1_ick>;
			clock-names = "fck", "ick";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49018000 0x1000>;

			timer1: timer@0 {
				compatible = "ti,omap2420-timer";
				reg = <0 0x400>;
				interrupts = <37>;
				ti,timer-alwon;
			};
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap2-mcspi";
			ti,hwmods = "mcspi3";
			reg = <0x480b8000 0x100>;
			interrupts = <91>;
			dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
		};

		usb_otg_hs: usb_otg_hs@480ac000 {
			compatible = "ti,omap2-musb";
			ti,hwmods = "usb_otg_hs";
			reg = <0x480ac000 0x1000>;
			interrupts = <93>;
		};

		wd_timer2: wdt@49016000 {
			compatible = "ti,omap2-wdt";
			ti,hwmods = "wd_timer2";
			reg = <0x49016000 0x80>;
		};
	};
};

&sdma {
	compatible = "ti,omap2430-sdma", "ti,omap-sdma";
};

&i2c1 {
	compatible = "ti,omap2430-i2c";
};

&i2c2 {
	compatible = "ti,omap2430-i2c";
};

#include "omap24xx-clocks.dtsi"
#include "omap2430-clocks.dtsi"

/* Preferred always-on timer for clockevent */
&timer1_target {
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&gpt1_fck>;
		assigned-clock-parents = <&func_32k_ck>;
	};
};