code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016 BayLibre, Inc.
 */
/dts-v1/;
#include "da850.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "DA850/AM1808/OMAP-L138 LCDK";
	compatible = "ti,da850-lcdk", "ti,da850";

	aliases {
		serial2 = &serial2;
		ethernet0 = &eth0;
	};

	chosen {
		stdout-path = "serial2:115200n8";
	};

	memory@c0000000 {
		/* 128 MB DDR2 SDRAM @ 0xc0000000 */
		reg = <0xc0000000 0x08000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dsp_memory_region: dsp-memory@c3000000 {
			compatible = "shared-dma-pool";
			reg = <0xc3000000 0x1000000>;
			reusable;
			status = "okay";
		};
	};

	vcc_5vd: fixedregulator-vcc_5vd {
		compatible = "regulator-fixed";
		regulator-name = "vcc_5vd";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
	};

	vcc_3v3d: fixedregulator-vcc_3v3d {
		/* TPS650250 - VDCDC1 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3d";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc_5vd>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_1v8d: fixedregulator-vcc_1v8d {
		/* TPS650250 - VDCDC2 */
		compatible = "regulator-fixed";
		regulator-name = "vcc_1v8d";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&vcc_5vd>;
		regulator-always-on;
		regulator-boot-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DA850-OMAPL138 LCDK";
		simple-audio-card,widgets =
			"Line", "Line In",
			"Line", "Line Out",
			"Microphone", "Mic Jack";
		simple-audio-card,routing =
			"LINE1L", "Line In",
			"LINE1R", "Line In",
			"Line Out", "LLOUT",
			"Line Out", "RLOUT",
			"MIC3L", "Mic Jack",
			"MIC3R", "Mic Jack",
			"Mic Jack", "Mic Bias";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&link0_codec>;
		simple-audio-card,frame-master = <&link0_codec>;
		simple-audio-card,bitclock-inversion;

		simple-audio-card,cpu {
			sound-dai = <&mcasp0>;
			system-clock-frequency = <24576000>;
		};

		link0_codec: simple-audio-card,codec {
			sound-dai = <&tlv320aic3106>;
			system-clock-frequency = <24576000>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;

		user1 {
			label = "GPIO Key USER1";
			linux,code = <BTN_0>;
			gpios = <&gpio 36 GPIO_ACTIVE_LOW>;
		};

		user2 {
			label = "GPIO Key USER2";
			linux,code = <BTN_1>;
			gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
		};
	};

	vga-bridge {
		compatible = "ti,ths8135";
		#address-cells = <1>;
		#size-cells = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				vga_bridge_in: endpoint {
					remote-endpoint = <&lcdc_out_vga>;
				};
			};

			port@1 {
				reg = <1>;

				vga_bridge_out: endpoint {
					remote-endpoint = <&vga_con_in>;
				};
			};
		};
	};

	vga {
		compatible = "vga-connector";

		ddc-i2c-bus = <&i2c0>;

		port {
			vga_con_in: endpoint {
				remote-endpoint = <&vga_bridge_out>;
			};
		};
	};

	cvdd: regulator0 {
		compatible = "regulator-fixed";
		regulator-name = "cvdd";
		regulator-min-microvolt = <1300000>;
		regulator-max-microvolt = <1300000>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&ref_clk {
	clock-frequency = <24000000>;
};

&cpu {
	cpu-supply = <&cvdd>;
};

/*
 * LCDK has a fixed CVDD of 1.3V, so only operating points >= 300MHz are
 * valid. Unfortunately due to a problem with the DA8XX OHCI controller, we
 * can't enable more than one OPP by default, since the controller sometimes
 * becomes unresponsive after a transition. Fix the frequency at 456 MHz.
 */

&opp_100 {
	status = "disabled";
};

&opp_200 {
	status = "disabled";
};

&opp_300 {
	status = "disabled";
};

&opp_456 {
	status = "okay";
};

&pmx_core {
	status = "okay";

	mcasp0_pins: pinmux_mcasp0_pins {
		pinctrl-single,bits = <
			/* AHCLKX AFSX ACLKX */
			0x00 0x00101010 0x00f0f0f0
			/* ARX13 ARX14 */
			0x04 0x00000110 0x00000ff0
		>;
	};

	nand_pins: nand_pins {
		pinctrl-single,bits = <
			/* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
			0x1c 0x10110010  0xf0ff00f0
			/*
			 * EMA_D[0], EMA_D[1], EMA_D[2],
			 * EMA_D[3], EMA_D[4], EMA_D[5],
			 * EMA_D[6], EMA_D[7]
			 */
			0x24 0x11111111  0xffffffff
			/*
			 * EMA_D[8],  EMA_D[9],  EMA_D[10],
			 * EMA_D[11], EMA_D[12], EMA_D[13],
			 * EMA_D[14], EMA_D[15]
			 */
			0x20 0x11111111  0xffffffff
			/* EMA_A[1], EMA_A[2] */
			0x30 0x01100000  0x0ff00000
		>;
	};
};

&serial2 {
	pinctrl-names = "default";
	pinctrl-0 = <&serial2_rxtx_pins>;
	status = "okay";
};

&wdt {
	status = "okay";
};

&rtc0 {
	status = "okay";
};

&gpio {
	status = "okay";
};

&sata_refclk {
	status = "okay";
	clock-frequency = <100000000>;
};

&sata {
	status = "okay";
};

&mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	bus_freq = <2200000>;
	status = "okay";
};

&eth0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mii_pins>;
	status = "okay";
};

&mmc0 {
	max-frequency = <50000000>;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	clock-frequency = <100000>;
	status = "okay";

	tlv320aic3106: tlv320aic3106@18 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x18>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;		/* 2.0V */
		status = "okay";

		/* Regulators */
		IOVDD-supply = <&vcc_3v3d>;
		AVDD-supply = <&vcc_3v3d>;
		DRVDD-supply = <&vcc_3v3d>;
		DVDD-supply = <&vcc_1v8d>;
	};
};

&mcasp0 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&mcasp0_pins>;
	status = "okay";

	op-mode = <0>;   /* DAVINCI_MCASP_IIS_MODE */
	tdm-slots = <2>;
	serial-dir = <   /* 0: INACTIVE, 1: TX, 2: RX */
		0 0 0 0
		0 0 0 0
		0 0 0 0
		0 1 2 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&usb_phy {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&aemif {
	pinctrl-names = "default";
	pinctrl-0 = <&nand_pins>;
	status = "okay";
	cs3 {
		#address-cells = <2>;
		#size-cells = <1>;
		clock-ranges;
		ranges;

		ti,cs-chipselect = <3>;

		nand@2000000,0 {
			compatible = "ti,davinci-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0 0x02000000 0x02000000
			       1 0x00000000 0x00008000>;

			ti,davinci-chipselect = <1>;
			ti,davinci-mask-ale = <0>;
			ti,davinci-mask-cle = <0>;
			ti,davinci-mask-chipsel = <0>;

			ti,davinci-nand-buswidth = <16>;
			ti,davinci-ecc-mode = "hw";
			ti,davinci-ecc-bits = <4>;
			ti,davinci-nand-use-bbt;

			/*
			 * The OMAP-L132/L138 Bootloader doc SPRAB41E reads:
			 * "To boot from NAND Flash, the AIS should be written
			 * to NAND block 1 (NAND block 0 is not used by default)".
			 * The same doc mentions that for ROM "Silicon Revision 2.1",
			 * "Updated NAND boot mode to offer boot from block 0 or block 1".
			 * However the limitaion is left here by default for compatibility
			 * with older silicon and because it needs new boot pin settings
			 * not possible in stock LCDK.
			 */
			partitions {
				compatible = "fixed-partitions";
				#address-cells = <1>;
				#size-cells = <1>;

				partition@0 {
					label = "u-boot env";
					reg = <0 0x020000>;
				};
				partition@20000 {
					/* The LCDK defaults to booting from this partition */
					label = "u-boot";
					reg = <0x020000 0x080000>;
				};
				partition@a0000 {
					label = "free space";
					reg = <0x0a0000 0>;
				};
			};
		};
	};
};

&prictrl {
	status = "okay";
};

&memctrl {
	status = "okay";
};

&lcdc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&lcd_pins>;

	port {
		lcdc_out_vga: endpoint {
			remote-endpoint = <&vga_bridge_in>;
		};
	};
};

&vpif {
	pinctrl-names = "default";
	pinctrl-0 = <&vpif_capture_pins>;
	status = "okay";
};

&dsp {
	memory-region = <&dsp_memory_region>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device tree for LEGO MINDSTORMS EV3
 *
 * Copyright (C) 2017 David Lechner <david@lechnology.com>
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pwm/pwm.h>

#include "da850.dtsi"

/ {
	compatible = "lego,ev3", "ti,da850";
	model = "LEGO MINDSTORMS EV3";

	aliases {
		serial1 = &serial1;
	};

	memory@c0000000 {
		device_type = "memory";
		reg = <0xc0000000 0x04000000>;
	};

	/*
	 * The buttons on the EV3 are mapped to keyboard keys.
	 */
	gpio_keys {
		compatible = "gpio-keys";
		label = "EV3 Brick Buttons";
		pinctrl-names = "default";
		pinctrl-0 = <&button_bias>;

		center {
			label = "Center";
			linux,code = <KEY_ENTER>;
			gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
		};

		left {
			label = "Left";
			linux,code = <KEY_LEFT>;
			gpios = <&gpio 102 GPIO_ACTIVE_HIGH>;
		};

		back {
			label = "Back";
			linux,code = <KEY_BACKSPACE>;
			gpios = <&gpio 106 GPIO_ACTIVE_HIGH>;
		};

		right {
			label = "Right";
			linux,code = <KEY_RIGHT>;
			gpios = <&gpio 124 GPIO_ACTIVE_HIGH>;
		};

		down {
			label = "Down";
			linux,code = <KEY_DOWN>;
			gpios = <&gpio 126 GPIO_ACTIVE_HIGH>;
		};

		up {
			label = "Up";
			linux,code = <KEY_UP>;
			gpios = <&gpio 127 GPIO_ACTIVE_HIGH>;
		};
	};

	/*
	 * The EV3 has two built-in bi-color LEDs behind the buttons.
	 */
	leds {
		compatible = "gpio-leds";

		left_green {
			label = "led0:green:brick-status";
			/* GP6[13] */
			gpios = <&gpio 103 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "default-on";
		};

		right_red {
			label = "led1:red:brick-status";
			/* GP6[7] */
			gpios = <&gpio 108 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "default-on";
		};

		left_red {
			label = "led0:red:brick-status";
			/* GP6[12] */
			gpios = <&gpio 109 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "default-on";
		};

		right_green {
			label = "led1:green:brick-status";
			/* GP6[14] */
			gpios = <&gpio 110 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "default-on";
		};
	};

	/*
	 * The EV3 is powered down by turning off the main 5V supply.
	 */
	gpio-poweroff {
		compatible = "gpio-poweroff";
		gpios = <&gpio 107 GPIO_ACTIVE_LOW>;
	};

	sound {
		compatible = "pwm-beeper";
		pinctrl-names = "default";
		pinctrl-0 = <&ehrpwm0b_pins>;
		pwms = <&ehrpwm0 1 1000000 0>;
		amp-supply = <&amp>;
	};

	cvdd: regulator0 {
		compatible = "regulator-fixed";
		regulator-name = "cvdd";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		regulator-always-on;
		regulator-boot-on;
	};

	/*
	 * This is a 5V current limiting regulator that is shared by USB,
	 * the sensor (input) ports, the motor (output) ports and the A/DC.
	 */
	vcc5v: regulator1 {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio 101 0>;
		over-current-gpios = <&gpio 99 GPIO_ACTIVE_LOW>;
		enable-active-high;
		regulator-boot-on;
	};

	/*
	 * This is a simple voltage divider on VCC5V to provide a 2.5V
	 * reference signal to the ADC.
	 */
	adc_ref: regulator2 {
		compatible = "regulator-fixed";
		regulator-name = "adc ref";
		regulator-min-microvolt = <2500000>;
		regulator-max-microvolt = <2500000>;
		regulator-boot-on;
		vin-supply = <&vcc5v>;
	};

	/*
	 * This is the amplifier for the speaker.
	 */
	amp: regulator3 {
		compatible = "regulator-fixed";
		regulator-name = "amp";
		gpio = <&gpio 111 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	/*
	 * The EV3 can use 6-AA batteries or a rechargeable Li-ion battery pack.
	 */
	battery {
		compatible = "lego,ev3-battery";
		io-channels = <&adc 4>, <&adc 3>;
		io-channel-names = "voltage", "current";
		rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>;
	};

	bt_slow_clk: bt-clock {
		pinctrl-names = "default";
		pinctrl-0 = <&ecap2_pins>, <&bt_clock_bias>;
		compatible = "pwm-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		pwms = <&ecap2 0 30518 0>;
	};

	/* ARM local RAM */
	memory@ffff0000 {
		compatible = "syscon", "simple-mfd";
		reg = <0xffff0000 0x2000>; /* 8k */

		/*
		 * The I2C bootloader looks for this magic value to either
		 * boot normally or boot into a firmware update mode.
		 */
		reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x1ffc>;
			mode-normal = <0x00000000>;
			mode-loader = <0x5555aaaa>;
		};
	};
};

&ref_clk {
	clock-frequency = <24000000>;
};

&cpu {
	cpu-supply = <&cvdd>;
};

/* since we have a fixed regulator, we can't run at these points */
&opp_100 {
	status = "disabled";
};

&opp_200 {
	status = "disabled";
};

/*
 * The SoC is actually the 456MHz version, but because of the fixed regulator
 * This is the fastest we can go.
 */
&opp_375 {
	status = "okay";
};

&pmx_core {
	status = "okay";

	ev3_lcd_pins: pinmux_lcd {
		pinctrl-single,bits = <
			/* SIMO, CLK */
			0x14 0x00100100 0x00f00f00
		>;
	};
};

&pinconf {
	status = "okay";

	/* Buttons have external pulldown resistors */
	button_bias: button-bias-groups {
		disable {
			groups = "cp5", "cp24", "cp25", "cp28";
			bias-disable;
		};
	};

	bt_clock_bias: bt-clock-bias-groups {
		disable {
			groups = "cp2";
			bias-disable;
		};
	};

	bt_pic_bias: bt-pic-bias-groups {
		disable {
			groups = "cp20";
			bias-disable;
		};
	};
};

/* Input port 1 */
&serial1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&serial1_rxtx_pins>;
};

&serial2 {
	pinctrl-names = "default";
	pinctrl-0 = <&serial2_rxtx_pins>, <&serial2_rtscts_pins>, <&bt_pic_bias>;
	status = "okay";

	bluetooth {
		compatible = "ti,cc2560";
		clocks = <&bt_slow_clk>;
		clock-names = "ext_clock";
		enable-gpios = <&gpio 73 GPIO_ACTIVE_HIGH>;
		max-speed = <2000000>;
		nvmem-cells = <&bdaddr>;
		nvmem-cell-names = "bd-address";
	};
};

&rtc0 {
	status = "okay";
};

&i2c0 {
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;

	/*
	 * EEPROM contains the first stage bootloader, HW ID and Bluetooth MAC.
	 */
	eeprom@50 {
		compatible = "microchip,24c128", "atmel,24c128";
		pagesize = <64>;
		read-only;
		reg = <0x50>;
		#address-cells = <1>;
		#size-cells = <1>;

		bdaddr: bdaddr@3f06 {
			reg = <0x3f06 0x06>;
		};
	};
};

&wdt {
	status = "okay";
};

&mmc0 {
	status = "okay";
	max-frequency = <50000000>;
	bus-width = <4>;
	cd-gpios = <&gpio 94 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
};

&spi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>, <&spi0_cs3_pin>;

	flash@0 {
		compatible = "n25q128a13", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <50000000>;
		ti,spi-wdelay = <8>;

		/* Partitions are based on the official firmware from LEGO */
		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0 0x40000>;
			};

			partition@40000 {
				label = "U-Boot Env";
				reg = <0x40000 0x10000>;
			};

			partition@50000 {
				label = "Kernel";
				reg = <0x50000 0x200000>;
			};

			partition@250000 {
				label = "Filesystem";
				reg = <0x250000 0xa50000>;
			};

			partition@cb0000 {
				label = "Storage";
				reg = <0xcb0000 0x2f0000>;
			};
		};
	};

	adc: adc@3 {
		compatible = "ti,ads7957";
		reg = <3>;
		#io-channel-cells = <1>;
		spi-max-frequency = <1000000>;
		ti,spi-wdelay = <63>;
		vref-supply = <&adc_ref>;
	};
};

&spi1 {
	status = "okay";
	pinctrl-0 = <&ev3_lcd_pins>;
	pinctrl-names = "default";
	cs-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;

	display@0{
		compatible = "lego,ev3-lcd";
		reg = <0>;
		spi-max-frequency = <10000000>;
		a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
	};
};

&ecap2 {
	status = "okay";
};

&ehrpwm0 {
	status = "okay";
};

&gpio {
	status = "okay";

	/* Don't pull down battery voltage adc io channel */
	batt_volt_en {
		gpio-hog;
		gpios = <6 GPIO_ACTIVE_HIGH>;
		output-high;
	};

	/* Don't impede Bluetooth clock signal */
	bt_clock_en {
		gpio-hog;
		gpios = <5 GPIO_ACTIVE_HIGH>;
		input;
	};

	/*
	 * There is a PIC microcontroller for interfacing with an Apple MFi
	 * chip. This interferes with normal Bluetooth operation, so we need
	 * to make sure it is turned off. Note: The publicly available
	 * schematics from LEGO don't show that these pins are connected to
	 * anything, but they are present in the source code from LEGO.
	 */

	bt_pic_en {
		gpio-hog;
		gpios = <51 GPIO_ACTIVE_HIGH>;
		output-low;
	};

	bt_pic_rst {
		gpio-hog;
		gpios = <78 GPIO_ACTIVE_HIGH>;
		output-high;
	};

	bt_pic_cts {
		gpio-hog;
		gpios = <87 GPIO_ACTIVE_HIGH>;
		input;
	};
};

&usb_phy {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
	vbus-supply = <&vcc5v>;
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 DENX Software Engineering GmbH
 * Heiko Schocher <hs@denx.de>
 */
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };
	aliases { };

	memory@c0000000 {
		device_type = "memory";
		reg = <0xc0000000 0x0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu: cpu@0 {
			compatible = "arm,arm926ej-s";
			device_type = "cpu";
			reg = <0>;
			clocks = <&psc0 14>;
			operating-points-v2 = <&opp_table>;
		};
	};

	opp_table: opp-table {
		compatible = "operating-points-v2";

		opp_100: opp100-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			opp-microvolt = <1000000 950000 1050000>;
		};

		opp_200: opp110-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			opp-microvolt = <1100000 1050000 1160000>;
		};

		opp_300: opp120-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <1200000 1140000 1320000>;
		};

		/*
		 * Original silicon was 300MHz max, so higher frequencies
		 * need to be enabled on a per-board basis if the chip is
		 * capable.
		 */

		opp_375: opp120-375000000 {
			status = "disabled";
			opp-hz = /bits/ 64 <375000000>;
			opp-microvolt = <1200000 1140000 1320000>;
		};

		opp_456: opp130-456000000 {
			status = "disabled";
			opp-hz = /bits/ 64 <456000000>;
			opp-microvolt = <1300000 1250000 1350000>;
		};
	};

	arm {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		intc: interrupt-controller@fffee000 {
			compatible = "ti,cp-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,intc-size = <101>;
			reg = <0xfffee000 0x2000>;
		};
	};
	clocks: clocks {
		ref_clk: ref_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-output-names = "ref_clk";
		};
		sata_refclk: sata_refclk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-output-names = "sata_refclk";
			status = "disabled";
		};
		usb_refclkin: usb_refclkin {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-output-names = "usb_refclkin";
			status = "disabled";
		};
	};
	dsp: dsp@11800000 {
		compatible = "ti,da850-dsp";
		reg = <0x11800000 0x40000>,
		      <0x11e00000 0x8000>,
		      <0x11f00000 0x8000>,
		      <0x01c14044 0x4>,
		      <0x01c14174 0x8>;
		reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
		interrupt-parent = <&intc>;
		interrupts = <28>;
		clocks = <&psc0 15>;
		resets = <&psc0 15>;
		status = "disabled";
	};
	soc@1c00000 {
		compatible = "simple-bus";
		model = "da850";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x01c00000 0x400000>;
		interrupt-parent = <&intc>;

		psc0: clock-controller@10000 {
			compatible = "ti,da850-psc0";
			reg = <0x10000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
				 <&pll0_sysclk 4>, <&pll0_sysclk 6>,
				 <&async1_clk>;
			clock-names = "pll0_sysclk1", "pll0_sysclk2",
				      "pll0_sysclk4", "pll0_sysclk6",
				      "async1";
		};
		pll0: clock-controller@11000 {
			compatible = "ti,da850-pll0";
			reg = <0x11000 0x1000>;
			clocks = <&ref_clk>, <&pll1_sysclk 3>;
			clock-names = "clksrc", "extclksrc";

			pll0_pllout: pllout {
				#clock-cells = <0>;
			};
			pll0_sysclk: sysclk {
				#clock-cells = <1>;
			};
			pll0_auxclk: auxclk {
				#clock-cells = <0>;
			};
			pll0_obsclk: obsclk {
				#clock-cells = <0>;
			};
		};
		pmx_core: pinmux@14120 {
			compatible = "pinctrl-single";
			reg = <0x14120 0x50>;
			#pinctrl-cells = <2>;
			pinctrl-single,bit-per-mux;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0xf>;
			/* pin base, nr pins & gpio function */
			pinctrl-single,gpio-range = <&range   0 17 0x8>,
						    <&range  17  8 0x4>,
						    <&range  26  8 0x4>,
						    <&range  34 80 0x8>,
						    <&range 129 31 0x8>;
			status = "disabled";

			range: gpio-range {
				#pinctrl-single,gpio-range-cells = <3>;
			};

			serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
				pinctrl-single,bits = <
					/* UART0_RTS UART0_CTS */
					0x0c 0x22000000 0xff000000
				>;
			};
			serial0_rxtx_pins: pinmux_serial0_rxtx_pins {
				pinctrl-single,bits = <
					/* UART0_TXD UART0_RXD */
					0x0c 0x00220000 0x00ff0000
				>;
			};
			serial1_rtscts_pins: pinmux_serial1_rtscts_pins {
				pinctrl-single,bits = <
					/* UART1_CTS UART1_RTS */
					0x00 0x00440000 0x00ff0000
				>;
			};
			serial1_rxtx_pins: pinmux_serial1_rxtx_pins {
				pinctrl-single,bits = <
					/* UART1_TXD UART1_RXD */
					0x10 0x22000000 0xff000000
				>;
			};
			serial2_rtscts_pins: pinmux_serial2_rtscts_pins {
				pinctrl-single,bits = <
					/* UART2_CTS UART2_RTS */
					0x00 0x44000000 0xff000000
				>;
			};
			serial2_rxtx_pins: pinmux_serial2_rxtx_pins {
				pinctrl-single,bits = <
					/* UART2_TXD UART2_RXD */
					0x10 0x00220000 0x00ff0000
				>;
			};
			i2c0_pins: pinmux_i2c0_pins {
				pinctrl-single,bits = <
					/* I2C0_SDA,I2C0_SCL */
					0x10 0x00002200 0x0000ff00
				>;
			};
			i2c1_pins: pinmux_i2c1_pins {
				pinctrl-single,bits = <
					/* I2C1_SDA, I2C1_SCL */
					0x10 0x00440000 0x00ff0000
				>;
			};
			mmc0_pins: pinmux_mmc_pins {
				pinctrl-single,bits = <
					/* MMCSD0_DAT[3] MMCSD0_DAT[2]
					 * MMCSD0_DAT[1] MMCSD0_DAT[0]
					 * MMCSD0_CMD    MMCSD0_CLK
					 */
					0x28 0x00222222  0x00ffffff
				>;
			};
			ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
				pinctrl-single,bits = <
					/* EPWM0A */
					0xc 0x00000002 0x0000000f
				>;
			};
			ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
				pinctrl-single,bits = <
					/* EPWM0B */
					0xc 0x00000020 0x000000f0
				>;
			};
			ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
				pinctrl-single,bits = <
					/* EPWM1A */
					0x14 0x00000002 0x0000000f
				>;
			};
			ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
				pinctrl-single,bits = <
					/* EPWM1B */
					0x14 0x00000020 0x000000f0
				>;
			};
			ecap0_pins: pinmux_ecap0_pins {
				pinctrl-single,bits = <
					/* ECAP0_APWM0 */
					0x8 0x20000000 0xf0000000
				>;
			};
			ecap1_pins: pinmux_ecap1_pins {
				pinctrl-single,bits = <
					/* ECAP1_APWM1 */
					0x4 0x40000000 0xf0000000
				>;
			};
			ecap2_pins: pinmux_ecap2_pins {
				pinctrl-single,bits = <
					/* ECAP2_APWM2 */
					0x4 0x00000004 0x0000000f
				>;
			};
			spi0_pins: pinmux_spi0_pins {
				pinctrl-single,bits = <
					/* SIMO, SOMI, CLK */
					0xc 0x00001101 0x0000ff0f
				>;
			};
			spi0_cs0_pin: pinmux_spi0_cs0 {
				pinctrl-single,bits = <
					/* CS0 */
					0x10 0x00000010 0x000000f0
				>;
			};
			spi0_cs3_pin: pinmux_spi0_cs3_pin {
				pinctrl-single,bits = <
					/* CS3 */
					0xc 0x01000000 0x0f000000
				>;
			};
			spi1_pins: pinmux_spi1_pins {
				pinctrl-single,bits = <
					/* SIMO, SOMI, CLK */
					0x14 0x00110100 0x00ff0f00
				>;
			};
			spi1_cs0_pin: pinmux_spi1_cs0 {
				pinctrl-single,bits = <
					/* CS0 */
					0x14 0x00000010 0x000000f0
				>;
			};
			mdio_pins: pinmux_mdio_pins {
				pinctrl-single,bits = <
					/* MDIO_CLK, MDIO_D */
					0x10 0x00000088 0x000000ff
				>;
			};
			mii_pins: pinmux_mii_pins {
				pinctrl-single,bits = <
					/*
					 * MII_TXEN, MII_TXCLK, MII_COL
					 * MII_TXD_3, MII_TXD_2, MII_TXD_1
					 * MII_TXD_0
					 */
					0x8 0x88888880 0xfffffff0
					/*
					 * MII_RXER, MII_CRS, MII_RXCLK
					 * MII_RXDV, MII_RXD_3, MII_RXD_2
					 * MII_RXD_1, MII_RXD_0
					 */
					0xc 0x88888888 0xffffffff
				>;
			};
			lcd_pins: pinmux_lcd_pins {
				pinctrl-single,bits = <
					/*
					 * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
					 * LCD_D[6], LCD_D[7]
					 */
					0x40 0x22222200 0xffffff00
					/*
					 * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
					 * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
					 */
					0x44 0x22222222 0xffffffff
					/* LCD_D[8], LCD_D[9] */
					0x48 0x00000022 0x000000ff

					/* LCD_PCLK */
					0x48 0x02000000 0x0f000000
					/* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
					0x4c 0x02000022 0x0f0000ff
				>;
			};
			vpif_capture_pins: vpif_capture_pins {
				pinctrl-single,bits = <
					/* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */
					0x38 0x11111111 0xffffffff
					/* VP_DIN[10..15,0..1] */
					0x3c 0x11111111 0xffffffff
					/* VP_DIN[8..9] */
					0x40 0x00000011 0x000000ff
				>;
			};
			vpif_display_pins: vpif_display_pins {
				pinctrl-single,bits = <
					/* VP_DOUT[2..7] */
					0x40 0x11111100 0xffffff00
					/* VP_DOUT[10..15,0..1] */
					0x44 0x11111111 0xffffffff
					/*  VP_DOUT[8..9] */
					0x48 0x00000011 0x000000ff
					/*
					 * VP_CLKOUT3, VP_CLKIN3,
					 * VP_CLKOUT2, VP_CLKIN2
					 */
					0x4c 0x00111100 0x00ffff00
				>;
			};
		};
		prictrl: priority-controller@14110 {
			compatible = "ti,da850-mstpri";
			reg = <0x14110 0x0c>;
			status = "disabled";
		};
		cfgchip: chip-controller@1417c {
			compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
			reg = <0x1417c 0x14>;

			usb_phy: usb-phy {
				compatible = "ti,da830-usb-phy";
				#phy-cells = <1>;
				clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>;
				clock-names = "usb0_clk48", "usb1_clk48";
				status = "disabled";
			};
			usb_phy_clk: usb-phy-clocks {
				compatible = "ti,da830-usb-phy-clocks";
				#clock-cells = <1>;
				clocks = <&psc1 1>, <&usb_refclkin>,
					 <&pll0_auxclk>;
				clock-names = "fck", "usb_refclkin", "auxclk";
			};
			ehrpwm_tbclk: ehrpwm_tbclk {
				compatible = "ti,da830-tbclksync";
				#clock-cells = <0>;
				clocks = <&psc1 17>;
				clock-names = "fck";
			};
			div4p5_clk: div4.5 {
				compatible = "ti,da830-div4p5ena";
				#clock-cells = <0>;
				clocks = <&pll0_pllout>;
				clock-names = "pll0_pllout";
			};
			async1_clk: async1 {
				compatible = "ti,da850-async1-clksrc";
				#clock-cells = <0>;
				clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
				clock-names = "pll0_sysclk3", "div4.5";
			};
			async3_clk: async3 {
				compatible = "ti,da850-async3-clksrc";
				#clock-cells = <0>;
				clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
				clock-names = "pll0_sysclk2", "pll1_sysclk2";
			};
		};
		edma0: edma@0 {
			compatible = "ti,edma3-tpcc";
			/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
			reg = <0x0 0x8000>;
			reg-names = "edma3_cc";
			interrupts = <11 12>;
			interrupt-names = "edma3_ccint", "edma3_ccerrint";
			#dma-cells = <2>;

			ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
			power-domains = <&psc0 0>;
		};
		edma0_tptc0: tptc@8000 {
			compatible = "ti,edma3-tptc";
			reg = <0x8000 0x400>;
			interrupts = <13>;
			interrupt-names = "edm3_tcerrint";
			power-domains = <&psc0 1>;
		};
		edma0_tptc1: tptc@8400 {
			compatible = "ti,edma3-tptc";
			reg = <0x8400 0x400>;
			interrupts = <32>;
			interrupt-names = "edm3_tcerrint";
			power-domains = <&psc0 2>;
		};
		edma1: edma@230000 {
			compatible = "ti,edma3-tpcc";
			/* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
			reg = <0x230000 0x8000>;
			reg-names = "edma3_cc";
			interrupts = <93 94>;
			interrupt-names = "edma3_ccint", "edma3_ccerrint";
			#dma-cells = <2>;

			ti,tptcs = <&edma1_tptc0 7>;
			power-domains = <&psc1 0>;
		};
		edma1_tptc0: tptc@238000 {
			compatible = "ti,edma3-tptc";
			reg = <0x238000 0x400>;
			interrupts = <95>;
			interrupt-names = "edm3_tcerrint";
			power-domains = <&psc1 21>;
		};
		serial0: serial@42000 {
			compatible = "ti,da830-uart", "ns16550a";
			reg = <0x42000 0x100>;
			reg-io-width = <4>;
			reg-shift = <2>;
			interrupts = <25>;
			clocks = <&psc0 9>;
			power-domains = <&psc0 9>;
			status = "disabled";
		};
		serial1: serial@10c000 {
			compatible = "ti,da830-uart", "ns16550a";
			reg = <0x10c000 0x100>;
			reg-io-width = <4>;
			reg-shift = <2>;
			interrupts = <53>;
			clocks = <&psc1 12>;
			power-domains = <&psc1 12>;
			status = "disabled";
		};
		serial2: serial@10d000 {
			compatible = "ti,da830-uart", "ns16550a";
			reg = <0x10d000 0x100>;
			reg-io-width = <4>;
			reg-shift = <2>;
			interrupts = <61>;
			clocks = <&psc1 13>;
			power-domains = <&psc1 13>;
			status = "disabled";
		};
		rtc0: rtc@23000 {
			compatible = "ti,da830-rtc";
			reg = <0x23000 0x1000>;
			interrupts = <19
				      19>;
			clocks = <&pll0_auxclk>;
			clock-names = "int-clk";
			status = "disabled";
		};
		i2c0: i2c@22000 {
			compatible = "ti,davinci-i2c";
			reg = <0x22000 0x1000>;
			interrupts = <15>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&pll0_auxclk>;
			status = "disabled";
		};
		i2c1: i2c@228000 {
			compatible = "ti,davinci-i2c";
			reg = <0x228000 0x1000>;
			interrupts = <51>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&psc1 11>;
			power-domains = <&psc1 11>;
			status = "disabled";
		};
		clocksource: timer@20000 {
			compatible = "ti,da830-timer";
			reg = <0x20000 0x1000>;
			interrupts = <21>, <22>;
			interrupt-names = "tint12", "tint34";
			clocks = <&pll0_auxclk>;
		};
		wdt: wdt@21000 {
			compatible = "ti,davinci-wdt";
			reg = <0x21000 0x1000>;
			clocks = <&pll0_auxclk>;
			status = "disabled";
		};
		mmc0: mmc@40000 {
			compatible = "ti,da830-mmc";
			reg = <0x40000 0x1000>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			interrupts = <16>;
			dmas = <&edma0 16 0>, <&edma0 17 0>;
			dma-names = "rx", "tx";
			clocks = <&psc0 5>;
			status = "disabled";
		};
		vpif: video@217000 {
			compatible = "ti,da850-vpif";
			reg = <0x217000 0x1000>;
			interrupts = <92>;
			power-domains = <&psc1 9>;
			status = "disabled";

			/* VPIF capture port */
			port@0 {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			/* VPIF display port */
			port@1 {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};
		mmc1: mmc@21b000 {
			compatible = "ti,da830-mmc";
			reg = <0x21b000 0x1000>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			interrupts = <72>;
			dmas = <&edma1 28 0>, <&edma1 29 0>;
			dma-names = "rx", "tx";
			clocks = <&psc1 18>;
			status = "disabled";
		};
		ehrpwm0: pwm@300000 {
			compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <3>;
			reg = <0x300000 0x2000>;
			clocks = <&psc1 17>, <&ehrpwm_tbclk>;
			clock-names = "fck", "tbclk";
			power-domains = <&psc1 17>;
			status = "disabled";
		};
		ehrpwm1: pwm@302000 {
			compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm";
			#pwm-cells = <3>;
			reg = <0x302000 0x2000>;
			clocks = <&psc1 17>, <&ehrpwm_tbclk>;
			clock-names = "fck", "tbclk";
			power-domains = <&psc1 17>;
			status = "disabled";
		};
		ecap0: pwm@306000 {
			compatible = "ti,da850-ecap", "ti,am3352-ecap";
			#pwm-cells = <3>;
			reg = <0x306000 0x80>;
			clocks = <&psc1 20>;
			clock-names = "fck";
			power-domains = <&psc1 20>;
			status = "disabled";
		};
		ecap1: pwm@307000 {
			compatible = "ti,da850-ecap", "ti,am3352-ecap";
			#pwm-cells = <3>;
			reg = <0x307000 0x80>;
			clocks = <&psc1 20>;
			clock-names = "fck";
			power-domains = <&psc1 20>;
			status = "disabled";
		};
		ecap2: pwm@308000 {
			compatible = "ti,da850-ecap", "ti,am3352-ecap";
			#pwm-cells = <3>;
			reg = <0x308000 0x80>;
			clocks = <&psc1 20>;
			clock-names = "fck";
			power-domains = <&psc1 20>;
			status = "disabled";
		};
		spi0: spi@41000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "ti,da830-spi";
			reg = <0x41000 0x1000>;
			num-cs = <6>;
			ti,davinci-spi-intr-line = <1>;
			interrupts = <20>;
			dmas = <&edma0 14 0>, <&edma0 15 0>;
			dma-names = "rx", "tx";
			clocks = <&psc0 4>;
			power-domains = <&psc0 4>;
			status = "disabled";
		};
		spi1: spi@30e000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "ti,da830-spi";
			reg = <0x30e000 0x1000>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <1>;
			interrupts = <56>;
			dmas = <&edma0 18 0>, <&edma0 19 0>;
			dma-names = "rx", "tx";
			clocks = <&psc1 10>;
			power-domains = <&psc1 10>;
			status = "disabled";
		};
		usb0: usb@200000 {
			compatible = "ti,da830-musb";
			reg = <0x200000 0x1000>;
			ranges;
			interrupts = <58>;
			interrupt-names = "mc";
			dr_mode = "otg";
			phys = <&usb_phy 0>;
			phy-names = "usb-phy";
			clocks = <&psc1 1>;
			clock-ranges;
			status = "disabled";

			#address-cells = <1>;
			#size-cells = <1>;

			dmas = <&cppi41dma 0 0 &cppi41dma 1 0
				&cppi41dma 2 0 &cppi41dma 3 0
				&cppi41dma 0 1 &cppi41dma 1 1
				&cppi41dma 2 1 &cppi41dma 3 1>;
			dma-names =
				"rx1", "rx2", "rx3", "rx4",
				"tx1", "tx2", "tx3", "tx4";

			cppi41dma: dma-controller@201000 {
				compatible = "ti,da830-cppi41";
				reg = <0x201000 0x1000
					0x202000 0x1000
					0x204000 0x4000>;
				reg-names = "controller",
					    "scheduler", "queuemgr";
				interrupts = <58>;
				#dma-cells = <2>;
				/* For backwards compatibility: */
				#dma-channels = <4>;
				dma-channels = <4>;
				power-domains = <&psc1 1>;
				status = "okay";
			};
		};
		sata: sata@218000 {
			compatible = "ti,da850-ahci";
			reg = <0x218000 0x2000>, <0x22c018 0x4>;
			interrupts = <67>;
			clocks = <&psc1 8>, <&sata_refclk>;
			clock-names = "fck", "refclk";
			status = "disabled";
		};
		pll1: clock-controller@21a000 {
			compatible = "ti,da850-pll1";
			reg = <0x21a000 0x1000>;
			clocks = <&ref_clk>;
			clock-names = "clksrc";

			pll1_sysclk: sysclk {
				#clock-cells = <1>;
			};
			pll1_obsclk: obsclk {
				#clock-cells = <0>;
			};
		};
		mdio: mdio@224000 {
			compatible = "ti,davinci_mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x224000 0x1000>;
			clocks = <&psc1 5>;
			clock-names = "fck";
			power-domains = <&psc1 5>;
			status = "disabled";
		};
		eth0: ethernet@220000 {
			compatible = "ti,davinci-dm6467-emac";
			reg = <0x220000 0x4000>;
			ti,davinci-ctrl-reg-offset = <0x3000>;
			ti,davinci-ctrl-mod-reg-offset = <0x2000>;
			ti,davinci-ctrl-ram-offset = <0>;
			ti,davinci-ctrl-ram-size = <0x2000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <33
					34
					35
					36
					>;
			clocks = <&psc1 5>;
			power-domains = <&psc1 5>;
			status = "disabled";
		};
		usb1: usb@225000 {
			compatible = "ti,da830-ohci";
			reg = <0x225000 0x1000>;
			interrupts = <59>;
			phys = <&usb_phy 1>;
			phy-names = "usb-phy";
			clocks = <&psc1 2>;
			status = "disabled";
		};
		gpio: gpio@226000 {
			compatible = "ti,dm6441-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0x226000 0x1000>;
			interrupts = <42 43 44 45 46 47 48 49 50>;
			ti,ngpio = <144>;
			ti,davinci-gpio-unbanked = <0>;
			clocks = <&psc1 3>;
			clock-names = "gpio";
			status = "disabled";
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx_core   0  15 1>,
				      <&pmx_core   1  14 1>,
				      <&pmx_core   2  13 1>,
				      <&pmx_core   3  12 1>,
				      <&pmx_core   4  11 1>,
				      <&pmx_core   5  10 1>,
				      <&pmx_core   6   9 1>,
				      <&pmx_core   7   8 1>,
				      <&pmx_core   8   7 1>,
				      <&pmx_core   9   6 1>,
				      <&pmx_core  10   5 1>,
				      <&pmx_core  11   4 1>,
				      <&pmx_core  12   3 1>,
				      <&pmx_core  13   2 1>,
				      <&pmx_core  14   1 1>,
				      <&pmx_core  15   0 1>,
				      <&pmx_core  16  39 1>,
				      <&pmx_core  17  38 1>,
				      <&pmx_core  18  37 1>,
				      <&pmx_core  19  36 1>,
				      <&pmx_core  20  35 1>,
				      <&pmx_core  21  34 1>,
				      <&pmx_core  22  33 1>,
				      <&pmx_core  23  32 1>,
				      <&pmx_core  24  24 1>,
				      <&pmx_core  25  22 1>,
				      <&pmx_core  26  21 1>,
				      <&pmx_core  27  20 1>,
				      <&pmx_core  28  19 1>,
				      <&pmx_core  29  18 1>,
				      <&pmx_core  30  17 1>,
				      <&pmx_core  31  16 1>,
				      <&pmx_core  32  55 1>,
				      <&pmx_core  33  54 1>,
				      <&pmx_core  34  53 1>,
				      <&pmx_core  35  52 1>,
				      <&pmx_core  36  51 1>,
				      <&pmx_core  37  50 1>,
				      <&pmx_core  38  49 1>,
				      <&pmx_core  39  48 1>,
				      <&pmx_core  40  47 1>,
				      <&pmx_core  41  46 1>,
				      <&pmx_core  42  45 1>,
				      <&pmx_core  43  44 1>,
				      <&pmx_core  44  43 1>,
				      <&pmx_core  45  42 1>,
				      <&pmx_core  46  41 1>,
				      <&pmx_core  47  40 1>,
				      <&pmx_core  48  71 1>,
				      <&pmx_core  49  70 1>,
				      <&pmx_core  50  69 1>,
				      <&pmx_core  51  68 1>,
				      <&pmx_core  52  67 1>,
				      <&pmx_core  53  66 1>,
				      <&pmx_core  54  65 1>,
				      <&pmx_core  55  64 1>,
				      <&pmx_core  56  63 1>,
				      <&pmx_core  57  62 1>,
				      <&pmx_core  58  61 1>,
				      <&pmx_core  59  60 1>,
				      <&pmx_core  60  59 1>,
				      <&pmx_core  61  58 1>,
				      <&pmx_core  62  57 1>,
				      <&pmx_core  63  56 1>,
				      <&pmx_core  64  87 1>,
				      <&pmx_core  65  86 1>,
				      <&pmx_core  66  85 1>,
				      <&pmx_core  67  84 1>,
				      <&pmx_core  68  83 1>,
				      <&pmx_core  69  82 1>,
				      <&pmx_core  70  81 1>,
				      <&pmx_core  71  80 1>,
				      <&pmx_core  72  70 1>,
				      <&pmx_core  73  78 1>,
				      <&pmx_core  74  77 1>,
				      <&pmx_core  75  76 1>,
				      <&pmx_core  76  75 1>,
				      <&pmx_core  77  74 1>,
				      <&pmx_core  78  73 1>,
				      <&pmx_core  79  72 1>,
				      <&pmx_core  80 103 1>,
				      <&pmx_core  81 102 1>,
				      <&pmx_core  82 101 1>,
				      <&pmx_core  83 100 1>,
				      <&pmx_core  84  99 1>,
				      <&pmx_core  85  98 1>,
				      <&pmx_core  86  97 1>,
				      <&pmx_core  87  96 1>,
				      <&pmx_core  88  95 1>,
				      <&pmx_core  89  94 1>,
				      <&pmx_core  90  93 1>,
				      <&pmx_core  91  92 1>,
				      <&pmx_core  92  91 1>,
				      <&pmx_core  93  90 1>,
				      <&pmx_core  94  89 1>,
				      <&pmx_core  95  88 1>,
				      <&pmx_core  96 158 1>,
				      <&pmx_core  97 157 1>,
				      <&pmx_core  98 156 1>,
				      <&pmx_core  99 155 1>,
				      <&pmx_core 100 154 1>,
				      <&pmx_core 101 129 1>,
				      <&pmx_core 102 113 1>,
				      <&pmx_core 103 112 1>,
				      <&pmx_core 104 111 1>,
				      <&pmx_core 105 110 1>,
				      <&pmx_core 106 109 1>,
				      <&pmx_core 107 108 1>,
				      <&pmx_core 108 107 1>,
				      <&pmx_core 109 106 1>,
				      <&pmx_core 110 105 1>,
				      <&pmx_core 111 104 1>,
				      <&pmx_core 112 145 1>,
				      <&pmx_core 113 144 1>,
				      <&pmx_core 114 143 1>,
				      <&pmx_core 115 142 1>,
				      <&pmx_core 116 141 1>,
				      <&pmx_core 117 140 1>,
				      <&pmx_core 118 139 1>,
				      <&pmx_core 119 138 1>,
				      <&pmx_core 120 137 1>,
				      <&pmx_core 121 136 1>,
				      <&pmx_core 122 135 1>,
				      <&pmx_core 123 134 1>,
				      <&pmx_core 124 133 1>,
				      <&pmx_core 125 132 1>,
				      <&pmx_core 126 131 1>,
				      <&pmx_core 127 130 1>,
				      <&pmx_core 128 159 1>,
				      <&pmx_core 129  31 1>,
				      <&pmx_core 130  30 1>,
				      <&pmx_core 131  20 1>,
				      <&pmx_core 132  28 1>,
				      <&pmx_core 133  27 1>,
				      <&pmx_core 134  26 1>,
				      <&pmx_core 135  23 1>,
				      <&pmx_core 136 153 1>,
				      <&pmx_core 137 152 1>,
				      <&pmx_core 138 151 1>,
				      <&pmx_core 139 150 1>,
				      <&pmx_core 140 149 1>,
				      <&pmx_core 141 148 1>,
				      <&pmx_core 142 147 1>,
				      <&pmx_core 143 146 1>;
		};
		psc1: clock-controller@227000 {
			compatible = "ti,da850-psc1";
			reg = <0x227000 0x1000>;
			#clock-cells = <1>;
			#power-domain-cells = <1>;
			clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>,
				 <&async3_clk>;
			clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3";
			assigned-clocks = <&async3_clk>;
			assigned-clock-parents = <&pll1_sysclk 2>;
		};
		pinconf: pin-controller@22c00c {
			compatible = "ti,da850-pupd";
			reg = <0x22c00c 0x8>;
			status = "disabled";
		};

		mcasp0: mcasp@100000 {
			compatible = "ti,da830-mcasp-audio";
			reg = <0x100000 0x2000>,
			      <0x102000 0x400000>;
			reg-names = "mpu", "dat";
			interrupts = <54>;
			interrupt-names = "common";
			power-domains = <&psc1 7>;
			status = "disabled";
			dmas = <&edma0 1 1>,
				<&edma0 0 1>;
			dma-names = "tx", "rx";
		};

		lcdc: display@213000 {
			compatible = "ti,da850-tilcdc";
			reg = <0x213000 0x1000>;
			interrupts = <52>;
			max-pixelclock = <37500>;
			clocks = <&psc1 16>;
			clock-names = "fck";
			power-domains = <&psc1 16>;
			status = "disabled";
		};
	};
	aemif: aemif@68000000 {
		compatible = "ti,da850-aemif";
		#address-cells = <2>;
		#size-cells = <1>;

		reg = <0x68000000 0x00008000>;
		ranges = <0 0 0x60000000 0x08000000
			  1 0 0x68000000 0x00008000>;
		clocks = <&psc0 3>;
		clock-names = "aemif";
		clock-ranges;
		status = "disabled";
	};
	memctrl: memory-controller@b0000000 {
		compatible = "ti,da850-ddr-controller";
		reg = <0xb0000000 0xe8>;
		status = "disabled";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
 */

#include "omap36xx.dtsi"

&sgx_module {
	status = "disabled";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;

#include "dm814x.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "DM8148 EVM";
	compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;	/* 1 GB */
	};

	/* MIC94060YC6 controlled by SD1_POW pin */
	vmmcsd_fixed: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "vmmcsd_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&cpsw_emac0 {
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-id";
};

&cpsw_emac1 {
	phy-handle = <&ethphy1>;
	phy-mode = "rgmii-id";
};

&davinci_mdio {
	ethphy0: ethernet-phy@0 {
		reg = <0>;
	};

	ethphy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&gpmc {
	ranges = <0 0 0x04000000 0x01000000>;	/* CS0: 16MB for NAND */

	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>; /* termcount */
		linux,mtd-name = "micron,mt29f2g16aadwp";
		#address-cells = <1>;
		#size-cells = <1>;
		ti,nand-ecc-opt = "bch8";
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <44>;
		gpmc,cs-wr-off-ns = <44>;
		gpmc,adv-on-ns = <6>;
		gpmc,adv-rd-off-ns = <34>;
		gpmc,adv-wr-off-ns = <44>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <40>;
		gpmc,oe-on-ns = <0>;
		gpmc,oe-off-ns = <54>;
		gpmc,access-ns = <64>;
		gpmc,rd-cycle-ns = <82>;
		gpmc,wr-cycle-ns = <82>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-access-ns = <40>;
		gpmc,wr-data-mux-bus-ns = <0>;
		partition@0 {
			label = "X-Loader";
			reg = <0 0x80000>;
		};
		partition@80000 {
			label = "U-Boot";
			reg = <0x80000 0x1c0000>;
		};
		partition@1c0000 {
			label = "Environment";
			reg = <0x240000 0x40000>;
		};
		partition@280000 {
			label = "Kernel";
			reg = <0x280000 0x500000>;
		};
		partition@780000 {
			label = "Filesystem";
			reg = <0x780000 0xf880000>;
		};
	};
};

&mmc1 {
        status = "disabled";
};

&mmc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd1_pins>;
	vmmc-supply = <&vmmcsd_fixed>;
	bus-width = <4>;
	cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
};

&mmc3 {
        status = "disabled";
};

&pincntl {
	sd1_pins: pinmux_sd1_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x0800, PIN_INPUT | 0x1)	/* SD1_CLK */
			DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP |  0x1)	/* SD1_CMD */
			DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP |  0x1)	/* SD1_DAT[0] */
			DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP |  0x1)	/* SD1_DAT[1] */
			DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP |  0x1)	/* SD1_DAT[2] */
			DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP |  0x1)	/* SD1_DAT[3] */
			DM814X_IOPAD(0x0924, PIN_OUTPUT |  0x40)	/* SD1_POW */
			DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP |  0x80)	/* GP1[6] */
			>;
	};

	usb0_pins: pinmux_usb0_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1)	/* USB0_DRVVBUS */
			>;
	};

	usb1_pins: pinmux_usb1_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80)	/* USB1_DRVVBUS */
			>;
	};
};

&usb0 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb0_pins>;
	dr_mode = "host";
};

&usb1 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb1_pins>;
	dr_mode = "host";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;

#include "dm814x.dtsi"

/ {
	model = "HP t410 Smart Zero Client";
	compatible = "hp,t410", "ti,dm8148", "ti,dm814";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;	/* 1 GB */
	};

	/* gpio9 seems to control USB VBUS regulator and/or hub power */
	usb_power: regulator@9 {
		compatible = "regulator-fixed";
		regulator-name = "usb_power";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};

	vmmcsd_fixed: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "vmmcsd_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&cpsw_emac0 {
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-id";
};

&cpsw_emac1 {
	phy-handle = <&ethphy1>;
	phy-mode = "rgmii-id";
};

&davinci_mdio {
	ethphy0: ethernet-phy@0 {
		reg = <0>;
	};

	ethphy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&mmc1 {
	status = "disabled";
};

&mmc2 {
	status = "disabled";
};

&mmc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd2_pins>;
	vmmc-supply = <&vmmcsd_fixed>;
	bus-width = <8>;
	dmas = <&edma_xbar 8 0 1	/* use SDTXEVT1 instead of MCASP0TX */
		&edma_xbar 9 0 2>;	/* use SDRXEVT1 instead of MCASP0RX */
	dma-names = "tx", "rx";
	non-removable;
};

&pincntl {
	sd2_pins: pinmux_sd2_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x09c0, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[7] */
			DM814X_IOPAD(0x09c4, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[6] */
			DM814X_IOPAD(0x09c8, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[5] */
			DM814X_IOPAD(0x09cc, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[4] */
			DM814X_IOPAD(0x09d0, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[3] */
			DM814X_IOPAD(0x09d4, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[2] */
			DM814X_IOPAD(0x09d8, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[1] */
			DM814X_IOPAD(0x09dc, PIN_INPUT_PULLUP | 0x1)	/* SD2_DAT[0] */
			DM814X_IOPAD(0x09e0, PIN_INPUT | 0x1)		/* SD2_CLK */
			DM814X_IOPAD(0x09f4, PIN_INPUT_PULLUP | 0x2)	/* SD2_CMD */
			DM814X_IOPAD(0x0920, PIN_INPUT | 0x40)	/* SD2_SDCD */
			>;
	};

	usb0_pins: pinmux_usb0_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1)	/* USB0_DRVVBUS */
			>;
	};

	usb1_pins: pinmux_usb1_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80)	/* USB1_DRVVBUS */
			>;
	};
};

&usb0 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb0_pins>;
	dr_mode = "host";
};

&usb1 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb1_pins>;
	dr_mode = "host";
};


code:
// SPDX-License-Identifier: GPL-2.0-only

&pllss {
	/*
	 * See TRM "2.6.10 Connected outputso DPLLS" and
	 * "2.6.11 Connected Outputs of DPLLJ". Only clkout is
	 * connected except for hdmi and usb.
	 */
	adpll_mpu_ck: adpll@40 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-s-clock";
		reg = <0x40 0x40>;
		clocks = <&devosc_ck &devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow", "clkinphif";
		clock-output-names = "481c5040.adpll.dcoclkldo",
				     "481c5040.adpll.clkout",
				     "481c5040.adpll.clkoutx2",
				     "481c5040.adpll.clkouthif";
	};

	adpll_dsp_ck: adpll@80 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0x80 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c5080.adpll.dcoclkldo",
				     "481c5080.adpll.clkout",
				     "481c5080.adpll.clkoutldo";
	};

	adpll_sgx_ck: adpll@b0 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0xb0 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c50b0.adpll.dcoclkldo",
				     "481c50b0.adpll.clkout",
				     "481c50b0.adpll.clkoutldo";
	};

	adpll_hdvic_ck: adpll@e0 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0xe0 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c50e0.adpll.dcoclkldo",
				     "481c50e0.adpll.clkout",
				     "481c50e0.adpll.clkoutldo";
	};

	adpll_l3_ck: adpll@110 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0x110 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c5110.adpll.dcoclkldo",
				     "481c5110.adpll.clkout",
				     "481c5110.adpll.clkoutldo";
	};

	adpll_isp_ck: adpll@140 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0x140 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c5140.adpll.dcoclkldo",
				     "481c5140.adpll.clkout",
				     "481c5140.adpll.clkoutldo";
	};

	adpll_dss_ck: adpll@170 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0x170 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c5170.adpll.dcoclkldo",
				     "481c5170.adpll.clkout",
				     "481c5170.adpll.clkoutldo";
	};

	adpll_video0_ck: adpll@1a0 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0x1a0 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c51a0.adpll.dcoclkldo",
				     "481c51a0.adpll.clkout",
				     "481c51a0.adpll.clkoutldo";
	};

	adpll_video1_ck: adpll@1d0 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0x1d0 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c51d0.adpll.dcoclkldo",
				     "481c51d0.adpll.clkout",
				     "481c51d0.adpll.clkoutldo";
	};

	adpll_hdmi_ck: adpll@200 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0x200 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c5200.adpll.dcoclkldo",
				     "481c5200.adpll.clkout",
				     "481c5200.adpll.clkoutldo";
	};

	adpll_audio_ck: adpll@230 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0x230 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c5230.adpll.dcoclkldo",
				     "481c5230.adpll.clkout",
				     "481c5230.adpll.clkoutldo";
	};

	adpll_usb_ck: adpll@260 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0x260 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c5260.adpll.dcoclkldo",
				     "481c5260.adpll.clkout",
				     "481c5260.adpll.clkoutldo";
	};

	adpll_ddr_ck: adpll@290 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0x290 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c5290.adpll.dcoclkldo",
				     "481c5290.adpll.clkout",
				     "481c5290.adpll.clkoutldo";
	};
};

&pllss_clocks {
	timer1_fck: timer1_fck@2e0 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
			  &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
		ti,bit-shift = <3>;
		reg = <0x2e0>;
	};

	timer2_fck: timer2_fck@2e0 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
			  &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
		ti,bit-shift = <6>;
		reg = <0x2e0>;
	};

	/* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&adpll_video0_ck 1
			  &adpll_video1_ck 1
			  &adpll_audio_ck 1>;
		ti,bit-shift = <1>;
		reg = <0x2e8>;
	};

	/* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
	cpsw_125mhz_gclk: cpsw_125mhz_gclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
	};

	sysclk18_ck: sysclk18_ck@2f0 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
		ti,bit-shift = <0>;
		reg = <0x02f0>;
	};
};

&scm_clocks {
	devosc_ck: devosc_ck@40 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
		ti,bit-shift = <21>;
		reg = <0x0040>;
	};

	/* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
	auxosc_ck: auxosc_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <22572900>;
	};

	/* Optional 32768Hz crystal or clock on RTCOSC pins */
	rtcosc_ck: rtcosc_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
	};

	/* Optional external clock on TCLKIN pin, set rate in baord dts file */
	tclkin_ck: tclkin_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	virt_20000000_ck: virt_20000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <20000000>;
	};

	virt_19200000_ck: virt_19200000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <19200000>;
	};

	mpu_ck: mpu_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <1000000000>;
	};
};

&prcm_clocks {
	osc_src_ck: osc_src_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&devosc_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	mpu_clksrc_ck: mpu_clksrc_ck@40 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&devosc_ck>, <&rtcdivider_ck>;
		ti,bit-shift = <0>;
		reg = <0x0040>;
	};

	/* Fixed divider clock 0.0016384 * devosc */
	rtcdivider_ck: rtcdivider_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&devosc_ck>;
		clock-mult = <128>;
		clock-div = <78125>;
	};

	/* L4_HS 220 MHz*/
	sysclk4_ck: sysclk4_ck {
		#clock-cells = <0>;
		compatible = "ti,fixed-factor-clock";
		clocks = <&adpll_l3_ck 1>;
		ti,clock-mult = <1>;
		ti,clock-div = <1>;
	};

	/* L4_FWCFG */
	sysclk5_ck: sysclk5_ck {
		#clock-cells = <0>;
		compatible = "ti,fixed-factor-clock";
		clocks = <&adpll_l3_ck 1>;
		ti,clock-mult = <1>;
		ti,clock-div = <2>;
	};

	/* L4_LS 110 MHz */
	sysclk6_ck: sysclk6_ck {
		#clock-cells = <0>;
		compatible = "ti,fixed-factor-clock";
		clocks = <&adpll_l3_ck 1>;
		ti,clock-mult = <1>;
		ti,clock-div = <2>;
	};

	sysclk8_ck: sysclk8_ck {
		#clock-cells = <0>;
		compatible = "ti,fixed-factor-clock";
		clocks = <&adpll_usb_ck 1>;
		ti,clock-mult = <1>;
		ti,clock-div = <1>;
	};

	sysclk10_ck: sysclk10_ck {
		compatible = "ti,divider-clock";
		reg = <0x324>;
		ti,max-div = <7>;
		#clock-cells = <0>;
		clocks = <&adpll_usb_ck 1>;
	};

	aud_clkin0_ck: aud_clkin0_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <20000000>;
	};

	aud_clkin1_ck: aud_clkin1_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <20000000>;
	};

	aud_clkin2_ck: aud_clkin2_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <20000000>;
	};
};

&prcm {
	default_cm: default_cm@500 {
		compatible = "ti,omap4-cm";
		reg = <0x500 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x500 0x100>;

		default_clkctrl: clk@0 {
			compatible = "ti,clkctrl";
			reg = <0x0 0x5c>;
			#clock-cells = <2>;
		};
	};

	alwon_cm: alwon_cm@1400 {
		compatible = "ti,omap4-cm";
		reg = <0x1400 0x300>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1400 0x300>;

		alwon_clkctrl: clk@0 {
			compatible = "ti,clkctrl";
			reg = <0x0 0x228>;
			#clock-cells = <2>;
		};
	};

	alwon_ethernet_cm: alwon_ethernet_cm@15d4 {
		compatible = "ti,omap4-cm";
		reg = <0x15d4 0x4>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x15d4 0x4>;

		alwon_ethernet_clkctrl: clk@0 {
			compatible = "ti,clkctrl";
			reg = <0 0x4>;
			#clock-cells = <2>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/dm814.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/dm814x.h>

/ {
	compatible = "ti,dm814";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		ethernet0 = &cpsw_emac0;
		ethernet1 = &cpsw_emac1;
		usb0 = &usb0;
		usb1 = &usb1;
		phy0 = &usb0_phy;
		phy1 = &usb1_phy;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "arm,cortex-a8";
			device_type = "cpu";
			reg = <0>;
		};
	};

	pmu {
		compatible = "arm,cortex-a8-pmu";
		interrupts = <3>;
	};

	/*
	 * The soc node represents the soc top level view. It is used for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap3-mpu";
			ti,hwmods = "mpu";
		};
	};

	ocp {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main";

		usb: usb@47400000 {
			compatible = "ti,am33xx-usb";
			reg = <0x47400000 0x1000>;
			ranges;
			#address-cells = <1>;
			#size-cells = <1>;
			ti,hwmods = "usb_otg_hs";

			usb0_phy: usb-phy@47401300 {
				compatible = "ti,am335x-usb-phy";
				reg = <0x47401300 0x100>;
				reg-names = "phy";
				ti,ctrl_mod = <&usb_ctrl_mod>;
				#phy-cells = <0>;
			};

			usb0: usb@47401000 {
				compatible = "ti,musb-am33xx";
				reg = <0x47401400 0x400
				       0x47401000 0x200>;
				reg-names = "mc", "control";

				interrupts = <18>;
				interrupt-names = "mc";
				dr_mode = "otg";
				mentor,multipoint = <1>;
				mentor,num-eps = <16>;
				mentor,ram-bits = <12>;
				mentor,power = <500>;
				phys = <&usb0_phy>;

				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
					&cppi41dma  2 0 &cppi41dma  3 0
					&cppi41dma  4 0 &cppi41dma  5 0
					&cppi41dma  6 0 &cppi41dma  7 0
					&cppi41dma  8 0 &cppi41dma  9 0
					&cppi41dma 10 0 &cppi41dma 11 0
					&cppi41dma 12 0 &cppi41dma 13 0
					&cppi41dma 14 0 &cppi41dma  0 1
					&cppi41dma  1 1 &cppi41dma  2 1
					&cppi41dma  3 1 &cppi41dma  4 1
					&cppi41dma  5 1 &cppi41dma  6 1
					&cppi41dma  7 1 &cppi41dma  8 1
					&cppi41dma  9 1 &cppi41dma 10 1
					&cppi41dma 11 1 &cppi41dma 12 1
					&cppi41dma 13 1 &cppi41dma 14 1>;
				dma-names =
					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
					"rx14", "rx15",
					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
					"tx14", "tx15";
			};

			usb1: usb@47401800 {
				compatible = "ti,musb-am33xx";
				reg = <0x47401c00 0x400
					0x47401800 0x200>;
				reg-names = "mc", "control";
				interrupts = <19>;
				interrupt-names = "mc";
				dr_mode = "otg";
				mentor,multipoint = <1>;
				mentor,num-eps = <16>;
				mentor,ram-bits = <12>;
				mentor,power = <500>;
				phys = <&usb1_phy>;

				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
					&cppi41dma 17 0 &cppi41dma 18 0
					&cppi41dma 19 0 &cppi41dma 20 0
					&cppi41dma 21 0 &cppi41dma 22 0
					&cppi41dma 23 0 &cppi41dma 24 0
					&cppi41dma 25 0 &cppi41dma 26 0
					&cppi41dma 27 0 &cppi41dma 28 0
					&cppi41dma 29 0 &cppi41dma 15 1
					&cppi41dma 16 1 &cppi41dma 17 1
					&cppi41dma 18 1 &cppi41dma 19 1
					&cppi41dma 20 1 &cppi41dma 21 1
					&cppi41dma 22 1 &cppi41dma 23 1
					&cppi41dma 24 1 &cppi41dma 25 1
					&cppi41dma 26 1 &cppi41dma 27 1
					&cppi41dma 28 1 &cppi41dma 29 1>;
				dma-names =
					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
					"rx14", "rx15",
					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
					"tx14", "tx15";
			};

			cppi41dma: dma-controller@47402000 {
				compatible = "ti,am3359-cppi41";
				reg =  <0x47400000 0x1000
					0x47402000 0x1000
					0x47403000 0x1000
					0x47404000 0x4000>;
				reg-names = "glue", "controller", "scheduler", "queuemgr";
				interrupts = <17>;
				interrupt-names = "glue";
				#dma-cells = <2>;
				/* For backwards compatibility: */
				#dma-channels = <30>;
				dma-channels = <30>;
				#dma-requests = <256>;
				dma-requests = <256>;
			};
		};

		/*
		 * See TRM "Table 1-317. L4LS Instance Summary" for hints.
		 * It shows the module target agent registers though, so the
		 * actual device is typically 0x1000 before the target agent
		 * except in cases where the module is larger than 0x1000.
		 */
		l4ls: l4ls@48000000 {
			compatible = "ti,dm814-l4ls", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x48000000 0x2000000>;

			i2c1: i2c@28000 {
				compatible = "ti,omap4-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				ti,hwmods = "i2c1";
				reg = <0x28000 0x1000>;
				interrupts = <70>;
			};

			elm: elm@80000 {
				compatible = "ti,814-elm";
				ti,hwmods = "elm";
				reg = <0x80000 0x2000>;
				interrupts = <4>;
			};

			gpio1: gpio@32000 {
				compatible = "ti,omap4-gpio";
				ti,hwmods = "gpio1";
				ti,gpio-always-on;
				reg = <0x32000 0x2000>;
				interrupts = <96>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@4c000 {
				compatible = "ti,omap4-gpio";
				ti,hwmods = "gpio2";
				ti,gpio-always-on;
				reg = <0x4c000 0x2000>;
				interrupts = <98>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@1ac000 {
				compatible = "ti,omap4-gpio";
				ti,hwmods = "gpio3";
				ti,gpio-always-on;
				reg = <0x1ac000 0x2000>;
				interrupts = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@1ae000 {
				compatible = "ti,omap4-gpio";
				ti,hwmods = "gpio4";
				ti,gpio-always-on;
				reg = <0x1ae000 0x2000>;
				interrupts = <62>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			i2c2: i2c@2a000 {
				compatible = "ti,omap4-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				ti,hwmods = "i2c2";
				reg = <0x2a000 0x1000>;
				interrupts = <71>;
			};

			mcspi1: spi@30000 {
				compatible = "ti,omap4-mcspi";
				reg = <0x30000 0x1000>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <65>;
				ti,spi-num-cs = <4>;
				ti,hwmods = "mcspi1";
				dmas = <&edma 16 0 &edma 17 0
					&edma 18 0 &edma 19 0
					&edma 20 0 &edma 21 0
					&edma 22 0 &edma 23 0>;

				dma-names = "tx0", "rx0", "tx1", "rx1",
					"tx2", "rx2", "tx3", "rx3";
			};

			mcspi2: spi@1a0000 {
				compatible = "ti,omap4-mcspi";
				reg = <0x1a0000 0x1000>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <125>;
				ti,spi-num-cs = <4>;
				ti,hwmods = "mcspi2";
				dmas = <&edma 42 0 &edma 43 0
					&edma 44 0 &edma 45 0>;
				dma-names = "tx0", "rx0", "tx1", "rx1";
			};

			/* Board must configure dmas with edma_xbar for EDMA */
			mcspi3: spi@1a2000 {
				compatible = "ti,omap4-mcspi";
				reg = <0x1a2000 0x1000>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <126>;
				ti,spi-num-cs = <4>;
				ti,hwmods = "mcspi3";
			};

			mcspi4: spi@1a4000 {
				compatible = "ti,omap4-mcspi";
				reg = <0x1a4000 0x1000>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <127>;
				ti,spi-num-cs = <4>;
				ti,hwmods = "mcspi4";
			};

			timer1_target: target-module@2e000 {
				compatible = "ti,sysc-omap4-timer", "ti,sysc";
				reg = <0x2e000 0x4>,
				      <0x2e010 0x4>;
				reg-names = "rev", "sysc";
				ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
				ti,sysc-sidle = <SYSC_IDLE_FORCE>,
						<SYSC_IDLE_NO>,
						<SYSC_IDLE_SMART>,
						<SYSC_IDLE_SMART_WKUP>;
				clocks = <&timer1_fck>;
				clock-names = "fck";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x2e000 0x1000>;

				timer1: timer@0 {
					compatible = "ti,am335x-timer-1ms";
					reg = <0x0 0x400>;
					interrupts = <67>;
					ti,timer-alwon;
					clocks = <&timer1_fck>;
					clock-names = "fck";
				};
			};

			uart1: uart@20000 {
				compatible = "ti,am3352-uart", "ti,omap3-uart";
				ti,hwmods = "uart1";
				reg = <0x20000 0x2000>;
				clock-frequency = <48000000>;
				interrupts = <72>;
				dmas = <&edma 26 0 &edma 27 0>;
				dma-names = "tx", "rx";
			};

			uart2: uart@22000 {
				compatible = "ti,am3352-uart", "ti,omap3-uart";
				ti,hwmods = "uart2";
				reg = <0x22000 0x2000>;
				clock-frequency = <48000000>;
				interrupts = <73>;
				dmas = <&edma 28 0 &edma 29 0>;
				dma-names = "tx", "rx";
			};

			uart3: uart@24000 {
				compatible = "ti,am3352-uart", "ti,omap3-uart";
				ti,hwmods = "uart3";
				reg = <0x24000 0x2000>;
				clock-frequency = <48000000>;
				interrupts = <74>;
				dmas = <&edma 30 0 &edma 31 0>;
				dma-names = "tx", "rx";
			};

			timer2_target: target-module@40000 {
				compatible = "ti,sysc-omap4-timer", "ti,sysc";
				reg = <0x40000 0x4>,
				      <0x40010 0x4>;
				reg-names = "rev", "sysc";
				ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
				ti,sysc-sidle = <SYSC_IDLE_FORCE>,
						<SYSC_IDLE_NO>,
						<SYSC_IDLE_SMART>,
						<SYSC_IDLE_SMART_WKUP>;
				clocks = <&timer2_fck>;
				clock-names = "fck";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x40000 0x1000>;

				timer2: timer@0 {
					compatible = "ti,dm814-timer";
					reg = <0 0x1000>;
					interrupts = <68>;
					clocks = <&timer2_fck>;
					clock-names = "fck";
				};
			};

			timer3: timer@42000 {
				compatible = "ti,dm814-timer";
				reg = <0x42000 0x2000>;
				interrupts = <69>;
				ti,hwmods = "timer3";
			};

			mmc1: mmc@60000 {
				compatible = "ti,omap4-hsmmc";
				ti,hwmods = "mmc1";
				dmas = <&edma 24 0
					&edma 25 0>;
				dma-names = "tx", "rx";
				interrupts = <64>;
				interrupt-parent = <&intc>;
				reg = <0x60000 0x1000>;
			};

			rtc: rtc@c0000 {
				compatible = "ti,am3352-rtc", "ti,da830-rtc";
				reg = <0xc0000 0x1000>;
				interrupts = <75 76>;
				ti,hwmods = "rtc";
			};

			mmc2: mmc@1d8000 {
				compatible = "ti,omap4-hsmmc";
				ti,hwmods = "mmc2";
				dmas = <&edma 2 0
					&edma 3 0>;
				dma-names = "tx", "rx";
				interrupts = <28>;
				interrupt-parent = <&intc>;
				reg = <0x1d8000 0x1000>;
			};

			control: control@140000 {
				compatible = "ti,dm814-scm", "simple-bus";
				reg = <0x140000 0x20000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x140000 0x20000>;

				scm_conf: scm_conf@0 {
					compatible = "syscon", "simple-bus";
					reg = <0x0 0x800>;
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0 0 0x800>;

					phy_gmii_sel: phy-gmii-sel {
						compatible = "ti,dm814-phy-gmii-sel";
						reg = <0x650 0x4>;
						#phy-cells = <1>;
					};

					scm_clocks: clocks {
						#address-cells = <1>;
						#size-cells = <0>;
					};

					scm_clockdomains: clockdomains {
					};
				};

				usb_ctrl_mod: control@620 {
					compatible = "ti,am335x-usb-ctrl-module";
					reg = <0x620 0x10
						0x648 0x4>;
					reg-names = "phy_ctrl", "wakeup";
				};

				edma_xbar: dma-router@f90 {
					compatible = "ti,am335x-edma-crossbar";
					reg = <0xf90 0x40>;
					#dma-cells = <3>;
					dma-requests = <32>;
					dma-masters = <&edma>;
				};

				/*
				 * Note that silicon revision 2.1 and older
				 * require input enabled (bit 18 set) for all
				 * 3.3V I/Os to avoid cumulative hardware damage.
				 * For more info, see errata advisory 2.1.87.
				 * We leave bit 18 out of function-mask and rely
				 * on the bootloader for it.
				 */
				pincntl: pinmux@800 {
					compatible = "pinctrl-single";
					reg = <0x800 0x438>;
					#address-cells = <1>;
					#size-cells = <0>;
					#pinctrl-cells = <1>;
					pinctrl-single,register-width = <32>;
					pinctrl-single,function-mask = <0x307ff>;
				};

				usb1_phy: usb-phy@1b00 {
					compatible = "ti,am335x-usb-phy";
					reg = <0x1b00 0x100>;
					reg-names = "phy";
					ti,ctrl_mod = <&usb_ctrl_mod>;
					#phy-cells = <0>;
				};
			};

			prcm: prcm@180000 {
				compatible = "ti,dm814-prcm", "simple-bus";
				reg = <0x180000 0x2000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x180000 0x2000>;

				prcm_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};

				prcm_clockdomains: clockdomains {
				};
			};

			/* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */
			pllss: pllss@1c5000 {
				compatible = "ti,dm814-pllss", "simple-bus";
				reg = <0x1c5000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x1c5000 0x1000>;

				pllss_clocks: clocks {
					#address-cells = <1>;
					#size-cells = <0>;
				};

				pllss_clockdomains: clockdomains {
				};
			};

			wdt1: wdt@1c7000 {
				compatible = "ti,omap3-wdt";
				ti,hwmods = "wd_timer";
				reg = <0x1c7000 0x1000>;
				interrupts = <91>;
			};
		};

		intc: interrupt-controller@48200000 {
			compatible = "ti,dm814-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x48200000 0x1000>;
		};

		/* Board must configure evtmux with edma_xbar for EDMA */
		mmc3: mmc@47810000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc3";
			interrupts = <29>;
			interrupt-parent = <&intc>;
			reg = <0x47810000 0x1000>;
		};

		target-module@49000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49000000 0x4>;
			reg-names = "rev";
			clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49000000 0x10000>;

			edma: dma@0 {
				compatible = "ti,edma3-tpcc";
				reg = <0 0x10000>;
				reg-names = "edma3_cc";
				interrupts = <12 13 14>;
				interrupt-names = "edma3_ccint", "edma3_mperr",
						  "edma3_ccerrint";
				dma-requests = <64>;
				#dma-cells = <2>;

				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
					   <&edma_tptc2 3>, <&edma_tptc3 0>;

				ti,edma-memcpy-channels = <20 21>;
			};
		};

		target-module@49800000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49800000 0x4>,
			      <0x49800010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49800000 0x100000>;

			edma_tptc0: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <112>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@49900000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49900000 0x4>,
			      <0x49900010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49900000 0x100000>;

			edma_tptc1: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <113>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@49a00000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49a00000 0x4>,
			      <0x49a00010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49a00000 0x100000>;

			edma_tptc2: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <114>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@49b00000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49b00000 0x4>,
			      <0x49b00010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49b00000 0x100000>;

			edma_tptc3: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <115>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		/* See TRM "Table 1-318. L4HS Instance Summary" */
		l4hs: l4hs@4a000000 {
			compatible = "ti,dm814-l4hs", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x4a000000 0x1b4040>;

			target-module@100000 {
				compatible = "ti,sysc-omap4-simple", "ti,sysc";
				reg = <0x100900 0x4>,
				      <0x100908 0x4>,
				      <0x100904 0x4>;
				reg-names = "rev", "sysc", "syss";
				ti,sysc-mask = <0>;
				ti,sysc-midle = <SYSC_IDLE_FORCE>,
						<SYSC_IDLE_NO>;
				ti,sysc-sidle = <SYSC_IDLE_FORCE>,
						<SYSC_IDLE_NO>;
				ti,syss-mask = <1>;
				clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
				clock-names = "fck";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x100000 0x8000>;

				mac: ethernet@0 {
					compatible = "ti,cpsw";
					clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
					clock-names = "fck", "cpts";
					cpdma_channels = <8>;
					ale_entries = <1024>;
					bd_ram_size = <0x2000>;
					mac_control = <0x20>;
					slaves = <2>;
					active_slave = <0>;
					cpts_clock_mult = <0x80000000>;
					cpts_clock_shift = <29>;
					reg = <0 0x800>,
					      <0x900 0x100>;
					#address-cells = <1>;
					#size-cells = <1>;
					/*
					* c0_rx_thresh_pend
					* c0_rx_pend
					* c0_tx_pend
					* c0_misc_pend
					*/
					interrupts = <40 41 42 43>;
					ranges = <0 0 0x8000>;
					syscon = <&scm_conf>;

					davinci_mdio: mdio@800 {
						compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
						clocks = <&cpsw_125mhz_gclk>;
						clock-names = "fck";
						#address-cells = <1>;
						#size-cells = <0>;
						bus_freq = <1000000>;
						reg = <0x800 0x100>;
					};

					cpsw_emac0: slave@200 {
						/* Filled in by U-Boot */
						mac-address = [ 00 00 00 00 00 00 ];
						phys = <&phy_gmii_sel 1>;
					};

					cpsw_emac1: slave@300 {
						/* Filled in by U-Boot */
						mac-address = [ 00 00 00 00 00 00 ];
						phys = <&phy_gmii_sel 2>;
					};
				};
			};
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,am3352-gpmc";
			ti,hwmods = "gpmc";
			ti,no-idle-on-init;
			reg = <0x50000000 0x2000>;
			interrupts = <100>;
			gpmc,num-cs = <7>;
			gpmc,num-waitpins = <2>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};
	};
};

#include "dm814x-clocks.dtsi"

/* Preferred always-on timer for clocksource */
&timer1_target {
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&timer1_fck>;
		assigned-clock-parents = <&devosc_ck>;
	};
};

/* Preferred timer for clockevent */
&timer2_target {
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&timer2_fck>;
		assigned-clock-parents = <&devosc_ck>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;

#include "dm816x.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "DM8168 EVM";
	compatible = "ti,dm8168-evm", "ti,dm8168", "ti,dm816";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000	/* 1 GB */
		       0xc0000000 0x40000000>;	/* 1 GB */
	};

	/* FDC6331L controlled by SD_POW pin */
	vmmcsd_fixed: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "vmmcsd_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	sata_refclk: fixedclock0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};
};

&dm816x_pinmux {
	mcspi1_pins: pinmux_mcspi1_pins {
		pinctrl-single,pins = <
			DM816X_IOPAD(0x0a94, MUX_MODE0)			/* SPI_SCLK */
			DM816X_IOPAD(0x0a98, MUX_MODE0)			/* SPI_SCS0 */
			DM816X_IOPAD(0x0aa8, MUX_MODE0)			/* SPI_D0 */
			DM816X_IOPAD(0x0aac, MUX_MODE0)			/* SPI_D1 */
		>;
	};

	mmc_pins: pinmux_mmc_pins {
		pinctrl-single,pins = <
			DM816X_IOPAD(0x0a70, MUX_MODE0)			/* SD_POW */
			DM816X_IOPAD(0x0a74, MUX_MODE0)			/* SD_CLK */
			DM816X_IOPAD(0x0a78, MUX_MODE0)			/* SD_CMD */
			DM816X_IOPAD(0x0a7C, MUX_MODE0)			/* SD_DAT0 */
			DM816X_IOPAD(0x0a80, MUX_MODE0)			/* SD_DAT1 */
			DM816X_IOPAD(0x0a84, MUX_MODE0)			/* SD_DAT2 */
			DM816X_IOPAD(0x0a88, MUX_MODE0)			/* SD_DAT2 */
			DM816X_IOPAD(0x0a8c, MUX_MODE2)			/* GP1[7] */
			DM816X_IOPAD(0x0a90, MUX_MODE2)			/* GP1[8] */
		>;
	};

	usb0_pins: pinmux_usb0_pins {
		pinctrl-single,pins = <
			DM816X_IOPAD(0x0d04, MUX_MODE0)			/* USB0_DRVVBUS */
		>;
	};

	usb1_pins: pinmux_usb1_pins {
		pinctrl-single,pins = <
			DM816X_IOPAD(0x0d08, MUX_MODE0)			/* USB1_DRVVBUS */
		>;
	};

	nandflash_pins: nandflash_pins {
		pinctrl-single,pins = <
			DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0)		/* PINCTRL207 GPMC_CS0*/
			DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0)		/* PINCTRL217 GPMC_ADV_ALE */
			DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0)	/* PINCTRL214 GPMC_OE_RE */
			DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0)		/* PINCTRL215 GPMC_BE0_CLE */
			DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0)		/* PINCTRL213 GPMC_WE */
			DM816X_IOPAD(0x0b6c, MUX_MODE0)				/* PINCTRL220 GPMC_WAIT */
			DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0)		/* PINCTRL250 GPMC_CLK */
			DM816X_IOPAD(0x0ba4, MUX_MODE0)				/* PINCTRL234 GPMC_D0 */
			DM816X_IOPAD(0x0ba8, MUX_MODE0)				/* PINCTRL234 GPMC_D1 */
			DM816X_IOPAD(0x0bac, MUX_MODE0)				/* PINCTRL234 GPMC_D2 */
			DM816X_IOPAD(0x0bb0, MUX_MODE0)				/* PINCTRL234 GPMC_D3 */
			DM816X_IOPAD(0x0bb4, MUX_MODE0)				/* PINCTRL234 GPMC_D4 */
			DM816X_IOPAD(0x0bb8, MUX_MODE0)				/* PINCTRL234 GPMC_D5 */
			DM816X_IOPAD(0x0bbc, MUX_MODE0)				/* PINCTRL234 GPMC_D6 */
			DM816X_IOPAD(0x0bc0, MUX_MODE0)				/* PINCTRL234 GPMC_D7 */
			DM816X_IOPAD(0x0bc4, MUX_MODE0)				/* PINCTRL234 GPMC_D8 */
			DM816X_IOPAD(0x0bc8, MUX_MODE0)				/* PINCTRL234 GPMC_D9 */
			DM816X_IOPAD(0x0bcc, MUX_MODE0)				/* PINCTRL234 GPMC_D10 */
			DM816X_IOPAD(0x0bd0, MUX_MODE0)				/* PINCTRL234 GPMC_D11 */
			DM816X_IOPAD(0x0bd4, MUX_MODE0)				/* PINCTRL234 GPMC_D12 */
			DM816X_IOPAD(0x0bd8, MUX_MODE0)				/* PINCTRL234 GPMC_D13 */
			DM816X_IOPAD(0x0bdc, MUX_MODE0)				/* PINCTRL234 GPMC_D14 */
			DM816X_IOPAD(0x0be0, MUX_MODE0)				/* PINCTRL234 GPMC_D15 */
		>;
	};
};

&i2c1 {
	extgpio0: pcf8575@20 {
		compatible = "nxp,pcf8575";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&i2c2 {
	extgpio1: pcf8575@20 {
		compatible = "nxp,pcf8575";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&gpmc {
	ranges = <0 0 0x04000000 0x01000000>;	/* CS0: 16MB for NAND */
	pinctrl-names = "default";
	pinctrl-0 = <&nandflash_pins>;

	nand@0,0 {
		compatible = "ti,omap2-nand";
		linux,mtd-name = "micron,mt29f2g16aadwp";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>; /* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
		#address-cells = <1>;
		#size-cells = <1>;
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <44>;
		gpmc,cs-wr-off-ns = <44>;
		gpmc,adv-on-ns = <6>;
		gpmc,adv-rd-off-ns = <34>;
		gpmc,adv-wr-off-ns = <44>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <40>;
		gpmc,oe-on-ns = <0>;
		gpmc,oe-off-ns = <54>;
		gpmc,access-ns = <64>;
		gpmc,rd-cycle-ns = <82>;
		gpmc,wr-cycle-ns = <82>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-access-ns = <40>;
		gpmc,wr-data-mux-bus-ns = <0>;
		partition@0 {
			label = "X-Loader";
			reg = <0 0x80000>;
		};
		partition@80000 {
			label = "U-Boot";
			reg = <0x80000 0x1c0000>;
		};
		partition@1c0000 {
			label = "Environment";
			reg = <0x240000 0x40000>;
		};
		partition@280000 {
			label = "Kernel";
			reg = <0x280000 0x500000>;
		};
		partition@780000 {
			label = "Filesystem";
			reg = <0x780000 0xf880000>;
		};
	};
};

&mcspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi1_pins>;

	flash@0 {
		compatible = "w25x32";
		spi-max-frequency = <48000000>;
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc_pins>;
	vmmc-supply = <&vmmcsd_fixed>;
	bus-width = <4>;
	cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
};

/* At least dm8168-evm rev c won't support multipoint, later may */
&usb0 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb0_pins>;
	mentor,multipoint = <0>;
};

&usb1 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb1_pins>;
	mentor,multipoint = <0>;
};

&sata {
	clocks = <&sysclk5_ck>, <&sata_refclk>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only

&scrm {
	main_fapll: main_fapll {
		#clock-cells = <1>;
		compatible = "ti,dm816-fapll-clock";
		reg = <0x400 0x40>;
		clocks = <&sys_clkin_ck &sys_clkin_ck>;
		clock-indices = <1>, <2>, <3>, <4>, <5>,
				<6>, <7>;
		clock-output-names = "main_pll_clk1",
				     "main_pll_clk2",
				     "main_pll_clk3",
				     "main_pll_clk4",
				     "main_pll_clk5",
				     "main_pll_clk6",
				     "main_pll_clk7";
	};

	ddr_fapll: ddr_fapll {
		#clock-cells = <1>;
		compatible = "ti,dm816-fapll-clock";
		reg = <0x440 0x30>;
		clocks = <&sys_clkin_ck &sys_clkin_ck>;
		clock-indices = <1>, <2>, <3>, <4>;
		clock-output-names = "ddr_pll_clk1",
				     "ddr_pll_clk2",
				     "ddr_pll_clk3",
				     "ddr_pll_clk4";
	};

	video_fapll: video_fapll {
		#clock-cells = <1>;
		compatible = "ti,dm816-fapll-clock";
		reg = <0x470 0x30>;
		clocks = <&sys_clkin_ck &sys_clkin_ck>;
		clock-indices = <1>, <2>, <3>;
		clock-output-names = "video_pll_clk1",
				     "video_pll_clk2",
				     "video_pll_clk3";
	};

	audio_fapll: audio_fapll {
		#clock-cells = <1>;
		compatible = "ti,dm816-fapll-clock";
		reg = <0x4a0 0x30>;
		clocks = <&main_fapll 7>, < &sys_clkin_ck>;
		clock-indices = <1>, <2>, <3>, <4>, <5>;
		clock-output-names = "audio_pll_clk1",
				     "audio_pll_clk2",
				     "audio_pll_clk3",
				     "audio_pll_clk4",
				     "audio_pll_clk5";
	};
};

&scrm_clocks {
	secure_32k_ck: secure_32k_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
	};

	sys_32k_ck: sys_32k_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
	};

	tclkin_ck: tclkin_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
	};

	sys_clkin_ck: sys_clkin_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <27000000>;
	};
};

/* 0x48180000 */
&prcm_clocks {
	clkout_pre_ck: clkout_pre_ck@100 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
			  &audio_fapll 1>;
		reg = <0x100>;
	};

	clkout_div_ck: clkout_div_ck@100 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&clkout_pre_ck>;
		ti,bit-shift = <3>;
		ti,max-div = <8>;
		reg = <0x100>;
	};

	clkout_ck: clkout_ck@100 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&clkout_div_ck>;
		ti,bit-shift = <7>;
		reg = <0x100>;
	};

	/* CM_DPLL clocks p1795 */
	sysclk1_ck: sysclk1_ck@300 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&main_fapll 1>;
		ti,max-div = <7>;
		reg = <0x0300>;
	};

	sysclk2_ck: sysclk2_ck@304 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&main_fapll 2>;
		ti,max-div = <7>;
		reg = <0x0304>;
	};

	sysclk3_ck: sysclk3_ck@308 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&main_fapll 3>;
		ti,max-div = <7>;
		reg = <0x0308>;
	};

	sysclk4_ck: sysclk4_ck@30c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&main_fapll 4>;
		ti,max-div = <1>;
		reg = <0x030c>;
	};

	sysclk5_ck: sysclk5_ck@310 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&sysclk4_ck>;
		ti,max-div = <1>;
		reg = <0x0310>;
	};

	sysclk6_ck: sysclk6_ck@314 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&main_fapll 4>;
		ti,dividers = <2>, <4>;
		reg = <0x0314>;
	};

	sysclk10_ck: sysclk10_ck@324 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&ddr_fapll 2>;
		ti,max-div = <7>;
		reg = <0x0324>;
	};

	sysclk24_ck: sysclk24_ck@3b4 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&main_fapll 5>;
		ti,max-div = <7>;
		reg = <0x03b4>;
	};

	mpu_ck: mpu_ck@15dc {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sysclk2_ck>;
		ti,bit-shift = <1>;
                reg = <0x15dc>;
	};

	audio_pll_a_ck: audio_pll_a_ck@35c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&audio_fapll 1>;
		ti,max-div = <7>;
		reg = <0x035c>;
	};

	sysclk18_ck: sysclk18_ck@378 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
		reg = <0x0378>;
	};

	timer1_fck: timer1_fck@390 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
		reg = <0x0390>;
	};

	timer2_fck: timer2_fck@394 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
		reg = <0x0394>;
	};

	timer3_fck: timer3_fck@398 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
		reg = <0x0398>;
	};

	timer4_fck: timer4_fck@39c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
		reg = <0x039c>;
	};

	timer5_fck: timer5_fck@3a0 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
		reg = <0x03a0>;
	};

	timer6_fck: timer6_fck@3a4 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
		reg = <0x03a4>;
	};

	timer7_fck: timer7_fck@3a8 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
		reg = <0x03a8>;
	};
};

&prcm {
	default_cm: default_cm@500 {
		compatible = "ti,omap4-cm";
		reg = <0x500 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x500 0x100>;

		default_clkctrl: clk@0 {
			compatible = "ti,clkctrl";
			reg = <0x0 0x5c>;
			#clock-cells = <2>;
		};
	};

	alwon_cm: alwon_cm@1400 {
		compatible = "ti,omap4-cm";
		reg = <0x1400 0x300>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1400 0x300>;

		alwon_clkctrl: clk@0 {
			compatible = "ti,clkctrl";
			reg = <0x0 0x208>;
			#clock-cells = <2>;
		};
	};
};