code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/samsung_uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Greg Kroah-Hartman <gregkh@linuxfoundation.org>

description: |+
  Each Samsung UART should have an alias correctly numbered in the "aliases"
  node, according to serialN format, where N is the port number (non-negative
  decimal integer) as specified by User's Manual of respective SoC.

properties:
  compatible:
    oneOf:
      - items:
          - const: samsung,exynosautov9-uart
          - const: samsung,exynos850-uart
      - enum:
          - apple,s5l-uart
          - axis,artpec8-uart
          - samsung,s3c2410-uart
          - samsung,s3c2412-uart
          - samsung,s3c2440-uart
          - samsung,s3c6400-uart
          - samsung,s5pv210-uart
          - samsung,exynos4210-uart
          - samsung,exynos5433-uart
          - samsung,exynos850-uart

  reg:
    maxItems: 1

  reg-io-width:
    description: |
      The size (in bytes) of the IO accesses that should be performed
      on the device.
    enum: [ 1, 4 ]

  clocks:
    minItems: 2
    maxItems: 5

  clock-names:
    description: N = 0 is allowed for SoCs without internal baud clock mux.
    minItems: 2
    items:
      - const: uart
      - pattern: '^clk_uart_baud[0-3]$'
      - pattern: '^clk_uart_baud[0-3]$'
      - pattern: '^clk_uart_baud[0-3]$'
      - pattern: '^clk_uart_baud[0-3]$'

  dmas:
    items:
      - description: DMA controller phandle and request line for RX
      - description: DMA controller phandle and request line for TX

  dma-names:
    items:
      - const: rx
      - const: tx

  interrupts:
    description: RX interrupt and optionally TX interrupt.
    minItems: 1
    maxItems: 2

  power-domains:
    maxItems: 1

  samsung,uart-fifosize:
    description: The fifo size supported by the UART channel.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [16, 64, 256]

required:
  - compatible
  - clocks
  - clock-names
  - interrupts
  - reg

unevaluatedProperties: false

allOf:
  - $ref: serial.yaml#

  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,s3c2410-uart
              - samsung,s5pv210-uart
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 3
        clock-names:
          minItems: 2
          items:
            - const: uart
            - pattern: '^clk_uart_baud[0-1]$'
            - pattern: '^clk_uart_baud[0-1]$'

  - if:
      properties:
        compatible:
          contains:
            enum:
              - apple,s5l-uart
              - axis,artpec8-uart
              - samsung,exynos4210-uart
              - samsung,exynos5433-uart
    then:
      properties:
        clocks:
          maxItems: 2
        clock-names:
          items:
            - const: uart
            - const: clk_uart_baud0

examples:
  - |
    #include <dt-bindings/clock/samsung,s3c64xx-clock.h>

    uart0: serial@7f005000 {
        compatible = "samsung,s3c6400-uart";
        reg = <0x7f005000 0x100>;
        interrupt-parent = <&vic1>;
        interrupts = <5>;
        clock-names = "uart", "clk_uart_baud2",
                      "clk_uart_baud3";
        clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
                 <&clocks SCLK_UART>;
        samsung,uart-fifosize = <16>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/serial.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Serial Interface Generic DT Bindings

maintainers:
  - Rob Herring <robh@kernel.org>
  - Greg Kroah-Hartman <gregkh@linuxfoundation.org>

description:
  This document lists a set of generic properties for describing UARTs in a
  device tree.  Whether these properties apply to a particular device depends
  on the DT bindings for the actual device.

  Each enabled UART may have an optional "serialN" alias in the "aliases" node,
  where N is the port number (non-negative decimal integer) as printed on the
  label next to the physical port.

properties:
  $nodename:
    pattern: "^serial(@.*)?$"

  label: true

  cts-gpios:
    maxItems: 1
    description:
      Must contain a GPIO specifier, referring to the GPIO pin to be used as
      the UART's CTS line.

  dcd-gpios:
    maxItems: 1
    description:
      Must contain a GPIO specifier, referring to the GPIO pin to be used as
      the UART's DCD line.

  dsr-gpios:
    maxItems: 1
    description:
      Must contain a GPIO specifier, referring to the GPIO pin to be used as
      the UART's DSR line.

  dtr-gpios:
    maxItems: 1
    description:
      Must contain a GPIO specifier, referring to the GPIO pin to be used as
      the UART's DTR line.

  rng-gpios:
    maxItems: 1
    description:
      Must contain a GPIO specifier, referring to the GPIO pin to be used as
      the UART's RNG line.

  rts-gpios:
    maxItems: 1
    description:
      Must contain a GPIO specifier, referring to the GPIO pin to be used as
      the UART's RTS line.

  uart-has-rtscts:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      The presence of this property indicates that the UART has dedicated lines
      for RTS/CTS hardware flow control, and that they are available for use
      (wired and enabled by pinmux configuration).  This depends on both the
      UART hardware and the board wiring.

  rx-tx-swap:
    type: boolean
    description: RX and TX pins are swapped.

  cts-rts-swap:
    type: boolean
    description: CTS and RTS pins are swapped.

  rx-threshold:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      RX FIFO threshold configuration (in bytes).

  tx-threshold:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      TX FIFO threshold configuration (in bytes).

if:
  required:
    - uart-has-rtscts
then:
  properties:
    cts-gpios: false
    rts-gpios: false

patternProperties:
  ".*":
    if:
      type: object
    then:
      description:
        Serial attached devices shall be a child node of the host UART device
        the slave device is attached to. It is expected that the attached
        device is the only child node of the UART device. The slave device node
        name shall reflect the generic type of device for the node.

      properties:
        compatible:
          description:
            Compatible of the device connected to the serial port.

        max-speed:
          $ref: /schemas/types.yaml#/definitions/uint32
          description:
            The maximum baud rate the device operates at.
            This should only be present if the maximum is less than the slave
            device can support.  For example, a particular board has some
            signal quality issue or the host processor can't support higher
            baud rates.

        current-speed:
          $ref: /schemas/types.yaml#/definitions/uint32
          description: |
            The current baud rate the device operates at.
            This should only be present in case a driver has no chance to know
            the baud rate of the slave device.
            Examples:
              * device supports auto-baud
              * the rate is setup by a bootloader and there is no way to reset
                the device
              * device baud rate is configured by its firmware but there is no
                way to request the actual settings

      required:
        - compatible

additionalProperties: true

examples:
  - |
    serial@1234 {
            compatible = "ns16550a";
            reg = <0x1234 0x20>;
            interrupts = <1>;

            bluetooth {
                    compatible = "brcm,bcm4330-bt";
                    interrupt-parent = <&gpio>;
                    interrupts = <10>;
            };
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive asynchronous serial interface (UART)

maintainers:
  - Pragnesh Patel <pragnesh.patel@sifive.com>
  - Paul Walmsley  <paul.walmsley@sifive.com>
  - Palmer Dabbelt <palmer@sifive.com>

allOf:
  - $ref: serial.yaml#

properties:
  compatible:
    items:
      - enum:
          - sifive,fu540-c000-uart
          - sifive,fu740-c000-uart
          - canaan,k210-uarths
      - const: sifive,uart0

    description:
      Should be something similar to "sifive,<chip>-uart"
      for the UART as integrated on a particular chip,
      and "sifive,uart<version>" for the general UART IP
      block programming model.

      UART HDL that corresponds to the IP block version
      numbers can be found here -

      https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
      #include <dt-bindings/clock/sifive-fu540-prci.h>
      serial@10010000 {
        compatible = "sifive,fu540-c000-uart", "sifive,uart0";
        interrupt-parent = <&plic0>;
        interrupts = <80>;
        reg = <0x10010000 0x1000>;
        clocks = <&prci FU540_PRCI_CLK_TLCLK>;
      };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare ABP UART

maintainers:
  - Rob Herring <robh@kernel.org>

allOf:
  - $ref: serial.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,r9a06g032-uart
              - renesas,r9a06g033-uart
          - const: renesas,rzn1-uart
      - items:
          - enum:
              - rockchip,px30-uart
              - rockchip,rk1808-uart
              - rockchip,rk3036-uart
              - rockchip,rk3066-uart
              - rockchip,rk3128-uart
              - rockchip,rk3188-uart
              - rockchip,rk3288-uart
              - rockchip,rk3308-uart
              - rockchip,rk3328-uart
              - rockchip,rk3368-uart
              - rockchip,rk3399-uart
              - rockchip,rk3568-uart
              - rockchip,rk3588-uart
              - rockchip,rv1108-uart
              - rockchip,rv1126-uart
          - const: snps,dw-apb-uart
      - items:
          - enum:
              - brcm,bcm11351-dw-apb-uart
              - brcm,bcm21664-dw-apb-uart
          - const: snps,dw-apb-uart
      - items:
          - enum:
              - starfive,jh7100-hsuart
              - starfive,jh7100-uart
          - const: snps,dw-apb-uart
      - const: snps,dw-apb-uart

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clock-frequency: true

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    items:
      - const: baudclk
      - const: apb_pclk

  snps,uart-16550-compatible:
    description: reflects the value of UART_16550_COMPATIBLE configuration
      parameter. Define this if your UART does not implement the busy functionality.
    type: boolean

  resets:
    maxItems: 1

  reg-shift: true

  reg-io-width: true

  dcd-override:
    description: Override the DCD modem status signal. This signal will
      always be reported as active instead of being obtained from the modem
      status register. Define this if your serial port does not use this
      pin.
    type: boolean

  dsr-override:
    description: Override the DTS modem status signal. This signal will
      always be reported as active instead of being obtained from the modem
      status register. Define this if your serial port does not use this
      pin.
    type: boolean

  cts-override:
    description: Override the CTS modem status signal. This signal will
      always be reported as active instead of being obtained from the modem
      status register. Define this if your serial port does not use this
      pin.
    type: boolean

  ri-override:
    description: Override the RI modem status signal. This signal will always
      be reported as inactive instead of being obtained from the modem status
      register. Define this if your serial port does not use this pin.
    type: boolean

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    serial@80230000 {
      compatible = "snps,dw-apb-uart";
      reg = <0x80230000 0x100>;
      clock-frequency = <3686400>;
      interrupts = <10>;
      reg-shift = <2>;
      reg-io-width = <4>;
      dcd-override;
      dsr-override;
      cts-override;
      ri-override;
    };

  - |
    // Example with one clock:
    serial@80230000 {
      compatible = "snps,dw-apb-uart";
      reg = <0x80230000 0x100>;
      clocks = <&baudclk>;
      interrupts = <10>;
      reg-shift = <2>;
      reg-io-width = <4>;
    };

  - |
    // Example with two clocks:
    serial@80230000 {
      compatible = "snps,dw-apb-uart";
      reg = <0x80230000 0x100>;
      clocks = <&baudclk>, <&apb_pclk>;
      clock-names = "baudclk", "apb_pclk";
      interrupts = <10>;
      reg-shift = <2>;
      reg-io-width = <4>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/socionext,uniphier-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UniPhier UART controller

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

properties:
  compatible:
    const: socionext,uniphier-uart

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  auto-flow-control:
    description: enable automatic flow control support.
    $ref: /schemas/types.yaml#/definitions/flag

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    aliases {
        serial0 = &serial0;
    };

    serial0: serial@54006800 {
        compatible = "socionext,uniphier-uart";
        reg = <0x54006800 0x40>;
        interrupts = <0 33 4>;
        clocks = <&uart_clk>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2019 Unisoc Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/sprd-uart.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Spreadtrum serial UART

maintainers:
  - Orson Zhai <orsonzhai@gmail.com>
  - Baolin Wang <baolin.wang7@gmail.com>
  - Chunyan Zhang <zhang.lyra@gmail.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - sprd,sc9860-uart
              - sprd,sc9863a-uart
              - sprd,ums512-uart
          - const: sprd,sc9836-uart
      - const: sprd,sc9836-uart

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 3

  clock-names:
    description: |
      "enable" for UART module enable clock, "uart" for UART clock, "source"
      for UART source (parent) clock.
    items:
      - const: enable
      - const: uart
      - const: source

  dmas:
    minItems: 1
    maxItems: 2

  dma-names:
    minItems: 1
    items:
      - const: rx
      - const: tx

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    serial@0 {
      compatible = "sprd,sc9860-uart", "sprd,sc9836-uart";
      reg = <0x0 0x100>;
      interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
      dma-names = "rx", "tx";
      dmas = <&ap_dma 19>, <&ap_dma 20>;
      clock-names = "enable", "uart", "source";
      clocks = <&clk_ap_apb_gates 9>, <&clk_uart0>, <&ext_26m>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

maintainers:
  - Erwan Le Ray <erwan.leray@foss.st.com>

title: STMicroelectronics STM32 USART bindings

properties:
  compatible:
    enum:
      - st,stm32-uart
      - st,stm32f7-uart
      - st,stm32h7-uart

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  label:
    description: label associated with this uart

  st,hw-flow-ctrl:
    description: enable hardware flow control (deprecated)
    $ref: /schemas/types.yaml#/definitions/flag

  uart-has-rtscts: true

  rx-tx-swap: true

  dmas:
    minItems: 1
    maxItems: 2

  dma-names:
    items:
      enum: [ rx, tx ]
    minItems: 1
    maxItems: 2

# cts-gpios and rts-gpios properties can be used instead of 'uart-has-rtscts'
# or 'st,hw-flow-ctrl' (deprecated) for making use of any gpio pins for flow
# control instead of dedicated pins.
#
# It should be noted that both cts-gpios/rts-gpios and 'uart-has-rtscts' or
# 'st,hw-flow-ctrl' (deprecated) properties cannot co-exist in a design.
  cts-gpios: true
  rts-gpios: true

  wakeup-source: true

  rs485-rts-delay: true
  rs485-rts-active-low: true
  linux,rs485-enabled-at-boot-time: true
  rs485-rx-during-tx: true

  rx-threshold:
    description:
      If value is set to 1, RX FIFO threshold is disabled.
    enum: [1, 2, 4, 8, 12, 14, 16]
    default: 8

  tx-threshold:
    description:
      If value is set to 1, TX FIFO threshold is disabled.
    enum: [1, 2, 4, 8, 12, 14, 16]
    default: 8

allOf:
  - $ref: rs485.yaml#
  - $ref: serial.yaml#
  - if:
      required:
        - st,hw-flow-ctrl
    then:
      properties:
        cts-gpios: false
        rts-gpios: false
  - if:
      properties:
        compatible:
          const: st,stm32-uart
    then:
      properties:
        rx-tx-swap: false
  - if:
      properties:
        compatible:
          contains:
            enum:
              - st,stm32-uart
              - st,stm32f7-uart
    then:
      properties:
        rx-threshold: false
        tx-threshold: false

required:
  - compatible
  - reg
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/stm32mp1-clks.h>
    usart1: serial@40011000 {
      compatible = "st,stm32h7-uart";
      reg = <0x40011000 0x400>;
      interrupts = <37>;
      clocks = <&rcc 0 164>;
      dmas = <&dma2 2 4 0x414 0x0>,
             <&dma2 7 4 0x414 0x0>;
      dma-names = "rx", "tx";
      rx-threshold = <4>;
      tx-threshold = <4>;
      rs485-rts-active-low;
    };

...


code:
*st-asc(Serial Port)

Required properties:
- compatible : Should be "st,asc".
- reg, reg-names, interrupts, interrupt-names	: Standard way to define device
			resources with names. look in
			Documentation/devicetree/bindings/resource-names.txt

Optional properties:
- st,hw-flow-ctrl	bool flag to enable hardware flow control.
- st,force-m1		bool flat to force asc to be in Mode-1 recommeded
			for high bit rates (above 19.2K)
Example:
serial@fe440000{
    compatible    = "st,asc";
    reg         = <0xfe440000 0x2c>;
    interrupts     =  <0 209 0>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: "http://devicetree.org/schemas/serial/sunplus,sp7021-uart.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Sunplus SoC SP7021 UART Controller

maintainers:
  - Hammer Hsieh <hammerh0314@gmail.com>

allOf:
  - $ref: serial.yaml#

properties:
  compatible:
    const: sunplus,sp7021-uart

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    aliases {
        serial0 = &uart0;
    };

    uart0: serial@9c000900 {
        compatible = "sunplus,sp7021-uart";
        reg = <0x9c000900 0x80>;
        interrupt-parent = <&intc>;
        interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clkc 0x28>;
        resets = <&rstc 0x18>;
    };
...


code:
* VIA VT8500 and WonderMedia WM8xxx UART Controller

Required properties:
- compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and
	including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later)

- reg: base physical address of the controller and length of memory mapped
	region.

- interrupts: hardware interrupt number

- clocks: shall be the input parent clock phandle for the clock. This should
	be the 24Mhz reference clock.

Aliases may be defined to ensure the correct ordering of the uarts.

Example:
	aliases {
		serial0 = &uart0;
	};

	uart0: serial@d8200000 {
		compatible = "via,vt8500-uart";
		reg = <0xd8200000 0x1040>;
		interrupts = <32>;
		clocks = <&clkuart0>;
	};


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/serial/xlnx,opb-uartlite.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Axi Uartlite

maintainers:
  - Peter Korsgaard <jacmet@sunsite.dk>

properties:
  compatible:
    contains:
      enum:
        - xlnx,xps-uartlite-1.00.a
        - xlnx,opb-uartlite-1.00.b

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  port-number:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Set Uart port number

  clocks:
    maxItems: 1

  clock-names:
    const: s_axi_aclk

  current-speed:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The fixed baud rate that the device was configured for.

  xlnx,data-bits:
    enum: [5, 6, 7, 8]
    description:
      The fixed number of data bits that the device was configured for.

  xlnx,use-parity:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]
    description:
      Whether parity checking was enabled when the device was configured.

  xlnx,odd-parity:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]
    description:
      Whether odd parity was configured.

required:
  - compatible
  - reg
  - interrupts
  - current-speed
  - xlnx,data-bits
  - xlnx,use-parity

allOf:
  - $ref: /schemas/serial.yaml#
  - if:
      properties:
        xlnx,use-parity:
          const: 1
    then:
      required:
        - xlnx,odd-parity

unevaluatedProperties: false

examples:
  - |
      serial@800c0000 {
        compatible = "xlnx,xps-uartlite-1.00.a";
        reg = <0x800c0000 0x10000>;
        interrupts = <0x0 0x6e 0x1>;
        port-number = <0>;
        current-speed = <115200>;
        xlnx,data-bits = <8>;
        xlnx,use-parity = <0>;
      };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/serio/allwinner,sun4i-a10-ps2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 PS2 Host Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description:
  A20 PS2 is dual role controller (PS2 host and PS2 device). These
  bindings for PS2 A10/A20 host controller. IBM compliant IBM PS2 and
  AT-compatible keyboard and mouse can be connected.

properties:
  compatible:
    const: allwinner,sun4i-a10-ps2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun7i-a20-ccu.h>

    ps20: ps2@1c2a000 {
        compatible = "allwinner,sun4i-a10-ps2";
        reg = <0x01c2a000 0x400>;
        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_APB1_PS20>;
    };

...


code:
Altera UP PS/2 controller

Required properties:
- compatible : should be "ALTR,ps2-1.0". <DEPRECATED>
- compatible : should be "altr,ps2-1.0".


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serio/arm,pl050.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm Ltd. PrimeCell PL050 PS/2 Keyboard/Mouse Interface

maintainers:
  - Andre Przywara <andre.przywara@arm.com>

description:
  The Arm PrimeCell PS2 Keyboard/Mouse Interface (KMI) is an AMBA compliant
  peripheral that can be used to implement a keyboard or mouse interface that
  is IBM PS2 or AT compatible.

# We need a select here so we don't match all nodes with 'arm,primecell'
select:
  properties:
    compatible:
      contains:
        const: arm,pl050
  required:
    - compatible

properties:
  compatible:
    items:
      - const: arm,pl050
      - const: arm,primecell

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: KMI reference clock, used to generate the bus timing
      - description: APB register access clock

  clock-names:
    items:
      - const: KMIREFCLK
      - const: apb_pclk

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    serio@70000 {
        compatible = "arm,pl050", "arm,primecell";
        reg = <0x070000 0x1000>;
        interrupts = <8>;
        clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
        clock-names = "KMIREFCLK", "apb_pclk";
    };

...


code:
OLPC AP-SP serio interface

Required properties:
- compatible : "olpc,ap-sp"
- reg : base address and length of SoC's WTM registers
- interrupts : SP-AP interrupt

Example:
	ap-sp@d4290000 {
		compatible = "olpc,ap-sp";
		reg = <0xd4290000 0x1000>;
		interrupts = <40>;
	}


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/serio/ps2-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Bindings for GPIO based PS/2

maintainers:
  - Danilo Krummrich <danilokrummrich@dk-develop.de>

properties:
  compatible:
    const: ps2-gpio

  data-gpios:
    description:
      the gpio used for the data signal - this should be flagged as
      active high using open drain with (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)
      from <dt-bindings/gpio/gpio.h> since the signal is open drain by
      definition
    maxItems: 1

  clk-gpios:
    description:
      the gpio used for the clock signal - this should be flagged as
      active high using open drain with (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)
      from <dt-bindings/gpio/gpio.h> since the signal is open drain by
      definition
    maxItems: 1

  interrupts:
    description:
      The given interrupt should trigger on the falling edge of the clock line.
    maxItems: 1

  write-enable:
    type: boolean
    description:
      Indicates whether write function is provided to serio device. Possibly
      providing the write function will not work, because of the tough timing
      requirements.

required:
  - compatible
  - data-gpios
  - clk-gpios
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    ps2 {
        compatible = "ps2-gpio";
        interrupt-parent = <&gpio>;
        interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
        data-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
        clk-gpios = <&gpio 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
        write-enable;
    };


code:
* ARC PS/2 driver: PS/2 block used in some ARC FPGA's & nSIM OSCI model

Required properties:
- compatible		: "snps,arc_ps2"
- reg			: offset and length (always 0x14) of registers
- interrupts		: interrupt
- interrupt-names	: name of interrupt, must be "arc_ps2_irq"

Example:

serio@c9000400 {
	compatible = "snps,arc_ps2";
	reg = <0xc9000400 0x14>;
	interrupts = <13>;
	interrupt-names = "arc_ps2_irq";
}


code:
DT compatible string versioning for SiFive open-source IP blocks

This document describes the version specification for DT "compatible"
strings for open-source SiFive IP blocks.  HDL for these IP blocks
can be found in this public repository:

https://github.com/sifive/sifive-blocks

IP block-specific DT compatible strings are contained within the HDL,
in the form "sifive,<ip-block-name><integer version number>".

An example is "sifive,uart0" from:

https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43

Until these IP blocks (or IP integration) support version
auto-discovery, the maintainers of these IP blocks intend to increment
the suffixed number in the compatible string whenever the software
interface to these IP blocks changes, or when the functionality of the
underlying IP blocks changes in a way that software should be aware of.

Driver developers can use compatible string "match" values such as
"sifive,uart0" to indicate that their driver is compatible with the
register interface and functionality associated with the relevant
upstream sifive-blocks commits.  It is expected that most drivers will
match on these IP block-specific compatible strings.

DT data authors, when writing data for a particular SoC, should
continue to specify an SoC-specific compatible string value, such as
"sifive,fu540-c000-uart".  This way, if SoC-specific
integration-specific bug fixes or workarounds are needed, the kernel
or other system software can match on this string to apply them.  The
IP block-specific compatible string (such as "sifive,uart0") should
then be specified as a subsequent value.

An example of this style:

    compatible = "sifive,fu540-c000-uart", "sifive,uart0";


code:
Eckelmann SIOX GPIO bus

Required properties:
- compatible : "eckelmann,siox-gpio"
- din-gpios, dout-gpios, dclk-gpios, dld-gpios: references gpios for the
    corresponding bus signals.

Examples:

        siox {
                compatible = "eckelmann,siox-gpio";
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_siox>;

                din-gpios = <&gpio6 11 0>;
                dout-gpios = <&gpio6 8 0>;
                dclk-gpios = <&gpio6 9 0>;
                dld-gpios = <&gpio6 10 0>;
        };


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/slimbus/qcom,slim-ngd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SoC SLIMBus Non Generic Device (NGD) Controller

maintainers:
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description:
  SLIMBus NGD controller is a light-weight driver responsible for communicating
  with SLIMBus slaves directly over the bus using messaging interface and
  communicating with master component residing on ADSP for bandwidth and
  data-channel management

properties:
  compatible:
    enum:
      - qcom,slim-ngd-v1.5.0        # for MSM8996
      - qcom,slim-ngd-v2.1.0        # for SDM845

  reg:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  dmas:
    maxItems: 2

  dma-names:
    items:
      - const: rx
      - const: tx

  interrupts:
    maxItems: 1

  iommus:
    maxItems: 1

patternProperties:
  "^slim@[0-9a-f]+$":
    type: object
    $ref: slimbus.yaml#
    description:
      Each subnode represents an instance of NGD

    properties:
      reg:
        maxItems: 1

    unevaluatedProperties: false

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - dmas
  - dma-names
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    slim-ngd@171c0000 {
        compatible = "qcom,slim-ngd-v2.1.0";
        reg = <0x171c0000 0x2c000>;
        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;

        dmas = <&slimbam 3>, <&slimbam 4>;
        dma-names = "rx", "tx";
        iommus = <&apps_smmu 0x1806 0x0>;
        #address-cells = <1>;
        #size-cells = <0>;

        slim@1 {
            reg = <1>;
            #address-cells = <2>;
            #size-cells = <0>;

            codec@1,0 {
                compatible = "slim217,250";
                reg = <1 0>;
                slim-ifc-dev = <&wcd9340_ifd>;

                #sound-dai-cells = <1>;

                interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-controller;
                #interrupt-cells = <1>;

                #clock-cells = <0>;
                clock-frequency = <9600000>;
                clock-output-names = "mclk";
                qcom,micbias1-microvolt = <1800000>;
                qcom,micbias2-microvolt = <1800000>;
                qcom,micbias3-microvolt = <1800000>;
                qcom,micbias4-microvolt = <1800000>;

                #address-cells = <1>;
                #size-cells = <1>;

                reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;

                /* Rest of the WCD9340 codec */
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/slimbus/qcom,slim.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SoC SLIMbus controller

maintainers:
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description:
  SLIMbus controller used when applications processor controls SLIMbus master
  component.

allOf:
  - $ref: slimbus.yaml#

properties:
  compatible:
    items:
      - enum:
          - qcom,apq8064-slim
      - const: qcom,slim

  reg:
    items:
      - description: Physical address of controller register blocks
      - description: SLEW RATE register

  reg-names:
    items:
      - const: ctrl
      - const: slew

  clocks:
    items:
      - description: Interface clock for this controller
      - description: Interrupt for controller core's BAM

  clock-names:
    items:
      - const: iface
      - const: core

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8960.h>
    #include <dt-bindings/clock/qcom,lcc-msm8960.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        slim@28080000 {
            compatible = "qcom,apq8064-slim", "qcom,slim";
            reg = <0x28080000 0x2000>, <0x80207c 4>;
            reg-names = "ctrl", "slew";
            interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&lcc SLIMBUS_SRC>, <&lcc AUDIO_SLIMBUS_CLK>;
            clock-names = "iface", "core";
            #address-cells = <2>;
            #size-cells = <0>;

            audio-codec@1,0 {
                compatible = "slim217,60";
                reg = <1 0>;
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/slimbus/slimbus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SLIM (Serial Low Power Interchip Media) bus

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description:
  SLIMbus is a 2-wire bus, and is used to communicate with peripheral
  components like audio-codec.

properties:
  $nodename:
    pattern: "^slim(@.*|-[0-9a-f])*$"

  "#address-cells":
    const: 2

  "#size-cells":
    const: 0

patternProperties:
  "^.*@[0-9a-f]+,[0-9a-f]+$":
    type: object
    description: |
      Every SLIMbus controller node can contain zero or more child nodes
      representing slave devices on the bus. Every SLIMbus slave device is
      uniquely determined by the enumeration address containing 4 fields::
      Manufacturer ID, Product code, Device index, and Instance value for the
      device.

      If child node is not present and it is instantiated after device
      discovery (slave device reporting itself present).

      In some cases it may be necessary to describe non-probeable device
      details such as non-standard ways of powering up a device. In such cases,
      child nodes for those devices will be present as slaves of the SLIMbus
      controller.

    properties:
      compatible:
        pattern: "^slim[0-9a-f]+,[0-9a-f]+$"

      reg:
        maxItems: 1
        description: |
          Pair of (device index, instande ID), where::
           - Device index, which uniquely identifies multiple devices within a
             single component.
           - Instance ID, can be used for the cases where multiple devices of
             the same type or class are attached to the bus.

    required:
      - compatible
      - reg

    additionalProperties: true

required:
  - "#address-cells"
  - "#size-cells"

additionalProperties: true

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8960.h>
    #include <dt-bindings/clock/qcom,lcc-msm8960.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        slim@28080000 {
            compatible = "qcom,apq8064-slim", "qcom,slim";
            reg = <0x28080000 0x2000>, <0x80207c 4>;
            reg-names = "ctrl", "slew";
            interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&lcc SLIMBUS_SRC>, <&lcc AUDIO_SLIMBUS_CLK>;
            clock-names = "iface", "core";
            #address-cells = <2>;
            #size-cells = <0>;

            audio-codec@1,0 {
                compatible = "slim217,60";
                reg = <1 0>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/amlogic/amlogic,canvas.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Canvas Video Lookup Table

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>
  - Maxime Jourdan <mjourdan@baylibre.com>

description: |
  A canvas is a collection of metadata that describes a pixel buffer.
  Those metadata include: width, height, phyaddr, wrapping and block mode.
  Starting with GXBB the endianness can also be described.

  Many IPs within Amlogic SoCs rely on canvas indexes to read/write pixel data
  rather than use the phy addresses directly. For instance, this is the case for
  the video decoders and the display.

  Amlogic SoCs have 256 canvas.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - amlogic,meson8-canvas
              - amlogic,meson8b-canvas
              - amlogic,meson8m2-canvas
          - const: amlogic,canvas
      - const: amlogic,canvas # GXBB and newer SoCs

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    canvas: video-lut@48 {
        compatible = "amlogic,canvas";
        reg = <0x48 0x14>;
    };


code:
Amlogic Internal Clock Measurer
===============================

The Amlogic SoCs contains an IP to measure the internal clocks.
The precision is multiple of MHz, useful to debug the clock states.

Required properties:
- compatible: Shall contain one of the following :
			"amlogic,meson-gx-clk-measure" for GX SoCs
			"amlogic,meson8-clk-measure" for Meson8 SoCs
			"amlogic,meson8b-clk-measure" for Meson8b SoCs
			"amlogic,meson-axg-clk-measure" for AXG SoCs
			"amlogic,meson-g12a-clk-measure" for G12a SoCs
			"amlogic,meson-sm1-clk-measure" for SM1 SoCs
- reg: base address and size of the Clock Measurer register space.

Example:
	clock-measure@8758 {
		compatible = "amlogic,meson-gx-clk-measure";
		reg = <0x0 0x8758 0x0 0x10>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# # Copyright (c) 2018 Google LLC
# # Copyright (c) 2021 Aspeed Technology Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Aspeed UART Routing Controller

maintainers:
  - Oskar Senft <osk@google.com>
  - Chia-Wei Wang <chiawei_wang@aspeedtech.com>

description:
  The Aspeed UART routing control allow to dynamically route the inputs for
  the built-in UARTS and physical serial I/O ports.

  This allows, for example, to connect the output of UART to another UART.
  This can be used to enable Host <-> BMC communication via UARTs, e.g. to
  allow access to the Host's serial console.

  This driver is for the BMC side. The sysfs files allow the BMC userspace
  which owns the system configuration policy, to configure how UARTs and
  physical serial I/O ports are routed.

properties:
  compatible:
    items:
      - enum:
          - aspeed,ast2400-uart-routing
          - aspeed,ast2500-uart-routing
          - aspeed,ast2600-uart-routing
  reg:
    maxItems: 1

required:
  - compatible

additionalProperties: false

examples:
  - |
    lpc: lpc@1e789000 {
        compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
        reg = <0x1e789000 0x1000>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x1e789000 0x1000>;

        uart_routing: uart-routing@98 {
            compatible = "aspeed,ast2600-uart-routing";
            reg = <0x98 0x8>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/bcm/brcm,bcm2835-pm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: BCM2835 PM (Power domains, watchdog)

description: |
  The PM block controls power domains and some reset lines, and includes a
  watchdog timer.

maintainers:
  - Nicolas Saenz Julienne <nsaenz@kernel.org>

allOf:
  - $ref: /schemas/watchdog/watchdog.yaml#

properties:
  compatible:
    items:
      - enum:
          - brcm,bcm2835-pm
          - brcm,bcm2711-pm
      - const: brcm,bcm2835-pm-wdt

  reg:
    minItems: 2
    maxItems: 3

  reg-names:
    minItems: 2
    items:
      - const: pm
      - const: asb
      - const: rpivid_asb

  "#power-domain-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    minItems: 4
    maxItems: 4

  clock-names:
    items:
      - const: v3d
      - const: peri_image
      - const: h264
      - const: isp

  system-power-controller:
    type: boolean

  timeout-sec: true

required:
  - compatible
  - reg
  - "#power-domain-cells"
  - "#reset-cells"
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/bcm2835.h>

    watchdog@7e100000 {
        compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
        #power-domain-cells = <1>;
        #reset-cells = <1>;
        reg = <0x7e100000 0x114>,
              <0x7e00a000 0x24>;
        reg-names = "pm", "asb";
        clocks = <&clocks BCM2835_CLOCK_V3D>,
               <&clocks BCM2835_CLOCK_PERI_IMAGE>,
               <&clocks BCM2835_CLOCK_H264>,
               <&clocks BCM2835_CLOCK_ISP>;
        clock-names = "v3d", "peri_image", "h264", "isp";
        system-power-controller;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/bcm/brcm,bcm2835-vchiq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom VCHIQ firmware services

maintainers:
  - Nicolas Saenz Julienne <nsaenz@kernel.org>

description:
  The VCHIQ communication channel can be provided by BCM283x and Capri SoCs,
  to communicate with the VPU-side OS services.

properties:
  compatible:
    oneOf:
      - description: BCM2835 based boards
        items:
          - enum:
              - brcm,bcm2835-vchiq

      - description: BCM2836/BCM2837 based boards
        items:
          - enum:
              - brcm,bcm2836-vchiq
          - const: brcm,bcm2835-vchiq

  reg:
    description: Physical base address and length of the doorbell register pair
    minItems: 1

  interrupts:
    description: Interrupt number of the doorbell interrupt
    minItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    mailbox@7e00b840 {
      compatible = "brcm,bcm2835-vchiq";
      reg = <0x7e00b840 0xf>;
      interrupts = <0 2>;
    };

...


code:
Raspberry Pi power domain driver

Required properties:

- compatible:		Should be "raspberrypi,bcm2835-power".
- firmware:		Reference to the RPi firmware device node.
- #power-domain-cells:	Should be <1>, we providing multiple power domains.

The valid defines for power domain are:

 RPI_POWER_DOMAIN_I2C0
 RPI_POWER_DOMAIN_I2C1
 RPI_POWER_DOMAIN_I2C2
 RPI_POWER_DOMAIN_VIDEO_SCALER
 RPI_POWER_DOMAIN_VPU1
 RPI_POWER_DOMAIN_HDMI
 RPI_POWER_DOMAIN_USB
 RPI_POWER_DOMAIN_VEC
 RPI_POWER_DOMAIN_JPEG
 RPI_POWER_DOMAIN_H264
 RPI_POWER_DOMAIN_V3D
 RPI_POWER_DOMAIN_ISP
 RPI_POWER_DOMAIN_UNICAM0
 RPI_POWER_DOMAIN_UNICAM1
 RPI_POWER_DOMAIN_CCP2RX
 RPI_POWER_DOMAIN_CSI2
 RPI_POWER_DOMAIN_CPI
 RPI_POWER_DOMAIN_DSI0
 RPI_POWER_DOMAIN_DSI1
 RPI_POWER_DOMAIN_TRANSPOSER
 RPI_POWER_DOMAIN_CCP2TX
 RPI_POWER_DOMAIN_CDP
 RPI_POWER_DOMAIN_ARM

Example:

power: power {
	compatible = "raspberrypi,bcm2835-power";
	firmware = <&firmware>;
	#power-domain-cells = <1>;
};

Example for using power domain:

&usb {
       power-domains = <&power RPI_POWER_DOMAIN_USB>;
};


code:
Device Tree bindings for Marvell PMU

Required properties:
 - compatible: value should be "marvell,dove-pmu".
    May also include "simple-bus" if there are child devices, in which
    case the ranges node is required.
 - reg: two base addresses and sizes of the PM controller and PMU.
 - interrupts: single interrupt number for the PMU interrupt
 - interrupt-controller: must be specified as the PMU itself is an
    interrupt controller.
 - #interrupt-cells: must be 1.
 - #reset-cells: must be 1.
 - domains: sub-node containing domain descriptions

Optional properties:
 - ranges: defines the address mapping for child devices, as per the
   standard property of this name.  Required when compatible includes
   "simple-bus".

Power domain descriptions are listed as child nodes of the "domains"
sub-node.  Each domain has the following properties:

Required properties:
 - #power-domain-cells: must be 0.

Optional properties:
 - marvell,pmu_pwr_mask: specifies the mask value for PMU power register
 - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
 - resets: points to the reset manager (PMU node) and reset index.

Example:

	pmu: power-management@d0000 {
		compatible = "marvell,dove-pmu";
		reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
		interrupts = <33>;
		interrupt-controller;
		#interrupt-cells = <1>;
		#reset-cells = <1>;

		domains {
			vpu_domain: vpu-domain {
				#power-domain-cells = <0>;
				marvell,pmu_pwr_mask = <0x00000008>;
				marvell,pmu_iso_mask = <0x00000001>;
				resets = <&pmu 16>;
			};

			gpu_domain: gpu-domain {
				#power-domain-cells = <0>;
				marvell,pmu_pwr_mask = <0x00000004>;
				marvell,pmu_iso_mask = <0x00000002>;
				resets = <&pmu 18>;
			};
		};
	};


code:
QorIQ DPAA Buffer Manager Portals Device Tree Binding

Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.

CONTENTS

	- BMan Portal
	- Example

BMan Portal Node

Portals are memory mapped interfaces to BMan that allow low-latency, lock-less
interaction by software running on processor cores, accelerators and network
interfaces with the BMan

PROPERTIES

- compatible
	Usage:		Required
	Value type:	<stringlist>
	Definition:	Must include "fsl,bman-portal-<hardware revision>"
			May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal"

- reg
	Usage:		Required
	Value type:	<prop-encoded-array>
	Definition:	Two regions. The first is the cache-enabled region of
			the portal. The second is the cache-inhibited region of
			the portal

- interrupts
	Usage:		Required
	Value type:	<prop-encoded-array>
	Definition:	Standard property

EXAMPLE

The example below shows a (P4080) BMan portals container/bus node with two portals

	bman-portals@ff4000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0 0xf 0xf4000000 0x200000>;

		bman-portal@0 {
			compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
			reg = <0x0 0x4000>, <0x100000 0x1000>;
			interrupts = <105 2 0 0>;
		};
		bman-portal@4000 {
			compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
			reg = <0x4000 0x4000>, <0x101000 0x1000>;
			interrupts = <107 2 0 0>;
		};
	};


code:
QorIQ DPAA Buffer Manager Device Tree Bindings

Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.

CONTENTS

	- BMan Node
	- BMan Private Memory Node
	- Example

BMan Node

The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA).
BMan supports hardware allocation and deallocation of buffers belonging to pools
originally created by software with configurable depletion thresholds. This
binding covers the CCSR space programming model

PROPERTIES

- compatible
	Usage:		Required
	Value type:	<stringlist>
	Definition:	Must include "fsl,bman"
			May include "fsl,<SoC>-bman"

- reg
	Usage:		Required
	Value type:	<prop-encoded-array>
	Definition:	Registers region within the CCSR address space

The BMan revision information is located in the BMAN_IP_REV_1/2 registers which
are located at offsets 0xbf8 and 0xbfc

- interrupts
	Usage:		Required
	Value type:	<prop-encoded-array>
	Definition:	Standard property. The error interrupt

- fsl,bman-portals
	Usage:		Required
	Value type:	<phandle>
	Definition:	Phandle to this BMan instance's portals

- fsl,liodn
	Usage:		See pamu.txt
	Value type:	<prop-encoded-array>
	Definition:	PAMU property used for static LIODN assignment

- fsl,iommu-parent
	Usage:		See pamu.txt
	Value type:	<phandle>
	Definition:	PAMU property used for dynamic LIODN assignment

	For additional details about the PAMU/LIODN binding(s) see pamu.txt

Devices connected to a BMan instance via Direct Connect Portals (DCP) must link
to the respective BMan instance

- fsl,bman
	Usage:		Required
	Value type:	<prop-encoded-array>
	Description:	List of phandle and DCP index pairs, to the BMan instance
			to which this device is connected via the DCP

BMan Private Memory Node

BMan requires a contiguous range of physical memory used for the backing store
for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as
a node under the /reserved-memory node.

The BMan FBPR memory node must be named "bman-fbpr"

PROPERTIES

- compatible
	Usage:		required
	Value type:	<stringlist>
	Definition:	PPC platforms: Must include "fsl,bman-fbpr"
			ARM platforms: Must include "shared-dma-pool"
				       as well as the "no-map" property

The following constraints are relevant to the FBPR private memory:
	- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
	  16 GiB
	- The alignment must be a muliptle of the memory size

The size of the FBPR must be chosen by observing the hardware features configured
via the Reset Configuration Word (RCW) and that are relevant to a specific board
(e.g. number of MAC(s) pinned-out, number of offline/host command FMan ports,
etc.). The size configured in the DT must reflect the hardware capabilities and
not the specific needs of an application

For additional details about reserved memory regions see reserved-memory.txt

EXAMPLE

The example below shows a BMan FBPR dynamic allocation memory node

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		bman_fbpr: bman-fbpr {
			compatible = "shared-mem-pool";
			size = <0 0x1000000>;
			alignment = <0 0x1000000>;
			no-map;
		};
	};

The example below shows a (P4080) BMan CCSR-space node

	bportals: bman-portals@ff4000000 {
		...
	};

	crypto@300000 {
		...
		fsl,bman = <&bman, 2>;
		...
	};

	bman: bman@31a000 {
		compatible = "fsl,bman";
		reg = <0x31a000 0x1000>;
		interrupts = <16 2 1 2>;
		fsl,liodn = <0x17>;
		fsl,bman-portals = <&bportals>;
		memory-region = <&bman_fbpr>;
	};

	fman@400000 {
		...
		fsl,bman = <&bman, 0>;
		...
	};


code:
* Freescale Communications Processor Module

NOTE: This is an interim binding, and will likely change slightly,
as more devices are supported.  The QE bindings especially are
incomplete.

* Root CPM node

Properties:
- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
- reg : A 48-byte region beginning with CPCR.

Example:
     cpm@119c0 {
	#address-cells = <1>;
	#size-cells = <1>;
	#interrupt-cells = <2>;
	compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
	reg = <119c0 30>;
     }

* Properties common to multiple CPM/QE devices

- fsl,cpm-command : This value is ORed with the opcode and command flag
                    to specify the device on which a CPM command operates.

- fsl,cpm-brg : Indicates which baud rate generator the device
                is associated with.  If absent, an unused BRG
                should be dynamically allocated.  If zero, the
                device uses an external clock rather than a BRG.

- reg : Unless otherwise specified, the first resource represents the
        scc/fcc/ucc registers, and the second represents the device's
        parameter RAM region (if it has one).

* Multi-User RAM (MURAM)

The multi-user/dual-ported RAM is expressed as a bus under the CPM node.

Ranges must be set up subject to the following restrictions:

- Children's reg nodes must be offsets from the start of all muram, even
  if the user-data area does not begin at zero.
- If multiple range entries are used, the difference between the parent
  address and the child address must be the same in all, so that a single
  mapping can cover them all while maintaining the ability to determine
  CPM-side offsets with pointer subtraction.  It is recommended that
  multiple range entries not be used.
- A child address of zero must be translatable, even if no reg resources
  contain it.

A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
indicate the portion of muram that is usable by the OS for arbitrary
purposes.  The data node may have an arbitrary number of reg resources,
all of which contribute to the allocatable muram pool.

Example, based on mpc8272:
	muram@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 10000>;

		data@0 {
			compatible = "fsl,cpm-muram-data";
			reg = <0 2000 9800 800>;
		};
	};


code:
* Baud Rate Generators

Currently defined compatibles:
fsl,cpm-brg
fsl,cpm1-brg
fsl,cpm2-brg

Properties:
- reg : There may be an arbitrary number of reg resources; BRG
  numbers are assigned to these in order.
- clock-frequency : Specifies the base frequency driving
  the BRG.

Example:
	brg@119f0 {
		compatible = "fsl,mpc8272-brg",
			     "fsl,cpm2-brg",
			     "fsl,cpm-brg";
		reg = <119f0 10 115f0 10>;
		clock-frequency = <d#25000000>;
	};


code:
* I2C

The I2C controller is expressed as a bus under the CPM node.

Properties:
- compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
- reg : On CPM2 devices, the second resource doesn't specify the I2C
  Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
  (typically 0x8afc 0x2).
- #address-cells : Should be one. The cell is the i2c device address with
  the r/w bit set to zero.
- #size-cells : Should be zero.
- clock-frequency : Can be used to set the i2c clock frequency. If
  unspecified, a default frequency of 60kHz is being used.
The following two properties are deprecated. They are only used by legacy
i2c drivers to find the bus to probe:
- linux,i2c-index : Can be used to hard code an i2c bus number. By default,
  the bus number is dynamically assigned by the i2c core.
- linux,i2c-class : Can be used to override the i2c class. The class is used
  by legacy i2c device drivers to find a bus in a specific context like
  system management, video or sound. By default, I2C_CLASS_HWMON (1) is
  being used. The definition of the classes can be found in
  include/i2c/i2c.h

Example, based on mpc823:

	i2c@860 {
		compatible = "fsl,mpc823-i2c",
			     "fsl,cpm1-i2c";
		reg = <0x860 0x20 0x3c80 0x30>;
		interrupts = <16>;
		interrupt-parent = <&CPM_PIC>;
		fsl,cpm-command = <0x10>;
		#address-cells = <1>;
		#size-cells = <0>;

		rtc@68 {
			compatible = "dallas,ds1307";
			reg = <0x68>;
		};
	};


code:
* Interrupt Controllers

Currently defined compatibles:
- fsl,cpm1-pic
  - only one interrupt cell
- fsl,pq1-pic
- fsl,cpm2-pic
  - second interrupt cell is level/sense:
    - 2 is falling edge
    - 8 is active low

Example:
	interrupt-controller@10c00 {
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <10c00 80>;
		compatible = "mpc8272-pic", "fsl,cpm2-pic";
	};


code:
* USB (Universal Serial Bus Controller)

Properties:
- compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"

Example:
	usb@11bc0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,cpm2-usb";
		reg = <11b60 18 8b00 100>;
		interrupts = <b 8>;
		interrupt-parent = <&PIC>;
		fsl,cpm-command = <2e600000>;
	};


code:
Every GPIO controller node must have #gpio-cells property defined,
this information will be used to translate gpio-specifiers.

On CPM1 devices, all ports are using slightly different register layouts.
Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.

On CPM2 devices, all ports are 32bit ports and use a common register layout.

Required properties:
- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
  "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
  "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
- #gpio-cells : Should be two. The first cell is the pin number and the
  second cell is used to specify optional parameters (currently unused).
- gpio-controller : Marks the port as GPIO controller.
Optional properties:
- fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
  on CPM1), this item tells which ports have an associated interrupt (ports are
  listed in the same order as in PCINT register)
- interrupts : This property provides the list of interrupt for each GPIO having
  one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
  many interrupts as number of ones in the mask property. The first interrupt in
  the list corresponds to the most significant bit of the mask.

Example of four SOC GPIO banks defined as gpio-controller nodes:

	CPM1_PIO_A: gpio-controller@950 {
		#gpio-cells = <2>;
		compatible = "fsl,cpm1-pario-bank-a";
		reg = <0x950 0x10>;
		gpio-controller;
	};

	CPM1_PIO_B: gpio-controller@ab8 {
		#gpio-cells = <2>;
		compatible = "fsl,cpm1-pario-bank-b";
		reg = <0xab8 0x10>;
		gpio-controller;
	};

	CPM1_PIO_C: gpio-controller@960 {
		#gpio-cells = <2>;
		compatible = "fsl,cpm1-pario-bank-c";
		reg = <0x960 0x10>;
		fsl,cpm1-gpio-irq-mask = <0x0fff>;
		interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>;
		interrupt-parent = <&CPM_PIC>;
		gpio-controller;
	};

	CPM1_PIO_E: gpio-controller@ac8 {
		#gpio-cells = <2>;
		compatible = "fsl,cpm1-pario-bank-e";
		reg = <0xac8 0x18>;
		gpio-controller;
	};


code:
* Network

Currently defined compatibles:
- fsl,cpm1-scc-enet
- fsl,cpm2-scc-enet
- fsl,cpm1-fec-enet
- fsl,cpm2-fcc-enet (third resource is GFEMR)
- fsl,qe-enet

Example:

	ethernet@11300 {
		compatible = "fsl,mpc8272-fcc-enet",
			     "fsl,cpm2-fcc-enet";
		reg = <11300 20 8400 100 11390 1>;
		local-mac-address = [ 00 00 00 00 00 00 ];
		interrupts = <20 8>;
		interrupt-parent = <&PIC>;
		phy-handle = <&PHY0>;
		fsl,cpm-command = <12000300>;
	};

* MDIO

Currently defined compatibles:
fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
fsl,cpm2-mdio-bitbang (reg is port C registers)

Properties for fsl,cpm2-mdio-bitbang:
fsl,mdio-pin : pin of port C controlling mdio data
fsl,mdc-pin : pin of port C controlling mdio clock

Example:
	mdio@10d40 {
		compatible = "fsl,mpc8272ads-mdio-bitbang",
			     "fsl,mpc8272-mdio-bitbang",
			     "fsl,cpm2-mdio-bitbang";
		reg = <10d40 14>;
		#address-cells = <1>;
		#size-cells = <0>;
		fsl,mdio-pin = <12>;
		fsl,mdc-pin = <13>;
	};

* HDLC

Currently defined compatibles:
- fsl,ucc-hdlc

Properties for fsl,ucc-hdlc:
- rx-clock-name
- tx-clock-name
	Usage: required
	Value type: <string>
	Definition : Must be "brg1"-"brg16" for internal clock source,
		     Must be "clk1"-"clk24" for external clock source.

- fsl,tdm-interface
	Usage: optional
	Value type: <empty>
	Definition : Specify that hdlc is based on tdm-interface

The property below is dependent on fsl,tdm-interface:
- fsl,rx-sync-clock
	Usage: required
	Value type: <string>
	Definition : Must be "none", "rsync_pin", "brg9-11" and "brg13-15".

- fsl,tx-sync-clock
	Usage: required
	Value type: <string>
	Definition : Must be "none", "tsync_pin", "brg9-11" and "brg13-15".

- fsl,tdm-framer-type
	Usage: required for tdm interface
	Value type: <string>
	Definition : "e1" or "t1".Now e1 and t1 are used, other framer types
		     are not supported.

- fsl,tdm-id
	Usage: required for tdm interface
	Value type: <u32>
	Definition : number of TDM ID

- fsl,tx-timeslot-mask
- fsl,rx-timeslot-mask
	Usage: required for tdm interface
	Value type: <u32>
	Definition : time slot mask for TDM operation. Indicates which time
		     slots used for transmitting and receiving.

- fsl,siram-entry-id
	Usage: required for tdm interface
	Value type: <u32>
	Definition : Must be 0,2,4...64. the number of TDM entry.

- fsl,tdm-internal-loopback
	usage: optional for tdm interface
	value type: <empty>
	Definition : Internal loopback connecting on TDM layer.
- fsl,hmask
	usage: optional
	Value type: <u16>
	Definition: HDLC address recognition. Set to zero to disable
		    address filtering of packets:
		    fsl,hmask = /bits/ 16 <0x0000>;

Example for tdm interface:

	ucc@2000 {
		compatible = "fsl,ucc-hdlc";
		rx-clock-name = "clk8";
		tx-clock-name = "clk9";
		fsl,rx-sync-clock = "rsync_pin";
		fsl,tx-sync-clock = "tsync_pin";
		fsl,tx-timeslot-mask = <0xfffffffe>;
		fsl,rx-timeslot-mask = <0xfffffffe>;
		fsl,tdm-framer-type = "e1";
		fsl,tdm-id = <0>;
		fsl,siram-entry-id = <0>;
		fsl,tdm-interface;
	};

Example for hdlc without tdm interface:

	ucc@2000 {
		compatible = "fsl,ucc-hdlc";
		rx-clock-name = "brg1";
		tx-clock-name = "brg1";
	};


code:
* Freescale QUICC Engine module (QE)
This represents qe module that is installed on PowerQUICC II Pro.

NOTE:  This is an interim binding; it should be updated to fit
in with the CPM binding later in this document.

Basically, it is a bus of devices, that could act more or less
as a complete entity (UCC, USB etc ). All of them should be siblings on
the "root" qe node, using the common properties from there.
The description below applies to the qe of MPC8360 and
more nodes and properties would be extended in the future.

i) Root QE device

Required properties:
- compatible : should be "fsl,qe";
- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
- reg : offset and length of the device registers.
- bus-frequency : the clock frequency for QUICC Engine.
- fsl,qe-num-riscs: define how many RISC engines the QE has.
- fsl,qe-snums: This property has to be specified as '/bits/ 8' value,
  defining the array of serial number (SNUM) values for the virtual
  threads.

Optional properties:
- fsl,firmware-phandle:
    Usage: required only if there is no fsl,qe-firmware child node
    Value type: <phandle>
    Definition: Points to a firmware node (see "QE Firmware Node" below)
        that contains the firmware that should be uploaded for this QE.
        The compatible property for the firmware node should say,
        "fsl,qe-firmware".

Recommended properties
- brg-frequency : the internal clock source frequency for baud-rate
  generators in Hz.

Deprecated properties
- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use
  for the threads. Use fsl,qe-snums instead to not only specify the
  number of snums, but also their values.

Example:
     qe@e0100000 {
	#address-cells = <1>;
	#size-cells = <1>;
	#interrupt-cells = <2>;
	compatible = "fsl,qe";
	ranges = <0 e0100000 00100000>;
	reg = <e0100000 480>;
	brg-frequency = <0>;
	bus-frequency = <179A7B00>;
	fsl,qe-snums = /bits/ 8 <
		0x04 0x05 0x0C 0x0D 0x14 0x15 0x1C 0x1D
		0x24 0x25 0x2C 0x2D 0x34 0x35 0x88 0x89
		0x98 0x99 0xA8 0xA9 0xB8 0xB9 0xC8 0xC9
		0xD8 0xD9 0xE8 0xE9>;
     }

* Multi-User RAM (MURAM)

Required properties:
- compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
- mode : the could be "host" or "slave".
- ranges : Should be defined as specified in 1) to describe the
   translation of MURAM addresses.
- data-only : sub-node which defines the address area under MURAM
   bus that can be allocated as data/parameter

Example:

     muram@10000 {
	compatible = "fsl,qe-muram", "fsl,cpm-muram";
	ranges = <0 00010000 0000c000>;

	data-only@0{
		compatible = "fsl,qe-muram-data",
			     "fsl,cpm-muram-data";
		reg = <0 c000>;
	};
     };

* Interrupt Controller (IC)

Required properties:
- compatible : should be "fsl,qe-ic".
- reg : Address range of IC register set.
- interrupts : interrupts generated by the device.
- interrupt-controller : this device is a interrupt controller.

Example:

	qeic: interrupt-controller@80 {
		interrupt-controller;
		compatible = "fsl,qe-ic";
		#address-cells = <0>;
		#interrupt-cells = <1>;
		reg = <0x80 0x80>;
		interrupts = <95 2 0 0  94 2 0 0>;
	};

* Serial Interface Block (SI)

The SI manages the routing of eight TDM lines to the QE block serial drivers
, the MCC and the UCCs, for receive and transmit.

Required properties:
- compatible : must be "fsl,<chip>-qe-si". For t1040, must contain
  "fsl,t1040-qe-si".
- reg : Address range of SI register set.

Example:

	si1: si@700 {
		compatible = "fsl,t1040-qe-si";
		reg = <0x700 0x80>;
	};

* Serial Interface Block RAM(SIRAM)

store the routing entries of SI

Required properties:
- compatible : should be "fsl,<chip>-qe-siram". For t1040, must contain
  "fsl,t1040-qe-siram".
- reg : Address range of SI RAM.

Example:

	siram1: siram@1000 {
		compatible = "fsl,t1040-qe-siram";
		reg = <0x1000 0x800>;
	};

* QE Firmware Node

This node defines a firmware binary that is embedded in the device tree, for
the purpose of passing the firmware from bootloader to the kernel, or from
the hypervisor to the guest.

The firmware node itself contains the firmware binary contents, a compatible
property, and any firmware-specific properties.  The node should be placed
inside a QE node that needs it.  Doing so eliminates the need for a
fsl,firmware-phandle property.  Other QE nodes that need the same firmware
should define an fsl,firmware-phandle property that points to the firmware node
in the first QE node.

The fsl,firmware property can be specified in the DTS (possibly using incbin)
or can be inserted by the boot loader at boot time.

Required properties:
  - compatible
      Usage: required
      Value type: <string>
      Definition: A standard property.  Specify a string that indicates what
          kind of firmware it is.  For QE, this should be "fsl,qe-firmware".

   - fsl,firmware
      Usage: required
      Value type: <prop-encoded-array>, encoded as an array of bytes
      Definition: A standard property.  This property contains the firmware
          binary "blob".

Example:
	qe1@e0080000 {
		compatible = "fsl,qe";
		qe_firmware:qe-firmware {
			compatible = "fsl,qe-firmware";
			fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...];
		};
		...
	};

	qe2@e0090000 {
		compatible = "fsl,qe";
		fsl,firmware-phandle = <&qe_firmware>;
		...
	};


code:
* Uploaded QE firmware

      If a new firmware has been uploaded to the QE (usually by the
      boot loader), then a 'firmware' child node should be added to the QE
      node.  This node provides information on the uploaded firmware that
      device drivers may need.

      Required properties:
      - id: The string name of the firmware.  This is taken from the 'id'
            member of the qe_firmware structure of the uploaded firmware.
            Device drivers can search this string to determine if the
            firmware they want is already present.
      - extended-modes: The Extended Modes bitfield, taken from the
		   firmware binary.  It is a 64-bit number represented
		   as an array of two 32-bit numbers.
      - virtual-traps: The virtual traps, taken from the firmware binary.
		  It is an array of 8 32-bit numbers.

Example:
	firmware {
		id = "Soft-UART";
		extended-modes = <0 0>;
		virtual-traps = <0 0 0 0 0 0 0 0>;
	};


code:
* Parallel I/O Ports

This node configures Parallel I/O ports for CPUs with QE support.
The node should reside in the "soc" node of the tree.  For each
device that using parallel I/O ports, a child node should be created.
See the definition of the Pin configuration nodes below for more
information.

Required properties:
- device_type : should be "par_io".
- reg : offset to the register set and its length.
- num-ports : number of Parallel I/O ports

Example:
par_io@1400 {
	reg = <1400 100>;
	#address-cells = <1>;
	#size-cells = <0>;
	device_type = "par_io";
	num-ports = <7>;
	ucc_pin@1 {
		......
	};

Note that "par_io" nodes are obsolete, and should not be used for
the new device trees. Instead, each Par I/O bank should be represented
via its own gpio-controller node:

Required properties:
- #gpio-cells : should be "2".
- compatible : should be "fsl,<chip>-qe-pario-bank",
  "fsl,mpc8323-qe-pario-bank".
- reg : offset to the register set and its length.
- gpio-controller : node to identify gpio controllers.

Example:
	qe_pio_a: gpio-controller@1400 {
		#gpio-cells = <2>;
		compatible = "fsl,mpc8360-qe-pario-bank",
		"fsl,mpc8323-qe-pario-bank";
		reg = <0x1400 0x18>;
		gpio-controller;
	  };

	qe_pio_e: gpio-controller@1460 {
		#gpio-cells = <2>;
		compatible = "fsl,mpc8360-qe-pario-bank",
			     "fsl,mpc8323-qe-pario-bank";
		reg = <0x1460 0x18>;
		gpio-controller;
	  };


code:
* Pin configuration nodes

Required properties:
- pio-map : array of pin configurations.  Each pin is defined by 6
  integers.  The six numbers are respectively: port, pin, dir,
  open_drain, assignment, has_irq.
  - port : port number of the pin; 0-6 represent port A-G in UM.
  - pin : pin number in the port.
  - dir : direction of the pin, should encode as follows:

     0 = The pin is disabled
     1 = The pin is an output
     2 = The pin is an input
     3 = The pin is I/O

  - open_drain : indicates the pin is normal or wired-OR:

     0 = The pin is actively driven as an output
     1 = The pin is an open-drain driver. As an output, the pin is
         driven active-low, otherwise it is three-stated.

  - assignment : function number of the pin according to the Pin Assignment
    tables in User Manual.  Each pin can have up to 4 possible functions in
    QE and two options for CPM.
  - has_irq : indicates if the pin is used as source of external
    interrupts.

Example:
     ucc_pin@1 {
	pio-map = <
	/* port  pin  dir  open_drain  assignment  has_irq */
		0  3  1  0  1  0 	/* TxD0 */
		0  4  1  0  1  0 	/* TxD1 */
		0  5  1  0  1  0 	/* TxD2 */
		0  6  1  0  1  0 	/* TxD3 */
		1  6  1  0  3  0 	/* TxD4 */
		1  7  1  0  1  0 	/* TxD5 */
		1  9  1  0  2  0 	/* TxD6 */
		1  a  1  0  2  0 	/* TxD7 */
		0  9  2  0  1  0 	/* RxD0 */
		0  a  2  0  1  0 	/* RxD1 */
		0  b  2  0  1  0 	/* RxD2 */
		0  c  2  0  1  0 	/* RxD3 */
		0  d  2  0  1  0 	/* RxD4 */
		1  1  2  0  2  0 	/* RxD5 */
		1  0  2  0  2  0 	/* RxD6 */
		1  4  2  0  2  0 	/* RxD7 */
		0  7  1  0  1  0 	/* TX_EN */
		0  8  1  0  1  0 	/* TX_ER */
		0  f  2  0  1  0 	/* RX_DV */
		0  10 2  0  1  0 	/* RX_ER */
		0  0  2  0  1  0 	/* RX_CLK */
		2  9  1  0  3  0 	/* GTX_CLK - CLK10 */
		2  8  2  0  1  0>;	/* GTX125 - CLK9 */
     };


code:
* UCC (Unified Communications Controllers)

Required properties:
- device_type : should be "network", "hldc", "uart", "transparent"
  "bisync", "atm", or "serial".
- compatible : could be "ucc_geth" or "fsl_atm" and so on.
- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
- reg : Offset and length of the register set for the device
- interrupts : <a b> where a is the interrupt number and b is a
  field that represents an encoding of the sense and level
  information for the interrupt.  This should be encoded based on
  the information in section 2) depending on the type of interrupt
  controller you have.
- pio-handle : The phandle for the Parallel I/O port configuration.
- port-number : for UART drivers, the port number to use, between 0 and 3.
  This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
  The port number is added to the minor number of the device.  Unlike the
  CPM UART driver, the port-number is required for the QE UART driver.
- soft-uart : for UART drivers, if specified this means the QE UART device
  driver should use "Soft-UART" mode, which is needed on some SOCs that have
  broken UART hardware.  Soft-UART is provided via a microcode upload.
- rx-clock-name: the UCC receive clock source
  "none": clock source is disabled
  "brg1" through "brg16": clock source is BRG1-BRG16, respectively
  "clk1" through "clk24": clock source is CLK1-CLK24, respectively
- tx-clock-name: the UCC transmit clock source
  "none": clock source is disabled
  "brg1" through "brg16": clock source is BRG1-BRG16, respectively
  "clk1" through "clk24": clock source is CLK1-CLK24, respectively
The following two properties are deprecated.  rx-clock has been replaced
with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
Drivers that currently use the deprecated properties should continue to
do so, in order to support older device trees, but they should be updated
to check for the new properties first.
- rx-clock : represents the UCC receive clock source.
  0x00 : clock source is disabled;
  0x1~0x10 : clock source is BRG1~BRG16 respectively;
  0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
- tx-clock: represents the UCC transmit clock source;
  0x00 : clock source is disabled;
  0x1~0x10 : clock source is BRG1~BRG16 respectively;
  0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.

Required properties for network device_type:
- mac-address : list of bytes representing the ethernet address.
- phy-handle : The phandle for the PHY connected to this controller.

Recommended properties:
- phy-connection-type : a string naming the controller/PHY interface type,
  i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
  Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
  "tbi", or "rtbi".

Example:
	ucc@2000 {
		device_type = "network";
		compatible = "ucc_geth";
		cell-index = <1>;
		reg = <2000 200>;
		interrupts = <a0 0>;
		interrupt-parent = <700>;
		mac-address = [ 00 04 9f 00 23 23 ];
		rx-clock = "none";
		tx-clock = "clk9";
		phy-handle = <212000>;
		phy-connection-type = "gmii";
		pio-handle = <140001>;
	};


code:
Freescale QUICC Engine USB Controller

Required properties:
- compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb".
- reg : the first two cells should contain usb registers location and
  length, the next two two cells should contain PRAM location and
  length.
- interrupts : should contain USB interrupt.
- fsl,fullspeed-clock : specifies the full speed USB clock source:
  "none": clock source is disabled
  "brg1" through "brg16": clock source is BRG1-BRG16, respectively
  "clk1" through "clk24": clock source is CLK1-CLK24, respectively
- fsl,lowspeed-clock : specifies the low speed USB clock source:
  "none": clock source is disabled
  "brg1" through "brg16": clock source is BRG1-BRG16, respectively
  "clk1" through "clk24": clock source is CLK1-CLK24, respectively
- hub-power-budget : USB power budget for the root hub, in mA.
- gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP,
  USBRN, SPEED (optional), and POWER (optional).

Example:

usb@6c0 {
	compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb";
	reg = <0x6c0 0x40 0x8b00 0x100>;
	interrupts = <11>;
	interrupt-parent = <&qeic>;
	fsl,fullspeed-clock = "clk21";
	gpios = <&qe_pio_b  2 0 /* USBOE */
		 &qe_pio_b  3 0 /* USBTP */
		 &qe_pio_b  8 0 /* USBTN */
		 &qe_pio_b  9 0 /* USBRP */
		 &qe_pio_b 11 0 /* USBRN */
		 &qe_pio_e 20 0 /* SPEED */
		 &qe_pio_e 21 0 /* POWER */>;
};


code:
* Serial

Currently defined compatibles:
- fsl,cpm1-smc-uart
- fsl,cpm2-smc-uart
- fsl,cpm1-scc-uart
- fsl,cpm2-scc-uart
- fsl,qe-uart

Modem control lines connected to GPIO controllers are listed in the gpios
property as described in booting-without-of.txt, section IX.1 in the following
order:

CTS, RTS, DCD, DSR, DTR, and RI.

The gpios property is optional and can be left out when control lines are
not used.

Example:

	serial@11a00 {
		device_type = "serial";
		compatible = "fsl,mpc8272-scc-uart",
			     "fsl,cpm2-scc-uart";
		reg = <11a00 20 8000 100>;
		interrupts = <28 8>;
		interrupt-parent = <&PIC>;
		fsl,cpm-brg = <1>;
		fsl,cpm-command = <00800000>;
		gpios = <&gpio_c 15 0
			 &gpio_d 29 0>;
	};


code:
* Serial

Required Properties:
compatible : must be "fsl,<chip>-ucc-uart". For t1040, must be
"fsl,t1040-ucc-uart".
port-number : port number of UCC-UART
tx/rx-clock-name : should be "brg1"-"brg16" for internal clock source,
		   should be "clk1"-"clk28" for external clock source.

Example:

	ucc_serial: ucc@2200 {
		compatible = "fsl,t1040-ucc-uart";
		port-number = <0>;
		rx-clock-name = "brg2";
		tx-clock-name = "brg2";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/fsl,layerscape-dcfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Layerscape Device Configuration Unit

maintainers:
  - Shawn Guo <shawnguo@kernel.org>
  - Li Yang <leoyang.li@nxp.com>

description: |
  DCFG is the device configuration unit, that provides general purpose
  configuration and status for the device. Such as setting the secondary
  core start address and release the secondary core from holdoff and
  startup.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - fsl,ls1012a-dcfg
              - fsl,ls1021a-dcfg
              - fsl,ls1043a-dcfg
              - fsl,ls1046a-dcfg
              - fsl,ls1088a-dcfg
              - fsl,ls2080a-dcfg
              - fsl,lx2160a-dcfg
          - const: syscon

      - items:
          - enum:
              - fsl,ls1028a-dcfg
          - const: syscon
          - const: simple-mfd

  reg:
    maxItems: 1

  little-endian: true
  big-endian: true

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  ranges: true

patternProperties:
  "^clock-controller@[0-9a-z]+$":
    $ref: /schemas/clock/fsl,flexspi-clock.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    syscon@1ee0000 {
        compatible = "fsl,ls1021a-dcfg", "syscon";
        reg = <0x1ee0000 0x10000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/fsl/fsl,layerscape-scfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Layerscape Supplemental Configuration Unit

maintainers:
  - Shawn Guo <shawnguo@kernel.org>
  - Li Yang <leoyang.li@nxp.com>

description: |
  SCFG is the supplemental configuration unit, that provides SoC specific
  configuration and status registers for the chip. Such as getting PEX port
  status.

properties:
  compatible:
    items:
      - enum:
          - fsl,ls1012a-scfg
          - fsl,ls1021a-scfg
          - fsl,ls1028a-scfg
          - fsl,ls1043a-scfg
          - fsl,ls1046a-scfg
      - const: syscon

  reg:
    maxItems: 1

  little-endian: true
  big-endian: true

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  ranges: true

patternProperties:
  "^interrupt-controller@[a-z0-9]+$":
    $ref: /schemas/interrupt-controller/fsl,ls-extirq.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    syscon@1570000 {
        compatible = "fsl,ls1021a-scfg", "syscon";
        reg = <0x1570000 0x10000>;
    };


code:
* Global Utilities Block

The global utilities block controls power management, I/O device
enabling, power-on-reset configuration monitoring, general-purpose
I/O signal configuration, alternate function selection for multiplexed
signals, and clock control.

Required properties:

 - compatible : Should define the compatible device type for
   global-utilities.
   Possible compatibles:
	"fsl,qoriq-device-config-1.0"
	"fsl,qoriq-device-config-2.0"
	"fsl,<chip>-device-config"
	"fsl,<chip>-guts"
 - reg : Offset and length of the register set for the device.

Recommended properties:

 - fsl,has-rstcr : Indicates that the global utilities register set
   contains a functioning "reset control register" (i.e. the board
   is wired to reset upon setting the HRESET_REQ bit in this register).

 - fsl,liodn-bits : Indicates the number of defined bits in the LIODN
   registers, for those SOCs that have a PAMU device.

 - little-endian : Indicates that the global utilities block is little
   endian. The default is big endian.

Examples:
	global-utilities@e0000 {	/* global utilities block */
		compatible = "fsl,mpc8548-guts";
		reg = <e0000 1000>;
		fsl,has-rstcr;
	};

	guts: global-utilities@e0000 {
		compatible = "fsl,qoriq-device-config-1.0";
		reg = <0xe0000 0xe00>;
		fsl,has-rstcr;
		#sleep-cells = <1>;
		fsl,liodn-bits = <12>;
	};


code:
QorIQ DPAA Queue Manager Portals Device Tree Binding

Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.

CONTENTS

	- QMan Portal
	- Example

QMan Portal Node

Portals are memory mapped interfaces to QMan that allow low-latency, lock-less
interaction by software running on processor cores, accelerators and network
interfaces with the QMan

PROPERTIES

- compatible
	Usage:		Required
	Value type:	<stringlist>
	Definition:	Must include "fsl,qman-portal-<hardware revision>"
			May include "fsl,<SoC>-qman-portal" or "fsl,qman-portal"

- reg
	Usage:		Required
	Value type:	<prop-encoded-array>
	Definition:	Two regions. The first is the cache-enabled region of
			the portal. The second is the cache-inhibited region of
			the portal

- interrupts
	Usage:		Required
	Value type:	<prop-encoded-array>
	Definition:	Standard property

- fsl,liodn
	Usage:		See pamu.txt
	Value type:	<prop-encoded-array>
	Definition:	Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN
			(FLIODN)

- fsl,iommu-parent
	Usage:		See pamu.txt
	Value type:	<phandle>
	Definition:	PAMU property used for dynamic LIODN assignment

	For additional details about the PAMU/LIODN binding(s) see pamu.txt

- cell-index
	Usage:		Required
	Value type:	<u32>
	Definition:	The hardware index of the channel. This can also be
			determined by dividing any of the channel's 8 work queue
			IDs by 8

In addition to these properties the qman-portals should have sub-nodes to
represent the HW devices/portals that are connected to the software portal
described here

The currently supported sub-nodes are:
	* fman0
	* fman1
	* pme
	* crypto

These subnodes should have the following properties:

- fsl,liodn
	Usage:		See pamu.txt
	Value type:	<prop-encoded-array>
	Definition:	PAMU property used for static LIODN assignment

- fsl,iommu-parent
	Usage:		See pamu.txt
	Value type:	<phandle>
	Definition:	PAMU property used for dynamic LIODN assignment

- dev-handle
	Usage:		Required
	Value type:	<phandle>
	Definition:	The phandle to the particular hardware device that this
			portal is connected to.

EXAMPLE

The example below shows a (P4080) QMan portals container/bus node with two portals

	qman-portals@ff4200000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0 0xf 0xf4200000 0x200000>;

		qman-portal@0 {
			compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
			reg = <0 0x4000>, <0x100000 0x1000>;
			interrupts = <104 2 0 0>;
			fsl,liodn = <1 2>;
			fsl,qman-channel-id = <0>;

			fman0 {
				fsl,liodn = <0x21>;
				dev-handle = <&fman0>;
			};
			fman1 {
				fsl,liodn = <0xa1>;
				dev-handle = <&fman1>;
			};
			crypto {
				fsl,liodn = <0x41 0x66>;
				dev-handle = <&crypto>;
			};
		};
		qman-portal@4000 {
			compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
			reg = <0x4000 0x4000>, <0x101000 0x1000>;
			interrupts = <106 2 0 0>;
			fsl,liodn = <3 4>;
			cell-index = <1>;

			fman0 {
				fsl,liodn = <0x22>;
				dev-handle = <&fman0>;
			};
			fman1 {
				fsl,liodn = <0xa2>;
				dev-handle = <&fman1>;
			};
			crypto {
				fsl,liodn = <0x42 0x67>;
				dev-handle = <&crypto>;
			};
		};
	};


code:
QorIQ DPAA Queue Manager Device Tree Binding

Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.

CONTENTS

	- QMan Node
	- QMan Private Memory Nodes
	- Example

QMan Node

The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan
supports queuing and QoS scheduling of frames to CPUs, network interfaces and
DPAA logic modules, maintains packet ordering within flows. Besides providing
flow-level queuing, is also responsible for congestion management functions such
as RED/WRED, congestion notifications and tail discards. This binding covers the
CCSR space programming model

PROPERTIES

- compatible
	Usage:		Required
	Value type:	<stringlist>
	Definition:	Must include "fsl,qman"
			May include "fsl,<SoC>-qman"

- reg
	Usage:		Required
	Value type:	<prop-encoded-array>
	Definition:	Registers region within the CCSR address space

The QMan revision information is located in the QMAN_IP_REV_1/2 registers which
are located at offsets 0xbf8 and 0xbfc

- interrupts
	Usage:		Required
	Value type:	<prop-encoded-array>
	Definition:	Standard property. The error interrupt

- fsl,qman-portals
	Usage:		Required
	Value type:	<phandle>
	Definition:	Phandle to this QMan instance's portals

- fsl,liodn
	Usage:		See pamu.txt
	Value type:	<prop-encoded-array>
	Definition:	PAMU property used for static LIODN assignment

- fsl,iommu-parent
	Usage:		See pamu.txt
	Value type:	<phandle>
	Definition:	PAMU property used for dynamic LIODN assignment

	For additional details about the PAMU/LIODN binding(s) see pamu.txt

- clocks
	Usage:		See clock-bindings.txt and qoriq-clock.txt
	Value type:	<prop-encoded-array>
	Definition:	Reference input clock. Its frequency is half of the
			platform clock
- memory-regions
	Usage:		Required for ARM
	Value type:	<phandle array>
	Definition:	List of phandles referencing the QMan private memory
			nodes (described below). The qman-fqd node must be
			first followed by qman-pfdr node. Only used on ARM

Devices connected to a QMan instance via Direct Connect Portals (DCP) must link
to the respective QMan instance

- fsl,qman
	Usage:		Required
	Value type:	<prop-encoded-array>
	Description:	List of phandle and DCP index pairs, to the QMan instance
			to which this device is connected via the DCP

QMan Private Memory Nodes

QMan requires two contiguous range of physical memory used for the backing store
for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR).
This memory is reserved/allocated as a node under the /reserved-memory node.

For additional details about reserved memory regions see reserved-memory.txt

The QMan FQD memory node must be named "qman-fqd"

PROPERTIES

- compatible
	Usage:		required
	Value type:	<stringlist>
	Definition:	PPC platforms: Must include "fsl,qman-fqd"
			ARM platforms: Must include "shared-dma-pool"
				       as well as the "no-map" property

The QMan PFDR memory node must be named "qman-pfdr"

PROPERTIES

- compatible
	Usage:		required
	Value type:	<stringlist>
	Definition:	PPC platforms: Must include "fsl,qman-pfdr"
			ARM platforms: Must include "shared-dma-pool"
				       as well as the "no-map" property

The following constraints are relevant to the FQD and PFDR private memory:
	- The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
	  1 GiB
	- The alignment must be a muliptle of the memory size

The size of the FQD and PFDP must be chosen by observing the hardware features
configured via the Reset Configuration Word (RCW) and that are relevant to a
specific board (e.g. number of MAC(s) pinned-out, number of offline/host command
FMan ports, etc.). The size configured in the DT must reflect the hardware
capabilities and not the specific needs of an application

For additional details about reserved memory regions see reserved-memory.txt

EXAMPLE

The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		qman_fqd: qman-fqd {
			compatible = "shared-dma-pool";
			size = <0 0x400000>;
			alignment = <0 0x400000>;
			no-map;
		};
		qman_pfdr: qman-pfdr {
			compatible = "shared-dma-pool";
			size = <0 0x2000000>;
			alignment = <0 0x2000000>;
			no-map;
		};
	};

The example below shows a (P4080) QMan CCSR-space node

	qportals: qman-portals@ff4200000 {
		...
	};

	clockgen: global-utilities@e1000 {
		...
		sysclk: sysclk {
			...
		};
		...
		platform_pll: platform-pll@c00 {
			#clock-cells = <1>;
			reg = <0xc00 0x4>;
			compatible = "fsl,qoriq-platform-pll-1.0";
			clocks = <&sysclk>;
			clock-output-names = "platform-pll", "platform-pll-div2";
		};
		...
	};

	crypto@300000 {
		...
		fsl,qman = <&qman, 2>;
		...
	};

	qman: qman@318000 {
		compatible = "fsl,qman";
		reg = <0x318000 0x1000>;
		interrupts = <16 2 1 3>
		fsl,liodn = <0x16>;
		fsl,qman-portals = <&qportals>;
		memory-region = <&qman_fqd &qman_pfdr>;
		clocks = <&platform_pll 1>;
	};

	fman@400000 {
		...
		fsl,qman = <&qman, 0>;
		...
	};


code:
* Run Control and Power Management
-------------------------------------------
The RCPM performs all device-level tasks associated with device run control
and power management.

Required properites:
  - reg : Offset and length of the register set of the RCPM block.
  - #fsl,rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
	fsl,rcpm-wakeup property.
  - compatible : Must contain a chip-specific RCPM block compatible string
	and (if applicable) may contain a chassis-version RCPM compatible
	string. Chip-specific strings are of the form "fsl,<chip>-rcpm",
	such as:
	* "fsl,p2041-rcpm"
	* "fsl,p5020-rcpm"
	* "fsl,t4240-rcpm"

	Chassis-version strings are of the form "fsl,qoriq-rcpm-<version>",
	such as:
	* "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
	* "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
	* "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
	* "fsl,qoriq-rcpm-2.1+": for chassis 2.1+ rcpm

All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.
Chassis Version		Example Chips
---------------		-------------------------------
1.0				p4080, p5020, p5040, p2041, p3041
2.0				t4240, b4860, b4420
2.1				t1040,
2.1+				ls1021a, ls1012a, ls1043a, ls1046a

Optional properties:
 - little-endian : RCPM register block is Little Endian. Without it RCPM
   will be Big Endian (default case).

Example:
The RCPM node for T4240:
	rcpm: global-utilities@e2000 {
		compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
		reg = <0xe2000 0x1000>;
		#fsl,rcpm-wakeup-cells = <2>;
	};

* Freescale RCPM Wakeup Source Device Tree Bindings
-------------------------------------------
Required fsl,rcpm-wakeup property should be added to a device node if the device
can be used as a wakeup source.

  - fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR
	register cells. The number of IPPDEXPCR register cells is defined in
	"#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is
	the bit mask that should be set in IPPDEXPCR0, and the second register
	cell is for IPPDEXPCR1, and so on.

	Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a
	mechanism for keeping certain blocks awake during STANDBY and MEM, in
	order to use them as wake-up sources.

Example:
	lpuart0: serial@2950000 {
		compatible = "fsl,ls1021a-lpuart";
		reg = <0x0 0x2950000 0x0 0x1000>;
		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sysclk>;
		clock-names = "ipg";
		fsl,rcpm-wakeup = <&rcpm 0x0 0x40000000>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,aips-bus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX AHB to IP Bridge

maintainers:
  - Peng Fan <peng.fan@nxp.com>

description: |
  This particular peripheral is designed as the bridge between
  AHB bus and peripherals with the lower bandwidth IP Slave (IPS)
  buses.

select:
  properties:
    compatible:
      contains:
        const: fsl,aips-bus
  required:
    - compatible

properties:
  compatible:
    items:
      - const: fsl,aips-bus
      - const: simple-bus

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: true

examples:
  - |
    bus@30000000 {
      compatible = "fsl,aips-bus", "simple-bus";
      reg = <0x30000000 0x400000>;
      #address-cells = <1>;
      #size-cells = <1>;
      ranges;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8MM DISP blk-ctrl

maintainers:
  - Lucas Stach <l.stach@pengutronix.de>

description:
  The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
  the NoC and ensuring proper power sequencing of the display and MIPI CSI
  peripherals located in the DISP domain of the SoC.

properties:
  compatible:
    items:
      - const: fsl,imx8mm-disp-blk-ctrl
      - const: syscon

  reg:
    maxItems: 1

  '#power-domain-cells':
    const: 1

  power-domains:
    minItems: 5
    maxItems: 5

  power-domain-names:
    items:
      - const: bus
      - const: csi-bridge
      - const: lcdif
      - const: mipi-dsi
      - const: mipi-csi

  clocks:
    minItems: 10
    maxItems: 10

  clock-names:
    items:
      - const: csi-bridge-axi
      - const: csi-bridge-apb
      - const: csi-bridge-core
      - const: lcdif-axi
      - const: lcdif-apb
      - const: lcdif-pix
      - const: dsi-pclk
      - const: dsi-ref
      - const: csi-aclk
      - const: csi-pclk

required:
  - compatible
  - reg
  - power-domains
  - power-domain-names
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mm-clock.h>
    #include <dt-bindings/power/imx8mm-power.h>

    disp_blk_ctl: blk_ctrl@32e28000 {
      compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
      reg = <0x32e28000 0x100>;
      power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>,
                      <&pgc_mipi>, <&pgc_mipi>;
      power-domain-names = "bus", "csi-bridge", "lcdif",
                           "mipi-dsi", "mipi-csi";
      clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
               <&clk IMX8MM_CLK_DISP_APB_ROOT>,
               <&clk IMX8MM_CLK_CSI1_ROOT>,
               <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
               <&clk IMX8MM_CLK_DISP_APB_ROOT>,
               <&clk IMX8MM_CLK_DISP_ROOT>,
               <&clk IMX8MM_CLK_DSI_CORE>,
               <&clk IMX8MM_CLK_DSI_PHY_REF>,
               <&clk IMX8MM_CLK_CSI1_CORE>,
               <&clk IMX8MM_CLK_CSI1_PHY_REF>;
       clock-names = "csi-bridge-axi", "csi-bridge-apb", "csi-bridge-core",
                     "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
                     "dsi-ref", "csi-aclk", "csi-pclk";
       #power-domain-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8MM VPU blk-ctrl

maintainers:
  - Lucas Stach <l.stach@pengutronix.de>

description:
  The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
  the NoC and ensuring proper power sequencing of the VPU peripherals
  located in the VPU domain of the SoC.

properties:
  compatible:
    items:
      - const: fsl,imx8mm-vpu-blk-ctrl
      - const: syscon

  reg:
    maxItems: 1

  '#power-domain-cells':
    const: 1

  power-domains:
    maxItems: 4

  power-domain-names:
    maxItems: 4

  clocks:
    maxItems: 3

  clock-names:
    maxItems: 3

  interconnects:
    maxItems: 3

  interconnect-names:
    maxItems: 3

required:
  - compatible
  - reg
  - power-domains
  - power-domain-names
  - clocks
  - clock-names

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8mm-vpu-blk-ctrl
    then:
      properties:
        power-domains:
          items:
            - description: bus power domain
            - description: G1 decoder power domain
            - description: G2 decoder power domain
            - description: H1 encoder power domain

        power-domain-names:
          items:
            - const: bus
            - const: g1
            - const: g2
            - const: h1

        clocks:
          items:
            - description: G1 decoder clk
            - description: G2 decoder clk
            - description: H1 encoder clk

        clock-names:
          items:
            - const: g1
            - const: g2
            - const: h1

        interconnects:
          items:
            - description: G1 decoder interconnect
            - description: G2 decoder interconnect
            - description: H1 encoder power domain

        interconnect-names:
          items:
            - const: g1
            - const: g2
            - const: h1

  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8mp-vpu-blk-ctrl
    then:
      properties:
        power-domains:
          items:
            - description: bus power domain
            - description: G1 decoder power domain
            - description: G2 decoder power domain
            - description: VC8000E encoder power domain

        power-domain-names:
          items:
            - const: bus
            - const: g1
            - const: g2
            - const: vc8000e

        clocks:
          items:
            - description: G1 decoder clk
            - description: G2 decoder clk
            - description: VC8000E encoder clk

        clock-names:
          items:
            - const: g1
            - const: g2
            - const: vc8000e

        interconnects:
          items:
            - description: G1 decoder interconnect
            - description: G2 decoder interconnect
            - description: VC8000E encoder interconnect

        interconnect-names:
          items:
            - const: g1
            - const: g2
            - const: vc8000e

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mm-clock.h>
    #include <dt-bindings/power/imx8mm-power.h>

    vpu_blk_ctrl: blk-ctrl@38330000 {
      compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
      reg = <0x38330000 0x100>;
      power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
                      <&pgc_vpu_g2>, <&pgc_vpu_h1>;
      power-domain-names = "bus", "g1", "g2", "h1";
      clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
               <&clk IMX8MM_CLK_VPU_G2_ROOT>,
               <&clk IMX8MM_CLK_VPU_H1_ROOT>;
      clock-names = "g1", "g2", "h1";
      #power-domain-cells = <1>;
    };