code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for DRA7xx clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 */
&cm_core_aon_clocks {
	atl_clkin0_ck: clock-atl-clkin0 {
		#clock-cells = <0>;
		compatible = "ti,dra7-atl-clock";
		clock-output-names = "atl_clkin0_ck";
		clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
	};

	atl_clkin1_ck: clock-atl-clkin1 {
		#clock-cells = <0>;
		compatible = "ti,dra7-atl-clock";
		clock-output-names = "atl_clkin1_ck";
		clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
	};

	atl_clkin2_ck: clock-atl-clkin2 {
		#clock-cells = <0>;
		compatible = "ti,dra7-atl-clock";
		clock-output-names = "atl_clkin2_ck";
		clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
	};

	atl_clkin3_ck: clock-atl-clkin3 {
		#clock-cells = <0>;
		compatible = "ti,dra7-atl-clock";
		clock-output-names = "atl_clkin3_ck";
		clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
	};

	hdmi_clkin_ck: clock-hdmi-clkin {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "hdmi_clkin_ck";
		clock-frequency = <0>;
	};

	mlb_clkin_ck: clock-mlb-clkin {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "mlb_clkin_ck";
		clock-frequency = <0>;
	};

	mlbp_clkin_ck: clock-mlbp-clkin {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "mlbp_clkin_ck";
		clock-frequency = <0>;
	};

	pciesref_acs_clk_ck: clock-pciesref-acs {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "pciesref_acs_clk_ck";
		clock-frequency = <100000000>;
	};

	ref_clkin0_ck: clock-ref-clkin0 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "ref_clkin0_ck";
		clock-frequency = <0>;
	};

	ref_clkin1_ck: clock-ref-clkin1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "ref_clkin1_ck";
		clock-frequency = <0>;
	};

	ref_clkin2_ck: clock-ref-clkin2 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "ref_clkin2_ck";
		clock-frequency = <0>;
	};

	ref_clkin3_ck: clock-ref-clkin3 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "ref_clkin3_ck";
		clock-frequency = <0>;
	};

	rmii_clk_ck: clock-rmii {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "rmii_clk_ck";
		clock-frequency = <0>;
	};

	sdvenc_clkin_ck: clock-sdvenc-clkin {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "sdvenc_clkin_ck";
		clock-frequency = <0>;
	};

	secure_32k_clk_src_ck: clock-secure-32k-clk-src {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "secure_32k_clk_src_ck";
		clock-frequency = <32768>;
	};

	sys_clk32_crystal_ck: clock-sys-clk32-crystal {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "sys_clk32_crystal_ck";
		clock-frequency = <32768>;
	};

	sys_clk32_pseudo_ck: clock-sys-clk32-pseudo {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "sys_clk32_pseudo_ck";
		clocks = <&sys_clkin1>;
		clock-mult = <1>;
		clock-div = <610>;
	};

	virt_12000000_ck: clock-virt-12000000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_12000000_ck";
		clock-frequency = <12000000>;
	};

	virt_13000000_ck: clock-virt-13000000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_13000000_ck";
		clock-frequency = <13000000>;
	};

	virt_16800000_ck: clock-virt-16800000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_16800000_ck";
		clock-frequency = <16800000>;
	};

	virt_19200000_ck: clock-virt-19200000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_19200000_ck";
		clock-frequency = <19200000>;
	};

	virt_20000000_ck: clock-virt-20000000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_20000000_ck";
		clock-frequency = <20000000>;
	};

	virt_26000000_ck: clock-virt-26000000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_26000000_ck";
		clock-frequency = <26000000>;
	};

	virt_27000000_ck: clock-virt-27000000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_27000000_ck";
		clock-frequency = <27000000>;
	};

	virt_38400000_ck: clock-virt-38400000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_38400000_ck";
		clock-frequency = <38400000>;
	};

	sys_clkin2: clock-sys-clkin2 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "sys_clkin2";
		clock-frequency = <22579200>;
	};

	usb_otg_clkin_ck: clock-usb-otg-clkin {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "usb_otg_clkin_ck";
		clock-frequency = <0>;
	};

	video1_clkin_ck: clock-video1-clkin {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "video1_clkin_ck";
		clock-frequency = <0>;
	};

	video1_m2_clkin_ck: clock-video1-m2-clkin {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "video1_m2_clkin_ck";
		clock-frequency = <0>;
	};

	video2_clkin_ck: clock-video2-clkin {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "video2_clkin_ck";
		clock-frequency = <0>;
	};

	video2_m2_clkin_ck: clock-video2-m2-clkin {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "video2_m2_clkin_ck";
		clock-frequency = <0>;
	};

	dpll_abe_ck: clock@1e0 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-m4xen-clock";
		clock-output-names = "dpll_abe_ck";
		clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
		reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
	};

	dpll_abe_x2_ck: clock-dpll-abe-x2 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clock-output-names = "dpll_abe_x2_ck";
		clocks = <&dpll_abe_ck>;
	};

	dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_abe_m2x2_ck";
		clocks = <&dpll_abe_x2_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x01f0>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	abe_clk: clock-abe@108 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "abe_clk";
		clocks = <&dpll_abe_m2x2_ck>;
		ti,max-div = <4>;
		reg = <0x0108>;
		ti,index-power-of-two;
	};

	dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_abe_m2_ck";
		clocks = <&dpll_abe_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x01f0>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_abe_m3x2_ck";
		clocks = <&dpll_abe_x2_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x01f4>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_core_byp_mux";
		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
		ti,bit-shift = <23>;
		reg = <0x012c>;
	};

	dpll_core_ck: clock@120 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-core-clock";
		clock-output-names = "dpll_core_ck";
		clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
	};

	dpll_core_x2_ck: clock-dpll-core-x2 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clock-output-names = "dpll_core_x2_ck";
		clocks = <&dpll_core_ck>;
	};

	dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h12x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x013c>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "mpu_dpll_hs_clk_div";
		clocks = <&dpll_core_h12x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_mpu_ck: clock@160 {
		#clock-cells = <0>;
		compatible = "ti,omap5-mpu-dpll-clock";
		clock-output-names = "dpll_mpu_ck";
		clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
	};

	dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_mpu_m2_ck";
		clocks = <&dpll_mpu_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x0170>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	mpu_dclk_div: clock-mpu-dclk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "mpu_dclk_div";
		clocks = <&dpll_mpu_m2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "dsp_dpll_hs_clk_div";
		clocks = <&dpll_core_h12x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_dsp_byp_mux";
		clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
		ti,bit-shift = <23>;
		reg = <0x0240>;
	};

	dpll_dsp_ck: clock@234 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clock-output-names = "dpll_dsp_ck";
		clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
		reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
		assigned-clocks = <&dpll_dsp_ck>;
		assigned-clock-rates = <600000000>;
	};

	dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_dsp_m2_ck";
		clocks = <&dpll_dsp_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x0244>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
		assigned-clocks = <&dpll_dsp_m2_ck>;
		assigned-clock-rates = <600000000>;
	};

	iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "iva_dpll_hs_clk_div";
		clocks = <&dpll_core_h12x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_iva_byp_mux";
		clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
		ti,bit-shift = <23>;
		reg = <0x01ac>;
	};

	dpll_iva_ck: clock@1a0 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clock-output-names = "dpll_iva_ck";
		clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
		assigned-clocks = <&dpll_iva_ck>;
		assigned-clock-rates = <1165000000>;
	};

	dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_iva_m2_ck";
		clocks = <&dpll_iva_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x01b0>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
		assigned-clocks = <&dpll_iva_m2_ck>;
		assigned-clock-rates = <388333334>;
	};

	iva_dclk: clock-iva-dclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "iva_dclk";
		clocks = <&dpll_iva_m2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_gpu_byp_mux";
		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
		ti,bit-shift = <23>;
		reg = <0x02e4>;
	};

	dpll_gpu_ck: clock@2d8 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clock-output-names = "dpll_gpu_ck";
		clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
		reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
		assigned-clocks = <&dpll_gpu_ck>;
		assigned-clock-rates = <1277000000>;
	};

	dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_gpu_m2_ck";
		clocks = <&dpll_gpu_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x02e8>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
		assigned-clocks = <&dpll_gpu_m2_ck>;
		assigned-clock-rates = <425666667>;
	};

	dpll_core_m2_ck: clock-dpll-core-m2-8@130 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_m2_ck";
		clocks = <&dpll_core_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x0130>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "core_dpll_out_dclk_div";
		clocks = <&dpll_core_m2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_ddr_byp_mux";
		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
		ti,bit-shift = <23>;
		reg = <0x021c>;
	};

	dpll_ddr_ck: clock@210 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clock-output-names = "dpll_ddr_ck";
		clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
		reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
	};

	dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_ddr_m2_ck";
		clocks = <&dpll_ddr_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x0220>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_gmac_byp_mux";
		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
		ti,bit-shift = <23>;
		reg = <0x02b4>;
	};

	dpll_gmac_ck: clock@2a8 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clock-output-names = "dpll_gmac_ck";
		clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
		reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
	};

	dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_gmac_m2_ck";
		clocks = <&dpll_gmac_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x02b8>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	video2_dclk_div: clock-video2-dclk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "video2_dclk_div";
		clocks = <&video2_m2_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	video1_dclk_div: clock-video1-dclk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "video1_dclk_div";
		clocks = <&video1_m2_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	hdmi_dclk_div: clock-hdmi-dclk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "hdmi_dclk_div";
		clocks = <&hdmi_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "per_dpll_hs_clk_div";
		clocks = <&dpll_abe_m3x2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "usb_dpll_hs_clk_div";
		clocks = <&dpll_abe_m3x2_ck>;
		clock-mult = <1>;
		clock-div = <3>;
	};

	eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "eve_dpll_hs_clk_div";
		clocks = <&dpll_core_h12x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_eve_byp_mux";
		clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
		ti,bit-shift = <23>;
		reg = <0x0290>;
	};

	dpll_eve_ck: clock@284 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clock-output-names = "dpll_eve_ck";
		clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
		reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
	};

	dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_eve_m2_ck";
		clocks = <&dpll_eve_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x0294>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	eve_dclk_div: clock-eve-dclk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "eve_dclk_div";
		clocks = <&dpll_eve_m2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h13x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x0140>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h14x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x0144>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h22x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x0154>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h23x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x0158>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h24x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x015c>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clock-output-names = "dpll_ddr_x2_ck";
		clocks = <&dpll_ddr_ck>;
	};

	dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_ddr_h11x2_ck";
		clocks = <&dpll_ddr_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x0228>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_dsp_x2_ck: clock-dpll-dsp-x2 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clock-output-names = "dpll_dsp_x2_ck";
		clocks = <&dpll_dsp_ck>;
	};

	dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_dsp_m3x2_ck";
		clocks = <&dpll_dsp_x2_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x0248>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
		assigned-clocks = <&dpll_dsp_m3x2_ck>;
		assigned-clock-rates = <400000000>;
	};

	dpll_gmac_x2_ck: clock-dpll-gmac-x2 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clock-output-names = "dpll_gmac_x2_ck";
		clocks = <&dpll_gmac_ck>;
	};

	dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_gmac_h11x2_ck";
		clocks = <&dpll_gmac_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x02c0>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_gmac_h12x2_ck";
		clocks = <&dpll_gmac_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x02c4>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_gmac_h13x2_ck";
		clocks = <&dpll_gmac_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x02c8>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_gmac_m3x2_ck";
		clocks = <&dpll_gmac_x2_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x02bc>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	gmii_m_clk_div: clock-gmii-m-clk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "gmii_m_clk_div";
		clocks = <&dpll_gmac_h11x2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	hdmi_clk2_div: clock-hdmi-clk2-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "hdmi_clk2_div";
		clocks = <&hdmi_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	hdmi_div_clk: clock-hdmi-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "hdmi_div_clk";
		clocks = <&hdmi_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	l3_iclk_div: clock-l3-iclk-div-4@100 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "l3_iclk_div";
		ti,max-div = <2>;
		ti,bit-shift = <4>;
		reg = <0x0100>;
		clocks = <&dpll_core_h12x2_ck>;
		ti,index-power-of-two;
	};

	l4_root_clk_div: clock-l4-root-clk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "l4_root_clk_div";
		clocks = <&l3_iclk_div>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	video1_clk2_div: clock-video1-clk2-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "video1_clk2_div";
		clocks = <&video1_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	video1_div_clk: clock-video1-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "video1_div_clk";
		clocks = <&video1_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	video2_clk2_div: clock-video2-clk2-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "video2_clk2_div";
		clocks = <&video2_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	video2_div_clk: clock-video2-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "video2_div_clk";
		clocks = <&video2_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dummy_ck: clock-dummy {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "dummy_ck";
		clock-frequency = <0>;
	};
};
&prm_clocks {
	sys_clkin1: clock-sys-clkin1@110 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "sys_clkin1";
		clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
		reg = <0x0110>;
		ti,index-starts-at-one;
	};

	abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "abe_dpll_sys_clk_mux";
		clocks = <&sys_clkin1>, <&sys_clkin2>;
		reg = <0x0118>;
	};

	abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "abe_dpll_bypass_clk_mux";
		clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
		reg = <0x0114>;
	};

	abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "abe_dpll_clk_mux";
		clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
		reg = <0x010c>;
	};

	abe_24m_fclk: clock-abe-24m@11c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "abe_24m_fclk";
		clocks = <&dpll_abe_m2x2_ck>;
		reg = <0x011c>;
		ti,dividers = <8>, <16>;
	};

	aess_fclk: clock-aess@178 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "aess_fclk";
		clocks = <&abe_clk>;
		reg = <0x0178>;
		ti,max-div = <2>;
	};

	abe_giclk_div: clock-abe-giclk-div@174 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "abe_giclk_div";
		clocks = <&aess_fclk>;
		reg = <0x0174>;
		ti,max-div = <2>;
	};

	abe_lp_clk_div: clock-abe-lp-clk-div@1d8 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "abe_lp_clk_div";
		clocks = <&dpll_abe_m2x2_ck>;
		reg = <0x01d8>;
		ti,dividers = <16>, <32>;
	};

	abe_sys_clk_div: clock-abe-sys-clk-div@120 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "abe_sys_clk_div";
		clocks = <&sys_clkin1>;
		reg = <0x0120>;
		ti,max-div = <2>;
	};

	adc_gfclk_mux: clock-adc-gfclk-mux@1dc {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "adc_gfclk_mux";
		clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
		reg = <0x01dc>;
	};

	sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "sys_clk1_dclk_div";
		clocks = <&sys_clkin1>;
		ti,max-div = <64>;
		reg = <0x01c8>;
		ti,index-power-of-two;
	};

	sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "sys_clk2_dclk_div";
		clocks = <&sys_clkin2>;
		ti,max-div = <64>;
		reg = <0x01cc>;
		ti,index-power-of-two;
	};

	per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "per_abe_x1_dclk_div";
		clocks = <&dpll_abe_m2_ck>;
		ti,max-div = <64>;
		reg = <0x01bc>;
		ti,index-power-of-two;
	};

	dsp_gclk_div: clock-dsp-gclk-div@18c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dsp_gclk_div";
		clocks = <&dpll_dsp_m2_ck>;
		ti,max-div = <64>;
		reg = <0x018c>;
		ti,index-power-of-two;
	};

	gpu_dclk: clock-gpu-dclk@1a0 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "gpu_dclk";
		clocks = <&dpll_gpu_m2_ck>;
		ti,max-div = <64>;
		reg = <0x01a0>;
		ti,index-power-of-two;
	};

	emif_phy_dclk_div: clock-emif-phy-dclk-div@190 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "emif_phy_dclk_div";
		clocks = <&dpll_ddr_m2_ck>;
		ti,max-div = <64>;
		reg = <0x0190>;
		ti,index-power-of-two;
	};

	gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "gmac_250m_dclk_div";
		clocks = <&dpll_gmac_m2_ck>;
		ti,max-div = <64>;
		reg = <0x019c>;
		ti,index-power-of-two;
	};

	gmac_main_clk: clock-gmac-main {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "gmac_main_clk";
		clocks = <&gmac_250m_dclk_div>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "l3init_480m_dclk_div";
		clocks = <&dpll_usb_m2_ck>;
		ti,max-div = <64>;
		reg = <0x01ac>;
		ti,index-power-of-two;
	};

	usb_otg_dclk_div: clock-usb-otg-dclk-div@184 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "usb_otg_dclk_div";
		clocks = <&usb_otg_clkin_ck>;
		ti,max-div = <64>;
		reg = <0x0184>;
		ti,index-power-of-two;
	};

	sata_dclk_div: clock-sata-dclk-div@1c0 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "sata_dclk_div";
		clocks = <&sys_clkin1>;
		ti,max-div = <64>;
		reg = <0x01c0>;
		ti,index-power-of-two;
	};

	pcie2_dclk_div: clock-pcie2-dclk-div@1b8 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "pcie2_dclk_div";
		clocks = <&dpll_pcie_ref_m2_ck>;
		ti,max-div = <64>;
		reg = <0x01b8>;
		ti,index-power-of-two;
	};

	pcie_dclk_div: clock-pcie-dclk-div@1b4 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "pcie_dclk_div";
		clocks = <&apll_pcie_m2_ck>;
		ti,max-div = <64>;
		reg = <0x01b4>;
		ti,index-power-of-two;
	};

	emu_dclk_div: clock-emu-dclk-div@194 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "emu_dclk_div";
		clocks = <&sys_clkin1>;
		ti,max-div = <64>;
		reg = <0x0194>;
		ti,index-power-of-two;
	};

	secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "secure_32k_dclk_div";
		clocks = <&secure_32k_clk_src_ck>;
		ti,max-div = <64>;
		reg = <0x01c4>;
		ti,index-power-of-two;
	};

	clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "clkoutmux0_clk_mux";
		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
		reg = <0x0158>;
	};

	clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "clkoutmux1_clk_mux";
		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
		reg = <0x015c>;
	};

	clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "clkoutmux2_clk_mux";
		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
		reg = <0x0160>;
	};

	custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "custefuse_sys_gfclk_div";
		clocks = <&sys_clkin1>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	eve_clk: clock-eve@180 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "eve_clk";
		clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
		reg = <0x0180>;
	};

	hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "hdmi_dpll_clk_mux";
		clocks = <&sys_clkin1>, <&sys_clkin2>;
		reg = <0x0164>;
	};

	mlb_clk: clock-mlb@134 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "mlb_clk";
		clocks = <&mlb_clkin_ck>;
		ti,max-div = <64>;
		reg = <0x0134>;
		ti,index-power-of-two;
	};

	mlbp_clk: clock-mlbp@130 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "mlbp_clk";
		clocks = <&mlbp_clkin_ck>;
		ti,max-div = <64>;
		reg = <0x0130>;
		ti,index-power-of-two;
	};

	per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "per_abe_x1_gfclk2_div";
		clocks = <&dpll_abe_m2_ck>;
		ti,max-div = <64>;
		reg = <0x0138>;
		ti,index-power-of-two;
	};

	timer_sys_clk_div: clock-timer-sys-clk-div@144 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "timer_sys_clk_div";
		clocks = <&sys_clkin1>;
		reg = <0x0144>;
		ti,max-div = <2>;
	};

	video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "video1_dpll_clk_mux";
		clocks = <&sys_clkin1>, <&sys_clkin2>;
		reg = <0x0168>;
	};

	video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "video2_dpll_clk_mux";
		clocks = <&sys_clkin1>, <&sys_clkin2>;
		reg = <0x016c>;
	};

	wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "wkupaon_iclk_mux";
		clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
		reg = <0x0108>;
	};
};

&cm_core_clocks {
	dpll_pcie_ref_ck: clock@200 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clock-output-names = "dpll_pcie_ref_ck";
		clocks = <&sys_clkin1>, <&sys_clkin1>;
		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
	};

	dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_pcie_ref_m2ldo_ck";
		clocks = <&dpll_pcie_ref_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x0210>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 {
		compatible = "ti,mux-clock";
		clock-output-names = "apll_pcie_in_clk_mux";
		clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
		#clock-cells = <0>;
		reg = <0x021c 0x4>;
		ti,bit-shift = <7>;
	};

	apll_pcie_ck: clock@21c {
		#clock-cells = <0>;
		compatible = "ti,dra7-apll-clock";
		clock-output-names = "apll_pcie_ck";
		clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
		reg = <0x021c>, <0x0220>;
	};

	optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c {
		compatible = "ti,divider-clock";
		clock-output-names = "optfclk_pciephy_div";
		clocks = <&apll_pcie_ck>;
		#clock-cells = <0>;
		reg = <0x021c>;
		ti,dividers = <2>, <1>;
		ti,bit-shift = <8>;
		ti,max-div = <2>;
	};

	apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "apll_pcie_clkvcoldo";
		clocks = <&apll_pcie_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "apll_pcie_clkvcoldo_div";
		clocks = <&apll_pcie_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	apll_pcie_m2_ck: clock-apll-pcie-m2 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "apll_pcie_m2_ck";
		clocks = <&apll_pcie_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_per_byp_mux";
		clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
		ti,bit-shift = <23>;
		reg = <0x014c>;
	};

	dpll_per_ck: clock@140 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clock-output-names = "dpll_per_ck";
		clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
	};

	dpll_per_m2_ck: clock-dpll-per-m2-8@150 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_m2_ck";
		clocks = <&dpll_per_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x0150>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "func_96m_aon_dclk_div";
		clocks = <&dpll_per_m2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_usb_byp_mux";
		clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
		ti,bit-shift = <23>;
		reg = <0x018c>;
	};

	dpll_usb_ck: clock@180 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-j-type-clock";
		clock-output-names = "dpll_usb_ck";
		clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
	};

	dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_usb_m2_ck";
		clocks = <&dpll_usb_ck>;
		ti,max-div = <127>;
		ti,autoidle-shift = <8>;
		reg = <0x0190>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_pcie_ref_m2_ck";
		clocks = <&dpll_pcie_ref_ck>;
		ti,max-div = <127>;
		ti,autoidle-shift = <8>;
		reg = <0x0210>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_per_x2_ck: clock-dpll-per-x2 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clock-output-names = "dpll_per_x2_ck";
		clocks = <&dpll_per_ck>;
	};

	dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_h11x2_ck";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x0158>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_h12x2_ck";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x015c>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_h13x2_ck";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x0160>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_h14x2_ck";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <63>;
		ti,autoidle-shift = <8>;
		reg = <0x0164>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_m2x2_ck";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x0150>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "dpll_usb_clkdcoldo";
		clocks = <&dpll_usb_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	func_128m_clk: clock-func-128m {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "func_128m_clk";
		clocks = <&dpll_per_h11x2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	func_12m_fclk: clock-func-12m-fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "func_12m_fclk";
		clocks = <&dpll_per_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <16>;
	};

	func_24m_clk: clock-func-24m {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "func_24m_clk";
		clocks = <&dpll_per_m2_ck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	func_48m_fclk: clock-func-48m-fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "func_48m_fclk";
		clocks = <&dpll_per_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	func_96m_fclk: clock-func-96m-fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "func_96m_fclk";
		clocks = <&dpll_per_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	l3init_60m_fclk: clock-l3init-60m@104 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "l3init_60m_fclk";
		clocks = <&dpll_usb_m2_ck>;
		reg = <0x0104>;
		ti,dividers = <1>, <8>;
	};

	clkout2_clk: clock-clkout2-8@6b0 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "clkout2_clk";
		clocks = <&clkoutmux2_clk_mux>;
		ti,bit-shift = <8>;
		reg = <0x06b0>;
	};

	l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "l3init_960m_gfclk";
		clocks = <&dpll_usb_clkdcoldo>;
		ti,bit-shift = <8>;
		reg = <0x06c0>;
	};

	usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "usb_phy1_always_on_clk32k";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x0640>;
	};

	usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "usb_phy2_always_on_clk32k";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x0688>;
	};

	usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "usb_phy3_always_on_clk32k";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x0698>;
	};

	gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "gpu_core_gclk_mux";
		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
		ti,bit-shift = <24>;
		reg = <0x1220>;
		assigned-clocks = <&gpu_core_gclk_mux>;
		assigned-clock-parents = <&dpll_gpu_m2_ck>;
	};

	gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "gpu_hyd_gclk_mux";
		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
		ti,bit-shift = <26>;
		reg = <0x1220>;
		assigned-clocks = <&gpu_hyd_gclk_mux>;
		assigned-clock-parents = <&dpll_gpu_m2_ck>;
	};

	l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "l3instr_ts_gclk_div";
		clocks = <&wkupaon_iclk_mux>;
		ti,bit-shift = <24>;
		reg = <0x0e50>;
		ti,dividers = <8>, <16>, <32>;
	};

	vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "vip1_gclk_mux";
		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
		ti,bit-shift = <24>;
		reg = <0x1020>;
	};

	vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "vip2_gclk_mux";
		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
		ti,bit-shift = <24>;
		reg = <0x1028>;
	};

	vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "vip3_gclk_mux";
		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
		ti,bit-shift = <24>;
		reg = <0x1030>;
	};
};

&cm_core_clockdomains {
	coreaon_clkdm: clock-coreaon-clkdm {
		compatible = "ti,clockdomain";
		clock-output-names = "coreaon_clkdm";
		clocks = <&dpll_usb_ck>;
	};
};

&scm_conf_clocks {
	dss_deshdcp_clk: clock-dss-deshdcp-0@558 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "dss_deshdcp_clk";
		clocks = <&l3_iclk_div>;
		ti,bit-shift = <0>;
		reg = <0x558>;
	};

       ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "ehrpwm0_tbclk";
		clocks = <&l4_root_clk_div>;
		ti,bit-shift = <20>;
		reg = <0x0558>;
	};

	ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "ehrpwm1_tbclk";
		clocks = <&l4_root_clk_div>;
		ti,bit-shift = <21>;
		reg = <0x0558>;
	};

	ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "ehrpwm2_tbclk";
		clocks = <&l4_root_clk_div>;
		ti,bit-shift = <22>;
		reg = <0x0558>;
	};

	sys_32k_ck: clock-sys-32k {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "sys_32k_ck";
		clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
		ti,bit-shift = <8>;
		reg = <0x6c4>;
	};
};

&cm_core_aon {
	mpu_cm: clock@300 {
		compatible = "ti,omap4-cm";
		clock-output-names = "mpu_cm";
		reg = <0x300 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x300 0x100>;

		mpu_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "mpu_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};

	};

	dsp1_cm: clock@400 {
		compatible = "ti,omap4-cm";
		clock-output-names = "dsp1_cm";
		reg = <0x400 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x400 0x100>;

		dsp1_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "dsp1_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};

	};

	ipu_cm: clock@500 {
		compatible = "ti,omap4-cm";
		clock-output-names = "ipu_cm";
		reg = <0x500 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x500 0x100>;

		ipu1_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "ipu1_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
			assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
			assigned-clock-parents = <&dpll_core_h22x2_ck>;
		};

		ipu_clkctrl: clock@50 {
			compatible = "ti,clkctrl";
			clock-output-names = "ipu_clkctrl";
			reg = <0x50 0x34>;
			#clock-cells = <2>;
		};

	};

	dsp2_cm: clock@600 {
		compatible = "ti,omap4-cm";
		clock-output-names = "dsp2_cm";
		reg = <0x600 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x600 0x100>;

		dsp2_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "dsp2_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};

	};

	rtc_cm: clock@700 {
		compatible = "ti,omap4-cm";
		clock-output-names = "rtc_cm";
		reg = <0x700 0x60>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x700 0x60>;

		rtc_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "rtc_clkctrl";
			reg = <0x20 0x28>;
			#clock-cells = <2>;
		};
	};

	vpe_cm: clock@760 {
		compatible = "ti,omap4-cm";
		clock-output-names = "vpe_cm";
		reg = <0x760 0xc>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x760 0xc>;

		vpe_clkctrl: clock@0 {
			compatible = "ti,clkctrl";
			clock-output-names = "vpe_clkctrl";
			reg = <0x0 0xc>;
			#clock-cells = <2>;
		};
	};

};

&cm_core {
	coreaon_cm: clock@600 {
		compatible = "ti,omap4-cm";
		clock-output-names = "coreaon_cm";
		reg = <0x600 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x600 0x100>;

		coreaon_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "coreaon_clkctrl";
			reg = <0x20 0x1c>;
			#clock-cells = <2>;
		};
	};

	l3main1_cm: clock@700 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l3main1_cm";
		reg = <0x700 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x700 0x100>;

		l3main1_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "l3main1_clkctrl";
			reg = <0x20 0x74>;
			#clock-cells = <2>;
		};

	};

	ipu2_cm: clock@900 {
		compatible = "ti,omap4-cm";
		clock-output-names = "ipu2_cm";
		reg = <0x900 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x900 0x100>;

		ipu2_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "ipu2_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};

	};

	dma_cm: clock@a00 {
		compatible = "ti,omap4-cm";
		clock-output-names = "dma_cm";
		reg = <0xa00 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xa00 0x100>;

		dma_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "dma_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};
	};

	emif_cm: clock@b00 {
		compatible = "ti,omap4-cm";
		clock-output-names = "emif_cm";
		reg = <0xb00 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xb00 0x100>;

		emif_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "emif_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};
	};

	atl_cm: clock@c00 {
		compatible = "ti,omap4-cm";
		clock-output-names = "atl_cm";
		reg = <0xc00 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xc00 0x100>;

		atl_clkctrl: clock@0 {
			compatible = "ti,clkctrl";
			clock-output-names = "atl_clkctrl";
			reg = <0x0 0x4>;
			#clock-cells = <2>;
		};
	};

	l4cfg_cm: clock@d00 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l4cfg_cm";
		reg = <0xd00 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xd00 0x100>;

		l4cfg_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4cfg_clkctrl";
			reg = <0x20 0x84>;
			#clock-cells = <2>;
		};
	};

	l3instr_cm: clock@e00 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l3instr_cm";
		reg = <0xe00 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xe00 0x100>;

		l3instr_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "l3instr_clkctrl";
			reg = <0x20 0xc>;
			#clock-cells = <2>;
		};
	};

	iva_cm: clock@f00 {
		compatible = "ti,omap4-cm";
		clock-output-names = "iva_cm";
		reg = <0xf00 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xf00 0x100>;

		iva_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "iva_clkctrl";
			reg = <0x20 0xc>;
			#clock-cells = <2>;
		};
	};

	cam_cm: clock@1000 {
		compatible = "ti,omap4-cm";
		clock-output-names = "cam_cm";
		reg = <0x1000 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1000 0x100>;

		cam_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "cam_clkctrl";
			reg = <0x20 0x2c>;
			#clock-cells = <2>;
		};
	};

	dss_cm: clock@1100 {
		compatible = "ti,omap4-cm";
		clock-output-names = "dss_cm";
		reg = <0x1100 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1100 0x100>;

		dss_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "dss_clkctrl";
			reg = <0x20 0x14>;
			#clock-cells = <2>;
		};
	};

	gpu_cm: clock@1200 {
		compatible = "ti,omap4-cm";
		clock-output-names = "gpu_cm";
		reg = <0x1200 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1200 0x100>;

		gpu_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "gpu_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};
	};

	l3init_cm: clock@1300 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l3init_cm";
		reg = <0x1300 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1300 0x100>;

		l3init_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "l3init_clkctrl";
			reg = <0x20 0x6c>, <0xe0 0x14>;
			#clock-cells = <2>;
		};

		pcie_clkctrl: clock@b0 {
			compatible = "ti,clkctrl";
			clock-output-names = "pcie_clkctrl";
			reg = <0xb0 0xc>;
			#clock-cells = <2>;
		};

		gmac_clkctrl: clock@d0 {
			compatible = "ti,clkctrl";
			clock-output-names = "gmac_clkctrl";
			reg = <0xd0 0x4>;
			#clock-cells = <2>;
		};

	};

	l4per_cm: clock@1700 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l4per_cm";
		reg = <0x1700 0x300>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1700 0x300>;

		l4per_clkctrl: clock@28 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4per_clkctrl";
			reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
			#clock-cells = <2>;

			assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
			assigned-clock-parents = <&abe_24m_fclk>;
		};

		l4sec_clkctrl: clock@1a0 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4sec_clkctrl";
			reg = <0x1a0 0x2c>;
			#clock-cells = <2>;
		};

		l4per2_clkctrl: clock@c {
			compatible = "ti,clkctrl";
			clock-output-names = "l4per2_clkctrl";
			reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>;
			#clock-cells = <2>;
		};

		l4per3_clkctrl: clock@14 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4per3_clkctrl";
			reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
			#clock-cells = <2>;
		};
	};

};

&prm {
	wkupaon_cm: clock@1800 {
		compatible = "ti,omap4-cm";
		clock-output-names = "wkupaon_cm";
		reg = <0x1800 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1800 0x100>;

		wkupaon_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "wkupaon_clkctrl";
			reg = <0x20 0x6c>;
			#clock-cells = <2>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2019 Andreas Kemnade
 * based on works
 * Copyright 2016 Freescale Semiconductor, Inc.
 * and
 * Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd
 *
 * Netronix E60K02 board common.
 * This board is equipped with different SoCs and
 * found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and
 * the Tolino Shine 3 (with i.MX6SL)
 */
#include <dt-bindings/input/input.h>

/ {

	chosen {
		stdout-path = &uart1;
	};

	gpio_keys: gpio-keys {
		compatible = "gpio-keys";

		key-power {
			label = "Power";
			gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_POWER>;
			wakeup-source;
		};

		key-cover {
			label = "Cover";
			gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
			linux,code = <SW_LID>;
			linux,input-type = <EV_SW>;
			wakeup-source;
		};
	};

	leds: leds {
		compatible = "gpio-leds";

		led {
			label = "e60k02:white:on";
			gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "timer";
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	reg_wifi: regulator-wifi {
		compatible = "regulator-fixed";
		regulator-name = "SD3_SPWR";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	wifi_pwrseq: wifi_pwrseq {
		compatible = "mmc-pwrseq-simple";
		post-power-on-delay-ms = <20>;
		reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
	};
};

&i2c1 {
	clock-frequency = <100000>;
	status = "okay";

	lm3630a: backlight@36 {
		reg = <0x36>;
		compatible = "ti,lm3630a";
		enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;

		#address-cells = <1>;
		#size-cells = <0>;

		led@0 {
			reg = <0>;
			led-sources = <0>;
			label = "backlight_warm";
			default-brightness = <0>;
			max-brightness = <255>;
		};

		led@1 {
			reg = <1>;
			led-sources = <1>;
			label = "backlight_cold";
			default-brightness = <0>;
			max-brightness = <255>;
		};
	};
};

&i2c2 {
	clock-frequency = <100000>;
	status = "okay";

	touchscreen@24 {
		compatible = "cypress,tt21000";
		reg = <0x24>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_cyttsp5_gpio>;
		interrupt-parent = <&gpio5>;
		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
		reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
		vdd-supply = <&ldo5_reg>;
	};

	/* TODO: TPS65185 PMIC for E Ink at 0x68 */

};

&i2c3 {
	clock-frequency = <100000>;
	status = "okay";

	ricoh619: pmic@32 {
		compatible = "ricoh,rc5t619";
		reg = <0x32>;
		interrupt-parent = <&gpio5>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
		system-power-controller;

		regulators {
			dcdc1_reg: DCDC1 {
				regulator-name = "DCDC1";
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-max-microvolt = <900000>;
					regulator-suspend-min-microvolt = <900000>;
				};
			};

			/* Core3_3V3 */
			dcdc2_reg: DCDC2 {
				regulator-name = "DCDC2";
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-max-microvolt = <3300000>;
					regulator-suspend-min-microvolt = <3300000>;
				};
			};

			dcdc3_reg: DCDC3 {
				regulator-name = "DCDC3";
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-max-microvolt = <1140000>;
					regulator-suspend-min-microvolt = <1140000>;
				};
			};

			/* Core4_1V2 */
			dcdc4_reg: DCDC4 {
				regulator-name = "DCDC4";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-max-microvolt = <1140000>;
					regulator-suspend-min-microvolt = <1140000>;
				};
			};

			/* Core4_1V8 */
			dcdc5_reg: DCDC5 {
				regulator-name = "DCDC5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-max-microvolt = <1700000>;
					regulator-suspend-min-microvolt = <1700000>;
				};
			};

			/* IR_3V3 */
			ldo1_reg: LDO1  {
				regulator-name = "LDO1";
				regulator-boot-on;
			};

			/* Core1_3V3 */
			ldo2_reg: LDO2  {
				regulator-name = "LDO2";
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-max-microvolt = <3000000>;
					regulator-suspend-min-microvolt = <3000000>;
				};
			};

			/* Core5_1V2 */
			ldo3_reg: LDO3  {
				regulator-name = "LDO3";
				regulator-always-on;
				regulator-boot-on;
			};

			ldo4_reg: LDO4 {
				regulator-name = "LDO4";
				regulator-boot-on;
			};

			/* SPD_3V3 */
			ldo5_reg: LDO5 {
				regulator-name = "LDO5";
				regulator-always-on;
				regulator-boot-on;
			};

			/* DDR_0V6 */
			ldo6_reg: LDO6 {
				regulator-name = "LDO6";
				regulator-always-on;
				regulator-boot-on;
			};

			/* VDD_PWM */
			ldo7_reg: LDO7 {
				regulator-name = "LDO7";
				regulator-always-on;
				regulator-boot-on;
			};

			/* ldo_1v8 */
			ldo8_reg: LDO8 {
				regulator-name = "LDO8";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			ldo9_reg: LDO9 {
				regulator-name = "LDO9";
				regulator-boot-on;
			};

			ldo10_reg: LDO10 {
				regulator-name = "LDO10";
				regulator-boot-on;
			};

			ldortc1_reg: LDORTC1  {
				regulator-name = "LDORTC1";
				regulator-boot-on;
			};
		};
	};
};

&snvs_rtc {
	/* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */
	status = "disabled";
};

&uart1 {
	/* J4, through-hole */
	status = "okay";
};

&uart4 {
	/* TP198, next to J4, SMD pads */
	status = "okay";
};

&usdhc2 {
	non-removable;
	status = "okay";
};

&usdhc3 {
	vmmc-supply = <&reg_wifi>;
	mmc-pwrseq = <&wifi_pwrseq>;
	cap-power-off-card;
	non-removable;
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	disable-over-current;
	srp-disable;
	hnp-disable;
	adp-disable;
	status = "okay";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2021 Andreas Kemnade
 * based on works
 * Copyright 2016 Freescale Semiconductor, Inc.
 * and
 * Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd
 *
 * Netronix E70K02 board common.
 * This board is equipped with different SoCs and
 * found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and
 * the Tolino Shine 3 (with i.MX6SL)
 */
#include <dt-bindings/input/input.h>

/ {
	aliases {
		mmc0 = &usdhc1;
		mmc1 = &usdhc3;
	};

	chosen {
		stdout-path = &uart1;
	};

	gpio_keys: gpio-keys {
		compatible = "gpio-keys";

		key-power {
			label = "Power";
			gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_POWER>;
			wakeup-source;
		};

		key-cover {
			label = "Cover";
			gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
			linux,code = <SW_LID>;
			linux,input-type = <EV_SW>;
			wakeup-source;
		};

		key-pageup {
			label = "PageUp";
			gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_PAGEUP>;
		};

		key-pagedown {
			label = "PageDown";
			gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_PAGEDOWN>;
		};
	};

	leds: leds {
		compatible = "gpio-leds";

		led {
			label = "e70k02:white:on";
			gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "timer";
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	reg_wifi: regulator-wifi {
		compatible = "regulator-fixed";
		regulator-name = "SD3_SPWR";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	wifi_pwrseq: wifi-pwrseq {
		compatible = "mmc-pwrseq-simple";
		post-power-on-delay-ms = <20>;
		reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
	};
};

&i2c1 {
	clock-frequency = <100000>;
	status = "okay";

	lm3630a: backlight@36 {
		reg = <0x36>;
		compatible = "ti,lm3630a";
		enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;

		#address-cells = <1>;
		#size-cells = <0>;

		led@0 {
			reg = <0>;
			led-sources = <0>;
			label = "backlight_warm";
			default-brightness = <0>;
			max-brightness = <255>;
		};

		led@1 {
			reg = <1>;
			led-sources = <1>;
			label = "backlight_cold";
			default-brightness = <0>;
			max-brightness = <255>;
		};
	};

	/* TODO: KX122 acceleration sensor a 0x1e */

};

&i2c2 {
	clock-frequency = <100000>;
	status = "okay";

	/* TODO: CYTTSP5 touch controller at 0x24 */

	/* TODO: SY7636 PMIC for E Ink at 0x62 */

};

&i2c3 {
	clock-frequency = <100000>;
	status = "okay";

	ricoh619: pmic@32 {
		compatible = "ricoh,rc5t619";
		reg = <0x32>;
		interrupt-parent = <&gpio4>;
		interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
		system-power-controller;

		regulators {
			dcdc1_reg: DCDC1 {
				regulator-name = "DCDC1";
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-max-microvolt = <900000>;
					regulator-suspend-min-microvolt = <900000>;
				};
			};

			/* Core3_3V3 */
			dcdc2_reg: DCDC2 {
				regulator-name = "DCDC2";
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-max-microvolt = <3300000>;
					regulator-suspend-min-microvolt = <3300000>;
				};
			};

			dcdc3_reg: DCDC3 {
				regulator-name = "DCDC3";
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-max-microvolt = <1140000>;
					regulator-suspend-min-microvolt = <1140000>;
				};
			};

			/* Core4_1V2 */
			dcdc4_reg: DCDC4 {
				regulator-name = "DCDC4";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-max-microvolt = <1140000>;
					regulator-suspend-min-microvolt = <1140000>;
				};
			};

			/* Core4_1V8 */
			dcdc5_reg: DCDC5 {
				regulator-name = "DCDC5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-max-microvolt = <1700000>;
					regulator-suspend-min-microvolt = <1700000>;
				};
			};

			ldo1_reg: LDO1  {
				regulator-name = "LDO1";
				regulator-boot-on;
			};

			/* Core1_3V3 */
			ldo2_reg: LDO2  {
				regulator-name = "LDO2";
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-max-microvolt = <3000000>;
					regulator-suspend-min-microvolt = <3000000>;
				};
			};

			/* Core5_1V2 */
			ldo3_reg: LDO3  {
				regulator-name = "LDO3";
				regulator-always-on;
				regulator-boot-on;
			};

			ldo4_reg: LDO4 {
				regulator-name = "LDO4";
				regulator-boot-on;
			};

			/* SPD_3V3 */
			ldo5_reg: LDO5 {
				regulator-name = "LDO5";
				regulator-always-on;
				regulator-boot-on;
			};

			/* DDR_0V6 */
			ldo6_reg: LDO6 {
				regulator-name = "LDO6";
				regulator-always-on;
				regulator-boot-on;
			};

			/* VDD_PWM */
			ldo7_reg: LDO7 {
				regulator-name = "LDO7";
				regulator-boot-on;
			};

			/* ldo_1v8 */
			ldo8_reg: LDO8 {
				regulator-name = "LDO8";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
			};

			ldo9_reg: LDO9 {
				regulator-name = "LDO9";
				regulator-boot-on;
			};

			ldo10_reg: LDO10 {
				regulator-name = "LDO10";
				regulator-boot-on;
			};

			ldortc1_reg: LDORTC1  {
				regulator-name = "LDORTC1";
				regulator-boot-on;
			};
		};
	};
};

&snvs_rtc {
	/* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */
	status = "disabled";
};

&uart1 {
	status = "okay";
};

&usdhc1 {
	non-removable;
	no-1-8-v;
	status = "okay";
};

&usdhc3 {
	vmmc-supply = <&reg_wifi>;
	mmc-pwrseq = <&wifi_pwrseq>;
	cap-power-off-card;
	non-removable;
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	disable-over-current;
	srp-disable;
	hnp-disable;
	adp-disable;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2011-2012 Calxeda, Inc.
 */

/dts-v1/;

/* First 4KB has pen for secondary cores. */
/memreserve/ 0x00000000 0x0001000;

/ {
	model = "Calxeda ECX-2000";
	compatible = "calxeda,ecx-2000";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};

		cpu@1 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <1>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};

		cpu@2 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <2>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};

		cpu@3 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <3>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
	};

	memory@200000000 {
		name = "memory";
		device_type = "memory";
		reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
	};

	soc {
		ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;

		timer {
			compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; 			interrupts = <1 13 0xf08>,
				<1 14 0xf08>,
				<1 11 0xf08>,
				<1 10 0xf08>;
		};

		memory-controller@fff00000 {
			compatible = "calxeda,ecx-2000-ddr-ctrl";
			reg = <0xfff00000 0x1000>;
			interrupts = <0 91 4>;
		};

		intc: interrupt-controller@fff11000 {
			compatible = "arm,cortex-a15-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			interrupts = <1 9 0xf04>;
			reg = <0xfff11000 0x1000>,
			      <0xfff12000 0x2000>,
			      <0xfff14000 0x2000>,
			      <0xfff16000 0x2000>;
		};

		pmu {
			compatible = "arm,cortex-a9-pmu";
			interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
		};
	};
};

/include/ "ecx-common.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2011-2012 Calxeda, Inc.
 */

/ {
	chosen {
		bootargs = "console=ttyAMA0";
	};

	psci {
		compatible = "arm,psci";
		method = "smc";
		cpu_suspend = <0x84000002>;
		cpu_off = <0x84000004>;
		cpu_on = <0x84000006>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&intc>;

		sata@ffe08000 {
			compatible = "calxeda,hb-ahci";
			reg = <0xffe08000 0x10000>;
			interrupts = <0 83 4>;
			dma-coherent;
			calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
					     <&combophy0 1>, <&combophy0 2>,
					     <&combophy0 3>;
			calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
					    <&gpioh 7 1>;
			calxeda,led-order = <4 0 1 2 3>;
		};

		sdhci@ffe0e000 {
			compatible = "calxeda,hb-sdhci";
			reg = <0xffe0e000 0x1000>;
			interrupts = <0 90 4>;
			clocks = <&eclk>;
			status = "disabled";
		};

		ipc@fff20000 {
			compatible = "arm,pl320", "arm,primecell";
			reg = <0xfff20000 0x1000>;
			interrupts = <0 7 4>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		gpioe: gpio@fff30000 {
			#gpio-cells = <2>;
			compatible = "arm,pl061", "arm,primecell";
			gpio-controller;
			reg = <0xfff30000 0x1000>;
			interrupts = <0 14 4>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpiof: gpio@fff31000 {
			#gpio-cells = <2>;
			compatible = "arm,pl061", "arm,primecell";
			gpio-controller;
			reg = <0xfff31000 0x1000>;
			interrupts = <0 15 4>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpiog: gpio@fff32000 {
			#gpio-cells = <2>;
			compatible = "arm,pl061", "arm,primecell";
			gpio-controller;
			reg = <0xfff32000 0x1000>;
			interrupts = <0 16 4>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpioh: gpio@fff33000 {
			#gpio-cells = <2>;
			compatible = "arm,pl061", "arm,primecell";
			gpio-controller;
			reg = <0xfff33000 0x1000>;
			interrupts = <0 17 4>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		timer@fff34000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0xfff34000 0x1000>;
			interrupts = <0 18 4>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		rtc@fff35000 {
			compatible = "arm,pl031", "arm,primecell";
			reg = <0xfff35000 0x1000>;
			interrupts = <0 19 4>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		serial@fff36000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xfff36000 0x1000>;
			interrupts = <0 20 4>;
			clocks = <&pclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		smic@fff3a000 {
			compatible = "ipmi-smic";
			device_type = "ipmi";
			reg = <0xfff3a000 0x1000>;
			interrupts = <0 24 4>;
			reg-size = <4>;
			reg-spacing = <4>;
		};

		sregs@fff3c000 {
			compatible = "calxeda,hb-sregs";
			reg = <0xfff3c000 0x1000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				osc: oscillator {
					#clock-cells = <0>;
					compatible = "fixed-clock";
					clock-frequency = <33333000>;
				};

				ddrpll: ddrpll {
					#clock-cells = <0>;
					compatible = "calxeda,hb-pll-clock";
					clocks = <&osc>;
					reg = <0x108>;
				};

				a9pll: a9pll {
					#clock-cells = <0>;
					compatible = "calxeda,hb-pll-clock";
					clocks = <&osc>;
					reg = <0x100>;
				};

				a9periphclk: a9periphclk {
					#clock-cells = <0>;
					compatible = "calxeda,hb-a9periph-clock";
					clocks = <&a9pll>;
					reg = <0x104>;
				};

				a9bclk: a9bclk {
					#clock-cells = <0>;
					compatible = "calxeda,hb-a9bus-clock";
					clocks = <&a9pll>;
					reg = <0x104>;
				};

				emmcpll: emmcpll {
					#clock-cells = <0>;
					compatible = "calxeda,hb-pll-clock";
					clocks = <&osc>;
					reg = <0x10C>;
				};

				eclk: eclk {
					#clock-cells = <0>;
					compatible = "calxeda,hb-emmc-clock";
					clocks = <&emmcpll>;
					reg = <0x114>;
				};

				pclk: pclk {
					#clock-cells = <0>;
					compatible = "fixed-clock";
					clock-frequency = <150000000>;
				};
			};
		};

		dma@fff3d000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xfff3d000 0x1000>;
			interrupts = <0 92 4>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		ethernet@fff50000 {
			compatible = "calxeda,hb-xgmac";
			reg = <0xfff50000 0x1000>;
			interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
			dma-coherent;
		};

		ethernet@fff51000 {
			compatible = "calxeda,hb-xgmac";
			reg = <0xfff51000 0x1000>;
			interrupts = <0 80 4>, <0 81 4>, <0 82 4>;
			dma-coherent;
		};

		combophy0: combo-phy@fff58000 {
			compatible = "calxeda,hb-combophy";
			#phy-cells = <1>;
			reg = <0xfff58000 0x1000>;
			phydev = <5>;
		};

		combophy5: combo-phy@fff5d000 {
			compatible = "calxeda,hb-combophy";
			#phy-cells = <1>;
			reg = <0xfff5d000 0x1000>;
			phydev = <31>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Common devices used in different OMAP boards
 */

/ {
	elpida_ECB240ABACN: lpddr2 {
		compatible	= "elpida,ECB240ABACN","jedec,lpddr2-s4";
		density		= <2048>;
		io-width	= <32>;

		tRPab-min-tck	= <3>;
		tRCD-min-tck	= <3>;
		tWR-min-tck	= <3>;
		tRASmin-min-tck	= <3>;
		tRRD-min-tck	= <2>;
		tWTR-min-tck	= <2>;
		tXP-min-tck	= <2>;
		tRTP-min-tck	= <2>;
		tCKE-min-tck	= <3>;
		tCKESR-min-tck	= <3>;
		tFAW-min-tck	= <8>;

		timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
			compatible	= "jedec,lpddr2-timings";
			min-freq	= <10000000>;
			max-freq	= <400000000>;
			tRPab		= <21000>;
			tRCD		= <18000>;
			tWR		= <15000>;
			tRAS-min	= <42000>;
			tRRD		= <10000>;
			tWTR		= <7500>;
			tXP		= <7500>;
			tRTP		= <7500>;
			tCKESR		= <15000>;
			tDQSCK-max	= <5500>;
			tFAW		= <50000>;
			tZQCS		= <90000>;
			tZQCL		= <360000>;
			tZQinit		= <1000000>;
			tRAS-max-ns	= <70000>;
			tDQSCK-max-derated = <6000>;
		};

		timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
			compatible	= "jedec,lpddr2-timings";
			min-freq	= <10000000>;
			max-freq	= <200000000>;
			tRPab		= <21000>;
			tRCD		= <18000>;
			tWR		= <15000>;
			tRAS-min	= <42000>;
			tRRD		= <10000>;
			tWTR		= <10000>;
			tXP		= <7500>;
			tRTP		= <7500>;
			tCKESR		= <15000>;
			tDQSCK-max	= <5500>;
			tFAW		= <50000>;
			tZQCS		= <90000>;
			tZQCL		= <360000>;
			tZQinit		= <1000000>;
			tRAS-max-ns	= <70000>;
			tDQSCK-max-derated = <6000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the KZM9D board
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 */
/dts-v1/;

#include "emev2.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "EMEV2 KZM9D Board";
	compatible = "renesas,kzm9d", "renesas,emev2";

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0x8000000>;
	};

	aliases {
		serial1 = &uart1;
	};

	chosen {
		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
		stdout-path = "serial1:115200n8";
	};

	gpio_keys {
		compatible = "gpio-keys";
		one {
			debounce-interval = <50>;
			wakeup-source;
			label = "DSW2-1";
			linux,code = <KEY_1>;
			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
		};
		two {
			debounce-interval = <50>;
			wakeup-source;
			label = "DSW2-2";
			linux,code = <KEY_2>;
			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
		};
		three {
			debounce-interval = <50>;
			wakeup-source;
			label = "DSW2-3";
			linux,code = <KEY_3>;
			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
		};
		four {
			debounce-interval = <50>;
			wakeup-source;
			label = "DSW2-4";
			linux,code = <KEY_4>;
			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
		};
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};

	ethernet@20000000 {
		compatible = "smsc,lan9221", "smsc,lan9115";
		reg = <0x20000000 0x10000>;
		phy-mode = "mii";
		interrupt-parent = <&gpio0>;
		interrupts = <1 IRQ_TYPE_EDGE_RISING>;
		reg-io-width = <4>;
		smsc,irq-active-high;
		smsc,irq-push-pull;
		vddvario-supply = <&reg_1p8v>;
		vdd33a-supply = <&reg_3p3v>;
	};
};

&iic0 {
	status = "okay";
};

&iic1 {
	status = "okay";
};

&pfc {
	uart1_pins: uart1 {
		groups = "uart1_ctrl", "uart1_data";
		function = "uart1";
	};
};

&uart1 {
	pinctrl-0 = <&uart1_pins>;
	pinctrl-names = "default";
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the Emma Mobile EV2 SoC
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,emev2";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		gpio4 = &gpio4;
		i2c0 = &iic0;
		i2c1 = &iic1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <533000000>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clock-frequency = <533000000>;
		};
	};

	gic: interrupt-controller@e0020000 {
		compatible = "arm,pl390";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0xe0028000 0x1000>,
		      <0xe0020000 0x0100>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	clocks@e0110000 {
		compatible = "renesas,emev2-smu";
		reg = <0xe0110000 0x10000>;
		#address-cells = <2>;
		#size-cells = <0>;

		c32ki: c32ki {
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			#clock-cells = <0>;
		};
		iic0_sclkdiv: iic0_sclkdiv@624,0 {
			compatible = "renesas,emev2-smu-clkdiv";
			reg = <0x624 0>;
			clocks = <&pll3_fo>;
			#clock-cells = <0>;
		};
		iic0_sclk: iic0_sclk@48c,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x48c 1>;
			clocks = <&iic0_sclkdiv>;
			#clock-cells = <0>;
		};
		iic1_sclkdiv: iic1_sclkdiv@624,16 {
			compatible = "renesas,emev2-smu-clkdiv";
			reg = <0x624 16>;
			clocks = <&pll3_fo>;
			#clock-cells = <0>;
		};
		iic1_sclk: iic1_sclk@490,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x490 1>;
			clocks = <&iic1_sclkdiv>;
			#clock-cells = <0>;
		};
		pll3_fo: pll3_fo {
			compatible = "fixed-factor-clock";
			clocks = <&c32ki>;
			clock-div = <1>;
			clock-mult = <7000>;
			#clock-cells = <0>;
		};
		usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
			compatible = "renesas,emev2-smu-clkdiv";
			reg = <0x610 0>;
			clocks = <&pll3_fo>;
			#clock-cells = <0>;
		};
		usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 {
			compatible = "renesas,emev2-smu-clkdiv";
			reg = <0x65c 0>;
			clocks = <&pll3_fo>;
			#clock-cells = <0>;
		};
		usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 {
			compatible = "renesas,emev2-smu-clkdiv";
			reg = <0x65c 16>;
			clocks = <&pll3_fo>;
			#clock-cells = <0>;
		};
		usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 {
			compatible = "renesas,emev2-smu-clkdiv";
			reg = <0x660 0>;
			clocks = <&pll3_fo>;
			#clock-cells = <0>;
		};
		usia_u0_sclk: usia_u0_sclk@4a0,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x4a0 1>;
			clocks = <&usia_u0_sclkdiv>;
			#clock-cells = <0>;
		};
		usib_u1_sclk: usib_u1_sclk@4b8,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x4b8 1>;
			clocks = <&usib_u1_sclkdiv>;
			#clock-cells = <0>;
		};
		usib_u2_sclk: usib_u2_sclk@4bc,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x4bc 1>;
			clocks = <&usib_u2_sclkdiv>;
			#clock-cells = <0>;
		};
		usib_u3_sclk: usib_u3_sclk@4c0,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x4c0 1>;
			clocks = <&usib_u3_sclkdiv>;
			#clock-cells = <0>;
		};
		sti_sclk: sti_sclk@528,1 {
			compatible = "renesas,emev2-smu-gclk";
			reg = <0x528 1>;
			clocks = <&c32ki>;
			#clock-cells = <0>;
		};
	};

	timer@e0180000 {
		compatible = "renesas,em-sti";
		reg = <0xe0180000 0x54>;
		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sti_sclk>;
		clock-names = "sclk";
	};

	uart0: serial@e1020000 {
		compatible = "renesas,em-uart";
		reg = <0xe1020000 0x38>;
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&usia_u0_sclk>;
		clock-names = "sclk";
	};

	uart1: serial@e1030000 {
		compatible = "renesas,em-uart";
		reg = <0xe1030000 0x38>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&usib_u1_sclk>;
		clock-names = "sclk";
	};

	uart2: serial@e1040000 {
		compatible = "renesas,em-uart";
		reg = <0xe1040000 0x38>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&usib_u2_sclk>;
		clock-names = "sclk";
	};

	uart3: serial@e1050000 {
		compatible = "renesas,em-uart";
		reg = <0xe1050000 0x38>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&usib_u3_sclk>;
		clock-names = "sclk";
	};

	pfc: pinctrl@e0140200 {
		compatible = "renesas,pfc-emev2";
		reg = <0xe0140200 0x100>;
	};

	gpio0: gpio@e0050000 {
		compatible = "renesas,em-gio";
		reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#gpio-cells = <2>;
		ngpios = <32>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio1: gpio@e0050080 {
		compatible = "renesas,em-gio";
		reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#gpio-cells = <2>;
		ngpios = <32>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio2: gpio@e0050100 {
		compatible = "renesas,em-gio";
		reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#gpio-cells = <2>;
		ngpios = <32>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio3: gpio@e0050180 {
		compatible = "renesas,em-gio";
		reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#gpio-cells = <2>;
		ngpios = <32>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio4: gpio@e0050200 {
		compatible = "renesas,em-gio";
		reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 31>;
		#gpio-cells = <2>;
		ngpios = <31>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	iic0: i2c@e0070000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-emev2";
		reg = <0xe0070000 0x28>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
		clocks = <&iic0_sclk>;
		clock-names = "sclk";
		status = "disabled";
	};

	iic1: i2c@e10a0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-emev2";
		reg = <0xe10a0000 0x28>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
		clocks = <&iic1_sclk>;
		clock-names = "sclk";
		status = "disabled";
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/dts-v1/;

/* Bootloader installs ATF here */
/memreserve/ 0x80000000 0x200000;

#include "en7523.dtsi"

/ {
	model = "Airoha EN7523 Evaluation Board";
	compatible = "airoha,en7523-evb", "airoha,en7523";

	aliases {
		serial0 = &uart1;
	};

	chosen {
		bootargs = "console=ttyS0,115200 earlycon";
		stdout-path = "serial0:115200n8";
		linux,usable-memory-range = <0x80200000 0x1fe00000>;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/en7523-clk.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		npu_binary@84000000 {
			no-map;
			reg = <0x84000000 0xA00000>;
		};

		npu_flag@84B0000 {
			no-map;
			reg = <0x84B00000 0x100000>;
		};

		npu_pkt@85000000 {
			no-map;
			reg = <0x85000000 0x1A00000>;
		};

		npu_phyaddr@86B00000 {
			no-map;
			reg = <0x86B00000 0x100000>;
		};

		npu_rxdesc@86D00000 {
			no-map;
			reg = <0x86D00000 0x100000>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			clock-frequency = <80000000>;
			next-level-cache = <&L2_0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			clock-frequency = <80000000>;
			next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache0 {
			compatible = "cache";
		};
	};

	scu: system-controller@1fa20000 {
		compatible = "airoha,en7523-scu";
		reg = <0x1fa20000 0x400>,
		      <0x1fb00000 0x1000>;
		#clock-cells = <1>;
	};

	gic: interrupt-controller@9000000 {
		compatible = "arm,gic-v3";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x09000000 0x20000>,
		      <0x09080000 0x80000>,
		      <0x09400000 0x2000>,
		      <0x09500000 0x2000>,
		      <0x09600000 0x20000>;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	uart1: serial@1fbf0000 {
		compatible = "ns16550";
		reg = <0x1fbf0000 0x30>;
		reg-io-width = <4>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <1843200>;
		status = "okay";
	};

	gpio0: gpio@1fbf0200 {
		compatible = "airoha,en7523-gpio";
		reg = <0x1fbf0204 0x4>,
		      <0x1fbf0200 0x4>,
		      <0x1fbf0220 0x4>,
		      <0x1fbf0214 0x4>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpio1: gpio@1fbf0270 {
		compatible = "airoha,en7523-gpio";
		reg = <0x1fbf0270 0x4>,
		      <0x1fbf0260 0x4>,
		      <0x1fbf0264 0x4>,
		      <0x1fbf0278 0x4>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pcie0: pcie@1fa91000 {
		compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
		device_type = "pci";
		reg = <0x1fa91000 0x1000>;
		reg-names = "port0";
		linux,pci-domain = <0>;
		#address-cells = <3>;
		#size-cells = <2>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "pcie_irq";
		clocks = <&scu EN7523_CLK_PCIE>;
		clock-names = "sys_ck0";
		bus-range = <0x00 0xff>;
		ranges = <0x82000000 0 0x20000000  0x20000000  0 0x8000000>;
		status = "disabled";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
				<0 0 0 2 &pcie_intc0 1>,
				<0 0 0 3 &pcie_intc0 2>,
				<0 0 0 4 &pcie_intc0 3>;
		pcie_intc0: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};
	};

	pcie1: pcie@1fa92000 {
		compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
		device_type = "pci";
		reg = <0x1fa92000 0x1000>;
		reg-names = "port1";
		linux,pci-domain = <1>;
		#address-cells = <3>;
		#size-cells = <2>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "pcie_irq";
		clocks = <&scu EN7523_CLK_PCIE>;
		clock-names = "sys_ck1";
		bus-range = <0x00 0xff>;
		ranges = <0x82000000 0 0x28000000  0x28000000  0 0x8000000>;
		status = "disabled";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
				<0 0 0 2 &pcie_intc1 1>,
				<0 0 0 3 &pcie_intc1 2>,
				<0 0 0 4 &pcie_intc1 3>;
		pcie_intc1: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later

/dts-v1/;

#include <dt-bindings/clock/clps711x-clock.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Cirrus Logic EP7209";
	compatible = "cirrus,ep7209";

	chosen { };

	aliases {
		gpio0 = &porta;
		gpio1 = &portb;
		gpio3 = &portd;
		gpio4 = &porte;
		serial0 = &uart1;
		serial1 = &uart2;
		spi0 = &spi;
		timer0 = &timer1;
		timer1 = &timer2;
	};

	cpus {
		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			device_type = "cpu";
			compatible = "arm,arm720t";
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&intc>;
		ranges;

		clks: clks@80000000 {
			#clock-cells = <1>;
			compatible = "cirrus,ep7209-clk";
			reg = <0x80000000 0xc000>;
			startup-frequency = <73728000>;
		};

		intc: intc@80000000 {
			compatible = "cirrus,ep7209-intc";
			reg = <0x80000000 0x4000>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		porta: gpio@80000000 {
			compatible = "cirrus,ep7209-gpio";
			reg = <0x80000000 0x1 0x80000040 0x1>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		portb: gpio@80000001 {
			compatible = "cirrus,ep7209-gpio";
			reg = <0x80000001 0x1 0x80000041 0x1>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		portd: gpio@80000003 {
			compatible = "cirrus,ep7209-gpio";
			reg = <0x80000003 0x1 0x80000043 0x1>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		porte: gpio@80000083 {
			compatible = "cirrus,ep7209-gpio";
			reg = <0x80000083 0x1 0x800000c3 0x1>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		syscon1: syscon@80000100 {
			compatible = "cirrus,ep7209-syscon1", "syscon";
			reg = <0x80000100 0x80>;
		};

		bus: bus@80000180 {
			#address-cells = <2>;
			#size-cells = <1>;
			compatible = "cirrus,ep7209-bus", "simple-bus";
			clocks = <&clks CLPS711X_CLK_BUS>;
			reg = <0x80000180 0x80>;
			ranges = <
				0 0 0x00000000 0x10000000
				1 0 0x10000000 0x10000000
				2 0 0x20000000 0x10000000
				3 0 0x30000000 0x10000000
				4 0 0x40000000 0x10000000
				5 0 0x50000000 0x10000000
				6 0 0x60000000 0x0000c000
				7 0 0x70000000 0x00000080
			>;
		};

		fb: fb@800002c0 {
			compatible = "cirrus,ep7209-fb";
			reg = <0x800002c0 0xd44>, <0x60000000 0xc000>;
			clocks = <&clks CLPS711X_CLK_BUS>;
			syscon = <&syscon1>;
			status = "disabled";
		};

		timer1: timer@80000300 {
			compatible = "cirrus,ep7209-timer";
			reg = <0x80000300 0x4>;
			clocks = <&clks CLPS711X_CLK_TIMER1>;
			interrupts = <8>;
		};

		timer2: timer@80000340 {
			compatible = "cirrus,ep7209-timer";
			reg = <0x80000340 0x4>;
			clocks = <&clks CLPS711X_CLK_TIMER2>;
			interrupts = <9>;
		};

		pwm: pwm@80000400 {
			compatible = "cirrus,ep7209-pwm";
			reg = <0x80000400 0x4>;
			clocks = <&clks CLPS711X_CLK_PWM>;
			#pwm-cells = <1>;
		};

		uart1: serial@80000480 {
			compatible = "cirrus,ep7209-uart";
			reg = <0x80000480 0x80>;
			interrupts = <12 13>;
			clocks = <&clks CLPS711X_CLK_UART>;
			syscon = <&syscon1>;
		};

		spi: spi@80000500 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "cirrus,ep7209-spi";
			reg = <0x80000500 0x4>;
			interrupts = <15>;
			clocks = <&clks CLPS711X_CLK_SPI>;
			syscon = <&syscon3>;
			status = "disabled";
		};

		syscon2: syscon@80001100 {
			compatible = "cirrus,ep7209-syscon2", "syscon";
			reg = <0x80001100 0x80>;
		};

		uart2: serial@80001480 {
			compatible = "cirrus,ep7209-uart";
			reg = <0x80001480 0x80>;
			interrupts = <28 29>;
			clocks = <&clks CLPS711X_CLK_UART>;
			syscon = <&syscon2>;
		};

		dai: dai@80002000 {
			#sound-dai-cells = <0>;
			compatible = "cirrus,ep7209-dai";
			reg = <0x80002000 0x604>;
			clocks = <&clks CLPS711X_CLK_PLL>;
			clock-names = "pll";
			interrupts = <32>;
			syscon = <&syscon3>;
			status = "disabled";
		};

		syscon3: syscon@80002200 {
			compatible = "cirrus,ep7209-syscon3", "syscon";
			reg = <0x80002200 0x40>;
		};
	};

	keypad: keypad {
		compatible = "cirrus,ep7209-keypad";
		interrupt-parent = <&intc>;
		interrupts = <16>;
		syscon = <&syscon1>;
		status = "disabled";
	};

	mctrl: mctrl {
		compatible = "cirrus,ep7209-mctrl-gpio";
		gpio,syscon-dev = <&syscon1 0 0>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later

#include "ep7211.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Cirrus Logic EP7211 Development Board";
	compatible = "cirrus,edb7211", "cirrus,ep7211", "cirrus,ep7209";

	memory@c0000000 {
		device_type = "memory";
		reg = <0xc0000000 0x02000000>;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm 0>;
		brightness-levels = <
			0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
			0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf
		>;
		default-brightness-level = <0x0>;
		power-supply = <&blen>;
	};

	display: display {
		model = "320x240x4";
		bits-per-pixel = <4>;
		ac-prescale = <17>;

		display-timings {
			native-mode = <&timing0>;
			timing0: 320x240 {
				hactive = <320>;
				hback-porch = <0>;
				hfront-porch = <0>;
				hsync-len = <0>;
				vactive = <240>;
				vback-porch = <0>;
				vfront-porch = <0>;
				vsync-len = <0>;
				clock-frequency = <6500000>;
			};
		};
	};

	i2c: i2c {
		compatible = "i2c-gpio";
		gpios = <&portd 4 GPIO_ACTIVE_HIGH>,
			<&portd 5 GPIO_ACTIVE_HIGH>;
		i2c-gpio,delay-us = <2>;
		i2c-gpio,scl-output-only;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	lcddc: lcddc {
		compatible = "regulator-fixed";
		regulator-name = "BACKLIGHT ENABLE";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&portd 1 GPIO_ACTIVE_HIGH>;
	};

	blen: blen {
		compatible = "regulator-fixed";
		regulator-name = "BACKLIGHT ENABLE";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&portd 3 GPIO_ACTIVE_HIGH>;
	};
};

&bus {
	flash: nor@0 {
		compatible = "cfi-flash";
		reg = <0 0x00000000 0x02000000>;
		bank-width = <2>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

&fb {
	display = <&display>;
	lcd-supply = <&lcddc>;
	status = "okay";
};

&portd {
	lcden {
		gpio-hog;
		gpios = <2 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "LCD ENABLE";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later

#include "ep7209.dtsi"

/ {
	model = "Cirrus Logic EP7211";
	compatible = "cirrus,ep7211", "cirrus,ep7209";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * ethernut5.dts - Device Tree file for Ethernut 5 board
 *
 * Copyright (C) 2012 egnite GmbH <info@egnite.de>
 */
/dts-v1/;
#include "at91sam9xe.dtsi"

/ {
	model = "Ethernut 5";
	compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9";

	chosen {
		bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2";
	};

	memory@20000000 {
		reg = <0x20000000 0x08000000>;
	};

	clocks {
		slow_xtal {
			clock-frequency = <32768>;
		};

		main_xtal {
			clock-frequency = <18432000>;
		};
	};

	ahb {
		apb {
			dbgu: serial@fffff200 {
				status = "okay";
			};

			tcb0: timer@fffa0000 {
				timer@0 {
					compatible = "atmel,tcb-timer";
					reg = <0>, <1>;
				};

				timer@2 {
					compatible = "atmel,tcb-timer";
					reg = <2>;
				};
			};

			usart0: serial@fffb0000 {
				status = "okay";
			};

			usart1: serial@fffb4000 {
				status = "okay";
			};

			macb0: ethernet@fffc4000 {
				phy-mode = "rmii";
				status = "okay";
			};

			usb1: gadget@fffa4000 {
				atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
				status = "okay";
			};
		};

		ebi: ebi@10000000 {
			status = "okay";

			nand_controller: nand-controller {
				status = "okay";
				pinctrl-0 = <&pinctrl_nand_cs>;
				pinctrl-names = "default";

				nand: nand@3 {
					reg = <0x3 0x0 0x800000>;
					cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
					nand-bus-width = <8>;
					nand-ecc-mode = "soft";
					nand-on-flash-bbt;
					label = "atmel_nand";

					partitions {
						compatible = "fixed-partitions";
						#address-cells = <1>;
						#size-cells = <1>;

						root@0 {
							label = "root";
							reg = <0x0 0x08000000>;
						};

						data@20000 {
							label = "data";
							reg = <0x08000000 0x38000000>;
						};
					};
				};
			};
		};

		usb0: ohci@500000 {
			num-ports = <2>;
			status = "okay";
		};
	};

	i2c-gpio-0 {
		status = "okay";

		pcf8563@50 {
			compatible = "nxp,pcf8563";
			reg = <0x51>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3
 *
 * Copyright (C) 2012 Telit,
 *               2012 Fabio Porcedda <fabio.porcedda@gmail.com>
 */

/dts-v1/;

#include "ge863-pro3.dtsi"

/ {
	model = "Telit EVK-PRO3 for Telit GE863-PRO3";
	compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9";

	clocks {
		slow_xtal {
			clock-frequency = <32768>;
		};
	};

	ahb {
		apb {
			macb0: ethernet@fffc4000 {
				phy-mode = "rmii";
				status = "okay";
			};

			usart0: serial@fffb0000 {
				status = "okay";
			};

			usart2: serial@fffb8000 {
				status = "okay";
			};

			usb1: gadget@fffa4000 {
				atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
				status = "okay";
			};

			watchdog@fffffd40 {
				status = "okay";
			};
		};

		usb0: ohci@500000 {
			num-ports = <2>;
			status = "okay";
		};
	};

	i2c-gpio-0 {
		status = "okay";
	};

};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition.
 *
 * Copyright (c) 2016 Samsung Electronics Co., Ltd
 */

/ {
	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		mfc_left: region-mfc-left {
			compatible = "shared-dma-pool";
			no-map;
			size = <0x2400000>;
			alignment = <0x100000>;
		};

		mfc_right: region-mfc-right {
			compatible = "shared-dma-pool";
			no-map;
			size = <0x800000>;
			alignment = <0x100000>;
		};
	};
};

&mfc {
	memory-region = <&mfc_left>, <&mfc_right>;
};


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Samsung Exynos DTS pinctrl constants
 *
 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 * Copyright (c) 2022 Linaro Ltd
 * Author: Krzysztof Kozlowski <krzk@kernel.org>
 */

#ifndef __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__
#define __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__

#define EXYNOS_PIN_PULL_NONE		0
#define EXYNOS_PIN_PULL_DOWN		1
#define EXYNOS_PIN_PULL_UP		3

/* Pin function in power down mode */
#define EXYNOS_PIN_PDN_OUT0		0
#define EXYNOS_PIN_PDN_OUT1		1
#define EXYNOS_PIN_PDN_INPUT		2
#define EXYNOS_PIN_PDN_PREV		3

/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */
#define EXYNOS4_PIN_DRV_LV1		0
#define EXYNOS4_PIN_DRV_LV2		2
#define EXYNOS4_PIN_DRV_LV3		1
#define EXYNOS4_PIN_DRV_LV4		3

/* Drive strengths for Exynos5260 */
#define EXYNOS5260_PIN_DRV_LV1		0
#define EXYNOS5260_PIN_DRV_LV2		1
#define EXYNOS5260_PIN_DRV_LV4		2
#define EXYNOS5260_PIN_DRV_LV6		3

/*
 * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except
 * GPIO_HSI block)
 */
#define EXYNOS5420_PIN_DRV_LV1		0
#define EXYNOS5420_PIN_DRV_LV2		1
#define EXYNOS5420_PIN_DRV_LV3		2
#define EXYNOS5420_PIN_DRV_LV4		3

#define EXYNOS_PIN_FUNC_INPUT		0
#define EXYNOS_PIN_FUNC_OUTPUT		1
#define EXYNOS_PIN_FUNC_2		2
#define EXYNOS_PIN_FUNC_3		3
#define EXYNOS_PIN_FUNC_4		4
#define EXYNOS_PIN_FUNC_5		5
#define EXYNOS_PIN_FUNC_6		6
#define EXYNOS_PIN_FUNC_EINT		0xf
#define EXYNOS_PIN_FUNC_F		EXYNOS_PIN_FUNC_EINT

#endif /* __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ */


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition.
 */

&pmu_system_controller {
	poweroff: syscon-poweroff {
		compatible = "syscon-poweroff";
		regmap = <&pmu_system_controller>;
		offset = <0x330C>; /* PS_HOLD_CONTROL */
		mask = <0x5200>; /* reset value */
	};

	reboot: syscon-reboot {
		compatible = "syscon-reboot";
		regmap = <&pmu_system_controller>;
		offset = <0x0400>; /* SWRESET */
		mask = <0x1>;
	};
};