code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP3 powerdomain definitions
 *
 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bug.h>

#include "soc.h"
#include "powerdomain.h"
#include "powerdomains2xxx_3xxx_data.h"
#include "prcm-common.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"

/*
 * 34XX-specific powerdomains, dependencies
 */

/*
 * Powerdomains
 */

static struct powerdomain iva2_pwrdm = {
	.name		  = "iva2_pwrdm",
	.prcm_offs	  = OMAP3430_IVA2_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 4,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
		[1] = PWRSTS_OFF_RET,
		[2] = PWRSTS_OFF_RET,
		[3] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,
		[1] = PWRSTS_ON,
		[2] = PWRSTS_OFF_ON,
		[3] = PWRSTS_ON,
	},
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain mpu_3xxx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_ON,
	},
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain mpu_am35x_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,
	},
	.voltdm		  = { .name = "mpu_iva" },
};

/*
 * The USBTLL Save-and-Restore mechanism is broken on
 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
 * needs to be disabled on these chips.
 * Refer: 3430 errata ID i459 and 3630 errata ID i579
 *
 * Note: setting the SAR flag could help for errata ID i478
 *  which applies to 3430 <= ES3.1, but since the SAR feature
 *  is broken, do not use it.
 */
static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain core_3xxx_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	/*
	 * Setting the SAR flag for errata ID i478 which applies
	 *  to 3430 <= ES3.1
	 */
	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain core_am35x_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON,	 /* MEM1RETSTATE */
		[1] = PWRSTS_ON,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_ON, /* MEM2ONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dss_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dss_am35x_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

/*
 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
 * possible SGX powerstate, the SGX device itself does not support
 * retention.
 */
static struct powerdomain sgx_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	/* XXX This is accurate for 3430 SGX, but what about GFX? */
	.pwrsts		  = PWRSTS_OFF_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain sgx_am35x_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain cam_pwrdm = {
	.name		  = "cam_pwrdm",
	.prcm_offs	  = OMAP3430_CAM_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain per_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain per_am35x_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain emu_pwrdm = {
	.name		= "emu_pwrdm",
	.prcm_offs	= OMAP3430_EMU_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain neon_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain neon_am35x_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain usbhost_pwrdm = {
	.name		  = "usbhost_pwrdm",
	.prcm_offs	  = OMAP3430ES2_USBHOST_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	/*
	 * REVISIT: Enabling usb host save and restore mechanism seems to
	 * leave the usb host domain permanently in ACTIVE mode after
	 * changing the usb host power domain state from OFF to active once.
	 * Disabling for now.
	 */
	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dpll1_pwrdm = {
	.name		= "dpll1_pwrdm",
	.prcm_offs	= MPU_MOD,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain dpll2_pwrdm = {
	.name		= "dpll2_pwrdm",
	.prcm_offs	= OMAP3430_IVA2_MOD,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain dpll3_pwrdm = {
	.name		= "dpll3_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dpll4_pwrdm = {
	.name		= "dpll4_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain dpll5_pwrdm = {
	.name		= "dpll5_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain alwon_81xx_pwrdm = {
	.name		  = "alwon_pwrdm",
	.prcm_offs	  = TI81XX_PRM_ALWON_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain device_81xx_pwrdm = {
	.name		  = "device_pwrdm",
	.prcm_offs	  = TI81XX_PRM_DEVICE_MOD,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain gem_814x_pwrdm = {
	.name		= "gem_pwrdm",
	.prcm_offs	= TI814X_PRM_DSP_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "dsp" },
};

static struct powerdomain ivahd_814x_pwrdm = {
	.name		= "ivahd_pwrdm",
	.prcm_offs	= TI814X_PRM_HDVICP_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "iva" },
};

static struct powerdomain hdvpss_814x_pwrdm = {
	.name		= "hdvpss_pwrdm",
	.prcm_offs	= TI814X_PRM_HDVPSS_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "dsp" },
};

static struct powerdomain sgx_814x_pwrdm = {
	.name		= "sgx_pwrdm",
	.prcm_offs	= TI814X_PRM_GFX_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "core" },
};

static struct powerdomain isp_814x_pwrdm = {
	.name		= "isp_pwrdm",
	.prcm_offs	= TI814X_PRM_ISP_MOD,
	.pwrsts		= PWRSTS_OFF_ON,
	.voltdm		= { .name = "core" },
};

static struct powerdomain active_81xx_pwrdm = {
	.name		  = "active_pwrdm",
	.prcm_offs	  = TI816X_PRM_ACTIVE_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain default_81xx_pwrdm = {
	.name		  = "default_pwrdm",
	.prcm_offs	  = TI81XX_PRM_DEFAULT_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "core" },
};

static struct powerdomain ivahd0_816x_pwrdm = {
	.name		  = "ivahd0_pwrdm",
	.prcm_offs	  = TI816X_PRM_IVAHD0_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain ivahd1_816x_pwrdm = {
	.name		  = "ivahd1_pwrdm",
	.prcm_offs	  = TI816X_PRM_IVAHD1_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain ivahd2_816x_pwrdm = {
	.name		  = "ivahd2_pwrdm",
	.prcm_offs	  = TI816X_PRM_IVAHD2_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "mpu_iva" },
};

static struct powerdomain sgx_816x_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = TI816X_PRM_SGX_MOD,
	.pwrsts		  = PWRSTS_OFF_ON,
	.voltdm		  = { .name = "core" },
};

/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
	&wkup_omap2_pwrdm,
	&iva2_pwrdm,
	&mpu_3xxx_pwrdm,
	&neon_pwrdm,
	&cam_pwrdm,
	&dss_pwrdm,
	&per_pwrdm,
	&emu_pwrdm,
	&dpll1_pwrdm,
	&dpll2_pwrdm,
	&dpll3_pwrdm,
	&dpll4_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
	&gfx_omap2_pwrdm,
	&core_3xxx_pre_es3_1_pwrdm,
	NULL
};

/* also includes 3630ES1.0 */
static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
	&core_3xxx_pre_es3_1_pwrdm,
	&sgx_pwrdm,
	&usbhost_pwrdm,
	&dpll5_pwrdm,
	NULL
};

/* also includes 3630ES1.1+ */
static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
	&core_3xxx_es3_1_pwrdm,
	&sgx_pwrdm,
	&usbhost_pwrdm,
	&dpll5_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_am35x[] __initdata = {
	&wkup_omap2_pwrdm,
	&mpu_am35x_pwrdm,
	&neon_am35x_pwrdm,
	&core_am35x_pwrdm,
	&sgx_am35x_pwrdm,
	&dss_am35x_pwrdm,
	&per_am35x_pwrdm,
	&emu_pwrdm,
	&dpll1_pwrdm,
	&dpll3_pwrdm,
	&dpll4_pwrdm,
	&dpll5_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_ti814x[] __initdata = {
	&alwon_81xx_pwrdm,
	&device_81xx_pwrdm,
	&active_81xx_pwrdm,
	&default_81xx_pwrdm,
	&gem_814x_pwrdm,
	&ivahd_814x_pwrdm,
	&hdvpss_814x_pwrdm,
	&sgx_814x_pwrdm,
	&isp_814x_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_ti816x[] __initdata = {
	&alwon_81xx_pwrdm,
	&device_81xx_pwrdm,
	&active_81xx_pwrdm,
	&default_81xx_pwrdm,
	&ivahd0_816x_pwrdm,
	&ivahd1_816x_pwrdm,
	&ivahd2_816x_pwrdm,
	&sgx_816x_pwrdm,
	NULL
};

/* TI81XX specific ops */
#define TI81XX_PM_PWSTCTRL				0x0000
#define TI81XX_RM_RSTCTRL				0x0010
#define TI81XX_PM_PWSTST				0x0004

static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{
	omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
				   (pwrst << OMAP_POWERSTATE_SHIFT),
				   pwrdm->prcm_offs, TI81XX_PM_PWSTCTRL);
	return 0;
}

static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
{
	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
					     TI81XX_PM_PWSTCTRL,
					     OMAP_POWERSTATE_MASK);
}

static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
{
	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
		(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
					     TI81XX_PM_PWSTST,
					     OMAP_POWERSTATEST_MASK);
}

static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
{
	return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
		(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
					     TI81XX_PM_PWSTST,
					     OMAP3430_LOGICSTATEST_MASK);
}

static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
{
	u32 c = 0;

	while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs,
		(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
				       TI81XX_PM_PWSTST) &
		OMAP_INTRANSITION_MASK) &&
		(c++ < PWRDM_TRANSITION_BAILOUT))
			udelay(1);

	if (c > PWRDM_TRANSITION_BAILOUT) {
		pr_err("powerdomain: %s timeout waiting for transition\n",
		       pwrdm->name);
		return -EAGAIN;
	}

	pr_debug("powerdomain: completed transition in %d loops\n", c);

	return 0;
}

/* For dm814x we need to fix up fix GFX pwstst and rstctrl reg offsets */
static struct pwrdm_ops ti81xx_pwrdm_operations = {
	.pwrdm_set_next_pwrst	= ti81xx_pwrdm_set_next_pwrst,
	.pwrdm_read_next_pwrst	= ti81xx_pwrdm_read_next_pwrst,
	.pwrdm_read_pwrst	= ti81xx_pwrdm_read_pwrst,
	.pwrdm_read_logic_pwrst	= ti81xx_pwrdm_read_logic_pwrst,
	.pwrdm_wait_transition	= ti81xx_pwrdm_wait_transition,
};

void __init omap3xxx_powerdomains_init(void)
{
	unsigned int rev;

	if (!cpu_is_omap34xx() && !cpu_is_ti81xx())
		return;

	/* Only 81xx needs custom pwrdm_operations */
	if (!cpu_is_ti81xx())
		pwrdm_register_platform_funcs(&omap3_pwrdm_operations);

	rev = omap_rev();

	if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
		pwrdm_register_pwrdms(powerdomains_am35x);
	} else if (rev == TI8148_REV_ES1_0 || rev == TI8148_REV_ES2_0 ||
		   rev == TI8148_REV_ES2_1) {
		pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
		pwrdm_register_pwrdms(powerdomains_ti814x);
	} else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
			|| rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
		pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
		pwrdm_register_pwrdms(powerdomains_ti816x);
	} else {
		pwrdm_register_pwrdms(powerdomains_omap3430_common);

		switch (rev) {
		case OMAP3430_REV_ES1_0:
			pwrdm_register_pwrdms(powerdomains_omap3430es1);
			break;
		case OMAP3430_REV_ES2_0:
		case OMAP3430_REV_ES2_1:
		case OMAP3430_REV_ES3_0:
		case OMAP3630_REV_ES1_0:
			pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
			break;
		case OMAP3430_REV_ES3_1:
		case OMAP3430_REV_ES3_1_2:
		case OMAP3630_REV_ES1_1:
		case OMAP3630_REV_ES1_2:
			pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
			break;
		default:
			WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
		}
	}

	pwrdm_complete_init();
}


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * AM43xx Power domains framework
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 */

#include <linux/kernel.h>
#include <linux/init.h>

#include "powerdomain.h"

#include "prcm-common.h"
#include "prcm44xx.h"
#include "prcm43xx.h"

static struct powerdomain gfx_43xx_pwrdm = {
	.name		  = "gfx_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = AM43XX_PRM_GFX_INST,
	.prcm_partition	  = AM43XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* gfx_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

static struct powerdomain mpu_43xx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.voltdm		  = { .name = "mpu" },
	.prcm_offs	  = AM43XX_PRM_MPU_INST,
	.prcm_partition	  = AM43XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 3,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* mpu_l1 */
		[1] = PWRSTS_OFF_RET,	/* mpu_l2 */
		[2] = PWRSTS_OFF_RET,	/* mpu_ram */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* mpu_l1 */
		[1] = PWRSTS_ON,	/* mpu_l2 */
		[2] = PWRSTS_ON,	/* mpu_ram */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

static struct powerdomain rtc_43xx_pwrdm = {
	.name		  = "rtc_pwrdm",
	.voltdm		  = { .name = "rtc" },
	.prcm_offs	  = AM43XX_PRM_RTC_INST,
	.prcm_partition	  = AM43XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

static struct powerdomain wkup_43xx_pwrdm = {
	.name		  = "wkup_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = AM43XX_PRM_WKUP_INST,
	.prcm_partition	  = AM43XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* debugss_mem */
	},
};

static struct powerdomain tamper_43xx_pwrdm = {
	.name		  = "tamper_pwrdm",
	.voltdm		  = { .name = "tamper" },
	.prcm_offs	  = AM43XX_PRM_TAMPER_INST,
	.prcm_partition	  = AM43XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

static struct powerdomain cefuse_43xx_pwrdm = {
	.name		  = "cefuse_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = AM43XX_PRM_CEFUSE_INST,
	.prcm_partition	  = AM43XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

static struct powerdomain per_43xx_pwrdm = {
	.name		  = "per_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = AM43XX_PRM_PER_INST,
	.prcm_partition	  = AM43XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 4,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* icss_mem */
		[1] = PWRSTS_OFF_RET,	/* per_mem */
		[2] = PWRSTS_OFF_RET,	/* ram1_mem */
		[3] = PWRSTS_OFF_RET,	/* ram2_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* icss_mem */
		[1] = PWRSTS_ON,	/* per_mem */
		[2] = PWRSTS_ON,	/* ram1_mem */
		[3] = PWRSTS_ON,	/* ram2_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

static struct powerdomain *powerdomains_am43xx[] __initdata = {
	&gfx_43xx_pwrdm,
	&mpu_43xx_pwrdm,
	&rtc_43xx_pwrdm,
	&wkup_43xx_pwrdm,
	&tamper_43xx_pwrdm,
	&cefuse_43xx_pwrdm,
	&per_43xx_pwrdm,
	NULL
};

static int am43xx_check_vcvp(void)
{
	return 0;
}

void __init am43xx_powerdomains_init(void)
{
	omap4_pwrdm_operations.pwrdm_has_voltdm = am43xx_check_vcvp;
	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
	pwrdm_register_pwrdms(powerdomains_am43xx);
	pwrdm_complete_init();
}

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP4 Power domains framework
 *
 * Copyright (C) 2009-2011 Texas Instruments, Inc.
 * Copyright (C) 2009-2011 Nokia Corporation
 *
 * Abhijit Pagare (abhijitpagare@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 * Paul Walmsley (paul@pwsan.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#include <linux/kernel.h>
#include <linux/init.h>

#include "powerdomain.h"

#include "prcm-common.h"
#include "prcm44xx.h"
#include "prm-regbits-44xx.h"
#include "prm44xx.h"
#include "prcm_mpu44xx.h"

/* core_44xx_pwrdm: CORE power domain */
static struct powerdomain core_44xx_pwrdm = {
	.name		  = "core_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_CORE_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 5,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* core_nret_bank */
		[1] = PWRSTS_RET,	/* core_ocmram */
		[2] = PWRSTS_RET,	/* core_other_bank */
		[3] = PWRSTS_OFF_RET,	/* ducati_l2ram */
		[4] = PWRSTS_OFF_RET,	/* ducati_unicache */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* core_nret_bank */
		[1] = PWRSTS_ON,	/* core_ocmram */
		[2] = PWRSTS_ON,	/* core_other_bank */
		[3] = PWRSTS_ON,	/* ducati_l2ram */
		[4] = PWRSTS_ON,	/* ducati_unicache */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* gfx_44xx_pwrdm: 3D accelerator power domain */
static struct powerdomain gfx_44xx_pwrdm = {
	.name		  = "gfx_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_GFX_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* gfx_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* gfx_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* abe_44xx_pwrdm: Audio back end power domain */
static struct powerdomain abe_44xx_pwrdm = {
	.name		  = "abe_pwrdm",
	.voltdm		  = { .name = "iva" },
	.prcm_offs	  = OMAP4430_PRM_ABE_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF,
	.banks		  = 2,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_RET,	/* aessmem */
		[1] = PWRSTS_OFF,	/* periphmem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* aessmem */
		[1] = PWRSTS_ON,	/* periphmem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* dss_44xx_pwrdm: Display subsystem power domain */
static struct powerdomain dss_44xx_pwrdm = {
	.name		  = "dss_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_DSS_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* dss_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* dss_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* tesla_44xx_pwrdm: Tesla processor power domain */
static struct powerdomain tesla_44xx_pwrdm = {
	.name		  = "tesla_pwrdm",
	.voltdm		  = { .name = "iva" },
	.prcm_offs	  = OMAP4430_PRM_TESLA_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 3,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_RET,	/* tesla_edma */
		[1] = PWRSTS_OFF_RET,	/* tesla_l1 */
		[2] = PWRSTS_OFF_RET,	/* tesla_l2 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* tesla_edma */
		[1] = PWRSTS_ON,	/* tesla_l1 */
		[2] = PWRSTS_ON,	/* tesla_l2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* wkup_44xx_pwrdm: Wake-up power domain */
static struct powerdomain wkup_44xx_pwrdm = {
	.name		  = "wkup_pwrdm",
	.voltdm		  = { .name = "wakeup" },
	.prcm_offs	  = OMAP4430_PRM_WKUP_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* wkup_bank */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* wkup_bank */
	},
};

/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
static struct powerdomain cpu0_44xx_pwrdm = {
	.name		  = "cpu0_pwrdm",
	.voltdm		  = { .name = "mpu" },
	.prcm_offs	  = OMAP4430_PRCM_MPU_CPU0_INST,
	.prcm_partition	  = OMAP4430_PRCM_MPU_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cpu0_l1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cpu0_l1 */
	},
};

/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
static struct powerdomain cpu1_44xx_pwrdm = {
	.name		  = "cpu1_pwrdm",
	.voltdm		  = { .name = "mpu" },
	.prcm_offs	  = OMAP4430_PRCM_MPU_CPU1_INST,
	.prcm_partition	  = OMAP4430_PRCM_MPU_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cpu1_l1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cpu1_l1 */
	},
};

/* emu_44xx_pwrdm: Emulation power domain */
static struct powerdomain emu_44xx_pwrdm = {
	.name		  = "emu_pwrdm",
	.voltdm		  = { .name = "wakeup" },
	.prcm_offs	  = OMAP4430_PRM_EMU_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* emu_bank */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* emu_bank */
	},
};

/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
static struct powerdomain mpu_44xx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.voltdm		  = { .name = "mpu" },
	.prcm_offs	  = OMAP4430_PRM_MPU_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 3,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* mpu_l1 */
		[1] = PWRSTS_OFF_RET,	/* mpu_l2 */
		[2] = PWRSTS_RET,	/* mpu_ram */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* mpu_l1 */
		[1] = PWRSTS_ON,	/* mpu_l2 */
		[2] = PWRSTS_ON,	/* mpu_ram */
	},
};

/* ivahd_44xx_pwrdm: IVA-HD power domain */
static struct powerdomain ivahd_44xx_pwrdm = {
	.name		  = "ivahd_pwrdm",
	.voltdm		  = { .name = "iva" },
	.prcm_offs	  = OMAP4430_PRM_IVAHD_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF,
	.banks		  = 4,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* hwa_mem */
		[1] = PWRSTS_OFF_RET,	/* sl2_mem */
		[2] = PWRSTS_OFF_RET,	/* tcm1_mem */
		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* hwa_mem */
		[1] = PWRSTS_ON,	/* sl2_mem */
		[2] = PWRSTS_ON,	/* tcm1_mem */
		[3] = PWRSTS_ON,	/* tcm2_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* cam_44xx_pwrdm: Camera subsystem power domain */
static struct powerdomain cam_44xx_pwrdm = {
	.name		  = "cam_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_CAM_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* cam_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cam_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* l3init_44xx_pwrdm: L3 initators pheripherals power domain  */
static struct powerdomain l3init_44xx_pwrdm = {
	.name		  = "l3init_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_L3INIT_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* l3init_bank1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* l3init_bank1 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* l4per_44xx_pwrdm: Target peripherals power domain */
static struct powerdomain l4per_44xx_pwrdm = {
	.name		  = "l4per_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_L4PER_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF,	/* nonretained_bank */
		[1] = PWRSTS_RET,	/* retained_bank */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* nonretained_bank */
		[1] = PWRSTS_ON,	/* retained_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/*
 * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
 * domain
 */
static struct powerdomain always_on_core_44xx_pwrdm = {
	.name		  = "always_on_core_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_ALWAYS_ON_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain cefuse_44xx_pwrdm = {
	.name		  = "cefuse_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP4430_PRM_CEFUSE_INST,
	.prcm_partition	  = OMAP4430_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/*
 * The following power domains are not under SW control
 *
 * always_on_iva
 * always_on_mpu
 * stdefuse
 */

/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap44xx[] __initdata = {
	&core_44xx_pwrdm,
	&gfx_44xx_pwrdm,
	&abe_44xx_pwrdm,
	&dss_44xx_pwrdm,
	&tesla_44xx_pwrdm,
	&wkup_44xx_pwrdm,
	&cpu0_44xx_pwrdm,
	&cpu1_44xx_pwrdm,
	&emu_44xx_pwrdm,
	&mpu_44xx_pwrdm,
	&ivahd_44xx_pwrdm,
	&cam_44xx_pwrdm,
	&l3init_44xx_pwrdm,
	&l4per_44xx_pwrdm,
	&always_on_core_44xx_pwrdm,
	&cefuse_44xx_pwrdm,
	NULL
};

void __init omap44xx_powerdomains_init(void)
{
	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
	pwrdm_register_pwrdms(powerdomains_omap44xx);
	pwrdm_complete_init();
}


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP54XX Power domains framework
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * Abhijit Pagare (abhijitpagare@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 * Paul Walmsley (paul@pwsan.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#include <linux/kernel.h>
#include <linux/init.h>

#include "powerdomain.h"

#include "prcm-common.h"
#include "prcm44xx.h"
#include "prm54xx.h"
#include "prcm_mpu54xx.h"

/* core_54xx_pwrdm: CORE power domain */
static struct powerdomain core_54xx_pwrdm = {
	.name		  = "core_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP54XX_PRM_CORE_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 5,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* core_nret_bank */
		[1] = PWRSTS_OFF_RET,	/* core_ocmram */
		[2] = PWRSTS_OFF_RET,	/* core_other_bank */
		[3] = PWRSTS_OFF_RET,	/* ipu_l2ram */
		[4] = PWRSTS_OFF_RET,	/* ipu_unicache */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_OFF_RET,	/* core_nret_bank */
		[1] = PWRSTS_OFF_RET,	/* core_ocmram */
		[2] = PWRSTS_OFF_RET,	/* core_other_bank */
		[3] = PWRSTS_OFF_RET,	/* ipu_l2ram */
		[4] = PWRSTS_OFF_RET,	/* ipu_unicache */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* abe_54xx_pwrdm: Audio back end power domain */
static struct powerdomain abe_54xx_pwrdm = {
	.name		  = "abe_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP54XX_PRM_ABE_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF,
	.banks		  = 2,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* aessmem */
		[1] = PWRSTS_OFF_RET,	/* periphmem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_OFF_RET,	/* aessmem */
		[1] = PWRSTS_OFF_RET,	/* periphmem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
static struct powerdomain coreaon_54xx_pwrdm = {
	.name		  = "coreaon_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP54XX_PRM_COREAON_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

/* dss_54xx_pwrdm: Display subsystem power domain */
static struct powerdomain dss_54xx_pwrdm = {
	.name		  = "dss_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP54XX_PRM_DSS_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* dss_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_OFF_RET,	/* dss_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
static struct powerdomain cpu0_54xx_pwrdm = {
	.name		  = "cpu0_pwrdm",
	.voltdm		  = { .name = "mpu" },
	.prcm_offs	  = OMAP54XX_PRCM_MPU_PRM_C0_INST,
	.prcm_partition	  = OMAP54XX_PRCM_MPU_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cpu0_l1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cpu0_l1 */
	},
};

/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
static struct powerdomain cpu1_54xx_pwrdm = {
	.name		  = "cpu1_pwrdm",
	.voltdm		  = { .name = "mpu" },
	.prcm_offs	  = OMAP54XX_PRCM_MPU_PRM_C1_INST,
	.prcm_partition	  = OMAP54XX_PRCM_MPU_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cpu1_l1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cpu1_l1 */
	},
};

/* emu_54xx_pwrdm: Emulation power domain */
static struct powerdomain emu_54xx_pwrdm = {
	.name		  = "emu_pwrdm",
	.voltdm		  = { .name = "wkup" },
	.prcm_offs	  = OMAP54XX_PRM_EMU_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* emu_bank */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_OFF_RET,	/* emu_bank */
	},
};

/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
static struct powerdomain mpu_54xx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.voltdm		  = { .name = "mpu" },
	.prcm_offs	  = OMAP54XX_PRM_MPU_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* mpu_l2 */
		[1] = PWRSTS_RET,	/* mpu_ram */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_OFF_RET,	/* mpu_l2 */
		[1] = PWRSTS_OFF_RET,	/* mpu_ram */
	},
};

/* custefuse_54xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain custefuse_54xx_pwrdm = {
	.name		  = "custefuse_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP54XX_PRM_CUSTEFUSE_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* dsp_54xx_pwrdm: Tesla processor power domain */
static struct powerdomain dsp_54xx_pwrdm = {
	.name		  = "dsp_pwrdm",
	.voltdm		  = { .name = "mm" },
	.prcm_offs	  = OMAP54XX_PRM_DSP_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 3,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* dsp_edma */
		[1] = PWRSTS_OFF_RET,	/* dsp_l1 */
		[2] = PWRSTS_OFF_RET,	/* dsp_l2 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_OFF_RET,	/* dsp_edma */
		[1] = PWRSTS_OFF_RET,	/* dsp_l1 */
		[2] = PWRSTS_OFF_RET,	/* dsp_l2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* cam_54xx_pwrdm: Camera subsystem power domain */
static struct powerdomain cam_54xx_pwrdm = {
	.name		  = "cam_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP54XX_PRM_CAM_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cam_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_OFF_RET,	/* cam_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* l3init_54xx_pwrdm: L3 initators pheripherals power domain  */
static struct powerdomain l3init_54xx_pwrdm = {
	.name		  = "l3init_pwrdm",
	.voltdm		  = { .name = "core" },
	.prcm_offs	  = OMAP54XX_PRM_L3INIT_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* l3init_bank1 */
		[1] = PWRSTS_OFF_RET,	/* l3init_bank2 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_OFF_RET,	/* l3init_bank1 */
		[1] = PWRSTS_OFF_RET,	/* l3init_bank2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* gpu_54xx_pwrdm: 3D accelerator power domain */
static struct powerdomain gpu_54xx_pwrdm = {
	.name		  = "gpu_pwrdm",
	.voltdm		  = { .name = "mm" },
	.prcm_offs	  = OMAP54XX_PRM_GPU_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* gpu_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_OFF_RET,	/* gpu_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* wkupaon_54xx_pwrdm: Wake-up power domain */
static struct powerdomain wkupaon_54xx_pwrdm = {
	.name		  = "wkupaon_pwrdm",
	.voltdm		  = { .name = "wkup" },
	.prcm_offs	  = OMAP54XX_PRM_WKUPAON_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* wkup_bank */
	},
};

/* iva_54xx_pwrdm: IVA-HD power domain */
static struct powerdomain iva_54xx_pwrdm = {
	.name		  = "iva_pwrdm",
	.voltdm		  = { .name = "mm" },
	.prcm_offs	  = OMAP54XX_PRM_IVA_INST,
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF,
	.banks		  = 4,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* hwa_mem */
		[1] = PWRSTS_OFF_RET,	/* sl2_mem */
		[2] = PWRSTS_OFF_RET,	/* tcm1_mem */
		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_OFF_RET,	/* hwa_mem */
		[1] = PWRSTS_OFF_RET,	/* sl2_mem */
		[2] = PWRSTS_OFF_RET,	/* tcm1_mem */
		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/*
 * The following power domains are not under SW control
 *
 * mpuaon
 * mmaon
 */

/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap54xx[] __initdata = {
	&core_54xx_pwrdm,
	&abe_54xx_pwrdm,
	&coreaon_54xx_pwrdm,
	&dss_54xx_pwrdm,
	&cpu0_54xx_pwrdm,
	&cpu1_54xx_pwrdm,
	&emu_54xx_pwrdm,
	&mpu_54xx_pwrdm,
	&custefuse_54xx_pwrdm,
	&dsp_54xx_pwrdm,
	&cam_54xx_pwrdm,
	&l3init_54xx_pwrdm,
	&gpu_54xx_pwrdm,
	&wkupaon_54xx_pwrdm,
	&iva_54xx_pwrdm,
	NULL
};

void __init omap54xx_powerdomains_init(void)
{
	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
	pwrdm_register_pwrdms(powerdomains_omap54xx);
	pwrdm_complete_init();
}


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * DRA7xx Power domains framework
 *
 * Copyright (C) 2009-2013 Texas Instruments, Inc.
 * Copyright (C) 2009-2011 Nokia Corporation
 *
 * Generated by code originally written by:
 * Abhijit Pagare (abhijitpagare@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 * Paul Walmsley (paul@pwsan.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#include <linux/kernel.h>
#include <linux/init.h>

#include "powerdomain.h"

#include "prcm-common.h"
#include "prcm44xx.h"
#include "prm7xx.h"
#include "prcm_mpu7xx.h"
#include "soc.h"

/* iva_7xx_pwrdm: IVA-HD power domain */
static struct powerdomain iva_7xx_pwrdm = {
	.name		  = "iva_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_IVA_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 4,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* hwa_mem */
		[1] = PWRSTS_ON,	/* sl2_mem */
		[2] = PWRSTS_ON,	/* tcm1_mem */
		[3] = PWRSTS_ON,	/* tcm2_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* rtc_7xx_pwrdm:  */
static struct powerdomain rtc_7xx_pwrdm = {
	.name		  = "rtc_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_RTC_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain custefuse_7xx_pwrdm = {
	.name		  = "custefuse_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_CUSTEFUSE_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* custefuse_aon_7xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain custefuse_aon_7xx_pwrdm = {
	.name		  = "custefuse_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_CUSTEFUSE_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

/* ipu_7xx_pwrdm: Audio back end power domain */
static struct powerdomain ipu_7xx_pwrdm = {
	.name		  = "ipu_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_IPU_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 2,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* aessmem */
		[1] = PWRSTS_ON,	/* periphmem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* dss_7xx_pwrdm: Display subsystem power domain */
static struct powerdomain dss_7xx_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_DSS_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* dss_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* l4per_7xx_pwrdm: Target peripherals power domain */
static struct powerdomain l4per_7xx_pwrdm = {
	.name		  = "l4per_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_L4PER_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 2,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* nonretained_bank */
		[1] = PWRSTS_ON,	/* retained_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* gpu_7xx_pwrdm: 3D accelerator power domain */
static struct powerdomain gpu_7xx_pwrdm = {
	.name		  = "gpu_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_GPU_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* gpu_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* wkupaon_7xx_pwrdm: Wake-up power domain */
static struct powerdomain wkupaon_7xx_pwrdm = {
	.name		  = "wkupaon_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_WKUPAON_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* wkup_bank */
	},
};

/* core_7xx_pwrdm: CORE power domain */
static struct powerdomain core_7xx_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_CORE_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 5,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* core_nret_bank */
		[1] = PWRSTS_ON,	/* core_ocmram */
		[2] = PWRSTS_ON,	/* core_other_bank */
		[3] = PWRSTS_ON,	/* ipu_l2ram */
		[4] = PWRSTS_ON,	/* ipu_unicache */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
static struct powerdomain coreaon_7xx_pwrdm = {
	.name		  = "coreaon_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_COREAON_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
static struct powerdomain cpu0_7xx_pwrdm = {
	.name		  = "cpu0_pwrdm",
	.prcm_offs	  = DRA7XX_MPU_PRCM_PRM_C0_INST,
	.prcm_partition	  = DRA7XX_MPU_PRCM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cpu0_l1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cpu0_l1 */
	},
};

/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
static struct powerdomain cpu1_7xx_pwrdm = {
	.name		  = "cpu1_pwrdm",
	.prcm_offs	  = DRA7XX_MPU_PRCM_PRM_C1_INST,
	.prcm_partition	  = DRA7XX_MPU_PRCM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cpu1_l1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cpu1_l1 */
	},
};

/* vpe_7xx_pwrdm:  */
static struct powerdomain vpe_7xx_pwrdm = {
	.name		  = "vpe_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_VPE_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* vpe_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
static struct powerdomain mpu_7xx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_MPU_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* mpu_l2 */
		[1] = PWRSTS_RET,	/* mpu_ram */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* mpu_l2 */
		[1] = PWRSTS_ON,	/* mpu_ram */
	},
};

/* l3init_7xx_pwrdm: L3 initators pheripherals power domain  */
static struct powerdomain l3init_7xx_pwrdm = {
	.name		  = "l3init_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_L3INIT_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 3,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* gmac_bank */
		[1] = PWRSTS_ON,	/* l3init_bank1 */
		[2] = PWRSTS_ON,	/* l3init_bank2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* eve3_7xx_pwrdm:  */
static struct powerdomain eve3_7xx_pwrdm = {
	.name		  = "eve3_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EVE3_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* eve3_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* emu_7xx_pwrdm: Emulation power domain */
static struct powerdomain emu_7xx_pwrdm = {
	.name		  = "emu_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EMU_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* emu_bank */
	},
};

/* dsp2_7xx_pwrdm:  */
static struct powerdomain dsp2_7xx_pwrdm = {
	.name		  = "dsp2_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_DSP2_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 3,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* dsp2_edma */
		[1] = PWRSTS_ON,	/* dsp2_l1 */
		[2] = PWRSTS_ON,	/* dsp2_l2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* dsp1_7xx_pwrdm: Tesla processor power domain */
static struct powerdomain dsp1_7xx_pwrdm = {
	.name		  = "dsp1_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_DSP1_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 3,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* dsp1_edma */
		[1] = PWRSTS_ON,	/* dsp1_l1 */
		[2] = PWRSTS_ON,	/* dsp1_l2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* cam_7xx_pwrdm: Camera subsystem power domain */
static struct powerdomain cam_7xx_pwrdm = {
	.name		  = "cam_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_CAM_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* vip_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* eve4_7xx_pwrdm:  */
static struct powerdomain eve4_7xx_pwrdm = {
	.name		  = "eve4_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EVE4_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* eve4_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* eve2_7xx_pwrdm:  */
static struct powerdomain eve2_7xx_pwrdm = {
	.name		  = "eve2_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EVE2_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* eve2_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* eve1_7xx_pwrdm:  */
static struct powerdomain eve1_7xx_pwrdm = {
	.name		  = "eve1_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EVE1_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* eve1_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/*
 * The following power domains are not under SW control
 *
 * mpuaon
 * mmaon
 */

/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_dra7xx[] __initdata = {
	&iva_7xx_pwrdm,
	&rtc_7xx_pwrdm,
	&ipu_7xx_pwrdm,
	&dss_7xx_pwrdm,
	&l4per_7xx_pwrdm,
	&gpu_7xx_pwrdm,
	&wkupaon_7xx_pwrdm,
	&core_7xx_pwrdm,
	&coreaon_7xx_pwrdm,
	&cpu0_7xx_pwrdm,
	&cpu1_7xx_pwrdm,
	&vpe_7xx_pwrdm,
	&mpu_7xx_pwrdm,
	&l3init_7xx_pwrdm,
	&eve3_7xx_pwrdm,
	&emu_7xx_pwrdm,
	&dsp2_7xx_pwrdm,
	&dsp1_7xx_pwrdm,
	&cam_7xx_pwrdm,
	&eve4_7xx_pwrdm,
	&eve2_7xx_pwrdm,
	&eve1_7xx_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_dra76x[] __initdata = {
	&custefuse_aon_7xx_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_dra74x[] __initdata = {
	&custefuse_7xx_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_dra72x[] __initdata = {
	&custefuse_aon_7xx_pwrdm,
	NULL
};

void __init dra7xx_powerdomains_init(void)
{
	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
	pwrdm_register_pwrdms(powerdomains_dra7xx);

	if (soc_is_dra76x())
		pwrdm_register_pwrdms(powerdomains_dra76x);
	else if (soc_is_dra74x())
		pwrdm_register_pwrdms(powerdomains_dra74x);
	else if (soc_is_dra72x())
		pwrdm_register_pwrdms(powerdomains_dra72x);

	pwrdm_complete_init();
}


code:
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H

/*
 * OMAP2/3 PRCM base and module definitions
 *
 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Written by Paul Walmsley
 */

/* Module offsets from both CM_BASE & PRM_BASE */

/*
 * Offsets that are the same on 24xx and 34xx
 *
 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
 */
#define OCP_MOD						0x000
#define MPU_MOD						0x100
#define CORE_MOD					0x200
#define GFX_MOD						0x300
#define WKUP_MOD					0x400
#define PLL_MOD						0x500

/* Chip-specific module offsets */
#define OMAP24XX_GR_MOD					OCP_MOD
#define OMAP24XX_DSP_MOD				0x800

#define OMAP2430_MDM_MOD				0xc00

/* IVA2 module is < base on 3430 */
#define OMAP3430_IVA2_MOD				-0x800
#define OMAP3430ES2_SGX_MOD				GFX_MOD
#define OMAP3430_CCR_MOD				PLL_MOD
#define OMAP3430_DSS_MOD				0x600
#define OMAP3430_CAM_MOD				0x700
#define OMAP3430_PER_MOD				0x800
#define OMAP3430_EMU_MOD				0x900
#define OMAP3430_GR_MOD					0xa00
#define OMAP3430_NEON_MOD				0xb00
#define OMAP3430ES2_USBHOST_MOD				0xc00

/*
 * TI81XX PRM module offsets
 */
#define TI814X_PRM_DSP_MOD				0x0a00
#define TI814X_PRM_HDVICP_MOD				0x0c00
#define TI814X_PRM_ISP_MOD				0x0d00
#define TI814X_PRM_HDVPSS_MOD				0x0e00
#define TI814X_PRM_GFX_MOD				0x0f00

#define TI81XX_PRM_DEVICE_MOD			0x0000
#define TI816X_PRM_ACTIVE_MOD			0x0a00
#define TI81XX_PRM_DEFAULT_MOD			0x0b00
#define TI816X_PRM_IVAHD0_MOD			0x0c00
#define TI816X_PRM_IVAHD1_MOD			0x0d00
#define TI816X_PRM_IVAHD2_MOD			0x0e00
#define TI816X_PRM_SGX_MOD				0x0f00
#define TI81XX_PRM_ALWON_MOD			0x1800

/* 24XX register bits shared between CM & PRM registers */

/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
#define OMAP2420_EN_MMC_SHIFT				26
#define OMAP2420_EN_MMC_MASK				(1 << 26)
#define OMAP24XX_EN_UART2_SHIFT				22
#define OMAP24XX_EN_UART2_MASK				(1 << 22)
#define OMAP24XX_EN_UART1_SHIFT				21
#define OMAP24XX_EN_UART1_MASK				(1 << 21)
#define OMAP24XX_EN_MCSPI2_SHIFT			18
#define OMAP24XX_EN_MCSPI2_MASK				(1 << 18)
#define OMAP24XX_EN_MCSPI1_SHIFT			17
#define OMAP24XX_EN_MCSPI1_MASK				(1 << 17)
#define OMAP24XX_EN_MCBSP2_SHIFT			16
#define OMAP24XX_EN_MCBSP2_MASK				(1 << 16)
#define OMAP24XX_EN_MCBSP1_SHIFT			15
#define OMAP24XX_EN_MCBSP1_MASK				(1 << 15)
#define OMAP24XX_EN_GPT12_SHIFT				14
#define OMAP24XX_EN_GPT12_MASK				(1 << 14)
#define OMAP24XX_EN_GPT11_SHIFT				13
#define OMAP24XX_EN_GPT11_MASK				(1 << 13)
#define OMAP24XX_EN_GPT10_SHIFT				12
#define OMAP24XX_EN_GPT10_MASK				(1 << 12)
#define OMAP24XX_EN_GPT9_SHIFT				11
#define OMAP24XX_EN_GPT9_MASK				(1 << 11)
#define OMAP24XX_EN_GPT8_SHIFT				10
#define OMAP24XX_EN_GPT8_MASK				(1 << 10)
#define OMAP24XX_EN_GPT7_SHIFT				9
#define OMAP24XX_EN_GPT7_MASK				(1 << 9)
#define OMAP24XX_EN_GPT6_SHIFT				8
#define OMAP24XX_EN_GPT6_MASK				(1 << 8)
#define OMAP24XX_EN_GPT5_SHIFT				7
#define OMAP24XX_EN_GPT5_MASK				(1 << 7)
#define OMAP24XX_EN_GPT4_SHIFT				6
#define OMAP24XX_EN_GPT4_MASK				(1 << 6)
#define OMAP24XX_EN_GPT3_SHIFT				5
#define OMAP24XX_EN_GPT3_MASK				(1 << 5)
#define OMAP24XX_EN_GPT2_SHIFT				4
#define OMAP24XX_EN_GPT2_MASK				(1 << 4)
#define OMAP2420_EN_VLYNQ_SHIFT				3
#define OMAP2420_EN_VLYNQ_MASK				(1 << 3)

/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
#define OMAP2430_EN_GPIO5_SHIFT				10
#define OMAP2430_EN_GPIO5_MASK				(1 << 10)
#define OMAP2430_EN_MCSPI3_SHIFT			9
#define OMAP2430_EN_MCSPI3_MASK				(1 << 9)
#define OMAP2430_EN_MMCHS2_SHIFT			8
#define OMAP2430_EN_MMCHS2_MASK				(1 << 8)
#define OMAP2430_EN_MMCHS1_SHIFT			7
#define OMAP2430_EN_MMCHS1_MASK				(1 << 7)
#define OMAP24XX_EN_UART3_SHIFT				2
#define OMAP24XX_EN_UART3_MASK				(1 << 2)
#define OMAP24XX_EN_USB_SHIFT				0
#define OMAP24XX_EN_USB_MASK				(1 << 0)

/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
#define OMAP2430_EN_MDM_INTC_SHIFT			11
#define OMAP2430_EN_MDM_INTC_MASK			(1 << 11)
#define OMAP2430_EN_USBHS_SHIFT				6
#define OMAP2430_EN_USBHS_MASK				(1 << 6)
#define OMAP24XX_EN_GPMC_SHIFT				1
#define OMAP24XX_EN_GPMC_MASK				(1 << 1)

/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
#define OMAP2420_ST_MMC_SHIFT				26
#define OMAP2420_ST_MMC_MASK				(1 << 26)
#define OMAP24XX_ST_UART2_SHIFT				22
#define OMAP24XX_ST_UART2_MASK				(1 << 22)
#define OMAP24XX_ST_UART1_SHIFT				21
#define OMAP24XX_ST_UART1_MASK				(1 << 21)
#define OMAP24XX_ST_MCSPI2_SHIFT			18
#define OMAP24XX_ST_MCSPI2_MASK				(1 << 18)
#define OMAP24XX_ST_MCSPI1_SHIFT			17
#define OMAP24XX_ST_MCSPI1_MASK				(1 << 17)
#define OMAP24XX_ST_MCBSP2_SHIFT			16
#define OMAP24XX_ST_MCBSP2_MASK				(1 << 16)
#define OMAP24XX_ST_MCBSP1_SHIFT			15
#define OMAP24XX_ST_MCBSP1_MASK				(1 << 15)
#define OMAP24XX_ST_GPT12_SHIFT				14
#define OMAP24XX_ST_GPT12_MASK				(1 << 14)
#define OMAP24XX_ST_GPT11_SHIFT				13
#define OMAP24XX_ST_GPT11_MASK				(1 << 13)
#define OMAP24XX_ST_GPT10_SHIFT				12
#define OMAP24XX_ST_GPT10_MASK				(1 << 12)
#define OMAP24XX_ST_GPT9_SHIFT				11
#define OMAP24XX_ST_GPT9_MASK				(1 << 11)
#define OMAP24XX_ST_GPT8_SHIFT				10
#define OMAP24XX_ST_GPT8_MASK				(1 << 10)
#define OMAP24XX_ST_GPT7_SHIFT				9
#define OMAP24XX_ST_GPT7_MASK				(1 << 9)
#define OMAP24XX_ST_GPT6_SHIFT				8
#define OMAP24XX_ST_GPT6_MASK				(1 << 8)
#define OMAP24XX_ST_GPT5_SHIFT				7
#define OMAP24XX_ST_GPT5_MASK				(1 << 7)
#define OMAP24XX_ST_GPT4_SHIFT				6
#define OMAP24XX_ST_GPT4_MASK				(1 << 6)
#define OMAP24XX_ST_GPT3_SHIFT				5
#define OMAP24XX_ST_GPT3_MASK				(1 << 5)
#define OMAP24XX_ST_GPT2_SHIFT				4
#define OMAP24XX_ST_GPT2_MASK				(1 << 4)
#define OMAP2420_ST_VLYNQ_SHIFT				3
#define OMAP2420_ST_VLYNQ_MASK				(1 << 3)

/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
#define OMAP2430_ST_MDM_INTC_SHIFT			11
#define OMAP2430_ST_MDM_INTC_MASK			(1 << 11)
#define OMAP2430_ST_GPIO5_SHIFT				10
#define OMAP2430_ST_GPIO5_MASK				(1 << 10)
#define OMAP2430_ST_MCSPI3_SHIFT			9
#define OMAP2430_ST_MCSPI3_MASK				(1 << 9)
#define OMAP2430_ST_MMCHS2_SHIFT			8
#define OMAP2430_ST_MMCHS2_MASK				(1 << 8)
#define OMAP2430_ST_MMCHS1_SHIFT			7
#define OMAP2430_ST_MMCHS1_MASK				(1 << 7)
#define OMAP2430_ST_USBHS_SHIFT				6
#define OMAP2430_ST_USBHS_MASK				(1 << 6)
#define OMAP24XX_ST_UART3_SHIFT				2
#define OMAP24XX_ST_UART3_MASK				(1 << 2)
#define OMAP24XX_ST_USB_SHIFT				0
#define OMAP24XX_ST_USB_MASK				(1 << 0)

/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
#define OMAP24XX_EN_GPIOS_SHIFT				2
#define OMAP24XX_EN_GPIOS_MASK				(1 << 2)
#define OMAP24XX_EN_GPT1_SHIFT				0
#define OMAP24XX_EN_GPT1_MASK				(1 << 0)

/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
#define OMAP24XX_ST_GPIOS_SHIFT				2
#define OMAP24XX_ST_GPIOS_MASK				(1 << 2)
#define OMAP24XX_ST_32KSYNC_SHIFT			1
#define OMAP24XX_ST_32KSYNC_MASK			(1 << 1)
#define OMAP24XX_ST_GPT1_SHIFT				0
#define OMAP24XX_ST_GPT1_MASK				(1 << 0)

/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
#define OMAP2430_ST_MDM_SHIFT				0
#define OMAP2430_ST_MDM_MASK				(1 << 0)

/* 3430 register bits shared between CM & PRM registers */

/* CM_REVISION, PRM_REVISION shared bits */
#define OMAP3430_REV_SHIFT				0
#define OMAP3430_REV_MASK				(0xff << 0)

/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
#define OMAP3430_AUTOIDLE_MASK				(1 << 0)

/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
#define OMAP3430_EN_MMC3_MASK				(1 << 30)
#define OMAP3430_EN_MMC3_SHIFT				30
#define OMAP3430_EN_MMC2_MASK				(1 << 25)
#define OMAP3430_EN_MMC2_SHIFT				25
#define OMAP3430_EN_MMC1_MASK				(1 << 24)
#define OMAP3430_EN_MMC1_SHIFT				24
#define AM35XX_EN_UART4_MASK				(1 << 23)
#define AM35XX_EN_UART4_SHIFT				23
#define OMAP3430_EN_MCSPI4_MASK				(1 << 21)
#define OMAP3430_EN_MCSPI4_SHIFT			21
#define OMAP3430_EN_MCSPI3_MASK				(1 << 20)
#define OMAP3430_EN_MCSPI3_SHIFT			20
#define OMAP3430_EN_MCSPI2_MASK				(1 << 19)
#define OMAP3430_EN_MCSPI2_SHIFT			19
#define OMAP3430_EN_MCSPI1_MASK				(1 << 18)
#define OMAP3430_EN_MCSPI1_SHIFT			18
#define OMAP3430_EN_I2C3_MASK				(1 << 17)
#define OMAP3430_EN_I2C3_SHIFT				17
#define OMAP3430_EN_I2C2_MASK				(1 << 16)
#define OMAP3430_EN_I2C2_SHIFT				16
#define OMAP3430_EN_I2C1_MASK				(1 << 15)
#define OMAP3430_EN_I2C1_SHIFT				15
#define OMAP3430_EN_UART2_MASK				(1 << 14)
#define OMAP3430_EN_UART2_SHIFT				14
#define OMAP3430_EN_UART1_MASK				(1 << 13)
#define OMAP3430_EN_UART1_SHIFT				13
#define OMAP3430_EN_GPT11_MASK				(1 << 12)
#define OMAP3430_EN_GPT11_SHIFT				12
#define OMAP3430_EN_GPT10_MASK				(1 << 11)
#define OMAP3430_EN_GPT10_SHIFT				11
#define OMAP3430_EN_MCBSP5_MASK				(1 << 10)
#define OMAP3430_EN_MCBSP5_SHIFT			10
#define OMAP3430_EN_MCBSP1_MASK				(1 << 9)
#define OMAP3430_EN_MCBSP1_SHIFT			9
#define OMAP3430_EN_FSHOSTUSB_MASK			(1 << 5)
#define OMAP3430_EN_FSHOSTUSB_SHIFT			5
#define OMAP3430_EN_D2D_MASK				(1 << 3)
#define OMAP3430_EN_D2D_SHIFT				3

/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
#define OMAP3430_EN_HSOTGUSB_MASK			(1 << 4)
#define OMAP3430_EN_HSOTGUSB_SHIFT			4

/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
#define OMAP3430_ST_MMC3_SHIFT				30
#define OMAP3430_ST_MMC3_MASK				(1 << 30)
#define OMAP3430_ST_MMC2_SHIFT				25
#define OMAP3430_ST_MMC2_MASK				(1 << 25)
#define OMAP3430_ST_MMC1_SHIFT				24
#define OMAP3430_ST_MMC1_MASK				(1 << 24)
#define OMAP3430_ST_MCSPI4_SHIFT			21
#define OMAP3430_ST_MCSPI4_MASK				(1 << 21)
#define OMAP3430_ST_MCSPI3_SHIFT			20
#define OMAP3430_ST_MCSPI3_MASK				(1 << 20)
#define OMAP3430_ST_MCSPI2_SHIFT			19
#define OMAP3430_ST_MCSPI2_MASK				(1 << 19)
#define OMAP3430_ST_MCSPI1_SHIFT			18
#define OMAP3430_ST_MCSPI1_MASK				(1 << 18)
#define OMAP3430_ST_I2C3_SHIFT				17
#define OMAP3430_ST_I2C3_MASK				(1 << 17)
#define OMAP3430_ST_I2C2_SHIFT				16
#define OMAP3430_ST_I2C2_MASK				(1 << 16)
#define OMAP3430_ST_I2C1_SHIFT				15
#define OMAP3430_ST_I2C1_MASK				(1 << 15)
#define OMAP3430_ST_UART2_SHIFT				14
#define OMAP3430_ST_UART2_MASK				(1 << 14)
#define OMAP3430_ST_UART1_SHIFT				13
#define OMAP3430_ST_UART1_MASK				(1 << 13)
#define OMAP3430_ST_GPT11_SHIFT				12
#define OMAP3430_ST_GPT11_MASK				(1 << 12)
#define OMAP3430_ST_GPT10_SHIFT				11
#define OMAP3430_ST_GPT10_MASK				(1 << 11)
#define OMAP3430_ST_MCBSP5_SHIFT			10
#define OMAP3430_ST_MCBSP5_MASK				(1 << 10)
#define OMAP3430_ST_MCBSP1_SHIFT			9
#define OMAP3430_ST_MCBSP1_MASK				(1 << 9)
#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT			5
#define OMAP3430ES1_ST_FSHOSTUSB_MASK			(1 << 5)
#define OMAP3430ES1_ST_HSOTGUSB_SHIFT			4
#define OMAP3430ES1_ST_HSOTGUSB_MASK			(1 << 4)
#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT		5
#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK		(1 << 5)
#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT		4
#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK		(1 << 4)
#define OMAP3430_ST_D2D_SHIFT				3
#define OMAP3430_ST_D2D_MASK				(1 << 3)

/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
#define OMAP3430_EN_GPIO1_MASK				(1 << 3)
#define OMAP3430_EN_GPIO1_SHIFT				3
#define OMAP3430_EN_GPT12_MASK				(1 << 1)
#define OMAP3430_EN_GPT12_SHIFT				1
#define OMAP3430_EN_GPT1_MASK				(1 << 0)
#define OMAP3430_EN_GPT1_SHIFT				0

/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
#define OMAP3430_EN_SR2_MASK				(1 << 7)
#define OMAP3430_EN_SR2_SHIFT				7
#define OMAP3430_EN_SR1_MASK				(1 << 6)
#define OMAP3430_EN_SR1_SHIFT				6

/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
#define OMAP3430_EN_GPT12_MASK				(1 << 1)
#define OMAP3430_EN_GPT12_SHIFT				1

/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
#define OMAP3430_ST_SR2_SHIFT				7
#define OMAP3430_ST_SR2_MASK				(1 << 7)
#define OMAP3430_ST_SR1_SHIFT				6
#define OMAP3430_ST_SR1_MASK				(1 << 6)
#define OMAP3430_ST_GPIO1_SHIFT				3
#define OMAP3430_ST_GPIO1_MASK				(1 << 3)
#define OMAP3430_ST_32KSYNC_SHIFT			2
#define OMAP3430_ST_32KSYNC_MASK			(1 << 2)
#define OMAP3430_ST_GPT12_SHIFT				1
#define OMAP3430_ST_GPT12_MASK				(1 << 1)
#define OMAP3430_ST_GPT1_SHIFT				0
#define OMAP3430_ST_GPT1_MASK				(1 << 0)

/*
 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
 */
#define OMAP3430_EN_MPU_MASK				(1 << 1)
#define OMAP3430_EN_MPU_SHIFT				1

/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */

#define OMAP3630_EN_UART4_MASK				(1 << 18)
#define OMAP3630_EN_UART4_SHIFT				18
#define OMAP3430_EN_GPIO6_MASK				(1 << 17)
#define OMAP3430_EN_GPIO6_SHIFT				17
#define OMAP3430_EN_GPIO5_MASK				(1 << 16)
#define OMAP3430_EN_GPIO5_SHIFT				16
#define OMAP3430_EN_GPIO4_MASK				(1 << 15)
#define OMAP3430_EN_GPIO4_SHIFT				15
#define OMAP3430_EN_GPIO3_MASK				(1 << 14)
#define OMAP3430_EN_GPIO3_SHIFT				14
#define OMAP3430_EN_GPIO2_MASK				(1 << 13)
#define OMAP3430_EN_GPIO2_SHIFT				13
#define OMAP3430_EN_UART3_MASK				(1 << 11)
#define OMAP3430_EN_UART3_SHIFT				11
#define OMAP3430_EN_GPT9_MASK				(1 << 10)
#define OMAP3430_EN_GPT9_SHIFT				10
#define OMAP3430_EN_GPT8_MASK				(1 << 9)
#define OMAP3430_EN_GPT8_SHIFT				9
#define OMAP3430_EN_GPT7_MASK				(1 << 8)
#define OMAP3430_EN_GPT7_SHIFT				8
#define OMAP3430_EN_GPT6_MASK				(1 << 7)
#define OMAP3430_EN_GPT6_SHIFT				7
#define OMAP3430_EN_GPT5_MASK				(1 << 6)
#define OMAP3430_EN_GPT5_SHIFT				6
#define OMAP3430_EN_GPT4_MASK				(1 << 5)
#define OMAP3430_EN_GPT4_SHIFT				5
#define OMAP3430_EN_GPT3_MASK				(1 << 4)
#define OMAP3430_EN_GPT3_SHIFT				4
#define OMAP3430_EN_GPT2_MASK				(1 << 3)
#define OMAP3430_EN_GPT2_SHIFT				3

/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
 * be ST_* bits instead? */
#define OMAP3430_EN_MCBSP4_MASK				(1 << 2)
#define OMAP3430_EN_MCBSP4_SHIFT			2
#define OMAP3430_EN_MCBSP3_MASK				(1 << 1)
#define OMAP3430_EN_MCBSP3_SHIFT			1
#define OMAP3430_EN_MCBSP2_MASK				(1 << 0)
#define OMAP3430_EN_MCBSP2_SHIFT			0

/* CM_IDLEST_PER, PM_WKST_PER shared bits */
#define OMAP3630_ST_UART4_SHIFT				18
#define OMAP3630_ST_UART4_MASK				(1 << 18)
#define OMAP3430_ST_GPIO6_SHIFT				17
#define OMAP3430_ST_GPIO6_MASK				(1 << 17)
#define OMAP3430_ST_GPIO5_SHIFT				16
#define OMAP3430_ST_GPIO5_MASK				(1 << 16)
#define OMAP3430_ST_GPIO4_SHIFT				15
#define OMAP3430_ST_GPIO4_MASK				(1 << 15)
#define OMAP3430_ST_GPIO3_SHIFT				14
#define OMAP3430_ST_GPIO3_MASK				(1 << 14)
#define OMAP3430_ST_GPIO2_SHIFT				13
#define OMAP3430_ST_GPIO2_MASK				(1 << 13)
#define OMAP3430_ST_UART3_SHIFT				11
#define OMAP3430_ST_UART3_MASK				(1 << 11)
#define OMAP3430_ST_GPT9_SHIFT				10
#define OMAP3430_ST_GPT9_MASK				(1 << 10)
#define OMAP3430_ST_GPT8_SHIFT				9
#define OMAP3430_ST_GPT8_MASK				(1 << 9)
#define OMAP3430_ST_GPT7_SHIFT				8
#define OMAP3430_ST_GPT7_MASK				(1 << 8)
#define OMAP3430_ST_GPT6_SHIFT				7
#define OMAP3430_ST_GPT6_MASK				(1 << 7)
#define OMAP3430_ST_GPT5_SHIFT				6
#define OMAP3430_ST_GPT5_MASK				(1 << 6)
#define OMAP3430_ST_GPT4_SHIFT				5
#define OMAP3430_ST_GPT4_MASK				(1 << 5)
#define OMAP3430_ST_GPT3_SHIFT				4
#define OMAP3430_ST_GPT3_MASK				(1 << 4)
#define OMAP3430_ST_GPT2_SHIFT				3
#define OMAP3430_ST_GPT2_MASK				(1 << 3)

/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
#define OMAP3430_EN_CORE_SHIFT				0
#define OMAP3430_EN_CORE_MASK				(1 << 0)

/*
 * Maximum time(us) it takes to output the signal WUCLKOUT of the last
 * pad of the I/O ring after asserting WUCLKIN high.  Tero measured
 * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4
 * microseconds on OMAP4, so this timeout may be too high.
 */
#define MAX_IOPAD_LATCH_TIME			100
# ifndef __ASSEMBLER__

#include <linux/delay.h>

/**
 * omap_test_timeout - busy-loop, testing a condition
 * @cond: condition to test until it evaluates to true
 * @timeout: maximum number of microseconds in the timeout
 * @index: loop index (integer)
 *
 * Loop waiting for @cond to become true or until at least @timeout
 * microseconds have passed.  To use, define some integer @index in the
 * calling code.  After running, if @index == @timeout, then the loop has
 * timed out.
 */
#define omap_test_timeout(cond, timeout, index)			\
({								\
	for (index = 0; index < timeout; index++) {		\
		if (cond)					\
			break;					\
		udelay(1);					\
	}							\
})

/**
 * struct omap_prcm_irq - describes a PRCM interrupt bit
 * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
 * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
 * @priority: should this interrupt be handled before @priority=false IRQs?
 *
 * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
 * On systems with multiple PRM MPU IRQ registers, the bitfields read from
 * the registers are concatenated, so @offset could be > 31 on these systems -
 * see omap_prm_irq_handler() for more details.  I/O ring interrupts should
 * have @priority set to true.
 */
struct omap_prcm_irq {
	const char *name;
	unsigned int offset;
	bool priority;
};

/**
 * struct omap_prcm_irq_setup - PRCM interrupt controller details
 * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
 * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
 * @pm_ctrl: PRM register offset for the PRM_IO_PMCTRL register
 * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
 * @nr_irqs: number of entries in the @irqs array
 * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
 * @irq: MPU IRQ asserted when a PRCM interrupt arrives
 * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
 * @ocp_barrier: fn ptr to force buffered PRM writes to complete
 * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
 * @restore_irqen: fn ptr to save and clear IRQENABLE regs
 * @reconfigure_io_chain: fn ptr to reconfigure IO chain
 * @saved_mask: IRQENABLE regs are saved here during suspend
 * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
 * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
 * @suspended: set to true after Linux suspend code has called our ->prepare()
 * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
 *
 * @saved_mask, @priority_mask, @base_irq, @suspended, and
 * @suspend_save_flag are populated dynamically, and are not to be
 * specified in static initializers.
 */
struct omap_prcm_irq_setup {
	u16 ack;
	u16 mask;
	u16 pm_ctrl;
	u8 nr_regs;
	u8 nr_irqs;
	const struct omap_prcm_irq *irqs;
	int irq;
	void (*read_pending_irqs)(unsigned long *events);
	void (*ocp_barrier)(void);
	void (*save_and_clear_irqen)(u32 *saved_mask);
	void (*restore_irqen)(u32 *saved_mask);
	void (*reconfigure_io_chain)(void);
	u32 *saved_mask;
	u32 *priority_mask;
	int base_irq;
	bool suspended;
	bool suspend_save_flag;
};

/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
#define OMAP_PRCM_IRQ(_name, _offset, _priority) {	\
	.name = _name,					\
	.offset = _offset,				\
	.priority = _priority				\
	}

struct omap_domain_base {
	u32 pa;
	void __iomem *va;
	s16 offset;
};

/**
 * struct omap_prcm_init_data - PRCM driver init data
 * @index: clock memory mapping index to be used
 * @mem: IO mem pointer for this module
 * @phys: IO mem physical base address for this module
 * @offset: module base address offset from the IO base
 * @flags: PRCM module init flags
 * @device_inst_offset: device instance offset within the module address space
 * @init: low level PRCM init function for this module
 * @np: device node for this PRCM module
 */
struct omap_prcm_init_data {
	int index;
	void __iomem *mem;
	u32 phys;
	s16 offset;
	u16 flags;
	s32 device_inst_offset;
	int (*init)(const struct omap_prcm_init_data *data);
	struct device_node *np;
};

extern void omap_prcm_irq_cleanup(void);
extern int omap_prcm_register_chain_handler(
	struct omap_prcm_irq_setup *irq_setup);
extern int omap_prcm_event_to_irq(const char *event);
extern void omap_prcm_irq_prepare(void);
extern void omap_prcm_irq_complete(void);

# endif

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * AM43x PRCM defines
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 */

#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H

#define AM43XX_PRM_PARTITION				1
#define AM43XX_CM_PARTITION				1

/* PRM instances */
#define AM43XX_PRM_OCP_SOCKET_INST			0x0000
#define AM43XX_PRM_MPU_INST				0x0300
#define AM43XX_PRM_GFX_INST				0x0400
#define AM43XX_PRM_RTC_INST				0x0500
#define AM43XX_PRM_TAMPER_INST				0x0600
#define AM43XX_PRM_CEFUSE_INST				0x0700
#define AM43XX_PRM_PER_INST				0x0800
#define AM43XX_PRM_WKUP_INST				0x2000
#define AM43XX_PRM_DEVICE_INST				0x4000

/* PRM_IRQ offsets */
#define AM43XX_PRM_IRQSTATUS_MPU_OFFSET			0x0004
#define AM43XX_PRM_IRQENABLE_MPU_OFFSET			0x0008

/* Other PRM offsets */
#define AM43XX_PRM_IO_PMCTRL_OFFSET			0x0024

/* CM instances */
#define AM43XX_CM_WKUP_INST				0x2800
#define AM43XX_CM_MPU_INST				0x8300
#define AM43XX_CM_GFX_INST				0x8400
#define AM43XX_CM_RTC_INST				0x8500
#define AM43XX_CM_TAMPER_INST				0x8600
#define AM43XX_CM_CEFUSE_INST				0x8700
#define AM43XX_CM_PER_INST				0x8800

/* CD offsets */
#define AM43XX_CM_WKUP_L3_AON_CDOFFS			0x0000
#define AM43XX_CM_WKUP_L3S_TSC_CDOFFS			0x0100
#define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS		0x0200
#define AM43XX_CM_WKUP_WKUP_CDOFFS			0x0300
#define AM43XX_CM_MPU_MPU_CDOFFS			0x0000
#define AM43XX_CM_GFX_GFX_L3_CDOFFS			0x0000
#define AM43XX_CM_RTC_RTC_CDOFFS			0x0000
#define AM43XX_CM_TAMPER_TAMPER_CDOFFS			0x0000
#define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS			0x0000
#define AM43XX_CM_PER_L3_CDOFFS				0x0000
#define AM43XX_CM_PER_L3S_CDOFFS			0x0200
#define AM43XX_CM_PER_ICSS_CDOFFS			0x0300
#define AM43XX_CM_PER_L4LS_CDOFFS			0x0400
#define AM43XX_CM_PER_EMIF_CDOFFS			0x0700
#define AM43XX_CM_PER_LCDC_CDOFFS			0x0800
#define AM43XX_CM_PER_DSS_CDOFFS			0x0a00
#define AM43XX_CM_PER_CPSW_CDOFFS			0x0b00
#define AM43XX_CM_PER_OCPWP_L3_CDOFFS			0x0c00

/* CLK CTRL offsets */
#define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET		0x0020
#define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET		0x0720

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP4 PRCM definitions
 *
 * Copyright (C) 2010 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 *
 * Paul Walmsley
 *
 * This file contains macros and functions that are common to all of
 * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2,
 * PRCM_MPU, SCRM
 */

#ifndef __ARCH_ARM_MACH_OMAP2_PRCM44XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM44XX_H

/*
 * OMAP4 PRCM partition IDs
 *
 * The numbers and order are arbitrary, but 0 is reserved for the
 * 'invalid' partition in case someone forgets to add a
 * .prcm_partition field.
 */
#define OMAP4430_INVALID_PRCM_PARTITION		0
#define OMAP4430_PRM_PARTITION			1
#define OMAP4430_CM1_PARTITION			2
#define OMAP4430_CM2_PARTITION			3
#define OMAP4430_SCRM_PARTITION			4
#define OMAP4430_PRCM_MPU_PARTITION		5

#define OMAP54XX_PRM_PARTITION			1
#define OMAP54XX_CM_CORE_AON_PARTITION		2
#define OMAP54XX_CM_CORE_PARTITION		3
#define OMAP54XX_SCRM_PARTITION			4
#define OMAP54XX_PRCM_MPU_PARTITION		5

#define DRA7XX_PRM_PARTITION                   1
#define DRA7XX_CM_CORE_AON_PARTITION           2
#define DRA7XX_CM_CORE_PARTITION               3
#define DRA7XX_MPU_PRCM_PARTITION              5

/*
 * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
 * IDs, plus one
 */
#define OMAP4_MAX_PRCM_PARTITIONS		6

#endif


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP4 PRCM_MPU module functions
 *
 * Copyright (C) 2009 Nokia Corporation
 * Paul Walmsley
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>

#include "iomap.h"
#include "common.h"
#include "prcm_mpu44xx.h"
#include "cm-regbits-44xx.h"

/*
 * prcm_mpu_base: the virtual address of the start of the PRCM_MPU IP
 *   block registers
 */
struct omap_domain_base prcm_mpu_base;

/* PRCM_MPU low-level functions */

u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg)
{
	return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
}

void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg)
{
	writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
}

u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
{
	u32 v;

	v = omap4_prcm_mpu_read_inst_reg(inst, reg);
	v &= ~mask;
	v |= bits;
	omap4_prcm_mpu_write_inst_reg(v, inst, reg);

	return v;
}

/**
 * omap2_set_globals_prcm_mpu - set the MPU PRCM base address (for early use)
 * @prcm_mpu: PRCM_MPU base virtual address
 *
 * XXX Will be replaced when the PRM/CM drivers are completed.
 */
void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu)
{
	prcm_mpu_base.va = prcm_mpu;
}


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP44xx PRCM MPU instance offset macros
 *
 * Copyright (C) 2010, 2012 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
 *     or "OMAP4430".
 */

#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H

#include "prcm_mpu_44xx_54xx.h"

#define OMAP4430_PRCM_MPU_BASE			0x48243000

#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg)				\
	OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))

/* PRCM_MPU instances */
#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST	0x0000
#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST	0x0200
#define OMAP4430_PRCM_MPU_CPU0_INST		0x0400
#define OMAP4430_PRCM_MPU_CPU1_INST		0x0800

/* PRCM_MPU clockdomain register offsets (from instance start) */
#define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS	0x0018
#define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS	0x0018

/*
 * PRCM_MPU
 *
 * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
 * point of view the PRCM_MPU is a single entity. It shares the same
 * programming model as the global PRCM and thus can be assimilate as two new
 * MOD inside the PRCM
 */

/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
#define OMAP4_REVISION_PRCM_OFFSET		0x0000
#define OMAP4430_REVISION_PRCM			OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)

/* PRCM_MPU.DEVICE_PRM register offsets */
#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET		0x0000
#define OMAP4430_PRCM_MPU_PRM_RSTST		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET	0x0004
#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT	OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)

/* PRCM_MPU.CPU0 register offsets */
#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET		0x0000
#define OMAP4430_PM_CPU0_PWRSTCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
#define OMAP4_PM_CPU0_PWRSTST_OFFSET		0x0004
#define OMAP4430_PM_CPU0_PWRSTST		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET	0x0008
#define OMAP4430_RM_CPU0_CPU0_CONTEXT		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET	0x000c
#define OMAP4430_RM_CPU0_CPU0_RSTCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET		0x0010
#define OMAP4430_RM_CPU0_CPU0_RSTST		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET	0x0014
#define OMAP4430_CM_CPU0_CPU0_CLKCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET		0x0018
#define OMAP4430_CM_CPU0_CLKSTCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)

/* PRCM_MPU.CPU1 register offsets */
#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET		0x0000
#define OMAP4430_PM_CPU1_PWRSTCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
#define OMAP4_PM_CPU1_PWRSTST_OFFSET		0x0004
#define OMAP4430_PM_CPU1_PWRSTST		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET	0x0008
#define OMAP4430_RM_CPU1_CPU1_CONTEXT		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET	0x000c
#define OMAP4430_RM_CPU1_CPU1_RSTCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET		0x0010
#define OMAP4430_RM_CPU1_CPU1_RSTST		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET	0x0014
#define OMAP4430_CM_CPU1_CPU1_CLKCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET		0x0018
#define OMAP4430_CM_CPU1_CLKSTCTRL		OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP54xx PRCM MPU instance offset macros
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H

#include "prcm_mpu_44xx_54xx.h"
#include "common.h"

#define OMAP54XX_PRCM_MPU_BASE			0x48243000

#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg)				\
	OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))

/* PRCM_MPU instances */
#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST	0x0000
#define OMAP54XX_PRCM_MPU_DEVICE_INST		0x0200
#define OMAP54XX_PRCM_MPU_PRM_C0_INST		0x0400
#define OMAP54XX_PRCM_MPU_CM_C0_INST		0x0600
#define OMAP54XX_PRCM_MPU_PRM_C1_INST		0x0800
#define OMAP54XX_PRCM_MPU_CM_C1_INST		0x0a00

/* PRCM_MPU clockdomain register offsets (from instance start) */
#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS	0x0000
#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS	0x0000

/*
 * PRCM_MPU
 *
 * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
 * point of view the PRCM_MPU is a single entity. It shares the same
 * programming model as the global PRCM and thus can be assimilate as two new
 * MOD inside the PRCM
 */

/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
#define OMAP54XX_REVISION_PRCM_MPU_OFFSET			0x0000

/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET			0x0000
#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET		0x0004
#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET		0x0010
#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET	0x0014

/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET			0x0000
#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET				0x0004
#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET			0x0010
#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET			0x0014
#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET			0x0024

/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET			0x0000
#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET			0x0020
#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL				OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)

/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET			0x0000
#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET				0x0004
#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET			0x0010
#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET			0x0014
#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET			0x0024

/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET			0x0000
#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET			0x0020
#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL				OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * DRA7xx PRCM MPU instance offset macros
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
 *
 * Generated by code originally written by:
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H

#include "prcm_mpu_44xx_54xx.h"

#define DRA7XX_PRCM_MPU_BASE			0x48243000

#define DRA7XX_PRCM_MPU_REGADDR(inst, reg)				\
	OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))

/* MPU_PRCM instances */
#define DRA7XX_MPU_PRCM_OCP_SOCKET_INST	0x0000
#define DRA7XX_MPU_PRCM_DEVICE_INST	0x0200
#define DRA7XX_MPU_PRCM_PRM_C0_INST	0x0400
#define DRA7XX_MPU_PRCM_CM_C0_INST	0x0600
#define DRA7XX_MPU_PRCM_PRM_C1_INST	0x0800
#define DRA7XX_MPU_PRCM_CM_C1_INST	0x0a00

/* PRCM_MPU clockdomain register offsets (from instance start) */
#define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS	0x0000
#define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS	0x0000

/* MPU_PRCM */

/* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
#define DRA7XX_REVISION_PRCM_MPU_OFFSET				0x0000

/* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
#define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET		0x0010
#define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET	0x0014

/* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
#define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET				0x0000
#define DRA7XX_PM_CPU0_PWRSTST_OFFSET				0x0004
#define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET			0x0010
#define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET			0x0014
#define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET			0x0024

/* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
#define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET				0x0000
#define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET			0x0020
#define DRA7XX_CM_CPU0_CPU0_CLKCTRL				DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)

/* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
#define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET				0x0000
#define DRA7XX_PM_CPU1_PWRSTST_OFFSET				0x0004
#define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET			0x0010
#define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET			0x0014
#define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET			0x0024

/* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
#define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET				0x0000
#define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET			0x0020
#define DRA7XX_CM_CPU1_CPU1_CLKCTRL				DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP44xx and OMAP54xx PRCM MPU function prototypes
 *
 * Copyright (C) 2010, 2013 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H

#ifndef __ASSEMBLER__
#include "prcm-common.h"

extern struct omap_domain_base prcm_mpu_base;

extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
					    s16 idx);
extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
#endif

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H

/*
 * OMAP24XX Power/Reset Management register bits
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Copyright (C) 2007 Nokia Corporation
 *
 * Written by Paul Walmsley
 */

#include "prm2xxx.h"

#define OMAP24XX_EN_CORE_SHIFT 				0
#define OMAP24XX_FORCESTATE_MASK			(1 << 18)
#define OMAP24XX_AUTOIDLE_MASK				(1 << 0)
#define OMAP24XX_AUTO_EXTVOLT_MASK			(1 << 15)
#define OMAP24XX_SETOFF_LEVEL_SHIFT			12
#define OMAP24XX_MEMRETCTRL_MASK			(1 << 8)
#define OMAP24XX_SETRET_LEVEL_SHIFT			6
#define OMAP24XX_VOLT_LEVEL_SHIFT			0
#define OMAP2420_CLKOUT2_EN_SHIFT			15
#define OMAP2420_CLKOUT2_DIV_SHIFT			11
#define OMAP2420_CLKOUT2_DIV_WIDTH			3
#define OMAP2420_CLKOUT2_SOURCE_MASK			(0x3 << 8)
#define OMAP24XX_CLKOUT_EN_SHIFT			7
#define OMAP24XX_CLKOUT_DIV_SHIFT			3
#define OMAP24XX_CLKOUT_DIV_WIDTH			3
#define OMAP24XX_CLKOUT_SOURCE_MASK			(0x3 << 0)
#define OMAP24XX_EMULATION_EN_SHIFT			0
#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT		5
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT		2
#define OMAP24XX_EXTWMPU_RST_SHIFT			6
#define OMAP24XX_SECU_WD_RST_SHIFT			5
#define OMAP24XX_MPU_WD_RST_SHIFT			4
#define OMAP24XX_SECU_VIOL_RST_SHIFT			3
#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * AM33XX PRM_XXX register bits
 *
 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
 */

#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H

#include "prm.h"

#define AM33XX_GFX_MEM_ONSTATE_MASK			(0x3 << 17)
#define AM33XX_GFX_MEM_RETSTATE_MASK			(1 << 6)
#define AM33XX_GFX_MEM_STATEST_MASK			(0x3 << 4)
#define AM33XX_GLOBAL_WARM_SW_RST_MASK			(1 << 1)
#define AM33XX_RST_GLOBAL_WARM_SW_MASK			(1 << 0)
#define AM33XX_PRUSS_MEM_ONSTATE_MASK			(0x3 << 5)
#define AM33XX_PRUSS_MEM_RETSTATE_MASK			(1 << 7)
#define AM33XX_PRUSS_MEM_STATEST_MASK			(0x3 << 23)
#define AM33XX_LASTPOWERSTATEENTERED_SHIFT		24
#define AM33XX_LASTPOWERSTATEENTERED_MASK		(0x3 << 24)
#define AM33XX_LOGICRETSTATE_MASK			(1 << 2)
#define AM33XX_LOGICRETSTATE_3_3_MASK			(1 << 3)
#define AM33XX_LOGICSTATEST_SHIFT			2
#define AM33XX_LOGICSTATEST_MASK			(1 << 2)
#define AM33XX_LOWPOWERSTATECHANGE_SHIFT		4
#define AM33XX_LOWPOWERSTATECHANGE_MASK			(1 << 4)
#define AM33XX_MPU_L1_ONSTATE_MASK			(0x3 << 18)
#define AM33XX_MPU_L1_RETSTATE_MASK			(1 << 22)
#define AM33XX_MPU_L1_STATEST_MASK			(0x3 << 6)
#define AM33XX_MPU_L2_ONSTATE_MASK			(0x3 << 20)
#define AM33XX_MPU_L2_RETSTATE_MASK			(1 << 23)
#define AM33XX_MPU_L2_STATEST_MASK			(0x3 << 8)
#define AM33XX_MPU_RAM_ONSTATE_MASK			(0x3 << 16)
#define AM33XX_MPU_RAM_RETSTATE_MASK			(1 << 24)
#define AM33XX_MPU_RAM_STATEST_MASK			(0x3 << 4)
#define AM33XX_PER_MEM_ONSTATE_MASK			(0x3 << 25)
#define AM33XX_PER_MEM_RETSTATE_MASK			(1 << 29)
#define AM33XX_PER_MEM_STATEST_MASK			(0x3 << 17)
#define AM33XX_RAM_MEM_ONSTATE_MASK			(0x3 << 30)
#define AM33XX_RAM_MEM_RETSTATE_MASK			(1 << 27)
#define AM33XX_RAM_MEM_STATEST_MASK			(0x3 << 21)
#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP3430 Power/Reset Management register bits
 *
 * Copyright (C) 2007-2008 Texas Instruments, Inc.
 * Copyright (C) 2007-2008 Nokia Corporation
 *
 * Written by Paul Walmsley
 */
#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H

#include "prm3xxx.h"

#define OMAP3430_ERROROFFSET_MASK			(0xff << 24)
#define OMAP3430_ERRORGAIN_MASK				(0xff << 16)
#define OMAP3430_INITVOLTAGE_MASK			(0xff << 8)
#define OMAP3430_TIMEOUTEN_MASK				(1 << 3)
#define OMAP3430_INITVDD_MASK				(1 << 2)
#define OMAP3430_FORCEUPDATE_MASK			(1 << 1)
#define OMAP3430_VPENABLE_MASK				(1 << 0)
#define OMAP3430_SMPSWAITTIMEMIN_SHIFT			8
#define OMAP3430_VSTEPMIN_SHIFT				0
#define OMAP3430_SMPSWAITTIMEMAX_SHIFT			8
#define OMAP3430_VSTEPMAX_SHIFT				0
#define OMAP3430_VDDMAX_SHIFT				24
#define OMAP3430_VDDMIN_SHIFT				16
#define OMAP3430_TIMEOUT_SHIFT				0
#define OMAP3430_VPVOLTAGE_MASK				(0xff << 0)
#define OMAP3430_EN_PER_SHIFT				7
#define OMAP3430_LOGICSTATEST_MASK			(1 << 2)
#define OMAP3430_LASTLOGICSTATEENTERED_MASK		(1 << 2)
#define OMAP3430_LASTPOWERSTATEENTERED_MASK		(0x3 << 0)
#define OMAP3430_GRPSEL_MCBSP5_MASK			(1 << 10)
#define OMAP3430_GRPSEL_MCBSP1_MASK			(1 << 9)
#define OMAP3630_GRPSEL_UART4_MASK			(1 << 18)
#define OMAP3430_GRPSEL_GPIO6_MASK			(1 << 17)
#define OMAP3430_GRPSEL_GPIO5_MASK			(1 << 16)
#define OMAP3430_GRPSEL_GPIO4_MASK			(1 << 15)
#define OMAP3430_GRPSEL_GPIO3_MASK			(1 << 14)
#define OMAP3430_GRPSEL_GPIO2_MASK			(1 << 13)
#define OMAP3430_GRPSEL_UART3_MASK			(1 << 11)
#define OMAP3430_GRPSEL_GPT8_MASK			(1 << 9)
#define OMAP3430_GRPSEL_GPT7_MASK			(1 << 8)
#define OMAP3430_GRPSEL_GPT6_MASK			(1 << 7)
#define OMAP3430_GRPSEL_GPT5_MASK			(1 << 6)
#define OMAP3430_GRPSEL_MCBSP4_MASK			(1 << 2)
#define OMAP3430_GRPSEL_MCBSP3_MASK			(1 << 1)
#define OMAP3430_GRPSEL_MCBSP2_MASK			(1 << 0)
#define OMAP3430_GRPSEL_GPIO1_MASK			(1 << 3)
#define OMAP3430_GRPSEL_GPT12_MASK			(1 << 1)
#define OMAP3430_GRPSEL_GPT1_MASK			(1 << 0)
#define OMAP3430_RST3_IVA2_MASK				(1 << 2)
#define OMAP3430_RST2_IVA2_MASK				(1 << 1)
#define OMAP3430_RST1_IVA2_MASK				(1 << 0)
#define OMAP3430_L2FLATMEMONSTATE_MASK			(0x3 << 22)
#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK		(0x3 << 20)
#define OMAP3430_L1FLATMEMONSTATE_MASK			(0x3 << 18)
#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK		(0x3 << 16)
#define OMAP3430_L2FLATMEMRETSTATE_MASK			(1 << 11)
#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK		(1 << 10)
#define OMAP3430_L1FLATMEMRETSTATE_MASK			(1 << 9)
#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK		(1 << 8)
#define OMAP3430_L2FLATMEMSTATEST_MASK			(0x3 << 10)
#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK		(0x3 << 8)
#define OMAP3430_L1FLATMEMSTATEST_MASK			(0x3 << 6)
#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK		(0x3 << 4)
#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK			(0x3 << 10)
#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK		(0x3 << 8)
#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT		25
#define OMAP3430_VP2_TRANXDONE_ST_MASK			(1 << 21)
#define OMAP3430_VP1_TRANXDONE_ST_MASK			(1 << 15)
#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT	8
#define OMAP3430_MPU_DPLL_ST_SHIFT			7
#define OMAP3430_PERIPH_DPLL_ST_SHIFT			6
#define OMAP3430_CORE_DPLL_ST_SHIFT			5
#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT		25
#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT	8
#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT			7
#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT			6
#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT			5
#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT		5
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT		2
#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK		(1 << 1)
#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK		(1 << 0)
#define OMAP3430_LASTMEM2STATEENTERED_MASK		(0x3 << 6)
#define OMAP3430_LASTMEM1STATEENTERED_MASK		(0x3 << 4)
#define OMAP3430_EN_IO_CHAIN_MASK			(1 << 16)
#define OMAP3430_EN_IO_MASK				(1 << 8)
#define OMAP3430_EN_GPIO1_MASK				(1 << 3)
#define OMAP3430_ST_IO_CHAIN_MASK			(1 << 16)
#define OMAP3430_ST_IO_MASK				(1 << 8)
#define OMAP3430_SYS_CLKIN_SEL_SHIFT			0
#define OMAP3430_SYS_CLKIN_SEL_WIDTH			3
#define OMAP3430_CLKOUT_EN_SHIFT			7
#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK		(1 << 0)
#define OMAP3430ES2_SAVEANDRESTORE_SHIFT		4
#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT		16
#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK		(0x7f << 16)
#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT		0
#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK		(0x7f << 0)
#define OMAP3430_VOLRA1_MASK				(0xff << 16)
#define OMAP3430_VOLRA0_MASK				(0xff << 0)
#define OMAP3430_CMDRA1_MASK				(0xff << 16)
#define OMAP3430_CMDRA0_MASK				(0xff << 0)
#define OMAP3430_VC_CMD_ON_SHIFT			24
#define OMAP3430_VC_CMD_ON_MASK				(0xFF << 24)
#define OMAP3430_VC_CMD_ONLP_SHIFT			16
#define OMAP3430_VC_CMD_RET_SHIFT			8
#define OMAP3430_VC_CMD_OFF_SHIFT			0
#define OMAP3430_SREN_MASK				(1 << 4)
#define OMAP3430_HSEN_MASK				(1 << 3)
#define OMAP3430_MCODE_MASK				(0x7 << 0)
#define OMAP3430_VALID_MASK				(1 << 24)
#define OMAP3430_DATA_SHIFT				16
#define OMAP3430_REGADDR_SHIFT				8
#define OMAP3430_SLAVEADDR_SHIFT			0
#define OMAP3430_ICECRUSHER_RST_SHIFT			10
#define OMAP3430_ICEPICK_RST_SHIFT			9
#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT		8
#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT		7
#define OMAP3430_EXTERNAL_WARM_RST_SHIFT		6
#define OMAP3430_SECURE_WD_RST_SHIFT			5
#define OMAP3430_MPU_WD_RST_SHIFT			4
#define OMAP3430_SECURITY_VIOL_RST_SHIFT		3
#define OMAP3430_GLOBAL_SW_RST_SHIFT			1
#define OMAP3430_GLOBAL_COLD_RST_SHIFT			0
#define OMAP3430_GLOBAL_COLD_RST_MASK			(1 << 0)
#define OMAP3430_PRM_VOLTCTRL_SEL_VMODE			(1 << 4)
#define OMAP3430_PRM_VOLTCTRL_SEL_OFF			(1 << 3)
#define OMAP3430_PRM_VOLTCTRL_AUTO_OFF			(1 << 2)
#define OMAP3430_PRM_VOLTCTRL_AUTO_RET			(1 << 1)
#define OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP		(1 << 0)
#define OMAP3430_SETUP_TIME2_MASK			(0xffff << 16)
#define OMAP3430_SETUP_TIME1_MASK			(0xffff << 0)
#define OMAP3430_PRM_POLCTRL_OFFMODE_POL		(1 << 3)
#define OMAP3430_PRM_POLCTRL_CLKOUT_POL			(1 << 2)
#define OMAP3430_PRM_POLCTRL_CLKREQ_POL			(1 << 1)
#define OMAP3430_PRM_POLCTRL_EXTVOL_POL			(1 << 0)
#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP44xx Power Management register bits
 *
 * Copyright (C) 2009-2010 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H

#define OMAP4430_C2C_RST_SHIFT						10
#define OMAP4430_CMDRA_VDD_CORE_L_MASK					(0xff << 0)
#define OMAP4430_CMDRA_VDD_IVA_L_MASK					(0xff << 8)
#define OMAP4430_CMDRA_VDD_MPU_L_MASK					(0xff << 16)
#define OMAP4430_DATA_SHIFT						16
#define OMAP4430_ERRORGAIN_MASK						(0xff << 16)
#define OMAP4430_ERROROFFSET_MASK					(0xff << 24)
#define OMAP4430_EXTERNAL_WARM_RST_SHIFT				5
#define OMAP4430_FORCEUPDATE_MASK					(1 << 1)
#define OMAP4430_GLOBAL_COLD_RST_SHIFT					0
#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT				1
#define OMAP4430_GLOBAL_WUEN_MASK					(1 << 16)
#define OMAP4430_HSMCODE_MASK						(0x7 << 0)
#define OMAP4430_SRMODEEN_MASK						(1 << 4)
#define OMAP4430_HSMODEEN_MASK						(1 << 3)
#define OMAP4430_HSSCLL_SHIFT						24
#define OMAP4430_ICEPICK_RST_SHIFT					9
#define OMAP4430_INITVDD_MASK						(1 << 2)
#define OMAP4430_INITVOLTAGE_MASK					(0xff << 8)
#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT				24
#define OMAP4430_LASTPOWERSTATEENTERED_MASK				(0x3 << 24)
#define OMAP4430_LOGICRETSTATE_SHIFT					2
#define OMAP4430_LOGICRETSTATE_MASK					(1 << 2)
#define OMAP4430_LOGICSTATEST_SHIFT					2
#define OMAP4430_LOGICSTATEST_MASK					(1 << 2)
#define OMAP4430_LOSTCONTEXT_DFF_MASK					(1 << 0)
#define OMAP4430_LOSTMEM_AESSMEM_MASK					(1 << 8)
#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT				4
#define OMAP4430_LOWPOWERSTATECHANGE_MASK				(1 << 4)
#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT				2
#define OMAP4430_MPU_WDT_RST_SHIFT					3
#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK				(0x3 << 24)
#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK				(1 << 12)
#define OMAP4430_OCP_NRET_BANK_STATEST_MASK				(0x3 << 12)
#define OMAP4430_OFF_SHIFT						0
#define OMAP4430_ON_SHIFT						24
#define OMAP4430_ON_MASK						(0xff << 24)
#define OMAP4430_ONLP_SHIFT						16
#define OMAP4430_RAMP_DOWN_COUNT_SHIFT					16
#define OMAP4430_RAMP_UP_COUNT_SHIFT					0
#define OMAP4430_RAMP_UP_PRESCAL_SHIFT					8
#define OMAP4430_REGADDR_SHIFT						8
#define OMAP4430_RET_SHIFT						8
#define OMAP4430_RST_GLOBAL_WARM_SW_MASK				(1 << 0)
#define OMAP4430_SA_VDD_CORE_L_SHIFT					0
#define OMAP4430_SA_VDD_CORE_L_0_6_MASK					(0x7f << 0)
#define OMAP4430_SA_VDD_IVA_L_SHIFT					8
#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK			(0x7f << 8)
#define OMAP4430_SA_VDD_MPU_L_SHIFT					16
#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK			(0x7f << 16)
#define OMAP4430_SCLH_SHIFT						0
#define OMAP4430_SCLL_SHIFT						8
#define OMAP4430_SECURE_WDT_RST_SHIFT					4
#define OMAP4430_SLAVEADDR_SHIFT					0
#define OMAP4430_SMPSWAITTIMEMAX_SHIFT					8
#define OMAP4430_SMPSWAITTIMEMIN_SHIFT					8
#define OMAP4430_TIMEOUT_SHIFT						0
#define OMAP4430_TIMEOUTEN_MASK						(1 << 3)
#define OMAP4430_VALID_MASK						(1 << 24)
#define OMAP4430_VDDMAX_SHIFT						24
#define OMAP4430_VDDMIN_SHIFT						16
#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT				8
#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT				7
#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT				6
#define OMAP4430_VOLRA_VDD_CORE_L_MASK					(0xff << 0)
#define OMAP4430_VOLRA_VDD_IVA_L_MASK					(0xff << 8)
#define OMAP4430_VOLRA_VDD_MPU_L_MASK					(0xff << 16)
#define OMAP4430_VPENABLE_MASK						(1 << 0)
#define OMAP4430_VPVOLTAGE_MASK						(0xff << 0)
#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK				(1 << 21)
#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK				(1 << 29)
#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK				(1 << 5)
#define OMAP4430_VSTEPMAX_SHIFT						0
#define OMAP4430_VSTEPMIN_SHIFT						0
#define OMAP4430_WUCLK_CTRL_MASK					(1 << 8)
#define OMAP4430_WUCLK_STATUS_SHIFT					9
#define OMAP4430_WUCLK_STATUS_MASK					(1 << 9)
#endif