code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra host1x controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: The host1x top-level node defines a number of children, each
  representing one of the host1x client modules defined in this binding.

properties:
  compatible:
    oneOf:
      - enum:
          - nvidia,tegra20-host1x
          - nvidia,tegra30-host1x
          - nvidia,tegra114-host1x
          - nvidia,tegra124-host1x
          - nvidia,tegra210-host1x
          - nvidia,tegra186-host1x
          - nvidia,tegra194-host1x
          - nvidia,tegra234-host1x

      - items:
          - const: nvidia,tegra132-host1x
          - const: nvidia,tegra124-host1x

  reg:
    minItems: 1
    maxItems: 3

  reg-names:
    minItems: 1
    maxItems: 3

  interrupts:
    minItems: 1
    maxItems: 9

  interrupt-names:
    minItems: 1
    maxItems: 9

  '#address-cells':
    description: The number of cells used to represent physical base addresses
      in the host1x address space.
    enum: [1, 2]

  '#size-cells':
    description: The number of cells used to represent the size of an address
      range in the host1x address space.
    enum: [1, 2]

  ranges:
    maxItems: 1

  clocks:
    description: Must contain one entry, for the module clock. See
      ../clocks/clock-bindings.txt for details.

  clock-names:
    items:
      - const: host1x

  resets:
    minItems: 1 # MC reset is optional on Tegra186 and later
    items:
      - description: module reset
      - description: memory client hotflush reset

  reset-names:
    minItems: 1 # MC reset is optional on Tegra186 and later
    items:
      - const: host1x
      - const: mc

  iommus:
    maxItems: 1

  interconnects:
    items:
      - description: memory read client for host1x

  interconnect-names:
    items:
      - const: dma-mem # read

  operating-points-v2:
    $ref: "/schemas/types.yaml#/definitions/phandle"

  power-domains:
    items:
      - description: phandle to the HEG or core power domain

required:
  - compatible
  - interrupts
  - interrupt-names
  - '#address-cells'
  - '#size-cells'
  - ranges
  - reg
  - clocks
  - clock-names

unevaluatedProperties:
  type: object

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra20-host1x
              - nvidia,tegra30-host1x
              - nvidia,tegra114-host1x
              - nvidia,tegra124-host1x
              - nvidia,tegra210-host1x
    then:
      properties:
        interrupts:
          items:
            - description: host1x syncpoint interrupt
            - description: host1x general interrupt

        interrupt-names:
          items:
            - const: syncpt
            - const: host1x
      required:
        - resets
        - reset-names
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra186-host1x
              - nvidia,tegra194-host1x
    then:
      properties:
        reg-names:
          items:
            - const: hypervisor
            - const: vm

        reg:
          items:
            - description: region used by the hypervisor
            - description: region assigned to the virtual machine

        resets:
          maxItems: 1

        reset-names:
          maxItems: 1

        interrupts:
          items:
            - description: host1x syncpoint interrupt
            - description: host1x general interrupt

        interrupt-names:
          items:
            - const: syncpt
            - const: host1x

        iommu-map:
          description: Specification of stream IDs available for memory context device
            use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
            usable stream IDs.

      required:
        - reg-names
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra234-host1x
    then:
      properties:
        reg-names:
          items:
            - const: common
            - const: hypervisor
            - const: vm

        reg:
          items:
            - description: region used by host1x server
            - description: region used by the hypervisor
            - description: region assigned to the virtual machine

        interrupts:
          items:
            - description: host1x syncpoint interrupt 0
            - description: host1x syncpoint interrupt 1
            - description: host1x syncpoint interrupt 2
            - description: host1x syncpoint interrupt 3
            - description: host1x syncpoint interrupt 4
            - description: host1x syncpoint interrupt 5
            - description: host1x syncpoint interrupt 6
            - description: host1x syncpoint interrupt 7
            - description: host1x general interrupt

        interrupt-names:
          items:
            - const: syncpt0
            - const: syncpt1
            - const: syncpt2
            - const: syncpt3
            - const: syncpt4
            - const: syncpt5
            - const: syncpt6
            - const: syncpt7
            - const: host1x

        iommu-map:
          description: Specification of stream IDs available for memory context device
            use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
            usable stream IDs.

      required:
        - reg-names

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
    #include <dt-bindings/gpio/tegra-gpio.h>
    #include <dt-bindings/memory/tegra20-mc.h>

    host1x@50000000 {
        compatible = "nvidia,tegra20-host1x";
        reg = <0x50000000 0x00024000>;
        interrupts = <0 65 0x04>, /* mpcore syncpt */
                     <0 67 0x04>; /* mpcore general */
        interrupt-names = "syncpt", "host1x";
        clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
        clock-names = "host1x";
        resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
        reset-names = "host1x", "mc";

        #address-cells = <1>;
        #size-cells = <1>;

        ranges = <0x54000000 0x54000000 0x04000000>;

        mpe@54040000 {
            compatible = "nvidia,tegra20-mpe";
            reg = <0x54040000 0x00040000>;
            interrupts = <0 68 0x04>;
            clocks = <&tegra_car TEGRA20_CLK_MPE>;
            resets = <&tegra_car 60>;
            reset-names = "mpe";
        };

        vi@54080000 {
            compatible = "nvidia,tegra20-vi";
            reg = <0x54080000 0x00040000>;
            interrupts = <0 69 0x04>;
            clocks = <&tegra_car TEGRA20_CLK_VI>;
            resets = <&tegra_car 100>;
            reset-names = "vi";
        };

        epp@540c0000 {
            compatible = "nvidia,tegra20-epp";
            reg = <0x540c0000 0x00040000>;
            interrupts = <0 70 0x04>;
            clocks = <&tegra_car TEGRA20_CLK_EPP>;
            resets = <&tegra_car 19>;
            reset-names = "epp";
        };

        isp@54100000 {
            compatible = "nvidia,tegra20-isp";
            reg = <0x54100000 0x00040000>;
            interrupts = <0 71 0x04>;
            clocks = <&tegra_car TEGRA20_CLK_ISP>;
            resets = <&tegra_car 23>;
            reset-names = "isp";
        };

        gr2d@54140000 {
            compatible = "nvidia,tegra20-gr2d";
            reg = <0x54140000 0x00040000>;
            interrupts = <0 72 0x04>;
            clocks = <&tegra_car TEGRA20_CLK_GR2D>;
            resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
            reset-names = "2d", "mc";
        };

        gr3d@54180000 {
            compatible = "nvidia,tegra20-gr3d";
            reg = <0x54180000 0x00040000>;
            clocks = <&tegra_car TEGRA20_CLK_GR3D>;
            resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
            reset-names = "3d", "mc";
        };

        dc@54200000 {
            compatible = "nvidia,tegra20-dc";
            reg = <0x54200000 0x00040000>;
            interrupts = <0 73 0x04>;
            clocks = <&tegra_car TEGRA20_CLK_DISP1>;
            clock-names = "dc";
            resets = <&tegra_car 27>;
            reset-names = "dc";

            rgb {
            };
        };

        dc@54240000 {
            compatible = "nvidia,tegra20-dc";
            reg = <0x54240000 0x00040000>;
            interrupts = <0 74 0x04>;
            clocks = <&tegra_car TEGRA20_CLK_DISP2>;
            clock-names = "dc";
            resets = <&tegra_car 26>;
            reset-names = "dc";

            rgb {
            };
        };

        hdmi@54280000 {
            compatible = "nvidia,tegra20-hdmi";
            reg = <0x54280000 0x00040000>;
            interrupts = <0 75 0x04>;
            clocks = <&tegra_car TEGRA20_CLK_HDMI>,
                     <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
            clock-names = "hdmi", "parent";
            resets = <&tegra_car 51>;
            reset-names = "hdmi";

            hdmi-supply = <&vdd_5v0_hdmi>;
            pll-supply = <&vdd_hdmi_pll>;
            vdd-supply = <&vdd_3v3_hdmi>;

            nvidia,ddc-i2c-bus = <&hdmi_ddc>;
            nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
        };

        tvo@542c0000 {
            compatible = "nvidia,tegra20-tvo";
            reg = <0x542c0000 0x00040000>;
            interrupts = <0 76 0x04>;
            clocks = <&tegra_car TEGRA20_CLK_TVO>;
        };

        dsi@54300000 {
            compatible = "nvidia,tegra20-dsi";
            reg = <0x54300000 0x00040000>;
            clocks = <&tegra_car TEGRA20_CLK_DSI>,
                     <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
            clock-names = "dsi", "parent";
            resets = <&tegra_car 48>;
            reset-names = "dsi";
        };
    };

  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/tegra210-mc.h>

    host1x@50000000 {
        compatible = "nvidia,tegra210-host1x";
        reg = <0x50000000 0x00024000>;
        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */
                     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */
        interrupt-names = "syncpt", "host1x";
        clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
        clock-names = "host1x";
        resets = <&tegra_car 28>;
        reset-names = "host1x";

        #address-cells = <1>;
        #size-cells = <1>;

        ranges = <0x54000000 0x54000000 0x01000000>;
        iommus = <&mc TEGRA_SWGROUP_HC>;

        vi@54080000 {
            compatible = "nvidia,tegra210-vi";
            reg = <0x54080000 0x00000700>;
            interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
            assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;

            clocks = <&tegra_car TEGRA210_CLK_VI>;
            power-domains = <&pd_venc>;

            #address-cells = <1>;
            #size-cells = <1>;

            ranges = <0x0 0x54080000 0x2000>;

            csi@838 {
                compatible = "nvidia,tegra210-csi";
                reg = <0x838 0x1300>;
                assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
                                  <&tegra_car TEGRA210_CLK_CILCD>,
                                  <&tegra_car TEGRA210_CLK_CILE>,
                                  <&tegra_car TEGRA210_CLK_CSI_TPG>;
                assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
                                         <&tegra_car TEGRA210_CLK_PLL_P>,
                                         <&tegra_car TEGRA210_CLK_PLL_P>;
                assigned-clock-rates = <102000000>,
                                       <102000000>,
                                       <102000000>,
                                       <972000000>;

                clocks = <&tegra_car TEGRA210_CLK_CSI>,
                         <&tegra_car TEGRA210_CLK_CILAB>,
                         <&tegra_car TEGRA210_CLK_CILCD>,
                         <&tegra_car TEGRA210_CLK_CILE>,
                         <&tegra_car TEGRA210_CLK_CSI_TPG>;
                clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
                power-domains = <&pd_sor>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra ISP processor

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    enum:
      - nvidia,tegra20-isp
      - nvidia,tegra30-isp
      - nvidia,tegra210-isp

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: module clock

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: isp

  iommus:
    maxItems: 1

  interconnects:
    items:
      - description: memory write client

  interconnect-names:
    items:
      - const: dma-mem # write

  power-domains:
    items:
      - description: phandle to the VENC or core power domain

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    isp@54100000 {
        compatible = "nvidia,tegra20-isp";
        reg = <0x54100000 0x00040000>;
        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA20_CLK_ISP>;
        resets = <&tegra_car 23>;
        reset-names = "isp";
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Video Encoder

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^mpe@[0-9a-f]+$"

  compatible:
    enum:
      - nvidia,tegra20-mpe
      - nvidia,tegra30-mpe
      - nvidia,tegra114-mpe

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: module clock

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: mpe

  iommus:
    maxItems: 1

  interconnects:
    maxItems: 6

  interconnect-names:
    maxItems: 6

  operating-points-v2:
    $ref: "/schemas/types.yaml#/definitions/phandle"

  power-domains:
    items:
      - description: phandle to the MPE power domain

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mpe@54040000 {
        compatible = "nvidia,tegra20-mpe";
        reg = <0x54040000 0x00040000>;
        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA20_CLK_MPE>;
        resets = <&tegra_car 60>;
        reset-names = "mpe";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-tvo.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra TV Encoder Output

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^tvo@[0-9a-f]+$"

  compatible:
    enum:
      - nvidia,tegra20-tvo
      - nvidia,tegra30-tvo
      - nvidia,tegra114-tvo

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: module clock

  operating-points-v2:
    $ref: "/schemas/types.yaml#/definitions/phandle"

  power-domains:
    items:
      - description: phandle to the core power domain

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tvo@542c0000 {
        compatible = "nvidia,tegra20-tvo";
        reg = <0x542c0000 0x00040000>;
        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA20_CLK_TVO>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Video Input controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^vi@[0-9a-f]+$"

  compatible:
    oneOf:
      - const: nvidia,tegra20-vi
      - const: nvidia,tegra30-vi
      - const: nvidia,tegra114-vi
      - const: nvidia,tegra124-vi
      - items:
          - const: nvidia,tegra132-vi
          - const: nvidia,tegra124-vi
      - const: nvidia,tegra210-vi
      - const: nvidia,tegra186-vi
      - const: nvidia,tegra194-vi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: vi

  iommus:
    maxItems: 1

  interconnects:
    minItems: 4
    maxItems: 5

  interconnect-names:
    minItems: 4
    maxItems: 5

  operating-points-v2:
    $ref: "/schemas/types.yaml#/definitions/phandle"

  power-domains:
    items:
      - description: phandle to the VENC power domain

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  ranges:
    maxItems: 1

  avdd-dsi-csi-supply:
    description: DSI/CSI power supply. Must supply 1.2 V.

patternProperties:
  "^csi@[0-9a-f]+$":
    type: object

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra20-vi
              - nvidia,tegra30-vi
              - nvidia,tegra114-vi
              - nvidia,tegra124-vi
    then:
      required:
        - resets
        - reset-names
    else:
      required:
        - power-domains

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    vi@54080000 {
        compatible = "nvidia,tegra20-vi";
        reg = <0x54080000 0x00040000>;
        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA20_CLK_VI>;
        resets = <&tegra_car 100>;
        reset-names = "vi";
    };

  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    vi@54080000 {
        compatible = "nvidia,tegra210-vi";
        reg = <0x54080000 0x00000700>;
        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
        assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;

        clocks = <&tegra_car TEGRA210_CLK_VI>;
        power-domains = <&pd_venc>;

        #address-cells = <1>;
        #size-cells = <1>;

        ranges = <0x0 0x54080000 0x2000>;

        csi@838 {
            compatible = "nvidia,tegra210-csi";
            reg = <0x838 0x1300>;
            assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
                              <&tegra_car TEGRA210_CLK_CILCD>,
                              <&tegra_car TEGRA210_CLK_CILE>,
                              <&tegra_car TEGRA210_CLK_CSI_TPG>;
            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
                                     <&tegra_car TEGRA210_CLK_PLL_P>,
                                     <&tegra_car TEGRA210_CLK_PLL_P>;
            assigned-clock-rates = <102000000>,
                                   <102000000>,
                                   <102000000>,
                                   <972000000>;

            clocks = <&tegra_car TEGRA210_CLK_CSI>,
                     <&tegra_car TEGRA210_CLK_CILAB>,
                     <&tegra_car TEGRA210_CLK_CILCD>,
                     <&tegra_car TEGRA210_CLK_CILE>,
                     <&tegra_car TEGRA210_CLK_CSI_TPG>;
            clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
            power-domains = <&pd_sor>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra CSI controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^csi@[0-9a-f]+$"

  compatible:
    enum:
      - nvidia,tegra210-csi

  reg:
    maxItems: 1

  clocks:
    items:
      - description: module clock
      - description: A/B lanes clock
      - description: C/D lanes clock
      - description: E lane clock
      - description: test pattern generator clock

  clock-names:
    items:
      - const: csi
      - const: cilab
      - const: cilcd
      - const: cile
      - const: csi_tpg

  power-domains:
    maxItems: 1

additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains

# see nvidia,tegra20-vi.yaml for an example


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Texas Instruments Incorporated
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Texas Instruments AM65x Display Subsystem

maintainers:
  - Jyri Sarha <jsarha@ti.com>
  - Tomi Valkeinen <tomi.valkeinen@ti.com>

description: |
  The AM65x TI Keystone Display SubSystem with two output ports and
  two video planes. The first video port supports OLDI and the second
  supports DPI format. The fist plane is full video plane with all
  features and the second is a "lite plane" without scaling support.

properties:
  compatible:
    const: ti,am65x-dss

  reg:
    description:
      Addresses to each DSS memory region described in the SoC's TRM.
    items:
      - description: common DSS register area
      - description: VIDL1 light video plane
      - description: VID video plane
      - description: OVR1 overlay manager for vp1
      - description: OVR2 overlay manager for vp2
      - description: VP1 video port 1
      - description: VP2 video port 2

  reg-names:
    items:
      - const: common
      - const: vidl1
      - const: vid
      - const: ovr1
      - const: ovr2
      - const: vp1
      - const: vp2

  clocks:
    items:
      - description: fck DSS functional clock
      - description: vp1 Video Port 1 pixel clock
      - description: vp2 Video Port 2 pixel clock

  clock-names:
    items:
      - const: fck
      - const: vp1
      - const: vp2

  assigned-clocks:
    minItems: 1
    maxItems: 3

  assigned-clock-parents:
    minItems: 1
    maxItems: 3

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1
    description: phandle to the associated power domain

  dma-coherent:
    type: boolean

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          The DSS OLDI output port node form video port 1

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          The DSS DPI output port node from video port 2

  ti,am65x-oldi-io-ctrl:
    $ref: "/schemas/types.yaml#/definitions/phandle"
    description:
      phandle to syscon device node mapping OLDI IO_CTRL registers.
      The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
      following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
      and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
      interface to work.

  max-memory-bandwidth:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Input memory (from main memory to dispc) bandwidth limit in
      bytes per second

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - interrupts
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    dss: dss@4a00000 {
            compatible = "ti,am65x-dss";
            reg =   <0x04a00000 0x1000>, /* common */
                    <0x04a02000 0x1000>, /* vidl1 */
                    <0x04a06000 0x1000>, /* vid */
                    <0x04a07000 0x1000>, /* ovr1 */
                    <0x04a08000 0x1000>, /* ovr2 */
                    <0x04a0a000 0x1000>, /* vp1 */
                    <0x04a0b000 0x1000>; /* vp2 */
            reg-names = "common", "vidl1", "vid",
                    "ovr1", "ovr2", "vp1", "vp2";
            ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
            power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
            clocks =        <&k3_clks 67 1>,
                            <&k3_clks 216 1>,
                            <&k3_clks 67 2>;
            clock-names = "fck", "vp1", "vp2";
            interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
            ports {
                    #address-cells = <1>;
                    #size-cells = <0>;
                    port@0 {
                            reg = <0>;
                            oldi_out0: endpoint {
                                    remote-endpoint = <&lcd_in0>;
                            };
                    };
            };
    };


code:
Texas Instruments DRA7x Display Subsystem
=========================================

See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
description about OMAP Display Subsystem bindings.

DSS Core
--------

Required properties:
- compatible: "ti,dra7-dss"
- reg: address and length of the register spaces for 'dss'
- ti,hwmods: "dss_core"
- clocks: handle to fclk
- clock-names: "fck"
- syscon: phandle to control module core syscon node

Optional properties:

Some DRA7xx SoCs have one dedicated video PLL, some have two. These properties
can be used to describe the video PLLs:

- reg: address and length of the register spaces for 'pll1_clkctrl',
  'pll1', 'pll2_clkctrl', 'pll2'
- clocks: handle to video1 pll clock and video2 pll clock
- clock-names: "video1_clk" and "video2_clk"

Required nodes:
- DISPC

Optional nodes:
- DSS Submodules: HDMI
- Video port for DPI output

DPI Endpoint required properties:
- data-lines: number of lines used

DISPC
-----

Required properties:
- compatible: "ti,dra7-dispc"
- reg: address and length of the register space
- ti,hwmods: "dss_dispc"
- interrupts: the DISPC interrupt
- clocks: handle to fclk
- clock-names: "fck"

Optional properties:
- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
			in bytes per second

HDMI
----

Required properties:
- compatible: "ti,dra7-hdmi"
- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
       'core'
- reg-names: "wp", "pll", "phy", "core"
- interrupts: the HDMI interrupt line
- ti,hwmods: "dss_hdmi"
- vdda-supply: vdda power supply
- clocks: handles to fclk and pll clock
- clock-names: "fck", "sys_clk"

Optional nodes:
- Video port for HDMI output

HDMI Endpoint optional properties:
- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
  D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7)


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Texas Instruments Incorporated
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Texas Instruments J721E Display Subsystem

maintainers:
  - Jyri Sarha <jsarha@ti.com>
  - Tomi Valkeinen <tomi.valkeinen@ti.com>

description: |
  The J721E TI Keystone Display SubSystem with four output ports and
  four video planes. There is two full video planes and two "lite
  planes" without scaling support. The video ports can be connected to
  the SoC's DPI pins or to integrated display bridges on the SoC.

properties:
  compatible:
    const: ti,j721e-dss

  reg:
    items:
      - description: common_m DSS Master common
      - description: common_s0 DSS Shared common 0
      - description: common_s1 DSS Shared common 1
      - description: common_s2 DSS Shared common 2
      - description: VIDL1 light video plane 1
      - description: VIDL2 light video plane 2
      - description: VID1 video plane 1
      - description: VID1 video plane 2
      - description: OVR1 overlay manager for vp1
      - description: OVR2 overlay manager for vp2
      - description: OVR3 overlay manager for vp3
      - description: OVR4 overlay manager for vp4
      - description: VP1 video port 1
      - description: VP2 video port 2
      - description: VP3 video port 3
      - description: VP4 video port 4
      - description: WB Write Back

  reg-names:
    items:
      - const: common_m
      - const: common_s0
      - const: common_s1
      - const: common_s2
      - const: vidl1
      - const: vidl2
      - const: vid1
      - const: vid2
      - const: ovr1
      - const: ovr2
      - const: ovr3
      - const: ovr4
      - const: vp1
      - const: vp2
      - const: vp3
      - const: vp4
      - const: wb

  clocks:
    items:
      - description: fck DSS functional clock
      - description: vp1 Video Port 1 pixel clock
      - description: vp2 Video Port 2 pixel clock
      - description: vp3 Video Port 3 pixel clock
      - description: vp4 Video Port 4 pixel clock

  clock-names:
    items:
      - const: fck
      - const: vp1
      - const: vp2
      - const: vp3
      - const: vp4

  assigned-clocks:
    minItems: 1
    maxItems: 5

  assigned-clock-parents:
    minItems: 1
    maxItems: 5

  interrupts:
    items:
      - description: common_m DSS Master common
      - description: common_s0 DSS Shared common 0
      - description: common_s1 DSS Shared common 1
      - description: common_s2 DSS Shared common 2

  interrupt-names:
    items:
      - const: common_m
      - const: common_s0
      - const: common_s1
      - const: common_s2

  power-domains:
    maxItems: 1
    description: phandle to the associated power domain

  dma-coherent:
    type: boolean

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          The output port node form video port 1

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          The output port node from video port 2

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          The output port node from video port 3

      port@3:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          The output port node from video port 4

  max-memory-bandwidth:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Input memory (from main memory to dispc) bandwidth limit in
      bytes per second

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - interrupts
  - interrupt-names
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    dss: dss@4a00000 {
            compatible = "ti,j721e-dss";
            reg =   <0x04a00000 0x10000>, /* common_m */
                    <0x04a10000 0x10000>, /* common_s0*/
                    <0x04b00000 0x10000>, /* common_s1*/
                    <0x04b10000 0x10000>, /* common_s2*/
                    <0x04a20000 0x10000>, /* vidl1 */
                    <0x04a30000 0x10000>, /* vidl2 */
                    <0x04a50000 0x10000>, /* vid1 */
                    <0x04a60000 0x10000>, /* vid2 */
                    <0x04a70000 0x10000>, /* ovr1 */
                    <0x04a90000 0x10000>, /* ovr2 */
                    <0x04ab0000 0x10000>, /* ovr3 */
                    <0x04ad0000 0x10000>, /* ovr4 */
                    <0x04a80000 0x10000>, /* vp1 */
                    <0x04aa0000 0x10000>, /* vp2 */
                    <0x04ac0000 0x10000>, /* vp3 */
                    <0x04ae0000 0x10000>, /* vp4 */
                    <0x04af0000 0x10000>; /* wb */
            reg-names = "common_m", "common_s0",
                    "common_s1", "common_s2",
                    "vidl1", "vidl2","vid1","vid2",
                    "ovr1", "ovr2", "ovr3", "ovr4",
                    "vp1", "vp2", "vp3", "vp4",
                    "wb";
            clocks =        <&k3_clks 152 0>,
                            <&k3_clks 152 1>,
                            <&k3_clks 152 4>,
                            <&k3_clks 152 9>,
                            <&k3_clks 152 13>;
            clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
            power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
            interrupts =    <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
                            <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
                            <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
                            <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names =       "common_m",
                                    "common_s0",
                                    "common_s1",
                                    "common_s2";
            ports {
                    #address-cells = <1>;
                    #size-cells = <0>;
                    port@0 {
                            reg = <0>;

                            dpi_out_0: endpoint {
                                    remote-endpoint = <&dp_bridge_input>;
                            };
                    };
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Texas Instruments Incorporated
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Texas Instruments K2G Display Subsystem

maintainers:
  - Jyri Sarha <jsarha@ti.com>
  - Tomi Valkeinen <tomi.valkeinen@ti.com>

description: |
  The K2G DSS is an ultra-light version of TI Keystone Display
  SubSystem. It has only one output port and video plane. The
  output is DPI.

properties:
  compatible:
    const: ti,k2g-dss

  reg:
    items:
      - description: cfg DSS top level
      - description: common DISPC common
      - description: VID1 video plane 1
      - description: OVR1 overlay manager for vp1
      - description: VP1 video port 1

  reg-names:
    items:
      - const: cfg
      - const: common
      - const: vid1
      - const: ovr1
      - const: vp1

  clocks:
    items:
      - description: fck DSS functional clock
      - description: vp1 Video Port 1 pixel clock

  clock-names:
    items:
      - const: fck
      - const: vp1

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1
    description: phandle to the associated power domain

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      The DSS DPI output port node

  max-memory-bandwidth:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Input memory (from main memory to dispc) bandwidth limit in
      bytes per second

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - interrupts
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    dss: dss@2540000 {
            compatible = "ti,k2g-dss";
            reg =   <0x02540000 0x400>,
                    <0x02550000 0x1000>,
                    <0x02557000 0x1000>,
                    <0x0255a800 0x100>,
                    <0x0255ac00 0x100>;
            reg-names = "cfg", "common", "vid1", "ovr1", "vp1";
            clocks =        <&k2g_clks 0x2 0>,
                            <&k2g_clks 0x2 1>;
            clock-names = "fck", "vp1";
            interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>;

            power-domains = <&k2g_pds 0x2>;

            max-memory-bandwidth = <230000000>;

            port {
                    dpi_out: endpoint {
                            remote-endpoint = <&sii9022_in>;
                    };
            };
    };


code:
Texas Instruments OMAP Display Subsystem
========================================

Generic Description
-------------------

This document is a generic description of the OMAP Display Subsystem bindings.
Binding details for each OMAP SoC version are described in respective binding
documentation.

The OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
a number of encoder modules. All DSS versions contain DSS Core and DISPC, but
the encoder modules vary.

The DSS Core is the parent of the other DSS modules, and manages clock routing,
integration to the SoC, etc.

DISPC is the display controller, which reads pixels from the memory and outputs
a RGB pixel stream to encoders.

The encoder modules encode the received RGB pixel stream to a video output like
HDMI, MIPI DPI, etc.

Video Ports
-----------

The DSS Core and the encoders have video port outputs. The structure of the
video ports is described in Documentation/devicetree/bindings/graph.txt,
and the properties for the ports and endpoints for each encoder are
described in the SoC's DSS binding documentation.

The video ports are used to describe the connections to external hardware, like
panels or external encoders.

Aliases
-------

The board dts file may define aliases for displays to assign "displayX" style
name for each display. If no aliases are defined, a semi-random number is used
for the display.

Example
-------

A shortened example of the DSS description for OMAP4, with non-relevant parts
removed, defined in omap4.dtsi:

dss: dss@58000000 {
	compatible = "ti,omap4-dss";
	reg = <0x58000000 0x80>;
	status = "disabled";
	ti,hwmods = "dss_core";
	clocks = <&dss_dss_clk>;
	clock-names = "fck";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	dispc@58001000 {
		compatible = "ti,omap4-dispc";
		reg = <0x58001000 0x1000>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		ti,hwmods = "dss_dispc";
		clocks = <&dss_dss_clk>;
		clock-names = "fck";
	};

	hdmi: encoder@58006000 {
		compatible = "ti,omap4-hdmi";
		reg = <0x58006000 0x200>,
		      <0x58006200 0x100>,
		      <0x58006300 0x100>,
		      <0x58006400 0x1000>;
		reg-names = "wp", "pll", "phy", "core";
		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
		ti,hwmods = "dss_hdmi";
		clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
		clock-names = "fck", "sys_clk";
	};
};

A shortened example of the board description for OMAP4 Panda board, defined in
omap4-panda.dts.

The Panda board has a DVI and a HDMI connector, and the board contains a TFP410
chip (MIPI DPI to DVI encoder) and a TPD12S015 chip (HDMI ESD protection & level
shifter). The video pipelines for the connectors are formed as follows:

DSS Core --(MIPI DPI)--> TFP410 --(DVI)--> DVI Connector
OMAP HDMI --(HDMI)--> TPD12S015 --(HDMI)--> HDMI Connector

/ {
	aliases {
		display0 = &dvi0;
		display1 = &hdmi0;
	};

	tfp410: encoder@0 {
		compatible = "ti,tfp410";
		gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;	/* 0, power-down */

		pinctrl-names = "default";
		pinctrl-0 = <&tfp410_pins>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				tfp410_in: endpoint@0 {
					remote-endpoint = <&dpi_out>;
				};
			};

			port@1 {
				reg = <1>;

				tfp410_out: endpoint@0 {
					remote-endpoint = <&dvi_connector_in>;
				};
			};
		};
	};

	dvi0: connector@0 {
		compatible = "dvi-connector";
		label = "dvi";

		i2c-bus = <&i2c3>;

		port {
			dvi_connector_in: endpoint {
				remote-endpoint = <&tfp410_out>;
			};
		};
	};

	tpd12s015: encoder@1 {
		compatible = "ti,tpd12s015";

		pinctrl-names = "default";
		pinctrl-0 = <&tpd12s015_pins>;

		gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>,	/* 60, CT CP HPD */
			<&gpio2 9 GPIO_ACTIVE_HIGH>,	/* 41, LS OE */
			<&gpio2 31 GPIO_ACTIVE_HIGH>;	/* 63, HPD */

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				tpd12s015_in: endpoint@0 {
					remote-endpoint = <&hdmi_out>;
				};
			};

			port@1 {
				reg = <1>;

				tpd12s015_out: endpoint@0 {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};

	hdmi0: connector@1 {
		compatible = "hdmi-connector";
		label = "hdmi";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&tpd12s015_out>;
			};
		};
	};
};

&dss {
	status = "ok";

	pinctrl-names = "default";
	pinctrl-0 = <&dss_dpi_pins>;

	port {
		dpi_out: endpoint {
			remote-endpoint = <&tfp410_in>;
			data-lines = <24>;
		};
	};
};

&hdmi {
	status = "ok";
	vdda-supply = <&vdac>;

	pinctrl-names = "default";
	pinctrl-0 = <&dss_hdmi_pins>;

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&tpd12s015_in>;
		};
	};
};


code:
Texas Instruments OMAP2 Display Subsystem
=========================================

See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
description about OMAP Display Subsystem bindings.

DSS Core
--------

Required properties:
- compatible: "ti,omap2-dss"
- reg: address and length of the register space
- ti,hwmods: "dss_core"

Optional nodes:
- Video port for DPI output

DPI Endpoint required properties:
- data-lines: number of lines used

DISPC
-----

Required properties:
- compatible: "ti,omap2-dispc"
- reg: address and length of the register space
- ti,hwmods: "dss_dispc"
- interrupts: the DISPC interrupt

Optional properties:
- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
			in bytes per second

RFBI
----

Required properties:
- compatible: "ti,omap2-rfbi"
- reg: address and length of the register space
- ti,hwmods: "dss_rfbi"

VENC
----

Required properties:
- compatible: "ti,omap2-venc"
- reg: address and length of the register space
- ti,hwmods: "dss_venc"
- vdda-supply: power supply for DAC

VENC Endpoint required properties:

Required properties:
- ti,invert-polarity: invert the polarity of the video signal
- ti,channels: 1 for composite, 2 for s-video


code:
Texas Instruments OMAP3 Display Subsystem
=========================================

See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
description about OMAP Display Subsystem bindings.

DSS Core
--------

Required properties:
- compatible: "ti,omap3-dss"
- reg: address and length of the register space
- ti,hwmods: "dss_core"
- clocks: handle to fclk
- clock-names: "fck"

Optional nodes:
- Video ports:
	- Port 0: DPI output
	- Port 1: SDI output

DPI Endpoint required properties:
- data-lines: number of lines used

SDI Endpoint required properties:
- datapairs: number of datapairs used

DISPC
-----

Required properties:
- compatible: "ti,omap3-dispc"
- reg: address and length of the register space
- ti,hwmods: "dss_dispc"
- interrupts: the DISPC interrupt
- clocks: handle to fclk
- clock-names: "fck"

Optional properties:
- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
			in bytes per second

RFBI
----

Required properties:
- compatible: "ti,omap3-rfbi"
- reg: address and length of the register space
- ti,hwmods: "dss_rfbi"
- clocks: handles to fclk and iclk
- clock-names: "fck", "ick"

VENC
----

Required properties:
- compatible: "ti,omap3-venc"
- reg: address and length of the register space
- ti,hwmods: "dss_venc"
- vdda-supply: power supply for DAC
- clocks: handle to fclk
- clock-names: "fck"

VENC Endpoint required properties:
- ti,invert-polarity: invert the polarity of the video signal
- ti,channels: 1 for composite, 2 for s-video

DSI
---

Required properties:
- compatible: "ti,omap3-dsi"
- reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
- reg-names: "proto", "phy", "pll"
- interrupts: the DSI interrupt line
- ti,hwmods: "dss_dsi1"
- vdd-supply: power supply for DSI
- clocks: handles to fclk and pll clock
- clock-names: "fck", "sys_clk"

DSI Endpoint required properties:
- lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
  DATA1+, DATA1-, ...


code:
Texas Instruments OMAP4 Display Subsystem
=========================================

See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
description about OMAP Display Subsystem bindings.

DSS Core
--------

Required properties:
- compatible: "ti,omap4-dss"
- reg: address and length of the register space
- ti,hwmods: "dss_core"
- clocks: handle to fclk
- clock-names: "fck"

Required nodes:
- DISPC

Optional nodes:
- DSS Submodules: RFBI, VENC, DSI, HDMI
- Video port for DPI output

DPI Endpoint required properties:
- data-lines: number of lines used

DISPC
-----

Required properties:
- compatible: "ti,omap4-dispc"
- reg: address and length of the register space
- ti,hwmods: "dss_dispc"
- interrupts: the DISPC interrupt
- clocks: handle to fclk
- clock-names: "fck"

Optional properties:
- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
			in bytes per second

RFBI
----

Required properties:
- compatible: "ti,omap4-rfbi"
- reg: address and length of the register space
- ti,hwmods: "dss_rfbi"
- clocks: handles to fclk and iclk
- clock-names: "fck", "ick"

Optional nodes:
- Video port for RFBI output
- RFBI controlled peripherals

VENC
----

Required properties:
- compatible: "ti,omap4-venc"
- reg: address and length of the register space
- ti,hwmods: "dss_venc"
- vdda-supply: power supply for DAC
- clocks: handle to fclk
- clock-names: "fck"

Optional nodes:
- Video port for VENC output

VENC Endpoint required properties:
- ti,invert-polarity: invert the polarity of the video signal
- ti,channels: 1 for composite, 2 for s-video

DSI
---

Required properties:
- compatible: "ti,omap4-dsi"
- reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
- reg-names: "proto", "phy", "pll"
- interrupts: the DSI interrupt line
- ti,hwmods: "dss_dsi1" or "dss_dsi2"
- vdd-supply: power supply for DSI
- clocks: handles to fclk and pll clock
- clock-names: "fck", "sys_clk"

Optional nodes:
- Video port for DSI output
- DSI controlled peripherals

DSI Endpoint required properties:
- lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
  DATA1+, DATA1-, ...

HDMI
----

Required properties:
- compatible: "ti,omap4-hdmi"
- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
       'core'
- reg-names: "wp", "pll", "phy", "core"
- interrupts: the HDMI interrupt line
- ti,hwmods: "dss_hdmi"
- vdda-supply: vdda power supply
- clocks: handles to fclk and pll clock
- clock-names: "fck", "sys_clk"

Optional nodes:
- Video port for HDMI output

HDMI Endpoint optional properties:
- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
  D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7)


code:
Texas Instruments OMAP5 Display Subsystem
=========================================

See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
description about OMAP Display Subsystem bindings.

DSS Core
--------

Required properties:
- compatible: "ti,omap5-dss"
- reg: address and length of the register space
- ti,hwmods: "dss_core"
- clocks: handle to fclk
- clock-names: "fck"

Required nodes:
- DISPC

Optional nodes:
- DSS Submodules: RFBI, DSI, HDMI
- Video port for DPI output

DPI Endpoint required properties:
- data-lines: number of lines used

DISPC
-----

Required properties:
- compatible: "ti,omap5-dispc"
- reg: address and length of the register space
- ti,hwmods: "dss_dispc"
- interrupts: the DISPC interrupt
- clocks: handle to fclk
- clock-names: "fck"

Optional properties:
- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
			in bytes per second

RFBI
----

Required properties:
- compatible: "ti,omap5-rfbi"
- reg: address and length of the register space
- ti,hwmods: "dss_rfbi"
- clocks: handles to fclk and iclk
- clock-names: "fck", "ick"

Optional nodes:
- Video port for RFBI output
- RFBI controlled peripherals

DSI
---

Required properties:
- compatible: "ti,omap5-dsi"
- reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
- reg-names: "proto", "phy", "pll"
- interrupts: the DSI interrupt line
- ti,hwmods: "dss_dsi1" or "dss_dsi2"
- vdd-supply: power supply for DSI
- clocks: handles to fclk and pll clock
- clock-names: "fck", "sys_clk"

Optional nodes:
- Video port for DSI output
- DSI controlled peripherals

DSI Endpoint required properties:
- lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
  DATA1+, DATA1-, ...

HDMI
----

Required properties:
- compatible: "ti,omap5-hdmi"
- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
       'core'
- reg-names: "wp", "pll", "phy", "core"
- interrupts: the HDMI interrupt line
- ti,hwmods: "dss_hdmi"
- vdda-supply: vdda power supply
- clocks: handles to fclk and pll clock
- clock-names: "fck", "sys_clk"

Optional nodes:
- Video port for HDMI output

HDMI Endpoint optional properties:
- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
  D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7)


code:
OPA362 analog video amplifier

Required properties:
- compatible: "ti,opa362"
- enable-gpios: enable/disable output gpio

Required node:
- Video port 0 for opa362 input
- Video port 1 for opa362 output

Example:

tv_amp: opa362 {
	compatible = "ti,opa362";
	enable-gpios = <&gpio1 23 0>;  /* GPIO to enable video out amplifier */

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			opa_in: endpoint@0 {
				remote-endpoint = <&venc_out>;
			};
		};

		port@1 {
			reg = <1>;
			opa_out: endpoint@0 {
				remote-endpoint = <&tv_connector_in>;
			};
		};
	};
};


code:
TPD12S015 HDMI level shifter and ESD protection chip
====================================================

Required properties:
- compatible: "ti,tpd12s015"

Optional properties:
- gpios: CT CP HPD, LS OE and HPD gpios

Required nodes:
- Video port 0 for HDMI input
- Video port 1 for HDMI output

Example
-------

tpd12s015: encoder@1 {
	compatible = "ti,tpd12s015";

	gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>,	/* 60, CT CP HPD */
		<&gpio2 9 GPIO_ACTIVE_HIGH>,	/* 41, LS OE */
		<&gpio2 31 GPIO_ACTIVE_HIGH>;	/* 63, HPD */

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;

			tpd12s015_in: endpoint@0 {
				remote-endpoint = <&hdmi_out>;
			};
		};

		port@1 {
			reg = <1>;

			tpd12s015_out: endpoint@0 {
				remote-endpoint = <&hdmi_connector_in>;
			};
		};
	};
};


code:
Device-Tree bindings for tilcdc DRM generic panel output driver

Required properties:
 - compatible: value should be "ti,tilcdc,panel".
 - panel-info: configuration info to configure LCDC correctly for the panel
   - ac-bias: AC Bias Pin Frequency
   - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
   - dma-burst-sz: DMA burst size
   - bpp: Bits per pixel
   - fdd: FIFO DMA Request Delay
   - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
   - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
   - raster-order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most
   - fifo-th: DMA FIFO threshold
 - display-timings: typical videomode of lcd panel.  Multiple video modes
   can be listed if the panel supports multiple timings, but the 'native-mode'
   should be the preferred/default resolution.  Refer to
   Documentation/devicetree/bindings/display/panel/display-timing.txt for display
   timing binding details.

Optional properties:
- backlight: phandle of the backlight device attached to the panel
- enable-gpios: GPIO pin to enable or disable the panel

Recommended properties:
 - pinctrl-names, pinctrl-0: the pincontrol settings to configure
   muxing properly for pins that connect to TFP410 device

Example:

	/* Settings for CDTech_S035Q01 / LCD3 cape: */
	lcd3 {
		compatible = "ti,tilcdc,panel";
		pinctrl-names = "default";
		pinctrl-0 = <&bone_lcd3_cape_lcd_pins>;
		backlight = <&backlight>;
		enable-gpios = <&gpio3 19 0>;

		panel-info {
			ac-bias           = <255>;
			ac-bias-intrpt    = <0>;
			dma-burst-sz      = <16>;
			bpp               = <16>;
			fdd               = <0x80>;
			sync-edge         = <0>;
			sync-ctrl         = <1>;
			raster-order      = <0>;
			fifo-th           = <0>;
		};
		display-timings {
			native-mode = <&timing0>;
			timing0: 320x240 {
				hactive         = <320>;
				vactive         = <240>;
				hback-porch     = <21>;
				hfront-porch    = <58>;
				hsync-len       = <47>;
				vback-porch     = <11>;
				vfront-porch    = <23>;
				vsync-len       = <2>;
				clock-frequency = <8000000>;
				hsync-active    = <0>;
				vsync-active    = <0>;
			};
		};
	};


code:
Device-Tree bindings for tilcdc DRM driver

Required properties:
 - compatible: value should be one of the following:
    - "ti,am33xx-tilcdc" for AM335x based boards
    - "ti,da850-tilcdc" for DA850/AM18x/OMAP-L138 based boards
 - interrupts: the interrupt number
 - reg: base address and size of the LCDC device

Recommended properties:
 - ti,hwmods: Name of the hwmod associated to the LCDC

Optional properties:
 - max-bandwidth: The maximum pixels per second that the memory
   interface / lcd controller combination can sustain
 - max-width: The maximum horizontal pixel width supported by
   the lcd controller.
 - max-pixelclock: The maximum pixel clock that can be supported
   by the lcd controller in KHz.
 - blue-and-red-wiring: Recognized values "straight" or "crossed".
   This property deals with the LCDC revision 2 (found on AM335x)
   color errata [1].
    - "straight" indicates normal wiring that supports RGB565,
      BGR888, and XBGR8888 color formats.
    - "crossed" indicates wiring that has blue and red wires
      crossed. This setup supports BGR565, RGB888 and XRGB8888
      formats.
    - If the property is not present or its value is not recognized
      the legacy mode is assumed. This configuration supports RGB565,
      RGB888 and XRGB8888 formats. However, depending on wiring, the red
      and blue colors are swapped in either 16 or 24-bit color modes.

Optional nodes:

 - port/ports: to describe a connection to an external encoder. The
   binding follows Documentation/devicetree/bindings/graph.txt and
   supports a single port with a single endpoint.

 - See also Documentation/devicetree/bindings/display/tilcdc/panel.txt and
   Documentation/devicetree/bindings/display/bridge/ti,tfp410.yaml for connecting
   tfp410 DVI encoder or lcd panel to lcdc

[1] There is an errata about AM335x color wiring. For 16-bit color mode
    the wires work as they should (LCD_DATA[0:4] is for Blue[3:7]),
    but for 24 bit color modes the wiring of blue and red components is
    crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is
    for Blue[3-7]. For more details see section 3.1.1 in AM335x
    Silicon Errata:
    https://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360

Example:

	fb: fb@4830e000 {
		compatible = "ti,am33xx-tilcdc", "ti,da850-tilcdc";
		reg = <0x4830e000 0x1000>;
		interrupt-parent = <&intc>;
		interrupts = <36>;
		ti,hwmods = "lcdc";

		blue-and-red-wiring = "crossed";

		port {
			lcdc_0: endpoint {
				remote-endpoint = <&hdmi_0>;
			};
		};
	};

	tda19988: tda19988 {
		compatible = "nxp,tda998x";
		reg = <0x70>;

		pinctrl-names = "default", "off";
		pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
		pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;

		port {
			hdmi_0: endpoint {
				remote-endpoint = <&lcdc_0>;
			};
		};
	};


code:
Truly model NT35597 DSI display driver

The Truly NT35597 is a generic display driver, currently only configured
for use in the 2K display on the Qualcomm SDM845 MTP board.

Required properties:
- compatible: should be "truly,nt35597-2K-display"
- vdda-supply: phandle of the regulator that provides the supply voltage
  Power IC supply
- vdispp-supply: phandle of the regulator that provides the supply voltage
  for positive LCD bias
- vdispn-supply: phandle of the regulator that provides the supply voltage
  for negative LCD bias
- reset-gpios: phandle of gpio for reset line
  This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names
  (active low)
- mode-gpios: phandle of the gpio for choosing the mode of the display
  for single DSI or Dual DSI
  This should be low for dual DSI and high for single DSI mode
- ports: This device has two video ports driven by two DSIs. Their connections
  are modeled using the OF graph bindings specified in
  Documentation/devicetree/bindings/graph.txt.
  - port@0: DSI input port driven by master DSI
  - port@1: DSI input port driven by secondary DSI

Example:

	dsi@ae94000 {
		panel@0 {
			compatible = "truly,nt35597-2K-display";
			reg = <0>;
			vdda-supply = <&pm8998_l14>;
			vdispp-supply = <&lab_regulator>;
			vdispn-supply = <&ibb_regulator>;
			pinctrl-names = "default", "suspend";
			pinctrl-0 = <&dpu_dsi_active>;
			pinctrl-1 = <&dpu_dsi_suspend>;

			reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
			mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
				port@0 {
					reg = <0>;
					panel0_in: endpoint {
						remote-endpoint = <&dsi0_out>;
					};
				};

				port@1 {
					reg = <1>;
					panel1_in: endpoint {
						remote-endpoint = <&dsi1_out>;
					};
				};
			};
		};
	};


code:
VIA VT8500 Framebuffer
-----------------------------------------------------

Required properties:
- compatible : "via,vt8500-fb"
- reg : Should contain 1 register ranges(address and length)
- interrupts : framebuffer controller interrupt
- bits-per-pixel : bit depth of framebuffer (16 or 32)

Required subnodes:
- display-timings: see display-timing.txt for information

Example:

	fb@d8050800 {
		compatible = "via,vt8500-fb";
		reg = <0xd800e400 0x400>;
		interrupts = <12>;
		bits-per-pixel = <16>;

		display-timings {
			native-mode = <&timing0>;
			timing0: 800x480 {
				clock-frequency = <0>; /* unused but required */
				hactive = <800>;
				vactive = <480>;
				hfront-porch = <40>;
				hback-porch = <88>;
				hsync-len = <0>;
				vback-porch = <32>;
				vfront-porch = <11>;
				vsync-len = <1>;
			};
		};
	};


code:
VIA/Wondermedia Graphics Engine Controller
-----------------------------------------------------

Required properties:
- compatible : "wm,prizm-ge-rops"
- reg : Should contain 1 register ranges(address and length)

Example:

	ge_rops@d8050400 {
		compatible = "wm,prizm-ge-rops";
		reg = <0xd8050400 0x100>;
	};


code:
Wondermedia WM8505 Framebuffer
-----------------------------------------------------

Required properties:
- compatible : "wm,wm8505-fb"
- reg : Should contain 1 register ranges(address and length)
- bits-per-pixel : bit depth of framebuffer (16 or 32)

Required subnodes:
- display-timings: see display-timing.txt for information

Example:

	fb@d8051700 {
		compatible = "wm,wm8505-fb";
		reg = <0xd8051700 0x200>;
		bits-per-pixel = <16>;

		display-timings {
			native-mode = <&timing0>;
			timing0: 800x480 {
				clock-frequency = <0>; /* unused but required */
				hactive = <800>;
				vactive = <480>;
				hfront-porch = <40>;
				hback-porch = <88>;
				hsync-len = <0>;
				vback-porch = <32>;
				vfront-porch = <11>;
				vsync-len = <1>;
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx ZynqMP DisplayPort Subsystem

description: |
  The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
  implements the display and audio pipelines based on the DisplayPort v1.2
  standard. The subsystem includes multiple functional blocks as below:

               +------------------------------------------------------------+
  +--------+   | +----------------+     +-----------+                       |
  | DPDMA  | --->|                | --> |   Video   | Video +-------------+ |
  | 4x vid |   | |                |     | Rendering | -+--> |             | |   +------+
  | 2x aud |   | |  Audio/Video   | --> | Pipeline  |  |    | DisplayPort |---> | PHY0 |
  +--------+   | | Buffer Manager |     +-----------+  |    |   Source    | |   +------+
               | |    and STC     |     +-----------+  |    | Controller  | |   +------+
  Live Video --->|                | --> |   Audio   | Audio |             |---> | PHY1 |
               | |                |     |   Mixer   | --+-> |             | |   +------+
  Live Audio --->|                | --> |           |  ||   +-------------+ |
               | +----------------+     +-----------+  ||                   |
               +---------------------------------------||-------------------+
                                                       vv
                                                 Blended Video and
                                                 Mixed Audio to PL

  The Buffer Manager interacts with external interface such as DMA engines or
  live audio/video streams from the programmable logic. The Video Rendering
  Pipeline blends the video and graphics layers and performs colorspace
  conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort
  Source Controller handles the DisplayPort protocol and connects to external
  PHYs.

  The subsystem supports 2 video and 2 audio streams, and various pixel formats
  and depths up to 4K@30 resolution.

  Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
  (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
  for more details.

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

properties:
  compatible:
    const: xlnx,zynqmp-dpsub-1.7

  reg:
    maxItems: 4
  reg-names:
    items:
      - const: dp
      - const: blend
      - const: av_buf
      - const: aud

  interrupts:
    maxItems: 1

  clocks:
    description:
      The APB clock and at least one video clock are mandatory, the audio clock
      is optional.
    minItems: 2
    items:
      - description: dp_apb_clk is the APB clock
      - description: dp_aud_clk is the Audio clock
      - description:
          dp_vtc_pixel_clk_in is the non-live video clock (from Processing
          System)
      - description:
          dp_live_video_in_clk is the live video clock (from Programmable
          Logic)
  clock-names:
    oneOf:
      - minItems: 2
        items:
          - const: dp_apb_clk
          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
      - minItems: 3
        items:
          - const: dp_apb_clk
          - const: dp_aud_clk
          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  dmas:
    items:
      - description: Video layer, plane 0 (RGB or luma)
      - description: Video layer, plane 1 (U/V or U)
      - description: Video layer, plane 2 (V)
      - description: Graphics layer
  dma-names:
    items:
      - const: vid0
      - const: vid1
      - const: vid2
      - const: gfx0

  phys:
    description: PHYs for the DP data lanes
    minItems: 1
    maxItems: 2
  phy-names:
    minItems: 1
    items:
      - const: dp-phy0
      - const: dp-phy1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description: |
      Connections to the programmable logic and the DisplayPort PHYs. Each port
      shall have a single endpoint.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: The live video input from the programmable logic

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: The live graphics input from the programmable logic

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: The live audio input from the programmable logic

      port@3:
        $ref: /schemas/graph.yaml#/properties/port
        description: The blended video output to the programmable logic

      port@4:
        $ref: /schemas/graph.yaml#/properties/port
        description: The mixed audio output to the programmable logic

      port@5:
        $ref: /schemas/graph.yaml#/properties/port
        description: The DisplayPort output

    required:
      - port@0
      - port@1
      - port@2
      - port@3
      - port@4
      - port@5

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names
  - power-domains
  - resets
  - dmas
  - dma-names
  - phys
  - phy-names
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>

    display@fd4a0000 {
        compatible = "xlnx,zynqmp-dpsub-1.7";
        reg = <0xfd4a0000 0x1000>,
              <0xfd4aa000 0x1000>,
              <0xfd4ab000 0x1000>,
              <0xfd4ac000 0x1000>;
        reg-names = "dp", "blend", "av_buf", "aud";
        interrupts = <0 119 4>;
        interrupt-parent = <&gic>;

        clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";
        clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;

        power-domains = <&pd_dp>;
        resets = <&reset ZYNQMP_RESET_DP>;

        dma-names = "vid0", "vid1", "vid2", "gfx0";
        dmas = <&xlnx_dpdma 0>,
               <&xlnx_dpdma 1>,
               <&xlnx_dpdma 2>,
               <&xlnx_dpdma 3>;

        phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
               <&psgtr 0 PHY_TYPE_DP 1 3>;

        phy-names = "dp-phy0", "dp-phy1";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
            };
            port@1 {
                reg = <1>;
            };
            port@2 {
                reg = <2>;
            };
            port@3 {
                reg = <3>;
            };
            port@4 {
                reg = <4>;
            };
            port@5 {
                reg = <5>;
                dpsub_dp_out: endpoint {
                    remote-endpoint = <&dp_connector>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Bootlin
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Xylon LogiCVC display controller

maintainers:
  - Paul Kocialkowski <paul.kocialkowski@bootlin.com>

description: |
  The Xylon LogiCVC is a display controller that supports multiple layers.
  It is usually implemented as programmable logic and was optimized for use
  with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.

  Because the controller is intended for use in a FPGA, most of the
  configuration of the controller takes place at logic configuration bitstream
  synthesis time. As a result, many of the device-tree bindings are meant to
  reflect the synthesis configuration and must not be configured differently.
  Matching synthesis parameters are provided when applicable.

  Layers are declared in the "layers" sub-node and have dedicated configuration.
  In version 3 of the controller, each layer has fixed memory offset and address
  starting from the video memory base address for its framebuffer. In version 4,
  framebuffers are configured with a direct memory address instead.

properties:
  compatible:
    enum:
      - xylon,logicvc-3.02.a-display
      - xylon,logicvc-4.01.a-display

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 4

  clock-names:
    minItems: 1
    items:
      # vclk is required and must be provided as first item.
      - const: vclk
      # Other clocks are optional and can be provided in any order.
      - enum:
          - vclk2
          - lvdsclk
          - lvdsclkn
      - enum:
          - vclk2
          - lvdsclk
          - lvdsclkn
      - enum:
          - vclk2
          - lvdsclk
          - lvdsclkn

  interrupts:
    maxItems: 1

  memory-region:
    maxItems: 1

  xylon,display-interface:
    enum:
      # Parallel RGB interface (C_DISPLAY_INTERFACE == 0)
      - parallel-rgb
      # ITU-T BR656 interface (C_DISPLAY_INTERFACE == 1)
      - bt656
      # 4-bit LVDS interface (C_DISPLAY_INTERFACE == 2)
      - lvds-4bits
      # 3-bit LVDS interface (C_DISPLAY_INTERFACE == 4)
      - lvds-3bits
      # DVI interface (C_DISPLAY_INTERFACE == 5)
      - dvi
    description: Display output interface (C_DISPLAY_INTERFACE).

  xylon,display-colorspace:
    enum:
      # RGB colorspace (C_DISPLAY_COLOR_SPACE == 0)
      - rgb
      # YUV 4:2:2 colorspace (C_DISPLAY_COLOR_SPACE == 1)
      - yuv422
      # YUV 4:4:4 colorspace (C_DISPLAY_COLOR_SPACE == 2)
      - yuv444
    description: Display output colorspace (C_DISPLAY_COLOR_SPACE).

  xylon,display-depth:
    $ref: "/schemas/types.yaml#/definitions/uint32"
    description: Display output depth (C_PIXEL_DATA_WIDTH).

  xylon,row-stride:
    $ref: "/schemas/types.yaml#/definitions/uint32"
    description: Fixed number of pixels in a framebuffer row (C_ROW_STRIDE).

  xylon,dithering:
    $ref: "/schemas/types.yaml#/definitions/flag"
    description: Dithering module is enabled (C_XCOLOR)

  xylon,background-layer:
    $ref: "/schemas/types.yaml#/definitions/flag"
    description: |
      The last layer is used to display a black background (C_USE_BACKGROUND).
      The layer must still be registered.

  xylon,layers-configurable:
    $ref: "/schemas/types.yaml#/definitions/flag"
    description: |
      Configuration of layers' size, position and offset is enabled
      (C_USE_SIZE_POSITION).

  layers:
    type: object

    properties:
      "#address-cells":
        const: 1

      "#size-cells":
        const: 0

    patternProperties:
      "^layer@[0-9]+$":
        type: object

        properties:
          reg:
            maxItems: 1

          xylon,layer-depth:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description: Layer depth (C_LAYER_X_DATA_WIDTH).

          xylon,layer-colorspace:
            enum:
              # RGB colorspace (C_LAYER_X_TYPE == 0)
              - rgb
              # YUV packed colorspace (C_LAYER_X_TYPE == 0)
              - yuv
            description: Layer colorspace (C_LAYER_X_TYPE).

          xylon,layer-alpha-mode:
            enum:
              # Alpha is configured layer-wide (C_LAYER_X_ALPHA_MODE == 0)
              - layer
              # Alpha is configured per-pixel (C_LAYER_X_ALPHA_MODE == 1)
              - pixel
            description: Alpha mode for the layer (C_LAYER_X_ALPHA_MODE).

          xylon,layer-base-offset:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description: |
              Offset in number of lines (C_LAYER_X_OFFSET) starting from the
              video RAM base (C_VMEM_BASEADDR), only for version 3.

          xylon,layer-buffer-offset:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description: |
              Offset in number of lines (C_BUFFER_*_OFFSET) starting from the
              layer base offset for the second buffer used in double-buffering.

          xylon,layer-primary:
            $ref: "/schemas/types.yaml#/definitions/flag"
            description: |
              Layer should be registered as a primary plane (exactly one is
              required).

        additionalProperties: false

        required:
          - reg
          - xylon,layer-depth
          - xylon,layer-colorspace
          - xylon,layer-alpha-mode

    required:
      - "#address-cells"
      - "#size-cells"
      - layer@0

    additionalProperties: false

    description: |
      The description of the display controller layers, containing layer
      sub-nodes that each describe a registered layer.

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description: |
      Video output port, typically connected to a panel or bridge.

additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts
  - xylon,display-interface
  - xylon,display-colorspace
  - xylon,display-depth
  - xylon,row-stride
  - layers
  - port

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    logicvc: logicvc@43c00000 {
      compatible = "xylon,logicvc-3.02.a", "syscon", "simple-mfd";
      reg = <0x43c00000 0x6000>;

      #address-cells = <1>;
      #size-cells = <1>;

      logicvc_display: display@0 {
        compatible = "xylon,logicvc-3.02.a-display";
        reg = <0x0 0x6000>;

        memory-region = <&logicvc_cma>;

        clocks = <&logicvc_vclk 0>, <&logicvc_lvdsclk 0>;
        clock-names = "vclk", "lvdsclk";

        interrupt-parent = <&intc>;
        interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;

        xylon,display-interface = "lvds-4bits";
        xylon,display-colorspace = "rgb";
        xylon,display-depth = <16>;
        xylon,row-stride = <1024>;

        xylon,layers-configurable;

        layers {
          #address-cells = <1>;
          #size-cells = <0>;

          layer@0 {
            reg = <0>;
            xylon,layer-depth = <16>;
            xylon,layer-colorspace = "rgb";
            xylon,layer-alpha-mode = "layer";
            xylon,layer-base-offset = <0>;
            xylon,layer-buffer-offset = <480>;
            xylon,layer-primary;
          };

          layer@1 {
            reg = <1>;
            xylon,layer-depth = <16>;
            xylon,layer-colorspace = "rgb";
            xylon,layer-alpha-mode = "layer";
            xylon,layer-base-offset = <2400>;
            xylon,layer-buffer-offset = <480>;
          };

          layer@2 {
            reg = <2>;
            xylon,layer-depth = <16>;
            xylon,layer-colorspace = "rgb";
            xylon,layer-alpha-mode = "layer";
            xylon,layer-base-offset = <960>;
            xylon,layer-buffer-offset = <480>;
          };

          layer@3 {
            reg = <3>;
            xylon,layer-depth = <16>;
            xylon,layer-colorspace = "rgb";
            xylon,layer-alpha-mode = "layer";
            xylon,layer-base-offset = <480>;
            xylon,layer-buffer-offset = <480>;
          };

          layer@4 {
            reg = <4>;
            xylon,layer-depth = <16>;
            xylon,layer-colorspace = "rgb";
            xylon,layer-alpha-mode = "layer";
            xylon,layer-base-offset = <8192>;
            xylon,layer-buffer-offset = <480>;
          };
        };

        port {
          #address-cells = <1>;
          #size-cells = <0>;

          logicvc_output: endpoint@0 {
            reg = <0>;
            remote-endpoint = <&panel_input>;
          };
        };
      };
    };


code:
Analog Devices AXI-DMAC DMA controller

Required properties:
 - compatible: Must be "adi,axi-dmac-1.00.a".
 - reg: Specification for the controllers memory mapped register map.
 - interrupts: Specification for the controllers interrupt.
 - clocks: Phandle and specifier to the controllers AXI interface clock
 - #dma-cells: Must be 1.

Required sub-nodes:
 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
   the channel sub-nodes the following bindings apply. They must match the
   configuration options of the peripheral as it was instantiated.

Required properties for adi,channels sub-node:
 - #size-cells: Must be 0
 - #address-cells: Must be 1

Required channel sub-node properties:
 - reg: Which channel this node refers to.
 - adi,source-bus-width,
   adi,destination-bus-width: Width of the source or destination bus in bits.
 - adi,source-bus-type,
   adi,destination-bus-type: Type of the source or destination bus. Must be one
   of the following:
	0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
	1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
	2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface

Deprecated optional channel properties:
 - adi,length-width: Width of the DMA transfer length register.
 - adi,cyclic: Must be set if the channel supports hardware cyclic DMA
   transfers.
 - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.

DMA clients connected to the AXI-DMAC DMA controller must use the format
described in the dma.txt file using a one-cell specifier. The value of the
specifier refers to the DMA channel index.

Example:

dma: dma@7c420000 {
	compatible = "adi,axi-dmac-1.00.a";
	reg = <0x7c420000 0x10000>;
	interrupts = <0 57 0>;
	clocks = <&clkc 16>;
	#dma-cells = <1>;

	adi,channels {
		#size-cells = <0>;
		#address-cells = <1>;

		dma-channel@0 {
			reg = <0>;
			adi,source-bus-width = <32>;
			adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;
			adi,destination-bus-width = <64>;
			adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;
		};
	};
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/allwinner,sun4i-a10-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 DMA Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  "#dma-cells":
    const: 2
    description:
      The first cell is either 0 or 1, the former to use the normal
      DMA, 1 for dedicated DMA. The second cell is the request line
      number.

  compatible:
    const: allwinner,sun4i-a10-dma

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - "#dma-cells"
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    dma: dma-controller@1c02000 {
        compatible = "allwinner,sun4i-a10-dma";
        reg = <0x01c02000 0x1000>;
        interrupts = <27>;
        clocks = <&ahb_gates 6>;
        #dma-cells = <2>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/allwinner,sun50i-a64-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A64 DMA Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  "#dma-cells":
    const: 1
    description: The cell is the request line number.

  compatible:
    oneOf:
      - enum:
          - allwinner,sun20i-d1-dma
          - allwinner,sun50i-a64-dma
          - allwinner,sun50i-a100-dma
          - allwinner,sun50i-h6-dma
      - items:
          - const: allwinner,sun8i-r40-dma
          - const: allwinner,sun50i-a64-dma

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    items:
      - const: bus
      - const: mbus

  resets:
    maxItems: 1

required:
  - "#dma-cells"
  - compatible
  - reg
  - interrupts
  - clocks
  - resets
  - dma-channels

if:
  properties:
    compatible:
      enum:
        - allwinner,sun20i-d1-dma
        - allwinner,sun50i-a100-dma
        - allwinner,sun50i-h6-dma

then:
  properties:
    clocks:
      minItems: 2

  required:
    - clock-names

else:
  properties:
    clocks:
      maxItems: 1

unevaluatedProperties: false

examples:
  - |
    dma: dma-controller@1c02000 {
        compatible = "allwinner,sun50i-a64-dma";
        reg = <0x01c02000 0x1000>;
        interrupts = <0 50 4>;
        clocks = <&ccu 30>;
        dma-channels = <8>;
        dma-requests = <27>;
        resets = <&ccu 7>;
        #dma-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/allwinner,sun6i-a31-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 DMA Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  "#dma-cells":
    const: 1
    description: The cell is the request line number.

  compatible:
    enum:
      - allwinner,sun6i-a31-dma
      - allwinner,sun8i-a23-dma
      - allwinner,sun8i-a83t-dma
      - allwinner,sun8i-h3-dma
      - allwinner,sun8i-v3s-dma

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - "#dma-cells"
  - compatible
  - reg
  - interrupts
  - clocks
  - resets

additionalProperties: false

examples:
  - |
    dma: dma-controller@1c02000 {
        compatible = "allwinner,sun6i-a31-dma";
        reg = <0x01c02000 0x1000>;
        interrupts = <0 50 4>;
        clocks = <&ahb1_gates 6>;
        resets = <&ahb1_rst 6>;
        #dma-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Altera mSGDMA IP core

maintainers:
  - Olivier Dautricourt <olivierdautricourt@gmail.com>

description: |
  Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
  intellectual property (IP)

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    const: altr,socfpga-msgdma

  reg:
    items:
      - description: Control and Status Register Slave Port
      - description: Descriptor Slave Port
      - description: Response Slave Port (Optional)
    minItems: 2

  reg-names:
    items:
      - const: csr
      - const: desc
      - const: resp
    minItems: 2

  interrupts:
    maxItems: 1

  "#dma-cells":
    const: 1
    description:
      The cell identifies the channel id (must be 0)

required:
  - compatible
  - reg
  - reg-names
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    msgdma_controller: dma-controller@ff200b00 {
        compatible = "altr,socfpga-msgdma";
        reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;
        reg-names = "csr", "desc", "resp";
        interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
        #dma-cells = <1>;
    };


code:
Applied Micro X-Gene SoC DMA nodes

DMA nodes are defined to describe on-chip DMA interfaces in
APM X-Gene SoC.

Required properties for DMA interfaces:
- compatible: Should be "apm,xgene-dma".
- device_type: set to "dma".
- reg: Address and length of the register set for the device.
  It contains the information of registers in the following order:
  1st - DMA control and status register address space.
  2nd - Descriptor ring control and status register address space.
  3rd - Descriptor ring command register address space.
  4th - Soc efuse register address space.
- interrupts: DMA has 5 interrupts sources. 1st interrupt is
  DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
  are completion interrupts for each DMA channels.
- clocks: Reference to the clock entry.

Optional properties:
- dma-coherent : Present if dma operations are coherent

Example:
	dmaclk: dmaclk@1f27c000 {
		compatible = "apm,xgene-device-clock";
		#clock-cells = <1>;
		clocks = <&socplldiv2 0>;
		reg = <0x0 0x1f27c000 0x0 0x1000>;
		reg-names = "csr-reg";
		clock-output-names = "dmaclk";
	};

	dma: dma@1f270000 {
			compatible = "apm,xgene-storm-dma";
			device_type = "dma";
			reg = <0x0 0x1f270000 0x0 0x10000>,
			      <0x0 0x1f200000 0x0 0x10000>,
			      <0x0 0x1b000000 0x0 0x400000>,
			      <0x0 0x1054a000 0x0 0x100>;
			interrupts = <0x0 0x82 0x4>,
				     <0x0 0xb8 0x4>,
				     <0x0 0xb9 0x4>,
				     <0x0 0xba 0x4>,
				     <0x0 0xbb 0x4>;
			dma-coherent;
			clocks = <&dmaclk 0>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/apple,admac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple Audio DMA Controller (ADMAC)

description: |
  Apple's Audio DMA Controller (ADMAC) is used to fetch and store audio samples
  on SoCs from the "Apple Silicon" family.

  The controller has been seen with up to 24 channels. Even-numbered channels
  are TX-only, odd-numbered are RX-only. Individual channels are coupled to
  fixed device endpoints.

maintainers:
  - Martin Povišer <povik+lin@cutebit.org>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    items:
      - enum:
          - apple,t6000-admac
          - apple,t8103-admac
      - const: apple,admac

  reg:
    maxItems: 1

  '#dma-cells':
    const: 1
    description:
      Clients specify a single cell with channel number.

  dma-channels:
    maximum: 24

  interrupts:
    minItems: 4
    maxItems: 4
    description:
      Interrupts that correspond to the 4 IRQ outputs of the controller. Usually
      only one of the controller outputs will be connected as an usable interrupt
      source. The remaining interrupts will be left without a valid value, e.g.
      in an interrupts-extended list the disconnected positions will contain
      an empty phandle reference <0>.

  iommus:
    minItems: 1
    maxItems: 2

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - '#dma-cells'
  - dma-channels
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/apple-aic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    aic: interrupt-controller {
      interrupt-controller;
      #interrupt-cells = <3>;
    };

    admac: dma-controller@238200000 {
      compatible = "apple,t8103-admac", "apple,admac";
      reg = <0x38200000 0x34000>;
      dma-channels = <24>;
      interrupts-extended = <0>,
                            <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>,
                            <0>,
                            <0>;
      #dma-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/arm,pl330.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM PrimeCell PL330 DMA Controller

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description:
  The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
  between memory and peripherals or memory to memory.

# We need a select here so we don't match all nodes with 'arm,primecell'
select:
  properties:
    compatible:
      contains:
        const: arm,pl330
  required:
    - compatible

allOf:
  - $ref: dma-controller.yaml#
  - $ref: /schemas/arm/primecell.yaml#

properties:
  compatible:
    items:
      - enum:
          - arm,pl330
      - const: arm,primecell

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 32
    description: A single combined interrupt or an interrupt per event

  '#dma-cells':
    const: 1
    description: Contains the DMA request number for the consumer

  arm,pl330-broken-no-flushp:
    type: boolean
    description: quirk for avoiding to execute DMAFLUSHP

  arm,pl330-periph-burst:
    type: boolean
    description: quirk for performing burst transfer only

  dma-coherent: true

  iommus:
    minItems: 1
    maxItems: 9
    description: Up to 1 IOMMU entry per DMA channel for writes and 1
      IOMMU entry for reads.

  power-domains:
    maxItems: 1

  resets:
    minItems: 1
    maxItems: 2

  reset-names:
    minItems: 1
    items:
      - const: dma
      - const: dma-ocp

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    dma-controller@12680000 {
        compatible = "arm,pl330", "arm,primecell";
        reg = <0x12680000 0x1000>;
        interrupts = <99>;
        #dma-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller

maintainers:
  - Vinod Koul <vkoul@kernel.org>

allOf:
  - $ref: /schemas/arm/primecell.yaml#
  - $ref: "dma-controller.yaml#"

# We need a select here so we don't match all nodes with 'arm,primecell'
select:
  properties:
    compatible:
      contains:
        enum:
          - arm,pl080
          - arm,pl081
  required:
    - compatible

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - arm,pl080
              - arm,pl081
          - const: arm,primecell
      - items:
          - const: faraday,ftdma020
          - const: arm,pl080
          - const: arm,primecell

  reg:
    maxItems: 1
    description: Address range of the PL08x registers

  interrupts:
    minItems: 1
    description: The PL08x interrupt number

  clocks:
    minItems: 1
    description: The clock running the IP core clock

  clock-names:
    maxItems: 1

  lli-bus-interface-ahb1:
    type: boolean
    description: if AHB master 1 is eligible for fetching LLIs

  lli-bus-interface-ahb2:
    type: boolean
    description: if AHB master 2 is eligible for fetching LLIs

  mem-bus-interface-ahb1:
    type: boolean
    description: if AHB master 1 is eligible for fetching memory contents

  mem-bus-interface-ahb2:
    type: boolean
    description: if AHB master 2 is eligible for fetching memory contents

  memcpy-burst-size:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum:
      - 1
      - 4
      - 8
      - 16
      - 32
      - 64
      - 128
      - 256
    description: the size of the bursts for memcpy

  memcpy-bus-width:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum:
      - 8
      - 16
      - 32
      - 64
    description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits

  resets:
    maxItems: 1

required:
  - reg
  - interrupts
  - clocks
  - clock-names
  - "#dma-cells"

unevaluatedProperties: false

examples:
  - |
    dmac0: dma-controller@10130000 {
      compatible = "arm,pl080", "arm,primecell";
      reg = <0x10130000 0x1000>;
      interrupt-parent = <&vica>;
      interrupts = <15>;
      clocks = <&hclkdma0>;
      clock-names = "apb_pclk";
      lli-bus-interface-ahb1;
      lli-bus-interface-ahb2;
      mem-bus-interface-ahb2;
      memcpy-burst-size = <256>;
      memcpy-bus-width = <32>;
      #dma-cells = <2>;
    };
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/reset/cortina,gemini-reset.h>
    #include <dt-bindings/clock/cortina,gemini-clock.h>
    dma-controller@67000000 {
      compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
      /* Faraday Technology FTDMAC020 variant */
      arm,primecell-periphid = <0x0003b080>;
      reg = <0x67000000 0x1000>;
      interrupts = <9 IRQ_TYPE_EDGE_RISING>;
      resets = <&syscon GEMINI_RESET_DMAC>;
      clocks = <&syscon GEMINI_CLK_AHB>;
      clock-names = "apb_pclk";
      /* Bus interface AHB1 (AHB0) is totally tilted */
      lli-bus-interface-ahb2;
      mem-bus-interface-ahb2;
      memcpy-burst-size = <256>;
      memcpy-bus-width = <32>;
      #dma-cells = <2>;
    };


code:
* Atmel Direct Memory Access Controller (DMA)

Required properties:
- compatible: Should be "atmel,<chip>-dma".
- reg: Should contain DMA registers location and length.
- interrupts: Should contain DMA interrupt.
- #dma-cells: Must be <2>, used to represent the number of integer cells in
the dmas property of client devices.

Example:

dma0: dma@ffffec00 {
	compatible = "atmel,at91sam9g45-dma";
	reg = <0xffffec00 0x200>;
	interrupts = <21>;
	#dma-cells = <2>;
};

DMA clients connected to the Atmel DMA controller must use the format
described in the dma.txt file, using a three-cell specifier for each channel:
a phandle plus two integer cells.
The three cells in order are:

1. A phandle pointing to the DMA controller.
2. The memory interface (16 most significant bits), the peripheral interface
(16 less significant bits).
3. Parameters for the at91 DMA configuration register which are device
dependent:
  - bit 7-0: peripheral identifier for the hardware handshaking interface. The
  identifier can be different for tx and rx.
  - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.

Example:

i2c0@i2c@f8010000 {
	compatible = "atmel,at91sam9x5-i2c";
	reg = <0xf8010000 0x100>;
	interrupts = <9 4 6>;
	dmas = <&dma0 1 7>,
	       <&dma0 1 8>;
	dma-names = "tx", "rx";
};


code:
* Atmel Extensible Direct Memory Access Controller (XDMAC)

* XDMA Controller
Required properties:
- compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or
  "microchip,sama7g5-dma".
- reg: Should contain DMA registers location and length.
- interrupts: Should contain DMA interrupt.
- #dma-cells: Must be <1>, used to represent the number of integer cells in
the dmas property of client devices.
  - The 1st cell specifies the channel configuration register:
    - bit 13: SIF, source interface identifier, used to get the memory
    interface identifier,
    - bit 14: DIF, destination interface identifier, used to get the peripheral
    interface identifier,
    - bit 30-24: PERID, peripheral identifier.

Example:

dma1: dma-controller@f0004000 {
	compatible = "atmel,sama5d4-dma";
	reg = <0xf0004000 0x200>;
	interrupts = <50 4 0>;
	#dma-cells = <1>;
};

* DMA clients
DMA clients connected to the Atmel XDMA controller must use the format
described in the dma.txt file, using a one-cell specifier for each channel.
The two cells in order are:
1. A phandle pointing to the DMA controller.
2. Channel configuration register. Configurable fields are:
    - bit 13: SIF, source interface identifier, used to get the memory
    interface identifier,
    - bit 14: DIF, destination interface identifier, used to get the peripheral
    interface identifier,
  - bit 30-24: PERID, peripheral identifier.

Example:

i2c2: i2c@f8024000 {
	compatible = "atmel,at91sam9x5-i2c";
	reg = <0xf8024000 0x4000>;
	interrupts = <34 4 6>;
	dmas = <&dma1
		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
		 | AT91_XDMAC_DT_PERID(6))>,
	       <&dma1
		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
		| AT91_XDMAC_DT_PERID(7))>;
	dma-names = "tx", "rx";
};


code:
* BCM2835 DMA controller

The BCM2835 DMA controller has 16 channels in total.
Only the lower 13 channels have an associated IRQ.
Some arbitrary channels are used by the firmware
(1,3,6,7 in the current firmware version).
The channels 0,2 and 3 have special functionality
and should not be used by the driver.

Required properties:
- compatible: Should be "brcm,bcm2835-dma".
- reg: Should contain DMA registers location and length.
- interrupts: Should contain the DMA interrupts associated
		to the DMA channels in ascending order.
- interrupt-names: Should contain the names of the interrupt
		   in the form "dmaXX".
		   Use "dma-shared-all" for the common interrupt line
		   that is shared by all dma channels.
- #dma-cells: Must be <1>, the cell in the dmas property of the
		client device represents the DREQ number.
- brcm,dma-channel-mask: Bit mask representing the channels
			 not used by the firmware in ascending order,
			 i.e. first channel corresponds to LSB.

Example:

dma: dma@7e007000 {
	compatible = "brcm,bcm2835-dma";
	reg = <0x7e007000 0xf00>;
	interrupts = <1 16>,
		     <1 17>,
		     <1 18>,
		     <1 19>,
		     <1 20>,
		     <1 21>,
		     <1 22>,
		     <1 23>,
		     <1 24>,
		     <1 25>,
		     <1 26>,
		     /* dma channel 11-14 share one irq */
		     <1 27>,
		     <1 27>,
		     <1 27>,
		     <1 27>,
		     /* unused shared irq for all channels */
		     <1 28>;
	interrupt-names = "dma0",
			  "dma1",
			  "dma2",
			  "dma3",
			  "dma4",
			  "dma5",
			  "dma6",
			  "dma7",
			  "dma8",
			  "dma9",
			  "dma10",
			  "dma11",
			  "dma12",
			  "dma13",
			  "dma14",
			  "dma-shared-all";

	#dma-cells = <1>;
	brcm,dma-channel-mask = <0x7f35>;
};

DMA clients connected to the BCM2835 DMA controller must use the format
described in the dma.txt file, using a two-cell specifier for each channel.

Example:

bcm2835_i2s: i2s@7e203000 {
	compatible = "brcm,bcm2835-i2s";
	reg = <	0x7e203000 0x24>;
	clocks = <&clocks BCM2835_CLOCK_PCM>;

	dmas = <&dma 2>,
	       <&dma 3>;
	dma-names = "tx", "rx";
};


code:
* Broadcom SBA RAID engine

Required properties:
- compatible: Should be one of the following
	      "brcm,iproc-sba"
	      "brcm,iproc-sba-v2"
  The "brcm,iproc-sba" has support for only 6 PQ coefficients
  The "brcm,iproc-sba-v2" has support for only 30 PQ coefficients
- mboxes: List of phandle and mailbox channel specifiers

Example:

raid_mbox: mbox@67400000 {
	...
	#mbox-cells = <3>;
	...
};

raid0 {
	compatible = "brcm,iproc-sba-v2";
	mboxes = <&raid_mbox 0 0x1 0xffff>,
		 <&raid_mbox 1 0x1 0xffff>,
		 <&raid_mbox 2 0x1 0xffff>,
		 <&raid_mbox 3 0x1 0xffff>,
		 <&raid_mbox 4 0x1 0xffff>,
		 <&raid_mbox 5 0x1 0xffff>,
		 <&raid_mbox 6 0x1 0xffff>,
		 <&raid_mbox 7 0x1 0xffff>;
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/dma-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DMA Engine Generic Binding

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description:
  Generic binding to provide a way for a driver using DMA Engine to
  retrieve the DMA request or channel information that goes from a
  hardware device to a DMA controller.

select: false

properties:
  "#dma-cells":
    minimum: 1
    # Should be enough
    maximum: 255
    description:
      Used to provide DMA controller specific information.

  dma-channel-mask:
    description:
      Bitmask of available DMA channels in ascending order that are
      not reserved by firmware and are available to the
      kernel. i.e. first channel corresponds to LSB.
      The first item in the array is for channels 0-31, the second is for
      channels 32-63, etc.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    items:
      minItems: 1
      # Should be enough
      maxItems: 255

  dma-channels:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Number of DMA channels supported by the controller.

  dma-requests:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Number of DMA request signals supported by the controller.

required:
  - "#dma-cells"

additionalProperties: true


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/dma-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DMA Controller Generic Binding

maintainers:
  - Vinod Koul <vkoul@kernel.org>

allOf:
  - $ref: "dma-common.yaml#"

# Everything else is described in the common file
properties:
  $nodename:
    pattern: "^dma-controller(@.*)?$"

additionalProperties: true

examples:
  - |
    dma: dma-controller@48000000 {
        compatible = "ti,omap-sdma";
        reg = <0x48000000 0x1000>;
        interrupts = <0 12 0x4>,
                     <0 13 0x4>,
                     <0 14 0x4>,
                     <0 15 0x4>;
        #dma-cells = <1>;
        dma-channels = <32>;
        dma-requests = <127>;
        dma-channel-mask = <0xfffe>;
    };

...