code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 USB HS PHY controller binding

description:

  The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
  switch. It controls PHY configuration and status, and the UTMI+ switch that
  selects either OTG or HOST controller for the second PHY port. It also sets
  PLL configuration.

  USBPHYC
  |_ PLL
  |
  |_ PHY port#1 _________________ HOST controller
  |                   __                 |
  |                  / 1|________________|
  |_ PHY port#2 ----|   |________________
  |                  \_0|                |
  |_ UTMI switch_______|          OTG controller

maintainers:
  - Amelie Delaunay <amelie.delaunay@foss.st.com>

properties:
  compatible:
    const: st,stm32mp1-usbphyc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  vdda1v1-supply:
    description: regulator providing 1V1 power supply to the PLL block

  vdda1v8-supply:
    description: regulator providing 1V8 power supply to the PLL block

  '#clock-cells':
    description: number of clock cells for ck_usbo_48m consumer
    const: 0

#Required child nodes:

patternProperties:
  "^usb-phy@[0|1]$":
    type: object
    description:
      Each port the controller provides must be represented as a sub-node.

    properties:
      reg:
        description: phy port index.
        maxItems: 1

      phy-supply:
        description: regulator providing 3V3 power supply to the PHY.

      "#phy-cells":
        enum: [ 0x0, 0x1 ]

      connector:
        type: object
        $ref: /schemas/connector/usb-connector.yaml
        unevaluatedProperties: false

        properties:
          vbus-supply: true

      # It can be necessary to adjust the PHY settings to compensate parasitics, which can be due
      # to USB connector/receptacle, routing, ESD protection component,... Here is the list of
      # all optional parameters to tune the interface of the PHY (HS for High-Speed, FS for Full-
      # Speed, LS for Low-Speed)

      st,current-boost-microamp:
        description: Current boosting in uA
        enum: [ 1000, 2000 ]

      st,no-lsfs-fb-cap:
        description: Disables the LS/FS feedback capacitor
        type: boolean

      st,decrease-hs-slew-rate:
        description: Decreases the HS driver slew rate by 10%
        type: boolean

      st,tune-hs-dc-level:
        description: |
          Tunes the HS driver DC level
          - <0> normal level
          - <1> increases the level by 5 to 7 mV
          - <2> increases the level by 10 to 14 mV
          - <3> decreases the level by 5 to 7 mV
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 0
        maximum: 3
        default: 0

      st,enable-fs-rftime-tuning:
        description: Enables the FS rise/fall tuning option
        type: boolean

      st,enable-hs-rftime-reduction:
        description: Enables the HS rise/fall reduction feature
        type: boolean

      st,trim-hs-current:
        description: |
          Controls HS driver current trimming for choke compensation
          - <0> = 18.87 mA target current / nominal + 0%
          - <1> = 19.165 mA target current / nominal + 1.56%
          - <2> = 19.46 mA target current / nominal + 3.12%
          - <3> = 19.755 mA target current / nominal + 4.68%
          - <4> = 20.05 mA target current / nominal + 6.24%
          - <5> = 20.345 mA target current / nominal + 7.8%
          - <6> = 20.64 mA target current / nominal + 9.36%
          - <7> = 20.935 mA target current / nominal + 10.92%
          - <8> = 21.23 mA target current / nominal + 12.48%
          - <9> = 21.525 mA target current / nominal + 14.04%
          - <10> = 21.82 mA target current / nominal + 15.6%
          - <11> = 22.115 mA target current / nominal + 17.16%
          - <12> = 22.458 mA target current / nominal + 19.01%
          - <13> = 22.755 mA target current / nominal + 20.58%
          - <14> = 23.052 mA target current / nominal + 22.16%
          - <15> = 23.348 mA target current / nominal + 23.73%
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 0
        maximum: 15
        default: 0

      st,trim-hs-impedance:
        description: |
          Controls HS driver impedance tuning for choke compensation
          - <0> = no impedance offset
          - <1> = reduce the impedance by 2 ohms
          - <2> = reduce the impedance by 4 ohms
          - <3> = reduce the impedance by 6 ohms
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 0
        maximum: 3
        default: 0

      st,tune-squelch-level:
        description: |
          Tunes the squelch DC threshold value
          - <0> = no shift in threshold
          - <1> = threshold shift by +7 mV
          - <2> = threshold shift by -5 mV
          - <3> = threshold shift by +14 mV
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 0
        maximum: 3
        default: 0

      st,enable-hs-rx-gain-eq:
        description: Enables the HS Rx gain equalizer
        type: boolean

      st,tune-hs-rx-offset:
        description: |
          Adjusts the HS Rx offset
          - <0> = no offset
          - <1> = offset of +5 mV
          - <2> = offset of +10 mV
          - <3> = offset of -5 mV
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 0
        maximum: 3
        default: 0

      st,no-hs-ftime-ctrl:
        description: Disables the HS fall time control of single ended signals during pre-emphasis
        type: boolean

      st,no-lsfs-sc:
        description: Disables the short circuit protection in LS/FS driver
        type: boolean

      st,enable-hs-tx-staggering:
        description: Enables the basic staggering in HS Tx mode
        type: boolean

    allOf:
      - if:
          properties:
            reg:
              const: 0
        then:
          properties:
            "#phy-cells":
              const: 0
        else:
          properties:
            "#phy-cells":
              const: 1
              description:
                The value is used to select UTMI switch output.
                0 for OTG controller and 1 for Host controller.

    required:
      - reg
      - phy-supply
      - "#phy-cells"

    additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - "#address-cells"
  - "#size-cells"
  - vdda1v1-supply
  - vdda1v8-supply
  - usb-phy@0
  - usb-phy@1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    usbphyc: usbphyc@5a006000 {
        compatible = "st,stm32mp1-usbphyc";
        reg = <0x5a006000 0x1000>;
        clocks = <&rcc USBPHY_K>;
        resets = <&rcc USBPHY_R>;
        vdda1v1-supply = <&reg11>;
        vdda1v8-supply = <&reg18>;
        #address-cells = <1>;
        #size-cells = <0>;
        #clock-cells = <0>;

        usbphyc_port0: usb-phy@0 {
            reg = <0>;
            phy-supply = <&vdd_usb>;
            #phy-cells = <0>;
            st,tune-hs-dc-level = <2>;
            st,enable-fs-rftime-tuning;
            st,enable-hs-rftime-reduction;
            st,trim-hs-current = <15>;
            st,trim-hs-impedance = <1>;
            st,tune-squelch-level = <3>;
            st,tune-hs-rx-offset = <2>;
            st,no-lsfs-sc;
            connector {
                compatible = "usb-a-connector";
                vbus-supply = <&vbus_sw>;
            };
        };

        usbphyc_port1: usb-phy@1 {
            reg = <1>;
            phy-supply = <&vdd_usb>;
            #phy-cells = <1>;
            st,tune-hs-dc-level = <2>;
            st,enable-fs-rftime-tuning;
            st,enable-hs-rftime-reduction;
            st,trim-hs-current = <15>;
            st,trim-hs-impedance = <1>;
            st,tune-squelch-level = <3>;
            st,tune-hs-rx-offset = <2>;
            st,no-lsfs-sc;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: NVIDIA Tegra194 & Tegra234 P2U binding

maintainers:
  - Thierry Reding <treding@nvidia.com>

description: >
  Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
  Speed) each interfacing with 12 and 8 P2U instances respectively.
  Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
  each interfacing with 8, 8 and 8 P2U instances respectively.
  A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
  interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
  PCIe lane.

properties:
  compatible:
    enum:
      - nvidia,tegra194-p2u
      - nvidia,tegra234-p2u

  reg:
    maxItems: 1
    description: Should be the physical address space and length of respective each P2U instance.

  reg-names:
    items:
      - const: ctl

  nvidia,skip-sz-protect-en:
    description: Should be present if two PCIe retimers are present between
      the root port and its immediate downstream device.
    type: boolean

  '#phy-cells':
    const: 0

additionalProperties: false

examples:
  - |
    p2u_hsio_0: phy@3e10000 {
        compatible = "nvidia,tegra194-p2u";
        reg = <0x03e10000 0x10000>;
        reg-names = "ctl";

        #phy-cells = <0>;
    };

repo_name: angery/linux


code:
IMG Pistachio USB PHY
=====================

Required properties:
--------------------
 - compatible: Must be "img,pistachio-usb-phy".
 - #phy-cells: Must be 0.  See ./phy-bindings.txt for details.
 - clocks: Must contain an entry for each entry in clock-names.
   See ../clock/clock-bindings.txt for details.
 - clock-names: Must include "usb_phy".
 - img,cr-top: Must constain a phandle to the CR_TOP syscon node.
 - img,refclk: Indicates the reference clock source for the USB PHY.
   See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.

Optional properties:
--------------------
 - phy-supply: USB VBUS supply.  Must supply 5.0V.

Example:
--------
usb_phy: usb-phy {
	compatible = "img,pistachio-usb-phy";
	clocks = <&clk_core CLK_USB_PHY>;
	clock-names = "usb_phy";
	phy-supply = <&usb_vbus>;
	img,refclk = <REFCLK_CLK_CORE>;
	img,cr-top = <&cr_top>;
	#phy-cells = <0>;
};


code:
* Marvell PXA1928 USB and HSIC PHYs

Required properties:
- compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy"
- reg: base address and length of the registers
- clocks - A single clock. From common clock binding.
- #phys-cells: should be 0. From commmon phy binding.
- resets: reference to the reset controller

Example:

	usbphy: phy@7000 {
		compatible = "marvell,pxa1928-usb-phy";
		reg = <0x7000 0xe0>;
		clocks = <&apmu_clocks PXA1928_CLK_USB>;
		#phy-cells = <0>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm eDP PHY

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  The Qualcomm eDP PHY is found in a number of Qualcomm platform and provides
  the physical interface for Embedded Display Port.

properties:
  compatible:
    enum:
      - qcom,sc7280-edp-phy
      - qcom,sc8180x-edp-phy
      - qcom,sc8280xp-dp-phy
      - qcom,sc8280xp-edp-phy

  reg:
    items:
      - description: PHY base register block
      - description: tx0 register block
      - description: tx1 register block
      - description: PLL register block

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: aux
      - const: cfg_ahb

  "#clock-cells":
    const: 1

  "#phy-cells":
    const: 0

  vdda-phy-supply: true
  vdda-pll-supply: true

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#clock-cells"
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    phy@aec2a00 {
      compatible = "qcom,sc8180x-edp-phy";
      reg = <0x0aec2a00 0x1c0>,
            <0x0aec2200 0xa0>,
            <0x0aec2600 0xa0>,
            <0x0aec2000 0x19c>;

      clocks = <&dispcc 0>, <&dispcc 1>;
      clock-names = "aux", "cfg_ahb";

      #clock-cells = <1>;
      #phy-cells = <0>;

      vdda-phy-supply = <&vdd_a_edp_0_1p2>;
      vdda-pll-supply = <&vdd_a_edp_0_0p9>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---

$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Adreno/Snapdragon HDMI phy

maintainers:
  - Rob Clark <robdclark@gmail.com>

properties:
  compatible:
    enum:
      - qcom,hdmi-phy-8660
      - qcom,hdmi-phy-8960
      - qcom,hdmi-phy-8974
      - qcom,hdmi-phy-8084

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: hdmi_phy
      - const: hdmi_pll

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    maxItems: 2

  power-domains:
    maxItems: 1

  core-vdda-supply:
    description: phandle to VDDA supply regulator

  vddio-supply:
    description: phandle to VDD I/O supply regulator

  '#phy-cells':
    const: 0

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,hdmi-phy-8660
              - qcom,hdmi-phy-8960
    then:
      properties:
        clocks:
          maxItems: 1
        clock-names:
          items:
            - const: slave_iface
        vddio-supply: false

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,hdmi-phy-8084
              - qcom,hdmi-phy-8974
    then:
      properties:
        clocks:
          maxItems: 2
        clock-names:
          items:
            - const: iface
            - const: alt_iface

required:
  - compatible
  - clocks
  - reg
  - reg-names
  - '#phy-cells'

additionalProperties: false

examples:
  - |
    hdmi_phy: phy@4a00400 {
      compatible = "qcom,hdmi-phy-8960";
      reg-names = "hdmi_phy",
                  "hdmi_pll";
      reg = <0x4a00400 0x60>,
            <0x4a00500 0x100>;
      #phy-cells = <0>;
      power-domains = <&mmcc 1>;
      clock-names = "slave_iface";
      clocks = <&clk 21>;
      core-vdda-supply = <&pm8921_hdmi_mvs>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---

$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Adreno/Snapdragon QMP HDMI phy

maintainers:
  - Rob Clark <robdclark@gmail.com>

properties:
  compatible:
    enum:
      - qcom,hdmi-phy-8996

  reg:
    maxItems: 6

  reg-names:
    items:
      - const: hdmi_pll
      - const: hdmi_tx_l0
      - const: hdmi_tx_l1
      - const: hdmi_tx_l2
      - const: hdmi_tx_l3
      - const: hdmi_phy

  clocks:
    minItems: 2
    maxItems: 3

  clock-names:
    minItems: 2
    items:
      - const: iface
      - const: ref
      - const: xo

  power-domains:
    maxItems: 1

  vcca-supply:
    description: phandle to VCCA supply regulator

  vddio-supply:
    description: phandle to VDD I/O supply regulator

  '#clock-cells':
    const: 0

  '#phy-cells':
    const: 0

required:
  - compatible
  - clocks
  - clock-names
  - reg
  - reg-names
  - '#phy-cells'

additionalProperties: false

examples:
  - |
    hdmi-phy@9a0600 {
      compatible = "qcom,hdmi-phy-8996";
      reg = <0x009a0600 0x1c4>,
            <0x009a0a00 0x124>,
            <0x009a0c00 0x124>,
            <0x009a0e00 0x124>,
            <0x009a1000 0x124>,
            <0x009a1200 0x0c8>;
      reg-names = "hdmi_pll",
                  "hdmi_tx_l0",
                  "hdmi_tx_l1",
                  "hdmi_tx_l2",
                  "hdmi_tx_l3",
                  "hdmi_phy";

      clocks = <&mmcc 116>,
               <&gcc 214>,
               <&xo_board>;
      clock-names = "iface",
                    "ref",
                    "xo";
      #clock-cells = <0>;
      #phy-cells = <0>;

      vddio-supply = <&vreg_l12a_1p8>;
      vcca-supply = <&vreg_l28a_0p925>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER

maintainers:
  - Ansuel Smith <ansuelsmth@gmail.com>

description:
  DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
  controllers used in ipq806x. Each DWC3 PHY controller should have its
  own node.

properties:
  compatible:
    const: qcom,ipq806x-usb-phy-hs

  "#phy-cells":
    const: 0

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: ref
      - const: xo

required:
  - compatible
  - "#phy-cells"
  - reg
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>

    hs_phy_0: phy@110f8800 {
      compatible = "qcom,ipq806x-usb-phy-hs";
      reg = <0x110f8800 0x30>;
      clocks = <&gcc USB30_0_UTMI_CLK>;
      clock-names = "ref";
      #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER

maintainers:
  - Ansuel Smith <ansuelsmth@gmail.com>

description:
  DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
  controllers used in ipq806x. Each DWC3 PHY controller should have its
  own node.

properties:
  compatible:
    const: qcom,ipq806x-usb-phy-ss

  "#phy-cells":
    const: 0

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: ref
      - const: xo

  qcom,rx-eq:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Override value for rx_eq.
    default: 4
    maximum: 7

  qcom,tx-deamp-3_5db:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Override value for transmit preemphasis.
    default: 23
    maximum: 63

  qcom,mpll:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Override value for mpll.
    default: 0
    maximum: 7

required:
  - compatible
  - "#phy-cells"
  - reg
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>

    ss_phy_0: phy@110f8830 {
      compatible = "qcom,ipq806x-usb-phy-ss";
      reg = <0x110f8830 0x30>;
      clocks = <&gcc USB30_0_MASTER_CLK>;
      clock-names = "ref";
      #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm QMP PHY controller (MSM8996 PCIe)

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description:
  QMP PHY controller supports physical layer functionality for a number of
  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.

properties:
  compatible:
    const: qcom,msm8996-qmp-pcie-phy

  reg:
    items:
      - description: serdes

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

  ranges: true

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: aux
      - const: cfg_ahb
      - const: ref

  resets:
    maxItems: 3

  reset-names:
    items:
      - const: phy
      - const: common
      - const: cfg

  vdda-phy-supply: true

  vdda-pll-supply: true

  vddp-ref-clk-supply: true

patternProperties:
  "^phy@[0-9a-f]+$":
    type: object
    description: one child node per PHY provided by this block
    properties:
      reg:
        items:
          - description: TX
          - description: RX
          - description: PCS

      clocks:
        items:
          - description: PIPE clock

      clock-names:
        deprecated: true
        items:
          - enum:
              - pipe0
              - pipe1
              - pipe2

      resets:
        items:
          - description: PHY reset

      reset-names:
        deprecated: true
        items:
          - enum:
              - lane0
              - lane1
              - lane2

      "#clock-cells":
        const: 0

      clock-output-names:
        maxItems: 1

      "#phy-cells":
        const: 0

    required:
      - reg
      - clocks
      - resets
      - "#clock-cells"
      - clock-output-names
      - "#phy-cells"

    additionalProperties: false

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - clocks
  - clock-names
  - resets
  - reset-names
  - vdda-phy-supply
  - vdda-pll-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
    pcie_phy: phy-wrapper@34000 {
        compatible = "qcom,msm8996-qmp-pcie-phy";
        reg = <0x34000 0x488>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x34000 0x4000>;

        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
                 <&gcc GCC_PCIE_CLKREF_CLK>;
        clock-names = "aux", "cfg_ahb", "ref";

        resets = <&gcc GCC_PCIE_PHY_BCR>,
                 <&gcc GCC_PCIE_PHY_COM_BCR>,
                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
        reset-names = "phy", "common", "cfg";

        vdda-phy-supply = <&vreg_l28a_0p925>;
        vdda-pll-supply = <&vreg_l12a_1p8>;

        pciephy_0: phy@1000 {
            reg = <0x1000 0x130>,
                  <0x1200 0x200>,
                  <0x1400 0x1dc>;

            clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
            resets = <&gcc GCC_PCIE_0_PHY_BCR>;

            #clock-cells = <0>;
            clock-output-names = "pcie_0_pipe_clk_src";

            #phy-cells = <0>;
        };

        pciephy_1: phy@2000 {
            reg = <0x2000 0x130>,
                  <0x2200 0x200>,
                  <0x2400 0x1dc>;

            clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
            resets = <&gcc GCC_PCIE_1_PHY_BCR>;

            #clock-cells = <0>;
            clock-output-names = "pcie_1_pipe_clk_src";

            #phy-cells = <0>;
        };

        pciephy_2: phy@3000 {
            reg = <0x3000 0x130>,
                  <0x3200 0x200>,
                  <0x3400 0x1dc>;

            clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
            resets = <&gcc GCC_PCIE_2_PHY_BCR>;

            #clock-cells = <0>;
            clock-output-names = "pcie_2_pipe_clk_src";

            #phy-cells = <0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm QMP PHY controller (PCIe)

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description:
  QMP PHY controller supports physical layer functionality for a number of
  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.

properties:
  compatible:
    enum:
      - qcom,ipq6018-qmp-pcie-phy
      - qcom,ipq8074-qmp-gen3-pcie-phy
      - qcom,ipq8074-qmp-pcie-phy
      - qcom,msm8998-qmp-pcie-phy
      - qcom,sc8180x-qmp-pcie-phy
      - qcom,sdm845-qhp-pcie-phy
      - qcom,sdm845-qmp-pcie-phy
      - qcom,sdx55-qmp-pcie-phy
      - qcom,sm8250-qmp-gen3x1-pcie-phy
      - qcom,sm8250-qmp-gen3x2-pcie-phy
      - qcom,sm8250-qmp-modem-pcie-phy
      - qcom,sm8450-qmp-gen3x1-pcie-phy
      - qcom,sm8450-qmp-gen4x2-pcie-phy

  reg:
    items:
      - description: serdes

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

  ranges: true

  clocks:
    minItems: 2
    maxItems: 4

  clock-names:
    minItems: 2
    maxItems: 4

  resets:
    minItems: 1
    maxItems: 2

  reset-names:
    minItems: 1
    maxItems: 2

  vdda-phy-supply: true

  vdda-pll-supply: true

  vddp-ref-clk-supply: true

patternProperties:
  "^phy@[0-9a-f]+$":
    type: object
    description: single PHY-provider child node
    properties:
      reg:
        minItems: 3
        maxItems: 6

      clocks:
        items:
          - description: PIPE clock

      clock-names:
        deprecated: true
        items:
          - const: pipe0

      "#clock-cells":
        const: 0

      clock-output-names:
        maxItems: 1

      "#phy-cells":
        const: 0

    required:
      - reg
      - clocks
      - "#clock-cells"
      - clock-output-names
      - "#phy-cells"

    additionalProperties: false

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - clocks
  - clock-names
  - resets
  - reset-names

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8998-qmp-pcie-phy
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          items:
            - const: aux
            - const: cfg_ahb
            - const: ref
        resets:
          maxItems: 2
        reset-names:
          items:
            - const: phy
            - const: common
      required:
        - vdda-phy-supply
        - vdda-pll-supply

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq6018-qmp-pcie-phy
              - qcom,ipq8074-qmp-gen3-pcie-phy
              - qcom,ipq8074-qmp-pcie-phy
    then:
      properties:
        clocks:
          maxItems: 2
        clock-names:
          items:
            - const: aux
            - const: cfg_ahb
        resets:
          maxItems: 2
        reset-names:
          items:
            - const: phy
            - const: common

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc8180x-qmp-pcie-phy
              - qcom,sdm845-qhp-pcie-phy
              - qcom,sdm845-qmp-pcie-phy
              - qcom,sdx55-qmp-pcie-phy
              - qcom,sm8250-qmp-gen3x1-pcie-phy
              - qcom,sm8250-qmp-gen3x2-pcie-phy
              - qcom,sm8250-qmp-modem-pcie-phy
              - qcom,sm8450-qmp-gen3x1-pcie-phy
              - qcom,sm8450-qmp-gen4x2-pcie-phy
    then:
      properties:
        clocks:
          maxItems: 4
        clock-names:
          items:
            - const: aux
            - const: cfg_ahb
            - const: ref
            - const: refgen
        resets:
          maxItems: 1
        reset-names:
          items:
            - const: phy
      required:
        - vdda-phy-supply
        - vdda-pll-supply

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sm8250-qmp-gen3x2-pcie-phy
              - qcom,sm8250-qmp-modem-pcie-phy
              - qcom,sm8450-qmp-gen4x2-pcie-phy
    then:
      patternProperties:
        "^phy@[0-9a-f]+$":
          properties:
            reg:
              items:
                - description: TX lane 1
                - description: RX lane 1
                - description: PCS
                - description: TX lane 2
                - description: RX lane 2
                - description: PCS_MISC

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc8180x-qmp-pcie-phy
              - qcom,sdm845-qmp-pcie-phy
              - qcom,sdx55-qmp-pcie-phy
              - qcom,sm8250-qmp-gen3x1-pcie-phy
              - qcom,sm8450-qmp-gen3x1-pcie-phy
    then:
      patternProperties:
        "^phy@[0-9a-f]+$":
          properties:
            reg:
              items:
                - description: TX
                - description: RX
                - description: PCS
                - description: PCS_MISC

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq6018-qmp-pcie-phy
              - qcom,ipq8074-qmp-pcie-phy
              - qcom,msm8998-qmp-pcie-phy
              - qcom,sdm845-qhp-pcie-phy
    then:
      patternProperties:
        "^phy@[0-9a-f]+$":
          properties:
            reg:
              items:
                - description: TX
                - description: RX
                - description: PCS

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
    phy-wrapper@1c0e000 {
        compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
        reg = <0x01c0e000 0x1c0>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x01c0e000 0x1000>;

        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
                 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
                 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
                 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
        clock-names = "aux", "cfg_ahb", "ref", "refgen";

        resets = <&gcc GCC_PCIE_1_PHY_BCR>;
        reset-names = "phy";

        vdda-phy-supply = <&vreg_l10c_0p88>;
        vdda-pll-supply = <&vreg_l6b_1p2>;

        phy@200 {
            reg = <0x200 0x170>,
                  <0x400 0x200>,
                  <0xa00 0x1f0>,
                  <0x600 0x170>,
                  <0x800 0x200>,
                  <0xe00 0xf4>;

            clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;

            #clock-cells = <0>;
            clock-output-names = "pcie_1_pipe_clk";

            #phy-cells = <0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm QMP PHY controller (UFS)

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description:
  QMP PHY controller supports physical layer functionality for a number of
  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.

properties:
  compatible:
    enum:
      - qcom,msm8996-qmp-ufs-phy
      - qcom,msm8998-qmp-ufs-phy
      - qcom,sc8180x-qmp-ufs-phy
      - qcom,sc8280xp-qmp-ufs-phy
      - qcom,sdm845-qmp-ufs-phy
      - qcom,sm6115-qmp-ufs-phy
      - qcom,sm6350-qmp-ufs-phy
      - qcom,sm8150-qmp-ufs-phy
      - qcom,sm8250-qmp-ufs-phy
      - qcom,sm8350-qmp-ufs-phy
      - qcom,sm8450-qmp-ufs-phy

  reg:
    items:
      - description: serdes

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

  ranges: true

  clocks:
    minItems: 1
    maxItems: 3

  clock-names:
    minItems: 1
    maxItems: 3

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: ufsphy

  vdda-phy-supply: true

  vdda-pll-supply: true

  vddp-ref-clk-supply: true

patternProperties:
  "^phy@[0-9a-f]+$":
    type: object
    description: single PHY-provider child node
    properties:
      reg:
        minItems: 3
        maxItems: 6

      "#phy-cells":
        const: 0

    required:
      - reg
      - "#phy-cells"

    additionalProperties: false

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - clocks
  - clock-names
  - resets
  - reset-names
  - vdda-phy-supply
  - vdda-pll-supply

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8996-qmp-ufs-phy
    then:
      properties:
        clocks:
          maxItems: 1
        clock-names:
          items:
            - const: ref

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8998-qmp-ufs-phy
              - qcom,sc8180x-qmp-ufs-phy
              - qcom,sc8280xp-qmp-ufs-phy
              - qcom,sdm845-qmp-ufs-phy
              - qcom,sm6115-qmp-ufs-phy
              - qcom,sm6350-qmp-ufs-phy
              - qcom,sm8150-qmp-ufs-phy
              - qcom,sm8250-qmp-ufs-phy
    then:
      properties:
        clocks:
          maxItems: 2
        clock-names:
          items:
            - const: ref
            - const: ref_aux

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sm8450-qmp-ufs-phy
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          items:
            - const: ref
            - const: ref_aux
            - const: qref

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8998-qmp-ufs-phy
              - qcom,sc8280xp-qmp-ufs-phy
              - qcom,sdm845-qmp-ufs-phy
              - qcom,sm6350-qmp-ufs-phy
              - qcom,sm8150-qmp-ufs-phy
              - qcom,sm8250-qmp-ufs-phy
              - qcom,sm8350-qmp-ufs-phy
              - qcom,sm8450-qmp-ufs-phy
    then:
      patternProperties:
        "^phy@[0-9a-f]+$":
          properties:
            reg:
              items:
                - description: TX lane 1
                - description: RX lane 1
                - description: PCS
                - description: TX lane 2
                - description: RX lane 2

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc8180x-qmp-ufs-phy
    then:
      patternProperties:
        "^phy@[0-9a-f]+$":
          properties:
            reg:
              items:
                - description: TX
                - description: RX
                - description: PCS
                - description: PCS_MISC

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8996-qmp-ufs-phy
              - qcom,sm6115-qmp-ufs-phy
    then:
      patternProperties:
        "^phy@[0-9a-f]+$":
          properties:
            reg:
              items:
                - description: TX
                - description: RX
                - description: PCS

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    phy-wrapper@1d87000 {
        compatible = "qcom,sc8280xp-qmp-ufs-phy";
        reg = <0x01d87000 0xe10>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x01d87000 0x1000>;

        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
        clock-names = "ref", "ref_aux";

        resets = <&ufs_mem_hc 0>;
        reset-names = "ufsphy";

        vdda-phy-supply = <&vreg_l6b>;
        vdda-pll-supply = <&vreg_l3b>;

        phy@400 {
            reg = <0x400 0x108>,
                  <0x600 0x1e0>,
                  <0xc00 0x1dc>,
                  <0x800 0x108>,
                  <0xa00 0x1e0>;
            #phy-cells = <0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,qmp-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm QMP PHY controller (USB)

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description:
  QMP PHY controller supports physical layer functionality for a number of
  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.

properties:
  compatible:
    enum:
      - qcom,ipq6018-qmp-usb3-phy
      - qcom,ipq8074-qmp-usb3-phy
      - qcom,msm8996-qmp-usb3-phy
      - qcom,msm8998-qmp-usb3-phy
      - qcom,qcm2290-qmp-usb3-phy
      - qcom,sc7180-qmp-usb3-phy
      - qcom,sc8180x-qmp-usb3-phy
      - qcom,sc8280xp-qmp-usb3-uni-phy
      - qcom,sdm845-qmp-usb3-phy
      - qcom,sdm845-qmp-usb3-uni-phy
      - qcom,sdx55-qmp-usb3-uni-phy
      - qcom,sdx65-qmp-usb3-uni-phy
      - qcom,sm8150-qmp-usb3-phy
      - qcom,sm8150-qmp-usb3-uni-phy
      - qcom,sm8250-qmp-usb3-phy
      - qcom,sm8250-qmp-usb3-uni-phy
      - qcom,sm8350-qmp-usb3-phy
      - qcom,sm8350-qmp-usb3-uni-phy
      - qcom,sm8450-qmp-usb3-phy

  reg:
    minItems: 1
    items:
      - description: serdes
      - description: DP_COM

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

  ranges: true

  clocks:
    minItems: 3
    maxItems: 4

  clock-names:
    minItems: 3
    maxItems: 4

  power-domains:
    maxItems: 1

  resets:
    maxItems: 2

  reset-names:
    maxItems: 2

  vdda-phy-supply: true

  vdda-pll-supply: true

  vddp-ref-clk-supply: true

patternProperties:
  "^phy@[0-9a-f]+$":
    type: object
    description: single PHY-provider child node
    properties:
      reg:
        minItems: 3
        maxItems: 6

      clocks:
        items:
          - description: PIPE clock

      clock-names:
        deprecated: true
        items:
          - const: pipe0

      "#clock-cells":
        const: 0

      clock-output-names:
        maxItems: 1

      "#phy-cells":
        const: 0

    required:
      - reg
      - clocks
      - "#clock-cells"
      - clock-output-names
      - "#phy-cells"

    additionalProperties: false

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - clocks
  - clock-names
  - resets
  - reset-names
  - vdda-phy-supply
  - vdda-pll-supply

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc7180-qmp-usb3-phy
    then:
      properties:
        clocks:
          maxItems: 4
        clock-names:
          items:
            - const: aux
            - const: cfg_ahb
            - const: ref
            - const: com_aux
        resets:
          maxItems: 1
        reset-names:
          items:
            - const: phy

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdm845-qmp-usb3-uni-phy
    then:
      properties:
        clocks:
          maxItems: 4
        clock-names:
          items:
            - const: aux
            - const: cfg_ahb
            - const: ref
            - const: com_aux
        resets:
          maxItems: 2
        reset-names:
          items:
            - const: phy
            - const: common

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq8074-qmp-usb3-phy
              - qcom,msm8996-qmp-usb3-phy
              - qcom,msm8998-qmp-usb3-phy
              - qcom,sdx55-qmp-usb3-uni-phy
              - qcom,sdx65-qmp-usb3-uni-phy
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          items:
            - const: aux
            - const: cfg_ahb
            - const: ref
        resets:
          maxItems: 2
        reset-names:
          items:
            - const: phy
            - const: common

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc8280xp-qmp-usb3-uni-phy
              - qcom,sm8150-qmp-usb3-phy
              - qcom,sm8150-qmp-usb3-uni-phy
              - qcom,sm8250-qmp-usb3-uni-phy
              - qcom,sm8350-qmp-usb3-uni-phy
    then:
      properties:
        clocks:
          maxItems: 4
        clock-names:
          items:
            - const: aux
            - const: ref_clk_src
            - const: ref
            - const: com_aux
        resets:
          maxItems: 2
        reset-names:
          items:
            - const: phy
            - const: common

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sm8250-qmp-usb3-phy
              - qcom,sm8350-qmp-usb3-phy
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          items:
            - const: aux
            - const: ref_clk_src
            - const: com_aux
        resets:
          maxItems: 2
        reset-names:
          items:
            - const: phy
            - const: common

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,qcm2290-qmp-usb3-phy
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          items:
            - const: cfg_ahb
            - const: ref
            - const: com_aux
        resets:
          maxItems: 2
        reset-names:
          items:
            - const: phy_phy
            - const: phy

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc8280xp-qmp-usb3-uni-phy
    then:
      required:
        - power-domains

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdm845-qmp-usb3-phy
              - qcom,sm8150-qmp-usb3-phy
              - qcom,sm8350-qmp-usb3-phy
              - qcom,sm8450-qmp-usb3-phy
    then:
      patternProperties:
        "^phy@[0-9a-f]+$":
          properties:
            reg:
              items:
                - description: TX lane 1
                - description: RX lane 1
                - description: PCS
                - description: TX lane 2
                - description: RX lane 2
                - description: PCS_MISC

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8998-qmp-usb3-phy
    then:
      patternProperties:
        "^phy@[0-9a-f]+$":
          properties:
            reg:
              items:
                - description: TX lane 1
                - description: RX lane 1
                - description: PCS
                - description: TX lane 2
                - description: RX lane 2

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq6018-qmp-usb3-phy
              - qcom,ipq8074-qmp-usb3-phy
              - qcom,qcm2290-qmp-usb3-phy
              - qcom,sc7180-qmp-usb3-phy
              - qcom,sc8180x-qmp-usb3-phy
              - qcom,sdx55-qmp-usb3-uni-phy
              - qcom,sdx65-qmp-usb3-uni-phy
              - qcom,sm8150-qmp-usb3-uni-phy
              - qcom,sm8250-qmp-usb3-phy
    then:
      patternProperties:
        "^phy@[0-9a-f]+$":
          properties:
            reg:
              items:
                - description: TX
                - description: RX
                - description: PCS
                - description: PCS_MISC

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8996-qmp-usb3-phy
              - qcom,sc8280xp-qmp-usb3-uni-phy
              - qcom,sm8250-qmp-usb3-uni-phy
              - qcom,sm8350-qmp-usb3-uni-phy
    then:
      patternProperties:
        "^phy@[0-9a-f]+$":
          properties:
            reg:
              items:
                - description: TX
                - description: RX
                - description: PCS

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    usb_2_qmpphy: phy-wrapper@88eb000 {
        compatible = "qcom,sdm845-qmp-usb3-uni-phy";
        reg = <0x088eb000 0x18c>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x088eb000 0x2000>;

        clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
                 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
                 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
        clock-names = "aux", "cfg_ahb", "ref", "com_aux";

        resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
                 <&gcc GCC_USB3_PHY_SEC_BCR>;
        reset-names = "phy", "common";

        vdda-phy-supply = <&vdda_usb2_ss_1p2>;
        vdda-pll-supply = <&vdda_usb2_ss_core>;

        usb_2_ssphy: phy@200 {
                reg = <0x200 0x128>,
                      <0x400 0x1fc>,
                      <0x800 0x218>,
                      <0x600 0x70>;

                clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;

                #clock-cells = <0>;
                clock-output-names = "usb3_uni_phy_pipe_clk_src";

                #phy-cells = <0>;
            };
        };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm QMP USB3 DP PHY controller

maintainers:
  - Wesley Cheng <quic_wcheng@quicinc.com>

properties:
  compatible:
    enum:
      - qcom,sc7180-qmp-usb3-dp-phy
      - qcom,sc7280-qmp-usb3-dp-phy
      - qcom,sc8180x-qmp-usb3-dp-phy
      - qcom,sc8280xp-qmp-usb43dp-phy
      - qcom,sdm845-qmp-usb3-dp-phy
      - qcom,sm8250-qmp-usb3-dp-phy
  reg:
    items:
      - description: Address and length of PHY's USB serdes block.
      - description: Address and length of the DP_COM control block.
      - description: Address and length of PHY's DP serdes block.

  reg-names:
    items:
      - const: usb
      - const: dp_com
      - const: dp

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

  ranges: true

  clocks:
    items:
      - description: Phy aux clock.
      - description: Phy config clock.
      - description: 19.2 MHz ref clk.
      - description: Phy common block aux clock.

  clock-names:
    items:
      - const: aux
      - const: cfg_ahb
      - const: ref
      - const: com_aux

  power-domains:
    maxItems: 1

  resets:
    items:
      - description: reset of phy block.
      - description: phy common block reset.

  reset-names:
    items:
      - const: phy
      - const: common

  vdda-phy-supply:
    description:
      Phandle to a regulator supply to PHY core block.

  vdda-pll-supply:
    description:
      Phandle to 1.8V regulator supply to PHY refclk pll block.

  vddp-ref-clk-supply:
    description:
      Phandle to a regulator supply to any specific refclk pll block.

#Required nodes:
patternProperties:
  "^usb3-phy@[0-9a-f]+$":
    type: object
    additionalProperties: false
    description:
      The USB3 PHY.

    properties:
      reg:
        items:
          - description: Address and length of TX.
          - description: Address and length of RX.
          - description: Address and length of PCS.
          - description: Address and length of TX2.
          - description: Address and length of RX2.
          - description: Address and length of pcs_misc.

      clocks:
        items:
          - description: pipe clock

      clock-names:
        deprecated: true
        items:
          - const: pipe0

      clock-output-names:
        items:
          - const: usb3_phy_pipe_clk_src

      '#clock-cells':
        const: 0

      '#phy-cells':
        const: 0

    required:
      - reg
      - clocks
      - '#clock-cells'
      - '#phy-cells'

  "^dp-phy@[0-9a-f]+$":
    type: object
    additionalProperties: false
    description:
      The DP PHY.

    properties:
      reg:
        items:
          - description: Address and length of TX.
          - description: Address and length of RX.
          - description: Address and length of PCS.
          - description: Address and length of TX2.
          - description: Address and length of RX2.

      '#clock-cells':
        const: 1

      '#phy-cells':
        const: 0

    required:
      - reg
      - '#clock-cells'
      - '#phy-cells'

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - clocks
  - clock-names
  - resets
  - reset-names
  - vdda-phy-supply
  - vdda-pll-supply

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc8280xp-qmp-usb43dp-phy
    then:
      required:
        - power-domains

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    usb_1_qmpphy: phy-wrapper@88e9000 {
        compatible = "qcom,sdm845-qmp-usb3-dp-phy";
        reg = <0x088e9000 0x18c>,
              <0x088e8000 0x10>,
              <0x088ea000 0x40>;
        reg-names = "usb", "dp_com", "dp";
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x088e9000 0x2000>;

        clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
                 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
                 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
        clock-names = "aux", "cfg_ahb", "ref", "com_aux";

        resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
                 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
        reset-names = "phy", "common";

        vdda-phy-supply = <&vdda_usb2_ss_1p2>;
        vdda-pll-supply = <&vdda_usb2_ss_core>;

        usb3-phy@200 {
            reg = <0x200 0x128>,
                  <0x400 0x200>,
                  <0xc00 0x218>,
                  <0x600 0x128>,
                  <0x800 0x200>,
                  <0xa00 0x100>;
            #clock-cells = <0>;
            #phy-cells = <0>;
            clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
            clock-output-names = "usb3_phy_pipe_clk_src";
        };

        dp-phy@88ea200 {
            reg = <0xa200 0x200>,
                  <0xa400 0x200>,
                  <0xaa00 0x200>,
                  <0xa600 0x200>,
                  <0xa800 0x200>;
            #clock-cells = <1>;
            #phy-cells = <0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm QUSB2 phy controller

maintainers:
  - Wesley Cheng <quic_wcheng@quicinc.com>

description:
  QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - qcom,ipq8074-qusb2-phy
              - qcom,msm8953-qusb2-phy
              - qcom,msm8996-qusb2-phy
              - qcom,msm8998-qusb2-phy
              - qcom,qcm2290-qusb2-phy
              - qcom,sdm660-qusb2-phy
              - qcom,ipq6018-qusb2-phy
              - qcom,sm4250-qusb2-phy
              - qcom,sm6115-qusb2-phy
      - items:
          - enum:
              - qcom,sc7180-qusb2-phy
              - qcom,sdm670-qusb2-phy
              - qcom,sdm845-qusb2-phy
              - qcom,sm6350-qusb2-phy
          - const: qcom,qusb2-v2-phy
  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  clocks:
    minItems: 2
    items:
      - description: phy config clock
      - description: 19.2 MHz ref clk
      - description: phy interface clock (Optional)

  clock-names:
    minItems: 2
    items:
      - const: cfg_ahb
      - const: ref
      - const: iface

  vdd-supply:
    description:
      Phandle to 0.9V regulator supply to PHY digital circuit.

  vdda-pll-supply:
    description:
      Phandle to 1.8V regulator supply to PHY refclk pll block.

  vdda-phy-dpdm-supply:
    description:
      Phandle to 3.1V regulator supply to Dp/Dm port signals.

  resets:
    maxItems: 1
    description:
      Phandle to reset to phy block.

  nvmem-cells:
    maxItems: 1
    description:
      Phandle to nvmem cell that contains 'HS Tx trim'
      tuning parameter value for qusb2 phy.

  qcom,tcsr-syscon:
    description:
      Phandle to TCSR syscon register region.
    $ref: /schemas/types.yaml#/definitions/phandle

if:
  properties:
    compatible:
      contains:
        const: qcom,qusb2-v2-phy
then:
  properties:
    qcom,imp-res-offset-value:
      description:
        It is a 6 bit value that specifies offset to be
        added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
        tuning parameter that may vary for different boards of same SOC.
      $ref: /schemas/types.yaml#/definitions/uint32
      minimum: 0
      maximum: 63
      default: 0

    qcom,bias-ctrl-value:
      description:
        It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
        tuning parameter that may vary for different boards of same SOC.
      $ref: /schemas/types.yaml#/definitions/uint32
      minimum: 0
      maximum: 63
      default: 32

    qcom,charge-ctrl-value:
      description:
        It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
        tuning parameter that may vary for different boards of same SOC.
      $ref: /schemas/types.yaml#/definitions/uint32
      minimum: 0
      maximum: 3
      default: 0

    qcom,hstx-trim-value:
      description:
        It is a 4 bit value that specifies tuning for HSTX
        output current.
        Possible range is - 15mA to 24mA (stepsize of 600 uA).
        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
      $ref: /schemas/types.yaml#/definitions/uint32
      minimum: 0
      maximum: 15
      default: 3

    qcom,preemphasis-level:
      description:
        It is a 2 bit value that specifies pre-emphasis level.
        Possible range is 0 to 15% (stepsize of 5%).
        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
      $ref: /schemas/types.yaml#/definitions/uint32
      minimum: 0
      maximum: 3
      default: 2

    qcom,preemphasis-width:
      description:
        It is a 1 bit value that specifies how long the HSTX
        pre-emphasis (specified using qcom,preemphasis-level) must be in
        effect. Duration could be half-bit of full-bit.
        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
      $ref: /schemas/types.yaml#/definitions/uint32
      minimum: 0
      maximum: 1
      default: 0

    qcom,hsdisc-trim-value:
      description:
        It is a 2 bit value tuning parameter that control disconnect
        threshold and may vary for different boards of same SOC.
      $ref: /schemas/types.yaml#/definitions/uint32
      minimum: 0
      maximum: 3
      default: 0

required:
  - compatible
  - reg
  - "#phy-cells"
  - clocks
  - clock-names
  - vdd-supply
  - vdda-pll-supply
  - vdda-phy-dpdm-supply
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
    hsusb_phy: phy@7411000 {
        compatible = "qcom,msm8996-qusb2-phy";
        reg = <0x7411000 0x180>;
        #phy-cells = <0>;

        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
        clock-names = "cfg_ahb", "ref";

        vdd-supply = <&pm8994_l28>;
        vdda-pll-supply = <&pm8994_l12>;
        vdda-phy-dpdm-supply = <&pm8994_l24>;

        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
        nvmem-cells = <&qusb2p_hstx_trim>;
    };


code:
Qualcomm's APQ8016/MSM8916 USB transceiver controller

- compatible:
    Usage: required
    Value type: <string>
    Definition: Should contain "qcom,usb-8x16-phy".

- reg:
    Usage: required
    Value type: <prop-encoded-array>
    Definition: USB PHY base address and length of the register map

- clocks:
    Usage: required
    Value type: <prop-encoded-array>
    Definition: See clock-bindings.txt section "consumers". List of
                two clock specifiers for interface and core controller
                clocks.

- clock-names:
    Usage: required
    Value type: <string>
    Definition: Must contain "iface" and "core" strings.

- vddcx-supply:
    Usage: required
    Value type: <phandle>
    Definition: phandle to the regulator VDCCX supply node.

- v1p8-supply:
    Usage: required
    Value type: <phandle>
    Definition: phandle to the regulator 1.8V supply node.

- v3p3-supply:
    Usage: required
    Value type: <phandle>
    Definition: phandle to the regulator 3.3V supply node.

- resets:
    Usage: required
    Value type: <prop-encoded-array>
    Definition: See reset.txt section "consumers". PHY reset specifier.

- reset-names:
    Usage: required
    Value type: <string>
    Definition: Must contain "phy" string.

- switch-gpio:
    Usage: optional
    Value type: <prop-encoded-array>
    Definition: Some boards are using Dual SPDT USB Switch, witch is
                controlled by GPIO to de/multiplex D+/D- USB lines
                between connectors.

Example:
	usb_phy: phy@78d9000 {
		compatible = "qcom,usb-8x16-phy";
		reg = <0x78d9000 0x400>;

		vddcx-supply = <&pm8916_s1_corner>;
		v1p8-supply = <&pm8916_l7>;
		v3p3-supply = <&pm8916_l13>;

		clocks = <&gcc GCC_USB_HS_AHB_CLK>,
			     <&gcc GCC_USB_HS_SYSTEM_CLK>;
		clock-names = "iface", "core";

		resets = <&gcc GCC_USB2A_PHY_BCR>;
		reset-names = "phy";

		// D+/D- lines: 1 - Routed to HUB, 0 - Device connector
		switch-gpio = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY

maintainers:
  - Bryan O'Donoghue <bryan.odonoghue@linaro.org>

description: |
  Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY

properties:
  compatible:
    enum:
      - qcom,usb-hs-28nm-femtophy
      - qcom,usb-hs-28nm-mdm9607

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  clocks:
    items:
      - description: rpmcc ref clock
      - description: PHY AHB clock
      - description: Rentention clock

  clock-names:
    items:
      - const: ref
      - const: ahb
      - const: sleep

  resets:
    items:
      - description: PHY core reset
      - description: POR reset

  reset-names:
    items:
      - const: phy
      - const: por

  vdd-supply:
    description: phandle to the regulator VDD supply node.

  vdda1p8-supply:
    description: phandle to the regulator 1.8V supply node.

  vdda3p3-supply:
    description: phandle to the regulator 3.3V supply node.

required:
  - compatible
  - reg
  - "#phy-cells"
  - clocks
  - clock-names
  - resets
  - reset-names
  - vdd-supply
  - vdda1p8-supply
  - vdda3p3-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
    #include <dt-bindings/clock/qcom,rpmcc.h>
    usb2_phy_prim: phy@7a000 {
        compatible = "qcom,usb-hs-28nm-femtophy";
        reg = <0x0007a000 0x200>;
        #phy-cells = <0>;
        clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
                 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
                 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
        clock-names = "ref", "ahb", "sleep";
        resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
                 <&gcc GCC_USB2A_PHY_BCR>;
        reset-names = "phy", "por";
        vdd-supply = <&vreg_l4_1p2>;
        vdda1p8-supply = <&vreg_l5_1p8>;
        vdda3p3-supply = <&vreg_l12_3p3>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm's USB HS PHY binding description

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

if:
  properties:
    compatible:
      contains:
        const: qcom,usb-hs-phy-apq8064
then:
  properties:
    resets:
      maxItems: 1

    reset-names:
      const: por

else:
  properties:
    resets:
      minItems: 2
      maxItems: 2

    reset-names:
      items:
        - const: phy
        - const: por

properties:
  compatible:
    items:
      - enum:
          - qcom,usb-hs-phy-apq8064
          - qcom,usb-hs-phy-msm8226
          - qcom,usb-hs-phy-msm8916
          - qcom,usb-hs-phy-msm8974
      - const: qcom,usb-hs-phy

  clocks:
    minItems: 2
    maxItems: 2

  clock-names:
    maxItems: 2
    contains:
      items:
        - const: ref
        - const: sleep

  resets: true

  reset-names: true

  v1p8-supply: true

  v3p3-supply: true

  extcon: true

  "#phy-cells":
    const: 0

  qcom,init-seq:
    $ref: /schemas/types.yaml#/definitions/uint8-matrix
    description: >
      Sequence of ULPI address and value pairs to
      program into the ULPI_EXT_VENDOR_SPECIFIC area.
      This is related to Device Mode Eye Diagram test.
    maxItems: 32 # no hard limit
    items:
      items:
        - description: >
            the address is offset from the ULPI_EXT_VENDOR_SPECIFIC address
        - description: value

required:
  - clocks
  - clock-names
  - resets
  - reset-names
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    otg: usb-controller {
      #reset-cells = <1>;

      ulpi {
        phy {
          compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy";
          #phy-cells = <0>;
          clocks = <&clk 0>, <&clk 258>;
          clock-names = "ref", "sleep";
          resets = <&gcc 10>, <&otg 0>;
          reset-names = "phy", "por";
          v3p3-supply = <&pm8941_l24>;
          v1p8-supply = <&pm8941_l6>;
          extcon = <&smbb>;
          qcom,init-seq = /bits/ 8 <0x1 0x63>;
        };
      };
    };


code:
Qualcomm's USB HSIC PHY

PROPERTIES

- compatible:
    Usage: required
    Value type: <string>
    Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the
		following:

			"qcom,usb-hsic-phy-mdm9615"
			"qcom,usb-hsic-phy-msm8974"

- #phy-cells:
    Usage: required
    Value type: <u32>
    Definition: Should contain 0

- clocks:
    Usage: required
    Value type: <prop-encoded-array>
    Definition: Should contain clock specifier for phy, calibration and
                a calibration sleep clock

- clock-names:
    Usage: required
    Value type: <stringlist>
    Definition: Should contain "phy, "cal" and "cal_sleep"

- pinctrl-names:
    Usage: required
    Value type: <stringlist>
    Definition: Should contain "init" and "default" in that order

- pinctrl-0:
    Usage: required
    Value type: <prop-encoded-array>
    Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch
                free state

- pinctrl-1:
    Usage: required
    Value type: <prop-encoded-array>
    Definition: List of pinctrl settings to apply to mux out the HSIC pins

EXAMPLE

usb-controller {
	ulpi {
		phy {
			compatible = "qcom,usb-hsic-phy-msm8974",
				     "qcom,usb-hsic-phy";
			#phy-cells = <0>;
			pinctrl-names = "init", "default";
			pinctrl-0 = <&hsic_sleep>;
			pinctrl-1 = <&hsic_default>;
			clocks = <&gcc GCC_USB_HSIC_CLK>,
				 <&gcc GCC_USB_HSIC_IO_CAL_CLK>,
				 <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;
			clock-names = "phy", "cal", "cal_sleep";
			assigned-clocks = <&gcc GCC_USB_HSIC_IO_CAL_CLK>;
			assigned-clock-rates = <960000>;
		};
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Synopsys Femto High-Speed USB PHY V2

maintainers:
  - Wesley Cheng <quic_wcheng@quicinc.com>

description: |
  Qualcomm High-Speed USB PHY

properties:
  compatible:
    enum:
      - qcom,usb-snps-hs-5nm-phy
      - qcom,usb-snps-hs-7nm-phy
      - qcom,sc7280-usb-hs-phy
      - qcom,sc8180x-usb-hs-phy
      - qcom,sc8280xp-usb-hs-phy
      - qcom,sm6375-usb-hs-phy
      - qcom,sm8150-usb-hs-phy
      - qcom,sm8250-usb-hs-phy
      - qcom,sm8350-usb-hs-phy
      - qcom,sm8450-usb-hs-phy
      - qcom,usb-snps-femto-v2-phy

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  clocks:
    items:
      - description: rpmhcc ref clock

  clock-names:
    items:
      - const: ref

  resets:
    items:
      - description: PHY core reset

  vdda-pll-supply:
    description: phandle to the regulator VDD supply node.

  vdda18-supply:
    description: phandle to the regulator 1.8V supply node.

  vdda33-supply:
    description: phandle to the regulator 3.3V supply node.

  qcom,hs-disconnect-bp:
    description:
      This adjusts the voltage level for the threshold used to
      detect a disconnect event at the host.
      The hardware accepts only discrete values. The value closest to the
      provided input will be chosen as the override value for this param.
    minimum: -272
    maximum: 2156

  qcom,squelch-detector-bp:
    description:
      This adjusts the voltage level for the threshold used to
      detect valid high-speed data.
      The hardware accepts only discrete values. The value closest to the
      provided input will be chosen as the override value for this param.
    minimum: -2090
    maximum: 1590

  qcom,hs-amplitude-bp:
    description:
      This adjusts the high-speed DC level voltage.
      The hardware accepts only discrete values. The value closest to the
      provided input will be chosen as the override value for this param.
    minimum: -660
    maximum: 2670

  qcom,pre-emphasis-duration-bp:
    description:
      This signal controls the duration for which the
      HS pre-emphasis current is sourced onto DP<#> or DM<#>.
      The HS Transmitter pre-emphasis duration is defined in terms of
      unit amounts. One unit of pre-emphasis duration is approximately
      650 ps and is defined as 1X pre-emphasis duration.
      The hardware accepts only discrete values. The value closest to the
      provided input will be chosen as the override value for this param.
    minimum: 10000
    maximum: 20000

  qcom,pre-emphasis-amplitude-bp:
    description:
      This signal controls the amount of current sourced to
      DP<#> and DM<#> after a J-to-K or K-to-J transition.
      The HS Transmitter pre-emphasis current is defined in terms of unit
      amounts. One unit amount is approximately 2 mA and is defined as
      1X pre-emphasis current.
      The hardware accepts only discrete values. The value closest to the
      provided input will be chosen as the override value for this param.
    minimum: 10000
    maximum: 40000

  qcom,hs-rise-fall-time-bp:
    description:
      This adjusts the rise/fall times of the high-speed waveform.
      The hardware accepts only discrete values. The value closest to the
      provided input will be chosen as the override value for this param.
    minimum: -4100
    maximum: 5430

  qcom,hs-crossover-voltage-microvolt:
    description:
      This adjusts the voltage at which the DP<#> and DM<#>
      signals cross while transmitting in HS mode.
      The hardware accepts only discrete values. The value closest to the
      provided input will be chosen as the override value for this param.
    minimum: -31000
    maximum: 28000

  qcom,hs-output-impedance-micro-ohms:
    description:
      In some applications, there can be significant series resistance
      on the D+ and D- paths between the transceiver and cable. This adjusts
      the driver source impedance to compensate for added series
      resistance on the USB. The hardware accepts only discrete values. The
      value closest to the provided input will be chosen as the override value
      for this param.
    minimum: -2300000
    maximum: 6100000

  qcom,ls-fs-output-impedance-bp:
    description:
      This adjusts the low- and full-speed single-ended source
      impedance while driving high. The following adjustment values are based
      on nominal process, voltage, and temperature.
      The hardware accepts only discrete values. The value closest to the
      provided input will be chosen as the override value for this param.
    minimum: -1053
    maximum: 1310

required:
  - compatible
  - reg
  - "#phy-cells"
  - clocks
  - clock-names
  - resets
  - vdda-pll-supply
  - vdda18-supply
  - vdda33-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,gcc-sm8150.h>
    phy@88e2000 {
        compatible = "qcom,sm8150-usb-hs-phy";
        reg = <0x088e2000 0x400>;
        #phy-cells = <0>;

        clocks = <&rpmhcc RPMH_CXO_CLK>;
        clock-names = "ref";

        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

        vdda-pll-supply = <&vdd_usb_hs_core>;
        vdda33-supply = <&vdda_usb_hs_3p1>;
        vdda18-supply = <&vdda_usb_hs_1p8>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY

maintainers:
  - Bryan O'Donoghue <bryan.odonoghue@linaro.org>

description: |
  Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY

properties:
  compatible:
    enum:
      - qcom,usb-ss-28nm-phy

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  clocks:
    items:
      - description: rpmcc clock
      - description: PHY AHB clock
      - description: SuperSpeed pipe clock

  clock-names:
    items:
      - const: ref
      - const: ahb
      - const: pipe

  vdd-supply:
    description: phandle to the regulator VDD supply node.

  vdda1p8-supply:
    description: phandle to the regulator 1.8V supply node.

  resets:
    items:
      - description: COM reset
      - description: PHY reset line

  reset-names:
    items:
      - const: com
      - const: phy

required:
  - compatible
  - reg
  - "#phy-cells"
  - clocks
  - clock-names
  - vdd-supply
  - vdda1p8-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
    #include <dt-bindings/clock/qcom,rpmcc.h>
    usb3_phy: usb3-phy@78000 {
        compatible = "qcom,usb-ss-28nm-phy";
        reg = <0x78000 0x400>;
        #phy-cells = <0>;
        clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
                 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
                 <&gcc GCC_USB3_PHY_PIPE_CLK>;
        clock-names = "ref", "ahb", "pipe";
        resets = <&gcc GCC_USB3_PHY_BCR>,
                 <&gcc GCC_USB3PHY_PHY_BCR>;
        reset-names = "com", "phy";
        vdd-supply = <&vreg_l3_1p05>;
        vdda1p8-supply = <&vreg_l5_1p8>;
    };
...


code:
Qualcomm APQ8064 SATA PHY Controller
------------------------------------

SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
Each SATA PHY controller should have its own node.

Required properties:
- compatible: compatible list, contains "qcom,apq8064-sata-phy".
- reg: offset and length of the SATA PHY register set;
- #phy-cells: must be zero
- clocks: a list of phandles and clock-specifier pairs, one for each entry in
  clock-names.
- clock-names: must be "cfg" for phy config clock.

Example:
	sata_phy: sata-phy@1b400000 {
		compatible = "qcom,apq8064-sata-phy";
		reg = <0x1b400000 0x200>;

		clocks = <&gcc SATA_PHY_CFG_CLK>;
		clock-names = "cfg";

		#phy-cells = <0>;
	};


code:
Qualcomm IPQ806x SATA PHY Controller
------------------------------------

SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
Each SATA PHY controller should have its own node.

Required properties:
- compatible: compatible list, contains "qcom,ipq806x-sata-phy"
- reg: offset and length of the SATA PHY register set;
- #phy-cells: must be zero
- clocks: must be exactly one entry
- clock-names: must be "cfg"

Example:
	sata_phy: sata-phy@1b400000 {
		compatible = "qcom,ipq806x-sata-phy";
		reg = <0x1b400000 0x200>;

		clocks = <&gcc SATA_PHY_CFG_CLK>;
		clock-names = "cfg";

		#phy-cells = <0>;
	};


code:
Qualcomm PCIe2 PHY controller
=============================

The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
platforms.

Required properties:
 - compatible: compatible list, should be:
	       "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"

 - reg: offset and length of the PHY register set.
 - #phy-cells: must be 0.

 - clocks: a clock-specifier pair for the "pipe" clock

 - vdda-vp-supply: phandle to low voltage regulator
 - vdda-vph-supply: phandle to high voltage regulator

 - resets: reset-specifier pairs for the "phy" and "pipe" resets
 - reset-names: list of resets, should contain:
		"phy" and "pipe"

 - clock-output-names: name of the outgoing clock signal from the PHY PLL
 - #clock-cells: must be 0

Example:
 phy@7786000 {
	compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
	reg = <0x07786000 0xb8>;

	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
	resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
	         <&gcc GCC_PCIE_0_PIPE_ARES>;
	reset-names = "phy", "pipe";

	vdda-vp-supply = <&vreg_l3_1p05>;
	vdda-vph-supply = <&vreg_l5_1p8>;

	clock-output-names = "pcie_0_pipe_clk";
	#clock-cells = <0>;
	#phy-cells = <0>;
 };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcom IPQ40xx Dakota HS/SS USB PHY

maintainers:
  - Robert Marko <robert.marko@sartura.hr>

properties:
  compatible:
    enum:
      - qcom,usb-ss-ipq4019-phy
      - qcom,usb-hs-ipq4019-phy

  reg:
    maxItems: 1

  resets:
    maxItems: 2

  reset-names:
    items:
      - const: por_rst
      - const: srif_rst

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - resets
  - reset-names
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-ipq4019.h>

    hsphy@a8000 {
      #phy-cells = <0>;
      compatible = "qcom,usb-hs-ipq4019-phy";
      reg = <0xa8000 0x40>;
      resets = <&gcc USB2_HSPHY_POR_ARES>,
               <&gcc USB2_HSPHY_S_ARES>;
      reset-names = "por_rst", "srif_rst";
    };


code:
Mediatek/Ralink USB PHY

Required properties:
 - compatible: "ralink,rt3352-usbphy"
	       "mediatek,mt7620-usbphy"
	       "mediatek,mt7628-usbphy"
 - reg: required for "mediatek,mt7628-usbphy", unused otherwise
 - #phy-cells: should be 0
 - ralink,sysctl: a phandle to a ralink syscon register region
 - resets: the two reset controllers for host and device
 - reset-names: the names of the 2 reset controllers

Example:

usbphy: phy {
	compatible = "mediatek,mt7628-usbphy";
	reg = <0x10120000 0x1000>;
	#phy-cells = <0>;

	ralink,sysctl = <&sysc>;
	resets = <&rstctrl 22 &rstctrl 25>;
	reset-names = "host", "device";
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car Gen2 USB PHY

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

properties:
  compatible:
    items:
      - enum:
          - renesas,usb-phy-r8a7742      # RZ/G1H
          - renesas,usb-phy-r8a7743      # RZ/G1M
          - renesas,usb-phy-r8a7744      # RZ/G1N
          - renesas,usb-phy-r8a7745      # RZ/G1E
          - renesas,usb-phy-r8a77470     # RZ/G1C
          - renesas,usb-phy-r8a7790      # R-Car H2
          - renesas,usb-phy-r8a7791      # R-Car M2-W
          - renesas,usb-phy-r8a7794      # R-Car E2
      - const: renesas,rcar-gen2-usb-phy # R-Car Gen2 or RZ/G1

  reg:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: usbhs

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

patternProperties:
  "^usb-phy@[02]$":
    type: object
    description: Subnode corresponding to a USB channel.

    properties:
      reg:
        description: FIXME RZ/G1C supports channel 0 only
        enum: [0, 2]

      '#phy-cells':
        description: |
          The phandle's argument in the PHY specifier is the USB controller
          selector for the USB channel.
          For RZ/G1C:
            - 0 for EHCI/OHCI
            - 1 for HS-USB
          For all other SoCS:
            - 0 for PCI EHCI/OHCI
            - 1 for HS-USB (channel 0) or xHCI (channel 2)
        const: 1

    required:
      - reg
      - '#phy-cells'

    additionalProperties: false

required:
  - compatible
  - reg
  - '#address-cells'
  - '#size-cells'
  - clocks
  - clock-names
  - resets
  - power-domains
  - usb-phy@0

if:
  properties:
    compatible:
      contains:
        const: renesas,usb-phy-r8a77470
then:
  properties:
    usb-phy@2: false
else:
  required:
    - usb-phy@2

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/power/r8a7790-sysc.h>
    usb-phy-controller@e6590100 {
        compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy";
        reg = <0xe6590100 0x100>;
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&cpg CPG_MOD 704>;
        clock-names = "usbhs";
        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
        resets = <&cpg 704>;

        usb0: usb-phy@0 {
            reg = <0>;
            #phy-cells = <1>;
        };
        usb2: usb-phy@2 {
            reg = <2>;
            #phy-cells = <1>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/renesas,rcar-gen3-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car Generation 3 PCIe PHY

maintainers:
  - Sergei Shtylyov <sergei.shtylyov@gmail.com>

properties:
  compatible:
    const: renesas,r8a77980-pcie-phy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  '#phy-cells':
    const: 0

required:
  - compatible
  - reg
  - clocks
  - power-domains
  - resets
  - '#phy-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
    #include <dt-bindings/power/r8a77980-sysc.h>

    pcie-phy@e65d0000 {
            compatible = "renesas,r8a77980-pcie-phy";
            reg = <0xe65d0000 0x8000>;
            #phy-cells = <0>;
            clocks = <&cpg CPG_MOD 319>;
            power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
            resets = <&cpg 319>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car generation 3 USB 2.0 PHY

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

properties:
  compatible:
    oneOf:
      - items:
          - const: renesas,usb2-phy-r8a77470 # RZ/G1C

      - items:
          - enum:
              - renesas,usb2-phy-r7s9210  # RZ/A2
              - renesas,usb2-phy-r8a774a1 # RZ/G2M
              - renesas,usb2-phy-r8a774b1 # RZ/G2N
              - renesas,usb2-phy-r8a774c0 # RZ/G2E
              - renesas,usb2-phy-r8a774e1 # RZ/G2H
              - renesas,usb2-phy-r8a7795  # R-Car H3
              - renesas,usb2-phy-r8a7796  # R-Car M3-W
              - renesas,usb2-phy-r8a77961 # R-Car M3-W+
              - renesas,usb2-phy-r8a77965 # R-Car M3-N
              - renesas,usb2-phy-r8a77990 # R-Car E3
              - renesas,usb2-phy-r8a77995 # R-Car D3
          - const: renesas,rcar-gen3-usb2-phy

      - items:
          - enum:
              - renesas,usb2-phy-r9a07g043 # RZ/G2UL
              - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
              - renesas,usb2-phy-r9a07g054 # RZ/V2L
          - const: renesas,rzg2l-usb2-phy

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: fck
      - const: usb_x1

  '#phy-cells':
    enum: [0, 1]  # and 0 is deprecated.
    description: |
      The phandle's argument in the PHY specifier is the INT_STATUS bit of
      controller.
      - 1 = USBH_INTA (OHCI)
      - 2 = USBH_INTB (EHCI)
      - 3 = UCOM_INT (OTG and BC)

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    minItems: 1
    items:
      - description: reset of USB 2.0 host side
      - description: reset of USB 2.0 peripheral side

  vbus-supply:
    description: |
      Phandle to a regulator that provides power to the VBUS. This regulator
      will be managed during the PHY power on/off sequence.

  renesas,no-otg-pins:
    $ref: /schemas/types.yaml#/definitions/flag
    description: |
      specify when a board does not provide proper otg pins.

  dr_mode: true

if:
  properties:
    compatible:
      contains:
        const: renesas,usb2-phy-r7s9210
then:
  required:
    - clock-names

required:
  - compatible
  - reg
  - clocks
  - '#phy-cells'

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: renesas,rzg2l-usb2-phy
    then:
      required:
        - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    usb-phy@ee080200 {
        compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
        reg = <0xee080200 0x700>;
        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD 703>;
        #phy-cells = <1>;
    };

    usb-phy@ee0a0200 {
        compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
        reg = <0xee0a0200 0x700>;
        clocks = <&cpg CPG_MOD 702>;
        #phy-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car generation 3 USB 3.0 PHY

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

properties:
  compatible:
    items:
      - enum:
          - renesas,r8a774a1-usb3-phy # RZ/G2M
          - renesas,r8a774b1-usb3-phy # RZ/G2N
          - renesas,r8a774e1-usb3-phy # RZ/G2H
          - renesas,r8a7795-usb3-phy  # R-Car H3
          - renesas,r8a7796-usb3-phy  # R-Car M3-W
          - renesas,r8a77961-usb3-phy # R-Car M3-W+
          - renesas,r8a77965-usb3-phy # R-Car M3-N
      - const: renesas,rcar-gen3-usb3-phy

  reg:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 3

  clock-names:
    # If you want to use the ssc, the clock-frequency of usb_extal
    # must not be 0.
    minItems: 2
    items:
      - const: usb3-if # The functional clock
      - const: usb3s_clk # The usb3's external clock
      - const: usb_extal # The usb2's external clock

  '#phy-cells':
    # see phy-bindings.txt in the same directory
    const: 0

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  renesas,ssc-range:
    description: |
      Enable/disable spread spectrum clock (ssc). 0 or the property doesn't
      exist means disabling the ssc. The actual value will be -<value> ppm.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 0, 4003, 4492, 4980 ]

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#phy-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    usb-phy@e65ee000 {
        compatible = "renesas,r8a7795-usb3-phy", "renesas,rcar-gen3-usb3-phy";
        reg = <0xe65ee000 0x90>;
        clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, <&usb_extal>;
        clock-names = "usb3-if", "usb3s_clk", "usb_extal";
        #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip PCIe v3 phy

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    enum:
      - rockchip,rk3568-pcie3-phy

  reg:
    maxItems: 1

  clocks:
    minItems: 3
    maxItems: 3

  clock-names:
    items:
      - const: refclk_m
      - const: refclk_n
      - const: pclk

  data-lanes:
    description: which lanes (by position) should be mapped to which
      controller (value). 0 means lane disabled, higher value means used.
      (controller-number +1 )
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 2
    maxItems: 16
    items:
      minimum: 0
      maximum: 16

  "#phy-cells":
    const: 0

  resets:
    maxItems: 1

  reset-names:
    const: phy

  rockchip,phy-grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle to the syscon managing the phy "general register files"

  rockchip,pipe-grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle to the syscon managing the pipe "general register files"

required:
  - compatible
  - reg
  - rockchip,phy-grf
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3568-cru.h>
    pcie30phy: phy@fe8c0000 {
      compatible = "rockchip,rk3568-pcie3-phy";
      reg = <0xfe8c0000 0x20000>;
      #phy-cells = <0>;
      clocks = <&pmucru CLK_PCIE30PHY_REF_M>,
               <&pmucru CLK_PCIE30PHY_REF_N>,
               <&cru PCLK_PCIE30PHY>;
      clock-names = "refclk_m", "refclk_n", "pclk";
      resets = <&cru SRST_PCIE30PHY>;
      reset-names = "phy";
      rockchip,phy-grf = <&pcie30_phy_grf>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip MIPI DPHY with additional LVDS/TTL modes

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  "#phy-cells":
    const: 0

  compatible:
    enum:
      - rockchip,px30-dsi-dphy
      - rockchip,rk3128-dsi-dphy
      - rockchip,rk3368-dsi-dphy
      - rockchip,rk3568-dsi-dphy

  reg:
    maxItems: 1

  clocks:
    items:
      - description: PLL reference clock
      - description: Module clock

  clock-names:
    items:
      - const: ref
      - const: pclk

  power-domains:
    maxItems: 1
    description: phandle to the associated power domain

  resets:
    items:
      - description: exclusive PHY reset line

  reset-names:
    items:
      - const: apb

required:
  - "#phy-cells"
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    dsi_dphy: phy@ff2e0000 {
        compatible = "rockchip,px30-dsi-dphy";
        reg = <0xff2e0000 0x10000>;
        clocks = <&pmucru 13>, <&cru 12>;
        clock-names = "ref", "pclk";
        resets = <&cru 12>;
        reset-names = "apb";
        #phy-cells = <0>;
    };

...


code:
Rockchip specific extensions to the Analogix Display Port PHY
------------------------------------

Required properties:
- compatible : should be one of the following supported values:
	 - "rockchip.rk3288-dp-phy"
- clocks: from common clock binding: handle to dp clock.
	of memory mapped region.
- clock-names: from common clock binding:
	Required elements: "24m"
- #phy-cells : from the generic PHY bindings, must be 0;

Example:

grf: syscon@ff770000 {
	compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";

...

	edp_phy: edp-phy {
		compatible = "rockchip,rk3288-dp-phy";
		clocks = <&cru SCLK_EDP_24M>;
		clock-names = "24m";
		#phy-cells = <0>;
	};
};


code:
Rockchip EMMC PHY
-----------------------

Required properties:
 - compatible: rockchip,rk3399-emmc-phy
 - #phy-cells: must be 0
 - reg: PHY register address offset and length in "general
   register files"

Optional properties:
 - clock-names: Should contain "emmcclk".  Although this is listed as optional
		(because most boards can get basic functionality without having
		access to it), it is strongly suggested.
		See ../clock/clock-bindings.txt for details.
 - clocks: Should have a phandle to the card clock exported by the SDHCI driver.
 - drive-impedance-ohm: Specifies the drive impedance in Ohm.
                        Possible values are 33, 40, 50, 66 and 100.
                        If not set, the default value of 50 will be applied.
 - rockchip,enable-strobe-pulldown: Enable internal pull-down for the strobe
                                    line.  If not set, pull-down is not used.
 - rockchip,output-tapdelay-select: Specifies the phyctrl_otapdlysec register.
                                    If not set, the register defaults to 0x4.
                                    Maximum value 0xf.

Example:

grf: syscon@ff770000 {
	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;

...

	emmcphy: phy@f780 {
		compatible = "rockchip,rk3399-emmc-phy";
		reg = <0xf780 0x20>;
		clocks = <&sdhci>;
		clock-names = "emmcclk";
		drive-impedance-ohm = <50>;
		#phy-cells = <0>;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip SoC MIPI RX0 D-PHY

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP wich
  connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.

properties:
  compatible:
    enum:
      - rockchip,px30-csi-dphy
      - rockchip,rk1808-csi-dphy
      - rockchip,rk3326-csi-dphy
      - rockchip,rk3368-csi-dphy
      - rockchip,rk3568-csi-dphy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: pclk

  '#phy-cells':
    const: 0

  power-domains:
    description: Video in/out power domain.
    maxItems: 1

  resets:
    items:
      - description: exclusive PHY reset line

  reset-names:
    items:
      - const: apb

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Some additional phy settings are access through GRF regs.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#phy-cells'
  - power-domains
  - resets
  - reset-names
  - rockchip,grf

additionalProperties: false

examples:
  - |

    csi_dphy: phy@ff2f0000 {
        compatible = "rockchip,px30-csi-dphy";
        reg = <0xff2f0000 0x4000>;
        clocks = <&cru 1>;
        clock-names = "pclk";
        #phy-cells = <0>;
        power-domains = <&power 1>;
        resets = <&cru 1>;
        reset-names = "apb";
        rockchip,grf = <&grf>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip SoC MIPI RX0 D-PHY

maintainers:
  - Helen Koike <helen.koike@collabora.com>
  - Ezequiel Garcia <ezequiel@collabora.com>

description: |
  The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
  the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.

properties:
  compatible:
    const: rockchip,rk3399-mipi-dphy-rx0

  clocks:
    items:
      - description: MIPI D-PHY ref clock
      - description: MIPI D-PHY RX0 cfg clock
      - description: Video in/out general register file clock

  clock-names:
    items:
      - const: dphy-ref
      - const: dphy-cfg
      - const: grf

  '#phy-cells':
    const: 0

  power-domains:
    description: Video in/out power domain.
    maxItems: 1

required:
  - compatible
  - clocks
  - clock-names
  - '#phy-cells'
  - power-domains

additionalProperties: false

examples:
  - |

    /*
     * MIPI D-PHY RX0 use registers in "general register files", it
     * should be a child of the GRF.
     *
     * grf: syscon@ff770000 {
     *  compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
     *  ...
     * };
     */

    #include <dt-bindings/clock/rk3399-cru.h>
    #include <dt-bindings/power/rk3399-power.h>

    mipi_dphy_rx0: mipi-dphy-rx0 {
        compatible = "rockchip,rk3399-mipi-dphy-rx0";
        clocks = <&cru SCLK_MIPIDPHY_REF>,
                 <&cru SCLK_DPHY_RX0_CFG>,
                 <&cru PCLK_VIO_GRF>;
        clock-names = "dphy-ref", "dphy-cfg", "grf";
        power-domains = <&power RK3399_PD_VIO>;
        #phy-cells = <0>;
    };


code:
Rockchip PCIE PHY
-----------------------

Required properties:
 - compatible: rockchip,rk3399-pcie-phy
 - clocks: Must contain an entry in clock-names.
	See ../clocks/clock-bindings.txt for details.
 - clock-names: Must be "refclk"
 - resets: Must contain an entry in reset-names.
	See ../reset/reset.txt for details.
 - reset-names: Must be "phy"

Required properties for legacy PHY mode (deprecated):
 - #phy-cells: must be 0

Required properties for per-lane PHY mode (preferred):
 - #phy-cells: must be 1

Example:

grf: syscon@ff770000 {
	compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
	#address-cells = <1>;
	#size-cells = <1>;

	...

	pcie_phy: pcie-phy {
		compatible = "rockchip,rk3399-pcie-phy";
		#phy-cells = <0>;
		clocks = <&cru SCLK_PCIEPHY_REF>;
		clock-names = "refclk";
		resets = <&cru SRST_PCIEPHY>;
		reset-names = "phy";
	};
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip USB2.0 phy

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    enum:
      - rockchip,rk3066a-usb-phy
      - rockchip,rk3188-usb-phy
      - rockchip,rk3288-usb-phy

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

required:
  - compatible
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

patternProperties:
  "usb-phy@[0-9a-f]+$":
    type: object

    properties:
      reg:
        maxItems: 1

      "#phy-cells":
        const: 0

      clocks:
        maxItems: 1

      clock-names:
        const: phyclk

      "#clock-cells":
        const: 0

      resets:
        maxItems: 1

      reset-names:
        const: phy-reset

      vbus-supply:
        description: phandle for vbus power source

    required:
      - reg
      - "#phy-cells"

    additionalProperties: false

examples:
  - |
    usbphy: usbphy {
      compatible = "rockchip,rk3288-usb-phy";
      #address-cells = <1>;
      #size-cells = <0>;

      usbphy0: usb-phy@320 {
        reg = <0x320>;
        #phy-cells = <0>;
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,dp-video-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC DisplayPort PHY

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Marek Szyprowski <m.szyprowski@samsung.com>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>

properties:
  compatible:
    enum:
      - samsung,exynos5250-dp-video-phy
      - samsung,exynos5420-dp-video-phy

  "#phy-cells":
    const: 0

  samsung,pmu-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to PMU system controller interface.

required:
  - compatible
  - "#phy-cells"
  - samsung,pmu-syscon

additionalProperties: false

examples:
  - |
    phy {
        compatible = "samsung,exynos5420-dp-video-phy";
        samsung,pmu-syscon = <&pmu_system_controller>;
        #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,exynos-hdmi-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC HDMI PHY

maintainers:
  - Inki Dae <inki.dae@samsung.com>
  - Seung-Woo Kim <sw0312.kim@samsung.com>
  - Kyungmin Park <kyungmin.park@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    oneOf:
      - enum:
          - samsung,exynos4210-hdmiphy
          - samsung,exynos4212-hdmiphy
      - const: samsung,exynos5-hdmiphy
        deprecated: true

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        hdmi-phy@38 {
            compatible = "samsung,exynos4210-hdmiphy";
            reg = <0x38>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung SoC series PCIe PHY

maintainers:
  - Marek Szyprowski <m.szyprowski@samsung.com>
  - Jaehoon Chung <jh80.chung@samsung.com>

properties:
  "#phy-cells":
    const: 0

  compatible:
    const: samsung,exynos5433-pcie-phy

  reg:
    maxItems: 1

  samsung,pmu-syscon:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: phandle for PMU system controller interface, used to
                 control PMU registers bits for PCIe PHY

  samsung,fsys-sysreg:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: phandle for FSYS sysreg interface, used to control
                 sysreg registers bits for PCIe PHY

required:
  - "#phy-cells"
  - compatible
  - reg
  - samsung,pmu-syscon
  - samsung,fsys-sysreg

additionalProperties: false

examples:
  - |
    pcie_phy: pcie-phy@15680000 {
        compatible = "samsung,exynos5433-pcie-phy";
        reg = <0x15680000 0x1000>;
        samsung,pmu-syscon = <&pmu_system_controller>;
        samsung,fsys-sysreg = <&syscon_fsys>;
        #phy-cells = <0>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,exynos5250-sata-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos5250 SoC SATA PHY

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Marek Szyprowski <m.szyprowski@samsung.com>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>

properties:
  compatible:
    const: samsung,exynos5250-sata-phy

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: sata_phyctrl

  "#phy-cells":
    const: 0

  reg:
    maxItems: 1

  samsung,syscon-phandle:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to PMU system controller interface.

  samsung,exynos-sataphy-i2c-phandle:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to I2C SATA interface.

required:
  - compatible
  - clocks
  - clock-names
  - "#phy-cells"
  - reg
  - samsung,syscon-phandle
  - samsung,exynos-sataphy-i2c-phandle

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5250.h>

    phy@12170000 {
        compatible = "samsung,exynos5250-sata-phy";
        reg = <0x12170000 0x1ff>;
        clocks = <&clock CLK_SATA_PHYCTRL>;
        clock-names = "sata_phyctrl";
        #phy-cells = <0>;
        samsung,syscon-phandle = <&pmu_system_controller>;
        samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
    };