code:
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
 *
 * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
 */

/dts-v1/;

#include "lpc18xx.dtsi"
#include "lpc4357.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "MYIR Tech LPC4357 Development Board";
	compatible = "myir,myd-lpc4357", "nxp,lpc4357";

	chosen {
		stdout-path = "serial3:115200n8";
	};

	memory@28000000 {
		device_type = "memory";
		reg = <0x28000000 0x2000000>;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&led_pins>;

		led1 {
			gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led2 {
			gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led3 {
			gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led4 {
			gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led5 {
			gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led6 {
			gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};

	panel: panel {
		compatible = "innolux,at070tn92";

		port {
			panel_input: endpoint {
				remote-endpoint = <&lcdc_output>;
			};
		};
	};

	vcc: vcc_fixed {
		compatible = "regulator-fixed";
		regulator-name = "vcc-supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	vmmc: vmmc_fixed {
		compatible = "regulator-fixed";
		regulator-name = "vmmc-supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&pinctrl {
	can0_pins: can0-pins {
		can_rd_cfg {
			pins = "p3_1";
			function = "can0";
			input-enable;
		};

		can_td_cfg {
			pins = "p3_2";
			function = "can0";
		};
	};

	can1_pins: can1-pins {
		can_rd_cfg {
			pins = "pe_1";
			function = "can1";
			input-enable;
		};

		can_td_cfg {
			pins = "pe_0";
			function = "can1";
		};
	};

	emc_pins: emc-pins {
		emc_addr0_22_cfg {
			pins = "p2_9",  "p2_10", "p2_11", "p2_12",
			       "p2_13", "p1_0",  "p1_1",  "p1_2",
			       "p2_8",  "p2_7",  "p2_6",  "p2_2",
			       "p2_1",  "p2_0",  "p6_8",  "p6_7",
			       "pd_16", "pd_15", "pe_0",  "pe_1",
			       "pe_2",  "pe_3",  "pe_4";
			function = "emc";
			slew-rate = <1>;
			bias-disable;
		};

		emc_data0_15_cfg {
			pins = "p1_7",  "p1_8",  "p1_9",  "p1_10",
			       "p1_11", "p1_12", "p1_13", "p1_14",
			       "p5_4",  "p5_5",  "p5_6",  "p5_7",
			       "p5_0",  "p5_1",  "p5_2",  "p5_3";
			function = "emc";
			input-enable;
			input-schmitt-disable;
			slew-rate = <1>;
			bias-disable;
		};

		emc_we_oe_cfg {
			pins = "p1_6", "p1_3";
			function = "emc";
			slew-rate = <1>;
			bias-disable;
		};

		emc_cs0_cfg {
			pins = "p1_5";
			function = "emc";
			slew-rate = <1>;
			bias-disable;
		};

		emc_sdram_dqm0_1_cfg {
			pins = "p6_12", "p6_10";
			function = "emc";
			slew-rate = <1>;
			bias-disable;
		};

		emc_sdram_ras_cas_cfg {
			pins = "p6_5", "p6_4";
			function = "emc";
			slew-rate = <1>;
			bias-disable;
		};

		emc_sdram_dycs0_cfg {
			pins = "p6_9";
			function = "emc";
			slew-rate = <1>;
			bias-disable;
		};

		emc_sdram_cke_cfg {
			pins = "p6_11";
			function = "emc";
			slew-rate = <1>;
			bias-disable;
		};

		emc_sdram_clock_cfg {
			pins = "clk0";
			function = "emc";
			input-enable;
			input-schmitt-disable;
			slew-rate = <1>;
			bias-disable;
		};
	};

	enet_rmii_pins: enet-rmii-pins {
		enet_rmii_rxd_cfg {
			pins = "p1_15", "p0_0";
			function = "enet";
			input-enable;
			input-schmitt-disable;
			slew-rate = <1>;
			bias-disable;
		};

		enet_rmii_txd_cfg {
			pins = "p1_18", "p1_20";
			function = "enet";
			slew-rate = <1>;
			bias-disable;
		};

		enet_rmii_rx_dv_cfg {
			pins = "p1_16";
			function = "enet";
			input-enable;
			input-schmitt-disable;
			bias-disable;
		};

		enet_mdio_cfg {
			pins = "p1_17";
			function = "enet";
			input-enable;
			input-schmitt-disable;
			bias-disable;
		};

		enet_mdc_cfg {
			pins = "pc_1";
			function = "enet";
			slew-rate = <1>;
			bias-disable;
		};

		enet_rmii_tx_en_cfg {
			pins = "p0_1";
			function = "enet";
			bias-disable;
		};

		enet_ref_clk_cfg {
			pins = "p1_19";
			function = "enet";
			slew-rate = <1>;
			input-enable;
			input-schmitt-disable;
			bias-disable;
		};
	};

	i2c0_pins: i2c0-pins {
		i2c0_pins_cfg {
			pins = "i2c0_scl", "i2c0_sda";
			function = "i2c0";
			input-enable;
		};
	};

	i2c1_pins: i2c1-pins {
		i2c1_pins_cfg {
			pins = "pe_15", "pe_13";
			function = "i2c1";
			input-enable;
		};
	};

	lcd_pins: lcd-pins {
		lcd_vd0_23_cfg {
			pins = "p4_1", "p4_4", "p4_3",  "p4_2",
			       "p8_7", "p8_6", "p8_5",  "p8_4",
			       "p7_5", "p4_8", "p4_10", "p4_9",
			       "p8_3", "pb_6", "pb_5",  "pb_4",
			       "p7_4", "p7_3", "p7_2",  "p7_1",
			       "pb_3", "pb_2", "pb_1",  "pb_0";
			function = "lcd";
		};

		lcd_vsync_en_dclk_lp_pwr_cfg {
			pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7";
			function = "lcd";
		};
	};

	led_pins: led-pins {
		led_1_6_cfg {
			pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0";
			function = "gpio";
			bias-pull-down;
		};
	};

	sdmmc_pins: sdmmc-pins {
		sdmmc_clk_cfg {
			pins = "pc_0";
			function = "sdmmc";
			slew-rate = <1>;
			bias-pull-down;
		};

		sdmmc_cmd_dat0_3_cfg {
			pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10";
			function = "sdmmc";
			input-enable;
			input-schmitt-disable;
			slew-rate = <1>;
			bias-disable;
		};

		sdmmc_cd_cfg {
			pins = "pc_8";
			function = "sdmmc";
			input-enable;
			bias-pull-down;
		};
	};

	spifi_pins: spifi-pins {
		spifi_sck_cfg {
			pins = "p3_3";
			function = "spifi";
			input-enable;
			input-schmitt-disable;
			slew-rate = <1>;
			bias-disable;
		};

		spifi_mosi_miso_sio2_sio3_cfg {
			pins = "p3_7", "p3_6", "p3_5", "p3_4";
			function = "spifi";
			input-enable;
			input-schmitt-disable;
			slew-rate = <1>;
			bias-disable;
		};

		spifi_cs_cfg {
			pins = "p3_8";
			function = "spifi";
			bias-disable;
		};
	};

	ssp1_pins: ssp1-pins {
		ssp1_sck_cfg {
			pins = "pf_4";
			function = "ssp1";
			slew-rate = <1>;
			bias-pull-down;
		};

		ssp1_miso_cfg {
			pins = "pf_6";
			function = "ssp1";
			input-enable;
			input-schmitt-disable;
			slew-rate = <1>;
			bias-pull-down;
		};

		ssp1_mosi_cfg {
			pins = "pf_7";
			function = "ssp1";
			slew-rate = <1>;
			bias-pull-down;
		};

		ssp1_ssel_cfg {
			pins = "pf_5";
			function = "gpio";
			bias-disable;
		};
	};

	uart0_pins: uart0-pins {
		uart0_rxd_cfg {
			pins = "pf_11";
			function = "uart0";
			input-enable;
			input-schmitt-disable;
			bias-disable;
		};

		uart0_clk_dir_txd_cfg {
			pins = "pf_8", "pf_9", "pf_10";
			function = "uart0";
			bias-pull-down;
		};
	};

	uart1_pins: uart1-pins {
		uart1_rxd_cfg {
			pins = "pc_14";
			function = "uart1";
			bias-disable;
			input-enable;
			input-schmitt-disable;
		};

		uart1_dtr_txd_cfg {
			pins = "pc_12", "pc_13";
			function = "uart1";
			bias-pull-down;
		};
	};

	uart2_pins: uart2-pins {
		uart2_rxd_cfg {
			pins = "pa_2";
			function = "uart2";
			bias-disable;
			input-enable;
			input-schmitt-disable;
		};

		uart2_txd_cfg {
			pins = "pa_1";
			function = "uart2";
			bias-pull-down;
		};
	};

	uart3_pins: uart3-pins {
		uart3_rx_cfg {
			pins = "p2_4";
			function = "uart3";
			bias-disable;
			input-enable;
			input-schmitt-disable;
		};

		uart3_tx_cfg {
			pins = "p2_3";
			function = "uart3";
			bias-pull-down;
		};
	};

	usb0_pins: usb0-pins {
		usb0_pwr_enable_cfg {
			pins = "p6_3";
			function = "usb0";
		};

		usb0_pwr_fault_cfg {
			pins = "p8_0";
			function = "usb0";
			bias-disable;
			input-enable;
		};
	};
};

&adc1 {
	status = "okay";
	vref-supply = <&vcc>;
};

&can0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&can0_pins>;
};

/* Pin conflict with EMC, muxed by JP5 and JP6 */
&can1 {
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&can1_pins>;
};

&emc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&emc_pins>;

	cs0 {
		#address-cells = <2>;
		#size-cells = <1>;
		ranges;

		mpmc,cs = <0>;
		mpmc,memory-width = <16>;
		mpmc,byte-lane-low;
		mpmc,write-enable-delay = <0>;
		mpmc,output-enable-delay = <0>;
		mpmc,read-access-delay = <70>;
		mpmc,page-mode-read-delay = <70>;

		/* SST/Microchip SST39VF1601 */
		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x400000>;
			bank-width = <2>;
		};
	};
};

&enet_tx_clk {
	clock-frequency = <50000000>;
};

&i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	clock-frequency = <400000>;
};

&i2c1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	clock-frequency = <400000>;

	sensor@49 {
		compatible = "lm75";
		reg = <0x49>;
	};

	eeprom@50 {
		compatible = "atmel,24c512";
		reg = <0x50>;
	};
};

&lcdc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&lcd_pins>;

	max-memory-bandwidth = <92240000>;

	port {
		lcdc_output: endpoint {
			remote-endpoint = <&panel_input>;
			arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
		};
	};
};

&mac {
	status = "okay";
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&enet_rmii_pins>;
	phy-handle = <&phy1>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";

		phy1: ethernet-phy@1 {
			reg = <1>;
		};
	};
};

&mmcsd {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_pins>;
	bus-width = <4>;
	vmmc-supply = <&vmmc>;
};

/* Pin conflict with SSP0, the latter is routed to J17 pin header */
&spifi {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spifi_pins>;

	/* Atmel AT25DF321A */
	flash {
		compatible = "jedec,spi-nor";
		spi-max-frequency = <51000000>;
		spi-cpol;
		spi-cpha;
	};
};

&ssp1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&ssp1_pins>;
	num-cs = <1>;
	cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>;
};

/* Routed to J17 pin header */
&uart0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
};

/* RS485 */
&uart1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
};

/* Routed to J17 pin header */
&uart2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
};

&uart3 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_pins>;
};

&usb0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&usb0_pins>;
};


code:
/*
 * NXP LPC435x, LPC433x, LPC4327, LPC4325, LPC4317 and LPC4315 SoC
 *
 * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
 *
 * This code is released using a dual license strategy: BSD/GPL
 * You can choose the licence that better fits your requirements.
 *
 * Released under the terms of 3-clause BSD License
 * Released under the terms of GNU General Public License Version 2.0
 *
 */

/ {
	compatible = "nxp,lpc4357";

	cpus {
		cpu@0 {
			compatible = "arm,cortex-m4";
		};
	};

	soc {
		sram0: sram@10000000 {
			compatible = "mmio-sram";
			reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
		};

		sram1: sram@10080000 {
			compatible = "mmio-sram";
			reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
		};

		sram2: sram@20000000 {
			compatible = "mmio-sram";
			reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
		};
	};
};

&eeprom {
	status = "okay";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2021-2022 NXP
 *
 */

/dts-v1/;
#include "ls1021a.dtsi"

/ {
	model = "LS1021A-IOT Board";
	compatible = "fsl,ls1021a-iot", "fsl,ls1021a";

	sys_mclk: clock-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};

	reg_3p3v: regulator-3V3 {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_2p5v: regulator-2V5 {
		compatible = "regulator-fixed";
		regulator-name = "2P5V";
		regulator-min-microvolt = <2500000>;
		regulator-max-microvolt = <2500000>;
		regulator-always-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack",
			"Speaker", "Speaker Ext",
			"Line", "Line In Jack";
		simple-audio-card,routing =
			"MIC_IN", "Microphone Jack",
			"Microphone Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Speaker Ext", "LINE_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
			frame-master;
			bitclock-master;
		};

		simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
			frame-master;
			bitclock-master;
		};
	};
};

&can0{
	status = "disabled";
};

&can1{
	status = "disabled";
};

&can2{
	status = "disabled";
};

&can3{
	status = "okay";
};

&dcu {
	display = <&display>;
	status = "okay";

	display: display@0 {
		bits-per-pixel = <24>;

		display-timings {
			native-mode = <&timing0>;

			timing0: mode0 {
				clock-frequency = <25000000>;
				hactive = <640>;
				vactive = <480>;
				hback-porch = <80>;
				hfront-porch = <80>;
				vback-porch = <16>;
				vfront-porch = <16>;
				hsync-len = <12>;
				vsync-len = <2>;
				hsync-active = <1>;
				vsync-active = <1>;
			};
		};
	};
};

&enet0 {
	tbi-handle = <&tbi1>;
	phy-handle = <&phy1>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&enet1 {
	tbi-handle = <&tbi1>;
	phy-handle = <&phy3>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&enet2 {
	fixed-link = <0 1 1000 0 0>;
	phy-connection-type = "rgmii-id";
	status = "okay";
};

&esdhc{
	status = "okay";
};

&i2c0 {
	status = "okay";

	pca9555: gpio@23 {
		compatible = "nxp,pca9555";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	sgtl5000: audio-codec@2a {
		#sound-dai-cells = <0x0>;
		compatible = "fsl,sgtl5000";
		reg = <0x2a>;
		VDDA-supply = <&reg_3p3v>;
		VDDIO-supply = <&reg_2p5v>;
		clocks = <&sys_mclk>;
	};

	max1239: adc@35 {
		compatible = "maxim,max1239";
		reg = <0x35>;
		#io-channel-cells = <1>;
	};

	ina2201: core-monitor@44 {
		compatible = "ti,ina220";
		reg = <0x44>;
		shunt-resistor = <1000>;
	};

	ina2202: current-monitor@45 {
		compatible = "ti,ina220";
		reg = <0x45>;
		shunt-resistor = <1000>;
	};

	lm75b: thermal-monitor@48 {
		compatible = "national,lm75b";
		reg = <0x48>;
	};
};

&lpuart0 {
	status = "okay";
};

&mdio0 {
	phy0: ethernet-phy@0 {
		reg = <0x0>;
	};

	phy1: ethernet-phy@1 {
		reg = <0x1>;
	};

	phy2: ethernet-phy@2 {
		reg = <0x2>;
	};

	phy3: ethernet-phy@3 {
		reg = <0x3>;
	};

	tbi1: tbi-phy@1f {
		reg = <0x1f>;
		device_type = "tbi-phy";
	};
};

&qspi {
	num-cs = <2>;
	status = "okay";

	s25fl128s: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&sai2 {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2017 Moxa Inc. - https://www.moxa.com/
 *
 * Author: Harry YJ Jhou (周亞諄) <harryyj.jhou@moxa.com>
 *         Jimmy Chen (陳永達)    <jimmy.chen@moxa.com>
 *         SZ Lin (林上智)        <sz.lin@moxa.com>
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "ls1021a.dtsi"

/ {
	model = "Moxa UC-8410A";
	compatible = "fsl,ls1021a-moxa-uc-8410a", "fsl,ls1021a";

	aliases {
		enet0_rgmii_phy = &rgmii_phy0;
		enet1_rgmii_phy = &rgmii_phy1;
		enet2_rgmii_phy = &rgmii_phy2;
	};

	sys_mclk: clock-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	leds {
		compatible = "gpio-leds";

		cel-pwr {
			label = "UC8410A:CEL-PWR";
			gpios = <&gpio3 27 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		cel-reset {
			label = "UC8410A:CEL-RESET";
			gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		str-led {
			label = "UC8410A:RED:PROG";
			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "mmc0";
		};

		sw-ready {
			label = "UC8410A:GREEN:SWRDY";
			gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		beeper {
			label = "UC8410A:BEEP";
			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		prog-led0 {
			label = "UC8410A:GREEN:PROG2";
			gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		prog-led1 {
			label = "UC8410A:GREEN:PROG1";
			gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		prog-led2 {
			label = "UC8410A:GREEN:PROG0";
			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		wifi-signal0 {
			label = "UC8410A:GREEN:CEL2";
			gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		wifi-signal1 {
			label = "UC8410A:GREEN:CEL1";
			gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		wifi-signal2 {
			label = "UC8410A:GREEN:CEL0";
			gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		cpu-diag-red {
			label = "UC8410A:RED:DIA";
			gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		cpu-diag-green {
			label = "UC8410A:GREEN:DIA";
			gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		cpu-diag-yellow {
			label = "UC8410A:YELLOW:DIA";
			gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		pushbtn-key {
			label = "push button key";
			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_MISC>;
			default-state = "on";
		};
	};
};

&enet0 {
	phy-handle = <&rgmii_phy0>;
	phy-connection-type = "rgmii-id";
	status = "okay";
};

&enet1 {
	phy-handle = <&rgmii_phy1>;
	phy-connection-type = "rgmii-id";
	status = "okay";
};

&enet2 {
	phy-handle = <&rgmii_phy2>;
	phy-connection-type = "rgmii-id";
	status = "okay";
};

&i2c0 {
	clock-frequency = <100000>;
	status = "okay";

	tpm@20 {
		compatible = "infineon,slb9635tt";
		reg = <0x20>;
	};

	rtc@68 {
		compatible = "dallas,ds1374";
		reg = <0x68>;
	};
};

&lpuart0 {
	status = "okay";
};

&mdio0 {
	rgmii_phy0: ethernet-phy@0 {
		compatible = "marvell,88e1118";
		reg = <0x0>;
		marvell,reg-init =
			<3 0x11 0 0x4415>, /* Reg 3,17 */
			<3 0x10 0 0x77>; /* Reg 3,16 */
	};

	rgmii_phy1: ethernet-phy@1 {
		compatible = "marvell,88e1118";
		reg = <0x1>;
		marvell,reg-init =
			<3 0x11 0 0x4415>, /* Reg 3,17 */
			<3 0x10 0 0x77>; /* Reg 3,16 */
	};

	rgmii_phy2: ethernet-phy@2 {
		compatible = "marvell,88e1118";
		reg = <0x2>;
		marvell,reg-init =
			<3 0x11 0 0x4415>, /* Reg 3,17 */
			<3 0x10 0 0x77>; /* Reg 3,16 */
	};
};

&qspi {
	status = "okay";

	flash: flash@0 {
		compatible = "spansion,s25fl064l", "spansion,s25fl164k";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <20000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		reg = <0>;

		partitions@0 {
			label = "U-Boot";
			reg = <0x0 0x180000>;
		};

		partitions@180000 {
			label = "U-Boot Env";
			reg = <0x180000 0x680000>;
		};
	};
};

&sata {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2013-2014 Freescale Semiconductor, Inc.
 * Copyright 2018 NXP
 */

/dts-v1/;
#include "ls1021a.dtsi"

/ {
	model = "LS1021A QDS Board";
	compatible = "fsl,ls1021a-qds", "fsl,ls1021a";

	aliases {
		enet0_rgmii_phy = &rgmii_phy1;
		enet1_rgmii_phy = &rgmii_phy2;
		enet2_rgmii_phy = &rgmii_phy3;
		enet0_sgmii_phy = &sgmii_phy1c;
		enet1_sgmii_phy = &sgmii_phy1d;
	};

	sys_mclk: clock-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};

	reg_3p3v: regulator {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack",
			"Speaker", "Speaker Ext",
			"Line", "Line In Jack";
		simple-audio-card,routing =
			"MIC_IN", "Microphone Jack",
			"Microphone Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Speaker Ext", "LINE_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
			frame-master;
			bitclock-master;
		};

		simple-audio-card,codec {
			sound-dai = <&codec>;
			frame-master;
			bitclock-master;
		};
	};
};

&dspi0 {
	bus-num = <0>;
	status = "okay";

	dspiflash: at45db021d@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
		spi-max-frequency = <16000000>;
		spi-cpol;
		spi-cpha;
		reg = <0>;
	};
};

&enet0 {
	tbi-handle = <&tbi0>;
	phy-handle = <&sgmii_phy1c>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&enet1 {
	tbi-handle = <&tbi0>;
	phy-handle = <&sgmii_phy1d>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&enet2 {
	phy-handle = <&rgmii_phy3>;
	phy-connection-type = "rgmii-id";
	status = "okay";
};

&esdhc {
	status = "okay";
};

&i2c0 {
	status = "okay";

	pca9547: mux@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0>;

			ds3232: rtc@68 {
				compatible = "dallas,ds3232";
				reg = <0x68>;
				interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			ina220@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};

			ina220@41 {
				compatible = "ti,ina220";
				reg = <0x41>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			eeprom@56 {
				compatible = "atmel,24c512";
				reg = <0x56>;
			};

			eeprom@57 {
				compatible = "atmel,24c512";
				reg = <0x57>;
			};

			adt7461a@4c {
				compatible = "adi,adt7461a";
				reg = <0x4c>;
			};
		};

		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x4>;

			codec: sgtl5000@2a {
				#sound-dai-cells = <0>;
				compatible = "fsl,sgtl5000";
				reg = <0x2a>;
				VDDA-supply = <&reg_3p3v>;
				VDDIO-supply = <&reg_3p3v>;
				clocks = <&sys_mclk>;
			};
		};
	};
};

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	/* NOR, NAND Flashes and FPGA on board */
	ranges = <0x0 0x0 0x0 0x60000000 0x08000000>,
		 <0x2 0x0 0x0 0x7e800000 0x00010000>,
		 <0x3 0x0 0x0 0x7fb00000 0x00000100>;
	status = "okay";

	nor@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x8000000>;
		big-endian;
		bank-width = <2>;
		device-width = <1>;
	};

	nand@2,0 {
		compatible = "fsl,ifc-nand";
		reg = <0x2 0x0 0x10000>;
	};

	fpga: board-control@3,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-mfd";
		reg = <0x3 0x0 0x0000100>;
		bank-width = <1>;
		device-width = <1>;
		ranges = <0 3 0 0x100>;

		mdio-mux-emi1 {
			compatible = "mdio-mux-mmioreg";
			mdio-parent-bus = <&mdio0>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x54 1>; /* BRDCFG4 */
			mux-mask = <0xe0>; /* EMI1[2:0] */

			/* Onboard PHYs */
			ls1021amdio0: mdio@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;
				rgmii_phy1: ethernet-phy@1 {
					reg = <0x1>;
				};
			};

			ls1021amdio1: mdio@20 {
				reg = <0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				rgmii_phy2: ethernet-phy@2 {
					reg = <0x2>;
				};
			};

			ls1021amdio2: mdio@40 {
				reg = <0x40>;
				#address-cells = <1>;
				#size-cells = <0>;
				rgmii_phy3: ethernet-phy@3 {
					reg = <0x3>;
				};
			};

			ls1021amdio3: mdio@60 {
				reg = <0x60>;
				#address-cells = <1>;
				#size-cells = <0>;
				sgmii_phy1c: ethernet-phy@1c {
					reg = <0x1c>;
				};
			};

			ls1021amdio4: mdio@80 {
				reg = <0x80>;
				#address-cells = <1>;
				#size-cells = <0>;
				sgmii_phy1d: ethernet-phy@1d {
					reg = <0x1d>;
				};
			};
		};
	};
};

&lpuart0 {
	status = "okay";
};

&mdio0 {
	tbi0: tbi-phy@8 {
		reg = <0x8>;
		device_type = "tbi-phy";
	};
};

&qspi {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <20000000>;
		reg = <0>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
	};
};

&sai2 {
	status = "okay";
};

&sata {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&can0 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&can2 {
	status = "disabled";
};

&can3 {
	status = "disabled";
};


code:
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2016-2018 NXP Semiconductors
 * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
 */

/dts-v1/;
#include "ls1021a.dtsi"

/ {
	model = "NXP LS1021A-TSN Board";
	compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";

	sys_mclk: clock-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};

	reg_vdda_codec: regulator-3V3 {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_vddio_codec: regulator-2V5 {
		compatible = "regulator-fixed";
		regulator-name = "2P5V";
		regulator-min-microvolt = <2500000>;
		regulator-max-microvolt = <2500000>;
		regulator-always-on;
	};
};

&dspi0 {
	bus-num = <0>;
	status = "okay";

	/* ADG704BRMZ 1:4 SPI mux/demux */
	sja1105: ethernet-switch@1 {
		reg = <0x1>;
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nxp,sja1105t";
		/* 12 MHz */
		spi-max-frequency = <12000000>;
		/* Sample data on trailing clock edge */
		spi-cpha;
		/* SPI controller settings for SJA1105 timing requirements */
		fsl,spi-cs-sck-delay = <1000>;
		fsl,spi-sck-cs-delay = <1000>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				/* ETH5 written on chassis */
				label = "swp5";
				phy-handle = <&rgmii_phy6>;
				phy-mode = "rgmii-id";
				reg = <0>;
			};

			port@1 {
				/* ETH2 written on chassis */
				label = "swp2";
				phy-handle = <&rgmii_phy3>;
				phy-mode = "rgmii-id";
				reg = <1>;
			};

			port@2 {
				/* ETH3 written on chassis */
				label = "swp3";
				phy-handle = <&rgmii_phy4>;
				phy-mode = "rgmii-id";
				reg = <2>;
			};

			port@3 {
				/* ETH4 written on chassis */
				label = "swp4";
				phy-handle = <&rgmii_phy5>;
				phy-mode = "rgmii-id";
				reg = <3>;
			};

			port@4 {
				/* Internal port connected to eth2 */
				ethernet = <&enet2>;
				phy-mode = "rgmii";
				rx-internal-delay-ps = <0>;
				tx-internal-delay-ps = <0>;
				reg = <4>;

				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
		};
	};
};

&enet0 {
	tbi-handle = <&tbi0>;
	phy-handle = <&sgmii_phy2>;
	phy-mode = "sgmii";
	status = "okay";
};

&enet1 {
	tbi-handle = <&tbi1>;
	phy-handle = <&sgmii_phy1>;
	phy-mode = "sgmii";
	status = "okay";
};

/* RGMII delays added via PCB traces */
&enet2 {
	phy-mode = "rgmii";
	status = "okay";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&esdhc {
	status = "okay";
};

&i2c0 {
	status = "okay";

	/* 3 axis accelerometer */
	accelerometer@1e {
		compatible = "fsl,fxls8471";
		reg = <0x1e>;
	};

	/* Audio codec (SAI2) */
	audio-codec@2a {
		compatible = "fsl,sgtl5000";
		VDDIO-supply = <&reg_vddio_codec>;
		VDDA-supply = <&reg_vdda_codec>;
		#sound-dai-cells = <0>;
		clocks = <&sys_mclk>;
		reg = <0x2a>;
	};

	/* Current sensing circuit for 1V VDDCORE PMIC rail */
	current-sensor@44 {
		compatible = "ti,ina220";
		shunt-resistor = <1000>;
		reg = <0x44>;
	};

	/* Current sensing circuit for 12V VCC rail */
	current-sensor@45 {
		compatible = "ti,ina220";
		shunt-resistor = <1000>;
		reg = <0x45>;
	};

	/* Thermal monitor - case */
	temperature-sensor@48 {
		compatible = "national,lm75";
		reg = <0x48>;
	};

	/* Thermal monitor - chip */
	temperature-sensor@4c {
		compatible = "ti,tmp451";
		reg = <0x4c>;
	};

	eeprom@51 {
		compatible = "atmel,24c32";
		reg = <0x51>;
	};

	/* Unsupported devices:
	 * - FXAS21002C Gyroscope at 0x20
	 * - TI ADS7924 4-channel ADC at 0x49
	 */
};

&ifc {
	status = "disabled";
};

&lpuart0 {
	status = "okay";
};

&lpuart3 {
	status = "okay";
};

&mdio0 {
	/* AR8031 */
	sgmii_phy1: ethernet-phy@1 {
		reg = <0x1>;
		/* SGMII1_PHY_INT_B: connected to IRQ2, active low */
		interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
	};

	/* AR8031 */
	sgmii_phy2: ethernet-phy@2 {
		reg = <0x2>;
		/* SGMII2_PHY_INT_B: connected to IRQ2, active low */
		interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
	};

	/* BCM5464 quad PHY */
	rgmii_phy3: ethernet-phy@3 {
		reg = <0x3>;
	};

	rgmii_phy4: ethernet-phy@4 {
		reg = <0x4>;
	};

	rgmii_phy5: ethernet-phy@5 {
		reg = <0x5>;
	};

	rgmii_phy6: ethernet-phy@6 {
		reg = <0x6>;
	};

	/* SGMII PCS for enet0 */
	tbi0: tbi-phy@1f {
		reg = <0x1f>;
		device_type = "tbi-phy";
	};
};

&mdio1 {
	/* SGMII PCS for enet1 */
	tbi1: tbi-phy@1f {
		reg = <0x1f>;
		device_type = "tbi-phy";
	};
};

&qspi {
	status = "okay";

	flash@0 {
		/* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */
		compatible = "jedec,spi-nor";
		spi-max-frequency = <20000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "RCW";
				reg = <0x0 0x40000>;
			};

			partition@40000 {
				label = "U-Boot";
				reg = <0x40000 0x300000>;
			};

			partition@340000 {
				label = "U-Boot Env";
				reg = <0x340000 0x100000>;
			};
		};
	};
};

&sai2 {
	status = "okay";
};

&sata {
	status = "okay";
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2013-2014 Freescale Semiconductor, Inc.
 * Copyright 2018 NXP
 */

/dts-v1/;
#include "ls1021a.dtsi"

/ {
	model = "LS1021A TWR Board";
	compatible = "fsl,ls1021a-twr", "fsl,ls1021a";

	aliases {
		enet2_rgmii_phy = &rgmii_phy1;
		enet0_sgmii_phy = &sgmii_phy2;
		enet1_sgmii_phy = &sgmii_phy0;
	};

	sys_mclk: clock-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};

	reg_3p3v: regulator {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack",
			"Speaker", "Speaker Ext",
			"Line", "Line In Jack";
		simple-audio-card,routing =
			"MIC_IN", "Microphone Jack",
			"Microphone Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Speaker Ext", "LINE_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai1>;
			frame-master;
			bitclock-master;
		};

		simple-audio-card,codec {
			sound-dai = <&codec>;
			frame-master;
			bitclock-master;
		};
	};

	panel: panel {
		compatible = "nec,nl4827hc19-05b";

		port {
			panel_in: endpoint {
				remote-endpoint = <&dcu_out>;
			};
		};
	};
};

&dcu {
	status = "okay";

	port {
		dcu_out: endpoint {
			remote-endpoint = <&panel_in>;
		};
	};
};

&dspi1 {
	bus-num = <0>;
	status = "okay";

	dspiflash: s25fl064k@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spansion,s25fl064k";
		spi-max-frequency = <16000000>;
		spi-cpol;
		spi-cpha;
		reg = <0>;
	};
};

&enet0 {
	tbi-handle = <&tbi0>;
	phy-handle = <&sgmii_phy2>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&enet1 {
	tbi-handle = <&tbi1>;
	phy-handle = <&sgmii_phy0>;
	phy-connection-type = "sgmii";
	status = "okay";
};

&enet2 {
	phy-handle = <&rgmii_phy1>;
	phy-connection-type = "rgmii-id";
	status = "okay";
};

&i2c0 {
	status = "okay";

	ina220@40 {
		compatible = "ti,ina220";
		reg = <0x40>;
		shunt-resistor = <1000>;
	};

	ina220@41 {
		compatible = "ti,ina220";
		reg = <0x41>;
		shunt-resistor = <1000>;
	};

};

&i2c1 {
	status = "okay";
	codec: sgtl5000@a {
		#sound-dai-cells = <0>;
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		VDDA-supply = <&reg_3p3v>;
		VDDIO-supply = <&reg_3p3v>;
		clocks = <&sys_mclk>;
	};
};

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	/* NOR Flash on board */
	ranges = <0x0 0x0 0x0 0x60000000 0x08000000>;
	status = "okay";

	nor@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x8000000>;
		big-endian;
		bank-width = <2>;
		device-width = <1>;
	};
};

&lpuart0 {
	status = "okay";
};

&mdio0 {
	sgmii_phy0: ethernet-phy@0 {
		reg = <0x0>;
	};
	rgmii_phy1: ethernet-phy@1 {
		reg = <0x1>;
	};
	sgmii_phy2: ethernet-phy@2 {
		reg = <0x2>;
	};
	tbi0: tbi-phy@1f {
		reg = <0x1f>;
		device_type = "tbi-phy";
	};
};

&mdio1 {
	tbi1: tbi-phy@1f {
		reg = <0x1f>;
		device_type = "tbi-phy";
	};
};

&esdhc {
        status = "okay";
};

&qspi {
	status = "okay";

	n25q128a130: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		reg = <0>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
	};
};

&sai1 {
	status = "okay";
};

&sata {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&can0 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&can2 {
	status = "disabled";
};

&can3 {
	status = "disabled";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2013-2014 Freescale Semiconductor, Inc.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	aliases {
		crypto = &crypto;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		rtc1 = &ftm_alarm0;
		serial0 = &lpuart0;
		serial1 = &lpuart1;
		serial2 = &lpuart2;
		serial3 = &lpuart3;
		serial4 = &lpuart4;
		serial5 = &lpuart5;
		sysclk = &sysclk;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@f00 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0xf00>;
			clocks = <&clockgen 1 0>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@f01 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0xf01>;
			clocks = <&clockgen 1 0>;
			#cooling-cells = <2>;
		};
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x0>;
	};

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	reboot {
		compatible = "syscon-reboot";
		regmap = <&dcfg>;
		offset = <0xb0>;
		mask = <0x02>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		device_type = "soc";
		interrupt-parent = <&gic>;
		ranges;

		ddr: memory-controller@1080000 {
			compatible = "fsl,qoriq-memory-controller";
			reg = <0x0 0x1080000 0x0 0x1000>;
			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
		};

		gic: interrupt-controller@1400000 {
			compatible = "arm,gic-400", "arm,cortex-a7-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x0 0x1401000 0x0 0x1000>,
			      <0x0 0x1402000 0x0 0x2000>,
			      <0x0 0x1404000 0x0 0x2000>,
			      <0x0 0x1406000 0x0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;

		};

		msi1: msi-controller@1570e00 {
			compatible = "fsl,ls1021a-msi";
			reg = <0x0 0x1570e00 0x0 0x8>;
			msi-controller;
			interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
		};

		msi2: msi-controller@1570e08 {
			compatible = "fsl,ls1021a-msi";
			reg = <0x0 0x1570e08 0x0 0x8>;
			msi-controller;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
		};

		ifc: memory-controller@1530000 {
			compatible = "fsl,ifc";
			reg = <0x0 0x1530000 0x0 0x10000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sfp: efuse@1e80000 {
			compatible = "fsl,ls1021a-sfp";
			reg = <0x0 0x1e80000 0x0 0x10000>;
			clocks = <&clockgen 4 3>;
			clock-names = "sfp";
		};

		dcfg: dcfg@1ee0000 {
			compatible = "fsl,ls1021a-dcfg", "syscon";
			reg = <0x0 0x1ee0000 0x0 0x1000>;
			big-endian;
		};

		qspi: spi@1550000 {
			compatible = "fsl,ls1021a-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x1550000 0x0 0x10000>,
			      <0x0 0x40000000 0x0 0x20000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "qspi_en", "qspi";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
			status = "disabled";
		};

		esdhc: esdhc@1560000 {
			compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
			reg = <0x0 0x1560000 0x0 0x10000>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			big-endian;
			bus-width = <4>;
			status = "disabled";
		};

		sata: sata@3200000 {
			compatible = "fsl,ls1021a-ahci";
			reg = <0x0 0x3200000 0x0 0x10000>,
			      <0x0 0x20220520 0x0 0x4>;
			reg-names = "ahci", "sata-ecc";
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			dma-coherent;
			status = "disabled";
		};

		scfg: scfg@1570000 {
			compatible = "fsl,ls1021a-scfg", "syscon";
			reg = <0x0 0x1570000 0x0 0x10000>;
			big-endian;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x1570000 0x10000>;

			extirq: interrupt-controller@1ac {
				compatible = "fsl,ls1021a-extirq";
				#interrupt-cells = <2>;
				#address-cells = <0>;
				interrupt-controller;
				reg = <0x1ac 4>;
				interrupt-map =
					<0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
					<1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
					<2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
					<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
					<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
					<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-map-mask = <0x7 0x0>;
			};
		};

		crypto: crypto@1700000 {
			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
			fsl,sec-era = <7>;
			#address-cells = <1>;
			#size-cells = <1>;
			reg		 = <0x0 0x1700000 0x0 0x100000>;
			ranges		 = <0x0 0x0 0x1700000 0x100000>;
			interrupts	 = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			dma-coherent;

			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.0-job-ring",
				     "fsl,sec-v4.0-job-ring";
				reg = <0x10000 0x10000>;
				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.0-job-ring",
				     "fsl,sec-v4.0-job-ring";
				reg = <0x20000 0x10000>;
				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.0-job-ring",
				     "fsl,sec-v4.0-job-ring";
				reg = <0x30000 0x10000>;
				interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.0-job-ring",
				     "fsl,sec-v4.0-job-ring";
				reg = <0x40000 0x10000>;
				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			};

		};

		clockgen: clocking@1ee1000 {
			compatible = "fsl,ls1021a-clockgen";
			reg = <0x0 0x1ee1000 0x0 0x1000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		tmu: tmu@1f00000 {
			compatible = "fsl,qoriq-tmu";
			reg = <0x0 0x1f00000 0x0 0x10000>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>;
			fsl,tmu-calibration = <0x00000000 0x00000020>,
					      <0x00000001 0x00000024>,
					      <0x00000002 0x0000002a>,
					      <0x00000003 0x00000032>,
					      <0x00000004 0x00000038>,
					      <0x00000005 0x0000003e>,
					      <0x00000006 0x00000043>,
					      <0x00000007 0x0000004a>,
					      <0x00000008 0x00000050>,
					      <0x00000009 0x00000059>,
					      <0x0000000a 0x0000005f>,
					      <0x0000000b 0x00000066>,

					      <0x00010000 0x00000023>,
					      <0x00010001 0x0000002b>,
					      <0x00010002 0x00000033>,
					      <0x00010003 0x0000003a>,
					      <0x00010004 0x00000042>,
					      <0x00010005 0x0000004a>,
					      <0x00010006 0x00000054>,
					      <0x00010007 0x0000005c>,
					      <0x00010008 0x00000065>,
					      <0x00010009 0x0000006f>,

					      <0x00020000 0x00000029>,
					      <0x00020001 0x00000033>,
					      <0x00020002 0x0000003d>,
					      <0x00020003 0x00000048>,
					      <0x00020004 0x00000054>,
					      <0x00020005 0x00000060>,
					      <0x00020006 0x0000006c>,

					      <0x00030000 0x00000025>,
					      <0x00030001 0x00000033>,
					      <0x00030002 0x00000043>,
					      <0x00030003 0x00000055>;
			#thermal-sensor-cells = <1>;
		};

		dspi0: spi@2100000 {
			compatible = "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&clockgen 4 1>;
			spi-num-chipselects = <6>;
			big-endian;
			status = "disabled";
		};

		dspi1: spi@2110000 {
			compatible = "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2110000 0x0 0x10000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&clockgen 4 1>;
			spi-num-chipselects = <6>;
			big-endian;
			status = "disabled";
		};

		i2c0: i2c@2180000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			dma-names = "rx", "tx";
			dmas = <&edma0 1 38>, <&edma0 1 39>;
			status = "disabled";
		};

		i2c1: i2c@2190000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			dma-names = "rx", "tx";
			dmas = <&edma0 1 36>, <&edma0 1 37>;
			status = "disabled";
		};

		i2c2: i2c@21a0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21a0000 0x0 0x10000>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			dma-names = "rx", "tx";
			dmas = <&edma0 1 34>, <&edma0 1 35>;
			status = "disabled";
		};

		uart0: serial@21c0500 {
			compatible = "fsl,16550-FIFO64", "ns16550a";
			reg = <0x0 0x21c0500 0x0 0x100>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			fifo-size = <15>;
			status = "disabled";
		};

		uart1: serial@21c0600 {
			compatible = "fsl,16550-FIFO64", "ns16550a";
			reg = <0x0 0x21c0600 0x0 0x100>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			fifo-size = <15>;
			status = "disabled";
		};

		uart2: serial@21d0500 {
			compatible = "fsl,16550-FIFO64", "ns16550a";
			reg = <0x0 0x21d0500 0x0 0x100>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			fifo-size = <15>;
			status = "disabled";
		};

		uart3: serial@21d0600 {
			compatible = "fsl,16550-FIFO64", "ns16550a";
			reg = <0x0 0x21d0600 0x0 0x100>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>;
			fifo-size = <15>;
			status = "disabled";
		};

		counter0: counter@29d0000 {
			compatible = "fsl,ftm-quaddec";
			reg = <0x0 0x29d0000 0x0 0x10000>;
			big-endian;
			status = "disabled";
		};

		counter1: counter@29e0000 {
			compatible = "fsl,ftm-quaddec";
			reg = <0x0 0x29e0000 0x0 0x10000>;
			big-endian;
			status = "disabled";
		};

		counter2: counter@29f0000 {
			compatible = "fsl,ftm-quaddec";
			reg = <0x0 0x29f0000 0x0 0x10000>;
			big-endian;
			status = "disabled";
		};

		counter3: counter@2a00000 {
			compatible = "fsl,ftm-quaddec";
			reg = <0x0 0x2a00000 0x0 0x10000>;
			big-endian;
			status = "disabled";
		};

		gpio0: gpio@2300000 {
			compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@2310000 {
			compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2320000 {
			compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2330000 {
			compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2330000 0x0 0x10000>;
			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		lpuart0: serial@2950000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2950000 0x0 0x1000>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysclk>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart1: serial@2960000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2960000 0x0 0x1000>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart2: serial@2970000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2970000 0x0 0x1000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart3: serial@2980000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2980000 0x0 0x1000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart4: serial@2990000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2990000 0x0 0x1000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart5: serial@29a0000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x29a0000 0x0 0x1000>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			clock-names = "ipg";
			status = "disabled";
		};

		pwm0: pwm@29d0000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x29d0000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				<&clockgen 4 1>, <&clockgen 4 1>;
			big-endian;
			status = "disabled";
		};

		pwm1: pwm@29e0000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x29e0000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				<&clockgen 4 1>, <&clockgen 4 1>;
			big-endian;
			status = "disabled";
		};

		pwm2: pwm@29f0000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x29f0000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				<&clockgen 4 1>, <&clockgen 4 1>;
			big-endian;
			status = "disabled";
		};

		pwm3: pwm@2a00000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2a00000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				<&clockgen 4 1>, <&clockgen 4 1>;
			big-endian;
			status = "disabled";
		};

		pwm4: pwm@2a10000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2a10000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				<&clockgen 4 1>, <&clockgen 4 1>;
			big-endian;
			status = "disabled";
		};

		pwm5: pwm@2a20000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2a20000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				<&clockgen 4 1>, <&clockgen 4 1>;
			big-endian;
			status = "disabled";
		};

		pwm6: pwm@2a30000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2a30000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				<&clockgen 4 1>, <&clockgen 4 1>;
			big-endian;
			status = "disabled";
		};

		pwm7: pwm@2a40000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2a40000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				<&clockgen 4 1>, <&clockgen 4 1>;
			big-endian;
			status = "disabled";
		};

		wdog0: watchdog@2ad0000 {
			compatible = "fsl,imx21-wdt";
			reg = <0x0 0x2ad0000 0x0 0x10000>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			clock-names = "wdog-en";
			big-endian;
		};

		sai1: sai@2b50000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0x2b50000 0x0 0x10000>;
			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&clockgen 4 1>, <&clockgen 4 1>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 47>,
			       <&edma0 1 46>;
			status = "disabled";
		};

		sai2: sai@2b60000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0x2b60000 0x0 0x10000>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&clockgen 4 1>, <&clockgen 4 1>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 45>,
			       <&edma0 1 44>;
			status = "disabled";
		};

		edma0: dma-controller@2c00000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x2c00000 0x0 0x10000>,
			      <0x0 0x2c10000 0x0 0x10000>,
			      <0x0 0x2c20000 0x0 0x10000>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			big-endian;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&clockgen 4 1>,
				 <&clockgen 4 1>;
		};

		dcu: dcu@2ce0000 {
			compatible = "fsl,ls1021a-dcu";
			reg = <0x0 0x2ce0000 0x0 0x10000>;
			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 0>,
				<&clockgen 4 0>;
			clock-names = "dcu", "pix";
			big-endian;
			status = "disabled";
		};

		mdio0: mdio@2d24000 {
			compatible = "gianfar";
			device_type = "mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2d24000 0x0 0x4000>,
			      <0x0 0x2d10030 0x0 0x4>;
		};

		mdio1: mdio@2d64000 {
			compatible = "gianfar";
			device_type = "mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2d64000 0x0 0x4000>,
			      <0x0 0x2d50030 0x0 0x4>;
		};

		ptp_clock@2d10e00 {
			compatible = "fsl,etsec-ptp";
			reg = <0x0 0x2d10e00 0x0 0xb0>;
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
			fsl,tclk-period = <5>;
			fsl,tmr-prsc    = <2>;
			fsl,tmr-add     = <0xaaaaaaab>;
			fsl,tmr-fiper1  = <999999995>;
			fsl,tmr-fiper2  = <999999995>;
			fsl,max-adj     = <499999999>;
			fsl,extts-fifo;
		};

		enet0: ethernet@2d10000 {
			compatible = "fsl,etsec2";
			device_type = "network";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			model = "eTSEC";
			fsl,magic-packet;
			ranges;
			dma-coherent;

			queue-group@2d10000 {
				#address-cells = <2>;
				#size-cells = <2>;
				reg = <0x0 0x2d10000 0x0 0x1000>;
				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
			};

			queue-group@2d14000  {
				#address-cells = <2>;
				#size-cells = <2>;
				reg = <0x0 0x2d14000 0x0 0x1000>;
				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		enet1: ethernet@2d50000 {
			compatible = "fsl,etsec2";
			device_type = "network";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			model = "eTSEC";
			ranges;
			dma-coherent;

			queue-group@2d50000  {
				#address-cells = <2>;
				#size-cells = <2>;
				reg = <0x0 0x2d50000 0x0 0x1000>;
				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			};

			queue-group@2d54000  {
				#address-cells = <2>;
				#size-cells = <2>;
				reg = <0x0 0x2d54000 0x0 0x1000>;
				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		enet2: ethernet@2d90000 {
			compatible = "fsl,etsec2";
			device_type = "network";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			model = "eTSEC";
			ranges;
			dma-coherent;

			queue-group@2d90000  {
				#address-cells = <2>;
				#size-cells = <2>;
				reg = <0x0 0x2d90000 0x0 0x1000>;
				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
			};

			queue-group@2d94000  {
				#address-cells = <2>;
				#size-cells = <2>;
				reg = <0x0 0x2d94000 0x0 0x1000>;
				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		usb2: usb@8600000 {
			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
			reg = <0x0 0x8600000 0x0 0x1000>;
			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "host";
			phy_type = "ulpi";
		};

		usb3: usb@3100000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3100000 0x0 0x10000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
			snps,dis_rxdet_inp3_quirk;
			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
		};

		pcie@3400000 {
			compatible = "fsl,ls1021a-pcie";
			reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */
			      <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
			fsl,pcie-scfg = <&scfg 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-viewport = <6>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */
				 <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi1>, <&msi2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		pcie@3500000 {
			compatible = "fsl,ls1021a-pcie";
			reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */
			      <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
			fsl,pcie-scfg = <&scfg 1>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-viewport = <6>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */
				 <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi1>, <&msi2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		can0: can@2a70000 {
			compatible = "fsl,ls1021ar2-flexcan";
			reg = <0x0 0x2a70000 0x0 0x1000>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
			clock-names = "ipg", "per";
			big-endian;
		};

		can1: can@2a80000 {
			compatible = "fsl,ls1021ar2-flexcan";
			reg = <0x0 0x2a80000 0x0 0x1000>;
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
			clock-names = "ipg", "per";
			big-endian;
		};

		can2: can@2a90000 {
			compatible = "fsl,ls1021ar2-flexcan";
			reg = <0x0 0x2a90000 0x0 0x1000>;
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
			clock-names = "ipg", "per";
			big-endian;
		};

		can3: can@2aa0000 {
			compatible = "fsl,ls1021ar2-flexcan";
			reg = <0x0 0x2aa0000 0x0 0x1000>;
			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
			clock-names = "ipg", "per";
			big-endian;
		};

		ocram1: sram@10000000 {
			compatible = "mmio-sram";
			reg = <0x0 0x10000000 0x0 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x10000000 0x10000>;
		};

		ocram2: sram@10010000 {
			compatible = "mmio-sram";
			reg = <0x0 0x10010000 0x0 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x10010000 0x10000>;
		};

		qdma: dma-controller@8390000 {
			compatible = "fsl,ls1021a-qdma";
			reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
			      <0x0 0x8389000 0x0 0x1000>, /* Status regs */
			      <0x0 0x838a000 0x0 0x2000>; /* Block regs */
			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "qdma-error",
				"qdma-queue0", "qdma-queue1";
			#dma-cells = <2>;
			dma-channels = <8>;
			block-number = <1>;
			block-offset = <0x1000>;
			fsl,dma-queues = <2>;
			status-sizes = <64>;
			queue-sizes = <64 64>;
			big-endian;
		};

		rcpm: power-controller@1ee2140 {
			compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
			reg = <0x0 0x1ee2140 0x0 0x8>;
			#fsl,rcpm-wakeup-cells = <2>;
			#power-domain-cells = <0>;
		};

		ftm_alarm0: timer0@29d0000 {
			compatible = "fsl,ls1021a-ftm-alarm";
			reg = <0x0 0x29d0000 0x0 0x10000>;
			reg-names = "ftm";
			fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
		};
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;

			thermal-sensors = <&tmu 0>;

			trips {
				cpu_alert: cpu-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit: cpu-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>,
						<&cpu1 THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2018-2022 TQ-Systems GmbH
 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
 */

/ {
	model = "TQ-Systems MBA6ULx Baseboard";

	aliases {
		mmc0 = &usdhc2;
		mmc1 = &usdhc1;
		rtc0 = &rtc0;
		rtc1 = &snvs_rtc;
	};

	chosen {
		stdout-path = &uart1;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		power-supply = <&reg_mba6ul_3v3>;
		enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
		status = "disabled";
	};

	beeper: beeper {
		compatible = "gpio-beeper";
		gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>;
	};

	gpio_buttons: gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_buttons>;

		button1 {
			label = "s14";
			linux,code = <KEY_1>;
			gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>;
		};

		button2 {
			label = "s6";
			linux,code = <KEY_2>;
			gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>;
		};

		button3 {
			label = "s7";
			linux,code = <KEY_3>;
			gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>;
		};

		power-button {
			label = "POWER";
			linux,code = <KEY_POWER>;
			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
			gpio-key,wakeup;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";
		status = "okay";

		led1 {
			label = "led1";
			gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "default-on";
		};

		led2 {
			label = "led2";
			gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	reg_lcd_pwr: regulator-lcd-pwr {
		compatible = "regulator-fixed";
		regulator-name = "lcd-pwr";
		gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		status = "disabled";
	};

	reg_mba6ul_3v3: regulator-mba6ul-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "supply-mba6ul-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_mba6ul_5v0: regulator-mba6ul-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "supply-mba6ul-5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
	};

	reg_mpcie: regulator-mpcie-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "mpcie-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
		startup-delay-us = <500000>;
		vin-supply = <&reg_mba6ul_3v3>;
	};

	reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 {
		compatible = "regulator-fixed";
		gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-name = "otg2-vbus-supply-5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&reg_mpcie>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x6000000>;
			linux,cma-default;
		};
	};

	sound {
		compatible = "fsl,imx-audio-tlv320aic32x4";
		model = "imx-audio-tlv320aic32x4";
		ssi-controller = <&sai1>;
		audio-codec = <&tlv320aic32x4>;
		audio-asrc = <&asrc>;
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_mba6ul_3v3>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_mba6ul_3v3>;
	status = "okay";
};

&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <768000000>;
};

&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	num-cs = <1>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	phy-supply = <&reg_mba6ul_3v3>;
	phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <25>;
	phy-reset-post-delay = <1>;
	status = "okay";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_mba6ul_3v3>;
	phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <25>;
	phy-reset-post-delay = <1>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			clocks = <&clks IMX6UL_CLK_ENET_REF>;
			reg = <0>;
			max-speed = <100>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
			reg = <1>;
			max-speed = <100>;
		};
	};
};

&i2c4 {
	tlv320aic32x4: audio-codec@18 {
		compatible = "ti,tlv320aic32x4";
		reg = <0x18>;
		clocks = <&clks IMX6UL_CLK_SAI1>;
		clock-names = "mclk";
		ldoin-supply = <&reg_mba6ul_3v3>;
		iov-supply = <&reg_mba6ul_3v3>;
	};

	jc42: temperature-sensor@19 {
		compatible = "nxp,se97", "jedec,jc-42.4-temp";
		reg = <0x19>;
	};

	expander_out0: gpio-expander@20 {
		compatible = "nxp,pca9554";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	expander_in0: gpio-expander@21 {
		compatible = "nxp,pca9554";
		reg = <0x21>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_expander_in0>;
		interrupt-parent = <&gpio4>;
		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-controller;
		#gpio-cells = <2>;

		enet1_int-hog {
			gpio-hog;
			gpios = <6 0>;
			input;
		};

		enet2_int-hog {
			gpio-hog;
			gpios = <7 0>;
			input;
		};
	};

	expander_out1: gpio-expander@22 {
		compatible = "nxp,pca9554";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	analog_touch: touchscreen@41 {
		compatible = "st,stmpe811";
		reg = <0x41>;
		interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
		interrupt-parent = <&gpio4>;
		interrupt-controller;
		status = "disabled";

		stmpe_touchscreen {
			compatible = "st,stmpe-ts";
			st,adc-freq = <1>;      /* 3.25 MHz ADC clock speed */
			st,ave-ctrl = <3>;      /* 8 sample average control */
			st,fraction-z = <7>;    /* 7 length fractional part in z */
			/*
			 * 50 mA typical 80 mA max touchscreen drivers
			 * current limit value
			 */
			st,i-drive = <1>;
			st,mod-12b = <1>;       /* 12-bit ADC */
			st,ref-sel = <0>;       /* internal ADC reference */
			st,sample-time = <4>;   /* ADC converstion time: 80 clocks */
			st,settling = <3>;      /* 1 ms panel driver settling time */
			st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */
		};
	};

	/* NXP SE97BTP with temperature sensor + eeprom */
	se97b: eeprom@51 {
		compatible = "nxp,se97b", "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
	};
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "okay";
};

&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>,
			  <&clks IMX6UL_CLK_SAI1>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <0>, <24000000>;
	fsl,sai-mclk-direction-output;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	/* for DTE mode, add below change */
	/* fsl,dte-mode; */
	/* pinctrl-0 = <&pinctrl_uart6dte>; */
	uart-has-rtscts;
	linux,rs485-enabled-at-boot-time;
	rs485-rts-active-low;
	rs485-rx-during-tx;
	status = "okay";
};

/* otg-port */
&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1>;
	power-active-high;
	over-current-active-low;
	/* we implement only dual role but not a fully featured OTG */
	hnp-disable;
	srp-disable;
	adp-disable;
	dr_mode = "otg";
	status = "okay";
};

/* 7-port usb hub */
/* id, pwr, oc pins not connected */
&usbotg2 {
	disable-over-current;
	vbus-supply = <&reg_otg2vbus_5v0>;
	dr_mode = "host";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
	bus-width = <4>;
	vmmc-supply = <&reg_mba6ul_3v3>;
	vqmmc-supply = <&reg_vccsd>;
	no-1-8-v;
	no-mmc;
	no-sdio;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog1>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_buttons: buttonsgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x100b0
		>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK	0x1b020
			MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO	0x1b020
			MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI	0x1b020
			MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0	0x1b020
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b0a8
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0a0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0a0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b0a8
		>;
	};

	pinctrl_enet2_mdc: enet2mdcgrp {
		fsl,pins = <
			/* mdio */
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
		>;
	};

	pinctrl_expander_in0: expanderin0grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA02__GPIO4_IO23	0x1b0b1
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			/* 100 k PD, DSE 120 OHM, SPPEED LO */
			MX6UL_PAD_GPIO1_IO09__PWM2_OUT		0x00003050
		>;
	};

	pinctrl_sai1: sai1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK	0x1b0b1
			MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC	0x1b0b1
			MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA	0x1f0b8
			MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA	0x110b0
			MX6UL_PAD_CSI_DATA01__SAI1_MCLK		0x1b0b1
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b1
			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_uart6: uart6grp {
		fsl,pins = <
			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x1b0b1
			MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX	0x1b0b1
			MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS	0x1b0b1
			MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS	0x1b0b1
		>;
	};

	pinctrl_uart6dte: uart6dte {
		fsl,pins = <
			MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX	0x1b0b1
			MX6UL_PAD_CSI_MCLK__UART6_DTE_RX	0x1b0b1
			MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS	0x1b0b1
			MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS	0x1b0b1
		>;
	};

	pinctrl_usb_otg1: usbotg1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x00017059
			MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC	0x0001b0b0
			MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR	0x0001b099
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x00017069
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x00017059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x00017059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x00017059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x00017059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x00017059
			/* WP */
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x0001b099
			/* CD */
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x0001b099
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x00017069
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x000170b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x000170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x000170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x000170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x000170b9
			/* WP */
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x0001b099
			/* CD */
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x0001b099
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x00017069
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x000170f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x000170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x000170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x000170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x000170f9
			/* WP */
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x0001b099
			/* CD */
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x0001b099
		>;
	};

	pinctrl_wdog1: wdog1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B	0x0001b099
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright 2014 Carlo Caione <carlo@caione.org>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/sound/meson-aiu.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	iio-hwmon {
		compatible = "iio-hwmon";
		io-channels = <&saradc 8>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		cbus: cbus@c1100000 {
			compatible = "simple-bus";
			reg = <0xc1100000 0x200000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xc1100000 0x200000>;

			hhi: system-controller@4000 {
				compatible = "amlogic,meson-hhi-sysctrl",
					     "simple-mfd",
					     "syscon";
				reg = <0x4000 0x400>;
			};

			aiu: audio-controller@5400 {
				compatible = "amlogic,aiu";
				#sound-dai-cells = <2>;
				sound-name-prefix = "AIU";
				reg = <0x5400 0x2ac>;
				interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
					     <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
				interrupt-names = "i2s", "spdif";
				status = "disabled";
			};

			assist: assist@7c00 {
				compatible = "amlogic,meson-mx-assist", "syscon";
				reg = <0x7c00 0x200>;
			};

			hwrng: rng@8100 {
				compatible = "amlogic,meson-rng";
				reg = <0x8100 0x8>;
			};

			uart_A: serial@84c0 {
				compatible = "amlogic,meson6-uart";
				reg = <0x84c0 0x18>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
				fifo-size = <128>;
				status = "disabled";
			};

			uart_B: serial@84dc {
				compatible = "amlogic,meson6-uart";
				reg = <0x84dc 0x18>;
				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			i2c_A: i2c@8500 {
				compatible = "amlogic,meson6-i2c";
				reg = <0x8500 0x20>;
				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			pwm_ab: pwm@8550 {
				compatible = "amlogic,meson-pwm";
				reg = <0x8550 0x10>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm_cd: pwm@8650 {
				compatible = "amlogic,meson-pwm";
				reg = <0x8650 0x10>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			saradc: adc@8680 {
				compatible = "amlogic,meson-saradc";
				reg = <0x8680 0x34>;
				#io-channel-cells = <1>;
				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			uart_C: serial@8700 {
				compatible = "amlogic,meson6-uart";
				reg = <0x8700 0x18>;
				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			i2c_B: i2c@87c0 {
				compatible = "amlogic,meson6-i2c";
				reg = <0x87c0 0x20>;
				interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			usb0_phy: phy@8800 {
				compatible = "amlogic,meson-mx-usb2-phy";
				#phy-cells = <0>;
				reg = <0x8800 0x20>;
				status = "disabled";
			};

			usb1_phy: phy@8820 {
				compatible = "amlogic,meson-mx-usb2-phy";
				#phy-cells = <0>;
				reg = <0x8820 0x20>;
				status = "disabled";
			};

			sdio: mmc@8c20 {
				compatible = "amlogic,meson-mx-sdio";
				reg = <0x8c20 0x20>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spifc: spi@8c80 {
				compatible = "amlogic,meson6-spifc";
				reg = <0x8c80 0x80>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			sdhc: mmc@8e00 {
				compatible = "amlogic,meson-mx-sdhc";
				reg = <0x8e00 0x42>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			gpio_intc: interrupt-controller@9880 {
				compatible = "amlogic,meson-gpio-intc";
				reg = <0x9880 0x10>;
				interrupt-controller;
				#interrupt-cells = <2>;
				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
				status = "disabled";
			};

			wdt: watchdog@9900 {
				compatible = "amlogic,meson6-wdt";
				reg = <0x9900 0x8>;
				interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
			};

			timer_abcde: timer@9940 {
				compatible = "amlogic,meson6-timer";
				reg = <0x9940 0x18>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
					     <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
					     <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
					     <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
			};
		};

		L2: cache-controller@c4200000 {
			compatible = "arm,pl310-cache";
			reg = <0xc4200000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};

		periph: bus@c4300000 {
			compatible = "simple-bus";
			reg = <0xc4300000 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xc4300000 0x10000>;

			gic: interrupt-controller@1000 {
				compatible = "arm,cortex-a9-gic";
				reg = <0x1000 0x1000>,
				      <0x100 0x100>;
				interrupt-controller;
				#interrupt-cells = <3>;
			};
		};

		aobus: aobus@c8100000 {
			compatible = "simple-bus";
			reg = <0xc8100000 0x100000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xc8100000 0x100000>;

			ao_arc_rproc: remoteproc@1c {
				compatible = "amlogic,meson-mx-ao-arc";
				reg = <0x1c 0x8>, <0x38 0x8>;
				reg-names = "remap", "cpu";
				status = "disabled";
			};

			ir_receiver: ir-receiver@480 {
				compatible = "amlogic,meson6-ir";
				reg = <0x480 0x20>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			uart_AO: serial@4c0 {
				compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart";
				reg = <0x4c0 0x18>;
				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};

			i2c_AO: i2c@500 {
				compatible = "amlogic,meson6-i2c";
				reg = <0x500 0x20>;
				interrupts = <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			rtc: rtc@740 {
				compatible = "amlogic,meson6-rtc";
				reg = <0x740 0x14>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
				#address-cells = <1>;
				#size-cells = <1>;
				status = "disabled";
			};
		};

		usb0: usb@c9040000 {
			compatible = "snps,dwc2";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xc9040000 0x40000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&usb0_phy>;
			phy-names = "usb2-phy";
			g-rx-fifo-size = <512>;
			g-np-tx-fifo-size = <500>;
			g-tx-fifo-size = <256 192 128 128 128>;
			dr_mode = "host";
			status = "disabled";
		};

		usb1: usb@c90c0000 {
			compatible = "snps,dwc2";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xc90c0000 0x40000>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&usb1_phy>;
			phy-names = "usb2-phy";
			dr_mode = "host";
			status = "disabled";
		};

		ethmac: ethernet@c9410000 {
			compatible = "amlogic,meson6-dwmac", "snps,dwmac";
			reg = <0xc9410000 0x10000
			       0xc1108108 0x4>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			status = "disabled";
		};

		ahb_sram: sram@d9000000 {
			compatible = "mmio-sram";
			reg = <0xd9000000 0x20000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0xd9000000 0x20000>;
		};

		bootrom: bootrom@d9040000 {
			compatible = "amlogic,meson-mx-bootrom", "syscon";
			reg = <0xd9040000 0x10000>;
		};

		secbus: secbus@da000000 {
			compatible = "simple-bus";
			reg = <0xda000000 0x6000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xda000000 0x6000>;

			efuse: nvmem@0 {
				compatible = "amlogic,meson6-efuse";
				reg = <0x0 0x2000>;
				#address-cells = <1>;
				#size-cells = <1>;
			};
		};
	};

	thermal_sensor: thermal-sensor {
		compatible = "generic-adc-thermal";
		#thermal-sensor-cells = <0>;
		io-channels = <&saradc 8>;
		io-channel-names = "sensor-channel";
	};

	xtal: xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xtal";
		#clock-cells = <0>;
	};
}; /* end of / */


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright 2014 Carlo Caione <carlo@caione.org>
 */

/dts-v1/;
#include "meson6.dtsi"

/ {
	model = "Geniatech ATV1200";
	compatible = "geniatech,atv1200", "amlogic,meson6";

	aliases {
		serial0 = &uart_AO;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x40000000 0x80000000>;
	};
};

&uart_AO {
	status = "okay";
};

&ethmac {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright 2014 Carlo Caione <carlo@caione.org>
 */

#include "meson.dtsi"

/ {
	model = "Amlogic Meson6 SoC";
	compatible = "amlogic,meson6";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x200>;
		};

		cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x201>;
		};
	};

	apb2: bus@d0000000 {
		compatible = "simple-bus";
		reg = <0xd0000000 0x40000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0xd0000000 0x40000>;
	};

	clk81: clk@0 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <200000000>;
	};
}; /* end of / */

&efuse {
	status = "disabled";
};

&timer_abcde {
	clocks = <&xtal>, <&clk81>;
	clock-names = "xtal", "pclk";
};

&uart_AO {
	clocks = <&xtal>, <&clk81>, <&clk81>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_A {
	clocks = <&xtal>, <&clk81>, <&clk81>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_B {
	clocks = <&xtal>, <&clk81>, <&clk81>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_C {
	clocks = <&xtal>, <&clk81>, <&clk81>;
	clock-names = "xtal", "pclk", "baud";
};


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright 2014 Beniamino Galvani <b.galvani@gmail.com>
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "meson8.dtsi"

/ {
	model = "MINIX NEO-X8";
	compatible = "minix,neo-x8", "amlogic,meson8";

	aliases {
		serial0 = &uart_AO;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x40000000 0x80000000>;
	};

	gpio-leds {
		compatible = "gpio-leds";

		blue {
			label = "x8:blue:power";
			gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>;
		};
	};
};

&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
};

&i2c_AO {
	status = "okay";
	pinctrl-0 = <&i2c_ao_pins>;
	pinctrl-names = "default";

	pmic@32 {
		compatible = "ricoh,rn5t618";
		reg = <0x32>;
		system-power-controller;

		regulators {
		};
	};

	rtc@51 {
		compatible = "nxp,pcf8563";
		reg = <0x51>;
	};
};

&spifc {
	status = "okay";
	pinctrl-0 = <&spi_nor_pins>;
	pinctrl-names = "default";

	flash@0 {
		compatible = "mxicy,mx25l1606e";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		spi-max-frequency = <30000000>;

		partition@0 {
			label = "boot";
			reg = <0x0 0x100000>;
		};

		partition@100000 {
			label = "env";
			reg = <0x100000 0x10000>;
		};
	};
};

&ir_receiver {
	status = "okay";
	pinctrl-0 = <&ir_recv_pins>;
	pinctrl-names = "default";
};

&ethmac {
	status = "okay";
	pinctrl-0 = <&eth_pins>;
	pnictrl-names = "default";
};