code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ST-Ericsson DMA40 DMA Engine

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  "#dma-cells":
    const: 3
    description: |
      The first cell is the unique device channel number as indicated by this
      table for DB8500 which is the only ASIC known to use DMA40:

      0:  SPI controller 0
      1:  SD/MMC controller 0 (unused)
      2:  SD/MMC controller 1 (unused)
      3:  SD/MMC controller 2 (unused)
      4:  I2C port 1
      5:  I2C port 3
      6:  I2C port 2
      7:  I2C port 4
      8:  Synchronous Serial Port SSP0
      9:  Synchronous Serial Port SSP1
      10: Multi-Channel Display Engine MCDE RX
      11: UART port 2
      12: UART port 1
      13: UART port 0
      14: Multirate Serial Port MSP2
      15: I2C port 0
      16: USB OTG in/out endpoints 7 & 15
      17: USB OTG in/out endpoints 6 & 14
      18: USB OTG in/out endpoints 5 & 13
      19: USB OTG in/out endpoints 4 & 12
      20: SLIMbus or HSI channel 0
      21: SLIMbus or HSI channel 1
      22: SLIMbus or HSI channel 2
      23: SLIMbus or HSI channel 3
      24: Multimedia DSP SXA0
      25: Multimedia DSP SXA1
      26: Multimedia DSP SXA2
      27: Multimedia DSP SXA3
      28: SD/MMC controller 2
      29: SD/MMC controller 0
      30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
      31: MSP port 0 or SLIMbus channel 0
      32: SD/MMC controller 1
      33: SPI controller 2
      34: i2c3 RX2 TX2
      35: SPI controller 1
      36: USB OTG in/out endpoints 3 & 11
      37: USB OTG in/out endpoints 2 & 10
      38: USB OTG in/out endpoints 1 & 9
      39: USB OTG in/out endpoints 8
      40: SPI controller 3
      41: SD/MMC controller 3
      42: SD/MMC controller 4
      43: SD/MMC controller 5
      44: Multimedia DSP SXA4
      45: Multimedia DSP SXA5
      46: SLIMbus channel 8 or Multimedia DSP SXA6
      47: SLIMbus channel 9 or Multimedia DSP SXA7
      48: Crypto Accelerator 1
      49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
      50: Hash Accelerator 1 TX
      51: memcpy TX (to be used by the DMA driver for memcpy operations)
      52: SLIMbus or HSI channel 4
      53: SLIMbus or HSI channel 5
      54: SLIMbus or HSI channel 6
      55: SLIMbus or HSI channel 7
      56: memcpy (to be used by the DMA driver for memcpy operations)
      57: memcpy (to be used by the DMA driver for memcpy operations)
      58: memcpy (to be used by the DMA driver for memcpy operations)
      59: memcpy (to be used by the DMA driver for memcpy operations)
      60: memcpy (to be used by the DMA driver for memcpy operations)
      61: Crypto Accelerator 0
      62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
      63: Hash Accelerator 0 TX

      The second cell is the DMA request line number. This is only used when
      a fixed channel is allocated, and indicated by setting bit 3 in the
      flags field (see below).

      The third cell is a 32bit flags bitfield with the following possible
      bits set:
      0x00000001 (bit 0) - mode:
        Logical channel when unset
        Physical channel when set
      0x00000002 (bit 1) - direction:
        Memory to Device when unset
        Device to Memory when set
      0x00000004 (bit 2) - endianness:
        Little endian when unset
        Big endian when set
      0x00000008 (bit 3) - use fixed channel:
        Use automatic channel selection when unset
        Use DMA request line number when set
      0x00000010 (bit 4) - set channel as high priority:
        Normal priority when unset
        High priority when set

  compatible:
    items:
      - const: stericsson,db8500-dma40
      - const: stericsson,dma40

  reg:
    items:
      - description: DMA40 memory base
      - description: LCPA memory base

  reg-names:
    items:
      - const: base
      - const: lcpa

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  memcpy-channels:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: Array of u32 elements indicating which channels on the DMA
      engine are elegible for memcpy transfers

required:
  - "#dma-cells"
  - compatible
  - reg
  - interrupts
  - clocks
  - memcpy-channels

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/mfd/dbx500-prcmu.h>
    dma-controller@801C0000 {
      compatible = "stericsson,db8500-dma40", "stericsson,dma40";
      reg = <0x801C0000 0x1000>, <0x40010000 0x800>;
      reg-names = "base", "lcpa";
      interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
      #dma-cells = <3>;
      memcpy-channels = <56 57 58 59 60>;
      clocks = <&prcmu_clk PRCMU_DMACLK>;
    };
...


code:
Texas Instruments DMA Crossbar (DMA request router)

Required properties:
- compatible:	"ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
		"ti,am335x-edma-crossbar" for AM335x and AM437x
- reg:		Memory map for accessing module
- #dma-cells:	Should be set to match with the DMA controller's dma-cells
		for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
- dma-requests:	Number of DMA requests the crossbar can receive
- dma-masters:	phandle pointing to the DMA controller

The DMA controller node need to have the following poroperties:
- dma-requests:	Number of DMA requests the controller can handle

Optional properties:
- ti,dma-safe-map: Safe routing value for unused request lines
- ti,reserved-dma-request-ranges: DMA request ranges which should not be used
		when mapping xbar input to DMA request, they are either
		allocated to be used by for example the DSP or they are used as
		memcpy channels in eDMA.

Notes:
When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request
the DMA event number as crossbar ID (input to the DMA crossbar).

For ti,am335x-edma-crossbar: the meaning of parameters of dmas for clients:
dmas = <&edma_xbar 12 0 1>; where <12> is the DMA request number, <0> is the TC
the event should be assigned and <1> is the mux selection for in the crossbar.
When mux 0 is used the DMA channel can be requested directly from edma node.

Example:

/* DMA controller */
sdma: dma-controller@4a056000 {
	compatible = "ti,omap4430-sdma";
	reg = <0x4a056000 0x1000>;
	interrupts =	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	dma-channels = <32>;
	dma-requests = <127>;
};

/* DMA crossbar */
sdma_xbar: dma-router@4a002b78 {
	compatible = "ti,dra7-dma-crossbar";
	reg = <0x4a002b78 0xfc>;
	#dma-cells = <1>;
	dma-requests = <205>;
	ti,dma-safe-map = <0>;
	/* Protect the sDMA request ranges: 10-14 and 100-126 */
	ti,reserved-dma-request-ranges = <10 5>, <100 27>;
	dma-masters = <&sdma>;
};

/* DMA client */
uart1: serial@4806a000 {
	compatible = "ti,omap4-uart";
	reg = <0x4806a000 0x100>;
	interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	ti,hwmods = "uart1";
	clock-frequency = <48000000>;
	/* Requesting crossbar input 49 and 50 */
	dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
	dma-names = "tx", "rx";
};

repo_name: angery/linux


code:
Texas Instruments eDMA

The eDMA3 consists of two components: Channel controller (CC) and Transfer
Controller(s) (TC). The CC is the main entry for DMA users since it is
responsible for the DMA channel handling, while the TCs are responsible to
execute the actual DMA tansfer.

------------------------------------------------------------------------------
eDMA3 Channel Controller

Required properties:
--------------------
- compatible:	Should be:
		- "ti,edma3-tpcc" for the channel controller(s) on OMAP,
		  AM33xx and AM43xx SoCs.
		- "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
		  channel controller(s) on 66AK2G.
- #dma-cells:	Should be set to <2>. The first number is the DMA request
		number and the second is the TC the channel is serviced on.
- reg:		Memory map of eDMA CC
- reg-names:	"edma3_cc"
- interrupts:	Interrupt lines for CCINT, MPERR and CCERRINT.
- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
- ti,tptcs:	List of TPTCs associated with the eDMA in the following form:
		<&tptc_phandle TC_priority_number>. The highest priority is 0.

SoC-specific Required properties:
--------------------------------
The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
- ti,hwmods:	Name of the hwmods associated to the eDMA CC.

The following are mandatory properties for 66AK2G SoCs only:
- power-domains:Should contain a phandle to a PM domain provider node
		and an args specifier containing the device id
		value. This property is as per the binding,
		Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml

Optional properties:
-------------------
- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
		these channels will be SW triggered channels. See example.
- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
		the driver, they are allocated to be used by for example the
		DSP. See example.
- dma-channel-mask: Mask of usable channels.
		Single uint32 for EDMA with 32 channels, array of two uint32 for
		EDMA with 64 channels. See example and
		Documentation/devicetree/bindings/dma/dma-common.yaml

------------------------------------------------------------------------------
eDMA3 Transfer Controller

Required properties:
--------------------
- compatible:	Should be:
		- "ti,edma3-tptc" for the transfer controller(s) on OMAP,
		  AM33xx and AM43xx SoCs.
		- "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the
		  transfer controller(s) on 66AK2G.
- reg:		Memory map of eDMA TC
- interrupts:	Interrupt number for TCerrint.

SoC-specific Required properties:
--------------------------------
The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
- ti,hwmods:	Name of the hwmods associated to the eDMA TC.

The following are mandatory properties for 66AK2G SoCs only:
- power-domains:Should contain a phandle to a PM domain provider node
		and an args specifier containing the device id
		value. This property is as per the binding,
		Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml

Optional properties:
-------------------
- interrupt-names: "edma3_tcerrint"

------------------------------------------------------------------------------
Examples:

1.
edma: edma@49000000 {
	compatible = "ti,edma3-tpcc";
	ti,hwmods = "tpcc";
	reg =	<0x49000000 0x10000>;
	reg-names = "edma3_cc";
	interrupts = <12 13 14>;
	interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
	dma-requests = <64>;
	#dma-cells = <2>;

	ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;

	/* Channel 20 and 21 is allocated for memcpy */
	ti,edma-memcpy-channels = <20 21>;
	/* The following PaRAM slots are reserved: 35-44 and 100-109 */
	ti,edma-reserved-slot-ranges = <35 10>, <100 10>;
	/* The following channels are reserved: 35-44 */
	dma-channel-mask = <0xffffffff /* Channel 0-31 */
			    0xffffe007>; /* Channel 32-63 */
};

edma_tptc0: tptc@49800000 {
	compatible = "ti,edma3-tptc";
	ti,hwmods = "tptc0";
	reg =	<0x49800000 0x100000>;
	interrupts = <112>;
	interrupt-names = "edm3_tcerrint";
};

edma_tptc1: tptc@49900000 {
	compatible = "ti,edma3-tptc";
	ti,hwmods = "tptc1";
	reg =	<0x49900000 0x100000>;
	interrupts = <113>;
	interrupt-names = "edm3_tcerrint";
};

edma_tptc2: tptc@49a00000 {
	compatible = "ti,edma3-tptc";
	ti,hwmods = "tptc2";
	reg =	<0x49a00000 0x100000>;
	interrupts = <114>;
	interrupt-names = "edm3_tcerrint";
};

sham: sham@53100000 {
	compatible = "ti,omap4-sham";
	ti,hwmods = "sham";
	reg = <0x53100000 0x200>;
	interrupts = <109>;
	/* DMA channel 36 executed on eDMA TC0 - low priority queue */
	dmas = <&edma 36 0>;
	dma-names = "rx";
};

mcasp0: mcasp@48038000 {
	compatible = "ti,am33xx-mcasp-audio";
	ti,hwmods = "mcasp0";
	reg = <0x48038000 0x2000>,
		<0x46000000 0x400000>;
	reg-names = "mpu", "dat";
	interrupts = <80>, <81>;
	interrupt-names = "tx", "rx";
	/* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
	dmas = <&edma 8 2>,
	       <&edma 9 2>;
	dma-names = "tx", "rx";
};

2.
edma1: edma@2728000 {
	compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
	reg =	<0x02728000 0x8000>;
	reg-names = "edma3_cc";
	interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
	interrupt-names = "edma3_ccint", "emda3_mperr",
			  "edma3_ccerrint";
	dma-requests = <64>;
	#dma-cells = <2>;

	ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;

	/*
	 * memcpy is disabled, can be enabled with:
	 * ti,edma-memcpy-channels = <12 13 14 15>;
	 * for example.
	 */

	power-domains = <&k2g_pds 0x4f>;
};

edma1_tptc0: tptc@27b0000 {
	compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
	reg =	<0x027b0000 0x400>;
	power-domains = <&k2g_pds 0x4f>;
};

edma1_tptc1: tptc@27b8000 {
	compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
	reg =	<0x027b8000 0x400>;
	power-domains = <&k2g_pds 0x4f>;
};

mmc0: mmc@23000000 {
	compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
	reg = <0x23000000 0x400>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
	dmas = <&edma1 24 0>, <&edma1 25 0>;
	dma-names = "tx", "rx";
	bus-width = <4>;
	ti,needs-special-reset;
	no-1-8-v;
	max-frequency = <96000000>;
	power-domains = <&k2g_pds 0xb>;
	clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
	clock-names = "fck", "mmchsdb_fck";
};

------------------------------------------------------------------------------
DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
binding.

Required properties:
- compatible : "ti,edma3"
- #dma-cells: Should be set to <1>
              Clients should use a single channel number per DMA request.
- reg: Memory map for accessing module
- interrupts: Exactly 3 interrupts need to be specified in the order:
              1. Transfer completion interrupt.
              2. Memory protection interrupt.
              3. Error interrupt.
Optional properties:
- ti,hwmods: Name of the hwmods associated to the EDMA
- ti,edma-xbar-event-map: Crossbar event to channel map

Deprecated properties:
Listed here in case one wants to boot an old kernel with new DTB. These
properties might need to be added to the new DTS files.
- ti,edma-regions: Number of regions
- ti,edma-slots: Number of slots
- dma-channels: Specify total DMA channels per CC

Example:

edma: edma@49000000 {
	reg = <0x49000000 0x10000>;
	interrupt-parent = <&intc>;
	interrupts = <12 13 14>;
	compatible = "ti,edma3";
	ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
	#dma-cells = <1>;
	ti,edma-xbar-event-map = /bits/ 16 <1 12
					    2 13>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 Texas Instruments Incorporated
# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/ti/k3-bcdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments K3 DMSS BCDMA Device Tree Bindings

maintainers:
  - Peter Ujfalusi <peter.ujfalusi@gmail.com>

description: |
  The Block Copy DMA (BCDMA) is intended to perform similar functions as the TR
  mode channels of K3 UDMA-P.
  BCDMA includes block copy channels and Split channels.

  Block copy channels mainly used for memory to memory transfers, but with
  optional triggers a block copy channel can service peripherals by accessing
  directly to memory mapped registers or area.

  Split channels can be used to service PSI-L based peripherals.
  The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
  with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
  legacy peripheral.

  PDMAs can be configured via BCDMA split channel's peer registers to match with
  the configuration of the legacy peripheral.

allOf:
  - $ref: /schemas/dma/dma-controller.yaml#
  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#

properties:
  compatible:
    const: ti,am64-dmss-bcdma

  "#dma-cells":
    const: 3
    description: |
      cell 1: type of the BCDMA channel to be used to service the peripheral:
        0 - split channel
        1 - block copy channel using global trigger 1
        2 - block copy channel using global trigger 2
        3 - block copy channel using local trigger

      cell 2: parameter for the channel:
        if cell 1 is 0 (split channel):
          PSI-L thread ID of the remote (to BCDMA) end.
          Valid ranges for thread ID depends on the data movement direction:
          for source thread IDs (rx): 0 - 0x7fff
          for destination thread IDs (tx): 0x8000 - 0xffff

          Please refer to the device documentation for the PSI-L thread map and
          also the PSI-L peripheral chapter for the correct thread ID.
        if cell 1 is 1 or 2 (block copy channel using global trigger):
          Unused, ignored

          The trigger must be configured for the channel externally to BCDMA,
          channels using global triggers should not be requested directly, but
          via DMA event router.
        if cell 1 is 3 (block copy channel using local trigger):
          bchan number of the locally triggered channel

      cell 3: ASEL value for the channel

  reg:
    maxItems: 5

  reg-names:
    items:
      - const: gcfg
      - const: bchanrt
      - const: rchanrt
      - const: tchanrt
      - const: ringrt

  msi-parent: true

  ti,asel:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: ASEL value for non slave channels

  ti,sci-rm-range-bchan:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: |
      Array of BCDMA block-copy channel resource subtypes for resource
      allocation for this host
    minItems: 1
    # Should be enough
    maxItems: 255
    items:
      maximum: 0x3f

  ti,sci-rm-range-tchan:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: |
      Array of BCDMA split tx channel resource subtypes for resource allocation
      for this host
    minItems: 1
    # Should be enough
    maxItems: 255
    items:
      maximum: 0x3f

  ti,sci-rm-range-rchan:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: |
      Array of BCDMA split rx channel resource subtypes for resource allocation
      for this host
    minItems: 1
    # Should be enough
    maxItems: 255
    items:
      maximum: 0x3f

required:
  - compatible
  - "#dma-cells"
  - reg
  - reg-names
  - msi-parent
  - ti,sci
  - ti,sci-dev-id
  - ti,sci-rm-range-bchan
  - ti,sci-rm-range-tchan
  - ti,sci-rm-range-rchan

unevaluatedProperties: false

examples:
  - |+
    cbass_main {
        #address-cells = <2>;
        #size-cells = <2>;

        main_dmss {
            compatible = "simple-mfd";
            #address-cells = <2>;
            #size-cells = <2>;
            dma-ranges;
            ranges;

            ti,sci-dev-id = <25>;

            main_bcdma: dma-controller@485c0100 {
                compatible = "ti,am64-dmss-bcdma";

                reg = <0x0 0x485c0100 0x0 0x100>,
                      <0x0 0x4c000000 0x0 0x20000>,
                      <0x0 0x4a820000 0x0 0x20000>,
                      <0x0 0x4aa40000 0x0 0x20000>,
                      <0x0 0x4bc00000 0x0 0x100000>;
                reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
                msi-parent = <&inta_main_dmss>;
                #dma-cells = <3>;

                ti,sci = <&dmsc>;
                ti,sci-dev-id = <26>;

                ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
                ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
                ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 Texas Instruments Incorporated
# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/ti/k3-pktdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments K3 DMSS PKTDMA Device Tree Bindings

maintainers:
  - Peter Ujfalusi <peter.ujfalusi@gmail.com>

description: |
  The Packet DMA (PKTDMA) is intended to perform similar functions as the packet
  mode channels of K3 UDMA-P.
  PKTDMA only includes Split channels to service PSI-L based peripherals.

  The peripherals can be PSI-L native or legacy, non PSI-L native peripherals
  with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the
  legacy peripheral.

  PDMAs can be configured via PKTDMA split channel's peer registers to match
  with the configuration of the legacy peripheral.

allOf:
  - $ref: /schemas/dma/dma-controller.yaml#
  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#

properties:
  compatible:
    const: ti,am64-dmss-pktdma

  "#dma-cells":
    const: 2
    description: |
      The first cell is the PSI-L  thread ID of the remote (to PKTDMA) end.
      Valid ranges for thread ID depends on the data movement direction:
      for source thread IDs (rx): 0 - 0x7fff
      for destination thread IDs (tx): 0x8000 - 0xffff

      Please refer to the device documentation for the PSI-L thread map and also
      the PSI-L peripheral chapter for the correct thread ID.

      The second cell is the ASEL value for the channel

  reg:
    maxItems: 4

  reg-names:
    items:
      - const: gcfg
      - const: rchanrt
      - const: tchanrt
      - const: ringrt

  msi-parent: true

  ti,sci-rm-range-tchan:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: |
      Array of PKTDMA split tx channel resource subtypes for resource allocation
      for this host
    minItems: 1
    # Should be enough
    maxItems: 255
    items:
      maximum: 0x3f

  ti,sci-rm-range-tflow:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: |
      Array of PKTDMA split tx flow resource subtypes for resource allocation
      for this host
    minItems: 1
    # Should be enough
    maxItems: 255
    items:
      maximum: 0x3f

  ti,sci-rm-range-rchan:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: |
      Array of PKTDMA split rx channel resource subtypes for resource allocation
      for this host
    minItems: 1
    # Should be enough
    maxItems: 255
    items:
      maximum: 0x3f

  ti,sci-rm-range-rflow:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: |
      Array of PKTDMA split rx flow resource subtypes for resource allocation
      for this host
    minItems: 1
    # Should be enough
    maxItems: 255
    items:
      maximum: 0x3f

required:
  - compatible
  - "#dma-cells"
  - reg
  - reg-names
  - msi-parent
  - ti,sci
  - ti,sci-dev-id
  - ti,sci-rm-range-tchan
  - ti,sci-rm-range-tflow
  - ti,sci-rm-range-rchan
  - ti,sci-rm-range-rflow

unevaluatedProperties: false

examples:
  - |+
    cbass_main {
        #address-cells = <2>;
        #size-cells = <2>;

        main_dmss {
            compatible = "simple-mfd";
            #address-cells = <2>;
            #size-cells = <2>;
            dma-ranges;
            ranges;

            ti,sci-dev-id = <25>;

            main_pktdma: dma-controller@485c0000 {
                compatible = "ti,am64-dmss-pktdma";

                reg = <0x0 0x485c0000 0x0 0x100>,
                      <0x0 0x4a800000 0x0 0x20000>,
                      <0x0 0x4aa00000 0x0 0x40000>,
                      <0x0 0x4b800000 0x0 0x400000>;
                reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
                msi-parent = <&inta_main_dmss>;
                #dma-cells = <2>;

                ti,sci = <&dmsc>;
                ti,sci-dev-id = <30>;

                ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
                                        <0x24>, /* CPSW_TX_CHAN */
                                        <0x25>, /* SAUL_TX_0_CHAN */
                                        <0x26>, /* SAUL_TX_1_CHAN */
                                        <0x27>, /* ICSSG_0_TX_CHAN */
                                        <0x28>; /* ICSSG_1_TX_CHAN */
                ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
                                        <0x11>, /* RING_CPSW_TX_CHAN */
                                        <0x12>, /* RING_SAUL_TX_0_CHAN */
                                        <0x13>, /* RING_SAUL_TX_1_CHAN */
                                        <0x14>, /* RING_ICSSG_0_TX_CHAN */
                                        <0x15>; /* RING_ICSSG_1_TX_CHAN */
                ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
                                        <0x2b>, /* CPSW_RX_CHAN */
                                        <0x2d>, /* SAUL_RX_0_CHAN */
                                        <0x2f>, /* SAUL_RX_1_CHAN */
                                        <0x31>, /* SAUL_RX_2_CHAN */
                                        <0x33>, /* SAUL_RX_3_CHAN */
                                        <0x35>, /* ICSSG_0_RX_CHAN */
                                        <0x37>; /* ICSSG_1_RX_CHAN */
                ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
                                        <0x2c>, /* FLOW_CPSW_RX_CHAN */
                                        <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
                                        <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
                                        <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
                                        <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2019 Texas Instruments Incorporated
# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments K3 NAVSS Unified DMA Device Tree Bindings

maintainers:
  - Peter Ujfalusi <peter.ujfalusi@gmail.com>

description: |
  The UDMA-P is intended to perform similar (but significantly upgraded)
  functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
  module supports the transmission and reception of various packet types.
  The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
  data structure compliant packets to/from smaller data blocks that are natively
  compatible with the specific requirements of each connected peripheral.
  Multiple Tx and Rx channels are provided within the DMA which allow multiple
  segmentation or reassembly operations to be ongoing. The DMA controller
  maintains state information for each of the channels which allows packet
  segmentation and reassembly operations to be time division multiplexed between
  channels in order to share the underlying DMA hardware. An external DMA
  scheduler is used to control the ordering and rate at which this multiplexing
  occurs for Transmit operations. The ordering and rate of Receive operations
  is indirectly controlled by the order in which blocks are pushed into the DMA
  on the Rx PSI-L interface.

  The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
  channels. Channels in the UDMA-P can be configured to be either Packet-Based
  or Third-Party channels on a channel by channel basis.

  All transfers within NAVSS is done between PSI-L source and destination
  threads.
  The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
  legacy, non PSI-L native peripherals. In the later case a special, small PDMA
  is tasked to act as a bridge between the PSI-L fabric and the legacy
  peripheral.

  PDMAs can be configured via UDMAP peer registers to match with the
  configuration of the legacy peripheral.

allOf:
  - $ref: "../dma-controller.yaml#"

properties:
  "#dma-cells":
    minimum: 1
    maximum: 2
    description: |
      The cell is the PSI-L  thread ID of the remote (to UDMAP) end.
      Valid ranges for thread ID depends on the data movement direction:
      for source thread IDs (rx): 0 - 0x7fff
      for destination thread IDs (tx): 0x8000 - 0xffff

      Please refer to the device documentation for the PSI-L thread map and also
      the PSI-L peripheral chapter for the correct thread ID.

      When #dma-cells is 2, the second parameter is the channel ATYPE.

  compatible:
    enum:
      - ti,am654-navss-main-udmap
      - ti,am654-navss-mcu-udmap
      - ti,j721e-navss-main-udmap
      - ti,j721e-navss-mcu-udmap

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: gcfg
      - const: rchanrt
      - const: tchanrt

  msi-parent: true

  ti,sci:
    description: phandle to TI-SCI compatible System controller node
    $ref: /schemas/types.yaml#/definitions/phandle

  ti,sci-dev-id:
    description: TI-SCI device id of UDMAP
    $ref: /schemas/types.yaml#/definitions/uint32

  ti,ringacc:
    description: phandle to the ring accelerator node
    $ref: /schemas/types.yaml#/definitions/phandle

  ti,sci-rm-range-tchan:
    description: |
      Array of UDMA tchan resource subtypes for resource allocation for this
      host
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    # Should be enough
    maxItems: 255

  ti,sci-rm-range-rchan:
    description: |
      Array of UDMA rchan resource subtypes for resource allocation for this
      host
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    # Should be enough
    maxItems: 255

  ti,sci-rm-range-rflow:
    description: |
      Array of UDMA rflow resource subtypes for resource allocation for this
      host
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    # Should be enough
    maxItems: 255

required:
  - compatible
  - "#dma-cells"
  - reg
  - reg-names
  - msi-parent
  - ti,sci
  - ti,sci-dev-id
  - ti,ringacc
  - ti,sci-rm-range-tchan
  - ti,sci-rm-range-rchan
  - ti,sci-rm-range-rflow

if:
  properties:
    "#dma-cells":
      const: 2
then:
  properties:
    ti,udma-atype:
      description: ATYPE value which should be used by non slave channels
      $ref: /schemas/types.yaml#/definitions/uint32

  required:
    - ti,udma-atype

unevaluatedProperties: false

examples:
  - |+
    cbass_main {
        #address-cells = <2>;
        #size-cells = <2>;

        cbass_main_navss: navss@30800000 {
            compatible = "simple-mfd";
            #address-cells = <2>;
            #size-cells = <2>;
            dma-coherent;
            dma-ranges;
            ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;

            ti,sci-dev-id = <118>;

            main_udmap: dma-controller@31150000 {
                compatible = "ti,am654-navss-main-udmap";
                reg = <0x0 0x31150000 0x0 0x100>,
                      <0x0 0x34000000 0x0 0x100000>,
                      <0x0 0x35000000 0x0 0x100000>;
                reg-names = "gcfg", "rchanrt", "tchanrt";
                #dma-cells = <1>;

                ti,ringacc = <&ringacc>;

                msi-parent = <&inta_main_udmass>;

                ti,sci = <&dmsc>;
                ti,sci-dev-id = <188>;

                ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
                                        <0x2>; /* TX_CHAN */
                ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
                                        <0x5>; /* RX_CHAN */
                ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
            };
        };
    };


code:
Xilinx AXI VDMA engine, it does transfers between memory and video devices.
It can be configured to have one channel or two channels. If configured
as two channels, one is to transmit to the video device and another is
to receive from the video device.

Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
target devices. It can be configured to have one channel or two channels.
If configured as two channels, one is to transmit to the device and another
is to receive from the device.

Xilinx AXI CDMA engine, it does transfers between memory-mapped source
address and a memory-mapped destination address.

Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
target devices. It can be configured to have up to 16 independent transmit
and receive channels.

Required properties:
- compatible: Should be one of-
		"xlnx,axi-vdma-1.00.a"
		"xlnx,axi-dma-1.00.a"
		"xlnx,axi-cdma-1.00.a"
		"xlnx,axi-mcdma-1.00.a"
- #dma-cells: Should be <1>, see "dmas" property below
- reg: Should contain VDMA registers location and length.
- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
- dma-channel child node: Should have at least one channel and can have up to
	two channels per device. This node specifies the properties of each
	DMA channel (see child node properties below).
- clocks: Input clock specifier. Refer to common clock bindings.
- clock-names: List of input clocks
	For VDMA:
	Required elements: "s_axi_lite_aclk"
	Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
			   "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
	For CDMA:
	Required elements: "s_axi_lite_aclk", "m_axi_aclk"
	For AXIDMA and MCDMA:
	Required elements: "s_axi_lite_aclk"
	Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
			   "m_axi_sg_aclk"

Required properties for VDMA:
- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.

Optional properties for AXI DMA and MCDMA:
- xlnx,sg-length-width: Should be set to the width in bits of the length
	register as configured in h/w. Takes values {8...26}. If the property
	is missing or invalid then the default value 23 is used. This is the
	maximum value that is supported by all IP versions.
Optional properties for VDMA:
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
	It takes following values:
	{1}, flush both channels
	{2}, flush mm2s channel
	{3}, flush s2mm channel

Required child node properties:
- compatible:
	For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
	"xlnx,axi-vdma-s2mm-channel".
	For CDMA: It should be "xlnx,axi-cdma-channel".
	For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel"
	or "xlnx,axi-dma-s2mm-channel".
- interrupts: Should contain per channel VDMA interrupts.
- xlnx,datawidth: Should contain the stream data width, take values
	{32,64...1024}.

Optional child node properties:
- xlnx,include-dre: Tells hardware is configured for Data
	Realignment Engine.
Optional child node properties for VDMA:
- xlnx,genlock-mode: Tells Genlock synchronization is
	enabled/disabled in hardware.
- xlnx,enable-vert-flip: Tells vertical flip is
	enabled/disabled in hardware(S2MM path).
Optional child node properties for MCDMA:
- dma-channels: Number of dma channels in child node.

Example:
++++++++

axi_vdma_0: axivdma@40030000 {
	compatible = "xlnx,axi-vdma-1.00.a";
	#dma_cells = <1>;
	reg = < 0x40030000 0x10000 >;
	dma-ranges = <0x00000000 0x00000000 0x40000000>;
	xlnx,num-fstores = <0x8>;
	xlnx,flush-fsync = <0x1>;
	xlnx,addrwidth = <0x20>;
	clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
	clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
		      "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
	dma-channel@40030000 {
		compatible = "xlnx,axi-vdma-mm2s-channel";
		interrupts = < 0 54 4 >;
		xlnx,datawidth = <0x40>;
	} ;
	dma-channel@40030030 {
		compatible = "xlnx,axi-vdma-s2mm-channel";
		interrupts = < 0 53 4 >;
		xlnx,datawidth = <0x40>;
	} ;
} ;

* DMA client

Required properties:
- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
	where Channel ID is '0' for write/tx and '1' for read/rx
	channel. For MCMDA, MM2S channel(write/tx) ID start from
	'0' and is in [0-15] range. S2MM channel(read/rx) ID start
	from '16' and is in [16-31] range. These channels ID are
	fixed irrespective of IP configuration.

- dma-names: a list of DMA channel names, one per "dmas" entry

Example:
++++++++

vdmatest_0: vdmatest@0 {
	compatible ="xlnx,axi-vdma-test-1.00.a";
	dmas = <&axi_vdma_0 0
		&axi_vdma_0 1>;
	dma-names = "vdma0", "vdma1";
} ;


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx ZynqMP DMA Engine

description: |
  The Xilinx ZynqMP DMA engine supports memory to memory transfers,
  memory to device and device to memory transfers. It also has flow
  control and rate control support for slave/peripheral dma access.

maintainers:
  - Michael Tretter <m.tretter@pengutronix.de>

allOf:
  - $ref: "../dma-controller.yaml#"

properties:
  "#dma-cells":
    const: 1

  compatible:
    const: xlnx,zynqmp-dma-1.0

  reg:
    description: memory map for gdma/adma module access
    maxItems: 1

  interrupts:
    description: DMA channel interrupt
    maxItems: 1

  clocks:
    description: input clocks
    minItems: 2
    maxItems: 2

  clock-names:
    items:
      - const: clk_main
      - const: clk_apb

  xlnx,bus-width:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum:
      - 64
      - 128
    description: AXI bus width in bits

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

  dma-coherent:
    description: present if dma operations are coherent

required:
  - "#dma-cells"
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>

    fpd_dma_chan1: dma-controller@fd500000 {
      compatible = "xlnx,zynqmp-dma-1.0";
      reg = <0xfd500000 0x1000>;
      interrupt-parent = <&gic>;
      interrupts = <0 117 0x4>;
      #dma-cells = <1>;
      clock-names = "clk_main", "clk_apb";
      clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
      xlnx,bus-width = <128>;
      dma-coherent;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings

description: |
  These bindings describe the DMA engine included in the Xilinx ZynqMP
  DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
  channels for a video stream, 1 channel for a graphics stream, and 2 channels
  for an audio stream).

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

allOf:
  - $ref: "../dma-controller.yaml#"

properties:
  "#dma-cells":
    const: 1
    description: |
      The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
      for a list of channel IDs).

  compatible:
    const: xlnx,zynqmp-dpdma

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    description: The AXI clock
    maxItems: 1

  clock-names:
    const: axi_clk

required:
  - "#dma-cells"
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    dma: dma-controller@fd4c0000 {
      compatible = "xlnx,zynqmp-dpdma";
      reg = <0xfd4c0000 0x1000>;
      interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-parent = <&gic>;
      clocks = <&dpdma_clk>;
      clock-names = "axi_clk";
      #dma-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8 DSP core

maintainers:
  - Daniel Baluta <daniel.baluta@nxp.com>
  - Shengjiu Wang <shengjiu.wang@nxp.com>

description: |
  Some boards from i.MX8 family contain a DSP core used for
  advanced pre- and post- audio processing.

properties:
  compatible:
    enum:
      - fsl,imx8qxp-dsp
      - fsl,imx8qm-dsp
      - fsl,imx8mp-dsp
      - fsl,imx8ulp-dsp
      - fsl,imx8qxp-hifi4
      - fsl,imx8qm-hifi4
      - fsl,imx8mp-hifi4
      - fsl,imx8ulp-hifi4

  reg:
    maxItems: 1

  clocks:
    items:
      - description: ipg clock
      - description: ocram clock
      - description: core clock
      - description: debug interface clock
      - description: message unit clock
    minItems: 3

  clock-names:
    items:
      - const: ipg
      - const: ocram
      - const: core
      - const: debug
      - const: mu
    minItems: 3

  power-domains:
    description:
      List of phandle and PM domain specifier as documented in
      Documentation/devicetree/bindings/power/power_domain.txt
    minItems: 1
    maxItems: 4

  mboxes:
    description:
      List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
      or - 1 channel for TX, 1 channel for RX, 1 channel for RXDB
      (see mailbox/fsl,mu.txt)
    minItems: 3
    maxItems: 4

  mbox-names:
    minItems: 3
    maxItems: 4

  memory-region:
    description:
      phandle to a node describing reserved memory (System RAM memory)
      used by DSP (see bindings/reserved-memory/reserved-memory.txt)
    minItems: 1
    maxItems: 4

  firmware-name:
    description: |
      Default name of the firmware to load to the remote processor.

  fsl,dsp-ctrl:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to syscon block which provide access for processor enablement

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains
  - mboxes
  - mbox-names
  - memory-region

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,imx8qxp-dsp
              - fsl,imx8qm-dsp
              - fsl,imx8qxp-hifi4
              - fsl,imx8qm-hifi4
    then:
      properties:
        power-domains:
          minItems: 4
    else:
      properties:
        power-domains:
          maxItems: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,imx8qxp-hifi4
              - fsl,imx8qm-hifi4
              - fsl,imx8mp-hifi4
              - fsl,imx8ulp-hifi4
    then:
      properties:
        memory-region:
          minItems: 4
        mboxes:
          maxItems: 3
        mbox-names:
          items:
            - const: tx
            - const: rx
            - const: rxdb
    else:
      properties:
        memory-region:
          maxItems: 1
        mboxes:
          minItems: 4
        mbox-names:
          items:
            - const: txdb0
            - const: txdb1
            - const: rxdb0
            - const: rxdb1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/firmware/imx/rsrc.h>
    #include <dt-bindings/clock/imx8-clock.h>
    dsp@596e8000 {
        compatible = "fsl,imx8qxp-dsp";
        reg = <0x596e8000 0x88000>;
        clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
                 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
                 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
        clock-names = "ipg", "ocram", "core";
        power-domains = <&pd IMX_SC_R_MU_13A>,
                        <&pd IMX_SC_R_MU_13B>,
                        <&pd IMX_SC_R_DSP>,
                        <&pd IMX_SC_R_DSP_RAM>;
        mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
        mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
        memory-region = <&dsp_reserved>;
    };
  - |
    #include <dt-bindings/clock/imx8mp-clock.h>
    dsp_reserved: dsp@92400000 {
      reg = <0x92400000 0x1000000>;
      no-map;
    };
    dsp_vdev0vring0: vdev0vring0@942f0000 {
      reg = <0x942f0000 0x8000>;
      no-map;
    };
    dsp_vdev0vring1: vdev0vring1@942f8000 {
      reg = <0x942f8000 0x8000>;
      no-map;
    };
    dsp_vdev0buffer: vdev0buffer@94300000 {
      compatible = "shared-dma-pool";
      reg = <0x94300000 0x100000>;
      no-map;
    };

    dsp: dsp@3b6e8000 {
      compatible = "fsl,imx8mp-hifi4";
      reg = <0x3b6e8000 0x88000>;
      clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
               <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>,
               <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
               <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>;
      clock-names = "ipg", "ocram", "core", "debug";
      firmware-name = "imx/dsp/hifi4.bin";
      power-domains = <&audiomix_pd>;
      mbox-names = "tx", "rx", "rxdb";
      mboxes = <&mu2 0 0>,
               <&mu2 1 0>,
               <&mu2 3 0>;
      memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
                      <&dsp_vdev0vring1>, <&dsp_reserved>;
      fsl,dsp-ctrl = <&audio_blk_ctrl>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dsp/mediatek,mt8186-dsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek mt8186 DSP core

maintainers:
  - Tinghan Shen <tinghan.shen@mediatek.com>

description: |
  MediaTek mt8186 SoC contains a DSP core used for
  advanced pre- and post- audio processing.

properties:
  compatible:
    const: mediatek,mt8186-dsp

  reg:
    items:
      - description: Address and size of the DSP config registers
      - description: Address and size of the DSP SRAM
      - description: Address and size of the DSP secure registers
      - description: Address and size of the DSP bus registers

  reg-names:
    items:
      - const: cfg
      - const: sram
      - const: sec
      - const: bus

  clocks:
    items:
      - description: mux for audio dsp clock
      - description: mux for audio dsp local bus

  clock-names:
    items:
      - const: audiodsp
      - const: adsp_bus

  power-domains:
    maxItems: 1

  mboxes:
    items:
      - description: mailbox for receiving audio DSP requests.
      - description: mailbox for transmitting requests to audio DSP.

  mbox-names:
    items:
      - const: rx
      - const: tx

  memory-region:
    items:
      - description: dma buffer between host and DSP.
      - description: DSP system memory.

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - power-domains
  - mbox-names
  - mboxes

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8186-clk.h>
    dsp@10680000 {
        compatible = "mediatek,mt8186-dsp";
        reg = <0x10680000 0x2000>,
              <0x10800000 0x100000>,
              <0x1068b000 0x100>,
              <0x1068f000 0x1000>;
        reg-names = "cfg", "sram", "sec", "bus";
        clocks = <&topckgen CLK_TOP_AUDIODSP>,
                 <&topckgen CLK_TOP_ADSP_BUS>;
        clock-names = "audiodsp",
                      "adsp_bus";
        power-domains = <&spm 6>;
        mbox-names = "rx", "tx";
        mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dsp/mediatek,mt8195-dsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek mt8195 DSP core

maintainers:
  - YC Hung <yc.hung@mediatek.com>

description: |
  Some boards from mt8195 contain a DSP core used for
  advanced pre- and post- audio processing.

properties:
  compatible:
    const: mediatek,mt8195-dsp

  reg:
    items:
      - description: Address and size of the DSP Cfg registers
      - description: Address and size of the DSP SRAM

  reg-names:
    items:
      - const: cfg
      - const: sram

  clocks:
    items:
      - description: mux for audio dsp clock
      - description: 26M clock
      - description: mux for audio dsp local bus
      - description: default audio dsp local bus clock source
      - description: clock gate for audio dsp clock
      - description: mux for audio dsp access external bus

  clock-names:
    items:
      - const: adsp_sel
      - const: clk26m_ck
      - const: audio_local_bus
      - const: mainpll_d7_d2
      - const: scp_adsp_audiodsp
      - const: audio_h

  power-domains:
    maxItems: 1

  mboxes:
    items:
      - description: mailbox for receiving audio DSP requests.
      - description: mailbox for transmitting requests to audio DSP.

  mbox-names:
    items:
      - const: rx
      - const: tx

  memory-region:
    items:
      - description: dma buffer between host and DSP.
      - description: DSP system memory.

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - memory-region
  - power-domains
  - mbox-names
  - mboxes

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    dsp@10803000 {
       compatible =  "mediatek,mt8195-dsp";
       reg = <0x10803000  0x1000>,
             <0x10840000  0x40000>;
       reg-names = "cfg", "sram";
       clocks = <&topckgen 10>, //CLK_TOP_ADSP
                <&clk26m>,
                <&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS
                <&topckgen 136>, //CLK_TOP_MAINPLL_D7_D2
                <&scp_adsp 0>, //CLK_SCP_ADSP_AUDIODSP
                <&topckgen 34>; //CLK_TOP_AUDIO_H
       clock-names = "adsp_sel",
                     "clk26m_ck",
                     "audio_local_bus",
                     "mainpll_d7_d2",
                     "scp_adsp_audiodsp",
                     "audio_h";
       memory-region = <&adsp_dma_mem_reserved>,
                       <&adsp_mem_reserved>;
       power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP
       mbox-names = "rx", "tx";
       mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic performance domains

maintainers:
  - Sudeep Holla <sudeep.holla@arm.com>

description: |+
  This binding is intended for performance management of groups of devices or
  CPUs that run in the same performance domain. Performance domains must not
  be confused with power domains. A performance domain is defined by a set
  of devices that always have to run at the same performance level. For a given
  performance domain, there is a single point of control that affects all the
  devices in the domain, making it impossible to set the performance level of
  an individual device in the domain independently from other devices in
  that domain. For example, a set of CPUs that share a voltage domain, and
  have a common frequency control, is said to be in the same performance
  domain.

  This device tree binding can be used to bind performance domain consumer
  devices with their performance domains provided by performance domain
  providers. A performance domain provider can be represented by any node in
  the device tree and can provide one or more performance domains. A consumer
  node can refer to the provider by a phandle and a set of phandle arguments
  (so called performance domain specifiers) of length specified by the
  \#performance-domain-cells property in the performance domain provider node.

select: true

properties:
  "#performance-domain-cells":
    description:
      Number of cells in a performance domain specifier. Typically 0 for nodes
      representing a single performance domain and 1 for nodes providing
      multiple performance domains (e.g. performance controllers), but can be
      any value as specified by device tree binding documentation of particular
      provider.
    enum: [ 0, 1 ]

  performance-domains:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    description:
      A phandle and performance domain specifier as defined by bindings of the
      performance controller/provider specified by phandle.

additionalProperties: true

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        performance: performance-controller@11bc00 {
            compatible = "mediatek,cpufreq-hw";
            reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;

            #performance-domain-cells = <1>;
        };
    };

    // The node above defines a performance controller that is a performance
    // domain provider and expects one cell as its phandle argument.

    cpus {
        #address-cells = <2>;
        #size-cells = <0>;

        cpu@0 {
            device_type = "cpu";
            compatible = "arm,cortex-a57";
            reg = <0x0 0x0>;
            performance-domains = <&performance 1>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/edac/amazon,al-mc-edac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amazon's Annapurna Labs Memory Controller EDAC

maintainers:
  - Talel Shenhar <talel@amazon.com>
  - Talel Shenhar <talelshenhar@gmail.com>

description: |
  EDAC node is defined to describe on-chip error detection and correction for
  Amazon's Annapurna Labs Memory Controller.

properties:

  compatible:
    const: amazon,al-mc-edac

  reg:
    maxItems: 1

  "#address-cells":
    const: 2

  "#size-cells":
    const: 2

  interrupts:
    minItems: 1
    items:
      - description: uncorrectable error interrupt
      - description: correctable error interrupt

  interrupt-names:
    minItems: 1
    items:
      - const: ue
      - const: ce

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    soc {
        #address-cells = <2>;
        #size-cells = <2>;
        edac@f0080000 {
          #address-cells = <2>;
          #size-cells = <2>;
          compatible = "amazon,al-mc-edac";
          reg = <0x0 0xf0080000 0x0 0x00010000>;
          interrupt-parent = <&amazon_al_system_fabric>;
          interrupt-names = "ue";
          interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
        };
    };


code:
* APM X-Gene SoC EDAC node

EDAC node is defined to describe on-chip error detection and correction.
The follow error types are supported:

  memory controller	- Memory controller
  PMD (L1/L2)		- Processor module unit (PMD) L1/L2 cache
  L3			- L3 cache controller
  SoC			- SoC IP's such as Ethernet, SATA, and etc

The following section describes the EDAC DT node binding.

Required properties:
- compatible		: Shall be "apm,xgene-edac".
- regmap-csw		: Regmap of the CPU switch fabric (CSW) resource.
- regmap-mcba		: Regmap of the MCB-A (memory bridge) resource.
- regmap-mcbb		: Regmap of the MCB-B (memory bridge) resource.
- regmap-efuse		: Regmap of the PMD efuse resource.
- regmap-rb		: Regmap of the register bus resource. This property
			  is optional only for compatibility. If the RB
			  error conditions are not cleared, it will
			  continuously generate interrupt.
- reg			: First resource shall be the CPU bus (PCP) resource.
- interrupts            : Interrupt-specifier for MCU, PMD, L3, or SoC error
			  IRQ(s).

Required properties for memory controller subnode:
- compatible		: Shall be "apm,xgene-edac-mc".
- reg			: First resource shall be the memory controller unit
                          (MCU) resource.
- memory-controller	: Instance number of the memory controller.

Required properties for PMD subnode:
- compatible		: Shall be "apm,xgene-edac-pmd" or
                          "apm,xgene-edac-pmd-v2".
- reg			: First resource shall be the PMD resource.
- pmd-controller	: Instance number of the PMD controller.

Required properties for L3 subnode:
- compatible		: Shall be "apm,xgene-edac-l3" or
                          "apm,xgene-edac-l3-v2".
- reg			: First resource shall be the L3 EDAC resource.

Required properties for SoC subnode:
- compatible		: Shall be "apm,xgene-edac-soc-v1" for revision 1 or
                          "apm,xgene-edac-l3-soc" for general value reporting
                          only.
- reg			: First resource shall be the SoC EDAC resource.

Example:
	csw: csw@7e200000 {
		compatible = "apm,xgene-csw", "syscon";
		reg = <0x0 0x7e200000 0x0 0x1000>;
	};

	mcba: mcba@7e700000 {
		compatible = "apm,xgene-mcb", "syscon";
		reg = <0x0 0x7e700000 0x0 0x1000>;
	};

	mcbb: mcbb@7e720000 {
		compatible = "apm,xgene-mcb", "syscon";
		reg = <0x0 0x7e720000 0x0 0x1000>;
	};

	efuse: efuse@1054a000 {
		compatible = "apm,xgene-efuse", "syscon";
		reg = <0x0 0x1054a000 0x0 0x20>;
	};

	rb: rb@7e000000 {
		compatible = "apm,xgene-rb", "syscon";
		reg = <0x0 0x7e000000 0x0 0x10>;
	};

	edac@78800000 {
		compatible = "apm,xgene-edac";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		regmap-csw = <&csw>;
		regmap-mcba = <&mcba>;
		regmap-mcbb = <&mcbb>;
		regmap-efuse = <&efuse>;
		regmap-rb = <&rb>;
		reg = <0x0 0x78800000 0x0 0x100>;
		interrupts = <0x0 0x20 0x4>,
			     <0x0 0x21 0x4>,
			     <0x0 0x27 0x4>;

		edacmc@7e800000 {
			compatible = "apm,xgene-edac-mc";
			reg = <0x0 0x7e800000 0x0 0x1000>;
			memory-controller = <0>;
		};

		edacpmd@7c000000 {
			compatible = "apm,xgene-edac-pmd";
			reg = <0x0 0x7c000000 0x0 0x200000>;
			pmd-controller = <0>;
		};

		edacl3@7e600000 {
			compatible = "apm,xgene-edac-l3";
			reg = <0x0 0x7e600000 0x0 0x1000>;
		};

		edacsoc@7e930000 {
			compatible = "apm,xgene-edac-soc-v1";
			reg = <0x0 0x7e930000 0x0 0x1000>;
		};
	};


code:
Aspeed BMC SoC EDAC node

The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
correction check).

The memory controller supports SECDED (single bit error correction, double bit
error detection) and single bit error auto scrubbing by reserving 8 bits for
every 64 bit word (effectively reducing available memory to 8/9).

Note, the bootloader must configure ECC mode in the memory controller.

Required properties:
- compatible: should be one of
	- "aspeed,ast2400-sdram-edac"
	- "aspeed,ast2500-sdram-edac"
	- "aspeed,ast2600-sdram-edac"
- reg:        sdram controller register set should be <0x1e6e0000 0x174>
- interrupts: should be AVIC interrupt #0

Example:

	edac: sdram@1e6e0000 {
		compatible = "aspeed,ast2500-sdram-edac";
		reg = <0x1e6e0000 0x174>;
		interrupts = <0>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/edac/dmc-520.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM DMC-520 EDAC bindings

maintainers:
  - Lei Wang <lewan@microsoft.com>

description: |+
  DMC-520 node is defined to describe DRAM error detection and correction.

  https://static.docs.arm.com/100000/0200/corelink_dmc520_trm_100000_0200_01_en.pdf

properties:
  compatible:
    items:
      - const: brcm,dmc-520
      - const: arm,dmc-520

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 10

  interrupt-names:
    minItems: 1
    maxItems: 10
    items:
      enum:
        - ram_ecc_errc
        - ram_ecc_errd
        - dram_ecc_errc
        - dram_ecc_errd
        - failed_access
        - failed_prog
        - link_err
        - temperature_event
        - arch_fsm
        - phy_request

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    dmc0: dmc@200000 {
        compatible = "brcm,dmc-520", "arm,dmc-520";
        reg = <0x200000 0x80000>;
        interrupts = <0x0 0x349 0x4>, <0x0 0x34B 0x4>;
        interrupt-names = "dram_ecc_errc", "dram_ecc_errd";
    };


code:
Altera SoCFPGA ECC Manager
This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
The ECC Manager counts and corrects single bit errors and counts/handles
double bit errors which are uncorrectable.

Cyclone5 and Arria5 ECC Manager
Required Properties:
- compatible : Should be "altr,socfpga-ecc-manager"
- #address-cells: must be 1
- #size-cells: must be 1
- ranges : standard definition, should translate from local addresses

Subcomponents:

L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt. Note the rising edge type.

On Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-ocram-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- iram : phandle to On-Chip RAM definition.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt. Note the rising edge type.

Example:

	eccmgr: eccmgr@ffd08140 {
		compatible = "altr,socfpga-ecc-manager";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		l2-ecc@ffd08140 {
			compatible = "altr,socfpga-l2-ecc";
			reg = <0xffd08140 0x4>;
			interrupts = <0 36 1>, <0 37 1>;
		};

		ocram-ecc@ffd08144 {
			compatible = "altr,socfpga-ocram-ecc";
			reg = <0xffd08144 0x4>;
			iram = <&ocram>;
			interrupts = <0 178 1>, <0 179 1>;
		};
	};

Arria10 SoCFPGA ECC Manager
The Arria10 SoC ECC Manager handles the IRQs for each peripheral
in a shared register instead of individual IRQs like the Cyclone5
and Arria5. Therefore the device tree is different as well.

Required Properties:
- compatible : Should be "altr,socfpga-a10-ecc-manager"
- altr,sysgr-syscon : phandle to Arria10 System Manager Block
	containing the ECC manager registers.
- #address-cells: must be 1
- #size-cells: must be 1
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt.
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
- #interrupt-cells : must be set to 2.
- ranges : standard definition, should translate from local addresses

Subcomponents:

L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

On-Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-ocram-ecc"
- reg        : Address and size for ECC block registers.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

Ethernet FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-eth-mac-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent Ethernet node.
- interrupts      : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

NAND FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-nand-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent NAND node.
- interrupts      : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

DMA FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-dma-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent DMA node.
- interrupts      : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

USB FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-usb-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent USB node.
- interrupts      : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

QSPI FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-qspi-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent QSPI node.
- interrupts      : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

SDMMC FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-sdmmc-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent SD/MMC node.
- interrupts      : Should be single bit error interrupt, then double bit error
	interrupt, in this order for port A, and then single bit error interrupt,
	then double bit error interrupt in this order for port B.

Example:

	eccmgr: eccmgr@ffd06000 {
		compatible = "altr,socfpga-a10-ecc-manager";
		altr,sysmgr-syscon = <&sysmgr>;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
			     <0 0 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ranges;

		l2-ecc@ffd06010 {
			compatible = "altr,socfpga-a10-l2-ecc";
			reg = <0xffd06010 0x4>;
			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
				     <32 IRQ_TYPE_LEVEL_HIGH>;
		};

		ocram-ecc@ff8c3000 {
			compatible = "altr,socfpga-a10-ocram-ecc";
			reg = <0xff8c3000 0x90>;
			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
				     <33 IRQ_TYPE_LEVEL_HIGH> ;
		};

		emac0-rx-ecc@ff8c0800 {
			compatible = "altr,socfpga-eth-mac-ecc";
			reg = <0xff8c0800 0x400>;
			altr,ecc-parent = <&gmac0>;
			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
				     <36 IRQ_TYPE_LEVEL_HIGH>;
		};

		emac0-tx-ecc@ff8c0c00 {
			compatible = "altr,socfpga-eth-mac-ecc";
			reg = <0xff8c0c00 0x400>;
			altr,ecc-parent = <&gmac0>;
			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
				     <37 IRQ_TYPE_LEVEL_HIGH>;
		};

		nand-buf-ecc@ff8c2000 {
			compatible = "altr,socfpga-nand-ecc";
			reg = <0xff8c2000 0x400>;
			altr,ecc-parent = <&nand>;
			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
				     <43 IRQ_TYPE_LEVEL_HIGH>;
		};

		nand-rd-ecc@ff8c2400 {
			compatible = "altr,socfpga-nand-ecc";
			reg = <0xff8c2400 0x400>;
			altr,ecc-parent = <&nand>;
			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
				     <45 IRQ_TYPE_LEVEL_HIGH>;
		};

		nand-wr-ecc@ff8c2800 {
			compatible = "altr,socfpga-nand-ecc";
			reg = <0xff8c2800 0x400>;
			altr,ecc-parent = <&nand>;
			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
				     <44 IRQ_TYPE_LEVEL_HIGH>;
		};

		dma-ecc@ff8c8000 {
			compatible = "altr,socfpga-dma-ecc";
			reg = <0xff8c8000 0x400>;
			altr,ecc-parent = <&pdma>;
			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
				     <42 IRQ_TYPE_LEVEL_HIGH>;

		usb0-ecc@ff8c8800 {
			compatible = "altr,socfpga-usb-ecc";
			reg = <0xff8c8800 0x400>;
			altr,ecc-parent = <&usb0>;
			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
				     <34 IRQ_TYPE_LEVEL_HIGH>;
		};

		qspi-ecc@ff8c8400 {
			compatible = "altr,socfpga-qspi-ecc";
			reg = <0xff8c8400 0x400>;
			altr,ecc-parent = <&qspi>;
			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
				     <46 IRQ_TYPE_LEVEL_HIGH>;
		};

		sdmmc-ecc@ff8c2c00 {
			compatible = "altr,socfpga-sdmmc-ecc";
			reg = <0xff8c2c00 0x400>;
			altr,ecc-parent = <&mmc>;
			interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
				     <47 IRQ_TYPE_LEVEL_HIGH>,
				     <16 IRQ_TYPE_LEVEL_HIGH>,
				     <48 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

Stratix10 SoCFPGA ECC Manager (ARM64)
The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
in a shared register similar to the Arria10. However, Stratix10 ECC
requires access to registers that can only be read from Secure Monitor
with SMC calls. Therefore the device tree is slightly different. Note
that only 1 interrupt is sent in Stratix10 because the double bit errors
are treated as SErrors in ARM64 instead of IRQs in ARM32.

Required Properties:
- compatible : Should be "altr,socfpga-s10-ecc-manager"
- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
	              containing the ECC manager registers.
- interrupts : Should be single bit error interrupt.
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
- #interrupt-cells : must be set to 2.
- #address-cells: must be 1
- #size-cells: must be 1
- ranges : standard definition, should translate from local addresses

Subcomponents:

SDRAM ECC
Required Properties:
- compatible : Should be "altr,sdram-edac-s10"
- interrupts : Should be single bit error interrupt.

On-Chip RAM ECC
Required Properties:
- compatible      : Should be "altr,socfpga-s10-ocram-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent OCRAM node.
- interrupts      : Should be single bit error interrupt.

Ethernet FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-s10-eth-mac-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent Ethernet node.
- interrupts      : Should be single bit error interrupt.

NAND FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-s10-nand-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent NAND node.
- interrupts      : Should be single bit error interrupt.

DMA FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-s10-dma-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent DMA node.
- interrupts      : Should be single bit error interrupt.

USB FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-s10-usb-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent USB node.
- interrupts      : Should be single bit error interrupt.

SDMMC FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-s10-sdmmc-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent SD/MMC node.
- interrupts      : Should be single bit error interrupt for port A
		    and then single bit error interrupt for port B.

Example:

	eccmgr {
		compatible = "altr,socfpga-s10-ecc-manager";
		altr,sysmgr-syscon = <&sysmgr>;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupts = <0 15 4>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ranges;

		sdramedac {
			compatible = "altr,sdram-edac-s10";
			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
		};

		ocram-ecc@ff8cc000 {
			compatible = "altr,socfpga-s10-ocram-ecc";
			reg = <ff8cc000 0x100>;
			altr,ecc-parent = <&ocram>;
			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
		};

		emac0-rx-ecc@ff8c0000 {
			compatible = "altr,socfpga-s10-eth-mac-ecc";
			reg = <0xff8c0000 0x100>;
			altr,ecc-parent = <&gmac0>;
			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
		};

		emac0-tx-ecc@ff8c0400 {
			compatible = "altr,socfpga-s10-eth-mac-ecc";
			reg = <0xff8c0400 0x100>;
			altr,ecc-parent = <&gmac0>;
			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
		};

		nand-buf-ecc@ff8c8000 {
			compatible = "altr,socfpga-s10-nand-ecc";
			reg = <0xff8c8000 0x100>;
			altr,ecc-parent = <&nand>;
			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
		};

		nand-rd-ecc@ff8c8400 {
			compatible = "altr,socfpga-s10-nand-ecc";
			reg = <0xff8c8400 0x100>;
			altr,ecc-parent = <&nand>;
			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
		};

		nand-wr-ecc@ff8c8800 {
			compatible = "altr,socfpga-s10-nand-ecc";
			reg = <0xff8c8800 0x100>;
			altr,ecc-parent = <&nand>;
			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
		};

		dma-ecc@ff8c9000 {
			compatible = "altr,socfpga-s10-dma-ecc";
			reg = <0xff8c9000 0x100>;
			altr,ecc-parent = <&pdma>;
			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;

		usb0-ecc@ff8c4000 {
			compatible = "altr,socfpga-s10-usb-ecc";
			reg = <0xff8c4000 0x100>;
			altr,ecc-parent = <&usb0>;
			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
		};

		sdmmc-ecc@ff8c8c00 {
			compatible = "altr,socfpga-s10-sdmmc-ecc";
			reg = <0xff8c8c00 0x100>;
			altr,ecc-parent = <&mmc>;
			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
				     <15 IRQ_TYPE_LEVEL_HIGH>;
		};
	};


code:
# SPDX-License-Identifier: GPL-2.0-only
# Copyright 2019 BayLibre SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/eeprom/at24.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: I2C EEPROMs compatible with Atmel's AT24

maintainers:
  - Bartosz Golaszewski <bgolaszewski@baylibre.com>

allOf:
  - $ref: /schemas/nvmem/nvmem.yaml

select:
  properties:
    compatible:
      contains:
        pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
  required:
    - compatible

properties:
  $nodename:
    pattern: "^eeprom@[0-9a-f]{1,2}$"

  # There are multiple known vendors who manufacture EEPROM chips compatible
  # with Atmel's AT24. The compatible string requires either a single item
  # if the memory comes from Atmel (in which case the vendor part must be
  # 'atmel') or two items with the same 'model' part where the vendor part of
  # the first one is the actual manufacturer and the second item is the
  # corresponding 'atmel,<model>' from Atmel.
  compatible:
    oneOf:
      - allOf:
          - minItems: 1
            items:
              - pattern: "^(atmel|catalyst|microchip|nxp|ramtron|renesas|rohm|st),(24(c|cs|lc|mac)[0-9]+|spd)$"
              - pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
          - oneOf:
              - items:
                  pattern: c00$
              - items:
                  pattern: c01$
              - items:
                  pattern: cs01$
              - items:
                  pattern: c02$
              - items:
                  pattern: cs02$
              - items:
                  pattern: mac402$
              - items:
                  pattern: mac602$
              - items:
                  pattern: c04$
              - items:
                  pattern: cs04$
              - items:
                  pattern: c08$
              - items:
                  pattern: cs08$
              - items:
                  pattern: c16$
              - items:
                  pattern: cs16$
              - items:
                  pattern: c32$
              - items:
                  pattern: cs32$
              - items:
                  pattern: c64$
              - items:
                  pattern: cs64$
              - items:
                  pattern: c128$
              - items:
                  pattern: cs128$
              - items:
                  pattern: c256$
              - items:
                  pattern: cs256$
              - items:
                  pattern: c512$
              - items:
                  pattern: cs512$
              - items:
                  pattern: c1024$
              - items:
                  pattern: cs1024$
              - items:
                  pattern: c1025$
              - items:
                  pattern: cs1025$
              - items:
                  pattern: c2048$
              - items:
                  pattern: cs2048$
              - items:
                  pattern: spd$
      # These are special cases that don't conform to the above pattern.
      # Each requires a standard at24 model as fallback.
      - items:
          - enum:
              - rohm,br24g01
              - rohm,br24t01
          - const: atmel,24c01
      - items:
          - enum:
              - nxp,se97b
              - renesas,r1ex24002
          - const: atmel,24c02
      - items:
          - enum:
              - onnn,cat24c04
              - onnn,cat24c05
          - const: atmel,24c04
      - items:
          - const: renesas,r1ex24016
          - const: atmel,24c16
      - items:
          - const: giantec,gt24c32a
          - const: atmel,24c32
      - items:
          - enum:
              - renesas,r1ex24128
              - samsung,s524ad0xd1
          - const: atmel,24c128

  label:
    description: Descriptive name of the EEPROM.

  reg:
    maxItems: 1

  pagesize:
    description:
      The length of the pagesize for writing. Please consult the
      manual of your device, that value varies a lot. A wrong value
      may result in data loss! If not specified, a safety value of
      '1' is used which will be very slow.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 8, 16, 32, 64, 128, 256]
    default: 1

  read-only:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Disables writes to the eeprom.

  size:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Total eeprom size in bytes.

  no-read-rollover:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Indicates that the multi-address eeprom does not automatically roll
      over reads to the next slave address. Please consult the manual of
      your device.

  wp-gpios: true

  address-width:
    description:
      Number of address bits.
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 8
    enum: [ 8, 16 ]

  num-addresses:
    description:
      Total number of i2c slave addresses this device takes.
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 1
    minimum: 1
    maximum: 8

  vcc-supply:
    description:
      phandle of the regulator that provides the supply voltage.

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      eeprom@52 {
          compatible = "microchip,24c32", "atmel,24c32";
          reg = <0x52>;
          pagesize = <32>;
          wp-gpios = <&gpio1 3 0>;
          num-addresses = <8>;
      };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: "http://devicetree.org/schemas/eeprom/at25.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: SPI EEPROMs or FRAMs compatible with Atmel's AT25

maintainers:
  - Christian Eggers <ceggers@arri.de>

properties:
  $nodename:
    anyOf:
      - pattern: "^eeprom@[0-9a-f]{1,2}$"
      - pattern: "^fram@[0-9a-f]{1,2}$"

  # There are multiple known vendors who manufacture EEPROM chips compatible
  # with Atmel's AT25. The compatible string requires two items where the
  # 'vendor' and 'model' parts of the first are the actual chip and the second
  # item is fixed to "atmel,at25". Some existing bindings only have the
  # "atmel,at25" part and should be fixed by somebody who knows vendor and
  # product.
  compatible:
    oneOf:
      - items:
          - enum:
              - anvo,anv32e61w
              - atmel,at25256B
              - fujitsu,mb85rs1mt
              - fujitsu,mb85rs64
              - microchip,at25160bn
              - microchip,25lc040
              - st,m95m02
              - st,m95256
              - cypress,fm25

          - const: atmel,at25

      # Please don't use this alternative for new bindings.
      - items:
          - const: atmel,at25

  reg:
    maxItems: 1

  pagesize:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072]
    description:
      Size of the eeprom page. FRAMs don't have pages.

  size:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Total eeprom size in bytes.

  address-width:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 8, 9, 16, 24 ]
    description:
      Number of address bits.
      For 9 bits, the MSB of the address is sent as bit 3 of the instruction
      byte, before the address byte.

  spi-cpha: true

  spi-cpol: true

  read-only:
    description:
      Disable writes to the eeprom.
    type: boolean

  wp-gpios:
    maxItems: 1
    description:
      GPIO to which the write-protect pin of the chip is connected.

  # Deprecated: at25,byte-len, at25,addr-mode, at25,page-size
  at25,byte-len:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Total eeprom size in bytes. Deprecated, use "size" property instead.
    deprecated: true

  at25,addr-mode:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Addr-mode flags, as defined in include/linux/spi/eeprom.h.
      Deprecated, use "address-width" property instead.
    deprecated: true

  at25,page-size:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Size of the eeprom page. Deprecated, use "pagesize" property instead.
    deprecated: true

required:
  - compatible
  - reg
  - spi-max-frequency

allOf:
  - $ref: /schemas/spi/spi-peripheral-props.yaml#
  - $ref: /schemas/nvmem/nvmem.yaml
  - if:
      properties:
        compatible:
          not:
            contains:
              const: cypress,fm25
    then:
      required:
        - pagesize
        - size
        - address-width

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    spi0 {
        #address-cells = <1>;
        #size-cells = <0>;

        eeprom@0 {
            compatible = "st,m95256", "atmel,at25";
            reg = <0>;
            spi-max-frequency = <5000000>;
            spi-cpha;
            spi-cpol;
            wp-gpios = <&gpio1 3 0>;

            pagesize = <64>;
            size = <32768>;
            address-width = <16>;
        };

        fram@1 {
            compatible = "cypress,fm25", "atmel,at25";
            reg = <1>;
            spi-max-frequency = <40000000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/eeprom/microchip,93lc46b.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip 93xx46 SPI compatible EEPROM family dt bindings

maintainers:
  - Cory Tusar <cory.tusar@pid1solutions.com>

properties:
  compatible:
    enum:
      - atmel,at93c46
      - atmel,at93c46d
      - atmel,at93c56
      - atmel,at93c66
      - eeprom-93xx46
      - microchip,93lc46b

  data-size:
    description: number of data bits per word
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [8, 16]

  reg:
    description: chip select of EEPROM
    maxItems: 1

  read-only:
    description:
      parameter-less property which disables writes to the EEPROM
    type: boolean

  select-gpios:
    description:
      specifies the GPIO that needs to be asserted prior to each access
      of EEPROM (e.g. for SPI bus multiplexing)
    maxItems: 1

required:
  - compatible
  - reg
  - data-size
  - spi-max-frequency

allOf:
  - $ref: /schemas/spi/spi-peripheral-props.yaml#
  - $ref: /schemas/nvmem/nvmem.yaml

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    spi {
      #address-cells = <1>;
      #size-cells = <0>;

      eeprom@0 {
        compatible = "eeprom-93xx46";
        reg = <0>;
        spi-max-frequency = <1000000>;
        spi-cs-high;
        data-size = <8>;
        select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
# All the top-level keys are standard json-schema keywords except for
# 'maintainers' and 'select'

# $id is a unique identifier based on the filename. There may or may not be a
# file present at the URL.
$id: http://devicetree.org/schemas/example-schema.yaml#
# $schema is the meta-schema this schema should be validated with.
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: An example schema annotated with jsonschema details

maintainers:
  - Rob Herring <robh@kernel.org>

description: |
  A more detailed multi-line description of the binding.

  Details about the hardware device and any links to datasheets can go here.

  Literal blocks are marked with the '|' at the beginning. The end is marked by
  indentation less than the first line of the literal block. Lines also cannot
  begin with a tab character.

select: false
  # 'select' is a schema applied to a DT node to determine if this binding
  # schema should be applied to the node. It is optional and by default the
  # possible compatible strings are extracted and used to match.

  # In this case, a 'false' schema will never match.

properties:
  # A dictionary of DT properties for this binding schema
  compatible:
    # More complicated schema can use oneOf (XOR), anyOf (OR), or allOf (AND)
    # to handle different conditions.
    # In this case, it's needed to handle a variable number of values as there
    # isn't another way to express a constraint of the last string value.
    # The boolean schema must be a list of schemas.
    oneOf:
      - items:
          # items is a list of possible values for the property. The number of
          # values is determined by the number of elements in the list.
          # Order in lists is significant, order in dicts is not
          # Must be one of the 1st enums followed by the 2nd enum
          #
          # Each element in items should be 'enum' or 'const'
          - enum:
              - vendor,soc4-ip
              - vendor,soc3-ip
              - vendor,soc2-ip
          - enum:
              - vendor,soc1-ip
        # additionalItems being false is implied
        # minItems/maxItems equal to 2 is implied
      - items:
          # 'const' is just a special case of an enum with a single possible value
          - const: vendor,soc1-ip

  reg:
    # The core schema already checks that reg values are numbers, so device
    # specific schema don't need to do those checks.
    # The description of each element defines the order and implicitly defines
    # the number of reg entries.
    items:
      - description: core registers
      - description: aux registers
    # minItems/maxItems equal to 2 is implied

  reg-names:
    # The core schema enforces this (*-names) is a string array
    items:
      - const: core
      - const: aux

  clocks:
    # Cases that have only a single entry just need to express that with maxItems
    maxItems: 1
    description: bus clock. A description is only needed for a single item if
      there's something unique to add.
      The items should have a fixed order, so pattern matching names are
      discouraged.

  clock-names:
    items:
      - const: bus

  interrupts:
    # Either 1 or 2 interrupts can be present
    minItems: 1
    items:
      - description: tx or combined interrupt
      - description: rx interrupt
    description:
      A variable number of interrupts warrants a description of what conditions
      affect the number of interrupts. Otherwise, descriptions on standard
      properties are not necessary.
      The items should have a fixed order, so pattern matching names are
      discouraged.

  interrupt-names:
    # minItems must be specified here because the default would be 2
    minItems: 1
    items:
      - const: tx irq
      - const: rx irq

  # Property names starting with '#' must be quoted
  '#interrupt-cells':
    # A simple case where the value must always be '2'.
    # The core schema handles that this must be a single integer.
    const: 2

  interrupt-controller: true
    # The core checks this is a boolean, so just have to list it here to be
    # valid for this binding.

  clock-frequency:
    # The type is set in the core schema. Per-device schema only need to set
    # constraints on the possible values.
    minimum: 100
    maximum: 400000
    # The value that should be used if the property is not present
    default: 200

  foo-gpios:
    maxItems: 1
    description: A connection of the 'foo' gpio line.

  # *-supply is always a single phandle, so nothing more to define.
  foo-supply: true

  # Vendor-specific properties
  #
  # Vendor-specific properties have slightly different schema requirements than
  # common properties. They must have at least a type definition and
  # 'description'.
  vendor,int-property:
    description: Vendor-specific properties must have a description
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [2, 4, 6, 8, 10]

  vendor,bool-property:
    description: Vendor-specific properties must have a description. Boolean
      properties are one case where the json-schema 'type' keyword can be used
      directly.
    type: boolean

  vendor,string-array-property:
    description: Vendor-specific properties should reference a type in the
      core schema.
    $ref: /schemas/types.yaml#/definitions/string-array
    items:
      - enum: [foo, bar]
      - enum: [baz, boo]

  vendor,property-in-standard-units-microvolt:
    description: Vendor-specific properties having a standard unit suffix
      don't need a type.
    enum: [ 100, 200, 300 ]

  vendor,int-array-variable-length-and-constrained-values:
    description: Array might define what type of elements might be used (e.g.
      their range).
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 2
    maxItems: 3
    items:
      minimum: 0
      maximum: 8

  child-node:
    description: Child nodes are just another property from a json-schema
      perspective.
    type: object  # DT nodes are json objects
    properties:
      vendor,a-child-node-property:
        description: Child node properties have all the same schema
          requirements.
        type: boolean

    required:
      - vendor,a-child-node-property

# Describe the relationship between different properties
dependencies:
  # 'vendor,bool-property' is only allowed when 'vendor,string-array-property'
  # is present
  vendor,bool-property: [ 'vendor,string-array-property' ]
  # Expressing 2 properties in both orders means all of the set of properties
  # must be present or none of them.
  vendor,string-array-property: [ 'vendor,bool-property' ]

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller

# if/then schema can be used to handle conditions on a property affecting
# another property. A typical case is a specific 'compatible' value changes the
# constraints on other properties.
#
# For multiple 'if' schema, group them under an 'allOf'.
#
# If the conditionals become too unweldy, then it may be better to just split
# the binding into separate schema documents.
allOf:
  - if:
      properties:
        compatible:
          contains:
            const: vendor,soc2-ip
    then:
      required:
        - foo-supply
    else:
      # If otherwise the property is not allowed:
      properties:
        foo-supply: false
  # Altering schema depending on presence of properties is usually done by
  # dependencies (see above), however some adjustments might require if:
  - if:
      required:
        - vendor,bool-property
    then:
      properties:
        vendor,int-property:
          enum: [2, 4, 6]

# Ideally, the schema should have this line otherwise any other properties
# present are allowed. There's a few common properties such as 'status' and
# 'pinctrl-*' which are added automatically by the tooling.
#
# This can't be used in cases where another schema is referenced
# (i.e. allOf: [{$ref: ...}]).
# If and only if another schema is referenced and arbitrary children nodes can
# appear, "unevaluatedProperties: false" could be used.  A typical example is
# an I2C controller where no name pattern matching for children can be added.
additionalProperties: false

examples:
  # Examples are now compiled with dtc and validated against the schemas
  #
  # Examples have a default #address-cells and #size-cells value of 1. This can
  # be overridden or an appropriate parent bus node should be shown (such as on
  # i2c buses).
  #
  # Any includes used have to be explicitly included. Use 4-space indentation.
  - |
    node@1000 {
        compatible = "vendor,soc4-ip", "vendor,soc1-ip";
        reg = <0x1000 0x80>,
              <0x3000 0x80>;
        reg-names = "core", "aux";
        interrupts = <10>;
        interrupt-controller;
    };


code:
Maxim Integrated MAX3355 USB OTG chip
-------------------------------------

MAX3355 integrates a charge pump and comparators to enable a system with an
integrated USB OTG dual-role transceiver to function as a USB OTG dual-role
device.

Required properties:
- compatible: should be "maxim,max3355";
- maxim,shdn-gpios: should contain a phandle and GPIO specifier for the GPIO pin
		    connected to the MAX3355's SHDN# pin;
- id-gpios: should contain a phandle and GPIO specifier for the GPIO pin
	    connected to the MAX3355's ID_OUT pin.

Example:

	usb-otg {
		compatible = "maxim,max3355";
		maxim,shdn-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
		id-gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>;
	};


code:
EXTCON FOR PALMAS/TWL CHIPS

PALMAS USB COMPARATOR
Required Properties:
 - compatible: should contain one of:
   * "ti,palmas-usb-vid".
   * "ti,twl6035-usb-vid".
   * "ti,palmas-usb" (DEPRECATED - use "ti,palmas-usb-vid").
   * "ti,twl6035-usb" (DEPRECATED - use "ti,twl6035-usb-vid").

Optional Properties:
 - ti,wakeup : To enable the wakeup comparator in probe
 - ti,enable-id-detection: Perform ID detection. If id-gpio is specified
		it performs id-detection using GPIO else using OTG core.
 - ti,enable-vbus-detection: Perform VBUS detection.
 - id-gpio: gpio for GPIO ID detection. See gpio binding.
 - debounce-delay-ms: debounce delay for GPIO ID pin in milliseconds.

palmas-usb {
       compatible = "ti,twl6035-usb", "ti,palmas-usb";
       ti,wakeup;
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/extcon/extcon-ptn5150.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PTN5150 CC (Configuration Channel) Logic device

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  PTN5150 is a small thin low power CC logic chip supporting the USB Type-C
  connector application with CC control logic detection and indication
  functions.  It is interfaced to the host controller using an I2C interface.

properties:
  compatible:
    const: nxp,ptn5150

  int-gpios:
    maxItems: 1
    deprecated: true
    description:
      GPIO pin (input) connected to the PTN5150's INTB pin.
      Use "interrupts" instead.

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

  vbus-gpios:
    maxItems: 1
    description:
      GPIO pin (output) used to control VBUS. If skipped, no such control
      takes place.

required:
  - compatible
  - interrupts
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        ptn5150@1d {
            compatible = "nxp,ptn5150";
            reg = <0x1d>;
            interrupt-parent = <&msmgpio>;
            interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
            vbus-gpios = <&msmgpio 148 GPIO_ACTIVE_HIGH>;
        };
    };


code:
* Richtek RT8973A - Micro USB Switch device

The Richtek RT8973A is Micro USB Switch with OVP and I2C interface. The RT8973A
is a USB port accessory detector and switch that is optimized to protect low
voltage system from abnormal high input voltage (up to 28V) and supports high
speed USB operation. Also, RT8973A support 'auto-configuration' mode.
If auto-configuration mode is enabled, RT8973A would control internal h/w patch
for USB D-/D+ switching.

Required properties:
- compatible: Should be "richtek,rt8973a-muic"
- reg: Specifies the I2C slave address of the MUIC block. It should be 0x14
- interrupts: Interrupt specifiers for detection interrupt sources.

Example:

	rt8973a@14 {
		compatible = "richtek,rt8973a-muic";
		interrupt-parent = <&gpx1>;
		interrupts = <5 0>;
		reg = <0x14>;
	};


code:
USB GPIO Extcon device

This is a virtual device used to generate USB cable states from the USB ID pin
connected to a GPIO pin.

Required properties:
- compatible: Should be "linux,extcon-usb-gpio"

Either one of id-gpio or vbus-gpio must be present. Both can be present as well.
- id-gpio: gpio for USB ID pin. See gpio binding.
- vbus-gpio: gpio for USB VBUS pin.

Example: Examples of extcon-usb-gpio node in dra7-evm.dts as listed below:
	extcon_usb1 {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&gpio6 1 GPIO_ACTIVE_HIGH>;
	}

	&omap_dwc3_1 {
		extcon = <&extcon_usb1>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/extcon/extcon-usbc-cros-ec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ChromeOS EC USB Type-C cable and accessories detection

maintainers:
  - Benson Leung <bleung@chromium.org>

description: |
  On ChromeOS systems with USB Type C ports, the ChromeOS Embedded Controller is
  able to detect the state of external accessories such as display adapters
  or USB devices when said accessories are attached or detached.
  The node for this device must be under a cros-ec node like google,cros-ec-spi
  or google,cros-ec-i2c.

properties:
  compatible:
    const: google,extcon-usbc-cros-ec

  google,usb-port-id:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: the port id
    minimum: 0
    maximum: 255

required:
  - compatible
  - google,usb-port-id

additionalProperties: false

examples:
  - |
    spi0 {
        #address-cells = <1>;
        #size-cells = <0>;
        cros-ec@0 {
            compatible = "google,cros-ec-spi";
            reg = <0>;
            interrupts = <44 0>;

            usbc_extcon0: extcon0 {
                compatible = "google,extcon-usbc-cros-ec";
                google,usb-port-id = <0>;
            };

            usbc_extcon1: extcon1 {
                compatible = "google,extcon-usbc-cros-ec";
                google,usb-port-id = <1>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/extcon/extcon-usbc-tusb320.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI TUSB320 USB Type-C CC Logic controller

maintainers:
  - Michael Auchter <michael.auchter@ni.com>

properties:
  compatible:
    enum:
      - ti,tusb320
      - ti,tusb320l

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;
        tusb320@61 {
            compatible = "ti,tusb320";
            reg = <0x61>;
            interrupt-parent = <&gpio>;
            interrupts = <27 1>;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/extcon/fcs,fsa880.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Fairchild Semiconductor FSA880, FSA9480 and compatibles

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description:
  The FSA880 and FSA9480 are USB port accessory detectors and switches.
  The switch is fully controlled using I2C and enables USB data, stereo
  and mono audio, video, microphone, and UART data to use a common
  connector port. Compatible switches exist from other manufacturers.

properties:
  compatible:
    enum:
      - fcs,fsa880
      - fcs,fsa9480
      - ti,tsu6111

  reg:
    maxItems: 1
    description: The I2C address for an FSA880 compatible device is
      usually 0x25.

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;
        usb-switch@25 {
            compatible = "fcs,fsa880";
            reg = <0x25>;
            interrupt-parent = <&gpio>;
            interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
        };
    };