code:
* Marvell Armada 370 SoC pinctrl driver for mpp

Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.

Required properties:
- compatible: "marvell,88f6710-pinctrl"
- reg: register specifier of MPP registers

Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.

name          pins     functions
================================================================================
mpp0          0        gpio, uart0(rxd)
mpp1          1        gpo, uart0(txd)
mpp2          2        gpio, i2c0(sck), uart0(txd)
mpp3          3        gpio, i2c0(sda), uart0(rxd)
mpp4          4        gpio, vdd(cpu-pd)
mpp5          5        gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk)
mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
mpp7          7        gpo, ge0(txd1), tdm(dtx), audio(lrclk)
mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
mpp9          9        gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
mpp10         10       gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
mpp11         11       gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
                       sata1(prsnt), spi1(cs1)
mpp12         12       gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
                       audio(spdifi)
mpp13         13       gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
                       audio(rmclk)
mpp14         14       gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
                       spi0(cs2)
mpp15         15       gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
                       spi0(cs3)
mpp16         16       gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
mpp17         17       gpo, ge(mdc)
mpp18         18       gpio, ge(mdio)
mpp19         19       gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
mpp20         20       gpo, ge0(txd4), ge1(txd0)
mpp21         21       gpo, ge0(txd5), ge1(txd1), uart1(txd)
mpp22         22       gpo, ge0(txd6), ge1(txd2), uart0(rts)
mpp23         23       gpo, ge0(txd7), ge1(txd3), spi1(mosi)
mpp24         24       gpio, ge0(col), ge1(txctl), spi1(cs0)
mpp25         25       gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
mpp26         26       gpio, ge0(crs), ge1(rxd1), spi1(miso)
mpp27         27       gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
mpp28         28       gpio, ge0(rxd5), ge1(rxd3)
mpp29         29       gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
mpp30         30       gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
mpp31         31       gpio, tclk, ge0(txerr)
mpp32         32       gpio, spi0(cs0)
mpp33         33       gpio, dev(bootcs), spi0(cs0)
mpp34         34       gpo, dev(we0), spi0(mosi)
mpp35         35       gpo, dev(oe), spi0(sck)
mpp36         36       gpo, dev(a1), spi0(miso)
mpp37         37       gpo, dev(a0), sata0(prsnt)
mpp38         38       gpio, dev(ready), uart1(cts), uart0(cts)
mpp39         39       gpo, dev(ad0), audio(spdifo)
mpp40         40       gpio, dev(ad1), uart1(rts), uart0(rts)
mpp41         41       gpio, dev(ad2), uart1(rxd)
mpp42         42       gpo, dev(ad3), uart1(txd)
mpp43         43       gpo, dev(ad4), audio(bclk)
mpp44         44       gpo, dev(ad5), audio(mclk)
mpp45         45       gpo, dev(ad6), audio(lrclk)
mpp46         46       gpo, dev(ad7), audio(sdo)
mpp47         47       gpo, dev(ad8), sd0(clk), audio(spdifo)
mpp48         48       gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
                       spi0(cs1)
mpp49         49       gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
                       audio(spdifi)
mpp50         50       gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
                       audio(rmclk)
mpp51         51       gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
mpp52         52       gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
mpp53         53       gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
                       pcie(clkreq1)
mpp54         54       gpo, dev(ad15), tdm(dtx)
mpp55         55       gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
                       sata0(prsnt)
mpp56         56       gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
                       pcie(clkreq0), spi1(cs1)
mpp57         57       gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
                       audio(sdo)
mpp58         58       gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
                       uart0(rts)
mpp59         59       gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout),
                       audio(sdi)
mpp61         61       gpo, dev(we1), uart1(txd), audio(lrclk)
mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
                       audio(mclk), uart0(cts)
mpp63         63       gpio, spi0(sck), tclk
mpp64         64       gpio, spi0(miso), spi0(cs1)
mpp65         65       gpio, spi0(mosi), spi0(cs2)

Note: According to the datasheet mpp63 is a gpo but there is at least
one example of a gpio usage on the board D-Link DNS-327L


code:
* Marvell Armada 375 SoC pinctrl driver for mpp

Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.

Required properties:
- compatible: "marvell,88f6720-pinctrl"
- reg: register specifier of MPP registers

Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.

name          pins     functions
================================================================================
mpp0          0        gpio, dev(ad2), spi0(cs1), spi1(cs1)
mpp1          1        gpio, dev(ad3), spi0(mosi), spi1(mosi)
mpp2          2        gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi)
mpp3          3        gpio, dev(ad5), ptp(trig), led(p3), audio(mclk)
mpp4          4        gpio, dev(ad6), spi0(miso), spi1(miso)
mpp5          5        gpio, dev(ad7), spi0(cs2), spi1(cs2)
mpp6          6        gpio, dev(ad0), led(p1), audio(lrclk)
mpp7          7        gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
mpp8          8        gpio, dev (bootcs), spi0(cs0), spi1(cs0)
mpp9          9        gpio, spi0(sck), spi1(sck), nand(we)
mpp10        10        gpio, dram(vttctrl), led(c1), nand(re)
mpp11        11        gpio, dev(a0), led(c2), audio(sdo)
mpp12        12        gpio, dev(a1), audio(bclk)
mpp13        13        gpio, dev(ready), pcie0(rstout), pcie1(rstout)
mpp14        14        gpio, i2c0(sda), uart1(txd)
mpp15        15        gpio, i2c0(sck), uart1(rxd)
mpp16        16        gpio, uart0(txd)
mpp17        17        gpio, uart0(rxd)
mpp18        18        gpio, tdm(int)
mpp19        19        gpio, tdm(rst)
mpp20        20        gpio, tdm(pclk)
mpp21        21        gpio, tdm(fsync)
mpp22        22        gpio, tdm(drx)
mpp23        23        gpio, tdm(dtx)
mpp24        24        gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts)
mpp25        25        gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts)
mpp26        26        gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts)
mpp27        27        gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts)
mpp28        28        gpio, led(p3), ge1(txctl), sd(clk)
mpp29        29        gpio, pcie1(clkreq), ge1(rxclk), sd(d3)
mpp30        30        gpio, ge1(txd0), spi1(cs0)
mpp31        31        gpio, ge1(txd1), spi1(mosi)
mpp32        32        gpio, ge1(txd2), spi1(sck), ptp(trig)
mpp33        33        gpio, ge1(txd3), spi1(miso)
mpp34        34        gpio, ge1(txclkout), spi1(sck)
mpp35        35        gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
mpp36        36        gpio, pcie0(clkreq)
mpp37        37        gpio, pcie0(clkreq), tdm(int), ge(mdc)
mpp38        38        gpio, pcie1(clkreq), ge(mdio)
mpp39        39        gpio, ref(clkout)
mpp40        40        gpio, uart1(txd)
mpp41        41        gpio, uart1(rxd)
mpp42        42        gpio, spi1(cs2), led(c0)
mpp43        43        gpio, sata0(prsnt), dram(vttctrl)
mpp44        44        gpio, sata0(prsnt)
mpp45        45        gpio, spi0(cs2), pcie0(rstout)
mpp46        46        gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1)
mpp47        47        gpio, led(p1), ge0(txd1), ge1(txd1)
mpp48        48        gpio, led(p2), ge0(txd2), ge1(txd2)
mpp49        49        gpio, led(p3), ge0(txd3), ge1(txd3)
mpp50        50        gpio, led(c0), ge0(rxd0), ge1(rxd0)
mpp51        51        gpio, led(c1), ge0(rxd1), ge1(rxd1)
mpp52        52        gpio, led(c2), ge0(rxd2), ge1(rxd2)
mpp53        53        gpio, pcie1(rstout), ge0(rxd3), ge1(rxd3)
mpp54        54        gpio, pcie0(rstout), ge0(rxctl), ge1(rxctl)
mpp55        55        gpio, ge0(rxclk), ge1(rxclk)
mpp56        56        gpio, ge0(txclkout), ge1(txclkout)
mpp57        57        gpio, ge0(txctl), ge1(txctl), dev(we0)
mpp58        58        gpio, led(c0)
mpp59        59        gpio, led(c1)
mpp60        60        gpio, uart1(txd), led(c2)
mpp61        61        gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)
mpp62        62        gpio, i2c1(sck), led(p1)
mpp63        63        gpio, ptp(trig), led(p2), dev(burst/last)
mpp64        64        gpio, dram(vttctrl), led(p3)
mpp65        65        gpio, sata1(prsnt)
mpp66        66        gpio, ptp(evreq), spi1(cs3)

repo_name: angery/linux


code:
* Marvell Armada 37xx SoC pin and gpio controller

Each Armada 37xx SoC come with two pin and gpio controller one for the
south bridge and the other for the north bridge.

Inside this set of register the gpio latch allows exposing some
configuration of the SoC and especially the clock frequency of the
xtal. Hence, this node is a represent as syscon allowing sharing the
register between multiple hardware block.

GPIO and pin controller:
------------------------

Main node:

Refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning
of the phrase "pin configuration node".

Required properties for pinctrl driver:

- compatible:	"marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
		for the south bridge
		"marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
		for the north bridge
- reg: The first set of register are for pinctrl/gpio and the second
  set for the interrupt controller
- interrupts: list of the interrupt use by the gpio

Available groups and functions for the North bridge:

group: jtag
 - pins 20-24
 - functions jtag, gpio

group sdio0
 - pins 8-10
 - functions sdio, gpio

group emmc_nb
 - pins 27-35
 - functions emmc, gpio

group pwm0
 - pin 11 (GPIO1-11)
 - functions pwm, led, gpio

group pwm1
 - pin 12
 - functions pwm, led, gpio

group pwm2
 - pin 13
 - functions pwm, led, gpio

group pwm3
 - pin 14
 - functions pwm, led, gpio

group pmic1
 - pin 7
 - functions pmic, gpio

group pmic0
 - pin 6
 - functions pmic, gpio

group i2c2
 - pins 2-3
 - functions i2c, gpio

group i2c1
 - pins 0-1
 - functions i2c, gpio

group spi_cs1
 - pin 17
 - functions spi, gpio

group spi_cs2
 - pin 18
 - functions spi, gpio

group spi_cs3
 - pin 19
 - functions spi, gpio

group onewire
 - pin 4
 - functions onewire, gpio

group uart1
 - pins 25-26
 - functions uart, gpio

group spi_quad
 - pins 15-16
 - functions spi, gpio

group uart2
 - pins 9-10 and 18-19
 - functions uart, gpio

Available groups and functions for the South bridge:

group usb32_drvvbus0
 - pin 36
 - functions drvbus, gpio

group usb2_drvvbus1
 - pin 37
 - functions drvbus, gpio

group sdio_sb
 - pins 60-65
 - functions sdio, gpio

group rgmii
 - pins 42-53
 - functions mii, gpio

group pcie1
 - pins 39
 - functions pcie, gpio

group pcie1_clkreq
 - pins 40
 - functions pcie, gpio

group pcie1_wakeup
 - pins 41
 - functions pcie, gpio

group smi
 - pins 54-55
 - functions smi, gpio

group ptp
 - pins 56
 - functions ptp, gpio

group ptp_clk
 - pin 57
 - functions ptp, mii

group ptp_trig
 - pin 58
 - functions ptp, mii

group mii_col
 - pin 59
 - functions mii, mii_err

GPIO subnode:

Please refer to gpio.txt in this directory for details of gpio-ranges property
and the common GPIO bindings used by client devices.

Required properties for gpio driver under the gpio subnode:
- interrupts: List of interrupt specifier for the controllers interrupt.
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the
   second cell specifies GPIO flags, as defined in
   <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
   GPIO_ACTIVE_LOW flags are supported.
- gpio-ranges: Range of pins managed by the GPIO controller.

Xtal Clock bindings for Marvell Armada 37xx SoCs
------------------------------------------------

see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt

Example:
pinctrl_sb: pinctrl-sb@18800 {
	compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
	reg = <0x18800 0x100>, <0x18C00 0x20>;
	gpio {
		#gpio-cells = <2>;
		gpio-ranges = <&pinctrl_sb 0 0 29>;
		gpio-controller;
		interrupts =
		<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	};

	rgmii_pins: mii-pins {
		groups = "rgmii";
		function = "mii";
	};

};


code:
* Marvell Armada 380/385 SoC pinctrl driver for mpp

Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.

Required properties:
- compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
  "marvell,88f6828-pinctrl" depending on the specific variant of the
  SoC being used.
- reg: register specifier of MPP registers

Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.

name          pins     functions
================================================================================
mpp0          0        gpio, ua0(rxd)
mpp1          1        gpio, ua0(txd)
mpp2          2        gpio, i2c0(sck)
mpp3          3        gpio, i2c0(sda)
mpp4          4        gpio, ge(mdc), ua1(txd), ua0(rts)
mpp5          5        gpio, ge(mdio), ua1(rxd), ua0(cts)
mpp6          6        gpio, ge0(txclkout), ge0(crs), dev(cs3)
mpp7          7        gpio, ge0(txd0), dev(ad9)
mpp8          8        gpio, ge0(txd1), dev(ad10)
mpp9          9        gpio, ge0(txd2), dev(ad11)
mpp10         10       gpio, ge0(txd3), dev(ad12)
mpp11         11       gpio, ge0(txctl), dev(ad13)
mpp12         12       gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq)
mpp13         13       gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq)
mpp14         14       gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq)
mpp15         15       gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi)
mpp16         16       gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1]
mpp17         17       gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt), sata0(prsnt)
mpp18         18       gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0)
mpp19         19       gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts)
mpp20         20       gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts)
mpp21         21       gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs), sata1(prsnt)
mpp22         22       gpio, spi0(mosi), dev(ad0)
mpp23         23       gpio, spi0(sck), dev(ad2)
mpp24         24       gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
mpp25         25       gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
mpp26         26       gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
mpp27         27       gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2)
mpp28         28       gpio, ge1(txd0), sd0(clk), dev(ad5)
mpp29         29       gpio, ge1(txd1), dev(ale0)
mpp30         30       gpio, ge1(txd2), dev(oe)
mpp31         31       gpio, ge1(txd3), dev(ale1)
mpp32         32       gpio, ge1(txctl), dev(we0)
mpp33         33       gpio, dram(deccerr), dev(ad3)
mpp34         34       gpio, dev(ad1)
mpp35         35       gpio, ref(clk_out1), dev(a1)
mpp36         36       gpio, ptp(trig), dev(a0)
mpp37         37       gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8)
mpp38         38       gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)
mpp39         39       gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2)
mpp40         40       gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6)
mpp41         41       gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0)
mpp42         42       gpio, ua1(txd), ua0(rts), dev(ad7)
mpp43         43       gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1)
mpp44         44       gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3]
mpp45         45       gpio, ref(clk_out0), pcie0(rstout), ua1(rxd)
mpp46         46       gpio, ref(clk_out1), pcie0(rstout), ua1(txd)
mpp47         47       gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2]
mpp48         48       gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq)
mpp49         49       gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq)
mpp50         50       gpio, pcie0(rstout), tdm(drx), audio(extclk), sd0(cmd)
mpp51         51       gpio, tdm(dtx), audio(sdo), dram(deccerr), ptp(trig)
mpp52         52       gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6), ptp(clk)
mpp53         53       gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7), ptp(evreq)
mpp54         54       gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3)
mpp55         55       gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd)
mpp56         56       gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd)
mpp57         57       gpio, spi1(sck), sd0(clk), ua1(txd)
mpp58         58       gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd)
mpp59         59       gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)

[1]: only available on 88F6820 and 88F6828
[2]: only available on 88F6828


code:
* Marvell Armada 39x SoC pinctrl driver for mpp

Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.

Required properties:
- compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
  "marvell,88f6928-pinctrl" depending on the specific variant of the
  SoC being used.
- reg: register specifier of MPP registers

Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.

name    pins    functions
================================================================================
mpp0	0	gpio, ua0(rxd)
mpp1	1	gpio, ua0(txd)
mpp2	2	gpio, i2c0(sck)
mpp3	3	gpio, i2c0(sda)
mpp4	4	gpio, ua1(txd), ua0(rts), smi(mdc)
mpp5	5	gpio, ua1(rxd), ua0(cts), smi(mdio)
mpp6	6	gpio, dev(cs3), xsmi(mdio)
mpp7	7	gpio, dev(ad9), xsmi(mdc)
mpp8	8	gpio, dev(ad10), ptp(trig)
mpp9	9	gpio, dev(ad11), ptp(clk)
mpp10	10	gpio, dev(ad12), ptp(evreq)
mpp11	11	gpio, dev(ad13), led(clk)
mpp12	12	gpio, pcie0(rstout), dev(ad14), led(stb)
mpp13	13	gpio, dev(ad15), pcie2(clkreq), led(data)
mpp14	14	gpio, dram(vttctrl), dev(we1), ua1(txd)
mpp15	15	gpio, pcie0(rstout), spi0(mosi), i2c1(sck)
mpp16	16	gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda)
mpp17	17	gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio)
mpp18	18	gpio, ua1(txd), spi0(cs0), i2c2(sck)
mpp19	19	gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda)
mpp20	20	gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc)
mpp21	21	gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs),
                sata1(prsnt) [1], ge(rxd0)
mpp22	22	gpio, spi0(mosi), dev(ad0)
mpp23	23	gpio, spi0(sck), dev(ad2)
mpp24	24	gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
mpp25	25	gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
mpp26	26	gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
mpp27	27	gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout)
mpp28	28	gpio, sd0(clk), dev(ad5), ge(txd0)
mpp29	29	gpio, dev(ale0), ge(txd1)
mpp30	30	gpio, dev(oe), ge(txd2)
mpp31	31	gpio, dev(ale1), ge(txd3)
mpp32	32	gpio, dev(we0), ge(txctl)
mpp33	33	gpio, dram(deccerr), dev(ad3)
mpp34	34	gpio, dev(ad1)
mpp35	35	gpio, ref(clk), dev(a1)
mpp36	36	gpio, dev(a0)
mpp37	37	gpio, sd0(d3), dev(ad8), ge(rxclk)
mpp38	38	gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1)
mpp39	39	gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2)
mpp40	40	gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3)
mpp41	41	gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl)
mpp42	42	gpio, ua1(txd), ua0(rts), dev(ad7)
mpp43	43	gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1)
mpp44	44	gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2],
                sata3(prsnt) [2], led(clk)
mpp45	45	gpio, ref(clk), pcie0(rstout), ua1(rxd)
mpp46	46	gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb)
mpp47	47	gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2],
                sata3(prsnt) [2], led(data)
mpp48	48	gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [2], audio(mclk) [2], sd0(d4), pcie0(clkreq), ua1(txd)
mpp49	49	gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync) [2],
                audio(lrclk) [2], sd0(d5), ua2(rxd)
mpp50	50	gpio, pcie0(rstout), tdm(drx) [2], audio(extclk) [2], sd0(cmd), ua2(rxd)
mpp51	51	gpio, tdm(dtx) [2], audio(sdo) [2], dram(deccerr), ua2(txd)
mpp52	52	gpio, pcie0(rstout), tdm(int) [2], audio(sdi) [2], sd0(d6), i2c3(sck)
mpp53	53	gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [2], audio(bclk) [2], sd0(d7), i2c3(sda)
mpp54	54	gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd)
mpp55	55	gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd)
mpp56	56	gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd)
mpp57	57	gpio, spi1(sck), sd0(clk), ua1(txd)
mpp58	58	gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd)
mpp59	59	gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)

[1]: only available on 88F6925/88F6928
[2]: only available on 88F6928


code:
* Marvell 98dx3236 pinctrl driver for mpp

Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage

Required properties:
- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
- reg: register specifier of MPP registers

This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants

name          pins     functions
================================================================================
mpp0          0        gpo, spi0(mosi), dev(ad8)
mpp1          1        gpio, spi0(miso), dev(ad9)
mpp2          2        gpo, spi0(sck), dev(ad10)
mpp3          3        gpio, spi0(cs0), dev(ad11)
mpp4          4        gpio, spi0(cs1), smi(mdc), dev(cs0)
mpp5          5        gpio, pex(rsto), sd0(cmd), dev(bootcs)
mpp6          6        gpo, sd0(clk), dev(a2)
mpp7          7        gpio, sd0(d0), dev(ale0)
mpp8          8        gpio, sd0(d1), dev(ale1)
mpp9          9        gpio, sd0(d2), dev(ready0)
mpp10         10       gpio, sd0(d3), dev(ad12)
mpp11         11       gpio, uart1(rxd), uart0(cts), dev(ad13)
mpp12         12       gpo, uart1(txd), uart0(rts), dev(ad14)
mpp13         13       gpio, intr(out), dev(ad15)
mpp14         14       gpio, i2c0(sck)
mpp15         15       gpio, i2c0(sda)
mpp16         16       gpo, dev(oe)
mpp17         17       gpo, dev(clkout)
mpp18         18       gpio, uart1(txd)
mpp19         19       gpio, uart1(rxd), dev(rb)
mpp20         20       gpo, dev(we0)
mpp21         21       gpo, dev(ad0)
mpp22         22       gpo, dev(ad1)
mpp23         23       gpo, dev(ad2)
mpp24         24       gpo, dev(ad3)
mpp25         25       gpo, dev(ad4)
mpp26         26       gpo, dev(ad5)
mpp27         27       gpo, dev(ad6)
mpp28         28       gpo, dev(ad7)
mpp29         29       gpo, dev(a0)
mpp30         30       gpo, dev(a1)
mpp31         31       gpio, slv_smi(mdc), smi(mdc), dev(we1)
mpp32         32       gpio, slv_smi(mdio), smi(mdio), dev(cs1)


code:
* Marvell Armada XP SoC pinctrl driver for mpp

Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.

Required properties:
- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
              "marvell,mv78460-pinctrl"
- reg: register specifier of MPP registers

This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.

Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.

* Marvell Armada XP (all variants)

name          pins     functions
================================================================================
mpp0          0        gpio, ge0(txclkout), lcd(d0)
mpp1          1        gpio, ge0(txd0), lcd(d1)
mpp2          2        gpio, ge0(txd1), lcd(d2)
mpp3          3        gpio, ge0(txd2), lcd(d3)
mpp4          4        gpio, ge0(txd3), lcd(d4)
mpp5          5        gpio, ge0(txctl), lcd(d5)
mpp6          6        gpio, ge0(rxd0), lcd(d6)
mpp7          7        gpio, ge0(rxd1), lcd(d7)
mpp8          8        gpio, ge0(rxd2), lcd(d8)
mpp9          9        gpio, ge0(rxd3), lcd(d9)
mpp10         10       gpio, ge0(rxctl), lcd(d10)
mpp11         11       gpio, ge0(rxclk), lcd(d11)
mpp12         12       gpio, ge0(txd4), ge1(txclkout), lcd(d12)
mpp13         13       gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13)
mpp14         14       gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15)
mpp15         15       gpio, ge0(txd7), ge1(txd2), lcd(d16)
mpp16         16       gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16)
mpp17         17       gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17)
mpp18         18       gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
mpp19         19       gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
mpp20         20       gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat)
mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
mpp24         24       gpio, lcd(hsync), sata1(prsnt), tdm(rst)
mpp25         25       gpio, lcd(vsync), sata0(prsnt), tdm(pclk)
mpp26         26       gpio, lcd(clk), tdm(fsync)
mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)
mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)
mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk)
mpp30         30       gpio, tdm(int1), sd0(clk)
mpp31         31       gpio, tdm(int2), sd0(cmd)
mpp32         32       gpio, tdm(int3), sd0(d0)
mpp33         33       gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl)
mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr)
mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
mpp36         36       gpio, spi0(mosi)
mpp37         37       gpio, spi0(miso)
mpp38         38       gpio, spi0(sck)
mpp39         39       gpio, spi0(cs0)
mpp40         40       gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0),
                       spi1(cs1)
mpp41         41       gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
                       pcie(clkreq1), spi1(cs2)
mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer)
mpp43         43       gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout),
                       spi1(cs3)
mpp44         44       gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2),
                       dram(bat), spi1(cs4)
mpp45         45       gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt),
                       spi1(cs5), dram(vttctrl)
mpp46         46       gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt),
                       spi1(cs6)
mpp47         47       gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3),
                       ref(clkout), spi1(cs7)
mpp48         48       gpio, dev(clkout), dev(burst/last), nand(rb)

* Marvell Armada XP (mv78260 and mv78460 only)

name          pins     functions
================================================================================
mpp49         49       gpio, dev(we3)
mpp50         50       gpio, dev(we2)
mpp51         51       gpio, dev(ad16)
mpp52         52       gpio, dev(ad17)
mpp53         53       gpio, dev(ad18)
mpp54         54       gpio, dev(ad19)
mpp55         55       gpio, dev(ad20)
mpp56         56       gpio, dev(ad21)
mpp57         57       gpio, dev(ad22)
mpp58         58       gpio, dev(ad23)
mpp59         59       gpio, dev(ad24)
mpp60         60       gpio, dev(ad25)
mpp61         61       gpio, dev(ad26)
mpp62         62       gpio, dev(ad27)
mpp63         63       gpio, dev(ad28)
mpp64         64       gpio, dev(ad29)
mpp65         65       gpio, dev(ad30)
mpp66         66       gpio, dev(ad31)


code:
* Marvell Dove SoC pinctrl driver for mpp

Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.

Required properties:
- compatible: "marvell,dove-pinctrl"
- clocks: (optional) phandle of pdma clock
- reg: register specifiers of MPP, MPP4, and PMU MPP registers

Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.
Note: pmu* also allows for Power Management functions listed below

name          pins     functions
================================================================================
mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
mpp2          2        gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
                       uart1(rts), pmu*
mpp3          3        gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
                       uart1(cts), lcd-spi(cs1), pmu*
mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*
mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu*
mpp8          8        gpio, pmu, watchdog(rstout), pmu*
mpp9          9        gpio, pmu, pex1(clkreq), pmu*
mpp10         10       gpio, pmu, ssp(sclk), pmu*
mpp11         11       gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
                       sdio1(ledctrl), pex0(clkreq), pmu*
mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd),
                       sata(act), pmu*
mpp13         13       gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
                       ssp(extclk), pmu*
mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu*
mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu*
mpp16         16       gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
mpp17         17       gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
                       ac97-1(sysclko)
mpp18         18       gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
mpp19         19       gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
mpp20         20       gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
                       ac97(sysclko)
mpp21         21       gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
                       uart1(cts), ssp(sfrm)
mpp22         22       gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
                       lcd-spi(mosi), uart1(cts), ssp(txd)
mpp23         23       gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
                       lcd-spi(sck), ssp(sclk)
mpp_camera    24-39    gpio, camera
mpp_sdio0     40-45    gpio, sdio0
mpp_sdio1     46-51    gpio, sdio1
mpp_audio1    52-57    gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
                       ssp/twsi
mpp_spi0      58-61    gpio, spi0
mpp_uart1     62-63    gpio, uart1
mpp_nand      64-71    gpo, nand
audio0        -        i2s, ac97
twsi          -        none, opt1, opt2, opt3

Power Management functions (pmu*):
pmu-nc               Pin not driven by any PM function
pmu-low              Pin driven low (0)
pmu-high             Pin driven high (1)
pmic(sdi)            Pin is used for PMIC SDI
cpu-pwr-down         Pin is used for CPU_PWRDWN
standby-pwr-down     Pin is used for STBY_PWRDWN
core-pwr-good        Pin is used for CORE_PWR_GOOD (Pins 0-7 only)
cpu-pwr-good         Pin is used for CPU_PWR_GOOD (Pins 8-15 only)
bat-fault            Pin is used for BATTERY_FAULT
ext0-wakeup          Pin is used for EXT0_WU
ext1-wakeup          Pin is used for EXT0_WU
ext2-wakeup          Pin is used for EXT0_WU
pmu-blink            Pin is used for blink function

Notes:
* group "mpp_audio1" allows the following functions and gpio pins:
  - gpio          : gpio on pins 52-57
  - i2s1/spdifo   : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
  - i2s1          : audio1 i2s on pins 52-55, gpio on pins 56,57
  - spdifo        : spdifo on pin 57, gpio on pins 52-55
  - twsi          : twsi on pins 56,57, gpio on pins 52-55
  - ssp/spdifo    : ssp on pins 52-55, spdifo on pin 57, no gpios
  - ssp           : ssp on pins 52-55, gpio on pins 56,57
  - ssp/twsi      : ssp on pins 52-55, twsi on pins 56,57, no gpios
* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
  audio0 pins.
* group "twsi" internally muxes twsi controller to the dedicated or option pins.


code:
* Marvell Kirkwood SoC pinctrl driver for mpp

Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.

Required properties:
- compatible: "marvell,88f6180-pinctrl",
              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
              "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
- reg: register specifier of MPP registers

This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.

Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.

* Marvell Kirkwood 88f6180

name          pins     functions
================================================================================
mpp0          0        gpio, nand(io2), spi(cs)
mpp1          1        gpo, nand(io3), spi(mosi)
mpp2          2        gpo, nand(io4), spi(sck)
mpp3          3        gpo, nand(io5), spi(miso)
mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig)
mpp6          6        sysrst(out), spi(mosi), ptp(trig)
mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
                       mii(col)
mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
                       mii(crs)
mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
                       ptp-2(trig)
mpp12         12       gpo, sdio(clk)
mpp13         13       gpio, sdio(cmd), uart1(txd)
mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd)
mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
mpp17         17       gpio, sdio(d3)
mpp18         18       gpo, nand(io0)
mpp19         19       gpo, nand(io1)
mpp35         35       gpio, mii(rxerr)
mpp36         36       gpio, audio(spdifi)
mpp37         37       gpio, audio(spdifo)
mpp38         38       gpio, audio(rmclk)
mpp39         39       gpio, audio(bclk)
mpp40         40       gpio, audio(sdo)
mpp41         41       gpio, audio(lrclk)
mpp42         42       gpio, audio(mclk)
mpp43         43       gpio, audio(sdi)
mpp44         44       gpio, audio(extclk)

* Marvell Kirkwood 88f6190

name          pins     functions
================================================================================
mpp0          0        gpio, nand(io2), spi(cs)
mpp1          1        gpo, nand(io3), spi(mosi)
mpp2          2        gpo, nand(io4), spi(sck)
mpp3          3        gpo, nand(io5), spi(miso)
mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
mpp6          6        sysrst(out), spi(mosi), ptp(trig)
mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
                       mii(col), mii-1(rxerr)
mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
                       mii(crs), sata0(prsnt)
mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
                       ptp-2(trig), sata0(act)
mpp12         12       gpo, sdio(clk)
mpp13         13       gpio, sdio(cmd), uart1(txd)
mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
mpp17         17       gpio, sdio(d3), sata0(prsnt)
mpp18         18       gpo, nand(io0)
mpp19         19       gpo, nand(io1)
mpp20         20       gpio, ge1(txd0)
mpp21         21       gpio, ge1(txd1), sata0(act)
mpp22         22       gpio, ge1(txd2)
mpp23         23       gpio, ge1(txd3), sata0(prsnt)
mpp24         24       gpio, ge1(rxd0)
mpp25         25       gpio, ge1(rxd1)
mpp26         26       gpio, ge1(rxd2)
mpp27         27       gpio, ge1(rxd3)
mpp28         28       gpio, ge1(col)
mpp29         29       gpio, ge1(txclk)
mpp30         30       gpio, ge1(rxclk)
mpp31         31       gpio, ge1(rxclk)
mpp32         32       gpio, ge1(txclko)
mpp33         33       gpo, ge1(txclk)
mpp34         34       gpio, ge1(txen)
mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr)

* Marvell Kirkwood 88f6192

name          pins     functions
================================================================================
mpp0          0        gpio, nand(io2), spi(cs)
mpp1          1        gpo, nand(io3), spi(mosi)
mpp2          2        gpo, nand(io4), spi(sck)
mpp3          3        gpo, nand(io5), spi(miso)
mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
mpp6          6        sysrst(out), spi(mosi), ptp(trig)
mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
                       mii(col), mii-1(rxerr), sata1(prsnt)
mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
                       mii(crs), sata0(prsnt)
mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
                       ptp-2(trig), sata0(act)
mpp12         12       gpo, sdio(clk)
mpp13         13       gpio, sdio(cmd), uart1(txd)
mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
                       sata1(act)
mpp17         17       gpio, sdio(d3), sata0(prsnt)
mpp18         18       gpo, nand(io0)
mpp19         19       gpo, nand(io1)
mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
                       sata1(act)
mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
                       audio(spdifo)
mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
                       sata1(prsnt)
mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
                       audio(bclk)
mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
mpp33         33       gpo, ge1(txclk), tdm(drx)
mpp34         34       gpio, ge1(txen), tdm(spi-cs1)
mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)

* Marvell Kirkwood 88f6281

name          pins     functions
================================================================================
mpp0          0        gpio, nand(io2), spi(cs)
mpp1          1        gpo, nand(io3), spi(mosi)
mpp2          2        gpo, nand(io4), spi(sck)
mpp3          3        gpo, nand(io5), spi(miso)
mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
mpp6          6        sysrst(out), spi(mosi), ptp(trig)
mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
                       mii(col), mii-1(rxerr), sata1(prsnt)
mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
                       mii(crs), sata0(prsnt)
mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
                       ptp-2(trig), sata0(act)
mpp12         12       gpio, sdio(clk)
mpp13         13       gpio, sdio(cmd), uart1(txd)
mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
                       sata1(act)
mpp17         17       gpio, sdio(d3), sata0(prsnt)
mpp18         18       gpo, nand(io0)
mpp19         19       gpo, nand(io1)
mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
                       sata1(act)
mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
                       audio(spdifo)
mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
                       sata1(prsnt)
mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
                       audio(bclk)
mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
mpp33         33       gpo, ge1(txclk), tdm(drx)
mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act)
mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo)
mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi)
mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk)
mpp45         45       gpio, ts(mp9), tdm(pclk)
mpp46         46       gpio, ts(mp10), tdm(fs)
mpp47         47       gpio, ts(mp11), tdm(drx)
mpp48         48       gpio, ts(mp12), tdm(dtx)
mpp49         49       gpio, ts(mp9), tdm(rx0ql), ptp(clk)

* Marvell Kirkwood 88f6282

name          pins     functions
================================================================================
mpp0          0        gpio, nand(io2), spi(cs)
mpp1          1        gpo, nand(io3), spi(mosi)
mpp2          2        gpo, nand(io4), spi(sck)
mpp3          3        gpo, nand(io5), spi(miso)
mpp4          4        gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
mpp5          5        gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
mpp6          6        sysrst(out), spi(mosi)
mpp7          7        gpo, spi(cs), lcd(pwm)
mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
                       mii-1(rxerr), sata1(prsnt)
mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
                       sata0(prsnt)
mpp10         10       gpo, spi(sck), uart0(txd), sata1(act)
mpp11         11       gpio, spi(miso), uart0(rxd), sata0(act)
mpp12         12       gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
mpp13         13       gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
                       audio(spdifi), audio-1(sdi)
mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
                       spi(cs)
mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
                       sata1(act), lcd(extclk)
mpp17         17       gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
mpp18         18       gpo, nand(io0), pex(clkreq)
mpp19         19       gpo, nand(io1)
mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
                       sata1(act), lcd(d0)
mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
                       audio(spdifo), lcd(d1)
mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
                       sata1(prsnt), lcd(d2)
mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
                       audio(bclk), lcd(d3)
mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
                       lcd(d4)
mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
                       lcd(d5)
mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
                       lcd(d6)
mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
                       lcd(d7)
mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
                       lcd(d8)
mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
mpp33         33       gpo, ge1(txclk), tdm(drx), lcd(d13)
mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
                       lcd(d15)
mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
mpp45         45       gpio, ts(mp9), tdm(pclk), lcd(e)
mpp46         46       gpio, ts(mp10), tdm(fs), lcd(hsync)
mpp47         47       gpio, ts(mp11), tdm(drx), lcd(vsync)
mpp48         48       gpio, ts(mp12), tdm(dtx), lcd(d16)
mpp49         49       gpo, tdm(rx0ql), pex(clkreq), lcd(d17)

* Marvell Bobcat 98dx4122

name          pins     functions
================================================================================
mpp0          0        gpio, nand(io2), spi(cs)
mpp1          1        gpo, nand(io3), spi(mosi)
mpp2          2        gpo, nand(io4), spi(sck)
mpp3          3        gpo, nand(io5), spi(miso)
mpp4          4        gpio, nand(io6), uart0(rxd)
mpp5          5        gpo, nand(io7), uart0(txd)
mpp6          6        sysrst(out), spi(mosi)
mpp7          7        gpo, pex(rsto), spi(cs)
mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts)
mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts)
mpp10         10       gpo, spi(sck), uart0(txd)
mpp11         11       gpio, spi(miso), uart0(rxd)
mpp13         13       gpio, uart1(txd)
mpp14         14       gpio, uart1(rxd)
mpp15         15       gpio, uart0(rts)
mpp16         16       gpio, uart0(cts)
mpp18         18       gpo, nand(io0)
mpp19         19       gpo, nand(io1)
mpp34         34       gpio
mpp35         35       gpio
mpp36         36       gpio
mpp37         37       gpio
mpp38         38       gpio
mpp39         39       gpio
mpp40         40       gpio
mpp41         41       gpio
mpp42         42       gpio
mpp43         43       gpio
mpp44         44       gpio
mpp45         45       gpio
mpp49         49       gpio

* Marvell Poncat2 98dx1135

name          pins     functions
================================================================================

mpp0          0        gpio, nand(io2), spi(cs)
mpp1          1        gpo, nand(io3), spi(mosi)
mpp2          2        gpo, nand(io4), spi(sck)
mpp3          3        gpo, nand(io5), spi(miso)
mpp4          4        gpio, nand(io6), uart0(rxd)
mpp5          5        gpo, nand(io7), uart0(txd)
mpp6          6        sysrst(out)
mpp7          7        gpo, spi(cs)
mpp8          8        gpio, twsi0(sda), uart1(rts)
mpp9          9        gpio, twsi(sck), uart1(cts)
mpp10         10       gpo, uart0(txd)
mpp11         11       gpio, uart0(rxd)
mpp13         13       gpio, uart1(txd)
mpp14         14       gpio, uart1(rxd)
mpp15         15       gpio, uart0(rts)
mpp16         16       gpio, uart0(cts)
mpp17         17       gpio, nand(cle)
mpp18         18       gpo, nand(io0)
mpp19         19       gpo, nand(io1)
mpp20         20       gpio
mpp21         21       gpio
mpp22         22       gpio
mpp23         23       gpio
mpp24         24       gpio
mpp25         25       gpio
mpp26         26       gpio
mpp27         27       gpio
mpp28         28       gpio, nand(ren)
mpp29         29       gpio, nand(wen)
mpp30         30       gpio
mpp31         31       gpio
mpp32         32       gpio
mpp33         33       gpio
mpp34         34       gpio, nand(ale)
mpp35         35       gpio, nand(cen)


code:
* Marvell SoC pinctrl core driver for mpp

The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
(mpp) to a specific function. For each SoC family there is a SoC specific
driver using this core driver.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

A Marvell SoC pin configuration node is a node of a group of pins which can
be used for a specific device or function. Each node requires one or more
mpp pins or group of pins and a mpp function common to all pins.

Required properties for pinctrl driver:
- compatible: "marvell,<soc>-pinctrl"
  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.

Required properties for pin configuration node:
- marvell,pins: string array of mpp pins or group of pins to be muxed.
- marvell,function: string representing a function to mux to for all
    marvell,pins given in this pin configuration node. The function has to be
    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
    valid pin/pin group names and available function names for each SoC.

Examples:

uart1: serial@12100 {
	compatible = "ns16550a";
	reg = <0x12100 0x100>;
	reg-shift = <2>;
	interrupts = <7>;

	pinctrl-0 = <&pmx_uart1_sw>;
	pinctrl-names = "default";
};

pinctrl: pinctrl@d0200 {
	compatible = "marvell,dove-pinctrl";
	reg = <0xd0200 0x14>, <0xd0440 0x04>, <0xd802c 0x08>;

	pmx_uart1_sw: pmx-uart1-sw {
		marvell,pins = "mpp_uart1";
		marvell,function = "uart1";
	};
};


code:
* Marvell Orion SoC pinctrl driver for mpp

Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
part and usage.

Required properties:
- compatible: "marvell,88f5181-pinctrl",
              "marvell,88f5181l-pinctrl",
              "marvell,88f5182-pinctrl",
              "marvell,88f5281-pinctrl"

- reg: two register areas, the first one describing the first two
  contiguous MPP registers, and the second one describing the single
  final MPP register, separated from the previous one.

Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.

* Marvell Orion 88f5181l

name          pins     functions
================================================================================
mpp0          0        pcie(rstout), pci(req2), gpio
mpp1          1        gpio, pci(gnt2)
mpp2          2        gpio, pci(req3), pci-1(pme)
mpp3          3        gpio, pci(gnt3)
mpp4          4        gpio, pci(req4)
mpp5          5        gpio, pci(gnt4)
mpp6          6        gpio, pci(req5), pci-1(clk)
mpp7          7        gpio, pci(gnt5), pci-1(clk)
mpp8          8        gpio, ge(col)
mpp9          9        gpio, ge(rxerr)
mpp10         10       gpio, ge(crs)
mpp11         11       gpio, ge(txerr)
mpp12         12       gpio, ge(txd4)
mpp13         13       gpio, ge(txd5)
mpp14         14       gpio, ge(txd6)
mpp15         15       gpio, ge(txd7)
mpp16         16       ge(rxd4)
mpp17         17       ge(rxd5)
mpp18         18       ge(rxd6)
mpp19         19       ge(rxd7)

* Marvell Orion 88f5182

name          pins     functions
================================================================================
mpp0          0        pcie(rstout), pci(req2), gpio
mpp1          1        gpio, pci(gnt2)
mpp2          2        gpio, pci(req3), pci-1(pme)
mpp3          3        gpio, pci(gnt3)
mpp4          4        gpio, pci(req4), bootnand(re), sata0(prsnt)
mpp5          5        gpio, pci(gnt4), bootnand(we), sata1(prsnt)
mpp6          6        gpio, pci(req5), nand(re0), sata0(act)
mpp7          7        gpio, pci(gnt5), nand(we0), sata1(act)
mpp8          8        gpio, ge(col)
mpp9          9        gpio, ge(rxerr)
mpp10         10       gpio, ge(crs)
mpp11         11       gpio, ge(txerr)
mpp12         12       gpio, ge(txd4), nand(re1), sata0(ledprsnt)
mpp13         13       gpio, ge(txd5), nand(we1), sata1(ledprsnt)
mpp14         14       gpio, ge(txd6), nand(re2), sata0(ledact)
mpp15         15       gpio, ge(txd7), nand(we2), sata1(ledact)
mpp16         16       uart1(rxd), ge(rxd4), gpio
mpp17         17       uart1(txd), ge(rxd5), gpio
mpp18         18       uart1(cts), ge(rxd6), gpio
mpp19         19       uart1(rts), ge(rxd7), gpio

* Marvell Orion 88f5281

name          pins     functions
================================================================================
mpp0          0        pcie(rstout), pci(req2), gpio
mpp1          1        gpio, pci(gnt2)
mpp2          2        gpio, pci(req3), pci(pme)
mpp3          3        gpio, pci(gnt3)
mpp4          4        gpio, pci(req4), bootnand(re)
mpp5          5        gpio, pci(gnt4), bootnand(we)
mpp6          6        gpio, pci(req5), nand(re0)
mpp7          7        gpio, pci(gnt5), nand(we0)
mpp8          8        gpio, ge(col)
mpp9          9        gpio, ge(rxerr)
mpp10         10       gpio, ge(crs)
mpp11         11       gpio, ge(txerr)
mpp12         12       gpio, ge(txd4), nand(re1)
mpp13         13       gpio, ge(txd5), nand(we1)
mpp14         14       gpio, ge(txd6), nand(re2)
mpp15         15       gpio, ge(txd7), nand(we2)
mpp16         16       uart1(rxd), ge(rxd4)
mpp17         17       uart1(txd), ge(rxd5)
mpp18         18       uart1(cts), ge(rxd6)
mpp19         19       uart1(rts), ge(rxd7)


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT65xx Pin Controller

maintainers:
  - Sean Wang <sean.wang@kernel.org>

description: |+
  The Mediatek's Pin controller is used to control SoC pins.

properties:
  compatible:
    enum:
      - mediatek,mt2701-pinctrl
      - mediatek,mt2712-pinctrl
      - mediatek,mt6397-pinctrl
      - mediatek,mt7623-pinctrl
      - mediatek,mt8127-pinctrl
      - mediatek,mt8135-pinctrl
      - mediatek,mt8167-pinctrl
      - mediatek,mt8173-pinctrl
      - mediatek,mt8516-pinctrl

  reg:
    maxItems: 1

  pins-are-numbered:
    $ref: /schemas/types.yaml#/definitions/flag
    description: |
      Specify the subnodes are using numbered pinmux to specify pins. (UNUSED)
    deprecated: true

  gpio-controller: true

  "#gpio-cells":
    const: 2
    description: |
      Number of cells in GPIO specifier. Since the generic GPIO
      binding is used, the amount of cells must be specified as 2. See the below
      mentioned gpio binding representation for description of particular cells.

  mediatek,pctl-regmap:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      maxItems: 1
    minItems: 1
    maxItems: 2
    description: |
      Should be phandles of the syscfg node.

  interrupt-controller: true

  interrupts:
    minItems: 1
    maxItems: 3

  "#interrupt-cells":
    const: 2

required:
  - compatible
  - gpio-controller
  - "#gpio-cells"

allOf:
  - $ref: "pinctrl.yaml#"

patternProperties:
  '-[0-9]+$':
    type: object
    additionalProperties: false
    patternProperties:
      'pins':
        type: object
        additionalProperties: false
        description: |
          A pinctrl node should contain at least one subnodes representing the
          pinctrl groups available on the machine. Each subnode will list the
          pins it needs, and how they should be configured, with regard to muxer
          configuration, pullups, drive strength, input enable/disable and input
          schmitt.
        $ref: "/schemas/pinctrl/pincfg-node.yaml"

        properties:
          pinmux:
            description:
              integer array, represents gpio pin number and mux setting.
              Supported pin number and mux varies for different SoCs, and are
              defined as macros in <soc>-pinfunc.h directly.

          bias-disable: true

          bias-pull-up:
            description: |
              Besides generic pinconfig options, it can be used as the pull up
              settings for 2 pull resistors, R0 and R1. User can configure those
              special pins. Some macros have been defined for this usage, such
              as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for
              valid arguments.

          bias-pull-down: true

          input-enable: true

          input-disable: true

          output-low: true

          output-high: true

          input-schmitt-enable: true

          input-schmitt-disable: true

          drive-strength:
            description: |
              Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,
              etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.

        required:
          - pinmux

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/pinctrl/mt8135-pinfunc.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        syscfg_pctl_a: syscfg-pctl-a@10005000 {
          compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
          reg = <0 0x10005000 0 0x1000>;
        };

        syscfg_pctl_b: syscfg-pctl-b@1020c020 {
          compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
          reg = <0 0x1020C020 0 0x1000>;
        };

        pinctrl@1c20800 {
          compatible = "mediatek,mt8135-pinctrl";
          reg = <0 0x1000B000 0 0x1000>;
          mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
          gpio-controller;
          #gpio-cells = <2>;
          interrupt-controller;
          #interrupt-cells = <2>;
          interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

          i2c0_pins_a: i2c0-0 {
            pins1 {
              pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
                <MT8135_PIN_101_SCL0__FUNC_SCL0>;
              bias-disable;
            };
          };

          i2c1_pins_a: i2c1-0 {
            pins {
              pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
                <MT8135_PIN_196_SCL1__FUNC_SCL1>;
              bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
            };
          };

          i2c2_pins_a: i2c2-0 {
            pins1 {
              pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
              bias-pull-down;
            };

            pins2 {
              pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
              bias-pull-up;
            };
          };

          i2c3_pins_a: i2c3-0 {
            pins1 {
              pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
                <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
              bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
            };

            pins2 {
              pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
                <MT8135_PIN_36_SDA3__FUNC_SDA3>;
              output-low;
              bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
            };

            pins3 {
              pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
                <MT8135_PIN_60_JTDI__FUNC_JTDI>;
              drive-strength = <32>;
            };
          };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT6779 Pin Controller

maintainers:
  - Andy Teng <andy.teng@mediatek.com>
  - Sean Wang <sean.wang@kernel.org>

description:
  The MediaTek pin controller on MT6779 is used to control pin
  functions, pull up/down resistance and drive strength options.

properties:
  compatible:
    enum:
      - mediatek,mt6779-pinctrl
      - mediatek,mt6797-pinctrl

  reg:
    description: Physical addresses for GPIO base(s) and EINT registers.

  reg-names: true

  gpio-controller: true

  "#gpio-cells":
    const: 2
    description: |
      Number of cells in GPIO specifier. Since the generic GPIO
      binding is used, the amount of cells must be specified as 2. See the below
      mentioned gpio binding representation for description of particular cells.

  gpio-ranges:
    minItems: 1
    maxItems: 5
    description: |
      GPIO valid number range.

  interrupt-controller: true

  interrupts:
    maxItems: 1
    description: |
      Specifies the summary IRQ.

  "#interrupt-cells":
    const: 2

required:
  - compatible
  - reg
  - reg-names
  - gpio-controller
  - "#gpio-cells"

allOf:
  - $ref: "pinctrl.yaml#"
  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt6779-pinctrl
    then:
      properties:
        reg:
          minItems: 9
          maxItems: 9

        reg-names:
          items:
            - const: gpio
            - const: iocfg_rm
            - const: iocfg_br
            - const: iocfg_lm
            - const: iocfg_lb
            - const: iocfg_rt
            - const: iocfg_lt
            - const: iocfg_tl
            - const: eint
  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt6797-pinctrl
    then:
      properties:
        reg:
          minItems: 5
          maxItems: 5

        reg-names:
          items:
            - const: gpio
            - const: iocfgl
            - const: iocfgb
            - const: iocfgr
            - const: iocfgt
  - if:
      properties:
        reg-names:
          contains:
            const: eint
    then:
      required:
        - interrupts
        - interrupt-controller
        - "#interrupt-cells"

patternProperties:
  '-[0-9]*$':
    type: object
    additionalProperties: false

    patternProperties:
      '-pins*$':
        type: object
        description: |
          A pinctrl node should contain at least one subnodes representing the
          pinctrl groups available on the machine. Each subnode will list the
          pins it needs, and how they should be configured, with regard to muxer
          configuration, pullups, drive strength, input enable/disable and input schmitt.
        $ref: "/schemas/pinctrl/pincfg-node.yaml"

        properties:
          pinmux:
            description:
              integer array, represents gpio pin number and mux setting.
              Supported pin number and mux varies for different SoCs, and are defined
              as macros in boot/dts/<soc>-pinfunc.h directly.

          bias-disable: true

          bias-pull-up: true

          bias-pull-down: true

          input-enable: true

          input-disable: true

          output-low: true

          output-high: true

          input-schmitt-enable: true

          input-schmitt-disable: true

          drive-strength:
            enum: [2, 4, 8, 12, 16]

          slew-rate:
            enum: [0, 1]

          mediatek,pull-up-adv:
            description: |
              Pull up setings for 2 pull resistors, R0 and R1. User can
              configure those special pins. Valid arguments are described as below:
              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [0, 1, 2, 3]

          mediatek,pull-down-adv:
            description: |
              Pull down settings for 2 pull resistors, R0 and R1. User can
              configure those special pins. Valid arguments are described as below:
              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [0, 1, 2, 3]

        required:
          - pinmux

        additionalProperties: false

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/pinctrl/mt6779-pinfunc.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pio: pinctrl@10005000 {
            compatible = "mediatek,mt6779-pinctrl";
            reg = <0 0x10005000 0 0x1000>,
                <0 0x11c20000 0 0x1000>,
                <0 0x11d10000 0 0x1000>,
                <0 0x11e20000 0 0x1000>,
                <0 0x11e70000 0 0x1000>,
                <0 0x11ea0000 0 0x1000>,
                <0 0x11f20000 0 0x1000>,
                <0 0x11f30000 0 0x1000>,
                <0 0x1000b000 0 0x1000>;
            reg-names = "gpio", "iocfg_rm",
              "iocfg_br", "iocfg_lm",
              "iocfg_lb", "iocfg_rt",
              "iocfg_lt", "iocfg_tl",
              "eint";
            gpio-controller;
            #gpio-cells = <2>;
            gpio-ranges = <&pio 0 0 210>;
            interrupt-controller;
            #interrupt-cells = <2>;
            interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;

            mmc0_pins_default: mmc0-0 {
                cmd-dat-pins {
                    pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
                        <PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
                        <PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
                        <PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
                        <PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
                        <PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
                        <PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
                        <PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
                        <PINMUX_GPIO167__FUNC_MSDC0_CMD>;
                    input-enable;
                    mediatek,pull-up-adv = <1>;
                };
                clk-pins {
                    pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
                    mediatek,pull-down-adv = <2>;
                };
                rst-pins {
                    pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
                    mediatek,pull-up-adv = <0>;
                };
            };
        };

        mmc0 {
           pinctrl-0 = <&mmc0_pins_default>;
           pinctrl-names = "default";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT7622 Pin Controller

maintainers:
  - Sean Wang <sean.wang@kernel.org>

description: |+
  The MediaTek's MT7622 Pin controller is used to control SoC pins.

properties:
  compatible:
    enum:
      - mediatek,mt7622-pinctrl
      - mediatek,mt7629-pinctrl

  reg:
    maxItems: 1

  reg-names:
    items:
      - const: eint

  gpio-controller: true

  "#gpio-cells":
    const: 2
    description: |
      Number of cells in GPIO specifier. Since the generic GPIO
      binding is used, the amount of cells must be specified as 2. See the below
      mentioned gpio binding representation for description of particular cells.

  interrupt-controller: true

  interrupts:
    maxItems: 1

  "#interrupt-cells":
    const: 2

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"

if:
  required:
    - interrupt-controller
then:
  required:
    - reg-names
    - interrupts
    - "#interrupt-cells"

patternProperties:
  '-[0-9]+$':
    type: object
    additionalProperties: false
    patternProperties:
      'mux':
        type: object
        additionalProperties: false
        description: |
          pinmux configuration nodes.
        $ref: "/schemas/pinctrl/pinmux-node.yaml"
        properties:
          function:
            description: |
              A string containing the name of the function to mux to the group.
            enum: [emmc, eth, i2c, i2s, ir, led, flash, pcie, pmic, pwm, sd,
                   spi, tdm, uart, watchdog, wifi]

          groups:
            description: |
              An array of strings. Each string contains the name of a group.

          drive-strength:
            enum: [4, 8, 12, 16]

        required:
          - groups
          - function

        allOf:
          - if:
              properties:
                function:
                  const: emmc
            then:
              properties:
                groups:
                  enum: [emmc, emmc_rst]
          - if:
              properties:
                function:
                  const: eth
            then:
              properties:
                groups:
                  enum: [esw, esw_p0_p1, esw_p2_p3_p4, rgmii_via_esw,
                         rgmii_via_gmac1, rgmii_via_gmac2, mdc_mdio]
          - if:
              properties:
                function:
                  const: i2c
            then:
              properties:
                groups:
                  enum: [i2c0, i2c_0, i2c_1, i2c1_0, i2c1_1, i2c1_2, i2c2_0,
                         i2c2_1, i2c2_2]
          - if:
              properties:
                function:
                  const: i2s
            then:
              properties:
                groups:
                  enum: [i2s_in_mclk_bclk_ws, i2s1_in_data, i2s2_in_data,
                         i2s3_in_data, i2s4_in_data, i2s_out_mclk_bclk_ws,
                         i2s1_out_data, i2s2_out_data, i2s3_out_data,
                         i2s4_out_data]
          - if:
              properties:
                function:
                  const: ir
            then:
              properties:
                groups:
                  enum: [ir_0_tx, ir_1_tx, ir_2_tx, ir_0_rx, ir_1_rx, ir_2_rx]
          - if:
              properties:
                function:
                  const: led
            then:
              properties:
                groups:
                  enum: [ephy_leds, ephy0_led, ephy1_led, ephy2_led, ephy3_led,
                         ephy4_led, wled, wf2g_led, wf5g_led]
          - if:
              properties:
                function:
                  const: flash
            then:
              properties:
                groups:
                  enum: [par_nand, snfi, spi_nor]
          - if:
              properties:
                function:
                  const: pcie
            then:
              properties:
                groups:
                  enum: [pcie0_0_waken, pcie0_1_waken, pcie1_0_waken,
                         pcie0_0_clkreq, pcie0_1_clkreq, pcie1_0_clkreq,
                         pcie0_pad_perst, pcie1_pad_perst, pcie_pereset,
                         pcie_wake, pcie_clkreq]
          - if:
              properties:
                function:
                  const: pmic
            then:
              properties:
                groups:
                  enum: [pmic_bus]
          - if:
              properties:
                function:
                  const: pwm
            then:
              properties:
                groups:
                  enum: [pwm_ch1_0, pwm_ch1_1, pwm_ch1_2, pwm_ch2_0, pwm_ch2_1,
                         pwm_ch2_2, pwm_ch3_0, pwm_ch3_1, pwm_ch3_2, pwm_ch4_0,
                         pwm_ch4_1, pwm_ch4_2, pwm_ch4_3, pwm_ch5_0, pwm_ch5_1,
                         pwm_ch5_2, pwm_ch6_0, pwm_ch6_1, pwm_ch6_2, pwm_ch6_3,
                         pwm_ch7_0, pwm_0, pwm_1]
          - if:
              properties:
                function:
                  const: sd
            then:
              properties:
                groups:
                  enum: [sd_0, sd_1]
          - if:
              properties:
                function:
                  const: spi
            then:
              properties:
                groups:
                  enum: [spic0_0, spic0_1, spic1_0, spic1_1, spic2_0_wp_hold,
                         spic2_0, spi_0, spi_1, spi_wp, spi_hold]
          - if:
              properties:
                function:
                  const: tdm
            then:
              properties:
                groups:
                  enum: [tdm_0_out_mclk_bclk_ws, tdm_0_in_mclk_bclk_ws,
                         tdm_0_out_data, tdm_0_in_data, tdm_1_out_mclk_bclk_ws,
                         tdm_1_in_mclk_bclk_ws, tdm_1_out_data, tdm_1_in_data]
          - if:
              properties:
                function:
                  const: uart
            then:
              properties:
                groups:
                  enum: [uart0_0_tx_rx, uart1_0_tx_rx, uart1_0_rts_cts,
                         uart1_1_tx_rx, uart1_1_rts_cts, uart2_0_tx_rx,
                         uart2_0_rts_cts, uart2_1_tx_rx, uart2_1_rts_cts,
                         uart2_2_tx_rx, uart2_2_rts_cts, uart2_3_tx_rx,
                         uart3_0_tx_rx, uart3_1_tx_rx, uart3_1_rts_cts,
                         uart4_0_tx_rx, uart4_1_tx_rx, uart4_1_rts_cts,
                         uart4_2_tx_rx, uart4_2_rts_cts, uart0_txd_rxd,
                         uart1_0_txd_rxd, uart1_0_cts_rts, uart1_1_txd_rxd,
                         uart1_1_cts_rts, uart2_0_txd_rxd, uart2_0_cts_rts,
                         uart2_1_txd_rxd, uart2_1_cts_rts]
          - if:
              properties:
                function:
                  const: watchdog
            then:
              properties:
                groups:
                  enum: [watchdog]
          - if:
              properties:
                function:
                  const: wifi
            then:
              properties:
                groups:
                  enum: [wf0_2g, wf0_5g]

      'conf':
        type: object
        additionalProperties: false
        description: |
          pinconf configuration nodes.
        $ref: "/schemas/pinctrl/pincfg-node.yaml"

        properties:
          groups:
            description: |
              An array of strings. Each string contains the name of a group.
              Valid values are the same as the pinmux node.

          pins:
            description: |
              An array of strings. Each string contains the name of a pin.
            enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, TXD0,
                   RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS,
                   I2C_SDA, I2C_SCL, I2S2_IN, I2S3_IN, I2S4_IN, I2S2_OUT,
                   I2S3_OUT, I2S4_OUT, GPIO_B, MDC, MDIO, G2_TXD0, G2_TXD1,
                   G2_TXD2, G2_TXD3, G2_TXEN, G2_TXC, G2_RXD0, G2_RXD1, G2_RXD2,
                   G2_RXD3, G2_RXDV, G2_RXC, NCEB, NWEB, NREB, NDL4, NDL5, NDL6,
                   NDL7, NRB, NCLE, NALE, NDL0, NDL1, NDL2, NDL3, MDI_TP_P0,
                   MDI_TN_P0, MDI_RP_P0, MDI_RN_P0, MDI_TP_P1, MDI_TN_P1,
                   MDI_RP_P1, MDI_RN_P1, MDI_RP_P2, MDI_RN_P2, MDI_TP_P2,
                   MDI_TN_P2, MDI_TP_P3, MDI_TN_P3, MDI_RP_P3, MDI_RN_P3,
                   MDI_RP_P4, MDI_RN_P4, MDI_TP_P4, MDI_TN_P4, PMIC_SCL,
                   PMIC_SDA, SPIC1_CLK, SPIC1_MOSI, SPIC1_MISO, SPIC1_CS,
                   GPIO_D, WATCHDOG, RTS3_N, CTS3_N, TXD3, RXD3, PERST0_N,
                   PERST1_N, WLED_N, EPHY_LED0_N, AUXIN0, AUXIN1, AUXIN2,
                   AUXIN3, TXD4, RXD4, RTS4_N, CST4_N, PWM1, PWM2, PWM3, PWM4,
                   PWM5, PWM6, PWM7, GPIO_E, TOP_5G_CLK, TOP_5G_DATA,
                   WF0_5G_HB0, WF0_5G_HB1, WF0_5G_HB2, WF0_5G_HB3, WF0_5G_HB4,
                   WF0_5G_HB5, WF0_5G_HB6, XO_REQ, TOP_RST_N, SYS_WATCHDOG,
                   EPHY_LED0_N_JTDO, EPHY_LED1_N_JTDI, EPHY_LED2_N_JTMS,
                   EPHY_LED3_N_JTCLK, EPHY_LED4_N_JTRST_N, WF2G_LED_N,
                   WF5G_LED_N, GPIO_9, GPIO_10, GPIO_11, GPIO_12, UART1_TXD,
                   UART1_RXD, UART1_CTS, UART1_RTS, UART2_TXD, UART2_RXD,
                   UART2_CTS, UART2_RTS, SMI_MDC, SMI_MDIO, PCIE_PERESET_N,
                   PWM_0, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5,
                   GPIO_6, GPIO_7, GPIO_8, UART0_TXD, UART0_RXD, TOP_2G_CLK,
                   TOP_2G_DATA, WF0_2G_HB0, WF0_2G_HB1, WF0_2G_HB2, WF0_2G_HB3,
                   WF0_2G_HB4, WF0_2G_HB5, WF0_2G_HB6]

          bias-disable: true

          bias-pull-up: true

          bias-pull-down: true

          input-enable: true

          input-disable: true

          output-enable: true

          output-low: true

          output-high: true

          input-schmitt-enable: true

          input-schmitt-disable: true

          drive-strength:
            enum: [4, 8, 12, 16]

          slew-rate:
            enum: [0, 1]

          mediatek,tdsel:
            description: |
              An integer describing the steps for output level shifter duty
              cycle when asserted (high pulse width adjustment). Valid arguments
              are from 0 to 15.
            $ref: /schemas/types.yaml#/definitions/uint32

          mediatek,rdsel:
            description: |
              An integer describing the steps for input level shifter duty cycle
              when asserted (high pulse width adjustment). Valid arguments are
              from 0 to 63.
            $ref: /schemas/types.yaml#/definitions/uint32

        required:
          - pins

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pio: pinctrl@10211000 {
          compatible = "mediatek,mt7622-pinctrl";
          reg = <0 0x10211000 0 0x1000>;
          gpio-controller;
          #gpio-cells = <2>;

          pinctrl_eth_default: eth-0 {
            mux-mdio {
              groups = "mdc_mdio";
              function = "eth";
              drive-strength = <12>;
            };

            mux-gmac2 {
              groups = "rgmii_via_gmac2";
              function = "eth";
              drive-strength = <12>;
            };

            mux-esw {
              groups = "esw";
              function = "eth";
              drive-strength = <8>;
            };

            conf-mdio {
              pins = "MDC";
              bias-pull-up;
            };
          };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT7986 Pin Controller

maintainers:
  - Sean Wang <sean.wang@kernel.org>

description: |+
  The MediaTek's MT7986 Pin controller is used to control SoC pins.

properties:
  compatible:
    enum:
      - mediatek,mt7986a-pinctrl
      - mediatek,mt7986b-pinctrl

  reg:
    minItems: 8
    maxItems: 8

  reg-names:
    items:
      - const: gpio
      - const: iocfg_rt
      - const: iocfg_rb
      - const: iocfg_lt
      - const: iocfg_lb
      - const: iocfg_tr
      - const: iocfg_tl
      - const: eint

  gpio-controller: true

  "#gpio-cells":
    const: 2
    description: |
      Number of cells in GPIO specifier. Since the generic GPIO
      binding is used, the amount of cells must be specified as 2. See the below
      mentioned gpio binding representation for description of particular cells.

  gpio-ranges:
    minItems: 1
    maxItems: 5
    description: |
      GPIO valid number range.

  interrupt-controller: true

  interrupts:
    maxItems: 1

  "#interrupt-cells":
    const: 2

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - reg-names
  - gpio-controller
  - "#gpio-cells"

patternProperties:
  '-pins$':
    type: object
    additionalProperties: false

    patternProperties:
      '.*mux.*':
        type: object
        additionalProperties: false
        description: |
          pinmux configuration nodes.

          The following table shows the effective values of "group", "function"
          properties and chip pinout pins

          groups	    function    pins (in pin#)
          ---------------------------------------------------------------------
          "watchdog"        "watchdog"  0
          "wifi_led"        "led"       1, 2
          "i2c"             "i2c"       3, 4
          "uart1_0"         "uart"      7, 8, 9, 10
          "uart1_rx_tx"     "uart"      42, 43
          "uart1_cts_rts"   "uart"      44, 45
          "pcie_clk"        "pcie"      9
          "pcie_wake"       "pcie"      10
          "spi1_0"          "spi"       11, 12, 13, 14
          "pwm1_1"          "pwm"       20,
          "pwm0"            "pwm"       21,
          "pwm1_0"          "pwm"       22,
          "snfi"            "flash"     23, 24, 25, 26, 27, 28
          "spi1_2"          "spi"       29, 30, 31, 32
          "emmc_45"         "emmc"      22, 23, 24, 25, 26, 27, 28, 29, 30,
                                        31, 32
          "spi1_1"          "spi"       23, 24, 25, 26
          "uart1_2_rx_tx"   "uart"      29, 30
          "uart1_2_cts_rts" "uart"      31, 32
          "uart1_1"         "uart"      23, 24, 25, 26
          "uart2_0_rx_tx"   "uart"      29, 30
          "uart2_0_cts_rts" "uart"      31, 32
          "spi0"            "spi"       33, 34, 35, 36
          "spi0_wp_hold"    "spi"       37, 38
          "uart1_3_rx_tx"   "uart"      35, 36
          "uart1_3_cts_rts" "uart"      37, 38
          "uart2_1"         "uart"      33, 34, 35, 36
          "spi1_3"          "spi"       33, 34, 35, 36
          "uart0"           "uart"      39, 40
          "pcie_pereset"    "pcie"      41
          "uart1"           "uart"      42, 43, 44, 45
          "uart2"           "uart"      46, 47, 48, 49
          "emmc_51"         "emmc"      50, 51, 52, 53, 54, 55, 56, 57, 57,
                                        59, 60, 61
          "pcm"             "audio"     62, 63, 64, 65
          "i2s"             "audio"     62, 63, 64, 65
          "switch_int"      "eth"       66
          "mdc_mdio"        "eth"       67
          "wf_2g"           "wifi"      74, 75, 76, 77, 78, 79, 80, 81, 82, 83
          "wf_5g"           "wifi"      91, 92, 93, 94, 95, 96, 97, 98, 99, 100
          "wf_dbdc"         "wifi"      74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
                                        84, 85

        $ref: "/schemas/pinctrl/pinmux-node.yaml"
        properties:
          function:
            description: |
              A string containing the name of the function to mux to the group.
              There is no "audio", "pcie" functions on mt7986b, you can only use
              those functions on mt7986a.
            enum: [audio, emmc, eth, i2c, led, flash, pcie, pwm, spi, uart,
                   watchdog, wifi]
          groups:
            description: |
              An array of strings. Each string contains the name of a group.
              There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm",
              and "i2s" groups on mt7986b, you can only use those groups on
              mt7986a.
        required:
          - function
          - groups

        allOf:
          - if:
              properties:
                function:
                  const: audio
            then:
              properties:
                groups:
                  enum: [pcm, i2s]
          - if:
              properties:
                function:
                  const: emmc
            then:
              properties:
                groups:
                  enum: [emmc_45, emmc_51]
          - if:
              properties:
                function:
                  const: eth
            then:
              properties:
                groups:
                  enum: [switch_int, mdc_mdio]
          - if:
              properties:
                function:
                  const: i2c
            then:
              properties:
                groups:
                  enum: [i2c]
          - if:
              properties:
                function:
                  const: led
            then:
              properties:
                groups:
                  enum: [wifi_led]
          - if:
              properties:
                function:
                  const: flash
            then:
              properties:
                groups:
                  enum: [snfi]
          - if:
              properties:
                function:
                  const: pcie
            then:
              properties:
                groups:
                  items:
                    enum: [pcie_clk, pcie_wake, pcie_pereset]
                  maxItems: 3
          - if:
              properties:
                function:
                  const: pwm
            then:
              properties:
                groups:
                  items:
                    enum: [pwm0, pwm1_0, pwm1_1]
                  maxItems: 2
          - if:
              properties:
                function:
                  const: spi
            then:
              properties:
                groups:
                  items:
                    enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3]
                  maxItems: 2
          - if:
              properties:
                function:
                  const: uart
            then:
              properties:
                groups:
                  items:
                    enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1,
                           uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx,
                           uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts,
                           uart2_1, uart0, uart1, uart2]
                  maxItems: 2
          - if:
              properties:
                function:
                  const: watchdog
            then:
              properties:
                groups:
                  enum: [watchdog]
          - if:
              properties:
                function:
                  const: wifi
            then:
              properties:
                groups:
                  items:
                    enum: [wf_2g, wf_5g, wf_dbdc]
                  maxItems: 3
      '.*conf.*':
        type: object
        additionalProperties: false
        description: |
          pinconf configuration nodes.
        $ref: "/schemas/pinctrl/pincfg-node.yaml"

        properties:
          pins:
            description: |
              An array of strings. Each string contains the name of a pin.
              There is no PIN 41 to PIN 65 above on mt7686b, you can only use
              those pins on mt7986a.
            items:
              enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0,
                     GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7,
                     GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14,
                     GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, SPI0_MISO, SPI0_CS,
                     SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, SPI1_MISO, SPI1_CS,
                     SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP,
                     UART0_RXD, UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD,
                     UART1_CTS, UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS,
                     UART2_RTS, EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2,
                     EMMC_DATA_3, EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6,
                     EMMC_DATA_7, EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX,
                     PCM_DRX, PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO,
                     WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK,
                     WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0,
                     WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9,
                     WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ,
                     WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3,
                     WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7,
                     WF1_HB8]
            maxItems: 101

          bias-disable: true

          bias-pull-up:
            oneOf:
              - type: boolean
                description: normal pull up.
              - enum: [100, 101, 102, 103]
                description: |
                  PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
                  dt-bindings/pinctrl/mt65xx.h.

          bias-pull-down:
            oneOf:
              - type: boolean
                description: normal pull down.
              - enum: [100, 101, 102, 103]
                description: |
                  PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
                  dt-bindings/pinctrl/mt65xx.h.

          input-enable: true

          input-disable: true

          output-enable: true

          output-low: true

          output-high: true

          input-schmitt-enable: true

          input-schmitt-disable: true

          drive-strength:
            enum: [2, 4, 6, 8, 10, 12, 14, 16]

          mediatek,pull-up-adv:
            description: |
              Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
              Pull up setings for 2 pull resistors, R0 and R1. Valid arguments
              are described as below:
              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [0, 1, 2, 3]

          mediatek,pull-down-adv:
            description: |
              Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
              Pull down setings for 2 pull resistors, R0 and R1. Valid arguments
              are described as below:
              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [0, 1, 2, 3]

        required:
          - pins

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/pinctrl/mt65xx.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;
      pio: pinctrl@1001f000 {
        compatible = "mediatek,mt7986a-pinctrl";
        reg = <0 0x1001f000 0 0x1000>,
              <0 0x11c30000 0 0x1000>,
              <0 0x11c40000 0 0x1000>,
              <0 0x11e20000 0 0x1000>,
              <0 0x11e30000 0 0x1000>,
              <0 0x11f00000 0 0x1000>,
              <0 0x11f10000 0 0x1000>,
              <0 0x1000b000 0 0x1000>;
        reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
                    "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&pio 0 0 100>;
        interrupt-controller;
        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-parent = <&gic>;
        #interrupt-cells = <2>;

        pcie_pins: pcie-pins {
          mux {
            function = "pcie";
            groups = "pcie_clk", "pcie_wake", "pcie_pereset";
          };
        };

        pwm_pins: pwm-pins {
          mux {
            function = "pwm";
            groups = "pwm0", "pwm1_0";
          };
        };

        spi0_pins: spi0-pins {
          mux {
            function = "spi";
            groups = "spi0", "spi0_wp_hold";
          };
        };

        uart1_pins: uart1-pins {
          mux {
            function = "uart";
            groups = "uart1";
          };
        };

        uart1_3_pins: uart1-3-pins {
          mux {
            function = "uart";
            groups = "uart1_3_rx_tx", "uart1_3_cts_rts";
          };
        };

        uart2_pins: uart2-pins {
          mux {
            function = "uart";
            groups = "uart2";
          };
        };

        mmc0_pins_default: mmc0-pins {
          mux {
            function = "emmc";
            groups = "emmc_51";
          };
          conf-cmd-dat {
            pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
                   "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
                   "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
            input-enable;
            drive-strength = <4>;
            bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
          };
          conf-clk {
            pins = "EMMC_CK";
            drive-strength = <6>;
            bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
          };
          conf-ds {
            pins = "EMMC_DSL";
            bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
          };
          conf-rst {
            pins = "EMMC_RSTB";
            drive-strength = <4>;
            bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
          };
        };

      };
    };