code:
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

/ {
	model = "MikroTik RB3011UiAS-RM";
	compatible = "mikrotik,rb3011", "qcom,ipq8064";

	aliases {
		serial0 = &gsbi7_serial;
		ethernet0 = &gmac0;
		ethernet1 = &gmac3;
		mdio-gpio0 = &mdio0;
		mdio-gpio1 = &mdio1;
	};

	chosen {
		bootargs = "loglevel=8 console=ttyMSM0,115200";
		stdout-path = "serial0:115200n8";
	};

	memory@42000000 {
		reg = <0x42000000 0x3e000000>;
		device_type = "memory";
	};

	mdio0: mdio-0 {
		status = "okay";
		compatible = "virtual,mdio-gpio";
		gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
			<&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		pinctrl-0 = <&mdio0_pins>;
		pinctrl-names = "default";

		switch0: switch@10 {
			compatible = "qca,qca8337";
			#address-cells = <1>;
			#size-cells = <0>;

			dsa,member = <0 0>;

			pinctrl-0 = <&sw0_reset_pin>;
			pinctrl-names = "default";

			reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
			reg = <0x10>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				switch0cpu: port@0 {
					reg = <0>;
					label = "cpu";
					ethernet = <&gmac0>;
					phy-mode = "rgmii-id";
					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};

				port@1 {
					reg = <1>;
					label = "sw1";
				};

				port@2 {
					reg = <2>;
					label = "sw2";
				};

				port@3 {
					reg = <3>;
					label = "sw3";
				};

				port@4 {
					reg = <4>;
					label = "sw4";
				};

				port@5 {
					reg = <5>;
					label = "sw5";
				};
			};
		};
	};

	mdio1: mdio-1 {
		status = "okay";
		compatible = "virtual,mdio-gpio";
		gpios = <&qcom_pinmux 11 GPIO_ACTIVE_HIGH>,
			<&qcom_pinmux 10 GPIO_ACTIVE_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		pinctrl-0 = <&mdio1_pins>;
		pinctrl-names = "default";

		switch1: switch@14 {
			compatible = "qca,qca8337";
			#address-cells = <1>;
			#size-cells = <0>;

			dsa,member = <1 0>;

			pinctrl-0 = <&sw1_reset_pin>;
			pinctrl-names = "default";

			reset-gpios = <&qcom_pinmux 17 GPIO_ACTIVE_LOW>;
			reg = <0x10>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				switch1cpu: port@0 {
					reg = <0>;
					label = "cpu";
					ethernet = <&gmac3>;
					phy-mode = "sgmii";
					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};

				port@1 {
					reg = <1>;
					label = "sw6";
				};

				port@2 {
					reg = <2>;
					label = "sw7";
				};

				port@3 {
					reg = <3>;
					label = "sw8";
				};

				port@4 {
					reg = <4>;
					label = "sw9";
				};

				port@5 {
					reg = <5>;
					label = "sw10";
				};
			};
		};
	};

	soc {
		gsbi5: gsbi@1a200000 {
			qcom,mode = <GSBI_PROT_SPI>;
			status = "okay";

			spi4: spi@1a280000 {
				status = "okay";
				spi-max-frequency = <50000000>;

				pinctrl-0 = <&spi_pins>;
				pinctrl-names = "default";

				cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;

				norflash: flash@0 {
					compatible = "jedec,spi-nor";
					#address-cells = <1>;
					#size-cells = <1>;
					spi-max-frequency = <50000000>;
					reg = <0>;

					partition@0 {
						label = "RouterBoot";
						reg = <0x0 0x40000>;
					};
				};
			};
		};

		gpio-keys {
			compatible = "gpio-keys";
			pinctrl-0 = <&buttons_pins>;
			pinctrl-names = "default";

			button {
				label = "reset";
				linux,code = <KEY_RESTART>;
				gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>;
				linux,input-type = <1>;
				debounce-interval = <60>;
			};
		};

		leds {
			compatible = "gpio-leds";
			pinctrl-0 = <&leds_pins>;
			pinctrl-names = "default";

			led@7 {
				label = "rb3011:green:user";
				color = <LED_COLOR_ID_GREEN>;
				gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;
				default-state = "off";
			};
		};

	};
};

&adm_dma {
	status = "okay";
};

&gmac0 {
	status = "okay";

	phy-mode = "rgmii";
	qcom,id = <0>;
	phy-handle = <&switch0cpu>;

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&gmac3 {
	status = "okay";

	phy-mode = "sgmii";
	qcom,id = <3>;
	phy-handle = <&switch1cpu>;

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&gsbi7 {
	status = "okay";
	qcom,mode = <GSBI_PROT_I2C_UART>;
};

&gsbi7_serial {
	status = "okay";
};

&hs_phy_1 {
	status = "okay";
};

&nand {
	status = "okay";

	nand@0 {
		reg = <0>;

		nand-ecc-strength = <4>;
		nand-bus-width = <8>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			boot@0 {
				label = "RouterBoard NAND 1 Boot";
				reg = <0x0000000 0x0800000>;
			};

			main@800000 {
				label = "RouterBoard NAND 1 Main";
				reg = <0x0800000 0x7800000>;
			};
		};
	};
};

&qcom_pinmux {
	buttons_pins: buttons_pins {
		mux {
			pins = "gpio66";
			drive-strength = <16>;
			bias-disable;
		};
	};

	leds_pins: leds_pins {
		mux {
			pins = "gpio33";
			drive-strength = <16>;
			bias-disable;
		};
	};

	mdio1_pins: mdio1_pins {
		mux {
			pins = "gpio10", "gpio11";
			function = "gpio";
			drive-strength = <8>;
			bias-disable;
		};
	};

	sw0_reset_pin: sw0_reset_pin {
		mux {
			pins = "gpio16";
			drive-strength = <16>;
			function = "gpio";
			bias-disable;
			input-disable;
		};
	};

	sw1_reset_pin: sw1_reset_pin {
		mux {
			pins = "gpio17";
			drive-strength = <16>;
			function = "gpio";
			bias-disable;
			input-disable;
		};
	};

	usb1_pwr_en_pins: usb1_pwr_en_pins {
		mux {
			pins = "gpio4";
			function = "gpio";
			drive-strength = <16>;
			bias-disable;
			output-high;
		};
	};
};

&ss_phy_1 {
	status = "okay";
};

&usb3_1 {
	pinctrl-0 = <&usb1_pwr_en_pins>;
	pinctrl-names = "default";

	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0

#include "qcom-ipq8064.dtsi"

&rpm {
	smb208_regulators: regulators {
		compatible = "qcom,rpm-smb208-regulators";

		smb208_s1a: s1a {
			regulator-min-microvolt = <1050000>;
			regulator-max-microvolt = <1150000>;

			qcom,switch-mode-frequency = <1200000>;
		};

		smb208_s1b: s1b {
			regulator-min-microvolt = <1050000>;
			regulator-max-microvolt = <1150000>;

			qcom,switch-mode-frequency = <1200000>;
		};

		smb208_s2a: s2a {
			regulator-min-microvolt = < 800000>;
			regulator-max-microvolt = <1250000>;

			qcom,switch-mode-frequency = <1200000>;
		};

		smb208_s2b: s2b {
			regulator-min-microvolt = < 800000>;
			regulator-max-microvolt = <1250000>;

			qcom,switch-mode-frequency = <1200000>;
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

/ {
	model = "Qualcomm Technologies, Inc. IPQ8064-v1.0";

	aliases {
		serial0 = &gsbi4_serial;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	soc {
		gsbi@16300000 {
			qcom,mode = <GSBI_PROT_I2C_UART>;
			status = "okay";

			serial@16340000 {
				status = "okay";
			};
		};

		gsbi5: gsbi@1a200000 {
			qcom,mode = <GSBI_PROT_SPI>;
			status = "okay";

			spi4: spi@1a280000 {
				status = "okay";
				spi-max-frequency = <50000000>;

				pinctrl-0 = <&spi_pins>;
				pinctrl-names = "default";

				cs-gpios = <&qcom_pinmux 20 0>;

				flash: flash@0 {
					compatible = "s25fl256s1";
					#address-cells = <1>;
					#size-cells = <1>;
					spi-max-frequency = <50000000>;
					reg = <0>;

					partition@0 {
						label = "rootfs";
						reg = <0x0 0x1000000>;
					};

					partition@1 {
						label = "scratch";
						reg = <0x1000000 0x1000000>;
					};
				};
			};
		};

		sata-phy@1b400000 {
			status = "okay";
		};

		sata@29000000 {
			ports-implemented = <0x1>;
			status = "okay";
		};

		gpio-keys {
			compatible = "gpio-keys";
			pinctrl-0 = <&buttons_pins>;
			pinctrl-names = "default";

			button-1 {
				label = "reset";
				linux,code = <KEY_RESTART>;
				gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
				linux,input-type = <1>;
				debounce-interval = <60>;
			};
			button-2 {
				label = "wps";
				linux,code = <KEY_WPS_BUTTON>;
				gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
				linux,input-type = <1>;
				debounce-interval = <60>;
			};
		};

		leds {
			compatible = "gpio-leds";
			pinctrl-0 = <&leds_pins>;
			pinctrl-names = "default";

			led@7 {
				label = "led_usb1";
				gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
				linux,default-trigger = "usbdev";
				default-state = "off";
			};

			led@8 {
				label = "led_usb3";
				gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
				linux,default-trigger = "usbdev";
				default-state = "off";
			};

			led@9 {
				label = "status_led_fail";
				function = LED_FUNCTION_STATUS;
				gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
				default-state = "off";
			};

			led@26 {
				label = "sata_led";
				gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
				default-state = "off";
			};

			led@53 {
				label = "status_led_pass";
				function = LED_FUNCTION_STATUS;
				gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
				default-state = "off";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0

#include "qcom-ipq8064-v2.0.dtsi"

&rpm {
	smb208_regulators: regulators {
		compatible = "qcom,rpm-smb208-regulators";

		smb208_s1a: s1a {
			regulator-min-microvolt = <1050000>;
			regulator-max-microvolt = <1150000>;

			qcom,switch-mode-frequency = <1200000>;
		};

		smb208_s1b: s1b {
			regulator-min-microvolt = <1050000>;
			regulator-max-microvolt = <1150000>;

			qcom,switch-mode-frequency = <1200000>;
		};

		smb208_s2a: s2a {
			regulator-min-microvolt = < 800000>;
			regulator-max-microvolt = <1250000>;

			qcom,switch-mode-frequency = <1200000>;
		};

		smb208_s2b: s2b {
			regulator-min-microvolt = < 800000>;
			regulator-max-microvolt = <1250000>;

			qcom,switch-mode-frequency = <1200000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0

#include "qcom-ipq8064.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. IPQ8064-v2.0";

	aliases {
		serial0 = &gsbi4_serial;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		rsvd@41200000 {
			reg = <0x41200000 0x300000>;
			no-map;
		};
	};
};

&gsbi4 {
	qcom,mode = <GSBI_PROT_I2C_UART>;
	status = "okay";

	serial@16340000 {
		status = "okay";
	};
	/*
	 * The i2c device on gsbi4 should not be enabled.
	 * On ipq806x designs gsbi4 i2c is meant for exclusive
	 * RPM usage. Turning this on in kernel manifests as
	 * i2c failure for the RPM.
	 */
};

&pcie0 {
	compatible = "qcom,pcie-ipq8064-v2";
};

&pcie1 {
	compatible = "qcom,pcie-ipq8064-v2";
};

&pcie2 {
	compatible = "qcom,pcie-ipq8064-v2";
};

&sata {
	ports-implemented = <0x1>;
};

&ss_phy_0 {
	qcom,rx-eq = <2>;
	qcom,tx-deamp_3_5db = <32>;
	qcom,mpll = <5>;
};

&ss_phy_1 {
	qcom,rx-eq = <2>;
	qcom,tx-deamp_3_5db = <32>;
	qcom,mpll = <5>;
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm IPQ8064";
	compatible = "qcom,ipq8064";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
		};

		cpu1: cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	thermal-zones {
		sensor0-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens 0>;

			trips {
				cpu-critical {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "critical";
				};

				cpu-hot {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		sensor1-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens 1>;

			trips {
				cpu-critical {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "critical";
				};

				cpu-hot {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		sensor2-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens 2>;

			trips {
				cpu-critical {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "critical";
				};

				cpu-hot {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		sensor3-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens 3>;

			trips {
				cpu-critical {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "critical";
				};

				cpu-hot {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		sensor4-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens 4>;

			trips {
				cpu-critical {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "critical";
				};

				cpu-hot {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		sensor5-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens 5>;

			trips {
				cpu-critical {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "critical";
				};

				cpu-hot {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		sensor6-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens 6>;

			trips {
				cpu-critical {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "critical";
				};

				cpu-hot {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		sensor7-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens 7>;

			trips {
				cpu-critical {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "critical";
				};

				cpu-hot {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		sensor8-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens 8>;

			trips {
				cpu-critical {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "critical";
				};

				cpu-hot {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		sensor9-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens 9>;

			trips {
				cpu-critical {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "critical";
				};

				cpu-hot {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		sensor10-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens 10>;

			trips {
				cpu-critical {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "critical";
				};

				cpu-hot {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_HIGH)>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		nss@40000000 {
			reg = <0x40000000 0x1000000>;
			no-map;
		};

		smem: smem@41000000 {
			compatible = "qcom,smem";
			reg = <0x41000000 0x200000>;
			no-map;

			hwlocks = <&sfpb_mutex 3>;
		};
	};

	clocks {
		cxo_board: cxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		pxo_board: pxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			#clock-cells = <0>;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-ipq806x", "qcom,scm";
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		stmmac_axi_setup: stmmac-axi-config {
			snps,wr_osr_lmt = <7>;
			snps,rd_osr_lmt = <7>;
			snps,blen = <16 0 0 0 0 0 0>;
		};

		vsdcc_fixed: vsdcc-regulator {
			compatible = "regulator-fixed";
			regulator-name = "SDCC Power";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		rpm: rpm@108000 {
			compatible = "qcom,rpm-ipq8064";
			reg = <0x00108000 0x1000>;
			qcom,ipc = <&l2cc 0x8 2>;

			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ack", "err", "wakeup";

			clocks = <&gcc RPM_MSG_RAM_H_CLK>;
			clock-names = "ram";

			rpmcc: clock-controller {
				compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
				#clock-cells = <1>;
			};
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x00500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";
		};

		qfprom: qfprom@700000 {
			compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
			reg = <0x00700000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			speedbin_efuse: speedbin@c0 {
				reg = <0xc0 0x4>;
			};
			tsens_calib: calib@400 {
				reg = <0x400 0xb>;
			};
			tsens_calib_backup: calib_backup@410 {
				reg = <0x410 0xb>;
			};
		};

		qcom_pinmux: pinmux@800000 {
			compatible = "qcom,ipq8064-pinctrl";
			reg = <0x00800000 0x4000>;

			gpio-controller;
			gpio-ranges = <&qcom_pinmux 0 0 69>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

			pcie0_pins: pcie0_pinmux {
				mux {
					pins = "gpio3";
					function = "pcie1_rst";
					drive-strength = <12>;
					bias-disable;
				};
			};

			pcie1_pins: pcie1_pinmux {
				mux {
					pins = "gpio48";
					function = "pcie2_rst";
					drive-strength = <12>;
					bias-disable;
				};
			};

			pcie2_pins: pcie2_pinmux {
				mux {
					pins = "gpio63";
					function = "pcie3_rst";
					drive-strength = <12>;
					bias-disable;
				};
			};

			i2c4_pins: i2c4-default {
				pins = "gpio12", "gpio13";
				function = "gsbi4";
				drive-strength = <12>;
				bias-disable;
			};

			spi_pins: spi_pins {
				mux {
					pins = "gpio18", "gpio19", "gpio21";
					function = "gsbi5";
					drive-strength = <10>;
					bias-none;
				};
			};

			leds_pins: leds_pins {
				mux {
					pins = "gpio7", "gpio8", "gpio9",
					       "gpio26", "gpio53";
					function = "gpio";
					drive-strength = <2>;
					bias-pull-down;
					output-low;
				};
			};

			buttons_pins: buttons_pins {
				mux {
					pins = "gpio54";
					drive-strength = <2>;
					bias-pull-up;
				};
			};

			nand_pins: nand_pins {
				mux {
					pins = "gpio34", "gpio35", "gpio36",
					       "gpio37", "gpio38", "gpio39",
					       "gpio40", "gpio41", "gpio42",
					       "gpio43", "gpio44", "gpio45",
					       "gpio46", "gpio47";
					function = "nand";
					drive-strength = <10>;
					bias-disable;
				};

				pullups {
					pins = "gpio39";
					function = "nand";
					drive-strength = <10>;
					bias-pull-up;
				};

				hold {
					pins = "gpio40", "gpio41", "gpio42",
					       "gpio43", "gpio44", "gpio45",
					       "gpio46", "gpio47";
					function = "nand";
					drive-strength = <10>;
					bias-bus-hold;
				};
			};

			mdio0_pins: mdio0-pins {
				mux {
					pins = "gpio0", "gpio1";
					function = "mdio";
					drive-strength = <8>;
					bias-disable;
				};
			};

			rgmii2_pins: rgmii2-pins {
				mux {
					pins = "gpio27", "gpio28", "gpio29",
					       "gpio30", "gpio31", "gpio32",
					       "gpio51", "gpio52", "gpio59",
					       "gpio60", "gpio61", "gpio62";
					function = "rgmii2";
					drive-strength = <8>;
					bias-disable;
				};
			};
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-ipq8064", "syscon";
			clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
			clock-names = "pxo", "cxo", "pll4";
			reg = <0x00900000 0x4000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;

			tsens: thermal-sensor@900000 {
				compatible = "qcom,ipq8064-tsens";

				nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
				nvmem-cell-names = "calib", "calib_backup";
				interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "uplow";

				#qcom,sensors = <11>;
				#thermal-sensor-cells = <1>;
			};
		};

		sfpb_mutex: hwlock@1200600 {
			compatible = "qcom,sfpb-mutex";
			reg = <0x01200600 0x100>;

			#hwlock-cells = <1>;
		};

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-timer",
				     "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
			interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
						 IRQ_TYPE_EDGE_RISING)>,
				     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
						 IRQ_TYPE_EDGE_RISING)>,
				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
						 IRQ_TYPE_EDGE_RISING)>,
				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
						 IRQ_TYPE_EDGE_RISING)>,
				     <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
						 IRQ_TYPE_EDGE_RISING)>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <25000000>,
					  <32768>;
			clocks = <&sleep_clk>;
			clock-names = "sleep";
			cpu-offset = <0x80000>;
		};

		l2cc: clock-controller@2011000 {
			compatible = "qcom,kpss-gcc", "syscon";
			reg = <0x02011000 0x1000>;
			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
			clock-names = "pll8_vote", "pxo";
			clock-output-names = "acpu_l2_aux";
		};

		acc0: clock-controller@2088000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
		};

		saw0: regulator@2089000 {
			compatible = "qcom,saw2";
			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		acc1: clock-controller@2098000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
		};

		saw1: regulator@2099000 {
			compatible = "qcom,saw2";
			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		nss_common: syscon@03000000 {
			compatible = "syscon";
			reg = <0x03000000 0x0000FFFF>;
		};

		usb3_0: usb3@100f8800 {
			compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x100f8800 0x8000>;
			clocks = <&gcc USB30_0_MASTER_CLK>;
			clock-names = "core";

			ranges;

			resets = <&gcc USB30_0_MASTER_RESET>;
			reset-names = "master";

			status = "disabled";

			dwc3_0: dwc3@10000000 {
				compatible = "snps,dwc3";
				reg = <0x10000000 0xcd00>;
				interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&hs_phy_0>, <&ss_phy_0>;
				phy-names = "usb2-phy", "usb3-phy";
				dr_mode = "host";
				snps,dis_u3_susphy_quirk;
			};
		};

		hs_phy_0: phy@100f8800 {
			compatible = "qcom,ipq806x-usb-phy-hs";
			reg = <0x100f8800 0x30>;
			clocks = <&gcc USB30_0_UTMI_CLK>;
			clock-names = "ref";
			#phy-cells = <0>;

			status = "disabled";
		};

		ss_phy_0: phy@100f8830 {
			compatible = "qcom,ipq806x-usb-phy-ss";
			reg = <0x100f8830 0x30>;
			clocks = <&gcc USB30_0_MASTER_CLK>;
			clock-names = "ref";
			#phy-cells = <0>;

			status = "disabled";
		};

		usb3_1: usb3@110f8800 {
			compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x110f8800 0x8000>;
			clocks = <&gcc USB30_1_MASTER_CLK>;
			clock-names = "core";

			ranges;

			resets = <&gcc USB30_1_MASTER_RESET>;
			reset-names = "master";

			status = "disabled";

			dwc3_1: dwc3@11000000 {
				compatible = "snps,dwc3";
				reg = <0x11000000 0xcd00>;
				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&hs_phy_1>, <&ss_phy_1>;
				phy-names = "usb2-phy", "usb3-phy";
				dr_mode = "host";
				snps,dis_u3_susphy_quirk;
			};
		};

		hs_phy_1: phy@110f8800 {
			compatible = "qcom,ipq806x-usb-phy-hs";
			reg = <0x110f8800 0x30>;
			clocks = <&gcc USB30_1_UTMI_CLK>;
			clock-names = "ref";
			#phy-cells = <0>;

			status = "disabled";
		};

		ss_phy_1: phy@110f8830 {
			compatible = "qcom,ipq806x-usb-phy-ss";
			reg = <0x110f8830 0x30>;
			clocks = <&gcc USB30_1_MASTER_CLK>;
			clock-names = "ref";
			#phy-cells = <0>;

			status = "disabled";
		};

		sdcc3bam: dma-controller@12182000 {
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12182000 0x8000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC3_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc1bam: dma-controller@12402000 {
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12402000 0x8000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC1_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		amba: amba {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			sdcc3: mmc@12180000 {
				compatible = "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status = "disabled";
				reg = <0x12180000 0x2000>;
				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
				clock-names = "mclk", "apb_pclk";
				bus-width = <8>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency = <192000000>;
				sd-uhs-sdr104;
				sd-uhs-ddr50;
				vqmmc-supply = <&vsdcc_fixed>;
				dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
				dma-names = "tx", "rx";
			};

			sdcc1: mmc@12400000 {
				status = "disabled";
				compatible = "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg = <0x12400000 0x2000>;
				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
				clock-names = "mclk", "apb_pclk";
				bus-width = <8>;
				max-frequency = <96000000>;
				non-removable;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				vmmc-supply = <&vsdcc_fixed>;
				dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
				dma-names = "tx", "rx";
			};
		};

		gsbi1: gsbi@12440000 {
			compatible = "qcom,gsbi-v1.0.0";
			reg = <0x12440000 0x100>;
			cell-index = <1>;
			clocks = <&gcc GSBI1_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			status = "disabled";

			gsbi1_serial: serial@12450000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x12450000 0x100>,
				      <0x12400000 0x03>;
				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";

				status = "disabled";
			};

			gsbi1_i2c: i2c@12460000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x12460000 0x1000>;
				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};
		};

		gsbi2: gsbi@12480000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <2>;
			reg = <0x12480000 0x100>;
			clocks = <&gcc GSBI2_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			syscon-tcsr = <&tcsr>;

			gsbi2_serial: serial@12490000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x12490000 0x1000>,
				      <0x12480000 0x1000>;
				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi2_i2c: i2c@124a0000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x124a0000 0x1000>;
				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";

				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi4: gsbi@16300000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <4>;
			reg = <0x16300000 0x100>;
			clocks = <&gcc GSBI4_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			syscon-tcsr = <&tcsr>;

			gsbi4_serial: serial@16340000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16340000 0x1000>,
				      <0x16300000 0x1000>;
				interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			i2c@16380000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x16380000 0x1000>;
				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";

				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi6: gsbi@16500000 {
			compatible = "qcom,gsbi-v1.0.0";
			reg = <0x16500000 0x100>;
			cell-index = <6>;
			clocks = <&gcc GSBI6_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			status = "disabled";

			gsbi6_i2c: i2c@16580000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x16580000 0x1000>;
				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
				clock-names = "core", "iface";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};

			gsbi6_spi: spi@16580000 {
				compatible = "qcom,spi-qup-v1.1.1";
				reg = <0x16580000 0x1000>;
				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
				clock-names = "core", "iface";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};
		};

		gsbi7: gsbi@16600000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <7>;
			reg = <0x16600000 0x100>;
			clocks = <&gcc GSBI7_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			syscon-tcsr = <&tcsr>;

			gsbi7_serial: serial@16640000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16640000 0x1000>,
				      <0x16600000 0x1000>;
				interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi7_i2c: i2c@16680000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x16680000 0x1000>;
				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};
		};

		adm_dma: dma-controller@18300000 {
			compatible = "qcom,adm";
			reg = <0x18300000 0x100000>;
			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;

			clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
			clock-names = "core", "iface";

			resets = <&gcc ADM0_RESET>,
				 <&gcc ADM0_PBUS_RESET>,
				 <&gcc ADM0_C0_RESET>,
				 <&gcc ADM0_C1_RESET>,
				 <&gcc ADM0_C2_RESET>;
			reset-names = "clk", "pbus", "c0", "c1", "c2";
			qcom,ee = <0>;

			status = "disabled";
		};

		gsbi5: gsbi@1a200000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <5>;
			reg = <0x1a200000 0x100>;
			clocks = <&gcc GSBI5_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;

			#size-cells = <1>;
			ranges;
			status = "disabled";

			syscon-tcsr = <&tcsr>;

			gsbi5_serial: serial@1a240000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x1a240000 0x1000>,
				      <0x1a200000 0x1000>;
				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			i2c@1a280000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x1a280000 0x1000>;
				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";

				#address-cells = <1>;
				#size-cells = <0>;
			};

			spi@1a280000 {
				compatible = "qcom,spi-qup-v1.1.1";
				reg = <0x1a280000 0x1000>;
				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";

				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-ipq8064", "syscon";
			reg = <0x1a400000 0x100>;
		};

		rng@1a500000 {
			compatible = "qcom,prng";
			reg = <0x1a500000 0x200>;
			clocks = <&gcc PRNG_CLK>;
			clock-names = "core";
		};

		nand: nand-controller@1ac00000 {
			compatible = "qcom,ipq806x-nand";
			reg = <0x1ac00000 0x800>;

			pinctrl-0 = <&nand_pins>;
			pinctrl-names = "default";

			clocks = <&gcc EBI2_CLK>,
				 <&gcc EBI2_AON_CLK>;
			clock-names = "core", "aon";

			dmas = <&adm_dma 3>;
			dma-names = "rxtx";
			qcom,cmd-crci = <15>;
			qcom,data-crci = <3>;

			#address-cells = <1>;
			#size-cells = <0>;

			status = "disabled";
		};

		sata_phy: sata-phy@1b400000 {
			compatible = "qcom,ipq806x-sata-phy";
			reg = <0x1b400000 0x200>;

			clocks = <&gcc SATA_PHY_CFG_CLK>;
			clock-names = "cfg";

			#phy-cells = <0>;
			status = "disabled";
		};

		pcie0: pci@1b500000 {
			compatible = "qcom,pcie-ipq8064";
			reg = <0x1b500000 0x1000
			       0x1b502000 0x80
			       0x1b600000 0x100
			       0x0ff00000 0x100000>;
			reg-names = "dbi", "elbi", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000   /* downstream I/O */
				  0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */

			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

			clocks = <&gcc PCIE_A_CLK>,
				 <&gcc PCIE_H_CLK>,
				 <&gcc PCIE_PHY_CLK>,
				 <&gcc PCIE_AUX_CLK>,
				 <&gcc PCIE_ALT_REF_CLK>;
			clock-names = "core", "iface", "phy", "aux", "ref";

			assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
			assigned-clock-rates = <100000000>;

			resets = <&gcc PCIE_ACLK_RESET>,
				 <&gcc PCIE_HCLK_RESET>,
				 <&gcc PCIE_POR_RESET>,
				 <&gcc PCIE_PCI_RESET>,
				 <&gcc PCIE_PHY_RESET>,
				 <&gcc PCIE_EXT_RESET>;
			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";

			pinctrl-0 = <&pcie0_pins>;
			pinctrl-names = "default";

			status = "disabled";
			perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
		};

		pcie1: pci@1b700000 {
			compatible = "qcom,pcie-ipq8064";
			reg = <0x1b700000 0x1000
			       0x1b702000 0x80
			       0x1b800000 0x100
			       0x31f00000 0x100000>;
			reg-names = "dbi", "elbi", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <1>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000   /* downstream I/O */
				  0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */

			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

			clocks = <&gcc PCIE_1_A_CLK>,
				 <&gcc PCIE_1_H_CLK>,
				 <&gcc PCIE_1_PHY_CLK>,
				 <&gcc PCIE_1_AUX_CLK>,
				 <&gcc PCIE_1_ALT_REF_CLK>;
			clock-names = "core", "iface", "phy", "aux", "ref";

			assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
			assigned-clock-rates = <100000000>;

			resets = <&gcc PCIE_1_ACLK_RESET>,
				 <&gcc PCIE_1_HCLK_RESET>,
				 <&gcc PCIE_1_POR_RESET>,
				 <&gcc PCIE_1_PCI_RESET>,
				 <&gcc PCIE_1_PHY_RESET>,
				 <&gcc PCIE_1_EXT_RESET>;
			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";

			pinctrl-0 = <&pcie1_pins>;
			pinctrl-names = "default";

			status = "disabled";
			perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
		};

		pcie2: pci@1b900000 {
			compatible = "qcom,pcie-ipq8064";
			reg = <0x1b900000 0x1000
			       0x1b902000 0x80
			       0x1ba00000 0x100
			       0x35f00000 0x100000>;
			reg-names = "dbi", "elbi", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <2>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000   /* downstream I/O */
				  0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */

			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

			clocks = <&gcc PCIE_2_A_CLK>,
				 <&gcc PCIE_2_H_CLK>,
				 <&gcc PCIE_2_PHY_CLK>,
				 <&gcc PCIE_2_AUX_CLK>,
				 <&gcc PCIE_2_ALT_REF_CLK>;
			clock-names = "core", "iface", "phy", "aux", "ref";

			assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
			assigned-clock-rates = <100000000>;

			resets = <&gcc PCIE_2_ACLK_RESET>,
				 <&gcc PCIE_2_HCLK_RESET>,
				 <&gcc PCIE_2_POR_RESET>,
				 <&gcc PCIE_2_PCI_RESET>,
				 <&gcc PCIE_2_PHY_RESET>,
				 <&gcc PCIE_2_EXT_RESET>;
			reset-names = "axi", "ahb", "por", "pci", "phy", "ext";

			pinctrl-0 = <&pcie2_pins>;
			pinctrl-names = "default";

			status = "disabled";
			perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
		};

		qsgmii_csr: syscon@1bb00000 {
			compatible = "syscon";
			reg = <0x1bb00000 0x000001FF>;
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-ipq8064";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		lpass@28100000 {
			compatible = "qcom,lpass-cpu";
			status = "disabled";
			clocks = <&lcc AHBIX_CLK>,
					<&lcc MI2S_OSR_CLK>,
					<&lcc MI2S_BIT_CLK>;
			clock-names = "ahbix-clk",
					"mi2s-osr-clk",
					"mi2s-bit-clk";
			interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "lpass-irq-lpaif";
			reg = <0x28100000 0x10000>;
			reg-names = "lpass-lpaif";
		};

		sata: sata@29000000 {
			compatible = "qcom,ipq806x-ahci", "generic-ahci";
			reg = <0x29000000 0x180>;

			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc SFAB_SATA_S_H_CLK>,
				 <&gcc SATA_H_CLK>,
				 <&gcc SATA_A_CLK>,
				 <&gcc SATA_RXOOB_CLK>,
				 <&gcc SATA_PMALIVE_CLK>;
			clock-names = "slave_face", "iface", "core",
					"rxoob", "pmalive";

			assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
			assigned-clock-rates = <100000000>, <100000000>;

			phys = <&sata_phy>;
			phy-names = "sata-phy";
			status = "disabled";
		};

		gmac0: ethernet@37000000 {
			device_type = "network";
			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
			reg = <0x37000000 0x200000>;
			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";

			snps,axi-config = <&stmmac_axi_setup>;
			snps,pbl = <32>;
			snps,aal;

			qcom,nss-common = <&nss_common>;
			qcom,qsgmii-csr = <&qsgmii_csr>;

			clocks = <&gcc GMAC_CORE1_CLK>;
			clock-names = "stmmaceth";

			resets = <&gcc GMAC_CORE1_RESET>,
				 <&gcc GMAC_AHB_RESET>;
			reset-names = "stmmaceth", "ahb";

			status = "disabled";
		};

		gmac1: ethernet@37200000 {
			device_type = "network";
			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
			reg = <0x37200000 0x200000>;
			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";

			snps,axi-config = <&stmmac_axi_setup>;
			snps,pbl = <32>;
			snps,aal;

			qcom,nss-common = <&nss_common>;
			qcom,qsgmii-csr = <&qsgmii_csr>;

			clocks = <&gcc GMAC_CORE2_CLK>;
			clock-names = "stmmaceth";

			resets = <&gcc GMAC_CORE2_RESET>,
				 <&gcc GMAC_AHB_RESET>;
			reset-names = "stmmaceth", "ahb";

			status = "disabled";
		};

		gmac2: ethernet@37400000 {
			device_type = "network";
			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
			reg = <0x37400000 0x200000>;
			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";

			snps,axi-config = <&stmmac_axi_setup>;
			snps,pbl = <32>;
			snps,aal;

			qcom,nss-common = <&nss_common>;
			qcom,qsgmii-csr = <&qsgmii_csr>;

			clocks = <&gcc GMAC_CORE3_CLK>;
			clock-names = "stmmaceth";

			resets = <&gcc GMAC_CORE3_RESET>,
				 <&gcc GMAC_AHB_RESET>;
			reset-names = "stmmaceth", "ahb";

			status = "disabled";
		};

		gmac3: ethernet@37600000 {
			device_type = "network";
			compatible = "qcom,ipq806x-gmac", "snps,dwmac";
			reg = <0x37600000 0x200000>;
			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";

			snps,axi-config = <&stmmac_axi_setup>;
			snps,pbl = <32>;
			snps,aal;

			qcom,nss-common = <&nss_common>;
			qcom,qsgmii-csr = <&qsgmii_csr>;

			clocks = <&gcc GMAC_CORE4_CLK>;
			clock-names = "stmmaceth";

			resets = <&gcc GMAC_CORE4_RESET>,
				 <&gcc GMAC_AHB_RESET>;
			reset-names = "stmmaceth", "ahb";

			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0

#include "qcom-ipq8065.dtsi"

&rpm {
	smb208_regulators: regulators {
		compatible = "qcom,rpm-smb208-regulators";

		smb208_s1a: s1a {
			regulator-min-microvolt = <1050000>;
			regulator-max-microvolt = <1150000>;

			qcom,switch-mode-frequency = <1200000>;
		};

		smb208_s1b: s1b {
			regulator-min-microvolt = <1050000>;
			regulator-max-microvolt = <1150000>;

			qcom,switch-mode-frequency = <1200000>;
		};

		smb208_s2a: s2a {
			regulator-min-microvolt = <775000>;
			regulator-max-microvolt = <1275000>;

			qcom,switch-mode-frequency = <1200000>;
		};

		smb208_s2b: s2b {
			regulator-min-microvolt = <775000>;
			regulator-max-microvolt = <1275000>;

			qcom,switch-mode-frequency = <1200000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0

#include "qcom-ipq8064-v2.0.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. IPQ8065";
	compatible = "qcom,ipq8065", "qcom,ipq8064";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Device Tree Source for mangOH Green Board with WP8548 Module
 *
 * Copyright (C) 2016 BayLibre, SAS.
 * Author : Neil Armstrong <narmstrong@baylibre.com>
 */

#include <dt-bindings/input/input.h>

#include "qcom-mdm9615-wp8548.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "MangOH Green with WP8548 Module";
	compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615";

	aliases {
		spi0 = &gsbi3_spi;
		serial0 = &gsbi4_serial;
		serial1 = &gsbi5_serial;
		i2c0 = &gsbi5_i2c;
		mmc0 = &sdcc1;
	};

	chosen {
		stdout-path = "serial1:115200n8";
	};
};

&msmgpio {
	/* MangOH GPIO Mapping :
	 * - 2 : GPIOEXP_INT2
	 * - 7 : IOT1_GPIO2
	 * - 8 : IOT0_GPIO4
	 * - 13: IOT0_GPIO3
	 * - 21: IOT1_GPIO4
	 * - 22: IOT2_GPIO1
	 * - 23: IOT2_GPIO2
	 * - 24: IOT2_GPIO3
	 * - 25: IOT1_GPIO1
	 * - 32: IOT1_GPIO3
	 * - 33: IOT0_GPIO2
	 * - 42: IOT0_GPIO1 and SD Card Detect
	 */

	gpioext1_pins: gpioext1-state {
		gpioext1-pins {
			pins = "gpio2";
			function = "gpio";
			input-enable;
			bias-disable;
		};
	};

	sdc_cd_pins: sdc-cd-state {
		sdc-cd-pins {
			pins = "gpio42";
			function = "gpio";
			drive-strength = <2>;
			bias-pull-up;
		};
	};
};

&gsbi3_spi {
	spi@0 {
		compatible = "swir,mangoh-iotport-spi";
		spi-max-frequency = <24000000>;
		reg = <0>;
	};
};

&gsbi5_i2c {
	mux@71 {
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x71>;

		i2c_iot0: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		i2c_iot1: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};

		i2c_iot2: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;

			usbhub: hub@8 {
				compatible = "smsc,usb3503a";
				reg = <0x8>;
				connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>;
				intn-gpios = <&gpioext2 0 GPIO_ACTIVE_HIGH>;
				initial-mode = <1>;
			};
		};

		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;

			gpioext0: pinctrl@3e {
				/* GPIO Expander 0 Mapping :
				 * - 0: ARDUINO_RESET_Level shift
				 * - 1: BattChrgr_PG_N
				 * - 2: BattGauge_GPIO
				 * - 3: LED_ON (out active high)
				 * - 4: ATmega_reset_GPIO
				 * - 5: X
				 * - 6: PCM_ANALOG_SELECT (out active high)
				 * - 7: X
				 * - 8: Board_rev_res1 (in)
				 * - 9: Board_rev_res2 (in)
				 * - 10: UART_EXP1_ENn (out active low / pull-down)
				 * - 11: UART_EXP1_IN (out pull-down)
				 * - 12: UART_EXP2_IN (out pull-down)
				 * - 13: SDIO_SEL (out pull-down)
				 * - 14: SPI_EXP1_ENn (out active low / pull-down)
				 * - 15: SPI_EXP1_IN (out pull-down)
				 */
				#gpio-cells = <2>;
				#interrupt-cells = <2>;
				compatible = "semtech,sx1509q";
				reg = <0x3e>;
				interrupt-parent = <&gpioext1>;
				interrupts = <0 IRQ_TYPE_EDGE_FALLING>;

				semtech,probe-reset;

				gpio-controller;
				interrupt-controller;
			};
		};

		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;

			gpioext1: pinctrl@3f {
				/* GPIO Expander 1 Mapping :
				 * - 0: GPIOEXP_INT1
				 * - 1: Battery detect
				 * - 2: GPIO_SCF3_RESET
				 * - 3: LED_CARD_DETECT_IOT0 (in)
				 * - 4: LED_CARD_DETECT_IOT1 (in)
				 * - 5: LED_CARD_DETECT_IOT2 (in)
				 * - 6: UIM2_PWM_SELECT
				 * - 7: UIM2_M2_S_SELECT
				 * - 8: TP900
				 * - 9: SENSOR_INT1 (in)
				 * - 10: SENSOR_INT2 (in)
				 * - 11: CARD_DETECT_IOT0 (in pull-up)
				 * - 12: CARD_DETECT_IOT2 (in pull-up)
				 * - 13: CARD_DETECT_IOT1 (in pull-up)
				 * - 14: GPIOEXP_INT3 (in active low / pull-up)
				 * - 15: BattChrgr_INT_N
				 */
				pinctrl-0 = <&gpioext1_pins>;
				pinctrl-names = "default";

				#gpio-cells = <2>;
				#interrupt-cells = <2>;
				compatible = "semtech,sx1509q";
				reg = <0x3f>;
				interrupt-parent = <&msmgpio>;
				interrupts = <0 IRQ_TYPE_EDGE_FALLING>;

				semtech,probe-reset;

				gpio-controller;
				interrupt-controller;
			};
		};

		i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;

			gpioext2: pinctrl@70 {
				/* GPIO Expander 2 Mapping :
				 * - 0: USB_HUB_INTn
				 * - 1: HUB_CONNECT
				 * - 2: GPIO_IOT2_RESET (out active low / pull-up)
				 * - 3: GPIO_IOT1_RESET (out active low / pull-up)
				 * - 4: GPIO_IOT0_RESET (out active low / pull-up)
				 * - 5: TP901
				 * - 6: TP902
				 * - 7: TP903
				 * - 8: UART_EXP2_ENn (out active low / pull-down)
				 * - 9: PCM_EXP1_ENn (out active low)
				 * - 10: PCM_EXP1_SEL (out)
				 * - 11: ARD_FTDI
				 * - 12: TP904
				 * - 13: TP905
				 * - 14: TP906
				 * - 15: RS232_Enable (out active high / pull-up)
				 */
				#gpio-cells = <2>;
				#interrupt-cells = <2>;
				compatible = "semtech,sx1509q";
				reg = <0x70>;
				interrupt-parent = <&gpioext1>;
				interrupts = <14 IRQ_TYPE_EDGE_FALLING>;

				semtech,probe-reset;

				gpio-controller;
				interrupt-controller;
			};
		};

		i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <7>;
		};
	};
};

&sdcc1 {
	pinctrl-0 = <&sdc_cd_pins>;
	pinctrl-names = "default";
	disable-wp;
	cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Device Tree Source for Sierra Wireless WP8548 Module
 *
 * Copyright (C) 2016 BayLibre, SAS.
 * Author : Neil Armstrong <narmstrong@baylibre.com>
 */

#include "qcom-mdm9615.dtsi"

/ {
	model = "Sierra Wireless WP8548 Module";
	compatible = "swir,wp8548", "qcom,mdm9615";

	memory@48000000 {
		device_type = "memory";
		reg = <0x48000000 0x7F00000>;
	};
};

&msmgpio {
	pinctrl-0 = <&reset_out_pins>;
	pinctrl-names = "default";

	gsbi3_pins: gsbi3-state {
		gsbi3-pins {
			pins = "gpio8", "gpio9", "gpio10", "gpio11";
			function = "gsbi3";
			drive-strength = <8>;
			bias-disable;
		};
	};

	gsbi4_pins: gsbi4-state {
		gsbi4-pins {
			pins = "gpio12", "gpio13", "gpio14", "gpio15";
			function = "gsbi4";
			drive-strength = <8>;
			bias-disable;
		};
	};

	gsbi5_i2c_pins: gsbi5-i2c-state {
		sda-pins {
			pins = "gpio16";
			function = "gsbi5_i2c";
			drive-strength = <8>;
			bias-disable;
		};

		scl-pins {
			pins = "gpio17";
			function = "gsbi5_i2c";
			drive-strength = <2>;
			bias-disable;
		};
	};

	gsbi5_uart_pins: gsbi5-uart-state {
		gsbi5-uart-pins {
			pins = "gpio18", "gpio19";
			function = "gsbi5_uart";
			drive-strength = <8>;
			bias-disable;
		};
	};

	reset_out_pins: reset-out-state {
		reset-out-pins {
			pins = "gpio66";
			function = "gpio";
			drive-strength = <2>;
			bias-pull-up;
			output-high;
		};
	};
};

&pmicgpio {
	usb_vbus_5v_pins: usb-vbus-5v-state {
		pins = "gpio4";
		function = "normal";
		output-high;
		bias-disable;
		qcom,drive-strength = <1>;
		power-source = <2>;
	};
};

&gsbi3 {
	status = "okay";
	qcom,mode = <GSBI_PROT_SPI>;
};

&gsbi3_spi {
	status = "okay";
	pinctrl-0 = <&gsbi3_pins>;
	pinctrl-names = "default";
	assigned-clocks = <&gcc GSBI3_QUP_CLK>;
	assigned-clock-rates = <24000000>;
};

&gsbi4 {
	status = "okay";
	qcom,mode = <GSBI_PROT_UART_W_FC>;
};

&gsbi4_serial {
	status = "okay";
	pinctrl-0 = <&gsbi4_pins>;
	pinctrl-names = "default";
};

&gsbi5 {
	status = "okay";
	qcom,mode = <GSBI_PROT_I2C_UART>;
};

&gsbi5_i2c {
	status = "okay";
	clock-frequency = <200000>;
	pinctrl-0 = <&gsbi5_i2c_pins>;
	pinctrl-names = "default";
};

&gsbi5_serial {
	status = "okay";
	pinctrl-0 = <&gsbi5_uart_pins>;
	pinctrl-names = "default";
};

&sdcc1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Device Tree Source for Qualcomm MDM9615 SoC
 *
 * Copyright (C) 2016 BayLibre, SAS.
 * Author : Neil Armstrong <narmstrong@baylibre.com>
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-mdm9615.h>
#include <dt-bindings/reset/qcom,gcc-mdm9615.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/soc/qcom,gsbi.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm MDM9615";
	compatible = "qcom,mdm9615";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a5";
			reg = <0>;
			device_type = "cpu";
			next-level-cache = <&L2>;
		};
	};

	cpu-pmu {
		compatible = "arm,cortex-a5-pmu";
		interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	clocks {
		cxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};
	};

	regulators {
		vsdcc_fixed: vsdcc-regulator {
			compatible = "regulator-fixed";
			regulator-name = "SDCC Power";
			regulator-min-microvolt = <2700000>;
			regulator-max-microvolt = <2700000>;
			regulator-always-on;
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		L2: cache-controller@2040000 {
			compatible = "arm,pl310-cache";
			reg = <0x02040000 0x1000>;
			arm,data-latency = <2 2 0>;
			cache-unified;
			cache-level = <2>;
		};

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-timer", "qcom,msm-timer";
			interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
				     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x80000>;
		};

		msmgpio: pinctrl@800000 {
			compatible = "qcom,mdm9615-pinctrl";
			gpio-controller;
			gpio-ranges = <&msmgpio 0 0 88>;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x800000 0x4000>;
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-mdm9615";
			#clock-cells = <1>;
			#power-domain-cells = <1>;
			#reset-cells = <1>;
			reg = <0x900000 0x4000>;
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-mdm9615";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		l2cc: clock-controller@2011000 {
			compatible = "qcom,kpss-gcc", "syscon";
			reg = <0x02011000 0x1000>;
		};

		rng@1a500000 {
			compatible = "qcom,prng";
			reg = <0x1a500000 0x200>;
			clocks = <&gcc PRNG_CLK>;
			clock-names = "core";
			assigned-clocks = <&gcc PRNG_CLK>;
			assigned-clock-rates = <32000000>;
		};

		gsbi2: gsbi@16100000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <2>;
			reg = <0x16100000 0x100>;
			clocks = <&gcc GSBI2_H_CLK>;
			clock-names = "iface";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gsbi2_i2c: i2c@16180000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x16180000 0x1000>;
				interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi3: gsbi@16200000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <3>;
			reg = <0x16200000 0x100>;
			clocks = <&gcc GSBI3_H_CLK>;
			clock-names = "iface";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gsbi3_spi: spi@16280000 {
				compatible = "qcom,spi-qup-v1.1.1";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x16280000 0x1000>;
				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi4: gsbi@16300000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <4>;
			reg = <0x16300000 0x100>;
			clocks = <&gcc GSBI4_H_CLK>;
			clock-names = "iface";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi4_serial: serial@16340000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16340000 0x1000>,
				      <0x16300000 0x1000>;
				interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi5: gsbi@16400000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <5>;
			reg = <0x16400000 0x100>;
			clocks = <&gcc GSBI5_H_CLK>;
			clock-names = "iface";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi5_i2c: i2c@16480000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x16480000 0x1000>;
				interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

				/* QUP clock is not initialized, set rate */
				assigned-clocks = <&gcc GSBI5_QUP_CLK>;
				assigned-clock-rates = <24000000>;

				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi5_serial: serial@16440000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16440000 0x1000>,
				      <0x16400000 0x1000>;
				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";

			pmicintc: pmic {
				compatible = "qcom,pm8018", "qcom,pm8921";
				interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <2>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;

				pwrkey@1c {
					compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
					reg = <0x1c>;
					interrupt-parent = <&pmicintc>;
					interrupts = <50 IRQ_TYPE_EDGE_RISING>,
						     <51 IRQ_TYPE_EDGE_RISING>;
					debounce = <15625>;
					pull-up;
				};

				pmicmpp: mpps@50 {
					compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
					interrupt-controller;
					#interrupt-cells = <2>;
					reg = <0x50>;
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&pmicmpp 0 0 6>;
				};

				rtc@11d {
					compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
					interrupt-parent = <&pmicintc>;
					interrupts = <39 IRQ_TYPE_EDGE_RISING>;
					reg = <0x11d>;
					allow-set-time;
				};

				pmicgpio: gpio@150 {
					compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
					reg = <0x150>;
					interrupt-controller;
					#interrupt-cells = <2>;
					gpio-controller;
					gpio-ranges = <&pmicgpio 0 0 6>;
					#gpio-cells = <2>;
				};
			};
		};

		sdcc1bam: dma-controller@12182000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12182000 0x8000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC1_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc2bam: dma-controller@12142000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12142000 0x8000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC2_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc1: mmc@12180000 {
			status = "disabled";
			compatible = "arm,pl18x", "arm,primecell";
			arm,primecell-periphid = <0x00051180>;
			reg = <0x12180000 0x2000>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
			clock-names = "mclk", "apb_pclk";
			bus-width = <8>;
			max-frequency = <48000000>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			vmmc-supply = <&vsdcc_fixed>;
			dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
			dma-names = "tx", "rx";
			assigned-clocks = <&gcc SDC1_CLK>;
			assigned-clock-rates = <400000>;
		};

		sdcc2: mmc@12140000 {
			compatible = "arm,pl18x", "arm,primecell";
			arm,primecell-periphid = <0x00051180>;
			status = "disabled";
			reg = <0x12140000 0x2000>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
			clock-names = "mclk", "apb_pclk";
			bus-width = <4>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			max-frequency = <48000000>;
			no-1-8-v;
			vmmc-supply = <&vsdcc_fixed>;
			dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
			dma-names = "tx", "rx";
			assigned-clocks = <&gcc SDC2_CLK>;
			assigned-clock-rates = <400000>;
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-mdm9615", "syscon";
			reg = <0x1a400000 0x100>;
		};

		rpm: rpm@108000 {
			compatible = "qcom,rpm-mdm9615";
			reg = <0x108000 0x1000>;

			qcom,ipc = <&l2cc 0x8 2>;

			interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "ack", "err", "wakeup";

			regulators {
				compatible = "qcom,rpm-pm8018-regulators";

				vin_lvs1-supply = <&pm8018_s3>;

				vdd_l7-supply = <&pm8018_s4>;
				vdd_l8-supply = <&pm8018_s3>;
				vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;

				/* Buck SMPS */
				pm8018_s1: s1 {
					regulator-min-microvolt = <500000>;
					regulator-max-microvolt = <1150000>;
					qcom,switch-mode-frequency = <1600000>;
					bias-pull-down;
				};

				pm8018_s2: s2 {
					regulator-min-microvolt = <1225000>;
					regulator-max-microvolt = <1300000>;
					qcom,switch-mode-frequency = <1600000>;
					bias-pull-down;
				};

				pm8018_s3: s3 {
					regulator-always-on;
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					qcom,switch-mode-frequency = <1600000>;
					bias-pull-down;
				};

				pm8018_s4: s4 {
					regulator-min-microvolt = <2100000>;
					regulator-max-microvolt = <2200000>;
					qcom,switch-mode-frequency = <1600000>;
					bias-pull-down;
				};

				pm8018_s5: s5 {
					regulator-always-on;
					regulator-min-microvolt = <1350000>;
					regulator-max-microvolt = <1350000>;
					qcom,switch-mode-frequency = <1600000>;
					bias-pull-down;
				};

				/* PMOS LDO */
				pm8018_l2: l2 {
					regulator-always-on;
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					bias-pull-down;
				};

				pm8018_l3: l3 {
					regulator-always-on;
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					bias-pull-down;
				};

				pm8018_l4: l4 {
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					bias-pull-down;
				};

				pm8018_l5: l5 {
					regulator-min-microvolt = <2850000>;
					regulator-max-microvolt = <2850000>;
					bias-pull-down;
				};

				pm8018_l6: l6 {
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <2850000>;
					bias-pull-down;
				};

				pm8018_l7: l7 {
					regulator-min-microvolt = <1850000>;
					regulator-max-microvolt = <1900000>;
					bias-pull-down;
				};

				pm8018_l8: l8 {
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					bias-pull-down;
				};

				pm8018_l9: l9 {
					regulator-min-microvolt = <750000>;
					regulator-max-microvolt = <1150000>;
					bias-pull-down;
				};

				pm8018_l10: l10 {
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
					bias-pull-down;
				};

				pm8018_l11: l11 {
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
					bias-pull-down;
				};

				pm8018_l12: l12 {
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
					bias-pull-down;
				};

				pm8018_l13: l13 {
					regulator-min-microvolt = <1850000>;
					regulator-max-microvolt = <2950000>;
					bias-pull-down;
				};

				pm8018_l14: l14 {
					regulator-min-microvolt = <2850000>;
					regulator-max-microvolt = <2850000>;
					bias-pull-down;
				};

				/* Low Voltage Switch */
				pm8018_lvs1: lvs1 {
					bias-pull-down;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
 */

#include "qcom-msm8226.dtsi"

/ {
	model = "Samsung Galaxy S III Neo";
	compatible = "samsung,s3ve3g", "qcom,msm8226";
	chassis-type = "handset";

	aliases {
		serial0 = &blsp1_uart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&blsp1_uart3 {
	status = "ok";
};


code:
// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,gcc-msm8974.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&intc>;

	chosen { };

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-msm8226", "qcom,scm";
			clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
			clock-names = "core", "bus", "iface";
		};
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		smem_region: smem@3000000 {
			reg = <0x3000000 0x100000>;
			no-map;
		};

		adsp_region: adsp@dc00000 {
			reg = <0x0dc00000 0x1900000>;
			no-map;
		};
	};

	smd {
		compatible = "qcom,smd";

		rpm {
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			rpm_requests: rpm-requests {
				compatible = "qcom,rpm-msm8226";
				qcom,smd-channels = "rpm_requests";

				rpmpd: power-controller {
					compatible = "qcom,msm8226-rpmpd";
					#power-domain-cells = <1>;
					operating-points-v2 = <&rpmpd_opp_table>;

					rpmpd_opp_table: opp-table {
						compatible = "operating-points-v2";

						rpmpd_opp_ret: opp1 {
							opp-level = <1>;
						};
						rpmpd_opp_svs_krait: opp2 {
							opp-level = <2>;
						};
						rpmpd_opp_svs_soc: opp3 {
							opp-level = <3>;
						};
						rpmpd_opp_nom: opp4 {
							opp-level = <4>;
						};
						rpmpd_opp_turbo: opp5 {
							opp-level = <5>;
						};
						rpmpd_opp_super_turbo: opp6 {
							opp-level = <6>;
						};
					};
				};
			};
		};
	};

	smem {
		compatible = "qcom,smem";

		memory-region = <&smem_region>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;

		interrupt-parent = <&intc>;
		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs 8 10>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		apcs: syscon@f9011000 {
			compatible = "syscon";
			reg = <0xf9011000 0x1000>;
		};

		sdhc_1: mmc@f9824900 {
			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc", "core";
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
				 <&gcc GCC_SDCC1_APPS_CLK>,
				 <&xo_board>;
			clock-names = "iface", "core", "xo";
			pinctrl-names = "default";
			pinctrl-0 = <&sdhc1_default_state>;
			status = "disabled";
		};

		sdhc_2: mmc@f98a4900 {
			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc", "core";
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				 <&gcc GCC_SDCC2_APPS_CLK>,
				 <&xo_board>;
			clock-names = "iface", "core", "xo";
			pinctrl-names = "default";
			pinctrl-0 = <&sdhc2_default_state>;
			status = "disabled";
		};

		sdhc_3: mmc@f9864900 {
			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
			reg-names = "hc", "core";
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC3_AHB_CLK>,
				 <&gcc GCC_SDCC3_APPS_CLK>,
				 <&xo_board>;
			clock-names = "iface", "core", "xo";
			pinctrl-names = "default";
			pinctrl-0 = <&sdhc3_default_state>;
			status = "disabled";
		};

		blsp1_uart1: serial@f991d000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991d000 0x1000>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_uart3: serial@f991f000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991f000 0x1000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_uart4: serial@f9920000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf9920000 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_i2c1: i2c@f9923000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9923000 0x1000>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c1_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c2: i2c@f9924000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9924000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c2_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c3: i2c@f9925000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9925000 0x1000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c3_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c4: i2c@f9926000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9926000 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c4_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c5: i2c@f9927000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9927000 0x1000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c5_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		cci: cci@fda0c000 {
			compatible = "qcom,msm8226-cci";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xfda0c000 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
			clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
				 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
				 <&mmcc CAMSS_CCI_CCI_CLK>;
			clock-names = "camss_top_ahb",
				      "cci_ahb",
				      "cci";

			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&cci_default>;
			pinctrl-1 = <&cci_sleep>;

			status = "disabled";

			cci_i2c0: i2c-bus@0 {
				reg = <0>;
				clock-frequency = <400000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		usb: usb@f9a55000 {
			compatible = "qcom,ci-hdrc";
			reg = <0xf9a55000 0x200>,
			      <0xf9a55200 0x200>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
			clock-names = "iface", "core";
			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
			assigned-clock-rates = <75000000>;
			resets = <&gcc GCC_USB_HS_BCR>;
			reset-names = "core";
			phy_type = "ulpi";
			dr_mode = "otg";
			hnp-disable;
			srp-disable;
			adp-disable;
			ahb-burst-config = <0>;
			phy-names = "usb-phy";
			phys = <&usb_hs_phy>;
			status = "disabled";
			#reset-cells = <1>;

			ulpi {
				usb_hs_phy: phy {
					compatible = "qcom,usb-hs-phy-msm8226",
						     "qcom,usb-hs-phy";
					#phy-cells = <0>;
					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
					clock-names = "ref", "sleep";
					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
					reset-names = "phy", "por";
					qcom,init-seq = /bits/ 8 <0x0 0x44
						0x1 0x68 0x2 0x24 0x3 0x13>;
				};
			};
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-msm8226";
			reg = <0xfc400000 0x4000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		mmcc: clock-controller@fd8c0000 {
			compatible = "qcom,mmcc-msm8226";
			reg = <0xfd8c0000 0x6000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		tlmm: pinctrl@fd510000 {
			compatible = "qcom,msm8226-pinctrl";
			reg = <0xfd510000 0x4000>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&tlmm 0 0 117>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

			blsp1_i2c1_pins: blsp1-i2c1-state {
				pins = "gpio2", "gpio3";
				function = "blsp_i2c1";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c2_pins: blsp1-i2c2-state {
				pins = "gpio6", "gpio7";
				function = "blsp_i2c2";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c3_pins: blsp1-i2c3-state {
				pins = "gpio10", "gpio11";
				function = "blsp_i2c3";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c4_pins: blsp1-i2c4-state {
				pins = "gpio14", "gpio15";
				function = "blsp_i2c4";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c5_pins: blsp1-i2c5-state {
				pins = "gpio18", "gpio19";
				function = "blsp_i2c5";
				drive-strength = <2>;
				bias-disable;
			};

			cci_default: cci-default-state {
				pins = "gpio29", "gpio30";
				function = "cci_i2c0";

				drive-strength = <2>;
				bias-disable;
			};

			cci_sleep: cci-sleep-state {
				pins = "gpio29", "gpio30";
				function = "gpio";

				drive-strength = <2>;
				bias-disable;
			};

			sdhc1_default_state: sdhc1-default-state {
				clk-pins {
					pins = "sdc1_clk";
					drive-strength = <10>;
					bias-disable;
				};

				cmd-data-pins {
					pins = "sdc1_cmd", "sdc1_data";
					drive-strength = <10>;
					bias-pull-up;
				};
			};

			sdhc2_default_state: sdhc2-default-state {
				clk-pins {
					pins = "sdc2_clk";
					drive-strength = <10>;
					bias-disable;
				};

				cmd-data-pins {
					pins = "sdc2_cmd", "sdc2_data";
					drive-strength = <10>;
					bias-pull-up;
				};
			};

			sdhc3_default_state: sdhc3-default-state {
				clk-pins {
					pins = "gpio44";
					function = "sdc3";
					drive-strength = <8>;
					bias-disable;
				};

				cmd-pins {
					pins = "gpio43";
					function = "sdc3";
					drive-strength = <8>;
					bias-pull-up;
				};

				data-pins {
					pins = "gpio39", "gpio40", "gpio41", "gpio42";
					function = "sdc3";
					drive-strength = <8>;
					bias-pull-up;
				};
			};
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		rng@f9bff000 {
			compatible = "qcom,prng";
			reg = <0xf9bff000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		timer@f9020000 {
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		rpm_msg_ram: sram@fc428000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0xfc428000 0x4000>;
		};

		tcsr_mutex: hwlock@fd484000 {
			compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
			reg = <0xfd484000 0x1000>;
			#hwlock-cells = <1>;
		};

		adsp: remoteproc@fe200000 {
			compatible = "qcom,msm8226-adsp-pil";
			reg = <0xfe200000 0x100>;

			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

			power-domains = <&rpmpd MSM8226_VDDCX>;
			power-domain-names = "cx";

			clocks = <&xo_board>;
			clock-names = "xo";

			memory-region = <&adsp_region>;

			qcom,smem-states = <&adsp_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			smd-edge {
				interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;

				qcom,ipc = <&apcs 8 8>;
				qcom,smd-edge = <1>;

				label = "lpass";
			};
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 2
				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3
				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 4
				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 1
				(GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/input/input.h>

#include "qcom-msm8660.dtsi"

/ {
	model = "Qualcomm MSM8660 SURF";
	compatible = "qcom,msm8660-surf", "qcom,msm8660";

	aliases {
		serial0 = &gsbi12_serial;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	/* Temporary fixed regulator */
	vsdcc_fixed: vsdcc-regulator {
		compatible = "regulator-fixed";
		regulator-name = "SDCC Power";
		regulator-min-microvolt = <2700000>;
		regulator-max-microvolt = <2700000>;
		regulator-always-on;
	};
};

&gsbi12 {
	qcom,mode = <GSBI_PROT_I2C_UART>;
	status = "okay";
};

&gsbi12_serial {
	status = "okay";
};

&pm8058 {
	keypad@148 {
		linux,keymap = <
			MATRIX_KEY(0, 0, KEY_FN_F1)
			MATRIX_KEY(0, 1, KEY_UP)
			MATRIX_KEY(0, 2, KEY_LEFT)
			MATRIX_KEY(0, 3, KEY_VOLUMEUP)
			MATRIX_KEY(1, 0, KEY_FN_F2)
			MATRIX_KEY(1, 1, KEY_RIGHT)
			MATRIX_KEY(1, 2, KEY_DOWN)
			MATRIX_KEY(1, 3, KEY_VOLUMEDOWN)
			MATRIX_KEY(2, 3, KEY_ENTER)
			MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS)
			MATRIX_KEY(4, 1, KEY_UP)
			MATRIX_KEY(4, 2, KEY_LEFT)
			MATRIX_KEY(4, 3, KEY_HOME)
			MATRIX_KEY(4, 4, KEY_FN_F3)
			MATRIX_KEY(5, 0, KEY_CAMERA)
			MATRIX_KEY(5, 1, KEY_RIGHT)
			MATRIX_KEY(5, 2, KEY_DOWN)
			MATRIX_KEY(5, 3, KEY_BACK)
			MATRIX_KEY(5, 4, KEY_MENU)
			>;
		keypad,num-rows = <6>;
		keypad,num-columns = <5>;
	};
};

/* eMMC */
&sdcc1 {
	vmmc-supply = <&vsdcc_fixed>;
	status = "okay";
};

/* External micro SD card */
&sdcc3 {
	vmmc-supply = <&vsdcc_fixed>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8660.h>
#include <dt-bindings/soc/qcom,gsbi.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm MSM8660";
	compatible = "qcom,msm8660";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "qcom,scorpion";
			enable-method = "qcom,gcc-msm8660";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			compatible = "qcom,scorpion";
			enable-method = "qcom,gcc-msm8660";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	cpu-pmu {
		compatible = "qcom,scorpion-mp-pmu";
		interrupts = <1 9 0x304>;
	};

	clocks {
		cxo_board: cxo-board-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
			clock-output-names = "cxo_board";
		};

		pxo_board: pxo-board-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
			clock-output-names = "pxo_board";
		};

		sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "sleep_clk";
		};
	};

	/*
	 * These channels from the ADC are simply hardware monitors.
	 * That is why the ADC is referred to as "HKADC" - HouseKeeping
	 * ADC.
	 */
	iio-hwmon {
		compatible = "iio-hwmon";
		io-channels = <&xoadc 0x00 0x01>, /* Battery */
			    <&xoadc 0x00 0x02>, /* DC in (charger) */
			    <&xoadc 0x00 0x04>, /* VPH the main system voltage */
			    <&xoadc 0x00 0x0b>, /* Die temperature */
			    <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
			    <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
			    <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@2080000 {
			compatible = "qcom,msm-8660-qgic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = < 0x02080000 0x1000 >,
			      < 0x02081000 0x1000 >;
		};

		timer@2000000 {
			compatible = "qcom,scss-timer", "qcom,msm-timer";
			interrupts = <1 0 0x301>,
				     <1 1 0x301>,
				     <1 2 0x301>;
			reg = <0x02000000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x40000>;
		};

		tlmm: pinctrl@800000 {
			compatible = "qcom,msm8660-pinctrl";
			reg = <0x800000 0x4000>;

			gpio-controller;
			gpio-ranges = <&tlmm 0 0 173>;
			#gpio-cells = <2>;
			interrupts = <0 16 0x4>;
			interrupt-controller;
			#interrupt-cells = <2>;

		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-msm8660";
			#clock-cells = <1>;
			#power-domain-cells = <1>;
			#reset-cells = <1>;
			reg = <0x900000 0x4000>;
			clocks = <&pxo_board>, <&cxo_board>;
			clock-names = "pxo", "cxo";
		};

		gsbi1: gsbi@16000000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <12>;
			reg = <0x16000000 0x100>;
			clocks = <&gcc GSBI1_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			status = "disabled";

			gsbi1_spi: spi@16080000 {
				compatible = "qcom,spi-qup-v1.1.1";
				reg = <0x16080000 0x1000>;
				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		gsbi3: gsbi@16200000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <12>;
			reg = <0x16200000 0x100>;
			clocks = <&gcc GSBI3_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;
			status = "disabled";

			gsbi3_i2c: i2c@16280000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x16280000 0x1000>;
				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		gsbi6: gsbi@16500000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <12>;
			reg = <0x16500000 0x100>;
			clocks = <&gcc GSBI6_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			syscon-tcsr = <&tcsr>;

			gsbi6_serial: serial@16540000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16540000 0x1000>,
				      <0x16500000 0x1000>;
				interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi6_i2c: i2c@16580000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x16580000 0x1000>;
				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		gsbi7: gsbi@16600000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <12>;
			reg = <0x16600000 0x100>;
			clocks = <&gcc GSBI7_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			syscon-tcsr = <&tcsr>;

			gsbi7_serial: serial@16640000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16640000 0x1000>,
				      <0x16600000 0x1000>;
				interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi7_i2c: i2c@16680000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x16680000 0x1000>;
				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		gsbi8: gsbi@19800000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <12>;
			reg = <0x19800000 0x100>;
			clocks = <&gcc GSBI8_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;
			status = "disabled";

			gsbi8_i2c: i2c@19880000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x19880000 0x1000>;
				interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		gsbi12: gsbi@19c00000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <12>;
			reg = <0x19c00000 0x100>;
			clocks = <&gcc GSBI12_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi12_serial: serial@19c40000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x19c40000 0x1000>,
				      <0x19c00000 0x1000>;
				interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi12_i2c: i2c@19c80000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x19c80000 0x1000>;
				interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		ebi2: external-bus@1a100000 {
			compatible = "qcom,msm8660-ebi2";
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <0 0x0 0x1a800000 0x00800000>,
				 <1 0x0 0x1b000000 0x00800000>,
				 <2 0x0 0x1b800000 0x00800000>,
				 <3 0x0 0x1d000000 0x08000000>,
				 <4 0x0 0x1c800000 0x00800000>,
				 <5 0x0 0x1c000000 0x00800000>;
			reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
			reg-names = "ebi2", "xmem";
			clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
			clock-names = "ebi2x", "ebi2";
			status = "disabled";
		};

		ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";

			pm8058: pmic {
				compatible = "qcom,pm8058";
				interrupt-parent = <&tlmm>;
				interrupts = <88 8>;
				#interrupt-cells = <2>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;

				pm8058_gpio: gpio@150 {
					compatible = "qcom,pm8058-gpio",
						     "qcom,ssbi-gpio";
					reg = <0x150>;
					interrupt-controller;
					#interrupt-cells = <2>;
					gpio-controller;
					gpio-ranges = <&pm8058_gpio 0 0 44>;
					#gpio-cells = <2>;

				};

				pm8058_mpps: mpps@50 {
					compatible = "qcom,pm8058-mpp",
						     "qcom,ssbi-mpp";
					reg = <0x50>;
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&pm8058_mpps 0 0 12>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				pwrkey@1c {
					compatible = "qcom,pm8058-pwrkey";
					reg = <0x1c>;
					interrupt-parent = <&pm8058>;
					interrupts = <50 1>, <51 1>;
					debounce = <15625>;
					pull-up;
				};

				pm8058_keypad: keypad@148 {
					compatible = "qcom,pm8058-keypad";
					reg = <0x148>;
					interrupt-parent = <&pm8058>;
					interrupts = <74 1>, <75 1>;
					debounce = <15>;
					scan-delay = <32>;
					row-hold = <91500>;
				};

				xoadc: xoadc@197 {
					compatible = "qcom,pm8058-adc";
					reg = <0x197>;
					interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>;
					#address-cells = <2>;
					#size-cells = <0>;
					#io-channel-cells = <2>;

					vcoin: adc-channel@0 {
						reg = <0x00 0x00>;
					};
					vbat: adc-channel@1 {
						reg = <0x00 0x01>;
					};
					dcin: adc-channel@2 {
						reg = <0x00 0x02>;
					};
					ichg: adc-channel@3 {
						reg = <0x00 0x03>;
					};
					vph_pwr: adc-channel@4 {
						reg = <0x00 0x04>;
					};
					usb_vbus: adc-channel@a {
						reg = <0x00 0x0a>;
					};
					die_temp: adc-channel@b {
						reg = <0x00 0x0b>;
					};
					ref_625mv: adc-channel@c {
						reg = <0x00 0x0c>;
					};
					ref_1250mv: adc-channel@d {
						reg = <0x00 0x0d>;
					};
					ref_325mv: adc-channel@e {
						reg = <0x00 0x0e>;
					};
					ref_muxoff: adc-channel@f {
						reg = <0x00 0x0f>;
					};
				};

				rtc@1e8 {
					compatible = "qcom,pm8058-rtc";
					reg = <0x1e8>;
					interrupt-parent = <&pm8058>;
					interrupts = <39 1>;
					allow-set-time;
				};

				vibrator@4a {
					compatible = "qcom,pm8058-vib";
					reg = <0x4a>;
				};

				pm8058_led48: led@48 {
					compatible = "qcom,pm8058-keypad-led";
					reg = <0x48>;
					status = "disabled";
				};

				pm8058_led131: led@131 {
					compatible = "qcom,pm8058-led";
					reg = <0x131>;
					status = "disabled";
				};

				pm8058_led132: led@132 {
					compatible = "qcom,pm8058-led";
					reg = <0x132>;
					status = "disabled";
				};

				pm8058_led133: led@133 {
					compatible = "qcom,pm8058-led";
					reg = <0x133>;
					status = "disabled";
				};

			};
		};

		l2cc: clock-controller@2082000 {
			compatible = "qcom,kpss-gcc", "syscon";
			reg = <0x02082000 0x1000>;
		};

		rpm: rpm@104000 {
			compatible = "qcom,rpm-msm8660";
			reg = <0x00104000 0x1000>;
			qcom,ipc = <&l2cc 0x8 2>;

			interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "ack", "err", "wakeup";
			clocks = <&gcc RPM_MSG_RAM_H_CLK>;
			clock-names = "ram";

			rpmcc: clock-controller {
				compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
				#clock-cells = <1>;
				clocks = <&pxo_board>;
				clock-names = "pxo";
			};

			regulators-0 {
				compatible = "qcom,rpm-pm8901-regulators";

				pm8901_l0: l0 {};
				pm8901_l1: l1 {};
				pm8901_l2: l2 {};
				pm8901_l3: l3 {};
				pm8901_l4: l4 {};
				pm8901_l5: l5 {};
				pm8901_l6: l6 {};

				/* S0 and S1 Handled as SAW regulators by SPM */
				pm8901_s2: s2 {};
				pm8901_s3: s3 {};
				pm8901_s4: s4 {};

				pm8901_lvs0: lvs0 {};
				pm8901_lvs1: lvs1 {};
				pm8901_lvs2: lvs2 {};
				pm8901_lvs3: lvs3 {};

				pm8901_mvs: mvs {};
			};

			regulators-1 {
				compatible = "qcom,rpm-pm8058-regulators";

				pm8058_l0: l0 {};
				pm8058_l1: l1 {};
				pm8058_l2: l2 {};
				pm8058_l3: l3 {};
				pm8058_l4: l4 {};
				pm8058_l5: l5 {};
				pm8058_l6: l6 {};
				pm8058_l7: l7 {};
				pm8058_l8: l8 {};
				pm8058_l9: l9 {};
				pm8058_l10: l10 {};
				pm8058_l11: l11 {};
				pm8058_l12: l12 {};
				pm8058_l13: l13 {};
				pm8058_l14: l14 {};
				pm8058_l15: l15 {};
				pm8058_l16: l16 {};
				pm8058_l17: l17 {};
				pm8058_l18: l18 {};
				pm8058_l19: l19 {};
				pm8058_l20: l20 {};
				pm8058_l21: l21 {};
				pm8058_l22: l22 {};
				pm8058_l23: l23 {};
				pm8058_l24: l24 {};
				pm8058_l25: l25 {};

				pm8058_s0: s0 {};
				pm8058_s1: s1 {};
				pm8058_s2: s2 {};
				pm8058_s3: s3 {};
				pm8058_s4: s4 {};

				pm8058_lvs0: lvs0 {};
				pm8058_lvs1: lvs1 {};

				pm8058_ncp: ncp {};
			};
		};

		amba {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			sdcc1: mmc@12400000 {
				status = "disabled";
				compatible = "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg = <0x12400000 0x8000>;
				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
				clock-names = "mclk", "apb_pclk";
				bus-width = <8>;
				max-frequency = <48000000>;
				non-removable;
				cap-sd-highspeed;
				cap-mmc-highspeed;
			};

			sdcc2: mmc@12140000 {
				status = "disabled";
				compatible = "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg = <0x12140000 0x8000>;
				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
				clock-names = "mclk", "apb_pclk";
				bus-width = <8>;
				max-frequency = <48000000>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
			};

			sdcc3: mmc@12180000 {
				compatible = "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status = "disabled";
				reg = <0x12180000 0x8000>;
				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
				clock-names = "mclk", "apb_pclk";
				bus-width = <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency = <48000000>;
				no-1-8-v;
			};

			sdcc4: mmc@121c0000 {
				compatible = "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status = "disabled";
				reg = <0x121c0000 0x8000>;
				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
				clock-names = "mclk", "apb_pclk";
				bus-width = <4>;
				max-frequency = <48000000>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
			};

			sdcc5: mmc@12200000 {
				compatible = "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status = "disabled";
				reg = <0x12200000 0x8000>;
				interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
				clock-names = "mclk", "apb_pclk";
				bus-width = <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency = <48000000>;
			};
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-msm8660", "syscon";
			reg = <0x1a400000 0x100>;
		};
	};

};


code:
// SPDX-License-Identifier: GPL-2.0-only
#include "arm64/qcom/msm8916-samsung-e5.dts"
#include "qcom-msm8916-smp.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0-only
#include "arm64/qcom/msm8916-samsung-e7.dts"
#include "qcom-msm8916-smp.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0-only
#include "arm64/qcom/msm8916-samsung-grandmax.dts"
#include "qcom-msm8916-smp.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0-only
#include "arm64/qcom/msm8916-samsung-serranove.dts"
#include "qcom-msm8916-smp.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0-only

/ {
	cpus {
		cpu@0 {
			enable-method = "qcom,msm8916-smp";
		};
		cpu@1 {
			enable-method = "qcom,msm8916-smp";
		};
		cpu@2 {
			enable-method = "qcom,msm8916-smp";
		};
		cpu@3 {
			enable-method = "qcom,msm8916-smp";
		};

		idle-states {
			/delete-property/ entry-method;
		};
	};

	psci {
		status = "disabled";
	};
};

&CPU_SLEEP_0 {
	compatible = "qcom,idle-state-spc";
};

&cpu0_acc {
	status = "okay";
};

&cpu0_saw {
	status = "okay";
};

&cpu1_acc {
	status = "okay";
};

&cpu1_saw {
	status = "okay";
};

&cpu2_acc {
	status = "okay";
};

&cpu2_saw {
	status = "okay";
};

&cpu3_acc {
	status = "okay";
};

&cpu3_saw {
	status = "okay";
};