code:
/*
 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
 * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
#include <dt-bindings/clock/sun8i-de2.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		framebuffer-lcd {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "mixer0-lcd0";
			clocks = <&display_clocks CLK_MIXER0>,
				 <&ccu CLK_TCON0>;
			status = "disabled";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			clocks = <&ccu CLK_CPU>;
		};
	};

	de: display-engine {
		compatible = "allwinner,sun8i-v3s-display-engine";
		allwinner,pipelines = <&mixer0>;
		status = "disabled";
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-accuracy = <50000>;
			clock-output-names = "osc24M";
		};

		osc32k: osc32k_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-accuracy = <50000>;
			clock-output-names = "ext-osc32k";
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		display_clocks: clock@1000000 {
			compatible = "allwinner,sun8i-v3s-de2-clk";
			reg = <0x01000000 0x10000>;
			clocks = <&ccu CLK_BUS_DE>,
				 <&ccu CLK_DE>;
			clock-names = "bus",
				      "mod";
			resets = <&ccu RST_BUS_DE>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		mixer0: mixer@1100000 {
			compatible = "allwinner,sun8i-v3s-de2-mixer";
			reg = <0x01100000 0x100000>;
			clocks = <&display_clocks 0>,
				 <&display_clocks 6>;
			clock-names = "bus",
				      "mod";
			resets = <&display_clocks 0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				mixer0_out: port@1 {
					reg = <1>;

					mixer0_out_tcon0: endpoint {
						remote-endpoint = <&tcon0_in_mixer0>;
					};
				};
			};
		};

		syscon: system-control@1c00000 {
			compatible = "allwinner,sun8i-v3s-system-control",
				     "allwinner,sun8i-h3-system-control";
			reg = <0x01c00000 0xd0>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
		};

		nmi_intc: interrupt-controller@1c000d0 {
			compatible = "allwinner,sun8i-v3s-nmi",
				     "allwinner,sun9i-a80-nmi";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x01c000d0 0x0c>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		};

		dma: dma-controller@1c02000 {
			compatible = "allwinner,sun8i-v3s-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_DMA>;
			resets = <&ccu RST_BUS_DMA>;
			#dma-cells = <1>;
		};

		tcon0: lcd-controller@1c0c000 {
			compatible = "allwinner,sun8i-v3s-tcon";
			reg = <0x01c0c000 0x1000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_TCON0>,
				 <&ccu CLK_TCON0>;
			clock-names = "ahb",
				      "tcon-ch0";
			clock-output-names = "tcon-pixel-clock";
			#clock-cells = <0>;
			resets = <&ccu RST_BUS_TCON0>;
			reset-names = "lcd";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon0_in: port@0 {
					reg = <0>;

					tcon0_in_mixer0: endpoint {
						remote-endpoint = <&mixer0_out_tcon0>;
					};
				};

				tcon0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;
				};
			};
		};

		mmc0: mmc@1c0f000 {
			compatible = "allwinner,sun7i-a20-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC0>,
				 <&ccu CLK_MMC0>,
				 <&ccu CLK_MMC0_OUTPUT>,
				 <&ccu CLK_MMC0_SAMPLE>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ccu RST_BUS_MMC0>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&mmc0_pins>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@1c10000 {
			compatible = "allwinner,sun7i-a20-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC1>,
				 <&ccu CLK_MMC1>,
				 <&ccu CLK_MMC1_OUTPUT>,
				 <&ccu CLK_MMC1_SAMPLE>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ccu RST_BUS_MMC1>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&mmc1_pins>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@1c11000 {
			compatible = "allwinner,sun7i-a20-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC2>,
				 <&ccu CLK_MMC2>,
				 <&ccu CLK_MMC2_OUTPUT>,
				 <&ccu CLK_MMC2_SAMPLE>;
			clock-names = "ahb",
				      "mmc",
				      "output",
				      "sample";
			resets = <&ccu RST_BUS_MMC2>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		crypto@1c15000 {
			compatible = "allwinner,sun8i-v3s-crypto",
				     "allwinner,sun8i-a33-crypto";
			reg = <0x01c15000 0x1000>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
			clock-names = "ahb", "mod";
			dmas = <&dma 16>, <&dma 16>;
			dma-names = "rx", "tx";
			resets = <&ccu RST_BUS_CE>;
			reset-names = "ahb";
		};

		usb_otg: usb@1c19000 {
			compatible = "allwinner,sun8i-h3-musb";
			reg = <0x01c19000 0x0400>;
			clocks = <&ccu CLK_BUS_OTG>;
			resets = <&ccu RST_BUS_OTG>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mc";
			phys = <&usbphy 0>;
			phy-names = "usb";
			extcon = <&usbphy 0>;
			status = "disabled";
		};

		usbphy: phy@1c19400 {
			compatible = "allwinner,sun8i-v3s-usb-phy";
			reg = <0x01c19400 0x2c>,
			      <0x01c1a800 0x4>;
			reg-names = "phy_ctrl",
				    "pmu0";
			clocks = <&ccu CLK_USB_PHY0>;
			clock-names = "usb0_phy";
			resets = <&ccu RST_USB_PHY0>;
			reset-names = "usb0_reset";
			status = "disabled";
			#phy-cells = <1>;
		};

		ccu: clock@1c20000 {
			compatible = "allwinner,sun8i-v3s-ccu";
			reg = <0x01c20000 0x400>;
			clocks = <&osc24M>, <&rtc CLK_OSC32K>;
			clock-names = "hosc", "losc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		rtc: rtc@1c20400 {
			#clock-cells = <1>;
			compatible = "allwinner,sun8i-v3-rtc";
			reg = <0x01c20400 0x54>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc32k>;
			clock-output-names = "osc32k", "osc32k-out";
		};

		pio: pinctrl@1c20800 {
			compatible = "allwinner,sun8i-v3s-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
				 <&rtc CLK_OSC32K>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			#gpio-cells = <3>;
			interrupt-controller;
			#interrupt-cells = <3>;

			/omit-if-no-ref/
			csi0_mclk_pin: csi0-mclk-pin {
				pins = "PE20";
				function = "csi_mipi";
			};

			/omit-if-no-ref/
			csi1_8bit_pins: csi1-8bit-pins {
				pins = "PE0", "PE2", "PE3", "PE8", "PE9",
				       "PE10", "PE11", "PE12", "PE13", "PE14",
				       "PE15";
				function = "csi";
			};

			/omit-if-no-ref/
			csi1_mclk_pin: csi1-mclk-pin {
				pins = "PE1";
				function = "csi";
			};

			i2c0_pins: i2c0-pins {
				pins = "PB6", "PB7";
				function = "i2c0";
			};

			/omit-if-no-ref/
			i2c1_pb_pins: i2c1-pb-pins {
				pins = "PB8", "PB9";
				function = "i2c1";
			};

			/omit-if-no-ref/
			i2c1_pe_pins: i2c1-pe-pins {
				pins = "PE21", "PE22";
				function = "i2c1";
			};

			uart0_pb_pins: uart0-pb-pins {
				pins = "PB8", "PB9";
				function = "uart0";
			};

			uart2_pins: uart2-pins {
				pins = "PB0", "PB1";
				function = "uart2";
			};

			mmc0_pins: mmc0-pins {
				pins = "PF0", "PF1", "PF2", "PF3",
				       "PF4", "PF5";
				function = "mmc0";
				drive-strength = <30>;
				bias-pull-up;
			};

			mmc1_pins: mmc1-pins {
				pins = "PG0", "PG1", "PG2", "PG3",
				       "PG4", "PG5";
				function = "mmc1";
				drive-strength = <30>;
				bias-pull-up;
			};

			spi0_pins: spi0-pins {
				pins = "PC0", "PC1", "PC2", "PC3";
				function = "spi0";
			};
		};

		timer@1c20c00 {
			compatible = "allwinner,sun8i-v3s-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		wdt0: watchdog@1c20ca0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x01c20ca0 0x20>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		pwm: pwm@1c21400 {
			compatible = "allwinner,sun8i-v3s-pwm",
				     "allwinner,sun7i-a20-pwm";
			reg = <0x01c21400 0xc>;
			clocks = <&osc24M>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		lradc: lradc@1c22800 {
			compatible = "allwinner,sun4i-a10-lradc-keys";
			reg = <0x01c22800 0x400>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		codec: codec@1c22c00 {
			#sound-dai-cells = <0>;
			compatible = "allwinner,sun8i-v3s-codec";
			reg = <0x01c22c00 0x400>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
			clock-names = "apb", "codec";
			resets = <&ccu RST_BUS_CODEC>;
			dmas = <&dma 15>, <&dma 15>;
			dma-names = "rx", "tx";
			allwinner,codec-analog-controls = <&codec_analog>;
			status = "disabled";
		};

		codec_analog: codec-analog@1c23000 {
			compatible = "allwinner,sun8i-v3s-codec-analog";
			reg = <0x01c23000 0x4>;
		};

		uart0: serial@1c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART0>;
			dmas = <&dma 6>, <&dma 6>;
			dma-names = "rx", "tx";
			resets = <&ccu RST_BUS_UART0>;
			status = "disabled";
		};

		uart1: serial@1c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART1>;
			dmas = <&dma 7>, <&dma 7>;
			dma-names = "rx", "tx";
			resets = <&ccu RST_BUS_UART1>;
			status = "disabled";
		};

		uart2: serial@1c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART2>;
			dmas = <&dma 8>, <&dma 8>;
			dma-names = "rx", "tx";
			resets = <&ccu RST_BUS_UART2>;
			pinctrl-0 = <&uart2_pins>;
			pinctrl-names = "default";
			status = "disabled";
		};

		i2c0: i2c@1c2ac00 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C0>;
			resets = <&ccu RST_BUS_I2C0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_pins>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@1c2b000 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C1>;
			resets = <&ccu RST_BUS_I2C1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		emac: ethernet@1c30000 {
			compatible = "allwinner,sun8i-v3s-emac";
			syscon = <&syscon>;
			reg = <0x01c30000 0x10000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			resets = <&ccu RST_BUS_EMAC>;
			reset-names = "stmmaceth";
			clocks = <&ccu CLK_BUS_EMAC>;
			clock-names = "stmmaceth";
			phy-handle = <&int_mii_phy>;
			phy-mode = "mii";
			status = "disabled";

			mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,dwmac-mdio";
			};

			mdio_mux: mdio-mux {
				compatible = "allwinner,sun8i-h3-mdio-mux";
				#address-cells = <1>;
				#size-cells = <0>;

				mdio-parent-bus = <&mdio>;
				/* Only one MDIO is usable at the time */
				internal_mdio: mdio@1 {
					compatible = "allwinner,sun8i-h3-mdio-internal";
					reg = <1>;
					#address-cells = <1>;
					#size-cells = <0>;

					int_mii_phy: ethernet-phy@1 {
						compatible = "ethernet-phy-ieee802.3-c22";
						reg = <1>;
						clocks = <&ccu CLK_BUS_EPHY>;
						resets = <&ccu RST_BUS_EPHY>;
					};
				};
			};
		};

		spi0: spi@1c68000 {
			compatible = "allwinner,sun8i-h3-spi";
			reg = <0x01c68000 0x1000>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
			clock-names = "ahb", "mod";
			dmas = <&dma 23>, <&dma 23>;
			dma-names = "rx", "tx";
			pinctrl-names = "default";
			pinctrl-0 = <&spi0_pins>;
			resets = <&ccu RST_BUS_SPI0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gic: interrupt-controller@1c81000 {
			compatible = "arm,gic-400";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x2000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		csi1: camera@1cb4000 {
			compatible = "allwinner,sun8i-v3s-csi";
			reg = <0x01cb4000 0x3000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_CSI>,
				 <&ccu CLK_CSI1_SCLK>,
				 <&ccu CLK_DRAM_CSI>;
			clock-names = "bus", "mod", "ram";
			resets = <&ccu RST_BUS_CSI>;
			status = "disabled";
		};
	};
};


code:
/*
 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "sun8i-r40.dtsi"
#include "sun8i-r40-cpu-opp.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Banana Pi M2 Berry";
	compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40";

	aliases {
		ethernet0 = &gmac;
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	connector {
		compatible = "hdmi-connector";
		type = "a";

		port {
			hdmi_con_in: endpoint {
				remote-endpoint = <&hdmi_out_con>;
			};
		};
	};

	leds {
		compatible = "gpio-leds";

		pwr-led {
			label = "bananapi:red:pwr";
			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};

		user-led {
			label = "bananapi:green:user";
			gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
		};
	};

	reg_vcc5v0: vcc5v0 {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
		enable-active-high;
	};

	wifi_pwrseq: wifi_pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
		clocks = <&ccu CLK_OUTA>;
		clock-names = "ext_clock";
	};
};

&ahci {
	ahci-supply = <&reg_dldo4>;
	phy-supply = <&reg_eldo3>;
	status = "okay";
};

&cpu0 {
	cpu-supply = <&reg_dcdc2>;
};

&de {
	status = "okay";
};

&ehci1 {
	/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
	status = "okay";
};

&gmac {
	pinctrl-names = "default";
	pinctrl-0 = <&gmac_rgmii_pins>;
	phy-handle = <&phy1>;
	phy-mode = "rgmii-id";
	phy-supply = <&reg_dc1sw>;
	status = "okay";
};

&gmac_mdio {
	phy1: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <1>;
	};
};

&hdmi {
	status = "okay";
};

&hdmi_out {
	hdmi_out_con: endpoint {
		remote-endpoint = <&hdmi_con_in>;
	};
};

&i2c0 {
	status = "okay";

	axp22x: pmic@34 {
		compatible = "x-powers,axp221";
		reg = <0x34>;
		interrupt-parent = <&nmi_intc>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
	};
};

#include "axp22x.dtsi"

&mmc0 {
	vmmc-supply = <&reg_dcdc1>;
	bus-width = <4>;
	cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
	status = "okay";
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pg_pins>;
	vmmc-supply = <&reg_dldo2>;
	vqmmc-supply = <&reg_dldo1>;
	mmc-pwrseq = <&wifi_pwrseq>;
	bus-width = <4>;
	non-removable;
	status = "okay";
};

&pio {
	pinctrl-names = "default";
	pinctrl-0 = <&clk_out_a_pin>;
	vcc-pa-supply = <&reg_aldo2>;
	vcc-pc-supply = <&reg_dcdc1>;
	vcc-pd-supply = <&reg_dcdc1>;
	vcc-pe-supply = <&reg_eldo1>;
	vcc-pf-supply = <&reg_dcdc1>;
	vcc-pg-supply = <&reg_dldo1>;
};

&reg_aldo2 {
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <2500000>;
	regulator-name = "vcc-pa";
};

&reg_aldo3 {
	regulator-always-on;
	regulator-min-microvolt = <2700000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "avcc";
};

&reg_dc1sw {
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-gmac-phy";
};

&reg_dcdc1 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-3v3";
};

&reg_dcdc2 {
	regulator-always-on;
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1300000>;
	regulator-name = "vdd-cpu";
};

&reg_dcdc3 {
	regulator-always-on;
	regulator-min-microvolt = <1000000>;
	regulator-max-microvolt = <1300000>;
	regulator-name = "vdd-sys";
};

&reg_dcdc5 {
	regulator-always-on;
	regulator-min-microvolt = <1500000>;
	regulator-max-microvolt = <1500000>;
	regulator-name = "vcc-dram";
};

&reg_dldo1 {
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi-io";
};

/*
 * Our WiFi chip needs both DLDO2 and DLDO3 to be powered at the same
 * time, with the two being in sync, to be able to meet maximum power
 * consumption during transmits. Since this is not really supported
 * right now, just use the two as always on, and we will fix it later.
 */

&reg_dldo2 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi";
};

&reg_dldo3 {
	regulator-always-on;
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
	regulator-name = "vcc-wifi-2";
};

&reg_dldo4 {
	regulator-min-microvolt = <2500000>;
	regulator-max-microvolt = <2500000>;
	regulator-name = "vdd2v5-sata";
};

&reg_eldo3 {
	regulator-min-microvolt = <1200000>;
	regulator-max-microvolt = <1200000>;
	regulator-name = "vdd1v2-sata";
};

&tcon_tv0 {
	status = "okay";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pb_pins>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
		compatible = "brcm,bcm43438-bt";
		clocks = <&ccu CLK_OUTA>;
		clock-names = "lpo";
		vbat-supply = <&reg_dldo2>;
		vddio-supply = <&reg_dldo1>;
		device-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
		/* TODO host wake line connected to PMIC GPIO pins */
		shutdown-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
		max-speed = <1500000>;
	};
};

&usbphy {
	usb1_vbus-supply = <&reg_vcc5v0>;
	status = "okay";
};

repo_name: angery/linux


code:
/*
 * Copyright 2015 Tyler Baker
 *
 * Tyler Baker <tyler.baker@linaro.org>
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "sun9i-a80.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Cubietech Cubieboard4";
	compatible = "cubietech,a80-cubieboard4", "allwinner,sun9i-a80";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	leds {
		compatible = "gpio-leds";

		led-0 {
			label = "cubieboard4:green:usr";
			gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */
		};

		led-1 {
			label = "cubieboard4:red:usr";
			gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
		};
	};

	vga-connector {
		compatible = "vga-connector";
		label = "vga";
		ddc-i2c-bus = <&i2c3>;

		port {
			vga_con_in: endpoint {
				remote-endpoint = <&vga_dac_out>;
			};
		};
	};

	vga-dac {
		compatible = "corpro,gm7123", "adi,adv7123";
		vdd-supply = <&reg_dcdc1>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				vga_dac_in: endpoint {
					remote-endpoint = <&tcon0_out_vga>;
				};
			};

			port@1 {
				reg = <1>;

				vga_dac_out: endpoint {
					remote-endpoint = <&vga_con_in>;
				};
			};
		};
	};

	wifi_pwrseq: wifi-pwrseq {
		compatible = "mmc-pwrseq-simple";
		clocks = <&ac100_rtc 1>;
		clock-names = "ext_clock";
		/* enables internal regulator and de-asserts reset */
		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
	};
};

&de {
	status = "okay";
};

&gmac {
	pinctrl-names = "default";
	pinctrl-0 = <&gmac_rgmii_pins>;
	phy-handle = <&phy1>;
	phy-mode = "rgmii-id";
	phy-supply = <&reg_cldo1>;
	status = "okay";
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;
	status = "okay";
};

&mdio {
	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	vmmc-supply = <&reg_dcdc1>;
	bus-width = <4>;
	cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH18 */
	status = "okay";
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	vmmc-supply = <&reg_dldo1>;
	vqmmc-supply = <&reg_cldo3>;
	mmc-pwrseq = <&wifi_pwrseq>;
	bus-width = <4>;
	non-removable;
	status = "okay";
};

&mmc1_pins {
	bias-pull-up;
};

&mmc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_8bit_pins>;
	vmmc-supply = <&reg_dcdc1>;
	bus-width = <8>;
	non-removable;
	cap-mmc-hw-reset;
	status = "okay";
};

&mmc2_8bit_pins {
	/* Increase drive strength for DDR modes */
	drive-strength = <40>;
};

&osc32k {
	/* osc32k input is from AC100 */
	clocks = <&ac100_rtc 0>;
};

&pio {
	vcc-pa-supply = <&reg_ldo_io1>;
	vcc-pb-supply = <&reg_aldo2>;
	vcc-pc-supply = <&reg_dcdc1>;
	vcc-pd-supply = <&reg_dc1sw>;
	vcc-pe-supply = <&reg_eldo2>;
	vcc-pf-supply = <&reg_dcdc1>;
	vcc-pg-supply = <&reg_ldo_io0>;
	vcc-ph-supply = <&reg_dcdc1>;
};

&r_ir {
	status = "okay";
};

&r_pio {
	vcc-pl-supply = <&reg_dldo2>;
	vcc-pm-supply = <&reg_eldo3>;
};

&r_rsb {
	status = "okay";

	axp809: pmic@3a3 {
		reg = <0x3a3>;
		interrupt-parent = <&nmi_intc>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			reg_aldo1: aldo1 {
				/*
				 * TODO: This should be handled by the
				 * USB PHY driver.
				 */
				regulator-always-on;
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "vcc33-usbh";
			};

			reg_aldo2: aldo2 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcc-pb-io-cam";
			};

			aldo3 {
				/* unused */
			};

			reg_dc1sw: dc1sw {
				regulator-name = "vcc-pd";
			};

			reg_dc5ldo: dc5ldo {
				regulator-always-on;
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1100000>;
				regulator-name = "vdd-cpus-09-usbh";
			};

			reg_dcdc1: dcdc1 {
				regulator-always-on;
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "vcc-3v";
			};

			reg_dcdc2: dcdc2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1100000>;
				regulator-name = "vdd-gpu";
			};

			reg_dcdc3: dcdc3 {
				regulator-always-on;
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1100000>;
				regulator-name = "vdd-cpua";
			};

			reg_dcdc4: dcdc4 {
				regulator-always-on;
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1100000>;
				regulator-name = "vdd-sys-usb0-hdmi";
			};

			reg_dcdc5: dcdc5 {
				regulator-always-on;
				regulator-min-microvolt = <1425000>;
				regulator-max-microvolt = <1575000>;
				regulator-name = "vcc-dram";
			};

			reg_dldo1: dldo1 {
				/*
				 * The WiFi chip supports a wide range
				 * (3.0 ~ 4.8V) of voltages, and so does
				 * this regulator (3.0 ~ 4.2V), but
				 * Allwinner SDK always sets it to 3.3V.
				 */
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vcc-wifi";
			};

			reg_dldo2: dldo2 {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "vcc-pl";
			};

			reg_eldo1: eldo1 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-name = "vcc-dvdd-cam";
			};

			reg_eldo2: eldo2 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcc-pe";
			};

			reg_eldo3: eldo3 {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "vcc-pm-codec-io1";
			};

			reg_ldo_io0: ldo_io0 {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "vcc-pg";
			};

			reg_ldo_io1: ldo_io1 {
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <2500000>;
				regulator-name = "vcc-pa-gmac-2v5";
			};

			reg_rtc_ldo: rtc_ldo {
				regulator-name = "vcc-rtc-vdd1v8-io";
			};

			sw {
				/* unused */
			};
		};
	};

	axp806: pmic@745 {
		compatible = "x-powers,axp806";
		reg = <0x745>;
		interrupt-parent = <&nmi_intc>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <1>;
		bldoin-supply = <&reg_dcdce>;

		regulators {
			reg_s_aldo1: aldo1 {
				regulator-always-on;
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "avcc";
			};

			aldo2 {
				/*
				 * unused, but use a different name to
				 * avoid name clash with axp809's aldo's
				 */
				regulator-name = "s_aldo2";
			};

			aldo3 {
				/*
				 * unused, but use a different name to
				 * avoid name clash with axp809's aldo's
				 */
				regulator-name = "s_aldo3";
			};

			reg_bldo1: bldo1 {
				regulator-always-on;
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <1900000>;
				regulator-name = "vcc18-efuse-adc-display-csi";
			};

			reg_bldo2: bldo2 {
				regulator-always-on;
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <1900000>;
				regulator-name =
					"vdd18-drampll-vcc18-pll-cpvdd";
			};

			bldo3 {
				/* unused */
			};

			reg_bldo4: bldo4 {
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1300000>;
				regulator-name = "vcc12-hsic";
			};

			reg_cldo1: cldo1 {
				/*
				 * This was 3V in the original design, but
				 * 3.3V is the recommended supply voltage
				 * for the Ethernet PHY.
				 */
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				/*
				 * The PHY requires 20ms after all voltages
				 * are applied until core logic is ready and
				 * 30ms after the reset pin is de-asserted.
				 * Set a 100ms delay to account for PMIC
				 * ramp time and board traces.
				 */
				regulator-enable-ramp-delay = <100000>;
				regulator-name = "vcc-gmac-phy";
			};

			reg_cldo2: cldo2 {
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-name = "afvcc-cam";
			};

			reg_cldo3: cldo3 {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "vcc-io-wifi-codec-io2";
			};

			reg_dcdca: dcdca {
				regulator-always-on;
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1100000>;
				regulator-name = "vdd-cpub";
			};

			reg_dcdcd: dcdcd {
				regulator-always-on;
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1100000>;
				regulator-name = "vdd-vpu";
			};

			reg_dcdce: dcdce {
				regulator-always-on;
				regulator-min-microvolt = <2100000>;
				regulator-max-microvolt = <2100000>;
				regulator-name = "vcc-bldo-codec-ldoin";
			};

			sw {
				/*
				 * unused, but use a different name to
				 * avoid name clash with axp809's sw
				 */
				regulator-name = "s_sw";
			};
		};
	};

	ac100: codec@e89 {
		compatible = "x-powers,ac100";
		reg = <0xe89>;

		ac100_codec: codec {
			compatible = "x-powers,ac100-codec";
			interrupt-parent = <&r_pio>;
			interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */
			#clock-cells = <0>;
			clock-output-names = "4M_adda";
		};

		ac100_rtc: rtc {
			compatible = "x-powers,ac100-rtc";
			interrupt-parent = <&nmi_intc>;
			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&ac100_codec>;
			#clock-cells = <1>;
			clock-output-names = "cko1_rtc",
					     "cko2_rtc",
					     "cko3_rtc";
		};
	};
};

#include "axp809.dtsi"

&tcon0 {
	pinctrl-names = "default";
	pinctrl-0 = <&lcd0_rgb888_pins>;
};

&tcon0_out {
	tcon0_out_vga: endpoint {
		remote-endpoint = <&vga_dac_in>;
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_ph_pins>;
	status = "okay";
};


code:
/*
 * Copyright 2014 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "sun9i-a80.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Merrii A80 Optimus Board";
	compatible = "merrii,a80-optimus", "allwinner,sun9i-a80";

	aliases {
		serial0 = &uart0;
		serial1 = &uart4;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	leds {
		compatible = "gpio-leds";

		/* The LED names match those found on the board */
		led2 {
			label = "optimus:led2:usr";
			gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>;
		};

		led3 {
			label = "optimus:led3:usr";
			gpios = <&r_pio 1 15 GPIO_ACTIVE_HIGH>; /* PM15 */
		};

		led4 {
			label = "optimus:led4:usr";
			gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>;
		};
	};

	reg_usb1_vbus: usb1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb1-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
	};

	reg_usb3_vbus: usb3-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb3-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
	};

	wifi_pwrseq: wifi-pwrseq {
		compatible = "mmc-pwrseq-simple";
		clocks = <&ac100_rtc 1>;
		clock-names = "ext_clock";
		/* enables internal regulator and de-asserts reset */
		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
	};
};

&ehci0 {
	status = "okay";
};

&ehci1 {
	/* Enable if HSIC peripheral is connected */
	status = "disabled";
};

&ehci2 {
	status = "okay";
};

&gmac {
	pinctrl-names = "default";
	pinctrl-0 = <&gmac_rgmii_pins>;
	phy-handle = <&phy1>;
	phy-mode = "rgmii-id";
	phy-supply = <&reg_cldo1>;
	status = "okay";
};

&mdio {
	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	vmmc-supply = <&reg_dcdc1>;
	bus-width = <4>;
	cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH8 */
	status = "okay";
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	vmmc-supply = <&reg_dldo1>;
	vqmmc-supply = <&reg_cldo3>;
	mmc-pwrseq = <&wifi_pwrseq>;
	bus-width = <4>;
	non-removable;
	status = "okay";
};

&mmc1_pins {
	bias-pull-up;
};

&mmc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_8bit_pins>;
	vmmc-supply = <&reg_dcdc1>;
	bus-width = <8>;
	non-removable;
	cap-mmc-hw-reset;
	status = "okay";
};

&mmc2_8bit_pins {
	/* Increase drive strength for DDR modes */
	drive-strength = <40>;
};

&ohci0 {
	status = "okay";
};

&ohci2 {
	status = "okay";
};

&osc32k {
	/* osc32k input is from AC100 */
	clocks = <&ac100_rtc 0>;
};

&pio {
	vcc-pa-supply = <&reg_ldo_io1>;
	vcc-pb-supply = <&reg_aldo2>;
	vcc-pc-supply = <&reg_dcdc1>;
	vcc-pd-supply = <&reg_dcdc1>;
	vcc-pe-supply = <&reg_eldo2>;
	vcc-pf-supply = <&reg_dcdc1>;
	vcc-pg-supply = <&reg_ldo_io0>;
	vcc-ph-supply = <&reg_dcdc1>;
};

&r_ir {
	status = "okay";
};

&r_pio {
	vcc-pl-supply = <&reg_dldo2>;
	vcc-pm-supply = <&reg_eldo3>;
};

&r_rsb {
	status = "okay";

	axp809: pmic@3a3 {
		reg = <0x3a3>;
		interrupt-parent = <&nmi_intc>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			reg_aldo1: aldo1 {
				/*
				 * TODO: This should be handled by the
				 * USB PHY driver.
				 */
				regulator-always-on;
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "vcc33-usbh";
			};

			reg_aldo2: aldo2 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcc-pb-io-cam";
			};

			aldo3 {
				/* unused */
			};

			reg_dc5ldo: dc5ldo {
				regulator-always-on;
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1100000>;
				regulator-name = "vdd-cpus-09-usbh";
			};

			dc1sw {
				/* unused */
			};

			reg_dcdc1: dcdc1 {
				regulator-always-on;
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "vcc-3v";
			};

			reg_dcdc2: dcdc2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1100000>;
				regulator-name = "vdd-gpu";
			};

			reg_dcdc3: dcdc3 {
				regulator-always-on;
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1100000>;
				regulator-name = "vdd-cpua";
			};

			reg_dcdc4: dcdc4 {
				regulator-always-on;
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1100000>;
				regulator-name = "vdd-sys-usb0-hdmi";
			};

			reg_dcdc5: dcdc5 {
				regulator-always-on;
				regulator-min-microvolt = <1425000>;
				regulator-max-microvolt = <1575000>;
				regulator-name = "vcc-dram";
			};

			reg_dldo1: dldo1 {
				/*
				 * The WiFi chip supports a wide range
				 * (3.0 ~ 4.8V) of voltages, and so does
				 * this regulator (3.0 ~ 4.2V), but
				 * Allwinner SDK always sets it to 3.3V.
				 */
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vcc-wifi";
			};

			reg_dldo2: dldo2 {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "vcc-pl";
			};

			reg_eldo1: eldo1 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-name = "vcc-dvdd-cam";
			};

			reg_eldo2: eldo2 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcc-pe";
			};

			reg_eldo3: eldo3 {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "vcc-pm-codec-io1";
			};

			reg_ldo_io0: ldo_io0 {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "vcc-pg";
			};

			reg_ldo_io1: ldo_io1 {
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <2500000>;
				regulator-name = "vcc-pa-gmac-2v5";
			};

			reg_rtc_ldo: rtc_ldo {
				regulator-name = "vcc-rtc-vdd1v8-io";
			};

			sw {
				/* unused */
			};
		};
	};

	axp806: pmic@745 {
		compatible = "x-powers,axp806";
		reg = <0x745>;
		interrupt-parent = <&nmi_intc>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <1>;
		bldoin-supply = <&reg_dcdce>;

		regulators {
			reg_s_aldo1: aldo1 {
				regulator-always-on;
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "avcc";
			};

			aldo2 {
				/*
				 * unused, but use a different name to
				 * avoid name clash with axp809's aldo's
				 */
				regulator-name = "s_aldo2";
			};

			aldo3 {
				/*
				 * unused, but use a different name to
				 * avoid name clash with axp809's aldo's
				 */
				regulator-name = "s_aldo3";
			};

			reg_bldo1: bldo1 {
				regulator-always-on;
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <1900000>;
				regulator-name = "vcc18-efuse-adc-display-csi";
			};

			reg_bldo2: bldo2 {
				regulator-always-on;
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <1900000>;
				regulator-name =
					"vdd18-drampll-vcc18-pll-cpvdd";
			};

			bldo3 {
				/* unused */
			};

			reg_bldo4: bldo4 {
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1300000>;
				regulator-name = "vcc12-hsic";
			};

			reg_cldo1: cldo1 {
				/*
				 * This was 3V in the original design, but
				 * 3.3V is the recommended supply voltage
				 * for the Ethernet PHY.
				 */
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				/*
				 * The PHY requires 20ms after all voltages
				 * are applied until core logic is ready and
				 * 30ms after the reset pin is de-asserted.
				 * Set a 100ms delay to account for PMIC
				 * ramp time and board traces.
				 */
				regulator-enable-ramp-delay = <100000>;
				regulator-name = "vcc-gmac-phy";
			};

			reg_cldo2: cldo2 {
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-name = "afvcc-cam";
			};

			reg_cldo3: cldo3 {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-name = "vcc-io-wifi-codec-io2";
			};

			reg_dcdca: dcdca {
				regulator-always-on;
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1100000>;
				regulator-name = "vdd-cpub";
			};

			reg_dcdcd: dcdcd {
				regulator-always-on;
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1100000>;
				regulator-name = "vdd-vpu";
			};

			reg_dcdce: dcdce {
				regulator-always-on;
				regulator-min-microvolt = <2100000>;
				regulator-max-microvolt = <2100000>;
				regulator-name = "vcc-bldo-codec-ldoin";
			};

			sw {
				/*
				 * unused, but use a different name to
				 * avoid name clash with axp809's sw
				 */
				regulator-name = "s_sw";
			};
		};
	};

	ac100: codec@e89 {
		compatible = "x-powers,ac100";
		reg = <0xe89>;

		ac100_codec: codec {
			compatible = "x-powers,ac100-codec";
			interrupt-parent = <&r_pio>;
			interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */
			#clock-cells = <0>;
			clock-output-names = "4M_adda";
		};

		ac100_rtc: rtc {
			compatible = "x-powers,ac100-rtc";
			interrupt-parent = <&nmi_intc>;
			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&ac100_codec>;
			#clock-cells = <1>;
			clock-output-names = "cko1_rtc",
					     "cko2_rtc",
					     "cko3_rtc";
		};
	};
};

#include "axp809.dtsi"

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_ph_pins>;
	status = "okay";
};

&usbphy1 {
	phy-supply = <&reg_usb1_vbus>;
	status = "okay";
};

&usbphy2 {
	phy-supply = <&reg_bldo4>;
	/* Enable if HSIC peripheral is connected */
	status = "disabled";
};

&usbphy3 {
	phy-supply = <&reg_usb3_vbus>;
	status = "okay";
};


code:
/*
 * Copyright 2014 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/sun9i-a80-ccu.h>
#include <dt-bindings/clock/sun9i-a80-de.h>
#include <dt-bindings/clock/sun9i-a80-usb.h>
#include <dt-bindings/reset/sun9i-a80-ccu.h>
#include <dt-bindings/reset/sun9i-a80-de.h>
#include <dt-bindings/reset/sun9i-a80-usb.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	aliases {
		ethernet0 = &gmac;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			cci-control-port = <&cci_control0>;
			clock-frequency = <12000000>;
			enable-method = "allwinner,sun9i-a80-smp";
			reg = <0x0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			cci-control-port = <&cci_control0>;
			clock-frequency = <12000000>;
			enable-method = "allwinner,sun9i-a80-smp";
			reg = <0x1>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			cci-control-port = <&cci_control0>;
			clock-frequency = <12000000>;
			enable-method = "allwinner,sun9i-a80-smp";
			reg = <0x2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			cci-control-port = <&cci_control0>;
			clock-frequency = <12000000>;
			enable-method = "allwinner,sun9i-a80-smp";
			reg = <0x3>;
		};

		cpu4: cpu@100 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			cci-control-port = <&cci_control1>;
			clock-frequency = <18000000>;
			enable-method = "allwinner,sun9i-a80-smp";
			reg = <0x100>;
		};

		cpu5: cpu@101 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			cci-control-port = <&cci_control1>;
			clock-frequency = <18000000>;
			enable-method = "allwinner,sun9i-a80-smp";
			reg = <0x101>;
		};

		cpu6: cpu@102 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			cci-control-port = <&cci_control1>;
			clock-frequency = <18000000>;
			enable-method = "allwinner,sun9i-a80-smp";
			reg = <0x102>;
		};

		cpu7: cpu@103 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			cci-control-port = <&cci_control1>;
			clock-frequency = <18000000>;
			enable-method = "allwinner,sun9i-a80-smp";
			reg = <0x103>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <24000000>;
		arm,cpu-registers-not-fw-configured;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		/*
		 * map 64 bit address range down to 32 bits,
		 * as the peripherals are all under 512MB.
		 */
		ranges = <0 0 0 0x20000000>;

		/*
		 * This clock is actually configurable from the PRCM address
		 * space. The external 24M oscillator can be turned off, and
		 * the clock switched to an internal 16M RC oscillator. Under
		 * normal operation there's no reason to do this, and the
		 * default is to use the external good one, so just model this
		 * as a fixed clock. Also it is not entirely clear if the
		 * osc24M mux in the PRCM affects the entire clock tree, which
		 * would also throw all the PLL clock rates off, or just the
		 * downstream clocks in the PRCM.
		 */
		osc24M: clk-24M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		/*
		 * The 32k clock is from an external source, normally the
		 * AC100 codec/RTC chip. This serves as a placeholder for
		 * board dts files to specify the source.
		 */
		osc32k: clk-32k {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <1>;
			clock-mult = <1>;
			clock-output-names = "osc32k";
		};

		/*
		 * The following two are dummy clocks, placeholders
		 * used in the gmac_tx clock. The gmac driver will
		 * choose one parent depending on the PHY interface
		 * mode, using clk_set_rate auto-reparenting.
		 *
		 * The actual TX clock rate is not controlled by the
		 * gmac_tx clock.
		 */
		mii_phy_tx_clk: mii_phy_tx_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
			clock-output-names = "mii_phy_tx";
		};

		gmac_int_tx_clk: gmac_int_tx_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <125000000>;
			clock-output-names = "gmac_int_tx";
		};

		gmac_tx_clk: clk@800030 {
			#clock-cells = <0>;
			compatible = "allwinner,sun7i-a20-gmac-clk";
			reg = <0x00800030 0x4>;
			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
			clock-output-names = "gmac_tx";
		};

		cpus_clk: clk@8001410 {
			compatible = "allwinner,sun9i-a80-cpus-clk";
			reg = <0x08001410 0x4>;
			#clock-cells = <0>;
			clocks = <&osc32k>, <&osc24M>,
				 <&ccu CLK_PLL_PERIPH0>,
				 <&ccu CLK_PLL_AUDIO>;
			clock-output-names = "cpus";
		};

		ahbs: clk-ahbs {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clock-div = <1>;
			clock-mult = <1>;
			clocks = <&cpus_clk>;
			clock-output-names = "ahbs";
		};

		apbs: clk@800141c {
			compatible = "allwinner,sun8i-a23-apb0-clk";
			reg = <0x0800141c 0x4>;
			#clock-cells = <0>;
			clocks = <&ahbs>;
			clock-output-names = "apbs";
		};

		apbs_gates: clk@8001428 {
			compatible = "allwinner,sun9i-a80-apbs-gates-clk";
			reg = <0x08001428 0x4>;
			#clock-cells = <1>;
			clocks = <&apbs>;
			clock-indices = <0>, <1>,
					<2>, <3>,
					<4>, <5>,
					<6>, <7>,
					<12>, <13>,
					<16>, <17>,
					<18>, <20>;
			clock-output-names = "apbs_pio", "apbs_ir",
					"apbs_timer", "apbs_rsb",
					"apbs_uart", "apbs_1wire",
					"apbs_i2c0", "apbs_i2c1",
					"apbs_ps2_0", "apbs_ps2_1",
					"apbs_dma", "apbs_i2s0",
					"apbs_i2s1", "apbs_twd";
		};

		r_1wire_clk: clk@8001450 {
			reg = <0x08001450 0x4>;
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			clocks = <&osc32k>, <&osc24M>;
			clock-output-names = "r_1wire";
		};

		r_ir_clk: clk@8001454 {
			reg = <0x08001454 0x4>;
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			clocks = <&osc32k>, <&osc24M>;
			clock-output-names = "r_ir";
		};
	};

	de: display-engine {
		compatible = "allwinner,sun9i-a80-display-engine";
		allwinner,pipelines = <&fe0>, <&fe1>;
		status = "disabled";
	};

	soc@20000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		/*
		 * map 64 bit address range down to 32 bits,
		 * as the peripherals are all under 512MB.
		 */
		ranges = <0 0 0 0x20000000>;

		sram_b: sram@20000 {
			/* 256 KiB secure SRAM at 0x20000 */
			compatible = "mmio-sram";
			reg = <0x00020000 0x40000>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x00020000 0x40000>;

			smp-sram@1000 {
				/*
				 * This is checked by BROM to determine if
				 * cpu0 should jump to SMP entry vector
				 */
				compatible = "allwinner,sun9i-a80-smp-sram";
				reg = <0x1000 0x8>;
			};
		};

		gmac: ethernet@830000 {
			compatible = "allwinner,sun7i-a20-gmac";
			reg = <0x00830000 0x1054>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
			clock-names = "stmmaceth", "allwinner_gmac_tx";
			resets = <&ccu RST_BUS_GMAC>;
			reset-names = "stmmaceth";
			snps,pbl = <2>;
			snps,fixed-burst;
			snps,force_sf_dma_mode;
			status = "disabled";

			mdio: mdio {
				compatible = "snps,dwmac-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		ehci0: usb@a00000 {
			compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
			reg = <0x00a00000 0x100>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&usb_clocks CLK_BUS_HCI0>;
			resets = <&usb_clocks RST_USB0_HCI>;
			phys = <&usbphy1>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci0: usb@a00400 {
			compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
			reg = <0x00a00400 0x100>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&usb_clocks CLK_BUS_HCI0>,
				 <&usb_clocks CLK_USB_OHCI0>;
			resets = <&usb_clocks RST_USB0_HCI>;
			phys = <&usbphy1>;
			phy-names = "usb";
			status = "disabled";
		};

		usbphy1: phy@a00800 {
			compatible = "allwinner,sun9i-a80-usb-phy";
			reg = <0x00a00800 0x4>;
			clocks = <&usb_clocks CLK_USB0_PHY>;
			clock-names = "phy";
			resets = <&usb_clocks RST_USB0_PHY>;
			reset-names = "phy";
			status = "disabled";
			#phy-cells = <0>;
		};

		ehci1: usb@a01000 {
			compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
			reg = <0x00a01000 0x100>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&usb_clocks CLK_BUS_HCI1>;
			resets = <&usb_clocks RST_USB1_HCI>;
			phys = <&usbphy2>;
			phy-names = "usb";
			status = "disabled";
		};

		usbphy2: phy@a01800 {
			compatible = "allwinner,sun9i-a80-usb-phy";
			reg = <0x00a01800 0x4>;
			clocks = <&usb_clocks CLK_USB1_PHY>,
				 <&usb_clocks CLK_USB_HSIC>,
				 <&usb_clocks CLK_USB1_HSIC>;
			clock-names = "phy",
				      "hsic_12M",
				      "hsic_480M";
			resets = <&usb_clocks RST_USB1_PHY>,
				 <&usb_clocks RST_USB1_HSIC>;
			reset-names = "phy",
				      "hsic";
			status = "disabled";
			#phy-cells = <0>;
			/* usb1 is always used with HSIC */
			phy_type = "hsic";
		};

		ehci2: usb@a02000 {
			compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
			reg = <0x00a02000 0x100>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&usb_clocks CLK_BUS_HCI2>;
			resets = <&usb_clocks RST_USB2_HCI>;
			phys = <&usbphy3>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci2: usb@a02400 {
			compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
			reg = <0x00a02400 0x100>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&usb_clocks CLK_BUS_HCI2>,
				 <&usb_clocks CLK_USB_OHCI2>;
			resets = <&usb_clocks RST_USB2_HCI>;
			phys = <&usbphy3>;
			phy-names = "usb";
			status = "disabled";
		};

		usbphy3: phy@a02800 {
			compatible = "allwinner,sun9i-a80-usb-phy";
			reg = <0x00a02800 0x4>;
			clocks = <&usb_clocks CLK_USB2_PHY>,
				 <&usb_clocks CLK_USB_HSIC>,
				 <&usb_clocks CLK_USB2_HSIC>;
			clock-names = "phy",
				      "hsic_12M",
				      "hsic_480M";
			resets = <&usb_clocks RST_USB2_PHY>,
				 <&usb_clocks RST_USB2_HSIC>;
			reset-names = "phy",
				      "hsic";
			status = "disabled";
			#phy-cells = <0>;
		};

		usb_clocks: clock@a08000 {
			compatible = "allwinner,sun9i-a80-usb-clks";
			reg = <0x00a08000 0x8>;
			clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
			clock-names = "bus", "hosc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		cpucfg@1700000 {
			compatible = "allwinner,sun9i-a80-cpucfg";
			reg = <0x01700000 0x100>;
		};

		crypto: crypto@1c02000 {
			compatible = "allwinner,sun9i-a80-crypto";
			reg = <0x01c02000 0x1000>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&ccu RST_BUS_SS>;
			clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
			clock-names = "bus", "mod";
		};

		mmc0: mmc@1c0f000 {
			compatible = "allwinner,sun9i-a80-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
				 <&ccu CLK_MMC0_OUTPUT>,
				 <&ccu CLK_MMC0_SAMPLE>;
			clock-names = "ahb", "mmc", "output", "sample";
			resets = <&mmc_config_clk 0>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@1c10000 {
			compatible = "allwinner,sun9i-a80-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
				 <&ccu CLK_MMC1_OUTPUT>,
				 <&ccu CLK_MMC1_SAMPLE>;
			clock-names = "ahb", "mmc", "output", "sample";
			resets = <&mmc_config_clk 1>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc2: mmc@1c11000 {
			compatible = "allwinner,sun9i-a80-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
				 <&ccu CLK_MMC2_OUTPUT>,
				 <&ccu CLK_MMC2_SAMPLE>;
			clock-names = "ahb", "mmc", "output", "sample";
			resets = <&mmc_config_clk 2>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc3: mmc@1c12000 {
			compatible = "allwinner,sun9i-a80-mmc";
			reg = <0x01c12000 0x1000>;
			clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
				 <&ccu CLK_MMC3_OUTPUT>,
				 <&ccu CLK_MMC3_SAMPLE>;
			clock-names = "ahb", "mmc", "output", "sample";
			resets = <&mmc_config_clk 3>;
			reset-names = "ahb";
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc_config_clk: clk@1c13000 {
			compatible = "allwinner,sun9i-a80-mmc-config-clk";
			reg = <0x01c13000 0x10>;
			clocks = <&ccu CLK_BUS_MMC>;
			resets = <&ccu RST_BUS_MMC>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			clock-output-names = "mmc0_config", "mmc1_config",
					     "mmc2_config", "mmc3_config";
		};

		gic: interrupt-controller@1c41000 {
			compatible = "arm,gic-400";
			reg = <0x01c41000 0x1000>,
			      <0x01c42000 0x2000>,
			      <0x01c44000 0x2000>,
			      <0x01c46000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		cci: cci@1c90000 {
			compatible = "arm,cci-400";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x01c90000 0x1000>;
			ranges = <0x0 0x01c90000 0x10000>;

			cci_control0: slave-if@4000 {
				compatible = "arm,cci-400-ctrl-if";
				interface-type = "ace";
				reg = <0x4000 0x1000>;
			};

			cci_control1: slave-if@5000 {
				compatible = "arm,cci-400-ctrl-if";
				interface-type = "ace";
				reg = <0x5000 0x1000>;
			};

			pmu@9000 {
				 compatible = "arm,cci-400-pmu,r1";
				 reg = <0x9000 0x5000>;
				 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
					      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
					      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
					      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
					      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		de_clocks: clock@3000000 {
			compatible = "allwinner,sun9i-a80-de-clks";
			reg = <0x03000000 0x30>;
			clocks = <&ccu CLK_DE>,
				 <&ccu CLK_SDRAM>,
				 <&ccu CLK_BUS_DE>;
			clock-names = "mod",
				      "dram",
				      "bus";
			resets = <&ccu RST_BUS_DE>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		fe0: display-frontend@3100000 {
			compatible = "allwinner,sun9i-a80-display-frontend";
			reg = <0x03100000 0x40000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
				 <&de_clocks CLK_DRAM_FE0>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&de_clocks RST_FE0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				fe0_out: port@1 {
					reg = <1>;

					fe0_out_deu0: endpoint {
						remote-endpoint = <&deu0_in_fe0>;
					};
				};
			};
		};

		fe1: display-frontend@3140000 {
			compatible = "allwinner,sun9i-a80-display-frontend";
			reg = <0x03140000 0x40000>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
				 <&de_clocks CLK_DRAM_FE1>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&de_clocks RST_FE0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				fe1_out: port@1 {
					reg = <1>;

					fe1_out_deu1: endpoint {
						remote-endpoint = <&deu1_in_fe1>;
					};
				};
			};
		};

		be0: display-backend@3200000 {
			compatible = "allwinner,sun9i-a80-display-backend";
			reg = <0x03200000 0x40000>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
				 <&de_clocks CLK_DRAM_BE0>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&de_clocks RST_BE0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				be0_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					be0_in_deu0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&deu0_out_be0>;
					};

					be0_in_deu1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&deu1_out_be0>;
					};
				};

				be0_out: port@1 {
					reg = <1>;

					be0_out_drc0: endpoint {
						remote-endpoint = <&drc0_in_be0>;
					};
				};
			};
		};

		be1: display-backend@3240000 {
			compatible = "allwinner,sun9i-a80-display-backend";
			reg = <0x03240000 0x40000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
				 <&de_clocks CLK_DRAM_BE1>;
			clock-names = "ahb", "mod",
				      "ram";
			resets = <&de_clocks RST_BE1>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				be1_in: port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					be1_in_deu0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&deu0_out_be1>;
					};

					be1_in_deu1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&deu1_out_be1>;
					};
				};

				be1_out: port@1 {
					reg = <1>;

					be1_out_drc1: endpoint {
						remote-endpoint = <&drc1_in_be1>;
					};
				};
			};
		};

		deu0: deu@3300000 {
			compatible = "allwinner,sun9i-a80-deu";
			reg = <0x03300000 0x40000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&de_clocks CLK_BUS_DEU0>,
				 <&de_clocks CLK_IEP_DEU0>,
				 <&de_clocks CLK_DRAM_DEU0>;
			clock-names = "ahb",
				      "mod",
				      "ram";
			resets = <&de_clocks RST_DEU0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				deu0_in: port@0 {
					reg = <0>;

					deu0_in_fe0: endpoint {
						remote-endpoint = <&fe0_out_deu0>;
					};
				};

				deu0_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					deu0_out_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_in_deu0>;
					};

					deu0_out_be1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&be1_in_deu0>;
					};
				};
			};
		};

		deu1: deu@3340000 {
			compatible = "allwinner,sun9i-a80-deu";
			reg = <0x03340000 0x40000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&de_clocks CLK_BUS_DEU1>,
				 <&de_clocks CLK_IEP_DEU1>,
				 <&de_clocks CLK_DRAM_DEU1>;
			clock-names = "ahb",
				      "mod",
				      "ram";
			resets = <&de_clocks RST_DEU1>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				deu1_in: port@0 {
					reg = <0>;

					deu1_in_fe1: endpoint {
						remote-endpoint = <&fe1_out_deu1>;
					};
				};

				deu1_out: port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					deu1_out_be0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&be0_in_deu1>;
					};

					deu1_out_be1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&be1_in_deu1>;
					};
				};
			};
		};

		drc0: drc@3400000 {
			compatible = "allwinner,sun9i-a80-drc";
			reg = <0x03400000 0x40000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&de_clocks CLK_BUS_DRC0>,
				 <&de_clocks CLK_IEP_DRC0>,
				 <&de_clocks CLK_DRAM_DRC0>;
			clock-names = "ahb",
				      "mod",
				      "ram";
			resets = <&de_clocks RST_DRC0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				drc0_in: port@0 {
					reg = <0>;

					drc0_in_be0: endpoint {
						remote-endpoint = <&be0_out_drc0>;
					};
				};

				drc0_out: port@1 {
					reg = <1>;

					drc0_out_tcon0: endpoint {
						remote-endpoint = <&tcon0_in_drc0>;
					};
				};
			};
		};

		drc1: drc@3440000 {
			compatible = "allwinner,sun9i-a80-drc";
			reg = <0x03440000 0x40000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&de_clocks CLK_BUS_DRC1>,
				 <&de_clocks CLK_IEP_DRC1>,
				 <&de_clocks CLK_DRAM_DRC1>;
			clock-names = "ahb",
				      "mod",
				      "ram";
			resets = <&de_clocks RST_DRC1>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				drc1_in: port@0 {
					reg = <0>;

					drc1_in_be1: endpoint {
						remote-endpoint = <&be1_out_drc1>;
					};
				};

				drc1_out: port@1 {
					reg = <1>;

					drc1_out_tcon1: endpoint {
						remote-endpoint = <&tcon1_in_drc1>;
					};
				};
			};
		};

		tcon0: lcd-controller@3c00000 {
			compatible = "allwinner,sun9i-a80-tcon-lcd";
			reg = <0x03c00000 0x10000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
			clock-names = "ahb", "tcon-ch0";
			resets = <&ccu RST_BUS_LCD0>,
				 <&ccu RST_BUS_EDP>,
				 <&ccu RST_BUS_LVDS>;
			reset-names = "lcd",
				      "edp",
				      "lvds";
			clock-output-names = "tcon0-pixel-clock";
			#clock-cells = <0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon0_in: port@0 {
					reg = <0>;

					tcon0_in_drc0: endpoint {
						remote-endpoint = <&drc0_out_tcon0>;
					};
				};

				tcon0_out: port@1 {
					reg = <1>;
				};
			};
		};

		tcon1: lcd-controller@3c10000 {
			compatible = "allwinner,sun9i-a80-tcon-tv";
			reg = <0x03c10000 0x10000>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
			clock-names = "ahb", "tcon-ch1";
			resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
			reset-names = "lcd", "edp";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				tcon1_in: port@0 {
					reg = <0>;

					tcon1_in_drc1: endpoint {
						remote-endpoint = <&drc1_out_tcon1>;
					};
				};

				tcon1_out: port@1 {
					reg = <1>;
				};
			};
		};

		ccu: clock@6000000 {
			compatible = "allwinner,sun9i-a80-ccu";
			reg = <0x06000000 0x800>;
			clocks = <&osc24M>, <&osc32k>;
			clock-names = "hosc", "losc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		timer@6000c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x06000c00 0xa0>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&osc24M>;
		};

		wdt: watchdog@6000ca0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x06000ca0 0x20>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		pio: pinctrl@6000800 {
			compatible = "allwinner,sun9i-a80-pinctrl";
			reg = <0x06000800 0x400>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#gpio-cells = <3>;

			gmac_rgmii_pins: gmac-rgmii-pins {
				pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
				       "PA7", "PA8", "PA9", "PA10", "PA12",
				       "PA13", "PA15", "PA16", "PA17";
				function = "gmac";
				/*
				 * data lines in RGMII mode use DDR mode
				 * and need a higher signal drive strength
				 */
				drive-strength = <40>;
			};

			i2c3_pins: i2c3-pins {
				pins = "PG10", "PG11";
				function = "i2c3";
			};

			lcd0_rgb888_pins: lcd0-rgb888-pins {
				pins = "PD0", "PD1", "PD2", "PD3",
				       "PD4", "PD5", "PD6", "PD7",
				       "PD8", "PD9", "PD10", "PD11",
				       "PD12", "PD13", "PD14", "PD15",
				       "PD16", "PD17", "PD18", "PD19",
				       "PD20", "PD21", "PD22", "PD23",
				       "PD24", "PD25", "PD26", "PD27";
				function = "lcd0";
			};

			mmc0_pins: mmc0-pins {
				pins = "PF0", "PF1" ,"PF2", "PF3",
				       "PF4", "PF5";
				function = "mmc0";
				drive-strength = <30>;
				bias-pull-up;
			};

			mmc1_pins: mmc1-pins {
				pins = "PG0", "PG1" ,"PG2", "PG3",
						 "PG4", "PG5";
				function = "mmc1";
				drive-strength = <30>;
				bias-pull-up;
			};

			mmc2_8bit_pins: mmc2-8bit-pins {
				pins = "PC6", "PC7", "PC8", "PC9",
				       "PC10", "PC11", "PC12",
				       "PC13", "PC14", "PC15",
				       "PC16";
				function = "mmc2";
				drive-strength = <30>;
				bias-pull-up;
			};

			uart0_ph_pins: uart0-ph-pins {
				pins = "PH12", "PH13";
				function = "uart0";
			};

			uart4_pins: uart4-pins {
				pins = "PG12", "PG13", "PG14", "PG15";
				function = "uart4";
			};
		};

		uart0: serial@7000000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07000000 0x400>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART0>;
			resets = <&ccu RST_BUS_UART0>;
			status = "disabled";
		};

		uart1: serial@7000400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07000400 0x400>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART1>;
			resets = <&ccu RST_BUS_UART1>;
			status = "disabled";
		};

		uart2: serial@7000800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07000800 0x400>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART2>;
			resets = <&ccu RST_BUS_UART2>;
			status = "disabled";
		};

		uart3: serial@7000c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07000c00 0x400>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART3>;
			resets = <&ccu RST_BUS_UART3>;
			status = "disabled";
		};

		uart4: serial@7001000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07001000 0x400>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART4>;
			resets = <&ccu RST_BUS_UART4>;
			status = "disabled";
		};

		uart5: serial@7001400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x07001400 0x400>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART5>;
			resets = <&ccu RST_BUS_UART5>;
			status = "disabled";
		};

		i2c0: i2c@7002800 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x07002800 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C0>;
			resets = <&ccu RST_BUS_I2C0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@7002c00 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x07002c00 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C1>;
			resets = <&ccu RST_BUS_I2C1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@7003000 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x07003000 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C2>;
			resets = <&ccu RST_BUS_I2C2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c3: i2c@7003400 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x07003400 0x400>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C3>;
			resets = <&ccu RST_BUS_I2C3>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c4: i2c@7003800 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x07003800 0x400>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ccu CLK_BUS_I2C4>;
			resets = <&ccu RST_BUS_I2C4>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		r_wdt: watchdog@8001000 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x08001000 0x20>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc24M>;
		};

		prcm@8001400 {
			compatible = "allwinner,sun9i-a80-prcm";
			reg = <0x08001400 0x200>;
		};

		apbs_rst: reset@80014b0 {
			reg = <0x080014b0 0x4>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			#reset-cells = <1>;
		};

		nmi_intc: interrupt-controller@80015a0 {
			compatible = "allwinner,sun9i-a80-nmi";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x080015a0 0xc>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		};

		r_ir: ir@8002000 {
			compatible = "allwinner,sun6i-a31-ir";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&r_ir_pins>;
			clocks = <&apbs_gates 1>, <&r_ir_clk>;
			clock-names = "apb", "ir";
			resets = <&apbs_rst 1>;
			reg = <0x08002000 0x40>;
			status = "disabled";
		};

		r_uart: serial@8002800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x08002800 0x400>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apbs_gates 4>;
			resets = <&apbs_rst 4>;
			status = "disabled";
		};

		r_pio: pinctrl@8002c00 {
			compatible = "allwinner,sun9i-a80-r-pinctrl";
			reg = <0x08002c00 0x400>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#gpio-cells = <3>;

			r_ir_pins: r-ir-pins {
				pins = "PL6";
				function = "s_cir_rx";
			};

			r_rsb_pins: r-rsb-pins {
				pins = "PN0", "PN1";
				function = "s_rsb";
				drive-strength = <20>;
				bias-pull-up;
			};
		};

		r_rsb: rsb@8003400 {
			compatible = "allwinner,sun8i-a23-rsb";
			reg = <0x08003400 0x400>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apbs_gates 3>;
			clock-frequency = <3000000>;
			resets = <&apbs_rst 3>;
			pinctrl-names = "default";
			pinctrl-0 = <&r_rsb_pins>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
 * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
 */

/dts-v1/;
#include "suniv-f1c100s.dtsi"

/ {
	model = "Lichee Pi Nano";
	compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";

	aliases {
		mmc0 = &mmc0;
		serial0 = &uart0;
		spi0 = &spi0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	reg_vcc3v3: vcc3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&mmc0 {
	broken-cd;
	bus-width = <4>;
	disable-wp;
	status = "okay";
	vmmc-supply = <&reg_vcc3v3>;
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pc_pins>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "winbond,w25q128", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <40000000>;
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pe_pins>;
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
 * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
 * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
 */

#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
#include <dt-bindings/reset/suniv-ccu-f1c100s.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&intc>;

	clocks {
		osc24M: clk-24M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: clk-32k {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,arm926ej-s";
			device_type = "cpu";
			reg = <0x0>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		sram-controller@1c00000 {
			compatible = "allwinner,suniv-f1c100s-system-control",
				     "allwinner,sun4i-a10-system-control";
			reg = <0x01c00000 0x30>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			sram_d: sram@10000 {
				compatible = "mmio-sram";
				reg = <0x00010000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00010000 0x1000>;

				otg_sram: sram-section@0 {
					compatible = "allwinner,suniv-f1c100s-sram-d",
						     "allwinner,sun4i-a10-sram-d";
					reg = <0x0000 0x1000>;
					status = "disabled";
				};
			};
		};

		spi0: spi@1c05000 {
			compatible = "allwinner,suniv-f1c100s-spi",
				     "allwinner,sun8i-h3-spi";
			reg = <0x01c05000 0x1000>;
			interrupts = <10>;
			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
			clock-names = "ahb", "mod";
			resets = <&ccu RST_BUS_SPI0>;
			status = "disabled";
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@1c06000 {
			compatible = "allwinner,suniv-f1c100s-spi",
				     "allwinner,sun8i-h3-spi";
			reg = <0x01c06000 0x1000>;
			interrupts = <11>;
			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
			clock-names = "ahb", "mod";
			resets = <&ccu RST_BUS_SPI1>;
			status = "disabled";
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc0: mmc@1c0f000 {
			compatible = "allwinner,suniv-f1c100s-mmc",
				     "allwinner,sun7i-a20-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC0>,
				 <&ccu CLK_MMC0>,
				 <&ccu CLK_MMC0_OUTPUT>,
				 <&ccu CLK_MMC0_SAMPLE>;
			clock-names = "ahb", "mmc", "output", "sample";
			resets = <&ccu RST_BUS_MMC0>;
			reset-names = "ahb";
			interrupts = <23>;
			pinctrl-names = "default";
			pinctrl-0 = <&mmc0_pins>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc1: mmc@1c10000 {
			compatible = "allwinner,suniv-f1c100s-mmc",
				     "allwinner,sun7i-a20-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ccu CLK_BUS_MMC1>,
				 <&ccu CLK_MMC1>,
				 <&ccu CLK_MMC1_OUTPUT>,
				 <&ccu CLK_MMC1_SAMPLE>;
			clock-names = "ahb", "mmc", "output", "sample";
			resets = <&ccu RST_BUS_MMC1>;
			reset-names = "ahb";
			interrupts = <24>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		ccu: clock@1c20000 {
			compatible = "allwinner,suniv-f1c100s-ccu";
			reg = <0x01c20000 0x400>;
			clocks = <&osc24M>, <&osc32k>;
			clock-names = "hosc", "losc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		intc: interrupt-controller@1c20400 {
			compatible = "allwinner,suniv-f1c100s-ic";
			reg = <0x01c20400 0x400>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		pio: pinctrl@1c20800 {
			compatible = "allwinner,suniv-f1c100s-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <38>, <39>, <40>;
			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
			clock-names = "apb", "hosc", "losc";
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <3>;
			#gpio-cells = <3>;

			mmc0_pins: mmc0-pins {
				pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
				function = "mmc0";
				drive-strength = <30>;
			};

			/omit-if-no-ref/
			i2c0_pd_pins: i2c0-pd-pins {
				pins = "PD0", "PD12";
				function = "i2c0";
			};

			spi0_pc_pins: spi0-pc-pins {
				pins = "PC0", "PC1", "PC2", "PC3";
				function = "spi0";
			};

			uart0_pe_pins: uart0-pe-pins {
				pins = "PE0", "PE1";
				function = "uart0";
			};
		};

		i2c0: i2c@1c27000 {
			compatible = "allwinner,suniv-f1c100s-i2c",
				     "allwinner,sun6i-a31-i2c";
			reg = <0x01c27000 0x400>;
			interrupts = <7>;
			clocks = <&ccu CLK_BUS_I2C0>;
			resets = <&ccu RST_BUS_I2C0>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@1c27400 {
			compatible = "allwinner,suniv-f1c100s-i2c",
				     "allwinner,sun6i-a31-i2c";
			reg = <0x01c27400 0x400>;
			interrupts = <8>;
			clocks = <&ccu CLK_BUS_I2C1>;
			resets = <&ccu RST_BUS_I2C1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@1c27800 {
			compatible = "allwinner,suniv-f1c100s-i2c",
				     "allwinner,sun6i-a31-i2c";
			reg = <0x01c27800 0x400>;
			interrupts = <9>;
			clocks = <&ccu CLK_BUS_I2C2>;
			resets = <&ccu RST_BUS_I2C2>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		timer@1c20c00 {
			compatible = "allwinner,suniv-f1c100s-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <13>, <14>, <15>;
			clocks = <&osc24M>;
		};

		wdt: watchdog@1c20ca0 {
			compatible = "allwinner,suniv-f1c100s-wdt",
				     "allwinner,sun6i-a31-wdt";
			reg = <0x01c20ca0 0x20>;
			interrupts = <16>;
			clocks = <&osc32k>;
		};

		pwm: pwm@1c21000 {
			compatible = "allwinner,suniv-f1c100s-pwm",
				     "allwinner,sun7i-a20-pwm";
			reg = <0x01c21000 0x400>;
			clocks = <&osc24M>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		ir: ir@1c22c00 {
			compatible = "allwinner,suniv-f1c100s-ir",
				     "allwinner,sun6i-a31-ir";
			reg = <0x01c22c00 0x400>;
			clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>;
			clock-names = "apb", "ir";
			resets = <&ccu RST_BUS_IR>;
			interrupts = <6>;
			status = "disabled";
		};

		lradc: lradc@1c23400 {
			compatible = "allwinner,suniv-f1c100s-lradc",
				     "allwinner,sun8i-a83t-r-lradc";
			reg = <0x01c23400 0x400>;
			interrupts = <22>;
			status = "disabled";
		};

		uart0: serial@1c25000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c25000 0x400>;
			interrupts = <1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART0>;
			resets = <&ccu RST_BUS_UART0>;
			status = "disabled";
		};

		uart1: serial@1c25400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c25400 0x400>;
			interrupts = <2>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART1>;
			resets = <&ccu RST_BUS_UART1>;
			status = "disabled";
		};

		uart2: serial@1c25800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c25800 0x400>;
			interrupts = <3>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&ccu CLK_BUS_UART2>;
			resets = <&ccu RST_BUS_UART2>;
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for Sunplus SP7021
 *
 * Copyright (C) 2021 Sunplus Technology Co.
 */

#include "sunplus-sp7021.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "sunplus,sp7021-achip", "sunplus,sp7021";
	model = "Sunplus SP7021 (CA7)";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			clock-frequency = <931000000>;
		};
		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
			clock-frequency = <931000000>;
		};
		cpu2: cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <2>;
			clock-frequency = <931000000>;
		};
		cpu3: cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <3>;
			clock-frequency = <931000000>;
		};
	};

	gic: interrupt-controller@9f101000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x9f101000 0x1000>,
		      <0x9f102000 0x2000>,
		      <0x9f104000 0x2000>,
		      <0x9f106000 0x2000>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <XTAL>;
		arm,cpu-registers-not-fw-configured;
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	soc@9c000000 {
		intc: interrupt-controller@780 {
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for Sunplus SP7021 Demo V3 SBC board
 *
 * Copyright (C) Sunplus Technology Co.
 */

/dts-v1/;

#include "sunplus-sp7021-achip.dtsi"

/ {
	compatible = "sunplus,sp7021-demo-v3", "sunplus,sp7021";
	model = "Sunplus SP7021/CA7/Demo_V3";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for Sunplus SP7021
 *
 * Copyright (C) 2021 Sunplus Technology Co.
 */

#include <dt-bindings/clock/sunplus,sp7021-clkc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/sunplus,sp7021-reset.h>
#include <dt-bindings/pinctrl/sppctl-sp7021.h>
#include <dt-bindings/gpio/gpio.h>

#define XTAL	27000000

/ {
	compatible = "sunplus,sp7021";
	model = "Sunplus SP7021";

	clocks {
		extclk: osc0 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <XTAL>;
			clock-output-names = "extclk";
		};
	};

	soc@9c000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x9c000000 0x400000>;
		interrupt-parent = <&intc>;

		clkc: clock-controller@4 {
			compatible = "sunplus,sp7021-clkc";
			reg = <0x4 0x28>,
			      <0x200 0x44>,
			      <0x268 0x04>;
			clocks = <&extclk>;
			#clock-cells = <1>;
		};

		intc: interrupt-controller@780 {
			compatible = "sunplus,sp7021-intc";
			reg = <0x780 0x80>, <0xa80 0x80>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		otp: otp@af00 {
			compatible = "sunplus,sp7021-ocotp";
			reg = <0xaf00 0x34>, <0xaf80 0x58>;
			reg-names = "hb_gpio", "otprx";
			clocks = <&clkc CLK_OTPRX>;
			resets = <&rstc RST_OTPRX>;
			#address-cells = <1>;
			#size-cells = <1>;

			therm_calib: thermal-calibration@14 {
				reg = <0x14 0x3>;
			};
			disc_vol: disconnect-voltage@18 {
				reg = <0x18 0x2>;
			};
			mac_addr0: mac-address0@34 {
				reg = <0x34 0x6>;
			};
			mac_addr1: mac-address1@3a {
				reg = <0x3a 0x6>;
			};
		};

		pctl: pinctrl@100 {
			compatible = "sunplus,sp7021-pctl";
			reg = <0x100 0x100>,
			      <0x300 0x100>,
			      <0x32e4 0x1C>,
			      <0x80 0x20>;
			reg-names = "moon2", "gpioxt", "first", "moon1";
			gpio-controller;
			#gpio-cells = <2>;
			clocks = <&clkc CLK_GPIO>;
			resets = <&rstc RST_GPIO>;

			emac_pins: pinmux-emac-pins {
				sunplus,pins = <
					SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
					SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
					SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
					SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
					SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
					SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
					SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
					SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
					SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
					SPPCTL_IOPAD(45,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXER,0)
					SPPCTL_IOPAD(59,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXEN,0)
					SPPCTL_IOPAD(57,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD0,0)
					SPPCTL_IOPAD(58,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD1,0)
					SPPCTL_IOPAD(54,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_CRSDV,0)
					SPPCTL_IOPAD(55,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD0,0)
					SPPCTL_IOPAD(56,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD1,0)
					SPPCTL_IOPAD(53,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXER,0)
				>;
				sunplus,zerofunc = <
					MUXF_L2SW_LED_FLASH0
					MUXF_L2SW_LED_FLASH1
					MUXF_L2SW_LED_ON0
					MUXF_L2SW_LED_ON1
					MUXF_DAISY_MODE
				>;
			};

			emmc_pins: pinmux-emmc-pins {
				function = "CARD0_EMMC";
				groups = "CARD0_EMMC";
			};

			leds_pins: pinmux-leds-pins {
				sunplus,pins = < SPPCTL_IOPAD(0,SPPCTL_PCTL_G_GPIO,0,SPPCTL_PCTL_L_OUT) >;
			};

			sdcard_pins: pinmux-sdcard-pins {
				function = "SD_CARD";
				groups = "SD_CARD";
				sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
			};

			spi0_pins: pinmux-spi0-pins {
				sunplus,pins = <
					SPPCTL_IOPAD(26,SPPCTL_PCTL_G_GPIO,0,0)
					SPPCTL_IOPAD(28,SPPCTL_PCTL_G_GPIO,0,0)
					SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DO,0)
					SPPCTL_IOPAD(25,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DI,0)
					SPPCTL_IOPAD(27,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_CLK,0)
				>;
			};

			uart0_pins: pinmux-uart0-pins {
				function = "UA0";
				groups = "UA0";
			};

			uart1_pins: pinmux-uart1-pins {
				sunplus,pins = <
					SPPCTL_IOPAD(14,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
					SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
				>;
			};

			uart2_pins: pinmux-uart2-pins {
				sunplus,pins = <
					SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA2_TX,0)
					SPPCTL_IOPAD(17,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RX,0)
					SPPCTL_IOPAD(18,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RTS,0)
					SPPCTL_IOPAD(19,SPPCTL_PCTL_G_PMUX,MUXF_UA2_CTS,0)
				>;
			};

			uart4_pins: pinmux-uart4-pins {
				sunplus,pins = <
					SPPCTL_IOPAD(22,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
					SPPCTL_IOPAD(20,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
					SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RTS,0)
					SPPCTL_IOPAD(21,SPPCTL_PCTL_G_PMUX,MUXF_UA4_CTS,0)
				>;
			};
		};

		rstc: reset@54 {
			compatible = "sunplus,sp7021-reset";
			reg = <0x54 0x28>;
			#reset-cells = <1>;
		};

		rtc: rtc@3a00 {
			compatible = "sunplus,sp7021-rtc";
			reg = <0x3a00 0x80>;
			reg-names = "rtc";
			clocks = <&clkc CLK_RTC>;
			resets = <&rstc RST_RTC>;
			interrupts = <163 IRQ_TYPE_EDGE_RISING>;
		};

		spi_controller0: spi@2d80 {
			compatible = "sunplus,sp7021-spi";
			reg = <0x2d80 0x80>, <0x2e00 0x80>;
			reg-names = "master", "slave";
			interrupts = <144 IRQ_TYPE_LEVEL_HIGH>,
				     <146 IRQ_TYPE_LEVEL_HIGH>,
				     <145 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dma_w", "master_risc", "slave_risc";
			clocks = <&clkc CLK_SPI_COMBO_0>;
			resets = <&rstc RST_SPI_COMBO_0>;

			pinctrl-names = "default";
			pinctrl-0 = <&spi0_pins>;
			cs-gpios = <&pctl 26 GPIO_ACTIVE_LOW>,
				   <&pctl 28 GPIO_ACTIVE_LOW>;
		};

		spi_controller1: spi@f480 {
			compatible = "sunplus,sp7021-spi";
			reg = <0xf480 0x80>, <0xf500 0x80>;
			reg-names = "master", "slave";
			interrupts = <67 IRQ_TYPE_LEVEL_HIGH>,
				     <69 IRQ_TYPE_LEVEL_HIGH>,
				     <68 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dma_w", "master_risc", "slave_risc";
			clocks = <&clkc CLK_SPI_COMBO_1>;
			resets = <&rstc RST_SPI_COMBO_1>;
			status = "disabled";
		};

		spi_controller2: spi@f600 {
			compatible = "sunplus,sp7021-spi";
			reg = <0xf600 0x80>, <0xf680 0x80>;
			reg-names = "master", "slave";
			interrupts = <70 IRQ_TYPE_LEVEL_HIGH>,
				     <72 IRQ_TYPE_LEVEL_HIGH>,
				     <71 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dma_w", "master_risc", "slave_risc";
			clocks = <&clkc CLK_SPI_COMBO_2>;
			resets = <&rstc RST_SPI_COMBO_2>;
			status = "disabled";
		};

		spi_controller3: spi@f780 {
			compatible = "sunplus,sp7021-spi";
			reg = <0xf780 0x80>, <0xf800 0x80>;
			reg-names = "master", "slave";
			interrupts = <73 IRQ_TYPE_LEVEL_HIGH>,
				     <75 IRQ_TYPE_LEVEL_HIGH>,
				     <74 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dma_w", "master_risc", "slave_risc";
			clocks = <&clkc CLK_SPI_COMBO_3>;
			resets = <&rstc RST_SPI_COMBO_3>;
			status = "disabled";
		};

		uart0: serial@900 {
			compatible = "sunplus,sp7021-uart";
			reg = <0x900 0x80>;
			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLK_UA0>;
			resets = <&rstc RST_UA0>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_pins>;
		};

		uart1: serial@980 {
			compatible = "sunplus,sp7021-uart";
			reg = <0x980 0x80>;
			interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLK_UA1>;
			resets = <&rstc RST_UA1>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart1_pins>;
			status = "disabled";
		};

		uart2: serial@800 {
			compatible = "sunplus,sp7021-uart";
			reg = <0x800 0x80>;
			interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLK_UA2>;
			resets = <&rstc RST_UA2>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart2_pins>;
			status = "disabled";
		};

		uart3: serial@880 {
			compatible = "sunplus,sp7021-uart";
			reg = <0x880 0x80>;
			interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLK_UA3>;
			resets = <&rstc RST_UA3>;
			status = "disabled";
		};

		uart4: serial@8780 {
			compatible = "sunplus,sp7021-uart";
			reg = <0x8780 0x80>;
			interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLK_UA4>;
			resets = <&rstc RST_UA4>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart4_pins>;
			status = "disabled";
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&leds_pins>;
		system-led {
			label = "system-led";
			gpios = <&pctl 0 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "heartbeat";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
 */

#include "sunxi-bananapi-m2-plus.dtsi"

/ {
	/*
	 * Bananapi M2+ v1.2 uses a GPIO line to change the effective
	 * resistance on the CPU regulator's feedback pin.
	 */
	reg_vdd_cpux: vdd-cpux {
		compatible = "regulator-gpio";
		regulator-name = "vdd-cpux";
		regulator-type = "voltage";
		regulator-boot-on;
		regulator-always-on;
		regulator-min-microvolt = <1108475>;
		regulator-max-microvolt = <1308475>;
		regulator-ramp-delay = <50>; /* 4ms */
		gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
		gpios-states = <0x1>;
		states = <1108475 0>, <1308475 1>;
	};
};

&cpu0 {
	cpu-supply = <&reg_vdd_cpux>;
};

&cpu1 {
	cpu-supply = <&reg_vdd_cpux>;
};

&cpu2 {
	cpu-supply = <&reg_vdd_cpux>;
};

&cpu3 {
	cpu-supply = <&reg_vdd_cpux>;
};