code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright Altera Corporation (C) 2015. All rights reserved.
 */

/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/stratix10-clock.h>

/ {
	compatible = "altr,socfpga-stratix10";
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		service_reserved: svcbuffer@0 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x0 0x0 0x1000000>;
			alignment = <0x1000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x1>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x3>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 170 4>,
			     <0 171 4>,
			     <0 172 4>,
			     <0 173 4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
		interrupt-parent = <&intc>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	/* Local timer */
	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
		interrupt-parent = <&intc>;
	};

	intc: interrupt-controller@fffc1000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0xfffc1000 0x0 0x1000>,
		      <0x0 0xfffc2000 0x0 0x2000>,
		      <0x0 0xfffc4000 0x0 0x2000>,
		      <0x0 0xfffc6000 0x0 0x2000>;
	};

	clocks {
		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		cb_intosc_ls_clk: cb-intosc-ls-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		f2s_free_clk: f2s-free-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		osc1: osc1 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		qspi_clk: qspi-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <200000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges = <0 0 0 0xffffffff>;

		base_fpga_region {
			#address-cells = <0x1>;
			#size-cells = <0x1>;

			compatible = "fpga-region";
			fpga-mgr = <&fpga_mgr>;
		};

		clkmgr: clock-controller@ffd10000 {
			compatible = "intel,stratix10-clkmgr";
			reg = <0xffd10000 0x1000>;
			#clock-cells = <1>;
		};

		gmac0: ethernet@ff800000 {
			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff800000 0x2000>;
			interrupts = <0 90 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			tx-fifo-depth = <16384>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <256>;
			iommus = <&smmu 1>;
			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
			status = "disabled";
		};

		gmac1: ethernet@ff802000 {
			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff802000 0x2000>;
			interrupts = <0 91 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			tx-fifo-depth = <16384>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <256>;
			iommus = <&smmu 2>;
			altr,sysmgr-syscon = <&sysmgr 0x48 8>;
			status = "disabled";
		};

		gmac2: ethernet@ff804000 {
			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff804000 0x2000>;
			interrupts = <0 92 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			tx-fifo-depth = <16384>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <256>;
			iommus = <&smmu 3>;
			altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
			status = "disabled";
		};

		gpio0: gpio@ffc03200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc03200 0x100>;
			resets = <&rst GPIO0_RESET>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 110 4>;
			};
		};

		gpio1: gpio@ffc03300 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc03300 0x100>;
			resets = <&rst GPIO1_RESET>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 111 4>;
			};
		};

		i2c0: i2c@ffc02800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02800 0x100>;
			interrupts = <0 103 4>;
			resets = <&rst I2C0_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		i2c1: i2c@ffc02900 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02900 0x100>;
			interrupts = <0 104 4>;
			resets = <&rst I2C1_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		i2c2: i2c@ffc02a00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02a00 0x100>;
			interrupts = <0 105 4>;
			resets = <&rst I2C2_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		i2c3: i2c@ffc02b00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02b00 0x100>;
			interrupts = <0 106 4>;
			resets = <&rst I2C3_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		i2c4: i2c@ffc02c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02c00 0x100>;
			interrupts = <0 107 4>;
			resets = <&rst I2C4_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		mmc: mmc@ff808000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff808000 0x1000>;
			interrupts = <0 96 4>;
			fifo-depth = <0x400>;
			resets = <&rst SDMMC_RESET>;
			reset-names = "reset";
			clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
				 <&clkmgr STRATIX10_SDMMC_CLK>;
			clock-names = "biu", "ciu";
			iommus = <&smmu 5>;
			altr,sysmgr-syscon = <&sysmgr 0x28 4>;
			status = "disabled";
		};

		nand: nand-controller@ffb90000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-denali-nand";
			reg = <0xffb90000 0x10000>,
			      <0xffb80000 0x1000>;
			reg-names = "nand_data", "denali_reg";
			interrupts = <0 97 4>;
			clocks = <&clkmgr STRATIX10_NAND_CLK>,
				 <&clkmgr STRATIX10_NAND_X_CLK>,
				 <&clkmgr STRATIX10_NAND_ECC_CLK>;
			clock-names = "nand", "nand_x", "ecc";
			resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
			status = "disabled";
		};

		ocram: sram@ffe00000 {
			compatible = "mmio-sram";
			reg = <0xffe00000 0x100000>;
		};

		pdma: dma-controller@ffda0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xffda0000 0x1000>;
			interrupts = <0 81 4>,
				     <0 82 4>,
				     <0 83 4>,
				     <0 84 4>,
				     <0 85 4>,
				     <0 86 4>,
				     <0 87 4>,
				     <0 88 4>,
				     <0 89 4>;
			#dma-cells = <1>;
			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
			clock-names = "apb_pclk";
			resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
			reset-names = "dma", "dma-ocp";
		};

		rst: rstmgr@ffd11000 {
			#reset-cells = <1>;
			compatible = "altr,stratix10-rst-mgr";
			reg = <0xffd11000 0x1000>;
		};

		smmu: iommu@fa000000 {
			compatible = "arm,mmu-500", "arm,smmu-v2";
			reg = <0xfa000000 0x40000>;
			#global-interrupts = <2>;
			#iommu-cells = <1>;
			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
			clock-names = "iommu";
			interrupt-parent = <&intc>;
			interrupts = <0 128 4>,	/* Global Secure Fault */
				<0 129 4>, /* Global Non-secure Fault */
				/* Non-secure Context Interrupts (32) */
				<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
				<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
				<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
				<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
				<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
				<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
				<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
				<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
			stream-match-mask = <0x7ff0>;
			status = "disabled";
		};

		spi0: spi@ffda4000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xffda4000 0x1000>;
			interrupts = <0 99 4>;
			resets = <&rst SPIM0_RESET>;
			reset-names = "spi";
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
			status = "disabled";
		};

		spi1: spi@ffda5000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xffda5000 0x1000>;
			interrupts = <0 100 4>;
			resets = <&rst SPIM1_RESET>;
			reset-names = "spi";
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
			status = "disabled";
		};

		sysmgr: sysmgr@ffd12000 {
			compatible = "altr,sys-mgr-s10","altr,sys-mgr";
			reg = <0xffd12000 0x228>;
		};

		timer0: timer0@ffc03000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 113 4>;
			reg = <0xffc03000 0x100>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer1: timer1@ffc03100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 114 4>;
			reg = <0xffc03100 0x100>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer2: timer2@ffd00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 115 4>;
			reg = <0xffd00000 0x100>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer3: timer3@ffd00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 116 4>;
			reg = <0xffd00100 0x100>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			clock-names = "timer";
		};

		uart0: serial@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x100>;
			interrupts = <0 108 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART0_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		uart1: serial@ffc02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02100 0x100>;
			interrupts = <0 109 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART1_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		usbphy0: usbphy@0 {
			#phy-cells = <0>;
			compatible = "usb-nop-xceiv";
			status = "okay";
		};

		usb0: usb@ffb00000 {
			compatible = "snps,dwc2";
			reg = <0xffb00000 0x40000>;
			interrupts = <0 93 4>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
			reset-names = "dwc2", "dwc2-ecc";
			clocks = <&clkmgr STRATIX10_USB_CLK>;
			clock-names = "otg";
			iommus = <&smmu 6>;
			status = "disabled";
		};

		usb1: usb@ffb40000 {
			compatible = "snps,dwc2";
			reg = <0xffb40000 0x40000>;
			interrupts = <0 94 4>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
			reset-names = "dwc2", "dwc2-ecc";
			clocks = <&clkmgr STRATIX10_USB_CLK>;
			iommus = <&smmu 7>;
			status = "disabled";
		};

		watchdog0: watchdog@ffd00200 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00200 0x100>;
			interrupts = <0 117 4>;
			resets = <&rst WATCHDOG0_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog1: watchdog@ffd00300 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00300 0x100>;
			interrupts = <0 118 4>;
			resets = <&rst WATCHDOG1_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog2: watchdog@ffd00400 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00400 0x100>;
			interrupts = <0 125 4>;
			resets = <&rst WATCHDOG2_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog3: watchdog@ffd00500 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00500 0x100>;
			interrupts = <0 126 4>;
			resets = <&rst WATCHDOG3_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		sdr: sdr@f8011100 {
			compatible = "altr,sdr-ctl", "syscon";
			reg = <0xf8011100 0xc0>;
		};

		eccmgr {
			compatible = "altr,socfpga-s10-ecc-manager",
				     "altr,socfpga-a10-ecc-manager";
			altr,sysmgr-syscon = <&sysmgr>;
			#address-cells = <1>;
			#size-cells = <1>;
			interrupts = <0 15 4>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ranges;

			sdramedac {
				compatible = "altr,sdram-edac-s10";
				altr,sdr-syscon = <&sdr>;
				interrupts = <16 4>;
			};

			ocram-ecc@ff8cc000 {
				compatible = "altr,socfpga-s10-ocram-ecc",
					     "altr,socfpga-a10-ocram-ecc";
				reg = <0xff8cc000 0x100>;
				altr,ecc-parent = <&ocram>;
				interrupts = <1 4>;
			};

			usb0-ecc@ff8c4000 {
				compatible = "altr,socfpga-s10-usb-ecc",
					     "altr,socfpga-usb-ecc";
				reg = <0xff8c4000 0x100>;
				altr,ecc-parent = <&usb0>;
				interrupts = <2 4>;
			};

			emac0-rx-ecc@ff8c0000 {
				compatible = "altr,socfpga-s10-eth-mac-ecc",
					     "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0000 0x100>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <4 4>;
			};

			emac0-tx-ecc@ff8c0400 {
				compatible = "altr,socfpga-s10-eth-mac-ecc",
					     "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0400 0x100>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <5 4>;
			};

		};

		qspi: spi@ff8d2000 {
			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xff8d2000 0x100>,
			      <0xff900000 0x100000>;
			interrupts = <0 3 4>;
			cdns,fifo-depth = <128>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x00000000>;
			clocks = <&qspi_clk>;

			status = "disabled";
		};

		firmware {
			svc {
				compatible = "intel,stratix10-svc";
				method = "smc";
				memory-region = <&service_reserved>;

				fpga_mgr: fpga-mgr {
					compatible = "intel,stratix10-soc-fpga-mgr";
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright Altera Corporation (C) 2015. All rights reserved.
 */

#include "socfpga_stratix10.dtsi"

/ {
	model = "SoCFPGA Stratix 10 SoCDK";
	compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";

	aliases {
		serial0 = &uart0;
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		ethernet2 = &gmac2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	leds {
		compatible = "gpio-leds";
		led-hps0 {
			label = "hps_led0";
			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
		};

		led-hps1 {
			label = "hps_led1";
			gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
		};

		led-hps2 {
			label = "hps_led2";
			gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
		};
	};

	memory {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0 0 0>;
	};

	ref_033v: regulator-v-ref {
		compatible = "regulator-fixed";
		regulator-name = "0.33V";
		regulator-min-microvolt = <330000>;
		regulator-max-microvolt = <330000>;
	};

	soc {
		eccmgr {
			sdmmca-ecc@ff8c8c00 {
				compatible = "altr,socfpga-s10-sdmmc-ecc",
					     "altr,socfpga-sdmmc-ecc";
				reg = <0xff8c8c00 0x100>;
				altr,ecc-parent = <&mmc>;
				interrupts = <14 4>,
					     <15 4>;
			};
		};
	};
};

&gpio1 {
	status = "okay";
};

&gmac0 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&phy0>;

	max-frame-size = <9000>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@0 {
			reg = <4>;

			txd0-skew-ps = <0>; /* -420ps */
			txd1-skew-ps = <0>; /* -420ps */
			txd2-skew-ps = <0>; /* -420ps */
			txd3-skew-ps = <0>; /* -420ps */
			rxd0-skew-ps = <420>; /* 0ps */
			rxd1-skew-ps = <420>; /* 0ps */
			rxd2-skew-ps = <420>; /* 0ps */
			rxd3-skew-ps = <420>; /* 0ps */
			txen-skew-ps = <0>; /* -420ps */
			txc-skew-ps = <900>; /* 0ps */
			rxdv-skew-ps = <420>; /* 0ps */
			rxc-skew-ps = <1680>; /* 780ps */
		};
	};
};

&mmc {
	status = "okay";
	cap-sd-highspeed;
	cap-mmc-highspeed;
	broken-cd;
	bus-width = <4>;
	clk-phase-sd-hs = <0>, <135>;
};

&osc1 {
	clock-frequency = <25000000>;
};

&uart0 {
	status = "okay";
};

&usb0 {
	status = "okay";
	disable-over-current;
};

&watchdog0 {
	status = "okay";
};

&i2c1 {
	status = "okay";
	clock-frequency = <100000>;
	i2c-sda-falling-time-ns = <890>;  /* hcnt */
	i2c-sdl-falling-time-ns = <890>;  /* lcnt */

	adc@14 {
		compatible = "lltc,ltc2497";
		reg = <0x14>;
		vref-supply = <&ref_033v>;
	};

	temp@4c {
		compatible = "maxim,max1619";
		reg = <0x4c>;
	};

	eeprom@51 {
		compatible = "atmel,24c32";
		reg = <0x51>;
		pagesize = <32>;
	};

	rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
	};
};

&qspi {
	status = "okay";
	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,mt25qu02g", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <100000000>;

		m25p,fast-read;
		cdns,page-size = <256>;
		cdns,block-size = <16>;
		cdns,read-delay = <1>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			qspi_boot: partition@0 {
				label = "Boot and fpga data";
				reg = <0x0 0x03FE0000>;
			};

			qspi_rootfs: partition@3FE0000 {
				label = "Root Filesystem - JFFS2";
				reg = <0x03FE0000 0x0C020000>;
			};
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright Altera Corporation (C) 2015. All rights reserved.
 */

#include "socfpga_stratix10.dtsi"

/ {
	model = "SoCFPGA Stratix 10 SoCDK";
	compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";

	aliases {
		serial0 = &uart0;
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		ethernet2 = &gmac2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	leds {
		compatible = "gpio-leds";
		led-hps0 {
			label = "hps_led0";
			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
		};

		led-hps1 {
			label = "hps_led1";
			gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
		};

		led-hps2 {
			label = "hps_led2";
			gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
		};
	};

	memory {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0 0 0>;
	};

	ref_033v: regulator-v-ref {
		compatible = "regulator-fixed";
		regulator-name = "0.33V";
		regulator-min-microvolt = <330000>;
		regulator-max-microvolt = <330000>;
	};

	soc {
		eccmgr {
			sdmmca-ecc@ff8c8c00 {
				compatible = "altr,socfpga-s10-sdmmc-ecc",
					     "altr,socfpga-sdmmc-ecc";
				reg = <0xff8c8c00 0x100>;
				altr,ecc-parent = <&mmc>;
				interrupts = <14 4>,
					     <15 4>;
			};
		};
	};
};

&gpio1 {
	status = "okay";
};

&gmac2 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&phy0>;

	max-frame-size = <9000>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@0 {
			reg = <4>;

			txd0-skew-ps = <0>; /* -420ps */
			txd1-skew-ps = <0>; /* -420ps */
			txd2-skew-ps = <0>; /* -420ps */
			txd3-skew-ps = <0>; /* -420ps */
			rxd0-skew-ps = <420>; /* 0ps */
			rxd1-skew-ps = <420>; /* 0ps */
			rxd2-skew-ps = <420>; /* 0ps */
			rxd3-skew-ps = <420>; /* 0ps */
			txen-skew-ps = <0>; /* -420ps */
			txc-skew-ps = <900>; /* 0ps */
			rxdv-skew-ps = <420>; /* 0ps */
			rxc-skew-ps = <1680>; /* 780ps */
		};
	};
};

&nand {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		nand-bus-width = <16>;

		partition@0 {
			label = "u-boot";
			reg = <0 0x200000>;
		};

		partition@200000 {
			label = "root";
			reg = <0x200000 0x3fe00000>;
		};
	};
};

&osc1 {
	clock-frequency = <25000000>;
};

&uart0 {
	status = "okay";
};

&usb0 {
	status = "okay";
	disable-over-current;
};

&watchdog0 {
	status = "okay";
};

&i2c2 {
	status = "okay";
	clock-frequency = <100000>;
	i2c-sda-falling-time-ns = <890>;  /* hcnt */
	i2c-sdl-falling-time-ns = <890>;  /* lcnt */

	adc@14 {
		compatible = "lltc,ltc2497";
		reg = <0x14>;
		vref-supply = <&ref_033v>;
	};

	temp@4c {
		compatible = "maxim,max1619";
		reg = <0x4c>;
	};

	eeprom@51 {
		compatible = "atmel,24c32";
		reg = <0x51>;
		pagesize = <32>;
	};

	rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
	};
};

&qspi {
	status = "okay";
	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,mt25qu02g", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <100000000>;

		m25p,fast-read;
		cdns,page-size = <256>;
		cdns,block-size = <16>;
		cdns,read-delay = <1>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			qspi_boot: partition@0 {
				label = "Boot and fpga data";
				reg = <0x0 0x03FE0000>;
			};

			qspi_rootfs: partition@3FE0000 {
				label = "Root Filesystem - JFFS2";
				reg = <0x03FE0000 0x0C020000>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022, Intel Corporation
 */

#include "socfpga_stratix10.dtsi"

/ {
	model = "SOCFPGA Stratix 10 SWVP";
	compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;

		timer0 = &timer0;
		timer1 = &timer1;
		timer2 = &timer2;
		timer3 = &timer3;

		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		ethernet2 = &gmac2;
	};

	chosen {
		stdout-path = "serial1:115200n8";
		linux,initrd-start = <0x10000000>;
		linux,initrd-end = <0x125c8324>;
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};
};

&cpu0 {
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x0000fff8>;
};

&cpu1 {
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x0000fff8>;
};

&cpu2 {
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x0000fff8>;
};

&cpu3 {
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x0000fff8>;
};

&osc1 {
	clock-frequency = <25000000>;
};

&gmac0 {
	status = "okay";
	phy-mode = "rgmii";
	phy-addr = <0xffffffff>;
	snps,max-mtu = <0x0>;
};

&gmac1 {
	status = "okay";
	phy-mode = "rgmii";
	phy-addr = <0xffffffff>;
};

&gmac2 {
	status = "okay";
	phy-mode = "rgmii";
	phy-addr = <0xffffffff>;
};

&mmc {
	status = "okay";
	altr,dw-mshc-ciu-div = <0x3>;
	altr,dw-mshc-sdr-timing = <0x0 0x3>;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	broken-cd;
	bus-width = <4>;
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&usb0 {
	clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
	status = "okay";
};

&usb1 {
	clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
	status = "okay";
};

&rst {
	altr,modrst-offset = <0x20>;
};

&sysmgr {
	reg = <0xffd12000 0x1000>;
	interrupts = <0x0 0x10 0x4>;
	cpu1-start-addr = <0xffd06230>;
};


code:
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_ALPINE)	+= alpine-v2-evp.dtb
dtb-$(CONFIG_ARCH_ALPINE)	+= alpine-v3-evp.dtb


code:
/*
 * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * Antoine Tenart <antoine.tenart@free-electrons.com>
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include "alpine-v2.dtsi"

/ {
	model = "Annapurna Labs Alpine v2 EVP";
	compatible = "al,alpine-v2-evp", "al,alpine-v2";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&uart0 { status = "okay"; };


code:
/*
 * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 *
 * Antoine Tenart <antoine.tenart@free-electrons.com>
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Annapurna Labs Alpine v2";
	compatible = "al,alpine-v2";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a57";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu@1 {
			compatible = "arm,cortex-a57";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu@2 {
			compatible = "arm,cortex-a57";
			device_type = "cpu";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu@3 {
			compatible = "arm,cortex-a57";
			device_type = "cpu";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-0.2", "arm,psci";
		method = "smc";
		cpu_suspend = <0x84000001>;
		cpu_off = <0x84000002>;
		cpu_on = <0x84000003>;
	};

	sbclk: sbclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <1000000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;

		interrupt-parent = <&gic>;
		ranges;

		timer {
			compatible = "arm,armv8-timer";
			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
		};

		pmu {
			compatible = "arm,armv8-pmuv3";
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		};

		gic: interrupt-controller@f0200000 {
			compatible = "arm,gic-v3";
			reg = <0x0 0xf0200000 0x0 0x10000>,	/* GIC Dist */
			      <0x0 0xf0280000 0x0 0x200000>,	/* GICR */
			      <0x0 0xf0100000 0x0 0x2000>,	/* GICC */
			      <0x0 0xf0110000 0x0 0x2000>,	/* GICV */
			      <0x0 0xf0120000 0x0 0x2000>;	/* GICH */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		pci@fbc00000 {
			compatible = "pci-host-ecam-generic";
			device_type = "pci";
			#size-cells = <2>;
			#address-cells = <3>;
			#interrupt-cells = <1>;
			reg = <0x0 0xfbc00000 0x0 0x100000>;
			interrupt-map-mask = <0xf800 0 0 7>;
			/* add legacy interrupts for SATA only */
			interrupt-map = <0x4000 0 0 1 &gic 0 53 4>,
					<0x4800 0 0 1 &gic 0 54 4>;
			/* 32 bit non prefetchable memory space */
			ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
			bus-range = <0x00 0x00>;
			msi-parent = <&msix>;
		};

		msix: msix@fbe00000 {
			compatible = "al,alpine-msix";
			reg = <0x0 0xfbe00000 0x0 0x100000>;
			interrupt-controller;
			msi-controller;
			al,msi-base-spi = <160>;
			al,msi-num-spis = <160>;
		};

		io-fabric {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0xfc000000 0x2000000>;

			uart0: serial@1883000 {
				compatible = "ns16550a";
				device_type = "serial";
				reg = <0x1883000 0x1000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clock-frequency = <500000000>;
				reg-shift = <2>;
				reg-io-width = <4>;
				status = "disabled";
			};

			uart1: serial@1884000 {
				compatible = "ns16550a";
				device_type = "serial";
				reg = <0x1884000 0x1000>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clock-frequency = <500000000>;
				reg-shift = <2>;
				reg-io-width = <4>;
				status = "disabled";
			};

			uart2: serial@1885000 {
				compatible = "ns16550a";
				device_type = "serial";
				reg = <0x1885000 0x1000>;
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
				clock-frequency = <500000000>;
				reg-shift = <2>;
				reg-io-width = <4>;
				status = "disabled";
			};

			uart3: serial@1886000 {
				compatible = "ns16550a";
				device_type = "serial";
				reg = <0x1886000 0x1000>;
				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				clock-frequency = <500000000>;
				reg-shift = <2>;
				reg-io-width = <4>;
				status = "disabled";
			};

			timer0: timer@1890000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x1890000 0x1000>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&sbclk>;
			};

			timer1: timer@1891000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x1891000 0x1000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&sbclk>;
				status = "disabled";
			};

			timer2: timer@1892000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x1892000 0x1000>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&sbclk>;
				status = "disabled";
			};

			timer3: timer@1893000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x1893000 0x1000>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&sbclk>;
				status = "disabled";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 */

#include "alpine-v3.dtsi"

/ {
	model = "Amazon's Annapurna Labs Alpine v3 Evaluation Platform (EVP)";
	compatible = "amazon,al-alpine-v3-evp", "amazon,al-alpine-v3";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&uart0 { status = "okay"; };


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Amazon's Annapurna Labs Alpine v3";
	compatible = "amazon,al-alpine-v3";

	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster0_l2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x1>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster0_l2>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x2>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster0_l2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x3>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster0_l2>;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x100>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster1_l2>;
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x101>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster1_l2>;
		};

		cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x102>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster1_l2>;
		};

		cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x103>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster1_l2>;
		};

		cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x200>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster2_l2>;
		};

		cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x201>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster2_l2>;
		};

		cpu@202 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x202>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster2_l2>;
		};

		cpu@203 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x203>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster2_l2>;
		};

		cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x300>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster3_l2>;
		};

		cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x301>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster3_l2>;
		};

		cpu@302 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x302>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster3_l2>;
		};

		cpu@303 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x303>;
			enable-method = "psci";
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			next-level-cache = <&cluster3_l2>;
		};

		cluster0_l2: cache@0 {
			compatible = "cache";
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
			cache-level = <2>;
		};

		cluster1_l2: cache@100 {
			compatible = "cache";
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
			cache-level = <2>;
		};

		cluster2_l2: cache@200 {
			compatible = "cache";
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
			cache-level = <2>;
		};

		cluster3_l2: cache@300 {
			compatible = "cache";
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
			cache-level = <2>;
		};

	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secmon@0 {
			reg = <0x0 0x0 0x0 0x100000>;
			no-map;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	pmu {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@f0000000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x0 0xf0800000 0 0x10000>,	/* GICD */
			      <0x0 0xf0a00000 0 0x200000>,	/* GICR */
			      <0x0 0xf0000000 0 0x2000>,	/* GICC */
			      <0x0 0xf0010000 0 0x1000>,	/* GICH */
			      <0x0 0xf0020000 0 0x2000>;	/* GICV */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		pcie@fbd00000 {
			compatible = "pci-host-ecam-generic";
			device_type = "pci";
			#size-cells = <2>;
			#address-cells = <3>;
			#interrupt-cells = <1>;
			reg = <0x0 0xfbd00000 0x0 0x100000>;
			interrupt-map-mask = <0xf800 0 0 7>;
			/* 8 x legacy interrupts for SATA only */
			interrupt-map = <0x4000 0 0 1 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
					<0x4800 0 0 1 &gic 0 58 IRQ_TYPE_LEVEL_HIGH>,
					<0x5000 0 0 1 &gic 0 59 IRQ_TYPE_LEVEL_HIGH>,
					<0x5800 0 0 1 &gic 0 60 IRQ_TYPE_LEVEL_HIGH>,
					<0x6000 0 0 1 &gic 0 61 IRQ_TYPE_LEVEL_HIGH>,
					<0x6800 0 0 1 &gic 0 62 IRQ_TYPE_LEVEL_HIGH>,
					<0x7000 0 0 1 &gic 0 63 IRQ_TYPE_LEVEL_HIGH>,
					<0x7800 0 0 1 &gic 0 64 IRQ_TYPE_LEVEL_HIGH>;
			ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
			bus-range = <0x00 0x00>;
			msi-parent = <&msix>;
		};

		msix: msix@fbe00000 {
			compatible = "al,alpine-msix";
			reg = <0x0 0xfbe00000 0x0 0x100000>;
			interrupt-controller;
			msi-controller;
			al,msi-base-spi = <336>;
			al,msi-num-spis = <959>;
			interrupt-parent = <&gic>;
		};

		io-fabric {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0xfc000000 0x2000000>;

			uart0: serial@1883000 {
				compatible = "ns16550a";
				reg = <0x1883000 0x1000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clock-frequency = <0>; /* Filled by firmware */
				reg-shift = <2>;
				reg-io-width = <4>;
				status = "disabled";
			};

			uart1: serial@1884000 {
				compatible = "ns16550a";
				reg = <0x1884000 0x1000>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clock-frequency = <0>; /* Filled by firmware */
				reg-shift = <2>;
				reg-io-width = <4>;
				status = "disabled";
			};

			uart2: serial@1885000 {
				compatible = "ns16550a";
				reg = <0x1885000 0x1000>;
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
				clock-frequency = <0>; /* Filled by firmware */
				reg-shift = <2>;
				reg-io-width = <4>;
				status = "disabled";
			};

			uart3: serial@1886000 {
				compatible = "ns16550a";
				reg = <0x1886000 0x1000>;
				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				clock-frequency = <0>; /* Filled by firmware */
				reg-shift = <2>;
				reg-io-width = <4>;
				status = "disabled";
			};
		};
	};
};


code:
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * DTS file for AMD Seattle Overdrive Development Board
 * Note: For Seattle Rev.B0
 *
 * Copyright (C) 2015 Advanced Micro Devices, Inc.
 */

/dts-v1/;

/include/ "amd-seattle-soc.dtsi"
/include/ "amd-seattle-cpus.dtsi"

/ {
	model = "AMD Seattle (Rev.B0) Development Board (Overdrive)";
	compatible = "amd,seattle-overdrive", "amd,seattle";

	chosen {
		stdout-path = &serial0;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};
};

&ccp0 {
	status = "ok";
	amd,zlib-support = <1>;
};

/**
 * NOTE: In Rev.B, gpio0 is reserved.
 */
&gpio1 {
	status = "ok";
};

&gpio4 {
	status = "ok";
};

&i2c0 {
	status = "ok";
};

&i2c1 {
	status = "ok";
};

&pcie0 {
	status = "ok";
};

&spi0 {
	status = "ok";
};

&spi1 {
	status = "ok";
	sdcard0: sdcard@0 {
		compatible = "mmc-spi-slot";
		reg = <0>;
		spi-max-frequency = <20000000>;
		voltage-ranges = <3200 3400>;
		pl022,hierarchy = <0>;
		pl022,interface = <0>;
		pl022,com-mode = <0x0>;
		pl022,rx-level-trig = <0>;
		pl022,tx-level-trig = <0>;
	};
};

&smb0 {
	/include/ "amd-seattle-xgbe-b.dtsi"
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * DTS file for AMD Seattle Overdrive Development Board
 * Note: For Seattle Rev.B1
 *
 * Copyright (C) 2015 Advanced Micro Devices, Inc.
 */

/dts-v1/;

/include/ "amd-seattle-soc.dtsi"
/include/ "amd-seattle-cpus.dtsi"

/ {
	model = "AMD Seattle (Rev.B1) Development Board (Overdrive)";
	compatible = "amd,seattle-overdrive", "amd,seattle";

	chosen {
		stdout-path = &serial0;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};
};

&ccp0 {
	status = "ok";
	amd,zlib-support = <1>;
};

/**
 * NOTE: In Rev.B, gpio0 is reserved.
 */
&gpio1 {
	status = "ok";
};

&gpio2 {
	status = "ok";
};

&gpio3 {
	status = "ok";
};

&gpio4 {
	status = "ok";
};

&i2c0 {
	status = "ok";
};

&i2c1 {
	status = "ok";
};

&pcie0 {
	status = "ok";
};

&sata1 {
	status = "ok";
};

&spi0 {
	status = "ok";
};

&spi1 {
	status = "ok";
	sdcard0: sdcard@0 {
		compatible = "mmc-spi-slot";
		reg = <0>;
		spi-max-frequency = <20000000>;
		voltage-ranges = <3200 3400>;
		pl022,hierarchy = <0>;
		pl022,interface = <0>;
		pl022,com-mode = <0x0>;
		pl022,rx-level-trig = <0>;
		pl022,tx-level-trig = <0>;
	};
};

&ipmi_kcs {
	status = "ok";
};

&smb0 {
	/include/ "amd-seattle-xgbe-b.dtsi"
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * DTS file for AMD Seattle Clocks
 *
 * Copyright (C) 2014 Advanced Micro Devices, Inc.
 */

	adl3clk_100mhz: clk100mhz_0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "adl3clk_100mhz";
	};

	ccpclk_375mhz: clk375mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <375000000>;
		clock-output-names = "ccpclk_375mhz";
	};

	sataclk_333mhz: clk333mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <333000000>;
		clock-output-names = "sataclk_333mhz";
	};

	pcieclk_500mhz: clk500mhz_0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <500000000>;
		clock-output-names = "pcieclk_500mhz";
	};

	dmaclk_500mhz: clk500mhz_1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <500000000>;
		clock-output-names = "dmaclk_500mhz";
	};

	miscclk_250mhz: clk250mhz_4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <250000000>;
		clock-output-names = "miscclk_250mhz";
	};

	uartspiclk_100mhz: clk100mhz_1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "uartspiclk_100mhz";
	};


code:
// SPDX-License-Identifier: GPL-2.0

/ {
	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
				core1 {
					cpu = <&CPU1>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&CPU2>;
				};
				core1 {
					cpu = <&CPU3>;
				};
			};
			cluster2 {
				core0 {
					cpu = <&CPU4>;
				};
				core1 {
					cpu = <&CPU5>;
				};
			};
			cluster3 {
				core0 {
					cpu = <&CPU6>;
				};
				core1 {
					cpu = <&CPU7>;
				};
			};
		};

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_0>;

		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x1>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_0>;
		};

		CPU2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x100>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_1>;
		};

		CPU3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x101>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_1>;
		};

		CPU4: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x200>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_2>;
		};

		CPU5: cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x201>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_2>;
		};

		CPU6: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x300>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_3>;
		};

		CPU7: cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x301>;
			enable-method = "psci";

			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			l2-cache = <&L2_3>;
		};
	};

	L2_0: l2-cache0 {
		cache-size = <0x100000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-unified;
		next-level-cache = <&L3>;
	};

	L2_1: l2-cache1 {
		cache-size = <0x100000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-unified;
		next-level-cache = <&L3>;
	};

	L2_2: l2-cache2 {
		cache-size = <0x100000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-unified;
		next-level-cache = <&L3>;
	};

	L2_3: l2-cache3 {
		cache-size = <0x100000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-unified;
		next-level-cache = <&L3>;
	};

	L3: l3-cache {
		cache-level = <3>;
		cache-size = <0x800000>;
		cache-line-size = <64>;
		cache-sets = <8192>;
		cache-unified;
	};

	pmu {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <0x0 0x7 0x4>,
			     <0x0 0x8 0x4>,
			     <0x0 0x9 0x4>,
			     <0x0 0xa 0x4>,
			     <0x0 0xb 0x4>,
			     <0x0 0xc 0x4>,
			     <0x0 0xd 0x4>,
			     <0x0 0xe 0x4>;
		interrupt-affinity = <&CPU0>,
				     <&CPU1>,
				     <&CPU2>,
				     <&CPU3>,
				     <&CPU4>,
				     <&CPU5>,
				     <&CPU6>,
				     <&CPU7>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * DTS file for AMD Seattle SoC
 *
 * Copyright (C) 2014 Advanced Micro Devices, Inc.
 */

/ {
	compatible = "amd,seattle";
	interrupt-parent = <&gic0>;
	#address-cells = <2>;
	#size-cells = <2>;

	gic0: interrupt-controller@e1101000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		reg = <0x0 0xe1110000 0 0x1000>,
		      <0x0 0xe112f000 0 0x2000>,
		      <0x0 0xe1140000 0 0x2000>,
		      <0x0 0xe1160000 0 0x2000>;
		interrupts = <1 9 0xf04>;
		ranges = <0 0 0 0xe1100000 0 0x100000>;
		v2m0: v2m@e0080000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0x00080000 0 0x1000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 0xff04>,
			     <1 14 0xff04>,
			     <1 11 0xff04>,
			     <1 10 0xff04>;
	};

	smb0: smb {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * dma-ranges is 40-bit address space containing:
		 * - GICv2m MSI register is at 0xe0080000
		 * - DRAM range [0x8000000000 to 0xffffffffff]
		 */
		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;

		/include/ "amd-seattle-clks.dtsi"

		sata0: sata@e0300000 {
			compatible = "snps,dwc-ahci";
			reg = <0 0xe0300000 0 0xf0000>;
			interrupts = <0 355 4>;
			clocks = <&sataclk_333mhz>;
			iommus = <&sata0_smmu 0x0 0x1f>;
			dma-coherent;
		};

		/* This is for Rev B only */
		sata1: sata@e0d00000 {
			status = "disabled";
			compatible = "snps,dwc-ahci";
			reg = <0 0xe0d00000 0 0xf0000>;
			interrupts = <0 354 4>;
			clocks = <&sataclk_333mhz>;
			iommus = <&sata1_smmu 0x0e>,
				 <&sata1_smmu 0x0f>,
				 <&sata1_smmu 0x1e>;
			dma-coherent;
		};

		sata0_smmu: iommu@e0200000 {
			compatible = "arm,mmu-401";
			reg = <0 0xe0200000 0 0x10000>;
			#global-interrupts = <1>;
			interrupts = <0 332 4>, <0 332 4>;
			#iommu-cells = <2>;
			dma-coherent;
		};

		sata1_smmu: iommu@e0c00000 {
			compatible = "arm,mmu-401";
			reg = <0 0xe0c00000 0 0x10000>;
			#global-interrupts = <1>;
			interrupts = <0 331 4>, <0 331 4>;
			#iommu-cells = <1>;
			dma-coherent;
		};

		i2c0: i2c@e1000000 {
			status = "disabled";
			compatible = "snps,designware-i2c";
			reg = <0 0xe1000000 0 0x1000>;
			interrupts = <0 357 4>;
			clocks = <&miscclk_250mhz>;
		};

		i2c1: i2c@e0050000 {
			status = "disabled";
			compatible = "snps,designware-i2c";
			reg = <0 0xe0050000 0 0x1000>;
			interrupts = <0 340 4>;
			clocks = <&miscclk_250mhz>;
		};

		serial0: serial@e1010000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0 0xe1010000 0 0x1000>;
			interrupts = <0 328 4>;
			clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
			clock-names = "uartclk", "apb_pclk";
		};

		spi0: spi@e1020000 {
			status = "disabled";
			compatible = "arm,pl022", "arm,primecell";
			reg = <0 0xe1020000 0 0x1000>;
			spi-controller;
			interrupts = <0 330 4>;
			clocks = <&uartspiclk_100mhz>;
			clock-names = "apb_pclk";
		};

		spi1: spi@e1030000 {
			status = "disabled";
			compatible = "arm,pl022", "arm,primecell";
			reg = <0 0xe1030000 0 0x1000>;
			spi-controller;
			interrupts = <0 329 4>;
			clocks = <&uartspiclk_100mhz>;
			clock-names = "apb_pclk";
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gpio0: gpio@e1040000 { /* Not available to OS for B0 */
			status = "disabled";
			compatible = "arm,pl061", "arm,primecell";
			#gpio-cells = <2>;
			reg = <0 0xe1040000 0 0x1000>;
			gpio-controller;
			interrupts = <0 359 4>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&miscclk_250mhz>;
			clock-names = "apb_pclk";
		};

		gpio1: gpio@e1050000 { /* [0:7] */
			status = "disabled";
			compatible = "arm,pl061", "arm,primecell";
			#gpio-cells = <2>;
			reg = <0 0xe1050000 0 0x1000>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 358 4>;
			clocks = <&miscclk_250mhz>;
			clock-names = "apb_pclk";
		};

		gpio2: gpio@e0020000 { /* [8:15] */
			status = "disabled";
			compatible = "arm,pl061", "arm,primecell";
			#gpio-cells = <2>;
			reg = <0 0xe0020000 0 0x1000>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 366 4>;
			clocks = <&miscclk_250mhz>;
			clock-names = "apb_pclk";
		};

		gpio3: gpio@e0030000 { /* [16:23] */
			status = "disabled";
			compatible = "arm,pl061", "arm,primecell";
			#gpio-cells = <2>;
			reg = <0 0xe0030000 0 0x1000>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 365 4>;
			clocks = <&miscclk_250mhz>;
			clock-names = "apb_pclk";
		};

		gpio4: gpio@e0080000 { /* [24] */
			status = "disabled";
			compatible = "arm,pl061", "arm,primecell";
			#gpio-cells = <2>;
			reg = <0 0xe0080000 0 0x1000>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 361 4>;
			clocks = <&miscclk_250mhz>;
			clock-names = "apb_pclk";
		};

		ccp0: ccp@e0100000 {
			status = "disabled";
			compatible = "amd,ccp-seattle-v1a";
			reg = <0 0xe0100000 0 0x10000>;
			interrupts = <0 3 4>;
			dma-coherent;
			iommus = <&sata1_smmu 0x00>,
				 <&sata1_smmu 0x02>,
				 <&sata1_smmu 0x40>,
				 <&sata1_smmu 0x42>;
		};

		pcie0: pcie@f0000000 {
			compatible = "pci-host-ecam-generic";
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			bus-range = <0 0x7f>;
			msi-parent = <&v2m0>;
			reg = <0 0xf0000000 0 0x10000000>;

			interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
			interrupt-map =
				<0x1100 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
				<0x1100 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
				<0x1100 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
				<0x1100 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>,

				<0x1200 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x124 0x1>,
				<0x1200 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x125 0x1>,
				<0x1200 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x126 0x1>,
				<0x1200 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x127 0x1>,

				<0x1300 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x128 0x1>,
				<0x1300 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x129 0x1>,
				<0x1300 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x12a 0x1>,
				<0x1300 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x12b 0x1>;

			dma-coherent;
			dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
			ranges =
				/* I/O Memory (size=64K) */
				<0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
				/* 32-bit MMIO (size=2G) */
				<0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
				/* 64-bit MMIO (size= 508G) */
				<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
			iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
		};

		pcie_smmu: iommu@e0a00000 {
			compatible = "arm,mmu-401";
			reg = <0 0xe0a00000 0 0x10000>;
			#global-interrupts = <1>;
			interrupts = <0 333 4>, <0 333 4>;
			#iommu-cells = <1>;
			dma-coherent;
		};

		/* Perf CCN504 PMU */
		ccn: ccn@e8000000 {
			compatible = "arm,ccn-504";
			reg = <0x0 0xe8000000 0 0x1000000>;
			interrupts = <0 380 4>;
		};

		ipmi_kcs: kcs@e0010000 {
			status = "disabled";
			compatible = "ipmi-kcs";
			device_type = "ipmi";
			reg = <0x0 0xe0010000 0 0x8>;
			interrupts = <0 389 4>;
			reg-size = <1>;
			reg-spacing = <4>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * DTS file for AMD Seattle XGBE (RevB)
 *
 * Copyright (C) 2015 Advanced Micro Devices, Inc.
 */

	xgmacclk0_dma_250mhz: clk250mhz_0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <250000000>;
		clock-output-names = "xgmacclk0_dma_250mhz";
	};

	xgmacclk0_ptp_250mhz: clk250mhz_1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <250000000>;
		clock-output-names = "xgmacclk0_ptp_250mhz";
	};

	xgmacclk1_dma_250mhz: clk250mhz_2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <250000000>;
		clock-output-names = "xgmacclk1_dma_250mhz";
	};

	xgmacclk1_ptp_250mhz: clk250mhz_3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <250000000>;
		clock-output-names = "xgmacclk1_ptp_250mhz";
	};

	xgmac0: xgmac@e0700000 {
		compatible = "amd,xgbe-seattle-v1a";
		reg = <0 0xe0700000 0 0x80000>,
		      <0 0xe0780000 0 0x80000>,
		      <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
		      <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
		      <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
		interrupts = <0 325 4>,
			     <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>,
			     <0 323 4>;
		amd,per-channel-interrupt;
		amd,speed-set = <0>;
		amd,serdes-blwc = <1>, <1>, <0>;
		amd,serdes-cdr-rate = <2>, <2>, <7>;
		amd,serdes-pq-skew = <10>, <10>, <18>;
		amd,serdes-tx-amp = <0>, <0>, <0>;
		amd,serdes-dfe-tap-config = <3>, <3>, <3>;
		amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
		mac-address = [ 02 A1 A2 A3 A4 A5 ];
		clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
		clock-names = "dma_clk", "ptp_clk";
		phy-mode = "xgmii";
		iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */
		dma-coherent;
	};

	xgmac1: xgmac@e0900000 {
		compatible = "amd,xgbe-seattle-v1a";
		reg = <0 0xe0900000 0 0x80000>,
		      <0 0xe0980000 0 0x80000>,
		      <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
		      <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */
		      <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */
		interrupts = <0 324 4>,
			     <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>,
			     <0 322 4>;
		amd,per-channel-interrupt;
		amd,speed-set = <0>;
		amd,serdes-blwc = <1>, <1>, <0>;
		amd,serdes-cdr-rate = <2>, <2>, <7>;
		amd,serdes-pq-skew = <10>, <10>, <18>;
		amd,serdes-tx-amp = <0>, <0>, <0>;
		amd,serdes-dfe-tap-config = <3>, <3>, <3>;
		amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
		mac-address = [ 02 B1 B2 B3 B4 B5 ];
		clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
		clock-names = "dma_clk", "ptp_clk";
		phy-mode = "xgmii";
		iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */
		dma-coherent;
	};

	xgmac0_smmu: iommu@e0600000 {
		 compatible = "arm,mmu-401";
		 reg = <0 0xe0600000 0 0x10000>;
		 #global-interrupts = <1>;
		 interrupts = /* Uses combined intr for both
			       * global and context
			       */
			      <0 336 4>,
			      <0 336 4>;
		#iommu-cells = <2>;
		dma-coherent;
	 };

	 xgmac1_smmu: iommu@e0800000 {
		 compatible = "arm,mmu-401";
		 reg = <0 0xe0800000 0 0x10000>;
		 #global-interrupts = <1>;
		 interrupts = /* Uses combined intr for both
			       * global and context
			       */
			      <0 335 4>,
			      <0 335 4>;
		#iommu-cells = <2>;
		dma-coherent;
	 };


code:
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-3.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12a-radxa-zero.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-go-ultra.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-libretech-ac.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-kii-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-vero4k-plus.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-jethome-jethub-j80.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-gt1-ultimate.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-minix-neo-u9h.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air-gbit.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-h96-max.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air-gbit.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

/dts-v1/;

#include "meson-a1.dtsi"

/ {
	compatible = "amlogic,ad401", "amlogic,a1";
	model = "Amlogic Meson A1 AD401 Development Board";

	aliases {
		serial0 = &uart_AO_B;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x8000000>;
	};
};

&uart_AO_B {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/meson-a1-gpio.h>

/ {
	compatible = "amlogic,a1";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		l2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x0 0x800000>;
			alignment = <0x0 0x400000>;
			linux,cma-default;
		};
	};

	sm: secure-monitor {
		compatible = "amlogic,meson-gxbb-sm";

		pwrc: power-controller {
			compatible = "amlogic,meson-a1-pwrc";
			#power-domain-cells = <1>;
			status = "okay";
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		apb: bus@fe000000 {
			compatible = "simple-bus";
			reg = <0x0 0xfe000000 0x0 0x1000000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;

			reset: reset-controller@0 {
				compatible = "amlogic,meson-a1-reset";
				reg = <0x0 0x0 0x0 0x8c>;
				#reset-cells = <1>;
			};

			periphs_pinctrl: pinctrl@400 {
				compatible = "amlogic,meson-a1-periphs-pinctrl";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges;

				gpio: bank@400 {
					reg = <0x0 0x0400 0x0 0x003c>,
					      <0x0 0x0480 0x0 0x0118>;
					reg-names = "mux", "gpio";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 0 62>;
				};

			};

			uart_AO: serial@1c00 {
				compatible = "amlogic,meson-gx-uart",
					     "amlogic,meson-ao-uart";
				reg = <0x0 0x1c00 0x0 0x18>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>, <&xtal>, <&xtal>;
				clock-names = "xtal", "pclk", "baud";
				status = "disabled";
			};

			uart_AO_B: serial@2000 {
				compatible = "amlogic,meson-gx-uart",
					     "amlogic,meson-ao-uart";
				reg = <0x0 0x2000 0x0 0x18>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>, <&xtal>, <&xtal>;
				clock-names = "xtal", "pclk", "baud";
				status = "disabled";
			};
		};

		gic: interrupt-controller@ff901000 {
			compatible = "arm,gic-400";
			reg = <0x0 0xff901000 0x0 0x1000>,
			      <0x0 0xff902000 0x0 0x2000>,
			      <0x0 0xff904000 0x0 0x2000>,
			      <0x0 0xff906000 0x0 0x2000>;
			interrupt-controller;
			interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
	};

	xtal: xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xtal";
		#clock-cells = <0>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Vyacheslav Bocharov <adeep@lexina.in>
 * Copyright (c) 2022 JetHome
 * Author: Vyacheslav Bocharov <adeep@lexina.in>
 */

/dts-v1/;

#include "meson-axg-jethome-jethub-j1xx.dtsi"

/ {
	compatible = "jethome,jethub-j100", "amlogic,a113d", "amlogic,meson-axg";
	model = "JetHome JetHub D1 (J100)";

	/* 1024MB RAM */
	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x40000000>;
	};
};

/* wifi module */
&sd_emmc_b {
	non-removable;

	brcmf: wifi@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
	};
};

/* UART Bluetooth */
&uart_B {
	bluetooth {
		compatible = "brcm,bcm43438-bt";
		shutdown-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Vyacheslav Bocharov <adeep@lexina.in>
 * Copyright (c) 2022 JetHome
 * Author: Vyacheslav Bocharov <adeep@lexina.in>
 */

/dts-v1/;

#include "meson-axg-jethome-jethub-j1xx.dtsi"

/ {
	compatible = "jethome,jethub-j110", "amlogic,a113d", "amlogic,meson-axg";
	model = "JetHome JetHub D1p (J110) HW rev.2";

	/* 2GiB or 4GiB RAM */
	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};
};

/* wifi module */
&sd_emmc_b {
	broken-cd;/* cd-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;*/
};

/* UART Bluetooth */
&uart_B {
	bluetooth {
		compatible = "realtek,rtl8822cs-bt";
		enable-gpios  = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>;
		host-wake-gpios = <&gpio GPIOZ_8 GPIO_ACTIVE_HIGH>;
		device-wake-gpios = <&gpio GPIOZ_6 GPIO_ACTIVE_HIGH>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Vyacheslav Bocharov <adeep@lexina.in>
 * Copyright (c) 2022 JetHome
 * Author: Vyacheslav Bocharov <adeep@lexina.in>
 */

/dts-v1/;

#include "meson-axg-jethome-jethub-j1xx.dtsi"

/ {
	compatible = "jethome,jethub-j110", "amlogic,a113d", "amlogic,meson-axg";
	model = "JetHome JetHub D1p (J110) Hw rev.3";

	/* 2GiB or 4GiB RAM */
	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};
};

/* wifi module */
&sd_emmc_b {
	broken-cd;/* cd-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;*/
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Vyacheslav Bocharov <adeep@lexina.in>
 * Copyright (c) 2022 JetHome
 * Author: Vyacheslav Bocharov <adeep@lexina.in>
 * Author: Aleksandr Kazantsev <ak@tvip.ru>
 * Author: Alexey Shevelkin <ash@tvip.ru>
 */

/dts-v1/;

#include "meson-axg.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	aliases {
		serial0 = &uart_AO;   /* Console */
		serial2 = &uart_AO_B; /* External UART (Wireless Module) */
		ethernet0 = &ethmac;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	reserved-memory {
		linux,cma {
			size = <0x0 0x400000>;
		};
	};

	emmc_pwrseq: emmc-pwrseq {
		compatible = "mmc-pwrseq-emmc";
		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
	};

	vcc_3v3: regulator-vcc_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "VCC_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vddao_3v3>;
		regulator-always-on;
	};

	vcc_5v: regulator-vcc_5v {
		compatible = "regulator-fixed";
		regulator-name = "VCC5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
	};

	vddao_3v3: regulator-vddao_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "VDDAO_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc_5v>;
		regulator-always-on;
	};

	vddio_ao18: regulator-vddio_ao18 {
		compatible = "regulator-fixed";
		regulator-name = "VDDIO_AO18";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&vddao_3v3>;
		regulator-always-on;
	};

	vddio_boot: regulator-vddio_boot {
		compatible = "regulator-fixed";
		regulator-name = "VDDIO_BOOT";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vddao_3v3>;
		regulator-always-on;
	};

	vccq_1v8: regulator-vccq_1v8 {
		compatible = "regulator-fixed";
		regulator-name = "VCCQ_1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&vddao_3v3>;
		regulator-always-on;
	};

	usb_pwr: regulator-usb_pwr {
		compatible = "regulator-fixed";
		regulator-name = "USB_PWR";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vcc_5v>;
		regulator-always-on;
	};

	sdio_pwrseq: sdio-pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
		clocks = <&wifi32k>;
		clock-names = "ext_clock";
	};

	wifi32k: wifi32k {
		compatible = "pwm-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&scpi_sensors 0>;
			trips {
				cpu_passive: cpu-passive {
					temperature = <70000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "passive";
				};

				cpu_hot: cpu-hot {
					temperature = <80000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "hot";
				};

				cpu_critical: cpu-critical {
					temperature = <100000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "critical";
				};
			};

			cpu_cooling_maps: cooling-maps {
				map0 {
					trip = <&cpu_passive>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};

				map1 {
					trip = <&cpu_hot>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	onewire {
		compatible = "w1-gpio";
		gpios = <&gpio GPIOA_14 GPIO_ACTIVE_HIGH>;
		#gpio-cells = <1>;
	};
};

&efuse {
	sn: sn@32 {
		reg = <0x32 0x20>;
	};

	eth_mac: eth_mac@0 {
		reg = <0x0 0x6>;
	};

	bt_mac: bt_mac@6 {
		reg = <0x6 0x6>;
	};

	wifi_mac: wifi_mac@c {
		reg = <0xc 0x6>;
	};

	bid: bid@12 {
		reg = <0x12 0x20>;
	};
};

&ethmac {
	status = "okay";
	pinctrl-0 = <&eth_rmii_x_pins>;
	pinctrl-names = "default";
	phy-handle = <&eth_phy0>;
	phy-mode = "rmii";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		/* ICPlus IP101A/G Ethernet PHY (vendor_id=0x0243, model_id=0x0c54) */
		eth_phy0: ethernet-phy@0 {
			/* compatible = "ethernet-phy-id0243.0c54";*/
			max-speed = <100>;
			reg = <0>;

			reset-assert-us = <10000>;
			reset-deassert-us = <10000>;
			reset-gpios = <&gpio GPIOZ_5 GPIO_ACTIVE_LOW>;
		};
	};
};

/* Internal I2C bus (on CPU module) */
&i2c1 {
	status = "okay";
	pinctrl-0 = <&i2c1_z_pins>;
	pinctrl-names = "default";

	/* RTC */
	pcf8563: pcf8563@51 {
		compatible = "nxp,pcf8563";
		reg = <0x51>;
		status = "okay";
	};
};

/* Peripheral I2C bus (on motherboard) */
&i2c_AO {
	status = "okay";
	pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
	pinctrl-names = "default";
};

&pwm_ab {
	status = "okay";
	pinctrl-0 = <&pwm_a_x20_pins>;
	pinctrl-names = "default";
};

/* wifi module */
&sd_emmc_b {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	pinctrl-0 = <&sdio_pins>;
	pinctrl-1 = <&sdio_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	max-frequency = <50000000>;
	disable-wp;

	mmc-pwrseq = <&sdio_pwrseq>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddio_boot>;
};

/* emmc storage */
&sd_emmc_c {
	status = "okay";
	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	max-frequency = <200000000>;
	non-removable;
	disable-wp;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;

	mmc-pwrseq = <&emmc_pwrseq>;

	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&vccq_1v8>;
};

/* UART Bluetooth */
&uart_B {
	status = "okay";
	pinctrl-0 = <&uart_b_z_pins>, <&uart_b_z_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;
};

/* UART Console */
&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
};

/* UART Wireless module */
&uart_AO_B {
	status = "okay";
	pinctrl-0 = <&uart_ao_b_pins>;
	pinctrl-names = "default";
};

&usb {
	status = "okay";
	phy-supply = <&usb_pwr>;
};

&spicc1 {
	status = "okay";
	pinctrl-0 = <&spi1_x_pins>, <&spi1_ss0_x_pins>;
	pinctrl-names = "default";
};

&gpio {
	gpio-line-names =
		"", "", "", "", "", // 0 - 4
		"", "", "", "", "", // 5 - 9
		"UserButton", "", "", "", "", // 10 - 14
		"", "", "", "", "", // 15 - 19
		"", "", "", "", "", // 20 - 24
		"", "LedRed", "LedGreen", "Output3", "Output2", // 25 - 29
		"Output1", "", "", "", "", // 30 - 34
		"", "ZigBeeBOOT", "", "", "", // 35 - 39
		"1Wire", "ZigBeeRESET", "", "Input4", "Input3", // 40 - 44
		"Input2", "Input1", "", "", "", // 45 - 49
		"", "", "", "", "", // 50 - 54
		"", "", "", "", "", // 55 - 59
		"", "", "", "", "", // 60 - 64
		"", "", "", "", "", // 65 - 69
		"", "", "", "", "", // 70 - 74
		"", "", "", "", "", // 75 - 79
		"", "", "", "", "", // 80 - 84
		"", ""; // 85-86
};

&cpu0 {
	#cooling-cells = <2>;
};

&cpu1 {
	#cooling-cells = <2>;
};

&cpu2 {
	#cooling-cells = <2>;
};

&cpu3 {
	#cooling-cells = <2>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
 */

/dts-v1/;

#include "meson-axg.dtsi"
#include <dt-bindings/input/input.h>

/ {
	compatible = "amlogic,s400", "amlogic,a113d", "amlogic,meson-axg";
	model = "Amlogic Meson AXG S400 Development Board";

	adc_keys {
		compatible = "adc-keys";
		io-channels = <&saradc 0>;
		io-channel-names = "buttons";
		keyup-threshold-microvolt = <1800000>;

		button-next {
			label = "Next";
			linux,code = <KEY_NEXT>;
			press-threshold-microvolt = <1116000>; /* 62% */
		};

		button-prev {
			label = "Previous";
			linux,code = <KEY_PREVIOUS>;
			press-threshold-microvolt = <900000>; /* 50% */
		};

		button-wifi {
			label = "Wifi";
			linux,code = <KEY_WLAN>;
			press-threshold-microvolt = <684000>; /* 38% */
		};

		button-up {
			label = "Volume Up";
			linux,code = <KEY_VOLUMEUP>;
			press-threshold-microvolt = <468000>; /* 26% */
		};

		button-down {
			label = "Volume Down";
			linux,code = <KEY_VOLUMEDOWN>;
			press-threshold-microvolt = <252000>; /* 14% */
		};

		button-voice {
			label = "Voice";
			linux,code = <KEY_VOICECOMMAND>;
			press-threshold-microvolt = <0>; /* 0% */
		};
	};

	aliases {
		serial0 = &uart_AO;
		serial1 = &uart_A;
	};

	linein: audio-codec-0 {
		#sound-dai-cells = <0>;
		compatible = "everest,es7241";
		VDDA-supply = <&vcc_3v3>;
		VDDP-supply = <&vcc_3v3>;
		VDDD-supply = <&vcc_3v3>;
		status = "okay";
		sound-name-prefix = "Linein";
	};

	lineout: audio-codec-1 {
		#sound-dai-cells = <0>;
		compatible = "everest,es7154";
		VDD-supply = <&vcc_3v3>;
		PVDD-supply = <&vcc_5v>;
		status = "okay";
		sound-name-prefix = "Lineout";
	};

	spdif_dit: audio-codec-2 {
		#sound-dai-cells = <0>;
		compatible = "linux,spdif-dit";
		status = "okay";
		sound-name-prefix = "DIT";
	};

	dmics: audio-codec-3 {
		#sound-dai-cells = <0>;
		compatible = "dmic-codec";
		num-channels = <7>;
		wakeup-delay-ms = <50>;
		status = "okay";
		sound-name-prefix = "MIC";
	};

	spdif_dir: audio-codec-4 {
		#sound-dai-cells = <0>;
		compatible = "linux,spdif-dir";
		status = "okay";
		sound-name-prefix = "DIR";
	};

	emmc_pwrseq: emmc-pwrseq {
		compatible = "mmc-pwrseq-emmc";
		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x40000000>;
	};

	main_12v: regulator-main_12v {
		compatible = "regulator-fixed";
		regulator-name = "12V";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
	};

	vcc_3v3: regulator-vcc_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "VCC_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vddao_3v3>;
		regulator-always-on;
	};

	vcc_5v: regulator-vcc_5v {
		compatible = "regulator-fixed";
		regulator-name = "VCC5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&main_12v>;

		gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vddao_3v3: regulator-vddao_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "VDDAO_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&main_12v>;
		regulator-always-on;
	};

	vddio_ao18: regulator-vddio_ao18 {
		compatible = "regulator-fixed";
		regulator-name = "VDDIO_AO18";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&vddao_3v3>;
		regulator-always-on;
	};

	vddio_boot: regulator-vddio_boot {
		compatible = "regulator-fixed";
		regulator-name = "VDDIO_BOOT";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&vddao_3v3>;
		regulator-always-on;
	};

	usb_pwr: regulator-usb_pwr {
		compatible = "regulator-fixed";
		regulator-name = "USB_PWR";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vcc_5v>;

		gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	sdio_pwrseq: sdio-pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
		clocks = <&wifi32k>;
		clock-names = "ext_clock";
	};

	speaker-leds {
		compatible = "gpio-leds";

		aled1 {
			label = "speaker:aled1";
			gpios = <&gpio_speaker 7 0>;
		};

		aled2 {
			label = "speaker:aled2";
			gpios = <&gpio_speaker 6 0>;
		};

		aled3 {
			label = "speaker:aled3";
			gpios = <&gpio_speaker 5 0>;
		};

		aled4 {
			label = "speaker:aled4";
			gpios = <&gpio_speaker 4 0>;
		};

		aled5 {
			label = "speaker:aled5";
			gpios = <&gpio_speaker 3 0>;
		};

		aled6 {
			label = "speaker:aled6";
			gpios = <&gpio_speaker 2 0>;
		};
	};

	sound {
		compatible = "amlogic,axg-sound-card";
		model = "AXG-S400";
		audio-aux-devs = <&tdmin_a>, <&tdmin_b>,  <&tdmin_c>,
				 <&tdmin_lb>, <&tdmout_c>;
		audio-widgets = "Line", "Lineout",
				"Line", "Linein",
				"Speaker", "Speaker1 Left",
				"Speaker", "Speaker1 Right";
		audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
				"SPDIFOUT IN 0", "FRDDR_A OUT 3",
				"TDMOUT_C IN 1", "FRDDR_B OUT 2",
				"SPDIFOUT IN 1", "FRDDR_B OUT 3",
				"TDMOUT_C IN 2", "FRDDR_C OUT 2",
				"SPDIFOUT IN 2", "FRDDR_C OUT 3",
				"TDM_C Playback", "TDMOUT_C OUT",
				"TDMIN_A IN 2", "TDM_C Capture",
				"TDMIN_A IN 5", "TDM_C Loopback",
				"TDMIN_B IN 2", "TDM_C Capture",
				"TDMIN_B IN 5", "TDM_C Loopback",
				"TDMIN_C IN 2", "TDM_C Capture",
				"TDMIN_C IN 5", "TDM_C Loopback",
				"TDMIN_LB IN 2", "TDM_C Loopback",
				"TDMIN_LB IN 5", "TDM_C Capture",
				"TODDR_A IN 0", "TDMIN_A OUT",
				"TODDR_B IN 0", "TDMIN_A OUT",
				"TODDR_C IN 0", "TDMIN_A OUT",
				"TODDR_A IN 1", "TDMIN_B OUT",
				"TODDR_B IN 1", "TDMIN_B OUT",
				"TODDR_C IN 1", "TDMIN_B OUT",
				"TODDR_A IN 2", "TDMIN_C OUT",
				"TODDR_B IN 2", "TDMIN_C OUT",
				"TODDR_C IN 2", "TDMIN_C OUT",
				"TODDR_A IN 3", "SPDIFIN Capture",
				"TODDR_B IN 3", "SPDIFIN Capture",
				"TODDR_C IN 3", "SPDIFIN Capture",
				"TODDR_A IN 4", "PDM Capture",
				"TODDR_B IN 4", "PDM Capture",
				"TODDR_C IN 4", "PDM Capture",
				"TODDR_A IN 6", "TDMIN_LB OUT",
				"TODDR_B IN 6", "TDMIN_LB OUT",
				"TODDR_C IN 6", "TDMIN_LB OUT",
				"Lineout", "Lineout AOUTL",
				"Lineout", "Lineout AOUTR",
				"Speaker1 Left", "SPK1 OUT_A",
				"Speaker1 Left", "SPK1 OUT_B",
				"Speaker1 Right", "SPK1 OUT_C",
				"Speaker1 Right", "SPK1 OUT_D",
				"Linein AINL", "Linein",
				"Linein AINR", "Linein";
		assigned-clocks = <&clkc CLKID_HIFI_PLL>,
				  <&clkc CLKID_MPLL0>,
				  <&clkc CLKID_MPLL1>;
		assigned-clock-parents = <0>, <0>, <0>;
		assigned-clock-rates = <589824000>,
				       <270950400>,
				       <393216000>;
		status = "okay";

		dai-link-0 {
			sound-dai = <&frddr_a>;
		};

		dai-link-1 {
			sound-dai = <&frddr_b>;
		};

		dai-link-2 {
			sound-dai = <&frddr_c>;
		};

		dai-link-3 {
			sound-dai = <&toddr_a>;
		};

		dai-link-4 {
			sound-dai = <&toddr_b>;
		};

		dai-link-5 {
			sound-dai = <&toddr_c>;
		};

		dai-link-6 {
			sound-dai = <&tdmif_c>;
			dai-format = "i2s";
			dai-tdm-slot-tx-mask-2 = <1 1>;
			dai-tdm-slot-rx-mask-1 = <1 1>;
			mclk-fs = <256>;

			codec-0 {
				sound-dai = <&lineout>;
			};

			codec-1 {
				sound-dai = <&speaker_amp1>;
			};

			codec-2 {
				sound-dai = <&linein>;
			};

		};

		dai-link-7 {
			sound-dai = <&spdifout>;

			codec {
				sound-dai = <&spdif_dit>;
			};
		};

		dai-link-8 {
			sound-dai = <&spdifin>;

			codec {
				sound-dai = <&spdif_dir>;
			};
		};

		dai-link-9 {
			sound-dai = <&pdm>;

			codec {
				sound-dai = <&dmics>;
			};
		};
	};

	wifi32k: wifi32k {
		compatible = "pwm-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
	};
};

&ethmac {
	status = "okay";
	pinctrl-0 = <&eth_rgmii_y_pins>;
	pinctrl-names = "default";
	phy-handle = <&eth_phy0>;
	phy-mode = "rgmii";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		eth_phy0: ethernet-phy@0 {
			/* Realtek RTL8211F (0x001cc916) */
			reg = <0>;
			interrupt-parent = <&gpio_intc>;
			interrupts = <98 IRQ_TYPE_LEVEL_LOW>;
			eee-broken-1000t;
		};
	};
};

&frddr_a {
	status = "okay";
};

&frddr_b {
	status = "okay";
};

&frddr_c {
	status = "okay";
};

&ir {
	status = "okay";
	pinctrl-0 = <&remote_input_ao_pins>;
	pinctrl-names = "default";
};

&i2c1 {
	status = "okay";
	pinctrl-0 = <&i2c1_z_pins>;
	pinctrl-names = "default";

	speaker_amp1: audio-codec@1b {
		compatible = "ti,tas5707";
		reg = <0x1b>;
		reset-gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>;
		#sound-dai-cells = <0>;
		AVDD-supply = <&vcc_3v3>;
		DVDD-supply = <&vcc_3v3>;
		PVDD_A-supply = <&main_12v>;
		PVDD_B-supply = <&main_12v>;
		PVDD_C-supply = <&main_12v>;
		PVDD_D-supply = <&main_12v>;
		sound-name-prefix = "SPK1";
	};
};

&i2c_AO {
	status = "okay";
	pinctrl-0 = <&i2c_ao_sck_10_pins>, <&i2c_ao_sda_11_pins>;
	pinctrl-names = "default";

	gpio_speaker: gpio-controller@1f {
		compatible = "nxp,pca9557";
		reg = <0x1f>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&vddao_3v3>;
	};
};

&pdm {
	pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>,
		    <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&pcieA {
	reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&pcieB {
	reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&pwm_ab {
	status = "okay";
	pinctrl-0 = <&pwm_a_x20_pins>;
	pinctrl-names = "default";
};

&saradc {
	status = "okay";
	vref-supply = <&vddio_ao18>;
};

/* wifi module */
&sd_emmc_b {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	pinctrl-0 = <&sdio_pins>;
	pinctrl-1 = <&sdio_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <4>;
	cap-sd-highspeed;
	sd-uhs-sdr104;
	max-frequency = <200000000>;
	non-removable;
	disable-wp;

	mmc-pwrseq = <&sdio_pwrseq>;

	vmmc-supply = <&vddao_3v3>;
	vqmmc-supply = <&vddio_boot>;

	brcmf: wifi@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
	};
};

/* emmc storage */
&sd_emmc_c {
	status = "okay";
	pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
	pinctrl-1 = <&emmc_clk_gate_pins>;
	pinctrl-names = "default", "clk-gate";

	bus-width = <8>;
	cap-mmc-highspeed;
	max-frequency = <200000000>;
	non-removable;
	disable-wp;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;

	mmc-pwrseq = <&emmc_pwrseq>;

	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&vddio_boot>;
};

&spdifin {
	pinctrl-0 = <&spdif_in_a19_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&spdifout {
	pinctrl-0 = <&spdif_out_a20_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&tdmif_a {
	pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
		    <&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&tdmif_b {
	pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
		    <&tdmb_din3_pins>, <&mclk_b_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&tdmif_c {
	pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
		    <&tdmc_din1_pins>, <&tdmc_dout2_pins>,
		    <&mclk_c_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&tdmin_a {
	status = "okay";
};

&tdmin_b {
	status = "okay";
};

&tdmin_c {
	status = "okay";
};

&tdmin_lb {
	status = "okay";
};

&tdmout_c {
	status = "okay";
};

&toddr_a {
	status = "okay";
};

&toddr_b {
	status = "okay";
};

&toddr_c {
	status = "okay";
};

&uart_A {
	status = "okay";
	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;

	bluetooth {
		compatible = "brcm,bcm43438-bt";
		shutdown-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>;
	};
};

&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
};

&usb {
	status = "okay";
	dr_mode = "otg";
	vbus-supply = <&usb_pwr>;
};