code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 39x family of SoCs.
 *
 * Copyright (C) 2015 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Marvell Armada 39x family SoC";
	compatible = "marvell,armada390";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-390-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts-extended = <&mpic 3>;
	};

	soc {
		compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
			     "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&gic>;
		pcie-mem-aperture = <0xe0000000 0x8000000>;
		pcie-io-aperture  = <0xe8000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			L2: cache-controller@8000 {
				compatible = "arm,pl310-cache";
				reg = <0x8000 0x1000>;
				cache-unified;
				cache-level = <2>;
				arm,double-linefill-incr = <0>;
				arm,double-linefill-wrap = <0>;
				arm,double-linefill = <0>;
				prefetch-data = <1>;
			};

			scu@c000 {
				compatible = "arm,cortex-a9-scu";
				reg = <0xc000 0x100>;
			};

			timer@c600 {
				compatible = "arm,cortex-a9-twd-timer";
				reg = <0xc600 0x20>;
				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
				clocks = <&coreclk 2>;
			};

			gic: interrupt-controller@d000 {
				compatible = "arm,cortex-a9-gic";
				#interrupt-cells = <3>;
				#size-cells = <0>;
				interrupt-controller;
				reg = <0xd000 0x1000>,
				      <0xc100 0x100>;
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c2: i2c@11200 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11200 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c3: i2c@11300 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11300 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart0: serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart2: serial@12200 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12200 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart3: serial@12300 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12300 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl@18000 {
				i2c0_pins: i2c0-pins {
					marvell,pins = "mpp2", "mpp3";
					marvell,function = "i2c0";
				};

				uart0_pins: uart0-pins {
					marvell,pins = "mpp0", "mpp1";
					marvell,function = "ua0";
				};

				uart1_pins: uart1-pins {
					marvell,pins = "mpp19", "mpp20";
					marvell,function = "ua1";
				};

				spi1_pins: spi1-pins {
					marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
					marvell,function = "spi1";
				};

				nand_pins: nand-pins {
					marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
						       "mpp38", "mpp28", "mpp40", "mpp42",
						       "mpp35", "mpp36", "mpp25", "mpp30",
						       "mpp32";
					marvell,function = "dev";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <28>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			};

			system-controller@18200 {
				compatible = "marvell,armada-390-system-controller",
					     "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x100>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-390-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			coreclk: mvebu-sar@18600 {
				compatible = "marvell,armada-390-core-clock";
				reg = <0x18600 0x04>;
				#clock-cells = <1>;
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
			};

			mpic: interrupt-controller@20a00 {
				compatible = "marvell,mpic";
				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			timer@20300 {
				compatible = "marvell,armada-380-timer",
					     "marvell,armada-xp-timer";
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
						      <&mpic 5>,
						      <&mpic 6>;
				clocks = <&coreclk 2>, <&coreclk 5>;
				clock-names = "nbclk", "fixed";
			};

			watchdog@20300 {
				compatible = "marvell,armada-380-wdt";
				reg = <0x20300 0x34>, <0x20704 0x4>,
				      <0x18260 0x4>;
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x10>;
			};

			mpcore-soc-ctrl@20d20 {
				compatible = "marvell,armada-380-mpcore-soc-ctrl";
				reg = <0x20d20 0x6c>;
			};

			coherency-fabric@21010 {
				compatible = "marvell,armada-380-coherency-fabric";
				reg = <0x21010 0x1c>;
			};

			pmsu@22000 {
				compatible = "marvell,armada-390-pmsu",
					     "marvell,armada-380-pmsu";
				reg = <0x22000 0x1000>;
			};

			xor@60800 {
				compatible = "marvell,armada-380-xor", "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60a00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor00 {
					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor@60900 {
				compatible = "marvell,armada-380-xor", "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 28>;
				status = "okay";

				xor10 {
					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			rtc@a3800 {
				compatible = "marvell,armada-380-rtc";
				reg = <0xa3800 0x20>, <0x184a0 0x0c>;
				reg-names = "rtc", "rtc-soc";
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			};

			nand_controller: nand-controller@d0000 {
				compatible = "marvell,armada370-nand-controller";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coredivclk 0>;
				status = "disabled";
			};

			sdhci@d8000 {
				compatible = "marvell,armada-380-sdhci";
				reg-names = "sdhci", "mbus", "conf-sdio3";
				reg = <0xd8000 0x1000>,
					<0xdc000 0x100>,
					<0x18454 0x4>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 17>;
				mrvl,clk-delay-cycles = <0x1F>;
				status = "disabled";
			};

			coredivclk: clock@e4250 {
				compatible = "marvell,armada-390-corediv-clock",
					     "marvell,armada-380-corediv-clock";
				reg = <0xe4250 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};

			thermal@e8078 {
				compatible = "marvell,armada380-thermal";
				reg = <0xe4078 0x4>, <0xe4074 0x4>;
				status = "okay";
			};
		};

		pcie {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;

			/*
			 * This port can be either x4 or x1. When
			 * configured in x4 by the bootloader, then
			 * pcie@4,0 is not available.
			 */
			pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
						<0 0 0 2 &pcie1_intc 1>,
						<0 0 0 3 &pcie1_intc 2>,
						<0 0 0 4 &pcie1_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 8>;
				status = "disabled";

				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			/* x1 port */
			pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
						<0 0 0 2 &pcie2_intc 1>,
						<0 0 0 3 &pcie2_intc 2>,
						<0 0 0 4 &pcie2_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";

				pcie2_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			/* x1 port */
			pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
						<0 0 0 2 &pcie3_intc 1>,
						<0 0 0 3 &pcie3_intc 2>,
						<0 0 0 4 &pcie3_intc 3>;
				marvell,pcie-port = <2>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 6>;
				status = "disabled";

				pcie3_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			/*
			 * x1 port only available when pcie@1,0 is
			 * configured as a x1 port
			 */
			pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82002000 0 0x48000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie4_intc 0>,
						<0 0 0 2 &pcie4_intc 1>,
						<0 0 0 3 &pcie4_intc 2>,
						<0 0 0 4 &pcie4_intc 3>;
				marvell,pcie-port = <3>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 7>;
				status = "disabled";

				pcie4_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};
		};

		spi0: spi@10600 {
			compatible = "marvell,armada-390-spi",
					"marvell,orion-spi";
			reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		spi1: spi@10680 {
			compatible = "marvell,armada-390-spi",
					"marvell,orion-spi";
			reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};
	};

	clocks {
		/* 1 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000000>;
		};

		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell 98dx3236 family SoC
 *
 * Copyright (C) 2016 Allied Telesis Labs
 *
 * Contains definitions specific to the 98dx3236 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-370-xp.dtsi"

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	model = "Marvell 98DX3236 SoC";
	compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,98dx3236-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
			clock-latency = <1000000>;
		};
	};

	soc {
		compatible = "marvell,armadaxp-mbus", "simple-bus";

		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
			  MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
			  MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
		};

		/*
		 * 98DX3236 has 1 x1 PCIe unit Gen2.0
		 */
		pciec: pcie@82000000 {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */>;

			pcie1: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 58>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
						<0 0 0 2 &pcie1_intc 1>,
						<0 0 0 3 &pcie1_intc 2>,
						<0 0 0 4 &pcie1_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";

				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};
		};

		internal-regs {
			sdramc: sdramc@1400 {
				compatible = "marvell,armada-xp-sdram-controller";
				reg = <0x1400 0x500>;
			};

			L2: l2-cache@8000 {
				compatible = "marvell,aurora-system-cache";
				reg = <0x08000 0x1000>;
				cache-id-part = <0x100>;
				cache-level = <2>;
				cache-unified;
				wt-override;
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
			};

			/* does not exist */
			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				status = "disabled";
			};

			gpio2: gpio@18180 { /* rework some properties */
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <1>; /* only gpio #32 */
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>;
			};

			systemc: system-controller@18200 {
				compatible = "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x500>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,mv98dx3236-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			cpuclk: clock-complex@18700 {
				#clock-cells = <1>;
				compatible = "marvell,mv98dx3236-cpu-clock";
				reg = <0x18700 0x24>, <0x1c054 0x10>;
				clocks = <&coreclk 1>;
			};

			corediv-clock@18740 {
				status = "disabled";
			};

			cpu-config@21000 {
				compatible = "marvell,armada-xp-cpu-config";
				reg = <0x21000 0x8>;
			};

			ethernet@70000 {
				compatible = "marvell,armada-xp-neta";
			};

			ethernet@74000 {
				compatible = "marvell,armada-xp-neta";
			};

			xor1: xor@f0800 {
				compatible = "marvell,orion-xor";
				reg = <0xf0800 0x100
				       0xf0a00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor10 {
					interrupts = <51>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <52>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			nand_controller: nand-controller@d0000 {
				clocks = <&dfx_coredivclk 0>;
			};

			xor0: xor@f0900 {
				compatible = "marvell,orion-xor";
				reg = <0xF0900 0x100
				       0xF0B00 0x100>;
				clocks = <&gateclk 28>;
				status = "okay";

				xor00 {
					interrupts = <94>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <95>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};
		};

		dfx: dfx-server@ac000000 {
			compatible = "marvell,dfx-server", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
			reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;

			coreclk: mvebu-sar@f8204 {
				compatible = "marvell,mv98dx3236-core-clock";
				reg = <0xf8204 0x4>;
				#clock-cells = <1>;
			};

			dfx_coredivclk: corediv-clock@f8268 {
				compatible = "marvell,mv98dx3236-corediv-clock";
				reg = <0xf8268 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};
		};

		switch: switch@a8000000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;

			pp0: packet-processor@0 {
				compatible = "marvell,prestera-98dx3236", "marvell,prestera";
				reg = <0 0x4000000>;
				interrupts = <33>, <34>, <35>;
				dfx = <&dfx>;
			};
		};
	};

	clocks {
		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};
};

&i2c0 {
	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
	reg = <0x11000 0x100>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
};

&mpic {
	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};

&rtc {
	status = "disabled";
};

&timer {
	compatible = "marvell,armada-xp-timer";
	clocks = <&coreclk 2>, <&refclk>;
	clock-names = "nbclk", "fixed";
};

&watchdog {
	compatible = "marvell,armada-xp-wdt";
	clocks = <&coreclk 2>, <&refclk>;
	clock-names = "nbclk", "fixed";
	interrupts = <93>, <38>;
};

&cpurst {
	reg = <0x20800 0x20>;
};

&usb0 {
	clocks = <&gateclk 18>;
};

&usb1 {
	clocks = <&gateclk 19>;
};

&pinctrl {
	compatible = "marvell,98dx3236-pinctrl";

	nand_pins: nand-pins {
		marvell,pins = "mpp20", "mpp21", "mpp22",
			       "mpp23", "mpp24", "mpp25",
			       "mpp26", "mpp27", "mpp28",
			       "mpp29", "mpp30";
		marvell,function = "dev";
	};

	nand_rb: nand-rb {
		marvell,pins = "mpp19";
		marvell,function = "nand";
	};

	spi0_pins: spi0-pins {
		marvell,pins = "mpp0", "mpp1",
			       "mpp2", "mpp3";
		marvell,function = "spi0";
	};

	i2c0_pins: i2c-pins-0 {
		marvell,pins = "mpp14", "mpp15";
		marvell,function = "i2c0";
	};
};

&spi0 {
	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
	pinctrl-0 = <&spi0_pins>;
	pinctrl-names = "default";
};

&sdio {
	status = "disabled";
};

&uart0 {
	compatible = "marvell,armada-38x-uart";
};

&uart1 {
	compatible = "marvell,armada-38x-uart";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell 98dx3336 family SoC
 *
 * Copyright (C) 2016 Allied Telesis Labs
 *
 * Contains definitions specific to the 98dx3236 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-xp-98dx3236.dtsi"

/ {
	model = "Marvell 98DX3336 SoC";
	compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";

	cpus {
		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
			clock-latency = <1000000>;
		};
	};

	soc {
		internal-regs {
			resume@20980 {
				compatible = "marvell,98dx3336-resume-ctrl";
				reg = <0x20980 0x10>;
			};
		};
	};
};

&pp0 {
	compatible = "marvell,prestera-98dx3336", "marvell,prestera";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell 98dx4521 family SoC
 *
 * Copyright (C) 2016 Allied Telesis Labs
 *
 * Contains definitions specific to the 98dx4521 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-xp-98dx3236.dtsi"

/ {
	model = "Marvell 98DX4251 SoC";
	compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";

	cpus {
		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
			clock-latency = <1000000>;
		};
	};

	soc {
		internal-regs {
			resume@20980 {
				compatible = "marvell,98dx3336-resume-ctrl";
				reg = <0x20980 0x10>;
			};
		};
	};
};

&sdio {
	status = "okay";
};

&pinctrl {
	compatible = "marvell,98dx4251-pinctrl";

	sdio_pins: sdio-pins {
		marvell,pins = "mpp5", "mpp6", "mpp7",
			       "mpp8", "mpp9", "mpp10";
		marvell,function = "sd0";
	};
};

&pp0 {
	compatible = "marvell,prestera-98dx4251", "marvell,prestera";
	interrupts = <33>, <34>, <35>, <36>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell RD-AXPWiFiAP.
 *
 * Note: this board is shipped with a new generation boot loader that
 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
 * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the
 * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used.
 *
 * Copyright (C) 2013 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-xp-mv78230.dtsi"

/ {
	model = "Marvell RD-AXPWiFiAP";
	compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;

		internal-regs {
			/* UART0 */
			serial@12000 {
				status = "okay";
			};

			/* UART1 */
			serial@12100 {
				status = "okay";
			};

			sata@a0000 {
				nr-ports = <1>;
				status = "okay";
			};

			ethernet@70000 {
				pinctrl-0 = <&ge0_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};
			ethernet@74000 {
				pinctrl-0 = <&ge1_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
			};
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&keys_pin>;
		pinctrl-names = "default";

		button-reset {
			label = "Factory Reset Button";
			linux,code = <KEY_SETUP>;
			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
		};
	};
};

&mdio {
	phy0: ethernet-phy@0 {
		reg = <0>;
	};

	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&pciec {
	status = "okay";

	/* First mini-PCIe port */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};

	/* Second mini-PCIe port */
	pcie@2,0 {
		/* Port 0, Lane 1 */
		status = "okay";
	};

	/* Renesas uPD720202 USB 3.0 controller */
	pcie@3,0 {
		/* Port 0, Lane 3 */
		status = "okay";
	};
};

&pinctrl {
	pinctrl-0 = <&phy_int_pin>;
	pinctrl-names = "default";

	keys_pin: keys-pin {
		marvell,pins = "mpp33";
		marvell,function = "gpio";
	};

	phy_int_pin: phy-int-pin {
		marvell,pins = "mpp32";
		marvell,function = "gpio";
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "n25q128a13", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <108000000>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for MikroTik CRS305-1G-4S+ Bit board
 *
 * Copyright (C) 2020 Sartura Ltd.
 * Author: Luka Kovacic <luka.kovacic@sartura.hr>
 */

#include "armada-xp-crs305-1g-4s.dtsi"

/ {
	model = "MikroTik CRS305-1G-4S+ Bit";
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <108000000>;
		m25p,fast-read;

		partition@u-boot {
			reg = <0x00000000 0x001f0000>;
			label = "u-boot";
		};
		partition@u-boot-env {
			reg = <0x001f0000 0x00010000>;
			label = "u-boot-env";
		};
		partition@ubi1 {
			reg = <0x00200000 0x03f00000>;
			label = "ubi1";
		};
		partition@ubi2 {
			reg = <0x04100000 0x03f00000>;
			label = "ubi2";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for MikroTik CRS305-1G-4S+ board
 *
 * Copyright (C) 2020 Sartura Ltd.
 * Author: Luka Kovacic <luka.kovacic@sartura.hr>
 */

#include "armada-xp-crs305-1g-4s.dtsi"

/ {
	model = "MikroTik CRS305-1G-4S+";
};

&spi0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for CRS305-1G-4S board
 *
 * Copyright (C) 2016 Allied Telesis Labs
 * Copyright (C) 2020 Sartura Ltd.
 *
 * Based on armada-xp-db.dts
 *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the default
 * 0xd0000000). The 0xf1000000 is the default used by the recent,
 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
 * boards were delivered with an older version of the bootloader that
 * left internal registers mapped at 0xd0000000. If you are in this
 * situation, you should either update your bootloader (preferred
 * solution) or the below Device Tree should be adjusted.
 */

/dts-v1/;
#include "armada-xp-98dx3236.dtsi"

/ {
	model = "CRS305-1G-4S+";
	compatible = "mikrotik,crs305-1g-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";

	chosen {
		bootargs = "console=ttyS0,115200 earlyprintk";
	};

	memory {
		device_type = "memory";
		reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
	};
};

&L2 {
	arm,parity-enable;
	marvell,ecc-enable;
};

&devbus_bootcs {
	status = "okay";

	/* Device Bus parameters are required */

	/* Read parameters */
	devbus,bus-width    = <16>;
	devbus,turn-off-ps  = <60000>;
	devbus,badr-skew-ps = <0>;
	devbus,acc-first-ps = <124000>;
	devbus,acc-next-ps  = <248000>;
	devbus,rd-setup-ps  = <0>;
	devbus,rd-hold-ps   = <0>;

	/* Write parameters */
	devbus,sync-enable = <0>;
	devbus,wr-high-ps  = <60000>;
	devbus,wr-low-ps   = <60000>;
	devbus,ale-wr-ps   = <60000>;
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&i2c0 {
	clock-frequency = <100000>;
	status = "okay";
};

&usb0 {
	status = "okay";
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <108000000>;
		m25p,fast-read;

		partition@u-boot {
			reg = <0x00000000 0x001f0000>;
			label = "u-boot";
		};
		partition@u-boot-env {
			reg = <0x001f0000 0x00010000>;
			label = "u-boot-env";
		};
		partition@ubi1 {
			reg = <0x00200000 0x00e00000>;
			label = "ubi1";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for MikroTik CRS326-24G-2S+ Bit board
 *
 * Copyright (C) 2020 Sartura Ltd.
 * Author: Luka Kovacic <luka.kovacic@sartura.hr>
 */

#include "armada-xp-crs326-24g-2s.dtsi"

/ {
	model = "MikroTik CRS326-24G-2S+ Bit";
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <108000000>;
		m25p,fast-read;

		partition@u-boot {
			reg = <0x00000000 0x001f0000>;
			label = "u-boot";
		};
		partition@u-boot-env {
			reg = <0x001f0000 0x00010000>;
			label = "u-boot-env";
		};
		partition@ubi1 {
			reg = <0x00200000 0x03f00000>;
			label = "ubi1";
		};
		partition@ubi2 {
			reg = <0x04100000 0x03f00000>;
			label = "ubi2";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for MikroTik CRS326-24G-2S+ board
 *
 * Copyright (C) 2020 Sartura Ltd.
 * Author: Luka Kovacic <luka.kovacic@sartura.hr>
 */

#include "armada-xp-crs326-24g-2s.dtsi"

/ {
	model = "MikroTik CRS326-24G-2S+";
};

&spi0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for CRS326-24G-2S board
 *
 * Copyright (C) 2016 Allied Telesis Labs
 * Copyright (C) 2020 Sartura Ltd.
 *
 * Based on armada-xp-db.dts
 *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the default
 * 0xd0000000). The 0xf1000000 is the default used by the recent,
 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
 * boards were delivered with an older version of the bootloader that
 * left internal registers mapped at 0xd0000000. If you are in this
 * situation, you should either update your bootloader (preferred
 * solution) or the below Device Tree should be adjusted.
 */

/dts-v1/;
#include "armada-xp-98dx3236.dtsi"

/ {
	model = "CRS326-24G-2S+";
	compatible = "mikrotik,crs326-24g-2s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";

	chosen {
		bootargs = "console=ttyS0,115200 earlyprintk";
	};

	memory {
		device_type = "memory";
		reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
	};
};

&L2 {
	arm,parity-enable;
	marvell,ecc-enable;
};

&devbus_bootcs {
	status = "okay";

	/* Device Bus parameters are required */

	/* Read parameters */
	devbus,bus-width    = <16>;
	devbus,turn-off-ps  = <60000>;
	devbus,badr-skew-ps = <0>;
	devbus,acc-first-ps = <124000>;
	devbus,acc-next-ps  = <248000>;
	devbus,rd-setup-ps  = <0>;
	devbus,rd-hold-ps   = <0>;

	/* Write parameters */
	devbus,sync-enable = <0>;
	devbus,wr-high-ps  = <60000>;
	devbus,wr-low-ps   = <60000>;
	devbus,ale-wr-ps   = <60000>;
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&i2c0 {
	clock-frequency = <100000>;
	status = "okay";
};

&usb0 {
	status = "okay";
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <108000000>;
		m25p,fast-read;

		partition@u-boot {
			reg = <0x00000000 0x001f0000>;
			label = "u-boot";
		};
		partition@u-boot-env {
			reg = <0x001f0000 0x00010000>;
			label = "u-boot-env";
		};
		partition@ubi1 {
			reg = <0x00200000 0x00e00000>;
			label = "ubi1";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for MikroTik CRS328-4C-20S-4S+ Bit board
 *
 * Copyright (C) 2020 Sartura Ltd.
 * Author: Luka Kovacic <luka.kovacic@sartura.hr>
 */

#include "armada-xp-crs328-4c-20s-4s.dtsi"

/ {
	model = "MikroTik CRS328-4C-20S-4S+ Bit";
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <108000000>;
		m25p,fast-read;

		partition@u-boot {
			reg = <0x00000000 0x001f0000>;
			label = "u-boot";
		};
		partition@u-boot-env {
			reg = <0x001f0000 0x00010000>;
			label = "u-boot-env";
		};
		partition@ubi1 {
			reg = <0x00200000 0x03f00000>;
			label = "ubi1";
		};
		partition@ubi2 {
			reg = <0x04100000 0x03f00000>;
			label = "ubi2";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for MikroTik CRS328-4C-20S-4S+ board
 *
 * Copyright (C) 2020 Sartura Ltd.
 * Author: Luka Kovacic <luka.kovacic@sartura.hr>
 */

#include "armada-xp-crs328-4c-20s-4s.dtsi"

/ {
	model = "MikroTik CRS328-4C-20S-4S+";
};

&spi0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for CRS328-4C-20S-4S+ board
 *
 * Copyright (C) 2016 Allied Telesis Labs
 * Copyright (C) 2020 Sartura Ltd.
 *
 * Based on armada-xp-db.dts
 *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the default
 * 0xd0000000). The 0xf1000000 is the default used by the recent,
 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
 * boards were delivered with an older version of the bootloader that
 * left internal registers mapped at 0xd0000000. If you are in this
 * situation, you should either update your bootloader (preferred
 * solution) or the below Device Tree should be adjusted.
 */

/dts-v1/;
#include "armada-xp-98dx3236.dtsi"

/ {
	model = "CRS328-4C-20S-4S+";
	compatible = "mikrotik,crs328-4c-20s-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";

	chosen {
		bootargs = "console=ttyS0,115200 earlyprintk";
	};

	memory {
		device_type = "memory";
		reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
	};
};

&L2 {
	arm,parity-enable;
	marvell,ecc-enable;
};

&devbus_bootcs {
	status = "okay";

	/* Device Bus parameters are required */

	/* Read parameters */
	devbus,bus-width    = <16>;
	devbus,turn-off-ps  = <60000>;
	devbus,badr-skew-ps = <0>;
	devbus,acc-first-ps = <124000>;
	devbus,acc-next-ps  = <248000>;
	devbus,rd-setup-ps  = <0>;
	devbus,rd-hold-ps   = <0>;

	/* Write parameters */
	devbus,sync-enable = <0>;
	devbus,wr-high-ps  = <60000>;
	devbus,wr-low-ps   = <60000>;
	devbus,ale-wr-ps   = <60000>;
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&i2c0 {
	clock-frequency = <100000>;
	status = "okay";
};

&usb0 {
	status = "okay";
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <108000000>;
		m25p,fast-read;

		partition@u-boot {
			reg = <0x00000000 0x001f0000>;
			label = "u-boot";
		};
		partition@u-boot-env {
			reg = <0x001f0000 0x00010000>;
			label = "u-boot-env";
		};
		partition@ubi1 {
			reg = <0x00200000 0x00e00000>;
			label = "ubi1";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for DB-DXBC2 board
 *
 * Copyright (C) 2016 Allied Telesis Labs
 *
 * Based on armada-xp-db.dts
 *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the default
 * 0xd0000000). The 0xf1000000 is the default used by the recent,
 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
 * boards were delivered with an older version of the bootloader that
 * left internal registers mapped at 0xd0000000. If you are in this
 * situation, you should either update your bootloader (preferred
 * solution) or the below Device Tree should be adjusted.
 */

/dts-v1/;
#include "armada-xp-98dx4251.dtsi"

/ {
	model = "Marvell Bobcat2 Evaluation Board";
	compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";

	chosen {
		bootargs = "console=ttyS0,115200 earlyprintk";
	};

	memory {
		device_type = "memory";
		reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
	};

};

&devbus_bootcs {
	status = "okay";

	/* Device Bus parameters are required */

	/* Read parameters */
	devbus,bus-width    = <16>;
	devbus,turn-off-ps  = <60000>;
	devbus,badr-skew-ps = <0>;
	devbus,acc-first-ps = <124000>;
	devbus,acc-next-ps  = <248000>;
	devbus,rd-setup-ps  = <0>;
	devbus,rd-hold-ps   = <0>;

	/* Write parameters */
	devbus,sync-enable = <0>;
	devbus,wr-high-ps  = <60000>;
	devbus,wr-low-ps   = <60000>;
	devbus,ale-wr-ps   = <60000>;
};

&i2c0 {
	clock-frequency = <100000>;
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		marvell,nand-keep-config;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;
	};
};

&sdio {
	pinctrl-0 = <&sdio_pins>;
	pinctrl-names = "default";
	status = "okay";
	/* No CD or WP GPIOs */
	broken-cd;
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p64";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <20000000>;
		m25p,fast-read;

		partition@u-boot {
			reg = <0x00000000 0x00100000>;
			label = "u-boot";
		};
		partition@u-boot-env {
			reg = <0x00100000 0x00040000>;
			label = "u-boot-env";
		};
		partition@unused {
			reg = <0x00140000 0x00ec0000>;
			label = "unused";
		};

	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for DB-XC3-24G4XG board
 *
 * Copyright (C) 2016 Allied Telesis Labs
 *
 * Based on armada-xp-db.dts
 *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the default
 * 0xd0000000). The 0xf1000000 is the default used by the recent,
 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
 * boards were delivered with an older version of the bootloader that
 * left internal registers mapped at 0xd0000000. If you are in this
 * situation, you should either update your bootloader (preferred
 * solution) or the below Device Tree should be adjusted.
 */

/dts-v1/;
#include "armada-xp-98dx3336.dtsi"

/ {
	model = "DB-XC3-24G4XG";
	compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";

	chosen {
		bootargs = "console=ttyS0,115200 earlyprintk";
	};

	memory {
		device_type = "memory";
		reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
	};
};

&L2 {
	arm,parity-enable;
	marvell,ecc-enable;
};

&devbus_bootcs {
	status = "okay";

	/* Device Bus parameters are required */

	/* Read parameters */
	devbus,bus-width    = <16>;
	devbus,turn-off-ps  = <60000>;
	devbus,badr-skew-ps = <0>;
	devbus,acc-first-ps = <124000>;
	devbus,acc-next-ps  = <248000>;
	devbus,rd-setup-ps  = <0>;
	devbus,rd-hold-ps   = <0>;

	/* Write parameters */
	devbus,sync-enable = <0>;
	devbus,wr-high-ps  = <60000>;
	devbus,wr-low-ps   = <60000>;
	devbus,ale-wr-ps   = <60000>;
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&i2c0 {
	clock-frequency = <100000>;
	status = "okay";
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		marvell,nand-keep-config;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p64";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <20000000>;
		m25p,fast-read;

		partition@u-boot {
			reg = <0x00000000 0x00100000>;
			label = "u-boot";
		};
		partition@u-boot-env {
			reg = <0x00100000 0x00040000>;
			label = "u-boot-env";
		};
		partition@unused {
			reg = <0x00140000 0x00ec0000>;
			label = "unused";
		};

	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell Armada XP evaluation board
 * (DB-78460-BP)
 *
 * Copyright (C) 2012-2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
  *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the default
 * 0xd0000000). The 0xf1000000 is the default used by the recent,
 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
 * boards were delivered with an older version of the bootloader that
 * left internal registers mapped at 0xd0000000. If you are in this
 * situation, you should either update your bootloader (preferred
 * solution) or the below Device Tree should be adjusted.
 */

/dts-v1/;
#include "armada-xp-mv78460.dtsi"

/ {
	model = "Marvell Armada XP Evaluation Board";
	compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;

		devbus-bootcs {
			status = "okay";

			/* Device Bus parameters are required */

			/* Read parameters */
			devbus,bus-width    = <16>;
			devbus,turn-off-ps  = <60000>;
			devbus,badr-skew-ps = <0>;
			devbus,acc-first-ps = <124000>;
			devbus,acc-next-ps  = <248000>;
			devbus,rd-setup-ps  = <0>;
			devbus,rd-hold-ps   = <0>;

			/* Write parameters */
			devbus,sync-enable = <0>;
			devbus,wr-high-ps  = <60000>;
			devbus,wr-low-ps   = <60000>;
			devbus,ale-wr-ps   = <60000>;

			/* NOR 16 MiB */
			nor@0 {
				compatible = "cfi-flash";
				reg = <0 0x1000000>;
				bank-width = <2>;
			};
		};

		internal-regs {
			serial@12000 {
				status = "okay";
			};
			serial@12100 {
				status = "okay";
			};
			serial@12200 {
				status = "okay";
			};
			serial@12300 {
				status = "okay";
			};

			sata@a0000 {
				nr-ports = <2>;
				status = "okay";
			};

			ethernet@70000 {
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
				buffer-manager = <&bm>;
				bm,pool-long = <0>;
			};
			ethernet@74000 {
				status = "okay";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
				buffer-manager = <&bm>;
				bm,pool-long = <1>;
			};
			ethernet@30000 {
				status = "okay";
				phy = <&phy2>;
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <2>;
			};
			ethernet@34000 {
				status = "okay";
				phy = <&phy3>;
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <3>;
			};

			bm@c0000 {
				status = "okay";
			};

			mvsdio@d4000 {
				pinctrl-0 = <&sdio_pins>;
				pinctrl-names = "default";
				status = "okay";
				/* No CD or WP GPIOs */
				broken-cd;
			};

			usb@50000 {
				status = "okay";
			};

			usb@51000 {
				status = "okay";
			};

			usb@52000 {
				status = "okay";
			};

			nand-controller@d0000 {
				status = "okay";

				nand@0 {
					reg = <0>;
					label = "pxa3xx_nand-0";
					nand-rb = <0>;
					nand-on-flash-bbt;

					partitions {
						compatible = "fixed-partitions";
						#address-cells = <1>;
						#size-cells = <1>;

						partition@0 {
							label = "U-Boot";
							reg = <0 0x800000>;
						};
						partition@800000 {
							label = "Linux";
							reg = <0x800000 0x800000>;
						};
						partition@1000000 {
							label = "Filesystem";
							reg = <0x1000000 0x3f000000>;
						};
					};
				};
			};
		};

		bm-bppi {
			status = "okay";
		};
	};
};

&pciec {
	status = "okay";

	/*
	 * All 6 slots are physically present as
	 * standard PCIe slots on the board.
	 */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};
	pcie@2,0 {
		/* Port 0, Lane 1 */
		status = "okay";
	};
	pcie@3,0 {
		/* Port 0, Lane 2 */
		status = "okay";
	};
	pcie@4,0 {
		/* Port 0, Lane 3 */
		status = "okay";
	};
	pcie@9,0 {
		/* Port 2, Lane 0 */
		status = "okay";
	};
	pcie@a,0 {
		/* Port 3, Lane 0 */
		status = "okay";
	};
};

&mdio {
	phy0: ethernet-phy@0 {
		reg = <0>;
	};

	phy1: ethernet-phy@1 {
		reg = <1>;
	};

	phy2: ethernet-phy@2 {
		reg = <25>;
	};

	phy3: ethernet-phy@3 {
		reg = <27>;
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p64", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <20000000>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell Armada XP development board
 * (DB-MV784MP-GP)
 *
 * Copyright (C) 2013-2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the default
 * 0xd0000000). The 0xf1000000 is the default used by the recent,
 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
 * boards were delivered with an older version of the bootloader that
 * left internal registers mapped at 0xd0000000. If you are in this
 * situation, you should either update your bootloader (preferred
 * solution) or the below Device Tree should be adjusted.
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-xp-mv78460.dtsi"

/ {
	model = "Marvell Armada XP Development Board DB-MV784MP-GP";
	compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		/*
                 * 8 GB of plug-in RAM modules by default.The amount
                 * of memory available can be changed by the
                 * bootloader according the size of the module
                 * actually plugged. However, memory between
                 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
                 * the address range used for I/O (internal registers,
                 * MBus windows).
		 */
		reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
		      <0x00000001 0x00000000 0x00000001 0x00000000>;
	};

	cpus {
		pm_pic {
			ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
				     <&gpio0 17 GPIO_ACTIVE_LOW>,
				     <&gpio0 18 GPIO_ACTIVE_LOW>;
		};
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;

		devbus-bootcs {
			status = "okay";

			/* Device Bus parameters are required */

			/* Read parameters */
			devbus,bus-width    = <16>;
			devbus,turn-off-ps  = <60000>;
			devbus,badr-skew-ps = <0>;
			devbus,acc-first-ps = <124000>;
			devbus,acc-next-ps  = <248000>;
			devbus,rd-setup-ps  = <0>;
			devbus,rd-hold-ps   = <0>;

			/* Write parameters */
			devbus,sync-enable = <0>;
			devbus,wr-high-ps  = <60000>;
			devbus,wr-low-ps   = <60000>;
			devbus,ale-wr-ps   = <60000>;

			/* NOR 16 MiB */
			nor@0 {
				compatible = "cfi-flash";
				reg = <0 0x1000000>;
				bank-width = <2>;
			};
		};

		internal-regs {
			serial@12000 {
				status = "okay";
			};
			serial@12100 {
				status = "okay";
			};
			serial@12200 {
				status = "okay";
			};
			serial@12300 {
				status = "okay";
			};
			pinctrl {
				pinctrl-0 = <&pic_pins>;
				pinctrl-names = "default";
				pic_pins: pic-pins-0 {
					marvell,pins = "mpp16", "mpp17",
						       "mpp18";
					marvell,function = "gpio";
				};
			};
			sata@a0000 {
				nr-ports = <2>;
				status = "okay";
			};

			ethernet@70000 {
				status = "okay";
				phy = <&phy0>;
				phy-mode = "qsgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <0>;
			};
			ethernet@74000 {
				status = "okay";
				phy = <&phy1>;
				phy-mode = "qsgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <1>;
			};
			ethernet@30000 {
				status = "okay";
				phy = <&phy2>;
				phy-mode = "qsgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <2>;
			};
			ethernet@34000 {
				status = "okay";
				phy = <&phy3>;
				phy-mode = "qsgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <3>;
			};

			/* Front-side USB slot */
			usb@50000 {
				status = "okay";
			};

			/* Back-side USB slot */
			usb@51000 {
				status = "okay";
			};

			bm@c0000 {
				status = "okay";
			};

			nand-controller@d0000 {
				status = "okay";

				nand@0 {
					reg = <0>;
					label = "pxa3xx_nand-0";
					nand-rb = <0>;
					nand-on-flash-bbt;
				};
			};
		};

		bm-bppi {
			status = "okay";
		};
	};
};

&pciec {
	status = "okay";

	/*
	 * The 3 slots are physically present as
	 * standard PCIe slots on the board.
	 */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};
	pcie@9,0 {
		/* Port 2, Lane 0 */
		status = "okay";
	};
	pcie@a,0 {
		/* Port 3, Lane 0 */
		status = "okay";
	};
};

&mdio {
	phy0: ethernet-phy@0 {
		reg = <16>;
	};

	phy1: ethernet-phy@1 {
		reg = <17>;
	};

	phy2: ethernet-phy@2 {
		reg = <18>;
	};

	phy3: ethernet-phy@3 {
		reg = <19>;
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "n25q128a13", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <108000000>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Lenovo Iomega ix4-300d
 *
 * Copyright (C) 2014, Benoit Masson <yahoo@perenite.com>
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-xp-mv78230.dtsi"

/ {
	model = "Lenovo Iomega ix4-300d";
	compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230",
		     "marvell,armadaxp", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0 0x00000000 0 0x20000000>; /* 512MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
			MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
			MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
			MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;

		internal-regs {
			serial@12000 {
				status = "okay";
			};

			ethernet@70000 {
				pinctrl-0 = <&ge0_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};

			ethernet@74000 {
				pinctrl-0 = <&ge1_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
			};

			usb@50000 {
				status = "okay";
			};

			usb@51000 {
				status = "okay";
			};

			i2c@11000 {
				clock-frequency = <400000>;
				status = "okay";

				adt7473@2e {
					compatible = "adi,adt7473";
					reg = <0x2e>;
				};

				eeprom@50 {
					compatible = "atmel,24c64";
					reg = <0x50>;
				};

				pcf8563@51 {
					compatible = "nxp,pcf8563";
					reg = <0x51>;
				};

			};

			nand-controller@d0000 {
				status = "okay";

				nand@0 {
					reg = <0>;
					label = "pxa3xx_nand-0";
					nand-rb = <0>;
					nand-on-flash-bbt;

					partitions {
						compatible = "fixed-partitions";
						#address-cells = <1>;
						#size-cells = <1>;

						partition@0 {
							label = "u-boot";
							reg = <0x00000000 0x000e0000>;
							read-only;
						};

						partition@e0000 {
							label = "u-boot-env";
							reg = <0x000e0000 0x00020000>;
							read-only;
						};

						partition@100000 {
							label = "u-boot-env2";
							reg = <0x00100000 0x00020000>;
							read-only;
						};

						partition@120000 {
							label = "zImage";
							reg = <0x00120000 0x00400000>;
						};

						partition@520000 {
							label = "initrd";
							reg = <0x00520000 0x00400000>;
						};

						partition@e00000 {
							label = "boot";
							reg = <0x00e00000 0x3f200000>;
						};
					};
				};
			};
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&power_button_pin &reset_button_pin
			&select_button_pin &scroll_button_pin>;
		pinctrl-names = "default";

		power-button {
			label = "Power Button";
			linux,code = <KEY_POWER>;
			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		};

		reset-button {
			label = "Reset Button";
			linux,code = <KEY_RESTART>;
			gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
		};

		select-button {
			label = "Select Button";
			linux,code = <BTN_SELECT>;
			gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
		};

		scroll-button {
			label = "Scroll Button";
			linux,code = <KEY_SCROLLDOWN>;
			gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
		};
	};

	spi-3 {
		compatible = "spi-gpio";
		status = "okay";
		gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>;
		gpio-mosi = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/
		cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
		num-chipselects = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		gpio_spi: gpio_spi@0 {
			compatible = "fairchild,74hc595";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0>;
			registers-number = <1>;
			spi-max-frequency = <100000>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&hdd_led_pin>;
		pinctrl-names = "default";

		hdd-led {
			label = "ix4-300d:hdd:blue";
			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		power-led {
			label = "ix4-300d:power:white";
			gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>;
			/* init blinking while booting */
			linux,default-trigger = "timer";
			default-state = "on";
		};

		sysfail-led {
			label = "ix4-300d:sysfail:red";
			gpios = <&gpio_spi 2 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		sys-led {
			label = "ix4-300d:sys:blue";
			gpios = <&gpio_spi 3 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		hddfail-led {
			label = "ix4-300d:hddfail:red";
			gpios = <&gpio_spi 4 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

	};

	/*
	 * Warning: you need both eth1 & 0 PHY initialized (i.e having
	 * them up does the tweak) for poweroff to shutdown otherwise it
	 * reboots
	 */
	gpio-poweroff {
		compatible = "gpio-poweroff";
		pinctrl-0 = <&poweroff_pin>;
		pinctrl-names = "default";
		gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
	};
};
&pciec {
	status = "okay";

	/* Quad port sata: Marvell 88SX7042 */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};

	/* USB 3.0 xHCI controller: NEC D720200F1 */
	pcie@5,0 {
		/* Port 1, Lane 0 */
		status = "okay";
	};
};

&mdio {
	phy0: ethernet-phy@0 { /* Marvell 88E1318 */
		reg = <0>;
	};

	phy1: ethernet-phy@1 { /* Marvell 88E1318 */
		reg = <1>;
	};
};

&pinctrl {
	poweroff_pin: poweroff-pin {
		marvell,pins = "mpp24";
		marvell,function = "gpio";
	};

	power_button_pin: power-button-pin {
		marvell,pins = "mpp44";
		marvell,function = "gpio";
	};

	reset_button_pin: reset-button-pin {
		marvell,pins = "mpp45";
		marvell,function = "gpio";
	};
	select_button_pin: select-button-pin {
		marvell,pins = "mpp41";
		marvell,function = "gpio";
	};

	scroll_button_pin: scroll-button-pin {
		marvell,pins = "mpp42";
		marvell,function = "gpio";
	};

	hdd_led_pin: hdd-led-pin {
		marvell,pins = "mpp26";
		marvell,function = "gpio";
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for the Linksys WRT1900AC (Mamba).
 *
 * Note: this board is shipped with a new generation boot loader that
 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
 * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option should be
 * used.
 *
 * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
 *
 * Based on armada-xp-axpwifiap.dts:
 *
 *     Copyright (C) 2013 Marvell
 *
 *     Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-xp-mv78230.dtsi"

/ {
	model = "Linksys WRT1900AC";
	compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
		     "marvell,armadaxp", "marvell,armada-370-xp";

	chosen {
		bootargs = "console=ttyS0,115200";
		stdout-path = &uart0;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;

		internal-regs {

			rtc@10300 {
				/* No crystal connected to the internal RTC */
				status = "disabled";
			};

			/* J10: VCC, NC, RX, NC, TX, GND  */
			serial@12000 {
				status = "okay";
			};

			sata@a0000 {
				nr-ports = <1>;
				status = "okay";
			};

			ethernet@70000 {
				pinctrl-0 = <&ge0_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy-mode = "rgmii-id";
				buffer-manager = <&bm>;
				bm,pool-long = <0>;
				bm,pool-short = <1>;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			ethernet@74000 {
				pinctrl-0 = <&ge1_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy-mode = "rgmii-id";
				buffer-manager = <&bm>;
				bm,pool-long = <2>;
				bm,pool-short = <3>;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			/* USB part of the eSATA/USB 2.0 port */
			usb@50000 {
				status = "okay";
			};

			i2c@11000 {
				status = "okay";
				clock-frequency = <100000>;

				tmp421@4c {
					compatible = "ti,tmp421";
					reg = <0x4c>;
				};

				tlc59116@68 {
					#address-cells = <1>;
					#size-cells = <0>;
					#gpio-cells = <2>;
					compatible = "ti,tlc59116";
					reg = <0x68>;

					wan_amber@0 {
						label = "mamba:amber:wan";
						reg = <0x0>;
					};

					wan_white@1 {
						label = "mamba:white:wan";
						reg = <0x1>;
					};

					wlan_2g@2 {
						label = "mamba:white:wlan_2g";
						reg = <0x2>;
					};

					wlan_5g@3 {
						label = "mamba:white:wlan_5g";
						reg = <0x3>;
					};

					esata@4 {
						label = "mamba:white:esata";
						reg = <0x4>;
						linux,default-trigger = "disk-activity";
					};

					usb2@5 {
						label = "mamba:white:usb2";
						reg = <0x5>;
					};

					usb3_1@6 {
						label = "mamba:white:usb3_1";
						reg = <0x6>;
					};

					usb3_2@7 {
						label = "mamba:white:usb3_2";
						reg = <0x7>;
					};

					wps_white@8 {
						label = "mamba:white:wps";
						reg = <0x8>;
					};

					wps_amber@9 {
						label = "mamba:amber:wps";
						reg = <0x9>;
					};
				};
			};

			bm@c8000 {
				status = "okay";
			};
		};

		bm-bppi {
			status = "okay";
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&keys_pin>;
		pinctrl-names = "default";

		button-wps {
			label = "WPS";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
		};

		button-reset {
			label = "Factory Reset Button";
			linux,code = <KEY_RESTART>;
			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&power_led_pin>;
		pinctrl-names = "default";

		led-power {
			label = "mamba:white:power";
			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};
	};

	pwm_fan {
		/* SUNON HA4010V4-0000-C99 */

		compatible = "pwm-fan";
		pwms = <&gpio0 24 4000>;
	};
};

&pciec {
	status = "okay";

	/* Etron EJ168 USB 3.0 controller */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};

	/* First mini-PCIe port */
	pcie@2,0 {
		/* Port 0, Lane 1 */
		status = "okay";
	};

	/* Second mini-PCIe port */
	pcie@3,0 {
		/* Port 0, Lane 3 */
		status = "okay";
	};
};

&pinctrl {

	keys_pin: keys-pin {
		marvell,pins = "mpp32", "mpp33";
		marvell,function = "gpio";
	};

	power_led_pin: power-led-pin {
		marvell,pins = "mpp40";
		marvell,function = "gpio";
	};

	gpio_fan_pin: gpio-fan-pin {
		marvell,pins = "mpp24";
		marvell,function = "gpio";
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "everspin,mr25h256";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <40000000>;
	};
};

&mdio {
	status = "okay";

	switch@0 {
		compatible = "marvell,mv88e6085";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				label = "lan4";
			};

			port@1 {
				reg = <1>;
				label = "lan3";
			};

			port@2 {
				reg = <2>;
				label = "lan2";
			};

			port@3 {
				reg = <3>;
				label = "lan1";
			};

			port@4 {
				reg = <4>;
				label = "internet";
			};

			port@5 {
				reg = <5>;
				label = "cpu";
				ethernet = <&eth0>;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
		};
	};
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		marvell,nand-keep-config;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0000000 0x100000>;  /* 1MB */
				read-only;
			};

			partition@100000 {
				label = "u_env";
				reg = <0x100000 0x40000>;    /* 256KB */
			};

			partition@140000 {
				label = "s_env";
				reg = <0x140000 0x40000>;    /* 256KB */
			};

			partition@900000 {
				label = "devinfo";
				reg = <0x900000 0x100000>;   /* 1MB */
				read-only;
			};

			/* kernel1 overlaps with rootfs1 by design */
			partition@a00000 {
				label = "kernel1";
				reg = <0xa00000 0x2800000>;  /* 40MB */
			};

			partition@d00000 {
				label = "rootfs1";
				reg = <0xd00000 0x2500000>;  /* 37MB */
			};

			/* kernel2 overlaps with rootfs2 by design */
			partition@3200000 {
				label = "kernel2";
				reg = <0x3200000 0x2800000>; /* 40MB */
			};

			partition@3500000 {
				label = "rootfs2";
				reg = <0x3500000 0x2500000>; /* 37MB */
			};

			/*
			 * 38MB, last MB is for the BBT, not writable
			 */
			partition@5a00000 {
				label = "syscfg";
				reg = <0x5a00000 0x2600000>;
			};

			/*
			 * Unused area between "s_env" and "devinfo".
			 * Moved here because otherwise the renumbered
			 * partitions would break the bootloader
			 * supplied bootargs
			 */
			partition@180000 {
				label = "unused_area";
				reg = <0x180000 0x780000>;   /* 7.5MB */
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell Armada XP Matrix board
 *
 * Copyright (C) 2013 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 */

/dts-v1/;
#include "armada-xp-mv78460.dtsi"

/ {
	model = "Marvell Armada XP Matrix Board";
	compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		/*
		 * This board has 4 GB of RAM, but the last 256 MB of
		 * RAM are not usable due to the overlap with the MBus
		 * Window address range
		 */
		reg = <0 0x00000000 0 0xf0000000>;
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;

		internal-regs {
			serial@12000 {
				status = "okay";
			};
			serial@12100 {
				status = "okay";
			};
			serial@12200 {
				status = "okay";
			};
			serial@12300 {
				status = "okay";
			};

			sata@a0000 {
				nr-ports = <2>;
				status = "okay";
			};

			ethernet@30000 {
				status = "okay";
				phy-mode = "sgmii";
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			usb@50000 {
				status = "okay";
			};
		};
	};
};

&pciec {
	status = "okay";

	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * Contains definitions specific to the Armada XP MV78230 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-xp.dtsi"

/ {
	model = "Marvell Armada XP MV78230 SoC";
	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-xp-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
			clock-latency = <1000000>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
			clock-latency = <1000000>;
		};
	};

	soc {
		/*
		 * MV78230 has 2 PCIe units Gen2.0: One unit can be
		 * configured as x4 or quad x1 lanes. One unit is
		 * x1 only.
		 */
		pciec: pcie@82000000 {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
				0x82000000 0x3 0       MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
				0x81000000 0x3 0       MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
				0x82000000 0x4 0       MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
				0x81000000 0x4 0       MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
				0x82000000 0x5 0       MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
				0x81000000 0x5 0       MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */>;

			pcie1: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 58>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
						<0 0 0 2 &pcie1_intc 1>,
						<0 0 0 3 &pcie1_intc 2>,
						<0 0 0 4 &pcie1_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";

				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie2: pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 59>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
						<0 0 0 2 &pcie2_intc 1>,
						<0 0 0 3 &pcie2_intc 2>,
						<0 0 0 4 &pcie2_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";

				pcie2_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie3: pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 60>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
						<0 0 0 2 &pcie3_intc 1>,
						<0 0 0 3 &pcie3_intc 2>,
						<0 0 0 4 &pcie3_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 7>;
				status = "disabled";

				pcie3_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie4: pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 61>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie4_intc 0>,
						<0 0 0 2 &pcie4_intc 1>,
						<0 0 0 3 &pcie4_intc 2>,
						<0 0 0 4 &pcie4_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 8>;
				status = "disabled";

				pcie4_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie5: pcie@5,0 {
				device_type = "pci";
				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
				reg = <0x2800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 62>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie5_intc 0>,
						<0 0 0 2 &pcie5_intc 1>,
						<0 0 0 3 &pcie5_intc 2>,
						<0 0 0 4 &pcie5_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";

				pcie5_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};
		};

		internal-regs {
			gpio0: gpio@18100 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18100 0x40>, <0x181c0 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
				clocks = <&coreclk 0>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18140 0x40>, <0x181c8 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <17>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>, <88>, <89>;
				clocks = <&coreclk 0>;
			};
		};
	};
};

&pinctrl {
	compatible = "marvell,mv78230-pinctrl";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * Contains definitions specific to the Armada XP MV78260 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-xp.dtsi"

/ {
	model = "Marvell Armada XP MV78260 SoC";
	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-xp-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
			clock-latency = <1000000>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
			clock-latency = <1000000>;
		};
	};

	soc {
		/*
		 * MV78260 has 3 PCIe units Gen2.0: Two units can be
		 * configured as x4 or quad x1 lanes. One unit is
		 * x4 only.
		 */
		pciec: pcie@82000000 {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
				0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
				0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
				0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
				0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
				0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
				0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
				0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
				0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
				0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */

				0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
				0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
				0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
				0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
				0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
				0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
				0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
				0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */

				0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
				0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */>;

			pcie1: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 58>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
						<0 0 0 2 &pcie1_intc 1>,
						<0 0 0 3 &pcie1_intc 2>,
						<0 0 0 4 &pcie1_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";

				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie2: pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 59>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
						<0 0 0 2 &pcie2_intc 1>,
						<0 0 0 3 &pcie2_intc 2>,
						<0 0 0 4 &pcie2_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";

				pcie2_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie3: pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 60>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
						<0 0 0 2 &pcie3_intc 1>,
						<0 0 0 3 &pcie3_intc 2>,
						<0 0 0 4 &pcie3_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 7>;
				status = "disabled";

				pcie3_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie4: pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 61>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie4_intc 0>,
						<0 0 0 2 &pcie4_intc 1>,
						<0 0 0 3 &pcie4_intc 2>,
						<0 0 0 4 &pcie4_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 8>;
				status = "disabled";

				pcie4_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie5: pcie@5,0 {
				device_type = "pci";
				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
				reg = <0x2800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 62>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie5_intc 0>,
						<0 0 0 2 &pcie5_intc 1>,
						<0 0 0 3 &pcie5_intc 2>,
						<0 0 0 4 &pcie5_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";

				pcie5_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie6: pcie@6,0 {
				device_type = "pci";
				assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
				reg = <0x3000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 63>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
					  0x81000000 0 0 0x81000000 0x6 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie6_intc 0>,
						<0 0 0 2 &pcie6_intc 1>,
						<0 0 0 3 &pcie6_intc 2>,
						<0 0 0 4 &pcie6_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 10>;
				status = "disabled";

				pcie6_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie7: pcie@7,0 {
				device_type = "pci";
				assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
				reg = <0x3800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 64>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
					  0x81000000 0 0 0x81000000 0x7 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie7_intc 0>,
						<0 0 0 2 &pcie7_intc 1>,
						<0 0 0 3 &pcie7_intc 2>,
						<0 0 0 4 &pcie7_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 11>;
				status = "disabled";

				pcie7_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie8: pcie@8,0 {
				device_type = "pci";
				assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
				reg = <0x4000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 65>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
					  0x81000000 0 0 0x81000000 0x8 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie8_intc 0>,
						<0 0 0 2 &pcie8_intc 1>,
						<0 0 0 3 &pcie8_intc 2>,
						<0 0 0 4 &pcie8_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 12>;
				status = "disabled";

				pcie8_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie9: pcie@9,0 {
				device_type = "pci";
				assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
				reg = <0x4800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 99>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
					  0x81000000 0 0 0x81000000 0x9 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie9_intc 0>,
						<0 0 0 2 &pcie9_intc 1>,
						<0 0 0 3 &pcie9_intc 2>,
						<0 0 0 4 &pcie9_intc 3>;
				marvell,pcie-port = <2>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 26>;
				status = "disabled";

				pcie9_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};
		};

		internal-regs {
			gpio0: gpio@18100 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18100 0x40>, <0x181c0 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
				clocks = <&coreclk 0>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18140 0x40>, <0x181c8 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>, <88>, <89>, <90>;
				clocks = <&coreclk 0>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <3>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <91>;
			};

			eth3: ethernet@34000 {
				compatible = "marvell,armada-xp-neta";
				reg = <0x34000 0x4000>;
				interrupts = <14>;
				clocks = <&gateclk 1>;
				status = "disabled";
			};
		};
	};
};

&pinctrl {
	compatible = "marvell,mv78260-pinctrl";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * Contains definitions specific to the Armada XP MV78460 SoC that are not
 * common to all Armada XP SoCs.
 */

#include "armada-xp.dtsi"

/ {
	model = "Marvell Armada XP MV78460 SoC";
	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-xp-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <0>;
			clocks = <&cpuclk 0>;
			clock-latency = <1000000>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <1>;
			clocks = <&cpuclk 1>;
			clock-latency = <1000000>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <2>;
			clocks = <&cpuclk 2>;
			clock-latency = <1000000>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "marvell,sheeva-v7";
			reg = <3>;
			clocks = <&cpuclk 3>;
			clock-latency = <1000000>;
		};
	};

	soc {
		/*
		 * MV78460 has 4 PCIe units Gen2.0: Two units can be
		 * configured as x4 or quad x1 lanes. Two units are
		 * x4/x1.
		 */
		pciec: pcie@82000000 {
			compatible = "marvell,armada-xp-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
				0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
				0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
				0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
				0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
				0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
				0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
				0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
				0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
				0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
				0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
				0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */

				0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
				0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
				0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
				0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
				0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
				0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
				0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
				0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */

				0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
				0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */

				0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
				0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;

			pcie1: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 58>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
						<0 0 0 2 &pcie1_intc 1>,
						<0 0 0 3 &pcie1_intc 2>,
						<0 0 0 4 &pcie1_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";

				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie2: pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 59>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
						<0 0 0 2 &pcie2_intc 1>,
						<0 0 0 3 &pcie2_intc 2>,
						<0 0 0 4 &pcie2_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";

				pcie2_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie3: pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 60>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
						<0 0 0 2 &pcie3_intc 1>,
						<0 0 0 3 &pcie3_intc 2>,
						<0 0 0 4 &pcie3_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 7>;
				status = "disabled";

				pcie3_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie4: pcie@4,0 {
				device_type = "pci";
				assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
				reg = <0x2000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 61>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie4_intc 0>,
						<0 0 0 2 &pcie4_intc 1>,
						<0 0 0 3 &pcie4_intc 2>,
						<0 0 0 4 &pcie4_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 8>;
				status = "disabled";

				pcie4_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie5: pcie@5,0 {
				device_type = "pci";
				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
				reg = <0x2800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 62>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
					  0x81000000 0 0 0x81000000 0x5 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie5_intc 0>,
						<0 0 0 2 &pcie5_intc 1>,
						<0 0 0 3 &pcie5_intc 2>,
						<0 0 0 4 &pcie5_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";

				pcie5_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie6: pcie@6,0 {
				device_type = "pci";
				assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
				reg = <0x3000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 63>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
					  0x81000000 0 0 0x81000000 0x6 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie6_intc 0>,
						<0 0 0 2 &pcie6_intc 1>,
						<0 0 0 3 &pcie6_intc 2>,
						<0 0 0 4 &pcie6_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 10>;
				status = "disabled";

				pcie6_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie7: pcie@7,0 {
				device_type = "pci";
				assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
				reg = <0x3800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 64>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
					  0x81000000 0 0 0x81000000 0x7 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie7_intc 0>,
						<0 0 0 2 &pcie7_intc 1>,
						<0 0 0 3 &pcie7_intc 2>,
						<0 0 0 4 &pcie7_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <2>;
				clocks = <&gateclk 11>;
				status = "disabled";

				pcie7_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie8: pcie@8,0 {
				device_type = "pci";
				assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
				reg = <0x4000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 65>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
					  0x81000000 0 0 0x81000000 0x8 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie8_intc 0>,
						<0 0 0 2 &pcie8_intc 1>,
						<0 0 0 3 &pcie8_intc 2>,
						<0 0 0 4 &pcie8_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <3>;
				clocks = <&gateclk 12>;
				status = "disabled";

				pcie8_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie9: pcie@9,0 {
				device_type = "pci";
				assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
				reg = <0x4800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 99>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
					  0x81000000 0 0 0x81000000 0x9 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie9_intc 0>,
						<0 0 0 2 &pcie9_intc 1>,
						<0 0 0 3 &pcie9_intc 2>,
						<0 0 0 4 &pcie9_intc 3>;
				marvell,pcie-port = <2>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 26>;
				status = "disabled";

				pcie9_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie10: pcie@a,0 {
				device_type = "pci";
				assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
				reg = <0x5000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 103>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
					  0x81000000 0 0 0x81000000 0xa 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie10_intc 0>,
						<0 0 0 2 &pcie10_intc 1>,
						<0 0 0 3 &pcie10_intc 2>,
						<0 0 0 4 &pcie10_intc 3>;
				marvell,pcie-port = <3>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 27>;
				status = "disabled";

				pcie10_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};
		};

		internal-regs {
			gpio0: gpio@18100 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18100 0x40>, <0x181c0 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
				clocks = <&coreclk 0>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18140 0x40>, <0x181c8 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>, <88>, <89>, <90>;
				clocks = <&coreclk 0>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <3>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <91>;
			};

			eth3: ethernet@34000 {
				compatible = "marvell,armada-xp-neta";
				reg = <0x34000 0x4000>;
				interrupts = <14>;
				clocks = <&gateclk 1>;
				status = "disabled";
			};
		};
	};
};

&pinctrl {
	compatible = "marvell,mv78460-pinctrl";
};