code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) STMicroelectronics 2019.
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STM32 GPIO and Pin Mux/Config controller

maintainers:
  - Alexandre TORGUE <alexandre.torgue@foss.st.com>

description: |
  STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
  controller. It controls the input/output settings on the available pins and
  also provides ability to multiplex and configure the output of various
  on-chip controllers onto these pads.

properties:
  compatible:
    enum:
      - st,stm32f429-pinctrl
      - st,stm32f469-pinctrl
      - st,stm32f746-pinctrl
      - st,stm32f769-pinctrl
      - st,stm32h743-pinctrl
      - st,stm32mp135-pinctrl
      - st,stm32mp157-pinctrl
      - st,stm32mp157-z-pinctrl

  '#address-cells':
    const: 1
  '#size-cells':
    const: 1

  ranges: true
  pins-are-numbered:
    $ref: /schemas/types.yaml#/definitions/flag
    deprecated: true
  hwlocks: true

  interrupts:
    maxItems: 1

  st,syscfg:
    description: Phandle+args to the syscon node which includes IRQ mux selection.
    $ref: "/schemas/types.yaml#/definitions/phandle-array"
    items:
      - items:
          - description: syscon node which includes IRQ mux selection
          - description: The offset of the IRQ mux selection register
          - description: The field mask of IRQ mux, needed if different of 0xf

  st,package:
    description:
      Indicates the SOC package used.
      More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2, 4, 8]

patternProperties:
  '^gpio@[0-9a-f]*$':
    type: object
    additionalProperties: false
    properties:
      gpio-controller: true
      '#gpio-cells':
        const: 2
      interrupt-controller: true
      '#interrupt-cells':
        const: 2

      reg:
        maxItems: 1
      clocks:
        maxItems: 1
      resets:
        maxItems: 1
      gpio-line-names: true
      gpio-ranges:
        minItems: 1
        maxItems: 16
      ngpios:
        description:
          Number of available gpios in a bank.
        minimum: 1
        maximum: 16

      st,bank-name:
        description:
          Should be a name string for this bank as specified in the datasheet.
        $ref: "/schemas/types.yaml#/definitions/string"
        enum:
          - GPIOA
          - GPIOB
          - GPIOC
          - GPIOD
          - GPIOE
          - GPIOF
          - GPIOG
          - GPIOH
          - GPIOI
          - GPIOJ
          - GPIOK
          - GPIOZ

      st,bank-ioport:
        description:
          Should correspond to the EXTI IOport selection (EXTI line used
          to select GPIOs as interrupts).
        $ref: "/schemas/types.yaml#/definitions/uint32"
        minimum: 0
        maximum: 11

    patternProperties:
      "^(.+-hog(-[0-9]+)?)$":
        type: object
        required:
          - gpio-hog

    required:
      - gpio-controller
      - '#gpio-cells'
      - reg
      - clocks
      - st,bank-name

  '-[0-9]*$':
    type: object
    additionalProperties: false

    patternProperties:
      '^pins':
        type: object
        additionalProperties: false
        description: |
          A pinctrl node should contain at least one subnode representing the
          pinctrl group available on the machine. Each subnode will list the
          pins it needs, and how they should be configured, with regard to muxer
          configuration, pullups, drive, output high/low and output speed.
        properties:
          pinmux:
            $ref: "/schemas/types.yaml#/definitions/uint32-array"
            description: |
              Integer array, represents gpio pin number and mux setting.
              Supported pin number and mux varies for different SoCs, and are
              defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
              These defines are calculated as: ((port * 16 + line) << 8) | function
              With:
              - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
              - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
              - function: The function number, can be:
              * 0 : GPIO
              * 1 : Alternate Function 0
              * 2 : Alternate Function 1
              * 3 : Alternate Function 2
              * ...
              * 16 : Alternate Function 15
              * 17 : Analog
              To simplify the usage, macro is available to generate "pinmux" field.
              This macro is available here:
                - include/dt-bindings/pinctrl/stm32-pinfunc.h
              Some examples of using macro:
               /* GPIO A9 set as alernate function 2 */
               ... {
                          pinmux = <STM32_PINMUX('A', 9, AF2)>;
               };
               /* GPIO A9 set as GPIO  */
               ... {
                          pinmux = <STM32_PINMUX('A', 9, GPIO)>;
               };
               /* GPIO A9 set as analog */
               ... {
                          pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
               };

          bias-disable:
            type: boolean
          bias-pull-down:
            type: boolean
          bias-pull-up:
            type: boolean
          drive-push-pull:
            type: boolean
          drive-open-drain:
            type: boolean
          output-low:
            type: boolean
          output-high:
            type: boolean
          slew-rate:
            description: |
              0: Low speed
              1: Medium speed
              2: Fast speed
              3: High speed
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [0, 1, 2, 3]

        required:
          - pinmux

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - '#address-cells'
  - '#size-cells'
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/pinctrl/stm32-pinfunc.h>
    #include <dt-bindings/mfd/stm32f4-rcc.h>
    //Example 1
      pinctrl@40020000 {
              #address-cells = <1>;
              #size-cells = <1>;
              compatible = "st,stm32f429-pinctrl";
              ranges = <0 0x40020000 0x3000>;

              gpioa: gpio@0 {
                      gpio-controller;
                      #gpio-cells = <2>;
                      reg = <0x0 0x400>;
                      resets = <&reset_ahb1 0>;
                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
                      st,bank-name = "GPIOA";
              };
       };

    //Example 2 (using gpio-ranges)
      pinctrl@50020000 {
              #address-cells = <1>;
              #size-cells = <1>;
              compatible = "st,stm32f429-pinctrl";
              ranges = <0 0x50020000 0x3000>;

              gpiob: gpio@1000 {
                      gpio-controller;
                      #gpio-cells = <2>;
                      reg = <0x1000 0x400>;
                      resets = <&reset_ahb1 0>;
                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
                      st,bank-name = "GPIOB";
                      gpio-ranges = <&pinctrl 0 0 16>;
              };

              gpioc: gpio@2000 {
                      gpio-controller;
                      #gpio-cells = <2>;
                      reg = <0x2000 0x400>;
                      resets = <&reset_ahb1 0>;
                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
                      st,bank-name = "GPIOC";
                      ngpios = <5>;
                      gpio-ranges = <&pinctrl 0 16 3>,
                                    <&pinctrl 14 30 2>;
              };
      };

    //Example 3 pin groups
      pinctrl {
        usart1_pins_a: usart1-0 {
                pins1 {
                        pinmux = <STM32_PINMUX('A', 9, AF7)>;
                        bias-disable;
                        drive-push-pull;
                        slew-rate = <0>;
                };
                pins2 {
                        pinmux = <STM32_PINMUX('A', 10, AF7)>;
                        bias-disable;
                };
        };
    };

    usart1 {
                pinctrl-0 = <&usart1_pins_a>;
                pinctrl-names = "default";
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7100 Pin Controller

description: |
  Bindings for the JH7100 RISC-V SoC from StarFive Ltd.

  Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]
  and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have
  configurable bias, drive strength, schmitt trigger etc. The SoC has an
  interesting 2-layered approach to pin muxing best illustrated by the diagram
  below.

                          Signal group 0, 1, ... or 6
                                 ___|___
                                |       |
    LCD output -----------------|       |
    CMOS Camera interface ------|       |--- PAD_GPIO[0]
    Ethernet PHY interface -----|  MUX  |--- PAD_GPIO[1]
      ...                       |       |      ...
                                |       |--- PAD_GPIO[63]
     -------- GPIO0 ------------|       |
    |  -------|-- GPIO1 --------|       |--- PAD_FUNC_SHARE[0]
    | |       |   |             |       |--- PAD_FUNC_SHARE[1]
    | |       |   |  ...        |       |       ...
    | |       |   |             |       |--- PAD_FUNC_SHARE[141]
    | |  -----|---|-- GPIO63 ---|       |
    | | |     |   |   |          -------
    UART0     UART1 --

  The big MUX in the diagram only has 7 different ways of mapping peripherals
  on the left to pins on the right. StarFive calls the 7 configurations "signal
  groups".
  However some peripherals have their I/O go through the 64 "GPIOs". The
  diagram only shows UART0 and UART1, but this also includes a number of other
  UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64
  GPIOs such that any GPIO can be set up to be controlled by any of the
  peripherals.
  Note that signal group 0 doesn't map any of the GPIOs to pins, and only
  signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63].

maintainers:
  - Emil Renner Berthing <kernel@esmil.dk>
  - Drew Fustini <drew@beagleboard.org>

properties:
  compatible:
    const: starfive,jh7100-pinctrl

  reg:
    minItems: 2
    maxItems: 2

  reg-names:
    items:
      - const: gpio
      - const: padctl

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  gpio-controller: true

  "#gpio-cells":
    const: 2

  interrupts:
    maxItems: 1
    description: The GPIO parent interrupt.

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  starfive,signal-group:
    description: |
      Select one of the 7 signal groups. If this property is not set it
      defaults to the configuration already chosen by the earlier boot stages.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2, 3, 4, 5, 6]

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - gpio-controller
  - "#gpio-cells"
  - interrupts
  - interrupt-controller
  - "#interrupt-cells"

patternProperties:
  '-[0-9]+$':
    type: object
    patternProperties:
      '-pins$':
        type: object
        description: |
          A pinctrl node should contain at least one subnode representing the
          pinctrl groups available on the machine. Each subnode will list the
          pins it needs, and how they should be configured, with regard to
          muxer configuration, bias, input enable/disable, input schmitt
          trigger enable/disable, slew-rate and drive strength.
        $ref: "/schemas/pinctrl/pincfg-node.yaml"

        properties:
          pins:
            description: |
              The list of pin identifiers that properties in the node apply to.
              This should be set using either the PAD_GPIO or PAD_FUNC_SHARE
              macros.
              Either this or "pinmux" has to be specified, but not both.
            $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pins"

          pinmux:
            description: |
              The list of GPIOs and their mux settings that properties in the
              node apply to. This should be set using the GPIOMUX macro.
              Either this or "pins" has to be specified, but not both.
            $ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pinmux"

          bias-disable: true

          bias-pull-up:
            type: boolean

          bias-pull-down:
            type: boolean

          drive-strength:
            enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ]

          input-enable: true

          input-disable: true

          input-schmitt-enable: true

          input-schmitt-disable: true

          slew-rate:
            maximum: 7

          starfive,strong-pull-up:
            description: enable strong pull-up.
            type: boolean

        additionalProperties: false

    additionalProperties: false

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/starfive-jh7100.h>
    #include <dt-bindings/reset/starfive-jh7100.h>
    #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pinctrl@11910000 {
            compatible = "starfive,jh7100-pinctrl";
            reg = <0x0 0x11910000 0x0 0x10000>,
                  <0x0 0x11858000 0x0 0x1000>;
            reg-names = "gpio", "padctl";
            clocks = <&clkgen JH7100_CLK_GPIO_APB>;
            resets = <&clkgen JH7100_RSTN_GPIO_APB>;
            interrupts = <32>;
            gpio-controller;
            #gpio-cells = <2>;
            interrupt-controller;
            #interrupt-cells = <2>;
            starfive,signal-group = <6>;

            gmac_pins_default: gmac-0 {
                gtxclk-pins {
                    pins = <PAD_FUNC_SHARE(115)>;
                    bias-pull-up;
                    drive-strength = <35>;
                    input-enable;
                    input-schmitt-enable;
                    slew-rate = <0>;
                };
                miitxclk-pins {
                    pins = <PAD_FUNC_SHARE(116)>;
                    bias-pull-up;
                    drive-strength = <14>;
                    input-enable;
                    input-schmitt-disable;
                    slew-rate = <0>;
                };
                tx-pins {
                    pins = <PAD_FUNC_SHARE(117)>,
                           <PAD_FUNC_SHARE(119)>,
                           <PAD_FUNC_SHARE(120)>,
                           <PAD_FUNC_SHARE(121)>,
                           <PAD_FUNC_SHARE(122)>,
                           <PAD_FUNC_SHARE(123)>,
                           <PAD_FUNC_SHARE(124)>,
                           <PAD_FUNC_SHARE(125)>,
                           <PAD_FUNC_SHARE(126)>;
                    bias-disable;
                    drive-strength = <35>;
                    input-disable;
                    input-schmitt-disable;
                    slew-rate = <0>;
                };
                rxclk-pins {
                    pins = <PAD_FUNC_SHARE(127)>;
                    bias-pull-up;
                    drive-strength = <14>;
                    input-enable;
                    input-schmitt-disable;
                    slew-rate = <6>;
                };
                rxer-pins {
                    pins = <PAD_FUNC_SHARE(129)>;
                    bias-pull-up;
                    drive-strength = <14>;
                    input-enable;
                    input-schmitt-disable;
                    slew-rate = <0>;
                };
                rx-pins {
                    pins = <PAD_FUNC_SHARE(128)>,
                           <PAD_FUNC_SHARE(130)>,
                           <PAD_FUNC_SHARE(131)>,
                           <PAD_FUNC_SHARE(132)>,
                           <PAD_FUNC_SHARE(133)>,
                           <PAD_FUNC_SHARE(134)>,
                           <PAD_FUNC_SHARE(135)>,
                           <PAD_FUNC_SHARE(136)>,
                           <PAD_FUNC_SHARE(137)>,
                           <PAD_FUNC_SHARE(138)>,
                           <PAD_FUNC_SHARE(139)>,
                           <PAD_FUNC_SHARE(140)>,
                           <PAD_FUNC_SHARE(141)>;
                    bias-pull-up;
                    drive-strength = <14>;
                    input-enable;
                    input-schmitt-enable;
                    slew-rate = <0>;
                };
            };

            i2c0_pins_default: i2c0-0 {
                i2c-pins {
                    pinmux = <GPIOMUX(62, GPO_LOW,
                              GPO_I2C0_PAD_SCK_OEN,
                              GPI_I2C0_PAD_SCK_IN)>,
                             <GPIOMUX(61, GPO_LOW,
                              GPO_I2C0_PAD_SDA_OEN,
                              GPI_I2C0_PAD_SDA_IN)>;
                    bias-disable; /* external pull-up */
                    input-enable;
                    input-schmitt-enable;
                };
            };

            uart3_pins_default: uart3-0 {
                rx-pins {
                    pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
                              GPI_UART3_PAD_SIN)>;
                    bias-pull-up;
                    input-enable;
                    input-schmitt-enable;
                };
                tx-pins {
                    pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
                              GPO_ENABLE, GPI_NONE)>;
                    bias-disable;
                    input-disable;
                    input-schmitt-disable;
                };
            };
        };

        gmac {
            pinctrl-0 = <&gmac_pins_default>;
            pinctrl-names = "default";
        };

        i2c0 {
            pinctrl-0 = <&i2c0_pins_default>;
            pinctrl-names = "default";
        };

        uart3 {
            pinctrl-0 = <&uart3_pins_default>;
            pinctrl-names = "default";
        };
    };

...

repo_name: angery/linux


code:
ST Ericsson abx500 pinmux controller

Required properties:
- compatible: "stericsson,ab8500-gpio",  "stericsson,ab8540-gpio",
	      "stericsson,ab8505-gpio", "stericsson,ab9540-gpio",

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

ST Ericsson's pin configuration nodes use the generic pin multiplexing
and pin configuration bindings, see pinctrl-bindings.txt

Example board file extract:

&pinctrl_abx500 {
	pinctrl-names = "default";
	pinctrl-0 = <&sysclkreq2_default_mode>, <&sysclkreq3_default_mode>, <&gpio3_default_mode>, <&sysclkreq6_default_mode>, <&pwmout1_default_mode>, <&pwmout2_default_mode>, <&pwmout3_default_mode>, <&adi1_default_mode>, <&dmic12_default_mode>, <&dmic34_default_mode>, <&dmic56_default_mode>, <&sysclkreq5_default_mode>, <&batremn_default_mode>, <&service_default_mode>, <&pwrctrl0_default_mode>, <&pwrctrl1_default_mode>, <&pwmextvibra1_default_mode>, <&pwmextvibra2_default_mode>, <&gpio51_default_mode>, <&gpio52_default_mode>, <&gpio53_default_mode>, <&gpio54_default_mode>, <&pdmclkdat_default_mode>;

	sysclkreq2 {
		sysclkreq2_default_mode: sysclkreq2_default {
			default_mux {
				function = "sysclkreq";
				groups = "sysclkreq2_d_1";
			};
			default_cfg {
				pins = "GPIO1";
				bias-disable;
			};
		};
	};
	sysclkreq3 {
		sysclkreq3_default_mode: sysclkreq3_default {
			default_mux {
				function = "sysclkreq";
				groups = "sysclkreq3_d_1";
			};
			default_cfg {
				pins = "GPIO2";
				output-low;
			};
		};
	};
	gpio3 {
		gpio3_default_mode: gpio3_default {
			default_mux {
				function = "gpio";
				groups = "gpio3_a_1";
			};
			default_cfg {
				pins = "GPIO3";
				output-low;
			};
		};
	};
	sysclkreq6 {
		sysclkreq6_default_mode: sysclkreq6_default {
			default_mux {
				function = "sysclkreq";
				groups = "sysclkreq6_d_1";
			};
			default_cfg {
				pins = "GPIO4";
				bias-disable;
			};
		};
	};
	pwmout1 {
		pwmout1_default_mode: pwmout1_default {
			default_mux {
				function = "pwmout";
				groups = "pwmout1_d_1";
			};
			default_cfg {
				pins = "GPIO14";
				output-low;
			};
		};
	};
	pwmout2 {
		pwmout2_default_mode: pwmout2_default {
			pwmout2_default_mux {
				function = "pwmout";
				groups = "pwmout2_d_1";
			};
			pwmout2_default_cfg {
				pins = "GPIO15";
				output-low;
			};
		};
	};
	pwmout3 {
		pwmout3_default_mode: pwmout3_default {
			pwmout3_default_mux {
				function = "pwmout";
				groups = "pwmout3_d_1";
			};
			pwmout3_default_cfg {
				pins = "GPIO16";
				output-low;
			};
		};
	};
	adi1 {

		adi1_default_mode: adi1_default {
			adi1_default_mux {
				function = "adi1";
				groups = "adi1_d_1";
			};
			adi1_default_cfg1 {
				pins = "GPIO17","GPIO19","GPIO20";
				bias-disable;
			};
			adi1_default_cfg2 {
				pins = "GPIO18";
				output-low;
			};
		};
	};
	dmic12 {
		dmic12_default_mode: dmic12_default {
			dmic12_default_mux {
				function = "dmic";
				groups = "dmic12_d_1";
			};
			dmic12_default_cfg1 {
				pins = "GPIO27";
				output-low;
			};
			dmic12_default_cfg2 {
				pins = "GPIO28";
				bias-disable;
			};
		};
	};
	dmic34 {
		dmic34_default_mode: dmic34_default {
			dmic34_default_mux {
				function = "dmic";
				groups = "dmic34_d_1";
			};
			dmic34_default_cfg1 {
				pins = "GPIO29";
				output-low;
			};
			dmic34_default_cfg2 {
				pins = "GPIO30";
				bias-disable;{

			};
		};
	};
	dmic56 {
		dmic56_default_mode: dmic56_default {
			dmic56_default_mux {
				function = "dmic";
				groups = "dmic56_d_1";
			};
			dmic56_default_cfg1 {
				pins = "GPIO31";
				output-low;
			};
			dmic56_default_cfg2 {
				pins = "GPIO32";
				bias-disable;
			};
		};
	};
	sysclkreq5 {
		sysclkreq5_default_mode: sysclkreq5_default {
			sysclkreq5_default_mux {
				function = "sysclkreq";
				groups = "sysclkreq5_d_1";
			};
			sysclkreq5_default_cfg {
				pins = "GPIO42";
				output-low;
			};
		};
	};
	batremn {
		batremn_default_mode: batremn_default {
			batremn_default_mux {
				function = "batremn";
				groups = "batremn_d_1";
			};
			batremn_default_cfg {
				pins = "GPIO43";
				bias-disable;
			};
		};
	};
	service {
		service_default_mode: service_default {
			service_default_mux {
				function = "service";
				groups = "service_d_1";
			};
			service_default_cfg {
				pins = "GPIO44";
				bias-disable;
			};
		};
	};
	pwrctrl0 {
		pwrctrl0_default_mux: pwrctrl0_mux {
			pwrctrl0_default_mux {
				function = "pwrctrl";
				groups = "pwrctrl0_d_1";
			};
		};
		pwrctrl0_default_mode: pwrctrl0_default {
			pwrctrl0_default_cfg {
				pins = "GPIO45";
				bias-disable;
			};
		};
	};
	pwrctrl1 {
		pwrctrl1_default_mux: pwrctrl1_mux {
			pwrctrl1_default_mux {
				function = "pwrctrl";
				groups = "pwrctrl1_d_1";
			};
		};
		pwrctrl1_default_mode: pwrctrl1_default {
			pwrctrl1_default_cfg {
				pins = "GPIO46";
				bias-disable;
			};
		};
	};
	pwmextvibra1 {
		pwmextvibra1_default_mode: pwmextvibra1_default {
			pwmextvibra1_default_mux {
				function = "pwmextvibra";
				groups = "pwmextvibra1_d_1";
			};
			pwmextvibra1_default_cfg {
				pins = "GPIO47";
				bias-disable;
			};
		};
	};
	pwmextvibra2 {
		pwmextvibra2_default_mode: pwmextvibra2_default {
			pwmextvibra2_default_mux {
				function = "pwmextvibra";
				groups = "pwmextvibra2_d_1";
			};
			pwmextvibra1_default_cfg {
				pins = "GPIO48";
				bias-disable;
			};
		};
	};
	gpio51 {
		gpio51_default_mode: gpio51_default {
				gpio51_default_mux {
				function = "gpio";
				groups = "gpio51_a_1";
			};
			gpio51_default_cfg {
				pins = "GPIO51";
				output-low;
			};
		};
	};
	gpio52 {
		gpio52_default_mode: gpio52_default {
			gpio52_default_mux {
				function = "gpio";
				groups = "gpio52_a_1";
			};
			gpio52_default_cfg {
				pins = "GPIO52";
				bias-pull-down;
			};
		};
	};
	gpio53 {
		gpio53_default_mode: gpio53_default {
			gpio53_default_mux {
				function = "gpio";
				groups = "gpio53_a_1";
			};
			gpio53_default_cfg {
				pins = "GPIO53";
				bias-pull-down;
			};
		};
	};
	gpio54 {
		gpio54_default_mode: gpio54_default {
			gpio54_default_mux {
				function = "gpio";
				groups = "gpio54_a_1";
			};
			gpio54_default_cfg {
				pins = "GPIO54";
				output-low;
			};
		};
	};
	pdmclkdat {
		pdmclkdat_default_mode: pdmclkdat_default {
			pdmclkdat_default_mux {
				function = "pdm";
				groups = "pdmclkdat_d_1";
			};
			pdmclkdat_default_cfg {
				pins = "GPIO55", "GPIO56";
				bias-disable;
			};
		};
	};
};


code:
ST Ericsson Nomadik pinmux controller

Required properties:
- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
              "stericsson,stn8815-pinctrl"
- nomadik-gpio-chips: array of phandles to the corresponding GPIO chips
              (these have the register ranges used by the pin controller).
- prcm: phandle to the PRCMU managing the back end of this pin controller

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as input, output, pull up, pull down...

The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content. The subnodes use the generic
pin multiplexing node layout from the standard pin control bindings
(see pinctrl-bindings.txt):

Required pin multiplexing subnode properties:
- function: A string containing the name of the function to mux to the
  pin or group.
- groups : An array of strings. Each string contains the name of a pin
  group that will be combined with the function to form a multiplexing
  set-up.

Required pin configuration subnode properties:
- pins: A string array describing the pins affected by the configuration
  in the node.
- ste,config: Handle of pin configuration node
  (e.g. ste,config = <&slpm_in_wkup_pdis>)

- ste,input : <0/1/2>
	0: input with no pull
	1: input with pull up,
	2: input with pull down,

- ste,output: <0/1/2>
	0: output low,
	1: output high,
	2: output (value is not specified).

- ste,sleep: <0/1>
	0: sleep mode disable,
	1: sleep mode enable.

- ste,sleep-input: <0/1/2/3>
	0: sleep input with no pull,
	1: sleep input with pull up,
	2: sleep input with pull down.
	3: sleep input and keep last input configuration (no pull, pull up or pull down).

- ste,sleep-output: <0/1/2>
	0: sleep output low,
	1: sleep output high,
	2: sleep output (value is not specified).

- ste,sleep-gpio: <0/1>
	0: disable sleep gpio mode,
	1: enable sleep gpio mode.

- ste,sleep-wakeup: <0/1>
	0: wake-up detection enabled,
	1: wake-up detection disabled.

- ste,sleep-pull-disable: <0/1>
	0: GPIO pull-up or pull-down resistor is enabled, when pin is an input,
	1: GPIO pull-up and pull-down resistor are disabled.

Example board file extract:

	pinctrl@80157000 {
		compatible = "stericsson,db8500-pinctrl";
		nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>;
		prcm = <&prcmu>;

		pinctrl-names = "default";

		slpm_in_wkup_pdis: slpm_in_wkup_pdis {
			ste,sleep = <1>;
			ste,sleep-input = <3>;
			ste,sleep-wakeup = <1>;
			ste,sleep-pull-disable = <0>;
		};

		slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis {
			ste,sleep = <1>;
			ste,sleep-output = <1>;
			ste,sleep-wakeup = <1>;
			ste,sleep-pull-disable = <0>;
		};

		slpm_out_wkup_pdis: slpm_out_wkup_pdis {
			ste,sleep = <1>;
			ste,sleep-output = <2>;
			ste,sleep-wakeup = <1>;
			ste,sleep-pull-disable = <0>;
		};

		uart0 {
			uart0_default_mux: uart0_mux {
				u0_default_mux {
					function = "u0";
					pins = "u0_a_1";
				};
			};
			uart0_default_mode: uart0_default {
				uart0_default_cfg1 {
					pins = "GPIO0", "GPIO2";
					ste,input = <1>;
				};

				uart0_default_cfg2 {
					pins = "GPIO1", "GPIO3";
					ste,output = <1>;
				};
			};
			uart0_sleep_mode: uart0_sleep {
				uart0_sleep_cfg1 {
					pins = "GPIO0", "GPIO2";
					ste,config = <&slpm_in_wkup_pdis>;
				};
				uart0_sleep_cfg2 {
					pins = "GPIO1";
					ste,config = <&slpm_out_hi_wkup_pdis>;
				};
				uart0_sleep_cfg3 {
					pins = "GPIO3";
					ste,config = <&slpm_out_wkup_pdis>;
				};
			};
		};
	};

	uart@80120000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x80120000 0x1000>;
		interrupts = <0 11 0x4>;

		pinctrl-names = "default","sleep";
		pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>;
		pinctrl-1 = <&uart0_sleep_mode>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sunplus SP7021 Pin Controller

maintainers:
  - Dvorkin Dmitry <dvorkin@tibbo.com>
  - Wells Lu <wellslutw@gmail.com>

description: |
  The Sunplus SP7021 pin controller is used to control SoC pins. Please
  refer to pinctrl-bindings.txt in this directory for details of the common
  pinctrl bindings used by client devices.

  SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
  are multiplexed with some special function pins. SP7021 has 3 types of
  special function pins:

  (1) function-group pins:
      Ex 1 (SPI-NOR flash):
        If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87
        will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79
        and 81 will be pins of SPI-NOR flash.

      Ex 2 (UART_0):
        If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and
        RX pins of UART_0 (UART channel 0).

      Ex 3 (eMMC):
        If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77,
        78, 79, 80, 81 will be pins of an eMMC device.

      Properties "function" and "groups" are used to select function-group
      pins.

  (2) fully pin-mux (like phone exchange mux) pins:
      GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of
      SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.)
      can be routed to any pins of fully pin-mux pins.

      Ex 1 (UART channel 1):
        If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be
        routed to GPIO 10 (3 - 1 + 8 = 10).
        If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be
        routed to GPIO 11 (4 - 1 + 8 = 11).
        If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will
        be routed to GPIO 12 (5 - 1 + 8 = 12).
        If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will
        be routed to GPIO 13 (6 - 1 + 8 = 13).

      Ex 2 (I2C channel 0):
        If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will
        be routed to GPIO 27 (20 - 1 + 8 = 27).
        If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0
        will be routed to GPIO 28 (21 - 1 + 9 = 28).

      Totally, SP7021 has 120 peripheral pins. The peripheral pins can be
      routed to any of 64 'fully pin-mux' pins.

  (3) I/O processor pins
      SP7021 has a built-in I/O processor.
      Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor.

  Vendor property "sunplus,pins" is used to select "fully pin-mux" pins,
  "I/O processor pins" and "digital GPIO" pins.

  The device node of pin controller of Sunplus SP7021 has following
  properties.

properties:
  compatible:
    const: sunplus,sp7021-pctl

  gpio-controller: true

  '#gpio-cells':
    const: 2

  reg:
    items:
      - description: the MOON2 registers
      - description: the GPIOXT registers
      - description: the FIRST registers
      - description: the MOON1 registers

  reg-names:
    items:
      - const: moon2
      - const: gpioxt
      - const: first
      - const: moon1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

patternProperties:
  '-pins$':
    type: object
    description: |
      A pinctrl node should contain at least one subnodes representing the
      pins or function-pins group available on the machine. Each subnode
      will list the pins it needs, and how they should be configured.

      Pinctrl node's client devices use subnodes for desired pin
      configuration. Client device subnodes use below standard properties.
    $ref: pinmux-node.yaml#

    properties:
      sunplus,pins:
        description: |
          Define 'sunplus,pins' which are used by pinctrl node's client
          device.

          It consists of one or more integers which represents the config
          setting for corresponding pin. Each integer defines a individual
          pin in which:

          Bit 32~24: defines GPIO number. Its range is 0 ~ 98.
          Bit 23~16: defines types: (1) fully pin-mux pins
                                    (2) IO processor pins
                                    (3) digital GPIO pins
          Bit 15~8:  defines pins of peripherals (which are defined in
                     'include/dt-binging/pinctrl/sppctl.h').
          Bit 7~0:   defines types or initial-state of digital GPIO pins.

          Please use macro SPPCTL_IOPAD to define the integers for pins.

        $ref: /schemas/types.yaml#/definitions/uint32-array

      function:
        description: |
          Define pin-function which is used by pinctrl node's client device.
          The name should be one of string in the following enumeration.
        $ref: "/schemas/types.yaml#/definitions/string"
        enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD,
                UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ]

      groups:
        description: |
          Define pin-group in a specified pin-function.
          The name should be one of string in the following enumeration.
        $ref: "/schemas/types.yaml#/definitions/string"
        enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2,
                SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1,
                HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ]

      sunplus,zerofunc:
        description: |
          This is a vendor specific property. It is used to disable pins
          which are not used by pinctrl node's client device.
          Some pins may be enabled by boot-loader. We can use this
          property to disable them.
        $ref: /schemas/types.yaml#/definitions/uint32-array

    additionalProperties: false

    allOf:
      - if:
          properties:
            function:
              enum:
                - SPI_FLASH
        then:
          properties:
            groups:
              enum:
                - SPI_FLASH1
                - SPI_FLASH2
      - if:
          properties:
            function:
              enum:
                - SPI_FLASH_4BIT
        then:
          properties:
            groups:
              enum:
                - SPI_FLASH_4BIT1
                - SPI_FLASH_4BIT2
      - if:
          properties:
            function:
              enum:
                - SPI_NAND
        then:
          properties:
            groups:
              enum:
                - SPI_NAND
      - if:
          properties:
            function:
              enum:
                - CARD0_EMMC
        then:
          properties:
            groups:
              enum:
                - CARD0_EMMC
      - if:
          properties:
            function:
              enum:
                - SD_CARD
        then:
          properties:
            groups:
              enum:
                - SD_CARD
      - if:
          properties:
            function:
              enum:
                - UA0
        then:
          properties:
            groups:
              enum:
                - UA0
      - if:
          properties:
            function:
              enum:
                - FPGA_IFX
        then:
          properties:
            groups:
              enum:
                - FPGA_IFX
      - if:
          properties:
            function:
              enum:
                - HDMI_TX
        then:
          properties:
            groups:
              enum:
                - HDMI_TX1
                - HDMI_TX2
                - HDMI_TX3
      - if:
          properties:
            function:
              enum:
                - LCDIF
        then:
          properties:
            groups:
              enum:
                - LCDIF
      - if:
          properties:
            function:
              enum:
                - USB0_OTG
        then:
          properties:
            groups:
              enum:
                - USB0_OTG
      - if:
          properties:
            function:
              enum:
                - USB1_OTG
        then:
          properties:
            groups:
              enum:
                - USB1_OTG

required:
  - compatible
  - reg
  - reg-names
  - "#gpio-cells"
  - gpio-controller
  - clocks
  - resets

additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

examples:
  - |
    #include <dt-bindings/pinctrl/sppctl-sp7021.h>

    pinctrl@9c000100 {
        compatible = "sunplus,sp7021-pctl";
        reg = <0x9c000100 0x100>, <0x9c000300 0x100>,
              <0x9c0032e4 0x1c>, <0x9c000080 0x20>;
        reg-names = "moon2", "gpioxt", "first", "moon1";
        gpio-controller;
        #gpio-cells = <2>;
        clocks = <&clkc 0x83>;
        resets = <&rstc 0x73>;

        uart0-pins {
            function = "UA0";
            groups = "UA0";
        };

        spinand0-pins {
            function = "SPI_NAND";
            groups = "SPI_NAND";
        };

        uart1-pins {
            sunplus,pins = <
                SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
                SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
            >;
        };

        uart2-pins {
            sunplus,pins = <
                SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0)
                SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0)
                SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0)
                SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0)
            >;
        };

        emmc-pins {
            function = "CARD0_EMMC";
            groups = "CARD0_EMMC";
        };

        sdcard-pins {
            function = "SD_CARD";
            groups = "SD_CARD";
            sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
        };

        hdmi_A_tx1-pins {
            function = "HDMI_TX";
            groups = "HDMI_TX1";
        };
        hdmi_A_tx2-pins {
            function = "HDMI_TX";
            groups = "HDMI_TX2";
        };
        hdmi_A_tx3-pins {
            function = "HDMI_TX";
            groups = "HDMI_TX3";
        };

        ethernet-pins {
            sunplus,pins = <
                SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
                SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
                SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
                SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
                SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
                SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
                SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
                SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
                SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
            >;
            sunplus,zerofunc = <
                MUXF_L2SW_LED_FLASH0
                MUXF_L2SW_LED_ON0
                MUXF_L2SW_P0_MAC_RMII_RXER
            >;
        };
    };
...


code:
* Pin configuration for TI DA850/OMAP-L138/AM18x

These SoCs have a separate controller for setting bias (internal pullup/down).
Bias can only be selected for groups rather than individual pins.

Required Properties:

  - compatible: Must be "ti,da850-pupd"
  - reg: Base address and length of the memory resource used by the pullup/down
    controller hardware module.

The controller node also acts as a container for pin group configuration nodes.
The names of these groups are ignored.

Pin Group Node Properties:

- groups: An array of strings, each string containing the name of a pin group.
          Valid names are "cp0".."cp31".

The pin configuration parameters use the generic pinconf bindings defined in
pinctrl-bindings.txt in this directory. The supported parameters are
bias-disable, bias-pull-up, bias-pull-down.

Example
-------

In common dtsi file:

	pinconf: pin-controller@22c00c {
		compatible = "ti,da850-pupd";
		reg = <0x22c00c 0x8>;
	};

In board-specific file:

	&pinconf {
		pinctrl-0 = <&pinconf_bias_groups>;
		pinctrl-names = "default";

		pinconf_bias_groups: bias-groups {
			pull-up {
				groups = "cp30", "cp31";
				bias-pull-up;
			};
			pull-down {
				groups = "cp29", "cp28";
				bias-pull-down;
			};
			disable {
				groups = "cp27", "cp26";
				bias-disable;
			};
		};
	};


code:
* Pin configuration for TI IODELAY controller

TI dra7 based SoCs such as am57xx have a controller for setting the IO delay
for each pin. For most part the IO delay values are programmed by the bootloader,
but some pins need to be configured dynamically by the kernel such as the
MMC pins.

Required Properties:

  - compatible: Must be "ti,dra7-iodelay"
  - reg: Base address and length of the memory resource used
  - #address-cells: Number of address cells
  - #size-cells: Size of cells
  - #pinctrl-cells: Number of pinctrl cells, must be 2. See also
    Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

Example
-------

In the SoC specific dtsi file:

	dra7_iodelay_core: padconf@4844a000 {
		compatible = "ti,dra7-iodelay";
		reg = <0x4844a000 0x0d1c>;
		#address-cells = <1>;
		#size-cells = <0>;
		#pinctrl-cells = <2>;
	};

In board-specific file:

&dra7_iodelay_core {
	mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf {
		pinctrl-pin-array = <
		0x18c A_DELAY_PS(0) G_DELAY_PS(120)	/* CFG_GPMC_A19_IN */
		0x1a4 A_DELAY_PS(265) G_DELAY_PS(360)	/* CFG_GPMC_A20_IN */
		0x1b0 A_DELAY_PS(0) G_DELAY_PS(120)	/* CFG_GPMC_A21_IN */
		0x1bc A_DELAY_PS(0) G_DELAY_PS(120)	/* CFG_GPMC_A22_IN */
		0x1c8 A_DELAY_PS(287) G_DELAY_PS(420)	/* CFG_GPMC_A23_IN */
		0x1d4 A_DELAY_PS(144) G_DELAY_PS(240)	/* CFG_GPMC_A24_IN */
		0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A25_IN */
		0x1ec A_DELAY_PS(120) G_DELAY_PS(0)	/* CFG_GPMC_A26_IN */
		0x1f8 A_DELAY_PS(120) G_DELAY_PS(180)	/* CFG_GPMC_A27_IN */
		0x360 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_CS1_IN */
		>;
	};
};


code:
OMAP Pinctrl definitions

Required properties:
- compatible : Should be one of:
  "ti,omap2420-padconf" - OMAP2420 compatible pinctrl
  "ti,omap2430-padconf" - OMAP2430 compatible pinctrl
  "ti,omap3-padconf" - OMAP3 compatible pinctrl
  "ti,omap4-padconf" - OMAP4 compatible pinctrl
  "ti,omap5-padconf" - OMAP5 compatible pinctrl
  "ti,dra7-padconf" - DRA7 compatible pinctrl
  "ti,am437-padconf" - AM437x compatible pinctrl

See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details.


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Toshiba Visconti TMPV770x pin mux/config controller

maintainers:
  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

description:
  Toshiba's Visconti ARM SoC a pin mux/config controller.

properties:
  compatible:
    enum:
      - toshiba,tmpv7708-pinctrl

  reg:
    maxItems: 1

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

patternProperties:
  '-pins$':
    type: object
    description: |
      A pinctrl node should contain at least one subnodes representing the
      pinctrl groups available on the machine. Each subnode will list the
      pins it needs, and how they should be configured, with regard to muxer
      configuration, pullups, drive strength.
    $ref: "pinmux-node.yaml"
    additionalProperties: false

    properties:
      function:
        description:
          Function to mux.
        $ref: "/schemas/types.yaml#/definitions/string"
        enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8,
               spi0, spi1, spi2, spi3, spi4, spi5, spi6,
               uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in]

      groups:
        description:
          Name of the pin group to use for the functions.
        $ref: "/schemas/types.yaml#/definitions/string"
        enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp,
               i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp,
               spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp,
               spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp,
               uart0_grp, uart1_grp, uart2_grp, uart3_grp,
               pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp,
               pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp,
               pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp,
               pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp,
               pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp,
               pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp]

      drive-strength:
        enum: [2, 4, 6, 8, 16, 24, 32]
        default: 2
        description:
          Selects the drive strength for the specified pins, in mA.

      bias-pull-up: true

      bias-pull-down: true

      bias-disable: true

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pmux: pinmux@24190000 {
            compatible = "toshiba,tmpv7708-pinctrl";
            reg = <0 0x24190000 0 0x10000>;

            spi0_pins: spi0-pins {
                function = "spi0";
                groups = "spi0_grp";
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Zynq Pinctrl

maintainers:
  - Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>

description: |
  Please refer to pinctrl-bindings.txt in this directory for details of the
  common pinctrl bindings used by client devices, including the meaning of the
  phrase "pin configuration node".

  Zynq's pin configuration nodes act as a container for an arbitrary number of
  subnodes. Each of these subnodes represents some desired configuration for a
  pin, a group, or a list of pins or groups. This configuration can include the
  mux function to select on those pin(s)/group(s), and various pin configuration
  parameters, such as pull-up, slew rate, etc.

  Each configuration node can consist of multiple nodes describing the pinmux and
  pinconf options. Those nodes can be pinmux nodes or pinconf nodes.

  The name of each subnode is not important; all subnodes should be enumerated
  and processed purely based on their content.

properties:
  compatible:
    const: xlnx,zynq-pinctrl

  reg:
    description: Specifies the base address and size of the SLCR space.
    maxItems: 1

  syscon:
    description:
      phandle to the SLCR.

patternProperties:
  '^(.*-)?(default|gpio)$':
    type: object
    patternProperties:
      '^mux':
        type: object
        description:
          Pinctrl node's client devices use subnodes for pin muxes,
          which in turn use below standard properties.
        $ref: pinmux-node.yaml#

        properties:
          groups:
            description:
              List of groups to select (either this or "pins" must be
              specified), available groups for this subnode.
            items:
              enum: [ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp,
                     mdio1_0_grp, qspi0_0_grp, qspi1_0_grp, qspi_fbclk,
                     qspi_cs1_grp, spi0_0_grp, spi0_1_grp, spi0_2_grp,
                     spi0_0_ss0, spi0_0_ss1, spi0_0_ss2, spi0_1_ss0,
                     spi0_1_ss1, spi0_1_ss2, spi0_2_ss0, spi0_2_ss1,
                     spi0_2_ss2, spi1_0_grp, spi1_1_grp, spi1_2_grp,
                     spi1_3_grp, spi1_0_ss0, spi1_0_ss1, spi1_0_ss2,
                     spi1_1_ss0, spi1_1_ss1, spi1_1_ss2, spi1_2_ss0,
                     spi1_2_ss1, spi1_2_ss2, spi1_3_ss0, spi1_3_ss1,
                     spi1_3_ss2, sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
                     sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, sdio1_3_grp,
                     sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
                     sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp,
                     smc0_nor_addr25_grp, smc0_nand, can0_0_grp, can0_1_grp,
                     can0_2_grp, can0_3_grp, can0_4_grp, can0_5_grp,
                     can0_6_grp, can0_7_grp, can0_8_grp, can0_9_grp,
                     can0_10_grp, can1_0_grp, can1_1_grp, can1_2_grp,
                     can1_3_grp, can1_4_grp, can1_5_grp, can1_6_grp,
                     can1_7_grp, can1_8_grp, can1_9_grp, can1_10_grp,
                     can1_11_grp, uart0_0_grp, uart0_1_grp, uart0_2_grp,
                     uart0_3_grp, uart0_4_grp, uart0_5_grp, uart0_6_grp,
                     uart0_7_grp, uart0_8_grp, uart0_9_grp, uart0_10_grp,
                     uart1_0_grp, uart1_1_grp, uart1_2_grp, uart1_3_grp,
                     uart1_4_grp, uart1_5_grp, uart1_6_grp, uart1_7_grp,
                     uart1_8_grp, uart1_9_grp, uart1_10_grp, uart1_11_grp,
                     i2c0_0_grp, i2c0_1_grp, i2c0_2_grp, i2c0_3_grp,
                     i2c0_4_grp, i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
                     i2c0_8_grp, i2c0_9_grp, i2c0_10_grp, i2c1_0_grp,
                     i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, i2c1_4_grp,
                     i2c1_5_grp, i2c1_6_grp, i2c1_7_grp, i2c1_8_grp,
                     i2c1_9_grp, i2c1_10_grp, ttc0_0_grp, ttc0_1_grp,
                     ttc0_2_grp, ttc1_0_grp, ttc1_1_grp, ttc1_2_grp,
                     swdt0_0_grp, swdt0_1_grp, swdt0_2_grp, swdt0_3_grp,
                     swdt0_4_grp, gpio0_0_grp, gpio0_1_grp, gpio0_2_grp,
                     gpio0_3_grp, gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
                     gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, gpio0_10_grp,
                     gpio0_11_grp, gpio0_12_grp, gpio0_13_grp, gpio0_14_grp,
                     gpio0_15_grp, gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
                     gpio0_19_grp, gpio0_20_grp, gpio0_21_grp, gpio0_22_grp,
                     gpio0_23_grp, gpio0_24_grp, gpio0_25_grp, gpio0_26_grp,
                     gpio0_27_grp, gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
                     gpio0_31_grp, gpio0_32_grp, gpio0_33_grp, gpio0_34_grp,
                     gpio0_35_grp, gpio0_36_grp, gpio0_37_grp, gpio0_38_grp,
                     gpio0_39_grp, gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
                     gpio0_43_grp, gpio0_44_grp, gpio0_45_grp, gpio0_46_grp,
                     gpio0_47_grp, gpio0_48_grp, gpio0_49_grp, gpio0_50_grp,
                     gpio0_51_grp, gpio0_52_grp, gpio0_53_grp, usb0_0_grp,
                     usb1_0_grp]
            maxItems: 54

          function:
            description:
              Specify the alternative function to be configured for the
              given pin groups.
            enum: [ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk,
                   qspi_cs1, spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc,
                   sdio0_cd, sdio0_wp, sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
                   smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0,
                   can1, uart0, uart1, i2c0, i2c1, ttc0, ttc1, swdt0, gpio0,
                   usb0, usb1]

        required:
          - groups
          - function

        additionalProperties: false

      '^conf':
        type: object
        description:
          Pinctrl node's client devices use subnodes for pin configurations,
          which in turn use the standard properties below.
        $ref: pincfg-node.yaml#

        properties:
          groups:
            description:
              List of pin groups as mentioned above.

          pins:
            description:
              List of pin names to select in this subnode.
            items:
              pattern: '^MIO([0-9]|[1-4][0-9]|5[0-3])$'
            maxItems: 54

          bias-pull-up: true

          bias-pull-down: true

          bias-disable: true

          bias-high-impedance: true

          low-power-enable: true

          low-power-disable: true

          slew-rate:
            enum: [0, 1]

          power-source:
            enum: [1, 2, 3, 4]

        oneOf:
          - required: [ groups ]
          - required: [ pins ]

        additionalProperties: false

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - syscon

additionalProperties: false

examples:
  - |
    #include <dt-bindings/pinctrl/pinctrl-zynq.h>
    pinctrl0: pinctrl@700 {
       compatible = "xlnx,zynq-pinctrl";
       reg = <0x700 0x200>;
       syscon = <&slcr>;

       pinctrl_uart1_default: uart1-default {
           mux {
               groups = "uart1_10_grp";
               function = "uart1";
           };

           conf {
               groups = "uart1_10_grp";
               slew-rate = <0>;
               power-source = <IO_STANDARD_LVCMOS18>;
           };

           conf-rx {
               pins = "MIO49";
               bias-high-impedance;
           };

           conf-tx {
               pins = "MIO48";
               bias-disable;
           };
       };
    };

    uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1_default>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx ZynqMP Pinctrl

maintainers:
  - Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
  - Rajan Vaja <rajan.vaja@xilinx.com>

description: |
  Please refer to pinctrl-bindings.txt in this directory for details of the
  common pinctrl bindings used by client devices, including the meaning of the
  phrase "pin configuration node".

  ZynqMP's pin configuration nodes act as a container for an arbitrary number of
  subnodes. Each of these subnodes represents some desired configuration for a
  pin, a group, or a list of pins or groups. This configuration can include the
  mux function to select on those pin(s)/group(s), and various pin configuration
  parameters, such as pull-up, slew rate, etc.

  Each configuration node can consist of multiple nodes describing the pinmux and
  pinconf options. Those nodes can be pinmux nodes or pinconf nodes.

  The name of each subnode is not important; all subnodes should be enumerated
  and processed purely based on their content.

properties:
  compatible:
    const: xlnx,zynqmp-pinctrl

patternProperties:
  '^(.*-)?(default|gpio)$':
    type: object
    patternProperties:
      '^mux':
        type: object
        description:
          Pinctrl node's client devices use subnodes for pin muxes,
          which in turn use below standard properties.
        $ref: pinmux-node.yaml#

        properties:
          groups:
            description:
              List of groups to select (either this or "pins" must be
              specified), available groups for this subnode.
            items:
              enum: [ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
                     ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
                     gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
                     mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
                     qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
                     spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
                     spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
                     spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
                     spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
                     spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
                     spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
                     spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
                     spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
                     spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
                     spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
                     spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
                     spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
                     spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
                     spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
                     spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
                     spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
                     sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
                     sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
                     sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
                     sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
                     sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
                     sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
                     sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
                     sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
                     sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
                     sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
                     sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
                     sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
                     sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
                     sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
                     sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
                     sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
                     sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
                     sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
                     sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
                     sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
                     sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
                     sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
                     nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
                     nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
                     can0_1_grp, can0_2_grp, can0_3_grp,
                     can0_4_grp, can0_5_grp, can0_6_grp,
                     can0_7_grp, can0_8_grp, can0_9_grp,
                     can0_10_grp, can0_11_grp, can0_12_grp,
                     can0_13_grp, can0_14_grp, can0_15_grp,
                     can0_16_grp, can0_17_grp, can0_18_grp,
                     can1_0_grp, can1_1_grp, can1_2_grp,
                     can1_3_grp, can1_4_grp, can1_5_grp,
                     can1_6_grp, can1_7_grp, can1_8_grp,
                     can1_9_grp, can1_10_grp, can1_11_grp,
                     can1_12_grp, can1_13_grp, can1_14_grp,
                     can1_15_grp, can1_16_grp, can1_17_grp,
                     can1_18_grp, can1_19_grp, uart0_0_grp,
                     uart0_1_grp, uart0_2_grp, uart0_3_grp,
                     uart0_4_grp, uart0_5_grp, uart0_6_grp,
                     uart0_7_grp, uart0_8_grp, uart0_9_grp,
                     uart0_10_grp, uart0_11_grp, uart0_12_grp,
                     uart0_13_grp, uart0_14_grp, uart0_15_grp,
                     uart0_16_grp, uart0_17_grp, uart0_18_grp,
                     uart1_0_grp, uart1_1_grp, uart1_2_grp,
                     uart1_3_grp, uart1_4_grp, uart1_5_grp,
                     uart1_6_grp, uart1_7_grp, uart1_8_grp,
                     uart1_9_grp, uart1_10_grp, uart1_11_grp,
                     uart1_12_grp, uart1_13_grp, uart1_14_grp,
                     uart1_15_grp, uart1_16_grp, uart1_17_grp,
                     uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
                     i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
                     i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
                     i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
                     i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
                     i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
                     i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
                     i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
                     i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
                     i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
                     i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
                     i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
                     i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
                     i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
                     ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
                     ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
                     ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
                     ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
                     ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
                     ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
                     ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
                     ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
                     ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
                     ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
                     ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
                     ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
                     ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
                     ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
                     ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
                     ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
                     ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
                     ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
                     ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
                     ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
                     ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
                     ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
                     ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
                     ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
                     swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
                     swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
                     swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
                     swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
                     swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
                     swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
                     swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
                     swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
                     swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
                     swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
                     swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
                     swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
                     swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
                     swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
                     swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
                     swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
                     swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
                     gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
                     gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
                     gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
                     gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
                     gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
                     gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
                     gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
                     gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
                     gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
                     gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
                     gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
                     gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
                     gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
                     gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
                     gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
                     gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
                     gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
                     gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
                     gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
                     gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
                     gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
                     gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
                     gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
                     gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
                     gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
                     gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
                     usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
                     pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
                     pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
                     pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
                     pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
                     pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
                     pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
                     csu0_0_grp, csu0_1_grp, csu0_2_grp,
                     csu0_3_grp, csu0_4_grp, csu0_5_grp,
                     csu0_6_grp, csu0_7_grp, csu0_8_grp,
                     csu0_9_grp, csu0_10_grp, csu0_11_grp,
                     dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
                     dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
                     pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
                     pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
                     trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
                     trace0_clk_2_grp, testscan0_0_grp]
            maxItems: 78

          function:
            description:
              Specify the alternative function to be configured for the
              given pin groups.
            enum: [ethernet0, ethernet1, ethernet2, ethernet3, gemtsu0, usb0, usb1, mdio0,
                   mdio1, mdio2, mdio3, qspi0, qspi_fbclk, qspi_ss, spi0, spi1, spi0_ss,
                   spi1_ss, sdio0, sdio0_pc, sdio0_wp, sdio0_cd, sdio1, sdio1_pc, sdio1_wp,
                   sdio1_cd, nand0, nand0_ce, nand0_rb, nand0_dqs, can0, can1, uart0, uart1,
                   i2c0, i2c1, ttc0_clk, ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav,
                   ttc3_clk, ttc3_wav, swdt0_clk, swdt0_rst, swdt1_clk, swdt1_rst, gpio0, pmu0,
                   pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0]

        required:
          - groups
          - function

        additionalProperties: false

      '^conf':
        type: object
        description:
          Pinctrl node's client devices use subnodes for pin configurations,
          which in turn use the standard properties below.
        $ref: pincfg-node.yaml#

        properties:
          groups:
            description:
              List of pin groups as mentioned above.

          pins:
            description:
              List of pin names to select in this subnode.
            items:
              pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
            maxItems: 78

          bias-pull-up: true

          bias-pull-down: true

          bias-disable: true

          input-schmitt-enable: true

          input-schmitt-disable: true

          bias-high-impedance: true

          low-power-enable: true

          low-power-disable: true

          slew-rate:
            enum: [0, 1]

          drive-strength:
            description:
              Selects the drive strength for MIO pins, in mA.
            enum: [2, 4, 8, 12]

          power-source:
            enum: [0, 1]

        oneOf:
          - required: [ groups ]
          - required: [ pins ]

        additionalProperties: false

    additionalProperties: false

allOf:
  - $ref: pinctrl.yaml#

required:
  - compatible

additionalProperties: false

examples:
  - |
    #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
    zynqmp_firmware: zynqmp-firmware {
        pinctrl0: pinctrl {
          compatible = "xlnx,zynqmp-pinctrl";

          pinctrl_uart1_default: uart1-default {
             mux {
                 groups = "uart0_4_grp", "uart0_5_grp";
                 function = "uart0";
             };

             conf {
                groups = "uart0_4_grp";
                slew-rate = <SLEW_RATE_SLOW>;
                power-source = <IO_STANDARD_LVCMOS18>;
             };

             conf-rx {
                pins = "MIO18";
                bias-pull-up;
             };

             conf-tx {
                pins = "MIO19";
                bias-disable;
                input-schmitt-disable;
             };
          };
        };
    };

    uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1_default>;
    };

...


code:
Device-tree bindings for persistent memory regions
-----------------------------------------------------

Persistent memory refers to a class of memory devices that are:

	a) Usable as main system memory (i.e. cacheable), and
	b) Retain their contents across power failure.

Given b) it is best to think of persistent memory as a kind of memory mapped
storage device. To ensure data integrity the operating system needs to manage
persistent regions separately to the normal memory pool. To aid with that this
binding provides a standardised interface for discovering where persistent
memory regions exist inside the physical address space.

Bindings for the region nodes:
-----------------------------

Required properties:
	- compatible = "pmem-region"

	- reg = <base, size>;
		The reg property should specificy an address range that is
		translatable to a system physical address range. This address
		range should be mappable as normal system memory would be
		(i.e cacheable).

		If the reg property contains multiple address ranges
		each address range will be treated as though it was specified
		in a separate device node. Having multiple address ranges in a
		node implies no special relationship between the two ranges.

Optional properties:
	- Any relevant NUMA assocativity properties for the target platform.

	- volatile; This property indicates that this region is actually
	  backed by non-persistent memory. This lets the OS know that it
	  may skip the cache flushes required to ensure data is made
	  persistent after a write.

	  If this property is absent then the OS must assume that the region
	  is backed by non-volatile memory.

Examples:
--------------------

	/*
	 * This node specifies one 4KB region spanning from
	 * 0x5000 to 0x5fff that is backed by non-volatile memory.
	 */
	pmem@5000 {
		compatible = "pmem-region";
		reg = <0x00005000 0x00001000>;
	};

	/*
	 * This node specifies two 4KB regions that are backed by
	 * volatile (normal) memory.
	 */
	pmem@6000 {
		compatible = "pmem-region";
		reg = < 0x00006000 0x00001000
			0x00008000 0x00001000 >;
		volatile;
	};


code:
Actions Semi Owl Smart Power System (SPS)

Required properties:
- compatible          :  "actions,s500-sps" for S500
                         "actions,s700-sps" for S700
                         "actions,s900-sps" for S900
- reg                 :  Offset and length of the register set for the device.
- #power-domain-cells :  Must be 1.
                         See macros in:
                          include/dt-bindings/power/owl-s500-powergate.h for S500
                          include/dt-bindings/power/owl-s700-powergate.h for S700
                          include/dt-bindings/power/owl-s900-powergate.h for S900

Example:

		sps: power-controller@b01b0100 {
			compatible = "actions,s500-sps";
			reg = <0xb01b0100 0x100>;
			#power-domain-cells = <1>;
		};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/amlogic,meson-ee-pwrc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic Meson Everything-Else Power Domains

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

description: |+
  The Everything-Else Power Domains node should be the child of a syscon
  node with the required property:

  - compatible: Should be the following:
                "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"

  Refer to the bindings described in
  Documentation/devicetree/bindings/mfd/syscon.yaml

properties:
  compatible:
    enum:
      - amlogic,meson8-pwrc
      - amlogic,meson8b-pwrc
      - amlogic,meson8m2-pwrc
      - amlogic,meson-gxbb-pwrc
      - amlogic,meson-axg-pwrc
      - amlogic,meson-g12a-pwrc
      - amlogic,meson-sm1-pwrc

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: vpu
      - const: vapb

  resets:
    minItems: 5
    maxItems: 12

  reset-names:
    minItems: 5
    maxItems: 12

  "#power-domain-cells":
    const: 1

  amlogic,ao-sysctrl:
    description: phandle to the AO sysctrl node
    $ref: /schemas/types.yaml#/definitions/phandle

allOf:
  - if:
      properties:
        compatible:
          enum:
            - amlogic,meson8b-pwrc
            - amlogic,meson8m2-pwrc
    then:
      properties:
        reset-names:
          items:
            - const: dblk
            - const: pic_dc
            - const: hdmi_apb
            - const: hdmi_system
            - const: venci
            - const: vencp
            - const: vdac
            - const: vencl
            - const: viu
            - const: venc
            - const: rdma
      required:
        - resets
        - reset-names

  - if:
      properties:
        compatible:
          enum:
            - amlogic,meson-gxbb-pwrc
    then:
      properties:
        reset-names:
          items:
            - const: viu
            - const: venc
            - const: vcbus
            - const: bt656
            - const: dvin
            - const: rdma
            - const: venci
            - const: vencp
            - const: vdac
            - const: vdi6
            - const: vencl
            - const: vid_lock
      required:
        - resets
        - reset-names

  - if:
      properties:
        compatible:
          enum:
            - amlogic,meson-axg-pwrc
    then:
      properties:
        reset-names:
          items:
            - const: viu
            - const: venc
            - const: vcbus
            - const: vencl
            - const: vid_lock
      required:
        - resets
        - reset-names

  - if:
      properties:
        compatible:
          enum:
            - amlogic,meson-g12a-pwrc
            - amlogic,meson-sm1-pwrc
    then:
      properties:
        reset-names:
          items:
            - const: viu
            - const: venc
            - const: vcbus
            - const: bt656
            - const: rdma
            - const: venci
            - const: vencp
            - const: vdac
            - const: vdi6
            - const: vencl
            - const: vid_lock
      required:
        - resets
        - reset-names

required:
  - compatible
  - clocks
  - clock-names
  - "#power-domain-cells"
  - amlogic,ao-sysctrl

additionalProperties: false

examples:
  - |
    pwrc: power-controller {
          compatible = "amlogic,meson-sm1-pwrc";
          #power-domain-cells = <1>;
          amlogic,ao-sysctrl = <&rti>;
          resets = <&reset_viu>,
                   <&reset_venc>,
                   <&reset_vcbus>,
                   <&reset_bt656>,
                   <&reset_rdma>,
                   <&reset_venci>,
                   <&reset_vencp>,
                   <&reset_vdac>,
                   <&reset_vdi6>,
                   <&reset_vencl>,
                   <&reset_vid_lock>;
          reset-names = "viu", "venc", "vcbus", "bt656",
                        "rdma", "venci", "vencp", "vdac",
                        "vdi6", "vencl", "vid_lock";
          clocks = <&clk_vpu>, <&clk_vapb>;
          clock-names = "vpu", "vapb";
    };


code:
Amlogic Meson Power Controller
==============================

The Amlogic Meson SoCs embeds an internal Power domain controller.

VPU Power Domain
----------------

The Video Processing Unit power domain is controlled by this power controller,
but the domain requires some external resources to meet the correct power
sequences.
The bindings must respect the power domain bindings as described in the file
power-domain.yaml

Device Tree Bindings:
---------------------

Required properties:
- compatible: should be one of the following :
	- "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
	- "amlogic,meson-g12a-pwrc-vpu" for the Meson G12A SoCs
- #power-domain-cells: should be 0
- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
- resets: phandles to the reset lines needed for this power demain sequence
	as described in ../reset/reset.txt
- clocks: from common clock binding: handle to VPU and VAPB clocks
- clock-names: from common clock binding: must contain "vpu", "vapb"
	corresponding to entry in the clocks property.

Parent node should have the following properties :
- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
- reg: base address and size of the AO system control register space.

Example:
-------

ao_sysctrl: sys-ctrl@0 {
	compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
	reg =  <0x0 0x0 0x0 0x100>;

	pwrc_vpu: power-controller-vpu {
		compatible = "amlogic,meson-gx-pwrc-vpu";
		#power-domain-cells = <0>;
		amlogic,hhi-sysctrl = <&sysctrl>;
		resets = <&reset RESET_VIU>,
			 <&reset RESET_VENC>,
			 <&reset RESET_VCBUS>,
			 <&reset RESET_BT656>,
			 <&reset RESET_DVIN_RESET>,
			 <&reset RESET_RDMA>,
			 <&reset RESET_VENCI>,
			 <&reset RESET_VENCP>,
			 <&reset RESET_VDAC>,
			 <&reset RESET_VDI6>,
			 <&reset RESET_VENCL>,
			 <&reset RESET_VID_LOCK>;
		clocks = <&clkc CLKID_VPU>,
			 <&clkc CLKID_VAPB>;
		clock-names = "vpu", "vapb";
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
# Copyright (c) 2019 Amlogic, Inc
# Author: Jianxin Pan <jianxin.pan@amlogic.com>
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/amlogic,meson-sec-pwrc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic Meson Secure Power Domains

maintainers:
  - Jianxin Pan <jianxin.pan@amlogic.com>

description: |+
  Secure Power Domains used in Meson A1/C1/S4 SoCs, and should be the child node
  of secure-monitor.

properties:
  compatible:
    enum:
      - amlogic,meson-a1-pwrc
      - amlogic,meson-s4-pwrc

  "#power-domain-cells":
    const: 1

required:
  - compatible
  - "#power-domain-cells"

additionalProperties: false

examples:
  - |
    secure-monitor {
        compatible = "amlogic,meson-gxbb-sm";

        pwrc: power-controller {
            compatible = "amlogic,meson-a1-pwrc";
            #power-domain-cells = <1>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple SoC PMGR Power States

maintainers:
  - Hector Martin <marcan@marcan.st>

allOf:
  - $ref: power-domain.yaml#

description: |
  Apple SoCs include PMGR blocks responsible for power management,
  which can control various clocks, resets, power states, and
  performance features. This binding describes the device power
  state registers, which control power states and resets.

  Each instance of a power controller within the PMGR syscon node
  represents a generic power domain provider, as documented in
  Documentation/devicetree/bindings/power/power-domain.yaml.
  The provider controls a single SoC block. The power hierarchy is
  represented via power-domains relationships between these nodes.

  See Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml
  for the top-level PMGR node documentation.

properties:
  compatible:
    items:
      - enum:
          - apple,t8103-pmgr-pwrstate
          - apple,t6000-pmgr-pwrstate
      - const: apple,pmgr-pwrstate

  reg:
    maxItems: 1

  "#power-domain-cells":
    const: 0

  "#reset-cells":
    const: 0

  power-domains:
    description:
      Reference to parent power domains. A domain may have multiple parents,
      and all will be powered up when it is powered.
    minItems: 1
    maxItems: 8 # Arbitrary, should be enough

  label:
    description:
      Specifies the name of the SoC domain being controlled. This is used to
      name the power/reset domains.

  apple,always-on:
    description:
      Forces this power domain to always be powered up.
    type: boolean

  apple,min-state:
    description:
      Specifies the minimum power state for auto-PM.
      0 = power gated, 4 = clock gated, 15 = on.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 15

required:
  - compatible
  - reg
  - "#power-domain-cells"
  - "#reset-cells"
  - label

additionalProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/avs/qcom,cpr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Core Power Reduction (CPR) bindings

maintainers:
  - Niklas Cassel <nks@flawful.org>

description: |
  CPR (Core Power Reduction) is a technology to reduce core power on a CPU
  or other device. Each OPP of a device corresponds to a "corner" that has
  a range of valid voltages for a particular frequency. While the device is
  running at a particular frequency, CPR monitors dynamic factors such as
  temperature, etc. and suggests adjustments to the voltage to save power
  and meet silicon characteristic requirements.

properties:
  compatible:
    items:
      - enum:
          - qcom,qcs404-cpr
      - const: qcom,cpr

  reg:
    description: Base address and size of the RBCPR register region.
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Reference clock.

  clock-names:
    items:
      - const: ref

  vdd-apc-supply:
    description: APC regulator supply.

  '#power-domain-cells':
    const: 0

  operating-points-v2:
    description: |
      A phandle to the OPP table containing the performance states
      supported by the CPR power domain.

  acc-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: A phandle to the syscon used for writing ACC settings.

  nvmem-cells:
    items:
      - description: Corner 1 quotient offset
      - description: Corner 2 quotient offset
      - description: Corner 3 quotient offset
      - description: Corner 1 initial voltage
      - description: Corner 2 initial voltage
      - description: Corner 3 initial voltage
      - description: Corner 1 quotient
      - description: Corner 2 quotient
      - description: Corner 3 quotient
      - description: Corner 1 ring oscillator
      - description: Corner 2 ring oscillator
      - description: Corner 3 ring oscillator
      - description: Fuse revision

  nvmem-cell-names:
    items:
      - const: cpr_quotient_offset1
      - const: cpr_quotient_offset2
      - const: cpr_quotient_offset3
      - const: cpr_init_voltage1
      - const: cpr_init_voltage2
      - const: cpr_init_voltage3
      - const: cpr_quotient1
      - const: cpr_quotient2
      - const: cpr_quotient3
      - const: cpr_ring_osc1
      - const: cpr_ring_osc2
      - const: cpr_ring_osc3
      - const: cpr_fuse_revision

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - vdd-apc-supply
  - '#power-domain-cells'
  - operating-points-v2
  - nvmem-cells
  - nvmem-cell-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    cpr_opp_table: opp-table-cpr {
        compatible = "operating-points-v2-qcom-level";

        cpr_opp1: opp1 {
            opp-level = <1>;
            qcom,opp-fuse-level = <1>;
        };
        cpr_opp2: opp2 {
            opp-level = <2>;
            qcom,opp-fuse-level = <2>;
        };
        cpr_opp3: opp3 {
            opp-level = <3>;
            qcom,opp-fuse-level = <3>;
        };
    };

    power-controller@b018000 {
        compatible = "qcom,qcs404-cpr", "qcom,cpr";
        reg = <0x0b018000 0x1000>;
        interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
        clocks = <&xo_board>;
        clock-names = "ref";
        vdd-apc-supply = <&pms405_s3>;
        #power-domain-cells = <0>;
        operating-points-v2 = <&cpr_opp_table>;
        acc-syscon = <&tcsr>;

        nvmem-cells = <&cpr_efuse_quot_offset1>,
            <&cpr_efuse_quot_offset2>,
            <&cpr_efuse_quot_offset3>,
            <&cpr_efuse_init_voltage1>,
            <&cpr_efuse_init_voltage2>,
            <&cpr_efuse_init_voltage3>,
            <&cpr_efuse_quot1>,
            <&cpr_efuse_quot2>,
            <&cpr_efuse_quot3>,
            <&cpr_efuse_ring1>,
            <&cpr_efuse_ring2>,
            <&cpr_efuse_ring3>,
            <&cpr_efuse_revision>;
        nvmem-cell-names = "cpr_quotient_offset1",
            "cpr_quotient_offset2",
            "cpr_quotient_offset3",
            "cpr_init_voltage1",
            "cpr_init_voltage2",
            "cpr_init_voltage3",
            "cpr_quotient1",
            "cpr_quotient2",
            "cpr_quotient3",
            "cpr_ring_osc1",
            "cpr_ring_osc2",
            "cpr_ring_osc3",
            "cpr_fuse_revision";
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/brcm,bcm-pmb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom PMB (Power Management Bus) controller

description: This document describes Broadcom's PMB controller. It supports
  powering various types of connected devices (e.g. PCIe, USB, SATA).

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

properties:
  compatible:
    enum:
      - brcm,bcm4908-pmb
      - brcm,bcm63138-pmb

  reg:
    description: register space of one or more buses
    maxItems: 1

  big-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description: Flag to use for block working in big endian mode.

  "#power-domain-cells":
    description: cell specifies device ID (see bcm-pmb.h)
    const: 1

required:
  - reg
  - "#power-domain-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/soc/bcm-pmb.h>

    pmb: power-controller@802800e0 {
        compatible = "brcm,bcm4908-pmb";
        reg = <0x802800e0 0x40>;
        #power-domain-cells = <1>;
    };

    foo {
        power-domains = <&pmb BCM_PMB_PCIE0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/brcm,bcm63xx-power.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: BCM63xx power domain driver

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>

description: |
  BCM6318, BCM6328, BCM6362 and BCM63268 SoCs have a power domain controller
  to enable/disable certain components in order to save power.

properties:
  compatible:
    items:
      - enum:
          - brcm,bcm6318-power-controller
          - brcm,bcm6328-power-controller
          - brcm,bcm6362-power-controller
          - brcm,bcm63268-power-controller

  reg:
    maxItems: 1

  "#power-domain-cells":
    const: 1

required:
  - compatible
  - reg
  - "#power-domain-cells"

additionalProperties: false

examples:
  - |
    periph_pwr: power-controller@10001848 {
        compatible = "brcm,bcm6328-power-controller";
        reg = <0x10001848 0x4>;
        #power-domain-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PM Domain Idle States binding description

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

description:
  A domain idle state node represents the state parameters that will be used to
  select the state when there are no active components in the PM domain.

properties:
  $nodename:
    const: domain-idle-states

patternProperties:
  "^(cpu|cluster|domain)-":
    type: object
    additionalProperties: false
    description:
      Each state node represents a domain idle state description.

    properties:
      compatible:
        const: domain-idle-state

      entry-latency-us:
        description:
          The worst case latency in microseconds required to enter the idle
          state. Note that, the exit-latency-us duration may be guaranteed only
          after the entry-latency-us has passed.

      exit-latency-us:
        description:
          The worst case latency in microseconds required to exit the idle
          state.

      min-residency-us:
        description:
          The minimum residency duration in microseconds after which the idle
          state will yield power benefits, after overcoming the overhead while
          entering the idle state.

      arm,psci-suspend-param:
        $ref: /schemas/types.yaml#/definitions/uint32
        description: |
          power_state parameter to pass to the ARM PSCI suspend call.

          Device tree nodes that require usage of PSCI CPU_SUSPEND function
          (i.e. idle states node with entry-method property is set to "psci")
          must specify this property.

    required:
      - compatible
      - entry-latency-us
      - exit-latency-us
      - min-residency-us

additionalProperties: false

examples:
  - |

    domain-idle-states {
      domain_retention: domain-retention {
        compatible = "domain-idle-state";
        entry-latency-us = <20>;
        exit-latency-us = <40>;
        min-residency-us = <80>;
      };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX General Power Controller

maintainers:
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  The i.MX6 General Power Control (GPC) block contains DVFS load tracking
  counters and Power Gating Control (PGC).

  The power domains are generic power domain providers as documented in
  Documentation/devicetree/bindings/power/power-domain.yaml. They are
  described as subnodes of the power gating controller 'pgc' node of the GPC.

  IP cores belonging to a power domain should contain a 'power-domains'
  property that is a phandle pointing to the power domain the device belongs
  to.

properties:
  compatible:
    enum:
      - fsl,imx6q-gpc
      - fsl,imx6qp-gpc
      - fsl,imx6sl-gpc
      - fsl,imx6sx-gpc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: ipg

  pgc:
    type: object
    additionalProperties: false
    description: list of power domains provided by this controller.

    properties:
      '#address-cells':
        const: 1

      '#size-cells':
        const: 0

    patternProperties:
      "power-domain@[0-9]$":
        type: object
        additionalProperties: false

        properties:

          '#power-domain-cells':
            const: 0

          reg:
            description: |
              The following DOMAIN_INDEX values are valid for i.MX6Q:
                ARM_DOMAIN     0
                PU_DOMAIN      1
              The following additional DOMAIN_INDEX value is valid for i.MX6SL:
                DISPLAY_DOMAIN 2
              The following additional DOMAIN_INDEX value is valid for i.MX6SX:
                PCI_DOMAIN     3
            maxItems: 1

          clocks:
            description: |
              A number of phandles to clocks that need to be enabled during domain
              power-up sequencing to ensure reset propagation into devices located
              inside this power domain.
            minItems: 1
            maxItems: 7

          power-supply: true

        required:
          - '#power-domain-cells'
          - reg

    required:
      - '#address-cells'
      - '#size-cells'

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - pgc

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx6qdl-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gpc@20dc000 {
        compatible = "fsl,imx6q-gpc";
        reg = <0x020dc000 0x4000>;
        interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clks IMX6QDL_CLK_IPG>;
        clock-names = "ipg";

        pgc {
            #address-cells = <1>;
            #size-cells = <0>;

            power-domain@0 {
                reg = <0>;
                #power-domain-cells = <0>;
            };

            pd_pu: power-domain@1 {
                reg = <1>;
                #power-domain-cells = <0>;
                power-supply = <&reg_pu>;
                clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
                         <&clks IMX6QDL_CLK_GPU3D_SHADER>,
                         <&clks IMX6QDL_CLK_GPU2D_CORE>,
                         <&clks IMX6QDL_CLK_GPU2D_AXI>,
                         <&clks IMX6QDL_CLK_OPENVG_AXI>,
                         <&clks IMX6QDL_CLK_VPU_AXI>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/fsl,imx-gpcv2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX General Power Controller v2

maintainers:
  - Andrey Smirnov <andrew.smirnov@gmail.com>

description: |
  The i.MX7S/D General Power Control (GPC) block contains Power Gating
  Control (PGC) for various power domains.

  Power domains contained within GPC node are generic power domain
  providers, documented in
  Documentation/devicetree/bindings/power/power-domain.yaml, which are
  described as subnodes of the power gating controller 'pgc' node.

  IP cores belonging to a power domain should contain a 'power-domains'
  property that is a phandle for PGC node representing the domain.

properties:
  compatible:
    enum:
      - fsl,imx7d-gpc
      - fsl,imx8mn-gpc
      - fsl,imx8mq-gpc
      - fsl,imx8mm-gpc
      - fsl,imx8mp-gpc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-controller: true
  '#interrupt-cells':
    const: 3

  pgc:
    type: object
    additionalProperties: false
    description: list of power domains provided by this controller.

    properties:
      '#address-cells':
        const: 1

      '#size-cells':
        const: 0

    patternProperties:
      "power-domain@[0-9a-f]+$":
        type: object
        additionalProperties: false

        properties:

          '#power-domain-cells':
            const: 0

          reg:
            description: |
              Power domain index. Valid values are defined in
              include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
              include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
              include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc
              include/dt-bindings/power/imx8mp-power.h for fsl,imx8mp-gpc
            maxItems: 1

          clocks:
            description: |
              A number of phandles to clocks that need to be enabled during domain
              power-up sequencing to ensure reset propagation into devices located
              inside this power domain.
            minItems: 1
            maxItems: 5

          power-supply: true

          power-domains:
            maxItems: 1

          resets:
            description: |
              A number of phandles to resets that need to be asserted during
              power-up sequencing of the domain. The resets belong to devices
              located inside the power domain, which need to be held in reset
              across the power-up sequence. So no means to specify what each
              reset is in a generic power-domain binding.
            minItems: 1
            maxItems: 4

        required:
          - '#power-domain-cells'
          - reg

    required:
      - '#address-cells'
      - '#size-cells'

required:
  - compatible
  - reg
  - interrupts
  - pgc

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gpc@303a0000 {
        compatible = "fsl,imx7d-gpc";
        reg = <0x303a0000 0x1000>;
        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;

        pgc {
            #address-cells = <1>;
            #size-cells = <0>;

            pgc_mipi_phy: power-domain@0 {
                #power-domain-cells = <0>;
                reg = <0>;
                power-supply = <&reg_1p0d>;
            };

            pgc_pcie_phy: power-domain@1 {
                #power-domain-cells = <0>;
                reg = <1>;
                power-supply = <&reg_1p0d>;
            };

            pgc_hsic_phy: power-domain@2 {
                #power-domain-cells = <0>;
                reg = <2>;
                power-supply = <&reg_1p2>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/fsl,scu-pd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX SCU Client Device Node - Power domain bindings based on SCU Message Protocol

maintainers:
  - Dong Aisheng <aisheng.dong@nxp.com>

description: i.MX SCU Client Device Node
  Client nodes are maintained as children of the relevant IMX-SCU device node.
  Power domain bindings based on SCU Message Protocol

allOf:
  - $ref: power-domain.yaml#

properties:
  compatible:
    items:
      - enum:
          - fsl,imx8qm-scu-pd
          - fsl,imx8qxp-scu-pd
      - const: fsl,scu-pd

  '#power-domain-cells':
    const: 1

required:
  - compatible
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    power-controller {
        compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
        #power-domain-cells = <1>;
    };