code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP54XX Clock domains framework
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 *
 * Abhijit Pagare (abhijitpagare@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 * Paul Walmsley (paul@pwsan.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#include <linux/kernel.h>
#include <linux/io.h>

#include "clockdomain.h"
#include "cm1_54xx.h"
#include "cm2_54xx.h"

#include "cm-regbits-54xx.h"
#include "prm54xx.h"
#include "prcm44xx.h"
#include "prcm_mpu54xx.h"

/* Static Dependencies for OMAP4 Clock Domains */

static struct clkdm_dep c2c_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ .clkdm_name = "l3main2_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ NULL },
};

static struct clkdm_dep cam_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ NULL },
};

static struct clkdm_dep dma_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "dss_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "ipu_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "l4sec_clkdm" },
	{ .clkdm_name = "wkupaon_clkdm" },
	{ NULL },
};

static struct clkdm_dep dsp_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ .clkdm_name = "l3main2_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "wkupaon_clkdm" },
	{ NULL },
};

static struct clkdm_dep dss_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3main2_clkdm" },
	{ NULL },
};

static struct clkdm_dep gpu_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ NULL },
};

static struct clkdm_dep ipu_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "dsp_clkdm" },
	{ .clkdm_name = "dss_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "gpu_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ .clkdm_name = "l3main2_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "l4sec_clkdm" },
	{ .clkdm_name = "wkupaon_clkdm" },
	{ NULL },
};

static struct clkdm_dep iva_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ NULL },
};

static struct clkdm_dep l3init_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "l4sec_clkdm" },
	{ .clkdm_name = "wkupaon_clkdm" },
	{ NULL },
};

static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ NULL },
};

static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ .clkdm_name = "l3main2_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ NULL },
};

static struct clkdm_dep mpu_wkup_sleep_deps[] = {
	{ .clkdm_name = "abe_clkdm" },
	{ .clkdm_name = "dsp_clkdm" },
	{ .clkdm_name = "dss_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "gpu_clkdm" },
	{ .clkdm_name = "ipu_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ .clkdm_name = "l3main2_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "l4sec_clkdm" },
	{ .clkdm_name = "wkupaon_clkdm" },
	{ NULL },
};

static struct clockdomain l4sec_54xx_clkdm = {
	.name		  = "l4sec_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
	.dep_bit	  = OMAP54XX_L4SEC_STATDEP_SHIFT,
	.wkdep_srcs	  = l4sec_wkup_sleep_deps,
	.sleepdep_srcs	  = l4sec_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_SWSUP,
};

static struct clockdomain iva_54xx_clkdm = {
	.name		  = "iva_clkdm",
	.pwrdm		  = { .name = "iva_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_IVA_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
	.dep_bit	  = OMAP54XX_IVA_STATDEP_SHIFT,
	.wkdep_srcs	  = iva_wkup_sleep_deps,
	.sleepdep_srcs	  = iva_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain mipiext_54xx_clkdm = {
	.name		  = "mipiext_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
	.wkdep_srcs	  = mipiext_wkup_sleep_deps,
	.sleepdep_srcs	  = mipiext_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain l3main2_54xx_clkdm = {
	.name		  = "l3main2_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
	.dep_bit	  = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP,
};

static struct clockdomain l3main1_54xx_clkdm = {
	.name		  = "l3main1_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
	.dep_bit	  = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP,
};

static struct clockdomain custefuse_54xx_clkdm = {
	.name		  = "custefuse_clkdm",
	.pwrdm		  = { .name = "custefuse_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain ipu_54xx_clkdm = {
	.name		  = "ipu_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
	.dep_bit	  = OMAP54XX_IPU_STATDEP_SHIFT,
	.wkdep_srcs	  = ipu_wkup_sleep_deps,
	.sleepdep_srcs	  = ipu_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain l4cfg_54xx_clkdm = {
	.name		  = "l4cfg_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
	.dep_bit	  = OMAP54XX_L4CFG_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP,
};

static struct clockdomain abe_54xx_clkdm = {
	.name		  = "abe_clkdm",
	.pwrdm		  = { .name = "abe_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_AON_ABE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
	.dep_bit	  = OMAP54XX_ABE_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain dss_54xx_clkdm = {
	.name		  = "dss_clkdm",
	.pwrdm		  = { .name = "dss_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_DSS_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
	.dep_bit	  = OMAP54XX_DSS_STATDEP_SHIFT,
	.wkdep_srcs	  = dss_wkup_sleep_deps,
	.sleepdep_srcs	  = dss_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain dsp_54xx_clkdm = {
	.name		  = "dsp_clkdm",
	.pwrdm		  = { .name = "dsp_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_AON_DSP_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
	.dep_bit	  = OMAP54XX_DSP_STATDEP_SHIFT,
	.wkdep_srcs	  = dsp_wkup_sleep_deps,
	.sleepdep_srcs	  = dsp_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain c2c_54xx_clkdm = {
	.name		  = "c2c_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
	.wkdep_srcs	  = c2c_wkup_sleep_deps,
	.sleepdep_srcs	  = c2c_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain l4per_54xx_clkdm = {
	.name		  = "l4per_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
	.dep_bit	  = OMAP54XX_L4PER_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain gpu_54xx_clkdm = {
	.name		  = "gpu_clkdm",
	.pwrdm		  = { .name = "gpu_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_GPU_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
	.dep_bit	  = OMAP54XX_GPU_STATDEP_SHIFT,
	.wkdep_srcs	  = gpu_wkup_sleep_deps,
	.sleepdep_srcs	  = gpu_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain wkupaon_54xx_clkdm = {
	.name		  = "wkupaon_clkdm",
	.pwrdm		  = { .name = "wkupaon_pwrdm" },
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.cm_inst	  = OMAP54XX_PRM_WKUPAON_CM_INST,
	.clkdm_offs	  = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
	.dep_bit	  = OMAP54XX_WKUPAON_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain mpu0_54xx_clkdm = {
	.name		  = "mpu0_clkdm",
	.pwrdm		  = { .name = "cpu0_pwrdm" },
	.prcm_partition	  = OMAP54XX_PRCM_MPU_PARTITION,
	.cm_inst	  = OMAP54XX_PRCM_MPU_CM_C0_INST,
	.clkdm_offs	  = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain mpu1_54xx_clkdm = {
	.name		  = "mpu1_clkdm",
	.pwrdm		  = { .name = "cpu1_pwrdm" },
	.prcm_partition	  = OMAP54XX_PRCM_MPU_PARTITION,
	.cm_inst	  = OMAP54XX_PRCM_MPU_CM_C1_INST,
	.clkdm_offs	  = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain coreaon_54xx_clkdm = {
	.name		  = "coreaon_clkdm",
	.pwrdm		  = { .name = "coreaon_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_COREAON_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain mpu_54xx_clkdm = {
	.name		  = "mpu_clkdm",
	.pwrdm		  = { .name = "mpu_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_AON_MPU_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
	.wkdep_srcs	  = mpu_wkup_sleep_deps,
	.sleepdep_srcs	  = mpu_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain l3init_54xx_clkdm = {
	.name		  = "l3init_clkdm",
	.pwrdm		  = { .name = "l3init_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_L3INIT_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
	.dep_bit	  = OMAP54XX_L3INIT_STATDEP_SHIFT,
	.wkdep_srcs	  = l3init_wkup_sleep_deps,
	.sleepdep_srcs	  = l3init_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain dma_54xx_clkdm = {
	.name		  = "dma_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
	.wkdep_srcs	  = dma_wkup_sleep_deps,
	.sleepdep_srcs	  = dma_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain l3instr_54xx_clkdm = {
	.name		  = "l3instr_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
};

static struct clockdomain emif_54xx_clkdm = {
	.name		  = "emif_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
	.dep_bit	  = OMAP54XX_EMIF_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain emu_54xx_clkdm = {
	.name		  = "emu_clkdm",
	.pwrdm		  = { .name = "emu_pwrdm" },
	.prcm_partition	  = OMAP54XX_PRM_PARTITION,
	.cm_inst	  = OMAP54XX_PRM_EMU_CM_INST,
	.clkdm_offs	  = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain cam_54xx_clkdm = {
	.name		  = "cam_clkdm",
	.pwrdm		  = { .name = "cam_pwrdm" },
	.prcm_partition	  = OMAP54XX_CM_CORE_PARTITION,
	.cm_inst	  = OMAP54XX_CM_CORE_CAM_INST,
	.clkdm_offs	  = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
	.wkdep_srcs	  = cam_wkup_sleep_deps,
	.sleepdep_srcs	  = cam_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

/* As clockdomains are added or removed above, this list must also be changed */
static struct clockdomain *clockdomains_omap54xx[] __initdata = {
	&l4sec_54xx_clkdm,
	&iva_54xx_clkdm,
	&mipiext_54xx_clkdm,
	&l3main2_54xx_clkdm,
	&l3main1_54xx_clkdm,
	&custefuse_54xx_clkdm,
	&ipu_54xx_clkdm,
	&l4cfg_54xx_clkdm,
	&abe_54xx_clkdm,
	&dss_54xx_clkdm,
	&dsp_54xx_clkdm,
	&c2c_54xx_clkdm,
	&l4per_54xx_clkdm,
	&gpu_54xx_clkdm,
	&wkupaon_54xx_clkdm,
	&mpu0_54xx_clkdm,
	&mpu1_54xx_clkdm,
	&coreaon_54xx_clkdm,
	&mpu_54xx_clkdm,
	&l3init_54xx_clkdm,
	&dma_54xx_clkdm,
	&l3instr_54xx_clkdm,
	&emif_54xx_clkdm,
	&emu_54xx_clkdm,
	&cam_54xx_clkdm,
	NULL
};

void __init omap54xx_clockdomains_init(void)
{
	clkdm_register_platform_funcs(&omap4_clkdm_operations);
	clkdm_register_clkdms(clockdomains_omap54xx);
	clkdm_complete_init();
}


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * DRA7xx Clock domains framework
 *
 * Copyright (C) 2009-2013 Texas Instruments, Inc.
 * Copyright (C) 2009-2011 Nokia Corporation
 *
 * Generated by code originally written by:
 * Abhijit Pagare (abhijitpagare@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 * Paul Walmsley (paul@pwsan.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#include <linux/kernel.h>
#include <linux/io.h>

#include "clockdomain.h"
#include "cm1_7xx.h"
#include "cm2_7xx.h"

#include "cm-regbits-7xx.h"
#include "prm7xx.h"
#include "prcm44xx.h"
#include "prcm_mpu7xx.h"

/* Static Dependencies for DRA7xx Clock Domains */

static struct clkdm_dep cam_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ NULL },
};

static struct clkdm_dep dma_wkup_sleep_deps[] = {
	{ .clkdm_name = "dss_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "ipu_clkdm" },
	{ .clkdm_name = "ipu1_clkdm" },
	{ .clkdm_name = "ipu2_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "l4per2_clkdm" },
	{ .clkdm_name = "l4per3_clkdm" },
	{ .clkdm_name = "l4sec_clkdm" },
	{ .clkdm_name = "pcie_clkdm" },
	{ .clkdm_name = "wkupaon_clkdm" },
	{ NULL },
};

static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
	{ .clkdm_name = "atl_clkdm" },
	{ .clkdm_name = "cam_clkdm" },
	{ .clkdm_name = "dsp2_clkdm" },
	{ .clkdm_name = "dss_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "eve1_clkdm" },
	{ .clkdm_name = "eve2_clkdm" },
	{ .clkdm_name = "eve3_clkdm" },
	{ .clkdm_name = "eve4_clkdm" },
	{ .clkdm_name = "gmac_clkdm" },
	{ .clkdm_name = "gpu_clkdm" },
	{ .clkdm_name = "ipu_clkdm" },
	{ .clkdm_name = "ipu1_clkdm" },
	{ .clkdm_name = "ipu2_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "l4per2_clkdm" },
	{ .clkdm_name = "l4per3_clkdm" },
	{ .clkdm_name = "l4sec_clkdm" },
	{ .clkdm_name = "pcie_clkdm" },
	{ .clkdm_name = "vpe_clkdm" },
	{ .clkdm_name = "wkupaon_clkdm" },
	{ NULL },
};

static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
	{ .clkdm_name = "atl_clkdm" },
	{ .clkdm_name = "cam_clkdm" },
	{ .clkdm_name = "dsp1_clkdm" },
	{ .clkdm_name = "dss_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "eve1_clkdm" },
	{ .clkdm_name = "eve2_clkdm" },
	{ .clkdm_name = "eve3_clkdm" },
	{ .clkdm_name = "eve4_clkdm" },
	{ .clkdm_name = "gmac_clkdm" },
	{ .clkdm_name = "gpu_clkdm" },
	{ .clkdm_name = "ipu_clkdm" },
	{ .clkdm_name = "ipu1_clkdm" },
	{ .clkdm_name = "ipu2_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "l4per2_clkdm" },
	{ .clkdm_name = "l4per3_clkdm" },
	{ .clkdm_name = "l4sec_clkdm" },
	{ .clkdm_name = "pcie_clkdm" },
	{ .clkdm_name = "vpe_clkdm" },
	{ .clkdm_name = "wkupaon_clkdm" },
	{ NULL },
};

static struct clkdm_dep dss_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ NULL },
};

static struct clkdm_dep eve1_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "eve2_clkdm" },
	{ .clkdm_name = "eve3_clkdm" },
	{ .clkdm_name = "eve4_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ NULL },
};

static struct clkdm_dep eve2_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "eve1_clkdm" },
	{ .clkdm_name = "eve3_clkdm" },
	{ .clkdm_name = "eve4_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ NULL },
};

static struct clkdm_dep eve3_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "eve1_clkdm" },
	{ .clkdm_name = "eve2_clkdm" },
	{ .clkdm_name = "eve4_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ NULL },
};

static struct clkdm_dep eve4_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "eve1_clkdm" },
	{ .clkdm_name = "eve2_clkdm" },
	{ .clkdm_name = "eve3_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ NULL },
};

static struct clkdm_dep gmac_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "l4per2_clkdm" },
	{ NULL },
};

static struct clkdm_dep gpu_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ NULL },
};

static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
	{ .clkdm_name = "atl_clkdm" },
	{ .clkdm_name = "dsp1_clkdm" },
	{ .clkdm_name = "dsp2_clkdm" },
	{ .clkdm_name = "dss_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "eve1_clkdm" },
	{ .clkdm_name = "eve2_clkdm" },
	{ .clkdm_name = "eve3_clkdm" },
	{ .clkdm_name = "eve4_clkdm" },
	{ .clkdm_name = "gmac_clkdm" },
	{ .clkdm_name = "gpu_clkdm" },
	{ .clkdm_name = "ipu_clkdm" },
	{ .clkdm_name = "ipu2_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "l4per2_clkdm" },
	{ .clkdm_name = "l4per3_clkdm" },
	{ .clkdm_name = "l4sec_clkdm" },
	{ .clkdm_name = "pcie_clkdm" },
	{ .clkdm_name = "vpe_clkdm" },
	{ .clkdm_name = "wkupaon_clkdm" },
	{ NULL },
};

static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
	{ .clkdm_name = "atl_clkdm" },
	{ .clkdm_name = "dsp1_clkdm" },
	{ .clkdm_name = "dsp2_clkdm" },
	{ .clkdm_name = "dss_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "eve1_clkdm" },
	{ .clkdm_name = "eve2_clkdm" },
	{ .clkdm_name = "eve3_clkdm" },
	{ .clkdm_name = "eve4_clkdm" },
	{ .clkdm_name = "gmac_clkdm" },
	{ .clkdm_name = "gpu_clkdm" },
	{ .clkdm_name = "ipu_clkdm" },
	{ .clkdm_name = "ipu1_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "l4per2_clkdm" },
	{ .clkdm_name = "l4per3_clkdm" },
	{ .clkdm_name = "l4sec_clkdm" },
	{ .clkdm_name = "pcie_clkdm" },
	{ .clkdm_name = "vpe_clkdm" },
	{ .clkdm_name = "wkupaon_clkdm" },
	{ NULL },
};

static struct clkdm_dep iva_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ NULL },
};

static struct clkdm_dep l3init_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "l4per3_clkdm" },
	{ .clkdm_name = "l4sec_clkdm" },
	{ .clkdm_name = "wkupaon_clkdm" },
	{ NULL },
};

static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
	{ .clkdm_name = "dsp1_clkdm" },
	{ .clkdm_name = "dsp2_clkdm" },
	{ .clkdm_name = "ipu1_clkdm" },
	{ .clkdm_name = "ipu2_clkdm" },
	{ NULL },
};

static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ NULL },
};

static struct clkdm_dep mpu_wkup_sleep_deps[] = {
	{ .clkdm_name = "cam_clkdm" },
	{ .clkdm_name = "dsp1_clkdm" },
	{ .clkdm_name = "dsp2_clkdm" },
	{ .clkdm_name = "dss_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "eve1_clkdm" },
	{ .clkdm_name = "eve2_clkdm" },
	{ .clkdm_name = "eve3_clkdm" },
	{ .clkdm_name = "eve4_clkdm" },
	{ .clkdm_name = "gmac_clkdm" },
	{ .clkdm_name = "gpu_clkdm" },
	{ .clkdm_name = "ipu_clkdm" },
	{ .clkdm_name = "ipu1_clkdm" },
	{ .clkdm_name = "ipu2_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l3main1_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "l4per2_clkdm" },
	{ .clkdm_name = "l4per3_clkdm" },
	{ .clkdm_name = "l4sec_clkdm" },
	{ .clkdm_name = "pcie_clkdm" },
	{ .clkdm_name = "vpe_clkdm" },
	{ .clkdm_name = "wkupaon_clkdm" },
	{ NULL },
};

static struct clkdm_dep pcie_wkup_sleep_deps[] = {
	{ .clkdm_name = "atl_clkdm" },
	{ .clkdm_name = "cam_clkdm" },
	{ .clkdm_name = "dsp1_clkdm" },
	{ .clkdm_name = "dsp2_clkdm" },
	{ .clkdm_name = "dss_clkdm" },
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "eve1_clkdm" },
	{ .clkdm_name = "eve2_clkdm" },
	{ .clkdm_name = "eve3_clkdm" },
	{ .clkdm_name = "eve4_clkdm" },
	{ .clkdm_name = "gmac_clkdm" },
	{ .clkdm_name = "gpu_clkdm" },
	{ .clkdm_name = "ipu_clkdm" },
	{ .clkdm_name = "ipu1_clkdm" },
	{ .clkdm_name = "iva_clkdm" },
	{ .clkdm_name = "l3init_clkdm" },
	{ .clkdm_name = "l4cfg_clkdm" },
	{ .clkdm_name = "l4per_clkdm" },
	{ .clkdm_name = "l4per2_clkdm" },
	{ .clkdm_name = "l4per3_clkdm" },
	{ .clkdm_name = "l4sec_clkdm" },
	{ .clkdm_name = "vpe_clkdm" },
	{ NULL },
};

static struct clkdm_dep vpe_wkup_sleep_deps[] = {
	{ .clkdm_name = "emif_clkdm" },
	{ .clkdm_name = "l4per3_clkdm" },
	{ NULL },
};

static struct clockdomain l4per3_7xx_clkdm = {
	.name		  = "l4per3_clkdm",
	.pwrdm		  = { .name = "l4per_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_L4PER_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
	.dep_bit	  = DRA7XX_L4PER3_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain l4per2_7xx_clkdm = {
	.name		  = "l4per2_clkdm",
	.pwrdm		  = { .name = "l4per_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_L4PER_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
	.dep_bit	  = DRA7XX_L4PER2_STATDEP_SHIFT,
	.wkdep_srcs	  = l4per2_wkup_sleep_deps,
	.sleepdep_srcs	  = l4per2_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_SWSUP,
};

static struct clockdomain mpu0_7xx_clkdm = {
	.name		  = "mpu0_clkdm",
	.pwrdm		  = { .name = "cpu0_pwrdm" },
	.prcm_partition	  = DRA7XX_MPU_PRCM_PARTITION,
	.cm_inst	  = DRA7XX_MPU_PRCM_CM_C0_INST,
	.clkdm_offs	  = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain iva_7xx_clkdm = {
	.name		  = "iva_clkdm",
	.pwrdm		  = { .name = "iva_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_IVA_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
	.dep_bit	  = DRA7XX_IVA_STATDEP_SHIFT,
	.wkdep_srcs	  = iva_wkup_sleep_deps,
	.sleepdep_srcs	  = iva_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain coreaon_7xx_clkdm = {
	.name		  = "coreaon_clkdm",
	.pwrdm		  = { .name = "coreaon_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_COREAON_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain ipu1_7xx_clkdm = {
	.name		  = "ipu1_clkdm",
	.pwrdm		  = { .name = "ipu_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_AON_IPU_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
	.dep_bit	  = DRA7XX_IPU1_STATDEP_SHIFT,
	.wkdep_srcs	  = ipu1_wkup_sleep_deps,
	.sleepdep_srcs	  = ipu1_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain ipu2_7xx_clkdm = {
	.name		  = "ipu2_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
	.dep_bit	  = DRA7XX_IPU2_STATDEP_SHIFT,
	.wkdep_srcs	  = ipu2_wkup_sleep_deps,
	.sleepdep_srcs	  = ipu2_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain l3init_7xx_clkdm = {
	.name		  = "l3init_clkdm",
	.pwrdm		  = { .name = "l3init_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_L3INIT_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
	.dep_bit	  = DRA7XX_L3INIT_STATDEP_SHIFT,
	.wkdep_srcs	  = l3init_wkup_sleep_deps,
	.sleepdep_srcs	  = l3init_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain l4sec_7xx_clkdm = {
	.name		  = "l4sec_clkdm",
	.pwrdm		  = { .name = "l4per_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_L4PER_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
	.dep_bit	  = DRA7XX_L4SEC_STATDEP_SHIFT,
	.wkdep_srcs	  = l4sec_wkup_sleep_deps,
	.sleepdep_srcs	  = l4sec_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_SWSUP,
};

static struct clockdomain l3main1_7xx_clkdm = {
	.name		  = "l3main1_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
	.dep_bit	  = DRA7XX_L3MAIN1_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP,
};

static struct clockdomain vpe_7xx_clkdm = {
	.name		  = "vpe_clkdm",
	.pwrdm		  = { .name = "vpe_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_AON_VPE_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
	.dep_bit	  = DRA7XX_VPE_STATDEP_SHIFT,
	.wkdep_srcs	  = vpe_wkup_sleep_deps,
	.sleepdep_srcs	  = vpe_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain mpu_7xx_clkdm = {
	.name		  = "mpu_clkdm",
	.pwrdm		  = { .name = "mpu_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_AON_MPU_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
	.wkdep_srcs	  = mpu_wkup_sleep_deps,
	.sleepdep_srcs	  = mpu_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain custefuse_7xx_clkdm = {
	.name		  = "custefuse_clkdm",
	.pwrdm		  = { .name = "custefuse_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_CUSTEFUSE_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain ipu_7xx_clkdm = {
	.name		  = "ipu_clkdm",
	.pwrdm		  = { .name = "ipu_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_AON_IPU_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
	.dep_bit	  = DRA7XX_IPU_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_SWSUP,
};

static struct clockdomain mpu1_7xx_clkdm = {
	.name		  = "mpu1_clkdm",
	.pwrdm		  = { .name = "cpu1_pwrdm" },
	.prcm_partition	  = DRA7XX_MPU_PRCM_PARTITION,
	.cm_inst	  = DRA7XX_MPU_PRCM_CM_C1_INST,
	.clkdm_offs	  = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain gmac_7xx_clkdm = {
	.name		  = "gmac_clkdm",
	.pwrdm		  = { .name = "l3init_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_L3INIT_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
	.dep_bit	  = DRA7XX_GMAC_STATDEP_SHIFT,
	.wkdep_srcs	  = gmac_wkup_sleep_deps,
	.sleepdep_srcs	  = gmac_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain l4cfg_7xx_clkdm = {
	.name		  = "l4cfg_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
	.dep_bit	  = DRA7XX_L4CFG_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP,
};

static struct clockdomain dma_7xx_clkdm = {
	.name		  = "dma_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
	.wkdep_srcs	  = dma_wkup_sleep_deps,
	.sleepdep_srcs	  = dma_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain rtc_7xx_clkdm = {
	.name		  = "rtc_clkdm",
	.pwrdm		  = { .name = "rtc_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_AON_RTC_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain pcie_7xx_clkdm = {
	.name		  = "pcie_clkdm",
	.pwrdm		  = { .name = "l3init_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_L3INIT_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
	.dep_bit	  = DRA7XX_PCIE_STATDEP_SHIFT,
	.wkdep_srcs	  = pcie_wkup_sleep_deps,
	.sleepdep_srcs	  = pcie_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_SWSUP,
};

static struct clockdomain atl_7xx_clkdm = {
	.name		  = "atl_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
	.dep_bit	  = DRA7XX_ATL_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain l3instr_7xx_clkdm = {
	.name		  = "l3instr_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
};

static struct clockdomain dss_7xx_clkdm = {
	.name		  = "dss_clkdm",
	.pwrdm		  = { .name = "dss_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_DSS_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
	.dep_bit	  = DRA7XX_DSS_STATDEP_SHIFT,
	.wkdep_srcs	  = dss_wkup_sleep_deps,
	.sleepdep_srcs	  = dss_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain emif_7xx_clkdm = {
	.name		  = "emif_clkdm",
	.pwrdm		  = { .name = "core_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_CORE_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
	.dep_bit	  = DRA7XX_EMIF_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain emu_7xx_clkdm = {
	.name		  = "emu_clkdm",
	.pwrdm		  = { .name = "emu_pwrdm" },
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.cm_inst	  = DRA7XX_PRM_EMU_CM_INST,
	.clkdm_offs	  = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain dsp2_7xx_clkdm = {
	.name		  = "dsp2_clkdm",
	.pwrdm		  = { .name = "dsp2_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_AON_DSP2_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
	.dep_bit	  = DRA7XX_DSP2_STATDEP_SHIFT,
	.wkdep_srcs	  = dsp2_wkup_sleep_deps,
	.sleepdep_srcs	  = dsp2_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain dsp1_7xx_clkdm = {
	.name		  = "dsp1_clkdm",
	.pwrdm		  = { .name = "dsp1_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_AON_DSP1_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
	.dep_bit	  = DRA7XX_DSP1_STATDEP_SHIFT,
	.wkdep_srcs	  = dsp1_wkup_sleep_deps,
	.sleepdep_srcs	  = dsp1_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain cam_7xx_clkdm = {
	.name		  = "cam_clkdm",
	.pwrdm		  = { .name = "cam_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_CAM_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
	.dep_bit	  = DRA7XX_CAM_STATDEP_SHIFT,
	.wkdep_srcs	  = cam_wkup_sleep_deps,
	.sleepdep_srcs	  = cam_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_SWSUP,
};

static struct clockdomain l4per_7xx_clkdm = {
	.name		  = "l4per_clkdm",
	.pwrdm		  = { .name = "l4per_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_L4PER_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
	.dep_bit	  = DRA7XX_L4PER_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain gpu_7xx_clkdm = {
	.name		  = "gpu_clkdm",
	.pwrdm		  = { .name = "gpu_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_GPU_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
	.dep_bit	  = DRA7XX_GPU_STATDEP_SHIFT,
	.wkdep_srcs	  = gpu_wkup_sleep_deps,
	.sleepdep_srcs	  = gpu_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain eve4_7xx_clkdm = {
	.name		  = "eve4_clkdm",
	.pwrdm		  = { .name = "eve4_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_AON_EVE4_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
	.dep_bit	  = DRA7XX_EVE4_STATDEP_SHIFT,
	.wkdep_srcs	  = eve4_wkup_sleep_deps,
	.sleepdep_srcs	  = eve4_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain eve2_7xx_clkdm = {
	.name		  = "eve2_clkdm",
	.pwrdm		  = { .name = "eve2_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_AON_EVE2_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
	.dep_bit	  = DRA7XX_EVE2_STATDEP_SHIFT,
	.wkdep_srcs	  = eve2_wkup_sleep_deps,
	.sleepdep_srcs	  = eve2_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain eve3_7xx_clkdm = {
	.name		  = "eve3_clkdm",
	.pwrdm		  = { .name = "eve3_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_AON_EVE3_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
	.dep_bit	  = DRA7XX_EVE3_STATDEP_SHIFT,
	.wkdep_srcs	  = eve3_wkup_sleep_deps,
	.sleepdep_srcs	  = eve3_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain wkupaon_7xx_clkdm = {
	.name		  = "wkupaon_clkdm",
	.pwrdm		  = { .name = "wkupaon_pwrdm" },
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.cm_inst	  = DRA7XX_PRM_WKUPAON_CM_INST,
	.clkdm_offs	  = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
	.dep_bit	  = DRA7XX_WKUPAON_STATDEP_SHIFT,
	.flags		  = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};

static struct clockdomain eve1_7xx_clkdm = {
	.name		  = "eve1_clkdm",
	.pwrdm		  = { .name = "eve1_pwrdm" },
	.prcm_partition	  = DRA7XX_CM_CORE_AON_PARTITION,
	.cm_inst	  = DRA7XX_CM_CORE_AON_EVE1_INST,
	.clkdm_offs	  = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
	.dep_bit	  = DRA7XX_EVE1_STATDEP_SHIFT,
	.wkdep_srcs	  = eve1_wkup_sleep_deps,
	.sleepdep_srcs	  = eve1_wkup_sleep_deps,
	.flags		  = CLKDM_CAN_HWSUP_SWSUP,
};

/* As clockdomains are added or removed above, this list must also be changed */
static struct clockdomain *clockdomains_dra7xx[] __initdata = {
	&l4per3_7xx_clkdm,
	&l4per2_7xx_clkdm,
	&mpu0_7xx_clkdm,
	&iva_7xx_clkdm,
	&coreaon_7xx_clkdm,
	&ipu1_7xx_clkdm,
	&ipu2_7xx_clkdm,
	&l3init_7xx_clkdm,
	&l4sec_7xx_clkdm,
	&l3main1_7xx_clkdm,
	&vpe_7xx_clkdm,
	&mpu_7xx_clkdm,
	&custefuse_7xx_clkdm,
	&ipu_7xx_clkdm,
	&mpu1_7xx_clkdm,
	&gmac_7xx_clkdm,
	&l4cfg_7xx_clkdm,
	&dma_7xx_clkdm,
	&rtc_7xx_clkdm,
	&pcie_7xx_clkdm,
	&atl_7xx_clkdm,
	&l3instr_7xx_clkdm,
	&dss_7xx_clkdm,
	&emif_7xx_clkdm,
	&emu_7xx_clkdm,
	&dsp2_7xx_clkdm,
	&dsp1_7xx_clkdm,
	&cam_7xx_clkdm,
	&l4per_7xx_clkdm,
	&gpu_7xx_clkdm,
	&eve4_7xx_clkdm,
	&eve2_7xx_clkdm,
	&eve3_7xx_clkdm,
	&wkupaon_7xx_clkdm,
	&eve1_7xx_clkdm,
	NULL
};

void __init dra7xx_clockdomains_init(void)
{
	clkdm_register_platform_funcs(&omap4_clkdm_operations);
	clkdm_register_clkdms(clockdomains_dra7xx);
	clkdm_complete_init();
}

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * TI81XX Clock Domain data.
 *
 * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H

#include <linux/kernel.h>
#include <linux/io.h>

#include "clockdomain.h"
#include "cm81xx.h"

/*
 * Note that 814x seems to have HWSUP_SWSUP for many clockdomains
 * while 816x does not. According to the TRM, 816x only has HWSUP
 * for ALWON_L3_FAST. Also note that the TI tree clockdomains81xx.h
 * seems to have the related ifdef the wrong way around claiming
 * 816x supports HWSUP while 814x does not. For now, we only set
 * HWSUP for ALWON_L3_FAST as that seems to be supported for both
 * dm814x and dm816x.
 */

/* Common for 81xx */

static struct clockdomain alwon_l3_slow_81xx_clkdm = {
	.name		= "alwon_l3s_clkdm",
	.pwrdm		= { .name = "alwon_pwrdm" },
	.cm_inst	= TI81XX_CM_ALWON_MOD,
	.clkdm_offs	= TI81XX_CM_ALWON_L3_SLOW_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain alwon_l3_med_81xx_clkdm = {
	.name		= "alwon_l3_med_clkdm",
	.pwrdm		= { .name = "alwon_pwrdm" },
	.cm_inst	= TI81XX_CM_ALWON_MOD,
	.clkdm_offs	= TI81XX_CM_ALWON_L3_MED_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain alwon_l3_fast_81xx_clkdm = {
	.name		= "alwon_l3_fast_clkdm",
	.pwrdm		= { .name = "alwon_pwrdm" },
	.cm_inst	= TI81XX_CM_ALWON_MOD,
	.clkdm_offs	= TI81XX_CM_ALWON_L3_FAST_CLKDM,
	.flags		= CLKDM_CAN_HWSUP_SWSUP,
};

static struct clockdomain alwon_ethernet_81xx_clkdm = {
	.name		= "alwon_ethernet_clkdm",
	.pwrdm		= { .name = "alwon_pwrdm" },
	.cm_inst	= TI81XX_CM_ALWON_MOD,
	.clkdm_offs	= TI81XX_CM_ETHERNET_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain mmu_81xx_clkdm = {
	.name		= "mmu_clkdm",
	.pwrdm		= { .name = "alwon_pwrdm" },
	.cm_inst	= TI81XX_CM_ALWON_MOD,
	.clkdm_offs	= TI81XX_CM_MMU_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain mmu_cfg_81xx_clkdm = {
	.name		= "mmu_cfg_clkdm",
	.pwrdm		= { .name = "alwon_pwrdm" },
	.cm_inst	= TI81XX_CM_ALWON_MOD,
	.clkdm_offs	= TI81XX_CM_MMUCFG_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain default_l3_slow_81xx_clkdm = {
	.name		= "default_l3_slow_clkdm",
	.pwrdm		= { .name = "default_pwrdm" },
	.cm_inst	= TI81XX_CM_DEFAULT_MOD,
	.clkdm_offs	= TI816X_CM_DEFAULT_L3_SLOW_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain default_sata_81xx_clkdm = {
	.name		= "default_clkdm",
	.pwrdm		= { .name = "default_pwrdm" },
	.cm_inst	= TI81XX_CM_DEFAULT_MOD,
	.clkdm_offs	= TI816X_CM_DEFAULT_SATA_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

/* 816x only */

static struct clockdomain alwon_mpu_816x_clkdm = {
	.name		= "alwon_mpu_clkdm",
	.pwrdm		= { .name = "alwon_pwrdm" },
	.cm_inst	= TI81XX_CM_ALWON_MOD,
	.clkdm_offs	= TI81XX_CM_ALWON_MPU_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain active_gem_816x_clkdm = {
	.name		= "active_gem_clkdm",
	.pwrdm		= { .name = "active_pwrdm" },
	.cm_inst	= TI81XX_CM_ACTIVE_MOD,
	.clkdm_offs	= TI816X_CM_ACTIVE_GEM_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain ivahd0_816x_clkdm = {
	.name		= "ivahd0_clkdm",
	.pwrdm		= { .name = "ivahd0_pwrdm" },
	.cm_inst	= TI816X_CM_IVAHD0_MOD,
	.clkdm_offs	= TI816X_CM_IVAHD0_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain ivahd1_816x_clkdm = {
	.name		= "ivahd1_clkdm",
	.pwrdm		= { .name = "ivahd1_pwrdm" },
	.cm_inst	= TI816X_CM_IVAHD1_MOD,
	.clkdm_offs	= TI816X_CM_IVAHD1_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain ivahd2_816x_clkdm = {
	.name		= "ivahd2_clkdm",
	.pwrdm		= { .name = "ivahd2_pwrdm" },
	.cm_inst	= TI816X_CM_IVAHD2_MOD,
	.clkdm_offs	= TI816X_CM_IVAHD2_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain sgx_816x_clkdm = {
	.name		= "sgx_clkdm",
	.pwrdm		= { .name = "sgx_pwrdm" },
	.cm_inst	= TI81XX_CM_SGX_MOD,
	.clkdm_offs	= TI816X_CM_SGX_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain default_l3_med_816x_clkdm = {
	.name		= "default_l3_med_clkdm",
	.pwrdm		= { .name = "default_pwrdm" },
	.cm_inst	= TI81XX_CM_DEFAULT_MOD,
	.clkdm_offs	= TI816X_CM_DEFAULT_L3_MED_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain default_ducati_816x_clkdm = {
	.name		= "default_ducati_clkdm",
	.pwrdm		= { .name = "default_pwrdm" },
	.cm_inst	= TI81XX_CM_DEFAULT_MOD,
	.clkdm_offs	= TI816X_CM_DEFAULT_DUCATI_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain default_pci_816x_clkdm = {
	.name		= "default_pci_clkdm",
	.pwrdm		= { .name = "default_pwrdm" },
	.cm_inst	= TI81XX_CM_DEFAULT_MOD,
	.clkdm_offs	= TI816X_CM_DEFAULT_PCI_CLKDM,
	.flags		= CLKDM_CAN_SWSUP,
};

static struct clockdomain *clockdomains_ti814x[] __initdata = {
	&alwon_l3_slow_81xx_clkdm,
	&alwon_l3_med_81xx_clkdm,
	&alwon_l3_fast_81xx_clkdm,
	&alwon_ethernet_81xx_clkdm,
	&mmu_81xx_clkdm,
	&mmu_cfg_81xx_clkdm,
	&default_l3_slow_81xx_clkdm,
	&default_sata_81xx_clkdm,
	NULL,
};

void __init ti814x_clockdomains_init(void)
{
	clkdm_register_platform_funcs(&am33xx_clkdm_operations);
	clkdm_register_clkdms(clockdomains_ti814x);
	clkdm_complete_init();
}

static struct clockdomain *clockdomains_ti816x[] __initdata = {
	&alwon_mpu_816x_clkdm,
	&alwon_l3_slow_81xx_clkdm,
	&alwon_l3_med_81xx_clkdm,
	&alwon_l3_fast_81xx_clkdm,
	&alwon_ethernet_81xx_clkdm,
	&mmu_81xx_clkdm,
	&mmu_cfg_81xx_clkdm,
	&active_gem_816x_clkdm,
	&ivahd0_816x_clkdm,
	&ivahd1_816x_clkdm,
	&ivahd2_816x_clkdm,
	&sgx_816x_clkdm,
	&default_l3_med_816x_clkdm,
	&default_ducati_816x_clkdm,
	&default_pci_816x_clkdm,
	&default_l3_slow_81xx_clkdm,
	&default_sata_81xx_clkdm,
	NULL,
};

void __init ti816x_clockdomains_init(void)
{
	clkdm_register_platform_funcs(&am33xx_clkdm_operations);
	clkdm_register_clkdms(clockdomains_ti816x);
	clkdm_complete_init();
}
#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H

/*
 * OMAP24XX Clock Management register bits
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Copyright (C) 2007 Nokia Corporation
 *
 * Written by Paul Walmsley
 */

#define OMAP24XX_AUTOSTATE_MPU_MASK			(1 << 0)
#define OMAP24XX_EN_DSS1_MASK				(1 << 0)
#define OMAP24XX_ST_MAILBOXES_SHIFT			30
#define OMAP24XX_ST_HDQ_SHIFT				23
#define OMAP2420_ST_I2C2_SHIFT				20
#define OMAP2430_ST_I2CHS1_SHIFT			19
#define OMAP2420_ST_I2C1_SHIFT				19
#define OMAP2430_ST_I2CHS2_SHIFT			20
#define OMAP24XX_ST_MCBSP2_SHIFT			16
#define OMAP24XX_ST_MCBSP1_SHIFT			15
#define OMAP2430_ST_MCBSP5_SHIFT			5
#define OMAP2430_ST_MCBSP4_SHIFT			4
#define OMAP2430_ST_MCBSP3_SHIFT			3
#define OMAP24XX_ST_AES_SHIFT				3
#define OMAP24XX_ST_RNG_SHIFT				2
#define OMAP24XX_ST_SHA_SHIFT				1
#define OMAP24XX_CLKSEL_DSS2_MASK			(0x1 << 13)
#define OMAP24XX_AUTOSTATE_DSS_MASK			(1 << 2)
#define OMAP24XX_AUTOSTATE_L4_MASK			(1 << 1)
#define OMAP24XX_AUTOSTATE_L3_MASK			(1 << 0)
#define OMAP24XX_AUTOSTATE_GFX_MASK			(1 << 0)
#define OMAP24XX_ST_MPU_WDT_SHIFT			3
#define OMAP24XX_ST_32KSYNC_SHIFT			1
#define OMAP24XX_EN_54M_PLL_SHIFT			6
#define OMAP24XX_EN_96M_PLL_SHIFT			2
#define OMAP24XX_ST_54M_APLL_SHIFT			9
#define OMAP24XX_ST_96M_APLL_SHIFT			8
#define OMAP24XX_AUTO_54M_MASK				(0x3 << 6)
#define OMAP24XX_AUTO_96M_MASK				(0x3 << 2)
#define OMAP24XX_AUTO_DPLL_SHIFT			0
#define OMAP24XX_AUTO_DPLL_MASK				(0x3 << 0)
#define OMAP24XX_CORE_CLK_SRC_MASK			(0x3 << 0)
#define OMAP2420_AUTOSTATE_IVA_MASK			(1 << 8)
#define OMAP24XX_AUTOSTATE_DSP_MASK			(1 << 0)
#define OMAP2430_AUTOSTATE_MDM_MASK			(1 << 0)
#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO		0x0
#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO		0x1
#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * AM33XX Power Management register bits
 *
 * This file is automatically generated from the AM33XX hardware databases.
 * Vaibhav Hiremath <hvaibhav@ti.com>
 *
 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H

#define AM33XX_CLKOUT2DIV_SHIFT				3
#define AM33XX_CLKOUT2DIV_WIDTH				3
#define AM33XX_CLKOUT2EN_SHIFT				7
#define AM33XX_CLKOUT2SOURCE_MASK			(0x7 << 0)
#define AM33XX_CLKSEL_0_0_SHIFT				0
#define AM33XX_CLKSEL_0_0_WIDTH				1
#define AM33XX_CLKSEL_0_0_MASK				(1 << 0)
#define AM33XX_CLKSEL_0_1_MASK				(3 << 0)
#define AM33XX_CLKSEL_0_2_MASK				(7 << 0)
#define AM33XX_CLKSEL_GFX_FCLK_MASK			(1 << 1)
#define AM33XX_CLKTRCTRL_SHIFT				0
#define AM33XX_CLKTRCTRL_MASK				(0x3 << 0)
#define AM33XX_DPLL_CLKOUT_DIV_SHIFT			0
#define AM33XX_DPLL_CLKOUT_DIV_WIDTH			5
#define AM33XX_DPLL_DIV_MASK				(0x7f << 0)
#define AM33XX_DPLL_PER_DIV_MASK			(0xff << 0)
#define AM33XX_DPLL_EN_MASK				(0x7 << 0)
#define AM33XX_DPLL_MULT_MASK				(0x7ff << 8)
#define AM33XX_DPLL_MULT_PERIPH_MASK			(0xfff << 8)
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT		0
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH		5
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT		0
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH		5
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT		0
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH		5
#define AM33XX_IDLEST_SHIFT				16
#define AM33XX_IDLEST_MASK				(0x3 << 16)
#define AM33XX_MODULEMODE_SHIFT				0
#define AM33XX_MODULEMODE_MASK				(0x3 << 0)
#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT			30
#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT		19
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT		18
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT		18
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT		18
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT		18
#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT			27
#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH			3
#define AM33XX_STM_PMD_CLKSEL_SHIFT			22
#define AM33XX_STM_PMD_CLKSEL_WIDTH			2
#define AM33XX_ST_DPLL_CLK_MASK				(1 << 0)
#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT			8
#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT			24
#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH			3
#define AM33XX_TRC_PMD_CLKSEL_SHIFT			20
#define AM33XX_TRC_PMD_CLKSEL_WIDTH			2
#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H

/*
 * OMAP3430 Clock Management register bits
 *
 * Copyright (C) 2007-2008 Texas Instruments, Inc.
 * Copyright (C) 2007-2008 Nokia Corporation
 *
 * Written by Paul Walmsley
 */

#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK		(1 << 0)
#define OMAP3430_ST_IVA2_SHIFT				0
#define OMAP3430_CLKTRCTRL_IVA2_MASK			(0x3 << 0)
#define OMAP3430_CLKACTIVITY_IVA2_MASK			(1 << 0)
#define OMAP3430_CLKTRCTRL_MPU_MASK			(0x3 << 0)
#define OMAP3430_ST_AES2_SHIFT				28
#define OMAP3430_ST_SHA12_SHIFT				27
#define AM35XX_ST_UART4_SHIFT				23
#define OMAP3430_ST_HDQ_SHIFT				22
#define OMAP3430ES2_ST_SSI_IDLE_SHIFT			8
#define OMAP3430_ST_MAILBOXES_SHIFT			7
#define OMAP3430_ST_SAD2D_SHIFT				3
#define OMAP3430_ST_SDMA_SHIFT				2
#define OMAP3430ES2_ST_USBTLL_SHIFT			2
#define OMAP3430ES1_CLKTRCTRL_D2D_MASK			(0x3 << 4)
#define OMAP3430_CLKTRCTRL_L4_MASK			(0x3 << 2)
#define OMAP3430_CLKTRCTRL_L3_MASK			(0x3 << 0)
#define OMAP3430ES1_CLKTRCTRL_GFX_MASK			(0x3 << 0)
#define OMAP3430ES2_CLKTRCTRL_SGX_MASK			(0x3 << 0)
#define OMAP3430_ST_WDT2_SHIFT				5
#define OMAP3430_ST_32KSYNC_SHIFT			2
#define OMAP3430_AUTO_PERIPH_DPLL_MASK			(0x7 << 3)
#define OMAP3430ES2_ST_DSS_IDLE_SHIFT			1
#define OMAP3430_CLKTRCTRL_DSS_MASK			(0x3 << 0)
#define OMAP3430_CLKTRCTRL_CAM_MASK			(0x3 << 0)
#define OMAP3430_ST_MCBSP4_SHIFT			2
#define OMAP3430_ST_MCBSP3_SHIFT			1
#define OMAP3430_ST_MCBSP2_SHIFT			0
#define OMAP3430_CLKTRCTRL_PER_MASK			(0x3 << 0)
#define OMAP3430_CLKTRCTRL_EMU_MASK			(0x3 << 0)
#define OMAP3430_CLKTRCTRL_NEON_MASK			(0x3 << 0)
#define OMAP3430ES2_EN_USBHOST2_SHIFT			1
#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT		1
#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK		(3 << 0)
#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO		0x0
#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP		0x1
#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP		0x2
#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO		0x3
#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP44xx Clock Management register bits
 *
 * Copyright (C) 2009-2012 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H

#define OMAP4430_ABE_STATDEP_SHIFT				3
#define OMAP4430_CLKTRCTRL_SHIFT				0
#define OMAP4430_CLKTRCTRL_MASK					(0x3 << 0)
#define OMAP4430_DSS_STATDEP_SHIFT				8
#define OMAP4430_DUCATI_STATDEP_SHIFT				0
#define OMAP4430_GFX_STATDEP_SHIFT				10
#define OMAP4430_IDLEST_SHIFT					16
#define OMAP4430_IDLEST_MASK					(0x3 << 16)
#define OMAP4430_IVAHD_STATDEP_SHIFT				2
#define OMAP4430_L3INIT_STATDEP_SHIFT				7
#define OMAP4430_L3_1_STATDEP_SHIFT				5
#define OMAP4430_L3_2_STATDEP_SHIFT				6
#define OMAP4430_L4CFG_STATDEP_SHIFT				12
#define OMAP4430_L4PER_STATDEP_SHIFT				13
#define OMAP4430_L4SEC_STATDEP_SHIFT				14
#define OMAP4430_L4WKUP_STATDEP_SHIFT				15
#define OMAP4430_MEMIF_STATDEP_SHIFT				4
#define OMAP4430_MODULEMODE_SHIFT				0
#define OMAP4430_MODULEMODE_MASK				(0x3 << 0)
#define OMAP4430_TESLA_STATDEP_SHIFT				1
#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP54xx Clock Management register bits
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H

#define OMAP54XX_ABE_STATDEP_SHIFT					3
#define OMAP54XX_AUTO_DPLL_MODE_MASK					(0x7 << 0)
#define OMAP54XX_CLKSEL_SHIFT						24
#define OMAP54XX_CLKSEL_WIDTH						0x1
#define OMAP54XX_CLKSEL_0_0_SHIFT					0
#define OMAP54XX_CLKSEL_0_0_WIDTH					0x1
#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT					24
#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH					0x1
#define OMAP54XX_CLKSEL_DIV_SHIFT					25
#define OMAP54XX_CLKSEL_DIV_WIDTH					0x1
#define OMAP54XX_CLKSEL_FCLK_SHIFT					24
#define OMAP54XX_CLKSEL_FCLK_WIDTH					0x1
#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT				24
#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH				0x1
#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT				25
#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH				0x1
#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT				26
#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH				0x2
#define OMAP54XX_CLKSEL_OPP_SHIFT					0
#define OMAP54XX_CLKSEL_OPP_WIDTH					0x2
#define OMAP54XX_CLKSEL_SOURCE_SHIFT					24
#define OMAP54XX_CLKSEL_SOURCE_WIDTH					0x2
#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT			24
#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH			0x1
#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT					24
#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH					0x1
#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT					25
#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH					0x1
#define OMAP54XX_DIVHS_MASK						(0x3f << 0)
#define OMAP54XX_DIVHS_0_4_MASK						(0x1f << 0)
#define OMAP54XX_DIVHS_0_6_MASK						(0x7f << 0)
#define OMAP54XX_DPLL_DIV_MASK						(0x7f << 0)
#define OMAP54XX_DPLL_EN_MASK						(0x7 << 0)
#define OMAP54XX_DPLL_LPMODE_EN_MASK					(1 << 10)
#define OMAP54XX_DPLL_MULT_MASK						(0x7ff << 8)
#define OMAP54XX_DPLL_REGM4XEN_MASK					(1 << 11)
#define OMAP54XX_DPLL_SD_DIV_MASK					(0xff << 24)
#define OMAP54XX_DSP_STATDEP_SHIFT					1
#define OMAP54XX_DSS_STATDEP_SHIFT					8
#define OMAP54XX_EMIF_STATDEP_SHIFT					4
#define OMAP54XX_GPU_STATDEP_SHIFT					10
#define OMAP54XX_IPU_STATDEP_SHIFT					0
#define OMAP54XX_IVA_STATDEP_SHIFT					2
#define OMAP54XX_L3INIT_STATDEP_SHIFT					7
#define OMAP54XX_L3MAIN1_STATDEP_SHIFT					5
#define OMAP54XX_L3MAIN2_STATDEP_SHIFT					6
#define OMAP54XX_L4CFG_STATDEP_SHIFT					12
#define OMAP54XX_L4PER_STATDEP_SHIFT					13
#define OMAP54XX_L4SEC_STATDEP_SHIFT					14
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT				11
#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT				8
#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT				9
#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT					8
#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT				8
#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT					8
#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT					8
#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT			13
#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT			14
#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT			7
#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT				11
#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT				12
#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT				6
#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT				8
#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT				8
#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT				11
#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT				10
#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT				8
#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT				9
#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT				8
#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT				9
#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT				10
#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT				8
#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT				9
#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT				10
#define OMAP54XX_PAD_CLKS_GATE_SHIFT					8
#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT				10
#define OMAP54XX_ST_DPLL_CLK_MASK					(1 << 0)
#define OMAP54XX_SYS_CLKSEL_SHIFT					0
#define OMAP54XX_SYS_CLKSEL_WIDTH					0x3
#define OMAP54XX_WKUPAON_STATDEP_SHIFT					15
#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * DRA7xx Clock Management register bits
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
 *
 * Generated by code originally written by:
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H

#define DRA7XX_ATL_STATDEP_SHIFT				30
#define DRA7XX_CAM_STATDEP_SHIFT				9
#define DRA7XX_DSP1_STATDEP_SHIFT				1
#define DRA7XX_DSP2_STATDEP_SHIFT				18
#define DRA7XX_DSS_STATDEP_SHIFT				8
#define DRA7XX_EMIF_STATDEP_SHIFT				4
#define DRA7XX_EVE1_STATDEP_SHIFT				19
#define DRA7XX_EVE2_STATDEP_SHIFT				20
#define DRA7XX_EVE3_STATDEP_SHIFT				21
#define DRA7XX_EVE4_STATDEP_SHIFT				22
#define DRA7XX_GMAC_STATDEP_SHIFT				25
#define DRA7XX_GPU_STATDEP_SHIFT				10
#define DRA7XX_IPU1_STATDEP_SHIFT				23
#define DRA7XX_IPU2_STATDEP_SHIFT				0
#define DRA7XX_IPU_STATDEP_SHIFT				24
#define DRA7XX_IVA_STATDEP_SHIFT				2
#define DRA7XX_L3INIT_STATDEP_SHIFT				7
#define DRA7XX_L3MAIN1_STATDEP_SHIFT				5
#define DRA7XX_L4CFG_STATDEP_SHIFT				12
#define DRA7XX_L4PER2_STATDEP_SHIFT				26
#define DRA7XX_L4PER3_STATDEP_SHIFT				27
#define DRA7XX_L4PER_STATDEP_SHIFT				13
#define DRA7XX_L4SEC_STATDEP_SHIFT				14
#define DRA7XX_PCIE_STATDEP_SHIFT				29
#define DRA7XX_VPE_STATDEP_SHIFT				28
#define DRA7XX_WKUPAON_STATDEP_SHIFT				15
#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP2+ Clock Management prototypes
 *
 * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Written by Paul Walmsley
 */
#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
#define __ARCH_ASM_MACH_OMAP2_CM_H

/*
 * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
 * PRCM to request that a module exit the inactive state in the case of
 * OMAP2 & 3.
 * In the case of OMAP4 this is the max duration in microseconds for the
 * module to reach the functionnal state from an inactive state.
 */
#define MAX_MODULE_READY_TIME		2000

# ifndef __ASSEMBLER__
#include <linux/clk/ti.h>

#include "prcm-common.h"

extern struct omap_domain_base cm_base;
extern struct omap_domain_base cm2_base;
# endif

/*
 * MAX_MODULE_DISABLE_TIME: max duration in microseconds to wait for
 * the PRCM to request that a module enter the inactive state in the
 * case of OMAP2 & 3.  In the case of OMAP4 this is the max duration
 * in microseconds for the module to reach the inactive state from
 * a functional state.
 * XXX FSUSB on OMAP4430 takes ~4ms to idle after reset during
 * kernel init.
 */
#define MAX_MODULE_DISABLE_TIME		5000

# ifndef __ASSEMBLER__

/**
 * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
 * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
 * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
 * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl
 * @module_enable: ptr to the SoC CM-specific module_enable impl
 * @module_disable: ptr to the SoC CM-specific module_disable impl
 * @xlate_clkctrl: ptr to the SoC CM-specific clkctrl xlate addr impl
 */
struct cm_ll_data {
	int (*split_idlest_reg)(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,
				u8 *idlest_reg_id);
	int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
				 u8 idlest_shift);
	int (*wait_module_idle)(u8 part, s16 prcm_mod, u16 idlest_reg,
				u8 idlest_shift);
	void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
	void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
	u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs);
};

extern int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,
			       u8 *idlest_reg_id);
int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
			      u8 idlest_shift);
int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,
			     u8 idlest_shift);
int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs);
extern int cm_register(const struct cm_ll_data *cld);
extern int cm_unregister(const struct cm_ll_data *cld);
int omap_cm_init(void);
int omap2_cm_base_init(void);

# endif

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP44xx CM1 instance offset macros
 *
 * Copyright (C) 2009-2011 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
 *     or "OMAP4430".
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H

/* CM1 base address */
#define OMAP4430_CM1_BASE		0x4a004000

#define OMAP44XX_CM1_REGADDR(inst, reg)				\
	OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))

/* CM1 instances */
#define OMAP4430_CM1_OCP_SOCKET_INST	0x0000
#define OMAP4430_CM1_CKGEN_INST		0x0100
#define OMAP4430_CM1_MPU_INST		0x0300
#define OMAP4430_CM1_TESLA_INST		0x0400
#define OMAP4430_CM1_ABE_INST		0x0500

/* CM1 clockdomain register offsets (from instance start) */
#define OMAP4430_CM1_MPU_MPU_CDOFFS	0x0000
#define OMAP4430_CM1_TESLA_TESLA_CDOFFS	0x0000
#define OMAP4430_CM1_ABE_ABE_CDOFFS	0x0000

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP54xx CM1 instance offset macros
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H

/* CM1 base address */
#define OMAP54XX_CM_CORE_AON_BASE		0x4a004000

#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg)				\
	OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))

/* CM_CORE_AON instances */
#define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST	0x0000
#define OMAP54XX_CM_CORE_AON_CKGEN_INST		0x0100
#define OMAP54XX_CM_CORE_AON_MPU_INST		0x0300
#define OMAP54XX_CM_CORE_AON_DSP_INST		0x0400
#define OMAP54XX_CM_CORE_AON_ABE_INST		0x0500

/* CM_CORE_AON clockdomain register offsets (from instance start) */
#define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS	0x0000
#define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS	0x0000
#define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS	0x0000

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * DRA7xx CM1 instance offset macros
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
 *
 * Generated by code originally written by:
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H

/* CM1 base address */
#define DRA7XX_CM_CORE_AON_BASE		0x4a005000

#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg)				\
	OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))

/* CM_CORE_AON instances */
#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST	0x0000
#define DRA7XX_CM_CORE_AON_CKGEN_INST		0x0100
#define DRA7XX_CM_CORE_AON_MPU_INST		0x0300
#define DRA7XX_CM_CORE_AON_DSP1_INST		0x0400
#define DRA7XX_CM_CORE_AON_IPU_INST		0x0500
#define DRA7XX_CM_CORE_AON_DSP2_INST		0x0600
#define DRA7XX_CM_CORE_AON_EVE1_INST		0x0640
#define DRA7XX_CM_CORE_AON_EVE2_INST		0x0680
#define DRA7XX_CM_CORE_AON_EVE3_INST		0x06c0
#define DRA7XX_CM_CORE_AON_EVE4_INST		0x0700
#define DRA7XX_CM_CORE_AON_RTC_INST		0x0740
#define DRA7XX_CM_CORE_AON_VPE_INST		0x0760

/* CM_CORE_AON clockdomain register offsets (from instance start) */
#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS	0x0000
#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS	0x0000
#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS	0x0000
#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS	0x0040
#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS	0x0000
#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS	0x0000
#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS	0x0000
#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS	0x0000
#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS	0x0000
#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS	0x0000
#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS	0x0000

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP44xx CM2 instance offset macros
 *
 * Copyright (C) 2009-2011 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
 *     or "OMAP4430".
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H

/* CM2 base address */
#define OMAP4430_CM2_BASE		0x4a008000

#define OMAP44XX_CM2_REGADDR(inst, reg)				\
	OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg))

/* CM2 instances */
#define OMAP4430_CM2_OCP_SOCKET_INST	0x0000
#define OMAP4430_CM2_CKGEN_INST		0x0100
#define OMAP4430_CM2_ALWAYS_ON_INST	0x0600
#define OMAP4430_CM2_CORE_INST		0x0700
#define OMAP4430_CM2_IVAHD_INST		0x0f00
#define OMAP4430_CM2_CAM_INST		0x1000
#define OMAP4430_CM2_DSS_INST		0x1100
#define OMAP4430_CM2_GFX_INST		0x1200
#define OMAP4430_CM2_L3INIT_INST	0x1300
#define OMAP4430_CM2_L4PER_INST		0x1400
#define OMAP4430_CM2_CEFUSE_INST	0x1600

/* CM2 clockdomain register offsets (from instance start) */
#define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS	0x0000
#define OMAP4430_CM2_CORE_L3_1_CDOFFS		0x0000
#define OMAP4430_CM2_CORE_L3_2_CDOFFS		0x0100
#define OMAP4430_CM2_CORE_DUCATI_CDOFFS		0x0200
#define OMAP4430_CM2_CORE_SDMA_CDOFFS		0x0300
#define OMAP4430_CM2_CORE_MEMIF_CDOFFS		0x0400
#define OMAP4430_CM2_CORE_D2D_CDOFFS		0x0500
#define OMAP4430_CM2_CORE_L4CFG_CDOFFS		0x0600
#define OMAP4430_CM2_CORE_L3INSTR_CDOFFS	0x0700
#define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS		0x0000
#define OMAP4430_CM2_CAM_CAM_CDOFFS		0x0000
#define OMAP4430_CM2_DSS_DSS_CDOFFS		0x0000
#define OMAP4430_CM2_GFX_GFX_CDOFFS		0x0000
#define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS	0x0000
#define OMAP4430_CM2_L4PER_L4PER_CDOFFS		0x0000
#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS		0x0180
#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS	0x0000

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP54xx CM2 instance offset macros
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
 *
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
#define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H

/* CM2 base address */
#define OMAP54XX_CM_CORE_BASE		0x4a008000

#define OMAP54XX_CM_CORE_REGADDR(inst, reg)				\
	OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg))

/* CM_CORE instances */
#define OMAP54XX_CM_CORE_OCP_SOCKET_INST	0x0000
#define OMAP54XX_CM_CORE_CKGEN_INST		0x0100
#define OMAP54XX_CM_CORE_COREAON_INST		0x0600
#define OMAP54XX_CM_CORE_CORE_INST		0x0700
#define OMAP54XX_CM_CORE_IVA_INST		0x1200
#define OMAP54XX_CM_CORE_CAM_INST		0x1300
#define OMAP54XX_CM_CORE_DSS_INST		0x1400
#define OMAP54XX_CM_CORE_GPU_INST		0x1500
#define OMAP54XX_CM_CORE_L3INIT_INST		0x1600
#define OMAP54XX_CM_CORE_CUSTEFUSE_INST		0x1700

/* CM_CORE clockdomain register offsets (from instance start) */
#define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS		0x0000
#define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS		0x0000
#define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS		0x0100
#define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS		0x0200
#define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS		0x0300
#define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS		0x0400
#define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS		0x0500
#define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS		0x0600
#define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS		0x0700
#define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS		0x0800
#define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS		0x0900
#define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS		0x0a80
#define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS			0x0000
#define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS			0x0000
#define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS			0x0000
#define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS			0x0000
#define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS		0x0000
#define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS	0x0000

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * DRA7xx CM2 instance offset macros
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
 *
 * Generated by code originally written by:
 * Paul Walmsley (paul@pwsan.com)
 * Rajendra Nayak (rnayak@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H

/* CM2 base address */
#define DRA7XX_CM_CORE_BASE		0x4a008000

#define DRA7XX_CM_CORE_REGADDR(inst, reg)				\
	OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))

/* CM_CORE instances */
#define DRA7XX_CM_CORE_OCP_SOCKET_INST	0x0000
#define DRA7XX_CM_CORE_CKGEN_INST	0x0104
#define DRA7XX_CM_CORE_COREAON_INST	0x0600
#define DRA7XX_CM_CORE_CORE_INST	0x0700
#define DRA7XX_CM_CORE_IVA_INST		0x0f00
#define DRA7XX_CM_CORE_CAM_INST		0x1000
#define DRA7XX_CM_CORE_DSS_INST		0x1100
#define DRA7XX_CM_CORE_GPU_INST		0x1200
#define DRA7XX_CM_CORE_L3INIT_INST	0x1300
#define DRA7XX_CM_CORE_CUSTEFUSE_INST	0x1600
#define DRA7XX_CM_CORE_L4PER_INST	0x1700

/* CM_CORE clockdomain register offsets (from instance start) */
#define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS		0x0000
#define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS		0x0000
#define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS			0x0200
#define DRA7XX_CM_CORE_CORE_DMA_CDOFFS			0x0300
#define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS			0x0400
#define DRA7XX_CM_CORE_CORE_ATL_CDOFFS			0x0520
#define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS		0x0600
#define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS		0x0700
#define DRA7XX_CM_CORE_IVA_IVA_CDOFFS			0x0000
#define DRA7XX_CM_CORE_CAM_CAM_CDOFFS			0x0000
#define DRA7XX_CM_CORE_DSS_DSS_CDOFFS			0x0000
#define DRA7XX_CM_CORE_GPU_GPU_CDOFFS			0x0000
#define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS		0x0000
#define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS		0x00a0
#define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS		0x00c0
#define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS	0x0000
#define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS		0x0000
#define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS		0x0180
#define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS		0x01fc
#define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS		0x0210

#endif


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP2xxx CM module functions
 *
 * Copyright (C) 2009 Nokia Corporation
 * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
 * Paul Walmsley
 * Rajendra Nayak <rnayak@ti.com>
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>

#include "prm2xxx.h"
#include "cm.h"
#include "cm2xxx.h"
#include "cm-regbits-24xx.h"
#include "clockdomain.h"

/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
#define DPLL_AUTOIDLE_DISABLE				0x0
#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP		0x3

/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
#define OMAP2XXX_APLL_AUTOIDLE_DISABLE			0x0
#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP		0x3

/* CM_IDLEST_PLL bit value offset for APLLs (OMAP2xxx only) */
#define EN_APLL_LOCKED					3

static const u8 omap2xxx_cm_idlest_offs[] = {
	CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
};

/*
 *
 */

static void _write_clktrctrl(u8 c, s16 module, u32 mask)
{
	u32 v;

	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
	v &= ~mask;
	v |= c << __ffs(mask);
	omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
}

static bool omap2xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
{
	u32 v;

	v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
	v &= mask;
	v >>= __ffs(mask);

	return (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
}

static void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
{
	_write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
}

static void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
{
	_write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
}

/*
 * DPLL autoidle control
 */

static void _omap2xxx_set_dpll_autoidle(u8 m)
{
	u32 v;

	v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
	v &= ~OMAP24XX_AUTO_DPLL_MASK;
	v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
	omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
}

void omap2xxx_cm_set_dpll_disable_autoidle(void)
{
	_omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
}

void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
{
	_omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
}

/*
 * APLL control
 */

static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
{
	u32 v;

	v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
	v &= ~mask;
	v |= m << __ffs(mask);
	omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
}

void omap2xxx_cm_set_apll54_disable_autoidle(void)
{
	_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
				    OMAP24XX_AUTO_54M_MASK);
}

void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
{
	_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
				    OMAP24XX_AUTO_54M_MASK);
}

void omap2xxx_cm_set_apll96_disable_autoidle(void)
{
	_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
				    OMAP24XX_AUTO_96M_MASK);
}

void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
{
	_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
				    OMAP24XX_AUTO_96M_MASK);
}

/* Enable an APLL if off */
static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit)
{
	u32 v, m;

	m = EN_APLL_LOCKED << enable_bit;

	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
	if (v & m)
		return 0;   /* apll already enabled */

	v |= m;
	omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);

	omap2xxx_cm_wait_module_ready(0, PLL_MOD, 1, status_bit);

	/*
	 * REVISIT: Should we return an error code if
	 * omap2xxx_cm_wait_module_ready() fails?
	 */
	return 0;
}

/* Stop APLL */
static void _omap2xxx_apll_disable(u8 enable_bit)
{
	u32 v;

	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
	v &= ~(EN_APLL_LOCKED << enable_bit);
	omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN);
}

/* Enable an APLL if off */
int omap2xxx_cm_apll54_enable(void)
{
	return _omap2xxx_apll_enable(OMAP24XX_EN_54M_PLL_SHIFT,
				     OMAP24XX_ST_54M_APLL_SHIFT);
}

/* Enable an APLL if off */
int omap2xxx_cm_apll96_enable(void)
{
	return _omap2xxx_apll_enable(OMAP24XX_EN_96M_PLL_SHIFT,
				     OMAP24XX_ST_96M_APLL_SHIFT);
}

/* Stop APLL */
void omap2xxx_cm_apll54_disable(void)
{
	_omap2xxx_apll_disable(OMAP24XX_EN_54M_PLL_SHIFT);
}

/* Stop APLL */
void omap2xxx_cm_apll96_disable(void)
{
	_omap2xxx_apll_disable(OMAP24XX_EN_96M_PLL_SHIFT);
}

/**
 * omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
 * @idlest_reg: CM_IDLEST* virtual address
 * @prcm_inst: pointer to an s16 to return the PRCM instance offset
 * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
 *
 * XXX This function is only needed until absolute register addresses are
 * removed from the OMAP struct clk records.
 */
static int omap2xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
					s16 *prcm_inst,
					u8 *idlest_reg_id)
{
	unsigned long offs;
	u8 idlest_offs;
	int i;

	idlest_offs = idlest_reg->offset & 0xff;
	for (i = 0; i < ARRAY_SIZE(omap2xxx_cm_idlest_offs); i++) {
		if (idlest_offs == omap2xxx_cm_idlest_offs[i]) {
			*idlest_reg_id = i + 1;
			break;
		}
	}

	if (i == ARRAY_SIZE(omap2xxx_cm_idlest_offs))
		return -EINVAL;

	offs = idlest_reg->offset;
	offs &= 0xff00;
	*prcm_inst = offs;

	return 0;
}

/*
 *
 */

/**
 * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
 * @part: PRCM partition, ignored for OMAP2
 * @prcm_mod: PRCM module offset
 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
 *
 * Wait for the PRCM to indicate that the module identified by
 * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
 * success or -EBUSY if the module doesn't enable in time.
 */
int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
				  u8 idlest_shift)
{
	int ena = 0, i = 0;
	u8 cm_idlest_reg;
	u32 mask;

	if (!idlest_id || (idlest_id > ARRAY_SIZE(omap2xxx_cm_idlest_offs)))
		return -EINVAL;

	cm_idlest_reg = omap2xxx_cm_idlest_offs[idlest_id - 1];

	mask = 1 << idlest_shift;
	ena = mask;

	omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
			    mask) == ena), MAX_MODULE_READY_TIME, i);

	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}

/* Clockdomain low-level functions */

static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
{
	omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
				       clkdm->clktrctrl_mask);
}

static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
{
	omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
					clkdm->clktrctrl_mask);
}

static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
{
	bool hwsup = false;

	if (!clkdm->clktrctrl_mask)
		return 0;

	hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
					      clkdm->clktrctrl_mask);
	if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
		omap2xxx_clkdm_wakeup(clkdm);

	return 0;
}

static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
{
	bool hwsup = false;

	if (!clkdm->clktrctrl_mask)
		return 0;

	hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
					      clkdm->clktrctrl_mask);

	if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
		omap2xxx_clkdm_sleep(clkdm);

	return 0;
}

struct clkdm_ops omap2_clkdm_operations = {
	.clkdm_add_wkdep	= omap2_clkdm_add_wkdep,
	.clkdm_del_wkdep	= omap2_clkdm_del_wkdep,
	.clkdm_read_wkdep	= omap2_clkdm_read_wkdep,
	.clkdm_clear_all_wkdeps	= omap2_clkdm_clear_all_wkdeps,
	.clkdm_sleep		= omap2xxx_clkdm_sleep,
	.clkdm_wakeup		= omap2xxx_clkdm_wakeup,
	.clkdm_allow_idle	= omap2xxx_clkdm_allow_idle,
	.clkdm_deny_idle	= omap2xxx_clkdm_deny_idle,
	.clkdm_clk_enable	= omap2xxx_clkdm_clk_enable,
	.clkdm_clk_disable	= omap2xxx_clkdm_clk_disable,
};

int omap2xxx_cm_fclks_active(void)
{
	u32 f1, f2;

	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);

	return (f1 | f2) ? 1 : 0;
}

int omap2xxx_cm_mpu_retention_allowed(void)
{
	u32 l;

	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
		 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
		 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
		return 0;
	/* Check for UART3. */
	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
	if (l & OMAP24XX_EN_UART3_MASK)
		return 0;

	return 1;
}

u32 omap2xxx_cm_get_core_clk_src(void)
{
	u32 v;

	v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
	v &= OMAP24XX_CORE_CLK_SRC_MASK;

	return v;
}

u32 omap2xxx_cm_get_core_pll_config(void)
{
	return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
}

void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
{
	u32 tmp;

	omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL);
	omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL);
	omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL);
	tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
		OMAP24XX_CLKSEL_DSS2_MASK;
	omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
	if (mdm)
		omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
}

/*
 *
 */

static const struct cm_ll_data omap2xxx_cm_ll_data = {
	.split_idlest_reg	= &omap2xxx_cm_split_idlest_reg,
	.wait_module_ready	= &omap2xxx_cm_wait_module_ready,
};

int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
{
	return cm_register(&omap2xxx_cm_ll_data);
}

static void __exit omap2xxx_cm_exit(void)
{
	cm_unregister(&omap2xxx_cm_ll_data);
}
__exitcall(omap2xxx_cm_exit);


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP2xxx Clock Management (CM) register definitions
 *
 * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
 * Copyright (C) 2007-2010 Nokia Corporation
 * Paul Walmsley
 *
 * The CM hardware modules on the OMAP2/3 are quite similar to each
 * other.  The CM modules/instances on OMAP4 are quite different, so
 * they are handled in a separate file.
 */
#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H
#define __ARCH_ASM_MACH_OMAP2_CM2XXX_H

#include "prcm-common.h"
#include "cm2xxx_3xxx.h"

#define OMAP2420_CM_REGADDR(module, reg)				\
			OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
#define OMAP2430_CM_REGADDR(module, reg)				\
			OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))

/*
 * Module specific CM register offsets from CM_BASE + domain offset
 * Use cm_{read,write}_mod_reg() with these registers.
 * These register offsets generally appear in more than one PRCM submodule.
 */

/* OMAP2-specific register offsets */

#define OMAP24XX_CM_FCLKEN2				0x0004
#define OMAP24XX_CM_ICLKEN4				0x001c
#define OMAP24XX_CM_AUTOIDLE4				0x003c
#define OMAP24XX_CM_IDLEST4				0x002c

/* CM_IDLEST bit field values to indicate deasserted IdleReq */

#define OMAP24XX_CM_IDLEST_VAL				0

/* Clock management domain register get/set */

#ifndef __ASSEMBLER__

extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);

extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);

int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
				  u8 idlest_shift);
extern int omap2xxx_cm_fclks_active(void);
extern int omap2xxx_cm_mpu_retention_allowed(void);
extern u32 omap2xxx_cm_get_core_clk_src(void);
extern u32 omap2xxx_cm_get_core_pll_config(void);
extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
					 u32 mdm);

int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);

#endif

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * OMAP2/3 Clock Management (CM) register definitions
 *
 * Copyright (C) 2007-2009 Texas Instruments, Inc.
 * Copyright (C) 2007-2010 Nokia Corporation
 * Paul Walmsley
 *
 * The CM hardware modules on the OMAP2/3 are quite similar to each
 * other.  The CM modules/instances on OMAP4 are quite different, so
 * they are handled in a separate file.
 */
#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
#define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H

#include "cm.h"

/*
 * Module specific CM register offsets from CM_BASE + domain offset
 * Use cm_{read,write}_mod_reg() with these registers.
 * These register offsets generally appear in more than one PRCM submodule.
 */

/* Common between OMAP2 and OMAP3 */

#define CM_FCLKEN					0x0000
#define CM_FCLKEN1					CM_FCLKEN
#define CM_CLKEN					CM_FCLKEN
#define CM_ICLKEN					0x0010
#define CM_ICLKEN1					CM_ICLKEN
#define CM_ICLKEN2					0x0014
#define CM_ICLKEN3					0x0018
#define CM_IDLEST					0x0020
#define CM_IDLEST1					CM_IDLEST
#define CM_IDLEST2					0x0024
#define OMAP2430_CM_IDLEST3				0x0028
#define CM_AUTOIDLE					0x0030
#define CM_AUTOIDLE1					CM_AUTOIDLE
#define CM_AUTOIDLE2					0x0034
#define CM_AUTOIDLE3					0x0038
#define CM_CLKSEL					0x0040
#define CM_CLKSEL1					CM_CLKSEL
#define CM_CLKSEL2					0x0044
#define OMAP2_CM_CLKSTCTRL				0x0048

#ifndef __ASSEMBLER__

#include <linux/io.h>

static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
{
	return readl_relaxed(cm_base.va + module + idx);
}

static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
{
	writel_relaxed(val, cm_base.va + module + idx);
}

/* Read-modify-write a register in a CM module. Caller must lock */
static inline u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
					    s16 idx)
{
	u32 v;

	v = omap2_cm_read_mod_reg(module, idx);
	v &= ~mask;
	v |= bits;
	omap2_cm_write_mod_reg(v, module, idx);

	return v;
}

/* Read a CM register, AND it, and shift the result down to bit 0 */
static inline u32 omap2_cm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
{
	u32 v;

	v = omap2_cm_read_mod_reg(domain, idx);
	v &= mask;
	v >>= __ffs(mask);

	return v;
}

static inline u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
	return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
}

static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
	return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
}

extern int omap2xxx_cm_apll54_enable(void);
extern void omap2xxx_cm_apll54_disable(void);
extern int omap2xxx_cm_apll96_enable(void);
extern void omap2xxx_cm_apll96_disable(void);

#endif

/* CM register bits shared between 24XX and 3430 */

/* CM_CLKSEL_GFX */
#define OMAP_CLKSEL_GFX_SHIFT				0
#define OMAP_CLKSEL_GFX_MASK				(0x7 << 0)
#define OMAP_CLKSEL_GFX_WIDTH				3

/* CM_ICLKEN_GFX */
#define OMAP_EN_GFX_SHIFT				0
#define OMAP_EN_GFX_MASK				(1 << 0)

/* CM_IDLEST_GFX */
#define OMAP_ST_GFX_MASK				(1 << 0)

#endif


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * AM33XX CM functions
 *
 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
 * Vaibhav Hiremath <hvaibhav@ti.com>
 *
 * Reference taken from from OMAP4 cminst44xx.c
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>

#include "clockdomain.h"
#include "cm.h"
#include "cm33xx.h"
#include "cm-regbits-34xx.h"
#include "cm-regbits-33xx.h"
#include "prm33xx.h"

/*
 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
 *
 *   0x0 func:     Module is fully functional, including OCP
 *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
 *                 abortion
 *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
 *                 using separate functional clock
 *   0x3 disabled: Module is disabled and cannot be accessed
 *
 */
#define CLKCTRL_IDLEST_FUNCTIONAL		0x0
#define CLKCTRL_IDLEST_INTRANSITION		0x1
#define CLKCTRL_IDLEST_INTERFACE_IDLE		0x2
#define CLKCTRL_IDLEST_DISABLED			0x3

/* Private functions */

/* Read a register in a CM instance */
static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
{
	return readl_relaxed(cm_base.va + inst + idx);
}

/* Write into a register in a CM */
static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
{
	writel_relaxed(val, cm_base.va + inst + idx);
}

/* Read-modify-write a register in CM */
static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
{
	u32 v;

	v = am33xx_cm_read_reg(inst, idx);
	v &= ~mask;
	v |= bits;
	am33xx_cm_write_reg(v, inst, idx);

	return v;
}

static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
{
	u32 v;

	v = am33xx_cm_read_reg(inst, idx);
	v &= mask;
	v >>= __ffs(mask);

	return v;
}

/**
 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
 * @inst: CM instance register offset (*_INST macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
 * bit 0.
 */
static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs)
{
	u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
	v &= AM33XX_IDLEST_MASK;
	v >>= AM33XX_IDLEST_SHIFT;
	return v;
}

/**
 * _is_module_ready - can module registers be accessed without causing an abort?
 * @inst: CM instance register offset (*_INST macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
 */
static bool _is_module_ready(u16 inst, u16 clkctrl_offs)
{
	u32 v;

	v = _clkctrl_idlest(inst, clkctrl_offs);

	return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
		v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
}

/**
 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
 * @inst: CM instance register offset (*_INST macro)
 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 *
 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
 * will handle the shift itself.
 */
static void _clktrctrl_write(u8 c, u16 inst, u16 cdoffs)
{
	u32 v;

	v = am33xx_cm_read_reg(inst, cdoffs);
	v &= ~AM33XX_CLKTRCTRL_MASK;
	v |= c << AM33XX_CLKTRCTRL_SHIFT;
	am33xx_cm_write_reg(v, inst, cdoffs);
}

/* Public functions */

/**
 * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
 * @inst: CM instance register offset (*_INST macro)
 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 *
 * Returns true if the clockdomain referred to by (@inst, @cdoffs)
 * is in hardware-supervised idle mode, or 0 otherwise.
 */
static bool am33xx_cm_is_clkdm_in_hwsup(u16 inst, u16 cdoffs)
{
	u32 v;

	v = am33xx_cm_read_reg(inst, cdoffs);
	v &= AM33XX_CLKTRCTRL_MASK;
	v >>= AM33XX_CLKTRCTRL_SHIFT;

	return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
}

/**
 * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
 * @inst: CM instance register offset (*_INST macro)
 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 *
 * Put a clockdomain referred to by (@inst, @cdoffs) into
 * hardware-supervised idle mode.  No return value.
 */
static void am33xx_cm_clkdm_enable_hwsup(u16 inst, u16 cdoffs)
{
	_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
}

/**
 * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
 * @inst: CM instance register offset (*_INST macro)
 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 *
 * Put a clockdomain referred to by (@inst, @cdoffs) into
 * software-supervised idle mode, i.e., controlled manually by the
 * Linux OMAP clockdomain code.  No return value.
 */
static void am33xx_cm_clkdm_disable_hwsup(u16 inst, u16 cdoffs)
{
	_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
}

/**
 * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle
 * @inst: CM instance register offset (*_INST macro)
 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 *
 * Put a clockdomain referred to by (@inst, @cdoffs) into idle
 * No return value.
 */
static void am33xx_cm_clkdm_force_sleep(u16 inst, u16 cdoffs)
{
	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
}

/**
 * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle
 * @inst: CM instance register offset (*_INST macro)
 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 *
 * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
 * waking it up.  No return value.
 */
static void am33xx_cm_clkdm_force_wakeup(u16 inst, u16 cdoffs)
{
	_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
}

/*
 *
 */

/**
 * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
 * @part: PRCM partition, ignored for AM33xx
 * @inst: CM instance register offset (*_INST macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 * @bit_shift: bit shift for the register, ignored for AM33xx
 *
 * Wait for the module IDLEST to be functional. If the idle state is in any
 * the non functional state (trans, idle or disabled), module and thus the
 * sysconfig cannot be accessed and will probably lead to an "imprecise
 * external abort"
 */
static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
				       u8 bit_shift)
{
	int i = 0;

	omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
			  MAX_MODULE_READY_TIME, i);

	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}

/**
 * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
 * state
 * @part: CM partition, ignored for AM33xx
 * @inst: CM instance register offset (*_INST macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 * @bit_shift: bit shift for the register, ignored for AM33xx
 *
 * Wait for the module IDLEST to be disabled. Some PRCM transition,
 * like reset assertion or parent clock de-activation must wait the
 * module to be fully disabled.
 */
static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
				      u8 bit_shift)
{
	int i = 0;

	omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) ==
				CLKCTRL_IDLEST_DISABLED),
				MAX_MODULE_READY_TIME, i);

	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}

/**
 * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
 * @mode: Module mode (SW or HW)
 * @part: CM partition, ignored for AM33xx
 * @inst: CM instance register offset (*_INST macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * No return value.
 */
static void am33xx_cm_module_enable(u8 mode, u8 part, u16 inst,
				    u16 clkctrl_offs)
{
	u32 v;

	v = am33xx_cm_read_reg(inst, clkctrl_offs);
	v &= ~AM33XX_MODULEMODE_MASK;
	v |= mode << AM33XX_MODULEMODE_SHIFT;
	am33xx_cm_write_reg(v, inst, clkctrl_offs);
}

/**
 * am33xx_cm_module_disable - Disable the module inside CLKCTRL
 * @part: CM partition, ignored for AM33xx
 * @inst: CM instance register offset (*_INST macro)
 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
 *
 * No return value.
 */
static void am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
{
	u32 v;

	v = am33xx_cm_read_reg(inst, clkctrl_offs);
	v &= ~AM33XX_MODULEMODE_MASK;
	am33xx_cm_write_reg(v, inst, clkctrl_offs);
}

/*
 * Clockdomain low-level functions
 */

static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
{
	am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
	return 0;
}

static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
{
	am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
	return 0;
}

static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
{
	am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
}

static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
{
	am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
}

static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
{
	if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
		return am33xx_clkdm_wakeup(clkdm);

	return 0;
}

static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
{
	bool hwsup = false;

	hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);

	if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
		am33xx_clkdm_sleep(clkdm);

	return 0;
}

static u32 am33xx_cm_xlate_clkctrl(u8 part, u16 inst, u16 offset)
{
	return cm_base.pa + inst + offset;
}

/**
 * am33xx_clkdm_save_context - Save the clockdomain transition context
 * @clkdm: The clockdomain pointer whose context needs to be saved
 *
 * Save the clockdomain transition context.
 */
static int am33xx_clkdm_save_context(struct clockdomain *clkdm)
{
	clkdm->context = am33xx_cm_read_reg_bits(clkdm->cm_inst,
						 clkdm->clkdm_offs,
						 AM33XX_CLKTRCTRL_MASK);

	return 0;
}

/**
 * am33xx_restore_save_context - Restore the clockdomain transition context
 * @clkdm: The clockdomain pointer whose context needs to be restored
 *
 * Restore the clockdomain transition context.
 */
static int am33xx_clkdm_restore_context(struct clockdomain *clkdm)
{
	switch (clkdm->context) {
	case OMAP34XX_CLKSTCTRL_DISABLE_AUTO:
		am33xx_clkdm_deny_idle(clkdm);
		break;
	case OMAP34XX_CLKSTCTRL_FORCE_SLEEP:
		am33xx_clkdm_sleep(clkdm);
		break;
	case OMAP34XX_CLKSTCTRL_FORCE_WAKEUP:
		am33xx_clkdm_wakeup(clkdm);
		break;
	case OMAP34XX_CLKSTCTRL_ENABLE_AUTO:
		am33xx_clkdm_allow_idle(clkdm);
		break;
	}
	return 0;
}

struct clkdm_ops am33xx_clkdm_operations = {
	.clkdm_sleep		= am33xx_clkdm_sleep,
	.clkdm_wakeup		= am33xx_clkdm_wakeup,
	.clkdm_allow_idle	= am33xx_clkdm_allow_idle,
	.clkdm_deny_idle	= am33xx_clkdm_deny_idle,
	.clkdm_clk_enable	= am33xx_clkdm_clk_enable,
	.clkdm_clk_disable	= am33xx_clkdm_clk_disable,
	.clkdm_save_context	= am33xx_clkdm_save_context,
	.clkdm_restore_context	= am33xx_clkdm_restore_context,
};

static const struct cm_ll_data am33xx_cm_ll_data = {
	.wait_module_ready	= &am33xx_cm_wait_module_ready,
	.wait_module_idle	= &am33xx_cm_wait_module_idle,
	.module_enable		= &am33xx_cm_module_enable,
	.module_disable		= &am33xx_cm_module_disable,
	.xlate_clkctrl		= &am33xx_cm_xlate_clkctrl,
};

int __init am33xx_cm_init(const struct omap_prcm_init_data *data)
{
	return cm_register(&am33xx_cm_ll_data);
}

static void __exit am33xx_cm_exit(void)
{
	cm_unregister(&am33xx_cm_ll_data);
}
__exitcall(am33xx_cm_exit);