code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2022 Amarulasolutions
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/ovti,ov5693.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Omnivision OV5693 CMOS Sensor

maintainers:
  - Tommaso Merciai <tommaso.merciai@amarulasolutions.com>

description: |
  The Omnivision OV5693 is a high performance, 1/4-inch, 5 megapixel, CMOS
  image sensor that delivers 2592x1944 at 30fps. It provides full-frame,
  sub-sampled, and windowed 10-bit MIPI images in various formats via the
  Serial Camera Control Bus (SCCB) interface.

  OV5693 is controlled via I2C and two-wire Serial Camera Control Bus (SCCB).
  The sensor output is available via CSI-2 serial data output (up to 2-lane).

allOf:
  - $ref: /schemas/media/video-interface-devices.yaml#

properties:
  compatible:
    const: ovti,ov5693

  reg:
    maxItems: 1

  clocks:
    description:
      System input clock (aka XVCLK). From 6 to 27 MHz.
    maxItems: 1

  dovdd-supply:
    description:
      Digital I/O voltage supply, 1.8V.

  avdd-supply:
    description:
      Analog voltage supply, 2.8V.

  dvdd-supply:
    description:
      Digital core voltage supply, 1.2V.

  reset-gpios:
    description:
      The phandle and specifier for the GPIO that controls sensor reset.
      This corresponds to the hardware pin XSHUTDN which is physically
      active low.
    maxItems: 1

  port:
    description: MIPI CSI-2 transmitter port
    $ref: /schemas/graph.yaml#/$defs/port-base
    additionalProperties: false

    properties:
      endpoint:
        $ref: /schemas/media/video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          link-frequencies: true

          data-lanes:
            minItems: 1
            maxItems: 2

        required:
          - data-lanes
          - link-frequencies

required:
  - compatible
  - reg
  - clocks
  - port

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/px30-cru.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/pinctrl/rockchip.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        ov5693: camera@36 {
            compatible = "ovti,ov5693";
            reg = <0x36>;

            reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
            pinctrl-names = "default";
            pinctrl-0 = <&cif_clkout_m0>;

            clocks = <&cru SCLK_CIF_OUT>;
            assigned-clocks = <&cru SCLK_CIF_OUT>;
            assigned-clock-rates = <19200000>;

            avdd-supply = <&vcc_1v8>;
            dvdd-supply = <&vcc_1v2>;
            dovdd-supply = <&vcc_2v8>;

            rotation = <90>;
            orientation = <0>;

            port {
                ucam_out: endpoint {
                    remote-endpoint = <&mipi_in_ucam>;
                    data-lanes = <1 2>;
                    link-frequencies = /bits/ 64 <450000000>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/ovti,ov772x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Omnivision OV7720/OV7725 CMOS sensor

maintainers:
  - Jacopo Mondi <jacopo@jmondi.org>

description: |
  The Omnivision OV7720/OV7725 sensor supports multiple resolutions output,
  such as VGA, QVGA, and any size scaling down from CIF to 40x30. It also can
  support the YUV422, RGB565/555/444, GRB422 or raw RGB output formats.

properties:
  compatible:
    enum:
      - ovti,ov7720
      - ovti,ov7725

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  reset-gpios:
    description: |
      Reference to the GPIO connected to the RSTB pin which is active low.
    maxItems: 1

  powerdown-gpios:
    description: |
      Reference to the GPIO connected to the PWDN pin which is active high.
    maxItems: 1

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    description: |
      Video output port.

    properties:
      endpoint:
        $ref: /schemas/media/video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          bus-type:
            enum: [5, 6]

          bus-width:
            enum: [8, 10]
            default: 10

          data-shift:
            enum: [0, 2]
            default: 0

          hsync-active:
            enum: [0, 1]
            default: 1

          vsync-active:
            enum: [0, 1]
            default: 1

          pclk-sample:
            enum: [0, 1]
            default: 1

        allOf:
          - if:
              properties:
                bus-type:
                  const: 6
            then:
              properties:
                hsync-active: false
                vsync-active: false

          - if:
              properties:
                bus-width:
                  const: 10
            then:
              properties:
                data-shift:
                  const: 0

        required:
          - bus-type

    additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/media/video-interfaces.h>

    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;
        ov772x: camera@21 {
            compatible = "ovti,ov7725";
            reg = <0x21>;
            reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_LOW>;
            powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_LOW>;
            clocks = <&xclk>;

            port {
                ov772x_0: endpoint {
                    bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
                    vsync-active = <0>;
                    hsync-active = <0>;
                    pclk-sample = <0>;
                    bus-width = <8>;
                    data-shift = <0>;
                    remote-endpoint = <&vcap1_in0>;
                };
            };
        };
    };

...

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/ovti,ov8865.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: OmniVision OV8865 Image Sensor Device Tree Bindings

maintainers:
  - Paul Kocialkowski <paul.kocialkowski@bootlin.com>

properties:
  compatible:
    const: ovti,ov8865

  reg:
    maxItems: 1

  clocks:
    items:
      - description: EXTCLK Clock

  assigned-clocks:
    maxItems: 1

  assigned-clock-rates:
    maxItems: 1

  dvdd-supply:
    description: Digital Domain Power Supply

  avdd-supply:
    description: Analog Domain Power Supply

  dovdd-supply:
    description: I/O Domain Power Supply

  powerdown-gpios:
    maxItems: 1
    description: Power Down Pin GPIO Control (active low)

  reset-gpios:
    maxItems: 1
    description: Reset Pin GPIO Control (active low)

  port:
    description: MIPI CSI-2 transmitter port
    $ref: /schemas/graph.yaml#/$defs/port-base
    additionalProperties: false

    properties:
      endpoint:
        $ref: /schemas/media/video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          link-frequencies: true

          data-lanes:
            minItems: 1
            maxItems: 4

        required:
          - data-lanes
          - link-frequencies

required:
  - compatible
  - reg
  - clocks
  - assigned-clocks
  - assigned-clock-rates
  - dvdd-supply
  - avdd-supply
  - dovdd-supply
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/sun8i-a83t-ccu.h>
    #include <dt-bindings/gpio/gpio.h>

    i2c2 {
        #address-cells = <1>;
        #size-cells = <0>;

        ov8865: camera@36 {
            compatible = "ovti,ov8865";
            reg = <0x36>;

            pinctrl-names = "default";
            pinctrl-0 = <&csi_mclk_pin>;

            clocks = <&ccu CLK_CSI_MCLK>;
            assigned-clocks = <&ccu CLK_CSI_MCLK>;
            assigned-clock-rates = <24000000>;

            avdd-supply = <&reg_ov8865_avdd>;
            dovdd-supply = <&reg_ov8865_dovdd>;
            dvdd-supply = <&reg_ov8865_dvdd>;

            powerdown-gpios = <&pio 4 17 GPIO_ACTIVE_LOW>; /* PE17 */
            reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */

            port {
                ov8865_out_mipi_csi2: endpoint {
                    data-lanes = <1 2 3 4>;
                    link-frequencies = /bits/ 64 <360000000>;

                    remote-endpoint = <&mipi_csi2_in_ov8865>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2021 Intel Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/ovti,ov9282.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: OmniVision OV9282 Sensor

maintainers:
  - Paul J. Murphy <paul.j.murphy@intel.com>
  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>

description:
  OV9282 sensor is an OmniVision black & white CMOS active pixel digital image
  sensor with an active array size of 1296H x 816V. It is programmable through
  I2C interface. The I2C client address is fixed to 0x60/0x70 as per sensor data
  sheet. Image data is sent through MIPI CSI-2.
  OV9281 has a different lens chief ray angle.

properties:
  compatible:
    enum:
      - ovti,ov9281
      - ovti,ov9282
  reg:
    description: I2C address
    maxItems: 1

  assigned-clocks: true
  assigned-clock-parents: true
  assigned-clock-rates: true

  clocks:
    description: Clock frequency from 6 to 27MHz
    maxItems: 1

  reset-gpios:
    description: Reference to the GPIO connected to the XCLR pin, if any.
    maxItems: 1

  avdd-supply:
    description: Analog voltage supply, 2.8 volts

  dvdd-supply:
    description: Digital core voltage supply, 1.2 volts

  dovdd-supply:
    description: Digital I/O voltage supply, 1.8 volts

  port:
    additionalProperties: false
    $ref: /schemas/graph.yaml#/$defs/port-base

    properties:
      endpoint:
        $ref: /schemas/media/video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          data-lanes: true
          link-frequencies: true

        required:
          - data-lanes
          - link-frequencies

    required:
      - endpoint

required:
  - compatible
  - reg
  - clocks
  - port

additionalProperties: false

examples:
  - |
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        camera@60 {
            compatible = "ovti,ov9282";
            reg = <0x60>;
            clocks = <&ov9282_clk>;

            assigned-clocks = <&ov9282_clk>;
            assigned-clock-parents = <&ov9282_clk_parent>;
            assigned-clock-rates = <24000000>;

            port {
                ov9282: endpoint {
                    remote-endpoint = <&cam>;
                    data-lanes = <1 2>;
                    link-frequencies = /bits/ 64 <800000000>;
                };
            };
        };
    };
...


code:
* Panasonic AMG88xx

The Panasonic family of AMG88xx Grid-Eye sensors allow recording
8x8 10Hz video which consists of thermal datapoints

Required Properties:
 - compatible : Must be "panasonic,amg88xx"
 - reg : i2c address of the device

Example:

	i2c0@1c22000 {
		...
		amg88xx@69 {
			compatible = "panasonic,amg88xx";
			reg = <0x69>;
		};
		...
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/rda,rda5807.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Unisoc Communications RDA5807 FM radio receiver

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

properties:
  compatible:
    enum:
      - rda,rda5807

  reg:
    description: I2C address.
    maxItems: 1

  power-supply: true

  rda,lnan:
    description: Use LNAN input port.
    type: boolean

  rda,lnap:
    description: Use LNAP input port.
    type: boolean

  rda,analog-out:
    description: Enable analog audio output.
    type: boolean

  rda,i2s-out:
    description: Enable I2S digital audio output.
    type: boolean

  rda,lna-microamp:
    description: LNA working current, in micro-amperes.
    default: 2500
    enum: [1800, 2100, 2500, 3000]

required:
  - compatible
  - reg
  - power-supply

additionalProperties: false

examples:
  - |
    i2c0 {
      #address-cells = <1>;
      #size-cells = <0>;

      radio@11 {
        compatible = "rda,rda5807";
        reg = <0x11>;

        power-supply = <&ldo6>;

        rda,lnan;
        rda,lnap;
        rda,analog-out;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/sony,imx214.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sony 1/3.06-Inch 13.13MP CMOS Digital Image Sensor

maintainers:
  - Ricardo Ribalda <ribalda@kernel.org>

description: |
  The Sony IMX214 is a 1/3.06-inch CMOS active pixel digital image sensor with
  an active array size of 4224H x 3200V. It is programmable through an I2C
  interface. Image data is sent through MIPI CSI-2, through 2 or 4 lanes at a
  maximum throughput of 1.2Gbps/lane.

allOf:
  - $ref: ../video-interface-devices.yaml#

properties:
  compatible:
    const: sony,imx214

  reg:
    enum:
      - 0x10
      - 0x1a

  clocks:
    description: Reference to the xclk clock.
    maxItems: 1

  clock-frequency:
    description: Frequency of the xclk clock in Hz.

  enable-gpios:
    description: GPIO descriptor for the enable pin.
    maxItems: 1

  vdddo-supply:
    description: Chip digital IO regulator (1.8V).

  vdda-supply:
    description: Chip analog regulator (2.7V).

  vddd-supply:
    description: Chip digital core regulator (1.12V).

  flash-leds: true
  lens-focus: true

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    description: |
      Video output port.

    properties:
      endpoint:
        $ref: /schemas/media/video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          data-lanes:
            anyOf:
              - items:
                  - const: 1
                  - const: 2
              - items:
                  - const: 1
                  - const: 2
                  - const: 3
                  - const: 4

          link-frequencies: true

        required:
          - data-lanes
          - link-frequencies

    additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-frequency
  - enable-gpios
  - vdddo-supply
  - vdda-supply
  - vddd-supply
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        camera-sensor@1a {
            compatible = "sony,imx214";
            reg = <0x1a>;
            vdddo-supply = <&pm8994_lvs1>;
            vddd-supply = <&camera_vddd_1v12>;
            vdda-supply = <&pm8994_l17>;
            lens-focus = <&ad5820>;
            enable-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>;
            clocks = <&camera_clk>;
            clock-frequency = <24000000>;

            port {
                imx214_ep: endpoint {
                    data-lanes = <1 2 3 4>;
                    link-frequencies = /bits/ 64 <480000000>;
                    remote-endpoint = <&csiphy0_ep>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/sony,imx274.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sony 1/2.5-Inch 8.51MP CMOS Digital Image Sensor

maintainers:
  - Leon Luo <leonl@leopardimaging.com>

description: |
  The Sony IMX274 is a 1/2.5-inch CMOS active pixel digital image sensor with an
  active array size of 3864H x 2202V. It is programmable through I2C interface.
  Image data is sent through MIPI CSI-2, which is configured as 4 lanes at 1440
  Mbps.

properties:
  compatible:
    const: sony,imx274

  reg:
    const: 0x1a

  reset-gpios:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: inck

  vana-supply:
    description: Sensor 2.8 V analog supply.

  vdig-supply:
    description: Sensor 1.8 V digital core supply.

  vddl-supply:
    description: Sensor digital IO 1.2 V supply.

  port:
    $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - port

additionalProperties: false

examples:
  - |
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        imx274: camera-sensor@1a {
            compatible = "sony,imx274";
            reg = <0x1a>;
            reset-gpios = <&gpio_sensor 0 0>;

            port {
                sensor_out: endpoint {
                    remote-endpoint = <&csiss_in>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/sony,imx290.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sony IMX290 1/2.8-Inch CMOS Image Sensor

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description: |-
  The Sony IMX290 is a 1/2.8-Inch CMOS Solid-state image sensor with Square
  Pixel for Color Cameras. It is programmable through I2C and 4-wire
  interfaces. The sensor output is available via CMOS logic parallel SDR
  output, Low voltage LVDS DDR output and CSI-2 serial data output. The CSI-2
  bus is the default. No bindings have been defined for the other busses.

properties:
  compatible:
    enum:
      - sony,imx290

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    description: Input clock (37.125 MHz or 74.25 MHz)
    items:
      - const: xclk

  clock-frequency:
    description: Frequency of the xclk clock in Hz

  vdda-supply:
    description: Analog power supply (2.9V)

  vddd-supply:
    description: Digital core power supply (1.2V)

  vdddo-supply:
    description: Digital I/O power supply (1.8V)

  reset-gpios:
    description: Sensor reset (XCLR) GPIO
    maxItems: 1

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    description: |
      Video output port

    properties:
      endpoint:
        $ref: /schemas/media/video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          data-lanes:
            anyOf:
              - items:
                  - const: 1
                  - const: 2
              - items:
                  - const: 1
                  - const: 2
                  - const: 3
                  - const: 4

          link-frequencies: true

        required:
          - data-lanes
          - link-frequencies

    additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - clock-frequency
  - vdda-supply
  - vddd-supply
  - vdddo-supply
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        imx290: camera-sensor@1a {
            compatible = "sony,imx290";
            reg = <0x1a>;

            pinctrl-names = "default";
            pinctrl-0 = <&camera_rear_default>;

            clocks = <&gcc 90>;
            clock-names = "xclk";
            clock-frequency = <37125000>;

            vdddo-supply = <&camera_vdddo_1v8>;
            vdda-supply = <&camera_vdda_2v8>;
            vddd-supply = <&camera_vddd_1v5>;

            reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>;

            port {
                imx290_ep: endpoint {
                    data-lanes = <1 2 3 4>;
                    link-frequencies = /bits/ 64 <445500000>;
                    remote-endpoint = <&csiphy0_ep>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2021 Intel Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/sony,imx334.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sony IMX334 Sensor

maintainers:
  - Paul J. Murphy <paul.j.murphy@intel.com>
  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>

description:
  IMX334 sensor is a Sony CMOS active pixel digital image sensor with an active
  array size of 3864H x 2202V. It is programmable through I2C interface. The
  I2C client address is fixed to 0x1a as per sensor data sheet. Image data is
  sent through MIPI CSI-2.

properties:
  compatible:
    const: sony,imx334
  reg:
    description: I2C address
    maxItems: 1

  assigned-clocks: true
  assigned-clock-parents: true
  assigned-clock-rates: true

  clocks:
    description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz
    maxItems: 1

  reset-gpios:
    description: Reference to the GPIO connected to the XCLR pin, if any.

  port:
    additionalProperties: false
    $ref: /schemas/graph.yaml#/$defs/port-base

    properties:
      endpoint:
        $ref: /schemas/media/video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          data-lanes: true
          link-frequencies: true

        required:
          - data-lanes
          - link-frequencies

    required:
      - endpoint

required:
  - compatible
  - reg
  - clocks
  - port

additionalProperties: false

examples:
  - |
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        camera@1a {
            compatible = "sony,imx334";
            reg = <0x1a>;
            clocks = <&imx334_clk>;

            assigned-clocks = <&imx334_clk>;
            assigned-clock-parents = <&imx334_clk_parent>;
            assigned-clock-rates = <24000000>;

            port {
                imx334: endpoint {
                    remote-endpoint = <&cam>;
                    data-lanes = <1 2 3 4>;
                    link-frequencies = /bits/ 64 <891000000>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2021 Intel Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/sony,imx335.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sony IMX335 Sensor

maintainers:
  - Paul J. Murphy <paul.j.murphy@intel.com>
  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>

description:
  IMX335 sensor is a Sony CMOS active pixel digital image sensor with an active
  array size of 2592H x 1944V. It is programmable through I2C interface. The
  I2C client address is fixed to 0x1a as per sensor data sheet. Image data is
  sent through MIPI CSI-2.

properties:
  compatible:
    const: sony,imx335
  reg:
    description: I2C address
    maxItems: 1

  assigned-clocks: true
  assigned-clock-parents: true
  assigned-clock-rates: true

  clocks:
    description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz
    maxItems: 1

  reset-gpios:
    description: Reference to the GPIO connected to the XCLR pin, if any.
    maxItems: 1

  port:
    additionalProperties: false
    $ref: /schemas/graph.yaml#/$defs/port-base

    properties:
      endpoint:
        $ref: /schemas/media/video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          data-lanes: true
          link-frequencies: true

        required:
          - data-lanes
          - link-frequencies

    required:
      - endpoint

required:
  - compatible
  - reg
  - clocks
  - port

additionalProperties: false

examples:
  - |
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        camera@1a {
            compatible = "sony,imx335";
            reg = <0x1a>;
            clocks = <&imx335_clk>;

            assigned-clocks = <&imx335_clk>;
            assigned-clock-parents = <&imx335_clk_parent>;
            assigned-clock-rates = <24000000>;

            port {
                imx335: endpoint {
                    remote-endpoint = <&cam>;
                    data-lanes = <1 2 3 4>;
                    link-frequencies = /bits/ 64 <594000000>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2021 Intel Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/sony,imx412.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sony IMX412 Sensor

maintainers:
  - Paul J. Murphy <paul.j.murphy@intel.com>
  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>

description:
  IMX412 sensor is a Sony CMOS active pixel digital image sensor with an active
  array size of 4072H x 3176V. It is programmable through I2C interface. The
  I2C client address is fixed to 0x1a as per sensor data sheet. Image data is
  sent through MIPI CSI-2.

properties:
  compatible:
    enum:
      - sony,imx412
      - sony,imx577
  reg:
    description: I2C address
    maxItems: 1

  assigned-clocks: true
  assigned-clock-parents: true
  assigned-clock-rates: true

  clocks:
    description: Clock frequency 6MHz, 12MHz, 18MHz, 24MHz or 27MHz
    maxItems: 1

  dovdd-supply:
    description: Interface power supply.

  avdd-supply:
    description: Analog power supply.

  dvdd-supply:
    description: Digital power supply.

  reset-gpios:
    description: Reference to the GPIO connected to the XCLR pin, if any.
    maxItems: 1

  port:
    additionalProperties: false
    $ref: /schemas/graph.yaml#/$defs/port-base

    properties:
      endpoint:
        $ref: /schemas/media/video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          data-lanes: true
          link-frequencies: true

        required:
          - data-lanes
          - link-frequencies

    required:
      - endpoint

required:
  - compatible
  - reg
  - clocks
  - port

additionalProperties: false

examples:
  - |
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        camera@1a {
            compatible = "sony,imx412";
            reg = <0x1a>;
            clocks = <&imx412_clk>;

            assigned-clocks = <&imx412_clk>;
            assigned-clock-parents = <&imx412_clk_parent>;
            assigned-clock-rates = <24000000>;

            port {
                imx412: endpoint {
                    remote-endpoint = <&cam>;
                    data-lanes = <1 2 3 4>;
                    link-frequencies = /bits/ 64 <600000000>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge

maintainers:
  - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
  - Sylvain Petinot <sylvain.petinot@foss.st.com>

description:
  MIPID02 has two CSI-2 input ports, only one of those ports can be
  active at a time. Active port input stream will be de-serialized
  and its content outputted through PARALLEL output port.
  CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
  second input port is a single lane 800Mbps. Both ports support clock
  and data lane polarity swap. First port also supports data lane swap.
  PARALLEL output port has a maximum width of 12 bits.
  Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888,
  RGB444, YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.

properties:
  compatible:
    const: st,st-mipid02

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xclk

  VDDE-supply:
    description:
      Sensor digital IO supply. Must be 1.8 volts.

  VDDIN-supply:
    description:
      Sensor internal regulator supply. Must be 1.8 volts.

  reset-gpios:
    description:
      Reference to the GPIO connected to the xsdn pin, if any.
      This is an active low signal to the mipid02.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: CSI-2 first input port
        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description:
                  Single-lane operation shall be <1> or <2> .
                  Dual-lane operation shall be <1 2> or <2 1> .
                minItems: 1
                maxItems: 2

              lane-polarities:
                description:
                  Any lane can be inverted or not.
                minItems: 1
                maxItems: 2

            required:
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: CSI-2 second input port
        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description:
                  Single-lane operation shall be <1> or <2> .
                maxItems: 1

              lane-polarities:
                description:
                  Any lane can be inverted or not.
                maxItems: 1

            required:
              - data-lanes

      port@2:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: Output port
        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              bus-width:
                enum: [6, 7, 8, 10, 12]

            required:
              - bus-width

    anyOf:
      - required:
          - port@0
      - required:
          - port@1

    required:
      - port@2

additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - VDDE-supply
  - VDDIN-supply
  - ports

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;
        mipid02: csi2rx@14 {
            compatible = "st,st-mipid02";
            reg = <0x14>;
            status = "okay";
            clocks = <&clk_ext_camera_12>;
            clock-names = "xclk";
            VDDE-supply = <&vdd>;
            VDDIN-supply = <&vdd>;
            ports {
                #address-cells = <1>;
                #size-cells = <0>;
                port@0 {
                    reg = <0>;

                    ep0: endpoint {
                        data-lanes = <1 2>;
                        remote-endpoint = <&mipi_csi2_in>;
                    };
                };
                port@2 {
                    reg = <2>;

                    ep2: endpoint {
                        bus-width = <8>;
                        hsync-active = <0>;
                        vsync-active = <0>;
                        remote-endpoint = <&parallel_out>;
                    };
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (c) 2022 STMicroelectronics SA.
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/st,st-vgxy61.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics VGxy61 HDR Global Shutter Sensor Family Device Tree Bindings

maintainers:
  - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
  - Sylvain Petinot <sylvain.petinot@foss.st.com>

description: |-
  STMicroelectronics VGxy61 family has a CSI-2 output port. CSI-2 output is a
  quad lanes 800Mbps per lane.
  Supported formats are RAW8, RAW10, RAW12, RAW14 and RAW16.
  Following part number are supported
  - VG5661 and VG6661 are 1.6 Mpx (1464 x 1104) monochrome and color sensors.
  Maximum frame rate is 75 fps.
  - VG5761 and VG6761 are 2.3 Mpx (1944 x 1204) monochrome and color sensors.
  Maximum frame rate is 60 fps.

properties:
  compatible:
    const: st,st-vgxy61

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  VCORE-supply:
    description:
      Sensor digital core supply. Must be 1.2 volts.

  VDDIO-supply:
    description:
      Sensor digital IO supply. Must be 1.8 volts.

  VANA-supply:
    description:
      Sensor analog supply. Must be 2.8 volts.

  reset-gpios:
    description:
      Reference to the GPIO connected to the reset pin, if any.
      This is an active low signal to the vgxy61.

  st,strobe-gpios-polarity:
    description:
      Invert polarity of illuminator's lights strobe GPIOs.
      These GPIOs directly drive the illuminator LEDs.
    type: boolean

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    additionalProperties: false

    properties:
      endpoint:
        $ref: /schemas/media/video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          data-lanes:
            description:
              CSI lanes to use
            items:
              - const: 1
              - const: 2
              - const: 3
              - const: 4

          remote-endpoint: true

        required:
          - data-lanes

required:
  - compatible
  - clocks
  - VCORE-supply
  - VDDIO-supply
  - VANA-supply
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;
        vgxy61: csi2tx@10 {
            compatible = "st,st-vgxy61";
            reg = <0x10>;
            clocks = <&clk_ext_camera>;
            VCORE-supply = <&v1v2>;
            VDDIO-supply = <&v1v8>;
            VANA-supply = <&v2v8>;
            reset-gpios = <&mfxgpio 18 GPIO_ACTIVE_LOW>;
            port {
                ep0: endpoint {
                    data-lanes = <1 2 3 4>;
                    remote-endpoint = <&mipi_csi2_out>;
                };
            };
        };
    };
...


code:
* Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge

The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.

Required Properties:

- compatible: value should be "toshiba,tc358743"
- clocks, clock-names: should contain a phandle link to the reference clock
		       source, the clock input is named "refclk".

Optional Properties:

- reset-gpios: gpio phandle GPIO connected to the reset pin
- interrupts: GPIO connected to the interrupt pin
- data-lanes: should be <1 2 3 4> for four-lane operation,
	      or <1 2> for two-lane operation
- clock-lanes: should be <0>
- clock-noncontinuous: Presence of this boolean property decides whether the
		       MIPI CSI-2 clock is continuous or non-continuous.
- link-frequencies: List of allowed link frequencies in Hz. Each frequency is
		    expressed as a 64-bit big-endian integer. The frequency
		    is half of the bps per lane due to DDR transmission.

For further information on the MIPI CSI-2 endpoint node properties, see
Documentation/devicetree/bindings/media/video-interfaces.txt.

Example:

	tc358743@f {
		compatible = "toshiba,tc358743";
		reg = <0x0f>;
		clocks = <&hdmi_osc>;
		clock-names = "refclk";
		reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>;
		interrupt-parent = <&gpio2>;
		interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;

		port {
			tc358743_out: endpoint {
				remote-endpoint = <&mipi_csi2_in>;
				data-lanes = <1 2 3 4>;
				clock-lanes = <0>;
				clock-noncontinuous;
				link-frequencies = /bits/ 64 <297000000>;
			};
		};
	};


code:
Device-Tree bindings for the NXP TDA1997x HDMI receiver

The TDA19971/73 are HDMI video receivers.

The TDA19971 Video port output pins can be used as follows:
 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)

The TDA19973 Video port output pins can be used as follows:
 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
 - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
 - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)

The Video port output pins are mapped via 4-bit 'pin groups' allowing
for a variety of connection possibilities including swapping pin order within
pin groups. The video_portcfg device-tree property consists of register mapping
pairs which map a chip-specific VP output register to a 4-bit pin group. If
the pin group needs to be bit-swapped you can use the *_S pin-group defines.

Required Properties:
 - compatible          :
  - "nxp,tda19971" for the TDA19971
  - "nxp,tda19973" for the TDA19973
 - reg                 : I2C slave address
 - interrupts          : The interrupt number
 - DOVDD-supply        : Digital I/O supply
 - DVDD-supply         : Digital Core supply
 - AVDD-supply         : Analog supply
 - nxp,vidout-portcfg  : array of pairs mapping VP output pins to pin groups.

Optional Properties:
 - nxp,audout-format   : DAI bus format: "i2s" or "spdif".
 - nxp,audout-width    : width of audio output data bus (1-4).
 - nxp,audout-layout   : data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used).
 - nxp,audout-mclk-fs  : Multiplication factor between stream rate and codec
                         mclk.

The port node shall contain one endpoint child node for its digital
output video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.

Optional Endpoint Properties:
  The following three properties are defined in video-interfaces.txt and
  are valid for the output parallel bus endpoint:
  - hsync-active: Horizontal synchronization polarity. Defaults to active high.
  - vsync-active: Vertical synchronization polarity. Defaults to active high.
  - data-active: Data polarity. Defaults to active high.

Examples:
 - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422
   16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
	hdmi-receiver@48 {
		compatible = "nxp,tda19971";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tda1997x>;
		reg = <0x48>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
		DOVDD-supply = <&reg_3p3v>;
		AVDD-supply = <&reg_1p8v>;
		DVDD-supply = <&reg_1p8v>;
		/* audio */
		#sound-dai-cells = <0>;
		nxp,audout-format = "i2s";
		nxp,audout-layout = <0>;
		nxp,audout-width = <16>;
		nxp,audout-mclk-fs = <128>;
		/*
		 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
		 * and Y[11:4] across 16bits in the same pixclk cycle.
		 */
		nxp,vidout-portcfg =
			/* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
			< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
			/* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
			< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
			/* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
			< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
			/* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
			< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;

		port {
			tda1997x_to_ipu1_csi0_mux: endpoint {
				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
				bus-width = <16>;
				hsync-active = <1>;
				vsync-active = <1>;
				data-active = <1>;
			};
		};
	};
 - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
   16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
	hdmi-receiver@48 {
		compatible = "nxp,tda19971";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tda1997x>;
		reg = <0x48>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
		DOVDD-supply = <&reg_3p3v>;
		AVDD-supply = <&reg_1p8v>;
		DVDD-supply = <&reg_1p8v>;
		/* audio */
		#sound-dai-cells = <0>;
		nxp,audout-format = "i2s";
		nxp,audout-layout = <0>;
		nxp,audout-width = <16>;
		nxp,audout-mclk-fs = <128>;
		/*
		 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
		 * and Y[11:4] across 16bits in the same pixclk cycle.
		 */
		nxp,vidout-portcfg =
			/* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
			< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
			/* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
			< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
			/* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
			< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
			/* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
			< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;

		port {
			tda1997x_to_ipu1_csi0_mux: endpoint {
				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
				bus-width = <16>;
				hsync-active = <1>;
				vsync-active = <1>;
				data-active = <1>;
			};
		};
	};
 - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
   16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
	hdmi-receiver@48 {
		compatible = "nxp,tda19971";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tda1997x>;
		reg = <0x48>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
		DOVDD-supply = <&reg_3p3v>;
		AVDD-supply = <&reg_1p8v>;
		DVDD-supply = <&reg_1p8v>;
		/* audio */
		#sound-dai-cells = <0>;
		nxp,audout-format = "i2s";
		nxp,audout-layout = <0>;
		nxp,audout-width = <16>;
		nxp,audout-mclk-fs = <128>;
		/*
		 * The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over
		 * 2 pixclk cycles.
		 */
		nxp,vidout-portcfg =
			/* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
			< TDA1997X_VP24_V15_12 TDA1997X_R_CR_CBCR_11_8 >,
			/* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
			< TDA1997X_VP24_V11_08 TDA1997X_R_CR_CBCR_7_4 >,

		port {
			tda1997x_to_ipu1_csi0_mux: endpoint {
				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
				bus-width = <16>;
				hsync-active = <1>;
				vsync-active = <1>;
				data-active = <1>;
			};
		};
	};


code:
* Texas Instruments THS8200 video encoder

The ths8200 device is a digital to analog converter used in DVD players, video
recorders, set-top boxes.

Required Properties :
- compatible : value must be "ti,ths8200"

Example:

	i2c0@1c22000 {
		...
		...
		ths8200@5c {
			compatible = "ti,ths8200";
			reg = <0x5c>;
		};
		...
	};


code:
Toshiba et8ek8 5MP sensor

Toshiba et8ek8 5MP sensor is an image sensor found in Nokia N900 device

More detailed documentation can be found in
Documentation/devicetree/bindings/media/video-interfaces.txt .

Mandatory properties
--------------------

- compatible: "toshiba,et8ek8"
- reg: I2C address (0x3e, or an alternative address)
- vana-supply: Analogue voltage supply (VANA), 2.8 volts
- clocks: External clock to the sensor
- clock-frequency: Frequency of the external clock to the sensor. Camera
  driver will set this frequency on the external clock. The clock frequency is
  a pre-determined frequency known to be suitable to the board.
- reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor
  is in hardware standby mode when the signal is in the low state.

Optional properties
-------------------

- flash-leds: See ../video-interfaces.txt
- lens-focus: See ../video-interfaces.txt

Endpoint node mandatory properties
----------------------------------

- remote-endpoint: A phandle to the bus receiver's endpoint node.

Example
-------

&i2c3 {
	clock-frequency = <400000>;

	cam1: camera@3e {
		compatible = "toshiba,et8ek8";
		reg = <0x3e>;
		vana-supply = <&vaux4>;
		clocks = <&isp 0>;
		clock-frequency = <9600000>;
		reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
		port {
			csi_cam1: endpoint {
				remote-endpoint = <&csi_out1>;
			};
		};
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/toshiba,tc358746.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Toshiba TC358746 Parallel to MIPI CSI2 Bridge

maintainers:
  - Marco Felsch <kernel@pengutronix.de>

description: |-
  The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
  stream. The direction can be either parallel-in -> csi-out or csi-in ->
  parallel-out The chip is programmable trough I2C and SPI but the SPI
  interface is only supported in parallel-in -> csi-out mode.

  Note that the current device tree bindings only support the
  parallel-in -> csi-out path.

properties:
  compatible:
    const: toshiba,tc358746

  reg:
    maxItems: 1

  clocks:
    description:
      The phandle to the reference clock source. This corresponds to the
      hardware pin REFCLK.
    maxItems: 1

  clock-names:
    const: refclk

  "#clock-cells":
    description: |
      The bridge can act as clock provider for the sensor. To enable this
      support #clock-cells must be specified. Attention if this feature is used
      then the mclk rate must be at least: (2 * link-frequency) / 8
                                           `------------------´   ^
                                           internal PLL rate   smallest possible
                                                                   mclk-div
    const: 0

  clock-output-names:
    description:
      The clock name of the MCLK output, the default name is tc358746-mclk.
    maxItems: 1

  vddc-supply:
    description: Digital core voltage supply, 1.2 volts

  vddio-supply:
    description: Digital I/O voltage supply, 1.8 volts

  vddmipi-supply:
    description: MIPI CSI phy voltage supply, 1.2 volts

  reset-gpios:
    description:
      The phandle and specifier for the GPIO that controls the chip reset.
      This corresponds to the hardware pin RESX which is physically active low.
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        description: Input port

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              hsync-active: true
              vsync-active: true
              bus-type:
                enum: [ 5, 6 ]

            required:
              - hsync-active
              - vsync-active
              - bus-type

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        description: Output port

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

              clock-noncontinuous: true
              link-frequencies: true

            required:
              - data-lanes
              - link-frequencies

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - vddc-supply
  - vddio-supply
  - vddmipi-supply
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      csi-bridge@e {
        compatible = "toshiba,tc358746";
        reg = <0xe>;

        clocks = <&refclk>;
        clock-names = "refclk";

        reset-gpios = <&gpio 2 GPIO_ACTIVE_LOW>;

        vddc-supply = <&v1_2d>;
        vddio-supply = <&v1_8d>;
        vddmipi-supply = <&v1_2d>;

        /* sensor mclk provider */
        #clock-cells = <0>;

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          /* Input */
          port@0 {
            reg = <0>;
            tc358746_in: endpoint {
              remote-endpoint = <&sensor_out>;
              hsync-active = <0>;
              vsync-active = <0>;
              bus-type = <5>;
            };
          };

          /* Output */
          port@1 {
            reg = <1>;
            tc358746_out: endpoint {
              remote-endpoint = <&mipi_csi2_in>;
              data-lanes = <1 2>;
              clock-noncontinuous;
              link-frequencies = /bits/ 64 <216000000>;
            };
          };
        };
      };
    };


code:
* Texas Instruments TVP514x video decoder

The TVP5146/TVP5146m2/TVP5147/TVP5147m1 device is high quality, single-chip
digital video decoder that digitizes and decodes all popular baseband analog
video formats into digital video component. The tvp514x decoder supports analog-
to-digital (A/D) conversion of component RGB and YPbPr signals as well as A/D
conversion and decoding of NTSC, PAL and SECAM composite and S-video into
component YCbCr.

Required Properties :
- compatible : value should be either one among the following
	(a) "ti,tvp5146" for tvp5146 decoder.
	(b) "ti,tvp5146m2" for tvp5146m2 decoder.
	(c) "ti,tvp5147" for tvp5147 decoder.
	(d) "ti,tvp5147m1" for tvp5147m1 decoder.

- hsync-active: HSYNC Polarity configuration for endpoint.

- vsync-active: VSYNC Polarity configuration for endpoint.

- pclk-sample: Clock polarity of the endpoint.

For further reading on port node refer to Documentation/devicetree/bindings/
media/video-interfaces.txt.

Example:

	i2c0@1c22000 {
		...
		...
		tvp514x@5c {
			compatible = "ti,tvp5146";
			reg = <0x5c>;

			port {
				tvp514x_1: endpoint {
					hsync-active = <1>;
					vsync-active = <1>;
					pclk-sample = <0>;
				};
			};
		};
		...
	};


code:
* Texas Instruments TVP5150 and TVP5151 video decoders

The TVP5150 and TVP5151 are video decoders that convert baseband NTSC and PAL
(and also SECAM in the TVP5151 case) video signals to either 8-bit 4:2:2 YUV
with discrete syncs or 8-bit ITU-R BT.656 with embedded syncs output formats.

Required Properties:
====================
- compatible:	Value must be "ti,tvp5150".
- reg:		I2C slave address.

Optional Properties:
====================
- pdn-gpios:	Phandle for the GPIO connected to the PDN pin, if any.
- reset-gpios:	Phandle for the GPIO connected to the RESETB pin, if any.

The device node must contain one 'port' child node per device physical input
and output port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
are numbered as follows

	  Name		Type		Port
	--------------------------------------
	  AIP1A		sink		0
	  AIP1B		sink		1
	  Y-OUT		src		2

The device node must contain at least one sink port and the src port. Each input
port must be linked to an endpoint defined in [1]. The port/connector layout is
as follows

tvp-5150 port@0 (AIP1A)
	endpoint@0 -----------> Comp0-Con  port
	endpoint@1 ------+----> Svideo-Con port
tvp-5150 port@1 (AIP1B)  |
	endpoint@1 ------+
	endpoint@0 -----------> Comp1-Con  port
tvp-5150 port@2
	endpoint (video bitstream output at YOUT[0-7] parallel bus)

Required Endpoint Properties for parallel synchronization on output port:
=========================================================================

- hsync-active:		Active state of the HSYNC signal. Must be <1> (HIGH).
- vsync-active:		Active state of the VSYNC signal. Must be <1> (HIGH).
- field-even-active:	Field signal level during the even field data
			transmission. Must be <0>.

Note: Do not specify any of these properties if you want to use the embedded
      BT.656 synchronization.

Optional Connector Properties:
==============================

- sdtv-standards: Set the possible signals to which the hardware tries to lock
                  instead of using the autodetection mechnism. Please look at
                  [1] for more information.

[1] Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml.

Example - three input sources:
#include <dt-bindings/display/sdtv-standards.h>

comp_connector_0 {
	compatible = "composite-video-connector";
	label = "Composite0";
	sdtv-standards = <SDTV_STD_PAL_M>; /* limit to pal-m signals */

	port {
		composite0_to_tvp5150: endpoint {
			remote-endpoint = <&tvp5150_to_composite0>;
		};
	};
};

comp_connector_1 {
	compatible = "composite-video-connector";
	label = "Composite1";
	sdtv-standards = <SDTV_STD_NTSC_M>; /* limit to ntsc-m signals */

	port {
		composite1_to_tvp5150: endpoint {
			remote-endpoint = <&tvp5150_to_composite1>;
		};
	};
};

svideo_connector {
	compatible = "svideo-connector";
	label = "S-Video";

	port {
		#address-cells = <1>;
		#size-cells = <0>;

		svideo_luma_to_tvp5150: endpoint@0 {
			reg = <0>;
			remote-endpoint = <&tvp5150_to_svideo_luma>;
		};

		svideo_chroma_to_tvp5150: endpoint@1 {
			reg = <1>;
			remote-endpoint = <&tvp5150_to_svideo_chroma>;
		};
	};
};

&i2c2 {
	tvp5150@5c {
		compatible = "ti,tvp5150";
		reg = <0x5c>;
		pdn-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
		reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			tvp5150_to_composite0: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&composite0_to_tvp5150>;
			};

			tvp5150_to_svideo_luma: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&svideo_luma_to_tvp5150>;
			};
		};

		port@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			tvp5150_to_composite1: endpoint@0 {
				reg = <0>;
                                remote-endpoint = <&composite1_to_tvp5150>;
			};

			tvp5150_to_svideo_chroma: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&svideo_chroma_to_tvp5150>;
			};
		};

		port@2 {
			reg = <2>;

			tvp5150_1: endpoint {
				remote-endpoint = <&ccdc_ep>;
			};
		};
	};
};


code:
* Texas Instruments TV7002 video decoder

The TVP7002 device supports digitizing of video and graphics signal in RGB and
YPbPr color space.

Required Properties :
- compatible : Must be "ti,tvp7002"

Optional Properties:
- hsync-active: HSYNC Polarity configuration for the bus. Default value when
  this property is not specified is <0>.

- vsync-active: VSYNC Polarity configuration for the bus. Default value when
  this property is not specified is <0>.

- pclk-sample: Clock polarity of the bus. Default value when this property is
  not specified is <0>.

- sync-on-green-active: Active state of Sync-on-green signal property of the
  endpoint.
  0 = Normal Operation (Active Low, Default)
  1 = Inverted operation

- field-even-active: Active-high Field ID output polarity control of the bus.
  Under normal operation, the field ID output is set to logic 1 for an odd field
  (field 1) and set to logic 0 for an even field (field 0).
  0 = Normal Operation (Active Low, Default)
  1 = FID output polarity inverted

For further reading of port node refer Documentation/devicetree/bindings/media/
video-interfaces.txt.

Example:

	i2c0@1c22000 {
		...
		...
		tvp7002@5c {
			compatible = "ti,tvp7002";
			reg = <0x5c>;

			port {
				tvp7002_1: endpoint {
					hsync-active = <1>;
					vsync-active = <1>;
					pclk-sample = <0>;
					sync-on-green-active = <1>;
					field-even-active = <0>;
				};
			};
		};
		...
	};


code:
* ImgTec Infrared (IR) decoder version 1

This binding is for Imagination Technologies' Infrared decoder block,
specifically major revision 1.

Required properties:
- compatible:		Should be "img,ir-rev1"
- reg:			Physical base address of the controller and length of
			memory mapped region.
- interrupts:		The interrupt specifier to the cpu.

Optional properties:
- clocks:		List of clock specifiers as described in standard
			clock bindings.
			Up to 3 clocks may be specified in the following order:
			1st:	Core clock (defaults to 32.768KHz if omitted).
			2nd:	System side (fast) clock.
			3rd:	Power modulation clock.
- clock-names:		List of clock names corresponding to the clocks
			specified in the clocks property.
			Accepted clock names are:
			"core":	Core clock.
			"sys":	System clock.
			"mod":	Power modulation clock.

Example:

	ir@2006200 {
		compatible = "img,ir-rev1";
		reg = <0x02006200 0x100>;
		interrupts = <29 4>;
		clocks = <&clk_32khz>;
		clock-names =  "core";
	};


code:
Freescale i.MX Media Video Device
=================================

Video Media Controller node
---------------------------

This is the media controller node for video capture support. It is a
virtual device that lists the camera serial interface nodes that the
media device will control.

Required properties:
- compatible : "fsl,imx-capture-subsystem";
- ports      : Should contain a list of phandles pointing to camera
		sensor interface ports of IPU devices

example:

capture-subsystem {
	compatible = "fsl,imx-capture-subsystem";
	ports = <&ipu1_csi0>, <&ipu1_csi1>;
};

mipi_csi2 node
--------------

This is the device node for the MIPI CSI-2 Receiver core in the i.MX
SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
combined with a D-PHY core mixed into the same register block. In
addition this device consists of an i.MX-specific "CSI2IPU gasket"
glue logic, also controlled from the same register block. The CSI2IPU
gasket demultiplexes the four virtual channel streams from the host
controller's 32-bit output image bus onto four 16-bit parallel busses
to the i.MX IPU CSIs.

Required properties:
- compatible	: "fsl,imx6-mipi-csi2";
- reg           : physical base address and length of the register set;
- clocks	: the MIPI CSI-2 receiver requires three clocks: hsi_tx
		  (the D-PHY clock), video_27m (D-PHY PLL reference
		  clock), and eim_podf;
- clock-names	: must contain "dphy", "ref", "pix";
- port@*        : five port nodes must exist, containing endpoints
		  connecting to the source and sink devices according to
		  of_graph bindings. The first port is an input port,
		  connecting with a MIPI CSI-2 source, and ports 1
		  through 4 are output ports connecting with parallel
		  bus sink endpoint nodes and correspond to the four
		  MIPI CSI-2 virtual channel outputs.

Optional properties:
- interrupts	: must contain two level-triggered interrupts,
		  in order: 100 and 101;


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2019,2020 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell MMP2 camera host interface bindings

maintainers:
  - Lubomir Rintel <lkundrak@v3.sk>

properties:
  $nodename:
    pattern: '^camera@[a-f0-9]+$'

  compatible:
    const: marvell,mmp2-ccic

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    additionalProperties: false

    properties:
      endpoint:
        $ref: video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          hsync-active: true
          vsync-active: true
          pclk-sample: true
          bus-type: true

  clocks:
    minItems: 1
    items:
      - description: AXI bus interface clock
      - description: Peripheral clock
      - description: Parallel video bus interface clock

  clock-names:
    const: axi

  '#clock-cells':
    const: 0

  clock-output-names:
    const: mclk

required:
  - compatible
  - reg
  - interrupts
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/marvell,mmp2.h>
    #include <dt-bindings/media/video-interfaces.h>
    #include <dt-bindings/power/marvell,mmp2.h>

    camera@d420a000 {
      compatible = "marvell,mmp2-ccic";
      reg = <0xd420a000 0x800>;
      interrupts = <42>;
      clocks = <&soc_clocks MMP2_CLK_CCIC0>;
      clock-names = "axi";
      #clock-cells = <0>;
      clock-output-names = "mclk";
      power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;

      port {
        camera0_0: endpoint {
          remote-endpoint = <&ov7670_0>;
          bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
          hsync-active = <1>;  /* Active high */
          vsync-active = <1>;  /* Active high */
          pclk-sample = <0>;   /* Falling */
        };
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Read Direct Memory Access

maintainers:
  - Matthias Brugger <matthias.bgg@gmail.com>
  - Moudy Ho <moudy.ho@mediatek.com>

description: |
  MediaTek Read Direct Memory Access(RDMA) component used to do read DMA.
  It contains one line buffer to store the sufficient pixel data, and
  must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    items:
      - const: mediatek,mt8183-mdp3-rdma

  reg:
    maxItems: 1

  mediatek,gce-client-reg:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    items:
      items:
        - description: phandle of GCE
        - description: GCE subsys id
        - description: register offset
        - description: register size
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property. Each GCE subsys id is mapping to
      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.

  mediatek,gce-events:
    description:
      The event id which is mapping to the specific hardware event signal
      to gce. The event id is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h of each chips.
    $ref: /schemas/types.yaml#/definitions/uint32-array

  power-domains:
    maxItems: 1

  clocks:
    items:
      - description: RDMA clock
      - description: RSZ clock

  iommus:
    maxItems: 1

  mboxes:
    items:
      - description: used for 1st data pipe from RDMA
      - description: used for 2nd data pipe from RDMA

required:
  - compatible
  - reg
  - mediatek,gce-client-reg
  - mediatek,gce-events
  - power-domains
  - clocks
  - iommus
  - mboxes

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/gce/mt8183-gce.h>
    #include <dt-bindings/power/mt8183-power.h>
    #include <dt-bindings/memory/mt8183-larb-port.h>

    mdp3_rdma0: mdp3-rdma0@14001000 {
      compatible = "mediatek,mt8183-mdp3-rdma";
      reg = <0x14001000 0x1000>;
      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
      mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
                            <CMDQ_EVENT_MDP_RDMA0_EOF>;
      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
      clocks = <&mmsys CLK_MM_MDP_RDMA0>,
               <&mmsys CLK_MM_MDP_RSZ1>;
      iommus = <&iommu>;
      mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
               <&gce 21 CMDQ_THR_PRIO_LOWEST>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Resizer

maintainers:
  - Matthias Brugger <matthias.bgg@gmail.com>
  - Moudy Ho <moudy.ho@mediatek.com>

description: |
  One of Media Data Path 3 (MDP3) components used to do frame resizing.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8183-mdp3-rsz

  reg:
    maxItems: 1

  mediatek,gce-client-reg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      items:
        - description: phandle of GCE
        - description: GCE subsys id
        - description: register offset
        - description: register size
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property. Each GCE subsys id is mapping to
      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.

  mediatek,gce-events:
    description:
      The event id which is mapping to the specific hardware event signal
      to gce. The event id is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h of each chips.
    $ref: /schemas/types.yaml#/definitions/uint32-array

  clocks:
    minItems: 1

required:
  - compatible
  - reg
  - mediatek,gce-client-reg
  - mediatek,gce-events
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/gce/mt8183-gce.h>

    mdp3_rsz0: mdp3-rsz0@14003000 {
      compatible = "mediatek,mt8183-mdp3-rsz";
      reg = <0x14003000 0x1000>;
      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
                            <CMDQ_EVENT_MDP_RSZ0_EOF>;
      clocks = <&mmsys CLK_MM_MDP_RSZ0>;
    };

    mdp3_rsz1: mdp3-rsz1@14004000 {
      compatible = "mediatek,mt8183-mdp3-rsz";
      reg = <0x14004000 0x1000>;
      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
                            <CMDQ_EVENT_MDP_RSZ1_EOF>;
      clocks = <&mmsys CLK_MM_MDP_RSZ1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Write DMA with Rotation

maintainers:
  - Matthias Brugger <matthias.bgg@gmail.com>
  - Moudy Ho <moudy.ho@mediatek.com>

description: |
  One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8183-mdp3-wrot

  reg:
    maxItems: 1

  mediatek,gce-client-reg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      items:
        - description: phandle of GCE
        - description: GCE subsys id
        - description: register offset
        - description: register size
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property. Each GCE subsys id is mapping to
      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.

  mediatek,gce-events:
    description:
      The event id which is mapping to the specific hardware event signal
      to gce. The event id is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h of each chips.
    $ref: /schemas/types.yaml#/definitions/uint32-array

  power-domains:
    maxItems: 1

  clocks:
    minItems: 1

  iommus:
    maxItems: 1

required:
  - compatible
  - reg
  - mediatek,gce-client-reg
  - mediatek,gce-events
  - power-domains
  - clocks
  - iommus

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/gce/mt8183-gce.h>
    #include <dt-bindings/power/mt8183-power.h>
    #include <dt-bindings/memory/mt8183-larb-port.h>

    mdp3_wrot0: mdp3-wrot0@14005000 {
      compatible = "mediatek,mt8183-mdp3-wrot";
      reg = <0x14005000 0x1000>;
      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
      mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
                            <CMDQ_EVENT_MDP_WROT0_EOF>;
      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
      clocks = <&mmsys CLK_MM_MDP_WROT0>;
      iommus = <&iommu>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek JPEG Decoder

maintainers:
  - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>

description:
  MediaTek JPEG Decoder is the JPEG decode hardware present in MediaTek SoCs

properties:
  compatible:
    const: mediatek,mt8195-jpgdec

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 6
    description:
      Points to the respective IOMMU block with master port as argument, see
      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
      Ports are according to the HW.

  dma-ranges:
    maxItems: 1
    description: |
      Describes the physical address space of IOMMU maps to memory.

  "#address-cells":
    const: 2

  "#size-cells":
    const: 2

  ranges: true

# Required child node:
patternProperties:
  "^jpgdec@[0-9a-f]+$":
    type: object
    description:
      The jpeg decoder hardware device node which should be added as subnodes to
      the main jpeg node.

    properties:
      compatible:
        const: mediatek,mt8195-jpgdec-hw

      reg:
        maxItems: 1

      iommus:
        minItems: 1
        maxItems: 32
        description:
          List of the hardware port in respective IOMMU block for current Socs.
          Refer to bindings/iommu/mediatek,iommu.yaml.

      interrupts:
        maxItems: 1

      clocks:
        maxItems: 1

      clock-names:
        items:
          - const: jpgdec

      power-domains:
        maxItems: 1

    required:
      - compatible
      - reg
      - iommus
      - interrupts
      - clocks
      - clock-names
      - power-domains

    additionalProperties: false

required:
  - compatible
  - power-domains
  - iommus
  - dma-ranges
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/mt8195-memory-port.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/mt8195-clk.h>
    #include <dt-bindings/power/mt8195-power.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        jpgdec-master {
            compatible = "mediatek,mt8195-jpgdec";
            power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
            iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
                     <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
                     <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
            dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
            #address-cells = <2>;
            #size-cells = <2>;
            ranges;

            jpgdec@1a040000 {
                compatible = "mediatek,mt8195-jpgdec-hw";
                reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
                iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
                         <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
                interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
                clocks = <&vencsys CLK_VENC_JPGDEC>;
                clock-names = "jpgdec";
                power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
            };

            jpgdec@1a050000 {
                compatible = "mediatek,mt8195-jpgdec-hw";
                reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
                iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
                         <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
                         <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
                interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
                clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
                clock-names = "jpgdec";
                power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
            };

            jpgdec@1b040000 {
                compatible = "mediatek,mt8195-jpgdec-hw";
                reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
                iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
                         <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
                         <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
                         <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
                         <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
                         <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
                interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
                clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
                clock-names = "jpgdec";
                power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek JPEG Encoder

maintainers:
  - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>

description:
  MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs

properties:
  compatible:
    const: mediatek,mt8195-jpgenc

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 4
    description:
      Points to the respective IOMMU block with master port as argument, see
      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
      Ports are according to the HW.

  dma-ranges:
    maxItems: 1
    description: |
      Describes the physical address space of IOMMU maps to memory.

  "#address-cells":
    const: 2

  "#size-cells":
    const: 2

  ranges: true

# Required child node:
patternProperties:
  "^jpgenc@[0-9a-f]+$":
    type: object
    description:
      The jpeg encoder hardware device node which should be added as subnodes to
      the main jpeg node.

    properties:
      compatible:
        const: mediatek,mt8195-jpgenc-hw

      reg:
        maxItems: 1

      iommus:
        minItems: 1
        maxItems: 32
        description:
          List of the hardware port in respective IOMMU block for current Socs.
          Refer to bindings/iommu/mediatek,iommu.yaml.

      interrupts:
        maxItems: 1

      clocks:
        maxItems: 1

      clock-names:
        items:
          - const: jpgenc

      power-domains:
        maxItems: 1

    required:
      - compatible
      - reg
      - iommus
      - interrupts
      - clocks
      - clock-names
      - power-domains

    additionalProperties: false

required:
  - compatible
  - power-domains
  - iommus
  - dma-ranges
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/mt8195-memory-port.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/mt8195-clk.h>
    #include <dt-bindings/power/mt8195-power.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        jpgenc-master {
            compatible = "mediatek,mt8195-jpgenc";
            power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
            iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
                     <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
                     <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
                     <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
            dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
            #address-cells = <2>;
            #size-cells = <2>;
            ranges;

            jpgenc@1a030000 {
                compatible = "mediatek,mt8195-jpgenc-hw";
                reg = <0 0x1a030000 0 0x10000>;
                iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
                         <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
                         <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
                         <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
                interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
                clocks = <&vencsys CLK_VENC_JPGENC>;
                clock-names = "jpgenc";
                power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
            };

            jpgenc@1b030000 {
                compatible = "mediatek,mt8195-jpgenc-hw";
                reg = <0 0x1b030000 0 0x10000>;
                iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
                         <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
                         <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
                         <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
                interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
                clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
                clock-names = "jpgenc";
                power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek Video Decode Accelerator

maintainers:
  - Yunfei Dong <yunfei.dong@mediatek.com>

description: |+
  Mediatek Video Decode is the video decode hardware present in Mediatek
  SoCs which supports high resolution decoding functionalities.

properties:
  compatible:
    enum:
      - mediatek,mt8173-vcodec-dec
      - mediatek,mt8183-vcodec-dec

  reg:
    maxItems: 12

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 8

  clock-names:
    items:
      - const: vcodecpll
      - const: univpll_d2
      - const: clk_cci400_sel
      - const: vdec_sel
      - const: vdecpll
      - const: vencpll
      - const: venc_lt_sel
      - const: vdec_bus_clk_src

  assigned-clocks: true

  assigned-clock-parents: true

  assigned-clock-rates: true

  power-domains:
    maxItems: 1

  iommus:
    minItems: 1
    maxItems: 32
    description: |
      List of the hardware port in respective IOMMU block for current Socs.
      Refer to bindings/iommu/mediatek,iommu.yaml.

  dma-ranges:
    maxItems: 1
    description: |
      Describes the physical address space of IOMMU maps to memory.

  mediatek,vpu:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Describes point to vpu.

  mediatek,scp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Describes point to scp.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - iommus
  - assigned-clocks
  - assigned-clock-parents

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8183-vcodec-dec

    then:
      required:
        - mediatek,scp

  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8173-vcodec-dec

    then:
      required:
        - mediatek,vpu

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/memory/mt8173-larb-port.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/mt8173-power.h>

    vcodec_dec: vcodec@16000000 {
      compatible = "mediatek,mt8173-vcodec-dec";
      reg = <0x16000000 0x100>,   /*VDEC_SYS*/
          <0x16020000 0x1000>,  /*VDEC_MISC*/
          <0x16021000 0x800>,   /*VDEC_LD*/
          <0x16021800 0x800>,   /*VDEC_TOP*/
          <0x16022000 0x1000>,  /*VDEC_CM*/
          <0x16023000 0x1000>,  /*VDEC_AD*/
          <0x16024000 0x1000>,  /*VDEC_AV*/
          <0x16025000 0x1000>,  /*VDEC_PP*/
          <0x16026800 0x800>,   /*VP8_VD*/
          <0x16027000 0x800>,   /*VP6_VD*/
          <0x16027800 0x800>,   /*VP8_VL*/
          <0x16028400 0x400>;   /*VP9_VD*/
      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
      iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
             <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
             <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
             <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
             <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
             <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
             <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
             <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
      mediatek,vpu = <&vpu>;
      power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
      clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
             <&topckgen CLK_TOP_UNIVPLL_D2>,
             <&topckgen CLK_TOP_CCI400_SEL>,
             <&topckgen CLK_TOP_VDEC_SEL>,
             <&topckgen CLK_TOP_VCODECPLL>,
             <&apmixedsys CLK_APMIXED_VENCPLL>,
             <&topckgen CLK_TOP_VENC_LT_SEL>,
             <&topckgen CLK_TOP_VCODECPLL_370P5>;
      clock-names = "vcodecpll",
                  "univpll_d2",
                  "clk_cci400_sel",
                  "vdec_sel",
                  "vdecpll",
                  "vencpll",
                  "venc_lt_sel",
                  "vdec_bus_clk_src";
      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
                      <&topckgen CLK_TOP_CCI400_SEL>,
                      <&topckgen CLK_TOP_VDEC_SEL>,
                      <&apmixedsys CLK_APMIXED_VCODECPLL>,
                      <&apmixedsys CLK_APMIXED_VENCPLL>;
      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
                             <&topckgen CLK_TOP_UNIVPLL_D2>,
                             <&topckgen CLK_TOP_VCODECPLL>;
      assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek Video Encode Accelerator

maintainers:
  - Yunfei Dong <yunfei.dong@mediatek.com>

description: |+
  Mediatek Video Encode is the video encode hardware present in Mediatek
  SoCs which supports high resolution encoding functionalities.

properties:
  compatible:
    enum:
      - mediatek,mt8173-vcodec-enc-vp8
      - mediatek,mt8173-vcodec-enc
      - mediatek,mt8183-vcodec-enc
      - mediatek,mt8188-vcodec-enc
      - mediatek,mt8192-vcodec-enc
      - mediatek,mt8195-vcodec-enc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 5

  clock-names:
    minItems: 1
    maxItems: 5

  assigned-clocks: true

  assigned-clock-parents: true

  iommus:
    minItems: 1
    maxItems: 32
    description: |
      List of the hardware port in respective IOMMU block for current Socs.
      Refer to bindings/iommu/mediatek,iommu.yaml.

  dma-ranges:
    maxItems: 1
    description: |
      Describes the physical address space of IOMMU maps to memory.

  mediatek,vpu:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Describes point to vpu.

  mediatek,scp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Describes point to scp.

  power-domains:
    maxItems: 1

  "#address-cells":
    const: 2

  "#size-cells":
    const: 2

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - iommus
  - assigned-clocks
  - assigned-clock-parents

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8183-vcodec-enc
              - mediatek,mt8188-vcodec-enc
              - mediatek,mt8192-vcodec-enc
              - mediatek,mt8195-vcodec-enc

    then:
      required:
        - mediatek,scp

  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8173-vcodec-enc-vp8
              - mediatek,mt8173-vcodec-enc

    then:
      required:
        - mediatek,vpu

  - if:
      properties:
        compatible:
          enum:
            - mediatek,mt8173-vcodec-enc
            - mediatek,mt8188-vcodec-enc
            - mediatek,mt8192-vcodec-enc
            - mediatek,mt8195-vcodec-enc

    then:
      properties:
        clock:
          items:
            minItems: 1
            maxItems: 1
        clock-names:
          items:
            - const: venc_sel
    else:  # for vp8 hw encoder
      properties:
        clock:
          items:
            minItems: 1
            maxItems: 1
        clock-names:
          items:
            - const: venc_lt_sel

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/memory/mt8173-larb-port.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    vcodec_enc_avc: vcodec@18002000 {
      compatible = "mediatek,mt8173-vcodec-enc";
      reg = <0x18002000 0x1000>;
      interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
      iommus = <&iommu M4U_PORT_VENC_RCPU>,
             <&iommu M4U_PORT_VENC_REC>,
             <&iommu M4U_PORT_VENC_BSDMA>,
             <&iommu M4U_PORT_VENC_SV_COMV>,
             <&iommu M4U_PORT_VENC_RD_COMV>,
             <&iommu M4U_PORT_VENC_CUR_LUMA>,
             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
             <&iommu M4U_PORT_VENC_REF_LUMA>,
             <&iommu M4U_PORT_VENC_REF_CHROMA>,
             <&iommu M4U_PORT_VENC_NBM_RDMA>,
             <&iommu M4U_PORT_VENC_NBM_WDMA>;
      mediatek,vpu = <&vpu>;
      clocks = <&topckgen CLK_TOP_VENC_SEL>;
      clock-names = "venc_sel";
      assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
    };

    vcodec_enc_vp8: vcodec@19002000 {
      compatible = "mediatek,mt8173-vcodec-enc-vp8";
      reg =  <0x19002000 0x1000>;	/* VENC_LT_SYS */
      interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
      iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
      mediatek,vpu = <&vpu>;
      clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
      clock-names = "venc_lt_sel";
      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Mediatek Video Decode Accelerator With Multi Hardware

maintainers:
  - Yunfei Dong <yunfei.dong@mediatek.com>

description: |
  Mediatek Video Decode is the video decode hardware present in Mediatek
  SoCs which supports high resolution decoding functionalities. Required
  parent and child device node.

  About the Decoder Hardware Block Diagram, please check below:

    +------------------------------------------------+-------------------------------------+
    |                                                |                                     |
    |  input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output  |
    |            ||             ||                   |                     ||              |
    +------------||-------------||-------------------+---------------------||--------------+
                 ||     lat     ||                   |               core workqueue  <parent>
    -------------||-------------||-------------------|---------------------||---------------
                 ||<------------||----------------HW index---------------->||        <child>
                 \/             \/                                         \/
               +-------------------------------------------------------------+
               |                          enable/disable                     |
               |                 clk     power    irq    iommu               |
               |                   (lat/lat soc/core0/core1)                 |
               +-------------------------------------------------------------+

  As above, there are parent and child devices, child mean each hardware. The child device
  controls the information of each hardware independent which include clk/power/irq.

  There are two workqueues in parent device: lat workqueue and core workqueue. They are used
  to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
  then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
  done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
  writing the result to output buffer, disable hardware when core decode done. These two
  hardwares will decode each frame cyclically.

  For the smi common may not the same for each hardware, can't combine all hardware in one node,
  or leading to iommu fault when access dram data.

  Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195
  platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and
  clock when lat start to work, don't have interrupt.

  mt8195: lat soc HW + lat HW + core HW
  mt8192: lat HW + core HW

properties:
  compatible:
    enum:
      - mediatek,mt8192-vcodec-dec
      - mediatek,mt8186-vcodec-dec
      - mediatek,mt8188-vcodec-dec
      - mediatek,mt8195-vcodec-dec

  reg:
    maxItems: 1

  iommus:
    minItems: 1
    maxItems: 32
    description: |
      List of the hardware port in respective IOMMU block for current Socs.
      Refer to bindings/iommu/mediatek,iommu.yaml.

  mediatek,scp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      The node of system control processor (SCP), using
      the remoteproc & rpmsg framework.

  dma-ranges:
    maxItems: 1
    description: |
      Describes the physical address space of IOMMU maps to memory.

  "#address-cells":
    const: 2

  "#size-cells":
    const: 2

  ranges: true

# Required child node:
patternProperties:
  '^vcodec-lat@[0-9a-f]+$':
    type: object

    properties:
      compatible:
        enum:
          - mediatek,mtk-vcodec-lat
          - mediatek,mtk-vcodec-lat-soc

      reg:
        maxItems: 1

      interrupts:
        maxItems: 1

      iommus:
        minItems: 1
        maxItems: 32
        description: |
          List of the hardware port in respective IOMMU block for current Socs.
          Refer to bindings/iommu/mediatek,iommu.yaml.

      clocks:
        maxItems: 5

      clock-names:
        items:
          - const: sel
          - const: soc-vdec
          - const: soc-lat
          - const: vdec
          - const: top

      assigned-clocks:
        maxItems: 1

      assigned-clock-parents:
        maxItems: 1

      power-domains:
        maxItems: 1

    required:
      - compatible
      - reg
      - iommus
      - clocks
      - clock-names
      - assigned-clocks
      - assigned-clock-parents
      - power-domains

    additionalProperties: false

  '^vcodec-core@[0-9a-f]+$':
    type: object

    properties:
      compatible:
        const: mediatek,mtk-vcodec-core

      reg:
        maxItems: 1

      interrupts:
        maxItems: 1

      iommus:
        minItems: 1
        maxItems: 32
        description: |
          List of the hardware port in respective IOMMU block for current Socs.
          Refer to bindings/iommu/mediatek,iommu.yaml.

      clocks:
        maxItems: 5

      clock-names:
        items:
          - const: sel
          - const: soc-vdec
          - const: soc-lat
          - const: vdec
          - const: top

      assigned-clocks:
        maxItems: 1

      assigned-clock-parents:
        maxItems: 1

      power-domains:
        maxItems: 1

    required:
      - compatible
      - reg
      - interrupts
      - iommus
      - clocks
      - clock-names
      - assigned-clocks
      - assigned-clock-parents
      - power-domains

    additionalProperties: false

required:
  - compatible
  - reg
  - iommus
  - mediatek,scp
  - dma-ranges
  - ranges

if:
  properties:
    compatible:
      contains:
        enum:
          - mediatek,mtk-vcodec-lat

then:
  required:
    - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/mt8192-larb-port.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/mt8192-clk.h>
    #include <dt-bindings/power/mt8192-power.h>

    bus@16000000 {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges = <0 0x16000000 0x16000000 0 0x40000>;

        video-codec@16000000 {
            compatible = "mediatek,mt8192-vcodec-dec";
            mediatek,scp = <&scp>;
            iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
            dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
            #address-cells = <2>;
            #size-cells = <2>;
            ranges = <0 0 0 0x16000000 0 0x40000>;
            reg = <0 0x16000000 0 0x1000>;		/* VDEC_SYS */
            vcodec-lat@10000 {
                compatible = "mediatek,mtk-vcodec-lat";
                reg = <0 0x10000 0 0x800>;
                interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
                iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
                    <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
                    <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
                    <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
                    <&vdecsys_soc CLK_VDEC_SOC_LAT>,
                    <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
                    <&topckgen CLK_TOP_MAINPLL_D4>;
                clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
                power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
            };

            vcodec-core@25000 {
                compatible = "mediatek,mtk-vcodec-core";
                reg = <0 0x25000 0 0x1000>;
                interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
                iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
                    <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
                    <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
                    <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
                    <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
                    <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
                    <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
                    <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
                    <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
                    <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
                    <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
                clocks = <&topckgen CLK_TOP_VDEC_SEL>,
                    <&vdecsys CLK_VDEC_VDEC>,
                    <&vdecsys CLK_VDEC_LAT>,
                    <&vdecsys CLK_VDEC_LARB1>,
                    <&topckgen CLK_TOP_MAINPLL_D4>;
                clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
                assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
                assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
                power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek JPEG Decoder

maintainers:
  - Xia Jiang <xia.jiang@mediatek.com>

description: |-
  Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt8173-jpgdec
              - mediatek,mt2701-jpgdec
      - items:
          - enum:
              - mediatek,mt7623-jpgdec
              - mediatek,mt8188-jpgdec
          - const: mediatek,mt2701-jpgdec

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 2
    minItems: 2

  clock-names:
    items:
      - const: jpgdec-smi
      - const: jpgdec

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 2
    description: |
      Points to the respective IOMMU block with master port as argument, see
      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
      Ports are according to the HW.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains
  - iommus

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt2701-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/mt2701-larb-port.h>
    #include <dt-bindings/power/mt2701-power.h>
    jpegdec: jpegdec@15004000 {
      compatible = "mediatek,mt2701-jpgdec";
      reg = <0x15004000 0x1000>;
      interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
      clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
                <&imgsys CLK_IMG_JPGDEC>;
      clock-names = "jpgdec-smi",
                    "jpgdec";
      power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
      iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
               <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek-jpeg-encoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek JPEG Encoder

maintainers:
  - Xia Jiang <xia.jiang@mediatek.com>

description: |-
  MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt2701-jpgenc
          - mediatek,mt8183-jpgenc
          - mediatek,mt8186-jpgenc
          - mediatek,mt8188-jpgenc
      - const: mediatek,mtk-jpgenc
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: jpgenc

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 2
    description: |
      Points to the respective IOMMU block with master port as argument, see
      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
      Ports are according to the HW.

  dma-ranges:
    maxItems: 1
    description: |
      Describes the physical address space of IOMMU maps to memory.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains
  - iommus

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt2701-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/mt2701-larb-port.h>
    #include <dt-bindings/power/mt2701-power.h>
    jpegenc: jpegenc@1500a000 {
      compatible = "mediatek,mt2701-jpgenc",
                   "mediatek,mtk-jpgenc";
      reg = <0x1500a000 0x1000>;
      interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
      clocks =  <&imgsys CLK_IMG_VENC>;
      clock-names = "jpgenc";
      power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
      iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
               <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
    };