code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC).
 *
 * Copyright (C) 2015 Seagate
 *
 * Author: Vincent Donnefort <vdonnefort@gmail.com>
 */

/*
 * TODO: add support for the white SATA LEDs associated with HDD 0 and 1.
 */

#include "armada-370.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x20000000>; /* 512 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;

		internal-regs {
			serial@12000 {
				status = "okay";
			};

			sata@a0000 {
				nr-ports = <2>;
				status = "okay";
			};

			ethernet@70000 {
				status = "okay";
				pinctrl-0 = <&ge0_rgmii_pins>;
				pinctrl-names = "default";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};

			i2c@11000 {
				status = "okay";
				pinctrl-0 = <&i2c0_pins>;
				pinctrl-names = "default";
				clock-frequency = <100000>;

				/* RTC - NXP 8563T (second source) */
				rtc@51 {
					compatible = "nxp,pcf8563";
					reg = <0x51>;
					interrupts = <110>;
				};
				/* RTC - MCP7940NT */
				rtc@6f {
					compatible = "microchip,mcp7941x";
					reg = <0x6f>;
					interrupts = <110>;
				};
			};
		};

	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";

		regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "SATA0 power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
		};
		regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "SATA1 power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
		};
	};

	gpio-fan {
		compatible = "gpio-fan";
		gpios = <&gpio2 0 GPIO_ACTIVE_HIGH
			 &gpio2 1 GPIO_ACTIVE_HIGH>;
	};

	gpio-keys {
		compatible = "gpio-keys";

		button-power {
			label = "Power button";
			linux,code = <KEY_POWER>;
			gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
			debounce-interval = <100>;
		};
		button-backup {
			label = "Backup button";
			linux,code = <KEY_OPTION>;
			gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
			debounce-interval = <100>;
		};
		button-reset {
			label = "Reset Button";
			linux,code = <KEY_RESTART>;
			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
			debounce-interval = <100>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		led-white-power {
			label = "dart:white:power";
			gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "timer";

		};
		led-red-power {
			label = "dart:red:power";
			gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
		};
		led-red-sata0 {
			label = "dart:red:sata0";
			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
		};
		led-red-sata1 {
			label = "dart:red:sata1";
			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
		};
	};

	gpio_poweroff {
		compatible = "gpio-poweroff";
		gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
	};
};

&pciec {
	status = "okay";

	/* USB 3.0 bridge ASM1042A */
	pcie@2,0 {
		status = "okay";
	};
};

&mdio {
	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";

	phy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&pinctrl {
	pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>;
	pinctrl-names = "default";

	hdd0_led_sata_pin: hdd0-led-sata-pin {
		marvell,pins = "mpp48";
		marvell,function = "sata1";
	};
	hdd0_led_gpio_pin: hdd0-led-gpio-pin {
		marvell,pins = "mpp48";
		marvell,function = "gpio";
	};
	hdd1_led_sata_pin: hdd1-led-sata-pin {
		marvell,pins = "mpp57";
		marvell,function = "sata0";
	};
	hdd1_led_gpio_pin: hdd1-led-gpio-pin {
		marvell,pins = "mpp57";
		marvell,function = "gpio";
	};
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		marvell,nand-keep-config;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x300000>;
			};
			partition@300000 {
				label = "device-tree";
				reg = <0x300000 0x20000>;
			};
			partition@320000 {
				label = "linux";
				reg = <0x320000 0x2000000>;
			};
			partition@2320000 {
				label = "rootfs";
				reg = <0x2320000 0xdce0000>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree file for Seagate Personal Cloud NAS 2-Bay (Armada 370 SoC).
 *
 * Copyright (C) 2015 Seagate
 *
 * Author: Simon Guinot <simon.guinot@sequanux.org>
 */

/*
 * Here are some information allowing to identify the device:
 *
 * Product name                 : Seagate Personal Cloud 2-Bay
 * Code name (board/PCB)        : Cumulus Max
 * Model name (case sticker)    : SRN22C
 * Material desc (product spec) : STCSxxxxxxx
 */

/dts-v1/;
#include "armada-370-seagate-personal-cloud.dtsi"

/ {
	model = "Seagate Personal Cloud 2-Bay (Cumulus, SRN22C)";
	compatible = "seagate,cumulus-max", "marvell,armada370", "marvell,armada-370-xp";

	soc {
		internal-regs {
			sata@a0000 {
				status = "okay";
				nr-ports = <2>;
			};
		};
	};

	regulators {
		regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "SATA1 power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree file for Seagate Personal Cloud NAS (Armada 370 SoC).
 *
 * Copyright (C) 2015 Seagate
 *
 * Author: Simon Guinot <simon.guinot@sequanux.org>
 */

/*
 * Here are some information allowing to identify the device:
 *
 * Product name                 : Seagate Personal Cloud
 * Code name (board/PCB)        : Cumulus
 * Model name (case sticker)    : SRN21C
 * Material desc (product spec) : STCRxxxxxxx
 */

/dts-v1/;
#include "armada-370-seagate-personal-cloud.dtsi"

/ {
	model = "Seagate Personal Cloud (Cumulus, SRN21C)";
	compatible = "seagate,cumulus", "marvell,armada370", "marvell,armada-370-xp";

	soc {
		internal-regs {
			sata@a0000 {
				status = "okay";
				nr-ports = <1>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay
 * (Armada 370 SoC).
 *
 * Copyright (C) 2015 Seagate
 *
 * Author: Simon Guinot <simon.guinot@sequanux.org>
 */

/*
 * TODO: add support for the white SATA LED.
 */

#include "armada-370.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x20000000>; /* 512 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;

		internal-regs {
			coherency-fabric@20200 {
				broken-idle;
			};

			serial@12000 {
				status = "okay";
			};

			ethernet@74000 {
				status = "okay";
				pinctrl-0 = <&ge1_rgmii_pins>;
				pinctrl-names = "default";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};

			usb@50000 {
				status = "okay";
			};
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "USB Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio1 27 GPIO_ACTIVE_LOW>;
		};
		regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "SATA0 power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		button-power {
			label = "Power button";
			linux,code = <KEY_POWER>;
			gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
			debounce-interval = <100>;
		};
		button-reset {
			label = "Reset Button";
			linux,code = <KEY_RESTART>;
			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
			debounce-interval = <100>;
		};
		button-usb {
			label = "USB VBUS error";
			linux,code = <KEY_UNKNOWN>;
			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
			debounce-interval = <100>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		led-red-sata0 {
			label = "cumulus:red:sata0";
			gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	gpio_poweroff {
		compatible = "gpio-poweroff";
		gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
	};
};

&pciec {
	status = "okay";

	/* USB 3.0 Bridge ASM1042A */
	pcie@1,0 {
		status = "okay";
	};
};

&mdio {
	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";

	phy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&pinctrl {
	pinctrl-0 = <&sata_led_pin>;
	pinctrl-names = "default";

	sata_led_pin: sata-led-pin {
		marvell,pins = "mpp60";
		marvell,function = "sata0";
	};
	gpio_led_pin: gpio-led-pin {
		marvell,pins = "mpp60";
		marvell,function = "gpio";
	};
};

&spi0 {
	status = "okay";
	pinctrl-0 = <&spi0_pins2>;
	pinctrl-names = "default";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		/* MX25L8006E */
		compatible = "mxicy,mx25l8005", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <50000000>;

		partition@0 {
			label = "u-boot";
			reg = <0x0 0x100000>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Synology DS213j
 *
 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
 *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
 * bootloaders provided by Marvell. It is used in recent versions of
 * DSM software provided by Synology. Nonetheless, some earlier boards
 * were delivered with an older version of u-boot that left internal
 * registers mapped at 0xd0000000. If you have such a device you will
 * not be able to directly boot a kernel based on this Device Tree. In
 * that case, the preferred solution is to update your bootloader (e.g.
 * by upgrading to latest version of DSM, or building a new one and
 * installing it from u-boot prompt) or adjust the Devive Tree
 * (s/0xf1000000/0xd0000000/ in 'ranges' below).
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi"

/ {
	model = "Synology DS213j";
	compatible = "synology,ds213j", "marvell,armada370",
		     "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x20000000>; /* 512 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;

		internal-regs {

			/* RTC provided by Seiko S-35390A I2C RTC chip below */
			rtc@10300 {
				status = "disabled";
			};

			i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				pinctrl-0 = <&i2c0_pins>;
				pinctrl-names = "default";
				clock-frequency = <400000>;
				status = "okay";

				/* Main device RTC chip */
				s35390a: s35390a@30 {
					 compatible = "sii,s35390a";
					 reg = <0x30>;
				};
			};

			/* Connected to a header on device's PCB */
			serial@12000 {
				status = "okay";
			};

			/* Connected to a TI MSP430F2111 for power control */
			serial@12100 {
				status = "okay";
			};

			poweroff@12100 {
				compatible = "synology,power-off";
				reg = <0x12100 0x100>;
				clocks = <&coreclk 0>;
			};

			/* rear USB port, near reset button */
			usb@50000 {
				status = "okay";
			};

			/* rear USB port, near RJ45 port */
			usb@51000 {
				status = "okay";
			};

			ethernet@70000 {
				status = "okay";
				phy = <&phy1>;
				phy-mode = "sgmii";
			};

			sata@a0000 {
				nr-ports = <2>;
				status = "okay";
			};
		};
	};

	gpio-fan-32-38 {
		status = "okay";
		compatible = "gpio-fan";
		pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin
			     &fan_ctrl_high_pin &fan_alarm_pin>;
		pinctrl-names = "default";
		gpios = <&gpio1 31 GPIO_ACTIVE_HIGH
			 &gpio2  0 GPIO_ACTIVE_HIGH
			 &gpio2  1 GPIO_ACTIVE_HIGH>;
		alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
		gpio-fan,speed-map = <    0 0
				       1000 1
				       1150 2
				       1350 4
				       1500 3
				       1650 5
				       1750 6
				       1900 7 >;
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&disk1_led_pin
			     &disk2_led_pin>;
		pinctrl-names = "default";

		disk1-led-amber {
			label = "synology:amber:disk1";
			gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
			default-state = "keep";
		};

		disk2-led-amber {
			label = "synology:amber:disk2";
			gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
			default-state = "keep";
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>;
		pinctrl-names = "default";

		sata1_regulator: sata1-regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "SATA1 Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			startup-delay-us = <2000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
		};

		sata2_regulator: sata2-regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "SATA2 Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			startup-delay-us = <4000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
		};
	};
};

&mdio {
	phy1: ethernet-phy@1 { /* Marvell 88E1512 */
		reg = <1>;
	};
};

&pinctrl {
	disk1_led_pin: disk1-led-pin {
		marvell,pins = "mpp31";
		marvell,function = "gpio";
	};

	disk2_led_pin: disk2-led-pin {
		marvell,pins = "mpp32";
		marvell,function = "gpio";
	};

	sata1_pwr_pin: sata1-pwr-pin {
		marvell,pins = "mpp37";
		marvell,function = "gpio";
	};

	sata2_pwr_pin: sata2-pwr-pin {
		marvell,pins = "mpp62";
		marvell,function = "gpio";
	};

	sata1_pres_pin: sata1-pres-pin {
		marvell,pins = "mpp60";
		marvell,function = "gpio";
	};

	sata2_pres_pin: sata2-pres-pin {
		marvell,pins = "mpp48";
		marvell,function = "gpio";
	};

	syno_id_bit0_pin: syno-id-bit0-pin {
		marvell,pins = "mpp55";
		marvell,function = "gpio";
	};

	syno_id_bit1_pin: syno-id-bit1-pin {
		marvell,pins = "mpp56";
		marvell,function = "gpio";
	};

	syno_id_bit2_pin: syno-id-bit2-pin {
		marvell,pins = "mpp57";
		marvell,function = "gpio";
	};

	syno_id_bit3_pin: syno-id-bit3-pin {
		marvell,pins = "mpp58";
		marvell,function = "gpio";
	};

	fan_ctrl_low_pin: fan-ctrl-low-pin {
		marvell,pins = "mpp65";
		marvell,function = "gpio";
	};

	fan_ctrl_mid_pin: fan-ctrl-mid-pin {
		marvell,pins = "mpp64";
		marvell,function = "gpio";
	};

	fan_ctrl_high_pin: fan-ctrl-high-pin {
		marvell,pins = "mpp63";
		marvell,function = "gpio";
	};

	fan_alarm_pin: fan-alarm-pin {
		marvell,pins = "mpp38";
		marvell,function = "gpio";
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q064", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <20000000>;

		/*
		 * Warning!
		 *
		 * Synology u-boot uses its compiled-in environment
		 * and it seems Synology did not care to change u-boot
		 * default configuration in order to allow saving a
		 * modified environment at a sensible location. So,
		 * if you do a 'saveenv' under u-boot, your modified
		 * environment will be saved at 1MB after the start
		 * of the flash, i.e. in the middle of the uImage.
		 * For that reason, it is strongly advised not to
		 * change the default environment, unless you know
		 * what you are doing.
		 */
		partition@0 { /* u-boot */
			label = "RedBoot";
			reg = <0x00000000 0x000c0000>; /* 768KB */
		};

		partition@c0000 { /* uImage */
			label = "zImage";
			reg = <0x000c0000 0x002d0000>; /* 2880KB */
		};

		partition@390000 { /* uInitramfs */
			label = "rd.gz";
			reg = <0x00390000 0x00440000>; /* 4250KB */
		};

		partition@7d0000 { /* MAC address and serial number */
			label = "vendor";
			reg = <0x007d0000 0x00010000>; /* 64KB */
		};

		partition@7e0000 {
			label = "RedBoot config";
			reg = <0x007e0000 0x00010000>; /* 64KB */
		};

		partition@7f0000 {
			label = "FIS directory";
			reg = <0x007f0000 0x00010000>; /* 64KB */
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file contains the definitions that are common to the Armada
 * 370 and Armada XP SoC.
 */

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	model = "Marvell Armada 370 and XP SoC";
	compatible = "marvell,armada-370-xp";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "marvell,sheeva-v7";
			device_type = "cpu";
			reg = <0>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts-extended = <&mpic 3>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&mpic>;
		pcie-mem-aperture = <0xf8000000 0x7e00000>;
		pcie-io-aperture  = <0xffe00000 0x100000>;

		devbus_bootcs: devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs0: devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs1: devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs2: devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs3: devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			rtc: rtc@10300 {
				compatible = "marvell,orion-rtc";
				reg = <0x10300 0x20>;
				interrupts = <50>;
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <31>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <32>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart0: serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <41>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <42>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl: pin-ctrl@18000 {
				reg = <0x18000 0x38>;
			};

			coredivclk: corediv-clock@18740 {
				compatible = "marvell,armada-370-corediv-clock";
				reg = <0x18740 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>,
				      <0x20250 0x8>;
			};

			mpic: interrupt-controller@20a00 {
				compatible = "marvell,mpic";
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
			};

			coherencyfab: coherency-fabric@20200 {
				compatible = "marvell,coherency-fabric";
				reg = <0x20200 0xb0>, <0x21010 0x1c>;
			};

			timer: timer@20300 {
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
			};

			watchdog: watchdog@20300 {
				reg = <0x20300 0x34>, <0x20704 0x4>;
			};

			cpurst: cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x8>;
			};

			pmsu: pmsu@22000 {
				compatible = "marvell,armada-370-pmsu";
				reg = <0x22000 0x1000>;
			};

			usb0: usb@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x500>;
				interrupts = <45>;
				status = "disabled";
			};

			usb1: usb@51000 {
				compatible = "marvell,orion-ehci";
				reg = <0x51000 0x500>;
				interrupts = <46>;
				status = "disabled";
			};

			eth0: ethernet@70000 {
				reg = <0x70000 0x4000>;
				interrupts = <8>;
				clocks = <&gateclk 4>;
				status = "disabled";
			};

			mdio: mdio@72004 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x72004 0x4>;
				clocks = <&gateclk 4>;
			};

			eth1: ethernet@74000 {
				reg = <0x74000 0x4000>;
				interrupts = <10>;
				clocks = <&gateclk 3>;
				status = "disabled";
			};

			sata: sata@a0000 {
				compatible = "marvell,armada-370-sata";
				reg = <0xa0000 0x5000>;
				interrupts = <55>;
				clocks = <&gateclk 15>, <&gateclk 30>;
				clock-names = "0", "1";
				status = "disabled";
			};

			nand_controller: nand-controller@d0000 {
				compatible = "marvell,armada370-nand-controller";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <113>;
				clocks = <&coredivclk 0>;
				status = "disabled";
			};

			sdio: mvsdio@d4000 {
				compatible = "marvell,orion-sdio";
				reg = <0xd4000 0x200>;
				interrupts = <54>;
				clocks = <&gateclk 17>;
				bus-width = <4>;
				cap-sdio-irq;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				status = "disabled";
			};
		};

		spi0: spi@10600 {
			reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
			      <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
			      <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
			      <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
			      <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
			      <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
			      <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
			      <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
			      <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			interrupts = <30>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		spi1: spi@10680 {
			reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
			      <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
			      <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
			      <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
			      <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
			      <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
			      <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
			      <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
			      <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			interrupts = <92>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};
	};

	clocks {
		/* 2 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <2000000000>;
		};
	};
 };


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 370 family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * Contains definitions specific to the Armada 370 SoC that are not
 * common to all Armada SoCs.
 */

#include "armada-370-xp.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	model = "Marvell Armada 370 family SoC";
	compatible = "marvell,armada370", "marvell,armada-370-xp";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	soc {
		compatible = "marvell,armada370-mbus", "simple-bus";

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
		};

		pciec: pcie@82000000 {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
				0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;

			pcie0: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 58>;
				#interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie0_intc 0>,
						<0 0 0 2 &pcie0_intc 1>,
						<0 0 0 3 &pcie0_intc 2>,
						<0 0 0 4 &pcie0_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";

				pcie0_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie2: pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82001000 0 0x80000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&mpic 62>;
				#interrupt-cells = <1>;
                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
						<0 0 0 2 &pcie2_intc 1>,
						<0 0 0 3 &pcie2_intc 2>,
						<0 0 0 4 &pcie2_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 9>;
				status = "disabled";

				pcie2_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};
		};

		internal-regs {
			L2: l2-cache@8000 {
				compatible = "marvell,aurora-outer-cache";
				reg = <0x08000 0x1000>;
				cache-id-part = <0x100>;
				cache-level = <2>;
				cache-unified;
				wt-override;
			};

			gpio0: gpio@18100 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18100 0x40>, <0x181c0 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <82>, <83>, <84>, <85>;
				clocks = <&coreclk 0>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18140 0x40>, <0x181c8 0x08>;
				reg-names = "gpio", "pwm";
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				#pwm-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <87>, <88>, <89>, <90>;
				clocks = <&coreclk 0>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,armada-370-gpio",
					     "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <2>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <91>;
			};

			systemc: system-controller@18200 {
				compatible = "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x100>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-370-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			coreclk: mvebu-sar@18230 {
				compatible = "marvell,armada-370-core-clock";
				reg = <0x18230 0x08>;
				#clock-cells = <1>;
			};

			thermal: thermal@18300 {
				compatible = "marvell,armada370-thermal";
				reg = <0x18300 0x4
					0x18304 0x4>;
				status = "okay";
			};

			sscg: sscg@18330 {
				reg = <0x18330 0x4>;
			};

			cpuconf: cpu-config@21000 {
				compatible = "marvell,armada-370-cpu-config";
				reg = <0x21000 0x8>;
			};

			audio_controller: audio-controller@30000 {
				#sound-dai-cells = <1>;
				compatible = "marvell,armada370-audio";
				reg = <0x30000 0x4000>;
				interrupts = <93>;
				clocks = <&gateclk 0>;
				clock-names = "internal";
				status = "disabled";
			};

			xor0: xor@60800 {
				compatible = "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60A00 0x100>;
				status = "okay";

				xor00 {
					interrupts = <51>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <52>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor1: xor@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				status = "okay";

				xor10 {
					interrupts = <94>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <95>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			cesa: crypto@90000 {
				compatible = "marvell,armada-370-crypto";
				reg = <0x90000 0x10000>;
				reg-names = "regs";
				interrupts = <48>;
				clocks = <&gateclk 23>;
				clock-names = "cesa0";
				marvell,crypto-srams = <&crypto_sram>;
				marvell,crypto-sram-size = <0x7e0>;
			};
		};

		crypto_sram: sa-sram {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
			reg-names = "sram";
			clocks = <&gateclk 23>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;

			/*
			 * The Armada 370 has an erratum preventing the use of
			 * the standard workflow for CPU idle support (relying
			 * on the BootROM code to enter/exit idle state).
			 * Reserve some amount of the crypto SRAM to put the
			 * cpuidle workaround.
			 */
			idle-sram@0 {
				reg = <0x0 0x20>;
			};
		};
	};
};

/*
 * Default UART pinctrl setting without RTS/CTS, can be overwritten on
 * board level if a different configuration is used.
 */

&uart0 {
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
};

&uart1 {
	pinctrl-0 = <&uart1_pins>;
	pinctrl-names = "default";
};

&i2c0 {
	reg = <0x11000 0x20>;
};

&i2c1 {
	reg = <0x11100 0x20>;
};

&mpic {
	reg = <0x20a00 0x1d0>, <0x21870 0x58>;
};

&timer {
	compatible = "marvell,armada-370-timer";
	clocks = <&coreclk 2>;
};

&watchdog {
	compatible = "marvell,armada-370-wdt";
	clocks = <&coreclk 2>;
};

&usb0 {
	clocks = <&coreclk 0>;
};

&usb1 {
	clocks = <&coreclk 0>;
};

&eth0 {
	compatible = "marvell,armada-370-neta";
};

&eth1 {
	compatible = "marvell,armada-370-neta";
};

&pinctrl {
	compatible = "marvell,mv88f6710-pinctrl";

	spi0_pins1: spi0-pins1 {
		marvell,pins = "mpp33", "mpp34",
			       "mpp35", "mpp36";
		marvell,function = "spi0";
	};

	spi0_pins2: spi0_pins2 {
		marvell,pins = "mpp32", "mpp63",
			       "mpp64", "mpp65";
		marvell,function = "spi0";
	};

	spi1_pins: spi1-pins {
		marvell,pins = "mpp49", "mpp50",
			       "mpp51", "mpp52";
		marvell,function = "spi1";
	};

	uart0_pins: uart0-pins {
		marvell,pins = "mpp0", "mpp1";
		marvell,function = "uart0";
	};

	uart1_pins: uart1-pins {
		marvell,pins = "mpp41", "mpp42";
		marvell,function = "uart1";
	};

	sdio_pins1: sdio-pins1 {
		marvell,pins = "mpp9",  "mpp11", "mpp12",
				"mpp13", "mpp14", "mpp15";
		marvell,function = "sd0";
	};

	sdio_pins2: sdio-pins2 {
		marvell,pins = "mpp47", "mpp48", "mpp49",
				"mpp50", "mpp51", "mpp52";
		marvell,function = "sd0";
	};

	sdio_pins3: sdio-pins3 {
		marvell,pins = "mpp48", "mpp49", "mpp50",
				"mpp51", "mpp52", "mpp53";
		marvell,function = "sd0";
	};

	i2c0_pins: i2c0-pins {
		marvell,pins = "mpp2", "mpp3";
		marvell,function = "i2c0";
	};

	i2s_pins1: i2s-pins1 {
		marvell,pins = "mpp5", "mpp6", "mpp7",
			       "mpp8", "mpp9", "mpp10",
			       "mpp12", "mpp13";
		marvell,function = "audio";
	};

	i2s_pins2: i2s-pins2 {
		marvell,pins = "mpp49", "mpp47", "mpp50",
			       "mpp59", "mpp57", "mpp61",
			       "mpp62", "mpp60", "mpp58";
		marvell,function = "audio";
	};

	mdio_pins: mdio-pins {
		marvell,pins = "mpp17", "mpp18";
		marvell,function = "ge";
	};

	ge0_rgmii_pins: ge0-rgmii-pins {
		marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
			       "mpp9", "mpp10", "mpp11", "mpp12",
			       "mpp13", "mpp14", "mpp15", "mpp16";
		marvell,function = "ge0";
	};

	ge1_rgmii_pins: ge1-rgmii-pins {
		marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
			       "mpp23", "mpp24", "mpp25", "mpp26",
			       "mpp27", "mpp28", "mpp29", "mpp30";
		marvell,function = "ge1";
	};
};

/*
 * Default SPI pinctrl setting, can be overwritten on
 * board level if a different configuration is used.
 */
&spi0 {
	compatible = "marvell,armada-370-spi", "marvell,orion-spi";
	pinctrl-0 = <&spi0_pins1>;
	pinctrl-names = "default";
};

&spi1 {
	compatible = "marvell,armada-370-spi", "marvell,orion-spi";
	pinctrl-0 = <&spi1_pins>;
	pinctrl-names = "default";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell Armada 375 evaluation board
 * (DB-88F6720)
 *
 *  Copyright (C) 2014 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-375.dtsi"

/ {
	model = "Marvell Armada 375 Development Board";
	compatible = "marvell,a375-db", "marvell,armada375";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x40000000>; /* 1 GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;

	};
};
&pciec {
	status = "okay";
};

/*
 * The two PCIe units are accessible through
 * standard PCIe slots on the board.
 */
&pcie0 {
	/* Port 0, Lane 0 */
	status = "okay";
};

&pcie1 {
	/* Port 1, Lane 0 */
	status = "okay";
};

&spi0 {
	pinctrl-0 = <&spi0_pins>;
	pinctrl-names = "default";

	/*
	 * SPI conflicts with NAND, so we disable it here, and
	 * select NAND as the enabled device by default.
	 */

	status = "disabled";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "n25q128a13", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <108000000>;
	};
};

&i2c0 {
	status = "okay";
	clock-frequency = <100000>;
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";
};

&i2c1 {
	status = "okay";
	clock-frequency = <100000>;
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "default";
};

&uart0 {
	status = "okay";
};

&pinctrl {
	sdio_st_pins: sdio-st-pins {
		marvell,pins = "mpp44", "mpp45";
		marvell,function = "gpio";
	};
};

&sata {
	status = "okay";
	nr-ports = <2>;
};

&nand_controller {
	status = "okay";
	pinctrl-0 = <&nand_pins>;
	pinctrl-names = "default";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		marvell,nand-keep-config;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0 0x800000>;
			};
			partition@800000 {
				label = "Linux";
				reg = <0x800000 0x800000>;
			};
			partition@1000000 {
				label = "Filesystem";
				reg = <0x1000000 0x3f000000>;
			};
		};
	};
};

&usb1 {
	status = "okay";
};

&usb2 {
	status = "okay";
};

&sdio {
	pinctrl-0 = <&sdio_pins &sdio_st_pins>;
	pinctrl-names = "default";
	status = "okay";
	cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};

&mdio {
	phy0: ethernet-phy@0 {
		reg = <0>;
	};

	phy3: ethernet-phy@3 {
		reg = <3>;
	};
};

&ethernet {
	status = "okay";
};

&eth0 {
	status = "okay";
	phy = <&phy0>;
	phy-mode = "rgmii-id";
};

&eth1 {
	status = "okay";
	phy = <&phy3>;
	phy-mode = "gmii";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 375 family SoC
 *
 * Copyright (C) 2014 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	model = "Marvell Armada 375 family SoC";
	compatible = "marvell,armada375";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		serial0 = &uart0;
		serial1 = &uart1;
	};

	clocks {
		/* 1 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000000>;
		};
		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-375-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts-extended = <&mpic 3>;
	};

	soc {
		compatible = "marvell,armada375-mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&gic>;
		pcie-mem-aperture = <0xe0000000 0x8000000>;
		pcie-io-aperture  = <0xe8000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
		};

		devbus_bootcs: devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs0: devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs1: devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs2: devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus_cs3: devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			L2: cache-controller@8000 {
				compatible = "arm,pl310-cache";
				reg = <0x8000 0x1000>;
				cache-unified;
				cache-level = <2>;
				arm,double-linefill-incr = <0>;
				arm,double-linefill-wrap = <0>;
				arm,double-linefill = <0>;
				prefetch-data = <1>;
			};

			scu: scu@c000 {
				compatible = "arm,cortex-a9-scu";
				reg = <0xc000 0x58>;
			};

			timer0: timer@c600 {
				compatible = "arm,cortex-a9-twd-timer";
				reg = <0xc600 0x20>;
				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
				clocks = <&coreclk 2>;
			};

			gic: interrupt-controller@d000 {
				compatible = "arm,cortex-a9-gic";
				#interrupt-cells = <3>;
				#size-cells = <0>;
				interrupt-controller;
				reg = <0xd000 0x1000>,
				      <0xc100 0x100>;
			};

			mdio: mdio@c0054 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0xc0054 0x4>;
				clocks = <&gateclk 19>;
			};

			/* Network controller */
			ethernet: ethernet@f0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,armada-375-pp2";
				reg = <0xf0000 0xa000>, /* Packet Processor regs */
				      <0xc0000 0x3060>, /* LMS regs */
				      <0xc4000 0x100>,  /* eth0 regs */
				      <0xc5000 0x100>;  /* eth1 regs */
				clocks = <&gateclk 3>, <&gateclk 19>;
				clock-names = "pp_clk", "gop_clk";
				status = "disabled";

				eth0: ethernet-port@0 {
					interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
					reg = <0>;
					port-id = <0>; /* For backward compatibility. */
					status = "disabled";
				};

				eth1: ethernet-port@1 {
					interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
					reg = <1>;
					port-id = <1>; /* For backward compatibility. */
					status = "disabled";
				};
			};

			rtc: rtc@10300 {
				compatible = "marvell,orion-rtc";
				reg = <0x10300 0x20>;
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			};

			spi0: spi@10600 {
				compatible = "marvell,armada-375-spi",
						"marvell,orion-spi";
				reg = <0x10600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			spi1: spi@10680 {
				compatible = "marvell,armada-375-spi",
						"marvell,orion-spi";
				reg = <0x10680 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <1>;
				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart0: serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl: pinctrl@18000 {
				compatible = "marvell,mv88f6720-pinctrl";
				reg = <0x18000 0x24>;

				i2c0_pins: i2c0-pins {
					marvell,pins = "mpp14",  "mpp15";
					marvell,function = "i2c0";
				};

				i2c1_pins: i2c1-pins {
					marvell,pins = "mpp61",  "mpp62";
					marvell,function = "i2c1";
				};

				nand_pins: nand-pins {
					marvell,pins = "mpp0", "mpp1", "mpp2",
						"mpp3", "mpp4", "mpp5",
						"mpp6", "mpp7", "mpp8",
						"mpp9", "mpp10", "mpp11",
						"mpp12", "mpp13";
					marvell,function = "nand";
				};

				sdio_pins: sdio-pins {
					marvell,pins = "mpp24",  "mpp25", "mpp26",
						     "mpp27", "mpp28", "mpp29";
					marvell,function = "sd";
				};

				spi0_pins: spi0-pins {
					marvell,pins = "mpp0",  "mpp1", "mpp4",
						     "mpp5", "mpp8", "mpp9";
					marvell,function = "spi0";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio2: gpio@18180 {
				compatible = "marvell,orion-gpio";
				reg = <0x18180 0x40>;
				ngpios = <3>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			};

			systemc: system-controller@18200 {
				compatible = "marvell,armada-375-system-controller";
				reg = <0x18200 0x100>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-375-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			usbcluster: usb-cluster@18400 {
				compatible = "marvell,armada-375-usb-cluster";
				reg = <0x18400 0x4>;
				#phy-cells = <1>;
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>;
			};

			mpic: interrupt-controller@20a00 {
				compatible = "marvell,mpic";
				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			timer1: timer@20300 {
				compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
						      <&mpic 5>,
						      <&mpic 6>;
				clocks = <&coreclk 0>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			watchdog: watchdog@20300 {
				compatible = "marvell,armada-375-wdt";
				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
				clocks = <&coreclk 0>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			cpurst: cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x10>;
			};

			coherencyfab: coherency-fabric@21010 {
				compatible = "marvell,armada-375-coherency-fabric";
				reg = <0x21010 0x1c>;
			};

			usb0: usb@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x500>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 18>;
				phys = <&usbcluster PHY_TYPE_USB2>;
				phy-names = "usb";
				status = "disabled";
			};

			usb1: usb@54000 {
				compatible = "marvell,orion-ehci";
				reg = <0x54000 0x500>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 26>;
				status = "disabled";
			};

			usb2: usb@58000 {
				compatible = "marvell,armada-375-xhci";
				reg = <0x58000 0x20000>,<0x5b880 0x80>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 16>;
				phys = <&usbcluster PHY_TYPE_USB3>;
				phy-names = "usb";
				status = "disabled";
			};

			xor0: xor@60800 {
				compatible = "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60A00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor00 {
					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor1: xor@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 23>;
				status = "okay";

				xor10 {
					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			cesa: crypto@90000 {
				compatible = "marvell,armada-375-crypto";
				reg = <0x90000 0x10000>;
				reg-names = "regs";
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 30>, <&gateclk 31>,
					 <&gateclk 28>, <&gateclk 29>;
				clock-names = "cesa0", "cesa1",
					      "cesaz0", "cesaz1";
				marvell,crypto-srams = <&crypto_sram0>,
						       <&crypto_sram1>;
				marvell,crypto-sram-size = <0x800>;
			};

			sata: sata@a0000 {
				compatible = "marvell,armada-370-sata";
				reg = <0xa0000 0x5000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 14>, <&gateclk 20>;
				clock-names = "0", "1";
				status = "disabled";
			};

			nand_controller: nand-controller@d0000 {
				compatible = "marvell,armada370-nand-controller";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 11>;
				status = "disabled";
			};

			sdio: mvsdio@d4000 {
				compatible = "marvell,orion-sdio";
				reg = <0xd4000 0x200>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 17>;
				bus-width = <4>;
				cap-sdio-irq;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				status = "disabled";
			};

			thermal: thermal@e8078 {
				compatible = "marvell,armada375-thermal";
				reg = <0xe8078 0x4>, <0xe807c 0x8>;
				status = "okay";
			};

			coreclk: mvebu-sar@e8204 {
				compatible = "marvell,armada-375-core-clock";
				reg = <0xe8204 0x04>;
				#clock-cells = <1>;
			};

			coredivclk: corediv-clock@e8250 {
				compatible = "marvell,armada-375-corediv-clock";
				reg = <0xe8250 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};
		};

		pciec: pcie@82000000 {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;

			pcie0: pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie0_intc 0>,
						<0 0 0 2 &pcie0_intc 1>,
						<0 0 0 3 &pcie0_intc 2>,
						<0 0 0 4 &pcie0_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";

				pcie0_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie1: pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
						<0 0 0 2 &pcie1_intc 1>,
						<0 0 0 3 &pcie1_intc 2>,
						<0 0 0 4 &pcie1_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <1>;
				clocks = <&gateclk 6>;
				status = "disabled";

				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

		};

		crypto_sram0: sa-sram0 {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
			clocks = <&gateclk 30>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
		};

		crypto_sram1: sa-sram1 {
			compatible = "mmio-sram";
			reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
			clocks = <&gateclk 31>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 380 SoC.
 *
 * Copyright (C) 2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 */

#include "armada-38x.dtsi"

/ {
	model = "Marvell Armada 380 family SoC";
	compatible = "marvell,armada380";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,armada-380-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
	};

	soc {
		internal-regs {
			pinctrl@18000 {
				compatible = "marvell,mv88f6810-pinctrl";
			};
		};

		pcie {
			compatible = "marvell,armada-370-pcie";
			status = "disabled";
			device_type = "pci";

			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&mpic>;
			bus-range = <0x00 0xff>;

			ranges =
			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */>;

			/* x1 port */
			pcie@1,0 {
				device_type = "pci";
				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
						<0 0 0 2 &pcie1_intc 1>,
						<0 0 0 3 &pcie1_intc 2>,
						<0 0 0 4 &pcie1_intc 3>;
				marvell,pcie-port = <0>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 8>;
				status = "disabled";

				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			/* x1 port */
			pcie@2,0 {
				device_type = "pci";
				assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
						<0 0 0 2 &pcie2_intc 1>,
						<0 0 0 3 &pcie2_intc 2>,
						<0 0 0 4 &pcie2_intc 3>;
				marvell,pcie-port = <1>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 5>;
				status = "disabled";

				pcie2_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			/* x1 port */
			pcie@3,0 {
				device_type = "pci";
				assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
				reg = <0x1800 0 0 0 0>;
				#address-cells = <3>;
				#size-cells = <2>;
				interrupt-names = "intx";
				interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
				bus-range = <0x00 0xff>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
						<0 0 0 2 &pcie3_intc 1>,
						<0 0 0 3 &pcie3_intc 2>,
						<0 0 0 4 &pcie3_intc 3>;
				marvell,pcie-port = <2>;
				marvell,pcie-lane = <0>;
				clocks = <&gateclk 6>;
				status = "disabled";

				pcie3_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Marcel Ziswiler <marcel@ziswiler.com> */

/dts-v1/;
#include "armada-385.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "Netgear GS110EMX";
	compatible = "netgear,gs110emx", "marvell,armada380";

	aliases {
		/* So that mvebu u-boot can update the MAC addresses */
		ethernet1 = &eth0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&front_button_pins>;
		pinctrl-names = "default";

		key-factory-default {
			label = "Factory Default";
			gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x08000000>; /* 128 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;

		internal-regs {
			rtc@a3800 {
				/*
				 * If the rtc doesn't work, run "date reset"
				 * twice in u-boot.
				 */
				status = "okay";
			};
		};
	};
};

&eth0 {
	/* ethernet@70000 */
	bm,pool-long = <0>;
	bm,pool-short = <1>;
	buffer-manager = <&bm>;
	phy-mode = "rgmii-id";
	pinctrl-0 = <&ge0_rgmii_pins>;
	pinctrl-names = "default";
	status = "okay";

	fixed-link {
		full-duplex;
		pause;
		speed = <1000>;
	};
};

&mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	status = "okay";

	switch@0 {
		compatible = "marvell,mv88e6190";
		#address-cells = <1>;
		#interrupt-cells = <2>;
		interrupt-controller;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-0 = <&switch_interrupt_pins>;
		pinctrl-names = "default";
		#size-cells = <0>;
		reg = <0>;

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch0phy1: switch0phy1@1 {
				reg = <0x1>;
			};

			switch0phy2: switch0phy2@2 {
				reg = <0x2>;
			};

			switch0phy3: switch0phy3@3 {
				reg = <0x3>;
			};

			switch0phy4: switch0phy4@4 {
				reg = <0x4>;
			};

			switch0phy5: switch0phy5@5 {
				reg = <0x5>;
			};

			switch0phy6: switch0phy6@6 {
				reg = <0x6>;
			};

			switch0phy7: switch0phy7@7 {
				reg = <0x7>;
			};

			switch0phy8: switch0phy8@8 {
				reg = <0x8>;
			};
		};

		mdio-external {
			compatible = "marvell,mv88e6xxx-mdio-external";
			#address-cells = <1>;
			#size-cells = <0>;

			phy1: ethernet-phy@b {
				reg = <0xb>;
				compatible = "ethernet-phy-ieee802.3-c45";
			};

			phy2: ethernet-phy@c {
				reg = <0xc>;
				compatible = "ethernet-phy-ieee802.3-c45";
			};
		};

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				ethernet = <&eth0>;
				label = "cpu";
				reg = <0>;

				fixed-link {
					full-duplex;
					pause;
					speed = <1000>;
				};
			};

			port@1 {
				label = "lan1";
				phy-handle = <&switch0phy1>;
				reg = <1>;
			};

			port@2 {
				label = "lan2";
				phy-handle = <&switch0phy2>;
				reg = <2>;
			};

			port@3 {
				label = "lan3";
				phy-handle = <&switch0phy3>;
				reg = <3>;
			};

			port@4 {
				label = "lan4";
				phy-handle = <&switch0phy4>;
				reg = <4>;
			};

			port@5 {
				label = "lan5";
				phy-handle = <&switch0phy5>;
				reg = <5>;
			};

			port@6 {
				label = "lan6";
				phy-handle = <&switch0phy6>;
				reg = <6>;
			};

			port@7 {
				label = "lan7";
				phy-handle = <&switch0phy7>;
				reg = <7>;
			};

			port@8 {
				label = "lan8";
				phy-handle = <&switch0phy8>;
				reg = <8>;
			};

			port@9 {
				/* 88X3310P external phy */
				label = "lan9";
				phy-handle = <&phy1>;
				phy-mode = "xaui";
				reg = <9>;
			};

			port@a {
				/* 88X3310P external phy */
				label = "lan10";
				phy-handle = <&phy2>;
				phy-mode = "xaui";
				reg = <0xa>;
			};
		};
	};
};

&pinctrl {
	front_button_pins: front-button-pins {
		marvell,pins = "mpp38";
		marvell,function = "gpio";
	};

	switch_interrupt_pins: switch-interrupt-pins {
		marvell,pins = "mpp39";
		marvell,function = "gpio";
	};
};

&spi0 {
	pinctrl-0 = <&spi0_pins>;
	pinctrl-names = "default";
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <3000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "boot";
				read-only;
				reg = <0x00000000 0x00100000>;
			};

			partition@100000 {
				label = "env";
				reg = <0x00100000 0x00010000>;
			};

			partition@200000 {
				label = "rsv";
				reg = <0x00110000 0x00010000>;
			};

			partition@300000 {
				label = "image0";
				reg = <0x00120000 0x00900000>;
			};

			partition@400000 {
				label = "config";
				reg = <0x00a20000 0x00300000>;
			};

			partition@480000 {
				label = "debug";
				reg = <0x00d20000 0x002e0000>;
			};
		};
	};
};

&uart0 {
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for Marvell Armada 382 reference board
 * (RD-AC3X-48G4X2XL)
 *
 * Copyright (C) 2020 Allied Telesis Labs
 */

/dts-v1/;
#include "armada-385.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Marvell Armada 382 RD-AC3X";
	compatible = "marvell,rd-ac3x-48g4x2xl", "marvell,rd-ac3x",
			 "marvell,armada385", "marvell,armada380";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		ethernet0 = &eth1;
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>; /* 512MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "okay";

	eeprom@53{
		compatible = "atmel,24c64";
		reg = <0x53>;
	};

	/* CPLD device present at 0x3c. Function unknown */
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&eth1 {
	status = "okay";
	phy = <&phy0>;
	phy-mode = "rgmii-id";
};

&mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;

	phy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&pciec {
	status = "okay";
};

&pcie1 {
	/* Port 0, Lane 0 */
	status = "okay";
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		nand-on-flash-bbt;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			partition@0 {
				reg = <0x00000000 0x00500000>;
				label = "u-boot";
			};
			partition@500000{
				reg = <0x00500000 0x00400000>;
				label = "u-boot env";
			};
			partition@900000{
				reg = <0x00900000 0x3F700000>;
				label = "user";
			};
		};
	};
};

&refclk {
	clock-frequency = <200000000>;
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for Armada 385 Allied Telesis x530/GS980MX Board.
 (x530/AT-GS980MX)
 *
 Copyright (C) 2020 Allied Telesis Labs
 */

/dts-v1/;
#include "armada-385.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "x530/AT-GS980MX";
	compatible = "alliedtelesis,gs980mx", "alliedtelesis,x530", "marvell,armada385", "marvell,armada380";

	chosen {
		stdout-path = "serial1:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>; /* 1GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x3d) 0 0xf4800000 0x80000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;

		internal-regs {
			i2c0: i2c@11000 {
				pinctrl-names = "default";
				pinctrl-0 = <&i2c0_pins>;
				status = "okay";
			};

			uart0: serial@12000 {
				pinctrl-names = "default";
				pinctrl-0 = <&uart0_pins>;
				status = "okay";
			};
		};
	};
};

&pciec {
	status = "okay";
};

&pcie1 {
	status = "okay";
	reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
	reset-delay-us = <400000>;
};

&pcie2 {
	status = "okay";
};

&devbus_cs1 {
	compatible = "marvell,mvebu-devbus";
	status = "okay";

	devbus,bus-width    = <8>;
	devbus,turn-off-ps  = <60000>;
	devbus,badr-skew-ps = <0>;
	devbus,acc-first-ps = <124000>;
	devbus,acc-next-ps  = <248000>;
	devbus,rd-setup-ps  = <0>;
	devbus,rd-hold-ps   = <0>;

	/* Write parameters */
	devbus,sync-enable = <0>;
	devbus,wr-high-ps  = <60000>;
	devbus,wr-low-ps   = <60000>;
	devbus,ale-wr-ps   = <60000>;

	nvs@0 {
		status = "okay";

		compatible = "mtd-ram";
		reg = <0 0x00080000>;
		bank-width = <1>;
		label = "nvs";
	};
};

&pinctrl {
	i2c0_gpio_pins: i2c-gpio-pins-0 {
		marvell,pins = "mpp2", "mpp3";
		marvell,function = "gpio";
	};
};

&i2c0 {
	clock-frequency = <100000>;
	status = "okay";

	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-1 = <&i2c0_gpio_pins>;
	scl-gpio = <&gpio0 2 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
	sda-gpio = <&gpio0 3 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;

	i2c0mux: mux@71 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nxp,pca9544";
		reg = <0x71>;
		i2c-mux-idle-disconnect;

		i2c@0 { /* POE devices MUX */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			adt7476_2e: hwmon@2e {
				compatible = "adi,adt7476";
				reg = <0x2e>;
			};

			adt7476_2d: hwmon@2d {
				compatible = "adi,adt7476";
				reg = <0x2d>;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;

			rtc@68 {
				compatible = "dallas,ds1340";
				reg = <0x68>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;

			gpio@20 {
				compatible = "nxp,pca9554";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x20>;
			};
		};
	};
};

&usb0 {
	status = "okay";
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins>;
	status = "okay";

	flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <1>; /* Chip select 1 */
		spi-max-frequency = <54000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			partition@u-boot {
				reg = <0x00000000 0x00100000>;
				label = "u-boot";
			};
			partition@u-boot-env {
				reg = <0x00100000 0x00040000>;
				label = "u-boot-env";
			};
			partition@unused {
				reg = <0x00140000 0x00e80000>;
				label = "unused";
			};
			partition@idprom {
				reg = <0x00fc0000 0x00040000>;
				label = "idprom";
			};
		};
	};
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		marvell,nand-enable-arbiter;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			partition@user {
				reg = <0x00000000 0x0f000000>;
				label = "user";
			};
			partition@errlog {
				/* Maximum mtdoops size is 8MB, so set to that. */
				reg = <0x0f000000 0x00800000>;
				label = "errlog";
			};
			partition@nand-bbt {
				reg = <0x0f800000 0x00800000>;
				label = "nand-bbt";
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

#include "armada-385-clearfog-gtr.dtsi"

/ {
	model = "SolidRun Clearfog GTR L8";
};

&mdio {
	switch0: switch0@4 {
		compatible = "marvell,mv88e6190";
		reg = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&cf_gtr_switch_reset_pins>;
		reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <1>;
				label = "lan8";
				phy-handle = <&switch0phy0>;
			};

			port@2 {
				reg = <2>;
				label = "lan7";
				phy-handle = <&switch0phy1>;
			};

			port@3 {
				reg = <3>;
				label = "lan6";
				phy-handle = <&switch0phy2>;
			};

			port@4 {
				reg = <4>;
				label = "lan5";
				phy-handle = <&switch0phy3>;
			};

			port@5 {
				reg = <5>;
				label = "lan4";
				phy-handle = <&switch0phy4>;
			};

			port@6 {
				reg = <6>;
				label = "lan3";
				phy-handle = <&switch0phy5>;
			};

			port@7 {
				reg = <7>;
				label = "lan2";
				phy-handle = <&switch0phy6>;
			};

			port@8 {
				reg = <8>;
				label = "lan1";
				phy-handle = <&switch0phy7>;
			};

			port@10 {
				reg = <10>;
				label = "cpu";
				ethernet = <&eth1>;
			};

		};

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch0phy0: switch0phy0@1 {
				reg = <0x1>;
			};

			switch0phy1: switch0phy1@2 {
				reg = <0x2>;
			};

			switch0phy2: switch0phy2@3 {
				reg = <0x3>;
			};

			switch0phy3: switch0phy3@4 {
				reg = <0x4>;
			};

			switch0phy4: switch0phy4@5 {
				reg = <0x5>;
			};

			switch0phy5: switch0phy5@6 {
				reg = <0x6>;
			};

			switch0phy6: switch0phy6@7 {
				reg = <0x7>;
			};

			switch0phy7: switch0phy7@8 {
				reg = <0x8>;
			};
		};

	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

#include "armada-385-clearfog-gtr.dtsi"

/ {
	model = "SolidRun Clearfog GTR S4";
};

&sfp0 {
	tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
};

&mdio {
	switch0: switch0@4 {
		compatible = "marvell,mv88e6085";
		reg = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&cf_gtr_switch_reset_pins>;
		reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <1>;
				label = "lan2";
				phy-handle = <&switch0phy0>;
			};

			port@2 {
				reg = <2>;
				label = "lan1";
				phy-handle = <&switch0phy1>;
			};

			port@3 {
				reg = <3>;
				label = "lan4";
				phy-handle = <&switch0phy2>;
			};

			port@4 {
				reg = <4>;
				label = "lan3";
				phy-handle = <&switch0phy3>;
			};

			port@5 {
				reg = <5>;
				label = "cpu";
				ethernet = <&eth1>;
			};

		};

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch0phy0: switch0phy0@11 {
				reg = <0x11>;
			};

			switch0phy1: switch0phy1@12 {
				reg = <0x12>;
			};

			switch0phy2: switch0phy2@13 {
				reg = <0x13>;
			};

			switch0phy3: switch0phy3@14 {
				reg = <0x14>;
			};
		};

	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for Clearfog GTR machines rev 1.0 (88F6825)
 *
 *  Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
 */

/*
	SERDES mapping -
	0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
	1. 6141 switch (2.5Gbps capable)
	2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
	3. USB 3.0 Host
	4. mini PCIe CON2 - PCIe2
	5. SFP connector, or optionally SGMII Ethernet 1512 PHY

	USB 2.0 mapping -
	0. USB 2.0 - 0 USB pins header CON12
	1. USB 2.0 - 1 mini PCIe CON2
	2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)

	Pin mapping -
	0,1 - console UART
	2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
	      front panel and PSE controller
	4,5 - MDC/MDIO
	6..17 - RGMII
	18 - Topaz switch reset (active low)
	19 - 1512 phy reset
	20 - 1512 phy reset (eth2, optional)
	21,28,37,38,39,40 - SD0
	22 - USB 3.0 current limiter enable (active high)
	24 - SFP TX fault (input active high)
	25 - SFP present (input active low)
	26,27 - I2C1 - connected to SFP
	29 - Fan PWM
	30 - CON4 mini PCIe wifi disable
	31 - CON3 mini PCIe wifi disable
	32 - Fuse programming power toggle (1.8v)
	33 - CON4 mini PCIe reset
	34 - CON2 mini PCIe wifi disable
	35 - CON3 mini PCIe reset
	36 - Rear button (GPIO active low)
	41 - CON1 front panel connector
	42 - Front LED1, or front panel CON1
	43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
	44 - CON2 mini PCIe reset
	45 - TPM PIRQ signal, or front panel CON1
	46 - SFP TX disable
	47 - Control isolation of boot sensitive SAR signals
	48 - PSE reset
	49 - PSE OSS signal
	50 - PSE interrupt
	52 - Front LED2, or front panel
	53 - Front button
	54 - SFP LOS (input active high)
	55 - Fan sense
	56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
	59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
*/

/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "armada-385.dtsi"

/ {
	compatible = "marvell,armada385", "marvell,armada380";

	aliases {
		/* So that mvebu u-boot can update the MAC addresses */
		ethernet1 = &eth0;
		ethernet2 = &eth1;
		ethernet3 = &eth2;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>; /* 256 MB */
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_5p0v: regulator-5p0v {
		compatible = "regulator-fixed";
		regulator-name = "5P0V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
	};

	v_usb3_con: regulator-v-usb3-con {
		compatible = "regulator-fixed";
		gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "v_usb3_con";
		vin-supply = <&reg_5p0v>;
		regulator-boot-on;
		regulator-always-on;
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;

		internal-regs {

			rtc@a3800 {
				status = "okay";
			};

			i2c@11000 { /* ROM, temp sensor and front panel */
				pinctrl-0 = <&i2c0_pins>;
				pinctrl-names = "default";
				status = "okay";
			};

			i2c@11100 { /* SFP (CON5/CON6) */
				pinctrl-0 = <&cf_gtr_i2c1_pins>;
				pinctrl-names = "default";
				status = "okay";
			};

			pinctrl@18000 {
				cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
					marvell,pins = "mpp18";
					marvell,function = "gpio";
				};

				cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
					marvell,pins = "mpp22";
					marvell,function = "gpio";
				};

				cf_gtr_fan_pwm: cf-gtr-fan-pwm {
					marvell,pins = "mpp23";
					marvell,function = "gpio";
				};

				cf_gtr_i2c1_pins: i2c1-pins {
					/* SFP */
					marvell,pins = "mpp26", "mpp27";
					marvell,function = "i2c1";
				};

				cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
					marvell,pins = "mpp21", "mpp28",
						       "mpp37", "mpp38",
						       "mpp39", "mpp40";
					marvell,function = "sd0";
				};

				cf_gtr_isolation_pins: cf-gtr-isolation-pins {
					marvell,pins = "mpp47";
					marvell,function = "gpio";
				};

				cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
					marvell,pins = "mpp48";
					marvell,function = "gpio";
				};

				cf_gtr_spi1_cs_pins: spi1-cs-pins {
					marvell,pins = "mpp59";
					marvell,function = "spi1";
				};

				cf_gtr_front_button_pins: cf-gtr-front-button-pins {
					marvell,pins = "mpp53";
					marvell,function = "gpio";
				};

				cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
					marvell,pins = "mpp36";
					marvell,function = "gpio";
				};
			};

			sdhci@d8000 {
				bus-width = <4>;
				no-1-8-v;
				non-removable;
				pinctrl-0 = <&cf_gtr_sdhci_pins>;
				pinctrl-names = "default";
				status = "okay";
				vmmc = <&reg_3p3v>;
				wp-inverted;
			};

			usb@58000 {
				status = "okay";
			};

			usb3@f0000 {
				status = "okay";
			};

			usb3@f8000 {
				vbus-supply = <&v_usb3_con>;
				status = "okay";
			};
		};

		pcie {
			status = "okay";
			/*
			 * The PCIe units are accessible through
			 * the mini-PCIe connectors on the board.
			 */
			pcie@1,0 {
				reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
				status = "okay";
			};

			pcie@2,0 {
				reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
				status = "okay";
			};

			pcie@3,0 {
				reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
				status = "okay";
			};
		};
	};

	sfp0: sfp {
		compatible = "sff,sfp";
		i2c-bus = <&i2c1>;
		los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
		tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
		pinctrl-names = "default";

		button-0 {
			label = "Rear Button";
			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
			linux,can-disable;
			linux,code = <BTN_0>;
		};

		button-1 {
			label = "Front Button";
			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
			linux,can-disable;
			linux,code = <BTN_1>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		led1 {
			function = LED_FUNCTION_CPU;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
		};

		led2 {
			function = LED_FUNCTION_HEARTBEAT;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
		};
	};
};

&bm {
	status = "okay";
};

&bm_bppi {
	status = "okay";
};

&eth0 {
	/* ethernet@70000 */
	pinctrl-0 = <&ge0_rgmii_pins>;
	pinctrl-names = "default";
	phy = <&phy_dedicated>;
	phy-mode = "rgmii-id";
	buffer-manager = <&bm>;
	bm,pool-long = <0>;
	bm,pool-short = <1>;
	status = "okay";
};

&eth1 {
	/* ethernet@30000 */
	bm,pool-long = <2>;
	bm,pool-short = <1>;
	buffer-manager = <&bm>;
	phys = <&comphy1 1>;
	phy-mode = "2500base-x";
	status = "okay";

	fixed-link {
		speed = <2500>;
		full-duplex;
	};
};

&eth2 {
	/* ethernet@34000 */
	bm,pool-long = <3>;
	bm,pool-short = <1>;
	buffer-manager = <&bm>;
	managed = "in-band-status";
	phys = <&comphy5 1>;
	phy-mode = "sgmii";
	sfp = <&sfp0>;
	status = "okay";
};

&mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	status = "okay";

	phy_dedicated: ethernet-phy@0 {
		/*
		 * Annoyingly, the marvell phy driver configures the LED
		 * register, rather than preserving reset-loaded setting.
		 * We undo that rubbish here.
		 */
		marvell,reg-init = <3 16 0 0x1017>;
		reg = <0>;
	};
};

&uart0 {
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&spi1 {
	/*
	 * CS0: W25Q32 flash
	 */
	pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
	pinctrl-names = "default";
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "w25q32", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <3000000>;
		status = "okay";
	};
};

&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";
	status = "okay";

	/* U26 temperature sensor placed near SoC */
	temp1: nct75@4c {
		compatible = "lm75";
		reg = <0x4c>;
	};

	/* U27 temperature sensor placed near RTC battery */
	temp2: nct75@4d {
		compatible = "lm75";
		reg = <0x4d>;
	};

	/* 2Kb eeprom */
	eeprom@53 {
		compatible = "atmel,24c02";
		reg = <0x53>;
	};
};

&ahci0 {
	status = "okay";
};

&ahci1 {
	status = "okay";
};

&gpio0 {
	pinctrl-0 = <&cf_gtr_fan_pwm>;
	pinctrl-names = "default";

	wifi-disable {
		gpio-hog;
		gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>;
		output-low;
		line-name = "wifi-disable";
	};
};

&gpio1 {
	pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
	pinctrl-names = "default";

	lte-disable {
		gpio-hog;
		gpios = <2 GPIO_ACTIVE_LOW>;
		output-low;
		line-name = "lte-disable";
	};

	/*
	 * This signal, when asserted, isolates Armada 38x sample at reset pins
	 * from control of external devices. Should be de-asserted after reset.
	 */
	sar-isolation {
		gpio-hog;
		gpios = <15 GPIO_ACTIVE_LOW>;
		output-low;
		line-name = "sar-isolation";
	};

	poe-reset {
		gpio-hog;
		gpios = <16 GPIO_ACTIVE_LOW>;
		output-low;
		line-name = "poe-reset";
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for Marvell Armada 385 AMC board
 * (DB-88F6820-AMC)
 *
 * Copyright (C) 2017 Allied Telesis Labs
 */

/dts-v1/;
#include "armada-385.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Marvell Armada 385 AMC";
	compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		ethernet0 = &eth0;
		ethernet1 = &eth1;
		spi1 = &spi1;
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x80000000>; /* 2GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "okay";
};

&uart0 {
	/*
	 * Exported on the micro USB connector CON3
	 * through an FTDI
	 */

	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&eth0 {
	pinctrl-names = "default";
	/*
	 * The Reference Clock 0 is used to provide a
	 * clock to the PHY
	 */
	pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
	status = "okay";
	phy = <&phy0>;
	phy-mode = "rgmii-id";
};

&eth2 {
	status = "okay";
	phy = <&phy1>;
	phy-mode = "sgmii";
};

&usb0 {
	status = "okay";
};

&mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;

	phy0: ethernet-phy@1 {
		reg = <1>;
	};

	phy1: ethernet-phy@0 {
		reg = <0>;
	};
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		nand-on-flash-bbt;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			partition@0 {
				reg = <0x00000000 0x40000000>;
				label = "user";
			};
		};
	};
};

&pciec {
	status = "okay";
};

&pcie1 {
	/* Port 0, Lane 0 */
	status = "okay";
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <50000000>;
		m25p,fast-read;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			partition@0 {
				reg = <0x00000000 0x00100000>;
				label = "u-boot";
			};
			partition@100000 {
				reg = <0x00100000 0x00040000>;
				label = "u-boot-env";
			};
		};
	};
};

&refclk {
	clock-frequency = <20000000>;
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for Marvell Armada 385 Access Point Development board
 * (DB-88F6820-AP)
 *
 *  Copyright (C) 2014 Marvell
 *
 * Nadav Haklai <nadavh@marvell.com>
 */

/dts-v1/;
#include "armada-385.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Marvell Armada 385 Access Point Development Board";
	compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";

	chosen {
		stdout-path = "serial1:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x80000000>; /* 2GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;

		internal-regs {
			i2c0: i2c@11000 {
				pinctrl-names = "default";
				pinctrl-0 = <&i2c0_pins>;
				status = "okay";

				/*
				 * This bus is wired to two EEPROM
				 * sockets, one of which holding the
				 * board ID used by the	bootloader.
				 * Erasing this EEPROM's content will
				 * brick the board.
				 * Use this bus with caution.
				 */
			};

			mdio@72004 {
				pinctrl-names = "default";
				pinctrl-0 = <&mdio_pins>;

				phy0: ethernet-phy@1 {
					reg = <1>;
				};

				phy1: ethernet-phy@4 {
					reg = <4>;
				};

				phy2: ethernet-phy@6 {
					reg = <6>;
				};
			};

			/* UART0 is exposed through the JP8 connector */
			uart0: serial@12000 {
				pinctrl-names = "default";
				pinctrl-0 = <&uart0_pins>;
				status = "okay";
			};

			/*
			 * UART1 is exposed through a FTDI chip
			 * wired to the mini-USB connector
			 */
			uart1: serial@12100 {
				pinctrl-names = "default";
				pinctrl-0 = <&uart1_pins>;
				status = "okay";
			};

			pinctrl@18000 {
				xhci0_vbus_pins: xhci0-vbus-pins {
					marvell,pins = "mpp44";
					marvell,function = "gpio";
				};
			};

			/* CON3 */
			ethernet@30000 {
				status = "okay";
				phy = <&phy2>;
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <1>;
				bm,pool-short = <3>;
			};

			/* CON2 */
			ethernet@34000 {
				status = "okay";
				phy = <&phy1>;
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <2>;
				bm,pool-short = <3>;
			};

			usb@58000 {
				status = "okay";
			};

			/* CON4 */
			ethernet@70000 {
				pinctrl-names = "default";

				/*
				 * The Reference Clock 0 is used to
				 * provide a clock to the PHY
				 */
				pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
				buffer-manager = <&bm>;
				bm,pool-long = <0>;
				bm,pool-short = <3>;
			};

			bm@c8000 {
				status = "okay";
			};

			usb3@f0000 {
				status = "okay";
				usb-phy = <&usb3_phy>;
			};
		};

		bm-bppi {
			status = "okay";
		};

		pcie {
			status = "okay";

			/*
			 * The three PCIe units are accessible through
			 * standard mini-PCIe slots on the board.
			 */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};

			pcie@2,0 {
				/* Port 1, Lane 0 */
				status = "okay";
			};

			pcie@3,0 {
				/* Port 2, Lane 0 */
				status = "okay";
			};
		};
	};

	usb3_phy: usb3_phy {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&reg_xhci0_vbus>;
		#phy-cells = <0>;
	};

	reg_xhci0_vbus: xhci0-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&xhci0_vbus_pins>;
		regulator-name = "xhci0-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	};
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p128", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <54000000>;
	};
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0x00000000 0x00800000>;
				read-only;
			};

			partition@800000 {
				label = "uImage";
				reg = <0x00800000 0x00400000>;
				read-only;
			};

			partition@c00000 {
				label = "Root";
				reg = <0x00c00000 0x3f400000>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree include for the Linksys WRT1200AC (Caiman)
 *
 * Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
 */

/dts-v1/;
#include "armada-385-linksys.dtsi"

/ {
	model = "Linksys WRT1200AC";
	compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385",
		     "marvell,armada380";
};

&expander0 {
	wan_amber@0 {
		label = "caiman:amber:wan";
		reg = <0x0>;
	};

	wan_white@1 {
		label = "caiman:white:wan";
		reg = <0x1>;
	};

	wlan_2g@2 {
		label = "caiman:white:wlan_2g";
		reg = <0x2>;
	};

	wlan_5g@3 {
		label = "caiman:white:wlan_5g";
		reg = <0x3>;
	};

	usb2@5 {
		label = "caiman:white:usb2";
		reg = <0x5>;
	};

	usb3_1@6 {
		label = "caiman:white:usb3_1";
		reg = <0x6>;
	};

	usb3_2@7 {
		label = "caiman:white:usb3_2";
		reg = <0x7>;
	};

	wps_white@8 {
		label = "caiman:white:wps";
		reg = <0x8>;
	};

	wps_amber@9 {
		label = "caiman:amber:wps";
		reg = <0x9>;
	};
};

&gpio_leds {
	led-power {
		label = "caiman:white:power";
	};

	led-sata {
		label = "caiman:white:sata";
	};
};

&nand {
	/* 128MiB */
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "u-boot";
			reg = <0x0000000 0x200000>;  /* 2MiB */
			read-only;
		};

		partition@100000 {
			label = "u_env";
			reg = <0x200000 0x40000>;    /* 256KiB */
		};

		partition@140000 {
			label = "s_env";
			reg = <0x240000 0x40000>;    /* 256KiB */
		};

		partition@900000 {
			label = "devinfo";
			reg = <0x900000 0x100000>;   /* 1MiB */
			read-only;
		};

		/* kernel1 overlaps with rootfs1 by design */
		partition@a00000 {
			label = "kernel1";
			reg = <0xa00000 0x2800000>;  /* 40MiB */
		};

		partition@1000000 {
			label = "rootfs1";
			reg = <0x1000000 0x2200000>;  /* 34MiB */
		};

		/* kernel2 overlaps with rootfs2 by design */
		partition@3200000 {
			label = "kernel2";
			reg = <0x3200000 0x2800000>; /* 40MiB */
		};

		partition@3800000 {
			label = "rootfs2";
			reg = <0x3800000 0x2200000>; /* 34MiB */
		};

		/*
		 * 38MiB, last MiB is for the BBT, not writable
		 */
		partition@5a00000 {
			label = "syscfg";
			reg = <0x5a00000 0x2600000>;
		};

		/*
		 * Unused area between "s_env" and "devinfo".
		 * Moved here because otherwise the renumbered
		 * partitions would break the bootloader
		 * supplied bootargs
		 */
		partition@180000 {
			label = "unused_area";
			reg = <0x280000 0x680000>;   /* 6.5MiB */
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for the Linksys WRT1900ACv2 (Cobra)
 *
 * Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
 */

/dts-v1/;
#include "armada-385-linksys.dtsi"

/ {
	model = "Linksys WRT1900ACv2";
	compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385",
		     "marvell,armada380";
};

&expander0 {
	wan_amber@0 {
		label = "cobra:amber:wan";
		reg = <0x0>;
	};

	wan_white@1 {
		label = "cobra:white:wan";
		reg = <0x1>;
	};

	wlan_2g@2 {
		label = "cobra:white:wlan_2g";
		reg = <0x2>;
	};

	wlan_5g@3 {
		label = "cobra:white:wlan_5g";
		reg = <0x3>;
	};

	usb2@5 {
		label = "cobra:white:usb2";
		reg = <0x5>;
	};

	usb3_1@6 {
		label = "cobra:white:usb3_1";
		reg = <0x6>;
	};

	usb3_2@7 {
		label = "cobra:white:usb3_2";
		reg = <0x7>;
	};

	wps_white@8 {
		label = "cobra:white:wps";
		reg = <0x8>;
	};

	wps_amber@9 {
		label = "cobra:amber:wps";
		reg = <0x9>;
	};
};

&gpio_leds {
	led-power {
		label = "cobra:white:power";
	};

	led-sata {
		label = "cobra:white:sata";
	};
};

&nand {
	/* 128MiB */
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "u-boot";
			reg = <0x0000000 0x200000>;  /* 2MiB */
			read-only;
		};

		partition@100000 {
			label = "u_env";
			reg = <0x200000 0x40000>;    /* 256KiB */
		};

		partition@140000 {
			label = "s_env";
			reg = <0x240000 0x40000>;    /* 256KiB */
		};

		partition@900000 {
			label = "devinfo";
			reg = <0x900000 0x100000>;   /* 1MiB */
			read-only;
		};

		/* kernel1 overlaps with rootfs1 by design */
		partition@a00000 {
			label = "kernel1";
			reg = <0xa00000 0x2800000>;  /* 40MiB */
		};

		partition@1000000 {
			label = "rootfs1";
			reg = <0x1000000 0x2200000>;  /* 34MiB */
		};

		/* kernel2 overlaps with rootfs2 by design */
		partition@3200000 {
			label = "kernel2";
			reg = <0x3200000 0x2800000>; /* 40MiB */
		};

		partition@3800000 {
			label = "rootfs2";
			reg = <0x3800000 0x2200000>; /* 34MiB */
		};

		/*
		 * 38MiB, last MiB is for the BBT, not writable
		 */
		partition@5a00000 {
			label = "syscfg";
			reg = <0x5a00000 0x2600000>;
		};

		/*
		 * Unused area between "s_env" and "devinfo".
		 * Moved here because otherwise the renumbered
		 * partitions would break the bootloader
		 * supplied bootargs
		 */
		partition@180000 {
			label = "unused_area";
			reg = <0x280000 0x680000>;   /* 6.5MiB */
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for the Linksys WRT3200ACM (Rango)
 *
 * Copyright (C) 2016 Imre Kaloz <kaloz@openwrt.org>
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-385-linksys.dtsi"

/ {
	model = "Linksys WRT3200ACM";
	compatible = "linksys,rango", "linksys,armada385", "marvell,armada385",
		     "marvell,armada380";
};

&expander0 {
	wan_amber@0 {
		label = "rango:amber:wan";
		reg = <0x0>;
	};

	wan_white@1 {
		label = "rango:white:wan";
		reg = <0x1>;
	};

	usb2@5 {
		label = "rango:white:usb2";
		reg = <0x5>;
	};

	usb3_1@6 {
		label = "rango:white:usb3_1";
		reg = <0x6>;
	};

	usb3_2@7 {
		label = "rango:white:usb3_2";
		reg = <0x7>;
	};

	wps_white@8 {
		label = "rango:white:wps";
		reg = <0x8>;
	};

	wps_amber@9 {
		label = "rango:amber:wps";
		reg = <0x9>;
	};
};

&gpio_leds {
	led-power {
		gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
		label = "rango:white:power";
	};

	led-sata {
		gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
		label = "rango:white:sata";
	};

	led-wlan_2g {
		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
		label = "rango:white:wlan_2g";
	};

	led-wlan_5g {
		gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
		label = "rango:white:wlan_5g";
	};
};

&gpio_leds_pins {
	marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56";
};

&nand {
	/* AMD/Spansion S34ML02G2 256MiB, OEM Layout */
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "u-boot";
			reg = <0x0000000 0x200000>;  /* 2MiB */
			read-only;
		};

		partition@200000 {
			label = "u_env";
			reg = <0x200000 0x20000>;    /* 128KiB */
		};

		partition@220000 {
			label = "s_env";
			reg = <0x220000 0x40000>;    /* 256KiB */
		};

		partition@7e0000 {
			label = "devinfo";
			reg = <0x7e0000 0x40000>;   /* 256KiB */
			read-only;
		};

		partition@820000 {
			label = "sysdiag";
			reg = <0x820000 0x1e0000>;   /* 1920KiB */
			read-only;
		};

		/* kernel1 overlaps with rootfs1 by design */
		partition@a00000 {
			label = "kernel1";
			reg = <0xa00000 0x5000000>;  /* 80MiB */
		};

		partition@1000000 {
			label = "rootfs1";
			reg = <0x1000000 0x4a00000>;  /* 74MiB */
		};

		/* kernel2 overlaps with rootfs2 by design */
		partition@5a00000 {
			label = "kernel2";
			reg = <0x5a00000 0x5000000>; /* 80MiB */
		};

		partition@6000000 {
			label = "rootfs2";
			reg = <0x6000000 0x4a00000>; /* 74MiB */
		};

		/*
		 * 86MiB, last MiB is for the BBT, not writable
		 */
		partition@aa00000 {
			label = "syscfg";
			reg = <0xaa00000 0x5600000>;
		};

		/*
		 * Unused area between "s_env" and "devinfo".
		 * Moved here because otherwise the renumbered
		 * partitions would break the bootloader
		 * supplied bootargs
		 */
		partition@180000 {
			label = "unused_area";
			reg = <0x260000 0x5c0000>;   /* 5.75MiB */
		};
	};
};

&sdhci {
	pinctrl-names = "default";
	pinctrl-0 = <&sdhci_pins>;
	no-1-8-v;
	non-removable;
	wp-inverted;
	bus-width = <8>;
	status = "okay";
};

&usb3_1_vbus {
	gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};

&usb3_1_vbus_pins {
	marvell,pins = "mpp44";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for the Linksys WRT1900ACS (Shelby)
 *
 * Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
 */

/dts-v1/;
#include "armada-385-linksys.dtsi"

/ {
	model = "Linksys WRT1900ACS";
	compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385",
		     "marvell,armada380";
};

&expander0 {
	wan_amber@0 {
		label = "shelby:amber:wan";
		reg = <0x0>;
	};

	wan_white@1 {
		label = "shelby:white:wan";
		reg = <0x1>;
	};

	wlan_2g@2 {
		label = "shelby:white:wlan_2g";
		reg = <0x2>;
	};

	wlan_5g@3 {
		label = "shelby:white:wlan_5g";
		reg = <0x3>;
	};

	usb2@5 {
		label = "shelby:white:usb2";
		reg = <0x5>;
	};

	usb3_1@6 {
		label = "shelby:white:usb3_1";
		reg = <0x6>;
	};

	usb3_2@7 {
		label = "shelby:white:usb3_2";
		reg = <0x7>;
	};

	wps_white@8 {
		label = "shelby:white:wps";
		reg = <0x8>;
	};

	wps_amber@9 {
		label = "shelby:amber:wps";
		reg = <0x9>;
	};
};

&gpio_leds {
	led-power {
		label = "shelby:white:power";
	};

	led-sata {
		label = "shelby:white:sata";
	};
};

&nand {
	/* 128MiB */
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "u-boot";
			reg = <0x0000000 0x200000>;  /* 2MiB */
			read-only;
		};

		partition@100000 {
			label = "u_env";
			reg = <0x200000 0x40000>;    /* 256KiB */
		};

		partition@140000 {
			label = "s_env";
			reg = <0x240000 0x40000>;    /* 256KiB */
		};

		partition@900000 {
			label = "devinfo";
			reg = <0x900000 0x100000>;   /* 1MiB */
			read-only;
		};

		/* kernel1 overlaps with rootfs1 by design */
		partition@a00000 {
			label = "kernel1";
			reg = <0xa00000 0x2800000>;  /* 40MiB */
		};

		partition@1000000 {
			label = "rootfs1";
			reg = <0x1000000 0x2200000>;  /* 34MiB */
		};

		/* kernel2 overlaps with rootfs2 by design */
		partition@3200000 {
			label = "kernel2";
			reg = <0x3200000 0x2800000>; /* 40MiB */
		};

		partition@3800000 {
			label = "rootfs2";
			reg = <0x3800000 0x2200000>; /* 34MiB */
		};

		/*
		 * 38MiB, last MiB is for the BBT, not writable
		 */
		partition@5a00000 {
			label = "syscfg";
			reg = <0x5a00000 0x2600000>;
		};

		/*
		 * Unused area between "s_env" and "devinfo".
		 * Moved here because otherwise the renumbered
		 * partitions would break the bootloader
		 * supplied bootargs
		 */
		partition@180000 {
			label = "unused_area";
			reg = <0x280000 0x680000>;   /* 6.5MiB */
		};
	};
};