code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Binding for simple fixed factor rate clock sources

maintainers:
  - Michael Turquette <mturquette@baylibre.com>
  - Stephen Boyd <sboyd@kernel.org>

properties:
  compatible:
    enum:
      - fixed-factor-clock

  "#clock-cells":
    const: 0

  clocks:
    maxItems: 1

  clock-div:
    description: Fixed divider
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1

  clock-mult:
    description: Fixed multiplier
    $ref: /schemas/types.yaml#/definitions/uint32

  clock-output-names:
    maxItems: 1

required:
  - compatible
  - clocks
  - "#clock-cells"
  - clock-div
  - clock-mult

additionalProperties: false

examples:
  - |
    clock {
      compatible = "fixed-factor-clock";
      clocks = <&parentclk>;
      #clock-cells = <0>;
      clock-div = <2>;
      clock-mult = <1>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Binding for simple memory mapped IO fixed-rate clock sources

description:
  This binding describes a fixed-rate clock for which the frequency can
  be read from a single 32-bit memory mapped I/O register.

  It was designed for test systems, like FPGA, not for complete,
  finished SoCs.

maintainers:
  - Jan Kotas <jank@cadence.com>

properties:
  compatible:
    const: fixed-mmio-clock

  reg:
    maxItems: 1

  "#clock-cells":
    const: 0

  clock-output-names:
    maxItems: 1

required:
  - compatible
  - reg
  - "#clock-cells"

additionalProperties: false

examples:
  - |
    sysclock: sysclock@fd020004 {
      compatible = "fixed-mmio-clock";
      #clock-cells = <0>;
      reg = <0xfd020004 0x4>;
      clock-output-names = "sysclk";
    };
...

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,flexspi-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale FlexSPI clock driver for Layerscape SoCs

maintainers:
  - Michael Walle <michael@walle.cc>

description:
  The Freescale Layerscape SoCs have a special FlexSPI clock which is
  derived from the platform PLL.

properties:
  compatible:
    enum:
      - fsl,ls1028a-flexspi-clk
      - fsl,lx2160a-flexspi-clk

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  '#clock-cells':
    const: 0

  clock-output-names:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    dcfg {
        #address-cells = <1>;
        #size-cells = <1>;

        fspi_clk: clock-controller@900 {
            compatible = "fsl,ls1028a-flexspi-clk";
            reg = <0x900 0x4>;
            #clock-cells = <0>;
            clocks = <&parentclk>;
            clock-output-names = "fspi_clk";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,imx8m-anatop.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8M Family Anatop Module

maintainers:
  - Peng Fan <peng.fan@nxp.com>

description: |
  NXP i.MX8M Family anatop PLL module which generates PLL to CCM root.

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx8mm-anatop
          - fsl,imx8mq-anatop
      - items:
          - enum:
              - fsl,imx8mn-anatop
              - fsl,imx8mp-anatop
          - const: fsl,imx8mm-anatop

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    anatop: clock-controller@30360000 {
        compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
        reg = <0x30360000 0x10000>;
        #clock-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding

maintainers:
  - Wen He <wen.he_1@nxp.com>

description: |
  NXP LS1028A has a clock domain PXLCLK0 used for the Display output
  interface in the display core, as implemented in TSMC CLN28HPM PLL.
  which generate and offers pixel clocks to Display.

properties:
  compatible:
    const: fsl,ls1028a-plldig

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  '#clock-cells':
    const: 0

  fsl,vco-hz:
    description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
      of this PLL cannot be changed during runtime only at startup. Therefore,
      the output frequencies are very limited and might not even closely match
      the requested frequency. To work around this restriction the user may specify
      its own desired VCO frequency for the PLL.
    minimum: 650000000
    maximum: 1300000000
    default: 1188000000

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  # Display PIXEL Clock node:
  - |
    dpclk: clock-display@f1f0000 {
        compatible = "fsl,ls1028a-plldig";
        reg = <0xf1f0000 0xffff>;
        #clock-cells = <0>;
        clocks = <&osc_27m>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale SAI bitclock-as-a-clock binding

maintainers:
  - Michael Walle <michael@walle.cc>

description: |
  It is possible to use the BCLK pin of a SAI module as a generic clock
  output. Some SoC are very constrained in their pin multiplexer
  configuration. Eg. pins can only be changed groups. For example, on the
  LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
  the second pins are wasted. Using this binding it is possible to use the
  clock of the second SAI as a MCLK clock for an audio codec, for example.

  This is a composite of a gated clock and a divider clock.

properties:
  compatible:
    const: fsl,vf610-sai-clock

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  '#clock-cells':
    const: 0

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        mclk: clock-mclk@f130080 {
            compatible = "fsl,vf610-sai-clock";
            reg = <0x0 0xf130080 0x0 0x80>;
            #clock-cells = <0>;
            clocks = <&parentclk>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX SCU Client Device Node - Clock bindings based on SCU Message Protocol

maintainers:
  - Abel Vesa <abel.vesa@nxp.com>

description: i.MX SCU Client Device Node
  Client nodes are maintained as children of the relevant IMX-SCU device node.
  This binding uses the common clock binding.
  (Documentation/devicetree/bindings/clock/clock-bindings.txt)
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. See the full list of clock IDs from
  include/dt-bindings/clock/imx8qxp-clock.h

properties:
  compatible:
    items:
      - enum:
          - fsl,imx8dxl-clk
          - fsl,imx8qm-clk
          - fsl,imx8qxp-clk
      - const: fsl,scu-clk

  '#clock-cells':
    const: 2

required:
  - compatible
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller {
        compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
        #clock-cells = <2>;
    };


code:
Fujitsu CRG11 clock driver bindings
-----------------------------------

Required properties :
- compatible : Shall contain "fujitsu,mb86s70-crg11"
- #clock-cells : Shall be 3 {cntrlr domain port}

The consumer specifies the desired clock pointing to its phandle.

Example:

	clock: crg11 {
		compatible = "fujitsu,mb86s70-crg11";
		#clock-cells = <3>;
	};

	mhu: mhu0@2b1f0000 {
		#mbox-cells = <1>;
		compatible = "arm,mhu";
		reg = <0 0x2B1F0000 0x1000>;
		interrupts = <0 36 4>, /* LP Non-Sec */
			     <0 35 4>, /* HP Non-Sec */
			     <0 37 4>; /* Secure */
		clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
		clock-names = "clk";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/gpio-gate-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Simple GPIO clock gate

maintainers:
  - Jyri Sarha <jsarha@ti.com>

properties:
  compatible:
    const: gpio-gate-clock

  clocks:
    maxItems: 1

  '#clock-cells':
    const: 0

  enable-gpios:
    description: GPIO reference for enabling and disabling the clock.
    maxItems: 1

required:
  - compatible
  - '#clock-cells'
  - enable-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    clock {
        compatible = "gpio-gate-clock";
        clocks = <&parentclk>;
        #clock-cells = <0>;
        enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/gpio-mux-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Simple GPIO clock multiplexer

maintainers:
  - Sergej Sawazki <ce3a@gmx.de>

properties:
  compatible:
    const: gpio-mux-clock

  clocks:
    items:
      - description: First parent clock
      - description: Second parent clock

  '#clock-cells':
    const: 0

  select-gpios:
    description: GPIO reference for selecting the parent clock.
    maxItems: 1

required:
  - compatible
  - clocks
  - '#clock-cells'
  - select-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    clock {
            compatible = "gpio-mux-clock";
            clocks = <&parentclk1>, <&parentclk2>;
            #clock-cells = <0>;
            select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
    };


code:
* Hisilicon Hi3620 Clock Controller

The Hi3620 clock controller generates and supplies clock to various
controllers within the Hi3620 SoC.

Required Properties:

- compatible: should be one of the following.
  - "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
  - "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.

- reg: physical base address of the controller and length of memory mapped
  region.

- #clock-cells: should be 1.

Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.

All these identifier could be found in <dt-bindings/clock/hi3620-clock.h>.


code:
* Hisilicon Hi3660 Clock Controller

The Hi3660 clock controller generates and supplies clock to various
controllers within the Hi3660 SoC.

Required Properties:

- compatible: the compatible should be one of the following strings to
	indicate the clock controller functionality.

	- "hisilicon,hi3660-crgctrl"
	- "hisilicon,hi3660-pctrl"
	- "hisilicon,hi3660-pmuctrl"
	- "hisilicon,hi3660-sctrl"
	- "hisilicon,hi3660-iomcu"
	- "hisilicon,hi3660-stub-clk"

- reg: physical base address of the controller and length of memory mapped
  region.

- #clock-cells: should be 1.

Optional Properties:

- mboxes: Phandle to the mailbox for sending message to MCU.
            (See: ../mailbox/hisilicon,hi3660-mailbox.txt for more info)

Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.

All these identifier could be found in <dt-bindings/clock/hi3660-clock.h>.

Examples:
	crg_ctrl: clock-controller@fff35000 {
		compatible = "hisilicon,hi3660-crgctrl", "syscon";
		reg = <0x0 0xfff35000 0x0 0x1000>;
		#clock-cells = <1>;
	};

	uart0: serial@fdf02000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x0 0xfdf02000 0x0 0x1000>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
			 <&crg_ctrl HI3660_PCLK>;
		clock-names = "uartclk", "apb_pclk";
	};


code:
* Hisilicon Hi3670 Clock Controller

The Hi3670 clock controller generates and supplies clock to various
controllers within the Hi3670 SoC.

Required Properties:

- compatible: the compatible should be one of the following strings to
	indicate the clock controller functionality.

	- "hisilicon,hi3670-crgctrl"
	- "hisilicon,hi3670-pctrl"
	- "hisilicon,hi3670-pmuctrl"
	- "hisilicon,hi3670-sctrl"
	- "hisilicon,hi3670-iomcu"
	- "hisilicon,hi3670-media1-crg"
	- "hisilicon,hi3670-media2-crg"

- reg: physical base address of the controller and length of memory mapped
  region.

- #clock-cells: should be 1.

Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.

All these identifier could be found in <dt-bindings/clock/hi3670-clock.h>.

Examples:
	crg_ctrl: clock-controller@fff35000 {
		compatible = "hisilicon,hi3670-crgctrl", "syscon";
		reg = <0x0 0xfff35000 0x0 0x1000>;
		#clock-cells = <1>;
	};

	uart0: serial@fdf02000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x0 0xfdf02000 0x0 0x1000>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
			 <&crg_ctrl HI3670_PCLK>;
		clock-names = "uartclk", "apb_pclk";
	};


code:
* Hisilicon Hi6220 Clock Controller

Clock control registers reside in different Hi6220 system controllers,
please refer the following document to know more about the binding rules
for these system controllers:

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml

Required Properties:

- compatible: the compatible should be one of the following strings to
	indicate the clock controller functionality.

	- "hisilicon,hi6220-acpu-sctrl"
	- "hisilicon,hi6220-aoctrl"
	- "hisilicon,hi6220-sysctrl"
	- "hisilicon,hi6220-mediactrl"
	- "hisilicon,hi6220-pmctrl"
	- "hisilicon,hi6220-stub-clk"

- reg: physical base address of the controller and length of memory mapped
  region.

- #clock-cells: should be 1.

Optional Properties:

- hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram;
  the driver need use the sram to pass parameters for frequency change.

- mboxes: use the label reference for the mailbox as the first parameter, the
  second parameter is the channel number.

Example 1:
	sys_ctrl: sys_ctrl@f7030000 {
		compatible = "hisilicon,hi6220-sysctrl", "syscon";
		reg = <0x0 0xf7030000 0x0 0x2000>;
		#clock-cells = <1>;
	};

Example 2:
	stub_clock: stub_clock {
		compatible = "hisilicon,hi6220-stub-clk";
		hisilicon,hi6220-clk-sram = <&sram>;
		#clock-cells = <1>;
		mboxes = <&mailbox 1>;
	};

Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.

All these identifier could be found in <dt-bindings/clock/hi6220-clock.h>.


code:
* HiSilicon Clock and Reset Generator(CRG)

The CRG module provides clock and reset signals to various
modules within the SoC.

This binding uses the following bindings:
    Documentation/devicetree/bindings/clock/clock-bindings.txt
    Documentation/devicetree/bindings/reset/reset.txt

Required Properties:

- compatible: should be one of the following.
  - "hisilicon,hi3516cv300-crg"
  - "hisilicon,hi3516cv300-sysctrl"
  - "hisilicon,hi3519-crg"
  - "hisilicon,hi3798cv200-crg"
  - "hisilicon,hi3798cv200-sysctrl"

- reg: physical base address of the controller and length of memory mapped
  region.

- #clock-cells: should be 1.

Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.

All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.

- #reset-cells: should be 2.

A reset signal can be controlled by writing a bit register in the CRG module.
The reset specifier consists of two cells. The first cell represents the
register offset relative to the base address. The second cell represents the
bit index in the register.

Example: CRG nodes
CRG: clock-reset-controller@12010000 {
	compatible = "hisilicon,hi3519-crg";
	reg = <0x12010000 0x10000>;
	#clock-cells = <1>;
	#reset-cells = <2>;
};

Example: consumer nodes
i2c0: i2c@12110000 {
	compatible = "hisilicon,hi3519-i2c";
	reg = <0x12110000 0x1000>;
	clocks = <&CRG HI3519_I2C0_RST>;
	resets = <&CRG 0xe4 0>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Hisilicon SOC Clock for HI3559AV100

maintainers:
  - Dongjiu Geng <gengdongjiu@huawei.com>

description: |
  Hisilicon SOC clock control module which supports the clocks, resets and
  power domains on HI3559AV100.

  See also:
    dt-bindings/clock/hi3559av100-clock.h

properties:
  compatible:
    enum:
      - hisilicon,hi3559av100-clock
      - hisilicon,hi3559av100-shub-clock

  reg:
    minItems: 1
    maxItems: 2

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 2
    description: |
      First cell is reset request register offset.
      Second cell is bit offset in reset request register.

required:
  - compatible
  - reg
  - '#clock-cells'
  - '#reset-cells'

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        clock-controller@12010000 {
            compatible = "hisilicon,hi3559av100-clock";
            #clock-cells = <1>;
            #reset-cells = <2>;
            reg = <0x0 0x12010000 0x0 0x10000>;
        };
    };
...


code:
* Hisilicon Hix5hd2 Clock Controller

The hix5hd2 clock controller generates and supplies clock to various
controllers within the hix5hd2 SoC.

Required Properties:

- compatible: should be "hisilicon,hix5hd2-clock"
- reg: Address and length of the register set
- #clock-cells: Should be <1>

Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.

All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.

Examples:
	clock: clock@f8a22000 {
		compatible = "hisilicon,hix5hd2-clock";
		reg = <0xf8a22000 0x1000>;
		#clock-cells = <1>;
	};

	uart0: uart@f8b00000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0xf8b00000 0x1000>;
		interrupts = <0 49 4>;
		clocks = <&clock HIX5HD2_FIXED_83M>;
		clock-names = "apb_pclk";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators

description: |
  The IDT VersaClock 5 and VersaClock 6 are programmable I2C
  clock generators providing from 3 to 12 output clocks.

  When referencing the provided clock in the DT using phandle and clock
  specifier, the following mapping applies:

  - 5P49V5923:
    0 -- OUT0_SEL_I2CB
    1 -- OUT1
    2 -- OUT2

  - 5P49V5933:
    0 -- OUT0_SEL_I2CB
    1 -- OUT1
    2 -- OUT4

  - other parts:
    0 -- OUT0_SEL_I2CB
    1 -- OUT1
    2 -- OUT2
    3 -- OUT3
    4 -- OUT4

  The idt,shutdown and idt,output-enable-active properties control the
  SH (en_global_shutdown) and SP bits of the Primary Source and Shutdown
  Register, respectively. Their behavior is summarized by the following
  table:

  SH SP Output when the SD/OE pin is Low/High
  == == =====================================
   0  0 Active/Inactive
   0  1 Inactive/Active
   1  0 Active/Shutdown
   1  1 Inactive/Shutdown

  The case where SH and SP are both 1 is likely not very interesting.

maintainers:
  - Luca Ceresoli <luca.ceresoli@bootlin.com>

properties:
  compatible:
    enum:
      - idt,5p49v5923
      - idt,5p49v5925
      - idt,5p49v5933
      - idt,5p49v5935
      - idt,5p49v6901
      - idt,5p49v6965
      - idt,5p49v6975

  reg:
    description: I2C device address
    enum: [ 0x68, 0x6a ]

  '#clock-cells':
    const: 1

  clock-names:
    minItems: 1
    maxItems: 2
    items:
      enum: [ xin, clkin ]
  clocks:
    minItems: 1
    maxItems: 2

  idt,xtal-load-femtofarads:
    minimum: 9000
    maximum: 22760
    description: Optional load capacitor for XTAL1 and XTAL2

  idt,shutdown:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]
    description: |
      If 1, this enables the shutdown functionality: the chip will be
      shut down if the SD/OE pin is driven high. If 0, this disables the
      shutdown functionality: the chip will never be shut down based on
      the value of the SD/OE pin. This property corresponds to the SH
      bit of the Primary Source and Shutdown Register.

  idt,output-enable-active:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]
    description: |
      If 1, this enables output when the SD/OE pin is high, and disables
      output when the SD/OE pin is low. If 0, this disables output when
      the SD/OE pin is high, and enables output when the SD/OE pin is
      low. This corresponds to the SP bit of the Primary Source and
      Shutdown Register.

patternProperties:
  "^OUT[1-4]$":
    type: object
    description:
      Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
      Configuration" in the Versaclock 5/6/6E Family Register Description
      and Programming Guide.
    properties:
      idt,mode:
        description:
          The output drive mode. Values defined in dt-bindings/clock/versaclock.h
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 0
        maximum: 6
      idt,voltage-microvolt:
        description: The output drive voltage.
        enum: [ 1800000, 2500000, 3300000 ]
      idt,slew-percent:
        description: The Slew rate control for CMOS single-ended.
        enum: [ 80, 85, 90, 100 ]
    additionalProperties: false

required:
  - compatible
  - reg
  - '#clock-cells'
  - idt,shutdown
  - idt,output-enable-active

allOf:
  - if:
      properties:
        compatible:
          enum:
            - idt,5p49v5933
            - idt,5p49v5935
            - idt,5p49v6975
    then:
      # Devices with builtin crystal + optional external input
      properties:
        clock-names:
          const: clkin
        clocks:
          maxItems: 1
    else:
      # Devices without builtin crystal
      required:
        - clock-names
        - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/versaclock.h>

    /* 25MHz reference crystal */
    ref25: ref25m {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <25000000>;
    };

    i2c@0 {
        reg = <0x0 0x100>;
        #address-cells = <1>;
        #size-cells = <0>;

        /* IDT 5P49V5923 I2C clock generator */
        vc5: clock-generator@6a {
            compatible = "idt,5p49v5923";
            reg = <0x6a>;
            #clock-cells = <1>;

            /* Connect XIN input to 25MHz reference */
            clocks = <&ref25m>;
            clock-names = "xin";

            /* Set the SD/OE pin's settings */
            idt,shutdown = <0>;
            idt,output-enable-active = <0>;

            OUT1 {
                idt,mode = <VC5_CMOSD>;
                idt,voltage-microvolt = <1800000>;
                idt,slew-percent = <80>;
            };

            OUT4 {
                idt,mode = <VC5_LVDS>;
            };
        };
    };

...


code:
Binding for Imagination Technologies MIPS Boston clock sources.

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

The device node must be a child node of the syscon node corresponding to the
Boston system's platform registers.

Required properties:
- compatible : Should be "img,boston-clock".
- #clock-cells : Should be set to 1.
  Values available for clock consumers can be found in the header file:
    <dt-bindings/clock/boston-clock.h>

Example:

	system-controller@17ffd000 {
		compatible = "img,boston-platform-regs", "syscon";
		reg = <0x17ffd000 0x1000>;

		clk_boston: clock {
			compatible = "img,boston-clock";
			#clock-cells = <1>;
		};
	};

	uart0: uart@17ffe000 {
		/* ... */
		clocks = <&clk_boston BOSTON_CLK_SYS>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx1-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX1 CPUs

maintainers:
  - Alexander Shiyan <shc_work@mail.ru>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
  for the full list of i.MX1 clock IDs.

properties:
  compatible:
    const: fsl,imx1-ccm

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx1-clock.h>

    clock-controller@21b000 {
        #clock-cells = <1>;
        compatible = "fsl,imx1-ccm";
        reg = <0x0021b000 0x1000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx21-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX21

maintainers:
  - Alexander Shiyan <shc_work@mail.ru>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
  for the full list of i.MX21 clock IDs.

properties:
  compatible:
    const: fsl,imx21-ccm

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx21-clock.h>

    clock-controller@10027000 {
        compatible = "fsl,imx21-ccm";
        reg = <0x10027000 0x800>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx23-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX23

maintainers:
  - Shawn Guo <shawnguo@kernel.org>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. The following is a full list of i.MX23
  clocks and IDs.

        Clock		ID
        ------------------
        ref_xtal	0
        pll		1
        ref_cpu		2
        ref_emi		3
        ref_pix		4
        ref_io		5
        saif_sel	6
        lcdif_sel	7
        gpmi_sel	8
        ssp_sel		9
        emi_sel		10
        cpu		11
        etm_sel		12
        cpu_pll		13
        cpu_xtal	14
        hbus		15
        xbus		16
        lcdif_div	17
        ssp_div		18
        gpmi_div	19
        emi_pll		20
        emi_xtal	21
        etm_div		22
        saif_div	23
        clk32k_div	24
        rtc		25
        adc		26
        spdif_div	27
        clk32k		28
        dri		29
        pwm		30
        filt		31
        uart		32
        ssp		33
        gpmi		34
        spdif		35
        emi		36
        saif		37
        lcdif		38
        etm		39
        usb		40
        usb_phy		41

properties:
  compatible:
    const: fsl,imx23-clkctrl

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller@80040000 {
        compatible = "fsl,imx23-clkctrl";
        reg = <0x80040000 0x2000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx25-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX25

maintainers:
  - Sascha Hauer <s.hauer@pengutronix.de>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. The following is a full list of i.MX25
  clocks and IDs.

        Clock			ID
        --------------------------
        dummy			0
        osc			1
        mpll			2
        upll			3
        mpll_cpu_3_4		4
        cpu_sel			5
        cpu			6
        ahb			7
        usb_div			8
        ipg			9
        per0_sel		10
        per1_sel		11
        per2_sel		12
        per3_sel		13
        per4_sel		14
        per5_sel		15
        per6_sel		16
        per7_sel		17
        per8_sel		18
        per9_sel		19
        per10_sel		20
        per11_sel		21
        per12_sel		22
        per13_sel		23
        per14_sel		24
        per15_sel		25
        per0			26
        per1			27
        per2			28
        per3			29
        per4			30
        per5			31
        per6			32
        per7			33
        per8			34
        per9			35
        per10			36
        per11			37
        per12			38
        per13			39
        per14			40
        per15			41
        csi_ipg_per		42
        epit_ipg_per		43
        esai_ipg_per		44
        esdhc1_ipg_per		45
        esdhc2_ipg_per		46
        gpt_ipg_per		47
        i2c_ipg_per		48
        lcdc_ipg_per		49
        nfc_ipg_per		50
        owire_ipg_per		51
        pwm_ipg_per		52
        sim1_ipg_per		53
        sim2_ipg_per		54
        ssi1_ipg_per		55
        ssi2_ipg_per		56
        uart_ipg_per		57
        ata_ahb			58
        reserved		59
        csi_ahb			60
        emi_ahb			61
        esai_ahb		62
        esdhc1_ahb		63
        esdhc2_ahb		64
        fec_ahb			65
        lcdc_ahb		66
        rtic_ahb		67
        sdma_ahb		68
        slcdc_ahb		69
        usbotg_ahb		70
        reserved		71
        reserved		72
        reserved		73
        reserved		74
        can1_ipg		75
        can2_ipg		76
        csi_ipg			77
        cspi1_ipg		78
        cspi2_ipg		79
        cspi3_ipg		80
        dryice_ipg		81
        ect_ipg			82
        epit1_ipg		83
        epit2_ipg		84
        reserved		85
        esdhc1_ipg		86
        esdhc2_ipg		87
        fec_ipg			88
        reserved		89
        reserved		90
        reserved		91
        gpt1_ipg		92
        gpt2_ipg		93
        gpt3_ipg		94
        gpt4_ipg		95
        reserved		96
        reserved		97
        reserved		98
        iim_ipg			99
        reserved		100
        reserved		101
        kpp_ipg			102
        lcdc_ipg		103
        reserved		104
        pwm1_ipg		105
        pwm2_ipg		106
        pwm3_ipg		107
        pwm4_ipg		108
        rngb_ipg		109
        reserved		110
        scc_ipg			111
        sdma_ipg		112
        sim1_ipg		113
        sim2_ipg		114
        slcdc_ipg		115
        spba_ipg		116
        ssi1_ipg		117
        ssi2_ipg		118
        tsc_ipg			119
        uart1_ipg		120
        uart2_ipg		121
        uart3_ipg		122
        uart4_ipg		123
        uart5_ipg		124
        reserved		125
        wdt_ipg			126
        cko_div			127
        cko_sel			128
        cko			129

properties:
  compatible:
    const: fsl,imx25-ccm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller@53f80000 {
        compatible = "fsl,imx25-ccm";
        reg = <0x53f80000 0x4000>;
        interrupts = <31>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx27-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX27

maintainers:
  - Fabio Estevam <festevam@gmail.com>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
  for the full list of i.MX27 clock IDs.

properties:
  compatible:
    const: fsl,imx27-ccm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx27-clock.h>

    clock-controller@10027000 {
        compatible = "fsl,imx27-ccm";
        reg = <0x10027000 0x1000>;
        interrupts = <31>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx28-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX28

maintainers:
  - Shawn Guo <shawnguo@kernel.org>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. The following is a full list of i.MX28
  clocks and IDs.

        Clock		ID
        ------------------
        ref_xtal	0
        pll0		1
        pll1		2
        pll2		3
        ref_cpu		4
        ref_emi		5
        ref_io0		6
        ref_io1		7
        ref_pix		8
        ref_hsadc	9
        ref_gpmi	10
        saif0_sel	11
        saif1_sel	12
        gpmi_sel	13
        ssp0_sel	14
        ssp1_sel	15
        ssp2_sel	16
        ssp3_sel	17
        emi_sel		18
        etm_sel		19
        lcdif_sel	20
        cpu		21
        ptp_sel		22
        cpu_pll		23
        cpu_xtal	24
        hbus		25
        xbus		26
        ssp0_div	27
        ssp1_div	28
        ssp2_div	29
        ssp3_div	30
        gpmi_div	31
        emi_pll		32
        emi_xtal	33
        lcdif_div	34
        etm_div		35
        ptp		36
        saif0_div	37
        saif1_div	38
        clk32k_div	39
        rtc		40
        lradc		41
        spdif_div	42
        clk32k		43
        pwm		44
        uart		45
        ssp0		46
        ssp1		47
        ssp2		48
        ssp3		49
        gpmi		50
        spdif		51
        emi		52
        saif0		53
        saif1		54
        lcdif		55
        etm		56
        fec		57
        can0		58
        can1		59
        usb0		60
        usb1		61
        usb0_phy	62
        usb1_phy	63
        enet_out	64

properties:
  compatible:
    const: fsl,imx28-clkctrl

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller@80040000 {
        compatible = "fsl,imx28-clkctrl";
        reg = <0x80040000 0x2000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx31-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX31

maintainers:
  - Fabio Estevam <festevam@gmail.com>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. The following is a full list of i.MX31
  clocks and IDs.

        Clock		    ID
        -----------------------
        dummy	             0
        ckih                 1
        ckil                 2
        mpll                 3
        spll                 4
        upll                 5
        mcu_main             6
        hsp                  7
        ahb                  8
        nfc                  9
        ipg                  10
        per_div              11
        per                  12
        csi_sel              13
        fir_sel              14
        csi_div              15
        usb_div_pre          16
        usb_div_post         17
        fir_div_pre          18
        fir_div_post         19
        sdhc1_gate           20
        sdhc2_gate           21
        gpt_gate             22
        epit1_gate           23
        epit2_gate           24
        iim_gate             25
        ata_gate             26
        sdma_gate            27
        cspi3_gate           28
        rng_gate             29
        uart1_gate           30
        uart2_gate           31
        ssi1_gate            32
        i2c1_gate            33
        i2c2_gate            34
        i2c3_gate            35
        hantro_gate          36
        mstick1_gate         37
        mstick2_gate         38
        csi_gate             39
        rtc_gate             40
        wdog_gate            41
        pwm_gate             42
        sim_gate             43
        ect_gate             44
        usb_gate             45
        kpp_gate             46
        ipu_gate             47
        uart3_gate           48
        uart4_gate           49
        uart5_gate           50
        owire_gate           51
        ssi2_gate            52
        cspi1_gate           53
        cspi2_gate           54
        gacc_gate            55
        emi_gate             56
        rtic_gate            57
        firi_gate            58

properties:
  compatible:
    const: fsl,imx31-ccm

  reg:
    maxItems: 1

  interrupts:
    description: CCM provides 2 interrupt requests, request 1 is to generate
      interrupt for DVFS when a frequency change is requested, request 2 is
      to generate interrupt for DPTC when a voltage change is requested.
    items:
      - description: CCM DVFS interrupt request 1
      - description: CCM DPTC interrupt request 2

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller@53f80000 {
        compatible = "fsl,imx31-ccm";
        reg = <0x53f80000 0x4000>;
        interrupts = <31>, <53>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx35-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX35

maintainers:
  - Steffen Trumtrar <s.trumtrar@pengutronix.de>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. The following is a full list of i.MX35
  clocks and IDs.

        Clock			ID
        ---------------------------
        ckih			0
        mpll			1
        ppll			2
        mpll_075		3
        arm			4
        hsp			5
        hsp_div			6
        hsp_sel			7
        ahb			8
        ipg			9
        arm_per_div		10
        ahb_per_div		11
        ipg_per			12
        uart_sel		13
        uart_div		14
        esdhc_sel		15
        esdhc1_div		16
        esdhc2_div		17
        esdhc3_div		18
        spdif_sel		19
        spdif_div_pre		20
        spdif_div_post		21
        ssi_sel			22
        ssi1_div_pre		23
        ssi1_div_post		24
        ssi2_div_pre		25
        ssi2_div_post		26
        usb_sel			27
        usb_div			28
        nfc_div			29
        asrc_gate		30
        pata_gate		31
        audmux_gate		32
        can1_gate		33
        can2_gate		34
        cspi1_gate		35
        cspi2_gate		36
        ect_gate		37
        edio_gate		38
        emi_gate		39
        epit1_gate		40
        epit2_gate		41
        esai_gate		42
        esdhc1_gate		43
        esdhc2_gate		44
        esdhc3_gate		45
        fec_gate		46
        gpio1_gate		47
        gpio2_gate		48
        gpio3_gate		49
        gpt_gate		50
        i2c1_gate		51
        i2c2_gate		52
        i2c3_gate		53
        iomuxc_gate		54
        ipu_gate		55
        kpp_gate		56
        mlb_gate		57
        mshc_gate		58
        owire_gate		59
        pwm_gate		60
        rngc_gate		61
        rtc_gate		62
        rtic_gate		63
        scc_gate		64
        sdma_gate		65
        spba_gate		66
        spdif_gate		67
        ssi1_gate		68
        ssi2_gate		69
        uart1_gate		70
        uart2_gate		71
        uart3_gate		72
        usbotg_gate		73
        wdog_gate		74
        max_gate		75
        admux_gate		76
        csi_gate		77
        csi_div			78
        csi_sel			79
        iim_gate		80
        gpu2d_gate		81
        ckli_gate		82

properties:
  compatible:
    const: fsl,imx35-ccm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller@53f80000 {
        compatible = "fsl,imx35-ccm";
        reg = <0x53f80000 0x4000>;
        interrupts = <31>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx5-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX5

maintainers:
  - Fabio Estevam <festevam@gmail.com>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h
  for the full list of i.MX5 clock IDs.

properties:
  compatible:
    enum:
      - fsl,imx53-ccm
      - fsl,imx51-ccm
      - fsl,imx50-ccm

  reg:
    maxItems: 1

  interrupts:
    description: CCM provides 2 interrupt requests, request 1 is to generate
      interrupt for frequency or mux change, request 2 is to generate
      interrupt for oscillator read or PLL lock.
    items:
      - description: CCM interrupt request 1
      - description: CCM interrupt request 2

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx5-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    clock-controller@53fd4000{
        compatible = "fsl,imx53-ccm";
        reg = <0x53fd4000 0x4000>;
        interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
                     <0 72 IRQ_TYPE_LEVEL_HIGH>;
        #clock-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx6q-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX6 Quad

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

properties:
  compatible:
    const: fsl,imx6q-ccm

  reg:
    maxItems: 1

  interrupts:
    description: CCM provides 2 interrupt requests, request 1 is to generate
      interrupt for frequency or mux change, request 2 is to generate
      interrupt for oscillator read or PLL lock.
    items:
      - description: CCM interrupt request 1
      - description: CCM interrupt request 2

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: 24m osc
      - description: 32k osc
      - description: ckih1 clock input
      - description: anaclk1 clock input
      - description: anaclk2 clock input

  clock-names:
    items:
      - const: osc
      - const: ckil
      - const: ckih1
      - const: anaclk1
      - const: anaclk2

  fsl,pmic-stby-poweroff:
    $ref: /schemas/types.yaml#/definitions/flag
    description: |
      Use this property if the SoC should be powered off by external power
      management IC (PMIC) triggered via PMIC_STBY_REQ signal.
      Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should
      be using "syscon-poweroff" driver instead.

required:
  - compatible
  - reg
  - interrupts
  - '#clock-cells'

additionalProperties: false

examples:
  # Clock Control Module node:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    clock-controller@20c4000 {
        compatible = "fsl,imx6q-ccm";
        reg = <0x020c4000 0x4000>;
        interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
                     <0 88 IRQ_TYPE_LEVEL_HIGH>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx6sl-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX6 SoloLite

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

properties:
  compatible:
    const: fsl,imx6sl-ccm

  reg:
    maxItems: 1

  interrupts:
    description: CCM provides 2 interrupt requests, request 1 is to generate
      interrupt for frequency or mux change, request 2 is to generate
      interrupt for oscillator read or PLL lock.
    items:
      - description: CCM interrupt request 1
      - description: CCM interrupt request 2

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - '#clock-cells'

additionalProperties: false

examples:
  # Clock Control Module node:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    clock-controller@20c4000 {
        compatible = "fsl,imx6sl-ccm";
        reg = <0x020c4000 0x4000>;
        interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
                     <0 88 IRQ_TYPE_LEVEL_HIGH>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx6sll-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX6 SLL

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

properties:
  compatible:
    const: fsl,imx6sll-ccm

  reg:
    maxItems: 1

  interrupts:
    description: CCM provides 2 interrupt requests, request 1 is to generate
      interrupt for frequency or mux change, request 2 is to generate
      interrupt for oscillator read or PLL lock.
    items:
      - description: CCM interrupt request 1
      - description: CCM interrupt request 2

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: 32k osc
      - description: 24m osc
      - description: ipp_di0 clock input
      - description: ipp_di1 clock input

  clock-names:
    items:
      - const: ckil
      - const: osc
      - const: ipp_di0
      - const: ipp_di1

required:
  - compatible
  - reg
  - interrupts
  - '#clock-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  # Clock Control Module node:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    clock-controller@20c4000 {
        compatible = "fsl,imx6sll-ccm";
        reg = <0x020c4000 0x4000>;
        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
        #clock-cells = <1>;
        clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
        clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx6sx-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX6 SoloX

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

properties:
  compatible:
    const: fsl,imx6sx-ccm

  reg:
    maxItems: 1

  interrupts:
    description: CCM provides 2 interrupt requests, request 1 is to generate
      interrupt for frequency or mux change, request 2 is to generate
      interrupt for oscillator read or PLL lock.
    items:
      - description: CCM interrupt request 1
      - description: CCM interrupt request 2

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: 32k osc
      - description: 24m osc
      - description: ipp_di0 clock input
      - description: ipp_di1 clock input
      - description: anaclk1 clock input
      - description: anaclk2 clock input

  clock-names:
    items:
      - const: ckil
      - const: osc
      - const: ipp_di0
      - const: ipp_di1
      - const: anaclk1
      - const: anaclk2

required:
  - compatible
  - reg
  - interrupts
  - '#clock-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  # Clock Control Module node:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    clock-controller@20c4000 {
        compatible = "fsl,imx6sx-ccm";
        reg = <0x020c4000 0x4000>;
        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
        #clock-cells = <1>;
        clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
        clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx6ul-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX6 UltraLite

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

properties:
  compatible:
    const: fsl,imx6ul-ccm

  reg:
    maxItems: 1

  interrupts:
    description: CCM provides 2 interrupt requests, request 1 is to generate
      interrupt for frequency or mux change, request 2 is to generate
      interrupt for oscillator read or PLL lock.
    items:
      - description: CCM interrupt request 1
      - description: CCM interrupt request 2

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: 32k osc
      - description: 24m osc
      - description: ipp_di0 clock input
      - description: ipp_di1 clock input

  clock-names:
    items:
      - const: ckil
      - const: osc
      - const: ipp_di0
      - const: ipp_di1

required:
  - compatible
  - reg
  - interrupts
  - '#clock-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  # Clock Control Module node:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    clock-controller@20c4000 {
        compatible = "fsl,imx6ul-ccm";
        reg = <0x020c4000 0x4000>;
        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
        #clock-cells = <1>;
        clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
        clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx7d-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX7 Dual

maintainers:
  - Frank Li <Frank.Li@nxp.com>
  - Anson Huang <Anson.Huang@nxp.com>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h
  for the full list of i.MX7 Dual clock IDs.

properties:
  compatible:
    const: fsl,imx7d-ccm

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: CCM interrupt request 1
      - description: CCM interrupt request 2

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: 32k osc
      - description: 24m osc

  clock-names:
    items:
      - const: ckil
      - const: osc

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    clock-controller@30380000 {
        compatible = "fsl,imx7d-ccm";
        reg = <0x30380000 0x10000>;
        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
        #clock-cells = <1>;
        clocks = <&ckil>, <&osc>;
        clock-names = "ckil", "osc";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules

maintainers:
  - A.s. Dong <aisheng.dong@nxp.com>

description: |
  i.MX7ULP Clock functions are under joint control of the System
  Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
  modules, and Core Mode Controller (CMC)1 blocks

  The clocking scheme provides clear separation between M4 domain
  and A7 domain. Except for a few clock sources shared between two
  domains, such as the System Oscillator clock, the Slow IRC (SIRC),
  and and the Fast IRC clock (FIRCLK), clock sources and clock
  management are separated and contained within each domain.

  M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
  A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.

  Note: this binding doc is only for A7 clock domain.

  The Peripheral Clock Control (PCC) is responsible for clock selection,
  optional division and clock gating mode for peripherals in their
  respected power domain.

  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell.
  See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
  i.MX7ULP clock IDs of each module.

properties:
  compatible:
    enum:
      - fsl,imx7ulp-pcc2
      - fsl,imx7ulp-pcc3

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: nic1 bus clock
      - description: nic1 clock
      - description: ddr clock
      - description: apll pfd2
      - description: apll pfd1
      - description: apll pfd0
      - description: usb pll
      - description: system osc bus clock
      - description: fast internal reference clock bus
      - description: rtc osc
      - description: system pll bus clock

  clock-names:
    items:
      - const: nic1_bus_clk
      - const: nic1_clk
      - const: ddr_clk
      - const: apll_pfd2
      - const: apll_pfd1
      - const: apll_pfd0
      - const: upll
      - const: sosc_bus_clk
      - const: firc_bus_clk
      - const: rosc
      - const: spll_bus_clk

required:
  - compatible
  - reg
  - '#clock-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx7ulp-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    clock-controller@403f0000 {
        compatible = "fsl,imx7ulp-pcc2";
        reg = <0x403f0000 0x10000>;
        #clock-cells = <1>;
        clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
                 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
                 <&scg1 IMX7ULP_CLK_DDR_DIV>,
                 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
                 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
                 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
                 <&scg1 IMX7ULP_CLK_UPLL>,
                 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
                 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
                 <&scg1 IMX7ULP_CLK_ROSC>,
                 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
         clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
                       "apll_pfd2", "apll_pfd1", "apll_pfd0",
                       "upll", "sosc_bus_clk", "firc_bus_clk",
                       "rosc", "spll_bus_clk";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX7ULP System Clock Generation (SCG) modules

maintainers:
  - A.s. Dong <aisheng.dong@nxp.com>

description: |
  i.MX7ULP Clock functions are under joint control of the System
  Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
  modules, and Core Mode Controller (CMC)1 blocks

  The clocking scheme provides clear separation between M4 domain
  and A7 domain. Except for a few clock sources shared between two
  domains, such as the System Oscillator clock, the Slow IRC (SIRC),
  and and the Fast IRC clock (FIRCLK), clock sources and clock
  management are separated and contained within each domain.

  M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
  A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.

  Note: this binding doc is only for A7 clock domain.

  The System Clock Generation (SCG) is responsible for clock generation
  and distribution across this device. Functions performed by the SCG
  include: clock reference selection, generation of clock used to derive
  processor, system, peripheral bus and external memory interface clocks,
  source selection for peripheral clocks and control of power saving
  clock gating mode.

  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell.
  See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
  i.MX7ULP clock IDs of each module.

properties:
  compatible:
    const: fsl,imx7ulp-scg1

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: rtc osc
      - description: system osc
      - description: slow internal reference clock
      - description: fast internal reference clock
      - description: usb PLL

  clock-names:
    items:
      - const: rosc
      - const: sosc
      - const: sirc
      - const: firc
      - const: upll

required:
  - compatible
  - reg
  - '#clock-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx7ulp-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    clock-controller@403e0000 {
        compatible = "fsl,imx7ulp-scg1";
        reg = <0x403e0000 0x10000>;
        clocks = <&rosc>, <&sosc>, <&sirc>,
                 <&firc>, <&upll>;
        clock-names = "rosc", "sosc", "sirc",
                      "firc", "upll";
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8m-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8M Family Clock Control Module Binding

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

description: |
  NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock
  controller, which generates and supplies to all modules.

properties:
  compatible:
    enum:
      - fsl,imx8mm-ccm
      - fsl,imx8mn-ccm
      - fsl,imx8mp-ccm
      - fsl,imx8mq-ccm

  reg:
    maxItems: 1

  clocks:
    minItems: 6
    maxItems: 7

  clock-names:
    minItems: 6
    maxItems: 7

  '#clock-cells':
    const: 1
    description:
      The clock consumer should specify the desired clock by having the clock
      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h
      for the full list of i.MX8M clock IDs.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8mq-ccm
    then:
      properties:
        clocks:
          items:
            - description: 32k osc
            - description: 25m osc
            - description: 27m osc
            - description: ext1 clock input
            - description: ext2 clock input
            - description: ext3 clock input
            - description: ext4 clock input
        clock-names:
          items:
            - const: ckil
            - const: osc_25m
            - const: osc_27m
            - const: clk_ext1
            - const: clk_ext2
            - const: clk_ext3
            - const: clk_ext4
    else:
      properties:
        clocks:
          items:
            - description: 32k osc
            - description: 24m osc
            - description: ext1 clock input
            - description: ext2 clock input
            - description: ext3 clock input
            - description: ext4 clock input

        clock-names:
          items:
            - const: osc_32k
            - const: osc_24m
            - const: clk_ext1
            - const: clk_ext2
            - const: clk_ext3
            - const: clk_ext4

additionalProperties: false

examples:
  # Clock Control Module node:
  - |
    clock-controller@30380000 {
        compatible = "fsl,imx8mm-ccm";
        reg = <0x30380000 0x10000>;
        #clock-cells = <1>;
        clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
                 <&clk_ext3>, <&clk_ext4>;
        clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
                      "clk_ext3", "clk_ext4";
    };

  - |
    clock-controller@30390000 {
        compatible = "fsl,imx8mq-ccm";
        reg = <0x30380000 0x10000>;
        #clock-cells = <1>;
        clocks = <&ckil>, <&osc_25m>, <&osc_27m>, <&clk_ext1>,
                 <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
        clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1",
                      "clk_ext2", "clk_ext3", "clk_ext4";
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings

maintainers:
  - Aisheng Dong <aisheng.dong@nxp.com>

description: |
  The Low-Power Clock Gate (LPCG) modules contain a local programming
  model to control the clock gates for the peripherals. An LPCG module
  is used to locally gate the clocks for the associated peripheral.

  This level of clock gating is provided after the clocks are generated
  by the SCU resources and clock controls. Thus even if the clock is
  enabled by these control bits, it might still not be running based
  on the base resource.

  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. See the full list of clock IDs from:
  include/dt-bindings/clock/imx8-lpcg.h

properties:
  compatible:
    oneOf:
      - const: fsl,imx8qxp-lpcg
      - items:
          - enum:
              - fsl,imx8qm-lpcg
          - const: fsl,imx8qxp-lpcg
      - enum:
          - fsl,imx8qxp-lpcg-adma
          - fsl,imx8qxp-lpcg-conn
          - fsl,imx8qxp-lpcg-dc
          - fsl,imx8qxp-lpcg-dsp
          - fsl,imx8qxp-lpcg-gpu
          - fsl,imx8qxp-lpcg-hsio
          - fsl,imx8qxp-lpcg-img
          - fsl,imx8qxp-lpcg-lsio
          - fsl,imx8qxp-lpcg-vpu
        deprecated: true
  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  clocks:
    description: |
      Input parent clocks phandle array for each clock
    minItems: 1
    maxItems: 8

  clock-indices:
    description: |
      An integer array indicating the bit offset for each clock.
      Refer to <include/dt-bindings/clock/imx8-lpcg.h> for the
      supported LPCG clock indices.
    minItems: 1
    maxItems: 8

  clock-output-names:
    description: |
      Shall be the corresponding names of the outputs.
      NOTE this property must be specified in the same order
      as the clock-indices property.
    minItems: 1
    maxItems: 8

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8-lpcg.h>
    #include <dt-bindings/firmware/imx/rsrc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    sdhc0_lpcg: clock-controller@5b200000 {
        compatible = "fsl,imx8qxp-lpcg";
        reg = <0x5b200000 0x10000>;
        #clock-cells = <1>;
        clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>,
                 <&conn_ipg_clk>,
                 <&conn_axi_clk>;
        clock-indices = <IMX_LPCG_CLK_0>,
                        <IMX_LPCG_CLK_4>,
                        <IMX_LPCG_CLK_5>;
        clock-output-names = "sdhc0_lpcg_per_clk",
                             "sdhc0_lpcg_ipg_clk",
                             "sdhc0_lpcg_ahb_clk";
        power-domains = <&pd IMX_SC_R_SDHC_0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8ULP Clock Generation & Control(CGC) Module Binding

maintainers:
  - Jacky Bai <ping.bai@nxp.com>

description: |
  On i.MX8ULP, The clock sources generation, distribution and management is
  under the control of several CGCs & PCCs modules. The CGC modules generate
  and distribute clocks on the device.

properties:
  compatible:
    enum:
      - fsl,imx8ulp-cgc1
      - fsl,imx8ulp-cgc2

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  # Clock Generation & Control Module node:
  - |
    clock-controller@292c0000 {
        compatible = "fsl,imx8ulp-cgc1";
        reg = <0x292c0000 0x10000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module Binding

maintainers:
  - Jacky Bai <ping.bai@nxp.com>

description: |
  On i.MX8ULP, The clock sources generation, distribution and management is
  under the control of several CGCs & PCCs modules. The PCC modules control
  software reset, clock selection, optional division and clock gating mode
  for peripherals.

properties:
  compatible:
    enum:
      - fsl,imx8ulp-pcc3
      - fsl,imx8ulp-pcc4
      - fsl,imx8ulp-pcc5

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'
  - '#reset-cells'

additionalProperties: false

examples:
  # Peripheral Clock Control Module node:
  - |
    clock-controller@292d0000 {
        compatible = "fsl,imx8ulp-pcc3";
        reg = <0x292d0000 0x10000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx93-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX93 Clock Control Module Binding

maintainers:
  - Peng Fan <peng.fan@nxp.com>

description: |
  i.MX93 clock control module is an integrated clock controller, which
  includes clock generator, clock gate and supplies to all modules.

properties:
  compatible:
    enum:
      - fsl,imx93-ccm

  reg:
    maxItems: 1

  clocks:
    description:
      specify the external clocks used by the CCM module.
    items:
      - description: 32k osc
      - description: 24m osc
      - description: ext1 clock input

  clock-names:
    description:
      specify the external clocks names used by the CCM module.
    items:
      - const: osc_32k
      - const: osc_24m
      - const: clk_ext1

  '#clock-cells':
    const: 1
    description:
      See include/dt-bindings/clock/imx93-clock.h for the full list of
      i.MX93 clock IDs.

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  # Clock Control Module node:
  - |
    clock-controller@44450000 {
        compatible = "fsl,imx93-ccm";
        reg = <0x44450000 0x10000>;
        #clock-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imxrt1050-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MXRT

maintainers:
  - Giulio Benetti <giulio.benetti@benettiengineering.com>
  - Jesse Taube <Mr.Bossman075@gmail.com>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell. See include/dt-bindings/clock/imxrt*-clock.h
  for the full list of i.MXRT clock IDs.

properties:
  compatible:
    const: fsl,imxrt1050-ccm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 2

  clocks:
    description: 24m osc
    maxItems: 1

  clock-names:
    const: osc

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imxrt1050-clock.h>

    clks: clock-controller@400fc000 {
        compatible = "fsl,imxrt1050-ccm";
        reg = <0x400fc000 0x4000>;
        interrupts = <95>, <96>;
        clocks = <&osc>;
        clock-names = "osc";
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ingenic,cgu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs CGU devicetree bindings

description: |
  The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
  typically includes a variety of PLLs, multiplexers, dividers & gates in order
  to provide many different clock signals derived from only 2 external source
  clocks.

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

select:
  properties:
    compatible:
      contains:
        enum:
          - ingenic,jz4740-cgu
          - ingenic,jz4725b-cgu
          - ingenic,jz4755-cgu
          - ingenic,jz4760-cgu
          - ingenic,jz4760b-cgu
          - ingenic,jz4770-cgu
          - ingenic,jz4780-cgu
          - ingenic,x1000-cgu
          - ingenic,x1830-cgu
  required:
    - compatible

properties:
  $nodename:
    pattern: "^clock-controller@[0-9a-f]+$"

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  "#clock-cells":
    const: 1

  ranges: true

  compatible:
    items:
      - enum:
          - ingenic,jz4740-cgu
          - ingenic,jz4725b-cgu
          - ingenic,jz4755-cgu
          - ingenic,jz4760-cgu
          - ingenic,jz4760b-cgu
          - ingenic,jz4770-cgu
          - ingenic,jz4780-cgu
          - ingenic,x1000-cgu
          - ingenic,x1830-cgu
      - const: simple-mfd
    minItems: 1

  reg:
    maxItems: 1

  clocks:
    items:
      - description: External oscillator clock
      - description: Internal 32 kHz RTC clock

  clock-names:
    items:
      - const: ext
      - enum:
          - rtc
          - osc32k # Different name, same clock

  assigned-clocks:
    minItems: 1
    maxItems: 64

  assigned-clock-parents:
    minItems: 1
    maxItems: 64

  assigned-clock-rates:
    minItems: 1
    maxItems: 64

required:
  - "#clock-cells"
  - compatible
  - reg
  - clocks
  - clock-names

patternProperties:
  "^usb-phy@[a-f0-9]+$":
    allOf: [ $ref: "../phy/ingenic,phy-usb.yaml#" ]
  "^mac-phy-ctrl@[a-f0-9]+$":
    allOf: [ $ref: "../net/ingenic,mac.yaml#" ]

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
    cgu: clock-controller@10000000 {
      compatible = "ingenic,jz4770-cgu", "simple-mfd";
      reg = <0x10000000 0x100>;
      #address-cells = <1>;
      #size-cells = <1>;
      ranges = <0x0 0x10000000 0x100>;

      clocks = <&ext>, <&osc32k>;
      clock-names = "ext", "osc32k";

      #clock-cells = <1>;

      otg_phy: usb-phy@3c {
        compatible = "ingenic,jz4770-phy";
        reg = <0x3c 0x10>;

        clocks = <&cgu JZ4770_CLK_OTG_PHY>;

        vcc-supply = <&ldo5>;

        #phy-cells = <0>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/intel,agilex.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel SoCFPGA Agilex platform clock controller binding

maintainers:
  - Dinh Nguyen <dinguyen@kernel.org>

description:
  The Intel Agilex Clock controller is an integrated clock controller, which
  generates and supplies to all modules.

properties:
  compatible:
    const: intel,agilex-clkmgr

  '#clock-cells':
    const: 1

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  # Clock controller node:
  - |
    clkmgr: clock-controller@ffd10000 {
      compatible = "intel,agilex-clkmgr";
      reg = <0xffd10000 0x1000>;
      clocks = <&osc1>;
      #clock-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Lightning Mountain SoC's Clock Controller(CGU) Binding

maintainers:
  - Rahul Tanwar <rahul.tanwar@linux.intel.com>

description: |
  Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
  all means to access the CGU hardware module in order to generate a series
  of clocks for the whole system and individual peripherals.

  Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it
  defines all available clocks as macros. These macros can be used in device
  tree sources.

properties:
  compatible:
    const: intel,cgu-lgm

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    cgu: clock-controller@e0200000 {
        compatible = "intel,cgu-lgm";
        reg = <0xe0200000 0x33c>;
        #clock-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/intel,easic-n5x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel SoCFPGA eASIC N5X platform clock controller binding

maintainers:
  - Dinh Nguyen <dinguyen@kernel.org>

description:
  The Intel eASIC N5X Clock controller is an integrated clock controller, which
  generates and supplies to all modules.

properties:
  compatible:
    const: intel,easic-n5x-clkmgr

  '#clock-cells':
    const: 1

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  # Clock controller node:
  - |
    clkmgr: clock-controller@ffd10000 {
      compatible = "intel,easic-n5x-clkmgr";
      reg = <0xffd10000 0x1000>;
      clocks = <&osc1>;
      #clock-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/intel,stratix10.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel SoCFPGA Stratix10 platform clock controller binding

maintainers:
  - Dinh Nguyen <dinguyen@kernel.org>

properties:
  compatible:
    const: intel,stratix10-clkmgr

  '#clock-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller@ffd10000 {
        compatible = "intel,stratix10-clkmgr";
        reg = <0xffd10000 0x1000>;
        #clock-cells = <1>;
    };


code:
Status: Unstable - ABI compatibility may be broken in the future

Binding for Keystone gate control driver which uses PSC controller IP.

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be "ti,keystone,psc-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : parent clock phandle
- reg :	psc control and domain address address space
- reg-names : psc control and domain registers
- domain-id : psc domain id needed to check the transition state register

Optional properties:
- clock-output-names : From common clock binding to override the
			default output clock name
Example:
	clkusb: clkusb {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk16>;
		clock-output-names = "usb";
		reg = <0x02350008 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};


code:
Status: Unstable - ABI compatibility may be broken in the future

Binding for keystone PLLs. The main PLL IP typically has a multiplier,
a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
and PAPLL are controlled by the memory mapped register where as the Main
PLL is controlled by a PLL controller registers along with memory mapped
registers.

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
- clocks : parent clock phandle
- reg - pll control0 and pll multipler registers
- reg-names : control, multiplier and post-divider. The multiplier and
		post-divider registers are applicable only for main pll clock
- fixed-postdiv : fixed post divider value. If absent, use clkod register bits
		for postdiv

Example:
	mainpllclk: mainpllclk@2310110 {
		#clock-cells = <0>;
		compatible = "ti,keystone,main-pll-clock";
		clocks = <&refclksys>;
		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
		reg-names = "control", "multiplier", "post-divider";
		fixed-postdiv = <2>;
	};

	papllclk: papllclk@2620358 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-clock";
		clocks = <&refclkpass>;
		clock-output-names = "pa-pll-clk";
		reg = <0x02620358 4>;
		reg-names = "control";
	};

Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- compatible : shall be "ti,keystone,pll-mux-clock"
- clocks : link phandles of parent clocks
- reg - pll mux register
- bit-shift : number of bits to shift the bit-mask
- bit-mask : arbitrary bitmask for programming the mux

Optional properties:
- clock-output-names : From common clock binding.

Example:
	mainmuxclk: mainmuxclk@2310108 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-mux-clock";
		clocks = <&mainpllclk>, <&refclkmain>;
		reg = <0x02310108 4>;
		bit-shift = <23>;
		bit-mask = <1>;
		clock-output-names = "mainmuxclk";
	};

Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- compatible : shall be "ti,keystone,pll-divider-clock"
- clocks : parent clock phandle
- reg - pll mux register
- bit-shift : number of bits to shift the bit-mask
- bit-mask : arbitrary bitmask for programming the divider

Optional properties:
- clock-output-names : From common clock binding.

Example:
	gemtraceclk: gemtraceclk@2310120 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-divider-clock";
		clocks = <&mainmuxclk>;
		reg = <0x02310120 4>;
		bit-shift = <0>;
		bit-mask = <8>;
		clock-output-names = "gemtraceclk";
	};


code:
* NXP LPC1850 Clock Control Unit (CCU)

Each CGU base clock has several clock branches which can be turned on
or off independently by the Clock Control Units CCU1 or CCU2. The
branch clocks are distributed between CCU1 and CCU2.

 - Above text taken from NXP LPC1850 User Manual.

This binding uses the common clock binding:
    Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible:
	Should be "nxp,lpc1850-ccu"
- reg:
	Shall define the base and range of the address space
	containing clock control registers
- #clock-cells:
	Shall have value <1>.  The permitted clock-specifier values
	are the branch clock names defined in table below.
- clocks:
	Shall contain a list of phandles for the base clocks routed
	from the CGU to the specific CCU. See mapping of base clocks
	and CCU in table below.
- clock-names:
	Shall contain a list of names for the base clock routed
	from the CGU to the specific CCU. Valid CCU clock names:
	"base_usb0_clk",  "base_periph_clk", "base_usb1_clk",
	"base_cpu_clk",   "base_spifi_clk",  "base_spi_clk",
	"base_apb1_clk",  "base_apb3_clk",   "base_adchs_clk",
	"base_sdio_clk",  "base_ssp0_clk",   "base_ssp1_clk",
	"base_uart0_clk", "base_uart1_clk",  "base_uart2_clk",
	"base_uart3_clk", "base_audio_clk"

Which branch clocks that are available on the CCU depends on the
specific LPC part. Check the user manual for your specific part.

A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.

Example board file:

soc {
	ccu1: clock-controller@40051000 {
		compatible = "nxp,lpc1850-ccu";
		reg = <0x40051000 0x1000>;
		#clock-cells = <1>;
		clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
			 <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
			 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
			 <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
		clock-names = "base_apb3_clk",   "base_apb1_clk",
			      "base_spifi_clk",  "base_cpu_clk",
			      "base_periph_clk", "base_usb0_clk",
			      "base_usb1_clk",   "base_spi_clk";
	};

	ccu2: clock-controller@40052000 {
		compatible = "nxp,lpc1850-ccu";
		reg = <0x40052000 0x1000>;
		#clock-cells = <1>;
		clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
			 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
			 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
			 <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
		clock-names = "base_audio_clk", "base_uart3_clk",
			      "base_uart2_clk", "base_uart1_clk",
			      "base_uart0_clk", "base_ssp1_clk",
			      "base_ssp0_clk",  "base_sdio_clk";
	};

	/* A user of CCU brach clocks */
	uart1: serial@40082000 {
		...
		clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
		...
	};
};


code:
* NXP LPC1850 Clock Generation Unit (CGU)

The CGU generates multiple independent clocks for the core and the
peripheral blocks of the LPC18xx. Each independent clock is called
a base clock and itself is one of the inputs to the two Clock
Control Units (CCUs) which control the branch clocks to the
individual peripherals.

The CGU selects the inputs to the clock generators from multiple
clock sources, controls the clock generation, and routes the outputs
of the clock generators through the clock source bus to the output
stages. Each output stage provides an independent clock source and
corresponds to one of the base clocks for the LPC18xx.

 - Above text taken from NXP LPC1850 User Manual.

This binding uses the common clock binding:
    Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible:
	Should be "nxp,lpc1850-cgu"
- reg:
	Shall define the base and range of the address space
	containing clock control registers
- #clock-cells:
	Shall have value <1>.  The permitted clock-specifier values
	are the base clock numbers defined below.
- clocks:
	Shall contain a list of phandles for the external input
	sources to the CGU. The list shall be in the following
	order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin.
- clock-indices:
	Shall be an ordered list of numbers defining the base clock
	number provided by the CGU.
- clock-output-names:
	Shall be an ordered list of strings defining the names of
	the clocks provided by the CGU.

Which base clocks that are available on the CGU depends on the
specific LPC part. Base clocks are numbered from 0 to 27.

Number:		Name:			Description:
 0		BASE_SAFE_CLK		Base safe clock (always on) for WWDT
 1		BASE_USB0_CLK		Base clock for USB0
 2		BASE_PERIPH_CLK		Base clock for Cortex-M0SUB subsystem,
					SPI, and SGPIO
 3		BASE_USB1_CLK		Base clock for USB1
 4		BASE_CPU_CLK		System base clock for ARM Cortex-M core
					and APB peripheral blocks #0 and #2
 5		BASE_SPIFI_CLK		Base clock for SPIFI
 6		BASE_SPI_CLK		Base clock for SPI
 7		BASE_PHY_RX_CLK		Base clock for Ethernet PHY Receive clock
 8		BASE_PHY_TX_CLK		Base clock for Ethernet PHY Transmit clock
 9		BASE_APB1_CLK		Base clock for APB peripheral block # 1
10		BASE_APB3_CLK		Base clock for APB peripheral block # 3
11		BASE_LCD_CLK		Base clock for LCD
12		BASE_ADCHS_CLK		Base clock for ADCHS
13		BASE_SDIO_CLK		Base clock for SD/MMC
14		BASE_SSP0_CLK		Base clock for SSP0
15		BASE_SSP1_CLK		Base clock for SSP1
16		BASE_UART0_CLK		Base clock for UART0
17		BASE_UART1_CLK		Base clock for UART1
18		BASE_UART2_CLK		Base clock for UART2
19		BASE_UART3_CLK		Base clock for UART3
20		BASE_OUT_CLK		Base clock for CLKOUT pin
24-21		-			Reserved
25		BASE_AUDIO_CLK		Base clock for audio system (I2S)
26 		BASE_CGU_OUT0_CLK	Base clock for CGU_OUT0 clock output
27 		BASE_CGU_OUT1_CLK	Base clock for CGU_OUT1 clock output

BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.
BASE_ADCHS_CLK is only available on LPC4370.

Example board file:

/ {
	clocks {
		xtal: xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <12000000>;
		};

		xtal32: xtal32 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		enet_rx_clk: enet_rx_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "enet_rx_clk";
		};

		enet_tx_clk: enet_tx_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "enet_tx_clk";
		};

		gp_clkin: gp_clkin {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "gp_clkin";
		};
	};

	soc {
		cgu: clock-controller@40050000 {
			compatible = "nxp,lpc1850-cgu";
			reg = <0x40050000 0x1000>;
			#clock-cells = <1>;
			clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
		};

		/* A CGU and CCU clock consumer */
		lcdc: lcdc@40008000 {
			...
			clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
			clock-names = "clcdclk", "apb_pclk";
			...
		};
	};
};


code:
* NXP LPC1850 CREG clocks

The NXP LPC18xx/43xx CREG (Configuration Registers) block contains
control registers for two low speed clocks. One of the clocks is a
32 kHz oscillator driver with power up/down and clock gating. Next
is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.

These clocks are used by the RTC and the Event Router peripherials.
The 32 kHz can also be routed to other peripherials to enable low
power modes.

This binding uses the common clock binding:
    Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible:
	Should be "nxp,lpc1850-creg-clk"
- #clock-cells:
	Shall have value <1>.
- clocks:
	Shall contain a phandle to the fixed 32 kHz crystal.

The creg-clk node must be a child of the creg syscon node.

The following clocks are available from the clock node.

Clock ID	Name
   0		 1 kHz clock
   1		32 kHz Oscillator

Example:
soc {
	creg: syscon@40043000 {
		compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
		reg = <0x40043000 0x1000>;

		creg_clk: clock-controller {
			compatible = "nxp,lpc1850-creg-clk";
			clocks = <&xtal32>;
			#clock-cells = <1>;
		};

		...
	};

	rtc: rtc@40046000 {
		...
		clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
		clock-names = "rtc", "reg";
		...
	};
};


code:
AXM5516 clock driver bindings
-----------------------------

Required properties :
- compatible : shall contain "lsi,axm5516-clks"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1

The consumer specifies the desired clock by having the clock ID in its "clocks"
phandle cell. See <dt-bindings/clock/lsi,axxia-clock.h> for the list of
supported clock IDs.

Example:

	clks: clock-controller@2010020000 {
		compatible = "lsi,axm5516-clks";
		#clock-cells = <1>;
		reg = <0x20 0x10020000 0 0x20000>;
	};

	serial0: uart@2010080000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x20 0x10080000 0 0x1000>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks AXXIA_CLK_PER>;
		clock-names = "apb_pclk";
	};
																																};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 3720 UART clocks

maintainers:
  - Pali Rohár <pali@kernel.org>

properties:
  compatible:
    const: marvell,armada-3700-uart-clock

  reg:
    items:
      - description: UART Clock Control Register
      - description: UART 2 Baud Rate Divisor Register

  clocks:
    description: |
      List of parent clocks suitable for UART from following set:
        "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"
      UART clock can use one from this set and when more are provided
      then kernel would choose and configure the most suitable one.
      It is suggest to specify at least one TBG clock to achieve
      baudrates above 230400 and also to specify clock which bootloader
      used for UART (most probably xtal) for smooth boot log on UART.

  clock-names:
    items:
      - const: TBG-A-P
      - const: TBG-B-P
      - const: TBG-A-S
      - const: TBG-B-S
      - const: xtal
    minItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    uartclk: clock-controller@12010 {
      compatible = "marvell,armada-3700-uart-clock";
      reg = <0x12010 0x4>, <0x12210 0x4>;
      clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>;
      clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal";
      #clock-cells = <1>;
    };


code:
Device Tree Clock bindings for Marvell Berlin

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Clock related registers are spread among the chip control registers. Berlin
clock node should be a sub-node of the chip controller node. Marvell Berlin2
(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some
minor differences in features and register layout.

Required properties:
- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk"
- #clock-cells: must be 1
- clocks: must be the input parent clock phandle
- clock-names: name of the input parent clock
	Allowed clock-names for the reference clocks are
	"refclk" for the SoCs oscillator input on all SoCs,
	and SoC-specific input clocks for
	BG2/BG2CD: "video_ext0" for the external video clock input

Example:

chip_clk: clock {
	compatible = "marvell,berlin2q-clk";

	#clock-cells = <1>;
	clocks = <&refclk>;
	clock-names = "refclk";
};


code:
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,mmp2-audio-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell MMP2 Audio Clock Controller

maintainers:
  - Lubomir Rintel <lkundrak@v3.sk>

description: |
  The audio clock controller generates and supplies the clocks to the audio
  codec.

  Each clock is assigned an identifier and client nodes use this identifier
  to specify the clock which they consume.

  All these identifiers could be found in
  <dt-bindings/clock/marvell,mmp2-audio.h>.

properties:
  compatible:
    enum:
      - marvell,mmp2-audio-clock

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Audio subsystem clock
      - description: The crystal oscillator clock
      - description: First I2S clock
      - description: Second I2S clock

  clock-names:
    items:
      - const: audio
      - const: vctcxo
      - const: i2s0
      - const: i2s1

  '#clock-cells':
    const: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/marvell,mmp2-audio.h>
    #include <dt-bindings/clock/marvell,mmp2.h>
    #include <dt-bindings/power/marvell,mmp2.h>

    clock-controller@d42a0c30 {
      compatible = "marvell,mmp2-audio-clock";
      reg = <0xd42a0c30 0x10>;
      clock-names = "audio", "vctcxo", "i2s0", "i2s1";
      clocks = <&soc_clocks MMP2_CLK_AUDIO>,
               <&soc_clocks MMP2_CLK_VCTCXO>,
               <&soc_clocks MMP2_CLK_I2S0>,
               <&soc_clocks MMP2_CLK_I2S1>;
      power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
      #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell MMP2 and MMP3 Clock Controller

maintainers:
  - Lubomir Rintel <lkundrak@v3.sk>

description: |
  The clock subsystem on MMP2 or MMP3 generates and supplies clock to various
  controllers within the SoC.

  Each clock is assigned an identifier and client nodes use this identifier
  to specify the clock which they consume.

  All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>.

properties:
  compatible:
    enum:
      - marvell,mmp2-clock # controller compatible with MMP2 SoC
      - marvell,mmp3-clock # controller compatible with MMP3 SoC

  reg:
    items:
      - description: MPMU register region
      - description: APMU register region
      - description: APBC register region

  reg-names:
    items:
      - const: mpmu
      - const: apmu
      - const: apbc

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

required:
  - compatible
  - reg
  - reg-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    clock-controller@d4050000 {
      compatible = "marvell,mmp2-clock";
      reg = <0xd4050000 0x1000>,
            <0xd4282800 0x400>,
            <0xd4015000 0x1000>;
      reg-names = "mpmu", "apmu", "apbc";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };


code:
* Marvell PXA168 Clock Controller

The PXA168 clock subsystem generates and supplies clock to various
controllers within the PXA168 SoC.

Required Properties:

- compatible: should be one of the following.
  - "marvell,pxa168-clock" - controller compatible with PXA168 SoC.

- reg: physical base address of the clock subsystem and length of memory mapped
  region. There are 3 places in SOC has clock control logic:
  "mpmu", "apmu", "apbc". So three reg spaces need to be defined.

- #clock-cells: should be 1.
- #reset-cells: should be 1.

Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.

All these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>.


code:
* Marvell PXA1928 Clock Controllers

The PXA1928 clock subsystem generates and supplies clock to various
controllers within the PXA1928 SoC. The PXA1928 contains 3 clock controller
blocks called APMU, MPMU, and APBC roughly corresponding to internal buses.

Required Properties:

- compatible: should be one of the following.
  - "marvell,pxa1928-apmu" - APMU controller compatible
  - "marvell,pxa1928-mpmu" - MPMU controller compatible
  - "marvell,pxa1928-apbc" - APBC controller compatible
- reg: physical base address of the clock controller and length of memory mapped
  region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.

Each clock is assigned an identifier and client nodes use the clock controller
phandle and this identifier to specify the clock which they consume.

All these identifiers can be found in <dt-bindings/clock/marvell,pxa1928.h>.


code:
* Marvell PXA910 Clock Controller

The PXA910 clock subsystem generates and supplies clock to various
controllers within the PXA910 SoC.

Required Properties:

- compatible: should be one of the following.
  - "marvell,pxa910-clock" - controller compatible with PXA910 SoC.

- reg: physical base address of the clock subsystem and length of memory mapped
  region. There are 4 places in SOC has clock control logic:
  "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.

- #clock-cells: should be 1.
- #reset-cells: should be 1.

Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.

All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.


code:
Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block

This is a part of device tree bindings of MAX77686/MAX77802/MAX77620
multi-function device. More information can be found in MFD DT binding
doc as follows:
	bindings/mfd/max77686.txt for MAX77686 and
	bindings/mfd/max77802.txt for MAX77802 and
	bindings/mfd/max77620.txt for MAX77620.

The MAX77686 contains three 32.768khz clock outputs that can be controlled
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
dt-bindings/clock/maxim,max77686.h.

The MAX77802 contains two 32.768khz clock outputs that can be controlled
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
dt-bindings/clock/maxim,max77802.h.

The MAX77686 contains one 32.768khz clock outputs that can be controlled
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
dt-bindings/clock/maxim,max77620.h.

Following properties should be presend in main device node of the MFD chip.

Required properties:

- #clock-cells: from common clock binding; shall be set to 1.

Optional properties:
- clock-output-names: From common clock binding.

Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Following indices are allowed:
    - 0: 32khz_ap clock (max77686, max77802), 32khz_out0 (max77620)
    - 1: 32khz_cp clock (max77686, max77802),
    - 2: 32khz_pmic clock (max77686).

Clocks are defined as preprocessor macros in above dt-binding header for
respective chips.

Example:

1. With MAX77686:

#include <dt-bindings/clock/maxim,max77686.h>
/* ... */

	Node of the MFD chip
		max77686: max77686@9 {
			compatible = "maxim,max77686";
			interrupt-parent = <&wakeup_eint>;
			interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
			reg = <0x09>;
			#clock-cells = <1>;

			/* ... */
		};

	Clock consumer node

		foo@0 {
			compatible = "bar,foo";
			/* ... */
			clock-names = "my-clock";
			clocks = <&max77686 MAX77686_CLK_PMIC>;
		};

2. With MAX77802:

#include <dt-bindings/clock/maxim,max77802.h>
/* ... */

	Node of the MFD chip
		max77802: max77802@9 {
			compatible = "maxim,max77802";
			interrupt-parent = <&wakeup_eint>;
			interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
			reg = <0x09>;
			#clock-cells = <1>;

			/* ... */
		};

	Clock consumer node

		foo@0 {
			compatible = "bar,foo";
			/* ... */
			clock-names = "my-clock";
			clocks = <&max77802 MAX77802_CLK_32K_AP>;
		};

3. With MAX77620:

#include <dt-bindings/clock/maxim,max77620.h>
/* ... */

	Node of the MFD chip
		max77620: max77620@3c {
			compatible = "maxim,max77620";
			reg = <0x3c>;
			#clock-cells = <1>;
			/* ... */
		};

	Clock consumer node

		foo@0 {
			compatible = "bar,foo";
			/* ... */
			clock-names = "my-clock";
			clocks = <&max77620 MAX77620_CLK_32K_OUT0>;
		};


code:
Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator

This device exposes 4 clocks in total:

- MAX9485_MCLKOUT: 	A gated, buffered output of the input clock of 27 MHz
- MAX9485_CLKOUT:	A PLL that can be configured to 16 different discrete
			frequencies
- MAX9485_CLKOUT[1,2]:	Two gated outputs for MAX9485_CLKOUT

MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
requests.

Required properties:
- compatible:	"maxim,max9485"
- clocks:	Input clock, must provice 27.000 MHz
- clock-names:	Must be set to "xclk"
- #clock-cells: From common clock binding; shall be set to 1

Optional properties:
- reset-gpios:		GPIO descriptor connected to the #RESET input pin
- vdd-supply:		A regulator node for Vdd
- clock-output-names:	Name of output clocks, as defined in common clock
			bindings

If not explicitly set, the output names are "mclkout", "clkout", "clkout1"
and "clkout2".

Clocks are defined as preprocessor macros in the dt-binding header.

Example:

	#include <dt-bindings/clock/maxim,max9485.h>

	xo-27mhz: xo-27mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
	};

	&i2c0 {
		max9485: audio-clock@63 {
			reg = <0x63>;
			compatible = "maxim,max9485";
			clock-names = "xclk";
			clocks = <&xo-27mhz>;
			reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
			vdd-supply = <&3v3-reg>;
			#clock-cells = <1>;
		};
	};

	// Clock consumer node

	foo@0 {
		compatible = "bar,foo";
		/* ... */
		clock-names = "foo-input-clk";
		clocks = <&max9485 MAX9485_CLKOUT1>;
	};