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code:
============================
 Core Driver Infrastructure
============================

GPU Hardware Structure
======================

Each ASIC is a collection of hardware blocks.  We refer to them as
"IPs" (Intellectual Property blocks).  Each IP encapsulates certain
functionality. IPs are versioned and can also be mixed and matched.
E.g., you might have two different ASICs that both have System DMA (SDMA) 5.x IPs.
The driver is arranged by IPs.  There are driver components to handle
the initialization and operation of each IP.  There are also a bunch
of smaller IPs that don't really need much if any driver interaction.
Those end up getting lumped into the common stuff in the soc files.
The soc files (e.g., vi.c, soc15.c nv.c) contain code for aspects of
the SoC itself rather than specific IPs.  E.g., things like GPU resets
and register access functions are SoC dependent.

An APU contains more than just CPU and GPU, it also contains all of
the platform stuff (audio, usb, gpio, etc.).  Also, a lot of
components are shared between the CPU, platform, and the GPU (e.g.,
SMU, PSP, etc.).  Specific components (CPU, GPU, etc.) usually have
their interface to interact with those common components.  For things
like S0i3 there is a ton of coordination required across all the
components, but that is probably a bit beyond the scope of this
section.

With respect to the GPU, we have the following major IPs:

GMC (Graphics Memory Controller)
    This was a dedicated IP on older pre-vega chips, but has since
    become somewhat decentralized on vega and newer chips.  They now
    have dedicated memory hubs for specific IPs or groups of IPs.  We
    still treat it as a single component in the driver however since
    the programming model is still pretty similar.  This is how the
    different IPs on the GPU get the memory (VRAM or system memory).
    It also provides the support for per process GPU virtual address
    spaces.

IH (Interrupt Handler)
    This is the interrupt controller on the GPU.  All of the IPs feed
    their interrupts into this IP and it aggregates them into a set of
    ring buffers that the driver can parse to handle interrupts from
    different IPs.

PSP (Platform Security Processor)
    This handles security policy for the SoC and executes trusted
    applications, and validates and loads firmwares for other blocks.

SMU (System Management Unit)
    This is the power management microcontroller.  It manages the entire
    SoC.  The driver interacts with it to control power management
    features like clocks, voltages, power rails, etc.

DCN (Display Controller Next)
    This is the display controller.  It handles the display hardware.
    It is described in more details in :ref:`Display Core <amdgpu-display-core>`.

SDMA (System DMA)
    This is a multi-purpose DMA engine.  The kernel driver uses it for
    various things including paging and GPU page table updates.  It's also
    exposed to userspace for use by user mode drivers (OpenGL, Vulkan,
    etc.)

GC (Graphics and Compute)
    This is the graphics and compute engine, i.e., the block that
    encompasses the 3D pipeline and and shader blocks.  This is by far the
    largest block on the GPU.  The 3D pipeline has tons of sub-blocks.  In
    addition to that, it also contains the CP microcontrollers (ME, PFP,
    CE, MEC) and the RLC microcontroller.  It's exposed to userspace for
    user mode drivers (OpenGL, Vulkan, OpenCL, etc.)

VCN (Video Core Next)
    This is the multi-media engine.  It handles video and image encode and
    decode.  It's exposed to userspace for user mode drivers (VA-API,
    OpenMAX, etc.)

Graphics and Compute Microcontrollers
-------------------------------------

CP (Command Processor)
    The name for the hardware block that encompasses the front end of the
    GFX/Compute pipeline.  Consists mainly of a bunch of microcontrollers
    (PFP, ME, CE, MEC).  The firmware that runs on these microcontrollers
    provides the driver interface to interact with the GFX/Compute engine.

    MEC (MicroEngine Compute)
        This is the microcontroller that controls the compute queues on the
        GFX/compute engine.

    MES (MicroEngine Scheduler)
        This is a new engine for managing queues.  This is currently unused.

RLC (RunList Controller)
    This is another microcontroller in the GFX/Compute engine.  It handles
    power management related functionality within the GFX/Compute engine.
    The name is a vestige of old hardware where it was originally added
    and doesn't really have much relation to what the engine does now.

Driver Structure
================

In general, the driver has a list of all of the IPs on a particular
SoC and for things like init/fini/suspend/resume, more or less just
walks the list and handles each IP.

Some useful constructs:

KIQ (Kernel Interface Queue)
    This is a control queue used by the kernel driver to manage other gfx
    and compute queues on the GFX/compute engine.  You can use it to
    map/unmap additional queues, etc.

IB (Indirect Buffer)
    A command buffer for a particular engine.  Rather than writing
    commands directly to the queue, you can write the commands into a
    piece of memory and then put a pointer to the memory into the queue.
    The hardware will then follow the pointer and execute the commands in
    the memory, then returning to the rest of the commands in the ring.

.. _amdgpu_memory_domains:

Memory Domains
==============

.. kernel-doc:: include/uapi/drm/amdgpu_drm.h
   :doc: memory domains

Buffer Objects
==============

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
   :doc: amdgpu_object

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
   :internal:

PRIME Buffer Sharing
====================

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
   :doc: PRIME Buffer Sharing

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
   :internal:

MMU Notifier
============

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
   :doc: MMU Notifier

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c
   :internal:

AMDGPU Virtual Memory
=====================

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
   :doc: GPUVM

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
   :internal:

Interrupt Handling
==================

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
   :doc: Interrupt Handling

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
   :internal:

IP Blocks
=========

.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h
   :doc: IP Blocks

.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h
   :identifiers: amd_ip_block_type amd_ip_funcs


code:
================================
 Misc AMDGPU driver information
================================

GPU Product Information
=======================

Information about the GPU can be obtained on certain cards
via sysfs

product_name
------------

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
   :doc: product_name

product_number
--------------

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
   :doc: product_name

serial_number
-------------

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
   :doc: serial_number

unique_id
---------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: unique_id

Accelerated Processing Units (APU) Info
---------------------------------------

.. csv-table::
   :header-rows: 1
   :widths: 3, 2, 2, 1, 1, 1
   :file: ./apu-asic-info-table.csv

Discrete GPU Info
-----------------

.. csv-table::
   :header-rows: 1
   :widths: 3, 2, 2, 1, 1, 1
   :file: ./dgpu-asic-info-table.csv

GPU Memory Usage Information
============================

Various memory accounting can be accessed via sysfs

mem_info_vram_total
-------------------

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
   :doc: mem_info_vram_total

mem_info_vram_used
------------------

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
   :doc: mem_info_vram_used

mem_info_vis_vram_total
-----------------------

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
   :doc: mem_info_vis_vram_total

mem_info_vis_vram_used
----------------------

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
   :doc: mem_info_vis_vram_used

mem_info_gtt_total
------------------

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
   :doc: mem_info_gtt_total

mem_info_gtt_used
-----------------

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
   :doc: mem_info_gtt_used

PCIe Accounting Information
===========================

pcie_bw
-------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: pcie_bw

pcie_replay_count
-----------------

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
   :doc: pcie_replay_count

GPU SmartShift Information
==========================

GPU SmartShift information via sysfs

smartshift_apu_power
--------------------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: smartshift_apu_power

smartshift_dgpu_power
---------------------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: smartshift_dgpu_power

smartshift_bias
---------------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: smartshift_bias


code:
==========================
 drm/amdgpu AMDgpu driver
==========================

The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.

.. toctree::

   module-parameters
   driver-core
   display/index
   xgmi
   ras
   thermal
   driver-misc
   amdgpu-glossary


code:
===================
 Module Parameters
===================

The amdgpu driver supports the following module parameters:

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c


code:
====================
 AMDGPU RAS Support
====================

The AMDGPU RAS interfaces are exposed via sysfs (for informational queries) and
debugfs (for error injection).

RAS debugfs/sysfs Control and Error Injection Interfaces
========================================================

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
   :doc: AMDGPU RAS debugfs control interface

RAS Reboot Behavior for Unrecoverable Errors
============================================

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
   :doc: AMDGPU RAS Reboot Behavior for Unrecoverable Errors

RAS Error Count sysfs Interface
===============================

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
   :doc: AMDGPU RAS sysfs Error Count Interface

RAS EEPROM debugfs Interface
============================

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
   :doc: AMDGPU RAS debugfs EEPROM table reset interface

RAS VRAM Bad Pages sysfs Interface
==================================

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
   :doc: AMDGPU RAS sysfs gpu_vram_bad_pages Interface

Sample Code
===========
Sample code for testing error injection can be found here:
https://cgit.freedesktop.org/mesa/drm/tree/tests/amdgpu/ras_tests.c

This is part of the libdrm amdgpu unit tests which cover several areas of the GPU.
There are four sets of tests:

RAS Basic Test

The test verifies the RAS feature enabled status and makes sure the necessary sysfs and debugfs files
are present.

RAS Query Test

This test checks the RAS availability and enablement status for each supported IP block as well as
the error counts.

RAS Inject Test

This test injects errors for each IP.

RAS Disable Test

This test tests disabling of RAS features for each IP block.


code:
===========================================
 GPU Power/Thermal Controls and Monitoring
===========================================

HWMON Interfaces
================

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: hwmon

GPU sysfs Power State Interfaces
================================

GPU power controls are exposed via sysfs files.

power_dpm_state
---------------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: power_dpm_state

power_dpm_force_performance_level
---------------------------------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: power_dpm_force_performance_level

pp_table
--------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: pp_table

pp_od_clk_voltage
-----------------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: pp_od_clk_voltage

pp_dpm_*
--------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie

pp_power_profile_mode
---------------------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: pp_power_profile_mode

\*_busy_percent
---------------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: gpu_busy_percent

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: mem_busy_percent

gpu_metrics
-----------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
   :doc: gpu_metrics

GFXOFF
======

GFXOFF is a feature found in most recent GPUs that saves power at runtime. The
card's RLC (RunList Controller) firmware powers off the gfx engine
dynamically when there is no workload on gfx or compute pipes. GFXOFF is on by
default on supported GPUs.

Userspace can interact with GFXOFF through a debugfs interface (all values in
`uint32_t`, unless otherwise noted):

``amdgpu_gfxoff``
-----------------

Use it to enable/disable GFXOFF, and to check if it's current enabled/disabled::

  $ xxd -l1 -p /sys/kernel/debug/dri/0/amdgpu_gfxoff
  01

- Write 0 to disable it, and 1 to enable it.
- Read 0 means it's disabled, 1 it's enabled.

If it's enabled, that means that the GPU is free to enter into GFXOFF mode as
needed. Disabled means that it will never enter GFXOFF mode.

``amdgpu_gfxoff_status``
------------------------

Read it to check current GFXOFF's status of a GPU::

  $ xxd -l1 -p /sys/kernel/debug/dri/0/amdgpu_gfxoff_status
  02

- 0: GPU is in GFXOFF state, the gfx engine is powered down.
- 1: Transition out of GFXOFF state
- 2: Not in GFXOFF state
- 3: Transition into GFXOFF state

If GFXOFF is enabled, the value will be transitioning around [0, 3], always
getting into 0 when possible. When it's disabled, it's always at 2. Returns
``-EINVAL`` if it's not supported.

``amdgpu_gfxoff_count``
-----------------------

Read it to get the total GFXOFF entry count at the time of query since system
power-up. The value is an `uint64_t` type, however, due to firmware limitations,
it can currently overflow as an `uint32_t`. *Only supported in vangogh*

``amdgpu_gfxoff_residency``
---------------------------

Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop. Read it to
get average GFXOFF residency % multiplied by 100 during the last logging
interval. E.g. a value of 7854 means 78.54% of the time in the last logging
interval the GPU was in GFXOFF mode. *Only supported in vangogh*


code:
=====================
 AMDGPU XGMI Support
=====================

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c


code:
=================
Backlight support
=================

.. kernel-doc:: drivers/video/backlight/backlight.c
   :doc: overview

.. kernel-doc:: include/linux/backlight.h
   :internal:

.. kernel-doc:: drivers/video/backlight/backlight.c
   :export:


code:
=======================================================
 drm/bridge/dw-hdmi Synopsys DesignWare HDMI Controller
=======================================================

Synopsys DesignWare HDMI Controller
===================================

This section covers everything related to the Synopsys DesignWare HDMI
Controller implemented as a DRM bridge.

Supported Input Formats and Encodings
-------------------------------------

.. kernel-doc:: include/drm/bridge/dw_hdmi.h
   :doc: Supported input formats and encodings


code:
digraph T {
    /* Make sure our payloads are always drawn below the driver node */
    subgraph cluster_driver {
        fillcolor = grey;
        style = filled;
        driver -> {payload1, payload2} [dir=none];
    }

    /* Driver malloc references */
    edge [style=dashed];
    driver -> port1;
    driver -> port2;
    driver -> port3:e;
    driver -> port4;

    payload1:s -> port1:e;
    payload2:s -> port3:e;
    edge [style=""];

    subgraph cluster_topology {
        label="Topology Manager";
        labelloc=bottom;

        /* Topology references */
        mstb1 -> {port1, port2};
        port1 -> mstb2;
        port2 -> mstb3 -> {port3, port4};
        port3 -> mstb4;

        /* Malloc references */
        edge [style=dashed;dir=back];
        mstb1 -> {port1, port2};
        port1 -> mstb2;
        port2 -> mstb3 -> {port3, port4};
        port3 -> mstb4;
    }

    driver [label="DRM driver";style=filled;shape=box;fillcolor=lightblue];

    payload1 [label="Payload #1";style=filled;shape=box;fillcolor=lightblue];
    payload2 [label="Payload #2";style=filled;shape=box;fillcolor=lightblue];

    mstb1 [label="MSTB #1";style=filled;fillcolor=palegreen;shape=oval];
    mstb2 [label="MSTB #2";style=filled;fillcolor=palegreen;shape=oval];
    mstb3 [label="MSTB #3";style=filled;fillcolor=palegreen;shape=oval];
    mstb4 [label="MSTB #4";style=filled;fillcolor=palegreen;shape=oval];

    port1 [label="Port #1";shape=oval];
    port2 [label="Port #2";shape=oval];
    port3 [label="Port #3";shape=oval];
    port4 [label="Port #4";shape=oval];
}


code:
digraph T {
    /* Make sure our payloads are always drawn below the driver node */
    subgraph cluster_driver {
        fillcolor = grey;
        style = filled;
        driver -> {payload1, payload2} [dir=none];
    }

    /* Driver malloc references */
    edge [style=dashed];
    driver -> port1;
    driver -> port2;
    driver -> port3:e;
    driver -> port4 [color=red];

    payload1:s -> port1:e;
    payload2:s -> port3:e;
    edge [style=""];

    subgraph cluster_topology {
        label="Topology Manager";
        labelloc=bottom;

        /* Topology references */
        mstb1 -> {port1, port2};
        port1 -> mstb2;
        edge [color=red];
        port2 -> mstb3 -> {port3, port4};
        port3 -> mstb4;
        edge [color=""];

        /* Malloc references */
        edge [style=dashed;dir=back];
        mstb1 -> {port1, port2};
        port1 -> mstb2;
        port2 -> mstb3 -> port3;
        edge [color=red];
        mstb3 -> port4;
        port3 -> mstb4;
    }

    mstb1 [label="MSTB #1";style=filled;fillcolor=palegreen];
    mstb2 [label="MSTB #2";style=filled;fillcolor=palegreen];
    mstb3 [label="MSTB #3";style=filled;fillcolor=palegreen];
    mstb4 [label="MSTB #4";style=filled;fillcolor=grey];

    port1 [label="Port #1"];
    port2 [label="Port #2"];
    port3 [label="Port #3"];
    port4 [label="Port #4";style=filled;fillcolor=grey];

    driver [label="DRM driver";style=filled;shape=box;fillcolor=lightblue];

    payload1 [label="Payload #1";style=filled;shape=box;fillcolor=lightblue];
    payload2 [label="Payload #2";style=filled;shape=box;fillcolor=lightblue];
}


code:
digraph T {
    /* Make sure our payloads are always drawn below the driver node */
    subgraph cluster_driver {
        fillcolor = grey;
        style = filled;
        edge [dir=none];
        driver -> payload1;
        driver -> payload2 [penwidth=3];
        edge [dir=""];
    }

    /* Driver malloc references */
    edge [style=dashed];
    driver -> port1;
    driver -> port2;
    driver -> port3:e;
    driver -> port4 [color=grey];
    payload1:s -> port1:e;
    payload2:s -> port3:e [penwidth=3];
    edge [style=""];

    subgraph cluster_topology {
        label="Topology Manager";
        labelloc=bottom;

        /* Topology references */
        mstb1 -> {port1, port2};
        port1 -> mstb2;
        edge [color=grey];
        port2 -> mstb3 -> {port3, port4};
        port3 -> mstb4;
        edge [color=""];

        /* Malloc references */
        edge [style=dashed;dir=back];
        mstb1 -> {port1, port2};
        port1 -> mstb2;
        port2 -> mstb3 [penwidth=3];
        mstb3 -> port3 [penwidth=3];
        edge [color=grey];
        mstb3 -> port4;
        port3 -> mstb4;
    }

    mstb1 [label="MSTB #1";style=filled;fillcolor=palegreen];
    mstb2 [label="MSTB #2";style=filled;fillcolor=palegreen];
    mstb3 [label="MSTB #3";style=filled;fillcolor=palegreen;penwidth=3];
    mstb4 [label="MSTB #4";style=filled;fillcolor=grey];

    port1 [label="Port #1"];
    port2 [label="Port #2";penwidth=5];
    port3 [label="Port #3";penwidth=3];
    port4 [label="Port #4";style=filled;fillcolor=grey];

    driver [label="DRM driver";style=filled;shape=box;fillcolor=lightblue];

    payload1 [label="Payload #1";style=filled;shape=box;fillcolor=lightblue];
    payload2 [label="Payload #2";style=filled;shape=box;fillcolor=lightblue;penwidth=3];
}


code:
========================
GPU Driver Documentation
========================

.. toctree::

   amdgpu/index
   i915
   mcde
   meson
   pl111
   tegra
   tve200
   v3d
   vc4
   vkms
   bridge/dw-hdmi
   xen-front
   afbc
   komeda-kms

.. only::  subproject and html

   Indices
   =======

   * :ref:`genindex`


code:
=================
Kernel clients
=================

.. kernel-doc:: drivers/gpu/drm/drm_client.c
   :doc: overview

.. kernel-doc:: include/drm/drm_client.h
   :internal:

.. kernel-doc:: drivers/gpu/drm/drm_client.c
   :export:

.. kernel-doc:: drivers/gpu/drm/drm_client_modeset.c
   :export: