code:
* Atmel High Speed MultiMedia Card Interface

This controller on atmel products provides an interface for MMC, SD and SDIO
types of memory cards.

This file documents differences between the core properties described
by mmc.txt and the properties used by the atmel-mci driver.

1) MCI node

Required properties:
- compatible: should be "atmel,hsmci"
- #address-cells: should be one. The cell is the slot id.
- #size-cells: should be zero.
- at least one slot node
- clock-names: tuple listing input clock names.
	Required elements: "mci_clk"
- clocks: phandles to input clocks.

The node contains child nodes for each slot that the platform uses

Example MCI node:

mmc0: mmc@f0008000 {
	compatible = "atmel,hsmci";
	reg = <0xf0008000 0x600>;
	interrupts = <12 4>;
	#address-cells = <1>;
	#size-cells = <0>;
	clock-names = "mci_clk";
	clocks = <&mci0_clk>;

	[ child node definitions...]
};

2) slot nodes

Required properties:
- reg: should contain the slot id.
- bus-width: number of data lines connected to the controller

Optional properties:
- cd-gpios: specify GPIOs for card detection
- cd-inverted: invert the value of external card detect gpio line
- wp-gpios: specify GPIOs for write protection

Example slot node:

slot@0 {
	reg = <0>;
	bus-width = <4>;
	cd-gpios = <&pioD 15 0>
	cd-inverted;
};

Example full MCI node:
mmc0: mmc@f0008000 {
	compatible = "atmel,hsmci";
	reg = <0xf0008000 0x600>;
	interrupts = <12 4>;
	#address-cells = <1>;
	#size-cells = <0>;
	slot@0 {
		reg = <0>;
		bus-width = <4>;
		cd-gpios = <&pioD 15 0>
		cd-inverted;
	};
	slot@1 {
		reg = <1>;
		bus-width = <4>;
	};
};


code:
* Mellanox Bluefield SoC specific extensions to the Synopsys Designware
  Mobile Storage Host Controller

Read synopsys-dw-mshc.txt for more details

The Synopsys designware mobile storage host controller is used to interface
a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
differences between the core Synopsys dw mshc controller properties described
by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
specific extensions to the Synopsys Designware Mobile Storage Host Controller.

Required Properties:

* compatible: should be one of the following.
  - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
    specific extensions.

Example:

	/* Mellanox Bluefield SoC MMC */
	mmc@6008000 {
		compatible = "mellanox,bluefield-dw-mshc";
		reg = <0x6008000 0x400>;
		interrupts = <32>;
		fifo-depth = <0x100>;
		clock-frequency = <24000000>;
		bus-width = <8>;
		cap-mmc-highspeed;
	};

repo_name: angery/linux


code:
Broadcom BCM2835 SDHOST controller

This file documents differences between the core properties described
by mmc.txt and the properties that represent the BCM2835 controller.

Required properties:
- compatible: Should be "brcm,bcm2835-sdhost".
- clocks: The clock feeding the SDHOST controller.

Optional properties:
- dmas: DMA channel for read and write.
          See Documentation/devicetree/bindings/dma/dma.txt for details

Example:

sdhost: mmc@7e202000 {
	compatible = "brcm,bcm2835-sdhost";
	reg = <0x7e202000 0x100>;
	interrupts = <2 24>;
	clocks = <&clocks BCM2835_CLOCK_VPU>;
	dmas = <&dma 13>;
	dma-names = "rx-tx";
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/brcm,iproc-sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom IPROC SDHCI controller

maintainers:
  - Ray Jui <ray.jui@broadcom.com>
  - Scott Branden <scott.branden@broadcom.com>
  - Nicolas Saenz Julienne <nsaenz@kernel.org>

allOf:
  - $ref: mmc-controller.yaml#

properties:
  compatible:
    enum:
      - brcm,bcm2835-sdhci
      - brcm,bcm2711-emmc2
      - brcm,sdhci-iproc-cygnus
      - brcm,sdhci-iproc
      - brcm,bcm7211a0-sdhci

  reg:
    minItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1
    description:
      Handle to core clock for the sdhci controller.

  sdhci,auto-cmd12:
    type: boolean
    description: Specifies that controller should use auto CMD12

required:
  - compatible
  - reg
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/bcm-cygnus.h>

    mmc@18041000 {
      compatible = "brcm,sdhci-iproc-cygnus";
      reg = <0x18041000 0x100>;
      interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&lcpll0_clks BCM_CYGNUS_LCPLL0_SDIO_CLK>;
      bus-width = <4>;
      sdhci,auto-cmd12;
      no-1-8-v;
    };
...


code:
Broadcom BCM281xx SDHCI

This file documents differences between the core properties in mmc.txt
and the properties present in the bcm281xx SDHCI

Required properties:
- compatible : Should be "brcm,kona-sdhci"
- DEPRECATED: compatible : Should be "bcm,kona-sdhci"
- clocks: phandle + clock specifier pair of the external clock

Refer to clocks/clock-bindings.txt for generic clock consumer properties.

Example:

sdio2: sdio@3f1a0000 {
	compatible = "brcm,kona-sdhci";
	reg = <0x3f1a0000 0x10000>;
	clocks = <&sdio3_clk>;
	interrupts = <0x0 74 0x4>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BRCMSTB/BMIPS SDHCI Controller binding

maintainers:
  - Al Cooper <alcooperx@gmail.com>
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - brcm,bcm7216-sdhci
          - const: brcm,bcm7445-sdhci
          - const: brcm,sdhci-brcmstb
      - items:
          - enum:
              - brcm,bcm7445-sdhci
          - const: brcm,sdhci-brcmstb
      - items:
          - enum:
              - brcm,bcm7425-sdhci
          - const: brcm,sdhci-brcmstb

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: host
      - const: cfg

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: handle to core clock for the sdhci controller
      - description: handle to improved 150Mhz clock for sdhci controller (Optional clock)

  clock-names:
    minItems: 1
    items:
      - const: sw_sdio
      - const: sdio_freq # Optional clock

  clock-frequency:
    description:
      Maximum operating frequency of sdio_freq sdhci controller clock
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 100000000
    maximum: 150000000

  sdhci,auto-cmd12:
    type: boolean
    description: Specifies that controller should use auto CMD12

allOf:
  - $ref: mmc-controller.yaml#
  - if:
      properties:
        clock-names:
          contains:
            const: sdio_freq

    then:
      required:
        - clock-frequency

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    mmc@84b0000 {
      compatible = "brcm,bcm7216-sdhci",
                   "brcm,bcm7445-sdhci",
                   "brcm,sdhci-brcmstb";
      reg = <0x84b0000 0x260>, <0x84b0300 0x200>;
      reg-names = "host", "cfg";
      sd-uhs-sdr50;
      sd-uhs-ddr50;
      sd-uhs-sdr104;
      sdhci,auto-cmd12;
      interrupts = <0x0 0x26 0x4>;
      clocks = <&scmi_clk 245>;
      clock-names = "sw_sdio";
    };

    mmc@84b1000 {
      compatible = "brcm,bcm7216-sdhci",
                   "brcm,bcm7445-sdhci",
                   "brcm,sdhci-brcmstb";
      reg = <0x84b1000 0x260>, <0x84b1300 0x200>;
      reg-names = "host", "cfg";
      mmc-ddr-1_8v;
      mmc-hs200-1_8v;
      mmc-hs400-1_8v;
      mmc-hs400-enhanced-strobe;
      supports-cqe;
      non-removable;
      bus-width = <0x8>;
      interrupts = <0x0 0x27 0x4>;
      clocks = <&scmi_clk 245>;
      clock-names = "sw_sdio";
    };


code:
* Cavium Octeon & ThunderX MMC controller

The highspeed MMC host controller on Caviums SoCs provides an interface
for MMC and SD types of memory cards.

Supported maximum speeds are the ones of the eMMC standard 4.41 as well
as the speed of SD standard 4.0. Only 3.3 Volt is supported.

Required properties:
 - compatible : should be one of:
   cavium,octeon-6130-mmc
   cavium,octeon-7890-mmc
   cavium,thunder-8190-mmc
   cavium,thunder-8390-mmc
   mmc-slot
 - reg : mmc controller base registers
 - clocks : phandle

Optional properties:
 - for cd, bus-width and additional generic mmc parameters
   please refer to mmc.txt within this directory
 - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command
 - cavium,dat-clk-skew : number of coprocessor clocks before sampling data

Deprecated properties:
- spi-max-frequency : use max-frequency instead
- cavium,bus-max-width : use bus-width instead
- power-gpios : use vmmc-supply instead
- cavium,octeon-6130-mmc-slot : use mmc-slot instead

Examples:
	mmc_1_4: mmc@1,4 {
		compatible = "cavium,thunder-8390-mmc";
		reg = <0x0c00 0 0 0 0>;	/* DEVFN = 0x0c (1:4) */
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&sclk>;

		mmc-slot@0 {
			compatible = "mmc-slot";
			reg = <0>;
			vmmc-supply = <&mmc_supply_3v3>;
			max-frequency = <42000000>;
			bus-width = <4>;
			cap-sd-highspeed;
		};

		mmc-slot@1 {
			compatible = "mmc-slot";
			reg = <1>;
			vmmc-supply = <&mmc_supply_3v3>;
			max-frequency = <42000000>;
			bus-width = <8>;
			cap-mmc-highspeed;
			non-removable;
		};
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

allOf:
  - $ref: mmc-controller.yaml

properties:
  compatible:
    items:
      - enum:
          - microchip,mpfs-sd4hc
          - socionext,uniphier-sd4hc
      - const: cdns,sd4hc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  # PHY DLL input delays:
  # They are used to delay the data valid window, and align the window to
  # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
  # and it is increased by 2.5ns in each step.

  cdns,phy-input-delay-sd-highspeed:
    description: Value of the delay in the input path for SD high-speed timing
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 0x1f

  cdns,phy-input-delay-legacy:
    description: Value of the delay in the input path for legacy timing
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 0x1f

  cdns,phy-input-delay-sd-uhs-sdr12:
    description: Value of the delay in the input path for SD UHS SDR12 timing
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 0x1f

  cdns,phy-input-delay-sd-uhs-sdr25:
    description: Value of the delay in the input path for SD UHS SDR25 timing
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 0x1f

  cdns,phy-input-delay-sd-uhs-sdr50:
    description: Value of the delay in the input path for SD UHS SDR50 timing
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 0x1f

  cdns,phy-input-delay-sd-uhs-ddr50:
    description: Value of the delay in the input path for SD UHS DDR50 timing
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 0x1f

  cdns,phy-input-delay-mmc-highspeed:
    description: Value of the delay in the input path for MMC high-speed timing
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 0x1f

  cdns,phy-input-delay-mmc-ddr:
    description: Value of the delay in the input path for eMMC high-speed DDR timing

  # PHY DLL clock delays:
  # Each delay property represents the fraction of the clock period.
  # The approximate delay value will be
  # (<delay property value>/128)*sdmclk_clock_period.
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 0x1f

  cdns,phy-dll-delay-sdclk:
    description: |
      Value of the delay introduced on the sdclk output for all modes except
      HS200, HS400 and HS400_ES.
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 0x7f

  cdns,phy-dll-delay-sdclk-hsmmc:
    description: |
      Value of the delay introduced on the sdclk output for HS200, HS400 and
      HS400_ES speed modes.
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 0x7f

  cdns,phy-dll-delay-strobe:
    description: |
      Value of the delay introduced on the dat_strobe input used in
      HS400 / HS400_ES speed modes.
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 0x7f

required:
  - compatible
  - reg
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    emmc: mmc@5a000000 {
        compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
        reg = <0x5a000000 0x400>;
        interrupts = <0 78 4>;
        clocks = <&clk 4>;
        bus-width = <8>;
        mmc-ddr-1_8v;
        mmc-hs200-1_8v;
        mmc-hs400-1_8v;
        cdns,phy-dll-delay-sdclk = <0>;
    };


code:
* TI Highspeed MMC host controller for DaVinci

The Highspeed MMC Host Controller on TI DaVinci family
provides an interface for MMC, SD and SDIO types of memory cards.

This file documents the properties used by the davinci_mmc driver.

Required properties:
- compatible:
 Should be "ti,da830-mmc": for da830, da850, dm365
 Should be "ti,dm355-mmc": for dm355, dm644x

Optional properties:
- bus-width: Number of data lines, can be <1>, <4>, or <8>, default <1>
- max-frequency: Maximum operating clock frequency, default 25MHz.
- dmas: List of DMA specifiers with the controller specific format
	as described in the generic DMA client binding. A tx and rx
	specifier is required.
- dma-names: RX and TX  DMA request names. These strings correspond
	1:1 with the DMA specifiers listed in dmas.

Example:
mmc0: mmc@1c40000 {
	compatible = "ti,da830-mmc",
	reg = <0x40000 0x1000>;
	interrupts = <16>;
	bus-width = <4>;
	max-frequency = <50000000>;
	dmas = <&edma 16
		&edma 17>;
	dma-names = "rx", "tx";
};


code:
* Freescale Enhanced Secure Digital Host Controller (eSDHC)

The Enhanced Secure Digital Host Controller provides an interface
for MMC, SD, and SDIO types of memory cards.

This file documents differences between the core properties described
by mmc.txt and the properties used by the sdhci-esdhc driver.

Required properties:
  - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
    Possible compatibles for PowerPC:
	"fsl,mpc8536-esdhc"
	"fsl,mpc8378-esdhc"
	"fsl,p2020-esdhc"
	"fsl,p4080-esdhc"
	"fsl,t1040-esdhc"
	"fsl,t4240-esdhc"
    Possible compatibles for ARM:
	"fsl,ls1012a-esdhc"
	"fsl,ls1028a-esdhc"
	"fsl,ls1088a-esdhc"
	"fsl,ls1043a-esdhc"
	"fsl,ls1046a-esdhc"
	"fsl,ls2080a-esdhc"
  - clock-frequency : specifies eSDHC base clock frequency.

Optional properties:
  - sdhci,wp-inverted : specifies that eSDHC controller reports
    inverted write-protect state; New devices should use the generic
    "wp-inverted" property.
  - sdhci,1-bit-only : specifies that a controller can only handle
    1-bit data transfers. New devices should use the generic
    "bus-width = <1>" property.
  - sdhci,auto-cmd12: specifies that a controller can only handle auto
    CMD12.
  - voltage-ranges : two cells are required, first cell specifies minimum
    slot voltage (mV), second cell specifies maximum slot voltage (mV).
    Several ranges could be specified.
  - little-endian : If the host controller is little-endian mode, specify
    this property. The default endian mode is big-endian.

Example:

sdhci@2e000 {
	compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
	reg = <0x2e000 0x1000>;
	interrupts = <42 0x8>;
	interrupt-parent = <&ipic>;
	/* Filled in by U-Boot */
	clock-frequency = <0>;
	voltage-ranges = <3300 3300>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX

maintainers:
  - Shawn Guo <shawnguo@kernel.org>

allOf:
  - $ref: "mmc-controller.yaml"

description: |
  The Enhanced Secure Digital Host Controller on Freescale i.MX family
  provides an interface for MMC, SD, and SDIO types of memory cards.

  This file documents differences between the core properties described
  by mmc.txt and the properties used by the sdhci-esdhc-imx driver.

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx25-esdhc
          - fsl,imx35-esdhc
          - fsl,imx51-esdhc
          - fsl,imx53-esdhc
          - fsl,imx6q-usdhc
          - fsl,imx6sl-usdhc
          - fsl,imx6sll-usdhc
          - fsl,imx6sx-usdhc
          - fsl,imx6ull-usdhc
          - fsl,imx7d-usdhc
          - fsl,imx7ulp-usdhc
          - fsl,imx8mm-usdhc
          - fsl,imxrt1050-usdhc
          - nxp,s32g2-usdhc
      - items:
          - enum:
              - fsl,imx8mq-usdhc
          - const: fsl,imx7d-usdhc
      - items:
          - enum:
              - fsl,imx8mn-usdhc
              - fsl,imx8mp-usdhc
              - fsl,imx93-usdhc
              - fsl,imx8ulp-usdhc
          - const: fsl,imx8mm-usdhc
      - items:
          - enum:
              - fsl,imx8dxl-usdhc
              - fsl,imx8qm-usdhc
          - const: fsl,imx8qxp-usdhc
      - items:
          - enum:
              - fsl,imx8mm-usdhc
              - fsl,imx8mn-usdhc
              - fsl,imx8mp-usdhc
              - fsl,imx8qm-usdhc
              - fsl,imx8qxp-usdhc
          - const: fsl,imx7d-usdhc
        deprecated: true
      - items:
          - enum:
              - fsl,imx8mn-usdhc
              - fsl,imx8mp-usdhc
          - const: fsl,imx8mm-usdhc
          - const: fsl,imx7d-usdhc
        deprecated: true
      - items:
          - enum:
              - fsl,imx8dxl-usdhc
              - fsl,imx8qm-usdhc
          - const: fsl,imx8qxp-usdhc
          - const: fsl,imx7d-usdhc
        deprecated: true
      - items:
          - enum:
              - fsl,imxrt1170-usdhc
          - const: fsl,imxrt1050-usdhc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  fsl,wp-controller:
    description: |
      boolean, if present, indicate to use controller internal write protection.
    type: boolean

  fsl,delay-line:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Specify the number of delay cells for override mode.
      This is used to set the clock delay for DLL(Delay Line) on override mode
      to select a proper data sampling window in case the clock quality is not good
      due to signal path is too long on the board. Please refer to eSDHC/uSDHC
      chapter, DLL (Delay Line) section in RM for details.
    default: 0

  voltage-ranges:
    $ref: '/schemas/types.yaml#/definitions/uint32-matrix'
    description: |
      Specify the voltage range in case there are software transparent level
      shifters on the outputs of the controller. Two cells are required, first
      cell specifies minimum slot voltage (mV), second cell specifies maximum
      slot voltage (mV).
    items:
      items:
        - description: value for minimum slot voltage
        - description: value for maximum slot voltage
    maxItems: 1

  fsl,tuning-start-tap:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Specify the start delay cell point when send first CMD19 in tuning procedure.
    default: 0

  fsl,tuning-step:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Specify the increasing delay cell steps in tuning procedure.
      The uSDHC use one delay cell as default increasing step to do tuning process.
      This property allows user to change the tuning step to more than one delay
      cells which is useful for some special boards or cards when the default
      tuning step can't find the proper delay window within limited tuning retries.
    default: 0

  fsl,strobe-dll-delay-target:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Specify the strobe dll control slave delay target.
      This delay target programming host controller loopback read clock, and this
      property allows user to change the delay target for the strobe input read clock.
      If not use this property, driver default set the delay target to value 7.
      Only eMMC HS400 mode need to take care of this property.
    default: 0

  clocks:
    maxItems: 3
    description:
      Handle clocks for the sdhc controller.

  clock-names:
    items:
      - const: ipg
      - const: ahb
      - const: per

  power-domains:
    maxItems: 1

  pinctrl-names:
    oneOf:
      - minItems: 3
        items:
          - const: default
          - const: state_100mhz
          - const: state_200mhz
          - const: sleep
      - minItems: 1
        items:
          - const: default
          - const: sleep

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    mmc@70004000 {
        compatible = "fsl,imx51-esdhc";
        reg = <0x70004000 0x4000>;
        interrupts = <1>;
        fsl,wp-controller;
    };

    mmc@70008000 {
        compatible = "fsl,imx51-esdhc";
        reg = <0x70008000 0x4000>;
        interrupts = <2>;
        cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
        wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/fsl-imx-mmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Secure Digital Host Controller for i.MX2/3 series

maintainers:
  - Markus Pargmann <mpa@pengutronix.de>

allOf:
  - $ref: "mmc-controller.yaml"

properties:
  compatible:
    oneOf:
      - const: fsl,imx21-mmc
      - const: fsl,imx31-mmc
      - items:
          - const: fsl,imx27-mmc
          - const: fsl,imx21-mmc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  dmas:
    maxItems: 1

  dma-names:
    const: rx-tx

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    mmc@10014000 {
        compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
        reg = <0x10014000 0x1000>;
        interrupts = <11>;
        dmas = <&dma 7>;
        dma-names = "rx-tx";
        bus-width = <4>;
        cd-gpios = <&gpio3 29>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/fujitsu,sdhci-fujitsu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Fujitsu/Socionext SDHCI controller (F_SDH30)

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

allOf:
  - $ref: mmc-controller.yaml#

properties:
  compatible:
    enum:
      - fujitsu,mb86s70-sdhci-3.0
      - socionext,f-sdh30-e51-mmc

  reg:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: iface
      - const: core

  resets:
    maxItems: 1

  fujitsu,cmd-dat-delay-select:
    type: boolean
    description: |
      Indicating that this host requires the CMD_DAT_DELAY control to be enabled

unevaluatedProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names

examples:
  - |
    sdhci1: mmc@36600000 {
        compatible = "fujitsu,mb86s70-sdhci-3.0";
        reg = <0x36600000 0x1000>;
        bus-width = <4>;
        vqmmc-supply = <&vccq_sdhci1>;
        clocks = <&clock 2 2 0>, <&clock 2 3 0>;
        clock-names = "iface", "core";
    };


code:
* Hisilicon Hi3798CV200 specific extensions to the Synopsys Designware Mobile
  Storage Host Controller

Read synopsys-dw-mshc.txt for more details

The Synopsys designware mobile storage host controller is used to interface
a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
differences between the core Synopsys dw mshc controller properties described
by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200
specific extensions to the Synopsys Designware Mobile Storage Host Controller.

Required Properties:
- compatible: Should contain "hisilicon,hi3798cv200-dw-mshc".
- clocks: A list of phandle + clock-specifier pairs for the clocks listed
  in clock-names.
- clock-names: Should contain the following:
	"ciu" - The ciu clock described in synopsys-dw-mshc.txt.
	"biu" - The biu clock described in synopsys-dw-mshc.txt.
	"ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
	"ciu-drive"  - Hi3798CV200 extended phase clock for ciu driving.

Example:

	emmc: mmc@9830000 {
		compatible = "hisilicon,hi3798cv200-dw-mshc";
		reg = <0x9830000 0x10000>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&crg HISTB_MMC_CIU_CLK>,
			 <&crg HISTB_MMC_BIU_CLK>,
			 <&crg HISTB_MMC_SAMPLE_CLK>,
			 <&crg HISTB_MMC_DRV_CLK>;
		clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
		fifo-depth = <256>;
		clock-frequency = <200000000>;
		cap-mmc-highspeed;
		mmc-ddr-1_8v;
		mmc-hs200-1_8v;
		non-removable;
		bus-width = <8>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/ingenic,mmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs MMC Controller DT bindings

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

allOf:
  - $ref: mmc-controller.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - ingenic,jz4740-mmc
          - ingenic,jz4725b-mmc
          - ingenic,jz4760-mmc
          - ingenic,jz4775-mmc
          - ingenic,jz4780-mmc
          - ingenic,x1000-mmc
      - items:
          - const: ingenic,jz4770-mmc
          - const: ingenic,jz4760-mmc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: mmc

  dmas:
    minItems: 1
    maxItems: 2

  dma-names:
    oneOf:
      - items:
          - const: rx
          - const: tx
      - const: tx-rx

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - dmas
  - dma-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
    #include <dt-bindings/dma/jz4780-dma.h>
    mmc0: mmc@13450000 {
      compatible = "ingenic,jz4780-mmc";
      reg = <0x13450000 0x1000>;

      interrupt-parent = <&intc>;
      interrupts = <37>;

      clocks = <&cgu JZ4780_CLK_MSC0>;
      clock-names = "mmc";

      cap-sd-highspeed;
      cap-mmc-highspeed;
      cap-sdio-irq;
      dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>,
             <&dma JZ4780_DMA_MSC0_TX 0xffffffff>;
      dma-names = "rx", "tx";
    };
  - |
    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
    #include <dt-bindings/dma/jz4780-dma.h>
    /*
     * Alternative version of the example above,
     * but using one single DMA channel for both
     * TX and RX.
     */
    mmc1: mmc@13460000 {
      compatible = "ingenic,jz4780-mmc";
      reg = <0x13460000 0x1000>;

      interrupt-parent = <&intc>;
      interrupts = <36>;

      clocks = <&cgu JZ4780_CLK_MSC1>;
      clock-names = "mmc";

      cap-sd-highspeed;
      cap-mmc-highspeed;
      cap-sdio-irq;
      dmas = <&dma JZ4780_DMA_MSC1_TX JZ4780_DMA_MSC1_RX 0xffffffff>;
      dma-names = "tx-rx";
    };


code:
* Hisilicon specific extensions to the Synopsys Designware Mobile
  Storage Host Controller

Read synopsys-dw-mshc.txt for more details

The Synopsys designware mobile storage host controller is used to interface
a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
differences between the core Synopsys dw mshc controller properties described
by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
extensions to the Synopsys Designware Mobile Storage Host Controller.

Required Properties:

* compatible: should be one of the following.
  - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
  - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
     with hi3670 specific extensions.
  - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
  - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.

Optional Properties:
- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.

Example:

	/* for Hi3620 */

	/* SoC portion */
	dwmmc_0: dwmmc0@fcd03000 {
		compatible = "hisilicon,hi4511-dw-mshc";
		reg = <0xfcd03000 0x1000>;
		interrupts = <0 16 4>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mmc_clock HI3620_SD_CIUCLK>, <&clock HI3620_DDRC_PER_CLK>;
		clock-names = "ciu", "biu";
	};

	/* Board portion */
	dwmmc0@fcd03000 {
		vmmc-supply = <&ldo12>;
		fifo-depth = <0x100>;
		pinctrl-names = "default";
		pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>;
		bus-width = <4>;
		disable-wp;
		cd-gpios = <&gpio10 3 0>;
		cap-mmc-highspeed;
		cap-sd-highspeed;
	};

	/* for Hi6220 */

	dwmmc_1: dwmmc1@f723e000 {
		compatible = "hisilicon,hi6220-dw-mshc";
		bus-width = <0x4>;
		disable-wp;
		cap-sd-highspeed;
		sd-uhs-sdr12;
		sd-uhs-sdr25;
		card-detect-delay = <200>;
		hisilicon,peripheral-syscon = <&ao_ctrl>;
		reg = <0x0 0xf723e000 0x0 0x1000>;
		interrupts = <0x0 0x49 0x4>;
		clocks = <&clock_sys HI6220_MMC1_CIUCLK>, <&clock_sys HI6220_MMC1_CLK>;
		clock-names = "ciu", "biu";
		cd-gpios = <&gpio1 0 1>;
		pinctrl-names = "default", "idle";
		pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
		pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
		vqmmc-supply = <&ldo7>;
		vmmc-supply = <&ldo10>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/litex,mmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LiteX LiteSDCard device

maintainers:
  - Gabriel Somlo <gsomlo@gmail.com>

description: |
  LiteSDCard is a small footprint, configurable SDCard core for FPGA based
  system on chips.

  The hardware source is Open Source and can be found on at
  https://github.com/enjoy-digital/litesdcard/.

allOf:
  - $ref: mmc-controller.yaml#

properties:
  compatible:
    const: litex,mmc

  reg:
    items:
      - description: PHY registers
      - description: CORE registers
      - description: DMA Reader buffer
      - description: DMA Writer buffer
      - description: IRQ registers
    minItems: 4

  reg-names:
    items:
      - const: phy
      - const: core
      - const: reader
      - const: writer
      - const: irq
    minItems: 4

  clocks:
    maxItems: 1
    description:
      Handle to reference clock.

  vmmc-supply:
    description:
      Handle to fixed-voltage supply for the card power.

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - vmmc-supply

additionalProperties: false

examples:
  - |
    mmc: mmc@12005000 {
        compatible = "litex,mmc";
        reg = <0x12005000 0x100>,
              <0x12003800 0x100>,
              <0x12003000 0x100>,
              <0x12004800 0x100>,
              <0x12004000 0x100>;
        reg-names = "phy", "core", "reader", "writer", "irq";
        clocks = <&reference_clk>;
        vmmc-supply = <&vreg_mmc>;
        interrupts = <4>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/marvell,dove-sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell sdhci-dove controller

maintainers:
  - Adrian Hunter <adrian.hunter@intel.com>
  - Ulf Hansson <ulf.hansson@linaro.org>

allOf:
  - $ref: mmc-controller.yaml#

properties:
  compatible:
    const: marvell,dove-sdhci

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 2

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    sdio0: mmc@92000 {
      compatible = "marvell,dove-sdhci";
      reg = <0x92000 0x100>;
      interrupts = <35>;
      clocks = <&gate_clk 9>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/marvell,orion-sdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell orion-sdio controller

maintainers:
  - Nicolas Pitre <nico@fluxnic.net>
  - Ulf Hansson <ulf.hansson@linaro.org>

allOf:
  - $ref: mmc-controller.yaml#

properties:
  compatible:
    const: marvell,orion-sdio

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    mmc@d00d4000 {
      compatible = "marvell,orion-sdio";
      reg = <0xd00d4000 0x200>;
      interrupts = <54>;
      clocks = <&gateclk 17>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell Xenon SDHCI Controller

description: |
  This file documents differences between the core MMC properties described by
  mmc-controller.yaml and the properties used by the Xenon implementation.

  Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
  Each SDHC is independent and owns independent resources, such as register
  sets, clock and PHY.

  Each SDHC should have an independent device tree node.

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

properties:
  compatible:
    oneOf:
      - enum:
          - marvell,armada-cp110-sdhci
          - marvell,armada-ap806-sdhci

      - items:
          - const: marvell,armada-ap807-sdhci
          - const: marvell,armada-ap806-sdhci

      - items:
          - const: marvell,armada-3700-sdhci
          - const: marvell,sdhci-xenon

  reg:
    minItems: 1
    maxItems: 2
    description: |
      For "marvell,armada-3700-sdhci", two register areas.  The first one
      for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
      Voltage Control register.  Please follow the examples with compatible
      "marvell,armada-3700-sdhci" in below.
      Please also check property marvell,pad-type in below.

      For other compatible strings, one register area for Xenon IP.

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: core
      - const: axi

  interrupts:
    maxItems: 1

  marvell,xenon-sdhc-id:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 7
    description: |
      Indicate the corresponding bit index of current SDHC in SDHC System
      Operation Control Register Bit[7:0].  Set/clear the corresponding bit to
      enable/disable current SDHC.

  marvell,xenon-phy-type:
    $ref: /schemas/types.yaml#/definitions/string
    enum:
      - "emmc 5.1 phy"
      - "emmc 5.0 phy"
    description: |
      Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
      marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
      choice if this property is not provided.  To select eMMC 5.0 PHY, set:
      marvell,xenon-phy-type = "emmc 5.0 phy"

      All those types of PHYs can support eMMC, SD and SDIO. Please note that
      this property only presents the type of PHY.  It doesn't stand for the
      entire SDHC type or property.  For example, "emmc 5.1 phy" doesn't mean
      that this Xenon SDHC only supports eMMC 5.1.

  marvell,xenon-phy-znr:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f
    default: 0xf
    description: |
      Set PHY ZNR value.
      Only available for eMMC PHY.

  marvell,xenon-phy-zpr:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f
    default: 0xf
    description: |
      Set PHY ZPR value.
      Only available for eMMC PHY.

  marvell,xenon-phy-nr-success-tun:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 7
    default: 0x4
    description: |
      Set the number of required consecutive successful sampling points
      used to identify a valid sampling window, in tuning process.

  marvell,xenon-phy-tun-step-divider:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 64
    description: |
      Set the divider for calculating TUN_STEP.

  marvell,xenon-phy-slow-mode:
    type: boolean
    description: |
      If this property is selected, transfers will bypass PHY.
      Only available when bus frequency lower than 55MHz in SDR mode.
      Disabled by default. Please only try this property if timing issues
      always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
      SD Default Speed and HS mode and eMMC legacy speed mode.

  marvell,xenon-tun-count:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0x9
    description: |
      Xenon SDHC SoC usually doesn't provide re-tuning counter in
      Capabilities Register 3 Bit[11:8].
      This property provides the re-tuning counter.

allOf:
  - $ref: mmc-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: marvell,armada-3700-sdhci

    then:
      properties:
        reg:
          items:
            - description: Xenon IP registers
            - description: Armada 3700 SoC PHY PAD Voltage Control register

        marvell,pad-type:
          $ref: /schemas/types.yaml#/definitions/string
          enum:
            - sd
            - fixed-1-8v
          description: |
            Type of Armada 3700 SoC PHY PAD Voltage Controller register.
            If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
            and is switched to 1.8V when later in higher speed mode.
            If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
            eMMC.
            Please follow the examples with compatible
            "marvell,armada-3700-sdhci" in below.

      required:
        - marvell,pad-type

  - if:
      properties:
        compatible:
          contains:
            enum:
              - marvell,armada-cp110-sdhci
              - marvell,armada-ap807-sdhci
              - marvell,armada-ap806-sdhci

    then:
      properties:
        clocks:
          minItems: 2

        clock-names:
          items:
            - const: core
            - const: axi

required:
  - compatible
  - reg
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    // For eMMC
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    mmc@aa0000 {
      compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci";
      reg = <0xaa0000 0x1000>;
      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&emmc_clk 0>, <&axi_clk 0>;
      clock-names = "core", "axi";
      bus-width = <4>;
      marvell,xenon-phy-slow-mode;
      marvell,xenon-tun-count = <11>;
      non-removable;
      no-sd;
      no-sdio;

      /* Vmmc and Vqmmc are both fixed */
    };

  - |
    // For SD/SDIO
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    mmc@ab0000 {
      compatible = "marvell,armada-cp110-sdhci";
      reg = <0xab0000 0x1000>;
      interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
      vqmmc-supply = <&sd_vqmmc_regulator>;
      vmmc-supply = <&sd_vmmc_regulator>;
      clocks = <&sdclk 0>, <&axi_clk 0>;
      clock-names = "core", "axi";
      bus-width = <4>;
      marvell,xenon-tun-count = <9>;
    };

  - |
    // For eMMC with compatible "marvell,armada-3700-sdhci":
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    mmc@aa0000 {
      compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
      reg = <0xaa0000 0x1000>,
            <0x17808 0x4>;
      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&emmcclk 0>;
      clock-names = "core";
      bus-width = <8>;
      mmc-ddr-1_8v;
      mmc-hs400-1_8v;
      non-removable;
      no-sd;
      no-sdio;

      /* Vmmc and Vqmmc are both fixed */

      marvell,pad-type = "fixed-1-8v";
    };

  - |
    // For SD/SDIO with compatible "marvell,armada-3700-sdhci":
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    mmc@ab0000 {
      compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
      reg = <0xab0000 0x1000>,
            <0x17808 0x4>;
      interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
      vqmmc-supply = <&sd_regulator>;
      /* Vmmc is fixed */
      clocks = <&sdclk 0>;
      clock-names = "core";
      bus-width = <4>;

      marvell,pad-type = "sd";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip Sparx5 Mobile Storage Host Controller Binding

allOf:
  - $ref: "mmc-controller.yaml"

maintainers:
  - Lars Povlsen <lars.povlsen@microchip.com>

# Everything else is described in the common file
properties:
  compatible:
    const: microchip,dw-sparx5-sdhci

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1
    description:
      Handle to "core" clock for the sdhci controller.

  clock-names:
    items:
      - const: core

  microchip,clock-delay:
    description: Delay clock to card to meet setup time requirements.
      Each step increase by 1.25ns.
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 1
    maximum: 15

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/microchip,sparx5.h>
    sdhci0: mmc@600800000 {
        compatible = "microchip,dw-sparx5-sdhci";
        reg = <0x00800000 0x1000>;
        pinctrl-0 = <&emmc_pins>;
        pinctrl-names = "default";
        clocks = <&clks CLK_ID_AUX1>;
        clock-names = "core";
        assigned-clocks = <&clks CLK_ID_AUX1>;
        assigned-clock-rates = <800000000>;
        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
        bus-width = <8>;
        microchip,clock-delay = <10>;
    };


code:
* Microchip PIC32 SDHCI Controller

This file documents differences between the core properties in mmc.txt
and the properties used by the sdhci-pic32 driver.

Required properties:
- compatible: Should be "microchip,pic32mzda-sdhci"
- interrupts: Should contain interrupt
- clock-names: Should be "base_clk", "sys_clk".
               See: Documentation/devicetree/bindings/resource-names.txt
- clocks: Phandle to the clock.
          See: Documentation/devicetree/bindings/clock/clock-bindings.txt
- pinctrl-names: A pinctrl state names "default" must be defined.
- pinctrl-0: Phandle referencing pin configuration of the SDHCI controller.
             See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

Example:

	sdhci@1f8ec000 {
		compatible = "microchip,pic32mzda-sdhci";
		reg = <0x1f8ec000 0x100>;
		interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>;
		clock-names = "base_clk", "sys_clk";
		bus-width = <4>;
		cap-sd-highspeed;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_sdhc1>;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/mmc-card.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MMC Card / eMMC Generic

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

description: |
  This documents describes the devicetree bindings for a mmc-host controller
  child node describing a mmc-card / an eMMC.

properties:
  compatible:
    const: mmc-card

  reg:
    const: 0

  broken-hpi:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Use this to indicate that the mmc-card has a broken hpi
      implementation, and that hpi should not be used.

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    mmc {
        #address-cells = <1>;
        #size-cells = <0>;

        card@0 {
            compatible = "mmc-card";
            reg = <0>;
            broken-hpi;
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MMC Controller Generic Binding

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

description: |
  These properties are common to multiple MMC host controllers. Any host
  that requires the respective functionality should implement them using
  these definitions.

  It is possible to assign a fixed index mmcN to an MMC host controller
  (and the corresponding mmcblkN devices) by defining an alias in the
  /aliases device tree node.

properties:
  $nodename:
    pattern: "^mmc(@.*)?$"

  "#address-cells":
    const: 1
    description: |
      The cell is the slot ID if a function subnode is used.

  "#size-cells":
    const: 0

  # Card Detection.
  # If none of these properties are supplied, the host native card
  # detect will be used. Only one of them should be provided.

  broken-cd:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      There is no card detection available; polling must be used.

  cd-gpios:
    maxItems: 1
    description:
      The card detection will be done using the GPIO provided.

  non-removable:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Non-removable slot (like eMMC); assume always present.

  # *NOTE* on CD and WP polarity. To use common for all SD/MMC host
  # controllers line polarity properties, we have to fix the meaning
  # of the "normal" and "inverted" line levels. We choose to follow
  # the SDHCI standard, which specifies both those lines as "active
  # low." Therefore, using the "cd-inverted" property means, that the
  # CD line is active high, i.e. it is high, when a card is
  # inserted. Similar logic applies to the "wp-inverted" property.
  #
  # CD and WP lines can be implemented on the hardware in one of two
  # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
  # as dedicated pins. Polarity of dedicated pins can be specified,
  # using *-inverted properties. GPIO polarity can also be specified
  # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
  # latter case. We choose to use the XOR logic for GPIO CD and WP
  # lines.  This means, the two properties are "superimposed," for
  # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
  # respective *-inverted property property results in a
  # double-inversion and actually means the "normal" line polarity is
  # in effect.
  wp-inverted:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      The Write Protect line polarity is inverted.

  cd-inverted:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      The CD line polarity is inverted.

  # Other properties

  bus-width:
    description:
      Number of data lines.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 4, 8]
    default: 1

  max-frequency:
    description: |
      Maximum operating frequency of the bus:
        - for eMMC, the maximum supported frequency is 200MHz,
        - for SD/SDIO cards the SDR104 mode has a max supported
          frequency of 208MHz,
        - some mmc host controllers do support a max frequency upto
          384MHz.
      So, lets keep the maximum supported value here.

    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 400000
    maximum: 384000000

  disable-wp:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      When set, no physical write-protect line is present. This
      property should only be specified when the controller has a
      dedicated write-protect detection logic. If a GPIO is always used
      for the write-protect detection logic, it is sufficient to not
      specify the wp-gpios property in the absence of a write-protect
      line. Not used in combination with eMMC or SDIO.

  wp-gpios:
    maxItems: 1
    description:
      GPIO to use for the write-protect detection.

  cd-debounce-delay-ms:
    description:
      Set delay time before detecting card after card insert
      interrupt.

  no-1-8-v:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      When specified, denotes that 1.8V card voltage is not supported
      on this system, even if the controller claims it.

  cap-sd-highspeed:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      SD high-speed timing is supported.

  cap-mmc-highspeed:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      MMC high-speed timing is supported.

  sd-uhs-sdr12:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      SD UHS SDR12 speed is supported.

  sd-uhs-sdr25:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      SD UHS SDR25 speed is supported.

  sd-uhs-sdr50:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      SD UHS SDR50 speed is supported.

  sd-uhs-sdr104:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      SD UHS SDR104 speed is supported.

  sd-uhs-ddr50:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      SD UHS DDR50 speed is supported.

  cap-power-off-card:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Powering off the card is safe.

  cap-mmc-hw-reset:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      eMMC hardware reset is supported

  cap-sdio-irq:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      enable SDIO IRQ signalling on this interface

  full-pwr-cycle:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Full power cycle of the card is supported.

  full-pwr-cycle-in-suspend:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Full power cycle of the card in suspend is supported.

  mmc-ddr-1_2v:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      eMMC high-speed DDR mode (1.2V I/O) is supported.

  mmc-ddr-1_8v:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      eMMC high-speed DDR mode (1.8V I/O) is supported.

  mmc-ddr-3_3v:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      eMMC high-speed DDR mode (3.3V I/O) is supported.

  mmc-hs200-1_2v:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      eMMC HS200 mode (1.2V I/O) is supported.

  mmc-hs200-1_8v:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      eMMC HS200 mode (1.8V I/O) is supported.

  mmc-hs400-1_2v:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      eMMC HS400 mode (1.2V I/O) is supported.

  mmc-hs400-1_8v:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      eMMC HS400 mode (1.8V I/O) is supported.

  mmc-hs400-enhanced-strobe:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      eMMC HS400 enhanced strobe mode is supported

  no-mmc-hs400:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      All eMMC HS400 modes are not supported.

  dsr:
    description:
      Value the card Driver Stage Register (DSR) should be programmed
      with.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xffff

  no-sdio:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Controller is limited to send SDIO commands during
      initialization.

  no-sd:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Controller is limited to send SD commands during initialization.

  no-mmc:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Controller is limited to send MMC commands during
      initialization.

  fixed-emmc-driver-type:
    description:
      For non-removable eMMC, enforce this driver type. The value is
      the driver type as specified in the eMMC specification (table
      206 in spec version 5.1)
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 4

  post-power-on-delay-ms:
    description:
      It was invented for MMC pwrseq-simple which could be referred to
      mmc-pwrseq-simple.txt. But now it\'s reused as a tunable delay
      waiting for I/O signalling and card power supply to be stable,
      regardless of whether pwrseq-simple is used. Default to 10ms if
      no available.
    default: 10

  supports-cqe:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      The presence of this property indicates that the corresponding
      MMC host controller supports HW command queue feature.

  disable-cqe-dcmd:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      The presence of this property indicates that the MMC
      controller\'s command queue engine (CQE) does not support direct
      commands (DCMDs).

  keep-power-in-suspend:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      SDIO only. Preserves card power during a suspend/resume cycle.

  wakeup-source:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      SDIO only. Enables wake up of host system on SDIO IRQ assertion.

  vmmc-supply:
    description:
      Supply for the card power

  vqmmc-supply:
    description:
      Supply for the bus IO line power, such as a level shifter.
      If the level shifter is controlled by a GPIO line, this shall
      be modeled as a "regulator-fixed" with a GPIO line for
      switching the level shifter on/off.

  mmc-pwrseq:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      System-on-Chip designs may specify a specific MMC power
      sequence. To successfully detect an (e)MMC/SD/SDIO card, that
      power sequence must be maintained while initializing the card.

patternProperties:
  "^.*@[0-9]+$":
    type: object
    description: |
      On embedded systems the cards connected to a host may need
      additional properties. These can be specified in subnodes to the
      host controller node. The subnodes are identified by the
      standard \'reg\' property. Which information exactly can be
      specified depends on the bindings for the SDIO function driver
      for the subnode, as specified by the compatible string.

    properties:
      compatible:
        description: |
          Name of SDIO function following generic names recommended
          practice

      reg:
        items:
          - minimum: 0
            maximum: 7
            description:
              Must contain the SDIO function number of the function this
              subnode describes. A value of 0 denotes the memory SD
              function, values from 1 to 7 denote the SDIO functions.

    required:
      - reg

  "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
    $ref: /schemas/types.yaml#/definitions/uint32-array

    minItems: 2
    maxItems: 2
    items:
      minimum: 0
      maximum: 359
      description:
        Set the clock (phase) delays which are to be configured in the
        controller while switching to particular speed mode. These values
        are in pair of degrees.

dependencies:
  cd-debounce-delay-ms: [ cd-gpios ]
  fixed-emmc-driver-type: [ non-removable ]

additionalProperties: true

examples:
  - |
    mmc3: mmc@1c12000 {
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x1c12000 0x200>;
        pinctrl-names = "default";
        pinctrl-0 = <&mmc3_pins_a>;
        vmmc-supply = <&reg_vmmc3>;
        bus-width = <4>;
        non-removable;
        mmc-pwrseq = <&sdhci0_pwrseq>;

        brcmf: wifi@1 {
            reg = <1>;
            compatible = "brcm,bcm4329-fmac";
            interrupt-parent = <&pio>;
            interrupts = <10 8>;
            interrupt-names = "host-wake";
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Simple eMMC hardware reset provider binding

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

description:
  The purpose of this driver is to perform standard eMMC hw reset
  procedure, as described by Jedec 4.4 specification. This procedure is
  performed just after MMC core enabled power to the given mmc host (to
  fix possible issues if bootloader has left eMMC card in initialized or
  unknown state), and before performing complete system reboot (also in
  case of emergency reboot call). The latter is needed on boards, which
  doesn't have hardware reset logic connected to emmc card and (limited or
  broken) ROM bootloaders are unable to read second stage from the emmc
  card if the card is left in unknown or already initialized state.

properties:
  compatible:
    const: mmc-pwrseq-emmc

  reset-gpios:
    minItems: 1
    description:
      contains a GPIO specifier. The reset GPIO is asserted
      and then deasserted to perform eMMC card reset. To perform
      reset procedure as described in Jedec 4.4 specification, the
      gpio line should be defined as GPIO_ACTIVE_LOW.

required:
  - compatible
  - reset-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    sdhci0_pwrseq {
      compatible = "mmc-pwrseq-emmc";
      reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-sd8787.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell SD8787 power sequence provider binding

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

properties:
  compatible:
    enum:
      - mmc-pwrseq-sd8787
      - mmc-pwrseq-wilc1000

  powerdown-gpios:
    minItems: 1
    description:
      contains a power down GPIO specifier with the default active state

  reset-gpios:
    minItems: 1
    description:
      contains a reset GPIO specifier with the default active state

required:
  - compatible
  - powerdown-gpios
  - reset-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    wifi_pwrseq: wifi_pwrseq {
      compatible = "mmc-pwrseq-sd8787";
      powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
      reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Simple MMC power sequence provider binding

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

description:
  The purpose of the simple MMC power sequence provider is to supports a set
  of common properties between various SOC designs. It thus enables us to use
  the same provider for several SOC designs.

properties:
  compatible:
    const: mmc-pwrseq-simple

  reset-gpios:
    minItems: 1
    # Put some limit to avoid false warnings
    maxItems: 32
    description:
      contains a list of GPIO specifiers. The reset GPIOs are asserted
      at initialization and prior we start the power up procedure of the card.
      They will be de-asserted right after the power has been provided to the
      card.

  clocks:
    minItems: 1
    description: Handle for the entry in clock-names.

  clock-names:
    items:
      - const: ext_clock
    description: External clock provided to the card.

  post-power-on-delay-ms:
    description:
      Delay in ms after powering the card and de-asserting the
      reset-gpios (if any).

  power-off-delay-us:
    description:
      Delay in us after asserting the reset-gpios (if any)
      during power off of the card.

required:
  - compatible

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    sdhci0_pwrseq {
      compatible = "mmc-pwrseq-simple";
      reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
      clocks = <&clk_32768_ck>;
      clock-names = "ext_clock";
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/mmc-spi-slot.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MMC/SD/SDIO slot directly connected to a SPI bus

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

allOf:
  - $ref: "mmc-controller.yaml"
  - $ref: /schemas/spi/spi-peripheral-props.yaml

description: |
  The extra properties used by an mmc connected via SPI.

properties:
  compatible:
    const: mmc-spi-slot

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  voltage-ranges:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: |
      Two cells are required, first cell specifies minimum slot voltage (mV),
      second cell specifies maximum slot voltage (mV).
    items:
      - description: |
          value for minimum slot voltage in mV
        default: 3200
      - description: |
          value for maximum slot voltage in mV
        default: 3400

  gpios:
    description: |
      For historical reasons, this does not follow the generic mmc-controller
      binding.
    minItems: 1
    items:
      - description: Card-Detect GPIO
      - description: Write-Protect GPIO

required:
  - compatible
  - reg
  - spi-max-frequency

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    spi {
      #address-cells = <1>;
      #size-cells = <0>;
      mmc@0 {
        compatible = "mmc-spi-slot";
        reg = <0>;
        gpios = <&gpio 14 GPIO_ACTIVE_LOW>, <&gpio 15 GPIO_ACTIVE_HIGH>;
        voltage-ranges = <3300 3300>;
        spi-max-frequency = <50000000>;
        interrupts = <42>;
        interrupt-parent = <&PIC>;
      };
    };

...


code: This file has moved to mmc-controller.yaml.


code:
MOXA ART MMC Host Controller Interface

  Inherits from mmc binding[1].

  [1] Documentation/devicetree/bindings/mmc/mmc.txt

Required properties:

- compatible :	Must be "moxa,moxart-mmc" or "faraday,ftsdc010"
- reg :		Should contain registers location and length
- interrupts :	Should contain the interrupt number
- clocks :	Should contain phandle for the clock feeding the MMC controller

Optional properties:

- dmas :	Should contain two DMA channels, line request number must be 5 for
		both channels
- dma-names :	Must be "tx", "rx"

Example:

	mmc: mmc@98e00000 {
		compatible = "moxa,moxart-mmc";
		reg = <0x98e00000 0x5C>;
		interrupts = <5 0>;
		clocks = <&clk_apb>;
		dmas =  <&dma 5>,
			<&dma 5>;
		dma-names = "tx", "rx";
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MTK MSDC Storage Host Controller Binding

maintainers:
  - Chaotian Jing <chaotian.jing@mediatek.com>
  - Wenbin Mei <wenbin.mei@mediatek.com>

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt2701-mmc
          - mediatek,mt2712-mmc
          - mediatek,mt6779-mmc
          - mediatek,mt6795-mmc
          - mediatek,mt7620-mmc
          - mediatek,mt7622-mmc
          - mediatek,mt7986-mmc
          - mediatek,mt8135-mmc
          - mediatek,mt8173-mmc
          - mediatek,mt8183-mmc
          - mediatek,mt8516-mmc
      - items:
          - const: mediatek,mt7623-mmc
          - const: mediatek,mt2701-mmc
      - items:
          - enum:
              - mediatek,mt8186-mmc
              - mediatek,mt8188-mmc
              - mediatek,mt8192-mmc
              - mediatek,mt8195-mmc
          - const: mediatek,mt8183-mmc

  reg:
    minItems: 1
    items:
      - description: base register (required).
      - description: top base register (required for MT8183).

  clocks:
    description:
      Should contain phandle for the clock feeding the MMC controller.
    minItems: 2
    maxItems: 7

  clock-names:
    minItems: 2
    maxItems: 7

  interrupts:
    description:
      Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
      interrupt is required and be configured as wakeup source irq.
    minItems: 1
    maxItems: 2

  interrupt-names:
    items:
      - const: msdc
      - const: sdio_wakeup

  pinctrl-names:
    description:
      Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
      will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this
      scenario.
    minItems: 2
    items:
      - const: default
      - const: state_uhs
      - const: state_eint

  pinctrl-0:
    description:
      should contain default/high speed pin ctrl.
    maxItems: 1

  pinctrl-1:
    description:
      should contain uhs mode pin ctrl.
    maxItems: 1

  pinctrl-2:
    description:
      should switch dat1 pin to GPIO mode.
    maxItems: 1

  assigned-clocks:
    description:
      PLL of the source clock.
    maxItems: 1

  assigned-clock-parents:
    description:
      parent of source clock, used for HS400 mode to get 400Mhz source clock.
    maxItems: 1

  hs400-ds-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      HS400 DS delay setting.
    minimum: 0
    maximum: 0xffffffff

  mediatek,hs200-cmd-int-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      HS200 command internal delay setting.
      This field has total 32 stages.
      The value is an integer from 0 to 31.
    minimum: 0
    maximum: 31

  mediatek,hs400-cmd-int-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      HS400 command internal delay setting.
      This field has total 32 stages.
      The value is an integer from 0 to 31.
    minimum: 0
    maximum: 31

  mediatek,hs400-cmd-resp-sel-rising:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      HS400 command response sample selection.
      If present, HS400 command responses are sampled on rising edges.
      If not present, HS400 command responses are sampled on falling edges.

  mediatek,hs400-ds-dly3:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Gear of the third delay line for DS for input data latch in data
      pad macro, there are 32 stages from 0 to 31.
      For different corner IC, the time is different about one step, it is
      about 100ps.
      The value is confirmed by doing scan and calibration to find a best
      value with corner IC and it is valid only for HS400 mode.
    minimum: 0
    maximum: 31

  mediatek,latch-ck:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
      data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
      if not present, default value is 0.
      applied to compatible "mediatek,mt2701-mmc".
    minimum: 0
    maximum: 7

  resets:
    maxItems: 1

  reset-names:
    const: hrst

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - pinctrl-names
  - pinctrl-0
  - pinctrl-1
  - vmmc-supply
  - vqmmc-supply

allOf:
  - $ref: mmc-controller.yaml#
  - if:
      properties:
        compatible:
          enum:
            - mediatek,mt2701-mmc
            - mediatek,mt6779-mmc
            - mediatek,mt6795-mmc
            - mediatek,mt7620-mmc
            - mediatek,mt7622-mmc
            - mediatek,mt7623-mmc
            - mediatek,mt8135-mmc
            - mediatek,mt8173-mmc
            - mediatek,mt8183-mmc
            - mediatek,mt8186-mmc
            - mediatek,mt8188-mmc
            - mediatek,mt8195-mmc
            - mediatek,mt8516-mmc
    then:
      properties:
        clocks:
          minItems: 2
          items:
            - description: source clock
            - description: HCLK which used for host
            - description: independent source clock gate
        clock-names:
          minItems: 2
          items:
            - const: source
            - const: hclk
            - const: source_cg

  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt2712-mmc
    then:
      properties:
        clocks:
          minItems: 3
          items:
            - description: source clock
            - description: HCLK which used for host
            - description: independent source clock gate
            - description: bus clock used for internal register access (required for MSDC0/3).
        clock-names:
          minItems: 3
          items:
            - const: source
            - const: hclk
            - const: source_cg
            - const: bus_clk

  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt8183-mmc
    then:
      properties:
        reg:
          minItems: 2

  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt7986-mmc
    then:
      properties:
        clocks:
          minItems: 3
          items:
            - description: source clock
            - description: HCLK which used for host
            - description: independent source clock gate
            - description: bus clock used for internal register access (required for MSDC0/3).
            - description: msdc subsys clock gate
        clock-names:
          minItems: 3
          items:
            - const: source
            - const: hclk
            - const: source_cg
            - const: bus_clk
            - const: sys_cg

  - if:
      properties:
        compatible:
          enum:
            - mediatek,mt8186-mmc
            - mediatek,mt8188-mmc
            - mediatek,mt8195-mmc
    then:
      properties:
        clocks:
          items:
            - description: source clock
            - description: HCLK which used for host
            - description: independent source clock gate
            - description: crypto clock used for data encrypt/decrypt (optional)
        clock-names:
          items:
            - const: source
            - const: hclk
            - const: source_cg
            - const: crypto

  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt8192-mmc
    then:
      properties:
        clocks:
          items:
            - description: source clock
            - description: HCLK which used for host
            - description: independent source clock gate
            - description: msdc subsys clock gate
            - description: peripheral bus clock gate
            - description: AXI bus clock gate
            - description: AHB bus clock gate
        clock-names:
          items:
            - const: source
            - const: hclk
            - const: source_cg
            - const: sys_cg
            - const: pclk_cg
            - const: axi_cg
            - const: ahb_cg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    mmc0: mmc@11230000 {
        compatible = "mediatek,mt8173-mmc";
        reg = <0x11230000 0x1000>;
        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
        vmmc-supply = <&mt6397_vemc_3v3_reg>;
        vqmmc-supply = <&mt6397_vio18_reg>;
        clocks = <&pericfg CLK_PERI_MSDC30_0>,
                 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
        clock-names = "source", "hclk";
        pinctrl-names = "default", "state_uhs";
        pinctrl-0 = <&mmc0_pins_default>;
        pinctrl-1 = <&mmc0_pins_uhs>;
        assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
        assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
        hs400-ds-delay = <0x14015>;
        mediatek,hs200-cmd-int-delay = <26>;
        mediatek,hs400-cmd-int-delay = <14>;
        mediatek,hs400-cmd-resp-sel-rising;
    };

    mmc3: mmc@11260000 {
        compatible = "mediatek,mt8173-mmc";
        reg = <0x11260000 0x1000>;
        clock-names = "source", "hclk";
        clocks = <&pericfg CLK_PERI_MSDC30_3>,
                 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
        interrupt-names = "msdc", "sdio_wakeup";
        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
                     <&pio 23 IRQ_TYPE_LEVEL_LOW>;
        pinctrl-names = "default", "state_uhs", "state_eint";
        pinctrl-0 = <&mmc2_pins_default>;
        pinctrl-1 = <&mmc2_pins_uhs>;
        pinctrl-2 = <&mmc2_pins_eint>;
        bus-width = <4>;
        max-frequency = <200000000>;
        cap-sd-highspeed;
        sd-uhs-sdr104;
        keep-power-in-suspend;
        wakeup-source;
        cap-sdio-irq;
        no-mmc;
        no-sd;
        non-removable;
        vmmc-supply = <&sdio_fixed_3v3>;
        vqmmc-supply = <&mt6397_vgp3_reg>;
        mmc-pwrseq = <&wifi_pwrseq>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/mxs-mmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale MXS MMC controller

maintainers:
  - Shawn Guo <shawnguo@kernel.org>

description: |
  The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller
  to support MMC, SD, and SDIO types of memory cards.

  This file documents differences between the core properties in mmc.txt
  and the properties used by the mxsmmc driver.

allOf:
  - $ref: "mmc-controller.yaml"

properties:
  compatible:
    enum:
      - fsl,imx23-mmc
      - fsl,imx28-mmc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  dmas:
    maxItems: 1

  dma-names:
    const: rx-tx

required:
  - compatible
  - reg
  - interrupts
  - dmas
  - dma-names

unevaluatedProperties: false

examples:
  - |
    mmc@80010000 {
        compatible = "fsl,imx28-mmc";
        reg = <0x80010000 2000>;
        interrupts = <96>;
        dmas = <&dma_apbh 0>;
        dma-names = "rx-tx";
        bus-width = <8>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Secure Digital Host Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: |
  This controller on Tegra family SoCs provides an interface for MMC, SD, and
  SDIO types of memory cards.

  This file documents differences between the core properties described by
  mmc-controller.yaml and the properties for the Tegra SDHCI controller.

properties:
  compatible:
    oneOf:
      - enum:
          - nvidia,tegra20-sdhci
          - nvidia,tegra30-sdhci
          - nvidia,tegra114-sdhci
          - nvidia,tegra124-sdhci
          - nvidia,tegra210-sdhci
          - nvidia,tegra186-sdhci
          - nvidia,tegra194-sdhci

      - items:
          - const: nvidia,tegra132-sdhci
          - const: nvidia,tegra124-sdhci

      - items:
          - enum:
              - nvidia,tegra194-sdhci
              - nvidia,tegra234-sdhci
          - const: nvidia,tegra186-sdhci

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  assigned-clocks: true
  assigned-clock-parents: true
  assigned-clock-rates: true

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    maxItems: 2

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: sdhci

  power-gpios:
    description: specify GPIOs for power control
    maxItems: 1

  interconnects:
    items:
      - description: memory read client
      - description: memory write client

  interconnect-names:
    items:
      - const: dma-mem # read
      - const: write

  iommus:
    maxItems: 1

  operating-points-v2:
    $ref: "/schemas/types.yaml#/definitions/phandle"

  power-domains:
    items:
      - description: phandle to the core power domain

  nvidia,default-tap:
    description: Specify the default inbound sampling clock trimmer value for
      non-tunable modes.

      The values are used for compensating trace length differences by
      adjusting the sampling point. The values are programmed to the Vendor
      Clock Control Register. Please refer to the reference manual of the SoC
      for correct values.

      The DQS trim values are only used on controllers which support HS400
      timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,default-trim:
    description: Specify the default outbound clock trimmer value.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,dqs-trim:
    description: Specify DQS trim value for HS400 timing.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,pad-autocal-pull-down-offset-1v8:
    description: Specify drive strength calibration offsets for 1.8 V
      signaling modes.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,pad-autocal-pull-down-offset-1v8-timeout:
    description: Specify drive strength used as a fallback in case the
      automatic calibration times out on a 1.8 V signaling mode.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,pad-autocal-pull-down-offset-3v3:
    description: Specify drive strength calibration offsets for 3.3 V
      signaling modes.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,pad-autocal-pull-down-offset-3v3-timeout:
    description: Specify drive strength used as a fallback in case the
      automatic calibration times out on a 3.3 V signaling mode.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,pad-autocal-pull-down-offset-sdr104:
    description: Specify drive strength calibration offsets for SDR104 mode.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,pad-autocal-pull-down-offset-hs400:
    description: Specify drive strength calibration offsets for HS400 mode.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,pad-autocal-pull-up-offset-1v8:
    description: Specify drive strength calibration offsets for 1.8 V
      signaling modes.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,pad-autocal-pull-up-offset-1v8-timeout:
    description: Specify drive strength used as a fallback in case the
      automatic calibration times out on a 1.8 V signaling mode.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,pad-autocal-pull-up-offset-3v3:
    description: Specify drive strength calibration offsets for 3.3 V
      signaling modes.

      The property values are drive codes which are programmed into the
      PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG
      register. A higher value corresponds to higher drive strength. Please
      refer to the reference manual of the SoC for correct values. The SDR104
      and HS400 timing specific values are used in corresponding modes if
      specified.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,pad-autocal-pull-up-offset-3v3-timeout:
    description: Specify drive strength used as a fallback in case the
      automatic calibration times out on a 3.3 V signaling mode.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,pad-autocal-pull-up-offset-sdr104:
    description: Specify drive strength calibration offsets for SDR104 mode.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,pad-autocal-pull-up-offset-hs400:
    description: Specify drive strength calibration offsets for HS400 mode.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,only-1-8v:
    description: The presence of this property indicates that the controller
      operates at a 1.8 V fixed I/O voltage.
    $ref: "/schemas/types.yaml#/definitions/flag"

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - resets
  - reset-names

allOf:
  - $ref: "mmc-controller.yaml"
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra20-sdhci
              - nvidia,tegra30-sdhci
              - nvidia,tegra114-sdhci
              - nvidia,tegra124-sdhci
    then:
      properties:
        clocks:
          items:
            - description: module clock
    else:
      properties:
        clocks:
          items:
            - description: module clock
            - description: timeout clock

        clock-names:
          items:
            - const: sdhci
            - const: tmclk
      required:
        - clock-names

  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra210-sdhci
    then:
      properties:
        pinctrl-names:
          oneOf:
            - items:
                - const: sdmmc-3v3
                  description: pad configuration for 3.3 V
                - const: sdmmc-1v8
                  description: pad configuration for 1.8 V
                - const: sdmmc-3v3-drv
                  description: pull-up/down configuration for 3.3 V
                - const: sdmmc-1v8-drv
                  description: pull-up/down configuration for 1.8 V
            - items:
                - const: sdmmc-3v3-drv
                  description: pull-up/down configuration for 3.3 V
                - const: sdmmc-1v8-drv
                  description: pull-up/down configuration for 1.8 V
            - items:
                - const: sdmmc-1v8-drv
                  description: pull-up/down configuration for 1.8 V
      required:
        - clock-names
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra186-sdhci
              - nvidia,tegra194-sdhci
    then:
      properties:
        pinctrl-names:
          items:
            - const: sdmmc-3v3
              description: pad configuration for 3.3 V
            - const: sdmmc-1v8
              description: pad configuration for 1.8 V
      required:
        - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mmc@c8000200 {
        compatible = "nvidia,tegra20-sdhci";
        reg = <0xc8000200 0x200>;
        interrupts = <47>;
        clocks = <&tegra_car 14>;
        resets = <&tegra_car 14>;
        reset-names = "sdhci";
        cd-gpios = <&gpio 69 0>; /* gpio PI5 */
        wp-gpios = <&gpio 57 0>; /* gpio PH1 */
        power-gpios = <&gpio 155 0>; /* gpio PT3 */
        bus-width = <8>;
    };

  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mmc@700b0000 {
        compatible = "nvidia,tegra210-sdhci";
        reg = <0x700b0000 0x200>;
        interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
                 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
        clock-names = "sdhci", "tmclk";
        resets = <&tegra_car 14>;
        reset-names = "sdhci";
        pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
                        "sdmmc-3v3-drv", "sdmmc-1v8-drv";
        pinctrl-0 = <&sdmmc1_3v3>;
        pinctrl-1 = <&sdmmc1_1v8>;
        pinctrl-2 = <&sdmmc1_3v3_drv>;
        pinctrl-3 = <&sdmmc1_1v8_drv>;
        nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
        nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
        nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
        nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
        nvidia,default-tap = <0x2>;
        nvidia,default-trim = <0x4>;
        assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
                          <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
                          <&tegra_car TEGRA210_CLK_PLL_C4>;
        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
        assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/owl-mmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Actions Semi Owl SoCs SD/MMC/SDIO controller

allOf:
  - $ref: "mmc-controller.yaml"

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

properties:
  compatible:
    oneOf:
      - const: actions,owl-mmc
      - items:
          - enum:
              - actions,s500-mmc
              - actions,s700-mmc
          - const: actions,owl-mmc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1

  resets:
    maxItems: 1

  dmas:
    maxItems: 1

  dma-names:
    const: mmc

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - resets
  - dmas
  - dma-names

unevaluatedProperties: false

examples:
  - |
    mmc0: mmc@e0330000 {
        compatible = "actions,owl-mmc";
        reg = <0xe0330000 0x4000>;
        interrupts = <0 42 4>;
        clocks = <&cmu 56>;
        resets = <&cmu 23>;
        dmas = <&dma 2>;
        dma-names = "mmc";
        bus-width = <4>;
    };

...


code:
* PXA MMC drivers

Driver bindings for the PXA MCI (MMC/SDIO) interfaces

Required properties:
- compatible: Should be "marvell,pxa-mmc".
- vmmc-supply: A regulator for VMMC

Optional properties:
- marvell,detect-delay-ms: sets the detection delay timeout in ms.

In addition to the properties described in this docuent, the details
described in mmc.txt are supported.

Examples:

mmc0: mmc@41100000 {
	compatible = "marvell,pxa-mmc";
	reg = <0x41100000 0x1000>;
	interrupts = <23>;
	vmmc-supply = <&mmc_regulator>;
	cd-gpios = <&gpio 23 0>;
	wp-gpios = <&gpio 24 0>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/renesas,mmcif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Multi Media Card Interface (MMCIF) Controller

maintainers:
  - Wolfram Sang <wsa+renesas@sang-engineering.com>

allOf:
  - $ref: "mmc-controller.yaml"

properties:
  compatible:
    items:
      - enum:
          - renesas,mmcif-r7s72100 # RZ/A1H
          - renesas,mmcif-r8a73a4  # R-Mobile APE6
          - renesas,mmcif-r8a7740  # R-Mobile A1
          - renesas,mmcif-r8a7742  # RZ/G1H
          - renesas,mmcif-r8a7743  # RZ/G1M
          - renesas,mmcif-r8a7744  # RZ/G1N
          - renesas,mmcif-r8a7745  # RZ/G1E
          - renesas,mmcif-r8a7778  # R-Car M1A
          - renesas,mmcif-r8a7790  # R-Car H2
          - renesas,mmcif-r8a7791  # R-Car M2-W
          - renesas,mmcif-r8a7793  # R-Car M2-N
          - renesas,mmcif-r8a7794  # R-Car E2
          - renesas,mmcif-sh73a0   # SH-Mobile AG5
      - const: renesas,sh-mmcif

  reg:
    maxItems: 1

  interrupts: true

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  dmas:
    minItems: 2
    maxItems: 4
    description:
      Must contain a list of pairs of references to DMA specifiers, one for
      transmission, and one for reception.

  dma-names:
    minItems: 2
    maxItems: 4
    items:
      enum:
        - tx
        - rx

  max-frequency: true

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains

if:
  properties:
    compatible:
      contains:
        const: renesas,mmcif-r7s72100
then:
  properties:
    interrupts:
      items:
        - description: Error interrupt
        - description: Normal operation interrupt
        - description: Card detection interrupt
else:
  if:
    properties:
      compatible:
        contains:
          enum:
            - renesas,mmcif-r8a7740
            - renesas,mmcif-sh73a0
  then:
    properties:
      interrupts:
        items:
          - description: Error interrupt
          - description: Normal operation interrupt
  else:
    if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,mmcif-r8a73a4
              - renesas,mmcif-r8a7778
    then:
      properties:
        interrupts:
          maxItems: 1
    else:
      properties:
        interrupts:
          maxItems: 1
      required:
        - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>

    mmcif0: mmc@ee200000 {
            compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
            reg = <0xee200000 0x80>;
            interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 315>;
            power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
            resets = <&cpg 315>;
            dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>;
            dma-names = "tx", "rx", "tx", "rx";
            max-frequency = <97500000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Renesas SDHI SD/MMC controller

maintainers:
  - Wolfram Sang <wsa+renesas@sang-engineering.com>

properties:
  compatible:
    oneOf:
      - items:
          - const: renesas,sdhi-sh73a0  # R-Mobile APE6
      - items:
          - const: renesas,sdhi-r7s72100 # RZ/A1H
      - items:
          - const: renesas,sdhi-r7s9210 # SH-Mobile AG5
      - items:
          - const: renesas,sdhi-r8a73a4 # R-Mobile APE6
      - items:
          - const: renesas,sdhi-r8a7740 # R-Mobile A1
      - items:
          - enum:
              - renesas,sdhi-r8a7778 # R-Car M1
              - renesas,sdhi-r8a7779 # R-Car H1
          - const: renesas,rcar-gen1-sdhi # R-Car Gen1
      - items:
          - enum:
              - renesas,sdhi-r8a7742  # RZ/G1H
              - renesas,sdhi-r8a7743  # RZ/G1M
              - renesas,sdhi-r8a7744  # RZ/G1N
              - renesas,sdhi-r8a7745  # RZ/G1E
              - renesas,sdhi-r8a77470 # RZ/G1C
              - renesas,sdhi-r8a7790  # R-Car H2
              - renesas,sdhi-r8a7791  # R-Car M2-W
              - renesas,sdhi-r8a7792  # R-Car V2H
              - renesas,sdhi-r8a7793  # R-Car M2-N
              - renesas,sdhi-r8a7794  # R-Car E2
          - const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1
      - items:
          - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
      - items:
          - enum:
              - renesas,sdhi-r8a774a1  # RZ/G2M
              - renesas,sdhi-r8a774b1  # RZ/G2N
              - renesas,sdhi-r8a774c0  # RZ/G2E
              - renesas,sdhi-r8a774e1  # RZ/G2H
              - renesas,sdhi-r8a7795   # R-Car H3
              - renesas,sdhi-r8a7796   # R-Car M3-W
              - renesas,sdhi-r8a77961  # R-Car M3-W+
              - renesas,sdhi-r8a77965  # R-Car M3-N
              - renesas,sdhi-r8a77970  # R-Car V3M
              - renesas,sdhi-r8a77980  # R-Car V3H
              - renesas,sdhi-r8a77990  # R-Car E3
              - renesas,sdhi-r8a77995  # R-Car D3
              - renesas,sdhi-r9a07g043 # RZ/G2UL
              - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
              - renesas,sdhi-r9a07g054 # RZ/V2L
          - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
      - items:
          - enum:
              - renesas,sdhi-r8a779a0  # R-Car V3U
              - renesas,sdhi-r8a779f0  # R-Car S4-8
              - renesas,sdhi-r8a779g0  # R-Car V4H
          - const: renesas,rcar-gen4-sdhi # R-Car Gen4

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 3

  clocks: true

  clock-names: true

  dmas:
    minItems: 4
    maxItems: 4

  dma-names:
    minItems: 4
    maxItems: 4
    items:
      enum:
        - tx
        - rx

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  pinctrl-0:
    minItems: 1
    maxItems: 2

  pinctrl-1:
    maxItems: 1

  pinctrl-names: true

  max-frequency: true

allOf:
  - $ref: "mmc-controller.yaml"

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,sdhi-r9a07g043
              - renesas,sdhi-r9a07g044
              - renesas,sdhi-r9a07g054
    then:
      properties:
        clocks:
          items:
            - description: IMCLK, SDHI channel main clock1.
            - description: CLK_HS, SDHI channel High speed clock which operates
                           4 times that of SDHI channel main clock1.
            - description: IMCLK2, SDHI channel main clock2. When this clock is
                           turned off, external SD card detection cannot be
                           detected.
            - description: ACLK, SDHI channel bus clock.
        clock-names:
          items:
            - const: core
            - const: clkh
            - const: cd
            - const: aclk
      required:
        - clock-names
        - resets
    else:
      if:
        properties:
          compatible:
            contains:
              enum:
                - renesas,rcar-gen2-sdhi
                - renesas,rcar-gen3-sdhi
                - renesas,rcar-gen4-sdhi
      then:
        properties:
          clocks:
            minItems: 1
            maxItems: 3
          clock-names:
            minItems: 1
            uniqueItems: true
            items:
              - const: core
              - enum: [ clkh, cd ]
              - const: cd
      else:
        properties:
          clocks:
            minItems: 1
            maxItems: 2
          clock-names:
            minItems: 1
            items:
              - const: core
              - const: cd

  - if:
      properties:
        compatible:
          contains:
            const: renesas,sdhi-mmc-r8a77470
    then:
      properties:
        pinctrl-names:
          items:
            - const: state_uhs
    else:
      properties:
        pinctrl-names:
          minItems: 1
          items:
            - const: default
            - const: state_uhs

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,sdhi-r7s72100
              - renesas,sdhi-r7s9210
    then:
      required:
        - clock-names
      description:
        The internal card detection logic that exists in these controllers is
        sectioned off to be run by a separate second clock source to allow
        the main core clock to be turned off to save power.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>

    sdhi0: mmc@ee100000 {
            compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
            reg = <0xee100000 0x328>;
            interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 314>;
            dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
            dma-names = "tx", "rx", "tx", "rx";
            max-frequency = <195000000>;
            power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
            resets = <&cpg 314>;
    };

    sdhi1: mmc@ee120000 {
             compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
             reg = <0xee120000 0x328>;
             interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
             clocks = <&cpg CPG_MOD 313>;
             dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
             dma-names = "tx", "rx", "tx", "rx";
             max-frequency = <195000000>;
             power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
             resets = <&cpg 313>;
    };

    sdhi2: mmc@ee140000 {
             compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
             reg = <0xee140000 0x100>;
             interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
             clocks = <&cpg CPG_MOD 312>;
             dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
             dma-names = "tx", "rx", "tx", "rx";
             max-frequency = <97500000>;
             power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
             resets = <&cpg 312>;
     };

     sdhi3: mmc@ee160000 {
              compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
              reg = <0xee160000 0x100>;
              interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
              clocks = <&cpg CPG_MOD 311>;
              dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
              dma-names = "tx", "rx", "tx", "rx";
              max-frequency = <97500000>;
              power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
              resets = <&cpg 311>;
    };