code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright (c) 2020 Protonic Holland
 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "imx6ull.dtsi"

/ {
	model = "JOZ Access Point";
	compatible = "joz,jozacp", "fsl,imx6ull";

	chosen {
		stdout-path = &uart1;
	};

	/* On board name LED_RGB1 */
	led-controller-1 {
		compatible = "pwm-leds";

		led-0 {
			color = <LED_COLOR_ID_RED>;
			function = LED_FUNCTION_INDICATOR;
			function-enumerator = <0>;
			pwms = <&pwm1 0 10000000 0>;
			max-brightness = <255>;
		};

		led-1 {
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_INDICATOR;
			function-enumerator = <1>;
			pwms = <&pwm3 0 10000000 0>;
			max-brightness = <255>;
		};

		led-2 {
			color = <LED_COLOR_ID_BLUE>;
			function = LED_FUNCTION_INDICATOR;
			function-enumerator = <2>;
			pwms = <&pwm5 0 10000000 0>;
			max-brightness = <255>;
			linux,default-trigger = "heartbeat";
		};
	};

	/* On board name LED_RGB2 */
	led-controller-2 {
		compatible = "pwm-leds";

		led-3 {
			color = <LED_COLOR_ID_RED>;
			function = LED_FUNCTION_INDICATOR;
			function-enumerator = <3>;
			pwms = <&pwm2 0 10000000 0>;
			max-brightness = <255>;
		};

		led-4 {
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_INDICATOR;
			function-enumerator = <4>;
			pwms = <&pwm4 0 10000000 0>;
			max-brightness = <255>;
		};

		led-5 {
			color = <LED_COLOR_ID_BLUE>;
			function = LED_FUNCTION_INDICATOR;
			function-enumerator = <5>;
			pwms = <&pwm6 0 10000000 0>;
			max-brightness = <255>;
		};
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&reg_5v0>;
	};

	reg_5v0: regulator-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_vbus: regulator-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_vbus>;
		regulator-name = "vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&reg_5v0>;
		gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq {
		compatible = "mmc-pwrseq-simple";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_wifi_npd>;
		reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can1>;
	status = "okay";
};

&cpu0 {
	clock-frequency = <792000000>;
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			reg = <0>;
			clocks = <&clks IMX6UL_CLK_ENET_REF>;
			clock-names = "rmii-ref";
			interrupts-extended = <&gpio1 29 IRQ_TYPE_LEVEL_LOW>;
			reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			reset-deassert-us = <300>;
		};
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clock-frequency = <100000>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clock-frequency = <100000>;
	status = "okay";

	rtc@51 {
		compatible = "nxp,pcf8563";
		reg = <0x51>;
	};
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "okay";
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
};

&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "okay";
};

&pwm5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm5>;
	status = "okay";
};

&pwm6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm6>;
	status = "okay";
};

&snvs_rtc {
	status = "disabled";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	dtr-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	vbus-supply = <&reg_vbus>;
	dr_mode = "host";
	over-current-active-low;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	vmmc-supply = <&reg_3v3>;
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	cap-mmc-hw-reset;
	no-sd;
	no-sdio;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
	bus-width = <4>;
	no-1-8-v;
	no-mmc;
	no-sd;
	non-removable;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	wifi@1 {
		compatible = "brcm,bcm4329-fmac";
		reg = <1>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_can1: can1grp {
		fsl,pins = <
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b0b0
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b0b0
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC	 0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031

			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28	0x038b0
			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x170b0
		>;
	};

	pinctrl_hog: hoggrp {
		fsl,pins = <
			/* HW Revision */
			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09	0x1b0b0
			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x1b0b0

			/* HW ID */
			MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15	0x1b0b0

			/* Digital inputs */
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x11000
			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0x11000
			MX6UL_PAD_GPIO1_IO05__GPIO1_IO05	0x11000
			MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0x11000
			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09	0x11000

			/* Isolated outputs */
			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x01020
			MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21	0x01020
			MX6UL_PAD_UART2_RTS_B__GPIO1_IO23	0x01020
			MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x01020
			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x01020
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001f8b1
			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001f8b1
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001f8b1
			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001f8b1
		>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__PWM1_OUT		0x01010
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA01__PWM2_OUT		0x01010
		>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA02__PWM3_OUT		0x01010
		>;
	};

	pinctrl_pwm4: pwm4grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA03__PWM4_OUT		0x01010
		>;
	};

	pinctrl_pwm5: pwm5grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA18__PWM5_OUT		0x01010
		>;
	};

	pinctrl_pwm6: pwm6grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA19__PWM6_OUT		0x01010
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__UART4_DCE_TX		0x1b0b0
			MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX	0x1b0b0
			MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS	0x1b0b0
			MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS	0x1b0b0
			MX6UL_PAD_LCD_RESET__GPIO3_IO04		0x1b0b0
		>;
	};

	pinctrl_usbotg1: usbotg1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC	0x1b0b0
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B	0x17099
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x1f099
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10099
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17099
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17099
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17099
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17099
			MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17099
			MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17099
			MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17099
			MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17099
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x100b9
			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x170b9
			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x170b9
			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x170b9
			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x170b9
			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x170b9
		>;
	};

	pinctrl_vbus: vbus0grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0x030b0
		>;
	};

	pinctrl_wifi_npd: wifigrp {
		fsl,pins = <
			/* WL_REG_ON */
			MX6UL_PAD_CSI_DATA04__GPIO4_IO25	0x03020
		>;
	};
};

&iomuxc_snvs {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_snvs_hog>;

	pinctrl_snvs_hog: snvs-hog-grp {
		fsl,pins = <
			/* Digital outputs */
			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x00020
			MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x00020
			MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x00020
			MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x00020
			MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x00020

			/* Digital outputs fault feedback */
			MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x17000
			MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17000
			MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x17000
			MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17000
			MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x17000
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017 exceet electronics GmbH
 * Copyright (C) 2019 Kontron Electronics GmbH
 */

/dts-v1/;

#include "imx6ull-kontron-sl.dtsi"
#include "imx6ul-kontron-bl-common.dtsi"

/ {
	model = "Kontron BL i.MX6ULL (N641X S)";
	compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017 exceet electronics GmbH
 * Copyright (C) 2018 Kontron Electronics GmbH
 */

#include "imx6ull.dtsi"
#include "imx6ul-kontron-sl-common.dtsi"

/ {
	model = "Kontron SL i.MX6ULL (N641X SOM)";
	compatible = "kontron,sl-imx6ull", "fsl,imx6ull";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020 Linumiz
 * Author: Parthiban Nallathambi <parthiban@linumiz.com>
 */

/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-myir-mys-6ulx.dtsi"

/ {
	model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND";
	compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull";
};

&gpmi {
	fsl,use-minimum-ecc;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020 Linumiz
 * Author: Parthiban Nallathambi <parthiban@linumiz.com>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>

/ {
	model = "MYiR MYS-6ULX Single Board Computer";
	compatible = "fsl,imx6ull";

	chosen {
		stdout-path = &uart1;
	};

	reg_vdd_5v: regulator-vdd-5v {
		compatible = "regulator-fixed";
		regulator-name = "VDD_5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_vdd_3v3: regulator-vdd-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "VDD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		vin-supply = <&reg_vdd_5v>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	phy-supply = <&reg_vdd_3v3>;
	status = "okay";

	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			reg = <0>;
			interrupt-parent = <&gpio5>;
			interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&clks IMX6UL_CLK_ENET_REF>;
			clock-names = "rmii-ref";
		};
	};
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	status = "disabled";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1_id>;
	dr_mode = "otg";
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&reg_vdd_3v3>;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	bus-width = <8>;
	non-removable;
	keep-power-in-suspend;
	vmmc-supply = <&reg_vdd_3v3>;
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0
		>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x0b0b1
			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x0b0b1
			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0x0b0b1
			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x0b000
			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x0b0b1
			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x0b0b1
			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x0b0b1
			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x0b0b1
			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x0b0b1
			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x0b0b1
			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x0b0b1
			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x0b0b1
			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x0b0b1
			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x0b0b1
			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x0b0b1
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_usb_otg1_id: usbotg1idgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10069
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x17059
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x17059
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x17059
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x17059
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100b9
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170b9
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170b9
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170b9
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170b9
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170b9
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170b9
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170b9
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170b9
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170b9
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100f9
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170f9
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170f9
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170f9
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170f9
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170f9
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170f9
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170f9
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170f9
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170f9
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2019 Armadeus Systems <support@armadeus.com>

#include "imx6ull.dtsi"
#include "imx6ul-imx6ull-opos6ul.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2019 Armadeus Systems <support@armadeus.com>

/dts-v1/;
#include "imx6ull-opos6ul.dtsi"
#include "imx6ul-imx6ull-opos6uldev.dtsi"

/ {
	model = "Armadeus Systems OPOS6UL SoM (i.MX6ULL) on OPOS6ULDev board";
	compatible = "armadeus,imx6ull-opos6uldev", "armadeus,imx6ull-opos6ul", "fsl,imx6ull";
};

&iomuxc_snvs {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_tamper_gpios>;

	pinctrl_tamper_gpios: tampergpiosgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x0b0b0
			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x0b0b0
			MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x0b0b0
			MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x0b0b0
			MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x0b0b0
			MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x0b0b0
			MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x0b0b0
			MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x0b0b0
		>;
	};

	pinctrl_usbotg2_vbus: usbotg2vbusgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x1b0b0
		>;
	};

	pinctrl_w1: w1grp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x0b0b0
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 PHYTEC Messtechnik GmbH
 * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
 */

#include "imx6ul-phytec-phycore-som.dtsi"

/ {
	model = "PHYTEC phyCORE-i.MX6 ULL";
	compatible = "phytec,imx6ull-pcl063", "fsl,imx6ull";
};

&iomuxc {
	/delete-node/ gpioledssomgrp;
};

&iomuxc_snvs {
	pinctrl_gpioleds_som: gpioledssomgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x0b0b0
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 PHYTEC Messtechnik GmbH
 * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
 */

/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-phytec-phycore-som.dtsi"
#include "imx6ull-phytec-segin.dtsi"
#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
#include "imx6ull-phytec-segin-peb-av-02.dtsi"

/ {
	model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC";
	compatible = "phytec,imx6ull-pbacd10-emmc", "phytec,imx6ull-pbacd10",
		     "phytec,imx6ull-pcl063","fsl,imx6ull";
};

&adc1 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&tlv320 {
	status = "okay";
};

&ecspi3 {
	status = "okay";
};

&ethphy1 {
	status = "okay";
};

&ethphy2 {
	status = "okay";
};

&fec1 {
	status = "okay";
};

&fec2 {
	status = "okay";
};

&i2c_rtc {
	status = "okay";
};

&reg_can1_en {
	status = "okay";
};

&reg_sound_1v8 {
	status = "okay";
};

&reg_sound_3v3 {
	status = "okay";
};

&sai2 {
	status = "okay";
};

&sound {
	status = "okay";
};

&uart5 {
	status = "okay";
};

&usbotg1 {
	status = "okay";
};

&usbotg2 {
	status = "okay";
};

&usdhc1 {
	status = "okay";
};

&usdhc2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 PHYTEC Messtechnik GmbH
 * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
 */

/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-phytec-phycore-som.dtsi"
#include "imx6ull-phytec-segin.dtsi"
#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
#include "imx6ull-phytec-segin-peb-av-02.dtsi"
#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi"

/ {
	model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND";
	compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
		     "phytec,imx6ull-pcl063", "fsl,imx6ull";
};

&adc1 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&tlv320 {
	status = "okay";
};

&ecspi3 {
	status = "okay";
};

&ethphy1 {
	status = "okay";
};

&ethphy2 {
	status = "okay";
};

&fec1 {
	status = "okay";
};

&fec2 {
	status = "okay";
};

&gpmi {
	status = "okay";
};

&i2c_rtc {
	status = "okay";
};

&reg_can1_en {
	status = "okay";
};

&reg_sound_1v8 {
	status = "okay";
};

&reg_sound_3v3 {
	status = "okay";
};

&sai2 {
	status = "okay";
};

&sound {
	status = "okay";
};

&uart5 {
	status = "okay";
};

&usbotg1 {
	status = "okay";
};

&usbotg2 {
	status = "okay";
};

&usdhc1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 PHYTEC Messtechnik GmbH
 * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
 */

/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-phytec-phycore-som.dtsi"
#include "imx6ull-phytec-segin.dtsi"
#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
#include "imx6ull-phytec-segin-peb-wlbt-05.dtsi"

/ {
	model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND";
	compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
		     "phytec,imx6ull-pcl063", "fsl,imx6ull";
};

&adc1 {
	status = "okay";
};

&ethphy1 {
	status = "okay";
};

&fec1 {
	status = "okay";
};

&gpmi {
	status = "okay";
};

&i2c_rtc {
	status = "okay";
};

&usbotg1 {
	status = "okay";
};

&usdhc1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright (C) 2018 PHYTEC Messtechnik GmbH
 * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
 */

#include "imx6ul-phytec-segin-peb-av-02.dtsi"

&iomuxc {
	/delete-node/ edtft5406grp;
	/delete-node/ stmpegrp;
};

&iomuxc_snvs {
	pinctrl_edt_ft5406: edtft5406grp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0
		>;
	};

	pinctrl_stmpe: stmpegrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x17059
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 PHYTEC Messtechnik GmbH
 * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
 */

#include "imx6ul-phytec-segin-peb-eval-01.dtsi"

&iomuxc {
	/delete-node/ gpio_keysgrp;
};

&iomuxc_snvs {
	pinctrl_gpio_keys: gpio_keysgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x79
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2021 PHYTEC Messtechnik GmbH
 * Author: Yunus Bas <y.bas@phytec.de>
 */

#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"

&iomuxc {
	/delete-node/ wlgrp;
};

&iomuxc_snvs {
	pinctrl_wl: wlgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x3031
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 PHYTEC Messtechnik GmbH
 * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
 */

#include "imx6ul-phytec-segin.dtsi"

/ {
	model = "PHYTEC phyBOARD-Segin i.MX6 ULL";
	compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull";
};

&iomuxc {
	/delete-node/ flexcan1engrp;
	/delete-node/ rtcintgrp;
};

&iomuxc_snvs {
	princtrl_flexcan1_en: flexcan1engrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x17059
		>;
	};

	pinctrl_rtc_int: rtcintgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17059
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2021 PHYTEC Messtechnik GmbH
 * Author: Alexander Bauer <a.bauer@phytec.de>
 */

/dts-v1/;
#include "imx6ull-phytec-tauri.dtsi"

/ {
	model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
	compatible = "phytec,imx6ull-phygate-tauri",
		     "phytec,imx6ull-phygate-tauri-emmc",
		     "phytec,imx6ull-pcl063", "fsl,imx6ull";
};

/* EMMC-Version */
&usdhc2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2021 PHYTEC Messtechnik GmbH
 * Author: Alexander Bauer <a.bauer@phytec.de>
 */

/dts-v1/;
#include "imx6ull-phytec-tauri.dtsi"

/ {
	model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
	compatible = "phytec,imx6ull-phygate-tauri",
		     "phytec,imx6ull-phygate-tauri-nand",
		     "phytec,imx6ull-pcl063", "fsl,imx6ull";
};

/* NAND-Version */
&gpmi {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2021 PHYTEC Messtechnik GmbH
 * Author: Alexander Bauer <a.bauer@phytec.de>
 */

/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-phytec-phycore-som.dtsi"

/ {

	model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
	compatible = "phytec,imx6ull-phygate-tauri",
		     "phytec,imx6ull-pcl063", "fsl,imx6ull";

	aliases {
		rtc0 = &i2c_rtc;
		rtc1 = &snvs_rtc;
	};

	gpio_keys: gpio-keys {
		compatible = "gpio-key";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;

		key {
			label = "KEY-A";
			gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_A>;
			wakeup-source;
		};
	};

	reg_adc1_vref_3v3: regulator-vref-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vref-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_s25fl064_hold: regulator-s25fl064-hold {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_s25fl064_hold>;
		compatible = "regulator-fixed";
		regulator-name = "s25fl064_hold";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};

	reg_usb_hub_vbus: regulator-hub-otg1-vbus {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbhubpwr>;
		compatible = "regulator-fixed";
		regulator-name = "usb_hub_vbus";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};

	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbotg1pwr>;
		compatible = "regulator-fixed";
		regulator-name = "usb_otg1_vbus";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};

	user_leds: user-leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_user_leds>,
			    <&pinctrl_user_leds_snvs>;

		user-led1 {
			label = "yellow";
			gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "off";
		};

		user-led2 {
			label = "red";
			gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "off";
		};
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "okay";
};

&ecspi1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>,
		    <&pinctrl_ecspi1_cs>;
	cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>,
		   <&gpio3 10 GPIO_ACTIVE_LOW>,
		   <&gpio3 11 GPIO_ACTIVE_LOW>;
	status = "okay";

	tpm_tis: tpm@1 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tpm>;
		compatible = "tcg,tpm_tis-spi";
		reg = <1>;
		spi-max-frequency = <20000000>;
		interrupt-parent = <&gpio5>;
		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
	};

	s25fl064: flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = " jedec,spi-nor";
		reg = <2>;
		spi-max-frequency = <40000000>;
		m25p,fast-read;
		status = "disabled";
	};
};

&ecspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
	dmas = <&sdma 7 8 0>,
	       <&sdma 8 8 0>;
	dma-names = "rx", "tx";
	status = "okay";
};

&ethphy1 {
	status = "okay";
};

&fec1 {
	status = "okay";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rmii";
	phy-handle = <&ethphy2>;
	status = "okay";
};

&i2c1 {
	status = "okay";

	tmp102: tmp@49 {
		compatible = "ti,tmp102";
		reg = <0x49>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tempsense>;
		interrupt-parent = <&gpio5>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
		#thermal-sensor-cells = <1>;
	};

	i2c_rtc: rtc@68 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_rtc_int>;
		compatible = "microcrystal,rv4162";
		reg = <0x68>;
		interrupt-parent = <&gpio5>;
		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
	};
};

&i2c2 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&i2c3 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&i2c4 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&mdio {
	ethphy2: ethernet-phy@2 {
		reg = <2>;
		micrel,led-mode = <1>;
		clocks = <&clks IMX6UL_CLK_ENET2_REF>;
		clock-names = "rmii-ref";
		status = "okay";
	};
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
};

&pwm6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm6>;
	status = "okay";
};

&pwm7 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm7>;
	status = "okay";
};

&pwm8 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm8>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

/* UART4 * RS485  */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
	rs485-rts-active-high;
	linux,rs485-enabled-at-boot-time;
	status = "okay";
};

/* UART5 * RS232  */
&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	uart-has-rtscts;
	status = "okay";
};

&uart7 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart7>;
	status = "okay";
};

/* USB */
&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1>;
	vbus-supply = <&reg_usb_otg1_vbus>;
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usb_hub_vbus>;
	disable-over-current;
	dr_mode = "host";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	status = "okay";
};

&usdhc2 {
	status = "disabled";
};

&iomuxc_snvs {
	pinctrl_rtc_int: rtcintgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17059
		>;
	};

	pinctrl_stmpe: stmpegrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x17059
		>;
	};

	pinctrl_tempsense: tempsensegrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x17059
		>;
	};

	pinctrl_tpm: tpmgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x17059
		>;
	};

	pinctrl_usbhubpwr: usbhubpwrgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x17059
		>;
	};

	pinctrl_user_leds_snvs: user_ledsgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x79
		>;
	};
};

&iomuxc {
	pinctrl_gpio: gpiogrp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x17059  /* nUART_MUX_RS232 */
			MX6UL_PAD_CSI_DATA04__GPIO4_IO25	0x17059  /* nUART_MUX_DUAL_RX_TX */
		>;
	};

	pinctrl_gpio_keys: gpiokeysgrp {
		fsl,pins = <
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x79
		>;
	};

	pinctrl_ecspi3: ecspi3grp {
		fsl,pins = <
			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x100b1
			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x100b1
			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x100b1
			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x10b0
		>;
	};

	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK	0x100b1
			MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	0x100b1
			MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	0x100b1
		>;
	};

	pinctrl_ecspi1_cs: ecspi1csgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x10b0
			MX6UL_PAD_LCD_DATA05__GPIO3_IO10	0x10b0
			MX6UL_PAD_LCD_DATA06__GPIO3_IO11	0x10b0
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b010
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b010
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b010
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b010
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x0b0b0
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x0b0b0
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX	0x0b0b0
			MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX	0x0b0b0
		>;
	};

	princtrl_flexcan2_en: flexcan2engrp {
		fsl,pins = <
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x17059
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__I2C2_SCL	0xb0
			MX6UL_PAD_GPIO1_IO01__I2C2_SDA	0xb0
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0xb0
			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA01__I2C3_SCL	0xb0
			MX6UL_PAD_LCD_DATA00__I2C3_SDA	0xb0
		>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA01__GPIO3_IO06	0xb0
			MX6UL_PAD_LCD_DATA00__GPIO3_IO05	0xb0
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA03__I2C4_SCL	0xb0
			MX6UL_PAD_LCD_DATA02__I2C4_SDA	0xb0
		>;
	};

	pinctrl_i2c4_gpio: i2c4gpiogrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA03__GPIO3_IO08	0xb0
			MX6UL_PAD_LCD_DATA02__GPIO3_IO07	0xb0
		>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO04__PWM3_OUT	0x0b0b0
		>;
	};

	pinctrl_pwm6: pwm6grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TDI__PWM6_OUT	0x0b0b0
		>;
	};

	pinctrl_pwm7: pwm7grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TCK__PWM7_OUT	0x0b0b0
		>;
	};

	pinctrl_pwm8: pwm8grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TRST_B__PWM8_OUT	0x0b0b0
		>;
	};

	pinctrl_s25fl064_hold: s25fl064holdgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA12__GPIO3_IO17	0x100b1
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b1
			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__UART4_DCE_TX		0x1b0b1
			MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX	0x1b0b1
			MX6UL_PAD_LCD_HSYNC__GPIO3_IO02	0x1b0b1
		>;
	};

	pinctrl_uart5: uart5grp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0b1
			MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_uart7: uart7grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA16__UART7_DCE_TX	0x1b0b1
			MX6UL_PAD_LCD_DATA17__UART7_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_usb_otg1: usbotg1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA06__GPIO4_IO27	0x80
		>;
	};

	pinctrl_usbotg1pwr: usbotg1pwrgrp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA07__GPIO4_IO28	0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
		>;
	};

	pinctrl_user_leds: userledsgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x79
		>;
	};
};


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright (C) 2017 NXP
 */

#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H
#define __DTS_IMX6ULL_PINFUNC_SNVS_H
/*
 * The pin function ID is a tuple of
 * <mux_reg conf_reg input_reg mux_mode input_val>
 */
#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10                          0x0000 0x0044 0x0000 0x5 0x0
#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11                          0x0004 0x0048 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00                        0x0008 0x004C 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01                        0x000C 0x0050 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02                        0x0010 0x0054 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03                        0x0014 0x0058 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04                        0x0018 0x005C 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05                        0x001C 0x0060 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06                        0x0020 0x0064 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07                        0x0024 0x0068 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08                        0x0028 0x006C 0x0000 0x5 0x0
#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09                        0x002C 0x0070 0x0000 0x5 0x0

#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 */

#ifndef __DTS_IMX6ULL_PINFUNC_H
#define __DTS_IMX6ULL_PINFUNC_H

#include "imx6ul-pinfunc.h"
/*
 * The pin function ID is a tuple of
 * <mux_reg conf_reg input_reg mux_mode input_val>
 */
/* signals common for i.MX6UL and i.MX6ULL */
#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX
#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX                    0x00BC 0x0348 0x0644 0x0 0x6
#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX
#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX                    0x00C0 0x034C 0x0644 0x0 0x7
#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS
#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS                     0x00CC 0x0358 0x0640 0x1 0x5
#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS
#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS                  0x00D0 0x035C 0x0640 0x1 0x6
#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS
#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS                      0x01EC 0x0478 0x0640 0x8 0x7

/* signals for i.MX6ULL only */
#define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX                    0x0084 0x0310 0x0000 0x9 0x0
#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX                    0x0084 0x0310 0x0644 0x9 0x4
#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX                    0x0088 0x0314 0x0644 0x9 0x5
#define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX                    0x0088 0x0314 0x0000 0x9 0x0
#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS                     0x008C 0x0318 0x0000 0x9 0x0
#define MX6ULL_PAD_UART1_CTS_B__UART5_DTE_RTS                     0x008C 0x0318 0x0640 0x9 0x3
#define MX6ULL_PAD_UART1_RTS_B__UART5_DCE_RTS                     0x0090 0x031C 0x0640 0x9 0x4
#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_CTS                     0x0090 0x031C 0x0000 0x9 0x0
#define MX6ULL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01                  0x00B8 0x0344 0x0000 0x9 0x0
#define MX6ULL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02                  0x00BC 0x0348 0x0000 0x9 0x0
#define MX6ULL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03                  0x00C0 0x034C 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04                    0x00C4 0x0350 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05                    0x00C8 0x0354 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06                       0x00CC 0x0358 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07                    0x00D0 0x035C 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08                    0x00D4 0x0360 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09                       0x00D8 0x0364 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED                       0x00DC 0x0368 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ                        0x00E0 0x036C 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08                    0x00E4 0x0370 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09                    0x00E8 0x0374 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10                       0x00EC 0x0378 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11                    0x00F0 0x037C 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12                    0x00F4 0x0380 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13                       0x00F8 0x0384 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14                      0x00FC 0x0388 0x0000 0x9 0x0
#define MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15                       0x0100 0x038C 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_CLK__EPDC_SDCLK                            0x0104 0x0390 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE                          0x0108 0x0394 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE                           0x010C 0x0398 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0                          0x0110 0x039C 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_RESET__EPDC_GDOE                           0x0114 0x03A0 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00                        0x0118 0x03A4 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01                        0x011C 0x03A8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02                        0x0120 0x03AC 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03                        0x0124 0x03B0 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04                        0x0128 0x03B4 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05                        0x012C 0x03B8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06                        0x0130 0x03BC 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07                        0x0134 0x03C0 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR                         0x0150 0x03DC 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA15__EPDC_GDRL                          0x0154 0x03E0 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK                         0x0158 0x03E4 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP                          0x015C 0x03E8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1                         0x016C 0x03F8 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02                        0x0170 0x03FC 0x0000 0x9 0x0
#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03                        0x0174 0x0400 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2                         0x01D4 0x0460 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3                       0x01D8 0x0464 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1                        0x01DC 0x0468 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_HSYNC__ESAI_TX1                            0x01E0 0x046C 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK                     0x01E4 0x0470 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK                     0x01E8 0x0474 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS                         0x01EC 0x0478 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK                        0x01F0 0x047C 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS                         0x01F4 0x0480 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK                        0x01F8 0x0484 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0                       0x01FC 0x0488 0x0000 0x9 0x0
#define MX6ULL_PAD_CSI_DATA07__ESAI_TX0                           0x0200 0x048C 0x0000 0x9 0x0

#endif /* __DTS_IMX6ULL_PINFUNC_H */


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2018-2022 TQ-Systems GmbH
 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
 */

/dts-v1/;

#include "imx6ull-tqma6ull2.dtsi"
#include "mba6ulx.dtsi"

/ {
	model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board";
	compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
};


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2018-2022 TQ-Systems GmbH
 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
 */

#include "imx6ull.dtsi"
#include "imx6ul-tqma6ul-common.dtsi"
#include "imx6ul-tqma6ulx-common.dtsi"

/ {
	model = "TQ-Systems TQMa6ULL2 SoM";
	compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
};

&usdhc2 {
	fsl,tuning-step = <6>;
	/* Errata ERR010450 Workaround */
	max-frequency = <99000000>;
	assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
	assigned-clock-rates = <0>, <198000000>;
};

&iomuxc {
	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x00017031
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x00017039
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x00017039
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x00017039
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x00017039
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x00017039
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x00017039
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x00017039
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x00017039
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x00017039
			/* rst */
			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x0001b051
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x000170f1
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x000170f1
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x000170f1
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x000170f1
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x000170f1
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x000170f1
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x000170f1
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x000170f1
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x000170f1
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x000170f1
			/* rst */
			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x0001b051
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x000170f1
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x000170f1
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x000170f1
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x000170f1
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x000170f1
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x000170f1
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x000170f1
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x000170f1
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x000170f1
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x000170f1
			/* rst */
			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x0001b051
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2018-2022 TQ-Systems GmbH
 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
 */

/dts-v1/;

#include "imx6ull-tqma6ull2l.dtsi"
#include "mba6ulx.dtsi"

/ {
	model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board";
	compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
};


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2018-2022 TQ-Systems GmbH
 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
 */

#include "imx6ull.dtsi"
#include "imx6ul-tqma6ul-common.dtsi"
#include "imx6ul-tqma6ulxl-common.dtsi"

/ {
	model = "TQ Systems TQMa6ULL2L SoM";
	compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
};

&usdhc2 {
	fsl,tuning-step = <6>;
	/* Errata ERR010450 Workaround */
	max-frequency = <99000000>;
	assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
	assigned-clock-rates = <0>, <198000000>;
};

&iomuxc {
	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x00017031
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x00017039
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x00017039
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x00017039
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x00017039
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x00017039
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x00017039
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x00017039
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x00017039
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x00017039
			/* rst */
			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x0001b051
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x000170f1
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x000170f1
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x000170f1
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x000170f1
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x000170f1
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x000170f1
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x000170f1
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x000170f1
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x000170f1
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x000170f1
			/* rst */
			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x0001b051
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x000170f1
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x000170f1
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x000170f1
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x000170f1
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x000170f1
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x000170f1
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x000170f1
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x000170f1
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x000170f1
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x000170f1
			/* rst */
			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x0001b051
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2016 Freescale Semiconductor, Inc.

#include "imx6ul.dtsi"
#include "imx6ull-pinfunc.h"
#include "imx6ull-pinfunc-snvs.h"

/* Delete UART8 in AIPS-1 (i.MX6UL specific) */
/delete-node/ &uart8;
/* Delete CAAM node in AIPS-2 (i.MX6UL specific) */
/delete-node/ &crypto;

&cpu0 {
	clock-frequency = <900000000>;
	operating-points = <
		/* kHz	uV */
		900000	1275000
		792000	1225000
		528000	1175000
		396000	1025000
		198000	950000
	>;
	fsl,soc-operating-points = <
		/* KHz	uV */
		900000	1250000
		792000	1175000
		528000	1175000
		396000	1175000
		198000	1175000
	>;
};

&ocotp {
	compatible = "fsl,imx6ull-ocotp", "syscon";
};

&pxp {
	compatible = "fsl,imx6ull-pxp";
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
};

&usdhc1 {
	compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
};

&usdhc2 {
	compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
};

/ {
	soc: soc {
		aips3: bus@2200000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02200000 0x100000>;
			ranges;

			dcp: crypto@2280000 {
				compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp";
				reg = <0x02280000 0x4000>;
				interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
				clock-names = "dcp";
			};

			rngb: rng@2284000 {
				compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb";
				reg = <0x02284000 0x4000>;
				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_DUMMY>;
			};

			iomuxc_snvs: iomuxc-snvs@2290000 {
				compatible = "fsl,imx6ull-iomuxc-snvs";
				reg = <0x02290000 0x4000>;
			};

			uart8: serial@2288000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart";
				reg = <0x02288000 0x4000>;
				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_UART8_IPG>,
					 <&clks IMX6UL_CLK_UART8_SERIAL>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2018 NXP.

/dts-v1/;

#include "imx6ulz.dtsi"
#include "imx6ul-14x14-evk.dtsi"

/delete-node/ &fec1;
/delete-node/ &fec2;
/delete-node/ &can1;
/delete-node/ &can2;
/delete-node/ &lcdif;
/delete-node/ &tsc;

/ {
	model = "Freescale i.MX6 ULZ 14x14 EVK Board";
	compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";

	/delete-node/ panel;
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2021 BSH Hausgeraete GmbH
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include "imx6ulz.dtsi"

/ {
	model = "BSH SMM M2";
	compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz";

	chosen {
		stdout-path = &uart4;
	};

	usdhc2_pwrseq: usdhc2-pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
	};
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	status = "okay";
};

&snvs_poweroff {
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
		compatible = "brcm,bcm4330-bt";
		max-speed = <3000000>;
		shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
		device-wakeup-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
		host-wakeup-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
	};
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "peripheral";
	srp-disable;
	hnp-disable;
	adp-disable;
	status = "okay";
};

&usbphy1 {
	fsl,tx-d-cal = <106>;
};

&usdhc2 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wlan>;
	bus-width = <4>;
	no-1-8-v;
	non-removable;
	cap-power-off-card;
	keep-power-in-suspend;
	cap-sdio-irq;
	mmc-pwrseq = <&usdhc2_pwrseq>;
	status = "okay";

	brcmf: wifi@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
		interrupt-parent = <&gpio1>;
		interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "host-wake";
	};
};

&wdog1 {
	status = "okay";
};

&iomuxc {
	pinctrl_gpmi_nand: gpmi-nand {
		fsl,pins = <
			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0xb0b1
			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0xb0b1
			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0xb0b1
			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0xb000
			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0xb0b1
			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0xb0b1
			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0xb0b1
			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0xb0b1
			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0xb0b1
			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0xb0b1
			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0xb0b1
			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0xb0b1
			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0xb0b1
			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0xb0b1
			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0xb0b1
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b1
			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b099
			MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS	0x1b0b1
			MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS	0x1b099
			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0x79		/* BT_REG_ON */
			MX6UL_PAD_SD1_CLK__GPIO2_IO17		0x100b1		/* BT_DEV_WAKE out */
			MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13	0x1b0b0		/* BT_HOST_WAKE in */
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX	0x1b0b1
			MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_wlan: wlangrp {
		fsl,pins = <
			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x10059
			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x17059
			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x17059
			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x17059
			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
			MX6UL_PAD_SD1_DATA3__GPIO2_IO21		0x79		/* WL_REG_ON */
			MX6UL_PAD_UART2_CTS_B__GPIO1_IO22	0x100b1		/* WL_DEV_WAKE - WiFi_GPIO_4 - WiFi FW UART */
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x1b0b1		/* WL_HOST_WAKE - WIFI_GPIO_0 - OOB IRQ */
			MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT	0x4001b031	/* OSC 32Khz wifi clk in */
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2018 NXP.

#include "imx6ull.dtsi"

/ {
	aliases {
		/delete-property/ ethernet0;
		/delete-property/ ethernet1;
		/delete-property/ i2c2;
		/delete-property/ i2c3;
		/delete-property/ serial4;
		/delete-property/ serial5;
		/delete-property/ serial6;
		/delete-property/ serial7;
		/delete-property/ spi2;
		/delete-property/ spi3;
	};
};

/delete-node/ &adc1;
/delete-node/ &ecspi3;
/delete-node/ &ecspi4;
/delete-node/ &epit2;
/delete-node/ &gpt2;
/delete-node/ &i2c3;
/delete-node/ &i2c4;
/delete-node/ &pwm5;
/delete-node/ &pwm6;
/delete-node/ &pwm7;
/delete-node/ &pwm8;
/delete-node/ &uart5;
/delete-node/ &uart6;
/delete-node/ &uart7;
/delete-node/ &uart8;


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2017-2022 Toradex
 */

/* Colibri AD0 to AD3 */
&adc1 {
	status = "okay";
};

/* Colibri SSP */
&ecspi3 {
	cs-gpios = <
		&gpio4 11 GPIO_ACTIVE_LOW /* SODIMM 86 / regular SSPFRM as UNO_SPI_CS or  */
		&gpio4 23 GPIO_ACTIVE_LOW /* SODIMM 65 / already muxed pinctrl_gpio2 as SPI_CE0_N */
		&gpio4 22 GPIO_ACTIVE_LOW /* SODIMM 85 / already muxed pinctrl_gpio2 as SPI_CE1_N */
	>;
	status = "okay";
};

/* Colibri Fast Ethernet */
&fec1 {
	status = "okay";
};

/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
&i2c4 {
	status = "okay";
};

/* Colibri PWM<A> */
&pwm1 {
	status = "okay";
};

/* Colibri PWM<B> */
&pwm2 {
	status = "okay";
};

/* Colibri PWM<C> */
&pwm3 {
	status = "okay";
};

/* Colibri PWM<D> */
&pwm4 {
	status = "okay";
};

/* M41T0M6 real time clock */
&rtc {
	status = "okay";
};

/* Colibri UART_A */
&uart1 {
	status = "okay";
};

/* Colibri UART_B */
&uart2 {
	status = "okay";
};

/* Colibri UART_C */
&uart3 {
	status = "okay";
};

/* Colibri USBC */
&usbotg1 {
	status = "okay";
};

/* Colibri MMC/SD */
&usdhc1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2016-2022 Toradex
 */

/ {
	/* Fixed crystal dedicated to MCP2515. */
	clk16m: clk16m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <16000000>;
	};
};

/* Colibri AD0 to AD3 */
&adc1 {
	status = "okay";
};

/*
 * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
 * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
 */
&atmel_mxt_ts {
	interrupt-parent = <&gpio1>;
	interrupts = <9 IRQ_TYPE_EDGE_FALLING>;		/* SODIMM 28 / INT */
	pinctrl-0 = <&pinctrl_atmel_adapter>;
	reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;	/* SODIMM 30 / RST */
	status = "disabled";
};

/* Colibri SSP */
&ecspi3 {
	status = "okay";

	mcp2515: can@0 {
		clocks = <&clk16m>;
		compatible = "microchip,mcp2515";
		interrupt-parent = <&gpio5>;
		interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_can_int>;
		reg = <0>;
		spi-max-frequency = <10000000>;
		vdd-supply = <&reg_3v3>;
		xceiver-supply = <&reg_5v0>;
	};
};

/* Colibri Fast Ethernet */
&fec1 {
	status = "okay";
};

/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
&i2c4 {
	status = "okay";
};

/* Colibri PWM<A> */
&pwm1 {
	status = "okay";
};

/* Colibri PWM<B> */
&pwm2 {
	/* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
	status = "okay";
};

/* Colibri PWM<C> */
&pwm3 {
	/* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
	status = "okay";
};

/* Colibri PWM<D> */
&pwm4 {
	status = "okay";
};

/* M41T0M6 real time clock */
&rtc {
	status = "okay";
};

/* Colibri UART_A */
&uart1 {
	status = "okay";
};

/* Colibri UART_B */
&uart2 {
	status = "okay";
};

/* Colibri UART_C */
&uart3 {
	status = "okay";
};

/* Colibri USBC */
&usbotg1 {
	status = "okay";
};

/* Colibri MMC/SD */
&usdhc1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

/ {
	reg_3v3_vmmc: regulator-3v3-vmmc {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* SODIMM 100 */
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "3v3_vmmc";
		startup-delay-us = <100>;
	};
};

/* Colibri AD0 to AD3 */
&adc1 {
	status = "okay";
};

/* Colibri SSP */
&ecspi3 {
	status = "okay";
};

/* Colibri Fast Ethernet */
&fec1 {
	status = "okay";
};

&gpio2 {
	/*
	 * uart_b_c_on_x14_enable turns the UART transceiver for UART2 and 5 on. If one wants to
	 * turn the transceiver off, that property has to be deleted and the gpio handled in
	 * userspace.
	 * The same applies to uart_a_on_x13_enable where the UART_A transceiver is turned on.
	 */
	uart-b-c-on-x14-enable-hog {
		gpio-hog;
		gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */
		output-high;
	};
};

&gpio5 {
	uart-a-on-x13-enable-hog {
		gpio-hog;
		gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */
		output-high;
	};
};

/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
&i2c4 {
	status = "okay";
};

/* Colibri PWM<A> */
&pwm1 {
	status = "okay";
};

/* Colibri PWM<B> */
&pwm2 {
	status = "okay";
};

/* Colibri PWM<C> */
&pwm3 {
	status = "okay";
};

/* Colibri PWM<D> */
&pwm4 {
	status = "okay";
};

/* M41T0M6 real time clock */
&rtc {
	status = "okay";
};

/* Colibri UART_A */
&uart1 {
	status = "okay";
};

/* Colibri UART_B */
&uart2 {
	status = "okay";
};

/* Colibri UART_C */
&uart3 {
	status = "okay";
};

/* Colibri USBC */
&usbotg1 {
	status = "okay";
};

/* Colibri MMC/SD, UHS-I capable uSD slot */
&usdhc1 {
	cap-power-off-card;
	/delete-property/ keep-power-in-suspend;
	/delete-property/ no-1-8-v;
	vmmc-supply = <&reg_3v3_vmmc>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

/* Colibri AD0 to AD3 */
&adc1 {
	status = "okay";
};

/*
 * The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
 * So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
 */
&atmel_mxt_ts {
	interrupt-parent = <&gpio1>;
	interrupts = <9 IRQ_TYPE_EDGE_FALLING>;		/* SODIMM 28 / INT */
	pinctrl-0 = <&pinctrl_atmel_adapter>;
	reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;	/* SODIMM 30 / RST */
};

/* Colibri SSP */
&ecspi3 {
	status = "okay";
};

/* Colibri Fast Ethernet */
&fec1 {
	status = "okay";
};

&gpio2 {
	/*
	 * uart25 turns the UART transceiver for UART2 and 5 on. If one wants to turn the
	 * transceiver off, that property has to be deleted and the gpio handled in userspace.
	 * The same applies to uart1_tx_on where the UART1 transceiver is turned on.
	 */
	uart25-tx-on-hog {
		gpio-hog;
		gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */
		output-high;
	};
};

&gpio5 {
	uart1-tx-on-hog {
		gpio-hog;
		gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */
		output-high;
	};
};

/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
&i2c4 {
	status = "okay";
};

/* Colibri PWM<A> */
&pwm1 {
	status = "okay";
};

/* Colibri PWM<B> */
&pwm2 {
	/* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
	status = "okay";
};

/* Colibri PWM<C> */
&pwm3 {
	/* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
	status = "okay";
};

/* Colibri PWM<D> */
&pwm4 {
	status = "okay";
};

/* M41T0M6 real time clock */
&rtc {
	status = "okay";
};

/* Colibri UART_A */
&uart1 {
	status = "okay";
};

/* Colibri UART_B */
&uart2 {
	status = "okay";
};

/* Colibri UART_C */
&uart3 {
	status = "okay";
};

/* Colibri USBC */
&usbotg1 {
	status = "okay";
};

/* Colibri MMC/SD */
&usdhc1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2016-2022 Toradex
 */

#include <dt-bindings/pwm/pwm.h>

/ {
	aliases {
		rtc0 = &rtc;
		rtc1 = &snvs_rtc;
	};

	backlight: backlight {
		brightness-levels = <0 45 63 88 119 158 203 255>;
		compatible = "pwm-backlight";
		default-brightness-level = <4>;
		enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_bl_on>;
		power-supply = <&reg_module_3v3>;
		pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
		status = "disabled";
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	extcon_usbc_det: usbc-det {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbc_det>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpiokeys>;

		wakeup {
			debounce-interval = <10>;
			gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */
			label = "Wake-Up";
			linux,code = <KEY_WAKEUP>;
			wakeup-source;
		};
	};

	panel_dpi: panel-dpi {
		backlight = <&backlight>;
		compatible = "edt,et057090dhu";
		power-supply = <&reg_3v3>;
		status = "disabled";

		port {
			lcd_panel_in: endpoint {
				remote-endpoint = <&lcdif_out>;
			};
		};
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "3.3V";
	};

	reg_5v0: regulator-5v0 {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "5V";
	};

	reg_module_3v3: regulator-module-3v3 {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "+V3.3";
	};

	reg_module_3v3_avdd: regulator-module-3v3-avdd {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "+V3.3_AVDD_AUDIO";
	};

	reg_module_3v3_eth: regulator-module-3v3-eth {
		compatible = "regulator-fixed";
		off-on-delay-us = <200000>;
		regulator-name = "+V3.3_ETH";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		startup-delay-us = <200000>;
		vin-supply = <&reg_LDO1>;
	};

	reg_usbh_vbus: regulator-usbh-vbus {
		compatible = "regulator-fixed";
		gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbh_reg>;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "VCC_USB[1-4]";
		vin-supply = <&reg_5v0>;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,format = "i2s";
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,name = "imx7-sgtl5000";

		simple-audio-card,cpu {
			sound-dai = <&sai1>;
		};

		dailink_master: simple-audio-card,codec {
			clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
			sound-dai = <&codec>;
		};
	};
};

/* Colibri AD0 to AD3 */
&adc1 {
	vref-supply = <&reg_DCDC3>;
};

/* ADC2 is not available as it conflicts with AD7879 resistive touchscreen. */

&cpu0 {
	cpu-supply = <&reg_DCDC2>;
};

/* Colibri SSP */
&ecspi3 {
	cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; /* SODIMM 86 / SSPFRM */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
};

/* Colibri Fast Ethernet */
&fec1 {
	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	assigned-clock-rates = <0>, <100000000>;
	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
	clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
		 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
		 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
		 <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
	fsl,magic-packet;
	phy-handle = <&ethphy0>;
	phy-mode = "rmii";
	phy-supply = <&reg_module_3v3_eth>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_enet1>;
	pinctrl-1 = <&pinctrl_enet1_sleep>;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		/* Micrel KSZ8041RNL */
		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			max-speed = <100>;
			micrel,led-mode = <0>;
			reg = <0>;
		};
	};
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
};

&gpio1 {
	gpio-line-names = "SODIMM_43",
			  "SODIMM_45",
			  "SODIMM_135",
			  "SODIMM_22",
			  "",
			  "",
			  "SODIMM_37",
			  "SODIMM_29",
			  "SODIMM_59",
			  "SODIMM_28",
			  "SODIMM_30",
			  "SODIMM_67",
			  "",
			  "",
			  "SODIMM_188",
			  "SODIMM_178";
};

&gpio2 {
	gpio-line-names = "SODIMM_111",
			  "SODIMM_113",
			  "SODIMM_115",
			  "SODIMM_117",
			  "SODIMM_119",
			  "SODIMM_121",
			  "SODIMM_123",
			  "SODIMM_125",
			  "SODIMM_91",
			  "SODIMM_89",
			  "SODIMM_105",
			  "SODIMM_152",
			  "SODIMM_150",
			  "SODIMM_95",
			  "SODIMM_126",
			  "SODIMM_107",
			  "SODIMM_114",
			  "SODIMM_116",
			  "SODIMM_118",
			  "SODIMM_120",
			  "SODIMM_122",
			  "SODIMM_124",
			  "SODIMM_127",
			  "SODIMM_130",
			  "SODIMM_132",
			  "SODIMM_134",
			  "SODIMM_133",
			  "SODIMM_104",
			  "SODIMM_106",
			  "SODIMM_110",
			  "SODIMM_112",
			  "SODIMM_128";
};

&gpio3 {
	gpio-line-names = "SODIMM_56",
			  "SODIMM_44",
			  "SODIMM_68",
			  "SODIMM_82",
			  "SODIMM_93",
			  "SODIMM_76",
			  "SODIMM_70",
			  "SODIMM_60",
			  "SODIMM_58",
			  "SODIMM_78",
			  "SODIMM_72",
			  "SODIMM_80",
			  "SODIMM_46",
			  "SODIMM_62",
			  "SODIMM_48",
			  "SODIMM_74",
			  "SODIMM_50",
			  "SODIMM_52",
			  "SODIMM_54",
			  "SODIMM_66",
			  "SODIMM_64",
			  "SODIMM_57",
			  "SODIMM_61",
			  "SODIMM_136",
			  "SODIMM_138",
			  "SODIMM_140",
			  "SODIMM_142",
			  "SODIMM_144",
			  "SODIMM_146";
};

&gpio4 {
	gpio-line-names = "SODIMM_35",
			  "SODIMM_33",
			  "SODIMM_38",
			  "SODIMM_36",
			  "SODIMM_21",
			  "SODIMM_19",
			  "SODIMM_131",
			  "SODIMM_129",
			  "SODIMM_90",
			  "SODIMM_92",
			  "SODIMM_88",
			  "SODIMM_86",
			  "SODIMM_81",
			  "SODIMM_94",
			  "SODIMM_96",
			  "SODIMM_75",
			  "SODIMM_101",
			  "SODIMM_103",
			  "SODIMM_79",
			  "SODIMM_97",
			  "SODIMM_67",
			  "SODIMM_59",
			  "SODIMM_85",
			  "SODIMM_65";
};

&gpio5 {
	gpio-line-names = "SODIMM_69",
			  "SODIMM_71",
			  "SODIMM_73",
			  "SODIMM_47",
			  "SODIMM_190",
			  "SODIMM_192",
			  "SODIMM_49",
			  "SODIMM_51",
			  "SODIMM_53",
			  "",
			  "",
			  "SODIMM_98",
			  "SODIMM_184",
			  "SODIMM_186",
			  "SODIMM_23",
			  "SODIMM_31",
			  "SODIMM_100",
			  "SODIMM_102";
};

&gpio6 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_169",
			  "",
			  "",
			  "",
			  "SODIMM_77",
			  "SODIMM_24",
			  "",
			  "SODIMM_25",
			  "SODIMM_27",
			  "SODIMM_32",
			  "SODIMM_34";
};

&gpio7 {
	gpio-line-names = "",
			  "",
			  "SODIMM_63",
			  "SODIMM_55",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_196",
			  "SODIMM_194",
			  "",
			  "SODIMM_99",
			  "",
			  "",
			  "SODIMM_137";
};

/* NAND on such SKUs */
&gpmi {
	fsl,use-minimum-ecc;
	nand-ecc-mode = "hw";
	nand-on-flash-bbt;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
};

/* On-module Power I2C */
&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
	pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
	scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	codec: sgtl5000@a {
		#sound-dai-cells = <0>;
		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
		compatible = "fsl,sgtl5000";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_sai1_mclk>;
		reg = <0xa>;
		VDDA-supply = <&reg_module_3v3_avdd>;
		VDDD-supply = <&reg_DCDC3>;
		VDDIO-supply = <&reg_module_3v3>;
	};

	ad7879_ts: touchscreen@2c {
		adi,acquisition-time = /bits/ 8 <1>;
		adi,averaging = /bits/ 8 <1>;
		adi,conversion-interval = /bits/ 8 <255>;
		adi,first-conversion-delay = /bits/ 8 <3>;
		adi,median-filter-size = /bits/ 8 <2>;
		adi,resistance-plate-x = <120>;
		compatible = "adi,ad7879-1";
		interrupt-parent = <&gpio1>;
		interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
		reg = <0x2c>;
		touchscreen-max-pressure = <4096>;
		status = "disabled";
	};

	pmic@33 {
		compatible = "ricoh,rn5t567";
		reg = <0x33>;

		regulators {
			reg_DCDC1: DCDC1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1100000>;
				regulator-min-microvolt = <1000000>;
				regulator-name = "+V1.0_SOC";
			};

			reg_DCDC2: DCDC2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1100000>;
				regulator-min-microvolt = <975000>;
				regulator-name = "+V1.1_ARM";
			};

			reg_DCDC3: DCDC3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1800000>;
				regulator-min-microvolt = <1800000>;
				regulator-name = "+V1.8";
			};

			reg_DCDC4: DCDC4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1350000>;
				regulator-min-microvolt = <1350000>;
				regulator-name = "+V1.35_DRAM";
			};

			reg_LDO1: LDO1 {
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <3300000>;
				regulator-name = "PWR_EN_+V3.3_ETH";
			};

			reg_LDO2: LDO2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <1800000>;
				regulator-name = "+V1.8_SD";
			};

			reg_LDO3: LDO3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <3300000>;
				regulator-name = "PWR_EN_+V3.3_LPSR";
			};

			reg_LDO4: LDO4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1800000>;
				regulator-min-microvolt = <1800000>;
				regulator-name = "+V1.8_LPSR";
			};

			reg_LDO5: LDO5 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <3300000>;
				regulator-name = "PWR_EN_+V3.3";
			};
		};
	};
};

/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_recovery>;
	scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "disabled";

	/* Atmel maxtouch controller */
	atmel_mxt_ts: touchscreen@4a {
		compatible = "atmel,maxtouch";
		interrupt-parent = <&gpio2>;
		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;        /* SODIMM 107 / INT */
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_atmel_connector>;
		reg = <0x4a>;
		reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;      /* SODIMM 106 / RST */
		status = "disabled";
	};

	/* M41T0M6 real time clock on carrier board */
	rtc: rtc@68 {
		compatible = "st,m41t0";
		reg = <0x68>;
		status = "disabled";
	};
};

&lcdif {
	assigned-clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_PLL_VIDEO_POST_DIV>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat
		     &pinctrl_lcdif_ctrl>;
	status = "disabled";

	port {
		lcdif_out: endpoint {
			remote-endpoint = <&lcd_panel_in>;
		};
	};
};

/* Colibri PWM<A> */
&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
};

/* Colibri PWM<B> */
&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
};

/* Colibri PWM<C> */
&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
};

/* Colibri PWM<D> */
&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
};

&reg_1p0d {
	vin-supply = <&reg_DCDC3>; /* VDDA_1P8_IN */
};

&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "okay";
};

/* Colibri UART_A */
&uart1 {
	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
	fsl,dte-mode;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
	uart-has-rtscts;
};

/* Colibri UART_B */
&uart2 {
	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
	fsl,dte-mode;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	uart-has-rtscts;
};

/* Colibri UART_C */
&uart3 {
	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
	fsl,dte-mode;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
};

/* Colibri USBC */
&usbotg1 {
	dr_mode = "otg";
	extcon = <0>, <&extcon_usbc_det>;
};

/* Colibri MMC/SD */
&usdhc1 {
	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
	disable-wp;
	no-1-8-v;
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>;
	pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>;
	vmmc-supply = <&reg_3v3>;
	vqmmc-supply = <&reg_LDO2>;
	wakeup-source;
};

/* eMMC on 1GB (eMMC) SKUs */
&usdhc3 {
	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
	assigned-clock-rates = <400000000>;
	bus-width = <8>;
	fsl,tuning-step = <2>;
	non-removable;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	sdhci-caps-mask = <0x80000000 0x0>;
	vmmc-supply = <&reg_module_3v3>;
	vqmmc-supply = <&reg_DCDC3>;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;

	/*
	 * Atmel MXT touchsceen + Capacitive Touch Adapter
	 * NOTE: This pin group conflicts with pin groups pinctrl_pwm2/pinctrl_pwm3.
	 * Don't use them simultaneously.
	 */
	pinctrl_atmel_adapter: atmeladaptergrp {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO09__GPIO1_IO9		0x74 /* SODIMM 28 / INT */
			MX7D_PAD_GPIO1_IO10__GPIO1_IO10		0x14 /* SODIMM 30 / RST */
		>;
	};

	/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
	pinctrl_atmel_connector: atmelconnectorgrp {
		fsl,pins = <
			MX7D_PAD_EPDC_BDR0__GPIO2_IO28		0x14 /* SODIMM 106 / RST */
			MX7D_PAD_EPDC_DATA15__GPIO2_IO15	0x74 /* SODIMM 107 / INT */
		>;
	};

	pinctrl_can_int: canintgrp {
		fsl,pins = <
			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0X14 /* SODIMM 73 */
		>;
	};

	pinctrl_ecspi3: ecspi3grp {
		fsl,pins = <
			MX7D_PAD_I2C1_SCL__ECSPI3_MISO		0x2 /* SODIMM 90 */
			MX7D_PAD_I2C1_SDA__ECSPI3_MOSI		0x2 /* SODIMM 92 */
			MX7D_PAD_I2C2_SCL__ECSPI3_SCLK		0x2 /* SODIMM 88 */
		>;
	};

	pinctrl_ecspi3_cs: ecspi3csgrp {
		fsl,pins = <
			MX7D_PAD_I2C2_SDA__GPIO4_IO11		0x14 /* SODIMM 86 */
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x73
			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x73
			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER		0x73
			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x73
			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x73
			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x73
			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x73
			MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1		0x73
			MX7D_PAD_SD2_CD_B__ENET1_MDIO			0x3
			MX7D_PAD_SD2_WP__ENET1_MDC			0x3
		>;
	};

	pinctrl_enet1_sleep: enet1-sleepgrp {
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0		0x0
			MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1		0x0
			MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5		0x0
			MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4		0x0
			MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6		0x0
			MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7		0x0
			MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10		0x0
			MX7D_PAD_GPIO1_IO12__GPIO1_IO12			0x0
			MX7D_PAD_SD2_CD_B__GPIO5_IO9			0x0
			MX7D_PAD_SD2_WP__GPIO5_IO10			0x0
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX	0x79 /* SODIMM 63 */
			MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX	0x79 /* SODIMM 55 */
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x79 /* SODIMM 188 */
			MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x79 /* SODIMM 178 */
		>;
	};

	pinctrl_gpio1: gpio1grp {
		fsl,pins = <
			MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x14 /* SODIMM 110 */
			MX7D_PAD_EPDC_DATA00__GPIO2_IO0		0x14 /* SODIMM 111 */
			MX7D_PAD_EPDC_DATA01__GPIO2_IO1		0x14 /* SODIMM 113 */
			MX7D_PAD_EPDC_DATA02__GPIO2_IO2		0x14 /* SODIMM 115 */
			MX7D_PAD_EPDC_DATA03__GPIO2_IO3		0x14 /* SODIMM 117 */
			MX7D_PAD_EPDC_DATA04__GPIO2_IO4		0x14 /* SODIMM 119 */
			MX7D_PAD_EPDC_DATA05__GPIO2_IO5		0x14 /* SODIMM 121 */
			MX7D_PAD_EPDC_DATA06__GPIO2_IO6		0x14 /* SODIMM 123 */
			MX7D_PAD_EPDC_DATA07__GPIO2_IO7		0x14 /* SODIMM 125 */
			MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x74 /* SODIMM 91 */
			MX7D_PAD_EPDC_DATA09__GPIO2_IO9		0x14 /* SODIMM 89 */
			MX7D_PAD_EPDC_DATA10__GPIO2_IO10	0x74 /* SODIMM 105 */
			MX7D_PAD_EPDC_DATA11__GPIO2_IO11	0x14 /* SODIMM 152 */
			MX7D_PAD_EPDC_DATA12__GPIO2_IO12	0x14 /* SODIMM 150 */
			MX7D_PAD_EPDC_DATA14__GPIO2_IO14	0x14 /* SODIMM 126 */
			MX7D_PAD_EPDC_GDCLK__GPIO2_IO24		0x14 /* SODIMM 132 */
			MX7D_PAD_EPDC_GDOE__GPIO2_IO25		0x14 /* SODIMM 134 */
			MX7D_PAD_EPDC_GDRL__GPIO2_IO26		0x14 /* SODIMM 133 */
			MX7D_PAD_EPDC_GDSP__GPIO2_IO27		0x14 /* SODIMM 104 */
			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x14 /* SODIMM 112 */
			MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x14 /* SODIMM 128 */
			MX7D_PAD_EPDC_SDCE0__GPIO2_IO20		0x14 /* SODIMM 122 */
			MX7D_PAD_EPDC_SDCE1__GPIO2_IO21		0x14 /* SODIMM 124 */
			MX7D_PAD_EPDC_SDCE2__GPIO2_IO22		0x14 /* SODIMM 127 */
			MX7D_PAD_EPDC_SDCE3__GPIO2_IO23		0x14 /* SODIMM 130 */
			MX7D_PAD_EPDC_SDCLK__GPIO2_IO16		0x14 /* SODIMM 114 */
			MX7D_PAD_EPDC_SDLE__GPIO2_IO17		0x14 /* SODIMM 116 */
			MX7D_PAD_EPDC_SDOE__GPIO2_IO18		0x14 /* SODIMM 118 */
			MX7D_PAD_EPDC_SDSHR__GPIO2_IO19		0x14 /* SODIMM 120 */
			MX7D_PAD_LCD_RESET__GPIO3_IO4		0x14 /* SODIMM 93 */
			MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17	0x14 /* SODIMM 24 */
			MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12	0x14 /* SODIMM 169 */
			MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16	0x14 /* SODIMM 77 */
			MX7D_PAD_SD2_CLK__GPIO5_IO12		0x14 /* SODIMM 184 */
			MX7D_PAD_SD2_CMD__GPIO5_IO13		0x14 /* SODIMM 186 */
			MX7D_PAD_SD2_DATA2__GPIO5_IO16		0x14 /* SODIMM 100 */
			MX7D_PAD_SD2_DATA3__GPIO5_IO17		0x14 /* SODIMM 102 */
			MX7D_PAD_UART3_RTS_B__GPIO4_IO6		0x14 /* SODIMM 131 */
		>;
	};

	pinctrl_gpio2: gpio2grp { /* On X22 Camera interface */
		fsl,pins = <
			MX7D_PAD_ECSPI1_MISO__GPIO4_IO18	0x14 /* SODIMM 79 */
			MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17	0x14 /* SODIMM 103 */
			MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16	0x14 /* SODIMM 101 */
			MX7D_PAD_ECSPI1_SS0__GPIO4_IO19		0x14 /* SODIMM 97 */
			MX7D_PAD_ECSPI2_MISO__GPIO4_IO22	0x14 /* SODIMM 85 */
			MX7D_PAD_ECSPI2_SS0__GPIO4_IO23		0x14 /* SODIMM 65 */
			MX7D_PAD_I2C3_SCL__GPIO4_IO12		0x14 /* SODIMM 81 */
			MX7D_PAD_I2C3_SDA__GPIO4_IO13		0x14 /* SODIMM 94 */
			MX7D_PAD_I2C4_SCL__GPIO4_IO14		0x14 /* SODIMM 96 */
			MX7D_PAD_I2C4_SDA__GPIO4_IO15		0x14 /* SODIMM 75 */
			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x74 /* SODIMM 69 */
			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x14 /* SODIMM 98 */
		>;
	};

	pinctrl_gpio3: gpio3grp { /* LCD 18-23 */
		fsl,pins = <
			MX7D_PAD_LCD_DATA18__GPIO3_IO23		0x14 /* SODIMM 136 */
			MX7D_PAD_LCD_DATA19__GPIO3_IO24		0x14 /* SODIMM 138 */
			MX7D_PAD_LCD_DATA20__GPIO3_IO25		0x14 /* SODIMM 140 */
			MX7D_PAD_LCD_DATA21__GPIO3_IO26		0x14 /* SODIMM 142 */
			MX7D_PAD_LCD_DATA22__GPIO3_IO27		0x74 /* SODIMM 144 */
			MX7D_PAD_LCD_DATA23__GPIO3_IO28		0x74 /* SODIMM 146 */
		>;
	};

	pinctrl_gpio4: gpio4grp { /* Alternatively CAN2 */
		fsl,pins = <
			MX7D_PAD_GPIO1_IO14__GPIO1_IO14		0x14 /* SODIMM 188 */
			MX7D_PAD_GPIO1_IO15__GPIO1_IO15		0x14 /* SODIMM 178 */
		>;
	};

	pinctrl_gpio7: gpio7grp { /* Alternatively CAN1 */
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2	0x14 /* SODIMM 63 */
			MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3	0x14 /* SODIMM 55 */
		>;
	};

	pinctrl_gpio_bl_on: gpioblongrp {
		fsl,pins = <
			MX7D_PAD_SD1_WP__GPIO5_IO1		0x14 /* SODIMM 71 */
		>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
		fsl,pins = <
			MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	0x71
			MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	0x74
			MX7D_PAD_SD3_CLK__NAND_CLE		0x71
			MX7D_PAD_SD3_CMD__NAND_ALE		0x71
			MX7D_PAD_SD3_DATA0__NAND_DATA00		0x71
			MX7D_PAD_SD3_DATA1__NAND_DATA01		0x71
			MX7D_PAD_SD3_DATA2__NAND_DATA02		0x71
			MX7D_PAD_SD3_DATA3__NAND_DATA03		0x71
			MX7D_PAD_SD3_DATA4__NAND_DATA04		0x71
			MX7D_PAD_SD3_DATA5__NAND_DATA05		0x71
			MX7D_PAD_SD3_DATA6__NAND_DATA06		0x71
			MX7D_PAD_SD3_DATA7__NAND_DATA07		0x71
			MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
			MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
		>;
	};

	pinctrl_i2c1_int: i2c1intgrp { /* PMIC / TOUCH */
		fsl,pins = <
			MX7D_PAD_GPIO1_IO13__GPIO1_IO13	0x79
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL	0x4000007f /* SODIMM 196 */
			MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA	0x4000007f /* SODIMM 194 */
		>;
	};

	pinctrl_i2c4_recovery: i2c4-recoverygrp {
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8	0x4000007f
			MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9	0x4000007f
		>;
	};

	pinctrl_lcdif_dat: lcdifdatgrp {
		fsl,pins = <
			MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79 /* SODIMM 76 */
			MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79 /* SODIMM 70 */
			MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79 /* SODIMM 60 */
			MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79 /* SODIMM 58 */
			MX7D_PAD_LCD_DATA04__LCD_DATA4		0x79 /* SODIMM 78 */
			MX7D_PAD_LCD_DATA05__LCD_DATA5		0x79 /* SODIMM 72 */
			MX7D_PAD_LCD_DATA06__LCD_DATA6		0x79 /* SODIMM 80 */
			MX7D_PAD_LCD_DATA07__LCD_DATA7		0x79 /* SODIMM 46 */
			MX7D_PAD_LCD_DATA08__LCD_DATA8		0x79 /* SODIMM 62 */
			MX7D_PAD_LCD_DATA09__LCD_DATA9		0x79 /* SODIMM 48 */
			MX7D_PAD_LCD_DATA10__LCD_DATA10		0x79 /* SODIMM 74 */
			MX7D_PAD_LCD_DATA11__LCD_DATA11		0x79 /* SODIMM 50 */
			MX7D_PAD_LCD_DATA12__LCD_DATA12		0x79 /* SODIMM 52 */
			MX7D_PAD_LCD_DATA13__LCD_DATA13		0x79 /* SODIMM 54 */
			MX7D_PAD_LCD_DATA14__LCD_DATA14		0x79 /* SODIMM 66 */
			MX7D_PAD_LCD_DATA15__LCD_DATA15		0x79 /* SODIMM 64 */
			MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79 /* SODIMM 57 */
			MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79 /* SODIMM 61 */
		>;
	};

	pinctrl_lcdif_dat_24: lcdifdat24grp {
		fsl,pins = <
			MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79 /* SODIMM 136 */
			MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79 /* SODIMM 138 */
			MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79 /* SODIMM 140 */
			MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79 /* SODIMM 142 */
			MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79 /* SODIMM 144 */
			MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79 /* SODIMM 146 */
		>;
	};

	pinctrl_lcdif_ctrl: lcdifctrlgrp {
		fsl,pins = <
			MX7D_PAD_LCD_CLK__LCD_CLK		0x79 /* SODIMM 56 */
			MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x79 /* SODIMM 44 */
			MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x79 /* SODIMM 68 */
			MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x79 /* SODIMM 82 */
		>;
	};

	pinctrl_lvds_transceiver: lvdstx {
		fsl,pins = <
			MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2     0x14 /* SODIMM 63 */
			MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3     0x74 /* SODIMM 55 */
			MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11    0x14 /* SODIMM 99 */
			MX7D_PAD_EPDC_DATA13__GPIO2_IO13        0x14 /* SODIMM 95 */
		>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21	0x4  /* SODIMM 59 */
			MX7D_PAD_GPIO1_IO08__PWM1_OUT		0x79 /* SODIMM 59 */
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO09__PWM2_OUT		0x79 /* SODIMM 28 */
		>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <
			MX7D_PAD_GPIO1_IO10__PWM3_OUT		0x79 /* SODIMM 30 */
		>;
	};

	pinctrl_pwm4: pwm4grp {
		fsl,pins = <
			MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20	0x4  /* SODIMM 67 */
			MX7D_PAD_GPIO1_IO11__PWM4_OUT		0x79 /* SODIMM 67 */
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS	0x79 /* SODIMM 25 */
			MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS	0x79 /* SODIMM 27 */
			MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX	0x79 /* SODIMM 35 */
			MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX	0x79 /* SODIMM 33 */
		>;
	};

	pinctrl_uart1_ctrl1: uart1ctrl1grp {
		fsl,pins = <
			MX7D_PAD_SD2_DATA0__GPIO5_IO14		0x14 /* SODIMM 23 / DTR */
			MX7D_PAD_SD2_DATA1__GPIO5_IO15		0x14 /* SODIMM 31 / DCD */
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS	0x79 /* SODIMM 32 / CTS */
			MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS	0x79 /* SODIMM 34 / RTS */
			MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX	0x79 /* SODIMM 38 */
			MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX	0x79 /* SODIMM 36 */
		>;
	};
	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX	0x79 /* SODIMM 21 */
			MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX	0x79 /* SODIMM 19 */
		>;
	};

	pinctrl_usbc_det: usbcdetgrp {
		fsl,pins = <
			MX7D_PAD_ENET1_CRS__GPIO7_IO14		0x14 /* SODIMM 137 / USBC_DET */
		>;
	};

	pinctrl_usbh_reg: usbhreggrp {
		fsl,pins = <
			MX7D_PAD_UART3_CTS_B__GPIO4_IO7		0x14 /* SODIMM 129 / USBH_PEN */
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX7D_PAD_SD1_CLK__SD1_CLK		0x19 /* SODIMM 47 */
			MX7D_PAD_SD1_CMD__SD1_CMD		0x59 /* SODIMM 190 */
			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59 /* SODIMM 192 */
			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59 /* SODIMM 49 */
			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59 /* SODIMM 51 */
			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59 /* SODIMM 53 */
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX7D_PAD_SD1_CLK__SD1_CLK		0x1a
			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX7D_PAD_SD1_CLK__SD1_CLK		0x1b
			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
		>;
	};

	/* Avoid backfeeding with removed card power. */
	pinctrl_usdhc1_sleep: usdhc1-slpgrp {
		fsl,pins = <
			MX7D_PAD_SD1_CMD__SD1_CMD		0x10
			MX7D_PAD_SD1_CLK__SD1_CLK		0x10
			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x10
			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x10
			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x10
			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x10
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
			MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
			MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
			MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
		>;
	};

	pinctrl_sai1: sai1grp {
		fsl,pins = <
			MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30
			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
			MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f
			MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x1f
		>;
	};

	pinctrl_sai1_mclk: sai1mclkgrp {
		fsl,pins = <
			MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
		>;
	};
};

&iomuxc_lpsr {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_lpsr>;

	pinctrl_cd_usdhc1: cdusdhc1grp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0	0x59 /* SODIMM 43 / MMC_CD */
		>;
	};

	pinctrl_cd_usdhc1_sleep: cdusdhc1-slpgrp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0	0x0
		>;
	};

	pinctrl_gpio_lpsr: gpiolpsrgrp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2	0x59 /* SODIMM 135 */
			MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3	0x59 /* SODIMM 22 */
		>;
	};

	pinctrl_gpiokeys: gpiokeysgrp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1	0x19 /* SODIMM 45 / WAKE_UP */
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL	0x4000007f
			MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA	0x4000007f
		>;
	};

	pinctrl_i2c1_recovery: i2c1-recoverygrp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4	0x4000007f
			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x4000007f
		>;
	};

	pinctrl_uart1_ctrl2: uart1ctrl2grp {
		fsl,pins = <
			MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6	0x14 /* SODIMM 37 / RI */
			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x14 /* SODIMM 29 / DSR */
		>;
	};
};