code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek AP Mixedsys Controller

maintainers:
  - Michael Turquette <mturquette@baylibre.com>
  - Stephen Boyd <sboyd@kernel.org>

description:
  The Mediatek apmixedsys controller provides PLLs to the system.
  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt6797-apmixedsys
          - mediatek,mt7622-apmixedsys
          - mediatek,mt7986-apmixedsys
          - mediatek,mt8135-apmixedsys
          - mediatek,mt8173-apmixedsys
          - mediatek,mt8516-apmixedsys
      - items:
          - const: mediatek,mt7623-apmixedsys
          - const: mediatek,mt2701-apmixedsys
          - const: syscon
      - items:
          - enum:
              - mediatek,mt2701-apmixedsys
              - mediatek,mt2712-apmixedsys
              - mediatek,mt6765-apmixedsys
              - mediatek,mt6779-apmixedsys
              - mediatek,mt6795-apmixedsys
              - mediatek,mt7629-apmixedsys
              - mediatek,mt8167-apmixedsys
              - mediatek,mt8183-apmixedsys
          - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    apmixedsys: clock-controller@10209000 {
        compatible = "mediatek,mt8173-apmixedsys";
        reg = <0x10209000 0x1000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Functional Clock Controller for MT6795

maintainers:
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  - Chun-Jie Chen <chun-jie.chen@mediatek.com>

description: |
  The clock architecture in MediaTek like below
  PLLs -->
          dividers -->
                      muxes
                           -->
                              clock gate

  The devices provide clock gate control in different IP blocks.

properties:
  compatible:
    enum:
      - mediatek,mt6795-mfgcfg
      - mediatek,mt6795-vdecsys
      - mediatek,mt6795-vencsys

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        mfgcfg: clock-controller@13000000 {
            compatible = "mediatek,mt6795-mfgcfg";
            reg = <0 0x13000000 0 0x1000>;
            #clock-cells = <1>;
        };

        vdecsys: clock-controller@16000000 {
            compatible = "mediatek,mt6795-vdecsys";
            reg = <0 0x16000000 0 0x1000>;
            #clock-cells = <1>;
        };

        vencsys: clock-controller@18000000 {
            compatible = "mediatek,mt6795-vencsys";
            reg = <0 0x18000000 0 0x1000>;
            #clock-cells = <1>;
        };
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek System Clock Controller for MT6795

maintainers:
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  - Chun-Jie Chen <chun-jie.chen@mediatek.com>

description:
  The Mediatek system clock controller provides various clocks and system
  configuration like reset and bus protection on MT6795.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt6795-apmixedsys
          - mediatek,mt6795-infracfg
          - mediatek,mt6795-pericfg
          - mediatek,mt6795-topckgen
      - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        topckgen: clock-controller@10000000 {
            compatible = "mediatek,mt6795-topckgen", "syscon";
            reg = <0 0x10000000 0 0x1000>;
            #clock-cells = <1>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MT7621 Clock

maintainers:
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

description: |
  The MT7621 has a PLL controller from where the cpu clock is provided
  as well as derived clocks for the bus and the peripherals. It also
  can gate SoC device clocks.

  Each clock is assigned an identifier and client nodes use this identifier
  to specify the clock which they consume.

  All these identifiers could be found in:
  [1]: <include/dt-bindings/clock/mt7621-clk.h>.

  The clocks are provided inside a system controller node.

  This node is also a reset provider for all the peripherals.

  Reset related bits are defined in:
  [2]: <include/dt-bindings/reset/mt7621-reset.h>.

properties:
  compatible:
    items:
      - const: mediatek,mt7621-sysc
      - const: syscon

  reg:
    maxItems: 1

  "#clock-cells":
    description:
      The first cell indicates the clock number, see [1] for available
      clocks.
    const: 1

  "#reset-cells":
    description:
      The first cell indicates the reset bit within the register, see
      [2] for available resets.
    const: 1

  ralink,memctl:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle of syscon used to control memory registers

  clock-output-names:
    maxItems: 8

required:
  - compatible
  - reg
  - '#clock-cells'
  - ralink,memctl

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt7621-clk.h>

    sysc: sysc@0 {
      compatible = "mediatek,mt7621-sysc", "syscon";
      reg = <0x0 0x100>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      ralink,memctl = <&memc>;
      clock-output-names = "xtal", "cpu", "bus",
                           "50m", "125m", "150m",
                           "250m", "270m";
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek frequency hopping and spread spectrum clocking control

maintainers:
  - Edward-JW Yang <edward-jw.yang@mediatek.com>

description: |
  Frequency hopping control (FHCTL) is a piece of hardware that control
  some PLLs to adopt "hopping" mechanism to adjust their frequency.
  Spread spectrum clocking (SSC) is another function provided by this hardware.

properties:
  compatible:
    const: mediatek,mt8186-fhctl

  reg:
    maxItems: 1

  clocks:
    description: Phandles of the PLL with FHCTL hardware capability.
    minItems: 1
    maxItems: 30

  mediatek,hopping-ssc-percent:
    description: The percentage of spread spectrum clocking for one PLL.
    minItems: 1
    maxItems: 30
    items:
      default: 0
      minimum: 0
      maximum: 8

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8186-clk.h>
    fhctl: fhctl@1000ce00 {
        compatible = "mediatek,mt8186-fhctl";
        reg = <0x1000ce00 0x200>;
        clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
        mediatek,hopping-ssc-percent = <3>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8365-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Functional Clock Controller for MT8365

maintainers:
  - Markus Schneider-Pargmann <msp@baylibre.com>

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8365-apu
          - mediatek,mt8365-imgsys
          - mediatek,mt8365-mfgcfg
          - mediatek,mt8365-vdecsys
          - mediatek,mt8365-vencsys
      - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    apu: clock-controller@19020000 {
        compatible = "mediatek,mt8365-apu", "syscon";
        reg = <0x19020000 0x1000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek System Clock Controller for MT8365

maintainers:
  - Markus Schneider-Pargmann <msp@baylibre.com>

description:
  The apmixedsys module provides most of PLLs which generated from SoC 26m.
  The topckgen provides dividers and muxes which provides the clock source to other IP blocks.
  The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8365-topckgen
          - mediatek,mt8365-infracfg
          - mediatek,mt8365-apmixedsys
          - mediatek,mt8365-pericfg
          - mediatek,mt8365-mcucfg
      - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    topckgen: clock-controller@10000000 {
        compatible = "mediatek,mt8365-topckgen", "syscon";
        reg = <0x10000000 0x1000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek Top Clock Generator Controller

maintainers:
  - Michael Turquette <mturquette@baylibre.com>
  - Stephen Boyd <sboyd@kernel.org>

description:
  The Mediatek topckgen controller provides various clocks to the system.
  The clock values can be found in <dt-bindings/clock/mt*-clk.h>.

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt6797-topckgen
          - mediatek,mt7622-topckgen
          - mediatek,mt8135-topckgen
          - mediatek,mt8173-topckgen
          - mediatek,mt8516-topckgen
      - items:
          - const: mediatek,mt7623-topckgen
          - const: mediatek,mt2701-topckgen
          - const: syscon
      - items:
          - enum:
              - mediatek,mt2701-topckgen
              - mediatek,mt2712-topckgen
              - mediatek,mt6765-topckgen
              - mediatek,mt6779-topckgen
              - mediatek,mt6795-topckgen
              - mediatek,mt7629-topckgen
              - mediatek,mt7986-topckgen
              - mediatek,mt8167-topckgen
              - mediatek,mt8183-topckgen
          - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    topckgen: clock-controller@10000000 {
        compatible = "mediatek,mt8173-topckgen";
        reg = <0x10000000 0x1000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip LAN966X Generic Clock Controller

maintainers:
  - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>

description: |
  The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
  ddr_clk and sys_clk. This clock controller generates and supplies
  clock to various peripherals within the SoC.

properties:
  compatible:
    const: microchip,lan966x-gck

  reg:
    minItems: 1
    items:
      - description: Generic clock registers
      - description: Optional gate clock registers

  clocks:
    items:
      - description: CPU clock source
      - description: DDR clock source
      - description: System clock source

  clock-names:
    items:
      - const: cpu
      - const: ddr
      - const: sys

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clks: clock-controller@e00c00a8 {
        compatible = "microchip,lan966x-gck";
        #clock-cells = <1>;
        clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
        clock-names = "cpu", "ddr", "sys";
        reg = <0xe00c00a8 0x38>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry

maintainers:
  - Conor Dooley <conor.dooley@microchip.com>

description: |
  Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
  these blocks contains two PLLs and 2 DLLs & are located in the four corners of
  the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
  https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html

properties:
  compatible:
    const: microchip,mpfs-ccc

  reg:
    items:
      - description: PLL0's control registers
      - description: PLL1's control registers
      - description: DLL0's control registers
      - description: DLL1's control registers

  clocks:
    description:
      The CCC PLL's have two input clocks. It is required that even if the input
      clocks are identical that both are provided.
    minItems: 2
    items:
      - description: PLL0's refclk0
      - description: PLL0's refclk1
      - description: PLL1's refclk0
      - description: PLL1's refclk1
      - description: DLL0's refclk
      - description: DLL1's refclk

  clock-names:
    minItems: 2
    items:
      - const: pll0_ref0
      - const: pll0_ref1
      - const: pll1_ref0
      - const: pll1_ref1
      - const: dll0_ref
      - const: dll1_ref

  '#clock-cells':
    const: 1
    description: |
      The clock consumer should specify the desired clock by having the clock
      ID in its "clocks" phandle cell.
      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
      PolarFire clock IDs.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller@38100000 {
        compatible = "microchip,mpfs-ccc";
        reg = <0x38010000 0x1000>, <0x38020000 0x1000>,
              <0x39010000 0x1000>, <0x39020000 0x1000>;
        #clock-cells = <1>;
        clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
                  <&refclk_ccc>, <&refclk_ccc>;
        clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
                      "dll0_ref", "dll1_ref";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip PolarFire Clock Control Module Binding

maintainers:
  - Daire McNamara <daire.mcnamara@microchip.com>

description: |
  Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
  which gates and enables all peripheral clocks.

  This device tree binding describes 33 gate clocks.  Clocks are referenced by
  user nodes by the CLKCFG node phandle and the clock index in the group, from
  0 to 32.

properties:
  compatible:
    const: microchip,mpfs-clkcfg

  reg:
    items:
      - description: |
          clock config registers:
          These registers contain enable, reset & divider tables for the, cpu,
          axi, ahb and rtc/mtimer reference clocks as well as enable and reset
          for the peripheral clocks.
      - description: |
          mss pll dri registers:
          Block of registers responsible for dynamic reconfiguration of the mss
          pll

  clocks:
    maxItems: 1

  '#clock-cells':
    const: 1
    description: |
      The clock consumer should specify the desired clock by having the clock
      ID in its "clocks" phandle cell.
      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
      PolarFire clock IDs.

  resets:
    maxItems: 1

  '#reset-cells':
    description:
      The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
      CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
      peripheral via the clock ID in its "resets" phandle cell.
      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
      PolarFire clock IDs.
    const: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  # Clock Config node:
  - |
    #include <dt-bindings/clock/microchip,mpfs-clock.h>
    soc {
            #address-cells = <2>;
            #size-cells = <2>;
            clkcfg: clock-controller@20002000 {
                compatible = "microchip,mpfs-clkcfg";
                reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
                clocks = <&ref>;
                #clock-cells = <1>;
        };
    };


code:
Microchip PIC32 Clock Controller Binding
----------------------------------------
Microchip clock controller is consists of few oscillators, PLL, multiplexer
and few divider modules.

This binding uses common clock bindings.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible: shall be "microchip,pic32mzda-clk".
- reg: shall contain base address and length of clock registers.
- #clock-cells: shall be 1.

Optional properties:
- microchip,pic32mzda-sosc: shall be added only if platform has
  secondary oscillator connected.

Example:
	rootclk: clock-controller@1f801200 {
		compatible = "microchip,pic32mzda-clk";
		reg = <0x1f801200 0x200>;
		#clock-cells = <1>;
		/* optional */
		microchip,pic32mzda-sosc;
	};

The clock consumer shall specify the desired clock-output of the clock
controller (as defined in [2]) by specifying output-id in its "clock"
phandle cell.
[2] include/dt-bindings/clock/microchip,pic32-clock.h

For example for UART2:
uart2: serial@2 {
	compatible = "microchip,pic32mzda-uart";
	reg = <>;
	interrupts = <>;
	clocks = <&rootclk PB2CLK>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip Sparx5 DPLL Clock

maintainers:
  - Lars Povlsen <lars.povlsen@microchip.com>

description: |
  The Sparx5 DPLL clock controller generates and supplies clock to
  various peripherals within the SoC.

properties:
  compatible:
    const: microchip,sparx5-dpll

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  # Clock provider for eMMC:
  - |
    lcpll_clk: lcpll-clk {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <2500000000>;
    };
    clks: clock-controller@61110000c {
        compatible = "microchip,sparx5-dpll";
        #clock-cells = <1>;
        clocks = <&lcpll_clk>;
        reg = <0x1110000c 0x24>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/milbeaut-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Milbeaut SoCs Clock Controller Binding

maintainers:
  - Taichi Sugaya <sugaya.taichi@socionext.com>

description: |
  Milbeaut SoCs Clock controller is an integrated clock controller, which
  generates and supplies to all modules.

  This binding uses common clock bindings
  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt

properties:
  compatible:
    enum:
      - socionext,milbeaut-m10v-ccu

  reg:
    maxItems: 1

  clocks:
    maxItems: 1
    description: external clock

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  # Clock controller node:
  - |
    m10v-clk-ctrl@1d021000 {
        compatible = "socionext,milbeaut-m10v-ccu";
        reg = <0x1d021000 0x4000>;
        #clock-cells = <1>;
        clocks = <&clki40mhz>;
    };

  # Required an external clock for Clock controller node:
  - |
    clocks {
        clki40mhz: clki40mhz {
            compatible = "fixed-clock";
            #clock-cells = <0>;
            clock-frequency = <40000000>;
        };
        /* other clocks */
    };

  # The clock consumer shall specify the desired clock-output of the clock
  # controller as below by specifying output-id in its "clk" phandle cell.
  # 2: uart
  # 4: 32-bit timer
  # 7: UHS-I/II
  - |
    serial@1e700010 {
        compatible = "socionext,milbeaut-usio-uart";
        reg = <0x1e700010 0x10>;
        interrupts = <0 141 0x4>, <0 149 0x4>;
        interrupt-names = "rx", "tx";
        clocks = <&clk 2>;
    };

...


code:
Device Tree Clock bindings for arch-moxart

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

MOXA ART SoCs allow to determine PLL output and APB frequencies
by reading registers holding multiplier and divisor information.

PLL:

Required properties:
- compatible : Must be "moxa,moxart-pll-clock"
- #clock-cells : Should be 0
- reg : Should contain registers location and length
- clocks : Should contain phandle + clock-specifier for the parent clock

Optional properties:
- clock-output-names : Should contain clock name

APB:

Required properties:
- compatible : Must be "moxa,moxart-apb-clock"
- #clock-cells : Should be 0
- reg : Should contain registers location and length
- clocks : Should contain phandle + clock-specifier for the parent clock

Optional properties:
- clock-output-names : Should contain clock name

For example:

	clk_pll: clk_pll@98100000 {
		compatible = "moxa,moxart-pll-clock";
		#clock-cells = <0>;
		reg = <0x98100000 0x34>;
	};

	clk_apb: clk_apb@98100000 {
		compatible = "moxa,moxart-apb-clock";
		#clock-cells = <0>;
		reg = <0x98100000 0x34>;
		clocks = <&clk_pll>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MStar/Sigmastar MSC313 CPU PLL

maintainers:
  - Daniel Palmer <daniel@thingy.jp>

description: |
  The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable
  PLL that can be used as the clock source for the CPU(s).

properties:
  compatible:
    const: mstar,msc313-cpupll

  "#clock-cells":
    const: 1

  clocks:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - "#clock-cells"
  - clocks
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mstar-msc313-mpll.h>
    cpupll: cpupll@206400 {
        compatible = "mstar,msc313-cpupll";
        reg = <0x206400 0x200>;
        #clock-cells = <1>;
        clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MStar/Sigmastar MSC313 MPLL

maintainers:
  - Daniel Palmer <daniel@thingy.jp>

description: |
  The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that
  takes the external xtal input and multiplies it to create a high
  frequency clock and divides that down into a number of clocks that
  peripherals use.

properties:
  compatible:
    const: mstar,msc313-mpll

  "#clock-cells":
    const: 1

  clocks:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - "#clock-cells"
  - clocks
  - reg

additionalProperties: false

examples:
  - |
    mpll@206000 {
        compatible = "mstar,msc313-mpll";
        reg = <0x206000 0x200>;
        #clock-cells = <1>;
        clocks = <&xtal>;
    };


code:
* Core Clock bindings for Marvell MVEBU SoCs

Marvell MVEBU SoCs usually allow to determine core clock frequencies by
reading the Sample-At-Reset (SAR) register. The core clock consumer should
specify the desired clock by having the clock ID in its "clocks" phandle cell.

The following is a list of provided IDs and clock names on Armada 370/XP:
 0 = tclk    (Internal Bus clock)
 1 = cpuclk  (CPU clock)
 2 = nbclk   (L2 Cache clock)
 3 = hclk    (DRAM control clock)
 4 = dramclk (DDR clock)

The following is a list of provided IDs and clock names on Armada 375:
 0 = tclk    (Internal Bus clock)
 1 = cpuclk  (CPU clock)
 2 = l2clk   (L2 Cache clock)
 3 = ddrclk  (DDR clock)

The following is a list of provided IDs and clock names on Armada 380/385:
 0 = tclk    (Internal Bus clock)
 1 = cpuclk  (CPU clock)
 2 = l2clk   (L2 Cache clock)
 3 = ddrclk  (DDR clock)

The following is a list of provided IDs and clock names on Armada 39x:
 0 = tclk    (Internal Bus clock)
 1 = cpuclk  (CPU clock)
 2 = nbclk   (Coherent Fabric clock)
 3 = hclk    (SDRAM Controller Internal Clock)
 4 = dclk    (SDRAM Interface Clock)
 5 = refclk  (Reference Clock)

The following is a list of provided IDs and clock names on 98dx3236:
 0 = tclk    (Internal Bus clock)
 1 = cpuclk  (CPU clock)
 2 = ddrclk   (DDR clock)
 3 = mpll    (MPLL Clock)

The following is a list of provided IDs and clock names on Kirkwood and Dove:
 0 = tclk   (Internal Bus clock)
 1 = cpuclk (CPU0 clock)
 2 = l2clk  (L2 Cache clock derived from CPU0 clock)
 3 = ddrclk (DDR controller clock derived from CPU0 clock)

The following is a list of provided IDs and clock names on Orion5x:
 0 = tclk   (Internal Bus clock)
 1 = cpuclk (CPU0 clock)
 2 = ddrclk (DDR controller clock derived from CPU0 clock)

Required properties:
- compatible : shall be one of the following:
	"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
	"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
	"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
	"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
	"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
	"marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
	"marvell,dove-core-clock" - for Dove SoC core clocks
	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
	"marvell,mv98dx1135-core-clock" - for Kirkwood 98dx1135 SoC
	"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
	"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
	"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
	"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
- reg : shall be the register address of the Sample-At-Reset (SAR) register
- #clock-cells : from common clock binding; shall be set to 1

Optional properties:
- clock-output-names : from common clock binding; allows overwrite default clock
	output names ("tclk", "cpuclk", "l2clk", "ddrclk")

Example:

core_clk: core-clocks@d0214 {
	compatible = "marvell,dove-core-clock";
	reg = <0xd0214 0x4>;
	#clock-cells = <1>;
};

spi0: spi@10600 {
	compatible = "marvell,orion-spi";
	/* ... */
	/* get tclk from core clock provider */
	clocks = <&core_clk 0>;
};


code:
* Core Divider Clock bindings for Marvell MVEBU SoCs

The following is a list of provided IDs and clock names on Armada 370/XP:
 0 = nand (NAND clock)

Required properties:
- compatible : must be "marvell,armada-370-corediv-clock",
		       "marvell,armada-375-corediv-clock",
		       "marvell,armada-380-corediv-clock",
                       "marvell,mv98dx3236-corediv-clock",

- reg : must be the register address of Core Divider control register
- #clock-cells : from common clock binding; shall be set to 1
- clocks : must be set to the parent's phandle

Example:

corediv_clk: corediv-clocks@18740 {
	compatible = "marvell,armada-370-corediv-clock";
	reg = <0x18740 0xc>;
	#clock-cells = <1>;
	clocks = <&pll>;
};


code:
Device Tree Clock bindings for cpu clock of Marvell EBU platforms

Required properties:
- compatible : shall be one of the following:
	"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
	"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
- reg : Address and length of the clock complex register set, followed
        by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.
- clocks : shall be the input parent clock phandle for the clock.

cpuclk: clock-complex@d0018700 {
	#clock-cells = <1>;
	compatible = "marvell,armada-xp-cpu-clock";
	reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
	clocks = <&coreclk 1>;
}

cpu@0 {
	compatible = "marvell,sheeva-v7";
	reg = <0>;
	clocks = <&cpuclk 0>;
};


code:
* Gated Clock bindings for Marvell EBU SoCs

Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some
peripheral clocks to be gated to save some power. The clock consumer
should specify the desired clock by having the clock ID in its
"clocks" phandle cell. The clock ID is directly mapped to the
corresponding clock gating control bit in HW to ease manual clock
lookup in datasheet.

The following is a list of provided IDs for Armada 370:
ID	Clock	Peripheral
-----------------------------------
0	Audio	AC97 Cntrl
1	pex0_en	PCIe 0 Clock out
2	pex1_en	PCIe 1 Clock out
3	ge1	Gigabit Ethernet 1
4	ge0	Gigabit Ethernet 0
5	pex0	PCIe Cntrl 0
9	pex1	PCIe Cntrl 1
15	sata0	SATA Host 0
17	sdio	SDHCI Host
23	crypto	CESA (crypto engine)
25	tdm	Time Division Mplx
28	ddr	DDR Cntrl
30	sata1	SATA Host 0

The following is a list of provided IDs for Armada 375:
ID	Clock		Peripheral
-----------------------------------
2	mu		Management Unit
3	pp		Packet Processor
4	ptp		PTP
5	pex0		PCIe 0 Clock out
6	pex1		PCIe 1 Clock out
8	audio		Audio Cntrl
11	nd_clk		Nand Flash Cntrl
14	sata0_link	SATA 0 Link
15	sata0_core	SATA 0 Core
16	usb3		USB3 Host
17	sdio		SDHCI Host
18	usb		USB Host
19	gop		Gigabit Ethernet MAC
20	sata1_link	SATA 1 Link
21	sata1_core	SATA 1 Core
22	xor0		XOR DMA 0
23	xor1		XOR DMA 0
24	copro		Coprocessor
25	tdm		Time Division Mplx
28	crypto0_enc	Cryptographic Unit Port 0 Encryption
29	crypto0_core	Cryptographic Unit Port 0 Core
30	crypto1_enc	Cryptographic Unit Port 1 Encryption
31	crypto1_core	Cryptographic Unit Port 1 Core

The following is a list of provided IDs for Armada 380/385:
ID	Clock		Peripheral
-----------------------------------
0	audio		Audio
2	ge2		Gigabit Ethernet 2
3	ge1		Gigabit Ethernet 1
4	ge0		Gigabit Ethernet 0
5	pex1		PCIe 1
6	pex2		PCIe 2
7	pex3		PCIe 3
8	pex0		PCIe 0
9	usb3h0		USB3 Host 0
10	usb3h1		USB3 Host 1
11	usb3d		USB3 Device
13	bm		Buffer Management
14	crypto0z	Cryptographic 0 Z
15	sata0		SATA 0
16	crypto1z	Cryptographic 1 Z
17	sdio		SDIO
18	usb2		USB 2
21	crypto1		Cryptographic 1
22	xor0		XOR 0
23	crypto0		Cryptographic 0
25	tdm		Time Division Multiplexing
28	xor1		XOR 1
30	sata1		SATA 1

The following is a list of provided IDs for Armada 39x:
ID	Clock		Peripheral
-----------------------------------
5	pex1		PCIe 1
6	pex2		PCIe 2
7	pex3		PCIe 3
8	pex0		PCIe 0
9	usb3h0		USB3 Host 0
10	usb3h1		USB3 Host 1
15	sata0		SATA 0
17	sdio		SDIO
22	xor0		XOR 0
28	xor1		XOR 1

The following is a list of provided IDs for Armada XP:
ID	Clock	Peripheral
-----------------------------------
0	audio	Audio Cntrl
1	ge3	Gigabit Ethernet 3
2	ge2	Gigabit Ethernet 2
3	ge1	Gigabit Ethernet 1
4	ge0	Gigabit Ethernet 0
5	pex0	PCIe Cntrl 0
6	pex1	PCIe Cntrl 1
7	pex2	PCIe Cntrl 2
8	pex3	PCIe Cntrl 3
13	bp
14	sata0lnk
15	sata0	SATA Host 0
16	lcd	LCD Cntrl
17	sdio	SDHCI Host
18	usb0	USB Host 0
19	usb1	USB Host 1
20	usb2	USB Host 2
22	xor0	XOR DMA 0
23	crypto	CESA engine
25	tdm	Time Division Mplx
28	xor1	XOR DMA 1
29	sata1lnk
30	sata1	SATA Host 1

The following is a list of provided IDs for 98dx3236:
ID	Clock	Peripheral
-----------------------------------
3	ge1	Gigabit Ethernet 1
4	ge0	Gigabit Ethernet 0
5	pex0	PCIe Cntrl 0
17	sdio	SDHCI Host
18	usb0	USB Host 0
22	xor0	XOR DMA 0

The following is a list of provided IDs for Dove:
ID	Clock	Peripheral
-----------------------------------
0	usb0	USB Host 0
1	usb1	USB Host 1
2	ge	Gigabit Ethernet
3	sata	SATA Host
4	pex0	PCIe Cntrl 0
5	pex1	PCIe Cntrl 1
8	sdio0	SDHCI Host 0
9	sdio1	SDHCI Host 1
10	nand	NAND Cntrl
11	camera	Camera Cntrl
12	i2s0	I2S Cntrl 0
13	i2s1	I2S Cntrl 1
15	crypto	CESA engine
21	ac97	AC97 Cntrl
22	pdma	Peripheral DMA
23	xor0	XOR DMA 0
24	xor1	XOR DMA 1
30	gephy	Gigabit Ethernel PHY
Note: gephy(30) is implemented as a parent clock of ge(2)

The following is a list of provided IDs for Kirkwood:
ID	Clock	Peripheral
-----------------------------------
0	ge0	Gigabit Ethernet 0
2	pex0	PCIe Cntrl 0
3	usb0	USB Host 0
4	sdio	SDIO Cntrl
5	tsu	Transp. Stream Unit
6	dunit	SDRAM Cntrl
7	runit	Runit
8	xor0	XOR DMA 0
9	audio	I2S Cntrl 0
14	sata0	SATA Host 0
15	sata1	SATA Host 1
16	xor1	XOR DMA 1
17	crypto	CESA engine
18	pex1	PCIe Cntrl 1
19	ge1	Gigabit Ethernet 1
20	tdm	Time Division Mplx

Required properties:
- compatible : shall be one of the following:
	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
	"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
	"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
	"marvell,dove-gating-clock" - for Dove SoC clock gating
	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
- reg : shall be the register address of the Clock Gating Control register
- #clock-cells : from common clock binding; shall be set to 1

Optional properties:
- clocks : default parent clock phandle (e.g. tclk)

Example:

gate_clk: clock-gating-control@d0038 {
	compatible = "marvell,dove-gating-clock";
	reg = <0xd0038 0x4>;
	/* default parent clock is tclk */
	clocks = <&core_clk 0>;
	#clock-cells = <1>;
};

sdio0: sdio@92000 {
	compatible = "marvell,dove-sdhci";
	/* get clk gate bit 8 (sdio0) */
	clocks = <&gate_clk 8>;
};


code:
TI-NSPIRE Clocks

Required properties:
- compatible: Valid compatible properties include:
	"lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
	"lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
	"lsi,nspire-cx-clock" for the base clock in the CX model
	"lsi,nspire-classic-clock" for the base clock in the older model

- reg: Physical base address of the controller and length of memory mapped
	region.

Optional:
- clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
	clock where it divides the rate from.

Example:

ahb_clk {
	#clock-cells = <0>;
	compatible = "lsi,nspire-cx-clock";
	reg = <0x900B0000 0x4>;
	clocks = <&base_clk>;
};


code:
* Nuvoton NPCM7XX Clock Controller

Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
generates and supplies clocks to all modules within the BMC.

External clocks:

There are six fixed clocks that are generated outside the BMC. All clocks are of
a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
clk_sysbypck are inputs to the clock controller.
clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
network. They are set on the device tree, but not used by the clock module. The
network devices use them directly.
Example can be found below.

All available clocks are defined as preprocessor macros in:
dt-bindings/clock/nuvoton,npcm7xx-clock.h
and can be reused as DT sources.

Required Properties of clock controller:

	- compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
		  Poleg BMC NPCM750

	- reg: physical base address of the clock controller and length of
		memory mapped region.

	- #clock-cells: should be 1.

Example: Clock controller node:

	clk: clock-controller@f0801000 {
		compatible = "nuvoton,npcm750-clk";
		#clock-cells = <1>;
		reg = <0xf0801000 0x1000>;
		clock-names = "refclk", "sysbypck", "mcbypck";
		clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
	};

Example: Required external clocks for network:

	/* external reference clock */
	clk_refclk: clk-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
		clock-output-names = "refclk";
	};

	/* external reference clock for cpu. float in normal operation */
	clk_sysbypck: clk-sysbypck {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <800000000>;
		clock-output-names = "sysbypck";
	};

	/* external reference clock for MC. float in normal operation */
	clk_mcbypck: clk-mcbypck {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <800000000>;
		clock-output-names = "mcbypck";
	};

	 /* external clock signal rg1refck, supplied by the phy */
	clk_rg1refck: clk-rg1refck {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
		clock-output-names = "clk_rg1refck";
	};

	 /* external clock signal rg2refck, supplied by the phy */
	clk_rg2refck: clk-rg2refck {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
		clock-output-names = "clk_rg2refck";
	};

	clk_xin: clk-xin {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
		clock-output-names = "clk_xin";
	};

Example: GMAC controller node that consumes two clocks: a generated clk by the
clock controller and a fixed clock from DT (clk_rg1refck).

	ethernet0: ethernet@f0802000 {
		compatible = "snps,dwmac";
		reg = <0xf0802000 0x2000>;
		interrupts = <0 14 4>;
		interrupt-names = "macirq";
		clocks	= <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
		clock-names = "stmmaceth", "clk_gmac";
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Nuvoton NPCM8XX Clock Controller Binding

maintainers:
  - Tomer Maimon <tmaimon77@gmail.com>

description: |
  Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which
  generates and supplies clocks to all modules within the BMC.

properties:
  compatible:
    enum:
      - nuvoton,npcm845-clk

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1
    description:
      See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full
      list of NPCM8XX clock IDs.

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    ahb {
        #address-cells = <2>;
        #size-cells = <2>;

        clock-controller@f0801000 {
            compatible = "nuvoton,npcm845-clk";
            reg = <0x0 0xf0801000 0x0 0x1000>;
            #clock-cells = <1>;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Clock and Reset Controller

maintainers:
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  The Clock and Reset (CAR) is the HW module responsible for muxing and gating
  Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.

  CLKGEN provides the registers to program the PLLs. It controls most of
  the clock source programming and most of the clock dividers.

  CLKGEN input signals include the external clock for the reference frequency
  (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).

  Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.

  RSTGEN provides the registers needed to control resetting of each block in
  the Tegra system.

properties:
  compatible:
    const: nvidia,tegra124-car

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  "#reset-cells":
    const: 1

  nvidia,external-memory-controller:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle of the external memory controller node

patternProperties:
  "^emc-timings-[0-9]+$":
    type: object
    properties:
      nvidia,ram-code:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
          this timing set is used for

    patternProperties:
      "^timing-[0-9]+$":
        type: object
        properties:
          clock-frequency:
            description:
              external memory clock rate in Hz
            minimum: 1000000
            maximum: 1000000000

          nvidia,parent-clock-frequency:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              rate of parent clock in Hz
            minimum: 1000000
            maximum: 1000000000

          clocks:
            items:
              - description: parent clock of EMC

          clock-names:
            items:
              - const: emc-parent

        required:
          - clock-frequency
          - nvidia,parent-clock-frequency
          - clocks
          - clock-names

        additionalProperties: false

    additionalProperties: false

required:
  - compatible
  - reg
  - '#clock-cells'
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra124-car.h>

    car: clock-controller@60006000 {
        compatible = "nvidia,tegra124-car";
        reg = <0x60006000 0x1000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
    };


code:
NVIDIA Tegra124 DFLL FCPU clocksource

This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt

The DFLL IP block on Tegra is a root clocksource designed for clocking
the fast CPU cluster. It consists of a free-running voltage controlled
oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
control module that will automatically adjust the VDD_CPU voltage by
communicating with an off-chip PMIC either via an I2C bus or via PWM signals.

Required properties:
- compatible : should be one of:
  - "nvidia,tegra124-dfll": for Tegra124
  - "nvidia,tegra210-dfll": for Tegra210
- reg : Defines the following set of registers, in the order listed:
        - registers for the DFLL control logic.
        - registers for the I2C output logic.
        - registers for the integrated I2C master controller.
        - look-up table RAM for voltage register values.
- interrupts: Should contain the DFLL block interrupt.
- clocks: Must contain an entry for each entry in clock-names.
  See clock-bindings.txt for details.
- clock-names: Must include the following entries:
  - soc: Clock source for the DFLL control logic.
  - ref: The closed loop reference clock
  - i2c: Clock source for the integrated I2C master.
- resets: Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
  - dvco: Reset control for the DFLL DVCO.
- #clock-cells: Must be 0.
- clock-output-names: Name of the clock output.
- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
  hardware will start controlling. The regulator will be queried for
  the I2C register, control values and supported voltages.

Required properties for the control loop parameters:
- nvidia,sample-rate: Sample rate of the DFLL control loop.
- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.

Optional properties for the control loop parameters:
- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.

Optional properties for mode selection:
- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.

Required properties for I2C mode:
- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.

Required properties for PWM mode:
- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.
- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM
  control is disabled and the PWM output is tristated. Note that this voltage is
  configured in hardware, typically via a resistor divider.
- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control
  is enabled and PWM output is low. Hence, this is the minimum output voltage
  that the regulator supports when PWM control is enabled.
- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts
  corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th
  duty cycle would be: nvidia,pwm-min-microvolts +
  nvidia,pwm-voltage-step-microvolts * 2.
- pinctrl-0: I/O pad configuration when PWM control is enabled.
- pinctrl-1: I/O pad configuration when PWM control is disabled.
- pinctrl-names: must include the following entries:
  - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
  - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.

Example for I2C:

clock@70110000 {
        compatible = "nvidia,tegra124-dfll";
        reg = <0 0x70110000 0 0x100>, /* DFLL control */
              <0 0x70110000 0 0x100>, /* I2C output control */
              <0 0x70110100 0 0x100>, /* Integrated I2C controller */
              <0 0x70110200 0 0x100>; /* Look-up table RAM */
        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
                 <&tegra_car TEGRA124_CLK_DFLL_REF>,
                 <&tegra_car TEGRA124_CLK_I2C5>;
        clock-names = "soc", "ref", "i2c";
        resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
        reset-names = "dvco";
        #clock-cells = <0>;
        clock-output-names = "dfllCPU_out";
        vdd-cpu-supply = <&vdd_cpu>;

        nvidia,sample-rate = <12500>;
        nvidia,droop-ctrl = <0x00000f00>;
        nvidia,force-mode = <1>;
        nvidia,cf = <10>;
        nvidia,ci = <0>;
        nvidia,cg = <2>;

        nvidia,i2c-fs-rate = <400000>;
};

Example for PWM:

clock@70110000 {
	compatible = "nvidia,tegra124-dfll";
	reg = <0 0x70110000 0 0x100>, /* DFLL control */
	      <0 0x70110000 0 0x100>, /* I2C output control */
	      <0 0x70110100 0 0x100>, /* Integrated I2C controller */
	      <0 0x70110200 0 0x100>; /* Look-up table RAM */
	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
	         <&tegra_car TEGRA210_CLK_DFLL_REF>,
		 <&tegra_car TEGRA124_CLK_I2C5>;;
	clock-names = "soc", "ref", "i2c";
	resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
	reset-names = "dvco";
	#clock-cells = <0>;
	clock-output-names = "dfllCPU_out";

	nvidia,sample-rate = <25000>;
	nvidia,droop-ctrl = <0x00000f00>;
	nvidia,force-mode = <1>;
	nvidia,cf = <6>;
	nvidia,ci = <0>;
	nvidia,cg = <2>;

	nvidia,pwm-min-microvolts = <708000>; /* 708mV */
	nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
	nvidia,pwm-to-pmic;
	nvidia,pwm-tristate-microvolts = <1000000>;
	nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */

	pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
	pinctrl-0 = <&dvfs_pwm_active_state>;
	pinctrl-1 = <&dvfs_pwm_inactive_state>;
};

/* pinmux nodes added for completeness. Binding doc can be found in:
 * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
 */

pinmux: pinmux@700008d4 {
	dvfs_pwm_active_state: dvfs_pwm_active {
		dvfs_pwm_pbb1 {
			nvidia,pins = "dvfs_pwm_pbb1";
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
		};
	};
	dvfs_pwm_inactive_state: dvfs_pwm_inactive {
		dvfs_pwm_pbb1 {
			nvidia,pins = "dvfs_pwm_pbb1";
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
		};
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Clock and Reset Controller

maintainers:
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  The Clock and Reset (CAR) is the HW module responsible for muxing and gating
  Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.

  CLKGEN provides the registers to program the PLLs. It controls most of
  the clock source programming and most of the clock dividers.

  CLKGEN input signals include the external clock for the reference frequency
  (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).

  Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.

  RSTGEN provides the registers needed to control resetting of each block in
  the Tegra system.

properties:
  compatible:
    enum:
      - nvidia,tegra20-car
      - nvidia,tegra30-car
      - nvidia,tegra114-car
      - nvidia,tegra210-car

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  "#reset-cells":
    const: 1

patternProperties:
  "^(sclk)|(pll-[cem])$":
    type: object
    properties:
      compatible:
        enum:
          - nvidia,tegra20-sclk
          - nvidia,tegra30-sclk
          - nvidia,tegra30-pllc
          - nvidia,tegra30-plle
          - nvidia,tegra30-pllm

      operating-points-v2: true

      clocks:
        items:
          - description: node's clock

      power-domains:
        maxItems: 1
        description: phandle to the core SoC power domain

    required:
      - compatible
      - operating-points-v2
      - clocks
      - power-domains

    additionalProperties: false

required:
  - compatible
  - reg
  - '#clock-cells'
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>

    car: clock-controller@60006000 {
        compatible = "nvidia,tegra20-car";
        reg = <0x60006000 0x1000>;
        #clock-cells = <1>;
        #reset-cells = <1>;

        sclk {
            compatible = "nvidia,tegra20-sclk";
            operating-points-v2 = <&opp_table>;
            clocks = <&tegra_car TEGRA20_CLK_SCLK>;
            power-domains = <&domain>;
        };
    };


code:
NXP LPC32xx Clock Controller

Required properties:
- compatible: should be "nxp,lpc3220-clk"
- reg:  should contain clock controller registers location and length
- #clock-cells: must be 1, the cell holds id of a clock provided by the
  clock controller
- clocks: phandles of external oscillators, the list must contain one
  32768 Hz oscillator and may have one optional high frequency oscillator
- clock-names: list of external oscillator clock names, must contain
  "xtal_32k" and may have optional "xtal"

Examples:

	/* System Control Block */
	scb {
		compatible = "simple-bus";
		ranges = <0x0 0x040004000 0x00001000>;
		#address-cells = <1>;
		#size-cells = <1>;

		clk: clock-controller@0 {
			compatible = "nxp,lpc3220-clk";
			reg = <0x00 0x114>;
			#clock-cells = <1>;

			clocks = <&xtal_32k>, <&xtal>;
			clock-names = "xtal_32k", "xtal";
		};
	};


code:
NXP LPC32xx USB Clock Controller

Required properties:
- compatible: should be "nxp,lpc3220-usb-clk"
- reg:  should contain clock controller registers location and length
- #clock-cells: must be 1, the cell holds id of a clock provided by the
  USB clock controller

Examples:

	usb {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0x0 0x31020000 0x00001000>;

		usbclk: clock-controller@f00 {
			compatible = "nxp,lpc3220-usb-clk";
			reg = <0xf00 0x100>;
			#clock-cells = <1>;
		};
	};


code:
Oxford Semiconductor OXNAS SoC Family Standard Clocks
================================================

Please also refer to clock-bindings.txt in this directory for common clock
bindings usage.

Required properties:
- compatible: For OX810SE, should be "oxsemi,ox810se-stdclk"
	      For OX820, should be "oxsemi,ox820-stdclk"
- #clock-cells: 1, see below

Parent node should have the following properties :
- compatible: For OX810SE, should be
		"oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
	      For OX820, should be
		"oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"

example:

sys: sys-ctrl@000000 {
	compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
	reg = <0x000000 0x100000>;

	stdclk: stdclk {
		compatible = "oxsemi,ox810se-stdclk";
		#clock-cells = <1>;
	};
};


code:
Imagination Technologies Pistachio SoC clock controllers
========================================================

Pistachio has four clock controllers (core clock, peripheral clock, peripheral
general control, and top general control) which are instantiated individually
from the device-tree.

External clocks:
----------------

There are three external inputs to the clock controllers which should be
defined with the following clock-output-names:
- "xtal": External 52Mhz oscillator (required)
- "audio_clk_in": Alternate audio reference clock (optional)
- "enet_clk_in": Alternate ethernet PHY clock (optional)

Core clock controller:
----------------------

The core clock controller generates clocks for the CPU, RPU (WiFi + BT
co-processor), audio, and several peripherals.

Required properties:
- compatible: Must be "img,pistachio-clk".
- reg: Must contain the base address and length of the core clock controller.
- #clock-cells: Must be 1.  The single cell is the clock identifier.
  See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
- clocks: Must contain an entry for each clock in clock-names.
- clock-names: Must include "xtal" (see "External clocks") and
  "audio_clk_in_gate", "enet_clk_in_gate" which are generated by the
  top-level general control.

Example:
	clk_core: clock-controller@18144000 {
		compatible = "img,pistachio-clk";
		reg = <0x18144000 0x800>;
		clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
			 <&cr_top EXT_CLK_ENET_IN>;
		clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";

		#clock-cells = <1>;
	};

Peripheral clock controller:
----------------------------

The peripheral clock controller generates clocks for the DDR, ROM, and other
peripherals.  The peripheral system clock ("periph_sys") generated by the core
clock controller is the input clock to the peripheral clock controller.

Required properties:
- compatible: Must be "img,pistachio-periph-clk".
- reg: Must contain the base address and length of the peripheral clock
  controller.
- #clock-cells: Must be 1.  The single cell is the clock identifier.
  See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
- clocks: Must contain an entry for each clock in clock-names.
- clock-names: Must include "periph_sys", the peripheral system clock generated
  by the core clock controller.

Example:
	clk_periph: clock-controller@18144800 {
		compatible = "img,pistachio-clk-periph";
		reg = <0x18144800 0x800>;
		clocks = <&clk_core CLK_PERIPH_SYS>;
		clock-names = "periph_sys";

		#clock-cells = <1>;
	};

Peripheral general control:
---------------------------

The peripheral general control block generates system interface clocks and
resets for various peripherals.  It also contains miscellaneous peripheral
control registers.  The system clock ("sys") generated by the peripheral clock
controller is the input clock to the system clock controller.

Required properties:
- compatible: Must include "img,pistachio-periph-cr" and "syscon".
- reg: Must contain the base address and length of the peripheral general
  control registers.
- #clock-cells: Must be 1.  The single cell is the clock identifier.
  See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
- clocks: Must contain an entry for each clock in clock-names.
- clock-names: Must include "sys", the system clock generated by the peripheral
  clock controller.

Example:
	cr_periph: syscon@18144800 {
		compatible = "img,pistachio-cr-periph", "syscon";
		reg = <0x18148000 0x1000>;
		clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>;
		clock-names = "sys";

		#clock-cells = <1>;
	};

Top-level general control:
--------------------------

The top-level general control block contains miscellaneous control registers and
gates for the external clocks "audio_clk_in" and "enet_clk_in".

Required properties:
- compatible: Must include "img,pistachio-cr-top" and "syscon".
- reg: Must contain the base address and length of the top-level
  control registers.
- clocks: Must contain an entry for each clock in clock-names.
- clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
  "External clocks").
- #clock-cells: Must be 1.  The single cell is the clock identifier.
  See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.

Example:
	cr_top: syscon@18144800 {
		compatible = "img,pistachio-cr-top", "syscon";
		reg = <0x18149000 0x200>;
		clocks = <&audio_refclk>, <&ext_enet_in>;
		clock-names = "audio_clk_in", "enet_clk_in";

		#clock-cells = <1>;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/pwm-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: An external clock signal driven by a PWM pin.

maintainers:
  - Philipp Zabel <p.zabel@pengutronix.de>

properties:
  compatible:
    const: pwm-clock

  '#clock-cells':
    const: 0

  clock-frequency:
    description: Exact output frequency, in case the PWM period is not exact
      but was rounded to nanoseconds.

  clock-output-names:
    maxItems: 1

  pwms:
    maxItems: 1

required:
  - compatible
  - '#clock-cells'
  - pwms

additionalProperties: false

examples:
  - |
    clock {
        compatible = "pwm-clock";
        #clock-cells = <0>;
        clock-frequency = <25000000>;
        clock-output-names = "mipi_mclk";
        pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */
    };
...


code:
* Clock bindings for Marvell PXA chips

Required properties:
- compatible: Should be "marvell,pxa-clocks"
- #clock-cells: Should be <1>

The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell (see include/.../pxa-clock.h).

Examples:

pxa2xx_clks: pxa2xx_clks@41300004 {
        compatible = "marvell,pxa-clocks";
        #clock-cells = <1>;
};


code:
Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller

The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.

Required Properties:
- compatible: has to be "qca,<soctype>-pll" and one of the following
  fallbacks:
  - "qca,ar7100-pll"
  - "qca,ar7240-pll"
  - "qca,ar9130-pll"
  - "qca,ar9330-pll"
  - "qca,ar9340-pll"
  - "qca,qca9550-pll"
- reg: Base address and size of the controllers memory area
- clock-names: Name of the input clock, has to be "ref"
- clocks: phandle of the external reference clock
- #clock-cells: has to be one

Optional properties:
- clock-output-names: should be "cpu", "ddr", "ahb"

Example:

	pll-controller@18050000 {
		compatible = "qca,ar9132-pll", "qca,ar9130-pll";
		reg = <0x18050000 0x20>;

		clock-names = "ref";
		clocks = <&extosc>;

		#clock-cells = <1>;
		clock-output-names = "cpu", "ddr", "ahb";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,a53pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm A53 PLL clock

maintainers:
  - Bjorn Andersson <andersson@kernel.org>

description:
  The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for
  frequencies above 1GHz.

properties:
  compatible:
    enum:
      - qcom,ipq6018-a53pll
      - qcom,ipq8074-a53pll
      - qcom,msm8916-a53pll
      - qcom,msm8939-a53pll

  reg:
    maxItems: 1

  '#clock-cells':
    const: 0

  clocks:
    items:
      - description: board XO clock

  clock-names:
    items:
      - const: xo

  operating-points-v2: true

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  #Example 1 - A53 PLL found on MSM8916 devices
  - |
    a53pll: clock@b016000 {
        compatible = "qcom,msm8916-a53pll";
        reg = <0xb016000 0x40>;
        #clock-cells = <0>;
    };
  #Example 2 - A53 PLL found on IPQ6018 devices
  - |
    a53pll_ipq: clock-controller@b116000 {
        compatible = "qcom,ipq6018-a53pll";
        reg = <0x0b116000 0x40>;
        #clock-cells = <0>;
        clocks = <&xo>;
        clock-names = "xo";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm A7 PLL clock

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

description:
  The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
  frequency clock to the CPU.

properties:
  compatible:
    enum:
      - qcom,sdx55-a7pll

  reg:
    maxItems: 1

  '#clock-cells':
    const: 0

  clocks:
    items:
      - description: board XO clock

  clock-names:
    items:
      - const: bi_tcxo

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    a7pll: clock@17808000 {
        compatible = "qcom,sdx55-a7pll";
        reg = <0x17808000 0x1000>;
        clocks = <&rpmhcc RPMH_CXO_CLK>;
        clock-names = "bi_tcxo";
        #clock-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,aoncc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LPASS Always ON Clock Controller on SM8250 SoCs

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell.
  See include/dt-bindings/clock/qcom,sm8250-lpass-aoncc.h for the full list
  of Audio Clock controller clock IDs.

properties:
  compatible:
    const: qcom,sm8250-lpass-aoncc

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: LPASS Core voting clock
      - description: LPASS Audio codec voting clock
      - description: Glitch Free Mux register clock

  clock-names:
    items:
      - const: core
      - const: audio
      - const: bus

required:
  - compatible
  - reg
  - '#clock-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
    #include <dt-bindings/sound/qcom,q6afe.h>
    clock-controller@3800000 {
      #clock-cells = <1>;
      compatible = "qcom,sm8250-lpass-aoncc";
      reg = <0x03380000 0x40000>;
      clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
               <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
               <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
      clock-names = "core", "audio", "bus";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,audiocc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LPASS Audio Clock Controller on SM8250 SoCs

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description: |
  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell.
  See include/dt-bindings/clock/qcom,sm8250-lpass-audiocc.h for the full list
  of Audio Clock controller clock IDs.

properties:
  compatible:
    const: qcom,sm8250-lpass-audiocc

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: LPASS Core voting clock
      - description: LPASS Audio codec voting clock
      - description: Glitch Free Mux register clock

  clock-names:
    items:
      - const: core
      - const: audio
      - const: bus

required:
  - compatible
  - reg
  - '#clock-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
    #include <dt-bindings/sound/qcom,q6afe.h>
    clock-controller@3300000 {
      #clock-cells = <1>;
      compatible = "qcom,sm8250-lpass-audiocc";
      reg = <0x03300000 0x30000>;
      clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
               <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
               <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
      clock-names = "core", "audio", "bus";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Camera Clock & Reset Controller on SM8250

maintainers:
  - Jonathan Marek <jonathan@marek.ca>

description: |
  Qualcomm camera clock control module provides the clocks, resets and
  power domains on SM8250.

  See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h

properties:
  compatible:
    const: qcom,sm8250-camcc

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: sleep_clk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@ad00000 {
      compatible = "qcom,sm8250-camcc";
      reg = <0x0ad00000 0x10000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&sleep_clk>;
      clock-names = "bi_tcxo", "sleep_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller Binding for SC8280XP

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |
  Qualcomm display clock control module which supports the clocks, resets and
  power domains for the two MDSS instances on SC8280XP.

  See also:
    include/dt-bindings/clock/qcom,dispcc-sc8280xp.h

properties:
  compatible:
    enum:
      - qcom,sc8280xp-dispcc0
      - qcom,sc8280xp-dispcc1

  clocks:
    items:
      - description: AHB interface clock,
      - description: SoC CXO clock
      - description: SoC sleep clock
      - description: DisplayPort 0 link clock
      - description: DisplayPort 0 VCO div clock
      - description: DisplayPort 1 link clock
      - description: DisplayPort 1 VCO div clock
      - description: DisplayPort 2 link clock
      - description: DisplayPort 2 VCO div clock
      - description: DisplayPort 3 link clock
      - description: DisplayPort 3 VCO div clock
      - description: DSI 0 PLL byte clock
      - description: DSI 0 PLL DSI clock
      - description: DSI 1 PLL byte clock
      - description: DSI 1 PLL DSI clock

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

  power-domains:
    items:
      - description: MMCX power domain

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    clock-controller@af00000 {
      compatible = "qcom,sc8280xp-dispcc0";
      reg = <0x0af00000 0x20000>;
      clocks = <&gcc GCC_DISP_AHB_CLK>,
               <&rpmhcc RPMH_CXO_CLK>,
               <&sleep_clk>,
               <&mdss0_dp_phy0 0>,
               <&mdss0_dp_phy0 1>,
               <&mdss0_dp_phy1 0>,
               <&mdss0_dp_phy1 1>,
               <&mdss0_dp_phy2 0>,
               <&mdss0_dp_phy2 1>,
               <&mdss0_dp_phy3 0>,
               <&mdss0_dp_phy3 1>,
               <&mdss0_dsi0_phy 0>,
               <&mdss0_dsi0_phy 1>,
               <&mdss0_dsi1_phy 0>,
               <&mdss0_dsi1_phy 1>;
      power-domains = <&rpmhpd SC8280XP_MMCX>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock Controller on SM6125

maintainers:
  - Martin Botka <martin.botka@somainline.org>

description: |
  Qualcomm display clock control module provides the clocks and power domains
  on SM6125.

  See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h

properties:
  compatible:
    enum:
      - qcom,sm6125-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY0
      - description: Pixel clock from DSI PHY1
      - description: Link clock from DP PHY
      - description: VCO DIV clock from DP PHY
      - description: AHB config clock from GCC

  clock-names:
    items:
      - const: bi_tcxo
      - const: dsi0_phy_pll_out_byteclk
      - const: dsi0_phy_pll_out_dsiclk
      - const: dsi1_phy_pll_out_dsiclk
      - const: dp_phy_pll_link_clk
      - const: dp_phy_pll_vco_div_clk
      - const: cfg_ahb_clk

  '#clock-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmcc.h>
    #include <dt-bindings/clock/qcom,gcc-sm6125.h>
    clock-controller@5f00000 {
      compatible = "qcom,sm6125-dispcc";
      reg = <0x5f00000 0x20000>;
      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
               <&dsi0_phy 0>,
               <&dsi0_phy 1>,
               <&dsi1_phy 1>,
               <&dp_phy 0>,
               <&dp_phy 1>,
               <&gcc GCC_DISP_AHB_CLK>;
      clock-names = "bi_tcxo",
                    "dsi0_phy_pll_out_byteclk",
                    "dsi0_phy_pll_out_dsiclk",
                    "dsi1_phy_pll_out_dsiclk",
                    "dp_phy_pll_link_clk",
                    "dp_phy_pll_vco_div_clk",
                    "cfg_ahb_clk";
      #clock-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on SM6350

maintainers:
  - Konrad Dybcio <konrad.dybcio@somainline.org>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on SM6350.

  See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h

properties:
  compatible:
    const: qcom,sm6350-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 source from GCC
      - description: Byte clock from DSI PHY
      - description: Pixel clock from DSI PHY
      - description: Link clock from DP PHY
      - description: VCO DIV clock from DP PHY

  clock-names:
    items:
      - const: bi_tcxo
      - const: gcc_disp_gpll0_clk
      - const: dsi0_phy_pll_out_byteclk
      - const: dsi0_phy_pll_out_dsiclk
      - const: dp_phy_pll_link_clk
      - const: dp_phy_pll_vco_div_clk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sm6350.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@af00000 {
      compatible = "qcom,sm6350-dispcc";
      reg = <0x0af00000 0x20000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&gcc GCC_DISP_GPLL0_CLK>,
               <&dsi_phy 0>,
               <&dsi_phy 1>,
               <&dp_phy 0>,
               <&dp_phy 1>;
      clock-names = "bi_tcxo",
                    "gcc_disp_gpll0_clk",
                    "dsi0_phy_pll_out_byteclk",
                    "dsi0_phy_pll_out_dsiclk",
                    "dp_phy_pll_link_clk",
                    "dp_phy_pll_vco_div_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350

maintainers:
  - Jonathan Marek <jonathan@marek.ca>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on SM8150/SM8250/SM8350.

  See also::
    include/dt-bindings/clock/qcom,dispcc-sm8150.h
    include/dt-bindings/clock/qcom,dispcc-sm8250.h
    include/dt-bindings/clock/qcom,dispcc-sm8350.h

properties:
  compatible:
    enum:
      - qcom,sc8180x-dispcc
      - qcom,sm8150-dispcc
      - qcom,sm8250-dispcc
      - qcom,sm8350-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY0
      - description: Byte clock from DSI PHY1
      - description: Pixel clock from DSI PHY1
      - description: Link clock from DP PHY
      - description: VCO DIV clock from DP PHY

  clock-names:
    items:
      - const: bi_tcxo
      - const: dsi0_phy_pll_out_byteclk
      - const: dsi0_phy_pll_out_dsiclk
      - const: dsi1_phy_pll_out_byteclk
      - const: dsi1_phy_pll_out_dsiclk
      - const: dp_phy_pll_link_clk
      - const: dp_phy_pll_vco_div_clk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

  power-domains:
    description:
      A phandle and PM domain specifier for the MMCX power domain.
    maxItems: 1

  required-opps:
    description:
      A phandle to an OPP node describing required MMCX performance point.
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    clock-controller@af00000 {
      compatible = "qcom,sm8250-dispcc";
      reg = <0x0af00000 0x10000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&dsi0_phy 0>,
               <&dsi0_phy 1>,
               <&dsi1_phy 0>,
               <&dsi1_phy 1>,
               <&dp_phy 0>,
               <&dp_phy 1>;
      clock-names = "bi_tcxo",
                    "dsi0_phy_pll_out_byteclk",
                    "dsi0_phy_pll_out_dsiclk",
                    "dsi1_phy_pll_out_byteclk",
                    "dsi1_phy_pll_out_dsiclk",
                    "dp_phy_pll_link_clk",
                    "dp_phy_pll_vco_div_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
      power-domains = <&rpmhpd SM8250_MMCX>;
      required-opps = <&rpmhpd_opp_low_svs>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on APQ8064/MSM8960

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on APQ8064.

  See also::
    include/dt-bindings/clock/qcom,gcc-msm8960.h
    include/dt-bindings/reset/qcom,gcc-msm8960.h

allOf:
  - $ref: qcom,gcc.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - qcom,gcc-apq8064
              - qcom,gcc-msm8960
          - const: syscon
      - enum:
          - qcom,gcc-apq8064
          - qcom,gcc-msm8960
        deprecated: true

  thermal-sensor:
    description: child tsens device
    $ref: /schemas/thermal/qcom-tsens.yaml#

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: cxo
      - const: pxo
      - const: pll4

  nvmem-cells:
    minItems: 1
    maxItems: 2
    deprecated: true
    description:
      Qualcomm TSENS (thermal sensor device) on some devices can
      be part of GCC and hence the TSENS properties can also be part
      of the GCC/clock-controller node.
      For more details on the TSENS properties please refer
      Documentation/devicetree/bindings/thermal/qcom-tsens.yaml

  nvmem-cell-names:
    minItems: 1
    deprecated: true
    items:
      - const: calib
      - const: calib_backup

  '#thermal-sensor-cells':
    const: 1
    deprecated: true

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    clock-controller@900000 {
      compatible = "qcom,gcc-apq8064", "syscon";
      reg = <0x00900000 0x4000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;

      thermal-sensor {
        compatible = "qcom,msm8960-tsens";

        nvmem-cells = <&tsens_calib>, <&tsens_backup>;
        nvmem-cell-names = "calib", "calib_backup";
        interrupts = <0 178 4>;
        interrupt-names = "uplow";

        #qcom,sensors = <11>;
        #thermal-sensor-cells = <1>;
      };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on APQ8084

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <quic_tdas@quicinc.com>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on APQ8084.

  See also::
    include/dt-bindings/clock/qcom,gcc-apq8084.h
    include/dt-bindings/reset/qcom,gcc-apq8084.h

allOf:
  - $ref: qcom,gcc.yaml#

properties:
  compatible:
    const: qcom,gcc-apq8084

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    clock-controller@fc400000 {
        compatible = "qcom,gcc-apq8084";
        reg = <0xfc400000 0x4000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on IPQ8064

maintainers:
  - Ansuel Smith <ansuelsmth@gmail.com>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on IPQ8064.

  See also::
    include/dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
    include/dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)

allOf:
  - $ref: qcom,gcc.yaml#

properties:
  compatible:
    items:
      - const: qcom,gcc-ipq8064
      - const: syscon

  clocks:
    minItems: 2
    items:
      - description: PXO source
      - description: CXO source
      - description: PLL4 from LCC

  clock-names:
    minItems: 2
    items:
      - const: pxo
      - const: cxo
      - const: pll4

  thermal-sensor:
    type: object

    allOf:
      - $ref: /schemas/thermal/qcom-tsens.yaml#

required:
  - compatible
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gcc: clock-controller@900000 {
      compatible = "qcom,gcc-ipq8064", "syscon";
      reg = <0x00900000 0x4000>;
      clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
      clock-names = "pxo", "cxo", "pll4";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;

      tsens: thermal-sensor {
        compatible = "qcom,ipq8064-tsens";

        nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
        nvmem-cell-names = "calib", "calib_backup";
        interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "uplow";

        #qcom,sensors = <11>;
        #thermal-sensor-cells = <1>;
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on IPQ8074

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on IPQ8074.

  See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h

allOf:
  - $ref: qcom,gcc.yaml#

properties:
  compatible:
    const: qcom,gcc-ipq8074

  clocks:
    items:
      - description: board XO clock
      - description: sleep clock

  clock-names:
    items:
      - const: xo
      - const: sleep_clk

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    clock-controller@1800000 {
      compatible = "qcom,gcc-ipq8074";
      reg = <0x01800000 0x80000>;
      #clock-cells = <1>;
      #power-domain-cells = <1>;
      #reset-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on MSM8660

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <quic_tdas@quicinc.com>

description: |
  Qualcomm global clock control module provides the clocks and resets on
  MSM8660

  See also::
    include/dt-bindings/clock/qcom,gcc-msm8660.h
    include/dt-bindings/reset/qcom,gcc-msm8660.h

allOf:
  - $ref: qcom,gcc.yaml#

properties:
  compatible:
    enum:
      - qcom,gcc-msm8660

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: pxo
      - const: cxo

required:
  - compatible

unevaluatedProperties: false

examples:
  # Example for GCC for MSM8974:
  - |
    clock-controller@900000 {
      compatible = "qcom,gcc-msm8660";
      reg = <0x900000 0x4000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
      clocks = <&pxo_board>, <&cxo_board>;
      clock-names = "pxo", "cxo";
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on MSM8909

maintainers:
  - Stephan Gerhold <stephan@gerhold.net>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on MSM8909.

  See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h

properties:
  compatible:
    const: qcom,gcc-msm8909

  clocks:
    items:
      - description: XO source
      - description: Sleep clock source
      - description: DSI phy instance 0 dsi clock
      - description: DSI phy instance 0 byte clock

  clock-names:
    items:
      - const: xo
      - const: sleep_clk
      - const: dsi0pll
      - const: dsi0pllbyte

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    gcc: clock-controller@1800000 {
      compatible = "qcom,gcc-msm8909";
      reg = <0x01800000 0x80000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
      clocks = <&xo_board>, <&sleep_clk>, <&dsi0_phy 1>, <&dsi0_phy 0>;
      clock-names = "xo", "sleep_clk", "dsi0pll", "dsi0pllbyte";
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on MSM8916 and MSM8939

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <quic_tdas@quicinc.com>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on MSM8916 or MSM8939.

  See also::
    include/dt-bindings/clock/qcom,gcc-msm8916.h
    include/dt-bindings/clock/qcom,gcc-msm8939.h
    include/dt-bindings/reset/qcom,gcc-msm8916.h
    include/dt-bindings/reset/qcom,gcc-msm8939.h

properties:
  compatible:
    enum:
      - qcom,gcc-msm8916
      - qcom,gcc-msm8939

  clocks:
    items:
      - description: XO source
      - description: Sleep clock source
      - description: DSI phy instance 0 dsi clock
      - description: DSI phy instance 0 byte clock
      - description: External MCLK clock
      - description: External Primary I2S clock
      - description: External Secondary I2S clock

  clock-names:
    items:
      - const: xo
      - const: sleep_clk
      - const: dsi0pll
      - const: dsi0pllbyte
      - const: ext_mclk
      - const: ext_pri_i2s
      - const: ext_sec_i2s

required:
  - compatible

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    clock-controller@300000 {
      compatible = "qcom,gcc-msm8916";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
      reg = <0x300000 0x90000>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8974.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on MSM8974 (including Pro) and MSM8226
  Controller

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <quic_tdas@quicinc.com>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on MSM8974 (all variants) and MSM8226.

  See also::
    include/dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
    include/dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)

$ref: qcom,gcc.yaml#

properties:
  compatible:
    enum:
      - qcom,gcc-msm8226
      - qcom,gcc-msm8974
      - qcom,gcc-msm8974pro
      - qcom,gcc-msm8974pro-ac

  clocks:
    items:
      - description: XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: xo
      - const: sleep_clk

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@fc400000 {
        compatible = "qcom,gcc-msm8974";
        reg = <0x00100000 0x94000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        #power-domain-cells = <1>;

        clock-names = "xo", "sleep_clk";
        clocks = <&xo_board>,
                 <&sleep_clk>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on MSM8976

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on MSM8976.

  See also:: include/dt-bindings/clock/qcom,gcc-msm8976.h

properties:
  compatible:
    enum:
      - qcom,gcc-msm8976
      - qcom,gcc-msm8976-v1.1

  clocks:
    items:
      - description: XO source
      - description: Always-on XO source
      - description: Pixel clock from DSI PHY0
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY1
      - description: Byte clock from DSI PHY1

  clock-names:
    items:
      - const: xo
      - const: xo_a
      - const: dsi0pll
      - const: dsi0pllbyte
      - const: dsi1pll
      - const: dsi1pllbyte

  vdd_gfx-supply:
    description:
      Phandle to voltage regulator providing power to the GX domain.

required:
  - compatible
  - clocks
  - clock-names
  - vdd_gfx-supply

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    clock-controller@1800000 {
      compatible = "qcom,gcc-msm8976";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
      reg = <0x1800000 0x80000>;

      clocks = <&xo_board>,
               <&xo_board>,
               <&dsi0_phy 1>,
               <&dsi0_phy 0>,
               <&dsi1_phy 1>,
               <&dsi1_phy 0>;

      clock-names = "xo",
                    "xo_a",
                    "dsi0pll",
                    "dsi0pllbyte",
                    "dsi1pll",
                    "dsi1pllbyte";

      vdd_gfx-supply = <&pm8004_s5>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8994.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on MSM8994

maintainers:
  - Konrad Dybcio <konrad.dybcio@somainline.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on MSM8994 and MSM8992.

  See also:: include/dt-bindings/clock/qcom,gcc-msm8994.h

properties:
  compatible:
    enum:
      - qcom,gcc-msm8992
      - qcom,gcc-msm8994

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: xo
      - const: sleep

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    clock-controller@300000 {
      compatible = "qcom,gcc-msm8994";
      reg = <0x00300000 0x90000>;
      clocks = <&xo_board>, <&sleep_clk>;
      clock-names = "xo", "sleep";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on MSM8996

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module which provides the clocks, resets and
  power domains on MSM8996.

  See also:: include/dt-bindings/clock/qcom,gcc-msm8996.h

properties:
  compatible:
    const: qcom,gcc-msm8996

  clocks:
    minItems: 3
    items:
      - description: XO source
      - description: Second XO source
      - description: Sleep clock source
      - description: PCIe 0 PIPE clock (optional)
      - description: PCIe 1 PIPE clock (optional)
      - description: PCIe 2 PIPE clock (optional)
      - description: USB3 PIPE clock (optional)
      - description: UFS RX symbol 0 clock (optional)
      - description: UFS RX symbol 1 clock (optional)
      - description: UFS TX symbol 0 clock (optional)

  clock-names:
    minItems: 3
    items:
      - const: cxo
      - const: cxo2
      - const: sleep_clk
      - const: pcie_0_pipe_clk_src
      - const: pcie_1_pipe_clk_src
      - const: pcie_2_pipe_clk_src
      - const: usb3_phy_pipe_clk_src
      - const: ufs_rx_symbol_0_clk_src
      - const: ufs_rx_symbol_1_clk_src
      - const: ufs_tx_symbol_0_clk_src

required:
  - compatible

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    clock-controller@300000 {
      compatible = "qcom,gcc-msm8996";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
      reg = <0x300000 0x90000>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on MSM8998

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on MSM8998.

  See also:: include/dt-bindings/clock/qcom,gcc-msm8998.h

properties:
  compatible:
    const: qcom,gcc-msm8998

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source
      - description: Audio reference clock (Optional clock)
      - description: PLL test clock source (Optional clock)
    minItems: 2

  clock-names:
    items:
      - const: xo
      - const: sleep_clk
      - const: aud_ref_clk # Optional clock
      - const: core_bi_pll_test_se # Optional clock
    minItems: 2

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmcc.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-msm8998";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
      reg = <0x00100000 0xb0000>;
      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
               <&sleep>,
               <0>,
               <0>;
      clock-names = "xo",
                    "sleep_clk",
                    "aud_ref_clk",
                    "core_bi_pll_test_se";
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains.

  See also::
    include/dt-bindings/clock/qcom,gcc-ipq4019.h
    include/dt-bindings/clock/qcom,gcc-ipq6018.h
    include/dt-bindings/reset/qcom,gcc-ipq6018.h
    include/dt-bindings/clock/qcom,gcc-msm8953.h
    include/dt-bindings/clock/qcom,gcc-mdm9607.h
    include/dt-bindings/clock/qcom,gcc-mdm9615.h
    include/dt-bindings/reset/qcom,gcc-mdm9615.h

allOf:
  - $ref: qcom,gcc.yaml#

properties:
  compatible:
    enum:
      - qcom,gcc-ipq4019
      - qcom,gcc-ipq6018
      - qcom,gcc-mdm9607
      - qcom,gcc-msm8953
      - qcom,gcc-mdm9615

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    clock-controller@900000 {
      compatible = "qcom,gcc-mdm9607";
      reg = <0x900000 0x4000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-qcm2290.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on QCM2290

maintainers:
  - Shawn Guo <shawn.guo@linaro.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on QCM2290.

  See also:: include/dt-bindings/clock/qcom,gcc-qcm2290.h

properties:
  compatible:
    const: qcom,gcc-qcm2290

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: sleep_clk

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmcc.h>
    clock-controller@1400000 {
        compatible = "qcom,gcc-qcm2290";
        reg = <0x01400000 0x1f0000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        #power-domain-cells = <1>;
        clock-names = "bi_tcxo", "sleep_clk";
        clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on QCS404

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on QCS404.

  See also:: include/dt-bindings/clock/qcom,gcc-qcs404.h

properties:
  compatible:
    const: qcom,gcc-qcs404

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  reg:
    maxItems: 1

  protected-clocks:
    description:
      Protected clock specifier list as per common clock binding.

required:
  - compatible
  - reg
  - '#clock-cells'
  - '#reset-cells'

additionalProperties: false

examples:
  - |
    clock-controller@1800000 {
      compatible = "qcom,gcc-qcs404";
      reg = <0x01800000 0x80000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SC7180

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SC7180.

  See also:: include/dt-bindings/clock/qcom,gcc-sc7180.h

properties:
  compatible:
    const: qcom,gcc-sc7180

  clocks:
    items:
      - description: Board XO source
      - description: Board active XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: bi_tcxo_ao
      - const: sleep_clk

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sc7180";
      reg = <0x00100000 0x1f0000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&rpmhcc RPMH_CXO_CLK_A>,
               <&sleep_clk>;
      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...