code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
//
// Copyright (C) 2016-2018 Zodiac Inflight Innovations

/dts-v1/;
#include "vf610.dtsi"

/ {
	model = "ZII VF610 SCU4 AIB";
	compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";

	chosen {
		stdout-path = &uart0;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pinctrl_leds_debug>;
		pinctrl-names = "default";

		debug {
			label = "zii:green:debug1";
			gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	mdio-mux {
		compatible = "mdio-mux-gpio";
		pinctrl-0 = <&pinctrl_mdio_mux>;
		pinctrl-names = "default";
		gpios = <&gpio4 4  GPIO_ACTIVE_HIGH
			 &gpio4 5  GPIO_ACTIVE_HIGH
			 &gpio3 30 GPIO_ACTIVE_HIGH
			 &gpio3 31 GPIO_ACTIVE_HIGH>;
		mdio-parent-bus = <&mdio1>;
		#address-cells = <1>;
		#size-cells = <0>;

		mdio_mux_1: mdio@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			switch0: switch0@0 {
				compatible = "marvell,mv88e6190";
				reg = <0>;
				dsa,member = <0 0>;
				eeprom-length = <65536>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						label = "cpu";
						ethernet = <&fec1>;

						fixed-link {
							speed = <100>;
							full-duplex;
						};
					};

					port@1 {
						reg = <1>;
						label = "aib2main_1";
					};

					port@2 {
						reg = <2>;
						label = "aib2main_2";
					};

					port@3 {
						reg = <3>;
						label = "eth_cu_1000_5";
					};

					port@4 {
						reg = <4>;
						label = "eth_cu_1000_6";
					};

					port@5 {
						reg = <5>;
						label = "eth_cu_1000_4";
					};

					port@6 {
						reg = <6>;
						label = "eth_cu_1000_7";
					};

					port@7 {
						reg = <7>;
						label = "modem_pic";

						fixed-link {
							speed = <100>;
							full-duplex;
						};
					};

					switch0port10: port@10 {
						reg = <10>;
						label = "dsa";
						phy-mode = "xgmii";
						link = <&switch1port10
							&switch3port10
							&switch2port10>;
					};
				};
			};
		};

		mdio_mux_2: mdio@2 {
			reg = <2>;
			#address-cells = <1>;
			#size-cells = <0>;

			switch1: switch1@0 {
				compatible = "marvell,mv88e6190";
				reg = <0>;
				dsa,member = <0 1>;
				eeprom-length = <65536>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@1 {
						reg = <1>;
						label = "eth_cu_1000_3";
					};

					port@2 {
						reg = <2>;
						label = "eth_cu_100_2";
					};

					port@3 {
						reg = <3>;
						label = "eth_cu_100_3";
					};

					switch1port9: port@9 {
						reg = <9>;
						label = "dsa";
						phy-mode = "xgmii";
						link = <&switch3port10
							&switch2port10>;
					};

					switch1port10: port@10 {
						reg = <10>;
						label = "dsa";
						phy-mode = "xgmii";
						link = <&switch0port10>;
					};
				};
			};
		};

		mdio_mux_4: mdio@4 {
			reg = <4>;
			#address-cells = <1>;
			#size-cells = <0>;

			switch2: switch2@0 {
				compatible = "marvell,mv88e6190";
				reg = <0>;
				dsa,member = <0 2>;
				eeprom-length = <65536>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@2 {
						reg = <2>;
						label = "eth_fc_1000_2";
						phy-mode = "1000base-x";
						managed = "in-band-status";
						sfp = <&sff1>;
					};

					port@3 {
						reg = <3>;
						label = "eth_fc_1000_3";
						phy-mode = "1000base-x";
						managed = "in-band-status";
						sfp = <&sff2>;
					};

					port@4 {
						reg = <4>;
						label = "eth_fc_1000_4";
						phy-mode = "1000base-x";
						managed = "in-band-status";
						sfp = <&sff3>;
					};

					port@5 {
						reg = <5>;
						label = "eth_fc_1000_5";
						phy-mode = "1000base-x";
						managed = "in-band-status";
						sfp = <&sff4>;
					};

					port@6 {
						reg = <6>;
						label = "eth_fc_1000_6";
						phy-mode = "1000base-x";
						managed = "in-band-status";
						sfp = <&sff5>;
					};

					port@7 {
						reg = <7>;
						label = "eth_fc_1000_7";
						phy-mode = "1000base-x";
						managed = "in-band-status";
						sfp = <&sff6>;
					};

					port@9 {
						reg = <9>;
						label = "eth_fc_1000_1";
						phy-mode = "1000base-x";
						managed = "in-band-status";
						sfp = <&sff0>;
					};

					switch2port10: port@10 {
						reg = <10>;
						label = "dsa";
						phy-mode = "2500base-x";
						link = <&switch3port9
							&switch1port9
							&switch0port10>;
					};
				};
			};
		};

		mdio_mux_8: mdio@8 {
			reg = <8>;
			#address-cells = <1>;
			#size-cells = <0>;

			switch3: switch3@0 {
				compatible = "marvell,mv88e6190";
				reg = <0>;
				dsa,member = <0 3>;
				eeprom-length = <65536>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@2 {
						reg = <2>;
						label = "eth_fc_1000_8";
						phy-mode = "1000base-x";
						managed = "in-band-status";
						sfp = <&sff7>;
					};

					port@3 {
						reg = <3>;
						label = "eth_fc_1000_9";
						phy-mode = "1000base-x";
						managed = "in-band-status";
						sfp = <&sff8>;
					};

					port@4 {
						reg = <4>;
						label = "eth_fc_1000_10";
						phy-mode = "1000base-x";
						managed = "in-band-status";
						sfp = <&sff9>;
					};

					switch3port9: port@9 {
						reg = <9>;
						label = "dsa";
						phy-mode = "2500base-x";
						link = <&switch2port10>;
					};

					switch3port10: port@10 {
						reg = <10>;
						label = "dsa";
						phy-mode = "xgmii";
						link = <&switch1port9
							&switch0port10>;
					};
				};
			};
		};
	};

	sff0: sff0 {
		compatible = "sff,sff";
		i2c-bus = <&sff0_i2c>;
		los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
	};

	sff1: sff1 {
		compatible = "sff,sff";
		i2c-bus = <&sff1_i2c>;
		los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
	};

	sff2: sff2 {
		compatible = "sff,sff";
		i2c-bus = <&sff2_i2c>;
		los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
	};

	sff3: sff3 {
		compatible = "sff,sff";
		i2c-bus = <&sff3_i2c>;
		los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
	};

	sff4: sff4 {
		compatible = "sff,sff";
		i2c-bus = <&sff4_i2c>;
		los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
	};

	sff5: sff5 {
		compatible = "sff,sff";
		i2c-bus = <&sff5_i2c>;
		los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>;
	};

	sff6: sff6 {
		compatible = "sff,sff";
		i2c-bus = <&sff6_i2c>;
		los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
	};

	sff7: sff7 {
		compatible = "sff,sff";
		i2c-bus = <&sff7_i2c>;
		los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
	};

	sff8: sff8 {
		compatible = "sff,sff";
		i2c-bus = <&sff8_i2c>;
		los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
	};

	sff9: sff9 {
		compatible = "sff,sff";
		i2c-bus = <&sff9_i2c>;
		los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
	};

	reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3_mcu";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&dspi0 {
	pinctrl-0 = <&pinctrl_dspi0>;
	pinctrl-names = "default";
	bus-num = <0>;
	status = "okay";

	adc@5 {
		compatible = "holt,hi8435";
		reg = <5>;
		gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
		spi-max-frequency = <1000000>;
	};
};

&dspi1 {
	bus-num = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi1>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <50000000>;

		partition@0 {
			label = "m25p128-0";
			reg = <0x0 0x01000000>;
		};
	};

	flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <1>;
		spi-max-frequency = <50000000>;

		partition@0 {
			label = "m25p128-1";
			reg = <0x0 0x01000000>;
		};
	};
};

&adc0 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
};

&adc1 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
};

&edma0 {
	status = "okay";
};

&edma1 {
	status = "okay";
};

&esdhc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc0>;
	bus-width = <8>;
	non-removable;
	no-1-8-v;
	no-sd;
	no-sdio;
	keep-power-in-suspend;
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	no-sdio;
	status = "okay";
};

&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";

	fixed-link {
		   speed = <100>;
		   full-duplex;
	};

	mdio1: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
	};
};

&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	gpio5: io-expander@20 {
		compatible = "nxp,pca9554";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpio6: io-expander@22 {
		compatible = "nxp,pca9554";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	temp-sensor@48 {
		compatible = "national,lm75";
		reg = <0x48>;
	};

	eeprom@50 {
		compatible = "atmel,24c04";
		reg = <0x50>;
	};

	eeprom@52 {
		compatible = "atmel,24c04";
		reg = <0x52>;
	};

	elapsed-time-recorder@6b {
		compatible = "dallas,ds1682";
		reg = <0x6b>;
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	watchdog@38 {
		compatible = "zii,rave-wdt";
		reg = <0x38>;
	};

	adc@4a {
		compatible = "adi,adt7411";
		reg = <0x4a>;
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	gpio9: io-expander@20 {
		compatible = "semtech,sx1503q";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_sx1503_20>;
		#gpio-cells = <2>;
		reg = <0x20>;
		gpio-controller;
		interrupt-parent = <&gpio1>;
		interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
	};

	temp-sensor@4e {
		compatible = "national,lm75";
		reg = <0x4e>;
	};

	temp-sensor@4f {
		compatible = "national,lm75";
		reg = <0x4f>;
	};

	gpio7: io-expander@23 {
		compatible = "nxp,pca9555";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x23>;
	};

	adc@4a {
		compatible = "adi,adt7411";
		reg = <0x4a>;
	};

	eeprom@54 {
		compatible = "atmel,24c08";
		reg = <0x54>;
	};

	i2c-mux@70 {
		compatible = "nxp,pca9548";
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;
		i2c-mux-idle-disconnect;

		sff0_i2c: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};

		sff1_i2c: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};

		sff2_i2c: i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};

		sff3_i2c: i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
		};

		sff4_i2c: i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
		};
	};

	i2c-mux@71 {
		compatible = "nxp,pca9548";
		pinctrl-names = "default";
		reg = <0x71>;
		#address-cells = <1>;
		#size-cells = <0>;
		i2c-mux-idle-disconnect;

		sff5_i2c: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};

		sff6_i2c: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};

		sff7_i2c: i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};

		sff8_i2c: i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
		};

		sff9_i2c: i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
		};
	};
};

&snvsrtc {
	status = "disabled";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	status = "okay";
};

&uart1 {
	linux,rs485-enabled-at-boot-time;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	linux,rs485-enabled-at-boot-time;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&iomuxc {
	pinctrl_dspi0: dspi0grp {
		fsl,pins = <
			VF610_PAD_PTB19__DSPI0_CS0		0x1182
			VF610_PAD_PTB18__DSPI0_CS1		0x1182
			VF610_PAD_PTB13__DSPI0_CS4		0x1182
			VF610_PAD_PTB12__DSPI0_CS5		0x1182
			VF610_PAD_PTB20__DSPI0_SIN		0x1181
			VF610_PAD_PTB21__DSPI0_SOUT		0x1182
			VF610_PAD_PTB22__DSPI0_SCK		0x1182
		>;
	};

	pinctrl_dspi1: dspi1grp {
		fsl,pins = <
			VF610_PAD_PTD5__DSPI1_CS0		0x1182
			VF610_PAD_PTD4__DSPI1_CS1		0x1182
			VF610_PAD_PTC6__DSPI1_SIN		0x1181
			VF610_PAD_PTC7__DSPI1_SOUT		0x1182
			VF610_PAD_PTC8__DSPI1_SCK		0x1182
		>;
	};

	pinctrl_dspi2: dspi2gpio {
		fsl,pins = <
			VF610_PAD_PTD30__GPIO_64		0x33e2
			VF610_PAD_PTD29__GPIO_65		0x33e1
			VF610_PAD_PTD28__GPIO_66		0x33e2
			VF610_PAD_PTD27__GPIO_67		0x33e2
			VF610_PAD_PTD26__GPIO_68		0x31c2
		>;
	};

	pinctrl_esdhc0: esdhc0grp {
		fsl,pins = <
			VF610_PAD_PTC0__ESDHC0_CLK		0x31ef
			VF610_PAD_PTC1__ESDHC0_CMD		0x31ef
			VF610_PAD_PTC2__ESDHC0_DAT0		0x31ef
			VF610_PAD_PTC3__ESDHC0_DAT1		0x31ef
			VF610_PAD_PTC4__ESDHC0_DAT2		0x31ef
			VF610_PAD_PTC5__ESDHC0_DAT3		0x31ef
			VF610_PAD_PTD23__ESDHC0_DAT4		0x31ef
			VF610_PAD_PTD22__ESDHC0_DAT5		0x31ef
			VF610_PAD_PTD21__ESDHC0_DAT6		0x31ef
			VF610_PAD_PTD20__ESDHC0_DAT7		0x31ef
		>;
	};

	pinctrl_esdhc1: esdhc1grp {
		fsl,pins = <
			VF610_PAD_PTA24__ESDHC1_CLK		0x31ef
			VF610_PAD_PTA25__ESDHC1_CMD		0x31ef
			VF610_PAD_PTA26__ESDHC1_DAT0		0x31ef
			VF610_PAD_PTA27__ESDHC1_DAT1		0x31ef
			VF610_PAD_PTA28__ESDHC1_DATA2		0x31ef
			VF610_PAD_PTA29__ESDHC1_DAT3		0x31ef
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			VF610_PAD_PTA6__RMII_CLKIN		0x30d1
			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
			VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
		>;
	};

	pinctrl_i2c0: i2c0grp {
		fsl,pins = <
			VF610_PAD_PTB14__I2C0_SCL		0x37ff
			VF610_PAD_PTB15__I2C0_SDA		0x37ff
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			VF610_PAD_PTB16__I2C1_SCL		0x37ff
			VF610_PAD_PTB17__I2C1_SDA		0x37ff
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			VF610_PAD_PTA22__I2C2_SCL		0x37ff
			VF610_PAD_PTA23__I2C2_SDA		0x37ff
		>;
	};

	pinctrl_leds_debug: pinctrl-leds-debug {
		fsl,pins = <
			 VF610_PAD_PTB26__GPIO_96		0x31c2
		   >;
	};

	pinctrl_mdio_mux: pinctrl-mdio-mux {
		fsl,pins = <
			VF610_PAD_PTE27__GPIO_132		0x31c2
			VF610_PAD_PTE28__GPIO_133		0x31c2
			VF610_PAD_PTE21__GPIO_126		0x31c2
			VF610_PAD_PTE22__GPIO_127		0x31c2
		>;
	};

	pinctrl_qspi0: qspi0grp {
		fsl,pins = <
			VF610_PAD_PTD7__QSPI0_B_QSCK		0x31c3
			VF610_PAD_PTD8__QSPI0_B_CS0		0x31ff
			VF610_PAD_PTD9__QSPI0_B_DATA3		0x31c3
			VF610_PAD_PTD10__QSPI0_B_DATA2		0x31c3
			VF610_PAD_PTD11__QSPI0_B_DATA1		0x31c3
			VF610_PAD_PTD12__QSPI0_B_DATA0		0x31c3
		>;
	};

	pinctrl_sx1503_20: pinctrl-sx1503-20 {
		fsl,pins = <
			VF610_PAD_PTD31__GPIO_63		0x219d
			>;
	};

	pinctrl_uart0: uart0grp {
		fsl,pins = <
			VF610_PAD_PTB10__UART0_TX		0x21a2
			VF610_PAD_PTB11__UART0_RX		0x21a1
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			VF610_PAD_PTB23__UART1_TX		0x21a2
			VF610_PAD_PTB24__UART1_RX		0x21a1
			VF610_PAD_PTB25__UART1_RTS		0x21a2	/* Used as DE signal for the RS-485 transceiver */
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			VF610_PAD_PTD0__UART2_TX		0x21a2
			VF610_PAD_PTD1__UART2_RX		0x21a1
			VF610_PAD_PTD2__UART2_RTS		0x21a2 /* Used as DE signal for the RS-485 transceiver */
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/*
 * Device tree file for ZII's SPB4 board
 *
 * SPB - Seat Power Box
 *
 * Copyright (C) 2019 Zodiac Inflight Innovations
 */

/dts-v1/;
#include "vf610.dtsi"

/ {
	model = "ZII VF610 SPB4 Board";
	compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610";

	chosen {
		stdout-path = &uart0;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pinctrl_leds_debug>;
		pinctrl-names = "default";

		led-debug {
			label = "zii:green:debug1";
			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3_mcu";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	supply-voltage-monitor {
		compatible = "iio-hwmon";
		io-channels = <&adc0 8>, /* 28V_SW   */
			      <&adc0 9>, /* +3.3V    */
			      <&adc1 8>, /* VCC_1V5  */
			      <&adc1 9>; /* VCC_1V2  */
	};
};

&adc0 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
};

&adc1 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
};

&dspi1 {
	bus-num = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi1>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p128", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <50000000>;
	};
};

&edma0 {
	status = "okay";
};

&edma1 {
	status = "okay";
};

&esdhc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc0>;
	bus-width = <8>;
	non-removable;
	no-1-8-v;
	keep-power-in-suspend;
	no-sdio;
	no-sd;
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	no-sdio;
	status = "okay";
};

&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";

	fixed-link {
		speed = <100>;
		full-duplex;
	};

	mdio1: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <12500000>;
		suppress-preamble;
		status = "okay";

		switch0: switch0@0 {
			compatible = "marvell,mv88e6190";
			pinctrl-0 = <&pinctrl_gpio_switch0>;
			pinctrl-names = "default";
			reg = <0>;
			eeprom-length = <65536>;
			interrupt-parent = <&gpio3>;
			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
			interrupt-controller;
			#interrupt-cells = <2>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "cpu";
					ethernet = <&fec1>;

					fixed-link {
						speed = <100>;
						full-duplex;
					};
				};

				port@1 {
					reg = <1>;
					label = "eth_cu_1000_1";
				};

				port@2 {
					reg = <2>;
					label = "eth_cu_1000_2";
				};

				port@3 {
					reg = <3>;
					label = "eth_cu_1000_3";
				};

				port@4 {
					reg = <4>;
					label = "eth_cu_1000_4";
				};

				port@5 {
					reg = <5>;
					label = "eth_cu_1000_5";
				};

				port@6 {
					reg = <6>;
					label = "eth_cu_1000_6";
				};
			};
		};
	};
};

&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	io-expander@22 {
		compatible = "nxp,pca9554";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	eeprom@50 {
		compatible = "atmel,24c04";
		reg = <0x50>;
		label = "nameplate";
	};

	eeprom@52 {
		compatible = "atmel,24c04";
		reg = <0x52>;
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	watchdog@38 {
		compatible = "zii,rave-wdt";
		reg = <0x38>;
	};
};

&snvsrtc {
	status = "disabled";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";

	rave-sp {
		compatible = "zii,rave-sp-rdu2";
		current-speed = <1000000>;
		#address-cells = <1>;
		#size-cells = <1>;

		watchdog {
			compatible = "zii,rave-sp-watchdog";
		};

		eeprom@a3 {
			compatible = "zii,rave-sp-eeprom";
			reg = <0xa3 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			zii,eeprom-name = "main-eeprom";
		};
	};
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&wdoga5 {
       status = "disabled";
};

&iomuxc {
	pinctrl_dspi1: dspi1grp {
		fsl,pins = <
			VF610_PAD_PTD5__DSPI1_CS0		0x1182
			VF610_PAD_PTD4__DSPI1_CS1		0x1182
			VF610_PAD_PTC6__DSPI1_SIN		0x1181
			VF610_PAD_PTC7__DSPI1_SOUT		0x1182
			VF610_PAD_PTC8__DSPI1_SCK		0x1182
		>;
	};

	pinctrl_esdhc0: esdhc0grp {
		fsl,pins = <
			VF610_PAD_PTC0__ESDHC0_CLK		0x31ef
			VF610_PAD_PTC1__ESDHC0_CMD		0x31ef
			VF610_PAD_PTC2__ESDHC0_DAT0		0x31ef
			VF610_PAD_PTC3__ESDHC0_DAT1		0x31ef
			VF610_PAD_PTC4__ESDHC0_DAT2		0x31ef
			VF610_PAD_PTC5__ESDHC0_DAT3		0x31ef
			VF610_PAD_PTD23__ESDHC0_DAT4		0x31ef
			VF610_PAD_PTD22__ESDHC0_DAT5		0x31ef
			VF610_PAD_PTD21__ESDHC0_DAT6		0x31ef
			VF610_PAD_PTD20__ESDHC0_DAT7		0x31ef
		>;
	};

	pinctrl_esdhc1: esdhc1grp {
		fsl,pins = <
			VF610_PAD_PTA24__ESDHC1_CLK		0x31ef
			VF610_PAD_PTA25__ESDHC1_CMD		0x31ef
			VF610_PAD_PTA26__ESDHC1_DAT0		0x31ef
			VF610_PAD_PTA27__ESDHC1_DAT1		0x31ef
			VF610_PAD_PTA28__ESDHC1_DATA2		0x31ef
			VF610_PAD_PTA29__ESDHC1_DAT3		0x31ef
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			VF610_PAD_PTA6__RMII_CLKIN		0x30d1
			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
			VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
		>;
	};

	pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
		fsl,pins = <
			VF610_PAD_PTB28__GPIO_98		0x219d
		>;
	};

	pinctrl_i2c0: i2c0grp {
		fsl,pins = <
			VF610_PAD_PTB14__I2C0_SCL		0x37ff
			VF610_PAD_PTB15__I2C0_SDA		0x37ff
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			VF610_PAD_PTB16__I2C1_SCL		0x37ff
			VF610_PAD_PTB17__I2C1_SDA		0x37ff
		>;
	};

	pinctrl_leds_debug: pinctrl-leds-debug {
		fsl,pins = <
			VF610_PAD_PTD3__GPIO_82			0x31c2
		>;
	};

	pinctrl_uart0: uart0grp {
		fsl,pins = <
			VF610_PAD_PTB10__UART0_TX		0x21a2
			VF610_PAD_PTB11__UART0_RX		0x21a1
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			VF610_PAD_PTB23__UART1_TX		0x21a2
			VF610_PAD_PTB24__UART1_RX		0x21a1
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			VF610_PAD_PTD0__UART2_TX		0x21a2
			VF610_PAD_PTD1__UART2_RX		0x21a1
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			VF610_PAD_PTA30__UART3_TX		0x21a2
			VF610_PAD_PTA31__UART3_RX		0x21a1
		>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/*
 * Device tree file for ZII's SSMB DTU board
 *
 * SSMB - SPU3 Switch Management Board
 * DTU - Digital Tapping Unit
 *
 * Copyright (C) 2015-2019 Zodiac Inflight Innovations
 *
 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
 * Freescale Semiconductor, Inc.
 */

/dts-v1/;
#include "vf610.dtsi"

/ {
	model = "ZII VF610 SSMB DTU Board";
	compatible = "zii,vf610dtu", "zii,vf610dev", "fsl,vf610";

	chosen {
		stdout-path = &uart0;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pinctrl_leds_debug>;
		pinctrl-names = "default";

		led-debug {
			label = "zii:green:debug1";
			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	reg_vcc_3v3_mcu: regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3_mcu";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	supply-voltage-monitor {
		compatible = "iio-hwmon";
		io-channels = <&adc0 8>, /* 12V_MAIN */
			      <&adc0 9>, /* +3.3V    */
			      <&adc1 8>, /* VCC_1V5  */
			      <&adc1 9>; /* VCC_1V2  */
	};
};

&adc0 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
};

&adc1 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
};

&edma0 {
	status = "okay";
};

&edma1 {
	status = "okay";
};

&esdhc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc0>;
	bus-width = <8>;
	non-removable;
	no-1-8-v;
	keep-power-in-suspend;
	no-sdio;
	no-sd;
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	no-sdio;
	status = "okay";
};

&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";

	fixed-link {
		speed = <100>;
		full-duplex;
	};

	mdio1: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <12500000>;
		suppress-preamble;
		status = "okay";

		switch0: switch0@0 {
			compatible = "marvell,mv88e6190";
			pinctrl-0 = <&pinctrl_gpio_switch0>;
			pinctrl-names = "default";
			reg = <0>;
			eeprom-length = <65536>;
			interrupt-parent = <&gpio3>;
			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
			interrupt-controller;
			#interrupt-cells = <2>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "cpu";
					ethernet = <&fec1>;

					fixed-link {
						speed = <100>;
						full-duplex;
					};
				};

				port@1 {
					reg = <1>;
					label = "eth_cu_100_3";
				};

				port@5 {
					reg = <5>;
					label = "eth_cu_1000_4";
				};

				port@6 {
					reg = <6>;
					label = "eth_cu_1000_5";
				};

				port@8 {
					reg = <8>;
					label = "eth_cu_1000_1";
				};

				port@9 {
					reg = <9>;
					label = "eth_cu_1000_2";
					phy-handle = <&phy9>;
					phy-mode = "sgmii";
					managed = "in-band-status";
				};
			};

			mdio1 {
				compatible = "marvell,mv88e6xxx-mdio-external";
				#address-cells = <1>;
				#size-cells = <0>;

				phy9: phy9@0 {
					compatible = "ethernet-phy-ieee802.3-c45";
					pinctrl-0 = <&pinctrl_gpio_phy9>;
					pinctrl-names = "default";
					interrupt-parent = <&gpio2>;
					interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
					reg = <0>;
				};
			};
		};
	};
};

&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	gpio6: gpio-expander@22 {
		compatible = "nxp,pca9554";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	/* On SSMB */
	temperature-sensor@48 {
		compatible = "national,lm75";
		reg = <0x48>;
	};

	/* On DSB */
	temperature-sensor@4d {
		compatible = "national,lm75";
		reg = <0x4d>;
	};

	eeprom@50 {
		compatible = "atmel,24c04";
		reg = <0x50>;
		label = "nameplate";
	};

	eeprom@52 {
		compatible = "atmel,24c04";
		reg = <0x52>;
	};
};

&snvsrtc {
	status = "disabled";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	status = "okay";
};

&iomuxc {
	pinctrl_dspi1: dspi1grp {
		fsl,pins = <
			VF610_PAD_PTD5__DSPI1_CS0		0x1182
			VF610_PAD_PTD4__DSPI1_CS1		0x1182
			VF610_PAD_PTC6__DSPI1_SIN		0x1181
			VF610_PAD_PTC7__DSPI1_SOUT		0x1182
			VF610_PAD_PTC8__DSPI1_SCK		0x1182
		>;
	};

	pinctrl_esdhc0: esdhc0grp {
		fsl,pins = <
			VF610_PAD_PTC0__ESDHC0_CLK		0x31ef
			VF610_PAD_PTC1__ESDHC0_CMD		0x31ef
			VF610_PAD_PTC2__ESDHC0_DAT0		0x31ef
			VF610_PAD_PTC3__ESDHC0_DAT1		0x31ef
			VF610_PAD_PTC4__ESDHC0_DAT2		0x31ef
			VF610_PAD_PTC5__ESDHC0_DAT3		0x31ef
			VF610_PAD_PTD23__ESDHC0_DAT4		0x31ef
			VF610_PAD_PTD22__ESDHC0_DAT5		0x31ef
			VF610_PAD_PTD21__ESDHC0_DAT6		0x31ef
			VF610_PAD_PTD20__ESDHC0_DAT7		0x31ef
		>;
	};

	pinctrl_esdhc1: esdhc1grp {
		fsl,pins = <
			VF610_PAD_PTA24__ESDHC1_CLK		0x31ef
			VF610_PAD_PTA25__ESDHC1_CMD		0x31ef
			VF610_PAD_PTA26__ESDHC1_DAT0		0x31ef
			VF610_PAD_PTA27__ESDHC1_DAT1		0x31ef
			VF610_PAD_PTA28__ESDHC1_DATA2		0x31ef
			VF610_PAD_PTA29__ESDHC1_DAT3		0x31ef
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			VF610_PAD_PTA6__RMII_CLKIN		0x30d1
			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
			VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
		>;
	};

	pinctrl_gpio_phy9: pinctrl-gpio-phy9 {
		fsl,pins = <
			VF610_PAD_PTB24__GPIO_94		0x219d
		>;
	};

	pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
		fsl,pins = <
			VF610_PAD_PTB28__GPIO_98		0x219d
		>;
	};

	pinctrl_i2c0: i2c0grp {
		fsl,pins = <
			VF610_PAD_PTB14__I2C0_SCL		0x37ff
			VF610_PAD_PTB15__I2C0_SDA		0x37ff
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			VF610_PAD_PTB16__I2C1_SCL		0x37ff
			VF610_PAD_PTB17__I2C1_SDA		0x37ff
		>;
	};

	pinctrl_leds_debug: pinctrl-leds-debug {
		fsl,pins = <
			VF610_PAD_PTD3__GPIO_82			0x31c2
		>;
	};

	pinctrl_uart0: uart0grp {
		fsl,pins = <
			VF610_PAD_PTB10__UART0_TX		0x21a2
			VF610_PAD_PTB11__UART0_RX		0x21a1
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/*
 * Device tree file for ZII's SSMB SPU3 board
 *
 * SSMB - SPU3 Switch Management Board
 * SPU - Seat Power Unit
 *
 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
 *
 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
 * Freescale Semiconductor, Inc.
 */

/dts-v1/;
#include "vf610.dtsi"

/ {
	model = "ZII VF610 SSMB SPU3 Board";
	compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610";

	chosen {
		stdout-path = &uart0;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pinctrl_leds_debug>;
		pinctrl-names = "default";

		led-debug {
			label = "zii:green:debug1";
			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	reg_vcc_3v3_mcu: regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3_mcu";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	supply-voltage-monitor {
		compatible = "iio-hwmon";
		io-channels = <&adc0 8>, /* 12V_MAIN */
			      <&adc0 9>, /* +3.3V    */
			      <&adc1 8>, /* VCC_1V5  */
			      <&adc1 9>; /* VCC_1V2  */
	};
};

&adc0 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
};

&adc1 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
};

&dspi1 {
	bus-num = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi1>;
	/*
	 * Some SPU3s come with SPI-NOR chip DNPed, so we leave this
	 * node disabled by default and rely on bootloader to enable
	 * it when appropriate.
	 */
	status = "disabled";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p128", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <50000000>;

		partition@0 {
			label = "m25p128-0";
			reg = <0x0 0x01000000>;
		};
	};
};

&edma0 {
	status = "okay";
};

&edma1 {
	status = "okay";
};

&esdhc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc0>;
	bus-width = <8>;
	non-removable;
	no-1-8-v;
	keep-power-in-suspend;
	no-sdio;
	no-sd;
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	no-sdio;
	status = "okay";
};

&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";

	fixed-link {
		speed = <100>;
		full-duplex;
	};

	mdio1: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <12500000>;
		suppress-preamble;
		status = "okay";

		switch0: switch0@0 {
			compatible = "marvell,mv88e6190";
			pinctrl-0 = <&pinctrl_gpio_switch0>;
			pinctrl-names = "default";
			reg = <0>;
			eeprom-length = <65536>;
			interrupt-parent = <&gpio3>;
			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
			interrupt-controller;
			#interrupt-cells = <2>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "cpu";
					ethernet = <&fec1>;

					fixed-link {
						speed = <100>;
						full-duplex;
					};
				};

				port@1 {
					reg = <1>;
					label = "eth_cu_1000_1";
				};

				port@2 {
					reg = <2>;
					label = "eth_cu_1000_2";
				};

				port@3 {
					reg = <3>;
					label = "eth_cu_1000_3";
				};

				port@4 {
					reg = <4>;
					label = "eth_cu_1000_4";
				};

				port@5 {
					reg = <5>;
					label = "eth_cu_1000_5";
				};

				port@6 {
					reg = <6>;
					label = "eth_cu_1000_6";
				};
			};
		};
	};
};

&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	gpio6: io-expander@22 {
		compatible = "nxp,pca9554";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	lm75@48 {
		compatible = "national,lm75";
		reg = <0x48>;
	};

	eeprom@50 {
		compatible = "atmel,24c04";
		reg = <0x50>;
		label = "nameplate";
	};

	eeprom@52 {
		compatible = "atmel,24c04";
		reg = <0x52>;
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	watchdog@38 {
		compatible = "zii,rave-wdt";
		reg = <0x38>;
	};
};

&snvsrtc {
	status = "disabled";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";

	rave-sp {
		compatible = "zii,rave-sp-rdu2";
		current-speed = <1000000>;
		#address-cells = <1>;
		#size-cells = <1>;

		watchdog {
			compatible = "zii,rave-sp-watchdog";
		};

		eeprom@a3 {
			compatible = "zii,rave-sp-eeprom";
			reg = <0xa3 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			zii,eeprom-name = "main-eeprom";
		};
	};
};

&wdoga5 {
	status = "disabled";
};

&iomuxc {
	pinctrl_dspi1: dspi1grp {
		fsl,pins = <
			VF610_PAD_PTD5__DSPI1_CS0		0x1182
			VF610_PAD_PTD4__DSPI1_CS1		0x1182
			VF610_PAD_PTC6__DSPI1_SIN		0x1181
			VF610_PAD_PTC7__DSPI1_SOUT		0x1182
			VF610_PAD_PTC8__DSPI1_SCK		0x1182
		>;
	};

	pinctrl_esdhc0: esdhc0grp {
		fsl,pins = <
			VF610_PAD_PTC0__ESDHC0_CLK		0x31ef
			VF610_PAD_PTC1__ESDHC0_CMD		0x31ef
			VF610_PAD_PTC2__ESDHC0_DAT0		0x31ef
			VF610_PAD_PTC3__ESDHC0_DAT1		0x31ef
			VF610_PAD_PTC4__ESDHC0_DAT2		0x31ef
			VF610_PAD_PTC5__ESDHC0_DAT3		0x31ef
			VF610_PAD_PTD23__ESDHC0_DAT4		0x31ef
			VF610_PAD_PTD22__ESDHC0_DAT5		0x31ef
			VF610_PAD_PTD21__ESDHC0_DAT6		0x31ef
			VF610_PAD_PTD20__ESDHC0_DAT7		0x31ef
		>;
	};

	pinctrl_esdhc1: esdhc1grp {
		fsl,pins = <
			VF610_PAD_PTA24__ESDHC1_CLK		0x31ef
			VF610_PAD_PTA25__ESDHC1_CMD		0x31ef
			VF610_PAD_PTA26__ESDHC1_DAT0		0x31ef
			VF610_PAD_PTA27__ESDHC1_DAT1		0x31ef
			VF610_PAD_PTA28__ESDHC1_DATA2		0x31ef
			VF610_PAD_PTA29__ESDHC1_DAT3		0x31ef
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			VF610_PAD_PTA6__RMII_CLKIN		0x30d1
			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
			VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
		>;
	};

	pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
		fsl,pins = <
			VF610_PAD_PTB28__GPIO_98		0x219d
		>;
	};

	pinctrl_i2c0: i2c0grp {
		fsl,pins = <
			VF610_PAD_PTB14__I2C0_SCL		0x37ff
			VF610_PAD_PTB15__I2C0_SDA		0x37ff
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			VF610_PAD_PTB16__I2C1_SCL		0x37ff
			VF610_PAD_PTB17__I2C1_SDA		0x37ff
		>;
	};

	pinctrl_leds_debug: pinctrl-leds-debug {
		fsl,pins = <
			VF610_PAD_PTD3__GPIO_82			0x31c2
		>;
	};

	pinctrl_uart0: uart0grp {
		fsl,pins = <
			VF610_PAD_PTB10__UART0_TX		0x21a2
			VF610_PAD_PTB11__UART0_RX		0x21a1
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			VF610_PAD_PTB23__UART1_TX		0x21a2
			VF610_PAD_PTB24__UART1_RX		0x21a1
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2013 Freescale Semiconductor, Inc.

#include "vf500.dtsi"

&a5_cpu {
	next-level-cache = <&L2>;
};

&aips0 {
	L2: cache-controller@40006000 {
		compatible = "arm,pl310-cache";
		reg = <0x40006000 0x1000>;
		cache-unified;
		cache-level = <2>;
		arm,data-latency = <3 3 3>;
		arm,tag-latency = <2 2 2>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Device tree for Colibri VF61 Cortex-M4 support
 *
 * Copyright (C) 2015 Stefan Agner
 */

/dts-v1/;
#include "vf610m4.dtsi"

/ {
	model = "VF610 Cortex-M4";
	compatible = "fsl,vf610m4";

	chosen {
		bootargs = "clk_ignore_unused init=/linuxrc rw";
		stdout-path = "serial2:115200";
	};

	memory@8c000000 {
		device_type = "memory";
		reg = <0x8c000000 0x3000000>;
	};
};

&gpio0 {
	status = "disabled";
};

&gpio1 {
	status = "disabled";
};

&gpio2 {
	status = "disabled";
};

&gpio3 {
	status = "disabled";
};

&gpio4 {
	status = "disabled";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&iomuxc {
	vf610-colibri {
		pinctrl_uart2: uart2grp {
			fsl,pins = <
				VF610_PAD_PTD0__UART2_TX		0x21a2
				VF610_PAD_PTD1__UART2_RX		0x21a1
				VF610_PAD_PTD2__UART2_RTS		0x21a2
				VF610_PAD_PTD3__UART2_CTS		0x21a1
			>;
		};
	};
};


code:
/*
 * Device tree for Cosmic+ VF6xx Cortex-M4 support
 *
 * Copyright (C) 2015
 *
 * Based on vf610m4 Colibri
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "vf610m4.dtsi"

/ {
	model = "VF610 Cortex-M4";
	compatible = "fsl,vf610m4";
};

&gpio0 {
	status = "disabled";
};

&gpio1 {
	status = "disabled";
};

&gpio2 {
	status = "disabled";
};

&gpio3 {
	status = "disabled";
};

&gpio4 {
	status = "disabled";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&iomuxc {
	vf610-cosmic {
		pinctrl_uart3: uart3grp {
			fsl,pins = <
				VF610_PAD_PTA20__UART3_TX		0x21a2
				VF610_PAD_PTA21__UART3_RX		0x21a1
			>;
		};
	};
};


code:
/*
 * Device tree for VF6xx Cortex-M4 support
 *
 * Copyright (C) 2015 Stefan Agner
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "armv7-m.dtsi"
#include "vfxxx.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };
	aliases { };
};

&mscm_ir {
	interrupt-parent = <&nvic>;
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2013 Freescale Semiconductor, Inc.

#include "vf610-pinfunc.h"
#include <dt-bindings/clock/vf610-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	aliases {
		can0 = &can0;
		can1 = &can1;
		ethernet0 = &fec0;
		ethernet1 = &fec1;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		gpio4 = &gpio4;
		usbphy0 = &usbphy0;
		usbphy1 = &usbphy1;
	};

	fxosc: fxosc {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
	};

	sxosc: sxosc {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
	};

	reboot: syscon-reboot {
		compatible = "syscon-reboot";
		regmap = <&src>;
		offset = <0x0>;
		mask = <0x1000>;
	};

	tempsensor: iio-hwmon {
		compatible = "iio-hwmon";
		io-channels = <&adc0 16>, <&adc1 16>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&mscm_ir>;
		ranges;

		aips0: bus@40000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40000000 0x00070000>;
			ranges;

			mscm_cpucfg: cpucfg@40001000 {
				compatible = "fsl,vf610-mscm-cpucfg", "syscon";
				reg = <0x40001000 0x800>;
			};

			mscm_ir: interrupt-controller@40001800 {
				compatible = "fsl,vf610-mscm-ir";
				reg = <0x40001800 0x400>;
				fsl,cpucfg = <&mscm_cpucfg>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			edma0: dma-controller@40018000 {
				#dma-cells = <2>;
				compatible = "fsl,vf610-edma";
				reg = <0x40018000 0x2000>,
					<0x40024000 0x1000>,
					<0x40025000 0x1000>;
				dma-channels = <32>;
				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
						<9 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "edma-tx", "edma-err";
				clock-names = "dmamux0", "dmamux1";
				clocks = <&clks VF610_CLK_DMAMUX0>,
					<&clks VF610_CLK_DMAMUX1>;
				status = "disabled";
			};

			can0: can@40020000 {
				compatible = "fsl,vf610-flexcan";
				reg = <0x40020000 0x4000>;
				interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_FLEXCAN0>,
					 <&clks VF610_CLK_FLEXCAN0>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart0: serial@40027000 {
				compatible = "fsl,vf610-lpuart";
				reg = <0x40027000 0x1000>;
				interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_UART0>;
				clock-names = "ipg";
				dmas = <&edma0 0 2>,
					<&edma0 0 3>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			uart1: serial@40028000 {
				compatible = "fsl,vf610-lpuart";
				reg = <0x40028000 0x1000>;
				interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_UART1>;
				clock-names = "ipg";
				dmas = <&edma0 0 4>,
					<&edma0 0 5>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			uart2: serial@40029000 {
				compatible = "fsl,vf610-lpuart";
				reg = <0x40029000 0x1000>;
				interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_UART2>;
				clock-names = "ipg";
				dmas = <&edma0 0 6>,
					<&edma0 0 7>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			uart3: serial@4002a000 {
				compatible = "fsl,vf610-lpuart";
				reg = <0x4002a000 0x1000>;
				interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_UART3>;
				clock-names = "ipg";
				dmas = <&edma0 0 8>,
					<&edma0 0 9>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			dspi0: spi@4002c000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-dspi";
				reg = <0x4002c000 0x1000>;
				interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_DSPI0>;
				clock-names = "dspi";
				spi-num-chipselects = <6>;
				dmas = <&edma1 1 12>,
					<&edma1 1 13>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			dspi1: spi@4002d000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-dspi";
				reg = <0x4002d000 0x1000>;
				interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_DSPI1>;
				clock-names = "dspi";
				spi-num-chipselects = <4>;
				dmas = <&edma1 1 14>,
					<&edma1 1 15>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			sai0: sai@4002f000 {
				compatible = "fsl,vf610-sai";
				reg = <0x4002f000 0x1000>;
				interrupts = <84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_SAI0>,
					<&clks VF610_CLK_SAI0_DIV>,
					<&clks 0>, <&clks 0>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dma-names = "tx", "rx";
				dmas = <&edma0 0 17>,
					<&edma0 0 16>;
				status = "disabled";
			};

			sai1: sai@40030000 {
				compatible = "fsl,vf610-sai";
				reg = <0x40030000 0x1000>;
				interrupts = <85 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_SAI1>,
					<&clks VF610_CLK_SAI1_DIV>,
					<&clks 0>, <&clks 0>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dma-names = "tx", "rx";
				dmas = <&edma0 0 19>,
					<&edma0 0 18>;
				status = "disabled";
			};

			sai2: sai@40031000 {
				compatible = "fsl,vf610-sai";
				reg = <0x40031000 0x1000>;
				interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_SAI2>,
					<&clks VF610_CLK_SAI2_DIV>,
					<&clks 0>, <&clks 0>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dma-names = "tx", "rx";
				dmas = <&edma0 0 21>,
					<&edma0 0 20>;
				status = "disabled";
			};

			sai3: sai@40032000 {
				compatible = "fsl,vf610-sai";
				reg = <0x40032000 0x1000>;
				interrupts = <87 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_SAI3>,
					<&clks VF610_CLK_SAI3_DIV>,
					<&clks 0>, <&clks 0>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dma-names = "tx", "rx";
				dmas = <&edma0 1 9>,
					<&edma0 1 8>;
				status = "disabled";
			};

			pit: pit@40037000 {
				compatible = "fsl,vf610-pit";
				reg = <0x40037000 0x1000>;
				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_PIT>;
				clock-names = "pit";
			};

			pwm0: pwm@40038000 {
				compatible = "fsl,vf610-ftm-pwm";
				#pwm-cells = <3>;
				reg = <0x40038000 0x1000>;
				clock-names = "ftm_sys", "ftm_ext",
					      "ftm_fix", "ftm_cnt_clk_en";
				clocks = <&clks VF610_CLK_FTM0>,
					<&clks VF610_CLK_FTM0_EXT_SEL>,
					<&clks VF610_CLK_FTM0_FIX_SEL>,
					<&clks VF610_CLK_FTM0_EXT_FIX_EN>;
				status = "disabled";
			};

			pwm1: pwm@40039000 {
				compatible = "fsl,vf610-ftm-pwm";
				#pwm-cells = <3>;
				reg = <0x40039000 0x1000>;
				clock-names = "ftm_sys", "ftm_ext",
					      "ftm_fix", "ftm_cnt_clk_en";
				clocks = <&clks VF610_CLK_FTM1>,
					<&clks VF610_CLK_FTM1_EXT_SEL>,
					<&clks VF610_CLK_FTM1_FIX_SEL>,
					<&clks VF610_CLK_FTM1_EXT_FIX_EN>;
				status = "disabled";
			};

			adc0: adc@4003b000 {
				compatible = "fsl,vf610-adc";
				reg = <0x4003b000 0x1000>;
				interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_ADC0>;
				clock-names = "adc";
				#io-channel-cells = <1>;
				status = "disabled";
				fsl,adck-max-frequency = <30000000>, <40000000>,
							<20000000>;
			};

			tcon0: timing-controller@4003d000 {
				compatible = "fsl,vf610-tcon";
				reg = <0x4003d000 0x1000>;
				clocks = <&clks VF610_CLK_TCON0>;
				clock-names = "ipg";
				status = "disabled";
			};

			wdoga5: watchdog@4003e000 {
				compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
				reg = <0x4003e000 0x1000>;
				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_WDT>;
				clock-names = "wdog";
				status = "disabled";
			};

			qspi0: spi@40044000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-qspi";
				reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_QSPI0_EN>,
					<&clks VF610_CLK_QSPI0>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			iomuxc: iomuxc@40048000 {
				compatible = "fsl,vf610-iomuxc";
				reg = <0x40048000 0x1000>;
			};

			gpio0: gpio@40049000 {
				compatible = "fsl,vf610-gpio";
				reg = <0x40049000 0x1000 0x400ff000 0x40>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 0 32>;
			};

			gpio1: gpio@4004a000 {
				compatible = "fsl,vf610-gpio";
				reg = <0x4004a000 0x1000 0x400ff040 0x40>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 32 32>;
			};

			gpio2: gpio@4004b000 {
				compatible = "fsl,vf610-gpio";
				reg = <0x4004b000 0x1000 0x400ff080 0x40>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 64 32>;
			};

			gpio3: gpio@4004c000 {
				compatible = "fsl,vf610-gpio";
				reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 96 32>;
			};

			gpio4: gpio@4004d000 {
				compatible = "fsl,vf610-gpio";
				reg = <0x4004d000 0x1000 0x400ff100 0x40>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 128 7>;
			};

			anatop: anatop@40050000 {
				compatible = "fsl,vf610-anatop", "syscon";
				reg = <0x40050000 0x400>;
			};

			usbphy0: usbphy@40050800 {
				compatible = "fsl,vf610-usbphy";
				reg = <0x40050800 0x400>;
				interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_USBPHY0>;
				fsl,anatop = <&anatop>;
				status = "disabled";
			};

			usbphy1: usbphy@40050c00 {
				compatible = "fsl,vf610-usbphy";
				reg = <0x40050c00 0x400>;
				interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_USBPHY1>;
				fsl,anatop = <&anatop>;
				status = "disabled";
			};

			dcu0: dcu@40058000 {
				compatible = "fsl,vf610-dcu";
				reg = <0x40058000 0x1200>;
				interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_DCU0>,
					<&clks VF610_CLK_DCU0_DIV>;
				clock-names = "dcu", "pix";
				fsl,tcon = <&tcon0>;
				status = "disabled";
			};

			i2c0: i2c@40066000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-i2c";
				reg = <0x40066000 0x1000>;
				interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_I2C0>;
				clock-names = "ipg";
				dmas = <&edma0 0 50>,
					<&edma0 0 51>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			i2c1: i2c@40067000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-i2c";
				reg = <0x40067000 0x1000>;
				interrupts = <72 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_I2C1>;
				clock-names = "ipg";
				dmas = <&edma0 0 52>,
					<&edma0 0 53>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			clks: ccm@4006b000 {
				compatible = "fsl,vf610-ccm";
				reg = <0x4006b000 0x1000>;
				clocks = <&sxosc>, <&fxosc>;
				clock-names = "sxosc", "fxosc";
				#clock-cells = <1>;
			};

			usbdev0: usb@40034000 {
				compatible = "fsl,vf610-usb", "fsl,imx27-usb";
				reg = <0x40034000 0x800>;
				interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_USBC0>;
				fsl,usbphy = <&usbphy0>;
				fsl,usbmisc = <&usbmisc0 0>;
				dr_mode = "peripheral";
				status = "disabled";
			};

			usbmisc0: usb@40034800 {
				#index-cells = <1>;
				compatible = "fsl,vf610-usbmisc";
				reg = <0x40034800 0x200>;
				clocks = <&clks VF610_CLK_USBC0>;
				status = "disabled";
			};

			src: src@4006e000 {
				compatible = "fsl,vf610-src", "syscon";
				reg = <0x4006e000 0x1000>;
				interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		aips1: bus@40080000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40080000 0x0007f000>;
			ranges;

			edma1: dma-controller@40098000 {
				#dma-cells = <2>;
				compatible = "fsl,vf610-edma";
				reg = <0x40098000 0x2000>,
					<0x400a1000 0x1000>,
					<0x400a2000 0x1000>;
				dma-channels = <32>;
				interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
						<11 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "edma-tx", "edma-err";
				clock-names = "dmamux0", "dmamux1";
				clocks = <&clks VF610_CLK_DMAMUX2>,
					<&clks VF610_CLK_DMAMUX3>;
				status = "disabled";
			};

			ocotp: ocotp@400a5000 {
				compatible = "fsl,vf610-ocotp", "syscon";
				reg = <0x400a5000 0x1000>;
				clocks = <&clks VF610_CLK_OCOTP>;
			};

			snvs0: snvs@400a7000 {
			    compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
				reg = <0x400a7000 0x2000>;

				snvsrtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap = <&snvs0>;
					offset = <0x34>;
					interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks VF610_CLK_SNVS>;
					clock-names = "snvs-rtc";
				};
			};

			uart4: serial@400a9000 {
				compatible = "fsl,vf610-lpuart";
				reg = <0x400a9000 0x1000>;
				interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_UART4>;
				clock-names = "ipg";
				status = "disabled";
			};

			uart5: serial@400aa000 {
				compatible = "fsl,vf610-lpuart";
				reg = <0x400aa000 0x1000>;
				interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_UART5>;
				clock-names = "ipg";
				status = "disabled";
			};

			dspi2: spi@400ac000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-dspi";
				reg = <0x400ac000 0x1000>;
				interrupts = <69 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_DSPI2>;
				clock-names = "dspi";
				spi-num-chipselects = <2>;
				dmas = <&edma1 0 10>,
					<&edma1 0 11>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			dspi3: spi@400ad000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-dspi";
				reg = <0x400ad000 0x1000>;
				interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_DSPI3>;
				clock-names = "dspi";
				spi-num-chipselects = <2>;
				dmas = <&edma1 0 12>,
					<&edma1 0 13>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			adc1: adc@400bb000 {
				compatible = "fsl,vf610-adc";
				reg = <0x400bb000 0x1000>;
				interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_ADC1>;
				clock-names = "adc";
				#io-channel-cells = <1>;
				status = "disabled";
				fsl,adck-max-frequency = <30000000>, <40000000>,
							<20000000>;
			};

			esdhc0: esdhc@400b1000 {
				compatible = "fsl,imx53-esdhc";
				reg = <0x400b1000 0x1000>;
				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_IPG_BUS>,
					<&clks VF610_CLK_PLATFORM_BUS>,
					<&clks VF610_CLK_ESDHC0>;
				clock-names = "ipg", "ahb", "per";
				status = "disabled";
			};

			esdhc1: esdhc@400b2000 {
				compatible = "fsl,imx53-esdhc";
				reg = <0x400b2000 0x1000>;
				interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_IPG_BUS>,
					<&clks VF610_CLK_PLATFORM_BUS>,
					<&clks VF610_CLK_ESDHC1>;
				clock-names = "ipg", "ahb", "per";
				status = "disabled";
			};

			usbh1: usb@400b4000 {
				compatible = "fsl,vf610-usb", "fsl,imx27-usb";
				reg = <0x400b4000 0x800>;
				interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_USBC1>;
				fsl,usbphy = <&usbphy1>;
				fsl,usbmisc = <&usbmisc1 0>;
				dr_mode = "host";
				status = "disabled";
			};

			usbmisc1: usb@400b4800 {
				#index-cells = <1>;
				compatible = "fsl,vf610-usbmisc";
				reg = <0x400b4800 0x200>;
				clocks = <&clks VF610_CLK_USBC1>;
				status = "disabled";
			};

			ftm: ftm@400b8000 {
				compatible = "fsl,ftm-timer";
				reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
				interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
				clock-names = "ftm-evt", "ftm-src",
					"ftm-evt-counter-en", "ftm-src-counter-en";
				clocks = <&clks VF610_CLK_FTM2>,
					<&clks VF610_CLK_FTM3>,
					<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
					<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
				status = "disabled";
			};

			qspi1: spi@400c4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-qspi";
				reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_QSPI1_EN>,
					<&clks VF610_CLK_QSPI1>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			dac0: dac@400cc000 {
				compatible = "fsl,vf610-dac";
				reg = <0x400cc000 1000>;
				interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
				clock-names = "dac";
				clocks = <&clks VF610_CLK_DAC0>;
				status = "disabled";
			};

			dac1: dac@400cd000 {
				compatible = "fsl,vf610-dac";
				reg = <0x400cd000 1000>;
				interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
				clock-names = "dac";
				clocks = <&clks VF610_CLK_DAC1>;
				status = "disabled";
			};

			fec0: ethernet@400d0000 {
				compatible = "fsl,mvf600-fec";
				reg = <0x400d0000 0x1000>;
				interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_ENET0>,
					<&clks VF610_CLK_ENET0>,
					<&clks VF610_CLK_ENET>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};

			fec1: ethernet@400d1000 {
				compatible = "fsl,mvf600-fec";
				reg = <0x400d1000 0x1000>;
				interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_ENET1>,
					<&clks VF610_CLK_ENET1>,
					<&clks VF610_CLK_ENET>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};

			can1: can@400d4000 {
				compatible = "fsl,vf610-flexcan";
				reg = <0x400d4000 0x4000>;
				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_FLEXCAN1>,
					 <&clks VF610_CLK_FLEXCAN1>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			nfc: nand@400e0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-nfc";
				reg = <0x400e0000 0x4000>;
				interrupts = <83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_NFC>;
				clock-names = "nfc";
				status = "disabled";
			};

			i2c2: i2c@400e6000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-i2c";
				reg = <0x400e6000 0x1000>;
				interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_I2C2>;
				clock-names = "ipg";
				dmas = <&edma0 1 36>,
					<&edma0 1 37>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			i2c3: i2c@400e7000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-i2c";
				reg = <0x400e7000 0x1000>;
				interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_I2C3>;
				clock-names = "ipg";
				dmas = <&edma0 1 38>,
					<&edma0 1 39>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			crypto: crypto@400f0000 {
				compatible = "fsl,sec-v4.0";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x400f0000 0x9000>;
				ranges = <0 0x400f0000 0x9000>;
				clocks = <&clks VF610_CLK_CAAM>;
				clock-names = "ipg";

				sec_jr0: jr0@1000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x1000 0x1000>;
					interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr1: jr1@2000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x2000 0x1000>;
					interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook
 *
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 */

/dts-v1/;
/include/ "vt8500.dtsi"

/ {
	model = "Benign BV07 Netbook";
};

&fb {
	bits-per-pixel = <16>;
	display-timings {
		native-mode = <&timing0>;
		timing0: 800x480 {
			clock-frequency = <0>; /* unused but required */
			hactive = <800>;
			vactive = <480>;
			hfront-porch = <40>;
			hback-porch = <88>;
			hsync-len = <0>;
			vback-porch = <32>;
			vfront-porch = <11>;
			vsync-len = <1>;
		};
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * vt8500.dtsi - Device tree file for VIA VT8500 SoC
 *
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "via,vt8500";

	cpus {
		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;
		interrupt-parent = <&intc>;

		intc: interrupt-controller@d8140000 {
			compatible = "via,vt8500-intc";
			interrupt-controller;
			reg = <0xd8140000 0x10000>;
			#interrupt-cells = <1>;
		};

		pinctrl: pinctrl@d8110000 {
			compatible = "via,vt8500-pinctrl";
			reg = <0xd8110000 0x10000>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		pmc@d8130000 {
			compatible = "via,vt8500-pmc";
			reg = <0xd8130000 0x1000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				ref24: ref24M {
					#clock-cells = <0>;
					compatible = "fixed-clock";
					clock-frequency = <24000000>;
				};

				clkuart0: uart0 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x250>;
					enable-bit = <1>;
				};

				clkuart1: uart1 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x250>;
					enable-bit = <2>;
				};

				clkuart2: uart2 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x250>;
					enable-bit = <3>;
				};

				clkuart3: uart3 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x250>;
					enable-bit = <4>;
				};
			};
		};

		timer@d8130100 {
			compatible = "via,vt8500-timer";
			reg = <0xd8130100 0x28>;
			interrupts = <36>;
		};

		ehci@d8007900 {
			compatible = "via,vt8500-ehci";
			reg = <0xd8007900 0x200>;
			interrupts = <43>;
		};

		uhci@d8007b00 {
			compatible = "platform-uhci";
			reg = <0xd8007b00 0x200>;
			interrupts = <43>;
		};

		fb: fb@d8050800 {
			compatible = "via,vt8500-fb";
			reg = <0xd800e400 0x400>;
			interrupts = <12>;
		};

		ge_rops@d8050400 {
			compatible = "wm,prizm-ge-rops";
			reg = <0xd8050400 0x100>;
		};

		uart0: serial@d8200000 {
			compatible = "via,vt8500-uart";
			reg = <0xd8200000 0x1040>;
			interrupts = <32>;
			clocks = <&clkuart0>;
			status = "disabled";
		};

		uart1: serial@d82b0000 {
			compatible = "via,vt8500-uart";
			reg = <0xd82b0000 0x1040>;
			interrupts = <33>;
			clocks = <&clkuart1>;
			status = "disabled";
		};

		uart2: serial@d8210000 {
			compatible = "via,vt8500-uart";
			reg = <0xd8210000 0x1040>;
			interrupts = <47>;
			clocks = <&clkuart2>;
			status = "disabled";
		};

		uart3: serial@d82c0000 {
			compatible = "via,vt8500-uart";
			reg = <0xd82c0000 0x1040>;
			interrupts = <50>;
			clocks = <&clkuart3>;
			status = "disabled";
		};

		rtc@d8100000 {
			compatible = "via,vt8500-rtc";
			reg = <0xd8100000 0x10000>;
			interrupts = <48>;
		};

		ethernet@d8004000 {
			compatible = "via,vt8500-rhine";
			reg = <0xd8004000 0x100>;
			interrupts = <10>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook
 *
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 */

/dts-v1/;
/include/ "wm8505.dtsi"

/ {
	model = "Wondermedia WM8505 Netbook";
};

&fb {
	bits-per-pixel = <32>;
	display-timings {
		native-mode = <&timing0>;
		timing0: 800x480 {
			clock-frequency = <0>; /* unused but required */
			hactive = <800>;
			vactive = <480>;
			hfront-porch = <40>;
			hback-porch = <88>;
			hsync-len = <0>;
			vback-porch = <32>;
			vfront-porch = <11>;
			vsync-len = <1>;
		};
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
 *
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "wm,wm8505";

	cpus {
		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

 	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
 	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;
		interrupt-parent = <&intc0>;

		intc0: interrupt-controller@d8140000 {
			compatible = "via,vt8500-intc";
			interrupt-controller;
			reg = <0xd8140000 0x10000>;
			#interrupt-cells = <1>;
		};

		/* Secondary IC cascaded to intc0 */
		intc1: interrupt-controller@d8150000 {
			compatible = "via,vt8500-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0xD8150000 0x10000>;
			interrupts = <56 57 58 59 60 61 62 63>;
		};

		pinctrl: pinctrl@d8110000 {
			compatible = "wm,wm8505-pinctrl";
			reg = <0xd8110000 0x10000>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		pmc@d8130000 {
			compatible = "via,vt8500-pmc";
			reg = <0xd8130000 0x1000>;
			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				ref24: ref24M {
					#clock-cells = <0>;
					compatible = "fixed-clock";
					clock-frequency = <24000000>;
				};

				ref25: ref25M {
					#clock-cells = <0>;
					compatible = "fixed-clock";
					clock-frequency = <25000000>;
				};

				plla: plla {
					#clock-cells = <0>;
					compatible = "via,vt8500-pll-clock";
					clocks = <&ref25>;
					reg = <0x200>;
				};

				pllb: pllb {
					#clock-cells = <0>;
					compatible = "via,vt8500-pll-clock";
					clocks = <&ref25>;
					reg = <0x204>;
				};

				pllc: pllc {
					#clock-cells = <0>;
					compatible = "via,vt8500-pll-clock";
					clocks = <&ref25>;
					reg = <0x208>;
				};

				plld: plld {
					#clock-cells = <0>;
					compatible = "via,vt8500-pll-clock";
					clocks = <&ref25>;
					reg = <0x20c>;
				};

				clkarm: arm {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&plla>;
					divisor-reg = <0x300>;
				};

				clkahb: ahb {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x304>;
				};

				clkapb: apb {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x350>;
				};

				clkddr: ddr {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&plld>;
					divisor-reg = <0x310>;
				};

				clkuart0: uart0 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x250>;
					enable-bit = <1>;
				};

				clkuart1: uart1 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x250>;
					enable-bit = <2>;
				};

				clkuart2: uart2 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x250>;
					enable-bit = <3>;
				};

				clkuart3: uart3 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x250>;
					enable-bit = <4>;
				};

				clkuart4: uart4 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x250>;
					enable-bit = <22>;
				};

				clkuart5: uart5 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x250>;
					enable-bit = <23>;
				};

				clksdhc: sdhc {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x328>;
					divisor-mask = <0x3f>;
					enable-reg = <0x254>;
					enable-bit = <18>;
				};
			};
		};

		timer@d8130100 {
			compatible = "via,vt8500-timer";
			reg = <0xd8130100 0x28>;
			interrupts = <36>;
		};

		ehci@d8007100 {
			compatible = "via,vt8500-ehci";
			reg = <0xd8007100 0x200>;
			interrupts = <1>;
		};

		uhci@d8007300 {
			compatible = "platform-uhci";
			reg = <0xd8007300 0x200>;
			interrupts = <0>;
		};

		fb: fb@d8050800 {
			compatible = "wm,wm8505-fb";
			reg = <0xd8050800 0x200>;
		};

		ge_rops@d8050400 {
			compatible = "wm,prizm-ge-rops";
			reg = <0xd8050400 0x100>;
		};

		uart0: serial@d8200000 {
			compatible = "via,vt8500-uart";
			reg = <0xd8200000 0x1040>;
			interrupts = <32>;
			clocks = <&clkuart0>;
			status = "disabled";
		};

		uart1: serial@d82b0000 {
			compatible = "via,vt8500-uart";
			reg = <0xd82b0000 0x1040>;
			interrupts = <33>;
			clocks = <&clkuart1>;
			status = "disabled";
		};

		uart2: serial@d8210000 {
			compatible = "via,vt8500-uart";
			reg = <0xd8210000 0x1040>;
			interrupts = <47>;
			clocks = <&clkuart2>;
			status = "disabled";
		};

		uart3: serial@d82c0000 {
			compatible = "via,vt8500-uart";
			reg = <0xd82c0000 0x1040>;
			interrupts = <50>;
			clocks = <&clkuart3>;
			status = "disabled";
		};

		uart4: serial@d8370000 {
			compatible = "via,vt8500-uart";
			reg = <0xd8370000 0x1040>;
			interrupts = <31>;
			clocks = <&clkuart4>;
			status = "disabled";
		};

		uart5: serial@d8380000 {
			compatible = "via,vt8500-uart";
			reg = <0xd8380000 0x1040>;
			interrupts = <30>;
			clocks = <&clkuart5>;
			status = "disabled";
		};

		rtc@d8100000 {
			compatible = "via,vt8500-rtc";
			reg = <0xd8100000 0x10000>;
			interrupts = <48>;
		};

		sdhc@d800a000 {
			compatible = "wm,wm8505-sdhc";
			reg = <0xd800a000 0x400>;
			interrupts = <20>, <21>;
			clocks = <&clksdhc>;
			bus-width = <4>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet
 *
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 */

/dts-v1/;
/include/ "wm8650.dtsi"

/ {
	model = "Wondermedia WM8650-MID Tablet";
};

&fb {
	bits-per-pixel = <16>;

	display-timings {
		native-mode = <&timing0>;
		timing0: 800x480 {
			clock-frequency = <0>; /* unused but required */
			hactive = <800>;
			vactive = <480>;
			hfront-porch = <40>;
			hback-porch = <88>;
			hsync-len = <0>;
			vback-porch = <32>;
			vfront-porch = <11>;
			vsync-len = <1>;
		};
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
 *
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "wm,wm8650";

	cpus {
		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

 	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;
		interrupt-parent = <&intc0>;

		intc0: interrupt-controller@d8140000 {
			compatible = "via,vt8500-intc";
			interrupt-controller;
			reg = <0xd8140000 0x10000>;
			#interrupt-cells = <1>;
		};

		/* Secondary IC cascaded to intc0 */
		intc1: interrupt-controller@d8150000 {
			compatible = "via,vt8500-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0xD8150000 0x10000>;
			interrupts = <56 57 58 59 60 61 62 63>;
		};

		pinctrl: pinctrl@d8110000 {
			compatible = "wm,wm8650-pinctrl";
			reg = <0xd8110000 0x10000>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		pmc@d8130000 {
			compatible = "via,vt8500-pmc";
			reg = <0xd8130000 0x1000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				ref25: ref25M {
					#clock-cells = <0>;
					compatible = "fixed-clock";
					clock-frequency = <25000000>;
				};

				ref24: ref24M {
					#clock-cells = <0>;
					compatible = "fixed-clock";
					clock-frequency = <24000000>;
				};

				plla: plla {
					#clock-cells = <0>;
					compatible = "wm,wm8650-pll-clock";
					clocks = <&ref25>;
					reg = <0x200>;
				};

				pllb: pllb {
					#clock-cells = <0>;
					compatible = "wm,wm8650-pll-clock";
					clocks = <&ref25>;
					reg = <0x204>;
				};

				pllc: pllc {
					#clock-cells = <0>;
					compatible = "wm,wm8650-pll-clock";
					clocks = <&ref25>;
					reg = <0x208>;
				};

				plld: plld {
					#clock-cells = <0>;
					compatible = "wm,wm8650-pll-clock";
					clocks = <&ref25>;
					reg = <0x20c>;
				};

				plle: plle {
					#clock-cells = <0>;
					compatible = "wm,wm8650-pll-clock";
					clocks = <&ref25>;
					reg = <0x210>;
				};

				clkarm: arm {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&plla>;
					divisor-reg = <0x300>;
				};

				clkahb: ahb {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x304>;
				};

				clkapb: apb {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x320>;
				};

				clkddr: ddr {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&plld>;
					divisor-reg = <0x310>;
				};

				clkuart0: uart0 {
 					#clock-cells = <0>;
 					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x250>;
					enable-bit = <1>;
 				};

				clkuart1: uart1 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x250>;
					enable-bit = <2>;
				};

				clksdhc: sdhc {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x328>;
					divisor-mask = <0x3f>;
					enable-reg = <0x254>;
					enable-bit = <18>;
				};
			};
		};

		timer@d8130100 {
			compatible = "via,vt8500-timer";
			reg = <0xd8130100 0x28>;
			interrupts = <36>;
		};

		ehci@d8007900 {
			compatible = "via,vt8500-ehci";
			reg = <0xd8007900 0x200>;
			interrupts = <43>;
		};

		uhci@d8007b00 {
			compatible = "platform-uhci";
			reg = <0xd8007b00 0x200>;
			interrupts = <43>;
		};

		sdhc@d800a000 {
			compatible = "wm,wm8505-sdhc";
			reg = <0xd800a000 0x400>;
			interrupts = <20>, <21>;
			clocks = <&clksdhc>;
			bus-width = <4>;
			sdon-inverted;
		};

		fb: fb@d8050800 {
			compatible = "wm,wm8505-fb";
			reg = <0xd8050800 0x200>;
		};

		ge_rops@d8050400 {
			compatible = "wm,prizm-ge-rops";
			reg = <0xd8050400 0x100>;
		};

		uart0: serial@d8200000 {
			compatible = "via,vt8500-uart";
			reg = <0xd8200000 0x1040>;
			interrupts = <32>;
			clocks = <&clkuart0>;
			status = "disabled";
		};

		uart1: serial@d82b0000 {
			compatible = "via,vt8500-uart";
			reg = <0xd82b0000 0x1040>;
			interrupts = <33>;
			clocks = <&clkuart1>;
			status = "disabled";
		};

		rtc@d8100000 {
			compatible = "via,vt8500-rtc";
			reg = <0xd8100000 0x10000>;
			interrupts = <48>;
		};

		ethernet@d8004000 {
			compatible = "via,vt8500-rhine";
			reg = <0xd8004000 0x100>;
			interrupts = <10>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * wm8750-apc8750.dts
 *  - Device tree file for VIA APC8750
 *
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 */

/dts-v1/;
/include/ "wm8750.dtsi"

/ {
	model = "VIA APC8750";
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c>;

	i2c: i2c {
		wm,pins = <168 169 170 171>;
		wm,function = <2>;	/* alt */
		wm,pull = <2>;	/* pull-up */
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
 *
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "wm,wm8750";

	cpus {
		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			device_type = "cpu";
			compatible = "arm,arm1176jzf";
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;
		interrupt-parent = <&intc0>;

		intc0: interrupt-controller@d8140000 {
			compatible = "via,vt8500-intc";
			interrupt-controller;
			reg = <0xd8140000 0x10000>;
			#interrupt-cells = <1>;
		};

		/* Secondary IC cascaded to intc0 */
		intc1: interrupt-controller@d8150000 {
			compatible = "via,vt8500-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0xD8150000 0x10000>;
			interrupts = <56 57 58 59 60 61 62 63>;
		};

		pinctrl: pinctrl@d8110000 {
			compatible = "wm,wm8750-pinctrl";
			reg = <0xd8110000 0x10000>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		pmc@d8130000 {
			compatible = "via,vt8500-pmc";
			reg = <0xd8130000 0x1000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				ref24: ref24M {
					#clock-cells = <0>;
					compatible = "fixed-clock";
					clock-frequency = <24000000>;
				};

				ref25: ref25M {
					#clock-cells = <0>;
					compatible = "fixed-clock";
					clock-frequency = <25000000>;
				};

				plla: plla {
					#clock-cells = <0>;
					compatible = "wm,wm8750-pll-clock";
					clocks = <&ref25>;
					reg = <0x200>;
				};

				pllb: pllb {
					#clock-cells = <0>;
					compatible = "wm,wm8750-pll-clock";
					clocks = <&ref25>;
					reg = <0x204>;
				};

				pllc: pllc {
					#clock-cells = <0>;
					compatible = "wm,wm8750-pll-clock";
					clocks = <&ref25>;
					reg = <0x208>;
				};

				plld: plld {
					#clock-cells = <0>;
					compatible = "wm,wm8750-pll-clock";
					clocks = <&ref25>;
					reg = <0x20C>;
				};

				plle: plle {
					#clock-cells = <0>;
					compatible = "wm,wm8750-pll-clock";
					clocks = <&ref25>;
					reg = <0x210>;
				};

				clkarm: arm {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&plla>;
					divisor-reg = <0x300>;
				};

				clkahb: ahb {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x304>;
				};

				clkapb: apb {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x320>;
				};

				clkddr: ddr {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&plld>;
					divisor-reg = <0x310>;
				};

				clkuart0: uart0 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x254>;
					enable-bit = <24>;
				};

				clkuart1: uart1 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x254>;
					enable-bit = <25>;
				};

                                clkuart2: uart2 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
                                        clocks = <&ref24>;
                                        enable-reg = <0x254>;
                                        enable-bit = <26>;
                                };

                                clkuart3: uart3 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
                                        clocks = <&ref24>;
                                        enable-reg = <0x254>;
                                        enable-bit = <27>;
                                };

                                clkuart4: uart4 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
                                        clocks = <&ref24>;
                                        enable-reg = <0x254>;
                                        enable-bit = <28>;
                                };

                                clkuart5: uart5 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
                                        clocks = <&ref24>;
                                        enable-reg = <0x254>;
                                        enable-bit = <29>;
                                };

				clkpwm: pwm {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x350>;
					enable-reg = <0x250>;
					enable-bit = <17>;
				};

				clksdhc: sdhc {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x330>;
					divisor-mask = <0x3f>;
					enable-reg = <0x250>;
					enable-bit = <0>;
				};

				clki2c0: i2c0clk {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x3A0>;
					enable-reg = <0x250>;
					enable-bit = <8>;
				};

				clki2c1: i2c1clk {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x3A4>;
					enable-reg = <0x250>;
					enable-bit = <9>;
				};
			};
		};

		pwm: pwm@d8220000 {
			#pwm-cells = <3>;
			compatible = "via,vt8500-pwm";
			reg = <0xd8220000 0x100>;
			clocks = <&clkpwm>;
		};

		timer@d8130100 {
			compatible = "via,vt8500-timer";
			reg = <0xd8130100 0x28>;
			interrupts = <36>;
		};

		ehci@d8007900 {
			compatible = "via,vt8500-ehci";
			reg = <0xd8007900 0x200>;
			interrupts = <26>;
		};

		uhci@d8007b00 {
			compatible = "platform-uhci";
			reg = <0xd8007b00 0x200>;
			interrupts = <26>;
		};

		uhci@d8008d00 {
			compatible = "platform-uhci";
			reg = <0xd8008d00 0x200>;
			interrupts = <26>;
		};

		uart0: serial@d8200000 {
			compatible = "via,vt8500-uart";
			reg = <0xd8200000 0x1040>;
			interrupts = <32>;
			clocks = <&clkuart0>;
			status = "disabled";
		};

		uart1: serial@d82b0000 {
			compatible = "via,vt8500-uart";
			reg = <0xd82b0000 0x1040>;
			interrupts = <33>;
			clocks = <&clkuart1>;
			status = "disabled";
		};

                uart2: serial@d8210000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8210000 0x1040>;
                        interrupts = <47>;
                        clocks = <&clkuart2>;
			status = "disabled";
                };

                uart3: serial@d82c0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82c0000 0x1040>;
                        interrupts = <50>;
                        clocks = <&clkuart3>;
			status = "disabled";
                };

                uart4: serial@d8370000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8370000 0x1040>;
                        interrupts = <30>;
                        clocks = <&clkuart4>;
			status = "disabled";
                };

                uart5: serial@d8380000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8380000 0x1040>;
                        interrupts = <43>;
                        clocks = <&clkuart5>;
			status = "disabled";
                };

		rtc@d8100000 {
			compatible = "via,vt8500-rtc";
			reg = <0xd8100000 0x10000>;
			interrupts = <48>;
		};

		sdhc@d800a000 {
			compatible = "wm,wm8505-sdhc";
			reg = <0xd800a000 0x1000>;
			interrupts = <20 21>;
			clocks = <&clksdhc>;
			bus-width = <4>;
			sdon-inverted;
		};

		i2c_0: i2c@d8280000 {
			compatible = "wm,wm8505-i2c";
			reg = <0xd8280000 0x1000>;
			interrupts = <19>;
			clocks = <&clki2c0>;
			clock-frequency = <400000>;
		};

		i2c_1: i2c@d8320000 {
			compatible = "wm,wm8505-i2c";
			reg = <0xd8320000 0x1000>;
			interrupts = <18>;
			clocks = <&clki2c1>;
			clock-frequency = <400000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * wm8850-w70v2.dts
 *  - Device tree file for Wondermedia WM8850 Tablet
 *  - 'W70-V2' mainboard
 *  - HongLianYing 'HLY070ML268-21A' 7" LCD panel
 *
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 */

/dts-v1/;
/include/ "wm8850.dtsi"
#include <dt-bindings/pwm/pwm.h>

/ {
	model = "Wondermedia WM8850-W70v2 Tablet";

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;

		brightness-levels = <0 40 60 80 100 130 190 255>;
		default-brightness-level = <5>;
	};
};

&fb {
	bits-per-pixel = <16>;
	display-timings {
		native-mode = <&timing0>;
		timing0: 800x480 {
			clock-frequency = <0>; /* unused but required */
			hactive = <800>;
			vactive = <480>;
			hfront-porch = <40>;
			hback-porch = <88>;
			hsync-len = <0>;
			vback-porch = <32>;
			vfront-porch = <11>;
			vsync-len = <1>;
		};
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
 *
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "wm,wm8850";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;
		interrupt-parent = <&intc0>;

		intc0: interrupt-controller@d8140000 {
			compatible = "via,vt8500-intc";
			interrupt-controller;
			reg = <0xd8140000 0x10000>;
			#interrupt-cells = <1>;
		};

		/* Secondary IC cascaded to intc0 */
		intc1: interrupt-controller@d8150000 {
			compatible = "via,vt8500-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0xD8150000 0x10000>;
			interrupts = <56 57 58 59 60 61 62 63>;
		};

		pinctrl: pinctrl@d8110000 {
			compatible = "wm,wm8850-pinctrl";
			reg = <0xd8110000 0x10000>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		pmc@d8130000 {
			compatible = "via,vt8500-pmc";
			reg = <0xd8130000 0x1000>;

			clocks {
				#address-cells = <1>;
				#size-cells = <0>;

				ref25: ref25M {
					#clock-cells = <0>;
					compatible = "fixed-clock";
					clock-frequency = <25000000>;
				};

				ref24: ref24M {
					#clock-cells = <0>;
					compatible = "fixed-clock";
					clock-frequency = <24000000>;
				};

				plla: plla {
					#clock-cells = <0>;
					compatible = "wm,wm8850-pll-clock";
					clocks = <&ref24>;
					reg = <0x200>;
				};

				pllb: pllb {
					#clock-cells = <0>;
					compatible = "wm,wm8850-pll-clock";
					clocks = <&ref24>;
					reg = <0x204>;
				};

				pllc: pllc {
					#clock-cells = <0>;
					compatible = "wm,wm8850-pll-clock";
					clocks = <&ref24>;
					reg = <0x208>;
				};

				plld: plld {
					#clock-cells = <0>;
					compatible = "wm,wm8850-pll-clock";
					clocks = <&ref24>;
					reg = <0x20c>;
				};

				plle: plle {
					#clock-cells = <0>;
					compatible = "wm,wm8850-pll-clock";
					clocks = <&ref24>;
					reg = <0x210>;
				};

				pllf: pllf {
					#clock-cells = <0>;
					compatible = "wm,wm8850-pll-clock";
					clocks = <&ref24>;
					reg = <0x214>;
				};

				pllg: pllg {
					#clock-cells = <0>;
					compatible = "wm,wm8850-pll-clock";
					clocks = <&ref24>;
					reg = <0x218>;
				};

				clkarm: arm {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&plla>;
					divisor-reg = <0x300>;
				};

				clkahb: ahb {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x304>;
				};

				clkapb: apb {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x320>;
				};

				clkddr: ddr {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&plld>;
					divisor-reg = <0x310>;
				};

				clkuart0: uart0 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x254>;
					enable-bit = <24>;
				};

				clkuart1: uart1 {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&ref24>;
					enable-reg = <0x254>;
					enable-bit = <25>;
				};

                                clkuart2: uart2 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
                                        clocks = <&ref24>;
                                        enable-reg = <0x254>;
                                        enable-bit = <26>;
                                };

                                clkuart3: uart3 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
                                        clocks = <&ref24>;
                                        enable-reg = <0x254>;
                                        enable-bit = <27>;
                                };

				clkpwm: pwm {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x350>;
					enable-reg = <0x250>;
					enable-bit = <17>;
				};

				clksdhc: sdhc {
					#clock-cells = <0>;
					compatible = "via,vt8500-device-clock";
					clocks = <&pllb>;
					divisor-reg = <0x330>;
					divisor-mask = <0x3f>;
					enable-reg = <0x250>;
					enable-bit = <0>;
				};
			};
		};

		fb: fb@d8051700 {
			compatible = "wm,wm8505-fb";
			reg = <0xd8051700 0x200>;
		};

		ge_rops@d8050400 {
			compatible = "wm,prizm-ge-rops";
			reg = <0xd8050400 0x100>;
		};

		pwm: pwm@d8220000 {
			#pwm-cells = <3>;
			compatible = "via,vt8500-pwm";
			reg = <0xd8220000 0x100>;
			clocks = <&clkpwm>;
		};

		timer@d8130100 {
			compatible = "via,vt8500-timer";
			reg = <0xd8130100 0x28>;
			interrupts = <36>;
		};

		ehci@d8007900 {
			compatible = "via,vt8500-ehci";
			reg = <0xd8007900 0x200>;
			interrupts = <26>;
		};

		uhci@d8007b00 {
			compatible = "platform-uhci";
			reg = <0xd8007b00 0x200>;
			interrupts = <26>;
		};

		uhci@d8008d00 {
			compatible = "platform-uhci";
			reg = <0xd8008d00 0x200>;
			interrupts = <26>;
		};

		uart0: serial@d8200000 {
			compatible = "via,vt8500-uart";
			reg = <0xd8200000 0x1040>;
			interrupts = <32>;
			clocks = <&clkuart0>;
			status = "disabled";
		};

		uart1: serial@d82b0000 {
			compatible = "via,vt8500-uart";
			reg = <0xd82b0000 0x1040>;
			interrupts = <33>;
			clocks = <&clkuart1>;
			status = "disabled";
		};

                uart2: serial@d8210000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd8210000 0x1040>;
                        interrupts = <47>;
                        clocks = <&clkuart2>;
			status = "disabled";
                };

                uart3: serial@d82c0000 {
                        compatible = "via,vt8500-uart";
                        reg = <0xd82c0000 0x1040>;
                        interrupts = <50>;
                        clocks = <&clkuart3>;
			status = "disabled";
                };

		rtc@d8100000 {
			compatible = "via,vt8500-rtc";
			reg = <0xd8100000 0x10000>;
			interrupts = <48>;
		};

		sdhc@d800a000 {
			compatible = "wm,wm8505-sdhc";
			reg = <0xd800a000 0x1000>;
			interrupts = <20 21>;
			clocks = <&clksdhc>;
			bus-width = <4>;
			sdon-inverted;
		};

		ethernet@d8004000 {
			compatible = "via,vt8500-rhine";
			reg = <0xd8004000 0x100>;
			interrupts = <10>;
                };
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Xen Virtual Machine for unprivileged guests
 *
 * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU)
 * Cortex-A15 MPCore (V2P-CA15)
 *
 */

/dts-v1/;

/ {
	model = "XENVM-4.2";
	compatible = "xen,xenvm-4.2", "xen,xenvm";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		/* this field is going to be adjusted by the hypervisor */
		bootargs = "console=hvc0 root=/dev/xvda";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};
	};

	psci {
		compatible      = "arm,psci";
		method          = "hvc";
		cpu_off         = <1>;
		cpu_on          = <2>;
	};

	memory@80000000 {
		device_type = "memory";
		/* this field is going to be adjusted by the hypervisor */
		reg = <0 0x80000000 0 0x08000000>;
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0x2c001000 0 0x1000>,
		      <0 0x2c002000 0 0x100>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
	};

	hypervisor {
		compatible = "xen,xen-4.2", "xen,xen";
		/* this field is going to be adjusted by the hypervisor */
		reg = <0 0xb0000000 0 0x20000>;
		/* this field is going to be adjusted by the hypervisor */
		interrupts = <1 15 0xf08>;
	};

	motherboard {
		arm,v2m-memory-map = "rs1";
	};
};