code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/dma-router.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DMA Router Generic Binding

maintainers:
  - Vinod Koul <vkoul@kernel.org>

allOf:
  - $ref: "dma-common.yaml#"

description:
  DMA routers are transparent IP blocks used to route DMA request
  lines from devices to the DMA controller. Some SoCs (like TI DRA7x)
  have more peripherals integrated with DMA requests than what the DMA
  controller can handle directly.

properties:
  $nodename:
    pattern: "^dma-router(@.*)?$"

  dma-masters:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      maxItems: 1
    description:
      Array of phandles to the DMA controllers the router can direct
      the signal to.

  dma-requests:
    description:
      Number of incoming request lines the router can handle.

required:
  - "#dma-cells"
  - dma-masters

additionalProperties: true

examples:
  - |
    sdma_xbar: dma-router@4a002b78 {
        compatible = "ti,dra7-dma-crossbar";
        reg = <0x4a002b78 0xfc>;
        #dma-cells = <1>;
        dma-requests = <205>;
        ti,dma-safe-map = <0>;
        dma-masters = <&sdma>;
    };

...


code: This file has been moved to dma-controller.yaml.

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale enhanced Direct Memory Access(eDMA) Controller

description: |
  The eDMA channels have multiplex capability by programmable
  memory-mapped registers. channels are split into two groups, called
  DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
  by any channel of certain group, DMAMUX0 or DMAMUX1, but not both.

maintainers:
  - Peng Fan <peng.fan@nxp.com>

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,vf610-edma
          - fsl,imx7ulp-edma
      - items:
          - const: fsl,ls1028a-edma
          - const: fsl,vf610-edma

  reg:
    minItems: 2
    maxItems: 3

  interrupts:
    minItems: 2
    maxItems: 17

  interrupt-names:
    minItems: 2
    maxItems: 17

  "#dma-cells":
    const: 2

  dma-channels:
    const: 32

  clocks:
    maxItems: 2

  clock-names:
    maxItems: 2

  big-endian:
    description: |
      If present registers and hardware scatter/gather descriptors of the
      eDMA are implemented in big endian mode, otherwise in little mode.
    type: boolean

required:
  - "#dma-cells"
  - compatible
  - reg
  - interrupts
  - clocks
  - dma-channels

allOf:
  - $ref: "dma-controller.yaml#"
  - if:
      properties:
        compatible:
          contains:
            const: fsl,vf610-edma
    then:
      properties:
        clock-names:
          items:
            - const: dmamux0
            - const: dmamux1
        interrupts:
          maxItems: 2
        interrupt-names:
          items:
            - const: edma-tx
            - const: edma-err
        reg:
          maxItems: 3

  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx7ulp-edma
    then:
      properties:
        clock-names:
          items:
            - const: dma
            - const: dmamux0
        interrupts:
          maxItems: 17
        reg:
          maxItems: 2

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/vf610-clock.h>

    edma0: dma-controller@40018000 {
      #dma-cells = <2>;
      compatible = "fsl,vf610-edma";
      reg = <0x40018000 0x2000>,
            <0x40024000 0x1000>,
            <0x40025000 0x1000>;
      interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
                   <0 9 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "edma-tx", "edma-err";
      dma-channels = <32>;
      clock-names = "dmamux0", "dmamux1";
      clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/imx7ulp-clock.h>

    edma1: dma-controller@40080000 {
      #dma-cells = <2>;
      compatible = "fsl,imx7ulp-edma";
      reg = <0x40080000 0x2000>,
            <0x40210000 0x1000>;
      dma-channels = <32>;
      interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
                   /* last is eDMA2-ERR interrupt */
                   <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
       clock-names = "dma", "dmamux0";
       clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
    };


code:
* Freescale Direct Memory Access (DMA) Controller for i.MX

This document will only describe differences to the generic DMA Controller and
DMA request bindings as described in dma/dma.txt .

* DMA controller

Required properties:
- compatible : Should be "fsl,<chip>-dma". chip can be imx1, imx21 or imx27
- reg : Should contain DMA registers location and length
- interrupts : First item should be DMA interrupt, second one is optional and
    should contain DMA Error interrupt
- #dma-cells : Has to be 1. imx-dma does not support anything else.

Optional properties:
- dma-channels : Number of DMA channels supported. Should be 16.
- #dma-channels : deprecated
- dma-requests : Number of DMA requests supported.
- #dma-requests : deprecated

Example:

	dma: dma@10001000 {
		compatible = "fsl,imx27-dma";
		reg = <0x10001000 0x1000>;
		interrupts = <32 33>;
		#dma-cells = <1>;
		dma-channels = <16>;
	};

* DMA client

Clients have to specify the DMA requests with phandles in a list.

Required properties:
- dmas: List of one or more DMA request specifiers. One DMA request specifier
    consists of a phandle to the DMA controller followed by the integer
    specifying the request line.
- dma-names: List of string identifiers for the DMA requests. For the correct
    names, have a look at the specific client driver.

Example:

	sdhci1: sdhci@10013000 {
		...
		dmas = <&dma 7>;
		dma-names = "rx-tx";
		...
	};


code:
* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX

Required properties:
- compatible : Should be one of
      "fsl,imx25-sdma"
      "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
      "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
      "fsl,imx51-sdma"
      "fsl,imx53-sdma"
      "fsl,imx6q-sdma"
      "fsl,imx7d-sdma"
      "fsl,imx6ul-sdma"
      "fsl,imx8mq-sdma"
      "fsl,imx8mm-sdma"
      "fsl,imx8mn-sdma"
      "fsl,imx8mp-sdma"
  The -to variants should be preferred since they allow to determine the
  correct ROM script addresses needed for the driver to work without additional
  firmware.
- reg : Should contain SDMA registers location and length
- interrupts : Should contain SDMA interrupt
- #dma-cells : Must be <3>.
  The first cell specifies the DMA request/event ID.  See details below
  about the second and third cell.
- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
  scripts firmware

The second cell of dma phandle specifies the peripheral type of DMA transfer.
The full ID of peripheral types can be found below.

	ID	transfer type
	---------------------
	0	MCU domain SSI
	1	Shared SSI
	2	MMC
	3	SDHC
	4	MCU domain UART
	5	Shared UART
	6	FIRI
	7	MCU domain CSPI
	8	Shared CSPI
	9	SIM
	10	ATA
	11	CCM
	12	External peripheral
	13	Memory Stick Host Controller
	14	Shared Memory Stick Host Controller
	15	DSP
	16	Memory
	17	FIFO type Memory
	18	SPDIF
	19	IPU Memory
	20	ASRC
	21	ESAI
	22	SSI Dual FIFO	(needs firmware ver >= 2)
	23	Shared ASRC
	24	SAI

The third cell specifies the transfer priority as below.

	ID	transfer priority
	-------------------------
	0	High
	1	Medium
	2	Low

Optional properties:

- gpr : The phandle to the General Purpose Register (GPR) node.
- fsl,sdma-event-remap : Register bits of sdma event remap, the format is
  <reg shift val>.
    reg is the GPR register offset.
    shift is the bit position inside the GPR register.
    val is the value of the bit (0 or 1).

Examples:

sdma@83fb0000 {
	compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
	reg = <0x83fb0000 0x4000>;
	interrupts = <6>;
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "sdma-imx51.bin";
};

DMA clients connected to the i.MX SDMA controller must use the format
described in the dma.txt file.

Examples:

ssi2: ssi@70014000 {
	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	reg = <0x70014000 0x4000>;
	interrupts = <30>;
	clocks = <&clks 49>;
	dmas = <&sdma 24 1 0>,
	       <&sdma 25 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
};

Using the fsl,sdma-event-remap property:

If we want to use SDMA on the SAI1 port on a MX6SX:

&sdma {
	gpr = <&gpr>;
	/* SDMA events remap for SAI1_RX and SAI1_TX */
	fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
};

The fsl,sdma-event-remap property in this case has two values:
- <0 15 1> means that the offset is 0, so GPR0 is the register of the
SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
Setting bit 15 to 1 selects SAI1_RX.
- <0 16 1> means that the offset is 0, so GPR0 is the register of the
SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
Setting bit 16 to 1 selects SAI1_TX.


code:
* Freescale MXS DMA

Required properties:
- compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx"
- reg : Should contain registers location and length
- interrupts : Should contain the interrupt numbers of DMA channels.
  If a channel is empty/reserved, 0 should be filled in place.
- #dma-cells : Must be <1>.  The number cell specifies the channel ID.
- dma-channels : Number of channels supported by the DMA controller

Optional properties:
- interrupt-names : Name of DMA channel interrupts

Supported chips:
imx23, imx28.

Examples:

dma_apbh: dma-apbh@80004000 {
	compatible = "fsl,imx28-dma-apbh";
	reg = <0x80004000 0x2000>;
	interrupts = <82 83 84 85
		      88 88 88 88
		      88 88 88 88
		      87 86 0 0>;
	interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
			  "gpmi0", "gmpi1", "gpmi2", "gmpi3",
			  "gpmi4", "gmpi5", "gpmi6", "gmpi7",
			  "hsadc", "lcdif", "empty", "empty";
	#dma-cells = <1>;
	dma-channels = <16>;
};

dma_apbx: dma-apbx@80024000 {
	compatible = "fsl,imx28-dma-apbx";
	reg = <0x80024000 0x2000>;
	interrupts = <78 79 66 0
		      80 81 68 69
		      70 71 72 73
		      74 75 76 77>;
	interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
			  "saif0", "saif1", "i2c0", "i2c1",
			  "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
			  "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
	#dma-cells = <1>;
	dma-channels = <16>;
};

DMA clients connected to the MXS DMA controller must use the format
described in the dma.txt file.

Examples:

auart0: serial@8006a000 {
	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
	reg = <0x8006a000 0x2000>;
	interrupts = <112>;
	dmas = <&dma_apbx 8>, <&dma_apbx 9>;
	dma-names = "rx", "tx";
};


code:
NXP Layerscape SoC qDMA Controller
==================================

This device follows the generic DMA bindings defined in dma/dma.txt.

Required properties:

- compatible:		Must be one of
			 "fsl,ls1021a-qdma": for LS1021A Board
			 "fsl,ls1028a-qdma": for LS1028A Board
			 "fsl,ls1043a-qdma": for ls1043A Board
			 "fsl,ls1046a-qdma": for ls1046A Board
- reg:			Should contain the register's base address and length.
- interrupts:		Should contain a reference to the interrupt used by this
			device.
- interrupt-names:	Should contain interrupt names:
			 "qdma-queue0": the block0 interrupt
			 "qdma-queue1": the block1 interrupt
			 "qdma-queue2": the block2 interrupt
			 "qdma-queue3": the block3 interrupt
			 "qdma-error":  the error interrupt
- fsl,dma-queues:	Should contain number of queues supported.
- dma-channels:	Number of DMA channels supported
- block-number:	the virtual block number
- block-offset:	the offset of different virtual block
- status-sizes:	status queue size of per virtual block
- queue-sizes:		command queue size of per virtual block, the size number
			based on queues

Optional properties:

- dma-channels:		Number of DMA channels supported by the controller.
- big-endian:		If present registers and hardware scatter/gather descriptors
			of the qDMA are implemented in big endian mode, otherwise in little
			mode.

Examples:

	qdma: dma-controller@8390000 {
			compatible = "fsl,ls1021a-qdma";
			reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
			      <0x0 0x8389000 0x0 0x1000>, /* Status regs */
			      <0x0 0x838a000 0x0 0x2000>; /* Block regs */
			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "qdma-error",
				"qdma-queue0", "qdma-queue1";
			dma-channels = <8>;
			block-number = <2>;
			block-offset = <0x1000>;
			fsl,dma-queues = <2>;
			status-sizes = <64>;
			queue-sizes = <64 64>;
			big-endian;
		};

DMA clients must use the format described in dma/dma.txt file.


code:
* IMG Multi-threaded DMA Controller (MDC)

Required properties:
- compatible: Must be "img,pistachio-mdc-dma".
- reg: Must contain the base address and length of the MDC registers.
- interrupts: Must contain all the per-channel DMA interrupts.
- clocks: Must contain an entry for each entry in clock-names.
  See ../clock/clock-bindings.txt for details.
- clock-names: Must include the following entries:
  - sys: MDC system interface clock.
- img,cr-periph: Must contain a phandle to the peripheral control syscon
  node which contains the DMA request to channel mapping registers.
- img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
  The maximum burst size is this value multiplied by the hardware-reported bus
  width.
- #dma-cells: Must be 3:
  - The first cell is the peripheral's DMA request line.
  - The second cell is a bitmap specifying to which channels the DMA request
    line may be mapped (i.e. bit N set indicates channel N is usable).
  - The third cell is the thread ID to be used by the channel.

Optional properties:
- dma-channels: Number of supported DMA channels, up to 32.  If not specified
  the number reported by the hardware is used.

Example:

mdc: dma-controller@18143000 {
	compatible = "img,pistachio-mdc-dma";
	reg = <0x18143000 0x1000>;
	interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&system_clk>;
	clock-names = "sys";

	img,max-burst-multiplier = <16>;
	img,cr-periph = <&cr_periph>;

	#dma-cells = <3>;
};

spi@18100f00 {
	...
	dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
	dma-names = "tx", "rx";
	...
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs DMA Controller DT bindings

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    oneOf:
      - enum:
          - ingenic,jz4740-dma
          - ingenic,jz4725b-dma
          - ingenic,jz4760-dma
          - ingenic,jz4760-bdma
          - ingenic,jz4760-mdma
          - ingenic,jz4760b-dma
          - ingenic,jz4760b-bdma
          - ingenic,jz4760b-mdma
          - ingenic,jz4770-dma
          - ingenic,jz4780-dma
          - ingenic,x1000-dma
          - ingenic,x1830-dma
      - items:
          - const: ingenic,jz4770-bdma
          - const: ingenic,jz4760b-bdma

  reg:
    items:
      - description: Channel-specific registers
      - description: System control registers

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  "#dma-cells":
    enum: [2, 3]
    description: >
      DMA clients must use the format described in dma.txt, giving a phandle
      to the DMA controller plus the following integer cells:

      - Request type: The DMA request type specifies the device endpoint that
        will be the source or destination of the DMA transfer.
        If "#dma-cells" is 2, the request type is a single cell, and the
        direction will be unidirectional (either RX or TX but not both).
        If "#dma-cells" is 3, the request type has two cells; the first
        one corresponds to the host to device direction (TX), the second one
        corresponds to the device to host direction (RX). The DMA channel is
        then bidirectional.

      - Channel: If set to 0xffffffff, any available channel will be allocated
        for the client. Otherwise, the exact channel specified will be used.
        The channel should be reserved on the DMA controller using the
        ingenic,reserved-channels property.

  ingenic,reserved-channels:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: >
      Bitmask of channels to reserve for devices that need a specific
      channel. These channels will only be assigned when explicitely
      requested by a client. The primary use for this is channels 0 and
      1, which can be configured to have special behaviour for NAND/BCH
      when using programmable firmware.

required:
  - compatible
  - reg
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
    dma: dma-controller@13420000 {
      compatible = "ingenic,jz4780-dma";
      reg = <0x13420000 0x400>, <0x13421000 0x40>;

      interrupt-parent = <&intc>;
      interrupts = <10>;

      clocks = <&cgu JZ4780_CLK_PDMA>;

      #dma-cells = <2>;

      ingenic,reserved-channels = <0x3>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Lightning Mountain centralized DMA controllers.

maintainers:
  - chuanhua.lei@intel.com
  - mallikarjunax.reddy@intel.com

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    enum:
      - intel,lgm-cdma
      - intel,lgm-dma2tx
      - intel,lgm-dma1rx
      - intel,lgm-dma1tx
      - intel,lgm-dma0tx
      - intel,lgm-dma3
      - intel,lgm-toe-dma30
      - intel,lgm-toe-dma31

  reg:
    maxItems: 1

  "#dma-cells":
    const: 3
    description:
      The first cell is the peripheral's DMA request line.
      The second cell is the peripheral's (port) number corresponding to the channel.
      The third cell is the burst length of the channel.

  dma-channels:
    minimum: 1
    maximum: 16

  dma-channel-mask:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: ctrl

  interrupts:
    maxItems: 1

  intel,dma-poll-cnt:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      DMA descriptor polling counter is used to control the poling mechanism
      for the descriptor fetching for all channels.

  intel,dma-byte-en:
    type: boolean
    description:
      DMA byte enable is only valid for DMA write(RX).
      Byte enable(1) means DMA write will be based on the number of dwords
      instead of the whole burst.

  intel,dma-drb:
    type: boolean
    description:
      DMA descriptor read back to make sure data and desc synchronization.

  intel,dma-dburst-wr:
    type: boolean
    description:
      Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst;
      if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16.
      It only applies to RX DMA and memcopy DMA.

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    dma0: dma-controller@e0e00000 {
      compatible = "intel,lgm-cdma";
      reg = <0xe0e00000 0x1000>;
      #dma-cells = <3>;
      dma-channels = <16>;
      dma-channel-mask = <0xFFFF>;
      interrupt-parent = <&ioapic1>;
      interrupts = <82 1>;
      resets = <&rcu0 0x30 0>;
      reset-names = "ctrl";
      clocks = <&cgu0 80>;
      intel,dma-poll-cnt = <4>;
      intel,dma-byte-en;
      intel,dma-drb;
    };
  - |
    dma3: dma-controller@ec800000 {
      compatible = "intel,lgm-dma3";
      reg = <0xec800000 0x1000>;
      clocks = <&cgu0 71>;
      resets = <&rcu0 0x10 9>;
      #dma-cells = <3>;
      intel,dma-poll-cnt = <16>;
      intel,dma-byte-en;
      intel,dma-dburst-wr;
    };


code:
* Hisilicon K3 DMA controller

See dma.txt first

Required properties:
- compatible: Must be one of
-              "hisilicon,k3-dma-1.0"
-              "hisilicon,hisi-pcm-asp-dma-1.0"
- reg: Should contain DMA registers location and length.
- interrupts: Should contain one interrupt shared by all channel
- #dma-cells: see dma.txt, should be 1, para number
- dma-channels: physical channels supported
- dma-requests: virtual channels supported, each virtual channel
		have specific request line
- clocks: clock required

Example:

Controller:
		dma0: dma@fcd02000 {
			compatible = "hisilicon,k3-dma-1.0";
			reg = <0xfcd02000 0x1000>;
			#dma-cells = <1>;
			dma-channels = <16>;
			dma-requests = <27>;
			interrupts = <0 12 4>;
			clocks = <&pclk>;
		};

Client:
Use specific request line passing from dmax
For example, i2c0 read channel request line is 18, while write channel use 19

		i2c0: i2c@fcb08000 {
			compatible = "snps,designware-i2c";
			dmas =	<&dma0 18          /* read channel */
				 &dma0 19>;        /* write channel */
			dma-names = "rx", "tx";
		};

		i2c1: i2c@fcb09000 {
			compatible = "snps,designware-i2c";
			dmas =	<&dma0 20          /* read channel */
				 &dma0 21>;        /* write channel */
			dma-names = "rx", "tx";
		};


code:
NXP LPC18xx/43xx DMA MUX (DMA request router)

Required properties:
- compatible:	"nxp,lpc1850-dmamux"
- reg:		Memory map for accessing module
- #dma-cells:	Should be set to <3>.
		* 1st cell contain the master dma request signal
		* 2nd cell contain the mux value (0-3) for the peripheral
		* 3rd cell contain either 1 or 2 depending on the AHB
		  master used.
- dma-requests:	Number of DMA requests for the mux
- dma-masters:	phandle pointing to the DMA controller

The DMA controller node need to have the following poroperties:
- dma-requests:	Number of DMA requests the controller can handle

Example:

dmac: dma@40002000 {
	compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";
	arm,primecell-periphid = <0x00041080>;
	reg = <0x40002000 0x1000>;
	interrupts = <2>;
	clocks = <&ccu1 CLK_CPU_DMA>;
	clock-names = "apb_pclk";
	#dma-cells = <2>;
	dma-channels = <8>;
	dma-requests = <16>;
	lli-bus-interface-ahb1;
	lli-bus-interface-ahb2;
	mem-bus-interface-ahb1;
	mem-bus-interface-ahb2;
	memcpy-burst-size = <256>;
	memcpy-bus-width = <32>;
};

dmamux: dma-mux {
	compatible = "nxp,lpc1850-dmamux";
	#dma-cells = <3>;
	dma-requests = <64>;
	dma-masters = <&dmac>;
};

uart0: serial@40081000 {
	compatible = "nxp,lpc1850-uart", "ns16550a";
	reg = <0x40081000 0x1000>;
	reg-shift = <2>;
	interrupts = <24>;
	clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
	clock-names = "uartclk", "reg";
	dmas = <&dmamux 1 1 2
		&dmamux 2 1 2>;
	dma-names = "tx", "rx";
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek UART APDMA controller

maintainers:
  - Long Cheng <long.cheng@mediatek.com>

description: |
  The MediaTek UART APDMA controller provides DMA capabilities
  for the UART peripheral bus.

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt2712-uart-dma
              - mediatek,mt6795-uart-dma
              - mediatek,mt8365-uart-dma
              - mediatek,mt8516-uart-dma
          - const: mediatek,mt6577-uart-dma
      - enum:
          - mediatek,mt6577-uart-dma

  reg:
    minItems: 1
    maxItems: 16

  interrupts:
    description: |
      TX, RX interrupt lines for each UART APDMA channel
    minItems: 1
    maxItems: 16

  clocks:
    description: Must contain one entry for the APDMA main clock
    maxItems: 1

  clock-names:
    const: apdma

  "#dma-cells":
    const: 1
    description: |
      The first cell specifies the UART APDMA channel number

  dma-requests:
    description: |
      Number of virtual channels of the UART APDMA controller
    maximum: 16

  mediatek,dma-33bits:
    type: boolean
    description: Enable 33-bits UART APDMA support

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

if:
  not:
    required:
      - dma-requests
then:
  properties:
    interrupts:
      maxItems: 8
    reg:
      maxItems: 8

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt2712-clk.h>
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        apdma: dma-controller@11000400 {
            compatible = "mediatek,mt2712-uart-dma",
                         "mediatek,mt6577-uart-dma";
            reg = <0 0x11000400 0 0x80>,
                  <0 0x11000480 0 0x80>,
                  <0 0x11000500 0 0x80>,
                  <0 0x11000580 0 0x80>,
                  <0 0x11000600 0 0x80>,
                  <0 0x11000680 0 0x80>,
                  <0 0x11000700 0 0x80>,
                  <0 0x11000780 0 0x80>,
                  <0 0x11000800 0 0x80>,
                  <0 0x11000880 0 0x80>,
                  <0 0x11000900 0 0x80>,
                  <0 0x11000980 0 0x80>;
            interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
                         <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
                         <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
                         <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
                         <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
                         <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
                         <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
                         <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
                         <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
                         <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
                         <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
                         <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
            dma-requests = <12>;
            clocks = <&pericfg CLK_PERI_AP_DMA>;
            clock-names = "apdma";
            mediatek,dma-33bits;
            #dma-cells = <1>;
        };
    };

...


code:
* Milbeaut AHB DMA Controller

Milbeaut AHB DMA controller has transfer capability below.
 - device to memory transfer
 - memory to device transfer

Required property:
- compatible:       Should be  "socionext,milbeaut-m10v-hdmac"
- reg:              Should contain DMA registers location and length.
- interrupts:       Should contain all of the per-channel DMA interrupts.
                     Number of channels is configurable - 2, 4 or 8, so
                     the number of interrupts specified should be {2,4,8}.
- #dma-cells:       Should be 1. Specify the ID of the slave.
- clocks:           Phandle to the clock used by the HDMAC module.

Example:

	hdmac1: dma-controller@1e110000 {
		compatible = "socionext,milbeaut-m10v-hdmac";
		reg = <0x1e110000 0x10000>;
		interrupts = <0 132 4>,
			     <0 133 4>,
			     <0 134 4>,
			     <0 135 4>,
			     <0 136 4>,
			     <0 137 4>,
			     <0 138 4>,
			     <0 139 4>;
		#dma-cells = <1>;
		clocks = <&dummy_clk>;
	};


code:
* Milbeaut AXI DMA Controller

Milbeaut AXI DMA controller has only memory to memory transfer capability.

* DMA controller

Required property:
- compatible: 	Should be  "socionext,milbeaut-m10v-xdmac"
- reg:		Should contain DMA registers location and length.
- interrupts: 	Should contain all of the per-channel DMA interrupts.
                Number of channels is configurable - 2, 4 or 8, so
                the number of interrupts specified should be {2,4,8}.
- #dma-cells: 	Should be 1.

Example:
	xdmac0: dma-controller@1c250000 {
		compatible = "socionext,milbeaut-m10v-xdmac";
		reg = <0x1c250000 0x1000>;
		interrupts = <0 17 0x4>,
			     <0 18 0x4>,
			     <0 19 0x4>,
			     <0 20 0x4>;
		#dma-cells = <1>;
	};


code:
* MARVELL MMP DMA controller

Marvell Peripheral DMA Controller
Used platforms: pxa688, pxa910, pxa3xx, etc

Required properties:
- compatible: Should be "marvell,pdma-1.0"
- reg: Should contain DMA registers location and length.
- interrupts: Either contain all of the per-channel DMA interrupts
		or one irq for pdma device

Optional properties:
- dma-channels: Number of DMA channels supported by the controller (defaults
  to 32 when not specified)
- #dma-channels: deprecated
- dma-requests: Number of DMA requestor lines supported by the controller
  (defaults to 32 when not specified)
- #dma-requests: deprecated

"marvell,pdma-1.0"
Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.

Examples:

/*
 * Each channel has specific irq
 * ICU parse out irq channel from ICU register,
 * while DMA controller may not able to distinguish the irq channel
 * Using this method, interrupt-parent is required as demuxer
 * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
 * 18~21 is ADMA irq
 */
pdma: dma-controller@d4000000 {
	      compatible = "marvell,pdma-1.0";
	      reg = <0xd4000000 0x10000>;
	      interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
	      interrupt-parent = <&intcmux32>;
	      dma-channels = <16>;
      };

/*
 * One irq for all channels
 * Dmaengine driver (DMA controller) distinguish irq channel via
 * parsing internal register
 */
pdma: dma-controller@d4000000 {
	      compatible = "marvell,pdma-1.0";
	      reg = <0xd4000000 0x10000>;
	      interrupts = <47>;
	      dma-channels = <16>;
      };

Marvell Two Channel DMA Controller used specifically for audio
Used platforms: pxa688, pxa910

Required properties:
- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
- reg: Should contain DMA registers location and length.
- interrupts: Either contain all of the per-channel DMA interrupts
		or one irq for dma device

"marvell,adma-1.0" used on pxa688
"marvell,pxa910-squ" used on pxa910

Examples:

/* each channel has specific irq */
adma0: dma-controller@d42a0800 {
	      compatible = "marvell,adma-1.0";
	      reg = <0xd42a0800 0x100>;
	      interrupts = <18 19>;
	      interrupt-parent = <&intcmux32>;
      };

/* One irq for all channels */
squ: dma-controller@d42a0800 {
	      compatible = "marvell,pxa910-squ";
	      reg = <0xd42a0800 0x100>;
	      interrupts = <46>;
      };


code:
MOXA ART DMA Controller

See dma.txt first

Required properties:

- compatible :	Must be "moxa,moxart-dma"
- reg :		Should contain registers location and length
- interrupts :	Should contain an interrupt-specifier for the sole
		interrupt generated by the device
- #dma-cells :	Should be 1, a single cell holding a line request number

Example:

	dma: dma@90500000 {
		compatible = "moxa,moxart-dma";
		reg = <0x90500080 0x40>;
		interrupts = <24 0>;
		#dma-cells = <1>;
	};

Clients:

DMA clients connected to the MOXA ART DMA controller must use the format
described in the dma.txt file, using a two-cell specifier for each channel:
a phandle plus one integer cells.
The two cells in order are:

1. A phandle pointing to the DMA controller.
2. Peripheral identifier for the hardware handshaking interface.

Example:
Use specific request line passing from dma
For example, MMC request line is 5

	mmc: mmc@98e00000 {
		compatible = "moxa,moxart-mmc";
		reg = <0x98e00000 0x5C>;
		interrupts = <5 0>;
		clocks = <&clk_apb>;
		dmas =  <&dma 5>,
			<&dma 5>;
		dma-names = "tx", "rx";
	};


code:
* Freescale MPC512x and MPC8308 DMA Controller

The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
blocks of memory contents between memory and peripherals or
from memory to memory.

Refer to "Generic DMA Controller and DMA request bindings" in
the dma/dma.txt file for a more detailed description of binding.

Required properties:
- compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma";
- reg: should contain the DMA controller registers location and length;
- interrupt for the DMA controller: syntax of interrupt client node
	is described in interrupt-controller/interrupts.txt file.
- #dma-cells: the length of the DMA specifier, must be <1>.
	Each channel of this DMA controller has a peripheral request line,
	the assignment is fixed in hardware. This one cell
	in dmas property of a client device represents the channel number.

Example:

	dma0: dma@14000 {
		compatible = "fsl,mpc5121-dma";
		reg = <0x14000 0x1800>;
		interrupts = <65 0x8>;
		#dma-cells = <1>;
	};

DMA clients must use the format described in dma/dma.txt file.


code:
MediaTek High-Speed DMA Controller
==================================

This device follows the generic DMA bindings defined in dma/dma.txt.

Required properties:

- compatible:	Must be one of
		  "mediatek,mt7622-hsdma": for MT7622 SoC
		  "mediatek,mt7623-hsdma": for MT7623 SoC
- reg:		Should contain the register's base address and length.
- interrupts:	Should contain a reference to the interrupt used by this
		device.
- clocks:	Should be the clock specifiers corresponding to the entry in
		clock-names property.
- clock-names:	Should contain "hsdma" entries.
- power-domains: Phandle to the power domain that the device is part of
- #dma-cells: 	The length of the DMA specifier, must be <1>. This one cell
		in dmas property of a client device represents the channel
		number.
Example:

        hsdma: dma-controller@1b007000 {
		compatible = "mediatek,mt7623-hsdma";
		reg = <0 0x1b007000 0 0x1000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&ethsys CLK_ETHSYS_HSDMA>;
		clock-names = "hsdma";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
		#dma-cells = <1>;
	};

DMA clients must use the format described in dma/dma.txt file.


code:
* Marvell XOR v2 engines

Required properties:
- compatible: one of the following values:
    "marvell,armada-7k-xor"
    "marvell,xor-v2"
- reg: Should contain registers location and length (two sets)
    the first set is the DMA registers
    the second set is the global registers
- msi-parent: Phandle to the MSI-capable interrupt controller used for
  interrupts.

Optional properties:
- clocks: Optional reference to the clocks used by the XOR engine.
- clock-names: mandatory if there is a second clock, in this case the
   name must be "core" for the first clock and "reg" for the second
   one

Example:

	xor0@400000 {
		compatible = "marvell,xor-v2";
		reg = <0x400000 0x1000>,
		      <0x410000 0x1000>;
		msi-parent = <&gic_v2m0>;
		dma-coherent;
	};


code:
* Marvell XOR engines

Required properties:
- compatible: Should be one of the following:
  - "marvell,orion-xor"
  - "marvell,armada-380-xor"
  - "marvell,armada-3700-xor".
- reg: Should contain registers location and length (two sets)
    the first set is the low registers, the second set the high
    registers for the XOR engine.
- clocks: pointer to the reference clock

The DT node must also contains sub-nodes for each XOR channel that the
XOR engine has. Those sub-nodes have the following required
properties:
- interrupts: interrupt of the XOR channel

The sub-nodes used to contain one or several of the following
properties, but they are now deprecated:
- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
- dmacap,memset to indicate that the XOR channel is capable of memset operations
- dmacap,xor to indicate that the XOR channel is capable of xor operations
- dmacap,interrupt to indicate that the XOR channel is capable of
  generating interrupts

Example:

xor@d0060900 {
	compatible = "marvell,orion-xor";
	reg = <0xd0060900 0x100
	       0xd0060b00 0x100>;
	clocks = <&coreclk 0>;

	xor00 {
	      interrupts = <51>;
	};
	xor01 {
	      interrupts = <52>;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra GPC DMA Controller

description: |
  The Tegra General Purpose Central (GPC) DMA controller is used for faster
  data transfers between memory to memory, memory to device and device to
  memory.

maintainers:
  - Jon Hunter <jonathanh@nvidia.com>
  - Rajesh Gumasta <rgumasta@nvidia.com>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    oneOf:
      - const: nvidia,tegra186-gpcdma
      - items:
          - enum:
              - nvidia,tegra234-gpcdma
              - nvidia,tegra194-gpcdma
          - const: nvidia,tegra186-gpcdma

  "#dma-cells":
    const: 1

  reg:
    maxItems: 1

  interrupts:
    description:
      Should contain all of the per-channel DMA interrupts in
      ascending order with respect to the DMA channel index.
    minItems: 1
    maxItems: 31

  resets:
    maxItems: 1

  reset-names:
    const: gpcdma

  iommus:
    maxItems: 1

  dma-coherent: true

required:
  - compatible
  - reg
  - interrupts
  - resets
  - reset-names
  - "#dma-cells"
  - iommus

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/tegra186-mc.h>
    #include <dt-bindings/reset/tegra186-reset.h>

    dma-controller@2600000 {
        compatible = "nvidia,tegra186-gpcdma";
        reg = <0x2600000 0x210000>;
        resets = <&bpmp TEGRA186_RESET_GPCDMA>;
        reset-names = "gpcdma";
        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
        #dma-cells = <1>;
        iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
        dma-coherent;
    };
...


code:
* NVIDIA Tegra APB DMA controller

Required properties:
- compatible: Should be "nvidia,<chip>-apbdma"
- reg: Should contain DMA registers location and length. This shuld include
  all of the per-channel registers.
- interrupts: Should contain all of the per-channel DMA interrupts.
- clocks: Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
  - dma
- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in
  client nodes' dmas properties. The specifier represents the DMA request
  select value for the peripheral. For more details, consult the Tegra TRM's
  documentation of the APB DMA channel control register REQ_SEL field.

Examples:

apbdma: dma@6000a000 {
	compatible = "nvidia,tegra20-apbdma";
	reg = <0x6000a000 0x1200>;
	interrupts = < 0 136 0x04
		       0 137 0x04
		       0 138 0x04
		       0 139 0x04
		       0 140 0x04
		       0 141 0x04
		       0 142 0x04
		       0 143 0x04
		       0 144 0x04
		       0 145 0x04
		       0 146 0x04
		       0 147 0x04
		       0 148 0x04
		       0 149 0x04
		       0 150 0x04
		       0 151 0x04 >;
	clocks = <&tegra_car 34>;
	resets = <&tegra_car 34>;
	reset-names = "dma";
	#dma-cells = <1>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/nvidia,tegra210-adma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Audio DMA (ADMA) controller

description: |
  The Tegra Audio DMA controller is used for transferring data
  between system memory and the Audio Processing Engine (APE).

maintainers:
  - Jon Hunter <jonathanh@nvidia.com>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    oneOf:
      - enum:
          - nvidia,tegra210-adma
          - nvidia,tegra186-adma
      - items:
          - enum:
              - nvidia,tegra234-adma
              - nvidia,tegra194-adma
          - const: nvidia,tegra186-adma

  reg:
    maxItems: 1

  interrupts:
    description: |
      Should contain all of the per-channel DMA interrupts in
      ascending order with respect to the DMA channel index.
    minItems: 1
    maxItems: 32

  clocks:
    description: Must contain one entry for the ADMA module clock
    maxItems: 1

  clock-names:
    const: d_audio

  "#dma-cells":
    description: |
      The first cell denotes the receive/transmit request number and
      should be between 1 and the maximum number of requests supported.
      This value corresponds to the RX/TX_REQUEST_SELECT fields in the
      ADMA_CHn_CTRL register.
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include<dt-bindings/clock/tegra210-car.h>

    dma-controller@702e2000 {
        compatible = "nvidia,tegra210-adma";
        reg = <0x702e2000 0x2000>;
        interrupt-parent = <&tegra_agic>;
        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
        clock-names = "d_audio";
        #dma-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/owl-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Actions Semi Owl SoCs DMA controller

description: |
  The OWL DMA is a general-purpose direct memory access controller capable of
  supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
  independent DMA channels for the S500 and S900 SoC variants.

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    enum:
      - actions,s500-dma
      - actions,s700-dma
      - actions,s900-dma

  reg:
    maxItems: 1

  interrupts:
    description:
      controller supports 4 interrupts, which are freely assignable to the
      DMA channels.
    maxItems: 4

  "#dma-cells":
    const: 1

  dma-channels:
    maximum: 12

  dma-requests:
    maximum: 46

  clocks:
    maxItems: 1
    description:
      Phandle and Specifier of the clock feeding the DMA controller.

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - "#dma-cells"
  - dma-channels
  - dma-requests
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    dma: dma-controller@e0260000 {
        compatible = "actions,s900-dma";
        reg = <0xe0260000 0x1000>;
        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
        #dma-cells = <1>;
        dma-channels = <12>;
        dma-requests = <46>;
        clocks = <&clock 22>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/qcom,adm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm ADM DMA Controller

maintainers:
  - Christian Marangi <ansuelsmth@gmail.com>
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |
  QCOM ADM DMA controller provides DMA capabilities for
  peripheral buses such as NAND and SPI.

properties:
  compatible:
    const: qcom,adm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#dma-cells":
    const: 1

  clocks:
    items:
      - description: phandle to the core clock
      - description: phandle to the iface clock

  clock-names:
    items:
      - const: core
      - const: iface

  resets:
    items:
      - description: phandle to the clk reset
      - description: phandle to the pbus reset
      - description: phandle to the c0 reset
      - description: phandle to the c1 reset
      - description: phandle to the c2 reset

  reset-names:
    items:
      - const: clk
      - const: pbus
      - const: c0
      - const: c1
      - const: c2

  qcom,ee:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: indicates the security domain identifier used in the secure world.
    minimum: 0
    maximum: 255

required:
  - compatible
  - reg
  - interrupts
  - "#dma-cells"
  - clocks
  - clock-names
  - resets
  - reset-names
  - qcom,ee

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
    #include <dt-bindings/reset/qcom,gcc-ipq806x.h>

    adm_dma: dma-controller@18300000 {
        compatible = "qcom,adm";
        reg = <0x18300000 0x100000>;
        interrupts = <0 170 0>;
        #dma-cells = <1>;

        clocks = <&gcc ADM0_CLK>,
                  <&gcc ADM0_PBUS_CLK>;
        clock-names = "core", "iface";

        resets = <&gcc ADM0_RESET>,
                  <&gcc ADM0_PBUS_RESET>,
                  <&gcc ADM0_C0_RESET>,
                  <&gcc ADM0_C1_RESET>,
                  <&gcc ADM0_C2_RESET>;
        reset-names = "clk", "pbus", "c0", "c1", "c2";
        qcom,ee = <0>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/qcom,bam-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies Inc BAM DMA controller

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <andersson@kernel.org>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    enum:
        # APQ8064, IPQ8064 and MSM8960
      - qcom,bam-v1.3.0
        # MSM8974, APQ8074 and APQ8084
      - qcom,bam-v1.4.0
        # MSM8916 and SDM845
      - qcom,bam-v1.7.0

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: bam_clk

  "#dma-cells":
    const: 1

  interrupts:
    maxItems: 1

  iommus:
    minItems: 1
    maxItems: 4

  num-channels:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Indicates supported number of DMA channels in a remotely controlled bam.

  qcom,controlled-remotely:
    type: boolean
    description:
      Indicates that the bam is controlled by remote proccessor i.e. execution
      environment.

  qcom,ee:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 7
    description:
      Indicates the active Execution Environment identifier (0-7) used in the
      secure world.

  qcom,num-ees:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Indicates supported number of Execution Environments in a remotely
      controlled bam.

  qcom,powered-remotely:
    type: boolean
    description:
      Indicates that the bam is powered up by a remote processor but must be
      initialized by the local processor.

  reg:
    maxItems: 1

required:
  - compatible
  - "#dma-cells"
  - interrupts
  - qcom,ee
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,gcc-msm8974.h>

    dma-controller@f9944000 {
        compatible = "qcom,bam-v1.4.0";
        reg = <0xf9944000 0x19000>;
        interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&gcc GCC_BLSP2_AHB_CLK>;
        clock-names = "bam_clk";
        #dma-cells = <1>;
        qcom,ee = <0>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies Inc GPI DMA controller

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description: |
  QCOM GPI DMA controller provides DMA capabilities for
  peripheral buses such as I2C, UART, and SPI.

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    enum:
      - qcom,sc7280-gpi-dma
      - qcom,sdm845-gpi-dma
      - qcom,sm6350-gpi-dma
      - qcom,sm8150-gpi-dma
      - qcom,sm8250-gpi-dma
      - qcom,sm8350-gpi-dma
      - qcom,sm8450-gpi-dma

  reg:
    maxItems: 1

  interrupts:
    description:
      Interrupt lines for each GPI instance
    minItems: 1
    maxItems: 13

  "#dma-cells":
    const: 3
    description: >
      DMA clients must use the format described in dma.txt, giving a phandle
      to the DMA controller plus the following 3 integer cells:
      - channel: if set to 0xffffffff, any available channel will be allocated
        for the client. Otherwise, the exact channel specified will be used.
      - seid: serial id of the client as defined in the SoC documentation.
      - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h

  iommus:
    maxItems: 1

  dma-channels:
    maximum: 31

  dma-channel-mask:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - "#dma-cells"
  - iommus
  - dma-channels
  - dma-channel-mask

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/dma/qcom-gpi.h>
    gpi_dma0: dma-controller@800000 {
        compatible = "qcom,sdm845-gpi-dma";
        #dma-cells = <3>;
        reg = <0x00800000 0x60000>;
        iommus = <&apps_smmu 0x0016 0x0>;
        dma-channels = <13>;
        dma-channel-mask = <0xfa>;
        interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
    };

...


code:
Qualcomm Technologies HIDMA Management interface

Qualcomm Technologies HIDMA is a high speed DMA device. It only supports
memcpy and memset capabilities. It has been designed for virtualized
environments.

Each HIDMA HW instance consists of multiple DMA channels. These channels
share the same bandwidth. The bandwidth utilization can be partitioned
among channels based on the priority and weight assignments.

There are only two priority levels and 15 weigh assignments possible.

Other parameters here determine how much of the system bus this HIDMA
instance can use like maximum read/write request and number of bytes to
read/write in a single burst.

Main node required properties:
- compatible: "qcom,hidma-mgmt-1.0";
- reg: Address range for DMA device
- dma-channels: Number of channels supported by this DMA controller.
- max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
  occupy the bus for in a single transaction. A memcpy requested is
  fragmented to multiples of this amount. This parameter is used while
  writing into destination memory. Setting this value incorrectly can
  starve other peripherals in the system.
- max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
  occupy the bus for in a single transaction. A memcpy request is
  fragmented to multiples of this amount. This parameter is used while
  reading the source memory. Setting this value incorrectly can starve
  other peripherals in the system.
- max-write-transactions: This value is how many times a write burst is
  applied back to back while writing to the destination before yielding
  the bus.
- max-read-transactions: This value is how many times a read burst is
  applied back to back while reading the source before yielding the bus.
- channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
  Once a reset is applied to the HW, HW starts a timer for reset operation
  to confirm. If reset is not completed within this time, HW reports reset
  failure.

Sub-nodes:

HIDMA has one or more DMA channels that are used to move data from one
memory location to another.

When the OS is not in control of the management interface (i.e. it's a guest),
the channel nodes appear on their own, not under a management node.

Required properties:
- compatible: must contain "qcom,hidma-1.0" for initial HW or
  "qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW.
- reg: Addresses for the transfer and event channel
- interrupts: Should contain the event interrupt
- desc-count: Number of asynchronous requests this channel can handle
- iommus: required a iommu node

Optional properties for MSI:
- msi-parent : See the generic MSI binding described in
 devicetree/bindings/interrupt-controller/msi.txt for a description of the
 msi-parent property.

Example:

Hypervisor OS configuration:

	hidma-mgmt@f9984000 = {
		compatible = "qcom,hidma-mgmt-1.0";
		reg = <0xf9984000 0x15000>;
		dma-channels = <6>;
		max-write-burst-bytes = <1024>;
		max-read-burst-bytes = <1024>;
		max-write-transactions = <31>;
		max-read-transactions = <31>;
		channel-reset-timeout-cycles = <0x500>;

		hidma_24: dma-controller@5c050000 {
			compatible = "qcom,hidma-1.0";
			reg = <0 0x5c050000 0x0 0x1000>,
			      <0 0x5c0b0000 0x0 0x1000>;
			interrupts = <0 389 0>;
			desc-count = <10>;
			iommus = <&system_mmu>;
		};
	};

Guest OS configuration:

	hidma_24: dma-controller@5c050000 {
		compatible = "qcom,hidma-1.0";
		reg = <0 0x5c050000 0x0 0x1000>,
		      <0 0x5c0b0000 0x0 0x1000>;
		interrupts = <0 389 0>;
		desc-count = <10>;
		iommus = <&system_mmu>;
	};


code:
* Renesas "Type-AXI" NBPFAXI* DMA controllers

* DMA controller

Required properties

- compatible:	must be one of
		"renesas,nbpfaxi64dmac1b4"
		"renesas,nbpfaxi64dmac1b8"
		"renesas,nbpfaxi64dmac1b16"
		"renesas,nbpfaxi64dmac4b4"
		"renesas,nbpfaxi64dmac4b8"
		"renesas,nbpfaxi64dmac4b16"
		"renesas,nbpfaxi64dmac8b4"
		"renesas,nbpfaxi64dmac8b8"
		"renesas,nbpfaxi64dmac8b16"
- #dma-cells:	must be 2: the first integer is a terminal number, to which this
		slave is connected, the second one is flags. Flags is a bitmask
		with the following bits defined:

#define NBPF_SLAVE_RQ_HIGH	1
#define NBPF_SLAVE_RQ_LOW	2
#define NBPF_SLAVE_RQ_LEVEL	4

Optional properties:
- max-burst-mem-read:	limit burst size for memory reads
  (DMA_MEM_TO_MEM/DMA_MEM_TO_DEV) to this value, specified in bytes, rather
  than using the maximum burst size allowed by the hardware's buffer size.
- max-burst-mem-write:	limit burst size for memory writes
  (DMA_DEV_TO_MEM/DMA_MEM_TO_MEM) to this value, specified in bytes, rather
  than using the maximum burst size allowed by the hardware's buffer size.
  If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
  will use the lower value.

You can use dma-channels and dma-requests as described in dma.txt, although they
won't be used, this information is derived from the compatibility string.

Example:

	dma: dma-controller@48000000 {
		compatible = "renesas,nbpfaxi64dmac8b4";
		reg = <0x48000000 0x400>;
		interrupts = <0 12 0x4
			      0 13 0x4
			      0 14 0x4
			      0 15 0x4
			      0 16 0x4
			      0 17 0x4
			      0 18 0x4
			      0 19 0x4>;
		#dma-cells = <2>;
		dma-channels = <8>;
		dma-requests = <8>;
	};

* DMA client

Required properties:

dmas and dma-names are required, as described in dma.txt.

Example:

#include <dt-bindings/dma/nbpfaxi.h>

...
		dmas = <&dma 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)
			&dma 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
		dma-names = "rx", "tx";


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car and RZ/G DMA Controller

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,dmac-r8a7742  # RZ/G1H
              - renesas,dmac-r8a7743  # RZ/G1M
              - renesas,dmac-r8a7744  # RZ/G1N
              - renesas,dmac-r8a7745  # RZ/G1E
              - renesas,dmac-r8a77470 # RZ/G1C
              - renesas,dmac-r8a774a1 # RZ/G2M
              - renesas,dmac-r8a774b1 # RZ/G2N
              - renesas,dmac-r8a774c0 # RZ/G2E
              - renesas,dmac-r8a774e1 # RZ/G2H
              - renesas,dmac-r8a7790  # R-Car H2
              - renesas,dmac-r8a7791  # R-Car M2-W
              - renesas,dmac-r8a7792  # R-Car V2H
              - renesas,dmac-r8a7793  # R-Car M2-N
              - renesas,dmac-r8a7794  # R-Car E2
              - renesas,dmac-r8a7795  # R-Car H3
              - renesas,dmac-r8a7796  # R-Car M3-W
              - renesas,dmac-r8a77961 # R-Car M3-W+
              - renesas,dmac-r8a77965 # R-Car M3-N
              - renesas,dmac-r8a77970 # R-Car V3M
              - renesas,dmac-r8a77980 # R-Car V3H
              - renesas,dmac-r8a77990 # R-Car E3
              - renesas,dmac-r8a77995 # R-Car D3
          - const: renesas,rcar-dmac

      - items:
          - enum:
              - renesas,dmac-r8a779a0     # R-Car V3U
              - renesas,dmac-r8a779f0     # R-Car S4-8
              - renesas,dmac-r8a779g0     # R-Car V4H
          - const: renesas,rcar-gen4-dmac # R-Car Gen4

  reg: true

  interrupts:
    minItems: 9
    maxItems: 17

  interrupt-names:
    minItems: 9
    items:
      - const: error
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"
      - pattern: "^ch([0-9]|1[0-5])$"

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: fck

  '#dma-cells':
    const: 1
    description:
      The cell specifies the MID/RID of the DMAC port connected to
      the DMA client.

  dma-channels:
    minimum: 8
    maximum: 16

  dma-channel-mask: true

  iommus:
    minItems: 8
    maxItems: 16

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - '#dma-cells'
  - dma-channels
  - power-domains
  - resets

if:
  properties:
    compatible:
      contains:
        enum:
          - renesas,rcar-gen4-dmac
then:
  properties:
    reg:
      items:
        - description: Base register block
        - description: Channel register block
else:
  properties:
    reg:
      maxItems: 1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>

    dmac0: dma-controller@e6700000 {
        compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
        reg = <0xe6700000 0x20000>;
        interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "error",
                          "ch0", "ch1", "ch2", "ch3",
                          "ch4", "ch5", "ch6", "ch7",
                          "ch8", "ch9", "ch10", "ch11",
                          "ch12", "ch13", "ch14";
        clocks = <&cpg CPG_MOD 219>;
        clock-names = "fck";
        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
        resets = <&cpg 219>;
        #dma-cells = <1>;
        dma-channels = <15>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller

maintainers:
  - Biju Das <biju.das.jz@bp.renesas.com>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    items:
      - enum:
          - renesas,r9a07g043-dmac # RZ/G2UL
          - renesas,r9a07g044-dmac # RZ/G2{L,LC}
          - renesas,r9a07g054-dmac # RZ/V2L
      - const: renesas,rz-dmac

  reg:
    items:
      - description: Control and channel register block
      - description: DMA extended resource selector block

  interrupts:
    maxItems: 17

  interrupt-names:
    items:
      - const: error
      - const: ch0
      - const: ch1
      - const: ch2
      - const: ch3
      - const: ch4
      - const: ch5
      - const: ch6
      - const: ch7
      - const: ch8
      - const: ch9
      - const: ch10
      - const: ch11
      - const: ch12
      - const: ch13
      - const: ch14
      - const: ch15

  clocks:
    items:
      - description: DMA main clock
      - description: DMA register access clock

  '#dma-cells':
    const: 1
    description:
      The cell specifies the encoded MID/RID values of the DMAC port
      connected to the DMA client and the slave channel configuration
      parameters.
      bits[0:9] - Specifies MID/RID value
      bit[10] - Specifies DMA request high enable (HIEN)
      bit[11] - Specifies DMA request detection type (LVL)
      bits[12:14] - Specifies DMAACK output mode (AM)
      bit[15] - Specifies Transfer Mode (TM)

  dma-channels:
    const: 16

  power-domains:
    maxItems: 1

  resets:
    items:
      - description: Reset for DMA ARESETN reset terminal
      - description: Reset for DMA RST_ASYNC reset terminal

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - '#dma-cells'
  - dma-channels
  - power-domains
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/r9a07g044-cpg.h>

    dmac: dma-controller@11820000 {
        compatible = "renesas,r9a07g044-dmac",
                     "renesas,rz-dmac";
        reg = <0x11820000 0x10000>,
              <0x11830000 0x10000>;
        interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
        interrupt-names = "error",
                          "ch0", "ch1", "ch2", "ch3",
                          "ch4", "ch5", "ch6", "ch7",
                          "ch8", "ch9", "ch10", "ch11",
                          "ch12", "ch13", "ch14", "ch15";
        clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
                 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
        power-domains = <&cpg>;
        resets = <&cpg R9A07G044_DMAC_ARESETN>,
                 <&cpg R9A07G044_DMAC_RST_ASYNC>;
        #dma-cells = <1>;
        dma-channels = <16>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/N1 DMA mux

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

allOf:
  - $ref: "dma-router.yaml#"

properties:
  compatible:
    const: renesas,rzn1-dmamux

  reg:
    maxItems: 1
    description: DMA mux first register offset within the system control parent.

  '#dma-cells':
    const: 6
    description:
      The first four cells are dedicated to the master DMA controller. The fifth
      cell gives the DMA mux bit index that must be set starting from 0. The
      sixth cell gives the binary value that must be written there, ie. 0 or 1.

  dma-masters:
    minItems: 1
    maxItems: 2

  dma-requests:
    const: 32

required:
  - reg
  - dma-requests

additionalProperties: false

examples:
  - |
    dma-router@a0 {
      compatible = "renesas,rzn1-dmamux";
      reg = <0xa0 4>;
      #dma-cells = <6>;
      dma-masters = <&dma0 &dma1>;
      dma-requests = <32>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/renesas,usb-dmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas USB DMA Controller

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    items:
      - enum:
          - renesas,r8a7742-usb-dmac  # RZ/G1H
          - renesas,r8a7743-usb-dmac  # RZ/G1M
          - renesas,r8a7744-usb-dmac  # RZ/G1N
          - renesas,r8a7745-usb-dmac  # RZ/G1E
          - renesas,r8a77470-usb-dmac # RZ/G1C
          - renesas,r8a774a1-usb-dmac # RZ/G2M
          - renesas,r8a774b1-usb-dmac # RZ/G2N
          - renesas,r8a774c0-usb-dmac # RZ/G2E
          - renesas,r8a774e1-usb-dmac # RZ/G2H
          - renesas,r8a7790-usb-dmac  # R-Car H2
          - renesas,r8a7791-usb-dmac  # R-Car M2-W
          - renesas,r8a7793-usb-dmac  # R-Car M2-N
          - renesas,r8a7794-usb-dmac  # R-Car E2
          - renesas,r8a7795-usb-dmac  # R-Car H3
          - renesas,r8a7796-usb-dmac  # R-Car M3-W
          - renesas,r8a77961-usb-dmac # R-Car M3-W+
          - renesas,r8a77965-usb-dmac # R-Car M3-N
          - renesas,r8a77990-usb-dmac # R-Car E3
          - renesas,r8a77995-usb-dmac # R-Car D3
      - const: renesas,usb-dmac

  reg:
    maxItems: 1

  interrupts:
    minItems: 2
    maxItems: 2

  interrupt-names:
    items:
      - pattern: ch0
      - pattern: ch1

  clocks:
    maxItems: 1

  '#dma-cells':
    const: 1
    description:
      The cell specifies the channel number of the DMAC port connected to
      the DMA client.

  dma-channels:
    const: 2

  iommus:
    minItems: 2
    maxItems: 2

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - '#dma-cells'
  - dma-channels
  - power-domains
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>

    usb_dmac0: dma-controller@e65a0000 {
        compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
        reg = <0xe65a0000 0x100>;
        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "ch0", "ch1";
        clocks = <&cpg CPG_MOD 330>;
        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
        resets = <&cpg 330>;
        #dma-cells = <1>;
        dma-channels = <2>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive Unleashed Rev C000 Platform DMA

maintainers:
  - Green Wan <green.wan@sifive.com>
  - Palmer Debbelt <palmer@sifive.com>
  - Paul Walmsley <paul.walmsley@sifive.com>

description: |
  Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
  channels. Each channel has 2 interrupts. One is for DMA done and
  the other is for DME error.

  In different SoC, DMA could be attached to different IRQ line.
  DT file need to be changed to meet the difference. For technical
  doc,

  https://static.dev.sifive.com/FU540-C000-v1.0.pdf

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    items:
      - enum:
          - sifive,fu540-c000-pdma
      - const: sifive,pdma0
    description:
      Should be "sifive,<chip>-pdma" and "sifive,pdma<version>".
      Supported compatible strings are -
      "sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the
      SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP block
      with no chip integration tweaks.

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 8

  dma-channels:
    description: For backwards-compatibility, the default value is 4
    minimum: 1
    maximum: 4
    default: 4

  '#dma-cells':
    const: 1

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    dma-controller@3000000 {
      compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
      reg = <0x3000000 0x8000>;
      dma-channels = <4>;
      interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
      #dma-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys Designware DMA Controller

maintainers:
  - Viresh Kumar <vireshk@kernel.org>
  - Andy Shevchenko <andriy.shevchenko@linux.intel.com>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    oneOf:
      - const: snps,dma-spear1340
      - items:
          - enum:
              - renesas,r9a06g032-dma
          - const: renesas,rzn1-dma

  "#dma-cells":
    minimum: 3
    maximum: 4
    description: |
      First cell is a phandle pointing to the DMA controller. Second one is
      the DMA request line number. Third cell is the memory master identifier
      for transfers on dynamically allocated channel. Fourth cell is the
      peripheral master identifier for transfers on an allocated channel. Fifth
      cell is an optional mask of the DMA channels permitted to be allocated
      for the corresponding client device.

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    description: AHB interface reference clock.
    const: hclk

  dma-channels:
    description: |
      Number of DMA channels supported by the controller. In case if
      not specified the driver will try to auto-detect this and
      the rest of the optional parameters.
    minimum: 1
    maximum: 8

  dma-requests:
    minimum: 1
    maximum: 16

  dma-masters:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Number of DMA masters supported by the controller. In case if
      not specified the driver will try to auto-detect this and
      the rest of the optional parameters.
    minimum: 1
    maximum: 4

  chan_allocation_order:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      DMA channels allocation order specifier. Zero means ascending order
      (first free allocated), while one - descending (last free allocated).
    default: 0
    enum: [0, 1]

  chan_priority:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      DMA channels priority order. Zero means ascending channels priority
      so the very first channel has the highest priority. While 1 means
      descending priority (the last channel has the highest priority).
    default: 0
    enum: [0, 1]

  block_size:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Maximum block size supported by the DMA controller.
    enum: [3, 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095]

  data-width:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: Data bus width per each DMA master in bytes.
    items:
      maxItems: 4
      items:
        enum: [4, 8, 16, 32]

  data_width:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    deprecated: true
    description: |
      Data bus width per each DMA master in (2^n * 8) bits. This property is
      deprecated. It' usage is discouraged in favor of data-width one. Moreover
      the property incorrectly permits to define data-bus width of 8 and 16
      bits, which is impossible in accordance with DW DMAC IP-core data book.
    items:
      maxItems: 4
      items:
        enum:
          - 0 # 8 bits
          - 1 # 16 bits
          - 2 # 32 bits
          - 3 # 64 bits
          - 4 # 128 bits
          - 5 # 256 bits
        default: 0

  multi-block:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: |
      LLP-based multi-block transfer supported by hardware per
      each DMA channel.
    items:
      maxItems: 8
      items:
        enum: [0, 1]
        default: 1

  snps,max-burst-len:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: |
      Maximum length of the burst transactions supported by the controller.
      This property defines the upper limit of the run-time burst setting
      (CTLx.SRC_MSIZE/CTLx.DST_MSIZE fields) so the allowed burst length
      will be from 1 to max-burst-len words. It's an array property with one
      cell per channel in the units determined by the value set in the
      CTLx.SRC_TR_WIDTH/CTLx.DST_TR_WIDTH fields (data width).
    items:
      maxItems: 8
      items:
        enum: [4, 8, 16, 32, 64, 128, 256]
        default: 256

  snps,dma-protection-control:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting
      indicates the following features: bit 0 - privileged mode,
      bit 1 - DMA is bufferable, bit 2 - DMA is cacheable.
    default: 0
    minimum: 0
    maximum: 7

unevaluatedProperties: false

required:
  - compatible
  - "#dma-cells"
  - reg
  - interrupts

examples:
  - |
    dma-controller@fc000000 {
      compatible = "snps,dma-spear1340";
      reg = <0xfc000000 0x1000>;
      interrupt-parent = <&vic1>;
      interrupts = <12>;

      dma-channels = <8>;
      dma-requests = <16>;
      dma-masters = <4>;
      #dma-cells = <3>;

      chan_allocation_order = <1>;
      chan_priority = <1>;
      block_size = <0xfff>;
      data-width = <8 8>;
      multi-block = <0 0 0 0 0 0 0 0>;
      snps,max-burst-len = <16 16 4 4 4 4 4 4>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare AXI DMA Controller

maintainers:
  - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

description:
  Synopsys DesignWare AXI DMA Controller DT Binding

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    enum:
      - snps,axi-dma-1.01a
      - intel,kmb-axi-dma

  reg:
    minItems: 1
    items:
      - description: Address range of the DMAC registers
      - description: Address range of the DMAC APB registers

  reg-names:
    items:
      - const: axidma_ctrl_regs
      - const: axidma_apb_regs

  interrupts:
    description:
      If the IP-core synthesis parameter DMAX_INTR_IO_TYPE is set to 1, this
      will be per-channel interrupts. Otherwise, this is a single combined IRQ
      for all channels.
    minItems: 1
    maxItems: 8

  clocks:
    items:
      - description: Bus Clock
      - description: Module Clock

  clock-names:
    items:
      - const: core-clk
      - const: cfgr-clk

  '#dma-cells':
    const: 1

  dma-channels:
    minimum: 1
    maximum: 8

  resets:
    maxItems: 1

  snps,dma-masters:
    description: |
      Number of AXI masters supported by the hardware.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2]

  snps,data-width:
    description: |
      AXI data width supported by hardware.
      (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2, 3, 4, 5, 6]

  snps,priority:
    description: |
      Channel priority specifier associated with the DMA channels.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 8

  snps,block-size:
    description: |
      Channel block size specifier associated with the DMA channels.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 8

  snps,axi-max-burst-len:
    description: |
      Restrict master AXI burst length by value specified in this property.
      If this property is missing the maximum AXI burst length supported by
      DMAC is used.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 256

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts
  - '#dma-cells'
  - dma-channels
  - snps,dma-masters
  - snps,data-width
  - snps,priority
  - snps,block-size

additionalProperties: false

examples:
  - |
     #include <dt-bindings/interrupt-controller/arm-gic.h>
     #include <dt-bindings/interrupt-controller/irq.h>
     /* example with snps,dw-axi-dmac */
     dmac: dma-controller@80000 {
         compatible = "snps,axi-dma-1.01a";
         reg = <0x80000 0x400>;
         clocks = <&core_clk>, <&cfgr_clk>;
         clock-names = "core-clk", "cfgr-clk";
         interrupt-parent = <&intc>;
         interrupts = <27>;
         #dma-cells = <1>;
         dma-channels = <4>;
         snps,dma-masters = <2>;
         snps,data-width = <3>;
         snps,block-size = <4096 4096 4096 4096>;
         snps,priority = <0 1 2 3>;
         snps,axi-max-burst-len = <16>;
     };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UniPhier Media IO DMA controller

description: |
  This works as an external DMA engine for SD/eMMC controllers etc.
  found in UniPhier LD4, Pro4, sLD8 SoCs.

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    const: socionext,uniphier-mio-dmac

  reg:
    maxItems: 1

  interrupts:
    description: |
      A list of interrupt specifiers associated with the DMA channels.
      The number of interrupt lines is SoC-dependent.

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  '#dma-cells':
    description: The single cell represents the channel index.
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - '#dma-cells'

additionalProperties: false

examples:
  - |
    // In the example below, "interrupts = <0 68 4>, <0 68 4>, ..." is not a
    // typo. The first two channels share a single interrupt line.

    dmac: dma-controller@5a000000 {
        compatible = "socionext,uniphier-mio-dmac";
        reg = <0x5a000000 0x1000>;
        interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
                     <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
        clocks = <&mio_clk 7>;
        resets = <&mio_rst 7>;
        #dma-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/socionext,uniphier-xdmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier external DMA controller

description: |
  This describes the devicetree bindings for an external DMA engine to perform
  memory-to-memory or peripheral-to-memory data transfer capable of supporting
  16 channels, implemented in Socionext UniPhier SoCs.

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    const: socionext,uniphier-xdmac

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#dma-cells":
    const: 2
    description: |
      DMA request from clients consists of 2 cells:
        1. Channel index
        2. Transfer request factor number, If no transfer factor, use 0.
           The number is SoC-specific, and this should be specified with
           relation to the device to use the DMA controller.

  dma-channels:
    minimum: 1
    maximum: 16

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - "#dma-cells"
  - dma-channels

examples:
  - |
    xdmac: dma-controller@5fc10000 {
        compatible = "socionext,uniphier-xdmac";
        reg = <0x5fc10000 0x5300>;
        interrupts = <0 188 4>;
        #dma-cells = <2>;
        dma-channels = <16>;
    };

...


code:
* Spreadtrum DMA controller

This binding follows the generic DMA bindings defined in dma.txt.

Required properties:
- compatible: Should be "sprd,sc9860-dma".
- reg: Should contain DMA registers location and length.
- interrupts: Should contain one interrupt shared by all channel.
- #dma-cells: must be <1>. Used to represent the number of integer
	cells in the dmas property of client device.
- dma-channels : Number of DMA channels supported. Should be 32.
- clock-names: Should contain the clock of the DMA controller.
- clocks: Should contain a clock specifier for each entry in clock-names.

Deprecated properties:
- #dma-channels : Number of DMA channels supported. Should be 32.

Example:

Controller:
apdma: dma-controller@20100000 {
	compatible = "sprd,sc9860-dma";
	reg = <0x20100000 0x4000>;
	interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	dma-channels = <32>;
	clock-names = "enable";
	clocks = <&clk_ap_ahb_gates 5>;
};

Client:
DMA clients connected to the Spreadtrum DMA controller must use the format
described in the dma.txt file, using a two-cell specifier for each channel.
The two cells in order are:
1. A phandle pointing to the DMA controller.
2. The slave id.

spi0: spi@70a00000{
	...
	dma-names = "rx_chn", "tx_chn";
	dmas = <&apdma 11>, <&apdma 12>;
	...
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 DMA Controller bindings

description: |
  The STM32 DMA is a general-purpose direct memory access controller capable of
  supporting 8 independent DMA channels. Each channel can have up to 8 requests.
  DMA clients connected to the STM32 DMA controller must use the format
  described in the dma.txt file, using a four-cell specifier for each
  channel: a phandle to the DMA controller plus the following four integer cells:
    1. The channel id
    2. The request line number
    3. A 32bit mask specifying the DMA channel configuration which are device
      dependent:
        -bit 9: Peripheral Increment Address
          0x0: no address increment between transfers
          0x1: increment address between transfers
        -bit 10: Memory Increment Address
          0x0: no address increment between transfers
          0x1: increment address between transfers
        -bit 15: Peripheral Increment Offset Size
          0x0: offset size is linked to the peripheral bus width
          0x1: offset size is fixed to 4 (32-bit alignment)
        -bit 16-17: Priority level
          0x0: low
          0x1: medium
          0x2: high
          0x3: very high
    4. A 32bit bitfield value specifying DMA features which are device dependent:
       -bit 0-1: DMA FIFO threshold selection
         0x0: 1/4 full FIFO
         0x1: 1/2 full FIFO
         0x2: 3/4 full FIFO
         0x3: full FIFO
       -bit 2: DMA direct mode
         0x0: FIFO mode with threshold selectable with bit 0-1
         0x1: Direct mode: each DMA request immediately initiates a transfer
              from/to the memory, FIFO is bypassed.
       -bit 4: alternative DMA request/acknowledge protocol
         0x0: Use standard DMA ACK management, where ACK signal is maintained
              up to the removal of request and transfer completion
         0x1: Use alternative DMA ACK management, where ACK de-assertion does
              not wait for the de-assertion of the REQuest, ACK is only managed
              by transfer completion. This must only be used on channels
              managing transfers for STM32 USART/UART.

maintainers:
  - Amelie Delaunay <amelie.delaunay@foss.st.com>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  "#dma-cells":
    const: 4

  compatible:
    const: st,stm32-dma

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 8
    description: Should contain all of the per-channel DMA
      interrupts in ascending order with respect to the
      DMA channel index.

  resets:
    maxItems: 1

  st,mem2mem:
    $ref: /schemas/types.yaml#/definitions/flag
    description: if defined, it indicates that the controller
      supports memory-to-memory transfer

required:
  - compatible
  - reg
  - clocks
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    dma-controller@40026400 {
      compatible = "st,stm32-dma";
      reg = <0x40026400 0x400>;
      interrupts = <56>,
                   <57>,
                   <58>,
                   <59>,
                   <60>,
                   <68>,
                   <69>,
                   <70>;
      clocks = <&clk_hclk>;
      #dma-cells = <4>;
      st,mem2mem;
      resets = <&rcc 150>;
      dma-requests = <8>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/st,stm32-dmamux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 DMA MUX (DMA request router) bindings

maintainers:
  - Amelie Delaunay <amelie.delaunay@foss.st.com>

allOf:
  - $ref: "dma-router.yaml#"

properties:
  "#dma-cells":
    const: 3

  compatible:
    const: st,stm32h7-dmamux

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - dma-masters

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    dma-router@40020800 {
      compatible = "st,stm32h7-dmamux";
      reg = <0x40020800 0x3c>;
      #dma-cells = <3>;
      dma-requests = <128>;
      dma-channels = <16>;
      dma-masters = <&dma1>, <&dma2>;
      clocks = <&timer_clk>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 MDMA Controller bindings

description: |
  The STM32 MDMA is a general-purpose direct memory access controller capable of
  supporting 64 independent DMA channels with 256 HW requests.
  DMA clients connected to the STM32 MDMA controller must use the format
  described in the dma.txt file, using a five-cell specifier for each channel:
  a phandle to the MDMA controller plus the following five integer cells:
    1. The request line number
    2. The priority level
      0x0: Low
      0x1: Medium
      0x2: High
      0x3: Very high
    3. A 32bit mask specifying the DMA channel configuration
      -bit 0-1: Source increment mode
        0x0: Source address pointer is fixed
        0x2: Source address pointer is incremented after each data transfer
        0x3: Source address pointer is decremented after each data transfer
      -bit 2-3: Destination increment mode
        0x0: Destination address pointer is fixed
        0x2: Destination address pointer is incremented after each data transfer
        0x3: Destination address pointer is decremented after each data transfer
      -bit 8-9: Source increment offset size
        0x0: byte (8bit)
        0x1: half-word (16bit)
        0x2: word (32bit)
        0x3: double-word (64bit)
      -bit 10-11: Destination increment offset size
        0x0: byte (8bit)
        0x1: half-word (16bit)
        0x2: word (32bit)
        0x3: double-word (64bit)
      -bit 25-18: The number of bytes to be transferred in a single transfer
                  (min = 1 byte, max = 128 bytes)
      -bit 29:28: Trigger Mode
        0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
        0x1: Each MDMA request triggers a block transfer (max 64K bytes)
        0x2: Each MDMA request triggers a repeated block transfer
        0x3: Each MDMA request triggers a linked list transfer
    4. A 32bit value specifying the register to be used to acknowledge the request
       if no HW ack signal is used by the MDMA client
    5. A 32bit mask specifying the value to be written to acknowledge the request
       if no HW ack signal is used by the MDMA client

maintainers:
  - Amelie Delaunay <amelie.delaunay@foss.st.com>

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  "#dma-cells":
    const: 5

  compatible:
    const: st,stm32h7-mdma

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  resets:
    maxItems: 1

  st,ahb-addr-masks:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: Array of u32 mask to list memory devices addressed via AHB bus.

required:
  - compatible
  - reg
  - clocks
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    dma-controller@52000000 {
      compatible = "st,stm32h7-mdma";
      reg = <0x52000000 0x1000>;
      interrupts = <122>;
      clocks = <&timer_clk>;
      resets = <&rcc 992>;
      #dma-cells = <5>;
      dma-channels = <16>;
      dma-requests = <32>;
      st,ahb-addr-masks = <0x20000000>, <0x00000000>;
    };

...


code:
* STMicroelectronics Flexible Direct Memory Access Device Tree bindings

The FDMA is a general-purpose direct memory access controller capable of
supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
The FDMA is based on a Slim processor which requires a firmware.

* FDMA Controller

Required properties:
- compatible	: Should be one of
		 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
		 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
		 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
- reg		: Should contain an entry for each name in reg-names
- reg-names	: Must contain "slimcore", "dmem", "peripherals", "imem" entries
- interrupts	: Should contain one interrupt shared by all channels
- dma-channels	: Number of channels supported by the controller
- #dma-cells	: Must be <3>. See DMA client section below
- clocks	: Must contain an entry for each clock
See: Documentation/devicetree/bindings/clock/clock-bindings.txt

Example:

	fdma0: dma-controller@8e20000 {
		compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
		reg = <0x8e20000 0x8000>,
		      <0x8e30000 0x3000>,
		      <0x8e37000 0x1000>,
		      <0x8e38000 0x8000>;
		reg-names = "slimcore", "dmem", "peripherals", "imem";
		clocks = <&clk_s_c0_flexgen CLK_FDMA>,
			 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
			 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
			 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
		dma-channels = <16>;
		#dma-cells = <3>;
	};

* DMA client

Required properties:
- dmas: Comma separated list of dma channel requests
- dma-names: Names of the aforementioned requested channels

Each dmas request consists of 4 cells:
1. A phandle pointing to the FDMA controller
2. The request line number
3. A 32bit mask specifying (see include/linux/platform_data/dma-st-fdma.h)
 -bit 2-0: Holdoff value, dreq will be masked for
	0x0: 0-0.5us
	0x1: 0.5-1us
	0x2: 1-1.5us
 -bit 17: data swap
	0x0: disabled
	0x1: enabled
 -bit 21: Increment Address
	0x0: no address increment between transfers
	0x1: increment address between transfers
 -bit 22: 2 STBus Initiator Coprocessor interface
	0x0: high priority port
	0x1: low priority port
4. transfers type
 0 free running
 1 paced

Example:

	sti_uni_player2: sti-uni-player@2 {
		compatible = "st,sti-uni-player";
		#sound-dai-cells = <0>;
		st,syscfg = <&syscfg_core>;
		clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
		assigned-clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
		assigned-clock-parents = <&clk_s_d0_quadfs 2>;
		assigned-clock-rates = <50000000>;
		reg = <0x8D82000 0x158>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
		dmas = <&fdma0 4 0 1>;
		dai-name = "Uni Player #1 (DAC)";
		dma-names = "tx";
		st,uniperiph-id = <2>;
		st,version = <5>;
		st,mode = "PCM";
	};