code:
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
 * Copyright (C) 2016 Amarula Solutions B.V.
 * Copyright (C) 2016 Engicam S.r.l.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6ul.dtsi"

/ {
	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	chosen {
		stdout-path = &uart1;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm8 0 100000>;
		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <100>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "imx6ul-isiot-sgtl5000";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,widgets =
			"Microphone", "Mic Jack",
			"Line", "Line In",
			"Line", "Line Out",
			"Headphone", "Headphone Jack";
		simple-audio-card,routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};

		dailink_master: simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
			clocks = <&clks IMX6UL_CLK_SAI2>;
		};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};
	};
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	status = "disabled";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	sgtl5000: codec@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		#sound-dai-cells = <0>;
		clocks = <&clks IMX6UL_CLK_OSC>;
		clock-names = "mclk";
		VDDA-supply = <&reg_3p3v>;
		VDDIO-supply = <&reg_3p3v>;
		VDDD-supply = <&reg_1p8v>;
	};

	stmpe811: gpio-expander@44 {
		compatible = "st,stmpe811";
		reg = <0x44>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_stmpe>;
		interrupt-parent = <&gpio1>;
		interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;

		stmpe: touchscreen {
			compatible = "st,stmpe-ts";
			st,sample-time = <4>;
			st,mod-12b = <1>;
			st,ref-sel = <0>;
			st,adc-freq = <1>;
			st,ave-ctrl = <1>;
			st,touch-det-delay = <2>;
			st,settling = <2>;
			st,fraction-z = <7>;
			st,i-drive = <1>;
		};
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat
		     &pinctrl_lcdif_ctrl>;
	display = <&display0>;
	status = "okay";

	display0: display0 {
		bits-per-pixel = <16>;
		bus-width = <18>;

		display-timings {
			native-mode = <&timing0>;
			timing0: timing0 {
				clock-frequency = <28000000>;
				hactive = <800>;
				vactive = <480>;
				hfront-porch = <30>;
				hback-porch = <30>;
				hsync-len = <64>;
				vback-porch = <5>;
				vfront-porch = <5>;
				vsync-len = <20>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};
	};
};

&pwm8 {
	#pwm-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm8>;
	status = "okay";
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	no-1-8-v;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
	bus-width = <8>;
	no-1-8-v;
	status = "disabled";
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC	0x1b0b0
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x1b0b0
		>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
			MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
			MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
		>;
	};

	pinctrl_lcdif_ctrl: lcdifctrlgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
		>;
	};

	pinctrl_lcdif_dat: lcdifdatgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
		>;
	};

	pinctrl_pwm8: pwm8grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_ER__PWM8_OUT   0x110b0
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x130b0
			MX6UL_PAD_JTAG_TMS__CCM_CLKO1		0x4001b031
			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x120b0
		>;
	};

	pinctrl_stmpe: stmpegrp  {
		fsl,pins = <
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017 exceet electronics GmbH
 * Copyright (C) 2018 Kontron Electronics GmbH
 * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
 */

#include "imx6ul-kontron-bl.dts"

/ {
	model = "Kontron BL i.MX6UL 43 (N631X S 43)";
	compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul",
		     "kontron,sl-imx6ul", "fsl,imx6ul";

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm7 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
		status = "okay";
	};
};

&i2c4 {
	touchscreen@5d {
		compatible = "goodix,gt928";
		reg = <0x5d>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_cap_touch>;
		interrupt-parent = <&gpio5>;
		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
		reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
		irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
	};
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
	/* Leave status disabled because of missing display panel node */
};

&pwm7 {
	#pwm-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm7>;
	status = "okay";
};

&iomuxc {
	pinctrl_cap_touch: captouchgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x1b0b0 /* Touch Interrupt */
			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x1b0b0 /* Touch Reset */
			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x1b0b0 /* Touch Wake */
		>;
	};

	pinctrl_lcdif_ctrl: lcdifctrlgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x79
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x79
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x79
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x79
			MX6UL_PAD_LCD_RESET__LCDIF_RESET	0x79
		>;
	};

	pinctrl_lcdif_dat: lcdifdatgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00	0x79
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01	0x79
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x79
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x79
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x79
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x79
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x79
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x79
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08	0x79
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09	0x79
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x79
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x79
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x79
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x79
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x79
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x79
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16	0x79
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17	0x79
			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x79
			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x79
			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x79
			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x79
			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x79
			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x79
		>;
	};

	pinctrl_pwm7: pwm7grp {
		fsl,pins = <
			MX6UL_PAD_CSI_VSYNC__PWM7_OUT		0x110b0
		>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017 exceet electronics GmbH
 * Copyright (C) 2018 Kontron Electronics GmbH
 * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
 */

#include <dt-bindings/gpio/gpio.h>

/ {
	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led1 {
			label = "debug-led1";
			gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
			default-state = "off";
			linux,default-trigger = "heartbeat";
		};

		led2 {
			label = "debug-led2";
			gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led3 {
			label = "debug-led3";
			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};

	pwm-beeper {
		compatible = "pwm-beeper";
		pwms = <&pwm8 0 5000>;
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_5v: regulator-5v {
		compatible = "regulator-fixed";
		regulator-name = "5v";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb_otg1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_vref_adc: regulator-vref-adc {
		compatible = "regulator-fixed";
		regulator-name = "vref-adc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&adc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc1>;
	vref-supply = <&reg_vref_adc>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "okay";
};

&ecspi1 {
	cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	status = "okay";

	eeprom@0 {
		compatible = "anvo,anv32e61w", "atmel,at25";
		reg = <0>;
		spi-max-frequency = <20000000>;
		spi-cpha;
		spi-cpol;
		pagesize = <1>;
		size = <8192>;
		address-width = <16>;
	};
};

&fec1 {
	pinctrl-0 = <&pinctrl_enet1>;
	/delete-node/ mdio;
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
	phy-mode = "rmii";
	phy-handle = <&ethphy2>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			reg = <1>;
			micrel,led-mode = <0>;
			clocks = <&clks IMX6UL_CLK_ENET_REF>;
			clock-names = "rmii-ref";
		};

		ethphy2: ethernet-phy@2 {
			reg = <2>;
			micrel,led-mode = <0>;
			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
			clock-names = "rmii-ref";
		};
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	rtc@32 {
		compatible = "epson,rx8900";
		reg = <0x32>;
	};
};

&pwm8 {
	#pwm-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm8>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	linux,rs485-enabled-at-boot-time;
	rs485-rx-during-tx;
	rs485-rts-active-low;
	uart-has-rtscts;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	dr_mode = "otg";
	srp-disable;
	hnp-disable;
	adp-disable;
	over-current-active-low;
	vbus-supply = <&reg_usb_otg1_vbus>;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	vbus-supply = <&reg_5v>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&reg_3v3>;
	voltage-ranges = <3300 3300>;
	no-1-8-v;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	non-removable;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&reg_3v3>;
	voltage-ranges = <3300 3300>;
	no-1-8-v;
	status = "okay";
};

&iomuxc {
	pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;

	pinctrl_adc1: adc1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
			MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0xb0
		>;
	};

	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA07__ECSPI1_MISO	0x100b1
			MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI	0x100b1
			MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK	0x100b1
			MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x100b1	/* ECSPI1-CS1 */
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b009
		>;
	};

	pinctrl_enet2_mdio: enet2mdiogrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
		>;
	};

	pinctrl_flexcan2: flexcan2grp{
		fsl,pins = <
			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
		>;
	};

	pinctrl_gpio: gpiogrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0	/* DOUT1 */
			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x1b0b0	/* DIN1 */
			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x1b0b0	/* DOUT2 */
			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0b0	/* DIN2 */
		>;
	};

	pinctrl_gpio_leds: gpioledsgrp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30	0x1b0b0	/* LED H14 */
			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x1b0b0	/* LED H15 */
			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0	/* LED H16 */
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX6UL_PAD_UART2_TX_DATA__I2C4_SCL	0x4001f8b0
			MX6UL_PAD_UART2_RX_DATA__I2C4_SDA	0x4001f8b0
		>;
	};

	pinctrl_pwm8: pwm8grp {
		fsl,pins = <
			MX6UL_PAD_CSI_HSYNC__PWM8_OUT		0x110b0
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_DATA04__UART2_DCE_TX	0x1b0b1
			MX6UL_PAD_NAND_DATA05__UART2_DCE_RX	0x1b0b1
			MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS	0x1b0b1
			/*
			 * mux unused RTS to make sure it doesn't cause
			 * any interrupts when it is undefined
			 */
			MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS	0x1b0b1
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b1
			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b0b1
			MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS	0x1b0b1
			MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS	0x1b0b1
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX	0x1b0b1
			MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_usbotg1: usbotg1 {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0x1b0b0
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x100b1	/* SD1_CD */
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10059
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100b9
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170b9
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170b9
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170b9
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170b9
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170b9
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100f9
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170f9
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170f9
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170f9
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170f9
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170f9
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017 exceet electronics GmbH
 * Copyright (C) 2018 Kontron Electronics GmbH
 * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
 */

/dts-v1/;

#include "imx6ul-kontron-sl.dtsi"
#include "imx6ul-kontron-bl-common.dtsi"

/ {
	model = "Kontron BL i.MX6UL (N631X S)";
	compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017 exceet electronics GmbH
 * Copyright (C) 2018 Kontron Electronics GmbH
 * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
 */

#include <dt-bindings/gpio/gpio.h>

/ {
	chosen {
		stdout-path = &uart4;
	};

	memory@80000000 {
		reg = <0x80000000 0x10000000>;
		device_type = "memory";
	};
};

&ecspi2 {
	cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	status = "okay";

	flash@0 {
		compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
		spi-max-frequency = <50000000>;
		reg = <0>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			reg = <1>;
			micrel,led-mode = <0>;
			clocks = <&clks IMX6UL_CLK_ENET_REF>;
			clock-names = "rmii-ref";
		};
	};
};

&fec2 {
	phy-mode = "rmii";
	status = "disabled";
};

&qspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	status = "okay";

	spi-flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spi-nand";
		spi-max-frequency = <104000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		reg = <0>;
	};
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_reset_out>;

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA03__ECSPI2_MISO      0x100b1
			MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI      0x100b1
			MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK      0x100b1
			MX6UL_PAD_CSI_DATA01__GPIO4_IO22       0x100b1
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b009
		>;
	};

	pinctrl_enet1_mdio: enet1mdiogrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
		>;
	};

	pinctrl_qspi: qspigrp {
		fsl,pins = <
			MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
			MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
			MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
			MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
			MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
			MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
		>;
	};

	pinctrl_reset_out: rstoutgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x1b0b0
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY    0x18b0
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017 exceet electronics GmbH
 * Copyright (C) 2018 Kontron Electronics GmbH
 * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
 */

#include "imx6ul.dtsi"
#include "imx6ul-kontron-sl-common.dtsi"

/ {
	model = "Kontron SL i.MX6UL (N631X SOM)";
	compatible = "kontron,sl-imx6ul", "fsl,imx6ul";
};


code:
/*
 * Copyright 2016 Grinn
 *
 * Author: Marcin Niestroj <m.niestroj@grinn-global.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include "imx6ul-litesom.dtsi"

/ {
	model = "Grinn i.MX6UL liteBoard";
	compatible = "grinn,imx6ul-liteboard", "grinn,imx6ul-litesom",
		     "fsl,imx6ul";

	chosen {
		stdout-path = &uart1;
	};

	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
		regulator-name = "usb_otg1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio2 8 GPIO_ACTIVE_LOW>;
	};
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10071
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
		>;
	};

	pinctrl_usb_otg1_vbus: usb-otg1-vbus {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x79
		>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

&snvs_poweroff {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	dr_mode = "host";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	status = "okay";
};


code:
/*
 * Copyright 2016 Grinn
 *
 * Author: Marcin Niestroj <m.niestroj@grinn-global.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "imx6ul.dtsi"

/ {
	model = "Grinn i.MX6UL liteSOM";
	compatible = "grinn,imx6ul-litesom", "fsl,imx6ul";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};
};

&iomuxc {
	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK	    0x10069
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD	    0x17059
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B  0x17059
		>;
	};
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	no-1-8-v;
	non-removable;
	keep-power-in-suspend;
	wakeup-source;
	bus-width = <8>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2017 Armadeus Systems <support@armadeus.com>

#include "imx6ul.dtsi"
#include "imx6ul-imx6ull-opos6ul.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2017 Armadeus Systems <support@armadeus.com>

/dts-v1/;
#include "imx6ul-opos6ul.dtsi"
#include "imx6ul-imx6ull-opos6uldev.dtsi"

/ {
	model = "Armadeus Systems OPOS6UL SoM (i.MX6UL) on OPOS6ULDev board";
	compatible = "armadeus,imx6ul-opos6uldev", "armadeus,imx6ul-opos6ul", "fsl,imx6ul";
};

&iomuxc {
	pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_tamper_gpios>;

	pinctrl_tamper_gpios: tampergpiosgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x0b0b0
			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x0b0b0
			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x0b0b0
			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x0b0b0
			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x0b0b0
			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x0b0b0
			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x0b0b0
			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x0b0b0
		>;
	};

	pinctrl_usbotg2_vbus: usbotg2vbusgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x1b0b0
		>;
	};

	pinctrl_w1: w1grp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x0b0b0
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
 * Author: Christian Hemp <c.hemp@phytec.de>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>

/ {
	model = "PHYTEC phyCORE-i.MX6 UltraLite";
	compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";

	chosen {
		stdout-path = &uart1;
	};

	/*
	 * Set the minimum memory size here and
	 * let the bootloader set the real size.
	 */
	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x8000000>;
	};

	gpio_leds_som: leds {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpioleds_som>;
		compatible = "gpio-leds";

		phycore-green {
			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	status = "disabled";

	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			reg = <1>;
			interrupt-parent = <&gpio1>;
			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
			micrel,led-mode = <1>;
			clocks = <&clks IMX6UL_CLK_ENET_REF>;
			clock-names = "rmii-ref";
			status = "disabled";
		};
	};
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	status = "disabled";
};

&i2c1 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	clock-frequency = <100000>;
	status = "okay";

	eeprom@52 {
		compatible = "catalyst,24c32", "atmel,24c32";
		pagesize = <32>;
		reg = <0x52>;
	};
};

&snvs_poweroff {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	status = "disabled";
};

&wdog1 {
	fsl,suspend-in-wait;
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x10010
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x10010
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b010
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b010
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b010
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b010
			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0x17059
		>;
	};

	pinctrl_gpioleds_som: gpioledssomgrp {
		fsl,pins = <MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x0b0b0>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x0b0b1
			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x0b0b1
			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0x0b0b1
			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x0b000
			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x0b0b1
			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x0b0b1
			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x0b0b1
			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x0b0b1
			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x0b0b1
			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x0b0b1
			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x0b0b1
			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x0b0b1
			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x0b0b1
			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x0b0b1
			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x0b0b1
		>;
	};

	pinctrl_i2c1: i2cgrp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL	0x4001b8b0
			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA	0x4001b8b0
		>;
	};

	pinctrl_i2c1_gpio: i2cgpiogrp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28	0x4001b8b0
			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x4001b8b0
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170f9
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100f9
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170f9
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170f9
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170f9
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170f9
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170f9
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170f9
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170f9
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170f9
		>;
	};

};


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
 * Author: Yunus Bas <y.bas@phytec.de>
 */

/dts-v1/;
#include "imx6ul.dtsi"
#include "imx6ul-phytec-phycore-som.dtsi"
#include "imx6ul-phytec-segin.dtsi"
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
#include "imx6ul-phytec-segin-peb-av-02.dtsi"

/ {
	model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC";
	compatible = "phytec,imx6ul-pbacd10-emmc", "phytec,imx6ul-pbacd10",
		     "phytec,imx6ul-pcl063","fsl,imx6ul";
};

&adc1 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&ecspi3 {
	status = "okay";
};

&ethphy1 {
	status = "okay";
};

&ethphy2 {
	status = "okay";
};

&fec1 {
	status = "okay";
};

&fec2 {
	status = "okay";
};

&i2c_rtc {
	status = "okay";
};

&reg_can1_en {
	status = "okay";
};

&reg_sound_1v8 {
	status = "okay";
};

&reg_sound_3v3 {
	status = "okay";
};

&sai2 {
	status = "okay";
};

&sound {
	status = "okay";
};

&tlv320 {
	status = "okay";
};

&uart5 {
	status = "okay";
};

&usbotg1 {
	status = "okay";
};

&usbotg2 {
	status = "okay";
};

&usdhc1 {
	status = "okay";
};

&usdhc2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
 * Author: Christian Hemp <c.hemp@phytec.de>
 */

/dts-v1/;
#include "imx6ul.dtsi"
#include "imx6ul-phytec-phycore-som.dtsi"
#include "imx6ul-phytec-segin.dtsi"
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
#include "imx6ul-phytec-segin-peb-av-02.dtsi"
#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"

/ {
	model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
	compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10",
		     "phytec,imx6ul-pcl063", "fsl,imx6ul";
};

&adc1 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&tlv320 {
	status = "okay";
};

&ecspi3 {
	status = "okay";
};

&ethphy1 {
	status = "okay";
};

&ethphy2 {
	status = "okay";
};

&fec1 {
	status = "okay";
};

&fec2 {
	status = "okay";
};

&gpmi {
	status = "okay";
};

&i2c_rtc {
	status = "okay";
};

&reg_can1_en {
	status = "okay";
};

&reg_sound_1v8 {
	status = "okay";
};

&reg_sound_3v3 {
	status = "okay";
};

&sai2 {
	status = "okay";
};

&sound {
	status = "okay";
};

&uart5 {
	status = "okay";
};

&usbotg1 {
	status = "okay";
};

&usbotg2 {
	status = "okay";
};

&usdhc1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright (C) 2016, 2020 PHYTEC Messtechnik
 * Author: Christian Hemp <c.hemp@phytec.de>
 * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
 */

/ {
	backlight_lcd: backlight-lcd {
		compatible = "pwm-backlight";
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <5>;
		power-supply = <&reg_backlight_en>;
		pwms = <&pwm3 0 5000000 0>;
		status = "disabled";
	};

	lcd_panel: lcd-panel {
		compatible = "edt,etm0700g0edh6";
		backlight = <&backlight_lcd>;
		status = "disabled";

		port {
			lcd_panel_in: endpoint {
				remote-endpoint = <&lcdif_parallel_out>;
			};
		};
	};

	reg_backlight_en: regulator-backlight-en {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_backlight_en>;
		regulator-name = "backlight-lcd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&i2c1 {
	edt_ft5406: touchscreen@38 {
		compatible = "edt,edt-ft5406";
		reg = <0x38>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_edt_ft5406>;
		interrupt-parent = <&gpio5>;
		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
		wakeup-source;
		status = "disabled";
	};

	stmpe: touchscreen@44 {
		compatible = "st,stmpe811";
		reg = <0x44>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_stmpe>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
		interrupt-parent = <&gpio5>;
		wakeup-source;
		status = "disabled";

		stmpe_touchscreen {
			compatible = "st,stmpe-ts";
			st,sample-time = <4>;
			st,mod-12b = <1>;
			st,ref-sel = <0>;
			st,adc-freq = <1>;
			st,ave-ctrl = <1>;
			st,touch-det-delay = <2>;
			st,settling = <2>;
			st,fraction-z = <7>;
			st,i-drive = <1>;
			touchscreen-inverted-x;
			touchscreen-inverted-y;
		};
	};
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat>;
	status = "disabled";

	port {
		lcdif_parallel_out: endpoint {
			remote-endpoint = <&lcd_panel_in>;
		};
	};
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "disabled";
};

&iomuxc {
	pinctrl_edt_ft5406: edtft5406grp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0
		>;
	};

	pinctrl_backlight_en: bachlightengrp {
		fsl,pins = <
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x1b0b0
		>;
	};

	pinctrl_lcdif_dat: lcdifdatgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x59
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x59
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x59
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x59
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x59
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x59
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x59
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x59
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x59
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x59
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x59
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x59
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x59
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x59
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x59
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x59
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x59
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x59
			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x59
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x59
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x59
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x59
		>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO04__PWM3_OUT	0x0b0b0
		>;
	};

	pinctrl_stmpe: stmpegrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x17059
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2016 PHYTEC Messtechnik
 * Author: Christian Hemp <c.hemp@phytec.de>
 */

#include <dt-bindings/input/input.h>

/ {
	gpio_keys: gpio-keys {
		compatible = "gpio-key";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;
		status = "disabled";

		power {
			label = "Power Button";
			gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_POWER>;
			wakeup-source;
		};
	};

	user_leds: user-leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_user_leds>;
		status = "disabled";

		user-led1 {
			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "gpio";
			default-state = "on";
		};

		user-led2 {
			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "gpio";
			default-state = "on";
		};
	};
};

&iomuxc {
	pinctrl_gpio_keys: gpio_keysgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x79
		>;
	};

	pinctrl_user_leds: user_ledsgrp {
		fsl,pins = <
			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x79
			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0x79
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2021 PHYTEC Messtechnik GmbH
 * Author: Yunus Bas <y.bas@phytec.de>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	reg_wl_en: regulator-wl-en {
		compatible = "regulator-fixed";
		regulator-name = "wlan_en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_wl>;
		gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
		status = "disabled";
	};
};

&iomuxc {
	pinctrl_bt: btgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0x3031	/* BT ENABLE */
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x3031	/* HOST WAKEUP */
			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x3031	/* DEV WAKEUP */
		>;
	};

	pinctrl_uart2_bt: uart2grp-bt {
		fsl,pins = <
			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x17059
			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x17059
			MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS    0x17059
			MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS    0x17059
		>;
	};

	pinctrl_usdhc2_wl: usdhc2grp-wl {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA18__USDHC2_CMD    0x10051
			MX6UL_PAD_LCD_DATA19__USDHC2_CLK    0x10061
			MX6UL_PAD_LCD_DATA20__USDHC2_DATA0  0x10051
			MX6UL_PAD_LCD_DATA21__USDHC2_DATA1  0x10051
			MX6UL_PAD_LCD_DATA22__USDHC2_DATA2  0x10051
			MX6UL_PAD_LCD_DATA23__USDHC2_DATA3  0x10051
		>;
	};

	pinctrl_wl: wlgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x3031	/* WLAN ENABLE */
		>;
	};
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2_bt &pinctrl_bt>;
	uart-has-rtscts;
	status = "disabled";

	bluetooth {
		compatible = "brcm,bcm43438-bt";
		shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
		device-wakeup-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
		host-wakeup-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
	};
};

&usdhc2 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2_wl>;
	vmmc-supply = <&reg_wl_en>;
	bus-width = <4>;
	non-removable;
	no-1-8-v;
	status = "disabled";

	brmcf: wifi@1 {
		compatible = "brcm,bcm4329-fmac";
		reg = <1>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
 * Author: Christian Hemp <c.hemp@phytec.de>
 */

/ {
	model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite";
	compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";

	aliases {
		rtc0 = &i2c_rtc;
		rtc1 = &snvs_rtc;
	};

	reg_sound_1v8: regulator-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "i2s-audio-1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		status = "disabled";
	};

	reg_sound_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "i2s-audio-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		status = "disabled";
	};

	reg_can1_en: regulator-can1 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&princtrl_flexcan1_en>;
		regulator-name = "Can";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		status = "disabled";
	};

	reg_adc1_vref_3v3: regulator-vref-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vref-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	sound: sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,widgets =
			"Line", "Line In",
			"Line", "Line Out",
			"Speaker", "Speaker";
		simple-audio-card,routing =
			"Line Out", "LLOUT",
			"Line Out", "RLOUT",
			"Speaker", "SPOP",
			"Speaker", "SPOM",
			"LINE1L", "Line In",
			"LINE1R", "Line In";
		status = "disabled";

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};

		dailink_master: simple-audio-card,codec {
			sound-dai = <&tlv320>;
			clocks = <&clks IMX6UL_CLK_SAI2>;
		};
	};

};

&adc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc1>;
	vref-supply = <&reg_adc1_vref_3v3>;
	status = "disabled";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can1_en>;
	status = "disabled";
};

&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <786432000>;
};

&ecspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
	status = "disabled";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rmii";
	phy-handle = <&ethphy2>;
	status = "disabled";
};

&i2c1 {
	tlv320: codec@18 {
		compatible = "ti,tlv320aic3007";
		#sound-dai-cells = <0>;
		reg = <0x18>;
		AVDD-supply = <&reg_sound_3v3>;
		IOVDD-supply = <&reg_sound_3v3>;
		DRVDD-supply = <&reg_sound_3v3>;
		DVDD-supply = <&reg_sound_1v8>;
		status = "disabled";
	};

	i2c_rtc: rtc@68 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_rtc_int>;
		compatible = "microcrystal,rv4162";
		reg = <0x68>;
		interrupt-parent = <&gpio5>;
		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
		status = "disabled";
	};
};

&mdio {
	ethphy2: ethernet-phy@2 {
		reg = <2>;
		micrel,led-mode = <1>;
		clocks = <&clks IMX6UL_CLK_ENET2_REF>;
		clock-names = "rmii-ref";
		status = "disabled";
	};
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
			<&clks IMX6UL_CLK_SAI2>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <0>, <19200000>;
	fsl,sai-mclk-direction-output;
	status = "disabled";
};

&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	uart-has-rtscts;
	status = "disabled";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1_id>;
	dr_mode = "otg";
	status = "disabled";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "disabled";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	disable-wp;
	status = "disabled";
};

&iomuxc {
	pinctrl_adc1: adc1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
		>;
	};

	pinctrl_ecspi3: ecspi3grp {
		fsl,pins = <
			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0
			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0
			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0
			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x10b0
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b010
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b010
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b010
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b010
		>;
	};

	pinctrl_flexcan1: flexcan1 {
		fsl,pins = <
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x0b0b0
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x0b0b0
		>;
	};

	princtrl_flexcan1_en: flexcan1engrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x17059
		>;
	};

	pinctrl_rtc_int: rtcintgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x17059
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
		>;
	};

	pinctrl_uart5: uart5grp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0b1
			MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX	0x1b0b1
			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
		>;
	};

	pinctrl_usb_otg1_id: usbotg1idgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2015 Technexion Ltd.
//
// Author: Wig Cheng  <wig.cheng@technexion.com>
//	   Richard Hu <richard.hu@technexion.com>
//	   Tapani Utriainen <tapani@technexion.com>
/dts-v1/;

#include "imx6ul-pico.dtsi"
/ {
	model = "TechNexion PICO-IMX6UL and DWARF baseboard";
	compatible = "technexion,imx6ul-pico-dwarf", "fsl,imx6ul";

	sound {
		compatible = "fsl,imx-audio-sgtl5000";
		model = "imx6ul-sgtl5000";
		audio-cpu = <&sai1>;
		audio-codec = <&sgtl5000>;
		audio-routing =
			"LINE_IN", "Line In Jack",
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
	};

	sys_mclk: clock-sys-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};
};

&i2c2 {
	clock_frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	sgtl5000: audio-codec@a {
		reg = <0x0a>;
		compatible = "fsl,sgtl5000";
		clocks = <&sys_mclk>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
	};

	pressure-sensor@60 {
		compatible = "fsl,mpl3115";
		reg = <0x60>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2015 Technexion Ltd.
//
// Author: Wig Cheng  <wig.cheng@technexion.com>
//	   Richard Hu <richard.hu@technexion.com>
//	   Tapani Utriainen <tapani@technexion.com>
/dts-v1/;

#include "imx6ul-pico.dtsi"
/ {
	model = "TechNexion PICO-IMX6UL and HOBBIT baseboard";
	compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led {
			label = "gpio-led";
			gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
		};
	};

	sound {
		compatible = "fsl,imx-audio-sgtl5000";
		model = "imx6ul-sgtl5000";
		audio-cpu = <&sai1>;
		audio-codec = <&sgtl5000>;
		audio-routing =
			"LINE_IN", "Line In Jack",
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
	};

	sys_mclk: clock-sys-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	sgtl5000: codec@a {
		reg = <0x0a>;
		compatible = "fsl,sgtl5000";
		clocks = <&sys_mclk>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
	};
};

&i2c3 {
	status = "okay";

	polytouch: touchscreen@38 {
		compatible = "edt,edt-ft5x06";
		reg = <0x38>;
		interrupt-parent = <&gpio1>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
		reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
		touchscreen-size-x = <800>;
		touchscreen-size-y = <480>;
	};

	adc081c: adc@50 {
		compatible = "ti,adc081c";
		reg = <0x50>;
		vref-supply = <&reg_3p3v>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX6UL_PAD_CSI_VSYNC__GPIO4_IO19		0x10b0
			MX6UL_PAD_CSI_DATA00__GPIO4_IO21	0x10b0
			MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x10b0
			MX6UL_PAD_CSI_DATA02__GPIO4_IO23	0x10b0
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x10b0
			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x10b0
		>;
	};

	pinctrl_gpio_leds: gpioledsgrp {
		fsl,pins = <
			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x10b0
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2015 Technexion Ltd.
//
// Author: Wig Cheng  <wig.cheng@technexion.com>
//	   Richard Hu <richard.hu@technexion.com>
//	   Tapani Utriainen <tapani@technexion.com>
/dts-v1/;

#include "imx6ul-pico.dtsi"
/ {
	model = "TechNexion PICO-IMX6UL and PI baseboard";
	compatible = "technexion,imx6ul-pico-pi", "fsl,imx6ul";

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led {
			label = "gpio-led";
			gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
		};
	};

	sound {
		compatible = "fsl,imx-audio-sgtl5000";
		model = "imx6ul-sgtl5000";
		audio-cpu = <&sai1>;
		audio-codec = <&sgtl5000>;
		audio-routing =
			"LINE_IN", "Line In Jack",
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
	};

	sys_mclk: clock-sys-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	sgtl5000: codec@a {
		reg = <0x0a>;
		compatible = "fsl,sgtl5000";
		clocks = <&sys_mclk>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
	};
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	polytouch: touchscreen@38 {
		compatible = "edt,edt-ft5x06";
		reg = <0x38>;
		interrupt-parent = <&gpio1>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
		reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
		touchscreen-size-x = <800>;
		touchscreen-size-y = <480>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX6UL_PAD_CSI_VSYNC__GPIO4_IO19		0x10b0
			MX6UL_PAD_CSI_DATA00__GPIO4_IO21	0x10b0
			MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x10b0
			MX6UL_PAD_CSI_DATA02__GPIO4_IO23	0x10b0
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x10b0
			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x10b0
		>;
	};

	pinctrl_gpio_leds: gpioledsgrp {
		fsl,pins = <
			MX6UL_PAD_CSI_HSYNC__GPIO4_IO20		0x10b0
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2015 Technexion Ltd.
//
// Author: Wig Cheng  <wig.cheng@technexion.com>
//	   Richard Hu <richard.hu@technexion.com>
//	   Tapani Utriainen <tapani@technexion.com>
/dts-v1/;

#include "imx6ul.dtsi"

/ {
	/* Will be filled by the bootloader */
	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0>;
	};

	chosen {
		stdout-path = &uart6;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm3 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
		status = "okay";
	};

	reg_2p5v: regulator-2p5v {
		compatible = "regulator-fixed";
		regulator-name = "2P5V";
		regulator-min-microvolt = <2500000>;
		regulator-max-microvolt = <2500000>;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_sd1_vmmc: regulator-sd1-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usb_otg_vbus: regulator-usb-otg-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb_otg1>;
		regulator-name = "usb_otg_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 6 0>;
	};

	reg_brcm: regulator-brcm {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_brcm_reg>;
		regulator-name = "brcm_reg";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		startup-delay-us = <200000>;
	};

	panel {
		compatible = "vxt,vl050-8048nt-c01";
		backlight = <&backlight>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&display_out>;
			};
		};
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "okay";
};

&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <786432000>;
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	status = "okay";
	phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <1>;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			max-speed = <100>;
			interrupt-parent = <&gpio5>;
			interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
		};
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic: pfuze3000@8 {
		compatible = "fsl,pfuze3000";
		reg = <0x08>;

		regulators {
			/* VDD_ARM_SOC_IN*/
			sw1b_reg: sw1b {
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1475000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			/* DRAM */
			sw3a_reg: sw3 {
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1650000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* DRAM */
			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
	status = "okay";

	port {
		display_out: endpoint {
			remote-endpoint = <&panel_in>;
		};
	};
};

&pwm3 {
	#pwm-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
};

&pwm7 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm7>;
	status = "okay";
};

&pwm8 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm8>;
	status = "okay";
};

&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	status = "okay";
};

&uart6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart6>;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1_id>;
	dr_mode = "otg";
	disable-over-current;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	keep-power-in-suspend;
	status = "okay";
};

&usdhc2 {  /* Wifi SDIO */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	no-1-8-v;
	non-removable;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&reg_brcm>;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
};

&iomuxc {
	pinctrl_brcm_reg: brcmreggrp {
		fsl,pins = <
			MX6UL_PAD_NAND_DATA06__GPIO4_IO08	0x10b0	/* WL_REG_ON */
			MX6UL_PAD_NAND_DATA04__GPIO4_IO06	0x10b0	/* WL_HOST_WAKE */
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET2_MDC	0x1b0b0
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x800
			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28	0x79
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX	0x1b020
			MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX	0x1b020
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX	0x1b020
			MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX	0x1b020
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO02__I2C1_SCL		0x4001b8b0
			MX6UL_PAD_GPIO1_IO03__I2C1_SDA		0x4001b8b0
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001b8b0
			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001b8b0
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__I2C3_SCL	0x4001b8b0
			MX6UL_PAD_UART1_RX_DATA__I2C3_SDA	0x4001b8b0
			>;
	};

	pinctrl_lcdif_dat: lcdifdatgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00	0x79
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01	0x79
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x79
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x79
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x79
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x79
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x79
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x79
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08	0x79
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09	0x79
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x79
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x79
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x79
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x79
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x79
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x79
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16	0x79
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17	0x79
			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x79
			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x79
			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x79
			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x79
			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x79
			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x79
		>;
	};

	pinctrl_lcdif_ctrl: lcdifctrlgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x79
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x79
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x79
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x79
			/* LCD reset */
			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x79
		>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <
			MX6UL_PAD_NAND_ALE__PWM3_OUT		0x110b0
		>;
	};

	pinctrl_pwm7: pwm7grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT	0x110b0
		>;
	};

	pinctrl_pwm8: pwm8grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_ER__PWM8_OUT		0x110b0
		>;
	};

	pinctrl_sai1: sai1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC	0x1b0b0
			MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK	0x1b0b0
			MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA	0x110b0
			MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA	0x1f0b8
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b0
			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b0b0
			MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS	0x1b0b0
			MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS	0x1b0b0
		>;
	};

	pinctrl_uart5: uart5grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX	0x1b0b1
			MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX	0x1b0b1
			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
		>;
	};

	pinctrl_uart6: uart6grp {
		fsl,pins = <
			MX6UL_PAD_CSI_MCLK__UART6_DCE_TX	0x1b0b1
			MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_usb_otg1: usbotg1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO06__GPIO1_IO06	0x10b0
			>;
	};

	pinctrl_usb_otg1_id: usbotg1idgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10071
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
			MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B	0x03029
			MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
			MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
			MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
			MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10059
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
		>;
	};
};