code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Abilis Systems TB10X SOC device tree
 *
 * Copyright (C) Abilis Systems 2013
 *
 * Author: Christian Ruppert <christian.ruppert@abilis.com>
 */

/ {
	compatible		= "abilis,arc-tb10x";
	#address-cells		= <1>;
	#size-cells		= <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "snps,arc770d";
			reg = <0>;
		};
	};

	/* TIMER0 with interrupt for clockevent */
	timer0 {
		compatible = "snps,arc-timer";
		interrupts = <3>;
		interrupt-parent = <&intc>;
		clocks = <&cpu_clk>;
	};

	/* TIMER1 for free running clocksource */
	timer1 {
		compatible = "snps,arc-timer";
		clocks = <&cpu_clk>;
	};

	soc100 {
		#address-cells	= <1>;
		#size-cells	= <1>;
		device_type	= "soc";
		ranges		= <0xfe000000 0xfe000000 0x02000000
				0x000f0000 0x000f0000 0x00010000>;
		compatible	= "abilis,tb10x", "simple-bus";

		pll0: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-output-names = "pll0";
		};
		cpu_clk: clkdiv_cpu {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&pll0>;
			clock-output-names = "cpu_clk";
		};
		ahb_clk: clkdiv_ahb {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&pll0>;
			clock-output-names = "ahb_clk";
		};

		iomux: iomux@ff10601c {
			compatible = "abilis,tb10x-iomux";
			#gpio-range-cells = <3>;
			reg = <0xff10601c 0x4>;
		};

		intc: interrupt-controller {
			compatible = "snps,arc700-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};
		tb10x_ictl: pic@fe002000 {
			compatible = "abilis,tb10x-ictl";
			reg = <0xfe002000 0x20>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
					20 21 22 23 24 25 26 27 28 29 30 31>;
		};

		uart@ff100000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff100000 0x100>;
			clock-frequency = <166666666>;
			interrupts = <25 8>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupt-parent = <&tb10x_ictl>;
		};
		ethernet@fe100000 {
			compatible = "snps,dwmac-3.70a","snps,dwmac";
			reg = <0xfe100000 0x1058>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <6 8>;
			interrupt-names = "macirq";
			clocks = <&ahb_clk>;
			clock-names = "stmmaceth";
		};
		dma@fe000000 {
			compatible = "snps,dma-spear1340";
			reg = <0xfe000000 0x400>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <14 8>;
			dma-channels = <6>;
			dma-requests = <0>;
			dma-masters = <1>;
			#dma-cells = <3>;
			chan_allocation_order = <0>;
			chan_priority = <1>;
			block_size = <0x7ff>;
			data-width = <4>;
			clocks = <&ahb_clk>;
			clock-names = "hclk";
			multi-block = <1 1 1 1 1 1>;
		};

		i2c0: i2c@ff120000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xff120000 0x1000>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <12 8>;
			clocks = <&ahb_clk>;
		};
		i2c1: i2c@ff121000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xff121000 0x1000>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <12 8>;
			clocks = <&ahb_clk>;
		};
		i2c2: i2c@ff122000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xff122000 0x1000>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <12 8>;
			clocks = <&ahb_clk>;
		};
		i2c3: i2c@ff123000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xff123000 0x1000>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <12 8>;
			clocks = <&ahb_clk>;
		};
		i2c4: i2c@ff124000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xff124000 0x1000>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <12 8>;
			clocks = <&ahb_clk>;
		};

		spi0: spi@fe010000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "abilis,tb100-spi";
			num-cs = <1>;
			reg = <0xfe010000 0x20>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <26 8>;
			clocks = <&ahb_clk>;
		};
		spi1: spi@fe011000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "abilis,tb100-spi";
			num-cs = <2>;
			reg = <0xfe011000 0x20>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <10 8>;
			clocks = <&ahb_clk>;
		};

		tb10x_tsm: tb10x-tsm@ff316000 {
			compatible = "abilis,tb100-tsm";
			reg = <0xff316000 0x400>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <17 8>;
			output-clkdiv = <4>;
			global-packet-delay = <0x21>;
			port-packet-delay = <0>;
		};
		tb10x_stream_proc: tb10x-stream-proc {
			compatible = "abilis,tb100-streamproc";
			reg =   <0xfff00000 0x200>,
				<0x000f0000 0x10000>,
				<0xfff00200 0x105>,
				<0xff10600c 0x1>,
				<0xfe001018 0x1>;
			reg-names =     "mbox",
					"sp_iccm",
					"mbox_irq",
					"cpuctrl",
					"a6it_int_force";
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <20 2>, <19 2>;
			interrupt-names = "cmd_irq", "event_irq";
		};
		tb10x_mdsc0: tb10x-mdscr@ff300000 {
			compatible = "abilis,tb100-mdscr";
			reg = <0xff300000 0x7000>;
			tb100-mdscr-manage-tsin;
		};
		tb10x_mscr0: tb10x-mdscr@ff307000 {
			compatible = "abilis,tb100-mdscr";
			reg = <0xff307000 0x7000>;
		};
		tb10x_scr0: tb10x-mdscr@ff30e000 {
			compatible = "abilis,tb100-mdscr";
			reg = <0xff30e000 0x4000>;
			tb100-mdscr-manage-tsin;
		};
		tb10x_scr1: tb10x-mdscr@ff312000 {
			compatible = "abilis,tb100-mdscr";
			reg = <0xff312000 0x4000>;
			tb100-mdscr-manage-tsin;
		};
		tb10x_wfb: tb10x-wfb@ff319000 {
			compatible = "abilis,tb100-wfb";
			reg = <0xff319000 0x1000>;
			interrupt-parent = <&tb10x_ictl>;
			interrupts = <16 8>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
 */

/*
 * Device tree for AXC001 770D/EM6/AS221 CPU card
 * Note that this file only supports the 770D CPU
 */

/include/ "skeleton.dtsi"

/ {
	compatible = "snps,arc";
	#address-cells = <2>;
	#size-cells = <2>;

	cpu_card {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;

		core_clk: core_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <750000000>;
		};

		input_clk: input-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <33333333>;
		};

		core_intc: arc700-intc@cpu {
			compatible = "snps,arc700-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		/*
		 * this GPIO block ORs all interrupts on CPU card (creg,..)
		 * to uplink only 1 IRQ to ARC core intc
		 */
		dw-apb-gpio@2000 {
			compatible = "snps,dw-apb-gpio";
			reg = < 0x2000 0x80 >;
			#address-cells = <1>;
			#size-cells = <0>;

			ictl_intc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <30>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupt-parent = <&core_intc>;
				interrupts = <15>;
			};
		};

		debug_uart: dw-apb-uart@5000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x5000 0x100>;
			clock-frequency = <33333000>;
			interrupt-parent = <&ictl_intc>;
			interrupts = <19 4>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		arcpct0: pct {
			compatible = "snps,arc700-pct";
		};
	};

	/*
	 * This INTC is actually connected to DW APB GPIO
	 * which acts as a wire between MB INTC and CPU INTC.
	 * GPIO INTC is configured in platform init code
	 * and here we mimic direct connection from MB INTC to
	 * CPU INTC, thus we set "interrupts = <7>" instead of
	 * "interrupts = <12>"
	 *
	 * This intc actually resides on MB, but we move it here to
	 * avoid duplicating the MB dtsi file given that IRQ from
	 * this intc to cpu intc are different for axs101 and axs103
	 */
	mb_intc: interrupt-controller@e0012000 {
		#interrupt-cells = <1>;
		compatible = "snps,dw-apb-ictl";
		reg = < 0x0 0xe0012000 0x0 0x200 >;
		interrupt-controller;
		interrupt-parent = <&core_intc>;
		interrupts = < 7 >;
	};

	memory {
		device_type = "memory";
		/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
		reg = <0x0 0x80000000 0x0 0x1b000000>;	/* (512 - 32) MiB */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		/*
		 * We just move frame buffer area to the very end of
		 * available DDR. And even though in case of ARC770 there's
		 * no strict requirement for a frame-buffer to be in any
		 * particular location it allows us to use the same
		 * base board's DT node for ARC PGU as for ARc HS38.
		 */
		frame_buffer: frame_buffer@9e000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9e000000 0x0 0x2000000>;
			no-map;
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 */

/*
 * Device tree for AXC003 CPU card: HS38x UP configuration
 */

/include/ "skeleton_hs.dtsi"

/ {
	compatible = "snps,arc";
	#address-cells = <2>;
	#size-cells = <2>;

	cpu_card {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;

		input_clk: input-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <33333333>;
		};

		core_clk: core-clk@80 {
			compatible = "snps,axs10x-arc-pll-clock";
			reg = <0x80 0x10>, <0x100 0x10>;
			#clock-cells = <0>;
			clocks = <&input_clk>;

			/*
			 * Set initial core pll output frequency to 90MHz.
			 * It will be applied at the core pll driver probing
			 * on early boot.
			 */
			assigned-clocks = <&core_clk>;
			assigned-clock-rates = <90000000>;
		};

		core_intc: archs-intc@cpu {
			compatible = "snps,archs-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		/*
		 * this GPIO block ORs all interrupts on CPU card (creg,..)
		 * to uplink only 1 IRQ to ARC core intc
		 */
		dw-apb-gpio@2000 {
			compatible = "snps,dw-apb-gpio";
			reg = < 0x2000 0x80 >;
			#address-cells = <1>;
			#size-cells = <0>;

			ictl_intc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <30>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupt-parent = <&core_intc>;
				interrupts = <25>;
			};
		};

		debug_uart: dw-apb-uart@5000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x5000 0x100>;
			clock-frequency = <33333000>;
			interrupt-parent = <&ictl_intc>;
			interrupts = <2 4>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		arcpct0: pct {
			compatible = "snps,archs-pct";
			#interrupt-cells = <1>;
			interrupt-parent = <&core_intc>;
			interrupts = <20>;
		};
	};

	/*
	 * Mark DMA peripherals connected via IOC port as dma-coherent. We do
	 * it via overlay because peripherals defined in axs10x_mb.dtsi are
	 * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so
	 * only AXS103 board has HW-coherent DMA peripherals)
	 * We don't need to mark pgu@17000 as dma-coherent because it uses
	 * external DMA buffer located outside of IOC aperture.
	 */
	axs10x_mb {
		ethernet@18000 {
			dma-coherent;
		};

		usb@40000 {
			dma-coherent;
		};

		usb@60000 {
			dma-coherent;
		};

		mmc@15000 {
			dma-coherent;
		};
	};

	/*
	 * The DW APB ICTL intc on MB is connected to CPU intc via a
	 * DT "invisible" DW APB GPIO block, configured to simply pass thru
	 * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
	 *
	 * So here we mimic a direct connection betwen them, ignoring the
	 * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
	 * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
	 *
	 * This intc actually resides on MB, but we move it here to
	 * avoid duplicating the MB dtsi file given that IRQ from
	 * this intc to cpu intc are different for axs101 and axs103
	 */
	mb_intc: interrupt-controller@e0012000 {
		#interrupt-cells = <1>;
		compatible = "snps,dw-apb-ictl";
		reg = < 0x0 0xe0012000 0x0 0x200 >;
		interrupt-controller;
		interrupt-parent = <&core_intc>;
		interrupts = < 24 >;
	};

	memory {
		device_type = "memory";
		/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
		reg = <0x0 0x80000000 0x0 0x20000000	/* 512 MiB low mem */
		       0x1 0xc0000000 0x0 0x40000000>;	/* 1 GiB highmem */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		/*
		 * Move frame buffer out of IOC aperture (0x8z-0xaz).
		 */
		frame_buffer: frame_buffer@be000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xbe000000 0x0 0x2000000>;
			no-map;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
 */

/*
 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
 */

/include/ "skeleton_hs_idu.dtsi"

/ {
	compatible = "snps,arc";
	#address-cells = <2>;
	#size-cells = <2>;

	cpu_card {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;

		input_clk: input-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <33333333>;
		};

		core_clk: core-clk@80 {
			compatible = "snps,axs10x-arc-pll-clock";
			reg = <0x80 0x10>, <0x100 0x10>;
			#clock-cells = <0>;
			clocks = <&input_clk>;

			/*
			 * Set initial core pll output frequency to 100MHz.
			 * It will be applied at the core pll driver probing
			 * on early boot.
			 */
			assigned-clocks = <&core_clk>;
			assigned-clock-rates = <100000000>;
		};

		core_intc: archs-intc@cpu {
			compatible = "snps,archs-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		idu_intc: idu-interrupt-controller {
			compatible = "snps,archs-idu-intc";
			interrupt-controller;
			interrupt-parent = <&core_intc>;
			#interrupt-cells = <1>;
		};

		/*
		 * this GPIO block ORs all interrupts on CPU card (creg,..)
		 * to uplink only 1 IRQ to ARC core intc
		 */
		dw-apb-gpio@2000 {
			compatible = "snps,dw-apb-gpio";
			reg = < 0x2000 0x80 >;
			#address-cells = <1>;
			#size-cells = <0>;

			ictl_intc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <30>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupt-parent = <&idu_intc>;
				interrupts = <1>;
			};
		};

		debug_uart: dw-apb-uart@5000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x5000 0x100>;
			clock-frequency = <33333000>;
			interrupt-parent = <&ictl_intc>;
			interrupts = <2 4>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		arcpct0: pct {
			compatible = "snps,archs-pct";
			#interrupt-cells = <1>;
			interrupt-parent = <&core_intc>;
			interrupts = <20>;
		};
	};

	/*
	 * Mark DMA peripherals connected via IOC port as dma-coherent. We do
	 * it via overlay because peripherals defined in axs10x_mb.dtsi are
	 * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so
	 * only AXS103 board has HW-coherent DMA peripherals)
	 * We don't need to mark pgu@17000 as dma-coherent because it uses
	 * external DMA buffer located outside of IOC aperture.
	 */
	axs10x_mb {
		ethernet@18000 {
			dma-coherent;
		};

		usb@40000 {
			dma-coherent;
		};

		usb@60000 {
			dma-coherent;
		};

		mmc@15000 {
			dma-coherent;
		};
	};

	/*
	 * This INTC is actually connected to DW APB GPIO
	 * which acts as a wire between MB INTC and CPU INTC.
	 * GPIO INTC is configured in platform init code
	 * and here we mimic direct connection from MB INTC to
	 * CPU INTC, thus we set "interrupts = <0 1>" instead of
	 * "interrupts = <12>"
	 *
	 * This intc actually resides on MB, but we move it here to
	 * avoid duplicating the MB dtsi file given that IRQ from
	 * this intc to cpu intc are different for axs101 and axs103
	 */
	mb_intc: interrupt-controller@e0012000 {
		#interrupt-cells = <1>;
		compatible = "snps,dw-apb-ictl";
		reg = < 0x0 0xe0012000 0x0 0x200 >;
		interrupt-controller;
		interrupt-parent = <&idu_intc>;
		interrupts = <0>;
	};

	memory {
		device_type = "memory";
		/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
		reg = <0x0 0x80000000 0x0 0x20000000	/* 512 MiB low mem */
		       0x1 0xc0000000 0x0 0x40000000>;	/* 1 GiB highmem */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		/*
		 * Move frame buffer out of IOC aperture (0x8z-0xaz).
		 */
		frame_buffer: frame_buffer@be000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0xbe000000 0x0 0x2000000>;
			no-map;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
 *
 * ARC AXS101 S/W development platform
 */
/dts-v1/;

/include/ "axc001.dtsi"
/include/ "axs10x_mb.dtsi"

/ {
	model = "snps,axs101";
	compatible = "snps,axs101", "snps,arc-sdp";

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 print-fatal-signals=1";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 */

/*
 * Device Tree for AXS103 SDP with AXS10X Main Board and
 * AXC003 FPGA Card (with UP bitfile)
 */
/dts-v1/;

/include/ "axc003.dtsi"
/include/ "axs10x_mb.dtsi"

/ {
	model = "snps,axs103";
	compatible = "snps,axs103", "snps,arc-sdp";

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8 debug print-fatal-signals=1";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 */

/*
 * Device Tree for AXS103 SDP with AXS10X Main Board and
 * AXC003 FPGA Card (with SMP bitfile)
 */
/dts-v1/;

/include/ "axc003_idu.dtsi"
/include/ "axs10x_mb.dtsi"

/ {
	model = "snps,axs103-smp";
	compatible = "snps,axs103", "snps,arc-sdp";

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 print-fatal-signals=1 consoleblank=0";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Support for peripherals on the AXS10x mainboard
 *
 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
 */

/ {
	aliases {
		ethernet = &gmac;
	};

	axs10x_mb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
		interrupt-parent = <&mb_intc>;

		creg_rst: reset-controller@11220 {
			compatible = "snps,axs10x-reset";
			#reset-cells = <1>;
			reg = <0x11220 0x4>;
		};

		i2sclk: i2sclk@100a0 {
			compatible = "snps,axs10x-i2s-pll-clock";
			reg = <0x100a0 0x10>;
			clocks = <&i2spll_clk>;
			#clock-cells = <0>;
		};

		clocks {
			i2spll_clk: i2spll_clk {
				compatible = "fixed-clock";
				clock-frequency = <27000000>;
				#clock-cells = <0>;
			};

			i2cclk: i2cclk {
				compatible = "fixed-clock";
				clock-frequency = <50000000>;
				#clock-cells = <0>;
			};

			apbclk: apbclk {
				compatible = "fixed-clock";
				clock-frequency = <50000000>;
				#clock-cells = <0>;
			};

			mmcclk: mmcclk {
				compatible = "fixed-clock";
				/*
				 * DW sdio controller has external ciu clock divider
				 * controlled via register in SDIO IP. It divides
				 * sdio_ref_clk (which comes from CGU) by 16 for
				 * default. So default mmcclk clock (which comes
				 * to sdk_in) is 25000000 Hz.
				 */
				clock-frequency = <25000000>;
				#clock-cells = <0>;
			};
		};

		pguclk: pguclk@10080 {
			compatible = "snps,axs10x-pgu-pll-clock";
			reg = <0x10080 0x10>, <0x110 0x10>;
			#clock-cells = <0>;
			clocks = <&input_clk>;
		};

		gmac: ethernet@18000 {
			#interrupt-cells = <1>;
			compatible = "snps,dwmac";
			reg = < 0x18000 0x2000 >;
			interrupts = < 4 >;
			interrupt-names = "macirq";
			phy-mode = "rgmii";
			snps,pbl = < 32 >;
			snps,multicast-filter-bins = <256>;
			clocks = <&apbclk>;
			clock-names = "stmmaceth";
			max-speed = <100>;
			resets = <&creg_rst 5>;
			reset-names = "stmmaceth";
			mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
		};

		usb@40000 {
			compatible = "generic-ehci";
			reg = < 0x40000 0x100 >;
			interrupts = < 8 >;
		};

		usb@60000 {
			compatible = "generic-ohci";
			reg = < 0x60000 0x100 >;
			interrupts = < 8 >;
		};

		/*
		 * According to DW Mobile Storage databook it is required
		 * to use  "Hold Register" if card is enumerated in SDR12 or
		 * SDR25 modes.
		 *
		 * Utilization of "Hold Register" is already implemented via
		 * dw_mci_pltfm_prepare_command() which in its turn gets
		 * used through dw_mci_drv_data->prepare_command call-back.
		 * This call-back is used in Altera Socfpga platform and so
		 * we may reuse it saying that we're compatible with their
		 * "altr,socfpga-dw-mshc".
		 *
		 * Most probably "Hold Register" utilization is platform-
		 * independent requirement which means that single unified
		 * "snps,dw-mshc" should be enough for all users of DW MMC once
		 * dw_mci_pltfm_prepare_command() is used in generic platform
		 * code.
		 */
		mmc@15000 {
			compatible = "altr,socfpga-dw-mshc";
			reg = < 0x15000 0x400 >;
			fifo-depth = < 16 >;
			card-detect-delay = < 200 >;
			clocks = <&apbclk>, <&mmcclk>;
			clock-names = "biu", "ciu";
			interrupts = < 7 >;
			bus-width = < 4 >;
		};

		uart@20000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x20000 0x100>;
			clock-frequency = <33333333>;
			interrupts = <17>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		uart@21000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x21000 0x100>;
			clock-frequency = <33333333>;
			interrupts = <18>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		/* UART muxed with USB data port (ttyS3) */
		uart@22000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x22000 0x100>;
			clock-frequency = <33333333>;
			interrupts = <19>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		i2c@1d000 {
			compatible = "snps,designware-i2c";
			reg = <0x1d000 0x100>;
			clock-frequency = <400000>;
			clocks = <&i2cclk>;
			interrupts = <14>;
		};

		i2s: i2s@1e000 {
			compatible = "snps,designware-i2s";
			reg = <0x1e000 0x100>;
			clocks = <&i2sclk 0>;
			clock-names = "i2sclk";
			interrupts = <15>;
			#sound-dai-cells = <0>;
		};

		i2c@1f000 {
			compatible = "snps,designware-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x1f000 0x100>;
			clock-frequency = <400000>;
			clocks = <&i2cclk>;
			interrupts = <16>;

			adv7511:adv7511@39{
				compatible="adi,adv7511";
				reg = <0x39>;
				interrupts = <23>;
				adi,input-depth = <8>;
				adi,input-colorspace = "rgb";
				adi,input-clock = "1x";
				adi,clock-delay = <0x03>;
				#sound-dai-cells = <0>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					/* RGB/YUV input */
					port@0 {
						reg = <0>;
						adv7511_input:endpoint {
						remote-endpoint = <&pgu_output>;
						};
					};

					/* HDMI output */
					port@1 {
						reg = <1>;
						adv7511_output: endpoint {
							remote-endpoint = <&hdmi_connector_in>;
						};
					};
				};
			};

			eeprom@54{
				compatible = "atmel,24c01";
				reg = <0x54>;
				pagesize = <0x8>;
			};

			eeprom@57{
				compatible = "atmel,24c04";
				reg = <0x57>;
				pagesize = <0x8>;
			};
		};

		hdmi0: connector {
			compatible = "hdmi-connector";
			type = "a";
			port {
				hdmi_connector_in: endpoint {
					remote-endpoint = <&adv7511_output>;
				};
			};
		};

		gpio0:gpio@13000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x13000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			gpio0_banka: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
			};

			gpio0_bankb: gpio-controller@1 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <8>;
				reg = <1>;
			};

			gpio0_bankc: gpio-controller@2 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <8>;
				reg = <2>;
			};
		};

		gpio1:gpio@14000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x14000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			gpio1_banka: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <30>;
				reg = <0>;
			};

			gpio1_bankb: gpio-controller@1 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <10>;
				reg = <1>;
			};

			gpio1_bankc: gpio-controller@2 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <8>;
				reg = <2>;
			};
		};

		pgu@17000 {
			compatible = "snps,arcpgu";
			reg = <0x17000 0x400>;
			clocks = <&pguclk>;
			clock-names = "pxlclk";
			memory-region = <&frame_buffer>;
			port {
				pgu_output: endpoint {
					remote-endpoint = <&adv7511_input>;
				};
			};
		};

		sound_playback {
			compatible = "simple-audio-card";
			simple-audio-card,name = "AXS10x HDMI Audio";
			simple-audio-card,format = "i2s";
			simple-audio-card,cpu {
				sound-dai = <&i2s>;
			};
			simple-audio-card,codec {
				sound-dai = <&adv7511>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
 */
/dts-v1/;

/include/ "skeleton_hs.dtsi"

/ {
	model = "snps,zebu_hs";
	compatible = "snps,zebu_hs";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&core_intc>;

	memory {
		device_type = "memory";
		/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
		reg = <0x0 0x80000000 0x0 0x40000000	/* 1 GB low mem */
		       0x1 0x00000000 0x0 0x40000000>;	/* 1 GB highmem */
	};

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
	};

	aliases {
		serial0 = &uart0;
	};

	fpga {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		/* only perip space at end of low mem accessible
			  bus addr,  parent bus addr, size    */
		ranges = <0x80000000 0x0 0x80000000 0x80000000>;

		core_clk: core_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};

		core_intc: interrupt-controller {
			compatible = "snps,archs-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		uart0: serial@f0000000 {
			compatible = "ns16550a";
			reg = <0xf0000000 0x2000>;
			interrupts = <24>;
			clock-frequency = <50000000>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			no-loopback-test = <1>;
		};

		arcpct0: pct {
			compatible = "snps,archs-pct";
			#interrupt-cells = <1>;
			interrupts = <20>;
		};

		virtio0: virtio@f0100000 {
			compatible = "virtio,mmio";
			reg = <0xf0100000 0x2000>;
			interrupts = <31>;
		};

		virtio1: virtio@f0102000 {
			compatible = "virtio,mmio";
			reg = <0xf0102000 0x2000>;
			interrupts = <32>;
		};

		virtio2: virtio@f0104000 {
			compatible = "virtio,mmio";
			reg = <0xf0104000 0x2000>;
			interrupts = <33>;
		};

		virtio3: virtio@f0106000 {
			compatible = "virtio,mmio";
			reg = <0xf0106000 0x2000>;
			interrupts = <34>;
		};

		virtio4: virtio@f0108000 {
			compatible = "virtio,mmio";
			reg = <0xf0108000 0x2000>;
			interrupts = <35>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
 */
/dts-v1/;

/include/ "skeleton_hs_idu.dtsi"

/ {
	model = "snps,zebu_hs-smp";
	compatible = "snps,zebu_hs";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&core_intc>;

	memory {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;	/* 512 */
	};

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
	};

	aliases {
		serial0 = &uart0;
	};

	fpga {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		/* child and parent address space 1:1 mapped */
		ranges;

		core_clk: core_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;	/* 50 MHZ */
		};

		core_intc: interrupt-controller {
			compatible = "snps,archs-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		idu_intc: idu-interrupt-controller {
			compatible = "snps,archs-idu-intc";
			interrupt-controller;
			interrupt-parent = <&core_intc>;
			#interrupt-cells = <1>;
		};

		uart0: serial@f0000000 {
			compatible = "ns16550a";
			reg = <0xf0000000 0x2000>;
			interrupt-parent = <&idu_intc>;
			interrupts = <0>;
			clock-frequency = <50000000>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			no-loopback-test = <1>;
		};

		arcpct0: pct {
			compatible = "snps,archs-pct";
			#interrupt-cells = <1>;
			interrupts = <20>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
 */

/*
 * Device Tree for ARC HS Development Kit
 */
/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/snps,hsdk-reset.h>

/ {
	model = "snps,hsdk";
	compatible = "snps,hsdk";

	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
	};

	aliases {
		ethernet = &gmac;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "snps,archs38";
			reg = <0>;
			clocks = <&core_clk>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "snps,archs38";
			reg = <1>;
			clocks = <&core_clk>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "snps,archs38";
			reg = <2>;
			clocks = <&core_clk>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "snps,archs38";
			reg = <3>;
			clocks = <&core_clk>;
		};
	};

	input_clk: input-clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <33333333>;
	};

	reg_5v0: regulator-5v0 {
		compatible = "regulator-fixed";

		regulator-name = "5v0-supply";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	cpu_intc: cpu-interrupt-controller {
		compatible = "snps,archs-intc";
		interrupt-controller;
		#interrupt-cells = <1>;
	};

	idu_intc: idu-interrupt-controller {
		compatible = "snps,archs-idu-intc";
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&cpu_intc>;
	};

	arcpct: pct {
		compatible = "snps,archs-pct";
		interrupt-parent = <&cpu_intc>;
		interrupts = <20>;
	};

	/* TIMER0 with interrupt for clockevent */
	timer {
		compatible = "snps,arc-timer";
		interrupts = <16>;
		interrupt-parent = <&cpu_intc>;
		clocks = <&core_clk>;
	};

	/* 64-bit Global Free Running Counter */
	gfrc {
		compatible = "snps,archs-timer-gfrc";
		clocks = <&core_clk>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&idu_intc>;

		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;

		cgu_rst: reset-controller@8a0 {
			compatible = "snps,hsdk-reset";
			#reset-cells = <1>;
			reg = <0x8a0 0x4>, <0xff0 0x4>;
		};

		core_clk: core-clk@0 {
			compatible = "snps,hsdk-core-pll-clock";
			reg = <0x00 0x10>, <0x14b8 0x4>;
			#clock-cells = <0>;
			clocks = <&input_clk>;

			/*
			 * Set initial core pll output frequency to 1GHz.
			 * It will be applied at the core pll driver probing
			 * on early boot.
			 */
			assigned-clocks = <&core_clk>;
			assigned-clock-rates = <1000000000>;
		};

		serial: serial@5000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x5000 0x100>;
			clock-frequency = <33330000>;
			interrupts = <6>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		gmacclk: gmacclk {
			compatible = "fixed-clock";
			clock-frequency = <400000000>;
			#clock-cells = <0>;
		};

		mmcclk_ciu: mmcclk-ciu {
			compatible = "fixed-clock";
			/*
			 * DW sdio controller has external ciu clock divider
			 * controlled via register in SDIO IP. Due to its
			 * unexpected default value (it should divide by 1
			 * but it divides by 8) SDIO IP uses wrong clock and
			 * works unstable (see STAR 9001204800)
			 * We switched to the minimum possible value of the
			 * divisor (div-by-2) in HSDK platform code.
			 * So add temporary fix and change clock frequency
			 * to 50000000 Hz until we fix dw sdio driver itself.
			 */
			clock-frequency = <50000000>;
			#clock-cells = <0>;
		};

		mmcclk_biu: mmcclk-biu {
			compatible = "fixed-clock";
			clock-frequency = <400000000>;
			#clock-cells = <0>;
		};

		gpu_core_clk: gpu-core-clk {
			compatible = "fixed-clock";
			clock-frequency = <400000000>;
			#clock-cells = <0>;
		};

		gpu_dma_clk: gpu-dma-clk {
			compatible = "fixed-clock";
			clock-frequency = <400000000>;
			#clock-cells = <0>;
		};

		gpu_cfg_clk: gpu-cfg-clk {
			compatible = "fixed-clock";
			clock-frequency = <200000000>;
			#clock-cells = <0>;
		};

		dmac_core_clk: dmac-core-clk {
			compatible = "fixed-clock";
			clock-frequency = <400000000>;
			#clock-cells = <0>;
		};

		dmac_cfg_clk: dmac-gpu-cfg-clk {
			compatible = "fixed-clock";
			clock-frequency = <200000000>;
			#clock-cells = <0>;
		};

		gmac: ethernet@8000 {
			#interrupt-cells = <1>;
			compatible = "snps,dwmac";
			reg = <0x8000 0x2000>;
			interrupts = <10>;
			interrupt-names = "macirq";
			phy-mode = "rgmii-id";
			snps,pbl = <32>;
			snps,multicast-filter-bins = <256>;
			clocks = <&gmacclk>;
			clock-names = "stmmaceth";
			phy-handle = <&phy0>;
			resets = <&cgu_rst HSDK_ETH_RESET>;
			reset-names = "stmmaceth";
			mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
			dma-coherent;

			tx-fifo-depth = <4096>;
			rx-fifo-depth = <4096>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,dwmac-mdio";
				phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
					reg = <0>;
				};
			};
		};

		usb@60000 {
			compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
			reg = <0x60000 0x100>;
			interrupts = <15>;
			resets = <&cgu_rst HSDK_USB_RESET>;
			dma-coherent;
		};

		usb@40000 {
			compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
			reg = <0x40000 0x100>;
			interrupts = <15>;
			resets = <&cgu_rst HSDK_USB_RESET>;
			dma-coherent;
		};

		mmc@a000 {
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xa000 0x400>;
			num-slots = <1>;
			fifo-depth = <16>;
			card-detect-delay = <200>;
			clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
			clock-names = "biu", "ciu";
			interrupts = <12>;
			bus-width = <4>;
			dma-coherent;
		};

		spi0: spi@20000 {
			compatible = "snps,dw-apb-ssi";
			reg = <0x20000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <16>;
			num-cs = <2>;
			reg-io-width = <4>;
			clocks = <&input_clk>;
			cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
				   <&creg_gpio 1 GPIO_ACTIVE_LOW>;

			flash@0 {
				compatible = "sst26wf016b", "jedec,spi-nor";
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <1>;
				spi-max-frequency = <4000000>;
			};

			adc@1 {
				compatible = "ti,adc108s102";
				reg = <1>;
				vref-supply = <&reg_5v0>;
				spi-max-frequency = <1000000>;
			};
		};

		creg_gpio: gpio@14b0 {
			compatible = "snps,creg-gpio-hsdk";
			reg = <0x14b0 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <2>;
		};

		gpio: gpio@3000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x3000 0x20>;
			#address-cells = <1>;
			#size-cells = <0>;

			gpio_port_a: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <24>;
				reg = <0>;
			};
		};

		gpu_3d: gpu@90000 {
			compatible = "vivante,gc";
			reg = <0x90000 0x4000>;
			clocks = <&gpu_dma_clk>,
				 <&gpu_cfg_clk>,
				 <&gpu_core_clk>,
				 <&gpu_core_clk>;
			clock-names = "bus", "reg", "core", "shader";
			interrupts = <28>;
		};

		dmac: dmac@80000 {
			compatible = "snps,axi-dma-1.01a";
			reg = <0x80000 0x400>;
			interrupts = <27>;
			clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
			clock-names = "core-clk", "cfgr-clk";

			dma-channels = <4>;
			snps,dma-masters = <2>;
			snps,data-width = <3>;
			snps,block-size = <4096 4096 4096 4096>;
			snps,priority = <0 1 2 3>;
			snps,axi-max-burst-len = <16>;
		};
	};

	memory@80000000 {
		#address-cells = <2>;
		#size-cells = <2>;
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;  /* 1 GB lowmem */
		/*     0x1 0x00000000 0x0 0x40000000>;     1 GB highmem */
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
 */
/dts-v1/;

/include/ "skeleton.dtsi"

/ {
	model = "snps,nsim";
	compatible = "snps,nsim";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&core_intc>;

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 print-fatal-signals=1";
	};

	aliases {
		serial0 = &uart0;
	};

	fpga {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		/* child and parent address space 1:1 mapped */
		ranges;

		core_clk: core_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <80000000>;
		};

		core_intc: interrupt-controller {
			compatible = "snps,arc700-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		uart0: serial@f0000000 {
			compatible = "ns16550a";
			reg = <0xf0000000 0x2000>;
			interrupts = <24>;
			clock-frequency = <50000000>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			no-loopback-test = <1>;
		};

		arcpct0: pct {
			compatible = "snps,arc700-pct";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
 */
/dts-v1/;

/include/ "skeleton.dtsi"

/ {
	model = "snps,nsimosci";
	compatible = "snps,nsimosci";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&core_intc>;

	chosen {
		/* this is for console on PGU */
		/* bootargs = "console=tty0 consoleblank=0"; */
		/* this is for console on serial */
		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
	};

	aliases {
		serial0 = &uart0;
	};

	fpga {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		/* child and parent address space 1:1 mapped */
		ranges;

		core_clk: core_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <20000000>;
		};

		core_intc: interrupt-controller {
			compatible = "snps,arc700-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		uart0: serial@f0000000 {
			compatible = "ns8250";
			reg = <0xf0000000 0x2000>;
			interrupts = <11>;
			clock-frequency = <3686400>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			no-loopback-test = <1>;
		};

		pguclk: pguclk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25175000>;
		};

		pgu@f9000000 {
			compatible = "snps,arcpgu";
			reg = <0xf9000000 0x400>;
			clocks = <&pguclk>;
			clock-names = "pxlclk";
		};

		ps2: ps2@f9001000 {
			compatible = "snps,arc_ps2";
			reg = <0xf9000400 0x14>;
			interrupts = <13>;
			interrupt-names = "arc_ps2_irq";
		};

		eth0: ethernet@f0003000 {
			compatible = "ezchip,nps-mgt-enet";
			reg = <0xf0003000 0x44>;
			interrupts = <7>;
		};

		arcpct0: pct {
			compatible = "snps,arc700-pct";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 */
/dts-v1/;

/include/ "skeleton_hs.dtsi"

/ {
	model = "snps,nsimosci_hs";
	compatible = "snps,nsimosci_hs";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&core_intc>;

	chosen {
		/* this is for console on PGU */
		/* bootargs = "console=tty0 consoleblank=0"; */
		/* this is for console on serial */
		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
	};

	aliases {
		serial0 = &uart0;
	};

	fpga {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		/* child and parent address space 1:1 mapped */
		ranges;

		core_clk: core_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <20000000>;
		};

		core_intc: core-interrupt-controller {
			compatible = "snps,archs-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		uart0: serial@f0000000 {
			compatible = "ns8250";
			reg = <0xf0000000 0x2000>;
			interrupts = <24>;
			clock-frequency = <3686400>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			no-loopback-test = <1>;
		};

		pguclk: pguclk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25175000>;
		};

		pgu@f9000000 {
			compatible = "snps,arcpgu";
			reg = <0xf9000000 0x400>;
			clocks = <&pguclk>;
			clock-names = "pxlclk";
		};

		ps2: ps2@f9001000 {
			compatible = "snps,arc_ps2";
			reg = <0xf9000400 0x14>;
			interrupts = <27>;
			interrupt-names = "arc_ps2_irq";
		};

		eth0: ethernet@f0003000 {
			compatible = "ezchip,nps-mgt-enet";
			reg = <0xf0003000 0x44>;
			interrupts = <25>;
		};

		arcpct0: pct {
			compatible = "snps,archs-pct";
			#interrupt-cells = <1>;
			interrupts = <20>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 */
/dts-v1/;

/include/ "skeleton_hs_idu.dtsi"

/ {
	model = "snps,nsimosci_hs-smp";
	compatible = "snps,nsimosci_hs";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&core_intc>;

	chosen {
		/* this is for console on serial */
		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1";
	};

	aliases {
		serial0 = &uart0;
	};

	fpga {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		/* child and parent address space 1:1 mapped */
		ranges;

		core_clk: core_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <5000000>;
		};

		core_intc: core-interrupt-controller {
			compatible = "snps,archs-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		idu_intc: idu-interrupt-controller {
			compatible = "snps,archs-idu-intc";
			interrupt-controller;
			interrupt-parent = <&core_intc>;
			#interrupt-cells = <1>;
		};

		uart0: serial@f0000000 {
			compatible = "ns8250";
			reg = <0xf0000000 0x2000>;
			interrupt-parent = <&idu_intc>;
			interrupts = <0>;
			clock-frequency = <3686400>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			no-loopback-test = <1>;
		};

		pguclk: pguclk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25175000>;
		};

		pgu@f9000000 {
			compatible = "snps,arcpgu";
			reg = <0xf9000000 0x400>;
			clocks = <&pguclk>;
			clock-names = "pxlclk";
		};

		ps2: ps2@f9001000 {
			compatible = "snps,arc_ps2";
			reg = <0xf9000400 0x14>;
			interrupts = <3>;
			interrupt-parent = <&idu_intc>;
			interrupt-names = "arc_ps2_irq";
		};

		eth0: ethernet@f0003000 {
			compatible = "ezchip,nps-mgt-enet";
			reg = <0xf0003000 0x44>;
			interrupt-parent = <&idu_intc>;
			interrupts = <1>;
		};

		arcpct0: pct {
			compatible = "snps,archs-pct";
			#interrupt-cells = <1>;
			interrupts = <20>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
 */

/*
 * Skeleton device tree; the bare minimum needed to boot; just include and
 * add a compatible value.
 */

/ {
	compatible = "snps,arc";
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };
	aliases { };

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "snps,arc770d";
			reg = <0>;
			clocks = <&core_clk>;
		};
	};

	/* TIMER0 with interrupt for clockevent */
	timer0 {
		compatible = "snps,arc-timer";
		interrupts = <3>;
		interrupt-parent = <&core_intc>;
		clocks = <&core_clk>;
	};

	/* TIMER1 for free running clocksource */
	timer1 {
		compatible = "snps,arc-timer";
		clocks = <&core_clk>;
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;	/* 256M */
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
 */

/ {
	compatible = "snps,arc";
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };
	aliases { };

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "snps,archs38";
			reg = <0>;
			clocks = <&core_clk>;
		};
	};

	/* TIMER0 with interrupt for clockevent */
	timer0 {
		compatible = "snps,arc-timer";
		interrupts = <16>;
		interrupt-parent = <&core_intc>;
		clocks = <&core_clk>;
	};

	/* 64-bit Local RTC: preferred clocksource for UP */
	rtc {
		compatible = "snps,archs-timer-rtc";
		clocks = <&core_clk>;
	};

	/* TIMER1 for free running clocksource: Fallback if rtc not found */
	timer1 {
		compatible = "snps,arc-timer";
		clocks = <&core_clk>;
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;	/* 256M */
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
 */

/ {
	compatible = "snps,arc";
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };
	aliases { };

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "snps,archs38";
			reg = <0>;
			clocks = <&core_clk>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "snps,archs38";
			reg = <1>;
			clocks = <&core_clk>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "snps,archs38";
			reg = <2>;
			clocks = <&core_clk>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "snps,archs38";
			reg = <3>;
			clocks = <&core_clk>;
		};
	};

	/* TIMER0 with interrupt for clockevent */
	timer0 {
		compatible = "snps,arc-timer";
		interrupts = <16>;
		interrupt-parent = <&core_intc>;
		clocks = <&core_clk>;
	};

	/* 64-bit Global Free Running Counter */
	gfrc {
		compatible = "snps,archs-timer-gfrc";
		clocks = <&core_clk>;
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;	/* 256M */
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com)
 */

/*
 * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version)
 */

/include/ "skeleton_hs.dtsi"

/ {
	compatible = "snps,arc";
	#address-cells = <1>;
	#size-cells = <1>;

	cpu_card {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x00000000 0xf0000000 0x10000000>;

		core_clk: core_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};

		core_intc: archs-intc@cpu {
			compatible = "snps,archs-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		debug_uart: dw-apb-uart@5000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x5000 0x100>;
			clock-frequency = <2403200>;
			interrupt-parent = <&core_intc>;
			interrupts = <19>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

	};

	mb_intc: interrupt-controller@e0012000 {
		#interrupt-cells = <1>;
		compatible = "snps,dw-apb-ictl";
		reg = < 0xe0012000 0x200 >;
		interrupt-controller;
		interrupt-parent = <&core_intc>;
		interrupts = < 18 >;
	};

	memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x80000000 0x40000000>;
		device_type = "memory";
		reg = <0x80000000 0x20000000>;	/* 512MiB */
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
 */

/*
 * Device tree for AXC003 CPU card:
 * HS38x2 (Dual Core) with IDU intc (VDK version)
 */

/include/ "skeleton_hs_idu.dtsi"

/ {
	compatible = "snps,arc";
	#address-cells = <1>;
	#size-cells = <1>;

	cpu_card {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x00000000 0xf0000000 0x10000000>;

		core_clk: core_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};

		core_intc: archs-intc@cpu {
			compatible = "snps,archs-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		idu_intc: idu-interrupt-controller {
			compatible = "snps,archs-idu-intc";
			interrupt-controller;
			interrupt-parent = <&core_intc>;
			#interrupt-cells = <1>;
		};

		debug_uart: dw-apb-uart@5000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x5000 0x100>;
			clock-frequency = <2403200>;
			interrupt-parent = <&idu_intc>;
			interrupts = <2>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

	};

	mb_intc: interrupt-controller@e0012000 {
		#interrupt-cells = <1>;
		compatible = "snps,dw-apb-ictl";
		reg = < 0xe0012000 0x200 >;
		interrupt-controller;
		interrupt-parent = <&idu_intc>;
		interrupts = <0>;
	};

	memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x80000000 0x40000000>;
		device_type = "memory";
		reg = <0x80000000 0x20000000>;	/* 512MiB */
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Support for peripherals on the AXS10x mainboard (VDK version)
 *
 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
 */

/ {
	axs10x_mb_vdk {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0xe0000000 0x10000000>;
		interrupt-parent = <&mb_intc>;

		clocks {
			apbclk: apbclk {
				compatible = "fixed-clock";
				clock-frequency = <50000000>;
				#clock-cells = <0>;
			};

			mmcclk: mmcclk {
				compatible = "fixed-clock";
				clock-frequency = <50000000>;
				#clock-cells = <0>;
			};

			pguclk: pguclk {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <25175000>;
			};
		};

		ethernet@18000 {
			#interrupt-cells = <1>;
			compatible = "snps,dwmac";
			reg = < 0x18000 0x2000 >;
			interrupts = < 4 >;
			interrupt-names = "macirq";
			phy-mode = "rgmii";
			snps,phy-addr = < 0 >;  // VDK model phy address is 0
			snps,pbl = < 32 >;
			clocks = <&apbclk>;
			clock-names = "stmmaceth";
		};

		usb@40000 {
			compatible = "generic-ehci";
			reg = < 0x40000 0x100 >;
			interrupts = < 8 >;
		};

		uart@20000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x20000 0x100>;
			clock-frequency = <2403200>;
			interrupts = <17>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		uart@21000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x21000 0x100>;
			clock-frequency = <2403200>;
			interrupts = <18>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		uart@22000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x22000 0x100>;
			clock-frequency = <2403200>;
			interrupts = <19>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

/* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */
		pgu@17000 {
			compatible = "snps,arcpgu";
			reg = <0x17000 0x400>;
			clocks = <&pguclk>;
			clock-names = "pxlclk";
		};

/* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */
		ps2: ps2@e0017400 {
			compatible = "snps,arc_ps2";
			reg = <0x17400 0x14>;
			interrupts = <5>;
			interrupt-names = "arc_ps2_irq";
		};

		mmc@15000 {
			compatible = "snps,dw-mshc";
			reg = <0x15000 0x400>;
			fifo-depth = <1024>;
			card-detect-delay = <200>;
			clocks = <&apbclk>, <&mmcclk>;
			clock-names = "biu", "ciu";
			interrupts = <7>;
			bus-width = <4>;
		};
	};

	/*
	 * Embedded Vision subsystem UIO mappings; only relevant for EV VDK
	 *
	 * This node is intentionally put outside of MB above becase
	 * it maps areas outside of MB's 0xez-0xfz.
	 */
	uio_ev: uio@d0000000 {
		compatible = "generic-uio";
		reg = <0xd0000000 0x2000 0xd1000000 0x2000 0x90000000 0x10000000 0xc0000000 0x10000000>;
		reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem";
		interrupt-parent = <&mb_intc>;
		interrupts = <23>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
 *
 * ARC HS38 Virtual Development Kit (VDK)
 */
/dts-v1/;

/include/ "vdk_axc003.dtsi"
/include/ "vdk_axs10x_mb.dtsi"

/ {
	model = "snps,vdk_archs";
	compatible = "snps,axs103";

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
 *
 * ARC HS38 Virtual Development Kit, SMP version (VDK)
 */
/dts-v1/;

/include/ "vdk_axc003_idu.dtsi"
/include/ "vdk_axs10x_mb.dtsi"

/ {
	model = "snps,vdk_archs-smp";
	compatible = "snps,axs103";

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 video=640x480-24";
	};
};


code:
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_ISA_ARCOMPACT=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARC_PLAT_AXS10X=y
CONFIG_AXS101=y
CONFIG_ARC_CACHE_LINE_SHIFT=5
CONFIG_ARC_BUILTIN_DTB_NAME="axs101"
CONFIG_PREEMPT=y
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_NATIONAL_PHY=y
# CONFIG_USB_NET_DRIVERS is not set
CONFIG_INPUT_EVDEV=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
CONFIG_MOUSE_SERIAL=y
CONFIG_MOUSE_SYNAPTICS_USB=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
# CONFIG_HWMON is not set
CONFIG_DRM=m
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_ARCPGU=m
CONFIG_FB=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_DW=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT3_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set


code:
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARC_PLAT_AXS10X=y
CONFIG_AXS103=y
CONFIG_ISA_ARCV2=y
CONFIG_ARC_BUILTIN_DTB_NAME="axs103"
CONFIG_PREEMPT=y
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_NATIONAL_PHY=y
# CONFIG_USB_NET_DRIVERS is not set
CONFIG_INPUT_EVDEV=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
CONFIG_MOUSE_SERIAL=y
CONFIG_MOUSE_SYNAPTICS_USB=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_DW=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT3_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set


code:
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARC_PLAT_AXS10X=y
CONFIG_AXS103=y
CONFIG_ISA_ARCV2=y
CONFIG_SMP=y
CONFIG_ARC_BUILTIN_DTB_NAME="axs103_idu"
CONFIG_PREEMPT=y
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_NATIONAL_PHY=y
# CONFIG_USB_NET_DRIVERS is not set
CONFIG_INPUT_EVDEV=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
CONFIG_MOUSE_SERIAL=y
CONFIG_MOUSE_SYNAPTICS_USB=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
# CONFIG_HWMON is not set
CONFIG_DRM=m
CONFIG_DRM_I2C_ADV7511=m
CONFIG_DRM_ARCPGU=m
CONFIG_FB=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_DW=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT3_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set


code:
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_PERF_EVENTS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs"
CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_UNIX_DIAG=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_VIRTIO_BLK=y
CONFIG_NETDEVICES=y
CONFIG_VIRTIO_NET=y
# CONFIG_ETHERNET is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_VIRTIO_MMIO=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_PREEMPT is not set


code:
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_SMP=y
CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs_idu"
CONFIG_KPROBES=y
CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_UNIX_DIAG=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
# CONFIG_ETHERNET is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_DEBUG_PREEMPT is not set


code:
CONFIG_SYSVIPC=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_BLK_DEV_RAM=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_ARC_SOC_HSDK=y
CONFIG_ISA_ARCV2=y
CONFIG_SMP=y
CONFIG_LINUX_LINK_BASE=0x90000000
CONFIG_LINUX_RAM_BASE=0x80000000
CONFIG_ARC_BUILTIN_DTB_NAME="hsdk"
CONFIG_PREEMPT=y
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_SPI_NOR=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_STMMAC_ETH=y
CONFIG_MICREL_PHY=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_SPI=y
CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_MMIO=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_SNPS_CREG=y
# CONFIG_HWMON is not set
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_DRM=y
# CONFIG_DRM_FBDEV_EMULATION is not set
CONFIG_DRM_UDL=y
CONFIG_DRM_ETNAVIV=y
CONFIG_FB=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_DW=y
CONFIG_DMADEVICES=y
CONFIG_DW_AXI_DMAC=y
CONFIG_IIO=y
CONFIG_TI_ADC108S102=y
CONFIG_EXT3_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
CONFIG_CRYPTO_ECHAINIV=y


code:
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_ISA_ARCOMPACT=y
CONFIG_ARC_BUILTIN_DTB_NAME="nsim_700"
CONFIG_KPROBES=y
CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_UNIX_DIAG=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
# CONFIG_ETHERNET is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
# CONFIG_DEBUG_PREEMPT is not set


code:
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_ISA_ARCOMPACT=y
CONFIG_KPROBES=y
CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci"
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_UNIX_DIAG=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_MOUSE_PS2_ALPS is not set
# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
# CONFIG_MOUSE_PS2_SYNAPTICS is not set
# CONFIG_MOUSE_PS2_CYPRESS is not set
# CONFIG_MOUSE_PS2_TRACKPOINT is not set
CONFIG_MOUSE_PS2_TOUCHKIT=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_ARC_PS2=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_DRM=y
CONFIG_DRM_ARCPGU=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y


code:
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_KPROBES=y
CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ISA_ARCV2=y
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs"
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_UNIX_DIAG=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=y
CONFIG_INPUT_EVDEV=y
# CONFIG_MOUSE_PS2_ALPS is not set
# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
# CONFIG_MOUSE_PS2_SYNAPTICS is not set
# CONFIG_MOUSE_PS2_TRACKPOINT is not set
CONFIG_MOUSE_PS2_TOUCHKIT=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_ARC_PS2=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_DRM=y
CONFIG_DRM_ARCPGU=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y


code:
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_PERF_EVENTS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_KPROBES=y
CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ISA_ARCV2=y
CONFIG_SMP=y
# CONFIG_ARC_TIMERS_64BIT is not set
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs_idu"
CONFIG_PREEMPT=y
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_UNIX_DIAG=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=y
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_ARC_PS2=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_DRM=y
CONFIG_DRM_ARCPGU=y
CONFIG_LOGO=y
# CONFIG_HID is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_FTRACE=y
# CONFIG_NET_VENDOR_CADENCE is not set


code:
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_DEFAULT_HOSTNAME="tb10x"
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="../tb10x-rootfs.cpio"
CONFIG_INITRAMFS_ROOT_UID=2100
CONFIG_INITRAMFS_ROOT_GID=501
# CONFIG_RD_GZIP is not set
CONFIG_KALLSYMS_ALL=y
# CONFIG_AIO is not set
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_ISA_ARCOMPACT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLOCK is not set
CONFIG_ARC_PLAT_TB10X=y
CONFIG_ARC_CACHE_LINE_SHIFT=5
CONFIG_HZ=250
CONFIG_ARC_BUILTIN_DTB_NAME="abilis_tb100_dvk"
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_COMPACTION is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_8250_DW=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_LEDS_TRIGGER_TRANSIENT=y
CONFIG_DMADEVICES=y
CONFIG_DW_DMAC=y
CONFIG_ASYNC_TX_DMA=y
# CONFIG_IOMMU_SUPPORT is not set
# CONFIG_DNOTIFY is not set
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
CONFIG_HEADERS_INSTALL=y
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_SCHEDSTATS=y
# CONFIG_CRYPTO_HW is not set
# CONFIG_NET_VENDOR_CADENCE is not set


code:
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARC_PLAT_AXS10X=y
CONFIG_AXS103=y
CONFIG_ISA_ARCV2=y
CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38"
CONFIG_PREEMPT=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_SLRAM=y
CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_NATIONAL_PHY=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
CONFIG_SERIO_ARC_PS2=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_FB=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SERIAL=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT3_FS=y
CONFIG_EXT4_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set


code:
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARC_PLAT_AXS10X=y
CONFIG_AXS103=y
CONFIG_ISA_ARCV2=y
CONFIG_SMP=y
# CONFIG_ARC_TIMERS_64BIT is not set
CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp"
CONFIG_PREEMPT=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_SLRAM=y
CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_NATIONAL_PHY=y
CONFIG_MOUSE_PS2_TOUCHKIT=y
CONFIG_SERIO_ARC_PS2=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_DRM=y
CONFIG_DRM_ARCPGU=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SERIAL=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_DW=y
CONFIG_UIO=y
CONFIG_UIO_PDRV_GENIRQ=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT3_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set


code:
# SPDX-License-Identifier: GPL-2.0
generic-y += extable.h
generic-y += kvm_para.h
generic-y += mcs_spinlock.h
generic-y += parport.h
generic-y += user.h

path: arch/arc/include/asm/Kbuild


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 */

#ifndef _ASM_ARC_ARCREGS_H
#define _ASM_ARC_ARCREGS_H

/* Build Configuration Registers */
#define ARC_REG_AUX_DCCM	0x18	/* DCCM Base Addr ARCv2 */
#define ARC_REG_ERP_CTRL	0x3F	/* ARCv2 Error protection control */
#define ARC_REG_DCCM_BASE_BUILD	0x61	/* DCCM Base Addr ARCompact */
#define ARC_REG_CRC_BCR		0x62
#define ARC_REG_VECBASE_BCR	0x68
#define ARC_REG_PERIBASE_BCR	0x69
#define ARC_REG_FP_BCR		0x6B	/* ARCompact: Single-Precision FPU */
#define ARC_REG_DPFP_BCR	0x6C	/* ARCompact: Dbl Precision FPU */
#define ARC_REG_ERP_BUILD	0xc7	/* ARCv2 Error protection Build: ECC/Parity */
#define ARC_REG_FP_V2_BCR	0xc8	/* ARCv2 FPU */
#define ARC_REG_SLC_BCR		0xce
#define ARC_REG_DCCM_BUILD	0x74	/* DCCM size (common) */
#define ARC_REG_AP_BCR		0x76
#define ARC_REG_ICCM_BUILD	0x78	/* ICCM size (common) */
#define ARC_REG_XY_MEM_BCR	0x79
#define ARC_REG_MAC_BCR		0x7a
#define ARC_REG_MUL_BCR		0x7b
#define ARC_REG_SWAP_BCR	0x7c
#define ARC_REG_NORM_BCR	0x7d
#define ARC_REG_MIXMAX_BCR	0x7e
#define ARC_REG_BARREL_BCR	0x7f
#define ARC_REG_D_UNCACH_BCR	0x6A
#define ARC_REG_BPU_BCR		0xc0
#define ARC_REG_ISA_CFG_BCR	0xc1
#define ARC_REG_LPB_BUILD	0xE9	/* ARCv2 Loop Buffer Build */
#define ARC_REG_RTT_BCR		0xF2
#define ARC_REG_IRQ_BCR		0xF3
#define ARC_REG_MICRO_ARCH_BCR	0xF9	/* ARCv2 Product revision */
#define ARC_REG_SMART_BCR	0xFF
#define ARC_REG_CLUSTER_BCR	0xcf
#define ARC_REG_AUX_ICCM	0x208	/* ICCM Base Addr (ARCv2) */
#define ARC_REG_LPB_CTRL	0x488	/* ARCv2 Loop Buffer control */
#define ARC_REG_FPU_CTRL	0x300
#define ARC_REG_FPU_STATUS	0x301

/* Common for ARCompact and ARCv2 status register */
#define ARC_REG_STATUS32	0x0A

/* status32 Bits Positions */
#define STATUS_AE_BIT		5	/* Exception active */
#define STATUS_DE_BIT		6	/* PC is in delay slot */
#define STATUS_U_BIT		7	/* User/Kernel mode */
#define STATUS_Z_BIT            11
#define STATUS_L_BIT		12	/* Loop inhibit */

/* These masks correspond to the status word(STATUS_32) bits */
#define STATUS_AE_MASK		(1<<STATUS_AE_BIT)
#define STATUS_DE_MASK		(1<<STATUS_DE_BIT)
#define STATUS_U_MASK		(1<<STATUS_U_BIT)
#define STATUS_Z_MASK		(1<<STATUS_Z_BIT)
#define STATUS_L_MASK		(1<<STATUS_L_BIT)

/*
 * ECR: Exception Cause Reg bits-n-pieces
 * [23:16] = Exception Vector
 * [15: 8] = Exception Cause Code
 * [ 7: 0] = Exception Parameters (for certain types only)
 */
#ifdef CONFIG_ISA_ARCOMPACT
#define ECR_V_MEM_ERR			0x01
#define ECR_V_INSN_ERR			0x02
#define ECR_V_MACH_CHK			0x20
#define ECR_V_ITLB_MISS			0x21
#define ECR_V_DTLB_MISS			0x22
#define ECR_V_PROTV			0x23
#define ECR_V_TRAP			0x25
#else
#define ECR_V_MEM_ERR			0x01
#define ECR_V_INSN_ERR			0x02
#define ECR_V_MACH_CHK			0x03
#define ECR_V_ITLB_MISS			0x04
#define ECR_V_DTLB_MISS			0x05
#define ECR_V_PROTV			0x06
#define ECR_V_TRAP			0x09
#define ECR_V_MISALIGN			0x0d
#endif

/* DTLB Miss and Protection Violation Cause Codes */

#define ECR_C_PROTV_INST_FETCH		0x00
#define ECR_C_PROTV_LOAD		0x01
#define ECR_C_PROTV_STORE		0x02
#define ECR_C_PROTV_XCHG		0x03
#define ECR_C_PROTV_MISALIG_DATA	0x04

#define ECR_C_BIT_PROTV_MISALIG_DATA	10

/* Machine Check Cause Code Values */
#define ECR_C_MCHK_DUP_TLB		0x01

/* DTLB Miss Exception Cause Code Values */
#define ECR_C_BIT_DTLB_LD_MISS		8
#define ECR_C_BIT_DTLB_ST_MISS		9

/* Auxiliary registers */
#define AUX_IDENTITY		4
#define AUX_EXEC_CTRL		8
#define AUX_INTR_VEC_BASE	0x25
#define AUX_VOL			0x5e

/*
 * Floating Pt Registers
 * Status regs are read-only (build-time) so need not be saved/restored
 */
#define ARC_AUX_FP_STAT         0x300
#define ARC_AUX_DPFP_1L         0x301
#define ARC_AUX_DPFP_1H         0x302
#define ARC_AUX_DPFP_2L         0x303
#define ARC_AUX_DPFP_2H         0x304
#define ARC_AUX_DPFP_STAT       0x305

/*
 * DSP-related registers
 * Registers names must correspond to dsp_callee_regs structure fields names
 * for automatic offset calculation in DSP_AUX_SAVE_RESTORE macros.
 */
#define ARC_AUX_DSP_BUILD	0x7A
#define ARC_AUX_ACC0_LO		0x580
#define ARC_AUX_ACC0_GLO	0x581
#define ARC_AUX_ACC0_HI		0x582
#define ARC_AUX_ACC0_GHI	0x583
#define ARC_AUX_DSP_BFLY0	0x598
#define ARC_AUX_DSP_CTRL	0x59F
#define ARC_AUX_DSP_FFT_CTRL	0x59E

#define ARC_AUX_AGU_BUILD	0xCC
#define ARC_AUX_AGU_AP0		0x5C0
#define ARC_AUX_AGU_AP1		0x5C1
#define ARC_AUX_AGU_AP2		0x5C2
#define ARC_AUX_AGU_AP3		0x5C3
#define ARC_AUX_AGU_OS0		0x5D0
#define ARC_AUX_AGU_OS1		0x5D1
#define ARC_AUX_AGU_MOD0	0x5E0
#define ARC_AUX_AGU_MOD1	0x5E1
#define ARC_AUX_AGU_MOD2	0x5E2
#define ARC_AUX_AGU_MOD3	0x5E3

#ifndef __ASSEMBLY__

#include <soc/arc/aux.h>

/* Helpers */
#define TO_KB(bytes)		((bytes) >> 10)
#define TO_MB(bytes)		(TO_KB(bytes) >> 10)
#define PAGES_TO_KB(n_pages)	((n_pages) << (PAGE_SHIFT - 10))
#define PAGES_TO_MB(n_pages)	(PAGES_TO_KB(n_pages) >> 10)

/*
 ***************************************************************
 * Build Configuration Registers, with encoded hardware config
 */
struct bcr_identity {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int chip_id:16, cpu_id:8, family:8;
#else
	unsigned int family:8, cpu_id:8, chip_id:16;
#endif
};

struct bcr_isa_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
		     pad1:12, ver:8;
#else
	unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
		     ldd:1, pad2:4, div_rem:4;
#endif
};

struct bcr_uarch_build_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:8, prod:8, maj:8, min:8;
#else
	unsigned int min:8, maj:8, prod:8, pad:8;
#endif
};

struct bcr_mpy {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
#else
	unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
#endif
};

struct bcr_iccm_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int base:16, pad:5, sz:3, ver:8;
#else
	unsigned int ver:8, sz:3, pad:5, base:16;
#endif
};

struct bcr_iccm_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
#else
	unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
#endif
};

struct bcr_dccm_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int res:21, sz:3, ver:8;
#else
	unsigned int ver:8, sz:3, res:21;
#endif
};

struct bcr_dccm_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
#else
	unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
#endif
};

/* ARCompact: Both SP and DP FPU BCRs have same format */
struct bcr_fp_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int fast:1, ver:8;
#else
	unsigned int ver:8, fast:1;
#endif
};

struct bcr_fp_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
#else
	unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
#endif
};

struct bcr_actionpoint {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:21, min:1, num:2, ver:8;
#else
	unsigned int ver:8, num:2, min:1, pad:21;
#endif
};

#include <soc/arc/timers.h>

struct bcr_bpu_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
#else
	unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
#endif
};

struct bcr_bpu_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
#else
	unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
#endif
};

/* Error Protection Build: ECC/Parity */
struct bcr_erp {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
#else
	unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
#endif
};

/* Error Protection Control */
struct ctl_erp {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1;
#else
	unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27;
#endif
};

struct bcr_lpb {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:16, entries:8, ver:8;
#else
	unsigned int ver:8, entries:8, pad:16;
#endif
};

struct bcr_generic {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int info:24, ver:8;
#else
	unsigned int ver:8, info:24;
#endif
};

/*
 *******************************************************************
 * Generic structures to hold build configuration used at runtime
 */

struct cpuinfo_arc_mmu {
	unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
	unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
};

struct cpuinfo_arc_cache {
	unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;
};

struct cpuinfo_arc_bpu {
	unsigned int ver, full, num_cache, num_pred, ret_stk;
};

struct cpuinfo_arc_ccm {
	unsigned int base_addr, sz;
};

struct cpuinfo_arc {
	struct cpuinfo_arc_cache icache, dcache, slc;
	struct cpuinfo_arc_mmu mmu;
	struct cpuinfo_arc_bpu bpu;
	struct bcr_identity core;
	struct bcr_isa_arcv2 isa;
	const char *release, *name;
	unsigned int vec_base;
	struct cpuinfo_arc_ccm iccm, dccm;
	struct {
		unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
			     fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,
			     ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1,
			     timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
	} extn;
	struct bcr_mpy extn_mpy;
};

extern struct cpuinfo_arc cpuinfo_arc700[];

static inline int is_isa_arcv2(void)
{
	return IS_ENABLED(CONFIG_ISA_ARCV2);
}

static inline int is_isa_arcompact(void)
{
	return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
}

#endif /* __ASEMBLY__ */

#endif /* _ASM_ARC_ARCREGS_H */


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 */

#include <generated/asm-offsets.h>


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2020 Synopsys, Inc. (www.synopsys.com)
 *
 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 */
#ifndef __ASM_ARC_ASSERTS_H
#define __ASM_ARC_ASSERTS_H

/* Helpers to sanitize config options. */

void chk_opt_strict(char *opt_name, bool hw_exists, bool opt_ena);
void chk_opt_weak(char *opt_name, bool hw_exists, bool opt_ena);

/*
 * Check required config option:
 *  - panic in case of OPT enabled but corresponding HW absent.
 *  - warn in case of OPT disabled but corresponding HW exists.
*/
#define CHK_OPT_STRICT(opt_name, hw_exists)				\
({									\
	chk_opt_strict(#opt_name, hw_exists, IS_ENABLED(opt_name));	\
})

/*
 * Check optional config option:
 *  - panic in case of OPT enabled but corresponding HW absent.
*/
#define CHK_OPT_WEAK(opt_name, hw_exists)				\
({									\
	chk_opt_weak(#opt_name, hw_exists, IS_ENABLED(opt_name));	\
})

#endif /* __ASM_ARC_ASSERTS_H */


code:
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef _ASM_ARC_ATOMIC_LLSC_H
#define _ASM_ARC_ATOMIC_LLSC_H

#define arch_atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))

#define ATOMIC_OP(op, asm_op)					\
static inline void arch_atomic_##op(int i, atomic_t *v)			\
{									\
	unsigned int val;						\
									\
	__asm__ __volatile__(						\
	"1:	llock   %[val], [%[ctr]]		\n"		\
	"	" #asm_op " %[val], %[val], %[i]	\n"		\
	"	scond   %[val], [%[ctr]]		\n"		\
	"	bnz     1b				\n"		\
	: [val]	"=&r"	(val) /* Early clobber to prevent reg reuse */	\
	: [ctr]	"r"	(&v->counter), /* Not "m": llock only supports reg direct addr mode */	\
	  [i]	"ir"	(i)						\
	: "cc");							\
}									\

#define ATOMIC_OP_RETURN(op, asm_op)				\
static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v)	\
{									\
	unsigned int val;						\
									\
	__asm__ __volatile__(						\
	"1:	llock   %[val], [%[ctr]]		\n"		\
	"	" #asm_op " %[val], %[val], %[i]	\n"		\
	"	scond   %[val], [%[ctr]]		\n"		\
	"	bnz     1b				\n"		\
	: [val]	"=&r"	(val)						\
	: [ctr]	"r"	(&v->counter),					\
	  [i]	"ir"	(i)						\
	: "cc");							\
									\
	return val;							\
}

#define arch_atomic_add_return_relaxed		arch_atomic_add_return_relaxed
#define arch_atomic_sub_return_relaxed		arch_atomic_sub_return_relaxed

#define ATOMIC_FETCH_OP(op, asm_op)				\
static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v)	\
{									\
	unsigned int val, orig;						\
									\
	__asm__ __volatile__(						\
	"1:	llock   %[orig], [%[ctr]]		\n"		\
	"	" #asm_op " %[val], %[orig], %[i]	\n"		\
	"	scond   %[val], [%[ctr]]		\n"		\
	"	bnz     1b				\n"		\
	: [val]	"=&r"	(val),						\
	  [orig] "=&r" (orig)						\
	: [ctr]	"r"	(&v->counter),					\
	  [i]	"ir"	(i)						\
	: "cc");							\
									\
	return orig;							\
}

#define arch_atomic_fetch_add_relaxed		arch_atomic_fetch_add_relaxed
#define arch_atomic_fetch_sub_relaxed		arch_atomic_fetch_sub_relaxed

#define arch_atomic_fetch_and_relaxed		arch_atomic_fetch_and_relaxed
#define arch_atomic_fetch_andnot_relaxed	arch_atomic_fetch_andnot_relaxed
#define arch_atomic_fetch_or_relaxed		arch_atomic_fetch_or_relaxed
#define arch_atomic_fetch_xor_relaxed		arch_atomic_fetch_xor_relaxed

#define ATOMIC_OPS(op, asm_op)					\
	ATOMIC_OP(op, asm_op)					\
	ATOMIC_OP_RETURN(op, asm_op)				\
	ATOMIC_FETCH_OP(op, asm_op)

ATOMIC_OPS(add, add)
ATOMIC_OPS(sub, sub)

#undef ATOMIC_OPS
#define ATOMIC_OPS(op, asm_op)					\
	ATOMIC_OP(op, asm_op)					\
	ATOMIC_FETCH_OP(op, asm_op)

ATOMIC_OPS(and, and)
ATOMIC_OPS(andnot, bic)
ATOMIC_OPS(or, or)
ATOMIC_OPS(xor, xor)

#define arch_atomic_andnot		arch_atomic_andnot

#undef ATOMIC_OPS
#undef ATOMIC_FETCH_OP
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef _ASM_ARC_ATOMIC_SPLOCK_H
#define _ASM_ARC_ATOMIC_SPLOCK_H

/*
 * Non hardware assisted Atomic-R-M-W
 * Locking would change to irq-disabling only (UP) and spinlocks (SMP)
 */

static inline void arch_atomic_set(atomic_t *v, int i)
{
	/*
	 * Independent of hardware support, all of the atomic_xxx() APIs need
	 * to follow the same locking rules to make sure that a "hardware"
	 * atomic insn (e.g. LD) doesn't clobber an "emulated" atomic insn
	 * sequence
	 *
	 * Thus atomic_set() despite being 1 insn (and seemingly atomic)
	 * requires the locking.
	 */
	unsigned long flags;

	atomic_ops_lock(flags);
	WRITE_ONCE(v->counter, i);
	atomic_ops_unlock(flags);
}

#define arch_atomic_set_release(v, i)	arch_atomic_set((v), (i))

#define ATOMIC_OP(op, c_op, asm_op)					\
static inline void arch_atomic_##op(int i, atomic_t *v)			\
{									\
	unsigned long flags;						\
									\
	atomic_ops_lock(flags);						\
	v->counter c_op i;						\
	atomic_ops_unlock(flags);					\
}

#define ATOMIC_OP_RETURN(op, c_op, asm_op)				\
static inline int arch_atomic_##op##_return(int i, atomic_t *v)		\
{									\
	unsigned long flags;						\
	unsigned int temp;						\
									\
	/*								\
	 * spin lock/unlock provides the needed smp_mb() before/after	\
	 */								\
	atomic_ops_lock(flags);						\
	temp = v->counter;						\
	temp c_op i;							\
	v->counter = temp;						\
	atomic_ops_unlock(flags);					\
									\
	return temp;							\
}

#define ATOMIC_FETCH_OP(op, c_op, asm_op)				\
static inline int arch_atomic_fetch_##op(int i, atomic_t *v)		\
{									\
	unsigned long flags;						\
	unsigned int orig;						\
									\
	/*								\
	 * spin lock/unlock provides the needed smp_mb() before/after	\
	 */								\
	atomic_ops_lock(flags);						\
	orig = v->counter;						\
	v->counter c_op i;						\
	atomic_ops_unlock(flags);					\
									\
	return orig;							\
}

#define ATOMIC_OPS(op, c_op, asm_op)					\
	ATOMIC_OP(op, c_op, asm_op)					\
	ATOMIC_OP_RETURN(op, c_op, asm_op)				\
	ATOMIC_FETCH_OP(op, c_op, asm_op)

ATOMIC_OPS(add, +=, add)
ATOMIC_OPS(sub, -=, sub)

#undef ATOMIC_OPS
#define ATOMIC_OPS(op, c_op, asm_op)					\
	ATOMIC_OP(op, c_op, asm_op)					\
	ATOMIC_FETCH_OP(op, c_op, asm_op)

ATOMIC_OPS(and, &=, and)
ATOMIC_OPS(andnot, &= ~, bic)
ATOMIC_OPS(or, |=, or)
ATOMIC_OPS(xor, ^=, xor)

#define arch_atomic_andnot		arch_atomic_andnot
#define arch_atomic_fetch_andnot	arch_atomic_fetch_andnot

#undef ATOMIC_OPS
#undef ATOMIC_FETCH_OP
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 */

#ifndef _ASM_ARC_ATOMIC_H
#define _ASM_ARC_ATOMIC_H

#ifndef __ASSEMBLY__

#include <linux/types.h>
#include <linux/compiler.h>
#include <asm/cmpxchg.h>
#include <asm/barrier.h>
#include <asm/smp.h>

#define arch_atomic_read(v)  READ_ONCE((v)->counter)

#ifdef CONFIG_ARC_HAS_LLSC
#include <asm/atomic-llsc.h>
#else
#include <asm/atomic-spinlock.h>
#endif

#define arch_atomic_cmpxchg(v, o, n)					\
({									\
	arch_cmpxchg(&((v)->counter), (o), (n));			\
})

#ifdef arch_cmpxchg_relaxed
#define arch_atomic_cmpxchg_relaxed(v, o, n)				\
({									\
	arch_cmpxchg_relaxed(&((v)->counter), (o), (n));		\
})
#endif

#define arch_atomic_xchg(v, n)						\
({									\
	arch_xchg(&((v)->counter), (n));				\
})

#ifdef arch_xchg_relaxed
#define arch_atomic_xchg_relaxed(v, n)					\
({									\
	arch_xchg_relaxed(&((v)->counter), (n));			\
})
#endif

/*
 * 64-bit atomics
 */
#ifdef CONFIG_GENERIC_ATOMIC64
#include <asm-generic/atomic64.h>
#else
#include <asm/atomic64-arcv2.h>
#endif

#endif	/* !__ASSEMBLY__ */

#endif