code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 */

#include <dt-bindings/gpio/gpio.h>

/ {
	chosen {
		stdout-path = &uart1;
	};

	sound {
		compatible = "fsl,imx6-wandboard-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx6-wandboard-sgtl5000";
		ssi-controller = <&ssi1>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <1>;
		mux-ext-port = <3>;
	};

	sound-spdif {
		compatible = "fsl,imx-audio-spdif";
		model = "imx-spdif";
		spdif-controller = <&spdif>;
		spdif-out;
	};

	reg_1p5v: regulator-1p5v {
		compatible = "regulator-fixed";
		regulator-name = "1P5V";
		regulator-min-microvolt = <1500000>;
		regulator-max-microvolt = <1500000>;
		regulator-always-on;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	reg_2p8v: regulator-2p8v {
		compatible = "regulator-fixed";
		regulator-name = "2P8V";
		regulator-min-microvolt = <2800000>;
		regulator-max-microvolt = <2800000>;
		regulator-always-on;
	};

	reg_2p5v: regulator-2p5v {
		compatible = "regulator-fixed";
		regulator-name = "2P5V";
		regulator-min-microvolt = <2500000>;
		regulator-max-microvolt = <2500000>;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_usb_otg_vbus: regulator-usbotgvbus {
		compatible = "regulator-fixed";
		regulator-name = "usb_otg_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbotgvbus>;
		gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&hdmi {
	ddc-i2c-bus = <&i2c1>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	codec: sgtl5000@a {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mclk>;
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks IMX6QDL_CLK_CKO>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
		lrclk-strength = <3>;
	};

	camera@3c {
		compatible = "ovti,ov5645";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ov5645>;
		reg = <0x3c>;
		clocks = <&clks IMX6QDL_CLK_CKO2>;
		clock-frequency = <24000000>;
		vdddo-supply = <&reg_1p8v>;
		vdda-supply = <&reg_2p8v>;
		vddd-supply = <&reg_1p5v>;
		enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;

		port {
			ov5645_to_mipi_csi2: endpoint {
				remote-endpoint = <&mipi_csi2_in>;
				clock-lanes = <0>;
				data-lanes = <1 2>;
			};
		};
	};
};

&iomuxc {
	pinctrl-names = "default";

	imx6qdl-wandboard {

		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
			>;
		};

		pinctrl_enet: enetgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
			>;
		};

		pinctrl_i2c1_gpio: i2c1gpiogrp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D21__GPIO3_IO21		0x4001b8b0
				MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x4001b8b0
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
			>;
		};

		pinctrl_i2c2_gpio: i2c2gpiogrp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL3__GPIO4_IO12		0x4001b8b0
				MX6QDL_PAD_KEY_ROW3__GPIO4_IO13		0x4001b8b0
			>;
		};

		pinctrl_mclk: mclkgrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0
			>;
		};

		pinctrl_ov5645: ov5645grp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_3__CCM_CLKO2		0x000b0
				MX6QDL_PAD_GPIO_6__GPIO1_IO06		0x1b0b0
				MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x1b0b0
			>;
		};

		pinctrl_spdif: spdifgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_RXD0__SPDIF_OUT		0x1b0b0
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
				MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
				MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
			>;
		};

		pinctrl_usbotg: usbotggrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
			>;
		};

		pinctrl_usbotgvbus: usbotgvbusgrp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x130b0
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17059
				MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10059
				MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17059
				MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17059
				MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17059
				MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17059
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
			>;
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy>;
	phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy: ethernet-phy@1 {
			reg = <1>;
			qca,clk-out-frequency = <125000000>;
		};
	};
};

&mipi_csi {
	status = "okay";

	port@0 {
		reg = <0>;

		mipi_csi2_in: endpoint {
			remote-endpoint = <&ov5645_to_mipi_csi2>;
			clock-lanes = <0>;
			data-lanes = <1 2>;
		};
	};
};

&spdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif>;
	status = "okay";
};

&ssi1 {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	status = "okay";
};

&usbh1 {
	status = "okay";
};

&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	dr_mode = "otg";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2016-2017 Zodiac Inflight Innovations
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>

/ {
	chosen {
		stdout-path = &uart1;
	};

	aliases {
		mdio-gpio0 = &mdio1;
		rtc0 = &ds1341;
	};

	mdio1: mdio {
		compatible = "virtual,mdio-gpio";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mdio1>;
		gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
		         &gpio6 4 GPIO_ACTIVE_HIGH>;

		phy: ethernet-phy@0 {
			pinctrl-0 = <&pinctrl_rmii_phy_irq>;
			pinctrl-names = "default";
			reg = <0>;
			interrupt-parent = <&gpio3>;
			interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
		};
	};

	reg_28p0v: regulator-28p0v {
		compatible = "regulator-fixed";
		regulator-name = "28V_IN";
		regulator-min-microvolt = <28000000>;
		regulator-max-microvolt = <28000000>;
		regulator-always-on;
	};

	reg_12p0v: regulator-12p0v {
		compatible = "regulator-fixed";
		vin-supply = <&reg_28p0v>;
		regulator-name = "12V_MAIN";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
	};

	reg_5p0v_main: regulator-5p0v-main {
		compatible = "regulator-fixed";
		vin-supply = <&reg_12p0v>;
		regulator-name = "5V_MAIN";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
	};

	reg_3p3v_pmic: regulator-3p3v-pmic {
		compatible = "regulator-fixed";
		vin-supply = <&reg_12p0v>;
		regulator-name = "PMIC_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		vin-supply = <&reg_3p3v_pmic>;
		regulator-name = "GEN_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_3p3v_sd: regulator-3p3v-sd {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
		vin-supply = <&reg_3p3v>;
		regulator-name = "3V3_SD";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
		startup-delay-us = <1000>;
		enable-active-high;
		regulator-always-on;
	};

	reg_3p3v_display: regulator-3p3v-display {
		compatible = "regulator-fixed";
		vin-supply = <&reg_12p0v>;
		regulator-name = "3V3_DISPLAY";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_3p3v_ssd: regulator-3p3v-ssd {
		compatible = "regulator-fixed";
		vin-supply = <&reg_12p0v>;
		regulator-name = "3V3_SSD";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	sound1 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "front";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&sound1_codec>;
		simple-audio-card,frame-master = <&sound1_codec>;
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack";
		simple-audio-card,routing =
			"Headphone Jack", "HPA1 HPLEFT",
			"Headphone Jack", "HPA1 HPRIGHT",
			"HPA1 LEFTIN", "HPL",
			"HPA1 RIGHTIN", "HPR";
		simple-audio-card,aux-devs = <&hpa1>;

		sound1_cpu: simple-audio-card,cpu {
			sound-dai = <&ssi2>;
		};

		sound1_codec: simple-audio-card,codec {
			sound-dai = <&codec1>;
			clocks = <&cs2000>;
		};
	};

	sound2 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "periph";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&sound2_codec>;
		simple-audio-card,frame-master = <&sound2_codec>;
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack";
		simple-audio-card,routing =
			"Headphone Jack", "HPA1 HPLEFT",
			"Headphone Jack", "HPA1 HPRIGHT",
			"HPA1 LEFTIN", "HPL",
			"HPA1 RIGHTIN", "HPR";
		simple-audio-card,aux-devs = <&hpa2>;

		sound2_cpu: simple-audio-card,cpu {
			sound-dai = <&ssi1>;
		};

		sound2_codec: simple-audio-card,codec {
			sound-dai = <&codec2>;
			clocks = <&cs2000>;
		};
	};

	panel {
		power-supply = <&reg_3p3v_display>;
		backlight = <&sp_backlight>;
		status = "disabled";

		port {
			panel_in: endpoint {
				remote-endpoint = <&lvds0_out>;
			};
		};
	};

	disp0: disp0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx-parallel-display";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_disp0>;
		status = "disabled";

		port@0 {
			reg = <0>;

			disp0_in_0: endpoint {
				remote-endpoint = <&ipu1_di0_disp0>;
			};
		};

		port@1 {
			reg = <1>;

			disp0_out: endpoint {
				remote-endpoint = <&tc358767_in>;
			};
		};
	};

	cs2000_ref: cs2000-ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};

	cs2000_in_dummy: cs2000-in-dummy {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	edp_refclk: edp-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <19200000>;
	};
};

&clks {
	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
	                  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
	                         <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
};

&cpu0 {
	fsl,soc-operating-points = <
		/* ARM kHz  SOC-PU uV */
		1200000 1300000
		996000	1275000
		852000	1275000
		792000	1200000
		396000	1200000
	>;
};

&reg_arm {
	vin-supply = <&sw1a_reg>;
};

&reg_pu {
	vin-supply = <&sw1c_reg>;
};

&reg_soc {
	vin-supply = <&sw1c_reg>;
};

&ldb {
	lvds-channel@0 {
		port@4 {
			reg = <4>;

			lvds0_out: endpoint {
				remote-endpoint = <&panel_in>;
			};
		};
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	linux,rs485-enabled-at-boot-time;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";

	rave-sp {
		compatible = "zii,rave-sp-rdu2";
		current-speed = <1000000>;
		#address-cells = <1>;
		#size-cells = <1>;

		watchdog {
			compatible = "zii,rave-sp-watchdog";
		};

		sp_backlight: backlight {
			compatible = "zii,rave-sp-backlight";
		};

		pwrbutton {
			compatible = "zii,rave-sp-pwrbutton";
		};

		eeprom@a3 {
			compatible = "zii,rave-sp-eeprom";
			reg = <0xa3 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			zii,eeprom-name = "dds-eeprom";
		};

		eeprom@a4 {
			compatible = "zii,rave-sp-eeprom";
			reg = <0xa4 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			zii,eeprom-name = "main-eeprom";
		};
	};
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
	status = "okay";

	flash@0 {
		compatible = "st,m25p128", "jedec,spi-nor";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&gpio3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio3_hog>;

	usb-emulation-hog {
		gpio-hog;
		gpios = <19 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "usb-emulation";
	};

	usb-mode1-hog {
		gpio-hog;
		gpios = <20 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "usb-mode1";
	};

	usb-pwr-hog {
		gpio-hog;
		gpios = <22 GPIO_ACTIVE_LOW>;
		output-high;
		line-name = "usb-pwr-ctrl-en-n";
	};

	usb-mode2-hog {
		gpio-hog;
		gpios = <23 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "usb-mode2";
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clock-frequency = <100000>;
	status = "okay";

	codec2: codec@18 {
		compatible = "ti,tlv320dac3100";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_codec2>;
		reg = <0x18>;
		#sound-dai-cells = <0>;
		HPVDD-supply = <&reg_3p3v>;
		SPRVDD-supply = <&reg_3p3v>;
		SPLVDD-supply = <&reg_3p3v>;
		AVDD-supply = <&reg_3p3v>;
		IOVDD-supply = <&reg_3p3v>;
		DVDD-supply = <&vgen4_reg>;
		reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
	};

	accel@1c {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_accel>;
		compatible = "fsl,mma8451";
		reg = <0x1c>;
		interrupt-parent = <&gpio1>;
		interrupt-names = "INT2";
		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
		vdd-supply = <&reg_3p3v>;
		vddio-supply = <&reg_3p3v>;
	};

	hpa2: amp@60 {
		compatible = "ti,tpa6130a2";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tpa2>;
		reg = <0x60>;
		power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
		Vdd-supply = <&reg_5p0v_main>;
		sound-name-prefix = "HPA1";
	};

	edp-bridge@68 {
		compatible = "toshiba,tc358767";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tc358767>;
		reg = <0x68>;
		shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
		clock-names = "ref";
		clocks = <&edp_refclk>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <1>;

				tc358767_in: endpoint {
					remote-endpoint = <&disp0_out>;
				};
			};
		};
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clock-frequency = <100000>;
	status = "okay";

	pmic@8 {
		compatible = "fsl,pfuze100";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pfuze100_irq>;
		reg = <0x08>;
		interrupt-parent = <&gpio7>;
		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw1c_reg: sw1c {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3a_reg: sw3a {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1500000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3b_reg: sw3b {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1500000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1500000>;
				regulator-always-on;
			};

			vgen4_reg: vgen4 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			vgen5_reg: vgen5 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <2500000>;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <2800000>;
				regulator-always-on;
			};
		};
	};

	watchdog@38 {
		compatible = "zii,rave-wdt";
		reg = <0x38>;
	};

	temp-sense@48 {
		compatible = "national,lm75";
		reg = <0x48>;
	};

	cs2000: clkgen@4e {
		compatible = "cirrus,cs2000-cp";
		reg = <0x4e>;
		#clock-cells = <0>;
		clock-names = "clk_in", "ref_clk";
		clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
		assigned-clocks = <&cs2000>;
		assigned-clock-rates = <24000000>;
	};

	eeprom@54 {
		compatible = "atmel,24c128";
		reg = <0x54>;
	};

	ds1341: rtc@68 {
		compatible = "dallas,ds1341";
		reg = <0x68>;
	};
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clock-frequency = <400000>;
	status = "okay";

	codec1: codec@18 {
		compatible = "ti,tlv320dac3100";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_codec1>;
		reg = <0x18>;
		#sound-dai-cells = <0>;
		HPVDD-supply = <&reg_3p3v>;
		SPRVDD-supply = <&reg_3p3v>;
		SPLVDD-supply = <&reg_3p3v>;
		AVDD-supply = <&reg_3p3v>;
		IOVDD-supply = <&reg_3p3v>;
		DVDD-supply = <&vgen4_reg>;
		reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
	};

	touchscreen@20 {
		compatible = "syna,rmi4-i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ts>;
		reg = <0x20>;
		interrupt-parent = <&gpio1>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		vdd-supply = <&reg_5p0v_main>;
		vio-supply = <&reg_3p3v>;

		#address-cells = <1>;
		#size-cells = <0>;

		rmi4-f01@1 {
			reg = <0x1>;
			syna,nosleep-mode = <2>;
		};

		rmi4-f11@11 {
			reg = <0x11>;
			touchscreen-inverted-x;
			touchscreen-swapped-x-y;
			syna,sensor-type = <1>;
			syna,delta-x-threshold = <5>;
			syna,delta-y-threshold = <10>;
		};

		rmi4-f12@12 {
			reg = <0x12>;
			touchscreen-inverted-x;
			touchscreen-swapped-x-y;
			syna,sensor-type = <1>;
		};
	};

	touchscreen@2a {
		compatible = "eeti,exc3000";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ts>;
		reg = <0x2a>;
		interrupt-parent = <&gpio1>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		touchscreen-inverted-x;
		touchscreen-swapped-x-y;
		status = "disabled";
	};

	reg_5p0v_user_usb: charger@32 {
		compatible = "microchip,ucs1002";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ucs1002_pins>;
		reg = <0x32>;
		interrupts-extended = <&gpio5 2 IRQ_TYPE_EDGE_BOTH>,
		                      <&gpio3 21 IRQ_TYPE_EDGE_FALLING>;
		interrupt-names = "a_det", "alert";
	};

	hpa1: amp@60 {
		compatible = "ti,tpa6130a2";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tpa1>;
		reg = <0x60>;
		power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
		Vdd-supply = <&reg_5p0v_main>;
		sound-name-prefix = "HPA1";
	};
};

&ipu1_di0_disp0 {
	remote-endpoint = <&disp0_in_0>;
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
	status = "okay";

	host@0 {
		reg = <0 0 0 0 0>;

		#address-cells = <3>;
		#size-cells = <2>;

		i210: i210@0 {
			reg = <0 0 0 0 0>;
		};
	};
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
	disable-wp;
	vmmc-supply = <&reg_3p3v_sd>;
	vqmmc-supply = <&reg_3p3v>;
	no-1-8-v;
	no-sdio;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	bus-width = <4>;
	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
	disable-wp;
	vmmc-supply = <&reg_3p3v_sd>;
	vqmmc-supply = <&reg_3p3v>;
	no-1-8-v;
	no-sdio;
	status = "okay";
};

&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	bus-width = <8>;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_3p3v>;
	no-1-8-v;
	non-removable;
	no-sdio;
	no-sd;
	status = "okay";
};

&sata {
	target-supply = <&reg_3p3v_ssd>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rmii";
	phy-handle = <&phy>;
	phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <100>;
	phy-supply = <&reg_3p3v>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <12500000>;
		suppress-preamble;
		status = "okay";

		switch: switch@0 {
			compatible = "marvell,mv88e6085";
			pinctrl-0 = <&pinctrl_switch_irq>;
			pinctrl-names = "default";
			reg = <0>;
			dsa,member = <0 0>;
			eeprom-length = <512>;
			interrupt-parent = <&gpio6>;
			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
			interrupt-controller;
			#interrupt-cells = <2>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "gigabit_proc";
					phy-handle = <&switchphy0>;
				};

				port@1 {
					reg = <1>;
					label = "netaux";
					phy-handle = <&switchphy1>;
				};

				port@2 {
					reg = <2>;
					label = "cpu";
					ethernet = <&fec>;

					fixed-link {
						speed = <100>;
						full-duplex;
					};
				};

				port@3 {
					reg = <3>;
					label = "netright";
					phy-handle = <&switchphy3>;
				};

				port@4 {
					reg = <4>;
					label = "netleft";
					phy-handle = <&switchphy4>;
				};
			};

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				switchphy0: switchphy@0 {
					reg = <0>;
					interrupt-parent = <&switch>;
					interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
				};

				switchphy1: switchphy@1 {
					reg = <1>;
					interrupt-parent = <&switch>;
					interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
				};

				switchphy2: switchphy@2 {
					reg = <2>;
					interrupt-parent = <&switch>;
					interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
				};

				switchphy3: switchphy@3 {
					reg = <3>;
					interrupt-parent = <&switch>;
					interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
				};

				switchphy4: switchphy@4 {
					reg = <4>;
					interrupt-parent = <&switch>;
					interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
				};
			};
		};
	};
};

&usbh1 {
	vbus-supply = <&reg_5p0v_main>;
	disable-over-current;
	maximum-speed = "full-speed";
	status = "okay";
};

&usbotg {
	vbus-supply = <&reg_5p0v_user_usb>;
	disable-over-current;
	dr_mode = "host";
	status = "okay";
};

&snvs_rtc {
	status = "disabled";
};

&ssi1 {
	status = "okay";
};

&ssi2 {
	status = "okay";
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";

	ssi1 {
		fsl,audmux-port = <0>;
		fsl,port-config = <
			(IMX_AUDMUX_V2_PTCR_SYN |
			 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
			 IMX_AUDMUX_V2_PTCR_TCSEL(2) |
			 IMX_AUDMUX_V2_PTCR_TFSDIR |
			 IMX_AUDMUX_V2_PTCR_TCLKDIR)
			IMX_AUDMUX_V2_PDCR_RXDSEL(2)
		>;
	};

	aud3 {
		fsl,audmux-port = <2>;
		fsl,port-config = <
			IMX_AUDMUX_V2_PTCR_SYN
			IMX_AUDMUX_V2_PDCR_RXDSEL(0)
		>;
	};

	ssi2 {
		fsl,audmux-port = <1>;
		fsl,port-config = <
			(IMX_AUDMUX_V2_PTCR_SYN |
			 IMX_AUDMUX_V2_PTCR_TFSEL(4) |
			 IMX_AUDMUX_V2_PTCR_TCSEL(4) |
			 IMX_AUDMUX_V2_PTCR_TFSDIR |
			 IMX_AUDMUX_V2_PTCR_TCLKDIR)
			IMX_AUDMUX_V2_PDCR_RXDSEL(4)
		>;
	};

	aud5 {
		fsl,audmux-port = <4>;
		fsl,port-config = <
			IMX_AUDMUX_V2_PTCR_SYN
			IMX_AUDMUX_V2_PDCR_RXDSEL(1)
		>;
	};
};

&iomuxc {
	pinctrl_accel: accelgrp {
		fsl,pins = <
			MX6QDL_PAD_SD1_CLK__GPIO1_IO20		0x4001b000
		>;
	};

	pinctrl_audmux: audmuxgrp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL0__AUD5_TXC		0x130b0
			MX6QDL_PAD_KEY_ROW0__AUD5_TXD		0x130b0
			MX6QDL_PAD_KEY_COL1__AUD5_TXFS		0x130b0
			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x130b0
			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
		>;
	};

	pinctrl_codec1: dac1grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x40000038
		>;
	};

	pinctrl_codec2: dac2grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x40000038
		>;
	};

	pinctrl_disp0: disp0grp {
		fsl,pins = <
			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f9
			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f9
			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f9
			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x100f9
			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x100f9
			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x100f9
			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x100f9
			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x100f9
			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x100f9
			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x100f9
			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x100f9
			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x100f9
			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x100f9
			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x100f9
			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x100f9
			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x100f9
			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x100f9
			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x100f9
			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x100f9
			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x100f9
			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x100f9
			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x100f9
			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x100f9
			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x100f9
			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x100f9
			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x100f9
			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x100f9
		>;
	};

	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x1b0b1
		>;
	};

	pinctrl_enet: enetgrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x000b1
			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b1
			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x100f5
			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x100f5
			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x100c0
			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x100c0
			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x100f5
			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x100f5
			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x40010040
			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x100b0
			MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23	0x1b0b0
		>;
	};

	pinctrl_gpio3_hog: gpio3hoggrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x1b0b0
			MX6QDL_PAD_EIM_D20__GPIO3_IO20		0x1b0b0
			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0
			MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x1b0b0
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA		0x4001b811
			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL		0x4001b811
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b811
			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b811
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b811
			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b811
		>;
	};

	pinctrl_mdio1: bitbangmdiogrp {
		fsl,pins = <
			/* Bitbang MDIO for DEB Switch */
			MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05	0x4001b030
			MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04	0x40018830
		>;
	};

	pinctrl_pcie: pciegrp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x10038
		>;
	};

	pinctrl_pfuze100_irq: pfuze100grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x40010000
		>;
	};

	pinctrl_reg_3p3v_sd: mmcsupply1grp {
		fsl,pins = <
			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x858
		>;
	};

	pinctrl_rmii_phy_irq: phygrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D30__GPIO3_IO30		0x40010000
		>;
	};

	pinctrl_switch_irq: switchgrp {
		fsl,pins = <
			MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03	0x4001b000
		>;
	};

	pinctrl_tc358767: tc358767grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_9__GPIO1_IO09		0x10
		>;
	};

	pinctrl_tpa1: tpa6130-1grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x40000038
		>;
	};

	pinctrl_tpa2: tpa6130-2grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x40000038
		>;
	};

	pinctrl_ts: tsgrp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_8__GPIO1_IO08		0x1b0b0
			MX6QDL_PAD_GPIO_7__GPIO1_IO07		0x1b0b0
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
			MX6QDL_PAD_EIM_D31__UART3_RTS_B		0x1b0b1
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA	0x1b0b1
			MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA	0x1b0b1
		>;
	};

	pinctrl_ucs1002_pins: ucs1002grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_A25__GPIO5_IO02  	0x1b0b0
			MX6QDL_PAD_EIM_D21__GPIO3_IO21  	0x1b0b0
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x10059
			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10069
			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
			MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x40010040
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x10059
			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10069
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
			MX6QDL_PAD_NANDF_D0__GPIO2_IO00		0x40010040

		>;
	};

	pinctrl_usdhc4: usdhc4grp {
		fsl,pins = <
			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
			MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
			MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
			MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
			MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
			MX6QDL_PAD_NANDF_ALE__SD4_RESET		0x1b0b1
		>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2011 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.

#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 */
	chosen {};

	aliases {
		ethernet0 = &fec;
		can0 = &can1;
		can1 = &can2;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		gpio6 = &gpio7;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		ipu0 = &ipu1;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		mmc3 = &usdhc4;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &ecspi3;
		spi3 = &ecspi4;
		usb0 = &usbotg;
		usb1 = &usbh1;
		usb2 = &usbh2;
		usb3 = &usbh3;
		usbphy0 = &usbphy1;
		usbphy1 = &usbphy2;
	};

	clocks {
		ckil {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
		};
	};

	ldb: ldb {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
		gpr = <&gpr>;
		status = "disabled";

		lvds-channel@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			status = "disabled";

			port@0 {
				reg = <0>;

				lvds0_mux_0: endpoint {
					remote-endpoint = <&ipu1_di0_lvds0>;
				};
			};

			port@1 {
				reg = <1>;

				lvds0_mux_1: endpoint {
					remote-endpoint = <&ipu1_di1_lvds0>;
				};
			};
		};

		lvds-channel@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			status = "disabled";

			port@0 {
				reg = <0>;

				lvds1_mux_0: endpoint {
					remote-endpoint = <&ipu1_di0_lvds1>;
				};
			};

			port@1 {
				reg = <1>;

				lvds1_mux_1: endpoint {
					remote-endpoint = <&ipu1_di1_lvds1>;
				};
			};
		};
	};

	pmu: pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupt-parent = <&gpc>;
		interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
	};

	usbphynop1: usbphynop1 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};

	usbphynop2: usbphynop2 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gpc>;
		ranges;

		dma_apbh: dma-apbh@110000 {
			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
			reg = <0x00110000 0x2000>;
			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
				     <0 13 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
			#dma-cells = <1>;
			dma-channels = <4>;
			clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
		};

		gpmi: nand-controller@112000 {
			compatible = "fsl,imx6q-gpmi-nand";
			reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
			reg-names = "gpmi-nand", "bch";
			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "bch";
			clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
				 <&clks IMX6QDL_CLK_GPMI_APB>,
				 <&clks IMX6QDL_CLK_GPMI_BCH>,
				 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
				 <&clks IMX6QDL_CLK_PER1_BCH>;
			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
				      "gpmi_bch_apb", "per1_bch";
			dmas = <&dma_apbh 0>;
			dma-names = "rx-tx";
			status = "disabled";
		};

		hdmi: hdmi@120000 {
			reg = <0x00120000 0x9000>;
			interrupts = <0 115 0x04>;
			gpr = <&gpr>;
			clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
				 <&clks IMX6QDL_CLK_HDMI_ISFR>;
			clock-names = "iahb", "isfr";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					hdmi_mux_0: endpoint {
						remote-endpoint = <&ipu1_di0_hdmi>;
					};
				};

				port@1 {
					reg = <1>;

					hdmi_mux_1: endpoint {
						remote-endpoint = <&ipu1_di1_hdmi>;
					};
				};
			};
		};

		gpu_3d: gpu@130000 {
			compatible = "vivante,gc";
			reg = <0x00130000 0x4000>;
			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
				 <&clks IMX6QDL_CLK_GPU3D_CORE>,
				 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
			clock-names = "bus", "core", "shader";
			power-domains = <&pd_pu>;
			#cooling-cells = <2>;
		};

		gpu_2d: gpu@134000 {
			compatible = "vivante,gc";
			reg = <0x00134000 0x4000>;
			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
			clock-names = "bus", "core";
			power-domains = <&pd_pu>;
			#cooling-cells = <2>;
		};

		timer@a00600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x00a00600 0x20>;
			interrupts = <1 13 0xf01>;
			interrupt-parent = <&intc>;
			clocks = <&clks IMX6QDL_CLK_TWD>;
		};

		intc: interrupt-controller@a01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x00a01000 0x1000>,
			      <0x00a00100 0x100>;
			interrupt-parent = <&intc>;
		};

		L2: cache-controller@a02000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a02000 0x1000>;
			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-level = <2>;
			arm,tag-latency = <4 2 3>;
			arm,data-latency = <4 2 3>;
			arm,shared-override;
		};

		pcie: pcie@1ffc000 {
			compatible = "fsl,imx6q-pcie";
			reg = <0x01ffc000 0x04000>,
			      <0x01f00000 0x80000>;
			reg-names = "dbi", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			bus-range = <0x00 0xff>;
			ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>, /* downstream I/O */
				 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
			num-lanes = <1>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
				 <&clks IMX6QDL_CLK_LVDS1_GATE>,
				 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
			clock-names = "pcie", "pcie_bus", "pcie_phy";
			status = "disabled";
		};

		aips1: bus@2000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02000000 0x100000>;
			ranges;

			spba-bus@2000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x02000000 0x40000>;
				ranges;

				spdif: spdif@2004000 {
					compatible = "fsl,imx35-spdif";
					reg = <0x02004000 0x4000>;
					interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&sdma 14 18 0>,
					       <&sdma 15 18 0>;
					dma-names = "rx", "tx";
					clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
						 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
						 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
					clock-names = "core",  "rxtx0",
						      "rxtx1", "rxtx2",
						      "rxtx3", "rxtx4",
						      "rxtx5", "rxtx6",
						      "rxtx7", "spba";
					status = "disabled";
				};

				ecspi1: spi@2008000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02008000 0x4000>;
					interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6QDL_CLK_ECSPI1>,
						 <&clks IMX6QDL_CLK_ECSPI1>;
					clock-names = "ipg", "per";
					dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi2: spi@200c000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x0200c000 0x4000>;
					interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6QDL_CLK_ECSPI2>,
						 <&clks IMX6QDL_CLK_ECSPI2>;
					clock-names = "ipg", "per";
					dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi3: spi@2010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02010000 0x4000>;
					interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6QDL_CLK_ECSPI3>,
						 <&clks IMX6QDL_CLK_ECSPI3>;
					clock-names = "ipg", "per";
					dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi4: spi@2014000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02014000 0x4000>;
					interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6QDL_CLK_ECSPI4>,
						 <&clks IMX6QDL_CLK_ECSPI4>;
					clock-names = "ipg", "per";
					dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart1: serial@2020000 {
					compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02020000 0x4000>;
					interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6QDL_CLK_UART_IPG>,
						 <&clks IMX6QDL_CLK_UART_SERIAL>;
					clock-names = "ipg", "per";
					dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				esai: esai@2024000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx35-esai";
					reg = <0x02024000 0x4000>;
					interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
						 <&clks IMX6QDL_CLK_ESAI_MEM>,
						 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
						 <&clks IMX6QDL_CLK_ESAI_IPG>,
						 <&clks IMX6QDL_CLK_SPBA>;
					clock-names = "core", "mem", "extal", "fsys", "spba";
					dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ssi1: ssi@2028000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6q-ssi",
							"fsl,imx51-ssi";
					reg = <0x02028000 0x4000>;
					interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
						 <&clks IMX6QDL_CLK_SSI1>;
					clock-names = "ipg", "baud";
					dmas = <&sdma 37 1 0>,
					       <&sdma 38 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				ssi2: ssi@202c000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6q-ssi",
							"fsl,imx51-ssi";
					reg = <0x0202c000 0x4000>;
					interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
						 <&clks IMX6QDL_CLK_SSI2>;
					clock-names = "ipg", "baud";
					dmas = <&sdma 41 1 0>,
					       <&sdma 42 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				ssi3: ssi@2030000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6q-ssi",
							"fsl,imx51-ssi";
					reg = <0x02030000 0x4000>;
					interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
						 <&clks IMX6QDL_CLK_SSI3>;
					clock-names = "ipg", "baud";
					dmas = <&sdma 45 1 0>,
					       <&sdma 46 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				asrc: asrc@2034000 {
					compatible = "fsl,imx53-asrc";
					reg = <0x02034000 0x4000>;
					interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
						<&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
						<&clks IMX6QDL_CLK_SPBA>;
					clock-names = "mem", "ipg", "asrck_0",
						"asrck_1", "asrck_2", "asrck_3", "asrck_4",
						"asrck_5", "asrck_6", "asrck_7", "asrck_8",
						"asrck_9", "asrck_a", "asrck_b", "asrck_c",
						"asrck_d", "asrck_e", "asrck_f", "spba";
					dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
						<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
					dma-names = "rxa", "rxb", "rxc",
							"txa", "txb", "txc";
					fsl,asrc-rate  = <48000>;
					fsl,asrc-width = <16>;
					status = "okay";
				};

				spba-bus@203c000 {
					reg = <0x0203c000 0x4000>;
				};
			};

			vpu: vpu@2040000 {
				compatible = "cnm,coda960";
				reg = <0x02040000 0x3c000>;
				interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
					     <0 3 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "bit", "jpeg";
				clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
					 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
				clock-names = "per", "ahb";
				power-domains = <&pd_pu>;
				resets = <&src 1>;
				iram = <&ocram>;
			};

			aipstz@207c000 { /* AIPSTZ1 */
				reg = <0x0207c000 0x4000>;
			};

			pwm1: pwm@2080000 {
				#pwm-cells = <3>;
				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
				reg = <0x02080000 0x4000>;
				interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_IPG>,
					 <&clks IMX6QDL_CLK_PWM1>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			pwm2: pwm@2084000 {
				#pwm-cells = <3>;
				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
				reg = <0x02084000 0x4000>;
				interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_IPG>,
					 <&clks IMX6QDL_CLK_PWM2>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			pwm3: pwm@2088000 {
				#pwm-cells = <3>;
				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
				reg = <0x02088000 0x4000>;
				interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_IPG>,
					 <&clks IMX6QDL_CLK_PWM3>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			pwm4: pwm@208c000 {
				#pwm-cells = <3>;
				compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
				reg = <0x0208c000 0x4000>;
				interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_IPG>,
					 <&clks IMX6QDL_CLK_PWM4>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			can1: can@2090000 {
				compatible = "fsl,imx6q-flexcan";
				reg = <0x02090000 0x4000>;
				interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
					 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
				clock-names = "ipg", "per";
				fsl,stop-mode = <&gpr 0x34 28>;
				status = "disabled";
			};

			can2: can@2094000 {
				compatible = "fsl,imx6q-flexcan";
				reg = <0x02094000 0x4000>;
				interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
					 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
				clock-names = "ipg", "per";
				fsl,stop-mode = <&gpr 0x34 29>;
				status = "disabled";
			};

			gpt: timer@2098000 {
				compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
				reg = <0x02098000 0x4000>;
				interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
					 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
					 <&clks IMX6QDL_CLK_GPT_3M>;
				clock-names = "ipg", "per", "osc_per";
			};

			gpio1: gpio@209c000 {
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
				reg = <0x0209c000 0x4000>;
				interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
					     <0 67 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@20a0000 {
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
				reg = <0x020a0000 0x4000>;
				interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
					     <0 69 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@20a4000 {
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
				reg = <0x020a4000 0x4000>;
				interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
					     <0 71 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@20a8000 {
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
				reg = <0x020a8000 0x4000>;
				interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
					     <0 73 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio5: gpio@20ac000 {
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
				reg = <0x020ac000 0x4000>;
				interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
					     <0 75 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio6: gpio@20b0000 {
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
				reg = <0x020b0000 0x4000>;
				interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
					     <0 77 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio7: gpio@20b4000 {
				compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
				reg = <0x020b4000 0x4000>;
				interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
					     <0 79 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			kpp: keypad@20b8000 {
				compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
				reg = <0x020b8000 0x4000>;
				interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_IPG>;
				status = "disabled";
			};

			wdog1: watchdog@20bc000 {
				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
				reg = <0x020bc000 0x4000>;
				interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_IPG>;
			};

			wdog2: watchdog@20c0000 {
				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
				reg = <0x020c0000 0x4000>;
				interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_IPG>;
				status = "disabled";
			};

			clks: clock-controller@20c4000 {
				compatible = "fsl,imx6q-ccm";
				reg = <0x020c4000 0x4000>;
				interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
					     <0 88 IRQ_TYPE_LEVEL_HIGH>;
				#clock-cells = <1>;
			};

			anatop: anatop@20c8000 {
				compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
				reg = <0x020c8000 0x1000>;
				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
					     <0 54 IRQ_TYPE_LEVEL_HIGH>,
					     <0 127 IRQ_TYPE_LEVEL_HIGH>;

				reg_vdd1p1: regulator-1p1 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd1p1";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
					anatop-reg-offset = <0x110>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <4>;
					anatop-min-voltage = <800000>;
					anatop-max-voltage = <1375000>;
					anatop-enable-bit = <0>;
				};

				reg_vdd3p0: regulator-3p0 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd3p0";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <3150000>;
					regulator-always-on;
					anatop-reg-offset = <0x120>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
					anatop-min-voltage = <2625000>;
					anatop-max-voltage = <3400000>;
					anatop-enable-bit = <0>;
				};

				reg_vdd2p5: regulator-2p5 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd2p5";
					regulator-min-microvolt = <2250000>;
					regulator-max-microvolt = <2750000>;
					regulator-always-on;
					anatop-reg-offset = <0x130>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
					anatop-min-voltage = <2100000>;
					anatop-max-voltage = <2875000>;
					anatop-enable-bit = <0>;
				};

				reg_arm: regulator-vddcore {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddarm";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <0>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <24>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				reg_pu: regulator-vddpu {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddpu";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-enable-ramp-delay = <380>;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <9>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <26>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				reg_soc: regulator-vddsoc {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddsoc";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <18>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <28>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				tempmon: tempmon {
					compatible = "fsl,imx6q-tempmon";
					interrupt-parent = <&gpc>;
					interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
					fsl,tempmon = <&anatop>;
					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
					nvmem-cell-names = "calib", "temp_grade";
					clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
					#thermal-sensor-cells = <0>;
				};
			};

			usbphy1: usbphy@20c9000 {
				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
				reg = <0x020c9000 0x1000>;
				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_USBPHY1>;
				fsl,anatop = <&anatop>;
			};

			usbphy2: usbphy@20ca000 {
				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
				reg = <0x020ca000 0x1000>;
				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_USBPHY2>;
				fsl,anatop = <&anatop>;
			};

			snvs: snvs@20cc000 {
				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
				reg = <0x020cc000 0x4000>;

				snvs_rtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap = <&snvs>;
					offset = <0x34>;
					interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
						     <0 20 IRQ_TYPE_LEVEL_HIGH>;
				};

				snvs_poweroff: snvs-poweroff {
					compatible = "syscon-poweroff";
					regmap = <&snvs>;
					offset = <0x38>;
					value = <0x60>;
					mask = <0x60>;
					status = "disabled";
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
					linux,keycode = <KEY_POWER>;
					wakeup-source;
					status = "disabled";
				};

				snvs_lpgpr: snvs-lpgpr {
					compatible = "fsl,imx6q-snvs-lpgpr";
				};
			};

			epit1: epit@20d0000 { /* EPIT1 */
				reg = <0x020d0000 0x4000>;
				interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			epit2: epit@20d4000 { /* EPIT2 */
				reg = <0x020d4000 0x4000>;
				interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
			};

			src: reset-controller@20d8000 {
				compatible = "fsl,imx6q-src", "fsl,imx51-src";
				reg = <0x020d8000 0x4000>;
				interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
					     <0 96 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};

			gpc: gpc@20dc000 {
				compatible = "fsl,imx6q-gpc";
				reg = <0x020dc000 0x4000>;
				interrupt-controller;
				#interrupt-cells = <3>;
				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-parent = <&intc>;
				clocks = <&clks IMX6QDL_CLK_IPG>;
				clock-names = "ipg";

				pgc {
					#address-cells = <1>;
					#size-cells = <0>;

					power-domain@0 {
						reg = <0>;
						#power-domain-cells = <0>;
					};
					pd_pu: power-domain@1 {
						reg = <1>;
						#power-domain-cells = <0>;
						power-supply = <&reg_pu>;
						clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
						         <&clks IMX6QDL_CLK_GPU3D_SHADER>,
						         <&clks IMX6QDL_CLK_GPU2D_CORE>,
						         <&clks IMX6QDL_CLK_GPU2D_AXI>,
						         <&clks IMX6QDL_CLK_OPENVG_AXI>,
						         <&clks IMX6QDL_CLK_VPU_AXI>;
					};
				};
			};

			gpr: iomuxc-gpr@20e0000 {
				compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
				reg = <0x20e0000 0x38>;

				mux: mux-controller {
					compatible = "mmio-mux";
					#mux-control-cells = <1>;
				};
			};

			iomuxc: pinctrl@20e0000 {
				compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
				reg = <0x20e0000 0x4000>;
			};

			dcic1: dcic@20e4000 {
				reg = <0x020e4000 0x4000>;
				interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
			};

			dcic2: dcic@20e8000 {
				reg = <0x020e8000 0x4000>;
				interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
			};

			sdma: dma-controller@20ec000 {
				compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
				reg = <0x020ec000 0x4000>;
				interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_IPG>,
					 <&clks IMX6QDL_CLK_SDMA>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
			};
		};

		aips2: bus@2100000 { /* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02100000 0x100000>;
			ranges;

			crypto: crypto@2100000 {
				compatible = "fsl,sec-v4.0";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x2100000 0x10000>;
				ranges = <0 0x2100000 0x10000>;
				clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
					 <&clks IMX6QDL_CLK_CAAM_ACLK>,
					 <&clks IMX6QDL_CLK_CAAM_IPG>,
					 <&clks IMX6QDL_CLK_EIM_SLOW>;
				clock-names = "mem", "aclk", "ipg", "emi_slow";

				sec_jr0: jr@1000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x1000 0x1000>;
					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr1: jr@2000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x2000 0x1000>;
					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			aipstz@217c000 { /* AIPSTZ2 */
				reg = <0x0217c000 0x4000>;
			};

			usbotg: usb@2184000 {
				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
				reg = <0x02184000 0x200>;
				interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_USBOH3>;
				fsl,usbphy = <&usbphy1>;
				fsl,usbmisc = <&usbmisc 0>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbh1: usb@2184200 {
				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
				reg = <0x02184200 0x200>;
				interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_USBOH3>;
				fsl,usbphy = <&usbphy2>;
				fsl,usbmisc = <&usbmisc 1>;
				dr_mode = "host";
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbh2: usb@2184400 {
				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
				reg = <0x02184400 0x200>;
				interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_USBOH3>;
				fsl,usbphy = <&usbphynop1>;
				phy_type = "hsic";
				fsl,usbmisc = <&usbmisc 2>;
				dr_mode = "host";
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbh3: usb@2184600 {
				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
				reg = <0x02184600 0x200>;
				interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_USBOH3>;
				fsl,usbphy = <&usbphynop2>;
				phy_type = "hsic";
				fsl,usbmisc = <&usbmisc 3>;
				dr_mode = "host";
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbmisc: usbmisc@2184800 {
				#index-cells = <1>;
				compatible = "fsl,imx6q-usbmisc";
				reg = <0x02184800 0x200>;
				clocks = <&clks IMX6QDL_CLK_USBOH3>;
			};

			fec: ethernet@2188000 {
				compatible = "fsl,imx6q-fec";
				reg = <0x02188000 0x4000>;
				interrupt-names = "int0", "pps";
				interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
					     <0 119 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_ENET>,
					 <&clks IMX6QDL_CLK_ENET>,
					 <&clks IMX6QDL_CLK_ENET_REF>,
					 <&clks IMX6QDL_CLK_ENET_REF>;
				clock-names = "ipg", "ahb", "ptp", "enet_out";
				fsl,stop-mode = <&gpr 0x34 27>;
				status = "disabled";
			};

			mlb@218c000 {
				reg = <0x0218c000 0x4000>;
				interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
					     <0 117 IRQ_TYPE_LEVEL_HIGH>,
					     <0 126 IRQ_TYPE_LEVEL_HIGH>;
			};

			usdhc1: mmc@2190000 {
				compatible = "fsl,imx6q-usdhc";
				reg = <0x02190000 0x4000>;
				interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_USDHC1>,
					 <&clks IMX6QDL_CLK_USDHC1>,
					 <&clks IMX6QDL_CLK_USDHC1>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@2194000 {
				compatible = "fsl,imx6q-usdhc";
				reg = <0x02194000 0x4000>;
				interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_USDHC2>,
					 <&clks IMX6QDL_CLK_USDHC2>,
					 <&clks IMX6QDL_CLK_USDHC2>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc3: mmc@2198000 {
				compatible = "fsl,imx6q-usdhc";
				reg = <0x02198000 0x4000>;
				interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_USDHC3>,
					 <&clks IMX6QDL_CLK_USDHC3>,
					 <&clks IMX6QDL_CLK_USDHC3>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc4: mmc@219c000 {
				compatible = "fsl,imx6q-usdhc";
				reg = <0x0219c000 0x4000>;
				interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_USDHC4>,
					 <&clks IMX6QDL_CLK_USDHC4>,
					 <&clks IMX6QDL_CLK_USDHC4>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			i2c1: i2c@21a0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
				reg = <0x021a0000 0x4000>;
				interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_I2C1>;
				status = "disabled";
			};

			i2c2: i2c@21a4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
				reg = <0x021a4000 0x4000>;
				interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_I2C2>;
				status = "disabled";
			};

			i2c3: i2c@21a8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
				reg = <0x021a8000 0x4000>;
				interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_I2C3>;
				status = "disabled";
			};

			romcp@21ac000 {
				reg = <0x021ac000 0x4000>;
			};

			mmdc0: memory-controller@21b0000 { /* MMDC0 */
				compatible = "fsl,imx6q-mmdc";
				reg = <0x021b0000 0x4000>;
				clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
			};

			mmdc1: memory-controller@21b4000 { /* MMDC1 */
				compatible = "fsl,imx6q-mmdc";
				reg = <0x021b4000 0x4000>;
				status = "disabled";
			};

			weim: weim@21b8000 {
				#address-cells = <2>;
				#size-cells = <1>;
				compatible = "fsl,imx6q-weim";
				reg = <0x021b8000 0x4000>;
				interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
				fsl,weim-cs-gpr = <&gpr>;
				status = "disabled";
			};

			ocotp: efuse@21bc000 {
				compatible = "fsl,imx6q-ocotp", "syscon";
				reg = <0x021bc000 0x4000>;
				clocks = <&clks IMX6QDL_CLK_IIM>;
				#address-cells = <1>;
				#size-cells = <1>;

				cpu_speed_grade: speed-grade@10 {
					reg = <0x10 4>;
				};

				tempmon_calib: calib@38 {
					reg = <0x38 4>;
				};

				tempmon_temp_grade: temp-grade@20 {
					reg = <0x20 4>;
				};
			};

			tzasc@21d0000 { /* TZASC1 */
				reg = <0x021d0000 0x4000>;
				interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
			};

			tzasc@21d4000 { /* TZASC2 */
				reg = <0x021d4000 0x4000>;
				interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
			};

			audmux: audmux@21d8000 {
				compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
				reg = <0x021d8000 0x4000>;
				status = "disabled";
			};

			mipi_csi: mipi@21dc000 {
				compatible = "fsl,imx6-mipi-csi2";
				reg = <0x021dc000 0x4000>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <0 100 0x04>, <0 101 0x04>;
				clocks = <&clks IMX6QDL_CLK_HSI_TX>,
					 <&clks IMX6QDL_CLK_VIDEO_27M>,
					 <&clks IMX6QDL_CLK_EIM_PODF>;
				clock-names = "dphy", "ref", "pix";
				status = "disabled";
			};

			mipi_dsi: mipi@21e0000 {
				reg = <0x021e0000 0x4000>;
				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						mipi_mux_0: endpoint {
							remote-endpoint = <&ipu1_di0_mipi>;
						};
					};

					port@1 {
						reg = <1>;

						mipi_mux_1: endpoint {
							remote-endpoint = <&ipu1_di1_mipi>;
						};
					};
				};
			};

			vdoa@21e4000 {
				compatible = "fsl,imx6q-vdoa";
				reg = <0x021e4000 0x4000>;
				interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_VDOA>;
			};

			uart2: serial@21e8000 {
				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021e8000 0x4000>;
				interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_UART_IPG>,
					 <&clks IMX6QDL_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart3: serial@21ec000 {
				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021ec000 0x4000>;
				interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_UART_IPG>,
					 <&clks IMX6QDL_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart4: serial@21f0000 {
				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021f0000 0x4000>;
				interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_UART_IPG>,
					 <&clks IMX6QDL_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart5: serial@21f4000 {
				compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021f4000 0x4000>;
				interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6QDL_CLK_UART_IPG>,
					 <&clks IMX6QDL_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};
		};

		ipu1: ipu@2400000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,imx6q-ipu";
			reg = <0x02400000 0x400000>;
			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
				     <0 5 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6QDL_CLK_IPU1>,
				 <&clks IMX6QDL_CLK_IPU1_DI0>,
				 <&clks IMX6QDL_CLK_IPU1_DI1>;
			clock-names = "bus", "di0", "di1";
			resets = <&src 2>;

			ipu1_csi0: port@0 {
				reg = <0>;

				ipu1_csi0_from_ipu1_csi0_mux: endpoint {
					remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
				};
			};

			ipu1_csi1: port@1 {
				reg = <1>;
			};

			ipu1_di0: port@2 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <2>;

				ipu1_di0_disp0: endpoint@0 {
					reg = <0>;
				};

				ipu1_di0_hdmi: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&hdmi_mux_0>;
				};

				ipu1_di0_mipi: endpoint@2 {
					reg = <2>;
					remote-endpoint = <&mipi_mux_0>;
				};

				ipu1_di0_lvds0: endpoint@3 {
					reg = <3>;
					remote-endpoint = <&lvds0_mux_0>;
				};

				ipu1_di0_lvds1: endpoint@4 {
					reg = <4>;
					remote-endpoint = <&lvds1_mux_0>;
				};
			};

			ipu1_di1: port@3 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <3>;

				ipu1_di1_disp1: endpoint@0 {
					reg = <0>;
				};

				ipu1_di1_hdmi: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&hdmi_mux_1>;
				};

				ipu1_di1_mipi: endpoint@2 {
					reg = <2>;
					remote-endpoint = <&mipi_mux_1>;
				};

				ipu1_di1_lvds0: endpoint@3 {
					reg = <3>;
					remote-endpoint = <&lvds0_mux_1>;
				};

				ipu1_di1_lvds1: endpoint@4 {
					reg = <4>;
					remote-endpoint = <&lvds1_mux_1>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2015-2021 TQ-Systems GmbH
 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
 */
/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include "imx6qp-tqma6b.dtsi"
#include "imx6qdl-mba6.dtsi"
#include "imx6qdl-mba6b.dtsi"
#include "imx6q-mba6.dtsi"

/ {
	model = "TQ TQMa6QP on MBa6x";
	compatible = "tq,imx6qp-mba6x-b", "tq,mba6b",
		     "tq,imx6qp-tqma6qp-b", "fsl,imx6qp";
};


code:
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
 * Copyright 2016 Boundary Devices, Inc.
 */

/dts-v1/;

#include "imx6qp.dtsi"
#include "imx6qdl-nitrogen6_max.dtsi"

/ {
	model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX Board";
	compatible = "boundary,imx6qp-nitrogen6_max", "fsl,imx6qp";
};

&pcie {
	status = "disabled";
};

&sata {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
 * Copyright 2017 Boundary Devices, Inc.
 */

/dts-v1/;

#include "imx6qp.dtsi"
#include "imx6qdl-nitrogen6_som2.dtsi"

/ {
	model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_SOM2 Board";
	compatible = "boundary,imx6qp-nitrogen6_som2", "fsl,imx6qp";
};

&sata {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2018 PHYTEC Messtechnik GmbH
 * Author: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
 */

/dts-v1/;
#include "imx6qp.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
#include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"

/ {
	model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
	compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06",
		     "phytec,imx6qdl-pcm058", "fsl,imx6qp";

	chosen {
		stdout-path = &uart2;
	};
};

&can1 {
	status = "okay";
};

&fec {
	status = "okay";
};

&gpmi {
	status = "okay";
};

&hdmi {
	status = "okay";
};

&i2c1 {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&i2c_rtc {
	status = "okay";
};

&m25p80 {
	status = "okay";
};

&pcie {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&usbh1 {
	status = "okay";
};

&usbotg {
	status = "okay";
};

&usdhc1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright (c) 2018 Protonic Holland
 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6qp.dtsi"

/ {
	model = "Protonic WD3 board";
	compatible = "prt,prtwd3", "fsl,imx6qp";

	chosen {
		stdout-path = &uart4;
	};

	memory@10000000 {
		device_type = "memory";
		reg = <0x10000000 0x20000000>;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	clock_ksz8081: clock-ksz8081 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
	};

	clock_ksz9031: clock-ksz9031 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	clock_mcp251xfd: clock-mcp251xfd {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <20000000>;
	};

	clock_sja1105: clock-sja1105 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	mdio {
		compatible = "virtual,mdio-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mdio>;

		#address-cells = <1>;
		#size-cells = <0>;
		gpios = <&gpio5 6 GPIO_ACTIVE_HIGH
			 &gpio5 7 GPIO_ACTIVE_HIGH>;

		/* Microchip KSZ8081 */
		usbeth_phy: ethernet-phy@3 {
			reg = <0x3>;

			interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>;
			reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
			reset-assert-us = <500>;
			reset-deassert-us = <1000>;
			clocks = <&clock_ksz8081>;
			clock-names = "rmii-ref";
			micrel,led-mode = <0>;
		};

		tja1102_phy0: ethernet-phy@4 {
			reg = <0x4>;

			interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
			reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
			reset-assert-us = <20>;
			reset-deassert-us = <2000>;
			#address-cells = <1>;
			#size-cells = <0>;

			tja1102_phy1: ethernet-phy@5 {
				reg = <0x5>;

				interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
			};
		};
	};

	reg_5v0: regulator-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_otg_vbus: regulator-otg-vbus {
		compatible = "regulator-fixed";
		regulator-name = "otg-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq {
		compatible = "mmc-pwrseq-simple";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_wifi_npd>;
		reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can1>;
	xceiver-supply = <&reg_5v0>;
	status = "okay";
};

&ecspi2 {
	cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	status = "okay";

	switch@0 {
		compatible = "nxp,sja1105q";
		reg = <0>;
		spi-max-frequency = <4000000>;
		spi-rx-delay-us = <1>;
		spi-tx-delay-us = <1>;
		spi-cpha;

		reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;

		clocks = <&clock_sja1105>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				label = "usb";
				phy-handle = <&usbeth_phy>;
				phy-mode = "rmii";
			};

			port@1 {
				reg = <1>;
				label = "t1slave";
				phy-handle = <&tja1102_phy1>;
				phy-mode = "rmii";
			};

			port@2 {
				reg = <2>;
				label = "t1master";
				phy-handle = <&tja1102_phy0>;
				phy-mode = "rmii";

			};

			port@3 {
				reg = <3>;
				label = "rj45";
				phy-handle = <&rgmii_phy>;
				phy-mode = "rgmii-id";
			};

			port@4 {
				reg = <4>;
				label = "cpu";
				ethernet = <&fec>;
				phy-mode = "rgmii-id";
				rx-internal-delay-ps = <2000>;
				tx-internal-delay-ps = <2000>;

				fixed-link {
					speed = <100>;
					full-duplex;
				};
			};
		};
	};
};

&ecspi3 {
	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	status = "okay";

	can@0 {
		compatible = "microchip,mcp251xfd";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_can2>;
		reg = <0>;
		clocks = <&clock_mcp251xfd>;
		spi-max-frequency = <10000000>;
		interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>;
	assigned-clock-rates = <125000000>;
	status = "okay";

	phy-mode = "rgmii";

	fixed-link {
		speed = <100>;
		full-duplex;
	};

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		/* Microchip KSZ9031 */
		rgmii_phy: ethernet-phy@2 {
			reg = <2>;

			interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>;
			reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			reset-deassert-us = <1000>;

			clocks = <&clock_ksz9031>;
		};
	};
};

&gpio1 {
	gpio-line-names =
		"", "SD1_CD", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "PHY3_RESET", "", "", "PHY3_INT", "", "", "";
};

&gpio2 {
	gpio-line-names =
		"", "", "", "", "", "", "", "",
		"REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "BOARD_ID3",
			"BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
		"", "", "", "", "", "", "", "",
		"", "", "ECSPI2_SS0", "", "", "", "", "";
};

&gpio3 {
	gpio-line-names =
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "USB_OTG_OC", "USB_OTG_PWR", "",
		"", "", "", "", "", "", "", "";
};

&gpio4 {
	gpio-line-names =
		"", "", "", "", "", "", "", "",
		"", "", "", "", "CAN1_SR", "CAN2_SR", "", "",
		"", "", "", "", "", "", "", "",
		"ECSPI3_SS0", "CANFD_INT", "USB_ETH_RESET", "", "", "", "", "";
};

&gpio5 {
	gpio-line-names =
		"", "", "", "", "", "SW_RESET", "", "",
		"PHY12_INT", "PHY12_RESET", "PHY12_EN", "PHY0_RESET",
			"PHY0_INT", "", "", "",
		"", "", "DISP1_EN", "DISP1_LR", "DISP1_TS_IRQ", "LVDS1_PD",
			"", "",
		"", "LVDS1_INT", "", "", "DISP0_LR", "DISP0_TS_IRQ",
			"DISP0_EN", "CAM_GPIO0";
};

&gpio6 {
	gpio-line-names =
		"LVDS0_INT", "LVDS0_PD", "CAM_INT", "CAM_GPIO1", "CAM_PD",
			"CAM_LOCK", "", "POWER_TG",
		"POWER_VSEL", "", "WLAN_REG_ON", "USB_ETH_CHG", "", "",
			"USB_ETH_CHG_ID0", "USB_ETH_CHG_ID1",
		"USB_ETH_CHG_ID2", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	/* additional i2c devices are added automatically by the boot loader */
};

&i2c3 {
	adc@49 {
		compatible = "ti,ads1015";
		reg = <0x49>;
		#address-cells = <1>;
		#size-cells = <0>;

		/* VIN */
		channel@4 {
			reg = <4>;
			ti,gain = <1>;
			ti,datarate = <3>;
		};

		/* VBUS */
		channel@5 {
			reg = <5>;
			ti,gain = <1>;
			ti,datarate = <3>;
		};

		/* ICHG */
		channel@6 {
			reg = <6>;
			ti,gain = <1>;
			ti,datarate = <3>;
		};

		channel@7 {
			reg = <7>;
			ti,gain = <1>;
			ti,datarate = <3>;
		};
	};
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbotg {
	vbus-supply = <&reg_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	phy_type = "utmi";
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usbphynop1 {
	status = "disabled";
};

&usbphynop2 {
	status = "disabled";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	disable-wp;
	cap-sd-highspeed;
	no-mmc;
	no-sdio;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	no-1-8-v;
	non-removable;
	mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	brcmf: bcrmf@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
	};
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	no-sd;
	no-sdio;
	status = "okay";
};

&iomuxc {
	pinctrl_can1: can1grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX		0x1b000
			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX		0x3008
			/* CAN1_SR */
			MX6QDL_PAD_KEY_COL3__GPIO4_IO12			0x13008
		>;
	};

	pinctrl_can2: can2grp {
		fsl,pins = <
			/* CAN2_nINT */
			MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25		0x1b0b1
			/* CAN2_SR */
			MX6QDL_PAD_KEY_ROW3__GPIO4_IO13			0x13070
		>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_OE__ECSPI2_MISO			0x100b1
			MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK			0x100b1
			MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI			0x100b1
			MX6QDL_PAD_EIM_RW__GPIO2_IO26			0x000b1
		>;
	};

	pinctrl_ecspi3: ecspi3grp {
		fsl,pins = <
			MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK		0x100b1
			MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI		0x100b1
			MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO		0x100b1
			/* CS */
			MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24		0x000b1
		>;
	};

	pinctrl_enet: enetgrp {
		fsl,pins = <
			MX6QDL_PAD_RGMII_RXC__RGMII_RXC			0x1b030
			MX6QDL_PAD_RGMII_RD0__RGMII_RD0			0x1b030
			MX6QDL_PAD_RGMII_RD1__RGMII_RD1			0x1b030
			MX6QDL_PAD_RGMII_RD2__RGMII_RD2			0x1b030
			MX6QDL_PAD_RGMII_RD3__RGMII_RD3			0x1b030
			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL		0x1b030
			MX6QDL_PAD_RGMII_TXC__RGMII_TXC			0x10030
			MX6QDL_PAD_RGMII_TD0__RGMII_TD0			0x10030
			MX6QDL_PAD_RGMII_TD1__RGMII_TD1			0x10030
			MX6QDL_PAD_RGMII_TD2__RGMII_TD2			0x10030
			MX6QDL_PAD_RGMII_TD3__RGMII_TD3			0x10030
			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL		0x10030

			MX6QDL_PAD_ENET_MDIO__ENET_MDIO			0x10030
			MX6QDL_PAD_ENET_MDC__ENET_MDC			0x10030

			/* Configure clock provider for RGMII ref clock */
			MX6QDL_PAD_GPIO_16__ENET_REF_CLK		0x4001b0b0
			/* Configure clock consumer for RGMII ref clock */
			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK		0x10030

			/* SJA1105Q switch reset */
			MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05		0x10030

			/* phy3/rgmii_phy reset */
			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25		0x10030
			/* phy3/rgmii_phy int */
			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28		0x40010000
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA			0x4001f8b1
			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL			0x4001f8b1
		>;
	};

	pinctrl_mdio: mdiogrp {
		fsl,pins = <
			/* phy0/usbeth_phy reset */
			MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11		0x10030
			/* phy0/usbeth_phy int */
			MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12		0x100b1

			/* phy12/tja1102_phy0 reset */
			MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09		0x10030
			/* phy12/tja1102_phy0 int */
			MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08		0x100b1
			/* phy12/tja1102_phy0 enable. Set 100K pull-up */
			MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10		0x1f030
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL0__UART4_TX_DATA		0x1b0b1
			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA		0x1b0b1
		>;
	};

	pinctrl_usbotg: usbotggrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D21__USB_OTG_OC			0x1b0b0
			MX6QDL_PAD_EIM_D22__GPIO3_IO22			0x1b0b0
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6QDL_PAD_SD1_CMD__SD1_CMD			0x170f9
			MX6QDL_PAD_SD1_CLK__SD1_CLK			0x100f9
			MX6QDL_PAD_SD1_DAT0__SD1_DATA0			0x170f9
			MX6QDL_PAD_SD1_DAT1__SD1_DATA1			0x170f9
			MX6QDL_PAD_SD1_DAT2__SD1_DATA2			0x170f9
			MX6QDL_PAD_SD1_DAT3__SD1_DATA3			0x170f9
			MX6QDL_PAD_GPIO_1__GPIO1_IO01			0x1b0b0
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6QDL_PAD_SD2_CMD__SD2_CMD			0x170b9
			MX6QDL_PAD_SD2_CLK__SD2_CLK			0x100b9
			MX6QDL_PAD_SD2_DAT0__SD2_DATA0			0x170b9
			MX6QDL_PAD_SD2_DAT1__SD2_DATA1			0x170b9
			MX6QDL_PAD_SD2_DAT2__SD2_DATA2			0x170b9
			MX6QDL_PAD_SD2_DAT3__SD2_DATA3			0x170b9
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD			0x17099
			MX6QDL_PAD_SD3_CLK__SD3_CLK			0x10099
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0			0x17099
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1			0x17099
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2			0x17099
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3			0x17099
			MX6QDL_PAD_SD3_DAT4__SD3_DATA4			0x17099
			MX6QDL_PAD_SD3_DAT5__SD3_DATA5			0x17099
			MX6QDL_PAD_SD3_DAT6__SD3_DATA6			0x17099
			MX6QDL_PAD_SD3_DAT7__SD3_DATA7			0x17099
			MX6QDL_PAD_SD3_RST__SD3_RESET			0x1b0b1
		>;
	};

	pinctrl_wifi_npd: wifinpd {
		fsl,pins = <
			/* WL_REG_ON */
			MX6QDL_PAD_NANDF_RB0__GPIO6_IO10		0x13069
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2016 Freescale Semiconductor, Inc.

/dts-v1/;

#include "imx6qp.dtsi"
#include "imx6qdl-sabreauto.dtsi"

/ {
	model = "Freescale i.MX6 Quad Plus SABRE Automotive Board";
	compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
};

&i2c2 {
	max7322: gpio@68 {
		compatible = "maxim,max7322";
		reg = <0x68>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&iomuxc {
	imx6qdl-sabreauto {
		pinctrl_enet: enetgrp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
				MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b018
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b018
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b018
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b018
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b018
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b018
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b018
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b018
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b018
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b018
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b018
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b018
				MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
			>;
		};
	};
};

&pcie {
	reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&sata {
	status = "okay";
};

&vgen3_reg {
	regulator-always-on;
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2016 Freescale Semiconductor, Inc.

/dts-v1/;

#include "imx6qp.dtsi"
#include "imx6qdl-sabresd.dtsi"

/ {
	model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
	compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
};

&reg_arm {
	vin-supply = <&sw2_reg>;
};

&iomuxc {
	imx6qdl-sabresd {
		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10071
				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10071
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
			>;
		};
	};
};

&vgen3_reg {
	regulator-always-on;
};

&pcie {
	status = "okay";
};

&sata {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2013 Sascha Hauer, Pengutronix
 */

#include "imx6q.dtsi"
#include "imx6qp.dtsi"
#include "imx6qdl-tqma6b.dtsi"
#include "imx6qdl-tqma6.dtsi"

/ {
	memory@10000000 {
		device_type = "memory";
		reg = <0x10000000 0x40000000>;
	};
};


code:
/*
 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "imx6qp-tx6qp-8037.dts"
#include "imx6qdl-tx6-mb7.dtsi"

/ {
	model = "Ka-Ro electronics TX6Q-8037 Module on MB7 baseboard";
};


code:
/*
 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "imx6qp.dtsi"
#include "imx6qdl-tx6.dtsi"
#include "imx6qdl-tx6-lcd.dtsi"

/ {
	model = "Ka-Ro electronics TX6QP-8037 Module";
	compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp";
};

&ds1339 {
	status = "disabled";
};

&gpmi {
	status = "disabled";
};

&ipu2 {
	status = "disabled";
};

&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	bus-width = <4>;
	non-removable;
	no-1-8-v;
	fsl,wp-controller;
	status = "okay";
};

&iomuxc {
	pinctrl_usdhc4: usdhc4grp {
		fsl,pins = <
			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x070b1
			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x070b1
			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x070b1
			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x070b1
			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x070b1
			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x070b1
			MX6QDL_PAD_NANDF_ALE__SD4_RESET		0x0b0b1
		>;
	};
};


code:
/*
 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "imx6qp-tx6qp-8137.dts"
#include "imx6qdl-tx6-mb7.dtsi"

/ {
	model = "Ka-Ro electronics TX6Q-8137 Module on MB7 baseboard";
	compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp";
};

&ipu2 {
	status = "disabled";
};

&sata {
	status = "okay";
};


code:
/*
 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "imx6qp.dtsi"
#include "imx6qdl-tx6.dtsi"
#include "imx6qdl-tx6-lvds.dtsi"

/ {
	model = "Ka-Ro electronics TX6QP-8137 Module";
	compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp";
};

&ds1339 {
	status = "disabled";
};

&gpmi {
	status = "disabled";
};

&ipu2 {
	status = "disabled";
};

&sata {
	status = "okay";
};

&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	bus-width = <4>;
	non-removable;
	no-1-8-v;
	fsl,wp-controller;
	status = "okay";
};

&iomuxc {
	pinctrl_usdhc4: usdhc4grp {
		fsl,pins = <
			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x070b1
			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x070b1
			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x070b1
			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x070b1
			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x070b1
			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x070b1
			MX6QDL_PAD_NANDF_ALE__SD4_RESET		0x0b0b1
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright (c) 2014 Protonic Holland
 */

/dts-v1/;
#include "imx6qp.dtsi"
#include "imx6qdl-vicut1.dtsi"
#include "imx6qdl-vicut1-12inch.dtsi"

/ {
	model = "Kverneland UT1P Board";
	compatible = "kvg,vicutp", "fsl,imx6qp";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 */
/dts-v1/;
#include "imx6qp.dtsi"
#include "imx6qdl-wandboard-revd1.dtsi"

/ {
	model = "Wandboard i.MX6 QuadPlus Board revD1";
	compatible = "wand,imx6qp-wandboard", "fsl,imx6qp";

	memory@10000000 {
		device_type = "memory";
		reg = <0x10000000 0x80000000>;
	};
};

&sata {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2021 Y Soft Corporation, a.s.

/dts-v1/;

#include "imx6qp.dtsi"
#include "imx6dl-yapp4-common.dtsi"

/ {
	model = "Y Soft IOTA Crux+ i.MX6QuadPlus board";
	compatible = "ysoft,imx6qp-yapp4-crux-plus", "fsl,imx6qp";

	memory@10000000 {
		device_type = "memory";
		reg = <0x10000000 0xf0000000>;
	};
};

&gpio_oled {
	status = "okay";
};

&leds {
	status = "okay";
};

&oled_1305 {
	status = "okay";
};

&oled_1309 {
	status = "okay";
};

&reg_pu {
	regulator-always-on;
};

&reg_usb_h1_vbus {
	status = "okay";
};

&touchkeys {
	status = "okay";
};

&uart2 {
	status = "disabled";
};

&usbh1 {
	status = "okay";
};

&usbphy2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2016-2017 Zodiac Inflight Innovations
 */

/dts-v1/;

#include "imx6qp.dtsi"
#include "imx6qdl-zii-rdu2.dtsi"

/ {
	model = "ZII RDU2+ Board";
	compatible = "zii,imx6qp-zii-rdu2", "fsl,imx6qp";

	/* Will be filled by the bootloader */
	memory@10000000 {
		device_type = "memory";
		reg = <0x10000000 0>;
	};
};

&gpu_3d {
	assigned-clocks = <&clks IMX6QDL_CLK_GPU3D_SHADER_SEL>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD1_594M>;
};