code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Display Port Controller

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Jitao shi <jitao.shi@mediatek.com>

description: |
  MediaTek DP and eDP are different hardwares and there are some features
  which are not supported for eDP. For example, audio is not supported for
  eDP. Therefore, we need to use two different compatibles to describe them.
  In addition, We just need to enable the power domain of DP, so the clock
  of DP is generated by itself and we are not using other PLL to generate
  clocks.

properties:
  compatible:
    enum:
      - mediatek,mt8195-dp-tx
      - mediatek,mt8195-edp-tx

  reg:
    maxItems: 1

  nvmem-cells:
    maxItems: 1
    description: efuse data for display port calibration

  nvmem-cell-names:
    const: dp_calibration_data

  power-domains:
    maxItems: 1

  interrupts:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Input endpoint of the controller, usually dp_intf

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: Output endpoint of the controller
        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false
            properties:
              data-lanes:
                description: |
                  number of lanes supported by the hardware.
                  The possible values:
                  0       - For 1 lane enabled in IP.
                  0 1     - For 2 lanes enabled in IP.
                  0 1 2 3 - For 4 lanes enabled in IP.
                minItems: 1
                maxItems: 4
            required:
              - data-lanes

    required:
      - port@0
      - port@1

  max-linkrate-mhz:
    enum: [ 1620, 2700, 5400, 8100 ]
    description: maximum link rate supported by the hardware.

required:
  - compatible
  - reg
  - interrupts
  - ports
  - max-linkrate-mhz

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/mt8195-power.h>
    dptx@1c600000 {
        compatible = "mediatek,mt8195-dp-tx";
        reg = <0x1c600000 0x8000>;
        power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
        interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
        max-linkrate-mhz = <8100>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                dptx_in: endpoint {
                    remote-endpoint = <&dp_intf0_out>;
                };
            };
            port@1 {
                reg = <1>;
                dptx_out: endpoint {
                    data-lanes = <0 1 2 3>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek DPI and DP_INTF Controller

maintainers:
  - CK Hu <ck.hu@mediatek.com>
  - Jitao shi <jitao.shi@mediatek.com>

description: |
  The MediaTek DPI and DP_INTF function blocks are a sink of the display
  subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
  parallel output bus.

properties:
  compatible:
    enum:
      - mediatek,mt2701-dpi
      - mediatek,mt7623-dpi
      - mediatek,mt8173-dpi
      - mediatek,mt8183-dpi
      - mediatek,mt8186-dpi
      - mediatek,mt8188-dp-intf
      - mediatek,mt8192-dpi
      - mediatek,mt8195-dp-intf

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Pixel Clock
      - description: Engine Clock
      - description: DPI PLL

  clock-names:
    items:
      - const: pixel
      - const: engine
      - const: pll

  pinctrl-0: true
  pinctrl-1: true

  pinctrl-names:
    items:
      - const: default
      - const: sleep

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      Output port node. This port should be connected to the input port of an
      attached HDMI, LVDS or DisplayPort encoder chip.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>

    dpi0: dpi@1401d000 {
        compatible = "mediatek,mt8173-dpi";
        reg = <0x1401d000 0x1000>;
        interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
        clocks = <&mmsys CLK_MM_DPI_PIXEL>,
             <&mmsys CLK_MM_DPI_ENGINE>,
             <&apmixedsys CLK_APMIXED_TVDPLL>;
        clock-names = "pixel", "engine", "pll";
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&dpi_pin_func>;
        pinctrl-1 = <&dpi_pin_idle>;

        port {
            dpi0_out: endpoint {
                remote-endpoint = <&hdmi0_in>;
            };
        };
    };

...

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: mediatek display DSC controller

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  The DSC standard is a specification of the algorithms used for
  compressing and decompressing image display streams, including
  the specification of the syntax and semantics of the compressed
  video bit stream. DSC is designed for real-time systems with
  real-time compression, transmission, decompression and Display.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt8195-disp-dsc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: DSC Wrapper Clock

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  mediatek,gce-client-reg:
    description:
      The register of client driver can be configured by gce with 4 arguments
      defined in this property, such as phandle of gce, subsys id,
      register offset and size.
      Each subsys id is mapping to a base address of display function blocks
      register which is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8195-clk.h>
    #include <dt-bindings/power/mt8195-power.h>
    #include <dt-bindings/gce/mt8195-gce.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        dsc0: disp_dsc_wrap@1c009000 {
            compatible = "mediatek,mt8195-disp-dsc";
            reg = <0 0x1c009000 0 0x1000>;
            interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
            power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
            clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
            mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek DSI Controller Device Tree Bindings

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>
  - Jitao Shi <jitao.shi@mediatek.com>
  - Xinlei Lee <xinlei.lee@mediatek.com>

description: |
  The MediaTek DSI function block is a sink of the display subsystem and can
  drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
  channel output.

allOf:
  - $ref: /schemas/display/dsi-controller.yaml#

properties:
  compatible:
    enum:
      - mediatek,mt2701-dsi
      - mediatek,mt7623-dsi
      - mediatek,mt8167-dsi
      - mediatek,mt8173-dsi
      - mediatek,mt8183-dsi
      - mediatek,mt8186-dsi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  clocks:
    items:
      - description: Engine Clock
      - description: Digital Clock
      - description: HS Clock

  clock-names:
    items:
      - const: engine
      - const: digital
      - const: hs

  resets:
    maxItems: 1

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: dphy

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      Output port node. This port should be connected to the input
      port of an attached DSI panel or DSI-to-eDP encoder chip.

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks
  - clock-names
  - phys
  - phy-names
  - port

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/mt8183-power.h>
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/reset/mt8183-resets.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        dsi0: dsi@14014000 {
            compatible = "mediatek,mt8183-dsi";
            reg = <0 0x14014000 0 0x1000>;
            interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
            clocks = <&mmsys CLK_MM_DSI0_MM>,
                <&mmsys CLK_MM_DSI0_IF>,
                <&mipi_tx0>;
            clock-names = "engine", "digital", "hs";
            resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
            phys = <&mipi_tx0>;
            phy-names = "dphy";
            port {
                dsi0_out: endpoint {
                    remote-endpoint = <&panel_in>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,gamma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display gamma correction

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display gamma correction, namely GAMMA, provides a nonlinear
  operation used to adjust luminance in display system.
  GAMMA device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt8173-disp-gamma
      - items:
          - const: mediatek,mt8183-disp-gamma
      - items:
          - enum:
              - mediatek,mt8186-disp-gamma
              - mediatek,mt8192-disp-gamma
              - mediatek,mt8195-disp-gamma
          - const: mediatek,mt8183-disp-gamma

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: GAMMA Clock

  mediatek,gce-client-reg:
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property, such as phandle of gce, subsys id,
      register offset and size. Each GCE subsys id is mapping to a client
      defined in the header include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>
    #include <dt-bindings/gce/mt8173-gce.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        gamma@14016000 {
            compatible = "mediatek,mt8173-disp-gamma";
            reg = <0 0x14016000 0 0x1000>;
            interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
            clocks = <&mmsys CLK_MM_DISP_GAMMA>;
            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek HDMI DDC Device Tree Bindings

maintainers:
  - CK Hu <ck.hu@mediatek.com>
  - Jitao shi <jitao.shi@mediatek.com>

description: |
  The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.

properties:
  compatible:
    enum:
      - mediatek,mt7623-hdmi-ddc
      - mediatek,mt8167-hdmi-ddc
      - mediatek,mt8173-hdmi-ddc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: ddc-i2c

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    hdmi_ddc0: i2c@11012000 {
        compatible = "mediatek,mt8173-hdmi-ddc";
        reg = <0x11012000 0x1c>;
        interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
        clocks = <&pericfg CLK_PERI_I2C5>;
        clock-names = "ddc-i2c";
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek HDMI Encoder Device Tree Bindings

maintainers:
  - CK Hu <ck.hu@mediatek.com>
  - Jitao shi <jitao.shi@mediatek.com>

description: |
  The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
  its parallel input.

properties:
  compatible:
    enum:
      - mediatek,mt2701-hdmi
      - mediatek,mt7623-hdmi
      - mediatek,mt8167-hdmi
      - mediatek,mt8173-hdmi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Pixel Clock
      - description: HDMI PLL
      - description: Bit Clock
      - description: S/PDIF Clock

  clock-names:
    items:
      - const: pixel
      - const: pll
      - const: bclk
      - const: spdif

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: hdmi

  mediatek,syscon-hdmi:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    items:
      - items:
          - description: phandle to system configuration registers
          - description: register offset in the system configuration registers
    description: |
      phandle link and register offset to the system configuration registers.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Input port node. This port should be connected to a DPI output port.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Output port node. This port should be connected to the input port of a connector
          node that contains a ddc-i2c-bus property, or to the  input port of an attached
          bridge chip, such as a SlimPort transmitter.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - phys
  - phy-names
  - mediatek,syscon-hdmi
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    hdmi0: hdmi@14025000 {
        compatible = "mediatek,mt8173-hdmi";
        reg = <0x14025000 0x400>;
        interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
        clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
             <&mmsys CLK_MM_HDMI_PLLCK>,
             <&mmsys CLK_MM_HDMI_AUDIO>,
             <&mmsys CLK_MM_HDMI_SPDIF>;
        clock-names = "pixel", "pll", "bclk", "spdif";
        pinctrl-names = "default";
        pinctrl-0 = <&hdmi_pin>;
        phys = <&hdmi_phy>;
        phy-names = "hdmi";
        mediatek,syscon-hdmi = <&mmsys 0x900>;

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;

            hdmi0_in: endpoint {
              remote-endpoint = <&dpi0_out>;
            };
          };

          port@1 {
            reg = <1>;

            hdmi0_out: endpoint {
              remote-endpoint = <&hdmi_con_in>;
            };
          };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek MDP RDMA

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description:
  The MediaTek MDP RDMA stands for Read Direct Memory Access.
  It provides real time data to the back-end panel driver, such as DSI,
  DPI and DP_INTF.
  It contains one line buffer to store the sufficient pixel data.
  RDMA device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.

properties:
  compatible:
    const: mediatek,mt8195-vdo1-rdma

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  clocks:
    items:
      - description: RDMA Clock

  iommus:
    maxItems: 1

  mediatek,gce-client-reg:
    description:
      The register of display function block to be set by gce. There are 4 arguments,
      such as gce node, subsys id, offset and register size. The subsys id that is
      mapping to the register of display function blocks is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h of each chips.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      items:
        - description: phandle of GCE
        - description: GCE subsys id
        - description: register offset
        - description: register size
    maxItems: 1

required:
  - compatible
  - reg
  - power-domains
  - clocks
  - iommus
  - mediatek,gce-client-reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8195-clk.h>
    #include <dt-bindings/power/mt8195-power.h>
    #include <dt-bindings/gce/mt8195-gce.h>
    #include <dt-bindings/memory/mt8195-memory-port.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        rdma@1c104000 {
            compatible = "mediatek,mt8195-vdo1-rdma";
            reg = <0 0x1c104000 0 0x1000>;
            interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
            clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
            power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
            iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
            mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display merge

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
  inputs into one side-by-side output.
  MERGE device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt8173-disp-merge
      - items:
          - const: mediatek,mt8195-disp-merge

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    oneOf:
      - items:
          - const: merge
      - items:
          - const: merge
          - const: merge_async

  mediatek,merge-fifo-en:
    description:
      The setting of merge fifo is mainly provided for the display latency
      buffer to ensure that the back-end panel display data will not be
      underrun, a little more data is needed in the fifo.
      According to the merge fifo settings, when the water level is detected
      to be insufficient, it will trigger RDMA sending ultra and preulra
      command to SMI to speed up the data rate.
    type: boolean

  mediatek,merge-mute:
    description: Support mute function. Mute the content of merge output.
    type: boolean

  mediatek,gce-client-reg:
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property, such as phandle of gce, subsys id,
      register offset and size. Each GCE subsys id is mapping to a client
      defined in the header include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

  resets:
    description: reset controller
      See Documentation/devicetree/bindings/reset/reset.txt for details.
    maxItems: 1

required:
  - compatible
  - reg
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        merge@14017000 {
            compatible = "mediatek,mt8173-disp-merge";
            reg = <0 0x14017000 0 0x1000>;
            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
            clocks = <&mmsys CLK_MM_DISP_MERGE>;
            clock-names = "merge";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display overdirve

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display overdrive, namely OD, increases the transition values
  of pixels between consecutive frames to make LCD rotate faster.
  OD device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt2712-disp-od
      - items:
          - const: mediatek,mt8173-disp-od

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: OD Clock

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        od@14023000 {
            compatible = "mediatek,mt8173-disp-od";
            reg = <0 0x14023000 0 0x1000>;
            clocks = <&mmsys CLK_MM_DISP_OD>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display overlay 2 layer

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
  for OVL.
  OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt8183-disp-ovl-2l
      - items:
          - const: mediatek,mt8192-disp-ovl-2l
      - items:
          - enum:
              - mediatek,mt8186-disp-ovl-2l
          - const: mediatek,mt8192-disp-ovl-2l

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: OVL-2L Clock

  iommus:
    description:
      This property should point to the respective IOMMU block with master port as argument,
      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.

  mediatek,gce-client-reg:
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property, such as phandle of gce, subsys id,
      register offset and size. Each GCE subsys id is mapping to a client
      defined in the header include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks
  - iommus

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/power/mt8183-power.h>
    #include <dt-bindings/gce/mt8183-gce.h>
    #include <dt-bindings/memory/mt8183-larb-port.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        ovl_2l0: ovl@14009000 {
            compatible = "mediatek,mt8183-disp-ovl-2l";
            reg = <0 0x14009000 0 0x1000>;
            interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
            clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
            iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display overlay

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display overlay, namely OVL, can do alpha blending from
  the memory.
  OVL device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt2701-disp-ovl
      - items:
          - const: mediatek,mt8173-disp-ovl
      - items:
          - const: mediatek,mt8183-disp-ovl
      - items:
          - const: mediatek,mt8192-disp-ovl
      - items:
          - enum:
              - mediatek,mt7623-disp-ovl
              - mediatek,mt2712-disp-ovl
          - const: mediatek,mt2701-disp-ovl
      - items:
          - enum:
              - mediatek,mt8195-disp-ovl
          - const: mediatek,mt8183-disp-ovl
      - items:
          - enum:
              - mediatek,mt8186-disp-ovl
          - const: mediatek,mt8192-disp-ovl

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: OVL Clock

  iommus:
    description:
      This property should point to the respective IOMMU block with master port as argument,
      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.

  mediatek,gce-client-reg:
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property, such as phandle of gce, subsys id,
      register offset and size. Each GCE subsys id is mapping to a client
      defined in the header include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks
  - iommus

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>
    #include <dt-bindings/gce/mt8173-gce.h>
    #include <dt-bindings/memory/mt8173-larb-port.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        ovl0: ovl@1400c000 {
            compatible = "mediatek,mt8173-disp-ovl";
            reg = <0 0x1400c000 0 0x1000>;
            interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
            clocks = <&mmsys CLK_MM_DISP_OVL0>;
            iommus = <&iommu M4U_PORT_DISP_OVL0>;
            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display postmask

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display postmask, namely POSTMASK, provides round corner pattern
  generation.
  POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt8192-disp-postmask
      - items:
          - enum:
              - mediatek,mt8186-disp-postmask
          - const: mediatek,mt8192-disp-postmask

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: POSTMASK Clock

  mediatek,gce-client-reg:
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property, such as phandle of gce, subsys id,
      register offset and size. Each GCE subsys id is mapping to a client
      defined in the header include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8192-clk.h>
    #include <dt-bindings/power/mt8192-power.h>
    #include <dt-bindings/gce/mt8192-gce.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        postmask0: postmask@1400d000 {
            compatible = "mediatek,mt8192-disp-postmask";
            reg = <0 0x1400d000 0 0x1000>;
            interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
            power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
            clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek Read Direct Memory Access

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek Read Direct Memory Access(RDMA) component used to read the
  data into DMA. It provides real time data to the back-end panel
  driver, such as DSI, DPI and DP_INTF.
  It contains one line buffer to store the sufficient pixel data.
  RDMA device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt2701-disp-rdma
      - items:
          - const: mediatek,mt8173-disp-rdma
      - items:
          - const: mediatek,mt8183-disp-rdma
      - items:
          - const: mediatek,mt8195-disp-rdma
      - items:
          - enum:
              - mediatek,mt7623-disp-rdma
              - mediatek,mt2712-disp-rdma
          - const: mediatek,mt2701-disp-rdma
      - items:
          - enum:
              - mediatek,mt8186-disp-rdma
              - mediatek,mt8192-disp-rdma
          - const: mediatek,mt8183-disp-rdma

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: RDMA Clock

  iommus:
    description:
      This property should point to the respective IOMMU block with master port as argument,
      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.

  mediatek,rdma-fifo-size:
    description:
      rdma fifo size may be different even in same SOC, add this property to the
      corresponding rdma.
      The value below is the Max value which defined in hardware data sheet
      mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
      mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
      mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [8192, 5120, 2048]

  mediatek,gce-client-reg:
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property, such as phandle of gce, subsys id,
      register offset and size. Each GCE subsys id is mapping to a client
      defined in the header include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks
  - iommus

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>
    #include <dt-bindings/gce/mt8173-gce.h>
    #include <dt-bindings/memory/mt8173-larb-port.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        rdma0: rdma@1400e000 {
            compatible = "mediatek,mt8173-disp-rdma";
            reg = <0 0x1400e000 0 0x1000>;
            interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
            clocks = <&mmsys CLK_MM_DISP_RDMA0>;
            iommus = <&iommu M4U_PORT_DISP_RDMA0>;
            mediatek,rdma-fifo-size = <8192>;
            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display split

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display split, namely SPLIT, is used to split stream to two
  encoders.
  SPLIT device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt8173-disp-split

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: SPLIT Clock

required:
  - compatible
  - reg
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        split0: split@14018000 {
            compatible = "mediatek,mt8173-disp-split";
            reg = <0 0x14018000 0 0x1000>;
            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
            clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display UFOe

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display UFOe stands for Unified Frame Optimization engine.
  UFOe can cut the data rate for DSI port which may lead to reduce power
  consumption.
  UFOe device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt8173-disp-ufoe

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: UFOe Clock

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        ufoe@1401a000 {
            compatible = "mediatek,mt8173-disp-ufoe";
            reg = <0 0x1401a000 0 0x1000>;
            interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
            clocks = <&mmsys CLK_MM_DISP_UFOE>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek Write Direct Memory Access

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek Write Direct Memory Access(WDMA) component used to write
  the data into DMA.
  WDMA device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt8173-disp-wdma

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: WDMA Clock

  iommus:
    description:
      This property should point to the respective IOMMU block with master port as argument,
      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.

  mediatek,gce-client-reg:
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property, such as phandle of gce, subsys id,
      register offset and size. Each GCE subsys id is mapping to a client
      defined in the header include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks
  - iommus

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>
    #include <dt-bindings/gce/mt8173-gce.h>
    #include <dt-bindings/memory/mt8173-larb-port.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        wdma0: wdma@14011000 {
            compatible = "mediatek,mt8173-disp-wdma";
            reg = <0 0x14011000 0 0x1000>;
            interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
            clocks = <&mmsys CLK_MM_DISP_WDMA0>;
            iommus = <&iommu M4U_PORT_DISP_WDMA0>;
            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
        };
    };


code:
MIPI DSI (Display Serial Interface) busses
==========================================

The MIPI Display Serial Interface specifies a serial bus and a protocol for
communication between a host and up to four peripherals. This document will
define the syntax used to represent a DSI bus in a device tree.

This document describes DSI bus-specific properties only or defines existing
standard properties in the context of the DSI bus.

Each DSI host provides a DSI bus. The DSI host controller's node contains a
set of properties that characterize the bus. Child nodes describe individual
peripherals on that bus.

The following assumes that only a single peripheral is connected to a DSI
host. Experience shows that this is true for the large majority of setups.

DSI host
========

In addition to the standard properties and those defined by the parent bus of
a DSI host, the following properties apply to a node representing a DSI host.

Required properties:
- #address-cells: The number of cells required to represent an address on the
  bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
  a maximum of 4 devices can be addressed on a single bus. Hence the value of
  this property should be 1.
- #size-cells: Should be 0. There are cases where it makes sense to use a
  different value here. See below.

Optional properties:
- clock-master: boolean. Should be enabled if the host is being used in
  conjunction with another DSI host to drive the same peripheral. Hardware
  supporting such a configuration generally requires the data on both the busses
  to be driven by the same clock. Only the DSI host instance controlling this
  clock should contain this property.

DSI peripheral
==============

Peripherals with DSI as control bus, or no control bus
------------------------------------------------------

Peripherals with the DSI bus as the primary control bus, or peripherals with
no control bus but use the DSI bus to transmit pixel data are represented
as child nodes of the DSI host's node. Properties described here apply to all
DSI peripherals, but individual bindings may want to define additional,
device-specific properties.

Required properties:
- reg: The virtual channel number of a DSI peripheral. Must be in the range
  from 0 to 3.

Some DSI peripherals respond to more than a single virtual channel. In that
case two alternative representations can be chosen:
- The reg property can take multiple entries, one for each virtual channel
  that the peripheral responds to.
- If the virtual channels that a peripheral responds to are consecutive, the
  #size-cells can be set to 1. The first cell of each entry in the reg
  property is the number of the first virtual channel and the second cell is
  the number of consecutive virtual channels.

Peripherals with a different control bus
----------------------------------------

There are peripherals that have I2C/SPI (or some other non-DSI bus) as the
primary control bus, but are also connected to a DSI bus (mostly for the data
path). Connections between such peripherals and a DSI host can be represented
using the graph bindings [1], [2].

Peripherals that support dual channel DSI
-----------------------------------------

Peripherals with higher bandwidth requirements can be connected to 2 DSI
busses. Each DSI bus/channel drives some portion of the pixel data (generally
left/right half of each line of the display, or even/odd lines of the display).
The graph bindings should be used to represent the multiple DSI busses that are
connected to this peripheral. Each DSI host's output endpoint can be linked to
an input endpoint of the DSI peripheral.

[1] Documentation/devicetree/bindings/graph.txt
[2] Documentation/devicetree/bindings/media/video-interfaces.txt

Examples
========
- (1), (2) and (3) are examples of a DSI host and peripheral on the DSI bus
  with different virtual channel configurations.
- (4) is an example of a peripheral on a I2C control bus connected to a
  DSI host using of-graph bindings.
- (5) is an example of 2 DSI hosts driving a dual-channel DSI peripheral,
  which uses I2C as its primary control bus.

1)
	dsi-host {
		...

		#address-cells = <1>;
		#size-cells = <0>;

		/* peripheral responds to virtual channel 0 */
		peripheral@0 {
			compatible = "...";
			reg = <0>;
		};

		...
	};

2)
	dsi-host {
		...

		#address-cells = <1>;
		#size-cells = <0>;

		/* peripheral responds to virtual channels 0 and 2 */
		peripheral@0 {
			compatible = "...";
			reg = <0, 2>;
		};

		...
	};

3)
	dsi-host {
		...

		#address-cells = <1>;
		#size-cells = <1>;

		/* peripheral responds to virtual channels 1, 2 and 3 */
		peripheral@1 {
			compatible = "...";
			reg = <1 3>;
		};

		...
	};

4)
	i2c-host {
		...

		dsi-bridge@35 {
			compatible = "...";
			reg = <0x35>;

			ports {
				...

				port {
					bridge_mipi_in: endpoint {
						remote-endpoint = <&host_mipi_out>;
					};
				};
			};
		};
	};

	dsi-host {
		...

		ports {
			...

			port {
				host_mipi_out: endpoint {
					remote-endpoint = <&bridge_mipi_in>;
				};
			};
		};
	};

5)
	i2c-host {
		dsi-bridge@35 {
			compatible = "...";
			reg = <0x35>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					dsi0_in: endpoint {
						remote-endpoint = <&dsi0_out>;
					};
				};

				port@1 {
					reg = <1>;
					dsi1_in: endpoint {
						remote-endpoint = <&dsi1_out>;
					};
				};
			};
		};
	};

	dsi0-host {
		...

		/*
		 * this DSI instance drives the clock for both the host
		 * controllers
		 */
		clock-master;

		ports {
			...

			port {
				dsi0_out: endpoint {
					remote-endpoint = <&dsi0_in>;
				};
			};
		};
	};

	dsi1-host {
		...

		ports {
			...

			port {
				dsi1_out: endpoint {
					remote-endpoint = <&dsi1_in>;
				};
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MSM Display Port Controller

maintainers:
  - Kuogee Hsieh <quic_khsieh@quicinc.com>

description: |
  Device tree bindings for DisplayPort host controller for MSM targets
  that are compatible with VESA DisplayPort interface specification.

properties:
  compatible:
    enum:
      - qcom,sc7180-dp
      - qcom,sc7280-dp
      - qcom,sc7280-edp
      - qcom,sc8180x-dp
      - qcom,sc8180x-edp
      - qcom,sm8350-dp

  reg:
    minItems: 4
    items:
      - description: ahb register block
      - description: aux register block
      - description: link register block
      - description: p0 register block
      - description: p1 register block

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: AHB clock to enable register access
      - description: Display Port AUX clock
      - description: Display Port Link clock
      - description: Link interface clock between DP and PHY
      - description: Display Port Pixel clock

  clock-names:
    items:
      - const: core_iface
      - const: core_aux
      - const: ctrl_link
      - const: ctrl_link_iface
      - const: stream_pixel

  assigned-clocks:
    items:
      - description: link clock source
      - description: pixel clock source

  assigned-clock-parents:
    items:
      - description: phy 0 parent
      - description: phy 1 parent

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: dp

  operating-points-v2:
    maxItems: 1

  opp-table: true

  power-domains:
    maxItems: 1

  aux-bus:
    $ref: /schemas/display/dp-aux-bus.yaml#

  data-lanes:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 4
    items:
      maximum: 3

  "#sound-dai-cells":
    const: 0

  vdda-0p9-supply:
    deprecated: true
  vdda-1p2-supply:
    deprecated: true

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Input endpoint of the controller

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Output endpoint of the controller

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - phys
  - phy-names
  - power-domains
  - ports

allOf:
  # AUX BUS does not exist on DP controllers
  # Audio output also is present only on DP output
  # p1 regions is present on DP, but not on eDP
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc7280-edp
              - qcom,sc8180x-edp
    then:
      properties:
        "#sound-dai-cells": false
        reg:
          maxItems: 4
    else:
      properties:
        aux-bus: false
        reg:
          minItems: 5
      required:
        - "#sound-dai-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    displayport-controller@ae90000 {
        compatible = "qcom,sc7180-dp";
        reg = <0xae90000 0x200>,
              <0xae90200 0x200>,
              <0xae90400 0xc00>,
              <0xae91000 0x400>,
              <0xae91400 0x400>;
        interrupt-parent = <&mdss>;
        interrupts = <12>;
        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
        clock-names = "core_iface", "core_aux",
                      "ctrl_link",
                      "ctrl_link_iface", "stream_pixel";

        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;

        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;

        phys = <&dp_phy>;
        phy-names = "dp";

        #sound-dai-cells = <0>;

        power-domains = <&rpmhpd SC7180_CX>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                endpoint {
                    remote-endpoint = <&dpu_intf0_out>;
                };
            };

            port@1 {
                reg = <1>;
                endpoint {
                    remote-endpoint = <&typec>;
                };
            };
        };
    };
...


code:
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dpu-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DPU common properties

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  - Rob Clark <robdclark@gmail.com>

description: |
  Common properties for QCom DPU display controller.

properties:
  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  operating-points-v2: true
  opp-table:
    type: object

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description: |
      Contains the list of output ports from DPU device. These ports
      connect to interfaces that are external to the DPU hardware,
      such as DSI, DP etc.

    patternProperties:
      "^port@[0-9a-f]+$":
        $ref: /schemas/graph.yaml#/properties/port

    # at least one port is required
    required:
      - port@0

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - interrupts
  - power-domains
  - operating-points-v2
  - ports

additionalProperties: true


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DSI controller

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

allOf:
  - $ref: "../dsi-controller.yaml#"

properties:
  compatible:
    enum:
      - qcom,mdss-dsi-ctrl
      - qcom,dsi-ctrl-6g-qcm2290

  reg:
    maxItems: 1

  reg-names:
    const: dsi_ctrl

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Display byte clock
      - description: Display byte interface clock
      - description: Display pixel clock
      - description: Display escape clock
      - description: Display AHB clock
      - description: Display AXI clock

  clock-names:
    items:
      - const: byte
      - const: byte_intf
      - const: pixel
      - const: core
      - const: iface
      - const: bus

  phys:
    maxItems: 1

  phy-names:
    deprecated: true
    const: dsi

  "#address-cells": true

  "#size-cells": true

  syscon-sfpb:
    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
    $ref: "/schemas/types.yaml#/definitions/phandle"

  qcom,dual-dsi-mode:
    type: boolean
    description: |
      Indicates if the DSI controller is driving a panel which needs
      2 DSI links.

  assigned-clocks:
    maxItems: 2
    description: |
      Parents of "byte" and "pixel" for the given platform.

  assigned-clock-parents:
    maxItems: 2
    description: |
      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.

  power-domains:
    maxItems: 1

  operating-points-v2: true

  opp-table:
    type: object

  ports:
    $ref: "/schemas/graph.yaml#/properties/ports"
    description: |
      Contains DSI controller input and output ports as children, each
      containing one endpoint subnode.

    properties:
      port@0:
        $ref: "/schemas/graph.yaml#/$defs/port-base"
        unevaluatedProperties: false
        description: |
          Input endpoints of the controller.
        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false
            properties:
              data-lanes:
                maxItems: 4
                minItems: 4
                items:
                  enum: [ 0, 1, 2, 3 ]

      port@1:
        $ref: "/schemas/graph.yaml#/$defs/port-base"
        unevaluatedProperties: false
        description: |
          Output endpoints of the controller.
        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false
            properties:
              data-lanes:
                maxItems: 4
                minItems: 4
                items:
                  enum: [ 0, 1, 2, 3 ]

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names
  - phys
  - assigned-clocks
  - assigned-clock-parents
  - power-domains
  - operating-points-v2
  - ports

additionalProperties: false

examples:
  - |
     #include <dt-bindings/interrupt-controller/arm-gic.h>
     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
     #include <dt-bindings/power/qcom-rpmpd.h>

     dsi@ae94000 {
           compatible = "qcom,mdss-dsi-ctrl";
           reg = <0x0ae94000 0x400>;
           reg-names = "dsi_ctrl";

           #address-cells = <1>;
           #size-cells = <0>;

           interrupt-parent = <&mdss>;
           interrupts = <4>;

           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
           clock-names = "byte",
                         "byte_intf",
                         "pixel",
                         "core",
                         "iface",
                         "bus";

           phys = <&dsi0_phy>;
           phy-names = "dsi";

           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;

           power-domains = <&rpmhpd SC7180_CX>;
           operating-points-v2 = <&dsi_opp_table>;

           ports {
                  #address-cells = <1>;
                  #size-cells = <0>;

                  port@0 {
                          reg = <0>;
                          dsi0_in: endpoint {
                                   remote-endpoint = <&dpu_intf1_out>;
                          };
                  };

                  port@1 {
                          reg = <1>;
                          dsi0_out: endpoint {
                                   remote-endpoint = <&sn65dsi86_in>;
                                   data-lanes = <0 1 2 3>;
                          };
                  };
           };
     };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DSI 10nm PHY

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

allOf:
  - $ref: dsi-phy-common.yaml#

properties:
  compatible:
    enum:
      - qcom,dsi-phy-10nm
      - qcom,dsi-phy-10nm-8998

  reg:
    items:
      - description: dsi phy register set
      - description: dsi phy lane register set
      - description: dsi pll register set

  reg-names:
    items:
      - const: dsi_phy
      - const: dsi_phy_lane
      - const: dsi_pll

  vdds-supply:
    description: |
      Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
      connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target

  qcom,phy-rescode-offset-top:
    $ref: /schemas/types.yaml#/definitions/int8-array
    maxItems: 5
    description:
      Integer array of offset for pull-up legs rescode for all five lanes.
      To offset the drive strength from the calibrated value in an increasing
      manner, -32 is the weakest and +31 is the strongest.
    items:
      minimum: -32
      maximum: 31

  qcom,phy-rescode-offset-bot:
    $ref: /schemas/types.yaml#/definitions/int8-array
    maxItems: 5
    description:
      Integer array of offset for pull-down legs rescode for all five lanes.
      To offset the drive strength from the calibrated value in a decreasing
      manner, -32 is the weakest and +31 is the strongest.
    items:
      minimum: -32
      maximum: 31

  qcom,phy-drive-ldo-level:
    $ref: "/schemas/types.yaml#/definitions/uint32"
    description:
      The PHY LDO has an amplitude tuning feature to adjust the LDO output
      for the HSTX drive. Use supported levels (mV) to offset the drive level
      from the default value.
    enum: [ 375, 400, 425, 450, 475, 500 ]

required:
  - compatible
  - reg
  - reg-names
  - vdds-supply

unevaluatedProperties: false

examples:
  - |
     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
     #include <dt-bindings/clock/qcom,rpmh.h>

     dsi-phy@ae94400 {
         compatible = "qcom,dsi-phy-10nm";
         reg = <0x0ae94400 0x200>,
               <0x0ae94600 0x280>,
               <0x0ae94a00 0x1e0>;
         reg-names = "dsi_phy",
                     "dsi_phy_lane",
                     "dsi_pll";

         #clock-cells = <1>;
         #phy-cells = <0>;

         vdds-supply = <&vdda_mipi_dsi0_pll>;
         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                  <&rpmhcc RPMH_CXO_CLK>;
         clock-names = "iface", "ref";

         qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
         qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
         qcom,phy-drive-ldo-level = <400>;
     };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DSI 14nm PHY

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

allOf:
  - $ref: dsi-phy-common.yaml#

properties:
  compatible:
    enum:
      - qcom,dsi-phy-14nm
      - qcom,dsi-phy-14nm-2290
      - qcom,dsi-phy-14nm-660
      - qcom,dsi-phy-14nm-8953

  reg:
    items:
      - description: dsi phy register set
      - description: dsi phy lane register set
      - description: dsi pll register set

  reg-names:
    items:
      - const: dsi_phy
      - const: dsi_phy_lane
      - const: dsi_pll

  vcca-supply:
    description: Phandle to vcca regulator device node.

required:
  - compatible
  - reg
  - reg-names
  - vcca-supply

unevaluatedProperties: false

examples:
  - |
     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
     #include <dt-bindings/clock/qcom,rpmh.h>

     dsi-phy@ae94400 {
         compatible = "qcom,dsi-phy-14nm";
         reg = <0x0ae94400 0x200>,
               <0x0ae94600 0x280>,
               <0x0ae94a00 0x1e0>;
         reg-names = "dsi_phy",
                     "dsi_phy_lane",
                     "dsi_pll";

         #clock-cells = <1>;
         #phy-cells = <0>;

         vcca-supply = <&vcca_reg>;
         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                  <&rpmhcc RPMH_CXO_CLK>;
         clock-names = "iface", "ref";
     };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DSI 20nm PHY

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

allOf:
  - $ref: dsi-phy-common.yaml#

properties:
  compatible:
    const: qcom,dsi-phy-20nm

  reg:
    items:
      - description: dsi pll register set
      - description: dsi phy register set
      - description: dsi phy regulator register set

  reg-names:
    items:
      - const: dsi_pll
      - const: dsi_phy
      - const: dsi_phy_regulator

  vcca-supply:
    description: Phandle to vcca regulator device node.

  vddio-supply:
    description: Phandle to vdd-io regulator device node.

required:
  - compatible
  - reg
  - reg-names
  - vddio-supply
  - vcca-supply

unevaluatedProperties: false

examples:
  - |
     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
     #include <dt-bindings/clock/qcom,rpmh.h>

     dsi-phy@fd922a00 {
         compatible = "qcom,dsi-phy-20nm";
         reg = <0xfd922a00 0xd4>,
               <0xfd922b00 0x2b0>,
               <0xfd922d80 0x7b>;
         reg-names = "dsi_pll",
                     "dsi_phy",
                     "dsi_phy_regulator";

         #clock-cells = <1>;
         #phy-cells = <0>;

         vcca-supply = <&vcca_reg>;
         vddio-supply = <&vddio_reg>;

         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                  <&rpmhcc RPMH_CXO_CLK>;
         clock-names = "iface", "ref";
     };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DSI 28nm PHY

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

allOf:
  - $ref: dsi-phy-common.yaml#

properties:
  compatible:
    enum:
      - qcom,dsi-phy-28nm-hpm
      - qcom,dsi-phy-28nm-lp
      - qcom,dsi-phy-28nm-8960

  reg:
    items:
      - description: dsi pll register set
      - description: dsi phy register set
      - description: dsi phy regulator register set

  reg-names:
    items:
      - const: dsi_pll
      - const: dsi_phy
      - const: dsi_phy_regulator

  vddio-supply:
    description: Phandle to vdd-io regulator device node.

required:
  - compatible
  - reg
  - reg-names
  - vddio-supply

unevaluatedProperties: false

examples:
  - |
     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
     #include <dt-bindings/clock/qcom,rpmh.h>

     dsi-phy@fd922a00 {
         compatible = "qcom,dsi-phy-28nm-lp";
         reg = <0xfd922a00 0xd4>,
               <0xfd922b00 0x2b0>,
               <0xfd922d80 0x7b>;
         reg-names = "dsi_pll",
                     "dsi_phy",
                     "dsi_phy_regulator";

         #clock-cells = <1>;
         #phy-cells = <0>;

         vddio-supply = <&vddio_reg>;

         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                  <&rpmhcc RPMH_CXO_CLK>;
         clock-names = "iface", "ref";
     };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DSI 7nm PHY

maintainers:
  - Jonathan Marek <jonathan@marek.ca>

allOf:
  - $ref: dsi-phy-common.yaml#

properties:
  compatible:
    enum:
      - qcom,dsi-phy-7nm
      - qcom,dsi-phy-7nm-8150
      - qcom,sc7280-dsi-phy-7nm

  reg:
    items:
      - description: dsi phy register set
      - description: dsi phy lane register set
      - description: dsi pll register set

  reg-names:
    items:
      - const: dsi_phy
      - const: dsi_phy_lane
      - const: dsi_pll

  vdds-supply:
    description: |
      Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)

  phy-type:
    description: D-PHY (default) or C-PHY mode
    enum: [ 10, 11 ]
    default: 10

required:
  - compatible
  - reg
  - reg-names
  - vdds-supply

unevaluatedProperties: false

examples:
  - |
     #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
     #include <dt-bindings/clock/qcom,rpmh.h>

     dsi-phy@ae94400 {
         compatible = "qcom,dsi-phy-7nm";
         reg = <0x0ae94400 0x200>,
               <0x0ae94600 0x280>,
               <0x0ae94900 0x260>;
         reg-names = "dsi_phy",
                     "dsi_phy_lane",
                     "dsi_pll";

         #clock-cells = <1>;
         #phy-cells = <0>;

         vdds-supply = <&vreg_l5a_0p88>;
         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                  <&rpmhcc RPMH_CXO_CLK>;
         clock-names = "iface", "ref";
     };


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Description of Qualcomm Display DSI PHY common dt properties

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

description: |
  This defines the DSI PHY dt properties which are common for all
  dsi phy versions.

properties:
  "#clock-cells":
    const: 1

  "#phy-cells":
    const: 0

  clocks:
    items:
      - description: Display AHB clock
      - description: Board XO source

  clock-names:
    items:
      - const: iface
      - const: ref

required:
  - clocks
  - clock-names
  - "#clock-cells"
  - "#phy-cells"

additionalProperties: true
...


code:
# SPDX-License-Identifier: GPL-2.0-only
# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
%YAML 1.2
---

$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Devicetree bindings for the GMU attached to certain Adreno GPUs

maintainers:
  - Rob Clark <robdclark@gmail.com>

description: |
  These bindings describe the Graphics Management Unit (GMU) that is attached
  to members of the Adreno A6xx GPU family. The GMU provides on-device power
  management and support to improve power efficiency and reduce the load on
  the CPU.

properties:
  compatible:
    items:
      - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
      - const: qcom,adreno-gmu

  reg:
    minItems: 3
    maxItems: 4

  reg-names:
    minItems: 3
    maxItems: 4

  clocks:
    minItems: 4
    maxItems: 7

  clock-names:
    minItems: 4
    maxItems: 7

  interrupts:
    items:
      - description: GMU HFI interrupt
      - description: GMU interrupt

  interrupt-names:
    items:
      - const: hfi
      - const: gmu

  power-domains:
    items:
      - description: CX power domain
      - description: GX power domain

  power-domain-names:
    items:
      - const: cx
      - const: gx

  iommus:
    maxItems: 1

  operating-points-v2: true

  opp-table:
    type: object

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - interrupts
  - interrupt-names
  - power-domains
  - power-domain-names
  - iommus
  - operating-points-v2

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,adreno-gmu-618.0
              - qcom,adreno-gmu-630.2
    then:
      properties:
        reg:
          items:
            - description: Core GMU registers
            - description: GMU PDC registers
            - description: GMU PDC sequence registers
        reg-names:
          items:
            - const: gmu
            - const: gmu_pdc
            - const: gmu_pdc_seq
        clocks:
          items:
            - description: GMU clock
            - description: GPU CX clock
            - description: GPU AXI clock
            - description: GPU MEMNOC clock
        clock-names:
          items:
            - const: gmu
            - const: cxo
            - const: axi
            - const: memnoc

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,adreno-gmu-635.0
    then:
      properties:
        reg:
          items:
            - description: Core GMU registers
            - description: Resource controller registers
            - description: GMU PDC registers
        reg-names:
          items:
            - const: gmu
            - const: rscc
            - const: gmu_pdc
        clocks:
          items:
            - description: GMU clock
            - description: GPU CX clock
            - description: GPU AXI clock
            - description: GPU MEMNOC clock
            - description: GPU AHB clock
            - description: GPU HUB CX clock
            - description: GPU SMMU vote clock
        clock-names:
          items:
            - const: gmu
            - const: cxo
            - const: axi
            - const: memnoc
            - const: ahb
            - const: hub
            - const: smmu_vote

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,adreno-gmu-640.1
    then:
      properties:
        reg:
          items:
            - description: Core GMU registers
            - description: GMU PDC registers
            - description: GMU PDC sequence registers
        reg-names:
          items:
            - const: gmu
            - const: gmu_pdc
            - const: gmu_pdc_seq

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,adreno-gmu-650.2
    then:
      properties:
        reg:
          items:
            - description: Core GMU registers
            - description: Resource controller registers
            - description: GMU PDC registers
            - description: GMU PDC sequence registers
        reg-names:
          items:
            - const: gmu
            - const: rscc
            - const: gmu_pdc
            - const: gmu_pdc_seq

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,adreno-gmu-640.1
              - qcom,adreno-gmu-650.2
    then:
      properties:
        clocks:
          items:
            - description: GPU AHB clock
            - description: GMU clock
            - description: GPU CX clock
            - description: GPU AXI clock
            - description: GPU MEMNOC clock
        clock-names:
          items:
            - const: ahb
            - const: gmu
            - const: cxo
            - const: axi
            - const: memnoc

examples:
  - |
    #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gmu: gmu@506a000 {
        compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";

        reg = <0x506a000 0x30000>,
              <0xb280000 0x10000>,
              <0xb480000 0x10000>;
        reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";

        clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
                 <&gpucc GPU_CC_CXO_CLK>,
                 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
                 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
        clock-names = "gmu", "cxo", "axi", "memnoc";

        interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "hfi", "gmu";

        power-domains = <&gpucc GPU_CX_GDSC>,
                        <&gpucc GPU_GX_GDSC>;
        power-domain-names = "cx", "gx";

        iommus = <&adreno_smmu 5>;
        operating-points-v2 = <&gmu_opp_table>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---

$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Devicetree bindings for the Adreno or Snapdragon GPUs

maintainers:
  - Rob Clark <robdclark@gmail.com>

properties:
  compatible:
    oneOf:
      - description: |
          The driver is parsing the compat string for Adreno to
          figure out the gpu-id and patch level.
        items:
          - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
          - const: qcom,adreno
      - description: |
          The driver is parsing the compat string for Imageon to
          figure out the gpu-id and patch level.
        items:
          - pattern: '^amd,imageon-200\.[0-1]$'
          - const: amd,imageon

  clocks: true

  clock-names: true

  reg:
    minItems: 1
    maxItems: 3

  reg-names:
    minItems: 1
    items:
      - const: kgsl_3d0_reg_memory
      - const: cx_mem
      - const: cx_dbgc

  interrupts:
    maxItems: 1

  interrupt-names:
    maxItems: 1

  interconnects:
    minItems: 1
    maxItems: 2

  interconnect-names:
    minItems: 1
    items:
      - const: gfx-mem
      - const: ocmem

  iommus:
    minItems: 1
    maxItems: 64

  sram:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 1
    maxItems: 4
    items:
      maxItems: 1
    description: |
      phandles to one or more reserved on-chip SRAM regions.
      phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
      a4xx Snapdragon SoCs. See
      Documentation/devicetree/bindings/sram/qcom,ocmem.yaml

  operating-points-v2: true
  opp-table:
    type: object

  power-domains:
    maxItems: 1

  zap-shader:
    type: object
    additionalProperties: false
    description: |
      For a5xx and a6xx devices this node contains a memory-region that
      points to reserved memory to store the zap shader that can be used to
      help bring the GPU out of secure mode.
    properties:
      memory-region:
        $ref: /schemas/types.yaml#/definitions/phandle

      firmware-name:
        description: |
          Default name of the firmware to load to the remote processor.

  "#cooling-cells":
    const: 2

  nvmem-cell-names:
    maxItems: 1

  nvmem-cells:
    description: efuse registers
    maxItems: 1

  qcom,gmu:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      For GMU attached devices a phandle to the GMU device that will
      control the power for the GPU.

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'

    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 7

        clock-names:
          items:
            anyOf:
              - const: core
                description: GPU Core clock
              - const: iface
                description: GPU Interface clock
              - const: mem
                description: GPU Memory clock
              - const: mem_iface
                description: GPU Memory Interface clock
              - const: alt_mem_iface
                description: GPU Alternative Memory Interface clock
              - const: gfx3d
                description: GPU 3D engine clock
              - const: rbbmtimer
                description: GPU RBBM Timer for Adreno 5xx series
          minItems: 2
          maxItems: 7

      required:
        - clocks
        - clock-names
  - if:
      properties:
        compatible:
          contains:
            pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'

    then: # Since Adreno 6xx series clocks should be defined in GMU
      properties:
        clocks: false
        clock-names: false

examples:
  - |

    // Example a3xx/4xx:

    #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
    #include <dt-bindings/clock/qcom,rpmcc.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gpu: gpu@fdb00000 {
        compatible = "qcom,adreno-330.2", "qcom,adreno";

        reg = <0xfdb00000 0x10000>;
        reg-names = "kgsl_3d0_reg_memory";

        clock-names = "core", "iface", "mem_iface";
        clocks = <&mmcc OXILI_GFX3D_CLK>,
                 <&mmcc OXILICX_AHB_CLK>,
                 <&mmcc OXILICX_AXI_CLK>;

        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "kgsl_3d0_irq";

        sram = <&gpu_sram>;
        power-domains = <&mmcc OXILICX_GDSC>;
        operating-points-v2 = <&gpu_opp_table>;
        iommus = <&gpu_iommu 0>;
        #cooling-cells = <2>;
    };

    ocmem@fdd00000 {
        compatible = "qcom,msm8974-ocmem";

        reg = <0xfdd00000 0x2000>,
              <0xfec00000 0x180000>;
        reg-names = "ctrl", "mem";

        clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
                 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
        clock-names = "core", "iface";

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0xfec00000 0x100000>;

        gpu_sram: gpu-sram@0 {
            reg = <0x0 0x100000>;
        };
    };
  - |

    // Example a6xx (with GMU):

    #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,sdm845.h>

    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;

        zap_shader_region: gpu@8f200000 {
            compatible = "shared-dma-pool";
            reg = <0x0 0x90b00000 0x0 0xa00000>;
            no-map;
        };
    };

    gpu@5000000 {
        compatible = "qcom,adreno-630.2", "qcom,adreno";

        reg = <0x5000000 0x40000>, <0x509e000 0x10>;
        reg-names = "kgsl_3d0_reg_memory", "cx_mem";

        #cooling-cells = <2>;

        interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

        iommus = <&adreno_smmu 0>;

        operating-points-v2 = <&gpu_opp_table>;

        interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
        interconnect-names = "gfx-mem";

        qcom,gmu = <&gmu>;

        gpu_opp_table: opp-table {
            compatible = "operating-points-v2";

            opp-430000000 {
                opp-hz = /bits/ 64 <430000000>;
                opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
                opp-peak-kBps = <5412000>;
            };

            opp-355000000 {
                opp-hz = /bits/ 64 <355000000>;
                opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
                opp-peak-kBps = <3072000>;
            };

            opp-267000000 {
                opp-hz = /bits/ 64 <267000000>;
                opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
                opp-peak-kBps = <3072000>;
            };

            opp-180000000 {
                opp-hz = /bits/ 64 <180000000>;
                opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
                opp-peak-kBps = <1804000>;
            };
        };

        zap-shader {
            memory-region = <&zap_shader_region>;
            firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---

$id: http://devicetree.org/schemas/display/msm/hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Adreno/Snapdragon HDMI output

maintainers:
  - Rob Clark <robdclark@gmail.com>

properties:
  compatible:
    enum:
      - qcom,hdmi-tx-8084
      - qcom,hdmi-tx-8660
      - qcom,hdmi-tx-8960
      - qcom,hdmi-tx-8974
      - qcom,hdmi-tx-8994
      - qcom,hdmi-tx-8996

  clocks:
    minItems: 1
    maxItems: 5

  clock-names:
    minItems: 1
    maxItems: 5

  reg:
    minItems: 1
    maxItems: 3

  reg-names:
    minItems: 1
    items:
      - const: core_physical
      - const: qfprom_physical
      - const: hdcp_physical

  interrupts:
    maxItems: 1

  phys:
    maxItems: 1

  phy-names:
    enum:
      - hdmi_phy
      - hdmi-phy
    deprecated: true

  core-vdda-supply:
    description: phandle to VDDA supply regulator

  hdmi-mux-supply:
    description: phandle to mux regulator
    deprecated: true

  core-vcc-supply:
    description: phandle to VCC supply regulator

  hpd-gpios:
    maxItems: 1
    description: hpd pin

  qcom,hdmi-tx-mux-en-gpios:
    maxItems: 1
    deprecated: true
    description: HDMI mux enable pin

  qcom,hdmi-tx-mux-sel-gpios:
    maxItems: 1
    deprecated: true
    description: HDMI mux select pin

  qcom,hdmi-tx-mux-lpm-gpios:
    maxItems: 1
    deprecated: true
    description: HDMI mux lpm pin

  '#sound-dai-cells':
    const: 1

  ports:
    type: object
    $ref: /schemas/graph.yaml#/properties/ports
    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        description: |
          Input endpoints of the controller.

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        description: |
          Output endpoints of the controller.

    required:
      - port@0

required:
  - compatible
  - clocks
  - clock-names
  - reg
  - reg-names
  - interrupts
  - phys

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,hdmi-tx-8960
              - qcom,hdmi-tx-8660
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: core
            - const: master_iface
            - const: slave_iface
        core-vcc-supplies: false

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,hdmi-tx-8974
              - qcom,hdmi-tx-8084
              - qcom,hdmi-tx-8994
              - qcom,hdmi-tx-8996
    then:
      properties:
        clocks:
          minItems: 5
        clock-names:
          items:
            - const: mdp_core
            - const: iface
            - const: core
            - const: alt_iface
            - const: extp
        hdmi-mux-supplies: false

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    hdmi: hdmi@4a00000 {
      compatible = "qcom,hdmi-tx-8960";
      reg-names = "core_physical";
      reg = <0x04a00000 0x2f0>;
      interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
      clock-names = "core",
                    "master_iface",
                    "slave_iface";
      clocks = <&clk 61>,
               <&clk 72>,
               <&clk 98>;
      hpd-gpios = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
      core-vdda-supply = <&pm8921_hdmi_mvs>;
      hdmi-mux-supply = <&ext_3p3v>;
      pinctrl-names = "default", "sleep";
      pinctrl-0 = <&hpd_active  &ddc_active  &cec_active>;
      pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;

      phys = <&hdmi_phy>;
    };
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
    #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    hdmi@9a0000 {
      compatible = "qcom,hdmi-tx-8996";
      reg = <0x009a0000 0x50c>,
            <0x00070000 0x6158>,
            <0x009e0000 0xfff>;
      reg-names = "core_physical",
                  "qfprom_physical",
                  "hdcp_physical";

      interrupt-parent = <&mdss>;
      interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&mmcc MDSS_MDP_CLK>,
               <&mmcc MDSS_AHB_CLK>,
               <&mmcc MDSS_HDMI_CLK>,
               <&mmcc MDSS_HDMI_AHB_CLK>,
               <&mmcc MDSS_EXTPCLK_CLK>;
      clock-names = "mdp_core",
                    "iface",
                    "core",
                    "alt_iface",
                    "extp";

      phys = <&hdmi_phy>;
      #sound-dai-cells = <1>;

      pinctrl-names = "default", "sleep";
      pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
      pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;

      core-vdda-supply = <&vreg_l12a_1p8>;
      core-vcc-supply = <&vreg_s4a_1p8>;

      ports {
        #address-cells = <1>;
        #size-cells = <0>;

        port@0 {
          reg = <0>;
          endpoint {
            remote-endpoint = <&mdp5_intf3_out>;
          };
        };
      };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/msm/mdp4.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Adreno/Snapdragon MDP4 display controller

description: >
  MDP4 display controller found in SoCs like MSM8960, APQ8064 and MSM8660.

maintainers:
  - Rob Clark <robdclark@gmail.com>

properties:
  compatible:
    const: qcom,mdp4

  clocks:
    minItems: 6
    maxItems: 6

  clock-names:
    items:
      - const: core_clk
      - const: iface_clk
      - const: bus_clk
      - const: lut_clk
      - const: hdmi_clk
      - const: tv_clk

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  iommus:
    maxItems: 4

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: LCDC/LVDS

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: DSI1 Cmd / Video

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: DSI2 Cmd / Video

      port@3:
        $ref: /schemas/graph.yaml#/properties/port
        description: Digital TV

  qcom,lcdc-align-lsb:
    type: boolean
    description: >
      Indication that LSB alignment should be used for LCDC.
      This is only valid for 18bpp panels.

required:
  - compatible
  - reg
  - clocks
  - ports

additionalProperties: false

examples:
  - |
    mdp: mdp@5100000 {
        compatible = "qcom,mdp4";
        reg = <0x05100000 0xf0000>;
        interrupts = <0 75 0>;
        clock-names =
            "core_clk",
            "iface_clk",
            "bus_clk",
            "lut_clk",
            "hdmi_clk",
            "tv_clk";
        clocks =
            <&mmcc 77>,
            <&mmcc 86>,
            <&mmcc 102>,
            <&mmcc 75>,
            <&mmcc 97>,
            <&mmcc 12>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                mdp_lvds_out: endpoint {
                };
            };

            port@1 {
                reg = <1>;
                mdp_dsi1_out: endpoint {
                };
            };

            port@2 {
                reg = <2>;
                mdp_dsi2_out: endpoint {
                };
            };

            port@3 {
                reg = <3>;
                mdp_dtv_out: endpoint {
                    remote-endpoint = <&hdmi_in>;
                };
            };
        };
    };


code:
Qualcomm adreno/snapdragon MDP5 display controller

Description:

This is the bindings documentation for the MDP5 display
controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.

MDP5:
Required properties:
- compatible:
  * "qcom,mdp5" - MDP5
- reg: Physical base address and length of the controller's registers.
- reg-names: The names of register regions. The following regions are required:
  * "mdp_phys"
- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required.
-   * "bus"
-   * "iface"
-   * "core"
-   * "vsync"
- ports: contains the list of output ports from MDP. These connect to interfaces
  that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
  special case since it is a part of the MDP block itself).

  Each output port contains an endpoint that describes how it is connected to an
  external interface. These are described by the standard properties documented
  here:
	Documentation/devicetree/bindings/graph.txt
	Documentation/devicetree/bindings/media/video-interfaces.txt

  The availability of output ports can vary across SoC revisions:

  For MSM8974 and APQ8084:
	 Port 0 -> MDP_INTF0 (eDP)
	 Port 1 -> MDP_INTF1 (DSI1)
	 Port 2 -> MDP_INTF2 (DSI2)
	 Port 3 -> MDP_INTF3 (HDMI)

  For MSM8916:
	 Port 0 -> MDP_INTF1 (DSI1)

  For MSM8994 and MSM8996:
	 Port 0 -> MDP_INTF1 (DSI1)
	 Port 1 -> MDP_INTF2 (DSI2)
	 Port 2 -> MDP_INTF3 (HDMI)

Optional properties:
- clock-names: the following clocks are optional:
  * "lut"
  * "tbu"
  * "tbu_rt"

Example:

/ {
	...

	mdss: mdss@1a00000 {
		compatible = "qcom,mdss";
		reg = <0x1a00000 0x1000>,
		      <0x1ac8000 0x3000>;
		reg-names = "mdss_phys", "vbif_phys";

		power-domains = <&gcc MDSS_GDSC>;

		clocks = <&gcc GCC_MDSS_AHB_CLK>,
			 <&gcc GCC_MDSS_AXI_CLK>,
			 <&gcc GCC_MDSS_VSYNC_CLK>;
		clock-names = "iface",
			      "bus",
			      "vsync"

		interrupts = <0 72 0>;

		interrupt-controller;
		#interrupt-cells = <1>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		mdp: mdp@1a01000 {
			compatible = "qcom,mdp5";
			reg = <0x1a01000 0x90000>;
			reg-names = "mdp_phys";

			interrupt-parent = <&mdss>;
			interrupts = <0 0>;

			clocks = <&gcc GCC_MDSS_AHB_CLK>,
				 <&gcc GCC_MDSS_AXI_CLK>,
				 <&gcc GCC_MDSS_MDP_CLK>,
				 <&gcc GCC_MDSS_VSYNC_CLK>;
			clock-names = "iface",
				      "bus",
				      "core",
				      "vsync";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					mdp5_intf1_out: endpoint {
						remote-endpoint = <&dsi0_in>;
					};
				};
			};
		};

		dsi0: dsi@1a98000 {
			...
			ports {
				...
				port@0 {
					reg = <0>;
					dsi0_in: endpoint {
						remote-endpoint = <&mdp5_intf1_out>;
					};
				};
				...
			};
			...
		};

		dsi_phy0: dsi-phy@1a98300 {
			...
		};
	};
};


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/mdss-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display MDSS common properties

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  - Rob Clark <robdclark@gmail.com>

description:
  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  sub-blocks like DPU display controller, DSI and DP interfaces etc.

properties:
  reg:
    maxItems: 1

  reg-names:
    const: mdss

  power-domains:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 4

  clock-names:
    minItems: 2
    maxItems: 4

  interrupts:
    maxItems: 1

  interrupt-controller: true

  "#address-cells": true

  "#size-cells": true

  "#interrupt-cells":
    const: 1

  iommus:
    minItems: 1
    items:
      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1

  ranges: true

  interconnects:
    minItems: 1
    items:
      - description: Interconnect path from mdp0 (or a single mdp) port to the data bus
      - description: Interconnect path from mdp1 port to the data bus

  interconnect-names:
    minItems: 1
    items:
      - const: mdp0-mem
      - const: mdp1-mem

  resets:
    items:
      - description: MDSS_CORE reset

required:
  - compatible
  - reg
  - reg-names
  - power-domains
  - clocks
  - interrupts
  - interrupt-controller
  - iommus
  - ranges

additionalProperties: true


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Mobile Display SubSystem (MDSS)

maintainers:
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  - Rob Clark <robdclark@gmail.com>

description:
  This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
  encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.

properties:
  compatible:
    enum:
      - qcom,mdss

  reg:
    minItems: 2
    maxItems: 3

  reg-names:
    minItems: 2
    items:
      - const: mdss_phys
      - const: vbif_phys
      - const: vbif_nrt_phys

  interrupts:
    maxItems: 1

  interrupt-controller: true

  "#interrupt-cells":
    const: 1

  power-domains:
    maxItems: 1
    description: |
      The MDSS power domain provided by GCC

  clocks:
    minItems: 1
    items:
      - description: Display abh clock
      - description: Display axi clock
      - description: Display vsync clock

  clock-names:
    minItems: 1
    items:
      - const: iface
      - const: bus
      - const: vsync

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  ranges: true

  resets:
    items:
      - description: MDSS_CORE reset

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-controller
  - "#interrupt-cells"
  - power-domains
  - clocks
  - clock-names
  - "#address-cells"
  - "#size-cells"
  - ranges

patternProperties:
  "^mdp@[1-9a-f][0-9a-f]*$":
    type: object
    properties:
      compatible:
        const: qcom,mdp5

  "^dsi@[1-9a-f][0-9a-f]*$":
    type: object
    properties:
      compatible:
        const: qcom,mdss-dsi-ctrl

  "^phy@[1-9a-f][0-9a-f]*$":
    type: object
    properties:
      compatible:
        enum:
          - qcom,dsi-phy-14nm
          - qcom,dsi-phy-14nm-660
          - qcom,dsi-phy-14nm-8953
          - qcom,dsi-phy-20nm
          - qcom,dsi-phy-28nm-hpm
          - qcom,dsi-phy-28nm-lp

  "^hdmi-phy@[1-9a-f][0-9a-f]*$":
    type: object
    properties:
      compatible:
        enum:
          - qcom,hdmi-phy-8084
          - qcom,hdmi-phy-8660
          - qcom,hdmi-phy-8960
          - qcom,hdmi-phy-8974
          - qcom,hdmi-phy-8996

  "^hdmi-tx@[1-9a-f][0-9a-f]*$":
    type: object
    properties:
      compatible:
        enum:
          - qcom,hdmi-tx-8084
          - qcom,hdmi-tx-8660
          - qcom,hdmi-tx-8960
          - qcom,hdmi-tx-8974
          - qcom,hdmi-tx-8994
          - qcom,hdmi-tx-8996

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8916.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    mdss@1a00000 {
        compatible = "qcom,mdss";
        reg = <0x1a00000 0x1000>,
              <0x1ac8000 0x3000>;
        reg-names = "mdss_phys", "vbif_phys";

        power-domains = <&gcc MDSS_GDSC>;

        clocks = <&gcc GCC_MDSS_AHB_CLK>,
                 <&gcc GCC_MDSS_AXI_CLK>,
                 <&gcc GCC_MDSS_VSYNC_CLK>;
        clock-names = "iface",
                      "bus",
                      "vsync";

        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-controller;
        #interrupt-cells = <1>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        mdp@1a01000 {
            compatible = "qcom,mdp5";
            reg = <0x01a01000 0x89000>;
            reg-names = "mdp_phys";

            interrupt-parent = <&mdss>;
            interrupts = <0>;

            clocks = <&gcc GCC_MDSS_AHB_CLK>,
                     <&gcc GCC_MDSS_AXI_CLK>,
                     <&gcc GCC_MDSS_MDP_CLK>,
                     <&gcc GCC_MDSS_VSYNC_CLK>;
            clock-names = "iface",
                      "bus",
                      "core",
                      "vsync";

            iommus = <&apps_iommu 4>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    mdp5_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };
            };
        };
    };
...