code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos850 SoC clock controller

maintainers:
  - Sam Protsenko <semen.protsenko@linaro.org>
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  Exynos850 clock controller is comprised of several CMU units, generating
  clocks for different domains. Those CMU units are modeled as separate device
  tree nodes, and might depend on each other. Root clocks in that clock tree are
  two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
  clocks must be defined as fixed-rate clocks in dts.

  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.

  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All clocks available for usage
  in clock consumer nodes are defined as preprocessor macros in
  'dt-bindings/clock/exynos850.h' header.

properties:
  compatible:
    enum:
      - samsung,exynos850-cmu-top
      - samsung,exynos850-cmu-apm
      - samsung,exynos850-cmu-aud
      - samsung,exynos850-cmu-cmgp
      - samsung,exynos850-cmu-core
      - samsung,exynos850-cmu-dpu
      - samsung,exynos850-cmu-hsi
      - samsung,exynos850-cmu-is
      - samsung,exynos850-cmu-mfcmscl
      - samsung,exynos850-cmu-peri

  clocks:
    minItems: 1
    maxItems: 5

  clock-names:
    minItems: 1
    maxItems: 5

  "#clock-cells":
    const: 1

  reg:
    maxItems: 1

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos850-cmu-top

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)

        clock-names:
          items:
            - const: oscclk

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos850-cmu-apm

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_APM bus clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_clkcmu_apm_bus

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos850-cmu-aud

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: AUD clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_aud

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos850-cmu-cmgp

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_CMGP bus clock (from CMU_APM)

        clock-names:
          items:
            - const: oscclk
            - const: gout_clkcmu_cmgp_bus

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos850-cmu-core

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_CORE bus clock (from CMU_TOP)
            - description: CCI clock (from CMU_TOP)
            - description: eMMC clock (from CMU_TOP)
            - description: SSS clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_core_bus
            - const: dout_core_cci
            - const: dout_core_mmc_embd
            - const: dout_core_sss

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos850-cmu-dpu

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: DPU clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_dpu

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos850-cmu-hsi

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: External RTC clock (32768 Hz)
            - description: CMU_HSI bus clock (from CMU_TOP)
            - description: SD card clock (from CMU_TOP)
            - description: "USB 2.0 DRD clock (from CMU_TOP)"

        clock-names:
          items:
            - const: oscclk
            - const: rtcclk
            - const: dout_hsi_bus
            - const: dout_hsi_mmc_card
            - const: dout_hsi_usb20drd

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos850-cmu-is

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_IS bus clock (from CMU_TOP)
            - description: Image Texture Processing core clock (from CMU_TOP)
            - description: Visual Recognition Accelerator clock (from CMU_TOP)
            - description: Geometric Distortion Correction clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_is_bus
            - const: dout_is_itp
            - const: dout_is_vra
            - const: dout_is_gdc

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos850-cmu-mfcmscl

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: Multi-Format Codec clock (from CMU_TOP)
            - description: Memory to Memory Scaler clock (from CMU_TOP)
            - description: Multi-Channel Scaler clock (from CMU_TOP)
            - description: JPEG codec clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_mfcmscl_mfc
            - const: dout_mfcmscl_m2m
            - const: dout_mfcmscl_mcsc
            - const: dout_mfcmscl_jpeg

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos850-cmu-peri

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_PERI bus clock (from CMU_TOP)
            - description: UART clock (from CMU_TOP)
            - description: Parent clock for HSI2C and SPI (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_peri_bus
            - const: dout_peri_uart
            - const: dout_peri_ip

required:
  - compatible
  - "#clock-cells"
  - clocks
  - clock-names
  - reg

additionalProperties: false

examples:
  # Clock controller node for CMU_PERI
  - |
    #include <dt-bindings/clock/exynos850.h>

    cmu_peri: clock-controller@10030000 {
        compatible = "samsung,exynos850-cmu-peri";
        reg = <0x10030000 0x8000>;
        #clock-cells = <1>;

        clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
                 <&cmu_top CLK_DOUT_PERI_UART>,
                 <&cmu_top CLK_DOUT_PERI_IP>;
        clock-names = "oscclk", "dout_peri_bus",
                      "dout_peri_uart", "dout_peri_ip";
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos Auto v9 SoC clock controller

maintainers:
  - Chanho Park <chanho61.park@samsung.com>
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  Exynos Auto v9 clock controller is comprised of several CMU units, generating
  clocks for different domains. Those CMU units are modeled as separate device
  tree nodes, and might depend on each other. Root clocks in that clock tree are
  two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
  The external OSCCLK must be defined as fixed-rate clock in dts.

  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
  dividers; all other clocks of function blocks (other CMUs) are usually
  derived from CMU_TOP.

  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All clocks available for usage
  in clock consumer nodes are defined as preprocessor macros in
  'include/dt-bindings/clock/samsung,exynosautov9.h' header.

properties:
  compatible:
    enum:
      - samsung,exynosautov9-cmu-top
      - samsung,exynosautov9-cmu-busmc
      - samsung,exynosautov9-cmu-core
      - samsung,exynosautov9-cmu-fsys0
      - samsung,exynosautov9-cmu-fsys1
      - samsung,exynosautov9-cmu-fsys2
      - samsung,exynosautov9-cmu-peric0
      - samsung,exynosautov9-cmu-peric1
      - samsung,exynosautov9-cmu-peris

  clocks:
    minItems: 1
    maxItems: 5

  clock-names:
    minItems: 1
    maxItems: 5

  "#clock-cells":
    const: 1

  reg:
    maxItems: 1

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynosautov9-cmu-top

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)

        clock-names:
          items:
            - const: oscclk

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynosautov9-cmu-busmc

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_BUSMC bus clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_clkcmu_busmc_bus

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynosautov9-cmu-core

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_CORE bus clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_clkcmu_core_bus

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynosautov9-cmu-fsys0

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_FSYS0 bus clock (from CMU_TOP)
            - description: CMU_FSYS0 pcie clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_clkcmu_fsys0_bus
            - const: dout_clkcmu_fsys0_pcie

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynosautov9-cmu-fsys1

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_FSYS1 bus clock (from CMU_TOP)
            - description: CMU_FSYS1 mmc card clock (from CMU_TOP)
            - description: CMU_FSYS1 usb clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_clkcmu_fsys1_bus
            - const: gout_clkcmu_fsys1_mmc_card
            - const: dout_clkcmu_fsys1_usbdrd

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynosautov9-cmu-fsys2

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_FSYS2 bus clock (from CMU_TOP)
            - description: UFS clock (from CMU_TOP)
            - description: Ethernet clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_clkcmu_fsys2_bus
            - const: dout_fsys2_clkcmu_ufs_embd
            - const: dout_fsys2_clkcmu_ethernet

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynosautov9-cmu-peric0

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_PERIC0 bus clock (from CMU_TOP)
            - description: PERIC0 IP clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_clkcmu_peric0_bus
            - const: dout_clkcmu_peric0_ip

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynosautov9-cmu-peric1

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_PERIC1 bus clock (from CMU_TOP)
            - description: PERIC1 IP clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_clkcmu_peric1_bus
            - const: dout_clkcmu_peric1_ip

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynosautov9-cmu-peris

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_PERIS bus clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_clkcmu_peris_bus

required:
  - compatible
  - "#clock-cells"
  - clocks
  - clock-names
  - reg

additionalProperties: false

examples:
  # Clock controller node for CMU_FSYS2
  - |
    #include <dt-bindings/clock/samsung,exynosautov9.h>

    cmu_fsys2: clock-controller@17c00000 {
        compatible = "samsung,exynosautov9-cmu-fsys2";
        reg = <0x17c00000 0x8000>;
        #clock-cells = <1>;

        clocks = <&xtcxo>,
                 <&cmu_top DOUT_CLKCMU_FSYS2_BUS>,
                 <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>,
                 <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>;
        clock-names = "oscclk",
                      "dout_clkcmu_fsys2_bus",
                      "dout_fsys2_clkcmu_ufs_embd",
                      "dout_fsys2_clkcmu_ethernet";
    };

...

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,s2mps11.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S2M and S5M family clock generator block

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  This is a part of device tree bindings for S2M and S5M family of Power
  Management IC (PMIC).

  The S2MPS11/13/15 and S5M8767 provide three(AP/CP/BT) buffered 32.768 kHz
  outputs. The S2MPS14 provides two (AP/BT) buffered 32.768 KHz outputs.

  All available clocks are defined as preprocessor macros in
  dt-bindings/clock/samsung,s2mps11.h header.

  See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for
  additional information and example.

properties:
  compatible:
    enum:
      - samsung,s2mps11-clk
      - samsung,s2mps13-clk # S2MPS13 and S2MPS15
      - samsung,s2mps14-clk
      - samsung,s5m8767-clk

  "#clock-cells":
    const: 1

  clock-output-names:
    maxItems: 3
    description: Names for AP, CP and BT clocks.

required:
  - compatible
  - "#clock-cells"

additionalProperties: false


code:
* Samsung S3C2410 Clock Controller

The S3C2410 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to the s3c2410,
s3c2440 and s3c2442 SoCs in the s3c24x family.

Required Properties:

- compatible: should be one of the following.
  - "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
  - "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
  - "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
- reg: physical base address of the controller and length of memory mapped
  region.
- #clock-cells: should be 1.

Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.

All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2410.h header and can be used in device
tree sources.

External clocks:

The xti clock used as input for the plls is generated outside the SoC. It is
expected that is are defined using standard clock bindings with a
clock-output-names value of "xti".

Example: Clock controller node:

	clocks: clock-controller@4c000000 {
		compatible = "samsung,s3c2410-clock";
		reg = <0x4c000000 0x20>;
		#clock-cells = <1>;
	};

Example: UART controller node that consumes the clock generated by the clock
  controller (refer to the standard clock bindings for information about
  "clocks" and "clock-names" properties):

	serial@50004000 {
		compatible = "samsung,s3c2440-uart";
		reg = <0x50004000 0x4000>;
		interrupts = <1 23 3 4>, <1 23 4 4>;
		clock-names = "uart", "clk_uart_baud2";
		clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
	};


code:
* Samsung S3C2412 Clock Controller

The S3C2412 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to the s3c2412
and s3c2413 SoCs in the s3c24x family.

Required Properties:

- compatible: should be "samsung,s3c2412-clock"
- reg: physical base address of the controller and length of memory mapped
  region.
- #clock-cells: should be 1.

Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.

All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2412.h header and can be used in device
tree sources.

External clocks:

There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
 - "xti" - crystal input - required,
 - "ext" - external clock source - optional,

Example: Clock controller node:

	clocks: clock-controller@4c000000 {
		compatible = "samsung,s3c2412-clock";
		reg = <0x4c000000 0x20>;
		#clock-cells = <1>;
	};

Example: UART controller node that consumes the clock generated by the clock
  controller (refer to the standard clock bindings for information about
  "clocks" and "clock-names" properties):

	serial@50004000 {
		compatible = "samsung,s3c2412-uart";
		reg = <0x50004000 0x4000>;
		interrupts = <1 23 3 4>, <1 23 4 4>;
		clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
		clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
			 <&clocks SCLK_UART>;
	};


code:
* Samsung S3C2443 Clock Controller

The S3C2443 clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to all SoCs in
the s3c24x family starting with the s3c2443.

Required Properties:

- compatible: should be one of the following.
  - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
  - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
  - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
- reg: physical base address of the controller and length of memory mapped
  region.
- #clock-cells: should be 1.

Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular SoC.

All available clocks are defined as preprocessor macros in
dt-bindings/clock/s3c2443.h header and can be used in device
tree sources.

External clocks:

There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
 - "xti" - crystal input - required,
 - "ext" - external clock source - optional,
 - "ext_i2s" - external I2S clock - optional,
 - "ext_uart" - external uart clock - optional,

Example: Clock controller node:

	clocks: clock-controller@4c000000 {
		compatible = "samsung,s3c2416-clock";
		reg = <0x4c000000 0x40>;
		#clock-cells = <1>;
	};

Example: UART controller node that consumes the clock generated by the clock
  controller (refer to the standard clock bindings for information about
  "clocks" and "clock-names" properties):

	serial@50004000 {
		compatible = "samsung,s3c2440-uart";
		reg = <0x50004000 0x4000>;
		interrupts = <1 23 3 4>, <1 23 4 4>;
		clock-names = "uart", "clk_uart_baud2",
				"clk_uart_baud3";
		clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
				<&clocks SCLK_UART>;
	};


code:
* Samsung S3C64xx Clock Controller

The S3C64xx clock controller generates and supplies clock to various controllers
within the SoC. The clock binding described here is applicable to all SoCs in
the S3C64xx family.

Required Properties:

- compatible: should be one of the following.
  - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
  - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.

- reg: physical base address of the controller and length of memory mapped
  region.

- #clock-cells: should be 1.

Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Some of the clocks are available only
on a particular S3C64xx SoC and this is specified where applicable.

All available clocks are defined as preprocessor macros in
dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
tree sources.

External clocks:

There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
 - "fin_pll" - PLL input clock (xtal/extclk) - required,
 - "xusbxti" - USB xtal - required,
 - "iiscdclk0" - I2S0 codec clock - optional,
 - "iiscdclk1" - I2S1 codec clock - optional,
 - "iiscdclk2" - I2S2 codec clock - optional,
 - "pcmcdclk0" - PCM0 codec clock - optional,
 - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.

Example: Clock controller node:

	clock: clock-controller@7e00f000 {
		compatible = "samsung,s3c6410-clock";
		reg = <0x7e00f000 0x1000>;
		#clock-cells = <1>;
	};

Example: Required external clocks:

	fin_pll: clock-fin-pll {
		compatible = "fixed-clock";
		clock-output-names = "fin_pll";
		clock-frequency = <12000000>;
		#clock-cells = <0>;
	};

	xusbxti: clock-xusbxti {
		compatible = "fixed-clock";
		clock-output-names = "xusbxti";
		clock-frequency = <48000000>;
		#clock-cells = <0>;
	};

Example: UART controller node that consumes the clock generated by the clock
  controller (refer to the standard clock bindings for information about
  "clocks" and "clock-names" properties):

		uart0: serial@7f005000 {
			compatible = "samsung,s3c6400-uart";
			reg = <0x7f005000 0x100>;
			interrupt-parent = <&vic1>;
			interrupts = <5>;
			clock-names = "uart", "clk_uart_baud2",
					"clk_uart_baud3";
			clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
					<&clock SCLK_UART>;
		};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S5Pv210 SoC Audio SubSystem clock controller

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  All available clocks are defined as preprocessor macros in
  include/dt-bindings/clock/s5pv210-audss.h header.

properties:
  compatible:
    const: samsung,s5pv210-audss-clock

  clocks:
    minItems: 4
    items:
      - description:
          AHB bus clock of the Audio Subsystem.
      - description:
          Optional fixed rate PLL reference clock, parent of mout_audss. If not
          specified (i.e. xusbxti is used for PLL reference), it is fixed to a
          clock named "xxti".
      - description:
          Input PLL to the AudioSS block, parent of mout_audss.
      - description:
          Audio bus clock, parent of mout_i2s.
      - description:
          Optional external i2s clock, parent of mout_i2s. If not specified, it
          is fixed to a clock named "iiscdclk0".

  clock-names:
    minItems: 4
    items:
      - const: hclk
      - const: xxti
      - const: fout_epll
      - const: sclk_audio0
      - const: iiscdclk0

  "#clock-cells":
    const: 1

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - clocks
  - clock-names
  - "#clock-cells"
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/s5pv210.h>

    clock-controller@c0900000 {
        compatible = "samsung,s5pv210-audss-clock";
        reg = <0xc0900000 0x1000>;
        #clock-cells = <1>;
        clock-names = "hclk", "xxti", "fout_epll", "sclk_audio0";
        clocks = <&clocks DOUT_HCLKP>, <&xxti>, <&clocks FOUT_EPLL>,
                 <&clocks SCLK_AUDIO0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  Expected external clocks, defined in DTS as fixed-rate clocks with a matching
  name::
    - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
      the SoC,
    - "xusbxti" - external crystal oscillator connected to XUSBXTI and XUSBXTO
      pins of the SoC,

  All available clocks are defined as preprocessor macros in
  include/dt-bindings/clock/s5pv210.h header.

properties:
  compatible:
    enum:
      - samsung,s5pv210-clock
      - samsung,s5p6442-clock

  clocks:
    items:
      - description: xxti clock
      - description: xusbxti clock

  clock-names:
    items:
      - const: xxti
      - const: xusbxti

  "#clock-cells":
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - "#clock-cells"
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/s5pv210.h>

    xxti: clock-0 {
        compatible = "fixed-clock";
        clock-frequency = <0>;
        clock-output-names = "xxti";
        #clock-cells = <0>;
    };

    xusbxti: clock-1 {
        compatible = "fixed-clock";
        clock-frequency = <0>;
        clock-output-names = "xusbxti";
        #clock-cells = <0>;
    };

    clock-controller@e0100000 {
        compatible = "samsung,s5pv210-clock";
        reg = <0xe0100000 0x10000>;
        clock-names = "xxti", "xusbxti";
        clocks = <&xxti>, <&xusbxti>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)

maintainers:
  - Sagar Kadam <sagar.kadam@sifive.com>
  - Paul Walmsley  <paul.walmsley@sifive.com>

description:
  On the FU540 family of SoCs, most system-wide clock and reset integration
  is via the PRCI IP block.
  The clock consumer should specify the desired clock via the clock ID
  macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
  These macros begin with PRCI_CLK_.

  The hfclk and rtcclk nodes are required, and represent physical
  crystals or resonators located on the PCB.  These nodes should be present
  underneath /, rather than /soc.

properties:
  compatible:
    const: sifive,fu540-c000-prci

  reg:
    maxItems: 1

  clocks:
    items:
      - description: high frequency clock.
      - description: RTL clock.

  clock-names:
    items:
      - const: hfclk
      - const: rtcclk

  "#clock-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - "#clock-cells"

additionalProperties: false

examples:
  - |
    prci: clock-controller@10000000 {
      compatible = "sifive,fu540-c000-prci";
      reg = <0x10000000 0x1000>;
      clocks = <&hfclk>, <&rtcclk>;
      #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sifive/fu740-prci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive FU740 Power Reset Clock Interrupt Controller (PRCI)

maintainers:
  - Zong Li <zong.li@sifive.com>
  - Paul Walmsley  <paul.walmsley@sifive.com>

description:
  On the FU740 family of SoCs, most system-wide clock and reset integration
  is via the PRCI IP block.
  The clock consumer should specify the desired clock via the clock ID
  macros defined in include/dt-bindings/clock/sifive-fu740-prci.h.
  These macros begin with PRCI_CLK_.

  The hfclk and rtcclk nodes are required, and represent physical
  crystals or resonators located on the PCB.  These nodes should be present
  underneath /, rather than /soc.

properties:
  compatible:
    const: sifive,fu740-c000-prci

  reg:
    maxItems: 1

  clocks:
    items:
      - description: high frequency clock.
      - description: RTL clock.

  clock-names:
    items:
      - const: hfclk
      - const: rtcclk

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - "#clock-cells"

additionalProperties: false

examples:
  - |
    prci: clock-controller@10000000 {
      compatible = "sifive,fu740-c000-prci";
      reg = <0x10000000 0x1000>;
      clocks = <&hfclk>, <&rtcclk>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
Binding for Silicon Labs 514 programmable I2C clock generator.

Reference
This binding uses the common clock binding[1]. Details about the device can be
found in the datasheet[2].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Si514 datasheet
    https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf

Required properties:
 - compatible: Shall be "silabs,si514"
 - reg: I2C device address.
 - #clock-cells: From common clock bindings: Shall be 0.

Optional properties:
 - clock-output-names: From common clock bindings. Recommended to be "si514".

Example:
	si514: clock-generator@55 {
		reg = <0x55>;
		#clock-cells = <0>;
		compatible = "silabs,si514";
	};


code:
Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable
i2c clock generator.

Reference
[1] Si5341 Data Sheet
    https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
[2] Si5341 Reference Manual
    https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
[3] Si5345 Reference Manual
    https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf

The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
in turn can be directed to any of the 10 (or 4) outputs through a divider.
The internal structure of the clock generators can be found in [2].
The Si5345 is similar to the Si5341 with the addition of fractional input
dividers and automatic input selection, as described in [3].
The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.

The driver can be used in "as is" mode, reading the current settings from the
chip at boot, in case you have a (pre-)programmed device. If the PLL is not
configured when the driver probes, it assumes the driver must fully initialize
it.

The device type, speed grade and revision are determined runtime by probing.

The driver currently does not support any fancy input configurations. They can
still be programmed into the chip and the driver will leave them "as is".

==I2C device node==

Required properties:
- compatible: shall be one of the following:
	"silabs,si5340" - Si5340 A/B/C/D
	"silabs,si5341" - Si5341 A/B/C/D
	"silabs,si5342" - Si5342 A/B/C/D
	"silabs,si5344" - Si5344 A/B/C/D
	"silabs,si5345" - Si5345 A/B/C/D
- reg: i2c device address, usually 0x74
- #clock-cells: from common clock binding; shall be set to 2.
	The first value is "0" for outputs, "1" for synthesizers.
	The second value is the output or synthesizer index.
- clocks: from common clock binding; list of parent clock  handles,
	corresponding to inputs. Use a fixed clock for the "xtal" input.
	At least one must be present.
- clock-names: One of: "xtal", "in0", "in1", "in2"

Optional properties:
- vdd-supply: Regulator node for VDD
- vdda-supply: Regulator node for VDDA
- vdds-supply: Regulator node for VDDS
- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
  feedback divider. Must be such that the PLL output is in the valid range. For
  example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
  the fraction matters, using 3500 and 12 will deliver the exact same result.
  If these are not specified, and the PLL is not yet programmed when the driver
  probes, the PLL will be set to 14GHz.
- silabs,reprogram: When present, the driver will always assume the device must
  be initialized, and always performs the soft-reset routine. Since this will
  temporarily stop all output clocks, don't do this if the chip is generating
  the CPU clock for example.
- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
  in EXTCLK (external reference clock) rather than XTAL (crystal) mode.
- interrupts: Interrupt for INTRb pin.
- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V
  rather than 1.8V thresholds.
- vddoX-supply (where X is an output index): Regulator node for VDDO for the
  specified output. The driver selects the output VDD_SEL setting based on this
  voltage.
- #address-cells: shall be set to 1.
- #size-cells: shall be set to 0.

== Child nodes: Outputs ==

The child nodes list the output clocks.

Each of the clock outputs can be overwritten individually by using a child node.
If a child node for a clock output is not set, the configuration remains
unchanged.

Required child node properties:
- reg: number of clock output.

Optional child node properties:
- silabs,format: Output format, one of:
	1 = differential (defaults to LVDS levels)
	2 = low-power (defaults to HCSL levels)
	4 = LVCMOS
- silabs,common-mode: Manually override output common mode, see [2] for values
- silabs,amplitude: Manually override output amplitude, see [2] for values
- silabs,synth-master: boolean. If present, this output is allowed to change the
	multisynth frequency dynamically.
- silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
	when disabled, otherwise it's driven LOW.

==Example==

/* 48MHz reference crystal */
ref48: ref48M {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <48000000>;
};

i2c-master-node {
	/* Programmable clock (for logic) */
	si5341: clock-generator@74 {
		reg = <0x74>;
		compatible = "silabs,si5341";
		#clock-cells = <2>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&ref48>;
		clock-names = "xtal";

		silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
		silabs,pll-m-den = <48>;
		silabs,reprogram; /* Chips are not programmed, always reset */

		out@0 {
			reg = <0>;
			silabs,format = <1>; /* LVDS 3v3 */
			silabs,common-mode = <3>;
			silabs,amplitude = <3>;
			silabs,synth-master;
		};

		/*
		 * Output 6 configuration:
		 *  LVDS 1v8
		 */
		out@6 {
			reg = <6>;
			silabs,format = <1>; /* LVDS 1v8 */
			silabs,common-mode = <13>;
			silabs,amplitude = <3>;
		};

		/*
		 * Output 8 configuration:
		 *  HCSL 3v3
		 */
		out@8 {
			reg = <8>;
			silabs,format = <2>;
			silabs,common-mode = <11>;
			silabs,amplitude = <3>;
		};
	};
};

some-video-node {
	/* Standard clock bindings */
	clock-names = "pixel";
	clocks = <&si5341 0 7>; /* Output 7 */

	/* Set output 7 to use syntesizer 3 as its parent */
	assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
	assigned-clock-parents = <&si5341 1 3>;
	/* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
	assigned-clock-rates = <148500000>, <594000000>;
};

some-audio-node {
	clock-names = "i2s-clk";
	clocks = <&si5341 0 0>;
	/*
	 * since output 0 is a synth-master, the synth will be automatically set
	 * to an appropriate frequency when the audio driver requests another
	 * frequency. We give control over synth 2 to this output here.
	 */
	assigned-clocks = <&si5341 0 0>;
	assigned-clock-parents = <&si5341 1 2>;
};


code:
Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.

Reference
[1] Si5351A/B/C Data Sheet
    https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf

The Si5351a/b/c are programmable i2c clock generators with up to 8 output
clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
3 output clocks are accessible. The internal structure of the clock
generators can be found in [1].

==I2C device node==

Required properties:
- compatible: shall be one of the following:
	"silabs,si5351a" - Si5351a, QFN20 package
	"silabs,si5351a-msop" - Si5351a, MSOP10 package
	"silabs,si5351b" - Si5351b, QFN20 package
	"silabs,si5351c" - Si5351c, QFN20 package
- reg: i2c device address, shall be 0x60 or 0x61.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock
  handles, shall be xtal reference clock or xtal and clkin for
  si5351c only. Corresponding clock input names are "xtal" and
  "clkin" respectively.
- #address-cells: shall be set to 1.
- #size-cells: shall be set to 0.

Optional properties:
- silabs,pll-source: pair of (number, source) for each pll. Allows
  to overwrite clock source of pll A (number=0) or B (number=1).

==Child nodes==

Each of the clock outputs can be overwritten individually by
using a child node to the I2C device node. If a child node for a clock
output is not set, the eeprom configuration is not overwritten.

Required child node properties:
- reg: number of clock output.

Optional child node properties:
- silabs,clock-source: source clock of the output divider stage N, shall be
  0 = multisynth N
  1 = multisynth 0 for output clocks 0-3, else multisynth4
  2 = xtal
  3 = clkin (si5351c only)
- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
  divider.
- silabs,pll-master: boolean, multisynth can change pll frequency.
- silabs,pll-reset: boolean, clock output can reset its pll.
- silabs,disable-state : clock output disable state, shall be
  0 = clock output is driven LOW when disabled
  1 = clock output is driven HIGH when disabled
  2 = clock output is FLOATING (HIGH-Z) when disabled
  3 = clock output is NEVER disabled

==Example==

/* 25MHz reference crystal */
ref25: ref25M {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <25000000>;
};

i2c-master-node {

	/* Si5351a msop10 i2c clock generator */
	si5351a: clock-generator@60 {
		compatible = "silabs,si5351a-msop";
		reg = <0x60>;
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;

		/* connect xtal input to 25MHz reference */
		clocks = <&ref25>;
		clock-names = "xtal";

		/* connect xtal input as source of pll0 and pll1 */
		silabs,pll-source = <0 0>, <1 0>;

		/*
		 * overwrite clkout0 configuration with:
		 * - 8mA output drive strength
		 * - pll0 as clock source of multisynth0
		 * - multisynth0 as clock source of output divider
		 * - multisynth0 can change pll0
		 * - set initial clock frequency of 74.25MHz
		 */
		clkout0 {
			reg = <0>;
			silabs,drive-strength = <8>;
			silabs,multisynth-source = <0>;
			silabs,clock-source = <0>;
			silabs,pll-master;
			clock-frequency = <74250000>;
		};

		/*
		 * overwrite clkout1 configuration with:
		 * - 4mA output drive strength
		 * - pll1 as clock source of multisynth1
		 * - multisynth1 as clock source of output divider
		 * - multisynth1 can change pll1
		 */
		clkout1 {
			reg = <1>;
			silabs,drive-strength = <4>;
			silabs,multisynth-source = <1>;
			silabs,clock-source = <0>;
			pll-master;
		};

		/*
		 * overwrite clkout2 configuration with:
		 * - xtal as clock source of output divider
		 */
		clkout2 {
			reg = <2>;
			silabs,clock-source = <2>;
		};
	};
};


code:
Binding for Silicon Labs 544 programmable I2C clock generator.

Reference
This binding uses the common clock binding[1]. Details about the device can be
found in the datasheet[2].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Si544 datasheet
    https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf

Required properties:
 - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
               to the speed grade of the chip.
 - reg: I2C device address.
 - #clock-cells: From common clock bindings: Shall be 0.

Optional properties:
 - clock-output-names: From common clock bindings. Recommended to be "si544".

Example:
	si544: clock-controller@55 {
		reg = <0x55>;
		#clock-cells = <0>;
		compatible = "silabs,si544b";
	};


code:
Binding for Silicon Labs 570, 571, 598 and 599 programmable
I2C clock generators.

Reference
This binding uses the common clock binding[1]. Details about the devices can be
found in the data sheets[2][3].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Si570/571 Data Sheet
    https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf
[3] Si598/599 Data Sheet
    https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf

Required properties:
 - compatible: Shall be one of "silabs,si570", "silabs,si571",
			       "silabs,si598", "silabs,si599"
 - reg: I2C device address.
 - #clock-cells: From common clock bindings: Shall be 0.
 - factory-fout: Factory set default frequency. This frequency is part specific.
		 The correct frequency for the part used has to be provided in
		 order to generate the correct output frequencies. For more
		 details, please refer to the data sheet.
 - temperature-stability: Temperature stability of the device in PPM. Should be
			  one of: 7, 20, 50 or 100.

Optional properties:
 - clock-output-names: From common clock bindings. Recommended to be "si570".
 - clock-frequency: Output frequency to generate. This defines the output
		    frequency set during boot. It can be reprogrammed during
		    runtime through the common clock framework.
 - silabs,skip-recall: Do not perform NVM->RAM recall operation. It will rely
		       on hardware loading of RAM from NVM at power on.

Example:
	si570: clock-generator@5d {
		#clock-cells = <0>;
		compatible = "silabs,si570";
		temperature-stability = <50>;
		reg = <0x5d>;
		factory-fout = <156250000>;
	};


code:
Binding for the HSDK Generic PLL clock

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible: should be "snps,hsdk-<name>-pll-clock"
  "snps,hsdk-core-pll-clock"
  "snps,hsdk-gp-pll-clock"
  "snps,hsdk-hdmi-pll-clock"
- reg : should contain base register location and length.
- clocks: shall be the input parent clock phandle for the PLL.
- #clock-cells: from common clock binding; Should always be set to 0.

Example:
	input_clk: input-clk {
		clock-frequency = <33333333>;
		compatible = "fixed-clock";
		#clock-cells = <0>;
	};

	cpu_clk: cpu-clk@0 {
		compatible = "snps,hsdk-core-pll-clock";
		reg = <0x00 0x10>;
		#clock-cells = <0>;
		clocks = <&input_clk>;
	};


code:
Binding for the AXS10X Generic PLL clock

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible: should be "snps,axs10x-<name>-pll-clock"
  "snps,axs10x-arc-pll-clock"
  "snps,axs10x-pgu-pll-clock"
- reg: should always contain 2 pairs address - length: first for PLL config
registers and second for corresponding LOCK CGU register.
- clocks: shall be the input parent clock phandle for the PLL.
- #clock-cells: from common clock binding; Should always be set to 0.

Example:
	input-clk: input-clk {
		clock-frequency = <33333333>;
		compatible = "fixed-clock";
		#clock-cells = <0>;
	};

	core-clk: core-clk@80 {
		compatible = "snps,axs10x-arc-pll-clock";
		reg = <0x80 0x10>, <0x100 0x10>;
		#clock-cells = <0>;
		clocks = <&input-clk>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/socionext,uniphier-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UniPhier clock controller

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

properties:
  compatible:
    oneOf:
      - description: System clock
        enum:
          - socionext,uniphier-ld4-clock
          - socionext,uniphier-pro4-clock
          - socionext,uniphier-sld8-clock
          - socionext,uniphier-pro5-clock
          - socionext,uniphier-pxs2-clock
          - socionext,uniphier-ld6b-clock
          - socionext,uniphier-ld11-clock
          - socionext,uniphier-ld20-clock
          - socionext,uniphier-pxs3-clock
          - socionext,uniphier-nx1-clock
      - description: Media I/O (MIO) clock, SD clock
        enum:
          - socionext,uniphier-ld4-mio-clock
          - socionext,uniphier-pro4-mio-clock
          - socionext,uniphier-sld8-mio-clock
          - socionext,uniphier-pro5-sd-clock
          - socionext,uniphier-pxs2-sd-clock
          - socionext,uniphier-ld11-mio-clock
          - socionext,uniphier-ld20-sd-clock
          - socionext,uniphier-pxs3-sd-clock
          - socionext,uniphier-nx1-sd-clock
      - description: Peripheral clock
        enum:
          - socionext,uniphier-ld4-peri-clock
          - socionext,uniphier-pro4-peri-clock
          - socionext,uniphier-sld8-peri-clock
          - socionext,uniphier-pro5-peri-clock
          - socionext,uniphier-pxs2-peri-clock
          - socionext,uniphier-ld11-peri-clock
          - socionext,uniphier-ld20-peri-clock
          - socionext,uniphier-pxs3-peri-clock
          - socionext,uniphier-nx1-peri-clock
      - description: SoC-glue clock
        enum:
          - socionext,uniphier-pro4-sg-clock

  "#clock-cells":
    const: 1

additionalProperties: false

required:
  - compatible
  - "#clock-cells"

examples:
  - |
    sysctrl@61840000 {
        compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon";
        reg = <0x61840000 0x4000>;

        clock {
            compatible = "socionext,uniphier-ld11-clock";
            #clock-cells = <1>;
        };

        // other nodes ...
    };

  - |
    mioctrl@59810000 {
        compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon";
        reg = <0x59810000 0x800>;

        clock {
            compatible = "socionext,uniphier-ld11-mio-clock";
            #clock-cells = <1>;
        };

        // other nodes ...
    };

  - |
    perictrl@59820000 {
        compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon";
        reg = <0x59820000 0x200>;

        clock {
            compatible = "socionext,uniphier-ld11-peri-clock";
            #clock-cells = <1>;
        };

        // other nodes ...
    };


code:
Spreadtrum SC9860 Clock Binding
------------------------

Required properties:
- compatible: should contain the following compatible strings:
	- "sprd,sc9860-pmu-gate"
	- "sprd,sc9860-pll"
	- "sprd,sc9860-ap-clk"
	- "sprd,sc9860-aon-prediv"
	- "sprd,sc9860-apahb-gate"
	- "sprd,sc9860-aon-gate"
	- "sprd,sc9860-aonsecure-clk"
	- "sprd,sc9860-agcp-gate"
	- "sprd,sc9860-gpu-clk"
	- "sprd,sc9860-vsp-clk"
	- "sprd,sc9860-vsp-gate"
	- "sprd,sc9860-cam-clk"
	- "sprd,sc9860-cam-gate"
	- "sprd,sc9860-disp-clk"
	- "sprd,sc9860-disp-gate"
	- "sprd,sc9860-apapb-gate"

- #clock-cells: must be 1

- clocks : Should be the input parent clock(s) phandle for the clock, this
	   property here just simply shows which clock group the clocks'
	   parents are in, since each clk node would represent many clocks
	   which are defined in the driver.  The detailed dependency
	   relationship (i.e. how many parents and which are the parents)
	   are implemented in driver code.

Optional properties:

- reg:	Contain the registers base address and length. It must be configured
	only if no 'sprd,syscon' under the node.

- sprd,syscon: phandle to the syscon which is in the same address area with
	       the clock, and so we can get regmap for the clocks from the
	       syscon device.

Example:

	pmu_gate: pmu-gate {
		compatible = "sprd,sc9860-pmu-gate";
		sprd,syscon = <&pmu_regs>;
		clocks = <&ext_26m>;
		#clock-cells = <1>;
	};

	pll: pll {
		compatible = "sprd,sc9860-pll";
		sprd,syscon = <&ana_regs>;
		clocks = <&pmu_gate 0>;
		#clock-cells = <1>;
	};

	ap_clk: clock-controller@20000000 {
		compatible = "sprd,sc9860-ap-clk";
		reg = <0 0x20000000 0 0x400>;
		clocks = <&ext_26m>, <&pll 0>,
			 <&pmu_gate 0>;
		#clock-cells = <1>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2019 Unisoc Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: SC9863A Clock Control Unit

maintainers:
  - Orson Zhai <orsonzhai@gmail.com>
  - Baolin Wang <baolin.wang7@gmail.com>
  - Chunyan Zhang <zhang.lyra@gmail.com>

properties:
  "#clock-cells":
    const: 1

  compatible:
    enum:
      - sprd,sc9863a-ap-clk
      - sprd,sc9863a-aon-clk
      - sprd,sc9863a-apahb-gate
      - sprd,sc9863a-pmu-gate
      - sprd,sc9863a-aonapb-gate
      - sprd,sc9863a-pll
      - sprd,sc9863a-mpll
      - sprd,sc9863a-rpll
      - sprd,sc9863a-dpll
      - sprd,sc9863a-mm-gate
      - sprd,sc9863a-mm-clk
      - sprd,sc9863a-apapb-gate

  clocks:
    minItems: 1
    maxItems: 4
    description: |
      The input parent clock(s) phandle for this clock, only list fixed
      clocks which are declared in devicetree.

  clock-names:
    minItems: 1
    items:
      - const: ext-26m
      - const: ext-32k
      - const: ext-4m
      - const: rco-100m

  reg:
    maxItems: 1

required:
  - compatible
  - '#clock-cells'

if:
  properties:
    compatible:
      enum:
        - sprd,sc9863a-ap-clk
        - sprd,sc9863a-aon-clk
then:
  required:
    - reg

else:
  description: |
    Other SC9863a clock nodes should be the child of a syscon node in
    which compatible string shoule be:
            "sprd,sc9863a-glbregs", "syscon", "simple-mfd"

    The 'reg' property for the clock node is also required if there is a sub
    range of registers for the clocks.

additionalProperties: false

examples:
  - |
    ap_clk: clock-controller@21500000 {
      compatible = "sprd,sc9863a-ap-clk";
      reg = <0x21500000 0x1000>;
      clocks = <&ext_26m>, <&ext_32k>;
      clock-names = "ext-26m", "ext-32k";
      #clock-cells = <1>;
    };

  - |
    syscon@20e00000 {
      compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd";
      reg = <0x20e00000 0x4000>;
      #address-cells = <1>;
      #size-cells = <1>;
      ranges = <0 0x20e00000 0x4000>;

      apahb_gate: apahb-gate@0 {
        compatible = "sprd,sc9863a-apahb-gate";
        reg = <0x0 0x1020>;
        #clock-cells = <1>;
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2022 Unisoc Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: UMS512 Soc clock controller

maintainers:
  - Orson Zhai <orsonzhai@gmail.com>
  - Baolin Wang <baolin.wang7@gmail.com>
  - Chunyan Zhang <zhang.lyra@gmail.com>

properties:
  compatible:
    enum:
      - sprd,ums512-apahb-gate
      - sprd,ums512-ap-clk
      - sprd,ums512-aonapb-clk
      - sprd,ums512-pmu-gate
      - sprd,ums512-g0-pll
      - sprd,ums512-g2-pll
      - sprd,ums512-g3-pll
      - sprd,ums512-gc-pll
      - sprd,ums512-aon-gate
      - sprd,ums512-audcpapb-gate
      - sprd,ums512-audcpahb-gate
      - sprd,ums512-gpu-clk
      - sprd,ums512-mm-clk
      - sprd,ums512-mm-gate-clk
      - sprd,ums512-apapb-gate

  "#clock-cells":
    const: 1

  clocks:
    minItems: 1
    maxItems: 4
    description: |
      The input parent clock(s) phandle for the clock, only list
      fixed clocks which are declared in devicetree.

  clock-names:
    minItems: 1
    items:
      - const: ext-26m
      - const: ext-32k
      - const: ext-4m
      - const: rco-100m

  reg:
    maxItems: 1

required:
  - compatible
  - '#clock-cells'
  - reg

additionalProperties: false

examples:
  - |
    ap_clk: clock-controller@20200000 {
      compatible = "sprd,ums512-ap-clk";
      reg = <0x20200000 0x1000>;
      clocks = <&ext_26m>;
      clock-names = "ext-26m";
      #clock-cells = <1>;
    };
...


code:
ST Microelectronics Nomadik SRC System Reset and Control

This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt

The Nomadik SRC controller is responsible of controlling chrystals,
PLLs and clock gates.

Required properties for the SRC node:
- compatible: must be "stericsson,nomadik-src"
- reg: must contain the SRC register base and size

Optional properties for the SRC node:
- disable-sxtalo: if present this will disable the SXTALO
  i.e. the driver output for the slow 32kHz chrystal, if the
  board has its own circuitry for providing this oscillator
- disable-mxtal: if present this will disable the MXTALO,
  i.e. the driver output for the main (~19.2 MHz) chrystal,
  if the board has its own circuitry for providing this
  oscillator

PLL nodes: these nodes represent the two PLLs on the system,
which should both have the main chrystal, represented as a
fixed frequency clock, as parent.

Required properties for the two PLL nodes:
- compatible: must be "st,nomadik-pll-clock"
- clock-cells: must be 0
- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
- clocks: this clock will have main chrystal as parent

HCLK nodes: these represent the clock gates on individual
lines from the HCLK clock tree and the gate for individual
lines from the PCLK clock tree.

Requires properties for the HCLK nodes:
- compatible: must be "st,nomadik-hclk-clock"
- clock-cells: must be 0
- clock-id: must be the clock ID from 0 to 63 according to
  this table:

	0:  HCLKDMA0
	1:  HCLKSMC
	2:  HCLKSDRAM
	3:  HCLKDMA1
	4:  HCLKCLCD
	5:  PCLKIRDA
	6:  PCLKSSP
	7:  PCLKUART0
	8:  PCLKSDI
	9:  PCLKI2C0
	10: PCLKI2C1
	11: PCLKUART1
	12: PCLMSP0
	13: HCLKUSB
	14: HCLKDIF
	15: HCLKSAA
	16: HCLKSVA
	17: PCLKHSI
	18: PCLKXTI
	19: PCLKUART2
	20: PCLKMSP1
	21: PCLKMSP2
	22: PCLKOWM
	23: HCLKHPI
	24: PCLKSKE
	25: PCLKHSEM
	26: HCLK3D
	27: HCLKHASH
	28: HCLKCRYP
	29: PCLKMSHC
	30: HCLKUSBM
	31: HCLKRNG
	(32, 33, 34, 35 RESERVED)
	36: CLDCLK
	37: IRDACLK
	38: SSPICLK
	39: UART0CLK
	40: SDICLK
	41: I2C0CLK
	42: I2C1CLK
	43: UART1CLK
	44: MSPCLK0
	45: USBCLK
	46: DIFCLK
	47: IPI2CCLK
	48: IPBMCCLK
	49: HSICLKRX
	50: HSICLKTX
	51: UART2CLK
	52: MSPCLK1
	53: MSPCLK2
	54: OWMCLK
	(55 RESERVED)
	56: SKECLK
	(57 RESERVED)
	58: 3DCLK
	59: PCLKMSP3
	60: MSPCLK3
	61: MSHCCLK
	62: USBMCLK
	63: RNGCCLK


code:
STMicroelectronics STM32 Reset and Clock Controller
===================================================

The RCC IP is both a reset and a clock controller.

Please refer to clock-bindings.txt for common clock controller binding usage.
Please also refer to reset.txt for common reset controller binding usage.

Required properties:
- compatible: Should be:
  "st,stm32f42xx-rcc"
  "st,stm32f469-rcc"
  "st,stm32f746-rcc"
  "st,stm32f769-rcc"

- reg: should be register base and length as documented in the
  datasheet
- #reset-cells: 1, see below
- #clock-cells: 2, device nodes should specify the clock in their "clocks"
  property, containing a phandle to the clock device node, an index selecting
  between gated clocks and other clocks and an index specifying the clock to
  use.
- clocks: External oscillator clock phandle
  - high speed external clock signal (HSE)
  - external I2S clock (I2S_CKIN)

Example:

	rcc: rcc@40023800 {
		#reset-cells = <1>;
		#clock-cells = <2>
		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
		reg = <0x40023800 0x400>;
		clocks = <&clk_hse>, <&clk_i2s_ckin>;
	};

Specifying gated clocks
=======================

The primary index must be set to 0.

The secondary index is the bit number within the RCC register bank, starting
from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).

It is calculated as: index = register_offset / 4 * 32 + bit_offset.
Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).

To simplify the usage and to share bit definition with the reset and clock
drivers of the RCC IP, macros are available to generate the index in
human-readble format.

For STM32F4 series, the macro are available here:
 - include/dt-bindings/mfd/stm32f4-rcc.h

Example:

	/* Gated clock, AHB1 bit 0 (GPIOA) */
	... {
		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
	};

	/* Gated clock, AHB2 bit 4 (CRYP) */
	... {
		clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
	};

Specifying other clocks
=======================

The primary index must be set to 1.

The secondary index is bound with the following magic numbers:

	0	SYSTICK
	1	FCLK
	2	CLK_LSI		(low-power clock source)
	3	CLK_LSE		(generated from a 32.768 kHz low-speed external
				 crystal or ceramic resonator)
	4	CLK_HSE_RTC	(HSE division factor for RTC clock)
	5	CLK_RTC		(real-time clock)
	6	PLL_VCO_I2S	(vco frequency of I2S pll)
	7	PLL_VCO_SAI	(vco frequency of SAI pll)
	8	CLK_LCD		(LCD-TFT)
	9	CLK_I2S		(I2S clocks)
	10	CLK_SAI1	(audio clocks)
	11	CLK_SAI2
	12	CLK_I2SQ_PDIV	(post divisor of pll i2s q divisor)
	13	CLK_SAIQ_PDIV	(post divisor of pll sai q divisor)

	14	CLK_HSI		(Internal ocscillator clock)
	15	CLK_SYSCLK	(System Clock)
	16	CLK_HDMI_CEC	(HDMI-CEC clock)
	17	CLK_SPDIF	(SPDIF-Rx clock)
	18	CLK_USART1	(U(s)arts clocks)
	19	CLK_USART2
	20	CLK_USART3
	21	CLK_UART4
	22	CLK_UART5
	23	CLK_USART6
	24	CLK_UART7
	25	CLK_UART8
	26	CLK_I2C1	(I2S clocks)
	27	CLK_I2C2
	28	CLK_I2C3
	29	CLK_I2C4
	30	CLK_LPTIMER	(LPTimer1 clock)
	31	CLK_PLL_SRC
	32	CLK_DFSDM1
	33	CLK_ADFSDM1
	34	CLK_F769_DSI
)

Example:

	/* Misc clock, FCLK */
	... {
		clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
	};

Specifying softreset control of devices
=======================================

Device nodes should specify the reset channel required in their "resets"
property, containing a phandle to the reset device node and an index specifying
which channel to use.
The index is the bit number within the RCC registers bank, starting from RCC
base address.
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
Where bit_offset is the bit offset within the register.
For example, for CRC reset:
  crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140

example:

	timer2 {
		resets	= <&rcc STM32F4_APB1_RESET(TIM2)>;
	};


code:
STMicroelectronics STM32H7 Reset and Clock Controller
=====================================================

The RCC IP is both a reset and a clock controller.

Please refer to clock-bindings.txt for common clock controller binding usage.
Please also refer to reset.txt for common reset controller binding usage.

Required properties:
- compatible: Should be:
  "st,stm32h743-rcc"

- reg: should be register base and length as documented in the
  datasheet

- #reset-cells: 1, see below

- #clock-cells : from common clock binding; shall be set to 1

- clocks: External oscillator clock phandle
  - high speed external clock signal (HSE)
  - low speed external clock signal (LSE)
  - external I2S clock (I2S_CKIN)

Optional properties:
- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
  write protection (RTC clock).

Example:

	rcc: reset-clock-controller@58024400 {
		compatible = "st,stm32h743-rcc", "st,stm32-rcc";
		reg = <0x58024400 0x400>;
		#reset-cells = <1>;
		#clock-cells = <1>;
		clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;

		st,syscfg = <&pwrcfg>;
};

The peripheral clock consumer should specify the desired clock by
having the clock ID in its "clocks" phandle cell.

Example:

		timer5: timer@40000c00 {
			compatible = "st,stm32-timer";
			reg = <0x40000c00 0x400>;
			interrupts = <50>;
			clocks = <&rcc TIM5_CK>;
		};

Specifying softreset control of devices
=======================================

Device nodes should specify the reset channel required in their "resets"
property, containing a phandle to the reset device node and an index specifying
which channel to use.
The index is the bit number within the RCC registers bank, starting from RCC
base address.
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
Where bit_offset is the bit offset within the register.

For example, for CRC reset:
  crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107

Example:

	timer2 {
		resets	= <&rcc STM32H7_APB1L_RESET(TIM2)>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Reset Clock Controller Binding

maintainers:
  - Gabriel Fernandez <gabriel.fernandez@foss.st.com>

description: |
  The RCC IP is both a reset and a clock controller.
  RCC makes also power management (resume/supend and wakeup interrupt).
  Please also refer to reset.txt for common reset controller binding usage.

  This binding uses common clock bindings
  Documentation/devicetree/bindings/clock/clock-bindings.txt

  Specifying clocks
  =================

  All available clocks are defined as preprocessor macros in
  dt-bindings/clock/stm32mp1-clks.h header and can be used in device
  tree sources.

  Specifying softreset control of devices
  =======================================

  Device nodes should specify the reset channel required in their "resets"
  property, containing a phandle to the reset device node and an index specifying
  which channel to use.
  The index is the bit number within the RCC registers bank, starting from RCC
  base address.
  It is calculated as: index = register_offset / 4 * 32 + bit_offset.
  Where bit_offset is the bit offset within the register.

  For example on STM32MP1, for LTDC reset:
     ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
          = 0x180 / 4 * 32 + 0 = 3072

  The list of valid indices for STM32MP1 is available in:
  include/dt-bindings/reset-controller/stm32mp1-resets.h
  include/dt-bindings/reset-controller/stm32mp13-resets.h

  This file implements defines like:
  #define LTDC_R	3072

properties:
  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  compatible:
    items:
      - enum:
          - st,stm32mp1-rcc-secure
          - st,stm32mp1-rcc
          - st,stm32mp13-rcc
      - const: syscon
  clocks: true
  clock-names: true

  reg:
    maxItems: 1

required:
  - "#clock-cells"
  - "#reset-cells"
  - compatible
  - reg

if:
  properties:
    compatible:
      contains:
        enum:
          - st,stm32mp1-rcc-secure
          - st,stm32mp13-rcc
then:
  properties:
    clocks:
      description: Specifies oscillators.
      maxItems: 5

    clock-names:
      items:
        - const: hse
        - const: hsi
        - const: csi
        - const: lse
        - const: lsi
  required:
    - clocks
    - clock-names
else:
  properties:
    clocks:
      description:
        Specifies the external RX clock for ethernet MAC.
      maxItems: 1

    clock-names:
      const: ETH_RX_CLK/ETH_REF_CLK

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/stm32mp1-clks.h>
    rcc: rcc@50000000 {
        compatible = "st,stm32mp1-rcc-secure", "syscon";
        reg = <0x50000000 0x1000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        clock-names = "hse", "hsi", "csi", "lse", "lsi";
        clocks = <&scmi_clk CK_SCMI_HSE>,
                 <&scmi_clk CK_SCMI_HSI>,
                 <&scmi_clk CK_SCMI_CSI>,
                 <&scmi_clk CK_SCMI_LSE>,
                 <&scmi_clk CK_SCMI_LSI>;
    };
...


code:
Binding for a ST multiplexed clock driver.

This binding supports only simple indexed multiplexers, it does not
support table based parent index to hardware value translations.

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:

- compatible : shall be:
	"st,stih407-clkgen-a9-mux"

- #clock-cells : from common clock binding; shall be set to 0.

- reg : A Base address and length of the register set.

- clocks : from common clock binding

Example:

	clk_m_a9: clk-m-a9@92b0000 {
		#clock-cells = <0>;
		compatible = "st,stih407-clkgen-a9-mux";
		reg = <0x92b0000 0x10000>;

		clocks = <&clockgen_a9_pll 0>,
			 <&clockgen_a9_pll 0>,
			 <&clk_s_c0_flexgen 13>,
			 <&clk_m_a9_ext2f_div2>;
	};


code:
Binding for a ST pll clock driver.

This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt

Required properties:

- compatible : shall be:
	"st,clkgen-pll0"
	"st,clkgen-pll0-a0"
	"st,clkgen-pll0-c0"
	"st,clkgen-pll1"
	"st,clkgen-pll1-c0"
	"st,stih407-clkgen-plla9"
	"st,stih418-clkgen-plla9"

- #clock-cells : From common clock binding; shall be set to 1.

- clocks : From common clock binding

- clock-output-names : From common clock binding.

Example:

	clockgen-a9@92b0000 {
		compatible = "st,clkgen-c32";
		reg = <0x92b0000 0xffff>;

		clockgen_a9_pll: clockgen-a9-pll {
			#clock-cells = <1>;
			compatible = "st,stih407-clkgen-plla9";

			clocks = <&clk_sysin>;

			clock-output-names = "clockgen-a9-pll-odf";
		};
	};


code:
Binding for a Clockgen hardware block found on
certain STMicroelectronics consumer electronics SoC devices.

A Clockgen node can contain pll, diviser or multiplexer nodes.

We will find only the base address of the Clockgen, this base
address is common of all subnode.

	clockgen_node {
		reg = <>;

		pll_node {
			...
		};

		quadfs_node {
			...
		};

		mux_node {
			...
		};

		flexgen_node {
			...
		};
		...
	};

This binding uses the common clock binding[1].
Each subnode should use the binding described in [2]..[7]

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
[4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
[7] Documentation/devicetree/bindings/clock/st/st,quadfs.txt
[8] Documentation/devicetree/bindings/clock/st/st,flexgen.txt

Required properties:
- reg : A Base address and length of the register set.

Example:

	clockgen-a@90ff000 {
		compatible = "st,clkgen-c32";
		reg = <0x90ff000 0x1000>;

		clk_s_a0_pll: clk-s-a0-pll {
			#clock-cells = <1>;
			compatible = "st,clkgen-pll0";

			clocks = <&clk_sysin>;

			clock-output-names = "clk-s-a0-pll-ofd-0";
		};

		clk_s_a0_flexgen: clk-s-a0-flexgen {
			compatible = "st,flexgen";

			#clock-cells = <1>;

			clocks = <&clk_s_a0_pll 0>,
				 <&clk_sysin>;

			clock-output-names = "clk-ic-lmi0";
		};
	};


code:
Binding for a type of quad channel digital frequency synthesizer found on
certain STMicroelectronics consumer electronics SoC devices.

This version contains a programmable PLL which can generate up to 216, 432
or 660MHz (from a 30MHz oscillator input) as the input to the digital
synthesizers.

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be:
  "st,quadfs"
  "st,quadfs-d0"
  "st,quadfs-d2"
  "st,quadfs-d3"
  "st,quadfs-pll"

- #clock-cells : from common clock binding; shall be set to 1.

- reg : A Base address and length of the register set.

- clocks : from common clock binding

- clock-output-names : From common clock binding. The block has 4
                       clock outputs but not all of them in a specific instance
                       have to be used in the SoC. If a clock name is left as
                       an empty string then no clock will be created for the
                       output associated with that string index. If fewer than
                       4 strings are provided then no clocks will be created
                       for the remaining outputs.

Example:

	clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
		#clock-cells = <1>;
		compatible = "st,quadfs-pll";
		reg = <0x9103000 0x1000>;

		clocks = <&clk_sysin>;

		clock-output-names = "clk-s-c0-fs0-ch0",
				     "clk-s-c0-fs0-ch1",
				     "clk-s-c0-fs0-ch2",
				     "clk-s-c0-fs0-ch3";
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7100 Audio Clock Generator

maintainers:
  - Emil Renner Berthing <kernel@esmil.dk>

properties:
  compatible:
    const: starfive,jh7100-audclk

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Audio source clock
      - description: External 12.288MHz clock
      - description: Domain 7 AHB bus clock

  clock-names:
    items:
      - const: audio_src
      - const: audio_12288
      - const: dom7ahb_bus

  '#clock-cells':
    const: 1
    description:
      See <dt-bindings/clock/starfive-jh7100-audio.h> for valid indices.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/starfive-jh7100.h>

    clock-controller@10480000 {
            compatible = "starfive,jh7100-audclk";
            reg = <0x10480000 0x10000>;
            clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
                     <&clkgen JH7100_CLK_AUDIO_12288>,
                     <&clkgen JH7100_CLK_DOM7AHB_BUS>;
            clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
            #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7100 Clock Generator

maintainers:
  - Geert Uytterhoeven <geert@linux-m68k.org>
  - Emil Renner Berthing <kernel@esmil.dk>

properties:
  compatible:
    const: starfive,jh7100-clkgen

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Main clock source (25 MHz)
      - description: Application-specific clock source (12-27 MHz)
      - description: RMII reference clock (50 MHz)
      - description: RGMII RX clock (125 MHz)

  clock-names:
    items:
      - const: osc_sys
      - const: osc_aud
      - const: gmac_rmii_ref
      - const: gmac_gr_mii_rxclk

  '#clock-cells':
    const: 1
    description:
      See <dt-bindings/clock/starfive-jh7100.h> for valid indices.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    clock-controller@11800000 {
            compatible = "starfive,jh7100-clkgen";
            reg = <0x11800000 0x10000>;
            clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
            clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
            #clock-cells = <1>;
    };


code:
Clock bindings for ST-Ericsson ABx500 clocks

Required properties :
- compatible : shall contain the following:
  "stericsson,ab8500-clk"
- #clock-cells should be <1>

The ABx500 clocks need to be placed as a subnode of an AB8500
device node, see mfd/ab8500.txt

All available clocks are defined as preprocessor macros in
dt-bindings/clock/ste-ab8500.h header and can be used in device
tree sources.

Example:

clock-controller {
	compatible = "stericsson,ab8500-clk";
	#clock-cells = <1>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ST-Ericsson DB8500 (U8500) clocks

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>
  - Linus Walleij <linus.walleij@linaro.org>

description: While named "U8500 clocks" these clocks are inside the
  DB8500 digital baseband system-on-chip and its siblings such as
  DB8520. These bindings consider the clocks present in the SoC
  itself, not off-chip clocks. There are four different on-chip
  clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
  control management unit) clocks and PRCC (peripheral reset and
  clock controller) clocks. For some reason PRCC 4 does not exist so
  the itemization can be a bit unintuitive.

properties:
  compatible:
    enum:
      - stericsson,u8500-clks
      - stericsson,u8540-clks
      - stericsson,u9540-clks

  reg:
    items:
      - description: PRCC 1 register area
      - description: PRCC 2 register area
      - description: PRCC 3 register area
      - description: PRCC 5 register area
      - description: PRCC 6 register area

  prcmu-clock:
    description: A subnode with one clock cell for PRCMU (power, reset, control
      management unit) clocks. The cell indicates which PRCMU clock in the
      prcmu-clock node the consumer wants to use.
    type: object

    properties:
      '#clock-cells':
        const: 1

    additionalProperties: false

  prcc-periph-clock:
    description: A subnode with two clock cells for PRCC (peripheral
      reset and clock controller) peripheral clocks. The first cell indicates
      which PRCC block the consumer wants to use, possible values are 1, 2, 3,
      5, 6. The second cell indicates which clock inside the PRCC block it
      wants, possible values are 0 thru 31.
    type: object

    properties:
      '#clock-cells':
        const: 2

    additionalProperties: false

  prcc-kernel-clock:
    description: A subnode with two clock cells for PRCC (peripheral reset
      and clock controller) kernel clocks. The first cell indicates which PRCC
      block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The
      second cell indicates which clock inside the PRCC block it wants, possible
      values are 0 thru 31.
    type: object

    properties:
      '#clock-cells':
        const: 2

    additionalProperties: false

  prcc-reset-controller:
    description: A subnode with two reset cells for the reset portions of the
      PRCC (peripheral reset and clock controller). The first cell indicates
      which PRCC block the consumer wants to use, possible values are 1, 2, 3
      5 and 6. The second cell indicates which reset line inside the PRCC block
      it wants to control, possible values are 0 thru 31.
    type: object

    properties:
      '#reset-cells':
        const: 2

    additionalProperties: false

  rtc32k-clock:
    description: A subnode with zero clock cells for the 32kHz RTC clock.
    type: object

    properties:
      '#clock-cells':
        const: 0

    additionalProperties: false

  smp-twd-clock:
    description: A subnode for the ARM SMP Timer Watchdog cluster with zero
      clock cells.
    type: object

    properties:
      '#clock-cells':
        const: 0

    additionalProperties: false

  clkout-clock:
    description: A subnode with three clock cells for externally routed clocks,
      output clocks. These are two PRCMU-internal clocks that can be divided and
      muxed out on the pads of the DB8500 SoC.
    type: object

    properties:
      '#clock-cells':
        description:
          The first cell indicates which output clock we are using,
          possible values are 0 (CLKOUT1) and 1 (CLKOUT2).
          The second cell indicates which clock we want to use as source,
          possible values are 0 thru 7, see the defines for the different
          source clocks.
          The third cell is a divider, legal values are 1 thru 63.
        const: 3

    additionalProperties: false

required:
  - compatible
  - reg
  - prcmu-clock
  - prcc-periph-clock
  - prcc-kernel-clock
  - rtc32k-clock
  - smp-twd-clock

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/ste-db8500-clkout.h>
    clocks@8012 {
      compatible = "stericsson,u8500-clks";
      reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
            <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
            <0xa03cf000 0x1000>;

      prcmu_clk: prcmu-clock {
        #clock-cells = <1>;
      };

      prcc_pclk: prcc-periph-clock {
        #clock-cells = <2>;
      };

      prcc_kclk: prcc-kernel-clock {
        #clock-cells = <2>;
      };

      prcc_reset: prcc-reset-controller {
        #reset-cells = <2>;
      };

      rtc_clk: rtc32k-clock {
        #clock-cells = <0>;
      };

      smp_twd_clk: smp-twd-clock {
        #clock-cells = <0>;
      };

      clkout_clk: clkout-clock {
        #clock-cells = <3>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sunplus SP7021 SoC Clock Controller

maintainers:
  - Qin Jian <qinjian@cqplus1.com>

properties:
  compatible:
    const: sunplus,sp7021-clkc

  reg:
    maxItems: 3

  clocks:
    maxItems: 1

  "#clock-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - "#clock-cells"

additionalProperties: false

examples:
  - |
    extclk: osc0 {
      compatible = "fixed-clock";
      #clock-cells = <0>;
      clock-frequency = <27000000>;
      clock-output-names = "extclk";
    };

    clkc: clock-controller@9c000004 {
      compatible = "sunplus,sp7021-clkc";
      reg = <0x9c000004 0x28>,
            <0x9c000200 0x44>,
            <0x9c000268 0x08>;
      clocks = <&extclk>;
      #clock-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Tesla FSD (Full Self-Driving) SoC clock controller

maintainers:
  - Alim Akhtar <alim.akhtar@samsung.com>
  - linux-fsd@tesla.com

description: |
  FSD clock controller consist of several clock management unit
  (CMU), which generates clocks for various inteernal SoC blocks.
  The root clock comes from external OSC clock (24 MHz).

  All available clocks are defined as preprocessor macros in
  'dt-bindings/clock/fsd-clk.h' header.

properties:
  compatible:
    enum:
      - tesla,fsd-clock-cmu
      - tesla,fsd-clock-imem
      - tesla,fsd-clock-peric
      - tesla,fsd-clock-fsys0
      - tesla,fsd-clock-fsys1
      - tesla,fsd-clock-mfc
      - tesla,fsd-clock-cam_csi

  clocks:
    minItems: 1
    maxItems: 6

  clock-names:
    minItems: 1
    maxItems: 6

  "#clock-cells":
    const: 1

  reg:
    maxItems: 1

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: tesla,fsd-clock-cmu
    then:
      properties:
        clocks:
          items:
            - description: External reference clock (24 MHz)
        clock-names:
          items:
            - const: fin_pll

  - if:
      properties:
        compatible:
          contains:
            const: tesla,fsd-clock-imem
    then:
      properties:
        clocks:
          items:
            - description: External reference clock (24 MHz)
            - description: IMEM TCU clock (from CMU_CMU)
            - description: IMEM bus clock (from CMU_CMU)
            - description: IMEM DMA clock (from CMU_CMU)
        clock-names:
          items:
            - const: fin_pll
            - const: dout_cmu_imem_tcuclk
            - const: dout_cmu_imem_aclk
            - const: dout_cmu_imem_dmaclk

  - if:
      properties:
        compatible:
          contains:
            const: tesla,fsd-clock-peric
    then:
      properties:
        clocks:
          items:
            - description: External reference clock (24 MHz)
            - description: Shared0 PLL div4 clock (from CMU_CMU)
            - description: PERIC shared1 div36 clock (from CMU_CMU)
            - description: PERIC shared0 div3 TBU clock (from CMU_CMU)
            - description: PERIC shared0 div20 clock (from CMU_CMU)
            - description: PERIC shared1 div4 DMAclock (from CMU_CMU)
        clock-names:
          items:
            - const: fin_pll
            - const: dout_cmu_pll_shared0_div4
            - const: dout_cmu_peric_shared1div36
            - const: dout_cmu_peric_shared0div3_tbuclk
            - const: dout_cmu_peric_shared0div20
            - const: dout_cmu_peric_shared1div4_dmaclk

  - if:
      properties:
        compatible:
          contains:
            const: tesla,fsd-clock-fsys0
    then:
      properties:
        clocks:
          items:
            - description: External reference clock (24 MHz)
            - description: Shared0 PLL div6 clock (from CMU_CMU)
            - description: FSYS0 shared1 div4 clock (from CMU_CMU)
            - description: FSYS0 shared0 div4 clock (from CMU_CMU)
        clock-names:
          items:
            - const: fin_pll
            - const: dout_cmu_pll_shared0_div6
            - const: dout_cmu_fsys0_shared1div4
            - const: dout_cmu_fsys0_shared0div4

  - if:
      properties:
        compatible:
          contains:
            const: tesla,fsd-clock-fsys1
    then:
      properties:
        clocks:
          items:
            - description: External reference clock (24 MHz)
            - description: FSYS1 shared0 div8 clock (from CMU_CMU)
            - description: FSYS1 shared0 div4 clock (from CMU_CMU)
        clock-names:
          items:
            - const: fin_pll
            - const: dout_cmu_fsys1_shared0div8
            - const: dout_cmu_fsys1_shared0div4

  - if:
      properties:
        compatible:
          contains:
            const: tesla,fsd-clock-mfc
    then:
      properties:
        clocks:
          items:
            - description: External reference clock (24 MHz)
        clock-names:
          items:
            - const: fin_pll

  - if:
      properties:
        compatible:
          contains:
            const: tesla,fsd-clock-cam_csi
    then:
      properties:
        clocks:
          items:
            - description: External reference clock (24 MHz)
        clock-names:
          items:
            - const: fin_pll

required:
  - compatible
  - "#clock-cells"
  - clocks
  - clock-names
  - reg

additionalProperties: false

examples:
  # Clock controller node for CMU_FSYS1
  - |
    #include <dt-bindings/clock/fsd-clk.h>

    clock_fsys1: clock-controller@16810000 {
          compatible = "tesla,fsd-clock-fsys1";
          reg = <0x16810000 0x3000>;
          #clock-cells = <1>;

          clocks = <&fin_pll>,
                   <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
                   <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
          clock-names = "fin_pll",
                        "dout_cmu_fsys1_shared0div8",
                        "dout_cmu_fsys1_shared0div4";
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti,am654-ehrpwm-tbclk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI EHRPWM Time Base Clock

maintainers:
  - Vignesh Raghavendra <vigneshr@ti.com>

properties:
  compatible:
    items:
      - enum:
          - ti,am654-ehrpwm-tbclk
          - ti,am64-epwm-tbclk
          - ti,am62-epwm-tbclk
      - const: syscon

  "#clock-cells":
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - "#clock-cells"
  - reg

additionalProperties: false

examples:
  - |
    ehrpwm_tbclk: syscon@4140 {
        compatible = "ti,am654-ehrpwm-tbclk", "syscon";
        reg = <0x4140 0x18>;
        #clock-cells = <1>;
    };


code:
Bindings for Texas Instruments CDCE706 programmable 3-PLL clock
synthesizer/multiplier/divider.

Reference: https://www.ti.com/lit/ds/symlink/cdce706.pdf

I2C device node required properties:
- compatible: shall be "ti,cdce706".
- reg: i2c device address, shall be in range [0x68...0x6b].
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock
  handles, shall be reference clock(s) connected to CLK_IN0
  and CLK_IN1 pins.
- clock-names: shall be clk_in0 and/or clk_in1. Use clk_in0
  in case of crystal oscillator or differential signal input
  configuration. Use clk_in0 and clk_in1 in case of independent
  single-ended LVCMOS inputs configuration.

Example:

	clocks {
		clk54: clk54 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <54000000>;
		};
	};
	...
	i2c0: i2c-master@d090000 {
		...
		cdce706: clock-synth@69 {
			compatible = "ti,cdce706";
			#clock-cells = <1>;
			reg = <0x69>;
			clocks = <&clk54>;
			clock-names = "clk_in0";
		};
	};
	...
	simple-audio-card,codec {
		...
		clocks = <&cdce706 4>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti,cdce925.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI CDCE913/925/937/949 programmable I2C clock synthesizers

maintainers:
  - Alexander Stein <alexander.stein@ew.tq-group.com>

description: |
  Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction

  - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
  - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
  - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
  - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949

properties:
  compatible:
    enum:
      - ti,cdce913
      - ti,cdce925
      - ti,cdce937
      - ti,cdce949

  reg:
    maxItems: 1

  clocks:
    items:
      - description: fixed parent clock

  "#clock-cells":
    const: 1

  vdd-supply:
    description: Regulator that provides 1.8V Vdd power supply

  vddout-supply:
    description: |
      Regulator that provides Vddout power supply.
      non-L variant: 2.5V or 3.3V for
      L variant: 1.8V for

  xtal-load-pf:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Crystal load-capacitor value to fine-tune performance on a
      board, or to compensate for external influences.

patternProperties:
  "^PLL[1-4]$":
    type: object
    description: |
      optional child node can be used to specify spread
      spectrum clocking parameters for a board

    additionalProperties: false

    properties:
      spread-spectrum:
        $ref: /schemas/types.yaml#/definitions/uint32
        description: SSC mode as defined in the data sheet

      spread-spectrum-center:
        type: boolean
        description: |
          Use "centered" mode instead of "max" mode. When
          present, the clock runs at the requested frequency on average.
          Otherwise the requested frequency is the maximum value of the
          SCC range.

required:
  - compatible
  - reg
  - clocks
  - "#clock-cells"

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        cdce925: clock-controller@64 {
            compatible = "ti,cdce925";
            reg = <0x64>;
            clocks = <&xtal_27Mhz>;
            #clock-cells = <1>;
            xtal-load-pf = <5>;
            vdd-supply = <&reg_1v8>;
            vddout-supply = <&reg_3v3>;
            /* PLL options to get SSC 1% centered */
            PLL2 {
                spread-spectrum = <4>;
                spread-spectrum-center;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for the Texas Instruments LMK04832

maintainers:
  - Liam Beguin <liambeguin@gmail.com>

description: |
  Devicetree binding for the LMK04832, a clock conditioner with JEDEC JESD204B
  support. The LMK04832 is pin compatible with the LMK0482x family.

  Link to datasheet, https://www.ti.com/lit/ds/symlink/lmk04832.pdf

properties:
  compatible:
    enum:
      - ti,lmk04832

  reg:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  '#clock-cells':
    const: 1

  spi-max-frequency:
    maximum: 5000000

  clocks:
    items:
      - description: PLL2 reference clock.

  clock-names:
    items:
      - const: oscin

  reset-gpios:
    maxItems: 1

  ti,spi-4wire-rdbk:
    description: |
      Select SPI 4wire readback pin configuration.
      Available readback pins are,
        CLKin_SEL0 0
        CLKin_SEL1 1
        RESET 2
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2]
    default: 1

  ti,vco-hz:
    description: Optional to set VCO frequency of the PLL in Hertz.

  ti,sysref-ddly:
    description: SYSREF digital delay value.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 8
    maximum: 8191
    default: 8

  ti,sysref-mux:
    description: |
      SYSREF Mux configuration.
      Available options are,
        Normal SYNC 0
        Re-clocked 1
        SYSREF Pulser 2
        SYSREF Continuous 3
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2, 3]
    default: 3

  ti,sync-mode:
    description: SYNC pin configuration.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2]
    default: 1

  ti,sysref-pulse-count:
    description:
      Number of SYSREF pulses to send when SYSREF is not in continuous mode.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2, 4, 8]
    default: 4

patternProperties:
  "@[0-9a-d]+$":
    type: object
    description:
      Child nodes used to configure output clocks.

    properties:
      reg:
        description:
          clock output identifier.
        minimum: 0
        maximum: 13

      ti,clkout-fmt:
        description:
          Clock output format.
          Available options are,
            Powerdown 0x00
            LVDS 0x01
            HSDS 6 mA 0x02
            HSDS 8 mA 0x03
            LVPECL 1600 mV 0x04
            LVPECL 2000 mV 0x05
            LCPECL 0x06
            CML 16 mA 0x07
            CML 24 mA 0x08
            CML 32 mA 0x09
            CMOS (Off/Inverted) 0x0a
            CMOS (Normal/Off) 0x0b
            CMOS (Inverted/Inverted) 0x0c
            CMOS (Inverted/Normal) 0x0d
            CMOS (Normal/Inverted) 0x0e
            CMOS (Normal/Normal) 0x0f
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 0
        maximum: 15

      ti,clkout-sysref:
        description:
          Select SYSREF clock path for output clock.
        type: boolean

    required:
      - reg

    additionalProperties: false

required:
  - compatible
  - reg
  - '#clock-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    clocks {
        lmk04832_oscin: oscin {
            compatible = "fixed-clock";

            #clock-cells = <0>;
            clock-frequency = <122880000>;
            clock-output-names = "lmk04832-oscin";
        };
    };

    spi0 {
        #address-cells = <1>;
        #size-cells = <0>;

        lmk04832: clock-controller@0 {
            #address-cells = <1>;
            #size-cells = <0>;

            reg = <0>;

            compatible = "ti,lmk04832";
            spi-max-frequency = <781250>;

            reset-gpios = <&gpio_lmk 0 0 0>;

            #clock-cells = <1>;
            clocks = <&lmk04832_oscin>;
            clock-names = "oscin";

            ti,spi-4wire-rdbk = <0>;
            ti,vco-hz = <2457600000>;

            assigned-clocks =
                <&lmk04832 0>, <&lmk04832 1>,
                <&lmk04832 2>, <&lmk04832 3>,
                <&lmk04832 4>,
                <&lmk04832 6>, <&lmk04832 7>,
                <&lmk04832 10>, <&lmk04832 11>;
            assigned-clock-rates =
                <122880000>, <384000>,
                <122880000>, <384000>,
                <122880000>,
                <153600000>, <384000>,
                <614400000>, <384000>;

            clkout0@0 {
                reg = <0>;
                ti,clkout-fmt = <0x01>; // LVDS
            };

            clkout1@1 {
                reg = <1>;
                ti,clkout-fmt = <0x01>; // LVDS
                ti,clkout-sysref;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI-SCI clock controller node bindings

maintainers:
  - Nishanth Menon <nm@ti.com>

description: |
  Some TI SoCs contain a system controller (like the Power Management Micro
  Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
  the state of the various hardware modules present on the SoC. Communication
  between the host processor running an OS and the system controller happens
  through a protocol called TI System Control Interface (TI-SCI protocol).

  This clock controller node uses the TI SCI protocol to perform various clock
  management of various hardware modules (devices) present on the SoC. This
  node must be a child node of the associated TI-SCI system controller node.

properties:
  $nodename:
    pattern: "^clock-controller$"

  compatible:
    const: ti,k2g-sci-clk

  "#clock-cells":
    const: 2
    description:
      The two cells represent values that the TI-SCI controller defines.

      The first cell should contain the device ID.

      The second cell should contain the clock ID.

      Please see  http://processors.wiki.ti.com/index.php/TISCI for
      protocol documentation for the values to be used for different devices.

additionalProperties: false

examples:
  - |
    k3_clks: clock-controller {
        compatible = "ti,k2g-sci-clk";
        #clock-cells = <2>;
    };


code:
Texas Instruments clkctrl clock binding

Texas Instruments SoCs can have a clkctrl clock controller for each
interconnect target module. The clkctrl clock controller manages functional
and interface clocks for each module. Each clkctrl controller can also
gate one or more optional functional clocks for a module, and can have one
or more clock muxes. There is a clkctrl clock controller typically for each
interconnect target module on omap4 and later variants.

The clock consumers can specify the index of the clkctrl clock using
the hardware offset from the clkctrl instance register space. The optional
clocks can be specified by clkctrl hardware offset and the index of the
optional clock.

For more information, please see the Linux clock framework binding at
Documentation/devicetree/bindings/clock/clock-bindings.txt.

Required properties :
- compatible : shall be "ti,clkctrl" or a clock domain specific name:
	       "ti,clkctrl-l4-cfg"
	       "ti,clkctrl-l4-per"
	       "ti,clkctrl-l4-secure"
	       "ti,clkctrl-l4-wkup"
- clock-output-names : from common clock binding
- #clock-cells : shall contain 2 with the first entry being the instance
		 offset from the clock domain base and the second being the
		 clock index
- reg : clock registers

Example: Clock controller node on omap 4430:

&cm2 {
	l4per: cm@1400 {
		cm_l4per@0 {
			cm_l4per_clkctrl: clock@20 {
				compatible = "ti,clkctrl";
				clock-output-names = "l4_per";
				reg = <0x20 0x1b0>;
				#clock-cells = <2>;
			};
		};
	};
};

Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h

#define OMAP4_CLKCTRL_OFFSET		0x20
#define OMAP4_CLKCTRL_INDEX(offset)	((offset) - OMAP4_CLKCTRL_OFFSET)
#define MODULEMODE_HWCTRL		1
#define MODULEMODE_SWCTRL		2

#define OMAP4_GPTIMER10_CLKTRL		OMAP4_CLKCTRL_INDEX(0x28)
#define OMAP4_GPTIMER11_CLKTRL		OMAP4_CLKCTRL_INDEX(0x30)
#define OMAP4_GPTIMER2_CLKTRL		OMAP4_CLKCTRL_INDEX(0x38)
...
#define OMAP4_GPIO2_CLKCTRL		OMAP_CLKCTRL_INDEX(0x60)

Example: Clock consumer node for GPIO2:

&gpio2 {
       clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0
		 &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>;
};


code:
* Device tree bindings for Texas Instruments keystone pll controller

The main pll controller used to drive theC66x CorePacs, the switch fabric,
and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
the NETCP modules) requires a PLL Controller to manage the various clock
divisions, gating, and synchronization.

Required properties:

- compatible:		"ti,keystone-pllctrl", "syscon"

- reg:			contains offset/length value for pll controller
			registers space.

Example:

pllctrl: pll-controller@02310000 {
	compatible = "ti,keystone-pllctrl", "syscon";
	reg = <0x02310000 0x200>;
};


code:
Binding for Texas Instruments ADPLL clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1]. It assumes a
register-mapped ADPLL with two to three selectable input clocks
and three to four children.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be one of "ti,dm814-adpll-s-clock" or
  "ti,dm814-adpll-lj-clock" depending on the type of the ADPLL
- #clock-cells : from common clock binding; shall be set to 1.
- clocks : link phandles of parent clocks clkinp and clkinpulow, note
  that the adpll-s-clock also has an optional clkinphif
- reg : address and length of the register set for controlling the ADPLL.

Examples:
	adpll_mpu_ck: adpll@40 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-s-clock";
		reg = <0x40 0x40>;
		clocks = <&devosc_ck &devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow", "clkinphif";
		clock-output-names = "481c5040.adpll.dcoclkldo",
				     "481c5040.adpll.clkout",
				     "481c5040.adpll.clkoutx2",
				     "481c5040.adpll.clkouthif";
	};

	adpll_dsp_ck: adpll@80 {
		#clock-cells = <1>;
		compatible = "ti,dm814-adpll-lj-clock";
		reg = <0x80 0x30>;
		clocks = <&devosc_ck &devosc_ck>;
		clock-names = "clkinp", "clkinpulow";
		clock-output-names = "481c5080.adpll.dcoclkldo",
				     "481c5080.adpll.clkout",
				     "481c5080.adpll.clkoutldo";
	};