code:
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (c) 2004-2006 Simtec Electronics
//	Ben Dooks <ben@simtec.co.uk>
//
// S3C24XX Power Manager (Suspend-To-RAM) support
//
// See Documentation/arm/samsung-s3c24xx/suspend.rst for more information
//
// Parts based on arch/arm/mach-pxa/pm.c
//
// Thanks to Dimitry Andric for debugging

#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/time.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/io.h>

#include "regs-clock.h"
#include "regs-gpio.h"
#include "regs-irq.h"
#include "gpio-samsung.h"

#include <asm/mach/time.h>

#include "gpio-cfg.h"
#include "pm.h"

#include "regs-mem-s3c24xx.h"

#define PFX "s3c24xx-pm: "

#ifdef CONFIG_PM_SLEEP
static struct sleep_save core_save[] = {
	/* we restore the timings here, with the proviso that the board
	 * brings the system up in an slower, or equal frequency setting
	 * to the original system.
	 *
	 * if we cannot guarantee this, then things are going to go very
	 * wrong here, as we modify the refresh and both pll settings.
	 */

	SAVE_ITEM(S3C2410_BWSCON),
	SAVE_ITEM(S3C2410_BANKCON0),
	SAVE_ITEM(S3C2410_BANKCON1),
	SAVE_ITEM(S3C2410_BANKCON2),
	SAVE_ITEM(S3C2410_BANKCON3),
	SAVE_ITEM(S3C2410_BANKCON4),
	SAVE_ITEM(S3C2410_BANKCON5),
};
#endif

/* s3c_pm_check_resume_pin
 *
 * check to see if the pin is configured correctly for sleep mode, and
 * make any necessary adjustments if it is not
*/

static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
{
	unsigned long irqstate;
	unsigned long pinstate;
	int irq = gpio_to_irq(pin);

	if (irqoffs < 4)
		irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
	else
		irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);

	pinstate = s3c_gpio_getcfg(pin);

	if (!irqstate) {
		if (pinstate == S3C2410_GPIO_IRQ)
			S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin);
	} else {
		if (pinstate == S3C2410_GPIO_IRQ) {
			S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
			s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
		}
	}
}

/* s3c_pm_configure_extint
 *
 * configure all external interrupt pins
*/

void s3c_pm_configure_extint(void)
{
	int pin;

	/* for each of the external interrupts (EINT0..EINT15) we
	 * need to check whether it is an external interrupt source,
	 * and then configure it as an input if it is not
	*/

	for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
		s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
	}

	for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
		s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
	}
}

#ifdef CONFIG_PM_SLEEP
void s3c_pm_restore_core(void)
{
	s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
}

void s3c_pm_save_core(void)
{
	s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
}
#endif


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2008 Openmoko, Inc.
// Copyright 2008 Simtec Electronics
//	Ben Dooks <ben@simtec.co.uk>
//	http://armlinux.simtec.co.uk/
//
// S3C64XX CPU PM support.

#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/serial_core.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/pm_domain.h>

#include "map.h"
#include "irqs.h"

#include "cpu.h"
#include "devs.h"
#include "pm.h"
#include "wakeup-mask.h"

#include "regs-gpio.h"
#include "regs-clock.h"
#include "gpio-samsung.h"

#include "regs-gpio-memport-s3c64xx.h"
#include "regs-modem-s3c64xx.h"
#include "regs-sys-s3c64xx.h"
#include "regs-syscon-power-s3c64xx.h"

struct s3c64xx_pm_domain {
	char *const name;
	u32 ena;
	u32 pwr_stat;
	struct generic_pm_domain pd;
};

static int s3c64xx_pd_off(struct generic_pm_domain *domain)
{
	struct s3c64xx_pm_domain *pd;
	u32 val;

	pd = container_of(domain, struct s3c64xx_pm_domain, pd);

	val = __raw_readl(S3C64XX_NORMAL_CFG);
	val &= ~(pd->ena);
	__raw_writel(val, S3C64XX_NORMAL_CFG);

	return 0;
}

static int s3c64xx_pd_on(struct generic_pm_domain *domain)
{
	struct s3c64xx_pm_domain *pd;
	u32 val;
	long retry = 1000000L;

	pd = container_of(domain, struct s3c64xx_pm_domain, pd);

	val = __raw_readl(S3C64XX_NORMAL_CFG);
	val |= pd->ena;
	__raw_writel(val, S3C64XX_NORMAL_CFG);

	/* Not all domains provide power status readback */
	if (pd->pwr_stat) {
		do {
			cpu_relax();
			if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat)
				break;
		} while (retry--);

		if (!retry) {
			pr_err("Failed to start domain %s\n", pd->name);
			return -EBUSY;
		}
	}

	return 0;
}

static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
	.name = "IROM",
	.ena = S3C64XX_NORMALCFG_IROM_ON,
	.pd = {
		.power_off = s3c64xx_pd_off,
		.power_on = s3c64xx_pd_on,
	},
};

static struct s3c64xx_pm_domain s3c64xx_pm_etm = {
	.name = "ETM",
	.ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON,
	.pwr_stat = S3C64XX_BLKPWRSTAT_ETM,
	.pd = {
		.power_off = s3c64xx_pd_off,
		.power_on = s3c64xx_pd_on,
	},
};

static struct s3c64xx_pm_domain s3c64xx_pm_s = {
	.name = "S",
	.ena = S3C64XX_NORMALCFG_DOMAIN_S_ON,
	.pwr_stat = S3C64XX_BLKPWRSTAT_S,
	.pd = {
		.power_off = s3c64xx_pd_off,
		.power_on = s3c64xx_pd_on,
	},
};

static struct s3c64xx_pm_domain s3c64xx_pm_f = {
	.name = "F",
	.ena = S3C64XX_NORMALCFG_DOMAIN_F_ON,
	.pwr_stat = S3C64XX_BLKPWRSTAT_F,
	.pd = {
		.power_off = s3c64xx_pd_off,
		.power_on = s3c64xx_pd_on,
	},
};

static struct s3c64xx_pm_domain s3c64xx_pm_p = {
	.name = "P",
	.ena = S3C64XX_NORMALCFG_DOMAIN_P_ON,
	.pwr_stat = S3C64XX_BLKPWRSTAT_P,
	.pd = {
		.power_off = s3c64xx_pd_off,
		.power_on = s3c64xx_pd_on,
	},
};

static struct s3c64xx_pm_domain s3c64xx_pm_i = {
	.name = "I",
	.ena = S3C64XX_NORMALCFG_DOMAIN_I_ON,
	.pwr_stat = S3C64XX_BLKPWRSTAT_I,
	.pd = {
		.power_off = s3c64xx_pd_off,
		.power_on = s3c64xx_pd_on,
	},
};

static struct s3c64xx_pm_domain s3c64xx_pm_g = {
	.name = "G",
	.ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
	.pd = {
		.power_off = s3c64xx_pd_off,
		.power_on = s3c64xx_pd_on,
	},
};

static struct s3c64xx_pm_domain s3c64xx_pm_v = {
	.name = "V",
	.ena = S3C64XX_NORMALCFG_DOMAIN_V_ON,
	.pwr_stat = S3C64XX_BLKPWRSTAT_V,
	.pd = {
		.power_off = s3c64xx_pd_off,
		.power_on = s3c64xx_pd_on,
	},
};

static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = {
	&s3c64xx_pm_irom,
};

static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
	&s3c64xx_pm_etm,
	&s3c64xx_pm_g,
	&s3c64xx_pm_v,
	&s3c64xx_pm_i,
	&s3c64xx_pm_p,
	&s3c64xx_pm_s,
	&s3c64xx_pm_f,
};

#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
void s3c_pm_debug_smdkled(u32 set, u32 clear)
{
	unsigned long flags;
	int i;

	local_irq_save(flags);
	for (i = 0; i < 4; i++) {
		if (clear & (1 << i))
			gpio_set_value(S3C64XX_GPN(12 + i), 0);
		if (set & (1 << i))
			gpio_set_value(S3C64XX_GPN(12 + i), 1);
	}
	local_irq_restore(flags);
}
#endif

#ifdef CONFIG_PM_SLEEP
static struct sleep_save core_save[] = {
	SAVE_ITEM(S3C64XX_MEM0DRVCON),
	SAVE_ITEM(S3C64XX_MEM1DRVCON),
};

static struct sleep_save misc_save[] = {
	SAVE_ITEM(S3C64XX_AHB_CON0),
	SAVE_ITEM(S3C64XX_AHB_CON1),
	SAVE_ITEM(S3C64XX_AHB_CON2),

	SAVE_ITEM(S3C64XX_SPCON),

	SAVE_ITEM(S3C64XX_MEM0CONSTOP),
	SAVE_ITEM(S3C64XX_MEM1CONSTOP),
	SAVE_ITEM(S3C64XX_MEM0CONSLP0),
	SAVE_ITEM(S3C64XX_MEM0CONSLP1),
	SAVE_ITEM(S3C64XX_MEM1CONSLP),

	SAVE_ITEM(S3C64XX_SDMA_SEL),
	SAVE_ITEM(S3C64XX_MODEM_MIFPCON),

	SAVE_ITEM(S3C64XX_NORMAL_CFG),
};

void s3c_pm_configure_extint(void)
{
	__raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
}

void s3c_pm_restore_core(void)
{
	__raw_writel(0, S3C64XX_EINT_MASK);

	s3c_pm_debug_smdkled(1 << 2, 0);

	s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
	s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
}

void s3c_pm_save_core(void)
{
	s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
	s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
}
#endif

/* since both s3c6400 and s3c6410 share the same sleep pm calls, we
 * put the per-cpu code in here until any new cpu comes along and changes
 * this.
 */

static int s3c64xx_cpu_suspend(unsigned long arg)
{
	unsigned long tmp;

	/* set our standby method to sleep */

	tmp = __raw_readl(S3C64XX_PWR_CFG);
	tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
	tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
	__raw_writel(tmp, S3C64XX_PWR_CFG);

	/* clear any old wakeup */

	__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
		     S3C64XX_WAKEUP_STAT);

	/* set the LED state to 0110 over sleep */
	s3c_pm_debug_smdkled(3 << 1, 0xf);

	/* issue the standby signal into the pm unit. Note, we
	 * issue a write-buffer drain just in case */

	tmp = 0;

	asm("b 1f\n\t"
	    ".align 5\n\t"
	    "1:\n\t"
	    "mcr p15, 0, %0, c7, c10, 5\n\t"
	    "mcr p15, 0, %0, c7, c10, 4\n\t"
	    "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));

	/* we should never get past here */

	pr_info("Failed to suspend the system\n");
	return 1; /* Aborting suspend */
}

/* mapping of interrupts to parts of the wakeup mask */
static const struct samsung_wakeup_mask wake_irqs[] = {
	{ .irq = IRQ_RTC_ALARM,	.bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
	{ .irq = IRQ_RTC_TIC,	.bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
	{ .irq = IRQ_PENDN,	.bit = S3C64XX_PWRCFG_TS_DISABLE, },
	{ .irq = IRQ_HSMMC0,	.bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
	{ .irq = IRQ_HSMMC1,	.bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
	{ .irq = IRQ_HSMMC2,	.bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
	{ .irq = NO_WAKEUP_IRQ,	.bit = S3C64XX_PWRCFG_BATF_DISABLE},
	{ .irq = NO_WAKEUP_IRQ,	.bit = S3C64XX_PWRCFG_MSM_DISABLE },
	{ .irq = NO_WAKEUP_IRQ,	.bit = S3C64XX_PWRCFG_HSI_DISABLE },
	{ .irq = NO_WAKEUP_IRQ,	.bit = S3C64XX_PWRCFG_MSM_DISABLE },
};

static void s3c64xx_pm_prepare(void)
{
	samsung_sync_wakemask(S3C64XX_PWR_CFG,
			      wake_irqs, ARRAY_SIZE(wake_irqs));

	/* store address of resume. */
	__raw_writel(__pa_symbol(s3c_cpu_resume), S3C64XX_INFORM0);

	/* ensure previous wakeup state is cleared before sleeping */
	__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
}

#ifdef CONFIG_SAMSUNG_PM_DEBUG
void s3c_pm_arch_update_uart(void __iomem *regs, struct pm_uart_save *save)
{
	u32 ucon;
	u32 ucon_clk
	u32 save_clk;
	u32 new_ucon;
	u32 delta;

	if (!soc_is_s3c64xx())
		return;

	ucon = __raw_readl(regs + S3C2410_UCON);
	ucon_clk = ucon & S3C6400_UCON_CLKMASK;
	sav_clk = save->ucon & S3C6400_UCON_CLKMASK;

	/* S3C64XX UART blocks only support level interrupts, so ensure that
	 * when we restore unused UART blocks we force the level interrupt
	 * settings. */
	save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;

	/* We have a constraint on changing the clock type of the UART
	 * between UCLKx and PCLK, so ensure that when we restore UCON
	 * that the CLK field is correctly modified if the bootloader
	 * has changed anything.
	 */
	if (ucon_clk != save_clk) {
		new_ucon = save->ucon;
		delta = ucon_clk ^ save_clk;

		/* change from UCLKx => wrong PCLK,
		 * either UCLK can be tested for by a bit-test
		 * with UCLK0 */
		if (ucon_clk & S3C6400_UCON_UCLK0 &&
		    !(save_clk & S3C6400_UCON_UCLK0) &&
		    delta & S3C6400_UCON_PCLK2) {
			new_ucon &= ~S3C6400_UCON_UCLK0;
		} else if (delta == S3C6400_UCON_PCLK2) {
			/* as an precaution, don't change from
			 * PCLK2 => PCLK or vice-versa */
			new_ucon ^= S3C6400_UCON_PCLK2;
		}

		S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
			  ucon, new_ucon, save->ucon);
		save->ucon = new_ucon;
	}
}
#endif

int __init s3c64xx_pm_init(void)
{
	int i;

	s3c_pm_init();

	for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++)
		pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd,
			      &pm_domain_always_on_gov, false);

	for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
		pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);

#ifdef CONFIG_S3C_DEV_FB
	if (dev_get_platdata(&s3c_device_fb.dev))
		pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
#endif

	return 0;
}

static __init int s3c64xx_pm_initcall(void)
{
	if (!soc_is_s3c64xx())
		return 0;

	pm_cpu_prep = s3c64xx_pm_prepare;
	pm_cpu_sleep = s3c64xx_cpu_suspend;

#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
	gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
	gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
	gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
	gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
	gpio_direction_output(S3C64XX_GPN(12), 0);
	gpio_direction_output(S3C64XX_GPN(13), 0);
	gpio_direction_output(S3C64XX_GPN(14), 0);
	gpio_direction_output(S3C64XX_GPN(15), 0);
#endif

	return 0;
}
arch_initcall(s3c64xx_pm_initcall);

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2008 Openmoko, Inc.
// Copyright 2004-2008 Simtec Electronics
//	Ben Dooks <ben@simtec.co.uk>
//	http://armlinux.simtec.co.uk/
//
// S3C common power management (suspend to ram) support.

#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/serial_s3c.h>
#include <linux/io.h>

#include <asm/cacheflush.h>
#include <asm/suspend.h>

#include "map.h"
#include "regs-clock.h"
#include "regs-irq.h"
#include "irqs.h"

#include <asm/irq.h>

#include "cpu.h"
#include "pm.h"
#include "pm-core.h"

/* for external use */

unsigned long s3c_pm_flags;

/* The IRQ ext-int code goes here, it is too small to currently bother
 * with its own file. */

unsigned long s3c_irqwake_intmask	= 0xffffffffL;
unsigned long s3c_irqwake_eintmask	= 0xffffffffL;

int s3c_irqext_wake(struct irq_data *data, unsigned int state)
{
	unsigned long bit = 1L << IRQ_EINT_BIT(data->irq);

	if (!(s3c_irqwake_eintallow & bit))
		return -ENOENT;

	printk(KERN_INFO "wake %s for irq %d\n",
	       state ? "enabled" : "disabled", data->irq);

	if (!state)
		s3c_irqwake_eintmask |= bit;
	else
		s3c_irqwake_eintmask &= ~bit;

	return 0;
}

void (*pm_cpu_prep)(void);
int (*pm_cpu_sleep)(unsigned long);

#define any_allowed(mask, allow) (((mask) & (allow)) != (allow))

/* s3c_pm_enter
 *
 * central control for sleep/resume process
*/

static int s3c_pm_enter(suspend_state_t state)
{
	int ret;
	/* ensure the debug is initialised (if enabled) */
	s3c_pm_debug_init_uart();

	S3C_PMDBG("%s(%d)\n", __func__, state);

	if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
		printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__);
		return -EINVAL;
	}

	/* check if we have anything to wake-up with... bad things seem
	 * to happen if you suspend with no wakeup (system will often
	 * require a full power-cycle)
	*/

	if (!of_have_populated_dt() &&
	    !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
		printk(KERN_ERR "%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	/* save all necessary core registers not covered by the drivers */

	if (!of_have_populated_dt()) {
		samsung_pm_save_gpios();
		samsung_pm_saved_gpios();
	}

	s3c_pm_save_uarts(soc_is_s3c2410());
	s3c_pm_save_core();

	/* set the irq configuration for wake */

	s3c_pm_configure_extint();

	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
	    s3c_irqwake_intmask, s3c_irqwake_eintmask);

	s3c_pm_arch_prepare_irqs();

	/* call cpu specific preparation */

	pm_cpu_prep();

	/* flush cache back to ram */

	flush_cache_all();

	s3c_pm_check_store();

	/* send the cpu to sleep... */

	s3c_pm_arch_stop_clocks();

	/* this will also act as our return point from when
	 * we resume as it saves its own register state and restores it
	 * during the resume.  */

	ret = cpu_suspend(0, pm_cpu_sleep);
	if (ret)
		return ret;

	/* restore the system state */

	s3c_pm_restore_core();
	s3c_pm_restore_uarts(soc_is_s3c2410());

	if (!of_have_populated_dt()) {
		samsung_pm_restore_gpios();
		s3c_pm_restored_gpios();
	}

	s3c_pm_debug_init_uart();

	/* check what irq (if any) restored the system */

	s3c_pm_arch_show_resume_irqs();

	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);

	/* LEDs should now be 1110 */
	s3c_pm_debug_smdkled(1 << 1, 0);

	s3c_pm_check_restore();

	/* ok, let's return from sleep */

	S3C_PMDBG("S3C PM Resume (post-restore)\n");
	return 0;
}

static int s3c_pm_prepare(void)
{
	/* prepare check area if configured */

	s3c_pm_check_prepare();
	return 0;
}

static void s3c_pm_finish(void)
{
	s3c_pm_check_cleanup();
}

static const struct platform_suspend_ops s3c_pm_ops = {
	.enter		= s3c_pm_enter,
	.prepare	= s3c_pm_prepare,
	.finish		= s3c_pm_finish,
	.valid		= suspend_valid_only_mem,
};

/* s3c_pm_init
 *
 * Attach the power management functions. This should be called
 * from the board specific initialisation if the board supports
 * it.
*/

int __init s3c_pm_init(void)
{
	printk("S3C Power Management, Copyright 2004 Simtec Electronics\n");

	suspend_set_ops(&s3c_pm_ops);
	return 0;
}


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2004 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Written by Ben Dooks, <ben@simtec.co.uk>
 */

/* s3c_pm_init
 *
 * called from board at initialisation time to setup the power
 * management
*/

#include "pm-common.h"

struct device;

#ifdef CONFIG_SAMSUNG_PM

extern __init int s3c_pm_init(void);
extern __init int s3c64xx_pm_init(void);

#else

static inline int s3c_pm_init(void)
{
	return 0;
}

static inline int s3c64xx_pm_init(void)
{
	return 0;
}
#endif

/* configuration for the IRQ mask over sleep */
extern unsigned long s3c_irqwake_intmask;
extern unsigned long s3c_irqwake_eintmask;

/* per-cpu sleep functions */

extern void (*pm_cpu_prep)(void);
extern int (*pm_cpu_sleep)(unsigned long);

/* Flags for PM Control */

extern unsigned long s3c_pm_flags;

/* from sleep.S */

extern int s3c2410_cpu_suspend(unsigned long);

#ifdef CONFIG_PM_SLEEP
extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
extern void s3c_cpu_resume(void);
#else
#define s3c_irq_wake NULL
#define s3c_cpu_resume NULL
#endif

#ifdef CONFIG_SAMSUNG_PM
extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
#else
#define s3c_irqext_wake NULL
#endif

#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
/**
 * s3c_pm_debug_smdkled() - Debug PM suspend/resume via SMDK Board LEDs
 * @set: set bits for the state of the LEDs
 * @clear: clear bits for the state of the LEDs.
 */
extern void s3c_pm_debug_smdkled(u32 set, u32 clear);

#else
static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { }
#endif /* CONFIG_S3C_PM_DEBUG_LED_SMDK */

/**
 * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ
 *
 * Setup all the necessary GPIO pins for waking the system on external
 * interrupt.
 */
extern void s3c_pm_configure_extint(void);

#ifdef CONFIG_GPIO_SAMSUNG
/**
 * samsung_pm_restore_gpios() - restore the state of the gpios after sleep.
 *
 * Restore the state of the GPIO pins after sleep, which may involve ensuring
 * that we do not glitch the state of the pins from that the bootloader's
 * resume code has done.
*/
extern void samsung_pm_restore_gpios(void);

/**
 * samsung_pm_save_gpios() - save the state of the GPIOs for restoring after sleep.
 *
 * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios().
 */
extern void samsung_pm_save_gpios(void);
#else
static inline void samsung_pm_restore_gpios(void) {}
static inline void samsung_pm_save_gpios(void) {}
#endif

extern void s3c_pm_save_core(void);
extern void s3c_pm_restore_core(void);


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2013 Tomasz Figa <tomasz.figa@gmail.com>
 *
 * Samsung PWM controller platform data helpers.
 */

#ifndef __ASM_ARCH_PWM_CORE_H
#define __ASM_ARCH_PWM_CORE_H __FILE__

#include <clocksource/samsung_pwm.h>

#ifdef CONFIG_SAMSUNG_DEV_PWM
extern void samsung_pwm_set_platdata(struct samsung_pwm_variant *pd);
#else
static inline void samsung_pwm_set_platdata(struct samsung_pwm_variant *pd) { }
#endif

#endif /* __ASM_ARCH_PWM_CORE_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2004 Shannon Holland <holland@loser.net>
 *
 * S3C2410 ADC registers
 */

#ifndef __ASM_ARCH_REGS_ADC_H
#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"

#define S3C2410_ADCREG(x) (x)

#define S3C2410_ADCCON	   S3C2410_ADCREG(0x00)
#define S3C2410_ADCTSC	   S3C2410_ADCREG(0x04)
#define S3C2410_ADCDLY	   S3C2410_ADCREG(0x08)
#define S3C2410_ADCDAT0	   S3C2410_ADCREG(0x0C)
#define S3C2410_ADCDAT1	   S3C2410_ADCREG(0x10)
#define S3C64XX_ADCUPDN		S3C2410_ADCREG(0x14)
#define S3C2443_ADCMUX		S3C2410_ADCREG(0x18)
#define S3C64XX_ADCCLRINT	S3C2410_ADCREG(0x18)
#define S5P_ADCMUX		S3C2410_ADCREG(0x1C)
#define S3C64XX_ADCCLRINTPNDNUP	S3C2410_ADCREG(0x20)

/* ADCCON Register Bits */
#define S3C64XX_ADCCON_RESSEL		(1<<16)
#define S3C2410_ADCCON_ECFLG		(1<<15)
#define S3C2410_ADCCON_PRSCEN		(1<<14)
#define S3C2410_ADCCON_PRSCVL(x)	(((x)&0xFF)<<6)
#define S3C2410_ADCCON_PRSCVLMASK	(0xFF<<6)
#define S3C2410_ADCCON_SELMUX(x)	(((x)&0x7)<<3)
#define S3C2410_ADCCON_MUXMASK		(0x7<<3)
#define S3C2416_ADCCON_RESSEL		(1 << 3)
#define S3C2410_ADCCON_STDBM		(1<<2)
#define S3C2410_ADCCON_READ_START	(1<<1)
#define S3C2410_ADCCON_ENABLE_START	(1<<0)
#define S3C2410_ADCCON_STARTMASK	(0x3<<0)

/* ADCTSC Register Bits */
#define S3C2443_ADCTSC_UD_SEN		(1 << 8)
#define S3C2410_ADCTSC_YM_SEN		(1<<7)
#define S3C2410_ADCTSC_YP_SEN		(1<<6)
#define S3C2410_ADCTSC_XM_SEN		(1<<5)
#define S3C2410_ADCTSC_XP_SEN		(1<<4)
#define S3C2410_ADCTSC_PULL_UP_DISABLE	(1<<3)
#define S3C2410_ADCTSC_AUTO_PST		(1<<2)
#define S3C2410_ADCTSC_XY_PST(x)	(((x)&0x3)<<0)

/* ADCDAT0 Bits */
#define S3C2410_ADCDAT0_UPDOWN		(1<<15)
#define S3C2410_ADCDAT0_AUTO_PST	(1<<14)
#define S3C2410_ADCDAT0_XY_PST		(0x3<<12)
#define S3C2410_ADCDAT0_XPDATA_MASK	(0x03FF)

/* ADCDAT1 Bits */
#define S3C2410_ADCDAT1_UPDOWN		(1<<15)
#define S3C2410_ADCDAT1_AUTO_PST	(1<<14)
#define S3C2410_ADCDAT1_XY_PST		(0x3<<12)
#define S3C2410_ADCDAT1_YPDATA_MASK	(0x03FF)

#endif /* __ASM_ARCH_REGS_ADC_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * S3C2410 clock register definitions
 */

#ifndef __ASM_ARM_REGS_CLOCK
#define __ASM_ARM_REGS_CLOCK

#include "map.h"

#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)

#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))

#define S3C2410_LOCKTIME    S3C2410_CLKREG(0x00)
#define S3C2410_MPLLCON	    S3C2410_CLKREG(0x04)
#define S3C2410_UPLLCON	    S3C2410_CLKREG(0x08)
#define S3C2410_CLKCON	    S3C2410_CLKREG(0x0C)
#define S3C2410_CLKSLOW	    S3C2410_CLKREG(0x10)
#define S3C2410_CLKDIVN	    S3C2410_CLKREG(0x14)

#define S3C2410_CLKCON_IDLE	     (1<<2)
#define S3C2410_CLKCON_POWER	     (1<<3)
#define S3C2410_CLKCON_NAND	     (1<<4)
#define S3C2410_CLKCON_LCDC	     (1<<5)
#define S3C2410_CLKCON_USBH	     (1<<6)
#define S3C2410_CLKCON_USBD	     (1<<7)
#define S3C2410_CLKCON_PWMT	     (1<<8)
#define S3C2410_CLKCON_SDI	     (1<<9)
#define S3C2410_CLKCON_UART0	     (1<<10)
#define S3C2410_CLKCON_UART1	     (1<<11)
#define S3C2410_CLKCON_UART2	     (1<<12)
#define S3C2410_CLKCON_GPIO	     (1<<13)
#define S3C2410_CLKCON_RTC	     (1<<14)
#define S3C2410_CLKCON_ADC	     (1<<15)
#define S3C2410_CLKCON_IIC	     (1<<16)
#define S3C2410_CLKCON_IIS	     (1<<17)
#define S3C2410_CLKCON_SPI	     (1<<18)

#define S3C2410_CLKDIVN_PDIVN	     (1<<0)
#define S3C2410_CLKDIVN_HDIVN	     (1<<1)

#define S3C2410_CLKSLOW_UCLK_OFF	(1<<7)
#define S3C2410_CLKSLOW_MPLL_OFF	(1<<5)
#define S3C2410_CLKSLOW_SLOW		(1<<4)
#define S3C2410_CLKSLOW_SLOWVAL(x)	(x)
#define S3C2410_CLKSLOW_GET_SLOWVAL(x)	((x) & 7)

#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)

/* extra registers */
#define S3C2440_CAMDIVN	    S3C2410_CLKREG(0x18)

#define S3C2440_CLKCON_CAMERA        (1<<19)
#define S3C2440_CLKCON_AC97          (1<<20)

#define S3C2440_CLKDIVN_PDIVN	     (1<<0)
#define S3C2440_CLKDIVN_HDIVN_MASK   (3<<1)
#define S3C2440_CLKDIVN_HDIVN_1      (0<<1)
#define S3C2440_CLKDIVN_HDIVN_2      (1<<1)
#define S3C2440_CLKDIVN_HDIVN_4_8    (2<<1)
#define S3C2440_CLKDIVN_HDIVN_3_6    (3<<1)
#define S3C2440_CLKDIVN_UCLK         (1<<3)

#define S3C2440_CAMDIVN_CAMCLK_MASK  (0xf<<0)
#define S3C2440_CAMDIVN_CAMCLK_SEL   (1<<4)
#define S3C2440_CAMDIVN_HCLK3_HALF   (1<<8)
#define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9)
#define S3C2440_CAMDIVN_DVSEN        (1<<12)

#define S3C2442_CAMDIVN_CAMCLK_DIV3  (1<<5)

#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */

#if defined(CONFIG_CPU_S3C2412)

#define S3C2412_OSCSET		S3C2410_CLKREG(0x18)
#define S3C2412_CLKSRC		S3C2410_CLKREG(0x1C)

#define S3C2412_PLLCON_OFF		(1<<20)

#define S3C2412_CLKDIVN_PDIVN		(1<<2)
#define S3C2412_CLKDIVN_HDIVN_MASK	(3<<0)
#define S3C2412_CLKDIVN_ARMDIVN		(1<<3)
#define S3C2412_CLKDIVN_DVSEN		(1<<4)
#define S3C2412_CLKDIVN_HALFHCLK	(1<<5)
#define S3C2412_CLKDIVN_USB48DIV	(1<<6)
#define S3C2412_CLKDIVN_UARTDIV_MASK	(15<<8)
#define S3C2412_CLKDIVN_UARTDIV_SHIFT	(8)
#define S3C2412_CLKDIVN_I2SDIV_MASK	(15<<12)
#define S3C2412_CLKDIVN_I2SDIV_SHIFT	(12)
#define S3C2412_CLKDIVN_CAMDIV_MASK	(15<<16)
#define S3C2412_CLKDIVN_CAMDIV_SHIFT	(16)

#define S3C2412_CLKCON_WDT		(1<<28)
#define S3C2412_CLKCON_SPI		(1<<27)
#define S3C2412_CLKCON_IIS		(1<<26)
#define S3C2412_CLKCON_IIC		(1<<25)
#define S3C2412_CLKCON_ADC		(1<<24)
#define S3C2412_CLKCON_RTC		(1<<23)
#define S3C2412_CLKCON_GPIO		(1<<22)
#define S3C2412_CLKCON_UART2		(1<<21)
#define S3C2412_CLKCON_UART1		(1<<20)
#define S3C2412_CLKCON_UART0		(1<<19)
#define S3C2412_CLKCON_SDI		(1<<18)
#define S3C2412_CLKCON_PWMT		(1<<17)
#define S3C2412_CLKCON_USBD		(1<<16)
#define S3C2412_CLKCON_CAMCLK		(1<<15)
#define S3C2412_CLKCON_UARTCLK		(1<<14)
/* missing 13 */
#define S3C2412_CLKCON_USB_HOST48	(1<<12)
#define S3C2412_CLKCON_USB_DEV48	(1<<11)
#define S3C2412_CLKCON_HCLKdiv2		(1<<10)
#define S3C2412_CLKCON_HCLKx2		(1<<9)
#define S3C2412_CLKCON_SDRAM		(1<<8)
/* missing 7 */
#define S3C2412_CLKCON_USBH		S3C2410_CLKCON_USBH
#define S3C2412_CLKCON_LCDC		S3C2410_CLKCON_LCDC
#define S3C2412_CLKCON_NAND		S3C2410_CLKCON_NAND
#define S3C2412_CLKCON_DMA3		(1<<3)
#define S3C2412_CLKCON_DMA2		(1<<2)
#define S3C2412_CLKCON_DMA1		(1<<1)
#define S3C2412_CLKCON_DMA0		(1<<0)

/* clock sourec controls */

#define S3C2412_CLKSRC_EXTCLKDIV_MASK		(7 << 0)
#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT		(0)
#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV	(1<<3)
#define S3C2412_CLKSRC_MSYSCLK_MPLL		(1<<4)
#define S3C2412_CLKSRC_USYSCLK_UPLL		(1<<5)
#define S3C2412_CLKSRC_UARTCLK_MPLL		(1<<8)
#define S3C2412_CLKSRC_I2SCLK_MPLL		(1<<9)
#define S3C2412_CLKSRC_USBCLK_HCLK		(1<<10)
#define S3C2412_CLKSRC_CAMCLK_HCLK		(1<<11)
#define S3C2412_CLKSRC_UREFCLK_EXTCLK	(1<<12)
#define S3C2412_CLKSRC_EREFCLK_EXTCLK	(1<<14)

#endif /* CONFIG_CPU_S3C2412 */

#define S3C2416_CLKDIV2		S3C2410_CLKREG(0x28)

#endif /* __ASM_ARM_REGS_CLOCK */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * S3C64XX clock register definitions
 */

#ifndef __PLAT_REGS_CLOCK_H
#define __PLAT_REGS_CLOCK_H __FILE__

/*
 * FIXME: Remove remaining definitions
 */

#define S3C_CLKREG(x)		(S3C_VA_SYS + (x))

#define S3C_PCLK_GATE		S3C_CLKREG(0x34)
#define S3C6410_CLK_SRC2	S3C_CLKREG(0x10C)
#define S3C_MEM_SYS_CFG		S3C_CLKREG(0x120)

/* PCLK GATE Registers */
#define S3C_CLKCON_PCLK_UART3		(1<<4)
#define S3C_CLKCON_PCLK_UART2		(1<<3)
#define S3C_CLKCON_PCLK_UART1		(1<<2)
#define S3C_CLKCON_PCLK_UART0		(1<<1)

/* MEM_SYS_CFG */
#define MEM_SYS_CFG_INDEP_CF		0x4000
#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON	0x30

#endif /* _PLAT_REGS_CLOCK_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */

#ifdef CONFIG_ARCH_S3C24XX
#include "regs-clock-s3c24xx.h"
#endif

#ifdef CONFIG_ARCH_S3C64XX
#include "regs-clock-s3c64xx.h"
#endif


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
 *		      http://www.simtec.co.uk/products/SWLINUX/
 *
 * S3C2440/S3C2412 Signal Drive Strength Control
 */

#ifndef __ASM_ARCH_REGS_DSC_S3C24XX_H
#define __ASM_ARCH_REGS_DSC_S3C24XX_H __FILE__

/* S3C2412 */
#define S3C2412_DSC0	   S3C2410_GPIOREG(0xdc)
#define S3C2412_DSC1	   S3C2410_GPIOREG(0xe0)

/* S3C2440 */
#define S3C2440_DSC0	   S3C2410_GPIOREG(0xc4)
#define S3C2440_DSC1	   S3C2410_GPIOREG(0xc8)

#endif	/* __ASM_ARCH_REGS_DSC_S3C24XX_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
 * S3C64XX - GPIO memory port register definitions
 */

#ifndef __MACH_S3C64XX_REGS_GPIO_MEMPORT_H
#define __MACH_S3C64XX_REGS_GPIO_MEMPORT_H __FILE__

#define S3C64XX_MEM0CONSTOP	S3C64XX_GPIOREG(0x1B0)
#define S3C64XX_MEM1CONSTOP	S3C64XX_GPIOREG(0x1B4)

#define S3C64XX_MEM0CONSLP0	S3C64XX_GPIOREG(0x1C0)
#define S3C64XX_MEM0CONSLP1	S3C64XX_GPIOREG(0x1C4)
#define S3C64XX_MEM1CONSLP	S3C64XX_GPIOREG(0x1C8)

#define S3C64XX_MEM0DRVCON	S3C64XX_GPIOREG(0x1D0)
#define S3C64XX_MEM1DRVCON	S3C64XX_GPIOREG(0x1D4)

#endif /* __MACH_S3C64XX_REGS_GPIO_MEMPORT_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk>
 *	http://www.simtec.co.uk/products/SWLINUX/
 *
 * S3C2410 GPIO register definitions
 */

#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H

#include "map-s3c.h"

#define S3C24XX_MISCCR		S3C24XX_GPIOREG2(0x80)

/* general configuration options */

#define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
#define S3C2410_GPIO_INPUT   (0xFFFFFFF0)	/* not available on A */
#define S3C2410_GPIO_OUTPUT  (0xFFFFFFF1)
#define S3C2410_GPIO_IRQ     (0xFFFFFFF2)	/* not available for all */
#define S3C2410_GPIO_SFN2    (0xFFFFFFF2)	/* bank A => addr/cs/nand */
#define S3C2410_GPIO_SFN3    (0xFFFFFFF3)	/* not available on A */

/* register address for the GPIO registers.
 * S3C24XX_GPIOREG2 is for the second set of registers in the
 * GPIO which move between s3c2410 and s3c2412 type systems */

#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)

/* configure GPIO ports A..G */

/* port A - S3C2410: 22bits, zero in bit X makes pin X output
 * 1 makes port special function, this is default
*/
#define S3C2410_GPACON	   S3C2410_GPIOREG(0x00)
#define S3C2410_GPADAT	   S3C2410_GPIOREG(0x04)

#define S3C2410_GPA0_ADDR0   (1<<0)
#define S3C2410_GPA1_ADDR16  (1<<1)
#define S3C2410_GPA2_ADDR17  (1<<2)
#define S3C2410_GPA3_ADDR18  (1<<3)
#define S3C2410_GPA4_ADDR19  (1<<4)
#define S3C2410_GPA5_ADDR20  (1<<5)
#define S3C2410_GPA6_ADDR21  (1<<6)
#define S3C2410_GPA7_ADDR22  (1<<7)
#define S3C2410_GPA8_ADDR23  (1<<8)
#define S3C2410_GPA9_ADDR24  (1<<9)
#define S3C2410_GPA10_ADDR25 (1<<10)
#define S3C2410_GPA11_ADDR26 (1<<11)
#define S3C2410_GPA12_nGCS1  (1<<12)
#define S3C2410_GPA13_nGCS2  (1<<13)
#define S3C2410_GPA14_nGCS3  (1<<14)
#define S3C2410_GPA15_nGCS4  (1<<15)
#define S3C2410_GPA16_nGCS5  (1<<16)
#define S3C2410_GPA17_CLE    (1<<17)
#define S3C2410_GPA18_ALE    (1<<18)
#define S3C2410_GPA19_nFWE   (1<<19)
#define S3C2410_GPA20_nFRE   (1<<20)
#define S3C2410_GPA21_nRSTOUT (1<<21)
#define S3C2410_GPA22_nFCE   (1<<22)

/* 0x08 and 0x0c are reserved on S3C2410 */

/* S3C2410:
 * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
 *   00 = input, 01 = output, 10=special function, 11=reserved

 * bit 0,1 = pin 0, 2,3= pin 1...
 *
 * CPBUP = pull up resistor control, 1=disabled, 0=enabled
*/

#define S3C2410_GPBCON	   S3C2410_GPIOREG(0x10)
#define S3C2410_GPBDAT	   S3C2410_GPIOREG(0x14)
#define S3C2410_GPBUP	   S3C2410_GPIOREG(0x18)

/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */

#define S3C2410_GPB0_TOUT0   (0x02 << 0)

#define S3C2410_GPB1_TOUT1   (0x02 << 2)

#define S3C2410_GPB2_TOUT2   (0x02 << 4)

#define S3C2410_GPB3_TOUT3   (0x02 << 6)

#define S3C2410_GPB4_TCLK0   (0x02 << 8)
#define S3C2410_GPB4_MASK    (0x03 << 8)

#define S3C2410_GPB5_nXBACK  (0x02 << 10)
#define S3C2443_GPB5_XBACK   (0x03 << 10)

#define S3C2410_GPB6_nXBREQ  (0x02 << 12)
#define S3C2443_GPB6_XBREQ   (0x03 << 12)

#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
#define S3C2443_GPB7_XDACK1  (0x03 << 14)

#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)

#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
#define S3C2443_GPB9_XDACK0  (0x03 << 18)

#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
#define S3C2443_GPB10_XDREQ0 (0x03 << 20)

#define S3C2410_GPB_PUPDIS(x)  (1<<(x))

/* Port C consits of 16 GPIO/Special function
 *
 * almost identical setup to port b, but the special functions are mostly
 * to do with the video system's sync/etc.
*/

#define S3C2410_GPCCON	   S3C2410_GPIOREG(0x20)
#define S3C2410_GPCDAT	   S3C2410_GPIOREG(0x24)
#define S3C2410_GPCUP	   S3C2410_GPIOREG(0x28)
#define S3C2410_GPC0_LEND	(0x02 << 0)
#define S3C2410_GPC1_VCLK	(0x02 << 2)
#define S3C2410_GPC2_VLINE	(0x02 << 4)
#define S3C2410_GPC3_VFRAME	(0x02 << 6)
#define S3C2410_GPC4_VM		(0x02 << 8)
#define S3C2410_GPC5_LCDVF0	(0x02 << 10)
#define S3C2410_GPC6_LCDVF1	(0x02 << 12)
#define S3C2410_GPC7_LCDVF2	(0x02 << 14)
#define S3C2410_GPC8_VD0	(0x02 << 16)
#define S3C2410_GPC9_VD1	(0x02 << 18)
#define S3C2410_GPC10_VD2	(0x02 << 20)
#define S3C2410_GPC11_VD3	(0x02 << 22)
#define S3C2410_GPC12_VD4	(0x02 << 24)
#define S3C2410_GPC13_VD5	(0x02 << 26)
#define S3C2410_GPC14_VD6	(0x02 << 28)
#define S3C2410_GPC15_VD7	(0x02 << 30)
#define S3C2410_GPC_PUPDIS(x)  (1<<(x))

/*
 * S3C2410: Port D consists of 16 GPIO/Special function
 *
 * almost identical setup to port b, but the special functions are mostly
 * to do with the video system's data.
 *
 * almost identical setup to port c
*/

#define S3C2410_GPDCON	   S3C2410_GPIOREG(0x30)
#define S3C2410_GPDDAT	   S3C2410_GPIOREG(0x34)
#define S3C2410_GPDUP	   S3C2410_GPIOREG(0x38)

#define S3C2410_GPD0_VD8	(0x02 << 0)
#define S3C2442_GPD0_nSPICS1	(0x03 << 0)

#define S3C2410_GPD1_VD9	(0x02 << 2)
#define S3C2442_GPD1_SPICLK1	(0x03 << 2)

#define S3C2410_GPD2_VD10	(0x02 << 4)

#define S3C2410_GPD3_VD11	(0x02 << 6)

#define S3C2410_GPD4_VD12	(0x02 << 8)

#define S3C2410_GPD5_VD13	(0x02 << 10)

#define S3C2410_GPD6_VD14	(0x02 << 12)

#define S3C2410_GPD7_VD15	(0x02 << 14)

#define S3C2410_GPD8_VD16	(0x02 << 16)
#define S3C2440_GPD8_SPIMISO1	(0x03 << 16)

#define S3C2410_GPD9_VD17	(0x02 << 18)
#define S3C2440_GPD9_SPIMOSI1	(0x03 << 18)

#define S3C2410_GPD10_VD18	(0x02 << 20)
#define S3C2440_GPD10_SPICLK1	(0x03 << 20)

#define S3C2410_GPD11_VD19	(0x02 << 22)

#define S3C2410_GPD12_VD20	(0x02 << 24)

#define S3C2410_GPD13_VD21	(0x02 << 26)

#define S3C2410_GPD14_VD22	(0x02 << 28)
#define S3C2410_GPD14_nSS1	(0x03 << 28)

#define S3C2410_GPD15_VD23	(0x02 << 30)
#define S3C2410_GPD15_nSS0	(0x03 << 30)

#define S3C2410_GPD_PUPDIS(x)  (1<<(x))

/* S3C2410:
 * Port E consists of 16 GPIO/Special function
 *
 * again, the same as port B, but dealing with I2S, SDI, and
 * more miscellaneous functions
 *
 * GPIO / interrupt inputs
*/

#define S3C2410_GPECON	   S3C2410_GPIOREG(0x40)
#define S3C2410_GPEDAT	   S3C2410_GPIOREG(0x44)
#define S3C2410_GPEUP	   S3C2410_GPIOREG(0x48)

#define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
#define S3C2410_GPE0_MASK      (0x03 << 0)

#define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
#define S3C2443_GPE1_AC_SYNC   (0x03 << 2)
#define S3C2410_GPE1_MASK      (0x03 << 2)

#define S3C2410_GPE2_CDCLK     (0x02 << 4)
#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)

#define S3C2410_GPE3_I2SSDI    (0x02 << 6)
#define S3C2443_GPE3_AC_SDI    (0x03 << 6)
#define S3C2410_GPE3_nSS0      (0x03 << 6)
#define S3C2410_GPE3_MASK      (0x03 << 6)

#define S3C2410_GPE4_I2SSDO    (0x02 << 8)
#define S3C2443_GPE4_AC_SDO    (0x03 << 8)
#define S3C2410_GPE4_I2SSDI    (0x03 << 8)
#define S3C2410_GPE4_MASK      (0x03 << 8)

#define S3C2410_GPE5_SDCLK     (0x02 << 10)
#define S3C2443_GPE5_SD1_CLK   (0x02 << 10)
#define S3C2443_GPE5_AC_BITCLK (0x03 << 10)

#define S3C2410_GPE6_SDCMD     (0x02 << 12)
#define S3C2443_GPE6_SD1_CMD   (0x02 << 12)
#define S3C2443_GPE6_AC_SDI    (0x03 << 12)

#define S3C2410_GPE7_SDDAT0    (0x02 << 14)
#define S3C2443_GPE5_SD1_DAT0  (0x02 << 14)
#define S3C2443_GPE7_AC_SDO    (0x03 << 14)

#define S3C2410_GPE8_SDDAT1    (0x02 << 16)
#define S3C2443_GPE8_SD1_DAT1  (0x02 << 16)
#define S3C2443_GPE8_AC_SYNC   (0x03 << 16)

#define S3C2410_GPE9_SDDAT2    (0x02 << 18)
#define S3C2443_GPE9_SD1_DAT2  (0x02 << 18)
#define S3C2443_GPE9_AC_nRESET (0x03 << 18)

#define S3C2410_GPE10_SDDAT3   (0x02 << 20)
#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)

#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)

#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)

#define S3C2410_GPE13_SPICLK0  (0x02 << 26)

#define S3C2410_GPE14_IICSCL   (0x02 << 28)
#define S3C2410_GPE14_MASK     (0x03 << 28)

#define S3C2410_GPE15_IICSDA   (0x02 << 30)
#define S3C2410_GPE15_MASK     (0x03 << 30)

#define S3C2440_GPE0_ACSYNC    (0x03 << 0)
#define S3C2440_GPE1_ACBITCLK  (0x03 << 2)
#define S3C2440_GPE2_ACRESET   (0x03 << 4)
#define S3C2440_GPE3_ACIN      (0x03 << 6)
#define S3C2440_GPE4_ACOUT     (0x03 << 8)

#define S3C2410_GPE_PUPDIS(x)  (1<<(x))

/* S3C2410:
 * Port F consists of 8 GPIO/Special function
 *
 * GPIO / interrupt inputs
 *
 * GPFCON has 2 bits for each of the input pins on port F
 *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
 *
 * pull up works like all other ports.
 *
 * GPIO/serial/misc pins
*/

#define S3C2410_GPFCON	   S3C2410_GPIOREG(0x50)
#define S3C2410_GPFDAT	   S3C2410_GPIOREG(0x54)
#define S3C2410_GPFUP	   S3C2410_GPIOREG(0x58)

#define S3C2410_GPF0_EINT0  (0x02 << 0)
#define S3C2410_GPF1_EINT1  (0x02 << 2)
#define S3C2410_GPF2_EINT2  (0x02 << 4)
#define S3C2410_GPF3_EINT3  (0x02 << 6)
#define S3C2410_GPF4_EINT4  (0x02 << 8)
#define S3C2410_GPF5_EINT5  (0x02 << 10)
#define S3C2410_GPF6_EINT6  (0x02 << 12)
#define S3C2410_GPF7_EINT7  (0x02 << 14)
#define S3C2410_GPF_PUPDIS(x)  (1<<(x))

/* S3C2410:
 * Port G consists of 8 GPIO/IRQ/Special function
 *
 * GPGCON has 2 bits for each of the input pins on port G
 *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
 *
 * pull up works like all other ports.
*/

#define S3C2410_GPGCON	   S3C2410_GPIOREG(0x60)
#define S3C2410_GPGDAT	   S3C2410_GPIOREG(0x64)
#define S3C2410_GPGUP	   S3C2410_GPIOREG(0x68)

#define S3C2410_GPG0_EINT8    (0x02 << 0)

#define S3C2410_GPG1_EINT9    (0x02 << 2)

#define S3C2410_GPG2_EINT10   (0x02 << 4)
#define S3C2410_GPG2_nSS0     (0x03 << 4)

#define S3C2410_GPG3_EINT11   (0x02 << 6)
#define S3C2410_GPG3_nSS1     (0x03 << 6)

#define S3C2410_GPG4_EINT12   (0x02 << 8)
#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)

#define S3C2410_GPG5_EINT13   (0x02 << 10)
#define S3C2410_GPG5_SPIMISO1 (0x03 << 10)	/* not s3c2443 */

#define S3C2410_GPG6_EINT14   (0x02 << 12)
#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)

#define S3C2410_GPG7_EINT15   (0x02 << 14)
#define S3C2410_GPG7_SPICLK1  (0x03 << 14)

#define S3C2410_GPG8_EINT16   (0x02 << 16)

#define S3C2410_GPG9_EINT17   (0x02 << 18)

#define S3C2410_GPG10_EINT18  (0x02 << 20)

#define S3C2410_GPG11_EINT19  (0x02 << 22)
#define S3C2410_GPG11_TCLK1   (0x03 << 22)
#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)

#define S3C2410_GPG12_EINT20  (0x02 << 24)
#define S3C2410_GPG12_XMON    (0x03 << 24)
#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
#define S3C2443_GPG12_nINPACK (0x03 << 24)

#define S3C2410_GPG13_EINT21  (0x02 << 26)
#define S3C2410_GPG13_nXPON   (0x03 << 26)
#define S3C2443_GPG13_CF_nREG (0x03 << 26)

#define S3C2410_GPG14_EINT22  (0x02 << 28)
#define S3C2410_GPG14_YMON    (0x03 << 28)
#define S3C2443_GPG14_CF_RESET (0x03 << 28)

#define S3C2410_GPG15_EINT23  (0x02 << 30)
#define S3C2410_GPG15_nYPON   (0x03 << 30)
#define S3C2443_GPG15_CF_PWR  (0x03 << 30)

#define S3C2410_GPG_PUPDIS(x)  (1<<(x))

/* Port H consists of11 GPIO/serial/Misc pins
 *
 * GPHCON has 2 bits for each of the input pins on port H
 *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
 *
 * pull up works like all other ports.
*/

#define S3C2410_GPHCON	   S3C2410_GPIOREG(0x70)
#define S3C2410_GPHDAT	   S3C2410_GPIOREG(0x74)
#define S3C2410_GPHUP	   S3C2410_GPIOREG(0x78)

#define S3C2410_GPH0_nCTS0  (0x02 << 0)
#define S3C2416_GPH0_TXD0  (0x02 << 0)

#define S3C2410_GPH1_nRTS0  (0x02 << 2)
#define S3C2416_GPH1_RXD0  (0x02 << 2)

#define S3C2410_GPH2_TXD0   (0x02 << 4)
#define S3C2416_GPH2_TXD1   (0x02 << 4)

#define S3C2410_GPH3_RXD0   (0x02 << 6)
#define S3C2416_GPH3_RXD1   (0x02 << 6)

#define S3C2410_GPH4_TXD1   (0x02 << 8)
#define S3C2416_GPH4_TXD2   (0x02 << 8)

#define S3C2410_GPH5_RXD1   (0x02 << 10)
#define S3C2416_GPH5_RXD2   (0x02 << 10)

#define S3C2410_GPH6_TXD2   (0x02 << 12)
#define S3C2416_GPH6_TXD3   (0x02 << 12)
#define S3C2410_GPH6_nRTS1  (0x03 << 12)
#define S3C2416_GPH6_nRTS2  (0x03 << 12)

#define S3C2410_GPH7_RXD2   (0x02 << 14)
#define S3C2416_GPH7_RXD3   (0x02 << 14)
#define S3C2410_GPH7_nCTS1  (0x03 << 14)
#define S3C2416_GPH7_nCTS2  (0x03 << 14)

#define S3C2410_GPH8_UCLK   (0x02 << 16)
#define S3C2416_GPH8_nCTS0  (0x02 << 16)

#define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
#define S3C2442_GPH9_nSPICS0  (0x03 << 18)
#define S3C2416_GPH9_nRTS0    (0x02 << 18)

#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
#define S3C2416_GPH10_nCTS1   (0x02 << 20)

#define S3C2416_GPH11_nRTS1   (0x02 << 22)

#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24)

#define S3C2416_GPH13_CLKOUT0 (0x02 << 26)

#define S3C2416_GPH14_CLKOUT1 (0x02 << 28)

/* The S3C2412 and S3C2413 move the GPJ register set to after
 * GPH, which means all registers after 0x80 are now offset by 0x10
 * for the 2412/2413 from the 2410/2440/2442
*/

/*
 * Port J consists of 13 GPIO/Camera pins. GPJCON has 2 bits
 * for each of the pins on port J.
 *   00 - input, 01 output, 10 - camera
 *
 * Pull up works like all other ports.
 */

#define S3C2413_GPJCON	   S3C2410_GPIOREG(0x80)
#define S3C2413_GPJDAT	   S3C2410_GPIOREG(0x84)
#define S3C2413_GPJUP	   S3C2410_GPIOREG(0x88)
#define S3C2413_GPJSLPCON  S3C2410_GPIOREG(0x8C)

/* S3C2443 and above */
#define S3C2440_GPJCON	   S3C2410_GPIOREG(0xD0)
#define S3C2440_GPJDAT	   S3C2410_GPIOREG(0xD4)
#define S3C2440_GPJUP	   S3C2410_GPIOREG(0xD8)

#define S3C2443_GPKCON	   S3C2410_GPIOREG(0xE0)
#define S3C2443_GPKDAT	   S3C2410_GPIOREG(0xE4)
#define S3C2443_GPKUP	   S3C2410_GPIOREG(0xE8)

#define S3C2443_GPLCON	   S3C2410_GPIOREG(0xF0)
#define S3C2443_GPLDAT	   S3C2410_GPIOREG(0xF4)
#define S3C2443_GPLUP	   S3C2410_GPIOREG(0xF8)

#define S3C2443_GPMCON	   S3C2410_GPIOREG(0x100)
#define S3C2443_GPMDAT	   S3C2410_GPIOREG(0x104)
#define S3C2443_GPMUP	   S3C2410_GPIOREG(0x108)

/* miscellaneous control */
#define S3C2410_MISCCR	   S3C2410_GPIOREG(0x80)

/* see clock.h for dclk definitions */

/* pullup control on databus */
#define S3C2410_MISCCR_SPUCR_HEN    (0<<0)
#define S3C2410_MISCCR_SPUCR_HDIS   (1<<0)
#define S3C2410_MISCCR_SPUCR_LEN    (0<<1)
#define S3C2410_MISCCR_SPUCR_LDIS   (1<<1)

#define S3C2410_MISCCR_USBDEV	    (0<<3)
#define S3C2410_MISCCR_USBHOST	    (1<<3)

#define S3C2410_MISCCR_CLK0_MPLL    (0<<4)
#define S3C2410_MISCCR_CLK0_UPLL    (1<<4)
#define S3C2410_MISCCR_CLK0_FCLK    (2<<4)
#define S3C2410_MISCCR_CLK0_HCLK    (3<<4)
#define S3C2410_MISCCR_CLK0_PCLK    (4<<4)
#define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)
#define S3C2410_MISCCR_CLK0_MASK    (7<<4)

#define S3C2412_MISCCR_CLK0_RTC	    (2<<4)

#define S3C2410_MISCCR_CLK1_MPLL    (0<<8)
#define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
#define S3C2410_MISCCR_CLK1_FCLK    (2<<8)
#define S3C2410_MISCCR_CLK1_HCLK    (3<<8)
#define S3C2410_MISCCR_CLK1_PCLK    (4<<8)
#define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)
#define S3C2410_MISCCR_CLK1_MASK    (7<<8)

#define S3C2412_MISCCR_CLK1_CLKsrc  (0<<8)

#define S3C2410_MISCCR_USBSUSPND0   (1<<12)
#define S3C2416_MISCCR_SEL_SUSPND   (1<<12)
#define S3C2410_MISCCR_USBSUSPND1   (1<<13)

#define S3C2410_MISCCR_nRSTCON	    (1<<16)

#define S3C2410_MISCCR_nEN_SCLK0    (1<<17)
#define S3C2410_MISCCR_nEN_SCLK1    (1<<18)
#define S3C2410_MISCCR_nEN_SCLKE    (1<<19)	/* not 2412 */
#define S3C2410_MISCCR_SDSLEEP	    (7<<17)

#define S3C2416_MISCCR_FLT_I2C      (1<<24)
#define S3C2416_MISCCR_HSSPI_EN2    (1<<31)

/* external interrupt control... */
/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
 * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
 *
 * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
 *
 * Samsung datasheet p9-25
*/
#define S3C2410_EXTINT0	   S3C2410_GPIOREG(0x88)
#define S3C2410_EXTINT1	   S3C2410_GPIOREG(0x8C)
#define S3C2410_EXTINT2	   S3C2410_GPIOREG(0x90)

#define S3C24XX_EXTINT0	   S3C24XX_GPIOREG2(0x88)
#define S3C24XX_EXTINT1	   S3C24XX_GPIOREG2(0x8C)
#define S3C24XX_EXTINT2	   S3C24XX_GPIOREG2(0x90)

/* interrupt filtering control for EINT16..EINT23 */
#define S3C2410_EINFLT0	   S3C2410_GPIOREG(0x94)
#define S3C2410_EINFLT1	   S3C2410_GPIOREG(0x98)
#define S3C2410_EINFLT2	   S3C2410_GPIOREG(0x9C)
#define S3C2410_EINFLT3	   S3C2410_GPIOREG(0xA0)

#define S3C24XX_EINFLT0	   S3C24XX_GPIOREG2(0x94)
#define S3C24XX_EINFLT1	   S3C24XX_GPIOREG2(0x98)
#define S3C24XX_EINFLT2	   S3C24XX_GPIOREG2(0x9C)
#define S3C24XX_EINFLT3	   S3C24XX_GPIOREG2(0xA0)

/* values for interrupt filtering */
#define S3C2410_EINTFLT_PCLK		(0x00)
#define S3C2410_EINTFLT_EXTCLK		(1<<7)
#define S3C2410_EINTFLT_WIDTHMSK(x)	((x) & 0x3f)

/* removed EINTxxxx defs from here, not meant for this */

/* GSTATUS have miscellaneous information in them
 *
 * These move between s3c2410 and s3c2412 style systems.
 */

#define S3C2410_GSTATUS0   S3C2410_GPIOREG(0x0AC)
#define S3C2410_GSTATUS1   S3C2410_GPIOREG(0x0B0)
#define S3C2410_GSTATUS2   S3C2410_GPIOREG(0x0B4)
#define S3C2410_GSTATUS3   S3C2410_GPIOREG(0x0B8)
#define S3C2410_GSTATUS4   S3C2410_GPIOREG(0x0BC)

#define S3C2412_GSTATUS0   S3C2410_GPIOREG(0x0BC)
#define S3C2412_GSTATUS1   S3C2410_GPIOREG(0x0C0)
#define S3C2412_GSTATUS2   S3C2410_GPIOREG(0x0C4)
#define S3C2412_GSTATUS3   S3C2410_GPIOREG(0x0C8)
#define S3C2412_GSTATUS4   S3C2410_GPIOREG(0x0CC)

#define S3C24XX_GSTATUS0   S3C24XX_GPIOREG2(0x0AC)
#define S3C24XX_GSTATUS1   S3C24XX_GPIOREG2(0x0B0)
#define S3C24XX_GSTATUS2   S3C24XX_GPIOREG2(0x0B4)
#define S3C24XX_GSTATUS3   S3C24XX_GPIOREG2(0x0B8)
#define S3C24XX_GSTATUS4   S3C24XX_GPIOREG2(0x0BC)

#define S3C2410_GSTATUS0_nWAIT	   (1<<3)
#define S3C2410_GSTATUS0_NCON	   (1<<2)
#define S3C2410_GSTATUS0_RnB	   (1<<1)
#define S3C2410_GSTATUS0_nBATTFLT  (1<<0)

#define S3C2410_GSTATUS1_IDMASK	   (0xffff0000)
#define S3C2410_GSTATUS1_2410	   (0x32410000)
#define S3C2410_GSTATUS1_2412	   (0x32412001)
#define S3C2410_GSTATUS1_2416	   (0x32416003)
#define S3C2410_GSTATUS1_2440	   (0x32440000)
#define S3C2410_GSTATUS1_2442	   (0x32440aaa)
/* some 2416 CPUs report this value also */
#define S3C2410_GSTATUS1_2450	   (0x32450003)

#define S3C2410_GSTATUS2_WTRESET   (1<<2)
#define S3C2410_GSTATUS2_OFFRESET  (1<<1)
#define S3C2410_GSTATUS2_PONRESET  (1<<0)

/* 2412/2413 sleep configuration registers */

#define S3C2412_GPBSLPCON	S3C2410_GPIOREG(0x1C)
#define S3C2412_GPCSLPCON	S3C2410_GPIOREG(0x2C)
#define S3C2412_GPDSLPCON	S3C2410_GPIOREG(0x3C)
#define S3C2412_GPFSLPCON	S3C2410_GPIOREG(0x5C)
#define S3C2412_GPGSLPCON	S3C2410_GPIOREG(0x6C)
#define S3C2412_GPHSLPCON	S3C2410_GPIOREG(0x7C)

/* definitions for each pin bit */
#define S3C2412_GPIO_SLPCON_LOW	 ( 0x00 )
#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 )
#define S3C2412_GPIO_SLPCON_IN   ( 0x02 )
#define S3C2412_GPIO_SLPCON_PULL ( 0x03 )

#define S3C2412_SLPCON_LOW(x)	( 0x00 << ((x) * 2))
#define S3C2412_SLPCON_HIGH(x)	( 0x01 << ((x) * 2))
#define S3C2412_SLPCON_IN(x)	( 0x02 << ((x) * 2))
#define S3C2412_SLPCON_PULL(x)	( 0x03 << ((x) * 2))
#define S3C2412_SLPCON_EINT(x)	( 0x02 << ((x) * 2))  /* only IRQ pins */
#define S3C2412_SLPCON_MASK(x)	( 0x03 << ((x) * 2))

#define S3C2412_SLPCON_ALL_LOW	(0x0)
#define S3C2412_SLPCON_ALL_HIGH	(0x11111111 | 0x44444444)
#define S3C2412_SLPCON_ALL_IN  	(0x22222222 | 0x88888888)
#define S3C2412_SLPCON_ALL_PULL	(0x33333333)

#endif	/* __ASM_ARCH_REGS_GPIO_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
 * S3C64XX - GPIO register definitions
 */

#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__

/* Base addresses for each of the banks */

#define S3C64XX_GPIOREG(reg)	(S3C64XX_VA_GPIO + (reg))

#define S3C64XX_GPA_BASE	S3C64XX_GPIOREG(0x0000)
#define S3C64XX_GPB_BASE	S3C64XX_GPIOREG(0x0020)
#define S3C64XX_GPC_BASE	S3C64XX_GPIOREG(0x0040)
#define S3C64XX_GPD_BASE	S3C64XX_GPIOREG(0x0060)
#define S3C64XX_GPE_BASE	S3C64XX_GPIOREG(0x0080)
#define S3C64XX_GPF_BASE	S3C64XX_GPIOREG(0x00A0)
#define S3C64XX_GPG_BASE	S3C64XX_GPIOREG(0x00C0)
#define S3C64XX_GPH_BASE	S3C64XX_GPIOREG(0x00E0)
#define S3C64XX_GPI_BASE	S3C64XX_GPIOREG(0x0100)
#define S3C64XX_GPJ_BASE	S3C64XX_GPIOREG(0x0120)
#define S3C64XX_GPK_BASE	S3C64XX_GPIOREG(0x0800)
#define S3C64XX_GPL_BASE	S3C64XX_GPIOREG(0x0810)
#define S3C64XX_GPM_BASE	S3C64XX_GPIOREG(0x0820)
#define S3C64XX_GPN_BASE	S3C64XX_GPIOREG(0x0830)
#define S3C64XX_GPO_BASE	S3C64XX_GPIOREG(0x0140)
#define S3C64XX_GPP_BASE	S3C64XX_GPIOREG(0x0160)
#define S3C64XX_GPQ_BASE	S3C64XX_GPIOREG(0x0180)

/* SPCON */

#define S3C64XX_SPCON		S3C64XX_GPIOREG(0x1A0)

#define S3C64XX_SPCON_DRVCON_CAM_MASK		(0x3 << 30)
#define S3C64XX_SPCON_DRVCON_CAM_SHIFT		(30)
#define S3C64XX_SPCON_DRVCON_CAM_2mA		(0x0 << 30)
#define S3C64XX_SPCON_DRVCON_CAM_4mA		(0x1 << 30)
#define S3C64XX_SPCON_DRVCON_CAM_7mA		(0x2 << 30)
#define S3C64XX_SPCON_DRVCON_CAM_9mA		(0x3 << 30)

#define S3C64XX_SPCON_DRVCON_HSSPI_MASK		(0x3 << 28)
#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT	(28)
#define S3C64XX_SPCON_DRVCON_HSSPI_2mA		(0x0 << 28)
#define S3C64XX_SPCON_DRVCON_HSSPI_4mA		(0x1 << 28)
#define S3C64XX_SPCON_DRVCON_HSSPI_7mA		(0x2 << 28)
#define S3C64XX_SPCON_DRVCON_HSSPI_9mA		(0x3 << 28)

#define S3C64XX_SPCON_DRVCON_HSMMC_MASK		(0x3 << 26)
#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT	(26)
#define S3C64XX_SPCON_DRVCON_HSMMC_2mA		(0x0 << 26)
#define S3C64XX_SPCON_DRVCON_HSMMC_4mA		(0x1 << 26)
#define S3C64XX_SPCON_DRVCON_HSMMC_7mA		(0x2 << 26)
#define S3C64XX_SPCON_DRVCON_HSMMC_9mA		(0x3 << 26)

#define S3C64XX_SPCON_DRVCON_LCD_MASK		(0x3 << 24)
#define S3C64XX_SPCON_DRVCON_LCD_SHIFT		(24)
#define S3C64XX_SPCON_DRVCON_LCD_2mA		(0x0 << 24)
#define S3C64XX_SPCON_DRVCON_LCD_4mA		(0x1 << 24)
#define S3C64XX_SPCON_DRVCON_LCD_7mA		(0x2 << 24)
#define S3C64XX_SPCON_DRVCON_LCD_9mA		(0x3 << 24)

#define S3C64XX_SPCON_DRVCON_MODEM_MASK		(0x3 << 22)
#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT	(22)
#define S3C64XX_SPCON_DRVCON_MODEM_2mA		(0x0 << 22)
#define S3C64XX_SPCON_DRVCON_MODEM_4mA		(0x1 << 22)
#define S3C64XX_SPCON_DRVCON_MODEM_7mA		(0x2 << 22)
#define S3C64XX_SPCON_DRVCON_MODEM_9mA		(0x3 << 22)

#define S3C64XX_SPCON_nRSTOUT_OEN		(1 << 21)

#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK	(0x3 << 18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT	(18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA	(0x0 << 18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA	(0x1 << 18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA	(0x2 << 18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA	(0x3 << 18)

#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK		(0x3 << 16)
#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT	(16)
#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED	(0x0 << 16)
#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN		(0x1 << 16)
#define S3C64XX_SPCON_MEM1_DQS_PUD_UP		(0x2 << 16)

#define S3C64XX_SPCON_MEM1_D_PUD1_MASK		(0x3 << 14)
#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT		(14)
#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED	(0x0 << 14)
#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN		(0x1 << 14)
#define S3C64XX_SPCON_MEM1_D_PUD1_UP		(0x2 << 14)

#define S3C64XX_SPCON_MEM1_D_PUD0_MASK		(0x3 << 12)
#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT		(12)
#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED	(0x0 << 12)
#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN		(0x1 << 12)
#define S3C64XX_SPCON_MEM1_D_PUD0_UP		(0x2 << 12)

#define S3C64XX_SPCON_MEM0_D_PUD_MASK		(0x3 << 8)
#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT		(8)
#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED	(0x0 << 8)
#define S3C64XX_SPCON_MEM0_D_PUD_DOWN		(0x1 << 8)
#define S3C64XX_SPCON_MEM0_D_PUD_UP		(0x2 << 8)

#define S3C64XX_SPCON_USBH_DMPD			(1 << 7)
#define S3C64XX_SPCON_USBH_DPPD			(1 << 6)
#define S3C64XX_SPCON_USBH_PUSW2		(1 << 5)
#define S3C64XX_SPCON_USBH_PUSW1		(1 << 4)
#define S3C64XX_SPCON_USBH_SUSPND		(1 << 3)

#define S3C64XX_SPCON_LCD_SEL_MASK		(0x3 << 0)
#define S3C64XX_SPCON_LCD_SEL_SHIFT		(0)
#define S3C64XX_SPCON_LCD_SEL_HOST		(0x0 << 0)
#define S3C64XX_SPCON_LCD_SEL_RGB		(0x1 << 0)
#define S3C64XX_SPCON_LCD_SEL_606_656		(0x2 << 0)

/* External interrupt registers */

#define S3C64XX_EINT12CON	S3C64XX_GPIOREG(0x200)
#define S3C64XX_EINT34CON	S3C64XX_GPIOREG(0x204)
#define S3C64XX_EINT56CON	S3C64XX_GPIOREG(0x208)
#define S3C64XX_EINT78CON	S3C64XX_GPIOREG(0x20C)
#define S3C64XX_EINT9CON	S3C64XX_GPIOREG(0x210)

#define S3C64XX_EINT12FLTCON	S3C64XX_GPIOREG(0x220)
#define S3C64XX_EINT34FLTCON	S3C64XX_GPIOREG(0x224)
#define S3C64XX_EINT56FLTCON	S3C64XX_GPIOREG(0x228)
#define S3C64XX_EINT78FLTCON	S3C64XX_GPIOREG(0x22C)
#define S3C64XX_EINT9FLTCON	S3C64XX_GPIOREG(0x230)

#define S3C64XX_EINT12MASK	S3C64XX_GPIOREG(0x240)
#define S3C64XX_EINT34MASK	S3C64XX_GPIOREG(0x244)
#define S3C64XX_EINT56MASK	S3C64XX_GPIOREG(0x248)
#define S3C64XX_EINT78MASK	S3C64XX_GPIOREG(0x24C)
#define S3C64XX_EINT9MASK	S3C64XX_GPIOREG(0x250)

#define S3C64XX_EINT12PEND	S3C64XX_GPIOREG(0x260)
#define S3C64XX_EINT34PEND	S3C64XX_GPIOREG(0x264)
#define S3C64XX_EINT56PEND	S3C64XX_GPIOREG(0x268)
#define S3C64XX_EINT78PEND	S3C64XX_GPIOREG(0x26C)
#define S3C64XX_EINT9PEND	S3C64XX_GPIOREG(0x270)

#define S3C64XX_PRIORITY	S3C64XX_GPIOREG(0x280)
#define S3C64XX_PRIORITY_ARB(x)	(1 << (x))

#define S3C64XX_SERVICE		S3C64XX_GPIOREG(0x284)
#define S3C64XX_SERVICEPEND	S3C64XX_GPIOREG(0x288)

#define S3C64XX_EINT0CON0	S3C64XX_GPIOREG(0x900)
#define S3C64XX_EINT0CON1	S3C64XX_GPIOREG(0x904)
#define S3C64XX_EINT0FLTCON0	S3C64XX_GPIOREG(0x910)
#define S3C64XX_EINT0FLTCON1	S3C64XX_GPIOREG(0x914)
#define S3C64XX_EINT0FLTCON2	S3C64XX_GPIOREG(0x918)
#define S3C64XX_EINT0FLTCON3	S3C64XX_GPIOREG(0x91C)

#define S3C64XX_EINT0MASK	S3C64XX_GPIOREG(0x920)
#define S3C64XX_EINT0PEND	S3C64XX_GPIOREG(0x924)

/* GPIO sleep configuration */

#define S3C64XX_SPCONSLP	S3C64XX_GPIOREG(0x880)

#define S3C64XX_SPCONSLP_TDO_PULLDOWN	(1 << 14)
#define S3C64XX_SPCONSLP_CKE1INIT	(1 << 5)

#define S3C64XX_SPCONSLP_RSTOUT_MASK	(0x3 << 12)
#define S3C64XX_SPCONSLP_RSTOUT_OUT0	(0x0 << 12)
#define S3C64XX_SPCONSLP_RSTOUT_OUT1	(0x1 << 12)
#define S3C64XX_SPCONSLP_RSTOUT_HIZ	(0x2 << 12)

#define S3C64XX_SPCONSLP_KPCOL_MASK	(0x3 << 0)
#define S3C64XX_SPCONSLP_KPCOL_OUT0	(0x0 << 0)
#define S3C64XX_SPCONSLP_KPCOL_OUT1	(0x1 << 0)
#define S3C64XX_SPCONSLP_KPCOL_INP	(0x2 << 0)

#define S3C64XX_SLPEN		S3C64XX_GPIOREG(0x930)

#define S3C64XX_SLPEN_USE_xSLP		(1 << 0)
#define S3C64XX_SLPEN_CFG_BYSLPEN	(1 << 1)

#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */

#ifdef CONFIG_ARCH_S3C24XX
#include "regs-gpio-s3c24xx.h"
#endif

#ifdef CONFIG_ARCH_S3C64XX
#include "regs-gpio-s3c64xx.h"
#endif


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
 *		      http://www.simtec.co.uk/products/SWLINUX/
 */

#ifndef ___ASM_ARCH_REGS_IRQ_H
#define ___ASM_ARCH_REGS_IRQ_H

#include "map-s3c.h"

/* interrupt controller */

#define S3C2410_IRQREG(x)   ((x) + S3C24XX_VA_IRQ)
#define S3C2410_EINTREG(x)  ((x) + S3C24XX_VA_GPIO)
#define S3C24XX_EINTREG(x)  ((x) + S3C24XX_VA_GPIO2)

#define S3C2410_SRCPND	       S3C2410_IRQREG(0x000)
#define S3C2410_INTMOD	       S3C2410_IRQREG(0x004)
#define S3C2410_INTMSK	       S3C2410_IRQREG(0x008)
#define S3C2410_PRIORITY       S3C2410_IRQREG(0x00C)
#define S3C2410_INTPND	       S3C2410_IRQREG(0x010)
#define S3C2410_INTOFFSET      S3C2410_IRQREG(0x014)
#define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
#define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)

#define S3C2416_PRIORITY_MODE1		S3C2410_IRQREG(0x030)
#define S3C2416_PRIORITY_UPDATE1	S3C2410_IRQREG(0x034)
#define S3C2416_SRCPND2			S3C2410_IRQREG(0x040)
#define S3C2416_INTMOD2			S3C2410_IRQREG(0x044)
#define S3C2416_INTMSK2			S3C2410_IRQREG(0x048)
#define S3C2416_INTPND2			S3C2410_IRQREG(0x050)
#define S3C2416_INTOFFSET2		S3C2410_IRQREG(0x054)
#define S3C2416_PRIORITY_MODE2		S3C2410_IRQREG(0x070)
#define S3C2416_PRIORITY_UPDATE2	S3C2410_IRQREG(0x074)

/* mask: 0=enable, 1=disable
 * 1 bit EINT, 4=EINT4, 23=EINT23
 * EINT0,1,2,3 are not handled here.
*/

#define S3C2410_EINTMASK       S3C2410_EINTREG(0x0A4)
#define S3C2410_EINTPEND       S3C2410_EINTREG(0X0A8)
#define S3C2412_EINTMASK       S3C2410_EINTREG(0x0B4)
#define S3C2412_EINTPEND       S3C2410_EINTREG(0X0B8)

#define S3C24XX_EINTMASK       S3C24XX_EINTREG(0x0A4)
#define S3C24XX_EINTPEND       S3C24XX_EINTREG(0X0A8)

#endif /* ___ASM_ARCH_REGS_IRQ_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C64XX - IRQ register definitions
 */

#ifndef __ASM_ARCH_REGS_IRQ_H
#define __ASM_ARCH_REGS_IRQ_H __FILE__

#endif /* __ASM_ARCH_6400_REGS_IRQ_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */

#ifdef CONFIG_ARCH_S3C24XX
#include "regs-irq-s3c24xx.h"
#endif

#ifdef CONFIG_ARCH_S3C64XX
#include "regs-irq-s3c64xx.h"
#endif


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
 * S3C - IRQ detection types.
 */

/* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including
 * the S3C64XX
*/
#define S3C2410_EXTINT_LOWLEV	 (0x00)
#define S3C2410_EXTINT_HILEV	 (0x01)
#define S3C2410_EXTINT_FALLEDGE	 (0x02)
#define S3C2410_EXTINT_RISEEDGE	 (0x04)
#define S3C2410_EXTINT_BOTHEDGE	 (0x06)


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
 *		http://www.simtec.co.uk/products/SWLINUX/
 *
 * S3C2410 Memory Control register definitions
 */

#ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H
#define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__

#include "map-s3c.h"

#define S3C2410_MEMREG(x)		(S3C24XX_VA_MEMCTRL + (x))

#define S3C2410_BWSCON			S3C2410_MEMREG(0x00)
#define S3C2410_BANKCON0		S3C2410_MEMREG(0x04)
#define S3C2410_BANKCON1		S3C2410_MEMREG(0x08)
#define S3C2410_BANKCON2		S3C2410_MEMREG(0x0C)
#define S3C2410_BANKCON3		S3C2410_MEMREG(0x10)
#define S3C2410_BANKCON4		S3C2410_MEMREG(0x14)
#define S3C2410_BANKCON5		S3C2410_MEMREG(0x18)
#define S3C2410_BANKCON6		S3C2410_MEMREG(0x1C)
#define S3C2410_BANKCON7		S3C2410_MEMREG(0x20)
#define S3C2410_REFRESH			S3C2410_MEMREG(0x24)
#define S3C2410_BANKSIZE		S3C2410_MEMREG(0x28)

#define S3C2410_BWSCON_ST1		(1 << 7)
#define S3C2410_BWSCON_ST2		(1 << 11)
#define S3C2410_BWSCON_ST3		(1 << 15)
#define S3C2410_BWSCON_ST4		(1 << 19)
#define S3C2410_BWSCON_ST5		(1 << 23)

#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)

#define S3C2410_BWSCON_WS		(1 << 2)

#define S3C2410_BANKCON_PMC16		(0x3)

#define S3C2410_BANKCON_Tacp_SHIFT	(2)
#define S3C2410_BANKCON_Tcah_SHIFT	(4)
#define S3C2410_BANKCON_Tcoh_SHIFT	(6)
#define S3C2410_BANKCON_Tacc_SHIFT	(8)
#define S3C2410_BANKCON_Tcos_SHIFT	(11)
#define S3C2410_BANKCON_Tacs_SHIFT	(13)

#define S3C2410_BANKCON_SDRAM		(0x3 << 15)

#define S3C2410_REFRESH_SELF		(1 << 22)

#define S3C2410_BANKSIZE_MASK		(0x7 << 0)

#endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C64XX - modem block registers
 */

#ifndef __MACH_S3C64XX_REGS_MODEM_H
#define __MACH_S3C64XX_REGS_MODEM_H __FILE__

#define S3C64XX_MODEMREG(x)			(S3C64XX_VA_MODEM + (x))

#define S3C64XX_MODEM_INT2AP			S3C64XX_MODEMREG(0x0)
#define S3C64XX_MODEM_INT2MODEM			S3C64XX_MODEMREG(0x4)
#define S3C64XX_MODEM_MIFCON			S3C64XX_MODEMREG(0x8)
#define S3C64XX_MODEM_MIFPCON			S3C64XX_MODEMREG(0xC)
#define S3C64XX_MODEM_INTCLR			S3C64XX_MODEMREG(0x10)
#define S3C64XX_MODEM_DMA_TXADDR		S3C64XX_MODEMREG(0x14)
#define S3C64XX_MODEM_DMA_RXADDR		S3C64XX_MODEMREG(0x18)

#define MIFPCON_INT2M_LEVEL			(1 << 4)
#define MIFPCON_LCD_BYPASS			(1 << 3)

#endif /* __MACH_S3C64XX_REGS_MODEM_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2007 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * S3C2443 clock register definitions
 */

#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
#define __ASM_ARM_REGS_S3C2443_CLOCK

#include <linux/delay.h>
#include "map-s3c.h"

#define S3C2443_CLKREG(x)		((x) + S3C24XX_VA_CLKPWR)

#define S3C2443_PLLCON_MDIVSHIFT	16
#define S3C2443_PLLCON_PDIVSHIFT	8
#define S3C2443_PLLCON_SDIVSHIFT	0
#define S3C2443_PLLCON_MDIVMASK		((1<<(1+(23-16)))-1)
#define S3C2443_PLLCON_PDIVMASK		((1<<(1+(9-8)))-1)
#define S3C2443_PLLCON_SDIVMASK		(3)

#define S3C2443_MPLLCON			S3C2443_CLKREG(0x10)
#define S3C2443_EPLLCON			S3C2443_CLKREG(0x18)
#define S3C2443_CLKSRC			S3C2443_CLKREG(0x20)
#define S3C2443_CLKDIV0			S3C2443_CLKREG(0x24)
#define S3C2443_CLKDIV1			S3C2443_CLKREG(0x28)
#define S3C2443_HCLKCON			S3C2443_CLKREG(0x30)
#define S3C2443_PCLKCON			S3C2443_CLKREG(0x34)
#define S3C2443_SCLKCON			S3C2443_CLKREG(0x38)
#define S3C2443_PWRMODE			S3C2443_CLKREG(0x40)
#define S3C2443_SWRST			S3C2443_CLKREG(0x44)
#define S3C2443_BUSPRI0			S3C2443_CLKREG(0x50)
#define S3C2443_SYSID			S3C2443_CLKREG(0x5C)
#define S3C2443_PWRCFG			S3C2443_CLKREG(0x60)
#define S3C2443_RSTCON			S3C2443_CLKREG(0x64)
#define S3C2443_PHYCTRL			S3C2443_CLKREG(0x80)
#define S3C2443_PHYPWR			S3C2443_CLKREG(0x84)
#define S3C2443_URSTCON			S3C2443_CLKREG(0x88)
#define S3C2443_UCLKCON			S3C2443_CLKREG(0x8C)

#define S3C2443_PLLCON_OFF		(1<<24)

#define S3C2443_CLKSRC_EPLLREF_XTAL	(2<<7)
#define S3C2443_CLKSRC_EPLLREF_EXTCLK	(3<<7)
#define S3C2443_CLKSRC_EPLLREF_MPLLREF	(0<<7)
#define S3C2443_CLKSRC_EPLLREF_MPLLREF2	(1<<7)
#define S3C2443_CLKSRC_EPLLREF_MASK	(3<<7)

#define S3C2443_CLKSRC_EXTCLK_DIV	(1<<3)

#define S3C2443_CLKDIV0_HALF_HCLK	(1<<3)
#define S3C2443_CLKDIV0_HALF_PCLK	(1<<2)

#define S3C2443_CLKDIV0_HCLKDIV_MASK	(3<<0)

#define S3C2443_CLKDIV0_EXTDIV_MASK	(3<<6)
#define S3C2443_CLKDIV0_EXTDIV_SHIFT	(6)

#define S3C2443_CLKDIV0_PREDIV_MASK	(3<<4)
#define S3C2443_CLKDIV0_PREDIV_SHIFT	(4)

#define S3C2416_CLKDIV0_ARMDIV_MASK	(7 << 9)
#define S3C2443_CLKDIV0_ARMDIV_MASK	(15<<9)
#define S3C2443_CLKDIV0_ARMDIV_SHIFT	(9)
#define S3C2443_CLKDIV0_ARMDIV_1	(0<<9)
#define S3C2443_CLKDIV0_ARMDIV_2	(8<<9)
#define S3C2443_CLKDIV0_ARMDIV_3	(2<<9)
#define S3C2443_CLKDIV0_ARMDIV_4	(9<<9)
#define S3C2443_CLKDIV0_ARMDIV_6	(10<<9)
#define S3C2443_CLKDIV0_ARMDIV_8	(11<<9)
#define S3C2443_CLKDIV0_ARMDIV_12	(13<<9)
#define S3C2443_CLKDIV0_ARMDIV_16	(15<<9)

/* S3C2443_CLKDIV1 removed, only used in clock.c code */

#define S3C2443_CLKCON_NAND

#define S3C2443_HCLKCON_DMA0		(1<<0)
#define S3C2443_HCLKCON_DMA1		(1<<1)
#define S3C2443_HCLKCON_DMA2		(1<<2)
#define S3C2443_HCLKCON_DMA3		(1<<3)
#define S3C2443_HCLKCON_DMA4		(1<<4)
#define S3C2443_HCLKCON_DMA5		(1<<5)
#define S3C2443_HCLKCON_CAMIF		(1<<8)
#define S3C2443_HCLKCON_LCDC		(1<<9)
#define S3C2443_HCLKCON_USBH		(1<<11)
#define S3C2443_HCLKCON_USBD		(1<<12)
#define S3C2416_HCLKCON_HSMMC0		(1<<15)
#define S3C2443_HCLKCON_HSMMC		(1<<16)
#define S3C2443_HCLKCON_CFC		(1<<17)
#define S3C2443_HCLKCON_SSMC		(1<<18)
#define S3C2443_HCLKCON_DRAMC		(1<<19)

#define S3C2443_PCLKCON_UART0		(1<<0)
#define S3C2443_PCLKCON_UART1		(1<<1)
#define S3C2443_PCLKCON_UART2		(1<<2)
#define S3C2443_PCLKCON_UART3		(1<<3)
#define S3C2443_PCLKCON_IIC		(1<<4)
#define S3C2443_PCLKCON_SDI		(1<<5)
#define S3C2443_PCLKCON_HSSPI		(1<<6)
#define S3C2443_PCLKCON_ADC		(1<<7)
#define S3C2443_PCLKCON_AC97		(1<<8)
#define S3C2443_PCLKCON_IIS		(1<<9)
#define S3C2443_PCLKCON_PWMT		(1<<10)
#define S3C2443_PCLKCON_WDT		(1<<11)
#define S3C2443_PCLKCON_RTC		(1<<12)
#define S3C2443_PCLKCON_GPIO		(1<<13)
#define S3C2443_PCLKCON_SPI0		(1<<14)
#define S3C2443_PCLKCON_SPI1		(1<<15)

#define S3C2443_SCLKCON_DDRCLK		(1<<16)
#define S3C2443_SCLKCON_SSMCCLK		(1<<15)
#define S3C2443_SCLKCON_HSSPICLK	(1<<14)
#define S3C2443_SCLKCON_HSMMCCLK_EXT	(1<<13)
#define S3C2443_SCLKCON_HSMMCCLK_EPLL	(1<<12)
#define S3C2443_SCLKCON_CAMCLK		(1<<11)
#define S3C2443_SCLKCON_DISPCLK		(1<<10)
#define S3C2443_SCLKCON_I2SCLK		(1<<9)
#define S3C2443_SCLKCON_UARTCLK		(1<<8)
#define S3C2443_SCLKCON_USBHOST		(1<<1)

#define S3C2443_PWRCFG_SLEEP		(1<<15)

#define S3C2443_PWRCFG_USBPHY		(1 << 4)

#define S3C2443_URSTCON_FUNCRST		(1 << 2)
#define S3C2443_URSTCON_PHYRST		(1 << 0)

#define S3C2443_PHYCTRL_CLKSEL		(1 << 3)
#define S3C2443_PHYCTRL_EXTCLK		(1 << 2)
#define S3C2443_PHYCTRL_PLLSEL		(1 << 1)
#define S3C2443_PHYCTRL_DSPORT		(1 << 0)

#define S3C2443_PHYPWR_COMMON_ON	(1 << 31)
#define S3C2443_PHYPWR_ANALOG_PD	(1 << 4)
#define S3C2443_PHYPWR_PLL_REFCLK	(1 << 3)
#define S3C2443_PHYPWR_XO_ON		(1 << 2)
#define S3C2443_PHYPWR_PLL_PWRDN	(1 << 1)
#define S3C2443_PHYPWR_FSUSPEND		(1 << 0)

#define S3C2443_UCLKCON_DETECT_VBUS	(1 << 31)
#define S3C2443_UCLKCON_FUNC_CLKEN	(1 << 2)
#define S3C2443_UCLKCON_TCLKEN		(1 << 0)

#include <asm/div64.h>

static inline unsigned int
s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
{
	unsigned int mdiv, pdiv, sdiv;
	uint64_t fvco;

	mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
	pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
	sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;

	mdiv &= S3C2443_PLLCON_MDIVMASK;
	pdiv &= S3C2443_PLLCON_PDIVMASK;
	sdiv &= S3C2443_PLLCON_SDIVMASK;

	fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
	do_div(fvco, pdiv << sdiv);

	return (unsigned int)fvco;
}

static inline unsigned int
s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
{
	unsigned int mdiv, pdiv, sdiv;
	uint64_t fvco;

	mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
	pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
	sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;

	mdiv &= S3C2443_PLLCON_MDIVMASK;
	pdiv &= S3C2443_PLLCON_PDIVMASK;
	sdiv &= S3C2443_PLLCON_SDIVMASK;

	fvco = (uint64_t)baseclk * (mdiv + 8);
	do_div(fvco, (pdiv + 2) << sdiv);

	return (unsigned int)fvco;
}

static inline void s3c_hsudc_init_phy(void)
{
	u32 cfg;

	cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
	writel(cfg, S3C2443_PWRCFG);

	cfg = readl(S3C2443_URSTCON);
	cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
	writel(cfg, S3C2443_URSTCON);
	mdelay(1);

	cfg = readl(S3C2443_URSTCON);
	cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
	writel(cfg, S3C2443_URSTCON);

	cfg = readl(S3C2443_PHYCTRL);
	cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
	cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
	writel(cfg, S3C2443_PHYCTRL);

	cfg = readl(S3C2443_PHYPWR);
	cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
		S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
		S3C2443_PHYPWR_ANALOG_PD);
	cfg |= S3C2443_PHYPWR_COMMON_ON;
	writel(cfg, S3C2443_PHYPWR);

	cfg = readl(S3C2443_UCLKCON);
	cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
		S3C2443_UCLKCON_TCLKEN);
	writel(cfg, S3C2443_UCLKCON);
}

static inline void s3c_hsudc_uninit_phy(void)
{
	u32 cfg;

	cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
	writel(cfg, S3C2443_PWRCFG);

	writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);

	cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
	writel(cfg, S3C2443_UCLKCON);
}

#endif /*  __ASM_ARM_REGS_S3C2443_CLOCK */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2009 Andy Green <andy@warmcat.com>
 *
 * S3C64XX SROM definitions
 */

#ifndef __MACH_S3C64XX_REGS_SROM_H
#define __MACH_S3C64XX_REGS_SROM_H __FILE__

#define S3C64XX_SROMREG(x)	(S3C_VA_MEM + (x))

#define S3C64XX_SROM_BW		S3C64XX_SROMREG(0)
#define S3C64XX_SROM_BC0	S3C64XX_SROMREG(4)
#define S3C64XX_SROM_BC1	S3C64XX_SROMREG(8)
#define S3C64XX_SROM_BC2	S3C64XX_SROMREG(0xc)
#define S3C64XX_SROM_BC3	S3C64XX_SROMREG(0x10)
#define S3C64XX_SROM_BC4	S3C64XX_SROMREG(0x14)
#define S3C64XX_SROM_BC5	S3C64XX_SROMREG(0x18)

/*
 * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4
 */

#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT	0
#define S3C64XX_SROM_BW__WAITENABLE__SHIFT	2
#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT	3
#define S3C64XX_SROM_BW__CS_MASK		0xf

#define S3C64XX_SROM_BW__NCS0__SHIFT	0
#define S3C64XX_SROM_BW__NCS1__SHIFT	4
#define S3C64XX_SROM_BW__NCS2__SHIFT	8
#define S3C64XX_SROM_BW__NCS3__SHIFT	0xc
#define S3C64XX_SROM_BW__NCS4__SHIFT	0x10

/*
 * applies to same to BCS0 - BCS4
 */

#define S3C64XX_SROM_BCX__PMC__SHIFT	0
#define S3C64XX_SROM_BCX__PMC__MASK	3
#define S3C64XX_SROM_BCX__TACP__SHIFT	4
#define S3C64XX_SROM_BCX__TACP__MASK	0xf
#define S3C64XX_SROM_BCX__TCAH__SHIFT	8
#define S3C64XX_SROM_BCX__TCAH__MASK	0xf
#define S3C64XX_SROM_BCX__TCOH__SHIFT	12
#define S3C64XX_SROM_BCX__TCOH__MASK	0xf
#define S3C64XX_SROM_BCX__TACC__SHIFT	16
#define S3C64XX_SROM_BCX__TACC__MASK	0x1f
#define S3C64XX_SROM_BCX__TCOS__SHIFT	24
#define S3C64XX_SROM_BCX__TCOS__MASK	0xf
#define S3C64XX_SROM_BCX__TACS__SHIFT	28
#define S3C64XX_SROM_BCX__TACS__MASK	0xf

#endif /* __MACH_S3C64XX_REGS_SROM_H */


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * S3C64XX system register definitions
*/

#ifndef __MACH_S3C64XX_REGS_SYS_H
#define __MACH_S3C64XX_REGS_SYS_H __FILE__

#define S3C_SYSREG(x)			(S3C_VA_SYS + (x))

#define S3C64XX_AHB_CON0		S3C_SYSREG(0x100)
#define S3C64XX_AHB_CON1		S3C_SYSREG(0x104)
#define S3C64XX_AHB_CON2		S3C_SYSREG(0x108)

#define S3C64XX_SDMA_SEL		S3C_SYSREG(0x110)

#define S3C64XX_OTHERS			S3C_SYSREG(0x900)

#define S3C64XX_OTHERS_USBMASK		(1 << 16)
#define S3C64XX_OTHERS_SYNCMUXSEL	(1 << 6)

#endif /* __MACH_S3C64XX_REGS_SYS_H */


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C64XX - syscon power and sleep control registers
*/

#ifndef __MACH_S3C64XX_REGS_SYSCON_POWER_H
#define __MACH_S3C64XX_REGS_SYSCON_POWER_H __FILE__

#define S3C64XX_PWR_CFG				S3C_SYSREG(0x804)

#define S3C64XX_PWRCFG_OSC_OTG_DISABLE		(1 << 17)
#define S3C64XX_PWRCFG_MMC2_DISABLE		(1 << 16)
#define S3C64XX_PWRCFG_MMC1_DISABLE		(1 << 15)
#define S3C64XX_PWRCFG_MMC0_DISABLE		(1 << 14)
#define S3C64XX_PWRCFG_HSI_DISABLE		(1 << 13)
#define S3C64XX_PWRCFG_TS_DISABLE		(1 << 12)
#define S3C64XX_PWRCFG_RTC_TICK_DISABLE		(1 << 11)
#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE	(1 << 10)
#define S3C64XX_PWRCFG_MSM_DISABLE		(1 << 9)
#define S3C64XX_PWRCFG_KEY_DISABLE		(1 << 8)
#define S3C64XX_PWRCFG_BATF_DISABLE		(1 << 7)

#define S3C64XX_PWRCFG_CFG_WFI_MASK		(0x3 << 5)
#define S3C64XX_PWRCFG_CFG_WFI_SHIFT		(5)
#define S3C64XX_PWRCFG_CFG_WFI_IGNORE		(0x0 << 5)
#define S3C64XX_PWRCFG_CFG_WFI_IDLE		(0x1 << 5)
#define S3C64XX_PWRCFG_CFG_WFI_STOP		(0x2 << 5)
#define S3C64XX_PWRCFG_CFG_WFI_SLEEP		(0x3 << 5)

#define S3C64XX_PWRCFG_CFG_BATFLT_MASK		(0x3 << 3)
#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT		(3)
#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE	(0x0 << 3)
#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ		(0x1 << 3)
#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP		(0x3 << 3)

#define S3C64XX_PWRCFG_CFG_BAT_WAKE		(1 << 2)
#define S3C64XX_PWRCFG_OSC27_EN			(1 << 0)

#define S3C64XX_EINT_MASK			S3C_SYSREG(0x808)

#define S3C64XX_NORMAL_CFG			S3C_SYSREG(0x810)

#define S3C64XX_NORMALCFG_IROM_ON		(1 << 30)
#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON		(1 << 16)
#define S3C64XX_NORMALCFG_DOMAIN_S_ON		(1 << 15)
#define S3C64XX_NORMALCFG_DOMAIN_F_ON		(1 << 14)
#define S3C64XX_NORMALCFG_DOMAIN_P_ON		(1 << 13)
#define S3C64XX_NORMALCFG_DOMAIN_I_ON		(1 << 12)
#define S3C64XX_NORMALCFG_DOMAIN_G_ON		(1 << 10)
#define S3C64XX_NORMALCFG_DOMAIN_V_ON		(1 << 9)

#define S3C64XX_STOP_CFG			S3C_SYSREG(0x814)

#define S3C64XX_STOPCFG_MEMORY_ARM_ON		(1 << 29)
#define S3C64XX_STOPCFG_TOP_MEMORY_ON		(1 << 20)
#define S3C64XX_STOPCFG_ARM_LOGIC_ON		(1 << 17)
#define S3C64XX_STOPCFG_TOP_LOGIC_ON		(1 << 8)
#define S3C64XX_STOPCFG_OSC_EN			(1 << 0)

#define S3C64XX_SLEEP_CFG			S3C_SYSREG(0x818)

#define S3C64XX_SLEEPCFG_OSC_EN			(1 << 0)

#define S3C64XX_STOP_MEM_CFG			S3C_SYSREG(0x81c)

#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN	(1 << 6)
#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN	(1 << 5)
#define S3C64XX_STOPMEMCFG_OTG_RETAIN		(1 << 4)
#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN		(1 << 3)
#define S3C64XX_STOPMEMCFG_IROM_RETAIN		(1 << 2)
#define S3C64XX_STOPMEMCFG_IRDA_RETAIN		(1 << 1)
#define S3C64XX_STOPMEMCFG_NFCON_RETAIN		(1 << 0)

#define S3C64XX_OSC_STABLE			S3C_SYSREG(0x824)
#define S3C64XX_PWR_STABLE			S3C_SYSREG(0x828)

#define S3C64XX_WAKEUP_STAT			S3C_SYSREG(0x908)

#define S3C64XX_WAKEUPSTAT_MMC2			(1 << 11)
#define S3C64XX_WAKEUPSTAT_MMC1			(1 << 10)
#define S3C64XX_WAKEUPSTAT_MMC0			(1 << 9)
#define S3C64XX_WAKEUPSTAT_HSI			(1 << 8)
#define S3C64XX_WAKEUPSTAT_BATFLT		(1 << 6)
#define S3C64XX_WAKEUPSTAT_MSM			(1 << 5)
#define S3C64XX_WAKEUPSTAT_KEY			(1 << 4)
#define S3C64XX_WAKEUPSTAT_TS			(1 << 3)
#define S3C64XX_WAKEUPSTAT_RTC_TICK		(1 << 2)
#define S3C64XX_WAKEUPSTAT_RTC_ALARM		(1 << 1)
#define S3C64XX_WAKEUPSTAT_EINT			(1 << 0)

#define S3C64XX_BLK_PWR_STAT			S3C_SYSREG(0x90c)

#define S3C64XX_BLKPWRSTAT_G			(1 << 7)
#define S3C64XX_BLKPWRSTAT_ETM			(1 << 6)
#define S3C64XX_BLKPWRSTAT_S			(1 << 5)
#define S3C64XX_BLKPWRSTAT_F			(1 << 4)
#define S3C64XX_BLKPWRSTAT_P			(1 << 3)
#define S3C64XX_BLKPWRSTAT_I			(1 << 2)
#define S3C64XX_BLKPWRSTAT_V			(1 << 1)
#define S3C64XX_BLKPWRSTAT_TOP			(1 << 0)

#define S3C64XX_INFORM0				S3C_SYSREG(0xA00)
#define S3C64XX_INFORM1				S3C_SYSREG(0xA04)
#define S3C64XX_INFORM2				S3C_SYSREG(0xA08)
#define S3C64XX_INFORM3				S3C_SYSREG(0xA0C)

#endif /* __MACH_S3C64XX_REGS_SYSCON_POWER_H */


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C - USB2.0 Highspeed/OtG device PHY registers
*/

/* Note, this is a separate header file as some of the clock framework
 * needs to touch this if the clk_48m is used as the USB OHCI or other
 * peripheral source.
*/

#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__

/* S3C64XX_PA_USB_HSPHY */

#define S3C_HSOTG_PHYREG(x)	((x) + S3C_VA_USB_HSPHY)

#define S3C_PHYPWR				S3C_HSOTG_PHYREG(0x00)
#define S3C_PHYPWR_NORMAL_MASK			(0x19 << 0)
#define S3C_PHYPWR_OTG_DISABLE			(1 << 4)
#define S3C_PHYPWR_ANALOG_POWERDOWN		(1 << 3)
#define SRC_PHYPWR_FORCE_SUSPEND		(1 << 1)

#define S3C_PHYCLK				S3C_HSOTG_PHYREG(0x04)
#define S3C_PHYCLK_MODE_USB11			(1 << 6)
#define S3C_PHYCLK_EXT_OSC			(1 << 5)
#define S3C_PHYCLK_CLK_FORCE			(1 << 4)
#define S3C_PHYCLK_ID_PULL			(1 << 2)
#define S3C_PHYCLK_CLKSEL_MASK			(0x3 << 0)
#define S3C_PHYCLK_CLKSEL_SHIFT			(0)
#define S3C_PHYCLK_CLKSEL_48M			(0x0 << 0)
#define S3C_PHYCLK_CLKSEL_12M			(0x2 << 0)
#define S3C_PHYCLK_CLKSEL_24M			(0x3 << 0)

#define S3C_RSTCON				S3C_HSOTG_PHYREG(0x08)
#define S3C_RSTCON_PHYCLK			(1 << 2)
#define S3C_RSTCON_HCLK				(1 << 1)
#define S3C_RSTCON_PHY				(1 << 0)

#define S3C_PHYTUNE				S3C_HSOTG_PHYREG(0x20)

#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2011 Heiko Stuebner <heiko@sntech.de>
 *
 * Samsung RTC Controller core functions
 */

#ifndef __RTC_CORE_S3C24XX_H
#define __RTC_CORE_S3C24XX_H __FILE__

/* These functions are only for use with the core support code, such as
 * the cpu specific initialisation code
 */

extern struct platform_device s3c_device_rtc;

/* re-define device name depending on support. */
static inline void s3c_rtc_setname(char *name)
{
	s3c_device_rtc.name = name;
}

#endif /* __RTC_CORE_S3C24XX_H */


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2003-2005 Simtec Electronics
//	Ben Dooks <ben@simtec.co.uk>
//
// http://www.simtec.co.uk/products/EB2410ITX/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/syscore_ops.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/io.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include "map.h"
#include "gpio-samsung.h"
#include <asm/irq.h>
#include <asm/system_misc.h>

#include "regs-clock.h"

#include "cpu.h"
#include "devs.h"
#include "pm.h"

#include "gpio-core.h"
#include "gpio-cfg.h"
#include "gpio-cfg-helpers.h"

#include "s3c24xx.h"

/* Initial IO mappings */

static struct map_desc s3c2410_iodesc[] __initdata __maybe_unused = {
	IODESC_ENT(CLKPWR),
	IODESC_ENT(TIMER),
	IODESC_ENT(WATCHDOG),
};

/* our uart devices */

/* uart registration process */

void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
	s3c24xx_init_uartdevs("s3c2410-uart", s3c2410_uart_resources, cfg, no);
}

/* s3c2410_map_io
 *
 * register the standard cpu IO areas, and any passed in from the
 * machine specific initialisation.
*/

void __init s3c2410_map_io(void)
{
	s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
	s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;

	iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
}

struct bus_type s3c2410_subsys = {
	.name = "s3c2410-core",
	.dev_name = "s3c2410-core",
};

/* Note, we would have liked to name this s3c2410-core, but we cannot
 * register two subsystems with the same name.
 */
struct bus_type s3c2410a_subsys = {
	.name = "s3c2410a-core",
	.dev_name = "s3c2410a-core",
};

static struct device s3c2410_dev = {
	.bus		= &s3c2410_subsys,
};

/* need to register the subsystem before we actually register the device, and
 * we also need to ensure that it has been initialised before any of the
 * drivers even try to use it (even if not on an s3c2410 based system)
 * as a driver which may support both 2410 and 2440 may try and use it.
*/

static int __init s3c2410_core_init(void)
{
	return subsys_system_register(&s3c2410_subsys, NULL);
}

core_initcall(s3c2410_core_init);

static int __init s3c2410a_core_init(void)
{
	return subsys_system_register(&s3c2410a_subsys, NULL);
}

core_initcall(s3c2410a_core_init);

int __init s3c2410_init(void)
{
	printk("S3C2410: Initialising architecture\n");

#ifdef CONFIG_PM_SLEEP
	register_syscore_ops(&s3c2410_pm_syscore_ops);
	register_syscore_ops(&s3c24xx_irq_syscore_ops);
#endif

	return device_register(&s3c2410_dev);
}

int __init s3c2410a_init(void)
{
	s3c2410_dev.bus = &s3c2410a_subsys;
	return s3c2410_init();
}


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 */

#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H
#define __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H __FILE__

#define S3C24XX_PWRREG(x)			((x) + S3C24XX_VA_CLKPWR)

#define S3C2412_PWRMODECON			S3C24XX_PWRREG(0x20)
#define S3C2412_PWRCFG				S3C24XX_PWRREG(0x24)

#define S3C2412_INFORM0				S3C24XX_PWRREG(0x70)
#define S3C2412_INFORM1				S3C24XX_PWRREG(0x74)
#define S3C2412_INFORM2				S3C24XX_PWRREG(0x78)
#define S3C2412_INFORM3				S3C24XX_PWRREG(0x7C)

#define S3C2412_PWRCFG_BATF_IRQ			(1 << 0)
#define S3C2412_PWRCFG_BATF_IGNORE		(2 << 0)
#define S3C2412_PWRCFG_BATF_SLEEP		(3 << 0)
#define S3C2412_PWRCFG_BATF_MASK		(3 << 0)

#define S3C2412_PWRCFG_STANDBYWFI_IGNORE	(0 << 6)
#define S3C2412_PWRCFG_STANDBYWFI_IDLE		(1 << 6)
#define S3C2412_PWRCFG_STANDBYWFI_STOP		(2 << 6)
#define S3C2412_PWRCFG_STANDBYWFI_SLEEP		(3 << 6)
#define S3C2412_PWRCFG_STANDBYWFI_MASK		(3 << 6)

#define S3C2412_PWRCFG_RTC_MASKIRQ		(1 << 8)
#define S3C2412_PWRCFG_NAND_NORST		(1 << 9)

#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_POWER_H */


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2006 Simtec Electronics
//	Ben Dooks <ben@simtec.co.uk>
//
// http://armlinux.simtec.co.uk/.

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/syscore_ops.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/reboot.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/system_misc.h>

#include "map.h"
#include "regs-clock.h"
#include "regs-gpio.h"

#include "cpu.h"
#include "devs.h"
#include "pm.h"

#include "s3c24xx.h"
#include "nand-core-s3c24xx.h"
#include "regs-dsc-s3c24xx.h"
#include "s3c2412-power.h"

#ifndef CONFIG_CPU_S3C2412_ONLY
void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;

static inline void s3c2412_init_gpio2(void)
{
	s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
}
#else
#define s3c2412_init_gpio2() do { } while(0)
#endif

/* Initial IO mappings */

static struct map_desc s3c2412_iodesc[] __initdata __maybe_unused = {
	IODESC_ENT(CLKPWR),
	IODESC_ENT(TIMER),
	IODESC_ENT(WATCHDOG),
	{
		.virtual = (unsigned long)S3C2412_VA_SSMC,
		.pfn	 = __phys_to_pfn(S3C2412_PA_SSMC),
		.length	 = SZ_1M,
		.type	 = MT_DEVICE,
	},
	{
		.virtual = (unsigned long)S3C2412_VA_EBI,
		.pfn	 = __phys_to_pfn(S3C2412_PA_EBI),
		.length	 = SZ_1M,
		.type	 = MT_DEVICE,
	},
};

/* uart registration process */

void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
	s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);

	/* rename devices that are s3c2412/s3c2413 specific */
	s3c_device_sdi.name  = "s3c2412-sdi";
	s3c_device_lcd.name  = "s3c2412-lcd";
	s3c_nand_setname("s3c2412-nand");

	/* alter IRQ of SDI controller */

	s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
	s3c_device_sdi.resource[1].end   = IRQ_S3C2412_SDI;

	/* spi channel related changes, s3c2412/13 specific */
	s3c_device_spi0.name = "s3c2412-spi";
	s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
	s3c_device_spi1.name = "s3c2412-spi";
	s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
	s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;

}

/* s3c2412_idle
 *
 * use the standard idle call by ensuring the idle mode
 * in power config, then issuing the idle co-processor
 * instruction
*/

static void s3c2412_idle(void)
{
	unsigned long tmp;

	/* ensure our idle mode is to go to idle */

	tmp = __raw_readl(S3C2412_PWRCFG);
	tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
	tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
	__raw_writel(tmp, S3C2412_PWRCFG);

	cpu_do_idle();
}

/* s3c2412_map_io
 *
 * register the standard cpu IO areas, and any passed in from the
 * machine specific initialisation.
*/

void __init s3c2412_map_io(void)
{
	/* move base of IO */

	s3c2412_init_gpio2();

	/* set our idle function */

	arm_pm_idle = s3c2412_idle;

	/* register our io-tables */

	iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
}

/* need to register the subsystem before we actually register the device, and
 * we also need to ensure that it has been initialised before any of the
 * drivers even try to use it (even if not on an s3c2412 based system)
 * as a driver which may support both 2410 and 2440 may try and use it.
*/

struct bus_type s3c2412_subsys = {
	.name = "s3c2412-core",
	.dev_name = "s3c2412-core",
};

static int __init s3c2412_core_init(void)
{
	return subsys_system_register(&s3c2412_subsys, NULL);
}

core_initcall(s3c2412_core_init);

static struct device s3c2412_dev = {
	.bus		= &s3c2412_subsys,
};

int __init s3c2412_init(void)
{
	printk("S3C2412: Initialising architecture\n");

#ifdef CONFIG_PM_SLEEP
	register_syscore_ops(&s3c2412_pm_syscore_ops);
	register_syscore_ops(&s3c24xx_irq_syscore_ops);
#endif

	return device_register(&s3c2412_dev);
}


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2008 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 */

#ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H
#define __ARCH_ARM_MACH_S3C24XX_S3C2412_H __FILE__

#include "map-s3c.h"

#define S3C2412_MEMREG(x)		(S3C24XX_VA_MEMCTRL + (x))
#define S3C2412_EBIREG(x)		(S3C2412_VA_EBI + (x))

#define S3C2412_SSMCREG(x)		(S3C2412_VA_SSMC + (x))
#define S3C2412_SSMC(x, o)		(S3C2412_SSMCREG((x * 0x20) + (o)))

#define S3C2412_REFRESH			S3C2412_MEMREG(0x10)

#define S3C2412_EBI_BANKCFG		S3C2412_EBIREG(0x4)

#define S3C2412_SSMC_BANK(x)		S3C2412_SSMC(x, 0x0)

#endif /* __ARCH_ARM_MACH_S3C24XX_S3C2412_H */


code:
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
//	as part of OpenInkpot project
// Copyright (c) 2009 Promwad Innovation Company
//	Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
//
// Samsung S3C2416 Mobile CPU support

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/device.h>
#include <linux/syscore_ops.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/reboot.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include "map.h"
#include "gpio-samsung.h"
#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/system_misc.h>

#include "regs-s3c2443-clock.h"
#include "rtc-core-s3c24xx.h"

#include "gpio-core.h"
#include "gpio-cfg.h"
#include "gpio-cfg-helpers.h"
#include "devs.h"
#include "cpu.h"
#include "sdhci.h"
#include "pm.h"

#include "iic-core.h"
#include "adc-core.h"

#include "s3c24xx.h"
#include "fb-core-s3c24xx.h"
#include "nand-core-s3c24xx.h"
#include "spi-core-s3c24xx.h"

static struct map_desc s3c2416_iodesc[] __initdata __maybe_unused = {
	IODESC_ENT(WATCHDOG),
	IODESC_ENT(CLKPWR),
	IODESC_ENT(TIMER),
};

struct bus_type s3c2416_subsys = {
	.name = "s3c2416-core",
	.dev_name = "s3c2416-core",
};

static struct device s3c2416_dev = {
	.bus		= &s3c2416_subsys,
};

int __init s3c2416_init(void)
{
	printk(KERN_INFO "S3C2416: Initializing architecture\n");

	/* change WDT IRQ number */
	s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
	s3c_device_wdt.resource[1].end   = IRQ_S3C2443_WDT;

	/* the i2c devices are directly compatible with s3c2440 */
	s3c_i2c0_setname("s3c2440-i2c");
	s3c_i2c1_setname("s3c2440-i2c");

	s3c_fb_setname("s3c2443-fb");

	s3c_adc_setname("s3c2416-adc");
	s3c_rtc_setname("s3c2416-rtc");

#ifdef CONFIG_PM_SLEEP
	register_syscore_ops(&s3c2416_pm_syscore_ops);
	register_syscore_ops(&s3c24xx_irq_syscore_ops);
	register_syscore_ops(&s3c2416_irq_syscore_ops);
#endif

	return device_register(&s3c2416_dev);
}

void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
	s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);

	s3c_nand_setname("s3c2412-nand");
}

/* s3c2416_map_io
 *
 * register the standard cpu IO areas, and any passed in from the
 * machine specific initialisation.
 */

void __init s3c2416_map_io(void)
{
	s3c24xx_gpiocfg_default.set_pull = samsung_gpio_setpull_updown;
	s3c24xx_gpiocfg_default.get_pull = samsung_gpio_getpull_updown;

	/* initialize device information early */
	s3c2416_default_sdhci0();
	s3c2416_default_sdhci1();
	s3c24xx_spi_setname("s3c2443-spi");

	iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
}

/* need to register the subsystem before we actually register the device, and
 * we also need to ensure that it has been initialised before any of the
 * drivers even try to use it (even if not on an s3c2416 based system)
 * as a driver which may support both 2443 and 2440 may try and use it.
*/

static int __init s3c2416_core_init(void)
{
	return subsys_system_register(&s3c2416_subsys, NULL);
}

core_initcall(s3c2416_core_init);


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2004-2006 Simtec Electronics
//   Ben Dooks <ben@simtec.co.uk>
//
// Samsung S3C2440 Mobile CPU support

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/device.h>
#include <linux/syscore_ops.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <asm/irq.h>

#include "devs.h"
#include "cpu.h"
#include "pm.h"

#include "gpio-core.h"
#include "gpio-cfg.h"
#include "gpio-cfg-helpers.h"
#include "gpio-samsung.h"

#include "s3c24xx.h"

static struct device s3c2440_dev = {
	.bus		= &s3c2440_subsys,
};

int __init s3c2440_init(void)
{
	printk("S3C2440: Initialising architecture\n");

	/* change irq for watchdog */

	s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
	s3c_device_wdt.resource[1].end   = IRQ_S3C2440_WDT;

	/* register suspend/resume handlers */

#ifdef CONFIG_PM_SLEEP
	register_syscore_ops(&s3c2410_pm_syscore_ops);
	register_syscore_ops(&s3c24xx_irq_syscore_ops);
	register_syscore_ops(&s3c244x_pm_syscore_ops);
#endif

	/* register our system device for everything else */

	return device_register(&s3c2440_dev);
}

void __init s3c2440_map_io(void)
{
	s3c244x_map_io();

	s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
	s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
}


code:
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (c) 2004-2005 Simtec Electronics
//	http://armlinux.simtec.co.uk/
//	Ben Dooks <ben@simtec.co.uk>
//
// S3C2442 core and lock support

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/syscore_ops.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mutex.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <linux/atomic.h>
#include <asm/irq.h>

#include "regs-clock.h"

#include "cpu.h"
#include "pm.h"

#include "gpio-core.h"
#include "gpio-cfg.h"
#include "gpio-cfg-helpers.h"
#include "gpio-samsung.h"

#include "s3c24xx.h"

static struct device s3c2442_dev = {
	.bus		= &s3c2442_subsys,
};

int __init s3c2442_init(void)
{
	printk("S3C2442: Initialising architecture\n");

#ifdef CONFIG_PM_SLEEP
	register_syscore_ops(&s3c2410_pm_syscore_ops);
	register_syscore_ops(&s3c24xx_irq_syscore_ops);
	register_syscore_ops(&s3c244x_pm_syscore_ops);
#endif

	return device_register(&s3c2442_dev);
}

void __init s3c2442_map_io(void)
{
	s3c244x_map_io();

	s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1down;
	s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1down;
}


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2007 Simtec Electronics
//   Ben Dooks <ben@simtec.co.uk>
//
// Samsung S3C2443 Mobile CPU support

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/reboot.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include "map.h"
#include "gpio-samsung.h"
#include "irqs.h"
#include <asm/irq.h>
#include <asm/system_misc.h>

#include "regs-s3c2443-clock.h"
#include "rtc-core-s3c24xx.h"

#include "gpio-core.h"
#include "gpio-cfg.h"
#include "gpio-cfg-helpers.h"
#include "devs.h"
#include "cpu.h"
#include "adc-core.h"

#include "s3c24xx.h"
#include "fb-core-s3c24xx.h"
#include "nand-core-s3c24xx.h"
#include "spi-core-s3c24xx.h"

static struct map_desc s3c2443_iodesc[] __initdata __maybe_unused = {
	IODESC_ENT(WATCHDOG),
	IODESC_ENT(CLKPWR),
	IODESC_ENT(TIMER),
};

struct bus_type s3c2443_subsys = {
	.name = "s3c2443-core",
	.dev_name = "s3c2443-core",
};

static struct device s3c2443_dev = {
	.bus		= &s3c2443_subsys,
};

int __init s3c2443_init(void)
{
	printk("S3C2443: Initialising architecture\n");

	s3c_nand_setname("s3c2412-nand");
	s3c_fb_setname("s3c2443-fb");

	s3c_adc_setname("s3c2443-adc");
	s3c_rtc_setname("s3c2443-rtc");

	/* change WDT IRQ number */
	s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
	s3c_device_wdt.resource[1].end   = IRQ_S3C2443_WDT;

	return device_register(&s3c2443_dev);
}

void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
	s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
}

/* s3c2443_map_io
 *
 * register the standard cpu IO areas, and any passed in from the
 * machine specific initialisation.
 */

void __init s3c2443_map_io(void)
{
	s3c24xx_gpiocfg_default.set_pull = s3c2443_gpio_setpull;
	s3c24xx_gpiocfg_default.get_pull = s3c2443_gpio_getpull;

	/* initialize device information early */
	s3c24xx_spi_setname("s3c2443-spi");

	iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
}

/* need to register the subsystem before we actually register the device, and
 * we also need to ensure that it has been initialised before any of the
 * drivers even try to use it (even if not on an s3c2443 based system)
 * as a driver which may support both 2443 and 2440 may try and use it.
*/

static int __init s3c2443_core_init(void)
{
	return subsys_system_register(&s3c2443_subsys, NULL);
}

core_initcall(s3c2443_core_init);


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (c) 2004-2006 Simtec Electronics
//   Ben Dooks <ben@simtec.co.uk>
//
// Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/serial_s3c.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/device.h>
#include <linux/syscore_ops.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/system_misc.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include "map.h"
#include <asm/irq.h>

#include "regs-clock.h"
#include "regs-gpio.h"

#include "devs.h"
#include "cpu.h"
#include "pm.h"

#include "s3c24xx.h"
#include "nand-core-s3c24xx.h"
#include "regs-dsc-s3c24xx.h"

static struct map_desc s3c244x_iodesc[] __initdata __maybe_unused = {
	IODESC_ENT(CLKPWR),
	IODESC_ENT(TIMER),
	IODESC_ENT(WATCHDOG),
};

/* uart initialisation */

void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
	s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
}

void __init s3c244x_map_io(void)
{
	/* register our io-tables */

	iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));

	/* rename any peripherals used differing from the s3c2410 */

	s3c_device_sdi.name  = "s3c2440-sdi";
	s3c_device_i2c0.name  = "s3c2440-i2c";
	s3c_nand_setname("s3c2440-nand");
	s3c_device_ts.name = "s3c2440-ts";
	s3c_device_usbgadget.name = "s3c2440-usbgadget";
	s3c2410_device_dclk.name = "s3c2440-dclk";
}

/* Since the S3C2442 and S3C2440 share items, put both subsystems here */

struct bus_type s3c2440_subsys = {
	.name		= "s3c2440-core",
	.dev_name	= "s3c2440-core",
};

struct bus_type s3c2442_subsys = {
	.name		= "s3c2442-core",
	.dev_name	= "s3c2442-core",
};

/* need to register the subsystem before we actually register the device, and
 * we also need to ensure that it has been initialised before any of the
 * drivers even try to use it (even if not on an s3c2440 based system)
 * as a driver which may support both 2410 and 2440 may try and use it.
*/

static int __init s3c2440_core_init(void)
{
	return subsys_system_register(&s3c2440_subsys, NULL);
}

core_initcall(s3c2440_core_init);

static int __init s3c2442_core_init(void)
{
	return subsys_system_register(&s3c2442_subsys, NULL);
}

core_initcall(s3c2442_core_init);

#ifdef CONFIG_PM_SLEEP
static struct sleep_save s3c244x_sleep[] = {
	SAVE_ITEM(S3C2440_DSC0),
	SAVE_ITEM(S3C2440_DSC1),
	SAVE_ITEM(S3C2440_GPJDAT),
	SAVE_ITEM(S3C2440_GPJCON),
	SAVE_ITEM(S3C2440_GPJUP)
};

static int s3c244x_suspend(void)
{
	s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
	return 0;
}

static void s3c244x_resume(void)
{
	s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
}

struct syscore_ops s3c244x_pm_syscore_ops = {
	.suspend	= s3c244x_suspend,
	.resume		= s3c244x_resume,
};
#endif