code:
/*
 * Broadcom BCM470X / BCM5301X ARM platform code.
 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
 *
 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include <dt-bindings/clock/bcm-nsp.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	chipcommon-a-bus@18000000 {
		compatible = "simple-bus";
		ranges = <0x00000000 0x18000000 0x00001000>;
		#address-cells = <1>;
		#size-cells = <1>;

		uart0: serial@300 {
			compatible = "ns16550";
			reg = <0x0300 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>;
			status = "disabled";
		};

		uart1: serial@400 {
			compatible = "ns16550";
			reg = <0x0400 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinmux_uart1>;
			status = "disabled";
		};
	};

	mpcore-bus@19000000 {
		compatible = "simple-bus";
		ranges = <0x00000000 0x19000000 0x00023000>;
		#address-cells = <1>;
		#size-cells = <1>;

		a9pll: arm_clk@0 {
			#clock-cells = <0>;
			compatible = "brcm,nsp-armpll";
			clocks = <&osc>;
			reg = <0x00000 0x1000>;
		};

		scu@20000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0x20000 0x100>;
		};

		timer@20200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x20200 0x100>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
			clocks = <&periph_clk>;
		};

		timer@20600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x20600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_EDGE_RISING)>;
			clocks = <&periph_clk>;
		};

		watchdog@20620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0x20620 0x20>;
			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_EDGE_RISING)>;
			clocks = <&periph_clk>;
		};

		gic: interrupt-controller@21000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x21000 0x1000>,
			      <0x20100 0x100>;
		};

		L2: cache-controller@22000 {
			compatible = "arm,pl310-cache";
			reg = <0x22000 0x1000>;
			cache-unified;
			arm,shared-override;
			prefetch-data = <1>;
			prefetch-instr = <1>;
			cache-level = <2>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts =
			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc: oscillator {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
		};

		iprocmed: iprocmed {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		iprocslow: iprocslow {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
			clock-div = <4>;
			clock-mult = <1>;
		};

		periph_clk: periph_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&a9pll>;
			clock-div = <2>;
			clock-mult = <1>;
		};
	};

	axi@18000000 {
		compatible = "brcm,bus-axi";
		reg = <0x18000000 0x1000>;
		ranges = <0x00000000 0x18000000 0x00100000>;
		#address-cells = <1>;
		#size-cells = <1>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0x000fffff 0xffff>;
		interrupt-map =
			/* ChipCommon */
			<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,

			/* Switch Register Access Block */
			<0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

			/* PCIe Controller 0 */
			<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

			/* PCIe Controller 1 */
			<0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
			<0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			<0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
			<0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
			<0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			<0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,

			/* PCIe Controller 2 */
			<0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			<0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

			/* USB 2.0 Controller */
			<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,

			/* USB 3.0 Controller */
			<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 0 */
			<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 1 */
			<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 2 */
			<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 3 */
			<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,

			/* NAND Controller */
			<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
			<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

		chipcommon: chipcommon@0 {
			reg = <0x00000000 0x1000>;

			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcie0: pcie@12000 {
			reg = <0x00012000 0x1000>;
		};

		pcie1: pcie@13000 {
			reg = <0x00013000 0x1000>;
		};

		pcie2: pcie@14000 {
			reg = <0x00014000 0x1000>;
		};

		usb2: usb2@21000 {
			reg = <0x00021000 0x1000>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			interrupt-parent = <&gic>;

			ehci: usb@21000 {
				#usb-cells = <0>;

				compatible = "generic-ehci";
				reg = <0x00021000 0x1000>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usb2_phy>;

				#address-cells = <1>;
				#size-cells = <0>;

				ehci_port1: port@1 {
					reg = <1>;
					#trigger-source-cells = <0>;
				};

				ehci_port2: port@2 {
					reg = <2>;
					#trigger-source-cells = <0>;
				};
			};

			ohci: usb@22000 {
				#usb-cells = <0>;

				compatible = "generic-ohci";
				reg = <0x00022000 0x1000>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;
				#size-cells = <0>;

				ohci_port1: port@1 {
					reg = <1>;
					#trigger-source-cells = <0>;
				};

				ohci_port2: port@2 {
					reg = <2>;
					#trigger-source-cells = <0>;
				};
			};
		};

		usb3: usb3@23000 {
			reg = <0x00023000 0x1000>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			interrupt-parent = <&gic>;

			xhci: usb@23000 {
				#usb-cells = <0>;

				compatible = "generic-xhci";
				reg = <0x00023000 0x1000>;
				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usb3_phy>;
				phy-names = "usb";

				#address-cells = <1>;
				#size-cells = <0>;

				xhci_port1: port@1 {
					reg = <1>;
					#trigger-source-cells = <0>;
				};
			};
		};

		gmac0: ethernet@24000 {
			reg = <0x24000 0x800>;
		};

		gmac1: ethernet@25000 {
			reg = <0x25000 0x800>;
		};

		gmac2: ethernet@26000 {
			reg = <0x26000 0x800>;
		};

		gmac3: ethernet@27000 {
			reg = <0x27000 0x800>;
		};
	};

	pwm: pwm@18002000 {
		compatible = "brcm,iproc-pwm";
		reg = <0x18002000 0x28>;
		clocks = <&osc>;
		#pwm-cells = <3>;
		status = "disabled";
	};

	mdio: mdio@18003000 {
		compatible = "brcm,iproc-mdio";
		reg = <0x18003000 0x8>;
		#size-cells = <0>;
		#address-cells = <1>;
	};

	mdio-mux@18003000 {
		compatible = "mdio-mux-mmioreg", "mdio-mux";
		mdio-parent-bus = <&mdio>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x18003000 0x4>;
		mux-mask = <0x200>;

		mdio@0 {
			reg = <0x0>;
			#address-cells = <1>;
			#size-cells = <0>;

			usb3_phy: usb3-phy@10 {
				compatible = "brcm,ns-ax-usb3-phy";
				reg = <0x10>;
				usb3-dmp-syscon = <&usb3_dmp>;
				#phy-cells = <0>;
				status = "disabled";
			};
		};
	};

	usb3_dmp: syscon@18105000 {
		reg = <0x18105000 0x1000>;
	};

	uart2: serial@18008000 {
		compatible = "ns16550a";
		reg = <0x18008000 0x20>;
		clocks = <&iprocslow>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		status = "disabled";
	};

	i2c0: i2c@18009000 {
		compatible = "brcm,iproc-i2c";
		reg = <0x18009000 0x50>;
		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <100000>;
		status = "disabled";
	};

	dmu-bus@1800c000 {
		compatible = "simple-bus";
		ranges = <0 0x1800c000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		cru-bus@100 {
			compatible = "brcm,ns-cru", "simple-mfd";
			reg = <0x100 0x1a4>;
			ranges;
			#address-cells = <1>;
			#size-cells = <1>;

			lcpll0: clock-controller@100 {
				#clock-cells = <1>;
				compatible = "brcm,nsp-lcpll0";
				reg = <0x100 0x14>;
				clocks = <&osc>;
				clock-output-names = "lcpll0", "pcie_phy",
						     "sdio", "ddr_phy";
			};

			genpll: clock-controller@140 {
				#clock-cells = <1>;
				compatible = "brcm,nsp-genpll";
				reg = <0x140 0x24>;
				clocks = <&osc>;
				clock-output-names = "genpll", "phy",
						     "ethernetclk",
						     "usbclk", "iprocfast",
						     "sata1", "sata2";
			};

			usb2_phy: phy@164 {
				compatible = "brcm,ns-usb2-phy";
				reg = <0x164 0x4>;
				brcm,syscon-clkset = <&cru_clkset>;
				clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
				clock-names = "phy-ref-clk";
				#phy-cells = <0>;
			};

			cru_clkset: syscon@180 {
				compatible = "brcm,cru-clkset", "syscon";
				reg = <0x180 0x4>;
			};

			pinctrl: pinctrl@1c0 {
				compatible = "brcm,bcm4708-pinmux";
				reg = <0x1c0 0x24>;
				reg-names = "cru_gpio_control";

				spi-pins {
					groups = "spi_grp";
					function = "spi";
				};

				pinmux_i2c: i2c-pins {
					groups = "i2c_grp";
					function = "i2c";
				};

				pinmux_pwm: pwm-pins {
					groups = "pwm0_grp", "pwm1_grp",
						 "pwm2_grp", "pwm3_grp";
					function = "pwm";
				};

				pinmux_uart1: uart1-pins {
					groups = "uart1_grp";
					function = "uart1";
				};
			};

			thermal: thermal@2c0 {
				compatible = "brcm,ns-thermal";
				reg = <0x2c0 0x10>;
				#thermal-sensor-cells = <0>;
			};
		};
	};

	srab: ethernet-switch@18007000 {
		compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
		reg = <0x18007000 0x1000>;

		status = "disabled";

		/* ports are defined in board DTS */
		ports {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	rng: rng@18004000 {
		compatible = "brcm,bcm5301x-rng";
		reg = <0x18004000 0x14>;
	};

	nand_controller: nand-controller@18028000 {
		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
		reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
		reg-names = "nand", "iproc-idm", "iproc-ext";
		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;
		#size-cells = <0>;

		brcm,nand-has-wp;
	};

	spi@18029200 {
		compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
		reg = <0x18029200 0x184>,
		      <0x18029000 0x124>,
		      <0x1811b408 0x004>,
		      <0x180293a0 0x01c>;
		reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "mspi_done",
				  "mspi_halted",
				  "spi_lr_fullness_reached",
				  "spi_lr_session_aborted",
				  "spi_lr_impatient",
				  "spi_lr_session_done",
				  "spi_lr_overread";
		clocks = <&iprocmed>;
		clock-names = "iprocmed";
		num-cs = <2>;
		#address-cells = <1>;
		#size-cells = <0>;

		spi_nor: flash@0 {
			compatible = "jedec,spi-nor";
			reg = <0>;
			spi-max-frequency = <20000000>;
			status = "disabled";

			partitions {
				compatible = "brcm,bcm947xx-cfe-partitions";
			};
		};
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			coefficients = <(-556) 418000>;
			thermal-sensors = <&thermal>;

			trips {
				cpu-crit {
					temperature = <125000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
			};
		};
	};
};


code:
/*
 * DTS for Unifi Switch 8 port
 *
 * Copyright (C) 2017 Florian Fainelli <f.fainelli@gmail.com>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

/dts-v1/;

#include "bcm-hr2.dtsi"

/ {
	compatible = "ubnt,unifi-switch8", "brcm,bcm53342", "brcm,hr2";
	model = "Ubiquiti UniFi Switch 8 (BCM53342)";

	/* Hurricane 2 designs use the second UART */
	chosen {
		bootargs = "console=ttyS1,115200 earlyprintk";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x08000000>,
		      <0x68000000 0x08000000>;
	};
};

&uart1 {
	status = "okay";
};

&qspi {
	status = "okay";
	bspi-sel = <0>;

	flash: flash@0 {
		compatible = "m25p80";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <12500000>;
		spi-cpol;
		spi-cpha;

		partition@0 {
			label = "u-boot";
			reg = <0x0 0xc0000>;
		};

		partition@c0000 {
			label = "u-boot-env";
			reg = <0xc0000 0x10000>;
		};

		partition@d0000 {
			label = "shmoo";
			reg = <0xd0000 0x10000>;
		};

		partition@e0000 {
			label = "kernel0";
			reg = <0xe0000 0xf00000>;
		};

		partition@fe0000 {
			label = "kernel1";
			reg = <0xfe0000 0xf10000>;
		};

		partition@1ef0000 {
			label = "cfg";
			reg = <0x1ef0000 0x100000>;
		};

		partition@1ff0000 {
			label = "EEPROM";
			reg = <0x1ff0000 0x10000>;
		};
	};
};

&pcie0 {
	/* Attaches to the internal switch */
	status = "okay";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
	};

	mpcore@18310000 {
		compatible = "simple-bus";
		ranges = <0x00000000 0x18310000 0x00008000>;
		#address-cells = <1>;
		#size-cells = <1>;

		gic: interrupt-controller@1000 {
			compatible = "arm,cortex-a7-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x1000 0x1000>,
			      <0x2000 0x0100>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		alp: oscillator {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <40000000>;
		};
	};

	axi@18000000 {
		compatible = "brcm,bus-axi";
		reg = <0x18000000 0x1000>;
		ranges = <0x00000000 0x18000000 0x00100000>;
		#address-cells = <1>;
		#size-cells = <1>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0x000fffff 0xffff>;
		interrupt-map =
			/* ChipCommon */
			<0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

			/* IEEE 802.11 0 */
			<0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

			/* PCIe Controller 0 */
			<0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			<0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			<0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			<0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			<0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			<0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

			/* USB 2.0 Controller */
			<0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 0 */
			<0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

			/* IEEE 802.11 1 */
			<0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 1 */
			<0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

		chipcommon: chipcommon@0 {
			compatible = "simple-bus";
			reg = <0x00000000 0x1000>;
			ranges;

			#address-cells = <1>;
			#size-cells = <1>;

			gpio-controller;
			#gpio-cells = <2>;

			uart0: serial@300 {
				compatible = "ns16550a";
				reg = <0x0300 0x100>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_PPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&alp>;
				status = "okay";
			};
		};

		pcie0: pcie@2000 {
			reg = <0x00002000 0x1000>;
		};

		usb2: usb2@4000 {
			reg = <0x4000 0x1000>;
			ranges;
			#address-cells = <1>;
			#size-cells = <1>;

			ehci: usb@4000 {
				compatible = "generic-ehci";
				reg = <0x4000 0x1000>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;
				#size-cells = <0>;

				ehci_port1: port@1 {
					reg = <1>;
					#trigger-source-cells = <0>;
				};

				ehci_port2: port@2 {
					reg = <2>;
					#trigger-source-cells = <0>;
				};
			};

			ohci: usb@d000 {
				#usb-cells = <0>;

				compatible = "generic-ohci";
				reg = <0xd000 0x1000>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

				#address-cells = <1>;
				#size-cells = <0>;

				ohci_port1: port@1 {
					reg = <1>;
					#trigger-source-cells = <0>;
				};

				ohci_port2: port@2 {
					reg = <2>;
					#trigger-source-cells = <0>;
				};
			};
		};

		gmac0: ethernet@5000 {
			reg = <0x5000 0x1000>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				switch: switch@1e {
					compatible = "brcm,bcm53125";
					reg = <0x1e>;

					status = "disabled";

					/* ports are defined in board DTS */
					ports {
						#address-cells = <1>;
						#size-cells = <0>;
					};
				};
			};
		};

		gmac1: ethernet@b000 {
			reg = <0xb000 0x1000>;
		};

		pmu@12000 {
			compatible = "simple-mfd", "syscon";
			reg = <0x00012000 0x00001000>;

			ilp: ilp {
				compatible = "brcm,bcm53573-ilp";
				clocks = <&alp>;
				#clock-cells = <0>;
				clock-output-names = "ilp";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2014 Linaro Limited
* Author: Matt Porter <mporter@linaro.org>
*/

&pmu {
	compatible = "brcm,bcm59056";
	regulators {
		rfldo_reg: rfldo {
		};

		camldo1_reg: camldo1 {
		};

		camldo2_reg: camldo2 {
		};

		simldo1_reg: simldo1 {
		};

		simldo2_reg: simldo2 {
		};

		sdldo_reg: sdldo {
		};

		sdxldo_reg: sdxldo {
		};

		mmcldo1_reg: mmcldo1 {
		};

		mmcldo2_reg: mmcldo2 {
		};

		audldo_reg: audldo {
		};

		micldo_reg: micldo {
		};

		usbldo_reg: usbldo {
		};

		vibldo_reg: vibldo {
		};

		csr_reg: csr {
		};

		iosr1_reg: iosr1 {
		};

		iosr2_reg: iosr2 {
		};

		msr_reg: msr {
		};

		sdsr1_reg: sdsr1 {
		};

		sdsr2_reg: sdsr2 {
		};

		vsr_reg: vsr {
		};

		gpldo1_reg: gpldo1 {
		};

		gpldo2_reg: gpldo2 {
		};

		gpldo3_reg: gpldo3 {
		};

		gpldo4_reg: gpldo4 {
		};

		gpldo5_reg: gpldo5 {
		};

		gpldo6_reg: gpldo6 {
		};

		vbus_reg: vbus {
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Broadcom BCM63138 DSL SoCs Device Tree
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "brcm,bcm63138", "brcm,bcmbca";
	model = "Broadcom BCM963138 Reference Board";
	interrupt-parent = <&gic>;

	aliases {
		uart0 = &serial0;
		uart1 = &serial1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0>;
			enable-method = "brcm,bcm63138";
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <1>;
			enable-method = "brcm,bcm63138";
			resets = <&pmb0 4 1>;
		};
	};

	clocks {
		/* UBUS peripheral clock */
		periph_clk: periph_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
			clock-output-names = "periph";
		};

		/* peripheral clock for system timer */
		axi_clk: axi_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&armpll>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		/* APB bus clock */
		apb_clk: apb_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&armpll>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	/* ARM bus */
	axi@80000000 {
		compatible = "simple-bus";
		ranges = <0 0x80000000 0x784000>;
		#address-cells = <1>;
		#size-cells = <1>;

		L2: cache-controller@1d000 {
			compatible = "arm,pl310-cache";
			reg = <0x1d000 0x1000>;
			cache-unified;
			cache-level = <2>;
			cache-size = <524288>;
			cache-sets = <1024>;
			cache-line-size = <32>;
			interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
		};

		scu: scu@1e000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0x1e000 0x100>;
		};

		gic: interrupt-controller@1f000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x1f000 0x1000
				0x1e100 0x100>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
		};

		global_timer: timer@1e200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x1e200 0x20>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
			clocks = <&axi_clk>;
		};

		local_timer: local-timer@1e600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x1e600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_EDGE_RISING)>;
			clocks = <&axi_clk>;
		};

		twd_watchdog: watchdog@1e620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0x1e620 0x20>;
			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_LEVEL_HIGH)>;
		};

		armpll: armpll@20000 {
			#clock-cells = <0>;
			compatible = "brcm,bcm63138-armpll";
			clocks = <&periph_clk>;
			reg = <0x20000 0xf00>;
		};

		pmb0: reset-controller@4800c0 {
			compatible = "brcm,bcm63138-pmb";
			reg = <0x4800c0 0x10>;
			#reset-cells = <2>;
		};

		pmb1: reset-controller@4800e0 {
			compatible = "brcm,bcm63138-pmb";
			reg = <0x4800e0 0x10>;
			#reset-cells = <2>;
		};

		ahci: sata@a000 {
			compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
			reg-names = "ahci", "top-ctrl";
			reg = <0xa000 0x9ac>, <0x8040 0x24>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			resets = <&pmb0 3 1>;
			reset-names = "ahci";
			status = "disabled";

			sata0: sata-port@0 {
				reg = <0>;
				phys = <&sata_phy0>;
			};
		};

		sata_phy: sata-phy@8100 {
			compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
			reg = <0x8100 0x1e00>;
			reg-names = "phy";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sata_phy0: sata-phy@0 {
				reg = <0>;
				#phy-cells = <0>;
			};
		};
	};

	/* Legacy UBUS base */
	ubus@fffe8000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xfffe8000 0x8100>;

		timer: timer@80 {
			compatible = "brcm,bcm6328-timer", "syscon";
			reg = <0x80 0x3c>;
		};

		serial0: serial@600 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x600 0x1b>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
			clock-names = "periph";
			status = "disabled";
		};

		serial1: serial@620 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x620 0x1b>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
			clock-names = "periph";
			status = "disabled";
		};

		nand_controller: nand-controller@2000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
			reg = <0x2000 0x600>, <0xf0 0x10>;
			reg-names = "nand", "nand-int-base";
			status = "disabled";
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "nand";
		};

		bootlut: bootlut@8000 {
			compatible = "brcm,bcm63138-bootlut";
			reg = <0x8000 0x50>;
		};

		reboot {
			compatible = "syscon-reboot";
			regmap = <&timer>;
			offset = <0x34>;
			mask = <1>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "brcm,bcm63148", "brcm,bcmbca";
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		B15_0: cpu@0 {
			device_type = "cpu";
			compatible = "brcm,brahma-b15";
			reg = <0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B15_1: cpu@1 {
			device_type = "cpu";
			compatible = "brcm,brahma-b15";
			reg = <0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu: pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&B15_0>, <&B15_1>;
	};

	clocks: clocks {
		periph_clk: periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <50000000>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@80030000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x80030000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,cortex-a15-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x1000 0x1000>,
				<0x2000 0x2000>,
				<0x4000 0x2000>,
				<0x6000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
					IRQ_TYPE_LEVEL_HIGH)>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xfffe8000 0x8000>;

		uart0: serial@600 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x600 0x20>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
			clock-names = "refclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "brcm,bcm63178", "brcm,bcmbca";
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CA7_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		CA7_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		CA7_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
		arm,cpu-registers-not-fw-configured;
	};

	pmu: pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&CA7_0>, <&CA7_1>,
			<&CA7_2>;
	};

	clocks: clocks {
		periph_clk: periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};
		uart_clk: uart-clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&periph_clk>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x81000000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,cortex-a7-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
			reg = <0x1000 0x1000>,
				<0x2000 0x2000>,
				<0x4000 0x2000>,
				<0x6000 0x2000>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xff800000 0x800000>;

		uart0: serial@12000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x12000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_clk>, <&uart_clk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "brcm,bcm6756", "brcm,bcmbca";
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CA7_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		CA7_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		CA7_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		CA7_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		arm,cpu-registers-not-fw-configured;
	};

	pmu: pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&CA7_0>, <&CA7_1>,
			<&CA7_2>, <&CA7_3>;
	};

	clocks: clocks {
		periph_clk: periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};

		uart_clk: uart-clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&periph_clk>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x81000000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,cortex-a7-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
			reg = <0x1000 0x1000>,
				<0x2000 0x2000>,
				<0x4000 0x2000>,
				<0x6000 0x2000>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xff800000 0x800000>;

		uart0: serial@12000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x12000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_clk>, <&uart_clk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "brcm,bcm6846", "brcm,bcmbca";
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CA7_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		CA7_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		arm,cpu-registers-not-fw-configured;
	};

	pmu: pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&CA7_0>, <&CA7_1>;
	};

	clocks: clocks {
		periph_clk: periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x81000000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,cortex-a7-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
			reg = <0x1000 0x1000>,
				<0x2000 0x2000>,
				<0x4000 0x2000>,
				<0x6000 0x2000>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xff800000 0x800000>;

		uart0: serial@640 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x640 0x1b>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
			clock-names = "refclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "brcm,bcm6855", "brcm,bcmbca";
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CA7_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		CA7_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		CA7_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
		arm,cpu-registers-not-fw-configured;
	};

	pmu: pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
	};

	clocks: clocks {
		periph_clk: periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};

		uart_clk: uart-clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&periph_clk>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x81000000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,cortex-a7-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
			reg = <0x1000 0x1000>,
				<0x2000 0x2000>,
				<0x4000 0x2000>,
				<0x6000 0x2000>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xff800000 0x800000>;

		uart0: serial@12000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x12000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_clk>, <&uart_clk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "brcm,bcm6878", "brcm,bcmbca";
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CA7_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		CA7_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		arm,cpu-registers-not-fw-configured;
	};

	pmu: pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&CA7_0>, <&CA7_1>;
	};

	clocks: clocks {
		periph_clk: periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};
		uart_clk: uart-clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&periph_clk>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x81000000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,cortex-a7-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x1000 0x1000>,
				<0x2000 0x2000>,
				<0x4000 0x2000>,
				<0x6000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
					IRQ_TYPE_LEVEL_HIGH)>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xff800000 0x800000>;

		uart0: serial@12000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x12000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_clk>, <&uart_clk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm7445.dtsi"

/ {
	model = "Broadcom STB (bcm7445), SVMB reference board";
	compatible = "brcm,bcm7445", "brcm,brcmstb";

	memory@0 {
		device_type = "memory";
		reg = <0x00 0x00000000 0x00 0x40000000>,
		      <0x00 0x40000000 0x00 0x40000000>,
		      <0x00 0x80000000 0x00 0x40000000>;
	};
};

&nand_controller {
	status = "okay";

	nand@1 {
		compatible = "brcm,nandcs";
		reg = <1>;
		nand-ecc-step-size = <512>;
		nand-ecc-strength = <8>;
		nand-on-flash-bbt;

		#size-cells = <2>;
		#address-cells = <2>;

		flash1.rootfs0@0 {
			reg = <0x0 0x0 0x0 0x80000000>;
		};

		flash1.rootfs1@80000000 {
			reg = <0x0 0x80000000 0x0 0x80000000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	model = "Broadcom STB (bcm7445)";
	compatible = "brcm,bcm7445", "brcm,brcmstb";
	interrupt-parent = <&gic>;

	chosen {
		bootargs = "console=ttyS0,115200 earlyprintk";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "brcm,brahma-b15";
			device_type = "cpu";
			enable-method = "brcm,brahma-b15";
			reg = <0>;
		};

		cpu@1 {
			compatible = "brcm,brahma-b15";
			device_type = "cpu";
			enable-method = "brcm,brahma-b15";
			reg = <1>;
		};

		cpu@2 {
			compatible = "brcm,brahma-b15";
			device_type = "cpu";
			enable-method = "brcm,brahma-b15";
			reg = <2>;
		};

		cpu@3 {
			compatible = "brcm,brahma-b15";
			device_type = "cpu";
			enable-method = "brcm,brahma-b15";
			reg = <3>;
		};
	};

	gic: interrupt-controller@ffd00000 {
		compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic";
		reg = <0x00 0xffd01000 0x00 0x1000>,
		      <0x00 0xffd02000 0x00 0x2000>,
		      <0x00 0xffd04000 0x00 0x2000>,
		      <0x00 0xffd06000 0x00 0x2000>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
	};

	rdb@f0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0 0x00 0xf0000000 0x1000000>;

		serial@40ab00 {
			compatible = "ns16550a";
			reg = <0x40ab00 0x20>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <81000000>;
		};

		sun_top_ctrl: syscon@404000 {
			compatible = "brcm,bcm7445-sun-top-ctrl",
				     "syscon";
			reg = <0x404000 0x51c>;
		};

		hif_cpubiuctrl: syscon@3e2400 {
			compatible = "brcm,bcm7445-hif-cpubiuctrl",
				     "syscon";
			reg = <0x3e2400 0x5b4>;
		};

		hif_continuation: syscon@452000 {
			compatible = "brcm,bcm7445-hif-continuation",
				     "syscon";
			reg = <0x452000 0x100>;
		};

		irq0_intc: interrupt-controller@40a780 {
			compatible = "brcm,bcm7120-l2-intc";
			interrupt-parent = <&gic>;
			#interrupt-cells = <1>;
			reg = <0x40a780 0x8>;
			interrupt-controller;
			interrupts = <GIC_SPI 0x45 0x0>,
				     <GIC_SPI 0x43 0x0>;
			brcm,int-map-mask = <0x25c>, <0x7000000>;
			brcm,int-fwd-mask = <0x70000>;
		};

		irq0_aon_intc: interrupt-controller@417280 {
			compatible = "brcm,bcm7120-l2-intc";
			reg = <0x417280 0x8>;
			interrupt-parent = <&gic>;
			#interrupt-cells = <1>;
			interrupt-controller;
			interrupts = <GIC_SPI 0x46 0x0>,
				     <GIC_SPI 0x44 0x0>,
				     <GIC_SPI 0x49 0x0>;
			brcm,int-map-mask = <0x1e3 0x18000000 0x100000>;
			brcm,int-fwd-mask = <0x0>;
			brcm,irq-can-wake;
		};

		hif_intr2_intc: interrupt-controller@3e1000 {
			compatible = "brcm,l2-intc";
			reg = <0x3e1000 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupts = <GIC_SPI 0x20 0x0>;
			interrupt-parent = <&gic>;
			interrupt-names = "hif";
		};

                aon_pm_l2_intc: interrupt-controller@410640 {
			compatible = "brcm,l2-intc";
			reg = <0x410640 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupts = <GIC_SPI 0x40 0x0>;
			interrupt-parent = <&gic>;
			brcm,irq-can-wake;
		};

		aon-ctrl@410000 {
			compatible = "brcm,brcmstb-aon-ctrl";
			reg = <0x410000 0x200>, <0x410200 0x400>;
			reg-names = "aon-ctrl", "aon-sram";
		};

		nand_controller: nand-controller@3e2800 {
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
			reg-names = "nand", "flash-dma";
			reg = <0x3e2800 0x600>, <0x3e3000 0x2c>;
			interrupt-parent = <&hif_intr2_intc>;
			interrupts = <24>, <4>;
			interrupt-names = "nand_ctlrdy", "flash_dma_done";
		};

		sata@45a000 {
			compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
			reg-names = "ahci", "top-ctrl";
			reg = <0x45a000 0xa9c>, <0x458040 0x24>;
			interrupts = <GIC_SPI 30 0>;
			#address-cells = <1>;
			#size-cells = <0>;

			sata0: sata-port@0 {
				reg = <0>;
				phys = <&sata_phy0>;
			};

			sata1: sata-port@1 {
				reg = <1>;
				phys = <&sata_phy1>;
			};
		};

		sata_phy: sata-phy@458100 {
			compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
			reg = <0x458100 0x1f00>;
			reg-names = "phy";
			#address-cells = <0x1>;
			#size-cells = <0x0>;

			sata_phy0: sata-phy@0 {
				reg = <0>;
				#phy-cells = <0>;
			};

			sata_phy1: sata-phy@1 {
				reg = <1>;
				#phy-cells = <0>;
			};
		};

		upg_gio: gpio@40a700 {
			compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
			reg = <0x40a700 0x80>;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupt-parent = <&irq0_intc>;
			interrupts = <6>;
			brcm,gpio-bank-widths = <32 32 32 24>;
		};

		upg_gio_aon: gpio@4172c0 {
			compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
			reg = <0x4172c0 0x40>;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupts-extended = <&irq0_aon_intc 0x6>,
					      <&aon_pm_l2_intc 0x5>;
			wakeup-source;
			brcm,gpio-bank-widths = <18 4>;
		};

	};

	memory_controllers@f1100000 {
		compatible = "simple-bus";
		ranges = <0x0 0x0 0xf1100000 0x200000>;
		#address-cells = <1>;
		#size-cells = <1>;

		memc@0 {
			compatible = "brcm,brcmstb-memc", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x80000>;

			memc-ddr@2000 {
				compatible = "brcm,brcmstb-memc-ddr";
				reg = <0x2000 0x800>;
			};

			ddr-phy@6000 {
				compatible = "brcm,brcmstb-ddr-phy-v240.1";
				reg = <0x6000 0x21c>;
				};

			shimphy@8000 {
				compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
				reg = <0x8000 0xe4>;
			};
		};

		memc@80000 {
			compatible = "brcm,brcmstb-memc", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x80000 0x80000>;

			memc-ddr@2000 {
				compatible = "brcm,brcmstb-memc-ddr";
				reg = <0x2000 0x800>;
			};

			ddr-phy@6000 {
				compatible = "brcm,brcmstb-ddr-phy-v240.1";
				reg = <0x6000 0x21c>;
			};

			shimphy@8000 {
				compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
				reg = <0x8000 0xe4>;
			};
		};

		memc@100000 {
			compatible = "brcm,brcmstb-memc", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x100000 0x80000>;

			memc-ddr@2000 {
				compatible = "brcm,brcmstb-memc-ddr";
				reg = <0x2000 0x800>;
			};

			ddr-phy@6000 {
				compatible = "brcm,brcmstb-ddr-phy-v240.1";
				reg = <0x6000 0x21c>;
			};

			shimphy@8000 {
				compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
				reg = <0x8000 0xe4>;
			};
		};
	};

	sram@ffe00000 {
		compatible = "brcm,boot-sram", "mmio-sram";
		reg = <0x0 0xffe00000 0x0 0x10000>;
	};

	smpboot {
		compatible = "brcm,brcmstb-smpboot";
		syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
		syscon-cont = <&hif_continuation>;
	};

	reboot {
		compatible = "brcm,brcmstb-reboot";
		syscon = <&sun_top_ctrl 0x304 0x308>;
	};
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm-cygnus.dtsi"
#include "dt-bindings/input/input.h"

/ {
	model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
	compatible = "brcm,bcm11360", "brcm,cygnus";

	aliases {
		serial0 = &uart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	gpio-keys {
		compatible = "gpio-keys";

		button-hook {
			label = "HOOK";
			linux,code = <KEY_O>;
			gpios = <&gpio_asiu 48 0>;
		};
	};
};

&eth0 {
	status = "okay";
};

&mdio {
	status = "okay";
};

&switch {
	status = "okay";
};

&v3d {
	assigned-clocks =
		<&mipipll BCM_CYGNUS_MIPIPLL>,
		<&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
	assigned-clock-rates = <525000000>, <300000000>;
	status = "okay";
};

&uart3 {
	status = "okay";
};

&nand_controller {
	nand@1 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <24>;
		nand-ecc-step-size = <1024>;

		brcm,nand-oob-sector-size = <27>;
	};
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm-cygnus.dtsi"

/ {
	model = "Cygnus SVK (BCM911360K)";
	compatible = "brcm,bcm11360", "brcm,cygnus";

	aliases {
		serial0 = &uart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&uart3 {
	status = "okay";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm4708.dtsi"

/ {
	model = "NorthStar SVK (BCM94708)";
	compatible = "brcm,bcm94708", "brcm,bcm4708";

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x08000000>;
	};
};

&usb3_phy {
	status = "okay";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm4708.dtsi"

/ {
	model = "NorthStar SVK (BCM94709)";
	compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708";

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x08000000>;
	};
};

&usb3_phy {
	status = "okay";
};


code:
/*
 * Copyright (C) 2017 Broadcom
 * Author: Florian Fainelli <f.fainelli@gmail.com>
 *
 * Licensed under the ISC license.
 */

/dts-v1/;

#include "bcm53573.dtsi"

/ {
	compatible = "brcm,bcm947189acdbmr", "brcm,bcm47189", "brcm,bcm53573";
	model = "Broadcom BCM947189ACDBMR";

	chosen {
		bootargs = "console=ttyS0,115200 earlycon";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x08000000>;
	};

	leds {
		compatible = "gpio-leds";

		led-wps {
			label = "bcm53xx:blue:wps";
			gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
		};

		led-5ghz {
			label = "bcm53xx:blue:5ghz";
			gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
		};

		led-2ghz {
			label = "bcm53xx:blue:2ghz";
			gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		button-restart {
			label = "Reset";
			linux,code = <KEY_RESTART>;
			gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
		};

		button-wps {
			label = "WPS";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
		};
	};

	spi {
		compatible = "spi-gpio";
		num-chipselects = <1>;
		gpio-sck = <&chipcommon 21 0>;
		gpio-miso = <&chipcommon 22 0>;
		gpio-mosi = <&chipcommon 23 0>;
		cs-gpios = <&chipcommon 24 0>;
		#address-cells = <1>;
		#size-cells = <0>;

		/* External BCM6802 MoCA chip is connected */
	};
};

&pcie0 {
	ranges = <0x00000000 0 0 0 0 0x00100000>;
	#address-cells = <3>;
	#size-cells = <2>;

	bridge@0,0,0 {
		reg = <0x0000 0 0 0 0>;
		ranges = <0x00000000 0 0 0 0 0 0 0x00100000>;
		#address-cells = <3>;
		#size-cells = <2>;

		wifi@0,1,0 {
			reg = <0x0000 0 0 0 0>;
			ranges = <0x00000000 0 0 0 0x00100000>;
			#address-cells = <1>;
			#size-cells = <1>;
		};
	};
};

&usb2 {
	vcc-gpio = <&chipcommon 8 GPIO_ACTIVE_HIGH>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm47622.dtsi"

/ {
	model = "Broadcom BCM947622 Reference Board";
	compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2016 Broadcom. All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm4708.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"

/ {
	model = "NorthStar Enterprise Router (BCM953012ER)";
	compatible = "brcm,bcm953012er", "brcm,bcm53012", "brcm,bcm4708";

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x8000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";

		button-wps {
			label = "WPS";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
		};

		button-restart {
			label = "Reset";
			linux,code = <KEY_RESTART>;
			gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
		};
	};
};

&spi_nor {
	status = "okay";
};

&srab {
	status = "okay";

	ports {
		port@0 {
			reg = <0>;
			label = "port0";
		};

		port@1 {
			reg = <1>;
			label = "port1";
		};

		port@5 {
			reg = <5>;
			label = "cpu";
			ethernet = <&gmac0>;
		};
	};
};

&usb3_phy {
	status = "okay";
};


code:
/*
 *  SPDX-License-Identifier: BSD-3-Clause
 *
 *  Copyright(c) 2017 Broadcom
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom nor the names of its contributors
 *      may be used to endorse or promote products derived from this
 *      software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm4708.dtsi"
#include "bcm5301x-nand-cs0-bch4.dtsi"

/ {
	model = "NorthStar HR (BCM953012HR)";
	compatible = "brcm,bcm953012hr", "brcm,bcm53012", "brcm,bcm4708";

	aliases {
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		ethernet2 = &gmac2;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;
	};
};

&nandcs {
	partition@0 {
		label = "nboot";
		reg = <0x00000000 0x00200000>;
		read-only;
	};
	partition@200000 {
		label = "nenv";
		reg = <0x00200000 0x00400000>;
	};
	partition@600000 {
		label = "nsystem";
		reg = <0x00600000 0x00a00000>;
	};
	partition@1000000 {
		label = "nrootfs";
		reg = <0x01000000 0x07000000>;
	};
};

&spi_nor {
	status = "okay";
	spi-max-frequency = <62500000>;
	m25p,default-addr-width = <3>;

	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
		label = "boot";
		reg = <0x00000000 0x000d0000>;
	};
	partition@d000 {
		label = "env";
		reg = <0x000d0000 0x00030000>;
	};
	partition@100000 {
		label = "system";
		reg = <0x00100000 0x00600000>;
	};
	partition@700000 {
		label = "rootfs";
		reg = <0x00700000 0x00900000>;
	};
};

&usb3_phy {
	status = "okay";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm4708.dtsi"

/ {
	model = "NorthStar SVK (BCM953012K)";
	compatible = "brcm,bcm953012k", "brcm,bcm53012", "brcm,bcm4708";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;
	};
};

&nand_controller {
	nand@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partition@0 {
			label = "nboot";
			reg = <0x00000000 0x00200000>;
			read-only;
		};
		partition@200000 {
			label = "nenv";
			reg = <0x00200000 0x00400000>;
		};
		partition@600000 {
			label = "nsystem";
			reg = <0x00600000 0x00a00000>;
		};
		partition@1000000 {
			label = "nrootfs";
			reg = <0x01000000 0x07000000>;
		};
	};
};

&spi_nor {
	status = "okay";
	spi-max-frequency = <62500000>;
	m25p,default-addr-width = <3>;

	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
		label = "boot";
		reg = <0x00000000 0x000d0000>;
	};
	partition@d000 {
		label = "env";
		reg = <0x000d0000 0x00030000>;
	};
	partition@100000 {
		label = "system";
		reg = <0x00100000 0x00600000>;
	};
	partition@700000 {
		label = "rootfs";
		reg = <0x00700000 0x00900000>;
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&usb3_phy {
	status = "okay";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm-cygnus.dtsi"
#include "bcm9hmidc.dtsi"

/ {
	model = "Cygnus SVK (BCM958300K)";
	compatible = "brcm,bcm58300", "brcm,cygnus";

	aliases {
		serial0 = &uart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&nand_controller {
	nand@1 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <24>;
		nand-ecc-step-size = <1024>;

		brcm,nand-oob-sector-size = <27>;
	};
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm-cygnus.dtsi"
#include "bcm9hmidc.dtsi"

/ {
	model = "Cygnus Wireless Audio (BCM958305K)";
	compatible = "brcm,bcm58305", "brcm,cygnus";

	aliases {
		serial0 = &uart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&nand_controller {
	nand@1 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <24>;
		nand-ecc-step-size = <1024>;

		brcm,nand-oob-sector-size = <27>;
	};
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2016 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm-nsp.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "NorthStar Plus SVK (BCM958522ER)";
	compatible = "brcm,bcm958522er", "brcm,bcm58522", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x80000000>;
	};

	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
		open-source;
		priority = <200>;
	};
};

/* USB 3 support needed to be complete */

&dma {
	status = "okay";
};

&amac0 {
	status = "okay";
};

&amac1 {
	status = "okay";
};

&ehci0 {
	status = "okay";
};

&nand_controller {
	nand@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <24>;
		nand-ecc-step-size = <1024>;

		brcm,nand-oob-sector-size = <27>;

		partition@0 {
			label = "nboot";
			reg = <0x00000000 0x00200000>;
			read-only;
		};
		partition@200000 {
			label = "nenv";
			reg = <0x00200000 0x00400000>;
		};
		partition@600000 {
			label = "nsystem";
			reg = <0x00600000 0x00a00000>;
		};
		partition@1000000 {
			label = "nrootfs";
			reg = <0x01000000 0x03000000>;
		};
		partition@4000000 {
			label = "ncustfs";
			reg = <0x04000000 0x3c000000>;
		};
	};
};

&ohci0 {
	status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <&nand_sel>;
	nand_sel: nand_sel {
		function = "nand";
		groups = "nand_grp";
	};
};

&qspi {
	status = "okay";
	bspi-sel = <0>;
	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p80";
		reg = <0x0>;
		spi-max-frequency = <12500000>;
		m25p,fast-read;
		spi-cpol;
		spi-cpha;

		partition@0 {
			label = "boot";
			reg = <0x00000000 0x000a0000>;
		};

		partition@a0000 {
			label = "env";
			reg = <0x000a0000 0x00060000>;
		};

		partition@100000 {
			label = "system";
			reg = <0x00100000 0x00600000>;
		};

		partition@700000 {
			label = "rootfs";
			reg = <0x00700000 0x01900000>;
		};
	};
};

&uart0 {
	status = "okay";
};

&usb3_phy {
	status = "okay";
};

&xhci {
	status = "okay";
};

&srab {
	compatible = "brcm,bcm58522-srab", "brcm,nsp-srab";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2016 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm-nsp.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "NorthStar Plus SVK (BCM958525ER)";
	compatible = "brcm,bcm958525er", "brcm,bcm58525", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x80000000>;
	};

	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
		open-source;
		priority = <200>;
	};
};

/* USB 3 support needed to be complete */

&dma {
	status = "okay";
};

&amac0 {
	status = "okay";
};

&amac1 {
	status = "okay";
};

&ehci0 {
	status = "okay";
};

&nand_controller {
	nand@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <24>;
		nand-ecc-step-size = <1024>;

		brcm,nand-oob-sector-size = <27>;

		partition@0 {
			label = "nboot";
			reg = <0x00000000 0x00200000>;
			read-only;
		};
		partition@200000 {
			label = "nenv";
			reg = <0x00200000 0x00400000>;
		};
		partition@600000 {
			label = "nsystem";
			reg = <0x00600000 0x00a00000>;
		};
		partition@1000000 {
			label = "nrootfs";
			reg = <0x01000000 0x03000000>;
		};
		partition@4000000 {
			label = "ncustfs";
			reg = <0x04000000 0x3c000000>;
		};
	};
};

&ohci0 {
	status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <&nand_sel>;
	nand_sel: nand_sel {
		function = "nand";
		groups = "nand_grp";
	};
};

&qspi {
	status = "okay";
	bspi-sel = <0>;
	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p80";
		reg = <0x0>;
		spi-max-frequency = <12500000>;
		m25p,fast-read;
		spi-cpol;
		spi-cpha;

		partition@0 {
			label = "boot";
			reg = <0x00000000 0x000a0000>;
		};

		partition@a0000 {
			label = "env";
			reg = <0x000a0000 0x00060000>;
		};

		partition@100000 {
			label = "system";
			reg = <0x00100000 0x00600000>;
		};

		partition@700000 {
			label = "rootfs";
			reg = <0x00700000 0x01900000>;
		};
	};
};

&sata_phy0 {
	status = "okay";
};

&sata_phy1 {
	status = "okay";
};

&sata {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&usb3_phy {
	status = "okay";
};

&xhci {
	status = "okay";
};

&srab {
	compatible = "brcm,bcm58525-srab", "brcm,nsp-srab";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2016 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm-nsp.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "NorthStar Plus XMC (BCM958525xmc)";
	compatible = "brcm,bcm958525xmc", "brcm,bcm58525", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x40000000>;
	};

	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&gpioa 31 GPIO_ACTIVE_LOW>;
		open-source;
		priority = <200>;
	};
};

/* XHCI support needed to be complete */

&dma {
	status = "okay";
};

&amac0 {
	status = "okay";
};

&ehci0 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	temperature-sensor@4c {
		compatible = "adi,adt7461a";
		reg = <0x4c>;
	};

	eeprom@52 {
		compatible = "atmel,24c02";
		reg = <0x52>;
		pagesize = <16>;
	};

	rtc@68 {
		compatible = "st,m41t81";
		reg = <0x68>;
	};
};

&nand_controller {
	nand@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <24>;
		nand-ecc-step-size = <1024>;

		brcm,nand-oob-sector-size = <27>;

		partition@0 {
			label = "nboot";
			reg = <0x00000000 0x00200000>;
			read-only;
		};
		partition@200000 {
			label = "nenv";
			reg = <0x00200000 0x00400000>;
		};
		partition@600000 {
			label = "nsystem";
			reg = <0x00600000 0x00a00000>;
		};
		partition@1000000 {
			label = "nrootfs";
			reg = <0x01000000 0x03000000>;
		};
		partition@4000000 {
			label = "ncustfs";
			reg = <0x04000000 0x3c000000>;
		};
	};
};

&ohci0 {
	status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <&nand_sel>;
	nand_sel: nand_sel {
		function = "nand";
		groups = "nand_grp";
	};
};

&qspi {
	status = "okay";
	bspi-sel = <0>;
	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p80";
		reg = <0x0>;
		spi-max-frequency = <12500000>;
		m25p,fast-read;
		spi-cpol;
		spi-cpha;

		partition@0 {
			label = "boot";
			reg = <0x00000000 0x000a0000>;
		};

		partition@a0000 {
			label = "env";
			reg = <0x000a0000 0x00060000>;
		};

		partition@100000 {
			label = "system";
			reg = <0x00100000 0x00600000>;
		};

		partition@700000 {
			label = "rootfs";
			reg = <0x00700000 0x01900000>;
		};
	};
};

&sata_phy0 {
	status = "okay";
};

&sata_phy1 {
	status = "okay";
};

&sata {
	status = "okay";
};

&sdio {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&usb3_phy {
	status = "okay";
};

&xhci {
	status = "okay";
};

&srab {
	compatible = "brcm,bcm58525-srab", "brcm,nsp-srab";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2016 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm-nsp.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "NorthStar Plus SVK (BCM958622HR)";
	compatible = "brcm,bcm958622hr", "brcm,bcm58622", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x80000000>;
	};

	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
		open-source;
		priority = <200>;
	};
};

/* USB 3 and SLIC support needed to be complete */

&dma {
	status = "okay";
};

&amac0 {
	status = "okay";
};

&amac1 {
	status = "okay";
};

&amac2 {
	status = "okay";
};

&ehci0 {
	status = "okay";
};

&nand_controller {
	nand@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <24>;
		nand-ecc-step-size = <1024>;

		brcm,nand-oob-sector-size = <27>;

		partition@0 {
			label = "nboot";
			reg = <0x00000000 0x00200000>;
			read-only;
		};
		partition@200000 {
			label = "nenv";
			reg = <0x00200000 0x00400000>;
		};
		partition@600000 {
			label = "nsystem";
			reg = <0x00600000 0x00a00000>;
		};
		partition@1000000 {
			label = "nrootfs";
			reg = <0x01000000 0x03000000>;
		};
		partition@4000000 {
			label = "ncustfs";
			reg = <0x04000000 0x3c000000>;
		};
	};
};

&ohci0 {
	status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <&nand_sel>;
	nand_sel: nand_sel {
		function = "nand";
		groups = "nand_grp";
	};
};

&qspi {
	status = "okay";
	bspi-sel = <0>;
	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p80";
		reg = <0x0>;
		spi-max-frequency = <12500000>;
		m25p,fast-read;
		spi-cpol;
		spi-cpha;

		partition@0 {
			label = "boot";
			reg = <0x00000000 0x000a0000>;
		};

		partition@a0000 {
			label = "env";
			reg = <0x000a0000 0x00060000>;
		};

		partition@100000 {
			label = "system";
			reg = <0x00100000 0x00600000>;
		};

		partition@700000 {
			label = "rootfs";
			reg = <0x00700000 0x01900000>;
		};
	};
};

&srab {
	compatible = "brcm,bcm58622-srab", "brcm,nsp-srab";
	status = "okay";

	ports {
		port@0 {
			label = "port0";
			reg = <0>;
		};

		port@1 {
			label = "port1";
			reg = <1>;
		};

		port@2 {
			label = "port2";
			reg = <2>;
		};

		port@3 {
			label = "port3";
			reg = <3>;
		};

		port@4 {
			label = "port4";
			reg = <4>;
		};

		port@8 {
			ethernet = <&amac2>;
			label = "cpu";
			reg = <8>;
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};

&uart0 {
	status = "okay";
};

&usb3_phy {
	status = "okay";
};

&xhci {
	status = "okay";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2016 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm-nsp.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "NorthStar Plus SVK (BCM958623HR)";
	compatible = "brcm,bcm958623hr", "brcm,bcm58623", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x80000000>;
	};

	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
		open-source;
		priority = <200>;
	};
};

/* USB 3 and SLIC support needed to be complete */

&dma {
	status = "okay";
};

&amac0 {
	status = "okay";
};

&amac1 {
	status = "okay";
};

&amac2 {
	status = "okay";
};

&ehci0 {
	status = "okay";
};

&nand_controller {
	nand@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <24>;
		nand-ecc-step-size = <1024>;

		brcm,nand-oob-sector-size = <27>;

		partition@0 {
			label = "nboot";
			reg = <0x00000000 0x00200000>;
			read-only;
		};
		partition@200000 {
			label = "nenv";
			reg = <0x00200000 0x00400000>;
		};
		partition@600000 {
			label = "nsystem";
			reg = <0x00600000 0x00a00000>;
		};
		partition@1000000 {
			label = "nrootfs";
			reg = <0x01000000 0x03000000>;
		};
		partition@4000000 {
			label = "ncustfs";
			reg = <0x04000000 0x3c000000>;
		};
	};
};

&ohci0 {
	status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <&nand_sel>;
	nand_sel: nand_sel {
		function = "nand";
		groups = "nand_grp";
	};
};

&sata_phy0 {
	status = "okay";
};

&qspi {
	status = "okay";
	bspi-sel = <0>;
	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p80";
		reg = <0x0>;
		spi-max-frequency = <12500000>;
		m25p,fast-read;
		spi-cpol;
		spi-cpha;

		partition@0 {
			label = "boot";
			reg = <0x00000000 0x000a0000>;
		};

		partition@a0000 {
			label = "env";
			reg = <0x000a0000 0x00060000>;
		};

		partition@100000 {
			label = "system";
			reg = <0x00100000 0x00600000>;
		};

		partition@700000 {
			label = "rootfs";
			reg = <0x00700000 0x01900000>;
		};
	};
};

&srab {
	compatible = "brcm,bcm58623-srab", "brcm,nsp-srab";
	status = "okay";

	ports {
		port@0 {
			label = "port0";
			reg = <0>;
		};

		port@1 {
			label = "port1";
			reg = <1>;
		};

		port@2 {
			label = "port2";
			reg = <2>;
		};

		port@3 {
			label = "port3";
			reg = <3>;
		};

		port@4 {
			label = "port4";
			reg = <4>;
		};

		port@8 {
			ethernet = <&amac2>;
			label = "cpu";
			reg = <8>;
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};

&uart0 {
	status = "okay";
};

&usb3_phy {
	status = "okay";
};

&xhci {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Device Tree Bindings for Cisco Meraki MX65 series (Alamo).
 *
 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
 */

#include "bcm958625-meraki-mx6x-common.dtsi"

/ {
	keys {
		compatible = "gpio-keys-polled";
		autorepeat;
		poll-interval = <20>;

		button-reset {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led-0 {
			/* green:wan1-left */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <0>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
		};

		led-1 {
			/* green:wan1-right */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <1>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
		};

		led-2 {
			/* green:wan2-left */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <2>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
		};

		led-3 {
			/* green:wan2-right */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <3>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
		};

		led-4 {
			/* amber:power */
			function = LED_FUNCTION_FAULT;
			color = <LED_COLOR_ID_AMBER>;
			gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
		};

		led-5 {
			/* white:status */
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_WHITE>;
			gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
		};
	};
};

&axi {
	mdio-mux@3f1c0 {
		compatible = "mdio-mux-mmioreg", "mdio-mux";
		reg = <0x3f1c0 0x4>;
		mux-mask = <0x2000>;
		mdio-parent-bus = <&mdio_ext>;
		#address-cells = <1>;
		#size-cells = <0>;

		mdio@0 {
			reg = <0x0>;
			#address-cells = <1>;
			#size-cells = <0>;

			phy_port6: phy@0 {
				reg = <0>;
			};

			phy_port7: phy@1 {
				reg = <1>;
			};

			phy_port8: phy@2 {
				reg = <2>;
			};

			phy_port9: phy@3 {
				reg = <3>;
			};

			phy_port10: phy@4 {
				reg = <4>;
			};

			switch@10 {
				compatible = "qca,qca8337";
				reg = <0x10>;
				dsa,member = <1 0>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;
					port@0 {
						reg = <0>;
						ethernet = <&sgmii1>;
						phy-mode = "sgmii";
						qca,sgmii-enable-pll;
						qca,sgmii-txclk-falling-edge;
						fixed-link {
							speed = <1000>;
							full-duplex;
						};
					};

					port@1 {
						reg = <1>;
						label = "lan8";
						phy-handle = <&phy_port6>;
					};

					port@2 {
						reg = <2>;
						label = "lan9";
						phy-handle = <&phy_port7>;
					};

					port@3 {
						reg = <3>;
						label = "lan10";
						phy-handle = <&phy_port8>;
					};

					port@4 {
						reg = <4>;
						label = "lan11";
						phy-handle = <&phy_port9>;
					};

					port@5 {
						reg = <5>;
						label = "lan12";
						phy-handle = <&phy_port10>;
					};
				};
			};
		};

		mdio-mii@2000 {
			reg = <0x2000>;
			#address-cells = <1>;
			#size-cells = <0>;

			phy_port1: phy@0 {
				reg = <0>;
			};

			phy_port2: phy@1 {
				reg = <1>;
			};

			phy_port3: phy@2 {
				reg = <2>;
			};

			phy_port4: phy@3 {
				reg = <3>;
			};

			phy_port5: phy@4 {
				reg = <4>;
			};

			switch@10 {
				compatible = "qca,qca8337";
				reg = <0x10>;
				dsa,member = <2 0>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;
					port@0 {
						reg = <0>;
						ethernet = <&sgmii0>;
						phy-mode = "sgmii";
						qca,sgmii-enable-pll;
						qca,sgmii-txclk-falling-edge;
						fixed-link {
							speed = <1000>;
							full-duplex;
						};
					};

					port@1 {
						reg = <1>;
						label = "lan3";
						phy-handle = <&phy_port1>;
					};

					port@2 {
						reg = <2>;
						label = "lan4";
						phy-handle = <&phy_port2>;
					};

					port@3 {
						reg = <3>;
						label = "lan5";
						phy-handle = <&phy_port3>;
					};

					port@4 {
						reg = <4>;
						label = "lan6";
						phy-handle = <&phy_port4>;
					};

					port@5 {
						reg = <5>;
						label = "lan7";
						phy-handle = <&phy_port5>;
					};
				};
			};
		};
	};
};

&srab {
	compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
	status = "okay";
	dsa,member = <0 0>;

	ports {
		port@0 {
			label = "wan1";
			reg = <0>;
		};

		port@1 {
			label = "wan2";
			reg = <1>;
		};

		sgmii0: port@4 {
			label = "sw0";
			reg = <4>;
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};

		sgmii1: port@5 {
			label = "sw1";
			reg = <5>;
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};

		port@8 {
			ethernet = <&amac2>;
			reg = <8>;
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};