code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Support for HP iPAQ hx4700 PDAs.
 *
 * Copyright (c) 2008-2009 Philipp Zabel
 *
 * Based on code:
 *    Copyright (c) 2004 Hewlett-Packard Company.
 *    Copyright (c) 2005 SDG Systems, LLC
 *    Copyright (c) 2006 Anton Vorontsov <cbou@mail.ru>
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/gpio/machine.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/input/navpoint.h>
#include <linux/lcd.h>
#include <linux/mfd/asic3.h>
#include <linux/mtd/physmap.h>
#include <linux/pda_power.h>
#include <linux/platform_data/gpio-htc-egpio.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/gpio-regulator.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/max1586.h>
#include <linux/spi/ads7846.h>
#include <linux/spi/spi.h>
#include <linux/spi/pxa2xx_spi.h>
#include <linux/platform_data/i2c-pxa.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>

#include "pxa27x.h"
#include "addr-map.h"
#include "hx4700.h"
#include <linux/platform_data/irda-pxaficp.h>

#include <sound/ak4641.h>
#include <video/platform_lcd.h>
#include <video/w100fb.h>

#include "devices.h"
#include "generic.h"
#include "udc.h"

/* Physical address space information */

#define ATI_W3220_PHYS  PXA_CS2_PHYS /* ATI Imageon 3220 Graphics */
#define ASIC3_PHYS      PXA_CS3_PHYS
#define ASIC3_SD_PHYS   (PXA_CS3_PHYS + 0x02000000)

static unsigned long hx4700_pin_config[] __initdata = {

	/* SDRAM and Static Memory I/O Signals */
	GPIO20_nSDCS_2,
	GPIO21_nSDCS_3,
	GPIO15_nCS_1,
	GPIO78_nCS_2,   /* W3220 */
	GPIO79_nCS_3,   /* ASIC3 */
	GPIO80_nCS_4,
	GPIO33_nCS_5,	/* EGPIO, WLAN */

	/* PC CARD */
	GPIO48_nPOE,
	GPIO49_nPWE,
	GPIO50_nPIOR,
	GPIO51_nPIOW,
	GPIO54_nPCE_2,
	GPIO55_nPREG,
	GPIO56_nPWAIT,
	GPIO57_nIOIS16,
	GPIO85_nPCE_1,
	GPIO104_PSKTSEL,

	/* I2C */
	GPIO117_I2C_SCL,
	GPIO118_I2C_SDA,

	/* FFUART (RS-232) */
	GPIO34_FFUART_RXD,
	GPIO35_FFUART_CTS,
	GPIO36_FFUART_DCD,
	GPIO37_FFUART_DSR,
	GPIO38_FFUART_RI,
	GPIO39_FFUART_TXD,
	GPIO40_FFUART_DTR,
	GPIO41_FFUART_RTS,

	/* BTUART */
	GPIO42_BTUART_RXD,
	GPIO43_BTUART_TXD_LPM_LOW,
	GPIO44_BTUART_CTS,
	GPIO45_BTUART_RTS_LPM_LOW,

	/* STUART (IRDA) */
	GPIO46_STUART_RXD,
	GPIO47_STUART_TXD,

	/* PWM 1 (Backlight) */
	GPIO17_PWM1_OUT,

	/* I2S */
	GPIO28_I2S_BITCLK_OUT,
	GPIO29_I2S_SDATA_IN,
	GPIO30_I2S_SDATA_OUT,
	GPIO31_I2S_SYNC,
	GPIO113_I2S_SYSCLK,

	/* SSP 1 (NavPoint) */
	GPIO23_SSP1_SCLK_IN,
	GPIO24_SSP1_SFRM,
	GPIO25_SSP1_TXD,
	GPIO26_SSP1_RXD,

	/* SSP 2 (TSC2046) */
	GPIO19_SSP2_SCLK,
	GPIO86_SSP2_RXD,
	GPIO87_SSP2_TXD,
	GPIO88_GPIO | MFP_LPM_DRIVE_HIGH,	/* TSC2046_CS */

	/* BQ24022 Regulator */
	GPIO72_GPIO | MFP_LPM_KEEP_OUTPUT,	/* BQ24022_nCHARGE_EN */
	GPIO96_GPIO | MFP_LPM_KEEP_OUTPUT,	/* BQ24022_ISET2 */

	/* HX4700 specific input GPIOs */
	GPIO12_GPIO | WAKEUP_ON_EDGE_RISE,	/* ASIC3_IRQ */
	GPIO13_GPIO,	/* W3220_IRQ */
	GPIO14_GPIO,	/* nWLAN_IRQ */

	/* HX4700 specific output GPIOs */
	GPIO61_GPIO | MFP_LPM_DRIVE_HIGH,	/* W3220_nRESET */
	GPIO71_GPIO | MFP_LPM_DRIVE_HIGH,	/* ASIC3_nRESET */
	GPIO81_GPIO | MFP_LPM_DRIVE_HIGH,	/* CPU_GP_nRESET */
	GPIO116_GPIO | MFP_LPM_DRIVE_HIGH,	/* CPU_HW_nRESET */
	GPIO102_GPIO | MFP_LPM_DRIVE_LOW,	/* SYNAPTICS_POWER_ON */

	GPIO10_GPIO,	/* GSM_IRQ */
	GPIO13_GPIO,	/* CPLD_IRQ */
	GPIO107_GPIO,	/* DS1WM_IRQ */
	GPIO108_GPIO,	/* GSM_READY */
	GPIO58_GPIO,	/* TSC2046_nPENIRQ */
	GPIO66_GPIO,	/* nSDIO_IRQ */
};

/*
 * IRDA
 */

static struct pxaficp_platform_data ficp_info = {
	.gpio_pwdown		= GPIO105_HX4700_nIR_ON,
	.transceiver_cap	= IR_SIRMODE | IR_OFF,
};

/*
 * GPIO Keys
 */

#define INIT_KEY(_code, _gpio, _active_low, _desc)	\
	{						\
		.code       = KEY_##_code,		\
		.gpio       = _gpio,			\
		.active_low = _active_low,		\
		.desc       = _desc,			\
		.type       = EV_KEY,			\
		.wakeup     = 1,			\
	}

static struct gpio_keys_button gpio_keys_buttons[] = {
	INIT_KEY(POWER,       GPIO0_HX4700_nKEY_POWER,   1, "Power button"),
	INIT_KEY(MAIL,        GPIO94_HX4700_KEY_MAIL,    0, "Mail button"),
	INIT_KEY(ADDRESSBOOK, GPIO99_HX4700_KEY_CONTACTS,0, "Contacts button"),
	INIT_KEY(RECORD,      GPIOD6_nKEY_RECORD,        1, "Record button"),
	INIT_KEY(CALENDAR,    GPIOD1_nKEY_CALENDAR,      1, "Calendar button"),
	INIT_KEY(HOMEPAGE,    GPIOD3_nKEY_HOME,          1, "Home button"),
};

static struct gpio_keys_platform_data gpio_keys_data = {
	.buttons = gpio_keys_buttons,
	.nbuttons = ARRAY_SIZE(gpio_keys_buttons),
};

static struct platform_device gpio_keys = {
	.name = "gpio-keys",
	.dev  = {
		.platform_data = &gpio_keys_data,
	},
	.id   = -1,
};

/*
 * Synaptics NavPoint connected to SSP1
 */

static struct navpoint_platform_data navpoint_platform_data = {
	.port	= 1,
	.gpio	= GPIO102_HX4700_SYNAPTICS_POWER_ON,
};

static struct platform_device navpoint = {
	.name	= "navpoint",
	.id	= -1,
	.dev = {
		.platform_data = &navpoint_platform_data,
	},
};

/*
 * ASIC3
 */

static u16 asic3_gpio_config[] = {
	/* ASIC3 GPIO banks A and B along with some of C and D
	   implement the buffering for the CF slot. */
	ASIC3_CONFIG_GPIO(0, 1, 1, 0),
	ASIC3_CONFIG_GPIO(1, 1, 1, 0),
	ASIC3_CONFIG_GPIO(2, 1, 1, 0),
	ASIC3_CONFIG_GPIO(3, 1, 1, 0),
	ASIC3_CONFIG_GPIO(4, 1, 1, 0),
	ASIC3_CONFIG_GPIO(5, 1, 1, 0),
	ASIC3_CONFIG_GPIO(6, 1, 1, 0),
	ASIC3_CONFIG_GPIO(7, 1, 1, 0),
	ASIC3_CONFIG_GPIO(8, 1, 1, 0),
	ASIC3_CONFIG_GPIO(9, 1, 1, 0),
	ASIC3_CONFIG_GPIO(10, 1, 1, 0),
	ASIC3_CONFIG_GPIO(11, 1, 1, 0),
	ASIC3_CONFIG_GPIO(12, 1, 1, 0),
	ASIC3_CONFIG_GPIO(13, 1, 1, 0),
	ASIC3_CONFIG_GPIO(14, 1, 1, 0),
	ASIC3_CONFIG_GPIO(15, 1, 1, 0),

	ASIC3_CONFIG_GPIO(16, 1, 1, 0),
	ASIC3_CONFIG_GPIO(17, 1, 1, 0),
	ASIC3_CONFIG_GPIO(18, 1, 1, 0),
	ASIC3_CONFIG_GPIO(19, 1, 1, 0),
	ASIC3_CONFIG_GPIO(20, 1, 1, 0),
	ASIC3_CONFIG_GPIO(21, 1, 1, 0),
	ASIC3_CONFIG_GPIO(22, 1, 1, 0),
	ASIC3_CONFIG_GPIO(23, 1, 1, 0),
	ASIC3_CONFIG_GPIO(24, 1, 1, 0),
	ASIC3_CONFIG_GPIO(25, 1, 1, 0),
	ASIC3_CONFIG_GPIO(26, 1, 1, 0),
	ASIC3_CONFIG_GPIO(27, 1, 1, 0),
	ASIC3_CONFIG_GPIO(28, 1, 1, 0),
	ASIC3_CONFIG_GPIO(29, 1, 1, 0),
	ASIC3_CONFIG_GPIO(30, 1, 1, 0),
	ASIC3_CONFIG_GPIO(31, 1, 1, 0),

	/* GPIOC - CF, LEDs, SD */
	ASIC3_GPIOC0_LED0,		/* red */
	ASIC3_GPIOC1_LED1,		/* green */
	ASIC3_GPIOC2_LED2,		/* blue */
	ASIC3_GPIOC5_nCIOW,
	ASIC3_GPIOC6_nCIOR,
	ASIC3_GPIOC7_nPCE_1,
	ASIC3_GPIOC8_nPCE_2,
	ASIC3_GPIOC9_nPOE,
	ASIC3_GPIOC10_nPWE,
	ASIC3_GPIOC11_PSKTSEL,
	ASIC3_GPIOC12_nPREG,
	ASIC3_GPIOC13_nPWAIT,
	ASIC3_GPIOC14_nPIOIS16,
	ASIC3_GPIOC15_nPIOR,

	/* GPIOD: input GPIOs, CF */
	ASIC3_GPIOD4_CF_nCD,
	ASIC3_GPIOD11_nCIOIS16,
	ASIC3_GPIOD12_nCWAIT,
	ASIC3_GPIOD15_nPIOW,
};

static struct asic3_led asic3_leds[ASIC3_NUM_LEDS] = {
	[0] = {
		.name = "hx4700:amber",
		.default_trigger = "ds2760-battery.0-charging-blink-full-solid",
	},
	[1] = {
		.name = "hx4700:green",
		.default_trigger = "unused",
	},
	[2] = {
		.name = "hx4700:blue",
		.default_trigger = "hx4700-radio",
	},
};

static struct resource asic3_resources[] = {
	/* GPIO part */
	[0] = DEFINE_RES_MEM(ASIC3_PHYS, ASIC3_MAP_SIZE_16BIT),
	[1] = DEFINE_RES_IRQ(PXA_GPIO_TO_IRQ(GPIO12_HX4700_ASIC3_IRQ)),
	/* SD part */
	[2] = DEFINE_RES_MEM(ASIC3_SD_PHYS, ASIC3_MAP_SIZE_16BIT),
	[3] = DEFINE_RES_IRQ(PXA_GPIO_TO_IRQ(GPIO66_HX4700_ASIC3_nSDIO_IRQ)),
};

static struct asic3_platform_data asic3_platform_data = {
	.gpio_config     = asic3_gpio_config,
	.gpio_config_num = ARRAY_SIZE(asic3_gpio_config),
	.irq_base        = IRQ_BOARD_START,
	.gpio_base       = HX4700_ASIC3_GPIO_BASE,
	.clock_rate      = 4000000,
	.leds            = asic3_leds,
};

static struct platform_device asic3 = {
	.name          = "asic3",
	.id            = -1,
	.resource      = asic3_resources,
	.num_resources = ARRAY_SIZE(asic3_resources),
	.dev = {
		.platform_data = &asic3_platform_data,
	},
};

/*
 * EGPIO
 */

static struct resource egpio_resources[] = {
	[0] = DEFINE_RES_MEM(PXA_CS5_PHYS, 0x4),
};

static struct htc_egpio_chip egpio_chips[] = {
	[0] = {
		.reg_start = 0,
		.gpio_base = HX4700_EGPIO_BASE,
		.num_gpios = 8,
		.direction = HTC_EGPIO_OUTPUT,
	},
};

static struct htc_egpio_platform_data egpio_info = {
	.reg_width = 16,
	.bus_width = 16,
	.chip      = egpio_chips,
	.num_chips = ARRAY_SIZE(egpio_chips),
};

static struct platform_device egpio = {
	.name          = "htc-egpio",
	.id            = -1,
	.resource      = egpio_resources,
	.num_resources = ARRAY_SIZE(egpio_resources),
	.dev = {
		.platform_data = &egpio_info,
	},
};

/*
 * LCD - Sony display connected to ATI Imageon w3220
 */

static void sony_lcd_init(void)
{
	gpio_set_value(GPIO84_HX4700_LCD_SQN, 1);
	gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
	gpio_set_value(GPIO111_HX4700_LCD_AVDD_3V3_ON, 0);
	gpio_set_value(GPIO70_HX4700_LCD_SLIN1, 0);
	gpio_set_value(GPIO62_HX4700_LCD_nRESET, 0);
	mdelay(10);
	gpio_set_value(GPIO59_HX4700_LCD_PC1, 0);
	gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
	mdelay(20);

	gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 1);
	mdelay(5);
	gpio_set_value(GPIO111_HX4700_LCD_AVDD_3V3_ON, 1);

	/* FIXME: init w3220 registers here */

	mdelay(5);
	gpio_set_value(GPIO70_HX4700_LCD_SLIN1, 1);
	mdelay(10);
	gpio_set_value(GPIO62_HX4700_LCD_nRESET, 1);
	mdelay(10);
	gpio_set_value(GPIO59_HX4700_LCD_PC1, 1);
	mdelay(10);
	gpio_set_value(GPIO112_HX4700_LCD_N2V7_7V3_ON, 1);
}

static void sony_lcd_off(void)
{
	gpio_set_value(GPIO59_HX4700_LCD_PC1, 0);
	gpio_set_value(GPIO62_HX4700_LCD_nRESET, 0);
	mdelay(10);
	gpio_set_value(GPIO112_HX4700_LCD_N2V7_7V3_ON, 0);
	mdelay(10);
	gpio_set_value(GPIO111_HX4700_LCD_AVDD_3V3_ON, 0);
	mdelay(10);
	gpio_set_value(GPIO110_HX4700_LCD_LVDD_3V3_ON, 0);
}

#ifdef CONFIG_PM
static void w3220_lcd_suspend(struct w100fb_par *wfb)
{
	sony_lcd_off();
}

static void w3220_lcd_resume(struct w100fb_par *wfb)
{
	sony_lcd_init();
}
#else
#define w3220_lcd_resume	NULL
#define w3220_lcd_suspend	NULL
#endif

static struct w100_tg_info w3220_tg_info = {
	.suspend	= w3220_lcd_suspend,
	.resume		= w3220_lcd_resume,
};

/*  				 W3220_VGA		QVGA */
static struct w100_gen_regs w3220_regs = {
	.lcd_format =        0x00000003,
	.lcdd_cntl1 =        0x00000000,
	.lcdd_cntl2 =        0x0003ffff,
	.genlcd_cntl1 =      0x00abf003,	/* 0x00fff003 */
	.genlcd_cntl2 =      0x00000003,
	.genlcd_cntl3 =      0x000102aa,
};

static struct w100_mode w3220_modes[] = {
{
	.xres 		= 480,
	.yres 		= 640,
	.left_margin 	= 15,
	.right_margin 	= 16,
	.upper_margin 	= 8,
	.lower_margin 	= 7,
	.crtc_ss	= 0x00000000,
	.crtc_ls	= 0xa1ff01f9,	/* 0x21ff01f9 */
	.crtc_gs	= 0xc0000000,	/* 0x40000000 */
	.crtc_vpos_gs	= 0x0000028f,
	.crtc_ps1_active = 0x00000000,	/* 0x41060010 */
	.crtc_rev	= 0,
	.crtc_dclk	= 0x80000000,
	.crtc_gclk	= 0x040a0104,
	.crtc_goe	= 0,
	.pll_freq 	= 95,
	.pixclk_divider = 4,
	.pixclk_divider_rotated = 4,
	.pixclk_src     = CLK_SRC_PLL,
	.sysclk_divider = 0,
	.sysclk_src     = CLK_SRC_PLL,
},
{
	.xres 		= 240,
	.yres 		= 320,
	.left_margin 	= 9,
	.right_margin 	= 8,
	.upper_margin 	= 5,
	.lower_margin 	= 4,
	.crtc_ss	= 0x80150014,
	.crtc_ls        = 0xa0fb00f7,
	.crtc_gs	= 0xc0080007,
	.crtc_vpos_gs	= 0x00080007,
	.crtc_rev	= 0x0000000a,
	.crtc_dclk	= 0x81700030,
	.crtc_gclk	= 0x8015010f,
	.crtc_goe	= 0x00000000,
	.pll_freq 	= 95,
	.pixclk_divider = 4,
	.pixclk_divider_rotated = 4,
	.pixclk_src     = CLK_SRC_PLL,
	.sysclk_divider = 0,
	.sysclk_src     = CLK_SRC_PLL,
},
};

struct w100_mem_info w3220_mem_info = {
	.ext_cntl        = 0x09640011,
	.sdram_mode_reg  = 0x00600021,
	.ext_timing_cntl = 0x1a001545,	/* 0x15001545 */
	.io_cntl         = 0x7ddd7333,
	.size            = 0x1fffff,
};

struct w100_bm_mem_info w3220_bm_mem_info = {
	.ext_mem_bw = 0x50413e01,
	.offset = 0,
	.ext_timing_ctl = 0x00043f7f,
	.ext_cntl = 0x00000010,
	.mode_reg = 0x00250000,
	.io_cntl = 0x0fff0000,
	.config = 0x08301480,
};

static struct w100_gpio_regs w3220_gpio_info = {
	.init_data1 = 0xdfe00100,	/* GPIO_DATA */
	.gpio_dir1  = 0xffff0000,	/* GPIO_CNTL1 */
	.gpio_oe1   = 0x00000000,	/* GPIO_CNTL2 */
	.init_data2 = 0x00000000,	/* GPIO_DATA2 */
	.gpio_dir2  = 0x00000000,	/* GPIO_CNTL3 */
	.gpio_oe2   = 0x00000000,	/* GPIO_CNTL4 */
};

static struct w100fb_mach_info w3220_info = {
	.tg        = &w3220_tg_info,
	.mem       = &w3220_mem_info,
	.bm_mem    = &w3220_bm_mem_info,
	.gpio      = &w3220_gpio_info,
	.regs      = &w3220_regs,
	.modelist  = w3220_modes,
	.num_modes = 2,
	.xtal_freq = 16000000,
};

static struct resource w3220_resources[] = {
	[0] = DEFINE_RES_MEM(ATI_W3220_PHYS, SZ_16M),
};

static struct platform_device w3220 = {
	.name	= "w100fb",
	.id	= -1,
	.dev	= {
		.platform_data = &w3220_info,
	},
	.num_resources = ARRAY_SIZE(w3220_resources),
	.resource      = w3220_resources,
};

static void hx4700_lcd_set_power(struct plat_lcd_data *pd, unsigned int power)
{
	if (power)
		sony_lcd_init();
	else
		sony_lcd_off();
}

static struct plat_lcd_data hx4700_lcd_data = {
	.set_power = hx4700_lcd_set_power,
};

static struct platform_device hx4700_lcd = {
	.name = "platform-lcd",
	.id   = -1,
	.dev  = {
		.platform_data = &hx4700_lcd_data,
		.parent        = &w3220.dev,
	},
};

/*
 * Backlight
 */

static struct platform_pwm_backlight_data backlight_data = {
	.max_brightness = 200,
	.dft_brightness = 100,
};

static struct platform_device backlight = {
	.name = "pwm-backlight",
	.id   = -1,
	.dev  = {
		.parent        = &pxa27x_device_pwm1.dev,
		.platform_data = &backlight_data,
	},
};

static struct pwm_lookup hx4700_pwm_lookup[] = {
	PWM_LOOKUP("pxa27x-pwm.1", 0, "pwm-backlight", NULL,
		   30923, PWM_POLARITY_NORMAL),
};

/*
 * USB "Transceiver"
 */

static struct gpiod_lookup_table gpio_vbus_gpiod_table = {
	.dev_id = "gpio-vbus",
	.table = {
		/* This GPIO is on ASIC3 */
		GPIO_LOOKUP("asic3",
			    /* Convert to a local offset on the ASIC3 */
			    GPIOD14_nUSBC_DETECT - HX4700_ASIC3_GPIO_BASE,
			    "vbus", GPIO_ACTIVE_LOW),
		/* This one is on the primary SOC GPIO */
		GPIO_LOOKUP("gpio-pxa", GPIO76_HX4700_USBC_PUEN,
			    "pullup", GPIO_ACTIVE_HIGH),
		{ },
	},
};

static struct platform_device gpio_vbus = {
	.name          = "gpio-vbus",
	.id            = -1,
};

static struct pxa2xx_udc_mach_info hx4700_udc_info;

/*
 * Touchscreen - TSC2046 connected to SSP2
 */

static const struct ads7846_platform_data tsc2046_info = {
	.model            = 7846,
	.vref_delay_usecs = 100,
	.pressure_max     = 1024,
	.debounce_max     = 10,
	.debounce_tol     = 3,
	.debounce_rep     = 1,
	.gpio_pendown     = GPIO58_HX4700_TSC2046_nPENIRQ,
};

static struct pxa2xx_spi_chip tsc2046_chip = {
	.tx_threshold = 1,
	.rx_threshold = 2,
	.timeout      = 64,
};

static struct spi_board_info tsc2046_board_info[] __initdata = {
	{
		.modalias        = "ads7846",
		.bus_num         = 2,
		.max_speed_hz    = 2600000, /* 100 kHz sample rate */
		.irq             = PXA_GPIO_TO_IRQ(GPIO58_HX4700_TSC2046_nPENIRQ),
		.platform_data   = &tsc2046_info,
		.controller_data = &tsc2046_chip,
	},
};

static struct pxa2xx_spi_controller pxa_ssp2_master_info = {
	.num_chipselect = 1,
	.enable_dma     = 1,
};

static struct gpiod_lookup_table pxa_ssp2_gpio_table = {
	.dev_id = "spi2",
	.table = {
		GPIO_LOOKUP_IDX("gpio-pxa", GPIO88_HX4700_TSC2046_CS, "cs", 0, GPIO_ACTIVE_LOW),
		{ },
	},
};

/*
 * External power
 */

static int power_supply_init(struct device *dev)
{
	return gpio_request(GPIOD9_nAC_IN, "AC charger detect");
}

static int hx4700_is_ac_online(void)
{
	return !gpio_get_value(GPIOD9_nAC_IN);
}

static void power_supply_exit(struct device *dev)
{
	gpio_free(GPIOD9_nAC_IN);
}

static char *hx4700_supplicants[] = {
	"ds2760-battery.0", "backup-battery"
};

static struct pda_power_pdata power_supply_info = {
	.init            = power_supply_init,
	.is_ac_online    = hx4700_is_ac_online,
	.exit            = power_supply_exit,
	.supplied_to     = hx4700_supplicants,
	.num_supplicants = ARRAY_SIZE(hx4700_supplicants),
};

static struct resource power_supply_resources[] = {
	[0] = DEFINE_RES_NAMED(PXA_GPIO_TO_IRQ(GPIOD9_nAC_IN), 1, "ac",
		IORESOURCE_IRQ |
		IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE),
	[1] = DEFINE_RES_NAMED(PXA_GPIO_TO_IRQ(GPIOD14_nUSBC_DETECT), 1, "usb",
		IORESOURCE_IRQ |
		IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE),
};

static struct platform_device power_supply = {
	.name = "pda-power",
	.id   = -1,
	.dev  = {
		.platform_data = &power_supply_info,
	},
	.resource      = power_supply_resources,
	.num_resources = ARRAY_SIZE(power_supply_resources),
};

/*
 * Battery charger
 */

static struct regulator_consumer_supply bq24022_consumers[] = {
	REGULATOR_SUPPLY("vbus_draw", NULL),
	REGULATOR_SUPPLY("ac_draw", NULL),
};

static struct regulator_init_data bq24022_init_data = {
	.constraints = {
		.max_uA         = 500000,
		.valid_ops_mask = REGULATOR_CHANGE_CURRENT|REGULATOR_CHANGE_STATUS,
	},
	.num_consumer_supplies  = ARRAY_SIZE(bq24022_consumers),
	.consumer_supplies      = bq24022_consumers,
};

static enum gpiod_flags bq24022_gpiod_gflags[] = { GPIOD_OUT_LOW };

static struct gpio_regulator_state bq24022_states[] = {
	{ .value = 100000, .gpios = (0 << 0) },
	{ .value = 500000, .gpios = (1 << 0) },
};

static struct gpio_regulator_config bq24022_info = {
	.supply_name = "bq24022",

	.enabled_at_boot = 0,

	.gflags = bq24022_gpiod_gflags,
	.ngpios = ARRAY_SIZE(bq24022_gpiod_gflags),

	.states = bq24022_states,
	.nr_states = ARRAY_SIZE(bq24022_states),

	.type = REGULATOR_CURRENT,
	.init_data = &bq24022_init_data,
};

static struct platform_device bq24022 = {
	.name = "gpio-regulator",
	.id   = -1,
	.dev  = {
		.platform_data = &bq24022_info,
	},
};

static struct gpiod_lookup_table bq24022_gpiod_table = {
	.dev_id = "gpio-regulator",
	.table = {
		GPIO_LOOKUP("gpio-pxa", GPIO96_HX4700_BQ24022_ISET2,
			    NULL, GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP("gpio-pxa", GPIO72_HX4700_BQ24022_nCHARGE_EN,
			    "enable", GPIO_ACTIVE_LOW),
		{ },
	},
};

/*
 * StrataFlash
 */

static void hx4700_set_vpp(struct platform_device *pdev, int vpp)
{
	gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp);
}

static struct resource strataflash_resource[] = {
	[0] = DEFINE_RES_MEM(PXA_CS0_PHYS, SZ_64M),
	[1] = DEFINE_RES_MEM(PXA_CS0_PHYS + SZ_64M, SZ_64M),
};

static struct physmap_flash_data strataflash_data = {
	.width = 4,
	.set_vpp = hx4700_set_vpp,
};

static struct platform_device strataflash = {
	.name          = "physmap-flash",
	.id            = -1,
	.resource      = strataflash_resource,
	.num_resources = ARRAY_SIZE(strataflash_resource),
	.dev = {
		.platform_data = &strataflash_data,
	},
};

/*
 * Maxim MAX1587A on PI2C
 */

static struct regulator_consumer_supply max1587a_consumer =
	REGULATOR_SUPPLY("vcc_core", NULL);

static struct regulator_init_data max1587a_v3_info = {
	.constraints = {
		.name = "vcc_core range",
		.min_uV =  900000,
		.max_uV = 1705000,
		.always_on = 1,
		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
	},
	.num_consumer_supplies = 1,
	.consumer_supplies     = &max1587a_consumer,
};

static struct max1586_subdev_data max1587a_subdev = {
	.name = "vcc_core",
	.id   = MAX1586_V3,
	.platform_data = &max1587a_v3_info,
};

static struct max1586_platform_data max1587a_info = {
	.num_subdevs = 1,
	.subdevs     = &max1587a_subdev,
	.v3_gain     = MAX1586_GAIN_R24_3k32, /* 730..1550 mV */
};

static struct i2c_board_info __initdata pi2c_board_info[] = {
	{
		I2C_BOARD_INFO("max1586", 0x14),
		.platform_data = &max1587a_info,
	},
};

/*
 * Asahi Kasei AK4641 on I2C
 */

static struct ak4641_platform_data ak4641_info = {
	.gpio_power = GPIO27_HX4700_CODEC_ON,
	.gpio_npdn  = GPIO109_HX4700_CODEC_nPDN,
};

static struct i2c_board_info i2c_board_info[] __initdata = {
	{
		I2C_BOARD_INFO("ak4641", 0x12),
		.platform_data = &ak4641_info,
	},
};

static struct gpiod_lookup_table hx4700_audio_gpio_table = {
	.dev_id = "hx4700-audio",
	.table = {
		GPIO_LOOKUP("gpio-pxa", GPIO75_HX4700_EARPHONE_nDET,
			    "earphone-det", GPIO_ACTIVE_LOW),
		GPIO_LOOKUP("gpio-pxa", GPIO92_HX4700_HP_DRIVER,
			    "hp-driver", GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP("gpio-pxa", GPIO107_HX4700_SPK_nSD,
			    "spk-sd", GPIO_ACTIVE_LOW),
		{ },
	},
};

static struct platform_device audio = {
	.name	= "hx4700-audio",
	.id	= -1,
};

/*
 * Platform devices
 */

static struct platform_device *devices[] __initdata = {
	&asic3,
	&gpio_keys,
	&navpoint,
	&backlight,
	&w3220,
	&hx4700_lcd,
	&egpio,
	&bq24022,
	&gpio_vbus,
	&power_supply,
	&strataflash,
	&audio,
};

static struct gpio global_gpios[] = {
	{ GPIO12_HX4700_ASIC3_IRQ, GPIOF_IN, "ASIC3_IRQ" },
	{ GPIO13_HX4700_W3220_IRQ, GPIOF_IN, "W3220_IRQ" },
	{ GPIO14_HX4700_nWLAN_IRQ, GPIOF_IN, "WLAN_IRQ" },
	{ GPIO59_HX4700_LCD_PC1,          GPIOF_OUT_INIT_HIGH, "LCD_PC1" },
	{ GPIO62_HX4700_LCD_nRESET,       GPIOF_OUT_INIT_HIGH, "LCD_RESET" },
	{ GPIO70_HX4700_LCD_SLIN1,        GPIOF_OUT_INIT_HIGH, "LCD_SLIN1" },
	{ GPIO84_HX4700_LCD_SQN,          GPIOF_OUT_INIT_HIGH, "LCD_SQN" },
	{ GPIO110_HX4700_LCD_LVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_LVDD" },
	{ GPIO111_HX4700_LCD_AVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_AVDD" },
	{ GPIO32_HX4700_RS232_ON,         GPIOF_OUT_INIT_HIGH, "RS232_ON" },
	{ GPIO61_HX4700_W3220_nRESET,     GPIOF_OUT_INIT_HIGH, "W3220_nRESET" },
	{ GPIO71_HX4700_ASIC3_nRESET,     GPIOF_OUT_INIT_HIGH, "ASIC3_nRESET" },
	{ GPIO81_HX4700_CPU_GP_nRESET,    GPIOF_OUT_INIT_HIGH, "CPU_GP_nRESET" },
	{ GPIO82_HX4700_EUART_RESET,      GPIOF_OUT_INIT_HIGH, "EUART_RESET" },
	{ GPIO116_HX4700_CPU_HW_nRESET,   GPIOF_OUT_INIT_HIGH, "CPU_HW_nRESET" },
};

static void __init hx4700_init(void)
{
	int ret;

	PCFR = PCFR_GPR_EN | PCFR_OPDE;

	pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config));
	gpio_set_wake(GPIO12_HX4700_ASIC3_IRQ, 1);
	ret = gpio_request_array(ARRAY_AND_SIZE(global_gpios));
	if (ret)
		pr_err ("hx4700: Failed to request GPIOs.\n");

	pxa_set_ffuart_info(NULL);
	pxa_set_btuart_info(NULL);
	pxa_set_stuart_info(NULL);

	gpiod_add_lookup_table(&bq24022_gpiod_table);
	gpiod_add_lookup_table(&gpio_vbus_gpiod_table);
	gpiod_add_lookup_table(&hx4700_audio_gpio_table);
	platform_add_devices(devices, ARRAY_SIZE(devices));
	pwm_add_table(hx4700_pwm_lookup, ARRAY_SIZE(hx4700_pwm_lookup));

	pxa_set_ficp_info(&ficp_info);
	pxa27x_set_i2c_power_info(NULL);
	pxa_set_i2c_info(NULL);
	i2c_register_board_info(0, ARRAY_AND_SIZE(i2c_board_info));
	i2c_register_board_info(1, ARRAY_AND_SIZE(pi2c_board_info));
	gpiod_add_lookup_table(&pxa_ssp2_gpio_table);
	pxa2xx_set_spi_info(2, &pxa_ssp2_master_info);
	spi_register_board_info(ARRAY_AND_SIZE(tsc2046_board_info));

	gpio_set_value(GPIO71_HX4700_ASIC3_nRESET, 0);
	mdelay(10);
	gpio_set_value(GPIO71_HX4700_ASIC3_nRESET, 1);
	mdelay(10);

	pxa_set_udc_info(&hx4700_udc_info);
	regulator_has_full_constraints();
}

MACHINE_START(H4700, "HP iPAQ HX4700")
	.atag_offset  = 0x100,
	.map_io       = pxa27x_map_io,
	.nr_irqs      = HX4700_NR_IRQS,
	.init_irq     = pxa27x_init_irq,
	.handle_irq     = pxa27x_handle_irq,
	.init_machine = hx4700_init,
	.init_time	= pxa_timer_init,
	.restart	= pxa_restart,
MACHINE_END


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * GPIO and IRQ definitions for HP iPAQ hx4700
 *
 * Copyright (c) 2008 Philipp Zabel
 */

#ifndef _HX4700_H_
#define _HX4700_H_

#include <linux/gpio.h>
#include <linux/mfd/asic3.h>
#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */

#define HX4700_ASIC3_GPIO_BASE	PXA_NR_BUILTIN_GPIO
#define HX4700_EGPIO_BASE	(HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
#define HX4700_NR_IRQS		(IRQ_BOARD_START + 70)

/*
 * PXA GPIOs
 */

#define GPIO0_HX4700_nKEY_POWER			0
#define GPIO12_HX4700_ASIC3_IRQ			12
#define GPIO13_HX4700_W3220_IRQ			13
#define GPIO14_HX4700_nWLAN_IRQ			14
#define GPIO18_HX4700_RDY			18
#define GPIO22_HX4700_LCD_RL			22
#define GPIO27_HX4700_CODEC_ON			27
#define GPIO32_HX4700_RS232_ON			32
#define GPIO52_HX4700_CPU_nBATT_FAULT		52
#define GPIO58_HX4700_TSC2046_nPENIRQ		58
#define GPIO59_HX4700_LCD_PC1			59
#define GPIO60_HX4700_CF_RNB			60
#define GPIO61_HX4700_W3220_nRESET		61
#define GPIO62_HX4700_LCD_nRESET		62
#define GPIO63_HX4700_CPU_SS_nRESET		63
#define GPIO65_HX4700_TSC2046_PEN_PU		65
#define GPIO66_HX4700_ASIC3_nSDIO_IRQ		66
#define GPIO67_HX4700_EUART_PS			67
#define GPIO70_HX4700_LCD_SLIN1			70
#define GPIO71_HX4700_ASIC3_nRESET		71
#define GPIO72_HX4700_BQ24022_nCHARGE_EN	72
#define GPIO73_HX4700_LCD_UD_1			73
#define GPIO75_HX4700_EARPHONE_nDET		75
#define GPIO76_HX4700_USBC_PUEN			76
#define GPIO81_HX4700_CPU_GP_nRESET		81
#define GPIO82_HX4700_EUART_RESET		82
#define GPIO83_HX4700_WLAN_nRESET		83
#define GPIO84_HX4700_LCD_SQN			84
#define GPIO85_HX4700_nPCE1			85
#define GPIO88_HX4700_TSC2046_CS		88
#define GPIO91_HX4700_FLASH_VPEN		91
#define GPIO92_HX4700_HP_DRIVER			92
#define GPIO93_HX4700_EUART_INT			93
#define GPIO94_HX4700_KEY_MAIL			94
#define GPIO95_HX4700_BATT_OFF			95
#define GPIO96_HX4700_BQ24022_ISET2		96
#define GPIO97_HX4700_nBL_DETECT		97
#define GPIO99_HX4700_KEY_CONTACTS		99
#define GPIO100_HX4700_AUTO_SENSE		100 /* BL auto brightness */
#define GPIO102_HX4700_SYNAPTICS_POWER_ON	102
#define GPIO103_HX4700_SYNAPTICS_INT		103
#define GPIO105_HX4700_nIR_ON			105
#define GPIO106_HX4700_CPU_BT_nRESET		106
#define GPIO107_HX4700_SPK_nSD			107
#define GPIO109_HX4700_CODEC_nPDN		109
#define GPIO110_HX4700_LCD_LVDD_3V3_ON		110
#define GPIO111_HX4700_LCD_AVDD_3V3_ON		111
#define GPIO112_HX4700_LCD_N2V7_7V3_ON		112
#define GPIO114_HX4700_CF_RESET			114
#define GPIO116_HX4700_CPU_HW_nRESET		116

/*
 * ASIC3 GPIOs
 */

#define GPIOC_BASE		(HX4700_ASIC3_GPIO_BASE + 32)
#define GPIOD_BASE		(HX4700_ASIC3_GPIO_BASE + 48)

#define GPIOC0_LED_RED		(GPIOC_BASE + 0)
#define GPIOC1_LED_GREEN	(GPIOC_BASE + 1)
#define GPIOC2_LED_BLUE		(GPIOC_BASE + 2)
#define GPIOC3_nSD_CS		(GPIOC_BASE + 3)
#define GPIOC4_CF_nCD		(GPIOC_BASE + 4)	/* Input */
#define GPIOC5_nCIOW		(GPIOC_BASE + 5)	/* Output, to CF */
#define GPIOC6_nCIOR		(GPIOC_BASE + 6)	/* Output, to CF */
#define GPIOC7_nPCE1		(GPIOC_BASE + 7)	/* Input, from CPU */
#define GPIOC8_nPCE2		(GPIOC_BASE + 8)	/* Input, from CPU */
#define GPIOC9_nPOE		(GPIOC_BASE + 9)	/* Input, from CPU */
#define GPIOC10_CF_nPWE		(GPIOC_BASE + 10)	/* Input */
#define GPIOC11_PSKTSEL		(GPIOC_BASE + 11)	/* Input, from CPU */
#define GPIOC12_nPREG		(GPIOC_BASE + 12)	/* Input, from CPU */
#define GPIOC13_nPWAIT		(GPIOC_BASE + 13)	/* Output, to CPU */
#define GPIOC14_nPIOIS16	(GPIOC_BASE + 14)	/* Output, to CPU */
#define GPIOC15_nPIOR		(GPIOC_BASE + 15)	/* Input, from CPU */

#define GPIOD0_CPU_SS_INT	(GPIOD_BASE + 0)	/* Input */
#define GPIOD1_nKEY_CALENDAR	(GPIOD_BASE + 1)
#define GPIOD2_BLUETOOTH_WAKEUP	(GPIOD_BASE + 2)
#define GPIOD3_nKEY_HOME	(GPIOD_BASE + 3)
#define GPIOD4_CF_nCD		(GPIOD_BASE + 4)	/* Input, from CF */
#define GPIOD5_nPIO		(GPIOD_BASE + 5)	/* Input */
#define GPIOD6_nKEY_RECORD	(GPIOD_BASE + 6)
#define GPIOD7_nSDIO_DETECT	(GPIOD_BASE + 7)
#define GPIOD8_COM_DCD		(GPIOD_BASE + 8)	/* Input */
#define GPIOD9_nAC_IN		(GPIOD_BASE + 9)
#define GPIOD10_nSDIO_IRQ	(GPIOD_BASE + 10)	/* Input */
#define GPIOD11_nCIOIS16	(GPIOD_BASE + 11)	/* Input, from CF */
#define GPIOD12_nCWAIT		(GPIOD_BASE + 12)	/* Input, from CF */
#define GPIOD13_CF_RNB		(GPIOD_BASE + 13)	/* Input */
#define GPIOD14_nUSBC_DETECT	(GPIOD_BASE + 14)
#define GPIOD15_nPIOW		(GPIOD_BASE + 15)	/* Input, from CPU */

/*
 * EGPIOs
 */

#define EGPIO0_VCC_3V3_EN	(HX4700_EGPIO_BASE + 0)	/* WLAN support chip */
#define EGPIO1_WL_VREG_EN	(HX4700_EGPIO_BASE + 1)	/* WLAN power */
#define EGPIO2_VCC_2V1_WL_EN	(HX4700_EGPIO_BASE + 2)	/* unused */
#define EGPIO3_SS_PWR_ON	(HX4700_EGPIO_BASE + 3)	/* smart slot power */
#define EGPIO4_CF_3V3_ON	(HX4700_EGPIO_BASE + 4)	/* CF 3.3V enable */
#define EGPIO5_BT_3V3_ON	(HX4700_EGPIO_BASE + 5)	/* BT 3.3V enable */
#define EGPIO6_WL1V8_EN		(HX4700_EGPIO_BASE + 6)	/* WLAN 1.8V enable */
#define EGPIO7_VCC_3V3_WL_EN	(HX4700_EGPIO_BASE + 7)	/* WLAN 3.3V enable */
#define EGPIO8_USB_3V3_ON	(HX4700_EGPIO_BASE + 8)	/* unused */

#endif /* _HX4700_H_ */

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * linux/arch/arm/mach-pxa/icontrol.c
 *
 * Support for the iControl and SafeTcam platforms from TMT Services
 * using the Embedian MXM-8x10 Computer on Module
 *
 * Copyright (C) 2009 TMT Services & Supplies (Pty) Ltd.
 *
 * 2010-01-21 Hennie van der Merve <hvdmerwe@tmtservies.co.za>
 */

#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/gpio/machine.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>

#include "pxa320.h"
#include "mxm8x10.h"

#include <linux/spi/spi.h>
#include <linux/spi/pxa2xx_spi.h>
#include <linux/regulator/machine.h>

#include "generic.h"

#define ICONTROL_MCP251x_nCS1	(15)
#define ICONTROL_MCP251x_nCS2	(16)
#define ICONTROL_MCP251x_nCS3	(17)
#define ICONTROL_MCP251x_nCS4	(24)

#define ICONTROL_MCP251x_nIRQ1	(74)
#define ICONTROL_MCP251x_nIRQ2	(75)
#define ICONTROL_MCP251x_nIRQ3	(76)
#define ICONTROL_MCP251x_nIRQ4	(77)

static struct pxa2xx_spi_chip mcp251x_chip_info1 = {
	.tx_threshold   = 8,
	.rx_threshold   = 128,
	.dma_burst_size = 8,
	.timeout        = 235,
};

static struct pxa2xx_spi_chip mcp251x_chip_info2 = {
	.tx_threshold   = 8,
	.rx_threshold   = 128,
	.dma_burst_size = 8,
	.timeout        = 235,
};

static struct pxa2xx_spi_chip mcp251x_chip_info3 = {
	.tx_threshold   = 8,
	.rx_threshold   = 128,
	.dma_burst_size = 8,
	.timeout        = 235,
};

static struct pxa2xx_spi_chip mcp251x_chip_info4 = {
	.tx_threshold   = 8,
	.rx_threshold   = 128,
	.dma_burst_size = 8,
	.timeout        = 235,
};

static const struct property_entry mcp251x_properties[] = {
	PROPERTY_ENTRY_U32("clock-frequency", 16000000),
	{}
};

static const struct software_node mcp251x_node = {
	.properties = mcp251x_properties,
};

static struct spi_board_info mcp251x_board_info[] = {
	{
		.modalias        = "mcp2515",
		.max_speed_hz    = 6500000,
		.bus_num         = 3,
		.chip_select     = 0,
		.swnode		 = &mcp251x_node,
		.controller_data = &mcp251x_chip_info1,
		.irq             = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ1)
	},
	{
		.modalias        = "mcp2515",
		.max_speed_hz    = 6500000,
		.bus_num         = 3,
		.chip_select     = 1,
		.swnode		 = &mcp251x_node,
		.controller_data = &mcp251x_chip_info2,
		.irq             = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ2)
	},
	{
		.modalias        = "mcp2515",
		.max_speed_hz    = 6500000,
		.bus_num         = 4,
		.chip_select     = 0,
		.swnode		 = &mcp251x_node,
		.controller_data = &mcp251x_chip_info3,
		.irq             = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ3)
	},
	{
		.modalias        = "mcp2515",
		.max_speed_hz    = 6500000,
		.bus_num         = 4,
		.chip_select     = 1,
		.swnode		 = &mcp251x_node,
		.controller_data = &mcp251x_chip_info4,
		.irq             = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ4)
	}
};

static struct pxa2xx_spi_controller pxa_ssp3_spi_master_info = {
	.num_chipselect = 2,
	.enable_dma     = 1
};

static struct pxa2xx_spi_controller pxa_ssp4_spi_master_info = {
	.num_chipselect = 2,
	.enable_dma     = 1
};

struct platform_device pxa_spi_ssp3 = {
	.name          = "pxa2xx-spi",
	.id            = 3,
	.dev           = {
		.platform_data = &pxa_ssp3_spi_master_info,
	}
};

struct platform_device pxa_spi_ssp4 = {
	.name          = "pxa2xx-spi",
	.id            = 4,
	.dev           = {
		.platform_data = &pxa_ssp4_spi_master_info,
	}
};

static struct gpiod_lookup_table pxa_ssp3_gpio_table = {
	.dev_id = "spi3",
	.table = {
		GPIO_LOOKUP_IDX("gpio-pxa", ICONTROL_MCP251x_nCS1, "cs", 0, GPIO_ACTIVE_LOW),
		GPIO_LOOKUP_IDX("gpio-pxa", ICONTROL_MCP251x_nCS2, "cs", 1, GPIO_ACTIVE_LOW),
		{ },
	},
};

static struct gpiod_lookup_table pxa_ssp4_gpio_table = {
	.dev_id = "spi4",
	.table = {
		GPIO_LOOKUP_IDX("gpio-pxa", ICONTROL_MCP251x_nCS3, "cs", 0, GPIO_ACTIVE_LOW),
		GPIO_LOOKUP_IDX("gpio-pxa", ICONTROL_MCP251x_nCS4, "cs", 1, GPIO_ACTIVE_LOW),
		{ },
	},
};

static struct platform_device *icontrol_spi_devices[] __initdata = {
	&pxa_spi_ssp3,
	&pxa_spi_ssp4,
};

static mfp_cfg_t mfp_can_cfg[] __initdata = {
	/* CAN CS lines */
	GPIO15_GPIO,
	GPIO16_GPIO,
	GPIO17_GPIO,
	GPIO24_GPIO,

	/* SPI (SSP3) lines */
	GPIO89_SSP3_SCLK,
	GPIO91_SSP3_TXD,
	GPIO92_SSP3_RXD,

	/* SPI (SSP4) lines */
	GPIO93_SSP4_SCLK,
	GPIO95_SSP4_TXD,
	GPIO96_SSP4_RXD,

	/* CAN nIRQ lines */
	GPIO74_GPIO | MFP_LPM_EDGE_RISE,
	GPIO75_GPIO | MFP_LPM_EDGE_RISE,
	GPIO76_GPIO | MFP_LPM_EDGE_RISE,
	GPIO77_GPIO | MFP_LPM_EDGE_RISE
};

static void __init icontrol_can_init(void)
{
	pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_can_cfg));
	gpiod_add_lookup_table(&pxa_ssp3_gpio_table);
	gpiod_add_lookup_table(&pxa_ssp4_gpio_table);
	platform_add_devices(ARRAY_AND_SIZE(icontrol_spi_devices));
	spi_register_board_info(ARRAY_AND_SIZE(mcp251x_board_info));
}

static void __init icontrol_init(void)
{
	mxm_8x10_barebones_init();
	mxm_8x10_usb_host_init();
	mxm_8x10_mmc_init();

	icontrol_can_init();

	regulator_has_full_constraints();
}

MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
	.atag_offset	= 0x100,
	.map_io		= pxa3xx_map_io,
	.nr_irqs	= PXA_NR_IRQS,
	.init_irq	= pxa3xx_init_irq,
	.handle_irq	= pxa3xx_handle_irq,
	.init_time	= pxa_timer_init,
	.init_machine	= icontrol_init,
	.restart	= pxa_restart,
MACHINE_END


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 *  linux/arch/arm/mach-pxa/idp.c
 *
 *  Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
 *
 *  2001-09-13: Cliff Brake <cbrake@accelent.com>
 *              Initial code
 *
 *  2005-02-15: Cliff Brake <cliff.brake@gmail.com>
 *  		<http://www.vibren.com> <http://bec-systems.com>
 *              Updated for 2.6 kernel
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/fb.h>

#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <asm/irq.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#include "pxa25x.h"
#include "idp.h"
#include <linux/platform_data/video-pxafb.h>
#include <linux/platform_data/mmc-pxamci.h>
#include <linux/smc91x.h>

#include "generic.h"
#include "devices.h"

/* TODO:
 * - add pxa2xx_audio_ops_t device structure
 * - Ethernet interrupt
 */

static unsigned long idp_pin_config[] __initdata = {
	/* LCD */
	GPIOxx_LCD_DSTN_16BPP,

	/* BTUART */
	GPIO42_BTUART_RXD,
	GPIO43_BTUART_TXD,
	GPIO44_BTUART_CTS,
	GPIO45_BTUART_RTS,

	/* STUART */
	GPIO46_STUART_RXD,
	GPIO47_STUART_TXD,

	/* MMC */
	GPIO6_MMC_CLK,
	GPIO8_MMC_CS0,

	/* Ethernet */
	GPIO33_nCS_5,	/* Ethernet CS */
	GPIO4_GPIO,	/* Ethernet IRQ */
};

static struct resource smc91x_resources[] = {
	[0] = {
		.start	= (IDP_ETH_PHYS + 0x300),
		.end	= (IDP_ETH_PHYS + 0xfffff),
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= PXA_GPIO_TO_IRQ(4),
		.end	= PXA_GPIO_TO_IRQ(4),
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
	}
};

static struct smc91x_platdata smc91x_platdata = {
	.flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
		 SMC91X_USE_DMA | SMC91X_NOWAIT,
	.pxa_u16_align4 = true,
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
	.dev.platform_data = &smc91x_platdata,
};

static void idp_backlight_power(int on)
{
	if (on) {
		IDP_CPLD_LCD |= (1<<1);
	} else {
		IDP_CPLD_LCD &= ~(1<<1);
	}
}

static void idp_vlcd(int on)
{
	if (on) {
		IDP_CPLD_LCD |= (1<<2);
	} else {
		IDP_CPLD_LCD &= ~(1<<2);
	}
}

static void idp_lcd_power(int on, struct fb_var_screeninfo *var)
{
	if (on) {
		IDP_CPLD_LCD |= (1<<0);
	} else {
		IDP_CPLD_LCD &= ~(1<<0);
	}

	/* call idp_vlcd for now as core driver does not support
	 * both power and vlcd hooks.  Note, this is not technically
	 * the correct sequence, but seems to work.  Disclaimer:
	 * this may eventually damage the display.
	 */

	idp_vlcd(on);
}

static struct pxafb_mode_info sharp_lm8v31_mode = {
	.pixclock	= 270000,
	.xres		= 640,
	.yres		= 480,
	.bpp		= 16,
	.hsync_len	= 1,
	.left_margin	= 3,
	.right_margin	= 3,
	.vsync_len	= 1,
	.upper_margin	= 0,
	.lower_margin	= 0,
	.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	.cmap_greyscale	= 0,
};

static struct pxafb_mach_info sharp_lm8v31 = {
	.modes          = &sharp_lm8v31_mode,
	.num_modes      = 1,
	.cmap_inverse	= 0,
	.cmap_static	= 0,
	.lcd_conn	= LCD_COLOR_DSTN_16BPP | LCD_PCLK_EDGE_FALL |
			  LCD_AC_BIAS_FREQ(255),
	.pxafb_backlight_power = &idp_backlight_power,
	.pxafb_lcd_power = &idp_lcd_power
};

static struct pxamci_platform_data idp_mci_platform_data = {
	.ocr_mask		= MMC_VDD_32_33|MMC_VDD_33_34,
};

static void __init idp_init(void)
{
	printk("idp_init()\n");

	pxa2xx_mfp_config(ARRAY_AND_SIZE(idp_pin_config));
	pxa_set_ffuart_info(NULL);
	pxa_set_btuart_info(NULL);
	pxa_set_stuart_info(NULL);

	platform_device_register(&smc91x_device);
	//platform_device_register(&mst_audio_device);
	pxa_set_fb_info(NULL, &sharp_lm8v31);
	pxa_set_mci_info(&idp_mci_platform_data);
}

static struct map_desc idp_io_desc[] __initdata = {
  	{
		.virtual	=  IDP_COREVOLT_VIRT,
		.pfn		= __phys_to_pfn(IDP_COREVOLT_PHYS),
		.length		= IDP_COREVOLT_SIZE,
		.type		= MT_DEVICE
	}, {
		.virtual	=  IDP_CPLD_VIRT,
		.pfn		= __phys_to_pfn(IDP_CPLD_PHYS),
		.length		= IDP_CPLD_SIZE,
		.type		= MT_DEVICE
	}
};

static void __init idp_map_io(void)
{
	pxa25x_map_io();
	iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
}

/* LEDs */
#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
struct idp_led {
	struct led_classdev     cdev;
	u8                      mask;
};

/*
 * The triggers lines up below will only be used if the
 * LED triggers are compiled in.
 */
static const struct {
	const char *name;
	const char *trigger;
} idp_leds[] = {
	{ "idp:green", "heartbeat", },
	{ "idp:red", "cpu0", },
};

static void idp_led_set(struct led_classdev *cdev,
		enum led_brightness b)
{
	struct idp_led *led = container_of(cdev,
			struct idp_led, cdev);
	u32 reg = IDP_CPLD_LED_CONTROL;

	if (b != LED_OFF)
		reg &= ~led->mask;
	else
		reg |= led->mask;

	IDP_CPLD_LED_CONTROL = reg;
}

static enum led_brightness idp_led_get(struct led_classdev *cdev)
{
	struct idp_led *led = container_of(cdev,
			struct idp_led, cdev);

	return (IDP_CPLD_LED_CONTROL & led->mask) ? LED_OFF : LED_FULL;
}

static int __init idp_leds_init(void)
{
	int i;

	if (!machine_is_pxa_idp())
		return -ENODEV;

	for (i = 0; i < ARRAY_SIZE(idp_leds); i++) {
		struct idp_led *led;

		led = kzalloc(sizeof(*led), GFP_KERNEL);
		if (!led)
			break;

		led->cdev.name = idp_leds[i].name;
		led->cdev.brightness_set = idp_led_set;
		led->cdev.brightness_get = idp_led_get;
		led->cdev.default_trigger = idp_leds[i].trigger;

		if (i == 0)
			led->mask = IDP_HB_LED;
		else
			led->mask = IDP_BUSY_LED;

		if (led_classdev_register(NULL, &led->cdev) < 0) {
			kfree(led);
			break;
		}
	}

	return 0;
}

/*
 * Since we may have triggers on any subsystem, defer registration
 * until after subsystem_init.
 */
fs_initcall(idp_leds_init);
#endif

MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
	/* Maintainer: Vibren Technologies */
	.map_io		= idp_map_io,
	.nr_irqs	= PXA_NR_IRQS,
	.init_irq	= pxa25x_init_irq,
	.handle_irq	= pxa25x_handle_irq,
	.init_time	= pxa_timer_init,
	.init_machine	= idp_init,
	.restart	= pxa_restart,
MACHINE_END


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  arch/arm/mach-pxa/include/mach/idp.h
 *
 * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
 *
 * 2001-09-13: Cliff Brake <cbrake@accelent.com>
 *             Initial code
 *
 * 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
 *             <http://www.vibren.com> <http://bec-systems.com>
 *             Changes for 2.6 kernel.
 */

/*
 * Note: this file must be safe to include in assembly files
 *
 * Support for the Vibren PXA255 IDP requires rev04 or later
 * IDP hardware.
 */

#include "irqs.h" /* PXA_GPIO_TO_IRQ */

#define IDP_FLASH_PHYS		(PXA_CS0_PHYS)
#define IDP_ALT_FLASH_PHYS	(PXA_CS1_PHYS)
#define IDP_MEDIAQ_PHYS		(PXA_CS3_PHYS)
#define IDP_IDE_PHYS		(PXA_CS5_PHYS + 0x03000000)
#define IDP_ETH_PHYS		(PXA_CS5_PHYS + 0x03400000)
#define IDP_COREVOLT_PHYS	(PXA_CS5_PHYS + 0x03800000)
#define IDP_CPLD_PHYS		(PXA_CS5_PHYS + 0x03C00000)

/*
 * virtual memory map
 */

#define IDP_COREVOLT_VIRT	(0xf0000000)
#define IDP_COREVOLT_SIZE	(1*1024*1024)

#define IDP_CPLD_VIRT		(IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
#define IDP_CPLD_SIZE		(1*1024*1024)

#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
#error Your custom IO space is getting a bit large !!
#endif

#define CPLD_P2V(x)		((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
#define CPLD_V2P(x)		((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)

#ifndef __ASSEMBLY__
#  define __CPLD_REG(x)		(*((volatile unsigned long *)CPLD_P2V(x)))
#else
#  define __CPLD_REG(x)		CPLD_P2V(x)
#endif

/* board level registers in the CPLD: (offsets from CPLD_VIRT) */

#define _IDP_CPLD_REV			(IDP_CPLD_PHYS + 0x00)
#define _IDP_CPLD_PERIPH_PWR		(IDP_CPLD_PHYS + 0x04)
#define _IDP_CPLD_LED_CONTROL		(IDP_CPLD_PHYS + 0x08)
#define _IDP_CPLD_KB_COL_HIGH		(IDP_CPLD_PHYS + 0x0C)
#define _IDP_CPLD_KB_COL_LOW		(IDP_CPLD_PHYS + 0x10)
#define _IDP_CPLD_PCCARD_EN		(IDP_CPLD_PHYS + 0x14)
#define _IDP_CPLD_GPIOH_DIR		(IDP_CPLD_PHYS + 0x18)
#define _IDP_CPLD_GPIOH_VALUE		(IDP_CPLD_PHYS + 0x1C)
#define _IDP_CPLD_GPIOL_DIR		(IDP_CPLD_PHYS + 0x20)
#define _IDP_CPLD_GPIOL_VALUE		(IDP_CPLD_PHYS + 0x24)
#define _IDP_CPLD_PCCARD_PWR		(IDP_CPLD_PHYS + 0x28)
#define _IDP_CPLD_MISC_CTRL		(IDP_CPLD_PHYS + 0x2C)
#define _IDP_CPLD_LCD			(IDP_CPLD_PHYS + 0x30)
#define _IDP_CPLD_FLASH_WE		(IDP_CPLD_PHYS + 0x34)

#define _IDP_CPLD_KB_ROW		(IDP_CPLD_PHYS + 0x50)
#define _IDP_CPLD_PCCARD0_STATUS	(IDP_CPLD_PHYS + 0x54)
#define _IDP_CPLD_PCCARD1_STATUS	(IDP_CPLD_PHYS + 0x58)
#define _IDP_CPLD_MISC_STATUS		(IDP_CPLD_PHYS + 0x5C)

/* FPGA register virtual addresses */

#define IDP_CPLD_REV			__CPLD_REG(_IDP_CPLD_REV)
#define IDP_CPLD_PERIPH_PWR		__CPLD_REG(_IDP_CPLD_PERIPH_PWR)
#define IDP_CPLD_LED_CONTROL		__CPLD_REG(_IDP_CPLD_LED_CONTROL)
#define IDP_CPLD_KB_COL_HIGH		__CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
#define IDP_CPLD_KB_COL_LOW		__CPLD_REG(_IDP_CPLD_KB_COL_LOW)
#define IDP_CPLD_PCCARD_EN		__CPLD_REG(_IDP_CPLD_PCCARD_EN)
#define IDP_CPLD_GPIOH_DIR		__CPLD_REG(_IDP_CPLD_GPIOH_DIR)
#define IDP_CPLD_GPIOH_VALUE		__CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
#define IDP_CPLD_GPIOL_DIR		__CPLD_REG(_IDP_CPLD_GPIOL_DIR)
#define IDP_CPLD_GPIOL_VALUE		__CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
#define IDP_CPLD_PCCARD_PWR		__CPLD_REG(_IDP_CPLD_PCCARD_PWR)
#define IDP_CPLD_MISC_CTRL		__CPLD_REG(_IDP_CPLD_MISC_CTRL)
#define IDP_CPLD_LCD			__CPLD_REG(_IDP_CPLD_LCD)
#define IDP_CPLD_FLASH_WE		__CPLD_REG(_IDP_CPLD_FLASH_WE)

#define IDP_CPLD_KB_ROW		        __CPLD_REG(_IDP_CPLD_KB_ROW)
#define IDP_CPLD_PCCARD0_STATUS	        __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
#define IDP_CPLD_PCCARD1_STATUS	        __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
#define IDP_CPLD_MISC_STATUS		__CPLD_REG(_IDP_CPLD_MISC_STATUS)

/*
 * Bit masks for various registers
 */

// IDP_CPLD_PCCARD_PWR
#define PCC0_PWR0	(1 << 0)
#define PCC0_PWR1	(1 << 1)
#define PCC0_PWR2	(1 << 2)
#define PCC0_PWR3	(1 << 3)
#define PCC1_PWR0	(1 << 4)
#define PCC1_PWR1	(1 << 5)
#define PCC1_PWR2	(1 << 6)
#define PCC1_PWR3	(1 << 7)

// IDP_CPLD_PCCARD_EN
#define PCC0_RESET	(1 << 6)
#define PCC1_RESET	(1 << 7)
#define PCC0_ENABLE	(1 << 0)
#define PCC1_ENABLE	(1 << 1)

// IDP_CPLD_PCCARDx_STATUS
#define _PCC_WRPROT	(1 << 7) // 7-4 read as low true
#define _PCC_RESET	(1 << 6)
#define _PCC_IRQ	(1 << 5)
#define _PCC_INPACK	(1 << 4)
#define PCC_BVD2	(1 << 3)
#define PCC_BVD1	(1 << 2)
#define PCC_VS2		(1 << 1)
#define PCC_VS1		(1 << 0)

/* A listing of interrupts used by external hardware devices */

#define TOUCH_PANEL_IRQ			PXA_GPIO_TO_IRQ(5)
#define IDE_IRQ				PXA_GPIO_TO_IRQ(21)

#define TOUCH_PANEL_IRQ_EDGE		IRQ_TYPE_EDGE_FALLING

#define ETHERNET_IRQ			PXA_GPIO_TO_IRQ(4)
#define ETHERNET_IRQ_EDGE		IRQ_TYPE_EDGE_RISING

#define IDE_IRQ_EDGE			IRQ_TYPE_EDGE_RISING

#define PCMCIA_S0_CD_VALID		PXA_GPIO_TO_IRQ(7)
#define PCMCIA_S0_CD_VALID_EDGE		IRQ_TYPE_EDGE_BOTH

#define PCMCIA_S1_CD_VALID		PXA_GPIO_TO_IRQ(8)
#define PCMCIA_S1_CD_VALID_EDGE		IRQ_TYPE_EDGE_BOTH

#define PCMCIA_S0_RDYINT		PXA_GPIO_TO_IRQ(19)
#define PCMCIA_S1_RDYINT		PXA_GPIO_TO_IRQ(22)

/*
 * Macros for LED Driver
 */

/* leds 0 = ON */
#define IDP_HB_LED	(1<<5)
#define IDP_BUSY_LED	(1<<6)

#define IDP_LEDS_MASK	(IDP_HB_LED | IDP_BUSY_LED)

/*
 * macros for MTD driver
 */

#define FLASH_WRITE_PROTECT_DISABLE()	((IDP_CPLD_FLASH_WE) &= ~(0x1))
#define FLASH_WRITE_PROTECT_ENABLE()	((IDP_CPLD_FLASH_WE) |= (0x1))

/*
 * macros for matrix keyboard driver
 */

#define KEYBD_MATRIX_NUMBER_INPUTS	7
#define KEYBD_MATRIX_NUMBER_OUTPUTS	14

#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC	FALSE
#define KEYBD_MATRIX_INVERT_INPUT_LOGIC		FALSE

#define KEYBD_MATRIX_SETTLING_TIME_US			100
#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT		2

#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
{\
	IDP_CPLD_KB_COL_LOW = outputs;\
	IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
}

#define KEYBD_MATRIX_GET_INPUTS(inputs) \
{\
	inputs = (IDP_CPLD_KB_ROW & 0x7f);\
}


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 *  linux/arch/arm/mach-pxa/irq.c
 *
 *  Generic PXA IRQ handling
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 */
#include <linux/bitops.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/syscore_ops.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/soc/pxa/cpu.h>

#include <asm/exception.h>

#include "irqs.h"

#include "generic.h"
#include "pxa-regs.h"

#define ICIP			(0x000)
#define ICMR			(0x004)
#define ICLR			(0x008)
#define ICFR			(0x00c)
#define ICPR			(0x010)
#define ICCR			(0x014)
#define ICHP			(0x018)
#define IPR(i)			(((i) < 32) ? (0x01c + ((i) << 2)) :		\
				((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) :	\
				      (0x144 + (((i) - 64) << 2)))
#define ICHP_VAL_IRQ		(1 << 31)
#define ICHP_IRQ(i)		(((i) >> 16) & 0x7fff)
#define IPR_VALID		(1 << 31)

#define MAX_INTERNAL_IRQS	128

/*
 * This is for peripheral IRQs internal to the PXA chip.
 */

static void __iomem *pxa_irq_base;
static int pxa_internal_irq_nr;
static bool cpu_has_ipr;
static struct irq_domain *pxa_irq_domain;

static inline void __iomem *irq_base(int i)
{
	static unsigned long phys_base_offset[] = {
		0x0,
		0x9c,
		0x130,
	};

	return pxa_irq_base + phys_base_offset[i];
}

void pxa_mask_irq(struct irq_data *d)
{
	void __iomem *base = irq_data_get_irq_chip_data(d);
	irq_hw_number_t irq = irqd_to_hwirq(d);
	uint32_t icmr = __raw_readl(base + ICMR);

	icmr &= ~BIT(irq & 0x1f);
	__raw_writel(icmr, base + ICMR);
}

void pxa_unmask_irq(struct irq_data *d)
{
	void __iomem *base = irq_data_get_irq_chip_data(d);
	irq_hw_number_t irq = irqd_to_hwirq(d);
	uint32_t icmr = __raw_readl(base + ICMR);

	icmr |= BIT(irq & 0x1f);
	__raw_writel(icmr, base + ICMR);
}

static struct irq_chip pxa_internal_irq_chip = {
	.name		= "SC",
	.irq_ack	= pxa_mask_irq,
	.irq_mask	= pxa_mask_irq,
	.irq_unmask	= pxa_unmask_irq,
};

asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
{
	uint32_t icip, icmr, mask;

	do {
		icip = __raw_readl(pxa_irq_base + ICIP);
		icmr = __raw_readl(pxa_irq_base + ICMR);
		mask = icip & icmr;

		if (mask == 0)
			break;

		handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
	} while (1);
}

asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
{
	uint32_t ichp;

	do {
		__asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));

		if ((ichp & ICHP_VAL_IRQ) == 0)
			break;

		handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
	} while (1);
}

static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
		       irq_hw_number_t hw)
{
	void __iomem *base = irq_base(hw / 32);

	/* initialize interrupt priority */
	if (cpu_has_ipr)
		__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));

	irq_set_chip_and_handler(virq, &pxa_internal_irq_chip,
				 handle_level_irq);
	irq_set_chip_data(virq, base);

	return 0;
}

static const struct irq_domain_ops pxa_irq_ops = {
	.map    = pxa_irq_map,
	.xlate  = irq_domain_xlate_onecell,
};

static __init void
pxa_init_irq_common(struct device_node *node, int irq_nr,
		    int (*fn)(struct irq_data *, unsigned int))
{
	int n;

	pxa_internal_irq_nr = irq_nr;
	pxa_irq_domain = irq_domain_add_legacy(node, irq_nr,
					       PXA_IRQ(0), 0,
					       &pxa_irq_ops, NULL);
	if (!pxa_irq_domain)
		panic("Unable to add PXA IRQ domain\n");
	irq_set_default_host(pxa_irq_domain);

	for (n = 0; n < irq_nr; n += 32) {
		void __iomem *base = irq_base(n >> 5);

		__raw_writel(0, base + ICMR);	/* disable all IRQs */
		__raw_writel(0, base + ICLR);	/* all IRQs are IRQ, not FIQ */
	}
	/* only unmasked interrupts kick us out of idle */
	__raw_writel(1, irq_base(0) + ICCR);

	pxa_internal_irq_chip.irq_set_wake = fn;
}

void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
{
	BUG_ON(irq_nr > MAX_INTERNAL_IRQS);

	pxa_irq_base = io_p2v(0x40d00000);
	cpu_has_ipr = !cpu_is_pxa25x();
	pxa_init_irq_common(NULL, irq_nr, fn);
}

#ifdef CONFIG_PM
static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
static unsigned long saved_ipr[MAX_INTERNAL_IRQS];

static int pxa_irq_suspend(void)
{
	int i;

	for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) {
		void __iomem *base = irq_base(i);

		saved_icmr[i] = __raw_readl(base + ICMR);
		__raw_writel(0, base + ICMR);
	}

	if (cpu_has_ipr) {
		for (i = 0; i < pxa_internal_irq_nr; i++)
			saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));
	}

	return 0;
}

static void pxa_irq_resume(void)
{
	int i;

	for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) {
		void __iomem *base = irq_base(i);

		__raw_writel(saved_icmr[i], base + ICMR);
		__raw_writel(0, base + ICLR);
	}

	if (cpu_has_ipr)
		for (i = 0; i < pxa_internal_irq_nr; i++)
			__raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));

	__raw_writel(1, pxa_irq_base + ICCR);
}
#else
#define pxa_irq_suspend		NULL
#define pxa_irq_resume		NULL
#endif

struct syscore_ops pxa_irq_syscore_ops = {
	.suspend	= pxa_irq_suspend,
	.resume		= pxa_irq_resume,
};

#ifdef CONFIG_OF
static const struct of_device_id intc_ids[] __initconst = {
	{ .compatible = "marvell,pxa-intc", },
	{}
};

void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
{
	struct device_node *node;
	struct resource res;
	int ret;

	node = of_find_matching_node(NULL, intc_ids);
	if (!node) {
		pr_err("Failed to find interrupt controller in arch-pxa\n");
		return;
	}

	ret = of_property_read_u32(node, "marvell,intc-nr-irqs",
				   &pxa_internal_irq_nr);
	if (ret) {
		pr_err("Not found marvell,intc-nr-irqs property\n");
		return;
	}

	ret = of_address_to_resource(node, 0, &res);
	if (ret < 0) {
		pr_err("No registers defined for node\n");
		return;
	}
	pxa_irq_base = io_p2v(res.start);

	if (of_find_property(node, "marvell,intc-priority", NULL))
		cpu_has_ipr = 1;

	ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
	if (ret < 0) {
		pr_err("Failed to allocate IRQ numbers\n");
		return;
	}

	pxa_init_irq_common(node, pxa_internal_irq_nr, fn);
}
#endif /* CONFIG_OF */


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  arch/arm/mach-pxa/include/mach/irqs.h
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 */
#ifndef __ASM_MACH_IRQS_H
#define __ASM_MACH_IRQS_H

#include <asm/irq.h>

#define PXA_ISA_IRQ(x)	(x)
#define PXA_IRQ(x)	(NR_IRQS_LEGACY + (x))

#define IRQ_SSP3	PXA_IRQ(0)	/* SSP3 service request */
#define IRQ_MSL		PXA_IRQ(1)	/* MSL Interface interrupt */
#define IRQ_USBH2	PXA_IRQ(2)	/* USB Host interrupt 1 (OHCI,PXA27x) */
#define IRQ_USBH1	PXA_IRQ(3)	/* USB Host interrupt 2 (non-OHCI,PXA27x) */
#define IRQ_KEYPAD	PXA_IRQ(4)	/* Key pad controller */
#define IRQ_MEMSTK	PXA_IRQ(5)	/* Memory Stick interrupt (PXA27x) */
#define IRQ_ACIPC0	PXA_IRQ(5)	/* AP-CP Communication (PXA930) */
#define IRQ_PWRI2C	PXA_IRQ(6)	/* Power I2C interrupt */
#define IRQ_HWUART	PXA_IRQ(7)	/* HWUART Transmit/Receive/Error (PXA26x) */
#define IRQ_OST_4_11	PXA_IRQ(7)	/* OS timer 4-11 matches (PXA27x) */
#define	IRQ_GPIO0	PXA_IRQ(8)	/* GPIO0 Edge Detect */
#define	IRQ_GPIO1	PXA_IRQ(9)	/* GPIO1 Edge Detect */
#define	IRQ_GPIO_2_x	PXA_IRQ(10)	/* GPIO[2-x] Edge Detect */
#define	IRQ_USB		PXA_IRQ(11)	/* USB Service */
#define	IRQ_PMU		PXA_IRQ(12)	/* Performance Monitoring Unit */
#define	IRQ_I2S		PXA_IRQ(13)	/* I2S Interrupt (PXA27x) */
#define IRQ_SSP4	PXA_IRQ(13)	/* SSP4 service request (PXA3xx) */
#define	IRQ_AC97	PXA_IRQ(14)	/* AC97 Interrupt */
#define IRQ_ASSP	PXA_IRQ(15)	/* Audio SSP Service Request (PXA25x) */
#define IRQ_USIM	PXA_IRQ(15)     /* Smart Card interface interrupt (PXA27x) */
#define IRQ_NSSP	PXA_IRQ(16)	/* Network SSP Service Request (PXA25x) */
#define IRQ_SSP2	PXA_IRQ(16)	/* SSP2 interrupt (PXA27x) */
#define	IRQ_LCD		PXA_IRQ(17)	/* LCD Controller Service Request */
#define	IRQ_I2C		PXA_IRQ(18)	/* I2C Service Request */
#define	IRQ_ICP		PXA_IRQ(19)	/* ICP Transmit/Receive/Error */
#define IRQ_ACIPC2	PXA_IRQ(19)	/* AP-CP Communication (PXA930) */
#define	IRQ_STUART	PXA_IRQ(20)	/* STUART Transmit/Receive/Error */
#define	IRQ_BTUART	PXA_IRQ(21)	/* BTUART Transmit/Receive/Error */
#define	IRQ_FFUART	PXA_IRQ(22)	/* FFUART Transmit/Receive/Error*/
#define	IRQ_MMC		PXA_IRQ(23)	/* MMC Status/Error Detection */
#define	IRQ_SSP		PXA_IRQ(24)	/* SSP Service Request */
#define	IRQ_DMA 	PXA_IRQ(25)	/* DMA Channel Service Request */
#define	IRQ_OST0 	PXA_IRQ(26)	/* OS Timer match 0 */
#define	IRQ_OST1 	PXA_IRQ(27)	/* OS Timer match 1 */
#define	IRQ_OST2 	PXA_IRQ(28)	/* OS Timer match 2 */
#define	IRQ_OST3 	PXA_IRQ(29)	/* OS Timer match 3 */
#define	IRQ_RTC1Hz	PXA_IRQ(30)	/* RTC HZ Clock Tick */
#define	IRQ_RTCAlrm	PXA_IRQ(31)	/* RTC Alarm */

#define IRQ_TPM		PXA_IRQ(32)	/* TPM interrupt */
#define IRQ_CAMERA	PXA_IRQ(33)	/* Camera Interface */
#define IRQ_CIR		PXA_IRQ(34)	/* Consumer IR */
#define IRQ_COMM_WDT	PXA_IRQ(35) 	/* Comm WDT interrupt */
#define IRQ_TSI		PXA_IRQ(36)	/* Touch Screen Interface (PXA320) */
#define IRQ_ENHROT	PXA_IRQ(37)	/* Enhanced Rotary (PXA930) */
#define IRQ_USIM2	PXA_IRQ(38)	/* USIM2 Controller */
#define IRQ_GCU		PXA_IRQ(39)	/* Graphics Controller (PXA3xx) */
#define IRQ_ACIPC1	PXA_IRQ(40)	/* AP-CP Communication (PXA930) */
#define IRQ_MMC2	PXA_IRQ(41)	/* MMC2 Controller */
#define IRQ_TRKBALL	PXA_IRQ(43)	/* Track Ball (PXA930) */
#define IRQ_1WIRE	PXA_IRQ(44)	/* 1-Wire Controller */
#define IRQ_NAND	PXA_IRQ(45)	/* NAND Controller */
#define IRQ_USB2	PXA_IRQ(46)	/* USB 2.0 Device Controller */
#define IRQ_WAKEUP0	PXA_IRQ(49)	/* EXT_WAKEUP0 */
#define IRQ_WAKEUP1	PXA_IRQ(50)	/* EXT_WAKEUP1 */
#define IRQ_DMEMC	PXA_IRQ(51)	/* Dynamic Memory Controller */
#define IRQ_MMC3	PXA_IRQ(55)	/* MMC3 Controller (PXA310) */

#define IRQ_U2O		PXA_IRQ(64)	/* USB OTG 2.0 Controller (PXA935) */
#define IRQ_U2H		PXA_IRQ(65)	/* USB Host 2.0 Controller (PXA935) */
#define IRQ_PXA935_MMC0	PXA_IRQ(72)	/* MMC0 Controller (PXA935) */
#define IRQ_PXA935_MMC1	PXA_IRQ(73)	/* MMC1 Controller (PXA935) */
#define IRQ_PXA935_MMC2	PXA_IRQ(74)	/* MMC2 Controller (PXA935) */
#define IRQ_U2P		PXA_IRQ(93)	/* USB PHY D+/D- Lines (PXA935) */

#define PXA_GPIO_IRQ_BASE	PXA_IRQ(96)
#define PXA_NR_BUILTIN_GPIO	(192)
#define PXA_GPIO_TO_IRQ(x)	(PXA_GPIO_IRQ_BASE + (x))

/*
 * The following interrupts are for board specific purposes. Since
 * the kernel can only run on one machine at a time, we can re-use
 * these.
 * By default, no board IRQ is reserved. It should be finished in
 * custom board since sparse IRQ is already enabled.
 */
#define IRQ_BOARD_START		(PXA_GPIO_IRQ_BASE + PXA_NR_BUILTIN_GPIO)

#define PXA_NR_IRQS		(IRQ_BOARD_START)

#ifndef __ASSEMBLY__
struct irq_data;
struct pt_regs;

void pxa_mask_irq(struct irq_data *);
void pxa_unmask_irq(struct irq_data *);
void icip_handle_irq(struct pt_regs *);
void ichp_handle_irq(struct pt_regs *);

void pxa_init_irq(int irq_nr, int (*set_wake)(struct irq_data *, unsigned int));
#endif

#endif /* __ASM_MACH_IRQS_H */


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 *  linux/arch/arm/mach-pxa/littleton.c
 *
 *  Support for the Marvell Littleton Development Platform.
 *
 *  Author:	Jason Chagas (largely modified code)
 *  Created:	Nov 20, 2006
 *  Copyright:	(C) Copyright 2006 Marvell International Ltd.
 *
 *  2007-11-22  modified to align with latest kernel
 *              eric miao <eric.miao@marvell.com>
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/gpio/machine.h>
#include <linux/spi/spi.h>
#include <linux/spi/pxa2xx_spi.h>
#include <linux/smc91x.h>
#include <linux/i2c.h>
#include <linux/leds.h>
#include <linux/mfd/da903x.h>
#include <linux/platform_data/max732x.h>
#include <linux/platform_data/i2c-pxa.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <asm/irq.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include "pxa300.h"
#include "devices.h"
#include <linux/platform_data/video-pxafb.h>
#include <linux/platform_data/mmc-pxamci.h>
#include <linux/platform_data/keypad-pxa27x.h>
#include "littleton.h"
#include <linux/platform_data/mtd-nand-pxa3xx.h>

#include "generic.h"

/* Littleton MFP configurations */
static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
	/* LCD */
	GPIO54_LCD_LDD_0,
	GPIO55_LCD_LDD_1,
	GPIO56_LCD_LDD_2,
	GPIO57_LCD_LDD_3,
	GPIO58_LCD_LDD_4,
	GPIO59_LCD_LDD_5,
	GPIO60_LCD_LDD_6,
	GPIO61_LCD_LDD_7,
	GPIO62_LCD_LDD_8,
	GPIO63_LCD_LDD_9,
	GPIO64_LCD_LDD_10,
	GPIO65_LCD_LDD_11,
	GPIO66_LCD_LDD_12,
	GPIO67_LCD_LDD_13,
	GPIO68_LCD_LDD_14,
	GPIO69_LCD_LDD_15,
	GPIO70_LCD_LDD_16,
	GPIO71_LCD_LDD_17,
	GPIO72_LCD_FCLK,
	GPIO73_LCD_LCLK,
	GPIO74_LCD_PCLK,
	GPIO75_LCD_BIAS,

	/* SSP2 */
	GPIO25_SSP2_SCLK,
	GPIO27_SSP2_TXD,
	GPIO17_GPIO,	/* SFRM as chip-select */

	/* Debug Ethernet */
	GPIO90_GPIO,

	/* Keypad */
	GPIO107_KP_DKIN_0,
	GPIO108_KP_DKIN_1,
	GPIO115_KP_MKIN_0,
	GPIO116_KP_MKIN_1,
	GPIO117_KP_MKIN_2,
	GPIO118_KP_MKIN_3,
	GPIO119_KP_MKIN_4,
	GPIO120_KP_MKIN_5,
	GPIO121_KP_MKOUT_0,
	GPIO122_KP_MKOUT_1,
	GPIO123_KP_MKOUT_2,
	GPIO124_KP_MKOUT_3,
	GPIO125_KP_MKOUT_4,

	/* MMC1 */
	GPIO3_MMC1_DAT0,
	GPIO4_MMC1_DAT1,
	GPIO5_MMC1_DAT2,
	GPIO6_MMC1_DAT3,
	GPIO7_MMC1_CLK,
	GPIO8_MMC1_CMD,
	GPIO15_GPIO, /* card detect */

	/* UART3 */
	GPIO107_UART3_CTS,
	GPIO108_UART3_RTS,
	GPIO109_UART3_TXD,
	GPIO110_UART3_RXD,
};

static struct resource smc91x_resources[] = {
	[0] = {
		.start	= (LITTLETON_ETH_PHYS + 0x300),
		.end	= (LITTLETON_ETH_PHYS + 0xfffff),
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO90)),
		.end	= PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO90)),
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
	}
};

static struct smc91x_platdata littleton_smc91x_info = {
	.flags	= SMC91X_USE_8BIT | SMC91X_USE_16BIT |
		  SMC91X_NOWAIT | SMC91X_USE_DMA,
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
	.dev		= {
		.platform_data = &littleton_smc91x_info,
	},
};

#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static struct pxafb_mode_info tpo_tdo24mtea1_modes[] = {
	[0] = {
		/* VGA */
		.pixclock	= 38250,
		.xres		= 480,
		.yres		= 640,
		.bpp		= 16,
		.hsync_len	= 8,
		.left_margin	= 8,
		.right_margin	= 24,
		.vsync_len	= 2,
		.upper_margin	= 2,
		.lower_margin	= 4,
		.sync		= 0,
	},
	[1] = {
		/* QVGA */
		.pixclock	= 153000,
		.xres		= 240,
		.yres		= 320,
		.bpp		= 16,
		.hsync_len	= 8,
		.left_margin	= 8,
		.right_margin	= 88,
		.vsync_len	= 2,
		.upper_margin	= 2,
		.lower_margin	= 2,
		.sync		= 0,
	},
};

static struct pxafb_mach_info littleton_lcd_info = {
	.modes			= tpo_tdo24mtea1_modes,
	.num_modes		= 2,
	.lcd_conn		= LCD_COLOR_TFT_16BPP,
};

static void __init littleton_init_lcd(void)
{
	pxa_set_fb_info(NULL, &littleton_lcd_info);
}
#else
static inline void littleton_init_lcd(void) {};
#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */

#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
static struct pxa2xx_spi_controller littleton_spi_info = {
	.num_chipselect		= 1,
};

static struct pxa2xx_spi_chip littleton_tdo24m_chip = {
	.rx_threshold	= 1,
	.tx_threshold	= 1,
};

static struct spi_board_info littleton_spi_devices[] __initdata = {
	{
		.modalias	= "tdo24m",
		.max_speed_hz	= 1000000,
		.bus_num	= 2,
		.chip_select	= 0,
		.controller_data= &littleton_tdo24m_chip,
	},
};

static struct gpiod_lookup_table littleton_spi_gpio_table = {
	.dev_id = "spi2",
	.table = {
		GPIO_LOOKUP_IDX("gpio-pxa", LITTLETON_GPIO_LCD_CS, "cs", 0, GPIO_ACTIVE_LOW),
		{ },
	},
};

static void __init littleton_init_spi(void)
{
	gpiod_add_lookup_table(&littleton_spi_gpio_table);
	pxa2xx_set_spi_info(2, &littleton_spi_info);
	spi_register_board_info(ARRAY_AND_SIZE(littleton_spi_devices));
}
#else
static inline void littleton_init_spi(void) {}
#endif

#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
static const unsigned int littleton_matrix_key_map[] = {
	/* KEY(row, col, key_code) */
	KEY(1, 3, KEY_0), KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3),
	KEY(0, 1, KEY_4), KEY(1, 1, KEY_5), KEY(2, 1, KEY_6), KEY(0, 2, KEY_7),
	KEY(1, 2, KEY_8), KEY(2, 2, KEY_9),

	KEY(0, 3, KEY_KPASTERISK), 	/* * */
	KEY(2, 3, KEY_KPDOT), 		/* # */

	KEY(5, 4, KEY_ENTER),

	KEY(5, 0, KEY_UP),
	KEY(5, 1, KEY_DOWN),
	KEY(5, 2, KEY_LEFT),
	KEY(5, 3, KEY_RIGHT),
	KEY(3, 2, KEY_HOME),
	KEY(4, 1, KEY_END),
	KEY(3, 3, KEY_BACK),

	KEY(4, 0, KEY_SEND),
	KEY(4, 2, KEY_VOLUMEUP),
	KEY(4, 3, KEY_VOLUMEDOWN),

	KEY(3, 0, KEY_F22),	/* soft1 */
	KEY(3, 1, KEY_F23),	/* soft2 */
};

static struct matrix_keymap_data littleton_matrix_keymap_data = {
	.keymap			= littleton_matrix_key_map,
	.keymap_size		= ARRAY_SIZE(littleton_matrix_key_map),
};

static struct pxa27x_keypad_platform_data littleton_keypad_info = {
	.matrix_key_rows	= 6,
	.matrix_key_cols	= 5,
	.matrix_keymap_data	= &littleton_matrix_keymap_data,

	.enable_rotary0		= 1,
	.rotary0_up_key		= KEY_UP,
	.rotary0_down_key	= KEY_DOWN,

	.debounce_interval	= 30,
};
static void __init littleton_init_keypad(void)
{
	pxa_set_keypad_info(&littleton_keypad_info);
}
#else
static inline void littleton_init_keypad(void) {}
#endif

#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
static struct pxamci_platform_data littleton_mci_platform_data = {
	.detect_delay_ms	= 200,
	.ocr_mask		= MMC_VDD_32_33 | MMC_VDD_33_34,
};

static struct gpiod_lookup_table littleton_mci_gpio_table = {
	.dev_id = "pxa2xx-mci.0",
	.table = {
		/* Card detect on MFP (gpio-pxa) GPIO 15 */
		GPIO_LOOKUP("gpio-pxa", MFP_PIN_GPIO15,
			    "cd", GPIO_ACTIVE_LOW),
		{ },
	},
};

static void __init littleton_init_mmc(void)
{
	gpiod_add_lookup_table(&littleton_mci_gpio_table);
	pxa_set_mci_info(&littleton_mci_platform_data);
}
#else
static inline void littleton_init_mmc(void) {}
#endif

#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
static struct mtd_partition littleton_nand_partitions[] = {
	[0] = {
		.name        = "Bootloader",
		.offset      = 0,
		.size        = 0x060000,
		.mask_flags  = MTD_WRITEABLE, /* force read-only */
	},
	[1] = {
		.name        = "Kernel",
		.offset      = 0x060000,
		.size        = 0x200000,
		.mask_flags  = MTD_WRITEABLE, /* force read-only */
	},
	[2] = {
		.name        = "Filesystem",
		.offset      = 0x0260000,
		.size        = 0x3000000,     /* 48M - rootfs */
	},
	[3] = {
		.name        = "MassStorage",
		.offset      = 0x3260000,
		.size        = 0x3d40000,
	},
	[4] = {
		.name        = "BBT",
		.offset      = 0x6FA0000,
		.size        = 0x80000,
		.mask_flags  = MTD_WRITEABLE,  /* force read-only */
	},
	/* NOTE: we reserve some blocks at the end of the NAND flash for
	 * bad block management, and the max number of relocation blocks
	 * differs on different platforms. Please take care with it when
	 * defining the partition table.
	 */
};

static struct pxa3xx_nand_platform_data littleton_nand_info = {
	.parts		= littleton_nand_partitions,
	.nr_parts	= ARRAY_SIZE(littleton_nand_partitions),
};

static void __init littleton_init_nand(void)
{
	pxa3xx_set_nand_info(&littleton_nand_info);
}
#else
static inline void littleton_init_nand(void) {}
#endif /* IS_ENABLED(CONFIG_MTD_NAND_MARVELL) */

#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
static struct led_info littleton_da9034_leds[] = {
	[0] = {
		.name	= "littleton:keypad1",
		.flags	= DA9034_LED_RAMP,
	},
	[1] = {
		.name	= "littleton:keypad2",
		.flags	= DA9034_LED_RAMP,
	},
	[2] = {
		.name	= "littleton:vibra",
		.flags	= 0,
	},
};

static struct da9034_touch_pdata littleton_da9034_touch = {
	.x_inverted     = 1,
	.interval_ms    = 20,
};

static struct da903x_subdev_info littleton_da9034_subdevs[] = {
	{
		.name		= "da903x-led",
		.id		= DA9034_ID_LED_1,
		.platform_data	= &littleton_da9034_leds[0],
	}, {
		.name		= "da903x-led",
		.id		= DA9034_ID_LED_2,
		.platform_data	= &littleton_da9034_leds[1],
	}, {
		.name		= "da903x-led",
		.id		= DA9034_ID_VIBRA,
		.platform_data	= &littleton_da9034_leds[2],
	}, {
		.name		= "da903x-backlight",
		.id		= DA9034_ID_WLED,
	}, {
		.name		= "da9034-touch",
		.id		= DA9034_ID_TOUCH,
		.platform_data	= &littleton_da9034_touch,
	},
};

static struct da903x_platform_data littleton_da9034_info = {
	.num_subdevs	= ARRAY_SIZE(littleton_da9034_subdevs),
	.subdevs	= littleton_da9034_subdevs,
};

static struct max732x_platform_data littleton_max7320_info = {
	.gpio_base	= EXT0_GPIO_BASE,
};

static struct i2c_board_info littleton_i2c_info[] = {
	[0] = {
		.type		= "da9034",
		.addr		= 0x34,
		.platform_data	= &littleton_da9034_info,
		.irq		= PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO18)),
	},
	[1] = {
		.type		= "max7320",
		.addr		= 0x50,
		.platform_data	= &littleton_max7320_info,
	},
};

static void __init littleton_init_i2c(void)
{
	pxa_set_i2c_info(NULL);
	i2c_register_board_info(0, ARRAY_AND_SIZE(littleton_i2c_info));
}
#else
static inline void littleton_init_i2c(void) {}
#endif /* CONFIG_I2C_PXA || CONFIG_I2C_PXA_MODULE */

static void __init littleton_init(void)
{
	/* initialize MFP configurations */
	pxa3xx_mfp_config(ARRAY_AND_SIZE(littleton_mfp_cfg));

	pxa_set_ffuart_info(NULL);
	pxa_set_btuart_info(NULL);
	pxa_set_stuart_info(NULL);

	/*
	 * Note: we depend bootloader set the correct
	 * value to MSC register for SMC91x.
	 */
	platform_device_register(&smc91x_device);

	littleton_init_spi();
	littleton_init_i2c();
	littleton_init_mmc();
	littleton_init_lcd();
	littleton_init_keypad();
	littleton_init_nand();
}

MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
	.atag_offset	= 0x100,
	.map_io		= pxa3xx_map_io,
	.nr_irqs	= LITTLETON_NR_IRQS,
	.init_irq	= pxa3xx_init_irq,
	.handle_irq	= pxa3xx_handle_irq,
	.init_time	= pxa_timer_init,
	.init_machine	= littleton_init,
	.restart	= pxa_restart,
MACHINE_END


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_ARCH_LITTLETON_H
#define __ASM_ARCH_LITTLETON_H

#define LITTLETON_ETH_PHYS	0x30000000

#define LITTLETON_GPIO_LCD_CS	(17)

#define EXT0_GPIO_BASE	(PXA_NR_BUILTIN_GPIO)
#define EXT0_GPIO(x)	(EXT0_GPIO_BASE + (x))

#define LITTLETON_NR_IRQS	(IRQ_BOARD_START + 8)

#endif /* __ASM_ARCH_LITTLETON_H */


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * linux/arch/arm/mach-pxa/lpd270.c
 *
 * Support for the LogicPD PXA270 Card Engine.
 * Derived from the mainstone code, which carries these notices:
 *
 * Author:	Nicolas Pitre
 * Created:	Nov 05, 2002
 * Copyright:	MontaVista Software Inc.
 */
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/bitops.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/smc91x.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <linux/sizes.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>

#include "pxa27x.h"
#include "lpd270.h"
#include "addr-map.h"
#include <linux/platform_data/asoc-pxa.h>
#include <linux/platform_data/video-pxafb.h>
#include <linux/platform_data/mmc-pxamci.h>
#include <linux/platform_data/irda-pxaficp.h>
#include <linux/platform_data/usb-ohci-pxa27x.h>
#include "smemc.h"

#include "generic.h"
#include "devices.h"

static unsigned long lpd270_pin_config[] __initdata = {
	/* Chip Selects */
	GPIO15_nCS_1,	/* Mainboard Flash */
	GPIO78_nCS_2,	/* CPLD + Ethernet */

	/* LCD - 16bpp Active TFT */
	GPIO58_LCD_LDD_0,
	GPIO59_LCD_LDD_1,
	GPIO60_LCD_LDD_2,
	GPIO61_LCD_LDD_3,
	GPIO62_LCD_LDD_4,
	GPIO63_LCD_LDD_5,
	GPIO64_LCD_LDD_6,
	GPIO65_LCD_LDD_7,
	GPIO66_LCD_LDD_8,
	GPIO67_LCD_LDD_9,
	GPIO68_LCD_LDD_10,
	GPIO69_LCD_LDD_11,
	GPIO70_LCD_LDD_12,
	GPIO71_LCD_LDD_13,
	GPIO72_LCD_LDD_14,
	GPIO73_LCD_LDD_15,
	GPIO74_LCD_FCLK,
	GPIO75_LCD_LCLK,
	GPIO76_LCD_PCLK,
	GPIO77_LCD_BIAS,
	GPIO16_PWM0_OUT,	/* Backlight */

	/* USB Host */
	GPIO88_USBH1_PWR,
	GPIO89_USBH1_PEN,

	/* AC97 */
	GPIO28_AC97_BITCLK,
	GPIO29_AC97_SDATA_IN_0,
	GPIO30_AC97_SDATA_OUT,
	GPIO31_AC97_SYNC,
	GPIO45_AC97_SYSCLK,

	GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
};

static unsigned int lpd270_irq_enabled;

static void lpd270_mask_irq(struct irq_data *d)
{
	int lpd270_irq = d->irq - LPD270_IRQ(0);

	__raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);

	lpd270_irq_enabled &= ~(1 << lpd270_irq);
	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
}

static void lpd270_unmask_irq(struct irq_data *d)
{
	int lpd270_irq = d->irq - LPD270_IRQ(0);

	lpd270_irq_enabled |= 1 << lpd270_irq;
	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
}

static struct irq_chip lpd270_irq_chip = {
	.name		= "CPLD",
	.irq_ack	= lpd270_mask_irq,
	.irq_mask	= lpd270_mask_irq,
	.irq_unmask	= lpd270_unmask_irq,
};

static void lpd270_irq_handler(struct irq_desc *desc)
{
	unsigned int irq;
	unsigned long pending;

	pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
	do {
		/* clear useless edge notification */
		desc->irq_data.chip->irq_ack(&desc->irq_data);
		if (likely(pending)) {
			irq = LPD270_IRQ(0) + __ffs(pending);
			generic_handle_irq(irq);

			pending = __raw_readw(LPD270_INT_STATUS) &
						lpd270_irq_enabled;
		}
	} while (pending);
}

static void __init lpd270_init_irq(void)
{
	int irq;

	pxa27x_init_irq();

	__raw_writew(0, LPD270_INT_MASK);
	__raw_writew(0, LPD270_INT_STATUS);

	/* setup extra LogicPD PXA270 irqs */
	for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
		irq_set_chip_and_handler(irq, &lpd270_irq_chip,
					 handle_level_irq);
		irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
	}
	irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
	irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
}

#ifdef CONFIG_PM
static void lpd270_irq_resume(void)
{
	__raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
}

static struct syscore_ops lpd270_irq_syscore_ops = {
	.resume = lpd270_irq_resume,
};

static int __init lpd270_irq_device_init(void)
{
	if (machine_is_logicpd_pxa270()) {
		register_syscore_ops(&lpd270_irq_syscore_ops);
		return 0;
	}
	return -ENODEV;
}

device_initcall(lpd270_irq_device_init);
#endif

static struct resource smc91x_resources[] = {
	[0] = {
		.start	= LPD270_ETH_PHYS,
		.end	= (LPD270_ETH_PHYS + 0xfffff),
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= LPD270_ETHERNET_IRQ,
		.end	= LPD270_ETHERNET_IRQ,
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
	},
};

struct smc91x_platdata smc91x_platdata = {
	.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
	.dev.platform_data = &smc91x_platdata,
};

static struct resource lpd270_flash_resources[] = {
	[0] = {
		.start	= PXA_CS0_PHYS,
		.end	= PXA_CS0_PHYS + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= PXA_CS1_PHYS,
		.end	= PXA_CS1_PHYS + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct mtd_partition lpd270_flash0_partitions[] = {
	{
		.name =		"Bootloader",
		.size =		0x00040000,
		.offset =	0,
		.mask_flags =	MTD_WRITEABLE  /* force read-only */
	}, {
		.name =		"Kernel",
		.size =		0x00400000,
		.offset =	0x00040000,
	}, {
		.name =		"Filesystem",
		.size =		MTDPART_SIZ_FULL,
		.offset =	0x00440000
	},
};

static struct flash_platform_data lpd270_flash_data[2] = {
	{
		.name		= "processor-flash",
		.map_name	= "cfi_probe",
		.parts		= lpd270_flash0_partitions,
		.nr_parts	= ARRAY_SIZE(lpd270_flash0_partitions),
	}, {
		.name		= "mainboard-flash",
		.map_name	= "cfi_probe",
		.parts		= NULL,
		.nr_parts	= 0,
	}
};

static struct platform_device lpd270_flash_device[2] = {
	{
		.name		= "pxa2xx-flash",
		.id		= 0,
		.dev = {
			.platform_data	= &lpd270_flash_data[0],
		},
		.resource	= &lpd270_flash_resources[0],
		.num_resources	= 1,
	}, {
		.name		= "pxa2xx-flash",
		.id		= 1,
		.dev = {
			.platform_data	= &lpd270_flash_data[1],
		},
		.resource	= &lpd270_flash_resources[1],
		.num_resources	= 1,
	},
};

static struct pwm_lookup lpd270_pwm_lookup[] = {
	PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
		   PWM_POLARITY_NORMAL),
};

static struct platform_pwm_backlight_data lpd270_backlight_data = {
	.max_brightness	= 1,
	.dft_brightness	= 1,
};

static struct platform_device lpd270_backlight_device = {
	.name		= "pwm-backlight",
	.dev		= {
		.parent	= &pxa27x_device_pwm0.dev,
		.platform_data = &lpd270_backlight_data,
	},
};

/* 5.7" TFT QVGA (LoLo display number 1) */
static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
	.pixclock		= 150000,
	.xres			= 320,
	.yres			= 240,
	.bpp			= 16,
	.hsync_len		= 0x14,
	.left_margin		= 0x28,
	.right_margin		= 0x0a,
	.vsync_len		= 0x02,
	.upper_margin		= 0x08,
	.lower_margin		= 0x14,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq057q3dc02 = {
	.modes			= &sharp_lq057q3dc02_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 12.1" TFT SVGA (LoLo display number 2) */
static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
	.pixclock		= 50000,
	.xres			= 800,
	.yres			= 600,
	.bpp			= 16,
	.hsync_len		= 0x05,
	.left_margin		= 0x52,
	.right_margin		= 0x05,
	.vsync_len		= 0x04,
	.upper_margin		= 0x14,
	.lower_margin		= 0x0a,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq121s1dg31 = {
	.modes			= &sharp_lq121s1dg31_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 3.6" TFT QVGA (LoLo display number 3) */
static struct pxafb_mode_info sharp_lq036q1da01_mode = {
	.pixclock		= 150000,
	.xres			= 320,
	.yres			= 240,
	.bpp			= 16,
	.hsync_len		= 0x0e,
	.left_margin		= 0x04,
	.right_margin		= 0x0a,
	.vsync_len		= 0x03,
	.upper_margin		= 0x03,
	.lower_margin		= 0x03,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq036q1da01 = {
	.modes			= &sharp_lq036q1da01_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 6.4" TFT VGA (LoLo display number 5) */
static struct pxafb_mode_info sharp_lq64d343_mode = {
	.pixclock		= 25000,
	.xres			= 640,
	.yres			= 480,
	.bpp			= 16,
	.hsync_len		= 0x31,
	.left_margin		= 0x89,
	.right_margin		= 0x19,
	.vsync_len		= 0x12,
	.upper_margin		= 0x22,
	.lower_margin		= 0x00,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq64d343 = {
	.modes			= &sharp_lq64d343_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 10.4" TFT VGA (LoLo display number 7) */
static struct pxafb_mode_info sharp_lq10d368_mode = {
	.pixclock		= 25000,
	.xres			= 640,
	.yres			= 480,
	.bpp			= 16,
	.hsync_len		= 0x31,
	.left_margin		= 0x89,
	.right_margin		= 0x19,
	.vsync_len		= 0x12,
	.upper_margin		= 0x22,
	.lower_margin		= 0x00,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq10d368 = {
	.modes			= &sharp_lq10d368_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

/* 3.5" TFT QVGA (LoLo display number 8) */
static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
	.pixclock		= 150000,
	.xres			= 240,
	.yres			= 320,
	.bpp			= 16,
	.hsync_len		= 0x0e,
	.left_margin		= 0x0a,
	.right_margin		= 0x0a,
	.vsync_len		= 0x03,
	.upper_margin		= 0x05,
	.lower_margin		= 0x14,
	.sync			= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
};

static struct pxafb_mach_info sharp_lq035q7db02_20 = {
	.modes			= &sharp_lq035q7db02_20_mode,
	.num_modes		= 1,
	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
				  LCD_ALTERNATE_MAPPING,
};

static struct pxafb_mach_info *lpd270_lcd_to_use;

static int __init lpd270_set_lcd(char *str)
{
	if (!strncasecmp(str, "lq057q3dc02", 11)) {
		lpd270_lcd_to_use = &sharp_lq057q3dc02;
	} else if (!strncasecmp(str, "lq121s1dg31", 11)) {
		lpd270_lcd_to_use = &sharp_lq121s1dg31;
	} else if (!strncasecmp(str, "lq036q1da01", 11)) {
		lpd270_lcd_to_use = &sharp_lq036q1da01;
	} else if (!strncasecmp(str, "lq64d343", 8)) {
		lpd270_lcd_to_use = &sharp_lq64d343;
	} else if (!strncasecmp(str, "lq10d368", 8)) {
		lpd270_lcd_to_use = &sharp_lq10d368;
	} else if (!strncasecmp(str, "lq035q7db02-20", 14)) {
		lpd270_lcd_to_use = &sharp_lq035q7db02_20;
	} else {
		printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
	}

	return 1;
}

__setup("lcd=", lpd270_set_lcd);

static struct platform_device *platform_devices[] __initdata = {
	&smc91x_device,
	&lpd270_backlight_device,
	&lpd270_flash_device[0],
	&lpd270_flash_device[1],
};

static struct pxaohci_platform_data lpd270_ohci_platform_data = {
	.port_mode	= PMM_PERPORT_MODE,
	.flags		= ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
};

static void __init lpd270_init(void)
{
	pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));

	pxa_set_ffuart_info(NULL);
	pxa_set_btuart_info(NULL);
	pxa_set_stuart_info(NULL);

	lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
	lpd270_flash_data[1].width = 4;

	/*
	 * System bus arbiter setting:
	 * - Core_Park
	 * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
	 */
	ARB_CNTRL = ARB_CORE_PARK | 0x234;

	pwm_add_table(lpd270_pwm_lookup, ARRAY_SIZE(lpd270_pwm_lookup));
	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));

	pxa_set_ac97_info(NULL);

	if (lpd270_lcd_to_use != NULL)
		pxa_set_fb_info(NULL, lpd270_lcd_to_use);

	pxa_set_ohci_info(&lpd270_ohci_platform_data);
}

static struct map_desc lpd270_io_desc[] __initdata = {
	{
		.virtual	= (unsigned long)LPD270_CPLD_VIRT,
		.pfn		= __phys_to_pfn(LPD270_CPLD_PHYS),
		.length		= LPD270_CPLD_SIZE,
		.type		= MT_DEVICE,
	},
};

static void __init lpd270_map_io(void)
{
	pxa27x_map_io();
	iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));

	/* for use I SRAM as framebuffer.  */
	PSLR |= 0x00000F04;
	PCFR  = 0x00000066;
}

MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
	/* Maintainer: Peter Barada */
	.atag_offset	= 0x100,
	.map_io		= lpd270_map_io,
	.nr_irqs	= LPD270_NR_IRQS,
	.init_irq	= lpd270_init_irq,
	.handle_irq	= pxa27x_handle_irq,
	.init_time	= pxa_timer_init,
	.init_machine	= lpd270_init,
	.restart	= pxa_restart,
MACHINE_END


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * arch/arm/mach-pxa/include/mach/lpd270.h
 *
 * Author:	Lennert Buytenhek
 * Created:	Feb 10, 2006
 */

#ifndef __ASM_ARCH_LPD270_H
#define __ASM_ARCH_LPD270_H

#define LPD270_CPLD_PHYS	PXA_CS2_PHYS
#define LPD270_CPLD_VIRT	IOMEM(0xf0000000)
#define LPD270_CPLD_SIZE	0x00100000

#define LPD270_ETH_PHYS		(PXA_CS2_PHYS + 0x01000000)

/* CPLD registers  */
#define LPD270_CPLD_REG(x)	(LPD270_CPLD_VIRT + (x))
#define LPD270_CONTROL		LPD270_CPLD_REG(0x00)
#define LPD270_PERIPHERAL0	LPD270_CPLD_REG(0x04)
#define LPD270_PERIPHERAL1	LPD270_CPLD_REG(0x08)
#define LPD270_CPLD_REVISION	LPD270_CPLD_REG(0x14)
#define LPD270_EEPROM_SPI_ITF	LPD270_CPLD_REG(0x20)
#define LPD270_MODE_PINS	LPD270_CPLD_REG(0x24)
#define LPD270_EGPIO		LPD270_CPLD_REG(0x30)
#define LPD270_INT_MASK		LPD270_CPLD_REG(0x40)
#define LPD270_INT_STATUS	LPD270_CPLD_REG(0x50)

#define LPD270_INT_AC97		(1 << 4)  /* AC'97 CODEC IRQ */
#define LPD270_INT_ETHERNET	(1 << 3)  /* Ethernet controller IRQ */
#define LPD270_INT_USBC		(1 << 2)  /* USB client cable detection IRQ */

#define LPD270_IRQ(x)		(IRQ_BOARD_START + (x))
#define LPD270_USBC_IRQ		LPD270_IRQ(2)
#define LPD270_ETHERNET_IRQ	LPD270_IRQ(3)
#define LPD270_AC97_IRQ		LPD270_IRQ(4)
#define LPD270_NR_IRQS		(IRQ_BOARD_START + 5)

#endif


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 *  linux/arch/arm/mach-pxa/lubbock.c
 *
 *  Support for the Intel DBPXA250 Development Platform.
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 */
#include <linux/clkdev.h>
#include <linux/gpio.h>
#include <linux/gpio/gpio-reg.h>
#include <linux/gpio/machine.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/major.h>
#include <linux/fb.h>
#include <linux/interrupt.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/smc91x.h>
#include <linux/slab.h>
#include <linux/leds.h>

#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/spi/pxa2xx_spi.h>

#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <linux/sizes.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/mach/flash.h>

#include <asm/hardware/sa1111.h>

#include "pxa25x.h"
#include <linux/platform_data/asoc-pxa.h>
#include "lubbock.h"
#include "udc.h"
#include <linux/platform_data/irda-pxaficp.h>
#include <linux/platform_data/video-pxafb.h>
#include <linux/platform_data/mmc-pxamci.h>
#include "pm.h"
#include "smemc.h"

#include "generic.h"
#include "devices.h"

static unsigned long lubbock_pin_config[] __initdata = {
	GPIO15_nCS_1,	/* CS1 - Flash */
	GPIO78_nCS_2,	/* CS2 - Baseboard FGPA */
	GPIO79_nCS_3,	/* CS3 - SMC ethernet */
	GPIO80_nCS_4,	/* CS4 - SA1111 */

	/* SSP data pins */
	GPIO23_SSP1_SCLK,
	GPIO25_SSP1_TXD,
	GPIO26_SSP1_RXD,

	/* AC97 */
	GPIO28_AC97_BITCLK,
	GPIO29_AC97_SDATA_IN_0,
	GPIO30_AC97_SDATA_OUT,
	GPIO31_AC97_SYNC,

	/* LCD - 16bpp DSTN */
	GPIOxx_LCD_DSTN_16BPP,

	/* BTUART */
	GPIO42_BTUART_RXD,
	GPIO43_BTUART_TXD,
	GPIO44_BTUART_CTS,
	GPIO45_BTUART_RTS,

	/* PC Card */
	GPIO48_nPOE,
	GPIO49_nPWE,
	GPIO50_nPIOR,
	GPIO51_nPIOW,
	GPIO52_nPCE_1,
	GPIO53_nPCE_2,
	GPIO54_nPSKTSEL,
	GPIO55_nPREG,
	GPIO56_nPWAIT,
	GPIO57_nIOIS16,

	/* MMC */
	GPIO6_MMC_CLK,
	GPIO8_MMC_CS0,

	/* SA1111 chip */
	GPIO11_3_6MHz,

	/* wakeup */
	GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
};

#define LUB_HEXLED		__LUB_REG(LUBBOCK_FPGA_PHYS + 0x010)

void lubbock_set_hexled(uint32_t value)
{
	LUB_HEXLED = value;
}

static struct gpio_chip *lubbock_misc_wr_gc;

static void lubbock_set_misc_wr(unsigned int mask, unsigned int set)
{
	unsigned long m = mask, v = set;
	lubbock_misc_wr_gc->set_multiple(lubbock_misc_wr_gc, &m, &v);
}

static int lubbock_udc_is_connected(void)
{
	return (LUB_MISC_RD & (1 << 9)) == 0;
}

static struct pxa2xx_udc_mach_info udc_info __initdata = {
	.udc_is_connected	= lubbock_udc_is_connected,
	// no D+ pullup; lubbock can't connect/disconnect in software
};

static struct resource lubbock_udc_resources[] = {
	DEFINE_RES_MEM(0x40600000, 0x10000),
	DEFINE_RES_IRQ(IRQ_USB),
	DEFINE_RES_IRQ(LUBBOCK_USB_IRQ),
	DEFINE_RES_IRQ(LUBBOCK_USB_DISC_IRQ),
};

/* GPIOs for SA1111 PCMCIA */
static struct gpiod_lookup_table sa1111_pcmcia_gpio_table = {
	.dev_id = "1800",
	.table = {
		{ "sa1111", 0, "a0vpp", GPIO_ACTIVE_HIGH },
		{ "sa1111", 1, "a1vpp", GPIO_ACTIVE_HIGH },
		{ "sa1111", 2, "a0vcc", GPIO_ACTIVE_HIGH },
		{ "sa1111", 3, "a1vcc", GPIO_ACTIVE_HIGH },
		{ "lubbock", 14, "b0vcc", GPIO_ACTIVE_HIGH },
		{ "lubbock", 15, "b1vcc", GPIO_ACTIVE_HIGH },
		{ },
	},
};

static void lubbock_init_pcmcia(void)
{
	struct clk *clk;

	gpiod_add_lookup_table(&sa1111_pcmcia_gpio_table);

	/* Add an alias for the SA1111 PCMCIA clock */
	clk = clk_get_sys("pxa2xx-pcmcia", NULL);
	if (!IS_ERR(clk)) {
		clkdev_create(clk, NULL, "1800");
		clk_put(clk);
	}
}

static struct resource sa1111_resources[] = {
	[0] = {
		.start	= 0x10000000,
		.end	= 0x10001fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= LUBBOCK_SA1111_IRQ,
		.end	= LUBBOCK_SA1111_IRQ,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct sa1111_platform_data sa1111_info = {
	.irq_base	= LUBBOCK_SA1111_IRQ_BASE,
	.disable_devs	= SA1111_DEVID_SAC,
};

static struct platform_device sa1111_device = {
	.name		= "sa1111",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(sa1111_resources),
	.resource	= sa1111_resources,
	.dev		= {
		.platform_data	= &sa1111_info,
	},
};

/* ADS7846 is connected through SSP ... and if your board has J5 populated,
 * you can select it to replace the ucb1400 by switching the touchscreen cable
 * (to J5) and poking board registers (as done below).  Else it's only useful
 * for the temperature sensors.
 */
static struct pxa2xx_spi_controller pxa_ssp_master_info = {
	.num_chipselect	= 1,
};

static int lubbock_ads7846_pendown_state(void)
{
	/* TS_BUSY is bit 8 in LUB_MISC_RD, but pendown is irq-only */
	return 0;
}

static struct ads7846_platform_data ads_info = {
	.model			= 7846,
	.vref_delay_usecs	= 100,		/* internal, no cap */
	.get_pendown_state	= lubbock_ads7846_pendown_state,
	// .x_plate_ohms		= 500,	/* GUESS! */
	// .y_plate_ohms		= 500,	/* GUESS! */
};

static struct gpiod_lookup_table ads7846_cs_gpios = {
	.dev_id		= "ads7846",
	.table		= {
		GPIO_LOOKUP("lubbock", 11, "cs", GPIO_ACTIVE_LOW),
		{}
	},
};

static struct pxa2xx_spi_chip ads_hw = {
	.tx_threshold		= 1,
	.rx_threshold		= 2,
};

static struct spi_board_info spi_board_info[] __initdata = { {
	.modalias	= "ads7846",
	.platform_data	= &ads_info,
	.controller_data = &ads_hw,
	.irq		= LUBBOCK_BB_IRQ,
	.max_speed_hz	= 120000 /* max sample rate at 3V */
				* 26 /* command + data + overhead */,
	.bus_num	= 1,
	.chip_select	= 0,
},
};

static struct resource smc91x_resources[] = {
	[0] = {
		.name	= "smc91x-regs",
		.start	= 0x0c000c00,
		.end	= 0x0c0fffff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= LUBBOCK_ETH_IRQ,
		.end	= LUBBOCK_ETH_IRQ,
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
	},
	[2] = {
		.name	= "smc91x-attrib",
		.start	= 0x0e000000,
		.end	= 0x0e0fffff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct smc91x_platdata lubbock_smc91x_info = {
	.flags	= SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_2,
};

static struct platform_device smc91x_device = {
	.name		= "smc91x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smc91x_resources),
	.resource	= smc91x_resources,
	.dev		= {
		.platform_data = &lubbock_smc91x_info,
	},
};

static struct resource flash_resources[] = {
	[0] = {
		.start	= 0x00000000,
		.end	= SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= 0x04000000,
		.end	= 0x04000000 + SZ_64M - 1,
		.flags	= IORESOURCE_MEM,
	},
};

static struct mtd_partition lubbock_partitions[] = {
	{
		.name =		"Bootloader",
		.size =		0x00040000,
		.offset =	0,
		.mask_flags =	MTD_WRITEABLE  /* force read-only */
	},{
		.name =		"Kernel",
		.size =		0x00100000,
		.offset =	0x00040000,
	},{
		.name =		"Filesystem",
		.size =		MTDPART_SIZ_FULL,
		.offset =	0x00140000
	}
};

static struct flash_platform_data lubbock_flash_data[2] = {
	{
		.map_name	= "cfi_probe",
		.parts		= lubbock_partitions,
		.nr_parts	= ARRAY_SIZE(lubbock_partitions),
	}, {
		.map_name	= "cfi_probe",
		.parts		= NULL,
		.nr_parts	= 0,
	}
};

static struct platform_device lubbock_flash_device[2] = {
	{
		.name		= "pxa2xx-flash",
		.id		= 0,
		.dev = {
			.platform_data = &lubbock_flash_data[0],
		},
		.resource = &flash_resources[0],
		.num_resources = 1,
	},
	{
		.name		= "pxa2xx-flash",
		.id		= 1,
		.dev = {
			.platform_data = &lubbock_flash_data[1],
		},
		.resource = &flash_resources[1],
		.num_resources = 1,
	},
};

static struct resource lubbock_cplds_resources[] = {
	[0] = {
		.start	= LUBBOCK_FPGA_PHYS + 0xc0,
		.end	= LUBBOCK_FPGA_PHYS + 0xe0 - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= PXA_GPIO_TO_IRQ(0),
		.end	= PXA_GPIO_TO_IRQ(0),
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
	},
	[2] = {
		.start	= LUBBOCK_IRQ(0),
		.end	= LUBBOCK_IRQ(6),
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device lubbock_cplds_device = {
	.name		= "pxa_cplds_irqs",
	.id		= -1,
	.resource	= &lubbock_cplds_resources[0],
	.num_resources	= 3,
};

static struct platform_device *devices[] __initdata = {
	&sa1111_device,
	&smc91x_device,
	&lubbock_flash_device[0],
	&lubbock_flash_device[1],
	&lubbock_cplds_device,
};

static struct pxafb_mode_info sharp_lm8v31_mode = {
	.pixclock	= 270000,
	.xres		= 640,
	.yres		= 480,
	.bpp		= 16,
	.hsync_len	= 1,
	.left_margin	= 3,
	.right_margin	= 3,
	.vsync_len	= 1,
	.upper_margin	= 0,
	.lower_margin	= 0,
	.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	.cmap_greyscale	= 0,
};

static struct pxafb_mach_info sharp_lm8v31 = {
	.modes		= &sharp_lm8v31_mode,
	.num_modes	= 1,
	.cmap_inverse	= 0,
	.cmap_static	= 0,
	.lcd_conn	= LCD_COLOR_DSTN_16BPP | LCD_PCLK_EDGE_FALL |
			  LCD_AC_BIAS_FREQ(255),
};

#define	MMC_POLL_RATE		msecs_to_jiffies(1000)

static irq_handler_t mmc_detect_int;
static void *mmc_detect_int_data;
static struct timer_list mmc_timer;

static void lubbock_mmc_poll(struct timer_list *unused)
{
	unsigned long flags;

	/* clear any previous irq state, then ... */
	local_irq_save(flags);
	LUB_IRQ_SET_CLR &= ~(1 << 0);
	local_irq_restore(flags);

	/* poll until mmc/sd card is removed */
	if (LUB_IRQ_SET_CLR & (1 << 0))
		mod_timer(&mmc_timer, jiffies + MMC_POLL_RATE);
	else {
		(void) mmc_detect_int(LUBBOCK_SD_IRQ, mmc_detect_int_data);
		enable_irq(LUBBOCK_SD_IRQ);
	}
}

static irqreturn_t lubbock_detect_int(int irq, void *data)
{
	/* IRQ is level triggered; disable, and poll for removal */
	disable_irq(irq);
	mod_timer(&mmc_timer, jiffies + MMC_POLL_RATE);

	return mmc_detect_int(irq, data);
}

static int lubbock_mci_init(struct device *dev,
		irq_handler_t detect_int,
		void *data)
{
	/* detect card insert/eject */
	mmc_detect_int = detect_int;
	mmc_detect_int_data = data;
	timer_setup(&mmc_timer, lubbock_mmc_poll, 0);
	return request_irq(LUBBOCK_SD_IRQ, lubbock_detect_int,
			   0, "lubbock-sd-detect", data);
}

static int lubbock_mci_get_ro(struct device *dev)
{
	return (LUB_MISC_RD & (1 << 2)) != 0;
}

static void lubbock_mci_exit(struct device *dev, void *data)
{
	free_irq(LUBBOCK_SD_IRQ, data);
	del_timer_sync(&mmc_timer);
}

static struct pxamci_platform_data lubbock_mci_platform_data = {
	.ocr_mask		= MMC_VDD_32_33|MMC_VDD_33_34,
	.detect_delay_ms	= 10,
	.init 			= lubbock_mci_init,
	.get_ro			= lubbock_mci_get_ro,
	.exit 			= lubbock_mci_exit,
};

static void lubbock_irda_transceiver_mode(struct device *dev, int mode)
{
	unsigned long flags;

	local_irq_save(flags);
	if (mode & IR_SIRMODE) {
		lubbock_set_misc_wr(BIT(4), 0);
	} else if (mode & IR_FIRMODE) {
		lubbock_set_misc_wr(BIT(4), BIT(4));
	}
	pxa2xx_transceiver_mode(dev, mode);
	local_irq_restore(flags);
}

static struct pxaficp_platform_data lubbock_ficp_platform_data = {
	.gpio_pwdown		= -1,
	.transceiver_cap	= IR_SIRMODE | IR_FIRMODE,
	.transceiver_mode	= lubbock_irda_transceiver_mode,
};

static void __init lubbock_init(void)
{
	int flashboot = (LUB_CONF_SWITCHES & 1);

	pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config));

	lubbock_misc_wr_gc = gpio_reg_init(NULL, (void *)&LUB_MISC_WR,
					   -1, 16, "lubbock", 0, LUB_MISC_WR,
					   NULL, NULL, NULL);
	if (IS_ERR(lubbock_misc_wr_gc)) {
		pr_err("Lubbock: unable to register lubbock GPIOs: %ld\n",
		       PTR_ERR(lubbock_misc_wr_gc));
		lubbock_misc_wr_gc = NULL;
	}

	pxa_set_ffuart_info(NULL);
	pxa_set_btuart_info(NULL);
	pxa_set_stuart_info(NULL);

	lubbock_init_pcmcia();

	clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL);
	/* lubbock has two extra IRQs */
	pxa25x_device_udc.resource = lubbock_udc_resources;
	pxa25x_device_udc.num_resources = ARRAY_SIZE(lubbock_udc_resources);
	pxa_set_udc_info(&udc_info);
	pxa_set_fb_info(NULL, &sharp_lm8v31);
	pxa_set_mci_info(&lubbock_mci_platform_data);
	pxa_set_ficp_info(&lubbock_ficp_platform_data);
	pxa_set_ac97_info(NULL);

	lubbock_flash_data[0].width = lubbock_flash_data[1].width =
		(__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
	/* Compensate for the nROMBT switch which swaps the flash banks */
	printk(KERN_NOTICE "Lubbock configured to boot from %s (bank %d)\n",
	       flashboot?"Flash":"ROM", flashboot);

	lubbock_flash_data[flashboot^1].name = "application-flash";
	lubbock_flash_data[flashboot].name = "boot-rom";
	(void) platform_add_devices(devices, ARRAY_SIZE(devices));

	gpiod_add_lookup_table(&ads7846_cs_gpios);

	pxa2xx_set_spi_info(1, &pxa_ssp_master_info);
	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
}

static struct map_desc lubbock_io_desc[] __initdata = {
  	{	/* CPLD */
		.virtual	=  LUBBOCK_FPGA_VIRT,
		.pfn		= __phys_to_pfn(LUBBOCK_FPGA_PHYS),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}
};

static void __init lubbock_map_io(void)
{
	pxa25x_map_io();
	iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc));

	PCFR |= PCFR_OPDE;
}

/*
 * Driver for the 8 discrete LEDs available for general use:
 * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
 * so be sure to not monkey with them here.
 */

#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
struct lubbock_led {
	struct led_classdev	cdev;
	u8			mask;
};

/*
 * The triggers lines up below will only be used if the
 * LED triggers are compiled in.
 */
static const struct {
	const char *name;
	const char *trigger;
} lubbock_leds[] = {
	{ "lubbock:D28", "default-on", },
	{ "lubbock:D27", "cpu0", },
	{ "lubbock:D26", "heartbeat" },
	{ "lubbock:D25", },
	{ "lubbock:D24", },
	{ "lubbock:D23", },
	{ "lubbock:D22", },
	{ "lubbock:D21", },
};

static void lubbock_led_set(struct led_classdev *cdev,
			      enum led_brightness b)
{
	struct lubbock_led *led = container_of(cdev,
					 struct lubbock_led, cdev);
	u32 reg = LUB_DISC_BLNK_LED;

	if (b != LED_OFF)
		reg |= led->mask;
	else
		reg &= ~led->mask;

	LUB_DISC_BLNK_LED = reg;
}

static enum led_brightness lubbock_led_get(struct led_classdev *cdev)
{
	struct lubbock_led *led = container_of(cdev,
					 struct lubbock_led, cdev);
	u32 reg = LUB_DISC_BLNK_LED;

	return (reg & led->mask) ? LED_FULL : LED_OFF;
}

static int __init lubbock_leds_init(void)
{
	int i;

	if (!machine_is_lubbock())
		return -ENODEV;

	/* All ON */
	LUB_DISC_BLNK_LED |= 0xff;
	for (i = 0; i < ARRAY_SIZE(lubbock_leds); i++) {
		struct lubbock_led *led;

		led = kzalloc(sizeof(*led), GFP_KERNEL);
		if (!led)
			break;

		led->cdev.name = lubbock_leds[i].name;
		led->cdev.brightness_set = lubbock_led_set;
		led->cdev.brightness_get = lubbock_led_get;
		led->cdev.default_trigger = lubbock_leds[i].trigger;
		led->mask = BIT(i);

		if (led_classdev_register(NULL, &led->cdev) < 0) {
			kfree(led);
			break;
		}
	}

	return 0;
}

/*
 * Since we may have triggers on any subsystem, defer registration
 * until after subsystem_init.
 */
fs_initcall(lubbock_leds_init);
#endif

MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
	/* Maintainer: MontaVista Software Inc. */
	.map_io		= lubbock_map_io,
	.nr_irqs	= LUBBOCK_NR_IRQS,
	.init_irq	= pxa25x_init_irq,
	.handle_irq	= pxa25x_handle_irq,
	.init_time	= pxa_timer_init,
	.init_machine	= lubbock_init,
	.restart	= pxa_restart,
MACHINE_END


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 */

#include "irqs.h"

#define LUBBOCK_ETH_PHYS	PXA_CS3_PHYS

#define LUBBOCK_FPGA_PHYS	PXA_CS2_PHYS
#define LUBBOCK_FPGA_VIRT	(0xf0000000)
#define LUB_P2V(x)		((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT)
#define LUB_V2P(x)		((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS)

#ifndef __ASSEMBLY__
#  define __LUB_REG(x)		(*((volatile unsigned long *)LUB_P2V(x)))
#else
#  define __LUB_REG(x)		LUB_P2V(x)
#endif

/* FPGA register virtual addresses */
#define LUB_WHOAMI		__LUB_REG(LUBBOCK_FPGA_PHYS + 0x000)
#define LUB_DISC_BLNK_LED	__LUB_REG(LUBBOCK_FPGA_PHYS + 0x040)
#define LUB_CONF_SWITCHES	__LUB_REG(LUBBOCK_FPGA_PHYS + 0x050)
#define LUB_USER_SWITCHES	__LUB_REG(LUBBOCK_FPGA_PHYS + 0x060)
#define LUB_MISC_WR		__LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
#define LUB_MISC_RD		__LUB_REG(LUBBOCK_FPGA_PHYS + 0x090)
#define LUB_IRQ_MASK_EN		__LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0)
#define LUB_IRQ_SET_CLR		__LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0)
#define LUB_GP			__LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)

/* Board specific IRQs */
#define LUBBOCK_NR_IRQS		IRQ_BOARD_START

#define LUBBOCK_IRQ(x)		(LUBBOCK_NR_IRQS + (x))
#define LUBBOCK_SD_IRQ		LUBBOCK_IRQ(0)
#define LUBBOCK_SA1111_IRQ	LUBBOCK_IRQ(1)
#define LUBBOCK_USB_IRQ		LUBBOCK_IRQ(2)  /* usb connect */
#define LUBBOCK_ETH_IRQ		LUBBOCK_IRQ(3)
#define LUBBOCK_UCB1400_IRQ	LUBBOCK_IRQ(4)
#define LUBBOCK_BB_IRQ		LUBBOCK_IRQ(5)
#define LUBBOCK_USB_DISC_IRQ	LUBBOCK_IRQ(6)  /* usb disconnect */
#define LUBBOCK_LAST_IRQ	LUBBOCK_IRQ(6)

#define LUBBOCK_SA1111_IRQ_BASE	(LUBBOCK_NR_IRQS + 32)