code:
// SPDX-License-Identifier: (GPL-2.0)
/*
 * Device tree for the Tolino Shine 3 ebook reader
 *
 * Name on mainboard is: 37NB-E60K00+4A4
 * Serials start with: E60K02 (a number also seen in
 * vendor kernel sources)
 *
 * This mainboard seems to be equipped with different SoCs.
 * In the Toline Shine 3 ebook reader it is a i.MX6SL
 *
 * Copyright 2019 Andreas Kemnade
 * based on works
 * Copyright 2016 Freescale Semiconductor, Inc.
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx6sl.dtsi"
#include "e60k02.dtsi"

/ {
	model = "Tolino Shine 3";
	compatible = "kobo,tolino-shine3", "fsl,imx6sl";
};

&gpio_keys {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_keys>;
};

&i2c1 {
	pinctrl-names = "default","sleep";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_sleep>;
};

&i2c2 {
	pinctrl-names = "default","sleep";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_sleep>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp {
		fsl,pins = <
			MX6SL_PAD_SD1_DAT3__GPIO5_IO06                0x17059 /* TP_INT */
			MX6SL_PAD_SD1_DAT2__GPIO5_IO13                0x10059 /* TP_RST */
		>;
	};

	pinctrl_gpio_keys: gpio-keysgrp {
		fsl,pins = <
			MX6SL_PAD_SD1_DAT1__GPIO5_IO08	0x17059	/* PWR_SW */
			MX6SL_PAD_SD1_DAT4__GPIO5_IO12	0x17059	/* HALL_EN */
		>;
	};

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX6SL_PAD_LCD_DAT0__GPIO2_IO20	0x79
			MX6SL_PAD_LCD_DAT1__GPIO2_IO21	0x79
			MX6SL_PAD_LCD_DAT2__GPIO2_IO22	0x79
			MX6SL_PAD_LCD_DAT3__GPIO2_IO23	0x79
			MX6SL_PAD_LCD_DAT4__GPIO2_IO24	0x79
			MX6SL_PAD_LCD_DAT5__GPIO2_IO25	0x79
			MX6SL_PAD_LCD_DAT6__GPIO2_IO26	0x79
			MX6SL_PAD_LCD_DAT7__GPIO2_IO27	0x79
			MX6SL_PAD_LCD_DAT8__GPIO2_IO28	0x79
			MX6SL_PAD_LCD_DAT9__GPIO2_IO29	0x79
			MX6SL_PAD_LCD_DAT10__GPIO2_IO30	0x79
			MX6SL_PAD_LCD_DAT11__GPIO2_IO31	0x79
			MX6SL_PAD_LCD_DAT12__GPIO3_IO00	0x79
			MX6SL_PAD_LCD_DAT13__GPIO3_IO01	0x79
			MX6SL_PAD_LCD_DAT14__GPIO3_IO02	0x79
			MX6SL_PAD_LCD_DAT15__GPIO3_IO03	0x79
			MX6SL_PAD_LCD_DAT16__GPIO3_IO04	0x79
			MX6SL_PAD_LCD_DAT17__GPIO3_IO05	0x79
			MX6SL_PAD_LCD_DAT18__GPIO3_IO06	0x79
			MX6SL_PAD_LCD_DAT19__GPIO3_IO07	0x79
			MX6SL_PAD_LCD_DAT20__GPIO3_IO08	0x79
			MX6SL_PAD_LCD_DAT21__GPIO3_IO09	0x79
			MX6SL_PAD_LCD_DAT22__GPIO3_IO10	0x79
			MX6SL_PAD_LCD_DAT23__GPIO3_IO11	0x79
			MX6SL_PAD_LCD_CLK__GPIO2_IO15		0x79
			MX6SL_PAD_LCD_ENABLE__GPIO2_IO16	0x79
			MX6SL_PAD_LCD_HSYNC__GPIO2_IO17	0x79
			MX6SL_PAD_LCD_VSYNC__GPIO2_IO18	0x79
			MX6SL_PAD_LCD_RESET__GPIO2_IO19	0x79
			MX6SL_PAD_KEY_COL3__GPIO3_IO30		0x79
			MX6SL_PAD_KEY_ROW7__GPIO4_IO07		0x79
			MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13	0x79
			MX6SL_PAD_KEY_COL5__GPIO4_IO02		0x79
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6SL_PAD_I2C1_SCL__I2C1_SCL	 0x4001f8b1
			MX6SL_PAD_I2C1_SDA__I2C1_SDA	 0x4001f8b1
		>;
	};

	pinctrl_i2c1_sleep: i2c1grp-sleep {
		fsl,pins = <
			MX6SL_PAD_I2C1_SCL__I2C1_SCL	 0x400108b1
			MX6SL_PAD_I2C1_SDA__I2C1_SDA	 0x400108b1
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6SL_PAD_I2C2_SCL__I2C2_SCL	 0x4001f8b1
			MX6SL_PAD_I2C2_SDA__I2C2_SDA	 0x4001f8b1
		>;
	};

	pinctrl_i2c2_sleep: i2c2grp-sleep {
		fsl,pins = <
			MX6SL_PAD_I2C2_SCL__I2C2_SCL	 0x400108b1
			MX6SL_PAD_I2C2_SDA__I2C2_SDA	 0x400108b1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6SL_PAD_REF_CLK_24M__I2C3_SCL  0x4001f8b1
			MX6SL_PAD_REF_CLK_32K__I2C3_SDA  0x4001f8b1
		>;
	};

	pinctrl_led: ledgrp {
		fsl,pins = <
			MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059
		>;
	};

	pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
		fsl,pins = <
			MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10		0x10059 /* HWEN */
		>;
	};

	pinctrl_ricoh_gpio: ricoh_gpiogrp {
		fsl,pins = <
			MX6SL_PAD_SD1_CLK__GPIO5_IO15                  0x1b8b1 /* ricoh619 chg */
			MX6SL_PAD_SD1_DAT0__GPIO5_IO11        0x1b8b1 /* ricoh619 irq */
			MX6SL_PAD_KEY_COL2__GPIO3_IO28                         0x1b8b1 /* ricoh619 bat_low_int */
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
			MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1
			MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1
		>;
	};

	pinctrl_usbotg1: usbotg1grp {
		fsl,pins = <
			MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6SL_PAD_SD2_CMD__SD2_CMD		0x17059
			MX6SL_PAD_SD2_CLK__SD2_CLK		0x13059
			MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x17059
			MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x17059
			MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x17059
			MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x17059
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
		fsl,pins = <
			MX6SL_PAD_SD2_CMD__SD2_CMD		0x170b9
			MX6SL_PAD_SD2_CLK__SD2_CLK		0x130b9
			MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x170b9
			MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x170b9
			MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x170b9
			MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x170b9
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
		fsl,pins = <
			MX6SL_PAD_SD2_CMD__SD2_CMD		0x170f9
			MX6SL_PAD_SD2_CLK__SD2_CLK		0x130f9
			MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x170f9
			MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x170f9
			MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x170f9
			MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x170f9
		>;
	};

	pinctrl_usdhc2_sleep: usdhc2grp-sleep {
		fsl,pins = <
			MX6SL_PAD_SD2_CMD__GPIO5_IO04		0x100f9
			MX6SL_PAD_SD2_CLK__GPIO5_IO05		0x100f9
			MX6SL_PAD_SD2_DAT0__GPIO5_IO01		0x100f9
			MX6SL_PAD_SD2_DAT1__GPIO4_IO30		0x100f9
			MX6SL_PAD_SD2_DAT2__GPIO5_IO03		0x100f9
			MX6SL_PAD_SD2_DAT3__GPIO4_IO28		0x100f9
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6SL_PAD_SD3_CMD__SD3_CMD	0x11059
			MX6SL_PAD_SD3_CLK__SD3_CLK	0x11059
			MX6SL_PAD_SD3_DAT0__SD3_DATA0	0x11059
			MX6SL_PAD_SD3_DAT1__SD3_DATA1	0x11059
			MX6SL_PAD_SD3_DAT2__SD3_DATA2	0x11059
			MX6SL_PAD_SD3_DAT3__SD3_DATA3	0x11059
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
		fsl,pins = <
			MX6SL_PAD_SD3_CMD__SD3_CMD	0x170b9
			MX6SL_PAD_SD3_CLK__SD3_CLK	0x170b9
			MX6SL_PAD_SD3_DAT0__SD3_DATA0	0x170b9
			MX6SL_PAD_SD3_DAT1__SD3_DATA1	0x170b9
			MX6SL_PAD_SD3_DAT2__SD3_DATA2	0x170b9
			MX6SL_PAD_SD3_DAT3__SD3_DATA3	0x170b9
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
		fsl,pins = <
			MX6SL_PAD_SD3_CMD__SD3_CMD	0x170f9
			MX6SL_PAD_SD3_CLK__SD3_CLK	0x170f9
			MX6SL_PAD_SD3_DAT0__SD3_DATA0	0x170f9
			MX6SL_PAD_SD3_DAT1__SD3_DATA1	0x170f9
			MX6SL_PAD_SD3_DAT2__SD3_DATA2	0x170f9
			MX6SL_PAD_SD3_DAT3__SD3_DATA3	0x170f9
		>;
	};

	pinctrl_usdhc3_sleep: usdhc3grp-sleep {
		fsl,pins = <
			MX6SL_PAD_SD3_CMD__GPIO5_IO21	0x100c1
			MX6SL_PAD_SD3_CLK__GPIO5_IO18	0x100c1
			MX6SL_PAD_SD3_DAT0__GPIO5_IO19	0x100c1
			MX6SL_PAD_SD3_DAT1__GPIO5_IO20	0x100c1
			MX6SL_PAD_SD3_DAT2__GPIO5_IO16	0x100c1
			MX6SL_PAD_SD3_DAT3__GPIO5_IO17	0x100c1
		>;
	};

	pinctrl_wifi_power: wifi-powergrp {
		fsl,pins = <
			MX6SL_PAD_SD2_DAT6__GPIO4_IO29	0x10059	/* WIFI_3V3_ON */
		>;
	};

	pinctrl_wifi_reset: wifi-resetgrp {
		fsl,pins = <
			MX6SL_PAD_SD2_DAT7__GPIO5_IO00	0x10059	/* WIFI_RST */
		>;
	};
};

&leds {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_led>;
};

&lm3630a {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
};

&reg_wifi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wifi_power>;
};

&reg_vdd1p1 {
	vin-supply = <&dcdc2_reg>;
};

&reg_vdd2p5 {
	vin-supply = <&dcdc2_reg>;
};

&ricoh619 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ricoh_gpio>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	pinctrl-3 = <&pinctrl_usdhc2_sleep>;
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	pinctrl-3 = <&pinctrl_usdhc3_sleep>;
};

&wifi_pwrseq {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wifi_reset>;
};


code:
// SPDX-License-Identifier: (GPL-2.0)
/*
 * Device tree for the Tolino Vision 5 ebook reader
 *
 * Name on mainboard is: 37NB-E70K0M+6A3
 * Serials start with: E70K02 (a number also seen in
 * vendor kernel sources)
 *
 * This mainboard seems to be equipped with different SoCs.
 * In the Tolino Vision 5 ebook reader it is a i.MX6SL
 *
 * Copyright 2021 Andreas Kemnade
 * based on works
 * Copyright 2016 Freescale Semiconductor, Inc.
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx6sl.dtsi"
#include "e70k02.dtsi"

/ {
	model = "Tolino Vision 5";
	compatible = "kobo,tolino-vision5", "fsl,imx6sl";
};

&gpio_keys {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_keys>;
};

&i2c1 {
	pinctrl-names = "default","sleep";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_sleep>;
};

&i2c2 {
	pinctrl-names = "default","sleep";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_sleep>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_gpio_keys: gpio-keysgrp {
		fsl,pins = <
			MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25	0x17059	/* PWR_SW */
			MX6SL_PAD_FEC_MDC__GPIO4_IO23	0x17059	/* HALL_EN */
			MX6SL_PAD_KEY_COL4__GPIO4_IO00		0x17059	/* PAGE_UP */
			MX6SL_PAD_KEY_COL5__GPIO4_IO02		0x17059	/* PAGE_DOWN */
		>;
	};

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX6SL_PAD_LCD_DAT1__GPIO2_IO21	0x79
			MX6SL_PAD_LCD_DAT4__GPIO2_IO24	0x79
			MX6SL_PAD_LCD_DAT5__GPIO2_IO25	0x79
			MX6SL_PAD_LCD_DAT6__GPIO2_IO26	0x79
			MX6SL_PAD_LCD_DAT7__GPIO2_IO27	0x79
			MX6SL_PAD_LCD_DAT8__GPIO2_IO28	0x79
			MX6SL_PAD_LCD_DAT9__GPIO2_IO29	0x79
			MX6SL_PAD_LCD_DAT10__GPIO2_IO30	0x79
			MX6SL_PAD_LCD_DAT11__GPIO2_IO31	0x79
			MX6SL_PAD_LCD_DAT12__GPIO3_IO00	0x79
			MX6SL_PAD_LCD_DAT13__GPIO3_IO01	0x79
			MX6SL_PAD_LCD_DAT14__GPIO3_IO02	0x79
			MX6SL_PAD_LCD_DAT15__GPIO3_IO03	0x79
			MX6SL_PAD_LCD_DAT16__GPIO3_IO04	0x79
			MX6SL_PAD_LCD_DAT17__GPIO3_IO05	0x79
			MX6SL_PAD_LCD_DAT18__GPIO3_IO06	0x79
			MX6SL_PAD_LCD_DAT19__GPIO3_IO07	0x79
			MX6SL_PAD_LCD_DAT20__GPIO3_IO08	0x79
			MX6SL_PAD_LCD_DAT21__GPIO3_IO09	0x79
			MX6SL_PAD_LCD_DAT22__GPIO3_IO10	0x79
			MX6SL_PAD_LCD_DAT23__GPIO3_IO11	0x79
			MX6SL_PAD_LCD_CLK__GPIO2_IO15		0x79
			MX6SL_PAD_LCD_ENABLE__GPIO2_IO16	0x79
			MX6SL_PAD_LCD_HSYNC__GPIO2_IO17	0x79
			MX6SL_PAD_LCD_VSYNC__GPIO2_IO18	0x79
			MX6SL_PAD_LCD_RESET__GPIO2_IO19	0x79
			MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21	0x79
			MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26	0x79
			MX6SL_PAD_KEY_COL3__GPIO3_IO30		0x79
			MX6SL_PAD_KEY_ROW7__GPIO4_IO07		0x79
			MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13	0x79
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6SL_PAD_I2C1_SCL__I2C1_SCL	 0x4001f8b1
			MX6SL_PAD_I2C1_SDA__I2C1_SDA	 0x4001f8b1
		>;
	};

	pinctrl_i2c1_sleep: i2c1grp-sleep {
		fsl,pins = <
			MX6SL_PAD_I2C1_SCL__I2C1_SCL	 0x400108b1
			MX6SL_PAD_I2C1_SDA__I2C1_SDA	 0x400108b1
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6SL_PAD_I2C2_SCL__I2C2_SCL	 0x4001f8b1
			MX6SL_PAD_I2C2_SDA__I2C2_SDA	 0x4001f8b1
		>;
	};

	pinctrl_i2c2_sleep: i2c2grp-sleep {
		fsl,pins = <
			MX6SL_PAD_I2C2_SCL__I2C2_SCL	 0x400108b1
			MX6SL_PAD_I2C2_SDA__I2C2_SDA	 0x400108b1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6SL_PAD_REF_CLK_24M__I2C3_SCL  0x4001f8b1
			MX6SL_PAD_REF_CLK_32K__I2C3_SDA  0x4001f8b1
		>;
	};

	pinctrl_led: ledgrp {
		fsl,pins = <
			MX6SL_PAD_FEC_RXD0__GPIO4_IO17	0x10059
		>;
	};

	pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
		fsl,pins = <
			MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10		0x10059 /* HWEN */
		>;
	};

	pinctrl_ricoh_gpio: ricoh-gpiogrp {
		fsl,pins = <
			MX6SL_PAD_FEC_MDIO__GPIO4_IO20		0x1b8b1 /* ricoh619 chg */
			MX6SL_PAD_FEC_RX_ER__GPIO4_IO19		0x1b8b1 /* ricoh619 irq */
			MX6SL_PAD_KEY_COL2__GPIO3_IO28		0x1b8b1 /* ricoh619 bat_low_int */
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
			MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
		>;
	};

	pinctrl_usbotg1: usbotg1grp {
		fsl,pins = <
			MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6SL_PAD_SD1_CMD__SD1_CMD	0x17059
			MX6SL_PAD_SD1_CLK__SD1_CLK	0x17059
			MX6SL_PAD_SD1_DAT0__SD1_DATA0	0x17059
			MX6SL_PAD_SD1_DAT1__SD1_DATA1	0x17059
			MX6SL_PAD_SD1_DAT2__SD1_DATA2	0x17059
			MX6SL_PAD_SD1_DAT3__SD1_DATA3	0x17059
			MX6SL_PAD_SD1_DAT4__SD1_DATA4	0x17059
			MX6SL_PAD_SD1_DAT5__SD1_DATA5	0x17059
			MX6SL_PAD_SD1_DAT6__SD1_DATA6	0x17059
			MX6SL_PAD_SD1_DAT7__SD1_DATA7	0x17059
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX6SL_PAD_SD1_CMD__SD1_CMD	0x170b9
			MX6SL_PAD_SD1_CLK__SD1_CLK	0x170b9
			MX6SL_PAD_SD1_DAT0__SD1_DATA0	0x170b9
			MX6SL_PAD_SD1_DAT1__SD1_DATA1	0x170b9
			MX6SL_PAD_SD1_DAT2__SD1_DATA2	0x170b9
			MX6SL_PAD_SD1_DAT3__SD1_DATA3	0x170b9
			MX6SL_PAD_SD1_DAT4__SD1_DATA4	0x170b9
			MX6SL_PAD_SD1_DAT5__SD1_DATA5	0x170b9
			MX6SL_PAD_SD1_DAT6__SD1_DATA6	0x170b9
			MX6SL_PAD_SD1_DAT7__SD1_DATA7	0x170b9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX6SL_PAD_SD1_CMD__SD1_CMD	0x170f9
			MX6SL_PAD_SD1_CLK__SD1_CLK	0x170f9
			MX6SL_PAD_SD1_DAT0__SD1_DATA0	0x170f9
			MX6SL_PAD_SD1_DAT1__SD1_DATA1	0x170f9
			MX6SL_PAD_SD1_DAT2__SD1_DATA2	0x170f9
			MX6SL_PAD_SD1_DAT3__SD1_DATA3	0x170f9
			MX6SL_PAD_SD1_DAT4__SD1_DATA4	0x170b9
			MX6SL_PAD_SD1_DAT5__SD1_DATA5	0x170b9
			MX6SL_PAD_SD1_DAT6__SD1_DATA6	0x170b9
			MX6SL_PAD_SD1_DAT7__SD1_DATA7	0x170b9
		>;
	};

	pinctrl_usdhc1_sleep: usdhc1-sleepgrp {
		fsl,pins = <
			MX6SL_PAD_SD1_CMD__SD1_CMD	0x10059
			MX6SL_PAD_SD1_CLK__SD1_CLK	0x10059
			MX6SL_PAD_SD1_DAT0__SD1_DATA0	0x10059
			MX6SL_PAD_SD1_DAT1__SD1_DATA1	0x10059
			MX6SL_PAD_SD1_DAT2__SD1_DATA2	0x10059
			MX6SL_PAD_SD1_DAT3__SD1_DATA3	0x10059
			MX6SL_PAD_SD1_DAT4__SD1_DATA4	0x10059
			MX6SL_PAD_SD1_DAT5__SD1_DATA5	0x10059
			MX6SL_PAD_SD1_DAT6__SD1_DATA6	0x10059
			MX6SL_PAD_SD1_DAT7__SD1_DATA7	0x10059
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6SL_PAD_SD3_CMD__SD3_CMD	0x11059
			MX6SL_PAD_SD3_CLK__SD3_CLK	0x11059
			MX6SL_PAD_SD3_DAT0__SD3_DATA0	0x11059
			MX6SL_PAD_SD3_DAT1__SD3_DATA1	0x11059
			MX6SL_PAD_SD3_DAT2__SD3_DATA2	0x11059
			MX6SL_PAD_SD3_DAT3__SD3_DATA3	0x11059
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX6SL_PAD_SD3_CMD__SD3_CMD	0x170b9
			MX6SL_PAD_SD3_CLK__SD3_CLK	0x170b9
			MX6SL_PAD_SD3_DAT0__SD3_DATA0	0x170b9
			MX6SL_PAD_SD3_DAT1__SD3_DATA1	0x170b9
			MX6SL_PAD_SD3_DAT2__SD3_DATA2	0x170b9
			MX6SL_PAD_SD3_DAT3__SD3_DATA3	0x170b9
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX6SL_PAD_SD3_CMD__SD3_CMD	0x170f9
			MX6SL_PAD_SD3_CLK__SD3_CLK	0x170f9
			MX6SL_PAD_SD3_DAT0__SD3_DATA0	0x170f9
			MX6SL_PAD_SD3_DAT1__SD3_DATA1	0x170f9
			MX6SL_PAD_SD3_DAT2__SD3_DATA2	0x170f9
			MX6SL_PAD_SD3_DAT3__SD3_DATA3	0x170f9
		>;
	};

	pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
		fsl,pins = <
			MX6SL_PAD_SD3_CMD__GPIO5_IO21	0x100c1
			MX6SL_PAD_SD3_CLK__GPIO5_IO18	0x100c1
			MX6SL_PAD_SD3_DAT0__GPIO5_IO19	0x100c1
			MX6SL_PAD_SD3_DAT1__GPIO5_IO20	0x100c1
			MX6SL_PAD_SD3_DAT2__GPIO5_IO16	0x100c1
			MX6SL_PAD_SD3_DAT3__GPIO5_IO17	0x100c1
		>;
	};

	pinctrl_wifi_power: wifi-powergrp {
		fsl,pins = <
			MX6SL_PAD_SD2_DAT6__GPIO4_IO29	0x10059	 /* WIFI_3V3_ON */
		>;
	};

	pinctrl_wifi_reset: wifi-resetgrp {
		fsl,pins = <
			MX6SL_PAD_SD2_DAT7__GPIO5_IO00	0x10059	/* WIFI_RST */
		>;
	};
};

&leds {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_led>;
};

&lm3630a {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
};

&reg_wifi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wifi_power>;
};

&reg_vdd1p1 {
	vin-supply = <&dcdc2_reg>;
};

&reg_vdd2p5 {
	vin-supply = <&dcdc2_reg>;
};

&reg_arm {
	vin-supply = <&dcdc3_reg>;
};

&reg_soc {
	vin-supply = <&dcdc1_reg>;
};

&reg_pu {
	vin-supply = <&dcdc1_reg>;
};

&ricoh619 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ricoh_gpio>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	pinctrl-3 = <&pinctrl_usdhc1_sleep>;
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	pinctrl-3 = <&pinctrl_usdhc3_sleep>;
};

&wifi_pwrseq {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wifi_reset>;
};

repo_name: angery/linux


code:
/*
 * Copyright 2014, 2015 O.S. Systems Software LTDA.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of
 *     the License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
 *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include "imx6sl.dtsi"

/ {
	model = "Revotics WaRP Board";
	compatible = "revotics,imx6sl-warp", "fsl,imx6sl";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	usdhc3_pwrseq: usdhc3_pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, 	/* WL_REG_ON */
			      <&gpio4 7 GPIO_ACTIVE_LOW>, 	/* WL_HOSTWAKE */
			      <&gpio3 25 GPIO_ACTIVE_LOW>, 	/* BT_REG_ON */
			      <&gpio3 27 GPIO_ACTIVE_LOW>,	/* BT_HOSTWAKE */
			      <&gpio4 4 GPIO_ACTIVE_LOW>, 	/* BT_WAKE */
			      <&gpio4 6 GPIO_ACTIVE_LOW>; 	/* BT_RST_N */
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	uart-has-rtscts;
	status = "okay";
};

&usbotg1 {
	dr_mode = "peripheral";
	disable-over-current;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <4>;
	non-removable;
	keep-power-in-suspend;
	wakeup-source;
	mmc-pwrseq = <&usdhc3_pwrseq>;
	status = "okay";
};

&iomuxc {
	imx6sl-warp {
		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6SL_PAD_UART1_RXD__UART1_RX_DATA	0x41b0b1
				MX6SL_PAD_UART1_TXD__UART1_TX_DATA	0x41b0b1
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX6SL_PAD_AUD_RXC__UART3_RX_DATA	0x41b0b1
				MX6SL_PAD_AUD_RXC__UART3_TX_DATA	0x41b0b1
			>;
		};

		pinctrl_uart5: uart5grp {
			fsl,pins = <
				MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA	0x41b0b1
				MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA	0x41b0b1
				MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B	0x4130b1
				MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B	0x4130b1
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6SL_PAD_SD2_CMD__SD2_CMD		0x417059
				MX6SL_PAD_SD2_CLK__SD2_CLK		0x410059
				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x417059
				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x417059
				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x417059
				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x417059
				MX6SL_PAD_SD2_DAT4__SD2_DATA4		0x417059
				MX6SL_PAD_SD2_DAT5__SD2_DATA5		0x417059
				MX6SL_PAD_SD2_DAT6__SD2_DATA6		0x417059
				MX6SL_PAD_SD2_DAT7__SD2_DATA7		0x417059
				MX6SL_PAD_SD2_RST__SD2_RESET		0x417059
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				MX6SL_PAD_SD2_CMD__SD2_CMD		0x4170b9
				MX6SL_PAD_SD2_CLK__SD2_CLK		0x4100b9
				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x4170b9
				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x4170b9
				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x4170b9
				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x4170b9
				MX6SL_PAD_SD2_DAT4__SD2_DATA4		0x4170b9
				MX6SL_PAD_SD2_DAT5__SD2_DATA5		0x4170b9
				MX6SL_PAD_SD2_DAT6__SD2_DATA6		0x4170b9
				MX6SL_PAD_SD2_DAT7__SD2_DATA7		0x4170b9
				MX6SL_PAD_SD2_RST__SD2_RESET		0x4170b9
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				MX6SL_PAD_SD2_CMD__SD2_CMD		0x4170f9
				MX6SL_PAD_SD2_CLK__SD2_CLK		0x4100f9
				MX6SL_PAD_SD2_DAT0__SD2_DATA0		0x4170f9
				MX6SL_PAD_SD2_DAT1__SD2_DATA1		0x4170f9
				MX6SL_PAD_SD2_DAT2__SD2_DATA2		0x4170f9
				MX6SL_PAD_SD2_DAT3__SD2_DATA3		0x4170f9
				MX6SL_PAD_SD2_DAT4__SD2_DATA4		0x4170f9
				MX6SL_PAD_SD2_DAT5__SD2_DATA5		0x4170f9
				MX6SL_PAD_SD2_DAT6__SD2_DATA6		0x4170f9
				MX6SL_PAD_SD2_DAT7__SD2_DATA7		0x4170f9
				MX6SL_PAD_SD2_RST__SD2_RESET		0x4170f9
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6SL_PAD_SD3_CMD__SD3_CMD		0x417059
				MX6SL_PAD_SD3_CLK__SD3_CLK		0x410059
				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x417059
				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x417059
				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x417059
				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x417059
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
			fsl,pins = <
				MX6SL_PAD_SD3_CMD__SD3_CMD		0x4170b9
				MX6SL_PAD_SD3_CLK__SD3_CLK		0x4100b9
				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x4170b9
				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x4170b9
				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x4170b9
				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x4170b9
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
			fsl,pins = <
				MX6SL_PAD_SD3_CMD__SD3_CMD		0x4170f9
				MX6SL_PAD_SD3_CLK__SD3_CLK		0x4100f9
				MX6SL_PAD_SD3_DAT0__SD3_DATA0		0x4170f9
				MX6SL_PAD_SD3_DAT1__SD3_DATA1		0x4170f9
				MX6SL_PAD_SD3_DAT2__SD3_DATA2		0x4170f9
				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x4170f9
			>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2013 Freescale Semiconductor, Inc.

#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6sl-pinfunc.h"
#include <dt-bindings/clock/imx6sl-clock.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 */
	chosen {};

	aliases {
		ethernet0 = &fec;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		mmc3 = &usdhc4;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &ecspi3;
		spi3 = &ecspi4;
		usb0 = &usbotg1;
		usb1 = &usbotg2;
		usb2 = &usbh;
		usbphy0 = &usbphy1;
		usbphy1 = &usbphy2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x0>;
			next-level-cache = <&L2>;
			operating-points =
				/* kHz    uV */
				<996000  1275000>,
				<792000  1175000>,
				<396000  975000>;
			fsl,soc-operating-points =
				/* ARM kHz	SOC-PU uV */
				<996000		1225000>,
				<792000		1175000>,
				<396000		1175000>;
			clock-latency = <61036>; /* two CLK32 periods */
			#cooling-cells = <2>;
			clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
					<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
					<&clks IMX6SL_CLK_PLL1_SYS>;
			clock-names = "arm", "pll2_pfd2_396m", "step",
				      "pll1_sw", "pll1_sys";
			arm-supply = <&reg_arm>;
			pu-supply = <&reg_pu>;
			soc-supply = <&reg_soc>;
			nvmem-cells = <&cpu_speed_grade>;
			nvmem-cell-names = "speed_grade";
		};
	};

	clocks {
		ckil {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupt-parent = <&gpc>;
		interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
	};

	usbphynop1: usbphynop1 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gpc>;
		ranges;

		ocram: sram@900000 {
			compatible = "mmio-sram";
			reg = <0x00900000 0x20000>;
			ranges = <0 0x00900000 0x20000>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&clks IMX6SL_CLK_OCRAM>;
		};

		intc: interrupt-controller@a01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x00a01000 0x1000>,
			      <0x00a00100 0x100>;
			interrupt-parent = <&intc>;
		};

		L2: cache-controller@a02000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a02000 0x1000>;
			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-level = <2>;
			arm,tag-latency = <4 2 3>;
			arm,data-latency = <4 2 3>;
		};

		aips1: bus@2000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02000000 0x100000>;
			ranges;

			spba: spba-bus@2000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x02000000 0x40000>;
				ranges;

				spdif: spdif@2004000 {
					compatible = "fsl,imx6sl-spdif",
						"fsl,imx35-spdif";
					reg = <0x02004000 0x4000>;
					interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&sdma 14 18 0>,
						<&sdma 15 18 0>;
					dma-names = "rx", "tx";
					clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
						 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
						 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
						 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
						 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
					clock-names = "core", "rxtx0",
						"rxtx1", "rxtx2",
						"rxtx3", "rxtx4",
						"rxtx5", "rxtx6",
						"rxtx7", "spba";
					status = "disabled";
				};

				ecspi1: spi@2008000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
					reg = <0x02008000 0x4000>;
					interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SL_CLK_ECSPI1>,
						 <&clks IMX6SL_CLK_ECSPI1>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi2: spi@200c000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
					reg = <0x0200c000 0x4000>;
					interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SL_CLK_ECSPI2>,
						 <&clks IMX6SL_CLK_ECSPI2>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi3: spi@2010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
					reg = <0x02010000 0x4000>;
					interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SL_CLK_ECSPI3>,
						 <&clks IMX6SL_CLK_ECSPI3>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi4: spi@2014000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
					reg = <0x02014000 0x4000>;
					interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SL_CLK_ECSPI4>,
						 <&clks IMX6SL_CLK_ECSPI4>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				uart5: serial@2018000 {
					compatible = "fsl,imx6sl-uart",
						     "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02018000 0x4000>;
					interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SL_CLK_UART>,
						 <&clks IMX6SL_CLK_UART_SERIAL>;
					clock-names = "ipg", "per";
					dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart1: serial@2020000 {
					compatible = "fsl,imx6sl-uart",
						     "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02020000 0x4000>;
					interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SL_CLK_UART>,
						 <&clks IMX6SL_CLK_UART_SERIAL>;
					clock-names = "ipg", "per";
					dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart2: serial@2024000 {
					compatible = "fsl,imx6sl-uart",
						     "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02024000 0x4000>;
					interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SL_CLK_UART>,
						 <&clks IMX6SL_CLK_UART_SERIAL>;
					clock-names = "ipg", "per";
					dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ssi1: ssi@2028000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6sl-ssi",
							"fsl,imx51-ssi";
					reg = <0x02028000 0x4000>;
					interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
						 <&clks IMX6SL_CLK_SSI1>;
					clock-names = "ipg", "baud";
					dmas = <&sdma 37 1 0>,
					       <&sdma 38 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				ssi2: ssi@202c000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6sl-ssi",
							"fsl,imx51-ssi";
					reg = <0x0202c000 0x4000>;
					interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
						 <&clks IMX6SL_CLK_SSI2>;
					clock-names = "ipg", "baud";
					dmas = <&sdma 41 1 0>,
					       <&sdma 42 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				ssi3: ssi@2030000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6sl-ssi",
							"fsl,imx51-ssi";
					reg = <0x02030000 0x4000>;
					interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
						 <&clks IMX6SL_CLK_SSI3>;
					clock-names = "ipg", "baud";
					dmas = <&sdma 45 1 0>,
					       <&sdma 46 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				uart3: serial@2034000 {
					compatible = "fsl,imx6sl-uart",
						     "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02034000 0x4000>;
					interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SL_CLK_UART>,
						 <&clks IMX6SL_CLK_UART_SERIAL>;
					clock-names = "ipg", "per";
					dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart4: serial@2038000 {
					compatible = "fsl,imx6sl-uart",
						     "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02038000 0x4000>;
					interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SL_CLK_UART>,
						 <&clks IMX6SL_CLK_UART_SERIAL>;
					clock-names = "ipg", "per";
					dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};
			};

			pwm1: pwm@2080000 {
				#pwm-cells = <3>;
				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
				reg = <0x02080000 0x4000>;
				interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_PERCLK>,
					 <&clks IMX6SL_CLK_PWM1>;
				clock-names = "ipg", "per";
			};

			pwm2: pwm@2084000 {
				#pwm-cells = <3>;
				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
				reg = <0x02084000 0x4000>;
				interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_PERCLK>,
					 <&clks IMX6SL_CLK_PWM2>;
				clock-names = "ipg", "per";
			};

			pwm3: pwm@2088000 {
				#pwm-cells = <3>;
				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
				reg = <0x02088000 0x4000>;
				interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_PERCLK>,
					 <&clks IMX6SL_CLK_PWM3>;
				clock-names = "ipg", "per";
			};

			pwm4: pwm@208c000 {
				#pwm-cells = <3>;
				compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
				reg = <0x0208c000 0x4000>;
				interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_PERCLK>,
					 <&clks IMX6SL_CLK_PWM4>;
				clock-names = "ipg", "per";
			};

			gpt: timer@2098000 {
				compatible = "fsl,imx6sl-gpt";
				reg = <0x02098000 0x4000>;
				interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_GPT>,
					 <&clks IMX6SL_CLK_GPT_SERIAL>;
				clock-names = "ipg", "per";
			};

			gpio1: gpio@209c000 {
				compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
				reg = <0x0209c000 0x4000>;
				interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
					     <0 67 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc  0 22 1>, <&iomuxc  1 20 2>,
					      <&iomuxc  3 23 1>, <&iomuxc  4 25 1>,
					      <&iomuxc  5 24 1>, <&iomuxc  6 19 1>,
					      <&iomuxc  7 36 2>, <&iomuxc  9 44 8>,
					      <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
					      <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
			};

			gpio2: gpio@20a0000 {
				compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
				reg = <0x020a0000 0x4000>;
				interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
					     <0 69 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc  0  53 3>, <&iomuxc  3  72 2>,
					      <&iomuxc  5  34 2>, <&iomuxc  7  57 4>,
					      <&iomuxc 11  56 1>, <&iomuxc 12  61 3>,
					      <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
					      <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
					      <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
					      <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
			};

			gpio3: gpio@20a4000 {
				compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
				reg = <0x020a4000 0x4000>;
				interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
					     <0 71 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc  0 112 8>, <&iomuxc  8 121 4>,
					      <&iomuxc 12  97 4>, <&iomuxc 16 166 3>,
					      <&iomuxc 19  85 2>, <&iomuxc 21 137 2>,
					      <&iomuxc 23 136 1>, <&iomuxc 24  91 1>,
					      <&iomuxc 25  99 1>, <&iomuxc 26  92 1>,
					      <&iomuxc 27 100 1>, <&iomuxc 28  93 1>,
					      <&iomuxc 29 101 1>, <&iomuxc 30  94 1>,
					      <&iomuxc 31 102 1>;
			};

			gpio4: gpio@20a8000 {
				compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
				reg = <0x020a8000 0x4000>;
				interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
					     <0 73 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc  0  95 1>, <&iomuxc  1 103 1>,
					      <&iomuxc  2  96 1>, <&iomuxc  3 104 1>,
					      <&iomuxc  4  97 1>, <&iomuxc  5 105 1>,
					      <&iomuxc  6  98 1>, <&iomuxc  7 106 1>,
					      <&iomuxc  8  28 1>, <&iomuxc  9  27 1>,
					      <&iomuxc 10  26 1>, <&iomuxc 11  29 1>,
					      <&iomuxc 12  32 1>, <&iomuxc 13  31 1>,
					      <&iomuxc 14  30 1>, <&iomuxc 15  33 1>,
					      <&iomuxc 16  84 1>, <&iomuxc 17  79 2>,
					      <&iomuxc 19  78 1>, <&iomuxc 20  76 1>,
					      <&iomuxc 21  81 2>, <&iomuxc 23  75 1>,
					      <&iomuxc 24  83 1>, <&iomuxc 25  74 1>,
					      <&iomuxc 26  77 1>, <&iomuxc 27 159 1>,
					      <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
					      <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
			};

			gpio5: gpio@20ac000 {
				compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
				reg = <0x020ac000 0x4000>;
				interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
					     <0 75 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc  0 158 1>, <&iomuxc  1 151 1>,
					      <&iomuxc  2 155 1>, <&iomuxc  3 153 1>,
					      <&iomuxc  4 150 1>, <&iomuxc  5 149 1>,
					      <&iomuxc  6 144 1>, <&iomuxc  7 147 1>,
					      <&iomuxc  8 142 1>, <&iomuxc  9 146 1>,
					      <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
					      <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
					      <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
					      <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
					      <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
					      <&iomuxc 21 161 1>;
			};

			kpp: keypad@20b8000 {
				compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
				reg = <0x020b8000 0x4000>;
				interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_IPG>;
				status = "disabled";
			};

			wdog1: watchdog@20bc000 {
				compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
				reg = <0x020bc000 0x4000>;
				interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_IPG>;
			};

			wdog2: watchdog@20c0000 {
				compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
				reg = <0x020c0000 0x4000>;
				interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_IPG>;
				status = "disabled";
			};

			clks: clock-controller@20c4000 {
				compatible = "fsl,imx6sl-ccm";
				reg = <0x020c4000 0x4000>;
				interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
					     <0 88 IRQ_TYPE_LEVEL_HIGH>;
				#clock-cells = <1>;
			};

			anatop: anatop@20c8000 {
				compatible = "fsl,imx6sl-anatop",
					     "fsl,imx6q-anatop",
					     "syscon", "simple-mfd";
				reg = <0x020c8000 0x1000>;
				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
					     <0 54 IRQ_TYPE_LEVEL_HIGH>,
					     <0 127 IRQ_TYPE_LEVEL_HIGH>;

				reg_vdd1p1: regulator-1p1 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd1p1";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
					anatop-reg-offset = <0x110>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <4>;
					anatop-min-voltage = <800000>;
					anatop-max-voltage = <1375000>;
					anatop-enable-bit = <0>;
				};

				reg_vdd3p0: regulator-3p0 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd3p0";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <3150000>;
					regulator-always-on;
					anatop-reg-offset = <0x120>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
					anatop-min-voltage = <2625000>;
					anatop-max-voltage = <3400000>;
					anatop-enable-bit = <0>;
				};

				reg_vdd2p5: regulator-2p5 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd2p5";
					regulator-min-microvolt = <2250000>;
					regulator-max-microvolt = <2750000>;
					regulator-always-on;
					anatop-reg-offset = <0x130>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
					anatop-min-voltage = <2100000>;
					anatop-max-voltage = <2850000>;
					anatop-enable-bit = <0>;
				};

				reg_arm: regulator-vddcore {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddarm";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <0>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <24>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				reg_pu: regulator-vddpu {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddpu";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <9>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <26>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				reg_soc: regulator-vddsoc {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddsoc";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <18>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <28>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				tempmon: tempmon {
					compatible = "fsl,imx6q-tempmon";
					interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-parent = <&gpc>;
					fsl,tempmon = <&anatop>;
					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
					nvmem-cell-names = "calib", "temp_grade";
					clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
				};
			};

			usbphy1: usbphy@20c9000 {
				compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
				reg = <0x020c9000 0x1000>;
				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_USBPHY1>;
				fsl,anatop = <&anatop>;
			};

			usbphy2: usbphy@20ca000 {
				compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
				reg = <0x020ca000 0x1000>;
				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_USBPHY2>;
				fsl,anatop = <&anatop>;
			};

			snvs: snvs@20cc000 {
				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
				reg = <0x020cc000 0x4000>;

				snvs_rtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap = <&snvs>;
					offset = <0x34>;
					interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
						     <0 20 IRQ_TYPE_LEVEL_HIGH>;
				};

				snvs_poweroff: snvs-poweroff {
					compatible = "syscon-poweroff";
					regmap = <&snvs>;
					offset = <0x38>;
					value = <0x60>;
					mask = <0x60>;
					status = "disabled";
				};
			};

			epit1: epit@20d0000 {
				reg = <0x020d0000 0x4000>;
				interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			epit2: epit@20d4000 {
				reg = <0x020d4000 0x4000>;
				interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
			};

			src: reset-controller@20d8000 {
				compatible = "fsl,imx6sl-src", "fsl,imx51-src";
				reg = <0x020d8000 0x4000>;
				interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
					     <0 96 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};

			gpc: gpc@20dc000 {
				compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
				reg = <0x020dc000 0x4000>;
				interrupt-controller;
				#interrupt-cells = <3>;
				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-parent = <&intc>;
				clocks = <&clks IMX6SL_CLK_IPG>;
				clock-names = "ipg";

				pgc {
					#address-cells = <1>;
					#size-cells = <0>;

					power-domain@0 {
						reg = <0>;
						#power-domain-cells = <0>;
					};

					pd_pu: power-domain@1 {
						reg = <1>;
						#power-domain-cells = <0>;
						power-supply = <&reg_pu>;
						clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
							 <&clks IMX6SL_CLK_GPU2D_PODF>;
					};

					pd_disp: power-domain@2 {
						reg = <2>;
						#power-domain-cells = <0>;
						clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
							 <&clks IMX6SL_CLK_LCDIF_PIX>,
							 <&clks IMX6SL_CLK_EPDC_AXI>,
							 <&clks IMX6SL_CLK_EPDC_PIX>,
							 <&clks IMX6SL_CLK_PXP_AXI>;
					};
				};
			};

			gpr: iomuxc-gpr@20e0000 {
				compatible = "fsl,imx6sl-iomuxc-gpr",
					     "fsl,imx6q-iomuxc-gpr", "syscon";
				reg = <0x020e0000 0x38>;
			};

			iomuxc: pinctrl@20e0000 {
				compatible = "fsl,imx6sl-iomuxc";
				reg = <0x020e0000 0x4000>;
			};

			csi: csi@20e4000 {
				reg = <0x020e4000 0x4000>;
				interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
			};

			spdc: spdc@20e8000 {
				reg = <0x020e8000 0x4000>;
				interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
			};

			sdma: dma-controller@20ec000 {
				compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
				reg = <0x020ec000 0x4000>;
				interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_SDMA>,
					 <&clks IMX6SL_CLK_AHB>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				/* imx6sl reuses imx6q sdma firmware */
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
			};

			pxp: pxp@20f0000 {
				reg = <0x020f0000 0x4000>;
				interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
			};

			epdc: epdc@20f4000 {
				reg = <0x020f4000 0x4000>;
				interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
			};

			lcdif: lcdif@20f8000 {
				compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
				reg = <0x020f8000 0x4000>;
				interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
					 <&clks IMX6SL_CLK_LCDIF_AXI>,
					 <&clks IMX6SL_CLK_DUMMY>;
				clock-names = "pix", "axi", "disp_axi";
				status = "disabled";
				power-domains = <&pd_disp>;
			};

			dcp: crypto@20fc000 {
				compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
				reg = <0x020fc000 0x4000>;
				interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
					     <0 100 IRQ_TYPE_LEVEL_HIGH>,
					     <0 101 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		aips2: bus@2100000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02100000 0x100000>;
			ranges;

			usbotg1: usb@2184000 {
				compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
				reg = <0x02184000 0x200>;
				interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_USBOH3>;
				fsl,usbphy = <&usbphy1>;
				fsl,usbmisc = <&usbmisc 0>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbotg2: usb@2184200 {
				compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
				reg = <0x02184200 0x200>;
				interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_USBOH3>;
				fsl,usbphy = <&usbphy2>;
				fsl,usbmisc = <&usbmisc 1>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbh: usb@2184400 {
				compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
				reg = <0x02184400 0x200>;
				interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_USBOH3>;
				fsl,usbphy = <&usbphynop1>;
				phy_type = "hsic";
				fsl,usbmisc = <&usbmisc 2>;
				dr_mode = "host";
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbmisc: usbmisc@2184800 {
				#index-cells = <1>;
				compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
				reg = <0x02184800 0x200>;
				clocks = <&clks IMX6SL_CLK_USBOH3>;
			};

			fec: ethernet@2188000 {
				compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
				reg = <0x02188000 0x4000>;
				interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_ENET>,
					 <&clks IMX6SL_CLK_ENET_REF>;
				clock-names = "ipg", "ahb";
				status = "disabled";
			};

			usdhc1: mmc@2190000 {
				compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
				reg = <0x02190000 0x4000>;
				interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_USDHC1>,
					 <&clks IMX6SL_CLK_USDHC1>,
					 <&clks IMX6SL_CLK_USDHC1>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@2194000 {
				compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
				reg = <0x02194000 0x4000>;
				interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_USDHC2>,
					 <&clks IMX6SL_CLK_USDHC2>,
					 <&clks IMX6SL_CLK_USDHC2>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc3: mmc@2198000 {
				compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
				reg = <0x02198000 0x4000>;
				interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_USDHC3>,
					 <&clks IMX6SL_CLK_USDHC3>,
					 <&clks IMX6SL_CLK_USDHC3>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc4: mmc@219c000 {
				compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
				reg = <0x0219c000 0x4000>;
				interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_USDHC4>,
					 <&clks IMX6SL_CLK_USDHC4>,
					 <&clks IMX6SL_CLK_USDHC4>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			i2c1: i2c@21a0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
				reg = <0x021a0000 0x4000>;
				interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_I2C1>;
				status = "disabled";
			};

			i2c2: i2c@21a4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
				reg = <0x021a4000 0x4000>;
				interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_I2C2>;
				status = "disabled";
			};

			i2c3: i2c@21a8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
				reg = <0x021a8000 0x4000>;
				interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_I2C3>;
				status = "disabled";
			};

			memory-controller@21b0000 {
				compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
				reg = <0x021b0000 0x4000>;
				clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
			};

			rngb: rngb@21b4000 {
				compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
				reg = <0x021b4000 0x4000>;
				interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SL_CLK_DUMMY>;
			};

			weim: weim@21b8000 {
				#address-cells = <2>;
				#size-cells = <1>;
				reg = <0x021b8000 0x4000>;
				interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
				fsl,weim-cs-gpr = <&gpr>;
				status = "disabled";
			};

			ocotp: efuse@21bc000 {
				compatible = "fsl,imx6sl-ocotp", "syscon";
				reg = <0x021bc000 0x4000>;
				clocks = <&clks IMX6SL_CLK_OCOTP>;
				#address-cells = <1>;
				#size-cells = <1>;

				cpu_speed_grade: speed-grade@10 {
					reg = <0x10 4>;
				};

				tempmon_calib: calib@38 {
					reg = <0x38 4>;
				};

				tempmon_temp_grade: temp-grade@20 {
					reg = <0x20 4>;
				};
			};

			audmux: audmux@21d8000 {
				compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
				reg = <0x021d8000 0x4000>;
				status = "disabled";
			};
		};

		gpu_2d: gpu@2200000 {
			compatible = "vivante,gc";
			reg = <0x02200000 0x4000>;
			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
				 <&clks IMX6SL_CLK_GPU2D_OVG>;
			clock-names = "bus", "core";
			power-domains = <&pd_pu>;
		};

		gpu_vg: gpu@2204000 {
			compatible = "vivante,gc";
			reg = <0x02204000 0x4000>;
			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
				 <&clks IMX6SL_CLK_GPU2D_OVG>;
			clock-names = "bus", "core";
			power-domains = <&pd_pu>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017-2018 NXP.
 *
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sll.dtsi"

/ {
	model = "Freescale i.MX6SLL EVK Board";
	compatible = "fsl,imx6sll-evk", "fsl,imx6sll";

	chosen {
		stdout-path = &uart1;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x80000000>;
	};

	backlight_display: backlight-display {
		compatible = "pwm-backlight";
		pwms = <&pwm1 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
		status = "okay";
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_led>;

		user {
			label = "debug";
			gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	reg_usb_otg1_vbus: regulator-otg1-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
		regulator-name = "usb_otg1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usb_otg2_vbus: regulator-otg2-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb_otg2_vbus>;
		regulator-name = "usb_otg2_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_aud3v: regulator-aud3v {
		compatible = "regulator-fixed";
		regulator-name = "wm8962-supply-3v15";
		regulator-min-microvolt = <3150000>;
		regulator-max-microvolt = <3150000>;
		regulator-boot-on;
	};

	reg_aud4v: regulator-aud4v {
		compatible = "regulator-fixed";
		regulator-name = "wm8962-supply-4v2";
		regulator-min-microvolt = <4325000>;
		regulator-max-microvolt = <4325000>;
		regulator-boot-on;
	};

	reg_lcd_3v3: regulator-lcd-3v3 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
		regulator-name = "lcd-3v3";
		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_lcd_5v: regulator-lcd-5v {
		compatible = "regulator-fixed";
		regulator-name = "lcd-5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_sd1_vmmc: regulator-sd1-vmmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_sd1_vmmc>;
		regulator-name = "SD1_SPWR";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_sd3_vmmc: regulator-sd3-vmmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_sd3_vmmc>;
		regulator-name = "SD3_WIFI";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	panel {
		compatible = "sii,43wvf1g";
		backlight = <&backlight_display>;
		dvdd-supply = <&reg_lcd_3v3>;
		avdd-supply = <&reg_lcd_5v>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&display_out>;
			};
		};
	};

	sound {
		compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_hp>;
		model = "wm8962-audio";
		audio-cpu = <&ssi2>;
		audio-codec = <&wm8962>;
		audio-routing =
			"Headphone Jack", "HPOUTL",
			"Headphone Jack", "HPOUTR",
			"Ext Spk", "SPKOUTL",
			"Ext Spk", "SPKOUTR",
			"AMIC", "MICBIAS",
			"IN3R", "AMIC";
		mux-int-port = <2>;
		mux-ext-port = <3>;
		hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux3>;
	status = "okay";
};

&cpu0 {
	arm-supply = <&sw1a_reg>;
	soc-supply = <&sw1c_reg>;
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pfuze100: pmic@8 {
		compatible = "fsl,pfuze100";
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw1c_reg: sw1c {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3a_reg: sw3a {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3b_reg: sw3b {
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1975000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
				regulator-always-on;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};

			vgen4_reg: vgen4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen5_reg: vgen5 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
		};
	};
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	wm8962: audio-codec@1a {
		compatible = "wlf,wm8962";
		reg = <0x1a>;
		clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
		DCVDD-supply = <&vgen3_reg>;
		DBVDD-supply = <&reg_aud3v>;
		AVDD-supply = <&vgen3_reg>;
		CPVDD-supply = <&vgen3_reg>;
		MICVDD-supply = <&reg_aud3v>;
		PLLVDD-supply = <&vgen3_reg>;
		SPKVDD1-supply = <&reg_aud4v>;
		SPKVDD2-supply = <&reg_aud4v>;
	};
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd>;
	status = "okay";

	port {
		display_out: endpoint {
			remote-endpoint = <&panel_in>;
		};
	};
};

&pwm1 {
	#pwm-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&snvs_poweroff {
	status = "okay";
};

&snvs_pwrkey {
	status = "okay";
};

&ssi2 {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&reg_sd1_vmmc>;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	disable-over-current;
	srp-disable;
	hnp-disable;
	adp-disable;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usb_otg2_vbus>;
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&reg_sd3_vmmc>;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog1>;
	fsl,ext-reset-output;
};

&iomuxc {
	pinctrl_audmux3: audmux3grp {
		fsl,pins = <
			MX6SLL_PAD_AUD_TXC__AUD3_TXC		0x4130b0
			MX6SLL_PAD_AUD_TXFS__AUD3_TXFS		0x4130b0
			MX6SLL_PAD_AUD_TXD__AUD3_TXD		0x4110b0
			MX6SLL_PAD_AUD_RXD__AUD3_RXD		0x4130b0
			MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT	0x4130b0
		>;
	};

	pinctrl_hp: hpgrp {
		fsl,pins = <
			MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
		>;
	};

	pinctrl_reg_sd3_vmmc: sd3vmmcgrp {
		fsl,pins = <
			MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059
		>;
	};

	pinctrl_usb_otg1_vbus: vbus1grp {
		fsl,pins = <
			MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
		>;
	};

	pinctrl_usb_otg2_vbus: vbus2grp {
		fsl,pins = <
			MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
		>;
	};

	pinctrl_reg_lcd_3v3: reglcd3v3grp {
		fsl,pins = <
			MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059
		>;
	};

	pinctrl_reg_sd1_vmmc: sd1vmmcgrp {
		fsl,pins = <
			MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
			MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6SLL_PAD_SD1_CMD__SD1_CMD	0x17059
			MX6SLL_PAD_SD1_CLK__SD1_CLK	0x13059
			MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x17059
			MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x17059
			MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x17059
			MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x17059
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
		fsl,pins = <
			MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170b9
			MX6SLL_PAD_SD1_CLK__SD1_CLK	0x130b9
			MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170b9
			MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170b9
			MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170b9
			MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170b9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
		fsl,pins = <
			MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170f9
			MX6SLL_PAD_SD1_CLK__SD1_CLK	0x130f9
			MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170f9
			MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170f9
			MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170f9
			MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170f9
		>;
	};

	pinctrl_usbotg1: usbotg1grp {
		fsl,pins = <
			MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6SLL_PAD_SD3_CMD__SD3_CMD		0x17061
			MX6SLL_PAD_SD3_CLK__SD3_CLK		0x13061
			MX6SLL_PAD_SD3_DATA0__SD3_DATA0		0x17061
			MX6SLL_PAD_SD3_DATA1__SD3_DATA1		0x17061
			MX6SLL_PAD_SD3_DATA2__SD3_DATA2		0x17061
			MX6SLL_PAD_SD3_DATA3__SD3_DATA3		0x17061
			MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22	0x17059
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
		fsl,pins = <
			MX6SLL_PAD_SD3_CMD__SD3_CMD		0x170a1
			MX6SLL_PAD_SD3_CLK__SD3_CLK		0x130a1
			MX6SLL_PAD_SD3_DATA0__SD3_DATA0		0x170a1
			MX6SLL_PAD_SD3_DATA1__SD3_DATA1		0x170a1
			MX6SLL_PAD_SD3_DATA2__SD3_DATA2		0x170a1
			MX6SLL_PAD_SD3_DATA3__SD3_DATA3		0x170a1
			MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22	0x17059
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
		fsl,pins = <
			MX6SLL_PAD_SD3_CMD__SD3_CMD		0x170e9
			MX6SLL_PAD_SD3_CLK__SD3_CLK		0x130f9
			MX6SLL_PAD_SD3_DATA0__SD3_DATA0		0x170e9
			MX6SLL_PAD_SD3_DATA1__SD3_DATA1		0x170e9
			MX6SLL_PAD_SD3_DATA2__SD3_DATA2		0x170e9
			MX6SLL_PAD_SD3_DATA3__SD3_DATA3		0x170e9
			MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22	0x17059
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6SLL_PAD_I2C1_SCL__I2C1_SCL	 0x4001b8b1
			MX6SLL_PAD_I2C1_SDA__I2C1_SDA	 0x4001b8b1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6SLL_PAD_AUD_RXFS__I2C3_SCL  0x4041b8b1
			MX6SLL_PAD_AUD_RXC__I2C3_SDA   0x4041b8b1
		>;
	};

	pinctrl_lcd: lcdgrp {
		fsl,pins = <
			MX6SLL_PAD_LCD_DATA00__LCD_DATA00	0x79
			MX6SLL_PAD_LCD_DATA01__LCD_DATA01	0x79
			MX6SLL_PAD_LCD_DATA02__LCD_DATA02	0x79
			MX6SLL_PAD_LCD_DATA03__LCD_DATA03	0x79
			MX6SLL_PAD_LCD_DATA04__LCD_DATA04	0x79
			MX6SLL_PAD_LCD_DATA05__LCD_DATA05	0x79
			MX6SLL_PAD_LCD_DATA06__LCD_DATA06	0x79
			MX6SLL_PAD_LCD_DATA07__LCD_DATA07	0x79
			MX6SLL_PAD_LCD_DATA08__LCD_DATA08	0x79
			MX6SLL_PAD_LCD_DATA09__LCD_DATA09	0x79
			MX6SLL_PAD_LCD_DATA10__LCD_DATA10	0x79
			MX6SLL_PAD_LCD_DATA11__LCD_DATA11	0x79
			MX6SLL_PAD_LCD_DATA12__LCD_DATA12	0x79
			MX6SLL_PAD_LCD_DATA13__LCD_DATA13	0x79
			MX6SLL_PAD_LCD_DATA14__LCD_DATA14	0x79
			MX6SLL_PAD_LCD_DATA15__LCD_DATA15	0x79
			MX6SLL_PAD_LCD_DATA16__LCD_DATA16	0x79
			MX6SLL_PAD_LCD_DATA17__LCD_DATA17	0x79
			MX6SLL_PAD_LCD_DATA18__LCD_DATA18	0x79
			MX6SLL_PAD_LCD_DATA19__LCD_DATA19	0x79
			MX6SLL_PAD_LCD_DATA20__LCD_DATA20	0x79
			MX6SLL_PAD_LCD_DATA21__LCD_DATA21	0x79
			MX6SLL_PAD_LCD_DATA22__LCD_DATA22	0x79
			MX6SLL_PAD_LCD_DATA23__LCD_DATA23	0x79
			MX6SLL_PAD_LCD_CLK__LCD_CLK		0x79
			MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE	0x79
			MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC		0x79
			MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC		0x79
			MX6SLL_PAD_LCD_RESET__LCD_RESET		0x79
		>;
	};

	pinctrl_led: ledgrp {
		fsl,pins = <
			MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04	0x17059
		>;
	};

	pinctrl_pwm1: pmw1grp {
		fsl,pins = <
			MX6SLL_PAD_PWM1__PWM1_OUT   0x110b0
		>;
	};

	pinctrl_wdog1: wdog1grp	{
		fsl,pins = <
			MX6SLL_PAD_WDOG_B__WDOG1_B   0x170b0
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0)
/*
 * Device tree for the Kobo Clara HD ebook reader
 *
 * Name on mainboard is: 37NB-E60K00+4A4
 * Serials start with: E60K02 (a number also seen in
 * vendor kernel sources)
 *
 * This mainboard seems to be equipped with different SoCs.
 * In the Kobo Clara HD ebook reader it is an i.MX6SLL
 *
 * Copyright 2019 Andreas Kemnade
 * based on works
 * Copyright 2016 Freescale Semiconductor, Inc.
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx6sll.dtsi"
#include "e60k02.dtsi"

/ {
	model = "Kobo Clara HD";
	compatible = "kobo,clarahd", "fsl,imx6sll";
};

&clks {
	assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <393216000>;
};

&cpu0 {
	arm-supply = <&dcdc3_reg>;
	soc-supply = <&dcdc1_reg>;
};

&gpio_keys {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_keys>;
};

&i2c1 {
	pinctrl-names = "default","sleep";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_sleep>;
};

&i2c2 {
	pinctrl-names = "default","sleep";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_sleep>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp {
		fsl,pins = <
			MX6SLL_PAD_SD1_DATA3__GPIO5_IO06                0x17059 /* TP_INT */
			MX6SLL_PAD_SD1_DATA2__GPIO5_IO13                0x10059 /* TP_RST */
		>;
	};

	pinctrl_gpio_keys: gpio-keysgrp {
		fsl,pins = <
			MX6SLL_PAD_SD1_DATA1__GPIO5_IO08	0x17059	/* PWR_SW */
			MX6SLL_PAD_SD1_DATA4__GPIO5_IO12	0x17059	/* HALL_EN */
		>;
	};

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX6SLL_PAD_LCD_DATA00__GPIO2_IO20	0x79
			MX6SLL_PAD_LCD_DATA01__GPIO2_IO21	0x79
			MX6SLL_PAD_LCD_DATA02__GPIO2_IO22	0x79
			MX6SLL_PAD_LCD_DATA03__GPIO2_IO23	0x79
			MX6SLL_PAD_LCD_DATA04__GPIO2_IO24	0x79
			MX6SLL_PAD_LCD_DATA05__GPIO2_IO25	0x79
			MX6SLL_PAD_LCD_DATA06__GPIO2_IO26	0x79
			MX6SLL_PAD_LCD_DATA07__GPIO2_IO27	0x79
			MX6SLL_PAD_LCD_DATA08__GPIO2_IO28	0x79
			MX6SLL_PAD_LCD_DATA09__GPIO2_IO29	0x79
			MX6SLL_PAD_LCD_DATA10__GPIO2_IO30	0x79
			MX6SLL_PAD_LCD_DATA11__GPIO2_IO31	0x79
			MX6SLL_PAD_LCD_DATA12__GPIO3_IO00	0x79
			MX6SLL_PAD_LCD_DATA13__GPIO3_IO01	0x79
			MX6SLL_PAD_LCD_DATA14__GPIO3_IO02	0x79
			MX6SLL_PAD_LCD_DATA15__GPIO3_IO03	0x79
			MX6SLL_PAD_LCD_DATA16__GPIO3_IO04	0x79
			MX6SLL_PAD_LCD_DATA17__GPIO3_IO05	0x79
			MX6SLL_PAD_LCD_DATA18__GPIO3_IO06	0x79
			MX6SLL_PAD_LCD_DATA19__GPIO3_IO07	0x79
			MX6SLL_PAD_LCD_DATA20__GPIO3_IO08	0x79
			MX6SLL_PAD_LCD_DATA21__GPIO3_IO09	0x79
			MX6SLL_PAD_LCD_DATA22__GPIO3_IO10	0x79
			MX6SLL_PAD_LCD_DATA23__GPIO3_IO11	0x79
			MX6SLL_PAD_LCD_CLK__GPIO2_IO15		0x79
			MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16	0x79
			MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17	0x79
			MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18	0x79
			MX6SLL_PAD_LCD_RESET__GPIO2_IO19	0x79
			MX6SLL_PAD_KEY_COL3__GPIO3_IO30		0x79
			MX6SLL_PAD_KEY_ROW7__GPIO4_IO07		0x79
			MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13	0x79
			MX6SLL_PAD_KEY_COL5__GPIO4_IO02		0x79
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6SLL_PAD_I2C1_SCL__I2C1_SCL	0x4001f8b1
			MX6SLL_PAD_I2C1_SDA__I2C1_SDA	0x4001f8b1
		>;
	};

	pinctrl_i2c1_sleep: i2c1grp-sleep {
		fsl,pins = <
			MX6SLL_PAD_I2C1_SCL__I2C1_SCL	0x400108b1
			MX6SLL_PAD_I2C1_SDA__I2C1_SDA	0x400108b1
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6SLL_PAD_I2C2_SCL__I2C2_SCL	0x4001f8b1
			MX6SLL_PAD_I2C2_SDA__I2C2_SDA	0x4001f8b1
		>;
	};

	pinctrl_i2c2_sleep: i2c2grp-sleep {
		fsl,pins = <
			MX6SLL_PAD_I2C2_SCL__I2C2_SCL	0x400108b1
			MX6SLL_PAD_I2C2_SDA__I2C2_SDA	0x400108b1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
			MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
		>;
	};

	pinctrl_led: ledgrp {
		fsl,pins = <
			MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x17059
		>;
	};

	pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
		fsl,pins = <
			MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10	0x10059 /* HWEN */
		>;
	};

	pinctrl_ricoh_gpio: ricoh-gpiogrp {
		fsl,pins = <
			MX6SLL_PAD_SD1_CLK__GPIO5_IO15	0x1b8b1 /* ricoh619 chg */
			MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */
			MX6SLL_PAD_KEY_COL2__GPIO3_IO28	0x1b8b1 /* ricoh619 bat_low_int */
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
			MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x1b0b1
			MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x1b0b1
		>;
	};

	pinctrl_usbotg1: usbotg1grp {
		fsl,pins = <
			MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6SLL_PAD_SD2_CMD__SD2_CMD		0x17059
			MX6SLL_PAD_SD2_CLK__SD2_CLK		0x13059
			MX6SLL_PAD_SD2_DATA0__SD2_DATA0		0x17059
			MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x17059
			MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x17059
			MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x17059
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
		fsl,pins = <
			MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170b9
			MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130b9
			MX6SLL_PAD_SD2_DATA0__SD2_DATA0		0x170b9
			MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170b9
			MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170b9
			MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170b9
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
		fsl,pins = <
			MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170f9
			MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130f9
			MX6SLL_PAD_SD2_DATA0__SD2_DATA0		0x170f9
			MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170f9
			MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170f9
			MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170f9
		>;
	};

	pinctrl_usdhc2_sleep: usdhc2grp-sleep {
		fsl,pins = <
			MX6SLL_PAD_SD2_CMD__GPIO5_IO04		0x100f9
			MX6SLL_PAD_SD2_CLK__GPIO5_IO05		0x100f9
			MX6SLL_PAD_SD2_DATA0__GPIO5_IO01	0x100f9
			MX6SLL_PAD_SD2_DATA1__GPIO4_IO30	0x100f9
			MX6SLL_PAD_SD2_DATA2__GPIO5_IO03	0x100f9
			MX6SLL_PAD_SD2_DATA3__GPIO4_IO28	0x100f9
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6SLL_PAD_SD3_CMD__SD3_CMD	0x11059
			MX6SLL_PAD_SD3_CLK__SD3_CLK	0x11059
			MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x11059
			MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x11059
			MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x11059
			MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x11059
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
		fsl,pins = <
			MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170b9
			MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170b9
			MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170b9
			MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170b9
			MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170b9
			MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170b9
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
		fsl,pins = <
			MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170f9
			MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170f9
			MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170f9
			MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170f9
			MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170f9
			MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170f9
		>;
	};

	pinctrl_usdhc3_sleep: usdhc3grp-sleep {
		fsl,pins = <
			MX6SLL_PAD_SD3_CMD__GPIO5_IO21	0x100c1
			MX6SLL_PAD_SD3_CLK__GPIO5_IO18	0x100c1
			MX6SLL_PAD_SD3_DATA0__GPIO5_IO19	0x100c1
			MX6SLL_PAD_SD3_DATA1__GPIO5_IO20	0x100c1
			MX6SLL_PAD_SD3_DATA2__GPIO5_IO16	0x100c1
			MX6SLL_PAD_SD3_DATA3__GPIO5_IO17	0x100c1
		>;
	};

	pinctrl_wifi_power: wifi-powergrp {
		fsl,pins = <
			MX6SLL_PAD_SD2_DATA6__GPIO4_IO29	0x10059		/* WIFI_3V3_ON */
		>;
	};

	pinctrl_wifi_reset: wifi-resetgrp {
		fsl,pins = <
			MX6SLL_PAD_SD2_DATA7__GPIO5_IO00	0x10059		/* WIFI_RST */
		>;
	};
};

&leds {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_led>;
};

&lm3630a {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
};

&reg_wifi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wifi_power>;
};

&ricoh619 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ricoh_gpio>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	pinctrl-3 = <&pinctrl_usdhc2_sleep>;
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	pinctrl-3 = <&pinctrl_usdhc3_sleep>;
};

&wifi_pwrseq {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wifi_reset>;
};


code:
// SPDX-License-Identifier: (GPL-2.0)
/*
 * Device tree for the Kobo Libra H2O ebook reader
 *
 * Name on mainboard is: 37NB-E70K0M+6A3
 * Serials start with: E70K02 (a number also seen in
 * vendor kernel sources)
 *
 * This mainboard seems to be equipped with different SoCs.
 * In the Kobo Libra H2O ebook reader it is an i.MX6SLL
 *
 * Copyright 2021 Andreas Kemnade
 * based on works
 * Copyright 2016 Freescale Semiconductor, Inc.
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx6sll.dtsi"
#include "e70k02.dtsi"

/ {
	model = "Kobo Libra H2O";
	compatible = "kobo,librah2o", "fsl,imx6sll";
};

&clks {
	assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <393216000>;
};

&cpu0 {
	arm-supply = <&dcdc3_reg>;
	soc-supply = <&dcdc1_reg>;
};

&gpio_keys {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_keys>;
};

&i2c1 {
	pinctrl-names = "default","sleep";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_sleep>;
};

&i2c2 {
	pinctrl-names = "default","sleep";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_sleep>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_gpio_keys: gpio-keysgrp {
		fsl,pins = <
			MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25	0x17059	/* PWR_SW */
			MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23	0x17059	/* HALL_EN */
			MX6SLL_PAD_KEY_COL4__GPIO4_IO00		0x17059	/* PAGE_UP */
			MX6SLL_PAD_KEY_COL5__GPIO4_IO02		0x17059	/* PAGE_DOWN */
		>;
	};

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX6SLL_PAD_LCD_DATA01__GPIO2_IO21	0x79
			MX6SLL_PAD_LCD_DATA04__GPIO2_IO24	0x79
			MX6SLL_PAD_LCD_DATA05__GPIO2_IO25	0x79
			MX6SLL_PAD_LCD_DATA06__GPIO2_IO26	0x79
			MX6SLL_PAD_LCD_DATA07__GPIO2_IO27	0x79
			MX6SLL_PAD_LCD_DATA08__GPIO2_IO28	0x79
			MX6SLL_PAD_LCD_DATA09__GPIO2_IO29	0x79
			MX6SLL_PAD_LCD_DATA10__GPIO2_IO30	0x79
			MX6SLL_PAD_LCD_DATA11__GPIO2_IO31	0x79
			MX6SLL_PAD_LCD_DATA12__GPIO3_IO00	0x79
			MX6SLL_PAD_LCD_DATA13__GPIO3_IO01	0x79
			MX6SLL_PAD_LCD_DATA14__GPIO3_IO02	0x79
			MX6SLL_PAD_LCD_DATA15__GPIO3_IO03	0x79
			MX6SLL_PAD_LCD_DATA16__GPIO3_IO04	0x79
			MX6SLL_PAD_LCD_DATA17__GPIO3_IO05	0x79
			MX6SLL_PAD_LCD_DATA18__GPIO3_IO06	0x79
			MX6SLL_PAD_LCD_DATA19__GPIO3_IO07	0x79
			MX6SLL_PAD_LCD_DATA20__GPIO3_IO08	0x79
			MX6SLL_PAD_LCD_DATA21__GPIO3_IO09	0x79
			MX6SLL_PAD_LCD_DATA22__GPIO3_IO10	0x79
			MX6SLL_PAD_LCD_DATA23__GPIO3_IO11	0x79
			MX6SLL_PAD_LCD_CLK__GPIO2_IO15		0x79
			MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16	0x79
			MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17	0x79
			MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18	0x79
			MX6SLL_PAD_LCD_RESET__GPIO2_IO19	0x79
			MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21	0x79
			MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26	0x79
			MX6SLL_PAD_KEY_COL3__GPIO3_IO30		0x79
			MX6SLL_PAD_KEY_ROW7__GPIO4_IO07		0x79
			MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13	0x79
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6SLL_PAD_I2C1_SCL__I2C1_SCL   0x4001f8b1
			MX6SLL_PAD_I2C1_SDA__I2C1_SDA   0x4001f8b1
		>;
	};

	pinctrl_i2c1_sleep: i2c1grp-sleep {
		fsl,pins = <
			MX6SLL_PAD_I2C1_SCL__I2C1_SCL   0x400108b1
			MX6SLL_PAD_I2C1_SDA__I2C1_SDA   0x400108b1
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6SLL_PAD_I2C2_SCL__I2C2_SCL   0x4001f8b1
			MX6SLL_PAD_I2C2_SDA__I2C2_SDA   0x4001f8b1
		>;
	};

	pinctrl_i2c2_sleep: i2c2grp-sleep {
		fsl,pins = <
			MX6SLL_PAD_I2C2_SCL__I2C2_SCL   0x400108b1
			MX6SLL_PAD_I2C2_SDA__I2C2_SDA   0x400108b1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1
			MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1
		>;
	};

	pinctrl_led: ledgrp {
		fsl,pins = <
			MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17	0x10059
		>;
	};

	pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp {
		fsl,pins = <
			MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10   0x10059 /* HWEN */
		>;
	};

	pinctrl_ricoh_gpio: ricoh-gpiogrp {
		fsl,pins = <
			MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20	0x1b8b1 /* ricoh619 chg */
			MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19	0x1b8b1 /* ricoh619 irq */
			MX6SLL_PAD_KEY_COL2__GPIO3_IO28		0x1b8b1 /* ricoh619 bat_low_int */
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
			MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
		>;
	};

	pinctrl_usbotg1: usbotg1grp {
		fsl,pins = <
			MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6SLL_PAD_SD1_CMD__SD1_CMD	0x17059
			MX6SLL_PAD_SD1_CLK__SD1_CLK	0x17059
			MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x17059
			MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x17059
			MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x17059
			MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x17059
			MX6SLL_PAD_SD1_DATA4__SD1_DATA4	0x17059
			MX6SLL_PAD_SD1_DATA5__SD1_DATA5	0x17059
			MX6SLL_PAD_SD1_DATA6__SD1_DATA6	0x17059
			MX6SLL_PAD_SD1_DATA7__SD1_DATA7	0x17059
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170b9
			MX6SLL_PAD_SD1_CLK__SD1_CLK	0x170b9
			MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170b9
			MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170b9
			MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170b9
			MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170b9
			MX6SLL_PAD_SD1_DATA4__SD1_DATA4	0x170b9
			MX6SLL_PAD_SD1_DATA5__SD1_DATA5	0x170b9
			MX6SLL_PAD_SD1_DATA6__SD1_DATA6	0x170b9
			MX6SLL_PAD_SD1_DATA7__SD1_DATA7	0x170b9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170f9
			MX6SLL_PAD_SD1_CLK__SD1_CLK	0x170f9
			MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170f9
			MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170f9
			MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170f9
			MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170f9
			MX6SLL_PAD_SD1_DATA4__SD1_DATA4	0x170b9
			MX6SLL_PAD_SD1_DATA5__SD1_DATA5	0x170b9
			MX6SLL_PAD_SD1_DATA6__SD1_DATA6	0x170b9
			MX6SLL_PAD_SD1_DATA7__SD1_DATA7	0x170b9
		>;
	};

	pinctrl_usdhc1_sleep: usdhc1-sleepgrp {
		fsl,pins = <
			MX6SLL_PAD_SD1_CMD__SD1_CMD	0x10059
			MX6SLL_PAD_SD1_CLK__SD1_CLK	0x10059
			MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x10059
			MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x10059
			MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x10059
			MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x10059
			MX6SLL_PAD_SD1_DATA4__SD1_DATA4	0x10059
			MX6SLL_PAD_SD1_DATA5__SD1_DATA5	0x10059
			MX6SLL_PAD_SD1_DATA6__SD1_DATA6	0x10059
			MX6SLL_PAD_SD1_DATA7__SD1_DATA7	0x10059
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6SLL_PAD_SD3_CMD__SD3_CMD	0x11059
			MX6SLL_PAD_SD3_CLK__SD3_CLK	0x11059
			MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x11059
			MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x11059
			MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x11059
			MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x11059
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170b9
			MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170b9
			MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170b9
			MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170b9
			MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170b9
			MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170b9
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170f9
			MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170f9
			MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170f9
			MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170f9
			MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170f9
			MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170f9
		>;
	};

	pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
		fsl,pins = <
			MX6SLL_PAD_SD3_CMD__GPIO5_IO21	0x100c1
			MX6SLL_PAD_SD3_CLK__GPIO5_IO18	0x100c1
			MX6SLL_PAD_SD3_DATA0__GPIO5_IO19	0x100c1
			MX6SLL_PAD_SD3_DATA1__GPIO5_IO20	0x100c1
			MX6SLL_PAD_SD3_DATA2__GPIO5_IO16	0x100c1
			MX6SLL_PAD_SD3_DATA3__GPIO5_IO17	0x100c1
		>;
	};

	pinctrl_wifi_power: wifi-powergrp {
		fsl,pins = <
			MX6SLL_PAD_SD2_DATA6__GPIO4_IO29	0x10059	 /* WIFI_3V3_ON */
		>;
	};

	pinctrl_wifi_reset: wifi-resetgrp {
		fsl,pins = <
			MX6SLL_PAD_SD2_DATA7__GPIO5_IO00	0x10059	 /* WIFI_RST */
		>;
	};
};

&leds {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_led>;
};

&lm3630a {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>;
};

&reg_wifi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wifi_power>;
};

&ricoh619 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ricoh_gpio>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	pinctrl-3 = <&pinctrl_usdhc1_sleep>;
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	pinctrl-3 = <&pinctrl_usdhc3_sleep>;
};

&wifi_pwrseq {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wifi_reset>;
};