code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
 *
 *  Copyright (C) 2014 Atmel,
 *                2014 Nicolas Ferre <nicolas.ferre@atmel.com>
 */

#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Atmel SAMA5D4 family SoC";
	compatible = "atmel,sama5d4";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &usart3;
		serial1 = &usart4;
		serial2 = &usart2;
		serial3 = &usart0;
		serial4 = &usart1;
		serial5 = &uart0;
		serial6 = &uart1;
		gpio0 = &pioA;
		gpio1 = &pioB;
		gpio2 = &pioC;
		gpio3 = &pioD;
		gpio4 = &pioE;
		pwm0 = &pwm0;
		ssc0 = &ssc0;
		ssc1 = &ssc1;
		tcb0 = &tcb0;
		tcb1 = &tcb1;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
	};
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			reg = <0>;
			next-level-cache = <&L2>;
		};
	};

	memory@20000000 {
		device_type = "memory";
		reg = <0x20000000 0x20000000>;
	};

	clocks {
		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		adc_op_clk: adc_op_clk{
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000>;
		};
	};

	ns_sram: sram@210000 {
		compatible = "mmio-sram";
		reg = <0x00210000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x00210000 0x10000>;
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		nfc_sram: sram@100000 {
			compatible = "mmio-sram";
			no-memory-wc;
			reg = <0x100000 0x2400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x100000 0x2400>;
		};

		vdec0: vdec@300000 {
			compatible = "microchip,sama5d4-vdec";
			reg = <0x00300000 0x100000>;
			interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
		};

		usb0: gadget@400000 {
			compatible = "atmel,sama5d3-udc";
			reg = <0x00400000 0x100000
			       0xfc02c000 0x4000>;
			interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
			clock-names = "pclk", "hclk";
			status = "disabled";
		};

		usb1: ohci@500000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00500000 0x100000>;
			interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>;
			clock-names = "ohci_clk", "hclk", "uhpck";
			status = "disabled";
		};

		usb2: ehci@600000 {
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00600000 0x100000>;
			interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>;
			clock-names = "usb_clk", "ehci_clk";
			status = "disabled";
		};

		L2: cache-controller@a00000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a00000 0x1000>;
			interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
			cache-unified;
			cache-level = <2>;
		};

		ebi: ebi@10000000 {
			compatible = "atmel,sama5d3-ebi";
			#address-cells = <2>;
			#size-cells = <1>;
			atmel,smc = <&hsmc>;
			reg = <0x10000000 0x10000000
			       0x60000000 0x28000000>;
			ranges = <0x0 0x0 0x10000000 0x10000000
				  0x1 0x0 0x60000000 0x10000000
				  0x2 0x0 0x70000000 0x10000000
				  0x3 0x0 0x80000000 0x8000000>;
			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
			status = "disabled";

			nand_controller: nand-controller {
				compatible = "atmel,sama5d3-nand-controller";
				atmel,nfc-sram = <&nfc_sram>;
				atmel,nfc-io = <&nfc_io>;
				ecc-engine = <&pmecc>;
				#address-cells = <2>;
				#size-cells = <1>;
				ranges;
				status = "disabled";
			};
		};

		nfc_io: nfc-io@90000000 {
			compatible = "atmel,sama5d3-nfc-io", "syscon";
			reg = <0x90000000 0x8000000>;
		};

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			hlcdc: hlcdc@f0000000 {
				compatible = "atmel,sama5d4-hlcdc";
				reg = <0xf0000000 0x4000>;
				interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
				clock-names = "periph_clk","sys_clk", "slow_clk";
				status = "disabled";

				hlcdc-display-controller {
					compatible = "atmel,hlcdc-display-controller";
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						#address-cells = <1>;
						#size-cells = <0>;
						reg = <0>;
					};
				};

				hlcdc_pwm: hlcdc-pwm {
					compatible = "atmel,hlcdc-pwm";
					pinctrl-names = "default";
					pinctrl-0 = <&pinctrl_lcd_pwm>;
					#pwm-cells = <3>;
				};
			};

			dma1: dma-controller@f0004000 {
				compatible = "atmel,sama5d4-dma";
				reg = <0xf0004000 0x200>;
				interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
				#dma-cells = <1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 50>;
				clock-names = "dma_clk";
			};

			isi: isi@f0008000 {
				compatible = "atmel,at91sam9g45-isi";
				reg = <0xf0008000 0x4000>;
				interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_isi_data_0_7>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
				clock-names = "isi_clk";
				status = "disabled";
				port {
					#address-cells = <1>;
					#size-cells = <0>;
				};
			};

			ramc0: ramc@f0010000 {
				compatible = "atmel,sama5d3-ddramc";
				reg = <0xf0010000 0x200>;
				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>;
				clock-names = "ddrck", "mpddr";
			};

			dma0: dma-controller@f0014000 {
				compatible = "atmel,sama5d4-dma";
				reg = <0xf0014000 0x200>;
				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
				#dma-cells = <1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
				clock-names = "dma_clk";
			};

			pmc: pmc@f0018000 {
				compatible = "atmel,sama5d4-pmc", "syscon";
				reg = <0xf0018000 0x120>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				#clock-cells = <2>;
				clocks = <&clk32k>, <&main_xtal>;
				clock-names = "slow_clk", "main_xtal";
			};

			mmc0: mmc@f8000000 {
				compatible = "atmel,hsmci";
				reg = <0xf8000000 0x600>;
				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(0))>;
				dma-names = "rxtx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
				status = "disabled";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
				clock-names = "mci_clk";
			};

			uart0: serial@f8004000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8004000 0x100>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(22))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(23))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_uart0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
				clock-names = "usart";
				status = "disabled";
			};

			ssc0: ssc@f8008000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xf8008000 0x4000>;
				interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(26))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(27))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
				clock-names = "pclk";
				status = "disabled";
			};

			pwm0: pwm@f800c000 {
				compatible = "atmel,sama5d3-pwm";
				reg = <0xf800c000 0x300>;
				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
				#pwm-cells = <3>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
				status = "disabled";
			};

			spi0: spi@f8010000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xf8010000 0x100>;
				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(10))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(11))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
				clock-names = "spi_clk";
				status = "disabled";
			};

			i2c0: i2c@f8014000 {
				compatible = "atmel,sama5d4-i2c";
				reg = <0xf8014000 0x4000>;
				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(2))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(3))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default", "gpio";
				pinctrl-0 = <&pinctrl_i2c0>;
				pinctrl-1 = <&pinctrl_i2c0_gpio>;
				sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
				scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
				status = "disabled";
			};

			i2c1: i2c@f8018000 {
				compatible = "atmel,sama5d4-i2c";
				reg = <0xf8018000 0x4000>;
				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(4))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(5))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default", "gpio";
				pinctrl-0 = <&pinctrl_i2c1>;
				pinctrl-1 = <&pinctrl_i2c1_gpio>;
				sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
				scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
				status = "disabled";
			};

			tcb0: timer@f801c000 {
				compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0xf801c000 0x100>;
				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>;
				clock-names = "t0_clk", "slow_clk";
			};

			macb0: ethernet@f8020000 {
				compatible = "atmel,sama5d4-gem";
				reg = <0xf8020000 0x100>;
				interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_macb0_rmii>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};

			i2c2: i2c@f8024000 {
				compatible = "atmel,sama5d4-i2c";
				reg = <0xf8024000 0x4000>;
				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(6))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(7))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default", "gpio";
				pinctrl-0 = <&pinctrl_i2c2>;
				pinctrl-1 = <&pinctrl_i2c2_gpio>;
				sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>;
				scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
				status = "disabled";
			};

			sfr: sfr@f8028000 {
				compatible = "atmel,sama5d4-sfr", "syscon";
				reg = <0xf8028000 0x60>;
			};

			usart0: serial@f802c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf802c000 0x100>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(36))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(37))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
				clock-names = "usart";
				status = "disabled";
			};

			usart1: serial@f8030000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8030000 0x100>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(38))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(39))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
				clock-names = "usart";
				status = "disabled";
			};

			mmc1: mmc@fc000000 {
				compatible = "atmel,hsmci";
				reg = <0xfc000000 0x600>;
				interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(1))>;
				dma-names = "rxtx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
				status = "disabled";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
				clock-names = "mci_clk";
			};

			uart1: serial@fc004000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc004000 0x100>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(24))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(25))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_uart1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
				clock-names = "usart";
				status = "disabled";
			};

			usart2: serial@fc008000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc008000 0x100>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(16))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(17))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
				clock-names = "usart";
				status = "disabled";
			};

			usart3: serial@fc00c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc00c000 0x100>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(18))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(19))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart3>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
				clock-names = "usart";
				status = "disabled";
			};

			usart4: serial@fc010000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc010000 0x100>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(20))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(21))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart4>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
				clock-names = "usart";
				status = "disabled";
			};

			ssc1: ssc@fc014000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xfc014000 0x4000>;
				interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(28))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(29))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
				clock-names = "pclk";
				status = "disabled";
			};

			spi1: spi@fc018000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xfc018000 0x100>;
				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(12))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(13))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
				clock-names = "spi_clk";
				status = "disabled";
			};

			spi2: spi@fc01c000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xfc01c000 0x100>;
				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(14))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(15))>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi2>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
				clock-names = "spi_clk";
				status = "disabled";
			};

			tcb1: timer@fc020000 {
				compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0xfc020000 0x100>;
				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>;
				clock-names = "t0_clk", "slow_clk";
			};

			tcb2: timer@fc024000 {
				compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0xfc024000 0x100>;
				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>;
				clock-names = "t0_clk", "slow_clk";
			};

			macb1: ethernet@fc028000 {
				compatible = "atmel,sama5d4-gem";
				reg = <0xfc028000 0x100>;
				interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_macb1_rmii>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};

			trng@fc030000 {
				compatible = "atmel,at91sam9g45-trng";
				reg = <0xfc030000 0x100>;
				interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
			};

			adc0: adc@fc034000 {
				compatible = "atmel,at91sam9x5-adc";
				reg = <0xfc034000 0x100>;
				interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 44>,
					 <&adc_op_clk>;
				clock-names = "adc_clk", "adc_op_clk";
				atmel,adc-channels-used = <0x01f>;
				atmel,adc-startup-time = <40>;
				atmel,adc-use-external-triggers;
				atmel,adc-vref = <3000>;
				atmel,adc-sample-hold-time = <11>;
				atmel,adc-ts-pressure-threshold = <10000>;
				status = "disabled";
			};

			aes: crypto@fc044000 {
				compatible = "atmel,at91sam9g46-aes";
				reg = <0xfc044000 0x100>;
				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(41))>,
				       <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(40))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
				clock-names = "aes_clk";
			};

			tdes: crpyto@fc04c000 {
				compatible = "atmel,at91sam9g46-tdes";
				reg = <0xfc04c000 0x100>;
				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(42))>,
				       <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(43))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
				clock-names = "tdes_clk";
			};

			sha: crypto@fc050000 {
				compatible = "atmel,at91sam9g46-sha";
				reg = <0xfc050000 0x100>;
				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(44))>;
				dma-names = "tx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
				clock-names = "sha_clk";
			};

			hsmc: smc@fc05c000 {
				compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
				reg = <0xfc05c000 0x1000>;
				interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				pmecc: ecc-engine@ffffc070 {
					compatible = "atmel,sama5d4-pmecc";
					reg = <0xfc05c070 0x490>,
					      <0xfc05c500 0x100>;
				};
			};

			reset_controller: reset-controller@fc068600 {
				compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
				reg = <0xfc068600 0x10>;
				clocks = <&clk32k>;
			};

			shutdown_controller: shdwc@fc068610 {
				compatible = "atmel,at91sam9x5-shdwc";
				reg = <0xfc068610 0x10>;
				clocks = <&clk32k>;
			};

			pit: timer@fc068630 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xfc068630 0x10>;
				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
				clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
			};

			watchdog: watchdog@fc068640 {
				compatible = "atmel,sama5d4-wdt";
				reg = <0xfc068640 0x10>;
				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k>;
				status = "disabled";
			};

			clk32k: sckc@fc068650 {
				compatible = "atmel,sama5d4-sckc";
				reg = <0xfc068650 0x4>;
				#clock-cells = <0>;
				clocks = <&slow_xtal>;
			};

			rtc@fc0686b0 {
				compatible = "atmel,sama5d4-rtc";
				reg = <0xfc0686b0 0x30>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k>;
			};

			dbgu: serial@fc069000 {
				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
				reg = <0xfc069000 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_dbgu>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
				clock-names = "usart";
				status = "disabled";
			};

			pinctrl: pinctrl@fc06a000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
				ranges = <0xfc068000 0xfc068000 0x100
					  0xfc06a000 0xfc06a000 0x4000>;
				/* WARNING: revisit as pin spec has changed */
				atmel,mux-mask = <
					/*   A          B          C  */
					0xffffffff 0x3ffcfe7c 0x1c010101	/* pioA */
					0x7fffffff 0xfffccc3a 0x3f00cc3a	/* pioB */
					0xffffffff 0x3ff83fff 0xff00ffff	/* pioC */
					0xb003ff00 0x8002a800 0x00000000	/* pioD */
					0xffffffff 0x7fffffff 0x76fff1bf	/* pioE */
					>;

				pioA: gpio@fc06a000 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfc06a000 0x100>;
					interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
				};

				pioB: gpio@fc06b000 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfc06b000 0x100>;
					interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
				};

				pioC: gpio@fc06c000 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfc06c000 0x100>;
					interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
				};

				pioD: gpio@fc068000 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfc068000 0x100>;
					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
				};

				pioE: gpio@fc06d000 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfc06d000 0x100>;
					interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
				};

				/* pinctrl pin settings */
				adc0 {
					pinctrl_adc0_adtrg: adc0_adtrg {
						atmel,pins =
							<AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* conflicts with USBA_VBUS */
					};
					pinctrl_adc0_ad0: adc0_ad0 {
						atmel,pins =
							<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad1: adc0_ad1 {
						atmel,pins =
							<AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad2: adc0_ad2 {
						atmel,pins =
							<AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad3: adc0_ad3 {
						atmel,pins =
							<AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad4: adc0_ad4 {
						atmel,pins =
							<AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				dbgu {
					pinctrl_dbgu: dbgu-0 {
						atmel,pins =
							<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* conflicts with D14 and TDI */
							 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;		/* conflicts with D15 and TDO */
					};
				};

				ebi {
					pinctrl_ebi_addr: ebi-addr-0 {
						atmel,pins =
							<AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nand_addr: ebi-addr-1 {
						atmel,pins =
							<AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_cs0: ebi-cs0-0 {
						atmel,pins =
							<AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_cs1: ebi-cs1-0 {
						atmel,pins =
							<AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_cs2: ebi-cs2-0 {
						atmel,pins =
							<AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_cs3: ebi-cs3-0 {
						atmel,pins =
							<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
						atmel,pins =
							<AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_data_8_15: ebi-data-msb-0 {
						atmel,pins =
							<AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nandrdy: ebi-nandrdy-0 {
						atmel,pins =
							<AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 {
						atmel,pins =
							<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nwait: ebi-nwait-0 {
						atmel,pins =
							<AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 {
						atmel,pins =
							<AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
						atmel,pins =
							<AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				i2c0 {
					pinctrl_i2c0: i2c0-0 {
						atmel,pins =
							<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_i2c0_gpio: i2c0-gpio {
						atmel,pins =
							<AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
							 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
				};

				i2c1 {
					pinctrl_i2c1: i2c1-0 {
						atmel,pins =
							<AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE	/* TWD1, conflicts with UART0 RX and DIBP */
							 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* TWCK1, conflicts with UART0 TX and DIBN */
					};

					pinctrl_i2c1_gpio: i2c1-gpio {
						atmel,pins =
							<AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
							 AT91_PIOE 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
				};

				i2c2 {
					pinctrl_i2c2: i2c2-0 {
						atmel,pins =
							<AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE	/* TWD2, conflicts with RD0 and PWML1 */
							 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
					};

					pinctrl_i2c2_gpio: i2c2-gpio {
						atmel,pins =
							<AT91_PIOB 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
							 AT91_PIOB 30 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
				};

				isi {
					pinctrl_isi_data_0_7: isi-0-data-0-7 {
						atmel,pins =
							<AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D0 */
							 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D1 */
							 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D2 */
							 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D3 */
							 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D4 */
							 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D5 */
							 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D6 */
							 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE	/* ISI_D7 */
							 AT91_PIOB  1 AT91_PERIPH_C AT91_PINCTRL_NONE	/* ISI_PCK, conflict with G0_RXCK */
							 AT91_PIOB  3 AT91_PERIPH_C AT91_PINCTRL_NONE	/* ISI_VSYNC */
							 AT91_PIOB  4 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* ISI_HSYNC */
					};
					pinctrl_isi_data_8_9: isi-0-data-8-9 {
						atmel,pins =
							<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE	/* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
							 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
					};
					pinctrl_isi_data_10_11: isi-0-data-10-11 {
						atmel,pins =
							<AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE	/* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
							 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
					};
				};

				lcd {
					pinctrl_lcd_base: lcd-base-0 {
						atmel,pins =
							<AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDVSYNC */
							 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDHSYNC */
							 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDDEN */
							 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDPCK */
					};
					pinctrl_lcd_pwm: lcd-pwm-0 {
						atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDPWM */
					};
					pinctrl_lcd_rgb444: lcd-rgb-0 {
						atmel,pins =
							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
							 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
							 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD11 pin */
					};
					pinctrl_lcd_rgb565: lcd-rgb-1 {
						atmel,pins =
							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
							 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
							 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD15 pin */
					};
					pinctrl_lcd_rgb666: lcd-rgb-2 {
						atmel,pins =
							<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
							 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD15 pin */
							 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD18 pin */
							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD19 pin */
							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD20 pin */
							 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD21 pin */
							 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD22 pin */
							 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD23 pin */
					};
					pinctrl_lcd_rgb777: lcd-rgb-3 {
						atmel,pins =
							 /* LCDDAT0 conflicts with TMS */
							<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
							 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
							 /* LCDDAT8 conflicts with TCK */
							 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD15 pin */
							 /* LCDDAT16 conflicts with NTRST */
							 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD17 pin */
							 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD18 pin */
							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD19 pin */
							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD20 pin */
							 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD21 pin */
							 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD22 pin */
							 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD23 pin */
					};
					pinctrl_lcd_rgb888: lcd-rgb-4 {
						atmel,pins =
							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
							 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
							 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD15 pin */
							 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD16 pin */
							 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD17 pin */
							 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD18 pin */
							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD19 pin */
							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD20 pin */
							 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD21 pin */
							 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD22 pin */
							 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD23 pin */
					};
				};

				macb0 {
					pinctrl_macb0_rmii: macb0_rmii-0 {
						atmel,pins =
							<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_TX0 */
							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_TX1 */
							 AT91_PIOB  8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_RX0 */
							 AT91_PIOB  9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_RX1 */
							 AT91_PIOB  6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_RXDV */
							 AT91_PIOB  7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_RXER */
							 AT91_PIOB  2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_TXEN */
							 AT91_PIOB  0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_TXCK */
							 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_MDC */
							 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* G0_MDIO */
							>;
					};
				};

				macb1 {
					pinctrl_macb1_rmii: macb1_rmii-0 {
						atmel,pins =
							<AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_TX0 */
							 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_TX1 */
							 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_RX0 */
							 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_RX1 */
							 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_RXDV */
							 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_RXER */
							 AT91_PIOA  4 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_TXEN */
							 AT91_PIOA  2 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_TXCK */
							 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_MDC */
							 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE	/* G1_MDIO */
							>;
					};
				};

				mmc0 {
					pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
						atmel,pins =
							<AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE	/* MCI0_CK, conflict with PCK1(ISI_MCK) */
							 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_CDA, conflict with NAND_D0 */
							 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA0, conflict with NAND_D1 */
							>;
					};
					pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
						atmel,pins =
							<AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA1, conflict with NAND_D2 */
							 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA2, conflict with NAND_D3 */
							 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA3, conflict with NAND_D4 */
							>;
					};
					pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
						atmel,pins =
							<AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA4, conflict with NAND_D5 */
							 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA5, conflict with NAND_D6 */
							 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA6, conflict with NAND_D7 */
							 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* MCI0_DA7, conflict with NAND_OE */
							>;
					};
				};

				mmc1 {
					pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
						atmel,pins =
							<AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE		/* MCI1_CK */
							 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* MCI1_CDA */
							 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* MCI1_DA0 */
							>;
					};
					pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
						atmel,pins =
							<AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* MCI1_DA1 */
							 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* MCI1_DA2 */
							 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* MCI1_DA3 */
							>;
					};
				};

				nand0 {
					pinctrl_nand: nand-0 {
						atmel,pins =
							<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC13 periph A Read Enable */
							 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC14 periph A Write Enable */

							 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PC17 ALE */
							 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PC18 CLE */

							 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PC15 NCS3/Chip Enable */
							 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PC16 NANDRDY */
							 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC5 Data bit 0 */
							 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC6 Data bit 1 */
							 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC7 Data bit 2 */
							 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC8 Data bit 3 */
							 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC9 Data bit 4 */
							 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC10 Data bit 5 */
							 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PC11 periph A Data bit 6 */
							 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PC12 periph A Data bit 7 */
					};
				};

				spi0 {
					pinctrl_spi0: spi0-0 {
						atmel,pins =
							<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* SPI0_MISO */
							 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* SPI0_MOSI */
							 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* SPI0_SPCK */
							>;
					};
				};

				ssc0 {
					pinctrl_ssc0_tx: ssc0_tx {
						atmel,pins =
							<AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* TK0 */
							 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE	/* TF0 */
							 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* TD0 */
					};

					pinctrl_ssc0_rx: ssc0_rx {
						atmel,pins =
							<AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE	/* RK0 */
							 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE	/* RF0 */
							 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* RD0 */
					};
				};

				ssc1 {
					pinctrl_ssc1_tx: ssc1_tx {
						atmel,pins =
							<AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE	/* TK1 */
							 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE	/* TF1 */
							 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* TD1 */
					};

					pinctrl_ssc1_rx: ssc1_rx {
						atmel,pins =
							<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE	/* RK1 */
							 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* RF1 */
							 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* RD1 */
					};
				};

				spi1 {
					pinctrl_spi1: spi1-0 {
						atmel,pins =
							<AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* SPI1_MISO */
							 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* SPI1_MOSI */
							 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* SPI1_SPCK */
							>;
					};
				};

				spi2 {
					pinctrl_spi2: spi2-0 {
						atmel,pins =
							<AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE	/* SPI2_MISO conflicts with RTS0 */
							 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE	/* SPI2_MOSI conflicts with TXD0 */
							 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE	/* SPI2_SPCK conflicts with RTS1 */
							>;
					};
				};

				uart0 {
					pinctrl_uart0: uart0-0 {
						atmel,pins =
							<AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* RXD */
							 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE		/* TXD */
							>;
					};
				};

				uart1 {
					pinctrl_uart1: uart1-0 {
						atmel,pins =
							<AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP	/* RXD */
							 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE		/* TXD */
							>;
					};
				};

				usart0 {
					pinctrl_usart0: usart0-0 {
						atmel,pins =
							<AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* RXD */
							 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE		/* TXD */
							>;
					};
					pinctrl_usart0_rts: usart0_rts-0 {
						atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_usart0_cts: usart0_cts-0 {
						atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				usart1 {
					pinctrl_usart1: usart1-0 {
						atmel,pins =
							<AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* RXD */
							 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE		/* TXD */
							>;
					};
					pinctrl_usart1_rts: usart1_rts-0 {
						atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_usart1_cts: usart1_cts-0 {
						atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				usart2 {
					pinctrl_usart2: usart2-0 {
						atmel,pins =
							<AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP		/* RXD - conflicts with G0_CRS, ISI_HSYNC */
							 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE		/* TXD - conflicts with G0_COL, PCK2 */
							>;
					};
					pinctrl_usart2_rts: usart2_rts-0 {
						atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with G0_RX3, PWMH1 */
					};
					pinctrl_usart2_cts: usart2_cts-0 {
						atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with G0_TXER, ISI_VSYNC */
					};
				};

				usart3 {
					pinctrl_usart3: usart3-0 {
						atmel,pins =
							<AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* RXD */
							 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE		/* TXD */
							>;
					};
				};

				usart4 {
					pinctrl_usart4: usart4-0 {
						atmel,pins =
							<AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* RXD */
							 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE		/* TXD */
							>;
					};
					pinctrl_usart4_rts: usart4_rts-0 {
						atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* conflicts with NWAIT, A19 */
					};
					pinctrl_usart4_cts: usart4_cts-0 {
						atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* conflicts with A0/NBS0, MCI0_CDB */
					};
				};
			};

			aic: interrupt-controller@fc06e000 {
				#interrupt-cells = <3>;
				compatible = "atmel,sama5d4-aic";
				interrupt-controller;
				reg = <0xfc06e000 0x200>;
				atmel,external-irqs = <56>;
			};
		};
	};
};


code:
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
#define PINMUX_PIN(no, func, ioset) \
(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20))

#define PIN_PA0				0
#define PIN_PA0__GPIO			PINMUX_PIN(PIN_PA0, 0, 0)
#define PIN_PA0__SDMMC0_CK		PINMUX_PIN(PIN_PA0, 1, 1)
#define PIN_PA0__FLEXCOM0_IO0		PINMUX_PIN(PIN_PA0, 2, 1)
#define PIN_PA0__CANTX3			PINMUX_PIN(PIN_PA0, 3, 1)
#define PIN_PA0__PWML0			PINMUX_PIN(PIN_PA0, 5, 2)
#define PIN_PA1				1
#define PIN_PA1__GPIO			PINMUX_PIN(PIN_PA1, 0, 0)
#define PIN_PA1__SDMMC0_CMD		PINMUX_PIN(PIN_PA1, 1, 1)
#define PIN_PA1__FLEXCOM0_IO1		PINMUX_PIN(PIN_PA1, 2, 1)
#define PIN_PA1__CANRX3			PINMUX_PIN(PIN_PA1, 3, 1)
#define PIN_PA1__D14			PINMUX_PIN(PIN_PA1, 4, 1)
#define PIN_PA1__PWMH0			PINMUX_PIN(PIN_PA1, 5, 3)
#define PIN_PA2				2
#define PIN_PA2__GPIO			PINMUX_PIN(PIN_PA2, 0, 0)
#define PIN_PA2__SDMMC0_RSTN		PINMUX_PIN(PIN_PA2, 1, 1)
#define PIN_PA2__FLEXCOM0_IO2		PINMUX_PIN(PIN_PA2, 2, 1)
#define PIN_PA2__PDMC1_CLK		PINMUX_PIN(PIN_PA2, 3, 1)
#define PIN_PA2__D15			PINMUX_PIN(PIN_PA2, 4, 1)
#define PIN_PA2__PWMH1			PINMUX_PIN(PIN_PA2, 5, 3)
#define PIN_PA2__FLEXCOM1_IO0		PINMUX_PIN(PIN_PA2, 6, 3)
#define PIN_PA3				3
#define PIN_PA3__GPIO			PINMUX_PIN(PIN_PA3, 0, 0)
#define PIN_PA3__SDMMC0_DAT0		PINMUX_PIN(PIN_PA3, 1, 1)
#define PIN_PA3__FLEXCOM0_IO3		PINMUX_PIN(PIN_PA3, 2, 1)
#define PIN_PA3__PDMC1_DS0		PINMUX_PIN(PIN_PA3, 3, 1)
#define PIN_PA3__NWR1_NBS1		PINMUX_PIN(PIN_PA3, 4, 1)
#define PIN_PA3__PWML3			PINMUX_PIN(PIN_PA3, 5, 3)
#define PIN_PA3__FLEXCOM1_IO1		PINMUX_PIN(PIN_PA3, 6, 3)
#define PIN_PA4				4
#define PIN_PA4__GPIO			PINMUX_PIN(PIN_PA4, 0, 0)
#define PIN_PA4__SDMMC0_DAT1		PINMUX_PIN(PIN_PA4, 1, 1)
#define PIN_PA4__FLEXCOM0_IO4		PINMUX_PIN(PIN_PA4, 2, 1)
#define PIN_PA4__PDMC1_DS1		PINMUX_PIN(PIN_PA4, 3, 1)
#define PIN_PA4__NCS2			PINMUX_PIN(PIN_PA4, 4, 1)
#define PIN_PA4__PWMH3			PINMUX_PIN(PIN_PA4, 5, 3)
#define PIN_PA4__FLEXCOM2_IO0		PINMUX_PIN(PIN_PA4, 6, 3)
#define PIN_PA5				5
#define PIN_PA5__GPIO			PINMUX_PIN(PIN_PA5, 0, 0)
#define PIN_PA5__SDMMC0_DAT2		PINMUX_PIN(PIN_PA5, 1, 1)
#define PIN_PA5__FLEXCOM1_IO0		PINMUX_PIN(PIN_PA5, 2, 1)
#define PIN_PA5__CANTX2			PINMUX_PIN(PIN_PA5, 3, 1)
#define PIN_PA5__A23			PINMUX_PIN(PIN_PA5, 4, 1)
#define PIN_PA5__PWMEXTRG0		PINMUX_PIN(PIN_PA5, 5, 3)
#define PIN_PA5__FLEXCOM2_IO1		PINMUX_PIN(PIN_PA5, 6, 3)
#define PIN_PA6				6
#define PIN_PA6__GPIO			PINMUX_PIN(PIN_PA6, 0, 0)
#define PIN_PA6__SDMMC0_DAT3		PINMUX_PIN(PIN_PA6, 1, 1)
#define PIN_PA6__FLEXCOM1_IO1		PINMUX_PIN(PIN_PA6, 2, 1)
#define PIN_PA6__CANRX2			PINMUX_PIN(PIN_PA6, 3, 1)
#define PIN_PA6__A24			PINMUX_PIN(PIN_PA6, 4, 1)
#define PIN_PA6__PWMEXTRG1		PINMUX_PIN(PIN_PA6, 5, 3)
#define PIN_PA6__FLEXCOM3_IO0		PINMUX_PIN(PIN_PA6, 6, 3)
#define PIN_PA7				7
#define PIN_PA7__GPIO			PINMUX_PIN(PIN_PA7, 0, 0)
#define PIN_PA7__SDMMC0_DAT4		PINMUX_PIN(PIN_PA7, 1, 1)
#define PIN_PA7__FLEXCOM2_IO0		PINMUX_PIN(PIN_PA7, 2, 1)
#define PIN_PA7__CANTX1			PINMUX_PIN(PIN_PA7, 3, 1)
#define PIN_PA7__NWAIT			PINMUX_PIN(PIN_PA7, 4, 1)
#define PIN_PA7__PWMFI0			PINMUX_PIN(PIN_PA7, 5, 3)
#define PIN_PA7__FLEXCOM3_IO1		PINMUX_PIN(PIN_PA7, 6, 3)
#define PIN_PA8				8
#define PIN_PA8__GPIO			PINMUX_PIN(PIN_PA8, 0, 0)
#define PIN_PA8__SDMMC0_DAT5		PINMUX_PIN(PIN_PA8, 1, 1)
#define PIN_PA8__FLEXCOM2_IO1		PINMUX_PIN(PIN_PA8, 2, 1)
#define PIN_PA8__CANRX1			PINMUX_PIN(PIN_PA8, 3, 1)
#define PIN_PA8__NCS0			PINMUX_PIN(PIN_PA8, 4, 1)
#define PIN_PA8__PWMIF1			PINMUX_PIN(PIN_PA8, 5, 3)
#define PIN_PA8__FLEXCOM4_IO0		PINMUX_PIN(PIN_PA8, 6, 3)
#define PIN_PA9				9
#define PIN_PA9__GPIO			PINMUX_PIN(PIN_PA9, 0, 0)
#define PIN_PA9__SDMMC0_DAT6		PINMUX_PIN(PIN_PA9, 1, 1)
#define PIN_PA9__FLEXCOM2_IO2		PINMUX_PIN(PIN_PA9, 2, 1)
#define PIN_PA9__CANTX0			PINMUX_PIN(PIN_PA9, 3, 1)
#define PIN_PA9__SMCK			PINMUX_PIN(PIN_PA9, 4, 1)
#define PIN_PA9__SPDIF_RX		PINMUX_PIN(PIN_PA9, 5, 1)
#define PIN_PA9__FLEXCOM4_IO1		PINMUX_PIN(PIN_PA9, 6, 3)
#define PIN_PA10			10
#define PIN_PA10__GPIO			PINMUX_PIN(PIN_PA10, 0, 0)
#define PIN_PA10__SDMMC0_DAT7		PINMUX_PIN(PIN_PA10, 1, 1)
#define PIN_PA10__FLEXCOM2_IO3		PINMUX_PIN(PIN_PA10, 2, 1)
#define PIN_PA10__CANRX0		PINMUX_PIN(PIN_PA10, 3, 1)
#define PIN_PA10__NCS1			PINMUX_PIN(PIN_PA10, 4, 1)
#define PIN_PA10__SPDIF_TX		PINMUX_PIN(PIN_PA10, 5, 1)
#define PIN_PA10__FLEXCOM5_IO0		PINMUX_PIN(PIN_PA10, 6, 3)
#define PIN_PA11			11
#define PIN_PA11__GPIO			PINMUX_PIN(PIN_PA11, 0, 0)
#define PIN_PA11__SDMMC0_DS		PINMUX_PIN(PIN_PA11, 1, 1)
#define PIN_PA11__FLEXCOM2_IO4		PINMUX_PIN(PIN_PA11, 2, 1)
#define PIN_PA11__A0_NBS0		PINMUX_PIN(PIN_PA11, 4, 1)
#define PIN_PA11__TIOA0			PINMUX_PIN(PIN_PA11, 5, 1)
#define PIN_PA11__FLEXCOM5_IO1		PINMUX_PIN(PIN_PA11, 6, 3)
#define PIN_PA12			12
#define PIN_PA12__GPIO			PINMUX_PIN(PIN_PA12, 0, 0)
#define PIN_PA12__SDMMC0_WP		PINMUX_PIN(PIN_PA12, 1, 1)
#define PIN_PA12__FLEXCOM1_IO3		PINMUX_PIN(PIN_PA12, 2, 1)
#define PIN_PA12__FLEXCOM3_IO5		PINMUX_PIN(PIN_PA12, 4, 1)
#define PIN_PA12__PWML2			PINMUX_PIN(PIN_PA12, 5, 3)
#define PIN_PA12__FLEXCOM6_IO0		PINMUX_PIN(PIN_PA12, 6, 3)
#define PIN_PA13			13
#define PIN_PA13__GPIO			PINMUX_PIN(PIN_PA13, 0, 0)
#define PIN_PA13__SDMMC0_1V8SEL		PINMUX_PIN(PIN_PA13, 1, 1)
#define PIN_PA13__FLEXCOM1_IO2		PINMUX_PIN(PIN_PA13, 2, 1)
#define PIN_PA13__FLEXCOM3_IO6		PINMUX_PIN(PIN_PA13, 4, 1)
#define PIN_PA13__PWMH2			PINMUX_PIN(PIN_PA13, 5, 3)
#define PIN_PA13__FLEXCOM6_IO1		PINMUX_PIN(PIN_PA13, 6, 3)
#define PIN_PA14			14
#define PIN_PA14__GPIO			PINMUX_PIN(PIN_PA14, 0, 0)
#define PIN_PA14__SDMMC0_CD		PINMUX_PIN(PIN_PA14, 1, 1)
#define PIN_PA14__FLEXCOM1_IO4		PINMUX_PIN(PIN_PA14, 2, 1)
#define PIN_PA14__A25			PINMUX_PIN(PIN_PA14, 4, 1)
#define PIN_PA14__PWML1			PINMUX_PIN(PIN_PA14, 5, 3)
#define PIN_PA15			15
#define PIN_PA15__GPIO			PINMUX_PIN(PIN_PA15, 0, 0)
#define PIN_PA15__G0_TXEN		PINMUX_PIN(PIN_PA15, 1, 1)
#define PIN_PA15__FLEXCOM3_IO0		PINMUX_PIN(PIN_PA15, 2, 1)
#define PIN_PA15__ISC_MCK		PINMUX_PIN(PIN_PA15, 3, 1)
#define PIN_PA15__A1			PINMUX_PIN(PIN_PA15, 4, 1)
#define PIN_PA15__TIOB0			PINMUX_PIN(PIN_PA15, 5, 1)
#define PIN_PA16			16
#define PIN_PA16__GPIO			PINMUX_PIN(PIN_PA16, 0, 0)
#define PIN_PA16__G0_TX0		PINMUX_PIN(PIN_PA16, 1, 1)
#define PIN_PA16__FLEXCOM3_IO1		PINMUX_PIN(PIN_PA16, 2, 1)
#define PIN_PA16__ISC_D0		PINMUX_PIN(PIN_PA16, 3, 1)
#define PIN_PA16__A2			PINMUX_PIN(PIN_PA16, 4, 1)
#define PIN_PA16__TCLK0			PINMUX_PIN(PIN_PA16, 5, 1)
#define PIN_PA17			17
#define PIN_PA17__GPIO			PINMUX_PIN(PIN_PA17, 0, 0)
#define PIN_PA17__G0_TX1		PINMUX_PIN(PIN_PA17, 1, 1)
#define PIN_PA17__FLEXCOM3_IO2		PINMUX_PIN(PIN_PA17, 2, 1)
#define PIN_PA17__ISC_D1		PINMUX_PIN(PIN_PA17, 3, 1)
#define PIN_PA17__A3			PINMUX_PIN(PIN_PA17, 4, 1)
#define PIN_PA17__TIOA1			PINMUX_PIN(PIN_PA17, 5, 1)
#define PIN_PA18			18
#define PIN_PA18__GPIO			PINMUX_PIN(PIN_PA18, 0, 0)
#define PIN_PA18__G0_RXDV		PINMUX_PIN(PIN_PA18, 1, 1)
#define PIN_PA18__FLEXCOM3_IO3		PINMUX_PIN(PIN_PA18, 2, 1)
#define PIN_PA18__ISC_D2		PINMUX_PIN(PIN_PA18, 3, 1)
#define PIN_PA18__A4			PINMUX_PIN(PIN_PA18, 4, 1)
#define PIN_PA18__TIOB1			PINMUX_PIN(PIN_PA18, 5, 1)
#define PIN_PA19			19
#define PIN_PA19__GPIO			PINMUX_PIN(PIN_PA19, 0, 0)
#define PIN_PA19__G0_RX0		PINMUX_PIN(PIN_PA19, 1, 1)
#define PIN_PA19__FLEXCOM3_IO4		PINMUX_PIN(PIN_PA19, 2, 1)
#define PIN_PA19__ISC_D3		PINMUX_PIN(PIN_PA19, 3, 1)
#define PIN_PA19__A5			PINMUX_PIN(PIN_PA19, 4, 1)
#define PIN_PA19__TCLK1			PINMUX_PIN(PIN_PA19, 5, 1)
#define PIN_PA20			20
#define PIN_PA20__GPIO			PINMUX_PIN(PIN_PA20, 0, 0)
#define PIN_PA20__G0_RX1		PINMUX_PIN(PIN_PA20, 1, 1)
#define PIN_PA20__FLEXCOM4_IO0		PINMUX_PIN(PIN_PA20, 2, 1)
#define PIN_PA20__ISC_D4		PINMUX_PIN(PIN_PA20, 3, 1)
#define PIN_PA20__A6			PINMUX_PIN(PIN_PA20, 4, 1)
#define PIN_PA20__TIOA2			PINMUX_PIN(PIN_PA20, 5, 1)
#define PIN_PA21			21
#define PIN_PA21__GPIO			PINMUX_PIN(PIN_PA21, 0, 0)
#define PIN_PA21__G0_RXER		PINMUX_PIN(PIN_PA21, 1, 1)
#define PIN_PA21__FLEXCOM4_IO1		PINMUX_PIN(PIN_PA21, 2, 1)
#define PIN_PA21__ISC_D5		PINMUX_PIN(PIN_PA21, 3, 1)
#define PIN_PA21__A7			PINMUX_PIN(PIN_PA21, 4, 1)
#define PIN_PA21__TIOB2			PINMUX_PIN(PIN_PA21, 5, 1)
#define PIN_PA22			22
#define PIN_PA22__GPIO			PINMUX_PIN(PIN_PA22, 0, 0)
#define PIN_PA22__G0_MDC		PINMUX_PIN(PIN_PA22, 1, 1)
#define PIN_PA22__FLEXCOM4_IO2		PINMUX_PIN(PIN_PA22, 2, 1)
#define PIN_PA22__ISC_D6		PINMUX_PIN(PIN_PA22, 3, 1)
#define PIN_PA22__A8			PINMUX_PIN(PIN_PA22, 4, 1)
#define PIN_PA22__TCLK2			PINMUX_PIN(PIN_PA22, 5, 1)
#define PIN_PA23			23
#define PIN_PA23__GPIO			PINMUX_PIN(PIN_PA23, 0, 0)
#define PIN_PA23__G0_MDIO		PINMUX_PIN(PIN_PA23, 1, 1)
#define PIN_PA23__FLEXCOM4_IO3		PINMUX_PIN(PIN_PA23, 2, 1)
#define PIN_PA23__ISC_D7		PINMUX_PIN(PIN_PA23, 3, 1)
#define PIN_PA23__A9			PINMUX_PIN(PIN_PA23, 4, 1)
#define PIN_PA24			24
#define PIN_PA24__GPIO			PINMUX_PIN(PIN_PA24, 0, 0)
#define PIN_PA24__G0_TXCK		PINMUX_PIN(PIN_PA24, 1, 1)
#define PIN_PA24__FLEXCOM4_IO4		PINMUX_PIN(PIN_PA24, 2, 1)
#define PIN_PA24__ISC_HSYNC		PINMUX_PIN(PIN_PA24, 3, 1)
#define PIN_PA24__A10			PINMUX_PIN(PIN_PA24, 4, 1)
#define PIN_PA24__FLEXCOM0_IO5		PINMUX_PIN(PIN_PA24, 5, 1)
#define PIN_PA25			25
#define PIN_PA25__GPIO			PINMUX_PIN(PIN_PA25, 0, 0)
#define PIN_PA25__G0_125CK		PINMUX_PIN(PIN_PA25, 1, 1)
#define PIN_PA25__FLEXCOM5_IO4		PINMUX_PIN(PIN_PA25, 2, 1)
#define PIN_PA25__ISC_VSYNC		PINMUX_PIN(PIN_PA25, 3, 1)
#define PIN_PA25__A11			PINMUX_PIN(PIN_PA25, 4, 1)
#define PIN_PA25__FLEXCOM0_IO6		PINMUX_PIN(PIN_PA25, 5, 1)
#define PIN_PA25__FLEXCOM7_IO0		PINMUX_PIN(PIN_PA25, 6, 3)
#define PIN_PA26			26
#define PIN_PA26__GPIO			PINMUX_PIN(PIN_PA26, 0, 0)
#define PIN_PA26__G0_TX2		PINMUX_PIN(PIN_PA26, 1, 1)
#define PIN_PA26__FLEXCOM5_IO2		PINMUX_PIN(PIN_PA26, 2, 1)
#define PIN_PA26__ISC_FIELD		PINMUX_PIN(PIN_PA26, 3, 1)
#define PIN_PA26__A12			PINMUX_PIN(PIN_PA26, 4, 1)
#define PIN_PA26__TF0			PINMUX_PIN(PIN_PA26, 5, 1)
#define PIN_PA26__FLEXCOM7_IO1		PINMUX_PIN(PIN_PA26, 6, 3)
#define PIN_PA27			27
#define PIN_PA27__GPIO			PINMUX_PIN(PIN_PA27, 0, 0)
#define PIN_PA27__G0_TX3		PINMUX_PIN(PIN_PA27, 1, 1)
#define PIN_PA27__FLEXCOM5_IO3		PINMUX_PIN(PIN_PA27, 2, 1)
#define PIN_PA27__ISC_PCK		PINMUX_PIN(PIN_PA27, 3, 1)
#define PIN_PA27__A13			PINMUX_PIN(PIN_PA27, 4, 1)
#define PIN_PA27__TK0			PINMUX_PIN(PIN_PA27, 5, 1)
#define PIN_PA27__FLEXCOM8_IO0		PINMUX_PIN(PIN_PA27, 6, 3)
#define PIN_PA28			28
#define PIN_PA28__GPIO			PINMUX_PIN(PIN_PA28, 0, 0)
#define PIN_PA28__G0_RX2		PINMUX_PIN(PIN_PA28, 1, 1)
#define PIN_PA28__FLEXCOM5_IO0		PINMUX_PIN(PIN_PA28, 2, 1)
#define PIN_PA28__ISC_D8		PINMUX_PIN(PIN_PA28, 3, 1)
#define PIN_PA28__A14			PINMUX_PIN(PIN_PA28, 4, 1)
#define PIN_PA28__RD0			PINMUX_PIN(PIN_PA28, 5, 1)
#define PIN_PA28__FLEXCOM8_IO1		PINMUX_PIN(PIN_PA28, 6, 3)
#define PIN_PA29			29
#define PIN_PA29__GPIO			PINMUX_PIN(PIN_PA29, 0, 0)
#define PIN_PA29__G0_RX3		PINMUX_PIN(PIN_PA29, 1, 1)
#define PIN_PA29__FLEXCOM5_IO1		PINMUX_PIN(PIN_PA29, 2, 1)
#define PIN_PA29__ISC_D9		PINMUX_PIN(PIN_PA29, 3, 1)
#define PIN_PA29__A15			PINMUX_PIN(PIN_PA29, 4, 1)
#define PIN_PA29__RF0			PINMUX_PIN(PIN_PA29, 5, 1)
#define PIN_PA29__FLEXCOM9_IO0		PINMUX_PIN(PIN_PA29, 6, 3)
#define PIN_PA30			30
#define PIN_PA30__GPIO			PINMUX_PIN(PIN_PA30, 0, 0)
#define PIN_PA30__G0_RXCK		PINMUX_PIN(PIN_PA30, 1, 1)
#define PIN_PA30__FLEXCOM6_IO4		PINMUX_PIN(PIN_PA30, 2, 1)
#define PIN_PA30__ISC_D10		PINMUX_PIN(PIN_PA30, 3, 1)
#define PIN_PA30__A16			PINMUX_PIN(PIN_PA30, 4, 1)
#define PIN_PA30__RK0			PINMUX_PIN(PIN_PA30, 5, 1)
#define PIN_PA30__FLEXCOM9_IO1		PINMUX_PIN(PIN_PA30, 6, 3)
#define PIN_PA31			31
#define PIN_PA31__GPIO			PINMUX_PIN(PIN_PA31, 0, 0)
#define PIN_PA31__G0_TXER		PINMUX_PIN(PIN_PA31, 1, 1)
#define PIN_PA31__FLEXCOM6_IO2		PINMUX_PIN(PIN_PA31, 2, 1)
#define PIN_PA31__ISC_D11		PINMUX_PIN(PIN_PA31, 3, 1)
#define PIN_PA31__A17			PINMUX_PIN(PIN_PA31, 4, 1)
#define PIN_PA31__TD0			PINMUX_PIN(PIN_PA31, 5, 1)
#define PIN_PA31__FLEXCOM10_IO0		PINMUX_PIN(PIN_PA31, 6, 3)
#define PIN_PB0				32
#define PIN_PB0__GPIO			PINMUX_PIN(PIN_PB0, 0, 0)
#define PIN_PB0__G0_COL			PINMUX_PIN(PIN_PB0, 1, 1)
#define PIN_PB0__FLEXCOM6_IO3		PINMUX_PIN(PIN_PB0, 2, 2)
#define PIN_PB0__EXT_IRQ0		PINMUX_PIN(PIN_PB0, 3, 1)
#define PIN_PB0__A18			PINMUX_PIN(PIN_PB0, 4, 1)
#define PIN_PB0__SPDIF_RX		PINMUX_PIN(PIN_PB0, 5, 2)
#define PIN_PB0__FLEXCOM10_IO1		PINMUX_PIN(PIN_PB0, 6, 3)
#define PIN_PB1				33
#define PIN_PB1__GPIO			PINMUX_PIN(PIN_PB1, 0, 0)
#define PIN_PB1__G0_CRS			PINMUX_PIN(PIN_PB1, 1, 1)
#define PIN_PB1__FLEXCOM6_IO1		PINMUX_PIN(PIN_PB1, 2, 2)
#define PIN_PB1__EXT_IRQ1		PINMUX_PIN(PIN_PB1, 3, 1)
#define PIN_PB1__A19			PINMUX_PIN(PIN_PB1, 4, 1)
#define PIN_PB1__SPDIF_TX		PINMUX_PIN(PIN_PB1, 5, 2)
#define PIN_PB1__FLEXCOM11_IO0		PINMUX_PIN(PIN_PB1, 6, 3)
#define PIN_PB2				34
#define PIN_PB2__GPIO			PINMUX_PIN(PIN_PB2, 0, 0)
#define PIN_PB2__G0_TSUCOMP		PINMUX_PIN(PIN_PB2, 1, 1)
#define PIN_PB2__FLEXCOM6_IO0		PINMUX_PIN(PIN_PB2, 2, 1)
#define PIN_PB2__ADTRG			PINMUX_PIN(PIN_PB2, 3, 1)
#define PIN_PB2__A20			PINMUX_PIN(PIN_PB2, 4, 1)
#define PIN_PB2__FLEXCOM11_IO1		PINMUX_PIN(PIN_PB2, 6, 3)
#define PIN_PB3				35
#define PIN_PB3__GPIO			PINMUX_PIN(PIN_PB3, 0, 0)
#define PIN_PB3__RF1			PINMUX_PIN(PIN_PB3, 1, 1)
#define PIN_PB3__FLEXCOM11_IO0		PINMUX_PIN(PIN_PB3, 2, 1)
#define PIN_PB3__PCK2			PINMUX_PIN(PIN_PB3, 3, 2)
#define PIN_PB3__D8			PINMUX_PIN(PIN_PB3, 4, 1)
#define PIN_PB4				36
#define PIN_PB4__GPIO			PINMUX_PIN(PIN_PB4, 0, 0)
#define PIN_PB4__TF1			PINMUX_PIN(PIN_PB4, 1, 1)
#define PIN_PB4__FLEXCOM11_IO1		PINMUX_PIN(PIN_PB4, 2, 1)
#define PIN_PB4__PCK3			PINMUX_PIN(PIN_PB4, 3, 2)
#define PIN_PB4__D9			PINMUX_PIN(PIN_PB4, 4, 1)
#define PIN_PB5				37
#define PIN_PB5__GPIO			PINMUX_PIN(PIN_PB5, 0, 0)
#define PIN_PB5__TK1			PINMUX_PIN(PIN_PB5, 1, 1)
#define PIN_PB5__FLEXCOM11_IO2		PINMUX_PIN(PIN_PB5, 2, 1)
#define PIN_PB5__PCK4			PINMUX_PIN(PIN_PB5, 3, 2)
#define PIN_PB5__D10			PINMUX_PIN(PIN_PB5, 4, 1)
#define PIN_PB6				38
#define PIN_PB6__GPIO			PINMUX_PIN(PIN_PB6, 0, 0)
#define PIN_PB6__RK1			PINMUX_PIN(PIN_PB6, 1, 1)
#define PIN_PB6__FLEXCOM11_IO3		PINMUX_PIN(PIN_PB6, 2, 1)
#define PIN_PB6__PCK5			PINMUX_PIN(PIN_PB6, 3, 2)
#define PIN_PB6__D11			PINMUX_PIN(PIN_PB6, 4, 1)
#define PIN_PB7				39
#define PIN_PB7__GPIO			PINMUX_PIN(PIN_PB7, 0, 0)
#define PIN_PB7__TD1			PINMUX_PIN(PIN_PB7, 1, 1)
#define PIN_PB7__FLEXCOM11_IO4		PINMUX_PIN(PIN_PB7, 2, 1)
#define PIN_PB7__FLEXCOM3_IO5		PINMUX_PIN(PIN_PB7, 3, 2)
#define PIN_PB7__D12			PINMUX_PIN(PIN_PB7, 4, 1)
#define PIN_PB8				40
#define PIN_PB8__GPIO			PINMUX_PIN(PIN_PB8, 0, 0)
#define PIN_PB8__RD1			PINMUX_PIN(PIN_PB8, 1, 1)
#define PIN_PB8__FLEXCOM8_IO0		PINMUX_PIN(PIN_PB8, 2, 1)
#define PIN_PB8__FLEXCOM3_IO6		PINMUX_PIN(PIN_PB8, 3, 2)
#define PIN_PB8__D13			PINMUX_PIN(PIN_PB8, 4, 1)
#define PIN_PB9				41
#define PIN_PB9__GPIO			PINMUX_PIN(PIN_PB9, 0, 0)
#define PIN_PB9__QSPI0_IO3		PINMUX_PIN(PIN_PB9, 1, 1)
#define PIN_PB9__FLEXCOM8_IO1		PINMUX_PIN(PIN_PB9, 2, 1)
#define PIN_PB9__PDMC0_CLK		PINMUX_PIN(PIN_PB9, 3, 1)
#define PIN_PB9__NCS3_NANDCS		PINMUX_PIN(PIN_PB9, 4, 1)
#define PIN_PB9__PWML0			PINMUX_PIN(PIN_PB9, 5, 2)
#define PIN_PB10			42
#define PIN_PB10__GPIO			PINMUX_PIN(PIN_PB10, 0, 0)
#define PIN_PB10__QSPI0_IO2		PINMUX_PIN(PIN_PB10, 1, 1)
#define PIN_PB10__FLEXCOM8_IO2		PINMUX_PIN(PIN_PB10, 2, 1)
#define PIN_PB10__PDMC0_DS0		PINMUX_PIN(PIN_PB10, 3, 1)
#define PIN_PB10__NWE_NWR0_NANDWE	PINMUX_PIN(PIN_PB10, 4, 1)
#define PIN_PB10__PWMH0			PINMUX_PIN(PIN_PB10, 5, 2)
#define PIN_PB11			43
#define PIN_PB11__GPIO			PINMUX_PIN(PIN_PB11, 0, 0)
#define PIN_PB11__QSPI0_IO1		PINMUX_PIN(PIN_PB11, 1, 1)
#define PIN_PB11__FLEXCOM8_IO3		PINMUX_PIN(PIN_PB11, 2, 1)
#define PIN_PB11__PDMC0_DS1		PINMUX_PIN(PIN_PB11, 3, 1)
#define PIN_PB11__NRD_NANDOE		PINMUX_PIN(PIN_PB11, 4, 1)
#define PIN_PB11__PWML1			PINMUX_PIN(PIN_PB11, 5, 2)
#define PIN_PB12			44
#define PIN_PB12__GPIO			PINMUX_PIN(PIN_PB12, 0, 0)
#define PIN_PB12__QSPI0_IO0		PINMUX_PIN(PIN_PB12, 1, 1)
#define PIN_PB12__FLEXCOM8_IO4		PINMUX_PIN(PIN_PB12, 2, 1)
#define PIN_PB12__FLEXCOM6_IO5		PINMUX_PIN(PIN_PB12, 3, 1)
#define PIN_PB12__A21_NANDALE		PINMUX_PIN(PIN_PB12, 4, 1)
#define PIN_PB12__PWMH1			PINMUX_PIN(PIN_PB12, 5, 2)
#define PIN_PB13			45
#define PIN_PB13__GPIO			PINMUX_PIN(PIN_PB13, 0, 0)
#define PIN_PB13__QSPI0_CS		PINMUX_PIN(PIN_PB13, 1, 1)
#define PIN_PB13__FLEXCOM9_IO0		PINMUX_PIN(PIN_PB13, 2, 1)
#define PIN_PB13__FLEXCOM6_IO6		PINMUX_PIN(PIN_PB13, 3, 1)
#define PIN_PB13__A22_NANDCLE		PINMUX_PIN(PIN_PB13, 4, 1)
#define PIN_PB13__PWML2			PINMUX_PIN(PIN_PB13, 5, 2)
#define PIN_PB14			46
#define PIN_PB14__GPIO			PINMUX_PIN(PIN_PB14, 0, 0)
#define PIN_PB14__QSPI0_SCK		PINMUX_PIN(PIN_PB14, 1, 1)
#define PIN_PB14__FLEXCOM9_IO1		PINMUX_PIN(PIN_PB14, 2, 1)
#define PIN_PB14__D0			PINMUX_PIN(PIN_PB14, 4, 1)
#define PIN_PB14__PWMH2			PINMUX_PIN(PIN_PB14, 5, 2)
#define PIN_PB15			47
#define PIN_PB15__GPIO			PINMUX_PIN(PIN_PB15, 0, 0)
#define PIN_PB15__QSPI0_SCKN		PINMUX_PIN(PIN_PB15, 1, 1)
#define PIN_PB15__FLEXCOM9_IO2		PINMUX_PIN(PIN_PB15, 2, 1)
#define PIN_PB15__D1			PINMUX_PIN(PIN_PB15, 4, 1)
#define PIN_PB15__PWML3			PINMUX_PIN(PIN_PB15, 5, 2)
#define PIN_PB16			48
#define PIN_PB16__GPIO			PINMUX_PIN(PIN_PB16, 0, 0)
#define PIN_PB16__QSPI0_IO4		PINMUX_PIN(PIN_PB16, 1, 1)
#define PIN_PB16__FLEXCOM9_IO3		PINMUX_PIN(PIN_PB16, 2, 1)
#define PIN_PB16__PCK0			PINMUX_PIN(PIN_PB16, 3, 1)
#define PIN_PB16__D2			PINMUX_PIN(PIN_PB16, 4, 1)
#define PIN_PB16__PWMH3			PINMUX_PIN(PIN_PB16, 5, 2)
#define PIN_PB16__EXT_IRQ0		PINMUX_PIN(PIN_PB16, 6, 2)
#define PIN_PB17			49
#define PIN_PB17__GPIO			PINMUX_PIN(PIN_PB17, 0, 0)
#define PIN_PB17__QSPI0_IO5		PINMUX_PIN(PIN_PB17, 1, 1)
#define PIN_PB17__FLEXCOM9_IO4		PINMUX_PIN(PIN_PB17, 2, 1)
#define PIN_PB17__PCK1			PINMUX_PIN(PIN_PB17, 3, 1)
#define PIN_PB17__D3			PINMUX_PIN(PIN_PB17, 4, 1)
#define PIN_PB17__PWMEXTRG0		PINMUX_PIN(PIN_PB17, 5, 2)
#define PIN_PB17__EXT_IRQ1		PINMUX_PIN(PIN_PB17, 6, 2)
#define PIN_PB18			50
#define PIN_PB18__GPIO			PINMUX_PIN(PIN_PB18, 0, 0)
#define PIN_PB18__QSPI0_IO6		PINMUX_PIN(PIN_PB18, 1, 1)
#define PIN_PB18__FLEXCOM10_IO0		PINMUX_PIN(PIN_PB18, 2, 1)
#define PIN_PB18__PCK2			PINMUX_PIN(PIN_PB18, 3, 1)
#define PIN_PB18__D4			PINMUX_PIN(PIN_PB18, 4, 1)
#define PIN_PB18__PWMEXTRG1		PINMUX_PIN(PIN_PB18, 5, 2)
#define PIN_PB19			51
#define PIN_PB19__GPIO			PINMUX_PIN(PIN_PB19, 0, 0)
#define PIN_PB19__QSPI0_IO7		PINMUX_PIN(PIN_PB19, 1, 1)
#define PIN_PB19__FLEXCOM10_IO1		PINMUX_PIN(PIN_PB19, 2, 1)
#define PIN_PB19__PCK3			PINMUX_PIN(PIN_PB19, 3, 1)
#define PIN_PB19__D5			PINMUX_PIN(PIN_PB19, 4, 1)
#define PIN_PB19__PWMFI0		PINMUX_PIN(PIN_PB19, 5, 2)
#define PIN_PB20			52
#define PIN_PB20__GPIO			PINMUX_PIN(PIN_PB20, 0, 0)
#define PIN_PB20__QSPI0_DQS		PINMUX_PIN(PIN_PB20, 1, 1)
#define PIN_PB20__FLEXCOM10_IO2		PINMUX_PIN(PIN_PB20, 2, 1)
#define PIN_PB20__D6			PINMUX_PIN(PIN_PB20, 4, 1)
#define PIN_PB20__PWMFI1		PINMUX_PIN(PIN_PB20, 5, 2)
#define PIN_PB21			53
#define PIN_PB21__GPIO			PINMUX_PIN(PIN_PB21, 0, 0)
#define PIN_PB21__QSPI0_INT		PINMUX_PIN(PIN_PB21, 1, 1)
#define PIN_PB21__FLEXCOM10_IO3		PINMUX_PIN(PIN_PB21, 2, 1)
#define PIN_PB21__FLEXCOM9_IO5		PINMUX_PIN(PIN_PB21, 3, 1)
#define PIN_PB21__D7			PINMUX_PIN(PIN_PB21, 4, 1)
#define PIN_PB22			54
#define PIN_PB22__GPIO			PINMUX_PIN(PIN_PB22, 0, 0)
#define PIN_PB22__QSPI1_IO3		PINMUX_PIN(PIN_PB22, 1, 1)
#define PIN_PB22__FLEXCOM10_IO4		PINMUX_PIN(PIN_PB22, 2, 1)
#define PIN_PB22__FLEXCOM9_IO6		PINMUX_PIN(PIN_PB22, 3, 1)
#define PIN_PB22__NANDRDY		PINMUX_PIN(PIN_PB22, 4, 1)
#define PIN_PB23			55
#define PIN_PB23__GPIO			PINMUX_PIN(PIN_PB23, 0, 0)
#define PIN_PB23__QSPI1_IO2		PINMUX_PIN(PIN_PB23, 1, 1)
#define PIN_PB23__FLEXCOM7_IO0		PINMUX_PIN(PIN_PB23, 2, 1)
#define PIN_PB23__I2SMCC0_CK		PINMUX_PIN(PIN_PB23, 3, 1)
#define PIN_PB23__PCK4			PINMUX_PIN(PIN_PB23, 6, 1)
#define PIN_PB24			56
#define PIN_PB24__GPIO			PINMUX_PIN(PIN_PB24, 0, 0)
#define PIN_PB24__QSPI1_IO1		PINMUX_PIN(PIN_PB24, 1, 1)
#define PIN_PB24__FLEXCOM7_IO1		PINMUX_PIN(PIN_PB24, 2, 1)
#define PIN_PB24__I2SMCC0_WS		PINMUX_PIN(PIN_PB24, 3, 1)
#define PIN_PB24__PCK5			PINMUX_PIN(PIN_PB24, 6, 1)
#define PIN_PB25			57
#define PIN_PB25__GPIO			PINMUX_PIN(PIN_PB25, 0, 0)
#define PIN_PB25__QSPI1_IO0		PINMUX_PIN(PIN_PB25, 1, 1)
#define PIN_PB25__FLEXCOM7_IO2		PINMUX_PIN(PIN_PB25, 2, 1)
#define PIN_PB25__I2SMCC0_DOUT1		PINMUX_PIN(PIN_PB25, 3, 1)
#define PIN_PB25__PCK6			PINMUX_PIN(PIN_PB25, 6, 1)
#define PIN_PB26			58
#define PIN_PB26__GPIO			PINMUX_PIN(PIN_PB26, 0, 0)
#define PIN_PB26__QSPI1_CS		PINMUX_PIN(PIN_PB26, 1, 1)
#define PIN_PB26__FLEXCOM7_IO3		PINMUX_PIN(PIN_PB26, 2, 1)
#define PIN_PB26__I2SMCC0_DOUT0		PINMUX_PIN(PIN_PB26, 3, 1)
#define PIN_PB26__PWMEXTRG0		PINMUX_PIN(PIN_PB26, 5, 1)
#define PIN_PB26__PCK7			PINMUX_PIN(PIN_PB26, 6, 1)
#define PIN_PB27			59
#define PIN_PB27__GPIO			PINMUX_PIN(PIN_PB27, 0, 0)
#define PIN_PB27__QSPI1_SCK		PINMUX_PIN(PIN_PB27, 1, 1)
#define PIN_PB27__FLEXCOM7_IO4		PINMUX_PIN(PIN_PB27, 2, 1)
#define PIN_PB27__I2SMCC0_MCK		PINMUX_PIN(PIN_PB27, 3, 1)
#define PIN_PB27__PWMEXTRG1		PINMUX_PIN(PIN_PB27, 5, 1)
#define PIN_PB28			60
#define PIN_PB28__GPIO			PINMUX_PIN(PIN_PB28, 0, 0)
#define PIN_PB28__SDMMC1_RSTN		PINMUX_PIN(PIN_PB28, 1, 1)
#define PIN_PB28__ADTRG			PINMUX_PIN(PIN_PB28, 2, 2)
#define PIN_PB28__PWMFI0		PINMUX_PIN(PIN_PB28, 5, 1)
#define PIN_PB28__FLEXCOM7_IO0		PINMUX_PIN(PIN_PB28, 6, 4)
#define PIN_PB29			61
#define PIN_PB29__GPIO			PINMUX_PIN(PIN_PB29, 0, 0)
#define PIN_PB29__SDMMC1_CMD		PINMUX_PIN(PIN_PB29, 1, 1)
#define PIN_PB29__FLEXCOM3_IO2		PINMUX_PIN(PIN_PB29, 2, 2)
#define PIN_PB29__FLEXCOM0_IO5		PINMUX_PIN(PIN_PB29, 3, 2)
#define PIN_PB29__TIOA3			PINMUX_PIN(PIN_PB29, 4, 2)
#define PIN_PB29__PWMFI1		PINMUX_PIN(PIN_PB29, 5, 1)
#define PIN_PB29__FLEXCOM7_IO1		PINMUX_PIN(PIN_PB29, 6, 4)
#define PIN_PB30			62
#define PIN_PB30__GPIO			PINMUX_PIN(PIN_PB30, 0, 0)
#define PIN_PB30__SDMMC1_CK		PINMUX_PIN(PIN_PB30, 1, 1)
#define PIN_PB30__FLEXCOM3_IO3		PINMUX_PIN(PIN_PB30, 2, 2)
#define PIN_PB30__FLEXCOM0_IO6		PINMUX_PIN(PIN_PB30, 3, 2)
#define PIN_PB30__TIOB3			PINMUX_PIN(PIN_PB30, 4, 1)
#define PIN_PB30__PWMH0			PINMUX_PIN(PIN_PB30, 5, 1)
#define PIN_PB30__FLEXCOM8_IO0		PINMUX_PIN(PIN_PB30, 6, 4)
#define PIN_PB31			63
#define PIN_PB31__GPIO			PINMUX_PIN(PIN_PB31, 0, 0)
#define PIN_PB31__SDMMC1_DAT0		PINMUX_PIN(PIN_PB31, 1, 1)
#define PIN_PB31__FLEXCOM3_IO4		PINMUX_PIN(PIN_PB31, 2, 2)
#define PIN_PB31__FLEXCOM9_IO5		PINMUX_PIN(PIN_PB31, 3, 2)
#define PIN_PB31__TCLK3			PINMUX_PIN(PIN_PB31, 4, 1)
#define PIN_PB31__PWML0			PINMUX_PIN(PIN_PB31, 5, 1)
#define PIN_PB31__FLEXCOM8_IO1		PINMUX_PIN(PIN_PB31, 6, 4)
#define PIN_PC0				64
#define PIN_PC0__GPIO			PINMUX_PIN(PIN_PC0, 0, 0)
#define PIN_PC0__SDMMC1_DAT1		PINMUX_PIN(PIN_PC0, 1, 1)
#define PIN_PC0__FLEXCOM3_IO0		PINMUX_PIN(PIN_PC0, 2, 2)
#define PIN_PC0__TIOA4			PINMUX_PIN(PIN_PC0, 4, 1)
#define PIN_PC0__PWML1			PINMUX_PIN(PIN_PC0, 5, 1)
#define PIN_PC0__FLEXCOM9_IO0		PINMUX_PIN(PIN_PC0, 6, 4)
#define PIN_PC1				65
#define PIN_PC1__GPIO			PINMUX_PIN(PIN_PC1, 0, 0)
#define PIN_PC1__SDMMC1_DAT2		PINMUX_PIN(PIN_PC1, 1, 1)
#define PIN_PC1__FLEXCOM3_IO1		PINMUX_PIN(PIN_PC1, 2, 2)
#define PIN_PC1__TIOB4			PINMUX_PIN(PIN_PC1, 4, 1)
#define PIN_PC1__PWMH1			PINMUX_PIN(PIN_PC1, 5, 1)
#define PIN_PC1__FLEXCOM9_IO1		PINMUX_PIN(PIN_PC1, 6, 4)
#define PIN_PC2				66
#define PIN_PC2__GPIO			PINMUX_PIN(PIN_PC2, 0, 0)
#define PIN_PC2__SDMMC1_DAT3		PINMUX_PIN(PIN_PC2, 1, 1)
#define PIN_PC2__FLEXCOM4_IO0		PINMUX_PIN(PIN_PC2, 2, 2)
#define PIN_PC2__TCLK4			PINMUX_PIN(PIN_PC2, 4, 1)
#define PIN_PC2__PWML2			PINMUX_PIN(PIN_PC2, 5, 1)
#define PIN_PC2__FLEXCOM10_IO0		PINMUX_PIN(PIN_PC2, 6, 4)
#define PIN_PC3				67
#define PIN_PC3__GPIO			PINMUX_PIN(PIN_PC3, 0, 0)
#define PIN_PC3__SDMMC1_WP		PINMUX_PIN(PIN_PC3, 1, 1)
#define PIN_PC3__FLEXCOM4_IO1		PINMUX_PIN(PIN_PC3, 2, 2)
#define PIN_PC3__TIOA5			PINMUX_PIN(PIN_PC3, 4, 1)
#define PIN_PC3__PWMH2			PINMUX_PIN(PIN_PC3, 5, 1)
#define PIN_PC3__FLEXCOM10_IO1		PINMUX_PIN(PIN_PC3, 6, 4)
#define PIN_PC4				68
#define PIN_PC4__GPIO			PINMUX_PIN(PIN_PC4, 0, 0)
#define PIN_PC4__SDMMC1_CD		PINMUX_PIN(PIN_PC4, 1, 1)
#define PIN_PC4__FLEXCOM4_IO2		PINMUX_PIN(PIN_PC4, 2, 2)
#define PIN_PC4__FLEXCOM9_IO6		PINMUX_PIN(PIN_PC4, 3, 2)
#define PIN_PC4__TIOB5			PINMUX_PIN(PIN_PC4, 4, 1)
#define PIN_PC4__PWML3			PINMUX_PIN(PIN_PC4, 5, 1)
#define PIN_PC4__FLEXCOM11_IO0		PINMUX_PIN(PIN_PC4, 6, 4)
#define PIN_PC5				69
#define PIN_PC5__GPIO			PINMUX_PIN(PIN_PC5, 0, 0)
#define PIN_PC5__SDMMC1_1V8SEL		PINMUX_PIN(PIN_PC5, 1, 1)
#define PIN_PC5__FLEXCOM4_IO3		PINMUX_PIN(PIN_PC5, 2, 2)
#define PIN_PC5__FLEXCOM6_IO5		PINMUX_PIN(PIN_PC5, 3, 2)
#define PIN_PC5__TCLK5			PINMUX_PIN(PIN_PC5, 4, 1)
#define PIN_PC5__PWMH3			PINMUX_PIN(PIN_PC5, 5, 1)
#define PIN_PC5__FLEXCOM11_IO1		PINMUX_PIN(PIN_PC5, 6, 4)
#define PIN_PC6				70
#define PIN_PC6__GPIO			PINMUX_PIN(PIN_PC6, 0, 0)
#define PIN_PC6__FLEXCOM4_IO4		PINMUX_PIN(PIN_PC6, 2, 2)
#define PIN_PC6__FLEXCOM6_IO6		PINMUX_PIN(PIN_PC6, 3, 2)
#define PIN_PC7				71
#define PIN_PC7__GPIO			PINMUX_PIN(PIN_PC7, 0, 0)
#define PIN_PC7__I2SMCC0_DIN0		PINMUX_PIN(PIN_PC7, 1, 1)
#define PIN_PC7__FLEXCOM7_IO0		PINMUX_PIN(PIN_PC7, 2, 2)
#define PIN_PC8				72
#define PIN_PC8__GPIO			PINMUX_PIN(PIN_PC8, 0, 0)
#define PIN_PC8__I2SMCC0_DIN1		PINMUX_PIN(PIN_PC8, 1, 1)
#define PIN_PC8__FLEXCOM7_IO1		PINMUX_PIN(PIN_PC8, 2, 2)
#define PIN_PC9				73
#define PIN_PC9__GPIO			PINMUX_PIN(PIN_PC9, 0, 0)
#define PIN_PC9__I2SMCC0_DOUT3		PINMUX_PIN(PIN_PC9, 1, 1)
#define PIN_PC9__FLEXCOM7_IO2		PINMUX_PIN(PIN_PC9, 2, 2)
#define PIN_PC9__FLEXCOM1_IO0		PINMUX_PIN(PIN_PC9, 6, 4)
#define PIN_PC10			74
#define PIN_PC10__GPIO			PINMUX_PIN(PIN_PC10, 0, 0)
#define PIN_PC10__I2SMCC0_DOUT2		PINMUX_PIN(PIN_PC10, 1, 1)
#define PIN_PC10__FLEXCOM7_IO3		PINMUX_PIN(PIN_PC10, 2, 2)
#define PIN_PC10__FLEXCOM1_IO1		PINMUX_PIN(PIN_PC10, 6, 4)
#define PIN_PC11			75
#define PIN_PC11__GPIO			PINMUX_PIN(PIN_PC11, 0, 0)
#define PIN_PC11__I2SMCC1_CK		PINMUX_PIN(PIN_PC11, 1, 1)
#define PIN_PC11__FLEXCOM7_IO4		PINMUX_PIN(PIN_PC11, 2, 2)
#define PIN_PC11__FLEXCOM2_IO0		PINMUX_PIN(PIN_PC11, 6, 4)
#define PIN_PC12			76
#define PIN_PC12__GPIO			PINMUX_PIN(PIN_PC12, 0, 0)
#define PIN_PC12__I2SMCC1_WS		PINMUX_PIN(PIN_PC12, 1, 1)
#define PIN_PC12__FLEXCOM8_IO2		PINMUX_PIN(PIN_PC12, 2, 2)
#define PIN_PC12__FLEXCOM2_IO1		PINMUX_PIN(PIN_PC12, 6, 4)
#define PIN_PC13			77
#define PIN_PC13__GPIO			PINMUX_PIN(PIN_PC13, 0, 0)
#define PIN_PC13__I2SMCC1_MCK		PINMUX_PIN(PIN_PC13, 1, 1)
#define PIN_PC13__FLEXCOM8_IO1		PINMUX_PIN(PIN_PC13, 2, 2)
#define PIN_PC13__FLEXCOM3_IO0		PINMUX_PIN(PIN_PC13, 6, 4)
#define PIN_PC14			78
#define PIN_PC14__GPIO			PINMUX_PIN(PIN_PC14, 0, 0)
#define PIN_PC14__I2SMCC1_DOUT0		PINMUX_PIN(PIN_PC14, 1, 1)
#define PIN_PC14__FLEXCOM8_IO0		PINMUX_PIN(PIN_PC14, 2, 2)
#define PIN_PC14__FLEXCOM3_IO1		PINMUX_PIN(PIN_PC14, 6, 4)
#define PIN_PC15			79
#define PIN_PC15__GPIO			PINMUX_PIN(PIN_PC15, 0, 0)
#define PIN_PC15__I2SMCC1_DOUT1		PINMUX_PIN(PIN_PC15, 1, 1)
#define PIN_PC15__FLEXCOM8_IO3		PINMUX_PIN(PIN_PC15, 2, 2)
#define PIN_PC15__FLEXCOM4_IO0		PINMUX_PIN(PIN_PC15, 6, 4)
#define PIN_PC16			80
#define PIN_PC16__GPIO			PINMUX_PIN(PIN_PC16, 0, 0)
#define PIN_PC16__I2SMCC1_DOUT2		PINMUX_PIN(PIN_PC16, 1, 1)
#define PIN_PC16__FLEXCOM8_IO4		PINMUX_PIN(PIN_PC16, 2, 2)
#define PIN_PC16__FLEXCOM3_IO1		PINMUX_PIN(PIN_PC16, 6, 4)
#define PIN_PC17			81
#define PIN_PC17__GPIO			PINMUX_PIN(PIN_PC17, 0, 0)
#define PIN_PC17__I2SMCC1_DOUT3		PINMUX_PIN(PIN_PC17, 1, 1)
#define PIN_PC17__EXT_IRQ0		PINMUX_PIN(PIN_PC17, 2, 3)
#define PIN_PC17__FLEXCOM5_IO0		PINMUX_PIN(PIN_PC17, 6, 4)
#define PIN_PC18			82
#define PIN_PC18__GPIO			PINMUX_PIN(PIN_PC18, 0, 0)
#define PIN_PC18__I2SMCC1_DIN0		PINMUX_PIN(PIN_PC18, 1, 1)
#define PIN_PC18__FLEXCOM9_IO0		PINMUX_PIN(PIN_PC18, 2, 2)
#define PIN_PC18__FLEXCOM5_IO1		PINMUX_PIN(PIN_PC18, 6, 4)
#define PIN_PC19			83
#define PIN_PC19__GPIO			PINMUX_PIN(PIN_PC19, 0, 0)
#define PIN_PC19__I2SMCC1_DIN1		PINMUX_PIN(PIN_PC19, 1, 1)
#define PIN_PC19__FLEXCOM9_IO1		PINMUX_PIN(PIN_PC19, 2, 2)
#define PIN_PC19__FLEXCOM6_IO0		PINMUX_PIN(PIN_PC19, 6, 4)
#define PIN_PC20			84
#define PIN_PC20__GPIO			PINMUX_PIN(PIN_PC20, 0, 0)
#define PIN_PC20__I2SMCC1_DIN2		PINMUX_PIN(PIN_PC20, 1, 1)
#define PIN_PC20__FLEXCOM9_IO4		PINMUX_PIN(PIN_PC20, 2, 2)
#define PIN_PC20__FLEXCOM6_IO1		PINMUX_PIN(PIN_PC20, 6, 4)
#define PIN_PC21			85
#define PIN_PC21__GPIO			PINMUX_PIN(PIN_PC21, 0, 0)
#define PIN_PC21__I2SMCC1_DIN3		PINMUX_PIN(PIN_PC21, 1, 1)
#define PIN_PC21__FLEXCOM9_IO2		PINMUX_PIN(PIN_PC21, 2, 2)
#define PIN_PC21__D3			PINMUX_PIN(PIN_PC21, 4, 2)
#define PIN_PC21__FLEXCOM6_IO0		PINMUX_PIN(PIN_PC21, 6, 5)
#define PIN_PC22			86
#define PIN_PC22__GPIO			PINMUX_PIN(PIN_PC22, 0, 0)
#define PIN_PC22__I2SMCC0_DIN2		PINMUX_PIN(PIN_PC22, 1, 1)
#define PIN_PC22__FLEXCOM9_IO3		PINMUX_PIN(PIN_PC22, 2, 2)
#define PIN_PC22__D4			PINMUX_PIN(PIN_PC22, 4, 2)
#define PIN_PC22__FLEXCOM6_IO1		PINMUX_PIN(PIN_PC22, 6, 5)
#define PIN_PC23			87
#define PIN_PC23__GPIO			PINMUX_PIN(PIN_PC23, 0, 0)
#define PIN_PC23__I2SMCC0_DIN3		PINMUX_PIN(PIN_PC23, 1, 1)
#define PIN_PC23__FLEXCOM0_IO5		PINMUX_PIN(PIN_PC23, 2, 3)
#define PIN_PC23__D5			PINMUX_PIN(PIN_PC23, 4, 2)
#define PIN_PC23__FLEXCOM7_IO0		PINMUX_PIN(PIN_PC23, 6, 5)
#define PIN_PC24			88
#define PIN_PC24__GPIO			PINMUX_PIN(PIN_PC24, 0, 0)
#define PIN_PC24__FLEXCOM0_IO6		PINMUX_PIN(PIN_PC24, 2, 3)
#define PIN_PC24__EXT_IRQ1		PINMUX_PIN(PIN_PC24, 3, 3)
#define PIN_PC24__D6			PINMUX_PIN(PIN_PC24, 4, 2)
#define PIN_PC24__FLEXCOM7_IO1		PINMUX_PIN(PIN_PC24, 6, 5)
#define PIN_PC25			89
#define PIN_PC25__GPIO			PINMUX_PIN(PIN_PC25, 0, 0)
#define PIN_PC25__NTRST			PINMUX_PIN(PIN_PC25, 1, 1)
#define PIN_PC26			90
#define PIN_PC26__GPIO			PINMUX_PIN(PIN_PC26, 0, 0)
#define PIN_PC26__TCK_SWCLK		PINMUX_PIN(PIN_PC26, 1, 1)
#define PIN_PC27			91
#define PIN_PC27__GPIO			PINMUX_PIN(PIN_PC27, 0, 0)
#define PIN_PC27__TMS_SWDIO		PINMUX_PIN(PIN_PC27, 1, 1)
#define PIN_PC28			92
#define PIN_PC28__GPIO			PINMUX_PIN(PIN_PC28, 0, 0)
#define PIN_PC28__TDI			PINMUX_PIN(PIN_PC28, 1, 1)
#define PIN_PC29			93
#define PIN_PC29__GPIO			PINMUX_PIN(PIN_PC29, 0, 0)
#define PIN_PC29__TDO			PINMUX_PIN(PIN_PC29, 1, 1)
#define PIN_PC30			94
#define PIN_PC30__GPIO			PINMUX_PIN(PIN_PC30, 0, 0)
#define PIN_PC30__FLEXCOM10_IO0		PINMUX_PIN(PIN_PC30, 2, 2)
#define PIN_PC31			95
#define PIN_PC31__GPIO			PINMUX_PIN(PIN_PC31, 0, 0)
#define PIN_PC31__FLEXCOM10_IO1		PINMUX_PIN(PIN_PC31, 2, 2)
#define PIN_PD0				96
#define PIN_PD0__GPIO			PINMUX_PIN(PIN_PD0, 0, 0)
#define PIN_PD0__FLEXCOM11_IO0		PINMUX_PIN(PIN_PD0, 2, 2)
#define PIN_PD1				97
#define PIN_PD1__GPIO			PINMUX_PIN(PIN_PD1, 0, 0)
#define PIN_PD1__FLEXCOM11_IO1		PINMUX_PIN(PIN_PD1, 2, 2)
#define PIN_PD2				98
#define PIN_PD2__GPIO			PINMUX_PIN(PIN_PD2, 0, 0)
#define PIN_PD2__SDMMC2_RSTN		PINMUX_PIN(PIN_PD2, 1, 1)
#define PIN_PD2__PCK0			PINMUX_PIN(PIN_PD2, 2, 2)
#define PIN_PD2__CANTX4			PINMUX_PIN(PIN_PD2, 3, 1)
#define PIN_PD2__D7			PINMUX_PIN(PIN_PD2, 4, 2)
#define PIN_PD2__TIOA0			PINMUX_PIN(PIN_PD2, 5, 2)
#define PIN_PD2__FLEXCOM8_IO0		PINMUX_PIN(PIN_PD2, 6, 5)
#define PIN_PD3				99
#define PIN_PD3__GPIO			PINMUX_PIN(PIN_PD3, 0, 0)
#define PIN_PD3__SDMMC2_CMD		PINMUX_PIN(PIN_PD3, 1, 1)
#define PIN_PD3__FLEXCOM0_IO0		PINMUX_PIN(PIN_PD3, 2, 2)
#define PIN_PD3__CANRX4			PINMUX_PIN(PIN_PD3, 3, 1)
#define PIN_PD3__NANDRDY		PINMUX_PIN(PIN_PD3, 4, 2)
#define PIN_PD3__TIOB0			PINMUX_PIN(PIN_PD3, 5, 2)
#define PIN_PD3__FLEXCOM8_IO1		PINMUX_PIN(PIN_PD3, 6, 5)
#define PIN_PD4				100
#define PIN_PD4__GPIO			PINMUX_PIN(PIN_PD4, 0, 0)
#define PIN_PD4__SDMMC2_CK		PINMUX_PIN(PIN_PD4, 1, 1)
#define PIN_PD4__FLEXCOM0_IO1		PINMUX_PIN(PIN_PD4, 2, 2)
#define PIN_PD4__CANTX5			PINMUX_PIN(PIN_PD4, 3, 1)
#define PIN_PD4__NCS3_NANDCS		PINMUX_PIN(PIN_PD4, 4, 2)
#define PIN_PD4__TCLK0			PINMUX_PIN(PIN_PD4, 5, 2)
#define PIN_PD4__FLEXCOM9_IO0		PINMUX_PIN(PIN_PD4, 6, 5)
#define PIN_PD5				101
#define PIN_PD5__GPIO			PINMUX_PIN(PIN_PD5, 0, 0)
#define PIN_PD5__SDMMC2_DAT0		PINMUX_PIN(PIN_PD5, 1, 1)
#define PIN_PD5__FLEXCOM0_IO2		PINMUX_PIN(PIN_PD5, 2, 2)
#define PIN_PD5__CANRX5			PINMUX_PIN(PIN_PD5, 3, 1)
#define PIN_PD5__NWE_NWR0_NANDWE	PINMUX_PIN(PIN_PD5, 4, 2)
#define PIN_PD5__TIOA1			PINMUX_PIN(PIN_PD5, 5, 2)
#define PIN_PD5__FLEXCOM9_IO1		PINMUX_PIN(PIN_PD5, 6, 5)
#define PIN_PD6				102
#define PIN_PD6__GPIO			PINMUX_PIN(PIN_PD6, 0, 0)
#define PIN_PD6__SDMMC2_DAT1		PINMUX_PIN(PIN_PD6, 1, 1)
#define PIN_PD6__FLEXCOM0_IO3		PINMUX_PIN(PIN_PD6, 2, 2)
#define PIN_PD6__SPDIF_RX		PINMUX_PIN(PIN_PD6, 3, 3)
#define PIN_PD6__NRD_NANDOE		PINMUX_PIN(PIN_PD6, 4, 2)
#define PIN_PD6__TIOB1			PINMUX_PIN(PIN_PD6, 5, 2)
#define PIN_PD6__FLEXCOM10_IO0		PINMUX_PIN(PIN_PD6, 6, 5)
#define PIN_PD7				103
#define PIN_PD7__GPIO			PINMUX_PIN(PIN_PD7, 0, 0)
#define PIN_PD7__SDMMC2_DAT2		PINMUX_PIN(PIN_PD7, 1, 1)
#define PIN_PD7__FLEXCOM0_IO4		PINMUX_PIN(PIN_PD7, 2, 2)
#define PIN_PD7__SPDIF_TX		PINMUX_PIN(PIN_PD7, 2, 2)
#define PIN_PD7__A21_NANDALE		PINMUX_PIN(PIN_PD7, 4, 2)
#define PIN_PD7__TCLK1			PINMUX_PIN(PIN_PD7, 5, 2)
#define PIN_PD7__FLEXCOM10_IO1		PINMUX_PIN(PIN_PD7, 6, 5)
#define PIN_PD8				104
#define PIN_PD8__GPIO			PINMUX_PIN(PIN_PD8, 0, 0)
#define PIN_PD8__SDMMC2_DAT3		PINMUX_PIN(PIN_PD8, 1, 1)
#define PIN_PD8__I2SMCC0_DIN0		PINMUX_PIN(PIN_PD8, 3, 1)
#define PIN_PD8__A22_NANDCLE		PINMUX_PIN(PIN_PD8, 4, 2)
#define PIN_PD8__TIOA2			PINMUX_PIN(PIN_PD8, 5, 2)
#define PIN_PD8__FLEXCOM11_IO0		PINMUX_PIN(PIN_PD8, 6, 5)
#define PIN_PD9				105
#define PIN_PD9__GPIO			PINMUX_PIN(PIN_PD9, 0, 0)
#define PIN_PD9__SDMMC2_WP		PINMUX_PIN(PIN_PD9, 1, 1)
#define PIN_PD9__I2SMCC0_DIN1		PINMUX_PIN(PIN_PD9, 3, 2)
#define PIN_PD9__D0			PINMUX_PIN(PIN_PD9, 4, 2)
#define PIN_PD9__TIOB2			PINMUX_PIN(PIN_PD9, 5, 2)
#define PIN_PD9__FLEXCOM11_IO1		PINMUX_PIN(PIN_PD9, 6, 5)
#define PIN_PD10			106
#define PIN_PD10__GPIO			PINMUX_PIN(PIN_PD10, 0, 0)
#define PIN_PD10__SDMMC2_CD		PINMUX_PIN(PIN_PD10, 1, 1)
#define PIN_PD10__PCK6			PINMUX_PIN(PIN_PD10, 2, 2)
#define PIN_PD10__I2SMCC0_DIN2		PINMUX_PIN(PIN_PD10, 3, 2)
#define PIN_PD10__D1			PINMUX_PIN(PIN_PD10, 4, 2)
#define PIN_PD10__TCLK2			PINMUX_PIN(PIN_PD10, 5, 2)
#define PIN_PD10__FLEXCOM0_IO0		PINMUX_PIN(PIN_PD10, 6, 3)
#define PIN_PD11			107
#define PIN_PD11__GPIO			PINMUX_PIN(PIN_PD11, 0, 0)
#define PIN_PD11__SDMMC2_1V8SEL		PINMUX_PIN(PIN_PD11, 1, 1)
#define PIN_PD11__PCK7			PINMUX_PIN(PIN_PD11, 2, 2)
#define PIN_PD11__I2SMCC0_DIN3		PINMUX_PIN(PIN_PD11, 3, 2)
#define PIN_PD11__D2			PINMUX_PIN(PIN_PD11, 4, 2)
#define PIN_PD11__TIOA3			PINMUX_PIN(PIN_PD11, 5, 2)
#define PIN_PD11__FLEXCOM0_IO1		PINMUX_PIN(PIN_PD11, 6, 3)
#define PIN_PD12			108
#define PIN_PD12__GPIO			PINMUX_PIN(PIN_PD12, 0, 0)
#define PIN_PD12__PCK1			PINMUX_PIN(PIN_PD12, 1, 2)
#define PIN_PD12__FLEXCOM1_IO0		PINMUX_PIN(PIN_PD12, 2, 2)
#define PIN_PD12__CANTX0		PINMUX_PIN(PIN_PD12, 4, 2)
#define PIN_PD12__TIOB3			PINMUX_PIN(PIN_PD12, 5, 2)
#define PIN_PD13			109
#define PIN_PD13__GPIO			PINMUX_PIN(PIN_PD13, 0, 0)
#define PIN_PD13__I2SMCC0_CK		PINMUX_PIN(PIN_PD13, 1, 2)
#define PIN_PD13__FLEXCOM1_IO1		PINMUX_PIN(PIN_PD13, 2, 2)
#define PIN_PD13__PWML0			PINMUX_PIN(PIN_PD13, 3, 4)
#define PIN_PD13__CANRX0		PINMUX_PIN(PIN_PD13, 4, 2)
#define PIN_PD13__TCLK3			PINMUX_PIN(PIN_PD13, 5, 2)
#define PIN_PD14			110
#define PIN_PD14__GPIO			PINMUX_PIN(PIN_PD14, 0, 0)
#define PIN_PD14__I2SMCC0_MCK		PINMUX_PIN(PIN_PD14, 1, 2)
#define PIN_PD14__FLEXCOM1_IO2		PINMUX_PIN(PIN_PD14, 2, 2)
#define PIN_PD14__PWMH0			PINMUX_PIN(PIN_PD14, 3, 4)
#define PIN_PD14__CANTX1		PINMUX_PIN(PIN_PD14, 4, 2)
#define PIN_PD14__TIOA4			PINMUX_PIN(PIN_PD14, 5, 2)
#define PIN_PD14__FLEXCOM2_IO0		PINMUX_PIN(PIN_PD14, 6, 5)
#define PIN_PD15			111
#define PIN_PD15__GPIO			PINMUX_PIN(PIN_PD15, 0, 0)
#define PIN_PD15__I2SMCC0_WS		PINMUX_PIN(PIN_PD15, 1, 2)
#define PIN_PD15__FLEXCOM1_IO3		PINMUX_PIN(PIN_PD15, 2, 2)
#define PIN_PD15__PWML1			PINMUX_PIN(PIN_PD15, 3, 4)
#define PIN_PD15__CANRX1		PINMUX_PIN(PIN_PD15, 4, 2)
#define PIN_PD15__TIOB4			PINMUX_PIN(PIN_PD15, 5, 2)
#define PIN_PD15__FLEXCOM2_IO1		PINMUX_PIN(PIN_PD15, 6, 5)
#define PIN_PD16			112
#define PIN_PD16__GPIO			PINMUX_PIN(PIN_PD16, 0, 0)
#define PIN_PD16__I2SMCC0_DOUT0		PINMUX_PIN(PIN_PD16, 1, 2)
#define PIN_PD16__FLEXCOM1_IO4		PINMUX_PIN(PIN_PD16, 2, 2)
#define PIN_PD16__PWMH1			PINMUX_PIN(PIN_PD16, 3, 4)
#define PIN_PD16__CANTX2		PINMUX_PIN(PIN_PD16, 4, 2)
#define PIN_PD16__TCLK4			PINMUX_PIN(PIN_PD16, 5, 2)
#define PIN_PD16__FLEXCOM3_IO0		PINMUX_PIN(PIN_PD16, 6, 5)
#define PIN_PD17			113
#define PIN_PD17__GPIO			PINMUX_PIN(PIN_PD17, 0, 0)
#define PIN_PD17__I2SMCC0_DOUT1		PINMUX_PIN(PIN_PD17, 1, 2)
#define PIN_PD17__FLEXCOM2_IO0		PINMUX_PIN(PIN_PD17, 2, 2)
#define PIN_PD17__PWML2			PINMUX_PIN(PIN_PD17, 3, 4)
#define PIN_PD17__CANRX2		PINMUX_PIN(PIN_PD17, 4, 2)
#define PIN_PD17__TIOA5			PINMUX_PIN(PIN_PD17, 5, 2)
#define PIN_PD17__FLEXCOM3_IO1		PINMUX_PIN(PIN_PD17, 6, 5)
#define PIN_PD18			114
#define PIN_PD18__GPIO			PINMUX_PIN(PIN_PD18, 0, 0)
#define PIN_PD18__I2SMCC0_DOUT2		PINMUX_PIN(PIN_PD18, 1, 2)
#define PIN_PD18__FLEXCOM2_IO1		PINMUX_PIN(PIN_PD18, 2, 2)
#define PIN_PD18__PWMH2			PINMUX_PIN(PIN_PD18, 3, 4)
#define PIN_PD18__CANTX3		PINMUX_PIN(PIN_PD18, 4, 2)
#define PIN_PD18__TIOB5			PINMUX_PIN(PIN_PD18, 5, 2)
#define PIN_PD18__FLEXCOM4_IO0		PINMUX_PIN(PIN_PD18, 6, 5)
#define PIN_PD19			115
#define PIN_PD19__GPIO			PINMUX_PIN(PIN_PD19, 0, 0)
#define PIN_PD19__I2SMCC0_DOUT3		PINMUX_PIN(PIN_PD19, 1, 2)
#define PIN_PD19__FLEXCOM2_IO2		PINMUX_PIN(PIN_PD19, 2, 2)
#define PIN_PD19__PWML3			PINMUX_PIN(PIN_PD19, 3, 4)
#define PIN_PD19__CANRX3		PINMUX_PIN(PIN_PD19, 4, 2)
#define PIN_PD19__TCLK5			PINMUX_PIN(PIN_PD19, 5, 2)
#define PIN_PD19__FLEXCOM4_IO1		PINMUX_PIN(PIN_PD19, 6, 5)
#define PIN_PD20			116
#define PIN_PD20__GPIO			PINMUX_PIN(PIN_PD20, 0, 0)
#define PIN_PD20__PCK0			PINMUX_PIN(PIN_PD20, 1, 3)
#define PIN_PD20__FLEXCOM2_IO3		PINMUX_PIN(PIN_PD20, 2, 2)
#define PIN_PD20__PWMH3			PINMUX_PIN(PIN_PD20, 3, 4)
#define PIN_PD20__CANTX4		PINMUX_PIN(PIN_PD20, 4, 2)
#define PIN_PD20__FLEXCOM5_IO0		PINMUX_PIN(PIN_PD20, 6, 5)
#define PIN_PD21			117
#define PIN_PD21__GPIO			PINMUX_PIN(PIN_PD21, 0, 0)
#define PIN_PD21__PCK1			PINMUX_PIN(PIN_PD21, 1, 3)
#define PIN_PD21__FLEXCOM2_IO4		PINMUX_PIN(PIN_PD21, 2, 2)
#define PIN_PD21__CANRX4		PINMUX_PIN(PIN_PD21, 4, 2)
#define PIN_PD21__FLEXCOM5_IO1		PINMUX_PIN(PIN_PD21, 6, 5)
#define PIN_PD21__G1_TXEN		PINMUX_PIN(PIN_PD21, 7, 1)
#define PIN_PD22			118
#define PIN_PD22__GPIO			PINMUX_PIN(PIN_PD22, 0, 0)
#define PIN_PD22__PDMC0_CLK		PINMUX_PIN(PIN_PD22, 1, 2)
#define PIN_PD22__PWMEXTRG0		PINMUX_PIN(PIN_PD22, 3, 4)
#define PIN_PD22__RD1			PINMUX_PIN(PIN_PD22, 4, 2)
#define PIN_PD22__CANTX5		PINMUX_PIN(PIN_PD22, 6, 2)
#define PIN_PD22__G1_TX0		PINMUX_PIN(PIN_PD22, 7, 1)
#define PIN_PD23			119
#define PIN_PD23__GPIO			PINMUX_PIN(PIN_PD23, 0, 0)
#define PIN_PD23__PDMC0_DS0		PINMUX_PIN(PIN_PD23, 1, 2)
#define PIN_PD23__PWMEXTRG1		PINMUX_PIN(PIN_PD23, 3, 4)
#define PIN_PD23__RF1			PINMUX_PIN(PIN_PD23, 4, 2)
#define PIN_PD23__ISC_MCK		PINMUX_PIN(PIN_PD23, 5, 2)
#define PIN_PD23__CANRX5		PINMUX_PIN(PIN_PD23, 6, 2)
#define PIN_PD23__G1_TX1		PINMUX_PIN(PIN_PD23, 7, 1)
#define PIN_PD24			120
#define PIN_PD24__GPIO			PINMUX_PIN(PIN_PD24, 0, 0)
#define PIN_PD24__PDMC0_DS1		PINMUX_PIN(PIN_PD24, 1, 2)
#define PIN_PD24__PWMFI0		PINMUX_PIN(PIN_PD24, 3, 4)
#define PIN_PD24__RK1			PINMUX_PIN(PIN_PD24, 4, 2)
#define PIN_PD24__ISC_D0		PINMUX_PIN(PIN_PD24, 5, 2)
#define PIN_PD24__G1_RXDV		PINMUX_PIN(PIN_PD24, 7, 1)
#define PIN_PD25			121
#define PIN_PD25__GPIO			PINMUX_PIN(PIN_PD25, 0, 0)
#define PIN_PD25__PDMC1_CLK		PINMUX_PIN(PIN_PD25, 1, 2)
#define PIN_PD25__FLEXCOM5_IO0		PINMUX_PIN(PIN_PD25, 2, 2)
#define PIN_PD25__PWMFI1		PINMUX_PIN(PIN_PD25, 3, 4)
#define PIN_PD25__TD1			PINMUX_PIN(PIN_PD25, 4, 2)
#define PIN_PD25__ISC_D1		PINMUX_PIN(PIN_PD25, 5, 2)
#define PIN_PD25__G1_RX0		PINMUX_PIN(PIN_PD25, 7, 1)
#define PIN_PD26			122
#define PIN_PD26__GPIO			PINMUX_PIN(PIN_PD26, 0, 0)
#define PIN_PD26__PDMC1_DS0		PINMUX_PIN(PIN_PD26, 1, 2)
#define PIN_PD26__FLEXCOM5_IO1		PINMUX_PIN(PIN_PD26, 2, 2)
#define PIN_PD26__ADTRG			PINMUX_PIN(PIN_PD26, 3, 3)
#define PIN_PD26__TF1			PINMUX_PIN(PIN_PD26, 4, 2)
#define PIN_PD26__ISC_D2		PINMUX_PIN(PIN_PD26, 5, 2)
#define PIN_PD26__G1_RX1		PINMUX_PIN(PIN_PD26, 7, 1)
#define PIN_PD27			123
#define PIN_PD27__GPIO			PINMUX_PIN(PIN_PD27, 0, 0)
#define PIN_PD27__PDMC1_DS1		PINMUX_PIN(PIN_PD27, 1, 2)
#define PIN_PD27__FLEXCOM5_IO2		PINMUX_PIN(PIN_PD27, 2, 2)
#define PIN_PD27__TIOA0			PINMUX_PIN(PIN_PD27, 3, 3)
#define PIN_PD27__TK1			PINMUX_PIN(PIN_PD27, 4, 2)
#define PIN_PD27__ISC_D3		PINMUX_PIN(PIN_PD27, 5, 2)
#define PIN_PD27__G1_RXER		PINMUX_PIN(PIN_PD27, 7, 1)
#define PIN_PD28			124
#define PIN_PD28__GPIO			PINMUX_PIN(PIN_PD28, 0, 0)
#define PIN_PD28__RD0			PINMUX_PIN(PIN_PD28, 1, 2)
#define PIN_PD28__FLEXCOM5_IO3		PINMUX_PIN(PIN_PD28, 2, 2)
#define PIN_PD28__TIOB0			PINMUX_PIN(PIN_PD28, 3, 3)
#define PIN_PD28__I2SMCC1_CK		PINMUX_PIN(PIN_PD28, 4, 2)
#define PIN_PD28__ISC_D4		PINMUX_PIN(PIN_PD28, 5, 2)
#define PIN_PD28__PWML3			PINMUX_PIN(PIN_PD28, 6, 5)
#define PIN_PD28__G1_MDC		PINMUX_PIN(PIN_PD28, 7, 1)
#define PIN_PD29			125
#define PIN_PD29__GPIO			PINMUX_PIN(PIN_PD29, 0, 0)
#define PIN_PD29__RF0			PINMUX_PIN(PIN_PD29, 1, 2)
#define PIN_PD29__FLEXCOM5_IO4		PINMUX_PIN(PIN_PD29, 2, 2)
#define PIN_PD29__TCLK0			PINMUX_PIN(PIN_PD29, 3, 3)
#define PIN_PD29__I2SMCC1_WS		PINMUX_PIN(PIN_PD29, 4, 2)
#define PIN_PD29__ISC_D5		PINMUX_PIN(PIN_PD29, 5, 2)
#define PIN_PD29__PWMH3			PINMUX_PIN(PIN_PD29, 6, 5)
#define PIN_PD29__G1_MDIO		PINMUX_PIN(PIN_PD29, 7, 1)
#define PIN_PD30			126
#define PIN_PD30__GPIO			PINMUX_PIN(PIN_PD30, 0, 0)
#define PIN_PD30__RK0			PINMUX_PIN(PIN_PD30, 1, 2)
#define PIN_PD30__FLEXCOM6_IO0		PINMUX_PIN(PIN_PD30, 2, 2)
#define PIN_PD30__TIOA1			PINMUX_PIN(PIN_PD30, 3, 3)
#define PIN_PD30__I2SMCC1_MCK		PINMUX_PIN(PIN_PD30, 4, 2)
#define PIN_PD30__ISC_D6		PINMUX_PIN(PIN_PD30, 5, 2)
#define PIN_PD30__PWMEXTRG0		PINMUX_PIN(PIN_PD30, 6, 5)
#define PIN_PD30__G1_TXCK		PINMUX_PIN(PIN_PD30, 7, 1)
#define PIN_PD31			127
#define PIN_PD31__GPIO			PINMUX_PIN(PIN_PD31, 0, 0)
#define PIN_PD31__TD0			PINMUX_PIN(PIN_PD31, 1, 2)
#define PIN_PD31__FLEXCOM6_IO1		PINMUX_PIN(PIN_PD31, 2, 2)
#define PIN_PD31__TIOB1			PINMUX_PIN(PIN_PD31, 3, 3)
#define PIN_PD31__I2SMCC1_DOUT0		PINMUX_PIN(PIN_PD31, 4, 2)
#define PIN_PD31__ISC_D7		PINMUX_PIN(PIN_PD31, 5, 2)
#define PIN_PD31__PWM_EXTRG1		PINMUX_PIN(PIN_PD31, 6, 5)
#define PIN_PD31__G1_TX2		PINMUX_PIN(PIN_PD31, 7, 1)
#define PIN_PE0				128
#define PIN_PE0__GPIO			PINMUX_PIN(PIN_PE0, 0, 0)
#define PIN_PE0__TF0			PINMUX_PIN(PIN_PE0, 1, 2)
#define PIN_PE0__FLEXCOM6_IO2		PINMUX_PIN(PIN_PE0, 2, 2)
#define PIN_PE0__TCLK1			PINMUX_PIN(PIN_PE0, 3, 3)
#define PIN_PE0__I2SMCC1_DOUT1		PINMUX_PIN(PIN_PE0, 4, 2)
#define PIN_PE0__ISC_HSYNC		PINMUX_PIN(PIN_PE0, 5, 2)
#define PIN_PE0__PWMFI0			PINMUX_PIN(PIN_PE0, 6, 5)
#define PIN_PE0__G1_TX3			PINMUX_PIN(PIN_PE0, 7, 1)
#define PIN_PE1				129
#define PIN_PE1__GPIO			PINMUX_PIN(PIN_PE1, 0, 0)
#define PIN_PE1__TK0			PINMUX_PIN(PIN_PE1, 1, 2)
#define PIN_PE1__FLEXCOM6_IO3		PINMUX_PIN(PIN_PE1, 2, 2)
#define PIN_PE1__TIOA2			PINMUX_PIN(PIN_PE1, 3, 3)
#define PIN_PE1__I2SMCC1_DOUT2		PINMUX_PIN(PIN_PE1, 4, 2)
#define PIN_PE1__ISC_VSYNC		PINMUX_PIN(PIN_PE1, 5, 2)
#define PIN_PE1__PWMFI1			PINMUX_PIN(PIN_PE1, 6, 5)
#define PIN_PE1__G1_RX2			PINMUX_PIN(PIN_PE1, 7, 1)
#define PIN_PE2				130
#define PIN_PE2__GPIO			PINMUX_PIN(PIN_PE2, 0, 0)
#define PIN_PE2__PWML0			PINMUX_PIN(PIN_PE2, 1, 5)
#define PIN_PE2__FLEXCOM6_IO4		PINMUX_PIN(PIN_PE2, 2, 2)
#define PIN_PE2__TIOB2			PINMUX_PIN(PIN_PE2, 3, 3)
#define PIN_PE2__I2SMCC1_DOUT3		PINMUX_PIN(PIN_PE2, 4, 2)
#define PIN_PE2__ISC_FIELD		PINMUX_PIN(PIN_PE2, 5, 2)
#define PIN_PE2__G1_RX3			PINMUX_PIN(PIN_PE2, 7, 1)
#define PIN_PE3				131
#define PIN_PE3__GPIO			PINMUX_PIN(PIN_PE3, 0, 0)
#define PIN_PE3__PWMH0			PINMUX_PIN(PIN_PE3, 1, 5)
#define PIN_PE3__FLEXCOM0_IO0		PINMUX_PIN(PIN_PE3, 2, 4)
#define PIN_PE3__TCLK2			PINMUX_PIN(PIN_PE3, 3, 3)
#define PIN_PE3__I2SMCC1_DIN0		PINMUX_PIN(PIN_PE3, 4, 2)
#define PIN_PE3__ISC_PCK		PINMUX_PIN(PIN_PE3, 5, 2)
#define PIN_PE3__G1_RXCK		PINMUX_PIN(PIN_PE3, 7, 1)
#define PIN_PE4				132
#define PIN_PE4__GPIO			PINMUX_PIN(PIN_PE4, 0, 0)
#define PIN_PE4__PWML1			PINMUX_PIN(PIN_PE4, 1, 5)
#define PIN_PE4__FLEXCOM0_IO1		PINMUX_PIN(PIN_PE4, 2, 4)
#define PIN_PE4__TIOA3			PINMUX_PIN(PIN_PE4, 3, 3)
#define PIN_PE4__I2SMCC1_DIN1		PINMUX_PIN(PIN_PE4, 4, 2)
#define PIN_PE4__ISC_D8			PINMUX_PIN(PIN_PE4, 5, 2)
#define PIN_PE4__G1_TXER		PINMUX_PIN(PIN_PE4, 7, 1)
#define PIN_PE5				133
#define PIN_PE5__GPIO			PINMUX_PIN(PIN_PE5, 0, 0)
#define PIN_PE5__PWMH1			PINMUX_PIN(PIN_PE5, 1, 5)
#define PIN_PE5__FLEXCOM0_IO2		PINMUX_PIN(PIN_PE5, 2, 4)
#define PIN_PE5__TIOB3			PINMUX_PIN(PIN_PE5, 3, 3)
#define PIN_PE5__I2SMCC1_DIN2		PINMUX_PIN(PIN_PE5, 4, 2)
#define PIN_PE5__ISC_D9			PINMUX_PIN(PIN_PE5, 5, 2)
#define PIN_PE5__G1_COL			PINMUX_PIN(PIN_PE5, 7, 1)
#define PIN_PE6				134
#define PIN_PE6__GPIO			PINMUX_PIN(PIN_PE6, 0, 0)
#define PIN_PE6__PWML2			PINMUX_PIN(PIN_PE6, 1, 5)
#define PIN_PE6__FLEXCOM0_IO3		PINMUX_PIN(PIN_PE6, 2, 4)
#define PIN_PE6__TCLK3			PINMUX_PIN(PIN_PE6, 3, 3)
#define PIN_PE6__I2SMCC1_DIN3		PINMUX_PIN(PIN_PE6, 4, 2)
#define PIN_PE6__ISC_D10		PINMUX_PIN(PIN_PE6, 5, 2)
#define PIN_PE6__G1_CRS			PINMUX_PIN(PIN_PE6, 7, 1)
#define PIN_PE7				135
#define PIN_PE7__GPIO			PINMUX_PIN(PIN_PE7, 0, 0)
#define PIN_PE7__PWMH2			PINMUX_PIN(PIN_PE7, 1, 5)
#define PIN_PE7__FLEXCOM0_IO4		PINMUX_PIN(PIN_PE7, 2, 4)
#define PIN_PE7__TIOA4			PINMUX_PIN(PIN_PE7, 3, 3)
#define PIN_PE7__ISC_D11		PINMUX_PIN(PIN_PE7, 5, 2)
#define PIN_PE7__G1_TSUCOMP		PINMUX_PIN(PIN_PE7, 7, 1)

repo_name: angery/linux