code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the R-Car E2 (R8A77940) SoC
 *
 * Copyright (C) 2014 Renesas Electronics Corporation
 * Copyright (C) 2014 Ulrich Hecht
 */

#include <dt-bindings/clock/r8a7794-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/r8a7794-sysc.h>

/ {
	compatible = "renesas,r8a7794";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c7;
		spi0 = &qspi;
		vin0 = &vin0;
		vin1 = &vin1;
	};

	/*
	 * The external audio clocks are configured as 0 Hz fixed frequency
	 * clocks by default.
	 * Boards that provide audio clocks should override them.
	 */
	audio_clka: audio_clka {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};
	audio_clkb: audio_clkb {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};
	audio_clkc: audio_clkc {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	/* External CAN clock */
	can_clk: can {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clock-frequency = <1000000000>;
			clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
			power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
			enable-method = "renesas,apmu";
			next-level-cache = <&L2_CA7>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clock-frequency = <1000000000>;
			clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
			power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
			enable-method = "renesas,apmu";
			next-level-cache = <&L2_CA7>;
		};

		L2_CA7: cache-controller-0 {
			compatible = "cache";
			power-domains = <&sysc R8A7794_PD_CA7_SCU>;
			cache-unified;
			cache-level = <2>;
		};
	};

	/* External root clock */
	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	/* External SCIF clock */
	scif_clk: scif {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;

		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rwdt: watchdog@e6020000 {
			compatible = "renesas,r8a7794-wdt",
				     "renesas,rcar-gen2-wdt";
			reg = <0 0xe6020000 0 0x0c>;
			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 402>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 402>;
			status = "disabled";
		};

		gpio0: gpio@e6050000 {
			compatible = "renesas,gpio-r8a7794",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6050000 0 0x50>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 0 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 912>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 912>;
		};

		gpio1: gpio@e6051000 {
			compatible = "renesas,gpio-r8a7794",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6051000 0 0x50>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 32 26>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 911>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 911>;
		};

		gpio2: gpio@e6052000 {
			compatible = "renesas,gpio-r8a7794",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6052000 0 0x50>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 64 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 910>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 910>;
		};

		gpio3: gpio@e6053000 {
			compatible = "renesas,gpio-r8a7794",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6053000 0 0x50>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 96 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 909>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 909>;
		};

		gpio4: gpio@e6054000 {
			compatible = "renesas,gpio-r8a7794",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6054000 0 0x50>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 128 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 908>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 908>;
		};

		gpio5: gpio@e6055000 {
			compatible = "renesas,gpio-r8a7794",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6055000 0 0x50>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 160 28>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 907>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 907>;
		};

		gpio6: gpio@e6055400 {
			compatible = "renesas,gpio-r8a7794",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6055400 0 0x50>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 192 26>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 905>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 905>;
		};

		pfc: pinctrl@e6060000 {
			compatible = "renesas,pfc-r8a7794";
			reg = <0 0xe6060000 0 0x11c>;
		};

		cpg: clock-controller@e6150000 {
			compatible = "renesas,r8a7794-cpg-mssr";
			reg = <0 0xe6150000 0 0x1000>;
			clocks = <&extal_clk>, <&usb_extal_clk>;
			clock-names = "extal", "usb_extal";
			#clock-cells = <2>;
			#power-domain-cells = <0>;
			#reset-cells = <1>;
		};

		apmu@e6151000 {
			compatible = "renesas,r8a7794-apmu", "renesas,apmu";
			reg = <0 0xe6151000 0 0x188>;
			cpus = <&cpu0>, <&cpu1>;
		};

		rst: reset-controller@e6160000 {
			compatible = "renesas,r8a7794-rst";
			reg = <0 0xe6160000 0 0x0100>;
		};

		sysc: system-controller@e6180000 {
			compatible = "renesas,r8a7794-sysc";
			reg = <0 0xe6180000 0 0x0200>;
			#power-domain-cells = <1>;
		};

		irqc0: interrupt-controller@e61c0000 {
			compatible = "renesas,irqc-r8a7794", "renesas,irqc";
			#interrupt-cells = <2>;
			interrupt-controller;
			reg = <0 0xe61c0000 0 0x200>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 407>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 407>;
		};

		ipmmu_sy0: iommu@e6280000 {
			compatible = "renesas,ipmmu-r8a7794",
				     "renesas,ipmmu-vmsa";
			reg = <0 0xe6280000 0 0x1000>;
			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
			status = "disabled";
		};

		ipmmu_sy1: iommu@e6290000 {
			compatible = "renesas,ipmmu-r8a7794",
				     "renesas,ipmmu-vmsa";
			reg = <0 0xe6290000 0 0x1000>;
			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
			status = "disabled";
		};

		ipmmu_ds: iommu@e6740000 {
			compatible = "renesas,ipmmu-r8a7794",
				     "renesas,ipmmu-vmsa";
			reg = <0 0xe6740000 0 0x1000>;
			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
			status = "disabled";
		};

		ipmmu_mp: iommu@ec680000 {
			compatible = "renesas,ipmmu-r8a7794",
				     "renesas,ipmmu-vmsa";
			reg = <0 0xec680000 0 0x1000>;
			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
			status = "disabled";
		};

		ipmmu_mx: iommu@fe951000 {
			compatible = "renesas,ipmmu-r8a7794",
				     "renesas,ipmmu-vmsa";
			reg = <0 0xfe951000 0 0x1000>;
			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
			status = "disabled";
		};

		ipmmu_gp: iommu@e62a0000 {
			compatible = "renesas,ipmmu-r8a7794",
				     "renesas,ipmmu-vmsa";
			reg = <0 0xe62a0000 0 0x1000>;
			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
			status = "disabled";
		};

		icram0:	sram@e63a0000 {
			compatible = "mmio-sram";
			reg = <0 0xe63a0000 0 0x12000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0xe63a0000 0x12000>;
		};

		icram1:	sram@e63c0000 {
			compatible = "mmio-sram";
			reg = <0 0xe63c0000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0xe63c0000 0x1000>;

			smp-sram@0 {
				compatible = "renesas,smp-sram";
				reg = <0 0x100>;
			};
		};

		/* The memory map in the User's Manual maps the cores to
		 * bus numbers
		 */
		i2c0: i2c@e6508000 {
			compatible = "renesas,i2c-r8a7794",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6508000 0 0x40>;
			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 931>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 931>;
			#address-cells = <1>;
			#size-cells = <0>;
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c1: i2c@e6518000 {
			compatible = "renesas,i2c-r8a7794",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6518000 0 0x40>;
			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 930>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 930>;
			#address-cells = <1>;
			#size-cells = <0>;
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c2: i2c@e6530000 {
			compatible = "renesas,i2c-r8a7794",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6530000 0 0x40>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 929>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 929>;
			#address-cells = <1>;
			#size-cells = <0>;
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c3: i2c@e6540000 {
			compatible = "renesas,i2c-r8a7794",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6540000 0 0x40>;
			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 928>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 928>;
			#address-cells = <1>;
			#size-cells = <0>;
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c4: i2c@e6520000 {
			compatible = "renesas,i2c-r8a7794",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6520000 0 0x40>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 927>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 927>;
			#address-cells = <1>;
			#size-cells = <0>;
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c5: i2c@e6528000 {
			compatible = "renesas,i2c-r8a7794",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6528000 0 0x40>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 925>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 925>;
			#address-cells = <1>;
			#size-cells = <0>;
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c6: i2c@e6500000 {
			compatible = "renesas,iic-r8a7794",
				     "renesas,rcar-gen2-iic",
				     "renesas,rmobile-iic";
			reg = <0 0xe6500000 0 0x425>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 318>;
			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
			       <&dmac1 0x61>, <&dmac1 0x62>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 318>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c7: i2c@e6510000 {
			compatible = "renesas,iic-r8a7794",
				     "renesas,rcar-gen2-iic",
				     "renesas,rmobile-iic";
			reg = <0 0xe6510000 0 0x425>;
			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 323>;
			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
			       <&dmac1 0x65>, <&dmac1 0x66>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 323>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		hsusb: usb@e6590000 {
			compatible = "renesas,usbhs-r8a7794",
				     "renesas,rcar-gen2-usbhs";
			reg = <0 0xe6590000 0 0x100>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 704>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 704>;
			renesas,buswait = <4>;
			phys = <&usb0 1>;
			phy-names = "usb";
			status = "disabled";
		};

		usbphy: usb-phy-controller@e6590100 {
			compatible = "renesas,usb-phy-r8a7794",
				     "renesas,rcar-gen2-usb-phy";
			reg = <0 0xe6590100 0 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cpg CPG_MOD 704>;
			clock-names = "usbhs";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 704>;
			status = "disabled";

			usb0: usb-phy@0 {
				reg = <0>;
				#phy-cells = <1>;
			};
			usb2: usb-phy@2 {
				reg = <2>;
				#phy-cells = <1>;
			};
		};

		dmac0: dma-controller@e6700000 {
			compatible = "renesas,dmac-r8a7794",
				     "renesas,rcar-dmac";
			reg = <0 0xe6700000 0 0x20000>;
			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					  "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12", "ch13", "ch14";
			clocks = <&cpg CPG_MOD 219>;
			clock-names = "fck";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 219>;
			#dma-cells = <1>;
			dma-channels = <15>;
		};

		dmac1: dma-controller@e6720000 {
			compatible = "renesas,dmac-r8a7794",
				     "renesas,rcar-dmac";
			reg = <0 0xe6720000 0 0x20000>;
			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					  "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12", "ch13", "ch14";
			clocks = <&cpg CPG_MOD 218>;
			clock-names = "fck";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 218>;
			#dma-cells = <1>;
			dma-channels = <15>;
		};

		avb: ethernet@e6800000 {
			compatible = "renesas,etheravb-r8a7794",
				     "renesas,etheravb-rcar-gen2";
			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 812>;
			clock-names = "fck";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 812>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		qspi: spi@e6b10000 {
			compatible = "renesas,qspi-r8a7794", "renesas,qspi";
			reg = <0 0xe6b10000 0 0x2c>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 917>;
			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
			       <&dmac1 0x17>, <&dmac1 0x18>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 917>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		scifa0: serial@e6c40000 {
			compatible = "renesas,scifa-r8a7794",
				     "renesas,rcar-gen2-scifa", "renesas,scifa";
			reg = <0 0xe6c40000 0 64>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 204>;
			clock-names = "fck";
			dmas = <&dmac0 0x21>, <&dmac0 0x22>,
			       <&dmac1 0x21>, <&dmac1 0x22>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 204>;
			status = "disabled";
		};

		scifa1: serial@e6c50000 {
			compatible = "renesas,scifa-r8a7794",
				     "renesas,rcar-gen2-scifa", "renesas,scifa";
			reg = <0 0xe6c50000 0 64>;
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 203>;
			clock-names = "fck";
			dmas = <&dmac0 0x25>, <&dmac0 0x26>,
			       <&dmac1 0x25>, <&dmac1 0x26>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 203>;
			status = "disabled";
		};

		scifa2: serial@e6c60000 {
			compatible = "renesas,scifa-r8a7794",
				     "renesas,rcar-gen2-scifa", "renesas,scifa";
			reg = <0 0xe6c60000 0 64>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 202>;
			clock-names = "fck";
			dmas = <&dmac0 0x27>, <&dmac0 0x28>,
			       <&dmac1 0x27>, <&dmac1 0x28>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 202>;
			status = "disabled";
		};

		scifa3: serial@e6c70000 {
			compatible = "renesas,scifa-r8a7794",
				     "renesas,rcar-gen2-scifa", "renesas,scifa";
			reg = <0 0xe6c70000 0 64>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 1106>;
			clock-names = "fck";
			dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
			       <&dmac1 0x1b>, <&dmac1 0x1c>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 1106>;
			status = "disabled";
		};

		scifa4: serial@e6c78000 {
			compatible = "renesas,scifa-r8a7794",
				     "renesas,rcar-gen2-scifa", "renesas,scifa";
			reg = <0 0xe6c78000 0 64>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 1107>;
			clock-names = "fck";
			dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
			       <&dmac1 0x1f>, <&dmac1 0x20>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 1107>;
			status = "disabled";
		};

		scifa5: serial@e6c80000 {
			compatible = "renesas,scifa-r8a7794",
				     "renesas,rcar-gen2-scifa", "renesas,scifa";
			reg = <0 0xe6c80000 0 64>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 1108>;
			clock-names = "fck";
			dmas = <&dmac0 0x23>, <&dmac0 0x24>,
			       <&dmac1 0x23>, <&dmac1 0x24>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 1108>;
			status = "disabled";
		};

		scifb0: serial@e6c20000 {
			compatible = "renesas,scifb-r8a7794",
				     "renesas,rcar-gen2-scifb", "renesas,scifb";
			reg = <0 0xe6c20000 0 0x100>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 206>;
			clock-names = "fck";
			dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
			       <&dmac1 0x3d>, <&dmac1 0x3e>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 206>;
			status = "disabled";
		};

		scifb1: serial@e6c30000 {
			compatible = "renesas,scifb-r8a7794",
				     "renesas,rcar-gen2-scifb", "renesas,scifb";
			reg = <0 0xe6c30000 0 0x100>;
			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 207>;
			clock-names = "fck";
			dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
			       <&dmac1 0x19>, <&dmac1 0x1a>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 207>;
			status = "disabled";
		};

		scifb2: serial@e6ce0000 {
			compatible = "renesas,scifb-r8a7794",
				     "renesas,rcar-gen2-scifb", "renesas,scifb";
			reg = <0 0xe6ce0000 0 0x100>;
			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 216>;
			clock-names = "fck";
			dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
			       <&dmac1 0x1d>, <&dmac1 0x1e>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 216>;
			status = "disabled";
		};

		scif0: serial@e6e60000 {
			compatible = "renesas,scif-r8a7794",
				     "renesas,rcar-gen2-scif",
				     "renesas,scif";
			reg = <0 0xe6e60000 0 64>;
			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
			       <&dmac1 0x29>, <&dmac1 0x2a>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 721>;
			status = "disabled";
		};

		scif1: serial@e6e68000 {
			compatible = "renesas,scif-r8a7794",
				     "renesas,rcar-gen2-scif",
				     "renesas,scif";
			reg = <0 0xe6e68000 0 64>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
			       <&dmac1 0x2d>, <&dmac1 0x2e>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 720>;
			status = "disabled";
		};

		scif2: serial@e6e58000 {
			compatible = "renesas,scif-r8a7794",
				     "renesas,rcar-gen2-scif", "renesas,scif";
			reg = <0 0xe6e58000 0 64>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
			       <&dmac1 0x2b>, <&dmac1 0x2c>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 719>;
			status = "disabled";
		};

		scif3: serial@e6ea8000 {
			compatible = "renesas,scif-r8a7794",
				     "renesas,rcar-gen2-scif", "renesas,scif";
			reg = <0 0xe6ea8000 0 64>;
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
			       <&dmac1 0x2f>, <&dmac1 0x30>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 718>;
			status = "disabled";
		};

		scif4: serial@e6ee0000 {
			compatible = "renesas,scif-r8a7794",
				     "renesas,rcar-gen2-scif", "renesas,scif";
			reg = <0 0xe6ee0000 0 64>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
			       <&dmac1 0xfb>, <&dmac1 0xfc>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 715>;
			status = "disabled";
		};

		scif5: serial@e6ee8000 {
			compatible = "renesas,scif-r8a7794",
				     "renesas,rcar-gen2-scif", "renesas,scif";
			reg = <0 0xe6ee8000 0 64>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
			       <&dmac1 0xfd>, <&dmac1 0xfe>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 714>;
			status = "disabled";
		};

		hscif0: serial@e62c0000 {
			compatible = "renesas,hscif-r8a7794",
				     "renesas,rcar-gen2-hscif", "renesas,hscif";
			reg = <0 0xe62c0000 0 96>;
			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 717>,
				 <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
			       <&dmac1 0x39>, <&dmac1 0x3a>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 717>;
			status = "disabled";
		};

		hscif1: serial@e62c8000 {
			compatible = "renesas,hscif-r8a7794",
				     "renesas,rcar-gen2-hscif", "renesas,hscif";
			reg = <0 0xe62c8000 0 96>;
			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 716>,
				 <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
			       <&dmac1 0x4d>, <&dmac1 0x4e>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 716>;
			status = "disabled";
		};

		hscif2: serial@e62d0000 {
			compatible = "renesas,hscif-r8a7794",
				     "renesas,rcar-gen2-hscif", "renesas,hscif";
			reg = <0 0xe62d0000 0 96>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
			       <&dmac1 0x3b>, <&dmac1 0x3c>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 713>;
			status = "disabled";
		};

		can0: can@e6e80000 {
			compatible = "renesas,can-r8a7794",
				     "renesas,rcar-gen2-can";
			reg = <0 0xe6e80000 0 0x1000>;
			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
				 <&can_clk>;
			clock-names = "clkp1", "clkp2", "can_clk";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 916>;
			status = "disabled";
		};

		can1: can@e6e88000 {
			compatible = "renesas,can-r8a7794",
				     "renesas,rcar-gen2-can";
			reg = <0 0xe6e88000 0 0x1000>;
			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
				 <&can_clk>;
			clock-names = "clkp1", "clkp2", "can_clk";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 915>;
			status = "disabled";
		};

		vin0: video@e6ef0000 {
			compatible = "renesas,vin-r8a7794",
				     "renesas,rcar-gen2-vin";
			reg = <0 0xe6ef0000 0 0x1000>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 811>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 811>;
			status = "disabled";
		};

		vin1: video@e6ef1000 {
			compatible = "renesas,vin-r8a7794",
				     "renesas,rcar-gen2-vin";
			reg = <0 0xe6ef1000 0 0x1000>;
			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 810>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 810>;
			status = "disabled";
		};

		rcar_sound: sound@ec500000 {
			/*
			 * #sound-dai-cells is required
			 *
			 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
			 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
			 */
			compatible = "renesas,rcar_sound-r8a7794",
				     "renesas,rcar_sound-gen2";
			reg = <0 0xec500000 0 0x1000>, /* SCU */
			      <0 0xec5a0000 0 0x100>,  /* ADG */
			      <0 0xec540000 0 0x1000>, /* SSIU */
			      <0 0xec541000 0 0x280>,  /* SSI */
			      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

			clocks = <&cpg CPG_MOD 1005>,
				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
				 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
				 <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
				 <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
				 <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
				 <&cpg CPG_CORE R8A7794_CLK_M2>;
			clock-names = "ssi-all",
				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
				      "ssi.1", "ssi.0",
				      "src.6", "src.5", "src.4", "src.3",
				      "src.2", "src.1",
				      "ctu.0", "ctu.1",
				      "mix.0", "mix.1",
				      "dvc.0", "dvc.1",
				      "clk_a", "clk_b", "clk_c", "clk_i";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 1005>,
				 <&cpg 1006>, <&cpg 1007>,
				 <&cpg 1008>, <&cpg 1009>,
				 <&cpg 1010>, <&cpg 1011>,
				 <&cpg 1012>, <&cpg 1013>,
				 <&cpg 1014>, <&cpg 1015>;
			reset-names = "ssi-all",
				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
				      "ssi.1", "ssi.0";

			status = "disabled";

			rcar_sound,dvc {
				dvc0: dvc-0 {
					dmas = <&audma0 0xbc>;
					dma-names = "tx";
				};
				dvc1: dvc-1 {
					dmas = <&audma0 0xbe>;
					dma-names = "tx";
				};
			};

			rcar_sound,mix {
				mix0: mix-0 { };
				mix1: mix-1 { };
			};

			rcar_sound,ctu {
				ctu00: ctu-0 { };
				ctu01: ctu-1 { };
				ctu02: ctu-2 { };
				ctu03: ctu-3 { };
				ctu10: ctu-4 { };
				ctu11: ctu-5 { };
				ctu12: ctu-6 { };
				ctu13: ctu-7 { };
			};

			rcar_sound,src {
				src-0 {
					status = "disabled";
				};
				src1: src-1 {
					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x87>, <&audma0 0x9c>;
					dma-names = "rx", "tx";
				};
				src2: src-2 {
					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x89>, <&audma0 0x9e>;
					dma-names = "rx", "tx";
				};
				src3: src-3 {
					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x8b>, <&audma0 0xa0>;
					dma-names = "rx", "tx";
				};
				src4: src-4 {
					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x8d>, <&audma0 0xb0>;
					dma-names = "rx", "tx";
				};
				src5: src-5 {
					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x8f>, <&audma0 0xb2>;
					dma-names = "rx", "tx";
				};
				src6: src-6 {
					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x91>, <&audma0 0xb4>;
					dma-names = "rx", "tx";
				};
			};

			rcar_sound,ssi {
				ssi0: ssi-0 {
					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x01>, <&audma0 0x02>,
					       <&audma0 0x15>, <&audma0 0x16>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi1: ssi-1 {
					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x03>, <&audma0 0x04>,
					       <&audma0 0x49>, <&audma0 0x4a>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi2: ssi-2 {
					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x05>, <&audma0 0x06>,
					       <&audma0 0x63>, <&audma0 0x64>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi3: ssi-3 {
					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x07>, <&audma0 0x08>,
					       <&audma0 0x6f>, <&audma0 0x70>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi4: ssi-4 {
					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x09>, <&audma0 0x0a>,
					       <&audma0 0x71>, <&audma0 0x72>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi5: ssi-5 {
					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x0b>, <&audma0 0x0c>,
					       <&audma0 0x73>, <&audma0 0x74>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi6: ssi-6 {
					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x0d>, <&audma0 0x0e>,
					       <&audma0 0x75>, <&audma0 0x76>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi7: ssi-7 {
					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x0f>, <&audma0 0x10>,
					       <&audma0 0x79>, <&audma0 0x7a>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi8: ssi-8 {
					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x11>, <&audma0 0x12>,
					       <&audma0 0x7b>, <&audma0 0x7c>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi9: ssi-9 {
					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x13>, <&audma0 0x14>,
					       <&audma0 0x7d>, <&audma0 0x7e>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
			};
		};

		audma0: dma-controller@ec700000 {
			compatible = "renesas,dmac-r8a7794",
				     "renesas,rcar-dmac";
			reg = <0 0xec700000 0 0x10000>;
			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					  "ch0", "ch1", "ch2", "ch3", "ch4",
					  "ch5", "ch6", "ch7", "ch8", "ch9",
					  "ch10", "ch11",
					  "ch12";
			clocks = <&cpg CPG_MOD 502>;
			clock-names = "fck";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 502>;
			#dma-cells = <1>;
			dma-channels = <13>;
		};

		pci0: pci@ee090000 {
			compatible = "renesas,pci-r8a7794",
				     "renesas,pci-rcar-gen2";
			device_type = "pci";
			reg = <0 0xee090000 0 0xc00>,
			      <0 0xee080000 0 0x1100>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 703>;
			status = "disabled";

			bus-range = <0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
			interrupt-map-mask = <0xf800 0 0 0x7>;
			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
					<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
					<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

			usb@1,0 {
				reg = <0x800 0 0 0 0>;
				phys = <&usb0 0>;
				phy-names = "usb";
			};

			usb@2,0 {
				reg = <0x1000 0 0 0 0>;
				phys = <&usb0 0>;
				phy-names = "usb";
			};
		};

		pci1: pci@ee0d0000 {
			compatible = "renesas,pci-r8a7794",
				     "renesas,pci-rcar-gen2";
			device_type = "pci";
			reg = <0 0xee0d0000 0 0xc00>,
			      <0 0xee0c0000 0 0x1100>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 703>;
			status = "disabled";

			bus-range = <1 1>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
			interrupt-map-mask = <0xf800 0 0 0x7>;
			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
					<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
					<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

			usb@1,0 {
				reg = <0x10800 0 0 0 0>;
				phys = <&usb2 0>;
				phy-names = "usb";
			};

			usb@2,0 {
				reg = <0x11000 0 0 0 0>;
				phys = <&usb2 0>;
				phy-names = "usb";
			};
		};

		sdhi0: mmc@ee100000 {
			compatible = "renesas,sdhi-r8a7794",
				     "renesas,rcar-gen2-sdhi";
			reg = <0 0xee100000 0 0x328>;
			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 314>;
			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
			       <&dmac1 0xcd>, <&dmac1 0xce>;
			dma-names = "tx", "rx", "tx", "rx";
			max-frequency = <195000000>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 314>;
			status = "disabled";
		};

		sdhi1: mmc@ee140000 {
			compatible = "renesas,sdhi-r8a7794",
				     "renesas,rcar-gen2-sdhi";
			reg = <0 0xee140000 0 0x100>;
			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 312>;
			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
			       <&dmac1 0xc1>, <&dmac1 0xc2>;
			dma-names = "tx", "rx", "tx", "rx";
			max-frequency = <97500000>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 312>;
			status = "disabled";
		};

		sdhi2: mmc@ee160000 {
			compatible = "renesas,sdhi-r8a7794",
				     "renesas,rcar-gen2-sdhi";
			reg = <0 0xee160000 0 0x100>;
			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 311>;
			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
			       <&dmac1 0xd3>, <&dmac1 0xd4>;
			dma-names = "tx", "rx", "tx", "rx";
			max-frequency = <97500000>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 311>;
			status = "disabled";
		};

		mmcif0: mmc@ee200000 {
			compatible = "renesas,mmcif-r8a7794",
				     "renesas,sh-mmcif";
			reg = <0 0xee200000 0 0x80>;
			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 315>;
			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
			       <&dmac1 0xd1>, <&dmac1 0xd2>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 315>;
			reg-io-width = <4>;
			status = "disabled";
		};

		ether: ethernet@ee700000 {
			compatible = "renesas,ether-r8a7794",
				     "renesas,rcar-gen2-ether";
			reg = <0 0xee700000 0 0x400>;
			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 813>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 813>;
			phy-mode = "rmii";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		gic: interrupt-controller@f1001000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0 0xf1001000 0 0x1000>,
			      <0 0xf1002000 0 0x2000>,
			      <0 0xf1004000 0 0x2000>,
			      <0 0xf1006000 0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&cpg CPG_MOD 408>;
			clock-names = "clk";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 408>;
		};

		vsp@fe928000 {
			compatible = "renesas,vsp1";
			reg = <0 0xfe928000 0 0x8000>;
			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 131>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 131>;
		};

		vsp@fe930000 {
			compatible = "renesas,vsp1";
			reg = <0 0xfe930000 0 0x8000>;
			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 128>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 128>;
		};

		fdp1@fe940000 {
			compatible = "renesas,fdp1";
			reg = <0 0xfe940000 0 0x2400>;
			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 119>;
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 119>;
		};

		du: display@feb00000 {
			compatible = "renesas,du-r8a7794";
			reg = <0 0xfeb00000 0 0x40000>;
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
			clock-names = "du.0", "du.1";
			resets = <&cpg 724>;
			reset-names = "du.0";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					du_out_rgb0: endpoint {
					};
				};
				port@1 {
					reg = <1>;
					du_out_rgb1: endpoint {
					};
				};
			};
		};

		prr: chipid@ff000044 {
			compatible = "renesas,prr";
			reg = <0 0xff000044 0 4>;
		};

		cmt0: timer@ffca0000 {
			compatible = "renesas,r8a7794-cmt0",
				     "renesas,rcar-gen2-cmt0";
			reg = <0 0xffca0000 0 0x1004>;
			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 124>;
			clock-names = "fck";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 124>;

			status = "disabled";
		};

		cmt1: timer@e6130000 {
			compatible = "renesas,r8a7794-cmt1",
				     "renesas,rcar-gen2-cmt1";
			reg = <0 0xe6130000 0 0x1004>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 329>;
			clock-names = "fck";
			power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
			resets = <&cpg 329>;

			status = "disabled";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clock - can be overridden by the board */
	usb_extal_clk: usb_extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <48000000>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Common file for the AA121TD01 panel connected to Renesas R-Car boards
 *
 * Copyright (C) 2015 Renesas Electronics Corp.
 */

/ {
	panel {
		compatible = "mitsubishi,aa121td01", "panel-lvds";

		width-mm = <261>;
		height-mm = <163>;
		data-mapping = "jeida-18";

		panel-timing {
			/* 1280x800 @60Hz */
			clock-frequency = <71000000>;
			hactive = <1280>;
			vactive = <800>;
			hsync-len = <70>;
			hfront-porch = <20>;
			hback-porch = <70>;
			vsync-len = <5>;
			vfront-porch = <3>;
			vback-porch = <15>;
		};

		port {
			panel_in: endpoint {
				remote-endpoint = <&lvds_connector>;
			};
		};
	};
};

&lvds_connector {
	remote-endpoint = <&panel_in>;
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the RZN1D-DB Board
 *
 * Copyright (C) 2018 Renesas Electronics Europe Limited
 *
 */

/dts-v1/;

#include <dt-bindings/pinctrl/rzn1-pinctrl.h>
#include <dt-bindings/net/pcs-rzn1-miic.h>

#include "r9a06g032.dtsi"

/ {
	model = "RZN1D-DB Board";
	compatible = "renesas,rzn1d400-db", "renesas,r9a06g032";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};
};

&can0 {
	pinctrl-0 = <&pins_can0>;
	pinctrl-names = "default";

	/* Assuming CN10/CN11 are wired for CAN1 */
	status = "okay";
};

&can1 {
	pinctrl-0 = <&pins_can1>;
	pinctrl-names = "default";

	/* Please only enable can0 or can1, depending on CN10/CN11 */
	/* status = "okay"; */
};

&eth_miic {
	status = "okay";
	renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
};

&gmac2 {
	status = "okay";
	phy-mode = "gmii";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&mii_conv4 {
	renesas,miic-input = <MIIC_SWITCH_PORTB>;
	status = "okay";
};

&mii_conv5 {
	renesas,miic-input = <MIIC_SWITCH_PORTA>;
	status = "okay";
};

&pinctrl{
	pins_can0: pins_can0 {
		pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>,	/* CAN0_TXD */
			 <RZN1_PINMUX(163, RZN1_FUNC_CAN)>;	/* CAN0_RXD */
		drive-strength = <6>;
	};

	pins_can1: pins_can1 {
		pinmux = <RZN1_PINMUX(109, RZN1_FUNC_CAN)>,	/* CAN1_TXD */
			 <RZN1_PINMUX(110, RZN1_FUNC_CAN)>;	/* CAN1_RXD */
		drive-strength = <6>;
	};

	pins_eth3: pins_eth3 {
		pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
		drive-strength = <6>;
		bias-disable;
	};

	pins_eth4: pins_eth4 {
		pinmux = <RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
			 <RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
		drive-strength = <6>;
		bias-disable;
	};

	pins_mdio1: pins_mdio1 {
		pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>,
			 <RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>;
	};
};

&rtc0 {
	status = "okay";
};

&switch {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	pinctrl-names = "default";
	pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>;

	dsa,member = <0 0>;

	mdio {
		clock-frequency = <2500000>;

		#address-cells = <1>;
		#size-cells = <0>;

		switch0phy4: ethernet-phy@4 {
			reg = <4>;
			micrel,led-mode = <1>;
		};

		switch0phy5: ethernet-phy@5 {
			reg = <5>;
			micrel,led-mode = <1>;
		};
	};
};

&switch_port0 {
	label = "lan0";
	phy-mode = "mii";
	phy-handle = <&switch0phy5>;
	status = "okay";
};

&switch_port1 {
	label = "lan1";
	phy-mode = "mii";
	phy-handle = <&switch0phy4>;
	status = "okay";
};

&switch_port4 {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&wdt0 {
	timeout-sec = <60>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
 *
 * Copyright (C) 2018 Renesas Electronics Europe Limited
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>

/ {
	compatible = "renesas,r9a06g032";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
			enable-method = "renesas,r9a06g032-smp";
			cpu-release-addr = <0 0x4000c204>;
		};
	};

	ext_jtag_clk: extjtagclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	ext_mclk: extmclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <40000000>;
	};

	ext_rgmii_ref: extrgmiiref {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	ext_rtc_clk: extrtcclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;
		ranges;

		rtc0: rtc@40006000 {
			compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
			reg = <0x40006000 0x1000>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "alarm", "timer", "pps";
			clocks = <&sysctrl R9A06G032_HCLK_RTC>;
			clock-names = "hclk";
			power-domains = <&sysctrl>;
			status = "disabled";
		};

		wdt0: watchdog@40008000 {
			compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
			reg = <0x40008000 0x1000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
			clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
			status = "disabled";
		};

		wdt1: watchdog@40009000 {
			compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
			reg = <0x40009000 0x1000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
			clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
			status = "disabled";
		};

		sysctrl: system-controller@4000c000 {
			compatible = "renesas,r9a06g032-sysctrl";
			reg = <0x4000c000 0x1000>;
			status = "okay";
			#clock-cells = <1>;
			#power-domain-cells = <0>;

			clocks = <&ext_mclk>, <&ext_rtc_clk>,
					<&ext_jtag_clk>, <&ext_rgmii_ref>;
			clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
			#address-cells = <1>;
			#size-cells = <1>;

			dmamux: dma-router@a0 {
				compatible = "renesas,rzn1-dmamux";
				reg = <0xa0 4>;
				#dma-cells = <6>;
				dma-requests = <32>;
				dma-masters = <&dma0 &dma1>;
			};
		};

		pci_usb: pci@40030000 {
			compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
			device_type = "pci";
			clocks = <&sysctrl R9A06G032_HCLK_USBH>,
				 <&sysctrl R9A06G032_HCLK_USBPM>,
				 <&sysctrl R9A06G032_CLK_PCI_USB>;
			clock-names = "hclkh", "hclkpm", "pciclk";
			power-domains = <&sysctrl>;
			reg = <0x40030000 0xc00>,
			      <0x40020000 0x1100>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";

			bus-range = <0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
			/* Should map all possible DDR as inbound ranges, but
			 * the IP only supports a 256MB, 512MB, or 1GB window.
			 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
			 */
			dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
			interrupt-map-mask = <0xf800 0 0 0x7>;
			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
					 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
					 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;

			usb@1,0 {
				reg = <0x800 0 0 0 0>;
				phys = <&usbphy>;
				phy-names = "usb";
			};

			usb@2,0 {
				reg = <0x1000 0 0 0 0>;
				phys = <&usbphy>;
				phy-names = "usb";
			};
		};

		uart0: serial@40060000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40060000 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart1: serial@40061000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40061000 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart2: serial@40062000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40062000 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart3: serial@50000000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50000000 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
			clock-names = "baudclk", "apb_pclk";
			dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart4: serial@50001000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50001000 0x400>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
			clock-names = "baudclk", "apb_pclk";
			dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart5: serial@50002000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50002000 0x400>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
			clock-names = "baudclk", "apb_pclk";
			dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart6: serial@50003000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50003000 0x400>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
			clock-names = "baudclk", "apb_pclk";
			dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart7: serial@50004000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50004000 0x400>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
			clock-names = "baudclk", "apb_pclk";
			dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		pinctrl: pinctrl@40067000 {
			compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
			reg = <0x40067000 0x1000>, <0x51000000 0x480>;
			clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
			clock-names = "bus";
			status = "okay";
		};

		nand_controller: nand-controller@40102000 {
			compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
			reg = <0x40102000 0x2000>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
			clock-names = "hclk", "eclk";
			power-domains = <&sysctrl>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		dma0: dma-controller@40104000 {
			compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
			reg = <0x40104000 0x1000>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "hclk";
			clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
			dma-channels = <8>;
			dma-requests = <16>;
			dma-masters = <1>;
			#dma-cells = <3>;
			block_size = <0xfff>;
			data-width = <8>;
		};

		dma1: dma-controller@40105000 {
			compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
			reg = <0x40105000 0x1000>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "hclk";
			clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
			dma-channels = <8>;
			dma-requests = <16>;
			dma-masters = <1>;
			#dma-cells = <3>;
			block_size = <0xfff>;
			data-width = <8>;
		};

		gmac2: ethernet@44002000 {
			compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
			reg = <0x44002000 0x2000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
			clocks = <&sysctrl R9A06G032_HCLK_GMAC1>;
			clock-names = "stmmaceth";
			power-domains = <&sysctrl>;
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <2048>;
			rx-fifo-depth = <4096>;
			status = "disabled";
		};

		eth_miic: eth-miic@44030000 {
			compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x44030000 0x10000>;
			clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
				 <&sysctrl R9A06G032_CLK_RGMII_REF>,
				 <&sysctrl R9A06G032_CLK_RMII_REF>,
				 <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
			clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
			power-domains = <&sysctrl>;
			status = "disabled";

			mii_conv1: mii-conv@1 {
				reg = <1>;
				status = "disabled";
			};

			mii_conv2: mii-conv@2 {
				reg = <2>;
				status = "disabled";
			};

			mii_conv3: mii-conv@3 {
				reg = <3>;
				status = "disabled";
			};

			mii_conv4: mii-conv@4 {
				reg = <4>;
				status = "disabled";
			};

			mii_conv5: mii-conv@5 {
				reg = <5>;
				status = "disabled";
			};
		};

		switch: switch@44050000 {
			compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
			reg = <0x44050000 0x10000>;
			clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
				 <&sysctrl R9A06G032_CLK_SWITCH>;
			clock-names = "hclk", "clk";
			power-domains = <&sysctrl>;
			status = "disabled";

			ethernet-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				switch_port0: port@0 {
					reg = <0>;
					pcs-handle = <&mii_conv5>;
					status = "disabled";
				};

				switch_port1: port@1 {
					reg = <1>;
					pcs-handle = <&mii_conv4>;
					status = "disabled";
				};

				switch_port2: port@2 {
					reg = <2>;
					pcs-handle = <&mii_conv3>;
					status = "disabled";
				};

				switch_port3: port@3 {
					reg = <3>;
					pcs-handle = <&mii_conv2>;
					status = "disabled";
				};

				switch_port4: port@4 {
					reg = <4>;
					ethernet = <&gmac2>;
					label = "cpu";
					phy-mode = "internal";
					status = "disabled";
					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};
			};
		};

		gic: interrupt-controller@44101000 {
			compatible = "arm,gic-400", "arm,cortex-a7-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x44101000 0x1000>, /* Distributer */
			      <0x44102000 0x2000>, /* CPU interface */
			      <0x44104000 0x2000>, /* Virt interface control */
			      <0x44106000 0x2000>; /* Virt CPU interface */
			interrupts =
				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		can0: can@52104000 {
			compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000";
			reg = <0x52104000 0x800>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
			power-domains = <&sysctrl>;
			status = "disabled";
		};

		can1: can@52105000 {
			compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
			reg = <0x52105000 0x800>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
			power-domains = <&sysctrl>;
			status = "disabled";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		arm,cpu-registers-not-fw-configured;
		always-on;
		interrupts =
			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	usbphy: usb-phy {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
		status = "disabled";
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 Andreas Färber
 * Copyright (c) 2018 Manivannan Sadhasivam
 */

/dts-v1/;

#include "rda8810pl.dtsi"

/ {
	compatible = "xunlong,orangepi-2g-iot", "rda,8810pl";
	model = "Orange Pi 2G-IoT";

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
	};

	chosen {
		stdout-path = "serial2:921600n8";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;
	};

	uart_clk: uart-clk {
		compatible = "fixed-clock";
		clock-frequency = <921600>;
		#clock-cells = <0>;
	};
};

&uart1 {
	status = "okay";
	clocks = <&uart_clk>;
};

&uart2 {
	status = "okay";
	clocks = <&uart_clk>;
};

&uart3 {
	status = "okay";
	clocks = <&uart_clk>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 Andreas Färber
 * Copyright (c) 2018 Manivannan Sadhasivam
 */

/dts-v1/;

#include "rda8810pl.dtsi"

/ {
	compatible = "xunlong,orangepi-i96", "rda,8810pl";
	model = "Orange Pi i96";

	aliases {
		serial0 = &uart2;
		serial1 = &uart1;
		serial2 = &uart3;
	};

	chosen {
		stdout-path = "serial2:921600n8";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;
	};

	uart_clk: uart-clk {
		compatible = "fixed-clock";
		clock-frequency = <921600>;
		#clock-cells = <0>;
	};
};

&uart1 {
	status = "okay";
	clocks = <&uart_clk>;
};

&uart2 {
	status = "okay";
	clocks = <&uart_clk>;
};

&uart3 {
	status = "okay";
	clocks = <&uart_clk>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * RDA8810PL SoC
 *
 * Copyright (c) 2017 Andreas Färber
 * Copyright (c) 2018 Manivannan Sadhasivam
 */

#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "rda,8810pl";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			reg = <0x0>;
		};
	};

	sram@100000 {
		compatible = "mmio-sram";
		reg = <0x100000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
	};

	modem@10000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x10000000 0xfffffff>;

		gpioc@1a08000 {
			compatible = "rda,8810pl-gpio";
			reg = <0x1a08000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <32>;
		};
	};

	apb@20800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x20800000 0x100000>;

		intc: interrupt-controller@0 {
			compatible = "rda,8810pl-intc";
			reg = <0x0 0x1000>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	apb@20900000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x20900000 0x100000>;

		timer@10000 {
			compatible = "rda,8810pl-timer";
			reg = <0x10000 0x1000>;
			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>,
				     <17 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hwtimer", "ostimer";
		};

		gpioa@30000 {
			compatible = "rda,8810pl-gpio";
			reg = <0x30000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <32>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
		};

		gpiob@31000 {
			compatible = "rda,8810pl-gpio";
			reg = <0x31000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <32>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
		};

		gpiod@32000 {
			compatible = "rda,8810pl-gpio";
			reg = <0x32000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios = <32>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	apb@20a00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x20a00000 0x100000>;

		uart1: serial@0 {
			compatible = "rda,8810pl-uart";
			reg = <0x0 0x1000>;
			interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart2: serial@10000 {
			compatible = "rda,8810pl-uart";
			reg = <0x10000 0x1000>;
			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart3: serial@90000 {
			compatible = "rda,8810pl-uart";
			reg = <0x90000 0x1000>;
			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};
	};

	l2: cache-controller@21100000 {
		compatible = "arm,pl310-cache";
		reg = <0x21100000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/dts-v1/;

#include "rk3036.dtsi"

/ {
	model = "Rockchip RK3036 Evaluation board";
	compatible = "rockchip,rk3036-evb", "rockchip,rk3036";

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x40000000>;
	};
};

&emac {
	phy = <&phy0>;
	phy-reset-duration = <10>; /* millisecond */
	phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
	pinctrl-names = "default";
	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		phy0: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

&i2c1 {
	status = "okay";

	hym8563: rtc@51 {
		compatible = "haoyu,hym8563";
		reg = <0x51>;
		#clock-cells = <0>;
		clock-output-names = "xin32k";
	};
};

&uart2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/dts-v1/;

#include "rk3036.dtsi"

/ {
	model = "Rockchip RK3036 KylinBoard";
	compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x20000000>;
	};

	leds: gpio-leds {
		compatible = "gpio-leds";

		work_led: led-0 {
			gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
			label = "kylin:red:led";
			pinctrl-names = "default";
			pinctrl-0 = <&led_ctl>;
		};
	};

	sdio_pwrseq: sdio-pwrseq {
		compatible = "mmc-pwrseq-simple";
		pinctrl-names = "default";
		pinctrl-0 = <&bt_wake_h>;

		/*
		 * On the module itself this is one of these (depending
		 * on the actual card populated):
		 * - SDIO_RESET_L_WL_REG_ON
		 * - SDIO_RESET_L_WL_RST
		 * - SDIO_RESET_L_BT_EN
		 */
		reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
			      <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>, /* WL_RST */
			      <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; /* BT_EN */
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,name = "rockchip,rt5616-codec";
		simple-audio-card,mclk-fs = <512>;
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack";
		simple-audio-card,routing =
			"MIC1", "Microphone Jack",
			"MIC2", "Microphone Jack",
			"Microphone Jack", "micbias1",
			"Headphone Jack", "HPOL",
			"Headphone Jack", "HPOR";

		simple-audio-card,cpu {
			sound-dai = <&i2s>;
		};

		simple-audio-card,codec {
			sound-dai = <&rt5616>;
		};
	};

	vcc_sys: vsys-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc_sys";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&acodec {
	status = "okay";
};

&emac {
	phy = <&phy0>;
	phy-reset-duration = <10>; /* millisecond */
	phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
	pinctrl-names = "default";
	pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		phy0: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

&emmc {
	status = "okay";
};

&gpu {
	mali-supply = <&vdd_gpu>;
	status = "okay";
};

&hdmi {
	status = "okay";
};

&i2c1 {
	clock-frequency = <400000>;

	status = "okay";

	rk808: pmic@1b {
		compatible = "rockchip,rk808";
		reg = <0x1b>;
		interrupt-parent = <&gpio2>;
		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pmic_int &global_pwroff>;
		rockchip,system-power-controller;
		wakeup-source;
		#clock-cells = <1>;
		clock-output-names = "xin32k", "rk808-clkout2";

		vcc1-supply = <&vcc_sys>;
		vcc2-supply = <&vcc_sys>;
		vcc3-supply = <&vcc_sys>;
		vcc4-supply = <&vcc_sys>;
		vcc6-supply = <&vcc_sys>;
		vcc7-supply = <&vcc_sys>;
		vcc8-supply = <&vcc_18>;
		vcc9-supply = <&vcc_io>;
		vcc10-supply = <&vcc_io>;
		vcc11-supply = <&vcc_sys>;
		vcc12-supply = <&vcc_io>;
		vddio-supply = <&vccio_pmu>;

		regulators {
			vdd_cpu: DCDC_REG1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <1350000>;
				regulator-name = "vdd_arm";
				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdd_gpu: DCDC_REG2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-name = "vdd_gpu";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1000000>;
				};
			};

			vcc_ddr: DCDC_REG3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-name = "vcc_ddr";
				regulator-state-mem {
					regulator-on-in-suspend;
				};
			};

			vcc_io: DCDC_REG4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vcc_io";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <3300000>;
				};
			};

			vccio_pmu: LDO_REG1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vccio_pmu";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <3300000>;
				};
			};

			vcc_tp: LDO_REG2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vcc_tp";
				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdd_10: LDO_REG3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-name = "vdd_10";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1000000>;
				};
			};

			vcc18_lcd: LDO_REG4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcc18_lcd";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1800000>;
				};
			};

			vccio_sd: LDO_REG5 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vccio_sd";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <3300000>;
				};
			};

			vout5: LDO_REG6 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <2500000>;
				regulator-name = "vout5";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1800000>;
				};
			};

			vcc_18: LDO_REG7 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcc_18";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1800000>;
				};
			};

			vcca_codec: LDO_REG8 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcca_codec";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1800000>;
				};
			};

			vcc_wl: SWITCH_REG1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-name = "vcc_wl";
				regulator-state-mem {
					regulator-on-in-suspend;
				};
			};

			vcc_lcd: SWITCH_REG2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-name = "vcc_lcd";
				regulator-state-mem {
					regulator-on-in-suspend;
				};
			};
		};
	};
};

&i2c2 {
	status = "okay";

	rt5616: rt5616@1b {
		compatible = "rt5616";
		reg = <0x1b>;
		clocks = <&cru SCLK_I2S_OUT>;
		clock-names = "mclk";
		#sound-dai-cells = <0>;
	};
};

&i2s {
	status = "okay";
};

&sdio {
	status = "okay";

	bus-width = <4>;
	cap-sd-highspeed;
	cap-sdio-irq;
	rockchip,default-sample-phase = <90>;
	keep-power-in-suspend;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
};

&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	card-detect-delay = <200>;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
};

&uart0 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&usb_host {
	status = "okay";
};

&usb_otg {
	status = "okay";
};

&vop {
	status = "okay";
};

&vop_mmu {
	status = "okay";
};

&pinctrl {
	leds {
		led_ctl: led-ctl {
			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	pmic {
		pmic_int: pmic-int {
			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_default>;
		};
	};

	sdio {
		bt_wake_h: bt-wake-h {
			rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_default>;
		};
	};

	sdmmc {
		sdmmc_pwr: sdmmc-pwr {
			rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	suspend {
		global_pwroff: global-pwroff {
			rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3036-cru.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/power/rk3036-power.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "rockchip,rk3036";

	interrupt-parent = <&gic>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		mshc0 = &emmc;
		mshc1 = &sdmmc;
		mshc2 = &sdio;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		spi = &spi;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3036-smp";

		cpu0: cpu@f00 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf00>;
			resets = <&cru SRST_CORE0>;
			operating-points = <
				/* KHz    uV */
				 816000 1000000
			>;
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
		};

		cpu1: cpu@f01 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf01>;
			resets = <&cru SRST_CORE1>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <&vop_out>;
	};

	timer {
		compatible = "arm,armv7-timer";
		arm,cpu-registers-not-fw-configured;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	xin24m: oscillator {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	bus_intmem: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x2000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x2000>;

		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x00 0x10>;
		};
	};

	gpu: gpu@10090000 {
		compatible = "rockchip,rk3036-mali", "arm,mali-400";
		reg = <0x10090000 0x10000>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "gp",
				  "gpmmu",
				  "pp0",
				  "ppmmu0";
		assigned-clocks = <&cru SCLK_GPU>;
		assigned-clock-rates = <100000000>;
		clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
		clock-names = "bus", "core";
		power-domains = <&power RK3036_PD_GPU>;
		resets = <&cru SRST_GPU>;
		status = "disabled";
	};

	vpu: video-codec@10108000 {
		compatible = "rockchip,rk3036-vpu";
		reg = <0x10108000 0x800>;
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vdpu";
		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
		clock-names = "aclk", "hclk";
		iommus = <&vpu_mmu>;
		power-domains = <&power RK3036_PD_VPU>;
	};

	vpu_mmu: iommu@10108800 {
		compatible = "rockchip,iommu";
		reg = <0x10108800 0x100>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3036_PD_VPU>;
		#iommu-cells = <0>;
	};

	vop: vop@10118000 {
		compatible = "rockchip,rk3036-vop";
		reg = <0x10118000 0x19c>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
		reset-names = "axi", "ahb", "dclk";
		iommus = <&vop_mmu>;
		power-domains = <&power RK3036_PD_VIO>;
		status = "disabled";

		vop_out: port {
			#address-cells = <1>;
			#size-cells = <0>;
			vop_out_hdmi: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&hdmi_in_vop>;
			};
		};
	};

	vop_mmu: iommu@10118300 {
		compatible = "rockchip,iommu";
		reg = <0x10118300 0x100>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3036_PD_VIO>;
		#iommu-cells = <0>;
		status = "disabled";
	};

	qos_gpu: qos@1012d000 {
		compatible = "rockchip,rk3036-qos", "syscon";
		reg = <0x1012d000 0x20>;
	};

	qos_vpu: qos@1012e000 {
		compatible = "rockchip,rk3036-qos", "syscon";
		reg = <0x1012e000 0x20>;
	};

	qos_vio: qos@1012f000 {
		compatible = "rockchip,rk3036-qos", "syscon";
		reg = <0x1012f000 0x20>;
	};

	gic: interrupt-controller@10139000 {
		compatible = "arm,gic-400";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <0>;

		reg = <0x10139000 0x1000>,
		      <0x1013a000 0x2000>,
		      <0x1013c000 0x2000>,
		      <0x1013e000 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	usb_otg: usb@10180000 {
		compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
				"snps,dwc2";
		reg = <0x10180000 0x40000>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_OTG0>;
		clock-names = "otg";
		dr_mode = "otg";
		g-np-tx-fifo-size = <16>;
		g-rx-fifo-size = <275>;
		g-tx-fifo-size = <256 128 128 64 64 32>;
		status = "disabled";
	};

	usb_host: usb@101c0000 {
		compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
				"snps,dwc2";
		reg = <0x101c0000 0x40000>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_OTG1>;
		clock-names = "otg";
		dr_mode = "host";
		status = "disabled";
	};

	emac: ethernet@10200000 {
		compatible = "rockchip,rk3036-emac";
		reg = <0x10200000 0x4000>;
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,grf = <&grf>;
		clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
		clock-names = "hclk", "macref", "macclk";
		/*
		 * Fix the emac parent clock is DPLL instead of APLL.
		 * since that will cause some unstable things if the cpufreq
		 * is working. (e.g: the accurate 50MHz what mac_ref need)
		 */
		assigned-clocks = <&cru SCLK_MACPLL>;
		assigned-clock-parents = <&cru PLL_DPLL>;
		max-speed = <100>;
		phy-mode = "rmii";
		status = "disabled";
	};

	sdmmc: mmc@10214000 {
		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x10214000 0x4000>;
		clock-frequency = <37500000>;
		max-frequency = <37500000>;
		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
		clock-names = "biu", "ciu";
		fifo-depth = <0x100>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		resets = <&cru SRST_MMC0>;
		reset-names = "reset";
		status = "disabled";
	};

	sdio: mmc@10218000 {
		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x10218000 0x4000>;
		max-frequency = <37500000>;
		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		resets = <&cru SRST_SDIO>;
		reset-names = "reset";
		status = "disabled";
	};

	emmc: mmc@1021c000 {
		compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x1021c000 0x4000>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		bus-width = <8>;
		cap-mmc-highspeed;
		clock-frequency = <37500000>;
		max-frequency = <37500000>;
		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		rockchip,default-sample-phase = <158>;
		disable-wp;
		dmas = <&pdma 12>;
		dma-names = "rx-tx";
		fifo-depth = <0x100>;
		mmc-ddr-1_8v;
		non-removable;
		pinctrl-names = "default";
		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
		resets = <&cru SRST_EMMC>;
		reset-names = "reset";
		status = "disabled";
	};

	i2s: i2s@10220000 {
		compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
		reg = <0x10220000 0x4000>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
		dmas = <&pdma 0>, <&pdma 1>;
		dma-names = "tx", "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&i2s_bus>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	nfc: nand-controller@10500000 {
		compatible = "rockchip,rk3036-nfc",
			     "rockchip,rk2928-nfc";
		reg = <0x10500000 0x4000>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
		clock-names = "ahb", "nfc";
		assigned-clocks = <&cru SCLK_NANDC>;
		assigned-clock-rates = <150000000>;
		pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
			     &flash_rdn &flash_rdy &flash_wrn>;
		pinctrl-names = "default";
		status = "disabled";
	};

	cru: clock-controller@20000000 {
		compatible = "rockchip,rk3036-cru";
		reg = <0x20000000 0x1000>;
		clocks = <&xin24m>;
		clock-names = "xin24m";
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		assigned-clocks = <&cru PLL_GPLL>;
		assigned-clock-rates = <594000000>;
	};

	grf: syscon@20008000 {
		compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
		reg = <0x20008000 0x1000>;

		power: power-controller {
			compatible = "rockchip,rk3036-power-controller";
			#power-domain-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			power-domain@RK3036_PD_VIO {
				reg = <RK3036_PD_VIO>;
				clocks = <&cru ACLK_LCDC>,
					 <&cru HCLK_LCDC>,
					 <&cru SCLK_LCDC>;
				pm_qos = <&qos_vio>;
				#power-domain-cells = <0>;
			};

			power-domain@RK3036_PD_VPU {
				reg = <RK3036_PD_VPU>;
				clocks = <&cru ACLK_VCODEC>,
					 <&cru HCLK_VCODEC>;
				pm_qos = <&qos_vpu>;
				#power-domain-cells = <0>;
			};

			power-domain@RK3036_PD_GPU {
				reg = <RK3036_PD_GPU>;
				clocks = <&cru SCLK_GPU>;
				pm_qos = <&qos_gpu>;
				#power-domain-cells = <0>;
			};
		};

		reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x1d8>;
			mode-normal = <BOOT_NORMAL>;
			mode-recovery = <BOOT_RECOVERY>;
			mode-bootloader = <BOOT_FASTBOOT>;
			mode-loader = <BOOT_BL_DOWNLOAD>;
		};
	};

	acodec: acodec-ana@20030000 {
		compatible = "rk3036-codec";
		reg = <0x20030000 0x4000>;
		rockchip,grf = <&grf>;
		clock-names = "acodec_pclk";
		clocks = <&cru PCLK_ACODEC>;
		status = "disabled";
	};

	hdmi: hdmi@20034000 {
		compatible = "rockchip,rk3036-inno-hdmi";
		reg = <0x20034000 0x4000>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru  PCLK_HDMI>;
		clock-names = "pclk";
		rockchip,grf = <&grf>;
		pinctrl-names = "default";
		pinctrl-0 = <&hdmi_ctl>;
		status = "disabled";

		hdmi_in: port {
			#address-cells = <1>;
			#size-cells = <0>;
			hdmi_in_vop: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&vop_out_hdmi>;
			};
		};
	};

	timer: timer@20044000 {
		compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
		reg = <0x20044000 0x20>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_TIMER>, <&xin24m>;
		clock-names = "pclk", "timer";
	};

	pwm0: pwm@20050000 {
		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
		reg = <0x20050000 0x10>;
		#pwm-cells = <3>;
		clocks = <&cru PCLK_PWM>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm0_pin>;
		status = "disabled";
	};

	pwm1: pwm@20050010 {
		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
		reg = <0x20050010 0x10>;
		#pwm-cells = <3>;
		clocks = <&cru PCLK_PWM>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm1_pin>;
		status = "disabled";
	};

	pwm2: pwm@20050020 {
		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
		reg = <0x20050020 0x10>;
		#pwm-cells = <3>;
		clocks = <&cru PCLK_PWM>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm2_pin>;
		status = "disabled";
	};

	pwm3: pwm@20050030 {
		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
		reg = <0x20050030 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm3_pin>;
		status = "disabled";
	};

	i2c1: i2c@20056000 {
		compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
		reg = <0x20056000 0x1000>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C1>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_xfer>;
		status = "disabled";
	};

	i2c2: i2c@2005a000 {
		compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
		reg = <0x2005a000 0x1000>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C2>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2_xfer>;
		status = "disabled";
	};

	uart0: serial@20060000 {
		compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
		reg = <0x20060000 0x100>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
		status = "disabled";
	};

	uart1: serial@20064000 {
		compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
		reg = <0x20064000 0x100>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart1_xfer>;
		status = "disabled";
	};

	uart2: serial@20068000 {
		compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
		reg = <0x20068000 0x100>;
		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
		status = "disabled";
	};

	i2c0: i2c@20072000 {
		compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
		reg = <0x20072000 0x1000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		status = "disabled";
	};

	spi: spi@20074000 {
		compatible = "rockchip,rockchip-spi";
		reg = <0x20074000 0x1000>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
		clock-names = "apb-pclk","spi_pclk";
		dmas = <&pdma 8>, <&pdma 9>;
		dma-names = "tx", "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	pdma: dma-controller@20078000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x20078000 0x4000>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		arm,pl330-broken-no-flushp;
		arm,pl330-periph-burst;
		clocks = <&cru ACLK_DMAC2>;
		clock-names = "apb_pclk";
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3036-pinctrl";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio@2007c000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2007c000 0x100>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@20080000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20080000 0x100>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@20084000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20084000 0x100>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_default: pcfg-pull-default {
			bias-pull-pin-default;
		};

		pcfg_pull_none: pcfg-pull-none {
			bias-disable;
		};

		pwm0 {
			pwm0_pin: pwm0-pin {
				rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_pin: pwm1-pin {
				rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_pin: pwm2-pin {
				rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_pin: pwm3-pin {
				rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
			};
		};

		sdmmc {
			sdmmc_clk: sdmmc-clk {
				rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
			};

			sdmmc_cmd: sdmmc-cmd {
				rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
			};

			sdmmc_cd: sdmmc-cd {
				rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
			};

			sdmmc_bus1: sdmmc-bus1 {
				rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
			};

			sdmmc_bus4: sdmmc-bus4 {
				rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
						<1 RK_PC3 1 &pcfg_pull_default>,
						<1 RK_PC4 1 &pcfg_pull_default>,
						<1 RK_PC5 1 &pcfg_pull_default>;
			};
		};

		sdio {
			sdio_bus1: sdio-bus1 {
				rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
			};

			sdio_bus4: sdio-bus4 {
				rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
						<0 RK_PB4 1 &pcfg_pull_default>,
						<0 RK_PB5 1 &pcfg_pull_default>,
						<0 RK_PB6 1 &pcfg_pull_default>;
			};

			sdio_cmd: sdio-cmd {
				rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
			};

			sdio_clk: sdio-clk {
				rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
			};
		};

		emmc {
			/*
			 * We run eMMC at max speed; bump up drive strength.
			 * We also have external pulls, so disable the internal ones.
			 */
			emmc_clk: emmc-clk {
				rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
			};

			emmc_bus8: emmc-bus8 {
				rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
						<1 RK_PD1 2 &pcfg_pull_default>,
						<1 RK_PD2 2 &pcfg_pull_default>,
						<1 RK_PD3 2 &pcfg_pull_default>,
						<1 RK_PD4 2 &pcfg_pull_default>,
						<1 RK_PD5 2 &pcfg_pull_default>,
						<1 RK_PD6 2 &pcfg_pull_default>,
						<1 RK_PD7 2 &pcfg_pull_default>;
			};
		};

		nfc {
			flash_ale: flash-ale {
				rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>;
			};

			flash_bus8: flash-bus8 {
				rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>,
						<1 RK_PD1 1 &pcfg_pull_default>,
						<1 RK_PD2 1 &pcfg_pull_default>,
						<1 RK_PD3 1 &pcfg_pull_default>,
						<1 RK_PD4 1 &pcfg_pull_default>,
						<1 RK_PD5 1 &pcfg_pull_default>,
						<1 RK_PD6 1 &pcfg_pull_default>,
						<1 RK_PD7 1 &pcfg_pull_default>;
			};

			flash_cle: flash-cle {
				rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>;
			};

			flash_csn0: flash-csn0 {
				rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>;
			};

			flash_rdn: flash-rdn {
				rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>;
			};

			flash_rdy: flash-rdy {
				rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>;
			};

			flash_wrn: flash-wrn {
				rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>;
			};
		};

		emac {
			emac_xfer: emac-xfer {
				rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
						<2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
						<2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
						<2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
						<2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
						<2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
						<2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
						<2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
			};

			emac_mdio: emac-mdio {
				rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
						<2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
			};
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
						<0 RK_PA1 1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
						<0 RK_PA3 1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
						<2 RK_PC5 1 &pcfg_pull_none>;
			};
		};

		i2s {
			i2s_bus: i2s-bus {
				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
						<1 RK_PA1 1 &pcfg_pull_default>,
						<1 RK_PA2 1 &pcfg_pull_default>,
						<1 RK_PA3 1 &pcfg_pull_default>,
						<1 RK_PA4 1 &pcfg_pull_default>,
						<1 RK_PA5 1 &pcfg_pull_default>;
			};
		};

		hdmi {
			hdmi_ctl: hdmi-ctl {
				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
						<1 RK_PB1 1 &pcfg_pull_none>,
						<1 RK_PB2 1 &pcfg_pull_none>,
						<1 RK_PB3 1 &pcfg_pull_none>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
						<0 RK_PC1 1 &pcfg_pull_none>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
						<2 RK_PC7 1 &pcfg_pull_none>;
			};
			/* no rts / cts for uart1 */
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
						<1 RK_PC3 2 &pcfg_pull_none>;
			};
			/* no rts / cts for uart2 */
		};

		spi-pins {
			spi_txd:spi-txd {
				rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
			};

			spi_rxd:spi-rxd {
				rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
			};

			spi_clk:spi-clk {
				rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
			};

			spi_cs0:spi-cs0 {
				rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;

			};

			spi_cs1:spi-cs1 {
				rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;

			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 */

/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3066a.dtsi"

/ {
	model = "bq Curie 2";
	compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";

	aliases {
		mmc0 = &mmc0;
		mmc1 = &mmc1;
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x40000000>;
	};

	vdd_log: vdd-log {
		compatible = "pwm-regulator";
		pwms = <&pwm3 0 1000>;
		regulator-name = "vdd_log";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		regulator-always-on;
		voltage-table = <1000000 100>,
				<1200000 42>;
		status = "okay";
	};

	vcc_sd0: fixed-regulator {
		compatible = "regulator-fixed";
		regulator-name = "sdmmc-supply";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
		startup-delay-us = <100000>;
		vin-supply = <&vcc_io>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;

		key-power {
			gpios = <&gpio6 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
			linux,code = <KEY_POWER>;
			label = "GPIO Key Power";
			linux,input-type = <1>;
			wakeup-source;
			debounce-interval = <100>;
		};
		key-volume-down {
			gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
			linux,code = <KEY_VOLUMEDOWN>;
			label = "GPIO Key Vol-";
			linux,input-type = <1>;
			debounce-interval = <100>;
		};
		/* VOL+ comes somehow thru the ADC */
	};
};

&cpu0 {
	cpu-supply = <&vdd_arm>;
};

&cpu1 {
	cpu-supply = <&vdd_arm>;
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	tps: tps@2d {
		reg = <0x2d>;

		interrupt-parent = <&gpio6>;
		interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>;

		vcc5-supply = <&vcc_io>;
		vcc6-supply = <&vcc_io>;

		regulators {
			vcc_rtc: regulator@0 {
				regulator-name = "vcc_rtc";
				regulator-always-on;
			};

			vcc_io: regulator@1 {
				regulator-name = "vcc_io";
				regulator-always-on;
			};

			vdd_arm: regulator@2 {
				regulator-name = "vdd_arm";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <1500000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vcc_ddr: regulator@3 {
				regulator-name = "vcc_ddr";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <1500000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vcc18_cif: regulator@5 {
				regulator-name = "vcc18_cif";
				regulator-always-on;
			};

			vdd_11: regulator@6 {
				regulator-name = "vdd_11";
				regulator-always-on;
			};

			vcc_25: regulator@7 {
				regulator-name = "vcc_25";
				regulator-always-on;
			};

			vcc_18: regulator@8 {
				regulator-name = "vcc_18";
				regulator-always-on;
			};

			vcc25_hdmi: regulator@9 {
				regulator-name = "vcc25_hdmi";
				regulator-always-on;
			};

			vcca_33: regulator@10 {
				regulator-name = "vcca_33";
				regulator-always-on;
			};

			vcc_tp: regulator@11 {
				regulator-name = "vcc_tp";
				regulator-always-on;
			};

			vcc28_cif: regulator@12 {
				regulator-name = "vcc28_cif";
				regulator-always-on;
			};
		};
	};
};

/* must be included after &tps gets defined */
#include "tps65910.dtsi"

&mmc0 { /* sdmmc */
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
	vmmc-supply = <&vcc_sd0>;
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	disable-wp;
};

&mmc1 { /* wifi */
	status = "okay";
	non-removable;

	pinctrl-names = "default";
	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;

	bus-width = <4>;
};

&pwm3 {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&wdt {
	status = "okay";
};