code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-decon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON)

maintainers:
  - Inki Dae <inki.dae@samsung.com>
  - Seung-Woo Kim <sw0312.kim@samsung.com>
  - Kyungmin Park <kyungmin.park@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  DECON (Display and Enhancement Controller) is the Display Controller for the
  Exynos5433 series of SoCs which transfers the image data from a video memory
  buffer to an external LCD interface.

properties:
  compatible:
    enum:
      - samsung,exynos5433-decon
      - samsung,exynos5433-decon-tv

  clocks:
    maxItems: 11

  clock-names:
    items:
      - const: pclk
      - const: aclk_decon
      - const: aclk_smmu_decon0x
      - const: aclk_xiu_decon0x
      - const: pclk_smmu_decon0x
      - const: aclk_smmu_decon1x
      - const: aclk_xiu_decon1x
      - const: pclk_smmu_decon1x
      - const: sclk_decon_vclk
      - const: sclk_decon_eclk
      - const: dsd

  interrupts:
    minItems: 3
    maxItems: 4
    description: |
      Interrupts depend on mode of work:
       - video mode: vsync
       - command mode: lcd_sys
       - command mode with software trigger: lcd_sys, te

  interrupt-names:
    minItems: 3
    items:
      - const: fifo
      - const: vsync
      - const: lcd_sys
      - const: te

  iommus:
    maxItems: 2

  iommu-names:
    items:
      - const: m0
      - const: m1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description:
      Contains a port which is connected to mic node.

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

  samsung,disp-sysreg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to DISP system controller interface.

required:
  - compatible
  - clocks
  - clock-names
  - interrupts
  - interrupt-names
  - ports
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5433.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    display-controller@13800000 {
        compatible = "samsung,exynos5433-decon";
        reg = <0x13800000 0x2104>;
        clocks = <&cmu_disp CLK_PCLK_DECON>,
                 <&cmu_disp CLK_ACLK_DECON>,
                 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
                 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
                 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
                 <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
                 <&cmu_disp CLK_ACLK_XIU_DECON1X>,
                 <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
                 <&cmu_disp CLK_SCLK_DECON_VCLK>,
                 <&cmu_disp CLK_SCLK_DECON_ECLK>,
                 <&cmu_disp CLK_SCLK_DSD>;
        clock-names = "pclk",
                      "aclk_decon",
                      "aclk_smmu_decon0x",
                      "aclk_xiu_decon0x",
                      "pclk_smmu_decon0x",
                      "aclk_smmu_decon1x",
                      "aclk_xiu_decon1x",
                      "pclk_smmu_decon1x",
                      "sclk_decon_vclk",
                      "sclk_decon_eclk",
                      "dsd";
        power-domains = <&pd_disp>;
        interrupt-names = "fifo", "vsync", "lcd_sys";
        interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
        samsung,disp-sysreg = <&syscon_disp>;
        iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
        iommu-names = "m0", "m1";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                decon_to_mic: endpoint {
                    remote-endpoint = <&mic_to_decon>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-mic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos5433 SoC Mobile Image Compressor (MIC)

maintainers:
  - Inki Dae <inki.dae@samsung.com>
  - Seung-Woo Kim <sw0312.kim@samsung.com>
  - Kyungmin Park <kyungmin.park@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  MIC (Mobile Image Compressor) resides between DECON and MIPI DSI. MIPI DSI is
  not capable of transferring high resoltuion frame data as DECON can send. MIC
  solves this problem by compressing the frame data by 1/2 before it is
  transferred through MIPI DSI. The compressed frame data must be uncompressed
  in the panel PCB.

properties:
  compatible:
    const: samsung,exynos5433-mic

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: pclk_mic0
      - const: sclk_rgb_vclk_to_mic0

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description:
      Contains a port which is connected to mic node.

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

  samsung,disp-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to DISP system controller interface.

required:
  - compatible
  - clocks
  - clock-names
  - ports
  - reg
  - samsung,disp-syscon

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5433.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    image-processor@13930000 {
        compatible = "samsung,exynos5433-mic";
        reg = <0x13930000 0x48>;
        clocks = <&cmu_disp CLK_PCLK_MIC0>,
                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
        clock-names = "pclk_mic0",
                      "sclk_rgb_vclk_to_mic0";
        power-domains = <&pd_disp>;
        samsung,disp-syscon = <&syscon_disp>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                mic_to_decon: endpoint {
                    remote-endpoint = <&decon_to_mic>;
                };
            };

            port@1 {
                reg = <1>;
                mic_to_dsi: endpoint {
                    remote-endpoint = <&dsi_to_mic>;
                };
            };
        };
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)

maintainers:
  - Inki Dae <inki.dae@samsung.com>
  - Seung-Woo Kim <sw0312.kim@samsung.com>
  - Kyungmin Park <kyungmin.park@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  DECON (Display and Enhancement Controller) is the Display Controller for the
  Exynos7 series of SoCs which transfers the image data from a video memory
  buffer to an external LCD interface.

properties:
  compatible:
    const: samsung,exynos7-decon

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: pclk_decon0
      - const: aclk_decon0
      - const: decon0_eclk
      - const: decon0_vclk

  display-timings:
    $ref: ../panel/display-timings.yaml#

  i80-if-timings:
    type: object
    additionalProperties: false
    description: timing configuration for lcd i80 interface support
    properties:
      cs-setup:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Clock cycles for the active period of address signal is enabled until
          chip select is enabled.
        default: 0

      wr-active:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Clock cycles for the active period of CS is enabled.
        default: 1

      wr-hold:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Clock cycles for the active period of CS is disabled until write
          signal is disabled.
        default: 0

      wr-setup:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Clock cycles for the active period of CS signal is enabled until
          write signal is enabled.
        default: 0

  interrupts:
    items:
      - description: FIFO level
      - description: VSYNC
      - description: LCD system

  interrupt-names:
    items:
      - const: fifo
      - const: vsync
      - const: lcd_sys

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - clocks
  - clock-names
  - interrupts
  - interrupt-names
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos7-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    display-controller@13930000 {
        compatible = "samsung,exynos7-decon";
        reg = <0x13930000 0x1000>;
        interrupt-names = "fifo", "vsync", "lcd_sys";
        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clock_disp 100>, /* PCLK_DECON_INT */
                 <&clock_disp 101>, /* ACLK_DECON_INT */
                 <&clock_disp 102>, /* SCLK_DECON_INT_ECLK */
                 <&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */
        clock-names = "pclk_decon0",
                      "aclk_decon0",
                      "decon0_eclk",
                      "decon0_vclk";
        pinctrl-0 = <&lcd_clk &pwm1_out>;
        pinctrl-names = "default";
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,fimd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)

maintainers:
  - Inki Dae <inki.dae@samsung.com>
  - Seung-Woo Kim <sw0312.kim@samsung.com>
  - Kyungmin Park <kyungmin.park@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - samsung,s3c2443-fimd
      - samsung,s3c6400-fimd
      - samsung,s5pv210-fimd
      - samsung,exynos3250-fimd
      - samsung,exynos4210-fimd
      - samsung,exynos5250-fimd
      - samsung,exynos5420-fimd

  '#address-cells':
    const: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: sclk_fimd
      - const: fimd

  display-timings:
    $ref: ../panel/display-timings.yaml#

  i80-if-timings:
    type: object
    additionalProperties: false
    description: |
      Timing configuration for lcd i80 interface support.
      The parameters are defined as::
      VCLK(internal)  __|??????|_____|??????|_____|??????|_____|??????|_____|??
                        :            :            :            :            :
      Address Output  --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
                        | cs-setup+1 |            :            :            :
                        |<---------->|            :            :            :
      Chip Select     ???????????????|____________:____________:____________|??
                                     | wr-setup+1 |            | wr-hold+1  |
                                     |<---------->|            |<---------->|
      Write Enable    ????????????????????????????|____________|???????????????
                                                  | wr-active+1|
                                                  |<---------->|
      Video Data      ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--

    properties:
      cs-setup:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Clock cycles for the active period of address signal is enabled until
          chip select is enabled.
        default: 0

      wr-active:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Clock cycles for the active period of CS is enabled.
        default: 1

      wr-hold:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Clock cycles for the active period of CS is disabled until write
          signal is disabled.
        default: 0

      wr-setup:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Clock cycles for the active period of CS signal is enabled until
          write signal is enabled.
        default: 0

  iommus:
    minItems: 1
    maxItems: 2

  iommu-names:
    items:
      - const: m0
      - const: m1

  interrupts:
    items:
      - description: FIFO level
      - description: VSYNC
      - description: LCD system

  interrupt-names:
    items:
      - const: fifo
      - const: vsync
      - const: lcd_sys

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

  samsung,invert-vden:
    type: boolean
    description:
      Video enable signal is inverted.

  samsung,invert-vclk:
    type: boolean
    description:
      Video clock signal is inverted.

  samsung,sysreg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to System Register syscon.

  '#size-cells':
    const: 0

patternProperties:
  "^port@[0-4]+$":
    $ref: /schemas/graph.yaml#/properties/port
    description: |
      Contains ports with port with index::
       0 - for CAMIF0 input,
       1 - for CAMIF1 input,
       2 - for CAMIF2 input,
       3 - for parallel output,
       4 - for write-back interface

required:
  - compatible
  - clocks
  - clock-names
  - interrupts
  - interrupt-names
  - reg

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5420-fimd
    then:
      properties:
        iommus:
          minItems: 2
          maxItems: 2

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos4.h>

    fimd@11c00000 {
        compatible = "samsung,exynos4210-fimd";
        interrupt-parent = <&combiner>;
        reg = <0x11c00000 0x20000>;
        interrupt-names = "fifo", "vsync", "lcd_sys";
        interrupts = <11 0>, <11 1>, <11 2>;
        clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
        clock-names = "sclk_fimd", "fimd";
        power-domains = <&pd_lcd0>;
        iommus = <&sysmmu_fimd0>;
        samsung,sysreg = <&sys_reg>;

        #address-cells = <1>;
        #size-cells = <0>;

        samsung,invert-vden;
        samsung,invert-vclk;

        pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
        pinctrl-names = "default";

        port@3 {
            reg = <3>;

            fimd_dpi_ep: endpoint {
                remote-endpoint = <&lcd_ep>;
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/simple-framebuffer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Simple Framebuffer

maintainers:
  - Hans de Goede <hdegoede@redhat.com>

description: |+
  A simple frame-buffer describes a frame-buffer setup by firmware or
  the bootloader, with the assumption that the display hardware has
  already been set up to scan out from the memory pointed to by the
  reg property.

  Since simplefb nodes represent runtime information they must be
  sub-nodes of the chosen node (*). Simplefb nodes must be named
  framebuffer@<address>.

  If the devicetree contains nodes for the display hardware used by a
  simplefb, then the simplefb node must contain a property called
  display, which contains a phandle pointing to the primary display
  hw node, so that the OS knows which simplefb to disable when handing
  over control to a driver for the real hardware. The bindings for the
  hw nodes must specify which node is considered the primary node.

  It is advised to add display# aliases to help the OS determine how
  to number things. If display# aliases are used, then if the simplefb
  node contains a display property then the /aliases/display# path
  must point to the display hw node the display property points to,
  otherwise it must point directly to the simplefb node.

  If a simplefb node represents the preferred console for user
  interaction, then the chosen node stdout-path property should point
  to it, or to the primary display hw node, as with display#
  aliases. If display aliases are used then it should be set to the
  alias instead.

  It is advised that devicetree files contain pre-filled, disabled
  framebuffer nodes, so that the firmware only needs to update the
  mode information and enable them. This way if e.g. later on support
  for more display clocks get added, the simplefb nodes will already
  contain this info and the firmware does not need to be updated.

  If pre-filled framebuffer nodes are used, the firmware may need
  extra information to find the right node. In that case an extra
  platform specific compatible and platform specific properties should
  be used and documented.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - apple,simple-framebuffer
              - allwinner,simple-framebuffer
              - amlogic,simple-framebuffer
          - const: simple-framebuffer
      - const: simple-framebuffer

  reg:
    description: Location and size of the framebuffer memory

  clocks:
    description: List of clocks used by the framebuffer.

  power-domains:
    description: List of power domains used by the framebuffer.

  width:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Width of the framebuffer in pixels

  height:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Height of the framebuffer in pixels

  stride:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Number of bytes of a line in the framebuffer

  format:
    description: >
      Format of the framebuffer:
        * `a1r5g5b5` - 16-bit pixels, d[15]=a, d[14:10]=r, d[9:5]=g, d[4:0]=b
        * `a2r10g10b10` - 32-bit pixels, d[31:30]=a, d[29:20]=r, d[19:10]=g, d[9:0]=b
        * `a8b8g8r8` - 32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r
        * `a8r8g8b8` - 32-bit pixels, d[31:24]=a, d[23:16]=r, d[15:8]=g, d[7:0]=b
        * `r5g6b5` - 16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b
        * `r5g5b5a1` - 16-bit pixels, d[15:11]=r, d[10:6]=g, d[5:1]=b d[1:0]=a
        * `r8g8b8` - 24-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
        * `x1r5g5b5` - 16-bit pixels, d[14:10]=r, d[9:5]=g, d[4:0]=b
        * `x2r10g10b10` - 32-bit pixels, d[29:20]=r, d[19:10]=g, d[9:0]=b
        * `x8r8g8b8` - 32-bit pixels, d[23:16]=r, d[15:8]=g, d[7:0]=b
    enum:
      - a1r5g5b5
      - a2r10g10b10
      - a8b8g8r8
      - a8r8g8b8
      - r5g6b5
      - r5g5b5a1
      - r8g8b8
      - x1r5g5b5
      - x2r10g10b10
      - x8r8g8b8

  display:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: Primary display hardware node

  allwinner,pipeline:
    description: Pipeline used by the framebuffer on Allwinner SoCs
    enum:
      - de_be0-lcd0
      - de_be0-lcd0-hdmi
      - de_be0-lcd0-tve0
      - de_be1-lcd0
      - de_be1-lcd1-hdmi
      - de_fe0-de_be0-lcd0
      - de_fe0-de_be0-lcd0-hdmi
      - de_fe0-de_be0-lcd0-tve0
      - mixer0-lcd0
      - mixer0-lcd0-hdmi
      - mixer1-lcd1-hdmi
      - mixer1-lcd1-tve

  amlogic,pipeline:
    description: Pipeline used by the framebuffer on Amlogic SoCs
    enum:
      - vpu-cvbs
      - vpu-hdmi

patternProperties:
  "^[a-zA-Z0-9-]+-supply$":
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Regulators used by the framebuffer. These should be named
      according to the names in the device design.

required:
  # The binding requires also reg, width, height, stride and format,
  # but usually they will be filled by the bootloader.
  - compatible

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: allwinner,simple-framebuffer

    then:
      required:
        - allwinner,pipeline

  - if:
      properties:
        compatible:
          contains:
            const: amlogic,simple-framebuffer

    then:
      required:
        - amlogic,pipeline

additionalProperties: false

examples:
  - |
    / {
        compatible = "foo";
        model = "foo";
        #address-cells = <1>;
        #size-cells = <1>;

        chosen {
            #address-cells = <1>;
            #size-cells = <1>;
            framebuffer0: framebuffer@1d385000 {
                compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
                allwinner,pipeline = "de_be0-lcd0";
                reg = <0x1d385000 3840000>;
                width = <1600>;
                height = <1200>;
                stride = <3200>;
                format = "r5g6b5";
                clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>;
                lcd-supply = <&reg_dc1sw>;
                display = <&lcdc0>;
            };
        };
    };

...


code:
Sitronix ST7586 display panel

Required properties:
- compatible:	"lego,ev3-lcd".
- a0-gpios:	The A0 signal (since this binding is for serial mode, this is
                the pin labeled D1 on the controller, not the pin labeled A0)
- reset-gpios:	Reset pin

The node for this driver must be a child node of a SPI controller, hence
all mandatory properties described in ../spi/spi-bus.txt must be specified.

Optional properties:
- rotation:	panel rotation in degrees counter clockwise (0,90,180,270)

Example:
	display@0{
		compatible = "lego,ev3-lcd";
		reg = <0>;
		spi-max-frequency = <10000000>;
		a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/sitronix,st7735r.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sitronix ST7735R Display Panels

maintainers:
  - David Lechner <david@lechnology.com>

description:
  This binding is for display panels using a Sitronix ST7715R or ST7735R
  controller in SPI mode.

allOf:
  - $ref: panel/panel-common.yaml#
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

properties:
  compatible:
    oneOf:
      - description:
          Adafruit 1.8" 160x128 Color TFT LCD (Product ID 358 or 618)
        items:
          - enum:
              - jianda,jd-t18003-t01
          - const: sitronix,st7735r
      - description:
          Okaya 1.44" 128x128 Color TFT LCD (E.g. Renesas YRSK-LCD-PMOD)
        items:
          - enum:
              - okaya,rh128128t
          - const: sitronix,st7715r

  dc-gpios:
    maxItems: 1
    description: Display data/command selection (D/CX)

  backlight: true
  reg: true
  spi-max-frequency: true
  reset-gpios: true
  rotation: true

required:
  - compatible
  - reg
  - dc-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    backlight: backlight {
            compatible = "gpio-backlight";
            gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
    };

    spi {
            #address-cells = <1>;
            #size-cells = <0>;

            display@0{
                    compatible = "jianda,jd-t18003-t01", "sitronix,st7735r";
                    reg = <0>;
                    spi-max-frequency = <32000000>;
                    dc-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
                    reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
                    rotation = <270>;
                    backlight = <&backlight>;
            };
    };

...


code:
* SM SM501

The SM SM501 is a LCD controller, with proper hardware, it can also
drive DVI monitors.

Required properties:
- compatible : should be "smi,sm501".
- reg : contain two entries:
    - First entry: System Configuration register
    - Second entry: IO space (Display Controller register)
- interrupts : SMI interrupt to the cpu should be described here.

Optional properties:
- mode : select a video mode:
    <xres>x<yres>[-<bpp>][@<refresh>]
- edid : verbatim EDID data block describing attached display.
  Data from the detailed timing descriptor will be used to
  program the display controller.
- little-endian: available on big endian systems, to
  set different foreign endian.
- big-endian: available on little endian systems, to
  set different foreign endian.

Example for MPC5200:
	display@1,0 {
		compatible = "smi,sm501";
		reg = <1 0x00000000 0x00800000
		       1 0x03e00000 0x00200000>;
		interrupts = <1 1 3>;
		mode = "640x480-32@60";
		edid = [edid-data];
	};


code:
ARC PGU

This is a display controller found on several development boards produced
by Synopsys. The ARC PGU is an RGB streamer that reads the data from a
framebuffer and sends it to a single digital encoder (usually HDMI).

Required properties:
  - compatible: "snps,arcpgu"
  - reg: Physical base address and length of the controller's registers.
  - clocks: A list of phandle + clock-specifier pairs, one for each
    entry in 'clock-names'.
  - clock-names: A list of clock names. For ARC PGU it should contain:
      - "pxlclk" for the clock feeding the output PLL of the controller.

Required sub-nodes:
  - port: The PGU connection to an encoder chip.

Example:

/ {
	...

	pgu@XXXXXXXX {
		compatible = "snps,arcpgu";
		reg = <0xXXXXXXXX 0x400>;
		clocks = <&clock_node>;
		clock-names = "pxlclk";

		port {
			pgu_output: endpoint {
				remote-endpoint = <&hdmi_enc_input>;
			};
		};
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/solomon,ssd1307fb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Solomon SSD1307 OLED Controller Framebuffer

maintainers:
  - Maxime Ripard <mripard@kernel.org>
  - Javier Martinez Canillas <javierm@redhat.com>

properties:
  compatible:
    oneOf:
      # Deprecated compatible strings
      - items:
          - enum:
              - solomon,ssd1305fb-i2c
              - solomon,ssd1306fb-i2c
              - solomon,ssd1307fb-i2c
              - solomon,ssd1309fb-i2c
        deprecated: true
      - items:
          - enum:
              - sinowealth,sh1106
              - solomon,ssd1305
              - solomon,ssd1306
              - solomon,ssd1307
              - solomon,ssd1309

  reg:
    maxItems: 1

  pwms:
    maxItems: 1

  reset-gpios:
    maxItems: 1

  # Only required for SPI
  dc-gpios:
    description:
      GPIO connected to the controller's D/C# (Data/Command) pin,
      that is needed for 4-wire SPI to tell the controller if the
      data sent is for a command register or the display data RAM
    maxItems: 1

  vbat-supply:
    description: The supply for VBAT

  solomon,height:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 16
    description:
      Height in pixel of the screen driven by the controller

  solomon,width:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 96
    description:
      Width in pixel of the screen driven by the controller

  solomon,page-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 1
    description:
      Offset of pages (band of 8 pixels) that the screen is mapped to

  solomon,segment-no-remap:
    type: boolean
    description:
      Display needs normal (non-inverted) data column to segment mapping

  solomon,col-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0
    description:
      Offset of columns (COL/SEG) that the screen is mapped to

  solomon,com-seq:
    type: boolean
    description:
      Display uses sequential COM pin configuration

  solomon,com-lrremap:
    type: boolean
    description:
      Display uses left-right COM pin remap

  solomon,com-invdir:
    type: boolean
    description:
      Display uses inverted COM pin scan direction

  solomon,com-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0
    description:
      Number of the COM pin wired to the first display line

  solomon,prechargep1:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 2
    description:
      Length of deselect period (phase 1) in clock cycles

  solomon,prechargep2:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 2
    description:
      Length of precharge period (phase 2) in clock cycles.  This needs to be
      the higher, the higher the capacitance of the OLED's pixels is.

  solomon,dclk-div:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 16
    description:
      Clock divisor. The default value is controller-dependent.

  solomon,dclk-frq:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 15
    description:
      Clock frequency, higher value means higher frequency.
      The default value is controller-dependent.

  solomon,lookup-table:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    maxItems: 4
    description:
      8 bit value array of current drive pulse widths for BANK0, and colors A,
      B, and C. Each value in range of 31 to 63 for pulse widths of 32 to 64.
      Color D is always width 64.

  solomon,area-color-enable:
    type: boolean
    description:
      Display uses color mode

  solomon,low-power:
    type: boolean
    description:
      Display runs in low power mode

required:
  - compatible
  - reg

allOf:
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

  - if:
      properties:
        compatible:
          contains:
            const: sinowealth,sh1106
    then:
      properties:
        solomon,dclk-div:
          default: 1
        solomon,dclk-frq:
          default: 5

  - if:
      properties:
        compatible:
          contains:
            enum:
              - solomon,ssd1305-i2c
              - solomon,ssd1305
    then:
      properties:
        solomon,dclk-div:
          default: 1
        solomon,dclk-frq:
          default: 7

  - if:
      properties:
        compatible:
          contains:
            enum:
              - solomon,ssd1306-i2c
              - solomon,ssd1306
    then:
      properties:
        solomon,dclk-div:
          default: 1
        solomon,dclk-frq:
          default: 8

  - if:
      properties:
        compatible:
          contains:
            enum:
              - solomon,ssd1307-i2c
              - solomon,ssd1307
    then:
      properties:
        solomon,dclk-div:
          default: 2
        solomon,dclk-frq:
          default: 12
      required:
        - pwms

  - if:
      properties:
        compatible:
          contains:
            enum:
              - solomon,ssd1309-i2c
              - solomon,ssd1309
    then:
      properties:
        solomon,dclk-div:
          default: 1
        solomon,dclk-frq:
          default: 10

unevaluatedProperties: false

examples:
  - |
    i2c1 {
            #address-cells = <1>;
            #size-cells = <0>;

            ssd1307_i2c: oled@3c {
                    compatible = "solomon,ssd1307";
                    reg = <0x3c>;
                    pwms = <&pwm 4 3000>;
                    reset-gpios = <&gpio2 7>;
            };

            ssd1306_i2c: oled@3d {
                    compatible = "solomon,ssd1306";
                    reg = <0x3c>;
                    pwms = <&pwm 4 3000>;
                    reset-gpios = <&gpio2 7>;
                    solomon,com-lrremap;
                    solomon,com-invdir;
                    solomon,com-offset = <32>;
                    solomon,lookup-table = /bits/ 8 <0x3f 0x3f 0x3f 0x3f>;
            };
    };
  - |
    spi {
            #address-cells = <1>;
            #size-cells = <0>;

            ssd1307_spi: oled@0 {
                    compatible = "solomon,ssd1307";
                    reg = <0x0>;
                    pwms = <&pwm 4 3000>;
                    reset-gpios = <&gpio2 7>;
                    dc-gpios = <&gpio2 8>;
                    spi-max-frequency = <10000000>;
            };

            ssd1306_spi: oled@1 {
                    compatible = "solomon,ssd1306";
                    reg = <0x1>;
                    pwms = <&pwm 4 3000>;
                    reset-gpios = <&gpio2 7>;
                    dc-gpios = <&gpio2 8>;
                    spi-max-frequency = <10000000>;
                    solomon,com-lrremap;
                    solomon,com-invdir;
                    solomon,com-offset = <32>;
                    solomon,lookup-table = /bits/ 8 <0x3f 0x3f 0x3f 0x3f>;
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Unisoc DRM master device

maintainers:
  - Kevin Tang <kevin.tang@unisoc.com>

description: |
  The Unisoc DRM master device is a virtual device needed to list all
  DPU devices or other display interface nodes that comprise the
  graphics subsystem.

  Unisoc's display pipeline have several components as below description,
  multi display controllers and corresponding physical interfaces.
  For different display scenarios, dpu0 and dpu1 maybe binding to different
  encoder.

  E.g:
  dpu0 and dpu1 both binding to DSI for dual mipi-dsi display;
  dpu0 binding to DSI for primary display, and dpu1 binding to DP for external display;

          +-----------------------------------------+
          |                                         |
          |                            +---------+  |
  +----+  |   +----+    +---------+    |DPHY/CPHY|  |   +------+
  |    +----->+dpu0+--->+MIPI|DSI +--->+Combo    +----->+Panel0|
  |AXI |  |   +----+    +---------+    +---------+  |   +------+
  |    |  |                  ^                      |
  |    |  |                  |                      |
  |    |  |      +-----------+                      |
  |    |  |      |                                  |
  |APB |  |   +--+-+    +-----------+    +---+      |   +------+
  |    +----->+dpu1+--->+DisplayPort+--->+PHY+--------->+Panel1|
  |    |  |   +----+    +-----------+    +---+      |   +------+
  +----+  |                                         |
          +-----------------------------------------+

properties:
  compatible:
    const: sprd,display-subsystem

  ports:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      maxItems: 1
    description:
      Should contain a list of phandles pointing to display interface port
      of DPU devices.

required:
  - compatible
  - ports

additionalProperties: false

examples:
  - |
    display-subsystem {
        compatible = "sprd,display-subsystem";
        ports = <&dpu_out>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Unisoc Sharkl3 Display Processor Unit (DPU)

maintainers:
  - Kevin Tang <kevin.tang@unisoc.com>

description: |
  DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
  which transfers the image data from a video memory buffer to an internal
  LCD interface.

properties:
  compatible:
    const: sprd,sharkl3-dpu

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2

  clock-names:
    items:
      - const: clk_src_128m
      - const: clk_src_384m

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

  port:
    type: object
    description:
      A port node with endpoint definitions as defined in
      Documentation/devicetree/bindings/media/video-interfaces.txt.
      That port should be the output endpoint, usually output to
      the associated DSI.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sprd,sc9860-clk.h>
    dpu: dpu@63000000 {
        compatible = "sprd,sharkl3-dpu";
        reg = <0x63000000 0x1000>;
        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
        clock-names = "clk_src_128m", "clk_src_384m";

        clocks = <&pll CLK_TWPLL_128M>,
          <&pll CLK_TWPLL_384M>;

        dpu_port: port {
            dpu_out: endpoint {
                remote-endpoint = <&dsi_in>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dsi-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Unisoc MIPI DSI Controller

maintainers:
  - Kevin Tang <kevin.tang@unisoc.com>

properties:
  compatible:
    const: sprd,sharkl3-dsi-host

  reg:
    maxItems: 1

  interrupts:
    maxItems: 2

  clocks:
    minItems: 1

  clock-names:
    items:
      - const: clk_src_96m

  power-domains:
    maxItems: 1

  ports:
    type: object

    properties:
      "#address-cells":
        const: 1

      "#size-cells":
        const: 0

      port@0:
        type: object
        description:
          A port node with endpoint definitions as defined in
          Documentation/devicetree/bindings/media/video-interfaces.txt.
          That port should be the input endpoint, usually coming from
          the associated DPU.

    required:
      - "#address-cells"
      - "#size-cells"
      - port@0

    additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sprd,sc9860-clk.h>
    dsi: dsi@63100000 {
        compatible = "sprd,sharkl3-dsi-host";
        reg = <0x63100000 0x1000>;
        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
        clock-names = "clk_src_96m";
        clocks = <&pll CLK_TWPLL_96M>;
        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@0 {
                reg = <0>;
                dsi_in: endpoint {
                    remote-endpoint = <&dpu_out>;
                };
            };
        };
    };


code:
* Solomon SSD1289 Framebuffer Driver

Required properties:
  - compatible: Should be "solomon,ssd1289fb". The only supported bus for
    now is lbc.
  - reg: Should contain address of the controller on the LBC bus. The detail
    was described in Documentation/devicetree/bindings/powerpc/fsl/lbc.txt

Examples:
display@2,0 {
	compatible = "solomon,ssd1289fb";
	reg = <0x2 0x0000 0x0004>;
};


code:
STMicroelectronics stih4xx platforms

- sti-vtg: video timing generator
  Required properties:
  - compatible: "st,vtg"
  - reg: Physical base address of the IP registers and length of memory mapped region.
  Optional properties:
  - interrupts : VTG interrupt number to the CPU.
  - st,slave: phandle on a slave vtg

- sti-vtac: video timing advanced inter dye communication Rx and TX
  Required properties:
  - compatible: "st,vtac-main" or "st,vtac-aux"
  - reg: Physical base address of the IP registers and length of memory mapped region.
  - clocks: from common clock binding: handle hardware IP needed clocks, the
    number of clocks may depend of the SoC type.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: names of the clocks listed in clocks property in the same
    order.

- sti-display-subsystem: Master device for DRM sub-components
  This device must be the parent of all the sub-components and is responsible
  of bind them.
  Required properties:
  - compatible: "st,sti-display-subsystem"
  - ranges: to allow probing of subdevices

- sti-compositor: frame compositor engine
  must be a child of sti-display-subsystem
  Required properties:
  - compatible: "st,stih<chip>-compositor"
  - reg: Physical base address of the IP registers and length of memory mapped region.
  - clocks: from common clock binding: handle hardware IP needed clocks, the
    number of clocks may depend of the SoC type.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: names of the clocks listed in clocks property in the same
    order.
  - resets: resets to be used by the device
    See ../reset/reset.txt for details.
  - reset-names: names of the resets listed in resets property in the same
    order.
  - st,vtg: phandle(s) on vtg device (main and aux) nodes.

- sti-tvout: video out hardware block
  must be a child of sti-display-subsystem
  Required properties:
  - compatible: "st,stih<chip>-tvout"
  - reg: Physical base address of the IP registers and length of memory mapped region.
  - reg-names: names of the mapped memory regions listed in regs property in
    the same order.
  - resets: resets to be used by the device
    See ../reset/reset.txt for details.
  - reset-names: names of the resets listed in resets property in the same
    order.

- sti-hdmi: hdmi output block
  must be a child of sti-display-subsystem
  Required properties:
  - compatible: "st,stih<chip>-hdmi";
  - reg: Physical base address of the IP registers and length of memory mapped region.
  - reg-names: names of the mapped memory regions listed in regs property in
    the same order.
  - interrupts : HDMI interrupt number to the CPU.
  - interrupt-names: names of the interrupts listed in interrupts property in
    the same order
  - clocks: from common clock binding: handle hardware IP needed clocks, the
    number of clocks may depend of the SoC type.
  - clock-names: names of the clocks listed in clocks property in the same
    order.
  - ddc: phandle of an I2C controller used for DDC EDID probing

sti-hda:
  Required properties:
  must be a child of sti-display-subsystem
  - compatible: "st,stih<chip>-hda"
  - reg: Physical base address of the IP registers and length of memory mapped region.
  - reg-names: names of the mapped memory regions listed in regs property in
    the same order.
  - clocks: from common clock binding: handle hardware IP needed clocks, the
    number of clocks may depend of the SoC type.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: names of the clocks listed in clocks property in the same
    order.

sti-dvo:
  Required properties:
  must be a child of sti-display-subsystem
  - compatible: "st,stih<chip>-dvo"
  - reg: Physical base address of the IP registers and length of memory mapped region.
  - reg-names: names of the mapped memory regions listed in regs property in
    the same order.
  - clocks: from common clock binding: handle hardware IP needed clocks, the
    number of clocks may depend of the SoC type.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: names of the clocks listed in clocks property in the same
    order.
  - pinctrl-0: pin control handle
  - pinctrl-names: names of the pin control states to use
  - sti,panel: phandle of the panel connected to the DVO output

sti-hqvdp:
  must be a child of sti-display-subsystem
  Required properties:
  - compatible: "st,stih<chip>-hqvdp"
  - reg: Physical base address of the IP registers and length of memory mapped region.
  - clocks: from common clock binding: handle hardware IP needed clocks, the
    number of clocks may depend of the SoC type.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: names of the clocks listed in clocks property in the same
    order.
  - resets: resets to be used by the device
    See ../reset/reset.txt for details.
  - reset-names: names of the resets listed in resets property in the same
    order.
  - st,vtg: phandle on vtg main device node.

Example:

/ {
	...

	vtg_main_slave: sti-vtg-main-slave@fe85a800 {
		compatible	= "st,vtg";
		reg		= <0xfe85A800 0x300>;
		interrupts	= <GIC_SPI 175 IRQ_TYPE_NONE>;
	};

	vtg_main: sti-vtg-main-master@fd348000 {
		compatible	= "st,vtg";
		reg		= <0xfd348000 0x400>;
		st,slave	= <&vtg_main_slave>;
	};

	vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
		compatible	= "st,vtg";
		reg		= <0xfe858200 0x300>;
		interrupts	= <GIC_SPI 176 IRQ_TYPE_NONE>;
	};

	vtg_aux: sti-vtg-aux-master@fd348400 {
		compatible	= "st,vtg";
		reg		= <0xfd348400 0x400>;
		st,slave	= <&vtg_aux_slave>;
	};

	sti-vtac-rx-main@fee82800 {
		compatible	= "st,vtac-main";
		reg		= <0xfee82800 0x200>;
		clock-names     = "vtac";
		clocks          = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
	};

	sti-vtac-rx-aux@fee82a00 {
		compatible	= "st,vtac-aux";
		reg		= <0xfee82a00 0x200>;
		clock-names     = "vtac";
		clocks          = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
	};

	sti-vtac-tx-main@fd349000 {
		compatible	= "st,vtac-main";
		reg		= <0xfd349000 0x200>, <0xfd320000 0x10000>;
		clock-names     = "vtac";
		clocks           = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
	};

	sti-vtac-tx-aux@fd349200 {
		compatible	= "st,vtac-aux";
		reg		= <0xfd349200 0x200>, <0xfd320000 0x10000>;
		clock-names     = "vtac";
		clocks          = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
	};

	sti-display-subsystem {
		compatible = "st,sti-display-subsystem";
		ranges;

		sti-compositor@fd340000 {
			compatible	= "st,stih416-compositor";
			reg		= <0xfd340000 0x1000>;
			clock-names	= "compo_main", "compo_aux",
			                  "pix_main", "pix_aux";
			clocks          = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
					  <&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
			reset-names     = "compo-main", "compo-aux";
			resets          = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
			st,vtg		= <&vtg_main>, <&vtg_aux>;
		};

		sti-tvout@fe000000 {
			compatible	= "st,stih416-tvout";
			reg		= <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
			reg-names	= "tvout-reg", "hda-reg", "syscfg";
			reset-names     = "tvout";
			resets          = <&softreset STIH416_HDTVOUT_SOFTRESET>;
		};

		sti-hdmi@fe85c000 {
			compatible	= "st,stih416-hdmi";
			reg		= <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
			reg-names	= "hdmi-reg", "syscfg";
			interrupts	= <GIC_SPI 173 IRQ_TYPE_NONE>;
			interrupt-names	= "irq";
			clock-names	= "pix", "tmds", "phy", "audio";
			clocks          = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
		};

		sti-hda@fe85a000 {
			compatible	= "st,stih416-hda";
			reg		= <0xfe85a000 0x400>, <0xfe83085c 0x4>;
			reg-names	= "hda-reg", "video-dacs-ctrl";
			clock-names	= "pix", "hddac";
			clocks          = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
		};

		sti-dvo@8d00400 {
			compatible	= "st,stih407-dvo";
			reg		= <0x8d00400 0x200>;
			reg-names	= "dvo-reg";
			clock-names	= "dvo_pix", "dvo",
					  "main_parent", "aux_parent";
			clocks		= <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>,
					  <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>;
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_dvo>;
			sti,panel	= <&panel_dvo>;
		};

		sti-hqvdp@9c000000 {
				compatible	= "st,stih407-hqvdp";
				reg		= <0x9C00000 0x100000>;
				clock-names	= "hqvdp", "pix_main";
				clocks		= <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
				reset-names     = "hqvdp";
				resets          = <&softreset STIH407_HDQVDP_SOFTRESET>;
				st,vtg		= <&vtg_main>;
		};
	};
	...
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 DSI host controller

maintainers:
  - Philippe Cornu <philippe.cornu@foss.st.com>
  - Yannick Fertre <yannick.fertre@foss.st.com>

description:
  The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.

allOf:
  - $ref: dsi-controller.yaml#

properties:
  compatible:
    const: st,stm32-dsi

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Module Clock
      - description: DSI bus clock
      - description: Pixel clock
    minItems: 2

  clock-names:
    items:
      - const: pclk
      - const: ref
      - const: px_clk
    minItems: 2

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: apb

  phy-dsi-supply:
    description:
      Phandle of the regulator that provides the supply voltage.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          DSI input port node, connected to the ltdc rgb output port.

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: |
          DSI output port node, connected to a panel or a bridge input port.
        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false
            properties:
              data-lanes:
                minItems: 1
                items:
                  - const: 1
                  - const: 2

required:
  - "#address-cells"
  - "#size-cells"
  - compatible
  - reg
  - clocks
  - clock-names
  - ports

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    #include <dt-bindings/gpio/gpio.h>
    dsi: dsi@5a000000 {
        compatible = "st,stm32-dsi";
        reg = <0x5a000000 0x800>;
        clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
        clock-names = "pclk", "ref", "px_clk";
        resets = <&rcc DSI_R>;
        reset-names = "apb";
        phy-dsi-supply = <&reg18>;

        #address-cells = <1>;
        #size-cells = <0>;

        ports {
              #address-cells = <1>;
              #size-cells = <0>;

              port@0 {
                    reg = <0>;
                    dsi_in: endpoint {
                        remote-endpoint = <&ltdc_ep1_out>;
                    };
              };

              port@1 {
                    reg = <1>;
                    dsi_out: endpoint {
                        remote-endpoint = <&panel_in>;
                    };
              };
        };

        panel@0 {
              compatible = "orisetech,otm8009a";
              reg = <0>;
              reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
              power-supply = <&v3v3>;

              port {
                    panel_in: endpoint {
                        remote-endpoint = <&dsi_out>;
                    };
              };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 lcd-tft display controller

maintainers:
  - Philippe Cornu <philippe.cornu@foss.st.com>
  - Yannick Fertre <yannick.fertre@foss.st.com>

properties:
  compatible:
    const: st,stm32-ltdc

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: events interrupt line.
      - description: errors interrupt line.
    minItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: lcd

  resets:
    maxItems: 1

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description: |
      Video port for DPI RGB output.
      ltdc has one video port with up to 2 endpoints:
      - for external dpi rgb panel or bridge, using gpios.
      - for internal dpi input of the MIPI DSI host controller.
      Note: These 2 endpoints cannot be activated simultaneously.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    ltdc: display-controller@40016800 {
        compatible = "st,stm32-ltdc";
        reg = <0x5a001000 0x400>;
        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&rcc LTDC_PX>;
        clock-names = "lcd";
        resets = <&rcc LTDC_R>;

        port {
             ltdc_out_dsi: endpoint {
                     remote-endpoint = <&dsi_in>;
             };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/ste,mcde.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ST-Ericsson Multi Channel Display Engine MCDE

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

properties:
  compatible:
    const: ste,mcde

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    description: an array of the MCDE clocks
    items:
      - description: MCDECLK (main MCDE clock)
      - description: LCDCLK (LCD clock)
      - description: PLLDSI (HDMI clock)

  clock-names:
    items:
      - const: mcde
      - const: lcd
      - const: hdmi

  resets:
    maxItems: 1

  epod-supply:
    description: a phandle to the EPOD regulator

  vana-supply:
    description: a phandle to the analog voltage regulator

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      A DPI port node

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  ranges: true

patternProperties:
  "^dsi@[0-9a-f]+$":
    description: subnodes for the three DSI host adapters
    type: object
    $ref: dsi-controller.yaml#

    properties:
      compatible:
        const: ste,mcde-dsi

      reg:
        maxItems: 1

      vana-supply:
        description: a phandle to the analog voltage regulator

      clocks:
        description: phandles to the high speed and low power (energy save) clocks
          the high speed clock is not present on the third (dsi2) block, so it
          should only have the "lp" clock
        minItems: 1
        maxItems: 2

      clock-names:
        oneOf:
          - items:
              - const: hs
              - const: lp
          - items:
              - const: lp

    required:
      - compatible
      - reg
      - vana-supply
      - clocks
      - clock-names

    unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - epod-supply
  - vana-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/mfd/dbx500-prcmu.h>
    #include <dt-bindings/gpio/gpio.h>

    mcde@a0350000 {
      compatible = "ste,mcde";
      reg = <0xa0350000 0x1000>;
      interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
      epod-supply = <&db8500_b2r2_mcde_reg>;
      vana-supply = <&ab8500_ldo_ana_reg>;
      clocks = <&prcmu_clk PRCMU_MCDECLK>,
               <&prcmu_clk PRCMU_LCDCLK>,
               <&prcmu_clk PRCMU_PLLDSI>;
      clock-names = "mcde", "lcd", "hdmi";
      #address-cells = <1>;
      #size-cells = <1>;
      ranges;

      dsi0: dsi@a0351000 {
        compatible = "ste,mcde-dsi";
        reg = <0xa0351000 0x1000>;
        vana-supply = <&ab8500_ldo_ana_reg>;
        clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
        clock-names = "hs", "lp";
        #address-cells = <1>;
        #size-cells = <0>;

        panel@0 {
          compatible = "samsung,s6d16d0";
          reg = <0>;
          vdd1-supply = <&ab8500_ldo_aux1_reg>;
          reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
        };
      };

      dsi1: dsi@a0352000 {
        compatible = "ste,mcde-dsi";
        reg = <0xa0352000 0x1000>;
        vana-supply = <&ab8500_ldo_ana_reg>;
        clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
        clock-names = "hs", "lp";
        #address-cells = <1>;
        #size-cells = <0>;
      };

      dsi2: dsi@a0353000 {
        compatible = "ste,mcde-dsi";
        reg = <0xa0353000 0x1000>;
        vana-supply = <&ab8500_ldo_ana_reg>;
        /* This DSI port only has the Low Power / Energy Save clock */
        clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
        clock-names = "lp";
        #address-cells = <1>;
        #size-cells = <0>;
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra MIPI pad calibration controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^mipi@[0-9a-f]+$"

  compatible:
    enum:
      - nvidia,tegra114-mipi
      - nvidia,tegra210-mipi
      - nvidia,tegra186-mipi

  reg:
    maxItems: 1

  clocks:
    items:
      - description: module clock

  clock-names:
    items:
      - const: mipi-cal

  power-domains:
    maxItems: 1

  "#nvidia,mipi-calibrate-cells":
    description: The number of cells in a MIPI calibration specifier.
      Should be 1. The single cell specifies a bitmask of the pads that
      need to be calibrated for a given device.
    $ref: "/schemas/types.yaml#/definitions/uint32"
    const: 1

additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - "#nvidia,mipi-calibrate-cells"

examples:
  - |
    #include <dt-bindings/clock/tegra114-car.h>

    mipi@700e3000 {
        compatible = "nvidia,tegra114-mipi";
        reg = <0x700e3000 0x100>;
        clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
        clock-names = "mipi-cal";
        #nvidia,mipi-calibrate-cells = <1>;
    };

    dsia: dsi@54300000 {
        compatible = "nvidia,tegra114-dsi";
        reg = <0x54300000 0x00040000>;
        clocks = <&tegra_car TEGRA114_CLK_DSIA>,
                 <&tegra_car TEGRA114_CLK_DSIALP>,
                 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
        clock-names = "dsi", "lp", "parent";
        resets = <&tegra_car 48>;
        reset-names = "dsi";
        nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra DisplayPort AUX Interface

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: |
  The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
  pins which can be assigned to either the DPAUX channel or to an I2C
  controller.

  When configured for DisplayPort AUX operation, the DPAUX controller
  can also be used to communicate with a DisplayPort device using the
  AUX channel.

properties:
  $nodename:
    pattern: "^dpaux@[0-9a-f]+$"

  compatible:
    oneOf:
      - enum:
          - nvidia,tegra124-dpaux
          - nvidia,tegra210-dpaux
          - nvidia,tegra186-dpaux
          - nvidia,tegra194-dpaux

      - items:
          - const: nvidia,tegra132-dpaux
          - const: nvidia,tegra124-dpaux

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: clock input for the DPAUX hardware
      - description: reference clock

  clock-names:
    items:
      - const: dpaux
      - const: parent

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: dpaux

  power-domains:
    maxItems: 1

  i2c-bus:
    description: Subnode where I2C slave devices are listed. This
      subnode must be always present. If there are no I2C slave
      devices, an empty node should be added. See ../../i2c/i2c.yaml
      for more information.
    type: object

  aux-bus:
    $ref: /schemas/display/dp-aux-bus.yaml#

  vdd-supply:
    description: phandle of a supply that powers the DisplayPort
      link

patternProperties:
  "^pinmux-[a-z0-9]+$":
    description:
      Since only three configurations are possible, only three child
      nodes are needed to describe the pin mux'ing options for the
      DPAUX pads. Furthermore, given that the pad functions are only
      applicable to a single set of pads, the child nodes only need
      to describe the pad group the functions are being applied to
      rather than the individual pads.
    type: object
    properties:
      groups:
        const: dpaux-io

      function:
        enum:
          - aux
          - i2c
          - off

    additionalProperties: false

    required:
      - groups
      - function

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - reset-names

examples:
  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    dpaux: dpaux@545c0000 {
        compatible = "nvidia,tegra210-dpaux";
        reg = <0x545c0000 0x00040000>;
        interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
                 <&tegra_car TEGRA210_CLK_PLL_DP>;
        clock-names = "dpaux", "parent";
        resets = <&tegra_car 181>;
        reset-names = "dpaux";
        power-domains = <&pd_sor>;

        state_dpaux_aux: pinmux-aux {
            groups = "dpaux-io";
            function = "aux";
        };

        state_dpaux_i2c: pinmux-i2c {
            groups = "dpaux-io";
            function = "i2c";
        };

        state_dpaux_off: pinmux-off {
            groups = "dpaux-io";
            function = "off";
        };

        i2c-bus {
            #address-cells = <1>;
            #size-cells = <0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra SOR Output Encoder

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: |
  The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
  and DP outputs.

properties:
  $nodename:
    pattern: "^sor@[0-9a-f]+$"

  compatible:
    oneOf:
      - enum:
          - nvidia,tegra124-sor
          - nvidia,tegra210-sor
          - nvidia,tegra210-sor1
          - nvidia,tegra186-sor
          - nvidia,tegra186-sor1
          - nvidia,tegra194-sor

      - items:
          - const: nvidia,tegra132-sor
          - const: nvidia,tegra124-sor

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 5
    maxItems: 6

  clock-names:
    minItems: 5
    maxItems: 6

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: sor

  power-domains:
    maxItems: 1

  avdd-io-hdmi-dp-supply:
    description: I/O supply for HDMI/DP

  vdd-hdmi-dp-pll-supply:
    description: PLL supply for HDMI/DP

  hdmi-supply:
    description: +5.0V HDMI connector supply, required for HDMI

  # Tegra186 and later
  nvidia,interface:
    description: index of the SOR interface
    $ref: "/schemas/types.yaml#/definitions/uint32"

  nvidia,ddc-i2c-bus:
    description: phandle of an I2C controller used for DDC EDID
      probing
    $ref: "/schemas/types.yaml#/definitions/phandle"

  nvidia,hpd-gpio:
    description: specifies a GPIO used for hotplug detection
    maxItems: 1

  nvidia,edid:
    description: supplies a binary EDID blob
    $ref: "/schemas/types.yaml#/definitions/uint8-array"

  nvidia,panel:
    description: phandle of a display panel, required for eDP
    $ref: "/schemas/types.yaml#/definitions/phandle"

  nvidia,xbar-cfg:
    description: 5 cells containing the crossbar configuration.
      Each lane of the SOR, identified by the cell's index, is
      mapped via the crossbar to the pad specified by the cell's
      value.
    $ref: "/schemas/types.yaml#/definitions/uint32-array"

  # optional when driving an eDP output
  nvidia,dpaux:
    description: phandle to a DispayPort AUX interface
    $ref: "/schemas/types.yaml#/definitions/phandle"

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra186-sor
              - nvidia,tegra194-sor
    then:
      properties:
        clocks:
          items:
            - description: clock input for the SOR hardware
            - description: SOR output clock
            - description: input for the pixel clock
            - description: reference clock for the SOR clock
            - description: safe reference clock for the SOR clock
                during power up
            - description: SOR pad output clock

        clock-names:
          items:
            - const: sor
            - enum:
                - source # deprecated
                - out
            - const: parent
            - const: dp
            - const: safe
            - const: pad
    else:
      properties:
        clocks:
          items:
            - description: clock input for the SOR hardware
            - description: SOR output clock
            - description: input for the pixel clock
            - description: reference clock for the SOR clock
            - description: safe reference clock for the SOR clock
                during power up

        clock-names:
          items:
            - const: sor
            - enum:
                - source # deprecated
                - out
            - const: parent
            - const: dp
            - const: safe

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - reset-names
  - avdd-io-hdmi-dp-supply
  - vdd-hdmi-dp-pll-supply

examples:
  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/gpio/tegra-gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    sor0: sor@54540000 {
        compatible = "nvidia,tegra210-sor";
        reg = <0x54540000 0x00040000>;
        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA210_CLK_SOR0>,
                 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
                 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
                 <&tegra_car TEGRA210_CLK_PLL_DP>,
                 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
        clock-names = "sor", "out", "parent", "dp", "safe";
        resets = <&tegra_car 182>;
        reset-names = "sor";
        pinctrl-0 = <&state_dpaux_aux>;
        pinctrl-1 = <&state_dpaux_i2c>;
        pinctrl-2 = <&state_dpaux_off>;
        pinctrl-names = "aux", "i2c", "off";
        power-domains = <&pd_sor>;

        avdd-io-hdmi-dp-supply = <&avdd_1v05>;
        vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
        hdmi-supply = <&vdd_hdmi>;

        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) GPIO_ACTIVE_LOW>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-vic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Video Image Composer

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^vic@[0-9a-f]+$"

  compatible:
    oneOf:
      - enum:
          - nvidia,tegra124-vic
          - nvidia,tegra210-vic
          - nvidia,tegra186-vic
          - nvidia,tegra194-vic
          - nvidia,tegra234-vic

      - items:
          - const: nvidia,tegra132-vic
          - const: nvidia,tegra124-vic

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: clock input for the VIC hardware

  clock-names:
    items:
      - const: vic

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: vic

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

  interconnects:
    description: Description of the interconnect paths for the VIC;
      see ../interconnect/interconnect.txt for details.
    items:
      - description: memory read client for VIC
      - description: memory write client for VIC

  interconnect-names:
    items:
      - const: dma-mem # read
      - const: write

  dma-coherent: true

additionalProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra186 (and later) Display Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^display@[0-9a-f]+$"

  compatible:
    enum:
      - nvidia,tegra186-dc
      - nvidia,tegra194-dc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: display controller pixel clock

  clock-names:
    items:
      - const: dc

  resets:
    items:
      - description: display controller reset

  reset-names:
    items:
      - const: dc

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

  interconnects:
    description: Description of the interconnect paths for the
      display controller; see ../interconnect/interconnect.txt
      for details.

  interconnect-names:
    items:
      - const: dma-mem # read-0
      - const: read-1

  nvidia,outputs:
    description: A list of phandles of outputs that this display
      controller can drive.
    $ref: "/schemas/types.yaml#/definitions/phandle-array"

  nvidia,head:
    description: The number of the display controller head. This
      is used to setup the various types of output to receive
      video data from the given head.
    $ref: "/schemas/types.yaml#/definitions/uint32"

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - reset-names
  - power-domains
  - nvidia,outputs
  - nvidia,head

# see nvidia,tegra186-display.yaml for examples


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra186 (and later) Display Hub

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^display-hub@[0-9a-f]+$"

  compatible:
    enum:
      - nvidia,tegra186-display
      - nvidia,tegra194-display

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 3

  clock-names:
    minItems: 2
    maxItems: 3

  resets:
    items:
      - description: display hub reset
      - description: window group 0 reset
      - description: window group 1 reset
      - description: window group 2 reset
      - description: window group 3 reset
      - description: window group 4 reset
      - description: window group 5 reset

  reset-names:
    items:
      - const: misc
      - const: wgrp0
      - const: wgrp1
      - const: wgrp2
      - const: wgrp3
      - const: wgrp4
      - const: wgrp5

  power-domains:
    maxItems: 1

  ranges:
    maxItems: 1

patternProperties:
  "^display@[0-9a-f]+$":
    type: object

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra186-display
    then:
      properties:
        clocks:
          items:
            - description: display core clock
            - description: display stream compression clock
            - description: display hub clock

        clock-names:
          items:
            - const: disp
            - const: dsc
            - const: hub
    else:
      properties:
        clocks:
          items:
            - description: display core clock
            - description: display hub clock

        clock-names:
          items:
            - const: disp
            - const: hub

additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - power-domains
  - "#address-cells"
  - "#size-cells"
  - ranges

examples:
  - |
    #include <dt-bindings/clock/tegra186-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/tegra186-mc.h>
    #include <dt-bindings/power/tegra186-powergate.h>
    #include <dt-bindings/reset/tegra186-reset.h>

    display-hub@15200000 {
        compatible = "nvidia,tegra186-display";
        reg = <0x15200000 0x00040000>;
        resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
                 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
        reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
                      "wgrp3", "wgrp4", "wgrp5";
        clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
                 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
                 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
        clock-names = "disp", "dsc", "hub";

        power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;

        #address-cells = <1>;
        #size-cells = <1>;

        ranges = <0x15200000 0x15200000 0x40000>;

        display@15200000 {
            compatible = "nvidia,tegra186-dc";
            reg = <0x15200000 0x10000>;
            interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
            clock-names = "dc";
            resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
            reset-names = "dc";

            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
                            <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
            interconnect-names = "dma-mem", "read-1";
            iommus = <&smmu TEGRA186_SID_NVDISPLAY>;

            nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
            nvidia,head = <0>;
        };

        display@15210000 {
            compatible = "nvidia,tegra186-dc";
            reg = <0x15210000 0x10000>;
            interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
            clock-names = "dc";
            resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
            reset-names = "dc";

            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
                            <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
            interconnect-names = "dma-mem", "read-1";
            iommus = <&smmu TEGRA186_SID_NVDISPLAY>;

            nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
            nvidia,head = <1>;
        };

        display@15220000 {
            compatible = "nvidia,tegra186-dc";
            reg = <0x15220000 0x10000>;
            interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
            clock-names = "dc";
            resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
            reset-names = "dc";

            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
                            <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
            interconnect-names = "dma-mem", "read-1";
            iommus = <&smmu TEGRA186_SID_NVDISPLAY>;

            nvidia,outputs = <&sor0 &sor1>;
            nvidia,head = <2>;
        };
    };

  - |
    #include <dt-bindings/clock/tegra194-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/tegra194-mc.h>
    #include <dt-bindings/power/tegra194-powergate.h>
    #include <dt-bindings/reset/tegra194-reset.h>

    display-hub@15200000 {
        compatible = "nvidia,tegra194-display";
        reg = <0x15200000 0x00040000>;
        resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
                 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
        reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
                      "wgrp3", "wgrp4", "wgrp5";
        clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
                 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
        clock-names = "disp", "hub";

        power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;

        #address-cells = <1>;
        #size-cells = <1>;

        ranges = <0x15200000 0x15200000 0x40000>;

        display@15200000 {
            compatible = "nvidia,tegra194-dc";
            reg = <0x15200000 0x10000>;
            interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
            clock-names = "dc";
            resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
            reset-names = "dc";

            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
            interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
                            <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
            interconnect-names = "dma-mem", "read-1";

            nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
            nvidia,head = <0>;
        };

        display@15210000 {
            compatible = "nvidia,tegra194-dc";
            reg = <0x15210000 0x10000>;
            interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
            clock-names = "dc";
            resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
            reset-names = "dc";

            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
            interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
                            <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
            interconnect-names = "dma-mem", "read-1";

            nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
            nvidia,head = <1>;
        };

        display@15220000 {
            compatible = "nvidia,tegra194-dc";
            reg = <0x15220000 0x10000>;
            interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
            clock-names = "dc";
            resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
            reset-names = "dc";

            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
            interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
                            <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
            interconnect-names = "dma-mem", "read-1";

            nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
            nvidia,head = <2>;
        };

        display@15230000 {
            compatible = "nvidia,tegra194-dc";
            reg = <0x15230000 0x10000>;
            interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
            clock-names = "dc";
            resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
            reset-names = "dc";

            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
            interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
                            <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
            interconnect-names = "dma-mem", "read-1";

            nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
            nvidia,head = <3>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dsi-padctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra MIPI DSI pad controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^padctl@[0-9a-f]+$"

  compatible:
    const: nvidia,tegra186-dsi-padctl

  reg:
    maxItems: 1

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: dsi

allOf:
  - $ref: "/schemas/reset/reset.yaml"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/reset/tegra186-reset.h>

    padctl@15880000 {
        compatible = "nvidia,tegra186-dsi-padctl";
        reg = <0x15880000 0x10000>;
        resets = <&bpmp TEGRA186_RESET_DSI>;
        reset-names = "dsi";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Display Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^dc@[0-9a-f]+$"

  compatible:
    oneOf:
      - enum:
          - nvidia,tegra20-dc
          - nvidia,tegra30-dc
          - nvidia,tegra114-dc
          - nvidia,tegra124-dc
          - nvidia,tegra210-dc

      - items:
          - const: nvidia,tegra124-dc
          - const: nvidia,tegra132-dc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: display controller pixel clock
      - description: parent clock # optional

  clock-names:
    minItems: 1
    items:
      - const: dc
      - const: parent # optional

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: dc

  interconnect-names: true
  interconnects: true

  iommus:
    maxItems: 1

  operating-points-v2:
    $ref: "/schemas/types.yaml#/definitions/phandle"

  power-domains:
    items:
      - description: phandle to the core power domain

  memory-region: true

  nvidia,head:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The number of the display controller head. This is used to setup the various
      types of output to receive video data from the given head.

  nvidia,outputs:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: A list of phandles of outputs that this display controller can drive.

  rgb:
    type: object

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra20-dc
              - nvidia,tegra30-dc
              - nvidia,tegra114-dc
    then:
      properties:
        interconnects:
          items:
            - description: window A memory client
            - description: window B memory client
            - description: window B memory client (vertical filter)
            - description: window C memory client
            - description: cursor memory client

        interconnect-names:
          items:
            - const: wina
            - const: winb
            - const: winb-vfilter
            - const: winc
            - const: cursor

        rgb:
          description: Each display controller node has a child node, named "rgb", that represents
            the RGB output associated with the controller.
          type: object
          properties:
            nvidia,ddc-i2c-bus:
              $ref: /schemas/types.yaml#/definitions/phandle
              description: phandle of an I2C controller used for DDC EDID probing

            nvidia,hpd-gpio:
              description: specifies a GPIO used for hotplug detection
              maxItems: 1

            nvidia,edid:
              $ref: /schemas/types.yaml#/definitions/uint8-array
              description: supplies a binary EDID blob

            nvidia,panel:
              $ref: /schemas/types.yaml#/definitions/phandle
              description: phandle of a display panel

  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra124-dc
    then:
      properties:
        interconnects:
          minItems: 4
          items:
            - description: window A memory client
            - description: window B memory client
            - description: window C memory client
            - description: cursor memory client
            - description: window D memory client
            - description: window T memory client

        interconnect-names:
          minItems: 4
          items:
            - const: wina
            - const: winb
            - const: winc
            - const: cursor
            - const: wind
            - const: wint

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - reset-names

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    dc@54200000 {
        compatible = "nvidia,tegra20-dc";
        reg = <0x54200000 0x00040000>;
        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA20_CLK_DISP1>;
        clock-names = "dc";
        resets = <&tegra_car 27>;
        reset-names = "dc";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Display Serial Interface

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    oneOf:
      - enum:
          - nvidia,tegra20-dsi
          - nvidia,tegra30-dsi
          - nvidia,tegra114-dsi
          - nvidia,tegra124-dsi
          - nvidia,tegra210-dsi
          - nvidia,tegra186-dsi

      - items:
          - const: nvidia,tegra132-dsi
          - const: nvidia,tegra124-dsi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 3

  clock-names:
    minItems: 2
    maxItems: 3

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: dsi

  operating-points-v2:
    $ref: "/schemas/types.yaml#/definitions/phandle"

  power-domains:
    maxItems: 1

  avdd-dsi-csi-supply:
    description: phandle of a supply that powers the DSI controller

  nvidia,mipi-calibrate:
    description: Should contain a phandle and a specifier specifying
      which pads are used by this DSI output and need to be
      calibrated. See nvidia,tegra114-mipi.yaml for details.
    $ref: "/schemas/types.yaml#/definitions/phandle-array"

  nvidia,ddc-i2c-bus:
    description: phandle of an I2C controller used for DDC EDID
      probing
    $ref: "/schemas/types.yaml#/definitions/phandle"

  nvidia,hpd-gpio:
    description: specifies a GPIO used for hotplug detection
    maxItems: 1

  nvidia,edid:
    description: supplies a binary EDID blob
    $ref: "/schemas/types.yaml#/definitions/uint8-array"

  nvidia,panel:
    description: phandle of a display panel
    $ref: "/schemas/types.yaml#/definitions/phandle"

  nvidia,ganged-mode:
    description: contains a phandle to a second DSI controller to
      gang up with in order to support up to 8 data lanes
    $ref: "/schemas/types.yaml#/definitions/phandle"

allOf:
  - $ref: "../dsi-controller.yaml#"
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra20-dsi
              - nvidia,tegra30-dsi
    then:
      properties:
        clocks:
          items:
            - description: DSI module clock
            - description: input for the pixel clock

        clock-names:
          items:
            - const: dsi
            - const: parent
    else:
      properties:
        clocks:
          items:
            - description: DSI module clock
            - description: low-power module clock
            - description: input for the pixel clock

        clock-names:
          items:
            - const: dsi
            - const: lp
            - const: parent

  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra186-dsi
    then:
      required:
        - interrupts

unevaluatedProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names

examples:
  - |
    #include <dt-bindings/clock/tegra186-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/tegra186-powergate.h>
    #include <dt-bindings/reset/tegra186-reset.h>

    dsi@15300000 {
        compatible = "nvidia,tegra186-dsi";
        reg = <0x15300000 0x10000>;
        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&bpmp TEGRA186_CLK_DSI>,
                 <&bpmp TEGRA186_CLK_DSIA_LP>,
                 <&bpmp TEGRA186_CLK_PLLD>;
        clock-names = "dsi", "lp", "parent";
        resets = <&bpmp TEGRA186_RESET_DSI>;
        reset-names = "dsi";

        power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Encoder Pre-Processor

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^epp@[0-9a-f]+$"

  compatible:
    enum:
      - nvidia,tegra20-epp
      - nvidia,tegra30-epp
      - nvidia,tegra114-epp

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: epp

  iommus:
    maxItems: 1

  interconnects:
    maxItems: 4

  interconnect-names:
    maxItems: 4

  operating-points-v2:
    $ref: "/schemas/types.yaml#/definitions/phandle"

  power-domains:
    items:
      - description: phandle to the core power domain

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    epp@540c0000 {
        compatible = "nvidia,tegra20-epp";
        reg = <0x540c0000 0x00040000>;
        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA20_CLK_EPP>;
        resets = <&tegra_car 19>;
        reset-names = "epp";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr2d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA 2D graphics engine

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^gr2d@[0-9a-f]+$"

  compatible:
    enum:
      - nvidia,tegra20-gr2d
      - nvidia,tegra30-gr2d
      - nvidia,tegra114-gr2d

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: module clock

  resets:
    items:
      - description: module reset
      - description: memory client hotflush reset

  reset-names:
    items:
      - const: 2d
      - const: mc

  iommus:
    maxItems: 1

  interconnects:
    maxItems: 4

  interconnect-names:
    maxItems: 4

  operating-points-v2:
    $ref: "/schemas/types.yaml#/definitions/phandle"

  power-domains:
    items:
      - description: phandle to the HEG or core power domain

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/tegra20-mc.h>

    gr2d@54140000 {
        compatible = "nvidia,tegra20-gr2d";
        reg = <0x54140000 0x00040000>;
        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA20_CLK_GR2D>;
        resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
        reset-names = "2d", "mc";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA 3D graphics engine

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^gr3d@[0-9a-f]+$"

  compatible:
    enum:
      - nvidia,tegra20-gr3d
      - nvidia,tegra30-gr3d
      - nvidia,tegra114-gr3d

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    maxItems: 2

  resets:
    minItems: 2
    maxItems: 4

  reset-names:
    minItems: 2
    maxItems: 4

  iommus:
    minItems: 1
    maxItems: 2

  interconnects:
    minItems: 4
    maxItems: 10

  interconnect-names:
    minItems: 4
    maxItems: 10

  operating-points-v2:
    $ref: "/schemas/types.yaml#/definitions/phandle"

  power-domains:
    minItems: 1
    maxItems: 2

  power-domain-names:
    maxItems: 2

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra20-gr2d
    then:
      properties:
        clocks:
          items:
            - description: module clock

        clock-names:
          items:
            - const: 3d

        resets:
          items:
            - description: module reset
            - description: memory client hotflush reset

        reset-names:
          items:
            - const: 3d
            - const: mc

        iommus:
          maxItems: 1

        interconnects:
          minItems: 4
          maxItems: 4

        interconnect-names:
          minItems: 4
          maxItems: 4

        power-domains:
          items:
            - description: phandle to the TD power domain

  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra30-gr3d
    then:
      properties:
        clocks:
          items:
            - description: primary module clock
            - description: secondary module clock

        clock-names:
          items:
            - const: 3d
            - const: 3d2

        resets:
          items:
            - description: primary module reset
            - description: secondary module reset
            - description: primary memory client hotflush reset
            - description: secondary memory client hotflush reset

        reset-names:
          items:
            - const: 3d
            - const: 3d2
            - const: mc
            - const: mc2

        iommus:
          minItems: 2
          maxItems: 2

        interconnects:
          minItems: 8
          maxItems: 8

        interconnect-names:
          minItems: 8
          maxItems: 8

        power-domains:
          items:
            - description: phandle to the TD power domain
            - description: phandle to the TD2 power domain

        power-domain-names:
          items:
            - const: 3d0
            - const: 3d1

      dependencies:
        power-domains: [ power-domain-names ]

  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra114-gr2d
    then:
      properties:
        clocks:
          items:
            - description: module clock

        clock-names:
          items:
            - const: 3d

        resets:
          items:
            - description: module reset
            - description: memory client hotflush reset

        reset-names:
          items:
            - const: 3d
            - const: mc

        iommus:
          maxItems: 1

        interconnects:
          minItems: 10
          maxItems: 10

        interconnect-names:
          minItems: 10
          maxItems: 10

        power-domains:
          items:
            - description: phandle to the TD power domain

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
    #include <dt-bindings/memory/tegra20-mc.h>

    gr3d@54180000 {
        compatible = "nvidia,tegra20-gr3d";
        reg = <0x54180000 0x00040000>;
        clocks = <&tegra_car TEGRA20_CLK_GR3D>;
        resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
        reset-names = "3d", "mc";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra HDMI Output Encoder

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    pattern: "^hdmi@[0-9a-f]+$"

  compatible:
    oneOf:
      - enum:
          - nvidia,tegra20-hdmi
          - nvidia,tegra30-hdmi
          - nvidia,tegra114-hdmi
          - nvidia,tegra124-hdmi

      - items:
          - const: nvidia,tegra132-hdmi
          - const: nvidia,tegra124-hdmi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: module clock
      - description: parent clock

  clock-names:
    items:
      - const: hdmi
      - const: parent

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: hdmi

  operating-points-v2:
    $ref: "/schemas/types.yaml#/definitions/phandle"

  power-domains:
    items:
      - description: phandle to the core power domain

  hdmi-supply:
    description: supply for the +5V HDMI connector pin

  vdd-supply:
    description: regulator for supply voltage

  pll-supply:
    description: regulator for PLL

  nvidia,ddc-i2c-bus:
    description: phandle of an I2C controller used for DDC EDID
      probing
    $ref: "/schemas/types.yaml#/definitions/phandle"

  nvidia,hpd-gpio:
    description: specifies a GPIO used for hotplug detection
    maxItems: 1

  nvidia,edid:
    description: supplies a binary EDID blob
    $ref: "/schemas/types.yaml#/definitions/uint8-array"

  nvidia,panel:
    description: phandle of a display panel
    $ref: "/schemas/types.yaml#/definitions/phandle"

  "#sound-dai-cells":
    const: 0

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - reset-names
  - pll-supply
  - vdd-supply
  - nvidia,ddc-i2c-bus
  - nvidia,hpd-gpio

examples:
  - |
    #include <dt-bindings/clock/tegra124-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/gpio/tegra-gpio.h>

    hdmi@54280000 {
        compatible = "nvidia,tegra124-hdmi";
        reg = <0x54280000 0x00040000>;
        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA124_CLK_HDMI>,
                 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
        clock-names = "hdmi", "parent";
        resets = <&tegra_car 51>;
        reset-names = "hdmi";

        hdmi-supply = <&vdd_5v0_hdmi>;
        pll-supply = <&vdd_hdmi_pll>;
        vdd-supply = <&vdd_3v3_hdmi>;

        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
    };