code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Versatile Express
 *
 * Motherboard Express uATX
 * V2M-P1
 *
 * HBI-0190D
 *
 * Original memory map ("Legacy memory map" in the board's
 * Technical Reference Manual)
 *
 * WARNING! The hardware described in this file is independent from the
 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
 * correspondence between the two configurations.
 *
 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
 * CHANGES TO vexpress-v2m-rs1.dtsi!
 */
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	bus@40000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x40000000 0x40000000 0x10000000>,
			 <0x10000000 0x10000000 0x00020000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 63>;
		interrupt-map = <0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
				<0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
				<0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
				<0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
				<0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
				<0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
				<0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
				<0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
				<0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
				<0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
				<0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				<0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				<0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				<0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				<0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				<0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				<0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				<0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				<0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				<0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
				<0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
				<0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				<0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				<0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				<0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				<0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
				<0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
				<0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
				<0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				<0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				<0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				<0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
				<0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
				<0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
				<0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
				<0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
				<0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
				<0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
				<0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				<0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				<0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				<0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;

		motherboard-bus@40000000 {
			arm,hbi = <0x190>;
			arm,vexpress,site = <0>;
			compatible = "arm,vexpress,v2m-p1", "simple-bus";
			#address-cells = <2>; /* SMB chipselect number and offset */
			#size-cells = <1>;
			ranges = <0 0 0x40000000 0x04000000>,
				 <1 0 0x44000000 0x04000000>,
				 <2 0 0x48000000 0x04000000>,
				 <3 0 0x4c000000 0x04000000>,
				 <7 0 0x10000000 0x00020000>;

			flash@0,00000000 {
				compatible = "arm,vexpress-flash", "cfi-flash";
				reg = <0 0x00000000 0x04000000>,
				      <1 0x00000000 0x04000000>;
				bank-width = <4>;
				partitions {
					compatible = "arm,arm-firmware-suite";
				};
			};

			psram@2,00000000 {
				compatible = "arm,vexpress-psram", "mtd-ram";
				reg = <2 0x00000000 0x02000000>;
				bank-width = <4>;
			};

			ethernet@3,02000000 {
				compatible = "smsc,lan9118", "smsc,lan9115";
				reg = <3 0x02000000 0x10000>;
				interrupts = <15>;
				phy-mode = "mii";
				reg-io-width = <4>;
				smsc,irq-active-high;
				smsc,irq-push-pull;
				vdd33a-supply = <&v2m_fixed_3v3>;
				vddvario-supply = <&v2m_fixed_3v3>;
			};

			usb@3,03000000 {
				compatible = "nxp,usb-isp1761";
				reg = <3 0x03000000 0x20000>;
				interrupts = <16>;
				dr_mode = "peripheral";
			};

			iofpga@7,00000000 {
				compatible = "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 7 0 0x20000>;

				v2m_sysreg: sysreg@0 {
					compatible = "arm,vexpress-sysreg";
					reg = <0x00000 0x1000>;
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0 0 0x1000>;

					v2m_led_gpios: gpio@8 {
						compatible = "arm,vexpress-sysreg,sys_led";
						reg = <0x008 4>;
						gpio-controller;
						#gpio-cells = <2>;
					};

					v2m_mmc_gpios: gpio@48 {
						compatible = "arm,vexpress-sysreg,sys_mci";
						reg = <0x048 4>;
						gpio-controller;
						#gpio-cells = <2>;
					};

					v2m_flash_gpios: gpio@4c {
						compatible = "arm,vexpress-sysreg,sys_flash";
						reg = <0x04c 4>;
						gpio-controller;
						#gpio-cells = <2>;
					};
				};

				v2m_sysctl: sysctl@1000 {
					compatible = "arm,sp810", "arm,primecell";
					reg = <0x01000 0x1000>;
					clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
					clock-names = "refclk", "timclk", "apb_pclk";
					#clock-cells = <1>;
					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
					assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
					assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
				};

				/* PCI-E I2C bus */
				v2m_i2c_pcie: i2c@2000 {
					compatible = "arm,versatile-i2c";
					reg = <0x02000 0x1000>;

					#address-cells = <1>;
					#size-cells = <0>;

					pcie-switch@60 {
						compatible = "idt,89hpes32h8";
						reg = <0x60>;
					};
				};

				aaci@4000 {
					compatible = "arm,pl041", "arm,primecell";
					reg = <0x04000 0x1000>;
					interrupts = <11>;
					clocks = <&smbclk>;
					clock-names = "apb_pclk";
				};

				mmci@5000 {
					compatible = "arm,pl180", "arm,primecell";
					reg = <0x05000 0x1000>;
					interrupts = <9>, <10>;
					cd-gpios = <&v2m_mmc_gpios 0 0>;
					wp-gpios = <&v2m_mmc_gpios 1 0>;
					max-frequency = <12000000>;
					vmmc-supply = <&v2m_fixed_3v3>;
					clocks = <&v2m_clk24mhz>, <&smbclk>;
					clock-names = "mclk", "apb_pclk";
				};

				kmi@6000 {
					compatible = "arm,pl050", "arm,primecell";
					reg = <0x06000 0x1000>;
					interrupts = <12>;
					clocks = <&v2m_clk24mhz>, <&smbclk>;
					clock-names = "KMIREFCLK", "apb_pclk";
				};

				kmi@7000 {
					compatible = "arm,pl050", "arm,primecell";
					reg = <0x07000 0x1000>;
					interrupts = <13>;
					clocks = <&v2m_clk24mhz>, <&smbclk>;
					clock-names = "KMIREFCLK", "apb_pclk";
				};

				v2m_serial0: uart@9000 {
					compatible = "arm,pl011", "arm,primecell";
					reg = <0x09000 0x1000>;
					interrupts = <5>;
					clocks = <&v2m_oscclk2>, <&smbclk>;
					clock-names = "uartclk", "apb_pclk";
				};

				v2m_serial1: uart@a000 {
					compatible = "arm,pl011", "arm,primecell";
					reg = <0x0a000 0x1000>;
					interrupts = <6>;
					clocks = <&v2m_oscclk2>, <&smbclk>;
					clock-names = "uartclk", "apb_pclk";
				};

				v2m_serial2: uart@b000 {
					compatible = "arm,pl011", "arm,primecell";
					reg = <0x0b000 0x1000>;
					interrupts = <7>;
					clocks = <&v2m_oscclk2>, <&smbclk>;
					clock-names = "uartclk", "apb_pclk";
				};

				v2m_serial3: uart@c000 {
					compatible = "arm,pl011", "arm,primecell";
					reg = <0x0c000 0x1000>;
					interrupts = <8>;
					clocks = <&v2m_oscclk2>, <&smbclk>;
					clock-names = "uartclk", "apb_pclk";
				};

				wdt@f000 {
					compatible = "arm,sp805", "arm,primecell";
					reg = <0x0f000 0x1000>;
					interrupts = <0>;
					clocks = <&v2m_refclk32khz>, <&smbclk>;
					clock-names = "wdog_clk", "apb_pclk";
				};

				v2m_timer01: timer@11000 {
					compatible = "arm,sp804", "arm,primecell";
					reg = <0x11000 0x1000>;
					interrupts = <2>;
					clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
					clock-names = "timclken1", "timclken2", "apb_pclk";
				};

				v2m_timer23: timer@12000 {
					compatible = "arm,sp804", "arm,primecell";
					reg = <0x12000 0x1000>;
					interrupts = <3>;
					clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
					clock-names = "timclken1", "timclken2", "apb_pclk";
				};

				/* DVI I2C bus */
				v2m_i2c_dvi: i2c@16000 {
					compatible = "arm,versatile-i2c";
					reg = <0x16000 0x1000>;
					#address-cells = <1>;
					#size-cells = <0>;

					dvi-transmitter@39 {
						compatible = "sil,sii9022-tpi", "sil,sii9022";
						reg = <0x39>;

						ports {
							#address-cells = <1>;
							#size-cells = <0>;

							/*
							 * Both the core tile and the motherboard routes their output
							 * pads to this transmitter. The motherboard system controller
							 * can select one of them as input using a mux register in
							 * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
							 * the only platform with this specific set-up.
							 */
							port@0 {
								reg = <0>;
								dvi_bridge_in_ct: endpoint {
									remote-endpoint = <&clcd_pads_ct>;
								};
							};
							port@1 {
								reg = <1>;
								dvi_bridge_in_mb: endpoint {
									remote-endpoint = <&clcd_pads_mb>;
								};
							};
						};
					};

					dvi-transmitter@60 {
						compatible = "sil,sii9022-cpi", "sil,sii9022";
						reg = <0x60>;
					};
				};

				rtc@17000 {
					compatible = "arm,pl031", "arm,primecell";
					reg = <0x17000 0x1000>;
					interrupts = <4>;
					clocks = <&smbclk>;
					clock-names = "apb_pclk";
				};

				compact-flash@1a000 {
					compatible = "arm,vexpress-cf", "ata-generic";
					reg = <0x1a000 0x100
					       0x1a100 0xf00>;
					reg-shift = <2>;
				};

				clcd@1f000 {
					compatible = "arm,pl111", "arm,primecell";
					reg = <0x1f000 0x1000>;
					interrupt-names = "combined";
					interrupts = <14>;
					clocks = <&v2m_oscclk1>, <&smbclk>;
					clock-names = "clcdclk", "apb_pclk";
					/* 800x600 16bpp @36MHz works fine */
					max-memory-bandwidth = <54000000>;
					memory-region = <&vram>;

					port {
						clcd_pads_mb: endpoint {
							remote-endpoint = <&dvi_bridge_in_mb>;
							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
						};
					};
				};
			};

			v2m_fixed_3v3: fixed-regulator-0 {
				compatible = "regulator-fixed";
				regulator-name = "3V3";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			v2m_clk24mhz: clk24mhz {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <24000000>;
				clock-output-names = "v2m:clk24mhz";
			};

			v2m_refclk1mhz: refclk1mhz {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <1000000>;
				clock-output-names = "v2m:refclk1mhz";
			};

			v2m_refclk32khz: refclk32khz {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <32768>;
				clock-output-names = "v2m:refclk32khz";
			};

			leds {
				compatible = "gpio-leds";

				led-user1 {
					label = "v2m:green:user1";
					gpios = <&v2m_led_gpios 0 0>;
					linux,default-trigger = "heartbeat";
				};

				led-user2 {
					label = "v2m:green:user2";
					gpios = <&v2m_led_gpios 1 0>;
					linux,default-trigger = "mmc0";
				};

				led-user3 {
					label = "v2m:green:user3";
					gpios = <&v2m_led_gpios 2 0>;
					linux,default-trigger = "cpu0";
				};

				led-user4 {
					label = "v2m:green:user4";
					gpios = <&v2m_led_gpios 3 0>;
					linux,default-trigger = "cpu1";
				};

				led-user5 {
					label = "v2m:green:user5";
					gpios = <&v2m_led_gpios 4 0>;
					linux,default-trigger = "cpu2";
				};

				led-user6 {
					label = "v2m:green:user6";
					gpios = <&v2m_led_gpios 5 0>;
					linux,default-trigger = "cpu3";
				};

				led-user7 {
					label = "v2m:green:user7";
					gpios = <&v2m_led_gpios 6 0>;
					linux,default-trigger = "cpu4";
				};

				led-user8 {
					label = "v2m:green:user8";
					gpios = <&v2m_led_gpios 7 0>;
					linux,default-trigger = "cpu5";
				};
			};

			mcc {
				compatible = "arm,vexpress,config-bus";
				arm,vexpress,config-bridge = <&v2m_sysreg>;

				oscclk0 {
					/* MCC static memory clock */
					compatible = "arm,vexpress-osc";
					arm,vexpress-sysreg,func = <1 0>;
					freq-range = <25000000 60000000>;
					#clock-cells = <0>;
					clock-output-names = "v2m:oscclk0";
				};

				v2m_oscclk1: oscclk1 {
					/* CLCD clock */
					compatible = "arm,vexpress-osc";
					arm,vexpress-sysreg,func = <1 1>;
					freq-range = <23750000 65000000>;
					#clock-cells = <0>;
					clock-output-names = "v2m:oscclk1";
				};

				v2m_oscclk2: oscclk2 {
					/* IO FPGA peripheral clock */
					compatible = "arm,vexpress-osc";
					arm,vexpress-sysreg,func = <1 2>;
					freq-range = <24000000 24000000>;
					#clock-cells = <0>;
					clock-output-names = "v2m:oscclk2";
				};

				volt-vio {
					/* Logic level voltage */
					compatible = "arm,vexpress-volt";
					arm,vexpress-sysreg,func = <2 0>;
					regulator-name = "VIO";
					regulator-always-on;
					label = "VIO";
				};

				temp-mcc {
					/* MCC internal operating temperature */
					compatible = "arm,vexpress-temp";
					arm,vexpress-sysreg,func = <4 0>;
					label = "MCC";
				};

				reset {
					compatible = "arm,vexpress-reset";
					arm,vexpress-sysreg,func = <5 0>;
				};

				muxfpga {
					compatible = "arm,vexpress-muxfpga";
					arm,vexpress-sysreg,func = <7 0>;
				};

				shutdown {
					compatible = "arm,vexpress-shutdown";
					arm,vexpress-sysreg,func = <8 0>;
				};

				reboot {
					compatible = "arm,vexpress-reboot";
					arm,vexpress-sysreg,func = <9 0>;
				};

				dvimode {
					compatible = "arm,vexpress-dvimode";
					arm,vexpress-sysreg,func = <11 0>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Versatile Express
 *
 * CoreTile Express A15x2 (version with Test Chip 1)
 * Cortex-A15 MPCore (V2P-CA15)
 *
 * HBI-0237A
 */

/dts-v1/;
#include "vexpress-v2m-rs1.dtsi"

/ {
	model = "V2P-CA15";
	arm,hbi = <0x237>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0 0x80000000 0 0x40000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* Chipselect 2 is physically at 0x18000000 */
		vram: vram@18000000 {
			/* 8 MB of designated video RAM */
			compatible = "shared-dma-pool";
			reg = <0 0x18000000 0 0x00800000>;
			no-map;
		};
	};

	hdlcd@2b000000 {
		compatible = "arm,hdlcd";
		reg = <0 0x2b000000 0 0x1000>;
		interrupts = <0 85 4>;
		clocks = <&hdlcd_clk>;
		clock-names = "pxlclk";
	};

	memory-controller@2b0a0000 {
		compatible = "arm,pl341", "arm,primecell";
		reg = <0 0x2b0a0000 0 0x1000>;
		clocks = <&sys_pll>;
		clock-names = "apb_pclk";
	};

	wdt@2b060000 {
		compatible = "arm,sp805", "arm,primecell";
		status = "disabled";
		reg = <0 0x2b060000 0 0x1000>;
		interrupts = <0 98 4>;
		clocks = <&sys_pll>, <&sys_pll>;
		clock-names = "wdog_clk", "apb_pclk";
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0x2c001000 0 0x1000>,
		      <0 0x2c002000 0 0x2000>,
		      <0 0x2c004000 0 0x2000>,
		      <0 0x2c006000 0 0x2000>;
		interrupts = <1 9 0xf04>;
	};

	memory-controller@7ffd0000 {
		compatible = "arm,pl354", "arm,primecell";
		reg = <0 0x7ffd0000 0 0x1000>;
		interrupts = <0 86 4>,
			     <0 87 4>;
		clocks = <&sys_pll>;
		clock-names = "apb_pclk";
	};

	dma@7ffb0000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0 0x7ffb0000 0 0x1000>;
		interrupts = <0 92 4>,
			     <0 88 4>,
			     <0 89 4>,
			     <0 90 4>,
			     <0 91 4>;
		clocks = <&sys_pll>;
		clock-names = "apb_pclk";
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <0 68 4>,
			     <0 69 4>;
	};

	dcc {
		compatible = "arm,vexpress,config-bus";
		arm,vexpress,config-bridge = <&v2m_sysreg>;

		oscclk0 {
			/* CPU PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 0>;
			freq-range = <50000000 60000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk0";
		};

		oscclk4 {
			/* Multiplexed AXI master clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 4>;
			freq-range = <20000000 40000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk4";
		};

		hdlcd_clk: oscclk5 {
			/* HDLCD PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 5>;
			freq-range = <23750000 165000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk5";
		};

		smbclk: oscclk6 {
			/* SMB clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 6>;
			freq-range = <20000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk6";
		};

		sys_pll: oscclk7 {
			/* SYS PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 7>;
			freq-range = <20000000 60000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk7";
		};

		oscclk8 {
			/* DDR2 PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 8>;
			freq-range = <40000000 40000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk8";
		};

		volt-cores {
			/* CPU core voltage */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 0>;
			regulator-name = "Cores";
			regulator-min-microvolt = <800000>;
			regulator-max-microvolt = <1050000>;
			regulator-always-on;
			label = "Cores";
		};

		amp-cores {
			/* Total current for the two cores */
			compatible = "arm,vexpress-amp";
			arm,vexpress-sysreg,func = <3 0>;
			label = "Cores";
		};

		temp-dcc {
			/* DCC internal temperature */
			compatible = "arm,vexpress-temp";
			arm,vexpress-sysreg,func = <4 0>;
			label = "DCC";
		};

		power-cores {
			/* Total power */
			compatible = "arm,vexpress-power";
			arm,vexpress-sysreg,func = <12 0>;
			label = "Cores";
		};

		energy {
			/* Total energy */
			compatible = "arm,vexpress-energy";
			arm,vexpress-sysreg,func = <13 0>;
			label = "Cores";
		};
	};

	bus@8000000 {
		ranges = <0x8000000 0 0x8000000 0x18000000>;
	};

	site2: hsb@40000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x40000000 0x3fef0000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 3>;
		interrupt-map = <0 0 &gic 0 36 4>,
				<0 1 &gic 0 37 4>,
				<0 2 &gic 0 38 4>,
				<0 3 &gic 0 39 4>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Versatile Express
 *
 * CoreTile Express A15x2 A7x3
 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
 *
 * HBI-0249A
 */

/dts-v1/;
#include "vexpress-v2m-rs1.dtsi"

/ {
	model = "V2P-CA15_CA7";
	arm,hbi = <0x249>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			cci-control-port = <&cci_control1>;
			cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <990>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
			cci-control-port = <&cci_control1>;
			cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <990>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x100>;
			cci-control-port = <&cci_control2>;
			cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
			capacity-dmips-mhz = <516>;
			dynamic-power-coefficient = <133>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x101>;
			cci-control-port = <&cci_control2>;
			cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
			capacity-dmips-mhz = <516>;
			dynamic-power-coefficient = <133>;
		};

		cpu4: cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x102>;
			cci-control-port = <&cci_control2>;
			cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
			capacity-dmips-mhz = <516>;
			dynamic-power-coefficient = <133>;
		};

		idle-states {
			CLUSTER_SLEEP_BIG: cluster-sleep-big {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <1000>;
				exit-latency-us = <700>;
				min-residency-us = <2000>;
			};

			CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <1000>;
				exit-latency-us = <500>;
				min-residency-us = <2500>;
			};
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0 0x80000000 0 0x40000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* Chipselect 2 is physically at 0x18000000 */
		vram: vram@18000000 {
			/* 8 MB of designated video RAM */
			compatible = "shared-dma-pool";
			reg = <0 0x18000000 0 0x00800000>;
			no-map;
		};
	};

	wdt@2a490000 {
		compatible = "arm,sp805", "arm,primecell";
		reg = <0 0x2a490000 0 0x1000>;
		interrupts = <0 98 4>;
		clocks = <&oscclk6a>, <&oscclk6a>;
		clock-names = "wdog_clk", "apb_pclk";
	};

	hdlcd@2b000000 {
		compatible = "arm,hdlcd";
		reg = <0 0x2b000000 0 0x1000>;
		interrupts = <0 85 4>;
		clocks = <&hdlcd_clk>;
		clock-names = "pxlclk";
	};

	memory-controller@2b0a0000 {
		compatible = "arm,pl341", "arm,primecell";
		reg = <0 0x2b0a0000 0 0x1000>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0x2c001000 0 0x1000>,
		      <0 0x2c002000 0 0x2000>,
		      <0 0x2c004000 0 0x2000>,
		      <0 0x2c006000 0 0x2000>;
		interrupts = <1 9 0xf04>;
	};

	cci@2c090000 {
		compatible = "arm,cci-400";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0 0x2c090000 0 0x1000>;
		ranges = <0x0 0x0 0x2c090000 0x10000>;

		cci_control1: slave-if@4000 {
			compatible = "arm,cci-400-ctrl-if";
			interface-type = "ace";
			reg = <0x4000 0x1000>;
		};

		cci_control2: slave-if@5000 {
			compatible = "arm,cci-400-ctrl-if";
			interface-type = "ace";
			reg = <0x5000 0x1000>;
		};

		pmu@9000 {
			 compatible = "arm,cci-400-pmu,r0";
			 reg = <0x9000 0x5000>;
			 interrupts = <0 105 4>,
				      <0 101 4>,
				      <0 102 4>,
				      <0 103 4>,
				      <0 104 4>;
		};
	};

	memory-controller@7ffd0000 {
		compatible = "arm,pl354", "arm,primecell";
		reg = <0 0x7ffd0000 0 0x1000>;
		interrupts = <0 86 4>,
			     <0 87 4>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
	};

	dma@7ff00000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0 0x7ff00000 0 0x1000>;
		interrupts = <0 92 4>,
			     <0 88 4>,
			     <0 89 4>,
			     <0 90 4>,
			     <0 91 4>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
	};

        scc@7fff0000 {
		compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
		reg = <0 0x7fff0000 0 0x1000>;
		interrupts = <0 95 4>;
        };

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
	};

	pmu-a15 {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <0 68 4>,
			     <0 69 4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>;
	};

	pmu-a7 {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <0 128 4>,
			     <0 129 4>,
			     <0 130 4>;
		interrupt-affinity = <&cpu2>,
				     <&cpu3>,
				     <&cpu4>;
	};

	oscclk6a: oscclk6a {
		/* Reference 24MHz clock */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "oscclk6a";
	};

	dcc {
		compatible = "arm,vexpress,config-bus";
		arm,vexpress,config-bridge = <&v2m_sysreg>;

		oscclk0 {
			/* A15 PLL 0 reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 0>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk0";
		};

		oscclk1 {
			/* A15 PLL 1 reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 1>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk1";
		};

		oscclk2 {
			/* A7 PLL 0 reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 2>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk2";
		};

		oscclk3 {
			/* A7 PLL 1 reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 3>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk3";
		};

		oscclk4 {
			/* External AXI master clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 4>;
			freq-range = <20000000 40000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk4";
		};

		hdlcd_clk: oscclk5 {
			/* HDLCD PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 5>;
			freq-range = <23750000 165000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk5";
		};

		smbclk: oscclk6 {
			/* Static memory controller clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 6>;
			freq-range = <20000000 40000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk6";
		};

		oscclk7 {
			/* SYS PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 7>;
			freq-range = <17000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk7";
		};

		oscclk8 {
			/* DDR2 PLL reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 8>;
			freq-range = <20000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk8";
		};

		volt-a15 {
			/* A15 CPU core voltage */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 0>;
			regulator-name = "A15 Vcore";
			regulator-min-microvolt = <800000>;
			regulator-max-microvolt = <1050000>;
			regulator-always-on;
			label = "A15 Vcore";
		};

		volt-a7 {
			/* A7 CPU core voltage */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 1>;
			regulator-name = "A7 Vcore";
			regulator-min-microvolt = <800000>;
			regulator-max-microvolt = <1050000>;
			regulator-always-on;
			label = "A7 Vcore";
		};

		amp-a15 {
			/* Total current for the two A15 cores */
			compatible = "arm,vexpress-amp";
			arm,vexpress-sysreg,func = <3 0>;
			label = "A15 Icore";
		};

		amp-a7 {
			/* Total current for the three A7 cores */
			compatible = "arm,vexpress-amp";
			arm,vexpress-sysreg,func = <3 1>;
			label = "A7 Icore";
		};

		temp-dcc {
			/* DCC internal temperature */
			compatible = "arm,vexpress-temp";
			arm,vexpress-sysreg,func = <4 0>;
			label = "DCC";
		};

		power-a15 {
			/* Total power for the two A15 cores */
			compatible = "arm,vexpress-power";
			arm,vexpress-sysreg,func = <12 0>;
			label = "A15 Pcore";
		};

		power-a7 {
			/* Total power for the three A7 cores */
			compatible = "arm,vexpress-power";
			arm,vexpress-sysreg,func = <12 1>;
			label = "A7 Pcore";
		};

		energy-a15 {
			/* Total energy for the two A15 cores */
			compatible = "arm,vexpress-energy";
			arm,vexpress-sysreg,func = <13 0>, <13 1>;
			label = "A15 Jcore";
		};

		energy-a7 {
			/* Total energy for the three A7 cores */
			compatible = "arm,vexpress-energy";
			arm,vexpress-sysreg,func = <13 2>, <13 3>;
			label = "A7 Jcore";
		};
	};

	etb@20010000 {
		compatible = "arm,coresight-etb10", "arm,primecell";
		reg = <0 0x20010000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		in-ports {
			port {
				etb_in_port: endpoint {
					remote-endpoint = <&replicator_out_port0>;
				};
			};
		};
	};

	tpiu@20030000 {
		compatible = "arm,coresight-tpiu", "arm,primecell";
		reg = <0 0x20030000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		in-ports {
			port {
				tpiu_in_port: endpoint {
					remote-endpoint = <&replicator_out_port1>;
				};
			};
		};
	};

	replicator {
		/* non-configurable replicators don't show up on the
		 * AMBA bus.  As such no need to add "arm,primecell".
		 */
		compatible = "arm,coresight-static-replicator";

		out-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				replicator_out_port0: endpoint {
					remote-endpoint = <&etb_in_port>;
				};
			};

			port@1 {
				reg = <1>;
				replicator_out_port1: endpoint {
					remote-endpoint = <&tpiu_in_port>;
				};
			};
		};

		in-ports {
			port {
				replicator_in_port0: endpoint {
					remote-endpoint = <&funnel_out_port0>;
				};
			};
		};
	};

	funnel@20040000 {
		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
		reg = <0 0x20040000 0 0x1000>;

		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				funnel_out_port0: endpoint {
					remote-endpoint =
						<&replicator_in_port0>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_in_port0: endpoint {
					remote-endpoint = <&ptm0_out_port>;
				};
			};

			port@1 {
				reg = <1>;
				funnel_in_port1: endpoint {
					remote-endpoint = <&ptm1_out_port>;
				};
			};

			port@2 {
				reg = <2>;
				funnel_in_port2: endpoint {
					remote-endpoint = <&etm0_out_port>;
				};
			};

			/* Input port #3 is for ITM, not supported here */

			port@4 {
				reg = <4>;
				funnel_in_port4: endpoint {
					remote-endpoint = <&etm1_out_port>;
				};
			};

			port@5 {
				reg = <5>;
				funnel_in_port5: endpoint {
					remote-endpoint = <&etm2_out_port>;
				};
			};
		};
	};

	ptm@2201c000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2201c000 0 0x1000>;

		cpu = <&cpu0>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				ptm0_out_port: endpoint {
					remote-endpoint = <&funnel_in_port0>;
				};
			};
		};
	};

	ptm@2201d000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2201d000 0 0x1000>;

		cpu = <&cpu1>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				ptm1_out_port: endpoint {
					remote-endpoint = <&funnel_in_port1>;
				};
			};
		};
	};

	etm@2203c000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2203c000 0 0x1000>;

		cpu = <&cpu2>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				etm0_out_port: endpoint {
					remote-endpoint = <&funnel_in_port2>;
				};
			};
		};
	};

	etm@2203d000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2203d000 0 0x1000>;

		cpu = <&cpu3>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				etm1_out_port: endpoint {
					remote-endpoint = <&funnel_in_port4>;
				};
			};
		};
	};

	etm@2203e000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0 0x2203e000 0 0x1000>;

		cpu = <&cpu4>;
		clocks = <&oscclk6a>;
		clock-names = "apb_pclk";
		out-ports {
			port {
				etm2_out_port: endpoint {
					remote-endpoint = <&funnel_in_port5>;
				};
			};
		};
	};

	smb: bus@8000000 {
		ranges = <0x8000000 0 0x8000000 0x18000000>;
	};

	site2: hsb@40000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x40000000 0x3fef0000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 3>;
		interrupt-map = <0 0 &gic 0 36 4>,
				<0 1 &gic 0 37 4>,
				<0 2 &gic 0 38 4>,
				<0 3 &gic 0 39 4>;
	};
};

&nor_flash {
	/*
	 * Unfortunately, accessing the flash disturbs the CPU idle states
	 * (suspend) and CPU hotplug of this platform. For this reason, flash
	 * hardware access is disabled by default on this platform alone.
	 */
	status = "disabled";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Versatile Express
 *
 * CoreTile Express A5x2
 * Cortex-A5 MPCore (V2P-CA5s)
 *
 * HBI-0225B
 */

/dts-v1/;
#include "vexpress-v2m-rs1.dtsi"

/ {
	model = "V2P-CA5s";
	arm,hbi = <0x225>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	chosen { };

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			reg = <0>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			reg = <1>;
			next-level-cache = <&L2>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* Chipselect 2 is physically at 0x18000000 */
		vram: vram@18000000 {
			/* 8 MB of designated video RAM */
			compatible = "shared-dma-pool";
			reg = <0x18000000 0x00800000>;
			no-map;
		};
	};

	hdlcd@2a110000 {
		compatible = "arm,hdlcd";
		reg = <0x2a110000 0x1000>;
		interrupts = <0 85 4>;
		clocks = <&hdlcd_clk>;
		clock-names = "pxlclk";
	};

	memory-controller@2a150000 {
		compatible = "arm,pl341", "arm,primecell";
		reg = <0x2a150000 0x1000>;
		clocks = <&axi_clk>;
		clock-names = "apb_pclk";
	};

	memory-controller@2a190000 {
		compatible = "arm,pl354", "arm,primecell";
		reg = <0x2a190000 0x1000>;
		interrupts = <0 86 4>,
			     <0 87 4>;
		clocks = <&axi_clk>;
		clock-names = "apb_pclk";
	};

	scu@2c000000 {
		compatible = "arm,cortex-a5-scu";
		reg = <0x2c000000 0x58>;
	};

	timer@2c000600 {
		compatible = "arm,cortex-a5-twd-timer";
		reg = <0x2c000600 0x20>;
		interrupts = <1 13 0x304>;
	};

	timer@2c000200 {
		compatible = "arm,cortex-a5-global-timer",
		             "arm,cortex-a9-global-timer";
		reg = <0x2c000200 0x20>;
		interrupts = <1 11 0x304>;
		clocks = <&cpu_clk>;
	};

	watchdog@2c000620 {
		compatible = "arm,cortex-a5-twd-wdt";
		reg = <0x2c000620 0x20>;
		interrupts = <1 14 0x304>;
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x2c001000 0x1000>,
		      <0x2c000100 0x100>;
	};

	L2: cache-controller@2c0f0000 {
		compatible = "arm,pl310-cache";
		reg = <0x2c0f0000 0x1000>;
		interrupts = <0 84 4>;
		cache-level = <2>;
	};

	pmu {
		compatible = "arm,cortex-a5-pmu";
		interrupts = <0 68 4>,
			     <0 69 4>;
	};

	dcc {
		compatible = "arm,vexpress,config-bus";
		arm,vexpress,config-bridge = <&v2m_sysreg>;

		cpu_clk: oscclk0 {
			/* CPU and internal AXI reference clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 0>;
			freq-range = <50000000 100000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk0";
		};

		axi_clk: oscclk1 {
			/* Multiplexed AXI master clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 1>;
			freq-range = <5000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk1";
		};

		oscclk2 {
			/* DDR2 */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 2>;
			freq-range = <80000000 120000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk2";
		};

		hdlcd_clk: oscclk3 {
			/* HDLCD */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 3>;
			freq-range = <23750000 165000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk3";
		};

		oscclk4 {
			/* Test chip gate configuration */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 4>;
			freq-range = <80000000 80000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk4";
		};

		smbclk: oscclk5 {
			/* SMB clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 5>;
			freq-range = <25000000 60000000>;
			#clock-cells = <0>;
			clock-output-names = "oscclk5";
		};

		temp-dcc {
			/* DCC internal operating temperature */
			compatible = "arm,vexpress-temp";
			arm,vexpress-sysreg,func = <4 0>;
			label = "DCC";
		};
	};

	smb: bus@8000000 {
		ranges = <0 0x8000000 0x18000000>;
	};

	site2: hsb@40000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x40000000 0x40000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 3>;
		interrupt-map = <0 0 &gic 0 36 4>,
				<0 1 &gic 0 37 4>,
				<0 2 &gic 0 38 4>,
				<0 3 &gic 0 39 4>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Versatile Express
 *
 * CoreTile Express A9x4
 * Cortex-A9 MPCore (V2P-CA9)
 *
 * HBI-0191B
 */

/dts-v1/;
#include "vexpress-v2m.dtsi"

/ {
	model = "V2P-CA9";
	arm,hbi = <0x191>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	chosen { };

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		A9_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			next-level-cache = <&L2>;
		};

		A9_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		A9_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			next-level-cache = <&L2>;
		};

		A9_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			next-level-cache = <&L2>;
		};
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x40000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* Chipselect 3 is physically at 0x4c000000 */
		vram: vram@4c000000 {
			/* 8 MB of designated video RAM */
			compatible = "shared-dma-pool";
			reg = <0x4c000000 0x00800000>;
			no-map;
		};
	};

	clcd@10020000 {
		compatible = "arm,pl111", "arm,primecell";
		reg = <0x10020000 0x1000>;
		interrupt-names = "combined";
		interrupts = <0 44 4>;
		clocks = <&oscclk1>, <&oscclk2>;
		clock-names = "clcdclk", "apb_pclk";
		/* 1024x768 16bpp @65MHz */
		max-memory-bandwidth = <95000000>;

		port {
			clcd_pads_ct: endpoint {
				remote-endpoint = <&dvi_bridge_in_ct>;
				arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
			};
		};
	};

	memory-controller@100e0000 {
		compatible = "arm,pl341", "arm,primecell";
		reg = <0x100e0000 0x1000>;
		clocks = <&oscclk2>;
		clock-names = "apb_pclk";
	};

	memory-controller@100e1000 {
		compatible = "arm,pl354", "arm,primecell";
		reg = <0x100e1000 0x1000>;
		interrupts = <0 45 4>,
			     <0 46 4>;
		clocks = <&oscclk2>;
		clock-names = "apb_pclk";
	};

	timer@100e4000 {
		compatible = "arm,sp804", "arm,primecell";
		reg = <0x100e4000 0x1000>;
		interrupts = <0 48 4>,
			     <0 49 4>;
		clocks = <&oscclk2>, <&oscclk2>, <&oscclk2>;
		clock-names = "timer0clk", "timer1clk", "apb_pclk";
		status = "disabled";
	};

	watchdog@100e5000 {
		compatible = "arm,sp805", "arm,primecell";
		reg = <0x100e5000 0x1000>;
		interrupts = <0 51 4>;
		clocks = <&oscclk2>, <&oscclk2>;
		clock-names = "wdog_clk", "apb_pclk";
	};

	scu@1e000000 {
		compatible = "arm,cortex-a9-scu";
		reg = <0x1e000000 0x58>;
	};

	timer@1e000600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x1e000600 0x20>;
		interrupts = <1 13 0xf04>;
	};

	watchdog@1e000620 {
		compatible = "arm,cortex-a9-twd-wdt";
		reg = <0x1e000620 0x20>;
		interrupts = <1 14 0xf04>;
	};

	gic: interrupt-controller@1e001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x1e001000 0x1000>,
		      <0x1e000100 0x100>;
	};

	L2: cache-controller@1e00a000 {
		compatible = "arm,pl310-cache";
		reg = <0x1e00a000 0x1000>;
		interrupts = <0 43 4>;
		cache-unified;
		cache-level = <2>;
		arm,data-latency = <1 1 1>;
		arm,tag-latency = <1 1 1>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 60 4>,
			     <0 61 4>,
			     <0 62 4>,
			     <0 63 4>;
		interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;

	};

	dcc {
		compatible = "arm,vexpress,config-bus";
		arm,vexpress,config-bridge = <&v2m_sysreg>;

		oscclk0: extsaxiclk {
			/* ACLK clock to the AXI master port on the test chip */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 0>;
			freq-range = <30000000 50000000>;
			#clock-cells = <0>;
			clock-output-names = "extsaxiclk";
		};

		oscclk1: clcdclk {
			/* Reference clock for the CLCD */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 1>;
			freq-range = <10000000 80000000>;
			#clock-cells = <0>;
			clock-output-names = "clcdclk";
		};

		smbclk: oscclk2: tcrefclk {
			/* Reference clock for the test chip internal PLLs */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 2>;
			freq-range = <33000000 100000000>;
			#clock-cells = <0>;
			clock-output-names = "tcrefclk";
		};

		volt-vd10 {
			/* Test Chip internal logic voltage */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 0>;
			regulator-name = "VD10";
			regulator-always-on;
			label = "VD10";
		};

		volt-vd10-s2 {
			/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 1>;
			regulator-name = "VD10_S2";
			regulator-always-on;
			label = "VD10_S2";
		};

		volt-vd10-s3 {
			/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 2>;
			regulator-name = "VD10_S3";
			regulator-always-on;
			label = "VD10_S3";
		};

		volt-vcc1v8 {
			/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 3>;
			regulator-name = "VCC1V8";
			regulator-always-on;
			label = "VCC1V8";
		};

		volt-ddr2vtt {
			/* DDR2 SDRAM VTT termination voltage */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 4>;
			regulator-name = "DDR2VTT";
			regulator-always-on;
			label = "DDR2VTT";
		};

		volt-vcc3v3 {
			/* Local board supply for miscellaneous logic external to the Test Chip */
			arm,vexpress-sysreg,func = <2 5>;
			compatible = "arm,vexpress-volt";
			regulator-name = "VCC3V3";
			regulator-always-on;
			label = "VCC3V3";
		};

		amp-vd10-s2 {
			/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
			compatible = "arm,vexpress-amp";
			arm,vexpress-sysreg,func = <3 0>;
			label = "VD10_S2";
		};

		amp-vd10-s3 {
			/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
			compatible = "arm,vexpress-amp";
			arm,vexpress-sysreg,func = <3 1>;
			label = "VD10_S3";
		};

		power-vd10-s2 {
			/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
			compatible = "arm,vexpress-power";
			arm,vexpress-sysreg,func = <12 0>;
			label = "PVD10_S2";
		};

		power-vd10-s3 {
			/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
			compatible = "arm,vexpress-power";
			arm,vexpress-sysreg,func = <12 1>;
			label = "PVD10_S3";
		};
	};

	site2: hsb@e0000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xe0000000 0x20000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 3>;
		interrupt-map = <0 0 &gic 0 36 4>,
				<0 1 &gic 0 37 4>,
				<0 2 &gic 0 38 4>,
				<0 3 &gic 0 39 4>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2014-2020 Toradex
 */

/ {
	chosen {
		stdout-path = "serial0:115200n8";
	};

	clk16m: clk16m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <16000000>;
	};

	panel: panel {
		compatible = "edt,et057090dhu";
		backlight = <&bl>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&dcu_out>;
			};
		};
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_5v0: regulator-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_usbh_vbus: regulator-usbh-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbh1_reg>;
		regulator-name = "VCC_USB[1-4]";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; /* USBH_PEN resp. USBH_P_EN */
		vin-supply = <&reg_5v0>;
	};
};

&bl {
	brightness-levels = <0 4 8 16 32 64 128 255>;
	default-brightness-level = <6>;
	power-supply = <&reg_3v3>;
	status  = "okay";
};

&dcu0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dcu0_1>;
	status = "okay";

	port {
		dcu_out: endpoint {
			remote-endpoint = <&panel_in>;
		};
	};
};

&dspi1 {
	status = "okay";

	mcp2515can: can@0 {
		compatible = "microchip,mcp2515";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_can_int>;
		reg = <0>;
		clocks = <&clk16m>;
		spi-max-frequency = <10000000>;
		interrupt-parent = <&gpio1>;
		interrupts = <11 IRQ_TYPE_EDGE_RISING>;
	};
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	status = "okay";
};

&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";
};

&i2c0 {
	status = "okay";

	/* M41T0M6 real time clock on carrier board */
	rtc: rtc@68 {
		compatible = "st,m41t0";
		reg = <0x68>;
	};
};

&pwm0 {
	status = "okay";
};

&pwm1 {
	status = "okay";
};

&reg_module_3v3 {
	vin-supply = <&reg_3v3>;
};

&tcon0 {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&usbh1 {
	vbus-supply = <&reg_usbh_vbus>;
};

&iomuxc {
	vf610-colibri {
		pinctrl_can_int: can_int {
			fsl,pins = <
				VF610_PAD_PTB21__GPIO_43	0x22ed
			>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2014-2020 Toradex
 *
 */

/ {
	aliases {
		ethernet0 = &fec1;
		ethernet1 = &fec0;
	};

	bl: backlight {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_bl_on>;
		pwms = <&pwm0 0 5000000 0>;
		enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
		status = "disabled";
	};

	reg_module_3v3: regulator-module-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_module_3v3_avdd: regulator-module-3v3-avdd {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3_AVDD_AUDIO";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&adc0 {
	status = "okay";
	vref-supply = <&reg_module_3v3_avdd>;
};

&adc1 {
	status = "okay";
	vref-supply = <&reg_module_3v3_avdd>;
};

&can0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan0>;
	status = "disabled";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "disabled";
};

&clks {
	assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
			  <&clks VF610_CLK_ENET_TS_SEL>;
	assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
				 <&clks VF610_CLK_ENET_50M>;
};

&dspi1 {
	bus-num = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi1>;
};

&edma0 {
	status = "okay";
};

&edma1 {
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
	disable-wp;
};

&fec1 {
	phy-mode = "rmii";
	phy-supply = <&reg_module_3v3>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
};

&i2c0 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c0>;
	pinctrl-1 = <&pinctrl_i2c0_gpio>;
	scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};

&nfc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nfc>;
	status = "okay";

	nand@0 {
		compatible = "fsl,vf610-nfc-nandcs";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		nand-bus-width = <8>;
		nand-ecc-mode = "hw";
		nand-ecc-strength = <32>;
		nand-ecc-step-size = <2048>;
		nand-on-flash-bbt;
	};
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm0>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
};

&usbdev0 {
	disable-over-current;
	status = "okay";
};

&usbh1 {
	disable-over-current;
	status = "okay";
};

&usbmisc0 {
	status = "okay";
};

&usbmisc1 {
	status = "okay";
};

&usbphy0 {
	status = "okay";
};

&usbphy1 {
	status = "okay";
};

&iomuxc {
	vf610-colibri {
		pinctrl_flexcan0: can0grp {
			fsl,pins = <
				VF610_PAD_PTB14__CAN0_RX	0x31F1
				VF610_PAD_PTB15__CAN0_TX	0x31F2
			>;
		};

		pinctrl_flexcan1: can1grp {
			fsl,pins = <
				VF610_PAD_PTB16__CAN1_RX	0x31F1
				VF610_PAD_PTB17__CAN1_TX	0x31F2
			>;
		};

		pinctrl_gpio_ext: gpio_ext {
			fsl,pins = <
				VF610_PAD_PTD10__GPIO_89	0x22ed /* EXT_IO_0 */
				VF610_PAD_PTD9__GPIO_88		0x22ed /* EXT_IO_1 */
				VF610_PAD_PTD26__GPIO_68	0x22ed /* EXT_IO_2 */
			>;
		};

		pinctrl_dcu0_1: dcu0grp_1 {
			fsl,pins = <
				VF610_PAD_PTE0__DCU0_HSYNC	0x1902
				VF610_PAD_PTE1__DCU0_VSYNC	0x1902
				VF610_PAD_PTE2__DCU0_PCLK	0x1902
				VF610_PAD_PTE4__DCU0_DE		0x1902
				VF610_PAD_PTE5__DCU0_R0		0x1902
				VF610_PAD_PTE6__DCU0_R1		0x1902
				VF610_PAD_PTE7__DCU0_R2		0x1902
				VF610_PAD_PTE8__DCU0_R3		0x1902
				VF610_PAD_PTE9__DCU0_R4		0x1902
				VF610_PAD_PTE10__DCU0_R5	0x1902
				VF610_PAD_PTE11__DCU0_R6	0x1902
				VF610_PAD_PTE12__DCU0_R7	0x1902
				VF610_PAD_PTE13__DCU0_G0	0x1902
				VF610_PAD_PTE14__DCU0_G1	0x1902
				VF610_PAD_PTE15__DCU0_G2	0x1902
				VF610_PAD_PTE16__DCU0_G3	0x1902
				VF610_PAD_PTE17__DCU0_G4	0x1902
				VF610_PAD_PTE18__DCU0_G5	0x1902
				VF610_PAD_PTE19__DCU0_G6	0x1902
				VF610_PAD_PTE20__DCU0_G7	0x1902
				VF610_PAD_PTE21__DCU0_B0	0x1902
				VF610_PAD_PTE22__DCU0_B1	0x1902
				VF610_PAD_PTE23__DCU0_B2	0x1902
				VF610_PAD_PTE24__DCU0_B3	0x1902
				VF610_PAD_PTE25__DCU0_B4	0x1902
				VF610_PAD_PTE26__DCU0_B5	0x1902
				VF610_PAD_PTE27__DCU0_B6	0x1902
				VF610_PAD_PTE28__DCU0_B7	0x1902
			>;
		};

		pinctrl_dspi1: dspi1grp {
			fsl,pins = <
				VF610_PAD_PTD5__DSPI1_CS0		0x33e2
				VF610_PAD_PTD6__DSPI1_SIN		0x33e1
				VF610_PAD_PTD7__DSPI1_SOUT		0x33e2
				VF610_PAD_PTD8__DSPI1_SCK		0x33e2
			>;
		};

		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
				VF610_PAD_PTA25__ESDHC1_CMD	0x31ef
				VF610_PAD_PTA26__ESDHC1_DAT0	0x31ef
				VF610_PAD_PTA27__ESDHC1_DAT1	0x31ef
				VF610_PAD_PTA28__ESDHC1_DATA2	0x31ef
				VF610_PAD_PTA29__ESDHC1_DAT3	0x31ef
				VF610_PAD_PTB20__GPIO_42	0x219d
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				VF610_PAD_PTA6__RMII_CLKOUT		0x30d2
				VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
				VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
				VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
				VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
				VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
				VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
				VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
				VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
				VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
			>;
		};

		pinctrl_gpio_bl_on: gpio_bl_on {
			fsl,pins = <
				VF610_PAD_PTC0__GPIO_45		0x22ef
			>;
		};

		pinctrl_i2c0: i2c0grp {
			fsl,pins = <
				VF610_PAD_PTB14__I2C0_SCL		0x37ff
				VF610_PAD_PTB15__I2C0_SDA		0x37ff
			>;
		};

		pinctrl_i2c0_gpio: i2c0gpiogrp {
			fsl,pins = <
				VF610_PAD_PTB14__GPIO_36		0x37ff
				VF610_PAD_PTB15__GPIO_37		0x37ff
			>;
		};

		pinctrl_nfc: nfcgrp {
			fsl,pins = <
				VF610_PAD_PTD23__NF_IO7		0x28df
				VF610_PAD_PTD22__NF_IO6		0x28df
				VF610_PAD_PTD21__NF_IO5		0x28df
				VF610_PAD_PTD20__NF_IO4		0x28df
				VF610_PAD_PTD19__NF_IO3		0x28df
				VF610_PAD_PTD18__NF_IO2		0x28df
				VF610_PAD_PTD17__NF_IO1		0x28df
				VF610_PAD_PTD16__NF_IO0		0x28df
				VF610_PAD_PTB24__NF_WE_B	0x28c2
				VF610_PAD_PTB25__NF_CE0_B	0x28c2
				VF610_PAD_PTB27__NF_RE_B	0x28c2
				VF610_PAD_PTC26__NF_RB_B	0x283d
				VF610_PAD_PTC27__NF_ALE		0x28c2
				VF610_PAD_PTC28__NF_CLE		0x28c2
			>;
		};

		pinctrl_pwm0: pwm0grp {
			fsl,pins = <
				VF610_PAD_PTB0__FTM0_CH0		0x1182
				VF610_PAD_PTB1__FTM0_CH1		0x1182
			>;
		};

		pinctrl_pwm1: pwm1grp {
			fsl,pins = <
				VF610_PAD_PTB8__FTM1_CH0		0x1182
				VF610_PAD_PTB9__FTM1_CH1		0x1182
			>;
		};

		pinctrl_uart0: uart0grp {
			fsl,pins = <
				VF610_PAD_PTB10__UART0_TX		0x21a2
				VF610_PAD_PTB11__UART0_RX		0x21a1
				VF610_PAD_PTB12__UART0_RTS		0x21a2
				VF610_PAD_PTB13__UART0_CTS		0x21a1
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				VF610_PAD_PTB4__UART1_TX		0x21a2
				VF610_PAD_PTB5__UART1_RX		0x21a1
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				VF610_PAD_PTD0__UART2_TX		0x21a2
				VF610_PAD_PTD1__UART2_RX		0x21a1
				VF610_PAD_PTD2__UART2_RTS		0x21a2
				VF610_PAD_PTD3__UART2_CTS		0x21a1
			>;
		};

		pinctrl_usbh1_reg: gpio_usb_vbus {
			fsl,pins = <
				VF610_PAD_PTD4__GPIO_83			0x22ed
			>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2014-2020 Toradex
 */

/dts-v1/;
#include "vf500-colibri.dtsi"
#include "vf-colibri-eval-v3.dtsi"

/ {
	model = "Toradex Colibri VF50 on Colibri Evaluation Board";
	compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500";
};

&touchscreen {
	vf50-ts-min-pressure = <200>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2014-2020 Toradex
 */

#include "vf500.dtsi"
#include "vf-colibri.dtsi"

/ {
	model = "Toradex Colibri VF50 COM";
	compatible = "toradex,vf500-colibri_vf50", "fsl,vf500";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x8000000>;
	};

	touchscreen: vf50-touchscreen {
		compatible = "toradex,vf50-touchscreen";
		io-channels = <&adc1 0>,<&adc0 0>,
				<&adc0 1>,<&adc1 2>;
		xp-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
		xm-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
		yp-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
		ym-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
		interrupt-parent = <&gpio0>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "idle","default","gpios";
		pinctrl-0 = <&pinctrl_touchctrl_idle>;
		pinctrl-1 = <&pinctrl_touchctrl_default>;
		pinctrl-2 = <&pinctrl_touchctrl_gpios>;
		vf50-ts-min-pressure = <200>;
		status = "disabled";
	};
};

&nfc {
	assigned-clocks = <&clks VF610_CLK_NFC>;
	assigned-clock-rates = <33000000>;
};

&iomuxc {
	vf610-colibri {
		pinctrl_touchctrl_idle: touchctrl_idle {
			fsl,pins = <
				VF610_PAD_PTA18__GPIO_8		0x006d
				VF610_PAD_PTA19__GPIO_9		0x006c
				>;
		};

		pinctrl_touchctrl_default: touchctrl_default {
			fsl,pins = <
				VF610_PAD_PTA18__ADC0_SE0	0x0040
				VF610_PAD_PTA19__ADC0_SE1	0x0040
				VF610_PAD_PTA16__ADC1_SE0	0x0040
				VF610_PAD_PTB2__ADC1_SE2	0x0040
				>;
		};

		pinctrl_touchctrl_gpios: touchctrl_gpios {
			fsl,pins = <
				VF610_PAD_PTA23__GPIO_13	0x22e9
				VF610_PAD_PTB23__GPIO_93	0x22e9
				VF610_PAD_PTA22__GPIO_12	0x22e9
				VF610_PAD_PTA11__GPIO_4		0x22e9
				>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright 2013 Freescale Semiconductor, Inc.

#include "vfxxx.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };
	aliases { };

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		a5_cpu: cpu@0 {
			compatible = "arm,cortex-a5";
			device_type = "cpu";
			reg = <0x0>;
		};
	};

	soc {
		bus@40000000 {

			intc: interrupt-controller@40003000 {
				compatible = "arm,cortex-a9-gic";
				#interrupt-cells = <3>;
				interrupt-controller;
				interrupt-parent = <&intc>;
				reg = <0x40003000 0x1000>,
				      <0x40002100 0x100>;
			};

			global_timer: timer@40002200 {
				compatible = "arm,cortex-a9-global-timer";
				reg = <0x40002200 0x20>;
				interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
				interrupt-parent = <&intc>;
				clocks = <&clks VF610_CLK_PLATFORM_BUS>;
			};
		};

		bus@40080000 {
			pmu@40089000 {
				compatible = "arm,cortex-a5-pmu";
				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-affinity = <&a5_cpu>;
				reg = <0x40089000 0x1000>;
			};
		};

	};
};

&mscm_ir {
	interrupt-parent = <&intc>;
};

&wdoga5 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2018
 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
 */

/dts-v1/;
#include "vf610.dtsi"

/ {
	model = "Liebherr BK4 controller";
	compatible = "lwn,bk4", "fsl,vf610";

	chosen {
		stdout-path = &uart1;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x8000000>;
	};

	audio_ext: oscillator-audio {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};

	enet_ext: oscillator-ethernet {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		/* LED D5 */
		led0: heartbeat {
			label = "heartbeat";
			gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_vcc_3v3_mcu: regulator-vcc3v3mcu {
		compatible = "regulator-fixed";
		regulator-name = "vcc_3v3_mcu";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	spi {
		compatible = "spi-gpio";
		pinctrl-0 = <&pinctrl_gpio_spi>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		/* PTD12 ->RPIO[91] */
		sck-gpios  = <&gpio2 27 GPIO_ACTIVE_LOW>;
		/* PTD10 ->RPIO[89] */
		miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
		num-chipselects = <0>;

		gpio@0 {
			compatible = "pisosr-gpio";
			reg = <0>;
			gpio-controller;
			#gpio-cells = <2>;
			/* PTB18 -> RGPIO[40] */
			load-gpios  = <&gpio1 8 GPIO_ACTIVE_LOW>;
			spi-max-frequency = <100000>;
		};
	};
};

&adc0 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
};

&adc1 {
	vref-supply = <&reg_vcc_3v3_mcu>;
	status = "okay";
};

&can0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can0>;
	status = "okay";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can1>;
	status = "okay";
};

&clks {
	clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
	clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
};

&dspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi0>;
	bus-num = <0>;
	status = "okay";

	spidev0@0 {
		compatible = "lwn,bk4";
		spi-max-frequency = <30000000>;
		reg = <0>;
		fsl,spi-cs-sck-delay = <200>;
		fsl,spi-sck-cs-delay = <400>;
	};
};

&dspi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi3>;
	bus-num = <3>;
	status = "okay";
	spi-slave;
	#address-cells = <0>;

	slave {
		compatible = "lwn,bk4";
		spi-max-frequency = <30000000>;
	};
};

&edma0 {
	status = "okay";
};

&edma1 {
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&fec0 {
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec0>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@1 {
			reg = <1>;
			clocks = <&clks VF610_CLK_ENET_50M>;
			clock-names = "rmii-ref";
		};
	};
};

&fec1 {
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			reg = <1>;
			clocks = <&clks VF610_CLK_ENET_50M>;
			clock-names = "rmii-ref";
		};
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	at24c256: eeprom@50 {
		compatible = "atmel,24c256";
		reg = <0x50>;
	};

	m41t62: rtc@68 {
		compatible = "st,m41t62";
		reg = <0x68>;
	};
};

&nfc {
	assigned-clocks = <&clks VF610_CLK_NFC>;
	assigned-clock-rates = <33000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nfc>;
	status = "okay";

	nand@0 {
		compatible = "fsl,vf610-nfc-nandcs";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		nand-bus-width = <16>;
		nand-ecc-mode = "hw";
		nand-ecc-strength = <24>;
		nand-ecc-step-size = <2048>;
		nand-on-flash-bbt;
	};
};

&qspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi0>;
	status = "okay";

	n25q128a13_4: flash@0 {
		compatible = "n25q128a13", "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <66000000>;
		spi-rx-bus-width = <4>;
		reg = <0>;
	};

	n25q128a13_2: flash@2 {
		compatible = "n25q128a13", "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <66000000>;
		spi-rx-bus-width = <2>;
		reg = <2>;
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
	/delete-property/dma-names;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	/delete-property/dma-names;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	/delete-property/dma-names;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	/delete-property/dma-names;
	status = "okay";
};

&usbdev0 {
	disable-over-current;
	status = "okay";
};

&usbh1 {
	disable-over-current;
	status = "okay";
};

&usbmisc0 {
	status = "okay";
};

&usbmisc1 {
	status = "okay";
};

&usbphy0 {
	status = "okay";
};

&usbphy1 {
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			/* One_Wire_PSU_EN */
			VF610_PAD_PTC29__GPIO_102		0x1183
			/* SPI ENABLE */
			VF610_PAD_PTB26__GPIO_96		0x1183
			/* EB control */
			VF610_PAD_PTE14__GPIO_119		0x1183
			VF610_PAD_PTE4__GPIO_109		0x1181
			/* Feedback_Lines */
			VF610_PAD_PTC31__GPIO_104		0x1181
			VF610_PAD_PTA7__GPIO_134		0x1181
			VF610_PAD_PTD9__GPIO_88		0x1181
			VF610_PAD_PTE1__GPIO_106		0x1183
			VF610_PAD_PTB2__GPIO_24		0x1181
			VF610_PAD_PTB3__GPIO_25		0x1181
			VF610_PAD_PTB1__GPIO_23		0x1181
			/* SDHC Enable */
			VF610_PAD_PTE19__GPIO_124		0x1183
			/* SDHC Overcurrent */
			VF610_PAD_PTB23__GPIO_93		0x1181
			/* GPI */
			VF610_PAD_PTE2__GPIO_107		0x1181
			VF610_PAD_PTE3__GPIO_108		0x1181
			VF610_PAD_PTE5__GPIO_110		0x1181
			VF610_PAD_PTE6__GPIO_111		0x1181
			/* GPO */
			VF610_PAD_PTE0__GPIO_105		0x1183
			VF610_PAD_PTE7__GPIO_112		0x1183
			/* RS485 Control */
			VF610_PAD_PTB8__GPIO_30		0x1183
			VF610_PAD_PTB9__GPIO_31		0x1183
			VF610_PAD_PTE8__GPIO_113		0x1183
			/* MPBUS MPB_EN */
			VF610_PAD_PTE28__GPIO_133		0x1183
			/* MISC */
			VF610_PAD_PTE10__GPIO_115		0x1183
			VF610_PAD_PTE11__GPIO_116		0x1183
			VF610_PAD_PTE17__GPIO_122		0x1183
			VF610_PAD_PTC30__GPIO_103		0x1183
			VF610_PAD_PTB0__GPIO_22		0x1181
			/* RESETINFO */
			VF610_PAD_PTE26__GPIO_131		0x1183
			VF610_PAD_PTD6__GPIO_85		0x1181
			VF610_PAD_PTE27__GPIO_132		0x1181
			VF610_PAD_PTE13__GPIO_118		0x1181
			VF610_PAD_PTE21__GPIO_126		0x1181
			VF610_PAD_PTE22__GPIO_127		0x1181
			/* EE_5V_EN */
			VF610_PAD_PTE18__GPIO_123		0x1183
			/* EE_5V_OC_N */
			VF610_PAD_PTE25__GPIO_130		0x1181
		>;
	};

	pinctrl_can0: can0grp {
		fsl,pins = <
			VF610_PAD_PTB14__CAN0_RX		0x1181
			VF610_PAD_PTB15__CAN0_TX		0x1182
		>;
	};

	pinctrl_can1: can1grp {
		fsl,pins = <
			VF610_PAD_PTB16__CAN1_RX		0x1181
			VF610_PAD_PTB17__CAN1_TX		0x1182
		>;
	};

	pinctrl_dspi0: dspi0grp {
		fsl,pins = <
			VF610_PAD_PTB18__DSPI0_CS1		0x1182
			VF610_PAD_PTB19__DSPI0_CS0		0x1182
			VF610_PAD_PTB20__DSPI0_SIN		0x1181
			VF610_PAD_PTB21__DSPI0_SOUT		0x1182
			VF610_PAD_PTB22__DSPI0_SCK		0x1182
		>;
	};

	pinctrl_dspi3: dspi3grp {
		fsl,pins = <
			VF610_PAD_PTD10__DSPI3_CS0		0x1181
			VF610_PAD_PTD11__DSPI3_SIN		0x1181
			VF610_PAD_PTD12__DSPI3_SOUT		0x1182
			VF610_PAD_PTD13__DSPI3_SCK		0x1181
		>;
	};

	pinctrl_esdhc1: esdhc1grp {
		fsl,pins = <
			VF610_PAD_PTA24__ESDHC1_CLK		0x31ef
			VF610_PAD_PTA25__ESDHC1_CMD		0x31ef
			VF610_PAD_PTA26__ESDHC1_DAT0		0x31ef
			VF610_PAD_PTA27__ESDHC1_DAT1		0x31ef
			VF610_PAD_PTA28__ESDHC1_DATA2		0x31ef
			VF610_PAD_PTA29__ESDHC1_DAT3		0x31ef
			VF610_PAD_PTB28__GPIO_98		0x219d
		>;
	};

	pinctrl_fec0: fec0grp {
		fsl,pins = <
			VF610_PAD_PTA6__RMII_CLKIN		0x30dd
			VF610_PAD_PTC0__ENET_RMII0_MDC		0x30de
			VF610_PAD_PTC1__ENET_RMII0_MDIO	0x30df
			VF610_PAD_PTC2__ENET_RMII0_CRS		0x30dd
			VF610_PAD_PTC3__ENET_RMII0_RXD1	0x30dd
			VF610_PAD_PTC4__ENET_RMII0_RXD0	0x30dd
			VF610_PAD_PTC5__ENET_RMII0_RXER	0x30dd
			VF610_PAD_PTC6__ENET_RMII0_TXD1	0x30de
			VF610_PAD_PTC7__ENET_RMII0_TXD0	0x30de
			VF610_PAD_PTC8__ENET_RMII0_TXEN	0x30de
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30de
			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30df
			VF610_PAD_PTC11__ENET_RMII1_CRS	0x30dd
			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30dd
			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30dd
			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30dd
			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30de
			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30de
			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30de
		>;
	};

	pinctrl_gpio_leds: gpioledsgrp {
		fsl,pins = <
			/* Heart bit LED */
			VF610_PAD_PTE12__GPIO_117	0x1183
			/* LEDS */
			VF610_PAD_PTE15__GPIO_120	0x1183
			VF610_PAD_PTA12__GPIO_5	0x1183
			VF610_PAD_PTA16__GPIO_6	0x1183
			VF610_PAD_PTE9__GPIO_114	0x1183
			VF610_PAD_PTE20__GPIO_125	0x1183
			VF610_PAD_PTE23__GPIO_128	0x1183
			VF610_PAD_PTE16__GPIO_121	0x1183
		>;
	};

	pinctrl_gpio_spi: pinctrl-gpio-spi {
		fsl,pins = <
			VF610_PAD_PTB18__GPIO_40        0x1183
			VF610_PAD_PTD10__GPIO_89        0x1183
			VF610_PAD_PTD12__GPIO_91        0x1183
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			VF610_PAD_PTA22__I2C2_SCL               0x34df
			VF610_PAD_PTA23__I2C2_SDA               0x34df
		>;
	};

	pinctrl_nfc: nfcgrp {
		fsl,pins = <
			VF610_PAD_PTD23__NF_IO7		0x28df
			VF610_PAD_PTD22__NF_IO6		0x28df
			VF610_PAD_PTD21__NF_IO5		0x28df
			VF610_PAD_PTD20__NF_IO4		0x28df
			VF610_PAD_PTD19__NF_IO3		0x28df
			VF610_PAD_PTD18__NF_IO2		0x28df
			VF610_PAD_PTD17__NF_IO1		0x28df
			VF610_PAD_PTD16__NF_IO0		0x28df
			VF610_PAD_PTB24__NF_WE_B		0x28c2
			VF610_PAD_PTB25__NF_CE0_B		0x28c2
			VF610_PAD_PTB27__NF_RE_B		0x28c2
			VF610_PAD_PTC26__NF_RB_B		0x283d
			VF610_PAD_PTC27__NF_ALE		0x28c2
			VF610_PAD_PTC28__NF_CLE		0x28c2
		>;
	};

	pinctrl_qspi0: qspi0grp {
		fsl,pins = <
			VF610_PAD_PTD0__QSPI0_A_QSCK	0x397f
			VF610_PAD_PTD1__QSPI0_A_CS0	0x397f
			VF610_PAD_PTD2__QSPI0_A_DATA3	0x397f
			VF610_PAD_PTD3__QSPI0_A_DATA2	0x397f
			VF610_PAD_PTD4__QSPI0_A_DATA1	0x397f
			VF610_PAD_PTD5__QSPI0_A_DATA0	0x397f
			VF610_PAD_PTD7__QSPI0_B_QSCK	0x397f
			VF610_PAD_PTD8__QSPI0_B_CS0	0x397f
			VF610_PAD_PTD11__QSPI0_B_DATA1	0x397f
			VF610_PAD_PTD12__QSPI0_B_DATA0	0x397f
		>;
	};

	pinctrl_uart0: uart0grp {
		fsl,pins = <
			VF610_PAD_PTB10__UART0_TX		0x21a2
			VF610_PAD_PTB11__UART0_RX		0x21a1
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			VF610_PAD_PTB4__UART1_TX		0x21a2
			VF610_PAD_PTB5__UART1_RX		0x21a1
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			VF610_PAD_PTB6__UART2_TX		0x21a2
			VF610_PAD_PTB7__UART2_RX		0x21a1
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			VF610_PAD_PTA20__UART3_TX		0x21a2
			VF610_PAD_PTA21__UART3_RX		0x21a1
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2014-2020 Toradex
 */

/dts-v1/;
#include "vf610-colibri.dtsi"
#include "vf-colibri-eval-v3.dtsi"

/ {
	model = "Toradex Colibri VF61 on Colibri Evaluation Board";
	compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2014-2020 Toradex
 */

#include "vf610.dtsi"
#include "vf-colibri.dtsi"

/ {
	model = "Toradex Colibri VF61 COM";
	compatible = "toradex,vf610-colibri_vf61", "fsl,vf610";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;
	};
};

&nfc {
	assigned-clocks = <&clks VF610_CLK_NFC>;
	assigned-clock-rates = <50000000>;
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 * Copyright 2013 Linaro Limited
 */

/dts-v1/;
#include "vf610.dtsi"

/ {
	model = "PHYTEC Cosmic/Cosmic+ Board";
	compatible = "phytec,vf610-cosmic", "fsl,vf610";

	chosen {
		bootargs = "console=ttyLP1,115200";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;
	};

	enet_ext: enet_ext {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
	};
};

&clks {
	clocks = <&sxosc>, <&fxosc>, <&enet_ext>;
	clock-names = "sxosc", "fxosc", "enet_ext";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	status = "okay";
};

&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";
};

&iomuxc {
	vf610-cosmic {
		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
				VF610_PAD_PTA25__ESDHC1_CMD	0x31ef
				VF610_PAD_PTA26__ESDHC1_DAT0	0x31ef
				VF610_PAD_PTA27__ESDHC1_DAT1	0x31ef
				VF610_PAD_PTA28__ESDHC1_DATA2	0x31ef
				VF610_PAD_PTA29__ESDHC1_DAT3	0x31ef
				VF610_PAD_PTB28__GPIO_98	0x219d
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
				VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
				VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
				VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
				VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
				VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
				VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
				VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
				VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				VF610_PAD_PTB4__UART1_TX		0x21a2
				VF610_PAD_PTB5__UART1_RX		0x21a1
			>;
		};
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};