code:
CS35L35 Boosted Speaker Amplifier

Required properties:

  - compatible : "cirrus,cs35l35"

  - reg : the I2C address of the device for I2C

  - VA-supply, VP-supply : power supplies for the device,
    as covered in
    Documentation/devicetree/bindings/regulator/regulator.txt.

  - interrupts : IRQ line info CS35L35.
    (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
    for further information relating to interrupt properties)

 - cirrus,boost-ind-nanohenry: Inductor value for boost converter. The value is
    in nH and they can be values of 1000nH, 1200nH, 1500nH, and 2200nH.

Optional properties:
  - reset-gpios : gpio used to reset the amplifier

  - cirrus,stereo-config : Boolean to determine if there are 2 AMPs for a
  Stereo configuration

  - cirrus,audio-channel : Set Location of Audio Signal on Serial Port
  0 = Data Packet received on Left I2S Channel
  1 = Data Packet received on Right I2S Channel

  - cirrus,advisory-channel : Set Location of Advisory Signal on Serial Port
  0 = Data Packet received on Left I2S Channel
  1 = Data Packet received on Right I2S Channel

  - cirrus,shared-boost : Boolean to enable ClassH tracking of Advisory Signal
  if 2 Devices share Boost BST_CTL

  - cirrus,external-boost : Boolean to specify the device is using an external
  boost supply, note that sharing a boost from another cs35l35 would constitute
  using an external supply for the slave device

  - cirrus,sp-drv-strength : Value for setting the Serial Port drive strength
  Table 3-10 of the datasheet lists drive-strength specifications
  0 = 1x (Default)
  1 = .5x
  - cirrus,sp-drv-unused : Determines how unused slots should be driven on the
  Serial Port.
  0 - Hi-Z
  2 - Drive 0's (Default)
  3 - Drive 1's

  - cirrus,bst-pdn-fet-on : Boolean to determine if the Boost PDN control
  powers down with a rectification FET On or Off. If VSPK is supplied
  externally then FET is off.

  - cirrus,boost-ctl-millivolt : Boost Voltage Value.  Configures the boost
    converter's output voltage in mV. The range is from 2600mV to 9000mV with
    increments of 100mV.
    (Default) VP

  - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
  Configures the peak current by monitoring the current through the boost FET.
  Range starts at 1680mA and goes to a maximum of 4480mA with increments of
  110mA.
  (Default) 2.46 Amps

  - cirrus,amp-gain-zc : Boolean to determine if to use Amplifier gain-change
  zero-cross

Optional H/G Algorithm sub-node:

  The cs35l35 node can have a single "cirrus,classh-internal-algo" sub-node
  that will disable automatic control of the internal H/G Algorithm.

  It is strongly recommended that the Datasheet be referenced when adjusting
  or using these Class H Algorithm controls over the internal Algorithm.
  Serious damage can occur to the Device and surrounding components.

  - cirrus,classh-internal-algo : Sub-node for the Internal Class H Algorithm
  See Section 4.3 Internal Class H Algorithm in the Datasheet.
  If not used, the device manages the ClassH Algorithm internally.

Optional properties for the "cirrus,classh-internal-algo" Sub-node

  Section 7.29 Class H Control
  - cirrus,classh-bst-overide : Boolean
  - cirrus,classh-bst-max-limit
  - cirrus,classh-mem-depth

  Section 7.30 Class H Headroom Control
  - cirrus,classh-headroom

  Section 7.31 Class H Release Rate
  - cirrus,classh-release-rate

  Section 7.32 Class H Weak FET Drive Control
  - cirrus,classh-wk-fet-disable
  - cirrus,classh-wk-fet-delay
  - cirrus,classh-wk-fet-thld

  Section 7.34 Class H VP Control
  - cirrus,classh-vpch-auto
  - cirrus,classh-vpch-rate
  - cirrus,classh-vpch-man

Optional Monitor Signal Format sub-node:

  The cs35l35 node can have a single "cirrus,monitor-signal-format" sub-node
  for adjusting the Depth, Location and Frame of the Monitoring Signals
  for Algorithms.

  See Sections 4.8.2 through 4.8.4 Serial-Port Control in the Datasheet

  -cirrus,monitor-signal-format : Sub-node for the Monitor Signaling Formating
  on the I2S Port. Each of the 3 8 bit values in the array contain the settings
  for depth, location, and frame.

  If not used, the defaults for the 6 monitor signals is used.

  Sections 7.44 - 7.53 lists values for the depth, location, and frame
  for each monitoring signal.

  - cirrus,imon : 4 8 bit values to set the depth, location, frame and ADC
  scale of the IMON monitor signal.

  - cirrus,vmon : 3 8 bit values to set the depth, location, and frame
  of the VMON monitor signal.

  - cirrus,vpmon : 3 8 bit values to set the depth, location, and frame
  of the VPMON monitor signal.

  - cirrus,vbstmon : 3 8 bit values to set the depth, location, and frame
  of the VBSTMON monitor signal

  - cirrus,vpbrstat : 3 8 bit values to set the depth, location, and frame
  of the VPBRSTAT monitor signal

  - cirrus,zerofill : 3 8 bit values to set the depth, location, and frame\
  of the ZEROFILL packet in the monitor signal

Example:

cs35l35: cs35l35@20 {
	compatible = "cirrus,cs35l35";
	reg = <0x20>;
	VA-supply = <&dummy_vreg>;
	VP-supply = <&dummy_vreg>;
	reset-gpios = <&axi_gpio 54 0>;
	interrupt-parent = <&gpio8>;
	interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
	cirrus,boost-ctl-millivolt = <9000>;

	cirrus,stereo-config;
	cirrus,audio-channel = <0x00>;
	cirrus,advisory-channel = <0x01>;
	cirrus,shared-boost;

	cirrus,classh-internal-algo {
		cirrus,classh-bst-overide;
		cirrus,classh-bst-max-limit = <0x01>;
		cirrus,classh-mem-depth = <0x01>;
		cirrus,classh-release-rate = <0x08>;
		cirrus,classh-headroom-millivolt = <0x0B>;
		cirrus,classh-wk-fet-disable = <0x01>;
		cirrus,classh-wk-fet-delay = <0x04>;
		cirrus,classh-wk-fet-thld = <0x01>;
		cirrus,classh-vpch-auto = <0x01>;
		cirrus,classh-vpch-rate = <0x02>;
		cirrus,classh-vpch-man = <0x05>;
	};

	/* Depth, Location, Frame */
	cirrus,monitor-signal-format {
		cirrus,imon = /bits/ 8 <0x03 0x00 0x01>;
		cirrus,vmon = /bits/ 8 <0x03 0x00 0x00>;
		cirrus,vpmon = /bits/ 8 <0x03 0x04 0x00>;
		cirrus,vbstmon = /bits/ 8 <0x03 0x04 0x01>;
		cirrus,vpbrstat = /bits/ 8 <0x00 0x04 0x00>;
		cirrus,zerofill = /bits/ 8 <0x00 0x00 0x00>;
	};

};


code:
CS35L36 Speaker Amplifier

Required properties:

  - compatible : "cirrus,cs35l36"

  - reg : the I2C address of the device for I2C

  - VA-supply, VP-supply : power supplies for the device,
  as covered in
  Documentation/devicetree/bindings/regulator/regulator.txt.

  - cirrus,boost-ctl-millivolt : Boost Voltage Value.  Configures the boost
  converter's output voltage in mV. The range is from 2550mV to 12000mV with
  increments of 50mV.
  (Default) VP

  - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
  Configures the peak current by monitoring the current through the boost FET.
  Range starts at 1600mA and goes to a maximum of 4500mA with increments of
  50mA.
  (Default) 4.50 Amps

  - cirrus,boost-ind-nanohenry : Inductor estimation LBST reference value.
  Seeds the digital boost converter's inductor estimation block with the initial
  inductance value to reference.

  1000 = 1uH (Default)
  1200 = 1.2uH

Optional properties:
  - cirrus,multi-amp-mode : Boolean to determine if there are more than
  one amplifier in the system. If more than one it is best to Hi-Z the ASP
  port to prevent bus contention on the output signal

  - cirrus,boost-ctl-select : Boost conerter control source selection.
  Selects the source of the BST_CTL target VBST voltage for the boost
  converter to generate.
  0x00 - Control Port Value
  0x01 - Class H Tracking (Default)
  0x10 - MultiDevice Sync Value

  - cirrus,amp-pcm-inv : Boolean to determine Amplifier will invert incoming
  PCM data

  - cirrus,imon-pol-inv : Boolean to determine Amplifier will invert the
  polarity of outbound IMON feedback data

  - cirrus,vmon-pol-inv : Boolean to determine Amplifier will invert the
  polarity of outbound VMON feedback data

  - cirrus,dcm-mode-enable : Boost converter automatic DCM Mode enable.
  This enables the digital boost converter to operate in a low power
  (Discontinuous Conduction) mode during low loading conditions.

  - cirrus,weak-fet-disable : Boolean : The strength of the output drivers is
  reduced when operating in a Weak-FET Drive Mode and must not be used to drive
  a large load.

  - cirrus,classh-wk-fet-delay :  Weak-FET entry delay. Controls the delay
  (in ms) before the Class H algorithm switches to the weak-FET voltage
  (after the audio falls and remains below the value specified in WKFET_AMP_THLD).

  0 = 0ms
  1 = 5ms
  2 = 10ms
  3 = 50ms
  4 = 100ms (Default)
  5 = 200ms
  6 = 500ms
  7 = 1000ms

  - cirrus,classh-weak-fet-thld-millivolt : Weak-FET amplifier drive threshold.
  Configures the signal threshold at which the PWM output stage enters
  weak-FET operation. The range is 50mV to 700mV in 50mV increments.

  - cirrus,temp-warn-threshold :  Amplifier overtemperature warning threshold.
  Configures the threshold at which the overtemperature warning condition occurs.
  When the threshold is met, the overtemperature warning attenuation is applied
  and the TEMP_WARN_EINT interrupt status bit is set.
  If TEMP_WARN_MASK = 0, INTb is asserted.

  0 = 105C
  1 = 115C
  2 = 125C (Default)
  3 = 135C

  - cirrus,irq-drive-select : Selects the driver type of the selected interrupt
  output.

  0 = Open-drain
  1 = Push-pull (Default)

  - cirrus,irq-gpio-select : Selects the pin to serve as the programmable
  interrupt output.

  0 = PDM_DATA / SWIRE_SD / INT (Default)
  1 = GPIO

Optional properties for the "cirrus,vpbr-config" Sub-node

  - cirrus,vpbr-en : VBST brownout prevention enable. Configures whether the
  VBST brownout prevention algorithm is enabled or disabled.

  0 = VBST brownout prevention disabled (default)
  1 = VBST brownout prevention enabled

  See Section 7.31.1 VPBR Config for configuration options & further details

  - cirrus,vpbr-thld : Initial VPBR threshold. Configures the VP brownout
  threshold voltage

  - cirrus,cirrus,vpbr-atk-rate : Attenuation attack step rate. Configures the
  amount delay between consecutive volume attenuation steps when a brownout
  condition is present and the VP brownout condition is in an attacking state.

  - cirrus,vpbr-atk-vol : VP brownout prevention step size. Configures the VP
  brownout prevention attacking attenuation step size when operating in either
  digital volume or analog gain modes.

  - cirrus,vpbr-max-attn : Maximum attenuation that the VP brownout prevention
  can apply to the audio signal.

  - cirrus,vpbr-wait : Configures the delay time between a brownout condition
  no longer being present and the VP brownout prevention entering an attenuation
  release state.

  - cirrus,vpbr-rel-rate : Attenuation release step rate. Configures the delay
  between consecutive volume attenuation release steps when a brownout condition
  is not longer present and the VP brownout is in an attenuation release state.

  - cirrus,vpbr-mute-en : During the attack state, if the vpbr-max-attn value
  is reached, the error condition still remains, and this bit is set, the audio
  is muted.

Example:

cs35l36: cs35l36@40 {
	compatible = "cirrus,cs35l36";
	reg = <0x40>;
	VA-supply = <&dummy_vreg>;
	VP-supply = <&dummy_vreg>;
	reset-gpios = <&gpio0 54 0>;
	interrupt-parent = <&gpio8>;
	interrupts = <3 IRQ_TYPE_LEVEL_LOW>;

	cirrus,boost-ind-nanohenry = <1000>;
	cirrus,boost-ctl-millivolt = <10000>;
	cirrus,boost-peak-milliamp = <4500>;
	cirrus,boost-ctl-select = <0x00>;
	cirrus,weak-fet-delay = <0x04>;
	cirrus,weak-fet-thld = <0x01>;
	cirrus,temp-warn-threshold = <0x01>;
	cirrus,multi-amp-mode;
	cirrus,irq-drive-select = <0x01>;
	cirrus,irq-gpio-select = <0x01>;

	cirrus,vpbr-config {
		cirrus,vpbr-en = <0x00>;
		cirrus,vpbr-thld = <0x05>;
		cirrus,vpbr-atk-rate = <0x02>;
		cirrus,vpbr-atk-vol = <0x01>;
		cirrus,vpbr-max-attn = <0x09>;
		cirrus,vpbr-wait = <0x01>;
		cirrus,vpbr-rel-rate = <0x05>;
		cirrus,vpbr-mute-en = <0x00>;
	};
};

repo_name: angery/linux


code:
CS4265 audio CODEC

This device supports I2C only.

Required properties:

  - compatible : "cirrus,cs4265"

  - reg : the I2C address of the device for I2C. The I2C address depends on
          the state of the AD0 pin.  If AD0 is high, the i2c address is 0x4f.
          If it is low, the i2c address is 0x4e.

Optional properties:

  - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
		 deasserted before communication to the codec starts.

Examples:

codec_ad0_high: cs4265@4f { /* AD0 Pin is high */
	compatible = "cirrus,cs4265";
	reg = <0x4f>;
};

codec_ad0_low: cs4265@4e { /* AD0 Pin is low */
	compatible = "cirrus,cs4265";
	reg = <0x4e>;
};


code:
CS4270 audio CODEC

The driver for this device currently only supports I2C.

Required properties:

  - compatible : "cirrus,cs4270"

  - reg : the I2C address of the device for I2C

Optional properties:

  - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
		  deasserted before communication to the codec starts.

Example:

codec: cs4270@48 {
	compatible = "cirrus,cs4270";
	reg = <0x48>;
};


code:
Cirrus Logic CS4271 DT bindings

This driver supports both the I2C and the SPI bus.

Required properties:

 - compatible: "cirrus,cs4271"

For required properties on SPI, please consult
Documentation/devicetree/bindings/spi/spi-bus.txt

Required properties on I2C:

 - reg: the i2c address

Optional properties:

 - reset-gpio: 	a GPIO spec to define which pin is connected to the chip's
		!RESET pin
 - cirrus,amuteb-eq-bmutec:	When given, the Codec's AMUTEB=BMUTEC flag
				is enabled.
 - cirrus,enable-soft-reset:
	The CS4271 requires its LRCLK and MCLK to be stable before its RESET
	line is de-asserted. That also means that clocks cannot be changed
	without putting the chip back into hardware reset, which also requires
	a complete re-initialization of all registers.

	One (undocumented) workaround is to assert and de-assert the PDN bit
	in the MODE2 register. This workaround can be enabled with this DT
	property.

	Note that this is not needed in case the clocks are stable
	throughout the entire runtime of the codec.

 - vd-supply:	Digital power
 - vl-supply:	Logic power
 - va-supply:	Analog Power

Examples:

	codec_i2c: cs4271@10 {
		compatible = "cirrus,cs4271";
		reg = <0x10>;
		reset-gpio = <&gpio 23 0>;
		vd-supply = <&vdd_3v3_reg>;
		vl-supply = <&vdd_3v3_reg>;
		va-supply = <&vdd_3v3_reg>;
	};

	codec_spi: cs4271@0 {
		compatible = "cirrus,cs4271";
		reg = <0x0>;
		reset-gpio = <&gpio 23 0>;
		spi-max-frequency = <6000000>;
	};


code:
CS42L52 audio CODEC

Required properties:

  - compatible : "cirrus,cs42l52"

  - reg : the I2C address of the device for I2C

Optional properties:

  - cirrus,reset-gpio : GPIO controller's phandle and the number
  of the GPIO used to reset the codec.

  - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
  Allowable values of 0x00 through 0x0F. These are raw values written to the
  register, not the actual frequency. The frequency is determined by the following.
  Frequency = (64xFs)/(N+2)
  N = chgfreq_val
  Fs = Sample Rate (variable)

  - cirrus,mica-differential-cfg : boolean, If present, then the MICA input is configured
  as a differential input. If not present then the MICA input is configured as
  Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.

  - cirrus,micb-differential-cfg : boolean, If present, then the MICB input is configured
  as a differential input. If not present then the MICB input is configured as
  Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input.

  - cirrus,micbias-lvl: Set the output voltage level on the MICBIAS Pin
  0 = 0.5 x VA
  1 = 0.6 x VA
  2 = 0.7 x VA
  3 = 0.8 x VA
  4 = 0.83 x VA
  5 = 0.91 x VA

Example:

codec: codec@4a {
	compatible = "cirrus,cs42l52";
	reg = <0x4a>;
	reset-gpio = <&gpio 10 0>;
	cirrus,chgfreq-divisor = <0x05>;
	cirrus.mica-differential-cfg;
	cirrus,micbias-lvl = <5>;
};


code:
CS42L52 audio CODEC

Required properties:

  - compatible : "cirrus,cs42l56"

  - reg : the I2C address of the device for I2C

  - VA-supply, VCP-supply, VLDO-supply : power supplies for the device,
  as covered in Documentation/devicetree/bindings/regulator/regulator.txt.

Optional properties:

  - cirrus,gpio-nreset : GPIO controller's phandle and the number
  of the GPIO used to reset the codec.

  - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
  Allowable values of 0x00 through 0x0F. These are raw values written to the
  register, not the actual frequency. The frequency is determined by the following.
  Frequency = MCLK / 4 * (N+2)
  N = chgfreq_val
  MCLK = Where MCLK is the frequency of the mclk signal after the MCLKDIV2 circuit.

  - cirrus,ain1a-ref-cfg, ain1b-ref-cfg : boolean, If present, AIN1A or AIN1B are configured
  as a pseudo-differential input referenced to AIN1REF/AIN3A.

  - cirrus,ain2a-ref-cfg, ain2b-ref-cfg : boolean, If present, AIN2A or AIN2B are configured
  as a pseudo-differential input referenced to AIN2REF/AIN3B.

  - cirrus,micbias-lvl: Set the output voltage level on the MICBIAS Pin.
  0 = 0.5 x VA
  1 = 0.6 x VA
  2 = 0.7 x VA
  3 = 0.8 x VA
  4 = 0.83 x VA
  5 = 0.91 x VA

  - cirrus,adaptive-pwr-cfg : Configures how the power to the Headphone and Lineout
  Amplifiers adapt to the output signal levels.
  0 = Adapt to Volume Mode. Voltage level determined by the sum of the relevant volume settings.
  1 = Fixed - Headphone and Line Amp supply = + or - VCP/2.
  2 = Fixed - Headphone and Line Amp supply = + or - VCP.
  3 = Adapted to Signal; Voltage level is dynamically determined by the output signal.

  - cirrus,hpf-left-freq, hpf-right-freq : Sets the corner frequency (-3dB point) for the internal High-Pass
  Filter.
  0 = 1.8Hz
  1 = 119Hz
  2 = 236Hz
  3 = 464Hz

Example:

codec: codec@4b {
	compatible = "cirrus,cs42l56";
	reg = <0x4b>;
	cirrus,gpio-nreset = <&gpio 10 0>;
	cirrus,chgfreq-divisor = <0x05>;
	cirrus.ain1_ref_cfg;
	cirrus,micbias-lvl = <5>;
	VA-supply = <&reg_audio>;
};


code:
CS42L73 audio CODEC

Required properties:

  - compatible : "cirrus,cs42l73"

  - reg : the I2C address of the device for I2C

Optional properties:

  - reset_gpio : a GPIO spec for the reset pin.
  - chgfreq    : Charge Pump Frequency values 0x00-0x0F

Example:

codec: cs42l73@4a {
	compatible = "cirrus,cs42l73";
	reg = <0x4a>;
	reset_gpio = <&gpio 10 0>;
	chgfreq = <0x05>;
};


code:
CS42448/CS42888 audio CODEC

Required properties:

  - compatible : must contain one of "cirrus,cs42448" and "cirrus,cs42888"

  - reg : the I2C address of the device for I2C

  - clocks : a list of phandles + clock-specifiers, one for each entry in
    clock-names

  - clock-names : must contain "mclk"

  - VA-supply, VD-supply, VLS-supply, VLC-supply: power supplies for the device,
    as covered in Documentation/devicetree/bindings/regulator/regulator.txt

Optional properties:

  - reset-gpios : a GPIO spec to define which pin is connected to the chip's
    !RESET pin

Example:

cs42888: codec@48 {
	compatible = "cirrus,cs42888";
	reg = <0x48>;
	clocks = <&codec_mclk 0>;
	clock-names = "mclk";
	VA-supply = <&reg_audio>;
	VD-supply = <&reg_audio>;
	VLS-supply = <&reg_audio>;
	VLC-supply = <&reg_audio>;
	reset-gpios = <&pca9557_b 1 GPIO_ACTIVE_LOW>;
};


code:
CS43130 DAC

Required properties:

  - compatible : "cirrus,cs43130", "cirrus,cs4399", "cirrus,cs43131",
                 "cirrus,cs43198"

  - reg : the I2C address of the device for I2C

  - VA-supply, VP-supply, VL-supply, VCP-supply, VD-supply:
	power supplies for the device, as covered in
	Documentation/devicetree/bindings/regulator/regulator.txt.

Optional properties:

  - reset-gpios : Active low GPIO used to reset the device

  - cirrus,xtal-ibias:
   When external MCLK is generated by external crystal
   oscillator, CS43130 can be used to provide bias current
   for external crystal.  Amount of bias current sent is
   set as:
   1 = 7.5uA
   2 = 12.5uA
   3 = 15uA

  - cirrus,dc-measure:
   Boolean, define to enable headphone DC impedance measurement.

  - cirrus,ac-measure:
   Boolean, define to enable headphone AC impedance measurement.
   DC impedance must also be enabled for AC impedance measurement.

  - cirrus,dc-threshold:
   Define 2 DC impedance thresholds in ohms for HP output control.
   Default values are 50 and 120 Ohms.

  - cirrus,ac-freq:
   Define the frequencies at which to measure HP AC impedance.
   Only used if "cirrus,dc-measure" is defined.
   Exactly 10 frequencies must be defined.
   If this properties is undefined, by default,
   following frequencies are used:
   <24 43 93 200 431 928 2000 4309 9283 20000>
   The above frequencies are logarithmically equally spaced.
   Log base is 10.

Example:

cs43130: audio-codec@30 {
   compatible = "cirrus,cs43130";
   reg = <0x30>;
   reset-gpios = <&axi_gpio 54 0>;
   VA-supply = <&dummy_vreg>;
   VP-supply = <&dummy_vreg>;
   VL-supply = <&dummy_vreg>;
   VCP-supply = <&dummy_vreg>;
   VD-supply = <&dummy_vreg>;
   cirrus,xtal-ibias = <2>;
   interrupt-parent = <&gpio0>;
   interrupts = <55 8>;
   cirrus,dc-measure;
   cirrus,ac-measure;
   cirrus,dc-threshold = /bits/ 16 <20 100>;
   cirrus,ac-freq = /bits/ 16 <24 43 93 200 431 928 2000 4309 9283 20000>;
};


code:
Cirrus Logic CS4341 audio DAC

This device supports both I2C and SPI (configured with pin strapping
on the board).

Required properties:
  - compatible: "cirrus,cs4341a"
  - reg : the I2C address of the device for I2C, the chip select
          number for SPI.

For required properties on I2C-bus, please consult
Documentation/devicetree/bindings/i2c/i2c.txt
For required properties on SPI-bus, please consult
Documentation/devicetree/bindings/spi/spi-bus.txt

Example:
	codec: cs4341@0 {
		#sound-dai-cells = <0>;
		compatible = "cirrus,cs4341a";
		reg = <0>;
		spi-max-frequency = <6000000>;
	};


code:
CS4349 audio CODEC

Required properties:

  - compatible : "cirrus,cs4349"

  - reg : the I2C address of the device for I2C

Optional properties:

  - reset-gpios : a GPIO spec for the reset pin.

Example:

codec: cs4349@48 {
        compatible = "cirrus,cs4349";
        reg = <0x48>;
        reset-gpios = <&gpio 54 0>;
};


code:
CS53L30 audio CODEC

Required properties:

  - compatible : "cirrus,cs53l30"

  - reg : the I2C address of the device

  - VA-supply, VP-supply : power supplies for the device,
    as covered in Documentation/devicetree/bindings/regulator/regulator.txt.

Optional properties:

  - reset-gpios : a GPIO spec for the reset pin.

  - mute-gpios : a GPIO spec for the MUTE pin. The active state can be either
		 GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW, which would be handled
		 by the driver automatically.

  - cirrus,micbias-lvl : Set the output voltage level on the MICBIAS Pin.
			 0 = Hi-Z
			 1 = 1.80 V
			 2 = 2.75 V

  - cirrus,use-sdout2 : This is a boolean property. If present, it indicates
			the hardware design connects both SDOUT1 and SDOUT2
			pins to output data. Otherwise, it indicates that
			only SDOUT1 is connected for data output.
			* CS53l30 supports 4-channel data output in the same
			* frame using two different ways:
			* 1) Normal I2S mode on two data pins -- each SDOUT
			*    carries 2-channel data in the same time.
			* 2) TDM mode on one signle data pin -- SDOUT1 carries
			*    4-channel data per frame.

Example:

codec: cs53l30@48 {
	compatible = "cirrus,cs53l30";
	reg = <0x48>;
	reset-gpios = <&gpio 54 0>;
	VA-supply = <&cs53l30_va>;
	VP-supply = <&cs53l30_vp>;
};


code:
Dialog Semiconductor DA7212/DA7213 Audio Codec bindings

======

Required properties:
- compatible : Should be "dlg,da7212" or "dlg,da7213"
- reg: Specifies the I2C slave address

Optional properties:
- clocks : phandle and clock specifier for codec MCLK.
- clock-names : Clock name string for 'clocks' attribute, should be "mclk".

- dlg,micbias1-lvl : Voltage (mV) for Mic Bias 1
	[<1600>, <2200>, <2500>, <3000>]
- dlg,micbias2-lvl : Voltage (mV) for Mic Bias 2
	[<1600>, <2200>, <2500>, <3000>]
- dlg,dmic-data-sel : DMIC channel select based on clock edge.
	["lrise_rfall", "lfall_rrise"]
- dlg,dmic-samplephase : When to sample audio from DMIC.
	["on_clkedge", "between_clkedge"]
- dlg,dmic-clkrate : DMIC clock frequency (Hz).
	[<1500000>, <3000000>]

 - VDDA-supply : Regulator phandle for Analogue power supply
 - VDDMIC-supply : Regulator phandle for Mic Bias
 - VDDIO-supply : Regulator phandle for I/O power supply

======

Example:

	codec_i2c: da7213@1a {
		compatible = "dlg,da7213";
 		reg = <0x1a>;

 		clocks = <&clks 201>;
		clock-names = "mclk";

		dlg,micbias1-lvl = <2500>;
		dlg,micbias2-lvl = <2500>;

		dlg,dmic-data-sel = "lrise_rfall";
		dlg,dmic-samplephase = "between_clkedge";
		dlg,dmic-clkrate = <3000000>;
	};


code:
Dialog Semiconductor DA7218 Audio Codec bindings

DA7218 is an audio codec with HP detect feature.

======

Required properties:
- compatible : Should be "dlg,da7217" or "dlg,da7218"
- reg: Specifies the I2C slave address

- VDD-supply: VDD power supply for the device
- VDDMIC-supply: VDDMIC power supply for the device
- VDDIO-supply: VDDIO power supply for the device
  (See Documentation/devicetree/bindings/regulator/regulator.txt for further
   information relating to regulators)

Optional properties:
- interrupts: IRQ line info for DA7218 chip.
  (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
   further information relating to interrupt properties)
- interrupt-names : Name associated with interrupt line. Should be "wakeup" if
  interrupt is to be used to wake system, otherwise "irq" should be used.
- wakeup-source: Flag to indicate this device can wake system (suspend/resume).

- clocks : phandle and clock specifier for codec MCLK.
- clock-names : Clock name string for 'clocks' attribute, should be "mclk".

- dlg,micbias1-lvl-millivolt : Voltage (mV) for Mic Bias 1
	[<1200>, <1600>, <1800>, <2000>, <2200>, <2400>, <2600>, <2800>, <3000>]
- dlg,micbias2-lvl-millivolt : Voltage (mV) for Mic Bias 2
	[<1200>, <1600>, <1800>, <2000>, <2200>, <2400>, <2600>, <2800>, <3000>]
- dlg,mic1-amp-in-sel : Mic1 input source type
	["diff", "se_p", "se_n"]
- dlg,mic2-amp-in-sel : Mic2 input source type
	["diff", "se_p", "se_n"]
- dlg,dmic1-data-sel : DMIC1 channel select based on clock edge.
	["lrise_rfall", "lfall_rrise"]
- dlg,dmic1-samplephase : When to sample audio from DMIC1.
	["on_clkedge", "between_clkedge"]
- dlg,dmic1-clkrate-hz : DMic1 clock frequency (Hz).
	[<1500000>, <3000000>]
- dlg,dmic2-data-sel : DMic2 channel select based on clock edge.
	["lrise_rfall", "lfall_rrise"]
- dlg,dmic2-samplephase : When to sample audio from DMic2.
	["on_clkedge", "between_clkedge"]
- dlg,dmic2-clkrate-hz : DMic2 clock frequency (Hz).
	[<1500000>, <3000000>]
- dlg,hp-diff-single-supply : Boolean flag, use single supply for HP
			      (DA7217 only)

======

Optional Child node - 'da7218_hpldet' (DA7218 only):

Optional properties:
- dlg,jack-rate-us : Time between jack detect measurements (us)
	[<5>, <10>, <20>, <40>, <80>, <160>, <320>, <640>]
- dlg,jack-debounce : Number of debounce measurements taken for jack detect
	[<0>, <2>, <3>, <4>]
- dlg,jack-threshold-pct : Threshold level for jack detection (% of VDD)
	[<84>, <88>, <92>, <96>]
- dlg,comp-inv : Boolean flag, invert comparator output
- dlg,hyst : Boolean flag, enable hysteresis
- dlg,discharge : Boolean flag, auto discharge of Mic Bias on jack removal

======

Example:

	codec: da7218@1a {
		compatible = "dlg,da7218";
		reg = <0x1a>;
		interrupt-parent = <&gpio6>;
		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
		wakeup-source;

		VDD-supply = <&reg_audio>;
		VDDMIC-supply = <&reg_audio>;
		VDDIO-supply = <&reg_audio>;

		clocks = <&clks 201>;
		clock-names = "mclk";

		dlg,micbias1-lvl-millivolt = <2600>;
		dlg,micbias2-lvl-millivolt = <2600>;
		dlg,mic1-amp-in-sel = "diff";
		dlg,mic2-amp-in-sel = "diff";

		dlg,dmic1-data-sel = "lrise_rfall";
		dlg,dmic1-samplephase = "on_clkedge";
		dlg,dmic1-clkrate-hz = <3000000>;
		dlg,dmic2-data-sel = "lrise_rfall";
		dlg,dmic2-samplephase = "on_clkedge";
		dlg,dmic2-clkrate-hz = <3000000>;

		da7218_hpldet {
			dlg,jack-rate-us = <40>;
			dlg,jack-debounce = <2>;
			dlg,jack-threshold-pct = <84>;
			dlg,hyst;
		};
	};


code:
Dialog Semiconductor DA7219 Audio Codec bindings

DA7219 is an audio codec with advanced accessory detect features.

======

Required properties:
- compatible : Should be "dlg,da7219"
- reg: Specifies the I2C slave address

- interrupts : IRQ line info for DA7219.
  (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
   further information relating to interrupt properties)

- VDD-supply: VDD power supply for the device
- VDDMIC-supply: VDDMIC power supply for the device
- VDDIO-supply: VDDIO power supply for the device
  (See Documentation/devicetree/bindings/regulator/regulator.txt for further
   information relating to regulators)

Optional properties:
- interrupt-names : Name associated with interrupt line. Should be "wakeup" if
  interrupt is to be used to wake system, otherwise "irq" should be used.
- wakeup-source: Flag to indicate this device can wake system (suspend/resume).

- #clock-cells :  Should be set to '<1>', two clock sources provided;
- clock-output-names : Names given for DAI clock outputs (WCLK & BCLK);

- clocks : phandle and clock specifier for codec MCLK.
- clock-names : Clock name string for 'clocks' attribute, should be "mclk".

- dlg,micbias-lvl : Voltage (mV) for Mic Bias
	[<1600>, <1800>, <2000>, <2200>, <2400>, <2600>]
- dlg,mic-amp-in-sel : Mic input source type
	["diff", "se_p", "se_n"]

Deprecated properties:
- dlg,ldo-lvl : Required internal LDO voltage (mV) level for digital engine
  (LDO unavailable in production HW so property no longer required).

======

Child node - 'da7219_aad':

Optional properties:
- dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV).
	[<2800>, <2900>]
- dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms)
- dlg,btn-cfg : Periodic button press measurements for 4-pole jack (ms)
	[<2>, <5>, <10>, <50>, <100>, <200>, <500>]
- dlg,mic-det-thr : Impedance threshold for mic detection measurement (Ohms)
	[<200>, <500>, <750>, <1000>]
- dlg,jack-ins-deb : Debounce time for jack insertion (ms)
	[<5>, <10>, <20>, <50>, <100>, <200>, <500>, <1000>]
- dlg,jack-det-rate: Jack type detection latency (3/4 pole)
	["32ms_64ms", "64ms_128ms", "128ms_256ms", "256ms_512ms"]
- dlg,jack-rem-deb : Debounce time for jack removal (ms)
	[<1>, <5>, <10>, <20>]
- dlg,a-d-btn-thr : Impedance threshold between buttons A and D
	[0x0 - 0xFF]
- dlg,d-b-btn-thr : Impedance threshold between buttons D and B
	[0x0 - 0xFF]
- dlg,b-c-btn-thr : Impedance threshold between buttons B and C
	[0x0 - 0xFF]
- dlg,c-mic-btn-thr : Impedance threshold between button C and Mic
	[0x0 - 0xFF]
- dlg,btn-avg : Number of 8-bit readings for averaged button measurement
	[<1>, <2>, <4>, <8>]
- dlg,adc-1bit-rpt : Repeat count for 1-bit button measurement
	[<1>, <2>, <4>, <8>]

======

Example:

	codec: da7219@1a {
		compatible = "dlg,da7219";
		reg = <0x1a>;

		interrupt-parent = <&gpio6>;
		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;

		VDD-supply = <&reg_audio>;
		VDDMIC-supply = <&reg_audio>;
		VDDIO-supply = <&reg_audio>;

		#clock-cells = <1>;
		clock-output-names = "dai-wclk", "dai-bclk";

		clocks = <&clks 201>;
		clock-names = "mclk";

		dlg,ldo-lvl = <1200>;
		dlg,micbias-lvl = <2600>;
		dlg,mic-amp-in-sel = "diff";

		da7219_aad {
			dlg,btn-cfg = <50>;
			dlg,mic-det-thr = <500>;
			dlg,jack-ins-deb = <20>;
			dlg,jack-det-rate = "32ms_64ms";
			dlg,jack-rem-deb = <1>;

			dlg,a-d-btn-thr = <0xa>;
			dlg,d-b-btn-thr = <0x16>;
			dlg,b-c-btn-thr = <0x21>;
			dlg,c-mic-btn-thr = <0x3E>;

			dlg,btn-avg = <4>;
			dlg,adc-1bit-rpt = <1>;
		};
	};


code:
* Dialog DA9055 Audio CODEC

DA9055 provides Audio CODEC support (I2C only).

The Audio CODEC device in DA9055 has its own I2C address which is configurable,
so the device is instantiated separately from the PMIC (MFD) device.

For details on accompanying PMIC I2C device, see the following:
Documentation/devicetree/bindings/mfd/da9055.txt

Required properties:

  - compatible: "dlg,da9055-codec"
  - reg: Specifies the I2C slave address

Example:

	codec: da9055-codec@1a {
		compatible = "dlg,da9055-codec";
		reg = <0x1a>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/dai-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Digital Audio Interface Common Properties

maintainers:
  - Jerome Brunet <jbrunet@baylibre.com>

properties:
  sound-name-prefix:
    $ref: /schemas/types.yaml#/definitions/string
    description: |
      Card implementing the routing property define the connection between
      audio components as list of string pair. Component using the same
      sink/source names may use this property to prepend the name of their
      sinks/sources with the provided string.

  '#sound-dai-cells': true

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/dai-params.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Digital Audio Interface (DAI) Stream Parameters

maintainers:
  - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

select: false

$defs:

  dai-channels:
    description: Number of audio channels used by DAI
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 32

  dai-sample-format:
    description: Audio sample format used by DAI
    $ref: /schemas/types.yaml#/definitions/string
    enum:
      - s8
      - s16_le
      - s24_le
      - s24_3le
      - s32_le

  dai-sample-rate:
    description: Audio sample rate used by DAI
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 8000
    maximum: 192000

properties: {}

additionalProperties: true


code:
* Texas Instruments SoC audio setups with TLV320AIC3X Codec

Required properties:
- compatible : "ti,da830-evm-audio" : forDM365/DA8xx/OMAPL1x/AM33xx
- ti,model : The user-visible name of this sound complex.
- ti,audio-codec : The phandle of the TLV320AIC3x audio codec
- ti,mcasp-controller : The phandle of the McASP controller
- ti,audio-routing : A list of the connections between audio components.
  Each entry is a pair of strings, the first being the connection's sink,
  the second being the connection's source. Valid names for sources and
  sinks are the codec's pins, and the jacks on the board:

Optional properties:
- ti,codec-clock-rate : The Codec Clock rate (in Hz) applied to the Codec.
- clocks : Reference to the master clock
- clock-names : The clock should be named "mclk"
- Either codec-clock-rate or the codec-clock reference has to be defined. If
  the both are defined the driver attempts to set referenced clock to the
  defined rate and takes the rate from the clock reference.

  Board connectors:

  * Headphone Jack
  * Line Out
  * Mic Jack
  * Line In

Example:

sound {
	compatible = "ti,da830-evm-audio";
	ti,model = "DA830 EVM";
	ti,audio-codec = <&tlv320aic3x>;
	ti,mcasp-controller = <&mcasp1>;
	ti,codec-clock-rate = <12000000>;
	ti,audio-routing =
		"Headphone Jack",       "HPLOUT",
		"Headphone Jack",       "HPROUT",
		"Line Out",             "LLOUT",
		"Line Out",             "RLOUT",
		"MIC3L",                "Mic Bias 2V",
		"MIC3R",                "Mic Bias 2V",
		"Mic Bias 2V",          "Mic Jack",
		"LINE1L",               "Line In",
		"LINE2L",               "Line In",
		"LINE1R",               "Line In",
		"LINE2R",               "Line In";
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/davinci-mcasp-audio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: McASP Controller for TI SoCs

maintainers:
  - Jayesh Choudhary <j-choudhary@ti.com>

properties:
  compatible:
    enum:
      - ti,dm646x-mcasp-audio
      - ti,da830-mcasp-audio
      - ti,am33xx-mcasp-audio
      - ti,dra7-mcasp-audio
      - ti,omap4-mcasp-audio

  reg:
    minItems: 1
    items:
      - description: CFG registers
      - description: data registers

  reg-names:
    minItems: 1
    items:
      - const: mpu
      - const: dat

  op-mode:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: 0 - I2S or 1 - DIT operation mode
    enum:
      - 0
      - 1

  tdm-slots:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      number of channels over one serializer
      the property is ignored in DIT mode
    minimum: 2
    maximum: 32

  serial-dir:
    description:
      A list of serializer configuration
      Entry is indication for serializer pin direction
      0 - Inactive, 1 - TX, 2 - RX
      All AXR pins should be present in the array even if inactive
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 25
    items:
      minimum: 0
      maximum: 2

  dmas:
    minItems: 1
    items:
      - description: transmission DMA channel
      - description: reception DMA channel

  dma-names:
    minItems: 1
    items:
      - const: tx
      - const: rx

  ti,hwmods:
    $ref: /schemas/types.yaml#/definitions/string
    description: Name of hwmod associated with McASP
    maxItems: 1
    deprecated: true

  tx-num-evt:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      configures WFIFO threshold
      0 disables the FIFO use
      if property is missing, then also FIFO use is disabled

  rx-num-evt:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      configures RFIFO threshold
      0 disables the FIFO use
      if property is missing, then also FIFO use is disabled

  dismod:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      specify the drive on TX pin during inactive time slots
      0 - 3-state, 2 - logic low, 3 - logic high
    enum:
      - 0
      - 2
      - 3
    default: 2

  interrupts:
    anyOf:
      - minItems: 1
        items:
          - description: TX interrupt
          - description: RX interrupt
      - items:
          - description: common/combined interrupt

  interrupt-names:
    oneOf:
      - minItems: 1
        items:
          - const: tx
          - const: rx
      - const: common

  fck_parent:
    $ref: /schemas/types.yaml#/definitions/string
    description: parent clock name for McASP fck
    maxItems: 1

  auxclk-fs-ratio:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: ratio of AUCLK and FS rate if applicable

  gpio-controller: true

  "#gpio-cells":
    const: 2

  clocks:
    minItems: 1
    items:
      - description: functional clock
      - description: module specific optional ahclkx clock
      - description: module specific optional ahclkr clock

  clock-names:
    minItems: 1
    items:
      - const: fck
      - const: ahclkx
      - const: ahclkr

  power-domains:
    description: phandle to the corresponding power-domain
    maxItems: 1

  "#sound-dai-cells":
    const: 0

  port:
    description: connection for when McASP is used via graph card
    type: object

required:
  - compatible
  - reg
  - reg-names
  - dmas
  - dma-names
  - interrupts
  - interrupt-names

allOf:
  - $ref: dai-common.yaml#
  - if:
      properties:
        opmode:
          enum:
            - 0

    then:
      required:
        - tdm-slots

unevaluatedProperties: false

examples:
  - |
    mcasp0: mcasp0@1d00000 {
      compatible = "ti,da830-mcasp-audio";
      reg = <0x100000 0x3000>;
      reg-names = "mpu";
      interrupts = <82>, <83>;
      interrupt-names = "tx", "rx";
      op-mode = <0>;		/* MCASP_IIS_MODE */
      tdm-slots = <2>;
      dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
      dma-names = "tx", "rx";
      serial-dir = <
          0 0 0 0	/* 0: INACTIVE, 1: TX, 2: RX */
          0 0 0 0
          0 0 0 1
          2 0 0 0 >;
      tx-num-evt = <1>;
      rx-num-evt = <1>;
    };


code:
Texas Instruments DaVinci McBSP module
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

This binding describes the "Multi-channel Buffered Serial Port" (McBSP)
audio interface found in some TI DaVinci processors like the OMAP-L138 or AM180x.

Required properties:
~~~~~~~~~~~~~~~~~~~~
- compatible :
        "ti,da850-mcbsp" : for DA850, AM180x and OPAM-L138 platforms

- reg : physical base address and length of the controller memory mapped
        region(s).
- reg-names : Should contain:
        * "mpu" for the main registers (required).
        * "dat" for the data FIFO (optional).

- dmas: three element list of DMA controller phandles, DMA request line and
	TC channel ordered triplets.
- dma-names: identifier string for each DMA request line in the dmas property.
	These strings correspond 1:1 with the ordered pairs in dmas. The dma
	identifiers must be "rx" and "tx".

Optional properties:
~~~~~~~~~~~~~~~~~~~~
- interrupts : Interrupt numbers for McBSP
- interrupt-names : Known interrupt names are "rx" and "tx"

- pinctrl-0: Should specify pin control group used for this controller.
- pinctrl-names: Should contain only one value - "default", for more details
        please refer to pinctrl-bindings.txt

Example (AM1808):
~~~~~~~~~~~~~~~~~

mcbsp0: mcbsp@1d10000 {
	compatible = "ti,da850-mcbsp";
	pinctrl-names = "default";
	pinctrl-0 = <&mcbsp0_pins>;

	reg = 	<0x00110000 0x1000>,
		<0x00310000 0x1000>;
	reg-names = "mpu", "dat";
	interrupts = <97 98>;
	interrupt-names = "rx", "tx";
	dmas = <&edma0 3 1
		&edma0 2 1>;
	dma-names = "tx", "rx";
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/dmic-codec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic PDM Digital microphone (DMIC) codec

maintainers:
  - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>

allOf:
  - $ref: dai-common.yaml#

properties:
  compatible:
    const: dmic-codec

  '#sound-dai-cells':
    const: 0

  dmicen-gpios:
    description: GPIO specifier for DMIC to control start and stop
    maxItems: 1

  num-channels:
    description: Number of microphones on this DAI
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 8
    default: 8

  modeswitch-delay-ms:
    description: Delay (in ms) to complete DMIC mode switch

  wakeup-delay-ms:
    description: Delay (in ms) after enabling the DMIC

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    dmic {
        compatible = "dmic-codec";
        dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
        num-channels = <1>;
        wakeup-delay-ms = <50>;
        modeswitch-delay-ms = <35>;
    };
...


code:
Everest ES8328 audio CODEC

This device supports both I2C and SPI.

Required properties:

  - compatible  : Should be "everest,es8328" or "everest,es8388"
  - DVDD-supply : Regulator providing digital core supply voltage 1.8 - 3.6V
  - AVDD-supply : Regulator providing analog supply voltage 3.3V
  - PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V
  - IPVDD-supply : Regulator providing analog output voltage 3.3V
  - clocks : A 22.5792 or 11.2896 MHz clock
  - reg : the I2C address of the device for I2C, the chip select number for SPI

Pins on the device (for linking into audio routes):

  * LOUT1
  * LOUT2
  * ROUT1
  * ROUT2
  * LINPUT1
  * RINPUT1
  * LINPUT2
  * RINPUT2
  * Mic Bias

Example:

codec: es8328@11 {
	compatible = "everest,es8328";
	DVDD-supply = <&reg_3p3v>;
	AVDD-supply = <&reg_3p3v>;
	PVDD-supply = <&reg_3p3v>;
	HPVDD-supply = <&reg_3p3v>;
	clocks = <&clks 169>;
	reg = <0x11>;
};


code:
Audio complex for Eukrea boards with tlv320aic23 codec.

Required properties:

  - compatible		: "eukrea,asoc-tlv320"

  - eukrea,model	: The user-visible name of this sound complex.

  - ssi-controller	: The phandle of the SSI controller.

  - fsl,mux-int-port	: The internal port of the i.MX audio muxer (AUDMUX).

  - fsl,mux-ext-port	: The external port of the i.MX audio muxer.

Note: The AUDMUX port numbering should start at 1, which is consistent with
hardware manual.

Example:

	sound {
		compatible = "eukrea,asoc-tlv320";
		eukrea,model = "imx51-eukrea-tlv320aic23";
		ssi-controller = <&ssi2>;
		fsl,mux-int-port = <2>;
		fsl,mux-ext-port = <3>;
	};


code:
ES7134 i2s DA converter

Required properties:
- compatible : "everest,es7134" or
               "everest,es7144" or
	       "everest,es7154"
- VDD-supply : regulator phandle for the VDD supply
- PVDD-supply: regulator phandle for the PVDD supply for the es7154

Example:

i2s_codec: external-codec {
	compatible = "everest,es7134";
	VDD-supply = <&vcc_5v>;
};


code:
ES7241 i2s AD converter

Required properties:
- compatible : "everest,es7241"
- VDDP-supply: regulator phandle for the VDDA supply
- VDDA-supply: regulator phandle for the VDDP supply
- VDDD-supply: regulator phandle for the VDDD supply

Optional properties:
- reset-gpios: gpio connected to the reset pin
- m0-gpios   : gpio connected to the m0 pin
- m1-gpios   : gpio connected to the m1 pin
- everest,sdout-pull-down:
   Format used by the serial interface is controlled by pulling
   the sdout. If the sdout is pulled down, leftj format is used.
   If this property is not provided, sdout is assumed to pulled
   up and i2s format is used

Example:

linein: audio-codec@2 {
	#sound-dai-cells = <0>;
	compatible = "everest,es7241";
	VDDA-supply = <&vcc_3v3>;
	VDDP-supply = <&vcc_3v3>;
	VDDD-supply = <&vcc_3v3>;
	reset-gpios = <&gpio GPIOH_42>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/everest,es8316.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Everest ES8316 audio CODEC

maintainers:
  - Daniel Drake <drake@endlessm.com>
  - Katsuhiro Suzuki <katsuhiro@katsuster.net>

allOf:
  - $ref: dai-common.yaml#

properties:
  compatible:
    const: everest,es8316

  reg:
    maxItems: 1

  clocks:
    items:
      - description: clock for master clock (MCLK)

  clock-names:
    items:
      - const: mclk

  "#sound-dai-cells":
    const: 0

required:
  - compatible
  - reg
  - "#sound-dai-cells"

unevaluatedProperties: false

examples:
  - |
    i2c0 {
      #address-cells = <1>;
      #size-cells = <0>;
      es8316: codec@11 {
        compatible = "everest,es8316";
        reg = <0x11>;
        clocks = <&clks 10>;
        clock-names = "mclk";
        #sound-dai-cells = <0>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/everest,es8326.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Everest ES8326 audio CODEC

maintainers:
  - David Yang <yangxiaohua@everest-semi.com>

properties:
  compatible:
    const: everest,es8326

  reg:
    maxItems: 1

  clocks:
    items:
      - description: clock for master clock (MCLK)

  clock-names:
    items:
      - const: mclk

  "#sound-dai-cells":
    const: 0

  everest,jack-pol:
    $ref: /schemas/types.yaml#/definitions/uint8
    description: |
      just the value of reg 57. Bit(3) decides whether the jack polarity is inverted.
      Bit(2) decides whether the button on the headset is inverted.
      Bit(1)/(0) decides the mic properity to be OMTP/CTIA or auto.
    minimum: 0x00
    maximum: 0x0f
    default: 0x0f

  everest,mic1-src:
    $ref: /schemas/types.yaml#/definitions/uint8
    description:
      the value of reg 2A when headset plugged.
    minimum: 0x00
    maximum: 0x77
    default: 0x22

  everest,mic2-src:
    $ref: /schemas/types.yaml#/definitions/uint8
    description:
      the value of reg 2A when headset unplugged.
    minimum: 0x00
    maximum: 0x77
    default: 0x44

  everest,jack-detect-inverted:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Defined to invert the jack detection.

  everest,interrupt-src:
    $ref: /schemas/types.yaml#/definitions/uint8
    description: |
      value of reg 0x58, Defines the interrupt source.
      Bit(2) 1 means button press triggers irq, 0 means not.
      Bit(3) 1 means PIN9 is the irq source for jack detection. When set to 0,
      bias change on PIN9 do not triggers irq.
      Bit(4) 1 means PIN27 is the irq source for jack detection.
      Bit(5) 1 means PIN9 is the irq source after MIC detect.
      Bit(6) 1 means PIN27 is the irq source after MIC detect.
    minimum: 0
    maximum: 0x3c
    default: 0x08

  everest,interrupt-clk:
    $ref: /schemas/types.yaml#/definitions/uint8
    description: |
     value of reg 0x59, Defines the interrupt output behavior.
     Bit(0-3) 0 means irq pulse equals 512*internal clock
       1 means irq pulse equals 1024*internal clock
       2 means ...
       7 means irq pulse equals 65536*internal clock
       8 means irq mutes PA
       9 means irq mutes PA and DAC output
     Bit(4) 1 means we invert the interrupt output.
     Bit(6) 1 means the chip do not detect jack type after button released.
       0 means the chip detect jack type again after button released.
    minimum: 0
    maximum: 0x7f
    default: 0x45

required:
  - compatible
  - reg
  - "#sound-dai-cells"

additionalProperties: false

examples:
  - |
    i2c {
      #address-cells = <1>;
      #size-cells = <0>;
      es8326: codec@19 {
        compatible = "everest,es8326";
        reg = <0x19>;
        clocks = <&clks 10>;
        clock-names = "mclk";
        #sound-dai-cells = <0>;
        everest,mic1-src = [22];
        everest,mic2-src = [44];
        everest,jack-pol = [0e];
        everest,interrupt-src = [08];
        everest,interrupt-clk = [45];
      };
    };


code:
Freescale Asynchronous Sample Rate Converter (ASRC) Controller

The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
signal associated with an input clock into a signal associated with a different
output clock. The driver currently works as a Front End of DPCM with other Back
Ends Audio controller such as ESAI, SSI and SAI. It has three pairs to support
three substreams within totally 10 channels.

Required properties:

  - compatible		: Compatible list, should contain one of the following
			  compatibles:
			  "fsl,imx35-asrc",
			  "fsl,imx53-asrc",
			  "fsl,imx8qm-asrc",
			  "fsl,imx8qxp-asrc",

  - reg			: Offset and length of the register set for the device.

  - interrupts		: Contains the spdif interrupt.

  - dmas		: Generic dma devicetree binding as described in
			  Documentation/devicetree/bindings/dma/dma.txt.

  - dma-names		: Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc".

  - clocks		: Contains an entry for each entry in clock-names.

  - clock-names		: Contains the following entries
	"mem"		  Peripheral access clock to access registers.
	"ipg"		  Peripheral clock to driver module.
	"asrck_<0-f>"	  Clock sources for input and output clock.
	"spba"		  The spba clock is required when ASRC is placed as a
			  bus slave of the Shared Peripheral Bus and when two
			  or more bus masters (CPU, DMA or DSP) try to access
			  it. This property is optional depending on the SoC
			  design.

   - fsl,asrc-rate	: Defines a mutual sample rate used by DPCM Back Ends.

   - fsl,asrc-width	: Defines a mutual sample width used by DPCM Back Ends.

   - fsl,asrc-clk-map   : Defines clock map used in driver. which is required
			  by imx8qm/imx8qxp platform
			  <0> - select the map for asrc0 in imx8qm/imx8qxp
			  <1> - select the map for asrc1 in imx8qm/imx8qxp

Optional properties:

   - big-endian		: If this property is absent, the little endian mode
			  will be in use as default. Otherwise, the big endian
			  mode will be in use for all the device registers.

   - fsl,asrc-format	: Defines a mutual sample format used by DPCM Back
			  Ends, which can replace the fsl,asrc-width.
			  The value is 2 (S16_LE), or 6 (S24_LE).

Example:

asrc: asrc@2034000 {
	compatible = "fsl,imx53-asrc";
	reg = <0x02034000 0x4000>;
	interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks 107>, <&clks 107>, <&clks 0>,
	       <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
	       <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
	       <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
	       <&clks 107>, <&clks 0>, <&clks 0>;
	clock-names = "mem", "ipg", "asrck0",
		"asrck_1", "asrck_2", "asrck_3", "asrck_4",
		"asrck_5", "asrck_6", "asrck_7", "asrck_8",
		"asrck_9", "asrck_a", "asrck_b", "asrck_c",
		"asrck_d", "asrck_e", "asrck_f";
	dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
	     <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
	dma-names = "rxa", "rxb", "rxc",
		"txa", "txb", "txc";
	fsl,asrc-rate  = <48000>;
	fsl,asrc-width = <16>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,aud2htx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP Audio Subsystem to HDMI RTX Subsystem Controller

maintainers:
  - Shengjiu Wang <shengjiu.wang@nxp.com>

properties:
  compatible:
    const: fsl,imx8mp-aud2htx

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Peripheral clock

  clock-names:
    items:
      - const: bus

  dmas:
    items:
      - description: DMA controller phandle and request line for TX

  dma-names:
    items:
      - const: tx

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - dmas
  - dma-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/imx8mp-clock.h>

    aud2htx: aud2htx@30cb0000 {
        compatible = "fsl,imx8mp-aud2htx";
        reg = <0x30cb0000 0x10000>;
        interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>;
        clock-names = "bus";
        dmas = <&sdma2 26 2 0>;
        dma-names = "tx";
        power-domains = <&audiomix_pd>;
    };


code:
NXP Audio Mixer (AUDMIX).

The Audio Mixer is a on-chip functional module that allows mixing of two
audio streams into a single audio stream. Audio Mixer has two input serial
audio interfaces. These are driven by two Synchronous Audio interface
modules (SAI). Each input serial interface carries 8 audio channels in its
frame in TDM manner. Mixer mixes audio samples of corresponding channels
from two interfaces into a single sample. Before mixing, audio samples of
two inputs can be attenuated based on configuration. The output of the
Audio Mixer is also a serial audio interface. Like input interfaces it has
the same TDM frame format. This output is used to drive the serial DAC TDM
interface of audio codec and also sent to the external pins along with the
receive path of normal audio SAI module for readback by the CPU.

The output of Audio Mixer can be selected from any of the three streams
 - serial audio input 1
 - serial audio input 2
 - mixed audio

Mixing operation is independent of audio sample rate but the two audio
input streams must have same audio sample rate with same number of channels
in TDM frame to be eligible for mixing.

Device driver required properties:
=================================
  - compatible		: Compatible list, contains "fsl,imx8qm-audmix"

  - reg			: Offset and length of the register set for the device.

  - clocks		: Must contain an entry for each entry in clock-names.

  - clock-names		: Must include the "ipg" for register access.

  - power-domains	: Must contain the phandle to AUDMIX power domain node

  - dais		: Must contain a list of phandles to AUDMIX connected
			  DAIs. The current implementation requires two phandles
			  to SAI interfaces to be provided, the first SAI in the
			  list being used to route the AUDMIX output.

Device driver configuration example:
======================================
  audmix: audmix@59840000 {
    compatible = "fsl,imx8qm-audmix";
    reg = <0x0 0x59840000 0x0 0x10000>;
    clocks = <&clk IMX8QXP_AUD_AUDMIX_IPG>;
    clock-names = "ipg";
    power-domains = <&pd_audmix>;
    dais = <&sai4>, <&sai5>;
  };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,easrc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP Asynchronous Sample Rate Converter (ASRC) Controller

maintainers:
  - Shengjiu Wang <shengjiu.wang@nxp.com>

properties:
  $nodename:
    pattern: "^easrc@.*"

  compatible:
    const: fsl,imx8mn-easrc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Peripheral clock

  clock-names:
    items:
      - const: mem

  dmas:
    maxItems: 8

  dma-names:
    items:
      - const: ctx0_rx
      - const: ctx0_tx
      - const: ctx1_rx
      - const: ctx1_tx
      - const: ctx2_rx
      - const: ctx2_tx
      - const: ctx3_rx
      - const: ctx3_tx

  firmware-name:
    $ref: /schemas/types.yaml#/definitions/string
    const: imx/easrc/easrc-imx8mn.bin
    description: The coefficient table for the filters

  fsl,asrc-rate:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 8000
    maximum: 192000
    description: Defines a mutual sample rate used by DPCM Back Ends

  fsl,asrc-format:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [2, 6, 10, 32, 36]
    default: 2
    description:
      Defines a mutual sample format used by DPCM Back Ends

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - dmas
  - dma-names
  - firmware-name
  - fsl,asrc-rate
  - fsl,asrc-format

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mn-clock.h>

    easrc: easrc@300c0000 {
           compatible = "fsl,imx8mn-easrc";
           reg = <0x300c0000 0x10000>;
           interrupts = <0x0 122 0x4>;
           clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
           clock-names = "mem";
           dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
                  <&sdma2 18 23 0> , <&sdma2 19 23 0>,
                  <&sdma2 20 23 0> , <&sdma2 21 23 0>,
                  <&sdma2 22 23 0> , <&sdma2 23 23 0>;
           dma-names = "ctx0_rx", "ctx0_tx",
                       "ctx1_rx", "ctx1_tx",
                       "ctx2_rx", "ctx2_tx",
                       "ctx3_rx", "ctx3_tx";
           firmware-name = "imx/easrc/easrc-imx8mn.bin";
           fsl,asrc-rate  = <8000>;
           fsl,asrc-format = <2>;
    };


code:
Freescale Enhanced Serial Audio Interface (ESAI) Controller

The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
for serial communication with a variety of serial devices, including industry
standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and
other DSPs. It has up to six transmitters and four receivers.

Required properties:

  - compatible		: Compatible list, should contain one of the following
			  compatibles:
			  "fsl,imx35-esai",
			  "fsl,vf610-esai",
			  "fsl,imx6ull-esai",
			  "fsl,imx8qm-esai",

  - reg			: Offset and length of the register set for the device.

  - interrupts		: Contains the spdif interrupt.

  - dmas		: Generic dma devicetree binding as described in
			  Documentation/devicetree/bindings/dma/dma.txt.

  - dma-names		: Two dmas have to be defined, "tx" and "rx".

  - clocks		: Contains an entry for each entry in clock-names.

  - clock-names		: Includes the following entries:
	"core"		  The core clock used to access registers
	"extal"		  The esai baud clock for esai controller used to
			  derive HCK, SCK and FS.
	"fsys"		  The system clock derived from ahb clock used to
			  derive HCK, SCK and FS.
	"spba"		  The spba clock is required when ESAI is placed as a
			  bus slave of the Shared Peripheral Bus and when two
			  or more bus masters (CPU, DMA or DSP) try to access
			  it. This property is optional depending on the SoC
			  design.

  - fsl,fifo-depth	: The number of elements in the transmit and receive
			  FIFOs. This number is the maximum allowed value for
			  TFCR[TFWM] or RFCR[RFWM].

  - fsl,esai-synchronous: This is a boolean property. If present, indicating
			  that ESAI would work in the synchronous mode, which
			  means all the settings for Receiving would be
			  duplicated from Transmition related registers.

Optional properties:

  - big-endian		: If this property is absent, the native endian mode
			  will be in use as default, or the big endian mode
			  will be in use for all the device registers.

Example:

esai: esai@2024000 {
	compatible = "fsl,imx35-esai";
	reg = <0x02024000 0x4000>;
	interrupts = <0 51 0x04>;
	clocks = <&clks 208>, <&clks 118>, <&clks 208>;
	clock-names = "core", "extal", "fsys";
	dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <128>;
	fsl,esai-synchronous;
	big-endian;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,micfil.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP MICFIL Digital Audio Interface (MICFIL)

maintainers:
  - Shengjiu Wang <shengjiu.wang@nxp.com>

description: |
  The MICFIL digital interface provides a 16-bit or 24-bit audio signal
  from a PDM microphone bitstream in a configurable output sampling rate.

properties:
  compatible:
    enum:
      - fsl,imx8mm-micfil
      - fsl,imx8mp-micfil
      - fsl,imx93-micfil

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: Digital Microphone interface interrupt
      - description: Digital Microphone interface error interrupt
      - description: voice activity detector event interrupt
      - description: voice activity detector error interrupt

  dmas:
    items:
      - description: DMA controller phandle and request line for RX

  dma-names:
    items:
      - const: rx

  clocks:
    items:
      - description: The ipg clock for register access
      - description: internal micfil clock
      - description: PLL clock source for 8kHz series
      - description: PLL clock source for 11kHz series
      - description: External clock 3
    minItems: 2

  clock-names:
    items:
      - const: ipg_clk
      - const: ipg_clk_app
      - const: pll8k
      - const: pll11k
      - const: clkext3
    minItems: 2

required:
  - compatible
  - reg
  - interrupts
  - dmas
  - dma-names
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/imx8mm-clock.h>
    micfil: audio-controller@30080000 {
        compatible = "fsl,imx8mm-micfil";
        reg = <0x30080000 0x10000>;
        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MM_CLK_PDM_IPG>,
                 <&clk IMX8MM_CLK_PDM_ROOT>;
        clock-names = "ipg_clk", "ipg_clk_app";
        dmas = <&sdma2 24 25 0>;
        dma-names = "rx";
    };


code:
fsl,mqs audio CODEC

Required properties:
  - compatible : Must contain one of "fsl,imx6sx-mqs", "fsl,codec-mqs"
		"fsl,imx8qm-mqs", "fsl,imx8qxp-mqs", "fsl,imx93-mqs".
  - clocks : A list of phandles + clock-specifiers, one for each entry in
	     clock-names
  - clock-names : "mclk" - must required.
		  "core" - required if compatible is "fsl,imx8qm-mqs", it
		           is for register access.
  - gpr : A phandle of General Purpose Registers in IOMUX Controller.
	  Required if compatible is "fsl,imx6sx-mqs".

Required if compatible is "fsl,imx8qm-mqs":
  - power-domains: A phandle of PM domain provider node.
  - reg: Offset and length of the register set for the device.

Example:

mqs: mqs {
	compatible = "fsl,imx6sx-mqs";
	gpr = <&gpr>;
	clocks = <&clks IMX6SX_CLK_SAI1>;
	clock-names = "mclk";
	status = "disabled";
};

mqs: mqs@59850000 {
	compatible = "fsl,imx8qm-mqs";
	reg = <0x59850000 0x10000>;
	clocks = <&clk IMX8QM_AUD_MQS_IPG>,
		 <&clk IMX8QM_AUD_MQS_HMCLK>;
	clock-names = "core", "mclk";
	power-domains = <&pd_mqs0>;
	status = "disabled";
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,rpmsg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP Audio RPMSG CPU DAI Controller

maintainers:
  - Shengjiu Wang <shengjiu.wang@nxp.com>

description: |
  fsl_rpmsg is a virtual audio device. Mapping to real hardware devices
  are SAI, MICFIL, DMA controlled by Cortex M core. What we see from
  Linux side is a device which provides audio service by rpmsg channel.
  We can create different sound cards which access different hardwares
  such as SAI, MICFIL, .etc through building rpmsg channels between
  Cortex-A and Cortex-M.

properties:
  compatible:
    enum:
      - fsl,imx7ulp-rpmsg-audio
      - fsl,imx8mn-rpmsg-audio
      - fsl,imx8mm-rpmsg-audio
      - fsl,imx8mp-rpmsg-audio
      - fsl,imx8ulp-rpmsg-audio

  model:
    $ref: /schemas/types.yaml#/definitions/string
    description: User specified audio sound card name

  clocks:
    items:
      - description: Peripheral clock for register access
      - description: Master clock
      - description: DMA clock for DMA register access
      - description: Parent clock for multiple of 8kHz sample rates
      - description: Parent clock for multiple of 11kHz sample rates

  clock-names:
    items:
      - const: ipg
      - const: mclk
      - const: dma
      - const: pll8k
      - const: pll11k

  power-domains:
    description:
      List of phandle and PM domain specifier as documented in
      Documentation/devicetree/bindings/power/power_domain.txt
    maxItems: 1

  memory-region:
    maxItems: 1
    description:
      phandle to a node describing reserved memory (System RAM memory)
      The M core can't access all the DDR memory space on some platform,
      So reserved a specific memory for dma buffer which M core can
      access.
      (see bindings/reserved-memory/reserved-memory.txt)

  audio-codec:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: The phandle to a node of audio codec

  audio-routing:
    $ref: /schemas/types.yaml#/definitions/non-unique-string-array
    description: |
      A list of the connections between audio components. Each entry is a
      pair of strings, the first being the connection's sink, the second
      being the connection's source.

  fsl,enable-lpa:
    $ref: /schemas/types.yaml#/definitions/flag
    description: enable low power audio path.

  fsl,rpmsg-out:
    $ref: /schemas/types.yaml#/definitions/flag
    description: |
      This is a boolean property. If present, the transmitting function
      will be enabled.

  fsl,rpmsg-in:
    $ref: /schemas/types.yaml#/definitions/flag
    description: |
      This is a boolean property. If present, the receiving function
      will be enabled.

  fsl,rpmsg-channel-name:
    $ref: /schemas/types.yaml#/definitions/string
    description: |
      A string property to assign rpmsg channel this sound card sits on.
      This property can be omitted if there is only one sound card and it sits
      on "rpmsg-audio-channel".
    enum:
      - rpmsg-audio-channel
      - rpmsg-micfil-channel

required:
  - compatible
  - model

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mn-clock.h>

    rpmsg_audio: rpmsg_audio {
        compatible = "fsl,imx8mn-rpmsg-audio";
        model = "wm8524-audio";
        fsl,enable-lpa;
        fsl,rpmsg-out;
        clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
                 <&clk IMX8MN_CLK_SAI3_ROOT>,
                 <&clk IMX8MN_CLK_SDMA3_ROOT>,
                 <&clk IMX8MN_AUDIO_PLL1_OUT>,
                 <&clk IMX8MN_AUDIO_PLL2_OUT>;
        clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k";
    };

  - |
    #include <dt-bindings/clock/imx8mm-clock.h>

    rpmsg_micfil: audio-controller {
        compatible = "fsl,imx8mm-rpmsg-audio";
        model = "micfil-audio";
        fsl,rpmsg-channel-name = "rpmsg-micfil-channel";
        fsl,enable-lpa;
        fsl,rpmsg-in;
        clocks = <&clk IMX8MM_CLK_PDM_IPG>,
                 <&clk IMX8MM_CLK_PDM_ROOT>,
                 <&clk IMX8MM_CLK_SDMA3_ROOT>,
                 <&clk IMX8MM_AUDIO_PLL1_OUT>,
                 <&clk IMX8MM_AUDIO_PLL2_OUT>;
        clock-names = "ipg", "mclk", "dma", "pll8k", "pll11k";
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Synchronous Audio Interface (SAI).

maintainers:
  - Shengjiu Wang <shengjiu.wang@nxp.com>

description: |
  The SAI is based on I2S module that used communicating with audio codecs,
  which provides a synchronous audio interface that supports fullduplex
  serial interfaces with frame synchronization such as I2S, AC97, TDM, and
  codec/DSP interfaces.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - fsl,imx6ul-sai
              - fsl,imx7d-sai
          - const: fsl,imx6sx-sai

      - items:
          - enum:
              - fsl,imx8mm-sai
              - fsl,imx8mn-sai
              - fsl,imx8mp-sai
          - const: fsl,imx8mq-sai

      - items:
          - enum:
              - fsl,imx6sx-sai
              - fsl,imx7ulp-sai
              - fsl,imx8mq-sai
              - fsl,imx8qm-sai
              - fsl,imx8ulp-sai
              - fsl,vf610-sai

  reg:
    maxItems: 1

  clocks:
    items:
      - description: The ipg clock for register access
      - description: master clock source 0 (obsoleted)
      - description: master clock source 1
      - description: master clock source 2
      - description: master clock source 3
      - description: PLL clock source for 8kHz series
      - description: PLL clock source for 11kHz series
    minItems: 4

  clock-names:
    oneOf:
      - items:
          - const: bus
          - const: mclk0
          - const: mclk1
          - const: mclk2
          - const: mclk3
          - const: pll8k
          - const: pll11k
        minItems: 5
      - items:
          - const: bus
          - const: mclk1
          - const: mclk2
          - const: mclk3
          - const: pll8k
          - const: pll11k
        minItems: 4

  dmas:
    maxItems: 2

  dma-names:
    maxItems: 2

  interrupts:
    items:
      - description: receive and transmit interrupt

  big-endian:
    description: |
      required if all the SAI registers are big-endian rather than little-endian.
    type: boolean

  fsl,dataline:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    description: |
      Configure the dataline. It has 3 value for each configuration
    maxItems: 16
    items:
      items:
        - description: format Default(0), I2S(1) or PDM(2)
          enum: [0, 1, 2]
        - description: dataline mask for 'rx'
        - description: dataline mask for 'tx'

  fsl,sai-mclk-direction-output:
    description: SAI will output the SAI MCLK clock.
    type: boolean

  fsl,sai-synchronous-rx:
    description: |
      SAI will work in the synchronous mode (sync Tx with Rx) which means
      both the transmitter and the receiver will send and receive data by
      following receiver's bit clocks and frame sync clocks.
    type: boolean

  fsl,sai-asynchronous:
    description: |
      SAI will work in the asynchronous mode, which means both transmitter
      and receiver will send and receive data by following their own bit clocks
      and frame sync clocks separately.
      If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
      default synchronous mode (sync Rx with Tx) will be used, which means both
      transmitter and receiver will send and receive data by following clocks
      of transmitter.
    type: boolean

  fsl,shared-interrupt:
    description: Interrupt is shared with other modules.
    type: boolean

  lsb-first:
    description: |
      Configures whether the LSB or the MSB is transmitted
      first for the fifo data. If this property is absent,
      the MSB is transmitted first as default, or the LSB
      is transmitted first.
    type: boolean

  "#sound-dai-cells":
    const: 0
    description: optional, some dts node didn't add it.

allOf:
  - $ref: dai-common.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: fsl,vf610-sai
    then:
      properties:
        dmas:
          items:
            - description: DMA controller phandle and request line for TX
            - description: DMA controller phandle and request line for RX
        dma-names:
          items:
            - const: tx
            - const: rx
    else:
      properties:
        dmas:
          items:
            - description: DMA controller phandle and request line for RX
            - description: DMA controller phandle and request line for TX
        dma-names:
          items:
            - const: rx
            - const: tx
  - if:
      required:
        - fsl,sai-asynchronous
    then:
      properties:
        fsl,sai-synchronous-rx: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - dmas
  - dma-names
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/vf610-clock.h>
    sai2: sai@40031000 {
        compatible = "fsl,vf610-sai";
        reg = <0x40031000 0x1000>;
        interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sai2_1>;
        clocks = <&clks VF610_CLK_PLATFORM_BUS>,
                 <&clks VF610_CLK_SAI2>,
                 <&clks 0>, <&clks 0>;
        clock-names = "bus", "mclk1", "mclk2", "mclk3";
        dma-names = "tx", "rx";
        dmas = <&edma0 0 21>,
               <&edma0 0 20>;
        big-endian;
        lsb-first;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/imx8mm-clock.h>
    sai1: sai@30010000 {
        compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
        reg = <0x30010000 0x10000>;
        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
                 <&clk IMX8MM_CLK_DUMMY>,
                 <&clk IMX8MM_CLK_SAI1_ROOT>,
                 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
        clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
        dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
        dma-names = "rx", "tx";
        fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
        #sound-dai-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,spdif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller

maintainers:
  - Shengjiu Wang <shengjiu.wang@nxp.com>

description: |
  The Freescale S/PDIF audio block is a stereo transceiver that allows the
  processor to receive and transmit digital audio via an coaxial cable or
  a fibre cable.

properties:
  compatible:
    enum:
      - fsl,imx35-spdif
      - fsl,vf610-spdif
      - fsl,imx6sx-spdif
      - fsl,imx8qm-spdif
      - fsl,imx8qxp-spdif
      - fsl,imx8mq-spdif
      - fsl,imx8mm-spdif
      - fsl,imx8mn-spdif
      - fsl,imx8ulp-spdif

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  dmas:
    items:
      - description: DMA controller phandle and request line for RX
      - description: DMA controller phandle and request line for TX

  dma-names:
    items:
      - const: rx
      - const: tx

  clocks:
    items:
      - description: The core clock of spdif controller.
      - description: Clock for tx0 and rx0.
      - description: Clock for tx1 and rx1.
      - description: Clock for tx2 and rx2.
      - description: Clock for tx3 and rx3.
      - description: Clock for tx4 and rx4.
      - description: Clock for tx5 and rx5.
      - description: Clock for tx6 and rx6.
      - description: Clock for tx7 and rx7.
      - description: The spba clock is required when SPDIF is placed as a bus
          slave of the Shared Peripheral Bus and when two or more bus masters
          (CPU, DMA or DSP) try to access it. This property is optional depending
          on the SoC design.
      - description: PLL clock source for 8kHz series rate, optional.
      - description: PLL clock source for 11khz series rate, optional.
    minItems: 9

  clock-names:
    items:
      - const: core
      - const: rxtx0
      - const: rxtx1
      - const: rxtx2
      - const: rxtx3
      - const: rxtx4
      - const: rxtx5
      - const: rxtx6
      - const: rxtx7
      - const: spba
      - const: pll8k
      - const: pll11k
    minItems: 9

  big-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description: |
      If this property is absent, the native endian mode will be in use
      as default, or the big endian mode will be in use for all the device
      registers. Set this flag for HCDs with big endian descriptors and big
      endian registers.

required:
  - compatible
  - reg
  - interrupts
  - dmas
  - dma-names
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    spdif@2004000 {
        compatible = "fsl,imx35-spdif";
        reg = <0x02004000 0x4000>;
        interrupts = <0 52 0x04>;
        dmas = <&sdma 14 18 0>,
               <&sdma 15 18 0>;
        dma-names = "rx", "tx";
        clocks = <&clks 197>, <&clks 3>,
                 <&clks 197>, <&clks 107>,
                 <&clks 0>, <&clks 118>,
                 <&clks 62>, <&clks 139>,
                 <&clks 0>;
        clock-names = "core", "rxtx0",
                      "rxtx1", "rxtx2",
                      "rxtx3", "rxtx4",
                      "rxtx5", "rxtx6",
                      "rxtx7";
        big-endian;
    };


code:
Freescale Synchronous Serial Interface

The SSI is a serial device that communicates with audio codecs.  It can
be programmed in AC97, I2S, left-justified, or right-justified modes.

Required properties:
- compatible:       Compatible list, should contain one of the following
                    compatibles:
                      fsl,mpc8610-ssi
                      fsl,imx51-ssi
                      fsl,imx35-ssi
                      fsl,imx21-ssi
- cell-index:       The SSI, <0> = SSI1, <1> = SSI2, and so on.
- reg:              Offset and length of the register set for the device.
- interrupts:       <a b> where a is the interrupt number and b is a
                    field that represents an encoding of the sense and
                    level information for the interrupt.  This should be
                    encoded based on the information in section 2)
                    depending on the type of interrupt controller you
                    have.
- fsl,fifo-depth:   The number of elements in the transmit and receive FIFOs.
                    This number is the maximum allowed value for SFCSR[TFWM0].
 - clocks:          "ipg" - Required clock for the SSI unit
                    "baud" - Required clock for SSI master mode. Otherwise this
		      clock is not used

Required are also ac97 link bindings if ac97 is used. See
Documentation/devicetree/bindings/sound/soc-ac97link.txt for the necessary
bindings.

Optional properties:
- codec-handle:     Phandle to a 'codec' node that defines an audio
                    codec connected to this SSI.  This node is typically
                    a child of an I2C or other control node.
- fsl,fiq-stream-filter: Bool property. Disabled DMA and use FIQ instead to
		    filter the codec stream. This is necessary for some boards
		    where an incompatible codec is connected to this SSI, e.g.
		    on pca100 and pcm043.
- dmas:		    Generic dma devicetree binding as described in
		    Documentation/devicetree/bindings/dma/dma.txt.
- dma-names:	    Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq
		    is not defined.
- fsl,mode:         The operating mode for the AC97 interface only.
                    "ac97-slave" - AC97 mode, SSI is clock slave
                    "ac97-master" - AC97 mode, SSI is clock master
- fsl,ssi-asynchronous:
                    If specified, the SSI is to be programmed in asynchronous
                    mode.  In this mode, pins SRCK, STCK, SRFS, and STFS must
                    all be connected to valid signals.  In synchronous mode,
                    SRCK and SRFS are ignored.  Asynchronous mode allows
                    playback and capture to use different sample sizes and
                    sample rates.  Some drivers may require that SRCK and STCK
                    be connected together, and SRFS and STFS be connected
                    together.  This would still allow different sample sizes,
                    but not different sample rates.
- fsl,playback-dma: Phandle to a node for the DMA channel to use for
                    playback of audio.  This is typically dictated by SOC
                    design.  See the notes below.
                    Only used on Power Architecture.
- fsl,capture-dma:  Phandle to a node for the DMA channel to use for
                    capture (recording) of audio.  This is typically dictated
                    by SOC design.  See the notes below.
                    Only used on Power Architecture.

Child 'codec' node required properties:
- compatible:       Compatible list, contains the name of the codec

Child 'codec' node optional properties:
- clock-frequency:  The frequency of the input clock, which typically comes
                    from an on-board dedicated oscillator.

Notes on fsl,playback-dma and fsl,capture-dma:

On SOCs that have an SSI, specific DMA channels are hard-wired for playback
and capture.  On the MPC8610, for example, SSI1 must use DMA channel 0 for
playback and DMA channel 1 for capture.  SSI2 must use DMA channel 2 for
playback and DMA channel 3 for capture.  The developer can choose which
DMA controller to use, but the channels themselves are hard-wired.  The
purpose of these two properties is to represent this hardware design.

The device tree nodes for the DMA channels that are referenced by
"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
"fsl,ssi-dma-channel".  The SOC-specific compatible string (e.g.
"fsl,mpc8610-dma-channel") can remain.  If these nodes are left as
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
drivers (fsldma) will attempt to use them, and it will conflict with the
sound drivers.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/fsl,xcvr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP Audio Transceiver (XCVR) Controller

maintainers:
  - Viorel Suman <viorel.suman@nxp.com>

description: |
  NXP XCVR (Audio Transceiver) is a on-chip functional module
  that allows CPU to receive and transmit digital audio via
  HDMI2.1 eARC, HDMI1.4 ARC and SPDIF.

properties:
  $nodename:
    pattern: "^xcvr@.*"

  compatible:
    enum:
      - fsl,imx8mp-xcvr

  reg:
    items:
      - description: 20K RAM for code and data
      - description: registers space
      - description: RX FIFO address
      - description: TX FIFO address

  reg-names:
    items:
      - const: ram
      - const: regs
      - const: rxfifo
      - const: txfifo

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Peripheral clock
      - description: PHY clock
      - description: SPBA clock
      - description: PLL clock

  clock-names:
    items:
      - const: ipg
      - const: phy
      - const: spba
      - const: pll_ipg

  dmas:
    items:
      - description: DMA controller phandle and request line for RX
      - description: DMA controller phandle and request line for TX

  dma-names:
    items:
      - const: rx
      - const: tx

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names
  - dmas
  - dma-names
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/imx8mp-clock.h>
    #include <dt-bindings/reset/imx8mp-reset.h>

    xcvr: xcvr@30cc0000 {
           compatible = "fsl,imx8mp-xcvr";
           reg = <0x30cc0000 0x800>,
                 <0x30cc0800 0x400>,
                 <0x30cc0c00 0x080>,
                 <0x30cc0e00 0x080>;
           reg-names = "ram", "regs", "rxfifo", "txfifo";
           interrupts = <0x0 128 IRQ_TYPE_LEVEL_HIGH>;
           clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
                    <&audiomix_clk IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
                    <&audiomix_clk IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
                    <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
           clock-names = "ipg", "phy", "spba", "pll_ipg";
           dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
           dma-names = "rx", "tx";
           resets = <&audiomix_reset 0>;
    };


code:
Freescale Generic ASoC Sound Card with ASRC support

The Freescale Generic ASoC Sound Card can be used, ideally, for all Freescale
SoCs connecting with external CODECs.

The idea of this generic sound card is a bit like ASoC Simple Card. However,
for Freescale SoCs (especially those released in recent years), most of them
have ASRC (Documentation/devicetree/bindings/sound/fsl,asrc.txt) inside. And
this is a specific feature that might be painstakingly controlled and merged
into the Simple Card.

So having this generic sound card allows all Freescale SoC users to benefit
from the simplification of a new card support and the capability of the wide
sample rates support through ASRC.

Note: The card is initially designed for those sound cards who use AC'97, I2S
      and PCM DAI formats. However, it'll be also possible to support those non
      AC'97/I2S/PCM type sound cards, such as S/PDIF audio and HDMI audio, as
      long as the driver has been properly upgraded.

The compatible list for this generic sound card currently:
 "fsl,imx-audio-ac97"

 "fsl,imx-audio-cs42888"

 "fsl,imx-audio-cs427x"
 (compatible with CS4271 and CS4272)

 "fsl,imx-audio-wm8962"

 "fsl,imx-audio-sgtl5000"
 (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt)

 "fsl,imx-audio-wm8960"

 "fsl,imx-audio-mqs"

 "fsl,imx-audio-wm8524"

 "fsl,imx-audio-tlv320aic32x4"

 "fsl,imx-audio-tlv320aic31xx"

 "fsl,imx-audio-si476x"

 "fsl,imx-audio-wm8958"

Required properties:

  - compatible		: Contains one of entries in the compatible list.

  - model		: The user-visible name of this sound complex

  - audio-cpu		: The phandle of an CPU DAI controller

  - audio-codec		: The phandle of an audio codec

Optional properties:

  - audio-asrc		: The phandle of ASRC. It can be absent if there's no
			  need to add ASRC support via DPCM.

  - audio-routing	: A list of the connections between audio components.
			  Each entry is a pair of strings, the first being the
			  connection's sink, the second being the connection's
			  source. There're a few pre-designed board connectors:
			   * Line Out Jack
			   * Line In Jack
			   * Headphone Jack
			   * Mic Jack
			   * Ext Spk
			   * AMIC (stands for Analog Microphone Jack)
			   * DMIC (stands for Digital Microphone Jack)

			  Note: The "Mic Jack" and "AMIC" are redundant while
			        coexisting in order to support the old bindings
				of wm8962 and sgtl5000.

  - hp-det-gpio		: The GPIO that detect headphones are plugged in
  - mic-det-gpio	: The GPIO that detect microphones are plugged in
  - bitclock-master	: Indicates dai-link bit clock master; for details see simple-card.yaml.
  - frame-master	: Indicates dai-link frame master; for details see simple-card.yaml.
  - dai-format		: audio format, for details see simple-card.yaml.
  - frame-inversion	: dai-link uses frame clock inversion, for details see simple-card.yaml.
  - bitclock-inversion	: dai-link uses bit clock inversion, for details see simple-card.yaml.
  - mclk-id		: main clock id, specific for each card configuration.

Optional unless SSI is selected as a CPU DAI:

  - mux-int-port	: The internal port of the i.MX audio muxer (AUDMUX)

  - mux-ext-port	: The external port of the i.MX audio muxer

Example:
sound-cs42888 {
	compatible = "fsl,imx-audio-cs42888";
	model = "cs42888-audio";
	audio-cpu = <&esai>;
	audio-asrc = <&asrc>;
	audio-codec = <&cs42888>;
	audio-routing =
		"Line Out Jack", "AOUT1L",
		"Line Out Jack", "AOUT1R",
		"Line Out Jack", "AOUT2L",
		"Line Out Jack", "AOUT2R",
		"Line Out Jack", "AOUT3L",
		"Line Out Jack", "AOUT3R",
		"Line Out Jack", "AOUT4L",
		"Line Out Jack", "AOUT4R",
		"AIN1L", "Line In Jack",
		"AIN1R", "Line In Jack",
		"AIN2L", "Line In Jack",
		"AIN2R", "Line In Jack";
};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/google,cros-ec-codec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Audio codec controlled by ChromeOS EC

maintainers:
  - Cheng-Yi Chiang <cychiang@chromium.org>
  - Tzung-Bi Shih <tzungbi@kernel.org>

description: |
  Google's ChromeOS EC codec is a digital mic codec provided by the
  Embedded Controller (EC) and is controlled via a host-command
  interface.  An EC codec node should only be found inside the "codecs"
  subnode of a cros-ec node.
  (see Documentation/devicetree/bindings/mfd/google,cros-ec.yaml).

allOf:
  - $ref: dai-common.yaml#

properties:
  compatible:
    const: google,cros-ec-codec

  "#sound-dai-cells":
    const: 1

  reg:
    items:
      - description: |
          Physical base address and length of shared memory region from EC.
          It contains 3 unsigned 32-bit integer. The first 2 integers
          combine to become an unsigned 64-bit physical address.
          The last one integer is the length of the shared memory.

  memory-region:
    maxItems: 1
    description: |
      Shared memory region to EC.  A "shared-dma-pool".
      See ../reserved-memory/reserved-memory.txt for details.

required:
  - compatible
  - '#sound-dai-cells'

unevaluatedProperties: false

examples:
  - |
    reserved_mem: reserved-mem@52800000 {
        compatible = "shared-dma-pool";
        reg = <0x52800000 0x100000>;
        no-map;
    };
    spi {
        #address-cells = <1>;
        #size-cells = <0>;
        cros-ec@0 {
            compatible = "google,cros-ec-spi";
            reg = <0>;
            interrupts = <93 0>;

            codecs {
                #address-cells = <2>;
                #size-cells = <1>;

                cros_ec_codec: ec-codec@10500000 {
                    compatible = "google,cros-ec-codec";
                    #sound-dai-cells = <1>;
                    reg = <0x0 0x10500000 0x80000>;
                    memory-region = <&reserved_mem>;
                };

            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/google,sc7180-trogdor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Google SC7180-Trogdor ASoC sound card driver

maintainers:
  - Rohit kumar <rohitkr@codeaurora.org>
  - Cheng-Yi Chiang <cychiang@chromium.org>

description:
  This binding describes the SC7180 sound card which uses LPASS for audio.

properties:
  compatible:
    enum:
      - google,sc7180-trogdor
      - google,sc7180-coachz

  audio-routing:
    $ref: /schemas/types.yaml#/definitions/non-unique-string-array
    description:
      A list of the connections between audio components. Each entry is a
      pair of strings, the first being the connection's sink, the second
      being the connection's source.

  model:
    $ref: /schemas/types.yaml#/definitions/string
    description: User specified audio sound card name

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  dmic-gpios:
    maxItems: 1
    description: GPIO for switching between DMICs

patternProperties:
  "^dai-link(@[0-9])?$":
    description:
      Each subnode represents a dai link. Subnodes of each dai links would be
      cpu/codec dais.

    type: object

    properties:
      link-name:
        description: Indicates dai-link name and PCM stream name.
        $ref: /schemas/types.yaml#/definitions/string
        maxItems: 1

      reg:
        maxItems: 1
        description: dai link address.

      cpu:
        description: Holds subnode which indicates cpu dai.
        type: object
        additionalProperties: false

        properties:
          sound-dai:
            maxItems: 1

      codec:
        description: Holds subnode which indicates codec dai.
        type: object
        additionalProperties: false

        properties:
          sound-dai:
            maxItems: 1

    required:
      - link-name
      - cpu
      - codec

    additionalProperties: false

required:
  - compatible
  - model
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:

  - |
    sound {
        compatible = "google,sc7180-trogdor";
        model = "sc7180-rt5682-max98357a-2mic";

        audio-routing =
                    "Headphone Jack", "HPOL",
                    "Headphone Jack", "HPOR";

        #address-cells = <1>;
        #size-cells = <0>;

        dmic-gpios = <&tlmm 86 0>;

        dai-link@0 {
            link-name = "MultiMedia0";
            reg = <0>;
            cpu {
                sound-dai = <&lpass_cpu 0>;
            };

            codec {
                sound-dai = <&alc5682 0>;
            };
        };

        dai-link@1 {
            link-name = "MultiMedia1";
            reg = <1>;
            cpu {
                sound-dai = <&lpass_cpu 1>;
            };

            codec {
                sound-dai = <&max98357a>;
            };
        };

        dai-link@2 {
            link-name = "MultiMedia2";
            reg = <2>;
            cpu {
                sound-dai = <&lpass_hdmi 0>;
            };

            codec {
                sound-dai = <&msm_dp>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/google,sc7280-herobrine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Google SC7280-Herobrine ASoC sound card driver

maintainers:
  - Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
  - Judy Hsiao <judyhsiao@chromium.org>

description:
  This binding describes the SC7280 sound card which uses LPASS for audio.

properties:
  compatible:
    enum:
      - google,sc7280-herobrine

  audio-routing:
    $ref: /schemas/types.yaml#/definitions/non-unique-string-array
    description:
      A list of the connections between audio components. Each entry is a
      pair of strings, the first being the connection's sink, the second
      being the connection's source.

  model:
    $ref: /schemas/types.yaml#/definitions/string
    description: User specified audio sound card name

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

patternProperties:
  "^dai-link@[0-9a-f]$":
    description:
      Each subnode represents a dai link. Subnodes of each dai links would be
      cpu/codec dais.

    type: object

    properties:
      link-name:
        description: Indicates dai-link name and PCM stream name.
        $ref: /schemas/types.yaml#/definitions/string
        maxItems: 1

      reg:
        maxItems: 1
        description: dai link address.

      cpu:
        description: Holds subnode which indicates cpu dai.
        type: object
        properties:
          sound-dai: true

        required:
          - sound-dai

        additionalProperties: false

      codec:
        description: Holds subnode which indicates codec dai.
        type: object
        properties:
          sound-dai: true

        required:
          - sound-dai

        additionalProperties: false

    required:
      - link-name
      - cpu
      - codec
      - reg

    additionalProperties: false

required:
  - compatible
  - model
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:

  - |
    #include <dt-bindings/sound/qcom,lpass.h>
    sound {
        compatible = "google,sc7280-herobrine";
        model = "sc7280-wcd938x-max98360a-4dmic";

        audio-routing =
            "IN1_HPHL", "HPHL_OUT",
            "IN2_HPHR", "HPHR_OUT",
            "AMIC1", "MIC BIAS1",
            "AMIC2", "MIC BIAS2",
            "VA DMIC0", "MIC BIAS3",
            "VA DMIC1", "MIC BIAS3",
            "VA DMIC2", "MIC BIAS4",
            "VA DMIC3", "MIC BIAS4",
            "TX SWR_ADC0", "ADC1_OUTPUT",
            "TX SWR_ADC1", "ADC2_OUTPUT",
            "TX SWR_ADC2", "ADC3_OUTPUT",
            "TX SWR_DMIC0", "DMIC1_OUTPUT",
            "TX SWR_DMIC1", "DMIC2_OUTPUT",
            "TX SWR_DMIC2", "DMIC3_OUTPUT",
            "TX SWR_DMIC3", "DMIC4_OUTPUT";

        #address-cells = <1>;
        #size-cells = <0>;

        dai-link@0 {
            link-name = "WCD Playback";
            reg = <LPASS_CDC_DMA_RX0>;
            cpu {
                sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>;
            };

            codec {
                sound-dai = <&wcd938x 0>, <&swr0 0>, <&rxmacro 0>;
            };
        };
        dai-link@1 {
            link-name = "WCD Capture";
            reg = <LPASS_CDC_DMA_TX3>;
            cpu {
                sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>;
            };

            codec {
                sound-dai = <&wcd938x 1>, <&swr1 0>, <&txmacro 0>;
            };
        };

        dai-link@2 {
            link-name = "MI2S Playback";
            reg = <MI2S_SECONDARY>;
            cpu {
                sound-dai = <&lpass_cpu MI2S_SECONDARY>;
            };

            codec {
                sound-dai = <&max98360a>;
            };
        };

        dai-link@3 {
            link-name = "DMIC Capture";
            reg = <LPASS_CDC_DMA_VA_TX0>;
            cpu {
                sound-dai = <&lpass_cpu LPASS_CDC_DMA_VA_TX0>;
            };

            codec {
                sound-dai = <&vamacro 0>;
            };
        };

        dai-link@5 {
            link-name = "DP Playback";
            reg = <LPASS_DP_RX>;
            cpu {
                sound-dai = <&lpass_cpu LPASS_DP_RX>;
            };

            codec {
                sound-dai = <&mdss_dp>;
            };
        };
    };


code:
GTM601 UMTS modem audio interface CODEC

This device has no configuration interface. The sample rate and channels are
based on the compatible string
	"option,gtm601" = 8kHz mono
	"broadmobi,bm818" = 48KHz stereo

Required properties:

  - compatible : one of
	"option,gtm601"
	"broadmobi,bm818"

Example:

codec: gtm601_codec {
	compatible = "option,gtm601";
};