code:
Message unit node:

For SRIO controllers that implement the message unit as part of the controller
this node is required.  For devices with RMAN this node should NOT exist.  The
node is composed of three types of sub-nodes ("fsl-srio-msg-unit",
"fsl-srio-dbell-unit" and "fsl-srio-port-write-unit").

See srio.txt for more details about generic SRIO controller details.

   - compatible
	Usage: required
	Value type: <string>
	Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu".

	The version X.Y should match the general SRIO controller's IP Block
	revision register's Major(X) and Minor (Y) value.

   - reg
	Usage: required
	Value type: <prop-encoded-array>
	Definition: A standard property.  Specifies the physical address and
		length of the SRIO configuration registers for message units
		and doorbell units.

   - fsl,liodn
	Usage: optional-but-recommended (for devices with PAMU)
	Value type: <prop-encoded-array>
	Definition: The logical I/O device number for the PAMU (IOMMU) to be
		correctly configured for SRIO accesses.  The property should
		not exist on devices that do not support PAMU.

		The LIODN value is associated with all RMU transactions
		(msg-unit, doorbell, port-write).

Sub-Nodes for RMU:  The RMU node is composed of multiple sub-nodes that
correspond to the actual sub-controllers in the RMU.  The manual for a given
SoC will detail which and how many of these sub-controllers are implemented.

Message Unit:

   - compatible
	Usage: required
	Value type: <string>
	Definition: Must include "fsl,srio-msg-unit-vX.Y", "fsl,srio-msg-unit".

	The version X.Y should match the general SRIO controller's IP Block
	revision register's Major(X) and Minor (Y) value.

   - reg
	Usage: required
	Value type: <prop-encoded-array>
	Definition: A standard property.  Specifies the physical address and
		length of the SRIO configuration registers for message units
		and doorbell units.

   - interrupts
	Usage: required
	Value type: <prop_encoded-array>
	Definition:  Specifies the interrupts generated by this device.  The
		value of the interrupts property consists of one interrupt
		specifier. The format of the specifier is defined by the
		binding document describing the node's interrupt parent.

		A pair of IRQs are specified in this property.  The first
		element is associated with the transmit (TX) interrupt and the
		second element is associated with the receive (RX) interrupt.

Doorbell Unit:

   - compatible
	Usage: required
	Value type: <string>
	Definition: Must include:
		"fsl,srio-dbell-unit-vX.Y", "fsl,srio-dbell-unit"

	The version X.Y should match the general SRIO controller's IP Block
	revision register's Major(X) and Minor (Y) value.

   - reg
	Usage: required
	Value type: <prop-encoded-array>
	Definition: A standard property.  Specifies the physical address and
		length of the SRIO configuration registers for message units
		and doorbell units.

   - interrupts
	Usage: required
	Value type: <prop_encoded-array>
	Definition:  Specifies the interrupts generated by this device.  The
		value of the interrupts property consists of one interrupt
		specifier. The format of the specifier is defined by the
		binding document describing the node's interrupt parent.

		A pair of IRQs are specified in this property.  The first
		element is associated with the transmit (TX) interrupt and the
		second element is associated with the receive (RX) interrupt.

Port-Write Unit:

   - compatible
	Usage: required
	Value type: <string>
	Definition: Must include:
		 "fsl,srio-port-write-unit-vX.Y", "fsl,srio-port-write-unit"

	The version X.Y should match the general SRIO controller's IP Block
	revision register's Major(X) and Minor (Y) value.

   - reg
	Usage: required
	Value type: <prop-encoded-array>
	Definition: A standard property.  Specifies the physical address and
		length of the SRIO configuration registers for message units
		and doorbell units.

   - interrupts
	Usage: required
	Value type: <prop_encoded-array>
	Definition:  Specifies the interrupts generated by this device.  The
		value of the interrupts property consists of one interrupt
		specifier. The format of the specifier is defined by the
		binding document describing the node's interrupt parent.

		A single IRQ that handles port-write conditions is
		specified by this property.  (Typically shared with error).

   Note: All other standard properties (see the Devicetree Specification)
   are allowed but are optional.

Example:
	rmu: rmu@d3000 {
		compatible = "fsl,srio-rmu";
		reg = <0xd3000 0x400>;
		ranges = <0x0 0xd3000 0x400>;
		fsl,liodn = <0xc8>;

		message-unit@0 {
			compatible = "fsl,srio-msg-unit";
			reg = <0x0 0x100>;
			interrupts = <
				60 2 0 0  /* msg1_tx_irq */
				61 2 0 0>;/* msg1_rx_irq */
		};
		message-unit@100 {
			compatible = "fsl,srio-msg-unit";
			reg = <0x100 0x100>;
			interrupts = <
				62 2 0 0  /* msg2_tx_irq */
				63 2 0 0>;/* msg2_rx_irq */
		};
		doorbell-unit@400 {
			compatible = "fsl,srio-dbell-unit";
			reg = <0x400 0x80>;
			interrupts = <
				56 2 0 0  /* bell_outb_irq */
				57 2 0 0>;/* bell_inb_irq */
		};
		port-write-unit@4e0 {
			compatible = "fsl,srio-port-write-unit";
			reg = <0x4e0 0x20>;
			interrupts = <16 2 1 11>;
		};
	};


code:
* Freescale Serial RapidIO (SRIO) Controller

RapidIO port node:
Properties:
   - compatible
	Usage: required
	Value type: <string>
	Definition: Must include "fsl,srio" for IP blocks with IP Block
	Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.

	Optionally, a compatible string of "fsl,srio-vX.Y" where X is Major
	version in IP Block Revision Register and Y is Minor version.  If this
	compatible is provided it should be ordered before "fsl,srio".

   - reg
	Usage: required
	Value type: <prop-encoded-array>
	Definition: A standard property.  Specifies the physical address and
		length of the SRIO configuration registers.  The size should
		be set to 0x11000.

   - interrupts
	Usage: required
	Value type: <prop_encoded-array>
	Definition:  Specifies the interrupts generated by this device.  The
		value of the interrupts property consists of one interrupt
		specifier. The format of the specifier is defined by the
		binding document describing the node's interrupt parent.

		A single IRQ that handles error conditions is specified by this
		property.  (Typically shared with port-write).

   - fsl,srio-rmu-handle:
	Usage: required if rmu node is defined
	Value type: <phandle>
	Definition: A single <phandle> value that points to the RMU.
	(See srio-rmu.txt for more details on RMU node binding)

Port Child Nodes:  There should a port child node for each port that exists in
the controller.  The ports are numbered starting at one (1) and should have
the following properties:

   - cell-index
	Usage: required
	Value type: <u32>
	Definition: A standard property.  Matches the port id.

   - ranges
	Usage: required if local access windows preset
	Value type: <prop-encoded-array>
	Definition: A standard property. Utilized to describe the memory mapped
		IO space utilized by the controller.  This corresponds to the
		setting of the local access windows that are targeted to this
		SRIO port.

   - fsl,liodn
	Usage: optional-but-recommended (for devices with PAMU)
	Value type: <prop-encoded-array>
	Definition: The logical I/O device number for the PAMU (IOMMU) to be
		correctly configured for SRIO accesses.  The property should
		not exist on devices that do not support PAMU.

		For HW (ie, the P4080) that only supports a LIODN for both
		memory and maintenance transactions then a single LIODN is
		represented in the property for both transactions.

		For HW (ie, the P304x/P5020, etc) that supports an LIODN for
		memory transactions and a unique LIODN for maintenance
		transactions then a pair of LIODNs are represented in the
		property.  Within the pair, the first element represents the
		LIODN associated with memory transactions and the second element
		represents the LIODN associated with maintenance transactions
		for the port.

Note: All other standard properties (see the Devicetree Specification)
are allowed but are optional.

Example:

	rapidio: rapidio@ffe0c0000 {
		#address-cells = <2>;
		#size-cells = <2>;
		reg = <0xf 0xfe0c0000 0 0x11000>;
		compatible = "fsl,srio";
		interrupts = <16 2 1 11>; /* err_irq */
		fsl,srio-rmu-handle = <&rmu>;
		ranges;

		port1 {
			cell-index = <1>;
			#address-cells = <2>;
			#size-cells = <2>;
			fsl,liodn = <34>;
			ranges = <0 0 0xc 0x20000000 0 0x10000000>;
		};

		port2 {
			cell-index = <2>;
			#address-cells = <2>;
			#size-cells = <2>;
			fsl,liodn = <48>;
			ranges = <0 0 0xc 0x30000000 0 0x10000000>;
		};
	};

repo_name: angery/linux


code:
*** NOTE ***
This document is copied from OPAL firmware
(skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)

There is more complete overview and documentation of features in that
source tree.  All patches and modifications should go there.
************

ibm,powerpc-cpu-features binding
================================

This device tree binding describes CPU features available to software, with
enablement, privilege, and compatibility metadata.

More general description of design and implementation of this binding is
found in design.txt, which also points to documentation of specific features.

/cpus/ibm,powerpc-cpu-features node binding
-------------------------------------------

Node: ibm,powerpc-cpu-features

Description: Container of CPU feature nodes.

The node name must be "ibm,powerpc-cpu-features".

It is implemented as a child of the node "/cpus", but this must not be
assumed by parsers.

The node is optional but should be provided by new OPAL firmware.

Properties:

- compatible
  Usage: required
  Value type: string
  Definition: "ibm,powerpc-cpu-features"

  This compatibility refers to backwards compatibility of the overall
  design with parsers that behave according to these guidelines. This can
  be extended in a backward compatible manner which would not warrant a
  revision of the compatible property.

- isa
  Usage: required
  Value type: <u32>
  Definition:

  isa that the CPU is currently running in. This provides instruction set
  compatibility, less the individual feature nodes. For example, an ISA v3.0
  implementation that lacks the "transactional-memory" cpufeature node
  should not use transactional memory facilities.

  Value corresponds to the "Power ISA Version" multiplied by 1000.
  For example, <3000> corresponds to Version 3.0, <2070> to Version 2.07.
  The minor digit is available for revisions.

- display-name
  Usage: optional
  Value type: string
  Definition:

  A human readable name for the CPU.

/cpus/ibm,powerpc-cpu-features/example-feature node bindings
----------------------------------------------------------------

Each child node of cpu-features represents a CPU feature / capability.

Node: A string describing an architected CPU feature, e.g., "floating-point".

Description: A feature or capability supported by the CPUs.

The name of the node is a human readable string that forms the interface
used to describe features to software. Features are currently documented
in the code where they are implemented in skiboot/core/cpufeatures.c

Presence of the node indicates the feature is available.

Properties:

- isa
  Usage: required
  Value type: <u32>
  Definition:

  First level of the Power ISA that the feature appears in.
  Software should filter out features when constraining the
  environment to a particular ISA version.

  Value is defined similarly to /cpus/features/isa

- usable-privilege
  Usage: required
  Value type: <u32> bit mask
  Definition:
              Bit numbers are LSB0
              bit 0 - PR (problem state / user mode)
              bit 1 - OS (privileged state)
              bit 2 - HV (hypervisor state)
              All other bits reserved and should be zero.

  This property describes the privilege levels and/or software components
  that can use the feature.

  If bit 0 is set, then the hwcap-bit-nr property will exist.

- hv-support
  Usage: optional
  Value type: <u32> bit mask
  Definition:
              Bit numbers are LSB0
              bit 0 -  HFSCR
              All other bits reserved and should be zero.

  This property describes the HV privilege support required to enable the
  feature to lesser privilege levels. If the property does not exist then no
  support is required.

  If no bits are set, the hypervisor must have explicit/custom support for
  this feature.

  If the HFSCR bit is set, then the hfscr-bit-nr property will exist and
  the feature may be enabled by setting this bit in the HFSCR register.

- os-support
  Usage: optional
  Value type: <u32> bit mask
  Definition:
              Bit numbers are LSB0
              bit 0 -  FSCR
              All other bits reserved and should be zero.

  This property describes the OS privilege support required to enable the
  feature to lesser privilege levels. If the property does not exist then no
  support is required.

  If no bits are set, the operating system must have explicit/custom support
  for this feature.

  If the FSCR bit is set, then the fscr-bit-nr property will exist and
  the feature may be enabled by setting this bit in the FSCR register.

- hfscr-bit-nr
  Usage: optional
  Value type: <u32>
  Definition: HFSCR bit position (LSB0)

  This property exists when the hv-support property HFSCR bit is set. This
  property describes the bit number in the HFSCR register that the
  hypervisor must set in order to enable this feature.

  This property also exists if an HFSCR bit corresponds with this feature.
  This makes CPU feature parsing slightly simpler.

- fscr-bit-nr
  Usage: optional
  Value type: <u32>
  Definition: FSCR bit position (LSB0)

  This property exists when the os-support property FSCR bit is set. This
  property describes the bit number in the FSCR register that the
  operating system must set in order to enable this feature.

  This property also exists if an FSCR bit corresponds with this feature.
  This makes CPU feature parsing slightly simpler.

- hwcap-bit-nr
  Usage: optional
  Value type: <u32>
  Definition: Linux ELF AUX vector bit position (LSB0)

  This property may exist when the usable-privilege property value has PR bit set.
  This property describes the bit number that should be set in the ELF AUX
  hardware capability vectors in order to advertise this feature to userspace.
  Bits 0-31 correspond to bits 0-31 in AT_HWCAP vector. Bits 32-63 correspond
  to 0-31 in AT_HWCAP2 vector, and so on.  Missing AT_HWCAPx vectors implies
  that the feature is not enabled or can not be advertised. Operating systems
  may provide a number of unassigned hardware capability bits to allow for new
  features to be advertised.

  Some properties representing features created before this binding are
  advertised to userspace without a one-to-one hwcap bit number may not specify
  this bit. Operating system will handle those bits specifically.  All new
  features usable by userspace will have a hwcap-bit-nr property.

- dependencies
  Usage: optional
  Value type: <prop-encoded-array>
  Definition:

  If this property exists then it is a list of phandles to cpu feature
  nodes that must be enabled for this feature to be enabled.

Example
-------

	/cpus/ibm,powerpc-cpu-features {
		compatible = "ibm,powerpc-cpu-features";

		isa = <3020>;

		darn {
			isa = <3000>;
			usable-privilege = <1 | 2 | 4>;
			hwcap-bit-nr = <xx>;
		};

		scv {
			isa = <3000>;
			usable-privilege = <1 | 2>;
			os-support = <0>;
			hwcap-bit-nr = <xx>;
		};

		stop {
			isa = <3000>;
			usable-privilege = <2 | 4>;
			hv-support = <0>;
			os-support = <0>;
		};

		vsx2 (hypothetical) {
			isa = <3010>;
			usable-privilege = <1 | 2 | 4>;
			hv-support = <0>;
			os-support = <0>;
			hwcap-bit-nr = <xx>;
		};

		vsx2-newinsns {
			isa = <3020>;
			usable-privilege = <1 | 2 | 4>;
			os-support = <1>;
			fscr-bit-nr = <xx>;
			hwcap-bit-nr = <xx>;
			dependencies = <&vsx2>;
		};

	};


code:
* IBM Powerpc Virtual Accelerator Switchboard (VAS)

VAS is a hardware mechanism that allows kernel subsystems and user processes
to directly submit compression and other requests to Nest accelerators (NX)
or other coprocessors functions.

Required properties:
- compatible : should be "ibm,vas".
- ibm,vas-id : A unique identifier for each instance of VAS in the system
- reg : Should contain 4 pairs of 64-bit fields specifying the Hypervisor
  window context start and length, OS/User window context start and length,
  "Paste address" start and length, "Paste window id" start bit and number
  of bits)

Example:

	vas@6019100000000 {
		compatible = "ibm,vas", "ibm,power9-vas";
		reg = <0x6019100000000 0x2000000 0x6019000000000 0x100000000 0x8000000000000 0x100000000 0x20 0x10>;
		name = "vas";
		ibm,vas-id = <0x1>;
	};


code:
Nintendo GameCube device tree
=============================

1) The "flipper" node

  This node represents the multi-function "Flipper" chip, which packages
  many of the devices found in the Nintendo GameCube.

  Required properties:

   - compatible : Should be "nintendo,flipper"

1.a) The Video Interface (VI) node

  Represents the interface between the graphics processor and a external
  video encoder.

  Required properties:

   - compatible : should be "nintendo,flipper-vi"
   - reg : should contain the VI registers location and length
   - interrupts : should contain the VI interrupt

1.b) The Processor Interface (PI) node

  Represents the data and control interface between the main processor
  and graphics and audio processor.

  Required properties:

  - compatible : should be "nintendo,flipper-pi"
  - reg : should contain the PI registers location and length

1.b.i) The "Flipper" interrupt controller node

  Represents the interrupt controller within the "Flipper" chip.
  The node for the "Flipper" interrupt controller must be placed under
  the PI node.

  Required properties:

  - compatible : should be "nintendo,flipper-pic"

1.c) The Digital Signal Procesor (DSP) node

  Represents the digital signal processor interface, designed to offload
  audio related tasks.

  Required properties:

   - compatible : should be "nintendo,flipper-dsp"
   - reg : should contain the DSP registers location and length
   - interrupts : should contain the DSP interrupt

1.c.i) The Auxiliary RAM (ARAM) node

  Represents the non cpu-addressable ram designed mainly to store audio
  related information.
  The ARAM node must be placed under the DSP node.

  Required properties:

   - compatible : should be "nintendo,flipper-aram"
   - reg : should contain the ARAM start (zero-based) and length

1.d) The Disk Interface (DI) node

  Represents the interface used to communicate with mass storage devices.

  Required properties:

   - compatible : should be "nintendo,flipper-di"
   - reg : should contain the DI registers location and length
   - interrupts : should contain the DI interrupt

1.e) The Audio Interface (AI) node

  Represents the interface to the external 16-bit stereo digital-to-analog
  converter.

  Required properties:

   - compatible : should be "nintendo,flipper-ai"
   - reg : should contain the AI registers location and length
   - interrupts : should contain the AI interrupt

1.f) The Serial Interface (SI) node

  Represents the interface to the four single bit serial interfaces.
  The SI is a proprietary serial interface used normally to control gamepads.
  It's NOT a RS232-type interface.

  Required properties:

   - compatible : should be "nintendo,flipper-si"
   - reg : should contain the SI registers location and length
   - interrupts : should contain the SI interrupt

1.g) The External Interface (EXI) node

  Represents the multi-channel SPI-like interface.

  Required properties:

   - compatible : should be "nintendo,flipper-exi"
   - reg : should contain the EXI registers location and length
   - interrupts : should contain the EXI interrupt


code:
Nintendo Wii device tree
========================

0) The root node

  This node represents the Nintendo Wii video game console.

  Required properties:

   - model : Should be "nintendo,wii"
   - compatible : Should be "nintendo,wii"

1) The "hollywood" node

  This node represents the multi-function "Hollywood" chip, which packages
  many of the devices found in the Nintendo Wii.

  Required properties:

   - compatible : Should be "nintendo,hollywood"

1.a) The Video Interface (VI) node

  Represents the interface between the graphics processor and a external
  video encoder.

  Required properties:

   - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
   - reg : should contain the VI registers location and length
   - interrupts : should contain the VI interrupt

1.b) The Processor Interface (PI) node

  Represents the data and control interface between the main processor
  and graphics and audio processor.

  Required properties:

  - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
  - reg : should contain the PI registers location and length

1.b.i) The "Flipper" interrupt controller node

  Represents the "Flipper" interrupt controller within the "Hollywood" chip.
  The node for the "Flipper" interrupt controller must be placed under
  the PI node.

  Required properties:

  - #interrupt-cells : <1>
  - compatible : should be "nintendo,flipper-pic"
  - interrupt-controller

1.c) The Digital Signal Procesor (DSP) node

  Represents the digital signal processor interface, designed to offload
  audio related tasks.

  Required properties:

   - compatible : should be "nintendo,hollywood-dsp","nintendo,flipper-dsp"
   - reg : should contain the DSP registers location and length
   - interrupts : should contain the DSP interrupt

1.d) The Serial Interface (SI) node

  Represents the interface to the four single bit serial interfaces.
  The SI is a proprietary serial interface used normally to control gamepads.
  It's NOT a RS232-type interface.

  Required properties:

   - compatible : should be "nintendo,hollywood-si","nintendo,flipper-si"
   - reg : should contain the SI registers location and length
   - interrupts : should contain the SI interrupt

1.e) The Audio Interface (AI) node

  Represents the interface to the external 16-bit stereo digital-to-analog
  converter.

  Required properties:

   - compatible : should be "nintendo,hollywood-ai","nintendo,flipper-ai"
   - reg : should contain the AI registers location and length
   - interrupts : should contain the AI interrupt

1.f) The External Interface (EXI) node

  Represents the multi-channel SPI-like interface.

  Required properties:

   - compatible : should be "nintendo,hollywood-exi","nintendo,flipper-exi"
   - reg : should contain the EXI registers location and length
   - interrupts : should contain the EXI interrupt

1.g) The Open Host Controller Interface (OHCI) nodes

  Represent the USB 1.x Open Host Controller Interfaces.

  Required properties:

   - compatible : should be "nintendo,hollywood-usb-ohci","usb-ohci"
   - reg : should contain the OHCI registers location and length
   - interrupts : should contain the OHCI interrupt

1.h) The Enhanced Host Controller Interface (EHCI) node

  Represents the USB 2.0 Enhanced Host Controller Interface.

  Required properties:

   - compatible : should be "nintendo,hollywood-usb-ehci","usb-ehci"
   - reg : should contain the EHCI registers location and length
   - interrupts : should contain the EHCI interrupt

1.i) The Secure Digital Host Controller Interface (SDHCI) nodes

  Represent the Secure Digital Host Controller Interfaces.

  Required properties:

   - compatible : should be "nintendo,hollywood-sdhci","sdhci"
   - reg : should contain the SDHCI registers location and length
   - interrupts : should contain the SDHCI interrupt

1.j) The Inter-Processor Communication (IPC) node

  Represent the Inter-Processor Communication interface. This interface
  enables communications between the Broadway and the Starlet processors.

   - compatible : should be "nintendo,hollywood-ipc"
   - reg : should contain the IPC registers location and length
   - interrupts : should contain the IPC interrupt

1.k) The "Hollywood" interrupt controller node

  Represents the "Hollywood" interrupt controller within the
  "Hollywood" chip.

  Required properties:

  - #interrupt-cells : <1>
  - compatible : should be "nintendo,hollywood-pic"
  - reg : should contain the controller registers location and length
  - interrupt-controller
  - interrupts : should contain the cascade interrupt of the "flipper" pic

1.l) The General Purpose I/O (GPIO) controller node

  see Documentation/devicetree/bindings/gpio/nintendo,hollywood-gpio.txt

1.m) The control node

  Represents the control interface used to setup several miscellaneous
  settings of the "Hollywood" chip like boot memory mappings, resets,
  disk interface mode, etc.

  Required properties:

   - compatible : should be "nintendo,hollywood-control"
   - reg : should contain the control registers location and length

1.n) The Disk Interface (DI) node

  Represents the interface used to communicate with mass storage devices.

  Required properties:

   - compatible : should be "nintendo,hollywood-di"
   - reg : should contain the DI registers location and length
   - interrupts : should contain the DI interrupt


code:
IBM OPAL Operator Panel Binding
-------------------------------

Required properties:
- compatible : Should be "ibm,opal-oppanel".
- #lines     : Number of lines on the operator panel e.g. <0x2>.
- #length    : Number of characters per line of the operator panel e.g. <0x10>.

Example:
	oppanel {
		compatible = "ibm,opal-oppanel";
		#lines = <0x2>;
		#length = <0x10>;
	};


code:
IBM Power-Management Bindings
=============================

Linux running on baremetal POWER machines has access to the processor
idle states. The description of these idle states is exposed via the
node @power-mgt in the device-tree by the firmware.

Definitions:
----------------
Typically each idle state has the following associated properties:

- name: The name of the idle state as defined by the firmware.

- flags: indicating some aspects of this idle states such as the
         extent of state-loss, whether timebase is stopped on this
         idle states and so on. The flag bits are as follows:

- exit-latency: The latency involved in transitioning the state of the
		CPU from idle to running.

- target-residency: The minimum time that the CPU needs to reside in
		    this idle state in order to accrue power-savings
		    benefit.

Properties
----------------
The following properties provide details about the idle states. These
properties are exposed as arrays. Each entry in the property array
provides the value of that property for the idle state associated with
the array index of that entry.

If idle-states are defined, then the properties
"ibm,cpu-idle-state-names" and "ibm,cpu-idle-state-flags" are
required. The other properties are required unless mentioned
otherwise. The length of all the property arrays must be the same.

- ibm,cpu-idle-state-names:
	Array of strings containing the names of the idle states.

- ibm,cpu-idle-state-flags:
	Array of unsigned 32-bit values containing the values of the
	flags associated with the aforementioned idle-states. The
	flag bits are as follows:
		0x00000001 /* Decrementer would stop */
		0x00000002 /* Needs timebase restore */
		0x00001000 /* Restore GPRs like nap */
		0x00002000 /* Restore hypervisor resource from PACA pointer */
		0x00004000 /* Program PORE to restore PACA pointer */
		0x00010000 /* This is a nap state (POWER7,POWER8) */
		0x00020000 /* This is a fast-sleep state (POWER8)*/
		0x00040000 /* This is a winkle state (POWER8) */
		0x00080000 /* This is a fast-sleep state which requires a */
			   /* software workaround for restoring the */
			   /* timebase (POWER8) */
		0x00800000 /* This state uses SPR PMICR instruction */
			   /* (POWER8)*/
		0x00100000 /* This is a fast stop state (POWER9) */
		0x00200000 /* This is a deep-stop state (POWER9) */

- ibm,cpu-idle-state-latencies-ns:
	Array of unsigned 32-bit values containing the values of the
	exit-latencies (in ns) for the idle states in
	ibm,cpu-idle-state-names.

- ibm,cpu-idle-state-residency-ns:
	Array of unsigned 32-bit values containing the values of the
	target-residency (in ns) for the idle states in
	ibm,cpu-idle-state-names. On POWER8 this is an optional
	property. If the property is absent, the target residency for
	the "Nap", "FastSleep" are defined to 10000 and 300000000
	respectively by the kernel. On POWER9 this property is required.

- ibm,cpu-idle-state-psscr:
	Array of unsigned 64-bit values containing the values for the
	PSSCR for each of the idle states in ibm,cpu-idle-state-names.
	This property is required on POWER9 and absent on POWER8.

- ibm,cpu-idle-state-psscr-mask:
	Array of unsigned 64-bit values containing the masks
	indicating which psscr fields are set in the corresponding
	entries of ibm,cpu-idle-state-psscr. This property is
	required on POWER9 and absent on POWER8.

	Whenever the firmware sets an entry in
	ibm,cpu-idle-state-psscr-mask value to 0xf, it implies that
	only the Requested Level (RL) field of the corresponding entry
	in ibm,cpu-idle-state-psscr should be considered by the
	kernel. For such idle states, the kernel would set the
	remaining fields of the psscr to the following sane-default
	values.

		- ESL and EC bits are to 1. So wakeup from any stop
		  state will be at vector 0x100.

		- MTL and PSLL are set to the maximum allowed value as
		  per the ISA, i.e. 15.

		- The Transition Rate, TR is set to the Maximum value
                  3.

	For all the other values of the entry in
	ibm,cpu-idle-state-psscr-mask, the kernel expects all the
	psscr fields of the corresponding entry in
	ibm,cpu-idle-state-psscr to be correctly set by the firmware.

- ibm,cpu-idle-state-pmicr:
	Array of unsigned 64-bit values containing the pmicr values
	for the idle states in ibm,cpu-idle-state-names. This 64-bit
	register value is to be set in pmicr for the corresponding
	state if the flag indicates that pmicr SPR should be set. This
	is an optional property on POWER8 and is absent on
	POWER9.

- ibm,cpu-idle-state-pmicr-mask:
	Array of unsigned 64-bit values containing the mask indicating
	which of the fields of the PMICR are set in the corresponding
	entries in ibm,cpu-idle-state-pmicr. This is an optional
	property on POWER8 and is absent on POWER9.


code:
IBM OPAL Sensor Groups Binding
-------------------------------

Node: /ibm,opal/sensor-groups

Description: Contains sensor groups available in the Powernv P9
servers. Each child node indicates a sensor group.

- compatible : Should be "ibm,opal-sensor-group"

Each child node contains below properties:

- type : String to indicate the type of sensor-group

- sensor-group-id: Abstract unique identifier provided by firmware of
		   type <u32> which is used for sensor-group
		   operations like clearing the min/max history of all
		   sensors belonging to the group.

- ibm,chip-id : Chip ID

- sensors : Phandle array of child nodes of /ibm,opal/sensor/
	    belonging to this group

- ops : Array of opal-call numbers indicating available operations on
	sensor groups like clearing min/max, enabling/disabling sensor
	group.


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/powerpc/sleep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PowerPC sleep property

maintainers:
  - Rob Herring <robh@kernel.org>

description: |
  Devices on SOCs often have mechanisms for placing devices into low-power
  states that are decoupled from the devices' own register blocks.  Sometimes,
  this information is more complicated than a cell-index property can
  reasonably describe.  Thus, each device controlled in such a manner
  may contain a "sleep" property which describes these connections.

  The sleep property consists of one or more sleep resources, each of
  which consists of a phandle to a sleep controller, followed by a
  controller-specific sleep specifier of zero or more cells.

  The semantics of what type of low power modes are possible are defined
  by the sleep controller.  Some examples of the types of low power modes
  that may be supported are:

   - Dynamic: The device may be disabled or enabled at any time.
   - System Suspend: The device may request to be disabled or remain
     awake during system suspend, but will not be disabled until then.
   - Permanent: The device is disabled permanently (until the next hard
     reset).

  Some devices may share a clock domain with each other, such that they should
  only be suspended when none of the devices are in use.  Where reasonable,
  such nodes should be placed on a virtual bus, where the bus has the sleep
  property.  If the clock domain is shared among devices that cannot be
  reasonably grouped in this manner, then create a virtual sleep controller
  (similar to an interrupt nexus, except that defining a standardized
  sleep-map should wait until its necessity is demonstrated).

select: true

properties:
  sleep:
    $ref: /schemas/types.yaml#/definitions/phandle-array

additionalProperties: true


code:
Device-Tree Bindings for a PPS Signal on GPIO

These properties describe a PPS (pulse-per-second) signal connected to
a GPIO pin.

Required properties:
- compatible: should be "pps-gpio"
- gpios: one PPS GPIO in the format described by ../gpio/gpio.txt

Additional required properties for the PPS ECHO functionality:
- echo-gpios: one PPS ECHO GPIO in the format described by ../gpio/gpio.txt
- echo-active-ms: duration in ms of the active portion of the echo pulse

Optional properties:
- assert-falling-edge: when present, assert is indicated by a falling edge
                       (instead of by a rising edge)

Example:
	pps {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pps>;

		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
		assert-falling-edge;

		echo-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
		echo-active-ms = <100>;

		compatible = "pps-gpio";
	};


code:
* Broadcom Digital Timing Engine(DTE) based PTP clock

Required properties:
- compatible: should contain the core compatibility string
              and the SoC compatibility string. The SoC
              compatibility string is to handle SoC specific
              hardware differences.
              Core compatibility string:
                 "brcm,ptp-dte"
              SoC compatibility strings:
                 "brcm,iproc-ptp-dte" - for iproc based SoC's
- reg: address and length of the DTE block's NCO registers

Example:

ptp: ptp-dte@180af650 {
	compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
	reg = <0x180af650 0x10>;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ptp/ptp-idt82p33.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: IDT 82P33 PTP Clock

description: |
  IDT 82P33XXX Synchronization Management Unit (SMU) based PTP clock

maintainers:
  - Min Li <min.li.xe@renesas.com>

properties:
  compatible:
    enum:
      - idt,82p33810
      - idt,82p33813
      - idt,82p33814
      - idt,82p33831
      - idt,82p33910
      - idt,82p33913
      - idt,82p33914
      - idt,82p33931

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;
        phc@51 {
            compatible = "idt,82p33810";
            reg = <0x51>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ptp/ptp-idtcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: IDT ClockMatrix (TM) PTP Clock

maintainers:
  - Vincent Cheng <vincent.cheng.xh@renesas.com>

properties:
  compatible:
    enum:
      # For System Synchronizer
      - idt,8a34000
      - idt,8a34001
      - idt,8a34002
      - idt,8a34003
      - idt,8a34004
      - idt,8a34005
      - idt,8a34006
      - idt,8a34007
      - idt,8a34008
      - idt,8a34009
      # For Port Synchronizer
      - idt,8a34010
      - idt,8a34011
      - idt,8a34012
      - idt,8a34013
      - idt,8a34014
      - idt,8a34015
      - idt,8a34016
      - idt,8a34017
      - idt,8a34018
      - idt,8a34019
      # For Universal Frequency Translator (UFT)
      - idt,8a34040
      - idt,8a34041
      - idt,8a34042
      - idt,8a34043
      - idt,8a34044
      - idt,8a34045
      - idt,8a34046
      - idt,8a34047
      - idt,8a34048
      - idt,8a34049

  reg:
    maxItems: 1
    description:
      I2C slave address of the device.

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;
        phc@5b {
            compatible = "idt,8a34000";
            reg = <0x5b>;
        };
    };


code:
ZHAW InES PTP time stamping IP core

The IP core needs two different kinds of nodes.  The control node
lives somewhere in the memory map and specifies the address of the
control registers.  There can be up to three port handles placed as
attributes of PHY nodes.  These associate a particular MII bus with a
port index within the IP core.

Required properties of the control node:

- compatible:		"ines,ptp-ctrl"
- reg:			physical address and size of the register bank

Required format of the port handle within the PHY node:

- timestamper:		provides control node reference and
			the port channel within the IP core

Example:

	tstamper: timestamper@60000000 {
		compatible = "ines,ptp-ctrl";
		reg = <0x60000000 0x80>;
	};

	ethernet@80000000 {
		...
		mdio {
			...
			ethernet-phy@3 {
				...
				timestamper = <&tstamper 0>;
			};
		};
	};


code:
* Freescale QorIQ 1588 timer based PTP clock

General Properties:

  - compatible   Should be "fsl,etsec-ptp" for eTSEC
                 Should be "fsl,fman-ptp-timer" for DPAA FMan
                 Should be "fsl,dpaa2-ptp" for DPAA2
                 Should be "fsl,enetc-ptp" for ENETC
  - reg          Offset and length of the register set for the device
  - interrupts   There should be at least two interrupts. Some devices
                 have as many as four PTP related interrupts.

Clock Properties:

  - fsl,cksel        Timer reference clock source.
  - fsl,tclk-period  Timer reference clock period in nanoseconds.
  - fsl,tmr-prsc     Prescaler, divides the output clock.
  - fsl,tmr-add      Frequency compensation value.
  - fsl,tmr-fiper1   Fixed interval period pulse generator.
  - fsl,tmr-fiper2   Fixed interval period pulse generator.
  - fsl,tmr-fiper3   Fixed interval period pulse generator.
                     Supported only on DPAA2 and ENETC hardware.
  - fsl,max-adj      Maximum frequency adjustment in parts per billion.
  - fsl,extts-fifo   The presence of this property indicates hardware
		     support for the external trigger stamp FIFO.
  - little-endian    The presence of this property indicates the 1588 timer
		     IP block is little-endian mode. The default endian mode
		     is big-endian.

  These properties set the operational parameters for the PTP
  clock. You must choose these carefully for the clock to work right.
  Here is how to figure good values:

  TimerOsc     = selected reference clock   MHz
  tclk_period  = desired clock period       nanoseconds
  NominalFreq  = 1000 / tclk_period         MHz
  FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
  tmr_add      = ceil(2^32 / FreqDivRatio)
  OutputClock  = NominalFreq / tmr_prsc     MHz
  PulseWidth   = 1 / OutputClock            microseconds
  FiperFreq1   = desired frequency in Hz
  FiperDiv1    = 1000000 * OutputClock / FiperFreq1
  tmr_fiper1   = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
  max_adj      = 1000000000 * (FreqDivRatio - 1.0) - 1

  The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
  driver expects that tmr_fiper1 will be correctly set to produce a 1
  Pulse Per Second (PPS) signal, since this will be offered to the PPS
  subsystem to synchronize the Linux clock.

  Reference clock source is determined by the value, which is holded
  in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
  value, which will be directly written in those bits, that is why,
  according to reference manual, the next clock sources can be used:

  For eTSEC,
  <0> - external high precision timer reference clock (TSEC_TMR_CLK
        input is used for this purpose);
  <1> - eTSEC system clock;
  <2> - eTSEC1 transmit clock;
  <3> - RTC clock input.

  For DPAA FMan,
  <0> - external high precision timer reference clock (TMR_1588_CLK)
  <1> - MAC system clock (1/2 FMan clock)
  <2> - reserved
  <3> - RTC clock oscillator

  When this attribute is not used, the IEEE 1588 timer reference clock
  will use the eTSEC system clock (for Gianfar) or the MAC system
  clock (for DPAA).

Example:

	ptp_clock@24e00 {
		compatible = "fsl,etsec-ptp";
		reg = <0x24E00 0xB0>;
		interrupts = <12 0x8 13 0x8>;
		interrupt-parent = < &ipic >;
		fsl,cksel       = <1>;
		fsl,tclk-period = <10>;
		fsl,tmr-prsc    = <100>;
		fsl,tmr-add     = <0x999999A4>;
		fsl,tmr-fiper1  = <0x3B9AC9F6>;
		fsl,tmr-fiper2  = <0x00018696>;
		fsl,max-adj     = <659999998>;
	};


code:
Time stamps from MII bus snooping devices

This binding supports non-PHY devices that snoop the MII bus and
provide time stamps.  In contrast to PHY time stamping drivers (which
can simply attach their interface directly to the PHY instance), stand
alone MII time stamping drivers use this binding to specify the
connection between the snooping device and a given network interface.

Non-PHY MII time stamping drivers typically talk to the control
interface over another bus like I2C, SPI, UART, or via a memory mapped
peripheral.  This controller device is associated with one or more
time stamping channels, each of which snoops on a MII bus.

The "timestamper" property lives in a phy node and links a time
stamping channel from the controller device to that phy's MII bus.

Example:

	tstamper: timestamper@10000000 {
		compatible = "ines,ptp-ctrl";
		reg = <0x10000000 0x80>;
	};

	ethernet@20000000 {
		mdio {
			ethernet-phy@1 {
				timestamper = <&tstamper 0>;
			};
		};
	};

	ethernet@30000000 {
		mdio {
			ethernet-phy@2 {
				timestamper = <&tstamper 1>;
			};
		};
	};

In this example, time stamps from the MII bus attached to phy@1 will
appear on time stamp channel 0 (zero), and those from phy@2 appear on
channel 1.


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 PWM

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#pwm-cells":
    const: 3

  compatible:
    oneOf:
      - const: allwinner,sun4i-a10-pwm
      - const: allwinner,sun5i-a10s-pwm
      - const: allwinner,sun5i-a13-pwm
      - const: allwinner,sun7i-a20-pwm
      - const: allwinner,sun8i-h3-pwm
      - items:
          - const: allwinner,sun8i-a83t-pwm
          - const: allwinner,sun8i-h3-pwm
      - items:
          - enum:
              - allwinner,suniv-f1c100s-pwm
              - allwinner,sun8i-v3s-pwm
          - const: allwinner,sun7i-a20-pwm
      - items:
          - const: allwinner,sun50i-a64-pwm
          - const: allwinner,sun5i-a13-pwm
      - items:
          - const: allwinner,sun50i-h5-pwm
          - const: allwinner,sun5i-a13-pwm
      - const: allwinner,sun50i-h6-pwm

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: Module Clock
      - description: Bus Clock

  # Even though it only applies to subschemas under the conditionals,
  # not listing them here will trigger a warning because of the
  # additionalsProperties set to false.
  clock-names: true

  resets:
    maxItems: 1

allOf:
  - $ref: pwm.yaml#

  - if:
      properties:
        compatible:
          contains:
            const: allwinner,sun50i-h6-pwm

    then:
      properties:
        clocks:
          maxItems: 2

        clock-names:
          items:
            - const: mod
            - const: bus

      required:
        - clock-names
        - resets

    else:
      properties:
        clocks:
          maxItems: 1

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    pwm: pwm@1c20e00 {
        compatible = "allwinner,sun7i-a20-pwm";
        reg = <0x01c20e00 0xc>;
        clocks = <&osc24M>;
        #pwm-cells = <3>;
    };

  - |
    #include <dt-bindings/clock/sun50i-h6-ccu.h>
    #include <dt-bindings/reset/sun50i-h6-ccu.h>

    pwm@300a000 {
      compatible = "allwinner,sun50i-h6-pwm";
      reg = <0x0300a000 0x400>;
      clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
      clock-names = "mod", "bus";
      resets = <&ccu RST_BUS_PWM>;
      #pwm-cells = <3>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/atmel,at91sam-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Atmel/Microchip PWM controller

maintainers:
  - Claudiu Beznea <claudiu.beznea@microchip.com>

allOf:
  - $ref: "pwm.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - atmel,at91sam9rl-pwm
              - atmel,sama5d3-pwm
              - atmel,sama5d2-pwm
              - microchip,sam9x60-pwm
      - items:
          - const: microchip,sama7g5-pwm
          - const: atmel,sama5d2-pwm

  reg:
    maxItems: 1

  "#pwm-cells":
    const: 3

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    pwm0: pwm@f8034000 {
        compatible = "atmel,at91sam9rl-pwm";
        reg = <0xf8034000 0x400>;
        #pwm-cells = <3>;
    };


code:
Device-Tree bindings for Atmel's HLCDC (High-end LCD Controller) PWM driver

The Atmel HLCDC PWM is subdevice of the HLCDC MFD device.
See ../mfd/atmel-hlcdc.txt for more details.

Required properties:
 - compatible: value should be one of the following:
   "atmel,hlcdc-pwm"
 - pinctr-names: the pin control state names. Should contain "default".
 - pinctrl-0: should contain the pinctrl states described by pinctrl
   default.
 - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells
   bindings defined in pwm.yaml in this directory.

Example:

	hlcdc: hlcdc@f0030000 {
		compatible = "atmel,sama5d3-hlcdc";
		reg = <0xf0030000 0x2000>;
		clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
		clock-names = "periph_clk","sys_clk", "slow_clk";

		hlcdc_pwm: hlcdc-pwm {
			compatible = "atmel,hlcdc-pwm";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_lcd_pwm>;
			#pwm-cells = <3>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/brcm,bcm7038-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM7038 PWM controller (BCM7xxx Set Top Box PWM controller)

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    const: brcm,bcm7038-pwm

  reg:
    maxItems: 1

  "#pwm-cells":
    const: 2

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    pwm: pwm@f0408000 {
       compatible = "brcm,bcm7038-pwm";
       reg = <0xf0408000 0x28>;
       #pwm-cells = <2>;
       clocks = <&upg_fixed>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/brcm,iproc-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom iProc PWM controller

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

description:
  This controller has 4 channels.

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    const: brcm,iproc-pwm

  reg:
    maxItems: 1

  clocks:
    description: external clock
    maxItems: 1

  "#pwm-cells":
    const: 3

unevaluatedProperties: false

required:
  - reg
  - clocks

examples:
  - |
    pwm@18031000 {
        compatible = "brcm,iproc-pwm";
        reg = <0x18031000 0x28>;
        clocks = <&osc>;
        #pwm-cells = <3>;
    };


code:
Broadcom Kona PWM controller device tree bindings

This controller has 6 channels.

Required Properties :
- compatible: should contain "brcm,kona-pwm"
- reg: physical base address and length of the controller's registers
- clocks: phandle + clock specifier pair for the external clock
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a
  description of the cells format.

Refer to clocks/clock-bindings.txt for generic clock consumer properties.

Example:

pwm: pwm@3e01a000 {
	compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
	reg = <0x3e01a000 0xc4>;
	clocks = <&pwm_clk>;
	#pwm-cells = <3>;
};


code:
* Cirris Logic CLPS711X PWM controller

Required properties:
- compatible: Shall contain "cirrus,ep7209-pwm".
- reg: Physical base address and length of the controller's registers.
- clocks: phandle + clock specifier pair of the PWM reference clock.
- #pwm-cells: Should be 1. The cell specifies the index of the channel.

Example:
	pwm: pwm@80000400 {
		compatible = "cirrus,ep7312-pwm", "cirrus,ep7209-pwm";
		reg = <0x80000400 0x4>;
		clocks = <&clks 8>;
		#pwm-cells = <1>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/clk-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock based PWM controller

maintainers:
  - Nikita Travkin <nikita@trvn.ru>

description: |
  Some systems have clocks that can be exposed to external devices.
  (e.g. by muxing them to GPIO pins)
  It's often possible to control duty-cycle of such clocks which makes them
  suitable for generating PWM signal.

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    const: clk-pwm

  clocks:
    description: Clock used to generate the signal.
    maxItems: 1

  "#pwm-cells":
    const: 2

unevaluatedProperties: false

required:
  - compatible
  - clocks

examples:
  - |
    pwm {
      compatible = "clk-pwm";
      #pwm-cells = <2>;
      clocks = <&gcc 0>;
      pinctrl-names = "default";
      pinctrl-0 = <&pwm_clk_flash_default>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/google,cros-ec-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PWM controlled by ChromeOS EC

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - '"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>'

description: |
  Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller
  (EC) and controlled via a host-command interface.
  An EC PWM node should be only found as a sub-node of the EC node (see
  Documentation/devicetree/bindings/mfd/google,cros-ec.yaml).

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    oneOf:
      - description: PWM controlled using EC_PWM_TYPE_GENERIC channels.
        items:
          - const: google,cros-ec-pwm
      - description: PWM controlled using CROS_EC_PWM_DT_<...> types.
        items:
          - const: google,cros-ec-pwm-type

  "#pwm-cells":
    description: The cell specifies the PWM index.
    const: 1

required:
  - compatible
  - '#pwm-cells'

additionalProperties: false

examples:
  - |
    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        cros-ec@0 {
            compatible = "google,cros-ec-spi";
            reg = <0>;
            interrupts = <101 0>;

            cros_ec_pwm: pwm {
                compatible = "google,cros-ec-pwm";
                #pwm-cells = <1>;
            };
        };
    };


code:
*Imagination Technologies PWM DAC driver

Required properties:
  - compatible: Should be "img,pistachio-pwm"
  - reg: Should contain physical base address and length of pwm registers.
  - clocks: Must contain an entry for each entry in clock-names.
	See ../clock/clock-bindings.txt for details.
  - clock-names: Must include the following entries.
    - pwm: PWM operating clock.
    - sys: PWM system interface clock.
  - #pwm-cells: Should be 2. See pwm.yaml in this directory for the
	description of the cells format.
  - img,cr-periph: Must contain a phandle to the peripheral control
	syscon node which contains PWM control registers.

Example:
	pwm: pwm@18101300 {
		compatible = "img,pistachio-pwm";
		reg = <0x18101300 0x100>;
		clocks = <&pwm_clk>, <&system_clk>;
		clock-names = "pwm", "sys";
		#pwm-cells = <2>;
		img,cr-periph = <&cr_periph>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX PWM controller

maintainers:
  - Philipp Zabel <p.zabel@pengutronix.de>

allOf:
  - $ref: pwm.yaml#

properties:
  "#pwm-cells":
    description: |
      Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
      in this directory for a description of the cells format.
    enum:
      - 2
      - 3

  compatible:
    oneOf:
      - enum:
          - fsl,imx1-pwm
          - fsl,imx27-pwm
      - items:
          - enum:
              - fsl,imx25-pwm
              - fsl,imx31-pwm
              - fsl,imx50-pwm
              - fsl,imx51-pwm
              - fsl,imx53-pwm
              - fsl,imx6q-pwm
              - fsl,imx6sl-pwm
              - fsl,imx6sll-pwm
              - fsl,imx6sx-pwm
              - fsl,imx6ul-pwm
              - fsl,imx7d-pwm
              - fsl,imx8mm-pwm
              - fsl,imx8mn-pwm
              - fsl,imx8mp-pwm
              - fsl,imx8mq-pwm
          - const: fsl,imx27-pwm

  reg:
    maxItems: 1

  clocks:
    items:
      - description: SoC PWM ipg clock
      - description: SoC PWM per clock

  clock-names:
    items:
      - const: ipg
      - const: per

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx5-clock.h>

    pwm@53fb4000 {
        #pwm-cells = <3>;
        compatible = "fsl,imx27-pwm";
        reg = <0x53fb4000 0x4000>;
        clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
                 <&clks IMX5_CLK_PWM1_HF_GATE>;
        clock-names = "ipg", "per";
        interrupts = <61>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX TPM PWM controller

maintainers:
  - Anson Huang <anson.huang@nxp.com>

description: |
  The TPM counter and period counter are shared between multiple
  channels, so all channels should use same period setting.

allOf:
  - $ref: pwm.yaml#

properties:
  "#pwm-cells":
    const: 3

  compatible:
    enum:
      - fsl,imx7ulp-pwm

  reg:
    maxItems: 1

  assigned-clocks:
    maxItems: 1

  assigned-clock-parents:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx7ulp-clock.h>

    pwm@40250000 {
        compatible = "fsl,imx7ulp-pwm";
        reg = <0x40250000 0x1000>;
        assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
        assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
        clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
        #pwm-cells = <3>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 Intel Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/intel,keembay-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Keem Bay PWM

maintainers:
  - Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    enum:
      - intel,keembay-pwm

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  "#pwm-cells":
    const: 2

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    #define KEEM_BAY_A53_GPIO

    pwm@203200a0 {
        compatible = "intel,keembay-pwm";
        reg = <0x203200a0 0xe8>;
        clocks = <&scmi_clk KEEM_BAY_A53_GPIO>;
        #pwm-cells = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/intel,lgm-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LGM SoC PWM fan controller

maintainers:
  - Rahul Tanwar <rtanwar@maxlinear.com>

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    const: intel,lgm-pwm

  reg:
    maxItems: 1

  "#pwm-cells":
    const: 2

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - resets

additionalProperties: false

examples:
  - |
    pwm: pwm@e0d00000 {
        compatible = "intel,lgm-pwm";
        reg = <0xe0d00000 0x30>;
        #pwm-cells = <2>;
        clocks = <&cgu0 126>;
        resets = <&rcu0 0x30 21>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/iqs620a-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Azoteq IQS620A PWM Generator

maintainers:
  - Jeff LaBundy <jeff@labundy.com>

description: |
  The Azoteq IQS620A multi-function sensor generates a fixed-frequency PWM
  output represented by a "pwm" child node from the parent MFD driver. See
  Documentation/devicetree/bindings/mfd/iqs62x.yaml for further details as
  well as an example.

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    enum:
      - azoteq,iqs620a-pwm

  "#pwm-cells":
    const: 2

required:
  - compatible

additionalProperties: false

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/kontron,sl28cpld-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PWM driver for the sl28cpld board management controller

maintainers:
  - Michael Walle <michael@walle.cc>

description: |
  This module is part of the sl28cpld multi-function device. For more
  details see ../mfd/kontron,sl28cpld.yaml.

  The controller supports one PWM channel and supports only four distinct
  frequencies (250Hz, 500Hz, 1kHz, 2kHz).

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    const: kontron,sl28cpld-pwm

  reg:
    maxItems: 1

  "#pwm-cells":
    const: 2

required:
  - compatible

additionalProperties: false


code:
* NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver

Required properties:
  - compatible: Should be "nxp,lpc1850-sct-pwm"
  - reg: Should contain physical base address and length of pwm registers.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clock/clock-bindings.txt for details.
  - clock-names: Must include the following entries.
    - pwm: PWM operating clock.
  - #pwm-cells: Should be 3. See pwm.yaml in this directory for the description
    of the cells format.

Example:
  pwm: pwm@40000000 {
    compatible = "nxp,lpc1850-sct-pwm";
    reg = <0x40000000 0x1000>;
    clocks =<&ccu1 CLK_CPU_SCT>;
    clock-names = "pwm";
    #pwm-cells = <3>;
  };


code:
LPC32XX PWM controller

Required properties:
- compatible: should be "nxp,lpc3220-pwm"
- reg: physical base address and length of the controller's registers

Examples:

pwm@4005c000 {
	compatible = "nxp,lpc3220-pwm";
	reg = <0x4005c000 0x4>;
};

pwm@4005c004 {
	compatible = "nxp,lpc3220-pwm";
	reg = <0x4005c004 0x4>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek DISP_PWM Controller

maintainers:
  - Jitao Shi <jitao.shi@mediatek.com>
  - Xinlei Lee <xinlei.lee@mediatek.com>

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt2701-disp-pwm
          - mediatek,mt6595-disp-pwm
          - mediatek,mt8173-disp-pwm
          - mediatek,mt8183-disp-pwm
      - items:
          - const: mediatek,mt8167-disp-pwm
          - const: mediatek,mt8173-disp-pwm
      - items:
          - enum:
              - mediatek,mt8186-disp-pwm
              - mediatek,mt8188-disp-pwm
              - mediatek,mt8192-disp-pwm
              - mediatek,mt8195-disp-pwm
          - const: mediatek,mt8183-disp-pwm

  reg:
    maxItems: 1

  "#pwm-cells":
    const: 2

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Main Clock
      - description: Mm Clock

  clock-names:
    items:
      - const: main
      - const: mm

required:
  - compatible
  - reg
  - "#pwm-cells"
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    pwm0: pwm@1401e000 {
        compatible = "mediatek,mt8173-disp-pwm";
        reg = <0x1401e000 0x1000>;
        #pwm-cells = <2>;
        clocks = <&mmsys CLK_MM_DISP_PWM026M>,
                 <&mmsys CLK_MM_DISP_PWM0MM>;
        clock-names = "main", "mm";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip IP corePWM controller bindings

maintainers:
  - Conor Dooley <conor.dooley@microchip.com>

description: |
  corePWM is an 16 channel pulse width modulator FPGA IP

  https://www.microsemi.com/existing-parts/parts/152118

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    items:
      - const: microchip,corepwm-rtl-v4

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  "#pwm-cells":
    enum: [2, 3]
    description:
      The only flag supported by the controller is PWM_POLARITY_INVERTED.

  microchip,sync-update-mask:
    description: |
      Depending on how the IP is instantiated, there are two modes of operation.
      In synchronous mode, all channels are updated at the beginning of the PWM period,
      and in asynchronous mode updates happen as the control registers are written.
      A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
      mode is possible for each channel, and is set by the bitstream programmed to the
      FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
      control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
      At runtime a bit wide register exposed to APB can be used to toggle on/off
      synchronised mode for all channels it has been synthesised for.
      Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
      whether synchronous mode is possible for the PWM channel.

    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

  microchip,dac-mode-mask:
    description: |
      Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
      a minimum period pulse train whose High/Low average is that of the chosen duty
      cycle. This "DAC" will have far better bandwidth and ripple performance than the
      standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
      core, set at instantiation and by the bitstream programmed to the FPGA, determines
      whether a given channel operates in regular PWM or DAC mode.
      Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
      for that channel.

    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    pwm@41000000 {
      compatible = "microchip,corepwm-rtl-v4";
      microchip,sync-update-mask = /bits/ 32 <0>;
      clocks = <&clkcfg 30>;
      reg = <0x41000000 0xF0>;
      #pwm-cells = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/mxs-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale MXS PWM controller

maintainers:
  - Shawn Guo <shawnguo@kernel.org>
  - Anson Huang <anson.huang@nxp.com>

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    enum:
      - fsl,imx23-pwm

  reg:
    maxItems: 1

  "#pwm-cells":
    const: 3

  fsl,pwm-number:
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description: u32 value representing the number of PWM devices

required:
  - compatible
  - reg
  - fsl,pwm-number

additionalProperties: false

examples:
  - |
    pwm@80064000 {
        compatible = "fsl,imx23-pwm";
        reg = <0x80064000 0x2000>;
        #pwm-cells = <3>;
        fsl,pwm-number = <8>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/nvidia,tegra20-pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra PWFM controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    oneOf:
      - enum:
          - nvidia,tegra20-pwm
          - nvidia,tegra186-pwm

      - items:
          - enum:
              - nvidia,tegra30-pwm
              - nvidia,tegra114-pwm
              - nvidia,tegra124-pwm
              - nvidia,tegra132-pwm
              - nvidia,tegra210-pwm
          - enum:
              - nvidia,tegra20-pwm

      - items:
          - const: nvidia,tegra194-pwm
          - const: nvidia,tegra186-pwm

      - items:
          - const: nvidia,tegra234-pwm
          - const: nvidia,tegra194-pwm

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: pwm

  "#pwm-cells":
    const: 2

  pinctrl-names:
    items:
      - const: default
      - const: sleep

  pinctrl-0:
    description: configuration for the default/active state

  pinctrl-1:
    description: configuration for the sleep state

  operating-points-v2:
    $ref: /schemas/types.yaml#/definitions/phandle

  power-domains:
    items:
      - description: phandle to the core power domain

allOf:
  - $ref: pwm.yaml

required:
  - compatible
  - reg
  - clocks
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>

    pwm: pwm@7000a000 {
        compatible = "nvidia,tegra20-pwm";
        reg = <0x7000a000 0x100>;
        #pwm-cells = <2>;
        clocks = <&tegra_car TEGRA20_CLK_PWM>;
        resets = <&tegra_car 17>;
        reset-names = "pwm";
    };


code:
NXP PCA9685 16-channel 12-bit PWM LED controller
================================================

Required properties:
  - compatible: "nxp,pca9685-pwm"
  - #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
    the cells format.
    The index 16 is the ALLCALL channel, that sets all PWM channels at the same
    time.

Optional properties:
  - invert (bool): boolean to enable inverted logic
  - open-drain (bool): boolean to configure outputs with open-drain structure;
		       if omitted use totem-pole structure

Example:

For LEDs that are directly connected to the PCA, the following setting is
applicable:

pca: pca@41 {
	compatible = "nxp,pca9685-pwm";
	#pwm-cells = <2>;
	reg = <0x41>;
	invert;
	open-drain;
};


code:
BCM2835 PWM controller (Raspberry Pi controller)

Required properties:
- compatible: should be "brcm,bcm2835-pwm"
- reg: physical base address and length of the controller's registers
- clocks: This clock defines the base clock frequency of the PWM hardware
  system, the period and the duty_cycle of the PWM signal is a multiple of
  the base period.
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
  the cells format.

Examples:

pwm@2020c000 {
	compatible = "brcm,bcm2835-pwm";
	reg = <0x2020c000 0x28>;
	clocks = <&clk_pwm>;
	#pwm-cells = <3>;
};

clocks {
	....
		clk_pwm: pwm {
			compatible = "fixed-clock";
			reg = <3>;
			#clock-cells = <0>;
			clock-frequency = <9200000>;
		};
	....
};


code:
Berlin PWM controller

Required properties:
- compatible: should be "marvell,berlin-pwm"
- reg: physical base address and length of the controller's registers
- clocks: phandle to the input clock
- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
  the cells format.

Example:

pwm: pwm@f7f20000 {
	compatible = "marvell,berlin-pwm";
	reg = <0xf7f20000 0x40>;
	clocks = <&chip_clk CLKID_CFG>;
	#pwm-cells = <3>;
}


code:
Freescale FlexTimer Module (FTM) PWM controller

The same FTM PWM device can have a different endianness on different SoCs. The
device tree provides a property to describing this so that an operating system
device driver can handle all variants of the device. Refer to the table below
for the endianness of the FTM PWM block as integrated into the existing SoCs:

	SoC     | FTM-PWM endianness
	--------+-------------------
	Vybrid  | LE
	LS1     | BE
	LS2     | LE

Please see ../regmap/regmap.txt for more detail about how to specify endian
modes in device tree.

Required properties:
- compatible : should be "fsl,<soc>-ftm-pwm" and one of the following
   compatible strings:
  - "fsl,vf610-ftm-pwm" for PWM compatible with the one integrated on VF610
  - "fsl,imx8qm-ftm-pwm" for PWM compatible with the one integrated on i.MX8QM
- reg: Physical base address and length of the controller's registers
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
  the cells format.
- clock-names: Should include the following module clock source entries:
    "ftm_sys" (module clock, also can be used as counter clock),
    "ftm_ext" (external counter clock),
    "ftm_fix" (fixed counter clock),
    "ftm_cnt_clk_en" (external and fixed counter clock enable/disable).
- clocks: Must contain a phandle and clock specifier for each entry in
  clock-names, please see clock/clock-bindings.txt for details of the property
  values.
- pinctrl-names: Must contain a "default" entry.
- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
  See pinctrl/pinctrl-bindings.txt for details of the property values.
- big-endian: Boolean property, required if the FTM PWM registers use a big-
  endian rather than little-endian layout.

Example:

pwm0: pwm@40038000 {
		compatible = "fsl,vf610-ftm-pwm";
		reg = <0x40038000 0x1000>;
		#pwm-cells = <3>;
		clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
		clocks = <&clks VF610_CLK_FTM0>,
			<&clks VF610_CLK_FTM0_EXT_SEL>,
			<&clks VF610_CLK_FTM0_FIX_SEL>,
			<&clks VF610_CLK_FTM0_EXT_FIX_EN>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pwm0_1>;
		big-endian;
};


code:
Hisilicon PWM controller

Required properties:
-compatible: should contain one SoC specific compatible string
 The SoC specific strings supported including:
	"hisilicon,hi3516cv300-pwm"
	"hisilicon,hi3519v100-pwm"
	"hisilicon,hi3559v100-shub-pwm"
	"hisilicon,hi3559v100-pwm
- reg: physical base address and length of the controller's registers.
- clocks: phandle and clock specifier of the PWM reference clock.
- resets: phandle and reset specifier for the PWM controller reset.
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
  the cells format.

Example:
	pwm: pwm@12130000 {
		compatible = "hisilicon,hi3516cv300-pwm";
		reg = <0x12130000 0x10000>;
		clocks = <&crg_ctrl HI3516CV300_PWM_CLK>;
		resets = <&crg_ctrl 0x38 0>;
		#pwm-cells = <3>;
	};


code:
TI/National Semiconductor LP3943 PWM controller

Required properties:
  - compatible: "ti,lp3943-pwm"
  - #pwm-cells: Should be 2. See pwm.yaml in this directory for a
                description of the cells format.
                Note that this hardware limits the period length to the
                range 6250~1600000.
  - ti,pwm0 or ti,pwm1: Output pin number(s) for PWM channel 0 or 1.
    0 = output 0
    1 = output 1
    .
    .
    15 = output 15

Example:
PWM 0 is for RGB LED brightness control
PWM 1 is for brightness control of LP8557 backlight device

&i2c3 {
	lp3943@60 {
		compatible = "ti,lp3943";
		reg = <0x60>;

		/*
		 * PWM 0 : output 8, 9 and 10
		 * PWM 1 : output 15
		 */
		pwm3943: pwm {
			compatible = "ti,lp3943-pwm";
			#pwm-cells = <2>;
			ti,pwm0 = <8 9 10>;
			ti,pwm1 = <15>;
		};
	};

};

/* LEDs control with PWM 0 of LP3943 */
pwmleds {
	compatible = "pwm-leds";
	rgb {
		label = "indi::rgb";
		pwms = <&pwm3943 0 10000>;
		max-brightness = <255>;
	};
};

&i2c4 {
	/* Backlight control with PWM 1 of LP3943 */
	backlight@2c {
		compatible = "ti,lp8557";
		reg = <0x2c>;

		pwms = <&pwm3943 1 10000>;
		pwm-names = "lp8557";
	};
};


code:
MediaTek PWM controller

Required properties:
 - compatible: should be "mediatek,<name>-pwm":
   - "mediatek,mt2712-pwm": found on mt2712 SoC.
   - "mediatek,mt6795-pwm": found on mt6795 SoC.
   - "mediatek,mt7622-pwm": found on mt7622 SoC.
   - "mediatek,mt7623-pwm": found on mt7623 SoC.
   - "mediatek,mt7628-pwm": found on mt7628 SoC.
   - "mediatek,mt7629-pwm": found on mt7629 SoC.
   - "mediatek,mt8183-pwm": found on mt8183 SoC.
   - "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC.
   - "mediatek,mt8365-pwm": found on mt8365 SoC.
   - "mediatek,mt8516-pwm": found on mt8516 SoC.
 - reg: physical base address and length of the controller's registers.
 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
   the cell format.
 - clocks: phandle and clock specifier of the PWM reference clock.
 - clock-names: must contain the following, except for MT7628 which
                has no clocks
   - "top": the top clock generator
   - "main": clock used by the PWM core
   - "pwm1-3": the three per PWM clocks for mt8365
   - "pwm1-8": the eight per PWM clocks for mt2712
   - "pwm1-6": the six per PWM clocks for mt7622
   - "pwm1-5": the five per PWM clocks for mt7623
   - "pwm1"  : the PWM1 clock for mt7629
 - pinctrl-names: Must contain a "default" entry.
 - pinctrl-0: One property must exist for each entry in pinctrl-names.
   See pinctrl/pinctrl-bindings.txt for details of the property values.

Optional properties:
- assigned-clocks: Reference to the PWM clock entries.
- assigned-clock-parents: The phandle of the parent clock of PWM clock.

Example:
	pwm0: pwm@11006000 {
		compatible = "mediatek,mt7623-pwm";
		reg = <0 0x11006000 0 0x1000>;
		#pwm-cells = <2>;
		clocks = <&topckgen CLK_TOP_PWM_SEL>,
			 <&pericfg CLK_PERI_PWM>,
			 <&pericfg CLK_PERI_PWM1>,
			 <&pericfg CLK_PERI_PWM2>,
			 <&pericfg CLK_PERI_PWM3>,
			 <&pericfg CLK_PERI_PWM4>,
			 <&pericfg CLK_PERI_PWM5>;
		clock-names = "top", "main", "pwm1", "pwm2",
			      "pwm3", "pwm4", "pwm5";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm0_pins>;
	};


code:
Amlogic Meson PWM Controller
============================

Required properties:
- compatible: Shall contain "amlogic,meson8b-pwm"
                         or "amlogic,meson-gxbb-pwm"
                         or "amlogic,meson-gxbb-ao-pwm"
                         or "amlogic,meson-axg-ee-pwm"
                         or "amlogic,meson-axg-ao-pwm"
                         or "amlogic,meson-g12a-ee-pwm"
                         or "amlogic,meson-g12a-ao-pwm-ab"
                         or "amlogic,meson-g12a-ao-pwm-cd"
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
  the cells format.

Optional properties:
- clocks: Could contain one or two parents clocks phandle for each of the two
  PWM channels.
- clock-names: Could contain at least the "clkin0" and/or "clkin1" names.

Example:

	pwm_ab: pwm@8550 {
		compatible = "amlogic,meson-gxbb-pwm";
		reg = <0x0 0x08550 0x0 0x10>;
		#pwm-cells = <3>;
		clocks = <&xtal>, <&xtal>;
		clock-names = "clkin0", "clkin1";
	}


code:
* OMAP PWM for dual-mode timers

Required properties:
- compatible: Shall contain "ti,omap-dmtimer-pwm".
- ti,timers: phandle to PWM capable OMAP timer. See timer/ti,timer-dm.yaml for info
  about these timers.
- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
  the cells format.

Optional properties:
- ti,prescaler: Should be a value between 0 and 7, see the timers datasheet
- ti,clock-source: Set dmtimer parent clock, values between 0 and 2:
  - 0x00 - high-frequency system clock (timer_sys_ck)
  - 0x01 - 32-kHz always-on clock (timer_32k_ck)
  - 0x02 - external clock (timer_ext_ck, OMAP2 only)

Example:
	pwm9: dmtimer-pwm@9 {
		compatible = "ti,omap-dmtimer-pwm";
		ti,timers = <&timer9>;
		#pwm-cells = <3>;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip PWM controller

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    oneOf:
      - const: rockchip,rk2928-pwm
      - const: rockchip,rk3288-pwm
      - const: rockchip,rk3328-pwm
      - const: rockchip,vop-pwm
      - items:
          - const: rockchip,rk3036-pwm
          - const: rockchip,rk2928-pwm
      - items:
          - enum:
              - rockchip,rk3128-pwm
              - rockchip,rk3368-pwm
              - rockchip,rk3399-pwm
              - rockchip,rv1108-pwm
          - const: rockchip,rk3288-pwm
      - items:
          - enum:
              - rockchip,px30-pwm
              - rockchip,rk3308-pwm
              - rockchip,rk3568-pwm
              - rockchip,rk3588-pwm
          - const: rockchip,rk3328-pwm

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    maxItems: 2

  "#pwm-cells":
    enum: [2, 3]
    description:
      Must be 2 (rk2928) or 3 (rk3288 and later).
      See pwm.yaml for a description of the cell format.

required:
  - compatible
  - reg

allOf:
  - $ref: pwm.yaml#

  - if:
      properties:
        compatible:
          contains:
            enum:
              - rockchip,rk3328-pwm
              - rockchip,rv1108-pwm

    then:
      properties:
        clocks:
          items:
            - description: Used to derive the functional clock for the device.
            - description: Used as the APB bus clock.

        clock-names:
          items:
            - const: pwm
            - const: pclk

      required:
        - clocks
        - clock-names

    else:
      properties:
        clocks:
          maxItems: 1
          description:
            Used both to derive the functional clock
            for the device and as the bus clock.

      required:
        - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3188-cru-common.h>
    pwm0: pwm@20030000 {
      compatible = "rockchip,rk2928-pwm";
      reg = <0x20030000 0x10>;
      clocks = <&cru PCLK_PWM01>;
      #pwm-cells = <2>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung SoC PWM timers

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |+
  Samsung SoCs contain PWM timer blocks which can be used for system clock source
  and clock event timers, as well as to drive SoC outputs with PWM signal. Each
  PWM timer block provides 5 PWM channels (not all of them can drive physical
  outputs - see SoC and board manual).

  Be aware that the clocksource driver supports only uniprocessor systems.

properties:
  compatible:
    enum:
      - samsung,s3c2410-pwm             # 16-bit, S3C24xx
      - samsung,s3c6400-pwm             # 32-bit, S3C64xx
      - samsung,s5p6440-pwm             # 32-bit, S5P64x0
      - samsung,s5pc100-pwm             # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs
      - samsung,exynos4210-pwm          # 32-bit, Exynos

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 3

  clock-names:
    description: |
      Should contain all following required clock names:
      - "timers" - PWM base clock used to generate PWM signals,
      and any subset of following optional clock names:
      - "pwm-tclk0" - first external PWM clock source,
      - "pwm-tclk1" - second external PWM clock source.
      Note that not all IP variants allow using all external clock sources.
      Refer to SoC documentation to learn which clock source configurations
      are available.
    oneOf:
      - items:
          - const: timers
      - items:
          - const: timers
          - const: pwm-tclk0
      - items:
          - const: timers
          - const: pwm-tclk1
      - items:
          - const: timers
          - const: pwm-tclk0
          - const: pwm-tclk1

  interrupts:
    description:
      One interrupt per timer, starting at timer 0. Necessary only for SoCs which
      use PWM clocksource.
    minItems: 1
    maxItems: 5

  "#pwm-cells":
    description:
      The only third cell flag supported by this binding
      is PWM_POLARITY_INVERTED.
    const: 3

  samsung,pwm-outputs:
    description:
      A list of PWM channels used as PWM outputs on particular platform.
      It is an array of up to 5 elements being indices of PWM channels
      (from 0 to 4), the order does not matter.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    uniqueItems: true
    items:
      minimum: 0
      maximum: 4

required:
  - clocks
  - clock-names
  - compatible
  - reg

additionalProperties: false

allOf:
  - $ref: pwm.yaml#

  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,s3c2410-pwm
              - samsung,s3c6400-pwm
              - samsung,s5p6440-pwm
              - samsung,s5pc100-pwm
    then:
      required:
        - interrupts

examples:
  - |
    pwm@7f006000 {
        compatible = "samsung,s3c6400-pwm";
        reg = <0x7f006000 0x1000>;
        interrupt-parent = <&vic0>;
        interrupts = <23>, <24>, <25>, <27>, <28>;
        clocks = <&clock 67>;
        clock-names = "timers";
        samsung,pwm-outputs = <0>, <1>;
        #pwm-cells = <3>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive PWM controller

maintainers:
  - Sagar Kadam <sagar.kadam@sifive.com>
  - Paul Walmsley <paul.walmsley@sifive.com>

description:
  Unlike most other PWM controllers, the SiFive PWM controller currently
  only supports one period for all channels in the PWM. All PWMs need to
  run at the same period. The period also has significant restrictions on
  the values it can achieve, which the driver rounds to the nearest
  achievable period. PWM RTL that corresponds to the IP block version
  numbers can be found here -

  https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    items:
      - enum:
          - sifive,fu540-c000-pwm
          - sifive,fu740-c000-pwm
      - const: sifive,pwm0
    description:
      Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
      compatible strings are "sifive,fu540-c000-pwm" and
      "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
      SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
      SiFive PWM v0 IP block with no chip integration tweaks.
      Please refer to sifive-blocks-ip-versioning.txt for details.

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  "#pwm-cells":
    const: 3

  interrupts:
    maxItems: 4
    description:
      Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator.

required:
  - compatible
  - reg
  - clocks
  - interrupts

additionalProperties: false

examples:
  - |
    pwm:  pwm@10020000 {
      compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
      reg = <0x10020000 0x1000>;
      clocks = <&tlclk>;
      interrupt-parent = <&plic>;
      interrupts = <42>, <43>, <44>, <45>;
      #pwm-cells = <3>;
    };


code:
Spreadtrum PWM controller

Spreadtrum SoCs PWM controller provides 4 PWM channels.

Required properties:
- compatible : Should be "sprd,ums512-pwm".
- reg: Physical base address and length of the controller's registers.
- clocks: The phandle and specifier referencing the controller's clocks.
- clock-names: Should contain following entries:
  "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
  "enablen": for PWM channel n enable clock (n range: 0 ~ 3).
- #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
  the cells format.

Optional properties:
- assigned-clocks: Reference to the PWM clock entries.
- assigned-clock-parents: The phandle of the parent clock of PWM clock.

Example:
	pwms: pwm@32260000 {
		compatible = "sprd,ums512-pwm";
		reg = <0 0x32260000 0 0x10000>;
		clock-names = "pwm0", "enable0",
			"pwm1", "enable1",
			"pwm2", "enable2",
			"pwm3", "enable3";
		clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
		       <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
		       <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
		       <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
		assigned-clocks = <&aon_clk CLK_PWM0>,
			<&aon_clk CLK_PWM1>,
			<&aon_clk CLK_PWM2>,
			<&aon_clk CLK_PWM3>;
		assigned-clock-parents = <&ext_26m>,
			<&ext_26m>,
			<&ext_26m>,
			<&ext_26m>;
		#pwm-cells = <2>;
	};


code:
STMicroelectronics PWM driver bindings
--------------------------------------

Required parameters:
- compatible :		"st,pwm"
- #pwm-cells : 		Number of cells used to specify a PWM. First cell
			specifies the per-chip index of the PWM to use and the
			second cell is the period in nanoseconds - fixed to 2
			for STiH41x.
- reg :			Physical base address and length of the controller's
			registers.
- pinctrl-names: 	Set to "default".
- pinctrl-0: 		List of phandles pointing to pin configuration nodes
			for PWM module.
			For Pinctrl properties, please refer to [1].
- clock-names: 		Valid entries are "pwm" and/or "capture".
- clocks: 		phandle of the clock used by the PWM module.
			For Clk properties, please refer to [2].
- interrupts:		IRQ for the Capture device

Optional properties:
- st,pwm-num-chan:	Number of available PWM channels.  Default is 0.
- st,capture-num-chan:	Number of available Capture channels.  Default is 0.

[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
[2] Documentation/devicetree/bindings/clock/clock-bindings.txt

Example:

pwm1: pwm@fe510000 {
	compatible = "st,pwm";
	reg = <0xfe510000 0x68>;
	#pwm-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1_chan0_default
		     &pinctrl_pwm1_chan1_default
		     &pinctrl_pwm1_chan2_default
		     &pinctrl_pwm1_chan3_default>;
	clocks = <&clk_sysin>;
	clock-names = "pwm";
	st,pwm-num-chan = <4>;
	st,capture-num-chan = <2>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/pwm-tiecap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI SOC ECAP based APWM controller

maintainers:
  - Vignesh R <vigneshr@ti.com>

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    oneOf:
      - const: ti,am3352-ecap
      - items:
          - enum:
              - ti,da850-ecap
              - ti,am4372-ecap
              - ti,dra746-ecap
              - ti,k2g-ecap
              - ti,am654-ecap
              - ti,am64-ecap
          - const: ti,am3352-ecap

  reg:
    maxItems: 1

  "#pwm-cells":
    const: 3
    description: |
      See pwm.yaml in this directory for a description of the cells format.
      The only third cell flag supported by this binding is PWM_POLARITY_INVERTED.

  clock-names:
    const: fck

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    ecap0: pwm@48300100 { /* ECAP on am33xx */
        compatible = "ti,am3352-ecap";
        #pwm-cells = <3>;
        reg = <0x48300100 0x80>;
        clocks = <&l4ls_gclk>;
        clock-names = "fck";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/pwm-tiehrpwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI SOC EHRPWM based PWM controller

maintainers:
  - Vignesh R <vigneshr@ti.com>

allOf:
  - $ref: pwm.yaml#

properties:
  compatible:
    oneOf:
      - const: ti,am3352-ehrpwm
      - items:
          - enum:
              - ti,da850-ehrpwm
              - ti,am4372-ehrpwm
              - ti,dra746-ehrpwm
              - ti,am654-ehrpwm
              - ti,am64-epwm
          - const: ti,am3352-ehrpwm

  reg:
    maxItems: 1

  "#pwm-cells":
    const: 3
    description: |
      See pwm.yaml in this directory for a description of the cells format.
      The only third cell flag supported by this binding is PWM_POLARITY_INVERTED.

  clock-names:
    items:
      - const: tbclk
      - const: fck

  clocks:
    maxItems: 2

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */
        compatible = "ti,am3352-ehrpwm";
        #pwm-cells = <3>;
        reg = <0x48300200 0x100>;
        clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
        clock-names = "tbclk", "fck";
    };


code:
TI SOC based PWM Subsystem

Required properties:
- compatible: Must be "ti,<soc>-pwmss".
  for am33xx  - compatible = "ti,am33xx-pwmss";
  for am4372  - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
  for dra746 - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"

- reg: physical base address and size of the registers map.
- address-cells: Specify the number of u32 entries needed in child nodes.
		  Should set to 1.
- size-cells: specify number of u32 entries needed to specify child nodes size
		in reg property. Should set to 1.
- ranges: describes the address mapping of a memory-mapped bus. Should set to
	   physical address map of child's base address, physical address within
	   parent's address  space and length of the address map. For am33xx,
	   3 set of child register maps present, ECAP register space, EQEP
	   register space, EHRPWM register space.

Also child nodes should also populated under PWMSS DT node.

Example:
epwmss0: epwmss@48300000 { /* PWMSS for am33xx */
	compatible = "ti,am33xx-pwmss";
	reg = <0x48300000 0x10>;
	ti,hwmods = "epwmss0";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x48300100 0x48300100 0x80   /* ECAP */
		  0x48300180 0x48300180 0x80   /* EQEP */
		  0x48300200 0x48300200 0x80>; /* EHRPWM */

	/* child nodes go here */
};

epwmss0: epwmss@48300000 { /* PWMSS for am4372 */
	compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"
	reg = <0x48300000 0x10>;
	ti,hwmods = "epwmss0";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x48300100 0x48300100 0x80   /* ECAP */
		  0x48300180 0x48300180 0x80   /* EQEP */
		  0x48300200 0x48300200 0x80>; /* EHRPWM */

	/* child nodes go here */
};

epwmss0: epwmss@4843e000 { /* PWMSS for DRA7xx */
	compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
	reg = <0x4843e000 0x30>;
	ti,hwmods = "epwmss0";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	/* child nodes go here */
};


code:
Specifying PWM information for devices
======================================

1) PWM user nodes
-----------------

PWM users should specify a list of PWM devices that they want to use
with a property containing a 'pwm-list':

	pwm-list ::= <single-pwm> [pwm-list]
	single-pwm ::= <pwm-phandle> <pwm-specifier>
	pwm-phandle : phandle to PWM controller node
	pwm-specifier : array of #pwm-cells specifying the given PWM
			(controller specific)

PWM properties should be named "pwms". The exact meaning of each pwms
property must be documented in the device tree binding for each device.
An optional property "pwm-names" may contain a list of strings to label
each of the PWM devices listed in the "pwms" property. If no "pwm-names"
property is given, the name of the user node will be used as fallback.

Drivers for devices that use more than a single PWM device can use the
"pwm-names" property to map the name of the PWM device requested by the
pwm_get() call to an index into the list given by the "pwms" property.

The following example could be used to describe a PWM-based backlight
device:

	pwm: pwm {
		#pwm-cells = <2>;
	};

	[...]

	bl: backlight {
		pwms = <&pwm 0 5000000>;
		pwm-names = "backlight";
	};

Note that in the example above, specifying the "pwm-names" is redundant
because the name "backlight" would be used as fallback anyway.

pwm-specifier typically encodes the chip-relative PWM number and the PWM
period in nanoseconds.

Optionally, the pwm-specifier can encode a number of flags (defined in
<dt-bindings/pwm/pwm.h>) in a third cell:
- PWM_POLARITY_INVERTED: invert the PWM signal polarity

Example with optional PWM specifier for inverse polarity

	bl: backlight {
		pwms = <&pwm 0 5000000 PWM_POLARITY_INVERTED>;
		pwm-names = "backlight";
	};

2) PWM controller nodes
-----------------------

See pwm.yaml.


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/pwm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PWM controllers (providers)

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>

select: false

properties:
  $nodename:
    pattern: "^pwm(@.*|-[0-9a-f])*$"

  "#pwm-cells":
    description:
      Number of cells in a PWM specifier.

required:
  - "#pwm-cells"

additionalProperties: true

examples:
  - |
    pwm: pwm@1c20e00 {
        compatible = "allwinner,sun7i-a20-pwm";
        reg = <0x01c20e00 0xc>;
        clocks = <&osc24M>;
        #pwm-cells = <3>;
    };


code:
Marvell PWM controller

Required properties:
- compatible: should be one or more of:
  - "marvell,pxa250-pwm"
  - "marvell,pxa270-pwm"
  - "marvell,pxa168-pwm"
  - "marvell,pxa910-pwm"
- reg: Physical base address and length of the registers used by the PWM channel
  Note that one device instance must be created for each PWM that is used, so the
  length covers only the register window for one PWM output, not that of the
  entire PWM controller.  Currently length is 0x10 for all supported devices.
- #pwm-cells: Should be 1.  This cell is used to specify the period in
  nanoseconds.

Example PWM device node:

pwm0: pwm@40b00000 {
	compatible = "marvell,pxa250-pwm";
	reg = <0x40b00000 0x10>;
	#pwm-cells = <1>;
};

Example PWM client node:

backlight {
	compatible = "pwm-backlight";
	pwms = <&pwm0 5000000>;
	...
}


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car PWM Timer Controller

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

properties:
  compatible:
    items:
      - enum:
          - renesas,pwm-r8a7742   # RZ/G1H
          - renesas,pwm-r8a7743   # RZ/G1M
          - renesas,pwm-r8a7744   # RZ/G1N
          - renesas,pwm-r8a7745   # RZ/G1E
          - renesas,pwm-r8a77470  # RZ/G1C
          - renesas,pwm-r8a774a1  # RZ/G2M
          - renesas,pwm-r8a774b1  # RZ/G2N
          - renesas,pwm-r8a774c0  # RZ/G2E
          - renesas,pwm-r8a774e1  # RZ/G2H
          - renesas,pwm-r8a7778   # R-Car M1A
          - renesas,pwm-r8a7779   # R-Car H1
          - renesas,pwm-r8a7790   # R-Car H2
          - renesas,pwm-r8a7791   # R-Car M2-W
          - renesas,pwm-r8a7794   # R-Car E2
          - renesas,pwm-r8a7795   # R-Car H3
          - renesas,pwm-r8a7796   # R-Car M3-W
          - renesas,pwm-r8a77961  # R-Car M3-W+
          - renesas,pwm-r8a77965  # R-Car M3-N
          - renesas,pwm-r8a77970  # R-Car V3M
          - renesas,pwm-r8a77980  # R-Car V3H
          - renesas,pwm-r8a77990  # R-Car E3
          - renesas,pwm-r8a77995  # R-Car D3
      - const: renesas,pwm-rcar

  reg:
    # base address and length of the registers block for the PWM.
    maxItems: 1

  '#pwm-cells':
    # should be 2. See pwm.yaml in this directory for a description of
    # the cells format.
    const: 2

  clocks:
    # clock phandle and specifier pair.
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - power-domains

allOf:
  - $ref: pwm.yaml#

  - if:
      not:
        properties:
          compatible:
            contains:
              enum:
                - renesas,pwm-r8a7778
                - renesas,pwm-r8a7779
    then:
      required:
        - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
    #include <dt-bindings/power/r8a7743-sysc.h>

    pwm0: pwm@e6e30000 {
        compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
        reg = <0xe6e30000 0x8>;
        clocks = <&cpg CPG_MOD 523>;
        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
        resets = <&cpg 523>;
        #pwm-cells = <2>;
        pinctrl-0 = <&pwm0_pins>;
        pinctrl-names = "default";
    };