code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * See craneboard.org for more details
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 */
/dts-v1/;

#include "am3517.dtsi"

/ {
	model = "TI AM3517 CraneBoard (TMDSEVM3517)";
	compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;	/* 256 MB */
	};

	vbat: fixedregulator {
		compatible = "regulator-fixed";
		regulator-name = "vbat";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
	};
};

&davinci_emac {
	status = "okay";
};

&davinci_mdio {
	status = "okay";
};

&i2c1 {
	clock-frequency = <2600000>;

	tps: tps@2d {
		reg = <0x2d>;
	};
};

&i2c2 {
	clock-frequency = <400000>;
	/* goes to expansion connector */
	status = "disabled";
};

&i2c3 {
	clock-frequency = <400000>;
	/* goes to expansion connector */
	status = "disabled";
};

&mmc1 {
	vmmc-supply = <&vdd2_reg>;
	bus-width = <8>;
};

&mmc2 {
	/* goes to expansion connector */
	status = "disabled";
};

&mmc3 {
	/* goes to expansion connector */
	status = "disabled";
};

#include "tps65910.dtsi"

&omap3_pmx_core {
	tps_pins: pinmux_tps_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */
		>;
	};
};

&tps {
	pinctrl-names = "default";
	pinctrl-0 = <&tps_pins>;

	interrupts = <7>; /* SYS_NIRQ cascaded to intc */
	interrupt-parent = <&intc>;

	ti,en-ck32k-xtal;

	vcc1-supply = <&vbat>;
	vcc2-supply = <&vbat>;
	vcc3-supply = <&vbat>;
	vcc4-supply = <&vbat>;
	vcc5-supply = <&vbat>;
	vcc6-supply = <&vbat>;
	vcc7-supply = <&vbat>;
	vccio-supply = <&vbat>;

	regulators {
		vrtc_reg: regulator@0 {
			regulator-always-on;
		};

		vio_reg: regulator@1 {
			regulator-always-on;
		};

		/*
		 * Unused:
		 * VDIG1=2.7V,300mA max
		 * VDIG2=1.8V,300mA max
		 */

		vpll_reg: regulator@7 {
			/* VDDS_DPLL_1V8 */
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
		};

		vaux1_reg: regulator@9 {
			/* VDDS_SRAM_1V8 */
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
		};

		vaux2_reg: regulator@10 {
			/* VDDA1P8V_USBPHY */
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
		};

		/* VAUX33 unused */

		vdac_reg: regulator@8 {
			/* VDDA_DAC_1V8 */
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
		};

		vmmc_reg: regulator@12 {
			/* VDDA3P3V_USBPHY */
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		vdd1_reg: regulator@2 {
			/* VDD_CORE */
			regulator-name = "vdd_core";
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd2_reg: regulator@3 {
			/* VDDSHV_3V3 */
			regulator-name = "vdd_shv";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		/* VDD3 unused */
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2018 Logic PD, Inc - https://www.logicpd.com/
 */

#include <dt-bindings/input/input.h>

/ {
	codec1 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "tlv320aic23-hifi";

		simple-audio-card,widgets =
			"Microphone", "Mic In",
			"Line", "Line In",
			"Line", "Line Out";

		simple-audio-card,routing =
			"Line Out", "LOUT",
			"Line Out", "ROUT",
			"LLINEIN", "Line In",
			"RLINEIN", "Line In",
			"MICIN", "Mic In";

		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&sound_master>;
		simple-audio-card,frame-master = <&sound_master>;

		simple-audio-card,cpu {
			sound-dai = <&mcbsp1>;
		};

		sound_master: simple-audio-card,codec {
			sound-dai = <&tlv320aic23_1>;
			system-clock-frequency = <12000000>;
		};
	};

	codec2 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "tlv320aic23-hifi";

		simple-audio-card,widgets =
			"Microphone", "Mic In",
			"Line", "Line In",
			"Line", "Line Out";

		simple-audio-card,routing =
			"Line Out", "LOUT",
			"Line Out", "ROUT",
			"LLINEIN", "Line In",
			"RLINEIN", "Line In",
			"MICIN", "Mic In";

		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&sound_master2>;
		simple-audio-card,frame-master = <&sound_master2>;

		simple-audio-card,cpu {
			sound-dai = <&mcbsp2>;
		};

		sound_master2: simple-audio-card,codec {
			sound-dai = <&tlv320aic23_2>;
			system-clock-frequency = <12000000>;
		};
	};

	expander-keys {
		compatible = "gpio-keys-polled";
		poll-interval = <100>;

		key-record {
			label = "Record";
			/* linux,code = <BTN_0>; */
			gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>;
		};

		key-play {
			label = "Play";
			linux,code = <KEY_PLAY>;
			gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>;
		};

		key-stop {
			label = "Stop";
			linux,code = <KEY_STOP>;
			gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>;
		};

		key-fwd {
			label = "FWD";
			linux,code = <KEY_FASTFORWARD>;
			gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>;
		};

		key-rwd {
			label = "RWD";
			linux,code = <KEY_REWIND>;
			gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>;
		};

		key-shift {
			label = "Shift";
			linux,code = <KEY_LEFTSHIFT>;
			gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>;
		};

		key-mode {
			label = "Mode";
			linux,code = <BTN_MODE>;
			gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>;
		};

		key-menu {
			label = "Menu";
			linux,code = <KEY_MENU>;
			gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>;
		};

		key-up {
			label = "Up";
			linux,code = <KEY_UP>;
			gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>;
		};

		key-down {
			label = "Down";
			linux,code = <KEY_DOWN>;
			gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>;
		};
	};
};

&i2c2 {
	/* Audio codecs */
	tlv320aic23_1: codec@1a {
		compatible = "ti,tlv320aic23";
		reg = <0x1a>;
		#sound-dai-cells = <0>;
		status = "okay";
	};

	tlv320aic23_2: codec@1b {
		compatible = "ti,tlv320aic23";
		reg = <0x1b>;
		#sound-dai-cells = <0>;
		status = "okay";
	};
};

&i2c3 {
	/* Audio codecs */
	tlv320aic23_3: codec@1a {
		compatible = "ti,tlv320aic23";
		reg = <0x1a>;
		#sound-dai-cells = <0>;
		status = "okay";
	};

	/* GPIO Expanders */
	tca6416_2: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&vdd_io_reg>;
	};

	tca6416_3: gpio@21 {
		compatible = "ti,tca6416";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&vdd_io_reg>;
	};

	/* TVP5146 Analog Video decoder input */
	tvp5146@5c {
		compatible = "ti,tvp5146m2";
		reg = <0x5c>;
	};
};

&mcbsp1 {
	status = "okay";
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&mcbsp1_pins>;
};

&mcbsp2 {
	status = "okay";
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&mcbsp2_pins>;
};

&omap3_pmx_core {
	mcbsp1_pins: pinmux_mcbsp1_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0)	/* mcbsp1_dx.mcbsp1_dx */
			OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0)	/* mcbsp1_dx.mcbsp1_dr */
			OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0)	/* mcbsp_clks.mcbsp1_fsx */
			OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0)	/* mcbsp1_clkx.mcbsp1_clkx */
		>;
	};

	mcbsp2_pins: pinmux_mcbsp2_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)	/* mcbsp2_fsx.mcbsp2_fsx */
			OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)	/* mcbsp2_clkx.mcbsp2_clkx */
			OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)	/* mcbsp2_dr.mcbsp2.dr */
			OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)	/* mcbsp2_dx.mcbsp2_dx */
		>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
 */
/dts-v1/;

#include "am3517.dtsi"
#include "am3517-som.dtsi"
#include "am3517-evm-ui.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)";
	compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3";

	aliases {
		display0 = &lcd0;
	};

	chosen {
		stdout-path = &uart3;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>; /* 256 MB */
	};

	vmmc_fixed: vmmc {
		compatible = "regulator-fixed";
		regulator-name = "vmmc_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	gpio-keys {
		compatible = "gpio-keys-polled";
		poll-interval = <100>;

		button-user {
			label = "User Push Button";
			linux,code = <BTN_0>;
			gpios = <&tca6416 5 GPIO_ACTIVE_LOW>;
		};

		switch-1 {
			label = "User Switch 1";
			linux,code = <BTN_1>;
			gpios = <&tca6416 8 GPIO_ACTIVE_LOW>;
		};

		switch-2 {
			label = "User Switch 2";
			linux,code = <BTN_2>;
			gpios = <&tca6416 9 GPIO_ACTIVE_LOW>;
		};

		switch-3 {
			label = "User Switch 3";
			linux,code = <BTN_3>;
			gpios = <&tca6416 10 GPIO_ACTIVE_LOW>;
		};

		switch-4 {
			label = "User Switch 4";
			linux,code = <BTN_4>;
			gpios = <&tca6416 11 GPIO_ACTIVE_LOW>;
		};

		switch-5 {
			label = "User Switch 5";
			linux,code = <BTN_5>;
			gpios = <&tca6416 12 GPIO_ACTIVE_LOW>;
		};

		switch-6 {
			label = "User Switch 6";
			linux,code = <BTN_6>;
			gpios = <&tca6416 13 GPIO_ACTIVE_LOW>;
		};

		switch-7 {
			label = "User Switch 7";
			linux,code = <BTN_7>;
			gpios = <&tca6416 14 GPIO_ACTIVE_LOW>;
		};

		switch-8 {
			label = "User Switch 8";
			linux,code = <BTN_8>;
			gpios = <&tca6416 15 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		pinctrl-names = "default";
		pinctrl-0 = <&leds_pins>;

		user_led_1 {
			label = "am3517evm:green:user_led_1";
			gpios = <&tca6416 7 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};

		user_led_2 {
			label = "am3517evm:green:user_led_2";
			gpios = <&tca6416 6 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};

		user_led_3 {
			label = "am3517evm:green:user_led_3";
			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "mmc0"; /* SD/MMC card activity */
		};

		user_led_4 {
			label = "am3517evm:green:user_led_4";
			gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	lcd0: display@0 {
		/* This isn't the exact LCD, but the timings meet spec */
		/* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */
		compatible = "newhaven,nhd-4.3-480272ef-atxl";
		label = "15";
		backlight = <&bl>;
		enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;	/* gpio176, lcd INI */
		vcc-supply = <&vdd_io_reg>;

		port {
			lcd_in: endpoint {
				remote-endpoint = <&dpi_out>;
			};
		};
	};

	bl: backlight {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		power-supply = <&vdd_io_reg>;
		pinctrl-0 = <&backlight_pins>;
		pwms = <&pwm11 0 5000000 0>;
		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
		default-brightness-level = <7>;
		enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */
	};

	pwm11: pwm-11 {
		compatible = "ti,omap-dmtimer-pwm";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm_pins>;
		ti,timers = <&timer11>;
		#pwm-cells = <3>;
		ti,clock-source = <0x01>;
	};

	/* HS USB Host PHY on PORT 1 */
	hsusb1_phy: hsusb1_phy {
		pinctrl-names = "default";
		pinctrl-0 = <&hsusb1_rst_pins>;
		compatible = "usb-nop-xceiv";
		reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */
		#phy-cells = <0>;
	};
};

&davinci_emac {
	pinctrl-names = "default";
	pinctrl-0 = <&ethernet_pins>;
	status = "okay";
};

&davinci_mdio {
	status = "okay";
};

&dss {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&dss_dpi_pins>;

	vdds_dsi-supply = <&vdd_io_reg>;
	vdda_video-supply = <&vdd_io_reg>;

	port {
		dpi_out: endpoint {
			remote-endpoint = <&lcd_in>;
			data-lines = <16>;
		};
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	clock-frequency = <400000>;
	/* User DIP swithes [1:8] / User LEDS [1:2] */
	tca6416: gpio@21 {
		compatible = "ti,tca6416";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&vdd_io_reg>;
	};
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;
	clock-frequency = <400000>;
};

&mmc1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	vmmc-supply = <&vmmc_fixed>;
	bus-width = <4>;
	wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
	cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio_127 */
};

&mmc3 {
	status = "disabled";
};

&usbhshost {
	pinctrl-names = "default";
	pinctrl-0 = <&hsusb1_pins>;
	port1-mode = "ehci-phy";
};

&usbhsehci {
	phys = <&hsusb1_phy>;
};

&omap3_pmx_core {

	ethernet_pins: pinmux_ethernet_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */
			OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */
			OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd0 */
			OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd1 */
			OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_crs_dv */
			OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_rxer */
			OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd0 */
			OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd1 */
			OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN |MUX_MODE0) /* rmii_txen */
			OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */
		>;
	};

	i2c2_pins: pinmux_i2c2_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT_PULLUP | MUX_MODE0)  /* i2c2_scl */
			OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE0)  /* i2c2_sda */
		>;
	};

	i2c3_pins: pinmux_i2c3_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0)  /* i2c3_scl */
			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0)  /* i2c3_sda */
		>;
	};

	leds_pins: pinmux_leds_pins {
		pinctrl-single,pins = <
			OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4)	/* jtag_emu0.gpio_11 */
			OMAP3_WKUP_IOPAD(0x2a26, PIN_OUTPUT_PULLUP | MUX_MODE4)	/* jtag_emu1.gpio_31 */
		>;
	};

	mmc1_pins: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_clk.sdmmc1_clk */
			OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_cmd.sdmmc1_cmd */
			OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat0.sdmmc1_dat0 */
			OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat1.sdmmc1_dat1 */
			OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat2.sdmmc1_dat2 */
			OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat3.sdmmc1_dat3 */
			OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat4.gpio_126 */
			OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat5.gpio_127 */
		>;
	};

	pwm_pins: pinmux_pwm_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21dc, PIN_OUTPUT | MUX_MODE1)       /* mcspi2_cs0.gpt11_pwm */
		>;
	};

	backlight_pins: pinmux_backlight_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21de, PIN_OUTPUT | MUX_MODE4)       /* mcspi2_cs1.gpio_182 */
		>;
	};

	dss_dpi_pins: pinmux_dss_dpi_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21d2, PIN_OUTPUT | MUX_MODE4)       /* mcspi1_cs2.gpio_176 */
			OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)       /* dss_pclk.dss_pclk */
			OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)       /* dss_hsync.dss_hsync */
			OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)       /* dss_vsync.dss_vsync */
			OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0)       /* dss_acbias.dss_acbias */
			OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0)       /* dss_data0.dss_data0 */
			OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0)       /* dss_data1.dss_data1 */
			OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0)       /* dss_data2.dss_data2 */
			OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0)       /* dss_data3.dss_data3 */
			OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0)       /* dss_data4.dss_data4 */
			OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0)       /* dss_data5.dss_data5 */
			OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0)       /* dss_data6.dss_data6 */
			OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0)       /* dss_data7.dss_data7 */
			OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0)       /* dss_data8.dss_data8 */
			OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0)       /* dss_data9.dss_data9 */
			OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0)       /* dss_data10.dss_data10 */
			OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0)       /* dss_data11.dss_data11 */
			OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0)       /* dss_data12.dss_data12 */
			OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0)       /* dss_data13.dss_data13 */
			OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0)       /* dss_data14.dss_data14 */
			OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0)       /* dss_data15.dss_data15 */
		>;
	};

	hsusb1_rst_pins: pinmux_hsusb1_rst_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4)	/* gpmc_ncs6.gpio_57 */
		>;
	};
};

&omap3_pmx_core2 {

	hsusb1_pins: pinmux_hsusb1_pins {
		pinctrl-single,pins = <
			OMAP3430_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3)	/* etk_clk.hsusb1_stp */
			OMAP3430_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3)	/* etk_ctl.hsusb1_clk */
			OMAP3430_CORE2_IOPAD(0x25ec, PIN_INPUT | MUX_MODE3)	/* etk_d8.hsusb1_dir */
			OMAP3430_CORE2_IOPAD(0x25ee, PIN_INPUT | MUX_MODE3)	/* etk_d9.hsusb1_nxt */
			OMAP3430_CORE2_IOPAD(0x25dc, PIN_INPUT | MUX_MODE3)	/* etk_d0.hsusb1_data0 */
			OMAP3430_CORE2_IOPAD(0x25de, PIN_INPUT | MUX_MODE3)	/* etk_d1.hsusb1_data1 */
			OMAP3430_CORE2_IOPAD(0x25e0, PIN_INPUT | MUX_MODE3)	/* etk_d2.hsusb1_data2 */
			OMAP3430_CORE2_IOPAD(0x25ea, PIN_INPUT | MUX_MODE3)	/* etk_d7.hsusb1_data3 */
			OMAP3430_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE3)	/* etk_d4.hsusb1_data4 */
			OMAP3430_CORE2_IOPAD(0x25e6, PIN_INPUT | MUX_MODE3)	/* etk_d5.hsusb1_data5 */
			OMAP3430_CORE2_IOPAD(0x25e8, PIN_INPUT | MUX_MODE3)	/* etk_d6.hsusb1_data6 */
			OMAP3430_CORE2_IOPAD(0x25e2, PIN_INPUT | MUX_MODE3)	/* etk_d3.hsusb1_data7 */
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2016 Derald D. Woods <woods.technical@gmail.com>
 *
 * Based on am3517-evm.dts
 */

/ {
	cpus {
		cpu@0 {
			cpu0-supply = <&vdd_core_reg>;
		};
	};

	wl12xx_buffer: wl12xx_buf {
		compatible = "regulator-fixed";
		regulator-name = "wl1271_buf";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		pinctrl-names = "default";
		pinctrl-0 = <&wl12xx_buffer_pins>;
		gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */
		regulator-always-on;
		vin-supply = <&vdd_1v8_reg>;
	};

	wl12xx_vmmc2: wl12xx_vmmc2 {
		compatible = "regulator-fixed";
		regulator-name = "vwl1271";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		pinctrl-names = "default";
		pinctrl-0 = <&wl12xx_wkup_pins>;
		gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */
		startup-delay-us = <70000>;
		enable-active-high;
		regulator-always-on;
		vin-supply = <&wl12xx_buffer>;
	};
};

&gpmc {
	ranges = <0 0 0x30000000 0x1000000>;	/* CS0: 16MB for NAND */

	nand@0,0 {
		compatible = "ti,omap2-nand";
		linux,mtd-name = "micron,mt29f4g16abchch";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		nand-bus-width = <16>;
		ti,nand-ecc-opt = "bch8";
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <44>;
		gpmc,cs-wr-off-ns = <44>;
		gpmc,adv-on-ns = <6>;
		gpmc,adv-rd-off-ns = <34>;
		gpmc,adv-wr-off-ns = <44>;
		gpmc,we-off-ns = <40>;
		gpmc,oe-off-ns = <54>;
		gpmc,access-ns = <64>;
		gpmc,rd-cycle-ns = <82>;
		gpmc,wr-cycle-ns = <82>;
		gpmc,wr-access-ns = <40>;
		gpmc,wr-data-mux-bus-ns = <0>;
		gpmc,device-width = <2>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	clock-frequency = <400000>;

	s35390a: s35390a@30 {
		compatible = "sii,s35390a";
		reg = <0x30>;

		pinctrl-names = "default";
		pinctrl-0 = <&rtc_pins>;
		interrupts-extended = <&gpio2 23 IRQ_TYPE_EDGE_FALLING>; /* gpio_55 */
	};

	tps: tps65023@48 {
		compatible = "ti,tps65023";
		reg = <0x48>;

		regulators {
			vdd_core_reg: VDCDC1 {
				regulator-name = "vdd_core";
				regulator-always-on;
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
			};

			vdd_io_reg: VDCDC2 {
				regulator-name = "vdd_io";
				regulator-always-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
			};

			vdd_1v8_reg: VDCDC3 {
				regulator-name = "vdd_1v8";
				regulator-always-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};

			vdd_usb18_reg: LDO1 {
				regulator-name = "vdd_usb18";
				regulator-always-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};

			vdd_usb33_reg: LDO2 {
				regulator-name = "vdd_usb33";
				regulator-always-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};

	touchscreen: tsc2004@4b {
		compatible = "ti,tsc2004";
		reg = <0x4b>;

		vio-supply = <&vdd_io_reg>;

		pinctrl-names = "default";
		pinctrl-0 = <&tsc2004_pins>;
		interrupts-extended = <&gpio3 1 IRQ_TYPE_EDGE_RISING>; /* gpio_65 */

		touchscreen-fuzz-x = <4>;
		touchscreen-fuzz-y = <7>;
		touchscreen-fuzz-pressure = <2>;
		touchscreen-size-x = <480>;
		touchscreen-size-y = <272>;
		touchscreen-max-pressure = <2048>;

		ti,x-plate-ohms = <280>;
		ti,esd-recovery-timeout-ms = <8000>;
	};
};

&mmc2 {
	interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>;

	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins>;
	vmmc-supply = <&wl12xx_vmmc2>;
	non-removable;
	bus-width = <4>;
	cap-power-off-card;
	#address-cells = <1>;
	#size-cells = <0>;
	wlcore: wlcore@2 {
		compatible = "ti,wl1271";
		reg = <2>;
		interrupt-parent = <&gpio6>;
		interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */
		ref-clock-frequency = <26000000>;
		tcxo-clock-frequency = <26000000>;
	};
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;

	bluetooth {
		compatible = "ti,wl1271-st";
		enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */
		max-speed = <3000000>;
	};
};

&omap3_pmx_core {

	i2c1_pins: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0)  /* i2c1_scl */
			OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0)  /* i2c1_sda */
		>;
	};

	wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4)  /* mmc1_dat7.gpio_129 */
		>;
	};

	mmc2_pins: pinmux_mmc2_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)  /* mmc2_clk.mmc2_clk */
			OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)  /* mmc2_cmd.mmc2_cmd */
			OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)  /* mmc2_dat0.mmc2_dat0 */
			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)  /* mmc2_dat1.mmc2_dat1 */
			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)  /* mmc2_dat2.mmc2_dat2 */
			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)  /* mmc2_dat3.mmc2_dat3 */
			OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */
			OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */
			OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */
			OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */
			OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4)	/* hdq_sio.gpio_170 */
		>;
	};

	rtc_pins: pinmux_rtc_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */
		>;
	};

	tsc2004_pins: pinmux_tsc2004_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */
		>;
	};

	uart2_pins: pinmux_uart2_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0)		/* uart2_cts */
			OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* uart2_rts */
			OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)		/* uart2_tx */
			OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)		/* uart2_rx */
			OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0)		/* gpio_56 */
		>;
	};
};

&omap3_pmx_wkup {

	wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins {
		pinctrl-single,pins = <
			OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4)	/* sys_boot1.gpio_3 */
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for am3517 SoC
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "omap3.dtsi"

/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */
/delete-node/ &aes1_target;
/delete-node/ &aes2_target;

/ {
	aliases {
		serial3 = &uart4;
		can = &hecc;
	};

	cpus {
		cpu: cpu@0 {
			/* Based on OMAP3630 variants OPP50 and OPP100 */
			operating-points-v2 = <&cpu0_opp_table>;

			clock-latency = <300000>; /* From legacy driver */
		};
	};

	cpu0_opp_table: opp-table {
		compatible = "operating-points-v2-ti-cpu";
		syscon = <&scm_conf>;
		/*
		 * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx
		 * appear to operate at 300MHz as well. Since AM3517 only
		 * lists one operating voltage, it will remain fixed at 1.2V
		 */
		opp50-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <1200000>;
			opp-supported-hw = <0xffffffff 0xffffffff>;
			opp-suspend;
		};

		opp100-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1200000>;
			opp-supported-hw = <0xffffffff 0xffffffff>;
		};
	};

	ocp@68000000 {
		target-module@5c040000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x5c040400 0x4>,
			      <0x5c040404 0x4>,
			      <0x5c040408 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			clocks = <&hsotgusb_ick_am35xx>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x5c040000 0x1000>;

			am35x_otg_hs: am35x_otg_hs@0 {
				compatible = "ti,omap3-musb";
				status = "disabled";
				reg = <0 0x1000>;
				interrupts = <71>;
				interrupt-names = "mc";
			};
		};

		davinci_emac: ethernet@5c000000 {
			compatible = "ti,am3517-emac";
			ti,hwmods = "davinci_emac";
			status = "disabled";
			reg = <0x5c000000 0x30000>;
			interrupts = <67 68 69 70>;
			syscon = <&scm_conf>;
			ti,davinci-ctrl-reg-offset = <0x10000>;
			ti,davinci-ctrl-mod-reg-offset = <0>;
			ti,davinci-ctrl-ram-offset = <0x20000>;
			ti,davinci-ctrl-ram-size = <0x2000>;
			ti,davinci-rmii-en = /bits/ 8 <1>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			clocks = <&emac_ick>;
			clock-names = "ick";
		};

		davinci_mdio: mdio@5c030000 {
			compatible = "ti,davinci_mdio";
			ti,hwmods = "davinci_mdio";
			status = "disabled";
			reg = <0x5c030000 0x1000>;
			bus_freq = <1000000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&emac_fck>;
			clock-names = "fck";
		};

		uart4: serial@4809e000 {
			compatible = "ti,omap3-uart";
			ti,hwmods = "uart4";
			status = "disabled";
			reg = <0x4809e000 0x400>;
			interrupts = <84>;
			dmas = <&sdma 55 &sdma 54>;
			dma-names = "tx", "rx";
			clock-frequency = <48000000>;
		};

		omap3_pmx_core2: pinmux@480025d8 {
			compatible = "ti,omap3-padconf", "pinctrl-single";
			reg = <0x480025d8 0x24>;
			#address-cells = <1>;
			#size-cells = <0>;
			#pinctrl-cells = <1>;
			#interrupt-cells = <1>;
			interrupt-controller;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0xff1f>;
		};

		hecc: can@5c050000 {
			compatible = "ti,am3517-hecc";
			status = "disabled";
			reg = <0x5c050000 0x80>,
			      <0x5c053000 0x180>,
			      <0x5c052000 0x200>;
			reg-names = "hecc", "hecc-ram", "mbx";
			interrupts = <24>;
			clocks = <&hecc_ck>;
		};

		/*
		 * On am3517 the OCP registers do not seem to be accessible
		 * similar to the omap34xx. Maybe SGX is permanently set to
		 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
		 * write-only at 0x50000e10. We detect SGX based on the SGX
		 * revision register instead of the unreadable OCP revision
		 * register.
		 */
		sgx_module: target-module@50000000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x50000014 0x4>;
			reg-names = "rev";
			clocks = <&sgx_fck>, <&sgx_ick>;
			clock-names = "fck", "ick";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x50000000 0x4000>;

			/*
			 * Closed source PowerVR driver, no child device
			 * binding or driver in mainline
			 */
		};
	};
};

/* Not currently working, probably needs at least different clocks */
&rng_target {
	status = "disabled";
	/delete-property/ clocks;
};

/* Table Table 5-79 of the TRM shows 480ab000 is reserved */
&usb_otg_target {
	status = "disabled";
};

&iva {
	status = "disabled";
};

&mailbox {
	status = "disabled";
};

&mmu_isp {
	status = "disabled";
};

#include "am35xx-clocks.dtsi"
#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

/* Preferred always-on timer for clocksource */
&timer1_target {
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&gpt1_fck>;
		assigned-clock-parents = <&sys_ck>;
	};
};

/* Preferred timer for clockevent */
&timer2_target {
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&gpt2_fck>;
		assigned-clock-parents = <&sys_ck>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2011 Ilya Yanok, EmCraft Systems
 */
/dts-v1/;

#include "omap34xx.dtsi"

/ {
	model = "TeeJet Mt.Ventoux";
	compatible = "teejet,mt_ventoux", "ti,am3517", "ti,omap3";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>; /* 256 MB */
	};

	/* AM35xx doesn't have IVA */
	soc {
		iva {
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP3 clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 */
&scm_clocks {
	emac_ick: emac_ick@32c {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&ipss_ick>;
		reg = <0x032c>;
		ti,bit-shift = <1>;
	};

	emac_fck: emac_fck@32c {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&rmii_ck>;
		reg = <0x032c>;
		ti,bit-shift = <9>;
	};

	vpfe_ick: vpfe_ick@32c {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&ipss_ick>;
		reg = <0x032c>;
		ti,bit-shift = <2>;
	};

	vpfe_fck: vpfe_fck@32c {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&pclk_ck>;
		reg = <0x032c>;
		ti,bit-shift = <10>;
	};

	hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&ipss_ick>;
		reg = <0x032c>;
		ti,bit-shift = <0>;
	};

	hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_ck>;
		reg = <0x032c>;
		ti,bit-shift = <8>;
	};

	hecc_ck: hecc_ck@32c {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&sys_ck>;
		reg = <0x032c>;
		ti,bit-shift = <3>;
	};
};
&cm_clocks {
	clock@a10 {
		compatible = "ti,clksel";
		reg = <0xa10>;
		#clock-cells = <2>;
		#address-cells = <0>;

		ipss_ick: clock-ipss-ick {
			#clock-cells = <0>;
			compatible = "ti,am35xx-interface-clock";
			clock-output-names = "ipss_ick";
			clocks = <&core_l3_ick>;
			ti,bit-shift = <4>;
		};

		uart4_ick_am35xx: clock-uart4-ick-am35xx {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "uart4_ick_am35xx";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <23>;
		};
	};

	rmii_ck: rmii_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
	};

	pclk_ck: pclk_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <27000000>;
	};

	clock@a00 {
		compatible = "ti,clksel";
		reg = <0xa00>;
		#clock-cells = <2>;
		#address-cells = <0>;

		uart4_fck_am35xx: clock-uart4-fck-am35xx {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "uart4_fck_am35xx";
			clocks = <&core_48m_fck>;
			ti,bit-shift = <23>;
		};
	};
};

&cm_clockdomains {
	core_l3_clkdm: core_l3_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
			 <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
			 <&hecc_ck>;
	};

	core_l4_clkdm: core_l4_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
			 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
			 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
			 <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
 */

#include "omap36xx.dtsi"

&iva {
	status = "disabled";
};

&sgx_module {
	status = "disabled";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
 */

#include "omap36xx.dtsi"

&iva {
	status = "disabled";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device tree for Winterland IceBoard
 *
 * https://mcgillcosmology.com
 * https://threespeedlogic.com
 *
 * This is an ARM + FPGA instrumentation board used at telescopes in
 * Antarctica (the South Pole Telescope), Chile (POLARBEAR), and at the DRAO
 * observatory in British Columbia (CHIME).
 *
 * Copyright (c) 2019 Three-Speed Logic, Inc. <gsmecher@threespeedlogic.com>
 */

/dts-v1/;

#include "dm814x.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "Winterland IceBoard";
	compatible = "ti,dm8148", "ti,dm814";

	chosen {
		stdout-path = "serial1:115200n8";
		bootargs = "earlycon";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;	/* 1 GB */
	};

	vmmcsd_fixed: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "vmmcsd_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};
};

/* The MAC provides internal delay for the transmit path ONLY, which is enabled
 * provided no -id/-txid/-rxid suffix is provided to "phy-mode".
 *
 * The receive path is delayed at the PHY. The recommended register settings
 * are 0xf0 for the control bits, and 0x7777 for the data bits. However, the
 * conversion code in the kernel lies: the PHY's registers are 120 ps per tap,
 * and the kernel assumes 200 ps per tap. So we have fudged the numbers here to
 * obtain the correct register settings.
 */
&mac { dual_emac = <1>; };
&cpsw_emac0 {
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
	phy-handle = <&ethphy1>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <2>;
};

&davinci_mdio {
	ethphy0: ethernet-phy@0 {
		reg = <0x2>;

		rxc-skew-ps = <3000>;
		rxdv-skew-ps = <0>;

		rxd3-skew-ps = <0>;
		rxd2-skew-ps = <0>;
		rxd1-skew-ps = <0>;
		rxd0-skew-ps = <0>;

		phy-reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
	};

	ethphy1: ethernet-phy@1 {
		reg = <0x1>;

		rxc-skew-ps = <3000>;
		rxdv-skew-ps = <0>;

		rxd3-skew-ps = <0>;
		rxd2-skew-ps = <0>;
		rxd1-skew-ps = <0>;
		rxd0-skew-ps = <0>;

		phy-reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
	};
};

&mmc1 { status = "disabled"; };
&mmc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins>;
	vmmc-supply = <&vmmcsd_fixed>;
	bus-width = <4>;
};
&mmc3 { status = "disabled"; };

&i2c1 {
	/* Most I2C activity happens through this port, with the sole exception
	 * of the backplane. Since there are multiply assigned addresses, the
	 * "i2c-mux-idle-disconnect" is important.
	 */

	pca9548@70 {
		compatible = "nxp,pca9548";
		reg = <0x70>;
		#address-cells = <1>;
		#size-cells = <0>;
		i2c-mux-idle-disconnect;

		i2c@0 {
			/* FMC A */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		i2c@1 {
			/* FMC B */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};

		i2c@2 {
			/* QSFP A */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};

		i2c@3 {
			/* QSFP B */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};

		i2c@4 {
			/* SFP */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
		};

		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;

			ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; };
			ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; };
			ina230@42 { compatible = "ti,ina230"; reg = <0x42>; shunt-resistor = <5000>; };

			ina230@44 { compatible = "ti,ina230"; reg = <0x44>; shunt-resistor = <5000>; };
			ina230@45 { compatible = "ti,ina230"; reg = <0x45>; shunt-resistor = <5000>; };
			ina230@46 { compatible = "ti,ina230"; reg = <0x46>; shunt-resistor = <5000>; };

			ina230@47 { compatible = "ti,ina230"; reg = <0x47>; shunt-resistor = <5500>; };
			ina230@48 { compatible = "ti,ina230"; reg = <0x48>; shunt-resistor = <2360>; };
			ina230@49 { compatible = "ti,ina230"; reg = <0x49>; shunt-resistor = <2360>; };
			ina230@43 { compatible = "ti,ina230"; reg = <0x43>; shunt-resistor = <2360>; };
			ina230@4b { compatible = "ti,ina230"; reg = <0x4b>; shunt-resistor = <5500>; };
			ina230@4c { compatible = "ti,ina230"; reg = <0x4c>; shunt-resistor = <2360>; };
			ina230@4d { compatible = "ti,ina230"; reg = <0x4d>; shunt-resistor = <770>; };
			ina230@4e { compatible = "ti,ina230"; reg = <0x4e>; shunt-resistor = <770>; };
			ina230@4f { compatible = "ti,ina230"; reg = <0x4f>; shunt-resistor = <770>; };
		};

		i2c@6 {
			/* Backplane */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
		};

		i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <7>;

			u41: pca9575@20 {
				compatible = "nxp,pca9575";
				reg = <0x20>;
				gpio-controller;
				#gpio-cells = <2>;

				gpio-line-names =
					"FMCA_EN_12V0", "FMCA_EN_3V3", "FMCA_EN_VADJ", "FMCA_PG_M2C",
					"FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS",
					"FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C",
					"FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL";
				reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
			};

			u42: pca9575@21 {
				compatible = "nxp,pca9575";
				reg = <0x21>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio-line-names =
					"QSFPA_ModPrsL", "QSFPA_IntL", "QSFPA_ResetL", "QSFPA_ModSelL",
					"QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL",
					"SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1",
					"QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR";
				reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
			};

			u48: pca9575@22 {
				compatible = "nxp,pca9575";
				reg = <0x22>;
				gpio-controller;
				#gpio-cells = <2>;

				sw-gpios = <&u48 0 0>, <&u48 1 0>, <&u48 2 0>, <&u48 3 0>,
					<&u48 4 0>, <&u48 5 0>, <&u48 6 0>, <&u48 7 0>;
				led-gpios = <&u48 7 0>, <&u48 6 0>, <&u48 5 0>, <&u48 4 0>,
					<&u48 3 0>, <&u48 2 0>, <&u48 1 0>, <&u48 0 0>;

				gpio-line-names =
					"GP_SW1", "GP_SW2", "GP_SW3", "GP_SW4",
					"GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8",
					"GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5",
					"GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1";
				reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
			};

			u59: pca9575@23 {
				compatible = "nxp,pca9575";
				reg = <0x23>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio-line-names =
					"GP_LED9", "GP_LED10", "GP_LED11", "GP_LED12",
					"GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault",
					"BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3",
					"BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17";
				reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
			};

			tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; };
			tmp100@4a { compatible = "ti,tmp100"; reg = <0x4a>; };
			tmp100@4b { compatible = "ti,tmp100"; reg = <0x4b>; };
			tmp100@4c { compatible = "ti,tmp100"; reg = <0x4c>; };

			/* EEPROM bank and serial number are treated as separate devices */
			at24c01@57 { compatible = "atmel,24c01"; reg = <0x57>; };
			at24cs01@5f { compatible = "atmel,24cs01"; reg = <0x5f>; };
		};
	};
};

&i2c2 {
	pca9548@71 {
		compatible = "nxp,pca9548";
		reg = <0x71>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@6 {
			/* Backplane */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
			multi-master;

			/* All backplanes should have this -- it's how we know they're there. */
			at24c08@54 { compatible="atmel,24c08"; reg=<0x54>; };
			at24cs08@5c { compatible="atmel,24cs08"; reg=<0x5c>; };

			/* 16 slot backplane */
			tmp421@4d { compatible="ti,tmp421"; reg=<0x4d>; };
			tmp421@4e { compatible="ti,tmp421"; reg=<0x4e>; };
			ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <2360>; };
			amc6821@18 { compatible = "ti,amc6821"; reg = <0x18>; };

			/* Single slot backplane */
		};
	};
};

&pincntl {
	mmc2_pins: pinmux_mmc2_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x0800, PIN_INPUT | 0x1)	/* SD1_CLK */
			DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP | 0x1)	/* SD1_CMD */
			DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP | 0x1)	/* SD1_DAT[0] */
			DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP | 0x1)	/* SD1_DAT[1] */
			DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP | 0x1)	/* SD1_DAT[2] */
			DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP | 0x1)	/* SD1_DAT[3] */
			DM814X_IOPAD(0x0924, PIN_INPUT_PULLUP | 0x40)	/* SD1_POW */
			DM814X_IOPAD(0x0928, PIN_INPUT | 0x40)	/* SD1_SDWP */
			DM814X_IOPAD(0x093C, PIN_INPUT | 0x2)	/* SD1_SDCD */
			>;
	};

	usb0_pins: pinmux_usb0_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1)	/* USB0_DRVVBUS */
			>;
	};

	usb1_pins: pinmux_usb1_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x0834, PIN_OUTPUT | 0x80)	/* USB1_DRVVBUS */
			>;
	};

	gpio1_pins: pinmux_gpio1_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x081c, PIN_OUTPUT | 0x80)	/* PROGRAM_B */
			DM814X_IOPAD(0x0820, PIN_INPUT | 0x80)	/* INIT_B */
			DM814X_IOPAD(0x0824, PIN_INPUT | 0x80)	/* DONE */

			DM814X_IOPAD(0x0838, PIN_INPUT_PULLUP | 0x80) /* FMCA_TMS */
			DM814X_IOPAD(0x083c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TCK */
			DM814X_IOPAD(0x0898, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDO */
			DM814X_IOPAD(0x089c, PIN_INPUT_PULLUP | 0x80) /* FMCA_TDI */
			DM814X_IOPAD(0x08ac, PIN_INPUT_PULLUP | 0x80) /* FMCA_TRST */

			DM814X_IOPAD(0x08b0, PIN_INPUT_PULLUP | 0x80) /* FMCB_TMS */
			DM814X_IOPAD(0x0a88, PIN_INPUT_PULLUP | 0x80) /* FMCB_TCK */
			DM814X_IOPAD(0x0a8c, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDO */
			DM814X_IOPAD(0x08bc, PIN_INPUT_PULLUP | 0x80) /* FMCB_TDI */
			DM814X_IOPAD(0x0a94, PIN_INPUT_PULLUP | 0x80) /* FMCB_TRST */

			DM814X_IOPAD(0x08d4, PIN_INPUT_PULLUP | 0x80) /* FPGA_TMS */
			DM814X_IOPAD(0x0aa8, PIN_INPUT_PULLUP | 0x80) /* FPGA_TCK */
			DM814X_IOPAD(0x0adc, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDO */
			DM814X_IOPAD(0x0ab0, PIN_INPUT_PULLUP | 0x80) /* FPGA_TDI */
			>;
	};

	gpio2_pins: pinmux_gpio2_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x090c, PIN_INPUT_PULLUP | 0x80) /* PHY A IRQ */
			DM814X_IOPAD(0x0910, PIN_INPUT_PULLUP | 0x80) /* PHY A RESET */
			DM814X_IOPAD(0x08f4, PIN_INPUT_PULLUP | 0x80) /* PHY B IRQ */
			DM814X_IOPAD(0x08f8, PIN_INPUT_PULLUP | 0x80) /* PHY B RESET */

			//DM814X_IOPAD(0x0a14, PIN_INPUT_PULLUP | 0x80) /* ARM IRQ */
			//DM814X_IOPAD(0x0900, PIN_INPUT | 0x80) /* GPIO IRQ */
			DM814X_IOPAD(0x0a2c, PIN_INPUT_PULLUP | 0x80) /* GPIO RESET */
		>;
	};

	gpio4_pins: pinmux_gpio4_pins {
		pinctrl-single,pins = <
			/* The PLL doesn't react well to the SPI controller reset, so
			 * we force the CS lines to pull up as GPIOs until we're ready.
			 * See https://e2e.ti.com/support/processors/f/791/t/276011?Linux-support-for-AM3874-DM8148-in-Arago-linux-omap3
			 */
			DM814X_IOPAD(0x0b3c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO0 */
			DM814X_IOPAD(0x0b40, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO1 */
			DM814X_IOPAD(0x0b44, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO2 */
			DM814X_IOPAD(0x0b48, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO3 */
			DM814X_IOPAD(0x0b4c, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO4 */
			DM814X_IOPAD(0x0b50, PIN_INPUT_PULLUP | 0x80) /* BP_ARM_GPIO5 */
		>;
	};

	spi2_pins: pinmux_spi2_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */
			DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */
		>;
	};

	spi4_pins: pinmux_spi4_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x0a7c, 0x20)
			DM814X_IOPAD(0x0b74, 0x20)
			DM814X_IOPAD(0x0b78, PIN_OUTPUT | 0x20)
			DM814X_IOPAD(0x0b7c, PIN_OUTPUT_PULLDOWN | 0x20)
			DM814X_IOPAD(0x0b80, PIN_INPUT | 0x20)
		>;
	};
};

&gpio1 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio1_pins>;
	gpio-line-names =
		"", "PROGRAM_B", "INIT_B", "DONE",			/* 0-3 */
		"", "", "", "",						/* 4-7 */
		"FMCA_TMS", "FMCA_TCK", "FMCA_TDO", "FMCA_TDI",		/* 8-11 */
		"", "", "", "FMCA_TRST",				/* 12-15 */
		"FMCB_TMS", "FMCB_TCK", "FMCB_TDO", "FMCB_TDI",		/* 16-19 */
		"FMCB_TRST", "", "", "",				/* 20-23 */
		"FPGA_TMS", "FPGA_TCK", "FPGA_TDO", "FPGA_TDI",		/* 24-27 */
		"", "", "", "";						/* 28-31 */
};

&gpio2 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio2_pins>;
	gpio-line-names =
		"PHYA_IRQ_N", "PHYA_RESET_N", "", "",			/* 0-3 */
		"", "", "", "PHYB_IRQ_N",				/* 4-7 */
		"PHYB_RESET_N", "ARM_IRQ", "GPIO_IRQ", "";		/* 8-11 */
};

&gpio3 {
	pinctrl-names = "default";
	/*pinctrl-0 = <&gpio3_pins>;*/
	gpio-line-names =
		"", "", "ARMClkSel0", "",				/* 0-3 */
		"EnFPGARef", "", "", "ARMClkSel1";			/* 4-7 */
};

&gpio4 {
	pinctrl-names = "default";
	pinctrl-0 = <&gpio4_pins>;
	gpio-line-names =
		"BP_ARM_GPIO0", "BP_ARM_GPIO1", "BP_ARM_GPIO2", "BP_ARM_GPIO3",
		"BP_ARM_GPIO4", "BP_ARM_GPIO5";
};

&usb0 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb0_pins>;
	dr_mode = "host";
};

&usb1 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb1_pins>;
	dr_mode = "host";
};

&mcspi1 {
	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <40000000>;

		fsbl@0 {
			/* 256 kB */
			label = "U-Boot-min";
			reg = <0 0x40000>;
		};
		ssbl@1 {
			/* 512 kB */
			label = "U-Boot";
			reg = <0x40000 0x80000>;
		};
		bootenv@2 {
			/* 256 kB */
			label = "U-Boot Env";
			reg = <0xc0000 0x40000>;
		};
		kernel@3 {
			/* 4 MB */
			label = "Kernel";
			reg = <0x100000 0x400000>;
		};
		ipmi@4 {
			label = "IPMI FRU";
			reg = <0x500000 0x40000>;
		};
		fs@5 {
			label = "File System";
			reg = <0x540000 0x1ac0000>;
		};
	};
};

&mcspi3 {
	/* DMA event numbers stolen from MCASP */
	dmas = <&edma_xbar 8 0 16 &edma_xbar 9 0 17
		&edma_xbar 10 0 18 &edma_xbar 11 0 19>;
	dma-names = "tx0", "rx0", "tx1", "rx1";
};

&mcspi4 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi4_pins>;

	/* DMA event numbers stolen from MCASP, MCBSP */
	dmas = <&edma_xbar 12 0 20 &edma_xbar 13 0 21>;
	dma-names = "tx0", "rx0";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for AM4372 SoC
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/am4.h>

/ {
	compatible = "ti,am4372", "ti,am43";
	interrupt-parent = <&wakeupgen>;
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };

	memory@0 {
		device_type = "memory";
		reg = <0 0>;
	};

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		ethernet0 = &cpsw_port1;
		ethernet1 = &cpsw_port2;
		spi0 = &qspi;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu: cpu@0 {
			compatible = "arm,cortex-a9";
			enable-method = "ti,am4372";
			device_type = "cpu";
			reg = <0>;

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			operating-points-v2 = <&cpu0_opp_table>;

			clock-latency = <300000>; /* From omap-cpufreq driver */
			cpu-idle-states = <&mpu_gate>;
		};

		idle-states {
			mpu_gate: mpu_gate {
				compatible = "arm,idle-state";
				entry-latency-us = <40>;
				exit-latency-us = <100>;
				min-residency-us = <300>;
				local-timer-stop;
			};
		};
	};

	cpu0_opp_table: opp-table {
		compatible = "operating-points-v2-ti-cpu";
		syscon = <&scm_conf>;

		opp50-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <950000 931000 969000>;
			opp-supported-hw = <0xFF 0x01>;
			opp-suspend;
		};

		opp100-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1100000 1078000 1122000>;
			opp-supported-hw = <0xFF 0x04>;
		};

		opp120-720000000 {
			opp-hz = /bits/ 64 <720000000>;
			opp-microvolt = <1200000 1176000 1224000>;
			opp-supported-hw = <0xFF 0x08>;
		};

		oppturbo-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <1260000 1234800 1285200>;
			opp-supported-hw = <0xFF 0x10>;
		};

		oppnitro-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <1325000 1298500 1351500>;
			opp-supported-hw = <0xFF 0x20>;
		};
	};

	soc {
		compatible = "ti,omap-infra";
	};

	gic: interrupt-controller@48241000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48241000 0x1000>,
		      <0x48240100 0x0100>;
		interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
		compatible = "ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48281000 0x1000>;
		interrupt-parent = <&gic>;
	};

	scu: scu@48240000 {
		compatible = "arm,cortex-a9-scu";
		reg = <0x48240000 0x100>;
	};

	global_timer: timer@48240200 {
		compatible = "arm,cortex-a9-global-timer";
		reg = <0x48240200 0x100>;
		interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
		interrupt-parent = <&gic>;
		clocks = <&mpu_periphclk>;
	};

	local_timer: timer@48240600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x48240600 0x100>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
		interrupt-parent = <&gic>;
		clocks = <&mpu_periphclk>;
	};

	cache-controller@48242000 {
		compatible = "arm,pl310-cache";
		reg = <0x48242000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	ocp@44000000 {
		compatible = "simple-pm-bus";
		power-domains = <&prm_per>;
		clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
		clock-names = "fck";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,no-idle;

		l3-noc@44000000 {
			compatible = "ti,am4372-l3-noc";
			reg = <0x44000000 0x400000>,
			      <0x44800000 0x400000>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		};

		l4_wkup: interconnect@44c00000 {
		};
		l4_per: interconnect@48000000 {
		};
		l4_fast: interconnect@4a000000 {
		};

		target-module@4c000000 {
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			reg = <0x4c000000 0x4>;
			reg-names = "rev";
			clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
			clock-names = "fck";
			ti,no-idle;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4c000000 0x1000000>;

			emif: emif@0 {
				compatible = "ti,emif-am4372";
				reg = <0 0x1000000>;
				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				sram = <&pm_sram_code
					&pm_sram_data>;
			};
		};

		target-module@49000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49000000 0x4>;
			reg-names = "rev";
			clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49000000 0x10000>;

			edma: dma@0 {
				compatible = "ti,edma3-tpcc";
				reg = <0 0x10000>;
				reg-names = "edma3_cc";
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "edma3_ccint", "edma3_mperr",
						  "edma3_ccerrint";
				dma-requests = <64>;
				#dma-cells = <2>;

				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
					   <&edma_tptc2 0>;

				ti,edma-memcpy-channels = <58 59>;
			};
		};

		target-module@49800000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49800000 0x4>,
			      <0x49800010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49800000 0x100000>;

			edma_tptc0: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@49900000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49900000 0x4>,
			      <0x49900010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49900000 0x100000>;

			edma_tptc1: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@49a00000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49a00000 0x4>,
			      <0x49a00010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49a00000 0x100000>;

			edma_tptc2: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@47810000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x478102fc 0x4>,
			      <0x47810110 0x4>,
			      <0x47810114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x47810000 0x1000>;

			mmc3: mmc@0 {
				compatible = "ti,am437-sdhci";
				ti,needs-special-reset;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x1000>;
				status = "disabled";
			};
		};

		sham_target: target-module@53100000 {
			compatible = "ti,sysc-omap3-sham", "ti,sysc";
			reg = <0x53100100 0x4>,
			      <0x53100110 0x4>,
			      <0x53100114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l3_clkdm */
			clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x53100000 0x1000>;

			sham: sham@0 {
				compatible = "ti,omap5-sham";
				reg = <0 0x300>;
				dmas = <&edma 36 0>;
				dma-names = "rx";
				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		aes_target: target-module@53501000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x53501080 0x4>,
			      <0x53501084 0x4>,
			      <0x53501088 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l3_clkdm */
			clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x53501000 0x1000>;

			aes: aes@0 {
				compatible = "ti,omap4-aes";
				reg = <0 0xa0>;
				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&edma 6 0>,
				      <&edma 5 0>;
				dma-names = "tx", "rx";
			};
		};

		des_target: target-module@53701000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x53701030 0x4>,
			      <0x53701034 0x4>,
			      <0x53701038 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l3_clkdm */
			clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x53701000 0x1000>;

			des: des@0 {
				compatible = "ti,omap4-des";
				reg = <0 0xa0>;
				interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&edma 34 0>,
				       <&edma 33 0>;
				dma-names = "tx", "rx";
			};
		};

		pruss_tm: target-module@54400000 {
			compatible = "ti,sysc-pruss", "ti,sysc";
			reg = <0x54426000 0x4>,
			      <0x54426004 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
					 SYSC_PRUSS_SUB_MWAIT)>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
			clock-names = "fck";
			resets = <&prm_per 1>;
			reset-names = "rstctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x54400000 0x80000>;

			pruss1: pruss@0 {
				compatible = "ti,am4376-pruss1";
				reg = <0x0 0x40000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				pruss1_mem: memories@0 {
					reg = <0x0 0x2000>,
					      <0x2000 0x2000>,
					      <0x10000 0x8000>;
					reg-names = "dram0", "dram1",
						    "shrdram2";
				};

				pruss1_cfg: cfg@26000 {
					compatible = "ti,pruss-cfg", "syscon";
					reg = <0x26000 0x2000>;
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0x0 0x26000 0x2000>;

					clocks {
						#address-cells = <1>;
						#size-cells = <0>;

						pruss1_iepclk_mux: iepclk-mux@30 {
							reg = <0x30>;
							#clock-cells = <0>;
							clocks = <&sysclk_div>,     /* icss_iep_gclk */
								 <&pruss_ocp_gclk>; /* icss_ocp_gclk */
						};
					};
				};

				pruss1_mii_rt: mii-rt@32000 {
					compatible = "ti,pruss-mii", "syscon";
					reg = <0x32000 0x58>;
				};

				pruss1_intc: interrupt-controller@20000 {
					compatible = "ti,pruss-intc";
					reg = <0x20000 0x2000>;
					interrupt-controller;
					#interrupt-cells = <3>;
					interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "host_intr0", "host_intr1",
							  "host_intr2", "host_intr3",
							  "host_intr4",
							  "host_intr6", "host_intr7";
					ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
				};

				pru1_0: pru@34000 {
					compatible = "ti,am4376-pru";
					reg = <0x34000 0x3000>,
					      <0x22000 0x400>,
					      <0x22400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am437x-pru1_0-fw";
				};

				pru1_1: pru@38000 {
					compatible = "ti,am4376-pru";
					reg = <0x38000 0x3000>,
					      <0x24000 0x400>,
					      <0x24400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am437x-pru1_1-fw";
				};

				pruss1_mdio: mdio@32400 {
					compatible = "ti,davinci_mdio";
					reg = <0x32400 0x90>;
					clocks = <&dpll_core_m4_ck>;
					clock-names = "fck";
					bus_freq = <1000000>;
					#address-cells = <1>;
					#size-cells = <0>;
				};
			};

			pruss0: pruss@40000 {
				compatible = "ti,am4376-pruss0";
				reg = <0x40000 0x40000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				pruss0_mem: memories@40000 {
					reg = <0x40000 0x1000>,
					      <0x42000 0x1000>;
					reg-names = "dram0", "dram1";
				};

				pruss0_cfg: cfg@66000 {
					compatible = "ti,pruss-cfg", "syscon";
					reg = <0x66000 0x2000>;
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0x0 0x66000 0x2000>;

					clocks {
						#address-cells = <1>;
						#size-cells = <0>;

						pruss0_iepclk_mux: iepclk-mux@30 {
							reg = <0x30>;
							#clock-cells = <0>;
							clocks = <&sysclk_div>,     /* icss_iep_gclk */
								 <&pruss_ocp_gclk>; /* icss_ocp_gclk */
						};
					};
				};

				pruss0_mii_rt: mii-rt@72000 {
					compatible = "ti,pruss-mii", "syscon";
					reg = <0x72000 0x58>;
					status = "disabled";
				};

				pruss0_intc: interrupt-controller@60000 {
					compatible = "ti,pruss-intc";
					reg = <0x60000 0x2000>;
					interrupt-controller;
					#interrupt-cells = <3>;
					interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "host_intr0", "host_intr1",
							  "host_intr2", "host_intr3",
							  "host_intr4",
							  "host_intr6", "host_intr7";
					ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
				};

				pru0_0: pru@74000 {
					compatible = "ti,am4376-pru";
					reg = <0x74000 0x1000>,
					      <0x62000 0x400>,
					      <0x62400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am437x-pru0_0-fw";
				};

				pru0_1: pru@78000 {
					compatible = "ti,am4376-pru";
					reg = <0x78000 0x1000>,
					      <0x64000 0x400>,
					      <0x64400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am437x-pru0_1-fw";
				};
			};
		};

		target-module@50000000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x50000000 4>,
			      <0x50000010 4>,
			      <0x50000014 4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
				 <0x00000000 0x00000000 0x40000000>; /* data */

			gpmc: gpmc@50000000 {
				compatible = "ti,am3352-gpmc";
				dmas = <&edma 52 0>;
				dma-names = "rxtx";
				clocks = <&l3s_gclk>;
				clock-names = "fck";
				reg = <0x50000000 0x2000>;
				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
				gpmc,num-cs = <7>;
				gpmc,num-waitpins = <2>;
				#address-cells = <2>;
				#size-cells = <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-controller;
				#gpio-cells = <2>;
				status = "disabled";
			};
		};

		target-module@47900000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x47900000 0x4>,
			      <0x47900010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x47900000 0x1000>,
				 <0x30000000 0x30000000 0x4000000>;

			qspi: spi@0 {
				compatible = "ti,am4372-qspi";
				reg = <0 0x100>,
				      <0x30000000 0x4000000>;
				reg-names = "qspi_base", "qspi_mmap";
				clocks = <&dpll_per_m2_div4_ck>;
				clock-names = "fck";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <0 138 0x4>;
				num-cs = <4>;
			};
		};

		target-module@40300000 {
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
			clock-names = "fck";
			ti,no-idle;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x40300000 0x40000>;

			ocmcram: sram@0 {
				compatible = "mmio-sram";
				reg = <0 0x40000>; /* 256k */
				ranges = <0 0 0x40000>;
				#address-cells = <1>;
				#size-cells = <1>;

				pm_sram_code: pm-code-sram@0 {
					compatible = "ti,sram";
					reg = <0x0 0x1000>;
					protect-exec;
				};

				pm_sram_data: pm-data-sram@1000 {
					compatible = "ti,sram";
					reg = <0x1000 0x1000>;
					pool;
				};
			};
		};

		target-module@56000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x5600fe00 0x4>,
			      <0x5600fe10 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
			clock-names = "fck";
			power-domains = <&prm_gfx>;
			resets = <&prm_gfx 0>;
			reset-names = "rstctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x56000000 0x1000000>;
		};
	};
};

#include "am437x-l4.dtsi"
#include "am43xx-clocks.dtsi"

&prcm {
	prm_mpu: prm@300 {
		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
		reg = <0x300 0x100>;
		#power-domain-cells = <0>;
	};

	prm_gfx: prm@400 {
		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
		reg = <0x400 0x100>;
		#power-domain-cells = <0>;
		#reset-cells = <1>;
	};

	prm_rtc: prm@500 {
		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
		reg = <0x500 0x100>;
		#power-domain-cells = <0>;
	};

	prm_tamper: prm@600 {
		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
		reg = <0x600 0x100>;
		#power-domain-cells = <0>;
	};

	prm_cefuse: prm@700 {
		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
		reg = <0x700 0x100>;
		#power-domain-cells = <0>;
	};

	prm_per: prm@800 {
		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
		reg = <0x800 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_wkup: prm@2000 {
		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
		reg = <0x2000 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_device: prm@4000 {
		compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
		reg = <0x4000 0x100>;
		#reset-cells = <1>;
	};
};

/* Preferred always-on timer for clocksource */
&timer1_target {
	ti,no-reset-on-init;
	ti,no-idle;
	clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
		 <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
	clock-names = "fck", "ick";
	timer@0 {
		assigned-clocks = <&timer1_fck>;
		assigned-clock-parents = <&sys_clkin_ck>;
	};
};

/* Preferred timer for clockevent */
&timer2_target {
	ti,no-reset-on-init;
	ti,no-idle;
	clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
		 <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
	clock-names = "fck", "ick";
	timer@0 {
		assigned-clocks = <&timer2_fck>;
		assigned-clock-parents = <&sys_clkin_ck>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/
 */

/dts-v1/;

#include <dt-bindings/pinctrl/am43xx.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am4372.dtsi"

/ {
	model = "CompuLab CM-T43";
	compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43";

	leds {
		compatible = "gpio-leds";

		ledb {
			label = "cm-t43:green";
			gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	vmmc_3v3: fixedregulator-v3_3 {
		compatible = "regulator-fixed";
		regulator-name = "vmmc_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		enable-active-high;
	};
};

&am43xx_pinmux {
	pinctrl-names = "default";
	pinctrl-0 = <&cm_t43_led_pins>;

	cm_t43_led_pins: cm_t43_led_pins {
		pinctrl-single,pins = <
			AM4372_IOPAD(0xa78, MUX_MODE7)
		>;
	};

	i2c0_pins: i2c0_pins {
		pinctrl-single,pins = <
			AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
			AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
		>;
	};

	emmc_pins: emmc_pins {
		pinctrl-single,pins = <
			AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */
			AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */
			AM4372_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2 */
			AM4372_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3 */
			AM4372_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad12.mmc1_dat4 */
			AM4372_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad13.mmc1_dat5 */
			AM4372_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad14.mmc1_dat6 */
			AM4372_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad15.mmc1_dat7 */
			AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
			AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
		>;
	};

	spi0_pins: pinmux_spi0_pins {
		pinctrl-single,pins = <
			AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */
			AM4372_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
			AM4372_IOPAD(0x958, PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
			AM4372_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
		>;
	};

	nand_flash_x8: nand_flash_x8 {
		pinctrl-single,pins = <
			AM4372_IOPAD(0x800, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
			AM4372_IOPAD(0x804, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
			AM4372_IOPAD(0x808, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
			AM4372_IOPAD(0x80c, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
			AM4372_IOPAD(0x810, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
			AM4372_IOPAD(0x814, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
			AM4372_IOPAD(0x818, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
			AM4372_IOPAD(0x81c, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
			AM4372_IOPAD(0x870, PIN_INPUT_PULLUP  | MUX_MODE0)
			AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE0)
			AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0)
			AM4372_IOPAD(0x898, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
			AM4372_IOPAD(0x894, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
			AM4372_IOPAD(0x890, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
			AM4372_IOPAD(0x89c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
		>;
	};

	cpsw_default: cpsw_default {
		pinctrl-single,pins = <
			/* Slave 1 */
			AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_txen */
			AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rxctl */
			AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_txd3 */
			AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_txd2 */
			AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_txd1 */
			AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_txd0 */
			AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rmii1_tclk */
			AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rmii1_rclk */
			AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rxd3 */
			AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rxd2 */
			AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rxd1 */
			AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rxd0 */
			AM4372_IOPAD(0xa74, MUX_MODE3)
			/* Slave 2 */
			AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a0.txen */
			AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN  | MUX_MODE2)	/* gpmc_a1.rxctl */
			AM4372_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a2.txd3 */
			AM4372_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a3.txd2 */
			AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a4.txd1 */
			AM4372_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a5.txd0 */
			AM4372_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a6.tclk */
			AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN  | MUX_MODE2)	/* gpmc_a7.rclk */
			AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN  | MUX_MODE2)	/* gpmc_a8.rxd3 */
			AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN  | MUX_MODE2)	/* gpmc_a9.rxd2 */
			AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN  | MUX_MODE2)	/* gpmc_a10.rxd1 */
			AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN  | MUX_MODE2)	/* gpmc_a11.rxd0 */
			AM4372_IOPAD(0xa38, MUX_MODE7)
		>;
	};

	davinci_mdio_default: davinci_mdio_default {
		pinctrl-single,pins = <
			/* MDIO */
			AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
			AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
		>;
	};
};

&gpmc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&nand_flash_x8>;
	ranges = <0 0 0x08000000 0x1000000>;
	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;		/* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;

		nand-bus-width = <8>;
		gpmc,device-width = <1>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <44>;
		gpmc,cs-wr-off-ns = <44>;
		gpmc,adv-on-ns = <6>;
		gpmc,adv-rd-off-ns = <34>;
		gpmc,adv-wr-off-ns = <44>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <40>;
		gpmc,oe-on-ns = <0>;
		gpmc,oe-off-ns = <54>;
		gpmc,access-ns = <64>;
		gpmc,rd-cycle-ns = <82>;
		gpmc,wr-cycle-ns = <82>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-access-ns = <40>;
		gpmc,wr-data-mux-bus-ns = <0>;

		#address-cells = <1>;
		#size-cells = <1>;
		/* MTD partition table */
		partition@0 {
			label = "kernel";
			reg = <0x0 0x00980000>;
		};
		partition@980000 {
			label = "dtb";
			reg = <0x00980000 0x00080000>;
		};
		partition@a00000 {
			label = "rootfs";
			reg = <0x00a00000 0x0>;
		};
	};
};

&i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	clock-frequency = <100000>;

	tps65218: tps65218@24 {
		compatible = "ti,tps65218";
		reg = <0x24>;
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */
		interrupt-parent = <&gic>;
		interrupt-controller;
		#interrupt-cells = <2>;

		dcdc1: regulator-dcdc1 {
			regulator-name = "vdd_core";
			regulator-min-microvolt = <912000>;
			regulator-max-microvolt = <1144000>;
			regulator-boot-on;
			regulator-always-on;
		};

		dcdc2: regulator-dcdc2 {
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <912000>;
			regulator-max-microvolt = <1378000>;
			regulator-boot-on;
			regulator-always-on;
		};

		dcdc3: regulator-dcdc3 {
			regulator-name = "vdcdc3";
			regulator-suspend-enable;
			regulator-min-microvolt = <1500000>;
			regulator-max-microvolt = <1500000>;
			regulator-boot-on;
			regulator-always-on;
		};

		dcdc5: regulator-dcdc5 {
			regulator-name = "v1_0bat";
			regulator-min-microvolt = <1000000>;
			regulator-max-microvolt = <1000000>;
			regulator-boot-on;
			regulator-always-on;
		};

		dcdc6: regulator-dcdc6 {
			regulator-name = "v1_8bat";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-boot-on;
			regulator-always-on;
		};

		ldo1: regulator-ldo1 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-boot-on;
			regulator-always-on;
		};
	};

	eeprom_module: at24@50 {
		compatible = "atmel,24c02";
		reg = <0x50>;
		pagesize = <16>;
	};
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&gpio3 {
	status = "okay";
};

&gpio4 {
	status = "okay";
};

&gpio5 {
	status = "okay";
};

&mmc2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_pins>;
	vmmc-supply = <&vmmc_3v3>;
	bus-width = <8>;
	non-removable;
};

&spi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins>;
	dmas = <&edma 16 0
		&edma 17 0>;
	dma-names = "tx0", "rx0";

	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <20000000>;
		partition@0 {
			label = "uboot";
			reg = <0x0 0xc0000>;
		};

		partition@c0000 {
			label = "uboot environment";
			reg = <0xc0000 0x40000>;
		};

		partition@100000 {
			label = "reserved";
			reg = <0x100000 0x100000>;
		};
	};
};

&mac_sw {
	pinctrl-names = "default";
	pinctrl-0 = <&cpsw_default>;
	status = "okay";
};

&davinci_mdio_sw {
	pinctrl-names = "default";
	pinctrl-0 = <&davinci_mdio_default>;

	ethphy0: ethernet-phy@0 {
		reg = <0>;
	};

	ethphy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&cpsw_port1 {
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-txid";
	ti,dual-emac-pvid = <1>;
};

&cpsw_port2 {
	phy-handle = <&ethphy1>;
	phy-mode = "rgmii-txid";
	ti,dual-emac-pvid = <2>;
};

&dwc3_1 {
	status = "okay";
};

&usb2_phy1 {
	status = "okay";
};

&usb1 {
	dr_mode = "host";
	status = "okay";
};

&dwc3_2 {
	status = "okay";
};

&usb2_phy2 {
	status = "okay";
};

&usb2 {
	dr_mode = "host";
	status = "okay";
	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "peripheral", "host", "otg";
};

&elm {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&tscadc {
	status = "okay";
	tsc {
		ti,wires = <4>;
		ti,x-plate-resistance = <200>;
		ti,coordinate-readouts = <5>;
		ti,wire-config = <0x00 0x11 0x22 0x33>;
	};

	adc {
		ti,adc-channels = <4 5 6 7>;
	};
};

&cpu {
	cpu0-supply = <&dcdc2>;
	operating-points = <1000000 1330000>,
			   <800000 1260000>,
			   <720000 1200000>,
			   <600000 1100000>,
			   <300000 950000>;
};

&pruss1_mdio {
	status = "disabled";
};