code:
* Rockchip AXI PCIe Root Port Bridge DT description

Required properties:
- #address-cells: Address representation for root ports, set to <3>
- #size-cells: Size representation for root ports, set to <2>
- #interrupt-cells: specifies the number of cells needed to encode an
		interrupt source. The value must be 1.
- compatible: Should contain "rockchip,rk3399-pcie"
- reg: Two register ranges as listed in the reg-names property
- reg-names: Must include the following names
	- "axi-base"
	- "apb-base"
- clocks: Must contain an entry for each entry in clock-names.
		See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
	- "aclk"
	- "aclk-perf"
	- "hclk"
	- "pm"
- msi-map: Maps a Requester ID to an MSI controller and associated
	msi-specifier data. See ./pci-msi.txt
- interrupts: Three interrupt entries must be specified.
- interrupt-names: Must include the following names
	- "sys"
	- "legacy"
	- "client"
- resets: Must contain seven entries for each entry in reset-names.
	   See ../reset/reset.txt for details.
- reset-names: Must include the following names
	- "core"
	- "mgmt"
	- "mgmt-sticky"
	- "pipe"
	- "pm"
	- "aclk"
	- "pclk"
- pinctrl-names : The pin control state names
- pinctrl-0: The "default" pinctrl state
- #interrupt-cells: specifies the number of cells needed to encode an
	interrupt source. The value must be 1.
- interrupt-map-mask and interrupt-map: standard PCI properties

Required properties for legacy PHY model (deprecated):
- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
- phy-names:  MUST be "pcie-phy".

Required properties for per-lane PHY model (preferred):
- phys: Must contain an phandle to a PHY for each entry in phy-names.
- phy-names: Must include 4 entries for all 4 lanes even if some of
  them won't be used for your cases. Entries are of the form "pcie-phy-N":
  where N ranges from 0 to 3.
  (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
  for changing the #phy-cells of phy node to support it)

Optional Property:
- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
	using 24MHz OSC for RC's PHY.
- ep-gpios: contain the entry for pre-reset GPIO
- num-lanes: number of lanes to use
- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.

*Interrupt controller child node*
The core controller provides a single interrupt for legacy INTx. The PCIe node
should contain an interrupt controller node as a target for the PCI
'interrupt-map' property. This node represents the domain at which the four
INTx interrupts are decoded and routed.

Required properties for Interrupt controller child node:
- interrupt-controller: identifies the node as an interrupt controller
- #address-cells: specifies the number of cells needed to encode an
	address. The value must be 0.
- #interrupt-cells: specifies the number of cells needed to encode an
	interrupt source. The value must be 1.

Example:

pcie0: pcie@f8000000 {
	compatible = "rockchip,rk3399-pcie";
	#address-cells = <3>;
	#size-cells = <2>;
	clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
		 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
	clock-names = "aclk", "aclk-perf",
		      "hclk", "pm";
	bus-range = <0x0 0x1>;
	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
		     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
		     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
	interrupt-names = "sys", "legacy", "client";
	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
	assigned-clock-rates = <100000000>;
	ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
	ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
		  0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
	num-lanes = <4>;
	msi-map = <0x0 &its 0x0 0x1000>;
	reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
	reg-names = "axi-base", "apb-base";
	resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
		 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
		 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
	reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
		      "pm", "pclk", "aclk";
	/* deprecated legacy PHY model */
	phys = <&pcie_phy>;
	phy-names = "pcie-phy";
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_clkreq>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 7>;
	interrupt-map = <0 0 0 1 &pcie0_intc 0>,
			<0 0 0 2 &pcie0_intc 1>,
			<0 0 0 3 &pcie0_intc 2>,
			<0 0 0 4 &pcie0_intc 3>;
	pcie0_intc: interrupt-controller {
		interrupt-controller;
		#address-cells = <0>;
		#interrupt-cells = <1>;
	};
};

pcie0: pcie@f8000000 {
	...

	/* preferred per-lane PHY model */
	phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
	phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";

	...
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung SoC series PCIe Host Controller

maintainers:
  - Marek Szyprowski <m.szyprowski@samsung.com>
  - Jaehoon Chung <jh80.chung@samsung.com>

description: |+
  Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
  PCIe IP and thus inherits all the common properties defined in
  snps,dw-pcie.yaml.

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    const: samsung,exynos5433-pcie

  reg:
    items:
      - description: Data Bus Interface (DBI) registers.
      - description: External Local Bus interface (ELBI) registers.
      - description: PCIe configuration space region.

  reg-names:
    items:
      - const: dbi
      - const: elbi
      - const: config

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: PCIe bridge clock
      - description: PCIe bus clock

  clock-names:
    items:
      - const: pcie
      - const: pcie_bus

  phys:
    maxItems: 1

  vdd10-supply:
    description:
      Phandle to a regulator that provides 1.0V power to the PCIe block.

  vdd18-supply:
    description:
      Phandle to a regulator that provides 1.8V power to the PCIe block.

  num-lanes:
    const: 1

  num-viewport:
    const: 3

required:
  - reg
  - reg-names
  - interrupts
  - "#address-cells"
  - "#size-cells"
  - "#interrupt-cells"
  - interrupt-map
  - interrupt-map-mask
  - ranges
  - bus-range
  - device_type
  - num-lanes
  - num-viewport
  - clocks
  - clock-names
  - phys
  - vdd10-supply
  - vdd18-supply

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/exynos5433.h>

    pcie: pcie@15700000 {
        compatible = "samsung,exynos5433-pcie";
        reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>;
        reg-names = "dbi", "elbi", "config";
        #address-cells = <3>;
        #size-cells = <2>;
        #interrupt-cells = <1>;
        device_type = "pci";
        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
        clock-names = "pcie", "pcie_bus";
        phys = <&pcie_phy>;
        pinctrl-0 = <&pcie_bus &pcie_wlanen>;
        pinctrl-names = "default";
        num-lanes = <1>;
        num-viewport = <3>;
        bus-range = <0x00 0xff>;
        ranges = <0x81000000 0 0	  0x0c001000 0 0x00010000>,
                 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
        vdd10-supply = <&ldo6_reg>;
        vdd18-supply = <&ldo7_reg>;
        interrupt-map-mask = <0 0 0 0>;
        interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
    };
...

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive FU740 PCIe host controller

description: |+
  SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
  PCI core. It shares common features with the PCIe DesignWare core and
  inherits common properties defined in
  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.

maintainers:
  - Paul Walmsley <paul.walmsley@sifive.com>
  - Greentime Hu <greentime.hu@sifive.com>

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    const: sifive,fu740-pcie

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: dbi
      - const: config
      - const: mgmt

  dma-coherent: true

  num-lanes:
    const: 8

  msi-parent: true

  interrupt-names:
    items:
      - const: msi
      - const: inta
      - const: intb
      - const: intc
      - const: intd

  resets:
    description: A phandle to the PCIe power up reset line.
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: pcie_aux

  pwren-gpios:
    description: Should specify the GPIO for controlling the PCI bus device power on.
    maxItems: 1

  reset-gpios:
    maxItems: 1

required:
  - dma-coherent
  - num-lanes
  - interrupts
  - interrupt-names
  - interrupt-map-mask
  - interrupt-map
  - clocks
  - clock-names
  - resets
  - pwren-gpios
  - reset-gpios

unevaluatedProperties: false

examples:
  - |
    bus {
        #address-cells = <2>;
        #size-cells = <2>;
        #include <dt-bindings/clock/sifive-fu740-prci.h>

        pcie@e00000000 {
            compatible = "sifive,fu740-pcie";
            #address-cells = <3>;
            #size-cells = <2>;
            #interrupt-cells = <1>;
            reg = <0xe 0x00000000 0x0 0x80000000>,
                  <0xd 0xf0000000 0x0 0x10000000>,
                  <0x0 0x100d0000 0x0 0x1000>;
            reg-names = "dbi", "config", "mgmt";
            device_type = "pci";
            dma-coherent;
            bus-range = <0x0 0xff>;
            ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000>,      /* I/O */
                     <0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000>,    /* mem */
                     <0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000>,    /* mem */
                     <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
            num-lanes = <0x8>;
            interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
            interrupt-names = "msi", "inta", "intb", "intc", "intd";
            interrupt-parent = <&plic0>;
            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
            interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
                            <0x0 0x0 0x0 0x2 &plic0 58>,
                            <0x0 0x0 0x0 0x3 &plic0 59>,
                            <0x0 0x0 0x0 0x4 &plic0 60>;
            clock-names = "pcie_aux";
            clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
            resets = <&prci 4>;
            pwren-gpios = <&gpio 5 0>;
            reset-gpios = <&gpio 8 0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DWC PCIe RP/EP controller

maintainers:
  - Jingoo Han <jingoohan1@gmail.com>
  - Gustavo Pimentel <gustavo.pimentel@synopsys.com>

description:
  Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
  properties.

select: false

properties:
  reg:
    description:
      DWC PCIe CSR space is normally accessed over the dedicated Data Bus
      Interface - DBI. In accordance with the reference manual the register
      configuration space belongs to the Configuration-Dependent Module (CDM)
      and is split up into several sub-parts Standard PCIe configuration
      space, Port Logic Registers (PL), Shadow Config-space Registers,
      iATU/eDMA registers. The particular sub-space is selected by the
      CDM/ELBI (dbi_cs) and CS2 (dbi_cs2) signals (selector bits). Such
      configuration provides a flexible interface for the system engineers to
      either map the particular space at a desired MMIO address or just leave
      them in a contiguous memory space if pure Native or AXI Bridge DBI access
      is selected. Note the PCIe CFG-space, PL and Shadow registers are
      specific for each activated function, while the rest of the sub-spaces
      are common for all of them (if there are more than one).
    minItems: 2
    maxItems: 6

  reg-names:
    minItems: 2
    maxItems: 6

  interrupts:
    description:
      There are two main sub-blocks which are normally capable of
      generating interrupts. It's System Information Interface and MSI
      interface. While the former one has some common for the Host and
      Endpoint controllers IRQ-signals, the later interface is obviously
      Root Complex specific since it's responsible for the incoming MSI
      messages signalling. The System Information IRQ signals are mainly
      responsible for reporting the generic PCIe hierarchy and Root
      Complex events like VPD IO request, general AER, PME, Hot-plug, link
      bandwidth change, link equalization request, INTx asserted/deasserted
      Message detection, embedded DMA Tx/Rx/Error.
    minItems: 1
    maxItems: 26

  interrupt-names:
    minItems: 1
    maxItems: 26

  clocks:
    description:
      DWC PCIe reference manual explicitly defines a set of the clocks required
      to get the controller working correctly. In general all of them can
      be divided into two groups':' application and core clocks. Note the
      platforms may have some of the clock sources unspecified in case if the
      corresponding domains are fed up from a common clock source.
    minItems: 1
    maxItems: 7

  clock-names:
    minItems: 1
    maxItems: 7
    items:
      oneOf:
        - description:
            Data Bus Interface (DBI) clock. Clock signal for the AXI-bus
            interface of the Configuration-Dependent Module, which is
            basically the set of the controller CSRs.
          const: dbi
        - description:
            Application AXI-bus Master interface clock. Basically this is
            a clock for the controller DMA interface (PCI-to-CPU).
          const: mstr
        - description:
            Application AXI-bus Slave interface clock. This is a clock for
            the CPU-to-PCI memory IO interface.
          const: slv
        - description:
            Controller Core-PCS PIPE interface clock. It's normally
            supplied by an external PCS-PHY.
          const: pipe
        - description:
            Controller Primary clock. It's assumed that all controller input
            signals (except resets) are synchronous to this clock.
          const: core
        - description:
            Auxiliary clock for the controller PMC domain. The controller
            partitioning implies having some parts to operate with this
            clock in some power management states.
          const: aux
        - description:
            Generic reference clock. In case if there are several
            interfaces fed up with a common clock source it's advisable to
            define it with this name (for instance pipe, core and aux can
            be connected to a single source of the periodic signal).
          const: ref
        - description:
            Clock for the PHY registers interface. Originally this is
            a PHY-viewport-based interface, but some platform may have
            specifically designed one.
          const: phy_reg
        - description:
            Vendor-specific clock names. Consider using the generic names
            above for new bindings.
          oneOf:
            - description: See native 'dbi' clock for details
              enum: [ pcie, pcie_apb_sys, aclk_dbi ]
            - description: See native 'mstr/slv' clock for details
              enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ]
            - description: See native 'pipe' clock for details
              enum: [ pcie_phy, pcie_phy_ref, link ]
            - description: See native 'aux' clock for details
              enum: [ pcie_aux ]
            - description: See native 'ref' clock for details.
              enum: [ gio ]
            - description: See nativs 'phy_reg' clock for details
              enum: [ pcie_apb_phy, pclk ]

  resets:
    description:
      DWC PCIe reference manual explicitly defines a set of the reset
      signals required to be de-asserted to properly activate the controller
      sub-parts. All of these signals can be divided into two sub-groups':'
      application and core resets with respect to the main sub-domains they
      are supposed to reset. Note the platforms may have some of these signals
      unspecified in case if they are automatically handled or aggregated into
      a comprehensive control module.
    minItems: 1
    maxItems: 10

  reset-names:
    minItems: 1
    maxItems: 10
    items:
      oneOf:
        - description: Data Bus Interface (DBI) domain reset
          const: dbi
        - description: AXI-bus Master interface reset
          const: mstr
        - description: AXI-bus Slave interface reset
          const: slv
        - description: Application-dependent interface reset
          const: app
        - description: Controller Non-sticky CSR flags reset
          const: non-sticky
        - description: Controller sticky CSR flags reset
          const: sticky
        - description: PIPE-interface (Core-PCS) logic reset
          const: pipe
        - description:
            Controller primary reset (resets everything except PMC module)
          const: core
        - description: PCS/PHY block reset
          const: phy
        - description: PMC hot reset signal
          const: hot
        - description: Cold reset signal
          const: pwr
        - description:
            Vendor-specific reset names. Consider using the generic names
            above for new bindings.
          oneOf:
            - description: See native 'app' reset for details
              enum: [ apps, gio, apb ]
            - description: See native 'phy' reset for details
              enum: [ pciephy, link ]
            - description: See native 'pwr' reset for details
              enum: [ turnoff ]

  phys:
    description:
      There can be up to the number of possible lanes PHYs specified placed in
      the phandle array in the line-based order. Obviously each the specified
      PHYs are supposed to be able to work in the PCIe mode with a speed
      implied by the DWC PCIe controller they are attached to.
    minItems: 1
    maxItems: 16

  phy-names:
    minItems: 1
    maxItems: 16
    oneOf:
      - description: Generic PHY names
        items:
          pattern: '^pcie[0-9]+$'
      - description:
          Vendor-specific PHY names. Consider using the generic
          names above for new bindings.
        items:
          oneOf:
            - pattern: '^pcie(-?phy[0-9]*)?$'
            - pattern: '^p2u-[0-7]$'

  reset-gpio:
    deprecated: true
    description:
      Reference to the GPIO-controlled PERST# signal. It is used to reset all
      the peripheral devices available on the PCIe bus.
    maxItems: 1

  reset-gpios:
    description:
      Reference to the GPIO-controlled PERST# signal. It is used to reset all
      the peripheral devices available on the PCIe bus.
    maxItems: 1

  max-link-speed:
    maximum: 5

  num-lanes:
    description:
      Number of PCIe link lanes to use. Can be omitted if the already brought
      up link is supposed to be preserved.
    maximum: 16

  num-ob-windows:
    $ref: /schemas/types.yaml#/definitions/uint32
    deprecated: true
    description:
      Number of outbound address translation windows. This parameter can be
      auto-detected based on the iATU memory writability. So there is no
      point in having a dedicated DT-property for it.
    maximum: 256

  num-ib-windows:
    $ref: /schemas/types.yaml#/definitions/uint32
    deprecated: true
    description:
      Number of inbound address translation windows. In the same way as
      for the outbound AT windows, this parameter can be auto-detected based
      on the iATU memory writability. There is no point having a dedicated
      DT-property for it either.
    maximum: 256

  num-viewport:
    $ref: /schemas/types.yaml#/definitions/uint32
    deprecated: true
    description:
      Number of outbound view ports configured in hardware. It's the same as
      the number of outbound AT windows.
    maximum: 256

  snps,enable-cdm-check:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Enable automatic checking of CDM (Configuration Dependent Module)
      registers for data corruption. CDM registers include standard PCIe
      configuration space registers, Port Logic registers, DMA and iATU
      registers. This feature has been available since DWC PCIe v4.80a.

  dma-coherent: true

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare PCIe endpoint interface

maintainers:
  - Jingoo Han <jingoohan1@gmail.com>
  - Gustavo Pimentel <gustavo.pimentel@synopsys.com>

description: |
  Synopsys DesignWare PCIe host controller endpoint

# Please create a separate DT-schema for your DWC PCIe Endpoint controller
# and make sure it's assigned with the vendor-specific compatible string.
select:
  properties:
    compatible:
      const: snps,dw-pcie-ep
  required:
    - compatible

allOf:
  - $ref: /schemas/pci/pci-ep.yaml#
  - $ref: /schemas/pci/snps,dw-pcie-common.yaml#

properties:
  reg:
    description:
      DBI, DBI2 reg-spaces and outbound memory window are required for the
      normal controller functioning. iATU memory IO region is also required
      if the space is unrolled (IP-core version >= 4.80a).
    minItems: 2
    maxItems: 5

  reg-names:
    minItems: 2
    maxItems: 5
    items:
      oneOf:
        - description:
            Basic DWC PCIe controller configuration-space accessible over
            the DBI interface. This memory space is either activated with
            CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
            with all spaces. Note iATU/eDMA CSRs are indirectly accessible
            via the PL viewports on the DWC PCIe controllers older than
            v4.80a.
          const: dbi
        - description:
            Shadow DWC PCIe config-space registers. This space is selected
            by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
            the PCI-SIG PCIe CFG-space with the shadow registers for some
            PCI Header space, PCI Standard and Extended Structures. It's
            mainly relevant for the end-point controller configuration,
            but still there are some shadow registers available for the
            Root Port mode too.
          const: dbi2
        - description:
            External Local Bus registers. It's an application-dependent
            registers normally defined by the platform engineers. The space
            can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
            be accessed over some platform-specific means (for instance
            as a part of a system controller).
          enum: [ elbi, app ]
        - description:
            iATU/eDMA registers common for all device functions. It's an
            unrolled memory space with the internal Address Translation
            Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1
            and CS2 = 1. For IP-core releases prior v4.80a, these registers
            have been programmed via an indirect addressing scheme using a
            set of viewport CSRs mapped into the PL space. Note iATU is
            normally mapped to the 0x0 address of this region, while eDMA
            is available at 0x80000 base address.
          const: atu
        - description:
            Platform-specific eDMA registers. Some platforms may have eDMA
            CSRs mapped in a non-standard base address. The registers offset
            can be changed or the MS/LS-bits of the address can be attached
            in an additional RTL block before the MEM-IO transactions reach
            the DW PCIe slave interface.
          const: dma
        - description:
            PHY/PCS configuration registers. Some platforms can have the
            PCS and PHY CSRs accessible over a dedicated memory mapped
            region, but mainly these registers are indirectly accessible
            either by means of the embedded PHY viewport schema or by some
            platform-specific method.
          const: phy
        - description:
            Outbound iATU-capable memory-region which will be used to
            generate various application-specific traffic on the PCIe bus
            hierarchy. It's usage scenario depends on the endpoint
            functionality, for instance it can be used to create MSI(X)
            messages.
          const: addr_space
        - description:
            Vendor-specific CSR names. Consider using the generic names above
            for new bindings.
          oneOf:
            - description: See native 'elbi/app' CSR region for details.
              enum: [ link, appl ]
            - description: See native 'atu' CSR region for details.
              enum: [ atu_dma ]
    allOf:
      - contains:
          const: dbi
      - contains:
          const: addr_space

  interrupts:
    description:
      There is no mandatory IRQ signals for the normal controller functioning,
      but in addition to the native set the platforms may have a link- or
      PM-related IRQs specified.
    minItems: 1
    maxItems: 20

  interrupt-names:
    minItems: 1
    maxItems: 20
    items:
      oneOf:
        - description:
            Controller request to read or write virtual product data
            from/to the VPD capability registers.
          const: vpd
        - description:
            Link Equalization Request flag is set in the Link Status 2
            register (applicable if the corresponding IRQ is enabled in
            the Link Control 3 register).
          const: l_eq
        - description:
            Indicates that the eDMA Tx/Rx transfer is complete or that an
            error has occurred on the corresponding channel. eDMA can have
            eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
            to 16 IRQ signals all together. Write eDMA channels shall go
            first in the ordered row as per default edma_int[*] bus setup.
          pattern: '^dma([0-9]|1[0-5])?$'
        - description:
            PCIe protocol correctable error or a Data Path protection
            correctable error is detected by the automotive/safety
            feature.
          const: sft_ce
        - description:
            Indicates that the internal safety mechanism has detected an
            uncorrectable error.
          const: sft_ue
        - description:
            Application-specific IRQ raised depending on the vendor-specific
            events basis.
          const: app
        - description:
            Vendor-specific IRQ names. Consider using the generic names above
            for new bindings.
          oneOf:
            - description: See native "app" IRQ for details
              enum: [ intr ]

  max-functions:
    maximum: 32

required:
  - compatible
  - reg
  - reg-names

additionalProperties: true

examples:
  - |
    pcie-ep@dfd00000 {
      compatible = "snps,dw-pcie-ep";
      reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
            <0xdfc01000 0x0001000>, /* IP registers 2 */
            <0xd0000000 0x2000000>; /* Configuration space */
      reg-names = "dbi", "dbi2", "addr_space";

      interrupts = <23>, <24>;
      interrupt-names = "dma0", "dma1";

      clocks = <&sys_clk 12>, <&sys_clk 24>;
      clock-names = "dbi", "ref";

      resets = <&sys_rst 12>, <&sys_rst 24>;
      reset-names = "dbi", "phy";

      phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>;
      phy-names = "pcie0", "pcie1", "pcie2", "pcie3";

      max-link-speed = <3>;
      max-functions = /bits/ 8 <4>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare PCIe interface

maintainers:
  - Jingoo Han <jingoohan1@gmail.com>
  - Gustavo Pimentel <gustavo.pimentel@synopsys.com>

description: |
  Synopsys DesignWare PCIe host controller

# Please create a separate DT-schema for your DWC PCIe Root Port controller
# and make sure it's assigned with the vendor-specific compatible string.
select:
  properties:
    compatible:
      const: snps,dw-pcie
  required:
    - compatible

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#
  - $ref: /schemas/pci/snps,dw-pcie-common.yaml#

properties:
  reg:
    description:
      At least DBI reg-space and peripheral devices CFG-space outbound window
      are required for the normal controller work. iATU memory IO region is
      also required if the space is unrolled (IP-core version >= 4.80a).
    minItems: 2
    maxItems: 5

  reg-names:
    minItems: 2
    maxItems: 5
    items:
      oneOf:
        - description:
            Basic DWC PCIe controller configuration-space accessible over
            the DBI interface. This memory space is either activated with
            CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
            with all spaces. Note iATU/eDMA CSRs are indirectly accessible
            via the PL viewports on the DWC PCIe controllers older than
            v4.80a.
          const: dbi
        - description:
            Shadow DWC PCIe config-space registers. This space is selected
            by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
            the PCI-SIG PCIe CFG-space with the shadow registers for some
            PCI Header space, PCI Standard and Extended Structures. It's
            mainly relevant for the end-point controller configuration,
            but still there are some shadow registers available for the
            Root Port mode too.
          const: dbi2
        - description:
            External Local Bus registers. It's an application-dependent
            registers normally defined by the platform engineers. The space
            can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
            be accessed over some platform-specific means (for instance
            as a part of a system controller).
          enum: [ elbi, app ]
        - description:
            iATU/eDMA registers common for all device functions. It's an
            unrolled memory space with the internal Address Translation
            Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1
            and CS2 = 1. For IP-core releases prior v4.80a, these registers
            have been programmed via an indirect addressing scheme using a
            set of viewport CSRs mapped into the PL space. Note iATU is
            normally mapped to the 0x0 address of this region, while eDMA
            is available at 0x80000 base address.
          const: atu
        - description:
            Platform-specific eDMA registers. Some platforms may have eDMA
            CSRs mapped in a non-standard base address. The registers offset
            can be changed or the MS/LS-bits of the address can be attached
            in an additional RTL block before the MEM-IO transactions reach
            the DW PCIe slave interface.
          const: dma
        - description:
            PHY/PCS configuration registers. Some platforms can have the
            PCS and PHY CSRs accessible over a dedicated memory mapped
            region, but mainly these registers are indirectly accessible
            either by means of the embedded PHY viewport schema or by some
            platform-specific method.
          const: phy
        - description:
            Outbound iATU-capable memory-region which will be used to access
            the peripheral PCIe devices configuration space.
          const: config
        - description:
            Vendor-specific CSR names. Consider using the generic names above
            for new bindings.
          oneOf:
            - description: See native 'elbi/app' CSR region for details.
              enum: [ apb, mgmt, link, ulreg, appl ]
            - description: See native 'atu' CSR region for details.
              enum: [ atu_dma ]
            - description: Syscon-related CSR regions.
              enum: [ smu, mpu ]
            - description: Tegra234 aperture
              enum: [ ecam ]
    allOf:
      - contains:
          const: dbi
      - contains:
          const: config

  interrupts:
    description:
      DWC PCIe Root Port/Complex specific IRQ signals. At least MSI interrupt
      signal is supposed to be specified for the host controller.
    minItems: 1
    maxItems: 26

  interrupt-names:
    minItems: 1
    maxItems: 26
    items:
      oneOf:
        - description:
            Controller request to read or write virtual product data
            from/to the VPD capability registers.
          const: vpd
        - description:
            Link Equalization Request flag is set in the Link Status 2
            register (applicable if the corresponding IRQ is enabled in
            the Link Control 3 register).
          const: l_eq
        - description:
            Indicates that the eDMA Tx/Rx transfer is complete or that an
            error has occurred on the corresponding channel. eDMA can have
            eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
            to 16 IRQ signals all together. Write eDMA channels shall go
            first in the ordered row as per default edma_int[*] bus setup.
          pattern: '^dma([0-9]|1[0-5])?$'
        - description:
            PCIe protocol correctable error or a Data Path protection
            correctable error is detected by the automotive/safety
            feature.
          const: sft_ce
        - description:
            Indicates that the internal safety mechanism has detected an
            uncorrectable error.
          const: sft_ue
        - description:
            Application-specific IRQ raised depending on the vendor-specific
            events basis.
          const: app
        - description:
            DSP AXI MSI Interrupt detected. It gets de-asserted when there is
            no more MSI interrupt pending. The interrupt is relevant to the
            iMSI-RX - Integrated MSI Receiver (AXI bridge).
          const: msi
        - description:
            Legacy A/B/C/D interrupt signal. Basically it's triggered by
            receiving a Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message
            from the downstream device.
          pattern: "^int(a|b|c|d)$"
        - description:
            Error condition detected and a flag is set in the Root Error Status
            register of the AER capability. It's asserted when the RC
            internally generated an error or an error message is received by
            the RC.
          const: aer
        - description:
            PME message is received by the port. That means having the PME
            status bit set in the Root Status register (the event is
            supposed to be unmasked in the Root Control register).
          const: pme
        - description:
            Hot-plug event is detected. That is a bit has been set in the
            Slot Status register and the corresponding event is enabled in
            the Slot Control register.
          const: hp
        - description:
            Link Autonomous Bandwidth Status flag has been set in the Link
            Status register (the event is supposed to be unmasked in the
            Link Control register).
          const: bw_au
        - description:
            Bandwidth Management Status flag has been set in the Link
            Status register (the event is supposed to be unmasked in the
            Link Control register).
          const: bw_mg
        - description:
            Vendor-specific IRQ names. Consider using the generic names above
            for new bindings.
          oneOf:
            - description: See native "app" IRQ for details
              enum: [ intr ]
    allOf:
      - contains:
          const: msi

additionalProperties: true

required:
  - compatible
  - reg
  - reg-names

examples:
  - |
    pcie@dfc00000 {
      compatible = "snps,dw-pcie";
      device_type = "pci";
      reg = <0xdfc00000 0x0001000>, /* IP registers */
            <0xd0000000 0x0002000>; /* Configuration space */
      reg-names = "dbi", "config";
      #address-cells = <3>;
      #size-cells = <2>;
      ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
               <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
      bus-range = <0x0 0xff>;

      interrupts = <25>, <24>;
      interrupt-names = "msi", "hp";
      #interrupt-cells = <1>;

      reset-gpios = <&port0 0 1>;

      phys = <&pcie_phy>;
      phy-names = "pcie";

      num-lanes = <1>;
      max-link-speed = <3>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier PCIe endpoint controller

description: |
  UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
  PCI core. It shares common features with the PCIe DesignWare core and
  inherits common properties defined in
  Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

allOf:
  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#

properties:
  compatible:
    enum:
      - socionext,uniphier-pro5-pcie-ep
      - socionext,uniphier-nx1-pcie-ep

  reg:
    minItems: 4
    maxItems: 5

  reg-names:
    oneOf:
      - items:
          - const: dbi
          - const: dbi2
          - const: link
          - const: addr_space
      - items:
          - const: dbi
          - const: dbi2
          - const: link
          - const: addr_space
          - const: atu

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    oneOf:
      - items:              # for Pro5
          - const: gio
          - const: link
      - const: link         # for NX1

  resets:
    minItems: 1
    maxItems: 2

  reset-names:
    oneOf:
      - items:              # for Pro5
          - const: gio
          - const: link
      - const: link         # for NX1

  num-ib-windows:
    const: 16

  num-ob-windows:
    const: 16

  num-lanes: true

  phys:
    maxItems: 1

  phy-names:
    const: pcie-phy

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - resets
  - reset-names

unevaluatedProperties: false

examples:
  - |
    pcie_ep: pcie-ep@66000000 {
        compatible = "socionext,uniphier-pro5-pcie-ep";
        reg-names = "dbi", "dbi2", "link", "addr_space";
        reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
              <0x66010000 0x10000>, <0x67000000 0x400000>;
        clock-names = "gio", "link";
        clocks = <&sys_clk 12>, <&sys_clk 24>;
        reset-names = "gio", "link";
        resets = <&sys_rst 12>, <&sys_rst 24>;
        num-ib-windows = <16>;
        num-ob-windows = <16>;
        num-lanes = <4>;
        phy-names = "pcie-phy";
        phys = <&pcie_phy>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier PCIe host controller

description: |
  UniPhier PCIe host controller is based on the Synopsys DesignWare
  PCI core. It shares common features with the PCIe DesignWare core and
  inherits common properties defined in
  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    enum:
      - socionext,uniphier-pcie

  reg:
    minItems: 3
    maxItems: 4

  reg-names:
    minItems: 3
    items:
      - const: dbi
      - const: link
      - const: config
      - const: atu

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  num-viewport: true

  num-lanes: true

  phys:
    maxItems: 1

  phy-names:
    const: pcie-phy

  interrupt-controller:
    type: object
    additionalProperties: false

    properties:
      interrupt-controller: true

      '#interrupt-cells':
        const: 1

      interrupts:
        maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - resets

unevaluatedProperties: false

examples:
  - |
    bus {
        gic: interrupt-controller {
            interrupt-controller;
            #interrupt-cells = <3>;
        };
    };

    pcie: pcie@66000000 {
        compatible = "socionext,uniphier-pcie";
        reg-names = "dbi", "link", "config";
        reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>;
        #address-cells = <3>;
        #size-cells = <2>;
        clocks = <&sys_clk 24>;
        resets = <&sys_rst 24>;
        num-lanes = <1>;
        num-viewport = <1>;
        bus-range = <0x0 0xff>;
        device_type = "pci";
        ranges = <0x81000000 0 0x00000000  0x2ffe0000  0 0x00010000>,
                 <0x82000000 0 0x00000000  0x20000000  0 0x0ffe0000>;
        phy-names = "pcie-phy";
        phys = <&pcie_phy>;
        #interrupt-cells = <1>;
        interrupt-names = "dma", "msi";
        interrupt-parent = <&gic>;
        interrupts = <0 224 4>, <0 225 4>;
        interrupt-map-mask = <0 0 0  7>;
        interrupt-map = <0 0 0  1  &pcie_intc 0>,
                        <0 0 0  2  &pcie_intc 1>,
                        <0 0 0  3  &pcie_intc 2>,
                        <0 0 0  4  &pcie_intc 3>;

        pcie_intc: interrupt-controller {
            interrupt-controller;
            #interrupt-cells = <1>;
            interrupt-parent = <&gic>;
            interrupts = <0 226 4>;
        };
    };


code:
SPEAr13XX PCIe DT detail:
================================

SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
controller.

Required properties:
- compatible	    : should be "st,spear1340-pcie", "snps,dw-pcie".
- phys		    : phandle to PHY node associated with PCIe controller
- phy-names	    : must be "pcie-phy"
- All other definitions as per generic PCI bindings

 Optional properties:
- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI AM65 PCI Endpoint

maintainers:
  - Kishon Vijay Abraham I <kishon@ti.com>

allOf:
  - $ref: pci-ep.yaml#

properties:
  compatible:
    enum:
      - ti,am654-pcie-ep

  reg:
    maxItems: 4

  reg-names:
    items:
      - const: app
      - const: dbics
      - const: addr_space
      - const: atu

  power-domains:
    maxItems: 1

  ti,syscon-pcie-mode:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to the SYSCON entry
          - description: pcie_ctrl register offset within SYSCON
    description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.

  interrupts:
    minItems: 1

  dma-coherent: true

required:
  - compatible
  - reg
  - reg-names
  - max-link-speed
  - power-domains
  - ti,syscon-pcie-mode
  - dma-coherent

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    pcie0_ep: pcie-ep@5500000 {
        compatible = "ti,am654-pcie-ep";
        reg =  <0x5500000 0x1000>,
               <0x5501000 0x1000>,
               <0x10000000 0x8000000>,
               <0x5506000 0x1000>;
        reg-names = "app", "dbics", "addr_space", "atu";
        power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
        ti,syscon-pcie-mode = <&scm_conf 0x4060>;
        max-link-speed = <2>;
        dma-coherent;
        interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI AM65 PCI Host

maintainers:
  - Kishon Vijay Abraham I <kishon@ti.com>

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

properties:
  compatible:
    enum:
      - ti,am654-pcie-rc
      - ti,keystone-pcie

  reg:
    maxItems: 4

  reg-names:
    items:
      - const: app
      - const: dbics
      - const: config
      - const: atu

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  ti,syscon-pcie-id:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to the SYSCON entry
          - description: pcie_device_id register offset within SYSCON
    description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID

  ti,syscon-pcie-mode:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to the SYSCON entry
          - description: pcie_ctrl register offset within SYSCON
    description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.

  msi-map: true

  dma-coherent: true

required:
  - compatible
  - reg
  - reg-names
  - max-link-speed
  - ti,syscon-pcie-id
  - ti,syscon-pcie-mode
  - ranges

if:
  properties:
    compatible:
      enum:
        - ti,am654-pcie-rc
then:
  required:
    - dma-coherent
    - power-domains
    - msi-map

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    pcie0_rc: pcie@5500000 {
        compatible = "ti,am654-pcie-rc";
        reg =  <0x5500000 0x1000>,
               <0x5501000 0x1000>,
               <0x10000000 0x2000>,
               <0x5506000 0x1000>;
        reg-names = "app", "dbics", "config", "atu";
        power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
        #address-cells = <3>;
        #size-cells = <2>;
        ranges = <0x81000000 0 0          0x10020000 0 0x00010000>,
                 <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
        ti,syscon-pcie-id = <&scm_conf 0x0210>;
        ti,syscon-pcie-mode = <&scm_conf 0x4060>;
        bus-range = <0x0 0xff>;
        max-link-speed = <2>;
        dma-coherent;
        interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
        msi-map = <0x0 &gic_its 0x0 0x10000>;
        device_type = "pci";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: TI J721E PCI EP (PCIe Wrapper)

maintainers:
  - Kishon Vijay Abraham I <kishon@ti.com>

allOf:
  - $ref: "cdns-pcie-ep.yaml#"

properties:
  compatible:
    oneOf:
      - const: ti,j721e-pcie-ep
      - description: PCIe EP controller in AM64
        items:
          - const: ti,am64-pcie-ep
          - const: ti,j721e-pcie-ep
      - description: PCIe EP controller in J7200
        items:
          - const: ti,j7200-pcie-ep
          - const: ti,j721e-pcie-ep

  reg:
    maxItems: 4

  reg-names:
    items:
      - const: intd_cfg
      - const: user_cfg
      - const: reg
      - const: mem

  ti,syscon-pcie-ctrl:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to the SYSCON entry
          - description: pcie_ctrl register offset within SYSCON
    description: Specifier for configuring PCIe mode and link speed.

  power-domains:
    maxItems: 1

  clocks:
    maxItems: 1
    description: clock-specifier to represent input to the PCIe

  clock-names:
    items:
      - const: fck

  dma-coherent:
    description: Indicates that the PCIe IP block can ensure the coherency

  interrupts:
    maxItems: 1

  interrupt-names:
    items:
      - const: link_state

required:
  - compatible
  - reg
  - reg-names
  - ti,syscon-pcie-ctrl
  - max-link-speed
  - num-lanes
  - power-domains
  - clocks
  - clock-names
  - max-functions
  - phys
  - phy-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie0_ep: pcie-ep@d000000 {
           compatible = "ti,j721e-pcie-ep";
           reg = <0x00 0x02900000 0x00 0x1000>,
                 <0x00 0x02907000 0x00 0x400>,
                 <0x00 0x0d000000 0x00 0x00800000>,
                 <0x00 0x10000000 0x00 0x08000000>;
           reg-names = "intd_cfg", "user_cfg", "reg", "mem";
           ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
           max-link-speed = <3>;
           num-lanes = <2>;
           power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
           clocks = <&k3_clks 239 1>;
           clock-names = "fck";
           max-functions = /bits/ 8 <6>;
           dma-coherent;
           phys = <&serdes0_pcie_link>;
           phy-names = "pcie-phy";
       };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: TI J721E PCI Host (PCIe Wrapper)

maintainers:
  - Kishon Vijay Abraham I <kishon@ti.com>

allOf:
  - $ref: "cdns-pcie-host.yaml#"

properties:
  compatible:
    oneOf:
      - const: ti,j721e-pcie-host
      - description: PCIe controller in AM64
        items:
          - const: ti,am64-pcie-host
          - const: ti,j721e-pcie-host
      - description: PCIe controller in J7200
        items:
          - const: ti,j7200-pcie-host
          - const: ti,j721e-pcie-host

  reg:
    maxItems: 4

  reg-names:
    items:
      - const: intd_cfg
      - const: user_cfg
      - const: reg
      - const: cfg

  ti,syscon-pcie-ctrl:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to the SYSCON entry
          - description: pcie_ctrl register offset within SYSCON
    description: Specifier for configuring PCIe mode and link speed.

  power-domains:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2
    description: |+
      clock-specifier to represent input to the PCIe for 1 item.
      2nd item if present represents reference clock to the connector.

  clock-names:
    minItems: 1
    items:
      - const: fck
      - const: pcie_refclk

  dma-coherent: true

  vendor-id:
    const: 0x104c

  device-id:
    oneOf:
      - items:
          - const: 0xb00d
      - items:
          - const: 0xb00f
      - items:
          - const: 0xb010
      - items:
          - const: 0xb013

  msi-map: true

  interrupts:
    maxItems: 1

  interrupt-names:
    items:
      - const: link_state

  interrupt-controller:
    type: object
    additionalProperties: false

    properties:
      interrupt-controller: true

      '#interrupt-cells':
        const: 1

      interrupts:
        maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - ti,syscon-pcie-ctrl
  - max-link-speed
  - num-lanes
  - power-domains
  - clocks
  - clock-names
  - vendor-id
  - device-id
  - msi-map
  - dma-ranges
  - ranges
  - reset-gpios
  - phys
  - phy-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/soc/ti,sci_pm_domain.h>
    #include <dt-bindings/gpio/gpio.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie0_rc: pcie@2900000 {
            compatible = "ti,j721e-pcie-host";
            reg = <0x00 0x02900000 0x00 0x1000>,
                  <0x00 0x02907000 0x00 0x400>,
                  <0x00 0x0d000000 0x00 0x00800000>,
                  <0x00 0x10000000 0x00 0x00001000>;
            reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
            max-link-speed = <3>;
            num-lanes = <2>;
            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
            clocks = <&k3_clks 239 1>;
            clock-names = "fck";
            device_type = "pci";
            #address-cells = <3>;
            #size-cells = <2>;
            bus-range = <0x0 0xf>;
            vendor-id = <0x104c>;
            device-id = <0xb00d>;
            msi-map = <0x0 &gic_its 0x0 0x10000>;
            dma-coherent;
            reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
            phys = <&serdes0_pcie_link>;
            phy-names = "pcie-phy";
            ranges = <0x01000000 0x0 0x10001000  0x00 0x10001000  0x0 0x0010000>,
                     <0x02000000 0x0 0x10011000  0x00 0x10011000  0x0 0x7fef000>;
            dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
        };
    };


code:
TI PCI Controllers

PCIe DesignWare Controller
 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
	       Should be "ti,dra7-pcie-ep" for EP (deprecated)
	       Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
	       Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
	       Should be "ti,dra726-pcie-rc" for dra72x in RC mode
	       Should be "ti,dra726-pcie-ep" for dra72x in EP mode
 - phys : list of PHY specifiers (used by generic PHY framework)
 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
	       number of PHYs as specified in *phys* property.
 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
	       where <X> is the instance number of the pcie from the HW spec.
 - num-lanes as specified in ../snps,dw-pcie.yaml
 - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
			module and the register offset to specify lane
			selection.

HOST MODE
=========
 - reg : Two register ranges as listed in the reg-names property
 - reg-names : The first entry must be "ti-conf" for the TI-specific registers
	       The second entry must be "rc-dbics" for the DesignWare PCIe
	       registers
	       The third entry must be "config" for the PCIe configuration space
 - interrupts : Two interrupt entries must be specified. The first one is for
		main interrupt line and the second for MSI interrupt line.
 - #address-cells,
   #size-cells,
   #interrupt-cells,
   device_type,
   ranges,
   interrupt-map-mask,
   interrupt-map : as specified in ../snps,dw-pcie.yaml
 - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
			       should contain the register offset within syscon
			       and the 2nd argument should contain the bit field
			       for setting the bit to enable unaligned
			       access.

DEVICE MODE
===========
 - reg : Four register ranges as listed in the reg-names property
 - reg-names : "ti-conf" for the TI-specific registers
	       "ep_dbics" for the standard configuration registers as
		they are locally accessed within the DIF CS space
	       "ep_dbics2" for the standard configuration registers as
		they are locally accessed within the DIF CS2 space
	       "addr_space" used to map remote RC address space
 - interrupts : one interrupt entries must be specified for main interrupt.
 - num-ib-windows : number of inbound address translation windows
 - num-ob-windows : number of outbound address translation windows
 - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
			       should contain the register offset within syscon
			       and the 2nd argument should contain the bit field
			       for setting the bit to enable unaligned
			       access.

Optional Property:
 - gpios : Should be added if a GPIO line is required to drive PERST# line

NOTE: Two DT nodes may be added for each PCI controller; one for host
mode and another for device mode. So in order for PCI to
work in host mode, EP mode DT node should be disabled and in order to PCI to
work in EP mode, host mode DT node should be disabled. Host mode and EP
mode are mutually exclusive.

Example:
axi {
	compatible = "simple-bus";
	#size-cells = <1>;
	#address-cells = <1>;
	ranges = <0x51000000 0x51000000 0x3000
		  0x0	     0x20000000 0x10000000>;
	pcie@51000000 {
		compatible = "ti,dra7-pcie";
		reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
		reg-names = "rc_dbics", "ti_conf", "config";
		interrupts = <0 232 0x4>, <0 233 0x4>;
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x81000000 0 0          0x03000 0 0x00010000
			  0x82000000 0 0x20013000 0x13000 0 0xffed000>;
		#interrupt-cells = <1>;
		num-lanes = <1>;
		ti,hwmods = "pcie1";
		phys = <&pcie1_phy>;
		phy-names = "pcie-phy0";
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc 1>,
				<0 0 0 2 &pcie_intc 2>,
				<0 0 0 3 &pcie_intc 3>,
				<0 0 0 4 &pcie_intc 4>;
		pcie_intc: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Toshiba Visconti5 SoC PCIe Host Controller

maintainers:
  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

description:
  Toshiba Visconti5 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP.

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    const: toshiba,visconti-pcie

  reg:
    items:
      - description: Data Bus Interface (DBI) registers.
      - description: PCIe configuration space region.
      - description: Visconti specific additional registers.
      - description: Visconti specific SMU registers
      - description: Visconti specific memory protection unit registers (MPU)

  reg-names:
    items:
      - const: dbi
      - const: config
      - const: ulreg
      - const: smu
      - const: mpu

  interrupts:
    maxItems: 2

  clocks:
    items:
      - description: PCIe reference clock
      - description: PCIe system clock
      - description: Auxiliary clock

  clock-names:
    items:
      - const: ref
      - const: core
      - const: aux

  num-lanes:
    const: 2

required:
  - reg
  - reg-names
  - interrupts
  - "#interrupt-cells"
  - interrupt-map
  - interrupt-map-mask
  - num-lanes
  - clocks
  - clock-names
  - max-link-speed

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie: pcie@28400000 {
            compatible = "toshiba,visconti-pcie";
            reg = <0x0 0x28400000 0x0 0x00400000>,
                  <0x0 0x70000000 0x0 0x10000000>,
                  <0x0 0x28050000 0x0 0x00010000>,
                  <0x0 0x24200000 0x0 0x00002000>,
                  <0x0 0x24162000 0x0 0x00001000>;
            reg-names  = "dbi", "config", "ulreg", "smu", "mpu";
            device_type = "pci";
            bus-range = <0x00 0xff>;
            num-lanes = <2>;
            num-viewport = <8>;

            #address-cells = <3>;
            #size-cells = <2>;
            #interrupt-cells = <1>;
            ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000>,
                     <0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
            interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "msi", "intr";
            interrupt-map-mask = <0 0 0 7>;
            interrupt-map =
                <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
                 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
                 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
                 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&extclk100mhz>, <&clk600mhz>, <&clk25mhz>;
            clock-names = "ref", "core", "aux";
            max-link-speed = <2>;
        };
    };
...


code:
V3 Semiconductor V360 EPC PCI bridge

This bridge is found in the ARM Integrator/AP (Application Platform)

Required properties:
- compatible: should be one of:
  "v3,v360epc-pci"
  "arm,integrator-ap-pci", "v3,v360epc-pci"
- reg: should contain two register areas:
  first the base address of the V3 host bridge controller, 64KB
  second the configuration area register space, 16MB
- interrupts: should contain a reference to the V3 error interrupt
  as routed on the system.
- bus-range: see pci.txt
- ranges: this follows the standard PCI bindings in the IEEE Std
  1275-1994 (see pci.txt) with the following restriction:
  - The non-prefetchable and prefetchable memory windows must
    each be exactly 256MB (0x10000000) in size.
  - The prefetchable memory window must be immediately adjacent
    to the non-prefetcable memory window
- dma-ranges: three ranges for the inbound memory region. The ranges must
  be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB,
  64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked
  as pre-fetchable. Two ranges are supported by the hardware.

Integrator-specific required properties:
- syscon: should contain a link to the syscon device node, since
  on the Integrator, some registers in the syscon are required to
  operate the V3 host bridge.

Example:

pci: pciv3@62000000 {
	compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
	#interrupt-cells = <1>;
	#size-cells = <2>;
	#address-cells = <3>;
	reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
	interrupt-parent = <&pic>;
	interrupts = <17>; /* Bus error IRQ */
	clocks = <&pciclk>;
	bus-range = <0x00 0xff>;
	ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
		0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
		0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
		0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
		0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
		0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
	dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
		0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
		0x02000000 0 0x80000000 /* Core module alias memory */
		0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
	interrupt-map-mask = <0xf800 0 0 0x7>;
	interrupt-map = <
	/* IDSEL 9 */
	0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
	0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
	0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
	0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
	/* IDSEL 10 */
	0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
	0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
	0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
	0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
	/* IDSEL 11 */
	0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
	0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
	0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
	0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
	/* IDSEL 12 */
	0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
	0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
	0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
	0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
	>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/versatile.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Versatile Platform Baseboard PCI interface

maintainers:
  - Rob Herring <robh@kernel.org>

description: |+
  PCI host controller found on the ARM Versatile PB board's FPGA.

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

properties:
  compatible:
    const: arm,versatile-pci

  reg:
    items:
      - description: Versatile-specific registers
      - description: Self Config space
      - description: Config space

  ranges:
    maxItems: 3

  "#interrupt-cells": true

  interrupt-map:
    maxItems: 16

  interrupt-map-mask:
    items:
      - const: 0x1800
      - const: 0
      - const: 0
      - const: 7

required:
  - compatible
  - reg
  - ranges
  - "#interrupt-cells"
  - interrupt-map
  - interrupt-map-mask

unevaluatedProperties: false

examples:
  - |
    pci@10001000 {
      compatible = "arm,versatile-pci";
      device_type = "pci";
      reg = <0x10001000 0x1000>,
            <0x41000000 0x10000>,
            <0x42000000 0x100000>;
      bus-range = <0 0xff>;
      #address-cells = <3>;
      #size-cells = <2>;
      #interrupt-cells = <1>;

      ranges =
          <0x01000000 0 0x00000000 0x43000000 0 0x00010000>,  /* downstream I/O */
          <0x02000000 0 0x50000000 0x50000000 0 0x10000000>,  /* non-prefetchable memory */
          <0x42000000 0 0x60000000 0x60000000 0 0x10000000>;  /* prefetchable memory */

      interrupt-map-mask = <0x1800 0 0 7>;
      interrupt-map = <0x1800 0 0 1 &sic 28>,
          <0x1800 0 0 2 &sic 29>,
          <0x1800 0 0 3 &sic 30>,
          <0x1800 0 0 4 &sic 27>,

          <0x1000 0 0 1 &sic 27>,
          <0x1000 0 0 2 &sic 28>,
          <0x1000 0 0 3 &sic 29>,
          <0x1000 0 0 4 &sic 30>,

          <0x0800 0 0 1 &sic 30>,
          <0x0800 0 0 2 &sic 27>,
          <0x0800 0 0 3 &sic 28>,
          <0x0800 0 0 4 &sic 29>,

          <0x0000 0 0 1 &sic 29>,
          <0x0000 0 0 2 &sic 30>,
          <0x0000 0 0 3 &sic 27>,
          <0x0000 0 0 4 &sic 28>;
    };

...


code:
* AppliedMicro X-Gene v1 PCIe MSI controller

Required properties:

- compatible: should be "apm,xgene1-msi" to identify
	      X-Gene v1 PCIe MSI controller block.
- msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
- reg: physical base address (0x79000000) and length (0x900000) for controller
       registers. These registers include the MSI termination address and data
       registers as well as the MSI interrupt status registers.
- reg-names: not required
- interrupts: A list of 16 interrupt outputs of the controller, starting from
	      interrupt number 0x10 to 0x1f.
- interrupt-names: not required

Each PCIe node needs to have property msi-parent that points to an MSI
controller node

Examples:

SoC DTSI:

	+ MSI node:
	msi@79000000 {
		compatible = "apm,xgene1-msi";
		msi-controller;
		reg = <0x00 0x79000000 0x0 0x900000>;
		interrupts = 	<0x0 0x10 0x4>
				<0x0 0x11 0x4>
				<0x0 0x12 0x4>
				<0x0 0x13 0x4>
				<0x0 0x14 0x4>
				<0x0 0x15 0x4>
				<0x0 0x16 0x4>
				<0x0 0x17 0x4>
				<0x0 0x18 0x4>
				<0x0 0x19 0x4>
				<0x0 0x1a 0x4>
				<0x0 0x1b 0x4>
				<0x0 0x1c 0x4>
				<0x0 0x1d 0x4>
				<0x0 0x1e 0x4>
				<0x0 0x1f 0x4>;
	};

	+ PCIe controller node with msi-parent property pointing to MSI node:
	pcie0: pcie@1f2b0000 {
		device_type = "pci";
		compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
			0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
		reg-names = "csr", "cfg";
		ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
			  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
		dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
			      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
		interrupt-map-mask = <0x0 0x0 0x0 0x7>;
		interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
				 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
				 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
				 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
		dma-coherent;
		clocks = <&pcie0clk 0>;
		msi-parent= <&msi>;
	};


code:
* AppliedMicro X-Gene PCIe interface

Required properties:
- device_type: set to "pci"
- compatible: should contain "apm,xgene-pcie" to identify the core.
- reg: A list of physical base address and length for each set of controller
       registers. Must contain an entry for each entry in the reg-names
       property.
- reg-names: Must include the following entries:
  "csr": controller configuration registers.
  "cfg": PCIe configuration space registers.
- #address-cells: set to <3>
- #size-cells: set to <2>
- ranges: ranges for the outbound memory, I/O regions.
- dma-ranges: ranges for the inbound memory regions.
- #interrupt-cells: set to <1>
- interrupt-map-mask and interrupt-map: standard PCI properties
	to define the mapping of the PCIe interface to interrupt
	numbers.
- clocks: from common clock binding: handle to pci clock.

Optional properties:
- status: Either "ok" or "disabled".
- dma-coherent: Present if DMA operations are coherent

Example:

	pcie0: pcie@1f2b0000 {
		status = "disabled";
		device_type = "pci";
		compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
			0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
		reg-names = "csr", "cfg";
		ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
			  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
		dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
			      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
		interrupt-map-mask = <0x0 0x0 0x0 0x7>;
		interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
				 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
				 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
				 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
		dma-coherent;
		clocks = <&pcie0clk 0>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: CPM Host Controller device tree for Xilinx Versal SoCs

maintainers:
  - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

properties:
  compatible:
    enum:
      - xlnx,versal-cpm-host-1.00
      - xlnx,versal-cpm5-host

  reg:
    items:
      - description: CPM system level control and status registers.
      - description: Configuration space region and bridge registers.
      - description: CPM5 control and status registers.
    minItems: 2

  reg-names:
    items:
      - const: cpm_slcr
      - const: cfg
      - const: cpm_csr
    minItems: 2

  interrupts:
    maxItems: 1

  msi-map:
    description:
      Maps a Requester ID to an MSI controller and associated MSI sideband data.

  ranges:
    maxItems: 2

  "#interrupt-cells":
    const: 1

  interrupt-controller:
    description: Interrupt controller node for handling legacy PCI interrupts.
    type: object
    properties:
      "#address-cells":
        const: 0
      "#interrupt-cells":
        const: 1
      "interrupt-controller": true
    additionalProperties: false

required:
  - reg
  - reg-names
  - "#interrupt-cells"
  - interrupts
  - interrupt-map
  - interrupt-map-mask
  - bus-range
  - msi-map
  - interrupt-controller

unevaluatedProperties: false

examples:
  - |

    versal {
               #address-cells = <2>;
               #size-cells = <2>;
               cpm_pcie: pcie@fca10000 {
                       compatible = "xlnx,versal-cpm-host-1.00";
                       device_type = "pci";
                       #address-cells = <3>;
                       #interrupt-cells = <1>;
                       #size-cells = <2>;
                       interrupts = <0 72 4>;
                       interrupt-parent = <&gic>;
                       interrupt-map-mask = <0 0 0 7>;
                       interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
                                       <0 0 0 2 &pcie_intc_0 1>,
                                       <0 0 0 3 &pcie_intc_0 2>,
                                       <0 0 0 4 &pcie_intc_0 3>;
                       bus-range = <0x00 0xff>;
                       ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
                                <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
                       msi-map = <0x0 &its_gic 0x0 0x10000>;
                       reg = <0x0 0xfca10000 0x0 0x1000>,
                             <0x6 0x00000000 0x0 0x10000000>;
                       reg-names = "cpm_slcr", "cfg";
                       pcie_intc_0: interrupt-controller {
                               #address-cells = <0>;
                               #interrupt-cells = <1>;
                               interrupt-controller;
                       };
               };

               cpm5_pcie: pcie@fcdd0000 {
                       compatible = "xlnx,versal-cpm5-host";
                       device_type = "pci";
                       #address-cells = <3>;
                       #interrupt-cells = <1>;
                       #size-cells = <2>;
                       interrupts = <0 72 4>;
                       interrupt-parent = <&gic>;
                       interrupt-map-mask = <0 0 0 7>;
                       interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
                                       <0 0 0 2 &pcie_intc_1 1>,
                                       <0 0 0 3 &pcie_intc_1 2>,
                                       <0 0 0 4 &pcie_intc_1 3>;
                       bus-range = <0x00 0xff>;
                       ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
                                <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
                       msi-map = <0x0 &its_gic 0x0 0x10000>;
                       reg = <0x00 0xfcdd0000 0x00 0x1000>,
                             <0x06 0x00000000 0x00 0x1000000>,
                             <0x00 0xfce20000 0x00 0x1000000>;
                       reg-names = "cpm_slcr", "cfg", "cpm_csr";

                       pcie_intc_1: interrupt-controller {
                               #address-cells = <0>;
                               #interrupt-cells = <1>;
                               interrupt-controller;
                       };
               };

    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx AXI PCIe Root Port Bridge

maintainers:
  - Thippeswamy Havalige <thippeswamy.havalige@amd.com>

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

properties:
  compatible:
    const: xlnx,axi-pcie-host-1.00.a

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  ranges:
    items:
      - description: |
          ranges for the PCI memory regions (I/O space region is not
          supported by hardware)

  "#interrupt-cells":
    const: 1

  interrupt-controller:
    description: identifies the node as an interrupt controller
    type: object
    properties:
      interrupt-controller: true

      "#address-cells":
        const: 0

      "#interrupt-cells":
        const: 1

    required:
      - interrupt-controller
      - "#address-cells"
      - "#interrupt-cells"

    additionalProperties: false

required:
  - compatible
  - reg
  - ranges
  - interrupts
  - interrupt-map
  - "#interrupt-cells"
  - interrupt-controller

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    pcie@50000000 {
        compatible = "xlnx,axi-pcie-host-1.00.a";
        reg = <0x50000000 0x1000000>;
        #address-cells = <3>;
        #size-cells = <2>;
        #interrupt-cells = <1>;
        device_type = "pci";
        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-map-mask = <0 0 0 7>;
        interrupt-map = <0 0 0 1 &pcie_intc 1>,
                        <0 0 0 2 &pcie_intc 2>,
                        <0 0 0 3 &pcie_intc 3>,
                        <0 0 0 4 &pcie_intc 4>;
        ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>;
        pcie_intc: interrupt-controller {
            interrupt-controller;
            #address-cells = <0>;
            #interrupt-cells = <1>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx NWL PCIe Root Port Bridge

maintainers:
  - Thippeswamy Havalige <thippeswamy.havalige@amd.com>

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#
  - $ref: /schemas/interrupt-controller/msi-controller.yaml#

properties:
  compatible:
    const: xlnx,nwl-pcie-2.11

  reg:
    items:
      - description: PCIe bridge registers location.
      - description: PCIe Controller registers location.
      - description: PCIe Configuration space region.

  reg-names:
    items:
      - const: breg
      - const: pcireg
      - const: cfg

  interrupts:
    items:
      - description: interrupt asserted when miscellaneous interrupt is received
      - description: unused interrupt(dummy)
      - description: interrupt asserted when a legacy interrupt is received
      - description: msi1 interrupt asserted when an MSI is received
      - description: msi0 interrupt asserted when an MSI is received

  interrupt-names:
    items:
      - const: misc
      - const: dummy
      - const: intx
      - const: msi1
      - const: msi0

  interrupt-map-mask:
    items:
      - const: 0
      - const: 0
      - const: 0
      - const: 7

  "#interrupt-cells":
    const: 1

  msi-parent:
    description: MSI controller the device is capable of using.

  interrupt-map:
    maxItems: 4

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

  dma-coherent:
    description: optional, only needed if DMA operations are coherent.

  clocks:
    maxItems: 1
    description: optional, input clock specifier.

  legacy-interrupt-controller:
    description: Interrupt controller node for handling legacy PCI interrupts.
    type: object
    properties:
      "#address-cells":
        const: 0

      "#interrupt-cells":
        const: 1

      "interrupt-controller": true

    required:
      - "#address-cells"
      - "#interrupt-cells"
      - interrupt-controller

    additionalProperties: false

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - "#interrupt-cells"
  - interrupt-map
  - interrupt-map-mask
  - msi-controller
  - power-domains

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/xlnx-zynqmp-power.h>
    soc {
        #address-cells = <2>;
        #size-cells = <2>;
        nwl_pcie: pcie@fd0e0000 {
            compatible = "xlnx,nwl-pcie-2.11";
            reg = <0x0 0xfd0e0000 0x0 0x1000>,
                  <0x0 0xfd480000 0x0 0x1000>,
                  <0x80 0x00000000 0x0 0x1000000>;
            reg-names = "breg", "pcireg", "cfg";
            ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
                     <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
            #address-cells = <3>;
            #size-cells = <2>;
            #interrupt-cells = <1>;
            msi-controller;
            device_type = "pci";
            interrupt-parent = <&gic>;
            interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "misc", "dummy", "intx", "msi1", "msi0";
            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
            interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
                            <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
                            <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
                            <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
            msi-parent = <&nwl_pcie>;
            power-domains = <&zynqmp_firmware PD_PCIE>;
            iommus = <&smmu 0x4d0>;
            pcie_intc: legacy-interrupt-controller {
                interrupt-controller;
                #address-cells = <0>;
                #interrupt-cells = <1>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/peci/peci-aspeed.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Aspeed PECI Bus

maintainers:
  - Iwona Winiarska <iwona.winiarska@intel.com>
  - Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>

allOf:
  - $ref: peci-controller.yaml#

properties:
  compatible:
    enum:
      - aspeed,ast2400-peci
      - aspeed,ast2500-peci
      - aspeed,ast2600-peci

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    description:
      Clock source for PECI controller. Should reference the external
      oscillator clock.
    maxItems: 1

  resets:
    maxItems: 1

  cmd-timeout-ms:
    minimum: 1
    maximum: 1000
    default: 1000

  clock-frequency:
    description:
      The desired operation frequency of PECI controller in Hz.
    minimum: 2000
    maximum: 2000000
    default: 1000000

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/ast2600-clock.h>
    peci-controller@1e78b000 {
      compatible = "aspeed,ast2600-peci";
      reg = <0x1e78b000 0x100>;
      interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>;
      resets = <&syscon ASPEED_RESET_PECI>;
      cmd-timeout-ms = <1000>;
      clock-frequency = <1000000>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/peci/peci-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic for PECI

maintainers:
  - Iwona Winiarska <iwona.winiarska@intel.com>

description:
  PECI (Platform Environment Control Interface) is an interface that provides a
  communication channel from Intel processors and chipset components to external
  monitoring or control devices.

properties:
  $nodename:
    pattern: "^peci-controller(@.*)?$"

  cmd-timeout-ms:
    description:
      Command timeout in units of ms.

additionalProperties: true

examples:
  - |
    peci-controller@1e78b000 {
      reg = <0x1e78b000 0x100>;
      cmd-timeout-ms = <500>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic G12 DDR performance monitor

maintainers:
  - Jiucheng Xu <jiucheng.xu@amlogic.com>

description: |
  Amlogic G12 series SoC integrate DDR bandwidth monitor.
  A timer is inside and can generate interrupt when timeout.
  The bandwidth is counted in the timer ISR. Different platform
  has different subset of event format attribute.

properties:
  compatible:
    enum:
      - amlogic,g12a-ddr-pmu
      - amlogic,g12b-ddr-pmu
      - amlogic,sm1-ddr-pmu

  reg:
    items:
      - description: DMC bandwidth register space.
      - description: DMC PLL register space.

  interrupts:
    items:
      - description: The IRQ of the inside timer timeout.

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pmu {
        #address-cells=<2>;
        #size-cells=<2>;

        pmu@ff638000 {
            compatible = "amlogic,g12a-ddr-pmu";
            reg = <0x0 0xff638000 0x0 0x100>,
                  <0x0 0xff638c00 0x0 0x100>;
            interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>;
        };
    };


code:
* APM X-Gene SoC PMU bindings

This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
The following PMU devices are supported:

  L3C			- L3 cache controller
  IOB			- IO bridge
  MCB			- Memory controller bridge
  MC			- Memory controller

The following section describes the SoC PMU DT node binding.

Required properties:
- compatible		: Shall be "apm,xgene-pmu" for revision 1 or
                          "apm,xgene-pmu-v2" for revision 2.
- regmap-csw		: Regmap of the CPU switch fabric (CSW) resource.
- regmap-mcba		: Regmap of the MCB-A (memory bridge) resource.
- regmap-mcbb		: Regmap of the MCB-B (memory bridge) resource.
- reg			: First resource shall be the CPU bus PMU resource.
- interrupts            : Interrupt-specifier for PMU IRQ.

Required properties for L3C subnode:
- compatible		: Shall be "apm,xgene-pmu-l3c".
- reg			: First resource shall be the L3C PMU resource.

Required properties for IOB subnode:
- compatible		: Shall be "apm,xgene-pmu-iob".
- reg			: First resource shall be the IOB PMU resource.

Required properties for MCB subnode:
- compatible		: Shall be "apm,xgene-pmu-mcb".
- reg			: First resource shall be the MCB PMU resource.
- enable-bit-index	: The bit indicates if the according MCB is enabled.

Required properties for MC subnode:
- compatible		: Shall be "apm,xgene-pmu-mc".
- reg			: First resource shall be the MC PMU resource.
- enable-bit-index	: The bit indicates if the according MC is enabled.

Example:
	csw: csw@7e200000 {
		compatible = "apm,xgene-csw", "syscon";
		reg = <0x0 0x7e200000 0x0 0x1000>;
	};

	mcba: mcba@7e700000 {
		compatible = "apm,xgene-mcb", "syscon";
		reg = <0x0 0x7e700000 0x0 0x1000>;
	};

	mcbb: mcbb@7e720000 {
		compatible = "apm,xgene-mcb", "syscon";
		reg = <0x0 0x7e720000 0x0 0x1000>;
	};

	pmu: pmu@78810000 {
		compatible = "apm,xgene-pmu-v2";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		regmap-csw = <&csw>;
		regmap-mcba = <&mcba>;
		regmap-mcbb = <&mcbb>;
		reg = <0x0 0x78810000 0x0 0x1000>;
		interrupts = <0x0 0x22 0x4>;

		pmul3c@7e610000 {
			compatible = "apm,xgene-pmu-l3c";
			reg = <0x0 0x7e610000 0x0 0x1000>;
		};

		pmuiob@7e940000 {
			compatible = "apm,xgene-pmu-iob";
			reg = <0x0 0x7e940000 0x0 0x1000>;
		};

		pmucmcb@7e710000 {
			compatible = "apm,xgene-pmu-mcb";
			reg = <0x0 0x7e710000 0x0 0x1000>;
			enable-bit-index = <0>;
		};

		pmucmcb@7e730000 {
			compatible = "apm,xgene-pmu-mcb";
			reg = <0x0 0x7e730000 0x0 0x1000>;
			enable-bit-index = <1>;
		};

		pmucmc@7e810000 {
			compatible = "apm,xgene-pmu-mc";
			reg = <0x0 0x7e810000 0x0 0x1000>;
			enable-bit-index = <0>;
		};

		pmucmc@7e850000 {
			compatible = "apm,xgene-pmu-mc";
			reg = <0x0 0x7e850000 0x0 0x1000>;
			enable-bit-index = <1>;
		};

		pmucmc@7e890000 {
			compatible = "apm,xgene-pmu-mc";
			reg = <0x0 0x7e890000 0x0 0x1000>;
			enable-bit-index = <2>;
		};

		pmucmc@7e8d0000 {
			compatible = "apm,xgene-pmu-mc";
			reg = <0x0 0x7e8d0000 0x0 0x1000>;
			enable-bit-index = <3>;
		};
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/arm,ccn.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM CCN (Cache Coherent Network) Performance Monitors

maintainers:
  - Robin Murphy <robin.murphy@arm.com>

properties:
  compatible:
    enum:
      - arm,ccn-502
      - arm,ccn-504
      - arm,ccn-508
      - arm,ccn-512

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    ccn@20000000 {
        compatible = "arm,ccn-504";
        reg = <0x20000000 0x1000000>;
        interrupts = <0 181 4>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2020 Arm Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/arm,cmn.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm CMN (Coherent Mesh Network) Performance Monitors

maintainers:
  - Robin Murphy <robin.murphy@arm.com>

properties:
  compatible:
    enum:
      - arm,cmn-600
      - arm,cmn-650
      - arm,cmn-700
      - arm,ci-700

  reg:
    items:
      - description: Physical address of the base (PERIPHBASE) and
          size of the configuration address space.

  interrupts:
    minItems: 1
    items:
      - description: Overflow interrupt for DTC0
      - description: Overflow interrupt for DTC1
      - description: Overflow interrupt for DTC2
      - description: Overflow interrupt for DTC3
    description: One interrupt for each DTC domain implemented must
      be specified, in order. DTC0 is always present.

  arm,root-node:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Offset from PERIPHBASE of CMN-600's configuration
      discovery node (see TRM definition of ROOTNODEBASE). Not
      relevant for newer CMN/CI products.

required:
  - compatible
  - reg
  - interrupts

if:
  properties:
    compatible:
      contains:
        const: arm,cmn-600
then:
  required:
    - arm,root-node

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    pmu@50000000 {
        compatible = "arm,cmn-600";
        reg = <0x50000000 0x4000000>;
        /* 4x2 mesh with one DTC, and CFG node at 0,1,1,0 */
        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
        arm,root-node = <0x104000>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2021 Arm Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)

maintainers:
  - Suzuki K Poulose <suzuki.poulose@arm.com>
  - Robin Murphy <robin.murphy@arm.com>

description:
  ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
  L3 memory system, control logic and external interfaces to form a multicore
  cluster. The PMU enables gathering various statistics on the operation of the
  DSU. The PMU provides independent 32-bit counters that can count any of the
  supported events, along with a 64-bit cycle counter. The PMU is accessed via
  CPU system registers and has no MMIO component.

properties:
  compatible:
    oneOf:
      - const: arm,dsu-pmu
      - items:
          - const: arm,dsu-110-pmu
          - const: arm,dsu-pmu

  interrupts:
    items:
      - description: nCLUSTERPMUIRQ interrupt

  cpus:
    minItems: 1
    maxItems: 12
    description: List of phandles for the CPUs connected to this DSU instance.

required:
  - compatible
  - interrupts
  - cpus

additionalProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm SMMUv3 Performance Monitor Counter Group

maintainers:
  - Will Deacon <will@kernel.org>
  - Robin Murphy <robin.murphy@arm.com>

description: |
  An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
  They are standalone performance monitoring units that support both
  architected and IMPLEMENTATION DEFINED event counters.

properties:
  $nodename:
    pattern: "^pmu@[0-9a-f]*"
  compatible:
    oneOf:
      - items:
          - const: arm,mmu-600-pmcg
          - const: arm,smmu-v3-pmcg
      - const: arm,smmu-v3-pmcg

  reg:
    items:
      - description: Register page 0
      - description: Register page 1, if SMMU_PMCG_CFGR.RELOC_CTRS = 1
    minItems: 1

  interrupts:
    maxItems: 1

  msi-parent: true

required:
  - compatible
  - reg

anyOf:
  - required:
      - interrupts
  - required:
      - msi-parent

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    pmu@2b420000 {
            compatible = "arm,smmu-v3-pmcg";
            reg = <0x2b420000 0x1000>,
                  <0x2b430000 0x1000>;
            interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
            msi-parent = <&its 0xff0000>;
    };

    pmu@2b440000 {
            compatible = "arm,smmu-v3-pmcg";
            reg = <0x2b440000 0x1000>,
                  <0x2b450000 0x1000>;
            interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
            msi-parent = <&its 0xff0000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale(NXP) IMX8 DDR performance monitor

maintainers:
  - Frank Li <frank.li@nxp.com>

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx8-ddr-pmu
          - fsl,imx8m-ddr-pmu
          - fsl,imx8mq-ddr-pmu
          - fsl,imx8mm-ddr-pmu
          - fsl,imx8mn-ddr-pmu
          - fsl,imx8mp-ddr-pmu
      - items:
          - enum:
              - fsl,imx8mm-ddr-pmu
              - fsl,imx8mn-ddr-pmu
              - fsl,imx8mq-ddr-pmu
              - fsl,imx8mp-ddr-pmu
          - const: fsl,imx8m-ddr-pmu

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    ddr-pmu@5c020000 {
        compatible = "fsl,imx8-ddr-pmu";
        reg = <0x5c020000 0x10000>;
        interrupt-parent = <&gic>;
        interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell CN10K DDR performance monitor

maintainers:
  - Bharat Bhushan <bbhushan2@marvell.com>

properties:
  compatible:
    items:
      - enum:
          - marvell,cn10k-ddr-pmu

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        pmu@87e1c0000000 {
            compatible = "marvell,cn10k-ddr-pmu";
            reg = <0x87e1 0xc0000000 0x0 0x10000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell CN10K LLC-TAD performance monitor

maintainers:
  - Bhaskara Budiredla <bbudiredla@marvell.com>

description: |
  The Tag-and-Data units (TADs) maintain coherence and contain CN10K
  shared on-chip last level cache (LLC). The tad pmu measures the
  performance of last-level cache. Each tad pmu supports up to eight
  counters.

  The DT setup comprises of number of tad blocks, the sizes of pmu
  regions, tad blocks and overall base address of the HW.

properties:
  compatible:
    const: marvell,cn10k-tad-pmu

  reg:
    maxItems: 1

  marvell,tad-cnt:
    description: specifies the number of tads on the soc
    $ref: /schemas/types.yaml#/definitions/uint32

  marvell,tad-page-size:
    description: specifies the size of each tad page
    $ref: /schemas/types.yaml#/definitions/uint32

  marvell,tad-pmu-page-size:
    description: specifies the size of page that the pmu uses
    $ref: /schemas/types.yaml#/definitions/uint32

required:
  - compatible
  - reg
  - marvell,tad-cnt
  - marvell,tad-page-size
  - marvell,tad-pmu-page-size

additionalProperties: false

examples:
  - |

    tad {
        #address-cells = <2>;
        #size-cells = <2>;

        tad_pmu@80000000 {
            compatible = "marvell,cn10k-tad-pmu";
            reg = <0x87e2 0x80000000 0x0 0x1000>;
            marvell,tad-cnt = <1>;
            marvell,tad-page-size = <0x1000>;
            marvell,tad-pmu-page-size = <0x1000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/spe-pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)

maintainers:
  - Will Deacon <will@kernel.org>

description:
  ARMv8.2 introduces the optional Statistical Profiling Extension for collecting
  performance sample data using an in-memory trace buffer.

properties:
  compatible:
    const: arm,statistical-profiling-extension-v1

  interrupts:
    maxItems: 1
    description: |
      The PPI to signal SPE events. For heterogeneous systems where SPE is only
      supported on a subset of the CPUs, please consult the arm,gic-v3 binding
      for details on describing a PPI partition.

additionalProperties: false

required:
  - compatible
  - interrupts

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    spe-pmu {
        compatible = "arm,statistical-profiling-extension-v1";
        interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
    };