code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/brcm,bcm2835.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: BCM2835/6368 Random number generator

maintainers:
  - Stefan Wahren <stefan.wahren@i2se.com>
  - Florian Fainelli <f.fainelli@gmail.com>
  - Herbert Xu <herbert@gondor.apana.org.au>

properties:
  compatible:
    enum:
      - brcm,bcm2835-rng
      - brcm,bcm-nsp-rng
      - brcm,bcm5301x-rng
      - brcm,bcm6368-rng

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: ipsec

  resets:
    maxItems: 1

  reset-names:
    const: ipsec

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg

if:
  properties:
    compatible:
      enum:
        - brcm,bcm6368-rng
then:
  required:
    - clocks
    - clock-names
    - resets
    - reset-names

additionalProperties: false

examples:
  - |
    rng@7e104000 {
        compatible = "brcm,bcm2835-rng";
        reg = <0x7e104000 0x10>;
        interrupts = <2 29>;
    };

  - |
    rng@18033000 {
        compatible = "brcm,bcm-nsp-rng";
        reg = <0x18033000 0x14>;
    };

  - |
    rng@10004180 {
        compatible = "brcm,bcm6368-rng";
        reg = <0x10004180 0x14>;

        clocks = <&periph_clk 18>;
        clock-names = "ipsec";

        resets = <&periph_rst 4>;
        reset-names = "ipsec";
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/rng/brcm,iproc-rng200.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: HWRNG support for the iproc-rng200 driver

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  compatible:
    enum:
      - brcm,bcm2711-rng200
      - brcm,bcm7211-rng200
      - brcm,bcm7278-rng200
      - brcm,iproc-rng200

  reg:
    maxItems: 1

additionalProperties: false

examples:
  - |
    rng@18032000 {
        compatible = "brcm,iproc-rng200";
        reg = <0x18032000 0x28>;
    };

repo_name: angery/linux


code:
Hisilicon Random Number Generator

Required properties:
- compatible : Should be "hisilicon,hip04-rng" or "hisilicon,hip05-rng"
- reg : Offset and length of the register set of this block

Example:

rng@d1010000 {
	compatible = "hisilicon,hip05-rng";
	reg = <0xd1010000 0x100>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/imx-rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale RNGA/RNGB/RNGC (Random Number Generator Versions A, B and C)

maintainers:
  - Vladimir Zapolskiy <vz@mleia.com>

properties:
  compatible:
    oneOf:
      - const: fsl,imx21-rnga
      - const: fsl,imx25-rngb
      - items:
          - const: fsl,imx31-rnga
          - const: fsl,imx21-rnga
      - items:
          - enum:
              - fsl,imx6sl-rngb
              - fsl,imx6sll-rngb
              - fsl,imx6ull-rngb
          - const: fsl,imx25-rngb
      - const: fsl,imx35-rngc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    rngb@53fb0000 {
        compatible = "fsl,imx25-rngb";
        reg = <0x53fb0000 0x4000>;
        clocks = <&clks 109>;
        interrupts = <22>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/ingenic,rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Bindings for RNG in Ingenic SoCs

maintainers:
  - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

description:
  The Random Number Generator in Ingenic SoCs.

properties:
  compatible:
    enum:
      - ingenic,jz4780-rng
      - ingenic,x1000-rng

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    rng: rng@d8 {
        compatible = "ingenic,jz4780-rng";
        reg = <0xd8 0x8>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/ingenic,trng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Bindings for DTRNG in Ingenic SoCs

maintainers:
  - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

description:
  The True Random Number Generator in Ingenic SoCs.

properties:
  compatible:
    enum:
      - ingenic,x1830-dtrng

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,x1830-cgu.h>

    dtrng: trng@10072000 {
        compatible = "ingenic,x1830-dtrng";
        reg = <0x10072000 0xc>;

        clocks = <&cgu X1830_CLK_DTRNG>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/intel,ixp46x-rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel IXP46x RNG bindings

description: |
  The Intel IXP46x has a random number generator at a fixed physical
  location in memory. Each read is guaranteed to provide a unique
  32 bit random number.

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

properties:
  compatible:
    const: intel,ixp46x-rng

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    rng@70002100 {
      compatible = "intel,ixp46x-rng";
      reg = <0x70002100 4>;
    };


code:
* Microchip PIC32 Random Number Generator

The PIC32 RNG provides a pseudo random number generator which can be seeded by
another true random number generator.

Required properties:
- compatible : should be "microchip,pic32mzda-rng"
- reg : Specifies base physical address and size of the registers.
- clocks: clock phandle.

Example:

	rng: rng@1f8e6000 {
		compatible = "microchip,pic32mzda-rng";
		reg = <0x1f8e6000 0x1000>;
		clocks = <&PBCLK5>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/rng/mtk-rng.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek Random number generator

maintainers:
  - Sean Wang <sean.wang@mediatek.com>

properties:
  $nodename:
    pattern: "^rng@[0-9a-f]+$"

  compatible:
    oneOf:
      - enum:
          - mediatek,mt7623-rng
      - items:
          - enum:
              - mediatek,mt7622-rng
              - mediatek,mt7629-rng
              - mediatek,mt7986-rng
              - mediatek,mt8365-rng
              - mediatek,mt8516-rng
          - const: mediatek,mt7623-rng

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: rng

required:
  - compatible
  - reg
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt2701-clk.h>
    rng: rng@1020f000 {
            compatible = "mediatek,mt7623-rng";
            reg = <0x1020f000 0x1000>;
            clocks = <&infracfg CLK_INFRA_TRNG>;
            clock-names = "rng";
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/nuvoton,npcm-rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Nuvoton NPCM SoC Random Number Generator

maintainers:
  - Avi Fishman <avifishman70@gmail.com>
  - Tomer Maimon <tmaimon77@gmail.com>
  - Tali Perry <tali.perry1@gmail.com>
  - Patrick Venture <venture@google.com>
  - Nancy Yuen <yuenn@google.com>
  - Benjamin Fair <benjaminfair@google.com>

properties:
  compatible:
    enum:
      - nuvoton,npcm750-rng
      - nuvoton,npcm845-rng

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    rng@f000b000 {
        compatible = "nuvoton,npcm750-rng";
        reg = <0xf000b000 0x8>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/omap_rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: OMAP SoC and Inside-Secure HWRNG Module

maintainers:
  - Jayesh Choudhary <j-choudhary@ti.com>

properties:
  compatible:
    enum:
      - ti,omap2-rng
      - ti,omap4-rng
      - inside-secure,safexcel-eip76

  ti,hwmods:
    const: rng
    deprecated: true
    description: Name of the hwmod associated with the RNG module

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: EIP150 gatable clock
      - description: Main gatable clock

  clock-names:
    minItems: 1
    items:
      - const: core
      - const: reg

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - ti,omap4-rng
              - inside-secure,safexcel-eip76

    then:
      required:
        - interrupts

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    /* AM335x */
    rng: rng@48310000 {
            compatible = "ti,omap4-rng";
            ti,hwmods = "rng";
            reg = <0x48310000 0x2000>;
            interrupts = <111>;
    };
  - |
    /* SafeXcel IP-76 */
    trng: rng@f2760000 {
            compatible = "inside-secure,safexcel-eip76";
            reg = <0xf2760000 0x7d>;
            interrupts = <0 59 4>;
            clocks = <&cpm_syscon0 1 25>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/samsung,exynos4-rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC Pseudo Random Number Generator

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - samsung,exynos4-rng                   # for Exynos4210 and Exynos4412
      - samsung,exynos5250-prng               # for Exynos5250+

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: secss

required:
  - compatible
  - reg
  - clock-names
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos4.h>

    rng@10830400 {
        compatible = "samsung,exynos4-rng";
        reg = <0x10830400 0x200>;
        clocks = <&clock CLK_SSS>;
        clock-names = "secss";
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/samsung,exynos5250-trng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC True Random Number Generator

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Łukasz Stelmach <l.stelmach@samsung.com>

properties:
  compatible:
    const: samsung,exynos5250-trng

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: secss

  reg:
    maxItems: 1

required:
  - compatible
  - clocks
  - clock-names
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5250.h>

    rng@10830600 {
        compatible = "samsung,exynos5250-trng";
        reg = <0x10830600 0x100>;
        clocks = <&clock CLK_SSS>;
        clock-names = "secss";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/silex-insight,ba431-rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Silex Insight BA431 RNG bindings

description: |
  The BA431 hardware random number generator is an IP that is FIPS-140-2/3
  certified.

maintainers:
  - Olivier Sobrie <olivier.sobrie@silexinsight.com>

properties:
  compatible:
    const: silex-insight,ba431-rng

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    rng@42800000 {
      compatible = "silex-insight,ba431-rng";
      reg = <0x42800000 0x1000>;
    };

...


code:
HWRNG support for the n2_rng driver

Required properties:
- reg		: base address to sample from
- compatible	: should contain one of the following
	RNG versions:
	- 'SUNW,n2-rng' for Niagara 2 Platform (SUN UltraSPARC T2 CPU)
	- 'SUNW,vf-rng' for Victoria Falls Platform (SUN UltraSPARC T2 Plus CPU)
	- 'SUNW,kt-rng' for Rainbow/Yosemite Falls Platform (SUN SPARC T3/T4), (UltraSPARC KT/Niagara 3 - development names)
	more recent systems (after Oracle acquisition of SUN)
	- 'ORCL,m4-rng' for SPARC T5/M5
	- 'ORCL,m7-rng' for SPARC T7/M7

Examples:
/* linux LDOM on SPARC T5-2 */
Node 0xf029a4f4
	.node:  f029a4f4
	rng-#units:  00000002
	compatible: 'ORCL,m4-rng'
	reg:  0000000e
	name: 'random-number-generator'

/* solaris on SPARC M7-8 */
Node 0xf028c08c
	rng-#units:  00000003
	compatible: 'ORCL,m7-rng'
	reg:  0000000e
	name:  'random-number-generator'

PS: see as well prtconfs.git by DaveM


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/st,rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics Hardware Random Number Generator

maintainers:
  - Patrice Chotard <patrice.chotard@foss.st.com>

properties:
  compatible:
    const: st,rng

  clocks:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - clocks
  - reg

additionalProperties: false

examples:
  - |
    rng@fee80000 {
        compatible = "st,rng";
        reg = <0xfee80000 0x1000>;
        clocks = <&clk_sysin>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/st,stm32-rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 RNG bindings

description: |
  The STM32 hardware random number generator is a simple fixed purpose
  IP and is fully separated from other crypto functions.

maintainers:
  - Lionel Debieve <lionel.debieve@foss.st.com>

properties:
  compatible:
    const: st,stm32-rng

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  clock-error-detect:
    type: boolean
    description: If set enable the clock detection management

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/stm32mp1-clks.h>
    rng@54003000 {
      compatible = "st,stm32-rng";
      reg = <0x54003000 0x400>;
      clocks = <&rcc RNG1_K>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/ti,keystone-rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Keystone SoC Hardware Random Number Generator

maintainers:
  - Nishanth Menon <nm@ti.com>
  - Santosh Shilimkar <ssantosh@kernel.org>

properties:
  compatible:
    const: ti,keystone-rng

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: fck

  reg:
    maxItems: 1

  ti,syscon-sa-cfg:
    $ref: "/schemas/types.yaml#/definitions/phandle"
    description: |
      Phandle to syscon node of the SA configuration registers.  These
      registers are shared between HWRNG and crypto drivers.

required:
  - compatible
  - clocks
  - clock-names
  - reg
  - ti,syscon-sa-cfg

additionalProperties: false

examples:
  - |
    rng@24000 {
        compatible = "ti,keystone-rng";
        ti,syscon-sa-cfg = <&sa_config>;
        clocks = <&clksa>;
        clock-names = "fck";
        reg = <0x24000 0x1000>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/ti,omap-rom-rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: OMAP ROM Random Number Generator

maintainers:
  - Pali Rohár <pali@kernel.org>
  - Tony Lindgren <tony@atomide.com>

description:
  Secure SoCs may provide RNG via secure ROM calls like Nokia N900 does.
  The implementation can depend on the SoC secure ROM used.

properties:
  compatible:
    const: nokia,n900-rom-rng

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: ick

required:
  - compatible
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    rng {
        compatible = "nokia,n900-rom-rng";
        clocks = <&rng_ick>;
        clock-names = "ick";
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/timeriomem_rng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TimerIO Random Number Generator

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    const: timeriomem_rng

  period:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: wait time in microseconds to use between samples

  quality:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0
    description:
      Estimated number of bits of true entropy per 1024 bits read from the rng.
      Defaults to zero which causes the kernel's default quality to be used
      instead.  Note that the default quality is usually zero which disables
      using this rng to automatically fill the kernel's entropy pool.

  reg:
    maxItems: 1
    description:
      Base address to sample from. Currently 'reg' must be at least four bytes
      wide and 32-bit aligned.

required:
  - compatible
  - period
  - reg

additionalProperties: false

examples:
  - |
    rng@44 {
        compatible = "timeriomem_rng";
        reg = <0x44 0x04>;
        period = <1000000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rng/xiphera,xip8001b-trng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xiphera XIP8001B-trng bindings

maintainers:
  - Atte Tommiska <atte.tommiska@xiphera.com>

description: |
  Xiphera FPGA-based true random number generator intellectual property core.

properties:
  compatible:
    const: xiphera,xip8001b-trng

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    rng@43c00000 {
        compatible = "xiphera,xip8001b-trng";
        reg = <0x43c00000 0x10000>;
    };


code:
Abracon ABX80X I2C ultra low power RTC/Alarm chip

The Abracon ABX80X family consist of the ab0801, ab0803, ab0804, ab0805, ab1801,
ab1803, ab1804 and ab1805. The ab0805 is the superset of ab080x and the ab1805
is the superset of ab180x.

Required properties:

 - "compatible": should one of:
        "abracon,abx80x"
        "abracon,ab0801"
        "abracon,ab0803"
        "abracon,ab0804"
        "abracon,ab0805"
        "abracon,ab1801"
        "abracon,ab1803"
        "abracon,ab1804"
        "abracon,ab1805"
        "microcrystal,rv1805"
	Using "abracon,abx80x" will enable chip autodetection.
 - "reg": I2C bus address of the device

Optional properties:

The abx804 and abx805 have a trickle charger that is able to charge the
connected battery or supercap. Both the following properties have to be defined
and valid to enable charging:

 - "abracon,tc-diode": should be "standard" (0.6V) or "schottky" (0.3V)
 - "abracon,tc-resistor": should be <0>, <3>, <6> or <11>. 0 disables the output
                          resistor, the other values are in kOhm.


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/allwinner,sun4i-a10-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 RTC

allOf:
  - $ref: "rtc.yaml#"

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    enum:
      - allwinner,sun4i-a10-rtc
      - allwinner,sun7i-a20-rtc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    rtc: rtc@1c20d00 {
        compatible = "allwinner,sun4i-a10-rtc";
        reg = <0x01c20d00 0x20>;
        interrupts = <24>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/allwinner,sun6i-a31-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 RTC

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#clock-cells":
    const: 1

  compatible:
    oneOf:
      - enum:
          - allwinner,sun6i-a31-rtc
          - allwinner,sun8i-a23-rtc
          - allwinner,sun8i-h3-rtc
          - allwinner,sun8i-r40-rtc
          - allwinner,sun8i-v3-rtc
          - allwinner,sun50i-h5-rtc
          - allwinner,sun50i-h6-rtc
          - allwinner,sun50i-h616-rtc
          - allwinner,sun50i-r329-rtc
      - items:
          - const: allwinner,sun50i-a64-rtc
          - const: allwinner,sun8i-h3-rtc
      - items:
          - const: allwinner,sun20i-d1-rtc
          - const: allwinner,sun50i-r329-rtc

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    items:
      - description: RTC Alarm 0
      - description: RTC Alarm 1

  clocks:
    minItems: 1
    maxItems: 4

  clock-names:
    minItems: 1
    maxItems: 4

  clock-output-names:
    minItems: 1
    maxItems: 3
    description:
      The RTC provides up to three clocks
        - the Low Frequency Oscillator or LOSC, at index 0,
        - the Low Frequency Oscillator External output (X32KFOUT in
          the datasheet), at index 1,
        - the Internal Oscillator, at index 2.

allOf:
  - $ref: "rtc.yaml#"
  - if:
      properties:
        compatible:
          contains:
            const: allwinner,sun6i-a31-rtc

    then:
      properties:
        clock-output-names:
          maxItems: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun8i-a23-rtc
              - allwinner,sun8i-r40-rtc
              - allwinner,sun8i-v3-rtc

    then:
      properties:
        clock-output-names:
          minItems: 2
          maxItems: 2

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun8i-h3-rtc
              - allwinner,sun50i-h5-rtc
              - allwinner,sun50i-h6-rtc

    then:
      properties:
        clock-output-names:
          minItems: 3

  - if:
      properties:
        compatible:
          contains:
            const: allwinner,sun50i-h616-rtc

    then:
      properties:
        clocks:
          items:
            - description: Bus clock for register access
            - description: 24 MHz oscillator
            - description: 32 kHz clock from the CCU

        clock-names:
          items:
            - const: bus
            - const: hosc
            - const: pll-32k

      required:
        - clocks
        - clock-names

  - if:
      properties:
        compatible:
          contains:
            const: allwinner,sun50i-r329-rtc

    then:
      properties:
        clocks:
          minItems: 3
          items:
            - description: Bus clock for register access
            - description: 24 MHz oscillator
            - description: AHB parent for internal SPI clock
            - description: External 32768 Hz oscillator

        clock-names:
          minItems: 3
          items:
            - const: bus
            - const: hosc
            - const: ahb
            - const: ext-osc32k

      required:
        - clocks
        - clock-names

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun8i-r40-rtc
              - allwinner,sun50i-h616-rtc
              - allwinner,sun50i-r329-rtc

    then:
      properties:
        interrupts:
          maxItems: 1

    else:
      properties:
        interrupts:
          minItems: 2

required:
  - "#clock-cells"
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    rtc: rtc@1f00000 {
        compatible = "allwinner,sun6i-a31-rtc";
        reg = <0x01f00000 0x400>;
        interrupts = <0 40 4>, <0 41 4>;
        clock-output-names = "osc32k";
        clocks = <&ext_osc32k>;
        #clock-cells = <1>;
    };

...


code:
* Alphascale asm9260 SoC Real Time Clock

Required properties:
- compatible: Should be "alphascale,asm9260-rtc"
- reg: Physical base address of the controller and length
       of memory mapped region.
- interrupts: IRQ line for the RTC.
- clocks: Reference to the clock entry.
- clock-names: should contain:
  * "ahb" for the SoC RTC clock

Example:
rtc0: rtc@800a0000 {
	compatible = "alphascale,asm9260-rtc";
	reg = <0x800a0000 0x100>;
	clocks = <&acc CLKID_AHB_RTC>;
	clock-names = "ahb";
	interrupts = <2>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/arm,pl031.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm Primecell PL031 Real Time Clock

select:
  properties:
    compatible:
      contains:
        const: arm,pl031
  required:
    - compatible

allOf:
  - $ref: rtc.yaml#

maintainers:
  - Rob Herring <robh@kernel.org>

properties:
  compatible:
    items:
      - const: arm,pl031
      - const: arm,primecell

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    maxItems: 1

  start-year: true

required:
  - compatible
  - reg
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    rtc@10017000 {
        compatible = "arm,pl031", "arm,primecell";
        reg = <0x10017000 0x1000>;
        clocks = <&pclk>;
        clock-names = "apb_pclk";
    };


code:
* Real Time Clock of the Armada 38x/7K/8K SoCs

RTC controller for the Armada 38x, 7K and 8K SoCs

Required properties:
- compatible : Should be one of the following:
	"marvell,armada-380-rtc" for Armada 38x SoC
	"marvell,armada-8k-rtc" for Aramda 7K/8K SoCs
- reg: a list of base address and size pairs, one for each entry in
  reg-names
- reg names: should contain:
  * "rtc" for the RTC registers
  * "rtc-soc" for the SoC related registers and among them the one
    related to the interrupt.
- interrupts: IRQ line for the RTC.

Example:

rtc@a3800 {
	compatible = "marvell,armada-380-rtc";
	reg = <0xa3800 0x20>, <0x184a0 0x0c>;
	reg-names = "rtc", "rtc-soc";
	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/atmel,at91rm9200-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Atmel AT91 RTC

allOf:
  - $ref: "rtc.yaml#"

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

properties:
  compatible:
    enum:
      - atmel,at91rm9200-rtc
      - atmel,at91sam9x5-rtc
      - atmel,sama5d4-rtc
      - atmel,sama5d2-rtc
      - microchip,sam9x60-rtc
      - microchip,sama7g5-rtc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    rtc@fffffe00 {
        compatible = "atmel,at91rm9200-rtc";
        reg = <0xfffffe00 0x100>;
        interrupts = <1 4 7>;
        clocks = <&clk32k>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/atmel,at91sam9260-rtt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Atmel AT91 RTT

allOf:
  - $ref: "rtc.yaml#"

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

properties:
  compatible:
    oneOf:
      - items:
          - const: atmel,at91sam9260-rtt
      - items:
          - const: microchip,sam9x60-rtt
          - const: atmel,at91sam9260-rtt
      - items:
          - const: microchip,sama7g5-rtt
          - const: microchip,sam9x60-rtt
          - const: atmel,at91sam9260-rtt

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  atmel,rtt-rtc-time-reg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to the GPBR node.
          - description: Offset within the GPBR block.
    description:
      Should encode the GPBR register used to store the time base when the
      RTT is used as an RTC. The first cell should point to the GPBR node
      and the second one encodes the offset within the GPBR block (or in
      other words, the GPBR register used to store the time base).

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - atmel,rtt-rtc-time-reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    rtc@fffffd20 {
        compatible = "atmel,at91sam9260-rtt";
        reg = <0xfffffd20 0x10>;
        interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
        clocks = <&clk32k>;
        atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/brcm,brcmstb-waketimer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom STB wake-up Timer

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

description:
  The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
  ability to wake up the system from low-power suspend/standby modes.

allOf:
  - $ref: "rtc.yaml#"

properties:
  compatible:
    const: brcm,brcmstb-waketimer

  reg:
    maxItems: 1

  interrupts:
    description: the TIMER interrupt
    maxItems: 1

  clocks:
    description: clock reference in the 27MHz domain
    maxItems: 1

additionalProperties: false

examples:
  - |
    rtc@f0411580 {
        compatible = "brcm,brcmstb-waketimer";
        reg = <0xf0411580 0x14>;
        interrupts = <0x3>;
        interrupt-parent = <&aon_pm_l2_intc>;
        clocks = <&upg_fixed>;
    };


code:
Cadence Real Time Clock

The Cadence RTC controller with date, time and alarm capabilities.
The alarm may wake the system from low-power state.

Required properties:
- compatible: Should be "cdns,rtc-r109v3"
- reg: Specifies base physical address and size of the register area.
- interrupts: A single interrupt specifier.
- clocks: Must contain two entries:
	- pclk: APB registers clock
	- ref_clk: reference 1Hz or 100Hz clock, depending on IP configuration
	See ../clocks/clock-bindings.txt for details.

Example:
        rtc0: rtc@fd080000 {
        	compatible = "cdns,rtc-r109v3";
        	reg = <0xfd080000 0x1000>;

        	clock-names = "pclk", "ref_clk";
        	clocks = <&sysclock>, <&refclock>;

        	interrupt-parent = <&gic>;
        	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
        };


code:
Motorola CPCAP PMIC RTC
-----------------------

This module is part of the CPCAP. For more details about the whole
chip see Documentation/devicetree/bindings/mfd/motorola-cpcap.txt.

Requires node properties:
- compatible: should contain "motorola,cpcap-rtc"
- interrupts: An interrupt specifier for alarm and 1 Hz irq

Example:

&cpcap {
	cpcap_rtc: rtc {
		compatible = "motorola,cpcap-rtc";
		interrupts = <39 IRQ_TYPE_NONE>, <26 IRQ_TYPE_NONE>;
	};
};


code:
* Dallas DS1390		SPI Serial Real-Time Clock

Required properties:
- compatible: Should contain "dallas,ds1390".
- reg: SPI address for chip

Optional properties:
- trickle-resistor-ohms : Selected resistor for trickle charger
	Values usable for ds1390 are 250, 2000, 4000
	Should be given if trickle charger should be enabled
- trickle-diode-disable : Do not use internal trickle charger diode
	Should be given if internal trickle charger diode should be disabled
Example:
	ds1390: rtc@0 {
		compatible = "dallas,ds1390";
		trickle-resistor-ohms = <250>;
		reg = <0>;
	};


code:
Conexant Digicolor Real Time Clock controller

This binding currently supports the CX92755 SoC.

Required properties:
- compatible: should be "cnxt,cx92755-rtc"
- reg: physical base address of the controller and length of memory mapped
  region.
- interrupts: rtc alarm interrupt

Example:

	rtc@f0000c30 {
		compatible = "cnxt,cx92755-rtc";
		reg = <0xf0000c30 0x18>;
		interrupts = <25>;
	};


code:
EPSON TOYOCOM RTC-7301SF/DG

Required properties:

- compatible: Should be "epson,rtc7301sf" or "epson,rtc7301dg"
- reg: Specifies base physical address and size of the registers.
- interrupts: A single interrupt specifier.

Example:

rtc: rtc@44a00000 {
	compatible = "epson,rtc7301dg";
	reg = <0x44a00000 0x10000>;
	interrupt-parent = <&axi_intc_0>;
	interrupts = <3 2>;
};


code:
Epson RX6110 Real Time Clock
============================

The Epson RX6110 can be used with SPI or I2C busses. The kind of
bus depends on the SPISEL pin and can not be configured via software.

I2C mode
--------

Required properties:
  - compatible: should be: "epson,rx6110"
  - reg : the I2C address of the device for I2C

Example:

	rtc: rtc@32 {
		compatible = "epson,rx6110"
		reg = <0x32>;
	};

SPI mode
--------

Required properties:
  - compatible: should be: "epson,rx6110"
  - reg: chip select number
  - spi-cs-high: RX6110 needs chipselect high
  - spi-cpha: RX6110 works with SPI shifted clock phase
  - spi-cpol: RX6110 works with SPI inverse clock polarity

Example:

	rtc: rtc@3 {
		compatible = "epson,rx6110"
		reg = <3>
		spi-cs-high;
		spi-cpha;
		spi-cpol;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/epson,rx8900.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: EPSON RX8900 / Microcrystal RV8803 Real-Time Clock DT bindings

maintainers:
  - Marek Vasut <marex@denx.de>

allOf:
  - $ref: rtc.yaml#

properties:
  compatible:
    enum:
      - epson,rx8804
      - epson,rx8900
      - microcrystal,rv8803

  reg:
    maxItems: 1

  epson,vdet-disable:
    type: boolean
    description: |
      Disable voltage detector. Should be set if no backup battery is used.

  trickle-diode-disable: true

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        rtc@32 {
            compatible = "epson,rx8900";
            reg = <0x32>;
            epson,vdet-disable;
            trickle-diode-disable;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/faraday,ftrtc010.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Faraday Technology FTRTC010 Real Time Clock

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  This RTC appears in for example the Storlink Gemini family of SoCs.

properties:
  compatible:
    oneOf:
      - const: faraday,ftrtc010
      - items:
          - const: cortina,gemini-rtc
          - const: faraday,ftrtc010

  resets:
    maxItems: 1

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: PCLK clocks
      - description: EXTCLK clocks. Faraday calls it CLK1HZ and says the clock
          should be 1 Hz, but implementers actually seem to choose different
          clocks here, like Cortina who chose 32768 Hz (a typical low-power clock).

  clock-names:
    items:
      - const: "PCLK"
      - const: "EXTCLK"

required:
  - compatible

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    rtc@45000000 {
      compatible = "cortina,gemini-rtc", "faraday,ftrtc010";
      reg = <0x45000000 0x100>;
      interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&foo 0>, <&foo 1>;
      clock-names = "PCLK", "EXTCLK";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/fsl,scu-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX SCU Client Device Node - RTC bindings based on SCU Message Protocol

maintainers:
  - Dong Aisheng <aisheng.dong@nxp.com>

description: i.MX SCU Client Device Node
  Client nodes are maintained as children of the relevant IMX-SCU device node.

allOf:
  - $ref: rtc.yaml#

properties:
  compatible:
    const: fsl,imx8qxp-sc-rtc

required:
  - compatible

additionalProperties: false

examples:
  - |
    rtc {
        compatible = "fsl,imx8qxp-sc-rtc";
    };


code:
Android Goldfish RTC

Android Goldfish RTC device used by Android emulator.

Required properties:

- compatible : should contain "google,goldfish-rtc"
- reg        : <registers mapping>
- interrupts : <interrupt mapping>

Example:

	goldfish_timer@9020000 {
		compatible = "google,goldfish-rtc";
		reg = <0x9020000 0x1000>;
		interrupts = <0x3>;
	};


code:
Haoyu Microelectronics HYM8563 Real Time Clock

The HYM8563 provides basic rtc and alarm functionality
as well as a clock output of up to 32kHz.

Required properties:
- compatible: should be: "haoyu,hym8563"
- reg: i2c address
- #clock-cells: the value should be 0

Optional properties:
- clock-output-names: From common clock binding
- interrupts: rtc alarm/event interrupt

Example:

hym8563: hym8563@51 {
	compatible = "haoyu,hym8563";
	reg = <0x51>;

	interrupts = <13 IRQ_TYPE_EDGE_FALLING>;

	#clock-cells = <0>;
};

device {
...
	clocks = <&hym8563>;
...
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/imxdi-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX25 Real Time Clock controller

maintainers:
  - Roland Stigge <stigge@antcom.de>

properties:
  compatible:
    const: fsl,imx25-rtc

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: rtc alarm interrupt
      - description: dryice security violation interrupt
    minItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    rtc@53ffc000 {
        compatible = "fsl,imx25-rtc";
        reg = <0x53ffc000 0x4000>;
        clocks = <&clks 81>;
        interrupts = <25>, <56>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/ingenic,rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs Real-Time Clock DT bindings

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

allOf:
  - $ref: rtc.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - ingenic,jz4740-rtc
          - ingenic,jz4760-rtc
      - items:
          - const: ingenic,jz4725b-rtc
          - const: ingenic,jz4740-rtc
      - items:
          - enum:
              - ingenic,jz4770-rtc
              - ingenic,jz4780-rtc
          - const: ingenic,jz4760-rtc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: rtc

  system-power-controller:
    description: |
      Indicates that the RTC is responsible for powering OFF
      the system.
    type: boolean

  ingenic,reset-pin-assert-time-ms:
    minimum: 0
    maximum: 125
    default: 60
    description: |
      Reset pin low-level assertion time after wakeup
      (assuming RTC clock at 32 kHz)

  ingenic,min-wakeup-pin-assert-time-ms:
    minimum: 0
    maximum: 2000
    default: 100
    description: |
      Minimum wakeup pin assertion time
      (assuming RTC clock at 32 kHz)

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
    rtc_dev: rtc@10003000 {
      compatible = "ingenic,jz4740-rtc";
      reg = <0x10003000 0x40>;

      interrupt-parent = <&intc>;
      interrupts = <15>;

      clocks = <&cgu JZ4740_CLK_RTC>;
      clock-names = "rtc";
    };


code:
ISL12026 I2C RTC/EEPROM

ISL12026 is an I2C RTC/EEPROM combination device.  The RTC and control
registers respond at bus address 0x6f, and the EEPROM array responds
at bus address 0x57.  The canonical "reg" value will be for the RTC portion.

Required properties supported by the device:

 - "compatible": must be "isil,isl12026"
 - "reg": I2C bus address of the device (always 0x6f)

Optional properties:

 - "isil,pwr-bsw": If present PWR.BSW bit must be set to the specified
                   value for proper operation.

 - "isil,pwr-sbib": If present PWR.SBIB bit must be set to the specified
                    value for proper operation.

Example:

	rtc@6f {
		compatible = "isil,isl12026";
		reg = <0x6f>;
		isil,pwr-bsw = <0>;
		isil,pwr-sbib = <1>;
	}


code:
Intersil ISL12057 I2C RTC/Alarm chip

ISL12057 is a trivial I2C device (it has simple device tree bindings,
consisting of a compatible field, an address and possibly an interrupt
line).

Nonetheless, it also supports an option boolean property
("wakeup-source") to handle the specific use-case found
on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
(associated with the alarm supported by the driver) is not connected
to the SoC but to a PMIC. It allows the device to be powered up when
RTC alarm rings. In order to mark the device has a wakeup source and
get access to the 'wakealarm' sysfs entry, this specific property can
be set when the IRQ#2 pin of the chip is not connected to the SoC but
can wake up the device.

Required properties supported by the device:

 - "compatible": must be "isil,isl12057"
 - "reg": I2C bus address of the device

Optional properties:

 - "wakeup-source": mark the chip as a wakeup source, independently of
    the availability of an IRQ line connected to the SoC.

Example isl12057 node without IRQ#2 pin connected (no alarm support):

	isl12057: isl12057@68 {
		compatible = "isil,isl12057";
		reg = <0x68>;
	};

Example isl12057 node with IRQ#2 pin connected to main SoC via MPP6 (note
that the pinctrl-related properties below are given for completeness and
may not be required or may be different depending on your system or
SoC, and the main function of the MPP used as IRQ line, i.e.
"interrupt-parent" and "interrupts" are usually sufficient):

		    pinctrl {
				...

				rtc_alarm_pin: rtc_alarm_pin {
					marvell,pins = "mpp6";
					marvell,function = "gpio";
				};

				...

		    };

	...

	isl12057: isl12057@68 {
		compatible = "isil,isl12057";
		reg = <0x68>;
		pinctrl-0 = <&rtc_alarm_pin>;
		pinctrl-names = "default";
		interrupt-parent = <&gpio0>;
		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
	};

Example isl12057 node without IRQ#2 pin connected to the SoC but to a
PMIC, allowing the device to be started based on configured alarm:

	isl12057: isl12057@68 {
		compatible = "isil,isl12057";
		reg = <0x68>;
		wakeup-source;
	};


code:
Intersil ISL1209/19 I2C RTC/Alarm chip with event in

ISL12X9 have additional pins EVIN and #EVDET for tamper detection, while the
ISL1208 and ISL1218 do not.  They are all use the same driver with the bindings
described here, with chip specific properties as noted.

Required properties supported by the device:
 - "compatible": Should be one of the following:
		- "isil,isl1208"
		- "isil,isl1209"
		- "isil,isl1218"
		- "isil,isl1219"
 - "reg": I2C bus address of the device

Optional properties:
 - "interrupt-names": list which may contains "irq" and "evdet"
	evdet applies to isl1209 and isl1219 only
 - "interrupts": list of interrupts for "irq" and "evdet"
	evdet applies to isl1209 and isl1219 only
 - "isil,ev-evienb": Enable or disable internal pull on EVIN pin
	Applies to isl1209 and isl1219 only
	Possible values are 0 and 1
	Value 0 enables internal pull-up on evin pin, 1 disables it.
	Default will leave the non-volatile configuration of the pullup
	as is.

Example isl1219 node with #IRQ pin connected to SoC gpio1 pin12 and #EVDET pin
connected to SoC gpio2 pin 24 and internal pull-up enabled in EVIN pin.

	isl1219: rtc@68 {
		compatible = "isil,isl1219";
		reg = <0x68>;
		interrupt-names = "irq", "evdet";
		interrupts-extended = <&gpio1 12 IRQ_TYPE_EDGE_FALLING>,
			<&gpio2 24 IRQ_TYPE_EDGE_FALLING>;
		isil,ev-evienb = <1>;
	};


code:
* NXP LPC32xx SoC Real Time Clock controller

Required properties:
- compatible: must be "nxp,lpc3220-rtc"
- reg: physical base address of the controller and length of memory mapped
  region.
- interrupts: The RTC interrupt

Example:

	rtc@40024000 {
		compatible = "nxp,lpc3220-rtc";
		reg = <0x40024000 0x1000>;
		interrupts = <52 0>;
	};


code:
* Maxim (Dallas) DS1742/DS1743 Real Time Clock

Required properties:
- compatible: Should contain "maxim,ds1742".
- reg: Physical base address of the RTC and length of memory
  mapped region.

Example:
	rtc: rtc@10000000 {
		compatible = "maxim,ds1742";
		reg = <0x10000000 0x800>;
	};


code:
* Maxim DS3231 Real Time Clock

Required properties:
- compatible: Should contain "maxim,ds3231".
- reg: I2C address for chip.

Optional property:
- #clock-cells: Should be 1.
- clock-output-names:
  overwrite the default clock names "ds3231_clk_sqw" and "ds3231_clk_32khz".

Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. Following indices are allowed:
    - 0: square-wave output on the SQW pin
    - 1: square-wave output on the 32kHz pin

- interrupts: rtc alarm/event interrupt. When this property is selected,
  clock on the SQW pin cannot be used.

Example:

ds3231: ds3231@51 {
	compatible = "maxim,ds3231";
	reg = <0x68>;
	#clock-cells = <1>;
};

device1 {
...
	clocks = <&ds3231 0>;
...
};

device2 {
...
	clocks = <&ds3231 1>;
...
};


code:
* Maxim MCP795		SPI Serial Real-Time Clock

Required properties:
- compatible: Should contain "maxim,mcp795".
- reg: SPI address for chip

Example:
	mcp795: rtc@0 {
		compatible = "maxim,mcp795";
		reg = <0>;
	};


code:
* Maxim/Dallas Semiconductor DS-1302 RTC

Simple device which could be used to store date/time between reboots.

The device uses the standard MicroWire half-duplex transfer timing.
Master output is set on low clock and sensed by the RTC on the rising
edge. Master input is set by the RTC on the trailing edge and is sensed
by the master on low clock.

Required properties:

- compatible : Should be "maxim,ds1302"

Required SPI properties:

- reg : Should be address of the device chip select within
  the controller.

- spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V,
  and 2MHz if powered at 5V.

- spi-3wire : The device has a shared signal IN/OUT line.

- spi-lsb-first : DS-1302 requires least significant bit first
  transfers.

- spi-cs-high: DS-1302 has active high chip select line. This is
  required unless inverted in hardware.

Example:

spi@901c {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "icpdas,lp8841-spi-rtc";
	reg = <0x901c 0x1>;

	rtc@0 {
		compatible = "maxim,ds1302";
		reg = <0>;
		spi-max-frequency = <500000>;
		spi-3wire;
		spi-lsb-first;
		spi-cs-high;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip PolarFire Soc (MPFS) RTC

allOf:
  - $ref: rtc.yaml#

maintainers:
  - Daire McNamara <daire.mcnamara@microchip.com>
  - Lewis Hanly <lewis.hanly@microchip.com>

properties:
  compatible:
    enum:
      - microchip,mpfs-rtc

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: |
          RTC_WAKEUP interrupt
      - description: |
          RTC_MATCH, asserted when the content of the Alarm register is equal
          to that of the RTC's count register.

  clocks:
    items:
      - description: |
          AHB clock
      - description: |
          Reference clock: divided by the prescaler to create a time-based
          strobe (typically 1 Hz) for the calendar counter. By default, the rtc
          on the PolarFire SoC shares it's reference with MTIMER so this will
          be a 1 MHz clock.

  clock-names:
    items:
      - const: rtc
      - const: rtcref

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include "dt-bindings/clock/microchip,mpfs-clock.h"
    rtc@20124000 {
        compatible = "microchip,mpfs-rtc";
        reg = <0x20124000 0x1000>;
        clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
        clock-names = "rtc", "rtcref";
        interrupts = <80>, <81>;
    };
...


code:
* Microchip PIC32 Real Time Clock and Calendar

The RTCC keeps time in hours, minutes, and seconds, and one half second. It
provides a calendar in weekday, date, month, and year. It also provides a
configurable alarm.

Required properties:
- compatible: should be: "microchip,pic32mzda-rtc"
- reg: physical base address of the controller and length of memory mapped
    region.
- interrupts: RTC alarm/event interrupt
- clocks: clock phandle

Example:

	rtc: rtc@1f8c0000 {
		compatible = "microchip,pic32mzda-rtc";
		reg = <0x1f8c0000 0x60>;
		interrupts = <166 IRQ_TYPE_EDGE_RISING>;
		clocks = <&PBCLK6>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/microcrystal,rv3032.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip RV-3032 RTC

allOf:
  - $ref: "rtc.yaml#"

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

properties:
  compatible:
    const: microcrystal,rv3032

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  start-year: true

  trickle-resistor-ohms:
    enum:
      - 1000
      - 2000
      - 7000
      - 11000

  trickle-voltage-millivolt:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum:
      - 1750
      - 3000
      - 4400

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        rtc@51 {
            compatible = "microcrystal,rv3032";
            reg = <0x51>;
            pinctrl-0 = <&rtc_nint_pins>;
            interrupts-extended = <&gpio1 16 IRQ_TYPE_LEVEL_HIGH>;
            trickle-resistor-ohms = <7000>;
            trickle-voltage-millivolt = <1750>;
        };
    };

...


code:
MOXA ART real-time clock

Required properties:

- compatible : Should be "moxa,moxart-rtc"
- gpio-rtc-sclk : RTC sclk gpio, with zero flags
- gpio-rtc-data : RTC data gpio, with zero flags
- gpio-rtc-reset : RTC reset gpio, with zero flags

Example:

	rtc: rtc {
		compatible = "moxa,moxart-rtc";
		gpio-rtc-sclk = <&gpio 5 0>;
		gpio-rtc-data = <&gpio 6 0>;
		gpio-rtc-reset = <&gpio 7 0>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/mstar,msc313-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mstar MSC313e RTC

allOf:
  - $ref: "rtc.yaml#"

maintainers:
  - Daniel Palmer <daniel@0x0f.com>
  - Romain Perier <romain.perier@gmail.com>

properties:
  compatible:
    enum:
      - mstar,msc313-rtc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  start-year: true

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    rtc@2400 {
        compatible = "mstar,msc313-rtc";
        reg = <0x2400 0x40>;
        clocks = <&xtal_div2>;
        interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/nuvoton,nct3018y.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NUVOTON NCT3018Y Real Time Clock

allOf:
  - $ref: "rtc.yaml#"

maintainers:
  - Medad CChien <ctcchien@nuvoton.com>
  - Mia Lin <mimi05633@gmail.com>

properties:
  compatible:
    const: nuvoton,nct3018y

  reg:
    maxItems: 1

  start-year: true

  reset-source: true

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        rtc@6f {
            compatible = "nuvoton,nct3018y";
            reg = <0x6f>;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra real-time clock

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: |
  The Tegra RTC maintains seconds and milliseconds counters, and five
  alarm registers. The alarms and other interrupts may wake the system
  from low-power state.

properties:
  compatible:
    oneOf:
      - const: nvidia,tegra20-rtc
      - items:
          - enum:
              - nvidia,tegra30-rtc
              - nvidia,tegra114-rtc
              - nvidia,tegra124-rtc
              - nvidia,tegra210-rtc
              - nvidia,tegra186-rtc
              - nvidia,tegra194-rtc
              - nvidia,tegra234-rtc
          - const: nvidia,tegra20-rtc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: rtc

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks

examples:
  - |
    timer@7000e000 {
        compatible = "nvidia,tegra20-rtc";
        reg = <0x7000e000 0x100>;
        interrupts = <0 2 0x04>;
        clocks = <&tegra_car 4>;
    };


code:
NXP LPC1788 real-time clock

The LPC1788 RTC provides calendar and clock functionality
together with periodic tick and alarm interrupt support.

Required properties:
- compatible	: must contain "nxp,lpc1788-rtc"
- reg		: Specifies base physical address and size of the registers.
- interrupts	: A single interrupt specifier.
- clocks	: Must contain clock specifiers for rtc and register clock
- clock-names	: Must contain "rtc" and "reg"
  See ../clocks/clock-bindings.txt for details.

Example:
rtc: rtc@40046000 {
	compatible = "nxp,lpc1788-rtc";
	reg = <0x40046000 0x1000>;
	interrupts = <47>;
	clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
	clock-names = "rtc", "reg";
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/nxp,pcf2127.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP PCF2127 Real Time Clock

allOf:
  - $ref: "rtc.yaml#"

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

properties:
  compatible:
    const: nxp,pcf2127

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  start-year: true

  reset-source: true

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        rtc@51 {
            compatible = "nxp,pcf2127";
            reg = <0x51>;
            pinctrl-0 = <&rtc_nint_pins>;
            interrupts-extended = <&gpio1 16 IRQ_TYPE_LEVEL_HIGH>;
            reset-source;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/nxp,pcf85063.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP PCF85063 Real Time Clock

maintainers:
  - Alexander Stein <alexander.stein@ew.tq-group.com>

properties:
  compatible:
    enum:
      - microcrystal,rv8263
      - nxp,pcf85063
      - nxp,pcf85063a
      - nxp,pcf85063tp
      - nxp,pca85073a

  reg:
    maxItems: 1

  "#clock-cells":
    const: 0

  clock-output-names:
    maxItems: 1

  interrupts:
    maxItems: 1

  quartz-load-femtofarads:
    description:
      The capacitive load of the quartz(x-tal).
    enum: [7000, 12500]
    default: 7000

  clock:
    $ref: /schemas/clock/fixed-clock.yaml
    description:
      Provide this if the square wave pin is used as boot-enabled
      fixed clock.

  wakeup-source: true

allOf:
  - $ref: rtc.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - microcrystal,rv8263
    then:
      properties:
        quartz-load-femtofarads: false
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nxp,pcf85063
    then:
      properties:
        quartz-load-femtofarads:
          const: 7000

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        rtc@51 {
          compatible = "nxp,pcf85063a";
          reg = <0x51>;
          quartz-load-femtofarads = <12500>;

          clock {
            compatible = "fixed-clock";
            #clock-cells = <0>;
            clock-frequency = <32768>;
          };
        };
      };


code:
* NXP PCF8523 Real Time Clock

Required properties:
- compatible: Should contain "nxp,pcf8523".
- reg: I2C address for chip.

Optional property:
- quartz-load-femtofarads: The capacitive load of the quartz(x-tal),
  expressed in femto Farad (fF). Valid values are 7000 and 12500.
  Default value (if no value is specified) is 12500fF.

Example:

pcf8523: rtc@68 {
	compatible = "nxp,pcf8523";
	reg = <0x68>;
	quartz-load-femtofarads = <7000>;
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/nxp,pcf8563.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Philips PCF8563/Epson RTC8564 Real Time Clock

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

allOf:
  - $ref: rtc.yaml#

properties:
  compatible:
    enum:
      - epson,rtc8564
      - microcrystal,rv8564
      - nxp,pca8565
      - nxp,pcf8563
      - nxp,pcf85263
      - nxp,pcf85363

  reg:
    maxItems: 1

  "#clock-cells":
    const: 0

  clock-output-names:
    maxItems: 1

  interrupts:
    maxItems: 1

  start-year: true
  wakeup-source: true

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        rtc@51 {
            compatible = "nxp,pcf8563";
            reg = <0x51>;
            #clock-cells = <0>;
        };
    };
...


code:
NXP PCF2123 SPI Real Time Clock

Required properties:
- compatible: should be: "nxp,pcf2123"
                      or "microcrystal,rv2123"
- reg: should be the SPI slave chipselect address

Optional properties:
- spi-cs-high: PCF2123 needs chipselect high

Example:

pcf2123: rtc@3 {
	compatible = "nxp,pcf2123"
	reg = <3>
	spi-cs-high;
};


code:
OLPC XO-1 RTC
~~~~~~~~~~~~~

Required properties:
 - compatible : "olpc,xo1-rtc"


code:
* Mvebu Real Time Clock

RTC controller for the Kirkwood, the Dove, the Armada 370 and the
Armada XP SoCs

Required properties:
- compatible : Should be "marvell,orion-rtc"
- reg: physical base address of the controller and length of memory mapped
  region.
- interrupts: IRQ line for the RTC.

Example:

rtc@10300 {
        compatible = "marvell,orion-rtc";
        reg = <0xd0010300 0x20>;
        interrupts = <50>;
};


code:
* PXA RTC

PXA specific RTC driver.

Required properties:
- compatible : Should be "marvell,pxa-rtc"

Examples:

rtc@40900000 {
	compatible = "marvell,pxa-rtc";
	reg = <0x40900000 0x3c>;
	interrupts = <30 31>;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/qcom-pm8xxx-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm PM8xxx PMIC RTC device

maintainers:
  - Satya Priya <quic_c_skakit@quicinc.com>

properties:
  compatible:
    enum:
      - qcom,pm8058-rtc
      - qcom,pm8921-rtc
      - qcom,pm8941-rtc
      - qcom,pm8018-rtc
      - qcom,pmk8350-rtc

  reg:
    minItems: 1
    maxItems: 2

  reg-names:
    minItems: 1
    items:
      - const: rtc
      - const: alarm

  interrupts:
    maxItems: 1

  allow-set-time:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Indicates that the setting of RTC time is allowed by the host CPU.

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/spmi/spmi.h>
    spmi_bus: spmi@c440000 {
      reg = <0x0c440000 0x1100>;
      #address-cells = <2>;
      #size-cells = <0>;
      pmicintc: pmic@0 {
        reg = <0x0 SPMI_USID>;
        compatible = "qcom,pm8921";
        interrupts = <104 8>;
        #interrupt-cells = <2>;
        interrupt-controller;
        #address-cells = <1>;
        #size-cells = <0>;

        pm8921_rtc: rtc@11d {
          compatible = "qcom,pm8921-rtc";
          reg = <0x11d>;
          interrupts = <0x27 0>;
        };
      };
    };
...


code:
Realtek RTD129x Real-Time Clock
===============================

Required properties:
- compatible :  Should be "realtek,rtd1295-rtc"
- reg        :  Specifies the physical base address and size
- clocks     :  Specifies the clock gate

Example:

	rtc@9801b600 {
		compatible = "realtek,rtd1295-clk";
		reg = <0x9801b600 0x100>;
		clocks = <&clkc RTD1295_CLK_EN_MISC_RTC>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/renesas,rzn1-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/N1 SoCs Real-Time Clock DT bindings

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

allOf:
  - $ref: rtc.yaml#

properties:
  compatible:
    items:
      - enum:
          - renesas,r9a06g032-rtc
      - const: renesas,rzn1-rtc

  reg:
    maxItems: 1

  interrupts:
    minItems: 3
    maxItems: 3

  interrupt-names:
    items:
      - const: alarm
      - const: timer
      - const: pps

  clocks:
    maxItems: 1

  clock-names:
    const: hclk

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - power-domains

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/r9a06g032-sysctrl.h>
    rtc@40006000 {
       compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
       reg = <0x40006000 0x1000>;
       interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
                    <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
                    <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
       interrupt-names = "alarm", "timer", "pps";
       clocks = <&sysctrl R9A06G032_HCLK_RTC>;
       clock-names = "hclk";
       power-domains = <&sysctrl>;
       start-year = <2000>;
     };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/renesas,sh-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Real Time Clock for Renesas SH and ARM SoCs

maintainers:
  - Chris Brandt <chris.brandt@renesas.com>
  - Geert Uytterhoeven <geert+renesas@glider.be>

properties:
  compatible:
    items:
      - const: renesas,r7s72100-rtc  # RZ/A1H
      - const: renesas,sh-rtc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 3

  interrupt-names:
    items:
      - const: alarm
      - const: period
      - const: carry

  clocks:
    # The functional clock source for the RTC controller must be listed
    # first (if it exists). Additionally, potential clock counting sources
    # are to be listed.
    minItems: 1
    maxItems: 4

  clock-names:
    # The functional clock must be labeled as "fck". Other clocks
    # may be named in accordance to the SoC hardware manuals.
    minItems: 1
    maxItems: 4
    items:
      enum: [ fck, rtc_x1, rtc_x3, extal ]

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r7s72100-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    rtc: rtc@fcff1000 {
        compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
        reg = <0xfcff1000 0x2e>;
        interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
        interrupt-names = "alarm", "period", "carry";
        clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
                 <&rtc_x3_clk>, <&extal_clk>;
        power-domains = <&cpg_clocks>;
        clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
    };


code:
ASPEED BMC RTC
==============

Required properties:
 - compatible: should be one of the following
   * aspeed,ast2400-rtc for the ast2400
   * aspeed,ast2500-rtc for the ast2500
   * aspeed,ast2600-rtc for the ast2600

 - reg: physical base address of the controller and length of memory mapped
   region

 - interrupts: The interrupt number

Example:

   rtc@1e781000 {
           compatible = "aspeed,ast2400-rtc";
           reg = <0x1e781000 0x18>;
           interrupts = <22>;
           status = "disabled";
   };


code:
 Motorola mc146818 compatible RTC
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Required properties:
  - compatible : "motorola,mc146818"
  - reg : should contain registers location and length.

Optional properties:
  - interrupts : should contain interrupt.
  - ctrl-reg : Contains the initial value of the control register also
    called "Register B".
  - freq-reg : Contains the initial value of the frequency register also
    called "Regsiter A".

"Register A" and "B" are usually initialized by the firmware (BIOS for
instance). If this is not done, it can be performed by the driver.

ISA Example:

	rtc@70 {
	         compatible = "motorola,mc146818";
	         interrupts = <8 3>;
	         interrupt-parent = <&ioapic1>;
	         ctrl-reg = <2>;
	         freq-reg = <0x26>;
	         reg = <1 0x70 2>;
	 };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/rtc-ds1307.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Dallas DS1307 and compatible RTC

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

properties:
  compatible:
    oneOf:
      - enum:
          - dallas,ds1307
          - dallas,ds1308
          - dallas,ds1337
          - dallas,ds1338
          - dallas,ds1339
          - dallas,ds1388
          - dallas,ds1340
          - dallas,ds1341
          - maxim,ds3231
          - st,m41t0
          - st,m41t00
          - st,m41t11
          - microchip,mcp7940x
          - microchip,mcp7941x
          - pericom,pt7c4338
          - epson,rx8025
          - isil,isl12057
          - epson,rx8130

      - items:
          - enum:
              - st,m41t00
          - const: dallas,ds1338

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 2

  interrupt-names:
    maxItems: 2

  "#clock-cells":
    const: 1

  clock-output-names:
    description: From common clock binding to override the default output clock name.

  wakeup-source:
    description: Enables wake up of host system on alarm.

  vcc-supply: true

allOf:
  - $ref: rtc.yaml
  - if:
      properties:
        compatible:
          contains:
            enum:
              - dallas,ds1339
              - dallas,ds1340
              - dallas,ds1388
    then:
      properties:
        trickle-resistor-ohms:
          description: Selected resistor for trickle charger. Should be specified if trickle
            charger should be enabled.
          enum: [ 250, 2000, 4000 ]

        trickle-diode-disable:
          description: Do not use internal trickle charger diode. Should be given if internal
            trickle charger diode should be disabled (superseded by aux-voltage-chargeable)
          deprecated: true

unevaluatedProperties: false

required:
  - compatible
  - reg

examples:
  - |
    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      rtc@68 {
        compatible = "dallas,ds1337";
        reg = <0x68>;
        interrupt-parent = <&gpio4>;
        interrupts = <20 0>;
        trickle-resistor-ohms = <250>;
      };
    };


code:
Freescale FlexTimer Module (FTM) Alarm

Required properties:
- compatible : Should be "fsl,<chip>-ftm-alarm", the
	       supported chips include
	       "fsl,ls1012a-ftm-alarm"
	       "fsl,ls1021a-ftm-alarm"
	       "fsl,ls1028a-ftm-alarm"
	       "fsl,ls1043a-ftm-alarm"
	       "fsl,ls1046a-ftm-alarm"
	       "fsl,ls1088a-ftm-alarm"
	       "fsl,ls208xa-ftm-alarm"
	       "fsl,lx2160a-ftm-alarm"
- reg : Specifies base physical address and size of the register sets for the
  FlexTimer Module.
- interrupts : Should be the FlexTimer Module interrupt.
- fsl,rcpm-wakeup property and rcpm node : Please refer
	Documentation/devicetree/bindings/soc/fsl/rcpm.txt

Optional properties:
- big-endian: If the host controller is big-endian mode, specify this property.
  The default endian mode is little-endian.

Example:
rcpm: rcpm@1e34040 {
	compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
	reg = <0x0 0x1e34040 0x0 0x18>;
	#fsl,rcpm-wakeup-cells = <6>;
};

ftm_alarm0: timer@2800000 {
	compatible = "fsl,ls1088a-ftm-alarm";
	reg = <0x0 0x2800000 0x0 0x10000>;
	fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
	interrupts = <0 44 4>;
};


code:
ST M41T80 family of RTC and compatible

Required properties:
- compatible: should be one of:
	"st,m41t62",
	"st,m41t65",
	"st,m41t80",
	"st,m41t81",
	"st,m41t81s",
	"st,m41t82",
	"st,m41t83",
	"st,m41t84",
	"st,m41t85",
	"st,m41t87",
	"microcrystal,rv4162",
- reg: I2C bus address of the device

Optional properties:
- interrupts: rtc alarm interrupt.
- clock-output-names: From common clock binding to override the default output
                      clock name
- wakeup-source: Enables wake up of host system on alarm

Optional child node:
- clock: Provide this if the square wave pin is used as boot-enabled fixed clock.

Example:
	rtc@68 {
		compatible = "st,m41t80";
		reg = <0x68>;
		interrupt-parent = <&UIC0>;
		interrupts = <0x9 0x8>;

		clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};


code:
* Amlogic Virtual RTC (VRTC)

This is a Linux interface to an RTC managed by firmware, hence it's
virtual from a Linux perspective.  The interface is 1 register where
an alarm time (in seconds) is to be written.

Required properties:
- compatible: should be "amlogic,meson-vrtc"
- reg: physical address for the alarm register

The alarm register is a simple scratch register shared between the
application processors (AP) and the secure co-processor (SCP.)  When
the AP suspends, the SCP will use the value of this register to
program an always-on timer before going sleep. When the timer expires,
the SCP will wake up and will then wake the AP.

Example:

	vrtc: rtc@0a8 {
		compatible = "amlogic,meson-vrtc";
		reg = <0x0 0x000a8 0x0 0x4>;
	};


code:
* Amlogic Meson6, Meson8, Meson8b and Meson8m2 RTC

Required properties:
- compatible: should be one of the following describing the hardware:
	* "amlogic,meson6-rtc"
	* "amlogic,meson8-rtc"
	* "amlogic,meson8b-rtc"
	* "amlogic,meson8m2-rtc"

- reg: physical register space for the controller's memory mapped registers.
- interrupts: the interrupt line of the RTC block.
- clocks: reference to the external 32.768kHz crystal oscillator.
- vdd-supply: reference to the power supply of the RTC block.
- resets: reset controller reference to allow reset of the controller

Optional properties for the battery-backed non-volatile memory:
- #address-cells: should be 1 to address the battery-backed non-volatile memory
- #size-cells: should be 1 to reference the battery-backed non-volatile memory

Optional child nodes:
- see ../nvmem/nvmem.txt

Example:

	rtc: rtc@740 {
		compatible = "amlogic,meson6-rtc";
		reg = <0x740 0x14>;
		interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
		clocks = <&rtc32k_xtal>;
		vdd-supply = <&rtc_vdd>;
		resets = <&reset RESET_RTC>;

		#address-cells = <1>;
		#size-cells = <1>;
	};


code:
Device-Tree bindings for MediaTek SoC based RTC

Required properties:
- compatible	    : Should be "mediatek,mt2712-rtc" : for MT2712 SoC
- reg 		    : Specifies base physical address and size of the registers;
- interrupts	    : Should contain the interrupt for RTC alarm;

Example:

rtc: rtc@10011000 {
	compatible = "mediatek,mt2712-rtc";
	reg = <0 0x10011000 0 0x1000>;
	interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>;
};


code:
Device-Tree bindings for MediaTek PMIC based RTC

MediaTek PMIC based RTC is an independent function of MediaTek PMIC that works
as a type of multi-function device (MFD). The RTC can be configured and set up
with PMIC wrapper bus which is a common resource shared with the other
functions found on the same PMIC.

For MediaTek PMIC MFD bindings, see:
../mfd/mt6397.txt

For MediaTek PMIC wrapper bus bindings, see:
../soc/mediatek/pwrap.txt

Required properties:
- compatible: Should be one of follows
       "mediatek,mt6323-rtc": for MT6323 PMIC
       "mediatek,mt6358-rtc": for MT6358 PMIC
       "mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC
       "mediatek,mt6397-rtc": for MT6397 PMIC

Example:

       pmic {
               compatible = "mediatek,mt6323";

               ...

               rtc {
                       compatible = "mediatek,mt6323-rtc";
               };
       };


code:
Device-Tree bindings for MediaTek SoC based RTC

Required properties:
- compatible	    : Should be
			"mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC
- reg 		    : Specifies base physical address and size of the registers;
- interrupts	    : Should contain the interrupt for RTC alarm;
- clocks	    : Specifies list of clock specifiers, corresponding to
		      entries in clock-names property;
- clock-names	    : Should contain "rtc" entries

Example:

rtc: rtc@10212800 {
	compatible = "mediatek,mt7622-rtc",
		     "mediatek,soc-rtc";
	reg = <0 0x10212800 0 0x200>;
	interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_RTC>;
	clock-names = "rtc";
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/rtc-mxc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Real Time Clock of the i.MX SoCs

allOf:
  - $ref: "rtc.yaml#"

maintainers:
  - Philippe Reynes <tremyfr@gmail.com>

properties:
  compatible:
    enum:
      - fsl,imx1-rtc
      - fsl,imx21-rtc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: input reference
      - description: the SoC RTC clock

  clock-names:
    items:
      - const: ref
      - const: ipg

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx27-clock.h>

    rtc@10007000 {
        compatible = "fsl,imx21-rtc";
        reg = <0x10007000 0x1000>;
        interrupts = <22>;
        clocks = <&clks IMX27_CLK_CKIL>,
                 <&clks IMX27_CLK_RTC_IPG_GATE>;
        clock-names = "ref", "ipg";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/rtc-mxc_v2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX53 Secure Real Time Clock (SRTC)

allOf:
  - $ref: "rtc.yaml#"

maintainers:
  - Patrick Bruenn <p.bruenn@beckhoff.com>

properties:
  compatible:
    enum:
      - fsl,imx53-rtc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx5-clock.h>

    rtc@53fa4000 {
        compatible = "fsl,imx53-rtc";
        reg = <0x53fa4000 0x4000>;
        interrupts = <24>;
        clocks = <&clks IMX5_CLK_SRTC_GATE>;
    };


code:
TI Real Time Clock

Required properties:
- compatible:
	- "ti,da830-rtc"  - for RTC IP used similar to that on DA8xx SoC family.
	- "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
			    This RTC IP has special WAKE-EN Register to enable
			    Wakeup generation for event Alarm. It can also be
			    used to control an external PMIC via the
			    pmic_power_en pin.
	- "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
- reg: Address range of rtc register set
- interrupts: rtc timer, alarm interrupts in order

Optional properties:
- system-power-controller: whether the rtc is controlling the system power
  through pmic_power_en
- clocks: Any internal or external clocks feeding in to rtc
- clock-names: Corresponding names of the clocks
- pinctrl-0: a phandle pointing to the pin settings for the device
- pinctrl-names: should be "default"

Optional subnodes:
- generic pinctrl node

Required pinctrl subnodes properties:
- pins - Names of ext_wakeup pins to configure

Optional pinctrl subnodes properties:
- input-enable - Enables ext_wakeup
- ti,active-high - Set input active high (by default active low)

Example:

rtc@1c23000 {
	compatible = "ti,da830-rtc";
	reg = <0x23000 0x1000>;
	interrupts = <19
		      19>;
	interrupt-parent = <&intc>;
	system-power-controller;
	clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
	clock-names = "ext-clk", "int-clk";

	pinctrl-0 = <&ext_wakeup>;
	pinctrl-names = "default";

	ext_wakeup: ext-wakeup {
		pins = "ext_wakeup0";
		input-enable;
		ti,active-high;
	};
};


code:
IBM OPAL real-time clock
------------------------

Required properties:
- compatible: Should be "ibm,opal-rtc"

Optional properties:
- wakeup-source: Decides if the wakeup is supported or not
		 (Legacy property supported: "has-tpo")

Example:
	rtc {
		compatible = "ibm,opal-rtc";
		wakeup-source;
		phandle = <0x10000029>;
		linux,phandle = <0x10000029>;
	};


code:
Palmas RTC controller bindings

Required properties:
- compatible:
  - "ti,palmas-rtc" for palma series of the RTC controller
- interrupts: Interrupt number of RTC submodule on device.

Optional properties:

- ti,backup-battery-chargeable: The Palmas series device like TPS65913 or
	TPS80036 supports the backup battery for powering the RTC when main
	battery is removed or in very low power state. The backup battery
	can be chargeable or non-chargeable. This flag will tells whether
	battery is chargeable or not. If charging battery then driver can
	enable the charging.
- ti,backup-battery-charge-high-current: Enable high current charging in
	backup battery. Device supports the < 100uA and > 100uA charging.
	The high current will be > 100uA. Absence of this property will
	charge battery to lower current i.e. < 100uA.

Example:
	palmas: tps65913@58 {
		...
		palmas_rtc: rtc {
			compatible = "ti,palmas-rtc";
			interrupt-parent = <&palmas>;
			interrupts = <8 0>;
			ti,backup-battery-chargeable;
			ti,backup-battery-charge-high-current;
		};
		...
	};


code:
STMicroelectronics Low Power Controller (LPC) - RTC
===================================================

LPC currently supports Watchdog OR Real Time Clock OR Clocksource
functionality.

[See: ../watchdog/st_lpc_wdt.txt for Watchdog options]
[See: ../timer/st,stih407-lpc for Clocksource options]

Required properties

- compatible 	: Must be: "st,stih407-lpc"
- reg		: LPC registers base address + size
- interrupts    : LPC interrupt line number and associated flags
- clocks	: Clock used by LPC device (See: ../clock/clock-bindings.txt)
- st,lpc-mode	: The LPC can run either one of three modes:
                  ST_LPC_MODE_RTC    [0]
                  ST_LPC_MODE_WDT    [1]
                  ST_LPC_MODE_CLKSRC [2]
		 One (and only one) mode must be selected.

Example:
	lpc@fde05000 {
		compatible	= "st,stih407-lpc";
		reg		= <0xfde05000 0x1000>;
		clocks 		= <&clk_s_d3_flexgen CLK_LPC_0>;
		st,lpc-mode	= <ST_LPC_MODE_RTC>;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RTC Generic Binding

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

description: |
  This document describes generic bindings which can be used to
  describe Real Time Clock devices in a device tree.

properties:
  $nodename:
    pattern: "^rtc(@.*|-[0-9a-f])*$"

  aux-voltage-chargeable:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]
    description: |
      Tells whether the battery/supercap of the RTC (if any) is
      chargeable or not:
      0: not chargeable
      1: chargeable

  quartz-load-femtofarads:
    description:
      The capacitive load of the quartz(x-tal), expressed in femto
      Farad (fF). The default value shall be listed (if optional),
      and likewise all valid values.

  start-year:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      If provided, the default hardware range supported by the RTC is
      shifted so the first usable year is the specified one.

  trickle-diode-disable:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Do not use internal trickle charger diode. Should be given if
      internal trickle charger diode should be disabled.
    deprecated: true

  trickle-resistor-ohms:
    description:
      Selected resistor for trickle charger. Should be given
      if trickle charger should be enabled.

  trickle-voltage-millivolt:
    description:
      Selected voltage for trickle charger. Should be given
      if trickle charger should be enabled and the trickle voltage is different
      from the RTC main power supply.

  wakeup-source:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Enables wake up of host system on alarm.

  reset-source:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      The RTC is able to reset the machine.

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/s3c-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S3C, S5P and Exynos Real Time Clock controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    oneOf:
      - enum:
          - samsung,s3c2410-rtc
          - samsung,s3c2416-rtc
          - samsung,s3c2443-rtc
          - samsung,s3c6410-rtc
      - const: samsung,exynos3250-rtc
        deprecated: true

  reg:
    maxItems: 1

  clocks:
    description:
      Must contain a list of phandle and clock specifier for the rtc
      clock and in the case of a s3c6410 compatible controller, also
      a source clock.
    minItems: 1
    maxItems: 2

  clock-names:
    description:
      Must contain "rtc" and for a s3c6410 compatible controller
      also "rtc_src".
    minItems: 1
    maxItems: 2

  interrupts:
    description:
      Two interrupt numbers to the cpu should be specified. First
      interrupt number is the rtc alarm interrupt and second interrupt number
      is the rtc tick interrupt. The number of cells representing a interrupt
      depends on the parent interrupt controller.
    minItems: 2
    maxItems: 2

allOf:
  - $ref: rtc.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,s3c6410-rtc
              - samsung,exynos3250-rtc
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: rtc
            - const: rtc_src
    else:
      properties:
        clocks:
          minItems: 1
          maxItems: 1
        clock-names:
          items:
            - const: rtc

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5420.h>
    #include <dt-bindings/clock/samsung,s2mps11.h>

    rtc@10070000 {
        compatible = "samsung,s3c6410-rtc";
        reg = <0x10070000 0x100>;
        interrupts = <0 44 4>, <0 45 4>;
        clocks = <&clock CLK_RTC>,
                 <&s2mps11_osc S2MPS11_CLK_AP>;
        clock-names = "rtc", "rtc_src";
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/sa1100-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell Real Time Clock controller bindings

allOf:
  - $ref: rtc.yaml#

maintainers:
  - Alessandro Zummo <a.zummo@towertech.it>
  - Alexandre Belloni <alexandre.belloni@bootlin.com>
  - Rob Herring <robh+dt@kernel.org>

properties:
  compatible:
    enum:
      - mrvl,sa1100-rtc
      - mrvl,mmp-rtc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  interrupts:
    minItems: 2

  interrupt-names:
    items:
      - const: 'rtc 1Hz'
      - const: 'rtc alarm'

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    rtc: rtc@d4010000 {
        compatible = "mrvl,mmp-rtc";
        reg = <0xd4010000 0x1000>;
        interrupts = <5>, <6>;
        interrupt-names = "rtc 1Hz", "rtc alarm";
    };

...


code: See Documentation/devicetree/bindings/crypto/fsl-sec4.txt for details.


code:
* SPEAr RTC

Required properties:
- compatible : "st,spear600-rtc"
- reg : Address range of the rtc registers
- interrupt: Should contain the rtc interrupt number

Example:

	rtc@fc000000 {
		compatible = "st,spear600-rtc";
		reg = <0xfc000000 0x1000>;
		interrupt-parent = <&vic1>;
		interrupts = <12>;
	};


code:
Spreadtrum SC27xx Real Time Clock

Required properties:
- compatible: should be "sprd,sc2731-rtc".
- reg: address offset of rtc register.
- interrupts: rtc alarm interrupt.

Example:

	sc2731_pmic: pmic@0 {
		compatible = "sprd,sc2731";
		reg = <0>;
		spi-max-frequency = <26000000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;
		#address-cells = <1>;
		#size-cells = <0>;

		rtc@280 {
			compatible = "sprd,sc2731-rtc";
			reg = <0x280>;
			interrupt-parent = <&sc2731_pmic>;
			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 Real Time Clock Bindings

maintainers:
  - Gabriel Fernandez <gabriel.fernandez@foss.st.com>

properties:
  compatible:
    enum:
      - st,stm32-rtc
      - st,stm32h7-rtc
      - st,stm32mp1-rtc

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    items:
      - const: pclk
      - const: rtc_ck

  interrupts:
    maxItems: 1

  st,syscfg:
    $ref: "/schemas/types.yaml#/definitions/phandle-array"
    items:
      minItems: 3
      maxItems: 3
    description: |
      Phandle/offset/mask triplet. The phandle to pwrcfg used to
      access control register at offset, and change the dbp (Disable Backup
      Protection) bit represented by the mask, mandatory to disable/enable backup
      domain (RTC registers) write protection.

  assigned-clocks:
    description: |
      override default rtc_ck parent clock reference to the rtc_ck clock entry
    maxItems: 1

  assigned-clock-parents:
    description: |
      override default rtc_ck parent clock phandle of the new parent clock of rtc_ck
    maxItems: 1

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: st,stm32-rtc

    then:
      properties:
        clocks:
          minItems: 1
          maxItems: 1

        clock-names: false

      required:
        - st,syscfg

  - if:
      properties:
        compatible:
          contains:
            const: st,stm32h7-rtc

    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2

      required:
        - clock-names
        - st,syscfg

  - if:
      properties:
        compatible:
          contains:
            const: st,stm32mp1-rtc

    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2

        assigned-clocks: false
        assigned-clock-parents: false

      required:
        - clock-names

required:
  - compatible
  - reg
  - clocks
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/mfd/stm32f4-rcc.h>
    #include <dt-bindings/clock/stm32fx-clock.h>
    rtc@40002800 {
      compatible = "st,stm32-rtc";
      reg = <0x40002800 0x400>;
      clocks = <&rcc 1 CLK_RTC>;
      assigned-clocks = <&rcc 1 CLK_RTC>;
      assigned-clock-parents = <&rcc 1 CLK_LSE>;
      interrupt-parent = <&exti>;
      interrupts = <17 1>;
      st,syscfg = <&pwrcfg 0x00 0x100>;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    rtc@5c004000 {
      compatible = "st,stm32mp1-rtc";
      reg = <0x5c004000 0x400>;
      clocks = <&rcc RTCAPB>, <&rcc RTC>;
      clock-names = "pclk", "rtc_ck";
      interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
    };

...


code:
* STMP3xxx/i.MX28 Time Clock controller

Required properties:
- compatible: should be one of the following.
    * "fsl,stmp3xxx-rtc"
- reg: physical base address of the controller and length of memory mapped
  region.
- interrupts: rtc alarm interrupt

Optional properties:
- stmp,crystal-freq: override crystal frequency as determined from fuse bits.
  Only <32000> and <32768> are possible for the hardware.  Use <0> for
  "no crystal".

Example:

rtc@80056000 {
	compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
	reg = <0x80056000 2000>;
	interrupts = <29>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/sunplus,sp7021-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sunplus SP7021 Real Time Clock controller

maintainers:
  - Vincent Shih <vincent.sunplus@gmail.com>

properties:
  compatible:
    const: sunplus,sp7021-rtc

  reg:
    maxItems: 1

  reg-names:
    items:
      - const: rtc

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - resets
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    rtc: serial@9c003a00 {
        compatible = "sunplus,sp7021-rtc";
        reg = <0x9c003a00 0x80>;
        reg-names = "rtc";
        clocks = <&clkc 0x12>;
        resets = <&rstc 0x02>;
        interrupt-parent = <&intc>;
        interrupts = <163 IRQ_TYPE_EDGE_RISING>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/ti,bq32000.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI BQ32000 I2C Serial Real-Time Clock

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

allOf:
  - $ref: rtc.yaml#

properties:
  compatible:
    const: ti,bq32000

  reg:
    const: 0x68

  interrupts:
    maxItems: 1

  start-year: true

  trickle-resistor-ohms:
    enum: [ 1120, 20180 ]

  trickle-diode-disable: true

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
            #address-cells = <1>;
            #size-cells = <0>;

            bq32000: rtc@68 {
                    compatible = "ti,bq32000";
                    reg = <0x68>;
                    trickle-resistor-ohms = <1120>;
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/ti,k3-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments K3 Real Time Clock

maintainers:
  - Nishanth Menon <nm@ti.com>

description: |
  This RTC appears in the AM62x family of SoCs.

allOf:
  - $ref: "rtc.yaml#"

properties:
  compatible:
    enum:
      - ti,am62-rtc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: VBUS Interface clock
      - description: 32k Clock source (external or internal).

  clock-names:
    items:
      - const: vbus
      - const: osc32k

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    rtc@2b1f0000 {
        compatible = "ti,am62-rtc";
        reg = <0x2b1f0000 0x100>;
        interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
        power-domains = <&bar 0>;
        clocks = <&foo 0>, <&foo 1>;
        clock-names = "vbus", "osc32k";
        wakeup-source;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/trivial-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Trivial RTCs

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

description: |
  This is a list of trivial RTC devices that have simple device tree
  bindings, consisting only of a compatible field, an address and
  possibly an interrupt line.

allOf:
  - $ref: "rtc.yaml#"

properties:
  compatible:
    enum:
      # AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
      - abracon,abb5zes3
      # AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
      - abracon,abeoz9
      # I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
      - dallas,ds1374
      # Dallas DS1672 Real-time Clock
      - dallas,ds1672
      # Extremely Accurate I²C RTC with Integrated Crystal and SRAM
      - dallas,ds3232
      # EM Microelectronic EM3027 RTC
      - emmicro,em3027
      # I2C-BUS INTERFACE REAL TIME CLOCK MODULE
      - epson,rx8010
      # I2C-BUS INTERFACE REAL TIME CLOCK MODULE
      - epson,rx8025
      - epson,rx8035
      # I2C-BUS INTERFACE REAL TIME CLOCK MODULE with Battery Backed RAM
      - epson,rx8571
      # I2C-BUS INTERFACE REAL TIME CLOCK MODULE
      - epson,rx8581
      # Intersil ISL1208 Low Power RTC with Battery Backed SRAM
      - isil,isl1208
      # Intersil ISL1218 Low Power RTC with Battery Backed SRAM
      - isil,isl1218
      # Intersil ISL12022 Real-time Clock
      - isil,isl12022
      # Real Time Clock Module with I2C-Bus
      - microcrystal,rv3028
      # Real Time Clock Module with I2C-Bus
      - microcrystal,rv3029
      # Real Time Clock
      - microcrystal,rv8523
      - nxp,pca2129
      - nxp,pcf2129
      # Real-time Clock Module
      - pericom,pt7c4338
      # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
      - ricoh,r2025sd
      # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
      - ricoh,r2221tl
      # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
      - ricoh,rs5c372a
      # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
      - ricoh,rs5c372b
      # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
      - ricoh,rv5c386
      # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
      - ricoh,rv5c387a
      # 2-wire CMOS real-time clock
      - sii,s35390a
      # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
      - whwave,sd3078
      # Xircom X1205 I2C RTC
      - xircom,x1205

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  start-year: true

required:
  - compatible
  - reg

additionalProperties: false

...


code:
* Texas Instruments TWL4030/6030 RTC

Required properties:
- compatible : Should be "ti,twl4030-rtc"
- interrupts : Should be the interrupt number.

Example:
	rtc {
		compatible = "ti,twl4030-rtc";
		interrupts = <11>;
	};


code:
VIA/Wondermedia VT8500 Realtime Clock Controller
-----------------------------------------------------

Required properties:
- compatible : "via,vt8500-rtc"
- reg : Should contain 1 register ranges(address and length)
- interrupts : alarm interrupt

Example:

	rtc@d8100000 {
		compatible = "via,vt8500-rtc";
		reg = <0xd8100000 0x10000>;
		interrupts = <48>;
	};


code:
* APM X-Gene Real Time Clock

RTC controller for the APM X-Gene Real Time Clock

Required properties:
- compatible : Should be "apm,xgene-rtc"
- reg: physical base address of the controller and length of memory mapped
  region.
- interrupts: IRQ line for the RTC.
- #clock-cells: Should be 1.
- clocks: Reference to the clock entry.

Example:

rtcclk: rtcclk {
	compatible = "fixed-clock";
	#clock-cells = <1>;
	clock-frequency = <100000000>;
	clock-output-names = "rtcclk";
};

rtc: rtc@10510000 {
	compatible = "apm,xgene-rtc";
	reg = <0x0 0x10510000 0x0 0x400>;
	interrupts = <0x0 0x46 0x4>;
	#clock-cells = <1>;
	clocks = <&rtcclk 0>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock

description:
  RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
  The RTC controller has separate IRQ lines for seconds and alarm.

maintainers:
  - Michal Simek <michal.simek@xilinx.com>

allOf:
  - $ref: rtc.yaml#

properties:
  compatible:
    const: xlnx,zynqmp-rtc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: rtc

  interrupts:
    maxItems: 2

  interrupt-names:
    items:
      - const: alarm
      - const: sec

  calibration:
    description: |
      calibration value for 1 sec period which will
      be programmed directly to calibration register.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0x1
    maximum: 0x1FFFFF
    default: 0x198233
    deprecated: true

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      rtc: rtc@ffa60000 {
        compatible = "xlnx,zynqmp-rtc";
        reg = <0x0 0xffa60000 0x0 0x100>;
        interrupt-parent = <&gic>;
        interrupts = <0 26 4>, <0 27 4>;
        interrupt-names = "alarm", "sec";
        calibration = <0x198233>;
        clock-names = "rtc";
        clocks = <&rtc_clk>;
      };
    };