code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DPU dt properties for MSM8998 target

maintainers:
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>

$ref: /schemas/display/msm/dpu-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,msm8998-dpu

  reg:
    items:
      - description: Address offset and size for mdp register set
      - description: Address offset and size for regdma register set
      - description: Address offset and size for vbif register set
      - description: Address offset and size for non-realtime vbif register set

  reg-names:
    items:
      - const: mdp
      - const: regdma
      - const: vbif
      - const: vbif_nrt

  clocks:
    items:
      - description: Display ahb clock
      - description: Display axi clock
      - description: Display mem-noc clock
      - description: Display core clock
      - description: Display vsync clock

  clock-names:
    items:
      - const: iface
      - const: bus
      - const: mnoc
      - const: core
      - const: vsync

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-controller@c901000 {
        compatible = "qcom,msm8998-dpu";
        reg = <0x0c901000 0x8f000>,
              <0x0c9a8e00 0xf0>,
              <0x0c9b0000 0x2008>,
              <0x0c9b8000 0x1040>;
        reg-names = "mdp", "regdma", "vbif", "vbif_nrt";

        clocks = <&mmcc MDSS_AHB_CLK>,
                 <&mmcc MDSS_AXI_CLK>,
                 <&mmcc MNOC_AHB_CLK>,
                 <&mmcc MDSS_MDP_CLK>,
                 <&mmcc MDSS_VSYNC_CLK>;
        clock-names = "iface", "bus", "mnoc", "core", "vsync";

        interrupt-parent = <&mdss>;
        interrupts = <0>;
        operating-points-v2 = <&mdp_opp_table>;
        power-domains = <&rpmpd MSM8998_VDDMX>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                endpoint {
                    remote-endpoint = <&dsi0_in>;
                };
            };

            port@1 {
                reg = <1>;
                endpoint {
                    remote-endpoint = <&dsi1_in>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm MSM8998 Display MDSS

maintainers:
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>

description:
  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  bindings of MDSS are mentioned for MSM8998 target.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,msm8998-mdss

  clocks:
    items:
      - description: Display AHB clock
      - description: Display AXI clock
      - description: Display core clock

  clock-names:
    items:
      - const: iface
      - const: bus
      - const: core

  iommus:
    maxItems: 1

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,msm8998-dpu

  "^dsi@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,mdss-dsi-ctrl

  "^phy@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,dsi-phy-10nm-8998

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
    #include <dt-bindings/clock/qcom,rpmcc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-subsystem@c900000 {
        compatible = "qcom,msm8998-mdss";
        reg = <0x0c900000 0x1000>;
        reg-names = "mdss";

        clocks = <&mmcc MDSS_AHB_CLK>,
                 <&mmcc MDSS_AXI_CLK>,
                 <&mmcc MDSS_MDP_CLK>;
        clock-names = "iface", "bus", "core";

        #address-cells = <1>;
        #interrupt-cells = <1>;
        #size-cells = <1>;

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        iommus = <&mmss_smmu 0>;

        power-domains = <&mmcc MDSS_GDSC>;
        ranges;

        display-controller@c901000 {
            compatible = "qcom,msm8998-dpu";
            reg = <0x0c901000 0x8f000>,
                  <0x0c9a8e00 0xf0>,
                  <0x0c9b0000 0x2008>,
                  <0x0c9b8000 0x1040>;
            reg-names = "mdp", "regdma", "vbif", "vbif_nrt";

            clocks = <&mmcc MDSS_AHB_CLK>,
                     <&mmcc MDSS_AXI_CLK>,
                     <&mmcc MNOC_AHB_CLK>,
                     <&mmcc MDSS_MDP_CLK>,
                     <&mmcc MDSS_VSYNC_CLK>;
            clock-names = "iface", "bus", "mnoc", "core", "vsync";

            interrupt-parent = <&mdss>;
            interrupts = <0>;
            operating-points-v2 = <&mdp_opp_table>;
            power-domains = <&rpmpd MSM8998_VDDMX>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dpu_intf2_out: endpoint {
                        remote-endpoint = <&dsi1_in>;
                    };
                };
            };
        };

        dsi@c994000 {
            compatible = "qcom,mdss-dsi-ctrl";
            reg = <0x0c994000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&mmcc MDSS_BYTE0_CLK>,
                     <&mmcc MDSS_BYTE0_INTF_CLK>,
                     <&mmcc MDSS_PCLK0_CLK>,
                     <&mmcc MDSS_ESC0_CLK>,
                     <&mmcc MDSS_AHB_CLK>,
                     <&mmcc MDSS_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";
            assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmpd MSM8998_VDDCX>;

            phys = <&dsi0_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi0_out: endpoint {
                    };
                };
            };
        };

        dsi0_phy: phy@c994400 {
            compatible = "qcom,dsi-phy-10nm-8998";
            reg = <0x0c994400 0x200>,
                  <0x0c994600 0x280>,
                  <0x0c994a00 0x1e0>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&mmcc MDSS_AHB_CLK>,
                     <&rpmcc RPM_SMD_XO_CLK_SRC>;
            clock-names = "iface", "ref";

            vdds-supply = <&pm8998_l1>;
        };

        dsi@c996000 {
            compatible = "qcom,mdss-dsi-ctrl";
            reg = <0x0c996000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <5>;

            clocks = <&mmcc MDSS_BYTE1_CLK>,
                     <&mmcc MDSS_BYTE1_INTF_CLK>,
                     <&mmcc MDSS_PCLK1_CLK>,
                     <&mmcc MDSS_ESC1_CLK>,
                     <&mmcc MDSS_AHB_CLK>,
                     <&mmcc MDSS_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";
            assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmpd MSM8998_VDDCX>;

            phys = <&dsi1_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi1_in: endpoint {
                        remote-endpoint = <&dpu_intf2_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi1_out: endpoint {
                    };
                };
            };
        };

        dsi1_phy: phy@c996400 {
            compatible = "qcom,dsi-phy-10nm-8998";
            reg = <0x0c996400 0x200>,
                  <0x0c996600 0x280>,
                  <0x0c996a00 0x10e>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&mmcc MDSS_AHB_CLK>,
                     <&rpmcc RPM_SMD_XO_CLK_SRC>;
            clock-names = "iface", "ref";

            vdds-supply = <&pm8998_l1>;
        };
    };
...

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DPU dt properties for QCM2290 target

maintainers:
  - Loic Poulain <loic.poulain@linaro.org>

$ref: /schemas/display/msm/dpu-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,qcm2290-dpu

  reg:
    items:
      - description: Address offset and size for mdp register set
      - description: Address offset and size for vbif register set

  reg-names:
    items:
      - const: mdp
      - const: vbif

  clocks:
    items:
      - description: Display AXI clock from gcc
      - description: Display AHB clock from dispcc
      - description: Display core clock from dispcc
      - description: Display lut clock from dispcc
      - description: Display vsync clock from dispcc

  clock-names:
    items:
      - const: bus
      - const: iface
      - const: core
      - const: lut
      - const: vsync

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
    #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-controller@5e01000 {
        compatible = "qcom,qcm2290-dpu";
        reg = <0x05e01000 0x8f000>,
              <0x05eb0000 0x2008>;
        reg-names = "mdp", "vbif";

        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
        clock-names = "bus", "iface", "core", "lut", "vsync";

        operating-points-v2 = <&mdp_opp_table>;
        power-domains = <&rpmpd QCM2290_VDDCX>;

        interrupt-parent = <&mdss>;
        interrupts = <0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                endpoint {
                    remote-endpoint = <&dsi0_in>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm QCM220 Display MDSS

maintainers:
  - Loic Poulain <loic.poulain@linaro.org>

description:
  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
  are mentioned for QCM2290 target.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,qcm2290-mdss

  clocks:
    items:
      - description: Display AHB clock from gcc
      - description: Display AXI clock
      - description: Display core clock

  clock-names:
    items:
      - const: iface
      - const: bus
      - const: core

  iommus:
    maxItems: 2

  interconnects:
    maxItems: 1

  interconnect-names:
    maxItems: 1

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,qcm2290-dpu

  "^dsi@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,dsi-ctrl-6g-qcm2290

  "^phy@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,dsi-phy-14nm-2290

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
    #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
    #include <dt-bindings/clock/qcom,rpmcc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,qcm2290.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    mdss@5e00000 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "qcom,qcm2290-mdss";
        reg = <0x05e00000 0x1000>;
        reg-names = "mdss";
        power-domains = <&dispcc MDSS_GDSC>;
        clocks = <&gcc GCC_DISP_AHB_CLK>,
                 <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
        clock-names = "iface", "bus", "core";

        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
        interconnect-names = "mdp0-mem";

        iommus = <&apps_smmu 0x420 0x2>,
                 <&apps_smmu 0x421 0x0>;
        ranges;

        display-controller@5e01000 {
            compatible = "qcom,qcm2290-dpu";
            reg = <0x05e01000 0x8f000>,
                  <0x05eb0000 0x2008>;
            reg-names = "mdp", "vbif";

            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            clock-names = "bus", "iface", "core", "lut", "vsync";

            operating-points-v2 = <&mdp_opp_table>;
            power-domains = <&rpmpd QCM2290_VDDCX>;

            interrupt-parent = <&mdss>;
            interrupts = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };
            };
        };

        dsi@5e94000 {
            compatible = "qcom,dsi-ctrl-6g-qcm2290";
            reg = <0x05e94000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";
            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmpd QCM2290_VDDCX>;

            phys = <&dsi0_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi0_out: endpoint {
                    };
                };
            };
        };

        dsi0_phy: phy@5e94400 {
            compatible = "qcom,dsi-phy-14nm-2290";
            reg = <0x05e94400 0x100>,
                  <0x05e94500 0x300>,
                  <0x05e94800 0x188>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
            clock-names = "iface", "ref";
            vcca-supply = <&vreg_dsi_phy>;
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DPU dt properties for SC7180 target

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

$ref: /schemas/display/msm/dpu-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,sc7180-dpu

  reg:
    items:
      - description: Address offset and size for mdp register set
      - description: Address offset and size for vbif register set

  reg-names:
    items:
      - const: mdp
      - const: vbif

  clocks:
    items:
      - description: Display hf axi clock
      - description: Display ahb clock
      - description: Display rotator clock
      - description: Display lut clock
      - description: Display core clock
      - description: Display vsync clock

  clock-names:
    items:
      - const: bus
      - const: iface
      - const: rot
      - const: lut
      - const: core
      - const: vsync

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-controller@ae01000 {
        compatible = "qcom,sc7180-dpu";
        reg = <0x0ae01000 0x8f000>,
              <0x0aeb0000 0x2008>;

        reg-names = "mdp", "vbif";

        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_ROT_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
        clock-names = "bus", "iface", "rot", "lut", "core",
                      "vsync";

        interrupt-parent = <&mdss>;
        interrupts = <0>;
        power-domains = <&rpmhpd SC7180_CX>;
        operating-points-v2 = <&mdp_opp_table>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                endpoint {
                    remote-endpoint = <&dsi0_in>;
                };
            };

            port@2 {
                reg = <2>;
                endpoint {
                    remote-endpoint = <&dp_in>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC7180 Display MDSS

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

description:
  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  bindings of MDSS are mentioned for SC7180 target.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,sc7180-mdss

  clocks:
    items:
      - description: Display AHB clock from gcc
      - description: Display AHB clock from dispcc
      - description: Display core clock

  clock-names:
    items:
      - const: iface
      - const: ahb
      - const: core

  iommus:
    maxItems: 1

  interconnects:
    maxItems: 1

  interconnect-names:
    maxItems: 1

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,sc7180-dpu

  "^displayport-controller@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,sc7180-dp

  "^dsi@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,mdss-dsi-ctrl

  "^phy@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,dsi-phy-10nm

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,sdm845.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-subsystem@ae00000 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "qcom,sc7180-mdss";
        reg = <0xae00000 0x1000>;
        reg-names = "mdss";
        power-domains = <&dispcc MDSS_GDSC>;
        clocks = <&gcc GCC_DISP_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
        clock-names = "iface", "ahb", "core";

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
        interconnect-names = "mdp0-mem";

        iommus = <&apps_smmu 0x800 0x2>;
        ranges;

        display-controller@ae01000 {
            compatible = "qcom,sc7180-dpu";
            reg = <0x0ae01000 0x8f000>,
                  <0x0aeb0000 0x2008>;

            reg-names = "mdp", "vbif";

            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            clock-names = "bus", "iface", "rot", "lut", "core",
                          "vsync";

            interrupt-parent = <&mdss>;
            interrupts = <0>;
            power-domains = <&rpmhpd SC7180_CX>;
            operating-points-v2 = <&mdp_opp_table>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };

                port@2 {
                    reg = <2>;
                    dpu_intf0_out: endpoint {
                        remote-endpoint = <&dp_in>;
                    };
                };
            };
        };

        dsi@ae94000 {
            compatible = "qcom,mdss-dsi-ctrl";
            reg = <0x0ae94000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";

            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmhpd SC7180_CX>;

            phys = <&dsi_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi0_out: endpoint {
                    };
                };
            };

            dsi_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-187500000 {
                    opp-hz = /bits/ 64 <187500000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-300000000 {
                    opp-hz = /bits/ 64 <300000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-358000000 {
                    opp-hz = /bits/ 64 <358000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };
            };
        };

        dsi_phy: phy@ae94400 {
            compatible = "qcom,dsi-phy-10nm";
            reg = <0x0ae94400 0x200>,
                  <0x0ae94600 0x280>,
                  <0x0ae94a00 0x1e0>;
            reg-names = "dsi_phy",
                    "dsi_phy_lane",
                    "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface", "ref";
            vdds-supply = <&vreg_dsi_phy>;
        };

        displayport-controller@ae90000 {
            compatible = "qcom,sc7180-dp";

            reg = <0xae90000 0x200>,
                  <0xae90200 0x200>,
                  <0xae90400 0xc00>,
                  <0xae91000 0x400>,
                  <0xae91400 0x400>;

            interrupt-parent = <&mdss>;
            interrupts = <12>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
                     <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
                     <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
            clock-names = "core_iface", "core_aux", "ctrl_link",
                          "ctrl_link_iface", "stream_pixel";
            assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
            assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
            phys = <&dp_phy>;
            phy-names = "dp";

            operating-points-v2 = <&dp_opp_table>;
            power-domains = <&rpmhpd SC7180_CX>;

            #sound-dai-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;
                port@0 {
                    reg = <0>;
                    dp_in: endpoint {
                        remote-endpoint = <&dpu_intf0_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dp_out: endpoint { };
                };
            };

            dp_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-160000000 {
                    opp-hz = /bits/ 64 <160000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-270000000 {
                    opp-hz = /bits/ 64 <270000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-540000000 {
                    opp-hz = /bits/ 64 <540000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };

                opp-810000000 {
                    opp-hz = /bits/ 64 <810000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DPU dt properties for SC7280

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

$ref: /schemas/display/msm/dpu-common.yaml#

properties:
  compatible:
    const: qcom,sc7280-dpu

  reg:
    items:
      - description: Address offset and size for mdp register set
      - description: Address offset and size for vbif register set

  reg-names:
    items:
      - const: mdp
      - const: vbif

  clocks:
    items:
      - description: Display hf axi clock
      - description: Display sf axi clock
      - description: Display ahb clock
      - description: Display lut clock
      - description: Display core clock
      - description: Display vsync clock

  clock-names:
    items:
      - const: bus
      - const: nrt_bus
      - const: iface
      - const: lut
      - const: core
      - const: vsync

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-controller@ae01000 {
        compatible = "qcom,sc7280-dpu";
        reg = <0x0ae01000 0x8f000>,
              <0x0aeb0000 0x2008>;

        reg-names = "mdp", "vbif";

        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&gcc GCC_DISP_SF_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
        clock-names = "bus",
                      "nrt_bus",
                      "iface",
                      "lut",
                      "core",
                      "vsync";

        interrupt-parent = <&mdss>;
        interrupts = <0>;
        power-domains = <&rpmhpd SC7280_CX>;
        operating-points-v2 = <&mdp_opp_table>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                endpoint {
                    remote-endpoint = <&dsi0_in>;
                };
            };

            port@1 {
                reg = <1>;
                endpoint {
                    remote-endpoint = <&edp_in>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC7280 Display MDSS

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

description:
  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  bindings of MDSS are mentioned for SC7280.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    const: qcom,sc7280-mdss

  clocks:
    items:
      - description: Display AHB clock from gcc
      - description: Display AHB clock from dispcc
      - description: Display core clock

  clock-names:
    items:
      - const: iface
      - const: ahb
      - const: core

  iommus:
    maxItems: 1

  interconnects:
    maxItems: 1

  interconnect-names:
    maxItems: 1

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,sc7280-dpu

  "^displayport-controller@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,sc7280-dp

  "^dsi@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,mdss-dsi-ctrl

  "^edp@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,sc7280-edp

  "^phy@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        enum:
          - qcom,sc7280-dsi-phy-7nm
          - qcom,sc7280-edp-phy

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,sc7280.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-subsystem@ae00000 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "qcom,sc7280-mdss";
        reg = <0xae00000 0x1000>;
        reg-names = "mdss";
        power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
        clocks = <&gcc GCC_DISP_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
        clock-names = "iface",
                      "ahb",
                      "core";

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
        interconnect-names = "mdp0-mem";

        iommus = <&apps_smmu 0x900 0x402>;
        ranges;

        display-controller@ae01000 {
            compatible = "qcom,sc7280-dpu";
            reg = <0x0ae01000 0x8f000>,
                  <0x0aeb0000 0x2008>;

            reg-names = "mdp", "vbif";

            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                     <&gcc GCC_DISP_SF_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            clock-names = "bus",
                          "nrt_bus",
                          "iface",
                          "lut",
                          "core",
                          "vsync";

            interrupt-parent = <&mdss>;
            interrupts = <0>;
            power-domains = <&rpmhpd SC7280_CX>;
            operating-points-v2 = <&mdp_opp_table>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dpu_intf5_out: endpoint {
                        remote-endpoint = <&edp_in>;
                    };
                };

                port@2 {
                    reg = <2>;
                    dpu_intf0_out: endpoint {
                        remote-endpoint = <&dp_in>;
                    };
                };
            };
        };

        dsi@ae94000 {
            compatible = "qcom,mdss-dsi-ctrl";
            reg = <0x0ae94000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";

            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmhpd SC7280_CX>;

            phys = <&mdss_dsi_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi0_out: endpoint {
                    };
                };
            };

            dsi_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-187500000 {
                    opp-hz = /bits/ 64 <187500000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-300000000 {
                    opp-hz = /bits/ 64 <300000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-358000000 {
                    opp-hz = /bits/ 64 <358000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };
            };
        };

        mdss_dsi_phy: phy@ae94400 {
            compatible = "qcom,sc7280-dsi-phy-7nm";
            reg = <0x0ae94400 0x200>,
                  <0x0ae94600 0x280>,
                  <0x0ae94900 0x280>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface", "ref";

            vdds-supply = <&vreg_dsi_supply>;
        };

        edp@aea0000 {
            compatible = "qcom,sc7280-edp";
            pinctrl-names = "default";
            pinctrl-0 = <&edp_hot_plug_det>;

            reg = <0xaea0000 0x200>,
                  <0xaea0200 0x200>,
                  <0xaea0400 0xc00>,
                  <0xaea1000 0x400>;

            interrupt-parent = <&mdss>;
            interrupts = <14>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
                     <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
                     <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
            clock-names = "core_iface",
                          "core_aux",
                          "ctrl_link",
                          "ctrl_link_iface",
                          "stream_pixel";
            assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
            assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;

            phys = <&mdss_edp_phy>;
            phy-names = "dp";

            operating-points-v2 = <&edp_opp_table>;
            power-domains = <&rpmhpd SC7280_CX>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    edp_in: endpoint {
                        remote-endpoint = <&dpu_intf5_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    mdss_edp_out: endpoint { };
                };
            };

            edp_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-160000000 {
                    opp-hz = /bits/ 64 <160000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-270000000 {
                    opp-hz = /bits/ 64 <270000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-540000000 {
                    opp-hz = /bits/ 64 <540000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };

                opp-810000000 {
                    opp-hz = /bits/ 64 <810000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
            };
        };

        mdss_edp_phy: phy@aec2a00 {
            compatible = "qcom,sc7280-edp-phy";

            reg = <0xaec2a00 0x19c>,
                  <0xaec2200 0xa0>,
                  <0xaec2600 0xa0>,
                  <0xaec2000 0x1c0>;

            clocks = <&rpmhcc RPMH_CXO_CLK>,
                     <&gcc GCC_EDP_CLKREF_EN>;
            clock-names = "aux",
                          "cfg_ahb";

            #clock-cells = <1>;
            #phy-cells = <0>;
        };

        displayport-controller@ae90000 {
            compatible = "qcom,sc7280-dp";

            reg = <0xae90000 0x200>,
                  <0xae90200 0x200>,
                  <0xae90400 0xc00>,
                  <0xae91000 0x400>,
                  <0xae91400 0x400>;

            interrupt-parent = <&mdss>;
            interrupts = <12>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
                     <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
                     <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
            clock-names = "core_iface",
                          "core_aux",
                          "ctrl_link",
                          "ctrl_link_iface",
                          "stream_pixel";
            assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
            assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
            phys = <&dp_phy>;
            phy-names = "dp";

            operating-points-v2 = <&dp_opp_table>;
            power-domains = <&rpmhpd SC7280_CX>;

            #sound-dai-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dp_in: endpoint {
                        remote-endpoint = <&dpu_intf0_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dp_out: endpoint { };
                };
            };

            dp_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-160000000 {
                    opp-hz = /bits/ 64 <160000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-270000000 {
                    opp-hz = /bits/ 64 <270000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-540000000 {
                    opp-hz = /bits/ 64 <540000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };

                opp-810000000 {
                    opp-hz = /bits/ 64 <810000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DPU dt properties for SDM845 target

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

$ref: /schemas/display/msm/dpu-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,sdm845-dpu

  reg:
    items:
      - description: Address offset and size for mdp register set
      - description: Address offset and size for vbif register set

  reg-names:
    items:
      - const: mdp
      - const: vbif

  clocks:
    items:
      - description: Display GCC bus clock
      - description: Display ahb clock
      - description: Display axi clock
      - description: Display core clock
      - description: Display vsync clock

  clock-names:
    items:
      - const: gcc-bus
      - const: iface
      - const: bus
      - const: core
      - const: vsync

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-controller@ae01000 {
        compatible = "qcom,sdm845-dpu";
        reg = <0x0ae01000 0x8f000>,
              <0x0aeb0000 0x2008>;
        reg-names = "mdp", "vbif";

        clocks = <&gcc GCC_DISP_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
        clock-names = "gcc-bus", "iface", "bus", "core", "vsync";

        interrupt-parent = <&mdss>;
        interrupts = <0>;
        power-domains = <&rpmhpd SDM845_CX>;
        operating-points-v2 = <&mdp_opp_table>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                endpoint {
                    remote-endpoint = <&dsi0_in>;
                };
            };

            port@1 {
                reg = <1>;
                endpoint {
                    remote-endpoint = <&dsi1_in>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SDM845 Display MDSS

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

description:
  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  bindings of MDSS are mentioned for SDM845 target.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,sdm845-mdss

  clocks:
    items:
      - description: Display AHB clock from gcc
      - description: Display core clock

  clock-names:
    items:
      - const: iface
      - const: core

  iommus:
    maxItems: 2

  interconnects:
    maxItems: 2

  interconnect-names:
    maxItems: 2

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,sdm845-dpu

  "^dsi@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,mdss-dsi-ctrl

  "^phy@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,dsi-phy-10nm

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-subsystem@ae00000 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "qcom,sdm845-mdss";
        reg = <0x0ae00000 0x1000>;
        reg-names = "mdss";
        power-domains = <&dispcc MDSS_GDSC>;

        clocks = <&gcc GCC_DISP_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
        clock-names = "iface", "core";

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        iommus = <&apps_smmu 0x880 0x8>,
                 <&apps_smmu 0xc80 0x8>;
        ranges;

        display-controller@ae01000 {
            compatible = "qcom,sdm845-dpu";
            reg = <0x0ae01000 0x8f000>,
                  <0x0aeb0000 0x2008>;
            reg-names = "mdp", "vbif";

            clocks = <&gcc GCC_DISP_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            clock-names = "gcc-bus", "iface", "bus", "core", "vsync";

            interrupt-parent = <&mdss>;
            interrupts = <0>;
            power-domains = <&rpmhpd SDM845_CX>;
            operating-points-v2 = <&mdp_opp_table>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dpu_intf2_out: endpoint {
                        remote-endpoint = <&dsi1_in>;
                    };
                };
            };
        };

        dsi@ae94000 {
            compatible = "qcom,mdss-dsi-ctrl";
            reg = <0x0ae94000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";
            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmhpd SDM845_CX>;

            phys = <&dsi0_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi0_out: endpoint {
                    };
                };
            };
        };

        dsi0_phy: phy@ae94400 {
            compatible = "qcom,dsi-phy-10nm";
            reg = <0x0ae94400 0x200>,
                  <0x0ae94600 0x280>,
                  <0x0ae94a00 0x1e0>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface", "ref";
            vdds-supply = <&vreg_dsi_phy>;
        };

        dsi@ae96000 {
            compatible = "qcom,mdss-dsi-ctrl";
            reg = <0x0ae96000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <5>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";
            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmhpd SDM845_CX>;

            phys = <&dsi1_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi1_in: endpoint {
                        remote-endpoint = <&dpu_intf2_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi1_out: endpoint {
                    };
                };
            };
        };

        dsi1_phy: phy@ae96400 {
            compatible = "qcom,dsi-phy-10nm";
            reg = <0x0ae96400 0x200>,
                  <0x0ae96600 0x280>,
                  <0x0ae96a00 0x10e>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface", "ref";
            vdds-supply = <&vreg_dsi_phy>;
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DPU dt properties for SM6115 target

maintainers:
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

$ref: /schemas/display/msm/dpu-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,sm6115-dpu

  reg:
    items:
      - description: MDP register set
      - description: VBIF register set

  reg-names:
    items:
      - const: mdp
      - const: vbif

  clocks:
    items:
      - description: Display AXI
      - description: Display AHB
      - description: Display core
      - description: Display lut
      - description: Display rotator
      - description: Display vsync

  clock-names:
    items:
      - const: bus
      - const: iface
      - const: core
      - const: lut
      - const: rot
      - const: vsync

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
    #include <dt-bindings/clock/qcom,gcc-sm6115.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-controller@5e01000 {
        compatible = "qcom,sm6115-dpu";
        reg = <0x05e01000 0x8f000>,
              <0x05eb0000 0x2008>;
        reg-names = "mdp", "vbif";

        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                 <&dispcc DISP_CC_MDSS_ROT_CLK>,
                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
        clock-names = "bus", "iface", "core", "lut", "rot", "vsync";

        operating-points-v2 = <&mdp_opp_table>;
        power-domains = <&rpmpd SM6115_VDDCX>;

        interrupt-parent = <&mdss>;
        interrupts = <0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                endpoint {
                    remote-endpoint = <&dsi0_in>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM6115 Display MDSS

maintainers:
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

description:
  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
  are mentioned for SM6115 target.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,sm6115-mdss

  clocks:
    items:
      - description: Display AHB clock from gcc
      - description: Display AXI clock
      - description: Display core clock

  iommus:
    maxItems: 2

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,sm6115-dpu

  "^dsi@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,dsi-ctrl-6g-qcm2290

  "^phy@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,dsi-phy-14nm-2290

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
    #include <dt-bindings/clock/qcom,gcc-sm6115.h>
    #include <dt-bindings/clock/qcom,rpmcc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    mdss@5e00000 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "qcom,sm6115-mdss";
        reg = <0x05e00000 0x1000>;
        reg-names = "mdss";
        power-domains = <&dispcc MDSS_GDSC>;
        clocks = <&gcc GCC_DISP_AHB_CLK>,
                 <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>;

        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        iommus = <&apps_smmu 0x420 0x2>,
                 <&apps_smmu 0x421 0x0>;
        ranges;

        display-controller@5e01000 {
            compatible = "qcom,sm6115-dpu";
            reg = <0x05e01000 0x8f000>,
                  <0x05eb0000 0x2008>;
            reg-names = "mdp", "vbif";

            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            clock-names = "bus", "iface", "core", "lut", "rot", "vsync";

            operating-points-v2 = <&mdp_opp_table>;
            power-domains = <&rpmpd SM6115_VDDCX>;

            interrupt-parent = <&mdss>;
            interrupts = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };
            };
        };

        dsi@5e94000 {
            compatible = "qcom,dsi-ctrl-6g-qcm2290";
            reg = <0x05e94000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";
            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmpd SM6115_VDDCX>;
            phys = <&dsi0_phy>;

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi0_out: endpoint {
                    };
                };
            };
        };

        dsi0_phy: phy@5e94400 {
            compatible = "qcom,dsi-phy-14nm-2290";
            reg = <0x05e94400 0x100>,
                  <0x05e94500 0x300>,
                  <0x05e94800 0x188>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
            clock-names = "iface", "ref";
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8250 Display DPU

maintainers:
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

$ref: /schemas/display/msm/dpu-common.yaml#

properties:
  compatible:
    const: qcom,sm8250-dpu

  reg:
    items:
      - description: Address offset and size for mdp register set
      - description: Address offset and size for vbif register set

  reg-names:
    items:
      - const: mdp
      - const: vbif

  clocks:
    items:
      - description: Display ahb clock
      - description: Display hf axi clock
      - description: Display core clock
      - description: Display vsync clock

  clock-names:
    items:
      - const: iface
      - const: bus
      - const: core
      - const: vsync

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,sm8250.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-controller@ae01000 {
        compatible = "qcom,sm8250-dpu";
        reg = <0x0ae01000 0x8f000>,
              <0x0aeb0000 0x2008>;
        reg-names = "mdp", "vbif";

        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
        clock-names = "iface", "bus", "core", "vsync";

        assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
        assigned-clock-rates = <19200000>;

        operating-points-v2 = <&mdp_opp_table>;
        power-domains = <&rpmhpd SM8250_MMCX>;

        interrupt-parent = <&mdss>;
        interrupts = <0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                endpoint {
                    remote-endpoint = <&dsi0_in>;
                };
            };

            port@1 {
                reg = <1>;
                endpoint {
                    remote-endpoint = <&dsi1_in>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8250 Display MDSS

maintainers:
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

description:
  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  bindings of MDSS are mentioned for SM8250 target.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    items:
      - const: qcom,sm8250-mdss

  clocks:
    items:
      - description: Display AHB clock from gcc
      - description: Display hf axi clock
      - description: Display sf axi clock
      - description: Display core clock

  clock-names:
    items:
      - const: iface
      - const: bus
      - const: nrt_bus
      - const: core

  iommus:
    maxItems: 1

  interconnects:
    maxItems: 2

  interconnect-names:
    maxItems: 2

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,sm8250-dpu

  "^dsi@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,mdss-dsi-ctrl

  "^phy@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,dsi-phy-7nm

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,sm8250.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-subsystem@ae00000 {
        compatible = "qcom,sm8250-mdss";
        reg = <0x0ae00000 0x1000>;
        reg-names = "mdss";

        interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
                        <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
        interconnect-names = "mdp0-mem", "mdp1-mem";

        power-domains = <&dispcc MDSS_GDSC>;

        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&gcc GCC_DISP_SF_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
        clock-names = "iface", "bus", "nrt_bus", "core";

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        iommus = <&apps_smmu 0x820 0x402>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        display-controller@ae01000 {
            compatible = "qcom,sm8250-dpu";
            reg = <0x0ae01000 0x8f000>,
                  <0x0aeb0000 0x2008>;
            reg-names = "mdp", "vbif";

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            clock-names = "iface", "bus", "core", "vsync";

            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            assigned-clock-rates = <19200000>;

            operating-points-v2 = <&mdp_opp_table>;
            power-domains = <&rpmhpd SM8250_MMCX>;

            interrupt-parent = <&mdss>;
            interrupts = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dpu_intf2_out: endpoint {
                        remote-endpoint = <&dsi1_in>;
                    };
                };
            };

            mdp_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-200000000 {
                    opp-hz = /bits/ 64 <200000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-300000000 {
                    opp-hz = /bits/ 64 <300000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-345000000 {
                    opp-hz = /bits/ 64 <345000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };

                opp-460000000 {
                    opp-hz = /bits/ 64 <460000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
            };
        };

        dsi@ae94000 {
            compatible = "qcom,mdss-dsi-ctrl";
            reg = <0x0ae94000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";

            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmhpd SM8250_MMCX>;

            phys = <&dsi0_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi0_out: endpoint {
                    };
                };
            };

            dsi_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-187500000 {
                    opp-hz = /bits/ 64 <187500000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-300000000 {
                    opp-hz = /bits/ 64 <300000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-358000000 {
                    opp-hz = /bits/ 64 <358000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };
            };
        };

        dsi0_phy: phy@ae94400 {
            compatible = "qcom,dsi-phy-7nm";
            reg = <0x0ae94400 0x200>,
                  <0x0ae94600 0x280>,
                  <0x0ae94900 0x260>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface", "ref";
            vdds-supply = <&vreg_dsi_phy>;
        };

        dsi@ae96000 {
            compatible = "qcom,mdss-dsi-ctrl";
            reg = <0x0ae96000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <5>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";

            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmhpd SM8250_MMCX>;

            phys = <&dsi1_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi1_in: endpoint {
                        remote-endpoint = <&dpu_intf2_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi1_out: endpoint {
                    };
                };
            };
        };

        dsi1_phy: phy@ae96400 {
            compatible = "qcom,dsi-phy-7nm";
            reg = <0x0ae96400 0x200>,
                  <0x0ae96600 0x280>,
                  <0x0ae96900 0x260>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>;
            clock-names = "iface", "ref";
            vdds-supply = <&vreg_dsi_phy>;
        };
    };
...


code:
Multi-Inno MI0283QT display panel

Required properties:
- compatible:	"multi-inno,mi0283qt".

The node for this driver must be a child node of a SPI controller, hence
all mandatory properties described in ../spi/spi-bus.txt must be specified.

Optional properties:
- dc-gpios:	D/C pin. The presence/absence of this GPIO determines
		the panel interface mode (IM[3:0] pins):
		- present: IM=x110 4-wire 8-bit data serial interface
		- absent:  IM=x101 3-wire 9-bit data serial interface
- reset-gpios:	Reset pin
- power-supply:	A regulator node for the supply voltage.
- backlight:	phandle of the backlight device attached to the panel
- rotation:	panel rotation in degrees counter clockwise (0,90,180,270)

Example:
	mi0283qt@0{
		compatible = "multi-inno,mi0283qt";
		reg = <0>;
		spi-max-frequency = <32000000>;
		rotation = <90>;
		dc-gpios = <&gpio 25 0>;
		backlight = <&backlight>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/abt,y030xx067a.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Asia Better Technology 3.0" (320x480 pixels) 24-bit IPS LCD panel

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

allOf:
  - $ref: panel-common.yaml#
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

properties:
  compatible:
    const: abt,y030xx067a

  backlight: true
  port: true
  power-supply: true
  reg: true
  reset-gpios: true

required:
  - compatible
  - reg
  - power-supply
  - reset-gpios

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        panel@0 {
            compatible = "abt,y030xx067a";
            reg = <0>;

            spi-max-frequency = <3125000>;

            reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>;

            backlight = <&backlight>;
            power-supply = <&vcc>;

            port {
                panel_input: endpoint {
                    remote-endpoint = <&panel_output>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/advantech,idk-1110wr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Advantech IDK-1110WR 10.1" WSVGA LVDS Display Panel

maintainers:
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  - Thierry Reding <thierry.reding@gmail.com>

allOf:
  - $ref: panel-common.yaml#
  - $ref: /schemas/display/lvds.yaml/#

select:
  properties:
    compatible:
      contains:
        const: advantech,idk-1110wr

  required:
    - compatible

properties:
  compatible:
    items:
      - const: advantech,idk-1110wr
      - const: panel-lvds

  data-mapping:
    const: jeida-24

  width-mm:
    const: 223

  height-mm:
    const: 125

  panel-timing: true
  port: true

additionalProperties: false

required:
  - compatible
  - data-mapping
  - width-mm
  - height-mm
  - panel-timing
  - port

examples:
  - |+
    panel {
      compatible = "advantech,idk-1110wr", "panel-lvds";

      width-mm = <223>;
      height-mm = <125>;

      data-mapping = "jeida-24";

      panel-timing {
        /* 1024x600 @60Hz */
        clock-frequency = <51200000>;
        hactive = <1024>;
        vactive = <600>;
        hsync-len = <240>;
        hfront-porch = <40>;
        hback-porch = <40>;
        vsync-len = <10>;
        vfront-porch = <15>;
        vback-porch = <10>;
      };

      port {
        panel_in: endpoint {
          remote-endpoint = <&lvds_encoder>;
        };
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/advantech,idk-2121wr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Advantech IDK-2121WR 21.5" Full-HD dual-LVDS panel

maintainers:
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  The IDK-2121WR from Advantech is a Full-HD dual-LVDS panel.
  A dual-LVDS interface is a dual-link connection with even pixels traveling
  on one link, and with odd pixels traveling on the other link.

  The panel expects odd pixels on the first port, and even pixels on the
  second port, therefore the ports must be marked accordingly (with either
  dual-lvds-odd-pixels or dual-lvds-even-pixels).

properties:
  compatible:
    items:
      - const: advantech,idk-2121wr
      - {} # panel-lvds, but not listed here to avoid false select

  width-mm:
    const: 476

  height-mm:
    const: 268

  data-mapping:
    const: vesa-24

  panel-timing: true

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: The sink for odd pixels.
        properties:
          dual-lvds-odd-pixels: true

        required:
          - dual-lvds-odd-pixels

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: The sink for even pixels.
        properties:
          dual-lvds-even-pixels: true

        required:
          - dual-lvds-even-pixels

    required:
      - port@0
      - port@1

additionalProperties: false

required:
  - compatible
  - width-mm
  - height-mm
  - data-mapping
  - panel-timing
  - ports

examples:
  - |+
    panel-lvds {
      compatible = "advantech,idk-2121wr", "panel-lvds";

      width-mm = <476>;
      height-mm = <268>;

      data-mapping = "vesa-24";

      panel-timing {
        clock-frequency = <148500000>;
        hactive = <1920>;
        vactive = <1080>;
        hsync-len = <44>;
        hfront-porch = <88>;
        hback-porch = <148>;
        vfront-porch = <4>;
        vback-porch = <36>;
        vsync-len = <5>;
      };

      ports {
        #address-cells = <1>;
        #size-cells = <0>;

        port@0 {
          reg = <0>;
          dual-lvds-odd-pixels;
          panel_in0: endpoint {
            remote-endpoint = <&lvds0_out>;
          };
        };

        port@1 {
          reg = <1>;
          dual-lvds-even-pixels;
          panel_in1: endpoint {
            remote-endpoint = <&lvds1_out>;
          };
        };
      };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/arm,rtsm-display.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm RTSM Virtual Platforms Display

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    const: arm,rtsm-display

  port: true

required:
  - compatible
  - port

additionalProperties: false

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/arm,versatile-tft-panel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Versatile TFT Panels

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  These panels are connected to the daughterboards found on the
  ARM Versatile reference designs.

  This device node must appear as a child to a "syscon"-compatible
  node.

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    const: arm,versatile-tft-panel

  port: true

required:
  - compatible
  - port

additionalProperties: false

examples:
  - |
    sysreg@0 {
        compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
        reg = <0x00000 0x1000>;

        panel {
            compatible = "arm,versatile-tft-panel";

            port {
                panel_in: endpoint {
                    remote-endpoint = <&foo>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/armadeus,st0700-adapt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Armadeus ST0700 Adapter

description:
  A Santek ST0700I5Y-RBSLW 7.0" WVGA (800x480) TFT with an adapter board.

maintainers:
  - '"Sébastien Szymanski" <sebastien.szymanski@armadeus.com>'
  - Thierry Reding <thierry.reding@gmail.com>

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    const: armadeus,st0700-adapt

  power-supply: true
  backlight: true
  port: true

additionalProperties: false

required:
  - compatible
  - power-supply

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/asus,z00t-tm5p5-nt35596.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASUS Z00T TM5P5 NT35596 5.5" 1080×1920 LCD Panel

maintainers:
  - Konrad Dybcio <konradybcio@gmail.com>

description: |+
  This panel seems to only be found in the Asus Z00T
  smartphone and we have no straightforward way of
  actually getting the correct model number,
  as no schematics are released publicly.

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    const: asus,z00t-tm5p5-n35596
  reg: true
  reset-gpios: true
  vdd-supply:
    description: core voltage supply
  vddio-supply:
    description: vddio supply

required:
  - compatible
  - reg
  - vdd-supply
  - vddio-supply
  - reset-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    dsi {
            #address-cells = <1>;
            #size-cells = <0>;
            panel@0 {
                    reg = <0>;

                    compatible = "asus,z00t-tm5p5-n35596";

                    vdd-supply = <&pm8916_l8>;
                    vddio-supply = <&pm8916_l6>;
                    reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>;
            };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/bananapi,s070wv20-ct16.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Banana Pi 7" (S070WV20-CT16) TFT LCD Panel

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Thierry Reding <thierry.reding@gmail.com>

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    const: bananapi,s070wv20-ct16

  power-supply: true
  backlight: true
  enable-gpios: true
  port: true

additionalProperties: false

required:
  - compatible
  - power-supply

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/boe,bf060y8m-aj0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: BOE BF060Y8M-AJ0 5.99" 1080x2160 AMOLED Panel

maintainers:
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>

description: |
  This is a 5.99" 1080x2160 16.7M Color active matrix AMOLED
  video mode panel module on MIPI-DSI 4-Lane interface, GGRB
  pixel arrangement, 63 micrometers pitch, with an active
  area of 68.04 x 136.08 millimeters.
  Each pixel is divided into red and green dots, or blue and
  green dots, and two pixels share red or blue dots which are
  arranged in vertical stripe.
  The DriverIC for this panel module is SW43404.

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    const: boe,bf060y8m-aj0

  elvdd-supply:
    description: EL Driving positive (VDD) supply (4.40-4.80V)
  elvss-supply:
    description: EL Driving negative (VSS) supply (-5.00V to -1.40V)
  vcc-supply:
    description: Core (TSP) voltage supply (2.70-3.60V)
  vci-supply:
    description: DriverIC Operation supply (2.60-3.60V)
  vddio-supply:
    description: I/O voltage supply (1.62-1.98V)

  port: true
  reg: true
  reset-gpios: true

required:
  - compatible
  - elvdd-supply
  - elvss-supply
  - vcc-supply
  - vci-supply
  - vddio-supply
  - reg
  - reset-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    dsi {
        #address-cells = <1>;
        #size-cells = <0>;
        panel@0 {
            compatible = "boe,bf060y8m-aj0";
            reg = <0>;

            reset-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>;

            vcc-supply = <&disp_vcc_vreg>;
            vddio-supply = <&disp_vddio_vreg>;
            vci-supply = <&disp_vci_vreg>;
            elvdd-supply = <&disp_elvdd_vreg>;
            elvss-supply = <&disp_elvss_vreg>;

            port {
                panel_in: endpoint {
                    remote-endpoint = <&dsi0_out>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/boe,himax8279d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Boe Himax8279d 1200x1920 TFT LCD panel

maintainers:
  - Jerry Han <jerry.han.hq@gmail.com>

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    items:
      - const: boe,himax8279d8p
      - const: boe,himax8279d10p

  backlight: true
  enable-gpios: true
  reg: true

  pp33-gpios:
    maxItems: 1
    description: GPIO for the 3.3v pin that provides the supply voltage

  pp18-gpios:
    maxItems: 1
    description: GPIO for the 1.8v pin that provides the supply voltage

required:
  - compatible
  - reg
  - enable-gpios
  - pp33-gpios
  - pp18-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    dsi {
        #address-cells = <1>;
        #size-cells = <0>;
        panel@0 {
            compatible = "boe,himax8279d8p", "boe,himax8279d10p";
            reg = <0>;
            backlight = <&backlight>;
            enable-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
            pp33-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
            pp18-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/boe,tv101wum-nl6.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: BOE TV101WUM-NL6 DSI Display Panel

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Sam Ravnborg <sam@ravnborg.org>

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    enum:
        # BOE TV101WUM-NL6 10.1" WUXGA TFT LCD panel
      - boe,tv101wum-nl6
        # AUO KD101N80-45NA 10.1" WUXGA TFT LCD panel
      - auo,kd101n80-45na
        # BOE TV101WUM-N53 10.1" WUXGA TFT LCD panel
      - boe,tv101wum-n53
        # AUO B101UAN08.3 10.1" WUXGA TFT LCD panel
      - auo,b101uan08.3
        # BOE TV105WUM-NW0 10.5" WUXGA TFT LCD panel
      - boe,tv105wum-nw0
        # BOE TV110C9M-LL3 10.95" WUXGA TFT LCD panel
      - boe,tv110c9m-ll3
        # INX HJ110IZ-01A 10.95" WUXGA TFT LCD panel
      - innolux,hj110iz-01a

  reg:
    description: the virtual channel number of a DSI peripheral

  enable-gpios:
    description: a GPIO spec for the enable pin

  pp1800-supply:
    description: core voltage supply

  pp3300-supply:
    description: core voltage supply

  avdd-supply:
    description: phandle of the regulator that provides positive voltage

  avee-supply:
    description: phandle of the regulator that provides negative voltage

  backlight:
    description: phandle of the backlight device attached to the panel

  port: true

required:
  - compatible
  - reg
  - enable-gpios
  - pp1800-supply
  - avdd-supply
  - avee-supply

additionalProperties: false

examples:
  - |
    dsi {
        #address-cells = <1>;
        #size-cells = <0>;
        panel@0 {
            compatible = "boe,tv101wum-nl6";
            reg = <0>;
            enable-gpios = <&pio 45 0>;
            avdd-supply = <&ppvarn_lcd>;
            avee-supply = <&ppvarp_lcd>;
            pp1800-supply = <&pp1800_lcd>;
            backlight = <&backlight_lcd0>;
            port {
                panel_in: endpoint {
                    remote-endpoint = <&dsi_out>;
                };
            };
        };
    };

...


code: See display-timings.yaml in this directory.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/display-timings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: display timings bindings

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
  - Sam Ravnborg <sam@ravnborg.org>

description: |
  A display panel may be able to handle several display timings,
  with different resolutions.
  The display-timings node makes it possible to specify the timings
  and to specify the timing that is native for the display.

properties:
  $nodename:
    const: display-timings

  native-mode:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      The default display timing is the one specified as native-mode.
      If no native-mode is specified then the first node is assumed
      to be the native mode.

patternProperties:
  "^timing":
    type: object
    $ref: panel-timing.yaml#

additionalProperties: false

examples:
  - |+

    /*
     * Example that specifies panel timing using minimum, typical,
     * maximum values as commonly used in datasheet description.
     * timing1 is the native-mode.
     */
    display-timings {
        native-mode = <&timing1>;
        timing0 {
            /* 1920x1080p24 */
            clock-frequency = <148500000>;
            hactive = <1920>;
            vactive = <1080>;
            hsync-len = <0 44 60>;
            hfront-porch = <80 88 95>;
            hback-porch = <100 148 160>;
            vfront-porch = <0 4 6>;
            vback-porch = <0 36 50>;
            vsync-len = <0 5 6>;
        };
        timing1 {
            /* 1920x1080p24 */
            clock-frequency = <52000000>;
            hactive = <1920>;
            vactive = <1080>;
            hfront-porch = <25>;
            hback-porch = <25>;
            hsync-len = <0 25 25>;
            vback-porch = <2>;
            vfront-porch = <2>;
            vsync-len = <2>;
            hsync-active = <1>;
            pixelclk-active = <1>;
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/dlc,dlc0700yzg-1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DLC Display Co. DLC0700YZG-1 7.0" WSVGA TFT LCD panel

maintainers:
  - Philipp Zabel <p.zabel@pengutronix.de>
  - Thierry Reding <thierry.reding@gmail.com>

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    const: dlc,dlc0700yzg-1

  reset-gpios: true
  enable-gpios: true
  backlight: true
  port: true

additionalProperties: false

required:
  - compatible
  - power-supply

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/ebbg,ft8719.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: EBBG FT8719 MIPI-DSI LCD panel

maintainers:
  - Joel Selvaraj <jo@jsfamily.in>

description: |
  The FT8719 panel from EBBG is a FHD+ LCD display panel with a resolution
  of 1080x2246. It is a video mode DSI panel. The backlight is managed
  through the QCOM WLED driver.

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    const: ebbg,ft8719

  reg:
    maxItems: 1
    description: DSI virtual channel of the peripheral

  vddio-supply:
    description: power IC supply regulator

  vddpos-supply:
    description: positive boost supply regulator

  vddneg-supply:
    description: negative boost supply regulator

required:
  - compatible
  - reg
  - vddio-supply
  - vddpos-supply
  - vddneg-supply
  - reset-gpios
  - port

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    dsi {
      #address-cells = <1>;
      #size-cells = <0>;

      panel@0 {
        compatible = "ebbg,ft8719";
        reg = <0>;

        vddio-supply = <&vreg_l14a_1p88>;
        vddpos-supply = <&lab>;
        vddneg-supply = <&ibb>;

        reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;

        backlight = <&pmi8998_wled>;

        port {
          ebbg_ft8719_in_0: endpoint {
            remote-endpoint = <&dsi0_out>;
          };
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/elida,kd35t133.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Elida KD35T133 3.5in 320x480 DSI panel

maintainers:
  - Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    const: elida,kd35t133
  reg: true
  backlight: true
  reset-gpios: true
  iovcc-supply:
    description: regulator that supplies the iovcc voltage
  vdd-supply:
    description: regulator that supplies the vdd voltage

required:
  - compatible
  - reg
  - backlight
  - iovcc-supply
  - vdd-supply

additionalProperties: false

examples:
  - |
    dsi {
        #address-cells = <1>;
        #size-cells = <0>;
        panel@0 {
            compatible = "elida,kd35t133";
            reg = <0>;
            backlight = <&backlight>;
            iovcc-supply = <&vcc_1v8>;
            vdd-supply = <&vcc3v3_lcd>;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/feixin,k101-im2ba02.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Feixin K101 IM2BA02 10.1" MIPI-DSI LCD panel

maintainers:
  - Icenowy Zheng <icenowy@aosc.io>

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    const: feixin,k101-im2ba02
  reg: true
  backlight: true
  reset-gpios: true
  avdd-supply:
    description: regulator that supplies the AVDD voltage
  dvdd-supply:
    description: regulator that supplies the DVDD voltage
  cvdd-supply:
    description: regulator that supplies the CVDD voltage

required:
  - compatible
  - reg
  - avdd-supply
  - dvdd-supply
  - cvdd-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    dsi {
        #address-cells = <1>;
        #size-cells = <0>;
        panel@0 {
            compatible = "feixin,k101-im2ba02";
            reg = <0>;
            avdd-supply = <&reg_dc1sw>;
            dvdd-supply = <&reg_dc1sw>;
            cvdd-supply = <&reg_ldo_io1>;
            reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>;
            backlight = <&backlight>;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/feiyang,fy07024di26a30d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Feiyang FY07024DI26A30-D 7" MIPI-DSI LCD Panel

maintainers:
  - Jagan Teki <jagan@amarulasolutions.com>

allOf:
  - $ref: panel-common.yaml#

properties:
  compatible:
    const: feiyang,fy07024di26a30d

  reg:
    description: DSI virtual channel used by that screen
    maxItems: 1

  avdd-supply:
    description: analog regulator dc1 switch

  dvdd-supply:
    description: 3v3 digital regulator

  reset-gpios: true

  backlight: true

required:
  - compatible
  - reg
  - avdd-supply
  - dvdd-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    dsi {
        #address-cells = <1>;
        #size-cells = <0>;

        panel@0 {
            compatible = "feiyang,fy07024di26a30d";
            reg = <0>;
            avdd-supply = <&reg_dc1sw>;
            dvdd-supply = <&reg_dldo2>;
            reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */
            backlight = <&backlight>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/ilitek,ili9163.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ilitek ILI9163 display panels device tree bindings

maintainers:
  - Daniel Mack <daniel@zonque.org>

description:
  This binding is for display panels using an Ilitek ILI9163 controller in SPI
  mode.

allOf:
  - $ref: panel-common.yaml#
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

properties:
  compatible:
    items:
      - enum:
          - newhaven,1.8-128160EF
      - const: ilitek,ili9163

  spi-max-frequency:
    maximum: 32000000

  dc-gpios:
    maxItems: 1
    description: Display data/command selection (D/CX)

  backlight: true
  reg: true
  reset-gpios: true
  rotation: true

required:
  - compatible
  - reg
  - dc-gpios
  - reset-gpios

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    backlight: backlight {
            compatible = "gpio-backlight";
            gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
    };
    spi {
            #address-cells = <1>;
            #size-cells = <0>;

            display@0 {
                    compatible = "newhaven,1.8-128160EF", "ilitek,ili9163";
                    reg = <0>;
                    spi-max-frequency = <32000000>;
                    dc-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
                    reset-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
                    rotation = <180>;
                    backlight = <&backlight>;
            };
    };

...