code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive Platform-Level Interrupt Controller (PLIC)

description:
  SiFive SoCs and other RISC-V SoCs include an implementation of the
  Platform-Level Interrupt Controller (PLIC) high-level specification in
  the RISC-V Privileged Architecture specification. The PLIC connects all
  external interrupts in the system to all hart contexts in the system, via
  the external interrupt source in each hart.

  A hart context is a privilege mode in a hardware execution thread. For example,
  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
  privilege modes per hart; machine mode and supervisor mode.

  Each interrupt can be enabled on per-context basis. Any context can claim
  a pending enabled interrupt and then release it once it has been handled.

  Each interrupt has a configurable priority. Higher priority interrupts are
  serviced first.  Each context can specify a priority threshold. Interrupts
  with priority below this threshold will not cause the PLIC to raise its
  interrupt line leading to the context.

  The PLIC supports both edge-triggered and level-triggered interrupts. For
  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
  seen while an interrupt handler is active; the PLIC may either queue them or
  ignore them. In the first case, handlers are oblivious to the trigger type, so
  it is not included in the interrupt specifier. In the second case, software
  needs to know the trigger type, so it can reorder the interrupt flow to avoid
  missing interrupts. This special handling is needed by at least the Renesas
  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.

  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
  contains a specific memory layout, which is documented in chapter 8 of the
  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.

  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
  T-HEAD PLIC implementation requires setting a delegation bit to allow access
  from S-mode. So add thead,c900-plic to distinguish them.

maintainers:
  - Sagar Kadam <sagar.kadam@sifive.com>
  - Paul Walmsley  <paul.walmsley@sifive.com>
  - Palmer Dabbelt <palmer@dabbelt.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,r9a07g043-plic
          - const: andestech,nceplic100
      - items:
          - enum:
              - sifive,fu540-c000-plic
              - starfive,jh7100-plic
              - canaan,k210-plic
          - const: sifive,plic-1.0.0
      - items:
          - enum:
              - allwinner,sun20i-d1-plic
          - const: thead,c900-plic
      - items:
          - const: sifive,plic-1.0.0
          - const: riscv,plic0
        deprecated: true
        description: For the QEMU virt machine only

  reg:
    maxItems: 1

  '#address-cells':
    const: 0

  '#interrupt-cells': true

  interrupt-controller: true

  interrupts-extended:
    minItems: 1
    maxItems: 15872
    description:
      Specifies which contexts are connected to the PLIC, with "-1" specifying
      that a context is not present. Each node pointed to should be a
      riscv,cpu-intc node, which has a riscv node as parent.

  riscv,ndev:
    $ref: "/schemas/types.yaml#/definitions/uint32"
    description:
      Specifies how many external interrupts are supported by this controller.

  clocks: true

  power-domains: true

  resets: true

required:
  - compatible
  - '#address-cells'
  - '#interrupt-cells'
  - interrupt-controller
  - reg
  - interrupts-extended
  - riscv,ndev

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - andestech,nceplic100
              - thead,c900-plic

    then:
      properties:
        '#interrupt-cells':
          const: 2

    else:
      properties:
        '#interrupt-cells':
          const: 1

  - if:
      properties:
        compatible:
          contains:
            const: renesas,r9a07g043-plic

    then:
      properties:
        clocks:
          maxItems: 1

        power-domains:
          maxItems: 1

        resets:
          maxItems: 1

      required:
        - clocks
        - power-domains
        - resets

additionalProperties: false

examples:
  - |
    plic: interrupt-controller@c000000 {
      #address-cells = <0>;
      #interrupt-cells = <1>;
      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
      interrupt-controller;
      interrupts-extended = <&cpu0_intc 11>,
                            <&cpu1_intc 11>, <&cpu1_intc 9>,
                            <&cpu2_intc 11>, <&cpu2_intc 9>,
                            <&cpu3_intc 11>, <&cpu3_intc 9>,
                            <&cpu4_intc 11>, <&cpu4_intc 9>;
      reg = <0xc000000 0x4000000>;
      riscv,ndev = <10>;
    };


code:
* ARC700 incore Interrupt Controller

  The core interrupt controller provides 32 prioritised interrupts (2 levels)
  to ARC700 core.

Properties:

- compatible: "snps,arc700-intc"
- interrupt-controller: This is an interrupt controller.
- #interrupt-cells: Must be <1>.

  Single Cell "interrupts" property of a device specifies the IRQ number
  between 0 to 31

  intc accessed via the special ARC AUX register interface, hence "reg" property
  is not specified.

Example:

	intc: interrupt-controller {
		compatible = "snps,arc700-intc";
		interrupt-controller;
		#interrupt-cells = <1>;
	};

repo_name: angery/linux


code:
* ARC-HS Interrupt Distribution Unit

  This optional 2nd level interrupt controller can be used in SMP configurations
  for dynamic IRQ routing, load balancing of common/external IRQs towards core
  intc.

Properties:

- compatible: "snps,archs-idu-intc"
- interrupt-controller: This is an interrupt controller.
- #interrupt-cells: Must be <1> or <2>.

  Value of the first cell specifies the "common" IRQ from peripheral to IDU.
  Number N of the particular interrupt line of IDU corresponds to the line N+24
  of the core interrupt controller.

  The (optional) second cell specifies any of the following flags:
    - bits[3:0] trigger type and level flags
        1 = low-to-high edge triggered
        2 = NOT SUPPORTED (high-to-low edge triggered)
        4 = active high level-sensitive <<< DEFAULT
        8 = NOT SUPPORTED (active low level-sensitive)
  When no second cell is specified, the interrupt is assumed to be level
  sensitive.

  The interrupt controller is accessed via the special ARC AUX register
  interface, hence "reg" property is not specified.

Example:
	core_intc: core-interrupt-controller {
		compatible = "snps,archs-intc";
		interrupt-controller;
		#interrupt-cells = <1>;
	};

	idu_intc: idu-interrupt-controller {
		compatible = "snps,archs-idu-intc";
		interrupt-controller;
		interrupt-parent = <&core_intc>;
		#interrupt-cells = <1>;
	};

	some_device: serial@c0fc1000 {
		interrupt-parent = <&idu_intc>;
		interrupts = <0>;	/* upstream idu IRQ #24 */
	};


code:
* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)

Properties:

- compatible: "snps,archs-intc"
- interrupt-controller: This is an interrupt controller.
- #interrupt-cells: Must be <1>.

  Single Cell "interrupts" property of a device specifies the IRQ number
  between 16 to 256

  intc accessed via the special ARC AUX register interface, hence "reg" property
  is not specified.

Example:

	intc: interrupt-controller {
		compatible = "snps,archs-intc";
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupts = <16 17 18 19 20 21 22 23 24 25>;
	};


code:
Synopsys DesignWare APB interrupt controller (dw_apb_ictl)

Synopsys DesignWare provides interrupt controller IP for APB known as
dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
controller in some SoCs, e.g. Hisilicon SD5203.

Required properties:
- compatible: shall be "snps,dw-apb-ictl"
- reg: physical base address of the controller and length of memory mapped
  region starting with ENABLE_LOW register
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1

Additional required property when it's used as secondary interrupt controller:
- interrupts: interrupt reference to primary interrupt controller

The interrupt sources map to the corresponding bits in the interrupt
registers, i.e.
- 0 maps to bit 0 of low interrupts,
- 1 maps to bit 1 of low interrupts,
- 32 maps to bit 0 of high interrupts,
- 33 maps to bit 1 of high interrupts,
- (optional) fast interrupts start at 64.

Example:
	/* dw_apb_ictl is used as secondary interrupt controller */
	aic: interrupt-controller@3000 {
		compatible = "snps,dw-apb-ictl";
		reg = <0x3000 0xc00>;
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	};

	/* dw_apb_ictl is used as primary interrupt controller */
	vic: interrupt-controller@10130000 {
		compatible = "snps,dw-apb-ictl";
		reg = <0x10130000 0x1000>;
		interrupt-controller;
		#interrupt-cells = <1>;
	};


code:
Socionext SynQuacer External Interrupt Unit (EXIU)

The Socionext Synquacer SoC has an external interrupt unit (EXIU)
that forwards a block of 32 configurable input lines to 32 adjacent
level-high type GICv3 SPIs.

Required properties:

- compatible           : Should be "socionext,synquacer-exiu".
- reg                  : Specifies base physical address and size of the
                         control registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells     : Specifies the number of cells needed to encode an
                         interrupt source. The value must be 3.
- socionext,spi-base   : The SPI number of the first SPI of the 32 adjacent
                         ones the EXIU forwards its interrups to.

Notes:

- Only SPIs can use the EXIU as an interrupt parent.

Example:

	exiu: interrupt-controller@510c0000 {
		compatible = "socionext,synquacer-exiu";
		reg = <0x0 0x510c0000 0x0 0x20>;
		interrupt-controller;
		interrupt-parent = <&gic>;
		#interrupt-cells = <3>;
		socionext,spi-base = <112>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/socionext,uniphier-aidet.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UniPhier AIDET

description: |
  UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC
  (Generic Interrupt Controller). GIC itself can handle only high level and
  rising edge interrupts. The AIDET provides logic inverter to support low
  level and falling edge interrupts.

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    enum:
      - socionext,uniphier-ld4-aidet
      - socionext,uniphier-pro4-aidet
      - socionext,uniphier-sld8-aidet
      - socionext,uniphier-pro5-aidet
      - socionext,uniphier-pxs2-aidet
      - socionext,uniphier-ld6b-aidet
      - socionext,uniphier-ld11-aidet
      - socionext,uniphier-ld20-aidet
      - socionext,uniphier-pxs3-aidet
      - socionext,uniphier-nx1-aidet

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    description: |
      The first cell defines the interrupt number (corresponds to the SPI
      interrupt number of GIC). The second cell specifies the trigger type as
      defined in interrupts.txt in this directory.
    const: 2

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'

additionalProperties: false

examples:
  - |
    interrupt-controller@5fc20000 {
        compatible = "socionext,uniphier-pro4-aidet";
        reg = <0x5fc20000 0x200>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };


code:
* SPEAr Shared IRQ layer (shirq)

SPEAr3xx architecture includes shared/multiplexed irqs for certain set
of devices. The multiplexor provides a single interrupt to parent
interrupt controller (VIC) on behalf of a group of devices.

There can be multiple groups available on SPEAr3xx variants but not
exceeding 4. The number of devices in a group can differ, further they
may share same set of status/mask registers spanning across different
bit masks. Also in some cases the group may not have enable or other
registers. This makes software little complex.

A single node in the device tree is used to describe the shared
interrupt multiplexor (one node for all groups). A group in the
interrupt controller shares config/control registers with other groups.
For example, a 32-bit interrupt enable/disable config register can
accommodate up to 4 interrupt groups.

Required properties:
  - compatible: should be, either of
     - "st,spear300-shirq"
     - "st,spear310-shirq"
     - "st,spear320-shirq"
  - interrupt-controller: Identifies the node as an interrupt controller.
  - #interrupt-cells: should be <1> which basically contains the offset
    (starting from 0) of interrupts for all the groups.
  - reg: Base address and size of shirq registers.
  - interrupts: The list of interrupts generated by the groups which are
    then connected to a parent interrupt controller. Each group is
    associated with one of the interrupts, hence number of interrupts (to
    parent) is equal to number of groups. The format of the interrupt
    specifier depends in the interrupt parent controller.

Example:

The following is an example from the SPEAr320 SoC dtsi file.

shirq: interrupt-controller@b3000000 {
	compatible = "st,spear320-shirq";
	reg = <0xb3000000 0x1000>;
	interrupts = <28 29 30 1>;
	#interrupt-cells = <1>;
	interrupt-controller;
};


code:
STMicroelectronics STi System Configuration Controlled IRQs
-----------------------------------------------------------

On STi based systems; External, CTI (Core Sight), PMU (Performance Management),
and PL310 L2 Cache IRQs are controlled using System Configuration registers.
This driver is used to unmask them prior to use.

Required properties:
- compatible	: Should be set to one of:
			"st,stih415-irq-syscfg"
			"st,stih416-irq-syscfg"
			"st,stih407-irq-syscfg"
			"st,stid127-irq-syscfg"
- st,syscfg	: Phandle to Cortex-A9 IRQ system config registers
- st,irq-device	: Array of IRQs to enable - should be 2 in length
- st,fiq-device	: Array of FIQs to enable - should be 2 in length

Optional properties:
- st,invert-ext	: External IRQs can be inverted at will.  This property inverts
		  these IRQs using bitwise logic.  A number of defines have been
		  provided for convenience:
			ST_IRQ_SYSCFG_EXT_1_INV
			ST_IRQ_SYSCFG_EXT_2_INV
			ST_IRQ_SYSCFG_EXT_3_INV
Example:

irq-syscfg {
	compatible    = "st,stih416-irq-syscfg";
	st,syscfg     = <&syscfg_cpu>;
	st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
			<ST_IRQ_SYSCFG_PMU_1>;
	st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
			<ST_IRQ_SYSCFG_DISABLED>;
	st,invert-ext = <(ST_IRQ_SYSCFG_EXT_1_INV | ST_IRQ_SYSCFG_EXT_3_INV)>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/st,stm32-exti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STM32 External Interrupt Controller

maintainers:
  - Alexandre Torgue <alexandre.torgue@foss.st.com>
  - Ludovic Barre <ludovic.barre@foss.st.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - st,stm32-exti
              - st,stm32h7-exti
      - items:
          - enum:
              - st,stm32mp1-exti
              - st,stm32mp13-exti
          - const: syscon

  "#interrupt-cells":
    const: 2

  reg:
    maxItems: 1

  interrupt-controller: true

  hwlocks:
    maxItems: 1
    description:
      Reference to a phandle of a hardware spinlock provider node.

  interrupts:
    minItems: 1
    maxItems: 96
    description:
      Interrupts references to primary interrupt controller

required:
  - "#interrupt-cells"
  - compatible
  - reg
  - interrupt-controller

allOf:
  - $ref: /schemas/interrupt-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - st,stm32-exti
    then:
      properties:
        interrupts:
          minItems: 1
          maxItems: 32
      required:
        - interrupts
  - if:
      properties:
        compatible:
          contains:
            enum:
              - st,stm32h7-exti
    then:
      properties:
        interrupts:
          minItems: 1
          maxItems: 96
      required:
        - interrupts

additionalProperties: false

examples:
  - |
    //Example 1
    exti1: interrupt-controller@5000d000 {
        compatible = "st,stm32mp1-exti", "syscon";
        interrupt-controller;
        #interrupt-cells = <2>;
        reg = <0x5000d000 0x400>;
    };

    //Example 2
    exti2: interrupt-controller@40013c00 {
        compatible = "st,stm32-exti";
        interrupt-controller;
        #interrupt-cells = <2>;
        reg = <0x40013C00 0x400>;
        interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sunplus SP7021 SoC Interrupt Controller

maintainers:
  - Qin Jian <qinjian@cqplus1.com>

properties:
  compatible:
    items:
      - const: sunplus,sp7021-intc

  reg:
    maxItems: 2
    description:
      Specifies base physical address(s) and size of the controller regs.
      The 1st region include type/polarity/priority/mask regs.
      The 2nd region include clear/masked_ext0/masked_ext1/group regs.

  interrupt-controller: true

  "#interrupt-cells":
    const: 2
    description:
      The first cell is the IRQ number, the second cell is the trigger
      type as defined in interrupt.txt in this directory.

  interrupts:
    maxItems: 2
    description:
      EXT_INT0 & EXT_INT1, 2 interrupts references to primary interrupt
      controller.

required:
  - compatible
  - reg
  - interrupt-controller
  - "#interrupt-cells"
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    intc: interrupt-controller@9c000780 {
        compatible = "sunplus,sp7021-intc";
        reg = <0x9c000780 0x80>, <0x9c000a80 0x80>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupt-parent = <&gic>;
        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */
                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */
    };

...


code:
TS-4800 FPGA interrupt controller

TS-4800 FPGA has an internal interrupt controller. When one of the
interrupts is triggered, the SoC is notified, usually using a GPIO as
parent interrupt source.

Required properties:
- compatible: should be "technologic,ts4800-irqc"
- interrupt-controller: identifies the node as an interrupt controller
- reg: physical base address of the controller and length of memory mapped
  region
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
  source, should be 1.
- interrupts: specifies the interrupt line in the interrupt-parent controller


code:
* TI Common Platform Interrupt Controller

Common Platform Interrupt Controller (cp_intc) is used on
OMAP-L1x SoCs and can support several configurable number
of interrupts.

Main node required properties:

- compatible : should be:
	"ti,cp-intc"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The type shall be a <u32> and the value shall be 1.

  The cell contains the interrupt number in the range [0-128].
- ti,intc-size: Number of interrupts handled by the interrupt controller.
- reg: physical base address and size of the intc registers map.

Example:

	intc: interrupt-controller@1 {
		compatible = "ti,cp-intc";
		interrupt-controller;
		#interrupt-cells = <1>;
		ti,intc-size = <101>;
		reg = <0xfffee000 0x2000>;
	};


code:
Keystone 2 IRQ controller IP

On Keystone SOCs, DSP cores can send interrupts to ARM
host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
The IRQ handler running on HOST OS can identify DSP signal source by
analyzing SRCCx bits in IPCARx registers. This is one of the component
used by the IPC mechanism used on Keystone SOCs.

Required Properties:
- compatible: should be "ti,keystone-irq"
- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
			access device control registers and the offset inside
			device control registers range.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
					 source should be 1.
- interrupts: interrupt reference to primary interrupt controller

Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.

Example:
	kirq0: keystone_irq0@26202a0 {
		compatible = "ti,keystone-irq";
		ti,syscon-dev = <&devctrl 0x2a0>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
		interrupt-controller;
		#interrupt-cells = <1>;
	};

	dsp0: dsp0 {
		compatible = "linux,rproc-user";
		...
		interrupt-parent = <&kirq0>;
		interrupts = <10 2>;
	};


code:
Omap2/3 intc controller

On TI omap2 and 3 the intc interrupt controller can provide
96 or 128 IRQ signals to the ARM host depending on the SoC.

Required Properties:
- compatible: should be one of
			"ti,omap2-intc"
			"ti,omap3-intc"
			"ti,dm814-intc"
			"ti,dm816-intc"
			"ti,am33xx-intc"

- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
		     source, should be 1 for intc
- interrupts: interrupt reference to primary interrupt controller

Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.

Example:
	intc: interrupt-controller@48200000 {
		compatible = "ti,omap3-intc";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x48200000 0x1000>;
	};


code:
* OMAP Interrupt Controller

OMAP2/3 are using a TI interrupt controller that can support several
configurable number of interrupts.

Main node required properties:

- compatible : should be:
	"ti,omap2-intc"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The type shall be a <u32> and the value shall be 1.

  The cell contains the interrupt number in the range [0-128].
- ti,intc-size: Number of interrupts handled by the interrupt controller.
- reg: physical base address and size of the intc registers map.

Example:

	intc: interrupt-controller@1 {
		compatible = "ti,omap2-intc";
		interrupt-controller;
		#interrupt-cells = <1>;
		ti,intc-size = <96>;
		reg = <0x48200000 0x1000>;
	};


code:
TI OMAP4 Wake-up Generator

All TI OMAP4/5 (and their derivatives) an interrupt controller that
routes interrupts to the GIC, and also serves as a wakeup source. It
is also referred to as "WUGEN-MPU", hence the name of the binding.

Required properties:

- compatible : should contain at least "ti,omap4-wugen-mpu" or
  "ti,omap5-wugen-mpu"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The value must be 3.

Notes:

- Because this HW ultimately routes interrupts to the GIC, the
  interrupt specifier must be that of the GIC.
- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
  are explicitly forbidden.

Example:

       wakeupgen: interrupt-controller@48281000 {
               compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
               interrupt-controller;
               #interrupt-cells = <3>;
               reg = <0x48281000 0x1000>;
               interrupt-parent = <&gic>;
       };


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI PRU-ICSS Local Interrupt Controller

maintainers:
  - Suman Anna <s-anna@ti.com>

description: |
  Each PRU-ICSS has a single interrupt controller instance that is common
  to all the PRU cores. Most interrupt controllers can route 64 input events
  which are then mapped to 10 possible output interrupts through two levels
  of mapping. The input events can be triggered by either the PRUs and/or
  various other PRUSS internal and external peripherals. The first 2 output
  interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
  remaining 8 (2 through 9) connected to external interrupt controllers
  including the MPU and/or other PRUSS instances, DSPs or devices.

  The property "ti,irqs-reserved" is used for denoting the connection
  differences on the output interrupts 2 through 9. If this property is not
  defined, it implies that all the PRUSS INTC output interrupts 2 through 9
  (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt
  controller.

  The K3 family of SoCs can handle 160 input events that can be mapped to 20
  different possible output interrupts. The additional output interrupts (10
  through 19) are connected to new sub-modules within the ICSSG instances.

  This interrupt-controller node should be defined as a child node of the
  corresponding PRUSS node. The node should be named "interrupt-controller".

properties:
  $nodename:
    pattern: "^interrupt-controller@[0-9a-f]+$"

  compatible:
    enum:
      - ti,pruss-intc
      - ti,icssg-intc
    description: |
      Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,
                              AM335x family of SoCs,
                              AM437x family of SoCs,
                              AM57xx family of SoCs
                              66AK2G family of SoCs
      Use "ti,icssg-intc" for K3 AM65x, J721E and AM64x family of SoCs

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 8
    description: |
      All the interrupts generated towards the main host processor in the SoC.
      A shared interrupt can be skipped if the desired destination and usage is
      by a different processor/device.

  interrupt-names:
    minItems: 1
    maxItems: 8
    items:
      pattern: host_intr[0-7]
    description: |
      Should use one of the above names for each valid host event interrupt
      connected to Arm interrupt controller, the name should match the
      corresponding host event interrupt number.

  interrupt-controller: true

  "#interrupt-cells":
    const: 3
    description: |
      Client users shall use the PRU System event number (the interrupt source
      that the client is interested in) [cell 1], PRU channel [cell 2] and PRU
      host_event (target) [cell 3] as the value of the interrupts property in
      their node.  The system events can be mapped to some output host
      interrupts through 2 levels of many-to-one mapping i.e. events to channel
      mapping and channels to host interrupts so through this property entire
      mapping is provided.

  ti,irqs-reserved:
    $ref: /schemas/types.yaml#/definitions/uint8
    description: |
      Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC
      output interrupts 2 through 9) that are not connected to the Arm interrupt
      controller or are shared and used by other devices or processors in the
      SoC. Define this property when any of 8 interrupts should not be handled
      by Arm interrupt controller.
        Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt
              connected to MPU
            - AM65x and J721E SoCs have "host_intr5", "host_intr6" and
              "host_intr7" interrupts connected to MPU, and other ICSSG
              instances.
            - AM64x SoCs have all the 8 host interrupts connected to various
              other SoC entities

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - interrupt-controller
  - "#interrupt-cells"

additionalProperties: false

examples:
  - |
    /* AM33xx PRU-ICSS */
    pruss: pruss@0 {
        compatible = "ti,am3356-pruss";
        reg = <0x0 0x80000>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        pruss_intc: interrupt-controller@20000 {
            compatible = "ti,pruss-intc";
            reg = <0x20000 0x2000>;
            interrupts = <20 21 22 23 24 25 26 27>;
            interrupt-names = "host_intr0", "host_intr1",
                              "host_intr2", "host_intr3",
                              "host_intr4", "host_intr5",
                              "host_intr6", "host_intr7";
            interrupt-controller;
            #interrupt-cells = <3>;
        };
    };

  - |

    /* AM4376 PRU-ICSS */
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pruss@0 {
        compatible = "ti,am4376-pruss1";
        reg = <0x0 0x40000>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        interrupt-controller@20000 {
            compatible = "ti,pruss-intc";
            reg = <0x20000 0x2000>;
            interrupt-controller;
            #interrupt-cells = <3>;
            interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "host_intr0", "host_intr1",
                              "host_intr2", "host_intr3",
                              "host_intr4",
                              "host_intr6", "host_intr7";
            ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments K3 Interrupt Aggregator

maintainers:
  - Lokesh Vutla <lokeshvutla@ti.com>

allOf:
  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#

description: |
  The Interrupt Aggregator (INTA) provides a centralized machine
  which handles the termination of system events to that they can
  be coherently processed by the host(s) in the system. A maximum
  of 64 events can be mapped to a single interrupt.

                                Interrupt Aggregator
                       +-----------------------------------------+
                       |      Intmap            VINT             |
                       | +--------------+  +------------+        |
              m ------>| | vint  | bit  |  | 0 |.....|63| vint0  |
                 .     | +--------------+  +------------+        |      +------+
                 .     |         .               .               |      | HOST |
  Globalevents  ------>|         .               .               |----->| IRQ  |
                 .     |         .               .               |      | CTRL |
                 .     |         .               .               |      +------+
              n ------>| +--------------+  +------------+        |
                       | | vint  | bit  |  | 0 |.....|63| vintx  |
                       | +--------------+  +------------+        |
                       |                                         |
                       |      Unmap                              |
                       | +--------------+                        |
  Unmapped events ---->| |   umapidx    |-------------------------> Globalevents
                       | +--------------+                        |
                       |                                         |
                       +-----------------------------------------+

  Configuration of these Intmap registers that maps global events to vint is
  done by a system controller (like the Device Memory and Security Controller
  on AM654 SoC). Driver should request the system controller to get the range
  of global events and vints assigned to the requesting host. Management
  of these requested resources should be handled by driver and requests
  system controller to map specific global event to vint, bit pair.

  Communication between the host processor running an OS and the system
  controller happens through a protocol called TI System Control Interface
  (TISCI protocol).

properties:
  compatible:
    const: ti,sci-inta

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 0

  msi-controller: true

  ti,interrupt-ranges:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    description: |
      Interrupt ranges that converts the INTA output hw irq numbers
      to parents's input interrupt numbers.
    items:
      items:
        - description: |
            "output_irq" specifies the base for inta output irq
        - description: |
            "parent's input irq" specifies the base for parent irq
        - description: |
            "limit" specifies the limit for translation

  ti,unmapped-event-sources:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      maxItems: 1
    description:
      Array of phandles to DMA controllers where the unmapped events originate.

required:
  - compatible
  - reg
  - interrupt-controller
  - msi-controller
  - ti,sci
  - ti,sci-dev-id
  - ti,interrupt-ranges

unevaluatedProperties: false

examples:
  - |
    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        main_udmass_inta: msi-controller@33d00000 {
            compatible = "ti,sci-inta";
            reg = <0x0 0x33d00000 0x0 0x100000>;
            interrupt-controller;
            msi-controller;
            interrupt-parent = <&main_navss_intr>;
            ti,sci = <&dmsc>;
            ti,sci-dev-id = <179>;
            ti,interrupt-ranges = <0 0 256>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments K3 Interrupt Router

maintainers:
  - Lokesh Vutla <lokeshvutla@ti.com>

allOf:
  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#

description: |
  The Interrupt Router (INTR) module provides a mechanism to mux M
  interrupt inputs to N interrupt outputs, where all M inputs are selectable
  to be driven per N output. An Interrupt Router can either handle edge
  triggered or level triggered interrupts and that is fixed in hardware.

                                   Interrupt Router
                               +----------------------+
                               |  Inputs     Outputs  |
          +-------+            | +------+    +-----+  |
          | GPIO  |----------->| | irq0 |    |  0  |  |       Host IRQ
          +-------+            | +------+    +-----+  |      controller
                               |    .           .     |      +-------+
          +-------+            |    .           .     |----->|  IRQ  |
          | INTA  |----------->|    .           .     |      +-------+
          +-------+            |    .        +-----+  |
                               | +------+    |  N  |  |
                               | | irqM |    +-----+  |
                               | +------+             |
                               |                      |
                               +----------------------+

  There is one register per output (MUXCNTL_N) that controls the selection.
  Configuration of these MUXCNTL_N registers is done by a system controller
  (like the Device Memory and Security Controller on K3 AM654 SoC). System
  controller will keep track of the used and unused registers within the Router.
  Driver should request the system controller to get the range of GIC IRQs
  assigned to the requesting hosts. It is the drivers responsibility to keep
  track of Host IRQs.

  Communication between the host processor running an OS and the system
  controller happens through a protocol called TI System Control Interface
  (TISCI protocol).

properties:
  compatible:
    const: ti,sci-intr

  ti,intr-trigger-type:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 4]
    description: |
      Should be one of the following.
        1 = If intr supports edge triggered interrupts.
        4 = If intr supports level triggered interrupts.

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 1
    description: |
      The 1st cell should contain interrupt router input hw number.

  ti,interrupt-ranges:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    description: |
      Interrupt ranges that converts the INTR output hw irq numbers
      to parents's input interrupt numbers.
    items:
      items:
        - description: |
            "output_irq" specifies the base for intr output irq
        - description: |
            "parent's input irq" specifies the base for parent irq
        - description: |
            "limit" specifies the limit for translation

required:
  - compatible
  - ti,intr-trigger-type
  - interrupt-controller
  - '#interrupt-cells'
  - ti,sci
  - ti,sci-dev-id
  - ti,interrupt-ranges

unevaluatedProperties: false

examples:
  - |
    main_gpio_intr: interrupt-controller0 {
        compatible = "ti,sci-intr";
        ti,intr-trigger-type = <1>;
        interrupt-controller;
        interrupt-parent = <&gic500>;
        #interrupt-cells = <1>;
        ti,sci = <&dmsc>;
        ti,sci-dev-id = <131>;
        ti,interrupt-ranges = <0 360 32>;
    };


code:
VIA/Wondermedia VT8500 Interrupt Controller
-----------------------------------------------------

Required properties:
- compatible : "via,vt8500-intc"
- reg : Should contain 1 register ranges(address and length)
- #interrupt-cells : should be <1>

Example:

	intc: interrupt-controller@d8140000 {
		compatible = "via,vt8500-intc";
		interrupt-controller;
		reg = <0xd8140000 0x10000>;
		#interrupt-cells = <1>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/allwinner,sun50i-h6-iommu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner H6 IOMMU

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#iommu-cells":
    const: 1
    description:
      The content of the cell is the master ID.

  compatible:
    const: allwinner,sun50i-h6-iommu

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - "#iommu-cells"
  - compatible
  - reg
  - interrupts
  - clocks
  - resets

additionalProperties: false

examples:
  - |
      #include <dt-bindings/interrupt-controller/arm-gic.h>
      #include <dt-bindings/interrupt-controller/irq.h>

      #include <dt-bindings/clock/sun50i-h6-ccu.h>
      #include <dt-bindings/reset/sun50i-h6-ccu.h>

      iommu: iommu@30f0000 {
          compatible = "allwinner,sun50i-h6-iommu";
          reg = <0x030f0000 0x10000>;
          interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
          clocks = <&ccu CLK_BUS_IOMMU>;
          resets = <&ccu RST_BUS_IOMMU>;
          #iommu-cells = <1>;
      };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/apple,dart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple DART IOMMU

maintainers:
  - Sven Peter <sven@svenpeter.dev>

description: |+
  Apple SoCs may contain an implementation of their Device Address
  Resolution Table which provides a mandatory layer of address
  translations for various masters.

  Each DART instance is capable of handling up to 16 different streams
  with individual pagetables and page-level read/write protection flags.

  This DART IOMMU also raises interrupts in response to various
  fault conditions.

properties:
  compatible:
    enum:
      - apple,t8103-dart
      - apple,t6000-dart

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    description:
      Reference to the gate clock phandle if required for this IOMMU.
      Optional since not all IOMMUs are attached to a clock gate.

  '#iommu-cells':
    const: 1
    description:
      Has to be one. The single cell describes the stream id emitted by
      a master to the IOMMU.

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - '#iommu-cells'
  - interrupts

additionalProperties: false

examples:
  - |+
    dart1: iommu@82f80000 {
      compatible = "apple,t8103-dart";
      reg = <0x82f80000 0x4000>;
      interrupts = <1 781 4>;
      #iommu-cells = <1>;
    };

    master1 {
      iommus = <&dart1 0>;
    };

  - |+
    dart2a: iommu@82f00000 {
      compatible = "apple,t8103-dart";
      reg = <0x82f00000 0x4000>;
      interrupts = <1 781 4>;
      #iommu-cells = <1>;
    };
    dart2b: iommu@82f80000 {
      compatible = "apple,t8103-dart";
      reg = <0x82f80000 0x4000>;
      interrupts = <1 781 4>;
      #iommu-cells = <1>;
    };

    master2 {
      iommus = <&dart2a 0>, <&dart2b 1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/apple,sart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple SART DMA address filter

maintainers:
  - Sven Peter <sven@svenpeter.dev>

description:
  Apple SART is a simple address filter for DMA transactions. Regions of
  physical memory must be added to the SART's allow list before any
  DMA can target these. Unlike a proper IOMMU no remapping can be done and
  special support in the consumer driver is required since not all DMA
  transactions of a single device are subject to SART filtering.

  SART1 has first been used since at least the A11 (iPhone 8 and iPhone X)
  and allows 36 bit of physical address space and filter entries with sizes
  up to 24 bit.

  SART2, first seen in A14 and M1, allows 36 bit of physical address space
  and filter entry size up to 36 bit.

  SART3, first seen in M1 Pro/Max, extends both the address space and filter
  entry size to 42 bit.

properties:
  compatible:
    enum:
      - apple,t6000-sart
      - apple,t8103-sart

  reg:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    iommu@7bc50000 {
      compatible = "apple,t8103-sart";
      reg = <0x7bc50000 0x4000>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM SMMUv3 Architecture Implementation

maintainers:
  - Will Deacon <will@kernel.org>
  - Robin Murphy <Robin.Murphy@arm.com>

description: |+
  The SMMUv3 architecture is a significant departure from previous
  revisions, replacing the MMIO register interface with in-memory command
  and event queues and adding support for the ATS and PRI components of
  the PCIe specification.

properties:
  $nodename:
    pattern: "^iommu@[0-9a-f]*"
  compatible:
    const: arm,smmu-v3

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 4

  interrupt-names:
    oneOf:
      - const: combined
        description:
          The combined interrupt is optional, and should only be provided if the
          hardware supports just a single, combined interrupt line.
          If provided, then the combined interrupt will be used in preference to
          any others.
      - minItems: 1
        items:
          enum:
            - eventq      # Event Queue not empty
            - gerror      # Global Error activated
            - cmdq-sync   # CMD_SYNC complete
            - priq        # PRI Queue not empty

  '#iommu-cells':
    const: 1

  dma-coherent:
    description: |
      Present if page table walks made by the SMMU are cache coherent with the
      CPU.

      NOTE: this only applies to the SMMU itself, not masters connected
      upstream of the SMMU.

  msi-parent: true

  hisilicon,broken-prefetch-cmd:
    type: boolean
    description: Avoid sending CMD_PREFETCH_* commands to the SMMU.

  cavium,cn9900-broken-page1-regspace:
    type: boolean
    description:
      Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS
      register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
      doesn't support SMMU page1 register space.

required:
  - compatible
  - reg
  - '#iommu-cells'

additionalProperties: false

examples:
  - |+
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    iommu@2b400000 {
            compatible = "arm,smmu-v3";
            reg = <0x2b400000 0x20000>;
            interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
            interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
            dma-coherent;
            #iommu-cells = <1>;
            msi-parent = <&its 0xff0000>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM System MMU Architecture Implementation

maintainers:
  - Will Deacon <will@kernel.org>
  - Robin Murphy <Robin.Murphy@arm.com>

description: |+
  ARM SoCs may contain an implementation of the ARM System Memory
  Management Unit Architecture, which can be used to provide 1 or 2 stages
  of address translation to bus masters external to the CPU.

  The SMMU may also raise interrupts in response to various fault
  conditions.

properties:
  $nodename:
    pattern: "^iommu@[0-9a-f]*"
  compatible:
    oneOf:
      - description: Qcom SoCs implementing "arm,smmu-v2"
        items:
          - enum:
              - qcom,msm8996-smmu-v2
              - qcom,msm8998-smmu-v2
          - const: qcom,smmu-v2

      - description: Qcom SoCs implementing "arm,mmu-500"
        items:
          - enum:
              - qcom,qcm2290-smmu-500
              - qcom,sc7180-smmu-500
              - qcom,sc7280-smmu-500
              - qcom,sc8180x-smmu-500
              - qcom,sc8280xp-smmu-500
              - qcom,sdm845-smmu-500
              - qcom,sdx55-smmu-500
              - qcom,sdx65-smmu-500
              - qcom,sm6350-smmu-500
              - qcom,sm6375-smmu-500
              - qcom,sm8150-smmu-500
              - qcom,sm8250-smmu-500
              - qcom,sm8350-smmu-500
              - qcom,sm8450-smmu-500
          - const: arm,mmu-500
      - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
        items:
          - enum:
              - qcom,sc7180-smmu-v2
              - qcom,sdm845-smmu-v2
          - const: qcom,adreno-smmu
          - const: qcom,smmu-v2
      - description: Marvell SoCs implementing "arm,mmu-500"
        items:
          - const: marvell,ap806-smmu-500
          - const: arm,mmu-500
      - description: NVIDIA SoCs that require memory controller interaction
          and may program multiple ARM MMU-500s identically with the memory
          controller interleaving translations between multiple instances
          for improved performance.
        items:
          - enum:
              - nvidia,tegra186-smmu
              - nvidia,tegra194-smmu
              - nvidia,tegra234-smmu
          - const: nvidia,smmu-500
      - items:
          - const: arm,mmu-500
          - const: arm,smmu-v2
      - items:
          - enum:
              - arm,mmu-400
              - arm,mmu-401
          - const: arm,smmu-v1
      - enum:
          - arm,smmu-v1
          - arm,smmu-v2
          - arm,mmu-400
          - arm,mmu-401
          - arm,mmu-500
          - cavium,smmu-v2

  reg:
    minItems: 1
    maxItems: 2

  '#global-interrupts':
    description: The number of global interrupts exposed by the device.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 260   # 2 secure, 2 non-secure, and up to 256 perf counters

  '#iommu-cells':
    enum: [ 1, 2 ]
    description: |
      See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
      value of 1, each IOMMU specifier represents a distinct stream ID emitted
      by that device into the relevant SMMU.

      SMMUs with stream matching support and complex masters may use a value of
      2, where the second cell of the IOMMU specifier represents an SMR mask to
      combine with the ID in the first cell.  Care must be taken to ensure the
      set of matched IDs does not result in conflicts.

  interrupts:
    minItems: 1
    maxItems: 388   # 260 plus 128 contexts
    description: |
      Interrupt list, with the first #global-interrupts entries corresponding to
      the global interrupts and any following entries corresponding to context
      interrupts, specified in order of their indexing by the SMMU.

      For SMMUv2 implementations, there must be exactly one interrupt per
      context bank. In the case of a single, combined interrupt, it must be
      listed multiple times.

  dma-coherent:
    description: |
      Present if page table walks made by the SMMU are cache coherent with the
      CPU.

      NOTE: this only applies to the SMMU itself, not masters connected
      upstream of the SMMU.

  calxeda,smmu-secure-config-access:
    type: boolean
    description:
      Enable proper handling of buggy implementations that always use secure
      access to SMMU configuration registers. In this case non-secure aliases of
      secure registers have to be used during SMMU configuration.

  stream-match-mask:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      For SMMUs supporting stream matching and using #iommu-cells = <1>,
      specifies a mask of bits to ignore when matching stream IDs (e.g. this may
      be programmed into the SMRn.MASK field of every stream match register
      used). For cases where it is desirable to ignore some portion of every
      Stream ID (e.g. for certain MMU-500 configurations given globally unique
      input IDs). This property is not valid for SMMUs using stream indexing, or
      using stream matching with #iommu-cells = <2>, and may be ignored if
      present in such cases.

  clock-names:
    items:
      - const: bus
      - const: iface

  clocks:
    items:
      - description: bus clock required for downstream bus access and for the
          smmu ptw
      - description: interface clock required to access smmu's registers
          through the TCU's programming interface.

  power-domains:
    maxItems: 1

  nvidia,memory-controller:
    description: |
      A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
      The memory controller needs to be programmed with a mapping of memory
      client IDs to ARM SMMU stream IDs.

      If this property is absent, the mapping programmed by early firmware
      will be used and it is not guaranteed that IOMMU translations will be
      enabled for any given device.
    $ref: /schemas/types.yaml#/definitions/phandle

required:
  - compatible
  - reg
  - '#global-interrupts'
  - '#iommu-cells'
  - interrupts

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra186-smmu
              - nvidia,tegra194-smmu
              - nvidia,tegra234-smmu
    then:
      properties:
        reg:
          minItems: 1
          maxItems: 2

      # The reference to the memory controller is required to ensure that the
      # memory client to stream ID mapping can be done synchronously with the
      # IOMMU attachment.
      required:
        - nvidia,memory-controller
    else:
      properties:
        reg:
          maxItems: 1

examples:
  - |+
    /* SMMU with stream matching or stream indexing */
    smmu1: iommu@ba5e0000 {
            compatible = "arm,smmu-v1";
            reg = <0xba5e0000 0x10000>;
            #global-interrupts = <2>;
            interrupts = <0 32 4>,
                         <0 33 4>,
                         <0 34 4>, /* This is the first context interrupt */
                         <0 35 4>,
                         <0 36 4>,
                         <0 37 4>;
            #iommu-cells = <1>;
    };

    /* device with two stream IDs, 0 and 7 */
    master1 {
            iommus = <&smmu1 0>,
                     <&smmu1 7>;
    };

    /* SMMU with stream matching */
    smmu2: iommu@ba5f0000 {
            compatible = "arm,smmu-v1";
            reg = <0xba5f0000 0x10000>;
            #global-interrupts = <2>;
            interrupts = <0 38 4>,
                         <0 39 4>,
                         <0 40 4>, /* This is the first context interrupt */
                         <0 41 4>,
                         <0 42 4>,
                         <0 43 4>;
            #iommu-cells = <2>;
    };

    /* device with stream IDs 0 and 7 */
    master2 {
            iommus = <&smmu2 0 0>,
                     <&smmu2 7 0>;
    };

    /* device with stream IDs 1, 17, 33 and 49 */
    master3 {
            iommus = <&smmu2 1 0x30>;
    };

    /* ARM MMU-500 with 10-bit stream ID input configuration */
    smmu3: iommu@ba600000 {
            compatible = "arm,mmu-500", "arm,smmu-v2";
            reg = <0xba600000 0x10000>;
            #global-interrupts = <2>;
            interrupts = <0 44 4>,
                         <0 45 4>,
                         <0 46 4>, /* This is the first context interrupt */
                         <0 47 4>,
                         <0 48 4>,
                         <0 49 4>;
            #iommu-cells = <1>;
            /* always ignore appended 5-bit TBU number */
            stream-match-mask = <0x7c00>;
    };

    bus {
            /* bus whose child devices emit one unique 10-bit stream
               ID each, but may master through multiple SMMU TBUs */
            iommu-map = <0 &smmu3 0 0x400>;

    };

  - |+
    /* Qcom's arm,smmu-v2 implementation */
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    smmu4: iommu@d00000 {
      compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
      reg = <0xd00000 0x10000>;

      #global-interrupts = <1>;
      interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
      #iommu-cells = <1>;
      power-domains = <&mmcc 0>;

      clocks = <&mmcc 123>,
        <&mmcc 124>;
      clock-names = "bus", "iface";
    };


code:
This document describes the generic device tree binding for IOMMUs and their
master(s).

IOMMU device node:
==================

An IOMMU can provide the following services:

* Remap address space to allow devices to access physical memory ranges that
  they otherwise wouldn't be capable of accessing.

  Example: 32-bit DMA to 64-bit physical addresses

* Implement scatter-gather at page level granularity so that the device does
  not have to.

* Provide system protection against "rogue" DMA by forcing all accesses to go
  through the IOMMU and faulting when encountering accesses to unmapped
  address regions.

* Provide address space isolation between multiple contexts.

  Example: Virtualization

Device nodes compatible with this binding represent hardware with some of the
above capabilities.

IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
typically have a fixed association to the master device, whereas multiple-
master IOMMU devices can translate accesses from more than one master.

The device tree node of the IOMMU device's parent bus must contain a valid
"dma-ranges" property that describes how the physical address space of the
IOMMU maps to memory. An empty "dma-ranges" property means that there is a
1:1 mapping from IOMMU to memory.

Required properties:
--------------------
- #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
  address.

The meaning of the IOMMU specifier is defined by the device tree binding of
the specific IOMMU. Below are a few examples of typical use-cases:

- #iommu-cells = <0>: Single master IOMMU devices are not configurable and
  therefore no additional information needs to be encoded in the specifier.
  This may also apply to multiple master IOMMU devices that do not allow the
  association of masters to be configured. Note that an IOMMU can by design
  be multi-master yet only expose a single master in a given configuration.
  In such cases the number of cells will usually be 1 as in the next case.
- #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
  in order to enable translation for a given master. In such cases the single
  address cell corresponds to the master device's ID. In some cases more than
  one cell can be required to represent a single master ID.
- #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
  be configured. The first cell of the address in this may contain the master
  device's ID for example, while the second cell could contain the start of
  the DMA window for the given device. The length of the DMA window is given
  by the third and fourth cells.

Note that these are merely examples and real-world use-cases may use different
definitions to represent their individual needs. Always refer to the specific
IOMMU binding for the exact meaning of the cells that make up the specifier.

IOMMU master node:
==================

Devices that access memory through an IOMMU are called masters. A device can
have multiple master interfaces (to one or more IOMMU devices).

Required properties:
--------------------
- iommus: A list of phandle and IOMMU specifier pairs that describe the IOMMU
  master interfaces of the device. One entry in the list describes one master
  interface of the device.

When an "iommus" property is specified in a device tree node, the IOMMU will
be used for address translation. If a "dma-ranges" property exists in the
device's parent node it will be ignored. An exception to this rule is if the
referenced IOMMU is disabled, in which case the "dma-ranges" property of the
parent shall take effect. Note that merely disabling a device tree node does
not guarantee that the IOMMU is really disabled since the hardware may not
have a means to turn off translation. But it is invalid in such cases to
disable the IOMMU's device tree node in the first place because it would
prevent any driver from properly setting up the translations.

Optional properties:
--------------------
- pasid-num-bits: Some masters support multiple address spaces for DMA, by
  tagging DMA transactions with an address space identifier. By default,
  this is 0, which means that the device only has one address space.

- dma-can-stall: When present, the master can wait for a transaction to
  complete for an indefinite amount of time. Upon translation fault some
  IOMMUs, instead of aborting the translation immediately, may first
  notify the driver and keep the transaction in flight. This allows the OS
  to inspect the fault and, for example, make physical pages resident
  before updating the mappings and completing the transaction. Such IOMMU
  accepts a limited number of simultaneous stalled transactions before
  having to either put back-pressure on the master, or abort new faulting
  transactions.

  Firmware has to opt-in stalling, because most buses and masters don't
  support it. In particular it isn't compatible with PCI, where
  transactions have to complete before a time limit. More generally it
  won't work in systems and masters that haven't been designed for
  stalling. For example the OS, in order to handle a stalled transaction,
  may attempt to retrieve pages from secondary storage in a stalled
  domain, leading to a deadlock.

Notes:
======

One possible extension to the above is to use an "iommus" property along with
a "dma-ranges" property in a bus device node (such as PCI host bridges). This
can be useful to describe how children on the bus relate to the IOMMU if they
are not explicitly listed in the device tree (e.g. PCI devices). However, the
requirements of that use-case haven't been fully determined yet. Implementing
this is therefore not recommended without further discussion and extension of
this binding.

Examples:
=========

Single-master IOMMU:
--------------------

	iommu {
		#iommu-cells = <0>;
	};

	master {
		iommus = <&{/iommu}>;
	};

Multiple-master IOMMU with fixed associations:
----------------------------------------------

	/* multiple-master IOMMU */
	iommu {
		/*
		 * Masters are statically associated with this IOMMU and share
		 * the same address translations because the IOMMU does not
		 * have sufficient information to distinguish between masters.
		 *
		 * Consequently address translation is always on or off for
		 * all masters at any given point in time.
		 */
		#iommu-cells = <0>;
	};

	/* static association with IOMMU */
	master@1 {
		reg = <1>;
		iommus = <&{/iommu}>;
	};

	/* static association with IOMMU */
	master@2 {
		reg = <2>;
		iommus = <&{/iommu}>;
	};

Multiple-master IOMMU:
----------------------

	iommu {
		/* the specifier represents the ID of the master */
		#iommu-cells = <1>;
	};

	master@1 {
		/* device has master ID 42 in the IOMMU */
		iommus = <&{/iommu} 42>;
	};

	master@2 {
		/* device has master IDs 23 and 24 in the IOMMU */
		iommus = <&{/iommu} 23>, <&{/iommu} 24>;
	};

Multiple-master IOMMU with configurable DMA window:
---------------------------------------------------

	/ {
		iommu {
			/*
			 * One cell for the master ID and one cell for the
			 * address of the DMA window. The length of the DMA
			 * window is encoded in two cells.
			 *
			 * The DMA window is the range addressable by the
			 * master (i.e. the I/O virtual address space).
			 */
			#iommu-cells = <4>;
		};

		master {
			/* master ID 42, 4 GiB DMA window starting at 0 */
			iommus = <&{/iommu}  42  0  0x1 0x0>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek IOMMU Architecture Implementation

maintainers:
  - Yong Wu <yong.wu@mediatek.com>

description: |+
  Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
  this M4U have two generations of HW architecture. Generation one uses flat
  pagetable, and only supports 4K size page mapping. Generation two uses the
  ARM Short-Descriptor translation table format for address translation.

  About the M4U Hardware Block Diagram, please check below:

                EMI (External Memory Interface)
                 |
                m4u (Multimedia Memory Management Unit)
                 |
            +--------+
            |        |
        gals0-rx   gals1-rx    (Global Async Local Sync rx)
            |        |
            |        |
        gals0-tx   gals1-tx    (Global Async Local Sync tx)
            |        |          Some SoCs may have GALS.
            +--------+
                 |
             SMI Common(Smart Multimedia Interface Common)
                 |
         +----------------+-------
         |                |
         |             gals-rx        There may be GALS in some larbs.
         |                |
         |                |
         |             gals-tx
         |                |
     SMI larb0        SMI larb1   ... SoCs have several SMI local arbiter(larb).
     (display)         (vdec)
         |                |
         |                |
   +-----+-----+     +----+----+
   |     |     |     |    |    |
   |     |     |...  |    |    |  ... There are different ports in each larb.
   |     |     |     |    |    |
  OVL0 RDMA0 WDMA0  MC   PP   VLD

  As above, The Multimedia HW will go through SMI and M4U while it
  access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
  smi local arbiter and smi common. It will control whether the Multimedia
  HW should go though the m4u for translation or bypass it and talk
  directly with EMI. And also SMI help control the power domain and clocks for
  each local arbiter.

  Normally we specify a local arbiter(larb) for each multimedia HW
  like display, video decode, and camera. And there are different ports
  in each larb. Take a example, There are many ports like MC, PP, VLD in the
  video decode local arbiter, all these ports are according to the video HW.

  In some SoCs, there may be a GALS(Global Async Local Sync) module between
  smi-common and m4u, and additional GALS module between smi-larb and
  smi-common. GALS can been seen as a "asynchronous fifo" which could help
  synchronize for the modules in different clock frequency.

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt2701-m4u  # generation one
          - mediatek,mt2712-m4u  # generation two
          - mediatek,mt6779-m4u  # generation two
          - mediatek,mt6795-m4u  # generation two
          - mediatek,mt8167-m4u  # generation two
          - mediatek,mt8173-m4u  # generation two
          - mediatek,mt8183-m4u  # generation two
          - mediatek,mt8186-iommu-mm         # generation two
          - mediatek,mt8192-m4u  # generation two
          - mediatek,mt8195-iommu-vdo        # generation two
          - mediatek,mt8195-iommu-vpp        # generation two
          - mediatek,mt8195-iommu-infra      # generation two

      - description: mt7623 generation one
        items:
          - const: mediatek,mt7623-m4u
          - const: mediatek,mt2701-m4u

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: bclk is the block clock.

  clock-names:
    items:
      - const: bclk

  mediatek,infracfg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: The phandle to the mediatek infracfg syscon

  mediatek,larbs:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 1
    maxItems: 32
    items:
      maxItems: 1
    description: |
      List of phandle to the local arbiters in the current Socs.
      Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
      according to the local arbiter index, like larb0, larb1, larb2...

  '#iommu-cells':
    const: 1
    description: |
      This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
      defined in
      dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
      dt-binding/memory/mt2712-larb-port.h for mt2712,
      dt-binding/memory/mt6779-larb-port.h for mt6779,
      dt-binding/memory/mt6795-larb-port.h for mt6795,
      dt-binding/memory/mt8167-larb-port.h for mt8167,
      dt-binding/memory/mt8173-larb-port.h for mt8173,
      dt-binding/memory/mt8183-larb-port.h for mt8183,
      dt-binding/memory/mt8186-memory-port.h for mt8186,
      dt-binding/memory/mt8192-larb-port.h for mt8192.
      dt-binding/memory/mt8195-memory-port.h for mt8195.

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - '#iommu-cells'

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt2701-m4u
              - mediatek,mt2712-m4u
              - mediatek,mt6795-m4u
              - mediatek,mt8173-m4u
              - mediatek,mt8186-iommu-mm
              - mediatek,mt8192-m4u
              - mediatek,mt8195-iommu-vdo
              - mediatek,mt8195-iommu-vpp

    then:
      required:
        - clocks

  - if:
      properties:
        compatible:
          enum:
            - mediatek,mt8186-iommu-mm
            - mediatek,mt8192-m4u
            - mediatek,mt8195-iommu-vdo
            - mediatek,mt8195-iommu-vpp

    then:
      required:
        - power-domains

  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt2712-m4u
              - mediatek,mt6795-m4u
              - mediatek,mt8173-m4u

    then:
      required:
        - mediatek,infracfg

  - if: # The IOMMUs don't have larbs.
      not:
        properties:
          compatible:
            contains:
              const: mediatek,mt8195-iommu-infra

    then:
      required:
        - mediatek,larbs

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    iommu: iommu@10205000 {
            compatible = "mediatek,mt8173-m4u";
            reg = <0x10205000 0x1000>;
            interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
            clocks = <&infracfg CLK_INFRA_M4U>;
            clock-names = "bclk";
            mediatek,infracfg = <&infracfg>;
            mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
                             <&larb3>, <&larb4>, <&larb5>;
            #iommu-cells = <1>;
    };


code:
* QCOM IOMMU

The MSM IOMMU is an implementation compatible with the ARM VMSA short
descriptor page tables. It provides address translation for bus masters outside
of the CPU, each connected to the IOMMU through a port called micro-TLB.

Required Properties:

  - compatible: Must contain "qcom,apq8064-iommu".
  - reg: Base address and size of the IOMMU registers.
  - interrupts: Specifiers for the MMU fault interrupts. For instances that
    support secure mode two interrupts must be specified, for non-secure and
    secure mode, in that order. For instances that don't support secure mode a
    single interrupt must be specified.
  - #iommu-cells: The number of cells needed to specify the stream id. This
		  is always 1.
  - qcom,ncb:	  The total number of context banks in the IOMMU.
  - clocks	: List of clocks to be used during SMMU register access. See
		  Documentation/devicetree/bindings/clock/clock-bindings.txt
		  for information about the format. For each clock specified
		  here, there must be a corresponding entry in clock-names
		  (see below).

  - clock-names	: List of clock names corresponding to the clocks specified in
		  the "clocks" property (above).
		  Should be "smmu_pclk" for specifying the interface clock
		  required for iommu's register accesses.
		  Should be "smmu_clk" for specifying the functional clock
		  required by iommu for bus accesses.

Each bus master connected to an IOMMU must reference the IOMMU in its device
node with the following property:

  - iommus: A reference to the IOMMU in multiple cells. The first cell is a
	    phandle to the IOMMU and the second cell is the stream id.
	    A single master device can be connected to more than one iommu
	    and multiple contexts in each of the iommu. So multiple entries
	    are required to list all the iommus and the stream ids that the
	    master is connected to.

Example: mdp iommu and its bus master

                mdp_port0: iommu@7500000 {
			compatible = "qcom,apq8064-iommu";
			#iommu-cells = <1>;
			clock-names =
			    "smmu_pclk",
			    "smmu_clk";
			clocks =
			    <&mmcc SMMU_AHB_CLK>,
			    <&mmcc MDP_AXI_CLK>;
			reg = <0x07500000 0x100000>;
			interrupts =
			    <GIC_SPI 63 0>,
			    <GIC_SPI 64 0>;
			qcom,ncb = <2>;
		};

		mdp: qcom,mdp@5100000 {
			compatible = "qcom,mdp";
			...
			iommus = <&mdp_port0 0
				  &mdp_port0 2>;
		};


code:
NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit)

Required properties:
- compatible : "nvidia,tegra30-smmu"
- reg : Should contain 3 register banks(address and length) for each
  of the SMMU register blocks.
- interrupts : Should contain MC General interrupt.
- nvidia,#asids : # of ASIDs
- dma-window : IOVA start address and length.
- nvidia,ahb : phandle to the ahb bus connected to SMMU.

Example:
	smmu {
		compatible = "nvidia,tegra30-smmu";
		reg = <0x7000f010 0x02c
		       0x7000f1f0 0x010
		       0x7000f228 0x05c>;
		nvidia,#asids = <4>;		/* # of ASIDs */
		dma-window = <0 0x40000000>;	/* IOVA start & length */
		nvidia,ahb = <&ahb>;
	};


code:
* QCOM IOMMU v1 Implementation

Qualcomm "B" family devices which are not compatible with arm-smmu have
a similar looking IOMMU but without access to the global register space,
and optionally requiring additional configuration to route context irqs
to non-secure vs secure interrupt line.

** Required properties:

- compatible       : Should be one of:

                        "qcom,msm8916-iommu"

                     Followed by "qcom,msm-iommu-v1".

- clock-names      : Should be a pair of "iface" (required for IOMMUs
                     register group access) and "bus" (required for
                     the IOMMUs underlying bus access).

- clocks           : Phandles for respective clocks described by
                     clock-names.

- #address-cells   : must be 1.

- #size-cells      : must be 1.

- #iommu-cells     : Must be 1.  Index identifies the context-bank #.

- ranges           : Base address and size of the iommu context banks.

- qcom,iommu-secure-id  : secure-id.

- List of sub-nodes, one per translation context bank.  Each sub-node
  has the following required properties:

  - compatible     : Should be one of:
        - "qcom,msm-iommu-v1-ns"  : non-secure context bank
        - "qcom,msm-iommu-v1-sec" : secure context bank
  - reg            : Base address and size of context bank within the iommu
  - interrupts     : The context fault irq.

** Optional properties:

- reg              : Base address and size of the SMMU local base, should
                     be only specified if the iommu requires configuration
                     for routing of context bank irq's to secure vs non-
                     secure lines.  (Ie. if the iommu contains secure
                     context banks)

** Examples:

	apps_iommu: iommu@1e20000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#iommu-cells = <1>;
		compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
		ranges = <0 0x1e20000 0x40000>;
		reg = <0x1ef0000 0x3000>;
		clocks = <&gcc GCC_SMMU_CFG_CLK>,
			 <&gcc GCC_APSS_TCU_CLK>;
		clock-names = "iface", "bus";
		qcom,iommu-secure-id = <17>;

		// mdp_0:
		iommu-ctx@4000 {
			compatible = "qcom,msm-iommu-v1-ns";
			reg = <0x4000 0x1000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
		};

		// venus_ns:
		iommu-ctx@5000 {
			compatible = "qcom,msm-iommu-v1-sec";
			reg = <0x5000 0x1000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	gpu_iommu: iommu@1f08000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#iommu-cells = <1>;
		compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
		ranges = <0 0x1f08000 0x10000>;
		clocks = <&gcc GCC_SMMU_CFG_CLK>,
			 <&gcc GCC_GFX_TCU_CLK>;
		clock-names = "iface", "bus";
		qcom,iommu-secure-id = <18>;

		// gfx3d_user:
		iommu-ctx@1000 {
			compatible = "qcom,msm-iommu-v1-ns";
			reg = <0x1000 0x1000>;
			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
		};

		// gfx3d_priv:
		iommu-ctx@2000 {
			compatible = "qcom,msm-iommu-v1-ns";
			reg = <0x2000 0x1000>;
			interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	...

	venus: video-codec@1d00000 {
		...
		iommus = <&apps_iommu 5>;
	};

	mdp: mdp@1a01000 {
		...
		iommus = <&apps_iommu 4>;
	};

	gpu@1c00000 {
		...
		iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas VMSA-Compatible IOMMU

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

description:
  The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
  It provides address translation for bus masters outside of the CPU, each
  connected to the IPMMU through a port called micro-TLB.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,ipmmu-r8a73a4  # R-Mobile APE6
              - renesas,ipmmu-r8a7742  # RZ/G1H
              - renesas,ipmmu-r8a7743  # RZ/G1M
              - renesas,ipmmu-r8a7744  # RZ/G1N
              - renesas,ipmmu-r8a7745  # RZ/G1E
              - renesas,ipmmu-r8a7790  # R-Car H2
              - renesas,ipmmu-r8a7791  # R-Car M2-W
              - renesas,ipmmu-r8a7793  # R-Car M2-N
              - renesas,ipmmu-r8a7794  # R-Car E2
          - const: renesas,ipmmu-vmsa  # R-Mobile APE6 or R-Car Gen2 or RZ/G1

      - items:
          - enum:
              - renesas,ipmmu-r8a774a1 # RZ/G2M
              - renesas,ipmmu-r8a774b1 # RZ/G2N
              - renesas,ipmmu-r8a774c0 # RZ/G2E
              - renesas,ipmmu-r8a774e1 # RZ/G2H
              - renesas,ipmmu-r8a7795  # R-Car H3
              - renesas,ipmmu-r8a7796  # R-Car M3-W
              - renesas,ipmmu-r8a77961 # R-Car M3-W+
              - renesas,ipmmu-r8a77965 # R-Car M3-N
              - renesas,ipmmu-r8a77970 # R-Car V3M
              - renesas,ipmmu-r8a77980 # R-Car V3H
              - renesas,ipmmu-r8a77990 # R-Car E3
              - renesas,ipmmu-r8a77995 # R-Car D3

      - items:
          - enum:
              - renesas,ipmmu-r8a779a0           # R-Car V3U
              - renesas,ipmmu-r8a779f0           # R-Car S4-8
          - const: renesas,rcar-gen4-ipmmu-vmsa  # R-Car Gen4

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    description:
      Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
    items:
      - description: non-secure mode
      - description: secure mode if supported

  '#iommu-cells':
    const: 1
    description:
      The number of the micro-TLB that the device is connected to.

  power-domains:
    maxItems: 1

  renesas,ipmmu-main:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to main IPMMU
          - description: the interrupt bit number associated with the particular
              cache IPMMU device. The interrupt bit number needs to match the main
              IPMMU IMSSTR register. Only used by cache IPMMU instances.
    description:
      Reference to the main IPMMU phandle plus 1 cell. The cell is
      the interrupt bit number associated with the particular cache IPMMU
      device. The interrupt bit number needs to match the main IPMMU IMSSTR
      register. Only used by cache IPMMU instances.

required:
  - compatible
  - reg
  - '#iommu-cells'

oneOf:
  - required:
      - interrupts
  - required:
      - renesas,ipmmu-main

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          not:
            contains:
              const: renesas,ipmmu-vmsa
    then:
      required:
        - power-domains

examples:
  - |
    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7791-sysc.h>

    ipmmu_mx: iommu@fe951000 {
        compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
        reg = <0xfe951000 0x1000>;
        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
        #iommu-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip IOMMU

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

description: |+
  A Rockchip DRM iommu translates io virtual addresses to physical addresses for
  its master device. Each slave device is bound to a single master device and
  shares its clocks, power domain and irq.

  For information on assigning IOMMU controller to its peripheral devices,
  see generic IOMMU bindings.

properties:
  compatible:
    enum:
      - rockchip,iommu
      - rockchip,rk3568-iommu

  reg:
    items:
      - description: configuration registers for MMU instance 0
      - description: configuration registers for MMU instance 1
    minItems: 1

  interrupts:
    items:
      - description: interruption for MMU instance 0
      - description: interruption for MMU instance 1
    minItems: 1

  clocks:
    items:
      - description: Core clock
      - description: Interface clock

  clock-names:
    items:
      - const: aclk
      - const: iface

  "#iommu-cells":
    const: 0

  power-domains:
    maxItems: 1

  rockchip,disable-mmu-reset:
    $ref: /schemas/types.yaml#/definitions/flag
    description: |
      Do not use the mmu reset operation.
      Some mmu instances may produce unexpected results
      when the reset operation is used.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - "#iommu-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3399-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    vopl_mmu: iommu@ff940300 {
      compatible = "rockchip,iommu";
      reg = <0xff940300 0x100>;
      interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
      clock-names = "aclk", "iface";
      #iommu-cells = <0>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/samsung,sysmmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)

maintainers:
  - Marek Szyprowski <m.szyprowski@samsung.com>

description: |+
  Samsung's Exynos architecture contains System MMUs that enables scattered
  physical memory chunks visible as a contiguous region to DMA-capable peripheral
  devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.

  System MMU is an IOMMU and supports identical translation table format to
  ARMv7 translation tables with minimum set of page properties including access
  permissions, shareability and security protection. In addition, System MMU has
  another capabilities like L2 TLB or block-fetch buffers to minimize translation
  latency.

  System MMUs are in many to one relation with peripheral devices, i.e. single
  peripheral device might have multiple System MMUs (usually one for each bus
  master), but one System MMU can handle transactions from only one peripheral
  device. The relation between a System MMU and the peripheral device needs to be
  defined in device node of the peripheral device.

  MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
  MMUs.
  * MFC has one System MMU on its left and right bus.
  * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
    for window 1, 2 and 3.
  * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
    the other System MMU on the write channel.

  For information on assigning System MMU controller to its peripheral devices,
  see generic IOMMU bindings.

properties:
  compatible:
    const: samsung,exynos-sysmmu

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    oneOf:
      - items:
          - const: sysmmu
      - items:
          - const: sysmmu
          - const: master
      - items:
          - const: aclk
          - const: pclk

  "#iommu-cells":
    const: 0

  power-domains:
    description: |
      Required if the System MMU is needed to gate its power.
      Please refer to the following document:
      Documentation/devicetree/bindings/power/pd-samsung.yaml
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - "#iommu-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5250.h>

    sysmmu_gsc0: iommu@13e80000 {
      compatible = "samsung,exynos-sysmmu";
      reg = <0x13E80000 0x1000>;
      interrupt-parent = <&combiner>;
      interrupts = <2 0>;
      clock-names = "sysmmu", "master";
      clocks = <&clock CLK_SMMU_GSCL0>,
               <&clock CLK_GSCL0>;
      power-domains = <&pd_gsc>;
      #iommu-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2020 Unisoc Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/sprd,iommu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Unisoc IOMMU and Multi-media MMU

maintainers:
  - Chunyan Zhang <zhang.lyra@gmail.com>

properties:
  compatible:
    enum:
      - sprd,iommu-v1

  "#iommu-cells":
    const: 0
    description:
      Unisoc IOMMUs are all single-master IOMMU devices, therefore no
      additional information needs to associate with its master device.
      Please refer to the generic bindings document for more details,
      Documentation/devicetree/bindings/iommu/iommu.txt

  reg:
    maxItems: 1

  clocks:
    description:
      Reference to a gate clock phandle, since access to some of IOMMUs are
      controlled by gate clock, but this is not required.

required:
  - compatible
  - reg
  - "#iommu-cells"

additionalProperties: false

examples:
  - |
    iommu_disp: iommu@63000800 {
      compatible = "sprd,iommu-v1";
      reg = <0x63000800 0x80>;
      #iommu-cells = <0>;
    };

  - |
    iommu_jpg: iommu@62300300 {
      compatible = "sprd,iommu-v1";
      reg = <0x62300300 0x80>;
      #iommu-cells = <0>;
      clocks = <&mm_gate 1>;
    };

...


code:
OMAP2+ IOMMU

Required properties:
- compatible : Should be one of,
		"ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
		"ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
		"ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
		"ti,dra7-iommu" for DRA7xx IOMMU instances
- ti,hwmods  : Name of the hwmod associated with the IOMMU instance
- reg        : Address space for the configuration registers
- interrupts : Interrupt specifier for the IOMMU instance
- #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
                 and needs no additional data in the pargs specifier. Please
                 also refer to the generic bindings document for more info
                 on this property,
                     Documentation/devicetree/bindings/iommu/iommu.txt

Optional properties:
- ti,#tlb-entries : Number of entries in the translation look-aside buffer.
                    Should be either 8 or 32 (default: 32)
- ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
		          back a bus error response on MMU faults.
- ti,syscon-mmuconfig : Should be a pair of the phandle to the DSP_SYSTEM
                        syscon node that contains the additional control
                        register for enabling the MMU, and the MMU instance
                        number (0-indexed) within the sub-system. This property
                        is required for DSP IOMMU instances on DRA7xx SoCs. The
                        instance number should be 0 for DSP MDMA MMUs and 1 for
                        DSP EDMA MMUs.

Example:
	/* OMAP3 ISP MMU */
	mmu_isp: mmu@480bd400 {
		#iommu-cells = <0>;
		compatible = "ti,omap2-iommu";
		reg = <0x480bd400 0x80>;
		interrupts = <24>;
		ti,hwmods = "mmu_isp";
		ti,#tlb-entries = <8>;
	};

	/* DRA74x DSP2 MMUs */
	mmu0_dsp2: mmu@41501000 {
		compatible = "ti,dra7-dsp-iommu";
		reg = <0x41501000 0x100>;
		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		ti,hwmods = "mmu0_dsp2";
		#iommu-cells = <0>;
		ti,syscon-mmuconfig = <&dsp2_system 0x0>;
	};

	mmu1_dsp2: mmu@41502000 {
		compatible = "ti,dra7-dsp-iommu";
		reg = <0x41502000 0x100>;
		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		ti,hwmods = "mmu1_dsp2";
		#iommu-cells = <0>;
		ti,syscon-mmuconfig = <&dsp2_system 0x1>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/xen,grant-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xen specific IOMMU for virtualized devices (e.g. virtio)

maintainers:
  - Stefano Stabellini <sstabellini@kernel.org>

description:
  The Xen IOMMU represents the Xen grant table interface. Grant mappings
  are to be used with devices connected to the Xen IOMMU using the "iommus"
  property, which also specifies the ID of the backend domain.
  The binding is required to restrict memory access using Xen grant mappings.

properties:
  compatible:
    const: xen,grant-dma

  '#iommu-cells':
    const: 1
    description:
      The single cell is the domid (domain ID) of the domain where the backend
      is running.

required:
  - compatible
  - "#iommu-cells"

additionalProperties: false

examples:
  - |
    iommu {
        compatible = "xen,grant-dma";
        #iommu-cells = <1>;
    };


code:
* Aspeed BT (Block Transfer) IPMI interface

The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
(BaseBoard Management Controllers) and the BT interface can be used to
perform in-band IPMI communication with their host.

Required properties:

- compatible : should be one of
	"aspeed,ast2400-ibt-bmc"
	"aspeed,ast2500-ibt-bmc"
	"aspeed,ast2600-ibt-bmc"
- reg: physical address and size of the registers
- clocks: clock for the device

Optional properties:

- interrupts: interrupt generated by the BT interface. without an
  interrupt, the driver will operate in poll mode.

Example:

	ibt@1e789140 {
		compatible = "aspeed,ast2400-ibt-bmc";
		reg = <0x1e789140 0x18>;
		interrupts = <8>;
		clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED BMC KCS Devices

maintainers:
  - Andrew Jeffery <andrew@aj.id.au>

description: |
  The Aspeed BMC SoCs typically use the Keyboard-Controller-Style (KCS)
  interfaces on the LPC bus for in-band IPMI communication with their host.

properties:
  compatible:
    oneOf:
      - description: Channel ID derived from reg
        items:
          enum:
            - aspeed,ast2400-kcs-bmc-v2
            - aspeed,ast2500-kcs-bmc-v2
            - aspeed,ast2600-kcs-bmc

      - description: Old-style with explicit channel ID, no reg
        deprecated: true
        items:
          enum:
            - aspeed,ast2400-kcs-bmc
            - aspeed,ast2500-kcs-bmc

  interrupts:
    maxItems: 1

  reg:
    # maxItems: 3
    items:
      - description: IDR register
      - description: ODR register
      - description: STR register

  aspeed,lpc-io-reg:
    $ref: '/schemas/types.yaml#/definitions/uint32-array'
    minItems: 1
    maxItems: 2
    description: |
      The host CPU LPC IO data and status addresses for the device. For most
      channels the status address is derived from the data address, but the
      status address may be optionally provided.

  aspeed,lpc-interrupts:
    $ref: "/schemas/types.yaml#/definitions/uint32-array"
    minItems: 2
    maxItems: 2
    description: |
      A 2-cell property expressing the LPC SerIRQ number and the interrupt
      level/sense encoding (specified in the standard fashion).

      Note that the generated interrupt is issued from the BMC to the host, and
      thus the target interrupt controller is not captured by the BMC's
      devicetree.

  kcs_chan:
    deprecated: true
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description: The LPC channel number in the controller

  kcs_addr:
    deprecated: true
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description: The host CPU IO map address

required:
  - compatible
  - interrupts

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - aspeed,ast2400-kcs-bmc
              - aspeed,ast2500-kcs-bmc
    then:
      required:
        - kcs_chan
        - kcs_addr
    else:
      required:
        - reg
        - aspeed,lpc-io-reg

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    kcs3: kcs@24 {
        compatible = "aspeed,ast2600-kcs-bmc";
        reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
        aspeed,lpc-io-reg = <0xca2>;
        aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
        interrupts = <8>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ipmi/ipmi-ipmb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: IPMI IPMB device bindings

description: IPMI IPMB device bindings

maintainers:
  - Corey Minyard <cminyard@mvista.com>

properties:
  compatible:
    enum:
      - ipmi-ipmb

  device_type:
    items:
      - const: "ipmi"

  reg:
    maxItems: 1

  bmcaddr:
    $ref: /schemas/types.yaml#/definitions/uint8
    description: The address of the BMC on the IPMB bus.  Defaults to 0x20.

  retry-time:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Time between retries of sends, in milliseconds.  Defaults to 250.

  max-retries:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Number of retries before a failure is declared.  Defaults to 1.

  slave-dev:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      The slave i2c device.  If not present, the main device is used. This
      lets you use two devices on the IPMB, one for master and one for slave,
      in case you have a slave device that can only be a slave.  The slave
      will receive messages and the master will transmit.

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
            #address-cells = <1>;
            #size-cells = <0>;

            ipmi-ipmb@40 {
                    compatible = "ipmi-ipmb";
                    device_type = "ipmi";
                    reg = <0x40>;
                    bmcaddr = /bits/ 8 <0x20>;
                    retry-time = <250>;
                    max-retries = <1>;
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ipmi/ipmi-smic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: IPMI device bindings

description: IPMI device bindings

maintainers:
  - Corey Minyard <cminyard@mvista.com>

properties:
  compatible:
    enum:
      - ipmi-kcs
      - ipmi-smic
      - ipmi-bt

  device_type:
    items:
      - const: "ipmi"

  reg:
    maxItems: 1

  interrupts:
    description: Interface is polled if this property is omitted.
    maxItems: 1

  reg-size:
    description: The access width of the register in bytes. Defaults to 1.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2, 4, 8]

  reg-spacing:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The number of bytes between register starts. Defaults to 1.

  reg-shift:
    description: |
      The amount of bits to shift the register content to the right to get
      the data into bit zero.
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 56

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    smic@fff3a000 {
        compatible = "ipmi-smic";
        device_type = "ipmi";
        reg = <0xfff3a000 0x1000>;
        interrupts = <0 24 4>;
        reg-size = <4>;
        reg-spacing = <4>;
    };


code:
* Nuvoton NPCM KCS (Keyboard Controller Style) IPMI interface

The Nuvoton SOCs (NPCM) are commonly used as BMCs
(Baseboard Management Controllers) and the KCS interface can be
used to perform in-band IPMI communication with their host.

Required properties:
- compatible : should be one of
    "nuvoton,npcm750-kcs-bmc"
    "nuvoton,npcm845-kcs-bmc", "nuvoton,npcm750-kcs-bmc"
- interrupts : interrupt generated by the controller
- kcs_chan : The KCS channel number in the controller

Example:

    lpc_kcs: lpc_kcs@f0007000 {
        compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
        reg = <0xf0007000 0x40>;
        reg-io-width = <1>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0xf0007000 0x40>;

        kcs1: kcs1@0 {
            compatible = "nuvoton,npcm750-kcs-bmc";
            reg = <0x0 0x40>;
            interrupts = <0 9 4>;
            kcs_chan = <1>;
            status = "disabled";
        };

        kcs2: kcs2@0 {
            compatible = "nuvoton,npcm750-kcs-bmc";
            reg = <0x0 0x40>;
            interrupts = <0 9 4>;
            kcs_chan = <2>;
            status = "disabled";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ipmi/ssif-bmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SSIF IPMI BMC interface

description: SSIF IPMI BMC device bindings

maintainers:
  - Quan Nguyen <quan@os.amperecomputing.com>

properties:
  compatible:
    enum:
      - ssif-bmc

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        ssif-bmc@10 {
            compatible = "ssif-bmc";
            reg = <0x10>;
        };
    };


code:
Jailhouse non-root cell device tree bindings
--------------------------------------------

When running in a non-root Jailhouse cell (partition), the device tree of this
platform shall have a top-level "hypervisor" node with the following
properties:

- compatible = "jailhouse,cell"