code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 MIPI-DSI Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    oneOf:
      - enum:
          - allwinner,sun6i-a31-mipi-dsi
          - allwinner,sun50i-a64-mipi-dsi
          - allwinner,sun50i-a100-mipi-dsi
      - items:
          - const: allwinner,sun20i-d1-mipi-dsi
          - const: allwinner,sun50i-a100-mipi-dsi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: Bus Clock
      - description: Module Clock

  clock-names:
    items:
      - const: bus
      - const: mod

  resets:
    maxItems: 1

  vcc-dsi-supply:
    description: VCC-DSI power supply of the DSI encoder

  phys:
    maxItems: 1

  phy-names:
    const: dphy

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      The port should be the input endpoint, usually coming from the
      associated TCON.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - phys
  - phy-names
  - resets
  - port

allOf:
  - $ref: dsi-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun6i-a31-mipi-dsi
              - allwinner,sun50i-a100-mipi-dsi

    then:
      properties:
        clocks:
          minItems: 2

      required:
        - clock-names

    else:
      properties:
        clocks:
          maxItems: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun6i-a31-mipi-dsi
              - allwinner,sun50i-a64-mipi-dsi

    then:
      required:
        - vcc-dsi-supply

unevaluatedProperties: false

examples:
  - |
    dsi0: dsi@1ca0000 {
        compatible = "allwinner,sun6i-a31-mipi-dsi";
        reg = <0x01ca0000 0x1000>;
        interrupts = <0 89 4>;
        clocks = <&ccu 23>, <&ccu 96>;
        clock-names = "bus", "mod";
        resets = <&ccu 4>;
        phys = <&dphy0>;
        phy-names = "dphy";
        vcc-dsi-supply = <&reg_dcdc1>;
        #address-cells = <1>;
        #size-cells = <0>;

        panel@0 {
                compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
                reg = <0>;
                power-supply = <&reg_display>;
                reset-gpios = <&r_pio 0 5 1>; /* PL05 */
                backlight = <&pwm_bl>;
        };

        port {
            dsi0_in_tcon0: endpoint {
                remote-endpoint = <&tcon0_out_dsi0>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-de2-mixer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner Display Engine 2.0 Mixer

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    enum:
      - allwinner,sun8i-a83t-de2-mixer-0
      - allwinner,sun8i-a83t-de2-mixer-1
      - allwinner,sun8i-h3-de2-mixer-0
      - allwinner,sun8i-r40-de2-mixer-0
      - allwinner,sun8i-r40-de2-mixer-1
      - allwinner,sun8i-v3s-de2-mixer
      - allwinner,sun20i-d1-de2-mixer-0
      - allwinner,sun20i-d1-de2-mixer-1
      - allwinner,sun50i-a64-de2-mixer-0
      - allwinner,sun50i-a64-de2-mixer-1
      - allwinner,sun50i-h6-de3-mixer-0

  reg:
    maxItems: 1

  clocks:
    items:
      - description: The mixer interface clock
      - description: The mixer module clock

  clock-names:
    items:
      - const: bus
      - const: mod

  iommus:
    maxItems: 1

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Input endpoints of the controller.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Output endpoints of the controller.

    required:
      - port@1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/sun8i-de2.h>
    #include <dt-bindings/reset/sun8i-de2.h>

    mixer0: mixer@1100000 {
        compatible = "allwinner,sun8i-a83t-de2-mixer-0";
        reg = <0x01100000 0x100000>;
        clocks = <&display_clocks CLK_BUS_MIXER0>,
                 <&display_clocks CLK_MIXER0>;
        clock-names = "bus",
                      "mod";
        resets = <&display_clocks RST_MIXER0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            mixer0_out: port@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;

                mixer0_out_tcon0: endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&tcon0_in_mixer0>;
                };

                mixer0_out_tcon1: endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&tcon1_in_mixer0>;
                };
            };
        };
    };

...

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A83t DWC HDMI TX Encoder

description: |
  The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
  IP with Allwinner\'s own PHY IP. It supports audio and video outputs
  and CEC.

  These DT bindings follow the Synopsys DWC HDMI TX bindings defined
  in bridge/synopsys,dw-hdmi.yaml with the following device-specific
  properties.

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 0

  compatible:
    oneOf:
      - const: allwinner,sun8i-a83t-dw-hdmi
      - const: allwinner,sun50i-h6-dw-hdmi

      - items:
          - enum:
              - allwinner,sun8i-h3-dw-hdmi
              - allwinner,sun8i-r40-dw-hdmi
              - allwinner,sun50i-a64-dw-hdmi
          - const: allwinner,sun8i-a83t-dw-hdmi

  reg:
    maxItems: 1

  reg-io-width:
    const: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    items:
      - description: Bus Clock
      - description: Register Clock
      - description: TMDS Clock
      - description: HDMI CEC Clock
      - description: HDCP Clock
      - description: HDCP Bus Clock

  clock-names:
    minItems: 3
    items:
      - const: iahb
      - const: isfr
      - const: tmds
      - const: cec
      - const: hdcp
      - const: hdcp-bus

  resets:
    minItems: 1
    items:
      - description: HDMI Controller Reset
      - description: HDCP Reset

  reset-names:
    minItems: 1
    items:
      - const: ctrl
      - const: hdcp

  phys:
    maxItems: 1
    description:
      Phandle to the DWC HDMI PHY.

  phy-names:
    const: phy

  hvcc-supply:
    description:
      The VCC power supply of the controller

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Input endpoints of the controller. Usually the associated
          TCON.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Output endpoints of the controller. Usually an HDMI
          connector.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - reg-io-width
  - interrupts
  - clocks
  - clock-names
  - resets
  - reset-names
  - phys
  - phy-names
  - ports

if:
  properties:
    compatible:
      contains:
        enum:
          - allwinner,sun50i-h6-dw-hdmi

then:
  properties:
    clocks:
      minItems: 6

    clock-names:
      minItems: 6

    resets:
      minItems: 2

    reset-names:
      minItems: 2

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    /*
     * This comes from the clock/sun8i-a83t-ccu.h and
     * reset/sun8i-a83t-ccu.h headers, but we can't include them since
     * it would trigger a bunch of warnings for redefinitions of
     * symbols with the other example.
     */
    #define CLK_BUS_HDMI	39
    #define CLK_HDMI		93
    #define CLK_HDMI_SLOW	94
    #define RST_BUS_HDMI1	26

    hdmi@1ee0000 {
        compatible = "allwinner,sun8i-a83t-dw-hdmi";
        reg = <0x01ee0000 0x10000>;
        reg-io-width = <1>;
        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
                 <&ccu CLK_HDMI>;
        clock-names = "iahb", "isfr", "tmds";
        resets = <&ccu RST_BUS_HDMI1>;
        reset-names = "ctrl";
        phys = <&hdmi_phy>;
        phy-names = "phy";
        pinctrl-names = "default";
        pinctrl-0 = <&hdmi_pins>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                endpoint {
                    remote-endpoint = <&tcon1_out_hdmi>;
                };
            };

            port@1 {
                reg = <1>;
            };
        };
    };

    /* Cleanup after ourselves */
    #undef CLK_BUS_HDMI
    #undef CLK_HDMI
    #undef CLK_HDMI_SLOW

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    /*
     * This comes from the clock/sun50i-h6-ccu.h and
     * reset/sun50i-h6-ccu.h headers, but we can't include them since
     * it would trigger a bunch of warnings for redefinitions of
     * symbols with the other example.
     */
    #define CLK_BUS_HDMI	126
    #define CLK_BUS_HDCP	137
    #define CLK_HDMI		123
    #define CLK_HDMI_SLOW	124
    #define CLK_HDMI_CEC	125
    #define CLK_HDCP		136
    #define RST_BUS_HDMI_SUB	57
    #define RST_BUS_HDCP	62

    hdmi@6000000 {
        compatible = "allwinner,sun50i-h6-dw-hdmi";
        reg = <0x06000000 0x10000>;
        reg-io-width = <1>;
        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
                 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
                 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
        clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
                      "hdcp-bus";
        resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
        reset-names = "ctrl", "hdcp";
        phys = <&hdmi_phy>;
        phy-names = "phy";
        pinctrl-names = "default";
        pinctrl-0 = <&hdmi_pins>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                endpoint {
                    remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
                };
            };

            port@1 {
                reg = <1>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-hdmi-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A83t HDMI PHY

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 0

  compatible:
    enum:
      - allwinner,sun8i-a83t-hdmi-phy
      - allwinner,sun8i-h3-hdmi-phy
      - allwinner,sun8i-r40-hdmi-phy
      - allwinner,sun50i-a64-hdmi-phy
      - allwinner,sun50i-h6-hdmi-phy

  reg:
    maxItems: 1

  clocks:
    minItems: 2
    items:
      - description: Bus Clock
      - description: Module Clock
      - description: Parent of the PHY clock
      - description: Second possible parent of the PHY clock

  clock-names:
    minItems: 2
    items:
      - const: bus
      - const: mod
      - const: pll-0
      - const: pll-1

  resets:
    maxItems: 1

  reset-names:
    const: phy

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names

if:
  properties:
    compatible:
      contains:
        enum:
          - allwinner,sun8i-r40-hdmi-phy

then:
  properties:
    clocks:
      minItems: 4

    clock-names:
      minItems: 4

else:
  if:
    properties:
      compatible:
        contains:
          enum:
            - allwinner,sun8i-h3-hdmi-phy
            - allwinner,sun50i-a64-hdmi-phy

  then:
    properties:
      clocks:
        minItems: 3

      clock-names:
        minItems: 3

  else:
    properties:
      clocks:
        maxItems: 2

      clock-names:
        maxItems: 2

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/sun8i-a83t-ccu.h>
    #include <dt-bindings/reset/sun8i-a83t-ccu.h>

    hdmi_phy: hdmi-phy@1ef0000 {
        compatible = "allwinner,sun8i-a83t-hdmi-phy";
        reg = <0x01ef0000 0x10000>;
        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
        clock-names = "bus", "mod";
        resets = <&ccu RST_BUS_HDMI0>;
        reset-names = "phy";
        #phy-cells = <0>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner R40 TCON TOP

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |
  TCON TOPs main purpose is to configure whole display pipeline. It
  determines relationships between mixers and TCONs, selects source
  TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV
  encoder clock source and contains additional TV TCON and DSI gates.

  It allows display pipeline to be configured in very different ways:

                                  / LCD0/LVDS0
                   / [0] TCON-LCD0
                   |              \ MIPI DSI
   mixer0          |
          \        / [1] TCON-LCD1 - LCD1/LVDS1
           TCON-TOP
          /        \ [2] TCON-TV0 [0] - TVE0/RGB
   mixer1          |                  \
                   |                   TCON-TOP - HDMI
                   |                  /
                   \ [3] TCON-TV1 [1] - TVE1/RGB

  Note that both TCON TOP references same physical unit. Both mixers
  can be connected to any TCON. Not all TCON TOP variants support all
  features.

properties:
  "#clock-cells":
    const: 1

  compatible:
    enum:
      - allwinner,sun8i-r40-tcon-top
      - allwinner,sun20i-d1-tcon-top
      - allwinner,sun50i-h6-tcon-top

  reg:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 6

  clock-names:
    minItems: 2
    maxItems: 6

  clock-output-names:
    minItems: 1
    maxItems: 3

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Input endpoint for Mixer 0 mux.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Output endpoint for Mixer 0 mux

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Input endpoint for Mixer 1 mux.

      port@3:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Output endpoint for Mixer 1 mux

      port@4:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Input endpoint for HDMI mux.

      port@5:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Output endpoint for HDMI mux

    required:
      - port@0
      - port@1
      - port@4
      - port@5

required:
  - "#clock-cells"
  - compatible
  - reg
  - clocks
  - clock-names
  - clock-output-names
  - resets
  - ports

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: allwinner,sun8i-r40-tcon-top

    then:
      properties:
        clocks:
          items:
            - description: The TCON TOP interface clock
            - description: The TCON TOP TV0 clock
            - description: The TCON TOP TVE0 clock
            - description: The TCON TOP TV1 clock
            - description: The TCON TOP TVE1 clock
            - description: The TCON TOP MIPI DSI clock

        clock-names:
          items:
            - const: bus
            - const: tcon-tv0
            - const: tve0
            - const: tcon-tv1
            - const: tve1
            - const: dsi

        clock-output-names:
          items:
            - description: TCON TV0 output clock name
            - description: TCON TV1 output clock name
            - description: DSI output clock name

        ports:
          required:
            - port@2
            - port@3

  - if:
      properties:
        compatible:
          contains:
            const: allwinner,sun20i-d1-tcon-top

    then:
      properties:
        clocks:
          items:
            - description: The TCON TOP interface clock
            - description: The TCON TOP TV0 clock
            - description: The TCON TOP TVE0 clock
            - description: The TCON TOP MIPI DSI clock

        clock-names:
          items:
            - const: bus
            - const: tcon-tv0
            - const: tve0
            - const: dsi

        clock-output-names:
          items:
            - description: TCON TV0 output clock name
            - description: DSI output clock name

  - if:
      properties:
        compatible:
          contains:
            const: allwinner,sun50i-h6-tcon-top

    then:
      properties:
        clocks:
          items:
            - description: The TCON TOP interface clock
            - description: The TCON TOP TV0 clock

        clock-names:
          items:
            - const: bus
            - const: tcon-tv0

        clock-output-names:
          items:
            - description: TCON TV0 output clock name

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/sun8i-r40-ccu.h>
    #include <dt-bindings/reset/sun8i-r40-ccu.h>

      tcon_top: tcon-top@1c70000 {
          compatible = "allwinner,sun8i-r40-tcon-top";
          reg = <0x01c70000 0x1000>;
          clocks = <&ccu CLK_BUS_TCON_TOP>,
                   <&ccu CLK_TCON_TV0>,
                   <&ccu CLK_TVE0>,
                   <&ccu CLK_TCON_TV1>,
                   <&ccu CLK_TVE1>,
                   <&ccu CLK_DSI_DPHY>;
          clock-names = "bus",
                        "tcon-tv0",
                        "tve0",
                        "tcon-tv1",
                        "tve1",
                        "dsi";
          clock-output-names = "tcon-top-tv0",
                               "tcon-top-tv1",
                               "tcon-top-dsi";
          resets = <&ccu RST_BUS_TCON_TOP>;
          #clock-cells = <1>;

          ports {
              #address-cells = <1>;
              #size-cells = <0>;

              tcon_top_mixer0_in: port@0 {
                  reg = <0>;

                  tcon_top_mixer0_in_mixer0: endpoint {
                      remote-endpoint = <&mixer0_out_tcon_top>;
                  };
              };

              tcon_top_mixer0_out: port@1 {
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <1>;

                  tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
                      reg = <0>;
                  };

                  tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
                      reg = <1>;
                  };

                  tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
                      reg = <2>;
                      remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
                  };

                  tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
                      reg = <3>;
                      remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
                  };
              };

              tcon_top_mixer1_in: port@2 {
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <2>;

                  tcon_top_mixer1_in_mixer1: endpoint@1 {
                      reg = <1>;
                      remote-endpoint = <&mixer1_out_tcon_top>;
                  };
              };

              tcon_top_mixer1_out: port@3 {
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <3>;

                  tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
                      reg = <0>;
                  };

                  tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
                      reg = <1>;
                  };

                  tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
                      reg = <2>;
                      remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
                  };

                  tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
                      reg = <3>;
                      remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
                  };
              };

              tcon_top_hdmi_in: port@4 {
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <4>;

                  tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
                      reg = <0>;
                      remote-endpoint = <&tcon_tv0_out_tcon_top>;
                  };

                  tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
                      reg = <1>;
                      remote-endpoint = <&tcon_tv1_out_tcon_top>;
                  };
              };

              tcon_top_hdmi_out: port@5 {
                  reg = <5>;

                  tcon_top_hdmi_out_hdmi: endpoint {
                      remote-endpoint = <&hdmi_in_tcon_top>;
                  };
              };
          };
      };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun9i-a80-deu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A80 Detail Enhancement Unit

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |
  The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
  can sharpen the display content in both luma and chroma channels.

properties:
  compatible:
    const: allwinner,sun9i-a80-deu

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: The DEU interface clock
      - description: The DEU module clock
      - description: The DEU DRAM clock

  clock-names:
    items:
      - const: ahb
      - const: mod
      - const: ram

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Input endpoints of the controller.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Output endpoints of the controller.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/sun9i-a80-de.h>
    #include <dt-bindings/reset/sun9i-a80-de.h>

    deu0: deu@3300000 {
        compatible = "allwinner,sun9i-a80-deu";
        reg = <0x03300000 0x40000>;
        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&de_clocks CLK_BUS_DEU0>,
                 <&de_clocks CLK_IEP_DEU0>,
                 <&de_clocks CLK_DRAM_DEU0>;
        clock-names = "ahb",
                      "mod",
                      "ram";
        resets = <&de_clocks RST_DEU0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            deu0_in: port@0 {
                reg = <0>;

                deu0_in_fe0: endpoint {
                    remote-endpoint = <&fe0_out_deu0>;
                };
            };

            deu0_out: port@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;

                deu0_out_be0: endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&be0_in_deu0>;
                };

                deu0_out_be1: endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&be1_in_deu0>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic specific extensions to the Synopsys Designware HDMI Controller

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

allOf:
  - $ref: /schemas/sound/dai-common.yaml#

description: |
  The Amlogic Meson Synopsys Designware Integration is composed of
  - A Synopsys DesignWare HDMI Controller IP
  - A TOP control block controlling the Clocks and PHY
  - A custom HDMI PHY in order to convert video to TMDS signal
   ___________________________________
  |            HDMI TOP               |<= HPD
  |___________________________________|
  |                  |                |
  |  Synopsys HDMI   |   HDMI PHY     |=> TMDS
  |    Controller    |________________|
  |___________________________________|<=> DDC

  The HDMI TOP block only supports HPD sensing.
  The Synopsys HDMI Controller interrupt is routed through the
  TOP Block interrupt.
  Communication to the TOP Block and the Synopsys HDMI Controller is done
  via a pair of dedicated addr+read/write registers.
  The HDMI PHY is configured by registers in the HHI register block.

  Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDMI mux
  selects either the ENCI encoder for the 576i or 480i formats or the ENCP
  encoder for all the other formats including interlaced HD formats.

  The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
  DVI timings for the HDMI controller.

  Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
  HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
  audio source interfaces.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - amlogic,meson-gxbb-dw-hdmi # GXBB (S905)
              - amlogic,meson-gxl-dw-hdmi # GXL (S905X, S905D)
              - amlogic,meson-gxm-dw-hdmi # GXM (S912)
          - const: amlogic,meson-gx-dw-hdmi
      - enum:
          - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3

  clock-names:
    items:
      - const: isfr
      - const: iahb
      - const: venci

  resets:
    minItems: 3

  reset-names:
    items:
      - const: hdmitx_apb
      - const: hdmitx
      - const: hdmitx_phy

  hdmi-supply:
    description: phandle to an external 5V regulator to power the HDMI logic

  port@0:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      A port node pointing to the VENC Input port node.

  port@1:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      A port node pointing to the TMDS Output port node.

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  "#sound-dai-cells":
    const: 0

  sound-name-prefix: true

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - reset-names
  - port@0
  - port@1
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:
  - |
    hdmi_tx: hdmi-tx@c883a000 {
        compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
        reg = <0xc883a000 0x1c>;
        interrupts = <57>;
        resets = <&reset_apb>, <&reset_hdmitx>, <&reset_hdmitx_phy>;
        reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
        clocks = <&clk_isfr>, <&clk_iahb>, <&clk_venci>;
        clock-names = "isfr", "iahb", "venci";
        #address-cells = <1>;
        #size-cells = <0>;

        /* VPU VENC Input */
        hdmi_tx_venc_port: port@0 {
            reg = <0>;

            hdmi_tx_in: endpoint {
                remote-endpoint = <&hdmi_tx_out>;
            };
        };

        /* TMDS Output */
        hdmi_tx_tmds_port: port@1 {
             reg = <1>;

             hdmi_tx_tmds_out: endpoint {
                 remote-endpoint = <&hdmi_connector_in>;
             };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Meson Display Controller

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

description: |
  The Amlogic Meson Display controller is composed of several components
  that are going to be documented below

  DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
     | vd1   _______     _____________    _________________     |               |
  D  |-------|      |----|            |   |                |    |   HDMI PLL    |
  D  | vd2   | VIU  |    | Video Post |   | Video Encoders |<---|-----VCLK      |
  R  |-------|      |----| Processing |   |                |    |               |
     | osd2  |      |    |            |---| Enci ----------|----|-----VDAC------|
  R  |-------| CSC  |----| Scalers    |   | Encp ----------|----|----HDMI-TX----|
  A  | osd1  |      |    | Blenders   |   | Encl ----------|----|---------------|
  M  |-------|______|----|____________|   |________________|    |               |
  ___|__________________________________________________________|_______________|

  VIU: Video Input Unit
  ---------------------

  The Video Input Unit is in charge of the pixel scanout from the DDR memory.
  It fetches the frames addresses, stride and parameters from the "Canvas" memory.
  This part is also in charge of the CSC (Colorspace Conversion).
  It can handle 2 OSD Planes and 2 Video Planes.

  VPP: Video Post Processing
  --------------------------

  The Video Post Processing is in charge of the scaling and blending of the
  various planes into a single pixel stream.
  There is a special "pre-blending" used by the video planes with a dedicated
  scaler and a "post-blending" to merge with the OSD Planes.
  The OSD planes also have a dedicated scaler for one of the OSD.

  VENC: Video Encoders
  --------------------

  The VENC is composed of the multiple pixel encoders
   - ENCI : Interlace Video encoder for CVBS and Interlace HDMI
   - ENCP : Progressive Video Encoder for HDMI
   - ENCL : LCD LVDS Encoder
  The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
  tree and provides the scanout clock to the VPP and VIU.
  The ENCI is connected to a single VDAC for Composite Output.
  The ENCI and ENCP are connected to an on-chip HDMI Transceiver.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - amlogic,meson-gxbb-vpu # GXBB (S905)
              - amlogic,meson-gxl-vpu # GXL (S905X, S905D)
              - amlogic,meson-gxm-vpu # GXM (S912)
          - const: amlogic,meson-gx-vpu
      - enum:
          - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: vpu
      - const: hhi

  interrupts:
    maxItems: 1

  amlogic,canvas:
    description: should point to a canvas provider node
    $ref: /schemas/types.yaml#/definitions/phandle

  power-domains:
    maxItems: 1
    description: phandle to the associated power domain

  port@0:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      A port node pointing to the CVBS VDAC port node.

  port@1:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      A port node pointing to the HDMI-TX port node.

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

required:
  - compatible
  - reg
  - interrupts
  - port@0
  - port@1
  - "#address-cells"
  - "#size-cells"
  - amlogic,canvas

additionalProperties: false

examples:
  - |
    vpu: vpu@d0100000 {
        compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
        reg = <0xd0100000 0x100000>, <0xc883c000 0x1000>;
        reg-names = "vpu", "hhi";
        interrupts = <3>;
        #address-cells = <1>;
        #size-cells = <0>;
        amlogic,canvas = <&canvas>;

        /* CVBS VDAC output port */
        port@0 {
            reg = <0>;

            cvbs_vdac_out: endpoint {
                remote-endpoint = <&tv_connector_in>;
            };
        };

        /* HDMI TX output port */
        port@1 {
            reg = <1>;

            hdmi_tx_out: endpoint {
                remote-endpoint = <&hdmi_tx_in>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,hdlcd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm HDLCD display controller binding

maintainers:
  - Liviu Dudau <Liviu.Dudau@arm.com>
  - Andre Przywara <andre.przywara@arm.com>

description:
  The Arm HDLCD is a display controller found on several development platforms
  produced by ARM Ltd and in more modern of its Fast Models. The HDLCD is an
  RGB streamer that reads the data from a framebuffer and sends it to a single
  digital encoder (DVI or HDMI).

properties:
  compatible:
    const: arm,hdlcd

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clock-names:
    const: pxlclk

  clocks:
    maxItems: 1
    description: The input reference for the pixel clock.

  memory-region:
    maxItems: 1
    description:
      Phandle to a node describing memory to be used for the framebuffer.
      If not present, the framebuffer may be located anywhere in memory.

  iommus:
    maxItems: 1

  port:
    $ref: /schemas/graph.yaml#/properties/port
    unevaluatedProperties: false
    description:
      Output endpoint of the controller, connecting the LCD panel signals.

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - port

examples:
  - |
    hdlcd@2b000000 {
        compatible = "arm,hdlcd";
        reg = <0x2b000000 0x1000>;
        interrupts = <0 85 4>;
        clocks = <&oscclk5>;
        clock-names = "pxlclk";
        port {
            hdlcd_output: endpoint {
                remote-endpoint = <&hdmi_enc_input>;
            };
        };
    };

    /* HDMI encoder on I2C bus */
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;
        hdmi-transmitter@70 {
            compatible = "nxp,tda998x";
            reg = <0x70>;
            port {
                hdmi_enc_input: endpoint {
                    remote-endpoint = <&hdlcd_output>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,komeda.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm Komeda display processor

maintainers:
  - Liviu Dudau <Liviu.Dudau@arm.com>
  - Andre Przywara <andre.przywara@arm.com>

description:
  The Arm Mali D71 display processor supports up to two displays with up
  to a 4K resolution each. Each pipeline can be composed of up to four
  layers. It is typically connected to a digital display connector like HDMI.

properties:
  compatible:
    oneOf:
      - items:
          - const: arm,mali-d32
          - const: arm,mali-d71
      - const: arm,mali-d71

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clock-names:
    const: aclk

  clocks:
    maxItems: 1
    description: The main DPU processor clock

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  memory-region:
    maxItems: 1
    description:
      Phandle to a node describing memory to be used for the framebuffer.
      If not present, the framebuffer may be located anywhere in memory.

  iommus:
    description:
      The stream IDs for each of the used pipelines, each four IDs for the
      four layers, plus one for the write-back stream.
    minItems: 5
    maxItems: 10

patternProperties:
  '^pipeline@[01]$':
    type: object
    additionalProperties: false
    description:
      clocks

    properties:
      reg:
        enum: [ 0, 1 ]

      clock-names:
        const: pxclk

      clocks:
        maxItems: 1
        description: The input reference for the pixel clock.

      port:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false

additionalProperties: false

required:
  - "#address-cells"
  - "#size-cells"
  - compatible
  - reg
  - interrupts
  - clock-names
  - clocks
  - pipeline@0

examples:
  - |
    display@c00000 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "arm,mali-d71";
        reg = <0xc00000 0x20000>;
        interrupts = <168>;
        clocks = <&dpu_aclk>;
        clock-names = "aclk";
        iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
                 <&smmu 8>,
                 <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
                 <&smmu 9>;

        dp0_pipe0: pipeline@0 {
            clocks = <&fpgaosc2>;
            clock-names = "pxclk";
            reg = <0>;

            port {
                dp0_pipe0_out: endpoint {
                    remote-endpoint = <&db_dvi0_in>;
                };
            };
        };

        dp0_pipe1: pipeline@1 {
            clocks = <&fpgaosc2>;
            clock-names = "pxclk";
            reg = <1>;

            port {
                dp0_pipe1_out: endpoint {
                    remote-endpoint = <&db_dvi1_in>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,malidp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm Mali Display Processor (Mali-DP) binding

maintainers:
  - Liviu Dudau <Liviu.Dudau@arm.com>
  - Andre Przywara <andre.przywara@arm.com>

description:
  The following bindings apply to a family of Display Processors sold as
  licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
  DP650 processors that offer multiple composition layers, support for
  rotation and scaling output.

properties:
  compatible:
    enum:
      - arm,mali-dp500
      - arm,mali-dp550
      - arm,mali-dp650

  reg:
    maxItems: 1

  interrupts:
    items:
      - description:
          The interrupt used by the Display Engine (DE). Can be shared with
          the interrupt for the Scaling Engine (SE), but it will have to be
          listed individually.
      - description:
          The interrupt used by the Scaling Engine (SE). Can be shared with
          the interrupt for the Display Engine (DE), but it will have to be
          listed individually.

  interrupt-names:
    items:
      - const: DE
      - const: SE

  clock-names:
    items:
      - const: pxlclk
      - const: mclk
      - const: aclk
      - const: pclk

  clocks:
    items:
      - description: the pixel clock feeding the output PLL of the processor
      - description: the main processor clock
      - description: the AXI interface clock
      - description: the APB interface clock

  memory-region:
    maxItems: 1
    description:
      Phandle to a node describing memory to be used for the framebuffer.
      If not present, the framebuffer may be located anywhere in memory.

  arm,malidp-output-port-lines:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    description:
      Number of output lines/bits for each colour channel.
    items:
      - description: number of output lines for the red channel (R)
      - description: number of output lines for the green channel (G)
      - description: number of output lines for the blue channel (B)

  arm,malidp-arqos-value:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Quality-of-Service value for the display engine FIFOs, to write
      into the RQOS register of the DP500.
      See the ARM Mali-DP500 TRM for details on the encoding.
      If omitted, the RQOS register will not be changed.

  port:
    $ref: /schemas/graph.yaml#/properties/port
    unevaluatedProperties: false
    description:
      Output endpoint of the controller, connecting the LCD panel signals.

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - port
  - arm,malidp-output-port-lines

examples:
  - |
    dp0: malidp@6f200000 {
        compatible = "arm,mali-dp650";
        reg = <0x6f200000 0x20000>;
        memory-region = <&display_reserved>;
        interrupts = <168>, <168>;
        interrupt-names = "DE", "SE";
        clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
        clock-names = "pxlclk", "mclk", "aclk", "pclk";
        arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
        arm,malidp-arqos-value = <0xd000d000>;

        port {
            dp0_output: endpoint {
                remote-endpoint = <&tda998x_2_input>;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,pl11x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm PrimeCell Color LCD Controller PL110/PL111

maintainers:
  - Liviu Dudau <Liviu.Dudau@arm.com>
  - Andre Przywara <andre.przywara@arm.com>

description:
  The Arm Primcell PL010/PL111 is an LCD controller IP, than scans out
  a framebuffer region in system memory, and creates timed signals for
  a variety of LCD panels.

# We need a select here so we don't match all nodes with 'arm,primecell'
select:
  properties:
    compatible:
      contains:
        enum:
          - arm,pl110
          - arm,pl111
  required:
    - compatible

properties:
  compatible:
    items:
      - enum:
          - arm,pl110
          - arm,pl111
      - const: arm,primecell

  reg:
    maxItems: 1

  interrupt-names:
    oneOf:
      - const: combined
        description:
          The IP provides four individual interrupt lines, but also one
          combined line. If the integration only connects this line to the
          interrupt controller, this single interrupt is noted here.
      - items:
          - const: mbe        # CLCDMBEINTR
          - const: vcomp      # CLCDVCOMPINTR
          - const: lnbu       # CLCDLNBUINTR
          - const: fuf        # CLCDFUFINTR

  interrupts:
    minItems: 1
    maxItems: 4

  clock-names:
    items:
      - const: clcdclk
      - const: apb_pclk

  clocks:
    items:
      - description: The CLCDCLK reference clock for the controller.
      - description: The HCLK AHB slave clock for the register access.

  memory-region:
    maxItems: 1
    description:
      Phandle to a node describing memory to be used for the framebuffer.
      If not present, the framebuffer may be located anywhere in memory.

  max-memory-bandwidth:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Maximum bandwidth in bytes per second that the cell's memory interface
      can handle.
      If not present, the memory interface is fast enough to handle all
      possible video modes.

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    additionalProperties: false

    description:
      Output endpoint of the controller, connecting the LCD panel signals.

    properties:
      endpoint:
        $ref: /schemas/graph.yaml#/$defs/endpoint-base
        unevaluatedProperties: false

        properties:
          arm,pl11x,tft-r0g0b0-pads:
            $ref: /schemas/types.yaml#/definitions/uint32-array
            items:
              - description: index of CLD pad used for first red bit (R0)
              - description: index of CLD pad used for first green bit (G0)
              - description: index of CLD pad used for first blue bit (G0)
            deprecated: true
            description: |
              DEPRECATED. An array of three 32-bit values, defining the way
              CLD[23:0] pads are wired up.
              The first value contains the index of the "CLD" external pin (pad)
              used as R0 (first bit of the red component), the second value for
              green, the third value for blue.
              See also "LCD panel signal multiplexing details" paragraphs in the
              PL110/PL111 Technical Reference Manuals.
              This implicitly defines available color modes, for example:
              - PL111 TFT 4:4:4 panel:
                  arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
              - PL110 TFT (1:)5:5:5 panel:
                  arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
              - PL111 TFT (1:)5:5:5 panel:
                  arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
              - PL111 TFT 5:6:5 panel:
                  arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
              - PL110 and PL111 TFT 8:8:8 panel:
                  arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
              - PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
                  arm,pl11x,tft-r0g0b0-pads = <16 8 0>;

additionalProperties: false

required:
  - compatible
  - reg
  - clock-names
  - clocks
  - port

allOf:
  - if:
      properties:
        interrupts:
          minItems: 2
      required:
        - interrupts
    then:
      required:
        - interrupt-names

examples:
  - |
    clcd@10020000 {
        compatible = "arm,pl111", "arm,primecell";
        reg = <0x10020000 0x1000>;
        interrupt-names = "combined";
        interrupts = <44>;
        clocks = <&oscclk1>, <&oscclk2>;
        clock-names = "clcdclk", "apb_pclk";
        max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */

        port {
            clcd_pads: endpoint {
                remote-endpoint = <&clcd_panel>;
            };
        };
    };

    panel {
        compatible = "arm,rtsm-display";

        port {
            clcd_panel: endpoint {
                remote-endpoint = <&clcd_pads>;
            };
        };
    };
...


code:
Device Tree bindings for Armada DRM CRTC driver

Required properties:
 - compatible: value should be "marvell,dove-lcd".
 - reg: base address and size of the LCD controller
 - interrupts: single interrupt number for the LCD controller
 - port: video output port with endpoints, as described by graph.txt

Optional properties:

 - clocks: as described by clock-bindings.txt
 - clock-names: as described by clock-bindings.txt
	"axiclk" - axi bus clock for pixel clock
	"plldivider" - pll divider clock for pixel clock
	"ext_ref_clk0" - external clock 0 for pixel clock
	"ext_ref_clk1" - external clock 1 for pixel clock

Note: all clocks are optional but at least one must be specified.
Further clocks may be added in the future according to requirements of
different SoCs.

Example:

	lcd0: lcd-controller@820000 {
		compatible = "marvell,dove-lcd";
		reg = <0x820000 0x1000>;
		interrupts = <47>;
		clocks = <&si5351 0>;
		clock-names = "ext_ref_clk_1";
	};


code:
Atmel LCDC Framebuffer
-----------------------------------------------------

Required properties:
- compatible :
	"atmel,at91sam9261-lcdc" ,
	"atmel,at91sam9263-lcdc" ,
	"atmel,at91sam9g10-lcdc" ,
	"atmel,at91sam9g45-lcdc" ,
	"atmel,at91sam9g45es-lcdc" ,
	"atmel,at91sam9rl-lcdc" ,
- reg : Should contain 1 register ranges(address and length).
	Can contain an additional register range(address and length)
	for fixed framebuffer memory. Useful for dedicated memories.
- interrupts : framebuffer controller interrupt
- display: a phandle pointing to the display node

Required nodes:
- display: a display node is required to initialize the lcd panel
	This should be in the board dts.
- default-mode: a videomode within the display with timing parameters
	as specified below.

Optional properties:
- lcd-supply: Regulator for LCD supply voltage.

Example:

	fb0: fb@00500000 {
		compatible = "atmel,at91sam9g45-lcdc";
		reg = <0x00500000 0x1000>;
		interrupts = <23 3 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_fb>;
		display = <&display0>;
		#address-cells = <1>;
		#size-cells = <1>;

	};

Example for fixed framebuffer memory:

	fb0: fb@00500000 {
		compatible = "atmel,at91sam9263-lcdc";
		reg = <0x00700000 0x1000 0x70000000 0x200000>;
		[...]
	};

Atmel LCDC Display
-----------------------------------------------------
Required properties (as per of_videomode_helper):

 - atmel,dmacon: dma controller configuration
 - atmel,lcdcon2: lcd controller configuration
 - atmel,guard-time: lcd guard time (Delay in frame periods)
 - bits-per-pixel: lcd panel bit-depth.

Optional properties (as per of_videomode_helper):
 - atmel,lcdcon-backlight: enable backlight
 - atmel,lcdcon-backlight-inverted: invert backlight PWM polarity
 - atmel,lcd-wiring-mode: lcd wiring mode "RGB" or "BRG"
 - atmel,power-control-gpio: gpio to power on or off the LCD (as many as needed)

Example:
	display0: display {
		bits-per-pixel = <32>;
		atmel,lcdcon-backlight;
		atmel,dmacon = <0x1>;
		atmel,lcdcon2 = <0x80008002>;
		atmel,guard-time = <9>;
		atmel,lcd-wiring-mode = <1>;

		display-timings {
			native-mode = <&timing0>;
			timing0: timing0 {
				clock-frequency = <9000000>;
				hactive = <480>;
				vactive = <272>;
				hback-porch = <1>;
				hfront-porch = <1>;
				vback-porch = <40>;
				vfront-porch = <1>;
				hsync-len = <45>;
				vsync-len = <1>;
			};
		};
	};


code:
Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver

The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device.
See ../../mfd/atmel-hlcdc.txt for more details.

Required properties:
 - compatible: value should be "atmel,hlcdc-display-controller"
 - pinctrl-names: the pin control state names. Should contain "default".
 - pinctrl-0: should contain the default pinctrl states.
 - #address-cells: should be set to 1.
 - #size-cells: should be set to 0.

Required children nodes:
 Children nodes are encoding available output ports and their connections
 to external devices using the OF graph reprensentation (see ../graph.txt).
 At least one port node is required.

Optional properties in grandchild nodes:
 Any endpoint grandchild node may specify a desired video interface
 according to ../../media/video-interfaces.txt, specifically
 - bus-width: recognized values are <12>, <16>, <18> and <24>, and
   override any output mode selection heuristic, forcing "rgb444",
   "rgb565", "rgb666" and "rgb888" respectively.

Example:

	hlcdc: hlcdc@f0030000 {
		compatible = "atmel,sama5d3-hlcdc";
		reg = <0xf0030000 0x2000>;
		interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
		clock-names = "periph_clk","sys_clk", "slow_clk";

		hlcdc-display-controller {
			compatible = "atmel,hlcdc-display-controller";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;

				hlcdc_panel_output: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&panel_input>;
				};
			};
		};

		hlcdc_pwm: hlcdc-pwm {
			compatible = "atmel,hlcdc-pwm";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_lcd_pwm>;
			#pwm-cells = <3>;
		};
	};

Example 2: With a video interface override to force rgb565; as above
but with these changes/additions:

	&hlcdc {
		hlcdc-display-controller {
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>;

			port@0 {
				hlcdc_panel_output: endpoint@0 {
					bus-width = <16>;
				};
			};
		};
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/brcm,bcm2711-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM2711 HDMI Controller

maintainers:
  - Eric Anholt <eric@anholt.net>

properties:
  compatible:
    enum:
      - brcm,bcm2711-hdmi0
      - brcm,bcm2711-hdmi1

  reg:
    items:
      - description: HDMI controller register range
      - description: DVP register range
      - description: HDMI PHY register range
      - description: Rate Manager register range
      - description: Packet RAM register range
      - description: Metadata RAM register range
      - description: CSC register range
      - description: CEC register range
      - description: HD register range

  reg-names:
    items:
      - const: hdmi
      - const: dvp
      - const: phy
      - const: rm
      - const: packet
      - const: metadata
      - const: csc
      - const: cec
      - const: hd

  clocks:
    items:
      - description: The HDMI state machine clock
      - description: The Pixel BVB clock
      - description: The HDMI Audio parent clock
      - description: The HDMI CEC parent clock

  clock-names:
    items:
      - const: hdmi
      - const: bvb
      - const: audio
      - const: cec

  interrupts:
    items:
      - description: CEC TX interrupt
      - description: CEC RX interrupt
      - description: CEC stuck at low interrupt
      - description: Wake-up interrupt
      - description: Hotplug connected interrupt
      - description: Hotplug removed interrupt

  interrupt-names:
    items:
      - const: cec-tx
      - const: cec-rx
      - const: cec-low
      - const: wakeup
      - const: hpd-connected
      - const: hpd-removed

  ddc:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: >
      Phandle of the I2C controller used for DDC EDID probing

  hpd-gpios:
    maxItems: 1
    description: >
      The GPIO pin for the HDMI hotplug detect (if it doesn't appear
      as an interrupt/status bit in the HDMI controller itself)

  dmas:
    maxItems: 1
    description: >
      Should contain one entry pointing to the DMA channel used to
      transfer audio data.

  dma-names:
    const: audio-rx

  resets:
    maxItems: 1

  wifi-2.4ghz-coexistence:
    type: boolean
    description: >
      Should the pixel frequencies in the WiFi frequencies range be
      avoided?

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - resets
  - ddc

additionalProperties: false

examples:
  - |
    hdmi0: hdmi@7ef00700 {
        compatible = "brcm,bcm2711-hdmi0";
        reg = <0x7ef00700 0x300>,
              <0x7ef00300 0x200>,
              <0x7ef00f00 0x80>,
              <0x7ef00f80 0x80>,
              <0x7ef01b00 0x200>,
              <0x7ef01f00 0x400>,
              <0x7ef00200 0x80>,
              <0x7ef04300 0x100>,
              <0x7ef20000 0x100>;
        reg-names = "hdmi",
                    "dvp",
                    "phy",
                    "rm",
                    "packet",
                    "metadata",
                    "csc",
                    "cec",
                    "hd";
        clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
        clock-names = "hdmi", "bvb", "audio", "cec";
        resets = <&dvp 0>;
        ddc = <&ddc0>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/brcm,bcm2835-dpi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom VC4 (VideoCore4) DPI Controller

maintainers:
  - Eric Anholt <eric@anholt.net>

properties:
  compatible:
    const: brcm,bcm2835-dpi

  reg:
    maxItems: 1

  clocks:
    items:
      - description: The core clock the unit runs on
      - description: The pixel clock that feeds the pixelvalve

  clock-names:
    items:
      - const: core
      - const: pixel

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      Port node with a single endpoint connecting to the panel.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/bcm2835.h>

    dpi: dpi@7e208000 {
        compatible = "brcm,bcm2835-dpi";
        reg = <0x7e208000 0x8c>;
        clocks = <&clocks BCM2835_CLOCK_VPU>,
                 <&clocks BCM2835_CLOCK_DPI>;
        clock-names = "core", "pixel";

        port {
            dpi_out: endpoint {
                remote-endpoint = <&panel_in>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/brcm,bcm2835-dsi0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom VC4 (VideoCore4) DSI Controller

maintainers:
  - Eric Anholt <eric@anholt.net>

allOf:
  - $ref: dsi-controller.yaml#

properties:
  "#clock-cells":
    const: 1

  compatible:
    enum:
      - brcm,bcm2711-dsi1
      - brcm,bcm2835-dsi0
      - brcm,bcm2835-dsi1

  reg:
    maxItems: 1

  clocks:
    items:
      - description: The DSI PLL clock feeding the DSI analog PHY
      - description: The DSI ESC clock
      - description: The DSI pixel clock

  clock-names:
    items:
      - const: phy
      - const: escape
      - const: pixel

  clock-output-names: true
    # FIXME: The meta-schemas don't seem to allow it for now
    # items:
    #   - description: The DSI byte clock for the PHY
    #   - description: The DSI DDR2 clock
    #   - description: The DSI DDR clock

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - "#clock-cells"
  - compatible
  - reg
  - clocks
  - clock-names
  - clock-output-names
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/bcm2835.h>

    dsi1: dsi@7e700000 {
        compatible = "brcm,bcm2835-dsi1";
        reg = <0x7e700000 0x8c>;
        interrupts = <2 12>;
        #address-cells = <1>;
        #size-cells = <0>;
        #clock-cells = <1>;

        clocks = <&clocks BCM2835_PLLD_DSI1>,
                 <&clocks BCM2835_CLOCK_DSI1E>,
                 <&clocks BCM2835_CLOCK_DSI1P>;
        clock-names = "phy", "escape", "pixel";

        clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr";

    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/brcm,bcm2835-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom VC4 (VideoCore4) HDMI Controller

maintainers:
  - Eric Anholt <eric@anholt.net>

properties:
  compatible:
    const: brcm,bcm2835-hdmi

  reg:
    items:
      - description: HDMI register range
      - description: HD register range

  interrupts:
    minItems: 2

  clocks:
    items:
      - description: The pixel clock
      - description: The HDMI state machine clock

  clock-names:
    items:
      - const: pixel
      - const: hdmi

  ddc:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: >
      Phandle of the I2C controller used for DDC EDID probing

  hpd-gpios:
    maxItems: 1
    description: >
      The GPIO pin for the HDMI hotplug detect (if it doesn't appear
      as an interrupt/status bit in the HDMI controller itself)

  dmas:
    maxItems: 1
    description: >
      Should contain one entry pointing to the DMA channel used to
      transfer audio data.

  dma-names:
    const: audio-rx

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - ddc

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/bcm2835.h>
    #include <dt-bindings/gpio/gpio.h>

    hdmi: hdmi@7e902000 {
        compatible = "brcm,bcm2835-hdmi";
        reg = <0x7e902000 0x600>,
              <0x7e808000 0x100>;
        interrupts = <2 8>, <2 9>;
        ddc = <&i2c2>;
        hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
        clocks = <&clocks BCM2835_PLLH_PIX>,
                 <&clocks BCM2835_CLOCK_HSM>;
        clock-names = "pixel", "hdmi";
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/brcm,bcm2835-hvs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom VC4 (VideoCore4) Hardware Video Scaler

maintainers:
  - Eric Anholt <eric@anholt.net>

properties:
  compatible:
    enum:
      - brcm,bcm2711-hvs
      - brcm,bcm2835-hvs

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1
    description: Core Clock

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

if:
  properties:
    compatible:
      contains:
        const: brcm,bcm2711-hvs

then:
  required:
    - clocks

examples:
  - |
    hvs@7e400000 {
        compatible = "brcm,bcm2835-hvs";
        reg = <0x7e400000 0x6000>;
        interrupts = <2 1>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/brcm,bcm2835-pixelvalve0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom VC4 (VideoCore4) PixelValve

maintainers:
  - Eric Anholt <eric@anholt.net>

properties:
  compatible:
    enum:
      - brcm,bcm2835-pixelvalve0
      - brcm,bcm2835-pixelvalve1
      - brcm,bcm2835-pixelvalve2
      - brcm,bcm2711-pixelvalve0
      - brcm,bcm2711-pixelvalve1
      - brcm,bcm2711-pixelvalve2
      - brcm,bcm2711-pixelvalve3
      - brcm,bcm2711-pixelvalve4

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    pixelvalve@7e807000 {
        compatible = "brcm,bcm2835-pixelvalve2";
        reg = <0x7e807000 0x100>;
        interrupts = <2 10>; /* pixelvalve */
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/brcm,bcm2835-txp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom VC4 (VideoCore4) TXP (writeback) Controller

maintainers:
  - Eric Anholt <eric@anholt.net>

properties:
  compatible:
    const: brcm,bcm2835-txp

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    txp: txp@7e004000 {
        compatible = "brcm,bcm2835-txp";
        reg = <0x7e004000 0x20>;
        interrupts = <1 11>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/brcm,bcm2835-v3d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom VC4 (VideoCore4) V3D GPU

maintainers:
  - Eric Anholt <eric@anholt.net>

properties:
  compatible:
    enum:
      - brcm,bcm2835-v3d
      - brcm,cygnus-v3d

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    v3d: v3d@7ec00000 {
        compatible = "brcm,bcm2835-v3d";
        reg = <0x7ec00000 0x1000>;
        interrupts = <1 10>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/brcm,bcm2835-vc4.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom VC4 (VideoCore4) GPU

maintainers:
  - Eric Anholt <eric@anholt.net>

description: >
  The VC4 device present on the Raspberry Pi includes a display system
  with HDMI output and the HVS (Hardware Video Scaler) for compositing
  display planes.

properties:
  compatible:
    enum:
      - brcm,bcm2711-vc5
      - brcm,bcm2835-vc4
      - brcm,cygnus-vc4

required:
  - compatible

additionalProperties: false

examples:
  - |
    vc4: gpu {
        compatible = "brcm,bcm2835-vc4";
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/brcm,bcm2835-vec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom VC4 (VideoCore4) VEC

maintainers:
  - Eric Anholt <eric@anholt.net>

properties:
  compatible:
    enum:
      - brcm,bcm2711-vec
      - brcm,bcm2835-vec

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/bcm2835.h>

    vec: vec@7e806000 {
        compatible = "brcm,bcm2835-vec";
        reg = <0x7e806000 0x1000>;
        clocks = <&clocks BCM2835_CLOCK_VEC>;
        interrupts = <2 27>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/adi,adv7511.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices ADV7511/11W/13 HDMI Encoders

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description: |
  The ADV7511, ADV7511W and ADV7513 are HDMI audio and video
  transmitters compatible with HDMI 1.4 and DVI 1.0. They support color
  space conversion, S/PDIF, CEC and HDCP. The transmitter input is
  parallel RGB or YUV data.

properties:
  compatible:
    enum:
      - adi,adv7511
      - adi,adv7511w
      - adi,adv7513

  reg:
    description: |
      I2C slave addresses.

      The ADV7511/11W/13 internal registers are split into four pages
      exposed through different I2C addresses, creating four register
      maps. Each map has it own I2C address and acts as a standard slave
      device on the I2C bus. The main address is mandatory, others are
      optional and revert to defaults if not specified.
    minItems: 1
    maxItems: 4

  reg-names:
    description:
      Names of maps with programmable addresses. It can contain any map
      needing a non-default address.
    minItems: 1
    items:
      - const: main
      - const: edid
      - const: cec
      - const: packet

  clocks:
    description: Reference to the CEC clock.
    maxItems: 1

  clock-names:
    const: cec

  interrupts:
    maxItems: 1

  pd-gpios:
    description: GPIO connected to the power down signal.
    maxItems: 1

  avdd-supply:
    description: A 1.8V supply that powers up the AVDD pin.

  dvdd-supply:
    description: A 1.8V supply that powers up the DVDD pin.

  pvdd-supply:
    description: A 1.8V supply that powers up the PVDD pin.

  dvdd-3v-supply:
    description: A 3.3V supply that powers up the DVDD_3V pin.

  bgvdd-supply:
    description: A 1.8V supply that powers up the BGVDD pin.

  adi,input-depth:
    description: Number of bits per color component at the input.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 8, 10, 12 ]

  adi,input-colorspace:
    description: Input color space.
    enum: [ rgb, yuv422, yuv444 ]

  adi,input-clock:
    description: |
      Input clock type.
        "1x": one clock cycle per pixel
        "2x": two clock cycles per pixel
        "dd": one clock cycle per pixel, data driven on both edges
    enum: [ 1x, 2x, dd ]

  adi,clock-delay:
    description:
      Video data clock delay relative to the pixel clock, in ps
      (-1200ps .. 1600 ps).
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

  adi,embedded-sync:
    description:
      If defined, the input uses synchronization signals embedded in the
      data stream (similar to BT.656).
    type: boolean

  adi,input-style:
    description:
      Input components arrangement variant as listed in the input
      format tables in the datasheet.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 1, 2, 3 ]

  adi,input-justification:
    description: Input bit justification.
    enum: [ left, evenly, right ]

  ports:
    description:
      The ADV7511(W)/13 has two video ports and one audio port.
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        description: Video port for the RGB or YUV input.
        $ref: /schemas/graph.yaml#/properties/port

      port@1:
        description: Video port for the HDMI output.
        $ref: /schemas/graph.yaml#/properties/port

      port@2:
        description: Audio port for the HDMI output.
        $ref: /schemas/graph.yaml#/properties/port

# adi,input-colorspace and adi,input-clock are required except in
# "rgb 1x" and "yuv444 1x" modes, in which case they must not be
# specified.
if:
  not:
    properties:
      adi,input-colorspace:
        contains:
          enum: [ rgb, yuv444 ]
      adi,input-clock:
        contains:
          const: 1x

then:
  required:
    - adi,input-style
    - adi,input-justification

else:
  properties:
    adi,input-style: false
    adi,input-justification: false

required:
  - compatible
  - reg
  - ports
  - adi,input-depth
  - adi,input-colorspace
  - adi,input-clock
  - avdd-supply
  - dvdd-supply
  - pvdd-supply
  - dvdd-3v-supply
  - bgvdd-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c@e6500000 {
        #address-cells = <1>;
        #size-cells = <0>;

        reg = <0 0xe6500000>;

        adv7511w: hdmi@39 {
            compatible = "adi,adv7511w";
            /*
             * The EDID page will be accessible on address 0x66 on the I2C
             * bus. All other maps continue to use their default addresses.
             */
            reg = <0x39>, <0x66>;
            reg-names = "main", "edid";
            interrupt-parent = <&gpio3>;
            interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
            clocks = <&cec_clock>;
            clock-names = "cec";
            avdd-supply = <&v1v8>;
            dvdd-supply = <&v1v8>;
            pvdd-supply = <&v1v8>;
            dvdd-3v-supply = <&v3v3>;
            bgvdd-supply = <&v1v8>;

            adi,input-depth = <8>;
            adi,input-colorspace = "yuv422";
            adi,input-clock = "1x";

            adi,input-style = <3>;
            adi,input-justification = "right";
            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    adv7511w_in: endpoint {
                        remote-endpoint = <&dpi_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    adv7511_out: endpoint {
                        remote-endpoint = <&hdmi_connector_in>;
                    };
                };

                port@2 {
                    reg = <2>;
                    codec_endpoint: endpoint {
                        remote-endpoint = <&i2s0_cpu_endpoint>;
                    };
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/adi,adv7533.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices ADV7533/35 HDMI Encoders

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description: |
  The ADV7533 and ADV7535 are HDMI audio and video transmitters
  compatible with HDMI 1.4 and DVI 1.0. They support color space
  conversion, S/PDIF, CEC and HDCP. The transmitter input is MIPI DSI.

properties:
  compatible:
    enum:
      - adi,adv7533
      - adi,adv7535

  reg:
    description: |
      I2C slave addresses.

      The ADV7533/35 internal registers are split into four pages
      exposed through different I2C addresses, creating four register
      maps. Each map has it own I2C address and acts as a standard slave
      device on the I2C bus. The main address is mandatory, others are
      optional and revert to defaults if not specified.
    minItems: 1
    maxItems: 4

  reg-names:
    description:
      Names of maps with programmable addresses. It can contain any map
      needing a non-default address.
    minItems: 1
    items:
      - const: main
      - const: edid
      - const: cec
      - const: packet

  clocks:
    description: Reference to the CEC clock.
    maxItems: 1

  clock-names:
    const: cec

  interrupts:
    maxItems: 1

  pd-gpios:
    description: GPIO connected to the power down signal.
    maxItems: 1

  avdd-supply:
    description: A 1.8V supply that powers up the AVDD pin.

  dvdd-supply:
    description: A 1.8V supply that powers up the DVDD pin.

  pvdd-supply:
    description: A 1.8V supply that powers up the PVDD pin.

  a2vdd-supply:
    description: A 1.8V supply that powers up the A2VDD pin.

  v3p3-supply:
    description: A 3.3V supply that powers up the V3P3 pin.

  v1p2-supply:
    description:
      A supply that powers up the V1P2 pin. It can be either 1.2V
      or 1.8V for ADV7533 but only 1.8V for ADV7535.

  adi,disable-timing-generator:
    description:
      Disables the internal timing generator. The chip will rely on the
      sync signals in the DSI data lanes, rather than generating its own
      timings for HDMI output.
    type: boolean

  adi,dsi-lanes:
    description: Number of DSI data lanes connected to the DSI host.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 1, 2, 3, 4 ]

  ports:
    description:
      The ADV7533/35 has two video ports and one audio port.
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        description:
          Video port for the DSI input. The remote endpoint phandle
          should be a reference to a valid mipi_dsi_host_device.
        $ref: /schemas/graph.yaml#/properties/port

      port@1:
        description: Video port for the HDMI output.
        $ref: /schemas/graph.yaml#/properties/port

      port@2:
        description: Audio port for the HDMI output.
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - ports
  - adi,dsi-lanes
  - avdd-supply
  - dvdd-supply
  - pvdd-supply
  - a2vdd-supply
  - v3p3-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c@e6500000 {
        #address-cells = <1>;
        #size-cells = <0>;

        reg = <0 0xe6500000>;

        adv7533: hdmi@39 {
            compatible = "adi,adv7533";
            /*
             * The EDID page will be accessible on address 0x66 on the I2C
             * bus. All other maps continue to use their default addresses.
             */
            reg = <0x39>, <0x66>;
            reg-names = "main", "edid";
            interrupt-parent = <&gpio3>;
            interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
            clocks = <&cec_clock>;
            clock-names = "cec";
            adi,dsi-lanes = <4>;
            avdd-supply = <&v1v8>;
            dvdd-supply = <&v1v8>;
            pvdd-supply = <&v1v8>;
            a2vdd-supply = <&v1v8>;
            v3p3-supply = <&v3v3>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    adv7533_in: endpoint {
                        remote-endpoint = <&dsi_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    adv7533_out: endpoint {
                        remote-endpoint = <&hdmi_connector_in>;
                    };
                };

                port@2 {
                    reg = <2>;
                    codec_endpoint: endpoint {
                        remote-endpoint = <&i2s0_cpu_endpoint>;
                    };
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Analogix Semiconductor, Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/bridge/analogix,anx7625.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Analogix ANX7625 SlimPort (4K Mobile HD Transmitter)

maintainers:
  - Xin Ji <xji@analogixsemi.com>

description: |
  The ANX7625 is an ultra-low power 4K Mobile HD Transmitter
  designed for portable devices.

properties:
  compatible:
    items:
      - const: analogix,anx7625

  reg:
    maxItems: 1

  interrupts:
    description: used for interrupt pin B8.
    maxItems: 1

  enable-gpios:
    description: used for power on chip control, POWER_EN pin D2.
    maxItems: 1

  reset-gpios:
    description: used for reset chip control, RESET_N pin B7.
    maxItems: 1

  vdd10-supply:
    description: Regulator that provides the supply 1.0V power.

  vdd18-supply:
    description: Regulator that provides the supply 1.8V power.

  vdd33-supply:
    description: Regulator that provides the supply 3.3V power.

  analogix,lane0-swing:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    minItems: 1
    maxItems: 20
    description:
      an array of swing register setting for DP tx lane0 PHY.
      Registers 0~9 are Swing0_Pre0, Swing1_Pre0, Swing2_Pre0,
      Swing3_Pre0, Swing0_Pre1, Swing1_Pre1, Swing2_Pre1, Swing0_Pre2,
      Swing1_Pre2, Swing0_Pre3, they are for [Boost control] and
      [Swing control] setting.
      Registers 0~9, bit 3:0 is [Boost control], these bits control
      post cursor manual, increase the [Boost control] to increase
      Pre-emphasis value.
      Registers 0~9, bit 6:4 is [Swing control], these bits control
      swing manual, increase [Swing control] setting to add Vp-p value
      for each Swing, Pre.
      Registers 10~19 are Swing0_Pre0, Swing1_Pre0, Swing2_Pre0,
      Swing3_Pre0, Swing0_Pre1, Swing1_Pre1, Swing2_Pre1, Swing0_Pre2,
      Swing1_Pre2, Swing0_Pre3, they are for [R select control] and
      [R Termination control] setting.
      Registers 10~19, bit 4:0 is [R select control], these bits are
      compensation manual, increase it can enhance IO driven strength
      and Vp-p.
      Registers 10~19, bit 5:6 is [R termination control], these bits
      adjust 50ohm impedance of DP tx termination. 00:55 ohm,
      01:50 ohm(default), 10:45 ohm, 11:40 ohm.

  analogix,lane1-swing:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    minItems: 1
    maxItems: 20
    description:
      an array of swing register setting for DP tx lane1 PHY.
      DP TX lane1 swing register setting same with lane0
      swing, please refer lane0-swing property description.

  analogix,audio-enable:
    type: boolean
    description: let the driver enable audio HDMI codec function or not.

  aux-bus:
    $ref: /schemas/display/dp-aux-bus.yaml#

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          MIPI DSI/DPI input.

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            type: object
            additionalProperties: false

            properties:
              remote-endpoint: true

              bus-type:
                enum: [7]
                default: 1

              data-lanes: true

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for panel or connector.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - vdd10-supply
  - vdd18-supply
  - vdd33-supply
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        encoder@58 {
            compatible = "analogix,anx7625";
            reg = <0x58>;
            enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
            reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
            vdd10-supply = <&pp1000_mipibrdg>;
            vdd18-supply = <&pp1800_mipibrdg>;
            vdd33-supply = <&pp3300_mipibrdg>;
            analogix,audio-enable;
            analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
            analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                mipi2dp_bridge_in: port@0 {
                    reg = <0>;
                    anx7625_in: endpoint {
                        remote-endpoint = <&mipi_dsi>;
                        bus-type = <7>;
                        data-lanes = <0 1 2 3>;
                    };
                };

                mipi2dp_bridge_out: port@1 {
                    reg = <1>;
                    anx7625_out: endpoint {
                        remote-endpoint = <&panel_in>;
                    };
                };
            };

            aux-bus {
                panel {
                    compatible = "innolux,n125hce-gn1";
                    power-supply = <&pp3300_disp_x>;
                    backlight = <&backlight_lcd0>;

                    port {
                        panel_in: endpoint {
                            remote-endpoint = <&anx7625_out>;
                        };
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/analogix,anx7814.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analogix ANX7814 SlimPort (Full-HD Transmitter)

maintainers:
  - Andrzej Hajda <andrzej.hajda@intel.com>
  - Neil Armstrong <neil.armstrong@linaro.org>
  - Robert Foss <robert.foss@linaro.org>

properties:
  compatible:
    enum:
      - analogix,anx7808
      - analogix,anx7812
      - analogix,anx7814
      - analogix,anx7818

  reg:
    maxItems: 1
    description: I2C address of the device.

  interrupts:
    maxItems: 1
    description: Should contain the INTP interrupt.

  hpd-gpios:
    deprecated: true
    maxItems: 1
    description: Which GPIO to use for hpd.

  pd-gpios:
    maxItems: 1
    description: Which GPIO to use for power down.

  reset-gpios:
    maxItems: 1
    description: Which GPIO to use for reset.

  dvdd10-supply:
    description: Regulator for 1.0V digital core power.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Video port for HDMI input.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for SlimPort, DisplayPort, eDP or MyDP output.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/gpio/gpio.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        anx7814: bridge@38 {
            compatible = "analogix,anx7814";
            reg = <0x38>;
            interrupt-parent = <&gpio0>;
            interrupts = <99 IRQ_TYPE_LEVEL_LOW>;   /* INTP */
            pd-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
            reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    anx7814_in: endpoint {
                        remote-endpoint = <&hdmi0_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    anx7814_out: endpoint {
                        remote-endpoint = <&edp_out>;
                    };
                };
            };
        };
    };

...


code:
Analogix Display Port bridge bindings

Required properties for dp-controller:
	-compatible:
		platform specific such as:
		 * "samsung,exynos5-dp"
		 * "rockchip,rk3288-dp"
		 * "rockchip,rk3399-edp"
	-reg:
		physical base address of the controller and length
		of memory mapped region.
	-interrupts:
		interrupt combiner values.
	-clocks:
		from common clock binding: handle to dp clock.
	-clock-names:
		from common clock binding: Shall be "dp".
	-phys:
		from general PHY binding: the phandle for the PHY device.
	-phy-names:
		from general PHY binding: Should be "dp".

Optional properties for dp-controller:
	-force-hpd:
		Indicate driver need force hpd when hpd detect failed, this
		is used for some eDP screen which don't have hpd signal.
	-hpd-gpios:
		Hotplug detect GPIO.
		Indicates which GPIO should be used for hotplug detection
	-port@[X]: SoC specific port nodes with endpoint definitions as defined
		in Documentation/devicetree/bindings/media/video-interfaces.txt,
		please refer to the SoC specific binding document:
		* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
		* Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt

[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
-------------------------------------------------------------------------------

Example:

	dp-controller {
		compatible = "samsung,exynos5-dp";
		reg = <0x145b0000 0x10000>;
		interrupts = <10 3>;
		interrupt-parent = <&combiner>;
		clocks = <&clock 342>;
		clock-names = "dp";

		phys = <&dp_phy>;
		phy-names = "dp";
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/anx6345.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analogix ANX6345 eDP Transmitter Device Tree Bindings

maintainers:
  - Torsten Duwe <duwe@lst.de>

description: |
  The ANX6345 is an ultra-low power Full-HD eDP transmitter designed for
  portable devices.

properties:
  compatible:
    const: analogix,anx6345

  reg:
    maxItems: 1
    description: base I2C address of the device

  reset-gpios:
    maxItems: 1
    description: GPIO connected to active low reset

  dvdd12-supply:
    description: Regulator for 1.2V digital core power.

  dvdd25-supply:
    description: Regulator for 2.5V digital core power.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for LVTTL input

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for eDP output (panel or connector).
          May be omitted if EDID works reliably.

    required:
      - port@0

required:
  - compatible
  - reg
  - reset-gpios
  - dvdd12-supply
  - dvdd25-supply
  - ports

additionalProperties: false

examples:
  - |
    i2c0 {
      #address-cells = <1>;
      #size-cells = <0>;

      anx6345: anx6345@38 {
        compatible = "analogix,anx6345";
        reg = <0x38>;
        reset-gpios = <&pio42 1 /* GPIO_ACTIVE_LOW */>;
        dvdd25-supply = <&reg_dldo2>;
        dvdd12-supply = <&reg_fldo1>;

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          anx6345_in: port@0 {
            reg = <0>;
            anx6345_in_tcon0: endpoint {
              remote-endpoint = <&tcon0_out_anx6345>;
            };
          };

          anx6345_out: port@1 {
            reg = <1>;
            anx6345_out_panel: endpoint {
              remote-endpoint = <&panel_in_edp>;
            };
          };
        };
      };
    };


code:
Cadence DSI bridge
==================

The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.

Required properties:
- compatible: should be set to "cdns,dsi".
- reg: physical base address and length of the controller's registers.
- interrupts: interrupt line connected to the DSI bridge.
- clocks: DSI bridge clocks.
- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
- phys: phandle link to the MIPI D-PHY controller.
- phy-names: must contain "dphy".
- #address-cells: must be set to 1.
- #size-cells: must be set to 0.

Optional properties:
- resets: DSI reset lines.
- reset-names: can contain "dsi_p_rst".

Required subnodes:
- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
  2 ports are available:
  * port 0: this port is only needed if some of your DSI devices are
	    controlled through  an external bus like I2C or SPI. Can have at
	    most 4 endpoints. The endpoint number is directly encoding the
	    DSI virtual channel used by this device.
  * port 1: represents the DPI input.
  Other ports will be added later to support the new kind of inputs.

- one subnode per DSI device connected on the DSI bus. Each DSI device should
  contain a reg property encoding its virtual channel.

Example:
	dsi0: dsi@fd0c0000 {
		compatible = "cdns,dsi";
		reg = <0x0 0xfd0c0000 0x0 0x1000>;
		clocks = <&pclk>, <&sysclk>;
		clock-names = "dsi_p_clk", "dsi_sys_clk";
		interrupts = <1>;
		phys = <&dphy0>;
		phy-names = "dphy";
		#address-cells = <1>;
		#size-cells = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <1>;
				dsi0_dpi_input: endpoint {
					remote-endpoint = <&xxx_dpi_output>;
				};
			};
		};

		panel: dsi-dev@0 {
			compatible = "<vendor,panel>";
			reg = <0>;
		};
	};

or

	dsi0: dsi@fd0c0000 {
		compatible = "cdns,dsi";
		reg = <0x0 0xfd0c0000 0x0 0x1000>;
		clocks = <&pclk>, <&sysclk>;
		clock-names = "dsi_p_clk", "dsi_sys_clk";
		interrupts = <1>;
		phys = <&dphy1>;
		phy-names = "dphy";
		#address-cells = <1>;
		#size-cells = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;

				dsi0_output: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&dsi_panel_input>;
				};
			};

			port@1 {
				reg = <1>;
				dsi0_dpi_input: endpoint {
					remote-endpoint = <&xxx_dpi_output>;
				};
			};
		};
	};

	i2c@xxx {
		panel: panel@59 {
			compatible = "<vendor,panel>";
			reg = <0x59>;

			port {
				dsi_panel_input: endpoint {
					remote-endpoint = <&dsi0_output>;
				};
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence MHDP8546 bridge

maintainers:
  - Swapnil Jakhade <sjakhade@cadence.com>
  - Yuti Amonkar <yamonkar@cadence.com>

properties:
  compatible:
    enum:
      - cdns,mhdp8546
      - ti,j721e-mhdp8546

  reg:
    minItems: 1
    items:
      - description:
          Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
          The AUX and PMA registers are not part of this range, they are instead
          included in the associated PHY.
      - description:
          Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
      - description:
          Register block of mhdptx sapb registers.

  reg-names:
    minItems: 1
    items:
      - const: mhdptx
      - const: j721e-intg
      - const: mhdptx-sapb

  clocks:
    maxItems: 1
    description:
      DP bridge clock, used by the IP to know how to translate a number of
      clock cycles into a time (which is used to comply with DP standard timings
      and delays).

  phys:
    maxItems: 1
    description:
      phandle to the DisplayPort PHY.

  phy-names:
    items:
      - const: dpphy

  power-domains:
    maxItems: 1

  interrupts:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          First input port representing the DP bridge input.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Second input port representing the DP bridge input.

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Third input port representing the DP bridge input.

      port@3:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Fourth input port representing the DP bridge input.

      port@4:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Output port representing the DP bridge output.

    required:
      - port@0
      - port@4

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: ti,j721e-mhdp8546
    then:
      properties:
        reg:
          minItems: 2
          maxItems: 3
        reg-names:
          minItems: 2
          maxItems: 3
    else:
      properties:
        reg:
          minItems: 1
          maxItems: 2
        reg-names:
          minItems: 1
          maxItems: 2

required:
  - compatible
  - clocks
  - reg
  - reg-names
  - phys
  - phy-names
  - interrupts
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        mhdp: dp-bridge@f0fb000000 {
            compatible = "cdns,mhdp8546";
            reg = <0xf0 0xfb000000 0x0 0x1000000>;
            reg-names = "mhdptx";
            clocks = <&mhdp_clock>;
            phys = <&dp_phy>;
            phy-names = "dpphy";
            interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dp_bridge_input: endpoint {
                        remote-endpoint = <&xxx_dpi_output>;
                    };
                };

                port@4 {
                    reg = <4>;
                    dp_bridge_output: endpoint {
                        remote-endpoint = <&xxx_dp_connector_input>;
                    };
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge

maintainers:
  - Jagan Teki <jagan@amarulasolutions.com>

description: |
  ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.

  It has a flexible configuration of MIPI DSI signal input and
  produce RGB565, RGB666, RGB888 output format.

properties:
  compatible:
    enum:
      - chipone,icn6211

  reg:
    maxItems: 1
    description: virtual channel number of a DSI peripheral

  clock-names:
    const: refclk

  clocks:
    maxItems: 1
    description: |
        Optional external clock connected to REF_CLK input.
        The clock rate must be in 10..154 MHz range.

  enable-gpios:
    description: Bridge EN pin, chip is reset when EN is low.

  vdd1-supply:
    description: A 1.8V/2.5V/3.3V supply that power the MIPI RX.

  vdd2-supply:
    description: A 1.8V/2.5V/3.3V supply that power the PLL.

  vdd3-supply:
    description: A 1.8V/2.5V/3.3V supply that power the RGB output.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Video port for MIPI DSI input

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description: array of physical DSI data lane indexes.
                minItems: 1
                items:
                  - const: 1
                  - const: 2
                  - const: 3
                  - const: 4

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for MIPI DPI output (panel or connector).

    required:
      - port@1

required:
  - compatible
  - reg
  - enable-gpios
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    dsi {
      #address-cells = <1>;
      #size-cells = <0>;

      bridge@0 {
        compatible = "chipone,icn6211";
        reg = <0>;
        enable-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* LCD-RST: PL5 */

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;

            bridge_in_dsi: endpoint {
              remote-endpoint = <&dsi_out_bridge>;
            };
          };

          port@1 {
            reg = <1>;

            bridge_out_panel: endpoint {
              remote-endpoint = <&panel_out_bridge>;
            };
          };
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2019,2020 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/chrontel,ch7033.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Chrontel CH7033 Video Encoder Device Tree Bindings

maintainers:
  - Lubomir Rintel <lkundrak@v3.sk>

properties:
  compatible:
    const: chrontel,ch7033

  reg:
    maxItems: 1
    description: I2C address of the device

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Video port for RGB input.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          DVI port, should be connected to a node compatible with the
          dvi-connector binding.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - ports

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        vga-dvi-encoder@76 {
            compatible = "chrontel,ch7033";
            reg = <0x76>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    endpoint {
                        remote-endpoint = <&lcd0_rgb_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    endpoint {
                        remote-endpoint = <&dvi_in>;
                    };
                };

            };
        };
    };