code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2019-2021 TQ-Systems GmbH
 */

/dts-v1/;

#include "imx8mq-tqma8mq.dtsi"
#include "mba8mx.dtsi"

/ {
	model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx";
	compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";

	aliases {
		eeprom0 = &eeprom3;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		rtc0 = &pcf85063;
		rtc1 = &snvs_rtc;
	};

	extcon_usbotg: extcon-usbotg0 {
		compatible = "linux,extcon-usb-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbcon0>;
		id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pcie1_refclk: pcie1-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	reg_otg_vbus: regulator-otg-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_regotgvbus>;
		regulator-name = "MBA8MQ_OTG_VBUS";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usdhc2_vmmc: regulator-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&btn2 {
	gpios = <&gpio3 17 GPIO_ACTIVE_LOW>;
};

&gpio_leds {
	led3 {
		label = "led3";
		gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
	};
};

&i2c1 {
	expander2: gpio@25 {
		compatible = "nxp,pca9555";
		reg = <0x25>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&reg_vcc_3v3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_expander>;
		interrupt-parent = <&gpio1>;
		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;

		mpcie-rst-hog {
			gpio-hog;
			gpios = <13 0>;
			output-high;
			line-name = "MPCIE_RST#";
		};
	};
};

&irqsteer {
	status = "okay";
};

&led2 {
	gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
};

&pcie0 {
	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	epdev_on-supply = <&reg_vcc_3v3>;
	hard-wired = <1>;
	status = "okay";
};

/*
 * miniPCIe, also usable for cards with USB. Therefore configure the reset as
 * static gpio hog.
 */
&pcie1 {
	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
		 <&pcie1_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	epdev_on-supply = <&reg_vcc_3v3>;
	hard-wired = <1>;
	status = "okay";
};

&sai3 {
	assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
	clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
		<&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
		<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
		<&clk IMX8MQ_AUDIO_PLL2_OUT>;
};

&tlv320aic3x04 {
	clock-names = "mclk";
	clocks = <&clk IMX8MQ_CLK_SAI3_ROOT>;
};

&uart1 {
	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
};

&uart2 {
	assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
};

/* console */
&uart3 {
	assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
};

&usb3_phy0 {
	vbus-supply = <&reg_otg_vbus>;
	status = "okay";
};

&usb_dwc3_0 {
	/* we implement dual role but not full featured OTG */
	extcon = <&extcon_usbotg>;
	hnp-disable;
	srp-disable;
	adp-disable;
	/* OC not supported due to non matching active polarity */
	disable-over-current;
	dr_mode = "otg";
	status = "okay";
};

&usb3_phy1 {
	status = "okay";
};

&usb_dwc3_1 {
	status = "okay";
	dr_mode = "host";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x0000004e>,
			   <MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x0000004e>,
			   <MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x0000004e>,
			   <MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x0000004e>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x0000004e>,
			   <MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x0000004e>,
			   <MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x0000004e>,
			   <MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x0000004e>;
	};

	pinctrl_expander: expandergrp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0xd6>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
			   <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23>,
			   <MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f>,
			   <MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f>,
			   <MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f>,
			   <MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f>,
			   <MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91>,
			   <MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91>,
			   <MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91>,
			   <MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91>,
			   <MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f>,
			   <MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91>,
			   <MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
			   <MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f>;
	};

	pinctrl_gpiobutton: gpiobuttongrp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x41>,
			   <MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x41>,
			   <MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x41>;
	};

	pinctrl_gpioled: gpioledgrp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x41>,
			   <MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x41>,
			   <MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16	0x41>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL		0x40000067>,
			   <MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA		0x40000067>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16		0x40000067>,
			   <MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17		0x40000067>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x40000067>,
			   <MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x40000067>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18		0x40000067>,
			   <MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19		0x40000067>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT		0x16>;
	};

	pinctrl_pwm4: pwm4grp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT		0x16>;
	};

	pinctrl_regotgvbus: reggotgvbusgrp {
		/* USB1 OTG PWR as GPIO */
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x06>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0xc1>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK		0xd6>,
			   <MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0xd6>,
			   <MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0xd6>,
			   <MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0xd6>,
			   <MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0xd6>,
			   <MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0xd6>,
			   <MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0xd6>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x79>,
			   <MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x79>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x79>,
			   <MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x79>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x79>,
			   <MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x79>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX		0x79>,
			   <MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX		0x79>;
	};

	pinctrl_usbcon0: usb0congrp {
		/* ID: floating / high: device, low: host -> use PU */
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0xe6>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83>,
			   <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3>,
			   <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3>,
			   <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3>,
			   <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3>,
			   <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3>,
			   <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x85>,
			   <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc5>,
			   <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5>,
			   <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5>,
			   <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5>,
			   <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5>,
			   <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f>,
			   <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc7>,
			   <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7>,
			   <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7>,
			   <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7>,
			   <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7>,
			   <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1>;
	};

	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
		fsl,pins = <MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2019-2021 TQ-Systems GmbH
 */

#include "imx8mq.dtsi"

/ {
	model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ";
	compatible = "tq,imx8mq-tqma8mq", "fsl,imx8mq";

	memory@40000000 {
		device_type = "memory";
		/*  our minimum RAM config will be 1024 MiB */
		reg = <0x00000000 0x40000000 0 0x40000000>;
	};

	/* e-MMC IO, needed for HS modes */
	reg_vcc1v8: regulator-vcc1v8 {
		compatible = "regulator-fixed";
		regulator-name = "TQMA8MX_VCC1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_vcc3v3: regulator-vcc3v3 {
		compatible = "regulator-fixed";
		regulator-name = "TQMA8MX_VCC3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_vdd_arm: regulator-vdd-arm {
		compatible = "regulator-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_dvfs>;
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <1000000>;
		regulator-name = "TQMa8Mx_DVFS";
		regulator-type = "voltage";
		regulator-settling-time-us = <150000>;
		gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
		states = <900000 0x1 1000000 0x0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			/* 640 MiB */
			size = <0 0x28000000>;
			/*  1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
			alloc-ranges = <0 0x40000000 0 0x78000000>;
			linux,cma-default;
		};
	};
};

&A53_0 {
	cpu-supply = <&reg_vdd_arm>;
};

&A53_1 {
	cpu-supply = <&reg_vdd_arm>;
};

&A53_2 {
	cpu-supply = <&reg_vdd_arm>;
};

&A53_3 {
	cpu-supply = <&reg_vdd_arm>;
};

&gpu {
	status = "okay";
};

&pgc_gpu {
	power-supply = <&sw1a_reg>;
};

&pgc_vpu {
	power-supply = <&sw1c_reg>;
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	pfuze100: pmic@8 {
		compatible = "fsl,pfuze100";
		fsl,pfuze-support-disable-sw;
		reg = <0x8>;

		regulators {
			/* VDD_GPU */
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
			};

			/* VDD_VPU */
			sw1c_reg: sw1c {
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
			};

			/* NVCC_DRAM */
			sw2_reg: sw2 {
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
			};

			/* VDD_DRAM */
			sw3a_reg: sw3ab {
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
			};

			/* 1.8 V for QSPI NOR, e-MMC IO, must not be changed */
			nvcc_1v8_reg: sw4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-always-on;
			};

			/* not used */
			vgen1_reg: vgen1 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			/* VDD_PHY_0V9 */
			vgen2_reg: vgen2 {
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <975000>;
				regulator-always-on;
			};

			/* VDD_PHY_1V8 */
			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1675000>;
				regulator-max-microvolt = <1975000>;
				regulator-always-on;
			};

			/* VDDA_1V8 */
			vgen4_reg: vgen4 {
				regulator-min-microvolt = <1625000>;
				regulator-max-microvolt = <1875000>;
				regulator-always-on;
			};

			/* VDD_PHY_3V3 */
			vgen5_reg: vgen5 {
				regulator-min-microvolt = <3075000>;
				regulator-max-microvolt = <3625000>;
				regulator-always-on;
			};

			/* not used */
			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};

	sensor0: temperature-sensor-eeprom@1b {
		compatible = "nxp,se97", "jedec,jc-42.4-temp";
		reg = <0x1b>;
	};

	pcf85063: rtc@51 {
		compatible = "nxp,pcf85063a";
		reg = <0x51>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_rtc>;
		interrupt-parent = <&gpio1>;
		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
		quartz-load-femtofarads = <7000>;

		clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	eeprom1: eeprom@53 {
		compatible = "nxp,se97b", "atmel,24c02";
		reg = <0x53>;
		pagesize = <16>;
		read-only;
		vcc-supply = <&reg_vcc3v3>;
	};

	eeprom0: eeprom@57 {
		compatible = "atmel,24c64";
		reg = <0x57>;
		pagesize = <32>;
		vcc-supply = <&reg_vcc3v3>;
	};
};

&pcie0 {
	/* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
	vph-supply = <&vgen5_reg>;
};

&pcie1 {
	/* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
	vph-supply = <&vgen5_reg>;
};

&qspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	assigned-clocks = <&clk IMX8MQ_CLK_QSPI>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>;
	status = "okay";

	flash0: flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <84000000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
	};
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	no-sd;
	no-sdio;
	vmmc-supply = <&reg_vcc3v3>;
	vqmmc-supply = <&reg_vcc1v8>;
	status = "okay";
};

/* Attention: wdog reset forcing POR needs baseboard support */
&wdog1 {
	status = "okay";
};

&iomuxc {
	pinctrl_dvfs: dvfsgrp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x16>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x4000007f>,
			   <MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA		0x4000007f>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14		0x40000074>,
			   <MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15		0x40000074>;
	};

	pinctrl_qspi: qspigrp {
		fsl,pins = <MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x97>,
			   <MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82>,
			   <MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x97>,
			   <MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x97>,
			   <MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x97>,
			   <MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x97>;
	};

	pinctrl_rtc: rtcgrp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x41>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x83>,
			   <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc3>,
			   <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3>,
			   <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3>,
			   <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3>,
			   <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3>,
			   <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3>,
			   <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3>,
			   <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3>,
			   <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3>,
			   <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x83>,
			   <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x85>,
			   <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc5>,
			   <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5>,
			   <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5>,
			   <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5>,
			   <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5>,
			   <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5>,
			   <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5>,
			   <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5>,
			   <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5>,
			   <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x85>,
			   <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x87>,
			   <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc7>,
			   <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7>,
			   <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7>,
			   <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7>,
			   <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7>,
			   <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7>,
			   <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7>,
			   <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7>,
			   <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7>,
			   <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x87>,
			   <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2019 Zodiac Inflight Innovations
 */

/dts-v1/;

#include "imx8mq-zii-ultra.dtsi"

/ {
	model = "ZII Ultra RMB3 Board";
	compatible = "zii,imx8mq-ultra-rmb3", "zii,imx8mq-ultra", "fsl,imx8mq";

	sound1 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "front";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&sound1_codec>;
		simple-audio-card,frame-master = <&sound1_codec>;
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack Front";
		simple-audio-card,routing =
			"Headphone Jack Front", "HPA1 HPLEFT",
			"Headphone Jack Front", "HPA1 HPRIGHT",
			"HPA1 LEFTIN", "HPL",
			"HPA1 RIGHTIN", "HPR";
		simple-audio-card,aux-devs = <&hpa1>;

		sound1_cpu: simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};

		sound1_codec: simple-audio-card,codec {
			sound-dai = <&codec1>;
			clocks = <&cs2000>;
		};
	};

	sound2 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "periph";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&sound2_codec>;
		simple-audio-card,frame-master = <&sound2_codec>;
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack Back";
		simple-audio-card,routing =
			"Headphone Jack Back", "HPA1 HPLEFT",
			"Headphone Jack Back", "HPA1 HPRIGHT",
			"HPA1 LEFTIN", "HPL",
			"HPA1 RIGHTIN", "HPR";
		simple-audio-card,aux-devs = <&hpa2>;

		sound2_cpu: simple-audio-card,cpu {
			sound-dai = <&sai3>;
		};

		sound2_codec: simple-audio-card,codec {
			sound-dai = <&codec2>;
			clocks = <&cs2000>;
		};
	};
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	nor_flash: flash@0 {
		compatible = "st,n25q128a13", "jedec,spi-nor";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&hpa2 {
	sound-name-prefix = "HPA1";
};

&i2c1 {
	codec2: codec@18 {
		compatible = "ti,tlv320dac3100";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_codec2>;
		reg = <0x18>;
		#sound-dai-cells = <0>;
		HPVDD-supply = <&reg_gen_3p3>;
		SPRVDD-supply = <&reg_gen_3p3>;
		SPLVDD-supply = <&reg_gen_3p3>;
		AVDD-supply = <&reg_gen_3p3>;
		IOVDD-supply = <&reg_gen_3p3>;
		DVDD-supply = <&vgen4_reg>;
		reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
	};
};

&i2c2 {
	temp-sense@48 {
		compatible = "national,lm75";
		reg = <0x48>;
	};
};

&i2c4 {
	touchscreen@20 {
		compatible = "syna,rmi4-i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ts>;
		reg = <0x20>;
		interrupt-parent = <&gpio1>;
		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;

		#address-cells = <1>;
		#size-cells = <0>;

		rmi4-f01@1 {
			reg = <0x1>;
			syna,nosleep-mode = <2>;
		};

		rmi4-f11@11 {
			reg = <0x11>;
			touchscreen-inverted-x;
			touchscreen-swapped-x-y;
			syna,sensor-type = <1>;
			syna,delta-x-threshold = <5>;
			syna,delta-y-threshold = <10>;
		};

		rmi4-f12@12 {
			reg = <0x12>;
			touchscreen-inverted-x;
			touchscreen-swapped-x-y;
			syna,sensor-type = <1>;
		};
	};

	touchscreen@2a {
		compatible = "eeti,exc3000";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ts>;
		reg = <0x2a>;
		interrupt-parent = <&gpio1>;
		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
		touchscreen-inverted-x;
		touchscreen-swapped-x-y;
		status = "disabled";
	};
};

&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	status = "okay";
};

&usbhub {
	swap-dx-lanes = <0>;
};

&iomuxc {
	pinctrl_codec2: dac2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x41
		>;
	};

	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x19
			MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82
			MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82
			MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0xd6
			MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0xd6
			MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0xd6
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2019 Zodiac Inflight Innovations
 */

/dts-v1/;

#include "imx8mq-zii-ultra.dtsi"

/ {
	model = "ZII Ultra Zest Board";
	compatible = "zii,imx8mq-ultra-zest", "zii,imx8mq-ultra", "fsl,imx8mq";

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "front";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&sound_codec>;
		simple-audio-card,frame-master = <&sound_codec>;
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack Front",
			"Headphone", "Headphone Jack Back";
		simple-audio-card,routing =
			"Headphone Jack Front", "HPA1 HPLEFT",
			"Headphone Jack Front", "HPA1 HPRIGHT",
			"Headphone Jack Back", "HPA2 HPLEFT",
			"Headphone Jack Back", "HPA2 HPRIGHT",
			"HPA1 LEFTIN", "HPL",
			"HPA1 RIGHTIN", "HPR",
			"HPA2 LEFTIN", "HPL",
			"HPA2 RIGHTIN", "HPR";
		simple-audio-card,aux-devs = <&hpa1>, <&hpa2>;

		sound_cpu: simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};

		sound_codec: simple-audio-card,codec {
			sound-dai = <&codec1>;
			clocks = <&cs2000>;
		};
	};
};

&i2c4 {
	touchscreen@4a {
		compatible = "atmel,maxtouch";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ts>;
		reg = <0x4a>;
		interrupt-parent = <&gpio1>;
		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2019 Zodiac Inflight Innovations
 */

#include "imx8mq.dtsi"

/ {
	aliases {
		mdio-gpio0 = &mdio0;
		rtc0 = &ds1341;
	};

	chosen {
		stdout-path = &uart1;
	};

	mdio0: bitbang-mdio {
		compatible = "virtual,mdio-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
			<&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
		#address-cells = <1>;
		#size-cells = <0>;

		phy0: ethernet-phy@0 {
			reg = <0>;
			reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
		};
	};

	pcie0_refclk: clock-pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pcie1_refclk: clock-pcie1-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	reg_12p0_main: regulator-12p0-main {
		compatible = "regulator-fixed";
		regulator-name = "12V_MAIN";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
	};

	reg_5p0_main: regulator-5p0-main {
		compatible = "regulator-fixed";
		vin-supply = <&reg_12p0_main>;
		regulator-name = "5V_MAIN";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
	};

	reg_3p3_main: regulator-3p3-main {
		compatible = "regulator-fixed";
		vin-supply = <&reg_12p0_main>;
		regulator-name = "3V3_MAIN";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_gen_3p3: regulator-gen-3p3 {
		compatible = "regulator-fixed";
		vin-supply = <&reg_3p3_main>;
		regulator-name = "GEN_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_usdhc2_vmmc: regulator-vsd-3v3 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2>;
		compatible = "regulator-fixed";
		vin-supply = <&reg_gen_3p3>;
		regulator-name = "3V3_SD";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_arm: regulator-arm {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_arm>;
		compatible = "regulator-gpio";
		vin-supply = <&reg_12p0_main>;
		regulator-name = "0V9_ARM";
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <1000000>;
		gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
		states = <1000000 0x1
		           900000 0x0>;
		regulator-always-on;
	};

	cs2000_ref: cs2000-ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
	};

	cs2000_in_dummy: cs2000-in-dummy {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};
};

&A53_0 {
	cpu-supply = <&reg_arm>;
};

&A53_1 {
	cpu-supply = <&reg_arm>;
};

&A53_2 {
	cpu-supply = <&reg_arm>;
};

&A53_3 {
	cpu-supply = <&reg_arm>;
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;

	phy-handle = <&phy0>;
	phy-mode = "rmii";
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <12500000>;
		suppress-preamble;
		status = "okay";

		switch: switch@0 {
			compatible = "marvell,mv88e6085";
			pinctrl-0 = <&pinctrl_switch_irq>;
			pinctrl-names = "default";
			reg = <0>;
			dsa,member = <0 0>;
			eeprom-length = <512>;
			interrupt-parent = <&gpio1>;
			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
			interrupt-controller;
			#interrupt-cells = <2>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "gigabit_proc";
					phy-handle = <&switchphy0>;
				};

				port@1 {
					reg = <1>;
					label = "netaux";
					phy-handle = <&switchphy1>;
				};

				port@2 {
					reg = <2>;
					label = "cpu";
					ethernet = <&fec1>;

					fixed-link {
						speed = <100>;
						full-duplex;
					};
				};

				port@3 {
					reg = <3>;
					label = "netright";
					phy-handle = <&switchphy3>;
				};

				port@4 {
					reg = <4>;
					label = "netleft";
					phy-handle = <&switchphy4>;
				};
			};

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				switchphy0: switchphy@0 {
					reg = <0>;
					interrupt-parent = <&switch>;
					interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
				};

				switchphy1: switchphy@1 {
					reg = <1>;
					interrupt-parent = <&switch>;
					interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
				};

				switchphy2: switchphy@2 {
					reg = <2>;
					interrupt-parent = <&switch>;
					interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
				};

				switchphy3: switchphy@3 {
					reg = <3>;
					interrupt-parent = <&switch>;
					interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
				};

				switchphy4: switchphy@4 {
					reg = <4>;
					interrupt-parent = <&switch>;
					interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
				};
			};
		};
	};
};

&gpio3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio3_hog>;

	usb-emulation-hog {
		gpio-hog;
		gpios = <10 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "usb-emulation";
	};

	usb-mode1-hog {
		gpio-hog;
		gpios = <11 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "usb-mode1";
	};

	usb-pwr-hog {
		gpio-hog;
		gpios = <12 GPIO_ACTIVE_LOW>;
		output-high;
		line-name = "usb-pwr-ctrl-en-n";
	};

	usb-mode2-hog {
		gpio-hog;
		gpios = <13 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "usb-mode2";
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	accelerometer@1c {
		compatible = "fsl,mma8451";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_accel>;
		reg = <0x1c>;
		interrupt-parent = <&gpio3>;
		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "INT2";
		vdd-supply = <&reg_gen_3p3>;
		vddio-supply = <&reg_gen_3p3>;
	};

	ucs1002: charger@32 {
		compatible = "microchip,ucs1002";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ucs1002>;
		reg = <0x32>;
		interrupt-parent = <&gpio3>;
		interrupts = <17 IRQ_TYPE_EDGE_BOTH>,
		             <18 IRQ_TYPE_EDGE_FALLING>;
		interrupt-names = "a_det", "alert";
	};

	hpa2: amp@60 {
		compatible = "ti,tpa6130a2";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tpa2>;
		reg = <0x60>;
		power-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
		Vdd-supply = <&reg_5p0_main>;
		sound-name-prefix = "HPA2";
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pmic@8 {
		compatible = "fsl,pfuze100";
		reg = <0x8>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
			};

			sw1c_reg: sw1c {
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
			};

			sw3a_reg: sw3ab {
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <975000>;
				regulator-always-on;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1675000>;
				regulator-max-microvolt = <1975000>;
				regulator-always-on;
			};

			vgen4_reg: vgen4 {
				regulator-min-microvolt = <1625000>;
				regulator-max-microvolt = <1875000>;
				regulator-always-on;
			};

			vgen5_reg: vgen5 {
				regulator-min-microvolt = <3075000>;
				regulator-max-microvolt = <3625000>;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};

	codec1: codec@18 {
		compatible = "ti,tlv320dac3100";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_codec1>;
		reg = <0x18>;
		#sound-dai-cells = <0>;
		HPVDD-supply = <&reg_gen_3p3>;
		SPRVDD-supply = <&reg_gen_3p3>;
		SPLVDD-supply = <&reg_gen_3p3>;
		AVDD-supply = <&reg_gen_3p3>;
		IOVDD-supply = <&reg_gen_3p3>;
		DVDD-supply = <&vgen4_reg>;
		reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
	};

	eeprom@54 {
		compatible = "atmel,24c128";
		reg = <0x54>;
	};

	hpa1: amp@60 {
		compatible = "ti,tpa6130a2";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tpa1>;
		reg = <0x60>;
		power-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
		Vdd-supply = <&reg_5p0_main>;
		sound-name-prefix = "HPA1";
	};

	ds1341: rtc@68 {
		compatible = "dallas,ds1341";
		reg = <0x68>;
	};
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	usbhub: usbhub@2c {
		compatible = "microchip,usb2513b";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbhub>;
		reg = <0x2c>;
		reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
	};

	watchdog@38 {
		compatible = "zii,rave-wdt";
		reg = <0x38>;
	};

	cs2000: clkgen@4e {
		compatible = "cirrus,cs2000-cp";
		reg = <0x4e>;
		#clock-cells = <0>;
		clock-names = "clk_in", "ref_clk";
		clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
		assigned-clocks = <&cs2000>;
		assigned-clock-rates = <24000000>;
	};
};

&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";

	rave-sp {
		compatible = "zii,rave-sp-rdu2";
		current-speed = <1000000>;
		#address-cells = <1>;
		#size-cells = <1>;

		watchdog {
			compatible = "zii,rave-sp-watchdog";
		};

		backlight {
			compatible = "zii,rave-sp-backlight";
		};

		pwrbutton {
			compatible = "zii,rave-sp-pwrbutton";
		};

		eeprom@a3 {
			compatible = "zii,rave-sp-eeprom";
			reg = <0xa3 0x4000>;
			zii,eeprom-name = "dds-eeprom";
		};

		eeprom@a4 {
			compatible = "zii,rave-sp-eeprom";
			reg = <0xa4 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			zii,eeprom-name = "main-eeprom";
		};
	};
};

&usb3_phy0 {
	vbus-supply = <&ucs1002>;
	status = "okay";
};

&usb_dwc3_0 {
	dr_mode = "host";
	maximum-speed = "high-speed";
	status = "okay";
};

&usb3_phy1 {
	vbus-supply = <&reg_5p0_main>;
	status = "okay";
};

&usb_dwc3_1 {
	dr_mode = "host";
	maximum-speed = "high-speed";
	status = "okay";
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
	         <&clk IMX8MQ_CLK_PCIE1_AUX>,
	         <&clk IMX8MQ_CLK_PCIE1_PHY>,
	         <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	vph-supply = <&vgen5_reg>;
	status = "okay";
};

&pcie1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie1>;
	reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
	         <&clk IMX8MQ_CLK_PCIE2_AUX>,
	         <&clk IMX8MQ_CLK_PCIE2_PHY>,
	         <&pcie1_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	vph-supply = <&vgen5_reg>;
	status = "okay";
};

&pgc_gpu {
	power-supply = <&sw1a_reg>;
};

&pgc_vpu {
	power-supply = <&sw1c_reg>;
};

&usdhc1 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	vqmmc-supply = <&sw4_reg>;
	bus-width = <8>;
	non-removable;
	no-sd;
	no-sdio;
	status = "okay";
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&snvs_rtc {
	status = "disabled";
};

&iomuxc {
	pinctrl_accel: accelgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20		0x41
		>;
	};

	pinctrl_codec1: dac1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x41
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK		0x1f
			MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER		0x91
			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
		>;
	};

	pinctrl_fec1_phy_reset: fec1phyresetgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29		0x11
		>;
	};

	pinctrl_gpio3_hog: gpio3hoggrp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10		0x6
			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x6
			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x6
			MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13		0x6
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000022
			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x400000a2
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000022
			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x400000a2
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000022
			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x400000a2
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000022
			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x400000a2
		>;
	};

	pinctrl_mdio_bitbang: bitbangmdiogrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x44
			MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x64
		>;
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B		0x66
			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x6
		>;
	};

	pinctrl_pcie1: pcie1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B		0x66
			MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x6
		>;
	};

	pinctrl_reg_arm: regarmgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19
		>;
	};

	pinctrl_reg_usdhc2: regusdhc2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6
			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6
			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0xd6
		>;
	};

	pinctrl_switch_irq: switchgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x41
		>;
	};

	pinctrl_tpa1: tpa6130-1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x41
		>;
	};

	pinctrl_tpa2: tpa6130-2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x41
		>;
	};

	pinctrl_ts: tsgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x96
			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x96
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
		>;
	};

	pinctrl_ucs1002: ucs1002grp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x41
			MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18		0x41
		>;
	};

	pinctrl_usbhub: usbhubgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x41
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2017 NXP
 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
 */

#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include "dt-bindings/input/input.h"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/interconnect/imx8mq.h>
#include "imx8mq-pinfunc.h"

/ {
	interrupt-parent = <&gpc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec1;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &ecspi3;
	};

	ckil: clock-ckil {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "ckil";
	};

	osc_25m: clock-osc-25m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
		clock-output-names = "osc_25m";
	};

	osc_27m: clock-osc-27m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
		clock-output-names = "osc_27m";
	};

	hdmi_phy_27m: clock-hdmi-phy-27m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
		clock-output-names = "hdmi_phy_27m";
	};

	clk_ext1: clock-ext1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext1";
	};

	clk_ext2: clock-ext2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext2";
	};

	clk_ext3: clock-ext3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext3";
	};

	clk_ext4: clock-ext4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext4";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		A53_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clk IMX8MQ_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			#cooling-cells = <2>;
			nvmem-cells = <&cpu_speed_grade>;
			nvmem-cell-names = "speed_grade";
		};

		A53_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clk IMX8MQ_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			#cooling-cells = <2>;
		};

		A53_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clk IMX8MQ_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			#cooling-cells = <2>;
		};

		A53_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clk IMX8MQ_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			#cooling-cells = <2>;
		};

		A53_L2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x100000>;
			cache-line-size = <64>;
			cache-sets = <1024>;
		};
	};

	a53_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <900000>;
			/* Industrial only */
			opp-supported-hw = <0xf>, <0x4>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};

		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <900000>;
			/* Consumer only */
			opp-supported-hw = <0xe>, <0x3>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};

		opp-1300000000 {
			opp-hz = /bits/ 64 <1300000000>;
			opp-microvolt = <1000000>;
			opp-supported-hw = <0xc>, <0x4>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};

		opp-1500000000 {
			opp-hz = /bits/ 64 <1500000000>;
			opp-microvolt = <1000000>;
			opp-supported-hw = <0x8>, <0x3>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tmu 0>;

			trips {
				cpu_alert: cpu-alert {
					temperature = <80000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu-crit {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert>;
					cooling-device =
						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		gpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tmu 1>;

			trips {
				gpu_alert: gpu-alert {
					temperature = <80000>;
					hysteresis = <2000>;
					type = "passive";
				};

				gpu-crit {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&gpu_alert>;
					cooling-device =
						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		vpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tmu 2>;

			trips {
				vpu-crit {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
		             <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
		             <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
		             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
		interrupt-parent = <&gic>;
		arm,no-tick-in-suspend;
	};

	soc: soc@0 {
		compatible = "fsl,imx8mq-soc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x3e000000>;
		dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
		nvmem-cells = <&imx8mq_uid>;
		nvmem-cell-names = "soc_unique_id";

		aips1: bus@30000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x30000000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30000000 0x30000000 0x400000>;

			sai1: sai@30010000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx8mq-sai";
				reg = <0x30010000 0x10000>;
				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
				         <&clk IMX8MQ_CLK_SAI1_ROOT>,
				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			sai6: sai@30030000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx8mq-sai";
				reg = <0x30030000 0x10000>;
				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
				         <&clk IMX8MQ_CLK_SAI6_ROOT>,
				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			sai5: sai@30040000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx8mq-sai";
				reg = <0x30040000 0x10000>;
				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
				         <&clk IMX8MQ_CLK_SAI5_ROOT>,
				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			sai4: sai@30050000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx8mq-sai";
				reg = <0x30050000 0x10000>;
				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
				         <&clk IMX8MQ_CLK_SAI4_ROOT>,
				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			gpio1: gpio@30200000 {
				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
				reg = <0x30200000 0x10000>;
				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 10 30>;
			};

			gpio2: gpio@30210000 {
				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
				reg = <0x30210000 0x10000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 40 21>;
			};

			gpio3: gpio@30220000 {
				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
				reg = <0x30220000 0x10000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 61 26>;
			};

			gpio4: gpio@30230000 {
				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
				reg = <0x30230000 0x10000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 87 32>;
			};

			gpio5: gpio@30240000 {
				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
				reg = <0x30240000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 119 30>;
			};

			tmu: tmu@30260000 {
				compatible = "fsl,imx8mq-tmu";
				reg = <0x30260000 0x10000>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
				little-endian;
				fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
				fsl,tmu-calibration = <0x00000000 0x00000023>,
						      <0x00000001 0x00000029>,
						      <0x00000002 0x0000002f>,
						      <0x00000003 0x00000035>,
						      <0x00000004 0x0000003d>,
						      <0x00000005 0x00000043>,
						      <0x00000006 0x0000004b>,
						      <0x00000007 0x00000051>,
						      <0x00000008 0x00000057>,
						      <0x00000009 0x0000005f>,
						      <0x0000000a 0x00000067>,
						      <0x0000000b 0x0000006f>,

						      <0x00010000 0x0000001b>,
						      <0x00010001 0x00000023>,
						      <0x00010002 0x0000002b>,
						      <0x00010003 0x00000033>,
						      <0x00010004 0x0000003b>,
						      <0x00010005 0x00000043>,
						      <0x00010006 0x0000004b>,
						      <0x00010007 0x00000055>,
						      <0x00010008 0x0000005d>,
						      <0x00010009 0x00000067>,
						      <0x0001000a 0x00000070>,

						      <0x00020000 0x00000017>,
						      <0x00020001 0x00000023>,
						      <0x00020002 0x0000002d>,
						      <0x00020003 0x00000037>,
						      <0x00020004 0x00000041>,
						      <0x00020005 0x0000004b>,
						      <0x00020006 0x00000057>,
						      <0x00020007 0x00000063>,
						      <0x00020008 0x0000006f>,

						      <0x00030000 0x00000015>,
						      <0x00030001 0x00000021>,
						      <0x00030002 0x0000002d>,
						      <0x00030003 0x00000039>,
						      <0x00030004 0x00000045>,
						      <0x00030005 0x00000053>,
						      <0x00030006 0x0000005f>,
						      <0x00030007 0x00000071>;
				#thermal-sensor-cells = <1>;
			};

			wdog1: watchdog@30280000 {
				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
				reg = <0x30280000 0x10000>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
				status = "disabled";
			};

			wdog2: watchdog@30290000 {
				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
				reg = <0x30290000 0x10000>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
				status = "disabled";
			};

			wdog3: watchdog@302a0000 {
				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
				reg = <0x302a0000 0x10000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
				status = "disabled";
			};

			sdma2: dma-controller@302c0000 {
				compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
				reg = <0x302c0000 0x10000>;
				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
					 <&clk IMX8MQ_CLK_SDMA2_ROOT>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			lcdif: lcd-controller@30320000 {
				compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
				reg = <0x30320000 0x10000>;
				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
				clock-names = "pix";
				assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
						  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
						  <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
						  <&clk IMX8MQ_VIDEO_PLL1>;
				assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
						  <&clk IMX8MQ_VIDEO_PLL1>,
						  <&clk IMX8MQ_VIDEO_PLL1_OUT>;
				assigned-clock-rates = <0>, <0>, <0>, <594000000>;
				status = "disabled";

				port {
					lcdif_mipi_dsi: endpoint {
						remote-endpoint = <&mipi_dsi_lcdif_in>;
					};
				};
			};

			iomuxc: pinctrl@30330000 {
				compatible = "fsl,imx8mq-iomuxc";
				reg = <0x30330000 0x10000>;
			};

			iomuxc_gpr: syscon@30340000 {
				compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
					     "syscon", "simple-mfd";
				reg = <0x30340000 0x10000>;

				mux: mux-controller {
					compatible = "mmio-mux";
					#mux-control-cells = <1>;
					mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
				};
			};

			ocotp: efuse@30350000 {
				compatible = "fsl,imx8mq-ocotp", "syscon";
				reg = <0x30350000 0x10000>;
				clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
				#address-cells = <1>;
				#size-cells = <1>;

				imx8mq_uid: soc-uid@410 {
					reg = <0x4 0x8>;
				};

				cpu_speed_grade: speed-grade@10 {
					reg = <0x10 4>;
				};

				fec_mac_address: mac-address@90 {
					reg = <0x90 6>;
				};
			};

			anatop: clock-controller@30360000 {
				compatible = "fsl,imx8mq-anatop";
				reg = <0x30360000 0x10000>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
				#clock-cells = <1>;
			};

			snvs: snvs@30370000 {
				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
				reg = <0x30370000 0x10000>;

				snvs_rtc: snvs-rtc-lp{
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap =<&snvs>;
					offset = <0x34>;
					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
					clock-names = "snvs-rtc";
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
					clock-names = "snvs-pwrkey";
					linux,keycode = <KEY_POWER>;
					wakeup-source;
					status = "disabled";
				};
			};

			clk: clock-controller@30380000 {
				compatible = "fsl,imx8mq-ccm";
				reg = <0x30380000 0x10000>;
				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				#clock-cells = <1>;
				clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
				         <&clk_ext1>, <&clk_ext2>,
				         <&clk_ext3>, <&clk_ext4>;
				clock-names = "ckil", "osc_25m", "osc_27m",
				              "clk_ext1", "clk_ext2",
				              "clk_ext3", "clk_ext4";
				assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
						  <&clk IMX8MQ_CLK_A53_CORE>,
						  <&clk IMX8MQ_CLK_NOC>,
						  <&clk IMX8MQ_CLK_AUDIO_AHB>,
						  <&clk IMX8MQ_AUDIO_PLL1_BYPASS>,
						  <&clk IMX8MQ_AUDIO_PLL2_BYPASS>,
						  <&clk IMX8MQ_AUDIO_PLL1>,
						  <&clk IMX8MQ_AUDIO_PLL2>;
				assigned-clock-rates = <0>, <0>,
						       <800000000>,
						       <0>,
						       <0>,
						       <0>,
						       <786432000>,
						       <722534400>;
				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
							 <&clk IMX8MQ_ARM_PLL_OUT>,
							 <0>,
							 <&clk IMX8MQ_SYS2_PLL_500M>,
							 <&clk IMX8MQ_AUDIO_PLL1>,
							 <&clk IMX8MQ_AUDIO_PLL2>;
			};

			src: reset-controller@30390000 {
				compatible = "fsl,imx8mq-src", "syscon";
				reg = <0x30390000 0x10000>;
				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};

			gpc: gpc@303a0000 {
				compatible = "fsl,imx8mq-gpc";
				reg = <0x303a0000 0x10000>;
				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-parent = <&gic>;
				interrupt-controller;
				#interrupt-cells = <3>;

				pgc {
					#address-cells = <1>;
					#size-cells = <0>;

					pgc_mipi: power-domain@0 {
						#power-domain-cells = <0>;
						reg = <IMX8M_POWER_DOMAIN_MIPI>;
					};

					/*
					 * As per comment in ATF source code:
					 *
					 * PCIE1 and PCIE2 share the
					 * same reset signal, if we
					 * power down PCIE2, PCIE1
					 * will be held in reset too.
					 *
					 * So instead of creating two
					 * separate power domains for
					 * PCIE1 and PCIE2 we create a
					 * link between both and use
					 * it as a shared PCIE power
					 * domain.
					 */
					pgc_pcie: power-domain@1 {
						#power-domain-cells = <0>;
						reg = <IMX8M_POWER_DOMAIN_PCIE1>;
						power-domains = <&pgc_pcie2>;
					};

					pgc_otg1: power-domain@2 {
						#power-domain-cells = <0>;
						reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
					};

					pgc_otg2: power-domain@3 {
						#power-domain-cells = <0>;
						reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
					};

					pgc_ddr1: power-domain@4 {
						#power-domain-cells = <0>;
						reg = <IMX8M_POWER_DOMAIN_DDR1>;
					};

					pgc_gpu: power-domain@5 {
						#power-domain-cells = <0>;
						reg = <IMX8M_POWER_DOMAIN_GPU>;
						clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
						         <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
							 <&clk IMX8MQ_CLK_GPU_AXI>,
						         <&clk IMX8MQ_CLK_GPU_AHB>;
					};

					pgc_vpu: power-domain@6 {
						#power-domain-cells = <0>;
						reg = <IMX8M_POWER_DOMAIN_VPU>;
						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
							 <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
							 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
						assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
								  <&clk IMX8MQ_CLK_VPU_G2>,
								  <&clk IMX8MQ_CLK_VPU_BUS>,
								  <&clk IMX8MQ_VPU_PLL_BYPASS>;
						assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
									 <&clk IMX8MQ_VPU_PLL_OUT>,
									 <&clk IMX8MQ_SYS1_PLL_800M>,
									 <&clk IMX8MQ_VPU_PLL>;
						assigned-clock-rates = <600000000>,
								       <600000000>,
								       <800000000>,
								       <0>;
					};

					pgc_disp: power-domain@7 {
						#power-domain-cells = <0>;
						reg = <IMX8M_POWER_DOMAIN_DISP>;
					};

					pgc_mipi_csi1: power-domain@8 {
						#power-domain-cells = <0>;
						reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
					};

					pgc_mipi_csi2: power-domain@9 {
						#power-domain-cells = <0>;
						reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
					};

					pgc_pcie2: power-domain@a {
						#power-domain-cells = <0>;
						reg = <IMX8M_POWER_DOMAIN_PCIE2>;
					};
				};
			};
		};

		aips2: bus@30400000 { /* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x30400000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30400000 0x30400000 0x400000>;

			pwm1: pwm@30660000 {
				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
				reg = <0x30660000 0x10000>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
				         <&clk IMX8MQ_CLK_PWM1_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm2: pwm@30670000 {
				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
				reg = <0x30670000 0x10000>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
				         <&clk IMX8MQ_CLK_PWM2_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm3: pwm@30680000 {
				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
				reg = <0x30680000 0x10000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
				         <&clk IMX8MQ_CLK_PWM3_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm4: pwm@30690000 {
				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
				reg = <0x30690000 0x10000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
				         <&clk IMX8MQ_CLK_PWM4_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			system_counter: timer@306a0000 {
				compatible = "nxp,sysctr-timer";
				reg = <0x306a0000 0x20000>;
				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&osc_25m>;
				clock-names = "per";
			};
		};

		aips3: bus@30800000 { /* AIPS3 */
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x30800000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30800000 0x30800000 0x400000>,
				 <0x08000000 0x08000000 0x10000000>;

			spdif1: spdif@30810000 {
				compatible = "fsl,imx35-spdif";
				reg = <0x30810000 0x10000>;
				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
					<&clk IMX8MQ_CLK_25M>, /* rxtx0 */
					<&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */
					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
					<&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
					<&clk IMX8MQ_CLK_DUMMY>; /* spba */
				clock-names = "core", "rxtx0",
					      "rxtx1", "rxtx2",
					      "rxtx3", "rxtx4",
					      "rxtx5", "rxtx6",
					      "rxtx7", "spba";
				dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			ecspi1: spi@30820000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
				reg = <0x30820000 0x10000>;
				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
					 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			ecspi2: spi@30830000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
				reg = <0x30830000 0x10000>;
				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
					 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			ecspi3: spi@30840000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
				reg = <0x30840000 0x10000>;
				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
					 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart1: serial@30860000 {
				compatible = "fsl,imx8mq-uart",
				             "fsl,imx6q-uart";
				reg = <0x30860000 0x10000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
				         <&clk IMX8MQ_CLK_UART1_ROOT>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart3: serial@30880000 {
				compatible = "fsl,imx8mq-uart",
				             "fsl,imx6q-uart";
				reg = <0x30880000 0x10000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
				         <&clk IMX8MQ_CLK_UART3_ROOT>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@30890000 {
				compatible = "fsl,imx8mq-uart",
				             "fsl,imx6q-uart";
				reg = <0x30890000 0x10000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
				         <&clk IMX8MQ_CLK_UART2_ROOT>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			spdif2: spdif@308a0000 {
				compatible = "fsl,imx35-spdif";
				reg = <0x308a0000 0x10000>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
					<&clk IMX8MQ_CLK_25M>, /* rxtx0 */
					<&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */
					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
					<&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
					<&clk IMX8MQ_CLK_DUMMY>; /* spba */
				clock-names = "core", "rxtx0",
					      "rxtx1", "rxtx2",
					      "rxtx3", "rxtx4",
					      "rxtx5", "rxtx6",
					      "rxtx7", "spba";
				dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			sai2: sai@308b0000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx8mq-sai";
				reg = <0x308b0000 0x10000>;
				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
					 <&clk IMX8MQ_CLK_SAI2_ROOT>,
					 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			sai3: sai@308c0000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx8mq-sai";
				reg = <0x308c0000 0x10000>;
				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
				         <&clk IMX8MQ_CLK_SAI3_ROOT>,
				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			crypto: crypto@30900000 {
				compatible = "fsl,sec-v4.0";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x30900000 0x40000>;
				ranges = <0 0x30900000 0x40000>;
				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_AHB>,
					 <&clk IMX8MQ_CLK_IPG_ROOT>;
				clock-names = "aclk", "ipg";

				sec_jr0: jr@1000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x1000 0x1000>;
					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
					status = "disabled";
				};

				sec_jr1: jr@2000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x2000 0x1000>;
					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr2: jr@3000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x3000 0x1000>;
					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			mipi_dsi: mipi-dsi@30a00000 {
				compatible = "fsl,imx8mq-nwl-dsi";
				reg = <0x30a00000 0x300>;
				clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
					 <&clk IMX8MQ_CLK_DSI_AHB>,
					 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
					 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
					 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
				clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
				assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
						  <&clk IMX8MQ_CLK_DSI_CORE>,
						  <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
							 <&clk IMX8MQ_SYS1_PLL_266M>;
				assigned-clock-rates = <80000000>, <266000000>, <20000000>;
				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
				mux-controls = <&mux 0>;
				power-domains = <&pgc_mipi>;
				phys = <&dphy>;
				phy-names = "dphy";
				resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
					 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
					 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
					 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
				reset-names = "byte", "dpi", "esc", "pclk";
				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						#address-cells = <1>;
						#size-cells = <0>;
						mipi_dsi_lcdif_in: endpoint@0 {
							reg = <0>;
							remote-endpoint = <&lcdif_mipi_dsi>;
						};
					};
				};
			};

			dphy: dphy@30a00300 {
				compatible = "fsl,imx8mq-mipi-dphy";
				reg = <0x30a00300 0x100>;
				clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
				clock-names = "phy_ref";
				assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
						  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
						  <&clk IMX8MQ_CLK_DSI_PHY_REF>,
						  <&clk IMX8MQ_VIDEO_PLL1>;
				assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
						  <&clk IMX8MQ_VIDEO_PLL1>,
						  <&clk IMX8MQ_VIDEO_PLL1_OUT>;
				assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
				#phy-cells = <0>;
				power-domains = <&pgc_mipi>;
				status = "disabled";
			};

			i2c1: i2c@30a20000 {
				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
				reg = <0x30a20000 0x10000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c2: i2c@30a30000 {
				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
				reg = <0x30a30000 0x10000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c3: i2c@30a40000 {
				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
				reg = <0x30a40000 0x10000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c4: i2c@30a50000 {
				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
				reg = <0x30a50000 0x10000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			uart4: serial@30a60000 {
				compatible = "fsl,imx8mq-uart",
				             "fsl,imx6q-uart";
				reg = <0x30a60000 0x10000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
				         <&clk IMX8MQ_CLK_UART4_ROOT>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			mipi_csi1: csi@30a70000 {
				compatible = "fsl,imx8mq-mipi-csi2";
				reg = <0x30a70000 0x1000>;
				clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
				   <&clk IMX8MQ_CLK_CSI1_ESC>,
				   <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
				clock-names = "core", "esc", "ui";
				assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
				    <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
				    <&clk IMX8MQ_CLK_CSI1_ESC>;
				assigned-clock-rates = <266000000>, <333000000>, <66000000>;
				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
					<&clk IMX8MQ_SYS2_PLL_1000M>,
					<&clk IMX8MQ_SYS1_PLL_800M>;
				power-domains = <&pgc_mipi_csi1>;
				resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
					 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
					 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
				fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
				interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
				interconnect-names = "dram";
				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@1 {
						reg = <1>;

						csi1_mipi_ep: endpoint {
							remote-endpoint = <&csi1_ep>;
						};
					};
				};
			};

			csi1: csi@30a90000 {
				compatible = "fsl,imx8mq-csi";
				reg = <0x30a90000 0x10000>;
				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
				clock-names = "mclk";
				status = "disabled";

				port {
					csi1_ep: endpoint {
						remote-endpoint = <&csi1_mipi_ep>;
					};
				};
			};

			mipi_csi2: csi@30b60000 {
				compatible = "fsl,imx8mq-mipi-csi2";
				reg = <0x30b60000 0x1000>;
				clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
				   <&clk IMX8MQ_CLK_CSI2_ESC>,
				   <&clk IMX8MQ_CLK_CSI2_PHY_REF>;
				clock-names = "core", "esc", "ui";
				assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
				    <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
				    <&clk IMX8MQ_CLK_CSI2_ESC>;
				assigned-clock-rates = <266000000>, <333000000>, <66000000>;
				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
					<&clk IMX8MQ_SYS2_PLL_1000M>,
					<&clk IMX8MQ_SYS1_PLL_800M>;
				power-domains = <&pgc_mipi_csi2>;
				resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>,
					 <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>,
					 <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>;
				fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
				interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
				interconnect-names = "dram";
				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@1 {
						reg = <1>;

						csi2_mipi_ep: endpoint {
							remote-endpoint = <&csi2_ep>;
						};
					};
				};
			};

			csi2: csi@30b80000 {
				compatible = "fsl,imx8mq-csi";
				reg = <0x30b80000 0x10000>;
				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
				clock-names = "mclk";
				status = "disabled";

				port {
					csi2_ep: endpoint {
						remote-endpoint = <&csi2_mipi_ep>;
					};
				};
			};

			mu: mailbox@30aa0000 {
				compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
				reg = <0x30aa0000 0x10000>;
				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
				#mbox-cells = <2>;
			};

			usdhc1: mmc@30b40000 {
				compatible = "fsl,imx8mq-usdhc",
				             "fsl,imx7d-usdhc";
				reg = <0x30b40000 0x10000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@30b50000 {
				compatible = "fsl,imx8mq-usdhc",
				             "fsl,imx7d-usdhc";
				reg = <0x30b50000 0x10000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
				         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			qspi0: spi@30bb0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
				reg = <0x30bb0000 0x10000>,
				      <0x08000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
					 <&clk IMX8MQ_CLK_QSPI_ROOT>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			sdma1: dma-controller@30bd0000 {
				compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
				reg = <0x30bd0000 0x10000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
					 <&clk IMX8MQ_CLK_AHB>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			fec1: ethernet@30be0000 {
				compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
				reg = <0x30be0000 0x10000>;
				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
				         <&clk IMX8MQ_CLK_ENET1_ROOT>,
				         <&clk IMX8MQ_CLK_ENET_TIMER>,
				         <&clk IMX8MQ_CLK_ENET_REF>,
				         <&clk IMX8MQ_CLK_ENET_PHY_REF>;
				clock-names = "ipg", "ahb", "ptp",
				              "enet_clk_ref", "enet_out";
				assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
						  <&clk IMX8MQ_CLK_ENET_TIMER>,
						  <&clk IMX8MQ_CLK_ENET_REF>,
						  <&clk IMX8MQ_CLK_ENET_PHY_REF>;
				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
							 <&clk IMX8MQ_SYS2_PLL_100M>,
							 <&clk IMX8MQ_SYS2_PLL_125M>,
							 <&clk IMX8MQ_SYS2_PLL_50M>;
				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				nvmem-cells = <&fec_mac_address>;
				nvmem-cell-names = "mac-address";
				fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
				status = "disabled";
			};
		};

		noc: interconnect@32700000 {
			compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
			reg = <0x32700000 0x100000>;
			clocks = <&clk IMX8MQ_CLK_NOC>;
			fsl,ddrc = <&ddrc>;
			#interconnect-cells = <1>;
			operating-points-v2 = <&noc_opp_table>;

			noc_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-133000000 {
					opp-hz = /bits/ 64 <133333333>;
				};

				opp-400000000 {
					opp-hz = /bits/ 64 <400000000>;
				};

				opp-800000000 {
					opp-hz = /bits/ 64 <800000000>;
				};
			};
		};

		aips4: bus@32c00000 { /* AIPS4 */
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x32c00000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x32c00000 0x32c00000 0x400000>;

			irqsteer: interrupt-controller@32e2d000 {
				compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
				reg = <0x32e2d000 0x1000>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
				clock-names = "ipg";
				fsl,channel = <0>;
				fsl,num-irqs = <64>;
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		gpu: gpu@38000000 {
			compatible = "vivante,gc";
			reg = <0x38000000 0x40000>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
			         <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
			         <&clk IMX8MQ_CLK_GPU_AXI>,
			         <&clk IMX8MQ_CLK_GPU_AHB>;
			clock-names = "core", "shader", "bus", "reg";
			#cooling-cells = <2>;
			assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
			                  <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
			                  <&clk IMX8MQ_CLK_GPU_AXI>,
			                  <&clk IMX8MQ_CLK_GPU_AHB>,
			                  <&clk IMX8MQ_GPU_PLL_BYPASS>;
			assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
			                         <&clk IMX8MQ_GPU_PLL_OUT>,
			                         <&clk IMX8MQ_GPU_PLL_OUT>,
			                         <&clk IMX8MQ_GPU_PLL_OUT>,
			                         <&clk IMX8MQ_GPU_PLL>;
			assigned-clock-rates = <800000000>, <800000000>,
			                       <800000000>, <800000000>, <0>;
			power-domains = <&pgc_gpu>;
		};

		usb_dwc3_0: usb@38100000 {
			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
			reg = <0x38100000 0x10000>;
			clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
				 <&clk IMX8MQ_CLK_32K>;
			clock-names = "bus_early", "ref", "suspend";
			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
			                         <&clk IMX8MQ_SYS1_PLL_100M>;
			assigned-clock-rates = <500000000>, <100000000>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&usb3_phy0>, <&usb3_phy0>;
			phy-names = "usb2-phy", "usb3-phy";
			power-domains = <&pgc_otg1>;
			usb3-resume-missing-cas;
			status = "disabled";
		};

		usb3_phy0: usb-phy@381f0040 {
			compatible = "fsl,imx8mq-usb-phy";
			reg = <0x381f0040 0x40>;
			clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
			clock-names = "phy";
			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
			assigned-clock-rates = <100000000>;
			#phy-cells = <0>;
			status = "disabled";
		};

		usb_dwc3_1: usb@38200000 {
			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
			reg = <0x38200000 0x10000>;
			clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
				 <&clk IMX8MQ_CLK_32K>;
			clock-names = "bus_early", "ref", "suspend";
			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
			                         <&clk IMX8MQ_SYS1_PLL_100M>;
			assigned-clock-rates = <500000000>, <100000000>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&usb3_phy1>, <&usb3_phy1>;
			phy-names = "usb2-phy", "usb3-phy";
			power-domains = <&pgc_otg2>;
			usb3-resume-missing-cas;
			status = "disabled";
		};

		usb3_phy1: usb-phy@382f0040 {
			compatible = "fsl,imx8mq-usb-phy";
			reg = <0x382f0040 0x40>;
			clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
			clock-names = "phy";
			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
			assigned-clock-rates = <100000000>;
			#phy-cells = <0>;
			status = "disabled";
		};

		vpu_g1: video-codec@38300000 {
			compatible = "nxp,imx8mq-vpu-g1";
			reg = <0x38300000 0x10000>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
			power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
		};

		vpu_g2: video-codec@38310000 {
			compatible = "nxp,imx8mq-vpu-g2";
			reg = <0x38310000 0x10000>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
			power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
		};

		vpu_blk_ctrl: blk-ctrl@38320000 {
			compatible = "fsl,imx8mq-vpu-blk-ctrl";
			reg = <0x38320000 0x100>;
			power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
			power-domain-names = "bus", "g1", "g2";
			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
			clock-names = "g1", "g2";
			#power-domain-cells = <1>;
		};

		pcie0: pcie@33800000 {
			compatible = "fsl,imx8mq-pcie";
			reg = <0x33800000 0x400000>,
			      <0x1ff00000 0x80000>;
			reg-names = "dbi", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			bus-range = <0x00 0xff>;
			ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
				 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
			num-lanes = <1>;
			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
			                <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
			                <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
			                <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
			fsl,max-link-speed = <2>;
			linux,pci-domain = <0>;
			power-domains = <&pgc_pcie>;
			resets = <&src IMX8MQ_RESET_PCIEPHY>,
			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
			reset-names = "pciephy", "apps", "turnoff";
			assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
			                  <&clk IMX8MQ_CLK_PCIE1_PHY>,
			                  <&clk IMX8MQ_CLK_PCIE1_AUX>;
			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
			                         <&clk IMX8MQ_SYS2_PLL_100M>,
			                         <&clk IMX8MQ_SYS1_PLL_80M>;
			assigned-clock-rates = <250000000>, <100000000>,
			                       <10000000>;
			status = "disabled";
		};

		pcie1: pcie@33c00000 {
			compatible = "fsl,imx8mq-pcie";
			reg = <0x33c00000 0x400000>,
			      <0x27f00000 0x80000>;
			reg-names = "dbi", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
				  <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
			num-lanes = <1>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			fsl,max-link-speed = <2>;
			linux,pci-domain = <1>;
			power-domains = <&pgc_pcie>;
			resets = <&src IMX8MQ_RESET_PCIEPHY2>,
			         <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
			         <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
			reset-names = "pciephy", "apps", "turnoff";
			assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
			                  <&clk IMX8MQ_CLK_PCIE2_PHY>,
			                  <&clk IMX8MQ_CLK_PCIE2_AUX>;
			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
			                         <&clk IMX8MQ_SYS2_PLL_100M>,
			                         <&clk IMX8MQ_SYS1_PLL_80M>;
			assigned-clock-rates = <250000000>, <100000000>,
			                       <10000000>;
			status = "disabled";
		};

		gic: interrupt-controller@38800000 {
			compatible = "arm,gic-v3";
			reg = <0x38800000 0x10000>,	/* GIC Dist */
			      <0x38880000 0xc0000>,	/* GICR */
			      <0x31000000 0x2000>,	/* GICC */
			      <0x31010000 0x2000>,	/* GICV */
			      <0x31020000 0x2000>;	/* GICH */
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
		};

		ddrc: memory-controller@3d400000 {
			compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
			reg = <0x3d400000 0x400000>;
			clock-names = "core", "pll", "alt", "apb";
			clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
				 <&clk IMX8MQ_DRAM_PLL_OUT>,
				 <&clk IMX8MQ_CLK_DRAM_ALT>,
				 <&clk IMX8MQ_CLK_DRAM_APB>;
			status = "disabled";
		};

		ddr-pmu@3d800000 {
			compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
			reg = <0x3d800000 0x400000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

/dts-v1/;

#include "imx8qm.dtsi"

/ {
	model = "Freescale i.MX8QM MEK";
	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";

	chosen {
		stdout-path = &lpuart0;
	};

	cpus {
		/delete-node/ cpu-map;
		/delete-node/ cpu@100;
		/delete-node/ cpu@101;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	reg_usdhc2_vmmc: usdhc2-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "SD1_SPWR";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&iomuxc {
	pinctrl_fec1: fec1grp {
		fsl,pins = <
			IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020
			IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
			IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
			IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
			IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
			IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
			IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
			IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
			IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
			IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
			IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
			IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
			IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
			IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
		>;
	};

	pinctrl_lpuart0: lpuart0grp {
		fsl,pins = <
			IMX8QM_UART0_RX_DMA_UART0_RX				0x06000020
			IMX8QM_UART0_TX_DMA_UART0_TX				0x06000020
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK				0x06000041
			IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD				0x00000021
			IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
			IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
			IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
			IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
			IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
			IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
			IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
			IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
			IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
			IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
			IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
			IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
			IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
			IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
			IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019-2020 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

&fec1 {
	compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
};

&fec2 {
	compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
};

&usdhc1 {
	compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};

&usdhc2 {
	compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};

&usdhc3 {
	compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

&dma_subsys {
	uart4_lpcg: clock-controller@5a4a0000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5a4a0000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
			 <&dma_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
		clock-output-names = "uart4_lpcg_baud_clk",
				     "uart4_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_UART_4>;
	};
};

&lpuart0 {
	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
};

&lpuart1 {
	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
};

&lpuart2 {
	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
};

&lpuart3 {
	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
};

&i2c0 {
	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};

&i2c1 {
	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};

&i2c2 {
	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};

&i2c3 {
	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2021 NXP
 */

&jpegdec {
	compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec";
};

&jpegenc {
	compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019-2020 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

&lsio_gpio0 {
	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 0 0 6>,
		      <&iomuxc 6 7 22>,
		      <&iomuxc 28 36 4>;
};

&lsio_gpio1 {
	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 0 40 4>,
		      <&iomuxc 4 50 12>,
		      <&iomuxc 16 63 8>,
		      <&iomuxc 24 72 8>;
};

&lsio_gpio2 {
	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 0 80 4>,
		      <&iomuxc 4 85 18>,
		      <&iomuxc 22 104 10>;
};

&lsio_gpio3 {
	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 0 114 2>,
		      <&iomuxc 2 117 16>,
		      <&iomuxc 18 141 1>,
		      <&iomuxc 19 140 1>,
		      <&iomuxc 20 139 1>,
		      <&iomuxc 21 138 1>,
		      <&iomuxc 22 137 1>,
		      <&iomuxc 23 136 1>,
		      <&iomuxc 24 135 1>,
		      <&iomuxc 25 134 1>,
		      <&iomuxc 26 142 3>,
		      <&iomuxc 29 146 3>;
};

&lsio_gpio4 {
	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 0 149 3>,
		      <&iomuxc 3 153 4>,
		      <&iomuxc 7 158 6>,
		      <&iomuxc 13 165 6>,
		      <&iomuxc 19 172 8>,
		      <&iomuxc 27 198 5>;
};

&lsio_gpio5 {
	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 0 203 1>,
		      <&iomuxc 1 205 2>,
		      <&iomuxc 3 210 11>,
		      <&iomuxc 14 223 3>,
		      <&iomuxc 17 227 2>,
		      <&iomuxc 19 230 5>,
		      <&iomuxc 24 236 6>,
		      <&iomuxc 30 243 2>;
};

&lsio_gpio6 {
	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 0 245 10>,
		      <&iomuxc 10 256 12>;
};

&lsio_gpio7 {
	compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
};

&lsio_mu0 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};

&lsio_mu1 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};

&lsio_mu2 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};

&lsio_mu3 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};

&lsio_mu4 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};

&lsio_mu5 {
	compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};

&lsio_mu6 {
	compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};

&lsio_mu13 {
	compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};