code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Based on "omap4.dtsi"
 */

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
#include <dt-bindings/clock/omap5.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	compatible = "ti,omap5";
	interrupt-parent = <&wakeupgen>;
	chosen { };

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		i2c4 = &i2c5;
		mmc0 = &mmc1;
		mmc1 = &mmc2;
		mmc2 = &mmc3;
		mmc3 = &mmc4;
		mmc4 = &mmc5;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		rproc0 = &dsp;
		rproc1 = &ipu;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x0>;

			operating-points = <
				/* kHz    uV */
				1000000 1060000
				1500000 1250000
			>;

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */

			/* cooling options */
			#cooling-cells = <2>; /* min followed by max */
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x1>;

			operating-points = <
				/* kHz    uV */
				1000000 1060000
				1500000 1250000
			>;

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */

			/* cooling options */
			#cooling-cells = <2>; /* min followed by max */
		};
	};

	thermal-zones {
		#include "omap4-cpu-thermal.dtsi"
		#include "omap5-gpu-thermal.dtsi"
		#include "omap5-core-thermal.dtsi"
	};

	timer {
		compatible = "arm,armv7-timer";
		/* PPI secure/nonsecure IRQ */
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&gic>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
	};

	/*
	 * Needed early by omap4_sram_init() for barrier, do not move to l3
	 * interconnect as simple-pm-bus probes at module_init() time.
	 */
	ocmcram: sram@40300000 {
		compatible = "mmio-sram";
		reg = <0 0x40300000 0 0x20000>; /* 128k */
	};

	gic: interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0 0x48211000 0 0x1000>,
		      <0 0x48212000 0 0x2000>,
		      <0 0x48214000 0 0x2000>,
		      <0 0x48216000 0 0x2000>;
		interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0 0x48281000 0 0x1000>;
		interrupt-parent = <&gic>;
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since it will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "simple-pm-bus";
		power-domains = <&prm_core>;
		clocks = <&l3main1_clkctrl OMAP5_L3_MAIN_1_CLKCTRL 0>,
			 <&l3main2_clkctrl OMAP5_L3_MAIN_2_CLKCTRL 0>,
			 <&l3instr_clkctrl OMAP5_L3_MAIN_3_CLKCTRL 0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xc0000000>;
		dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;

		l3-noc@44000000 {
			compatible = "ti,omap5-l3-noc";
			reg = <0x44000000 0x2000>,
			      <0x44800000 0x3000>,
			      <0x45000000 0x4000>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		};

		l4_wkup: interconnect@4ae00000 {
		};

		l4_cfg: interconnect@4a000000 {
		};

		l4_per: interconnect@48000000 {
		};

		target-module@48210000 {
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			power-domains = <&prm_mpu>;
			clocks = <&mpu_clkctrl OMAP5_MPU_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x48210000 0x1f0000>;

			mpu {
				compatible = "ti,omap4-mpu";
				sram = <&ocmcram>;
			};
		};

		l4_abe: interconnect@40100000 {
		};

		target-module@50000000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x50000000 4>,
			      <0x50000010 4>,
			      <0x50000014 4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			ti,no-idle-on-init;
			clocks = <&l3main2_clkctrl OMAP5_L3_MAIN_2_GPMC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
				 <0x00000000 0x00000000 0x40000000>; /* data */

			gpmc: gpmc@50000000 {
				compatible = "ti,omap4430-gpmc";
				reg = <0x50000000 0x1000>;
				#address-cells = <2>;
				#size-cells = <1>;
				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&sdma 4>;
				dma-names = "rxtx";
				gpmc,num-cs = <8>;
				gpmc,num-waitpins = <4>;
				clock-names = "fck";
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-controller;
				#gpio-cells = <2>;
			};
		};

		target-module@55082000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x55082000 0x4>,
			      <0x55082010 0x4>,
			      <0x55082014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
			clock-names = "fck";
			resets = <&prm_core 2>;
			reset-names = "rstctrl";
			ranges = <0x0 0x55082000 0x100>;
			#size-cells = <1>;
			#address-cells = <1>;

			mmu_ipu: mmu@0 {
				compatible = "ti,omap4-iommu";
				reg = <0x0 0x100>;
				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
				#iommu-cells = <0>;
				ti,iommu-bus-err-back;
			};
		};

		dsp: dsp {
			compatible = "ti,omap5-dsp";
			ti,bootreg = <&scm_conf 0x304 0>;
			iommus = <&mmu_dsp>;
			resets = <&prm_dsp 0>;
			clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
			firmware-name = "omap5-dsp-fw.xe64T";
			mboxes = <&mailbox &mbox_dsp>;
			status = "disabled";
		};

		ipu: ipu@55020000 {
			compatible = "ti,omap5-ipu";
			reg = <0x55020000 0x10000>;
			reg-names = "l2ram";
			iommus = <&mmu_ipu>;
			resets = <&prm_core 0>, <&prm_core 1>;
			clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
			firmware-name = "omap5-ipu-fw.xem4";
			mboxes = <&mailbox &mbox_ipu>;
			status = "disabled";
		};

		target-module@4e000000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x4e000000 0x4>,
			      <0x4e000010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ranges = <0x0 0x4e000000 0x2000000>;
			#size-cells = <1>;
			#address-cells = <1>;

			dmm@0 {
				compatible = "ti,omap5-dmm";
				reg = <0 0x800>;
				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		target-module@4c000000 {
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			reg = <0x4c000000 0x4>;
			reg-names = "rev";
			clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>;
			clock-names = "fck";
			ti,no-idle;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4c000000 0x1000000>;

			emif1: emif@0 {
				compatible = "ti,emif-4d5";
				reg = <0 0x400>;
				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
				phy-type = <2>; /* DDR PHY type: Intelli PHY */
				hw-caps-read-idle-ctrl;
				hw-caps-ll-interface;
				hw-caps-temp-alert;
			};
		};

		target-module@4d000000 {
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			reg = <0x4d000000 0x4>;
			reg-names = "rev";
			clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>;
			clock-names = "fck";
			ti,no-idle;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4d000000 0x1000000>;

			emif2: emif@0 {
				compatible = "ti,emif-4d5";
				reg = <0 0x400>;
				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
				phy-type = <2>; /* DDR PHY type: Intelli PHY */
				hw-caps-read-idle-ctrl;
				hw-caps-ll-interface;
				hw-caps-temp-alert;
			};
		};

		aes1_target: target-module@4b501000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x4b501080 0x4>,
			      <0x4b501084 0x4>,
			      <0x4b501088 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
			clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4b501000 0x1000>;

			aes1: aes@0 {
				compatible = "ti,omap4-aes";
				reg = <0 0xa0>;
				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&sdma 111>, <&sdma 110>;
				dma-names = "tx", "rx";
			};
		};

		aes2_target: target-module@4b701000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x4b701080 0x4>,
			      <0x4b701084 0x4>,
			      <0x4b701088 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
			clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4b701000 0x1000>;

			aes2: aes@0 {
				compatible = "ti,omap4-aes";
				reg = <0 0xa0>;
				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&sdma 114>, <&sdma 113>;
				dma-names = "tx", "rx";
			};
		};

		sham_target: target-module@4b100000 {
			compatible = "ti,sysc-omap3-sham", "ti,sysc";
			reg = <0x4b100100 0x4>,
			      <0x4b100110 0x4>,
			      <0x4b100114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
			clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4b100000 0x1000>;

			sham: sham@0 {
				compatible = "ti,omap4-sham";
				reg = <0 0x300>;
				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&sdma 119>;
				dma-names = "rx";
			};
		};

		bandgap: bandgap@4a0021e0 {
			reg = <0x4a0021e0 0xc
			       0x4a00232c 0xc
			       0x4a002380 0x2c
			       0x4a0023C0 0x3c>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			compatible = "ti,omap5430-bandgap";

			#thermal-sensor-cells = <1>;
		};

		target-module@56000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x5600fe00 0x4>,
			      <0x5600fe10 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x56000000 0x2000000>;

			/*
			 * Closed source PowerVR driver, no child device
			 * binding or driver in mainline
			 */
		};

		target-module@58000000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x58000000 4>,
			      <0x58000014 4>;
			reg-names = "rev", "syss";
			ti,syss-mask = <1>;
			power-domains = <&prm_dss>;
			clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
				 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
				 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
				 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
			clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x58000000 0x1000000>;

			dss: dss@0 {
				compatible = "ti,omap5-dss";
				reg = <0 0x80>;
				status = "disabled";
				clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
				clock-names = "fck";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0 0x1000000>;

				target-module@1000 {
					compatible = "ti,sysc-omap2", "ti,sysc";
					reg = <0x1000 0x4>,
					      <0x1010 0x4>,
					      <0x1014 0x4>;
					reg-names = "rev", "sysc", "syss";
					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
							<SYSC_IDLE_NO>,
							<SYSC_IDLE_SMART>;
					ti,sysc-midle = <SYSC_IDLE_FORCE>,
							<SYSC_IDLE_NO>,
							<SYSC_IDLE_SMART>;
					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
							 SYSC_OMAP2_ENAWAKEUP |
							 SYSC_OMAP2_SOFTRESET |
							 SYSC_OMAP2_AUTOIDLE)>;
					ti,syss-mask = <1>;
					clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
					clock-names = "fck";
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0 0x1000 0x1000>;

					dispc@0 {
						compatible = "ti,omap5-dispc";
						reg = <0 0x1000>;
						interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
						clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
						clock-names = "fck";
					};
				};

				target-module@2000 {
					compatible = "ti,sysc-omap2", "ti,sysc";
					reg = <0x2000 0x4>,
					      <0x2010 0x4>,
					      <0x2014 0x4>;
					reg-names = "rev", "sysc", "syss";
					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
							<SYSC_IDLE_NO>,
							<SYSC_IDLE_SMART>;
					ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
							 SYSC_OMAP2_AUTOIDLE)>;
					ti,syss-mask = <1>;
					clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
					clock-names = "fck";
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0 0x2000 0x1000>;

					rfbi: encoder@0  {
						compatible = "ti,omap5-rfbi";
						reg = <0 0x100>;
						status = "disabled";
						clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
						clock-names = "fck", "ick";
					};
				};

				target-module@4000 {
					compatible = "ti,sysc-omap2", "ti,sysc";
					reg = <0x4000 0x4>,
					      <0x4010 0x4>,
					      <0x4014 0x4>;
					reg-names = "rev", "sysc", "syss";
					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
							<SYSC_IDLE_NO>,
							<SYSC_IDLE_SMART>;
					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
							 SYSC_OMAP2_ENAWAKEUP |
							 SYSC_OMAP2_SOFTRESET |
							 SYSC_OMAP2_AUTOIDLE)>;
					ti,syss-mask = <1>;
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0 0x4000 0x1000>;

					dsi1: encoder@0 {
						compatible = "ti,omap5-dsi";
						reg = <0 0x200>,
						      <0x200 0x40>,
						      <0x300 0x40>;
						reg-names = "proto", "phy", "pll";
						interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
						status = "disabled";
						clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
							 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
						clock-names = "fck", "sys_clk";

						#address-cells = <1>;
						#size-cells = <0>;
					};
				};

				target-module@9000 {
					compatible = "ti,sysc-omap2", "ti,sysc";
					reg = <0x9000 0x4>,
					      <0x9010 0x4>,
					      <0x9014 0x4>;
					reg-names = "rev", "sysc", "syss";
					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
							<SYSC_IDLE_NO>,
							<SYSC_IDLE_SMART>;
					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
							 SYSC_OMAP2_ENAWAKEUP |
							 SYSC_OMAP2_SOFTRESET |
							 SYSC_OMAP2_AUTOIDLE)>;
					ti,syss-mask = <1>;
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0 0x9000 0x1000>;

					dsi2: encoder@0 {
						compatible = "ti,omap5-dsi";
						reg = <0 0x200>,
						      <0x200 0x40>,
						      <0x300 0x40>;
						reg-names = "proto", "phy", "pll";
						interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
						status = "disabled";
						clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
							 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
						clock-names = "fck", "sys_clk";

						#address-cells = <1>;
						#size-cells = <0>;
					};
				};

				target-module@40000 {
					compatible = "ti,sysc-omap4", "ti,sysc";
					reg = <0x40000 0x4>,
					      <0x40010 0x4>;
					reg-names = "rev", "sysc";
					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
							<SYSC_IDLE_NO>,
							<SYSC_IDLE_SMART>,
							<SYSC_IDLE_SMART_WKUP>;
					ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
					clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
						 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
					clock-names = "fck", "dss_clk";
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0 0x40000 0x40000>;

					hdmi: encoder@0 {
						compatible = "ti,omap5-hdmi";
						reg = <0 0x200>,
						      <0x200 0x80>,
						      <0x300 0x80>,
						      <0x20000 0x19000>;
						reg-names = "wp", "pll", "phy", "core";
						interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
						status = "disabled";
						clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
							 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
						clock-names = "fck", "sys_clk";
						dmas = <&sdma 76>;
						dma-names = "audio_tx";
					};
				};
			};
		};

		abb_mpu: regulator-abb-mpu {
			compatible = "ti,abb-v2";
			regulator-name = "abb_mpu";
			#address-cells = <0>;
			#size-cells = <0>;
			clocks = <&sys_clkin>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
			      <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
			reg-names = "base-address", "int-address",
				    "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x80>;
			/* LDOVBBMPU_MUX_CTRL */
			ti,ldovbb-override-mask = <0x400>;
			/* LDOVBBMPU_VSET_OUT */
			ti,ldovbb-vset-mask = <0x1F>;

			/*
			 * NOTE: only FBB mode used but actual vset will
			 * determine final biasing
			 */
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
			1060000		0	0x0	0 0x02000000 0x01F00000
			1250000		0	0x4	0 0x02000000 0x01F00000
			>;
		};

		abb_mm: regulator-abb-mm {
			compatible = "ti,abb-v2";
			regulator-name = "abb_mm";
			#address-cells = <0>;
			#size-cells = <0>;
			clocks = <&sys_clkin>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
			      <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
			reg-names = "base-address", "int-address",
				    "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x80000000>;
			/* LDOVBBMM_MUX_CTRL */
			ti,ldovbb-override-mask = <0x400>;
			/* LDOVBBMM_VSET_OUT */
			ti,ldovbb-vset-mask = <0x1F>;

			/*
			 * NOTE: only FBB mode used but actual vset will
			 * determine final biasing
			 */
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
			1025000		0	0x0	0 0x02000000 0x01F00000
			1120000		0	0x4	0 0x02000000 0x01F00000
			>;
		};
	};
};

&cpu_thermal {
	polling-delay = <500>; /* milliseconds */
	coefficients = <65 (-1791)>;
};

#include "omap5-l4.dtsi"
#include "omap54xx-clocks.dtsi"

&gpu_thermal {
	coefficients = <117 (-2992)>;
};

&core_thermal {
	coefficients = <0 2000>;
};

#include "omap5-l4-abe.dtsi"
#include "omap54xx-clocks.dtsi"

&prm {
	prm_mpu: prm@300 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x300 0x100>;
		#power-domain-cells = <0>;
	};

	prm_dsp: prm@400 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x400 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_abe: prm@500 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x500 0x100>;
		#power-domain-cells = <0>;
	};

	prm_coreaon: prm@600 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x600 0x100>;
		#power-domain-cells = <0>;
	};

	prm_core: prm@700 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x700 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_iva: prm@1200 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x1200 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_cam: prm@1300 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x1300 0x100>;
		#power-domain-cells = <0>;
	};

	prm_dss: prm@1400 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x1400 0x100>;
		#power-domain-cells = <0>;
	};

	prm_gpu: prm@1500 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x1500 0x100>;
		#power-domain-cells = <0>;
	};

	prm_l3init: prm@1600 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x1600 0x100>;
		#power-domain-cells = <0>;
	};

	prm_custefuse: prm@1700 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x1700 0x100>;
		#power-domain-cells = <0>;
	};

	prm_wkupaon: prm@1800 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x1800 0x100>;
		#power-domain-cells = <0>;
	};

	prm_emu: prm@1a00 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x1a00 0x100>;
		#power-domain-cells = <0>;
	};

	prm_device: prm@1c00 {
		compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
		reg = <0x1c00 0x100>;
		#reset-cells = <1>;
	};
};

/* Preferred always-on timer for clockevent */
&timer1_target {
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
		assigned-clock-parents = <&sys_32k_ck>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP5 clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 */
&cm_core_aon_clocks {
	pad_clks_src_ck: pad_clks_src_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "pad_clks_src_ck";
		clock-frequency = <12000000>;
	};

	pad_clks_ck: pad_clks_ck@108 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "pad_clks_ck";
		clocks = <&pad_clks_src_ck>;
		ti,bit-shift = <8>;
		reg = <0x0108>;
	};

	secure_32k_clk_src_ck: secure_32k_clk_src_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "secure_32k_clk_src_ck";
		clock-frequency = <32768>;
	};

	slimbus_src_clk: slimbus_src_clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "slimbus_src_clk";
		clock-frequency = <12000000>;
	};

	slimbus_clk: slimbus_clk@108 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "slimbus_clk";
		clocks = <&slimbus_src_clk>;
		ti,bit-shift = <10>;
		reg = <0x0108>;
	};

	sys_32k_ck: sys_32k_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "sys_32k_ck";
		clock-frequency = <32768>;
	};

	virt_12000000_ck: virt_12000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_12000000_ck";
		clock-frequency = <12000000>;
	};

	virt_13000000_ck: virt_13000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_13000000_ck";
		clock-frequency = <13000000>;
	};

	virt_16800000_ck: virt_16800000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_16800000_ck";
		clock-frequency = <16800000>;
	};

	virt_19200000_ck: virt_19200000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_19200000_ck";
		clock-frequency = <19200000>;
	};

	virt_26000000_ck: virt_26000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_26000000_ck";
		clock-frequency = <26000000>;
	};

	virt_27000000_ck: virt_27000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_27000000_ck";
		clock-frequency = <27000000>;
	};

	virt_38400000_ck: virt_38400000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_38400000_ck";
		clock-frequency = <38400000>;
	};

	xclk60mhsp1_ck: xclk60mhsp1_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "xclk60mhsp1_ck";
		clock-frequency = <60000000>;
	};

	xclk60mhsp2_ck: xclk60mhsp2_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "xclk60mhsp2_ck";
		clock-frequency = <60000000>;
	};

	dpll_abe_ck: dpll_abe_ck@1e0 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-m4xen-clock";
		clock-output-names = "dpll_abe_ck";
		clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
		reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
	};

	dpll_abe_x2_ck: dpll_abe_x2_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clock-output-names = "dpll_abe_x2_ck";
		clocks = <&dpll_abe_ck>;
	};

	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_abe_m2x2_ck";
		clocks = <&dpll_abe_x2_ck>;
		ti,max-div = <31>;
		reg = <0x01f0>;
		ti,index-starts-at-one;
	};

	abe_24m_fclk: abe_24m_fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "abe_24m_fclk";
		clocks = <&dpll_abe_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <8>;
	};

	abe_clk: abe_clk@108 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "abe_clk";
		clocks = <&dpll_abe_m2x2_ck>;
		ti,max-div = <4>;
		reg = <0x0108>;
		ti,index-power-of-two;
	};

	abe_iclk: abe_iclk@528 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "abe_iclk";
		clocks = <&aess_fclk>;
		ti,bit-shift = <24>;
		reg = <0x0528>;
		ti,dividers = <2>, <1>;
	};

	abe_lp_clk_div: abe_lp_clk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "abe_lp_clk_div";
		clocks = <&dpll_abe_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <16>;
	};

	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_abe_m3x2_ck";
		clocks = <&dpll_abe_x2_ck>;
		ti,max-div = <31>;
		reg = <0x01f4>;
		ti,index-starts-at-one;
	};

	dpll_core_byp_mux: dpll_core_byp_mux@12c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_core_byp_mux";
		clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
		ti,bit-shift = <23>;
		reg = <0x012c>;
	};

	dpll_core_ck: dpll_core_ck@120 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-core-clock";
		clock-output-names = "dpll_core_ck";
		clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
	};

	dpll_core_x2_ck: dpll_core_x2_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clock-output-names = "dpll_core_x2_ck";
		clocks = <&dpll_core_ck>;
	};

	dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h21x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0150>;
		ti,index-starts-at-one;
	};

	c2c_fclk: c2c_fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "c2c_fclk";
		clocks = <&dpll_core_h21x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	c2c_iclk: c2c_iclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "c2c_iclk";
		clocks = <&c2c_fclk>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h11x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0138>;
		ti,index-starts-at-one;
	};

	dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h12x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x013c>;
		ti,index-starts-at-one;
	};

	dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h13x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0140>;
		ti,index-starts-at-one;
	};

	dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h14x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0144>;
		ti,index-starts-at-one;
	};

	dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h22x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0154>;
		ti,index-starts-at-one;
	};

	dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h23x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0158>;
		ti,index-starts-at-one;
	};

	dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_h24x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <63>;
		reg = <0x015c>;
		ti,index-starts-at-one;
	};

	dpll_core_m2_ck: dpll_core_m2_ck@130 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_m2_ck";
		clocks = <&dpll_core_ck>;
		ti,max-div = <31>;
		reg = <0x0130>;
		ti,index-starts-at-one;
	};

	dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_m3x2_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <31>;
		reg = <0x0134>;
		ti,index-starts-at-one;
	};

	iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "iva_dpll_hs_clk_div";
		clocks = <&dpll_core_h12x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_iva_byp_mux";
		clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
		ti,bit-shift = <23>;
		reg = <0x01ac>;
	};

	dpll_iva_ck: dpll_iva_ck@1a0 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clock-output-names = "dpll_iva_ck";
		clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
		assigned-clocks = <&dpll_iva_ck>;
		assigned-clock-rates = <1165000000>;
	};

	dpll_iva_x2_ck: dpll_iva_x2_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clock-output-names = "dpll_iva_x2_ck";
		clocks = <&dpll_iva_ck>;
	};

	dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_iva_h11x2_ck";
		clocks = <&dpll_iva_x2_ck>;
		ti,max-div = <63>;
		reg = <0x01b8>;
		ti,index-starts-at-one;
		assigned-clocks = <&dpll_iva_h11x2_ck>;
		assigned-clock-rates = <465920000>;
	};

	dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_iva_h12x2_ck";
		clocks = <&dpll_iva_x2_ck>;
		ti,max-div = <63>;
		reg = <0x01bc>;
		ti,index-starts-at-one;
		assigned-clocks = <&dpll_iva_h12x2_ck>;
		assigned-clock-rates = <388300000>;
	};

	mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "mpu_dpll_hs_clk_div";
		clocks = <&dpll_core_h12x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_mpu_ck: dpll_mpu_ck@160 {
		#clock-cells = <0>;
		compatible = "ti,omap5-mpu-dpll-clock";
		clock-output-names = "dpll_mpu_ck";
		clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
	};

	dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_mpu_m2_ck";
		clocks = <&dpll_mpu_ck>;
		ti,max-div = <31>;
		reg = <0x0170>;
		ti,index-starts-at-one;
	};

	per_dpll_hs_clk_div: per_dpll_hs_clk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "per_dpll_hs_clk_div";
		clocks = <&dpll_abe_m3x2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "usb_dpll_hs_clk_div";
		clocks = <&dpll_abe_m3x2_ck>;
		clock-mult = <1>;
		clock-div = <3>;
	};

	l3_iclk_div: l3_iclk_div@100 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "l3_iclk_div";
		ti,max-div = <2>;
		ti,bit-shift = <4>;
		reg = <0x100>;
		clocks = <&dpll_core_h12x2_ck>;
		ti,index-power-of-two;
	};

	gpu_l3_iclk: gpu_l3_iclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "gpu_l3_iclk";
		clocks = <&l3_iclk_div>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	l4_root_clk_div: l4_root_clk_div@100 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "l4_root_clk_div";
		ti,max-div = <2>;
		ti,bit-shift = <8>;
		reg = <0x100>;
		clocks = <&l3_iclk_div>;
		ti,index-power-of-two;
	};

	slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "slimbus1_slimbus_clk";
		clocks = <&slimbus_clk>;
		ti,bit-shift = <11>;
		reg = <0x0560>;
	};

	aess_fclk: aess_fclk@528 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "aess_fclk";
		clocks = <&abe_clk>;
		ti,bit-shift = <24>;
		ti,max-div = <2>;
		reg = <0x0528>;
	};

	mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "mcasp_sync_mux_ck";
		clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
		ti,bit-shift = <26>;
		reg = <0x0540>;
	};

	mcasp_gfclk: mcasp_gfclk@540 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "mcasp_gfclk";
		clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
		ti,bit-shift = <24>;
		reg = <0x0540>;
	};

	dummy_ck: dummy_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "dummy_ck";
		clock-frequency = <0>;
	};
};
&prm_clocks {
	sys_clkin: sys_clkin@110 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "sys_clkin";
		clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
		reg = <0x0110>;
		ti,index-starts-at-one;
	};

	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "abe_dpll_bypass_clk_mux";
		clocks = <&sys_clkin>, <&sys_32k_ck>;
		reg = <0x0108>;
	};

	abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "abe_dpll_clk_mux";
		clocks = <&sys_clkin>, <&sys_32k_ck>;
		reg = <0x010c>;
	};

	custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "custefuse_sys_gfclk_div";
		clocks = <&sys_clkin>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	dss_syc_gfclk_div: dss_syc_gfclk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "dss_syc_gfclk_div";
		clocks = <&sys_clkin>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "wkupaon_iclk_mux";
		clocks = <&sys_clkin>, <&abe_lp_clk_div>;
		reg = <0x0108>;
	};

	l3instr_ts_gclk_div: l3instr_ts_gclk_div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "l3instr_ts_gclk_div";
		clocks = <&wkupaon_iclk_mux>;
		clock-mult = <1>;
		clock-div = <1>;
	};
};

&cm_core_clocks {

	dpll_per_byp_mux: dpll_per_byp_mux@14c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_per_byp_mux";
		clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
		ti,bit-shift = <23>;
		reg = <0x014c>;
	};

	dpll_per_ck: dpll_per_ck@140 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clock-output-names = "dpll_per_ck";
		clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
	};

	dpll_per_x2_ck: dpll_per_x2_ck {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-x2-clock";
		clock-output-names = "dpll_per_x2_ck";
		clocks = <&dpll_per_ck>;
	};

	dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_h11x2_ck";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0158>;
		ti,index-starts-at-one;
	};

	dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_h12x2_ck";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <63>;
		reg = <0x015c>;
		ti,index-starts-at-one;
	};

	dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_h14x2_ck";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <63>;
		reg = <0x0164>;
		ti,index-starts-at-one;
	};

	dpll_per_m2_ck: dpll_per_m2_ck@150 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_m2_ck";
		clocks = <&dpll_per_ck>;
		ti,max-div = <31>;
		reg = <0x0150>;
		ti,index-starts-at-one;
	};

	dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_m2x2_ck";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <31>;
		reg = <0x0150>;
		ti,index-starts-at-one;
	};

	dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_m3x2_ck";
		clocks = <&dpll_per_x2_ck>;
		ti,max-div = <31>;
		reg = <0x0154>;
		ti,index-starts-at-one;
	};

	dpll_unipro1_ck: dpll_unipro1_ck@200 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clock-output-names = "dpll_unipro1_ck";
		clocks = <&sys_clkin>, <&sys_clkin>;
		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
	};

	dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "dpll_unipro1_clkdcoldo";
		clocks = <&dpll_unipro1_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_unipro1_m2_ck";
		clocks = <&dpll_unipro1_ck>;
		ti,max-div = <127>;
		reg = <0x0210>;
		ti,index-starts-at-one;
	};

	dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-clock";
		clock-output-names = "dpll_unipro2_ck";
		clocks = <&sys_clkin>, <&sys_clkin>;
		reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
	};

	dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "dpll_unipro2_clkdcoldo";
		clocks = <&dpll_unipro2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_unipro2_m2_ck";
		clocks = <&dpll_unipro2_ck>;
		ti,max-div = <127>;
		reg = <0x01d0>;
		ti,index-starts-at-one;
	};

	dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "dpll_usb_byp_mux";
		clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
		ti,bit-shift = <23>;
		reg = <0x018c>;
	};

	dpll_usb_ck: dpll_usb_ck@180 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-j-type-clock";
		clock-output-names = "dpll_usb_ck";
		clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
	};

	dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "dpll_usb_clkdcoldo";
		clocks = <&dpll_usb_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_usb_m2_ck";
		clocks = <&dpll_usb_ck>;
		ti,max-div = <127>;
		reg = <0x0190>;
		ti,index-starts-at-one;
	};

	func_128m_clk: func_128m_clk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "func_128m_clk";
		clocks = <&dpll_per_h11x2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	func_12m_fclk: func_12m_fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "func_12m_fclk";
		clocks = <&dpll_per_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <16>;
	};

	func_24m_clk: func_24m_clk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "func_24m_clk";
		clocks = <&dpll_per_m2_ck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	func_48m_fclk: func_48m_fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "func_48m_fclk";
		clocks = <&dpll_per_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	func_96m_fclk: func_96m_fclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "func_96m_fclk";
		clocks = <&dpll_per_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	l3init_60m_fclk: l3init_60m_fclk@104 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "l3init_60m_fclk";
		clocks = <&dpll_usb_m2_ck>;
		reg = <0x0104>;
		ti,dividers = <1>, <8>;
	};

	iss_ctrlclk: iss_ctrlclk@1320 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "iss_ctrlclk";
		clocks = <&func_96m_fclk>;
		ti,bit-shift = <8>;
		reg = <0x1320>;
	};

	lli_txphy_clk: lli_txphy_clk@f20 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "lli_txphy_clk";
		clocks = <&dpll_unipro1_clkdcoldo>;
		ti,bit-shift = <8>;
		reg = <0x0f20>;
	};

	lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "lli_txphy_ls_clk";
		clocks = <&dpll_unipro1_m2_ck>;
		ti,bit-shift = <9>;
		reg = <0x0f20>;
	};

	usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "usb_phy_cm_clk32k";
		clocks = <&sys_32k_ck>;
		ti,bit-shift = <8>;
		reg = <0x0640>;
	};

	fdif_fclk: fdif_fclk@1328 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "fdif_fclk";
		clocks = <&dpll_per_h11x2_ck>;
		ti,bit-shift = <24>;
		ti,max-div = <2>;
		reg = <0x1328>;
	};

	gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "gpu_core_gclk_mux";
		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
		ti,bit-shift = <24>;
		reg = <0x1520>;
	};

	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "gpu_hyd_gclk_mux";
		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
		ti,bit-shift = <25>;
		reg = <0x1520>;
	};

	hsi_fclk: hsi_fclk@1638 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "hsi_fclk";
		clocks = <&dpll_per_m2x2_ck>;
		ti,bit-shift = <24>;
		ti,max-div = <2>;
		reg = <0x1638>;
	};
};

&cm_core_clockdomains {
	l3init_clkdm: l3init_clkdm {
		compatible = "ti,clockdomain";
		clock-output-names = "l3init_clkdm";
		clocks = <&dpll_usb_ck>;
	};
};

&scrm_clocks {
	auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clock-output-names = "auxclk0_src_gate_ck";
		clocks = <&dpll_core_m3x2_ck>;
		ti,bit-shift = <8>;
		reg = <0x0310>;
	};

	auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clock-output-names = "auxclk0_src_mux_ck";
		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
		ti,bit-shift = <1>;
		reg = <0x0310>;
	};

	auxclk0_src_ck: auxclk0_src_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clock-output-names = "auxclk0_src_ck";
		clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
	};

	auxclk0_ck: auxclk0_ck@310 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "auxclk0_ck";
		clocks = <&auxclk0_src_ck>;
		ti,bit-shift = <16>;
		ti,max-div = <16>;
		reg = <0x0310>;
	};

	auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clock-output-names = "auxclk1_src_gate_ck";
		clocks = <&dpll_core_m3x2_ck>;
		ti,bit-shift = <8>;
		reg = <0x0314>;
	};

	auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clock-output-names = "auxclk1_src_mux_ck";
		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
		ti,bit-shift = <1>;
		reg = <0x0314>;
	};

	auxclk1_src_ck: auxclk1_src_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clock-output-names = "auxclk1_src_ck";
		clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
	};

	auxclk1_ck: auxclk1_ck@314 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "auxclk1_ck";
		clocks = <&auxclk1_src_ck>;
		ti,bit-shift = <16>;
		ti,max-div = <16>;
		reg = <0x0314>;
	};

	auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clock-output-names = "auxclk2_src_gate_ck";
		clocks = <&dpll_core_m3x2_ck>;
		ti,bit-shift = <8>;
		reg = <0x0318>;
	};

	auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clock-output-names = "auxclk2_src_mux_ck";
		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
		ti,bit-shift = <1>;
		reg = <0x0318>;
	};

	auxclk2_src_ck: auxclk2_src_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clock-output-names = "auxclk2_src_ck";
		clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
	};

	auxclk2_ck: auxclk2_ck@318 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "auxclk2_ck";
		clocks = <&auxclk2_src_ck>;
		ti,bit-shift = <16>;
		ti,max-div = <16>;
		reg = <0x0318>;
	};

	auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clock-output-names = "auxclk3_src_gate_ck";
		clocks = <&dpll_core_m3x2_ck>;
		ti,bit-shift = <8>;
		reg = <0x031c>;
	};

	auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clock-output-names = "auxclk3_src_mux_ck";
		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
		ti,bit-shift = <1>;
		reg = <0x031c>;
	};

	auxclk3_src_ck: auxclk3_src_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clock-output-names = "auxclk3_src_ck";
		clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
	};

	auxclk3_ck: auxclk3_ck@31c {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "auxclk3_ck";
		clocks = <&auxclk3_src_ck>;
		ti,bit-shift = <16>;
		ti,max-div = <16>;
		reg = <0x031c>;
	};

	auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clock-output-names = "auxclk4_src_gate_ck";
		clocks = <&dpll_core_m3x2_ck>;
		ti,bit-shift = <8>;
		reg = <0x0320>;
	};

	auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clock-output-names = "auxclk4_src_mux_ck";
		clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
		ti,bit-shift = <1>;
		reg = <0x0320>;
	};

	auxclk4_src_ck: auxclk4_src_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clock-output-names = "auxclk4_src_ck";
		clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
	};

	auxclk4_ck: auxclk4_ck@320 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "auxclk4_ck";
		clocks = <&auxclk4_src_ck>;
		ti,bit-shift = <16>;
		ti,max-div = <16>;
		reg = <0x0320>;
	};

	auxclkreq0_ck: auxclkreq0_ck@210 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "auxclkreq0_ck";
		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
		ti,bit-shift = <2>;
		reg = <0x0210>;
	};

	auxclkreq1_ck: auxclkreq1_ck@214 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "auxclkreq1_ck";
		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
		ti,bit-shift = <2>;
		reg = <0x0214>;
	};

	auxclkreq2_ck: auxclkreq2_ck@218 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "auxclkreq2_ck";
		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
		ti,bit-shift = <2>;
		reg = <0x0218>;
	};

	auxclkreq3_ck: auxclkreq3_ck@21c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "auxclkreq3_ck";
		clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
		ti,bit-shift = <2>;
		reg = <0x021c>;
	};
};

&cm_core_aon {
	mpu_cm: mpu_cm@300 {
		compatible = "ti,omap4-cm";
		clock-output-names = "mpu_cm";
		reg = <0x300 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x300 0x100>;

		mpu_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "mpu_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};
	};

	dsp_cm: dsp_cm@400 {
		compatible = "ti,omap4-cm";
		clock-output-names = "dsp_cm";
		reg = <0x400 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x400 0x100>;

		dsp_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "dsp_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};
	};

	abe_cm: abe_cm@500 {
		compatible = "ti,omap4-cm";
		clock-output-names = "abe_cm";
		reg = <0x500 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x500 0x100>;

		abe_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "abe_clkctrl";
			reg = <0x20 0x64>;
			#clock-cells = <2>;
		};
	};

};

&cm_core {
	l3main1_cm: l3main1_cm@700 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l3main1_cm";
		reg = <0x700 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x700 0x100>;

		l3main1_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "l3main1_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};
	};

	l3main2_cm: l3main2_cm@800 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l3main2_cm";
		reg = <0x800 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x800 0x100>;

		l3main2_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "l3main2_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};
	};

	ipu_cm: ipu_cm@900 {
		compatible = "ti,omap4-cm";
		clock-output-names = "ipu_cm";
		reg = <0x900 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x900 0x100>;

		ipu_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "ipu_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};
	};

	dma_cm: dma_cm@a00 {
		compatible = "ti,omap4-cm";
		clock-output-names = "dma_cm";
		reg = <0xa00 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xa00 0x100>;

		dma_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "dma_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};
	};

	emif_cm: emif_cm@b00 {
		compatible = "ti,omap4-cm";
		clock-output-names = "emif_cm";
		reg = <0xb00 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xb00 0x100>;

		emif_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "emif_clkctrl";
			reg = <0x20 0x1c>;
			#clock-cells = <2>;
		};
	};

	l4cfg_cm: l4cfg_cm@d00 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l4cfg_cm";
		reg = <0xd00 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xd00 0x100>;

		l4cfg_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4cfg_clkctrl";
			reg = <0x20 0x14>;
			#clock-cells = <2>;
		};
	};

	l3instr_cm: l3instr_cm@e00 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l3instr_cm";
		reg = <0xe00 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xe00 0x100>;

		l3instr_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "l3instr_clkctrl";
			reg = <0x20 0xc>;
			#clock-cells = <2>;
		};
	};

	l4per_cm: clock@1000 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l4per_cm";
		reg = <0x1000 0x200>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1000 0x200>;

		l4per_clkctrl: clock@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4per_clkctrl";
			reg = <0x20 0x15c>;
			#clock-cells = <2>;
		};

		l4sec_clkctrl: clock@1a0 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4sec_clkctrl";
			reg = <0x1a0 0x3c>;
			#clock-cells = <2>;
		};
	};

	dss_cm: dss_cm@1400 {
		compatible = "ti,omap4-cm";
		clock-output-names = "dss_cm";
		reg = <0x1400 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1400 0x100>;

		dss_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "dss_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};
	};

	gpu_cm: gpu_cm@1500 {
		compatible = "ti,omap4-cm";
		clock-output-names = "gpu_cm";
		reg = <0x1500 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1500 0x100>;

		gpu_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "gpu_clkctrl";
			reg = <0x20 0x4>;
			#clock-cells = <2>;
		};
	};

	l3init_cm: l3init_cm@1600 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l3init_cm";
		reg = <0x1600 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1600 0x100>;

		l3init_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "l3init_clkctrl";
			reg = <0x20 0xd4>;
			#clock-cells = <2>;
		};
	};
};

&prm {
	wkupaon_cm: wkupaon_cm@1900 {
		compatible = "ti,omap4-cm";
		clock-output-names = "wkupaon_cm";
		reg = <0x1900 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x1900 0x100>;

		wkupaon_clkctrl: clk@20 {
			compatible = "ti,clkctrl";
			clock-output-names = "wkupaon_clkctrl";
			reg = <0x20 0x5c>;
			#clock-cells = <2>;
		};
	};
};

&scm_wkup_pad_conf_clocks {
	fref_xtal_ck: fref_xtal_ck {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "fref_xtal_ck";
		clocks = <&sys_clkin>;
		ti,bit-shift = <28>;
		reg = <0x14>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2020 Bytedance.
 */

partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	u-boot@0 {
		reg = <0x0 0xe0000>; // 896KB
		label = "alt-u-boot";
	};

	u-boot-env@e0000 {
		reg = <0xe0000 0x20000>; // 128KB
		label = "alt-u-boot-env";
	};

	kernel@100000 {
		reg = <0x100000 0x900000>; // 9MB
		label = "alt-kernel";
	};

	rofs@a00000 {
		reg = <0xa00000 0x2000000>; // 32MB
		label = "alt-rofs";
	};

	rwfs@6000000 {
		reg = <0x2a00000 0x1600000>; // 22MB
		label = "alt-rwfs";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2020 Bytedance.
 */

partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	u-boot@0 {
		reg = <0x0 0xe0000>; // 896KB
		label = "u-boot";
	};

	u-boot-env@e0000 {
		reg = <0xe0000 0x20000>; // 128KB
		label = "u-boot-env";
	};

	kernel@100000 {
		reg = <0x100000 0x900000>; // 9MB
		label = "kernel";
	};

	rofs@a00000 {
		reg = <0xa00000 0x2000000>; // 32MB
		label = "rofs";
	};

	rwfs@2a00000 {
		reg = <0x2a00000 0x1600000>; // 22MB
		label = "rwfs";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+

partitions {
	compatible = "fixed-partitions";
	#address-cells = <1>;
	#size-cells = <1>;

	u-boot@0 {
		reg = <0x0 0x60000>;
		label = "u-boot";
	};

	u-boot-env@60000 {
		reg = <0x60000 0x20000>;
		label = "u-boot-env";
	};

	kernel@80000 {
		reg = <0x80000 0x440000>;
		label = "kernel";
	};

	rofs@4c0000 {
		reg = <0x4c0000 0x1740000>;
		label = "rofs";
	};

	rwfs@1c00000 {
		reg = <0x1c00000 0x400000>;
		label = "rwfs";
	};
};


code:
/*
 * Device Tree file for Buffalo/Revogear Kurobox Pro
 *
 * Copyright (C) 2016
 * Roger Shimizu <rogershimizu@gmail.com>
 *
 * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c
 * Copyright (C) Ronen Shitrit <rshitrit@marvell.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include "orion5x-linkstation.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Buffalo/Revogear Kurobox Pro";
	compatible = "buffalo,kurobox-pro", "marvell,orion5x-88f5182", "marvell,orion5x";

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
				 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
				 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>,
				 <MBUS_ID(0x01, 0x1e) 0 0xfc000000 0x1000000>;
	};

	memory { /* 128 MB */
		device_type = "memory";
		reg = <0x00000000 0x8000000>;
	};
};

&pinctrl {
	pmx_power_hdd: pmx-power-hdd {
		marvell,pins = "mpp1";
		marvell,function = "gpio";
	};

	pmx_power_usb: pmx-power-usb {
		marvell,pins = "mpp9";
		marvell,function = "gpio";
	};
};

&devbus_cs0 {
	status = "okay";
	compatible = "marvell,orion-nand";
	reg = <MBUS_ID(0x01, 0x1e) 0 0x400>;
	cle = <0>;
	ale = <1>;
	bank-width = <1>;

	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		uImage@0 { /* 4 MB */
			reg = <0 0x400000>;
			read-only;
		};

		rootfs@400000 { /* 64 MB */
			reg = <0x400000 0x4000000>;
			read-only;
		};

		extra@4400000 { /* 188 MB */
			reg = <0x4400000 0xBC00000>;
			read-only;
		};
	};
};

&hdd_power {
	gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
};

&usb_power {
	gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};

&sata {
	nr-ports = <2>;
};

&ehci1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "orion5x-mv88f5182.dtsi"

/ {
	model = "LaCie d2 Network";
	compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x";

	memory {
		device_type = "memory";
		reg = <0x00000000 0x4000000>; /* 64 MB */
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 earlyprintk";
		stdout-path = &uart0;
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
			 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&pmx_buttons>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		front_button {
			label = "Front Push Button";
			linux,code = <KEY_POWER>;
			gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
		};

		power_rocker_sw_on {
			label = "Power rocker switch (on|auto)";
			linux,input-type = <5>; /* EV_SW */
			linux,code = <1>; /* D2NET_SWITCH_POWER_ON */
			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
		};

		power_rocker_sw_off {
			label = "Power rocker switch (auto|off)";
			linux,input-type = <5>; /* EV_SW */
			linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */
			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>;
		pinctrl-names = "default";

		sata0_power: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "SATA0 Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
		};

		sata1_power: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "SATA1 Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
		};
	};
};

&devbus_bootcs {
	status = "okay";

	devbus,keep-config;

	/*
	 * Currently the MTD code does not recognize the MX29LV400CBCT
	 * as a bottom-type device. This could cause risks of
	 * accidentally erasing critical flash sectors. We thus define
	 * a single, write-protected partition covering the whole
	 * flash.  TODO: once the flash part TOP/BOTTOM detection
	 * issue is sorted out in the MTD code, break this into at
	 * least three partitions: 'u-boot code', 'u-boot environment'
	 * and 'whatever is left'.
	 */
	flash@0 {
		compatible = "cfi-flash";
		reg = <0 0x80000>;
		bank-width = <1>;
                #address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "Full512Kb";
			reg = <0 0x80000>;
			read-only;
		};
	};
};

&mdio {
	status = "okay";

	ethphy: ethernet-phy {
		reg = <8>;
	};
};

&ehci0 {
	status = "okay";
};

&eth {
	status = "okay";

	ethernet-port@0 {
		phy-handle = <&ethphy>;
	};
};

&i2c {
	status = "okay";
	clock-frequency = <100000>;
	#address-cells = <1>;

	rtc@32 {
		compatible = "ricoh,rs5c372b";
		reg = <0x32>;
	};

	fan@3e {
		compatible = "gmt,g762";
		reg = <0x3e>;

		/* Not enough HW info */
		status = "disabled";
	};

	eeprom@50 {
		compatible = "atmel,24c08";
		reg = <0x50>;
	};
};

&pinctrl {
	pinctrl-0 = <&pmx_leds &pmx_board_id &pmx_fan_fail>;
	pinctrl-names = "default";

	pmx_board_id: pmx-board-id {
		marvell,pins = "mpp0", "mpp1", "mpp2";
		marvell,function = "gpio";
	};

	pmx_buttons: pmx-buttons {
		marvell,pins = "mpp8", "mpp9", "mpp18";
		marvell,function = "gpio";
	};

	pmx_fan_fail: pmx-fan-fail {
		marvell,pins = "mpp5";
		marvell,function = "gpio";
	};

	/*
	 * MPP6: Red front LED
	 * MPP16: Blue front LED blink control
	 */
	pmx_leds: pmx-leds {
		marvell,pins = "mpp6", "mpp16";
		marvell,function = "gpio";
	};

	pmx_sata0_led_active: pmx-sata0-led-active {
		marvell,pins = "mpp14";
		marvell,function = "sata0";
	};

	pmx_sata0_power: pmx-sata0-power {
		marvell,pins = "mpp3";
		marvell,function = "gpio";
	};

	pmx_sata1_led_active: pmx-sata1-led-active {
		marvell,pins = "mpp15";
		marvell,function = "sata1";
	};

	pmx_sata1_power: pmx-sata1-power {
		marvell,pins = "mpp12";
		marvell,function = "gpio";
	};

	/*
	 * Non MPP GPIOs:
	 *  GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok)
	 *  GPIO 23: Blue front LED off
	 *  GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled)
	 */
};

&sata {
	pinctrl-0 = <&pmx_sata0_led_active
		     &pmx_sata1_led_active>;
	pinctrl-names = "default";
	status = "okay";
	nr-ports = <2>;
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

/*
 * TODO: add Orion USB device port init when kernel.org support is added.
 * TODO: add flash write support: see below.
 * TODO: add power-off support.
 * TODO: add I2C EEPROM support.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "orion5x-mv88f5182.dtsi"

/ {
	model = "LaCie Ethernet Disk mini V2";
	compatible = "lacie,ethernet-disk-mini-v2", "marvell,orion5x-88f5182", "marvell,orion5x";

	memory {
		device_type = "memory";
		reg = <0x00000000 0x4000000>; /* 64 MB */
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 earlyprintk";
		stdout-path = &uart0;
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
			 <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&pmx_power_button>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		button@1 {
			label = "Power-on Switch";
			linux,code = <KEY_POWER>;
			gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pmx_power_led>;
		pinctrl-names = "default";

		led@1 {
			label = "power:blue";
			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
		};
	};
};

&devbus_bootcs {
	status = "okay";

	/* Read parameters */
	devbus,bus-width    = <8>;
	devbus,turn-off-ps  = <90000>;
	devbus,badr-skew-ps = <0>;
	devbus,acc-first-ps = <186000>;
	devbus,acc-next-ps  = <186000>;

	/* Write parameters */
	devbus,wr-high-ps  = <90000>;
	devbus,wr-low-ps   = <90000>;
	devbus,ale-wr-ps   = <90000>;

	/*
	 * Currently the MTD code does not recognize the MX29LV400CBCT
	 * as a bottom-type device. This could cause risks of
	 * accidentally erasing critical flash sectors. We thus define
	 * a single, write-protected partition covering the whole
	 * flash.  TODO: once the flash part TOP/BOTTOM detection
	 * issue is sorted out in the MTD code, break this into at
	 * least three partitions: 'u-boot code', 'u-boot environment'
	 * and 'whatever is left'.
	 */
	flash@0 {
		compatible = "cfi-flash";
		reg = <0 0x80000>;
		bank-width = <1>;
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "Full512Kb";
			reg = <0 0x80000>;
			read-only;
		};
	};
};

&ehci0 {
	status = "okay";
};

&eth {
	status = "okay";

	ethernet-port@0 {
		phy-handle = <&ethphy>;
	};
};

&i2c {
	status = "okay";
	clock-frequency = <100000>;
	#address-cells = <1>;

	rtc@32 {
		compatible = "ricoh,rs5c372a";
		reg = <0x32>;
		interrupt-parent = <&gpio0>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
	};
};

&mdio {
	status = "okay";

	ethphy: ethernet-phy {
		reg = <8>;
	};
};

&pinctrl {
	pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>;
	pinctrl-names = "default";

	pmx_power_button: pmx-power-button {
		marvell,pins = "mpp18";
		marvell,function = "gpio";
	};

	pmx_power_led: pmx-power-led {
		marvell,pins = "mpp16";
		marvell,function = "gpio";
	};

	pmx_power_led_ctrl: pmx-power-led-ctrl {
		marvell,pins = "mpp17";
		marvell,function = "gpio";
	};

	pmx_rtc: pmx-rtc {
		marvell,pins = "mpp3";
		marvell,function = "gpio";
	};
};

&sata {
	pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
	pinctrl-names = "default";
	status = "okay";
	nr-ports = <2>;
};

&uart0 {
	status = "okay";
};


code:
/*
 * Device Tree file for Buffalo Linkstation LS-CHLv3
 *
 * Copyright (C) 2016 Ash Hughes <ashley.hughes@blueyonder.co.uk>
 * Copyright (C) 2015-2017
 * Roger Shimizu <rogershimizu@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include "orion5x-linkstation.dtsi"
#include "mvebu-linkstation-gpio-simple.dtsi"
#include "mvebu-linkstation-fan.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Buffalo Linkstation LiveV3 (LS-CHL)";
	compatible = "buffalo,lschl", "marvell,orion5x-88f5182", "marvell,orion5x";

	memory { /* 128 MB */
		device_type = "memory";
		reg = <0x00000000 0x8000000>;
	};

	gpio_keys {
		func {
			label = "Function Button";
			linux,code = <KEY_OPTION>;
			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
		};

		power-on-switch {
			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
		};

		power-auto-switch {
			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
		};
	};

	gpio_leds {
		pinctrl-0 = <&pmx_led_power &pmx_led_alarm &pmx_led_info &pmx_led_func>;
		blue-power-led {
			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
		};

		red-alarm-led {
			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
		};

		amber-info-led {
			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
		};

		func {
			label = "lschl:func:blue:top";
			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
		};
	};

	gpio_fan {
		gpios = <&gpio0 14 GPIO_ACTIVE_LOW
			 &gpio0 16 GPIO_ACTIVE_LOW>;

		alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
	};
};

&pinctrl {
	pmx_led_power: pmx-leds {
		marvell,pins = "mpp0";
		marvell,function = "gpio";
	};

	pmx_power_hdd: pmx-power-hdd {
		marvell,pins = "mpp1";
		marvell,function = "gpio";
	};

	pmx_led_alarm: pmx-leds {
		marvell,pins = "mpp2";
		marvell,function = "gpio";
	};

	pmx_led_info: pmx-leds {
		marvell,pins = "mpp3";
		marvell,function = "gpio";
	};

	pmx_fan_lock: pmx-fan-lock {
		marvell,pins = "mpp6";
		marvell,function = "gpio";
	};

	pmx_power_switch: pmx-power-switch {
		marvell,pins = "mpp8", "mpp10", "mpp15";
		marvell,function = "gpio";
	};

	pmx_power_usb: pmx-power-usb {
		marvell,pins = "mpp9";
		marvell,function = "gpio";
	};

	pmx_fan_high: pmx-fan-high {
		marvell,pins = "mpp14";
		marvell,function = "gpio";
	};

	pmx_fan_low: pmx-fan-low {
		marvell,pins = "mpp16";
		marvell,function = "gpio";
	};

	pmx_led_func: pmx-leds {
		marvell,pins = "mpp17";
		marvell,function = "gpio";
	};

	pmx_sw_init: pmx-sw-init {
		marvell,pins = "mpp7";
		marvell,function = "gpio";
	};
};

&hdd_power {
	gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
};

&usb_power {
	gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};


code:
/*
 * Device Tree file for Buffalo Linkstation LS-GL
 *       (also known as Buffalo Linkstation Pro/Live)
 *
 * Copyright (C) 2016
 * Roger Shimizu <rogershimizu@gmail.com>
 *
 * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c
 * Copyright (C) Ronen Shitrit <rshitrit@marvell.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include "orion5x-linkstation.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Buffalo Linkstation Pro/Live";
	compatible = "buffalo,lsgl", "marvell,orion5x-88f5182", "marvell,orion5x";

	memory { /* 128 MB */
		device_type = "memory";
		reg = <0x00000000 0x8000000>;
	};
};

&pinctrl {
	pmx_power_hdd: pmx-power-hdd {
		marvell,pins = "mpp1";
		marvell,function = "gpio";
	};

	pmx_power_usb: pmx-power-usb {
		marvell,pins = "mpp9";
		marvell,function = "gpio";
	};
};

&hdd_power {
	gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
};

&usb_power {
	gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};

&sata {
	nr-ports = <2>;
};

&ehci1 {
	status = "okay";
};


code:
/*
 * Device Tree file for Buffalo Linkstation LS-WTGL
 *
 * Copyright (C) 2015, 2016
 * Roger Shimizu <rogershimizu@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include "orion5x-linkstation.dtsi"
#include "mvebu-linkstation-gpio-simple.dtsi"
#include "mvebu-linkstation-fan.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Buffalo Linkstation LS-WTGL";
	compatible = "buffalo,lswtgl", "marvell,orion5x-88f5182", "marvell,orion5x";

	memory { /* 64 MB */
		device_type = "memory";
		reg = <0x00000000 0x4000000>;
	};

	gpio_keys {
		power-on-switch {
			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
		};

		power-auto-switch {
			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
		};
	};

	gpio_leds {
		blue-power-led {
			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
		};

		red-alarm-led {
			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
		};

		amber-info-led {
			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
		};
	};

	gpio_fan {
		gpios = <&gpio0 14 GPIO_ACTIVE_LOW
			 &gpio0 17 GPIO_ACTIVE_LOW>;

		alarm-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
	};
};

&pinctrl {
	pmx_led_power: pmx-leds {
		marvell,pins = "mpp0";
		marvell,function = "gpio";
	};

	pmx_power_hdd: pmx-power-hdd {
		marvell,pins = "mpp1";
		marvell,function = "gpio";
	};

	pmx_led_alarm: pmx-leds {
		marvell,pins = "mpp2";
		marvell,function = "gpio";
	};

	pmx_led_info: pmx-leds {
		marvell,pins = "mpp3";
		marvell,function = "gpio";
	};

	pmx_fan_lock: pmx-fan-lock {
		marvell,pins = "mpp6";
		marvell,function = "gpio";
	};

	pmx_power_switch: pmx-power-switch {
		marvell,pins = "mpp8", "mpp10";
		marvell,function = "gpio";
	};

	pmx_power_usb: pmx-power-usb {
		marvell,pins = "mpp9";
		marvell,function = "gpio";
	};

	pmx_fan_high: pmx-fan-high {
		marvell,pins = "mpp14";
		marvell,function = "gpio";
	};

	pmx_fan_low: pmx-fan-low {
		marvell,pins = "mpp17";
		marvell,function = "gpio";
	};
};

&hdd_power {
	gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
};

&usb_power {
	gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};

&sata {
	nr-ports = <2>;
};


code:
/*
 * Device Tree common file for orion5x based Buffalo Linkstation
 *
 * Copyright (C) 2015, 2016
 * Roger Shimizu <rogershimizu@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "orion5x-mv88f5182.dtsi"

/ {
	chosen {
		bootargs = "console=ttyS0,115200n8 earlyprintk";
		stdout-path = &uart0;
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
				 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
				 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>;
	};

	restart_poweroff {
		compatible = "restart-poweroff";
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-0 = <&pmx_power_usb &pmx_power_hdd>;
		pinctrl-names = "default";

		usb_power: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "USB Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
		};

		hdd_power: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "HDD Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
		};
	};
};

&pinctrl {
	pmx_power_hdd: pmx-power-hdd {
		marvell,function = "gpio";
	};

	pmx_power_usb: pmx-power-usb {
		marvell,function = "gpio";
	};
};

&devbus_bootcs {
	status = "okay";
	devbus,keep-config;

	flash@0 {
		compatible = "jedec-flash";
		reg = <0 0x40000>;
		bank-width = <1>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			header@0 {
				reg = <0 0x30000>;
				read-only;
			};

			uboot@30000 {
				reg = <0x30000 0xF000>;
				read-only;
			};

			uboot_env@3F000 {
				reg = <0x3F000 0x1000>;
			};
		};
	};
};

&mdio {
	status = "okay";

	ethphy: ethernet-phy {
		reg = <8>;
	};
};

&eth {
	status = "okay";

	ethernet-port@0 {
		phy-handle = <&ethphy>;
	};
};

&ehci0 {
	status = "okay";
};

&i2c {
	status = "okay";

	rtc@32 {
		compatible = "ricoh,rs5c372a";
		reg = <0x32>;
	};
};

&wdt {
	status = "disabled";
};

&sata {
	status = "okay";
	nr-ports = <1>;
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};


code:
/*
 * Copyright (C) 2015 Benjamin Cama <benoar@dolka.fr>
 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Based on the board file arch/arm/mach-orion5x/lsmini-setup.c,
 * Copyright (C) 2008 Alexey Kopytko <alexey@kopytko.ru>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "orion5x-mv88f5182.dtsi"

/ {
	model = "Buffalo Linkstation Mini (LS-WSGL)";
	compatible = "buffalo,lswsgl", "marvell,orion5x-88f5182", "marvell,orion5x";

	memory {
		device_type = "memory";
		reg = <0x00000000 0x8000000>; /* 128 MB */
	};

	chosen {
		bootargs = "console=ttyS0,115200 earlyprintk";
		stdout-path = &uart0;
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&pmx_buttons>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		func {
			label = "Function Button";
			linux,code = <KEY_OPTION>;
			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
		};

		power {
			label = "Power-on Switch";
			linux,input-type = <5>; /* EV_SW */
			linux,code = <KEY_RESERVED>; /* LSMINI_SW_POWER */
			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
		};

		autopower {
			label = "Power-auto Switch";
			linux,input-type = <5>; /* EV_SW */
			linux,code = <KEY_ESC>; /* LSMINI_SW_AUTOPOWER */
			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pmx_led_alarm &pmx_led_info &pmx_led_func
			     &pmx_led_power>;
		pinctrl-names = "default";

		alarm {
			label = "lswsgl:alarm:red";
			gpio = <&gpio0 2 GPIO_ACTIVE_LOW>;
		};

		info {
			label = "lswsgl:info:amber";
			gpio = <&gpio0 3 GPIO_ACTIVE_LOW>;
		};

		func {
			label = "lswsgl:func:blue:top";
			gpio = <&gpio0 9 GPIO_ACTIVE_LOW>;
		};

		power {
			label = "lswsgl:power:blue:bottom";
			gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};
	};

	restart_poweroff {
		compatible = "restart-poweroff";
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power &pmx_usb_power>;
		pinctrl-names = "default";

		sata0_power: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "SATA0 Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio0 1 GPIO_ACTIVE_HIGH>;
		};

		sata1_power: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "SATA1 Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
		};

		usb_power: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "USB Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
		};
	};
};

&devbus_bootcs {
	status = "okay";

	devbus,keep-config;

	flash@0 {
		compatible = "cfi-flash";
		reg = <0 0x40000>;
		bank-width = <1>;
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "Full256Kb";
			reg = <0 0x40000>;
			read-only;
		};
	};
};

&mdio {
	status = "okay";

	ethphy: ethernet-phy {
		reg = <8>;
	};
};

&ehci0 {
	status = "okay";
};

&eth {
	status = "okay";

	ethernet-port@0 {
		phy-handle = <&ethphy>;
	};
};

&i2c {
	status = "okay";
	clock-frequency = <100000>;
	#address-cells = <1>;

	rtc@32 {
		compatible = "ricoh,rs5c372a";
		reg = <0x32>;
	};
};

&pinctrl {
	pmx_buttons: pmx-buttons {
		marvell,pins = "mpp15", "mpp17", "mpp18";
		marvell,function = "gpio";
	};

	pmx_led_alarm: pmx-leds {
		marvell,pins = "mpp2";
		marvell,function = "gpio";
	};

	pmx_led_info: pmx-leds {
		marvell,pins = "mpp3";
		marvell,function = "gpio";
	};

	pmx_led_func: pmx-leds {
		marvell,pins = "mpp9";
		marvell,function = "gpio";
	};

	pmx_led_power: pmx-leds {
		marvell,pins = "mpp14";
		marvell,function = "gpio";
	};

	pmx_sata0_power: pmx-sata0-power {
		marvell,pins = "mpp1";
		marvell,function = "gpio";
	};

	pmx_sata1_power: pmx-sata1-power {
		marvell,pins = "mpp19";
		marvell,function = "gpio";
	};

	pmx_usb_power: pmx-usb-power {
		marvell,pins = "mpp16";
		marvell,function = "gpio";
	};
};

&sata {
	status = "okay";
	nr-ports = <2>;
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Copyright (C) Sylver Bruneau <sylver.bruneau@googlemail.com>
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "orion5x-mv88f5182.dtsi"

/ {
	model = "Maxtor Shared Storage II";
	compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x";

	memory {
		device_type = "memory";
		reg = <0x00000000 0x4000000>; /* 64 MB */
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 earlyprintk";
		stdout-path = &uart0;
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
			 <MBUS_ID(0x01, 0x0f) 0 0xff800000 0x40000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&pmx_buttons>;
		pinctrl-names = "default";
		#address-cells = <1>;
		#size-cells = <0>;
		power {
			label = "Power";
			linux,code = <KEY_POWER>;
			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
		};

		reset {
			label = "Reset";
			linux,code = <KEY_RESTART>;
			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
		};
	};
};

&devbus_bootcs {
	status = "okay";

	devbus,keep-config;

	/*
	 * Currently the MTD code does not recognize the MX29LV400CBCT
	 * as a bottom-type device. This could cause risks of
	 * accidentally erasing critical flash sectors. We thus define
	 * a single, write-protected partition covering the whole
	 * flash.  TODO: once the flash part TOP/BOTTOM detection
	 * issue is sorted out in the MTD code, break this into at
	 * least three partitions: 'u-boot code', 'u-boot environment'
	 * and 'whatever is left'.
	 */
	flash@0 {
		compatible = "cfi-flash";
		reg = <0 0x40000>;
		bank-width = <1>;
                #address-cells = <1>;
		#size-cells = <1>;
	};
};

&mdio {
	status = "okay";

	ethphy: ethernet-phy {
		reg = <8>;
	};
};

&ehci0 {
	status = "okay";
};

&eth {
	status = "okay";

	ethernet-port@0 {
		phy-handle = <&ethphy>;
	};
};

&i2c {
	status = "okay";
	clock-frequency = <100000>;
	#address-cells = <1>;

	rtc@68 {
		compatible = "st,m41t81";
		reg = <0x68>;
		pinctrl-0 = <&pmx_rtc>;
		pinctrl-names = "default";
		interrupt-parent = <&gpio0>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
	};
};

&pinctrl {
	pinctrl-0 = <&pmx_leds &pmx_misc>;
	pinctrl-names = "default";

	pmx_buttons: pmx-buttons {
		marvell,pins = "mpp11", "mpp12";
		marvell,function = "gpio";
	};

	/*
	 * MPP0: Power LED
	 * MPP1: Error LED
	 */
	pmx_leds: pmx-leds {
		marvell,pins = "mpp0", "mpp1";
		marvell,function = "gpio";
	};

	/*
	 * MPP4: HDD ind. (Single/Dual)
	 * MPP5: HD0 5V control
	 * MPP6: HD0 12V control
	 * MPP7: HD1 5V control
	 * MPP8: HD1 12V control
	 */
	pmx_misc: pmx-misc {
		marvell,pins = "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp10";
		marvell,function = "gpio";
	};

	pmx_rtc: pmx-rtc {
		marvell,pins = "mpp3";
		marvell,function = "gpio";
	};

	pmx_sata0_led_active: pmx-sata0-led-active {
		marvell,pins = "mpp14";
		marvell,function = "sata0";
	};

	pmx_sata1_led_active: pmx-sata1-led-active {
		marvell,pins = "mpp15";
		marvell,function = "sata1";
	};

	/*
	 * Non MPP GPIOs:
	 *  GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok)
	 *  GPIO 23: Blue front LED off
	 *  GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled)
	 */
};

&sata {
	pinctrl-0 = <&pmx_sata0_led_active
		     &pmx_sata1_led_active>;
	pinctrl-names = "default";
	status = "okay";
	nr-ports = <2>;
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>

#include "orion5x.dtsi"

/ {
	compatible = "marvell,orion5x-88f5181", "marvell,orion5x";

	soc {
		compatible = "marvell,orion5x-88f5181-mbus", "simple-bus";

		internal-regs {
			pinctrl: pinctrl@10000 {
				compatible = "marvell,88f5181-pinctrl";
				reg = <0x10000 0x8>, <0x10050 0x4>;
			};

			core_clk: core-clocks@10030 {
				compatible = "marvell,mv88f5181-core-clock";
				reg = <0x10010 0x4>;
				#clock-cells = <1>;
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x1500 0x20>;
			};
		};
	};
};

&pinctrl {
	pmx_ge: pmx-ge {
		marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11",
			       "mpp12", "mpp13", "mpp14", "mpp15",
			       "mpp16", "mpp17", "mpp18", "mpp19";
		marvell,function = "ge";
	};
};

&eth {
	pinctrl-0 = <&pmx_ge>;
	pinctrl-names = "default";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

#include "orion5x.dtsi"

/ {
	compatible = "marvell,orion5x-88f5182", "marvell,orion5x";

	soc {
		compatible = "marvell,orion5x-88f5182-mbus", "simple-bus";

		internal-regs {
			pinctrl: pinctrl@10000 {
				compatible = "marvell,88f5182-pinctrl";
				reg = <0x10000 0x8>, <0x10050 0x4>;

				pmx_sata0: pmx-sata0 {
					marvell,pins = "mpp12", "mpp14";
					marvell,function = "sata0";
				};

				pmx_sata1: pmx-sata1 {
					marvell,pins = "mpp13", "mpp15";
					marvell,function = "sata1";
				};
			};

			core_clk: core-clocks@10030 {
				compatible = "marvell,mv88f5182-core-clock";
				reg = <0x10010 0x4>;
				#clock-cells = <1>;
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x1500 0x20>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2016 Jamie Lentin <jm@lentin.co.uk>

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "orion5x-mv88f5181.dtsi"

/ {
	model = "Netgear WNR854-t";
	compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
		     "marvell,orion5x";
	aliases {
		serial0 = &uart0;
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x2000000>; /* 32 MB */
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
			 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
			 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&pmx_reset_button>;
		pinctrl-names = "default";

		reset {
			label = "Reset Button";
			linux,code = <KEY_RESTART>;
			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
		pinctrl-names = "default";

		led@0 {
			label = "wnr854t:green:power";
			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
		};

		led@1 {
			label = "wnr854t:blink:power";
			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
		};

		led@2 {
			label = "wnr854t:green:wan";
			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
		};
	};
};

&devbus_bootcs {
	status = "okay";

	devbus,keep-config;

	flash@0 {
		compatible = "cfi-flash";
		reg = <0 0x800000>;
		bank-width = <2>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "kernel";
				reg = <0x0 0x100000>;
			};

			partition@100000 {
				label = "rootfs";
				reg = <0x100000 0x660000>;
			};

			partition@760000 {
				label = "uboot_env";
				reg = <0x760000 0x20000>;
			};

			partition@780000 {
				label = "uboot";
				reg = <0x780000 0x80000>;
				read-only;
			};
		};
	};
};

&mdio {
	status = "okay";

	switch: switch@0 {
		compatible = "marvell,mv88e6085";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0>;
		dsa,member = <0 0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				label = "lan3";
				phy-handle = <&lan3phy>;
			};

			port@1 {
				reg = <1>;
				label = "lan4";
				phy-handle = <&lan4phy>;
			};

			port@2 {
				reg = <2>;
				label = "wan";
				phy-handle = <&wanphy>;
			};

			port@3 {
				reg = <3>;
				label = "cpu";
				ethernet = <&ethport>;
			};

			port@5 {
				reg = <5>;
				label = "lan1";
				phy-handle = <&lan1phy>;
			};

			port@7 {
				reg = <7>;
				label = "lan2";
				phy-handle = <&lan2phy>;
			};
		};

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			lan3phy: ethernet-phy@0 {
				/* Marvell 88E1121R (port 1) */
				compatible = "ethernet-phy-id0141.0cb0",
					     "ethernet-phy-ieee802.3-c22";
				reg = <0>;
				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
			};

			lan4phy: ethernet-phy@1 {
				/* Marvell 88E1121R (port 2) */
				compatible = "ethernet-phy-id0141.0cb0",
					     "ethernet-phy-ieee802.3-c22";
				reg = <1>;
				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
			};

			wanphy: ethernet-phy@2 {
				/* Marvell 88E1121R (port 1) */
				compatible = "ethernet-phy-id0141.0cb0",
					     "ethernet-phy-ieee802.3-c22";
				reg = <2>;
				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
			};

			lan1phy: ethernet-phy@5 {
				/* Marvell 88E1112 */
				compatible = "ethernet-phy-id0141.0cb0",
					     "ethernet-phy-ieee802.3-c22";
				reg = <5>;
				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
			};

			lan2phy: ethernet-phy@7 {
				/* Marvell 88E1112 */
				compatible = "ethernet-phy-id0141.0cb0",
					     "ethernet-phy-ieee802.3-c22";
				reg = <7>;
				marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>;
			};
		};
	};
};

&eth {
	status = "okay";

	ethernet-port@0 {
		/* Hardwired to DSA switch */
		speed = <1000>;
		duplex = <1>;
	};
};

&pinctrl {
	pinctrl-0 = <&pmx_pci_gpios>;
	pinctrl-names = "default";

	pmx_power_led: pmx-power-led {
		marvell,pins = "mpp0";
		marvell,function = "gpio";
	};

	pmx_reset_button: pmx-reset-button {
		marvell,pins = "mpp1";
		marvell,function = "gpio";
	};

	pmx_power_led_blink: pmx-power-led-blink {
		marvell,pins = "mpp2";
		marvell,function = "gpio";
	};

	pmx_wan_led: pmx-wan-led {
		marvell,pins = "mpp3";
		marvell,function = "gpio";
	};

	pmx_pci_gpios: pmx-pci-gpios {
		marvell,pins = "mpp4";
		marvell,function = "gpio";
	};
};

&uart0 {
	/* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
	status = "okay";
};