code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright 2014 Carlo Caione <carlo@caione.org>
 */

#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h>
#include <dt-bindings/power/meson8-power.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
#include <dt-bindings/reset/amlogic,meson8b-reset.h>
#include <dt-bindings/thermal/thermal.h>
#include "meson.dtsi"

/ {
	model = "Amlogic Meson8 SoC";
	compatible = "amlogic,meson8";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x200>;
			enable-method = "amlogic,meson8-smp";
			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
			operating-points-v2 = <&cpu_opp_table>;
			clocks = <&clkc CLKID_CPUCLK>;
			#cooling-cells = <2>; /* min followed by max */
		};

		cpu1: cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x201>;
			enable-method = "amlogic,meson8-smp";
			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
			operating-points-v2 = <&cpu_opp_table>;
			clocks = <&clkc CLKID_CPUCLK>;
			#cooling-cells = <2>; /* min followed by max */
		};

		cpu2: cpu@202 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x202>;
			enable-method = "amlogic,meson8-smp";
			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
			operating-points-v2 = <&cpu_opp_table>;
			clocks = <&clkc CLKID_CPUCLK>;
			#cooling-cells = <2>; /* min followed by max */
		};

		cpu3: cpu@203 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x203>;
			enable-method = "amlogic,meson8-smp";
			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
			operating-points-v2 = <&cpu_opp_table>;
			clocks = <&clkc CLKID_CPUCLK>;
			#cooling-cells = <2>; /* min followed by max */
		};
	};

	cpu_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-96000000 {
			opp-hz = /bits/ 64 <96000000>;
			opp-microvolt = <825000>;
		};
		opp-192000000 {
			opp-hz = /bits/ 64 <192000000>;
			opp-microvolt = <825000>;
		};
		opp-312000000 {
			opp-hz = /bits/ 64 <312000000>;
			opp-microvolt = <825000>;
		};
		opp-408000000 {
			opp-hz = /bits/ 64 <408000000>;
			opp-microvolt = <825000>;
		};
		opp-504000000 {
			opp-hz = /bits/ 64 <504000000>;
			opp-microvolt = <825000>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <850000>;
		};
		opp-720000000 {
			opp-hz = /bits/ 64 <720000000>;
			opp-microvolt = <850000>;
		};
		opp-816000000 {
			opp-hz = /bits/ 64 <816000000>;
			opp-microvolt = <875000>;
		};
		opp-1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <925000>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <975000>;
		};
		opp-1416000000 {
			opp-hz = /bits/ 64 <1416000000>;
			opp-microvolt = <1025000>;
		};
		opp-1608000000 {
			opp-hz = /bits/ 64 <1608000000>;
			opp-microvolt = <1100000>;
		};
		opp-1800000000 {
			status = "disabled";
			opp-hz = /bits/ 64 <1800000000>;
			opp-microvolt = <1125000>;
		};
		opp-1992000000 {
			status = "disabled";
			opp-hz = /bits/ 64 <1992000000>;
			opp-microvolt = <1150000>;
		};
	};

	gpu_opp_table: gpu-opp-table {
		compatible = "operating-points-v2";

		opp-182142857 {
			opp-hz = /bits/ 64 <182142857>;
			opp-microvolt = <1150000>;
		};
		opp-318750000 {
			opp-hz = /bits/ 64 <318750000>;
			opp-microvolt = <1150000>;
		};
		opp-425000000 {
			opp-hz = /bits/ 64 <425000000>;
			opp-microvolt = <1150000>;
		};
		opp-510000000 {
			opp-hz = /bits/ 64 <510000000>;
			opp-microvolt = <1150000>;
		};
		opp-637500000 {
			opp-hz = /bits/ 64 <637500000>;
			opp-microvolt = <1150000>;
			turbo-mode;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* 2 MiB reserved for Hardware ROM Firmware? */
		hwrom@0 {
			reg = <0x0 0x200000>;
			no-map;
		};

		/*
		 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
		 * code which is responsible for system suspend. It loads a
		 * piece of ARC code ("arc_power" in the vendor u-boot tree)
		 * into SRAM, executes that and shuts down the (last) ARM core.
		 * The arc_power firmware then checks various wakeup sources
		 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
		 * simply the power key) and re-starts the ARM core once it
		 * detects a wakeup request.
		 */
		power-firmware@4f00000 {
			reg = <0x4f00000 0x100000>;
			no-map;
		};
	};

	thermal-zones {
		soc {
			polling-delay-passive = <250>; /* milliseconds */
			polling-delay = <1000>; /* milliseconds */
			thermal-sensors = <&thermal_sensor>;

			cooling-maps {
				map0 {
					trip = <&soc_passive>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};

				map1 {
					trip = <&soc_hot>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				soc_passive: soc-passive {
					temperature = <80000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "passive";
				};

				soc_hot: soc-hot {
					temperature = <90000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "hot";
				};

				soc_critical: soc-critical {
					temperature = <110000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "critical";
				};
			};
		};
	};

	mmcbus: bus@c8000000 {
		compatible = "simple-bus";
		reg = <0xc8000000 0x8000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0xc8000000 0x8000>;

		ddr_clkc: clock-controller@400 {
			compatible = "amlogic,meson8-ddr-clkc";
			reg = <0x400 0x20>;
			clocks = <&xtal>;
			clock-names = "xtal";
			#clock-cells = <1>;
		};

		dmcbus: bus@6000 {
			compatible = "simple-bus";
			reg = <0x6000 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x6000 0x400>;

			canvas: video-lut@20 {
				compatible = "amlogic,meson8-canvas",
					     "amlogic,canvas";
				reg = <0x20 0x14>;
			};
		};
	};

	apb: bus@d0000000 {
		compatible = "simple-bus";
		reg = <0xd0000000 0x200000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0xd0000000 0x200000>;

		mali: gpu@c0000 {
			compatible = "amlogic,meson8-mali", "arm,mali-450";
			reg = <0xc0000 0x40000>;
			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gp", "gpmmu", "pp", "pmu",
					  "pp0", "ppmmu0", "pp1", "ppmmu1",
					  "pp2", "ppmmu2", "pp4", "ppmmu4",
					  "pp5", "ppmmu5", "pp6", "ppmmu6";
			resets = <&reset RESET_MALI>;

			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
			clock-names = "bus", "core";

			assigned-clocks = <&clkc CLKID_MALI>;
			assigned-clock-rates = <318750000>;

			operating-points-v2 = <&gpu_opp_table>;
			#cooling-cells = <2>; /* min followed by max */
		};
	};
}; /* end of / */

&aiu {
	compatible = "amlogic,aiu-meson8", "amlogic,aiu";
	clocks = <&clkc CLKID_AIU_GLUE>,
		 <&clkc CLKID_I2S_OUT>,
		 <&clkc CLKID_AOCLK_GATE>,
		 <&clkc CLKID_CTS_AMCLK>,
		 <&clkc CLKID_MIXER_IFACE>,
		 <&clkc CLKID_IEC958>,
		 <&clkc CLKID_IEC958_GATE>,
		 <&clkc CLKID_CTS_MCLK_I958>,
		 <&clkc CLKID_CTS_I958>;
	clock-names = "pclk",
		      "i2s_pclk",
		      "i2s_aoclk",
		      "i2s_mclk",
		      "i2s_mixer",
		      "spdif_pclk",
		      "spdif_aoclk",
		      "spdif_mclk",
		      "spdif_mclk_sel";
	resets = <&reset RESET_AIU>;
};

&aobus {
	pmu: pmu@e0 {
		compatible = "amlogic,meson8-pmu", "syscon";
		reg = <0xe0 0x18>;
	};

	pinctrl_aobus: pinctrl@84 {
		compatible = "amlogic,meson8-aobus-pinctrl";
		reg = <0x84 0xc>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio_ao: ao-bank@14 {
			reg = <0x14 0x4>,
			      <0x2c 0x4>,
			      <0x24 0x8>;
			reg-names = "mux", "pull", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_aobus 0 0 16>;
		};

		i2s_am_clk_pins: i2s-am-clk-out {
			mux {
				groups = "i2s_am_clk_out_ao";
				function = "i2s_ao";
				bias-disable;
			};
		};

		i2s_out_ao_clk_pins: i2s-ao-clk-out {
			mux {
				groups = "i2s_ao_clk_out_ao";
				function = "i2s_ao";
				bias-disable;
			};
		};

		i2s_out_lr_clk_pins: i2s-lr-clk-out {
			mux {
				groups = "i2s_lr_clk_out_ao";
				function = "i2s_ao";
				bias-disable;
			};
		};

		i2s_out_ch01_ao_pins: i2s-out-ch01 {
			mux {
				groups = "i2s_out_ch01_ao";
				function = "i2s_ao";
				bias-disable;
			};
		};

		uart_ao_a_pins: uart_ao_a {
			mux {
				groups = "uart_tx_ao_a", "uart_rx_ao_a";
				function = "uart_ao";
				bias-disable;
			};
		};

		i2c_ao_pins: i2c_mst_ao {
			mux {
				groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
				function = "i2c_mst_ao";
				bias-disable;
			};
		};

		ir_recv_pins: remote {
			mux {
				groups = "remote_input";
				function = "remote";
				bias-disable;
			};
		};

		pwm_f_ao_pins: pwm-f-ao {
			mux {
				groups = "pwm_f_ao";
				function = "pwm_f_ao";
				bias-disable;
			};
		};
	};
};

&ao_arc_rproc {
	compatible = "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
	amlogic,secbus2 = <&secbus2>;
	sram = <&ao_arc_sram>;
	resets = <&reset RESET_MEDIA_CPU>;
	clocks = <&clkc CLKID_AO_MEDIA_CPU>;
};

&cbus {
	reset: reset-controller@4404 {
		compatible = "amlogic,meson8b-reset";
		reg = <0x4404 0x9c>;
		#reset-cells = <1>;
	};

	analog_top: analog-top@81a8 {
		compatible = "amlogic,meson8-analog-top", "syscon";
		reg = <0x81a8 0x14>;
	};

	pwm_ef: pwm@86c0 {
		compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
		reg = <0x86c0 0x10>;
		#pwm-cells = <3>;
		status = "disabled";
	};

	clock-measure@8758 {
		compatible = "amlogic,meson8-clk-measure";
		reg = <0x8758 0x1c>;
	};

	pinctrl_cbus: pinctrl@9880 {
		compatible = "amlogic,meson8-cbus-pinctrl";
		reg = <0x9880 0x10>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio: banks@80b0 {
			reg = <0x80b0 0x28>,
			      <0x80e8 0x18>,
			      <0x8120 0x18>,
			      <0x8030 0x30>;
			reg-names = "mux", "pull", "pull-enable", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_cbus 0 0 120>;
		};

		sd_a_pins: sd-a {
			mux {
				groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
					"sd_d3_a", "sd_clk_a", "sd_cmd_a";
				function = "sd_a";
				bias-disable;
			};
		};

		sd_b_pins: sd-b {
			mux {
				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
				function = "sd_b";
				bias-disable;
			};
		};

		sd_c_pins: sd-c {
			mux {
				groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
					"sd_d3_c", "sd_clk_c", "sd_cmd_c";
				function = "sd_c";
				bias-disable;
			};
		};

		sdxc_b_pins: sdxc-b {
			mux {
				groups = "sdxc_d0_b", "sdxc_d13_b",
					 "sdxc_clk_b", "sdxc_cmd_b";
				function = "sdxc_b";
				bias-pull-up;
			};
		};

		spdif_out_pins: spdif-out {
			mux {
				groups = "spdif_out";
				function = "spdif";
				bias-disable;
			};
		};

		spi_nor_pins: nor {
			mux {
				groups = "nor_d", "nor_q", "nor_c", "nor_cs";
				function = "nor";
				bias-disable;
			};
		};

		eth_pins: ethernet {
			mux {
				groups = "eth_tx_clk_50m", "eth_tx_en",
					 "eth_txd1", "eth_txd0",
					 "eth_rx_clk_in", "eth_rx_dv",
					 "eth_rxd1", "eth_rxd0", "eth_mdio",
					 "eth_mdc";
				function = "ethernet";
				bias-disable;
			};
		};

		pwm_e_pins: pwm-e {
			mux {
				groups = "pwm_e";
				function = "pwm_e";
				bias-disable;
			};
		};

		uart_a1_pins: uart-a1 {
			mux {
				groups = "uart_tx_a1",
				       "uart_rx_a1";
				function = "uart_a";
				bias-disable;
			};
		};

		uart_a1_cts_rts_pins: uart-a1-cts-rts {
			mux {
				groups = "uart_cts_a1",
				       "uart_rts_a1";
				function = "uart_a";
				bias-disable;
			};
		};
	};
};

&ahb_sram {
	ao_arc_sram: ao-arc-sram@0 {
		compatible = "amlogic,meson8-ao-arc-sram";
		reg = <0x0 0x8000>;
		pool;
	};

	smp-sram@1ff80 {
		compatible = "amlogic,meson8-smp-sram";
		reg = <0x1ff80 0x8>;
	};
};

&efuse {
	compatible = "amlogic,meson8-efuse";
	clocks = <&clkc CLKID_EFUSE>;
	clock-names = "core";

	temperature_calib: calib@1f4 {
		/* only the upper two bytes are relevant */
		reg = <0x1f4 0x4>;
	};
};

&ethmac {
	clocks = <&clkc CLKID_ETH>;
	clock-names = "stmmaceth";

	power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
};

&gpio_intc {
	compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
	status = "okay";
};

&hhi {
	clkc: clock-controller {
		compatible = "amlogic,meson8-clkc";
		clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
		clock-names = "xtal", "ddr_pll";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pwrc: power-controller {
		compatible = "amlogic,meson8-pwrc";
		#power-domain-cells = <1>;
		amlogic,ao-sysctrl = <&pmu>;
		clocks = <&clkc CLKID_VPU>;
		clock-names = "vpu";
		assigned-clocks = <&clkc CLKID_VPU>;
		assigned-clock-rates = <364285714>;
	};
};

&hwrng {
	compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
	clocks = <&clkc CLKID_RNG0>;
	clock-names = "core";
};

&i2c_AO {
	clocks = <&clkc CLKID_CLK81>;
};

&i2c_A {
	clocks = <&clkc CLKID_CLK81>;
};

&i2c_B {
	clocks = <&clkc CLKID_CLK81>;
};

&L2 {
	arm,data-latency = <3 3 3>;
	arm,tag-latency = <2 2 2>;
	arm,filter-ranges = <0x100000 0xc0000000>;
	prefetch-data = <1>;
	prefetch-instr = <1>;
	arm,shared-override;
};

&periph {
	scu@0 {
		compatible = "arm,cortex-a9-scu";
		reg = <0x0 0x100>;
	};

	timer@200 {
		compatible = "arm,cortex-a9-global-timer";
		reg = <0x200 0x20>;
		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&clkc CLKID_PERIPH>;

		/*
		 * the arm_global_timer driver currently does not handle clock
		 * rate changes. Keep it disabled for now.
		 */
		status = "disabled";
	};

	timer@600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x600 0x20>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&clkc CLKID_PERIPH>;
	};
};

&pwm_ab {
	compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
};

&pwm_cd {
	compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
};

&rtc {
	compatible = "amlogic,meson8-rtc";
	resets = <&reset RESET_RTC>;
};

&saradc {
	compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
	clock-names = "clkin", "core";
	amlogic,hhi-sysctrl = <&hhi>;
	nvmem-cells = <&temperature_calib>;
	nvmem-cell-names = "temperature_calib";
};

&sdhc {
	compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
	clocks = <&xtal>,
		 <&clkc CLKID_FCLK_DIV4>,
		 <&clkc CLKID_FCLK_DIV3>,
		 <&clkc CLKID_FCLK_DIV5>,
		 <&clkc CLKID_SDHC>;
	clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
};

&secbus {
	secbus2: system-controller@4000 {
		compatible = "amlogic,meson8-secbus2", "syscon";
		reg = <0x4000 0x2000>;
	};
};

&sdio {
	compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
	clock-names = "core", "clkin";
};

&spifc {
	clocks = <&clkc CLKID_CLK81>;
};

&timer_abcde {
	clocks = <&xtal>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "pclk";
};

&uart_AO {
	compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart";
	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_A {
	compatible = "amlogic,meson8-uart";
	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_B {
	compatible = "amlogic,meson8-uart";
	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_C {
	compatible = "amlogic,meson8-uart";
	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "pclk", "baud";
};

&usb0 {
	compatible = "amlogic,meson8-usb", "snps,dwc2";
	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
	clock-names = "otg";
};

&usb1 {
	compatible = "amlogic,meson8-usb", "snps,dwc2";
	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
	clock-names = "otg";
};

&usb0_phy {
	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
	clock-names = "usb_general", "usb";
	resets = <&reset RESET_USB_OTG>;
};

&usb1_phy {
	compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
	clock-names = "usb_general", "usb";
	resets = <&reset RESET_USB_OTG>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

#include "meson8b.dtsi"

/ {
	model = "Endless Computers Endless Mini";
	compatible = "endless,ec100", "amlogic,meson8b";

	aliases {
		serial0 = &uart_AO;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x40000000 0x40000000>;
	};

	emmc_pwrseq: emmc-pwrseq {
		compatible = "mmc-pwrseq-emmc";
		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
	};

	gpio-keys {
		compatible = "gpio-keys-polled";
		#address-cells = <1>;
		#size-cells = <0>;
		poll-interval = <100>;

		pal-switch {
			label = "pal";
			linux,input-type = <EV_SW>;
			linux,code = <KEY_SWITCHVIDEOMODE>;
			gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>;
		};

		ntsc-switch {
			label = "ntsc";
			linux,input-type = <EV_SW>;
			linux,code = <KEY_SWITCHVIDEOMODE>;
			gpios = <&gpio GPIOH_8 GPIO_ACTIVE_HIGH>;
		};

		power-button {
			label = "power";
			linux,code = <KEY_POWER>;
			gpios = <&gpio GPIOH_9 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-poweroff {
		compatible = "gpio-poweroff";
		/*
		 * shutdown is managed by the EC (embedded micro-controller)
		 * which is configured through GPIOAO_2 (poweroff GPIO) and
		 * GPIOAO_7 (power LED, which has to go LOW as well).
		 */
		gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
		timeout-ms = <20000>;
	};

	leds {
		compatible = "gpio-leds";

		power {
			label = "ec100:red:power";
			/*
			 * Needs to go LOW (together with the poweroff GPIO)
			 * during shutdown to allow the EC (embedded
			 * micro-controller) to shutdown the system. Setting
			 * the output to LOW signals the EC to start a
			 * "breathing"/pulsing effect until the power is fully
			 * turned off.
			 */
			gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};
	};

	rtc32k_xtal: rtc32k-xtal-clk {
		/* X2 in the schematics */
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "RTC32K";
		#clock-cells = <0>;
	};

	sound {
		compatible = "amlogic,gx-sound-card";
		model = "M8B-EC100";

		assigned-clocks = <&clkc CLKID_MPLL0>,
				  <&clkc CLKID_MPLL1>,
				  <&clkc CLKID_MPLL2>;
		assigned-clock-rates = <270950400>,
				       <294912000>,
				       <393216000>;

		dai-link-0 {
			sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
		};

		dai-link-1 {
			sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
			dai-format = "i2s";
			mclk-fs = <256>;

			codec-0 {
				sound-dai = <&rt5640>;
			};
		};
	};

	usb_vbus: regulator-usb-vbus {
		/*
		 * Silergy SY6288CCAC-GP 2A Power Distribution Switch.
		 */
		compatible = "regulator-fixed";

		regulator-name = "USB_VBUS";

		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;

		vin-supply = <&vcc_5v>;

		/*
		 * signal name from the schematics: USB_PWR_EN
		 */
		gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vcc_5v: regulator-vcc5v {
		/*
		 * supplied by the main power input which called PWR_5V_STB
		 * in the schematics
		 */
		compatible = "regulator-fixed";

		regulator-name = "VCC5V";

		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;

		/*
		 * signal name from the schematics: 3V3_5V_EN
		 */
		gpio = <&gpio GPIODV_29 GPIO_ACTIVE_LOW>;

		regulator-boot-on;
		regulator-always-on;
	};

	vcck: regulator-vcck {
		/*
		 * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz
		 * Synchronous Step Down Regulator.
		 */
		compatible = "pwm-regulator";

		regulator-name = "VCCK";
		regulator-min-microvolt = <860000>;
		regulator-max-microvolt = <1140000>;

		pwm-supply = <&vcc_5v>;

		pwms = <&pwm_cd 0 1148 0>;
		pwm-dutycycle-range = <100 0>;

		regulator-boot-on;
		regulator-always-on;
	};

	vcc_1v8: regulator-vcc1v8 {
		/*
		 * ABLIC S-1339D18-M5001-GP
		 */
		compatible = "regulator-fixed";

		regulator-name = "VCC1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;

		vin-supply = <&vcc_3v3>;
	};

	vcc_3v3: regulator-vcc3v3 {
		/*
		 * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz
		 * Synchronous Step Down Regulator. Also called
		 * VDDIO_AO3.3V in the schematics.
		 */
		compatible = "regulator-fixed";

		regulator-name = "VCC3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		vin-supply = <&vcc_5v>;
	};

	vcc_ddr3: regulator-vcc-ddr3 {
		/*
		 * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz
		 * Synchronous Step Down Regulator. Also called
		 * DDR3_1.5V in the schematics.
		 */
		compatible = "regulator-fixed";

		regulator-name = "VCC_DDR3_1V5";
		regulator-min-microvolt = <1500000>;
		regulator-max-microvolt = <1500000>;

		vin-supply = <&vcc_5v>;

		regulator-boot-on;
		regulator-always-on;
	};

	vcc_rtc: regulator-vcc-rtc {
		/*
		 * Global Mixed-mode Technology Inc. G918T12U-GP
		 */
		compatible = "regulator-fixed";

		regulator-name = "VCC_RTC";
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <900000>;

		/*
		 * When the board is powered then the input is VCC3V3,
		 * otherwise power is taken from the coin cell battery.
		 */
		vin-supply = <&vcc_3v3>;
	};

	vddee: regulator-vddee {
		/*
		 * Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz
		 * Synchronous Step Down Regulator. Also called VDDAO
		 * in a part of the schematics.
		 */
		compatible = "pwm-regulator";

		regulator-name = "VDDEE";
		regulator-min-microvolt = <860000>;
		regulator-max-microvolt = <1140000>;

		pwm-supply = <&vcc_5v>;

		pwms = <&pwm_cd 1 1148 0>;
		pwm-dutycycle-range = <100 0>;

		regulator-boot-on;
		regulator-always-on;
	};
};

&aiu {
	status = "okay";

	pinctrl-0 = <&i2s_am_clk_pins>, <&i2s_out_ao_clk_pins>,
		    <&i2s_out_lr_clk_pins>, <&i2s_out_ch01_ao_pins>;
	pinctrl-names = "default";
};

&cpu0 {
	cpu-supply = <&vcck>;
};

&ethmac {
	status = "okay";

	pinctrl-0 = <&eth_rmii_pins>;
	pinctrl-names = "default";

	phy-handle = <&eth_phy0>;
	phy-mode = "rmii";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		eth_phy0: ethernet-phy@0 {
			/* IC Plus IP101A/G (0x02430c54) */
			reg = <0>;

			reset-assert-us = <10000>;
			reset-deassert-us = <10000>;
			reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;

			icplus,select-interrupt;
			interrupt-parent = <&gpio_intc>;
			/* GPIOH_3 */
			interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
		};
	};
};

&i2c_A {
	status = "okay";
	pinctrl-0 = <&i2c_a_pins>;
	pinctrl-names = "default";

	rt5640: codec@1c {
		compatible = "realtek,rt5640";

		reg = <0x1c>;

		#sound-dai-cells = <0>;

		interrupt-parent = <&gpio_intc>;
		interrupts = <13 IRQ_TYPE_EDGE_BOTH>; /* GPIOAO_13 */

		/*
		 * TODO: realtek,ldo1-en-gpios is connected to GPIO_BSD_EN.
		 * We currently cannot configure this pin correctly.
		 * Luckily for us it's in the "right" state by default.
		 */
		realtek,in1-differential;
	};
};

&mali {
	mali-supply = <&vddee>;
};

&saradc {
	status = "okay";
	vref-supply = <&vcc_1v8>;
};

&sdhc {
	status = "okay";

	pinctrl-0 = <&sdxc_c_pins>;
	pinctrl-names = "default";

	bus-width = <8>;
	max-frequency = <50000000>;

	cap-mmc-highspeed;
	disable-wp;
	non-removable;
	no-sdio;

	mmc-pwrseq = <&emmc_pwrseq>;

	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&vcc_3v3>;
};

&sdio {
	status = "okay";

	pinctrl-0 = <&sd_b_pins>;
	pinctrl-names = "default";

	/* SD card */
	sd_card_slot: slot@1 {
		compatible = "mmc-slot";
		reg = <1>;
		status = "okay";

		bus-width = <4>;
		no-sdio;
		cap-mmc-highspeed;
		cap-sd-highspeed;
		disable-wp;

		cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;

		vmmc-supply = <&vcc_3v3>;
	};
};

&gpio_ao {
	gpio-line-names = "Linux_TX", "Linux_RX",
			  "SLP_S5_N", "USB2_OC_FLAG#",
			  "HUB_RST", "USB_PWR_EN",
			  "I2S_IN", "SLP_S1_N",
			  "TCK", "TMS", "TDI", "TDO",
			  "HDMI_CEC", "5640_IRQ",
			  "MUTE", "S805_TEST#";
};

&gpio {
	gpio-line-names = /* Bank GPIOX */
			  "WIFI_SD_D0", "WIFI_SD_D1", "WIFI_SD_D2",
			  "WIFI_SD_D3", "BTPCM_DOUT", "BTPCM_DIN",
			  "BTPCM_SYNC", "BTPCM_CLK", "WIFI_SD_CLK",
			  "WIFI_SD_CMD", "WIFI_32K", "WIFI_PWREN",
			  "UART_B_TX", "UART_B_RX", "UART_B_CTS_N",
			  "UART_B_RTS_N", "BT_EN", "WIFI_WAKE_HOST",
			  /* Bank GPIOY */
			  "", "", "", "", "", "", "", "", "", "",
			  "", "",
			  /* Bank GPIODV */
			  "VCCK_PWM_C", "I2C_SDA_A", "I2C_SCL_A",
			  "I2C_SDA_B", "I2C_SCL_B", "VDDEE_PWM_D",
			  "VDDEE_PWM 3V3_5V_EN",
			  /* Bank GPIOH */
			  "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL",
			  "RMII_IRQ", "RMII_RST#", "RMII_TXD1",
			  "RMII_TXD0", "AV_select_1", "AV_select_2",
			  "MCU_Control_S",
			  /* Bank CARD */
			  "SD_D1_B", "SD_D0_B", "SD_CLK_8726MX",
			  "SD_CMD_8726MX", "SD_D3_B", "SD_D2_B",
			  "CARD_EN_DET (CARD_DET)",
			  /* Bank BOOT */
			  "NAND_D0 (EMMC)", "NAND_D1 (EMMC)",
			  "NAND_D2 (EMMC)", "NAND_D3 (EMMC)",
			  "NAND_D4 (EMMC)", "NAND_D5 (EMMC)",
			  "NAND_D6 (EMMC)", "NAND_D7 (EMMC)",
			  "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)",
			  "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)",
			  "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)",
			  "nWE_S1 NAND_nWE (EMMC)",  "", "", "SPI_CS",
			  /* Bank DIF */
			  "RMII_RXD1", "RMII_RXD0", "RMII_CRS_DV",
			  "RMII_50M_IN", "GPIODIF_4", "GPIODIF_5",
			  "RMII_TXEN", "CPUETH_25MOUT", "RMII_MDC",
			  "RMII_MDIO";
};

&pwm_cd {
	status = "okay";
	pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>, <&xtal>;
	clock-names = "clkin0", "clkin1";
};

&rtc {
	status = "okay";
	clocks = <&rtc32k_xtal>;
	vdd-supply = <&vcc_rtc>;
};

/* exposed through the pin headers labeled "URDUG1" on the top of the PCB */
&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
};

/*
 * connected to the Bluetooth part of the RTL8723BS SDIO wifi / Bluetooth
 * combo chip. This is only available on the variant with 2GB RAM.
 */
&uart_B {
	status = "okay";
	pinctrl-0 = <&uart_b0_pins>, <&uart_b0_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;
};

&usb1 {
	status = "okay";
	vbus-supply = <&usb_vbus>;
};

&usb1_phy {
	status = "okay";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright 2015 Endless Mobile, Inc.
 * Author: Carlo Caione <carlo@endlessm.com>
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>

#include "meson8b.dtsi"

/ {
	model = "TRONFY MXQ S805";
	compatible = "tronfy,mxq", "amlogic,meson8b";

	aliases {
		serial0 = &uart_AO;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x40000000 0x40000000>;
	};

	vcck: regulator-vcck {
		compatible = "pwm-regulator";

		regulator-name = "VCCK";
		regulator-min-microvolt = <860000>;
		regulator-max-microvolt = <1140000>;

		pwm-supply = <&vcc_5v>;

		pwms = <&pwm_cd 0 1148 0>;
		pwm-dutycycle-range = <100 0>;

		regulator-boot-on;
		regulator-always-on;
	};

	vcc_1v8: regulator-vcc1v8 {
		compatible = "regulator-fixed";

		regulator-name = "VCC1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;

		vin-supply = <&vcc_3v3>;
	};

	vcc_3v3: regulator-vcc3v3 {
		compatible = "regulator-fixed";

		regulator-name = "VCC3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		vin-supply = <&vcc_5v>;
	};

	vcc_5v: regulator-vcc5v {
		compatible = "regulator-fixed";

		regulator-name = "VCC5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;

		regulator-boot-on;
		regulator-always-on;
	};

	vddee: regulator-vddee {
		compatible = "pwm-regulator";

		regulator-name = "VDDEE";
		regulator-min-microvolt = <860000>;
		regulator-max-microvolt = <1140000>;

		pwm-supply = <&vcc_5v>;

		pwms = <&pwm_cd 1 1148 0>;
		pwm-dutycycle-range = <100 0>;

		regulator-boot-on;
		regulator-always-on;
	};
};

&cpu0 {
	cpu-supply = <&vcck>;
};

&ethmac {
	status = "okay";

	pinctrl-0 = <&eth_rmii_pins>;
	pinctrl-names = "default";

	phy-handle = <&eth_phy0>;
	phy-mode = "rmii";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		eth_phy0: ethernet-phy@0 {
			/* IC Plus IP101A/G (0x02430c54) */
			reg = <0>;

			reset-assert-us = <10000>;
			reset-deassert-us = <10000>;
			reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;

			icplus,select-interrupt;
			interrupt-parent = <&gpio_intc>;
			/* GPIOH_3 */
			interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
		};
	};
};

&mali {
	mali-supply = <&vddee>;
};

&saradc {
	status = "okay";
	vref-supply = <&vcc_1v8>;
};

&sdio {
	status = "okay";

	pinctrl-0 = <&sd_b_pins>;
	pinctrl-names = "default";

	/* SD card */
	sd_card_slot: slot@1 {
		compatible = "mmc-slot";
		reg = <1>;
		status = "okay";

		bus-width = <4>;
		no-sdio;
		cap-mmc-highspeed;
		cap-sd-highspeed;
		disable-wp;

		cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;

		vmmc-supply = <&vcc_3v3>;
	};
};

&pwm_cd {
	status = "okay";
	pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>, <&xtal>;
	clock-names = "clkin0", "clkin1";
};

&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
};

&usb0 {
	status = "okay";
};

&usb0_phy {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&usb1_phy {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright 2015 Endless Mobile, Inc.
 * Author: Carlo Caione <carlo@endlessm.com>
 */

/dts-v1/;
#include "meson8b.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Hardkernel ODROID-C1";
	compatible = "hardkernel,odroid-c1", "amlogic,meson8b";

	aliases {
		serial0 = &uart_AO;
		mmc0 = &sd_card_slot;
		mmc1 = &sdhc;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x40000000 0x40000000>;
	};

	emmc_pwrseq: emmc-pwrseq {
		compatible = "mmc-pwrseq-emmc";
		reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
	};

	leds {
		compatible = "gpio-leds";
		blue {
			label = "c1:blue:alive";
			gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
			default-state = "off";
		};
	};

	p5v0: regulator-p5v0 {
		compatible = "regulator-fixed";

		regulator-name = "P5V0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	tflash_vdd: regulator-tflash_vdd {
		/*
		 * signal name from schematics: TFLASH_VDD_EN
		 */
		compatible = "regulator-fixed";

		regulator-name = "TFLASH_VDD";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		vin-supply = <&vcc_3v3>;

		gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	tf_io: gpio-regulator-tf_io {
		compatible = "regulator-gpio";

		regulator-name = "TF_IO";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;

		vin-supply = <&vcc_3v3>;

		/*
		 * signal name from schematics: TF_3V3N_1V8_EN
		 */
		gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
		gpios-states = <0>;

		states = <3300000 0
			  1800000 1>;
	};

	rtc32k_xtal: rtc32k-xtal-clk {
		/* X3 in the schematics */
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "RTC32K";
		#clock-cells = <0>;
	};

	vcc_1v8: regulator-vcc-1v8 {
		/*
		 * RICHTEK RT9179 configured for a fixed output voltage of
		 * 1.8V. This supplies not only VCC1V8 but also IOREF_1V8 and
		 * VDD1V8 according to the schematics.
		 */
		compatible = "regulator-fixed";

		regulator-name = "VCC1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;

		vin-supply = <&p5v0>;
	};

	vcc_3v3: regulator-vcc-3v3 {
		/*
		 * Monolithic Power Systems MP2161 configured for a fixed
		 * output voltage of 3.3V. This supplies not only VCC3V3 but
		 * also VDD3V3 and VDDIO_AO3V3 according to the schematics.
		 */
		compatible = "regulator-fixed";

		regulator-name = "VCC3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		vin-supply = <&p5v0>;
	};

	vcck: regulator-vcck {
		/* Monolithic Power Systems MP2161 */
		compatible = "pwm-regulator";

		regulator-name = "VCCK";
		regulator-min-microvolt = <860000>;
		regulator-max-microvolt = <1140000>;

		pwm-supply = <&p5v0>;

		pwms = <&pwm_cd 0 12218 0>;
		pwm-dutycycle-range = <91 0>;

		regulator-boot-on;
		regulator-always-on;
	};

	vddc_ddr: regulator-vddc-ddr {
		/*
		 * Monolithic Power Systems MP2161 configured for a fixed
		 * output voltage of 1.5V. This supplies not only DDR_VDDC but
		 * also DDR3_1V5 according to the schematics.
		 */
		compatible = "regulator-fixed";

		regulator-name = "DDR_VDDC";
		regulator-min-microvolt = <1500000>;
		regulator-max-microvolt = <1500000>;

		vin-supply = <&p5v0>;
	};

	vddee: regulator-vddee {
		/* Monolithic Power Systems MP2161 */
		compatible = "pwm-regulator";

		regulator-name = "VDDEE";
		regulator-min-microvolt = <860000>;
		regulator-max-microvolt = <1140000>;

		pwm-supply = <&p5v0>;

		pwms = <&pwm_cd 1 12218 0>;
		pwm-dutycycle-range = <91 0>;

		regulator-boot-on;
		regulator-always-on;
	};

	vdd_rtc: regulator-vdd-rtc {
		/*
		 * Torex Semiconductor XC6215 configured for a fixed output of
		 * 0.9V.
		 */
		compatible = "regulator-fixed";

		regulator-name = "VDD_RTC";
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <900000>;

		vin-supply = <&vcc_3v3>;
	};
};

&cpu0 {
	cpu-supply = <&vcck>;
};

&efuse {
	ethernet_mac_address: mac@1b4 {
		reg = <0x1b4 0x6>;
	};
};

&ethmac {
	status = "okay";

	pinctrl-0 = <&eth_rgmii_pins>;
	pinctrl-names = "default";

	phy-handle = <&eth_phy>;
	phy-mode = "rgmii-id";

	nvmem-cells = <&ethernet_mac_address>;
	nvmem-cell-names = "mac-address";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		/* Realtek RTL8211F (0x001cc916) */
		eth_phy: ethernet-phy@0 {
			reg = <0>;

			reset-assert-us = <10000>;
			reset-deassert-us = <80000>;
			reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;

			interrupt-parent = <&gpio_intc>;
			/* GPIOH_3 */
			interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
		};
	};
};

&gpio {
	gpio-line-names = /* Bank GPIOX */
			  "J2 Header Pin 35", "J2 Header Pin 36",
			  "J2 Header Pin 32", "J2 Header Pin 31",
			  "J2 Header Pin 29", "J2 Header Pin 18",
			  "J2 Header Pin 22", "J2 Header Pin 16",
			  "J2 Header Pin 23", "J2 Header Pin 21",
			  "J2 Header Pin 19", "J2 Header Pin 33",
			  "J2 Header Pin 8", "J2 Header Pin 10",
			  "J2 Header Pin 15", "J2 Header Pin 13",
			  "J2 Header Pin 24", "J2 Header Pin 26",
			  /* Bank GPIOY */
			  "Revision (upper)", "Revision (lower)",
			  "J2 Header Pin 7", "", "J2 Header Pin 12",
			  "J2 Header Pin 11", "", "", "",
			  "TFLASH_VDD_EN", "", "",
			  /* Bank GPIODV */
			  "VCCK_PWM (PWM_C)", "I2CA_SDA", "I2CA_SCL",
			  "I2CB_SDA", "I2CB_SCL", "VDDEE_PWM (PWM_D)",
			  "",
			  /* Bank GPIOH */
			  "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL",
			  "ETH_PHY_INTR", "ETH_PHY_NRST", "ETH_TXD1",
			  "ETH_TXD0", "ETH_TXD3", "ETH_TXD2",
			  "ETH_RGMII_TX_CLK",
			  /* Bank CARD */
			  "SD_DATA1 (SDB_D1)", "SD_DATA0 (SDB_D0)",
			  "SD_CLK",  "SD_CMD", "SD_DATA3 (SDB_D3)",
			  "SD_DATA2 (SDB_D2)", "SD_CDN (SD_DET_N)",
			  /* Bank BOOT */
			  "SDC_D0 (EMMC)", "SDC_D1 (EMMC)",
			  "SDC_D2 (EMMC)", "SDC_D3 (EMMC)",
			  "SDC_D4 (EMMC)", "SDC_D5 (EMMC)",
			  "SDC_D6 (EMMC)", "SDC_D7 (EMMC)",
			  "SDC_CLK (EMMC)", "SDC_RSTn (EMMC)",
			  "SDC_CMD (EMMC)", "BOOT_SEL", "", "", "",
			  "", "", "", "",
			  /* Bank DIF */
			  "ETH_RXD1", "ETH_RXD0", "ETH_RX_DV",
			  "RGMII_RX_CLK", "ETH_RXD3", "ETH_RXD2",
			  "ETH_TXEN", "ETH_PHY_REF_CLK_25MOUT",
			  "ETH_MDC", "ETH_MDIO";
};

&gpio_ao {
	gpio-line-names = "UART TX", "UART RX", "",
			  "TF_3V3N_1V8_EN", "USB_HUB_RST_N",
			  "USB_OTG_PWREN", "J7 Header Pin 2",
			  "IR_IN", "J7 Header Pin 4",
			  "J7 Header Pin 6", "J7 Header Pin 5",
			  "J7 Header Pin 7", "HDMI_CEC",
			  "SYS_LED", "", "";

	/*
	 * WARNING: The USB Hub on the Odroid-C1/C1+ needs a reset signal
	 * to be turned high in order to be detected by the USB Controller.
	 * This signal should be handled by a USB specific power sequence
	 * in order to reset the Hub when USB bus is powered down.
	 */
	usb-hub {
		gpio-hog;
		gpios = <GPIOAO_4 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "usb-hub-reset";
	};
};

&ir_receiver {
	status = "okay";
	pinctrl-0 = <&ir_recv_pins>;
	pinctrl-names = "default";
};

&mali {
	mali-supply = <&vddee>;
};

&saradc {
	status = "okay";
	vref-supply = <&vcc_1v8>;
};

&sdhc {
	status = "okay";

	pinctrl-0 = <&sdxc_c_pins>;
	pinctrl-names = "default";

	bus-width = <8>;
	max-frequency = <100000000>;

	disable-wp;
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	no-sdio;

	mmc-pwrseq = <&emmc_pwrseq>;

	vmmc-supply = <&vcc_3v3>;
	vqmmc-supply = <&vcc_1v8>;
};

&sdio {
	status = "okay";

	pinctrl-0 = <&sd_b_pins>;
	pinctrl-names = "default";

	/* SD card */
	sd_card_slot: slot@1 {
		compatible = "mmc-slot";
		reg = <1>;
		status = "okay";

		bus-width = <4>;
		no-sdio;
		cap-mmc-highspeed;
		cap-sd-highspeed;
		disable-wp;

		cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;

		vmmc-supply = <&tflash_vdd>;
		vqmmc-supply = <&tf_io>;
	};
};

&pwm_cd {
	status = "okay";
	pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
	pinctrl-names = "default";
	clocks = <&xtal>, <&xtal>;
	clock-names = "clkin0", "clkin1";
};

&rtc {
	/* needs to be enabled manually when a battery is connected */
	clocks = <&rtc32k_xtal>;
	vdd-supply = <&vdd_rtc>;
};

&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
};

&usb1_phy {
	status = "okay";
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright 2015 Endless Mobile, Inc.
 * Author: Carlo Caione <carlo@endlessm.com>
 */

#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8b-gpio.h>
#include <dt-bindings/power/meson8-power.h>
#include <dt-bindings/reset/amlogic,meson8b-reset.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
#include <dt-bindings/thermal/thermal.h>
#include "meson.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			next-level-cache = <&L2>;
			reg = <0x200>;
			enable-method = "amlogic,meson8b-smp";
			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
			operating-points-v2 = <&cpu_opp_table>;
			clocks = <&clkc CLKID_CPUCLK>;
			#cooling-cells = <2>; /* min followed by max */
		};

		cpu1: cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			next-level-cache = <&L2>;
			reg = <0x201>;
			enable-method = "amlogic,meson8b-smp";
			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
			operating-points-v2 = <&cpu_opp_table>;
			clocks = <&clkc CLKID_CPUCLK>;
			#cooling-cells = <2>; /* min followed by max */
		};

		cpu2: cpu@202 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			next-level-cache = <&L2>;
			reg = <0x202>;
			enable-method = "amlogic,meson8b-smp";
			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
			operating-points-v2 = <&cpu_opp_table>;
			clocks = <&clkc CLKID_CPUCLK>;
			#cooling-cells = <2>; /* min followed by max */
		};

		cpu3: cpu@203 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			next-level-cache = <&L2>;
			reg = <0x203>;
			enable-method = "amlogic,meson8b-smp";
			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
			operating-points-v2 = <&cpu_opp_table>;
			clocks = <&clkc CLKID_CPUCLK>;
			#cooling-cells = <2>; /* min followed by max */
		};
	};

	cpu_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-96000000 {
			opp-hz = /bits/ 64 <96000000>;
			opp-microvolt = <860000>;
		};
		opp-192000000 {
			opp-hz = /bits/ 64 <192000000>;
			opp-microvolt = <860000>;
		};
		opp-312000000 {
			opp-hz = /bits/ 64 <312000000>;
			opp-microvolt = <860000>;
		};
		opp-408000000 {
			opp-hz = /bits/ 64 <408000000>;
			opp-microvolt = <860000>;
		};
		opp-504000000 {
			opp-hz = /bits/ 64 <504000000>;
			opp-microvolt = <860000>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <860000>;
		};
		opp-720000000 {
			opp-hz = /bits/ 64 <720000000>;
			opp-microvolt = <860000>;
		};
		opp-816000000 {
			opp-hz = /bits/ 64 <816000000>;
			opp-microvolt = <900000>;
		};
		opp-1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <1140000>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <1140000>;
		};
		opp-1320000000 {
			opp-hz = /bits/ 64 <1320000000>;
			opp-microvolt = <1140000>;
		};
		opp-1488000000 {
			opp-hz = /bits/ 64 <1488000000>;
			opp-microvolt = <1140000>;
		};
		opp-1536000000 {
			opp-hz = /bits/ 64 <1536000000>;
			opp-microvolt = <1140000>;
		};
	};

	gpu_opp_table: gpu-opp-table {
		compatible = "operating-points-v2";

		opp-255000000 {
			opp-hz = /bits/ 64 <255000000>;
			opp-microvolt = <1100000>;
		};
		opp-364285714 {
			opp-hz = /bits/ 64 <364285714>;
			opp-microvolt = <1100000>;
		};
		opp-425000000 {
			opp-hz = /bits/ 64 <425000000>;
			opp-microvolt = <1100000>;
		};
		opp-510000000 {
			opp-hz = /bits/ 64 <510000000>;
			opp-microvolt = <1100000>;
		};
		opp-637500000 {
			opp-hz = /bits/ 64 <637500000>;
			opp-microvolt = <1100000>;
			turbo-mode;
		};
	};

	pmu {
		compatible = "arm,cortex-a5-pmu";
		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* 2 MiB reserved for Hardware ROM Firmware? */
		hwrom@0 {
			reg = <0x0 0x200000>;
			no-map;
		};
	};

	thermal-zones {
		soc {
			polling-delay-passive = <250>; /* milliseconds */
			polling-delay = <1000>; /* milliseconds */
			thermal-sensors = <&thermal_sensor>;

			cooling-maps {
				map0 {
					trip = <&soc_passive>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};

				map1 {
					trip = <&soc_hot>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				soc_passive: soc-passive {
					temperature = <80000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "passive";
				};

				soc_hot: soc-hot {
					temperature = <90000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "hot";
				};

				soc_critical: soc-critical {
					temperature = <110000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "critical";
				};
			};
		};
	};

	mmcbus: bus@c8000000 {
		compatible = "simple-bus";
		reg = <0xc8000000 0x8000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0xc8000000 0x8000>;

		ddr_clkc: clock-controller@400 {
			compatible = "amlogic,meson8b-ddr-clkc";
			reg = <0x400 0x20>;
			clocks = <&xtal>;
			clock-names = "xtal";
			#clock-cells = <1>;
		};

		dmcbus: bus@6000 {
			compatible = "simple-bus";
			reg = <0x6000 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x6000 0x400>;

			canvas: video-lut@48 {
				compatible = "amlogic,meson8b-canvas",
					     "amlogic,canvas";
				reg = <0x48 0x14>;
			};
		};
	};

	apb: bus@d0000000 {
		compatible = "simple-bus";
		reg = <0xd0000000 0x200000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0xd0000000 0x200000>;

		mali: gpu@c0000 {
			compatible = "amlogic,meson8b-mali", "arm,mali-450";
			reg = <0xc0000 0x40000>;
			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gp", "gpmmu", "pp", "pmu",
					  "pp0", "ppmmu0", "pp1", "ppmmu1";
			resets = <&reset RESET_MALI>;
			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
			clock-names = "bus", "core";
			operating-points-v2 = <&gpu_opp_table>;
			#cooling-cells = <2>; /* min followed by max */
		};
	};
}; /* end of / */

&aiu {
	compatible = "amlogic,aiu-meson8b", "amlogic,aiu";
	clocks = <&clkc CLKID_AIU_GLUE>,
		 <&clkc CLKID_I2S_OUT>,
		 <&clkc CLKID_AOCLK_GATE>,
		 <&clkc CLKID_CTS_AMCLK>,
		 <&clkc CLKID_MIXER_IFACE>,
		 <&clkc CLKID_IEC958>,
		 <&clkc CLKID_IEC958_GATE>,
		 <&clkc CLKID_CTS_MCLK_I958>,
		 <&clkc CLKID_CTS_I958>;
	clock-names = "pclk",
		      "i2s_pclk",
		      "i2s_aoclk",
		      "i2s_mclk",
		      "i2s_mixer",
		      "spdif_pclk",
		      "spdif_aoclk",
		      "spdif_mclk",
		      "spdif_mclk_sel";
	resets = <&reset RESET_AIU>;
};

&aobus {
	pmu: pmu@e0 {
		compatible = "amlogic,meson8b-pmu", "syscon";
		reg = <0xe0 0x18>;
	};

	pinctrl_aobus: pinctrl@84 {
		compatible = "amlogic,meson8b-aobus-pinctrl";
		reg = <0x84 0xc>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio_ao: ao-bank@14 {
			reg = <0x14 0x4>,
				<0x2c 0x4>,
				<0x24 0x8>;
			reg-names = "mux", "pull", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_aobus 0 0 16>;
		};

		i2s_am_clk_pins: i2s-am-clk-out {
			mux {
				groups = "i2s_am_clk_out";
				function = "i2s";
				bias-disable;
			};
		};

		i2s_out_ao_clk_pins: i2s-ao-clk-out {
			mux {
				groups = "i2s_ao_clk_out";
				function = "i2s";
				bias-disable;
			};
		};

		i2s_out_lr_clk_pins: i2s-lr-clk-out {
			mux {
				groups = "i2s_lr_clk_out";
				function = "i2s";
				bias-disable;
			};
		};

		i2s_out_ch01_ao_pins: i2s-out-ch01 {
			mux {
				groups = "i2s_out_01";
				function = "i2s";
				bias-disable;
			};
		};

		spdif_out_1_pins: spdif-out-1 {
			mux {
				groups = "spdif_out_1";
				function = "spdif_1";
				bias-disable;
			};
		};

		uart_ao_a_pins: uart_ao_a {
			mux {
				groups = "uart_tx_ao_a", "uart_rx_ao_a";
				function = "uart_ao";
				bias-disable;
			};
		};

		ir_recv_pins: remote {
			mux {
				groups = "remote_input";
				function = "remote";
				bias-disable;
			};
		};
	};
};

&ao_arc_rproc {
	compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc";
	amlogic,secbus2 = <&secbus2>;
	sram = <&ao_arc_sram>;
	resets = <&reset RESET_MEDIA_CPU>;
	clocks = <&clkc CLKID_AO_MEDIA_CPU>;
};

&cbus {
	reset: reset-controller@4404 {
		compatible = "amlogic,meson8b-reset";
		reg = <0x4404 0x9c>;
		#reset-cells = <1>;
	};

	analog_top: analog-top@81a8 {
		compatible = "amlogic,meson8b-analog-top", "syscon";
		reg = <0x81a8 0x14>;
	};

	pwm_ef: pwm@86c0 {
		compatible = "amlogic,meson8b-pwm";
		reg = <0x86c0 0x10>;
		#pwm-cells = <3>;
		status = "disabled";
	};

	clock-measure@8758 {
		compatible = "amlogic,meson8b-clk-measure";
		reg = <0x8758 0x1c>;
	};

	pinctrl_cbus: pinctrl@9880 {
		compatible = "amlogic,meson8b-cbus-pinctrl";
		reg = <0x9880 0x10>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio: banks@80b0 {
			reg = <0x80b0 0x28>,
				<0x80e8 0x18>,
				<0x8120 0x18>,
				<0x8030 0x38>;
			reg-names = "mux", "pull", "pull-enable", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_cbus 0 0 83>;
		};

		eth_rgmii_pins: eth-rgmii {
			mux {
				groups = "eth_tx_clk",
					 "eth_tx_en",
					 "eth_txd1_0",
					 "eth_txd0_0",
					 "eth_rx_clk",
					 "eth_rx_dv",
					 "eth_rxd1",
					 "eth_rxd0",
					 "eth_mdio_en",
					 "eth_mdc",
					 "eth_ref_clk",
					 "eth_txd2",
					 "eth_txd3",
					 "eth_rxd3",
					 "eth_rxd2";
				function = "ethernet";
				bias-disable;
			};
		};

		eth_rmii_pins: eth-rmii {
			mux {
				groups = "eth_tx_en",
					 "eth_txd1_0",
					 "eth_txd0_0",
					 "eth_rx_clk",
					 "eth_rx_dv",
					 "eth_rxd1",
					 "eth_rxd0",
					 "eth_mdio_en",
					 "eth_mdc";
				function = "ethernet";
				bias-disable;
			};
		};

		i2c_a_pins: i2c-a {
			mux {
				groups = "i2c_sda_a", "i2c_sck_a";
				function = "i2c_a";
				bias-disable;
			};
		};

		sd_b_pins: sd-b {
			mux {
				groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
					"sd_d3_b", "sd_clk_b", "sd_cmd_b";
				function = "sd_b";
				bias-disable;
			};
		};

		sdxc_c_pins: sdxc-c {
			mux {
				groups = "sdxc_d0_c", "sdxc_d13_c",
					 "sdxc_d47_c", "sdxc_clk_c",
					 "sdxc_cmd_c";
				function = "sdxc_c";
				bias-pull-up;
			};
		};

		pwm_c1_pins: pwm-c1 {
			mux {
				groups = "pwm_c1";
				function = "pwm_c";
				bias-disable;
			};
		};

		pwm_d_pins: pwm-d {
			mux {
				groups = "pwm_d";
				function = "pwm_d";
				bias-disable;
			};
		};

		uart_b0_pins: uart-b0 {
			mux {
				groups = "uart_tx_b0",
				       "uart_rx_b0";
				function = "uart_b";
				bias-disable;
			};
		};

		uart_b0_cts_rts_pins: uart-b0-cts-rts {
			mux {
				groups = "uart_cts_b0",
				       "uart_rts_b0";
				function = "uart_b";
				bias-disable;
			};
		};
	};
};

&ahb_sram {
	ao_arc_sram: ao-arc-sram@0 {
		compatible = "amlogic,meson8b-ao-arc-sram";
		reg = <0x0 0x8000>;
		pool;
	};

	smp-sram@1ff80 {
		compatible = "amlogic,meson8b-smp-sram";
		reg = <0x1ff80 0x8>;
	};
};

&efuse {
	compatible = "amlogic,meson8b-efuse";
	clocks = <&clkc CLKID_EFUSE>;
	clock-names = "core";

	temperature_calib: calib@1f4 {
		/* only the upper two bytes are relevant */
		reg = <0x1f4 0x4>;
	};
};

&ethmac {
	compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";

	reg = <0xc9410000 0x10000
	       0xc1108140 0x4>;

	clocks = <&clkc CLKID_ETH>,
		 <&clkc CLKID_MPLL2>,
		 <&clkc CLKID_MPLL2>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
	rx-fifo-depth = <4096>;
	tx-fifo-depth = <2048>;

	resets = <&reset RESET_ETHERNET>;
	reset-names = "stmmaceth";

	power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
};

&gpio_intc {
	compatible = "amlogic,meson-gpio-intc",
		     "amlogic,meson8b-gpio-intc";
	status = "okay";
};

&hhi {
	clkc: clock-controller {
		compatible = "amlogic,meson8b-clkc";
		clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
		clock-names = "xtal", "ddr_pll";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pwrc: power-controller {
		compatible = "amlogic,meson8b-pwrc";
		#power-domain-cells = <1>;
		amlogic,ao-sysctrl = <&pmu>;
		resets = <&reset RESET_DBLK>,
			 <&reset RESET_PIC_DC>,
			 <&reset RESET_HDMI_APB>,
			 <&reset RESET_HDMI_SYSTEM_RESET>,
			 <&reset RESET_VENCI>,
			 <&reset RESET_VENCP>,
			 <&reset RESET_VDAC_4>,
			 <&reset RESET_VENCL>,
			 <&reset RESET_VIU>,
			 <&reset RESET_VENC>,
			 <&reset RESET_RDMA>;
		reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
			      "venci", "vencp", "vdac", "vencl", "viu",
			      "venc", "rdma";
		clocks = <&clkc CLKID_VPU>;
		clock-names = "vpu";
		assigned-clocks = <&clkc CLKID_VPU>;
		assigned-clock-rates = <182142857>;
	};
};

&hwrng {
	compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
	clocks = <&clkc CLKID_RNG0>;
	clock-names = "core";
};

&i2c_AO {
	clocks = <&clkc CLKID_CLK81>;
};

&i2c_A {
	clocks = <&clkc CLKID_I2C>;
};

&i2c_B {
	clocks = <&clkc CLKID_I2C>;
};

&L2 {
	arm,data-latency = <3 3 3>;
	arm,tag-latency = <2 2 2>;
	arm,filter-ranges = <0x100000 0xc0000000>;
	prefetch-data = <1>;
	prefetch-instr = <1>;
	arm,shared-override;
};

&periph {
	scu@0 {
		compatible = "arm,cortex-a5-scu";
		reg = <0x0 0x100>;
	};

	timer@200 {
		compatible = "arm,cortex-a5-global-timer";
		reg = <0x200 0x20>;
		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&clkc CLKID_PERIPH>;

		/*
		 * the arm_global_timer driver currently does not handle clock
		 * rate changes. Keep it disabled for now.
		 */
		status = "disabled";
	};

	timer@600 {
		compatible = "arm,cortex-a5-twd-timer";
		reg = <0x600 0x20>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&clkc CLKID_PERIPH>;
	};
};

&pwm_ab {
	compatible = "amlogic,meson8b-pwm";
};

&pwm_cd {
	compatible = "amlogic,meson8b-pwm";
};

&rtc {
	compatible = "amlogic,meson8b-rtc";
	resets = <&reset RESET_RTC>;
};

&saradc {
	compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
	clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
	clock-names = "clkin", "core";
	amlogic,hhi-sysctrl = <&hhi>;
	nvmem-cells = <&temperature_calib>;
	nvmem-cell-names = "temperature_calib";
};

&sdhc {
	compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
	clocks = <&xtal>,
		 <&clkc CLKID_FCLK_DIV4>,
		 <&clkc CLKID_FCLK_DIV3>,
		 <&clkc CLKID_FCLK_DIV5>,
		 <&clkc CLKID_SDHC>;
	clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
};

&secbus {
	secbus2: system-controller@4000 {
		compatible = "amlogic,meson8b-secbus2", "syscon";
		reg = <0x4000 0x2000>;
	};
};

&sdio {
	compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
	clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
	clock-names = "core", "clkin";
};

&timer_abcde {
	clocks = <&xtal>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "pclk";
};

&uart_AO {
	compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart";
	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_A {
	compatible = "amlogic,meson8b-uart";
	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_B {
	compatible = "amlogic,meson8b-uart";
	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "pclk", "baud";
};

&uart_C {
	compatible = "amlogic,meson8b-uart";
	clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
	clock-names = "xtal", "pclk", "baud";
};

&usb0 {
	compatible = "amlogic,meson8b-usb", "snps,dwc2";
	clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
	clock-names = "otg";
};

&usb1 {
	compatible = "amlogic,meson8b-usb", "snps,dwc2";
	clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
	clock-names = "otg";
};

&usb0_phy {
	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
	clock-names = "usb_general", "usb";
	resets = <&reset RESET_USB_OTG>;
};

&usb1_phy {
	compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
	clock-names = "usb_general", "usb";
	resets = <&reset RESET_USB_OTG>;
};

&wdt {
	compatible = "amlogic,meson8b-wdt";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2018 Oleg Ivanov <balbes-150@yandex.ru>
 * Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
 */

/dts-v1/;

#include "meson8m2.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "Tronsmart MXIII Plus";
	compatible = "tronsmart,mxiii-plus", "amlogic,meson8m2";

	aliases {
		ethernet0 = &ethmac;
		i2c0 = &i2c_AO;
		serial0 = &uart_AO;
		serial1 = &uart_A;
		mmc0 = &sd_card_slot;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x40000000 0x80000000>;
	};

	adc-keys {
		compatible = "adc-keys";
		io-channels = <&saradc 0>;
		io-channel-names = "buttons";
		keyup-threshold-microvolt = <1710000>;

		button-function {
			label = "Function";
			linux,code = <KEY_FN>;
			press-threshold-microvolt = <10000>;
		};
	};

	vcc_3v3: regulator-vcc3v3 {
		compatible = "regulator-fixed";
		regulator-name = "VCC3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&cpu0 {
	cpu-supply = <&vcck>;
};

&ethmac {
	status = "okay";

	pinctrl-0 = <&eth_rgmii_pins>;
	pinctrl-names = "default";

	phy-handle = <&eth_phy0>;
	phy-mode = "rgmii-id";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		eth_phy0: ethernet-phy@0 {
			/* Realtek RTL8211F (0x001cc916) */
			reg = <0>;

			reset-assert-us = <10000>;
			reset-deassert-us = <80000>;
			reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>;
		};
	};
};

&ir_receiver {
	status = "okay";
	pinctrl-0 = <&ir_recv_pins>;
	pinctrl-names = "default";
};

&i2c_AO {
	status = "okay";
	pinctrl-0 = <&i2c_ao_pins>;
	pinctrl-names = "default";

	pmic@32 {
		compatible = "ricoh,rn5t618";
		reg = <0x32>;
		system-power-controller;

		regulators {
			vcck: DCDC1 {
				regulator-name = "VCCK";
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vddee: DCDC2 {
				/* the output is also used as VDDAO */
				regulator-name = "VDD_EE";
				regulator-min-microvolt = <950000>;
				regulator-max-microvolt = <1150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			DCDC3 {
				regulator-name = "VDD_DDR";
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <1500000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO1 {
				regulator-name = "VDDIO_AO28";
				regulator-min-microvolt = <2900000>;
				regulator-max-microvolt = <2900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vddio_ao1v8: LDO2 {
				regulator-name = "VDDIO_AO18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO3 {
				regulator-name = "VCC1V8";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO4 {
				regulator-name = "VCC2V8";
				regulator-min-microvolt = <2850000>;
				regulator-max-microvolt = <2850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO5 {
				regulator-name = "AVDD1V8";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDORTC1 {
				regulator-name = "VDD_LDO";
				regulator-min-microvolt = <2700000>;
				regulator-max-microvolt = <2700000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDORTC2 {
				regulator-name = "RTC_0V9";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&mali {
	mali-supply = <&vddee>;
};

&saradc {
	status = "okay";
	vref-supply = <&vddio_ao1v8>;
};

&sdio {
	status = "okay";

	pinctrl-0 = <&sd_b_pins>;
	pinctrl-names = "default";

	/* SD card */
	sd_card_slot: slot@1 {
		compatible = "mmc-slot";
		reg = <1>;
		status = "okay";

		bus-width = <4>;
		no-sdio;
		cap-mmc-highspeed;
		cap-sd-highspeed;
		disable-wp;

		cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;

		vmmc-supply = <&vcc_3v3>;
	};
};

/* connected to the Bluetooth module */
&uart_A {
	status = "okay";
	pinctrl-0 = <&uart_a1_pins>, <&uart_a1_cts_rts_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;
};

&uart_AO {
	status = "okay";
	pinctrl-0 = <&uart_ao_a_pins>;
	pinctrl-names = "default";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&usb0_phy {
	status = "okay";
};

&usb1_phy {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
 */

#include "meson8.dtsi"

/ {
	model = "Amlogic Meson8m2 SoC";
	compatible = "amlogic,meson8m2";
}; /* end of / */

&clkc {
	compatible = "amlogic,meson8m2-clkc", "amlogic,meson8-clkc";
};

&dmcbus {
	/* the offset of the canvas registers has changed compared to Meson8 */
	/delete-node/ video-lut@20;

	canvas: video-lut@48 {
		compatible = "amlogic,meson8m2-canvas", "amlogic,canvas";
		reg = <0x48 0x14>;
	};
};

&ethmac {
	compatible = "amlogic,meson8m2-dwmac", "snps,dwmac";
	reg = <0xc9410000 0x10000
		0xc1108140 0x8>;
	clocks = <&clkc CLKID_ETH>,
		 <&clkc CLKID_MPLL2>,
		 <&clkc CLKID_MPLL2>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
	resets = <&reset RESET_ETHERNET>;
	reset-names = "stmmaceth";
};

&pinctrl_aobus {
	compatible = "amlogic,meson8m2-aobus-pinctrl",
		     "amlogic,meson8-aobus-pinctrl";
};

&pinctrl_cbus {
	compatible = "amlogic,meson8m2-cbus-pinctrl",
		     "amlogic,meson8-cbus-pinctrl";

	eth_rgmii_pins: ethernet {
		mux {
			groups = "eth_tx_clk_50m", "eth_tx_en",
				 "eth_txd3", "eth_txd2",
				 "eth_txd1", "eth_txd0",
				 "eth_rx_clk_in", "eth_rx_dv",
				 "eth_rxd3", "eth_rxd2",
				 "eth_rxd1", "eth_rxd0",
				 "eth_mdio", "eth_mdc";
			function = "ethernet";
			bias-disable;
		};
	};
};

&pwrc {
	compatible = "amlogic,meson8m2-pwrc";
	resets = <&reset RESET_DBLK>,
		 <&reset RESET_PIC_DC>,
		 <&reset RESET_HDMI_APB>,
		 <&reset RESET_HDMI_SYSTEM_RESET>,
		 <&reset RESET_VENCI>,
		 <&reset RESET_VENCP>,
		 <&reset RESET_VDAC_4>,
		 <&reset RESET_VENCL>,
		 <&reset RESET_VIU>,
		 <&reset RESET_VENC>,
		 <&reset RESET_RDMA>;
	reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci",
		      "vencp", "vdac", "vencl", "viu", "venc", "rdma";
	assigned-clocks = <&clkc CLKID_VPU>;
	assigned-clock-rates = <364000000>;
};

&saradc {
	compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
};

&sdhc {
	compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc";
};

&usb0_phy {
	compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
};

&usb1_phy {
	compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy";
};

&wdt {
	compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
};


code:
// SPDX-License-Identifier: GPL-2.0
/* Socionext Milbeaut M10V Evaluation Board */
/dts-v1/;
#include "milbeaut-m10v.dtsi"

/ {
	model = "Socionext M10V EVB";
	compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a";

	aliases {
		serial0 = &uart1;
	};

	chosen {
		bootargs = "rootwait earlycon";
		stdout-path = "serial0:115200n8";
	};

	clocks {
		uclk40xi: uclk40xi {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <40000000>;
		};
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000  0x80000000>;
	};

};


code:
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "socionext,sc2000a";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "socionext,milbeaut-m10v-smp";
		cpu@f00 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf00>;
		};
		cpu@f01 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf01>;
		};
		cpu@f02 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf02>;
		};
		cpu@f03 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf03>;
		};
	};

	timer { /* The Generic Timer */
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			<GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			<GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			<GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <40000000>;
		always-on;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&gic>;

		gic: interrupt-controller@1d000000 {
			compatible = "arm,cortex-a7-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x1d001000 0x1000>,
			      <0x1d002000 0x1000>; /* CPU I/f base and size */
		};

		clk: clock-ctrl@1d021000 {
			compatible = "socionext,milbeaut-m10v-ccu";
			#clock-cells = <1>;
			reg = <0x1d021000 0x1000>;
			clocks = <&uclk40xi>;
		};

		timer@1e000050 { /* 32-bit Reload Timers */
			compatible = "socionext,milbeaut-timer";
			reg = <0x1e000050 0x20>;
			interrupts = <0 91 4>;
			clocks = <&clk 4>;
		};

		uart1: serial@1e700010 { /* PE4, PE5 */
			/* Enable this as ttyUSI0 */
			compatible = "socionext,milbeaut-usio-uart";
			reg = <0x1e700010 0x10>;
			interrupts = <0 141 0x4>, <0 149 0x4>;
			interrupt-names = "rx", "tx";
			clocks = <&clk 2>;
		};

	};

	sram@0 {
		compatible = "mmio-sram";
		reg = <0x0 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x0 0x10000>;
		smp-sram@f100 {
			compatible = "socionext,milbeaut-smp-sram";
			reg = <0xf100 0x20>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 *  Copyright (C) 2012 Marvell Technology Group Ltd.
 *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
 */

/dts-v1/;
#include "mmp2.dtsi"

/ {
	model = "Marvell MMP2 Brownstone Development Board";
	compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";

	chosen {
		bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x08000000>;
	};
};

&uart3 {
	status = "okay";
};

&twsi1 {
	status = "okay";
	pmic: max8925@3c {
		compatible = "maxium,max8925";
		reg = <0x3c>;
		interrupts = <1>;
		interrupt-parent = <&intcmux4>;
		interrupt-controller;
		#interrupt-cells = <1>;
		maxim,tsc-irq = <0>;

		regulators {
			SDV1 {
				regulator-min-microvolt = <637500>;
				regulator-max-microvolt = <1425000>;
				regulator-boot-on;
				regulator-always-on;
			};
			SDV2 {
				regulator-min-microvolt = <650000>;
				regulator-max-microvolt = <2225000>;
				regulator-boot-on;
				regulator-always-on;
			};
			SDV3 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO1 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO2 {
				regulator-min-microvolt = <650000>;
				regulator-max-microvolt = <2250000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO3 {
				regulator-min-microvolt = <650000>;
				regulator-max-microvolt = <2250000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO4 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO5 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO6 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO7 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO8 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO9 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO10 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
			};
			LDO11 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO12 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO13 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO14 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO15 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO16 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO17 {
				regulator-min-microvolt = <650000>;
				regulator-max-microvolt = <2250000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO18 {
				regulator-min-microvolt = <650000>;
				regulator-max-microvolt = <2250000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO19 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO20 {
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <3900000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
		backlight {
			maxim,max8925-dual-string = <0>;
		};
		charger {
			batt-detect = <0>;
			topoff-threshold = <1>;
			fast-charge = <7>;
			no-temp-support = <0>;
			no-insert-detect = <0>;
		};
	};
};

&rtc {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * OLPC XO 1.75 Laptop.
 *
 * Copyright (C) 2018,2019,2020 Lubomir Rintel <lkundrak@v3.sk>
 */

/dts-v1/;
#include "mmp2.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/marvell,mmp2-audio.h>

/ {
	model = "OLPC XO-1.75";
	compatible = "olpc,xo-1.75", "mrvl,mmp2";

	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		framebuffer@1fc00000 {
			compatible = "simple-framebuffer";
			reg = <0x1fc00000 (1200 * 900 * 2)>;
			width = <1200>;
			height = <900>;
			stride = <(1200 * 2)>;
			format = "r5g6b5";
			clocks = <&soc_clocks MMP2_CLK_DISP0_LCDC>,
				 <&soc_clocks MMP2_CLK_DISP0>;
		};
	};

	memory@0 {
		available = <0xcf000 0x1ef31000 0x1000 0xbf000>;
		reg = <0x0 0x20000000>;
		device_type = "memory";
	};

	gpio-keys {
		compatible = "gpio-keys";

		lid {
			label = "Lid";
			gpios = <&gpio 129 GPIO_ACTIVE_LOW>;
			linux,input-type = <EV_SW>;
			linux,code = <SW_LID>;
			wakeup-source;
		};

		tablet_mode {
			label = "E-Book Mode";
			gpios = <&gpio 128 GPIO_ACTIVE_LOW>;
			linux,input-type = <EV_SW>;
			linux,code = <SW_TABLET_MODE>;
			wakeup-source;
		};
	};

	i2c {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio 109 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio 108 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		#address-cells = <1>;
		#size-cells = <0>;
		i2c-gpio,timeout-ms = <1000>;
		status = "okay";

		camera@21 {
			compatible = "ovti,ov7670";
			reg = <0x21>;
			reset-gpios = <&gpio 102 GPIO_ACTIVE_LOW>;
			powerdown-gpios = <&gpio 150 GPIO_ACTIVE_LOW>;
			clocks = <&camera0>;
			clock-names = "xclk";

			port {
				ov7670_0: endpoint {
					hsync-active = <1>;
					vsync-active = <1>;
					remote-endpoint = <&camera0_0>;
				};
			};
		};
	};

	battery {
		compatible = "olpc,xo1.5-battery", "olpc,xo1-battery";
	};

	wlan_reg: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "wlan";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio 34 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	wlan_pwrseq: pwrseq0 {
		compatible = "mmc-pwrseq-sd8787";
		powerdown-gpios = <&gpio 57 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>;
	};

	sound-card {
		compatible = "audio-graph-card";
		label = "OLPC XO";
		dais = <&sspa0_dai>;
		routing = "Headphones", "HPOL",
			  "Headphones", "HPOR",
			  "MIC2", "Mic Jack";
		widgets = "Headphone", "Headphones", "Microphone", "Mic Jack";
		hp-det-gpio = <&gpio 97 GPIO_ACTIVE_HIGH>;
		mic-det-gpio = <&gpio 96 GPIO_ACTIVE_HIGH>;
	};

	soc {
		axi@d4200000 {
			ap-sp@d4290000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "olpc,ap-sp";
				interrupts = <40>;
				reg = <0xd4290000 0x1000>;
				data-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>;
				clk-gpios = <&gpio 71 GPIO_ACTIVE_HIGH>;
				status = "okay";
			};
		};
	};
};

&uart3 {
	status = "okay";
};

&uart4 {
	status = "okay";
};

&rtc {
	status = "okay";
};

&usb_phy0 {
	status = "okay";
};

&usb_otg0 {
	status = "okay";
};

&mmc1 {
	clock-frequency = <50000000>;
	no-1-8-v;
	mrvl,clk-delay-cycles = <31>;
	broken-cd;
	status = "okay";
};

&mmc2 {
	clock-frequency = <50000000>;
	no-1-8-v;
	bus-width = <4>;
	non-removable;
	broken-cd;
	wakeup-source;
	keep-power-in-suspend;
	mmc-pwrseq = <&wlan_pwrseq>;
	vmmc-supply = <&wlan_reg>;
	status = "okay";
};

&mmc3 {
	clock-frequency = <50000000>;
	no-1-8-v;
	bus-width = <8>;
	non-removable;
	broken-cd;
	mrvl,clk-delay-cycles = <31>;
	status = "okay";
};

&twsi1 {
	status = "okay";

	audio-codec@1a {
		compatible = "realtek,alc5631";
		reg = <0x1a>;
		status = "okay";

		port {
			rt5631_0: endpoint {
				mclk-fs = <256>;
				clocks = <&audio_clk MMP2_CLK_AUDIO_SYSCLK>;
				remote-endpoint = <&sspa0_0>;
			};
		};
	};
};

&twsi2 {
	status = "okay";

	rtc@68 {
		compatible = "dallas,ds1338";
		reg = <0x68>;
		status = "okay";
	};
};

&twsi6 {
	status = "okay";

	accelerometer@1d {
		compatible = "st,lis331dlh", "st,lis3lv02d";
		reg = <0x1d>;
		status = "okay";
	};
};

&ssp3 {
	#address-cells = <0>;
	spi-slave;
	status = "okay";
	ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>;

	slave {
		compatible = "olpc,xo1.75-ec";
		spi-cpha;
		cmd-gpios = <&gpio 155 GPIO_ACTIVE_HIGH>;
	};
};

&camera0 {
	status = "okay";

	port {
		camera0_0: endpoint {
			remote-endpoint = <&ov7670_0>;
		};
	};
};

&asram {
	status = "okay";
};

&adma0 {
	status = "okay";
};

&audio_clk {
	status = "okay";
};

&sspa0 {
	status = "okay";
	dmas = <&adma0 0>, <&adma0 1>;
	dma-names = "tx", "rx";

	sspa0_dai: port {
		sspa0_0: endpoint {
			remote-endpoint = <&rt5631_0>;
			frame-master;
			bitclock-master;
			dai-format = "i2s";
		};
	};
};

&gpu {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 *  Copyright (C) 2012 Marvell Technology Group Ltd.
 *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
 */

#include <dt-bindings/clock/marvell,mmp2.h>
#include <dt-bindings/power/marvell,mmp2.h>
#include <dt-bindings/clock/marvell,mmp2-audio.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		i2c0 = &twsi1;
		i2c1 = &twsi2;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&intc>;
		ranges;

		L2: l2-cache {
			compatible = "marvell,tauros2-cache";
			marvell,tauros2-cache-features = <0x3>;
		};

		axi@d4200000 {	/* AXI */
			compatible = "mrvl,axi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0xd4200000 0x00200000>;
			ranges;

			gpu: gpu@d420d000 {
				compatible = "vivante,gc";
				reg = <0xd420d000 0x4000>;
				interrupts = <8>;
				status = "disabled";
				clocks = <&soc_clocks MMP2_CLK_GPU_3D>,
					 <&soc_clocks MMP2_CLK_GPU_BUS>;
				clock-names = "core", "bus";
				power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
			};

			intc: interrupt-controller@d4282000 {
				compatible = "mrvl,mmp2-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0xd4282000 0x1000>;
				mrvl,intc-nr-irqs = <64>;
			};

			intcmux4: interrupt-controller@d4282150 {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <4>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x150 0x4>, <0x168 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <2>;
			};

			intcmux5: interrupt-controller@d4282154 {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <5>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x154 0x4>, <0x16c 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <2>;
				mrvl,clr-mfp-irq = <1>;
			};

			intcmux9: interrupt-controller@d4282180 {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <9>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x180 0x4>, <0x17c 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <3>;
			};

			intcmux17: interrupt-controller@d4282158 {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <17>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x158 0x4>, <0x170 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <5>;
			};

			intcmux35: interrupt-controller@d428215c {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <35>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x15c 0x4>, <0x174 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <15>;
			};

			intcmux51: interrupt-controller@d4282160 {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <51>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x160 0x4>, <0x178 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <2>;
			};

			intcmux55: interrupt-controller@d4282188 {
				compatible = "mrvl,mmp2-mux-intc";
				interrupts = <55>;
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x188 0x4>, <0x184 0x4>;
				reg-names = "mux status", "mux mask";
				mrvl,intc-nr-irqs = <2>;
			};

			usb_phy0: usb-phy@d4207000 {
				compatible = "marvell,mmp2-usb-phy";
				reg = <0xd4207000 0x40>;
				#phy-cells = <0>;
				status = "disabled";
			};

			usb_otg0: usb-otg@d4208000 {
				compatible = "marvell,pxau2o-ehci";
				reg = <0xd4208000 0x200>;
				interrupts = <44>;
				clocks = <&soc_clocks MMP2_CLK_USB>;
				clock-names = "USBCLK";
				phys = <&usb_phy0>;
				phy-names = "usb";
				status = "disabled";
			};

			mmc1: mmc@d4280000 {
				compatible = "mrvl,pxav3-mmc";
				reg = <0xd4280000 0x120>;
				clocks = <&soc_clocks MMP2_CLK_SDH0>;
				clock-names = "io";
				interrupts = <39>;
				status = "disabled";
			};

			mmc2: mmc@d4280800 {
				compatible = "mrvl,pxav3-mmc";
				reg = <0xd4280800 0x120>;
				clocks = <&soc_clocks MMP2_CLK_SDH1>;
				clock-names = "io";
				interrupts = <52>;
				status = "disabled";
			};

			mmc3: mmc@d4281000 {
				compatible = "mrvl,pxav3-mmc";
				reg = <0xd4281000 0x120>;
				clocks = <&soc_clocks MMP2_CLK_SDH2>;
				clock-names = "io";
				interrupts = <53>;
				status = "disabled";
			};

			mmc4: mmc@d4281800 {
				compatible = "mrvl,pxav3-mmc";
				reg = <0xd4281800 0x120>;
				clocks = <&soc_clocks MMP2_CLK_SDH3>;
				clock-names = "io";
				interrupts = <54>;
				status = "disabled";
			};

			camera0: camera@d420a000 {
				compatible = "marvell,mmp2-ccic";
				reg = <0xd420a000 0x800>;
				interrupts = <42>;
				clocks = <&soc_clocks MMP2_CLK_CCIC0>;
				clock-names = "axi";
				#clock-cells = <0>;
				clock-output-names = "mclk";
				status = "disabled";
			};

			camera1: camera@d420a800 {
				compatible = "marvell,mmp2-ccic";
				reg = <0xd420a800 0x800>;
				interrupts = <30>;
				clocks = <&soc_clocks MMP2_CLK_CCIC1>;
				clock-names = "axi";
				#clock-cells = <0>;
				clock-output-names = "mclk";
				status = "disabled";
			};

			adma0: dma-controller@d42a0800 {
				compatible = "marvell,adma-1.0";
				reg = <0xd42a0800 0x100>;
				interrupts = <48>;
				#dma-cells = <1>;
				asram = <&asram>;
				iram = <&asram>;
				status = "disabled";
			};

			adma1: dma-controller@d42a0900 {
				compatible = "marvell,adma-1.0";
				reg = <0xd42a0900 0x100>;
				interrupts = <48>;
				#dma-cells = <1>;
				status = "disabled";
			};

			audio_clk: clocks@d42a0c30 {
				compatible = "marvell,mmp2-audio-clock";
				reg = <0xd42a0c30 0x10>;
				clock-names = "audio", "vctcxo", "i2s0", "i2s1";
				clocks = <&soc_clocks MMP2_CLK_AUDIO>,
					 <&soc_clocks MMP2_CLK_VCTCXO>,
					 <&soc_clocks MMP2_CLK_I2S0>,
					 <&soc_clocks MMP2_CLK_I2S1>;
				power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
				#clock-cells = <1>;
				status = "disabled";
			};

			sspa0: audio-controller@d42a0c00 {
				compatible = "marvell,mmp-sspa";
				reg = <0xd42a0c00 0x30>,
				      <0xd42a0c80 0x30>;
				interrupts = <2>;
				clock-names = "audio", "bitclk";
				clocks = <&soc_clocks MMP2_CLK_AUDIO>,
					 <&audio_clk MMP2_CLK_AUDIO_SSPA0>;
				power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
				#sound-dai-cells = <0>;
				status = "disabled";
			};

			sspa1: audio-controller@d42a0d00 {
				compatible = "marvell,mmp-sspa";
				reg = <0xd42a0d00 0x30>,
				      <0xd42a0d80 0x30>;
				interrupts = <3>;
				clock-names = "audio", "bitclk";
				clocks = <&soc_clocks MMP2_CLK_AUDIO>,
					 <&audio_clk MMP2_CLK_AUDIO_SSPA1>;
				power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
				#sound-dai-cells = <0>;
				status = "disabled";
			};
		};

		apb@d4000000 {	/* APB */
			compatible = "mrvl,apb-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0xd4000000 0x00200000>;
			ranges;

			dma-controller@d4000000 {
				compatible = "marvell,pdma-1.0";
				reg = <0xd4000000 0x10000>;
				interrupts = <48>;
				/* For backwards compatibility: */
				#dma-channels = <16>;
				dma-channels = <16>;
				status = "disabled";
			};

			timer0: timer@d4014000 {
				compatible = "mrvl,mmp-timer";
				reg = <0xd4014000 0x100>;
				interrupts = <13>;
				clocks = <&soc_clocks MMP2_CLK_TIMER>;
			};

			uart1: serial@d4030000 {
				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
				reg = <0xd4030000 0x1000>;
				interrupts = <27>;
				clocks = <&soc_clocks MMP2_CLK_UART0>;
				resets = <&soc_clocks MMP2_CLK_UART0>;
				reg-shift = <2>;
				status = "disabled";
			};

			uart2: serial@d4017000 {
				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
				reg = <0xd4017000 0x1000>;
				interrupts = <28>;
				clocks = <&soc_clocks MMP2_CLK_UART1>;
				resets = <&soc_clocks MMP2_CLK_UART1>;
				reg-shift = <2>;
				status = "disabled";
			};

			uart3: serial@d4018000 {
				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
				reg = <0xd4018000 0x1000>;
				interrupts = <24>;
				clocks = <&soc_clocks MMP2_CLK_UART2>;
				resets = <&soc_clocks MMP2_CLK_UART2>;
				reg-shift = <2>;
				status = "disabled";
			};

			uart4: serial@d4016000 {
				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
				reg = <0xd4016000 0x1000>;
				interrupts = <46>;
				clocks = <&soc_clocks MMP2_CLK_UART3>;
				resets = <&soc_clocks MMP2_CLK_UART3>;
				reg-shift = <2>;
				status = "disabled";
			};

			gpio: gpio@d4019000 {
				compatible = "marvell,mmp2-gpio";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xd4019000 0x1000>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupts = <49>;
				interrupt-names = "gpio_mux";
				clocks = <&soc_clocks MMP2_CLK_GPIO>;
				resets = <&soc_clocks MMP2_CLK_GPIO>;
				interrupt-controller;
				#interrupt-cells = <2>;
				ranges;

				gcb0: gpio@d4019000 {
					reg = <0xd4019000 0x4>;
				};

				gcb1: gpio@d4019004 {
					reg = <0xd4019004 0x4>;
				};

				gcb2: gpio@d4019008 {
					reg = <0xd4019008 0x4>;
				};

				gcb3: gpio@d4019100 {
					reg = <0xd4019100 0x4>;
				};

				gcb4: gpio@d4019104 {
					reg = <0xd4019104 0x4>;
				};

				gcb5: gpio@d4019108 {
					reg = <0xd4019108 0x4>;
				};
			};

			twsi1: i2c@d4011000 {
				compatible = "mrvl,mmp-twsi";
				reg = <0xd4011000 0x1000>;
				interrupts = <7>;
				clocks = <&soc_clocks MMP2_CLK_TWSI0>;
				resets = <&soc_clocks MMP2_CLK_TWSI0>;
				#address-cells = <1>;
				#size-cells = <0>;
				mrvl,i2c-fast-mode;
				status = "disabled";
			};

			twsi2: i2c@d4031000 {
				compatible = "mrvl,mmp-twsi";
				reg = <0xd4031000 0x1000>;
				interrupt-parent = <&intcmux17>;
				interrupts = <0>;
				clocks = <&soc_clocks MMP2_CLK_TWSI1>;
				resets = <&soc_clocks MMP2_CLK_TWSI1>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			twsi3: i2c@d4032000 {
				compatible = "mrvl,mmp-twsi";
				reg = <0xd4032000 0x1000>;
				interrupt-parent = <&intcmux17>;
				interrupts = <1>;
				clocks = <&soc_clocks MMP2_CLK_TWSI2>;
				resets = <&soc_clocks MMP2_CLK_TWSI2>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			twsi4: i2c@d4033000 {
				compatible = "mrvl,mmp-twsi";
				reg = <0xd4033000 0x1000>;
				interrupt-parent = <&intcmux17>;
				interrupts = <2>;
				clocks = <&soc_clocks MMP2_CLK_TWSI3>;
				resets = <&soc_clocks MMP2_CLK_TWSI3>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			twsi5: i2c@d4033800 {
				compatible = "mrvl,mmp-twsi";
				reg = <0xd4033800 0x1000>;
				interrupt-parent = <&intcmux17>;
				interrupts = <3>;
				clocks = <&soc_clocks MMP2_CLK_TWSI4>;
				resets = <&soc_clocks MMP2_CLK_TWSI4>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			twsi6: i2c@d4034000 {
				compatible = "mrvl,mmp-twsi";
				reg = <0xd4034000 0x1000>;
				interrupt-parent = <&intcmux17>;
				interrupts = <4>;
				clocks = <&soc_clocks MMP2_CLK_TWSI5>;
				resets = <&soc_clocks MMP2_CLK_TWSI5>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			rtc: rtc@d4010000 {
				compatible = "mrvl,mmp-rtc";
				reg = <0xd4010000 0x1000>;
				interrupts = <1>, <0>;
				interrupt-names = "rtc 1Hz", "rtc alarm";
				interrupt-parent = <&intcmux5>;
				clocks = <&soc_clocks MMP2_CLK_RTC>;
				resets = <&soc_clocks MMP2_CLK_RTC>;
				status = "disabled";
			};

			ssp1: spi@d4035000 {
				compatible = "marvell,mmp2-ssp";
				reg = <0xd4035000 0x1000>;
				clocks = <&soc_clocks MMP2_CLK_SSP0>;
				interrupts = <0>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			ssp2: spi@d4036000 {
				compatible = "marvell,mmp2-ssp";
				reg = <0xd4036000 0x1000>;
				clocks = <&soc_clocks MMP2_CLK_SSP1>;
				interrupts = <1>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			ssp3: spi@d4037000 {
				compatible = "marvell,mmp2-ssp";
				reg = <0xd4037000 0x1000>;
				clocks = <&soc_clocks MMP2_CLK_SSP2>;
				interrupts = <20>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			ssp4: spi@d4039000 {
				compatible = "marvell,mmp2-ssp";
				reg = <0xd4039000 0x1000>;
				clocks = <&soc_clocks MMP2_CLK_SSP3>;
				interrupts = <21>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		asram: sram@e0000000 {
			compatible = "mmio-sram";
			reg = <0xe0000000 0x10000>;
			ranges = <0 0xe0000000 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;
			status = "disabled";
		};

		soc_clocks: clocks {
			compatible = "marvell,mmp2-clock";
			reg = <0xd4050000 0x2000>,
			      <0xd4282800 0x400>,
			      <0xd4015000 0x1000>;
			reg-names = "mpmu", "apmu", "apbc";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Dell Wyse 3020 a.k.a. "Ariel" a.k.a. Tx0D (T00D, T10D)
 *
 * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
 */

/dts-v1/;
#include "mmp3.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "Dell Ariel";
	compatible = "dell,wyse-ariel", "marvell,mmp3";

	aliases {
		serial2 = &uart3;
	};

	chosen {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges;
		bootargs = "earlyprintk=ttyS2,115200 console=ttyS2,115200";
	};

	memory@0 {
		available = <0x7f700000 0x7ff00000 0x00000000 0x7f600000>;
		reg = <0x0 0x80000000>;
		device_type = "memory";
	};

	ec_input_spi: spi {
		compatible = "spi-gpio";
		#address-cells = <1>;
		#size-cells = <0>;

		num-chipselects = <0>;
		sck-gpios = <&gpio 55 GPIO_ACTIVE_HIGH>;
		miso-gpios = <&gpio 57 GPIO_ACTIVE_HIGH>;
		mosi-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>;
	};
};

&uart3 {
	status = "okay";
};

&rtc {
	status = "okay";
};

&usb_otg0 {
	status = "okay";
};

&usb_otg_phy0 {
	status = "okay";
};

&hsic0 {
	status = "okay";

	usb1@1 {
		compatible = "usb424,2640";
		reg = <0x01>;
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		mass-storage@1 {
			compatible = "usb424,4040";
			reg = <0x01>;
			status = "disabled";
		};
	};
};

&hsic_phy0 {
	status = "okay";
	reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
};

&mmc3 {
	status = "okay";
	max-frequency = <50000000>;
	status = "okay";
	bus-width = <8>;
	non-removable;
	cap-mmc-highspeed;
};

&twsi1 {
	status = "okay";

	rtc@68 {
		compatible = "dallas,ds1338";
		reg = <0x68>;
		status = "okay";
	};
};

&twsi3 {
	status = "okay";
};

&twsi4 {
	status = "okay";

	embedded-controller@58 {
		compatible = "dell,wyse-ariel-ec", "ene,kb3930";
		reg = <0x58>;
		system-power-controller;

		off-gpios = <&gpio 126 GPIO_ACTIVE_HIGH>,
			    <&gpio 127 GPIO_ACTIVE_HIGH>;
	};
};

&ssp1 {
	status = "okay";
	cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;

	firmware-flash@0 {
		compatible = "winbond,w25q32", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <104000000>;
		m25p,fast-read;
	};
};

&ec_input_spi {
	status = "okay";
	cs-gpios = <&gpio 56 GPIO_ACTIVE_LOW>;

	power-button@0 {
		reg = <0>;
		interrupt-parent = <&gpio>;
		interrupts = <60 IRQ_TYPE_EDGE_RISING>;
		compatible = "dell,wyse-ariel-ec-input", "ene,kb3930-input";
		spi-max-frequency = <33000000>;
	};
};

&gpu_2d {
	status = "okay";
};

&gpu_3d {
	status = "okay";
};