code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the R-Car M1A (R8A77781) SoC
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * based on r8a7779
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Simon Horman
 */

#include <dt-bindings/clock/r8a7778-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a7778";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <800000000>;
			clocks = <&z_clk>;
		};
	};

	aliases {
		spi0 = &hspi0;
		spi1 = &hspi1;
		spi2 = &hspi2;
	};

	bsc: bus@1c000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x1c000000>;
	};

	ether: ethernet@fde00000 {
		compatible = "renesas,ether-r8a7778",
			     "renesas,rcar-gen1-ether";
		reg = <0xfde00000 0x400>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
		power-domains = <&cpg_clocks>;
		phy-mode = "rmii";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	gic: interrupt-controller@fe438000 {
		compatible = "arm,pl390";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xfe438000 0x1000>,
		      <0xfe430000 0x100>;
	};

	/* irqpin: IRQ0 - IRQ3 */
	irqpin: interrupt-controller@fe78001c {
		compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		status = "disabled"; /* default off */
		reg =	<0xfe78001c 4>,
			<0xfe780010 4>,
			<0xfe780024 4>,
			<0xfe780044 4>,
			<0xfe780064 4>,
			<0xfe780000 4>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		sense-bitfield-width = <2>;
	};

	gpio0: gpio@ffc40000 {
		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
		reg = <0xffc40000 0x2c>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio1: gpio@ffc41000 {
		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
		reg = <0xffc41000 0x2c>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio2: gpio@ffc42000 {
		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
		reg = <0xffc42000 0x2c>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio3: gpio@ffc43000 {
		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
		reg = <0xffc43000 0x2c>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio4: gpio@ffc44000 {
		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
		reg = <0xffc44000 0x2c>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 27>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pfc: pinctrl@fffc0000 {
		compatible = "renesas,pfc-r8a7778";
		reg = <0xfffc0000 0x118>;
	};

	i2c0: i2c@ffc70000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
		reg = <0xffc70000 0x1000>;
		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	i2c1: i2c@ffc71000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
		reg = <0xffc71000 0x1000>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
		power-domains = <&cpg_clocks>;
		i2c-scl-internal-delay-ns = <5>;
		status = "disabled";
	};

	i2c2: i2c@ffc72000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
		reg = <0xffc72000 0x1000>;
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
		power-domains = <&cpg_clocks>;
		i2c-scl-internal-delay-ns = <5>;
		status = "disabled";
	};

	i2c3: i2c@ffc73000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
		reg = <0xffc73000 0x1000>;
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
		power-domains = <&cpg_clocks>;
		i2c-scl-internal-delay-ns = <5>;
		status = "disabled";
	};

	tmu0: timer@ffd80000 {
		compatible = "renesas,tmu-r8a7778", "renesas,tmu";
		reg = <0xffd80000 0x30>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu1: timer@ffd81000 {
		compatible = "renesas,tmu-r8a7778", "renesas,tmu";
		reg = <0xffd81000 0x30>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu2: timer@ffd82000 {
		compatible = "renesas,tmu-r8a7778", "renesas,tmu";
		reg = <0xffd82000 0x30>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
		clock-names = "fck";
		power-domains = <&cpg_clocks>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	rcar_sound: sound@ffd90000 {
		/*
		 * #sound-dai-cells is required
		 *
		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
		 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
		 */
		compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
		reg =	<0xffd90000 0x1000>,	/* SRU */
			<0xffd91000 0x240>,	/* SSI */
			<0xfffe0000 0x24>;	/* ADG */
		clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
			<&mstp3_clks R8A7778_CLK_SSI7>,
			<&mstp3_clks R8A7778_CLK_SSI6>,
			<&mstp3_clks R8A7778_CLK_SSI5>,
			<&mstp3_clks R8A7778_CLK_SSI4>,
			<&mstp0_clks R8A7778_CLK_SSI3>,
			<&mstp0_clks R8A7778_CLK_SSI2>,
			<&mstp0_clks R8A7778_CLK_SSI1>,
			<&mstp0_clks R8A7778_CLK_SSI0>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC8>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC7>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC6>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC5>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC4>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC3>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC2>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC1>,
			<&mstp5_clks R8A7778_CLK_SRU_SRC0>,
			<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
			<&cpg_clocks R8A7778_CLK_S1>;
		clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
			"ssi.3", "ssi.2", "ssi.1", "ssi.0",
			"src.8", "src.7", "src.6", "src.5", "src.4",
			"src.3", "src.2", "src.1", "src.0",
			"clk_a", "clk_b", "clk_c", "clk_i";

		status = "disabled";

		rcar_sound,src {
			src3: src-3 { };
			src4: src-4 { };
			src5: src-5 { };
			src6: src-6 { };
			src7: src-7 { };
			src8: src-8 { };
			src9: src-9 { };
		};

		rcar_sound,ssi {
			ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
			ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
			ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
			ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
			ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
			ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
			ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
		};
	};

	scif0: serial@ffe40000 {
		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe40000 0x100>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif1: serial@ffe41000 {
		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe41000 0x100>;
		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif2: serial@ffe42000 {
		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe42000 0x100>;
		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif3: serial@ffe43000 {
		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe43000 0x100>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif4: serial@ffe44000 {
		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe44000 0x100>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	scif5: serial@ffe45000 {
		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe45000 0x100>;
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
			 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	hscif0: serial@ffe48000 {
		compatible = "renesas,hscif-r8a7778",
			     "renesas,rcar-gen1-hscif", "renesas,hscif";
		reg = <0xffe48000 96>;
		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
			 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	hscif1: serial@ffe49000 {
		compatible = "renesas,hscif-r8a7778",
			     "renesas,rcar-gen1-hscif", "renesas,hscif";
		reg = <0xffe49000 96>;
		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
			 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	mmcif: mmc@ffe4e000 {
		compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
		reg = <0xffe4e000 0x100>;
		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7778_CLK_MMC>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	sdhi0: mmc@ffe4c000 {
		compatible = "renesas,sdhi-r8a7778",
			     "renesas,rcar-gen1-sdhi";
		reg = <0xffe4c000 0x100>;
		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	sdhi1: mmc@ffe4d000 {
		compatible = "renesas,sdhi-r8a7778",
			     "renesas,rcar-gen1-sdhi";
		reg = <0xffe4d000 0x100>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	sdhi2: mmc@ffe4f000 {
		compatible = "renesas,sdhi-r8a7778",
			     "renesas,rcar-gen1-sdhi";
		reg = <0xffe4f000 0x100>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
		power-domains = <&cpg_clocks>;
		status = "disabled";
	};

	hspi0: spi@fffc7000 {
		compatible = "renesas,hspi-r8a7778", "renesas,hspi";
		reg = <0xfffc7000 0x18>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
		power-domains = <&cpg_clocks>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	hspi1: spi@fffc8000 {
		compatible = "renesas,hspi-r8a7778", "renesas,hspi";
		reg = <0xfffc8000 0x18>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
		power-domains = <&cpg_clocks>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	hspi2: spi@fffc6000 {
		compatible = "renesas,hspi-r8a7778", "renesas,hspi";
		reg = <0xfffc6000 0x18>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
		power-domains = <&cpg_clocks>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* External input clock */
		extal_clk: extal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		/* External SCIF clock */
		scif_clk: scif {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overridden by the board. */
			clock-frequency = <0>;
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@ffc80000 {
			compatible = "renesas,r8a7778-cpg-clocks";
			reg = <0xffc80000 0x80>;
			#clock-cells = <1>;
			clocks = <&extal_clk>;
			clock-output-names = "plla", "pllb", "b",
					     "out", "p", "s", "s1";
			#power-domain-cells = <0>;
		};

		/* Audio clocks; frequencies are set by boards if applicable. */
		audio_clk_a: audio_clk_a {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};
		audio_clk_b: audio_clk_b {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};
		audio_clk_c: audio_clk_c {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		/* Fixed ratio clocks */
		g_clk: g {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <12>;
			clock-mult = <1>;
		};
		i_clk: i {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <1>;
			clock-mult = <1>;
		};
		s3_clk: s3 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <4>;
			clock-mult = <1>;
		};
		s4_clk: s4 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
		};
		z_clk: z {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
			#clock-cells = <0>;
			clock-div = <1>;
			clock-mult = <1>;
		};

		/* Gate clocks */
		mstp0_clks: mstp0_clks@ffc80030 {
			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xffc80030 4>;
			clocks = <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_S>,
				 <&cpg_clocks R8A7778_CLK_S>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_S>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
				R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
				R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
				R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
				R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
				R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1
				R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
				R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
				R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
				R8A7778_CLK_SSI3 R8A7778_CLK_SRU
				R8A7778_CLK_HSPI
			>;
			clock-output-names =
				"i2c0", "i2c1", "i2c2", "i2c3", "scif0",
				"scif1", "scif2", "scif3", "scif4", "scif5",
				"hscif0", "hscif1",
				"tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
				"ssi2", "ssi3", "sru", "hspi";
		};
		mstp1_clks: mstp1_clks@ffc80034 {
			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xffc80034 4>, <0xffc80044 4>;
			clocks = <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_S>,
				 <&cpg_clocks R8A7778_CLK_S>,
				 <&cpg_clocks R8A7778_CLK_P>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7778_CLK_ETHER R8A7778_CLK_VIN0
				R8A7778_CLK_VIN1 R8A7778_CLK_USB
			>;
			clock-output-names =
				"ether", "vin0", "vin1", "usb";
		};
		mstp3_clks: mstp3_clks@ffc8003c {
			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xffc8003c 4>;
			clocks = <&s4_clk>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7778_CLK_MMC R8A7778_CLK_SDHI0
				R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
				R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
				R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
				R8A7778_CLK_SSI8
			>;
			clock-output-names =
				"mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
				"ssi5", "ssi6", "ssi7", "ssi8";
		};
		mstp5_clks: mstp5_clks@ffc80054 {
			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xffc80054 4>;
			clocks = <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>,
				 <&cpg_clocks R8A7778_CLK_P>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
				R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
				R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
				R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
				R8A7778_CLK_SRU_SRC8
			>;
			clock-output-names =
				"sru-src0", "sru-src1", "sru-src2",
				"sru-src3", "sru-src4", "sru-src5",
				"sru-src6", "sru-src7", "sru-src8";
		};
	};

	rst: reset-controller@ffcc0000 {
		compatible = "renesas,r8a7778-reset-wdt";
		reg = <0xffcc0000 0x40>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the R-Car H1 (R8A77790) Marzen board
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Simon Horman
 */

/dts-v1/;
#include "r8a7779.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "marzen";
	compatible = "renesas,marzen", "renesas,r8a7779";

	aliases {
		serial0 = &scif2;
		serial1 = &scif4;
	};

	chosen {
		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x40000000>;
	};

	fixedregulator3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
		compatible = "regulator-gpio";

		regulator-name = "SDHI0 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;

		gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
		gpios-states = <1>;
		states = <3300000 1>, <1800000 0>;
	};

	ethernet@18000000 {
		compatible = "smsc,lan89218", "smsc,lan9115";
		reg = <0x18000000 0x100>;
		pinctrl-0 = <&ethernet_pins>;
		pinctrl-names = "default";

		phy-mode = "mii";
		interrupt-parent = <&irqpin0>;
		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
		smsc,irq-push-pull;
		reg-io-width = <4>;
		vddvario-supply = <&fixedregulator3v3>;
		vdd33a-supply = <&fixedregulator3v3>;
	};

	leds {
		compatible = "gpio-leds";
		led2 {
			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
		};
		led3 {
			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
		};
		led4 {
			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
		};
	};

	vga-encoder {
		compatible = "adi,adv7123";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				vga_enc_in: endpoint {
					remote-endpoint = <&du_out_rgb0>;
				};
			};
			port@1 {
				reg = <1>;
				vga_enc_out: endpoint {
					remote-endpoint = <&vga_in>;
				};
			};
		};
	};

	vga {
		compatible = "vga-connector";

		port {
			vga_in: endpoint {
				remote-endpoint = <&vga_enc_out>;
			};
		};
	};

	lvds-encoder {
		compatible = "thine,thc63lvdm83d";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				lvds_enc_in: endpoint {
					remote-endpoint = <&du_out_rgb1>;
				};
			};
			port@1 {
				reg = <1>;
				lvds_connector: endpoint {
				};
			};
		};
	};

	x3_clk: x3-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <65000000>;
	};
};

&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>;
	clock-names = "du.0", "dclkin.0";

	ports {
		port@0 {
			endpoint {
				remote-endpoint = <&vga_enc_in>;
			};
		};
		port@1 {
			endpoint {
				remote-endpoint = <&lvds_enc_in>;
			};
		};
	};
};

&irqpin0 {
	status = "okay";
};

&extal_clk {
	clock-frequency = <31250000>;
};

&tmu0 {
	status = "okay";
};

&pfc {
	pinctrl-0 = <&scif_clk_pins>;
	pinctrl-names = "default";

	du_pins: du {
		du0 {
			groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in";
			function = "du0";
		};
		du1 {
			groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
			function = "du1";
		};
	};

	scif_clk_pins: scif_clk {
		groups = "scif_clk_b";
		function = "scif_clk";
	};

	ethernet_pins: ethernet {
		intc {
			groups = "intc_irq1_b";
			function = "intc";
		};
		lbsc {
			groups = "lbsc_ex_cs0";
			function = "lbsc";
		};
	};

	scif2_pins: scif2 {
		groups = "scif2_data_c";
		function = "scif2";
	};

	scif4_pins: scif4 {
		groups = "scif4_data";
		function = "scif4";
	};

	sdhi0_pins: sd0 {
		groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
		function = "sdhi0";
	};

	hspi0_pins: hspi0 {
		groups = "hspi0";
		function = "hspi0";
	};
};

&sata {
	status = "okay";
};

&scif2 {
	pinctrl-0 = <&scif2_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&scif4 {
	pinctrl-0 = <&scif4_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&scif_clk {
	clock-frequency = <14745600>;
};

&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&fixedregulator3v3>;
	vqmmc-supply = <&vccq_sdhi0>;
	bus-width = <4>;
	status = "okay";
};

&hspi0 {
	pinctrl-0 = <&hspi0_pins>;
	pinctrl-names = "default";
	status = "okay";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the R-Car H1 (R8A77790) SoC
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Simon Horman
 */

#include <dt-bindings/clock/r8a7779-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/r8a7779-sysc.h>

/ {
	compatible = "renesas,r8a7779";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <1000000000>;
			clocks = <&cpg_clocks R8A7779_CLK_Z>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clock-frequency = <1000000000>;
			clocks = <&cpg_clocks R8A7779_CLK_Z>;
			power-domains = <&sysc R8A7779_PD_ARM1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			clock-frequency = <1000000000>;
			clocks = <&cpg_clocks R8A7779_CLK_Z>;
			power-domains = <&sysc R8A7779_PD_ARM2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			clock-frequency = <1000000000>;
			clocks = <&cpg_clocks R8A7779_CLK_Z>;
			power-domains = <&sysc R8A7779_PD_ARM3>;
		};
	};

	aliases {
		spi0 = &hspi0;
		spi1 = &hspi1;
		spi2 = &hspi2;
	};

	gic: interrupt-controller@f0001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xf0001000 0x1000>,
		      <0xf0000100 0x100>;
	};

	timer@f0000200 {
		compatible = "arm,cortex-a9-global-timer";
		reg = <0xf0000200 0x100>;
		interrupts = <GIC_PPI 11
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&cpg_clocks R8A7779_CLK_ZS>;
	};

	timer@f0000600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0xf0000600 0x20>;
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&cpg_clocks R8A7779_CLK_ZS>;
	};

	gpio0: gpio@ffc40000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc40000 0x2c>;
		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio1: gpio@ffc41000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc41000 0x2c>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio2: gpio@ffc42000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc42000 0x2c>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio3: gpio@ffc43000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc43000 0x2c>;
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio4: gpio@ffc44000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc44000 0x2c>;
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio5: gpio@ffc45000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc45000 0x2c>;
		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 160 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio6: gpio@ffc46000 {
		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
		reg = <0xffc46000 0x2c>;
		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 192 9>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	irqpin0: interrupt-controller@fe78001c {
		compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		status = "disabled";
		interrupt-controller;
		reg = <0xfe78001c 4>,
			<0xfe780010 4>,
			<0xfe780024 4>,
			<0xfe780044 4>,
			<0xfe780064 4>,
			<0xfe780000 4>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		sense-bitfield-width = <2>;
	};

	i2c0: i2c@ffc70000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
		reg = <0xffc70000 0x1000>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	i2c1: i2c@ffc71000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
		reg = <0xffc71000 0x1000>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		i2c-scl-internal-delay-ns = <5>;
		status = "disabled";
	};

	i2c2: i2c@ffc72000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
		reg = <0xffc72000 0x1000>;
		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		i2c-scl-internal-delay-ns = <5>;
		status = "disabled";
	};

	i2c3: i2c@ffc73000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
		reg = <0xffc73000 0x1000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		i2c-scl-internal-delay-ns = <5>;
		status = "disabled";
	};

	scif0: serial@ffe40000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe40000 0x100>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif1: serial@ffe41000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe41000 0x100>;
		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif2: serial@ffe42000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe42000 0x100>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif3: serial@ffe43000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe43000 0x100>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif4: serial@ffe44000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe44000 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif5: serial@ffe45000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe45000 0x100>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	hscif0: serial@ffe48000 {
		compatible = "renesas,hscif-r8a7779",
			     "renesas,rcar-gen1-hscif", "renesas,hscif";
		reg = <0xffe48000 96>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>,
			 <&cpg_clocks R8A7779_CLK_S>,
			 <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	hscif1: serial@ffe49000 {
		compatible = "renesas,hscif-r8a7779",
			     "renesas,rcar-gen1-hscif", "renesas,hscif";
		reg = <0xffe49000 96>;
		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>,
			 <&cpg_clocks R8A7779_CLK_S>,
			 <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	pfc: pinctrl@fffc0000 {
		compatible = "renesas,pfc-r8a7779";
		reg = <0xfffc0000 0x23c>;
	};

	thermal@ffc48000 {
		compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
		reg = <0xffc48000 0x38>;
	};

	tmu0: timer@ffd80000 {
		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
		reg = <0xffd80000 0x30>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
		clock-names = "fck";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu1: timer@ffd81000 {
		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
		reg = <0xffd81000 0x30>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
		clock-names = "fck";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu2: timer@ffd82000 {
		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
		reg = <0xffd82000 0x30>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
		clock-names = "fck";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	sata: sata@fc600000 {
		compatible = "renesas,sata-r8a7779";
		reg = <0xfc600000 0x200000>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	sdhi0: mmc@ffe4c000 {
		compatible = "renesas,sdhi-r8a7779",
			     "renesas,rcar-gen1-sdhi";
		reg = <0xffe4c000 0x100>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	sdhi1: mmc@ffe4d000 {
		compatible = "renesas,sdhi-r8a7779",
			     "renesas,rcar-gen1-sdhi";
		reg = <0xffe4d000 0x100>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	sdhi2: mmc@ffe4e000 {
		compatible = "renesas,sdhi-r8a7779",
			     "renesas,rcar-gen1-sdhi";
		reg = <0xffe4e000 0x100>;
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	sdhi3: mmc@ffe4f000 {
		compatible = "renesas,sdhi-r8a7779",
			     "renesas,rcar-gen1-sdhi";
		reg = <0xffe4f000 0x100>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	hspi0: spi@fffc7000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc7000 0x18>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	hspi1: spi@fffc8000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc8000 0x18>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	hspi2: spi@fffc6000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc6000 0x18>;
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	du: display@fff80000 {
		compatible = "renesas,du-r8a7779";
		reg = <0xfff80000 0x40000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7779_CLK_DU>;
		clock-names = "du.0";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				du_out_rgb0: endpoint {
				};
			};
			port@1 {
				reg = <1>;
				du_out_rgb1: endpoint {
				};
			};
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* External root clock */
		extal_clk: extal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overriden by the board. */
			clock-frequency = <0>;
		};

		/* External SCIF clock */
		scif_clk: scif {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overridden by the board. */
			clock-frequency = <0>;
		};

		/* Special CPG clocks */
		cpg_clocks: clocks@ffc80000 {
			compatible = "renesas,r8a7779-cpg-clocks";
			reg = <0xffc80000 0x30>;
			clocks = <&extal_clk>;
			#clock-cells = <1>;
			clock-output-names = "plla", "z", "zs", "s",
					     "s1", "p", "b", "out";
			#power-domain-cells = <0>;
		};

		/* Fixed factor clocks */
		i_clk: i {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};
		s3_clk: s3 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
		};
		s4_clk: s4 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <16>;
			clock-mult = <1>;
		};
		g_clk: g {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <24>;
			clock-mult = <1>;
		};

		/* Gate clocks */
		mstp0_clks: clocks@ffc80030 {
			compatible = "renesas,r8a7779-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0xffc80030 4>;
			clocks = <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7779_CLK_HSPI R8A7779_CLK_TMU2
				R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
				R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
			>;
			clock-output-names =
				"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
				"hscif0", "scif5", "scif4", "scif3", "scif2",
				"scif1", "scif0", "i2c3", "i2c2", "i2c1",
				"i2c0";
		};
		mstp1_clks: clocks@ffc80034 {
			compatible = "renesas,r8a7779-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0xffc80034 4>, <0xffc80044 4>;
			clocks = <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7779_CLK_USB01 R8A7779_CLK_USB2
				R8A7779_CLK_DU R8A7779_CLK_VIN2
				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
				R8A7779_CLK_ETHER R8A7779_CLK_SATA
				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
			>;
			clock-output-names =
				"usb01", "usb2",
				"du", "vin2",
				"vin1", "vin0",
				"ether", "sata",
				"pcie", "vin3";
		};
		mstp3_clks: clocks@ffc8003c {
			compatible = "renesas,r8a7779-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0xffc8003c 4>;
			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
				 <&s4_clk>, <&s4_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
			>;
			clock-output-names =
				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
				"mmc1", "mmc0";
		};
	};

	prr: chipid@ff000044 {
		compatible = "renesas,prr";
		reg = <0xff000044 4>;
	};

	rst: reset-controller@ffcc0000 {
		compatible = "renesas,r8a7779-reset-wdt";
		reg = <0xffcc0000 0x48>;
	};

	sysc: system-controller@ffd85000 {
		compatible = "renesas,r8a7779-sysc";
		reg = <0xffd85000 0x0200>;
		#power-domain-cells = <1>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the Lager board
 *
 * Copyright (C) 2013-2014 Renesas Solutions Corp.
 * Copyright (C) 2014 Cogent Embedded, Inc.
 * Copyright (C) 2015-2016 Renesas Electronics Corporation
 */

/*
 * SSI-AK4643
 *
 * SW1: 1: AK4643
 *      2: CN22
 *      3: ADV7511
 *
 * This command is required when Playback/Capture
 *
 *	amixer set "LINEOUT Mixer DACL" on
 *	amixer set "DVC Out" 100%
 *	amixer set "DVC In" 100%
 *
 * You can use Mute
 *
 *	amixer set "DVC Out Mute" on
 *	amixer set "DVC In Mute" on
 *
 * You can use Volume Ramp
 *
 *	amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
 *	amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
 *	amixer set "DVC Out Ramp" on
 *	aplay xxx.wav &
 *	amixer set "DVC Out"  80%  // Volume Down
 *	amixer set "DVC Out" 100%  // Volume Up
 */

/dts-v1/;
#include "r8a7790.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "Lager";
	compatible = "renesas,lager", "renesas,r8a7790";

	aliases {
		serial0 = &scif0;
		serial1 = &scifa1;
		i2c8 = &gpioi2c1;
		i2c9 = &gpioi2c2;
		i2c10 = &i2cexio0;
		i2c11 = &i2cexio1;
		i2c12 = &i2chdmi;
		i2c13 = &i2cpwr;
		mmc0 = &mmcif1;
		mmc1 = &sdhi0;
		mmc2 = &sdhi2;
	};

	chosen {
		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x40000000>;
	};

	memory@140000000 {
		device_type = "memory";
		reg = <1 0x40000000 0 0xc0000000>;
	};

	lbsc {
		#address-cells = <1>;
		#size-cells = <1>;
	};

	keyboard {
		compatible = "gpio-keys";

		pinctrl-0 = <&keyboard_pins>;
		pinctrl-names = "default";

		one {
			linux,code = <KEY_1>;
			label = "SW2-1";
			wakeup-source;
			debounce-interval = <20>;
			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
		};
		two {
			linux,code = <KEY_2>;
			label = "SW2-2";
			wakeup-source;
			debounce-interval = <20>;
			gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
		};
		three {
			linux,code = <KEY_3>;
			label = "SW2-3";
			wakeup-source;
			debounce-interval = <20>;
			gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
		};
		four {
			linux,code = <KEY_4>;
			label = "SW2-4";
			wakeup-source;
			debounce-interval = <20>;
			gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
		};
	};

	leds {
		compatible = "gpio-leds";
		led6 {
			gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
		};
		led7 {
			gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
		};
		led8 {
			gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
		};
	};

	fixedregulator3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
		compatible = "regulator-fixed";

		regulator-name = "SDHI0 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
		compatible = "regulator-gpio";

		regulator-name = "SDHI0 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;

		gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
		gpios-states = <1>;
		states = <3300000 1>, <1800000 0>;
	};

	vcc_sdhi2: regulator-vcc-sdhi2 {
		compatible = "regulator-fixed";

		regulator-name = "SDHI2 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vccq_sdhi2: regulator-vccq-sdhi2 {
		compatible = "regulator-gpio";

		regulator-name = "SDHI2 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;

		gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
		gpios-states = <1>;
		states = <3300000 1>, <1800000 0>;
	};

	audio_clock: audio_clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <11289600>;
	};

	rsnd_ak4643: sound {
		compatible = "simple-audio-card";

		simple-audio-card,format = "left_j";
		simple-audio-card,bitclock-master = <&sndcodec>;
		simple-audio-card,frame-master = <&sndcodec>;

		sndcpu: simple-audio-card,cpu {
			sound-dai = <&rcar_sound>;
		};

		sndcodec: simple-audio-card,codec {
			sound-dai = <&ak4643>;
			clocks = <&audio_clock>;
		};
	};

	vga-encoder {
		compatible = "adi,adv7123";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				adv7123_in: endpoint {
					remote-endpoint = <&du_out_rgb>;
				};
			};
			port@1 {
				reg = <1>;
				adv7123_out: endpoint {
					remote-endpoint = <&vga_in>;
				};
			};
		};
	};

	vga {
		compatible = "vga-connector";

		port {
			vga_in: endpoint {
				remote-endpoint = <&adv7123_out>;
			};
		};
	};

	hdmi-in {
		compatible = "hdmi-connector";
		type = "a";

		port {
			hdmi_con_in: endpoint {
				remote-endpoint = <&adv7612_in>;
			};
		};
	};

	cec_clock: cec-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <12000000>;
	};

	hdmi-out {
		compatible = "hdmi-connector";
		type = "a";

		port {
			hdmi_con_out: endpoint {
				remote-endpoint = <&adv7511_out>;
			};
		};
	};

	x2_clk: x2-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <148500000>;
	};

	x13_clk: x13-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <148500000>;
	};

	gpioi2c1: i2c-8 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "i2c-gpio";
		status = "disabled";
		scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		i2c-gpio,delay-us = <5>;
	};

	gpioi2c2: i2c-9 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "i2c-gpio";
		status = "disabled";
		scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		i2c-gpio,delay-us = <5>;
	};

	/*
	 * IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
	 * We use the I2C demuxer, so the desired IP core can be selected at runtime
	 * depending on the use case (e.g. DMA with IIC0 or slave support with I2C0).
	 * Note: For testing the I2C slave feature, it is convenient to connect this
	 * bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
	 * instantiate the slave device at runtime according to the documentation.
	 * You can then communicate with the slave via IIC3.
	 *
	 * IIC0/I2C0 does not appear to support fallback to GPIO.
	 */
	i2cexio0: i2c-10 {
		compatible = "i2c-demux-pinctrl";
		i2c-parent = <&iic0>, <&i2c0>;
		i2c-bus-name = "i2c-exio0";
		#address-cells = <1>;
		#size-cells = <0>;
	};

	/*
	 * IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
	 * This is similar to the arangement described for i2cexio0 (above)
	 * with a fallback to GPIO also provided.
	 */
	i2cexio1: i2c-11 {
		compatible = "i2c-demux-pinctrl";
		i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
		i2c-bus-name = "i2c-exio1";
		#address-cells = <1>;
		#size-cells = <0>;
	};

	/*
	 * IIC2 and I2C2 may be switched using pinmux.
	 * A fallback to GPIO is also provided.
	 */
	i2chdmi: i2c-12 {
		compatible = "i2c-demux-pinctrl";
		i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
		i2c-bus-name = "i2c-hdmi";
		#address-cells = <1>;
		#size-cells = <0>;

		ak4643: codec@12 {
			compatible = "asahi-kasei,ak4643";
			#sound-dai-cells = <0>;
			reg = <0x12>;
		};

		composite-in@20 {
			compatible = "adi,adv7180";
			reg = <0x20>;

			port {
				adv7180: endpoint {
					bus-width = <8>;
					remote-endpoint = <&vin1ep0>;
				};
			};
		};

		hdmi@39 {
			compatible = "adi,adv7511w";
			reg = <0x39>;
			interrupt-parent = <&gpio1>;
			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&cec_clock>;
			clock-names = "cec";

			adi,input-depth = <8>;
			adi,input-colorspace = "rgb";
			adi,input-clock = "1x";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					adv7511_in: endpoint {
						remote-endpoint = <&lvds0_out>;
					};
				};

				port@1 {
					reg = <1>;
					adv7511_out: endpoint {
						remote-endpoint = <&hdmi_con_out>;
					};
				};
			};
		};

		hdmi-in@4c {
			compatible = "adi,adv7612";
			reg = <0x4c>;
			interrupt-parent = <&gpio1>;
			interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
			default-input = <0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					adv7612_in: endpoint {
						remote-endpoint = <&hdmi_con_in>;
					};
				};

				port@2 {
					reg = <2>;
					adv7612_out: endpoint {
						remote-endpoint = <&vin0ep2>;
					};
				};
			};
		};
	};

	/*
	 * IIC3 and I2C3 may be switched using pinmux.
	 * IIC3/I2C3 does not appear to support fallback to GPIO.
	 */
	i2cpwr: i2c-13 {
		compatible = "i2c-demux-pinctrl";
		pinctrl-names = "default";
		pinctrl-0 = <&pmic_irq_pins>;
		i2c-parent = <&iic3>, <&i2c3>;
		i2c-bus-name = "i2c-pwr";
		#address-cells = <1>;
		#size-cells = <0>;

		pmic@58 {
			compatible = "dlg,da9063";
			reg = <0x58>;
			interrupt-parent = <&irqc0>;
			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
			interrupt-controller;

			rtc {
				compatible = "dlg,da9063-rtc";
			};

			watchdog {
				compatible = "dlg,da9063-watchdog";
			};
		};

		vdd_dvfs: regulator@68 {
			compatible = "dlg,da9210";
			reg = <0x68>;
			interrupt-parent = <&irqc0>;
			interrupts = <2 IRQ_TYPE_LEVEL_LOW>;

			regulator-min-microvolt = <1000000>;
			regulator-max-microvolt = <1000000>;
			regulator-boot-on;
			regulator-always-on;
		};
	};
};

&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
		 <&x13_clk>, <&x2_clk>;
	clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1";

	ports {
		port@0 {
			endpoint {
				remote-endpoint = <&adv7123_in>;
			};
		};
	};
};

&lvds0 {
	status = "okay";

	ports {
		port@1 {
			endpoint {
				remote-endpoint = <&adv7511_in>;
			};
		};
	};
};

&lvds1 {
	ports {
		port@1 {
			lvds_connector: endpoint {
			};
		};
	};
};

&extal_clk {
	clock-frequency = <20000000>;
};

&pfc {
	pinctrl-0 = <&scif_clk_pins>;
	pinctrl-names = "default";

	du_pins: du {
		groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
		function = "du";
	};

	scif0_pins: scif0 {
		groups = "scif0_data";
		function = "scif0";
	};

	scif_clk_pins: scif_clk {
		groups = "scif_clk";
		function = "scif_clk";
	};

	ether_pins: ether {
		groups = "eth_link", "eth_mdio", "eth_rmii";
		function = "eth";
	};

	phy1_pins: phy1 {
		groups = "intc_irq0";
		function = "intc";
	};

	scifa1_pins: scifa1 {
		groups = "scifa1_data";
		function = "scifa1";
	};

	sdhi0_pins: sd0 {
		groups = "sdhi0_data4", "sdhi0_ctrl";
		function = "sdhi0";
		power-source = <3300>;
	};

	sdhi0_pins_uhs: sd0_uhs {
		groups = "sdhi0_data4", "sdhi0_ctrl";
		function = "sdhi0";
		power-source = <1800>;
	};

	sdhi2_pins: sd2 {
		groups = "sdhi2_data4", "sdhi2_ctrl";
		function = "sdhi2";
		power-source = <3300>;
	};

	sdhi2_pins_uhs: sd2_uhs {
		groups = "sdhi2_data4", "sdhi2_ctrl";
		function = "sdhi2";
		power-source = <1800>;
	};

	mmc1_pins: mmc1 {
		groups = "mmc1_data8", "mmc1_ctrl";
		function = "mmc1";
	};

	qspi_pins: qspi {
		groups = "qspi_ctrl", "qspi_data4";
		function = "qspi";
	};

	msiof1_pins: msiof1 {
		groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
				 "msiof1_tx";
		function = "msiof1";
	};

	i2c0_pins: i2c0 {
		groups = "i2c0";
		function = "i2c0";
	};

	iic0_pins: iic0 {
		groups = "iic0";
		function = "iic0";
	};

	i2c1_pins: i2c1 {
		groups = "i2c1";
		function = "i2c1";
	};

	iic1_pins: iic1 {
		groups = "iic1";
		function = "iic1";
	};

	i2c2_pins: i2c2 {
		groups = "i2c2";
		function = "i2c2";
	};

	iic2_pins: iic2 {
		groups = "iic2";
		function = "iic2";
	};

	i2c3_pins: i2c3 {
		groups = "i2c3";
		function = "i2c3";
	};

	iic3_pins: iic3 {
		groups = "iic3";
		function = "iic3";
	};

	pmic_irq_pins: pmicirq {
		groups = "intc_irq2";
		function = "intc";
	};

	hsusb_pins: hsusb {
		groups = "usb0_ovc_vbus";
		function = "usb0";
	};

	usb0_pins: usb0 {
		groups = "usb0";
		function = "usb0";
	};

	usb1_pins: usb1 {
		groups = "usb1";
		function = "usb1";
	};

	usb2_pins: usb2 {
		groups = "usb2";
		function = "usb2";
	};

	vin0_pins: vin0 {
		groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
		function = "vin0";
	};

	vin1_pins: vin1 {
		groups = "vin1_data8", "vin1_clk";
		function = "vin1";
	};

	sound_pins: sound {
		groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
		function = "ssi";
	};

	sound_clk_pins: sound_clk {
		groups = "audio_clk_a";
		function = "audio_clk";
	};

	keyboard_pins: keyboard {
		pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28";
		bias-pull-up;
	};
};

&ether {
	pinctrl-0 = <&ether_pins>, <&phy1_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy1>;
	renesas,ether-link-active-low;
	status = "okay";

	phy1: ethernet-phy@1 {
		compatible = "ethernet-phy-id0022.1537",
			     "ethernet-phy-ieee802.3-c22";
		reg = <1>;
		interrupt-parent = <&irqc0>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
		micrel,led-mode = <1>;
		reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
	};
};

&cmt0 {
	status = "okay";
};

&mmcif1 {
	pinctrl-0 = <&mmc1_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&fixedregulator3v3>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&sata1 {
	status = "okay";
};

&qspi {
	pinctrl-0 = <&qspi_pins>;
	pinctrl-names = "default";

	status = "okay";

	flash: flash@0 {
		compatible = "spansion,s25fl512s", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <30000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		spi-cpha;
		spi-cpol;
		m25p,fast-read;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "loader";
				reg = <0x00000000 0x00040000>;
				read-only;
			};
			partition@40000 {
				label = "user";
				reg = <0x00040000 0x00400000>;
				read-only;
			};
			partition@440000 {
				label = "flash";
				reg = <0x00440000 0x03bc0000>;
			};
		};
	};
};

&scif0 {
	pinctrl-0 = <&scif0_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&scifa1 {
	pinctrl-0 = <&scifa1_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&scif_clk {
	clock-frequency = <14745600>;
};

&msiof1 {
	pinctrl-0 = <&msiof1_pins>;
	pinctrl-names = "default";

	status = "okay";

	pmic: pmic@0 {
		compatible = "renesas,r2a11302ft";
		reg = <0>;
		spi-max-frequency = <6000000>;
		spi-cpol;
		spi-cpha;
	};
};

&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-1 = <&sdhi0_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi0>;
	vqmmc-supply = <&vccq_sdhi0>;
	cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
};

&sdhi2 {
	pinctrl-0 = <&sdhi2_pins>;
	pinctrl-1 = <&sdhi2_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi2>;
	vqmmc-supply = <&vccq_sdhi2>;
	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
	sd-uhs-sdr50;
	status = "okay";
};

&cpu0 {
	cpu0-supply = <&vdd_dvfs>;
};

&i2c0	{
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "i2c-exio0";
};

&iic0	{
	pinctrl-0 = <&iic0_pins>;
	pinctrl-names = "i2c-exio0";
};

&i2c1	{
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "i2c-exio1";
};

&iic1	{
	pinctrl-0 = <&iic1_pins>;
	pinctrl-names = "i2c-exio1";
};

&i2c2	{
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "i2c-hdmi";

	clock-frequency = <100000>;
};

&iic2	{
	pinctrl-0 = <&iic2_pins>;
	pinctrl-names = "i2c-hdmi";

	clock-frequency = <100000>;
};

&i2c3	{
	pinctrl-0 = <&i2c3_pins>;
	pinctrl-names = "i2c-pwr";
};

&iic3	{
	pinctrl-0 = <&iic3_pins>;
	pinctrl-names = "i2c-pwr";
};

&pci0 {
	status = "okay";
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
};

&pci1 {
	status = "okay";
	pinctrl-0 = <&usb1_pins>;
	pinctrl-names = "default";
};

&xhci {
	status = "okay";
	pinctrl-0 = <&usb2_pins>;
	pinctrl-names = "default";
};

&pci2 {
	status = "okay";
	pinctrl-0 = <&usb2_pins>;
	pinctrl-names = "default";
};

&hsusb {
	status = "okay";
	pinctrl-0 = <&hsusb_pins>;
	pinctrl-names = "default";
	renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
};

&usbphy {
	status = "okay";
};

/* HDMI video input */
&vin0 {
	pinctrl-0 = <&vin0_pins>;
	pinctrl-names = "default";

	status = "okay";

	port {
		vin0ep2: endpoint {
			remote-endpoint = <&adv7612_out>;
			bus-width = <24>;
			hsync-active = <0>;
			vsync-active = <0>;
			pclk-sample = <1>;
			data-active = <1>;
		};
	};
};

/* composite video input */
&vin1 {
	pinctrl-0 = <&vin1_pins>;
	pinctrl-names = "default";

	status = "okay";

	port {
		vin1ep0: endpoint {
			remote-endpoint = <&adv7180>;
			bus-width = <8>;
		};
	};
};

&rcar_sound {
	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
	pinctrl-names = "default";

	/* Single DAI */
	#sound-dai-cells = <0>;

	status = "okay";

	rcar_sound,dai {
		dai0 {
			playback = <&ssi0>, <&src2>, <&dvc0>;
			capture  = <&ssi1>, <&src3>, <&dvc1>;
		};
	};
};

&rwdt {
	timeout-sec = <60>;
	status = "okay";
};

&ssi1 {
	shared-pin;
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the Stout board
 *
 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
 */

/dts-v1/;
#include "r8a7790.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "Stout";
	compatible = "renesas,stout", "renesas,r8a7790";

	aliases {
		serial0 = &scifa0;
	};

	chosen {
		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x40000000>;
	};

	leds {
		compatible = "gpio-leds";
		led1 {
			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
		};
		led2 {
			gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
		};
		led3 {
			gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
		};
		led5 {
			gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
		};
	};

	fixedregulator3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
		compatible = "regulator-fixed";

		regulator-name = "SDHI0 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	hdmi-out {
		compatible = "hdmi-connector";
		type = "a";

		port {
			hdmi_con_out: endpoint {
				remote-endpoint = <&adv7511_out>;
			};
		};
	};

	osc1_clk: osc1-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <148500000>;
	};

	osc4_clk: osc4-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <12000000>;
	};
};

&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";
	status = "okay";

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
		 <&osc1_clk>;
	clock-names = "du.0", "du.1", "du.2", "dclkin.0";

	ports {
		port@0 {
			endpoint {
				remote-endpoint = <&adv7511_in>;
			};
		};
	};
};

&lvds0 {
	ports {
		port@1 {
			lvds_connector0: endpoint {
			};
		};
	};
};

&lvds1 {
	ports {
		port@1 {
			lvds_connector1: endpoint {
			};
		};
	};
};

&extal_clk {
	clock-frequency = <20000000>;
};

&pfc {

	pinctrl-0 = <&scif_clk_pins>;
	pinctrl-names = "default";

	du_pins: du {
		groups = "du_rgb888", "du_sync_1", "du_clk_out_0";
		function = "du";
	};

	scifa0_pins: scifa0 {
		groups = "scifa0_data_b";
		function = "scifa0";
	};

	scif_clk_pins: scif_clk {
		groups = "scif_clk";
		function = "scif_clk";
	};

	ether_pins: ether {
		groups = "eth_link", "eth_mdio", "eth_rmii";
		function = "eth";
	};

	phy1_pins: phy1 {
		groups = "intc_irq1";
		function = "intc";
	};

	sdhi0_pins: sd0 {
		groups = "sdhi0_data4", "sdhi0_ctrl";
		function = "sdhi0";
		power-source = <3300>;
	};

	qspi_pins: qspi {
		groups = "qspi_ctrl", "qspi_data4";
		function = "qspi";
	};

	iic2_pins: iic2 {
		groups = "iic2_b";
		function = "iic2";
	};

	iic3_pins: iic3 {
		groups = "iic3";
		function = "iic3";
	};

	pmic_irq_pins: pmicirq {
		groups = "intc_irq2";
		function = "intc";
	};

	usb0_pins: usb0 {
		groups = "usb0";
		function = "usb0";
	};
};

&ether {
	pinctrl-0 = <&ether_pins>, <&phy1_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy1>;
	renesas,ether-link-active-low;
	status = "okay";

	phy1: ethernet-phy@1 {
		compatible = "ethernet-phy-id0022.1537",
			     "ethernet-phy-ieee802.3-c22";
		reg = <1>;
		interrupt-parent = <&irqc0>;
		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
		micrel,led-mode = <1>;
		reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
	};
};

&cmt0 {
	status = "okay";
};

&qspi {
	pinctrl-0 = <&qspi_pins>;
	pinctrl-names = "default";

	status = "okay";

	flash: flash@0 {
		compatible = "spansion,s25fl512s", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <30000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		spi-cpha;
		spi-cpol;
		m25p,fast-read;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "loader";
				reg = <0x00000000 0x00080000>;
				read-only;
			};
			partition@80000 {
				label = "uboot";
				reg = <0x00080000 0x00040000>;
				read-only;
			};
			partition@c0000 {
				label = "uboot-env";
				reg = <0x000c0000 0x00040000>;
				read-only;
			};
			partition@100000 {
				label = "flash";
				reg = <0x00100000 0x03f00000>;
			};
		};
	};
};

&scifa0 {
	pinctrl-0 = <&scifa0_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&scif_clk {
	clock-frequency = <14745600>;
};

&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vcc_sdhi0>;
	cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&cpu0 {
	cpu0-supply = <&vdd_dvfs>;
};

&iic2	{
	status = "okay";
	pinctrl-0 = <&iic2_pins>;
	pinctrl-names = "default";

	clock-frequency = <100000>;

	hdmi@39 {
		compatible = "adi,adv7511w";
		reg = <0x39>;
		interrupt-parent = <&gpio1>;
		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&osc4_clk>;
		clock-names = "cec";

		adi,input-depth = <8>;
		adi,input-colorspace = "rgb";
		adi,input-clock = "1x";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				adv7511_in: endpoint {
					remote-endpoint = <&du_out_rgb>;
				};
			};

			port@1 {
				reg = <1>;
				adv7511_out: endpoint {
					remote-endpoint = <&hdmi_con_out>;
				};
			};
		};
	};
};

&iic3 {
	pinctrl-names = "default";
	pinctrl-0 = <&iic3_pins>, <&pmic_irq_pins>;
	status = "okay";

	pmic@58 {
		compatible = "dlg,da9063";
		reg = <0x58>;
		interrupt-parent = <&irqc0>;
		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;

		onkey {
			compatible = "dlg,da9063-onkey";
		};

		rtc {
			compatible = "dlg,da9063-rtc";
		};

		watchdog {
			compatible = "dlg,da9063-watchdog";
		};
	};

	vdd_dvfs: regulator@68 {
		compatible = "dlg,da9210";
		reg = <0x68>;
		interrupt-parent = <&irqc0>;
		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;

		regulator-min-microvolt = <1000000>;
		regulator-max-microvolt = <1000000>;
		regulator-boot-on;
		regulator-always-on;
	};

	vdd: regulator@70 {
		compatible = "dlg,da9210";
		reg = <0x70>;
		interrupt-parent = <&irqc0>;
		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;

		regulator-min-microvolt = <1000000>;
		regulator-max-microvolt = <1000000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&pci0 {
	status = "okay";
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
};

&usbphy {
	status = "okay";
};