code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)

maintainers:
  - Rahul Tanwar <rtanwar@maxlinear.com>

description: |
  Intel's Advanced Programmable Interrupt Controller (APIC) is a
  family of interrupt controllers. The APIC is a split
  architecture design, with a local component (LAPIC) integrated
  into the processor itself and an external I/O APIC. Local APIC
  (lapic) receives interrupts from the processor's interrupt pins,
  from internal sources and from an external I/O APIC (ioapic).
  And it sends these to the processor core for handling.
  See [1] Chapter 8 for more details.

  Many of the Intel's generic devices like hpet, ioapic, lapic have
  the ce4100 name in their compatible property names because they
  first appeared in CE4100 SoC.

  This schema defines bindings for I/O APIC interrupt controller.

  [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf

properties:
  compatible:
    const: intel,ce4100-ioapic

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'

additionalProperties: false

examples:
  - |
    ioapic1: interrupt-controller@fec00000 {
        compatible = "intel,ce4100-ioapic";
        reg = <0xfec00000 0x1000>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)

maintainers:
  - Rahul Tanwar <rtanwar@maxlinear.com>

description: |
  Intel's Advanced Programmable Interrupt Controller (APIC) is a
  family of interrupt controllers. The APIC is a split
  architecture design, with a local component (LAPIC) integrated
  into the processor itself and an external I/O APIC. Local APIC
  (lapic) receives interrupts from the processor's interrupt pins,
  from internal sources and from an external I/O APIC (ioapic).
  And it sends these to the processor core for handling.
  See [1] Chapter 8 for more details.

  Many of the Intel's generic devices like hpet, ioapic, lapic have
  the ce4100 name in their compatible property names because they
  first appeared in CE4100 SoC.

  This schema defines bindings for local APIC interrupt controller.

  [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf

properties:
  compatible:
    const: intel,ce4100-lapic

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  intel,virtual-wire-mode:
    description: Intel defines a few possible interrupt delivery
      modes. With respect to boot/init time, mainly two interrupt
      delivery modes are possible.
      PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
      Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
      For ACPI or MPS spec compliant systems, it is figured out by some read
      only bit field/s available in their respective defined data structures.
      For OF based systems, it is by default set to PIC mode.
      But if this optional boolean property is set, then the interrupt delivery
      mode is configured to virtual wire compatibility mode.
    type: boolean

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'

additionalProperties: false

examples:
  - |
    lapic0: interrupt-controller@fee00000 {
        compatible = "intel,ce4100-lapic";
        reg = <0xfee00000 0x1000>;
        interrupt-controller;
        #interrupt-cells = <2>;
        intel,virtual-wire-mode;
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel IXP4xx XScale Networking Processors Interrupt Controller

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  This interrupt controller is found in the Intel IXP4xx processors.
  Some processors have 32 interrupts, some have up to 64 interrupts.
  The exact number of interrupts is determined from the compatible
  string.

  The distinct IXP4xx families with different interrupt controller
  variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four
  families were the only ones to reach the developer and consumer
  market.

properties:
  compatible:
    items:
      - enum:
          - intel,ixp42x-interrupt
          - intel,ixp43x-interrupt
          - intel,ixp45x-interrupt
          - intel,ixp46x-interrupt

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'

additionalProperties: false

examples:
  - |
    intcon: interrupt-controller@c8003000 {
        compatible = "intel,ixp43x-interrupt";
        reg = <0xc8003000 0x100>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };


code:
Specifying interrupt information for devices
============================================

1) Interrupt client nodes
-------------------------

Nodes that describe devices which generate interrupts must contain an
"interrupts" property, an "interrupts-extended" property, or both. If both are
present, the latter should take precedence; the former may be provided simply
for compatibility with software that does not recognize the latter. These
properties contain a list of interrupt specifiers, one per output interrupt. The
format of the interrupt specifier is determined by the interrupt controller to
which the interrupts are routed; see section 2 below for details.

  Example:
	interrupt-parent = <&intc1>;
	interrupts = <5 0>, <6 0>;

The "interrupt-parent" property is used to specify the controller to which
interrupts are routed and contains a single phandle referring to the interrupt
controller node. This property is inherited, so it may be specified in an
interrupt client node or in any of its parent nodes. Interrupts listed in the
"interrupts" property are always in reference to the node's interrupt parent.

The "interrupts-extended" property is a special form; useful when a node needs
to reference multiple interrupt parents or a different interrupt parent than
the inherited one. Each entry in this property contains both the parent phandle
and the interrupt specifier.

  Example:
	interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;

2) Interrupt controller nodes
-----------------------------

A device is marked as an interrupt controller with the "interrupt-controller"
property. This is a empty, boolean property. An additional "#interrupt-cells"
property defines the number of cells needed to specify a single interrupt.

It is the responsibility of the interrupt controller's binding to define the
length and format of the interrupt specifier. The following two variants are
commonly used:

  a) one cell
  -----------
  The #interrupt-cells property is set to 1 and the single cell defines the
  index of the interrupt within the controller.

  Example:

	vic: intc@10140000 {
		compatible = "arm,versatile-vic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x10140000 0x1000>;
	};

	sic: intc@10003000 {
		compatible = "arm,versatile-sic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x10003000 0x1000>;
		interrupt-parent = <&vic>;
		interrupts = <31>; /* Cascaded to vic */
	};

  b) two cells
  ------------
  The #interrupt-cells property is set to 2 and the first cell defines the
  index of the interrupt within the controller, while the second cell is used
  to specify any of the following flags:
    - bits[3:0] trigger type and level flags
        1 = low-to-high edge triggered
        2 = high-to-low edge triggered
        4 = active high level-sensitive
        8 = active low level-sensitive

  Example:

	i2c@7000c000 {
		gpioext: gpio-adnp@41 {
			compatible = "ad,gpio-adnp";
			reg = <0x41>;

			interrupt-parent = <&gpio>;
			interrupts = <160 1>;

			gpio-controller;
			#gpio-cells = <1>;

			interrupt-controller;
			#interrupt-cells = <2>;

			nr-gpios = <64>;
		};

		sx8634@2b {
			compatible = "smtc,sx8634";
			reg = <0x2b>;

			interrupt-parent = <&gpioext>;
			interrupts = <3 0x8>;

			#address-cells = <1>;
			#size-cells = <0>;

			threshold = <0x40>;
			sensitivity = <7>;
		};
	};

3) Interrupt wakeup parent
--------------------------

Some interrupt controllers in a SoC, are always powered on and have a select
interrupts routed to them, so that they can wakeup the SoC from suspend. These
interrupt controllers do not fall into the category of a parent interrupt
controller and can be specified by the "wakeup-parent" property and contain a
single phandle referring to the wakeup capable interrupt controller.

   Example:
	wakeup-parent = <&pdc_intc>;


code:
J-Core Advanced Interrupt Controller

Required properties:

- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
  with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
  the "aic2" core with 64 interrupts.

- reg: Memory region(s) for configuration. For SMP, there should be one
  region per cpu, indexed by the sequential, zero-based hardware cpu
  number.

- interrupt-controller: Identifies the node as an interrupt controller

- #interrupt-cells: Specifies the number of cells needed to encode an
  interrupt source. The value shall be 1.

Example:

aic: interrupt-controller@200 {
	compatible = "jcore,aic2";
	reg = < 0x200 0x30 0x500 0x30 >;
	interrupt-controller;
	#interrupt-cells = <1>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/kontron,sl28cpld-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Interrupt controller driver for the sl28cpld board management controller

maintainers:
  - Michael Walle <michael@walle.cc>

description: |
  This module is part of the sl28cpld multi-function device. For more
  details see ../mfd/kontron,sl28cpld.yaml.

  The following interrupts are available. All types and levels are fixed
  and handled by the board management controller.

  ==== ============= ==================================
   IRQ line/device   description
  ==== ============= ==================================
    0  RTC_INT#      Interrupt line from on-board RTC
    1  SMB_ALERT#    Event on SMB_ALERT# line (P1)
    2  ESPI_ALERT0#  Event on ESPI_ALERT0# line (S43)
    3  ESPI_ALERT1#  Event on ESPI_ALERT1# line (S44)
    4  PWR_BTN#      Event on PWR_BTN# line (P128)
    5  SLEEP#        Event on SLEEP# line (S149)
    6  watchdog      Interrupt of the internal watchdog
    7  n/a           not used
  ==== ============= ==================================

properties:
  compatible:
    enum:
      - kontron,sl28cpld-intc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#interrupt-cells":
    const: 2

  interrupt-controller: true

required:
  - compatible
  - interrupts
  - "#interrupt-cells"
  - interrupt-controller

additionalProperties: false


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LoongArch CPU Interrupt Controller

maintainers:
  - Liu Peibao <liupeibao@loongson.cn>

properties:
  compatible:
    const: loongarch,cpu-interrupt-controller

  '#interrupt-cells':
    const: 1

  interrupt-controller: true

additionalProperties: false

required:
  - compatible
  - '#interrupt-cells'
  - interrupt-controller

examples:
  - |
    interrupt-controller {
      compatible = "loongarch,cpu-interrupt-controller";
      #interrupt-cells = <1>;
      interrupt-controller;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Loongson-3 HyperTransport Interrupt Controller

maintainers:
  - Jiaxun Yang <jiaxun.yang@flygoat.com>

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

description: |
  This interrupt controller is found in the Loongson-3 family of chips to transmit
  interrupts from PCH PIC connected on HyperTransport bus.

properties:
  compatible:
    const: loongson,htpic-1.0

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 4
    description: |
      Four parent interrupts that receive chained interrupts.

  interrupt-controller: true

  '#interrupt-cells':
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    htintc: interrupt-controller@1fb000080 {
      compatible = "loongson,htpic-1.0";
      reg = <0xfb000080 0x40>;
      interrupt-controller;
      #interrupt-cells = <1>;

      interrupt-parent = <&liointc>;
      interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
                    <25 IRQ_TYPE_LEVEL_HIGH>,
                    <26 IRQ_TYPE_LEVEL_HIGH>,
                    <27 IRQ_TYPE_LEVEL_HIGH>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Loongson-3 HyperTransport Interrupt Vector Controller

maintainers:
  - Jiaxun Yang <jiaxun.yang@flygoat.com>

description:
  This interrupt controller is found in the Loongson-3 family of chips for
  receiving vectorized interrupts from PCH's interrupt controller.

properties:
  compatible:
    const: loongson,htvec-1.0

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 8
    description: Eight parent interrupts that receive chained interrupts.

  interrupt-controller: true

  '#interrupt-cells':
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    htvec: interrupt-controller@fb000080 {
      compatible = "loongson,htvec-1.0";
      reg = <0xfb000080 0x40>;
      interrupt-controller;
      #interrupt-cells = <1>;

      interrupt-parent = <&liointc>;
      interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
                    <25 IRQ_TYPE_LEVEL_HIGH>,
                    <26 IRQ_TYPE_LEVEL_HIGH>,
                    <27 IRQ_TYPE_LEVEL_HIGH>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Loongson Local I/O Interrupt Controller

maintainers:
  - Jiaxun Yang <jiaxun.yang@flygoat.com>

description: |
  This interrupt controller is found in the Loongson-3 family of chips and
  Loongson-2K1000 chip, as the primary package interrupt controller which
  can route local I/O interrupt to interrupt lines of cores.

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    enum:
      - loongson,liointc-1.0
      - loongson,liointc-1.0a
      - loongson,liointc-2.0

  reg:
    minItems: 1
    maxItems: 3

  reg-names:
    items:
      - const: main
      - const: isr0
      - const: isr1

  interrupt-controller: true

  interrupts:
    description:
      Interrupt source of the CPU interrupts.
    minItems: 1
    maxItems: 4

  interrupt-names:
    description: List of names for the parent interrupts.
    items:
      - const: int0
      - const: int1
      - const: int2
      - const: int3
    minItems: 1

  '#interrupt-cells':
    const: 2

  'loongson,parent_int_map':
    description: |
      This property points how the children interrupts will be mapped into CPU
      interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
      and each bit in the cell refers to a child interrupt from 0 to 31.
      If a CPU interrupt line didn't connect with liointc, then keep its
      cell with zero.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 4
    maxItems: 4

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'
  - 'loongson,parent_int_map'

unevaluatedProperties: false

if:
  properties:
    compatible:
      contains:
        enum:
          - loongson,liointc-2.0

then:
  properties:
    reg:
      minItems: 3

  required:
    - reg-names

else:
  properties:
    reg:
      maxItems: 1

examples:
  - |
    iointc: interrupt-controller@3ff01400 {
      compatible = "loongson,liointc-1.0";
      reg = <0x3ff01400 0x64>;

      interrupt-controller;
      #interrupt-cells = <2>;

      interrupt-parent = <&cpuintc>;
      interrupts = <2>, <3>;
      interrupt-names = "int0", "int1";

      loongson,parent_int_map = <0xf0ffffff>, /* int0 */
                                <0x0f000000>, /* int1 */
                                <0x00000000>, /* int2 */
                                <0x00000000>; /* int3 */

    };

...


code:
Loongson ls1x Interrupt Controller

Required properties:

- compatible : should be "loongson,ls1x-intc". Valid strings are:

- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The value shall be 2.
- interrupts : Specifies the CPU interrupt the controller is connected to.

Example:

intc: interrupt-controller@1fd01040 {
	compatible = "loongson,ls1x-intc";
	reg = <0x1fd01040 0x18>;

	interrupt-controller;
	#interrupt-cells = <2>;

	interrupt-parent = <&cpu_intc>;
	interrupts = <2>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Loongson PCH MSI Controller

maintainers:
  - Jiaxun Yang <jiaxun.yang@flygoat.com>

description:
  This interrupt controller is found in the Loongson LS7A family of PCH for
  transforming interrupts from PCIe MSI into HyperTransport vectorized
  interrupts.

properties:
  compatible:
    const: loongson,pch-msi-1.0

  reg:
    maxItems: 1

  loongson,msi-base-vec:
    description:
      u32 value of the base of parent HyperTransport vector allocated
      to PCH MSI.
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 255

  loongson,msi-num-vecs:
    description:
      u32 value of the number of parent HyperTransport vectors allocated
      to PCH MSI.
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 1
    maximum: 256

  msi-controller: true

required:
  - compatible
  - reg
  - msi-controller
  - loongson,msi-base-vec
  - loongson,msi-num-vecs

additionalProperties: true #fixme

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    msi: msi-controller@2ff00000 {
      compatible = "loongson,pch-msi-1.0";
      reg = <0x2ff00000 0x4>;
      msi-controller;
      loongson,msi-base-vec = <64>;
      loongson,msi-num-vecs = <64>;
      interrupt-parent = <&htvec>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Loongson PCH PIC Controller

maintainers:
  - Jiaxun Yang <jiaxun.yang@flygoat.com>

description:
  This interrupt controller is found in the Loongson LS7A family of PCH for
  transforming interrupts from on-chip devices into HyperTransport vectorized
  interrupts.

properties:
  compatible:
    const: loongson,pch-pic-1.0

  reg:
    maxItems: 1

  loongson,pic-base-vec:
    description:
      u32 value of the base of parent HyperTransport vector allocated
      to PCH PIC.
    $ref: "/schemas/types.yaml#/definitions/uint32"
    minimum: 0
    maximum: 192

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

required:
  - compatible
  - reg
  - loongson,pic-base-vec
  - interrupt-controller
  - '#interrupt-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    pic: interrupt-controller@10000000 {
      compatible = "loongson,pch-pic-1.0";
      reg = <0x10000000 0x400>;
      interrupt-controller;
      #interrupt-cells = <2>;
      loongson,pic-base-vec = <64>;
      interrupt-parent = <&htvec>;
    };
...


code:
TI-NSPIRE interrupt controller

Required properties:
- compatible: Compatible property value should be "lsi,zevio-intc".

- reg: Physical base address of the controller and length of memory mapped
	region.

- interrupt-controller : Identifies the node as an interrupt controller

Example:

interrupt-controller {
	compatible = "lsi,zevio-intc";
	interrupt-controller;
	reg = <0xDC000000 0x1000>;
	#interrupt-cells = <1>;
};


code:
Marvell Armada 370, 375, 38x, XP Interrupt Controller
-----------------------------------------------------

Required properties:
- compatible: Should be "marvell,mpic"
- interrupt-controller: Identifies the node as an interrupt controller.
- msi-controller: Identifies the node as an PCI Message Signaled
  Interrupt controller.
- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
  The cell is the IRQ number

- reg: Should contain PMIC registers location and length. First pair
  for the main interrupt registers, second pair for the per-CPU
  interrupt registers. For this last pair, to be compliant with SMP
  support, the "virtual" must be use (For the record, these registers
  automatically map to the interrupt controller registers of the
  current CPU)

Optional properties:

- interrupts: If defined, then it indicates that this MPIC is
  connected as a slave to another interrupt controller. This is
  typically the case on Armada 375 and Armada 38x, where the MPIC is
  connected as a slave to the Cortex-A9 GIC. The provided interrupt
  indicate to which GIC interrupt the MPIC output is connected.

Example:

        mpic: interrupt-controller@d0020000 {
              compatible = "marvell,mpic";
              #interrupt-cells = <1>;
              #address-cells = <1>;
              #size-cells = <1>;
              interrupt-controller;
              msi-controller;
              reg = <0xd0020a00 0x1d0>,
                    <0xd0021070 0x58>;
        };


code:
Marvell Armada 7K/8K PIC Interrupt controller
---------------------------------------------

This is the Device Tree binding for the PIC, a secondary interrupt
controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
typically connected to the GIC as the primary interrupt controller.

Required properties:
- compatible: should be "marvell,armada-8k-pic"
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: the number of cells to define interrupts on this
  controller. Should be 1
- reg: the register area for the PIC interrupt controller
- interrupts: the interrupt to the primary interrupt controller,
  typically the GIC

Example:

	pic: interrupt-controller@3f0100 {
		compatible = "marvell,armada-8k-pic";
		reg = <0x3f0100 0x10>;
		#interrupt-cells = <1>;
		interrupt-controller;
		interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
	};


code:
Marvell GICP Controller
-----------------------

GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
interrupts by doing a memory transaction. It is used by the ICU
located in the Marvell CP110 to turn wired interrupts inside the CP
into GIC SPI interrupts.

Required properties:

- compatible: Must be "marvell,ap806-gicp"

- reg: Must be the address and size of the GICP SPI registers

- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
  for this GICP

- msi-controller: indicates that this is an MSI controller

Example:

gicp_spi: gicp-spi@3f0040 {
	compatible = "marvell,ap806-gicp";
	reg = <0x3f0040 0x10>;
	marvell,spi-ranges = <64 64>, <288 64>;
	msi-controller;
};


code:
Marvell ICU Interrupt Controller
--------------------------------

The Marvell ICU (Interrupt Consolidation Unit) controller is
responsible for collecting all wired-interrupt sources in the CP and
communicating them to the GIC in the AP, the unit translates interrupt
requests on input wires to MSG memory mapped transactions to the GIC.
These messages will access a different GIC memory area depending on
their type (NSR, SR, SEI, REI, etc).

Required properties:

- compatible: Should be "marvell,cp110-icu"

- reg: Should contain ICU registers location and length.

Subnodes: Each group of interrupt is declared as a subnode of the ICU,
with their own compatible.

Required properties for the icu_nsr/icu_sei subnodes:

- compatible: Should be one of:
              * "marvell,cp110-icu-nsr"
	      * "marvell,cp110-icu-sr"
	      * "marvell,cp110-icu-sei"
	      * "marvell,cp110-icu-rei"

- #interrupt-cells: Specifies the number of cells needed to encode an
  interrupt source. The value shall be 2.

  The 1st cell is the index of the interrupt in the ICU unit.

  The 2nd cell is the type of the interrupt. See arm,gic.txt for
  details.

- interrupt-controller: Identifies the node as an interrupt
  controller.

- msi-parent: Should point to the GICP controller, the GIC extension
  that allows to trigger interrupts using MSG memory mapped
  transactions.

Note: each 'interrupts' property referring to any 'icu_xxx' node shall
      have a different number within [0:206].

Example:

icu: interrupt-controller@1e0000 {
	compatible = "marvell,cp110-icu";
	reg = <0x1e0000 0x440>;

	CP110_LABEL(icu_nsr): interrupt-controller@10 {
		compatible = "marvell,cp110-icu-nsr";
		reg = <0x10 0x20>;
		#interrupt-cells = <2>;
		interrupt-controller;
		msi-parent = <&gicp>;
	};

	CP110_LABEL(icu_sei): interrupt-controller@50 {
		compatible = "marvell,cp110-icu-sei";
		reg = <0x50 0x10>;
		#interrupt-cells = <2>;
		interrupt-controller;
		msi-parent = <&sei>;
	};
};

node1 {
	interrupt-parent = <&icu_nsr>;
	interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
};

node2 {
	interrupt-parent = <&icu_sei>;
	interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
};

/* Would not work with the above nodes */
node3 {
	interrupt-parent = <&icu_nsr>;
	interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
};

The legacy bindings were different in this way:

- #interrupt-cells: The value was 3.
	The 1st cell was the group type of the ICU interrupt. Possible
	group types were:
	ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
	ICU_GRP_SR  (0x1) : Shared peripheral interrupt, secure
	ICU_GRP_SEI (0x4) : System error interrupt
	ICU_GRP_REI (0x5) : RAM error interrupt
	The 2nd cell was the index of the interrupt in the ICU unit.
	The 3rd cell was the type of the interrupt. See arm,gic.txt for
	details.

Example:

icu: interrupt-controller@1e0000 {
	compatible = "marvell,cp110-icu";
	reg = <0x1e0000 0x440>;

	#interrupt-cells = <3>;
	interrupt-controller;
	msi-parent = <&gicp>;
};

node1 {
	interrupt-parent = <&icu>;
	interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
};


code:
* Marvell ODMI for MSI support

Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
which can be used by on-board peripheral for MSI interrupts.

Required properties:

- compatible           : The value here should contain:

    "marvell,ap806-odmi-controller", "marvell,odmi-controller".

- interrupt,controller : Identifies the node as an interrupt controller.

- msi-controller       : Identifies the node as an MSI controller.

- marvell,odmi-frames  : Number of ODMI frames available. Each frame
                         provides a number of events.

- reg                  : List of register definitions, one for each
                         ODMI frame.

- marvell,spi-base     : List of GIC base SPI interrupts, one for each
                         ODMI frame. Those SPI interrupts are 0-based,
                         i.e marvell,spi-base = <128> will use SPI #96.
                         See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
                         for details about the GIC Device Tree binding.

Example:

	odmi: odmi@300000 {
		compatible = "marvell,ap806-odmi-controller",
			     "marvell,odmi-controller";
		interrupt-controller;
		msi-controller;
		marvell,odmi-frames = <4>;
		reg = <0x300000 0x4000>,
		      <0x304000 0x4000>,
		      <0x308000 0x4000>,
		      <0x30C000 0x4000>;
		marvell,spi-base = <128>, <136>, <144>, <152>;
	};


code:
Marvell Orion SoC interrupt controllers

* Main interrupt controller

Required properties:
- compatible: shall be "marvell,orion-intc"
- reg: base address(es) of interrupt registers starting with CAUSE register
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt source, shall be 1

The interrupt sources map to the corresponding bits in the interrupt
registers, i.e.
- 0 maps to bit 0 of first base address,
- 1 maps to bit 1 of first base address,
- 32 maps to bit 0 of second base address, and so on.

Example:
	intc: interrupt-controller {
		compatible = "marvell,orion-intc";
		interrupt-controller;
		#interrupt-cells = <1>;
		 /* Dove has 64 first level interrupts */
		reg = <0x20200 0x10>, <0x20210 0x10>;
	};

* Bridge interrupt controller

Required properties:
- compatible: shall be "marvell,orion-bridge-intc"
- reg: base address of bridge interrupt registers starting with CAUSE register
- interrupts: bridge interrupt of the main interrupt controller
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt source, shall be 1

Optional properties:
- marvell,#interrupts: number of interrupts provided by bridge interrupt
      controller, defaults to 32 if not set

Example:
	bridge_intc: interrupt-controller {
		compatible = "marvell,orion-bridge-intc";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x20110 0x8>;
		interrupts = <0>;
		/* Dove bridge provides 5 interrupts */
		marvell,#interrupts = <5>;
	};


code:
Marvell SEI (System Error Interrupt) Controller
-----------------------------------------------

Marvell SEI (System Error Interrupt) controller is an interrupt
aggregator. It receives interrupts from several sources and aggregates
them to a single interrupt line (an SPI) on the parent interrupt
controller.

This interrupt controller can handle up to 64 SEIs, a set comes from the
AP and is wired while a second set comes from the CPs by the mean of
MSIs.

Required properties:

- compatible: should be one of:
              * "marvell,ap806-sei"
- reg: SEI registers location and length.
- interrupts: identifies the parent IRQ that will be triggered.
- #interrupt-cells: number of cells to define an SEI wired interrupt
                    coming from the AP, should be 1. The cell is the IRQ
                    number.
- interrupt-controller: identifies the node as an interrupt controller
                        for AP interrupts.
- msi-controller: identifies the node as an MSI controller for the CPs
                  interrupts.

Example:

        sei: interrupt-controller@3f0200 {
                compatible = "marvell,ap806-sei";
                reg = <0x3f0200 0x40>;
                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
                #interrupt-cells = <1>;
                interrupt-controller;
                msi-controller;
        };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mtk-cirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek System Interrupt Controller

maintainers:
  - Youlin Pei <youlin.pei@mediatek.com>

description:
  In MediaTek SoCs, the CIRQ is a low power interrupt controller designed to
  work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC.
  The external interrupts (outside MCUSYS) will feed through CIRQ and connect
  to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
  interrupts and generate a pulse signal to parent interrupt controller when
  flush command is executed. With CIRQ, MCUSYS can be completely turned off
  to improve the system power consumption without losing interrupts.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt2701-cirq
          - mediatek,mt8135-cirq
          - mediatek,mt8173-cirq
          - mediatek,mt8192-cirq
      - const: mediatek,mtk-cirq

  reg:
    maxItems: 1

  '#interrupt-cells':
    const: 3

  interrupt-controller: true

  mediatek,ext-irq-range:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    items:
      - description: First CIRQ interrupt
      - description: Last CIRQ interrupt
    description:
      Identifies the range of external interrupts in different SoCs

required:
  - compatible
  - reg
  - '#interrupt-cells'
  - interrupt-controller
  - mediatek,ext-irq-range

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    cirq: interrupt-controller@10204000 {
        compatible = "mediatek,mt2701-cirq", "mediatek,mtk-cirq";
        reg = <0x10204000 0x400>;
        #interrupt-cells = <3>;
        interrupt-controller;
        interrupt-parent = <&sysirq>;
        mediatek,ext-irq-range = <32 200>;
    };


code:
MediaTek sysirq

MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
interrupt.

Required properties:
- compatible: should be
	"mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
	"mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183
	"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
	"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
	"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
	"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
	"mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623
	"mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
	"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
	"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
	"mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq": for MT6779
	"mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765
	"mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
	"mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
	"mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
	"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
	"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
	"mediatek,mt6577-sysirq": for MT6577
	"mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
	"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
- reg: Physical base address of the intpol registers and length of memory
  mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others
  need 1.

Example:
	sysirq: intpol-controller@10200620 {
		compatible = "mediatek,mt6797-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10220620 0 0x20>,
		      <0 0x10220690 0 0x10>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip External Interrupt Controller

maintainers:
  - Claudiu Beznea <claudiu.beznea@microchip.com>

description:
  This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides
  support for handling up to 2 external interrupt lines.

properties:
  compatible:
    enum:
      - microchip,sama7g5-eic

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2
    description:
      The first cell is the input IRQ number (between 0 and 1), the second cell
      is the trigger type as defined in interrupt.txt present in this directory.

  interrupts:
    description: |
      Contains the GIC SPI IRQs mapped to the external interrupt lines. They
      should be specified sequentially from output 0 to output 1.
    minItems: 2
    maxItems: 2

  clocks:
    maxItems: 1

  clock-names:
    const: pclk

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/at91.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    eic: interrupt-controller@e1628000 {
      compatible = "microchip,sama7g5-eic";
      reg = <0xe1628000 0x100>;
      interrupt-parent = <&gic>;
      interrupt-controller;
      #interrupt-cells = <2>;
      interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
      clock-names = "pclk";
    };

...


code:
Microchip PIC32 Interrupt Controller
====================================

The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC).
It handles all internal and external interrupts. This controller exists outside
of the CPU and is the arbitrator of all interrupts (including interrupts from
the CPU itself) before they are presented to the CPU.

External interrupts have a software configurable edge polarity. Non external
interrupts have a type and polarity that is determined by the source of the
interrupt.

Required properties
-------------------

- compatible: Should be "microchip,pic32mzda-evic"
- reg: Specifies physical base address and size of register range.
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt cells: Specifies the number of cells used to encode an interrupt
  source connected to this controller. The value shall be 2 and interrupt
  descriptor shall have the following format:

	<hw_irq irq_type>

  hw_irq - represents the hardware interrupt number as in the data sheet.
  irq_type - is used to describe the type and polarity of an interrupt. For
  internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and
  IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
  IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity.

Optional properties
-------------------
- microchip,external-irqs: u32 array of external interrupts with software
  polarity configuration. This array corresponds to the bits in the INTCON
  SFR.

Example
-------

evic: interrupt-controller@1f810000 {
	compatible = "microchip,pic32mzda-evic";
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x1f810000 0x1000>;
	microchip,external-irqs = <3 8 13 18 23>;
};

Each device/peripheral must request its interrupt line with the associated type
and polarity.

Internal interrupt DTS snippet
------------------------------

device@1f800000 {
	...
	interrupts = <113 IRQ_TYPE_LEVEL_HIGH>;
	...
};

External interrupt DTS snippet
------------------------------

device@1f800000 {
	...
	interrupts = <3 IRQ_TYPE_EDGE_RISING>;
	...
};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell MMP/Orion Interrupt controller bindings

maintainers:
  - Andrew Lunn <andrew@lunn.ch>
  - Gregory Clement <gregory.clement@bootlin.com>

allOf:
  - if:
      properties:
        compatible:
          not:
            contains:
              const: marvell,orion-intc
    then:
      required:
        - mrvl,intc-nr-irqs
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mrvl,mmp-intc
              - mrvl,mmp2-intc
    then:
      properties:
        reg:
          maxItems: 1
  - if:
      properties:
        compatible:
          contains:
            enum:
              - marvell,mmp3-intc
              - mrvl,mmp2-mux-intc
    then:
      properties:
        reg:
          minItems: 2
  - if:
      properties:
        compatible:
          contains:
            const: mrvl,mmp2-mux-intc
    then:
      properties:
        interrupts:
          maxItems: 1
        reg-names:
          items:
            - const: 'mux status'
            - const: 'mux mask'
      required:
        - interrupts
    else:
      properties:
        interrupts: false

properties:
  '#interrupt-cells':
    const: 1

  compatible:
    enum:
      - mrvl,mmp-intc
      - mrvl,mmp2-intc
      - marvell,mmp3-intc
      - marvell,orion-intc
      - mrvl,mmp2-mux-intc

  reg:
    minItems: 1
    maxItems: 2

  reg-names: true

  interrupts: true

  interrupt-controller: true

  mrvl,intc-nr-irqs:
    description: |
      Specifies the number of interrupts in the interrupt controller.
    $ref: /schemas/types.yaml#/definitions/uint32

  mrvl,clr-mfp-irq:
    description: |
      Specifies the interrupt that needs to clear MFP edge detection first.
    $ref: /schemas/types.yaml#/definitions/uint32

required:
  - '#interrupt-cells'
  - compatible
  - reg
  - interrupt-controller

additionalProperties: false

examples:
  - |
    interrupt-controller@d4282000 {
        compatible = "mrvl,mmp2-intc";
        interrupt-controller;
        #interrupt-cells = <1>;
        reg = <0xd4282000 0x1000>;
        mrvl,intc-nr-irqs = <64>;
    };

    interrupt-controller@d4282150 {
        compatible = "mrvl,mmp2-mux-intc";
        interrupts = <4>;
        interrupt-controller;
        #interrupt-cells = <1>;
        reg = <0x150 0x4>, <0x168 0x4>;
        reg-names = "mux status", "mux mask";
        mrvl,intc-nr-irqs = <2>;
    };
  - |
    interrupt-controller@fed20204 {
        compatible = "marvell,orion-intc";
        interrupt-controller;
        #interrupt-cells = <1>;
        reg = <0xfed20204 0x04>,
              <0xfed20214 0x04>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Microsemi Ocelot SoC ICPU Interrupt Controller

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

description: |
  the Microsemi Ocelot interrupt controller that is part of the
  ICPU. It is connected directly to the MIPS core interrupt
  controller.

properties:
  compatible:
    items:
      - enum:
          - mscc,jaguar2-icpu-intr
          - mscc,luton-icpu-intr
          - mscc,ocelot-icpu-intr
          - mscc,serval-icpu-intr

  '#interrupt-cells':
    const: 1

  '#address-cells':
    const: 0

  interrupt-controller: true

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - '#interrupt-cells'
  - '#address-cells'
  - interrupt-controller
  - reg

additionalProperties: false

examples:
  - |
    intc: interrupt-controller@70000070 {
        compatible = "mscc,ocelot-icpu-intr";
        reg = <0x70000070 0x70>;
        #interrupt-cells = <1>;
        #address-cells = <0>;
        interrupt-controller;
        interrupt-parent = <&cpuintc>;
        interrupts = <2>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MSI controller

maintainers:
  - Marc Zyngier <maz@kernel.org>

description: |
  An MSI controller signals interrupts to a CPU when a write is made
  to an MMIO address by some master. An MSI controller may feature a
  number of doorbells.

properties:
  "#msi-cells":
    description: |
      The number of cells in an msi-specifier, required if not zero.

      Typically this will encode information related to sideband data,
      and will not encode doorbells or payloads as these can be
      configured dynamically.

      The meaning of the msi-specifier is defined by the device tree
      binding of the specific MSI controller.
    enum: [0, 1]

  msi-controller:
    description:
      Identifies the node as an MSI controller.
    $ref: /schemas/types.yaml#/definitions/flag

  msi-ranges:
    description:
      A list of <phandle intspec span> tuples, where "phandle" is the
      parent interrupt controller, "intspec" is the starting/base
      interrupt specifier and "span" is the size of the
      range. Multiple ranges can be provided.
    $ref: /schemas/types.yaml#/definitions/phandle-array

dependencies:
  "#msi-cells": [ msi-controller ]

additionalProperties: true


code:
This document describes the generic device tree binding for MSI controllers and
their master(s).

Message Signaled Interrupts (MSIs) are a class of interrupts generated by a
write to an MMIO address.

MSIs were originally specified by PCI (and are used with PCIe), but may also be
used with other busses, and hence a mechanism is required to relate devices on
those busses to the MSI controllers which they are capable of using,
potentially including additional information.

MSIs are distinguished by some combination of:

- The doorbell (the MMIO address written to).

  Devices may be configured by software to write to arbitrary doorbells which
  they can address. An MSI controller may feature a number of doorbells.

- The payload (the value written to the doorbell).

  Devices may be configured to write an arbitrary payload chosen by software.
  MSI controllers may have restrictions on permitted payloads.

- Sideband information accompanying the write.

  Typically this is neither configurable nor probeable, and depends on the path
  taken through the memory system (i.e. it is a property of the combination of
  MSI controller and device rather than a property of either in isolation).

MSI controllers:
================

An MSI controller signals interrupts to a CPU when a write is made to an MMIO
address by some master. An MSI controller may feature a number of doorbells.

Required properties:
--------------------

- msi-controller: Identifies the node as an MSI controller.

Optional properties:
--------------------

- #msi-cells: The number of cells in an msi-specifier, required if not zero.

  Typically this will encode information related to sideband data, and will
  not encode doorbells or payloads as these can be configured dynamically.

  The meaning of the msi-specifier is defined by the device tree binding of
  the specific MSI controller.

MSI clients
===========

MSI clients are devices which generate MSIs. For each MSI they wish to
generate, the doorbell and payload may be configured, though sideband
information may not be configurable.

Required properties:
--------------------

- msi-parent: A list of phandle + msi-specifier pairs, one for each MSI
  controller which the device is capable of using.

  This property is unordered, and MSIs may be allocated from any combination of
  MSI controllers listed in the msi-parent property.

  If a device has restrictions on the allocation of MSIs, these restrictions
  must be described with additional properties.

  When #msi-cells is non-zero, busses with an msi-parent will require
  additional properties to describe the relationship between devices on the bus
  and the set of MSIs they can potentially generate.

Example
=======

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	msi_a: msi-controller@a {
		reg = <0xa 0xf00>;
		compatible = "vendor-a,some-controller";
		msi-controller;
		/* No sideband data, so #msi-cells omitted */
	};

	msi_b: msi-controller@b {
		reg = <0xb 0xf00>;
		compatible = "vendor-b,another-controller";
		msi-controller;
		/* Each device has some unique ID */
		#msi-cells = <1>;
	};

	msi_c: msi-controller@c {
		reg = <0xc 0xf00>;
		compatible = "vendor-b,another-controller";
		msi-controller;
		/* Each device has some unique ID */
		#msi-cells = <1>;
	};

	dev@0 {
		reg = <0x0 0xf00>;
		compatible = "vendor-c,some-device";

		/* Can only generate MSIs to msi_a */
		msi-parent = <&msi_a>;
	};

	dev@1 {
		reg = <0x1 0xf00>;
		compatible = "vendor-c,some-device";

		/*
		 * Can generate MSIs to either A or B.
		 */
		msi-parent = <&msi_a>, <&msi_b 0x17>;
	};

	dev@2 {
		reg = <0x2 0xf00>;
		compatible = "vendor-c,some-device";
		/*
		 * Has different IDs at each MSI controller.
		 * Can generate MSIs to all of the MSI controllers.
		 */
		msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MStar Interrupt Controller

maintainers:
  - Mark-PK Tsai <mark-pk.tsai@mediatek.com>

description: |+
  MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy
  interrupt controllers that routes interrupts to the GIC.

  The HW block exposes a number of interrupt controllers, each
  can support up to 64 interrupts.

properties:
  compatible:
    const: mstar,mst-intc

  interrupt-controller: true

  "#interrupt-cells":
    const: 3
    description: |
      Use the same format as specified by GIC in arm,gic.yaml.

  reg:
    maxItems: 1

  mstar,irqs-map-range:
    description: |
      The range <start, end> of parent interrupt controller's interrupt
      lines that are hardwired to mstar interrupt controller.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    items:
      minItems: 2
      maxItems: 2

  mstar,intc-no-eoi:
    description:
      Mark this controller has no End Of Interrupt(EOI) implementation.
    type: boolean

required:
  - compatible
  - reg
  - mstar,irqs-map-range

additionalProperties: false

examples:
  - |
    mst_intc0: interrupt-controller@1f2032d0 {
      compatible = "mstar,mst-intc";
      interrupt-controller;
      #interrupt-cells = <3>;
      interrupt-parent = <&gic>;
      reg = <0x1f2032d0 0x30>;
      mstar,irqs-map-range = <0 63>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mti,cpu-interrupt-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MIPS CPU Interrupt Controller

description: >
   On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
   IRQs from a devicetree file and create a irq_domain for IRQ controller.

   With the irq_domain in place we can describe how the 8 IRQs are wired to the
   platforms internal interrupt controller cascade.

maintainers:
  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>

properties:
  compatible:
    const: mti,cpu-interrupt-controller

  '#interrupt-cells':
    const: 1

  '#address-cells':
    const: 0

  interrupt-controller: true

additionalProperties: false

required:
  - compatible
  - '#interrupt-cells'
  - '#address-cells'
  - interrupt-controller

examples:
  - |
    interrupt-controller {
      compatible = "mti,cpu-interrupt-controller";
      #address-cells = <0>;
      #interrupt-cells = <1>;
      interrupt-controller;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MIPS Global Interrupt Controller

maintainers:
  - Paul Burton <paulburton@kernel.org>
  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>

description: |
  The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
  It also supports local (per-processor) interrupts and software-generated
  interrupts which can be used as IPIs. The GIC also includes a free-running
  global timer, per-CPU count/compare timers, and a watchdog.

properties:
  compatible:
    const: mti,gic

  "#interrupt-cells":
    const: 3
    description: |
      The 1st cell is the type of interrupt: local or shared defined in the
      file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
      GIC interrupt number. The 3d cell encodes the interrupt flags setting up
      the IRQ trigger modes, which are defined in the file
      'dt-bindings/interrupt-controller/irq.h'.

  reg:
    description: |
      Base address and length of the GIC registers space. If not present,
      the base address reported by the hardware GCR_GIC_BASE will be used.
    maxItems: 1

  interrupt-controller: true

  mti,reserved-cpu-vectors:
    description: |
      Specifies the list of CPU interrupt vectors to which the GIC may not
      route interrupts. This property is ignored if the CPU is started in EIC
      mode.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 6
    uniqueItems: true
    items:
      minimum: 2
      maximum: 7

  mti,reserved-ipi-vectors:
    description: |
      Specifies the range of GIC interrupts that are reserved for IPIs.
      It accepts two values: the 1st is the starting interrupt and the 2nd is
      the size of the reserved range. If not specified, the driver will
      allocate the last (2 * number of VPEs in the system).
    $ref: /schemas/types.yaml#/definitions/uint32-array
    items:
      - minimum: 0
        maximum: 254
      - minimum: 2
        maximum: 254

  timer:
    type: object
    description: |
      MIPS GIC includes a free-running global timer, per-CPU count/compare
      timers, and a watchdog. Currently only the GIC Timer is supported.
    properties:
      compatible:
        const: mti,gic-timer

      interrupts:
        description: |
          Interrupt for the GIC local timer, so normally it's suppose to be of
          <GIC_LOCAL X IRQ_TYPE_NONE> format.
        maxItems: 1

      clocks:
        maxItems: 1

      clock-frequency: true

    required:
      - compatible
      - interrupts

    oneOf:
      - required:
          - clocks
      - required:
          - clock-frequency

    additionalProperties: false

additionalProperties: false

required:
  - compatible
  - "#interrupt-cells"
  - interrupt-controller

examples:
  - |
    #include <dt-bindings/interrupt-controller/mips-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    interrupt-controller@1bdc0000 {
      compatible = "mti,gic";
      reg = <0x1bdc0000 0x20000>;
      interrupt-controller;
      #interrupt-cells = <3>;
      mti,reserved-cpu-vectors = <7>;
      mti,reserved-ipi-vectors = <40 8>;

      timer {
        compatible = "mti,gic-timer";
        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
        clock-frequency = <50000000>;
      };
    };
  - |
    #include <dt-bindings/interrupt-controller/mips-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    interrupt-controller@1bdc0000 {
      compatible = "mti,gic";
      reg = <0x1bdc0000 0x20000>;
      interrupt-controller;
      #interrupt-cells = <3>;

      timer {
        compatible = "mti,gic-timer";
        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
        clocks = <&cpu_pll>;
      };
    };
  - |
    interrupt-controller {
      compatible = "mti,gic";
      interrupt-controller;
      #interrupt-cells = <3>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/nuvoton,wpcm450-aic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Nuvoton WPCM450 Advanced Interrupt Controller bindings

maintainers:
  - Jonathan Neuschäfer <j.neuschaefer@gmx.net>

properties:
  '#interrupt-cells':
    const: 2

  compatible:
    const: nuvoton,wpcm450-aic

  interrupt-controller: true

  reg:
    maxItems: 1

additionalProperties: false

required:
  - '#interrupt-cells'
  - compatible
  - reg
  - interrupt-controller

examples:
  - |
    aic: interrupt-controller@b8002000 {
        compatible = "nuvoton,wpcm450-aic";
        reg = <0xb8002000 0x1000>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };


code:
NVIDIA Legacy Interrupt Controller

All Tegra SoCs contain a legacy interrupt controller that routes
interrupts to the GIC, and also serves as a wakeup source. It is also
referred to as "ictlr", hence the name of the binding.

The HW block exposes a number of interrupt controllers, each
implementing a set of 32 interrupts.

Required properties:

- compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on
  subsequent SoCs remained backwards-compatible with Tegra30, so on
  Tegra generations later than Tegra30 the compatible value should
  include "nvidia,tegra30-ictlr".
- reg : Specifies base physical address and size of the registers.
  Each controller must be described separately (Tegra20 has 4 of them,
  whereas Tegra30 and later have 5).
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The value must be 3.

Notes:

- Because this HW ultimately routes interrupts to the GIC, the
  interrupt specifier must be that of the GIC.
- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
  are explicitly forbidden.

Example:

	ictlr: interrupt-controller@60004000 {
		compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr";
		reg = <0x60004000 64>,
		      <0x60004100 64>,
		      <0x60004200 64>,
		      <0x60004300 64>;
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&intc>;
	};


code:
* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers

Required properties:
- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
- reg: should contain IC registers location and length.
- interrupt-controller: identifies the node as an interrupt controller.
- #interrupt-cells: the number of cells to define an interrupt, should be 2.
  The first cell is the IRQ number, the second cell is used to specify
  one of the supported IRQ types:
      IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
      IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
      IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
      IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
  Reset value is IRQ_TYPE_LEVEL_LOW.

Optional properties:
- interrupts: empty for MIC interrupt controller, cascaded MIC
  hardware interrupts for SIC1 and SIC2

Examples:

	/* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
	mic: interrupt-controller@40008000 {
		compatible = "nxp,lpc3220-mic";
		reg = <0x40008000 0x4000>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	sic1: interrupt-controller@4000c000 {
		compatible = "nxp,lpc3220-sic";
		reg = <0x4000c000 0x4000>;
		interrupt-controller;
		#interrupt-cells = <2>;

		interrupt-parent = <&mic>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
			     <30 IRQ_TYPE_LEVEL_LOW>;
	};

	sic2: interrupt-controller@40010000 {
		compatible = "nxp,lpc3220-sic";
		reg = <0x40010000 0x4000>;
		interrupt-controller;
		#interrupt-cells = <2>;

		interrupt-parent = <&mic>;
		interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
			     <31 IRQ_TYPE_LEVEL_LOW>;
	};

	/* ADC */
	adc@40048000 {
		compatible = "nxp,lpc3220-adc";
		reg = <0x40048000 0x1000>;
		interrupt-parent = <&sic1>;
		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
	};


code:
* Open PIC Binding

This binding specifies what properties must be available in the device tree
representation of an Open PIC compliant interrupt controller.  This binding is
based on the binding defined for Open PIC in [1] and is a superset of that
binding.

Required properties:

  NOTE: Many of these descriptions were paraphrased here from [1] to aid
        readability.

    - compatible: Specifies the compatibility list for the PIC.  The type
      shall be <string> and the value shall include "open-pic".

    - reg: Specifies the base physical address(s) and size(s) of this
      PIC's addressable register space.  The type shall be <prop-encoded-array>.

    - interrupt-controller: The presence of this property identifies the node
      as an Open PIC.  No property value shall be defined.

    - #interrupt-cells: Specifies the number of cells needed to encode an
      interrupt source.  The type shall be a <u32> and the value shall be 2.

    - #address-cells: Specifies the number of cells needed to encode an
      address.  The type shall be <u32> and the value shall be 0.  As such,
      'interrupt-map' nodes do not have to specify a parent unit address.

Optional properties:

    - pic-no-reset: The presence of this property indicates that the PIC
      shall not be reset during runtime initialization.  No property value shall
      be defined.  The presence of this property also mandates that any
      initialization related to interrupt sources shall be limited to sources
      explicitly referenced in the device tree.

* Interrupt Specifier Definition

  Interrupt specifiers consists of 2 cells encoded as
  follows:

    - <1st-cell>: The interrupt-number that identifies the interrupt source.

    - <2nd-cell>: The level-sense information, encoded as follows:
                    0 = low-to-high edge triggered
                    1 = active low level-sensitive
                    2 = active high level-sensitive
                    3 = high-to-low edge triggered

* Examples

Example 1:

	/*
	 * An Open PIC interrupt controller
	 */
	mpic: pic@40000 {
		// This is an interrupt controller node.
		interrupt-controller;

		// No address cells so that 'interrupt-map' nodes which reference
		// this Open PIC node do not need a parent address specifier.
		#address-cells = <0>;

		// Two cells to encode interrupt sources.
		#interrupt-cells = <2>;

		// Offset address of 0x40000 and size of 0x40000.
		reg = <0x40000 0x40000>;

		// Compatible with Open PIC.
		compatible = "open-pic";

		// The PIC shall not be reset.
		pic-no-reset;
	};

Example 2:

	/*
	 * An interrupt generating device that is wired to an Open PIC.
	 */
	serial0: serial@4500 {
		// Interrupt source '42' that is active high level-sensitive.
		// Note that there are only two cells as specified in the interrupt
		// parent's '#interrupt-cells' property.
		interrupts = <42 2>;

		// The interrupt controller that this device is wired to.
		interrupt-parent = <&mpic>;
	};

* References

[1] Devicetree Specification
    (https://www.devicetree.org/specifications/)


code:
OpenRISC 1000 Programmable Interrupt Controller

Required properties:

- compatible : should be "opencores,or1k-pic-level" for variants with
  level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
  edge triggered interrupt lines or "opencores,or1200-pic" for machines
  with the non-spec compliant or1200 type implementation.

  "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
  but this is only for backwards compatibility.

- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The value shall be 1.

Example:

intc: interrupt-controller {
	compatible = "opencores,or1k-pic-level";
	interrupt-controller;
	#interrupt-cells = <1>;
};


code:
Open Multi-Processor Interrupt Controller

Required properties:

- compatible : This should be "openrisc,ompic"
- reg : Specifies base physical address and size of the register space. The
  size is based on the number of cores the controller has been configured
  to handle, this should be set to 8 bytes per cpu core.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : This should be set to 0 as this will not be an irq
  parent.
- interrupts : Specifies the interrupt line to which the ompic is wired.

Example:

ompic: interrupt-controller@98000000 {
	compatible = "openrisc,ompic";
	reg = <0x98000000 16>;
	interrupt-controller;
	#interrupt-cells = <0>;
	interrupts = <1>;
};


code:
Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller

On most SoC the IRQ controller need to flush the DDR FIFO before running
the interrupt handler of some devices. This is configured using the
qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.

Required Properties:

- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
  as fallback
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
		     source, should be 1 for intc

Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.

Optional Properties:

- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
  buffer flush
- qca,ddr-wb-channels: List of phandles to the write buffer channels for
  each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
  default to the entry's index.

Example:

	interrupt-controller {
		compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";

		interrupt-controller;
		#interrupt-cells = <1>;

		qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
					<&ddr_ctrl 0>, <&ddr_ctrl 1>;
	};

	...

	ddr_ctrl: memory-controller@18000000 {
		...
		#qca,ddr-wb-channel-cells = <1>;
	};


code:
Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller

The MISC interrupt controller is a secondary controller for lower priority
interrupt.

Required Properties:
- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
  "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
- reg: Base address and size of the controllers memory area
- interrupts: Interrupt specifier for the controllers interrupt.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
		     source, should be 1

Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
use ar7240 for all other SoCs.

Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.

Example:

	interrupt-controller@18060010 {
		compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
		reg = <0x18060010 0x4>;

		interrupt-parent = <&cpuintc>;
		interrupts = <6>;

		interrupt-controller;
		#interrupt-cells = <1>;
	};

Another example:

	interrupt-controller@18060010 {
		compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
		reg = <0x18060010 0x4>;

		interrupt-parent = <&cpuintc>;
		interrupts = <6>;

		interrupt-controller;
		#interrupt-cells = <1>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcom MPM Interrupt Controller

maintainers:
  - Shawn Guo <shawn.guo@linaro.org>

description:
  Qualcomm Technologies Inc. SoCs based on the RPM architecture have a
  MSM Power Manager (MPM) that is in always-on domain. In addition to managing
  resources during sleep, the hardware also has an interrupt controller that
  monitors the interrupts when the system is asleep, wakes up the APSS when
  one of these interrupts occur and replays it to GIC interrupt controller
  after GIC becomes operational.

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    items:
      - const: qcom,mpm

  reg:
    maxItems: 1
    description:
      Specifies the base address and size of vMPM registers in RPM MSG RAM.

  interrupts:
    maxItems: 1
    description:
      Specify the IRQ used by RPM to wakeup APSS.

  mboxes:
    maxItems: 1
    description:
      Specify the mailbox used to notify RPM for writing vMPM registers.

  interrupt-controller: true

  '#interrupt-cells':
    const: 2
    description:
      The first cell is the MPM pin number for the interrupt, and the second
      is the trigger type.

  qcom,mpm-pin-count:
    description:
      Specify the total MPM pin count that a SoC supports.
    $ref: /schemas/types.yaml#/definitions/uint32

  qcom,mpm-pin-map:
    description:
      A set of MPM pin numbers and the corresponding GIC SPIs.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    items:
      items:
        - description: MPM pin number
        - description: GIC SPI number for the MPM pin

required:
  - compatible
  - reg
  - interrupts
  - mboxes
  - interrupt-controller
  - '#interrupt-cells'
  - qcom,mpm-pin-count
  - qcom,mpm-pin-map

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    mpm: interrupt-controller@45f01b8 {
        compatible = "qcom,mpm";
        interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
        reg = <0x45f01b8 0x1000>;
        mboxes = <&apcs_glb 1>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupt-parent = <&intc>;
        qcom,mpm-pin-count = <96>;
        qcom,mpm-pin-map = <2 275>,
                           <5 296>,
                           <12 422>,
                           <24 79>,
                           <86 183>,
                           <90 260>,
                           <91 260>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PDC interrupt controller

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |
  Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
  Power Domain Controller (PDC) that is on always-on domain. In addition to
  providing power control for the power domains, the hardware also has an
  interrupt controller that can be used to help detect edge low interrupts as
  well detect interrupts when the GIC is non-operational.

  GIC is parent interrupt controller at the highest level. Platform interrupt
  controller PDC is next in hierarchy, followed by others. Drivers requiring
  wakeup capabilities of their device interrupts routed through the PDC, must
  specify PDC as their interrupt controller and request the PDC port associated
  with the GIC interrupt. See example below.

properties:
  compatible:
    items:
      - enum:
          - qcom,sc7180-pdc
          - qcom,sc7280-pdc
          - qcom,sc8280xp-pdc
          - qcom,sdm845-pdc
          - qcom,sdx55-pdc
          - qcom,sdx65-pdc
          - qcom,sm6350-pdc
          - qcom,sm8150-pdc
          - qcom,sm8250-pdc
          - qcom,sm8350-pdc
          - qcom,sm8450-pdc
      - const: qcom,pdc

  reg:
    minItems: 1
    items:
      - description: PDC base register region
      - description: Edge or Level config register for SPI interrupts

  '#interrupt-cells':
    const: 2

  interrupt-controller: true

  qcom,pdc-ranges:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    minItems: 1
    maxItems: 32 # no hard limit
    items:
      items:
        - description: starting PDC port
        - description: GIC hwirq number for the PDC port
        - description: number of interrupts in sequence
    description: |
      Specifies the PDC pin offset and the number of PDC ports.
      The tuples indicates the valid mapping of valid PDC ports
      and their hwirq mapping.

required:
  - compatible
  - reg
  - '#interrupt-cells'
  - interrupt-controller
  - qcom,pdc-ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    pdc: interrupt-controller@b220000 {
        compatible = "qcom,sdm845-pdc", "qcom,pdc";
        reg = <0xb220000 0x30000>;
        qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
        #interrupt-cells = <2>;
        interrupt-parent = <&intc>;
        interrupt-controller;
    };

    wake-device {
        interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/rda,8810pl-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RDA Micro RDA8810PL interrupt controller

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    const: rda,8810pl-intc

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'

additionalProperties: false

examples:
  - |
    intc: interrupt-controller@0 {
      compatible = "rda,8810pl-intc";
      reg = <0x0 0x1000>;
      interrupt-controller;
      #interrupt-cells = <2>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Realtek RTL SoC interrupt controller devicetree bindings

description:
  Interrupt controller and router for Realtek MIPS SoCs, allowing each SoC
  interrupt to be routed to one parent CPU (hardware) interrupt, or left
  disconnected.
  All connected input lines from SoC peripherals can be masked individually,
  and an interrupt status register is present to indicate which interrupts are
  pending.

maintainers:
  - Birger Koblitz <mail@birger-koblitz.de>
  - Bert Vermeulen <bert@biot.com>
  - John Crispin <john@phrozen.org>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - realtek,rtl8380-intc
          - const: realtek,rtl-intc
      - const: realtek,rtl-intc
        deprecated: true

  "#interrupt-cells":
    description:
      SoC interrupt line index.
    const: 1

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 15
    description:
      List of parent interrupts, in the order that they are connected to this
      interrupt router's outputs, starting at the first output.

  interrupt-controller: true

  interrupt-map:
    deprecated: true
    description: Describes mapping from SoC interrupts to CPU interrupts

required:
  - compatible
  - reg
  - "#interrupt-cells"
  - interrupt-controller

allOf:
  - if:
      properties:
        compatible:
          const: realtek,rtl-intc
    then:
      properties:
        "#address-cells":
          const: 0
      required:
        - "#address-cells"
        - interrupt-map
    else:
      required:
        - interrupts

additionalProperties: false

examples:
  - |
    interrupt-controller@3000 {
      compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
      #interrupt-cells = <1>;
      interrupt-controller;
      reg = <0x3000 0x18>;

      interrupt-parent = <&cpuintc>;
      interrupts = <2>, <3>, <4>, <5>, <6>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Interrupt Controller (INTC) for external pins

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

properties:
  compatible:
    items:
      - enum:
          - renesas,intc-irqpin-r8a7740  # R-Mobile A1
          - renesas,intc-irqpin-r8a7778  # R-Car M1A
          - renesas,intc-irqpin-r8a7779  # R-Car H1
          - renesas,intc-irqpin-sh73a0   # SH-Mobile AG5
      - const: renesas,intc-irqpin

  reg:
    minItems: 5
    items:
      - description: Interrupt control register
      - description: Interrupt priority register
      - description: Interrupt source register
      - description: Interrupt mask register
      - description: Interrupt mask clear register
      - description: Interrupt control register for ICR0 with IRLM0 bit

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  interrupts:
    minItems: 1
    maxItems: 8

  sense-bitfield-width:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [2, 4]
    default: 4
    description:
      Width of a single sense bitfield in the SENSE register, if different from the
      default.

  control-parent:
    type: boolean
    description:
      Disable and enable interrupts on the parent interrupt controller, needed for some
      broken implementations.

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'
  - interrupts

if:
  properties:
    compatible:
      contains:
        enum:
          - renesas,intc-irqpin-r8a7740
          - renesas,intc-irqpin-sh73a0
then:
  required:
    - clocks
    - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7740-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    irqpin1: interrupt-controller@e6900004 {
        compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
        reg = <0xe6900004 4>,
              <0xe6900014 4>,
              <0xe6900024 1>,
              <0xe6900044 1>,
              <0xe6900064 1>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
        power-domains = <&pd_a4s>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,irqc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

properties:
  compatible:
    items:
      - enum:
          - renesas,irqc-r8a73a4        # R-Mobile APE6
          - renesas,irqc-r8a7742        # RZ/G1H
          - renesas,irqc-r8a7743        # RZ/G1M
          - renesas,irqc-r8a7744        # RZ/G1N
          - renesas,irqc-r8a7745        # RZ/G1E
          - renesas,irqc-r8a77470       # RZ/G1C
          - renesas,irqc-r8a7790        # R-Car H2
          - renesas,irqc-r8a7791        # R-Car M2-W
          - renesas,irqc-r8a7792        # R-Car V2H
          - renesas,irqc-r8a7793        # R-Car M2-N
          - renesas,irqc-r8a7794        # R-Car E2
          - renesas,intc-ex-r8a774a1    # RZ/G2M
          - renesas,intc-ex-r8a774b1    # RZ/G2N
          - renesas,intc-ex-r8a774c0    # RZ/G2E
          - renesas,intc-ex-r8a774e1    # RZ/G2H
          - renesas,intc-ex-r8a7795     # R-Car H3
          - renesas,intc-ex-r8a7796     # R-Car M3-W
          - renesas,intc-ex-r8a77961    # R-Car M3-W+
          - renesas,intc-ex-r8a77965    # R-Car M3-N
          - renesas,intc-ex-r8a77970    # R-Car V3M
          - renesas,intc-ex-r8a77980    # R-Car V3H
          - renesas,intc-ex-r8a77990    # R-Car E3
          - renesas,intc-ex-r8a77995    # R-Car D3
          - renesas,intc-ex-r8a779a0    # R-Car V3U
          - renesas,intc-ex-r8a779g0    # R-Car V4H
      - const: renesas,irqc

  '#interrupt-cells':
    # an interrupt index and flags, as defined in interrupts.txt in
    # this directory
    const: 2

  interrupt-controller: true

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 32

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - '#interrupt-cells'
  - interrupt-controller
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    irqc0: interrupt-controller@e61c0000 {
        compatible = "renesas,irqc-r8a7790", "renesas,irqc";
        #interrupt-cells = <2>;
        interrupt-controller;
        reg = <0xe61c0000 0x200>;
        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD 407>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/A1 Interrupt Controller

maintainers:
  - Chris Brandt <chris.brandt@renesas.com>
  - Geert Uytterhoeven <geert+renesas@glider.be>

description: |
  The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
  RZ/A2 SoCs:
    - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
    - NMI edge select.

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - renesas,r7s72100-irqc # RZ/A1H
          - renesas,r7s9210-irqc  # RZ/A2M
      - const: renesas,rza1-irqc

  '#interrupt-cells':
    const: 2

  '#address-cells':
    const: 0

  interrupt-controller: true

  reg:
    maxItems: 1

  interrupt-map:
    maxItems: 8
    description: Specifies the mapping from external interrupts to GIC interrupts.

  interrupt-map-mask:
    items:
      - const: 7
      - const: 0

required:
  - compatible
  - '#interrupt-cells'
  - '#address-cells'
  - interrupt-controller
  - reg
  - interrupt-map
  - interrupt-map-mask

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    irqc: interrupt-controller@fcfef800 {
            compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
            #interrupt-cells = <2>;
            #address-cells = <0>;
            interrupt-controller;
            reg = <0xfcfef800 0x6>;
            interrupt-map =
                    <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                    <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                    <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                    <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                    <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                    <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
                    <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                    <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-map-mask = <7 0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)

maintainers:
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  - Geert Uytterhoeven <geert+renesas@glider.be>

description: |
  IA55 performs various interrupt controls including synchronization for the external
  interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
  interrupts output by each IP. And it notifies the interrupt to the GIC
    - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
    - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
    - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
      stand-up edge detection interrupts)

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - renesas,r9a07g044-irqc    # RZ/G2{L,LC}
          - renesas,r9a07g054-irqc    # RZ/V2L
      - const: renesas,rzg2l-irqc

  '#interrupt-cells':
    description: The first cell should contain external interrupt number (IRQ0-7) and the
                 second cell is used to specify the flag.
    const: 2

  '#address-cells':
    const: 0

  interrupt-controller: true

  reg:
    maxItems: 1

  interrupts:
    maxItems: 41

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: clk
      - const: pclk

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - '#interrupt-cells'
  - '#address-cells'
  - interrupt-controller
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains
  - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/r9a07g044-cpg.h>

    irqc: interrupt-controller@110a0000 {
            compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
            reg = <0x110a0000 0x10000>;
            #interrupt-cells = <2>;
            #address-cells = <0>;
            interrupt-controller;
            interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
                     <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
            clock-names = "clk", "pclk";
            power-domains = <&cpg>;
            resets = <&cpg R9A07G044_IA55_RESETN>;
    };


code:
RISC-V Hart-Level Interrupt Controller (HLIC)
---------------------------------------------

RISC-V cores include Control Status Registers (CSRs) which are local to each
CPU core (HART in RISC-V terminology) and can be read or written by software.
Some of these CSRs are used to control local interrupts connected to the core.
Every interrupt is ultimately routed through a hart's HLIC before it
interrupts that hart.

The RISC-V supervisor ISA manual specifies three interrupt sources that are
attached to every HLIC: software interrupts, the timer interrupt, and external
interrupts.  Software interrupts are used to send IPIs between cores.  The
timer interrupt comes from an architecturally mandated real-time timer that is
controlled via Supervisor Binary Interface (SBI) calls and CSR reads.  External
interrupts connect all other device interrupts to the HLIC, which are routed
via the platform-level interrupt controller (PLIC).

All RISC-V systems that conform to the supervisor ISA specification are
required to have a HLIC with these three interrupt sources present.  Since the
interrupt map is defined by the ISA it's not listed in the HLIC's device tree
entry, though external interrupt controllers (like the PLIC, for example) will
need to define how their interrupts map to the relevant HLICs.  This means
a PLIC interrupt property will typically list the HLICs for all present HARTs
in the system.

Required properties:
- compatible : "riscv,cpu-intc"
- #interrupt-cells : should be <1>.  The interrupt sources are defined by the
  RISC-V supervisor ISA manual, with only the following three interrupts being
  defined for supervisor mode:
    - Source 1 is the supervisor software interrupt, which can be sent by an SBI
      call and is reserved for use by software.
    - Source 5 is the supervisor timer interrupt, which can be configured by
      SBI calls and implements a one-shot timer.
    - Source 9 is the supervisor external interrupt, which chains to all other
      device interrupts.
- interrupt-controller : Identifies the node as an interrupt controller

Furthermore, this interrupt-controller MUST be embedded inside the cpu
definition of the hart whose CSRs control these local interrupts.

An example device tree entry for a HLIC is show below.

	cpu1: cpu@1 {
		compatible = "riscv";
		...
		cpu1-intc: interrupt-controller {
			#interrupt-cells = <1>;
			compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
			interrupt-controller;
		};
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC Interrupt Combiner Controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  Samsung's Exynos4 architecture includes a interrupt combiner controller which
  can combine interrupt sources as a group and provide a single interrupt
  request for the group. The interrupt request from each group are connected to
  a parent interrupt controller, such as GIC in case of Exynos4210.

  The interrupt combiner controller consists of multiple combiners. Up to eight
  interrupt sources can be connected to a combiner. The combiner outputs one
  combined interrupt for its eight interrupt sources. The combined interrupt is
  usually connected to a parent interrupt controller.

  A single node in the device tree is used to describe the interrupt combiner
  controller module (which includes multiple combiners). A combiner in the
  interrupt controller module shares config/control registers with other
  combiners. For example, a 32-bit interrupt enable/disable config register can
  accommodate up to 4 interrupt combiners (with each combiner supporting up to
  8 interrupt sources).

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    const: samsung,exynos4210-combiner

  interrupt-controller: true

  interrupts:
    minItems: 8
    maxItems: 32

  "#interrupt-cells":
    description: |
      The meaning of the cells are:
        * First Cell: Combiner Group Number.
        * Second Cell: Interrupt number within the group.
    const: 2

  reg:
    maxItems: 1

  samsung,combiner-nr:
    description: |
      The number of interrupt combiners supported.  Should match number
      of interrupts set in "interrupts" property.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 8
    maximum: 32
    default: 16

required:
  - compatible
  - interrupt-controller
  - interrupts
  - "#interrupt-cells"
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    interrupt-controller@10440000 {
        compatible = "samsung,exynos4210-combiner";
        interrupt-controller;
        #interrupt-cells = <2>;
        reg = <0x10440000 0x1000>;
        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
    };


code:
Samsung S3C24XX Interrupt Controllers

The S3C24XX SoCs contain a custom set of interrupt controllers providing a
varying number of interrupt sources. The set consists of a main- and sub-
controller and on newer SoCs even a second main controller.

Required properties:
- compatible: Compatible property value should be "samsung,s3c2410-irq"
  for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.

- reg: Physical base address of the controller and length of memory mapped
  region.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The value shall be 4 and interrupt descriptor shall
  have the following format:
      <ctrl_num parent_irq ctrl_irq type>

  ctrl_num contains the controller to use:
      - 0 ... main controller
      - 1 ... sub controller
      - 2 ... second main controller on s3c2416 and s3c2450
  parent_irq contains the parent bit in the main controller and will be
             ignored in main controllers
  ctrl_irq contains the interrupt bit of the controller
  type contains the trigger type to use

Example:

	interrupt-controller@4a000000 {
		compatible = "samsung,s3c2410-irq";
		reg = <0x4a000000 0x100>;
		interrupt-controller;
		#interrupt-cells=<4>;
	};

	[...]

	serial@50000000 {
		compatible = "samsung,s3c2410-uart";
		reg = <0x50000000 0x4000>;
		interrupt-parent = <&subintc>;
		interrupts = <1 28 0 4>, <1 28 1 4>;
	};

	rtc@57000000 {
		compatible = "samsung,s3c2410-rtc";
		reg = <0x57000000 0x100>;
		interrupt-parent = <&intc>;
		interrupts = <0 30 0 3>, <0 8 0 3>;
	};