code:
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 */

#ifndef __DTS_IMX1_PINFUNC_H
#define __DTS_IMX1_PINFUNC_H

/*
 * The pin function ID is a tuple of
 * <pin mux_id>
 * mux_id consists of
 * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
 *
 * function:      0 - Primary function
 *                1 - Alternate function
 *                2 - GPIO
 * direction:     0 - Input
 *                1 - Output
 * gpio_oconf:    0 - A_IN
 *                1 - B_IN
 *                2 - A_OUT
 *                3 - Data Register
 * gpio_iconfa/b: 0 - GPIO_IN
 *                1 - Interrupt Status Register
 *                2 - 0
 *                3 - 1
 *
 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32
 * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is
 * the pin number on the specific port (between 0 and 31).
 */

#define MX1_PAD_A24__A24			0x00 0x004
#define MX1_PAD_A24__GPIO1_0			0x00 0x032
#define MX1_PAD_A24__SPI2_CLK			0x00 0x006
#define MX1_PAD_TIN__TIN			0x01 0x000
#define MX1_PAD_TIN__GPIO1_1			0x01 0x032
#define MX1_PAD_TIN__SPI2_RXD			0x01 0x022
#define MX1_PAD_PWMO__PWMO			0x02 0x004
#define MX1_PAD_PWMO__GPIO1_2			0x02 0x032
#define MX1_PAD_CSI_MCLK__CSI_MCLK		0x03 0x004
#define MX1_PAD_CSI_MCLK__GPIO1_3		0x03 0x032
#define MX1_PAD_CSI_D0__CSI_D0			0x04 0x000
#define MX1_PAD_CSI_D0__GPIO1_4			0x04 0x032
#define MX1_PAD_CSI_D1__CSI_D1			0x05 0x000
#define MX1_PAD_CSI_D1__GPIO1_5			0x05 0x032
#define MX1_PAD_CSI_D2__CSI_D2			0x06 0x000
#define MX1_PAD_CSI_D2__GPIO1_6			0x06 0x032
#define MX1_PAD_CSI_D3__CSI_D3			0x07 0x000
#define MX1_PAD_CSI_D3__GPIO1_7			0x07 0x032
#define MX1_PAD_CSI_D4__CSI_D4			0x08 0x000
#define MX1_PAD_CSI_D4__GPIO1_8			0x08 0x032
#define MX1_PAD_CSI_D5__CSI_D5			0x09 0x000
#define MX1_PAD_CSI_D5__GPIO1_9			0x09 0x032
#define MX1_PAD_CSI_D6__CSI_D6			0x0a 0x000
#define MX1_PAD_CSI_D6__GPIO1_10		0x0a 0x032
#define MX1_PAD_CSI_D7__CSI_D7			0x0b 0x000
#define MX1_PAD_CSI_D7__GPIO1_11		0x0b 0x032
#define MX1_PAD_CSI_VSYNC__CSI_VSYNC		0x0c 0x000
#define MX1_PAD_CSI_VSYNC__GPIO1_12		0x0c 0x032
#define MX1_PAD_CSI_HSYNC__CSI_HSYNC		0x0d 0x000
#define MX1_PAD_CSI_HSYNC__GPIO1_13		0x0d 0x032
#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK		0x0e 0x000
#define MX1_PAD_CSI_PIXCLK__GPIO1_14		0x0e 0x032
#define MX1_PAD_I2C_SDA__I2C_SDA		0x0f 0x000
#define MX1_PAD_I2C_SDA__GPIO1_15		0x0f 0x032
#define MX1_PAD_I2C_SCL__I2C_SCL		0x10 0x004
#define MX1_PAD_I2C_SCL__GPIO1_16		0x10 0x032
#define MX1_PAD_DTACK__DTACK			0x11 0x000
#define MX1_PAD_DTACK__GPIO1_17			0x11 0x032
#define MX1_PAD_DTACK__SPI2_SS			0x11 0x002
#define MX1_PAD_DTACK__A25			0x11 0x016
#define MX1_PAD_BCLK__BCLK			0x12 0x004
#define MX1_PAD_BCLK__GPIO1_18			0x12 0x032
#define MX1_PAD_LBA__LBA			0x13 0x004
#define MX1_PAD_LBA__GPIO1_19			0x13 0x032
#define MX1_PAD_ECB__ECB			0x14 0x000
#define MX1_PAD_ECB__GPIO1_20			0x14 0x032
#define MX1_PAD_A0__A0				0x15 0x004
#define MX1_PAD_A0__GPIO1_21			0x15 0x032
#define MX1_PAD_CS4__CS4			0x16 0x004
#define MX1_PAD_CS4__GPIO1_22			0x16 0x032
#define MX1_PAD_CS5__CS5			0x17 0x004
#define MX1_PAD_CS5__GPIO1_23			0x17 0x032
#define MX1_PAD_A16__A16			0x18 0x004
#define MX1_PAD_A16__GPIO1_24			0x18 0x032
#define MX1_PAD_A17__A17			0x19 0x004
#define MX1_PAD_A17__GPIO1_25			0x19 0x032
#define MX1_PAD_A18__A18			0x1a 0x004
#define MX1_PAD_A18__GPIO1_26			0x1a 0x032
#define MX1_PAD_A19__A19			0x1b 0x004
#define MX1_PAD_A19__GPIO1_27			0x1b 0x032
#define MX1_PAD_A20__A20			0x1c 0x004
#define MX1_PAD_A20__GPIO1_28			0x1c 0x032
#define MX1_PAD_A21__A21			0x1d 0x004
#define MX1_PAD_A21__GPIO1_29			0x1d 0x032
#define MX1_PAD_A22__A22			0x1e 0x004
#define MX1_PAD_A22__GPIO1_30			0x1e 0x032
#define MX1_PAD_A23__A23			0x1f 0x004
#define MX1_PAD_A23__GPIO1_31			0x1f 0x032
#define MX1_PAD_SD_DAT0__SD_DAT0		0x28 0x000
#define MX1_PAD_SD_DAT0__MS_PI0			0x28 0x001
#define MX1_PAD_SD_DAT0__GPIO2_8		0x28 0x032
#define MX1_PAD_SD_DAT1__SD_DAT1		0x29 0x000
#define MX1_PAD_SD_DAT1__MS_PI1			0x29 0x001
#define MX1_PAD_SD_DAT1__GPIO2_9		0x29 0x032
#define MX1_PAD_SD_DAT2__SD_DAT2		0x2a 0x000
#define MX1_PAD_SD_DAT2__MS_SCLKI		0x2a 0x001
#define MX1_PAD_SD_DAT2__GPIO2_10		0x2a 0x032
#define MX1_PAD_SD_DAT3__SD_DAT3		0x2b 0x000
#define MX1_PAD_SD_DAT3__MS_SDIO		0x2b 0x001
#define MX1_PAD_SD_DAT3__GPIO2_11		0x2b 0x032
#define MX1_PAD_SD_SCLK__SD_SCLK		0x2c 0x004
#define MX1_PAD_SD_SCLK__MS_SCLKO		0x2c 0x005
#define MX1_PAD_SD_SCLK__GPIO2_12		0x2c 0x032
#define MX1_PAD_SD_CMD__SD_CMD			0x2d 0x000
#define MX1_PAD_SD_CMD__MS_BS			0x2d 0x005
#define MX1_PAD_SD_CMD__GPIO2_13		0x2d 0x032
#define MX1_PAD_SIM_SVEN__SIM_SVEN		0x2e 0x004
#define MX1_PAD_SIM_SVEN__SSI_RXFS		0x2e 0x001
#define MX1_PAD_SIM_SVEN__GPIO2_14		0x2e 0x032
#define MX1_PAD_SIM_PD__SIM_PD			0x2f 0x000
#define MX1_PAD_SIM_PD__SSI_RXCLK		0x2f 0x001
#define MX1_PAD_SIM_PD__GPIO2_15		0x2f 0x032
#define MX1_PAD_SIM_TX__SIM_TX			0x30 0x000
#define MX1_PAD_SIM_TX__SSI_RXDAT		0x30 0x001
#define MX1_PAD_SIM_TX__GPIO2_16		0x30 0x032
#define MX1_PAD_SIM_RX__SIM_RX			0x31 0x000
#define MX1_PAD_SIM_RX__SSI_TXDAT		0x31 0x005
#define MX1_PAD_SIM_RX__GPIO2_17		0x31 0x032
#define MX1_PAD_SIM_RST__SIM_RST		0x32 0x004
#define MX1_PAD_SIM_RST__SSI_TXFS		0x32 0x001
#define MX1_PAD_SIM_RST__GPIO2_18		0x32 0x032
#define MX1_PAD_SIM_CLK__SIM_CLK		0x33 0x004
#define MX1_PAD_SIM_CLK__SSI_TXCLK		0x33 0x001
#define MX1_PAD_SIM_CLK__GPIO2_19		0x33 0x032
#define MX1_PAD_USBD_AFE__USBD_AFE		0x34 0x004
#define MX1_PAD_USBD_AFE__GPIO2_20		0x34 0x032
#define MX1_PAD_USBD_OE__USBD_OE		0x35 0x004
#define MX1_PAD_USBD_OE__GPIO2_21		0x35 0x032
#define MX1_PAD_USBD_RCV__USBD_RCV		0x36 0x000
#define MX1_PAD_USBD_RCV__GPIO2_22		0x36 0x032
#define MX1_PAD_USBD_SUSPND__USBD_SUSPND	0x37 0x004
#define MX1_PAD_USBD_SUSPND__GPIO2_23		0x37 0x032
#define MX1_PAD_USBD_VP__USBD_VP		0x38 0x000
#define MX1_PAD_USBD_VP__GPIO2_24		0x38 0x032
#define MX1_PAD_USBD_VM__USBD_VM		0x39 0x000
#define MX1_PAD_USBD_VM__GPIO2_25		0x39 0x032
#define MX1_PAD_USBD_VPO__USBD_VPO		0x3a 0x004
#define MX1_PAD_USBD_VPO__GPIO2_26		0x3a 0x032
#define MX1_PAD_USBD_VMO__USBD_VMO		0x3b 0x004
#define MX1_PAD_USBD_VMO__GPIO2_27		0x3b 0x032
#define MX1_PAD_UART2_CTS__UART2_CTS		0x3c 0x004
#define MX1_PAD_UART2_CTS__GPIO2_28		0x3c 0x032
#define MX1_PAD_UART2_RTS__UART2_RTS		0x3d 0x000
#define MX1_PAD_UART2_RTS__GPIO2_29		0x3d 0x032
#define MX1_PAD_UART2_TXD__UART2_TXD		0x3e 0x004
#define MX1_PAD_UART2_TXD__GPIO2_30		0x3e 0x032
#define MX1_PAD_UART2_RXD__UART2_RXD		0x3f 0x000
#define MX1_PAD_UART2_RXD__GPIO2_31		0x3f 0x032
#define MX1_PAD_SSI_RXFS__SSI_RXFS		0x43 0x000
#define MX1_PAD_SSI_RXFS__GPIO3_3		0x43 0x032
#define MX1_PAD_SSI_RXCLK__SSI_RXCLK		0x44 0x000
#define MX1_PAD_SSI_RXCLK__GPIO3_4		0x44 0x032
#define MX1_PAD_SSI_RXDAT__SSI_RXDAT		0x45 0x000
#define MX1_PAD_SSI_RXDAT__GPIO3_5		0x45 0x032
#define MX1_PAD_SSI_TXDAT__SSI_TXDAT		0x46 0x004
#define MX1_PAD_SSI_TXDAT__GPIO3_6		0x46 0x032
#define MX1_PAD_SSI_TXFS__SSI_TXFS		0x47 0x000
#define MX1_PAD_SSI_TXFS__GPIO3_7		0x47 0x032
#define MX1_PAD_SSI_TXCLK__SSI_TXCLK		0x48 0x000
#define MX1_PAD_SSI_TXCLK__GPIO3_8		0x48 0x032
#define MX1_PAD_UART1_CTS__UART1_CTS		0x49 0x004
#define MX1_PAD_UART1_CTS__GPIO3_9		0x49 0x032
#define MX1_PAD_UART1_RTS__UART1_RTS		0x4a 0x000
#define MX1_PAD_UART1_RTS__GPIO3_10		0x4a 0x032
#define MX1_PAD_UART1_TXD__UART1_TXD		0x4b 0x004
#define MX1_PAD_UART1_TXD__GPIO3_11		0x4b 0x032
#define MX1_PAD_UART1_RXD__UART1_RXD		0x4c 0x000
#define MX1_PAD_UART1_RXD__GPIO3_12		0x4c 0x032
#define MX1_PAD_SPI1_RDY__SPI1_RDY		0x4d 0x000
#define MX1_PAD_SPI1_RDY__GPIO3_13		0x4d 0x032
#define MX1_PAD_SPI1_SCLK__SPI1_SCLK		0x4e 0x004
#define MX1_PAD_SPI1_SCLK__GPIO3_14		0x4e 0x032
#define MX1_PAD_SPI1_SS__SPI1_SS		0x4f 0x000
#define MX1_PAD_SPI1_SS__GPIO3_15		0x4f 0x032
#define MX1_PAD_SPI1_MISO__SPI1_MISO		0x50 0x000
#define MX1_PAD_SPI1_MISO__GPIO3_16		0x50 0x032
#define MX1_PAD_SPI1_MOSI__SPI1_MOSI		0x51 0x004
#define MX1_PAD_SPI1_MOSI__GPIO3_17		0x51 0x032
#define MX1_PAD_BT13__BT13			0x53 0x004
#define MX1_PAD_BT13__SSI2_RXCLK		0x53 0x001
#define MX1_PAD_BT13__GPIO3_19			0x53 0x032
#define MX1_PAD_BT12__BT12			0x54 0x004
#define MX1_PAD_BT12__SSI2_TXFS			0x54 0x001
#define MX1_PAD_BT12__GPIO3_20			0x54 0x032
#define MX1_PAD_BT11__BT11			0x55 0x004
#define MX1_PAD_BT11__SSI2_TXCLK		0x55 0x001
#define MX1_PAD_BT11__GPIO3_21			0x55 0x032
#define MX1_PAD_BT10__BT10			0x56 0x004
#define MX1_PAD_BT10__SSI2_TX			0x56 0x001
#define MX1_PAD_BT10__GPIO3_22			0x56 0x032
#define MX1_PAD_BT9__BT9			0x57 0x004
#define MX1_PAD_BT9__SSI2_RX			0x57 0x001
#define MX1_PAD_BT9__GPIO3_23			0x57 0x032
#define MX1_PAD_BT8__BT8			0x58 0x004
#define MX1_PAD_BT8__SSI2_RXFS			0x58 0x001
#define MX1_PAD_BT8__GPIO3_24			0x58 0x032
#define MX1_PAD_BT8__UART3_RI			0x58 0x016
#define MX1_PAD_BT7__BT7			0x59 0x004
#define MX1_PAD_BT7__GPIO3_25			0x59 0x032
#define MX1_PAD_BT7__UART3_DSR			0x59 0x016
#define MX1_PAD_BT6__BT6			0x5a 0x004
#define MX1_PAD_BT6__GPIO3_26			0x5a 0x032
#define MX1_PAD_BT6__SPI2_SS3			0x5a 0x016
#define MX1_PAD_BT6__UART3_DTR			0x5a 0x022
#define MX1_PAD_BT5__BT5			0x5b 0x000
#define MX1_PAD_BT5__GPIO3_27			0x5b 0x032
#define MX1_PAD_BT5__UART3_DCD			0x5b 0x016
#define MX1_PAD_BT4__BT4			0x5c 0x000
#define MX1_PAD_BT4__GPIO3_28			0x5c 0x032
#define MX1_PAD_BT4__UART3_CTS			0x5c 0x016
#define MX1_PAD_BT3__BT3			0x5d 0x000
#define MX1_PAD_BT3__GPIO3_29			0x5d 0x032
#define MX1_PAD_BT3__UART3_RTS			0x5d 0x022
#define MX1_PAD_BT2__BT2			0x5e 0x004
#define MX1_PAD_BT2__GPIO3_30			0x5e 0x032
#define MX1_PAD_BT2__UART3_TX			0x5e 0x016
#define MX1_PAD_BT1__BT1			0x5f 0x000
#define MX1_PAD_BT1__GPIO3_31			0x5f 0x032
#define MX1_PAD_BT1__UART3_RX			0x5f 0x022
#define MX1_PAD_LSCLK__LSCLK			0x66 0x004
#define MX1_PAD_LSCLK__GPIO4_6			0x66 0x032
#define MX1_PAD_REV__REV			0x67 0x004
#define MX1_PAD_REV__UART2_DTR			0x67 0x001
#define MX1_PAD_REV__GPIO4_7			0x67 0x032
#define MX1_PAD_REV__SPI2_CLK			0x67 0x006
#define MX1_PAD_CLS__CLS			0x68 0x004
#define MX1_PAD_CLS__UART2_DCD			0x68 0x005
#define MX1_PAD_CLS__GPIO4_8			0x68 0x032
#define MX1_PAD_CLS__SPI2_SS			0x68 0x002
#define MX1_PAD_PS__PS				0x69 0x004
#define MX1_PAD_PS__UART2_RI			0x69 0x005
#define MX1_PAD_PS__GPIO4_9			0x69 0x032
#define MX1_PAD_PS__SPI2_RXD			0x69 0x022
#define MX1_PAD_SPL_SPR__SPL_SPR		0x6a 0x004
#define MX1_PAD_SPL_SPR__UART2_DSR		0x6a 0x005
#define MX1_PAD_SPL_SPR__GPIO4_10		0x6a 0x032
#define MX1_PAD_SPL_SPR__SPI2_TXD		0x6a 0x006
#define MX1_PAD_CONTRAST__CONTRAST		0x6b 0x004
#define MX1_PAD_CONTRAST__GPIO4_11		0x6b 0x032
#define MX1_PAD_CONTRAST__SPI2_SS2		0x6b 0x012
#define MX1_PAD_ACD_OE__ACD_OE			0x6c 0x004
#define MX1_PAD_ACD_OE__GPIO4_12		0x6c 0x032
#define MX1_PAD_LP_HSYNC__LP_HSYNC		0x6d 0x004
#define MX1_PAD_LP_HSYNC__GPIO4_13		0x6d 0x032
#define MX1_PAD_FLM_VSYNC__FLM_VSYNC		0x6e 0x004
#define MX1_PAD_FLM_VSYNC__GPIO4_14		0x6e 0x032
#define MX1_PAD_LD0__LD0			0x6f 0x004
#define MX1_PAD_LD0__GPIO4_15			0x6f 0x032
#define MX1_PAD_LD1__LD1			0x70 0x004
#define MX1_PAD_LD1__GPIO4_16			0x70 0x032
#define MX1_PAD_LD2__LD2			0x71 0x004
#define MX1_PAD_LD2__GPIO4_17			0x71 0x032
#define MX1_PAD_LD3__LD3			0x72 0x004
#define MX1_PAD_LD3__GPIO4_18			0x72 0x032
#define MX1_PAD_LD4__LD4			0x73 0x004
#define MX1_PAD_LD4__GPIO4_19			0x73 0x032
#define MX1_PAD_LD5__LD5			0x74 0x004
#define MX1_PAD_LD5__GPIO4_20			0x74 0x032
#define MX1_PAD_LD6__LD6			0x75 0x004
#define MX1_PAD_LD6__GPIO4_21			0x75 0x032
#define MX1_PAD_LD7__LD7			0x76 0x004
#define MX1_PAD_LD7__GPIO4_22			0x76 0x032
#define MX1_PAD_LD8__LD8			0x77 0x004
#define MX1_PAD_LD8__GPIO4_23			0x77 0x032
#define MX1_PAD_LD9__LD9			0x78 0x004
#define MX1_PAD_LD9__GPIO4_24			0x78 0x032
#define MX1_PAD_LD10__LD10			0x79 0x004
#define MX1_PAD_LD10__GPIO4_25			0x79 0x032
#define MX1_PAD_LD11__LD11			0x7a 0x004
#define MX1_PAD_LD11__GPIO4_26			0x7a 0x032
#define MX1_PAD_LD12__LD12			0x7b 0x004
#define MX1_PAD_LD12__GPIO4_27			0x7b 0x032
#define MX1_PAD_LD13__LD13			0x7c 0x004
#define MX1_PAD_LD13__GPIO4_28			0x7c 0x032
#define MX1_PAD_LD14__LD14			0x7d 0x004
#define MX1_PAD_LD14__GPIO4_29			0x7d 0x032
#define MX1_PAD_LD15__LD15			0x7e 0x004
#define MX1_PAD_LD15__GPIO4_30			0x7e 0x032
#define MX1_PAD_TMR2OUT__TMR2OUT		0x7f 0x000
#define MX1_PAD_TMR2OUT__GPIO4_31		0x7f 0x032
#define MX1_PAD_TMR2OUT__SPI2_TXD		0x7f 0x006

#endif


code:
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>

#include "imx1-pinfunc.h"

#include <dt-bindings/clock/imx1-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 */
	chosen {};

	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		i2c0 = &i2c;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		spi0 = &cspi1;
		spi1 = &cspi2;
	};

	aitc: aitc-interrupt-controller@223000 {
		compatible = "fsl,imx1-aitc", "fsl,avic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x00223000 0x1000>;
	};

	cpus {
		#size-cells = <0>;
		#address-cells = <1>;

		cpu@0 {
			device_type = "cpu";
			reg = <0>;
			compatible = "arm,arm920t";
			operating-points = <200000 1900000>;
			clock-latency = <62500>;
			clocks = <&clks IMX1_CLK_MCU>;
			voltage-tolerance = <5>;
		};
	};

	clocks {
		clk32 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&aitc>;
		ranges;

		aipi@200000 {
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x00200000 0x10000>;
			ranges;

			gpt1: timer@202000 {
				compatible = "fsl,imx1-gpt";
				reg = <0x00202000 0x1000>;
				interrupts = <59>;
				clocks = <&clks IMX1_CLK_HCLK>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
			};

			gpt2: timer@203000 {
				compatible = "fsl,imx1-gpt";
				reg = <0x00203000 0x1000>;
				interrupts = <58>;
				clocks = <&clks IMX1_CLK_HCLK>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
			};

			fb: fb@205000 {
				compatible = "fsl,imx1-fb";
				reg = <0x00205000 0x1000>;
				interrupts = <14>;
				clocks = <&clks IMX1_CLK_DUMMY>,
					 <&clks IMX1_CLK_DUMMY>,
					 <&clks IMX1_CLK_PER2>;
				clock-names = "ipg", "ahb", "per";
				status = "disabled";
			};

			uart1: serial@206000 {
				compatible = "fsl,imx1-uart";
				reg = <0x00206000 0x1000>;
				interrupts = <30 29 26>;
				clocks = <&clks IMX1_CLK_HCLK>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@207000 {
				compatible = "fsl,imx1-uart";
				reg = <0x00207000 0x1000>;
				interrupts = <24 23 20>;
				clocks = <&clks IMX1_CLK_HCLK>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			pwm: pwm@208000 {
				#pwm-cells = <3>;
				compatible = "fsl,imx1-pwm";
				reg = <0x00208000 0x1000>;
				interrupts = <34>;
				clocks = <&clks IMX1_CLK_DUMMY>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
			};

			dma: dma@209000 {
				compatible = "fsl,imx1-dma";
				reg = <0x00209000 0x1000>;
				interrupts = <61 60>;
				clocks = <&clks IMX1_CLK_HCLK>,
					 <&clks IMX1_CLK_DMA_GATE>;
				clock-names = "ipg", "ahb";
				#dma-cells = <1>;
			};

			uart3: serial@20a000 {
				compatible = "fsl,imx1-uart";
				reg = <0x0020a000 0x1000>;
				interrupts = <54 4 1>;
				clocks = <&clks IMX1_CLK_UART3_GATE>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};

		aipi@210000 {
			compatible = "fsl,aipi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x00210000 0x10000>;
			ranges;

			cspi1: spi@213000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx1-cspi";
				reg = <0x00213000 0x1000>;
				interrupts = <41>;
				clocks = <&clks IMX1_CLK_DUMMY>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c: i2c@217000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx1-i2c";
				reg = <0x00217000 0x1000>;
				interrupts = <39>;
				clocks = <&clks IMX1_CLK_HCLK>;
				status = "disabled";
			};

			cspi2: spi@219000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx1-cspi";
				reg = <0x00219000 0x1000>;
				interrupts = <40>;
				clocks = <&clks IMX1_CLK_DUMMY>,
					 <&clks IMX1_CLK_PER1>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			clks: ccm@21b000 {
				compatible = "fsl,imx1-ccm";
				reg = <0x0021b000 0x1000>;
				#clock-cells = <1>;
			};

			iomuxc: iomuxc@21c000 {
				compatible = "fsl,imx1-iomuxc";
				reg = <0x0021c000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				gpio1: gpio@21c000 {
					compatible = "fsl,imx1-gpio";
					reg = <0x0021c000 0x100>;
					interrupts = <11>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio2: gpio@21c100 {
					compatible = "fsl,imx1-gpio";
					reg = <0x0021c100 0x100>;
					interrupts = <12>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio3: gpio@21c200 {
					compatible = "fsl,imx1-gpio";
					reg = <0x0021c200 0x100>;
					interrupts = <13>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio4: gpio@21c300 {
					compatible = "fsl,imx1-gpio";
					reg = <0x0021c300 0x100>;
					interrupts = <62>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};
			};
		};

		weim: weim@220000 {
			#address-cells = <2>;
			#size-cells = <1>;
			compatible = "fsl,imx1-weim";
			reg = <0x00220000 0x1000>;
			clocks = <&clks IMX1_CLK_DUMMY>;
			ranges = <
				0 0 0x10000000 0x02000000
				1 0 0x12000000 0x01000000
				2 0 0x13000000 0x01000000
				3 0 0x14000000 0x01000000
				4 0 0x15000000 0x01000000
				5 0 0x16000000 0x01000000
			>;
			status = "disabled";
		};

		esram: esram@300000 {
			compatible = "mmio-sram";
			reg = <0x00300000 0x20000>;
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.

/dts-v1/;
#include "imx23.dtsi"

/ {
	model = "Freescale i.MX23 Evaluation Kit";
	compatible = "fsl,imx23-evk", "fsl,imx23";

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0x08000000>;
	};

	reg_vddio_sd0: regulator-vddio-sd0 {
		compatible = "regulator-fixed";
		regulator-name = "vddio-sd0";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio1 29 0>;
	};

	reg_lcd_3v3: regulator-lcd-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "lcd-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio1 18 0>;
		enable-active-high;
	};

	reg_lcd_5v: regulator-lcd-5v {
		compatible = "regulator-fixed";
		regulator-name = "lcd-5v";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	panel {
		compatible = "sii,43wvf1g";
		backlight = <&backlight_display>;
		dvdd-supply = <&reg_lcd_3v3>;
		avdd-supply = <&reg_lcd_5v>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&display_out>;
			};
		};
	};

	apb@80000000 {
		apbh@80000000 {
			nand-controller@8000c000 {
				pinctrl-names = "default";
				pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>;
				status = "okay";
			};

			ssp0: spi@80010000 {
				compatible = "fsl,imx23-mmc";
				pinctrl-names = "default";
				pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
				bus-width = <4>;
				wp-gpios = <&gpio1 30 0>;
				vmmc-supply = <&reg_vddio_sd0>;
				status = "okay";
			};

			pinctrl@80018000 {
				pinctrl-names = "default";
				pinctrl-0 = <&hog_pins_a>;

				hog_pins_a: hog@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_LCD_RESET__GPIO_1_18
						MX23_PAD_PWM3__GPIO_1_29
						MX23_PAD_PWM4__GPIO_1_30
					>;
					fsl,drive-strength = <MXS_DRIVE_4mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};
			};

			lcdif@80030000 {
				pinctrl-names = "default";
				pinctrl-0 = <&lcdif_24bit_pins_a>;
				status = "okay";

				port {
					display_out: endpoint {
						remote-endpoint = <&panel_in>;
					};
				};
			};
		};

		apbx@80040000 {
			lradc@80050000 {
				status = "okay";
				fsl,lradc-touchscreen-wires = <4>;
			};

			pwm: pwm@80064000 {
				pinctrl-names = "default";
				pinctrl-0 = <&pwm2_pins_a>;
				status = "okay";
			};

			auart0: serial@8006c000 {
				pinctrl-names = "default";
				pinctrl-0 = <&auart0_pins_a>;
				status = "okay";
			};

			duart: serial@80070000 {
				pinctrl-names = "default";
				pinctrl-0 = <&duart_pins_a>;
				status = "okay";
			};

			usbphy0: usbphy@8007c000 {
				status = "okay";
			};
		};
	};

	ahb@80080000 {
		usb0: usb@80080000 {
			status = "okay";
		};
	};

	backlight_display: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm 2 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx23.dtsi"

/ {
	model = "i.MX23 Olinuxino Low Cost Board";
	compatible = "olimex,imx23-olinuxino", "fsl,imx23";

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0x04000000>;
	};

	apb@80000000 {
		apbh@80000000 {
			ssp0: spi@80010000 {
				compatible = "fsl,imx23-mmc";
				pinctrl-names = "default";
				pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
				bus-width = <4>;
				broken-cd;
				status = "okay";
			};

			pinctrl@80018000 {
				pinctrl-names = "default";
				pinctrl-0 = <&hog_pins_a>;

				hog_pins_a: hog@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_GPMI_ALE__GPIO_0_17
					>;
					fsl,drive-strength = <MXS_DRIVE_4mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};

				led_pin_gpio2_1: led_gpio2_1@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_SSP1_DETECT__GPIO_2_1
					>;
					fsl,drive-strength = <MXS_DRIVE_4mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};
			};

			ssp1: spi@80034000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx23-spi";
				pinctrl-names = "default";
				pinctrl-0 = <&spi2_pins_a>;
				status = "okay";
			};
		};

		apbx@80040000 {
			lradc@80050000 {
				status = "okay";
			};

			i2c: i2c@80058000 {
				pinctrl-names = "default";
				pinctrl-0 = <&i2c_pins_b>;
				status = "okay";
			};

			duart: serial@80070000 {
				pinctrl-names = "default";
				pinctrl-0 = <&duart_pins_a>;
				status = "okay";
			};

			auart0: serial@8006c000 {
				pinctrl-names = "default";
				pinctrl-0 = <&auart0_2pins_a>;
				status = "okay";
			};

			usbphy0: usbphy@8007c000 {
				status = "okay";
			};
		};
	};

	ahb@80080000 {
		usb0: usb@80080000 {
			dr_mode = "host";
			vbus-supply = <&reg_usb0_vbus>;
			status = "okay";
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usb0_vbus: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "usb0_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
			gpio = <&gpio0 17 0>;
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&led_pin_gpio2_1>;

		user {
			label = "green";
			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
		};
	};
};


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Header providing constants for i.MX23 pinctrl bindings.
 *
 * Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
 */

#ifndef __DT_BINDINGS_MX23_PINCTRL_H__
#define __DT_BINDINGS_MX23_PINCTRL_H__

#include "mxs-pinfunc.h"

#define MX23_PAD_GPMI_D00__GPMI_D00			0x0000
#define MX23_PAD_GPMI_D01__GPMI_D01			0x0010
#define MX23_PAD_GPMI_D02__GPMI_D02			0x0020
#define MX23_PAD_GPMI_D03__GPMI_D03			0x0030
#define MX23_PAD_GPMI_D04__GPMI_D04			0x0040
#define MX23_PAD_GPMI_D05__GPMI_D05			0x0050
#define MX23_PAD_GPMI_D06__GPMI_D06			0x0060
#define MX23_PAD_GPMI_D07__GPMI_D07			0x0070
#define MX23_PAD_GPMI_D08__GPMI_D08			0x0080
#define MX23_PAD_GPMI_D09__GPMI_D09			0x0090
#define MX23_PAD_GPMI_D10__GPMI_D10			0x00a0
#define MX23_PAD_GPMI_D11__GPMI_D11			0x00b0
#define MX23_PAD_GPMI_D12__GPMI_D12			0x00c0
#define MX23_PAD_GPMI_D13__GPMI_D13			0x00d0
#define MX23_PAD_GPMI_D14__GPMI_D14			0x00e0
#define MX23_PAD_GPMI_D15__GPMI_D15			0x00f0
#define MX23_PAD_GPMI_CLE__GPMI_CLE			0x0100
#define MX23_PAD_GPMI_ALE__GPMI_ALE			0x0110
#define MX23_PAD_GPMI_CE2N__GPMI_CE2N			0x0120
#define MX23_PAD_GPMI_RDY0__GPMI_RDY0			0x0130
#define MX23_PAD_GPMI_RDY1__GPMI_RDY1			0x0140
#define MX23_PAD_GPMI_RDY2__GPMI_RDY2			0x0150
#define MX23_PAD_GPMI_RDY3__GPMI_RDY3			0x0160
#define MX23_PAD_GPMI_WPN__GPMI_WPN			0x0170
#define MX23_PAD_GPMI_WRN__GPMI_WRN			0x0180
#define MX23_PAD_GPMI_RDN__GPMI_RDN			0x0190
#define MX23_PAD_AUART1_CTS__AUART1_CTS			0x01a0
#define MX23_PAD_AUART1_RTS__AUART1_RTS			0x01b0
#define MX23_PAD_AUART1_RX__AUART1_RX			0x01c0
#define MX23_PAD_AUART1_TX__AUART1_TX			0x01d0
#define MX23_PAD_I2C_SCL__I2C_SCL			0x01e0
#define MX23_PAD_I2C_SDA__I2C_SDA			0x01f0
#define MX23_PAD_LCD_D00__LCD_D00			0x1000
#define MX23_PAD_LCD_D01__LCD_D01			0x1010
#define MX23_PAD_LCD_D02__LCD_D02			0x1020
#define MX23_PAD_LCD_D03__LCD_D03			0x1030
#define MX23_PAD_LCD_D04__LCD_D04			0x1040
#define MX23_PAD_LCD_D05__LCD_D05			0x1050
#define MX23_PAD_LCD_D06__LCD_D06			0x1060
#define MX23_PAD_LCD_D07__LCD_D07			0x1070
#define MX23_PAD_LCD_D08__LCD_D08			0x1080
#define MX23_PAD_LCD_D09__LCD_D09			0x1090
#define MX23_PAD_LCD_D10__LCD_D10			0x10a0
#define MX23_PAD_LCD_D11__LCD_D11			0x10b0
#define MX23_PAD_LCD_D12__LCD_D12			0x10c0
#define MX23_PAD_LCD_D13__LCD_D13			0x10d0
#define MX23_PAD_LCD_D14__LCD_D14			0x10e0
#define MX23_PAD_LCD_D15__LCD_D15			0x10f0
#define MX23_PAD_LCD_D16__LCD_D16			0x1100
#define MX23_PAD_LCD_D17__LCD_D17			0x1110
#define MX23_PAD_LCD_RESET__LCD_RESET			0x1120
#define MX23_PAD_LCD_RS__LCD_RS				0x1130
#define MX23_PAD_LCD_WR__LCD_WR				0x1140
#define MX23_PAD_LCD_CS__LCD_CS				0x1150
#define MX23_PAD_LCD_DOTCK__LCD_DOTCK			0x1160
#define MX23_PAD_LCD_ENABLE__LCD_ENABLE			0x1170
#define MX23_PAD_LCD_HSYNC__LCD_HSYNC			0x1180
#define MX23_PAD_LCD_VSYNC__LCD_VSYNC			0x1190
#define MX23_PAD_PWM0__PWM0				0x11a0
#define MX23_PAD_PWM1__PWM1				0x11b0
#define MX23_PAD_PWM2__PWM2				0x11c0
#define MX23_PAD_PWM3__PWM3				0x11d0
#define MX23_PAD_PWM4__PWM4				0x11e0
#define MX23_PAD_SSP1_CMD__SSP1_CMD			0x2000
#define MX23_PAD_SSP1_DETECT__SSP1_DETECT		0x2010
#define MX23_PAD_SSP1_DATA0__SSP1_DATA0			0x2020
#define MX23_PAD_SSP1_DATA1__SSP1_DATA1			0x2030
#define MX23_PAD_SSP1_DATA2__SSP1_DATA2			0x2040
#define MX23_PAD_SSP1_DATA3__SSP1_DATA3			0x2050
#define MX23_PAD_SSP1_SCK__SSP1_SCK			0x2060
#define MX23_PAD_ROTARYA__ROTARYA			0x2070
#define MX23_PAD_ROTARYB__ROTARYB			0x2080
#define MX23_PAD_EMI_A00__EMI_A00			0x2090
#define MX23_PAD_EMI_A01__EMI_A01			0x20a0
#define MX23_PAD_EMI_A02__EMI_A02			0x20b0
#define MX23_PAD_EMI_A03__EMI_A03			0x20c0
#define MX23_PAD_EMI_A04__EMI_A04			0x20d0
#define MX23_PAD_EMI_A05__EMI_A05			0x20e0
#define MX23_PAD_EMI_A06__EMI_A06			0x20f0
#define MX23_PAD_EMI_A07__EMI_A07			0x2100
#define MX23_PAD_EMI_A08__EMI_A08			0x2110
#define MX23_PAD_EMI_A09__EMI_A09			0x2120
#define MX23_PAD_EMI_A10__EMI_A10			0x2130
#define MX23_PAD_EMI_A11__EMI_A11			0x2140
#define MX23_PAD_EMI_A12__EMI_A12			0x2150
#define MX23_PAD_EMI_BA0__EMI_BA0			0x2160
#define MX23_PAD_EMI_BA1__EMI_BA1			0x2170
#define MX23_PAD_EMI_CASN__EMI_CASN			0x2180
#define MX23_PAD_EMI_CE0N__EMI_CE0N			0x2190
#define MX23_PAD_EMI_CE1N__EMI_CE1N			0x21a0
#define MX23_PAD_GPMI_CE1N__GPMI_CE1N			0x21b0
#define MX23_PAD_GPMI_CE0N__GPMI_CE0N			0x21c0
#define MX23_PAD_EMI_CKE__EMI_CKE			0x21d0
#define MX23_PAD_EMI_RASN__EMI_RASN			0x21e0
#define MX23_PAD_EMI_WEN__EMI_WEN			0x21f0
#define MX23_PAD_EMI_D00__EMI_D00			0x3000
#define MX23_PAD_EMI_D01__EMI_D01			0x3010
#define MX23_PAD_EMI_D02__EMI_D02			0x3020
#define MX23_PAD_EMI_D03__EMI_D03			0x3030
#define MX23_PAD_EMI_D04__EMI_D04			0x3040
#define MX23_PAD_EMI_D05__EMI_D05			0x3050
#define MX23_PAD_EMI_D06__EMI_D06			0x3060
#define MX23_PAD_EMI_D07__EMI_D07			0x3070
#define MX23_PAD_EMI_D08__EMI_D08			0x3080
#define MX23_PAD_EMI_D09__EMI_D09			0x3090
#define MX23_PAD_EMI_D10__EMI_D10			0x30a0
#define MX23_PAD_EMI_D11__EMI_D11			0x30b0
#define MX23_PAD_EMI_D12__EMI_D12			0x30c0
#define MX23_PAD_EMI_D13__EMI_D13			0x30d0
#define MX23_PAD_EMI_D14__EMI_D14			0x30e0
#define MX23_PAD_EMI_D15__EMI_D15			0x30f0
#define MX23_PAD_EMI_DQM0__EMI_DQM0			0x3100
#define MX23_PAD_EMI_DQM1__EMI_DQM1			0x3110
#define MX23_PAD_EMI_DQS0__EMI_DQS0			0x3120
#define MX23_PAD_EMI_DQS1__EMI_DQS1			0x3130
#define MX23_PAD_EMI_CLK__EMI_CLK			0x3140
#define MX23_PAD_EMI_CLKN__EMI_CLKN			0x3150
#define MX23_PAD_GPMI_D00__LCD_D8			0x0001
#define MX23_PAD_GPMI_D01__LCD_D9			0x0011
#define MX23_PAD_GPMI_D02__LCD_D10			0x0021
#define MX23_PAD_GPMI_D03__LCD_D11			0x0031
#define MX23_PAD_GPMI_D04__LCD_D12			0x0041
#define MX23_PAD_GPMI_D05__LCD_D13			0x0051
#define MX23_PAD_GPMI_D06__LCD_D14			0x0061
#define MX23_PAD_GPMI_D07__LCD_D15			0x0071
#define MX23_PAD_GPMI_D08__LCD_D18			0x0081
#define MX23_PAD_GPMI_D09__LCD_D19			0x0091
#define MX23_PAD_GPMI_D10__LCD_D20			0x00a1
#define MX23_PAD_GPMI_D11__LCD_D21			0x00b1
#define MX23_PAD_GPMI_D12__LCD_D22			0x00c1
#define MX23_PAD_GPMI_D13__LCD_D23			0x00d1
#define MX23_PAD_GPMI_D14__AUART2_RX			0x00e1
#define MX23_PAD_GPMI_D15__AUART2_TX			0x00f1
#define MX23_PAD_GPMI_CLE__LCD_D16			0x0101
#define MX23_PAD_GPMI_ALE__LCD_D17			0x0111
#define MX23_PAD_GPMI_CE2N__ATA_A2			0x0121
#define MX23_PAD_AUART1_RTS__IR_CLK			0x01b1
#define MX23_PAD_AUART1_RX__IR_RX			0x01c1
#define MX23_PAD_AUART1_TX__IR_TX			0x01d1
#define MX23_PAD_I2C_SCL__GPMI_RDY2			0x01e1
#define MX23_PAD_I2C_SDA__GPMI_CE2N			0x01f1
#define MX23_PAD_LCD_D00__ETM_DA8			0x1001
#define MX23_PAD_LCD_D01__ETM_DA9			0x1011
#define MX23_PAD_LCD_D02__ETM_DA10			0x1021
#define MX23_PAD_LCD_D03__ETM_DA11			0x1031
#define MX23_PAD_LCD_D04__ETM_DA12			0x1041
#define MX23_PAD_LCD_D05__ETM_DA13			0x1051
#define MX23_PAD_LCD_D06__ETM_DA14			0x1061
#define MX23_PAD_LCD_D07__ETM_DA15			0x1071
#define MX23_PAD_LCD_D08__ETM_DA0			0x1081
#define MX23_PAD_LCD_D09__ETM_DA1			0x1091
#define MX23_PAD_LCD_D10__ETM_DA2			0x10a1
#define MX23_PAD_LCD_D11__ETM_DA3			0x10b1
#define MX23_PAD_LCD_D12__ETM_DA4			0x10c1
#define MX23_PAD_LCD_D13__ETM_DA5			0x10d1
#define MX23_PAD_LCD_D14__ETM_DA6			0x10e1
#define MX23_PAD_LCD_D15__ETM_DA7			0x10f1
#define MX23_PAD_LCD_RESET__ETM_TCTL			0x1121
#define MX23_PAD_LCD_RS__ETM_TCLK			0x1131
#define MX23_PAD_LCD_DOTCK__GPMI_RDY3			0x1161
#define MX23_PAD_LCD_ENABLE__I2C_SCL			0x1171
#define MX23_PAD_LCD_HSYNC__I2C_SDA			0x1181
#define MX23_PAD_LCD_VSYNC__LCD_BUSY			0x1191
#define MX23_PAD_PWM0__ROTARYA				0x11a1
#define MX23_PAD_PWM1__ROTARYB				0x11b1
#define MX23_PAD_PWM2__GPMI_RDY3			0x11c1
#define MX23_PAD_PWM3__ETM_TCTL				0x11d1
#define MX23_PAD_PWM4__ETM_TCLK				0x11e1
#define MX23_PAD_SSP1_DETECT__GPMI_CE3N			0x2011
#define MX23_PAD_SSP1_DATA1__I2C_SCL			0x2031
#define MX23_PAD_SSP1_DATA2__I2C_SDA			0x2041
#define MX23_PAD_ROTARYA__AUART2_RTS			0x2071
#define MX23_PAD_ROTARYB__AUART2_CTS			0x2081
#define MX23_PAD_GPMI_D00__SSP2_DATA0			0x0002
#define MX23_PAD_GPMI_D01__SSP2_DATA1			0x0012
#define MX23_PAD_GPMI_D02__SSP2_DATA2			0x0022
#define MX23_PAD_GPMI_D03__SSP2_DATA3			0x0032
#define MX23_PAD_GPMI_D04__SSP2_DATA4			0x0042
#define MX23_PAD_GPMI_D05__SSP2_DATA5			0x0052
#define MX23_PAD_GPMI_D06__SSP2_DATA6			0x0062
#define MX23_PAD_GPMI_D07__SSP2_DATA7			0x0072
#define MX23_PAD_GPMI_D08__SSP1_DATA4			0x0082
#define MX23_PAD_GPMI_D09__SSP1_DATA5			0x0092
#define MX23_PAD_GPMI_D10__SSP1_DATA6			0x00a2
#define MX23_PAD_GPMI_D11__SSP1_DATA7			0x00b2
#define MX23_PAD_GPMI_D15__GPMI_CE3N			0x00f2
#define MX23_PAD_GPMI_RDY0__SSP2_DETECT			0x0132
#define MX23_PAD_GPMI_RDY1__SSP2_CMD			0x0142
#define MX23_PAD_GPMI_WRN__SSP2_SCK			0x0182
#define MX23_PAD_AUART1_CTS__SSP1_DATA4			0x01a2
#define MX23_PAD_AUART1_RTS__SSP1_DATA5			0x01b2
#define MX23_PAD_AUART1_RX__SSP1_DATA6			0x01c2
#define MX23_PAD_AUART1_TX__SSP1_DATA7			0x01d2
#define MX23_PAD_I2C_SCL__AUART1_TX			0x01e2
#define MX23_PAD_I2C_SDA__AUART1_RX			0x01f2
#define MX23_PAD_LCD_D08__SAIF2_SDATA0			0x1082
#define MX23_PAD_LCD_D09__SAIF1_SDATA0			0x1092
#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK		0x10a2
#define MX23_PAD_LCD_D11__SAIF_LRCLK			0x10b2
#define MX23_PAD_LCD_D12__SAIF2_SDATA1			0x10c2
#define MX23_PAD_LCD_D13__SAIF2_SDATA2			0x10d2
#define MX23_PAD_LCD_D14__SAIF1_SDATA2			0x10e2
#define MX23_PAD_LCD_D15__SAIF1_SDATA1			0x10f2
#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK		0x1102
#define MX23_PAD_LCD_RESET__GPMI_CE3N			0x1122
#define MX23_PAD_PWM0__DUART_RX				0x11a2
#define MX23_PAD_PWM1__DUART_TX				0x11b2
#define MX23_PAD_PWM3__AUART1_CTS			0x11d2
#define MX23_PAD_PWM4__AUART1_RTS			0x11e2
#define MX23_PAD_SSP1_CMD__JTAG_TDO			0x2002
#define MX23_PAD_SSP1_DETECT__USB_OTG_ID		0x2012
#define MX23_PAD_SSP1_DATA0__JTAG_TDI			0x2022
#define MX23_PAD_SSP1_DATA1__JTAG_TCLK			0x2032
#define MX23_PAD_SSP1_DATA2__JTAG_RTCK			0x2042
#define MX23_PAD_SSP1_DATA3__JTAG_TMS			0x2052
#define MX23_PAD_SSP1_SCK__JTAG_TRST			0x2062
#define MX23_PAD_ROTARYA__SPDIF				0x2072
#define MX23_PAD_ROTARYB__GPMI_CE3N			0x2082
#define MX23_PAD_GPMI_D00__GPIO_0_0			0x0003
#define MX23_PAD_GPMI_D01__GPIO_0_1			0x0013
#define MX23_PAD_GPMI_D02__GPIO_0_2			0x0023
#define MX23_PAD_GPMI_D03__GPIO_0_3			0x0033
#define MX23_PAD_GPMI_D04__GPIO_0_4			0x0043
#define MX23_PAD_GPMI_D05__GPIO_0_5			0x0053
#define MX23_PAD_GPMI_D06__GPIO_0_6			0x0063
#define MX23_PAD_GPMI_D07__GPIO_0_7			0x0073
#define MX23_PAD_GPMI_D08__GPIO_0_8			0x0083
#define MX23_PAD_GPMI_D09__GPIO_0_9			0x0093
#define MX23_PAD_GPMI_D10__GPIO_0_10			0x00a3
#define MX23_PAD_GPMI_D11__GPIO_0_11			0x00b3
#define MX23_PAD_GPMI_D12__GPIO_0_12			0x00c3
#define MX23_PAD_GPMI_D13__GPIO_0_13			0x00d3
#define MX23_PAD_GPMI_D14__GPIO_0_14			0x00e3
#define MX23_PAD_GPMI_D15__GPIO_0_15			0x00f3
#define MX23_PAD_GPMI_CLE__GPIO_0_16			0x0103
#define MX23_PAD_GPMI_ALE__GPIO_0_17			0x0113
#define MX23_PAD_GPMI_CE2N__GPIO_0_18			0x0123
#define MX23_PAD_GPMI_RDY0__GPIO_0_19			0x0133
#define MX23_PAD_GPMI_RDY1__GPIO_0_20			0x0143
#define MX23_PAD_GPMI_RDY2__GPIO_0_21			0x0153
#define MX23_PAD_GPMI_RDY3__GPIO_0_22			0x0163
#define MX23_PAD_GPMI_WPN__GPIO_0_23			0x0173
#define MX23_PAD_GPMI_WRN__GPIO_0_24			0x0183
#define MX23_PAD_GPMI_RDN__GPIO_0_25			0x0193
#define MX23_PAD_AUART1_CTS__GPIO_0_26			0x01a3
#define MX23_PAD_AUART1_RTS__GPIO_0_27			0x01b3
#define MX23_PAD_AUART1_RX__GPIO_0_28			0x01c3
#define MX23_PAD_AUART1_TX__GPIO_0_29			0x01d3
#define MX23_PAD_I2C_SCL__GPIO_0_30			0x01e3
#define MX23_PAD_I2C_SDA__GPIO_0_31			0x01f3
#define MX23_PAD_LCD_D00__GPIO_1_0			0x1003
#define MX23_PAD_LCD_D01__GPIO_1_1			0x1013
#define MX23_PAD_LCD_D02__GPIO_1_2			0x1023
#define MX23_PAD_LCD_D03__GPIO_1_3			0x1033
#define MX23_PAD_LCD_D04__GPIO_1_4			0x1043
#define MX23_PAD_LCD_D05__GPIO_1_5			0x1053
#define MX23_PAD_LCD_D06__GPIO_1_6			0x1063
#define MX23_PAD_LCD_D07__GPIO_1_7			0x1073
#define MX23_PAD_LCD_D08__GPIO_1_8			0x1083
#define MX23_PAD_LCD_D09__GPIO_1_9			0x1093
#define MX23_PAD_LCD_D10__GPIO_1_10			0x10a3
#define MX23_PAD_LCD_D11__GPIO_1_11			0x10b3
#define MX23_PAD_LCD_D12__GPIO_1_12			0x10c3
#define MX23_PAD_LCD_D13__GPIO_1_13			0x10d3
#define MX23_PAD_LCD_D14__GPIO_1_14			0x10e3
#define MX23_PAD_LCD_D15__GPIO_1_15			0x10f3
#define MX23_PAD_LCD_D16__GPIO_1_16			0x1103
#define MX23_PAD_LCD_D17__GPIO_1_17			0x1113
#define MX23_PAD_LCD_RESET__GPIO_1_18			0x1123
#define MX23_PAD_LCD_RS__GPIO_1_19			0x1133
#define MX23_PAD_LCD_WR__GPIO_1_20			0x1143
#define MX23_PAD_LCD_CS__GPIO_1_21			0x1153
#define MX23_PAD_LCD_DOTCK__GPIO_1_22			0x1163
#define MX23_PAD_LCD_ENABLE__GPIO_1_23			0x1173
#define MX23_PAD_LCD_HSYNC__GPIO_1_24			0x1183
#define MX23_PAD_LCD_VSYNC__GPIO_1_25			0x1193
#define MX23_PAD_PWM0__GPIO_1_26			0x11a3
#define MX23_PAD_PWM1__GPIO_1_27			0x11b3
#define MX23_PAD_PWM2__GPIO_1_28			0x11c3
#define MX23_PAD_PWM3__GPIO_1_29			0x11d3
#define MX23_PAD_PWM4__GPIO_1_30			0x11e3
#define MX23_PAD_SSP1_CMD__GPIO_2_0			0x2003
#define MX23_PAD_SSP1_DETECT__GPIO_2_1			0x2013
#define MX23_PAD_SSP1_DATA0__GPIO_2_2			0x2023
#define MX23_PAD_SSP1_DATA1__GPIO_2_3			0x2033
#define MX23_PAD_SSP1_DATA2__GPIO_2_4			0x2043
#define MX23_PAD_SSP1_DATA3__GPIO_2_5			0x2053
#define MX23_PAD_SSP1_SCK__GPIO_2_6			0x2063
#define MX23_PAD_ROTARYA__GPIO_2_7			0x2073
#define MX23_PAD_ROTARYB__GPIO_2_8			0x2083
#define MX23_PAD_EMI_A00__GPIO_2_9			0x2093
#define MX23_PAD_EMI_A01__GPIO_2_10			0x20a3
#define MX23_PAD_EMI_A02__GPIO_2_11			0x20b3
#define MX23_PAD_EMI_A03__GPIO_2_12			0x20c3
#define MX23_PAD_EMI_A04__GPIO_2_13			0x20d3
#define MX23_PAD_EMI_A05__GPIO_2_14			0x20e3
#define MX23_PAD_EMI_A06__GPIO_2_15			0x20f3
#define MX23_PAD_EMI_A07__GPIO_2_16			0x2103
#define MX23_PAD_EMI_A08__GPIO_2_17			0x2113
#define MX23_PAD_EMI_A09__GPIO_2_18			0x2123
#define MX23_PAD_EMI_A10__GPIO_2_19			0x2133
#define MX23_PAD_EMI_A11__GPIO_2_20			0x2143
#define MX23_PAD_EMI_A12__GPIO_2_21			0x2153
#define MX23_PAD_EMI_BA0__GPIO_2_22			0x2163
#define MX23_PAD_EMI_BA1__GPIO_2_23			0x2173
#define MX23_PAD_EMI_CASN__GPIO_2_24			0x2183
#define MX23_PAD_EMI_CE0N__GPIO_2_25			0x2193
#define MX23_PAD_EMI_CE1N__GPIO_2_26			0x21a3
#define MX23_PAD_GPMI_CE1N__GPIO_2_27			0x21b3
#define MX23_PAD_GPMI_CE0N__GPIO_2_28			0x21c3
#define MX23_PAD_EMI_CKE__GPIO_2_29			0x21d3
#define MX23_PAD_EMI_RASN__GPIO_2_30			0x21e3
#define MX23_PAD_EMI_WEN__GPIO_2_31			0x21f3

#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */


code:
/*
 * Copyright (C) 2013-2016 Marek Vasut <marek.vasut@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of
 *     the License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx23.dtsi"

/ {
	model = "SanDisk Sansa Fuze+";
	compatible = "sandisk,sansa_fuze_plus", "fsl,imx23";

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0x04000000>;
	};

	apb@80000000 {
		apbh@80000000 {
			ssp0: spi@80010000 {
				compatible = "fsl,imx23-mmc";
				pinctrl-names = "default";
				pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
				bus-width = <4>;
				vmmc-supply = <&reg_vddio_sd0>;
				cd-inverted;
				status = "okay";
			};

			ssp1: spi@80034000 {
				compatible = "fsl,imx23-mmc";
				pinctrl-names = "default";
				pinctrl-0 = <&mmc1_8bit_pins_a>;
				bus-width = <8>;
				vmmc-supply = <&reg_vddio_sd1>;
				non-removable;
				status = "okay";
			};

			pinctrl@80018000 {
				pinctrl-names = "default";
				pinctrl-0 = <&hog_pins_a>;

				hog_pins_a: hog@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_GPMI_D08__GPIO_0_8
						MX23_PAD_PWM3__GPIO_1_29
						MX23_PAD_AUART1_RTS__GPIO_0_27
						MX23_PAD_AUART1_CTS__GPIO_0_26
						MX23_PAD_I2C_SCL__I2C_SCL
						MX23_PAD_I2C_SDA__I2C_SDA
						MX23_PAD_LCD_DOTCK__GPIO_1_22
						MX23_PAD_LCD_HSYNC__GPIO_1_24
						MX23_PAD_PWM3__GPIO_1_29
					>;
					fsl,drive-strength = <0>;
					fsl,voltage = <1>;
					fsl,pull-up = <0>;
				};
			};
		};

		apbx@80040000 {
			pwm: pwm@80064000 {
				pinctrl-names = "default";
				pinctrl-0 = <&pwm2_pins_a>;
				status = "okay";
			};

			duart: serial@80070000 {
				pinctrl-names = "default";
				pinctrl-0 = <&duart_pins_a>;
				status = "okay";
			};

			usbphy0: usbphy@8007c000 {
				status = "okay";
			};

			lradc@80050000 {
				status = "okay";
			};
		};
	};

	ahb@80080000 {
		usb0: usb@80080000 {
			dr_mode = "peripheral";
			status = "okay";
		};
	};

	reg_vddio_sd0: regulator-vddio-sd0 {
		compatible = "regulator-fixed";
		regulator-name = "vddio-sd0";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio0 8 0>;
	};

	reg_vddio_sd1: regulator-vddio-sd1 {
		compatible = "regulator-fixed";
		regulator-name = "vddio-sd1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio1 29 0>;
	};

	reg_vdd_touchpad: regulator-vdd-touchpad0 {
		compatible = "regulator-fixed";
		regulator-name = "vdd-touchpad0";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio0 26 GPIO_ACTIVE_LOW>;
		regulator-always-on;
	};

	reg_vdd_tuner: regulator-vdd-tuner0 {
		compatible = "regulator-fixed";
		regulator-name = "vdd-tuner0";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio0 29 GPIO_ACTIVE_LOW>;
		regulator-always-on;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm 2 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
	};

	i2c-0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "i2c-gpio";
		gpios = <
			&gpio1 24 0		/* SDA */
			&gpio1 22 0		/* SCL */
		>;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
	};

	i2c-1 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "i2c-gpio";
		gpios = <
			&gpio0 31 0		/* SDA */
			&gpio0 30 0		/* SCL */
		>;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */

		touch: touch@20 {
			compatible = "synaptics,synaptics_i2c";
			reg = <0x20>;
		};

		eeprom: eeprom@50 {
			compatible = "atmel,24c64";
			reg = <0x50>;
			pagesize = <32>;
		};
	};

};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 */

/dts-v1/;
#include "imx23.dtsi"

/ {
	model = "Freescale STMP378x Development Board";
	compatible = "fsl,stmp378x-devb", "fsl,imx23";

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0x04000000>;
	};

	apb@80000000 {
		apbh@80000000 {
			ssp0: spi@80010000 {
				compatible = "fsl,imx23-mmc";
				pinctrl-names = "default";
				pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
				bus-width = <4>;
				wp-gpios = <&gpio1 30 0>;
				vmmc-supply = <&reg_vddio_sd0>;
				status = "okay";
			};

			pinctrl@80018000 {
				pinctrl-names = "default";
				pinctrl-0 = <&hog_pins_a>;

				hog_pins_a: hog@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_PWM3__GPIO_1_29
						MX23_PAD_PWM4__GPIO_1_30
					>;
					fsl,drive-strength = <MXS_DRIVE_4mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};
			};
		};

		apbx@80040000 {
			auart0: serial@8006c000 {
				pinctrl-names = "default";
				pinctrl-0 = <&auart0_pins_a>;
				status = "okay";
			};

			duart: serial@80070000 {
				pinctrl-names = "default";
				pinctrl-0 = <&duart_pins_a>;
				status = "okay";
			};
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_vddio_sd0: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "vddio-sd0";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio1 29 0>;
		};
	};
};


code:
/*
 * Copyright (C) 2013-2016 Marek Vasut <marek.vasut@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of
 *     the License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 *
 */

/dts-v1/;
#include "imx23.dtsi"

/ {
	model = "Creative ZEN X-Fi3";
	compatible = "creative,x-fi3", "fsl,imx23";

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0x04000000>;
	};

	apb@80000000 {
		apbh@80000000 {
			ssp0: spi@80010000 {
				compatible = "fsl,imx23-mmc";
				pinctrl-names = "default";
				pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
				bus-width = <4>;
				vmmc-supply = <&reg_vddio_sd0>;
				cd-inverted;
				status = "okay";
			};

			ssp1: spi@80034000 {
				compatible = "fsl,imx23-mmc";
				pinctrl-names = "default";
				pinctrl-0 = <&mmc1_4bit_pins_a>;
				bus-width = <4>;
				non-removable;
				status = "okay";
			};

			pinctrl@80018000 {
				pinctrl-names = "default";
				pinctrl-0 = <&hog_pins_a>;

				hog_pins_a: hog@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_GPMI_D07__GPIO_0_7
					>;
					fsl,drive-strength = <0>;
					fsl,voltage = <1>;
					fsl,pull-up = <0>;
				};

				key_pins_a: keys@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_ROTARYA__GPIO_2_7
						MX23_PAD_ROTARYB__GPIO_2_8
					>;
					fsl,drive-strength = <0>;
					fsl,voltage = <1>;
					fsl,pull-up = <1>;
				};
			};
		};

		apbx@80040000 {
			i2c: i2c@80058000 {
				pinctrl-names = "default";
				pinctrl-0 = <&i2c_pins_a>;
				status = "okay";
			};

			pwm: pwm@80064000 {
				pinctrl-names = "default";
				pinctrl-0 = <&pwm2_pins_a>;
				status = "okay";
			};

			duart: serial@80070000 {
				pinctrl-names = "default";
				pinctrl-0 = <&duart_pins_a>;
				status = "okay";
			};

			auart1: serial@8006e000 {
				pinctrl-names = "default";
				pinctrl-0 = <&auart1_2pins_a>;
				status = "okay";
			};

			usbphy0: usbphy@8007c000 {
				status = "okay";
			};

			lradc@80050000 {
				status = "okay";
			};
		};
	};

	ahb@80080000 {
		usb0: usb@80080000 {
			dr_mode = "peripheral";
			status = "okay";
		};
	};

	reg_vddio_sd0: regulator-vddio-sd0 {
		compatible = "regulator-fixed";
		regulator-name = "vddio-sd0";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio0 7 0>;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm 2 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&key_pins_a>;

		key-voldown {
			label = "volume-down";
			linux,code = <114>;
			gpios = <&gpio2 7 0>;
			debounce-interval = <20>;
		};

		key-volup {
			label = "volume-up";
			linux,code = <115>;
			gpios = <&gpio2 8 0>;
			debounce-interval = <20>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.

#include "imx23-pinfunc.h"

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&icoll>;
	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 */
	chosen {};

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		serial0 = &auart0;
		serial1 = &auart1;
		spi0 = &ssp0;
		spi1 = &ssp1;
		usbphy0 = &usbphy0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,arm926ej-s";
			device_type = "cpu";
			reg = <0>;
		};
	};

	apb@80000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x80000000 0x80000>;
		ranges;

		apbh@80000000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x80000000 0x40000>;
			ranges;

			icoll: interrupt-controller@80000000 {
				compatible = "fsl,imx23-icoll", "fsl,icoll";
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x80000000 0x2000>;
			};

			dma_apbh: dma-apbh@80004000 {
				compatible = "fsl,imx23-dma-apbh";
				reg = <0x80004000 0x2000>;
				interrupts = <0 14 20 0
					      13 13 13 13>;
				interrupt-names = "empty", "ssp0", "ssp1", "empty",
						  "gpmi0", "gpmi1", "gpmi2", "gpmi3";
				#dma-cells = <1>;
				dma-channels = <8>;
				clocks = <&clks 15>;
			};

			ecc@80008000 {
				reg = <0x80008000 0x2000>;
				status = "disabled";
			};

			nand-controller@8000c000 {
				compatible = "fsl,imx23-gpmi-nand";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
				reg-names = "gpmi-nand", "bch";
				interrupts = <56>;
				interrupt-names = "bch";
				clocks = <&clks 34>;
				clock-names = "gpmi_io";
				dmas = <&dma_apbh 4>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			ssp0: spi@80010000 {
				reg = <0x80010000 0x2000>;
				interrupts = <15>;
				clocks = <&clks 33>;
				dmas = <&dma_apbh 1>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			etm@80014000 {
				reg = <0x80014000 0x2000>;
				status = "disabled";
			};

			pinctrl@80018000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx23-pinctrl", "simple-bus";
				reg = <0x80018000 0x2000>;

				gpio0: gpio@0 {
					compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
					reg = <0>;
					interrupts = <16>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio1: gpio@1 {
					compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
					reg = <1>;
					interrupts = <17>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				gpio2: gpio@2 {
					compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
					reg = <2>;
					interrupts = <18>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				duart_pins_a: duart@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_PWM0__DUART_RX
						MX23_PAD_PWM1__DUART_TX
					>;
					fsl,drive-strength = <MXS_DRIVE_4mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};

				auart0_pins_a: auart0@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_AUART1_RX__AUART1_RX
						MX23_PAD_AUART1_TX__AUART1_TX
						MX23_PAD_AUART1_CTS__AUART1_CTS
						MX23_PAD_AUART1_RTS__AUART1_RTS
					>;
					fsl,drive-strength = <MXS_DRIVE_4mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};

				auart0_2pins_a: auart0-2pins@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_I2C_SCL__AUART1_TX
						MX23_PAD_I2C_SDA__AUART1_RX
					>;
					fsl,drive-strength = <MXS_DRIVE_4mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};

				auart1_2pins_a: auart1-2pins@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_GPMI_D14__AUART2_RX
						MX23_PAD_GPMI_D15__AUART2_TX
					>;
					fsl,drive-strength = <MXS_DRIVE_4mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};

				gpmi_pins_a: gpmi-nand@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_GPMI_D00__GPMI_D00
						MX23_PAD_GPMI_D01__GPMI_D01
						MX23_PAD_GPMI_D02__GPMI_D02
						MX23_PAD_GPMI_D03__GPMI_D03
						MX23_PAD_GPMI_D04__GPMI_D04
						MX23_PAD_GPMI_D05__GPMI_D05
						MX23_PAD_GPMI_D06__GPMI_D06
						MX23_PAD_GPMI_D07__GPMI_D07
						MX23_PAD_GPMI_CLE__GPMI_CLE
						MX23_PAD_GPMI_ALE__GPMI_ALE
						MX23_PAD_GPMI_RDY0__GPMI_RDY0
						MX23_PAD_GPMI_RDY1__GPMI_RDY1
						MX23_PAD_GPMI_WPN__GPMI_WPN
						MX23_PAD_GPMI_WRN__GPMI_WRN
						MX23_PAD_GPMI_RDN__GPMI_RDN
						MX23_PAD_GPMI_CE1N__GPMI_CE1N
						MX23_PAD_GPMI_CE0N__GPMI_CE0N
					>;
					fsl,drive-strength = <MXS_DRIVE_4mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};

				gpmi_pins_fixup: gpmi-pins-fixup@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_GPMI_WPN__GPMI_WPN
						MX23_PAD_GPMI_WRN__GPMI_WRN
						MX23_PAD_GPMI_RDN__GPMI_RDN
					>;
					fsl,drive-strength = <MXS_DRIVE_12mA>;
				};

				mmc0_4bit_pins_a: mmc0-4bit@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_SSP1_DATA0__SSP1_DATA0
						MX23_PAD_SSP1_DATA1__SSP1_DATA1
						MX23_PAD_SSP1_DATA2__SSP1_DATA2
						MX23_PAD_SSP1_DATA3__SSP1_DATA3
						MX23_PAD_SSP1_CMD__SSP1_CMD
						MX23_PAD_SSP1_SCK__SSP1_SCK
					>;
					fsl,drive-strength = <MXS_DRIVE_8mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_ENABLE>;
				};

				mmc0_8bit_pins_a: mmc0-8bit@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_SSP1_DATA0__SSP1_DATA0
						MX23_PAD_SSP1_DATA1__SSP1_DATA1
						MX23_PAD_SSP1_DATA2__SSP1_DATA2
						MX23_PAD_SSP1_DATA3__SSP1_DATA3
						MX23_PAD_GPMI_D08__SSP1_DATA4
						MX23_PAD_GPMI_D09__SSP1_DATA5
						MX23_PAD_GPMI_D10__SSP1_DATA6
						MX23_PAD_GPMI_D11__SSP1_DATA7
						MX23_PAD_SSP1_CMD__SSP1_CMD
						MX23_PAD_SSP1_DETECT__SSP1_DETECT
						MX23_PAD_SSP1_SCK__SSP1_SCK
					>;
					fsl,drive-strength = <MXS_DRIVE_8mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_ENABLE>;
				};

				mmc0_pins_fixup: mmc0-pins-fixup@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_SSP1_DETECT__SSP1_DETECT
						MX23_PAD_SSP1_SCK__SSP1_SCK
					>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};

				mmc0_sck_cfg: mmc0-sck-cfg@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_SSP1_SCK__SSP1_SCK
					>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};

				mmc1_4bit_pins_a: mmc1-4bit@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_GPMI_D00__SSP2_DATA0
						MX23_PAD_GPMI_D01__SSP2_DATA1
						MX23_PAD_GPMI_D02__SSP2_DATA2
						MX23_PAD_GPMI_D03__SSP2_DATA3
						MX23_PAD_GPMI_RDY1__SSP2_CMD
						MX23_PAD_GPMI_WRN__SSP2_SCK
					>;
					fsl,drive-strength = <MXS_DRIVE_8mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_ENABLE>;
				};

				mmc1_8bit_pins_a: mmc1-8bit@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_GPMI_D00__SSP2_DATA0
						MX23_PAD_GPMI_D01__SSP2_DATA1
						MX23_PAD_GPMI_D02__SSP2_DATA2
						MX23_PAD_GPMI_D03__SSP2_DATA3
						MX23_PAD_GPMI_D04__SSP2_DATA4
						MX23_PAD_GPMI_D05__SSP2_DATA5
						MX23_PAD_GPMI_D06__SSP2_DATA6
						MX23_PAD_GPMI_D07__SSP2_DATA7
						MX23_PAD_GPMI_RDY1__SSP2_CMD
						MX23_PAD_GPMI_WRN__SSP2_SCK
					>;
					fsl,drive-strength = <MXS_DRIVE_8mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_ENABLE>;
				};

				pwm2_pins_a: pwm2@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_PWM2__PWM2
					>;
					fsl,drive-strength = <MXS_DRIVE_4mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};

				lcdif_24bit_pins_a: lcdif-24bit@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_LCD_D00__LCD_D00
						MX23_PAD_LCD_D01__LCD_D01
						MX23_PAD_LCD_D02__LCD_D02
						MX23_PAD_LCD_D03__LCD_D03
						MX23_PAD_LCD_D04__LCD_D04
						MX23_PAD_LCD_D05__LCD_D05
						MX23_PAD_LCD_D06__LCD_D06
						MX23_PAD_LCD_D07__LCD_D07
						MX23_PAD_LCD_D08__LCD_D08
						MX23_PAD_LCD_D09__LCD_D09
						MX23_PAD_LCD_D10__LCD_D10
						MX23_PAD_LCD_D11__LCD_D11
						MX23_PAD_LCD_D12__LCD_D12
						MX23_PAD_LCD_D13__LCD_D13
						MX23_PAD_LCD_D14__LCD_D14
						MX23_PAD_LCD_D15__LCD_D15
						MX23_PAD_LCD_D16__LCD_D16
						MX23_PAD_LCD_D17__LCD_D17
						MX23_PAD_GPMI_D08__LCD_D18
						MX23_PAD_GPMI_D09__LCD_D19
						MX23_PAD_GPMI_D10__LCD_D20
						MX23_PAD_GPMI_D11__LCD_D21
						MX23_PAD_GPMI_D12__LCD_D22
						MX23_PAD_GPMI_D13__LCD_D23
						MX23_PAD_LCD_DOTCK__LCD_DOTCK
						MX23_PAD_LCD_ENABLE__LCD_ENABLE
						MX23_PAD_LCD_HSYNC__LCD_HSYNC
						MX23_PAD_LCD_VSYNC__LCD_VSYNC
					>;
					fsl,drive-strength = <MXS_DRIVE_4mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};

				spi2_pins_a: spi2@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_GPMI_WRN__SSP2_SCK
						MX23_PAD_GPMI_RDY1__SSP2_CMD
						MX23_PAD_GPMI_D00__SSP2_DATA0
						MX23_PAD_GPMI_D03__SSP2_DATA3
					>;
					fsl,drive-strength = <MXS_DRIVE_8mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_ENABLE>;
				};

				i2c_pins_a: i2c@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_I2C_SCL__I2C_SCL
						MX23_PAD_I2C_SDA__I2C_SDA
					>;
					fsl,drive-strength = <MXS_DRIVE_8mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_ENABLE>;
				};

				i2c_pins_b: i2c@1 {
					reg = <1>;
					fsl,pinmux-ids = <
						MX23_PAD_LCD_ENABLE__I2C_SCL
						MX23_PAD_LCD_HSYNC__I2C_SDA
					>;
					fsl,drive-strength = <MXS_DRIVE_8mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_ENABLE>;
				};

				i2c_pins_c: i2c@2 {
					reg = <2>;
					fsl,pinmux-ids = <
						MX23_PAD_SSP1_DATA1__I2C_SCL
						MX23_PAD_SSP1_DATA2__I2C_SDA
					>;
					fsl,drive-strength = <MXS_DRIVE_8mA>;
					fsl,voltage = <MXS_VOLTAGE_HIGH>;
					fsl,pull-up = <MXS_PULL_ENABLE>;
				};
			};

			digctl@8001c000 {
				compatible = "fsl,imx23-digctl";
				reg = <0x8001c000 2000>;
				status = "disabled";
			};

			emi@80020000 {
				reg = <0x80020000 0x2000>;
				status = "disabled";
			};

			dma_apbx: dma-apbx@80024000 {
				compatible = "fsl,imx23-dma-apbx";
				reg = <0x80024000 0x2000>;
				interrupts = <7 5 9 26
					      19 0 25 23
					      60 58 9 0
					      0 0 0 0>;
				interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
						  "saif0", "empty", "auart0-rx", "auart0-tx",
						  "auart1-rx", "auart1-tx", "saif1", "empty",
						  "empty", "empty", "empty", "empty";
				#dma-cells = <1>;
				dma-channels = <16>;
				clocks = <&clks 16>;
			};

			dcp: crypto@80028000 {
				compatible = "fsl,imx23-dcp";
				reg = <0x80028000 0x2000>;
				interrupts = <53 54>;
				status = "okay";
			};

			pxp@8002a000 {
				reg = <0x8002a000 0x2000>;
				status = "disabled";
			};

			efuse@8002c000 {
				compatible = "fsl,imx23-ocotp", "fsl,ocotp";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x8002c000 0x2000>;
				clocks = <&clks 15>;
			};

			axi-ahb@8002e000 {
				reg = <0x8002e000 0x2000>;
				status = "disabled";
			};

			lcdif@80030000 {
				compatible = "fsl,imx23-lcdif";
				reg = <0x80030000 2000>;
				interrupts = <46 45>;
				clocks = <&clks 38>;
				status = "disabled";
			};

			ssp1: spi@80034000 {
				reg = <0x80034000 0x2000>;
				interrupts = <2>;
				clocks = <&clks 33>;
				dmas = <&dma_apbh 2>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			tvenc@80038000 {
				reg = <0x80038000 0x2000>;
				status = "disabled";
			};
		};

		apbx@80040000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x80040000 0x40000>;
			ranges;

			clks: clkctrl@80040000 {
				compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
				reg = <0x80040000 0x2000>;
				#clock-cells = <1>;
			};

			saif0: saif@80042000 {
				reg = <0x80042000 0x2000>;
				dmas = <&dma_apbx 4>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			power@80044000 {
				reg = <0x80044000 0x2000>;
				status = "disabled";
			};

			saif1: saif@80046000 {
				reg = <0x80046000 0x2000>;
				dmas = <&dma_apbx 10>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			audio-out@80048000 {
				reg = <0x80048000 0x2000>;
				dmas = <&dma_apbx 1>;
				dma-names = "tx";
				status = "disabled";
			};

			audio-in@8004c000 {
				reg = <0x8004c000 0x2000>;
				dmas = <&dma_apbx 0>;
				dma-names = "rx";
				status = "disabled";
			};

			lradc: lradc@80050000 {
				compatible = "fsl,imx23-lradc";
				reg = <0x80050000 0x2000>;
				interrupts = <36 37 38 39 40 41 42 43 44>;
				status = "disabled";
				clocks = <&clks 26>;
				#io-channel-cells = <1>;
			};

			spdif@80054000 {
				reg = <0x80054000 2000>;
				dmas = <&dma_apbx 2>;
				dma-names = "tx";
				status = "disabled";
			};

			i2c: i2c@80058000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx23-i2c";
				reg = <0x80058000 0x2000>;
				interrupts = <27>;
				clock-frequency = <100000>;
				dmas = <&dma_apbx 3>;
				dma-names = "rx-tx";
				status = "disabled";
			};

			rtc@8005c000 {
				compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
				reg = <0x8005c000 0x2000>;
				interrupts = <22>;
			};

			pwm: pwm@80064000 {
				compatible = "fsl,imx23-pwm";
				reg = <0x80064000 0x2000>;
				clocks = <&clks 30>;
				#pwm-cells = <2>;
				fsl,pwm-number = <5>;
				status = "disabled";
			};

			timrot@80068000 {
				compatible = "fsl,imx23-timrot", "fsl,timrot";
				reg = <0x80068000 0x2000>;
				interrupts = <28 29 30 31>;
				clocks = <&clks 28>;
			};

			auart0: serial@8006c000 {
				compatible = "fsl,imx23-auart";
				reg = <0x8006c000 0x2000>;
				interrupts = <24>;
				clocks = <&clks 32>;
				dmas = <&dma_apbx 6>, <&dma_apbx 7>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			auart1: serial@8006e000 {
				compatible = "fsl,imx23-auart";
				reg = <0x8006e000 0x2000>;
				interrupts = <59>;
				clocks = <&clks 32>;
				dmas = <&dma_apbx 8>, <&dma_apbx 9>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			duart: serial@80070000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x80070000 0x2000>;
				interrupts = <0>;
				clocks = <&clks 32>, <&clks 16>;
				clock-names = "uart", "apb_pclk";
				status = "disabled";
			};

			usbphy0: usbphy@8007c000 {
				compatible = "fsl,imx23-usbphy";
				reg = <0x8007c000 0x2000>;
				clocks = <&clks 41>;
				status = "disabled";
			};
		};
	};

	ahb@80080000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x80080000 0x80000>;
		ranges;

		usb0: usb@80080000 {
			compatible = "fsl,imx23-usb", "fsl,imx27-usb";
			reg = <0x80080000 0x40000>;
			interrupts = <11>;
			fsl,usbphy = <&usbphy0>;
			clocks = <&clks 40>;
			status = "disabled";
		};
	};

	iio-hwmon {
		compatible = "iio-hwmon";
		io-channels = <&lradc 8>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
 */

#include "imx25.dtsi"

/ {
	model = "Eukrea CPUIMX25";
	compatible = "eukrea,cpuimx25", "fsl,imx25";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x4000000>; /* 64M */
	};
};

&fec {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	status = "okay";
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pcf8563@51 {
		compatible = "nxp,pcf8563";
		reg = <0x51>;
	};
};

&iomuxc {
	imx25-eukrea-cpuimx25 {
		pinctrl_fec: fecgrp {
			fsl,pins = <
				MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
				MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
				MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
				MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
				MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
				MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
				MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
				MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
				MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
				MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
			>;
		};
	};
};

&nfc {
	nand-bus-width = <8>;
	nand-ecc-mode = "hw";
	nand-on-flash-bbt;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
 */

#include "imx25-eukrea-mbimxsd25-baseboard.dts"

/ {
	model = "Eukrea MBIMXSD25 with the CMO-QVGA Display";
	compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";

	cmo_qvga: display {
		model = "CMO-QVGA";
		bits-per-pixel = <16>;
		fsl,pcr = <0xcad08b80>;
		bus-width = <18>;
		display-timings {
			native-mode = <&qvga_timings>;
			qvga_timings: 320x240 {
				clock-frequency = <6500000>;
				hactive = <320>;
				vactive = <240>;
				hback-porch = <30>;
				hfront-porch = <38>;
				vback-porch = <20>;
				vfront-porch = <3>;
				hsync-len = <15>;
				vsync-len = <4>;
			};
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_lcd_3v3: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
			regulator-name = "lcd-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};
	};
};

&iomuxc {
	imx25-eukrea-mbimxsd25-baseboard-cmo-qvga {
		pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
			fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
		};
	};
};

&lcdc {
	display = <&cmo_qvga>;
	fsl,lpccr = <0x00a903ff>;
	lcd-supply = <&reg_lcd_3v3>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
 */

#include "imx25-eukrea-mbimxsd25-baseboard.dts"

/ {
	model = "Eukrea MBIMXSD25 with the DVI-SVGA Display";
	compatible = "eukrea,mbimxsd25-baseboard-dvi-svga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";

	dvi_svga: display {
		model = "DVI-SVGA";
		bits-per-pixel = <16>;
		fsl,pcr = <0xfa208b80>;
		bus-width = <18>;
		display-timings {
			native-mode = <&dvi_svga_timings>;
			dvi_svga_timings: 800x600 {
				clock-frequency = <40000000>;
				hactive = <800>;
				vactive = <600>;
				hback-porch = <75>;
				hfront-porch = <75>;
				vback-porch = <7>;
				vfront-porch = <75>;
				hsync-len = <7>;
				vsync-len = <7>;
			};
		};
	};
};

&lcdc {
	display = <&dvi_svga>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
 */

#include "imx25-eukrea-mbimxsd25-baseboard.dts"

/ {
	model = "Eukrea MBIMXSD25 with the DVI-VGA Display";
	compatible = "eukrea,mbimxsd25-baseboard-dvi-vga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";

	dvi_vga: display {
		model = "DVI-VGA";
		bits-per-pixel = <16>;
		fsl,pcr = <0xfa208b80>;
		bus-width = <18>;
		display-timings {
			native-mode = <&dvi_vga_timings>;
			dvi_vga_timings: 640x480 {
				clock-frequency = <31250000>;
				hactive = <640>;
				vactive = <480>;
				hback-porch = <100>;
				hfront-porch = <100>;
				vback-porch = <7>;
				vfront-porch = <100>;
				hsync-len = <7>;
				vsync-len = <7>;
			};
		};
	};
};

&lcdc {
	display = <&dvi_vga>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx25-eukrea-cpuimx25.dtsi"

/ {
	model = "Eukrea MBIMXSD25";
	compatible = "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpiokeys>;

		button {
			label = "BP1";
			gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_MISC>;
			wakeup-source;
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpioled>;

		led1 {
			label = "led1";
			gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
		};
	};

	sound {
		compatible = "eukrea,asoc-tlv320";
		eukrea,model = "imx25-eukrea-tlv320aic23";
		ssi-controller = <&ssi1>;
		fsl,mux-int-port = <1>;
		fsl,mux-ext-port = <5>;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	cd-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&i2c1 {
	tlv320aic23: codec@1a {
		compatible = "ti,tlv320aic23";
		reg = <0x1a>;
	};
};

&iomuxc {
	imx25-eukrea-mbimxsd25-baseboard {
		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX25_PAD_KPP_COL3__AUD5_TXFS		0xe0
				MX25_PAD_KPP_COL2__AUD5_TXC		0xe0
				MX25_PAD_KPP_COL1__AUD5_RXD		0xe0
				MX25_PAD_KPP_COL0__AUD5_TXD		0xe0
			>;
		};

		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				MX25_PAD_SD1_CMD__ESDHC1_CMD		0x400000c0
				MX25_PAD_SD1_CLK__ESDHC1_CLK		0x400000c0
				MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x400000c0
				MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x400000c0
				MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x400000c0
				MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x400000c0
			>;
		};

		pinctrl_gpiokeys: gpiokeysgrp {
			fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
		};

		pinctrl_gpioled: gpioledgrp {
			fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
		};

		pinctrl_lcdc: lcdcgrp {
			fsl,pins = <
				MX25_PAD_LD0__LD0			0x1
				MX25_PAD_LD1__LD1			0x1
				MX25_PAD_LD2__LD2			0x1
				MX25_PAD_LD3__LD3			0x1
				MX25_PAD_LD4__LD4			0x1
				MX25_PAD_LD5__LD5			0x1
				MX25_PAD_LD6__LD6			0x1
				MX25_PAD_LD7__LD7			0x1
				MX25_PAD_LD8__LD8			0x1
				MX25_PAD_LD9__LD9			0x1
				MX25_PAD_LD10__LD10			0x1
				MX25_PAD_LD11__LD11			0x1
				MX25_PAD_LD12__LD12			0x1
				MX25_PAD_LD13__LD13			0x1
				MX25_PAD_LD14__LD14			0x1
				MX25_PAD_LD15__LD15			0x1
				MX25_PAD_GPIO_E__LD16			0x1
				MX25_PAD_GPIO_F__LD17			0x1
				MX25_PAD_HSYNC__HSYNC			0x80000000
				MX25_PAD_VSYNC__VSYNC			0x80000000
				MX25_PAD_LSCLK__LSCLK			0x80000000
				MX25_PAD_OE_ACD__OE_ACD			0x80000000
				MX25_PAD_CONTRAST__CONTRAST		0x80000000
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX25_PAD_UART1_RTS__UART1_RTS		0xe0
				MX25_PAD_UART1_CTS__UART1_CTS		0xe0
				MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
				MX25_PAD_UART1_RXD__UART1_RXD		0xc0
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX25_PAD_UART2_RXD__UART2_RXD		0x80000000
				MX25_PAD_UART2_TXD__UART2_TXD		0x80000000
				MX25_PAD_UART2_RTS__UART2_RTS		0x80000000
				MX25_PAD_UART2_CTS__UART2_CTS		0x80000000
			>;
		};
	};
};

&ssi1 {
	codec-handle = <&tlv320aic23>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	uart-has-rtscts;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	uart-has-rtscts;
	status = "okay";
};

&usbhost1 {
	status = "okay";
};

&usbotg {
	external-vbus-divider;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Sascha Hauer, Pengutronix
 */

/dts-v1/;
#include "imx25.dtsi"

/ {
	model = "Ka-Ro TX25";
	compatible = "karo,imx25-tx25", "fsl,imx25";

	chosen {
		stdout-path = &uart1;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_fec_phy: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "fec-phy";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio4 9 0>;
			enable-active-high;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
	};
};

&iomuxc {
	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
			MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
			MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
			MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
		>;
	};

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX25_PAD_D11__GPIO_4_9		0x80000000 /* FEC PHY power on pin */
			MX25_PAD_D13__GPIO_4_7		0x80000000 /* FEC reset */
			MX25_PAD_FEC_MDC__FEC_MDC	0x80000000
			MX25_PAD_FEC_MDIO__FEC_MDIO	0x80000000
			MX25_PAD_FEC_TDATA0__FEC_TDATA0	0x80000000
			MX25_PAD_FEC_TDATA1__FEC_TDATA1	0x80000000
			MX25_PAD_FEC_TX_EN__FEC_TX_EN	0x80000000
			MX25_PAD_FEC_RDATA0__FEC_RDATA0	0x80000000
			MX25_PAD_FEC_RDATA1__FEC_RDATA1	0x80000000
			MX25_PAD_FEC_RX_DV__FEC_RX_DV	0x80000000
			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK	0x80000000
		>;
	};

	pinctrl_nfc: nfcgrp {
		fsl,pins = <
			MX25_PAD_NF_CE0__NF_CE0		0x80000000
			MX25_PAD_NFWE_B__NFWE_B		0x80000000
			MX25_PAD_NFRE_B__NFRE_B		0x80000000
			MX25_PAD_NFALE__NFALE		0x80000000
			MX25_PAD_NFCLE__NFCLE		0x80000000
			MX25_PAD_NFWP_B__NFWP_B		0x80000000
			MX25_PAD_NFRB__NFRB		0x80000000
			MX25_PAD_D7__D7			0x80000000
			MX25_PAD_D6__D6			0x80000000
			MX25_PAD_D5__D5			0x80000000
			MX25_PAD_D4__D4			0x80000000
			MX25_PAD_D3__D3			0x80000000
			MX25_PAD_D2__D2			0x80000000
			MX25_PAD_D1__D1			0x80000000
			MX25_PAD_D0__D0			0x80000000
		>;
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
	phy-mode = "rmii";
	phy-supply = <&reg_fec_phy>;
	status = "okay";
};

&nfc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nfc>;
	nand-on-flash-bbt;
	nand-ecc-mode = "hw";
	nand-bus-width = <8>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2013 Freescale Semiconductor, Inc.

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx25.dtsi"

/ {
	model = "Freescale i.MX25 Product Development Kit";
	compatible = "fsl,imx25-pdk", "fsl,imx25";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x4000000>;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_fec_3v3: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "fec-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio2 3 0>;
			enable-active-high;
		};

		reg_2p5v: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "2P5V";
			regulator-min-microvolt = <2500000>;
			regulator-max-microvolt = <2500000>;
		};

		reg_3p3v: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};

		reg_can_3v3: regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			regulator-name = "can-3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio4 6 0>;
		};
	};

	sound {
		compatible = "fsl,imx25-pdk-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx25-pdk-sgtl5000";
		ssi-controller = <&ssi1>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <1>;
		mux-ext-port = <4>;
	};

	wvga: display {
		model = "CLAA057VC01CW";
		bits-per-pixel = <16>;
		fsl,pcr = <0xfa208b80>;
		bus-width = <18>;
		display-timings {
			native-mode = <&wvga_timings>;
			wvga_timings: 640x480 {
				hactive = <640>;
				vactive = <480>;
				hback-porch = <45>;
				hfront-porch = <114>;
				hsync-len = <1>;
				vback-porch = <33>;
				vfront-porch = <11>;
				vsync-len = <1>;
				clock-frequency = <25200000>;
			};
		};
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can1>;
	xceiver-supply = <&reg_can_3v3>;
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&fec {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-supply = <&reg_fec_3v3>;
	phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks 129>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
	};
};

&iomuxc {
	imx25-pdk {
		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX25_PAD_RW__AUD4_TXFS			0xe0
				MX25_PAD_OE__AUD4_TXC			0xe0
				MX25_PAD_EB0__AUD4_TXD			0xe0
				MX25_PAD_EB1__AUD4_RXD			0xe0
			>;
		};

		pinctrl_can1: can1grp {
			fsl,pins = <
				MX25_PAD_GPIO_A__CAN1_TX		0x0
				MX25_PAD_GPIO_B__CAN1_RX		0x0
				MX25_PAD_D14__GPIO_4_6 			0x80000000
			>;
		};

		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				MX25_PAD_SD1_CMD__ESDHC1_CMD		0x80000000
				MX25_PAD_SD1_CLK__ESDHC1_CLK		0x80000000
				MX25_PAD_SD1_DATA0__ESDHC1_DAT0		0x80000000
				MX25_PAD_SD1_DATA1__ESDHC1_DAT1		0x80000000
				MX25_PAD_SD1_DATA2__ESDHC1_DAT2		0x80000000
				MX25_PAD_SD1_DATA3__ESDHC1_DAT3		0x80000000
				MX25_PAD_A14__GPIO_2_0			0x80000000
				MX25_PAD_A15__GPIO_2_1			0x80000000
			>;
		};

		pinctrl_fec: fecgrp {
			fsl,pins = <
				MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
				MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
				MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
				MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
				MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
				MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
				MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
				MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
				MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
				MX25_PAD_A17__GPIO_2_3			0x80000000
				MX25_PAD_D12__GPIO_4_8			0x80000000
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
				MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
			>;
		};

		pinctrl_kpp: kppgrp {
			fsl,pins = <
				MX25_PAD_KPP_ROW0__KPP_ROW0	0x80000000
				MX25_PAD_KPP_ROW1__KPP_ROW1	0x80000000
				MX25_PAD_KPP_ROW2__KPP_ROW2	0x80000000
				MX25_PAD_KPP_ROW3__KPP_ROW3	0x80000000
				MX25_PAD_KPP_COL0__KPP_COL0	0x80000000
				MX25_PAD_KPP_COL1__KPP_COL1	0x80000000
				MX25_PAD_KPP_COL2__KPP_COL2	0x80000000
				MX25_PAD_KPP_COL3__KPP_COL3	0x80000000
			>;
		};

		pinctrl_lcd: lcdgrp {
			fsl,pins = <
				MX25_PAD_LD0__LD0		0xe0
				MX25_PAD_LD1__LD1		0xe0
				MX25_PAD_LD2__LD2		0xe0
				MX25_PAD_LD3__LD3		0xe0
				MX25_PAD_LD4__LD4		0xe0
				MX25_PAD_LD5__LD5		0xe0
				MX25_PAD_LD6__LD6		0xe0
				MX25_PAD_LD7__LD7		0xe0
				MX25_PAD_LD8__LD8		0xe0
				MX25_PAD_LD9__LD9		0xe0
				MX25_PAD_LD10__LD10		0xe0
				MX25_PAD_LD11__LD11		0xe0
				MX25_PAD_LD12__LD12		0xe0
				MX25_PAD_LD13__LD13		0xe0
				MX25_PAD_LD14__LD14		0xe0
				MX25_PAD_LD15__LD15		0xe0
				MX25_PAD_GPIO_E__LD16		0xe0
				MX25_PAD_GPIO_F__LD17		0xe0
				MX25_PAD_HSYNC__HSYNC		0xe0
				MX25_PAD_VSYNC__VSYNC		0xe0
				MX25_PAD_LSCLK__LSCLK		0xe0
				MX25_PAD_OE_ACD__OE_ACD		0xe0
				MX25_PAD_CONTRAST__CONTRAST	0xe0
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX25_PAD_UART1_RTS__UART1_RTS		0xe0
				MX25_PAD_UART1_CTS__UART1_CTS		0xe0
				MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
				MX25_PAD_UART1_RXD__UART1_RXD		0xc0
			>;
		};
	};
};

&lcdc {
	display = <&wvga>;
	fsl,lpccr = <0x00a903ff>;
	fsl,lscr1 = <0x00120300>;
	fsl,dmacr = <0x00020010>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd>;
	status = "okay";
};

&nfc {
	nand-on-flash-bbt;
	status = "okay";
};

&kpp {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_kpp>;
	linux,keymap = <
			MATRIX_KEY(0x0, 0x0, KEY_UP)
			MATRIX_KEY(0x0, 0x1, KEY_DOWN)
			MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN)
			MATRIX_KEY(0x0, 0x3, KEY_HOME)
			MATRIX_KEY(0x1, 0x0, KEY_RIGHT)
			MATRIX_KEY(0x1, 0x1, KEY_LEFT)
			MATRIX_KEY(0x1, 0x2, KEY_ENTER)
			MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP)
			MATRIX_KEY(0x2, 0x0, KEY_F6)
			MATRIX_KEY(0x2, 0x1, KEY_F8)
			MATRIX_KEY(0x2, 0x2, KEY_F9)
			MATRIX_KEY(0x2, 0x3, KEY_F10)
			MATRIX_KEY(0x3, 0x0, KEY_F1)
			MATRIX_KEY(0x3, 0x1, KEY_F2)
			MATRIX_KEY(0x3, 0x2, KEY_F3)
			MATRIX_KEY(0x3, 0x2, KEY_POWER)
	>;
	status = "okay";
};

&ssi1 {
	status = "okay";
};

&tsc {
	status = "okay";
};

&tscadc {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	uart-has-rtscts;
	status = "okay";
};

&usbhost1 {
	status = "okay";
};

&usbotg {
	external-vbus-divider;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>

#include <dt-bindings/gpio/gpio.h>
#include "imx25-pinfunc.h"

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 */
	chosen {};

	aliases {
		ethernet0 = &fec;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		mmc0 = &esdhc1;
		mmc1 = &esdhc2;
		pwm0 = &pwm1;
		pwm1 = &pwm2;
		pwm2 = &pwm3;
		pwm3 = &pwm4;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		spi0 = &spi1;
		spi1 = &spi2;
		spi2 = &spi3;
		usb0 = &usbotg;
		usb1 = &usbhost1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,arm926ej-s";
			device_type = "cpu";
			reg = <0>;
		};
	};

	asic: asic-interrupt-controller@68000000 {
		compatible = "fsl,imx25-asic", "fsl,avic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x68000000 0x8000000>;
	};

	clocks {
		osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&asic>;
		ranges;

		bus@43f00000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x43f00000 0x100000>;
			ranges;

			aips1: bridge@43f00000 {
				compatible = "fsl,imx25-aips";
				reg = <0x43f00000 0x4000>;
			};

			i2c1: i2c@43f80000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
				reg = <0x43f80000 0x4000>;
				clocks = <&clks 48>;
				clock-names = "";
				interrupts = <3>;
				status = "disabled";
			};

			i2c3: i2c@43f84000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
				reg = <0x43f84000 0x4000>;
				clocks = <&clks 48>;
				clock-names = "";
				interrupts = <10>;
				status = "disabled";
			};

			can1: can@43f88000 {
				compatible = "fsl,imx25-flexcan";
				reg = <0x43f88000 0x4000>;
				interrupts = <43>;
				clocks = <&clks 75>, <&clks 75>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			can2: can@43f8c000 {
				compatible = "fsl,imx25-flexcan";
				reg = <0x43f8c000 0x4000>;
				interrupts = <44>;
				clocks = <&clks 76>, <&clks 76>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart1: serial@43f90000 {
				compatible = "fsl,imx25-uart", "fsl,imx21-uart";
				reg = <0x43f90000 0x4000>;
				interrupts = <45>;
				clocks = <&clks 120>, <&clks 57>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@43f94000 {
				compatible = "fsl,imx25-uart", "fsl,imx21-uart";
				reg = <0x43f94000 0x4000>;
				interrupts = <32>;
				clocks = <&clks 121>, <&clks 57>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@43f98000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
				reg = <0x43f98000 0x4000>;
				clocks = <&clks 48>;
				clock-names = "";
				interrupts = <4>;
				status = "disabled";
			};

			owire@43f9c000 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x43f9c000 0x4000>;
				clocks = <&clks 51>;
				clock-names = "";
				interrupts = <2>;
				status = "disabled";
			};

			spi1: spi@43fa4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
				reg = <0x43fa4000 0x4000>;
				clocks = <&clks 78>, <&clks 78>;
				clock-names = "ipg", "per";
				interrupts = <14>;
				status = "disabled";
			};

			kpp: kpp@43fa8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx25-kpp", "fsl,imx21-kpp";
				reg = <0x43fa8000 0x4000>;
				clocks = <&clks 102>;
				clock-names = "";
				interrupts = <24>;
				status = "disabled";
			};

			iomuxc: iomuxc@43fac000 {
				compatible = "fsl,imx25-iomuxc";
				reg = <0x43fac000 0x4000>;
			};

			audmux: audmux@43fb0000 {
				compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
				reg = <0x43fb0000 0x4000>;
				status = "disabled";
			};
		};

		spba-bus@50000000 {
			compatible = "fsl,spba-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x50000000 0x40000>;
			ranges;

			spi3: spi@50004000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
				reg = <0x50004000 0x4000>;
				interrupts = <0>;
				clocks = <&clks 80>, <&clks 80>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart4: serial@50008000 {
				compatible = "fsl,imx25-uart", "fsl,imx21-uart";
				reg = <0x50008000 0x4000>;
				interrupts = <5>;
				clocks = <&clks 123>, <&clks 57>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart3: serial@5000c000 {
				compatible = "fsl,imx25-uart", "fsl,imx21-uart";
				reg = <0x5000c000 0x4000>;
				interrupts = <18>;
				clocks = <&clks 122>, <&clks 57>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			spi2: spi@50010000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
				reg = <0x50010000 0x4000>;
				clocks = <&clks 79>, <&clks 79>;
				clock-names = "ipg", "per";
				interrupts = <13>;
				status = "disabled";
			};

			ssi2: ssi@50014000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
				reg = <0x50014000 0x4000>;
				interrupts = <11>;
				clocks = <&clks 118>;
				clock-names = "ipg";
				dmas = <&sdma 24 1 0>,
				       <&sdma 25 1 0>;
				dma-names = "rx", "tx";
				fsl,fifo-depth = <15>;
				status = "disabled";
			};

			esai@50018000 {
				reg = <0x50018000 0x4000>;
				interrupts = <7>;
			};

			uart5: serial@5002c000 {
				compatible = "fsl,imx25-uart", "fsl,imx21-uart";
				reg = <0x5002c000 0x4000>;
				interrupts = <40>;
				clocks = <&clks 124>, <&clks 57>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			tscadc: tscadc@50030000 {
				compatible = "fsl,imx25-tsadc";
				reg = <0x50030000 0xc>;
				interrupts = <46>;
				clocks = <&clks 119>;
				clock-names = "ipg";
				interrupt-controller;
				#interrupt-cells = <1>;
				#address-cells = <1>;
				#size-cells = <1>;
				status = "disabled";
				ranges;

				adc: adc@50030800 {
					compatible = "fsl,imx25-gcq";
					reg = <0x50030800 0x60>;
					interrupt-parent = <&tscadc>;
					interrupts = <1>;
					#address-cells = <1>;
					#size-cells = <0>;
					status = "disabled";
				};

				tsc: tcq@50030400 {
					compatible = "fsl,imx25-tcq";
					reg = <0x50030400 0x60>;
					interrupt-parent = <&tscadc>;
					interrupts = <0>;
					fsl,wires = <4>;
					status = "disabled";
				};
			};

			ssi1: ssi@50034000 {
				#sound-dai-cells = <0>;
				compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
				reg = <0x50034000 0x4000>;
				interrupts = <12>;
				clocks = <&clks 117>;
				clock-names = "ipg";
				dmas = <&sdma 28 1 0>,
				       <&sdma 29 1 0>;
				dma-names = "rx", "tx";
				fsl,fifo-depth = <15>;
				status = "disabled";
			};

			fec: ethernet@50038000 {
				compatible = "fsl,imx25-fec";
				reg = <0x50038000 0x4000>;
				interrupts = <57>;
				clocks = <&clks 88>, <&clks 65>;
				clock-names = "ipg", "ahb";
				status = "disabled";
			};
		};

		bus@53f00000 { /* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x53f00000 0x100000>;
			ranges;

			aips2: bridge@53f00000 {
				compatible = "fsl,imx25-aips";
				reg = <0x53f00000 0x4000>;
			};

			clks: ccm@53f80000 {
				compatible = "fsl,imx25-ccm";
				reg = <0x53f80000 0x4000>;
				interrupts = <31>;
				#clock-cells = <1>;
			};

			gpt4: timer@53f84000 {
				compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
				reg = <0x53f84000 0x4000>;
				clocks = <&clks 95>, <&clks 47>;
				clock-names = "ipg", "per";
				interrupts = <1>;
			};

			gpt3: timer@53f88000 {
				compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
				reg = <0x53f88000 0x4000>;
				clocks = <&clks 94>, <&clks 47>;
				clock-names = "ipg", "per";
				interrupts = <29>;
			};

			gpt2: timer@53f8c000 {
				compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
				reg = <0x53f8c000 0x4000>;
				clocks = <&clks 93>, <&clks 47>;
				clock-names = "ipg", "per";
				interrupts = <53>;
			};

			gpt1: timer@53f90000 {
				compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
				reg = <0x53f90000 0x4000>;
				clocks = <&clks 92>, <&clks 47>;
				clock-names = "ipg", "per";
				interrupts = <54>;
			};

			epit1: timer@53f94000 {
				compatible = "fsl,imx25-epit";
				reg = <0x53f94000 0x4000>;
				clocks = <&clks 83>, <&clks 43>;
				clock-names = "ipg", "per";
				interrupts = <28>;
			};

			epit2: timer@53f98000 {
				compatible = "fsl,imx25-epit";
				reg = <0x53f98000 0x4000>;
				clocks = <&clks 84>, <&clks 43>;
				clock-names = "ipg", "per";
				interrupts = <27>;
			};

			gpio4: gpio@53f9c000 {
				compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
				reg = <0x53f9c000 0x4000>;
				interrupts = <23>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			pwm2: pwm@53fa0000 {
				compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
				#pwm-cells = <3>;
				reg = <0x53fa0000 0x4000>;
				clocks = <&clks 106>, <&clks 52>;
				clock-names = "ipg", "per";
				interrupts = <36>;
			};

			gpio3: gpio@53fa4000 {
				compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
				reg = <0x53fa4000 0x4000>;
				interrupts = <16>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			pwm3: pwm@53fa8000 {
				compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
				#pwm-cells = <3>;
				reg = <0x53fa8000 0x4000>;
				clocks = <&clks 107>, <&clks 52>;
				clock-names = "ipg", "per";
				interrupts = <41>;
			};

			scc: crypto@53fac000 {
				compatible = "fsl,imx25-scc";
				reg = <0x53fac000 0x4000>;
				clocks = <&clks 111>;
				clock-names = "ipg";
				interrupts = <49>, <50>;
				interrupt-names = "scm", "smn";
			};

			rngb: rngb@53fb0000 {
				compatible = "fsl,imx25-rngb";
				reg = <0x53fb0000 0x4000>;
				clocks = <&clks 109>;
				interrupts = <22>;
			};

			esdhc1: mmc@53fb4000 {
				compatible = "fsl,imx25-esdhc";
				reg = <0x53fb4000 0x4000>;
				interrupts = <9>;
				clocks = <&clks 86>, <&clks 63>, <&clks 45>;
				clock-names = "ipg", "ahb", "per";
				status = "disabled";
			};

			esdhc2: mmc@53fb8000 {
				compatible = "fsl,imx25-esdhc";
				reg = <0x53fb8000 0x4000>;
				interrupts = <8>;
				clocks = <&clks 87>, <&clks 64>, <&clks 46>;
				clock-names = "ipg", "ahb", "per";
				status = "disabled";
			};

			lcdc: lcdc@53fbc000 {
				compatible = "fsl,imx25-fb", "fsl,imx21-fb";
				reg = <0x53fbc000 0x4000>;
				interrupts = <39>;
				clocks = <&clks 103>, <&clks 66>, <&clks 49>;
				clock-names = "ipg", "ahb", "per";
				status = "disabled";
			};

			slcdc@53fc0000 {
				reg = <0x53fc0000 0x4000>;
				interrupts = <38>;
				status = "disabled";
			};

			pwm4: pwm@53fc8000 {
				compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
				#pwm-cells = <3>;
				reg = <0x53fc8000 0x4000>;
				clocks = <&clks 108>, <&clks 52>;
				clock-names = "ipg", "per";
				interrupts = <42>;
			};

			gpio1: gpio@53fcc000 {
				compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
				reg = <0x53fcc000 0x4000>;
				interrupts = <52>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@53fd0000 {
				compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
				reg = <0x53fd0000 0x4000>;
				interrupts = <51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			sdma: dma-controller@53fd4000 {
				compatible = "fsl,imx25-sdma";
				reg = <0x53fd4000 0x4000>;
				clocks = <&clks 112>, <&clks 68>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				interrupts = <34>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
			};

			watchdog@53fdc000 {
				compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
				reg = <0x53fdc000 0x4000>;
				clocks = <&clks 126>;
				clock-names = "";
				interrupts = <55>;
			};

			pwm1: pwm@53fe0000 {
				compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
				#pwm-cells = <3>;
				reg = <0x53fe0000 0x4000>;
				clocks = <&clks 105>, <&clks 52>;
				clock-names = "ipg", "per";
				interrupts = <26>;
			};

			iim: efuse@53ff0000 {
				compatible = "fsl,imx25-iim", "fsl,imx27-iim";
				reg = <0x53ff0000 0x4000>;
				interrupts = <19>;
				clocks = <&clks 99>;
			};

			usbotg: usb@53ff4000 {
				compatible = "fsl,imx25-usb", "fsl,imx27-usb";
				reg = <0x53ff4000 0x0200>;
				interrupts = <37>;
				clocks = <&clks 9>, <&clks 70>, <&clks 8>;
				clock-names = "ipg", "ahb", "per";
				fsl,usbmisc = <&usbmisc 0>;
				fsl,usbphy = <&usbphy0>;
				phy_type = "utmi";
				dr_mode = "otg";
				status = "disabled";
			};

			usbhost1: usb@53ff4400 {
				compatible = "fsl,imx25-usb", "fsl,imx27-usb";
				reg = <0x53ff4400 0x0200>;
				interrupts = <35>;
				clocks = <&clks 9>, <&clks 70>, <&clks 8>;
				clock-names = "ipg", "ahb", "per";
				fsl,usbmisc = <&usbmisc 1>;
				fsl,usbphy = <&usbphy1>;
				maximum-speed = "full-speed";
				phy_type = "serial";
				dr_mode = "host";
				status = "disabled";
			};

			usbmisc: usbmisc@53ff4600 {
				#index-cells = <1>;
				compatible = "fsl,imx25-usbmisc";
				reg = <0x53ff4600 0x00f>;
			};

			dryice@53ffc000 {
				compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
				reg = <0x53ffc000 0x4000>;
				clocks = <&clks 81>;
				clock-names = "ipg";
				interrupts = <25 56>;
			};
		};

		iram: sram@78000000 {
			compatible = "mmio-sram";
			reg = <0x78000000 0x20000>;
		};

		emi@80000000 {
			compatible = "fsl,emi-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x80000000 0x3b002000>;
			ranges;

			nfc: nand@bb000000 {
				#address-cells = <1>;
				#size-cells = <1>;

				compatible = "fsl,imx25-nand";
				reg = <0xbb000000 0x2000>;
				clocks = <&clks 50>;
				clock-names = "";
				interrupts = <33>;
				status = "disabled";
			};
		};
	};

	usbphy {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		usbphy0: usb-phy@0 {
			reg = <0>;
			compatible = "usb-nop-xceiv";
			#phy-cells = <0>;
		};

		usbphy1: usb-phy@1 {
			reg = <1>;
			compatible = "usb-nop-xceiv";
			#phy-cells = <0>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Philippe Reynes <tremyfr@yahoo.fr>
 * Copyright 2012 Armadeus Systems <support@armadeus.com>
 *
 * Based on code which is: Copyright 2012 Sascha Hauer, Pengutronix
 */

/dts-v1/;
#include "imx27.dtsi"

/ {
	model = "Armadeus Systems APF27 module";
	compatible = "armadeus,imx27-apf27", "fsl,imx27";

	memory@a0000000 {
		device_type = "memory";
		reg = <0xa0000000 0x04000000>;
	};
};

&clk_osc26m {
	clock-frequency = <0>;
};

&iomuxc {
	imx27-apf27 {
		pinctrl_fec1: fec1grp {
			fsl,pins = <
				MX27_PAD_SD3_CMD__FEC_TXD0 0x0
				MX27_PAD_SD3_CLK__FEC_TXD1 0x0
				MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
				MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
				MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
				MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
				MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
				MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
				MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
				MX27_PAD_ATA_DATA7__FEC_MDC 0x0
				MX27_PAD_ATA_DATA8__FEC_CRS 0x0
				MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
				MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
				MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
				MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
				MX27_PAD_ATA_DATA13__FEC_COL 0x0
				MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
				MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX27_PAD_UART1_TXD__UART1_TXD 0x0
				MX27_PAD_UART1_RXD__UART1_RXD 0x0
			>;
		};
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";
};

&nfc {
	status = "okay";
	nand-bus-width = <16>;
	nand-ecc-mode = "hw";
	nand-on-flash-bbt;

	partition@0 {
		label = "u-boot";
		reg = <0x0 0x100000>;
	};

	partition@100000 {
		label = "env";
		reg = <0x100000 0x80000>;
	};

	partition@180000 {
		label = "env2";
		reg = <0x180000 0x80000>;
	};

	partition@200000 {
		label = "firmware";
		reg = <0x200000 0x80000>;
	};

	partition@280000 {
		label = "dtb";
		reg = <0x280000 0x80000>;
	};

	partition@300000 {
		label = "kernel";
		reg = <0x300000 0x500000>;
	};

	partition@800000 {
		label = "rootfs";
		reg = <0x800000 0xf800000>;
	};
};