code:
# SPDX-License-Identifier: GPL-2.0-or-later
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2500-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED AST2500 Pin Controller

maintainers:
  - Andrew Jeffery <andrew@aj.id.au>

description: |+
  The pin controller node should be the child of a syscon node with the
  required property:

  - compatible: 	Should be one of the following:
  			"aspeed,ast2500-scu", "syscon", "simple-mfd"
  			"aspeed,g5-scu", "syscon", "simple-mfd"

  Refer to the bindings described in
  Documentation/devicetree/bindings/mfd/syscon.yaml

properties:
  compatible:
    const: aspeed,ast2500-pinctrl
  reg:
    maxItems: 2

  aspeed,external-nodes:
    minItems: 2
    maxItems: 2
    items:
      maxItems: 1
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: |
      A cell of phandles to external controller nodes:
      0: compatible with "aspeed,ast2500-gfx", "syscon"
      1: compatible with "aspeed,ast2500-lhc", "syscon"

patternProperties:
  '^.*$':
    if:
      type: object
    then:
      patternProperties:
        "^function|groups$":
          $ref: "/schemas/types.yaml#/definitions/string"
          enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
                  ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
                  ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2,
                  GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5,
                  I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC,
                  LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK,
                  MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
                  NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2,
                  NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0,
                  PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
                  RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13,
                  SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1,
                  SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
                  SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG,
                  SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3,
                  TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6,
                  USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS,
                  VGAVS, VPI24, VPO, WDTRST1, WDTRST2]

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - aspeed,external-nodes

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/aspeed-clock.h>
    scu@1e6e2000 {
        compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
        reg = <0x1e6e2000 0x1a8>;
        #clock-cells = <1>;
        #reset-cells = <1>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x1e6e2000 0x1000>;

        pinctrl: pinctrl {
            compatible = "aspeed,ast2500-pinctrl";
            aspeed,external-nodes = <&gfx>, <&lhc>;

            pinctrl_i2c3_default: i2c3_default {
                function = "I2C3";
                groups = "I2C3";
            };

            pinctrl_gpioh0_unbiased_default: gpioh0 {
                pins = "A18";
                bias-disable;
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2600-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED AST2600 Pin Controller

maintainers:
  - Andrew Jeffery <andrew@aj.id.au>

description: |+
  The pin controller node should be the child of a syscon node with the
  required property:

  - compatible: Should be one of the following:
                "aspeed,ast2600-scu", "syscon", "simple-mfd"

  Refer to the bindings described in
  Documentation/devicetree/bindings/mfd/syscon.yaml

properties:
  compatible:
    const: aspeed,ast2600-pinctrl

patternProperties:
  '^.*$':
    if:
      type: object
    then:
      properties:
        function:
          $ref: "/schemas/types.yaml#/definitions/string"
          enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
                  ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT,
                  FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
                  GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5,
                  GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16,
                  I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5,
                  I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
                  MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4,
                  NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2,
                  NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4,
                  NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11,
                  PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8,
                  PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
                  RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
                  SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8,
                  SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
                  SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
                  SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14,
                  TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0,
                  THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12,
                  UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
                  USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ]

        groups:
          $ref: "/schemas/types.yaml#/definitions/string"
          enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
                  ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4,
                  EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP,
                  GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
                  GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10,
                  I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5,
                  I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
                  LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3,
                  MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4,
                  NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
                  NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
                  OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0,
                  PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2,
                  PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
                  QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
                  RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1,
                  SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0,
                  SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6,
                  SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2,
                  SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
                  SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
                  TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6,
                  TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3,
                  TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
                  UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
                  WDTRST3, WDTRST4]

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible

additionalProperties: false

examples:
  - |
    syscon: scu@1e6e2000 {
        compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
        reg = <0x1e6e2000 0xf6c>;
        #clock-cells = <1>;
        #reset-cells = <1>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x1e6e2000 0x1000>;

        pinctrl: pinctrl {
            compatible = "aspeed,ast2600-pinctrl";

            pinctrl_pwm10g1_default: pwm10g1_default {
                function = "PWM10";
                groups = "PWM10G1";
            };

            pinctrl_gpioh0_unbiased_default: gpioh0 {
                pins = "A18";
                bias-disable;
            };
        };
    };

repo_name: angery/linux


code:
* Atmel AT91 Pinmux Controller

The AT91 Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to
8 muxing options (called periph modes). Since different modules require
different PAD settings (like pull up, keeper, etc) the controller controls
also the PAD settings parameters.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

Atmel AT91 pin configuration node is a node of a group of pins which can be
used for a specific device or function. This node represents both mux and config
of the pins in that group. The 'pins' selects the function mode(also named pin
mode) this pin can work on and the 'config' configures various pad settings
such as pull-up, multi drive, etc.

Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
		or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
  configured in this periph mode. All the periph and bank need to be describe.

How to create such array:

Each column will represent the possible peripheral of the pinctrl
Each line will represent a pio bank

Take an example on the 9260
Peripheral: 2 ( A and B)
Bank: 3 (A, B and C)
=>

  /*    A         B     */
  0xffffffff 0xffc00c3b  /* pioA */
  0xffffffff 0x7fff3ccf  /* pioB */
  0xffffffff 0x007fffff  /* pioC */

For each peripheral/bank we will describe in a u32 if a pin can be
configured in it by putting 1 to the pin bit (1 << pin)

Let's take the pioA on peripheral B
From the datasheet Table 10-2.
Peripheral B
PA0	MCDB0
PA1	MCCDB
PA2
PA3	MCDB3
PA4	MCDB2
PA5	MCDB1
PA6
PA7
PA8
PA9
PA10	ETX2
PA11	ETX3
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22	ETXER
PA23	ETX2
PA24	ETX3
PA25	ERX2
PA26	ERX3
PA27	ERXCK
PA28	ECRS
PA29	ECOL
PA30	RXD4
PA31	TXD4

=> 0xffc00c3b

Required properties for pin configuration node:
- atmel,pins: 4 integers array, represents a group of pins mux and config
  setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
  The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
  PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...

Bits used for CONFIG:
PULL_UP		(1 << 0): indicate this pin needs a pull up.
MULTIDRIVE	(1 << 1): indicate this pin needs to be configured as multi-drive.
			Multi-drive is equivalent to open-drain type output.
DEGLITCH	(1 << 2): indicate this pin needs deglitch.
PULL_DOWN	(1 << 3): indicate this pin needs a pull down.
DIS_SCHMIT	(1 << 4): indicate this pin needs to the disable schmitt trigger.
DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
			following values:
				00 - No change (reset state value kept)
				01 - Low
				10 - Medium
				11 - High
OUTPUT		(1 << 7): indicate this pin need to be configured as an output.
OUTPUT_VAL	(1 << 8): output val (1 = high, 0 = low)
SLEWRATE	(1 << 9): slew rate of the pin: 0 = disable, 1 = enable
DEBOUNCE	(1 << 16): indicate this pin needs debounce.
DEBOUNCE_VAL	(0x3fff << 17): debounce value.

NOTE:
Some requirements for using atmel,at91rm9200-pinctrl binding:
1. We have pin function node defined under at91 controller node to represent
   what pinmux functions this SoC supports.
2. The driver can use the function node's name and pin configuration node's
   name describe the pin function and group hierarchy.
   For example, Linux at91 pinctrl driver takes the function node's name
   as the function name and pin configuration node's name as group name to
   create the map table.
3. Each pin configuration node should have a phandle, devices can set pins
   configurations by referring to the phandle of that pin configuration node.
4. The gpio controller must be describe in the pinctrl simple-bus.

For each bank the required properties are:
- compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or
  "microchip,sam9x60-gpio"
- reg: physical base address and length of the controller's registers
- interrupts: interrupt outputs from the controller
- interrupt-controller: marks the device node as an interrupt controller
- #interrupt-cells: should be 2; refer to ../interrupt-controller/interrupts.txt
  for more details.
- gpio-controller
- #gpio-cells: should be 2; the first cell is the GPIO number and the second
  cell specifies GPIO flags as defined in <dt-bindings/gpio/gpio.h>.
- clocks: bank clock

Examples:

pinctrl@fffff400 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
	reg = <0xfffff400 0x600>;

	pioA: gpio@fffff400 {
		compatible = "atmel,at91sam9x5-gpio";
		reg = <0xfffff400 0x200>;
		interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
		#gpio-cells = <2>;
		gpio-controller;
		interrupt-controller;
		#interrupt-cells = <2>;
		clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
	};

	atmel,mux-mask = <
	      /*    A         B     */
	       0xffffffff 0xffc00c3b  /* pioA */
	       0xffffffff 0x7fff3ccf  /* pioB */
	       0xffffffff 0x007fffff  /* pioC */
	      >;

	/* shared pinctrl settings */
	dbgu {
		pinctrl_dbgu: dbgu-0 {
			atmel,pins =
				<1 14 0x1 0x0	/* PB14 periph A */
				 1 15 0x1 0x1>;	/* PB15 periph A with pullup */
		};
	};
};

dbgu: serial@fffff200 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xfffff200 0x200>;
	interrupts = <1 4 7>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dbgu>;
};


code:
* Atmel PIO4 Controller

The Atmel PIO4 controller is used to select the function of a pin and to
configure it.

Required properties:
- compatible:
	"atmel,sama5d2-pinctrl"
	"microchip,sama7g5-pinctrl"
- reg: base address and length of the PIO controller.
- interrupts: interrupt outputs from the controller, one for each bank.
- interrupt-controller: mark the device node as an interrupt controller.
- #interrupt-cells: should be two.
- gpio-controller: mark the device node as a gpio controller.
- #gpio-cells: should be two.

Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.

Subnode format
Each node (or subnode) will list the pins it needs and how to configured these
pins.

	node {
		pinmux = <PIN_NUMBER_PINMUX>;
		GENERIC_PINCONFIG;
	};

Required properties:
- pinmux: integer array. Each integer represents a pin number plus mux and
ioset settings. Use the macros from boot/dts/<soc>-pinfunc.h file to get the
right representation of the pin.

Optional properties:
- GENERIC_PINCONFIG: generic pinconfig options to use:
	- bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
	  input-schmitt-enable, input-debounce, output-low, output-high.
	- for microchip,sama7g5-pinctrl only:
		- slew-rate: 0 - disabled, 1 - enabled (default)
- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for
high drive. The default value is low drive.

Example:

#include <sama5d2-pinfunc.h>

...
{
	pioA: pinctrl@fc038000 {
		compatible = "atmel,sama5d2-pinctrl";
		reg = <0xfc038000 0x600>;
		interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
			     <68 IRQ_TYPE_LEVEL_HIGH 7>,
			     <69 IRQ_TYPE_LEVEL_HIGH 7>,
			     <70 IRQ_TYPE_LEVEL_HIGH 7>;
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-controller;
		#gpio-cells = <2>;
		clocks = <&pioA_clk>;

		pinctrl_i2c0_default: i2c0_default {
			pinmux = <PIN_PD21__TWD0>,
				 <PIN_PD22__TWCK0>;
			bias-disable;
		};

		pinctrl_led_gpio_default: led_gpio_default {
			pinmux = <PIN_PB0>,
				 <PIN_PB5>;
			bias-pull-up;
			atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>;
		};

		pinctrl_sdmmc1_default: sdmmc1_default {
			cmd_data {
				pinmux = <PIN_PA28__SDMMC1_CMD>,
					 <PIN_PA18__SDMMC1_DAT0>,
					 <PIN_PA19__SDMMC1_DAT1>,
					 <PIN_PA20__SDMMC1_DAT2>,
					 <PIN_PA21__SDMMC1_DAT3>;
				bias-pull-up;
			};

			ck_cd {
				pinmux = <PIN_PA22__SDMMC1_CK>,
					 <PIN_PA30__SDMMC1_CD>;
				bias-disable;
			};
		};
		...
	};
};
...


code:
Axis ARTPEC-6 Pin Controller

Required properties:
- compatible: "axis,artpec6-pinctrl".
- reg: Should contain the register physical address and length for the pin
       controller.

A pinctrl node should contain at least one subnode representing the pinctrl
groups available on the machine. Each subnode will list the mux function
required and what pin group it will use. Each subnode will also configure the
drive strength and bias pullup of the pin group. If either of these options is
not set, its actual value will be unspecified.

Required subnode-properties:
- function: Function to mux.
- groups: Name of the pin group to use for the function above.

	Available functions and groups (function: group0, group1...):
		gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
		      i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
		      spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2,
		      uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2,
		      uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1,
		      uart5nocts
		cpuclkout: cpuclkoutgrp0
		udlclkout: udlclkoutgrp0
		i2c1: i2c1grp0
		i2c2: i2c2grp0
		i2c3: i2c3grp0
		i2s0: i2s0grp0
		i2s1: i2s1grp0
		i2srefclk: i2srefclkgrp0
		spi0: spi0grp0
		spi1: spi1grp0
		pciedebug: pciedebuggrp0
		uart0: uart0grp0, uart0grp1, uart0grp2
		uart1: uart1grp0, uart1grp1
		uart2: uart2grp0, uart2grp1, uart2grp2
		uart3: uart3grp0
		uart4: uart4grp0, uart4grp1
		uart5: uart5grp0, uart5grp1, uart5nocts
		nand: nandgrp0
		sdio0: sdio0grp0
		sdio1: sdio1grp0
		ethernet: ethernetgrp0

Optional subnode-properties (see pinctrl-bindings.txt):
- drive-strength: 4, 6, 8, 9 mA.  For SD and NAND pins, this is for 3.3V VCCQ3.
- bias-pull-up
- bias-disable

Examples:
pinctrl@f801d000 {
	compatible = "axis,artpec6-pinctrl";
	reg = <0xf801d000 0x400>;

	pinctrl_uart0: uart0grp {
		function = "uart0";
		groups = "uart0grp0";
		drive-strength = <4>;
		bias-pull-up;
	};
	pinctrl_uart3: uart3grp {
		function = "uart3";
		groups = "uart3grp0";
	};
};
uart0: uart@f8036000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0xf8036000 0x1000>;
	interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pll2div24>, <&apb_pclk>;
	clock-names = "uart_clk", "apb_pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
};
uart3: uart@f8039000 {
	compatible = "arm,pl011", "arm,primecell";
	reg = <0xf8039000 0x1000>;
	interrupts = <0 128 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&pll2div24>, <&apb_pclk>;
	clock-names = "uart_clk", "apb_pclk";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
};


code:
* Pin-controller driver for the Marvell Berlin SoCs

Pin control registers are part of both chip controller and system
controller register sets. Pin controller nodes should be a sub-node of
either the chip controller or system controller node. The pins
controlled are organized in groups, so no actual pin information is
needed.

A pin-controller node should contain subnodes representing the pin group
configurations, one per function. Each subnode has the group name and
the muxing function used.

Be aware the Marvell Berlin datasheets use the keyword 'mode' for what
is called a 'function' in the pin-controller subsystem.

Required properties:
- compatible: should be one of:
	"marvell,berlin2-soc-pinctrl",
	"marvell,berlin2-system-pinctrl",
	"marvell,berlin2cd-soc-pinctrl",
	"marvell,berlin2cd-system-pinctrl",
	"marvell,berlin2q-soc-pinctrl",
	"marvell,berlin2q-system-pinctrl",
	"marvell,berlin4ct-avio-pinctrl",
	"marvell,berlin4ct-soc-pinctrl",
	"marvell,berlin4ct-system-pinctrl",
	"syna,as370-soc-pinctrl"

Required subnode-properties:
- groups: a list of strings describing the group names.
- function: a string describing the function used to mux the groups.

Example:

sys_pinctrl: pin-controller {
	compatible = "marvell,berlin2q-system-pinctrl";

	uart0_pmux: uart0-pmux {
		groups = "GSM12";
		function = "uart0";
	};
};

&uart0 {
	pinctrl-0 = <&uart0_pmux>;
	pinctrl-names = "default";
};


code:
Bitmain BM1880 Pin Controller

This binding describes the pin controller found in the BM1880 SoC.

Required Properties:

- compatible:   Should be "bitmain,bm1880-pinctrl"
- reg:          Offset and length of pinctrl space in SCTRL.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
includes pinmux and various pin configuration parameters, such as pull-up,
slew rate etc...

Each configuration node can consist of multiple nodes describing the pinmux
options. The name of each subnode is not important; all subnodes should be
enumerated and processed purely based on their content.

The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pinmux subnode:

Required Properties:

- pins:           An array of strings, each string containing the name of a pin.
                  Valid values for pins are:

                  MIO0 - MIO111

- groups:         An array of strings, each string containing the name of a pin
                  group. Valid values for groups are:

                  nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp,
                  pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp,
                  pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp,
                  pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp,
                  pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp,
                  pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp,
                  pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp,
                  pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp,
                  i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp,
                  uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp,
                  uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp,
                  uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp,
                  gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp,
                  gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp,
                  gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp,
                  gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp,
                  gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp,
                  gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp,
                  gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp,
                  gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp,
                  gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp,
                  gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp,
                  gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp,
                  gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp,
                  gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp,
                  gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp,
                  i2s1_grp, i2s1_mclkin_grp, spi0_grp

- function:       An array of strings, each string containing the name of the
                  pinmux functions. The following are the list of pinmux
                  functions available:

                  nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4,
                  pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13,
                  pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22,
                  pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31,
                  pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3,
                  i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7,
                  uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15,
                  gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8,
                  gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16,
                  gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23,
                  gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30,
                  gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37,
                  gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44,
                  gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51,
                  gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58,
                  gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65,
                  gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin,
                  spi0

Optional Properties:

- bias-disable:  No arguments. Disable pin bias.
- bias-pull-down: No arguments. The specified pins should be configured as
                  pull down.
- bias-pull-up:   No arguments. The specified pins should be configured as
                  pull up.
- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
                  pins
- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
                  pins
- slew-rate:      Integer. Sets slew rate for the specified pins.
                  Valid values are:
                  <0>  - Slow
                  <1>  - Fast
- drive-strength: Integer. Selects the drive strength for the specified
                  pins in mA.
                  Valid values are:
                  <4>
                  <8>
                  <12>
                  <16>
                  <20>
                  <24>
                  <28>
                  <32>

Example:
        pinctrl: pinctrl@400 {
                compatible = "bitmain,bm1880-pinctrl";
                reg = <0x400 0x120>;

                pinctrl_uart0_default: uart0-default {
                        pinmux {
                                groups = "uart0_grp";
                                function = "uart0";
                        };
                };
        };


code:
Broadcom BCM281xx Pin Controller

This is a pin controller for the Broadcom BCM281xx SoC family, which includes
BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs.

=== Pin Controller Node ===

Required Properties:

- compatible:	Must be "brcm,bcm11351-pinctrl"
- reg:		Base address of the PAD Controller register block and the size
		of the block.

For example, the following is the bare minimum node:

	pinctrl@35004800 {
		compatible = "brcm,bcm11351-pinctrl";
		reg = <0x35004800 0x430>;
	};

As a pin controller device, in addition to the required properties, this node
should also contain the pin configuration nodes that client devices reference,
if any.

=== Pin Configuration Node ===

Each pin configuration node is a sub-node of the pin controller node and is a
container of an arbitrary number of subnodes, called pin group nodes in this
document.

Please refer to the pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the definition of a
"pin configuration node".

=== Pin Group Node ===

A pin group node specifies the desired pin mux and/or pin configuration for an
arbitrary number of pins.  The name of the pin group node is optional and not
used.

A pin group node only affects the properties specified in the node, and has no
effect on any properties that are omitted.

The pin group node accepts a subset of the generic pin config properties. For
details generic pin config properties, please refer to pinctrl-bindings.txt
and <include/linux/pinctrl/pinconfig-generic.h>.

Each pin controlled by this pin controller belong to one of three types:
Standard, I2C, and HDMI.  Each type accepts a different set of pin config
properties.  A list of pins and their types is provided below.

Required Properties (applicable to all pins):

- pins:		Multiple strings.  Specifies the name(s) of one or more pins to
		be configured by this node.

Optional Properties (for standard pins):

- function:			String. Specifies the pin mux selection. Values
				must be one of: "alt1", "alt2", "alt3", "alt4"
- input-schmitt-enable:		No arguments. Enable schmitt-trigger mode.
- input-schmitt-disable:	No arguments. Disable schmitt-trigger mode.
- bias-pull-up:			No arguments. Pull up on pin.
- bias-pull-down:		No arguments. Pull down on pin.
- bias-disable:			No arguments. Disable pin bias.
- slew-rate:			Integer. Meaning depends on configured pin mux:
				*_SCL or *_SDA:
					0: Standard(100kbps)& Fast(400kbps) mode
					1: Highspeed (3.4Mbps) mode
				IC_DM or IC_DP:
					0: normal slew rate
					1: fast slew rate
				Otherwise:
					0: fast slew rate
					1: normal slew rate
- input-enable:			No arguments. Enable input (does not affect
				output.)
- input-disable:		No arguments. Disable input (does not affect
				output.)
- drive-strength:		Integer. Drive strength in mA.  Valid values are
				2, 4, 6, 8, 10, 12, 14, 16 mA.

Optional Properties (for I2C pins):

- function:			String. Specifies the pin mux selection. Values
				must be one of: "alt1", "alt2", "alt3", "alt4"
- bias-pull-up:			Integer. Pull up strength in Ohm. There are 3
				pull-up resistors (1.2k, 1.8k, 2.7k) available
				in parallel for I2C pins, so the valid values
				are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm.
- bias-disable:			No arguments. Disable pin bias.
- slew-rate:			Integer. Meaning depends on configured pin mux:
				*_SCL or *_SDA:
					0: Standard(100kbps)& Fast(400kbps) mode
					1: Highspeed (3.4Mbps) mode
				IC_DM or IC_DP:
					0: normal slew rate
					1: fast slew rate
				Otherwise:
					0: fast slew rate
					1: normal slew rate
- input-enable:			No arguments. Enable input (does not affect
				output.)
- input-disable:		No arguments. Disable input (does not affect
				output.)

Optional Properties (for HDMI pins):

- function:			String. Specifies the pin mux selection. Values
				must be one of: "alt1", "alt2", "alt3", "alt4"
- slew-rate:			Integer. Controls slew rate.
					0: Standard(100kbps)& Fast(400kbps) mode
					1: Highspeed (3.4Mbps) mode
- input-enable:			No arguments. Enable input (does not affect
				output.)
- input-disable:		No arguments. Disable input (does not affect
				output.)

Example:
// pin controller node
pinctrl@35004800 {
	compatible = "brcm,bcm11351-pinctrl";
	reg = <0x35004800 0x430>;

	// pin configuration node
	dev_a_default: dev_a_active {
		//group node defining 1 standard pin
		grp_1 {
			pins		= "std_pin1";
			function	= "alt1";
			input-schmitt-enable;
			bias-disable;
			slew-rate	= <1>;
			drive-strength	= <4>;
		};

		// group node defining 2 I2C pins
		grp_2 {
			pins		= "i2c_pin1", "i2c_pin2";
			function	= "alt2";
			bias-pull-up	= <720>;
			input-enable;
		};

		// group node defining 2 HDMI pins
		grp_3 {
			pins		= "hdmi_pin1", "hdmi_pin2";
			function	= "alt3";
			slew-rate	= <1>;
		};

		// other pin group nodes
		...
	};

	// other pin configuration nodes
	...
};

In the example above, "dev_a_active" is a pin configuration node with a number
of sub-nodes.  In the pin group node "grp_1", one pin, "std_pin1", is defined in
the "pins" property.  Thus, the remaining properties in the "grp_1" node applies
only to this pin, including the following settings:
 - setting pinmux to "alt1"
 - enabling schmitt-trigger (hystersis) mode
 - disabling pin bias
 - setting the slew-rate to 1
 - setting the drive strength to 4 mA
Note that neither "input-enable" nor "input-disable" was specified - the pinctrl
subsystem will therefore leave this property unchanged from whatever state it
was in before applying these changes.

The "pins" property in the pin group node "grp_2" specifies two pins -
"i2c_pin1" and "i2c_pin2"; the remaining properties in this pin group node,
therefore, applies to both of these pins.  The properties include:
 - setting pinmux to "alt2"
 - setting pull-up resistance to 720 Ohm (ie. enabling 1.2k and 1.8k resistors
   in parallel)
 - enabling both pins' input
"slew-rate" is not specified in this pin group node, so the slew-rate for these
pins are left as-is.

Finally, "grp_3" defines two HDMI pins.  The following properties are applied to
both pins:
 - setting pinmux to "alt3"
 - setting slew-rate to 1; for HDMI pins, this corresponds to the 3.4 Mbps
   Highspeed mode
The input is neither enabled or disabled, and is left untouched.

=== Pin Names and Type ===

The following are valid pin names and their pin types:

	"adcsync",		Standard
	"bat_rm",		Standard
	"bsc1_scl",		I2C
	"bsc1_sda",		I2C
	"bsc2_scl",		I2C
	"bsc2_sda",		I2C
	"classgpwr",		Standard
	"clk_cx8",		Standard
	"clkout_0",		Standard
	"clkout_1",		Standard
	"clkout_2",		Standard
	"clkout_3",		Standard
	"clkreq_in_0",		Standard
	"clkreq_in_1",		Standard
	"cws_sys_req1",		Standard
	"cws_sys_req2",		Standard
	"cws_sys_req3",		Standard
	"digmic1_clk",		Standard
	"digmic1_dq",		Standard
	"digmic2_clk",		Standard
	"digmic2_dq",		Standard
	"gpen13",		Standard
	"gpen14",		Standard
	"gpen15",		Standard
	"gpio00",		Standard
	"gpio01",		Standard
	"gpio02",		Standard
	"gpio03",		Standard
	"gpio04",		Standard
	"gpio05",		Standard
	"gpio06",		Standard
	"gpio07",		Standard
	"gpio08",		Standard
	"gpio09",		Standard
	"gpio10",		Standard
	"gpio11",		Standard
	"gpio12",		Standard
	"gpio13",		Standard
	"gpio14",		Standard
	"gps_pablank",		Standard
	"gps_tmark",		Standard
	"hdmi_scl",		HDMI
	"hdmi_sda",		HDMI
	"ic_dm",		Standard
	"ic_dp",		Standard
	"kp_col_ip_0",		Standard
	"kp_col_ip_1",		Standard
	"kp_col_ip_2",		Standard
	"kp_col_ip_3",		Standard
	"kp_row_op_0",		Standard
	"kp_row_op_1",		Standard
	"kp_row_op_2",		Standard
	"kp_row_op_3",		Standard
	"lcd_b_0",		Standard
	"lcd_b_1",		Standard
	"lcd_b_2",		Standard
	"lcd_b_3",		Standard
	"lcd_b_4",		Standard
	"lcd_b_5",		Standard
	"lcd_b_6",		Standard
	"lcd_b_7",		Standard
	"lcd_g_0",		Standard
	"lcd_g_1",		Standard
	"lcd_g_2",		Standard
	"lcd_g_3",		Standard
	"lcd_g_4",		Standard
	"lcd_g_5",		Standard
	"lcd_g_6",		Standard
	"lcd_g_7",		Standard
	"lcd_hsync",		Standard
	"lcd_oe",		Standard
	"lcd_pclk",		Standard
	"lcd_r_0",		Standard
	"lcd_r_1",		Standard
	"lcd_r_2",		Standard
	"lcd_r_3",		Standard
	"lcd_r_4",		Standard
	"lcd_r_5",		Standard
	"lcd_r_6",		Standard
	"lcd_r_7",		Standard
	"lcd_vsync",		Standard
	"mdmgpio0",		Standard
	"mdmgpio1",		Standard
	"mdmgpio2",		Standard
	"mdmgpio3",		Standard
	"mdmgpio4",		Standard
	"mdmgpio5",		Standard
	"mdmgpio6",		Standard
	"mdmgpio7",		Standard
	"mdmgpio8",		Standard
	"mphi_data_0",		Standard
	"mphi_data_1",		Standard
	"mphi_data_2",		Standard
	"mphi_data_3",		Standard
	"mphi_data_4",		Standard
	"mphi_data_5",		Standard
	"mphi_data_6",		Standard
	"mphi_data_7",		Standard
	"mphi_data_8",		Standard
	"mphi_data_9",		Standard
	"mphi_data_10",		Standard
	"mphi_data_11",		Standard
	"mphi_data_12",		Standard
	"mphi_data_13",		Standard
	"mphi_data_14",		Standard
	"mphi_data_15",		Standard
	"mphi_ha0",		Standard
	"mphi_hat0",		Standard
	"mphi_hat1",		Standard
	"mphi_hce0_n",		Standard
	"mphi_hce1_n",		Standard
	"mphi_hrd_n",		Standard
	"mphi_hwr_n",		Standard
	"mphi_run0",		Standard
	"mphi_run1",		Standard
	"mtx_scan_clk",		Standard
	"mtx_scan_data",	Standard
	"nand_ad_0",		Standard
	"nand_ad_1",		Standard
	"nand_ad_2",		Standard
	"nand_ad_3",		Standard
	"nand_ad_4",		Standard
	"nand_ad_5",		Standard
	"nand_ad_6",		Standard
	"nand_ad_7",		Standard
	"nand_ale",		Standard
	"nand_cen_0",		Standard
	"nand_cen_1",		Standard
	"nand_cle",		Standard
	"nand_oen",		Standard
	"nand_rdy_0",		Standard
	"nand_rdy_1",		Standard
	"nand_wen",		Standard
	"nand_wp",		Standard
	"pc1",			Standard
	"pc2",			Standard
	"pmu_int",		Standard
	"pmu_scl",		I2C
	"pmu_sda",		I2C
	"rfst2g_mtsloten3g",	Standard
	"rgmii_0_rx_ctl",	Standard
	"rgmii_0_rxc",		Standard
	"rgmii_0_rxd_0",	Standard
	"rgmii_0_rxd_1",	Standard
	"rgmii_0_rxd_2",	Standard
	"rgmii_0_rxd_3",	Standard
	"rgmii_0_tx_ctl",	Standard
	"rgmii_0_txc",		Standard
	"rgmii_0_txd_0",	Standard
	"rgmii_0_txd_1",	Standard
	"rgmii_0_txd_2",	Standard
	"rgmii_0_txd_3",	Standard
	"rgmii_1_rx_ctl",	Standard
	"rgmii_1_rxc",		Standard
	"rgmii_1_rxd_0",	Standard
	"rgmii_1_rxd_1",	Standard
	"rgmii_1_rxd_2",	Standard
	"rgmii_1_rxd_3",	Standard
	"rgmii_1_tx_ctl",	Standard
	"rgmii_1_txc",		Standard
	"rgmii_1_txd_0",	Standard
	"rgmii_1_txd_1",	Standard
	"rgmii_1_txd_2",	Standard
	"rgmii_1_txd_3",	Standard
	"rgmii_gpio_0",		Standard
	"rgmii_gpio_1",		Standard
	"rgmii_gpio_2",		Standard
	"rgmii_gpio_3",		Standard
	"rtxdata2g_txdata3g1",	Standard
	"rtxen2g_txdata3g2",	Standard
	"rxdata3g0",		Standard
	"rxdata3g1",		Standard
	"rxdata3g2",		Standard
	"sdio1_clk",		Standard
	"sdio1_cmd",		Standard
	"sdio1_data_0",		Standard
	"sdio1_data_1",		Standard
	"sdio1_data_2",		Standard
	"sdio1_data_3",		Standard
	"sdio4_clk",		Standard
	"sdio4_cmd",		Standard
	"sdio4_data_0",		Standard
	"sdio4_data_1",		Standard
	"sdio4_data_2",		Standard
	"sdio4_data_3",		Standard
	"sim_clk",		Standard
	"sim_data",		Standard
	"sim_det",		Standard
	"sim_resetn",		Standard
	"sim2_clk",		Standard
	"sim2_data",		Standard
	"sim2_det",		Standard
	"sim2_resetn",		Standard
	"sri_c",		Standard
	"sri_d",		Standard
	"sri_e",		Standard
	"ssp_extclk",		Standard
	"ssp0_clk",		Standard
	"ssp0_fs",		Standard
	"ssp0_rxd",		Standard
	"ssp0_txd",		Standard
	"ssp2_clk",		Standard
	"ssp2_fs_0",		Standard
	"ssp2_fs_1",		Standard
	"ssp2_fs_2",		Standard
	"ssp2_fs_3",		Standard
	"ssp2_rxd_0",		Standard
	"ssp2_rxd_1",		Standard
	"ssp2_txd_0",		Standard
	"ssp2_txd_1",		Standard
	"ssp3_clk",		Standard
	"ssp3_fs",		Standard
	"ssp3_rxd",		Standard
	"ssp3_txd",		Standard
	"ssp4_clk",		Standard
	"ssp4_fs",		Standard
	"ssp4_rxd",		Standard
	"ssp4_txd",		Standard
	"ssp5_clk",		Standard
	"ssp5_fs",		Standard
	"ssp5_rxd",		Standard
	"ssp5_txd",		Standard
	"ssp6_clk",		Standard
	"ssp6_fs",		Standard
	"ssp6_rxd",		Standard
	"ssp6_txd",		Standard
	"stat_1",		Standard
	"stat_2",		Standard
	"sysclken",		Standard
	"traceclk",		Standard
	"tracedt00",		Standard
	"tracedt01",		Standard
	"tracedt02",		Standard
	"tracedt03",		Standard
	"tracedt04",		Standard
	"tracedt05",		Standard
	"tracedt06",		Standard
	"tracedt07",		Standard
	"tracedt08",		Standard
	"tracedt09",		Standard
	"tracedt10",		Standard
	"tracedt11",		Standard
	"tracedt12",		Standard
	"tracedt13",		Standard
	"tracedt14",		Standard
	"tracedt15",		Standard
	"txdata3g0",		Standard
	"txpwrind",		Standard
	"uartb1_ucts",		Standard
	"uartb1_urts",		Standard
	"uartb1_urxd",		Standard
	"uartb1_utxd",		Standard
	"uartb2_urxd",		Standard
	"uartb2_utxd",		Standard
	"uartb3_ucts",		Standard
	"uartb3_urts",		Standard
	"uartb3_urxd",		Standard
	"uartb3_utxd",		Standard
	"uartb4_ucts",		Standard
	"uartb4_urts",		Standard
	"uartb4_urxd",		Standard
	"uartb4_utxd",		Standard
	"vc_cam1_scl",		I2C
	"vc_cam1_sda",		I2C
	"vc_cam2_scl",		I2C
	"vc_cam2_sda",		I2C
	"vc_cam3_scl",		I2C
	"vc_cam3_sda",		I2C


code:
Broadcom BCM2835 GPIO (and pinmux) controller

The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
controller, and pinmux/control device.

Required properties:
- compatible: "brcm,bcm2835-gpio"
- compatible: should be one of:
  "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
  "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
  "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
  "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
- reg: Should contain the physical address of the GPIO module's registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and the
  second cell is used to specify optional parameters:
  - bit 0 specifies polarity (0 for normal, 1 for inverted)
- interrupts : The interrupt outputs from the controller. One interrupt per
  individual bank followed by the "all banks" interrupt. For BCM7211, an
  additional set of per-bank interrupt line and an "all banks" wake-up
  interrupt may be specified.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells : Should be 2.
  The first cell is the GPIO number.
  The second cell is used to specify flags:
    bits[3:0] trigger type and level flags:
      1 = low-to-high edge triggered.
      2 = high-to-low edge triggered.
      4 = active high level-sensitive.
      8 = active low level-sensitive.
    Valid combinations are 1, 2, 3, 4, 8.

Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

Each pin configuration node lists the pin(s) to which it applies, and one or
more of the mux function to select on those pin(s), and pull-up/down
configuration. Each subnode only affects those parameters that are explicitly
listed. In other words, a subnode that lists only a mux function implies no
information about any pull configuration. Similarly, a subnode that lists only
a pul parameter implies no information about the mux function.

The BCM2835 pin configuration and multiplexing supports the generic bindings.
For details on each properties, you can refer to ./pinctrl-bindings.txt.

Required sub-node properties:
  - pins
  - function

Optional sub-node properties:
  - bias-disable
  - bias-pull-up
  - bias-pull-down
  - output-high
  - output-low

Legacy pin configuration and multiplexing binding:
*** (Its use is deprecated, use generic multiplexing and configuration
bindings instead)

Required subnode-properties:
- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs
  are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.

Optional subnode-properties:
- brcm,function: Integer, containing the function to mux to the pin(s):
  0: GPIO in
  1: GPIO out
  2: alt5
  3: alt4
  4: alt0
  5: alt1
  6: alt2
  7: alt3
- brcm,pull: Integer, representing the pull-down/up to apply to the pin(s):
  0: none
  1: down
  2: up

Each of brcm,function and brcm,pull may contain either a single value which
will be applied to all pins in brcm,pins, or 1 value for each entry in
brcm,pins.

Example:

	gpio: gpio {
		compatible = "brcm,bcm2835-gpio";
		reg = <0x2200000 0xb4>;
		interrupts = <2 17>, <2 19>, <2 18>, <2 20>;

		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM4908 pin controller

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

description:
  Binding for pin controller present on BCM4908 family SoCs.

properties:
  compatible:
    const: brcm,bcm4908-pinctrl

  reg:
    maxItems: 1

patternProperties:
  '-pins$':
    type: object
    $ref: pinmux-node.yaml#
    additionalProperties: false

    properties:
      function:
        enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8,
                led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16,
                led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24,
                led_25, led_26, led_27, led_28, led_29, led_30, led_31,
                hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr,
                usb1_pwr ]

      groups:
        minItems: 1
        maxItems: 2
        items:
          enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a,
                  led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a,
                  led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b,
                  led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b,
                  led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a,
                  led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a,
                  led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a,
                  led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a,
                  led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a,
                  led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp,
                  nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp,
                  usb1_pwr_grp ]

allOf:
  - $ref: pinctrl.yaml#

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    pinctrl@ff800560 {
        compatible = "brcm,bcm4908-pinctrl";
        reg = <0xff800560 0x10>;

        led_0-a-pins {
            function = "led_0";
            groups = "led_0_grp_a";
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6318-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6318 pin controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description:
  Bindings for Broadcom's BCM6318 memory-mapped pin controller.

properties:
  compatible:
    const: brcm,bcm6318-pinctrl

  reg:
    maxItems: 2

patternProperties:
  '-pins$':
    type: object
    $ref: pinmux-node.yaml#

    properties:
      function:
        enum: [ ephy0_spd_led, ephy1_spd_led, ephy2_spd_led, ephy3_spd_led,
                ephy0_act_led, ephy1_act_led, ephy2_act_led, ephy3_act_led,
                serial_led_data, serial_led_clk, inet_act_led, inet_fail_led,
                dsl_led, post_fail_led, wlan_wps_led, usb_pwron,
                usb_device_led, usb_active ]

      pins:
        enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
                gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio40 ]

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pinctrl@18 {
      compatible = "brcm,bcm6318-pinctrl";
      reg = <0x18 0x10>, <0x54 0x18>;

      pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
        function = "ephy0_spd_led";
        pins = "gpio0";
      };

      pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
        function = "ephy1_spd_led";
        pins = "gpio1";
      };

      pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
        function = "ephy2_spd_led";
        pins = "gpio2";
      };

      pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
        function = "ephy3_spd_led";
        pins = "gpio3";
      };

      pinctrl_ephy0_act_led: ephy0_act_led-pins {
        function = "ephy0_act_led";
        pins = "gpio4";
      };

      pinctrl_ephy1_act_led: ephy1_act_led-pins {
        function = "ephy1_act_led";
        pins = "gpio5";
      };

      pinctrl_ephy2_act_led: ephy2_act_led-pins {
        function = "ephy2_act_led";
        pins = "gpio6";
      };

      pinctrl_ephy3_act_led: ephy3_act_led-pins {
        function = "ephy3_act_led";
        pins = "gpio7";
      };

      pinctrl_serial_led: serial_led-pins {
        pinctrl_serial_led_data: serial_led_data-pins {
          function = "serial_led_data";
          pins = "gpio6";
        };

        pinctrl_serial_led_clk: serial_led_clk-pins {
          function = "serial_led_clk";
          pins = "gpio7";
        };
      };

      pinctrl_inet_act_led: inet_act_led-pins {
        function = "inet_act_led";
        pins = "gpio8";
      };

      pinctrl_inet_fail_led: inet_fail_led-pins {
        function = "inet_fail_led";
        pins = "gpio9";
      };

      pinctrl_dsl_led: dsl_led-pins {
        function = "dsl_led";
        pins = "gpio10";
      };

      pinctrl_post_fail_led: post_fail_led-pins {
        function = "post_fail_led";
        pins = "gpio11";
      };

      pinctrl_wlan_wps_led: wlan_wps_led-pins {
        function = "wlan_wps_led";
        pins = "gpio12";
      };

      pinctrl_usb_pwron: usb_pwron-pins {
        function = "usb_pwron";
        pins = "gpio13";
      };

      pinctrl_usb_device_led: usb_device_led-pins {
        function = "usb_device_led";
        pins = "gpio13";
      };

      pinctrl_usb_active: usb_active-pins {
        function = "usb_active";
        pins = "gpio40";
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM63268 pin controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description:
  Bindings for Broadcom's BCM63268 memory-mapped pin controller.

properties:
  compatible:
    const: brcm,bcm63268-pinctrl

  reg:
    maxItems: 3

patternProperties:
  '-pins$':
    type: object
    $ref: pinmux-node.yaml#

    properties:
      function:
        enum: [ serial_led_clk, serial_led_data, hsspi_cs4, hsspi_cs5,
                hsspi_cs6, hsspi_cs7, adsl_spi_miso, adsl_spi_mosi,
                vreq_clk, pcie_clkreq_b, robosw_led_clk, robosw_led_data,
                nand, gpio35_alt, dectpd, vdsl_phy_override_0,
                vdsl_phy_override_1, vdsl_phy_override_2,
                vdsl_phy_override_3, dsl_gpio8, dsl_gpio9 ]

      pins:
        enum: [ gpio0, gpio1, gpio16, gpio17, gpio8, gpio9, gpio18, gpio19,
                gpio22, gpio23, gpio30, gpio31, nand_grp, gpio35
                dectpd_grp, vdsl_phy_override_0_grp,
                vdsl_phy_override_1_grp, vdsl_phy_override_2_grp,
                vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ]

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pinctrl@10 {
      compatible = "brcm,bcm63268-pinctrl";
      reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;

      pinctrl_serial_led: serial_led-pins {
        pinctrl_serial_led_clk: serial_led_clk-pins {
          function = "serial_led_clk";
          pins = "gpio0";
        };

        pinctrl_serial_led_data: serial_led_data-pins {
          function = "serial_led_data";
          pins = "gpio1";
        };
      };

      pinctrl_hsspi_cs4: hsspi_cs4-pins {
        function = "hsspi_cs4";
        pins = "gpio16";
      };

      pinctrl_hsspi_cs5: hsspi_cs5-pins {
        function = "hsspi_cs5";
        pins = "gpio17";
      };

      pinctrl_hsspi_cs6: hsspi_cs6-pins {
        function = "hsspi_cs6";
        pins = "gpio8";
      };

      pinctrl_hsspi_cs7: hsspi_cs7-pins {
        function = "hsspi_cs7";
        pins = "gpio9";
      };

      pinctrl_adsl_spi: adsl_spi-pins {
        pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
          function = "adsl_spi_miso";
          pins = "gpio18";
        };

        pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
          function = "adsl_spi_mosi";
          pins = "gpio19";
        };
      };

      pinctrl_vreq_clk: vreq_clk-pins {
        function = "vreq_clk";
        pins = "gpio22";
      };

      pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
        function = "pcie_clkreq_b";
        pins = "gpio23";
      };

      pinctrl_robosw_led_clk: robosw_led_clk-pins {
        function = "robosw_led_clk";
        pins = "gpio30";
      };

      pinctrl_robosw_led_data: robosw_led_data-pins {
        function = "robosw_led_data";
        pins = "gpio31";
      };

      pinctrl_nand: nand-pins {
        function = "nand";
        group = "nand_grp";
      };

      pinctrl_gpio35_alt: gpio35_alt-pins {
        function = "gpio35_alt";
        pin = "gpio35";
      };

      pinctrl_dectpd: dectpd-pins {
        function = "dectpd";
        group = "dectpd_grp";
      };

      pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
        function = "vdsl_phy_override_0";
        group = "vdsl_phy_override_0_grp";
      };

      pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
        function = "vdsl_phy_override_1";
        group = "vdsl_phy_override_1_grp";
      };

      pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
        function = "vdsl_phy_override_2";
        group = "vdsl_phy_override_2_grp";
      };

      pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
        function = "vdsl_phy_override_3";
        group = "vdsl_phy_override_3_grp";
      };

      pinctrl_dsl_gpio8: dsl_gpio8-pins {
        function = "dsl_gpio8";
        group = "dsl_gpio8";
      };

      pinctrl_dsl_gpio9: dsl_gpio9-pins {
        function = "dsl_gpio9";
        group = "dsl_gpio9";
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6328-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6328 pin controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description:
  Bindings for Broadcom's BCM6328 memory-mapped pin controller.

properties:
  compatible:
    const: brcm,bcm6328-pinctrl

  reg:
    maxItems: 1

patternProperties:
  '-pins$':
    type: object
    $ref: pinmux-node.yaml#

    properties:
      function:
        enum: [ serial_led_data, serial_led_clk, inet_act_led, pcie_clkreq,
                led, ephy0_act_led, ephy1_act_led, ephy2_act_led,
                ephy3_act_led, hsspi_cs1, usb_device_port, usb_host_port ]

      pins:
        enum: [ gpio6, gpio7, gpio11, gpio16, gpio17, gpio18, gpio19,
                gpio20, gpio25, gpio26, gpio27, gpio28, hsspi_cs1,
                usb_port1 ]

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pinctrl@18 {
      compatible = "brcm,bcm6328-pinctrl";
      reg = <0x18 0x10>;

      pinctrl_serial_led: serial_led-pins {
        pinctrl_serial_led_data: serial_led_data-pins {
          function = "serial_led_data";
          pins = "gpio6";
        };

        pinctrl_serial_led_clk: serial_led_clk-pins {
          function = "serial_led_clk";
          pins = "gpio7";
        };
      };

      pinctrl_inet_act_led: inet_act_led-pins {
        function = "inet_act_led";
        pins = "gpio11";
      };

      pinctrl_pcie_clkreq: pcie_clkreq-pins {
        function = "pcie_clkreq";
        pins = "gpio16";
      };

      pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
        function = "led";
        pins = "gpio17";
      };

      pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
        function = "led";
        pins = "gpio18";
      };

      pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
        function = "led";
        pins = "gpio19";
      };

      pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
        function = "led";
        pins = "gpio20";
      };

      pinctrl_ephy0_act_led: ephy0_act_led-pins {
        function = "ephy0_act_led";
        pins = "gpio25";
      };

      pinctrl_ephy1_act_led: ephy1_act_led-pins {
        function = "ephy1_act_led";
        pins = "gpio26";
      };

      pinctrl_ephy2_act_led: ephy2_act_led-pins {
        function = "ephy2_act_led";
        pins = "gpio27";
      };

      pinctrl_ephy3_act_led: ephy3_act_led-pins {
        function = "ephy3_act_led";
        pins = "gpio28";
      };

      pinctrl_hsspi_cs1: hsspi_cs1-pins {
        function = "hsspi_cs1";
        pins = "hsspi_cs1";
      };

      pinctrl_usb_port1_device: usb_port1_device-pins {
        function = "usb_device_port";
        pins = "usb_port1";
      };

      pinctrl_usb_port1_host: usb_port1_host-pins {
        function = "usb_host_port";
        pins = "usb_port1";
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6358-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6358 pin controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description:
  Bindings for Broadcom's BCM6358 memory-mapped pin controller.

properties:
  compatible:
    const: brcm,bcm6358-pinctrl

  reg:
    maxItems: 1

patternProperties:
  '-pins$':
    type: object
    $ref: pinmux-node.yaml#

    properties:
      function:
        enum: [ ebi_cs, uart1, serial_led, legacy_led, led, spi_cs, utopia,
                pwm_syn_clk, sys_irq ]

      pins:
        enum: [ ebi_cs_grp, uart1_grp, serial_led_grp, legacy_led_grp,
                led_grp, spi_cs_grp, utopia_grp, pwm_syn_clk, sys_irq_grp ]

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pinctrl@18 {
      compatible = "brcm,bcm6358-pinctrl";
      reg = <0x18 0x4>;

      pinctrl_ebi_cs: ebi_cs-pins {
        function = "ebi_cs";
        groups = "ebi_cs_grp";
      };

      pinctrl_uart1: uart1-pins {
        function = "uart1";
        groups = "uart1_grp";
      };

      pinctrl_serial_led: serial_led-pins {
        function = "serial_led";
        groups = "serial_led_grp";
      };

      pinctrl_legacy_led: legacy_led-pins {
        function = "legacy_led";
        groups = "legacy_led_grp";
      };

      pinctrl_led: led-pins {
        function = "led";
        groups = "led_grp";
      };

      pinctrl_spi_cs_23: spi_cs-pins {
        function = "spi_cs";
        groups = "spi_cs_grp";
      };

      pinctrl_utopia: utopia-pins {
        function = "utopia";
        groups = "utopia_grp";
      };

      pinctrl_pwm_syn_clk: pwm_syn_clk-pins {
        function = "pwm_syn_clk";
        groups = "pwm_syn_clk_grp";
      };

      pinctrl_sys_irq: sys_irq-pins {
        function = "sys_irq";
        groups = "sys_irq_grp";
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6362-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6362 pin controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description:
  Bindings for Broadcom's BCM6362 memory-mapped pin controller.

properties:
  compatible:
    const: brcm,bcm6362-pinctrl

  reg:
    maxItems: 2

patternProperties:
  '-pins$':
    type: object
    $ref: pinmux-node.yaml#

    properties:
      function:
        enum: [ usb_device_led, sys_irq, serial_led_clk, serial_led_data,
                robosw_led_data, robosw_led_clk, robosw_led0, robosw_led1,
                inet_led, spi_cs2, spi_cs3, ntr_pulse, uart1_scts,
                uart1_srts, uart1_sdin, uart1_sdout, adsl_spi_miso,
                adsl_spi_mosi, adsl_spi_clk, adsl_spi_cs, ephy0_led,
                ephy1_led, ephy2_led, ephy3_led, ext_irq0, ext_irq1,
                ext_irq2, ext_irq3, nand ]

      pins:
        enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
                gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,
                gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21,
                gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, nand_grp ]

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pinctrl@18 {
      compatible = "brcm,bcm6362-pinctrl";
      reg = <0x18 0x10>, <0x38 0x4>;

      pinctrl_usb_device_led: usb_device_led-pins {
        function = "usb_device_led";
        pins = "gpio0";
      };

      pinctrl_sys_irq: sys_irq-pins {
        function = "sys_irq";
        pins = "gpio1";
      };

      pinctrl_serial_led: serial_led-pins {
        pinctrl_serial_led_clk: serial_led_clk-pins {
          function = "serial_led_clk";
          pins = "gpio2";
        };

        pinctrl_serial_led_data: serial_led_data-pins {
          function = "serial_led_data";
          pins = "gpio3";
        };
      };

      pinctrl_robosw_led_data: robosw_led_data-pins {
        function = "robosw_led_data";
        pins = "gpio4";
      };

      pinctrl_robosw_led_clk: robosw_led_clk-pins {
        function = "robosw_led_clk";
        pins = "gpio5";
      };

      pinctrl_robosw_led0: robosw_led0-pins {
        function = "robosw_led0";
        pins = "gpio6";
      };

      pinctrl_robosw_led1: robosw_led1-pins {
        function = "robosw_led1";
        pins = "gpio7";
      };

      pinctrl_inet_led: inet_led-pins {
        function = "inet_led";
        pins = "gpio8";
      };

      pinctrl_spi_cs2: spi_cs2-pins {
        function = "spi_cs2";
        pins = "gpio9";
      };

      pinctrl_spi_cs3: spi_cs3-pins {
        function = "spi_cs3";
        pins = "gpio10";
      };

      pinctrl_ntr_pulse: ntr_pulse-pins {
        function = "ntr_pulse";
        pins = "gpio11";
      };

      pinctrl_uart1_scts: uart1_scts-pins {
        function = "uart1_scts";
        pins = "gpio12";
      };

      pinctrl_uart1_srts: uart1_srts-pins {
        function = "uart1_srts";
        pins = "gpio13";
      };

      pinctrl_uart1: uart1-pins {
        pinctrl_uart1_sdin: uart1_sdin-pins {
          function = "uart1_sdin";
          pins = "gpio14";
        };

        pinctrl_uart1_sdout: uart1_sdout-pins {
          function = "uart1_sdout";
          pins = "gpio15";
        };
      };

      pinctrl_adsl_spi: adsl_spi-pins {
        pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
          function = "adsl_spi_miso";
          pins = "gpio16";
        };

        pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
          function = "adsl_spi_mosi";
          pins = "gpio17";
        };

        pinctrl_adsl_spi_clk: adsl_spi_clk-pins {
          function = "adsl_spi_clk";
          pins = "gpio18";
        };

        pinctrl_adsl_spi_cs: adsl_spi_cs-pins {
          function = "adsl_spi_cs";
          pins = "gpio19";
        };
      };

      pinctrl_ephy0_led: ephy0_led-pins {
        function = "ephy0_led";
        pins = "gpio20";
      };

      pinctrl_ephy1_led: ephy1_led-pins {
        function = "ephy1_led";
        pins = "gpio21";
      };

      pinctrl_ephy2_led: ephy2_led-pins {
        function = "ephy2_led";
        pins = "gpio22";
      };

      pinctrl_ephy3_led: ephy3_led-pins {
        function = "ephy3_led";
        pins = "gpio23";
      };

      pinctrl_ext_irq0: ext_irq0-pins {
        function = "ext_irq0";
        pins = "gpio24";
      };

      pinctrl_ext_irq1: ext_irq1-pins {
        function = "ext_irq1";
        pins = "gpio25";
      };

      pinctrl_ext_irq2: ext_irq2-pins {
        function = "ext_irq2";
        pins = "gpio26";
      };

      pinctrl_ext_irq3: ext_irq3-pins {
        function = "ext_irq3";
        pins = "gpio27";
      };

      pinctrl_nand: nand-pins {
        function = "nand";
        group = "nand_grp";
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6368-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6368 pin controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description:
  Bindings for Broadcom's BCM6368 memory-mapped pin controller.

properties:
  compatible:
    const: brcm,bcm6368-pinctrl

  reg:
    maxItems: 2

patternProperties:
  '-pins$':
    type: object
    $ref: pinmux-node.yaml#

    properties:
      function:
        enum: [ analog_afe_0, analog_afe_1, sys_irq, serial_led_data,
                serial_led_clk, inet_led, ephy0_led, ephy1_led, ephy2_led,
                ephy3_led, robosw_led_data, robosw_led_clk, robosw_led0,
                robosw_led1, usb_device_led, pci_req1, pci_gnt1, pci_intb,
                pci_req0, pci_gnt0, pcmcia_cd1, pcmcia_cd2, pcmcia_vs1,
                pcmcia_vs2, ebi_cs2, ebi_cs3, spi_cs2, spi_cs3, spi_cs4,
                spi_cs5, uart1 ]

      pins:
        enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
                gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,
                gpio16, gpio17, gpio18, gpio19, gpio20, gpio22, gpio23,
                gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30,
                gpio31, uart1_grp ]

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pinctrl@18 {
      compatible = "brcm,bcm6368-pinctrl";
      reg = <0x18 0x4>, <0x38 0x4>;

      pinctrl_analog_afe_0: analog_afe_0-pins {
        function = "analog_afe_0";
        pins = "gpio0";
      };

      pinctrl_analog_afe_1: analog_afe_1-pins {
        function = "analog_afe_1";
        pins = "gpio1";
      };

      pinctrl_sys_irq: sys_irq-pins {
        function = "sys_irq";
        pins = "gpio2";
      };

      pinctrl_serial_led: serial_led-pins {
        pinctrl_serial_led_data: serial_led_data-pins {
          function = "serial_led_data";
          pins = "gpio3";
        };

        pinctrl_serial_led_clk: serial_led_clk-pins {
          function = "serial_led_clk";
          pins = "gpio4";
        };
      };

      pinctrl_inet_led: inet_led-pins {
        function = "inet_led";
        pins = "gpio5";
      };

      pinctrl_ephy0_led: ephy0_led-pins {
        function = "ephy0_led";
        pins = "gpio6";
      };

      pinctrl_ephy1_led: ephy1_led-pins {
        function = "ephy1_led";
        pins = "gpio7";
      };

      pinctrl_ephy2_led: ephy2_led-pins {
        function = "ephy2_led";
        pins = "gpio8";
      };

      pinctrl_ephy3_led: ephy3_led-pins {
        function = "ephy3_led";
        pins = "gpio9";
      };

      pinctrl_robosw_led_data: robosw_led_data-pins {
        function = "robosw_led_data";
        pins = "gpio10";
      };

      pinctrl_robosw_led_clk: robosw_led_clk-pins {
        function = "robosw_led_clk";
        pins = "gpio11";
      };

      pinctrl_robosw_led0: robosw_led0-pins {
        function = "robosw_led0";
        pins = "gpio12";
      };

      pinctrl_robosw_led1: robosw_led1-pins {
        function = "robosw_led1";
        pins = "gpio13";
      };

      pinctrl_usb_device_led: usb_device_led-pins {
        function = "usb_device_led";
        pins = "gpio14";
      };

      pinctrl_pci: pci-pins {
        pinctrl_pci_req1: pci_req1-pins {
          function = "pci_req1";
          pins = "gpio16";
        };

        pinctrl_pci_gnt1: pci_gnt1-pins {
          function = "pci_gnt1";
          pins = "gpio17";
        };

        pinctrl_pci_intb: pci_intb-pins {
          function = "pci_intb";
          pins = "gpio18";
        };

        pinctrl_pci_req0: pci_req0-pins {
          function = "pci_req0";
          pins = "gpio19";
        };

        pinctrl_pci_gnt0: pci_gnt0-pins {
          function = "pci_gnt0";
          pins = "gpio20";
        };
      };

      pinctrl_pcmcia: pcmcia-pins {
        pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
          function = "pcmcia_cd1";
          pins = "gpio22";
        };

        pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
          function = "pcmcia_cd2";
          pins = "gpio23";
        };

        pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
          function = "pcmcia_vs1";
          pins = "gpio24";
        };

        pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
          function = "pcmcia_vs2";
          pins = "gpio25";
        };
      };

      pinctrl_ebi_cs2: ebi_cs2-pins {
        function = "ebi_cs2";
        pins = "gpio26";
      };

      pinctrl_ebi_cs3: ebi_cs3-pins {
        function = "ebi_cs3";
        pins = "gpio27";
      };

      pinctrl_spi_cs2: spi_cs2-pins {
        function = "spi_cs2";
        pins = "gpio28";
      };

      pinctrl_spi_cs3: spi_cs3-pins {
        function = "spi_cs3";
        pins = "gpio29";
      };

      pinctrl_spi_cs4: spi_cs4-pins {
        function = "spi_cs4";
        pins = "gpio30";
      };

      pinctrl_spi_cs5: spi_cs5-pins {
        function = "spi_cs5";
        pins = "gpio31";
      };

      pinctrl_uart1: uart1-pins {
        function = "uart1";
        group = "uart1_grp";
      };
    };


code:
Broadcom Cygnus IOMUX Controller

The Cygnus IOMUX controller supports group based mux configuration. In
addition, certain pins can be muxed to GPIO function individually.

Required properties:

- compatible:
    Must be "brcm,cygnus-pinmux"

- reg:
    Define the base and range of the I/O address space that contains the Cygnus
IOMUX registers

Properties in subnodes:

- function:
    The mux function to select

- groups:
    The list of groups to select with a given function

For more details, refer to
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

For example:

	pinmux: pinmux@0301d0c8 {
		compatible = "brcm,cygnus-pinmux";
		reg = <0x0301d0c8 0x1b0>;

		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_default>;

		i2s0_default: i2s0_default {
			mux {
				function = "i2s0";
				groups = "i2s0_0_grp", "i2s0_1_grp";
			};
		};
	};

List of supported functions and groups in Cygnus:

"i2s0": "i2s0_0_grp", "i2s0_1_grp"

"i2s1": "i2s1_0_grp", "i2s1_1_grp"

"i2s2": "i2s2_0_grp", "i2s2_1_grp", "i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp"

"spdif": "spdif_grp"

"pwm0": "pwm0_grp"

"pwm1": "pwm1_grp"

"pwm2": "pwm2_grp"

"pwm3": "pwm3_grp"

"pwm4": "pwm4_grp"

"pwm5": "pwm5_grp"

"key": "key0_grp", "key1_grp", "key2_grp", "key3_grp", "key4_grp", "key5_grp",
"key6_grp", "key7_grp", "key8_grp", "key9_grp", "key10_grp", "key11_grp",
"key12_grp", "key13_grp", "key14_grp", "key15_grp"

"audio_dte": "audio_dte0_grp", "audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp"

"smart_card0": "smart_card0_grp", "smart_card0_fcb_grp"

"smart_card1": "smart_card1_grp", "smart_card1_fcb_grp"

"spi0": "spi0_grp"

"spi1": "spi1_grp"

"spi2": "spi2_grp"

"spi3": "spi3_grp"

"spi4": "spi4_0_grp", "spi4_1_grp"

"spi5": "spi5_grp"

"sw_led0": "sw_led0_0_grp", "sw_led0_1_grp"

"sw_led1": "sw_led1_grp"

"sw_led2": "sw_led2_0_grp", "sw_led2_1_grp"

"d1w": "d1w_grp"

"lcd": "lcd_grp"

"sram": "sram_0_grp", "sram_1_grp"

"uart0": "uart0_grp"

"uart1": "uart1_grp", "uart1_dte_grp"

"uart2": "uart2_grp"

"uart3": "uart3_grp"

"uart4": "uart4_grp"

"qspi": "qspi_0_grp", "qspi_1_grp"

"nand": "nand_grp"

"sdio0": "sdio0_grp", "sdio0_cd_grp", "sdio0_mmc_grp"

"sdio1": "sdio1_data_0_grp", "sdio1_data_1_grp", "sdio1_cd_grp",
"sdio1_led_grp", "sdio1_mmc_grp"

"can0": "can0_grp"

"can1": "can1_grp"

"cam": "cam_led_grp", "cam_0_grp", "cam_1_grp"

"bsc1": "bsc1_grp"

"pcie_clkreq": "pcie_clkreq_grp"

"usb0_oc": "usb0_oc_grp"

"usb1_oc": "usb1_oc_grp"

"usb2_oc": "usb2_oc_grp"


code:
Broadcom iProc GPIO/PINCONF Controller

Required properties:

- compatible:
    "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
    supports full-featured pinctrl and GPIO functions used in various iProc
    based SoCs

    May contain an SoC-specific compatibility string to accommodate any
    SoC-specific features

    "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
    "brcm,cygnus-crmu-gpio" for Cygnus SoCs

    "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
    disabled

    "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
    pinctrl support completely disabled in this IP block. In Stingray, a
    different IP block is used to handle pinctrl related functions

- reg:
    Define the base and range of the I/O address space that contains SoC
GPIO/PINCONF controller registers

- ngpios:
    Total number of in-use slots in GPIO controller

- #gpio-cells:
    Must be two. The first cell is the GPIO pin number (within the
controller's pin space) and the second cell is used for the following:
    bit[0]: polarity (0 for active high and 1 for active low)

- gpio-controller:
    Specifies that the node is a GPIO controller

Optional properties:

- interrupts:
    Interrupt ID

- interrupt-controller:
    Specifies that the node is an interrupt controller

- gpio-ranges:
    Specifies the mapping between gpio controller and pin-controllers pins.
    This requires 4 fields in cells defined as -
    1. Phandle of pin-controller.
    2. GPIO base pin offset.
    3  Pin-control base pin offset.
    4. number of gpio pins which are linearly mapped from pin base.

Supported generic PINCONF properties in child nodes:

- pins:
    The list of pins (within the controller's own pin space) that properties
in the node apply to. Pin names are "gpio-<pin>"

- bias-disable:
    Disable pin bias

- bias-pull-up:
    Enable internal pull up resistor

- bias-pull-down:
    Enable internal pull down resistor

- drive-strength:
    Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA)

Example:
	gpio_ccm: gpio@1800a000 {
		compatible = "brcm,cygnus-ccm-gpio";
		reg = <0x1800a000 0x50>,
		      <0x0301d164 0x20>;
		ngpios = <24>;
		#gpio-cells = <2>;
		gpio-controller;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;

		touch_pins: touch_pins {
			pwr: pwr {
				pins = "gpio-0";
				drive-strength = <16>;
			};

			event: event {
				pins = "gpio-1";
				bias-pull-up;
			};
		};
	};

	gpio_asiu: gpio@180a5000 {
		compatible = "brcm,cygnus-asiu-gpio";
		reg = <0x180a5000 0x668>;
		ngpios = <146>;
		#gpio-cells = <2>;
		gpio-controller;
		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		gpio-ranges = <&pinctrl 0 42 1>,
				<&pinctrl 1 44 3>;
	};

	/*
	 * Touchscreen that uses the CCM GPIO 0 and 1
	 */
	tsc {
		...
		...
		gpio-pwr = <&gpio_ccm 0 0>;
		gpio-event = <&gpio_ccm 1 0>;
	};

	/* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */
	bluetooth {
		...
		...
		bcm,rfkill-bank-sel = <&gpio_asiu 5 1>
	}


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Northstar pins mux controller

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

description:
  Some of Northstar SoCs's pins can be used for various purposes thanks to the
  mux controller. This binding allows describing mux controller and listing
  available functions. They can be referenced later by other bindings to let
  system configure controller correctly.

  A list of pins varies across chipsets so few bindings are available.

properties:
  compatible:
    enum:
      - brcm,bcm4708-pinmux
      - brcm,bcm4709-pinmux
      - brcm,bcm53012-pinmux

  reg:
    maxItems: 1

  reg-names:
    const: cru_gpio_control

patternProperties:
  '-pins$':
    type: object
    description: pin node
    $ref: pinmux-node.yaml#

    properties:
      function:
        enum: [ spi, i2c, pwm, uart1, mdio, uart2, sdio ]
      groups:
        minItems: 1
        maxItems: 4
        items:
          enum: [ spi_grp, i2c_grp, pwm0_grp, pwm1_grp, pwm2_grp, pwm3_grp,
                  uart1_grp, mdio_grp, uart2_grp, sdio_pwr_grp, sdio_1p8v_grp ]

    required:
      - function
      - groups

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"
  - if:
      properties:
        compatible:
          contains:
            const: brcm,bcm4708-pinmux
    then:
      patternProperties:
        '-pins$':
          properties:
            function:
              enum: [ spi, i2c, pwm, uart1 ]
            groups:
              items:
                enum: [ spi_grp, i2c_grp, pwm0_grp, pwm1_grp, pwm2_grp, pwm3_grp,
                        uart1_grp ]

required:
  - reg
  - reg-names

additionalProperties: false

examples:
  - |
    pinctrl@1800c1c0 {
        compatible = "brcm,bcm4708-pinmux";
        reg = <0x1800c1c0 0x24>;
        reg-names = "cru_gpio_control";

        spi-pins {
            function = "spi";
            groups = "spi_grp";
        };
    };


code:
Broadcom Northstar2 IOMUX Controller

The Northstar2 IOMUX controller supports group based mux configuration. There
are some individual pins that support modifying the pinconf parameters.

Required properties:

- compatible:
    Must be "brcm,ns2-pinmux"

- reg:
    Define the base and range of the I/O address space that contains the
    Northstar2 IOMUX and pin configuration registers.

Properties in sub nodes:

- function:
    The mux function to select

- groups:
    The list of groups to select with a given function

- pins:
    List of pin names to change configuration

The generic properties bias-disable, bias-pull-down, bias-pull-up,
drive-strength, slew-rate, input-enable, input-disable are supported
for some individual pins listed at the end.

For more details, refer to
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

For example:

	pinctrl: pinctrl@6501d130 {
		compatible = "brcm,ns2-pinmux";
		reg = <0x6501d130 0x08>,
		      <0x660a0028 0x04>,
		      <0x660009b0 0x40>;

		pinctrl-names = "default";
		pinctrl-0 = <&nand_sel>, <&uart3_rx>, <&sdio0_d4>;

		/* Select nand function */
		nand_sel: nand_sel {
			function = "nand";
			groups = "nand_grp";
		};

		/* Pull up the uart3 rx pin */
		uart3_rx: uart3_rx {
			pins = "uart3_sin";
			bias-pull-up;
		};

		/* Set the drive strength of sdio d4 pin */
		sdio0_d4: sdio0_d4 {
			pins = "sdio0_data4";
			drive-strength = <8>;
		};
	};

List of supported functions and groups in Northstar2:

"nand": "nand_grp"

"nor": "nor_data_grp", "nor_adv_grp", "nor_addr_0_3_grp", "nor_addr_4_5_grp",
	"nor_addr_6_7_grp", "nor_addr_8_9_grp", "nor_addr_10_11_grp",
	"nor_addr_12_15_grp"

"gpio": "gpio_0_1_grp", "gpio_2_5_grp", "gpio_6_7_grp", "gpio_8_9_grp",
	"gpio_10_11_grp", "gpio_12_13_grp", "gpio_14_17_grp", "gpio_18_19_grp",
	"gpio_20_21_grp", "gpio_22_23_grp", "gpio_24_25_grp", "gpio_26_27_grp",
	"gpio_28_29_grp", "gpio_30_31_grp"

"pcie": "pcie_ab1_clk_wak_grp", "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp",
	"pcie_b2_clk_wak_grp", "pcie_a2_clk_wak_grp"

"uart0": "uart0_modem_grp", "uart0_rts_cts_grp", "uart0_in_out_grp"

"uart1": "uart1_ext_clk_grp", "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp",
	"uart1_rts_cts_grp", "uart1_in_out_grp"

"uart2": "uart2_rts_cts_grp"

"pwm": "pwm_0_grp", "pwm_1_grp", "pwm_2_grp", "pwm_3_grp"

List of pins that support pinconf parameters:

"qspi_wp", "qspi_hold", "qspi_cs", "qspi_sck", "uart3_sin", "uart3_sout",
"qspi_mosi", "qspi_miso", "spi0_fss", "spi0_rxd", "spi0_txd", "spi0_sck",
"spi1_fss", "spi1_rxd", "spi1_txd", "spi1_sck", "sdio0_data7",
"sdio0_emmc_rst", "sdio0_led_on", "sdio0_wp", "sdio0_data3", "sdio0_data4",
"sdio0_data5", "sdio0_data6", "sdio0_cmd", "sdio0_data0", "sdio0_data1",
"sdio0_data2", "sdio1_led_on", "sdio1_wp", "sdio0_cd_l", "sdio0_clk",
"sdio1_data5", "sdio1_data6", "sdio1_data7", "sdio1_emmc_rst", "sdio1_data1",
"sdio1_data2", "sdio1_data3", "sdio1_data4", "sdio1_cd_l", "sdio1_clk",
"sdio1_cmd", "sdio1_data0", "ext_mdio_0", "ext_mdc_0", "usb3_p1_vbus_ppc",
"usb3_p1_overcurrent", "usb3_p0_vbus_ppc", "usb3_p0_overcurrent",
"usb2_presence_indication", "usb2_vbus_present", "usb2_vbus_ppc",
"usb2_overcurrent", "sata_led1", "sata_led0"


code:
Broadcom Northstar plus (NSP) GPIO/PINCONF Controller

Required properties:
- compatible:
    Must be "brcm,nsp-gpio-a"

- reg:
    Should contain the register physical address and length for each of
    GPIO base, IO control registers

- #gpio-cells:
    Must be two. The first cell is the GPIO pin number (within the
    controller's pin space) and the second cell is used for the following:
    bit[0]: polarity (0 for active high and 1 for active low)

- gpio-controller:
    Specifies that the node is a GPIO controller

- ngpios:
    Number of gpios supported (58x25 supports 32 and 58x23 supports 24)

Optional properties:
- interrupts:
    Interrupt ID

- interrupt-controller:
    Specifies that the node is an interrupt controller

- gpio-ranges:
    Specifies the mapping between gpio controller and pin-controllers pins.
    This requires 4 fields in cells defined as -
    1. Phandle of pin-controller.
    2. GPIO base pin offset.
    3  Pin-control base pin offset.
    4. number of gpio pins which are linearly mapped from pin base.

Supported generic PINCONF properties in child nodes:
- pins:
    The list of pins (within the controller's own pin space) that properties
    in the node apply to. Pin names are "gpio-<pin>"

- bias-disable:
    Disable pin bias

- bias-pull-up:
    Enable internal pull up resistor

- bias-pull-down:
    Enable internal pull down resistor

- drive-strength:
    Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA)

Example:

	gpioa: gpio@18000020 {
		compatible = "brcm,nsp-gpio-a";
		reg = <0x18000020 0x100>,
		      <0x1803f1c4 0x1c>;
		#gpio-cells = <2>;
		gpio-controller;
		ngpios = <32>;
		gpio-ranges = <&pinctrl 0 0 31>;
		interrupt-controller;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

		/* Hog a few default settings */
		pinctrl-names = "default";
		pinctrl-0 = <&led>;
		led: led {
			pins = "gpio-1";
			bias-pull-up;
		};

		pwr: pwr {
			gpio-hog;
			gpios = <3 1>;
			output-high;
		};
	};


code:
Broadcom NSP (Northstar plus) IOMUX Controller

The NSP IOMUX controller supports group based mux configuration. In
addition, certain pins can be muxed to GPIO function individually.

Required properties:
- compatible:
    Must be "brcm,nsp-pinmux"

- reg:
    Should contain the register physical address and length for each of
    GPIO_CONTROL0, GP_AUX_SEL and IPROC_CONFIG IOMUX registers

Properties in subnodes:
- function:
    The mux function to select

- groups:
    The list of groups to select with a given function

For more details, refer to
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

For example:

	pinmux: pinmux@1803f1c0 {
		compatible = "brcm,nsp-pinmux";
		reg = <0x1803f1c0 0x04>,
		      <0x18030028 0x04>,
		      <0x1803f408 0x04>;

		pinctrl-names = "default";
		pinctrl-0 = <&pwm>, <&gpio_b>, <&nand_sel>;

		pwm: pwm {
			function = "pwm";
			groups = "pwm0_grp", "pwm1_grp";
		};

		gpio_b: gpio_b {
			function = "gpio_b";
			groups = "gpio_b_0_grp", "gpio_b_1_grp";
		};

		nand_sel: nand_sel {
			function = "nand";
			groups = "nand_grp";
		};
	};

List of supported functions and groups in Northstar Plus:

"spi": "spi_grp"

"i2c": "i2c_grp"

"mdio": "mdio_grp"

"pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"

"gpio_b": "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", "gpio_b_3_grp"

"uart1": "uart1_grp"

"uart2": "uart2_grp"

"synce": "synce_grp"

"sata_led_grps": "sata0_led_grp", "sata1_led_grp"

"xtal_out": "xtal_out_grp"

"sdio": "sdio_pwr_grp", "sdio_1p8v_grp"

"switch_led": "switch_p05_led0_grp", "switch_p05_led1_grp"

"nand": "nand_grp"

"emmc": "emmc_grp"


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Canaan Kendryte K210 FPIOA

maintainers:
  - Damien Le Moal <damien.lemoal@wdc.com>

description:
  The Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA)
  controller allows assiging any of 256 possible functions to any of
  48 IO pins of the SoC. Pin function configuration is performed on
  a per-pin basis.

properties:
  compatible:
    const: canaan,k210-fpioa

  reg:
    maxItems: 1
    description:
      Address and length of the register set for the FPIOA controller.

  clocks:
    items:
      - description: Controller reference clock source
      - description: APB interface clock source

  clock-names:
    items:
      - const: ref
      - const: pclk

  resets:
    maxItems: 1

  canaan,k210-sysctl-power:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle of the K210 system controller node
          - description: offset of its power domain control register
    description: |
      phandle of the K210 system controller node and offset of its
      power domain control register.

patternProperties:
  '-pinmux$':
    type: object
    $ref: /schemas/pinctrl/pinmux-node.yaml
    description:
      FPIOA client devices use sub-nodes to define the desired pin
      configuration. Client device sub-nodes use the pinux property
      below.

    properties:
      pinmux:
        description:
          List of IO pins alternate functions. The values for each IO
          pin is a combination of an IO pin number (0 to 47) with the
          desired function for the IO pin. Functions are defined as
          macros in include/dt-bindings/pinctrl/k210-fpioa.h.
          The K210_FPIOA(IO pin, function) macro is provided to
          facilitate the combination of IO pin numbers and functions.

    required:
      - pinmux

    additionalProperties: false

  '-pins$':
    type: object
    $ref: /schemas/pinctrl/pincfg-node.yaml
    description:
      FPIOA client devices use sub-nodes to define the desired
      configuration of pins. Client device sub-nodes use the
      properties below.

    properties:
      pins:
        description:
          List of IO pins affected by the properties specified in this
          subnode. IO pins are identified using the pin names "IO_xx".
          Pin configuration nodes can also define the power domain to
          be used for the SoC pin groups A0 (IO pins 0-5),
          A1 (IO pins 6-11), A2 (IO pins 12-17), B0 (IO pins 18-23),
          B1 (IO pins 24-29), B2 (IO pins 30-35), B3 (IO pins 30-35),
          C0 (IO pins 36-41) and C1 (IO pins 42-47) using the
          power-source property.
        items:
          anyOf:
            - pattern: "^(IO_([0-9]*))|(A[0-2])|(B[3-5])|(C[6-7])$"
            - enum: [ IO_0, IO_1, IO_2, IO_3, IO_4, IO_5, IO_6, IO_7,
                      IO_8, IO_9, IO_10, IO_11, IO_12, IO_13, IO_14,
                      IO_15, IO_16, IO_17, IO_18, IO_19, IO_20, IO_21,
                      IO_22, IO_23, IO_24, IO_25, IO_26, IO_27, IO_28,
                      IO_29, IO_30, IO_31, IO_32, IO_33, IO_34, IO_35,
                      IO_36, IO_37, IO_38, IO_39, IO_40, IO_41, IO_42,
                      IO_43, IO_44, IO_45, IO_46, IO_47,
                      A0, A1, A2, B3, B4, B5, C6, C7 ]
      bias-disable: true

      bias-pull-down: true

      bias-pull-up: true

      drive-strength: true

      drive-strength-microamp: true

      input-enable: true

      input-disable: true

      input-schmitt-enable: true

      input-schmitt-disable: true

      input-polarity-invert:
        type: boolean
        description:
          Enable or disable pin input polarity inversion.

      output-enable: true

      output-disable: true

      output-high: true

      output-low: true

      output-polarity-invert:
        type: boolean
        description:
          Enable or disable pin output polarity inversion.

      slew-rate: true

      power-source: true

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - clocks
  - canaan,k210-sysctl-power

additionalProperties: false

examples:
  - |
    #include <dt-bindings/pinctrl/k210-fpioa.h>
    #include <dt-bindings/clock/k210-clk.h>
    #include <dt-bindings/reset/k210-rst.h>

    fpioa: pinmux@502b0000 {
      compatible = "canaan,k210-fpioa";
      reg = <0x502b0000 0x100>;
      clocks = <&sysclk K210_CLK_FPIOA>,
               <&sysclk K210_CLK_APB0>;
      clock-names = "ref", "pclk";
      resets = <&sysrst K210_RST_FPIOA>;
      canaan,k210-sysctl-power = <&sysctl 108>;
      pinctrl-0 = <&jtag_pinctrl>;
      pinctrl-names = "default";

      jtag_pinctrl: jtag-pinmux {
        pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>,
                 <K210_FPIOA(1, K210_PCF_JTAG_TDI)>,
                 <K210_FPIOA(2, K210_PCF_JTAG_TMS)>,
                 <K210_FPIOA(3, K210_PCF_JTAG_TDO)>;
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/cirrus,lochnagar.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cirrus Logic Lochnagar Audio Development Board

maintainers:
  - patches@opensource.cirrus.com

description: |
  Lochnagar is an evaluation and development board for Cirrus Logic
  Smart CODEC and Amp devices. It allows the connection of most Cirrus
  Logic devices on mini-cards, as well as allowing connection of various
  application processor systems to provide a full evaluation platform.
  Audio system topology, clocking and power can all be controlled through
  the Lochnagar, allowing the device under test to be used in a variety of
  possible use cases.

  This binding document describes the binding for the pinctrl portion of
  the driver.

  Also see these documents for generic binding information:
    [1] GPIO : ../gpio/gpio.txt
    [2] Pinctrl: ../pinctrl/pinctrl-bindings.txt

  And these for relevant defines:
    [3] include/dt-bindings/pinctrl/lochnagar.h

  This binding must be part of the Lochnagar MFD binding:
    [4] ../mfd/cirrus,lochnagar.yaml

properties:
  compatible:
    enum:
      - cirrus,lochnagar-pinctrl

  gpio-controller: true

  '#gpio-cells':
    description:
      The first cell is the pin number and the second cell is used
      to specify optional parameters.
    const: 2

  gpio-ranges:
    description:
      Range of pins managed by the GPIO controller, see [1]. Both the
      GPIO and Pinctrl base should be set to zero and the count to the
      appropriate of the LOCHNAGARx_PIN_NUM_GPIOS define, see [3].
    maxItems: 1

  pin-settings:
    type: object
    patternProperties:
      '-pins$':
        description:
          The pin configurations are defined as a child of the pinctrl
          states node, see [2]. Each sub-node can have the following
          properties.
        type: object
        allOf:
          - $ref: pincfg-node.yaml#
          - $ref: pinmux-node.yaml#

        properties:
          groups:
            description:
              A list of groups to select (either this or "pins" must be
              specified), available groups.
            enum: [ codec-aif1, codec-aif2, codec-aif3, dsp-aif1,
                    dsp-aif2, psia1, psia2, gf-aif1, gf-aif2, gf-aif3,
                    gf-aif4, spdif-aif, usb-aif1, usb-aif2, adat-aif,
                    soundcard-aif ]

          pins:
            description:
              A list of pin names to select (either this or "groups" must
              be specified), available pins.
            enum: [ fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4,
                    fpga-gpio5, fpga-gpio6, codec-gpio1, codec-gpio2,
                    codec-gpio3, codec-gpio4, codec-gpio5, codec-gpio6,
                    codec-gpio7, codec-gpio8, dsp-gpio1, dsp-gpio2,
                    dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6,
                    gf-gpio2, gf-gpio3, gf-gpio7, codec-aif1-bclk,
                    codec-aif1-rxdat, codec-aif1-lrclk, codec-aif1-txdat,
                    codec-aif2-bclk, codec-aif2-rxdat, codec-aif2-lrclk,
                    codec-aif2-txdat, codec-aif3-bclk, codec-aif3-rxdat,
                    codec-aif3-lrclk, codec-aif3-txdat, dsp-aif1-bclk,
                    dsp-aif1-rxdat, dsp-aif1-lrclk, dsp-aif1-txdat,
                    dsp-aif2-bclk, dsp-aif2-rxdat, dsp-aif2-lrclk,
                    dsp-aif2-txdat, psia1-bclk, psia1-rxdat, psia1-lrclk,
                    psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk,
                    psia2-txdat, gf-aif3-bclk, gf-aif3-rxdat,
                    gf-aif3-lrclk, gf-aif3-txdat, gf-aif4-bclk,
                    gf-aif4-rxdat, gf-aif4-lrclk, gf-aif4-txdat,
                    gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk,
                    gf-aif1-txdat, gf-aif2-bclk, gf-aif2-rxdat,
                    gf-aif2-lrclk, gf-aif2-txdat, dsp-uart1-rx,
                    dsp-uart1-tx, dsp-uart2-rx, dsp-uart2-tx,
                    gf-uart2-rx, gf-uart2-tx, usb-uart-rx, codec-pdmclk1,
                    codec-pdmdat1, codec-pdmclk2, codec-pdmdat2,
                    codec-dmicclk1, codec-dmicdat1, codec-dmicclk2,
                    codec-dmicdat2, codec-dmicclk3, codec-dmicdat3,
                    codec-dmicclk4, codec-dmicdat4, dsp-dmicclk1,
                    dsp-dmicdat1, dsp-dmicclk2, dsp-dmicdat2, i2c2-scl,
                    i2c2-sda, i2c3-scl, i2c3-sda, i2c4-scl, i2c4-sda,
                    dsp-standby, codec-mclk1, codec-mclk2, dsp-clkin,
                    psia1-mclk, psia2-mclk, gf-gpio1, gf-gpio5,
                    dsp-gpio20, led1, led2 ]

          function:
            description:
              The mux function to select, available functions.
            enum: [ aif, fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4,
                    fpga-gpio5, fpga-gpio6, codec-gpio1, codec-gpio2,
                    codec-gpio3, codec-gpio4, codec-gpio5, codec-gpio6,
                    codec-gpio7, codec-gpio8, dsp-gpio1, dsp-gpio2,
                    dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6,
                    gf-gpio2, gf-gpio3, gf-gpio7, gf-gpio1, gf-gpio5,
                    dsp-gpio20, codec-clkout, dsp-clkout, pmic-32k,
                    spdif-clkout, clk-12m288, clk-11m2986, clk-24m576,
                    clk-22m5792, xmos-mclk, gf-clkout1, gf-mclk1,
                    gf-mclk3, gf-mclk2, gf-clkout2, codec-mclk1,
                    codec-mclk2, dsp-clkin, psia1-mclk, psia2-mclk,
                    spdif-mclk, codec-irq, codec-reset, dsp-reset,
                    dsp-irq, dsp-standby, codec-pdmclk1, codec-pdmdat1,
                    codec-pdmclk2, codec-pdmdat2, codec-dmicclk1,
                    codec-dmicdat1, codec-dmicclk2, codec-dmicdat2,
                    codec-dmicclk3, codec-dmicdat3, codec-dmicclk4,
                    codec-dmicdat4, dsp-dmicclk1, dsp-dmicdat1,
                    dsp-dmicclk2, dsp-dmicdat2, dsp-uart1-rx,
                    dsp-uart1-tx, dsp-uart2-rx, dsp-uart2-tx,
                    gf-uart2-rx, gf-uart2-tx, usb-uart-rx, usb-uart-tx,
                    i2c2-scl, i2c2-sda, i2c3-scl, i2c3-sda, i2c4-scl,
                    i2c4-sda, spdif-aif, psia1, psia1-bclk, psia1-lrclk,
                    psia1-rxdat, psia1-txdat, psia2, psia2-bclk,
                    psia2-lrclk, psia2-rxdat, psia2-txdat, codec-aif1,
                    codec-aif1-bclk, codec-aif1-lrclk, codec-aif1-rxdat,
                    codec-aif1-txdat, codec-aif2, codec-aif2-bclk,
                    codec-aif2-lrclk, codec-aif2-rxdat, codec-aif2-txdat,
                    codec-aif3, codec-aif3-bclk, codec-aif3-lrclk,
                    codec-aif3-rxdat, codec-aif3-txdat, dsp-aif1,
                    dsp-aif1-bclk, dsp-aif1-lrclk, dsp-aif1-rxdat,
                    dsp-aif1-txdat, dsp-aif2, dsp-aif2-bclk,
                    dsp-aif2-lrclk, dsp-aif2-rxdat, dsp-aif2-txdat,
                    gf-aif3, gf-aif3-bclk, gf-aif3-lrclk, gf-aif3-rxdat,
                    gf-aif3-txdat, gf-aif4, gf-aif4-bclk, gf-aif4-lrclk,
                    gf-aif4-rxdat, gf-aif4-txdat, gf-aif1, gf-aif1-bclk,
                    gf-aif1-lrclk, gf-aif1-rxdat, gf-aif1-txdat, gf-aif2,
                    gf-aif2-bclk, gf-aif2-lrclk, gf-aif2-rxdat,
                    gf-aif2-txdat, usb-aif1, usb-aif2, adat-aif,
                    soundcard-aif ]

          output-enable:
            description:
              Specifies that an AIF group will be used as a master
              interface (either this or input-enable is required if a
              group is being muxed to an AIF)

          input-enable:
            description:
              Specifies that an AIF group will be used as a slave
              interface (either this or output-enable is required if a
              group is being muxed to an AIF)

        additionalProperties: false

        required:
          - function

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges
  - pinctrl-0
  - pinctrl-names

additionalProperties: false