code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

/dts-v1/;

#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp.dtsi"

/ {
	model = "NXP i.MX8MPlus EVK board";
	compatible = "fsl,imx8mp-evk", "fsl,imx8mp";

	chosen {
		stdout-path = &uart2;
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_led>;

		status {
			label = "yellow:status";
			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0xc0000000>,
		      <0x1 0x00000000 0 0xc0000000>;
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <100000000>;
	};

	reg_can1_stby: regulator-can1-stby {
		compatible = "regulator-fixed";
		regulator-name = "can1-stby";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_flexcan1_reg>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_can2_stby: regulator-can2-stby {
		compatible = "regulator-fixed";
		regulator-name = "can2-stby";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_flexcan2_reg>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_pcie0: regulator-pcie {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pcie0_reg>;
		regulator-name = "MPCIE_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <80000000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
	};
};

&A53_0 {
	cpu-supply = <&reg_arm>;
};

&A53_1 {
	cpu-supply = <&reg_arm>;
};

&A53_2 {
	cpu-supply = <&reg_arm>;
};

&A53_3 {
	cpu-supply = <&reg_arm>;
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	snps,force_thresh_dma_mode;
	snps,mtl-tx-config = <&mtl_tx_setup>;
	snps,mtl-rx-config = <&mtl_rx_setup>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			eee-broken-1000t;
			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			reset-deassert-us = <80000>;
			realtek,clkout-disable;
		};
	};

	mtl_tx_setup: tx-queues-config {
		snps,tx-queues-to-use = <5>;
		snps,tx-sched-sp;

		queue0 {
			snps,dcb-algorithm;
			snps,priority = <0x1>;
		};

		queue1 {
			snps,dcb-algorithm;
			snps,priority = <0x2>;
		};

		queue2 {
			snps,dcb-algorithm;
			snps,priority = <0x4>;
		};

		queue3 {
			snps,dcb-algorithm;
			snps,priority = <0x8>;
		};

		queue4 {
			snps,dcb-algorithm;
			snps,priority = <0xf0>;
		};
	};

	mtl_rx_setup: rx-queues-config {
		snps,rx-queues-to-use = <5>;
		snps,rx-sched-sp;

		queue0 {
			snps,dcb-algorithm;
			snps,priority = <0x1>;
			snps,map-to-dma-channel = <0>;
		};

		queue1 {
			snps,dcb-algorithm;
			snps,priority = <0x2>;
			snps,map-to-dma-channel = <1>;
		};

		queue2 {
			snps,dcb-algorithm;
			snps,priority = <0x4>;
			snps,map-to-dma-channel = <2>;
		};

		queue3 {
			snps,dcb-algorithm;
			snps,priority = <0x8>;
			snps,map-to-dma-channel = <3>;
		};

		queue4 {
			snps,dcb-algorithm;
			snps,priority = <0xf0>;
			snps,map-to-dma-channel = <4>;
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			eee-broken-1000t;
			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			reset-deassert-us = <80000>;
			realtek,clkout-disable;
		};
	};
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can1_stby>;
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can2_stby>;
	status = "disabled";/* can2 pin conflict with pdm */
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@25 {
		compatible = "nxp,pca9450c";
		reg = <0x25>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			BUCK1 {
				regulator-name = "BUCK1";
				regulator-min-microvolt = <720000>;
				regulator-max-microvolt = <1000000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			reg_arm: BUCK2 {
				regulator-name = "BUCK2";
				regulator-min-microvolt = <720000>;
				regulator-max-microvolt = <1025000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
				nxp,dvs-run-voltage = <950000>;
				nxp,dvs-standby-voltage = <850000>;
			};

			BUCK4 {
				regulator-name = "BUCK4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3600000>;
				regulator-boot-on;
				regulator-always-on;
			};

			BUCK5 {
				regulator-name = "BUCK5";
				regulator-min-microvolt = <1650000>;
				regulator-max-microvolt = <1950000>;
				regulator-boot-on;
				regulator-always-on;
			};

			BUCK6 {
				regulator-name = "BUCK6";
				regulator-min-microvolt = <1045000>;
				regulator-max-microvolt = <1155000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO1 {
				regulator-name = "LDO1";
				regulator-min-microvolt = <1650000>;
				regulator-max-microvolt = <1950000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO3 {
				regulator-name = "LDO3";
				regulator-min-microvolt = <1710000>;
				regulator-max-microvolt = <1890000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO5 {
				regulator-name = "LDO5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	pca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pca6416_int>;
		interrupt-parent = <&gpio1>;
		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
		gpio-line-names = "EXT_PWREN1",
			"EXT_PWREN2",
			"CAN1/I2C5_SEL",
			"PDM/CAN2_SEL",
			"FAN_EN",
			"PWR_MEAS_IO1",
			"PWR_MEAS_IO2",
			"EXP_P0_7",
			"EXP_P1_0",
			"EXP_P1_1",
			"EXP_P1_2",
			"EXP_P1_3",
			"EXP_P1_4",
			"EXP_P1_5",
			"EXP_P1_6",
			"EXP_P1_7";
	};
};

/* I2C on expansion connector J22. */
&i2c5 {
	clock-frequency = <100000>; /* Lower clock speed for external bus. */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c5>;
	status = "disabled"; /* can1 pins conflict with i2c5 */

	/* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
	 *     LOW:  CAN1 (default, pull-down)
	 *     HIGH: I2C5
	 * You need to set it to high to enable I2C5 (for example, add gpio-hog
	 * in pca6416 node).
	 */
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	clocks = <&pcie0_refclk>;
	clock-names = "ref";
	status = "okay";
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
		 <&clk IMX8MP_CLK_PCIE_ROOT>,
		 <&clk IMX8MP_CLK_HSIO_AXI>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
	assigned-clock-rates = <10000000>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
	vpcie-supply = <&reg_pcie0>;
	status = "okay";
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "okay";
};

&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "okay";
};

&snvs_pwrkey {
	status = "okay";
};

&uart1 { /* BT */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	uart-has-rtscts;
	status = "okay";
};

&uart2 {
	/* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usb3_phy1 {
	status = "okay";
};

&usb3_1 {
	status = "okay";
};

&usb_dwc3_1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb1_vbus>;
	dr_mode = "host";
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	uart-has-rtscts;
	status = "okay";
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	bus-width = <4>;
	status = "okay";
};

&usdhc3 {
	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22				0x10
		>;
	};

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x2
			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x2
			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90
			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90
			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90
			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90
			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90
			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90
			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16
			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16
			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16
			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16
			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16
			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16
			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x10
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX          0x154
			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX          0x154
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
		>;
	};

	pinctrl_flexcan1_reg: flexcan1reggrp {
		fsl,pins = <
			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154   /* CAN1_STBY */
		>;
	};

	pinctrl_flexcan2_reg: flexcan2reggrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154   /* CAN2_STBY */
		>;
	};

	pinctrl_flexspi0: flexspi0grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2
			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82
			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82
			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82
			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82
			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82
		>;
	};

	pinctrl_gpio_led: gpioledgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x140
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
		>;
	};

	pinctrl_i2c5: i2c5grp {
		fsl,pins = <
			MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA         0x400001c2
			MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c2
		>;
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B	0x60 /* open drain, pull up */
			MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x40
		>;
	};

	pinctrl_pcie0_reg: pcie0reggrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x40
		>;
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x000001c0
		>;
	};

	pinctrl_pca6416_int: pca6416_int_grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x146 /* Input pull-up. */
		>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT	0x116
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT	0x116
		>;
	};

	pinctrl_pwm4: pwm4grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT	0x116
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
			MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS	0x140
			MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS	0x140
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
		>;
	};

	pinctrl_usb1_vbus: usb1grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x10
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140
			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140
			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x140
			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2018 NXP
 * Copyright (c) 2019 Engicam srl
 * Copyright (c) 2020 Amarula Solutions(India)
 */

/dts-v1/;

#include "imx8mp.dtsi"
#include "imx8mp-icore-mx8mp.dtsi"
#include <dt-bindings/usb/pd.h>

/ {
	model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit";
	compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp",
		     "fsl,imx8mp";

	chosen {
		stdout-path = &uart2;
	};

	reg_usb1_vbus: regulator-usb1 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb1>;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "usb1_host_vbus";
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "VSD_3V3";
	};
};

/* Ethernet */
&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-id";
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@7 {
			compatible = "ethernet-phy-ieee802.3-c22";
			micrel,led-mode = <0>;
			reg = <7>;
		};
	};
};

/* console */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usb3_phy0 {
	status = "okay";
};

&usb3_0 {
	status = "okay";
};

&usb_dwc3_0 {
	dr_mode = "host";
	status = "okay";
};

&usb3_phy1 {
	status = "okay";
};

&usb3_1 {
	status = "okay";
};

&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
};

/* SDCARD */
&usdhc2 {
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	pinctrl-names = "default" ;
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&iomuxc {
	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07				0x10
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x40
			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x40
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140
			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140
			MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS	0x140
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
		>;
	};

	pinctrl_reg_usb1: regusb1grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x10
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
		>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2018 NXP
 * Copyright (c) 2019 Engicam srl
 * Copyright (c) 2020 Amarula Solutions(India)
 */

/ {
	compatible = "engicam,icore-mx8mp", "fsl,imx8mp";
};

&A53_0 {
	cpu-supply = <&buck2>;
};

&A53_1 {
	cpu-supply = <&buck2>;
};

&A53_2 {
	cpu-supply = <&buck2>;
};

&A53_3 {
	cpu-supply = <&buck2>;
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pca9450: pmic@25 {
		compatible = "nxp,pca9450c";
		interrupt-parent = <&gpio3>;
		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		reg = <0x25>;

		regulators {
			buck1: BUCK1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <720000>;
				regulator-max-microvolt = <1000000>;
				regulator-name = "BUCK1";
				regulator-ramp-delay = <3125>;
			};

			buck2: BUCK2  {
				nxp,dvs-run-voltage = <950000>;
				nxp,dvs-standby-voltage = <850000>;
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1025000>;
				regulator-min-microvolt = <720000>;
				regulator-name = "BUCK2";
				regulator-ramp-delay = <3125>;
			};

			buck4: BUCK4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3600000>;
				regulator-min-microvolt = <3000000>;
				regulator-name = "BUCK4";
			};

			buck5: BUCK5 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1950000>;
				regulator-min-microvolt = <1650000>;
				regulator-name = "BUCK5";
			};

			buck6: BUCK6 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1155000>;
				regulator-min-microvolt = <1045000>;
				regulator-name = "BUCK6";
			};

			ldo1: LDO1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1950000>;
				regulator-min-microvolt = <1650000>;
				regulator-name = "LDO1";
			};

			ldo3: LDO3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1890000>;
				regulator-min-microvolt = <1710000>;
				regulator-name = "LDO3";
			};

			ldo5: LDO5 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <1800000>;
				regulator-name = "LDO5";
			};
		};
	};
};

/* EMMC */
&usdhc3 {
	bus-width = <8>;
	non-removable;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	status = "okay";
};

&iomuxc {
	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01	  0x41
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022 Avnet Embedded GmbH
 */
/dts-v1/;

#include "imx8mp-msc-sm2s.dtsi"

/ {
	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>; /* bank0, 2GiB */
	};
};

&cpu_alert0 {
	temperature = <95000>;
};

&cpu_crit0 {
	temperature = <105000>;
};

&soc_alert0 {
	temperature = <95000>;
};

&soc_crit0 {
	temperature = <105000>;
};

&tca6424 {
	gbe0-int-hog {
		gpio-hog;
		input;
		gpios = <3 GPIO_ACTIVE_LOW>;
	};

	gbe1-int-hog {
		gpio-hog;
		input;
		gpios = <4 GPIO_ACTIVE_LOW>;
	};

	cam2-rst-hog {
		gpio-hog;
		output-high;
		gpios = <9 GPIO_ACTIVE_LOW>;
	};

	cam2-pwr-hog {
		gpio-hog;
		output-high;
		gpios = <10 GPIO_ACTIVE_LOW>;
	};

	tpm-int-hog {
		gpio-hog;
		input;
		gpios = <13 GPIO_ACTIVE_LOW>;
	};

	wifi-int-hog {
		gpio-hog;
		input;
		gpios = <14 GPIO_ACTIVE_LOW>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022 Avnet Embedded GmbH
 */

/dts-v1/;

#include "imx8mp-msc-sm2s-14N0600E.dtsi"
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "MSC SM2-MB-EP1 Carrier Board with SM2S-IMX8PLUS-QC6-14N0600E SoM";
	compatible = "avnet,sm2s-imx8mp-14N0600E-ep1",
		     "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp",
		     "fsl,imx8mp";
};

&flexcan1 {
	status = "okay";
};

&flexcan2 {
	status = "okay";
};

&usdhc2 {
	no-1-8-v;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_smarc_gpio>;

	pinctrl_smarc_gpio: smarcgpiosgrp {
		fsl,pins =
			<MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x19>, /* GPIO0 */
			<MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x19>, /* GPIO1 */
			<MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02	0x19>, /* GPIO2 */
			<MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03	0x19>, /* GPIO3 */
			<MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x19>, /* GPIO4 */
			<MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x19>, /* GPIO5 */
			<MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x19>, /* GPIO6 */
			<MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x19>, /* GPIO7 */
			<MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x19>, /* GPIO8 */
			<MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x19>, /* GPIO9 */
			<MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x19>, /* GPIO10 */
			<MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x19>, /* GPIO11 */
			<MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x19>, /* GPIO12 */
			<MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00	0x19>; /* GPIO13 */
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022 Avnet Embedded GmbH
 */

/dts-v1/;

#include "imx8mp.dtsi"
#include <dt-bindings/net/ti-dp83867.h>

/ {
	aliases {
		rtc0 = &sys_rtc;
		rtc1 = &snvs_rtc;
	};

	chosen {
		stdout-path = &uart2;
	};

	reg_usb0_host_vbus: regulator-usb0-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb0_host_vbus";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb0_vbus>;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usb1_host_vbus: regulator-usb1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb1_host_vbus";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1_vbus>;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
		off-on-delay-us = <12000>;
	};

	reg_flexcan1_xceiver: regulator-flexcan1 {
		compatible = "regulator-fixed";
		regulator-name = "flexcan1-xceiver";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_flexcan2_xceiver: regulator-flexcan2 {
		compatible = "regulator-fixed";
		regulator-name = "flexcan2-xceiver";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	lcd0_backlight: backlight-0 {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lcd0_backlight>;
		pwms = <&pwm1 0 100000 0>;
		brightness-levels = <0 255>;
		num-interpolated-steps = <255>;
		default-brightness-level = <255>;
		enable-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
		status = "disabled";
	};

	lcd1_backlight: backlight-1 {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lcd1_backlight>;
		pwms = <&pwm2 0 100000 0>;
		brightness-levels = <0 255>;
		num-interpolated-steps = <255>;
		default-brightness-level = <255>;
		enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
		status = "disabled";
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_leds>;
		status = "okay";

		led-sw {
			label = "sw-led";
			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "heartbeat";
		};
	};

	extcon_usb0: extcon-usb0 {
		compatible = "linux,extcon-usb-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb0_extcon>;
		id-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
	};
};

&A53_0 {
	cpu-supply = <&vcc_arm>;
};

&A53_1 {
	cpu-supply = <&vcc_arm>;
};

&A53_2 {
	cpu-supply = <&vcc_arm>;
};

&A53_3 {
	cpu-supply = <&vcc_arm>;
};

&ecspi1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <0>, <&gpio2 8 GPIO_ACTIVE_LOW>;
};

&ecspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	cs-gpios = <0>, <&gpio2 9 GPIO_ACTIVE_LOW>;
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			eee-broken-1000t;
			reset-gpios = <&tca6424 16 GPIO_ACTIVE_LOW>;
			reset-assert-us = <1000>;
			reset-deassert-us = <1000>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			eee-broken-1000t;
			reset-gpios = <&tca6424 17 GPIO_ACTIVE_LOW>;
			reset-assert-us = <1000>;
			reset-deassert-us = <1000>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
		};
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clock-frequency = <400000>;
	status = "okay";

	id_eeprom: eeprom@50 {
		compatible = "atmel,24c64";
		reg = <0x50>;
		pagesize = <32>;
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clock-frequency = <400000>;
	status = "disabled";
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clock-frequency = <400000>;
	status = "disabled";
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	clock-frequency = <400000>;
	status = "disabled";
};

&i2c5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c5>;
	clock-frequency = <400000>;
	status = "disabled";
};

&i2c6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c6>;
	clock-frequency = <400000>;
	status = "okay";

	tca6424: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tca6424>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "BOOT_SEL0#", "BOOT_SEL1#", "BOOT_SEL2#",
			"gbe0_int", "gbe1_int", "pmic_int", "rtc_int", "lvds_int",
			"PCIE_WAKE#", "cam2_rst", "cam2_pwr", "SLEEP#",
			"wifi_pd", "tpm_int", "wifi_int", "PCIE_A_RST#",
			"gbe0_rst", "gbe1_rst", "LID#", "BATLOW#", "CHARGING#",
			"CHARGER_PRSNT#";
		interrupt-parent = <&gpio1>;
		interrupts = <9 IRQ_TYPE_EDGE_RISING>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	dsi_lvds_bridge: bridge@2d {
		compatible = "ti,sn65dsi83";
		reg = <0x2d>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lvds_bridge>;
		enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
		status = "disabled";
	};

	pmic: pmic@30 {
		compatible = "ricoh,rn5t567";
		reg = <0x30>;
		interrupt-parent = <&tca6424>;
		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;

		regulators {
			DCDC1 {
				regulator-name = "VCC_SOC";
				regulator-always-on;
				regulator-min-microvolt = <950000>;
				regulator-max-microvolt = <950000>;
			};

			DCDC2 {
				regulator-name = "VCC_DRAM";
				regulator-always-on;
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
			};

			vcc_arm: DCDC3 {
				regulator-name = "VCC_ARM";
				regulator-always-on;
				regulator-min-microvolt = <950000>;
				regulator-max-microvolt = <950000>;
			};

			DCDC4 {
				regulator-name = "VCC_1V8";
				regulator-always-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};

			LDO1 {
				regulator-name = "VCC_LDO1_2V5";
				regulator-always-on;
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <2500000>;
			};

			LDO2 {
				regulator-name = "VCC_LDO2_1V8";
				regulator-always-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};

			LDO3 {
				regulator-name = "VCC_ETH_2V5";
				regulator-always-on;
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <2500000>;
			};

			LDO4 {
				regulator-name = "VCC_DDR4_2V5";
				regulator-always-on;
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <2500000>;
			};

			LDO5 {
				regulator-name = "VCC_LDO5_1V8";
				regulator-always-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};

			LDORTC1 {
				regulator-name = "VCC_SNVS_1V8";
				regulator-always-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};

			LDORTC2 {
				regulator-name = "VCC_SNVS_3V3";
				regulator-always-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};

	sys_rtc: rtc@32 {
		compatible = "ricoh,r2221tl";
		reg = <0x32>;
		interrupt-parent = <&tca6424>;
		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
	};

	tmp_sensor: temperature-sensor@71 {
		compatible = "ti,tmp103";
		reg = <0x71>;
	};
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_flexcan1_xceiver>;
	status = "disabled";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_flexcan2_xceiver>;
	status = "disabled";
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	qspi_flash: flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <80000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "disabled";
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "disabled";
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "disabled";
};

&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "disabled";
};

&snvs_pwrkey {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	uart-has-rtscts;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "disabled";
};

&usb3_phy0 {
	vbus-supply = <&reg_usb0_host_vbus>;
	status = "okay";
};

&usb3_phy1 {
	vbus-supply = <&reg_usb1_host_vbus>;
	status = "okay";
};

&usb3_0 {
	status = "okay";
};

&usb3_1 {
	status = "okay";
};

&usb_dwc3_0 {
	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	adp-disable;
	extcon = <&extcon_usb0>;
	status = "okay";
};

&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&usdhc3 {
	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_ecspi1: ecspi1grp {
		fsl,pins =
			<MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x82>,
			<MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x82>,
			<MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x82>,
			<MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0		0x40000>,
			<MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x40000>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins =
			<MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82>,
			<MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82>,
			<MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82>,
			<MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0		0x40000>,
			<MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x40000>;
	};

	pinctrl_eqos: eqosgrp {
		fsl,pins =
			<MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3>,
			<MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3>,
			<MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91>,
			<MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91>,
			<MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91>,
			<MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91>,
			<MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91>,
			<MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91>,
			<MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f>,
			<MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f>,
			<MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f>,
			<MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f>,
			<MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f>,
			<MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f>;
	};

	pinctrl_fec: fecgrp {
		fsl,pins =
			<MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3>,
			<MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3>,
			<MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x91>,
			<MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x91>,
			<MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x91>,
			<MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x91>,
			<MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91>,
			<MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91>,
			<MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0	0x1f>,
			<MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1	0x1f>,
			<MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2	0x1f>,
			<MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3	0x1f>,
			<MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f>,
			<MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC	0x1f>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins =
			<MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX		0x154>,
			<MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX		0x154>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins =
			<MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154>,
			<MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154>;
	};

	pinctrl_flexspi0: flexspi0grp {
		fsl,pins =
			<MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2>,
			<MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82>,
			<MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82>,
			<MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82>,
			<MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82>,
			<MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82>,
			<MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x19>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins =
			<MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3>,
			<MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins =
			<MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3>,
			<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c3>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins =
			<MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3>,
			<MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins =
			<MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c3>,
			<MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c3>;
	};

	pinctrl_i2c5: i2c5grp {
		fsl,pins =
			<MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL		0x400001c3>,
			<MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA		0x400001c3>;
	};

	pinctrl_i2c6: i2c6grp {
		fsl,pins =
			<MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL		0x400001c3>,
			<MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA		0x400001c3>;
	};

	pinctrl_lcd0_backlight: lcd0-backlightgrp {
		fsl,pins =
			<MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x41>;
	};

	pinctrl_lcd1_backlight: lcd1-backlightgrp {
		fsl,pins =
			<MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x41>;
	};

	pinctrl_leds: ledsgrp {
		fsl,pins =
			<MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x19>;
	};

	pinctrl_lvds_bridge: lvds-bridgegrp {
		fsl,pins =
			<MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x41>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins =
			<MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT		0x116>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins =
			<MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT		0x116>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins =
			<MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT		0x116>;
	};

	pinctrl_pwm4: pwm4grp {
		fsl,pins =
			<MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT		0x116>;
	};

	pinctrl_tca6424: tca6424grp {
		fsl,pins =
			<MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x41>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins =
			<MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x49>,
			<MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x49>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins =
			<MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06		0x1c4>,
			<MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07		0x1c4>,
			<MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49>,
			<MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins =
			<MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x1c4>,
			<MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x1c4>,
			<MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x49>,
			<MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x49>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins =
			<MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49>,
			<MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49>;
	};

	pinctrl_usb0_extcon: usb0-extcongrp {
		fsl,pins =
			<MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x19>;
	};

	pinctrl_usb0_vbus: usb0-vbusgrp {
		fsl,pins =
			<MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x19>;
	};

	pinctrl_usb1_vbus: usb1-vbusgrp {
		fsl,pins =
			<MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x19>;
	};

	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
		fsl,pins =
			<MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4>,
			<MX8MP_IOMUXC_SD2_WP__GPIO2_IO20		0x1c4>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins =
			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190>,
			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0>,
			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0>,
			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0>,
			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0>,
			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0>,
			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1>;
	};

	pinctrl_usdhc2_vmmc: usdhc2-vmmcgrp {
		fsl,pins =
			<MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x41>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins =
			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194>,
			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4>,
			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4>,
			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4>,
			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4>,
			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4>,
			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins =
			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196>,
			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6>,
			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6>,
			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6>,
			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6>,
			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6>,
			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins =
			<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190>,
			<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0>,
			<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0>,
			<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0>,
			<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0>,
			<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0>,
			<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0>,
			<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0>,
			<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0>,
			<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0>,
			<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins =
			<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
			<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
			<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4>,
			<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4>,
			<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4>,
			<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4>,
			<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4>,
			<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4>,
			<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4>,
			<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
			<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins =
			<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196>,
			<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6>,
			<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6>,
			<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6>,
			<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6>,
			<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6>,
			<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6>,
			<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6>,
			<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6>,
			<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6>,
			<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins =
			<MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
 * Author: Teresa Remmet <t.remmet@phytec.de>
 */

/dts-v1/;

#include <dt-bindings/leds/leds-pca9532.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mp-phycore-som.dtsi"

/ {
	model = "PHYTEC phyBOARD-Pollux i.MX8MP";
	compatible = "phytec,imx8mp-phyboard-pollux-rdk",
		     "phytec,imx8mp-phycore-som", "fsl,imx8mp";

	chosen {
		stdout-path = &uart1;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
		off-on-delay-us = <12000>;
	};
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0x1>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
			enet-phy-lane-no-swap;
		};
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	eeprom@51 {
		compatible = "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
	};

	leds@62 {
		compatible = "nxp,pca9533";
		reg = <0x62>;

		led1 {
			type = <PCA9532_TYPE_LED>;
		};

		led2 {
			type = <PCA9532_TYPE_LED>;
		};

		led3 {
			type = <PCA9532_TYPE_LED>;
		};
	};
};

&snvs_pwrkey {
	status = "okay";
};

/* debug console */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* SD-Card */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	bus-width = <4>;
	status = "okay";
};

&iomuxc {
	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x2
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x2
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20			0x10
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1e2
			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1e2
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x40
			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x40
		>;
	};

	pinctrl_usdhc2_pins: usdhc2-gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
 * Author: Teresa Remmet <t.remmet@phytec.de>
 */

#include <dt-bindings/net/ti-dp83867.h>
#include "imx8mp.dtsi"

/ {
	model = "PHYTEC phyCORE-i.MX8MP";
	compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";

	aliases {
		rtc0 = &rv3028;
		rtc1 = &snvs_rtc;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};
};

&A53_0 {
	cpu-supply = <&buck2>;
};

&A53_1 {
	cpu-supply = <&buck2>;
};

&A53_2 {
	cpu-supply = <&buck2>;
};

&A53_3 {
	cpu-supply = <&buck2>;
};

/* ethernet 1 */
&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			interrupt-parent = <&gpio1>;
			interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
			ti,min-output-impedance;
			enet-phy-lane-no-swap;
		};
	};
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	som_flash: flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <80000000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	pmic: pmic@25 {
		reg = <0x25>;
		compatible = "nxp,pca9450c";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio4>;
		interrupts = <18 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			buck1: BUCK1 {
				regulator-compatible = "BUCK1";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			buck2: BUCK2 {
				regulator-compatible = "BUCK2";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <2187500>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
				nxp,dvs-run-voltage = <950000>;
				nxp,dvs-standby-voltage = <850000>;
			};

			buck4: BUCK4 {
				regulator-compatible = "BUCK4";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5: BUCK5 {
				regulator-compatible = "BUCK5";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6: BUCK6 {
				regulator-compatible = "BUCK6";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <3400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1: LDO1 {
				regulator-compatible = "LDO1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2: LDO2 {
				regulator-compatible = "LDO2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3: LDO3 {
				regulator-compatible = "LDO3";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4: LDO4 {
				regulator-compatible = "LDO4";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
			};

			ldo5: LDO5 {
				regulator-compatible = "LDO5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};

	eeprom@51 {
		compatible = "atmel,24c32";
		reg = <0x51>;
		pagesize = <32>;
	};

	rv3028: rtc@52 {
		compatible = "microcrystal,rv3028";
		reg = <0x52>;
		trickle-resistor-ohms = <3000>;
	};
};

/* eMMC */
&usdhc3 {
	assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x12
			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x12
			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x14
			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x14
			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x14
			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x14
			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x11
		>;
	};

	pinctrl_flexspi0: flexspi0grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x1e3
			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x1e3
		>;
	};

	pinctrl_pmic: pmicirqgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x141
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d2
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d2
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d2
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d2
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d2
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d2
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d2
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d2
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xe6
		>;
	};
};