code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (c) 2020 MediaTek Inc.
 */
#include <dt-bindings/input/input.h>

&pwrap {
	pmic: mt6358 {
		compatible = "mediatek,mt6358";
		interrupt-controller;
		interrupt-parent = <&pio>;
		interrupts = <182 IRQ_TYPE_LEVEL_HIGH>;
		#interrupt-cells = <2>;

		mt6358codec: mt6358codec {
			compatible = "mediatek,mt6358-sound";
			mediatek,dmic-mode = <0>; /* two-wires */
		};

		mt6358regulator: mt6358regulator {
			compatible = "mediatek,mt6358-regulator";

			mt6358_vdram1_reg: buck_vdram1 {
				regulator-name = "vdram1";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <2087500>;
				regulator-ramp-delay = <12500>;
				regulator-enable-ramp-delay = <0>;
				regulator-always-on;
				regulator-allowed-modes = <0 1>;
			};

			mt6358_vcore_reg: buck_vcore {
				regulator-name = "vcore";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <6250>;
				regulator-enable-ramp-delay = <200>;
				regulator-always-on;
				regulator-allowed-modes = <0 1>;
			};

			mt6358_vpa_reg: buck_vpa {
				regulator-name = "vpa";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <3650000>;
				regulator-ramp-delay = <50000>;
				regulator-enable-ramp-delay = <250>;
				regulator-allowed-modes = <0 1>;
			};

			mt6358_vproc11_reg: buck_vproc11 {
				regulator-name = "vproc11";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <6250>;
				regulator-enable-ramp-delay = <200>;
				regulator-always-on;
				regulator-allowed-modes = <0 1>;
			};

			mt6358_vproc12_reg: buck_vproc12 {
				regulator-name = "vproc12";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <6250>;
				regulator-enable-ramp-delay = <200>;
				regulator-always-on;
				regulator-allowed-modes = <0 1>;
			};

			mt6358_vgpu_reg: buck_vgpu {
				regulator-name = "vgpu";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <6250>;
				regulator-enable-ramp-delay = <200>;
				regulator-allowed-modes = <0 1>;
			};

			mt6358_vs2_reg: buck_vs2 {
				regulator-name = "vs2";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <2087500>;
				regulator-ramp-delay = <12500>;
				regulator-enable-ramp-delay = <0>;
				regulator-always-on;
			};

			mt6358_vmodem_reg: buck_vmodem {
				regulator-name = "vmodem";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <6250>;
				regulator-enable-ramp-delay = <900>;
				regulator-always-on;
				regulator-allowed-modes = <0 1>;
			};

			mt6358_vs1_reg: buck_vs1 {
				regulator-name = "vs1";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <2587500>;
				regulator-ramp-delay = <12500>;
				regulator-enable-ramp-delay = <0>;
				regulator-always-on;
			};

			mt6358_vdram2_reg: ldo_vdram2 {
				regulator-name = "vdram2";
				regulator-min-microvolt = <600000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <3300>;
			};

			mt6358_vsim1_reg: ldo_vsim1 {
				regulator-name = "vsim1";
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <3100000>;
				regulator-enable-ramp-delay = <540>;
			};

			mt6358_vibr_reg: ldo_vibr {
				regulator-name = "vibr";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <60>;
			};

			mt6358_vrf12_reg: ldo_vrf12 {
				compatible = "regulator-fixed";
				regulator-name = "vrf12";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-enable-ramp-delay = <120>;
			};

			mt6358_vio18_reg: ldo_vio18 {
				compatible = "regulator-fixed";
				regulator-name = "vio18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <2700>;
				regulator-always-on;
			};

			mt6358_vusb_reg: ldo_vusb {
				regulator-name = "vusb";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3100000>;
				regulator-enable-ramp-delay = <270>;
				regulator-always-on;
			};

			mt6358_vcamio_reg: ldo_vcamio {
				compatible = "regulator-fixed";
				regulator-name = "vcamio";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <325>;
			};

			mt6358_vcamd_reg: ldo_vcamd {
				regulator-name = "vcamd";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <325>;
			};

			mt6358_vcn18_reg: ldo_vcn18 {
				compatible = "regulator-fixed";
				regulator-name = "vcn18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <270>;
			};

			mt6358_vfe28_reg: ldo_vfe28 {
				compatible = "regulator-fixed";
				regulator-name = "vfe28";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <270>;
			};

			mt6358_vsram_proc11_reg: ldo_vsram_proc11 {
				regulator-name = "vsram_proc11";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <6250>;
				regulator-enable-ramp-delay = <240>;
				regulator-always-on;
			};

			mt6358_vcn28_reg: ldo_vcn28 {
				compatible = "regulator-fixed";
				regulator-name = "vcn28";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <270>;
			};

			mt6358_vsram_others_reg: ldo_vsram_others {
				regulator-name = "vsram_others";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <6250>;
				regulator-enable-ramp-delay = <240>;
				regulator-always-on;
			};

			mt6358_vsram_gpu_reg: ldo_vsram_gpu {
				regulator-name = "vsram_gpu";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <6250>;
				regulator-enable-ramp-delay = <240>;
			};

			mt6358_vxo22_reg: ldo_vxo22 {
				compatible = "regulator-fixed";
				regulator-name = "vxo22";
				regulator-min-microvolt = <2200000>;
				regulator-max-microvolt = <2200000>;
				regulator-enable-ramp-delay = <120>;
				regulator-always-on;
			};

			mt6358_vefuse_reg: ldo_vefuse {
				regulator-name = "vefuse";
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <1900000>;
				regulator-enable-ramp-delay = <270>;
			};

			mt6358_vaux18_reg: ldo_vaux18 {
				compatible = "regulator-fixed";
				regulator-name = "vaux18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <270>;
			};

			mt6358_vmch_reg: ldo_vmch {
				regulator-name = "vmch";
				regulator-min-microvolt = <2900000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <60>;
			};

			mt6358_vbif28_reg: ldo_vbif28 {
				compatible = "regulator-fixed";
				regulator-name = "vbif28";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <270>;
			};

			mt6358_vsram_proc12_reg: ldo_vsram_proc12 {
				regulator-name = "vsram_proc12";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <6250>;
				regulator-enable-ramp-delay = <240>;
				regulator-always-on;
			};

			mt6358_vcama1_reg: ldo_vcama1 {
				regulator-name = "vcama1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <325>;
			};

			mt6358_vemc_reg: ldo_vemc {
				regulator-name = "vemc";
				regulator-min-microvolt = <2900000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <60>;
			};

			mt6358_vio28_reg: ldo_vio28 {
				compatible = "regulator-fixed";
				regulator-name = "vio28";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <270>;
			};

			mt6358_va12_reg: ldo_va12 {
				compatible = "regulator-fixed";
				regulator-name = "va12";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-enable-ramp-delay = <270>;
				regulator-always-on;
			};

			mt6358_vrf18_reg: ldo_vrf18 {
				compatible = "regulator-fixed";
				regulator-name = "vrf18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <120>;
			};

			mt6358_vcn33_bt_reg: ldo_vcn33_bt {
				regulator-name = "vcn33_bt";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3500000>;
				regulator-enable-ramp-delay = <270>;
			};

			mt6358_vcn33_wifi_reg: ldo_vcn33_wifi {
				regulator-name = "vcn33_wifi";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3500000>;
				regulator-enable-ramp-delay = <270>;
			};

			mt6358_vcama2_reg: ldo_vcama2 {
				regulator-name = "vcama2";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <325>;
			};

			mt6358_vmc_reg: ldo_vmc {
				regulator-name = "vmc";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <60>;
			};

			mt6358_vldo28_reg: ldo_vldo28 {
				regulator-name = "vldo28";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <270>;
			};

			mt6358_vaud28_reg: ldo_vaud28 {
				compatible = "regulator-fixed";
				regulator-name = "vaud28";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <270>;
			};

			mt6358_vsim2_reg: ldo_vsim2 {
				regulator-name = "vsim2";
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <3100000>;
				regulator-enable-ramp-delay = <540>;
			};
		};

		mt6358rtc: mt6358rtc {
			compatible = "mediatek,mt6358-rtc";
		};

		mt6358keys: mt6358keys {
			compatible = "mediatek,mt6358-keys";
			power {
				linux,keycodes = <KEY_POWER>;
				wakeup-source;
			};
			home {
				linux,keycodes = <KEY_HOME>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2022 MediaTek Inc.
 */

&pwrap {
	pmic: pmic {
		compatible = "mediatek,mt6359";
		interrupt-controller;
		#interrupt-cells = <2>;

		mt6359codec: mt6359codec {
		};

		regulators {
			mt6359_vs1_buck_reg: buck_vs1 {
				regulator-name = "vs1";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <2200000>;
				regulator-enable-ramp-delay = <0>;
				regulator-always-on;
			};
			mt6359_vgpu11_buck_reg: buck_vgpu11 {
				regulator-name = "vgpu11";
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1193750>;
				regulator-ramp-delay = <5000>;
				regulator-enable-ramp-delay = <200>;
				regulator-allowed-modes = <0 1 2>;
			};
			mt6359_vmodem_buck_reg: buck_vmodem {
				regulator-name = "vmodem";
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1100000>;
				regulator-ramp-delay = <10760>;
				regulator-enable-ramp-delay = <200>;
			};
			mt6359_vpu_buck_reg: buck_vpu {
				regulator-name = "vpu";
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1193750>;
				regulator-ramp-delay = <5000>;
				regulator-enable-ramp-delay = <200>;
				regulator-allowed-modes = <0 1 2>;
			};
			mt6359_vcore_buck_reg: buck_vcore {
				regulator-name = "vcore";
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1300000>;
				regulator-ramp-delay = <5000>;
				regulator-enable-ramp-delay = <200>;
				regulator-allowed-modes = <0 1 2>;
			};
			mt6359_vs2_buck_reg: buck_vs2 {
				regulator-name = "vs2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1600000>;
				regulator-enable-ramp-delay = <0>;
				regulator-always-on;
			};
			mt6359_vpa_buck_reg: buck_vpa {
				regulator-name = "vpa";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <3650000>;
				regulator-enable-ramp-delay = <300>;
			};
			mt6359_vproc2_buck_reg: buck_vproc2 {
				regulator-name = "vproc2";
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1193750>;
				regulator-ramp-delay = <7500>;
				regulator-enable-ramp-delay = <200>;
				regulator-allowed-modes = <0 1 2>;
			};
			mt6359_vproc1_buck_reg: buck_vproc1 {
				regulator-name = "vproc1";
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1193750>;
				regulator-ramp-delay = <7500>;
				regulator-enable-ramp-delay = <200>;
				regulator-allowed-modes = <0 1 2>;
			};
			mt6359_vcore_sshub_buck_reg: buck_vcore_sshub {
				regulator-name = "vcore_sshub";
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1193750>;
			};
			mt6359_vgpu11_sshub_buck_reg: buck_vgpu11_sshub {
				regulator-name = "vgpu11_sshub";
				regulator-min-microvolt = <400000>;
				regulator-max-microvolt = <1193750>;
			};
			mt6359_vaud18_ldo_reg: ldo_vaud18 {
				regulator-name = "vaud18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <240>;
			};
			mt6359_vsim1_ldo_reg: ldo_vsim1 {
				regulator-name = "vsim1";
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <3100000>;
			};
			mt6359_vibr_ldo_reg: ldo_vibr {
				regulator-name = "vibr";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
			};
			mt6359_vrf12_ldo_reg: ldo_vrf12 {
				regulator-name = "vrf12";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1300000>;
			};
			mt6359_vusb_ldo_reg: ldo_vusb {
				regulator-name = "vusb";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <960>;
				regulator-always-on;
			};
			mt6359_vsram_proc2_ldo_reg: ldo_vsram_proc2 {
				regulator-name = "vsram_proc2";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <7500>;
				regulator-enable-ramp-delay = <240>;
				regulator-always-on;
			};
			mt6359_vio18_ldo_reg: ldo_vio18 {
				regulator-name = "vio18";
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <1900000>;
				regulator-enable-ramp-delay = <960>;
				regulator-always-on;
			};
			mt6359_vcamio_ldo_reg: ldo_vcamio {
				regulator-name = "vcamio";
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <1900000>;
			};
			mt6359_vcn18_ldo_reg: ldo_vcn18 {
				regulator-name = "vcn18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <240>;
			};
			mt6359_vfe28_ldo_reg: ldo_vfe28 {
				regulator-name = "vfe28";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <120>;
			};
			mt6359_vcn13_ldo_reg: ldo_vcn13 {
				regulator-name = "vcn13";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1300000>;
			};
			mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt {
				regulator-name = "vcn33_1_bt";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <3500000>;
			};
			mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi {
				regulator-name = "vcn33_1_wifi";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <3500000>;
			};
			mt6359_vaux18_ldo_reg: ldo_vaux18 {
				regulator-name = "vaux18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <240>;
				regulator-always-on;
			};
			mt6359_vsram_others_ldo_reg: ldo_vsram_others {
				regulator-name = "vsram_others";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <5000>;
				regulator-enable-ramp-delay = <240>;
			};
			mt6359_vefuse_ldo_reg: ldo_vefuse {
				regulator-name = "vefuse";
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <2000000>;
			};
			mt6359_vxo22_ldo_reg: ldo_vxo22 {
				regulator-name = "vxo22";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <2200000>;
				regulator-always-on;
			};
			mt6359_vrfck_ldo_reg: ldo_vrfck {
				regulator-name = "vrfck";
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <1700000>;
			};
			mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 {
				regulator-name = "vrfck";
				regulator-min-microvolt = <1240000>;
				regulator-max-microvolt = <1600000>;
			};
			mt6359_vbif28_ldo_reg: ldo_vbif28 {
				regulator-name = "vbif28";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <240>;
			};
			mt6359_vio28_ldo_reg: ldo_vio28 {
				regulator-name = "vio28";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
			mt6359_vemc_ldo_reg: ldo_vemc {
				regulator-name = "vemc";
				regulator-min-microvolt = <2900000>;
				regulator-max-microvolt = <3300000>;
			};
			mt6359_vemc_1_ldo_reg: ldo_vemc_1 {
				regulator-name = "vemc";
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <3300000>;
			};
			mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt {
				regulator-name = "vcn33_2_bt";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <3500000>;
			};
			mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi {
				regulator-name = "vcn33_2_wifi";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <3500000>;
			};
			mt6359_va12_ldo_reg: ldo_va12 {
				regulator-name = "va12";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1300000>;
				regulator-always-on;
			};
			mt6359_va09_ldo_reg: ldo_va09 {
				regulator-name = "va09";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1200000>;
			};
			mt6359_vrf18_ldo_reg: ldo_vrf18 {
				regulator-name = "vrf18";
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <1810000>;
			};
			mt6359_vsram_md_ldo_reg: ldo_vsram_md {
				regulator-name = "vsram_md";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <10760>;
				regulator-enable-ramp-delay = <240>;
			};
			mt6359_vufs_ldo_reg: ldo_vufs {
				regulator-name = "vufs";
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <1900000>;
			};
			mt6359_vm18_ldo_reg: ldo_vm18 {
				regulator-name = "vm18";
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <1900000>;
				regulator-always-on;
			};
			mt6359_vbbck_ldo_reg: ldo_vbbck {
				regulator-name = "vbbck";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1200000>;
			};
			mt6359_vsram_proc1_ldo_reg: ldo_vsram_proc1 {
				regulator-name = "vsram_proc1";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
				regulator-ramp-delay = <7500>;
				regulator-enable-ramp-delay = <240>;
				regulator-always-on;
			};
			mt6359_vsim2_ldo_reg: ldo_vsim2 {
				regulator-name = "vsim2";
				regulator-min-microvolt = <1700000>;
				regulator-max-microvolt = <3100000>;
			};
			mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub {
				regulator-name = "vsram_others_sshub";
				regulator-min-microvolt = <500000>;
				regulator-max-microvolt = <1293750>;
			};
		};

		mt6359rtc: mt6359rtc {
			compatible = "mediatek,mt6358-rtc";
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for MediaTek MT6380 regulator
 *
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Chenglin Xu <chenglin.xu@mediatek.com>
 *	   Sean Wang <sean.wang@mediatek.com>
 */

&pwrap {
	regulators {
		compatible = "mediatek,mt6380-regulator";

		mt6380_vcpu_reg: buck-vcore1 {
			regulator-name = "vcore1";
			regulator-min-microvolt = < 600000>;
			regulator-max-microvolt = <1393750>;
			regulator-ramp-delay = <6250>;
			regulator-always-on;
			regulator-boot-on;
		};

		mt6380_vcore_reg: buck-vcore {
			regulator-name = "vcore";
			regulator-min-microvolt = <600000>;
			regulator-max-microvolt = <1393750>;
			regulator-ramp-delay = <6250>;
			regulator-always-on;
			regulator-boot-on;
		};

		mt6380_vrf_reg: buck-vrf {
			regulator-name = "vrf";
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1575000>;
			regulator-ramp-delay = <0>;
			regulator-always-on;
			regulator-boot-on;
		};

		mt6380_vm_reg: ldo-vm {
			regulator-name = "vm";
			regulator-min-microvolt = <1050000>;
			regulator-max-microvolt = <1400000>;
			regulator-ramp-delay = <0>;
			regulator-always-on;
			regulator-boot-on;
		};

		mt6380_va_reg: ldo-va {
			regulator-name = "va";
			regulator-min-microvolt = <2200000>;
			regulator-max-microvolt = <3300000>;
			regulator-ramp-delay = <0>;
			regulator-always-on;
			regulator-boot-on;
		};

		mt6380_vphy_reg: ldo-vphy {
			regulator-name = "vphy";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-ramp-delay = <0>;
			regulator-always-on;
			regulator-boot-on;
		};

		mt6380_vddr_reg: ldo-vddr {
			regulator-name = "vddr";
			regulator-min-microvolt = <1240000>;
			regulator-max-microvolt = <1840000>;
			regulator-ramp-delay = <0>;
			regulator-always-on;
			regulator-boot-on;
		};

		mt6380_vt_reg: ldo-vt {
			regulator-name = "vt";
			regulator-min-microvolt = <2200000>;
			regulator-max-microvolt = <3300000>;
			regulator-ramp-delay = <0>;
			regulator-always-on;
			regulator-boot-on;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016 MediaTek Inc.
 * Author: Mars.C <mars.cheng@mediatek.com>
 */

/dts-v1/;
#include "mt6755.dtsi"

/ {
	model = "MediaTek MT6755 EVB";
	compatible = "mediatek,mt6755-evb", "mediatek,mt6755";

	aliases {
		serial0 = &uart0;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x1e800000>;
	};

	chosen {
		stdout-path = "serial0:921600n8";
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016 MediaTek Inc.
 * Author: Mars.C <mars.cheng@mediatek.com>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "mediatek,mt6755";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x001>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x002>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x003>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x100>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x101>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x102>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x103>;
		};
	};

	uart_clk: dummy26m {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	sysirq: intpol-controller@10200620 {
		compatible = "mediatek,mt6755-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10200620 0 0x20>;
	};

	gic: interrupt-controller@10231000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		interrupt-controller;
		reg = <0 0x10231000 0 0x1000>,
		      <0 0x10232000 0 0x2000>,
		      <0 0x10234000 0 0x2000>,
		      <0 0x10236000 0 0x2000>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt6755-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt6755-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2019 MediaTek Inc.
 * Author: Mars.C <mars.cheng@mediatek.com>
 *
 */

/dts-v1/;
#include "mt6779.dtsi"

/ {
	model = "MediaTek MT6779 EVB";
	compatible = "mediatek,mt6779-evb", "mediatek,mt6779";

	aliases {
		serial0 = &uart0;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x1e800000>;
	};

	chosen {
		stdout-path = "serial0:921600n8";
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2019 MediaTek Inc.
 * Author: Mars.C <mars.cheng@mediatek.com>
 *
 */

#include <dt-bindings/clock/mt6779-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt6779-pinfunc.h>

/ {
	compatible = "mediatek,mt6779";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			enable-method = "psci";
			reg = <0x000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			enable-method = "psci";
			reg = <0x100>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			enable-method = "psci";
			reg = <0x200>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			enable-method = "psci";
			reg = <0x300>;
		};

		cpu4: cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			enable-method = "psci";
			reg = <0x400>;
		};

		cpu5: cpu@5 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			enable-method = "psci";
			reg = <0x500>;
		};

		cpu6: cpu@6 {
			device_type = "cpu";
			compatible = "arm,cortex-a75";
			enable-method = "psci";
			reg = <0x600>;
		};

		cpu7: cpu@7 {
			device_type = "cpu";
			compatible = "arm,cortex-a75";
			enable-method = "psci";
			reg = <0x700>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
	};

	clk26m: oscillator-26m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	clk32k: oscillator-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "clk32k";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		gic: interrupt-controller@c000000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <4>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
			      <0 0x0c040000 0 0x200000>; /* GICR */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;

			ppi-partitions {
				ppi_cluster0: interrupt-partition-0 {
					affinity = <&cpu0 &cpu1 \
						&cpu2 &cpu3 &cpu4 &cpu5>;
				};
				ppi_cluster1: interrupt-partition-1 {
					affinity = <&cpu6 &cpu7>;
				};
			};

		};

		sysirq: intpol-controller@c53a650 {
			compatible = "mediatek,mt6779-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x0c53a650 0 0x50>;
		};

		topckgen: clock-controller@10000000 {
			compatible = "mediatek,mt6779-topckgen", "syscon";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg_ao: clock-controller@10001000 {
			compatible = "mediatek,mt6779-infracfg_ao", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
		};

		pio: pinctrl@10005000 {
			compatible = "mediatek,mt6779-pinctrl";
			reg = <0 0x10005000 0 0x1000>,
			      <0 0x11c20000 0 0x1000>,
			      <0 0x11d10000 0 0x1000>,
			      <0 0x11e20000 0 0x1000>,
			      <0 0x11e70000 0 0x1000>,
			      <0 0x11ea0000 0 0x1000>,
			      <0 0x11f20000 0 0x1000>,
			      <0 0x11f30000 0 0x1000>,
			      <0 0x1000b000 0 0x1000>;
			reg-names = "gpio", "iocfg_rm",
				    "iocfg_br", "iocfg_lm",
				    "iocfg_lb", "iocfg_rt",
				    "iocfg_lt", "iocfg_tl",
				    "eint";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pio 0 0 210>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
		};

		apmixed: clock-controller@1000c000 {
			compatible = "mediatek,mt6779-apmixed", "syscon";
			reg = <0 0x1000c000 0 0xe00>;
			#clock-cells = <1>;
		};

		pwrap: pwrap@1000d000 {
			compatible = "mediatek,mt6779-pwrap";
			reg = <0 0x1000d000 0 0x1000>;
			reg-names = "pwrap";
			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_PMIC_AP>;
			clock-names = "spi", "wrap";
		};

		devapc: devapc@10207000 {
			compatible = "mediatek,mt6779-devapc";
			reg = <0 0x10207000 0 0x1000>;
			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
			clock-names = "devapc-infra-clock";
		};

		uart0: serial@11002000 {
			compatible = "mediatek,mt6779-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11002000 0 0x400>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart1: serial@11003000 {
			compatible = "mediatek,mt6779-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11003000 0 0x400>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart2: serial@11004000 {
			compatible = "mediatek,mt6779-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11004000 0 0x400>;
			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		audio: clock-controller@11210000 {
			compatible = "mediatek,mt6779-audio", "syscon";
			reg = <0 0x11210000 0 0x1000>;
			#clock-cells = <1>;
		};

		mfgcfg: clock-controller@13fbf000 {
			compatible = "mediatek,mt6779-mfgcfg", "syscon";
			reg = <0 0x13fbf000 0 0x1000>;
			#clock-cells = <1>;
		};

		mmsys: syscon@14000000 {
			compatible = "mediatek,mt6779-mmsys", "syscon";
			reg = <0 0x14000000 0 0x1000>;
			#clock-cells = <1>;
		};

		imgsys: clock-controller@15020000 {
			compatible = "mediatek,mt6779-imgsys", "syscon";
			reg = <0 0x15020000 0 0x1000>;
			#clock-cells = <1>;
		};

		vdecsys: clock-controller@16000000 {
			compatible = "mediatek,mt6779-vdecsys", "syscon";
			reg = <0 0x16000000 0 0x1000>;
			#clock-cells = <1>;
		};

		vencsys: clock-controller@17000000 {
			compatible = "mediatek,mt6779-vencsys", "syscon";
			reg = <0 0x17000000 0 0x1000>;
			#clock-cells = <1>;
		};

		camsys: clock-controller@1a000000 {
			compatible = "mediatek,mt6779-camsys", "syscon";
			reg = <0 0x1a000000 0 0x10000>;
			#clock-cells = <1>;
		};

		ipesys: clock-controller@1b000000 {
			compatible = "mediatek,mt6779-ipesys", "syscon";
			reg = <0 0x1b000000 0 0x1000>;
			#clock-cells = <1>;
		};

	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Mars.C <mars.cheng@mediatek.com>
 */

/dts-v1/;
#include "mt6795.dtsi"

/ {
	model = "MediaTek MT6795 Evaluation Board";
	compatible = "mediatek,mt6795-evb", "mediatek,mt6795";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x1e800000>;
	};

	chosen {
		stdout-path = "serial0:921600n8";
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2022, Collabora Ltd
 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
 */

/dts-v1/;
#include "mt6795.dtsi"

/ {
	model = "Sony Xperia M5";
	compatible = "sony,xperia-m5", "mediatek,mt6795";
	chassis-type = "handset";

	aliases {
		mmc0 = &mmc0;
		mmc1 = &mmc1;
		serial0 = &uart0;
		serial1 = &uart1;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x1e800000>;
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* 128 KiB reserved for ARM Trusted Firmware (BL31) */
		bl31_secmon_reserved: secmon@43000000 {
			reg = <0 0x43000000 0 0x30000>;
			no-map;
		};

		/* preloader and bootloader regions cannot be touched */
		preloader-region@44800000 {
			reg = <0 0x44800000 0 0x100000>;
			no-map;
		};

		bootloader-region@46000000 {
			reg = <0 0x46000000 0 0x400000>;
			no-map;
		};
	};
};

&pio {
	uart0_pins: uart0-pins {
		pins-rx {
			pinmux = <PINMUX_GPIO113__FUNC_URXD0>;
			bias-pull-up;
			input-enable;
		};
		pins-tx {
			pinmux = <PINMUX_GPIO114__FUNC_UTXD0>;
			output-high;
		};
	};

	uart2_pins: uart2-pins {
		pins-rx {
			pinmux = <PINMUX_GPIO31__FUNC_URXD2>;
			bias-pull-up;
			input-enable;
		};
		pins-tx {
			pinmux = <PINMUX_GPIO32__FUNC_UTXD2>;
		};
	};
};

&uart0 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
};

&uart2 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Mars.C <mars.cheng@mediatek.com>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
#include <dt-bindings/reset/mediatek,mt6795-resets.h>

/ {
	compatible = "mediatek,mt6795";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x000>;
			cci-control-port = <&cci_control2>;
			next-level-cache = <&l2_0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x001>;
			cci-control-port = <&cci_control2>;
			next-level-cache = <&l2_0>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x002>;
			cci-control-port = <&cci_control2>;
			next-level-cache = <&l2_0>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x003>;
			cci-control-port = <&cci_control2>;
			next-level-cache = <&l2_0>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x100>;
			cci-control-port = <&cci_control1>;
			next-level-cache = <&l2_1>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x101>;
			cci-control-port = <&cci_control1>;
			next-level-cache = <&l2_1>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x102>;
			cci-control-port = <&cci_control1>;
			next-level-cache = <&l2_1>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x103>;
			cci-control-port = <&cci_control1>;
			next-level-cache = <&l2_1>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};

				core1 {
					cpu = <&cpu5>;
				};

				core2 {
					cpu = <&cpu6>;
				};

				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		l2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};

		l2_1: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	clk26m: oscillator-26m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	clk32k: oscillator-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32000>;
		clock-output-names = "clk32k";
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI  9 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		topckgen: syscon@10000000 {
			compatible = "mediatek,mt6795-topckgen", "syscon";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg: syscon@10001000 {
			compatible = "mediatek,mt6795-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pericfg: syscon@10003000 {
			compatible = "mediatek,mt6795-pericfg", "syscon";
			reg = <0 0x10003000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pio: pinctrl@10005000 {
			compatible = "mediatek,mt6795-pinctrl";
			reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
			reg-names = "base", "eint";
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pio 0 0 196>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		watchdog: watchdog@10007000 {
			compatible = "mediatek,mt6795-wdt";
			reg = <0 0x10007000 0 0x100>;
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
			#reset-cells = <1>;
			timeout-sec = <20>;
		};

		timer: timer@10008000 {
			compatible = "mediatek,mt6795-timer",
				     "mediatek,mt6577-timer";
			reg = <0 0x10008000 0 0x1000>;
			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&system_clk>, <&clk32k>;
		};

		sysirq: intpol-controller@10200620 {
			compatible = "mediatek,mt6795-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10200620 0 0x20>;
		};

		systimer: timer@10200670 {
			compatible = "mediatek,mt6795-systimer";
			reg = <0 0x10200670 0 0x10>;
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&system_clk>;
			clock-names = "clk13m";
		};

		gic: interrupt-controller@10221000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			reg = <0 0x10221000 0 0x1000>,
			      <0 0x10222000 0 0x2000>,
			      <0 0x10224000 0 0x2000>,
			      <0 0x10226000 0 0x2000>;
			interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		cci: cci@10390000 {
			compatible = "arm,cci-400";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0 0x10390000 0 0x1000>;
			ranges = <0 0 0x10390000 0x10000>;

			cci_control0: slave-if@1000 {
				compatible = "arm,cci-400-ctrl-if";
				interface-type = "ace-lite";
				reg = <0x1000 0x1000>;
			};

			cci_control1: slave-if@4000 {
				compatible = "arm,cci-400-ctrl-if";
				interface-type = "ace";
				reg = <0x4000 0x1000>;
			};

			cci_control2: slave-if@5000 {
				compatible = "arm,cci-400-ctrl-if";
				interface-type = "ace";
				reg = <0x5000 0x1000>;
			};

			pmu@9000 {
				compatible = "arm,cci-400-pmu,r1";
				reg = <0x9000 0x5000>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		uart0: serial@11002000 {
			compatible = "mediatek,mt6795-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11002000 0 0x400>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
			clock-names = "baud", "bus";
			dmas = <&apdma 0>, <&apdma 1>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		uart1: serial@11003000 {
			compatible = "mediatek,mt6795-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11003000 0 0x400>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
			clock-names = "baud", "bus";
			dmas = <&apdma 2>, <&apdma 3>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		apdma: dma-controller@11000380 {
			compatible = "mediatek,mt6795-uart-dma",
				     "mediatek,mt6577-uart-dma";
			reg = <0 0x11000380 0 0x60>,
			      <0 0x11000400 0 0x60>,
			      <0 0x11000480 0 0x60>,
			      <0 0x11000500 0 0x60>,
			      <0 0x11000580 0 0x60>,
			      <0 0x11000600 0 0x60>,
			      <0 0x11000680 0 0x60>,
			      <0 0x11000700 0 0x60>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
			dma-requests = <8>;
			clocks = <&pericfg CLK_PERI_AP_DMA>;
			clock-names = "apdma";
			mediatek,dma-33bits;
			#dma-cells = <1>;
		};

		uart2: serial@11004000 {
			compatible = "mediatek,mt6795-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11004000 0 0x400>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
			clock-names = "baud", "bus";
			dmas = <&apdma 4>, <&apdma 5>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		uart3: serial@11005000 {
			compatible = "mediatek,mt6795-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11005000 0 0x400>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
			clock-names = "baud", "bus";
			dmas = <&apdma 6>, <&apdma 7>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		mmc0: mmc@11230000 {
			compatible = "mediatek,mt6795-mmc";
			reg = <0 0x11230000 0 0x1000>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_MSDC30_0>,
				 <&topckgen CLK_TOP_MSDC50_0_H_SEL>,
				 <&topckgen CLK_TOP_MSDC50_0_SEL>;
			clock-names = "source", "hclk", "source_cg";
			status = "disabled";
		};

		mmc1: mmc@11240000 {
			compatible = "mediatek,mt6795-mmc";
			reg = <0 0x11240000 0 0x1000>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_MSDC30_1>,
				 <&topckgen CLK_TOP_AXI_SEL>;
			clock-names = "source", "hclk";
			status = "disabled";
		};

		mmc2: mmc@11250000 {
			compatible = "mediatek,mt6795-mmc";
			reg = <0 0x11250000 0 0x1000>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_MSDC30_2>,
				 <&topckgen CLK_TOP_AXI_SEL>;
			clock-names = "source", "hclk";
			status = "disabled";
		};

		mmc3: mmc@11260000 {
			compatible = "mediatek,mt6795-mmc";
			reg = <0 0x11260000 0 0x1000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_MSDC30_3>,
				 <&topckgen CLK_TOP_AXI_SEL>;
			clock-names = "source", "hclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2017 MediaTek Inc.
 * Author: Mars.C <mars.cheng@mediatek.com>
 */

/dts-v1/;
#include "mt6797.dtsi"

/ {
	model = "MediaTek MT6797 Evaluation Board";
	compatible = "mediatek,mt6797-evb", "mediatek,mt6797";

	aliases {
		serial0 = &uart0;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x1e800000>;
	};

	chosen {};
};

&uart0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins_a>;
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for MediaTek X20 Development Board
 *
 * Copyright (C) 2018, Linaro Ltd.
 *
 */

/dts-v1/;

#include "mt6797.dtsi"

/ {
	model = "Mediatek X20 Development Board";
	compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797";

	aliases {
		serial0 = &uart1;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x80000000>;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

/* HDMI */
&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins_a>;
	status = "okay";
};

/* HS - I2C2 */
&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins_a>;
	status = "okay";
};

/* HS - I2C3 */
&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins_a>;
	status = "okay";
};

/* LS - I2C0 */
&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins_a>;
	status = "okay";
};

/* LS - I2C1 */
&i2c5 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c5_pins_a>;
	status = "okay";
};

/* POWER_VPROC */
&i2c6 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c6_pins_a>;
	status = "okay";
};

/* FAN53555 */
&i2c7 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c7_pins_a>;
	status = "okay";
};

&uart1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins_a>;
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2017 MediaTek Inc.
 * Author: Mars.C <mars.cheng@mediatek.com>
 */

#include <dt-bindings/clock/mt6797-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt6797-pinfunc.h>

/ {
	compatible = "mediatek,mt6797";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x001>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x002>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x003>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x100>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x101>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x102>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x103>;
		};

		cpu8: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			enable-method = "psci";
			reg = <0x200>;
		};

		cpu9: cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			enable-method = "psci";
			reg = <0x201>;
		};
	};

	clk26m: oscillator-26m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	topckgen: topckgen@10000000 {
		compatible = "mediatek,mt6797-topckgen";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
	};

	infrasys: infracfg_ao@10001000 {
		compatible = "mediatek,mt6797-infracfg", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		#clock-cells = <1>;
	};

	pio: pinctrl@10005000 {
		compatible = "mediatek,mt6797-pinctrl";
		reg = <0 0x10005000 0 0x1000>,
		      <0 0x10002000 0 0x400>,
		      <0 0x10002400 0 0x400>,
		      <0 0x10002800 0 0x400>,
		      <0 0x10002C00 0 0x400>;
		reg-names = "gpio", "iocfgl", "iocfgb",
			    "iocfgr", "iocfgt";
		gpio-controller;
		#gpio-cells = <2>;

		uart0_pins_a: uart0 {
			pins0 {
				pinmux = <MT6797_GPIO234__FUNC_UTXD0>,
					 <MT6797_GPIO235__FUNC_URXD0>;
			};
		};

		uart1_pins_a: uart1 {
			pins1 {
				pinmux = <MT6797_GPIO232__FUNC_URXD1>,
					 <MT6797_GPIO233__FUNC_UTXD1>;
			};
		};

		i2c0_pins_a: i2c0 {
			pins0 {
				pinmux = <MT6797_GPIO37__FUNC_SCL0_0>,
					 <MT6797_GPIO38__FUNC_SDA0_0>;
			};
		};

		i2c1_pins_a: i2c1 {
			pins1 {
				pinmux = <MT6797_GPIO55__FUNC_SCL1_0>,
					 <MT6797_GPIO56__FUNC_SDA1_0>;
			};
		};

		i2c2_pins_a: i2c2 {
			pins2 {
				pinmux = <MT6797_GPIO96__FUNC_SCL2_0>,
					 <MT6797_GPIO95__FUNC_SDA2_0>;
			};
		};

		i2c3_pins_a: i2c3 {
			pins3 {
				pinmux = <MT6797_GPIO75__FUNC_SDA3_0>,
					 <MT6797_GPIO74__FUNC_SCL3_0>;
			};
		};

		i2c4_pins_a: i2c4 {
			pins4 {
				pinmux = <MT6797_GPIO238__FUNC_SDA4_0>,
					 <MT6797_GPIO239__FUNC_SCL4_0>;
			};
		};

		i2c5_pins_a: i2c5 {
			pins5 {
				pinmux = <MT6797_GPIO240__FUNC_SDA5_0>,
					 <MT6797_GPIO241__FUNC_SCL5_0>;
			};
		};

		i2c6_pins_a: i2c6 {
			pins6 {
				pinmux = <MT6797_GPIO152__FUNC_SDA6_0>,
					 <MT6797_GPIO151__FUNC_SCL6_0>;
			};
		};

		i2c7_pins_a: i2c7 {
			pins7 {
				pinmux = <MT6797_GPIO154__FUNC_SDA7_0>,
					 <MT6797_GPIO153__FUNC_SCL7_0>;
			};
		};
	};

	scpsys: power-controller@10006000 {
		compatible = "mediatek,mt6797-scpsys";
		#power-domain-cells = <1>;
		reg = <0 0x10006000 0 0x1000>;
		clocks = <&topckgen CLK_TOP_MUX_MFG>,
			 <&topckgen CLK_TOP_MUX_MM>,
			 <&topckgen CLK_TOP_MUX_VDEC>;
		clock-names = "mfg", "mm", "vdec";
		infracfg = <&infrasys>;
	};

	watchdog: watchdog@10007000 {
		compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
		reg = <0 0x10007000 0 0x100>;
	};

	apmixedsys: apmixed@1000c000 {
		compatible = "mediatek,mt6797-apmixedsys";
		reg = <0 0x1000c000 0 0x1000>;
		#clock-cells = <1>;
	};

	sysirq: intpol-controller@10200620 {
		compatible = "mediatek,mt6797-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10220620 0 0x20>,
		      <0 0x10220690 0 0x10>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt6797-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_UART0>,
			 <&infrasys CLK_INFRA_AP_DMA>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt6797-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_UART1>,
			 <&infrasys CLK_INFRA_AP_DMA>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt6797-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_UART2>,
			 <&infrasys CLK_INFRA_AP_DMA>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt6797-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11005000 0 0x400>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_UART3>,
			 <&infrasys CLK_INFRA_AP_DMA>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	i2c0: i2c@11007000 {
		compatible = "mediatek,mt6797-i2c",
			     "mediatek,mt6577-i2c";
		id = <0>;
		reg = <0 0x11007000 0 0x1000>,
		      <0 0x11000100 0 0x80>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_I2C0>,
			 <&infrasys CLK_INFRA_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <10>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c1: i2c@11008000 {
		compatible = "mediatek,mt6797-i2c",
			     "mediatek,mt6577-i2c";
		id = <1>;
		reg = <0 0x11008000 0 0x1000>,
		      <0 0x11000180 0 0x80>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_I2C1>,
			 <&infrasys CLK_INFRA_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <10>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c8: i2c@11009000 {
		compatible = "mediatek,mt6797-i2c",
			     "mediatek,mt6577-i2c";
		id = <8>;
		reg = <0 0x11009000 0 0x1000>,
		      <0 0x11000200 0 0x80>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_I2C2>,
			 <&infrasys CLK_INFRA_AP_DMA>,
			 <&infrasys CLK_INFRA_I2C2_ARB>;
		clock-names = "main", "dma", "arb";
		clock-div = <10>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c9: i2c@1100d000 {
		compatible = "mediatek,mt6797-i2c",
			     "mediatek,mt6577-i2c";
		id = <9>;
		reg = <0 0x1100d000 0 0x1000>,
		      <0 0x11000280 0 0x80>;
		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_I2C3>,
			 <&infrasys CLK_INFRA_AP_DMA>,
			 <&infrasys CLK_INFRA_I2C3_ARB>;
		clock-names = "main", "dma", "arb";
		clock-div = <10>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c6: i2c@1100e000 {
		compatible = "mediatek,mt6797-i2c",
			     "mediatek,mt6577-i2c";
		id = <6>;
		reg = <0 0x1100e000 0 0x1000>,
		      <0 0x11000500 0 0x80>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_I2C_APPM>,
			 <&infrasys CLK_INFRA_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <10>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c7: i2c@11010000 {
		compatible = "mediatek,mt6797-i2c",
			     "mediatek,mt6577-i2c";
		id = <7>;
		reg = <0 0x11010000 0 0x1000>,
		      <0 0x11000580 0 0x80>;
		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_I2C_GPUPM>,
			 <&infrasys CLK_INFRA_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <10>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c4: i2c@11011000 {
		compatible = "mediatek,mt6797-i2c",
			     "mediatek,mt6577-i2c";
		id = <4>;
		reg = <0 0x11011000 0 0x1000>,
		      <0 0x11000300 0 0x80>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_I2C4>,
			 <&infrasys CLK_INFRA_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <10>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@11013000 {
		compatible = "mediatek,mt6797-i2c",
			     "mediatek,mt6577-i2c";
		id = <2>;
		reg = <0 0x11013000 0 0x1000>,
		      <0 0x11000400 0 0x80>;
		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_I2C2_IMM>,
			 <&infrasys CLK_INFRA_AP_DMA>,
			 <&infrasys CLK_INFRA_I2C2_ARB>;
		clock-names = "main", "dma", "arb";
		clock-div = <10>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c3: i2c@11014000 {
		compatible = "mediatek,mt6797-i2c",
			     "mediatek,mt6577-i2c";
		id = <3>;
		reg = <0 0x11014000 0 0x1000>,
		      <0 0x11000480 0 0x80>;
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_I2C3_IMM>,
			 <&infrasys CLK_INFRA_AP_DMA>,
			 <&infrasys CLK_INFRA_I2C3_ARB>;
		clock-names = "main", "dma", "arb";
		clock-div = <10>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c5: i2c@1101c000 {
		compatible = "mediatek,mt6797-i2c",
			     "mediatek,mt6577-i2c";
		id = <5>;
		reg = <0 0x1101c000 0 0x1000>,
		      <0 0x11000380 0 0x80>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infrasys CLK_INFRA_I2C5>,
			 <&infrasys CLK_INFRA_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <10>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	mmsys: syscon@14000000 {
		compatible = "mediatek,mt6797-mmsys", "syscon";
		reg = <0 0x14000000 0 0x1000>;
		#clock-cells = <1>;
	};

	imgsys: imgsys_config@15000000  {
		compatible = "mediatek,mt6797-imgsys", "syscon";
		reg = <0 0x15000000 0 0x1000>;
		#clock-cells = <1>;
	};

	vdecsys: vdec_gcon@16000000 {
		compatible = "mediatek,mt6797-vdecsys", "syscon";
		reg = <0 0x16000000 0 0x10000>;
		#clock-cells = <1>;
	};

	vencsys: venc_gcon@17000000 {
		compatible = "mediatek,mt6797-vencsys", "syscon";
		reg = <0 0x17000000 0 0x1000>;
		#clock-cells = <1>;
	};

	gic: interrupt-controller@19000000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		reg = <0 0x19000000 0 0x10000>,    /* GICD */
		      <0 0x19200000 0 0x200000>,   /* GICR */
		      <0 0x10240000 0 0x2000>;     /* GICC */
	};
};


code:
/*
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Ryder Lee <ryder.lee@mediatek.com>
 *
 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
 */

/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>

#include "mt7622.dtsi"
#include "mt6380.dtsi"

/ {
	model = "Bananapi BPI-R64";
	compatible = "bananapi,bpi-r64", "mediatek,mt7622";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
	};

	cpus {
		cpu@0 {
			proc-supply = <&mt6380_vcpu_reg>;
			sram-supply = <&mt6380_vm_reg>;
		};

		cpu@1 {
			proc-supply = <&mt6380_vcpu_reg>;
			sram-supply = <&mt6380_vm_reg>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		factory-key {
			label = "factory";
			linux,code = <BTN_0>;
			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
		};

		wps-key {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led-0 {
			label = "bpi-r64:pio:green";
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-1 {
			label = "bpi-r64:pio:red";
			color = <LED_COLOR_ID_RED>;
			gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	memory {
		reg = <0 0x40000000 0 0x40000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_5v: regulator-5v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&bch {
	status = "disabled";
};

&btif {
	status = "okay";
};

&cir {
	pinctrl-names = "default";
	pinctrl-0 = <&irrx_pins>;
	status = "okay";
};

&eth {
	status = "okay";
	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "2500base-x";

		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
		};
	};

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-mode = "rgmii";

		fixed-link {
			speed = <1000>;
			full-duplex;
			pause;
		};
	};

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		switch@0 {
			compatible = "mediatek,mt7531";
			reg = <0>;
			reset-gpios = <&pio 54 0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "wan";
				};

				port@1 {
					reg = <1>;
					label = "lan0";
				};

				port@2 {
					reg = <2>;
					label = "lan1";
				};

				port@3 {
					reg = <3>;
					label = "lan2";
				};

				port@4 {
					reg = <4>;
					label = "lan3";
				};

				port@6 {
					reg = <6>;
					label = "cpu";
					ethernet = <&gmac0>;
					phy-mode = "2500base-x";

					fixed-link {
						speed = <2500>;
						full-duplex;
						pause;
					};
				};
			};
		};

	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "okay";
};

&mmc0 {
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&emmc_pins_default>;
	pinctrl-1 = <&emmc_pins_uhs>;
	status = "okay";
	bus-width = <8>;
	max-frequency = <50000000>;
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
	non-removable;
};

&mmc1 {
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&sd0_pins_default>;
	pinctrl-1 = <&sd0_pins_uhs>;
	status = "okay";
	bus-width = <4>;
	max-frequency = <50000000>;
	cap-sd-highspeed;
	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_3p3v>;
	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
};

&nandc {
	pinctrl-names = "default";
	pinctrl-0 = <&parallel_nand_pins>;
	status = "disabled";
};

&nor_flash {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_nor_pins>;
	status = "disabled";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
	};
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie0_pins>;
	status = "okay";
};

&pcie1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie1_pins>;
	status = "okay";
};

&pio {
	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
	 * SATA functions. i.e. output-high: PCIe, output-low: SATA
	 */
	asm_sel {
		gpio-hog;
		gpios = <90 GPIO_ACTIVE_HIGH>;
		output-high;
	};

	/* eMMC is shared pin with parallel NAND */
	emmc_pins_default: emmc-pins-default {
		mux {
			function = "emmc", "emmc_rst";
			groups = "emmc";
		};

		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
		 */
		conf-cmd-dat {
			pins = "NDL0", "NDL1", "NDL2",
			       "NDL3", "NDL4", "NDL5",
			       "NDL6", "NDL7", "NRB";
			input-enable;
			bias-pull-up;
		};

		conf-clk {
			pins = "NCLE";
			bias-pull-down;
		};
	};

	emmc_pins_uhs: emmc-pins-uhs {
		mux {
			function = "emmc";
			groups = "emmc";
		};

		conf-cmd-dat {
			pins = "NDL0", "NDL1", "NDL2",
			       "NDL3", "NDL4", "NDL5",
			       "NDL6", "NDL7", "NRB";
			input-enable;
			drive-strength = <4>;
			bias-pull-up;
		};

		conf-clk {
			pins = "NCLE";
			drive-strength = <4>;
			bias-pull-down;
		};
	};

	eth_pins: eth-pins {
		mux {
			function = "eth";
			groups = "mdc_mdio", "rgmii_via_gmac2";
		};
	};

	i2c1_pins: i2c1-pins {
		mux {
			function = "i2c";
			groups = "i2c1_0";
		};
	};

	i2c2_pins: i2c2-pins {
		mux {
			function = "i2c";
			groups = "i2c2_0";
		};
	};

	i2s1_pins: i2s1-pins {
		mux {
			function = "i2s";
			groups =  "i2s_out_mclk_bclk_ws",
				  "i2s1_in_data",
				  "i2s1_out_data";
		};

		conf {
			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
			       "I2S_WS", "I2S_MCLK";
			drive-strength = <12>;
			bias-pull-down;
		};
	};

	irrx_pins: irrx-pins {
		mux {
			function = "ir";
			groups = "ir_1_rx";
		};
	};

	irtx_pins: irtx-pins {
		mux {
			function = "ir";
			groups = "ir_1_tx";
		};
	};

	/* Parallel nand is shared pin with eMMC */
	parallel_nand_pins: parallel-nand-pins {
		mux {
			function = "flash";
			groups = "par_nand";
		};
	};

	pcie0_pins: pcie0-pins {
		mux {
			function = "pcie";
			groups = "pcie0_pad_perst",
				 "pcie0_1_waken",
				 "pcie0_1_clkreq";
		};
	};

	pcie1_pins: pcie1-pins {
		mux {
			function = "pcie";
			groups = "pcie1_pad_perst",
				 "pcie1_0_waken",
				 "pcie1_0_clkreq";
		};
	};

	pmic_bus_pins: pmic-bus-pins {
		mux {
			function = "pmic";
			groups = "pmic_bus";
		};
	};

	pwm_pins: pwm-pins {
		mux {
			function = "pwm";
			groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
				 "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
				 "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
				 "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
				 "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
				 "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
		};
	};

	wled_pins: wled-pins {
		mux {
			function = "led";
			groups = "wled";
		};
	};

	sd0_pins_default: sd0-pins-default {
		mux {
			function = "sd";
			groups = "sd_0";
		};

		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
		 *  DAT2, DAT3, CMD, CLK for SD respectively.
		 */
		conf-cmd-data {
			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
			       "I2S2_IN","I2S4_OUT";
			input-enable;
			drive-strength = <8>;
			bias-pull-up;
		};
		conf-clk {
			pins = "I2S3_OUT";
			drive-strength = <12>;
			bias-pull-down;
		};
		conf-cd {
			pins = "TXD3";
			bias-pull-up;
		};
	};

	sd0_pins_uhs: sd0-pins-uhs {
		mux {
			function = "sd";
			groups = "sd_0";
		};

		conf-cmd-data {
			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
			       "I2S2_IN","I2S4_OUT";
			input-enable;
			bias-pull-up;
		};

		conf-clk {
			pins = "I2S3_OUT";
			bias-pull-down;
		};
	};

	/* Serial NAND is shared pin with SPI-NOR */
	serial_nand_pins: serial-nand-pins {
		mux {
			function = "flash";
			groups = "snfi";
		};
	};

	spic0_pins: spic0-pins {
		mux {
			function = "spi";
			groups = "spic0_0";
		};
	};

	spic1_pins: spic1-pins {
		mux {
			function = "spi";
			groups = "spic1_0";
		};
	};

	/* SPI-NOR is shared pin with serial NAND */
	spi_nor_pins: spi-nor-pins {
		mux {
			function = "flash";
			groups = "spi_nor";
		};
	};

	/* serial NAND is shared pin with SPI-NOR */
	serial_nand_pins: serial-nand-pins {
		mux {
			function = "flash";
			groups = "snfi";
		};
	};

	uart0_pins: uart0-pins {
		mux {
			function = "uart";
			groups = "uart0_0_tx_rx" ;
		};
	};

	uart2_pins: uart2-pins {
		mux {
			function = "uart";
			groups = "uart2_1_tx_rx" ;
		};
	};

	watchdog_pins: watchdog-pins {
		mux {
			function = "watchdog";
			groups = "watchdog";
		};
	};
};

&pwm {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm_pins>;
	status = "okay";
};

&pwrap {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_bus_pins>;

	status = "okay";
};

&sata {
	status = "disable";
};

&sata_phy {
	status = "disable";
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic0_pins>;
	status = "okay";
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic1_pins>;
};

&ssusb {
	vusb33-supply = <&reg_3p3v>;
	vbus-supply = <&reg_5v>;
	status = "okay";
};

&u3phy {
	status = "okay";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
};

&watchdog {
	pinctrl-names = "default";
	pinctrl-0 = <&watchdog_pins>;
	status = "okay";
};

&wmac {
	status = "okay";
};


code:
/*
 * Copyright (c) 2017 MediaTek Inc.
 * Author: Ming Huang <ming.huang@mediatek.com>
 *	   Sean Wang <sean.wang@mediatek.com>
 *
 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
 */

/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

#include "mt7622.dtsi"
#include "mt6380.dtsi"

/ {
	model = "MediaTek MT7622 RFB1 board";
	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
	};

	cpus {
		cpu@0 {
			proc-supply = <&mt6380_vcpu_reg>;
			sram-supply = <&mt6380_vm_reg>;
		};

		cpu@1 {
			proc-supply = <&mt6380_vcpu_reg>;
			sram-supply = <&mt6380_vm_reg>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-factory {
			label = "factory";
			linux,code = <BTN_0>;
			gpios = <&pio 0 0>;
		};

		key-wps {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&pio 102 0>;
		};
	};

	memory {
		reg = <0 0x40000000 0 0x20000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_5v: regulator-5v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&bch {
	status = "disabled";
};

&btif {
	status = "okay";
};

&cir {
	pinctrl-names = "default";
	pinctrl-0 = <&irrx_pins>;
	status = "okay";
};

&eth {
	pinctrl-names = "default";
	pinctrl-0 = <&eth_pins>;
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "2500base-x";

		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
		};
	};

	mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		switch@0 {
			compatible = "mediatek,mt7531";
			reg = <0>;
			reset-gpios = <&pio 54 0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "lan0";
				};

				port@1 {
					reg = <1>;
					label = "lan1";
				};

				port@2 {
					reg = <2>;
					label = "lan2";
				};

				port@3 {
					reg = <3>;
					label = "lan3";
				};

				port@4 {
					reg = <4>;
					label = "wan";
				};

				port@6 {
					reg = <6>;
					label = "cpu";
					ethernet = <&gmac0>;
					phy-mode = "2500base-x";

					fixed-link {
						speed = <2500>;
						full-duplex;
						pause;
					};
				};
			};
		};

	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "okay";
};

&mmc0 {
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&emmc_pins_default>;
	pinctrl-1 = <&emmc_pins_uhs>;
	status = "okay";
	bus-width = <8>;
	max-frequency = <50000000>;
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_1p8v>;
	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
	non-removable;
};

&mmc1 {
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&sd0_pins_default>;
	pinctrl-1 = <&sd0_pins_uhs>;
	status = "okay";
	bus-width = <4>;
	max-frequency = <50000000>;
	cap-sd-highspeed;
	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_3p3v>;
	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
};

&nandc {
	pinctrl-names = "default";
	pinctrl-0 = <&parallel_nand_pins>;
	status = "disabled";
};

&nor_flash {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_nor_pins>;
	status = "disabled";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
	};
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie0_pins>;
	status = "okay";
};

&pio {
	/* eMMC is shared pin with parallel NAND */
	emmc_pins_default: emmc-pins-default {
		mux {
			function = "emmc", "emmc_rst";
			groups = "emmc";
		};

		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
		 */
		conf-cmd-dat {
			pins = "NDL0", "NDL1", "NDL2",
			       "NDL3", "NDL4", "NDL5",
			       "NDL6", "NDL7", "NRB";
			input-enable;
			bias-pull-up;
		};

		conf-clk {
			pins = "NCLE";
			bias-pull-down;
		};
	};

	emmc_pins_uhs: emmc-pins-uhs {
		mux {
			function = "emmc";
			groups = "emmc";
		};

		conf-cmd-dat {
			pins = "NDL0", "NDL1", "NDL2",
			       "NDL3", "NDL4", "NDL5",
			       "NDL6", "NDL7", "NRB";
			input-enable;
			drive-strength = <4>;
			bias-pull-up;
		};

		conf-clk {
			pins = "NCLE";
			drive-strength = <4>;
			bias-pull-down;
		};
	};

	eth_pins: eth-pins {
		mux {
			function = "eth";
			groups = "mdc_mdio", "rgmii_via_gmac2";
		};
	};

	i2c1_pins: i2c1-pins {
		mux {
			function = "i2c";
			groups = "i2c1_0";
		};
	};

	i2c2_pins: i2c2-pins {
		mux {
			function = "i2c";
			groups = "i2c2_0";
		};
	};

	i2s1_pins: i2s1-pins {
		mux {
			function = "i2s";
			groups =  "i2s_out_mclk_bclk_ws",
				  "i2s1_in_data",
				  "i2s1_out_data";
		};

		conf {
			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
			       "I2S_WS", "I2S_MCLK";
			drive-strength = <12>;
			bias-pull-down;
		};
	};

	irrx_pins: irrx-pins {
		mux {
			function = "ir";
			groups = "ir_1_rx";
		};
	};

	irtx_pins: irtx-pins {
		mux {
			function = "ir";
			groups = "ir_1_tx";
		};
	};

	/* Parallel nand is shared pin with eMMC */
	parallel_nand_pins: parallel-nand-pins {
		mux {
			function = "flash";
			groups = "par_nand";
		};
	};

	pcie0_pins: pcie0-pins {
		mux {
			function = "pcie";
			groups = "pcie0_pad_perst",
				 "pcie0_1_waken",
				 "pcie0_1_clkreq";
		};
	};

	pcie1_pins: pcie1-pins {
		mux {
			function = "pcie";
			groups = "pcie1_pad_perst",
				 "pcie1_0_waken",
				 "pcie1_0_clkreq";
		};
	};

	pmic_bus_pins: pmic-bus-pins {
		mux {
			function = "pmic";
			groups = "pmic_bus";
		};
	};

	pwm7_pins: pwm1-2-pins {
		mux {
			function = "pwm";
			groups = "pwm_ch7_2";
		};
	};

	wled_pins: wled-pins {
		mux {
			function = "led";
			groups = "wled";
		};
	};

	sd0_pins_default: sd0-pins-default {
		mux {
			function = "sd";
			groups = "sd_0";
		};

		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
		 *  DAT2, DAT3, CMD, CLK for SD respectively.
		 */
		conf-cmd-data {
			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
			       "I2S2_IN","I2S4_OUT";
			input-enable;
			drive-strength = <8>;
			bias-pull-up;
		};
		conf-clk {
			pins = "I2S3_OUT";
			drive-strength = <12>;
			bias-pull-down;
		};
		conf-cd {
			pins = "TXD3";
			bias-pull-up;
		};
	};

	sd0_pins_uhs: sd0-pins-uhs {
		mux {
			function = "sd";
			groups = "sd_0";
		};

		conf-cmd-data {
			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
			       "I2S2_IN","I2S4_OUT";
			input-enable;
			bias-pull-up;
		};

		conf-clk {
			pins = "I2S3_OUT";
			bias-pull-down;
		};
	};

	/* Serial NAND is shared pin with SPI-NOR */
	serial_nand_pins: serial-nand-pins {
		mux {
			function = "flash";
			groups = "snfi";
		};
	};

	spic0_pins: spic0-pins {
		mux {
			function = "spi";
			groups = "spic0_0";
		};
	};

	spic1_pins: spic1-pins {
		mux {
			function = "spi";
			groups = "spic1_0";
		};
	};

	/* SPI-NOR is shared pin with serial NAND */
	spi_nor_pins: spi-nor-pins {
		mux {
			function = "flash";
			groups = "spi_nor";
		};
	};

	/* serial NAND is shared pin with SPI-NOR */
	serial_nand_pins: serial-nand-pins {
		mux {
			function = "flash";
			groups = "snfi";
		};
	};

	uart0_pins: uart0-pins {
		mux {
			function = "uart";
			groups = "uart0_0_tx_rx" ;
		};
	};

	uart2_pins: uart2-pins {
		mux {
			function = "uart";
			groups = "uart2_1_tx_rx" ;
		};
	};

	watchdog_pins: watchdog-pins {
		mux {
			function = "watchdog";
			groups = "watchdog";
		};
	};

	wmac_pins: wmac-pins {
		mux {
			function = "antsel";
			groups = "antsel0", "antsel1", "antsel2", "antsel3",
				 "antsel4", "antsel5", "antsel6", "antsel7",
				 "antsel8", "antsel9", "antsel12", "antsel13",
				 "antsel14", "antsel15", "antsel16", "antsel17";
		};
	};
};

&pwm {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm7_pins>;
	status = "okay";
};

&pwrap {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_bus_pins>;

	status = "okay";
};

&sata {
	status = "okay";
};

&sata_phy {
	status = "okay";
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic0_pins>;
	status = "okay";
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic1_pins>;
	status = "okay";
};

&ssusb {
	vusb33-supply = <&reg_3p3v>;
	vbus-supply = <&reg_5v>;
	status = "okay";
};

&u3phy {
	status = "okay";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
	status = "okay";
};

&watchdog {
	pinctrl-names = "default";
	pinctrl-0 = <&watchdog_pins>;
	status = "okay";
};

&wmac {
	pinctrl-names = "default";
	pinctrl-0 = <&wmac_pins>;
	status = "okay";
};