code:
Coherency fabric
----------------
Available on Marvell SOCs: Armada 370, Armada 375, Armada 38x and Armada XP

Required properties:

- compatible: the possible values are:

 * "marvell,coherency-fabric", to be used for the coherency fabric of
   the Armada 370 and Armada XP.

 * "marvell,armada-375-coherency-fabric", for the Armada 375 coherency
   fabric.

 * "marvell,armada-380-coherency-fabric", for the Armada 38x coherency
   fabric.

- reg: Should contain coherency fabric registers location and
  length.

 * For "marvell,coherency-fabric", the first pair for the coherency
   fabric registers, second pair for the per-CPU fabric registers.

 * For "marvell,armada-375-coherency-fabric", only one pair is needed
   for the per-CPU fabric registers.

 * For "marvell,armada-380-coherency-fabric", only one pair is needed
   for the per-CPU fabric registers.

Optional properties:

- broken-idle: boolean to set when the Idle mode is not supported by the
  hardware.

Examples:

coherency-fabric@d0020200 {
	compatible = "marvell,coherency-fabric";
	reg = <0xd0020200 0xb0>,
		<0xd0021810 0x1c>;

};

coherency-fabric@21810 {
	compatible = "marvell,armada-375-coherency-fabric";
	reg = <0x21810 0x1c>;
};


code:
Marvell Armada CP110 System Controller
======================================

The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
SoCs. It contains system controllers, which provide several registers
giving access to numerous features: clocks, pin-muxing and many other
SoC configuration items. This DT binding allows to describe these
system controllers.

For the top level node:
 - compatible: must be: "syscon", "simple-mfd";
 - reg: register area of the CP110 system controller

SYSTEM CONTROLLER 0
===================

Clocks:
-------

The Device Tree node representing this System Controller 0 provides a
number of clocks:

 - a set of core clocks
 - a set of gatable clocks

Those clocks can be referenced by other Device Tree nodes using two
cells:
 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
   gatable clocks.
 - The second cell identifies the particular core clock or gatable
   clocks.

The following clocks are available:
 - Core clocks
   - 0 0	APLL
   - 0 1	PPv2 core
   - 0 2	EIP
   - 0 3	Core
   - 0 4	NAND core
   - 0 5	SDIO core
 - Gatable clocks
   - 1 0	Audio
   - 1 1	Comm Unit
   - 1 2	NAND
   - 1 3	PPv2
   - 1 4	SDIO
   - 1 5	MG Domain
   - 1 6	MG Core
   - 1 7	XOR1
   - 1 8	XOR0
   - 1 9	GOP DP
   - 1 11	PCIe x1 0
   - 1 12	PCIe x1 1
   - 1 13	PCIe x4
   - 1 14	PCIe / XOR
   - 1 15	SATA
   - 1 16	SATA USB
   - 1 17	Main
   - 1 18	SD/MMC/GOP
   - 1 21	Slow IO (SPI, NOR, BootROM, I2C, UART)
   - 1 22	USB3H0
   - 1 23	USB3H1
   - 1 24	USB3 Device
   - 1 25	EIP150
   - 1 26	EIP197

Required properties:

 - compatible: must be:
     "marvell,cp110-clock"
 - #clock-cells: must be set to 2

Pinctrl:
--------

For common binding part and usage, refer to the file
Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.

Required properties:

- compatible: "marvell,armada-7k-pinctrl", "marvell,armada-8k-cpm-pinctrl",
  "marvell,armada-8k-cps-pinctrl" or "marvell,cp115-standalone-pinctrl"
  depending on the specific variant of the SoC being used.

Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
only for more detailed description in this document.

name	pins	functions
================================================================================
mpp0	0	gpio, dev(ale1), au(i2smclk), ge0(rxd3), tdm(pclk), ptp(pulse), mss_i2c(sda), uart0(rxd), sata0(present_act), ge(mdio)
mpp1	1	gpio, dev(ale0), au(i2sdo_spdifo), ge0(rxd2), tdm(drx), ptp(clk), mss_i2c(sck), uart0(txd), sata1(present_act), ge(mdc)
mpp2	2	gpio, dev(ad15), au(i2sextclk), ge0(rxd1), tdm(dtx), mss_uart(rxd), ptp(pclk_out), i2c1(sck), uart1(rxd), sata0(present_act), xg(mdc)
mpp3	3	gpio, dev(ad14), au(i2slrclk), ge0(rxd0), tdm(fsync), mss_uart(txd), pcie(rstoutn), i2c1(sda), uart1(txd), sata1(present_act), xg(mdio)
mpp4	4	gpio, dev(ad13), au(i2sbclk), ge0(rxctl), tdm(rstn), mss_uart(rxd), uart1(cts), pcie0(clkreq), uart3(rxd), ge(mdc)
mpp5	5	gpio, dev(ad12), au(i2sdi), ge0(rxclk), tdm(intn), mss_uart(txd), uart1(rts), pcie1(clkreq), uart3(txd), ge(mdio)
mpp6	6	gpio, dev(ad11), ge0(txd3), spi0(csn2), au(i2sextclk), sata1(present_act), pcie2(clkreq), uart0(rxd), ptp(pulse)
mpp7	7	gpio, dev(ad10), ge0(txd2), spi0(csn1), spi1(csn1), sata0(present_act), led(data), uart0(txd), ptp(clk)
mpp8	8	gpio, dev(ad9), ge0(txd1), spi0(csn0), spi1(csn0), uart0(cts), led(stb), uart2(rxd), ptp(pclk_out), synce1(clk)
mpp9	9	gpio, dev(ad8), ge0(txd0), spi0(mosi), spi1(mosi), pcie(rstoutn), synce2(clk)
mpp10	10	gpio, dev(readyn), ge0(txctl), spi0(miso), spi1(miso), uart0(cts), sata1(present_act)
mpp11	11	gpio, dev(wen1), ge0(txclkout), spi0(clk), spi1(clk), uart0(rts), led(clk), uart2(txd), sata0(present_act)
mpp12	12	gpio, dev(clk_out), nf(rbn1), spi1(csn1), ge0(rxclk)
mpp13	13	gpio, dev(burstn), nf(rbn0), spi1(miso), ge0(rxctl), mss_spi(miso)
mpp14	14	gpio, dev(bootcsn), dev(csn0), spi1(csn0), spi0(csn3), au(i2sextclk), spi0(miso), sata0(present_act), mss_spi(csn)
mpp15	15	gpio, dev(ad7), spi1(mosi), spi0(mosi), mss_spi(mosi), ptp(pulse_cp2cp)
mpp16	16	gpio, dev(ad6), spi1(clk), mss_spi(clk)
mpp17	17	gpio, dev(ad5), ge0(txd3)
mpp18	18	gpio, dev(ad4), ge0(txd2), ptp(clk_cp2cp)
mpp19	19	gpio, dev(ad3), ge0(txd1), wakeup(out_cp2cp)
mpp20	20	gpio, dev(ad2), ge0(txd0)
mpp21	21	gpio, dev(ad1), ge0(txctl), sei(in_cp2cp)
mpp22	22	gpio, dev(ad0), ge0(txclkout), wakeup(in_cp2cp)
mpp23	23	gpio, dev(a1), au(i2smclk), link(rd_in_cp2cp)
mpp24	24	gpio, dev(a0), au(i2slrclk)
mpp25	25	gpio, dev(oen), au(i2sdo_spdifo)
mpp26	26	gpio, dev(wen0), au(i2sbclk)
mpp27	27	gpio, dev(csn0), spi1(miso), mss_gpio4, ge0(rxd3), spi0(csn4), ge(mdio), sata0(present_act), uart0(rts), rei(in_cp2cp)
mpp28	28	gpio, dev(csn1), spi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), pcie2(clkreq), ptp(pulse), ge(mdc), sata1(present_act), uart0(cts), led(data)
mpp29	29	gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), pcie1(clkreq), ptp(clk), mss_i2c(sda), sata0(present_act), uart0(rxd), led(stb)
mpp30	30	gpio, dev(csn3), spi1(clk), mss_gpio7, ge0(rxd0), spi0(csn7), pcie0(clkreq), ptp(pclk_out), mss_i2c(sck), sata1(present_act), uart0(txd), led(clk)
mpp31	31	gpio, dev(a2), mss_gpio4, pcie(rstoutn), ge(mdc)
mpp32	32	gpio, mii(col), mii(txerr), mss_spi(miso), tdm(drx), au(i2sextclk), au(i2sdi), ge(mdio), sdio(v18_en), pcie1(clkreq), mss_gpio0
mpp33	33	gpio, mii(txclk), sdio(pwr10), mss_spi(csn), tdm(fsync), au(i2smclk), sdio(bus_pwr), xg(mdio), pcie2(clkreq), mss_gpio1
mpp34	34	gpio, mii(rxerr), sdio(pwr11), mss_spi(mosi), tdm(dtx), au(i2slrclk), sdio(wr_protect), ge(mdc), pcie0(clkreq), mss_gpio2
mpp35	35	gpio, sata1(present_act), i2c1(sda), mss_spi(clk), tdm(pclk), au(i2sdo_spdifo), sdio(card_detect), xg(mdio), ge(mdio), pcie(rstoutn), mss_gpio3
mpp36	36	gpio, synce2(clk), i2c1(sck), ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(mdc), ge(mdc), pcie2(clkreq), mss_gpio5
mpp37	37	gpio, uart2(rxd), i2c0(sck), ptp(pclk_out), tdm(intn), mss_i2c(sck), sata1(present_act), ge(mdc), xg(mdc), pcie1(clkreq), mss_gpio6, link(rd_out_cp2cp)
mpp38	38	gpio, uart2(txd), i2c0(sda), ptp(pulse), tdm(rstn), mss_i2c(sda), sata0(present_act), ge(mdio), xg(mdio), au(i2sextclk), mss_gpio7, ptp(pulse_cp2cp)
mpp39	39	gpio, sdio(wr_protect), au(i2sbclk), ptp(clk), spi0(csn1), sata1(present_act), mss_gpio0
mpp40	40	gpio, sdio(pwr11), synce1(clk), mss_i2c(sda), au(i2sdo_spdifo), ptp(pclk_out), spi0(clk), uart1(txd), ge(mdio), sata0(present_act), mss_gpio1
mpp41	41	gpio, sdio(pwr10), sdio(bus_pwr), mss_i2c(sck), au(i2slrclk), ptp(pulse), spi0(mosi), uart1(rxd), ge(mdc), sata1(present_act), mss_gpio2, rei(out_cp2cp)
mpp42	42	gpio, sdio(v18_en), sdio(wr_protect), synce2(clk), au(i2smclk), mss_uart(txd), spi0(miso), uart1(cts), xg(mdc), sata0(present_act), mss_gpio4
mpp43	43	gpio, sdio(card_detect), synce1(clk), au(i2sextclk), mss_uart(rxd), spi0(csn0), uart1(rts), xg(mdio), sata1(present_act), mss_gpio5, wakeup(out_cp2cp)
mpp44	44	gpio, ge1(txd2), uart0(rts), ptp(clk_cp2cp)
mpp45	45	gpio, ge1(txd3), uart0(txd), pcie(rstoutn)
mpp46	46	gpio, ge1(txd1), uart1(rts)
mpp47	47	gpio, ge1(txd0), spi1(clk), uart1(txd), ge(mdc)
mpp48	48	gpio, ge1(txctl_txen), spi1(mosi), xg(mdc), wakeup(in_cp2cp)
mpp49	49	gpio, ge1(txclkout), mii(crs), spi1(miso), uart1(rxd), ge(mdio), pcie0(clkreq), sdio(v18_en), sei(out_cp2cp)
mpp50	50	gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg(mdio), sdio(pwr11)
mpp51	51	gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10)
mpp52	52	gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq)
mpp53	53	gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led)
mpp54	54	gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio_wp(wr_protect)
mpp55	55	gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio_cd(card_detect)
mpp56	56	gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk)
mpp57	57	gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd)
mpp58	58	gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0)
mpp59	59	gpio, mss_gpio7, synce2(clk), tdm(fsync), au(i2slrclk), spi0(csn0), uart0(cts), led(stb), uart1(txd), sdio(d1)
mpp60	60	gpio, mss_gpio6, ptp(pulse), tdm(dtx), au(i2smclk), spi0(csn1), uart0(rts), led(data), uart1(rxd), sdio(d2)
mpp61	61	gpio, mss_gpio5, ptp(clk), tdm(pclk), au(i2sextclk), spi0(csn2), uart0(txd), uart2(txd), sata1(present_act), ge(mdio), sdio(d3)
mpp62	62	gpio, mss_gpio4, synce1(clk), ptp(pclk_out), sata1(present_act), spi0(csn3), uart0(rxd), uart2(rxd), sata0(present_act), ge(mdc)

GPIO:
-----

For common binding part and usage, refer to
Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.

Required properties:

- compatible: "marvell,armada-8k-gpio"

- offset: offset address inside the syscon block

Example:

CP110_LABEL(syscon0): system-controller@440000 {
	compatible = "syscon", "simple-mfd";
	reg = <0x440000 0x1000>;

	CP110_LABEL(clk): clock {
		compatible = "marvell,cp110-clock";
		#clock-cells = <2>;
	};

	CP110_LABEL(pinctrl): pinctrl {
		compatible = "marvell,armada-8k-cpm-pinctrl";
	};

	CP110_LABEL(gpio1): gpio@100 {
		compatible = "marvell,armada-8k-gpio";
		offset = <0x100>;
		ngpios = <32>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
	};

};

SYSTEM CONTROLLER 1
===================

Thermal:
--------

The thermal IP can probe the temperature all around the processor. It
may feature several channels, each of them wired to one sensor.

It is possible to setup an overheat interrupt by giving at least one
critical point to any subnode of the thermal-zone node.

For common binding part and usage, refer to
Documentation/devicetree/bindings/thermal/thermal*.yaml

Required properties:
- compatible: must be one of:
  * marvell,armada-cp110-thermal
- reg: register range associated with the thermal functions.

Optional properties:
- interrupts-extended: overheat interrupt handle. Should point to
  a line of the ICU-SEI irqchip (116 is what is usually used by the
  firmware). The ICU-SEI will redirect towards interrupt line #37 of the
  AP SEI which is shared across all CPs.
  See interrupt-controller/interrupts.txt
- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
  to this IP and represents the channel ID. There is one sensor per
  channel. O refers to the thermal IP internal channel.

Example:
CP110_LABEL(syscon1): system-controller@6f8000 {
	compatible = "syscon", "simple-mfd";
	reg = <0x6f8000 0x1000>;

	CP110_LABEL(thermal): thermal-sensor@70 {
		compatible = "marvell,armada-cp110-thermal";
		reg = <0x70 0x10>;
		interrupts-extended = <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
		#thermal-sensor-cells = <1>;
	};
};

repo_name: angery/linux


code:
Marvell Kirkwood Platforms Device Tree Bindings
-----------------------------------------------

Boards with a SoC of the Marvell Kirkwood
shall have the following property:

Required root node property:

compatible: must contain "marvell,kirkwood";

In order to support the kirkwood cpufreq driver, there must be a node
cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave",
where the "powersave" clock is a gating clock used to switch the CPU
between the "cpu_clk" and the "ddrclk".

Example:

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
		      device_type = "cpu";
		      compatible = "marvell,sheeva-88SV131";
		      clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
		      clock-names = "cpu_clk", "ddrclk", "powersave";
		};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/marvell/marvell,ac5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell Alleycat5/5X Platforms

maintainers:
  - Chris Packham <chris.packham@alliedtelesis.co.nz>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: Alleycat5 (98DX25xx) Reference Design
        items:
          - enum:
              - marvell,rd-ac5
          - const: marvell,ac5

      - description: Alleycat5X (98DX35xx) Reference Design
        items:
          - enum:
              - marvell,rd-ac5x
          - const: marvell,ac5x
          - const: marvell,ac5

additionalProperties: true

...


code:
Marvell Dove Platforms Device Tree Bindings
-----------------------------------------------

Boards with a Marvell Dove SoC shall have the following properties:

Required root node property:
- compatible: must contain "marvell,dove";

* Global Configuration registers

Global Configuration registers of Dove SoC are shared by a syscon node.

Required properties:
- compatible: must contain "marvell,dove-global-config" and "syscon".
- reg: base address and size of the Global Configuration registers.

Example:

gconf: global-config@e802c {
	compatible = "marvell,dove-global-config", "syscon";
	reg = <0xe802c 0x14>;
};


code:
Marvell Kirkwood SoC Family Device Tree Bindings
------------------------------------------------

Boards with a SoC of the Marvell Kirkwook family, eg 88f6281

* Required root node properties:
compatible: must contain "marvell,kirkwood"

In addition, the above compatible shall be extended with the specific
SoC. Currently known SoC compatibles are:

"marvell,kirkwood-88f6192"
"marvell,kirkwood-88f6281"
"marvell,kirkwood-88f6282"
"marvell,kirkwood-88f6283"
"marvell,kirkwood-88f6702"
"marvell,kirkwood-98DX4122"

And in addition, the compatible shall be extended with the specific
board. Currently known boards are:

"buffalo,linkstation-lsqvl"
"buffalo,linkstation-lsvl"
"buffalo,linkstation-lswsxl"
"buffalo,linkstation-lswxl"
"buffalo,linkstation-lswvl"
"buffalo,lschlv2"
"buffalo,lsxhl"
"buffalo,lsxl"
"cloudengines,pogo02"
"cloudengines,pogoplugv4"
"dlink,dns-320"
"dlink,dns-320-a1"
"dlink,dns-325"
"dlink,dns-325-a1"
"dlink,dns-kirkwood"
"excito,b3"
"globalscale,dreamplug-003-ds2001"
"globalscale,guruplug"
"globalscale,guruplug-server-plus"
"globalscale,sheevaplug"
"globalscale,sheevaplug"
"globalscale,sheevaplug-esata"
"globalscale,sheevaplug-esata-rev13"
"iom,iconnect"
"iom,iconnect-1.1"
"iom,ix2-200"
"keymile,km_kirkwood"
"lacie,cloudbox"
"lacie,inetspace_v2"
"lacie,laplug"
"lacie,nas2big"
"lacie,netspace_lite_v2"
"lacie,netspace_max_v2"
"lacie,netspace_mini_v2"
"lacie,netspace_v2"
"marvell,db-88f6281-bp"
"marvell,db-88f6282-bp"
"marvell,mv88f6281gtw-ge"
"marvell,rd88f6281"
"marvell,rd88f6281"
"marvell,rd88f6281-a0"
"marvell,rd88f6281-a1"
"mpl,cec4"
"mpl,cec4-10"
"netgear,readynas"
"netgear,readynas"
"netgear,readynas-duo-v2"
"netgear,readynas-nv+-v2"
"plathome,openblocks-a6"
"plathome,openblocks-a7"
"raidsonic,ib-nas6210"
"raidsonic,ib-nas6210-b"
"raidsonic,ib-nas6220"
"raidsonic,ib-nas6220-b"
"raidsonic,ib-nas62x0"
"seagate,dockstar"
"seagate,goflexnet"
"synology,ds109"
"synology,ds110jv10"
"synology,ds110jv20"
"synology,ds110jv30"
"synology,ds111"
"synology,ds209"
"synology,ds210jv10"
"synology,ds210jv20"
"synology,ds212"
"synology,ds212jv10"
"synology,ds212jv20"
"synology,ds212pv10"
"synology,ds409"
"synology,ds409slim"
"synology,ds410j"
"synology,ds411"
"synology,ds411j"
"synology,ds411slim"
"synology,ds413jv10"
"synology,rs212"
"synology,rs409"
"synology,rs411"
"synology,rs812"
"usi,topkick"
"usi,topkick-1281P2"
"zyxel,nsa310"
"zyxel,nsa310a"


code:
Marvell Orion SoC Family Device Tree Bindings
---------------------------------------------

Boards with a SoC of the Marvell Orion family, eg 88f5181

* Required root node properties:
compatible: must contain "marvell,orion5x"

In addition, the above compatible shall be extended with the specific
SoC. Currently known SoC compatibles are:

"marvell,orion5x-88f5181"
"marvell,orion5x-88f5182"

And in addition, the compatible shall be extended with the specific
board. Currently known boards are:

"buffalo,lsgl"
"buffalo,lswsgl"
"buffalo,lswtgl"
"lacie,ethernet-disk-mini-v2"
"lacie,d2-network"
"marvell,rd-88f5182-nas"
"maxtor,shared-storage-2"
"netgear,wnr854t"


code:
MVEBU CPU Config registers
--------------------------

MVEBU (Marvell SOCs: Armada 370/XP)

Required properties:

- compatible: one of:
	- "marvell,armada-370-cpu-config"
	- "marvell,armada-xp-cpu-config"

- reg: Should contain CPU config registers location and length, in
  their per-CPU variant

Example:

	cpu-config@21000 {
		compatible = "marvell,armada-xp-cpu-config";
		reg = <0x21000 0x8>;
	};


code:
MVEBU System Controller
-----------------------
MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x)

Required properties:

- compatible: one of:
	- "marvell,orion-system-controller"
	- "marvell,armada-370-xp-system-controller"
	- "marvell,armada-375-system-controller"
- reg: Should contain system controller registers location and length.

Example:

	system-controller@d0018200 {
		compatible = "marvell,armada-370-xp-system-controller";
		reg = <0xd0018200 0x500>;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mediatek.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek SoC based Platforms

maintainers:
  - Sean Wang <sean.wang@mediatek.com>
  - Matthias Brugger <matthias.bgg@gmail.com>
description: |
  Boards with a MediaTek SoC shall have the following properties.

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt2701-evb
          - const: mediatek,mt2701

      - items:
          - enum:
              - mediatek,mt2712-evb
          - const: mediatek,mt2712
      - items:
          - enum:
              - mediatek,mt6580-evbp1
          - const: mediatek,mt6580
      - items:
          - enum:
              - prestigio,pmt5008-3g
          - const: mediatek,mt6582
      - items:
          - enum:
              - fairphone,fp1
              - mundoreader,bq-aquaris5
          - const: mediatek,mt6589
      - items:
          - enum:
              - mediatek,mt6592-evb
          - const: mediatek,mt6592
      - items:
          - enum:
              - mediatek,mt6755-evb
          - const: mediatek,mt6755
      - items:
          - enum:
              - mediatek,mt6765-evb
          - const: mediatek,mt6765
      - items:
          - enum:
              - mediatek,mt6779-evb
          - const: mediatek,mt6779
      - items:
          - enum:
              - mediatek,mt6795-evb
              - sony,xperia-m5
          - const: mediatek,mt6795
      - items:
          - enum:
              - archermind,mt6797-x20-dev
              - mediatek,mt6797-evb
          - const: mediatek,mt6797
      - items:
          - enum:
              - bananapi,bpi-r64
              - mediatek,mt7622-rfb1
          - const: mediatek,mt7622
      - items:
          - enum:
              - mediatek,mt7623a-rfb-emmc
              - mediatek,mt7623a-rfb-nand
              - mediatek,mt7623n-rfb-emmc
              - bananapi,bpi-r2
          - const: mediatek,mt7623

      - items:
          - enum:
              - mediatek,mt7629-rfb
          - const: mediatek,mt7629
      - items:
          - enum:
              - bananapi,bpi-r3
              - mediatek,mt7986a-rfb
          - const: mediatek,mt7986a
      - items:
          - enum:
              - mediatek,mt7986b-rfb
          - const: mediatek,mt7986b
      - items:
          - enum:
              - mediatek,mt8127-moose
          - const: mediatek,mt8127
      - items:
          - enum:
              - mediatek,mt8135-evbp1
          - const: mediatek,mt8135
      - items:
          - enum:
              - mediatek,mt8167-pumpkin
          - const: mediatek,mt8167
      - description: Google Elm (Acer Chromebook R13)
        items:
          - const: google,elm-rev8
          - const: google,elm-rev7
          - const: google,elm-rev6
          - const: google,elm-rev5
          - const: google,elm-rev4
          - const: google,elm-rev3
          - const: google,elm
          - const: mediatek,mt8173
      - description: Google Hana (Lenovo Chromebook N23 Yoga, C330, 300e,...)
        items:
          - const: google,hana-rev6
          - const: google,hana-rev5
          - const: google,hana-rev4
          - const: google,hana-rev3
          - const: google,hana
          - const: mediatek,mt8173
      - description: Google Hana rev7 (Poin2 Chromebook 11C)
        items:
          - const: google,hana-rev7
          - const: mediatek,mt8173
      - items:
          - enum:
              - mediatek,mt8173-evb
          - const: mediatek,mt8173
      - items:
          - enum:
              - mediatek,mt8183-evb
          - const: mediatek,mt8183
      - description: Google Hayato
        items:
          - const: google,hayato-rev1
          - const: google,hayato
          - const: mediatek,mt8192
      - description: Google Spherion (Acer Chromebook 514)
        items:
          - const: google,spherion-rev3
          - const: google,spherion-rev2
          - const: google,spherion-rev1
          - const: google,spherion-rev0
          - const: google,spherion
          - const: mediatek,mt8192
      - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)
        items:
          - enum:
              - google,tomato-rev2
              - google,tomato-rev1
          - const: google,tomato
          - const: mediatek,mt8195
      - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)
        items:
          - const: google,tomato-rev4
          - const: google,tomato-rev3
          - const: google,tomato
          - const: mediatek,mt8195
      - items:
          - enum:
              - mediatek,mt8186-evb
          - const: mediatek,mt8186
      - items:
          - enum:
              - mediatek,mt8192-evb
          - const: mediatek,mt8192
      - items:
          - enum:
              - mediatek,mt8195-demo
              - mediatek,mt8195-evb
          - const: mediatek,mt8195
      - description: Google Burnet (HP Chromebook x360 11MK G3 EE)
        items:
          - const: google,burnet
          - const: mediatek,mt8183
      - description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
        items:
          - enum:
              - google,krane-sku0
              - google,krane-sku176
          - const: google,krane
          - const: mediatek,mt8183
      - description: Google Cozmo (Acer Chromebook 314)
        items:
          - const: google,cozmo
          - const: mediatek,mt8183
      - description: Google Damu (ASUS Chromebook Flip CM3)
        items:
          - const: google,damu
          - const: mediatek,mt8183
      - description: Google Fennel (Lenovo IdeaPad 3 Chromebook)
        items:
          - enum:
              - google,fennel-sku0
              - google,fennel-sku1
              - google,fennel-sku2
              - google,fennel-sku6
              - google,fennel-sku7
          - const: google,fennel
          - const: mediatek,mt8183
      - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311)
        items:
          - enum:
              - google,juniper-sku16
              - google,juniper-sku17
          - const: google,juniper
          - const: mediatek,mt8183
      - description: Google Kakadu (ASUS Chromebook Detachable CM3)
        items:
          - const: google,kakadu-rev3
          - const: google,kakadu-rev2
          - const: google,kakadu
          - const: mediatek,mt8183
      - description: Google Kakadu (ASUS Chromebook Detachable CM3)
        items:
          - const: google,kakadu-rev3-sku22
          - const: google,kakadu-rev2-sku22
          - const: google,kakadu
          - const: mediatek,mt8183
      - description: Google Kappa (HP Chromebook 11a)
        items:
          - const: google,kappa
          - const: mediatek,mt8183
      - description: Google Kodama (Lenovo 10e Chromebook Tablet)
        items:
          - enum:
              - google,kodama-sku16
              - google,kodama-sku272
              - google,kodama-sku288
              - google,kodama-sku32
          - const: google,kodama
          - const: mediatek,mt8183
      - description: Google Willow (Acer Chromebook 311 C722/C722T)
        items:
          - enum:
              - google,willow-sku0
              - google,willow-sku1
          - const: google,willow
          - const: mediatek,mt8183
      - items:
          - enum:
              - mediatek,mt8183-pumpkin
          - const: mediatek,mt8183
      - items:
          - enum:
              - mediatek,mt8516-pumpkin
          - const: mediatek,mt8516

additionalProperties: true

...


code:
MediaTek AUDSYS controller
============================

The MediaTek AUDSYS controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:
	- "mediatek,mt2701-audsys", "syscon"
	- "mediatek,mt6765-audsys", "syscon"
	- "mediatek,mt6779-audio", "syscon"
	- "mediatek,mt7622-audsys", "syscon"
	- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
	- "mediatek,mt8167-audiosys", "syscon"
	- "mediatek,mt8183-audiosys", "syscon"
	- "mediatek,mt8192-audsys", "syscon"
	- "mediatek,mt8516-audsys", "syscon"
- #clock-cells: Must be 1

The AUDSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Required sub-nodes:
-------
For common binding part and usage, refer to
../sonud/mt2701-afe-pcm.txt.

Example:

	audsys: clock-controller@11220000 {
		compatible = "mediatek,mt7622-audsys", "syscon";
		reg = <0 0x11220000 0 0x2000>;
		#clock-cells = <1>;

		afe: audio-controller {
			...
		};
	};


code:
Mediatek bdpsys controller
============================

The Mediatek bdpsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be:
	- "mediatek,mt2701-bdpsys", "syscon"
	- "mediatek,mt2712-bdpsys", "syscon"
	- "mediatek,mt7623-bdpsys", "mediatek,mt2701-bdpsys", "syscon"
- #clock-cells: Must be 1

The bdpsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

bdpsys: clock-controller@1c000000 {
	compatible = "mediatek,mt2701-bdpsys", "syscon";
	reg = <0 0x1c000000 0 0x1000>;
	#clock-cells = <1>;
};


code:
MediaTek CAMSYS controller
============================

The MediaTek camsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:
	- "mediatek,mt6765-camsys", "syscon"
	- "mediatek,mt6779-camsys", "syscon"
	- "mediatek,mt8183-camsys", "syscon"
- #clock-cells: Must be 1

The camsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

camsys: camsys@1a000000  {
	compatible = "mediatek,mt8183-camsys", "syscon";
	reg = <0 0x1a000000  0 0x1000>;
	#clock-cells = <1>;
};


code:
Mediatek ethsys controller
============================

The Mediatek ethsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be:
	- "mediatek,mt2701-ethsys", "syscon"
	- "mediatek,mt7622-ethsys", "syscon"
	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
	- "mediatek,mt7629-ethsys", "syscon"
	- "mediatek,mt7986-ethsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1

The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

ethsys: clock-controller@1b000000 {
	compatible = "mediatek,mt2701-ethsys", "syscon";
	reg = <0 0x1b000000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
};


code:
MediaTek g3dsys controller
============================

The MediaTek g3dsys controller provides various clocks and reset controller to
the GPU.

Required Properties:

- compatible: Should be:
	- "mediatek,mt2701-g3dsys", "syscon":
		for MT2701 SoC
	- "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
		for MT7623 SoC
- #clock-cells: Must be 1
- #reset-cells: Must be 1

The g3dsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

g3dsys: clock-controller@13000000 {
	compatible = "mediatek,mt7623-g3dsys",
		     "mediatek,mt2701-g3dsys",
		     "syscon";
	reg = <0 0x13000000 0 0x200>;
	#clock-cells = <1>;
	#reset-cells = <1>;
};


code:
Mediatek hifsys controller
============================

The Mediatek hifsys controller provides various clocks and reset
outputs to the system.

Required Properties:

- compatible: Should be:
	- "mediatek,mt2701-hifsys", "syscon"
	- "mediatek,mt7622-hifsys", "syscon"
	- "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon"
- #clock-cells: Must be 1

The hifsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

hifsys: clock-controller@1a000000 {
	compatible = "mediatek,mt2701-hifsys", "syscon";
	reg = <0 0x1a000000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
};


code:
Mediatek imgsys controller
============================

The Mediatek imgsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:
	- "mediatek,mt2701-imgsys", "syscon"
	- "mediatek,mt2712-imgsys", "syscon"
	- "mediatek,mt6765-imgsys", "syscon"
	- "mediatek,mt6779-imgsys", "syscon"
	- "mediatek,mt6797-imgsys", "syscon"
	- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
	- "mediatek,mt8167-imgsys", "syscon"
	- "mediatek,mt8173-imgsys", "syscon"
	- "mediatek,mt8183-imgsys", "syscon"
- #clock-cells: Must be 1

The imgsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

imgsys: clock-controller@15000000 {
	compatible = "mediatek,mt8173-imgsys", "syscon";
	reg = <0 0x15000000 0 0x1000>;
	#clock-cells = <1>;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek Infrastructure System Configuration Controller

maintainers:
  - Matthias Brugger <matthias.bgg@gmail.com>

description:
  The Mediatek infracfg controller provides various clocks and reset outputs
  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
  and reset values in <dt-bindings/reset/mt*-reset.h> and
  <dt-bindings/reset/mt*-resets.h>.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt2701-infracfg
              - mediatek,mt2712-infracfg
              - mediatek,mt6765-infracfg
              - mediatek,mt6795-infracfg
              - mediatek,mt6779-infracfg_ao
              - mediatek,mt6797-infracfg
              - mediatek,mt7622-infracfg
              - mediatek,mt7629-infracfg
              - mediatek,mt7986-infracfg
              - mediatek,mt8135-infracfg
              - mediatek,mt8167-infracfg
              - mediatek,mt8173-infracfg
              - mediatek,mt8183-infracfg
              - mediatek,mt8516-infracfg
          - const: syscon
      - items:
          - const: mediatek,mt7623-infracfg
          - const: mediatek,mt2701-infracfg
          - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

if:
  properties:
    compatible:
      contains:
        enum:
          - mediatek,mt2701-infracfg
          - mediatek,mt2712-infracfg
          - mediatek,mt6795-infracfg
          - mediatek,mt7622-infracfg
          - mediatek,mt7986-infracfg
          - mediatek,mt8135-infracfg
          - mediatek,mt8173-infracfg
          - mediatek,mt8183-infracfg
then:
  required:
    - '#reset-cells'

additionalProperties: false

examples:
  - |
    infracfg: clock-controller@10001000 {
        compatible = "mediatek,mt8173-infracfg", "syscon";
        reg = <0x10001000 0x1000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
    };


code:
Mediatek ipesys controller
============================

The Mediatek ipesys controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:
	- "mediatek,mt6779-ipesys", "syscon"
- #clock-cells: Must be 1

The ipesys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

ipesys: clock-controller@1b000000 {
	compatible = "mediatek,mt6779-ipesys", "syscon";
	reg = <0 0x1b000000 0 0x1000>;
	#clock-cells = <1>;
};


code:
Mediatek IPU controller
============================

The Mediatek ipu controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:
	- "mediatek,mt8183-ipu_conn", "syscon"
	- "mediatek,mt8183-ipu_adl", "syscon"
	- "mediatek,mt8183-ipu_core0", "syscon"
	- "mediatek,mt8183-ipu_core1", "syscon"
- #clock-cells: Must be 1

The ipu controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

ipu_conn: syscon@19000000 {
	compatible = "mediatek,mt8183-ipu_conn", "syscon";
	reg = <0 0x19000000 0 0x1000>;
	#clock-cells = <1>;
};

ipu_adl: syscon@19010000 {
	compatible = "mediatek,mt8183-ipu_adl", "syscon";
	reg = <0 0x19010000 0 0x1000>;
	#clock-cells = <1>;
};

ipu_core0: syscon@19180000 {
	compatible = "mediatek,mt8183-ipu_core0", "syscon";
	reg = <0 0x19180000 0 0x1000>;
	#clock-cells = <1>;
};

ipu_core1: syscon@19280000 {
	compatible = "mediatek,mt8183-ipu_core1", "syscon";
	reg = <0 0x19280000 0 0x1000>;
	#clock-cells = <1>;
};


code:
Mediatek jpgdecsys controller
============================

The Mediatek jpgdecsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be:
	- "mediatek,mt2712-jpgdecsys", "syscon"
- #clock-cells: Must be 1

The jpgdecsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

jpgdecsys: syscon@19000000 {
	compatible = "mediatek,mt2712-jpgdecsys", "syscon";
	reg = <0 0x19000000 0 0x1000>;
	#clock-cells = <1>;
};


code:
Mediatek mcucfg controller
============================

The Mediatek mcucfg controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:
	- "mediatek,mt2712-mcucfg", "syscon"
	- "mediatek,mt8183-mcucfg", "syscon"
- #clock-cells: Must be 1

The mcucfg controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

mcucfg: syscon@10220000 {
	compatible = "mediatek,mt2712-mcucfg", "syscon";
	reg = <0 0x10220000 0 0x1000>;
	#clock-cells = <1>;
};


code:
Mediatek mfgcfg controller
============================

The Mediatek mfgcfg controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:
	- "mediatek,mt2712-mfgcfg", "syscon"
	- "mediatek,mt6779-mfgcfg", "syscon"
	- "mediatek,mt8167-mfgcfg", "syscon"
	- "mediatek,mt8183-mfgcfg", "syscon"
- #clock-cells: Must be 1

The mfgcfg controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

mfgcfg: syscon@13000000 {
	compatible = "mediatek,mt2712-mfgcfg", "syscon";
	reg = <0 0x13000000 0 0x1000>;
	#clock-cells = <1>;
};


code:
Mediatek mipi0a (mipi_rx_ana_csi0a) controller
============================

The Mediatek mipi0a controller provides various clocks
to the system.

Required Properties:

- compatible: Should be one of:
	- "mediatek,mt6765-mipi0a", "syscon"
- #clock-cells: Must be 1

The mipi0a controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

The mipi0a controller also uses the common power domain from
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
The available power doamins are defined in dt-bindings/power/mt*-power.h.

Example:

mipi0a: clock-controller@11c10000 {
	compatible = "mediatek,mt6765-mipi0a", "syscon";
	reg = <0 0x11c10000 0 0x1000>;
	power-domains = <&scpsys MT6765_POWER_DOMAIN_CAM>;
	#clock-cells = <1>;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek mmsys controller

maintainers:
  - Matthias Brugger <matthias.bgg@gmail.com>

description:
  The MediaTek mmsys system controller provides clock control, routing control,
  and miscellaneous control in mmsys partition.

properties:
  $nodename:
    pattern: "^syscon@[0-9a-f]+$"

  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt2701-mmsys
              - mediatek,mt2712-mmsys
              - mediatek,mt6765-mmsys
              - mediatek,mt6779-mmsys
              - mediatek,mt6795-mmsys
              - mediatek,mt6797-mmsys
              - mediatek,mt8167-mmsys
              - mediatek,mt8173-mmsys
              - mediatek,mt8183-mmsys
              - mediatek,mt8186-mmsys
              - mediatek,mt8192-mmsys
              - mediatek,mt8365-mmsys
          - const: syscon

      - description: vdosys0 and vdosys1 are 2 display HW pipelines,
                     so mt8195 binding should be deprecated.
        deprecated: true
        items:
          - const: mediatek,mt8195-mmsys
          - const: syscon

      - items:
          - const: mediatek,mt7623-mmsys
          - const: mediatek,mt2701-mmsys
          - const: syscon

      - items:
          - const: mediatek,mt8195-vdosys0
          - const: mediatek,mt8195-mmsys
          - const: syscon

  reg:
    maxItems: 1

  power-domains:
    description:
      A phandle and PM domain specifier as defined by bindings
      of the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  mboxes:
    description:
      Using mailbox to communicate with GCE, it should have this
      property and list of phandle, mailbox specifiers. See
      Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
      for details.
    $ref: /schemas/types.yaml#/definitions/phandle-array

  mediatek,gce-client-reg:
    description:
      The register of client driver can be configured by gce with 4 arguments
      defined in this property, such as phandle of gce, subsys id,
      register offset and size.
      Each subsys id is mapping to a base address of display function blocks
      register which is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

  "#clock-cells":
    const: 1

  '#reset-cells':
    const: 1

required:
  - compatible
  - reg
  - "#clock-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/power/mt8173-power.h>
    #include <dt-bindings/gce/mt8173-gce.h>

    mmsys: syscon@14000000 {
        compatible = "mediatek,mt8173-mmsys", "syscon";
        reg = <0x14000000 0x1000>;
        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek PCIE Mirror Controller for MT7622

maintainers:
  - Lorenzo Bianconi <lorenzo@kernel.org>
  - Felix Fietkau <nbd@nbd.name>

description:
  The mediatek PCIE mirror provides a configuration interface for PCIE
  controller on MT7622 soc.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt7622-pcie-mirror
      - const: syscon

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    soc {
      #address-cells = <2>;
      #size-cells = <2>;
      pcie_mirror: pcie-mirror@10000400 {
        compatible = "mediatek,mt7622-pcie-mirror", "syscon";
        reg = <0 0x10000400 0 0x10>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek Wireless Ethernet Dispatch Controller for MT7622

maintainers:
  - Lorenzo Bianconi <lorenzo@kernel.org>
  - Felix Fietkau <nbd@nbd.name>

description:
  The mediatek wireless ethernet dispatch controller can be configured to
  intercept and handle access to the WLAN DMA queues and PCIe interrupts
  and implement hardware flow offloading from ethernet to WLAN.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt7622-wed
          - mediatek,mt7986-wed
      - const: syscon

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  memory-region:
    items:
      - description: firmware EMI region
      - description: firmware ILM region
      - description: firmware DLM region
      - description: firmware CPU DATA region
      - description: firmware BOOT region

  memory-region-names:
    items:
      - const: wo-emi
      - const: wo-ilm
      - const: wo-dlm
      - const: wo-data
      - const: wo-boot

  mediatek,wo-ccif:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: mediatek wed-wo controller interface.

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt7622-wed
    then:
      properties:
        memory-region-names: false
        memory-region: false
        mediatek,wo-ccif: false

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    soc {
      #address-cells = <2>;
      #size-cells = <2>;
      wed0: wed@1020a000 {
        compatible = "mediatek,mt7622-wed","syscon";
        reg = <0 0x1020a000 0 0x1000>;
        interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
      };
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      wed@15010000 {
        compatible = "mediatek,mt7986-wed", "syscon";
        reg = <0 0x15010000 0 0x1000>;
        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;

        memory-region = <&wo_emi>, <&wo_ilm>, <&wo_dlm>,
                        <&wo_data>, <&wo_boot>;
        memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
                              "wo-data", "wo-boot";
        mediatek,wo-ccif = <&wo_ccif0>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek PCIE WED Controller for MT7986

maintainers:
  - Lorenzo Bianconi <lorenzo@kernel.org>
  - Felix Fietkau <nbd@nbd.name>

description:
  The mediatek WED PCIE provides a configuration interface for PCIE
  controller on MT7986 soc.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt7986-wed-pcie
      - const: syscon

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    soc {
      #address-cells = <2>;
      #size-cells = <2>;
      wed_pcie: wed-pcie@10003000 {
        compatible = "mediatek,mt7986-wed-pcie",
                     "syscon";
        reg = <0 0x10003000 0 0x10>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek Functional Clock Controller for MT8186

maintainers:
  - Chun-Jie Chen <chun-jie.chen@mediatek.com>

description: |
  The clock architecture in MediaTek like below
  PLLs -->
          dividers -->
                      muxes
                           -->
                              clock gate

  The devices provide clock gate control in different IP blocks.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8186-imp_iic_wrap
          - mediatek,mt8186-mfgsys
          - mediatek,mt8186-wpesys
          - mediatek,mt8186-imgsys1
          - mediatek,mt8186-imgsys2
          - mediatek,mt8186-vdecsys
          - mediatek,mt8186-vencsys
          - mediatek,mt8186-camsys
          - mediatek,mt8186-camsys_rawa
          - mediatek,mt8186-camsys_rawb
          - mediatek,mt8186-mdpsys
          - mediatek,mt8186-ipesys
  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    imp_iic_wrap: clock-controller@11017000 {
        compatible = "mediatek,mt8186-imp_iic_wrap";
        reg = <0x11017000 0x1000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek System Clock Controller for MT8186

maintainers:
  - Chun-Jie Chen <chun-jie.chen@mediatek.com>

description: |
  The clock architecture in MediaTek like below
  PLLs -->
          dividers -->
                      muxes
                           -->
                              clock gate

  The apmixedsys provides most of PLLs which generated from SoC 26m.
  The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
  The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
  The mcusys provides mux control to select the clock source in AP MCU.
  The device nodes also provide the system control capacity for configuration.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8186-mcusys
          - mediatek,mt8186-topckgen
          - mediatek,mt8186-infracfg_ao
          - mediatek,mt8186-apmixedsys
      - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    topckgen: syscon@10000000 {
        compatible = "mediatek,mt8186-topckgen", "syscon";
        reg = <0x10000000 0x1000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek Functional Clock Controller for MT8192

maintainers:
  - Chun-Jie Chen <chun-jie.chen@mediatek.com>

description:
  The Mediatek functional clock controller provides various clocks on MT8192.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8192-scp_adsp
          - mediatek,mt8192-imp_iic_wrap_c
          - mediatek,mt8192-imp_iic_wrap_e
          - mediatek,mt8192-imp_iic_wrap_s
          - mediatek,mt8192-imp_iic_wrap_ws
          - mediatek,mt8192-imp_iic_wrap_w
          - mediatek,mt8192-imp_iic_wrap_n
          - mediatek,mt8192-msdc_top
          - mediatek,mt8192-mfgcfg
          - mediatek,mt8192-imgsys
          - mediatek,mt8192-imgsys2
          - mediatek,mt8192-vdecsys_soc
          - mediatek,mt8192-vdecsys
          - mediatek,mt8192-vencsys
          - mediatek,mt8192-camsys
          - mediatek,mt8192-camsys_rawa
          - mediatek,mt8192-camsys_rawb
          - mediatek,mt8192-camsys_rawc
          - mediatek,mt8192-ipesys
          - mediatek,mt8192-mdpsys

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    scp_adsp: clock-controller@10720000 {
        compatible = "mediatek,mt8192-scp_adsp";
        reg = <0x10720000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imp_iic_wrap_c: clock-controller@11007000 {
        compatible = "mediatek,mt8192-imp_iic_wrap_c";
        reg = <0x11007000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imp_iic_wrap_e: clock-controller@11cb1000 {
        compatible = "mediatek,mt8192-imp_iic_wrap_e";
        reg = <0x11cb1000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imp_iic_wrap_s: clock-controller@11d03000 {
        compatible = "mediatek,mt8192-imp_iic_wrap_s";
        reg = <0x11d03000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imp_iic_wrap_ws: clock-controller@11d23000 {
        compatible = "mediatek,mt8192-imp_iic_wrap_ws";
        reg = <0x11d23000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imp_iic_wrap_w: clock-controller@11e01000 {
        compatible = "mediatek,mt8192-imp_iic_wrap_w";
        reg = <0x11e01000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imp_iic_wrap_n: clock-controller@11f02000 {
        compatible = "mediatek,mt8192-imp_iic_wrap_n";
        reg = <0x11f02000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    msdc_top: clock-controller@11f10000 {
        compatible = "mediatek,mt8192-msdc_top";
        reg = <0x11f10000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    mfgcfg: clock-controller@13fbf000 {
        compatible = "mediatek,mt8192-mfgcfg";
        reg = <0x13fbf000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imgsys: clock-controller@15020000 {
        compatible = "mediatek,mt8192-imgsys";
        reg = <0x15020000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imgsys2: clock-controller@15820000 {
        compatible = "mediatek,mt8192-imgsys2";
        reg = <0x15820000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    vdecsys_soc: clock-controller@1600f000 {
        compatible = "mediatek,mt8192-vdecsys_soc";
        reg = <0x1600f000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    vdecsys: clock-controller@1602f000 {
        compatible = "mediatek,mt8192-vdecsys";
        reg = <0x1602f000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    vencsys: clock-controller@17000000 {
        compatible = "mediatek,mt8192-vencsys";
        reg = <0x17000000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    camsys: clock-controller@1a000000 {
        compatible = "mediatek,mt8192-camsys";
        reg = <0x1a000000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    camsys_rawa: clock-controller@1a04f000 {
        compatible = "mediatek,mt8192-camsys_rawa";
        reg = <0x1a04f000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    camsys_rawb: clock-controller@1a06f000 {
        compatible = "mediatek,mt8192-camsys_rawb";
        reg = <0x1a06f000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    camsys_rawc: clock-controller@1a08f000 {
        compatible = "mediatek,mt8192-camsys_rawc";
        reg = <0x1a08f000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    ipesys: clock-controller@1b000000 {
        compatible = "mediatek,mt8192-ipesys";
        reg = <0x1b000000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    mdpsys: clock-controller@1f000000 {
        compatible = "mediatek,mt8192-mdpsys";
        reg = <0x1f000000 0x1000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek System Clock Controller for MT8192

maintainers:
  - Chun-Jie Chen <chun-jie.chen@mediatek.com>

description:
  The Mediatek system clock controller provides various clocks and system configuration
  like reset and bus protection on MT8192.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8192-topckgen
          - mediatek,mt8192-infracfg
          - mediatek,mt8192-pericfg
          - mediatek,mt8192-apmixedsys
      - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    topckgen: syscon@10000000 {
        compatible = "mediatek,mt8192-topckgen", "syscon";
        reg = <0x10000000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    infracfg: syscon@10001000 {
        compatible = "mediatek,mt8192-infracfg", "syscon";
        reg = <0x10001000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    pericfg: syscon@10003000 {
        compatible = "mediatek,mt8192-pericfg", "syscon";
        reg = <0x10003000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    apmixedsys: syscon@1000c000 {
        compatible = "mediatek,mt8192-apmixedsys", "syscon";
        reg = <0x1000c000 0x1000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek Functional Clock Controller for MT8195

maintainers:
  - Chun-Jie Chen <chun-jie.chen@mediatek.com>

description:
  The clock architecture in Mediatek like below
  PLLs -->
          dividers -->
                      muxes
                           -->
                              clock gate

  The devices except apusys_pll provide clock gate control in different IP blocks.
  The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8195-scp_adsp
          - mediatek,mt8195-imp_iic_wrap_s
          - mediatek,mt8195-imp_iic_wrap_w
          - mediatek,mt8195-mfgcfg
          - mediatek,mt8195-vppsys0
          - mediatek,mt8195-wpesys
          - mediatek,mt8195-wpesys_vpp0
          - mediatek,mt8195-wpesys_vpp1
          - mediatek,mt8195-vppsys1
          - mediatek,mt8195-imgsys
          - mediatek,mt8195-imgsys1_dip_top
          - mediatek,mt8195-imgsys1_dip_nr
          - mediatek,mt8195-imgsys1_wpe
          - mediatek,mt8195-ipesys
          - mediatek,mt8195-camsys
          - mediatek,mt8195-camsys_rawa
          - mediatek,mt8195-camsys_yuva
          - mediatek,mt8195-camsys_rawb
          - mediatek,mt8195-camsys_yuvb
          - mediatek,mt8195-camsys_mraw
          - mediatek,mt8195-ccusys
          - mediatek,mt8195-vdecsys_soc
          - mediatek,mt8195-vdecsys
          - mediatek,mt8195-vdecsys_core1
          - mediatek,mt8195-vencsys
          - mediatek,mt8195-vencsys_core1
          - mediatek,mt8195-apusys_pll
  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    scp_adsp: clock-controller@10720000 {
        compatible = "mediatek,mt8195-scp_adsp";
        reg = <0x10720000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imp_iic_wrap_s: clock-controller@11d03000 {
        compatible = "mediatek,mt8195-imp_iic_wrap_s";
        reg = <0x11d03000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imp_iic_wrap_w: clock-controller@11e05000 {
        compatible = "mediatek,mt8195-imp_iic_wrap_w";
        reg = <0x11e05000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    mfgcfg: clock-controller@13fbf000 {
        compatible = "mediatek,mt8195-mfgcfg";
        reg = <0x13fbf000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    vppsys0: clock-controller@14000000 {
        compatible = "mediatek,mt8195-vppsys0";
        reg = <0x14000000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    wpesys: clock-controller@14e00000 {
        compatible = "mediatek,mt8195-wpesys";
        reg = <0x14e00000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    wpesys_vpp0: clock-controller@14e02000 {
        compatible = "mediatek,mt8195-wpesys_vpp0";
        reg = <0x14e02000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    wpesys_vpp1: clock-controller@14e03000 {
        compatible = "mediatek,mt8195-wpesys_vpp1";
        reg = <0x14e03000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    vppsys1: clock-controller@14f00000 {
        compatible = "mediatek,mt8195-vppsys1";
        reg = <0x14f00000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imgsys: clock-controller@15000000 {
        compatible = "mediatek,mt8195-imgsys";
        reg = <0x15000000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imgsys1_dip_top: clock-controller@15110000 {
        compatible = "mediatek,mt8195-imgsys1_dip_top";
        reg = <0x15110000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imgsys1_dip_nr: clock-controller@15130000 {
        compatible = "mediatek,mt8195-imgsys1_dip_nr";
        reg = <0x15130000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    imgsys1_wpe: clock-controller@15220000 {
        compatible = "mediatek,mt8195-imgsys1_wpe";
        reg = <0x15220000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    ipesys: clock-controller@15330000 {
        compatible = "mediatek,mt8195-ipesys";
        reg = <0x15330000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    camsys: clock-controller@16000000 {
        compatible = "mediatek,mt8195-camsys";
        reg = <0x16000000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    camsys_rawa: clock-controller@1604f000 {
        compatible = "mediatek,mt8195-camsys_rawa";
        reg = <0x1604f000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    camsys_yuva: clock-controller@1606f000 {
        compatible = "mediatek,mt8195-camsys_yuva";
        reg = <0x1606f000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    camsys_rawb: clock-controller@1608f000 {
        compatible = "mediatek,mt8195-camsys_rawb";
        reg = <0x1608f000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    camsys_yuvb: clock-controller@160af000 {
        compatible = "mediatek,mt8195-camsys_yuvb";
        reg = <0x160af000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    camsys_mraw: clock-controller@16140000 {
        compatible = "mediatek,mt8195-camsys_mraw";
        reg = <0x16140000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    ccusys: clock-controller@17200000 {
        compatible = "mediatek,mt8195-ccusys";
        reg = <0x17200000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    vdecsys_soc: clock-controller@1800f000 {
        compatible = "mediatek,mt8195-vdecsys_soc";
        reg = <0x1800f000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    vdecsys: clock-controller@1802f000 {
        compatible = "mediatek,mt8195-vdecsys";
        reg = <0x1802f000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    vdecsys_core1: clock-controller@1803f000 {
        compatible = "mediatek,mt8195-vdecsys_core1";
        reg = <0x1803f000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    vencsys: clock-controller@1a000000 {
        compatible = "mediatek,mt8195-vencsys";
        reg = <0x1a000000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    vencsys_core1: clock-controller@1b000000 {
        compatible = "mediatek,mt8195-vencsys_core1";
        reg = <0x1b000000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    apusys_pll: clock-controller@190f3000 {
        compatible = "mediatek,mt8195-apusys_pll";
        reg = <0x190f3000 0x1000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek System Clock Controller for MT8195

maintainers:
  - Chun-Jie Chen <chun-jie.chen@mediatek.com>

description:
  The clock architecture in Mediatek like below
  PLLs -->
          dividers -->
                      muxes
                           -->
                              clock gate

  The apmixedsys provides most of PLLs which generated from SoC 26m.
  The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
  The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8195-topckgen
          - mediatek,mt8195-infracfg_ao
          - mediatek,mt8195-apmixedsys
          - mediatek,mt8195-pericfg_ao
      - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    topckgen: syscon@10000000 {
        compatible = "mediatek,mt8195-topckgen", "syscon";
        reg = <0x10000000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    infracfg_ao: syscon@10001000 {
        compatible = "mediatek,mt8195-infracfg_ao", "syscon";
        reg = <0x10001000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    apmixedsys: syscon@1000c000 {
        compatible = "mediatek,mt8195-apmixedsys", "syscon";
        reg = <0x1000c000 0x1000>;
        #clock-cells = <1>;
    };

  - |
    pericfg_ao: syscon@11003000 {
        compatible = "mediatek,mt8195-pericfg_ao", "syscon";
        reg = <0x11003000 0x1000>;
        #clock-cells = <1>;
    };


code:
MediaTek PCIESYS controller
============================

The MediaTek PCIESYS controller provides various clocks to the system.

Required Properties:

- compatible: Should be:
	- "mediatek,mt7622-pciesys", "syscon"
	- "mediatek,mt7629-pciesys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1

The PCIESYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

pciesys: pciesys@1a100800 {
	compatible = "mediatek,mt7622-pciesys", "syscon";
	reg = <0 0x1a100800 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek Peripheral Configuration Controller

maintainers:
  - Bartosz Golaszewski <bgolaszewski@baylibre.com>

description:
  The Mediatek pericfg controller provides various clocks and reset outputs
  to the system.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt2701-pericfg
              - mediatek,mt2712-pericfg
              - mediatek,mt6765-pericfg
              - mediatek,mt6795-pericfg
              - mediatek,mt7622-pericfg
              - mediatek,mt7629-pericfg
              - mediatek,mt8135-pericfg
              - mediatek,mt8173-pericfg
              - mediatek,mt8183-pericfg
              - mediatek,mt8186-pericfg
              - mediatek,mt8195-pericfg
              - mediatek,mt8516-pericfg
          - const: syscon
      - items:
          # Special case for mt7623 for backward compatibility
          - const: mediatek,mt7623-pericfg
          - const: mediatek,mt2701-pericfg
          - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pericfg@10003000 {
        compatible = "mediatek,mt8173-pericfg", "syscon";
        reg = <0x10003000 0x1000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
    };

  - |
    pericfg@10003000 {
        compatible =  "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon";
        reg = <0x10003000 0x1000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
    };


code:
MediaTek SGMIISYS controller
============================

The MediaTek SGMIISYS controller provides various clocks to the system.

Required Properties:

- compatible: Should be:
	- "mediatek,mt7622-sgmiisys", "syscon"
	- "mediatek,mt7629-sgmiisys", "syscon"
	- "mediatek,mt7986-sgmiisys_0", "syscon"
	- "mediatek,mt7986-sgmiisys_1", "syscon"
- #clock-cells: Must be 1

The SGMIISYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

sgmiisys: sgmiisys@1b128000 {
	compatible = "mediatek,mt7622-sgmiisys", "syscon";
	reg = <0 0x1b128000 0 0x1000>;
	#clock-cells = <1>;
};


code:
MediaTek SSUSBSYS controller
============================

The MediaTek SSUSBSYS controller provides various clocks to the system.

Required Properties:

- compatible: Should be:
	- "mediatek,mt7622-ssusbsys", "syscon"
	- "mediatek,mt7629-ssusbsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1

The SSUSBSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

ssusbsys: ssusbsys@1a000000 {
	compatible = "mediatek,mt7622-ssusbsys", "syscon";
	reg = <0 0x1a000000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
};


code:
Mediatek vcodecsys controller
============================

The Mediatek vcodecsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:
	- "mediatek,mt6765-vcodecsys", "syscon"
- #clock-cells: Must be 1

The vcodecsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

The vcodecsys controller also uses the common power domain from
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
The available power doamins are defined in dt-bindings/power/mt*-power.h.

Example:

venc_gcon: clock-controller@17000000 {
	compatible = "mediatek,mt6765-vcodecsys", "syscon";
	reg = <0 0x17000000 0 0x10000>;
	power-domains = <&scpsys MT6765_POWER_DOMAIN_VCODEC>;
	#clock-cells = <1>;
};


code:
Mediatek vdecsys controller
============================

The Mediatek vdecsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:
	- "mediatek,mt2701-vdecsys", "syscon"
	- "mediatek,mt2712-vdecsys", "syscon"
	- "mediatek,mt6779-vdecsys", "syscon"
	- "mediatek,mt6797-vdecsys", "syscon"
	- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
	- "mediatek,mt8167-vdecsys", "syscon"
	- "mediatek,mt8173-vdecsys", "syscon"
	- "mediatek,mt8183-vdecsys", "syscon"
- #clock-cells: Must be 1

The vdecsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

vdecsys: clock-controller@16000000 {
	compatible = "mediatek,mt8173-vdecsys", "syscon";
	reg = <0 0x16000000 0 0x1000>;
	#clock-cells = <1>;
};


code:
Mediatek vencltsys controller
============================

The Mediatek vencltsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be:
	- "mediatek,mt8173-vencltsys", "syscon"
- #clock-cells: Must be 1

The vencltsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

vencltsys: clock-controller@19000000 {
	compatible = "mediatek,mt8173-vencltsys", "syscon";
	reg = <0 0x19000000 0 0x1000>;
	#clock-cells = <1>;
};


code:
Mediatek vencsys controller
============================

The Mediatek vencsys controller provides various clocks to the system.

Required Properties:

- compatible: Should be one of:
	- "mediatek,mt2712-vencsys", "syscon"
	- "mediatek,mt6779-vencsys", "syscon"
	- "mediatek,mt6797-vencsys", "syscon"
	- "mediatek,mt8173-vencsys", "syscon"
	- "mediatek,mt8183-vencsys", "syscon"
- #clock-cells: Must be 1

The vencsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

vencsys: clock-controller@18000000 {
	compatible = "mediatek,mt8173-vencsys", "syscon";
	reg = <0 0x18000000 0 0x1000>;
	#clock-cells = <1>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip Sparx5 Boards

maintainers:
  - Lars Povlsen <lars.povlsen@microchip.com>

description: |+
   The Microchip Sparx5 SoC is a ARMv8-based used in a family of
   gigabit TSN-capable gigabit switches.

   The SparX-5 Ethernet switch family provides a rich set of switching
   features such as advanced TCAM-based VLAN and QoS processing
   enabling delivery of differentiated services, and security through
   TCAM-based frame processing using versatile content aware processor
   (VCAP)

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: The Sparx5 pcb125 board is a modular board,
          which has both spi-nor and eMMC storage. The modular design
          allows for connection of different network ports.
        items:
          - const: microchip,sparx5-pcb125
          - const: microchip,sparx5

      - description: The Sparx5 pcb134 is a pizzabox form factor
          gigabit switch with 20 SFP ports. It features spi-nor and
          either spi-nand or eMMC storage (mount option).
        items:
          - const: microchip,sparx5-pcb134
          - const: microchip,sparx5

      - description: The Sparx5 pcb135 is a pizzabox form factor
          gigabit switch with 48+4 Cu ports. It features spi-nor and
          either spi-nand or eMMC storage (mount option).
        items:
          - const: microchip,sparx5-pcb135
          - const: microchip,sparx5

  axi@600000000:
    type: object
    description: the root node in the Sparx5 platforms must contain
      an axi bus child node. They are always at physical address
      0x600000000 in all the Sparx5 variants.
    properties:
      compatible:
        items:
          - const: simple-bus

    required:
      - compatible

required:
  - compatible
  - axi@600000000

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/moxart.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MOXA ART

maintainers:
  - Jonas Jensen <jonas.jensen@gmail.com>

properties:
  compatible:
    description: UC-7112-LX embedded computer
    items:
      - const: moxa,moxart-uc-7112-lx
      - const: moxa,moxart

additionalProperties: true
...


code:
* Marvell Feroceon Cache

Required properties:
- compatible : Should be either "marvell,feroceon-cache" or
  	       "marvell,kirkwood-cache".

Optional properties:
- reg        : Address of the L2 cache control register. Mandatory for
  	       "marvell,kirkwood-cache", not used by "marvell,feroceon-cache"

Example:
		l2: l2-cache@20128 {
			compatible = "marvell,kirkwood-cache";
			reg = <0x20128 0x4>;
		};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mrvl/mrvl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell Platforms Device Tree Bindings

maintainers:
  - Lubomir Rintel <lkundrak@v3.sk>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: PXA168 Aspenite Board
        items:
          - enum:
              - mrvl,pxa168-aspenite
          - const: mrvl,pxa168
      - description: PXA910 DKB Board
        items:
          - enum:
              - mrvl,pxa910-dkb
          - const: mrvl,pxa910
      - description: MMP2 based boards
        items:
          - enum:
              - mrvl,mmp2-brownstone
              - olpc,xo-1.75
          - const: mrvl,mmp2
      - description: MMP3 based boards
        items:
          - enum:
              - dell,wyse-ariel
          - const: marvell,mmp3

additionalProperties: true

...


code:
* Marvell Tauros2 Cache

Required properties:
- compatible : Should be "marvell,tauros2-cache".
- marvell,tauros2-cache-features : Specify the features supported for the
  tauros2 cache.
  The features including
    CACHE_TAUROS2_PREFETCH_ON       (1 << 0)
    CACHE_TAUROS2_LINEFILL_BURST8   (1 << 1)
  The definition can be found at
  arch/arm/include/asm/hardware/cache-tauros2.h

Example:
	L2: l2-cache {
		compatible = "marvell,tauros2-cache";
		marvell,tauros2-cache-features = <0x3>;
	};


code:
QCOM Idle States for cpuidle driver

ARM provides idle-state node to define the cpuidle states, as defined in [1].
cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
states. Idle states have different enter/exit latency and residency values.
The idle states supported by the QCOM SoC are defined as -

    * Standby
    * Retention
    * Standalone Power Collapse (Standalone PC or SPC)
    * Power Collapse (PC)

Standby: Standby does a little more in addition to architectural clock gating.
When the WFI instruction is executed the ARM core would gate its internal
clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
trigger to execute the SPM state machine. The SPM state machine waits for the
interrupt to trigger the core back in to active. This triggers the cache
hierarchy to enter standby states, when all cpus are idle. An interrupt brings
the SPM state machine out of its wait, the next step is to ensure that the
cache hierarchy is also out of standby, and then the cpu is allowed to resume
execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
driver and is not defined in the DT. The SPM state machine should be
configured to execute this state by default and after executing every other
state below.

Retention: Retention is a low power state where the core is clock gated and
the memory and the registers associated with the core are retained. The
voltage may be reduced to the minimum value needed to keep the processor
registers active. The SPM should be configured to execute the retention
sequence and would wait for interrupt, before restoring the cpu to execution
state. Retention may have a slightly higher latency than Standby.

Standalone PC: A cpu can power down and warmboot if there is a sufficient time
between the time it enters idle and the next known wake up. SPC mode is used
to indicate a core entering a power down state without consulting any other
cpu or the system resources. This helps save power only on that core.  The SPM
sequence for this idle state is programmed to power down the supply to the
core, wait for the interrupt, restore power to the core, and ensure the
system state including cache hierarchy is ready before allowing core to
resume. Applying power and resetting the core causes the core to warmboot
back into Elevation Level (EL) which trampolines the control back to the
kernel. Entering a power down state for the cpu, needs to be done by trapping
into a EL. Failing to do so, would result in a crash enforced by the warm boot
code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
be flushed in s/w, before powering down the core.

Power Collapse: This state is similar to the SPC mode, but distinguishes
itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
modes. In a hierarchical power domain SoC, this means L2 and other caches can
be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
voltages reduced, provided all cpus enter this state.  Since the span of low
power modes possible at this state is vast, the exit latency and the residency
of this low power mode would be considered high even though at a cpu level,
this essentially is cpu power down. The SPM in this state also may handshake
with the Resource power manager (RPM) processor in the SoC to indicate a
complete application processor subsystem shut down.

The idle-state for QCOM SoCs are distinguished by the compatible property of
the idle-states device node.

The devicetree representation of the idle state should be -

Required properties:

- compatible: Must be one of -
			"qcom,idle-state-ret",
			"qcom,idle-state-spc",
			"qcom,idle-state-pc",
		and "arm,idle-state".

Other required and optional properties are specified in [1].

Example:

	idle-states {
		CPU_SPC: spc {
			compatible = "qcom,idle-state-spc", "arm,idle-state";
			entry-latency-us = <150>;
			exit-latency-us = <200>;
			min-residency-us = <2000>;
		};
	};

[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml


code:
Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)

The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
There is one ACC register region per CPU within the KPSS remapped region as
well as an alias register region that remaps accesses to the ACC associated
with the CPU accessing the region.

PROPERTIES

- compatible:
	Usage: required
	Value type: <string>
	Definition: should be one of:
			"qcom,kpss-acc-v1"
			"qcom,kpss-acc-v2"

- reg:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: the first element specifies the base address and size of
		    the register region. An optional second element specifies
		    the base address and size of the alias register region.

- clocks:
        Usage: required
        Value type: <prop-encoded-array>
        Definition: reference to the pll parents.

- clock-names:
        Usage: required
        Value type: <stringlist>
        Definition: must be "pll8_vote", "pxo".

- clock-output-names:
	Usage: optional
	Value type: <string>
	Definition: Name of the output clock. Typically acpuX_aux where X is a
		    CPU number starting at 0.

Example:

	clock-controller@2088000 {
		compatible = "qcom,kpss-acc-v2";
		reg = <0x02088000 0x1000>,
		      <0x02008000 0x1000>;
		clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
		clock-names = "pll8_vote", "pxo";
		clock-output-names = "acpu0_aux";
	};


code:
Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)

PROPERTIES

- compatible:
	Usage: required
	Value type: <string>
	Definition: should be one of the following. The generic compatible
			"qcom,kpss-gcc" should also be included.
			"qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
			"qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
			"qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
			"qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"

- reg:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: base address and size of the register region

- clocks:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: reference to the pll parents.

- clock-names:
	Usage: required
	Value type: <stringlist>
	Definition: must be "pll8_vote", "pxo".

- clock-output-names:
	Usage: required
	Value type: <string>
	Definition: Name of the output clock. Typically acpu_l2_aux indicating
		    an L2 cache auxiliary clock.

Example:

	l2cc: clock-controller@2011000 {
		compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
		reg = <0x2011000 0x1000>;
		clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
		clock-names = "pll8_vote", "pxo";
		clock-output-names = "acpu_l2_aux";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Last Level Cache Controller

maintainers:
  - Rishabh Bhatnagar <rishabhb@codeaurora.org>
  - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>

description: |
  LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
  that can be shared by multiple clients. Clients here are different cores in the
  SoC, the idea is to minimize the local caches at the clients and migrate to
  common pool of memory. Cache memory is divided into partitions called slices
  which are assigned to clients. Clients can query the slice details, activate
  and deactivate them.

properties:
  compatible:
    enum:
      - qcom,sc7180-llcc
      - qcom,sc7280-llcc
      - qcom,sc8180x-llcc
      - qcom,sc8280xp-llcc
      - qcom,sdm845-llcc
      - qcom,sm6350-llcc
      - qcom,sm8150-llcc
      - qcom,sm8250-llcc
      - qcom,sm8350-llcc
      - qcom,sm8450-llcc
      - qcom,sm8550-llcc

  reg:
    items:
      - description: LLCC base register region
      - description: LLCC broadcast base register region

  reg-names:
    items:
      - const: llcc_base
      - const: llcc_broadcast_base

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    system-cache-controller@1100000 {
      compatible = "qcom,sdm845-llcc";
      reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
      reg-names = "llcc_base", "llcc_broadcast_base";
      interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
    };


code:
SPM AVS Wrapper 2 (SAW2)

The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
power-controller that transitions a piece of hardware (like a processor or
subsystem) into and out of low power modes via a direct connection to
the PMIC. It can also be wired up to interact with other processors in the
system, notifying them when a low power state is entered or exited.

Multiple revisions of the SAW hardware are supported using these Device Nodes.
SAW2 revisions differ in the register offset and configuration data. Also, the
same revision of the SAW in different SoCs may have different configuration
data due the differences in hardware capabilities. Hence the SoC name, the
version of the SAW hardware in that SoC and the distinction between cpu (big
or Little) or cache, may be needed to uniquely identify the SAW register
configuration and initialization data. The compatible string is used to
indicate this parameter.

PROPERTIES

- compatible:
	Usage: required
	Value type: <string>
	Definition: Must have
			"qcom,saw2"
		    A more specific value could be one of:
			"qcom,apq8064-saw2-v1.1-cpu"
			"qcom,msm8226-saw2-v2.1-cpu"
			"qcom,msm8974-saw2-v2.1-cpu"
			"qcom,apq8084-saw2-v2.1-cpu"

- reg:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: the first element specifies the base address and size of
		    the register region. An optional second element specifies
		    the base address and size of the alias register region.

- regulator:
	Usage: optional
	Value type: boolean
	Definition: Indicates that this SPM device acts as a regulator device
			device for the core (CPU or Cache) the SPM is attached
			to.

Example 1:

	power-controller@2099000 {
		compatible = "qcom,saw2";
		reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
		regulator;
	};

Example 2:
	saw0: power-controller@f9089000 {
		compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
		reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
	};


code:
* Qualcomm SSBI

Some Qualcomm MSM devices contain a point-to-point serial bus used to
communicate with a limited range of devices (mostly power management
chips).

These require the following properties:

- compatible: "qcom,ssbi"

- qcom,controller-type
  indicates the SSBI bus variant the controller should use to talk
  with the slave device.  This should be one of "ssbi", "ssbi2", or
  "pmic-arbiter".  The type chosen is determined by the attached
  slave.

The slave device should be the single child node of the ssbi device
with a compatible field.


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 thingy.jp.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MStar/SigmaStar Armv7 SoC l3bridge

maintainers:
  - Daniel Palmer <daniel@thingy.jp>

description: |
  MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface
  between the CPU and memory. This means that before DMA capable
  devices are allowed to run the pipeline must be flushed to ensure
  everything is in memory.

  The l3bridge region contains registers that allow such a flush
  to be triggered.

  This node is used by the platform code to find where the registers
  are and install a barrier that triggers the required pipeline flush.

properties:
  compatible:
    items:
      - const: mstar,l3bridge

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    l3bridge: l3bridge@1f204400 {
        compatible = "mstar,l3bridge";
        reg = <0x1f204400 0x200>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 thingy.jp.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MStar/SigmaStar Armv7 SoC SMP control registers

maintainers:
  - Daniel Palmer <daniel@thingy.jp>

description: |
  MStar/SigmaStar's Armv7 SoCs that have more than one processor
  have a region of registers that allow setting the boot address
  and a magic number that allows secondary processors to leave
  the loop they are parked in by the boot ROM.

properties:
  compatible:
    items:
      - enum:
          - sstar,ssd201-smpctrl # SSD201/SSD202D
      - const: mstar,smpctrl

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    smpctrl@204000 {
        compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl";
        reg = <0x204000 0x200>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mstar/mstar.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MStar platforms device tree bindings

maintainers:
  - Daniel Palmer <daniel@thingy.jp>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: infinity boards
        items:
          - enum:
              - thingyjp,breadbee-crust # thingy.jp BreadBee Crust
          - const: mstar,infinity

      - description: infinity2m boards
        items:
          - enum:
              - 100ask,dongshanpione # 100ask DongShanPiOne
              - honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit
              - m5stack,unitv2 # M5Stack UnitV2
              - miyoo,miyoo-mini # Miyoo Mini
              - wirelesstag,ido-som2d01 # Wireless Tag IDO-SOM2D01
              - wirelesstag,ido-sbc2d06-v1b-22w # Wireless Tag IDO-SBC2D06-1VB-22W
          - const: mstar,infinity2m

      - description: infinity3 boards
        items:
          - enum:
              - thingyjp,breadbee # thingy.jp BreadBee
          - const: mstar,infinity3

      - description: mercury5 boards
        items:
          - enum:
              - 70mai,midrived08 # 70mai midrive d08
          - const: mstar,mercury5

additionalProperties: true


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/npcm/npcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NPCM Platforms Device Tree Bindings

maintainers:
  - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
  - Tomer Maimon <tmaimon77@gmail.com>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: WPCM450 based boards
        items:
          - enum:
              - supermicro,x9sci-ln4f-bmc   # Supermicro X9SCI-LN4F server's BMC
          - const: nuvoton,wpcm450

      - description: NPCM750 based boards
        items:
          - enum:
              - nuvoton,npcm750-evb         # NPCM750 evaluation board
          - const: nuvoton,npcm750

      - description: NPCM845 based boards
        items:
          - enum:
              - nuvoton,npcm845-evb         # NPCM845 evaluation board
          - const: nuvoton,npcm845

additionalProperties: true


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Global Control Registers block in Nuvoton SoCs

maintainers:
  - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
  - Tomer Maimon <tmaimon77@gmail.com>

description:
  The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs
  that expose misc functionality such as chip model and version information or
  pinmux settings.

properties:
  compatible:
    items:
      - enum:
          - nuvoton,wpcm450-gcr
          - nuvoton,npcm750-gcr
          - nuvoton,npcm845-gcr
      - const: syscon
      - const: simple-mfd

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties:
  type: object

examples:
  - |
    gcr: syscon@800000 {
      compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
      reg = <0x800000 0x1000>;

      mux-controller {
        compatible = "mmio-mux";
        #mux-control-cells = <1>;
        mux-reg-masks = <0x38 0x07>;
        idle-states = <2>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: NVIDIA Tegra194 CPU Complex

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jonathan Hunter <jonathanh@nvidia.com>
  - Sumit Gupta <sumitg@nvidia.com>

description: |+
  Tegra194 SOC has homogeneous architecture where each cluster has two
  symmetric cores. Compatible string in "cpus" node represents the CPU
  Complex having all clusters.

properties:
  $nodename:
    const: cpus

  compatible:
    enum:
      - nvidia,tegra194-ccplex

  nvidia,bpmp:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: |
      Specifies the bpmp node that needs to be queried to get
      operating point data for all CPUs.

additionalProperties: true

examples:
  - |
    cpus {
      compatible = "nvidia,tegra194-ccplex";
      nvidia,bpmp = <&bpmp>;
      #address-cells = <1>;
      #size-cells = <0>;

      cpu0_0: cpu@0 {
        compatible = "nvidia,tegra194-carmel";
        device_type = "cpu";
        reg = <0x0>;
        enable-method = "psci";
      };

      cpu0_1: cpu@1 {
        compatible = "nvidia,tegra194-carmel";
        device_type = "cpu";
        reg = <0x001>;
        enable-method = "psci";
      };

      cpu1_0: cpu@100 {
        compatible = "nvidia,tegra194-carmel";
        device_type = "cpu";
        reg = <0x100>;
        enable-method = "psci";
      };

      cpu1_1: cpu@101 {
        compatible = "nvidia,tegra194-carmel";
        device_type = "cpu";
        reg = <0x101>;
        enable-method = "psci";
      };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/nxp/lpc32xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP LPC32xx Platforms Device Tree Bindings

maintainers:
  - Roland Stigge <stigge@antcom.de>

properties:
  compatible:
    oneOf:
      - enum:
          - nxp,lpc3220
          - nxp,lpc3230
          - nxp,lpc3240
      - items:
          - enum:
              - ea,ea3250
              - phytec,phy3250
          - const: nxp,lpc3250

additionalProperties: true
...


code:
OMAP Counter-32K bindings

Required properties:
- compatible:	Must be "ti,omap-counter32k" for OMAP controllers
- reg:		Contains timer register address range (base address and length)
- ti,hwmods:	Name of the hwmod associated to the counter, which is typically
		"counter_32k"

Example:

counter32k: counter@4a304000 {
	compatible = "ti,omap-counter32k";
	reg = <0x4a304000 0x20>;
	ti,hwmods = "counter_32k";
};


code:
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are preceded by an CROSSBAR
that provides flexibility in muxing the device requests to the controller
inputs.

Required properties:
- compatible : Should be "ti,irq-crossbar"
- reg: Base address and the size of the crossbar registers.
- interrupt-controller: indicates that this block is an interrupt controller.
- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
	    register is assumed to be of same size. Valid sizes are 1, 2, 4.
- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
		 crossbar. These interrupt lines are reserved in the soc,
		 so crossbar bar driver should not consider them as free
		 lines.

Optional properties:
- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
  SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
  crossbar. These irqs have a crossbar register, but still cannot be used.

- ti,irqs-safe-map: integer which maps to a safe configuration to use
  when the interrupt controller irq is unused (when not provided, default is 0)

Examples:
		crossbar_mpu: crossbar@4a002a48 {
			compatible = "ti,irq-crossbar";
			reg = <0x4a002a48 0x130>;
			ti,max-irqs = <160>;
			ti,max-crossbar-sources = <400>;
			ti,reg-size = <2>;
			ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
			ti,irqs-skip = <10 133 139 140>;
		};

Consumer:
========
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for
further details.

An interrupt consumer on an SoC using crossbar will use:
	interrupts = <GIC_SPI request_number interrupt_level>

Example:
	device_x@4a023000 {
		/* Crossbar 8 used */
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		...
	};


code:
OMAP Control Module bindings

Control Module contains miscellaneous features under it based on SoC type.
Pincontrol is one common feature, and it has a specialized support
described in [1]. Typically some clock nodes are also under control module.
Syscon is used to share register level access to drivers external to
control module driver itself.

See [2] for documentation about clock/clockdomain nodes.

[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
[2] Documentation/devicetree/bindings/clock/ti/*

Required properties:
- compatible:	Must be one of:
		"ti,am3-scm"
		"ti,am4-scm"
		"ti,dm814-scrm"
		"ti,dm816-scrm"
		"ti,omap2-scm"
		"ti,omap3-scm"
		"ti,omap4-scm-core"
		"ti,omap4-scm-padconf-core"
		"ti,omap4-scm-wkup"
		"ti,omap4-scm-padconf-wkup"
		"ti,omap5-scm-core"
		"ti,omap5-scm-padconf-core"
		"ti,omap5-scm-wkup-pad-conf"
		"ti,dra7-scm-core"
- reg:		Contains Control Module register address range
		(base address and length)

Optional properties:
- clocks:	clocks for this module
- clockdomains:	clockdomains for this module

Examples:

scm: scm@2000 {
	compatible = "ti,omap3-scm", "simple-bus";
	reg = <0x2000 0x2000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0x2000 0x2000>;

	omap3_pmx_core: pinmux@30 {
		compatible = "ti,omap3-padconf",
			     "pinctrl-single";
		reg = <0x30 0x230>;
		#address-cells = <1>;
		#size-cells = <0>;
		#interrupt-cells = <1>;
		interrupt-controller;
		pinctrl-single,register-width = <16>;
		pinctrl-single,function-mask = <0xff1f>;
	};

	scm_conf: scm_conf@270 {
		compatible = "syscon";
		reg = <0x270 0x330>;
		#address-cells = <1>;
		#size-cells = <1>;

		scm_clocks: clocks {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	scm_clockdomains: clockdomains {
	};
}

&scm_clocks {
	mcbsp5_mux_fck: mcbsp5_mux_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&core_96m_fck>, <&mcbsp_clks>;
		ti,bit-shift = <4>;
		reg = <0x02d8>;
	};
};


code:
OMAP Dynamic Memory Manager (DMM) bindings

The dynamic memory manager (DMM) is a module located immediately in front of the
SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
accesses such as priority generation amongst initiators, configuration of SDRAM
interleaving, optimizing transfer of 2D block objects, and provide MMU-like page
translation for initiators which need contiguous dma bus addresses.

Required properties:
- compatible:	Should contain "ti,omap4-dmm" for OMAP4 family
		Should contain "ti,omap5-dmm" for OMAP5 and DRA7x family
- reg:		Contains DMM register address range (base address and length)
- interrupts:	Should contain an interrupt-specifier for DMM_IRQ.
- ti,hwmods:	Name of the hwmod associated to DMM, which is typically "dmm"

Example:

dmm@4e000000 {
	compatible = "ti,omap4-dmm";
	reg = <0x4e000000 0x800>;
	ti,hwmods = "dmm";
};


code:
* TI - DSP (Digital Signal Processor)

TI DSP included in OMAP SoC

Required properties:
- compatible : Should be "ti,omap3-c64" for OMAP3 & 4
- ti,hwmods: "dsp"

Examples:

dsp {
    compatible = "ti,omap3-c64";
    ti,hwmods = "dsp";
};


code:
* TI - IVA (Imaging and Video Accelerator) subsystem

The IVA contain various audio, video or imaging HW accelerator
depending of the version.

Required properties:
- compatible : Should be:
  - "ti,ivahd" for OMAP4
  - "ti,iva2.2" for OMAP3
  - "ti,iva2.1" for OMAP2430
  - "ti,iva1" for OMAP2420
- ti,hwmods: "iva"

Examples:

iva {
    compatible = "ti,ivahd", "ti,iva";
    ti,hwmods = "iva";
};