code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for Keystone 2 clock tree
 *
 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
 */

clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	mainmuxclk: mainmuxclk@2310108 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-mux-clock";
		clocks = <&mainpllclk>, <&refclksys>;
		reg = <0x02310108 4>;
		bit-shift = <23>;
		bit-mask = <1>;
		clock-output-names = "mainmuxclk";
	};

	chipclk1: chipclk1 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&mainmuxclk>;
		clock-div = <1>;
		clock-mult = <1>;
		clock-output-names = "chipclk1";
	};

	chipclk1rstiso: chipclk1rstiso {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&mainmuxclk>;
		clock-div = <1>;
		clock-mult = <1>;
		clock-output-names = "chipclk1rstiso";
	};

	gemtraceclk: gemtraceclk@2310120 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-divider-clock";
		clocks = <&mainmuxclk>;
		reg = <0x02310120 4>;
		bit-shift = <0>;
		bit-mask = <8>;
		clock-output-names = "gemtraceclk";
	};

	chipstmxptclk: chipstmxptclk@2310164 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-divider-clock";
		clocks = <&mainmuxclk>;
		reg = <0x02310164 4>;
		bit-shift = <0>;
		bit-mask = <8>;
		clock-output-names = "chipstmxptclk";
	};

	chipclk12: chipclk12 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&chipclk1>;
		clock-div = <2>;
		clock-mult = <1>;
		clock-output-names = "chipclk12";
	};

	chipclk13: chipclk13 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&chipclk1>;
		clock-div = <3>;
		clock-mult = <1>;
		clock-output-names = "chipclk13";
	};

	paclk13: paclk13 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&papllclk>;
		clock-div = <3>;
		clock-mult = <1>;
		clock-output-names = "paclk13";
	};

	chipclk14: chipclk14 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&chipclk1>;
		clock-div = <4>;
		clock-mult = <1>;
		clock-output-names = "chipclk14";
	};

	chipclk16: chipclk16 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&chipclk1>;
		clock-div = <6>;
		clock-mult = <1>;
		clock-output-names = "chipclk16";
	};

	chipclk112: chipclk112 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&chipclk1>;
		clock-div = <12>;
		clock-mult = <1>;
		clock-output-names = "chipclk112";
	};

	chipclk124: chipclk124 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&chipclk1>;
		clock-div = <24>;
		clock-mult = <1>;
		clock-output-names = "chipclk114";
	};

	chipclk1rstiso13: chipclk1rstiso13 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&chipclk1rstiso>;
		clock-div = <3>;
		clock-mult = <1>;
		clock-output-names = "chipclk1rstiso13";
	};

	chipclk1rstiso14: chipclk1rstiso14 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&chipclk1rstiso>;
		clock-div = <4>;
		clock-mult = <1>;
		clock-output-names = "chipclk1rstiso14";
	};

	chipclk1rstiso16: chipclk1rstiso16 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&chipclk1rstiso>;
		clock-div = <6>;
		clock-mult = <1>;
		clock-output-names = "chipclk1rstiso16";
	};

	chipclk1rstiso112: chipclk1rstiso112 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&chipclk1rstiso>;
		clock-div = <12>;
		clock-mult = <1>;
		clock-output-names = "chipclk1rstiso112";
	};

	clkmodrst0: clkmodrst0@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk16>;
		clock-output-names = "modrst0";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkusb: clkusb@2350008 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk16>;
		clock-output-names = "usb";
		reg = <0x02350008 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkaemifspi: clkaemifspi@235000c {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk16>;
		clock-output-names = "aemif-spi";
		reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkdebugsstrc: clkdebugsstrc@2350014 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "debugss-trc";
		reg = <0x02350014 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <1>;
	};

	clktetbtrc: clktetbtrc@2350018 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "tetb-trc";
		reg = <0x02350018 0xb00>, <0x02350004 0x400>;
		reg-names = "control", "domain";
		domain-id = <1>;
	};

	clkpa: clkpa@235001c {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&paclk13>;
		clock-output-names = "pa";
		reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
		reg-names = "control", "domain";
		domain-id = <2>;
	};

	clkcpgmac: clkcpgmac@2350020 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkpa>;
		clock-output-names = "cpgmac";
		reg = <0x02350020 0xb00>, <0x02350008 0x400>;
		reg-names = "control", "domain";
		domain-id = <2>;
	};

	clksa: clksa@2350024 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkpa>;
		clock-output-names = "sa";
		reg = <0x02350024 0xb00>, <0x02350008 0x400>;
		reg-names = "control", "domain";
		domain-id = <2>;
	};

	clkpcie: clkpcie@2350028 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk12>;
		clock-output-names = "pcie";
		reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
		reg-names = "control", "domain";
		domain-id = <3>;
	};

	clksr: clksr@2350034 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1rstiso112>;
		clock-output-names = "sr";
		reg = <0x02350034 0xb00>, <0x02350018 0x400>;
		reg-names = "control", "domain";
		domain-id = <6>;
	};

	clkgem0: clkgem0@235003c {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1>;
		clock-output-names = "gem0";
		reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
		reg-names = "control", "domain";
		domain-id = <8>;
	};

	clkddr30: clkddr30@235005c {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk12>;
		clock-output-names = "ddr3-0";
		reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
		reg-names = "control", "domain";
		domain-id = <16>;
	};

	clkwdtimer0: clkwdtimer0@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "timer0";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkwdtimer1: clkwdtimer1@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "timer1";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkwdtimer2: clkwdtimer2@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "timer2";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkwdtimer3: clkwdtimer3@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "timer3";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clktimer15: clktimer15@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "timer15";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkuart0: clkuart0@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "uart0";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkuart1: clkuart1@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "uart1";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkaemif: clkaemif@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkaemifspi>;
		clock-output-names = "aemif";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkusim: clkusim@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "usim";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clki2c: clki2c@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "i2c";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkspi: clkspi@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkaemifspi>;
		clock-output-names = "spi";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkgpio: clkgpio@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "gpio";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkkeymgr: clkkeymgr@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&clkmodrst0>;
		clock-output-names = "keymgr";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	/*
	 * Below are set of fixed, input clocks definitions,
	 * for which real frequencies have to be defined in board files.
	 * Those clocks can be used as reference clocks for some HW modules
	 * (as cpts, for example) by configuring corresponding clock muxes.
	 */
	timi0: timi0 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
		clock-output-names = "timi0";
	};

	timi1: timi1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
		clock-output-names = "timi1";
	};

	tsrefclk: tsrefclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
		clock-output-names = "tsrefclk";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Keystone 2 Edison SoC specific device tree
 *
 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
 */

clocks {
	mainpllclk: mainpllclk@2310110 {
		#clock-cells = <0>;
		compatible = "ti,keystone,main-pll-clock";
		clocks = <&refclksys>;
		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
		reg-names = "control", "multiplier", "post-divider";
	};

	papllclk: papllclk@2620358 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-clock";
		clocks = <&refclkpass>;
		clock-output-names = "papllclk";
		reg = <0x02620358 4>;
		reg-names = "control";
	};

	ddr3apllclk: ddr3apllclk@2620360 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-clock";
		clocks = <&refclkddr3a>;
		clock-output-names = "ddr-3a-pll-clk";
		reg = <0x02620360 4>;
		reg-names = "control";
	};

	clkusb1: clkusb1@2350004 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk16>;
		clock-output-names = "usb1";
		reg = <0x02350004 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clkhyperlink0: clkhyperlink0@2350030 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk12>;
		clock-output-names = "hyperlink-0";
		reg = <0x02350030 0xb00>, <0x02350014 0x400>;
		reg-names = "control", "domain";
		domain-id = <5>;
	};

	clkpcie1: clkpcie1@235006c {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk12>;
		clock-output-names = "pcie1";
		reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
		reg-names = "control", "domain";
		domain-id = <18>;
	};

	clkxge: clkxge@23500c8 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "xge";
		reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
		reg-names = "control", "domain";
		domain-id = <29>;
	};

	/*
	 * Below are set of fixed, input clocks definitions,
	 * for which real frequencies have to be defined in board files.
	 * Those clocks can be used as reference clocks for some HW modules
	 * (as cpts, for example) by configuring corresponding clock muxes.
	 */
	tsipclka: tsipclka {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
		clock-output-names = "tsipclka";
	};

	tsipclkb: tsipclkb {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
		clock-output-names = "tsipclkb";
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Keystone 2 Edison EVM device tree
 *
 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
 */
/dts-v1/;

#include "keystone.dtsi"
#include "keystone-k2e.dtsi"

/ {
	compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
	model = "Texas Instruments Keystone 2 Edison EVM";

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp_common_memory: dsp-common-memory@81f800000 {
			compatible = "shared-dma-pool";
			reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
			reusable;
			status = "okay";
		};
	};
};

&soc0 {

		clocks {
			refclksys: refclksys {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <100000000>;
				clock-output-names = "refclk-sys";
			};

			refclkpass: refclkpass {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <100000000>;
				clock-output-names = "refclk-pass";
			};

			refclkddr3a: refclkddr3a {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <100000000>;
				clock-output-names = "refclk-ddr3a";
			};
		};
};

&usb_phy {
	status = "okay";
};

&keystone_usb0 {
	status = "okay";
};

&usb0 {
	dr_mode = "host";
};

&usb1_phy {
	status = "okay";
};

&keystone_usb1 {
	status = "okay";
};

&usb1 {
	dr_mode = "peripheral";
};

&i2c0 {
	dtt@50 {
		compatible = "atmel,24c1024";
		reg = <0x50>;
	};
};

&aemif {
	cs0 {
		#address-cells = <2>;
		#size-cells = <1>;
		clock-ranges;
		ranges;

		ti,cs-chipselect = <0>;
		/* all timings in nanoseconds */
		ti,cs-min-turnaround-ns = <12>;
		ti,cs-read-hold-ns = <6>;
		ti,cs-read-strobe-ns = <23>;
		ti,cs-read-setup-ns = <9>;
		ti,cs-write-hold-ns = <8>;
		ti,cs-write-strobe-ns = <23>;
		ti,cs-write-setup-ns = <8>;

		nand@0,0 {
			compatible = "ti,keystone-nand","ti,davinci-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0 0 0x4000000
			       1 0 0x0000100>;

			ti,davinci-chipselect = <0>;
			ti,davinci-mask-ale = <0x2000>;
			ti,davinci-mask-cle = <0x4000>;
			ti,davinci-mask-chipsel = <0>;
			nand-ecc-mode = "hw";
			ti,davinci-ecc-bits = <4>;
			nand-on-flash-bbt;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x100000>;
				read-only;
			};

			partition@100000 {
				label = "params";
				reg = <0x100000 0x80000>;
				read-only;
			};

			partition@180000 {
				label = "ubifs";
				reg = <0x180000 0x1FE80000>;
			};
		};
	};
};

&spi0 {
	nor_flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q128a11", "jedec,spi-nor";
		spi-max-frequency = <54000000>;
		m25p,fast-read;
		reg = <0>;

		partition@0 {
			label = "u-boot-spl";
			reg = <0x0 0x80000>;
			read-only;
		};

		partition@1 {
			label = "misc";
			reg = <0x80000 0xf80000>;
		};
	};
};

&mdio {
	status = "ok";
	ethphy0: ethernet-phy@0 {
		compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
		reg = <0>;
	};

	ethphy1: ethernet-phy@1 {
		compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
		reg = <1>;
	};
};

&dsp0 {
	memory-region = <&dsp_common_memory>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for Keystone 2 Edison Netcp driver
 *
 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
 */

qmss: qmss@2a40000 {
	compatible = "ti,keystone-navigator-qmss";
	dma-coherent;
	#address-cells = <1>;
	#size-cells = <1>;
	clocks = <&chipclk13>;
	ranges;
	queue-range = <0 0x2000>;
	linkram0 = <0x100000 0x4000>;
	linkram1 = <0 0x10000>;

	qmgrs {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		qmgr0 {
			managed-queues = <0 0x2000>;
			reg = <0x2a40000 0x20000>,
			      <0x2a06000 0x400>,
			      <0x2a02000 0x1000>,
			      <0x2a03000 0x1000>,
			      <0x23a80000 0x20000>,
			      <0x2a80000 0x20000>;
			reg-names = "peek", "status", "config",
				    "region", "push", "pop";
		};
	};
	queue-pools {
		qpend {
			qpend-0 {
				qrange = <658 8>;
				interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
					     0 43 0xf04 0 44 0xf04 0 45 0xf04
					     0 46 0xf04 0 47 0xf04>;
			};
			qpend-1 {
				qrange = <528 16>;
				interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
					      0 51 0xf04 0 52 0xf04 0 53 0xf04
					      0 54 0xf04 0 55 0xf04 0 56 0xf04
					      0 57 0xf04 0 58 0xf04 0 59 0xf04
					      0 60 0xf04 0 61 0xf04 0 62 0xf04
					      0 63 0xf04>;
				qalloc-by-id;
			};
			qpend-2 {
				qrange = <544 16>;
				interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
					      0 59 0xf04 0 68 0xf04 0 69 0xf04
					      0 70 0xf04 0 71 0xf04 0 72 0xf04
					      0 73 0xf04 0 74 0xf04 0 75 0xf04
					      0 76 0xf04 0 77 0xf04 0 78 0xf04
					      0 79 0xf04>;
			};
		};
		general-purpose {
			gp-0 {
				qrange = <4000 64>;
			};
			netcp-tx {
				qrange = <896 128>;
				qalloc-by-id;
			};
		};
		accumulator {
			acc-low-0 {
				qrange = <480 32>;
				accumulator = <0 47 16 2 50>;
				interrupts = <0 226 0xf01>;
				multi-queue;
				qalloc-by-id;
			};
		};
	};

	descriptor-regions {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		region-12 {
			id = <12>;
			region-spec = <8192 128>;	/* num_desc desc_size */
			link-index = <0x4000>;
		};
	};

	pdsps {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		pdsp0@2a10000 {
			reg = <0x2a10000 0x1000    /*iram */
			       0x2a0f000 0x100     /*reg*/
			       0x2a0c000 0x3c8	   /*intd */
			       0x2a20000 0x4000>;  /*cmd*/
			id = <0>;
		};
	};
}; /* qmss */

knav_dmas: knav_dmas@0 {
	compatible = "ti,keystone-navigator-dma";
	clocks = <&papllclk>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	ti,navigator-cloud-address = <0x23a80000 0x23a90000
				 0x23a80000 0x23a90000>;

	dma_gbe: dma_gbe@0 {
		reg = <0x24186000 0x100>,
			  <0x24187000 0x2a0>,
			  <0x24188000 0xb60>,
			  <0x24186100 0x80>,
			  <0x24189000 0x1000>;
		reg-names = "global", "txchan", "rxchan",
				"txsched", "rxflow";
	};
};

netcp: netcp@24000000 {
	reg = <0x2620110 0x8>;
	reg-names = "efuse";
	compatible = "ti,netcp-1.0";
	#address-cells = <1>;
	#size-cells = <1>;

	/* NetCP address range */
	ranges = <0 0x24000000 0x1000000>;

	clocks = <&clkpa>, <&clkcpgmac>;
	clock-names = "pa_clk", "ethss_clk";
	dma-coherent;

	ti,navigator-dmas = <&dma_gbe 0>,
			<&dma_gbe 8>,
			<&dma_gbe 0>;
	ti,navigator-dma-names = "netrx0", "netrx1", "nettx";

	netcp-devices {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		gbe@200000 { /* ETHSS */
			label = "netcp-gbe";
			compatible = "ti,netcp-gbe-9";
			reg = <0x200000 0x900>, <0x220000 0x20000>;
			/* enable-ale; */
			tx-queue = <896>;
			tx-channel = "nettx";

			cpts {
				clocks = <&cpts_refclk_mux>;
				clock-names = "cpts";

				cpts_refclk_mux: cpts-refclk-mux {
					#clock-cells = <0>;
					clocks = <&chipclk12>, <&chipclk13>,
						 <&timi0>, <&timi1>,
						 <&tsipclka>, <&tsrefclk>,
						 <&tsipclkb>;
					ti,mux-tbl = <0x0>, <0x1>, <0x2>,
						<0x3>, <0x4>, <0x8>, <0xC>;
					assigned-clocks = <&cpts_refclk_mux>;
					assigned-clock-parents = <&chipclk12>;
				};
			};

			interfaces {
				gbe0: interface-0 {
					slave-port = <0>;
					link-interface = <1>;
					phy-handle = <&ethphy0>;
				};
				gbe1: interface-1 {
					slave-port = <1>;
					link-interface = <1>;
					phy-handle = <&ethphy1>;
				};
			};

			secondary-slave-ports {
				port-2 {
					slave-port = <2>;
					link-interface = <2>;
				};
				port-3 {
					slave-port = <3>;
					link-interface = <2>;
				};
				port-4 {
					slave-port = <4>;
					link-interface = <2>;
				};
				port-5 {
					slave-port = <5>;
					link-interface = <2>;
				};
				port-6 {
					slave-port = <6>;
					link-interface = <2>;
				};
				port-7 {
					slave-port = <7>;
					link-interface = <2>;
				};
			};
		};
	};

	netcp-interfaces {
		interface-0 {
			rx-channel = "netrx0";
			rx-pool = <1024 12>;
			tx-pool = <1024 12>;
			rx-queue-depth = <128 128 0 0>;
			rx-buffer-size = <1518 4096 0 0>;
			rx-queue = <528>;
			tx-completion-queue = <530>;
			efuse-mac = <1>;
			netcp-gbe = <&gbe0>;

		};
		interface-1 {
			rx-channel = "netrx1";
			rx-pool = <1024 12>;
			tx-pool = <1024 12>;
			rx-queue-depth = <128 128 0 0>;
			rx-buffer-size = <1518 4096 0 0>;
			rx-queue = <529>;
			tx-completion-queue = <531>;
			efuse-mac = <0>;
			local-mac-address = [02 18 31 7e 3e 00];
			netcp-gbe = <&gbe1>;
		};
	};
};

sa_subsys: subsys@24080000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";
	ranges = <0 0x24080000 0x40000>;

	sa_config: subsys@0 {
		compatible = "syscon";
		reg = <0x0 0x100>;
	};

	rng@24000 {
		compatible = "ti,keystone-rng";
		reg = <0x24000 0x1000>;
		ti,syscon-sa-cfg = <&sa_config>;
		clocks = <&clksa>;
		clock-names = "fck";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Keystone 2 Edison soc device tree
 *
 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
 */

#include <dt-bindings/reset/ti-syscon.h>

/ {
	compatible = "ti,k2e", "ti,keystone";
	model = "Texas Instruments Keystone 2 Edison SoC";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		interrupt-parent = <&gic>;

		cpu@0 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <3>;
		};
	};

	aliases {
		rproc0 = &dsp0;
	};
};

&soc0 {
		/include/ "keystone-k2e-clocks.dtsi"

		usb: usb@2680000 {
			interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
			usb@2690000 {
				interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
			};
		};

		usb1_phy: usb_phy@2620750 {
			compatible = "ti,keystone-usbphy";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2620750 24>;
			status = "disabled";
		};

		keystone_usb1: usb@25000000 {
			compatible = "ti,keystone-dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x25000000 0x10000>;
			clocks = <&clkusb1>;
			clock-names = "usb";
			interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
			ranges;
			dma-coherent;
			dma-ranges;
			status = "disabled";

			usb1: usb@25010000 {
				compatible = "snps,dwc3";
				reg = <0x25010000 0x70000>;
				interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
				usb-phy = <&usb1_phy>, <&usb1_phy>;
			};
		};

		msm_ram: sram@c000000 {
			compatible = "mmio-sram";
			reg = <0x0c000000 0x200000>;
			ranges = <0x0 0x0c000000 0x200000>;
			#address-cells = <1>;
			#size-cells = <1>;

			bm-sram@1f0000 {
				reg = <0x001f0000 0x8000>;
			};
		};

		psc: power-sleep-controller@2350000 {
			pscrst: reset-controller {
				compatible = "ti,k2e-pscrst", "ti,syscon-reset";
				#reset-cells = <1>;

				ti,reset-bits = <
					0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
				>;
			};
		};

		devctrl: device-state-control@2620000 {
			dspgpio0: keystone_dsp_gpio@240 {
				compatible = "ti,keystone-dsp-gpio";
				reg = <0x240 0x4>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio,syscon-dev = <&devctrl 0x240>;
			};
		};

		dsp0: dsp@10800000 {
			compatible = "ti,k2e-dsp";
			reg = <0x10800000 0x00080000>,
			      <0x10e00000 0x00008000>,
			      <0x10f00000 0x00008000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			clocks = <&clkgem0>;
			ti,syscon-dev = <&devctrl 0x844>;
			resets = <&pscrst 0>;
			interrupt-parent = <&kirq0>;
			interrupts = <0 8>;
			interrupt-names = "vring", "exception";
			kick-gpios = <&dspgpio0 27 0>;
			status = "disabled";
		};

		pcie1: pcie@21020000 {
			compatible = "ti,keystone-pcie","snps,dw-pcie";
			clocks = <&clkpcie1>;
			clock-names = "pcie";
			#address-cells = <3>;
			#size-cells = <2>;
			reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
			ranges = <0x82000000 0 0x60000000 0x60000000
				  0 0x10000000>;

			status = "disabled";
			device_type = "pci";
			num-lanes = <2>;
			bus-range = <0x00 0xff>;

			/* error interrupt */
			interrupts = <GIC_SPI 385 IRQ_TYPE_EDGE_RISING>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
					<0 0 0 2 &pcie_intc1 1>, /* INT B */
					<0 0 0 3 &pcie_intc1 2>, /* INT C */
					<0 0 0 4 &pcie_intc1 3>; /* INT D */

			pcie_msi_intc1: msi-interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
			};

			pcie_intc1: legacy-interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
			};
		};

		mdio: mdio@24200f00 {
			compatible = "ti,keystone_mdio", "ti,davinci_mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x24200f00 0x100>;
			status = "disabled";
			clocks = <&clkcpgmac>;
			clock-names = "fck";
			bus_freq = <2500000>;
		};
		/include/ "keystone-k2e-netcp.dtsi"
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for K2G EVM
 *
 * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
 */
/dts-v1/;

#include "keystone-k2g.dtsi"

/ {
	compatible =  "ti,k2g-evm", "ti,k2g", "ti,keystone";
	model = "Texas Instruments K2G General Purpose EVM";

	memory@800000000 {
		device_type = "memory";
		reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp_common_memory: dsp-common-memory@81f800000 {
			compatible = "shared-dma-pool";
			reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
			reusable;
			status = "okay";
		};
	};

	vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin {
		compatible = "regulator-fixed";
		regulator-name = "mmc0_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 {
		compatible = "regulator-fixed";
		regulator-name = "ldo1";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	vcc1v8_ldo2_reg: fixedregulator-vcc1v8-ldo2 {
		compatible = "regulator-fixed";
		regulator-name = "ldo2";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	hdmi: connector {
		compatible = "hdmi-connector";
		label = "hdmi";

		type = "a";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&sii9022_out>;
			};
		};
	};

	aud_mclk: aud_mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <12288000>;
	};

	sound0: sound@0 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "K2G-EVM";
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Line", "Line In";
		simple-audio-card,routing =
			"Headphone Jack",	"HPLOUT",
			"Headphone Jack",	"HPROUT",
			"LINE1L",		"Line In",
			"LINE1R",		"Line In";

		simple-audio-card,dai-link@0 {
			format = "i2s";
			bitclock-master = <&sound0_0_master>;
			frame-master = <&sound0_0_master>;
			sound0_0_master: cpu {
				sound-dai = <&mcasp2>;
				clocks = <&k2g_clks 0x6 1>;
				system-clock-direction-out;
			};

			codec {
				sound-dai = <&tlv320aic3106>;
				clocks = <&aud_mclk>;
			};
		};

		simple-audio-card,dai-link@1 {
			format = "i2s";
			bitclock-master = <&sound0_1_master>;
			frame-master = <&sound0_1_master>;
			sound0_1_master: cpu {
				sound-dai = <&mcasp2>;
				clocks = <&k2g_clks 0x6 1>;
				system-clock-direction-out;
			};

			codec {
				sound-dai = <&sii9022>;
				clocks = <&aud_mclk>;
			};
		};
	};
};

&k2g_pinctrl {
	uart0_pins: pinmux_uart0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
			K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
		>;
	};

	mmc0_pins: pinmux_mmc0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_dat3.mmc0_dat3 */
			K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_dat2.mmc0_dat2 */
			K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_dat1.mmc0_dat1 */
			K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_dat0.mmc0_dat0 */
			K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_clk.mmc0_clk */
			K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)	/* mmc0_cmd.mmc0_cmd */
			K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* mmc0_sdcd.gpio1_12 */
		>;
	};

	mmc1_pins: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat7.mmc1_dat7 */
			K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat6.mmc1_dat6 */
			K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat5.mmc1_dat5 */
			K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat4.mmc1_dat4 */
			K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat3.mmc1_dat3 */
			K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat2.mmc1_dat2 */
			K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat1.mmc1_dat1 */
			K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat0.mmc1_dat0 */
			K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_clk.mmc1_clk */
			K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_cmd.mmc1_cmd */
		>;
	};

	i2c0_pins: pinmux_i2c0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
			K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
		>;
	};

	i2c1_pins: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c1_scl.i2c1_scl */
			K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c1_sda.i2c1_sda */
		>;
	};

	ecap0_pins: ecap0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4)	/* pr1_mdio_data.ecap0_in_apwm0_out */
		>;
	};

	spi1_pins: pinmux_spi1_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* spi1_scs0.spi1_scs0 */
			K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* spi1_clk.spi1_clk */
			K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* spi1_miso.spi1_miso */
			K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* spi1_mosi.spi1_mosi */
		>;
	};

	qspi_pins: pinmux_qspi_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
			K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
			K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
			K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
			K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
			K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
			K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
		>;
	};

	uart2_pins: pinmux_uart2_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* uart2_rxd.uart2_rxd */
			K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)      /* uart2_txd.uart2_txd */
		>;
	};

	dcan0_pins: pinmux_dcan0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE  | MUX_MODE0)	/* dcan0tx.dcan0tx */
			K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN  | MUX_MODE0)	/* dcan0rx.dcan0rx */
		>;
	};

	dcan1_pins: pinmux_dcan1_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE  | MUX_MODE1)	/* qspicsn2.dcan1tx */
			K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN  | MUX_MODE1)	/* qspicsn3.dcan1rx */
		>;
	};

	emac_pins: pinmux_emac_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_RXD1.RGMII_RXD1 */
			K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_RXD2.RGMII_RXD2 */
			K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_RXD3.RGMII_RXD3 */
			K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_RXD0.RGMII_RXD0 */
			K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_TXD0.RGMII_TXD0 */
			K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_TXD1.RGMII_TXD1 */
			K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_TXD2.RGMII_TXD2 */
			K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_TXD3.RGMII_TXD3 */
			K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_TXCLK.RGMII_TXC */
			K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_TXEN.RGMII_TXCTL */
			K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_RXCLK.RGMII_RXC */
			K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_RXDV.RGMII_RXCTL */
		>;
	};

	mdio_pins: pinmux_mdio_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* MDIO_CLK.MDIO_CLK */
			K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* MDIO_DATA.MDIO_DATA */
		>;
	};

	vout_pins: pinmux_vout_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */
			K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */
			K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */
			K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */
			K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */
			K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */
			K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */
			K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */
			K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */
			K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */
			K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */
			K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */
			K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */
			K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */
			K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */
			K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */
			K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */
			K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */
			K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */
			K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */
			K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */
			K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */
			K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */
			K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */
			K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */
			K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */
			K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */
			K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */
			K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */
		>;
	};

	mcasp2_pins: pinmux_mcasp2_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */
			K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */
			K2G_CORE_IOPAD(0x1254) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo10.mcasp2_afsx */
			K2G_CORE_IOPAD(0x125c) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo12.mcasp2_aclkx */
		>;
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	vmmc-supply = <&vcc3v3_dcin_reg>;
	vqmmc-supply = <&vcc3v3_dcin_reg>;
	cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */
	vqmmc-supply = <&vcc1v8_ldo1_reg>;
	ti,non-removable;
	status = "okay";
};

&dsp0 {
	memory-region = <&dsp_common_memory>;
	status = "okay";
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "okay";

	eeprom@50 {
		compatible = "atmel,24c1024";
		reg = <0x50>;
	};
};

&keystone_usb0 {
	status = "okay";
};

&usb0_phy {
	status = "okay";
};

&usb0 {
	dr_mode = "host";
	status = "okay";
};

&keystone_usb1 {
	status = "okay";
};

&usb1_phy {
	status = "okay";
};

&usb1 {
	dr_mode = "peripheral";
	status = "okay";
};

&ecap0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&ecap0_pins>;
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins>;
	status = "okay";

	spi_nor: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <5000000>;
		m25p,fast-read;
		reg = <0>;

		partition@0 {
			label = "u-boot-spl";
			reg = <0x0 0x100000>;
			read-only;
		};

		partition@1 {
			label = "misc";
			reg = <0x100000 0xf00000>;
		};
	};
};

&qspi {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&qspi_pins>;
	cdns,rclk-en;

	flash0: flash@0 {
		compatible = "s25fl512s", "jedec,spi-nor";
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <96000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		cdns,read-delay = <5>;
		cdns,tshsl-ns = <500>;
		cdns,tsd2d-ns = <500>;
		cdns,tchsh-ns = <119>;
		cdns,tslch-ns = <119>;

		partition@0 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x00000000 0x00100000>;
		};
		partition@1 {
			label = "QSPI.u-boot-env";
			reg = <0x00100000 0x00040000>;
		};
		partition@2 {
			label = "QSPI.skern";
			reg = <0x00140000 0x0040000>;
		};
		partition@3 {
			label = "QSPI.pmmc-firmware";
			reg = <0x00180000 0x0040000>;
		};
		partition@4 {
			label = "QSPI.kernel";
			reg = <0x001C0000 0x0800000>;
		};
		partition@5 {
			label = "QSPI.file-system";
			reg = <0x009C0000 0x3640000>;
		};
	};
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
	status = "okay";
};

&dcan0 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan0_pins>;
	status = "okay";
};

&dcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan1_pins>;
	status = "okay";
};

&qmss {
	status = "okay";
};

&knav_dmas {
	status = "okay";
};

&mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	status = "okay";
	ethphy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&gbe0 {
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-rxid";
	status = "okay";
};

&netcp {
	pinctrl-names = "default";
	pinctrl-0 = <&emac_pins>;
	status = "okay";
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "okay";
	clock-frequency = <400000>;

	sii9022: sii9022@3b {
		#sound-dai-cells = <0>;
		compatible = "sil,sii9022";
		reg = <0x3b>;

		sil,i2s-data-lanes = < 0 >;
		clocks = <&aud_mclk>;
		clock-names = "mclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				sii9022_in: endpoint {
					remote-endpoint = <&dpi_out>;
				};
			};

			port@1 {
				reg = <1>;

				sii9022_out: endpoint {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};

	tlv320aic3106: tlv320aic3106@1b {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x1b>;
		status = "okay";

		/* Regulators */
		AVDD-supply = <&vcc3v3_dcin_reg>;
		IOVDD-supply = <&vcc3v3_dcin_reg>;
		DRVDD-supply = <&vcc3v3_dcin_reg>;
		DVDD-supply = <&vcc1v8_ldo2_reg>;
	};
};

&dss {
	pinctrl-names = "default";
	pinctrl-0 = <&vout_pins>;
	status = "ok";

	port {
		dpi_out: endpoint {
			remote-endpoint = <&sii9022_in>;
			data-lines = <24>;
		};
	};
};

&mcasp2 {
	#sound-dai-cells = <0>;

	pinctrl-names = "default";
	pinctrl-0 = <&mcasp2_pins>;

	assigned-clocks = <&k2g_clks 0x4c 2>, <&k2g_clks 0x6 1>;
	assigned-clock-parents = <0>, <&k2g_clks 0x6 2>;
	assigned-clock-rates = <22579200>, <0>;

	status = "okay";

	op-mode = <0>;		/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 6 serializer */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		0 0 1 2 0 0 // AXR2: TX, AXR3: rx
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for K2G Industrial Communication Engine EVM
 *
 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
 */
/dts-v1/;

#include "keystone-k2g.dtsi"
#include <dt-bindings/net/ti-dp83867.h>

/ {
	compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
	model = "Texas Instruments K2G Industrial Communication EVM";

	memory@800000000 {
		device_type = "memory";
		reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp_common_memory: dsp-common-memory@81f800000 {
			compatible = "shared-dma-pool";
			reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
			reusable;
			status = "okay";
		};
	};

	vmain: fixedregulator-vmain {
		compatible = "regulator-fixed";
		regulator-name = "vmain_fixed";
		regulator-min-microvolt = <24000000>;
		regulator-max-microvolt = <24000000>;
		regulator-always-on;
	};

	v5_0: fixedregulator-v5_0 {
		/* TPS54531 */
		compatible = "regulator-fixed";
		regulator-name = "v5_0_fixed";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vmain>;
		regulator-always-on;
	};

	vdd_3v3: fixedregulator-vdd_3v3 {
		/* TLV62084 */
		compatible = "regulator-fixed";
		regulator-name = "vdd_3v3_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&v5_0>;
		regulator-always-on;
	};

	vdd_1v8: fixedregulator-vdd_1v8 {
		/* TLV62084 */
		compatible = "regulator-fixed";
		regulator-name = "vdd_1v8_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&v5_0>;
		regulator-always-on;
	};

	vdds_ddr: fixedregulator-vdds_ddr {
		/* TLV62080 */
		compatible = "regulator-fixed";
		regulator-name = "vdds_ddr_fixed";
		regulator-min-microvolt = <1350000>;
		regulator-max-microvolt = <1350000>;
		vin-supply = <&v5_0>;
		regulator-always-on;
	};

	vref_ddr: fixedregulator-vref_ddr {
		/* LP2996A */
		compatible = "regulator-fixed";
		regulator-name = "vref_ddr_fixed";
		regulator-min-microvolt = <675000>;
		regulator-max-microvolt = <675000>;
		vin-supply = <&vdd_3v3>;
		regulator-always-on;
	};

	vtt_ddr: fixedregulator-vtt_ddr {
		/* LP2996A */
		compatible = "regulator-fixed";
		regulator-name = "vtt_ddr_fixed";
		regulator-min-microvolt = <675000>;
		regulator-max-microvolt = <675000>;
		vin-supply = <&vdd_3v3>;
		regulator-always-on;
	};

	vdd_0v9: fixedregulator-vdd_0v9 {
		/* TPS62180 */
		compatible = "regulator-fixed";
		regulator-name = "vdd_0v9_fixed";
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <900000>;
		vin-supply = <&v5_0>;
		regulator-always-on;
	};

	vddb: fixedregulator-vddb {
		/* TPS22945 */
		compatible = "regulator-fixed";
		regulator-name = "vddb_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&gpio1 53 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	gpio-decoder {
		compatible = "gpio-decoder";
		gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>,
			<&pca9536 2 GPIO_ACTIVE_HIGH>,
			<&pca9536 1 GPIO_ACTIVE_HIGH>,
			<&pca9536 0 GPIO_ACTIVE_HIGH>;
		linux,axis = <0>; /* ABS_X */
		decoder-max-value = <9>;
	};

	leds1 {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&user_leds>;

		led0 {
			label = "status0:red:cpu0";
			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "cpu0";
		};

		led1 {
			label = "status0:green:usr";
			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led2 {
			label = "status0:yellow:usr";
			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led3 {
			label = "status1:red:mmc0";
			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "mmc0";
		};

		led4 {
			label = "status1:green:usr";
			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led5 {
			label = "status1:yellow:usr";
			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led6 {
			label = "status2:red:usr";
			gpios = <&gpio0 44 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led7 {
			label = "status2:green:usr";
			gpios = <&gpio0 43 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led8 {
			label = "status2:yellow:usr";
			gpios = <&gpio0 42 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led9 {
			label = "status3:red:usr";
			gpios = <&gpio0 41 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led10 {
			label = "status3:green:usr";
			gpios = <&gpio0 101 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led11 {
			label = "status3:yellow:usr";
			gpios = <&gpio0 102 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led12 {
			label = "status4:green:heartbeat";
			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};
};

&k2g_pinctrl {
	uart0_pins: pinmux_uart0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
			K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
		>;
	};

	qspi_pins: pinmux_qspi_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
			K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
			K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
			K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
			K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
			K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
			K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
		>;
	};

	mmc1_pins: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x10FC) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat3.mmc1_dat3 */
			K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat2.mmc1_dat2 */
			K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat1.mmc1_dat1 */
			K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_dat0.mmc1_dat0 */
			K2G_CORE_IOPAD(0x110C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_clk.mmc1_clk */
			K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_cmd.mmc1_cmd */
			K2G_CORE_IOPAD(0x1114) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* mmc1_sdcd.gpio0_69 */
			K2G_CORE_IOPAD(0x1118) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_sdwp.mmc1_sdwp */
			K2G_CORE_IOPAD(0x111C) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* mmc1_pow.mmc1_pow */
		>;
	};

	i2c0_pins: pinmux_i2c0_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
			K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
		>;
	};

	i2c1_pins: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c1_scl.i2c1_scl */
			K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)	/* i2c1_sda.i2c1_sda */
		>;
	};

	user_leds: pinmux_user_leds {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_ad11.gpio0_11 */
			K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_ad12.gpio0_12 */
			K2G_CORE_IOPAD(0x1034) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_ad13.gpio0_13 */
			K2G_CORE_IOPAD(0x1038) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_ad14.gpio0_14 */
			K2G_CORE_IOPAD(0x103c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_ad15.gpio0_15 */
			K2G_CORE_IOPAD(0x1040) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_clk.gpio0_16 */
			K2G_CORE_IOPAD(0x104c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* gpmc_wen.gpio0_19 */
			K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* dss_data9.gpio0_44 */
			K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* dss_data10.gpio0_43 */
			K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* dss_data11.gpio0_42 */
			K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* dss_data12.gpio0_41 */
			K2G_CORE_IOPAD(0x11b8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* spi2_scsn0.gpio0_101 */
			K2G_CORE_IOPAD(0x11bc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)	/* spi2_scsn1.gpio0_102 */
		>;
	};

	emac_pins: pinmux_emac_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_RXD1.RGMII_RXD1 */
			K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_RXD2.RGMII_RXD2 */
			K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_RXD3.RGMII_RXD3 */
			K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_RXD0.RGMII_RXD0 */
			K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_TXD0.RGMII_TXD0 */
			K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_TXD1.RGMII_TXD1 */
			K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_TXD2.RGMII_TXD2 */
			K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_TXD3.RGMII_TXD3 */
			K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_TXCLK.RGMII_TXC */
			K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_TXEN.RGMII_TXCTL */
			K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_RXCLK.RGMII_RXC */
			K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)	/* MII_RXDV.RGMII_RXCTL */
		>;
	};

	mdio_pins: pinmux_mdio_pins {
		pinctrl-single,pins = <
			K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* MDIO_CLK.MDIO_CLK */
			K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)	/* MDIO_DATA.MDIO_DATA */
		>;
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&dsp0 {
	memory-region = <&dsp_common_memory>;
	status = "okay";
};

&qspi {
	pinctrl-names = "default";
	pinctrl-0 = <&qspi_pins>;
	cdns,rclk-en;
	status = "okay";

	flash0: flash@0 {
		compatible = "s25fl256s1", "jedec,spi-nor";
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <96000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		cdns,read-delay = <5>;
		cdns,tshsl-ns = <500>;
		cdns,tsd2d-ns = <500>;
		cdns,tchsh-ns = <119>;
		cdns,tslch-ns = <119>;

		partition@0 {
			label = "QSPI.u-boot";
			reg = <0x00000000 0x00100000>;
		};
		partition@1 {
			label = "QSPI.u-boot-env";
			reg = <0x00100000 0x00040000>;
		};
		partition@2 {
			label = "QSPI.skern";
			reg = <0x00140000 0x0040000>;
		};
		partition@3 {
			label = "QSPI.pmmc-firmware";
			reg = <0x00180000 0x0040000>;
		};
		partition@4 {
			label = "QSPI.kernel";
			reg = <0x001c0000 0x0800000>;
		};
		partition@5 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x009c0000 0x0040000>;
		};
		partition@6 {
			label = "QSPI.file-system";
			reg = <0x00a00000 0x1600000>;
		};
	};
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	vmmc-supply = <&vdd_3v3>;
	cd-gpios = <&gpio0 69 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "okay";

	eeprom@50 {
		compatible = "atmel,24c256";
		reg = <0x50>;
	};
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "okay";
	clock-frequency = <400000>;

	pca9536: gpio@41 {
		compatible = "ti,pca9536";
		reg = <0x41>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&vdd_3v3>;
	};
};

&qmss {
	status = "okay";
};

&knav_dmas {
	status = "okay";
};

&netcp {
	pinctrl-names = "default";
	pinctrl-0 = <&emac_pins>;
	status = "okay";
};

&mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	status = "okay";
	ethphy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
		ti,min-output-impedance;
		ti,dp83867-rxctrl-strap-quirk;
	};
};

&gbe0 {
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-id";
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for K2G Netcp driver
 *
 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
 */

qmss: qmss@4020000 {
	compatible = "ti,66ak2g-navss-qm";
	dma-coherent;
	#address-cells = <1>;
	#size-cells = <1>;
	power-domains = <&k2g_pds 0x0018>;
	clocks = <&k2g_clks 0x0018 0>;
	clock-names = "nss_vclk";
	ranges;
	queue-range = <0 0x80>;
	linkram0 = <0x4020000 0x7ff>;
	status = "disabled";

	qmgrs {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		qmgr0 {
			managed-queues = <0 0x80>;
			reg = <0x4100000 0x800>,
			      <0x4040000 0x100>,
			      <0x4080000 0x800>,
			      <0x40c0000 0x800>;
			reg-names = "peek", "config",
				    "region", "push";
		};

	};
	queue-pools {
		qpend {
			qpend-0 {
				qrange = <77 8>;
				interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04
					     0 311 0xf04 0 312 0xf04 0 313 0xf04
					     0 314 0xf04 0 315 0xf04>;
				qalloc-by-id;
			};
		};
		general-purpose {
			gp-0 {
				qrange = <112 8>;
			};
			netcp-tx {
				qrange = <5 8>;
				qalloc-by-id;
			};
		};
	};

	descriptor-regions {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		region-12 {
			id = <12>;
			region-spec = <1023 128>; /* num_desc desc_size */
			link-index = <0x400>;
		};
	};
}; /* qmss */

knav_dmas: knav_dmas@0 {
	compatible = "ti,keystone-navigator-dma";
	#address-cells = <1>;
	#size-cells = <1>;
	status = "disabled";
	power-domains = <&k2g_pds 0x0018>;
	clocks = <&k2g_clks 0x0018 0>;
	clock-names = "nss_vclk";
	ranges;
	ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>;

	dma_gbe: dma_gbe@0 {
		reg = <0x4010000 0x100>,
		      <0x4011000 0x2a0>, /* 21 Tx channels */
		      <0x4012000 0x400>, /* 32 Rx channels */
		      <0x4010100 0x80>,
		      <0x4013000 0x400>; /* 32 Rx flows */
		reg-names = "global", "txchan", "rxchan",
			    "txsched", "rxflow";
	};

};

netcp: netcp@4000000 {
	reg = <0x2620110 0x8>;
	reg-names = "efuse";
	compatible = "ti,netcp-1.0";
	#address-cells = <1>;
	#size-cells = <1>;
	status = "disabled";
	power-domains = <&k2g_pds 0x0018>;
	clocks = <&k2g_clks 0x0018 3>, <&k2g_clks 0x0018 8>;
	clock-names = "ethss_clk", "cpts";

	/* NetCP address range */
	ranges = <0 0x4000000 0x1000000>;

	dma-coherent;

	ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>;
	ti,navigator-dma-names = "netrx0", "nettx";

	netcp-devices {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		gbe: gbe@200000 {
			label = "netcp-gbe";
			compatible = "ti,netcp-gbe-2";
			reg = <0x200000 0x20>, <0x220000 0x20000>;
			enable-ale;
			tx-queue = <5>;
			tx-channel = "nettx";
			cpts-rftclk-sel = <0>;
			cpts-ext-ts-inputs = <8>;

			interfaces {
				gbe0: interface-0 {
					slave-port = <0>;
					link-interface = <5>;
				};
			};
		};
	};

	netcp-interfaces {
		interface-0 {
			rx-channel = "netrx0";
			rx-pool = <512 12>;
			tx-pool = <511 12>;
			rx-queue-depth = <128 128 0 0>;
			rx-buffer-size = <1518 4096 0 0>;
			rx-queue = <77>;
			tx-completion-queue = <78>;
			efuse-mac = <1>;
			netcp-gbe = <&gbe0>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for K2G SOC
 *
 * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/keystone.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "ti,k2g","ti,keystone";
	model = "Texas Instruments K2G SoC";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	chosen { };

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		rproc0 = &dsp0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0>;
		};
	};

	gic: interrupt-controller@2561000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x02561000 0x0 0x1000>,
		      <0x0 0x02562000 0x0 0x2000>,
		      <0x0 0x02564000 0x0 0x2000>,
		      <0x0 0x02566000 0x0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
				IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts =
			<GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
	};

	usbphy {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "simple-bus";

		usb0_phy: usb-phy@0 {
			compatible = "usb-nop-xceiv";
			reg = <0>;
			status = "disabled";
		};

		usb1_phy: usb-phy@1 {
			compatible = "usb-nop-xceiv";
			reg = <1>;
			status = "disabled";
		};
	};

	soc0: soc@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		#pinctrl-cells = <1>;
		compatible = "ti,keystone","simple-bus";
		ranges = <0x0 0x0 0x0 0xc0000000>;
		dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;

		msm_ram: sram@c000000 {
			compatible = "mmio-sram";
			reg = <0x0c000000 0x100000>;
			ranges = <0x0 0x0c000000 0x100000>;
			#address-cells = <1>;
			#size-cells = <1>;

			bm-sram@f7000 {
				reg = <0x000f7000 0x8000>;
			};
		};

		k2g_pinctrl: pinmux@2621000 {
			compatible = "pinctrl-single";
			reg = <0x02621000 0x410>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0x001b0007>;
		};

		devctrl: device-state-control@2620000 {
			compatible = "ti,keystone-devctrl", "syscon", "simple-mfd";
			reg = <0x02620000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x02620000 0x1000>;

			kirq0: keystone_irq@2a0 {
				compatible = "ti,keystone-irq";
				reg = <0x2a0 0x10>;
				interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>;
				interrupt-controller;
				#interrupt-cells = <1>;
				ti,syscon-dev = <&devctrl 0x2a0>;
			};

			dspgpio0: keystone_dsp_gpio@240 {
				compatible = "ti,keystone-dsp-gpio";
				reg = <0x240 0x4>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio,syscon-dev = <&devctrl 0x240>;
			};
		};

		uart0: serial@2530c00 {
			compatible = "ti,da830-uart", "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02530c00 0x100>;
			interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
			clocks = <&k2g_clks 0x2c 0>;
			power-domains = <&k2g_pds 0x2c>;
			status = "disabled";
		};

		uart1: serial@2531000 {
			compatible = "ti,da830-uart", "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02531000 0x100>;
			interrupts = <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>;
			clocks = <&k2g_clks 0x2d 0>;
			power-domains = <&k2g_pds 0x2d>;
			status = "disabled";
		};

		uart2: serial@2531400 {
			compatible = "ti,da830-uart", "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02531400 0x100>;
			interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
			clocks = <&k2g_clks 0x2e 0>;
			power-domains = <&k2g_pds 0x2e>;
			status = "disabled";
		};

		dcan0: can@260b200 {
			compatible = "ti,am4372-d_can", "ti,am3352-d_can";
			reg = <0x0260B200 0x200>;
			interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
			power-domains = <&k2g_pds 0x0008>;
			clocks = <&k2g_clks 0x0008 1>;
		};

		dcan1: can@260b400 {
			compatible = "ti,am4372-d_can", "ti,am3352-d_can";
			reg = <0x0260B400 0x200>;
			interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
			power-domains = <&k2g_pds 0x0009>;
			clocks = <&k2g_clks 0x0009 1>;
		};

		i2c0: i2c@2530000 {
			compatible = "ti,keystone-i2c";
			reg = <0x02530000 0x400>;
			clocks = <&k2g_clks 0x003a 0>;
			power-domains = <&k2g_pds 0x003a>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@2530400 {
			compatible = "ti,keystone-i2c";
			reg = <0x02530400 0x400>;
			clocks = <&k2g_clks 0x003b 0>;
			power-domains = <&k2g_pds 0x003b>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@2530800 {
			compatible = "ti,keystone-i2c";
			reg = <0x02530800 0x400>;
			clocks = <&k2g_clks 0x003c 0>;
			power-domains = <&k2g_pds 0x003c>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		dsp0: dsp@10800000 {
			compatible = "ti,k2g-dsp";
			reg = <0x10800000 0x00100000>,
			      <0x10e00000 0x00008000>,
			      <0x10f00000 0x00008000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			power-domains = <&k2g_pds 0x0046>;
			ti,syscon-dev = <&devctrl 0x844>;
			resets = <&k2g_reset 0x0046 0x1>;
			interrupt-parent = <&kirq0>;
			interrupts = <0 8>;
			interrupt-names = "vring", "exception";
			kick-gpios = <&dspgpio0 27 0>;
			status = "disabled";
		};

		msgmgr: mailbox@2a00000 {
			compatible = "ti,k2g-message-manager";
			#mbox-cells = <2>;
			reg-names = "queue_proxy_region",
				    "queue_state_debug_region";
			reg = <0x02a00000 0x400000>, <0x028c3400 0x400>;
			interrupt-names = "rx_005",
					  "rx_057";
			interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
		};

		pmmc: system-controller@2921c00 {
			compatible = "ti,k2g-sci";
			/*
			 * In case of rare platforms that does not use k2g as
			 * system master, use /delete-property/
			 */
			ti,system-reboot-controller;
			mbox-names = "rx", "tx";
			mboxes = <&msgmgr 5 2>,
				<&msgmgr 0 0>;
			reg-names = "debug_messages";
			reg = <0x02921c00 0x400>;

			k2g_pds: power-controller {
				compatible = "ti,sci-pm-domain";
				#power-domain-cells = <1>;
			};

			k2g_clks: clock-controller {
				compatible = "ti,k2g-sci-clk";
				#clock-cells = <2>;
			};

			k2g_reset: reset-controller {
				compatible = "ti,sci-reset";
				#reset-cells = <2>;
			};
		};

		gpio0: gpio@2603000 {
			compatible = "ti,k2g-gpio", "ti,keystone-gpio";
			reg = <0x02603000 0x100>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,ngpio = <144>;
			ti,davinci-gpio-unbanked = <0>;
			clocks = <&k2g_clks 0x001b 0x0>;
			clock-names = "gpio";
		};

		gpio1: gpio@260a000 {
			compatible = "ti,k2g-gpio", "ti,keystone-gpio";
			reg = <0x0260a000 0x100>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 442 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 443 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 444 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 445 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 446 IRQ_TYPE_EDGE_RISING>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ti,ngpio = <68>;
			ti,davinci-gpio-unbanked = <0>;
			clocks = <&k2g_clks 0x001c 0x0>;
			clock-names = "gpio";
		};

		dss: dss@02540000 {
			compatible = "ti,k2g-dss";
			reg = <0x02540000 0x400>,
				<0x02550000 0x1000>,
				<0x02557000 0x1000>,
				<0x0255a800 0x100>,
				<0x0255ac00 0x100>;
			reg-names = "cfg", "common", "vid1", "ovr1", "vp1";
			clocks = <&k2g_clks 0x2 0>,
					<&k2g_clks 0x2 1>;
			clock-names = "fck", "vp1";
			interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>;

			power-domains = <&k2g_pds 0x2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			max-memory-bandwidth = <230000000>;
		};

		edma0: edma@2700000 {
			compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
			reg = <0x02700000 0x8000>;
			reg-names = "edma3_cc";
			interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 216 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "edma3_ccint", "emda3_mperr",
					  "edma3_ccerrint";
			dma-requests = <64>;
			#dma-cells = <2>;

			ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;

			ti,edma-memcpy-channels = <32 33 34 35>;

			power-domains = <&k2g_pds 0x3f>;
		};

		edma0_tptc0: tptc@2760000 {
			compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
			reg = <0x02760000 0x400>;
			power-domains = <&k2g_pds 0x3f>;
		};

		edma0_tptc1: tptc@2768000 {
			compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
			reg = <0x02768000 0x400>;
			power-domains = <&k2g_pds 0x3f>;
		};

		edma1: edma@2728000 {
			compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
			reg = <0x02728000 0x8000>;
			reg-names = "edma3_cc";
			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
					<GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "edma3_ccint", "emda3_mperr",
					  "edma3_ccerrint";
			dma-requests = <64>;
			#dma-cells = <2>;

			ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;

			/*
			 * memcpy is disabled, can be enabled with:
			 * ti,edma-memcpy-channels = <12 13 14 15>;
			 * for example.
			 */

			power-domains = <&k2g_pds 0x4f>;
		};

		edma1_tptc0: tptc@27b0000 {
			compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
			reg = <0x027b0000 0x400>;
			power-domains = <&k2g_pds 0x4f>;
		};

		edma1_tptc1: tptc@27b8000 {
			compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
			reg = <0x027b8000 0x400>;
			power-domains = <&k2g_pds 0x4f>;
		};

		mmc0: mmc@23000000 {
			compatible = "ti,k2g-sdhci";
			reg = <0x23000000 0x400>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
			bus-width = <4>;
			no-1-8-v;
			max-frequency = <96000000>;
			power-domains = <&k2g_pds 0xb>;
			clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
			clock-names = "fck", "mmchsdb_fck";
			status = "disabled";
		};

		mmc1: mmc@23100000 {
			compatible = "ti,k2g-sdhci";
			reg = <0x23100000 0x400>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
			bus-width = <8>;
			no-1-8-v;
			non-removable;
			max-frequency = <96000000>;
			power-domains = <&k2g_pds 0xc>;
			clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>;
			clock-names = "fck", "mmchsdb_fck";
		};

		qspi: spi@2940000 {
			compatible = "ti,k2g-qspi", "cdns,qspi-nor";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x02940000 0x1000>,
			      <0x24000000 0x4000000>;
			interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
			cdns,fifo-depth = <256>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x24000000>;
			clocks = <&k2g_clks 0x43 0x0>;
			power-domains = <&k2g_pds 0x43>;
			status = "disabled";
		};

		mcasp0: mcasp@2340000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x02340000 0x2000>,
			      <0x21804000 0x1000>;
			reg-names = "mpu","dat";
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tx", "rx";
			dmas = <&edma0 24 1>, <&edma0 25 1>;
			dma-names = "tx", "rx";
			power-domains = <&k2g_pds 0x4>;
			clocks = <&k2g_clks 0x4 0>;
			clock-names = "fck";
			status = "disabled";
		};

		mcasp1: mcasp@2342000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x02342000 0x2000>,
			      <0x21804400 0x1000>;
			reg-names = "mpu","dat";
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tx", "rx";
			dmas = <&edma1 48 1>, <&edma1 49 1>;
			dma-names = "tx", "rx";
			power-domains = <&k2g_pds 0x5>;
			clocks = <&k2g_clks 0x5 0>;
			clock-names = "fck";
			status = "disabled";
		};

		mcasp2: mcasp@2344000 {
			compatible = "ti,am33xx-mcasp-audio";
			reg = <0x02344000 0x2000>,
			      <0x21804800 0x1000>;
			reg-names = "mpu","dat";
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tx", "rx";
			dmas = <&edma1 50 1>, <&edma1 51 1>;
			dma-names = "tx", "rx";
			power-domains = <&k2g_pds 0x6>;
			clocks = <&k2g_clks 0x6 0>;
			clock-names = "fck";
			status = "disabled";
		};

		keystone_usb0: keystone-dwc3@2680000 {
			compatible = "ti,keystone-dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2680000 0x10000>;
			interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
			ranges;
			dma-coherent;
			dma-ranges;
			status = "disabled";
			power-domains = <&k2g_pds 0x0016>;

			usb0: usb@2690000 {
				compatible = "snps,dwc3";
				reg = <0x2690000 0x10000>;
				interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
				maximum-speed = "high-speed";
				dr_mode = "otg";
				usb-phy = <&usb0_phy>;
				status = "disabled";
			};
		};

		keystone_usb1: keystone-dwc3@2580000 {
			compatible = "ti,keystone-dwc3";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2580000 0x10000>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
			ranges;
			dma-coherent;
			dma-ranges;
			status = "disabled";
			power-domains = <&k2g_pds 0x0017>;

			usb1: usb@2590000 {
				compatible = "snps,dwc3";
				reg = <0x2590000 0x10000>;
				interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
				maximum-speed = "high-speed";
				dr_mode = "otg";
				usb-phy = <&usb1_phy>;
				status = "disabled";
			};
		};

		ecap0: pwm@21d1800 {
			compatible = "ti,k2g-ecap", "ti,am3352-ecap";
			#pwm-cells = <3>;
			reg = <0x021d1800 0x60>;
			power-domains = <&k2g_pds 0x38>;
			clocks = <&k2g_clks 0x38 0>;
			clock-names = "fck";
			status = "disabled";
		};

		ecap1: pwm@21d1c00 {
			compatible = "ti,k2g-ecap", "ti,am3352-ecap";
			#pwm-cells = <3>;
			reg = <0x021d1c00 0x60>;
			power-domains = <&k2g_pds 0x39>;
			clocks = <&k2g_clks 0x39 0x0>;
			clock-names = "fck";
			status = "disabled";
		};

		spi0: spi@21805400 {
			compatible = "ti,keystone-spi";
			reg = <0x21805400 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
			power-domains = <&k2g_pds 0x0010>;
			clocks = <&k2g_clks 0x0010 0>;
		};

		spi1: spi@21805800 {
			compatible = "ti,keystone-spi";
			reg = <0x21805800 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
			power-domains = <&k2g_pds 0x0011>;
			clocks = <&k2g_clks 0x0011 0>;
		};

		spi2: spi@21805c00 {
			compatible = "ti,keystone-spi";
			reg = <0x21805C00 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
			power-domains = <&k2g_pds 0x0012>;
			clocks = <&k2g_clks 0x0012 0>;
		};

		spi3: spi@21806000 {
			compatible = "ti,keystone-spi";
			reg = <0x21806000 0x200>;
			num-cs = <4>;
			ti,davinci-spi-intr-line = <0>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
			power-domains = <&k2g_pds 0x0013>;
			clocks = <&k2g_clks 0x0013 0>;
		};

		wdt: wdt@02250000 {
			compatible = "ti,keystone-wdt", "ti,davinci-wdt";
			reg = <0x02250000 0x80>;
			power-domains = <&k2g_pds 0x22>;
			clocks = <&k2g_clks 0x22 0>;
		};

		emif: emif@21010000 {
			compatible = "ti,emif-keystone";
			reg = <0x21010000 0x200>;
			interrupts = <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>;
		};

		mdio: mdio@4200f00 {
			compatible = "ti,keystone_mdio", "ti,davinci_mdio";
			reg = <0x04200f00 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&k2g_clks 0x0018 3>;
			clock-names = "fck";
			power-domains = <&k2g_pds 0x0018>;
			status = "disabled";
			bus_freq = <2500000>;
		};
		#include "keystone-k2g-netcp.dtsi"
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Keystone 2 Kepler/Hawking SoC clock nodes
 *
 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
 */

clocks {
	armpllclk: armpllclk@2620370 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-clock";
		clocks = <&refclkarm>;
		clock-output-names = "arm-pll-clk";
		reg = <0x02620370 4>;
		reg-names = "control";
	};

	mainpllclk: mainpllclk@2310110 {
		#clock-cells = <0>;
		compatible = "ti,keystone,main-pll-clock";
		clocks = <&refclksys>;
		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
		reg-names = "control", "multiplier", "post-divider";
	};

	papllclk: papllclk@2620358 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-clock";
		clocks = <&refclkpass>;
		clock-output-names = "papllclk";
		reg = <0x02620358 4>;
		reg-names = "control";
	};

	ddr3apllclk: ddr3apllclk@2620360 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-clock";
		clocks = <&refclkddr3a>;
		clock-output-names = "ddr-3a-pll-clk";
		reg = <0x02620360 4>;
		reg-names = "control";
	};

	ddr3bpllclk: ddr3bpllclk@2620368 {
		#clock-cells = <0>;
		compatible = "ti,keystone,pll-clock";
		clocks = <&refclkddr3b>;
		clock-output-names = "ddr-3b-pll-clk";
		reg = <0x02620368 4>;
		reg-names = "control";
	};

	clktsip: clktsip@2350000 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk16>;
		clock-output-names = "tsip";
		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
		reg-names = "control", "domain";
		domain-id = <0>;
	};

	clksrio: clksrio@235002c {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1rstiso13>;
		clock-output-names = "srio";
		reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
		reg-names = "control", "domain";
		domain-id = <4>;
	};

	clkhyperlink0: clkhyperlink0@2350030 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk12>;
		clock-output-names = "hyperlink-0";
		reg = <0x02350030 0xb00>, <0x02350014 0x400>;
		reg-names = "control", "domain";
		domain-id = <5>;
	};

	clkgem1: clkgem1@2350040 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1>;
		clock-output-names = "gem1";
		reg = <0x02350040 0xb00>, <0x02350024 0x400>;
		reg-names = "control", "domain";
		domain-id = <9>;
	};

	clkgem2: clkgem2@2350044 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1>;
		clock-output-names = "gem2";
		reg = <0x02350044 0xb00>, <0x02350028 0x400>;
		reg-names = "control", "domain";
		domain-id = <10>;
	};

	clkgem3: clkgem3@2350048 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1>;
		clock-output-names = "gem3";
		reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
		reg-names = "control", "domain";
		domain-id = <11>;
	};

	clkgem4: clkgem4@235004c {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1>;
		clock-output-names = "gem4";
		reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
		reg-names = "control", "domain";
		domain-id = <12>;
	};

	clkgem5: clkgem5@2350050 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1>;
		clock-output-names = "gem5";
		reg = <0x02350050 0xb00>, <0x02350034 0x400>;
		reg-names = "control", "domain";
		domain-id = <13>;
	};

	clkgem6: clkgem6@2350054 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1>;
		clock-output-names = "gem6";
		reg = <0x02350054 0xb00>, <0x02350038 0x400>;
		reg-names = "control", "domain";
		domain-id = <14>;
	};

	clkgem7: clkgem7@2350058 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk1>;
		clock-output-names = "gem7";
		reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
		reg-names = "control", "domain";
		domain-id = <15>;
	};

	clkddr31: clkddr31@2350060 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "ddr3-1";
		reg = <0x02350060 0xb00>, <0x02350040 0x400>;
		reg-names = "control", "domain";
		domain-id = <16>;
	};

	clktac: clktac@2350064 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "tac";
		reg = <0x02350064 0xb00>, <0x02350044 0x400>;
		reg-names = "control", "domain";
		domain-id = <17>;
	};

	clkrac01: clkrac01@2350068 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "rac-01";
		reg = <0x02350068 0xb00>, <0x02350044 0x400>;
		reg-names = "control", "domain";
		domain-id = <17>;
	};

	clkrac23: clkrac23@235006c {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "rac-23";
		reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
		reg-names = "control", "domain";
		domain-id = <18>;
	};

	clkfftc0: clkfftc0@2350070 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "fftc-0";
		reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
		reg-names = "control", "domain";
		domain-id = <19>;
	};

	clkfftc1: clkfftc1@2350074 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "fftc-1";
		reg = <0x02350074 0xb00>, <0x0235004c 0x400>;
		reg-names = "control", "domain";
		domain-id = <19>;
	};

	clkfftc2: clkfftc2@2350078 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "fftc-2";
		reg = <0x02350078 0xb00>, <0x02350050 0x400>;
		reg-names = "control", "domain";
		domain-id = <20>;
	};

	clkfftc3: clkfftc3@235007c {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "fftc-3";
		reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
		reg-names = "control", "domain";
		domain-id = <20>;
	};

	clkfftc4: clkfftc4@2350080 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "fftc-4";
		reg = <0x02350080 0xb00>, <0x02350050 0x400>;
		reg-names = "control", "domain";
		domain-id = <20>;
	};

	clkfftc5: clkfftc5@2350084 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "fftc-5";
		reg = <0x02350084 0xb00>, <0x02350050 0x400>;
		reg-names = "control", "domain";
		domain-id = <20>;
	};

	clkaif: clkaif@2350088 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "aif";
		reg = <0x02350088 0xb00>, <0x02350054 0x400>;
		reg-names = "control", "domain";
		domain-id = <21>;
	};

	clktcp3d0: clktcp3d0@235008c {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "tcp3d-0";
		reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
		reg-names = "control", "domain";
		domain-id = <22>;
	};

	clktcp3d1: clktcp3d1@2350090 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "tcp3d-1";
		reg = <0x02350090 0xb00>, <0x02350058 0x400>;
		reg-names = "control", "domain";
		domain-id = <22>;
	};

	clktcp3d2: clktcp3d2@2350094 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "tcp3d-2";
		reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
		reg-names = "control", "domain";
		domain-id = <23>;
	};

	clktcp3d3: clktcp3d3@2350098 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "tcp3d-3";
		reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
		reg-names = "control", "domain";
		domain-id = <23>;
	};

	clkvcp0: clkvcp0@235009c {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "vcp-0";
		reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
		reg-names = "control", "domain";
		domain-id = <24>;
	};

	clkvcp1: clkvcp1@23500a0 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "vcp-1";
		reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
		reg-names = "control", "domain";
		domain-id = <24>;
	};

	clkvcp2: clkvcp2@23500a4 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "vcp-2";
		reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
		reg-names = "control", "domain";
		domain-id = <24>;
	};

	clkvcp3: clkvcp3@23500a8 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "vcp-3";
		reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
		reg-names = "control", "domain";
		domain-id = <24>;
	};

	clkvcp4: clkvcp4@23500ac {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "vcp-4";
		reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
		reg-names = "control", "domain";
		domain-id = <25>;
	};

	clkvcp5: clkvcp5@23500b0 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "vcp-5";
		reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
		reg-names = "control", "domain";
		domain-id = <25>;
	};

	clkvcp6: clkvcp6@23500b4 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "vcp-6";
		reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
		reg-names = "control", "domain";
		domain-id = <25>;
	};

	clkvcp7: clkvcp7@23500b8 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "vcp-7";
		reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
		reg-names = "control", "domain";
		domain-id = <25>;
	};

	clkbcp: clkbcp@23500bc {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "bcp";
		reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
		reg-names = "control", "domain";
		domain-id = <26>;
	};

	clkdxb: clkdxb@23500c0 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "dxb";
		reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
		reg-names = "control", "domain";
		domain-id = <27>;
	};

	clkhyperlink1: clkhyperlink1@23500c4 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk12>;
		clock-output-names = "hyperlink-1";
		reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
		reg-names = "control", "domain";
		domain-id = <28>;
	};

	clkxge: clkxge@23500c8 {
		#clock-cells = <0>;
		compatible = "ti,keystone,psc-clock";
		clocks = <&chipclk13>;
		clock-output-names = "xge";
		reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
		reg-names = "control", "domain";
		domain-id = <29>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Keystone 2 Kepler/Hawking EVM device tree
 *
 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
 */
/dts-v1/;

#include "keystone.dtsi"
#include "keystone-k2hk.dtsi"

/ {
	compatible =  "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
	model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp_common_memory: dsp-common-memory@81f800000 {
			compatible = "shared-dma-pool";
			reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
			reusable;
			status = "okay";
		};
	};

	leds {
		compatible = "gpio-leds";
		debug1_1 {
			label = "keystone:green:debug1";
			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */
		};

		debug1_2 {
			label = "keystone:red:debug1";
			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */
		};

		debug2 {
			label = "keystone:blue:debug2";
			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */
		};

		debug3 {
			label = "keystone:blue:debug3";
			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */
		};
	};
};

&soc0 {
		clocks {
			refclksys: refclksys {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <122880000>;
				clock-output-names = "refclk-sys";
			};

			refclkpass: refclkpass {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <122880000>;
				clock-output-names = "refclk-pass";
			};

			refclkarm: refclkarm {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <125000000>;
				clock-output-names = "refclk-arm";
			};

			refclkddr3a: refclkddr3a {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <100000000>;
				clock-output-names = "refclk-ddr3a";
			};

			refclkddr3b: refclkddr3b {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <100000000>;
				clock-output-names = "refclk-ddr3b";
			};
		};
};

&usb_phy {
	status = "okay";
};

&keystone_usb0 {
	status = "okay";
};

&usb0 {
	dr_mode = "host";
};

&aemif {
	cs0 {
		#address-cells = <2>;
		#size-cells = <1>;
		clock-ranges;
		ranges;

		ti,cs-chipselect = <0>;
		/* all timings in nanoseconds */
		ti,cs-min-turnaround-ns = <12>;
		ti,cs-read-hold-ns = <6>;
		ti,cs-read-strobe-ns = <23>;
		ti,cs-read-setup-ns = <9>;
		ti,cs-write-hold-ns = <8>;
		ti,cs-write-strobe-ns = <23>;
		ti,cs-write-setup-ns = <8>;

		nand@0,0 {
			compatible = "ti,keystone-nand","ti,davinci-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0 0 0x4000000
			       1 0 0x0000100>;

			ti,davinci-chipselect = <0>;
			ti,davinci-mask-ale = <0x2000>;
			ti,davinci-mask-cle = <0x4000>;
			ti,davinci-mask-chipsel = <0>;
			nand-ecc-mode = "hw";
			ti,davinci-ecc-bits = <4>;
			nand-on-flash-bbt;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x100000>;
				read-only;
			};

			partition@100000 {
				label = "params";
				reg = <0x100000 0x80000>;
				read-only;
			};

			partition@180000 {
				label = "ubifs";
				reg = <0x180000 0x1fe80000>;
			};
		};
	};
};

&i2c0 {
	dtt@50 {
		compatible = "atmel,24c1024";
		reg = <0x50>;
	};
};

&spi0 {
	nor_flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q128a11", "jedec,spi-nor";
		spi-max-frequency = <54000000>;
		m25p,fast-read;
		reg = <0>;

		partition@0 {
			label = "u-boot-spl";
			reg = <0x0 0x80000>;
			read-only;
		};

		partition@1 {
			label = "misc";
			reg = <0x80000 0xf80000>;
		};
	};
};

&mdio {
	status = "ok";
	ethphy0: ethernet-phy@0 {
		compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
		reg = <0>;
	};

	ethphy1: ethernet-phy@1 {
		compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
		reg = <1>;
	};
};

&dsp0 {
	memory-region = <&dsp_common_memory>;
	status = "okay";
};

&dsp1 {
	memory-region = <&dsp_common_memory>;
	status = "okay";
};

&dsp2 {
	memory-region = <&dsp_common_memory>;
	status = "okay";
};

&dsp3 {
	memory-region = <&dsp_common_memory>;
	status = "okay";
};

&dsp4 {
	memory-region = <&dsp_common_memory>;
	status = "okay";
};

&dsp5 {
	memory-region = <&dsp_common_memory>;
	status = "okay";
};

&dsp6 {
	memory-region = <&dsp_common_memory>;
	status = "okay";
};

&dsp7 {
	memory-region = <&dsp_common_memory>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Keystone 2 Kepler/Hawking soc specific device tree
 *
 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
 */

#include <dt-bindings/reset/ti-syscon.h>

/ {
	compatible = "ti,k2hk", "ti,keystone";
	model = "Texas Instruments Keystone 2 Kepler/Hawking SoC";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		interrupt-parent = <&gic>;

		cpu@0 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <3>;
		};
	};

	aliases {
		rproc0 = &dsp0;
		rproc1 = &dsp1;
		rproc2 = &dsp2;
		rproc3 = &dsp3;
		rproc4 = &dsp4;
		rproc5 = &dsp5;
		rproc6 = &dsp6;
		rproc7 = &dsp7;
	};
};

&soc0 {
		/include/ "keystone-k2hk-clocks.dtsi"

		msm_ram: sram@c000000 {
			compatible = "mmio-sram";
			reg = <0x0c000000 0x600000>;
			ranges = <0x0 0x0c000000 0x600000>;
			#address-cells = <1>;
			#size-cells = <1>;

			bm-sram@5f0000 {
				reg = <0x5f0000 0x8000>;
			};
		};

		psc: power-sleep-controller@2350000 {
			pscrst: reset-controller {
				compatible = "ti,k2hk-pscrst", "ti,syscon-reset";
				#reset-cells = <1>;

				ti,reset-bits = <
					0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
					0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
					0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
					0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
					0xa4c 8 0xa4c 8 0x84c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 4: dsp4 */
					0xa50 8 0xa50 8 0x850 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 5: dsp5 */
					0xa54 8 0xa54 8 0x854 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 6: dsp6 */
					0xa58 8 0xa58 8 0x858 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 7: dsp7 */
				>;
			};
		};

		devctrl: device-state-control@2620000 {
			dspgpio0: keystone_dsp_gpio@240 {
				compatible = "ti,keystone-dsp-gpio";
				reg = <0x240 0x4>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio,syscon-dev = <&devctrl 0x240>;
			};

			dspgpio1: keystone_dsp_gpio@244 {
				compatible = "ti,keystone-dsp-gpio";
				reg = <0x244 0x4>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio,syscon-dev = <&devctrl 0x244>;
			};

			dspgpio2: keystone_dsp_gpio@248 {
				compatible = "ti,keystone-dsp-gpio";
				reg = <0x248 0x4>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio,syscon-dev = <&devctrl 0x248>;
			};

			dspgpio3: keystone_dsp_gpio@24c {
				compatible = "ti,keystone-dsp-gpio";
				reg = <0x24c 0x4>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio,syscon-dev = <&devctrl 0x24c>;
			};

			dspgpio4: keystone_dsp_gpio@250 {
				compatible = "ti,keystone-dsp-gpio";
				reg = <0x250 0x4>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio,syscon-dev = <&devctrl 0x250>;
			};

			dspgpio5: keystone_dsp_gpio@254 {
				compatible = "ti,keystone-dsp-gpio";
				reg = <0x254 0x4>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio,syscon-dev = <&devctrl 0x254>;
			};

			dspgpio6: keystone_dsp_gpio@258 {
				compatible = "ti,keystone-dsp-gpio";
				reg = <0x258 0x4>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio,syscon-dev = <&devctrl 0x258>;
			};

			dspgpio7: keystone_dsp_gpio@25c {
				compatible = "ti,keystone-dsp-gpio";
				reg = <0x25c 0x4>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio,syscon-dev = <&devctrl 0x25c>;
			};
		};

		dsp0: dsp@10800000 {
			compatible = "ti,k2hk-dsp";
			reg = <0x10800000 0x00100000>,
			      <0x10e00000 0x00008000>,
			      <0x10f00000 0x00008000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			clocks = <&clkgem0>;
			ti,syscon-dev = <&devctrl 0x40>;
			resets = <&pscrst 0>;
			interrupt-parent = <&kirq0>;
			interrupts = <0 8>;
			interrupt-names = "vring", "exception";
			kick-gpios = <&dspgpio0 27 0>;
			status = "disabled";
		};

		dsp1: dsp@11800000 {
			compatible = "ti,k2hk-dsp";
			reg = <0x11800000 0x00100000>,
			      <0x11e00000 0x00008000>,
			      <0x11f00000 0x00008000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			clocks = <&clkgem1>;
			ti,syscon-dev = <&devctrl 0x44>;
			resets = <&pscrst 1>;
			interrupt-parent = <&kirq0>;
			interrupts = <1 9>;
			interrupt-names = "vring", "exception";
			kick-gpios = <&dspgpio1 27 0>;
			status = "disabled";
		};

		dsp2: dsp@12800000 {
			compatible = "ti,k2hk-dsp";
			reg = <0x12800000 0x00100000>,
			      <0x12e00000 0x00008000>,
			      <0x12f00000 0x00008000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			clocks = <&clkgem2>;
			ti,syscon-dev = <&devctrl 0x48>;
			resets = <&pscrst 2>;
			interrupt-parent = <&kirq0>;
			interrupts = <2 10>;
			interrupt-names = "vring", "exception";
			kick-gpios = <&dspgpio2 27 0>;
			status = "disabled";
		};

		dsp3: dsp@13800000 {
			compatible = "ti,k2hk-dsp";
			reg = <0x13800000 0x00100000>,
			      <0x13e00000 0x00008000>,
			      <0x13f00000 0x00008000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			clocks = <&clkgem3>;
			ti,syscon-dev = <&devctrl 0x4c>;
			resets = <&pscrst 3>;
			interrupt-parent = <&kirq0>;
			interrupts = <3 11>;
			interrupt-names = "vring", "exception";
			kick-gpios = <&dspgpio3 27 0>;
			status = "disabled";
		};

		dsp4: dsp@14800000 {
			compatible = "ti,k2hk-dsp";
			reg = <0x14800000 0x00100000>,
			      <0x14e00000 0x00008000>,
			      <0x14f00000 0x00008000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			clocks = <&clkgem4>;
			ti,syscon-dev = <&devctrl 0x50>;
			resets = <&pscrst 4>;
			interrupt-parent = <&kirq0>;
			interrupts = <4 12>;
			interrupt-names = "vring", "exception";
			kick-gpios = <&dspgpio4 27 0>;
			status = "disabled";
		};

		dsp5: dsp@15800000 {
			compatible = "ti,k2hk-dsp";
			reg = <0x15800000 0x00100000>,
			      <0x15e00000 0x00008000>,
			      <0x15f00000 0x00008000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			clocks = <&clkgem5>;
			ti,syscon-dev = <&devctrl 0x54>;
			resets = <&pscrst 5>;
			interrupt-parent = <&kirq0>;
			interrupts = <5 13>;
			interrupt-names = "vring", "exception";
			kick-gpios = <&dspgpio5 27 0>;
			status = "disabled";
		};

		dsp6: dsp@16800000 {
			compatible = "ti,k2hk-dsp";
			reg = <0x16800000 0x00100000>,
			      <0x16e00000 0x00008000>,
			      <0x16f00000 0x00008000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			clocks = <&clkgem6>;
			ti,syscon-dev = <&devctrl 0x58>;
			resets = <&pscrst 6>;
			interrupt-parent = <&kirq0>;
			interrupts = <6 14>;
			interrupt-names = "vring", "exception";
			kick-gpios = <&dspgpio6 27 0>;
			status = "disabled";
		};

		dsp7: dsp@17800000 {
			compatible = "ti,k2hk-dsp";
			reg = <0x17800000 0x00100000>,
			      <0x17e00000 0x00008000>,
			      <0x17f00000 0x00008000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			clocks = <&clkgem7>;
			ti,syscon-dev = <&devctrl 0x5c>;
			resets = <&pscrst 7>;
			interrupt-parent = <&kirq0>;
			interrupts = <7 15>;
			interrupt-names = "vring", "exception";
			kick-gpios = <&dspgpio7 27 0>;
			status = "disabled";
		};

		mdio: mdio@2090300 {
			compatible = "ti,keystone_mdio", "ti,davinci_mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x02090300 0x100>;
			status = "disabled";
			clocks = <&clkcpgmac>;
			clock-names = "fck";
			bus_freq = <2500000>;
		};
		/include/ "keystone-k2hk-netcp.dtsi"
};