code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for SPEAr310 Evaluation Baord
 *
 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
 */

/dts-v1/;
/include/ "spear310.dtsi"

/ {
	model = "ST SPEAr310 Evaluation Board";
	compatible = "st,spear310-evb", "st,spear310";
	#address-cells = <1>;
	#size-cells = <1>;

	memory {
		reg = <0 0x40000000>;
	};

	ahb {
		pinmux@b4000000 {
			pinctrl-names = "default";
			pinctrl-0 = <&state_default>;

			state_default: pinmux {
				gpio0 {
					st,pins = "gpio0_pin0_grp",
						"gpio0_pin1_grp",
						"gpio0_pin2_grp",
						"gpio0_pin3_grp",
						"gpio0_pin4_grp",
						"gpio0_pin5_grp";
					st,function = "gpio0";
				};
				i2c0 {
					st,pins = "i2c0_grp";
					st,function = "i2c0";
				};
				mii0 {
					st,pins = "mii0_grp";
					st,function = "mii0";
				};
				ssp0 {
					st,pins = "ssp0_grp";
					st,function = "ssp0";
				};
				uart0 {
					st,pins = "uart0_grp";
					st,function = "uart0";
				};
				emi {
					st,pins = "emi_cs_0_to_5_grp";
					st,function = "emi";
				};
				fsmc {
					st,pins = "fsmc_grp";
					st,function = "fsmc";
				};
				uart1 {
					st,pins = "uart1_grp";
					st,function = "uart1";
				};
				uart2 {
					st,pins = "uart2_grp";
					st,function = "uart2";
				};
				uart3 {
					st,pins = "uart3_grp";
					st,function = "uart3";
				};
				uart4 {
					st,pins = "uart4_grp";
					st,function = "uart4";
				};
				uart5 {
					st,pins = "uart5_grp";
					st,function = "uart5";
				};
			};
		};

		dma@fc400000 {
			status = "okay";
		};

		fsmc: flash@44000000 {
			status = "okay";
		};

		gmac: eth@e0800000 {
			status = "okay";
		};

		smi: flash@fc000000 {
			status = "okay";
			clock-rate = <50000000>;

			flash@f8000000 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xf8000000 0x800000>;
				st,smi-fast-mode;

				partition@0 {
					label = "xloader";
					reg = <0x0 0x10000>;
				};
				partition@10000 {
					label = "u-boot";
					reg = <0x10000 0x50000>;
				};
				partition@60000 {
					label = "environment";
					reg = <0x60000 0x10000>;
				};
				partition@70000 {
					label = "dtb";
					reg = <0x70000 0x10000>;
				};
				partition@80000 {
					label = "linux";
					reg = <0x80000 0x310000>;
				};
				partition@390000 {
					label = "rootfs";
					reg = <0x390000 0x0>;
				};
			};
		};

		spi0: spi@d0100000 {
			status = "okay";
		};

		ehci@e1800000 {
			status = "okay";
		};

		ohci@e1900000 {
			status = "okay";
		};

		ohci@e2100000 {
			status = "okay";
		};

		apb {
			gpio0: gpio@fc980000 {
			       status = "okay";
			};

			i2c0: i2c@d0180000 {
			       status = "okay";
			};

			rtc@fc900000 {
			       status = "okay";
			};

			serial@d0000000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			serial@b2000000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			serial@b2080000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			serial@b2100000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			serial@b2180000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			serial@b2200000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			wdt@fc880000 {
			       status = "okay";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for SPEAr310 SoC
 *
 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
 */

/include/ "spear3xx.dtsi"

/ {
	ahb {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0x40000000 0x40000000 0x10000000
			  0xb0000000 0xb0000000 0x10000000
			  0xd0000000 0xd0000000 0x30000000>;

		pinmux: pinmux@b4000000 {
			compatible = "st,spear310-pinmux";
			reg = <0xb4000000 0x1000>;
			#gpio-range-cells = <3>;
		};

		fsmc: flash@44000000 {
			compatible = "st,spear600-fsmc-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x44000000 0x1000	/* FSMC Register */
			       0x40000000 0x0010	/* NAND Base DATA */
			       0x40020000 0x0010	/* NAND Base ADDR */
			       0x40010000 0x0010>;	/* NAND Base CMD */
			reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
			status = "disabled";
		};

		shirq: interrupt-controller@0xb4000000 {
			compatible = "st,spear310-shirq";
			reg = <0xb4000000 0x1000>;
			interrupts = <28 29 30 1>;
			#interrupt-cells = <1>;
			interrupt-controller;
		};

		apb {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0xb0000000 0xb0000000 0x10000000
				  0xd0000000 0xd0000000 0x30000000>;

			serial@b2000000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0xb2000000 0x1000>;
				interrupts = <8>;
				interrupt-parent = <&shirq>;
				status = "disabled";
			};

			serial@b2080000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0xb2080000 0x1000>;
				interrupts = <9>;
				interrupt-parent = <&shirq>;
				status = "disabled";
			};

			serial@b2100000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0xb2100000 0x1000>;
				interrupts = <10>;
				interrupt-parent = <&shirq>;
				status = "disabled";
			};

			serial@b2180000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0xb2180000 0x1000>;
				interrupts = <11>;
				interrupt-parent = <&shirq>;
				status = "disabled";
			};

			serial@b2200000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0xb2200000 0x1000>;
				interrupts = <12>;
				interrupt-parent = <&shirq>;
				status = "disabled";
			};

			gpiopinctrl: gpio@b4000000 {
				compatible = "st,spear-plgpio";
				reg = <0xb4000000 0x1000>;
				regmap = <&pinmux>;
				#interrupt-cells = <1>;
				interrupt-controller;
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinmux 0 0 102>;
				status = "disabled";

				st-plgpio,ngpio = <102>;
				st-plgpio,enb-reg = <0x10>;
				st-plgpio,wdata-reg = <0x20>;
				st-plgpio,dir-reg = <0x30>;
				st-plgpio,ie-reg = <0x50>;
				st-plgpio,rdata-reg = <0x40>;
				st-plgpio,mis-reg = <0x60>;
			};
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for SPEAr320 Evaluation Baord
 *
 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
 */

/dts-v1/;
/include/ "spear320.dtsi"

/ {
	model = "ST SPEAr320 Evaluation Board";
	compatible = "st,spear320-evb", "st,spear320";
	#address-cells = <1>;
	#size-cells = <1>;

	memory {
		reg = <0 0x40000000>;
	};

	ahb {
		pinmux@b3000000 {
			st,pinmux-mode = <4>;
			pinctrl-names = "default";
			pinctrl-0 = <&state_default>;

			state_default: pinmux {
				i2c0 {
					st,pins = "i2c0_grp";
					st,function = "i2c0";
				};
				mii0 {
					st,pins = "mii0_grp";
					st,function = "mii0";
				};
				ssp0 {
					st,pins = "ssp0_grp";
					st,function = "ssp0";
				};
				uart0 {
					st,pins = "uart0_grp";
					st,function = "uart0";
				};
				sdhci {
					st,pins = "sdhci_cd_51_grp";
					st,function = "sdhci";
				};
				i2s {
					st,pins = "i2s_grp";
					st,function = "i2s";
				};
				uart1 {
					st,pins = "uart1_grp";
					st,function = "uart1";
				};
				uart2 {
					st,pins = "uart2_grp";
					st,function = "uart2";
				};
				can0 {
					st,pins = "can0_grp";
					st,function = "can0";
				};
				can1 {
					st,pins = "can1_grp";
					st,function = "can1";
				};
				mii2 {
					st,pins = "mii2_grp";
					st,function = "mii2";
				};
				pwm0_1 {
					st,pins = "pwm0_1_pin_37_38_grp";
					st,function = "pwm0_1";
				};
			};
		};

		dma@fc400000 {
			status = "okay";
		};

		fsmc: flash@4c000000 {
			status = "okay";
		};

		gmac: eth@e0800000 {
			status = "okay";
		};

		sdhci@70000000 {
			power-gpio = <&gpiopinctrl 61 1>;
			status = "okay";
		};

		smi: flash@fc000000 {
			status = "okay";
			clock-rate = <50000000>;

			flash@f8000000 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xf8000000 0x800000>;
				st,smi-fast-mode;

				partition@0 {
					label = "xloader";
					reg = <0x0 0x10000>;
				};
				partition@10000 {
					label = "u-boot";
					reg = <0x10000 0x50000>;
				};
				partition@60000 {
					label = "environment";
					reg = <0x60000 0x10000>;
				};
				partition@70000 {
					label = "dtb";
					reg = <0x70000 0x10000>;
				};
				partition@80000 {
					label = "linux";
					reg = <0x80000 0x310000>;
				};
				partition@390000 {
					label = "rootfs";
					reg = <0x390000 0x0>;
				};
			};
		};

		spi0: spi@d0100000 {
			status = "okay";
		};

		spi1: spi@a5000000 {
			status = "okay";
		};

		spi2: spi@a6000000 {
			status = "okay";
		};

		ehci@e1800000 {
			status = "okay";
		};

		ohci@e1900000 {
			status = "okay";
		};

		ohci@e2100000 {
			status = "okay";
		};

		apb {
			gpio0: gpio@fc980000 {
			       status = "okay";
			};

			gpio@b3000000 {
			       status = "okay";
			};

			i2c0: i2c@d0180000 {
			       status = "okay";
			};

			i2c1: i2c@a7000000 {
			       status = "okay";
			};

			rtc@fc900000 {
			       status = "okay";
			};

			serial@d0000000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			serial@a3000000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			serial@a4000000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			wdt@fc880000 {
			       status = "okay";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for SPEAr320 Evaluation Baord
 *
 * Copyright 2012 Shiraz Hashim <shiraz.linux.kernel@gmail.com>
 */

/dts-v1/;
/include/ "spear320.dtsi"

/ {
	model = "ST SPEAr320 HMI Board";
	compatible = "st,spear320-hmi", "st,spear320";
	#address-cells = <1>;
	#size-cells = <1>;

	memory {
		reg = <0 0x40000000>;
	};

	ahb {
		pinmux@b3000000 {
			st,pinmux-mode = <4>;
			pinctrl-names = "default";
			pinctrl-0 = <&state_default>;

			state_default: pinmux {
				i2c0 {
					st,pins = "i2c0_grp";
					st,function = "i2c0";
				};
				ssp0 {
					st,pins = "ssp0_grp";
					st,function = "ssp0";
				};
				uart0 {
					st,pins = "uart0_grp";
					st,function = "uart0";
				};
				clcd {
					st,pins = "clcd_grp";
					st,function = "clcd";
				};
				fsmc {
					st,pins = "fsmc_8bit_grp";
					st,function = "fsmc";
				};
				sdhci {
					st,pins = "sdhci_cd_12_grp";
					st,function = "sdhci";
				};
				i2s {
					st,pins = "i2s_grp";
					st,function = "i2s";
				};
				uart1 {
					st,pins = "uart1_grp";
					st,function = "uart1";
				};
				uart2 {
					st,pins = "uart2_grp";
					st,function = "uart2";
				};
				can0 {
					st,pins = "can0_grp";
					st,function = "can0";
				};
				can1 {
					st,pins = "can1_grp";
					st,function = "can1";
				};
				mii0_1 {
					st,pins = "rmii0_1_grp";
					st,function = "mii0_1";
				};
				pwm0_1 {
					st,pins = "pwm0_1_pin_37_38_grp";
					st,function = "pwm0_1";
				};
				pwm2 {
					st,pins = "pwm2_pin_34_grp";
					st,function = "pwm2";
				};
			};
		};

		clcd@90000000 {
			status = "okay";
		};

		dma@fc400000 {
			status = "okay";
		};

		ehci@e1800000 {
			status = "okay";
		};

		fsmc: flash@4c000000 {
			status = "okay";

			partition@0 {
				label = "xloader";
				reg = <0x0 0x80000>;
			};
			partition@80000 {
				label = "u-boot";
				reg = <0x80000 0x140000>;
			};
			partition@1C0000 {
				label = "environment";
				reg = <0x1C0000 0x40000>;
			};
			partition@200000 {
				label = "dtb";
				reg = <0x200000 0x40000>;
			};
			partition@240000 {
				label = "linux";
				reg = <0x240000 0xC00000>;
			};
			partition@E40000 {
				label = "rootfs";
				reg = <0xE40000 0x0>;
			};
		};

		gpio_keys {
			compatible = "gpio-keys";
			#address-cells = <1>;
			#size-cells = <0>;

			button@1 {
				label = "user button 1";
				linux,code = <0x100>;
				gpios = <&stmpegpio 3 0x4>;
				debounce-interval = <20>;
				wakeup-source;
			};

			button@2 {
				label = "user button 2";
				linux,code = <0x200>;
				gpios = <&stmpegpio 2 0x4>;
				debounce-interval = <20>;
				wakeup-source;
			};
		};

		ohci@e1900000 {
			status = "okay";
		};

		ohci@e2100000 {
			status = "okay";
		};

		pwm: pwm@a8000000 {
			status = "okay";
		};

		sdhci@70000000 {
			power-gpio = <&gpiopinctrl 50 1>;
			power_always_enb;
			status = "okay";
		};

		smi: flash@fc000000 {
			status = "okay";
			clock-rate = <50000000>;

			flash@f8000000 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xf8000000 0x800000>;
				st,smi-fast-mode;

				partition@0 {
					label = "xloader";
					reg = <0x0 0x10000>;
				};
				partition@10000 {
					label = "u-boot";
					reg = <0x10000 0x50000>;
				};
				partition@60000 {
					label = "environment";
					reg = <0x60000 0x10000>;
				};
				partition@70000 {
					label = "dtb";
					reg = <0x70000 0x10000>;
				};
				partition@80000 {
					label = "linux";
					reg = <0x80000 0x310000>;
				};
				partition@390000 {
					label = "rootfs";
					reg = <0x390000 0x0>;
				};
			};
		};

		spi0: spi@d0100000 {
			status = "okay";
		};

		spi1: spi@a5000000 {
			status = "okay";
		};

		spi2: spi@a6000000 {
			status = "okay";
		};

		usbd@e1100000 {
			status = "okay";
		};

		apb {
			gpio0: gpio@fc980000 {
			       status = "okay";
			};

			gpio@b3000000 {
				status = "okay";
			};

			i2c0: i2c@d0180000 {
				status = "okay";

				stmpe811@41 {
					compatible = "st,stmpe811";
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0x41>;
					irq-gpios = <&gpiopinctrl 29 0x4>;
					id = <0>;
					blocks = <0x5>;
					irq-trigger = <0x1>;

					stmpegpio: stmpe-gpio {
						compatible = "stmpe,gpio";
						reg = <0>;
						gpio-controller;
						#gpio-cells = <2>;
						gpio,norequest-mask = <0xF3>;
					};

					stmpe610-ts {
						compatible = "stmpe,ts";
						reg = <0>;
						ts,sample-time = <4>;
						ts,mod-12b = <1>;
						ts,ref-sel = <0>;
						ts,adc-freq = <1>;
						ts,ave-ctrl = <1>;
						ts,touch-det-delay = <3>;
						ts,settling = <4>;
						ts,fraction-z = <7>;
						ts,i-drive = <1>;
					};
				};
			};

			i2c1: i2c@a7000000 {
			       status = "okay";
			};

			rtc@fc900000 {
			       status = "okay";
			};

			serial@d0000000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			serial@a3000000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			serial@a4000000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			wdt@fc880000 {
			       status = "okay";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for SPEAr320 SoC
 *
 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
 */

/include/ "spear3xx.dtsi"

/ {
	ahb {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0x40000000 0x40000000 0x80000000
			  0xd0000000 0xd0000000 0x30000000>;

		pinmux: pinmux@b3000000 {
			compatible = "st,spear320-pinmux";
			reg = <0xb3000000 0x1000>;
			#gpio-range-cells = <3>;
		};

		clcd@90000000 {
			compatible = "arm,pl110", "arm,primecell";
			reg = <0x90000000 0x1000>;
			interrupts = <8>;
			interrupt-parent = <&shirq>;
			status = "disabled";
		};

		fsmc: flash@4c000000 {
			compatible = "st,spear600-fsmc-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x4c000000 0x1000	/* FSMC Register */
			       0x50000000 0x0010	/* NAND Base DATA */
			       0x50020000 0x0010	/* NAND Base ADDR */
			       0x50010000 0x0010>;	/* NAND Base CMD */
			reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
			status = "disabled";
		};

		sdhci@70000000 {
			compatible = "st,sdhci-spear";
			reg = <0x70000000 0x100>;
			interrupts = <10>;
			interrupt-parent = <&shirq>;
			status = "disabled";
		};

		shirq: interrupt-controller@0xb3000000 {
			compatible = "st,spear320-shirq";
			reg = <0xb3000000 0x1000>;
			interrupts = <30 28 29 1>;
			#interrupt-cells = <1>;
			interrupt-controller;
		};

		spi1: spi@a5000000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0xa5000000 0x1000>;
			interrupts = <15>;
			interrupt-parent = <&shirq>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@a6000000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0xa6000000 0x1000>;
			interrupts = <16>;
			interrupt-parent = <&shirq>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		pwm: pwm@a8000000 {
			compatible = "st,spear-pwm";
			reg = <0xa8000000 0x1000>;
			#pwm-cells = <2>;
			status = "disabled";
                };

		apb {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0xa0000000 0xa0000000 0x20000000
				  0xd0000000 0xd0000000 0x30000000>;

			i2c1: i2c@a7000000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,designware-i2c";
				reg = <0xa7000000 0x1000>;
				interrupts = <21>;
				interrupt-parent = <&shirq>;
				status = "disabled";
			};

			serial@a3000000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0xa3000000 0x1000>;
				interrupts = <13>;
				interrupt-parent = <&shirq>;
				status = "disabled";
			};

			serial@a4000000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0xa4000000 0x1000>;
				interrupts = <14>;
				interrupt-parent = <&shirq>;
				status = "disabled";
			};

			gpiopinctrl: gpio@b3000000 {
				compatible = "st,spear-plgpio";
				reg = <0xb3000000 0x1000>;
				regmap = <&pinmux>;
				#interrupt-cells = <1>;
				interrupt-controller;
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinmux 0 0 102>;
				status = "disabled";

				st-plgpio,ngpio = <102>;
				st-plgpio,enb-reg = <0x24>;
				st-plgpio,wdata-reg = <0x34>;
				st-plgpio,dir-reg = <0x44>;
				st-plgpio,ie-reg = <0x64>;
				st-plgpio,rdata-reg = <0x54>;
				st-plgpio,mis-reg = <0x84>;
				st-plgpio,eit-reg = <0x94>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for SPEAr320s SoC
 *
 * Copyright 2021 Herve Codina <herve.codina@bootlin.com>
 */

/include/ "spear320.dtsi"

/ {
	ahb {
		apb {
			gpiopinctrl: gpio@b3000000 {
				/*
				 * The "RM0321 SPEAr320s address and map
				 * registers" document mentions interrupt 6
				 * (NPGIO_INTR) for the PL_GPIO interrupt.
				 */
				interrupts = <6>;
				interrupt-parent = <&shirq>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for all SPEAr3xx SoCs
 *
 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&vic>;

	cpus {
		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			compatible = "arm,arm926ej-s";
			device_type = "cpu";
		};
	};

	memory {
		device_type = "memory";
		reg = <0 0x40000000>;
	};

	ahb {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0xd0000000 0xd0000000 0x30000000>;

		vic: interrupt-controller@f1100000 {
			compatible = "arm,pl190-vic";
			interrupt-controller;
			reg = <0xf1100000 0x1000>;
			#interrupt-cells = <1>;
		};

		dma@fc400000 {
			compatible = "arm,pl080", "arm,primecell";
			reg = <0xfc400000 0x1000>;
			interrupt-parent = <&vic>;
			interrupts = <8>;
			status = "disabled";
		};

		gmac: eth@e0800000 {
			compatible = "snps,dwmac-3.40a";
			reg = <0xe0800000 0x8000>;
			interrupts = <23 22>;
			interrupt-names = "macirq", "eth_wake_irq";
			phy-mode = "mii";
			status = "disabled";
		};

		smi: flash@fc000000 {
			compatible = "st,spear600-smi";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0xfc000000 0x1000>;
			interrupts = <9>;
			status = "disabled";
		};

		spi0: spi@d0100000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0xd0100000 0x1000>;
			interrupts = <20>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ehci@e1800000 {
			compatible = "st,spear600-ehci", "usb-ehci";
			reg = <0xe1800000 0x1000>;
			interrupts = <26>;
			status = "disabled";
		};

		ohci@e1900000 {
			compatible = "st,spear600-ohci", "usb-ohci";
			reg = <0xe1900000 0x1000>;
			interrupts = <25>;
			status = "disabled";
		};

		ohci@e2100000 {
			compatible = "st,spear600-ohci", "usb-ohci";
			reg = <0xe2100000 0x1000>;
			interrupts = <27>;
			status = "disabled";
		};

		apb {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0xd0000000 0xd0000000 0x30000000>;

			gpio0: gpio@fc980000 {
				compatible = "arm,pl061", "arm,primecell";
				reg = <0xfc980000 0x1000>;
				interrupts = <11>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				status = "disabled";
			};

			i2c0: i2c@d0180000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,designware-i2c";
				reg = <0xd0180000 0x1000>;
				interrupts = <21>;
				status = "disabled";
			};

			rtc@fc900000 {
				compatible = "st,spear600-rtc";
				reg = <0xfc900000 0x1000>;
				interrupts = <10>;
				status = "disabled";
			};

			serial@d0000000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0xd0000000 0x1000>;
				interrupts = <19>;
				status = "disabled";
			};

			wdt@fc880000 {
				compatible = "arm,sp805", "arm,primecell";
				reg = <0xfc880000 0x1000>;
				interrupts = <12>;
				status = "disabled";
			};

			timer@f0000000 {
				compatible = "st,spear-timer";
				reg = <0xf0000000 0x400>;
				interrupts = <2>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Stefan Roese <sr@denx.de>
 */

/dts-v1/;
/include/ "spear600.dtsi"

/ {
	model = "ST SPEAr600 Evaluation Board";
	compatible = "st,spear600-evb", "st,spear600";
	#address-cells = <1>;
	#size-cells = <1>;

	memory {
		device_type = "memory";
		reg = <0 0x10000000>;
	};
};

&clcd {
	status = "okay";
};

&dmac {
	status = "okay";
};

&ehci_usb0 {
	status = "okay";
};

&ehci_usb1 {
	status = "okay";
};

&gmac {
	phy-mode = "gmii";
	status = "okay";
};

&ohci_usb0 {
	status = "okay";
};

&ohci_usb1 {
	status = "okay";
};

&smi {
	status = "okay";
	clock-rate = <50000000>;

	flash@f8000000 {
		reg = <0xf8000000 0x800000>;
		st,smi-fast-mode;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "xloader";
				reg = <0x0 0x10000>;
			};
			partition@10000 {
				label = "u-boot";
				reg = <0x10000 0x50000>;
			};
			partition@60000 {
				label = "environment";
				reg = <0x60000 0x10000>;
			};
			partition@70000 {
				label = "dtb";
				reg = <0x70000 0x10000>;
			};
			partition@80000 {
				label = "linux";
				reg = <0x80000 0x310000>;
			};
			partition@390000 {
				label = "rootfs";
				reg = <0x390000 0x0>;
			};
		};
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&rtc {
	status = "okay";
};

&i2c {
	clock-frequency = <400000>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Stefan Roese <sr@denx.de>
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "st,spear600";

	cpus {
		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			compatible = "arm,arm926ej-s";
			device_type = "cpu";
		};
	};

	memory {
		device_type = "memory";
		reg = <0 0x40000000>;
	};

	ahb {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0xd0000000 0xd0000000 0x30000000>;

		vic0: interrupt-controller@f1100000 {
			compatible = "arm,pl190-vic";
			interrupt-controller;
			reg = <0xf1100000 0x1000>;
			#interrupt-cells = <1>;
		};

		vic1: interrupt-controller@f1000000 {
			compatible = "arm,pl190-vic";
			interrupt-controller;
			reg = <0xf1000000 0x1000>;
			#interrupt-cells = <1>;
		};

		clcd: clcd@fc200000 {
			compatible = "arm,pl110", "arm,primecell";
			reg = <0xfc200000 0x1000>;
			interrupt-parent = <&vic1>;
			interrupts = <13>;
			status = "disabled";
		};

		dmac: dma@fc400000 {
			compatible = "arm,pl080", "arm,primecell";
			reg = <0xfc400000 0x1000>;
			interrupt-parent = <&vic1>;
			interrupts = <10>;
			status = "disabled";
		};

		gmac: ethernet@e0800000 {
			compatible = "st,spear600-gmac";
			reg = <0xe0800000 0x8000>;
			interrupt-parent = <&vic1>;
			interrupts = <24 23>;
			interrupt-names = "macirq", "eth_wake_irq";
			phy-mode = "gmii";
			status = "disabled";
		};

		fsmc: flash@d1800000 {
			compatible = "st,spear600-fsmc-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0xd1800000 0x1000	/* FSMC Register */
			       0xd2000000 0x0010	/* NAND Base DATA */
			       0xd2020000 0x0010	/* NAND Base ADDR */
			       0xd2010000 0x0010>;	/* NAND Base CMD */
			reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
			status = "disabled";
		};

		smi: flash@fc000000 {
			compatible = "st,spear600-smi";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0xfc000000 0x1000>;
			interrupt-parent = <&vic1>;
			interrupts = <12>;
			status = "disabled";
		};

		ehci_usb0: ehci@e1800000 {
			compatible = "st,spear600-ehci", "usb-ehci";
			reg = <0xe1800000 0x1000>;
			interrupt-parent = <&vic1>;
			interrupts = <27>;
			status = "disabled";
		};

		ehci_usb1: ehci@e2000000 {
			compatible = "st,spear600-ehci", "usb-ehci";
			reg = <0xe2000000 0x1000>;
			interrupt-parent = <&vic1>;
			interrupts = <29>;
			status = "disabled";
		};

		ohci_usb0: ohci@e1900000 {
			compatible = "st,spear600-ohci", "usb-ohci";
			reg = <0xe1900000 0x1000>;
			interrupt-parent = <&vic1>;
			interrupts = <26>;
			status = "disabled";
		};

		ohci_usb1: ohci@e2100000 {
			compatible = "st,spear600-ohci", "usb-ohci";
			reg = <0xe2100000 0x1000>;
			interrupt-parent = <&vic1>;
			interrupts = <28>;
			status = "disabled";
		};

		apb {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0xd0000000 0xd0000000 0x30000000>;

			uart0: serial@d0000000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0xd0000000 0x1000>;
				interrupt-parent = <&vic0>;
				interrupts = <24>;
				status = "disabled";
			};

			uart1: serial@d0080000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0xd0080000 0x1000>;
				interrupt-parent = <&vic0>;
				interrupts = <25>;
				status = "disabled";
			};

			/* local/cpu GPIO */
			gpio0: gpio@f0100000 {
				#gpio-cells = <2>;
				compatible = "arm,pl061", "arm,primecell";
				gpio-controller;
				reg = <0xf0100000 0x1000>;
				interrupt-parent = <&vic0>;
				interrupts = <18>;
			};

			/* basic GPIO */
			gpio1: gpio@fc980000 {
				#gpio-cells = <2>;
				compatible = "arm,pl061", "arm,primecell";
				gpio-controller;
				reg = <0xfc980000 0x1000>;
				interrupt-parent = <&vic1>;
				interrupts = <19>;
			};

			/* appl GPIO */
			gpio2: gpio@d8100000 {
				#gpio-cells = <2>;
				compatible = "arm,pl061", "arm,primecell";
				gpio-controller;
				reg = <0xd8100000 0x1000>;
				interrupt-parent = <&vic1>;
				interrupts = <4>;
			};

			i2c: i2c@d0200000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,designware-i2c";
				reg = <0xd0200000 0x1000>;
				interrupt-parent = <&vic0>;
				interrupts = <28>;
				status = "disabled";
			};

			rtc: rtc@fc900000 {
				compatible = "st,spear600-rtc";
				reg = <0xfc900000 0x1000>;
				interrupt-parent = <&vic0>;
				interrupts = <10>;
				status = "disabled";
			};

			timer@f0000000 {
				compatible = "st,spear-timer";
				reg = <0xf0000000 0x400>;
				interrupt-parent = <&vic0>;
				interrupts = <16>;
			};

			adc: adc@d820b000 {
				compatible = "st,spear600-adc";
				reg = <0xd820b000 0x1000>;
				interrupt-parent = <&vic1>;
				interrupts = <6>;
				status = "disabled";
			};

			ssp1: spi@d0100000 {
				compatible = "arm,pl022", "arm,primecell";
				reg = <0xd0100000 0x1000>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupt-parent = <&vic0>;
				interrupts = <26>;
				status = "disabled";
			};

			ssp2: spi@d0180000 {
				compatible = "arm,pl022", "arm,primecell";
				reg = <0xd0180000 0x1000>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupt-parent = <&vic0>;
				interrupts = <27>;
				status = "disabled";
			};

			ssp3: spi@d8180000 {
				compatible = "arm,pl022", "arm,primecell";
				reg = <0xd8180000 0x1000>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupt-parent = <&vic1>;
				interrupts = <5>;
				status = "disabled";
			};
		};
	};
};


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ST_PINCFG_H_
#define _ST_PINCFG_H_

/* Alternate functions */
#define ALT1	1
#define ALT2	2
#define ALT3	3
#define ALT4	4
#define ALT5	5
#define ALT6	6
#define ALT7	7

/* Output enable */
#define OE			(1 << 27)
/* Pull Up */
#define PU			(1 << 26)
/* Open Drain */
#define OD			(1 << 25)
#define RT			(1 << 23)
#define INVERTCLK		(1 << 22)
#define CLKNOTDATA		(1 << 21)
#define DOUBLE_EDGE		(1 << 20)
#define CLK_A			(0 << 18)
#define CLK_B			(1 << 18)
#define CLK_C			(2 << 18)
#define CLK_D			(3 << 18)

/* User-frendly defines for Pin Direction */
		/* oe = 0, pu = 0, od = 0 */
#define IN			(0)
		/* oe = 0, pu = 1, od = 0 */
#define IN_PU			(PU)
		/* oe = 1, pu = 0, od = 0 */
#define OUT			(OE)
		/* oe = 1, pu = 0, od = 1 */
#define BIDIR			(OE | OD)
		/* oe = 1, pu = 1, od = 1 */
#define BIDIR_PU		(OE | PU | OD)

/* RETIME_TYPE */
/*
 * B Mode
 * Bypass retime with optional delay parameter
 */
#define BYPASS		(0)
/*
 * R0, R1, R0D, R1D modes
 * single-edge data non inverted clock, retime data with clk
 */
#define SE_NICLK_IO	(RT)
/*
 * RIV0, RIV1, RIV0D, RIV1D modes
 * single-edge data inverted clock, retime data with clk
 */
#define SE_ICLK_IO	(RT | INVERTCLK)
/*
 * R0E, R1E, R0ED, R1ED modes
 * double-edge data, retime data with clk
 */
#define DE_IO		(RT | DOUBLE_EDGE)
/*
 * CIV0, CIV1 modes with inverted clock
 * Retiming the clk pins will park clock & reduce the noise within the core.
 */
#define ICLK		(RT | CLKNOTDATA | INVERTCLK)
/*
 * CLK0, CLK1 modes with non-inverted clock
 * Retiming the clk pins will park clock & reduce the noise within the core.
 */
#define NICLK		(RT | CLKNOTDATA)
#endif /* _ST_PINCFG_H_ */


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Linaro Ltd
 */

#include <dt-bindings/clock/ste-ab8500.h>

/ {
	/* Essential housekeeping hardware monitors */
	iio-hwmon {
		compatible = "iio-hwmon";
		io-channels = <&gpadc 0x02>, /* Battery temperature */
			    <&gpadc 0x03>, /* Main charger voltage */
			    <&gpadc 0x08>, /* Main battery voltage */
			    <&gpadc 0x09>, /* VBUS */
			    <&gpadc 0x0a>, /* Main charger current */
			    <&gpadc 0x0b>, /* USB charger current */
			    <&gpadc 0x0c>, /* Backup battery voltage */
			    <&gpadc 0x0d>, /* Die temperature */
			    <&gpadc 0x12>; /* Crystal temperature */
	};

	soc {
		prcmu@80157000 {
			ab8500 {
				compatible = "stericsson,ab8500";
				interrupt-parent = <&intc>;
				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#address-cells = <1>;
				#size-cells = <0>;

				ab8500_clock: clock-controller {
					compatible = "stericsson,ab8500-clk";
					#clock-cells = <1>;
				};

				ab8500_gpio: gpio {
					compatible = "stericsson,ab8500-gpio";
					gpio-controller;
					#gpio-cells = <2>;
				};

				rtc {
					compatible = "stericsson,ab8500-rtc";
					interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
						     <18 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "60S", "ALARM";
				};

				gpadc: adc {
					compatible = "stericsson,ab8500-gpadc";
					interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
						     <39 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "HW_CONV_END", "SW_CONV_END";
					vddadc-supply = <&ab8500_ldo_tvout_reg>;
					#address-cells = <1>;
					#size-cells = <0>;
					#io-channel-cells = <1>;

					/* GPADC channels */
					bat_ctrl: channel@1 {
						reg = <0x01>;
					};
					btemp_ball: channel@2 {
						reg = <0x02>;
					};
					main_charger_v: channel@3 {
						reg = <0x03>;
					};
					acc_detect1: channel@4 {
						reg = <0x04>;
					};
					acc_detect2: channel@5 {
						reg = <0x05>;
					};
					adc_aux1: channel@6 {
						reg = <0x06>;
					};
					adc_aux2: channel@7 {
						reg = <0x07>;
					};
					main_batt_v: channel@8 {
						reg = <0x08>;
					};
					vbus_v: channel@9 {
						reg = <0x09>;
					};
					main_charger_c: channel@a {
						reg = <0x0a>;
					};
					usb_charger_c: channel@b {
						reg = <0x0b>;
					};
					bk_bat_v: channel@c {
						reg = <0x0c>;
					};
					die_temp: channel@d {
						reg = <0x0d>;
					};
					usb_id: channel@e {
						reg = <0x0e>;
					};
					xtal_temp: channel@12 {
						reg = <0x12>;
					};
					vbat_true_meas: channel@13 {
						reg = <0x13>;
					};
					bat_ctrl_and_ibat: channel@1c {
						reg = <0x1c>;
					};
					vbat_meas_and_ibat: channel@1d {
						reg = <0x1d>;
					};
					vbat_true_meas_and_ibat: channel@1e {
						reg = <0x1e>;
					};
					bat_temp_and_ibat: channel@1f {
						reg = <0x1f>;
					};
				};

				thermal {
					compatible = "stericsson,abx500-temp";
					interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "ABX500_TEMP_WARM";
				};

				ab8500_fg {
					compatible = "stericsson,ab8500-fg";
					interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
						     <8 IRQ_TYPE_LEVEL_HIGH>,
						     <28 IRQ_TYPE_LEVEL_HIGH>,
						     <27 IRQ_TYPE_LEVEL_HIGH>,
						     <26 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "NCONV_ACCU",
							  "BATT_OVV",
							  "LOW_BAT_F",
							  "CC_INT_CALIB",
							  "CCEOC";
					monitored-battery = <&battery>;
					io-channels = <&gpadc 0x08>;
					io-channel-names = "main_bat_v";
				};

				ab8500_btemp {
					compatible = "stericsson,ab8500-btemp";
					interrupts = <20 IRQ_TYPE_LEVEL_HIGH>,
						     <80 IRQ_TYPE_LEVEL_HIGH>,
						     <83 IRQ_TYPE_LEVEL_HIGH>,
						     <81 IRQ_TYPE_LEVEL_HIGH>,
						     <82 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "BAT_CTRL_INDB",
							  "BTEMP_LOW",
							  "BTEMP_HIGH",
							  "BTEMP_LOW_MEDIUM",
							  "BTEMP_MEDIUM_HIGH";
					monitored-battery = <&battery>;
					io-channels = <&gpadc 0x02>,
						      <&gpadc 0x01>;
					io-channel-names = "btemp_ball",
							"bat_ctrl";
				};

				ab8500_charger {
					compatible = "stericsson,ab8500-charger";
					interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
						     <11 IRQ_TYPE_LEVEL_HIGH>,
						     <0 IRQ_TYPE_LEVEL_HIGH>,
						     <107 IRQ_TYPE_LEVEL_HIGH>,
						     <106 IRQ_TYPE_LEVEL_HIGH>,
						     <14 IRQ_TYPE_LEVEL_HIGH>,
						     <15 IRQ_TYPE_LEVEL_HIGH>,
						     <79 IRQ_TYPE_LEVEL_HIGH>,
						     <105 IRQ_TYPE_LEVEL_HIGH>,
						     <104 IRQ_TYPE_LEVEL_HIGH>,
						     <89 IRQ_TYPE_LEVEL_HIGH>,
						     <22 IRQ_TYPE_LEVEL_HIGH>,
						     <21 IRQ_TYPE_LEVEL_HIGH>,
						     <16 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "MAIN_CH_UNPLUG_DET",
							  "MAIN_CHARGE_PLUG_DET",
							  "MAIN_EXT_CH_NOT_OK",
							  "MAIN_CH_TH_PROT_R",
							  "MAIN_CH_TH_PROT_F",
							  "VBUS_DET_F",
							  "VBUS_DET_R",
							  "USB_LINK_STATUS",
							  "USB_CH_TH_PROT_R",
							  "USB_CH_TH_PROT_F",
							  "USB_CHARGER_NOT_OKR",
							  "VBUS_OVV",
							  "CH_WD_EXP",
							  "VBUS_CH_DROP_END";
					monitored-battery = <&battery>;
					vddadc-supply = <&ab8500_ldo_tvout_reg>;
					io-channels = <&gpadc 0x03>,
						      <&gpadc 0x0a>,
						      <&gpadc 0x09>,
						      <&gpadc 0x0b>;
					io-channel-names = "main_charger_v",
							"main_charger_c",
							"vbus_v",
							"usb_charger_c";
				};

				ab8500_chargalg {
					compatible = "stericsson,ab8500-chargalg";
					monitored-battery = <&battery>;
				};

				ab8500_usb: phy {
					compatible = "stericsson,ab8500-usb";
					interrupts = <90 IRQ_TYPE_LEVEL_HIGH>,
						     <96 IRQ_TYPE_LEVEL_HIGH>,
						     <14 IRQ_TYPE_LEVEL_HIGH>,
						     <15 IRQ_TYPE_LEVEL_HIGH>,
						     <79 IRQ_TYPE_LEVEL_HIGH>,
						     <74 IRQ_TYPE_LEVEL_HIGH>,
						     <75 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "ID_WAKEUP_R",
							  "ID_WAKEUP_F",
							  "VBUS_DET_F",
							  "VBUS_DET_R",
							  "USB_LINK_STATUS",
							  "USB_ADP_PROBE_PLUG",
							  "USB_ADP_PROBE_UNPLUG";
					vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
					v-ape-supply = <&db8500_vape_reg>;
					musb_1v8-supply = <&db8500_vsmps2_reg>;
					clocks = <&prcmu_clk PRCMU_SYSCLK>;
					clock-names = "sysclk";
					#phy-cells = <0>;
				};

				key {
					compatible = "stericsson,ab8500-poweron-key";
					interrupts = <6 IRQ_TYPE_LEVEL_HIGH>,
						     <7 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
				};

				ab8500-sysctrl {
					compatible = "stericsson,ab8500-sysctrl";
				};

				pwm@1 {
					compatible = "stericsson,ab8500-pwm";
					reg = <1>;
					clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
					clock-names = "intclk";
					#pwm-cells = <1>;
				};

				pwm@2 {
					compatible = "stericsson,ab8500-pwm";
					reg = <2>;
					clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
					clock-names = "intclk";
					#pwm-cells = <1>;
				};

				pwm@3 {
					compatible = "stericsson,ab8500-pwm";
					reg = <3>;
					clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
					clock-names = "intclk";
					#pwm-cells = <1>;
				};

				codec: codec {
					compatible = "stericsson,ab8500-codec";

					V-AUD-supply = <&ab8500_ldo_audio_reg>;
					V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
					V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
					V-DMIC-supply = <&ab8500_ldo_dmic_reg>;

					clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
					clock-names = "audioclk";

					stericsson,earpeice-cmv = <950>; /* Units in mV. */
				};

				ext_regulators: regulator-external {
					compatible = "stericsson,ab8500-ext-regulator";

					ab8500_ext1_reg: ab8500_ext1 {
						regulator-min-microvolt = <1800000>;
						regulator-max-microvolt = <1800000>;
						regulator-boot-on;
						regulator-always-on;
					};

					ab8500_ext2_reg: ab8500_ext2 {
						regulator-min-microvolt = <1360000>;
						regulator-max-microvolt = <1360000>;
						regulator-boot-on;
						regulator-always-on;
					};

					ab8500_ext3_reg: ab8500_ext3 {
						regulator-min-microvolt = <3400000>;
						regulator-max-microvolt = <3400000>;
						regulator-boot-on;
					};
				};

				regulator {
					compatible = "stericsson,ab8500-regulator";
					vin-supply = <&ab8500_ext3_reg>;

					// supplies to the display/camera
					ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
						regulator-min-microvolt = <2800000>;
						regulator-max-microvolt = <3300000>;
						regulator-boot-on;
						/* BUG: If turned off MMC will be affected. */
						regulator-always-on;
					};

					// supplies to the on-board eMMC
					ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
						regulator-min-microvolt = <1100000>;
						regulator-max-microvolt = <3300000>;
					};

					// supply for VAUX3; SDcard slots
					ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
						regulator-min-microvolt = <1100000>;
						regulator-max-microvolt = <3300000>;
					};

					// supply for v-intcore12; VINTCORE12 LDO
					ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
					};

					// supply for tvout; gpadc; TVOUT LDO
					ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
					};

					// supply for ab8500-vaudio; VAUDIO LDO
					ab8500_ldo_audio_reg: ab8500_ldo_audio {
					};

					// supply for v-anamic1 VAMIC1 LDO
					ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
					};

					// supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
					ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
					};

					// supply for v-dmic; VDMIC LDO
					ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
					};

					// supply for U8500 CSI/DSI; VANA LDO
					ab8500_ldo_ana_reg: ab8500_ldo_ana {
					};
				};
			};
		};

		sound {
			stericsson,audio-codec = <&codec>;
			clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
			clock-names = "sysclk", "ulpclk", "intclk";
		};

		mcde@a0350000 {
			vana-supply = <&ab8500_ldo_ana_reg>;

			dsi@a0351000 {
				vana-supply = <&ab8500_ldo_ana_reg>;
			};
			dsi@a0352000 {
				vana-supply = <&ab8500_ldo_ana_reg>;
			};
			dsi@a0353000 {
				vana-supply = <&ab8500_ldo_ana_reg>;
			};
		};

		usb_per5@a03e0000 {
			phys = <&ab8500_usb>;
			phy-names = "usb";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Linaro Ltd
 */

#include <dt-bindings/clock/ste-ab8500.h>

/ {
	/* Essential housekeeping hardware monitors */
	iio-hwmon {
		compatible = "iio-hwmon";
		io-channels = <&gpadc 0x02>, /* Battery temperature */
			      <&gpadc 0x08>, /* Main battery voltage */
			      <&gpadc 0x09>, /* VBUS */
			      <&gpadc 0x0b>, /* Charger current */
			      <&gpadc 0x0c>, /* Backup battery voltage */
			      <&gpadc 0x0d>; /* Die temperature */
	};

	soc {
		prcmu@80157000 {
			ab8505 {
				compatible = "stericsson,ab8505";
				interrupt-parent = <&intc>;
				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-controller;
				#interrupt-cells = <2>;
				#address-cells = <1>;
				#size-cells = <0>;

				ab8500_clock: clock-controller {
					compatible = "stericsson,ab8500-clk";
					#clock-cells = <1>;
				};

				ab8505_gpio: gpio {
					compatible = "stericsson,ab8505-gpio";
					gpio-controller;
					#gpio-cells = <2>;
				};

				rtc {
					compatible = "stericsson,ab8500-rtc";
					interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
						     <18 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "60S", "ALARM";
				};

				gpadc: adc {
					compatible = "stericsson,ab8500-gpadc";
					interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "SW_CONV_END";
					vddadc-supply = <&ab8500_ldo_adc_reg>;
					#address-cells = <1>;
					#size-cells = <0>;
					#io-channel-cells = <1>;

					/* GPADC channels */
					bat_ctrl: channel@1 {
						reg = <0x01>;
					};
					btemp_ball: channel@2 {
						reg = <0x02>;
					};
					acc_detect1: channel@4 {
						reg = <0x04>;
					};
					acc_detect2: channel@5 {
						reg = <0x05>;
					};
					adc_aux1: channel@6 {
						reg = <0x06>;
					};
					adc_aux2: channel@7 {
						reg = <0x07>;
					};
					main_batt_v: channel@8 {
						reg = <0x08>;
					};
					vbus_v: channel@9 {
						reg = <0x09>;
					};
					charger_c: channel@b {
						reg = <0x0b>;
					};
					bk_bat_v: channel@c {
						reg = <0x0c>;
					};
					die_temp: channel@d {
						reg = <0x0d>;
					};
					usb_id: channel@e {
						reg = <0x0e>;
					};
				};

				thermal {
					compatible = "stericsson,abx500-temp";
					interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "ABX500_TEMP_WARM";
				};

				ab8500_fg {
					compatible = "stericsson,ab8500-fg";
					interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
						     <8 IRQ_TYPE_LEVEL_HIGH>,
						     <28 IRQ_TYPE_LEVEL_HIGH>,
						     <27 IRQ_TYPE_LEVEL_HIGH>,
						     <26 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "NCONV_ACCU",
							  "BATT_OVV",
							  "LOW_BAT_F",
							  "CC_INT_CALIB",
							  "CCEOC";
					monitored-battery = <&battery>;
					io-channels = <&gpadc 0x08>;
					io-channel-names = "main_bat_v";
				};

				ab8500_btemp {
					compatible = "stericsson,ab8500-btemp";
					interrupts = <20 IRQ_TYPE_LEVEL_HIGH>,
						     <80 IRQ_TYPE_LEVEL_HIGH>,
						     <83 IRQ_TYPE_LEVEL_HIGH>,
						     <81 IRQ_TYPE_LEVEL_HIGH>,
						     <82 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "BAT_CTRL_INDB",
							  "BTEMP_LOW",
							  "BTEMP_HIGH",
							  "BTEMP_LOW_MEDIUM",
							  "BTEMP_MEDIUM_HIGH";
					monitored-battery = <&battery>;
					io-channels = <&gpadc 0x02>,
						      <&gpadc 0x01>;
					io-channel-names = "btemp_ball",
							  "bat_ctrl";
				};

				ab8500_charger {
					compatible = "stericsson,ab8500-charger";
					interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
						     <11 IRQ_TYPE_LEVEL_HIGH>,
						     <0 IRQ_TYPE_LEVEL_HIGH>,
						     <107 IRQ_TYPE_LEVEL_HIGH>,
						     <106 IRQ_TYPE_LEVEL_HIGH>,
						     <14 IRQ_TYPE_LEVEL_HIGH>,
						     <15 IRQ_TYPE_LEVEL_HIGH>,
						     <79 IRQ_TYPE_LEVEL_HIGH>,
						     <105 IRQ_TYPE_LEVEL_HIGH>,
						     <104 IRQ_TYPE_LEVEL_HIGH>,
						     <89 IRQ_TYPE_LEVEL_HIGH>,
						     <22 IRQ_TYPE_LEVEL_HIGH>,
						     <21 IRQ_TYPE_LEVEL_HIGH>,
						     <16 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "MAIN_CH_UNPLUG_DET",
							  "MAIN_CHARGE_PLUG_DET",
							  "MAIN_EXT_CH_NOT_OK",
							  "MAIN_CH_TH_PROT_R",
							  "MAIN_CH_TH_PROT_F",
							  "VBUS_DET_F",
							  "VBUS_DET_R",
							  "USB_LINK_STATUS",
							  "USB_CH_TH_PROT_R",
							  "USB_CH_TH_PROT_F",
							  "USB_CHARGER_NOT_OKR",
							  "VBUS_OVV",
							  "CH_WD_EXP",
							  "VBUS_CH_DROP_END";
					monitored-battery = <&battery>;
					vddadc-supply = <&ab8500_ldo_adc_reg>;
					io-channels = <&gpadc 0x09>,
						      <&gpadc 0x0b>;
					io-channel-names = "vbus_v",
							  "usb_charger_c";
				};

				ab8500_chargalg {
					compatible = "stericsson,ab8500-chargalg";
					monitored-battery = <&battery>;
				};

				ab8500_usb: phy {
					compatible = "stericsson,ab8500-usb";
					interrupts = <90 IRQ_TYPE_LEVEL_HIGH>,
						     <96 IRQ_TYPE_LEVEL_HIGH>,
						     <14 IRQ_TYPE_LEVEL_HIGH>,
						     <15 IRQ_TYPE_LEVEL_HIGH>,
						     <79 IRQ_TYPE_LEVEL_HIGH>,
						     <74 IRQ_TYPE_LEVEL_HIGH>,
						     <75 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "ID_WAKEUP_R",
							  "ID_WAKEUP_F",
							  "VBUS_DET_F",
							  "VBUS_DET_R",
							  "USB_LINK_STATUS",
							  "USB_ADP_PROBE_PLUG",
							  "USB_ADP_PROBE_UNPLUG";
					vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
					v-ape-supply = <&db8500_vape_reg>;
					musb_1v8-supply = <&db8500_vsmps2_reg>;
					clocks = <&prcmu_clk PRCMU_SYSCLK>;
					clock-names = "sysclk";
					#phy-cells = <0>;
				};

				key {
					compatible = "stericsson,ab8500-poweron-key";
					interrupts = <6 IRQ_TYPE_LEVEL_HIGH>,
						     <7 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
				};

				ab8500-sysctrl {
					compatible = "stericsson,ab8500-sysctrl";
				};

				pwm@1 {
					compatible = "stericsson,ab8500-pwm";
					reg = <1>;
					clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
					clock-names = "intclk";
					#pwm-cells = <1>;
				};

				codec: codec {
					compatible = "stericsson,ab8500-codec";

					V-AUD-supply = <&ab8500_ldo_audio_reg>;
					V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
					V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;

					clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
					clock-names = "audioclk";

					stericsson,earpeice-cmv = <950>; /* Units in mV. */
				};

				regulator {
					compatible = "stericsson,ab8505-regulator";

					ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
						regulator-min-microvolt = <2800000>;
						regulator-max-microvolt = <3300000>;
					};

					ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
						regulator-min-microvolt = <1100000>;
						regulator-max-microvolt = <3300000>;
					};

					ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
						regulator-min-microvolt = <1100000>;
						regulator-max-microvolt = <3300000>;
					};

					ab8500_ldo_aux4_reg: ab8500_ldo_aux4 {
						regulator-min-microvolt = <1100000>;
						regulator-max-microvolt = <3300000>;
					};

					ab8500_ldo_aux5_reg: ab8500_ldo_aux5 {
						regulator-min-microvolt = <1050000>;
						regulator-max-microvolt = <2790000>;
					};

					ab8500_ldo_aux6_reg: ab8500_ldo_aux6 {
						regulator-min-microvolt = <1050000>;
						regulator-max-microvolt = <2790000>;
					};

					// supply for v-intcore12; VINTCORE12 LDO
					ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
						regulator-min-microvolt = <1250000>;
						regulator-max-microvolt = <1350000>;
					};

					// supply for gpadc; ADC LDO
					ab8500_ldo_adc_reg: ab8500_ldo_adc {
					};

					// supply for ab8500-vaudio; VAUDIO LDO
					ab8500_ldo_audio_reg: ab8500_ldo_audio {
					};

					// supply for v-anamic1 VAMIC1 LDO
					ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
					};

					// supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
					ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
					};

					// supply for v-aux8; VAUX8 LDO
					ab8500_ldo_aux8_reg: ab8500_ldo_aux8 {
					};

					// supply for U8500 CSI/DSI; VANA LDO
					ab8500_ldo_ana_reg: ab8500_ldo_ana {
					};
				};
			};
		};

		sound {
			stericsson,audio-codec = <&codec>;
			clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
			clock-names = "sysclk", "ulpclk", "intclk";
		};

		mcde@a0350000 {
			vana-supply = <&ab8500_ldo_ana_reg>;

			dsi@a0351000 {
				vana-supply = <&ab8500_ldo_ana_reg>;
			};
			dsi@a0352000 {
				vana-supply = <&ab8500_ldo_ana_reg>;
			};
			dsi@a0353000 {
				vana-supply = <&ab8500_ldo_ana_reg>;
			};
		};

		usb_per5@a03e0000 {
			phys = <&ab8500_usb>;
			phy-names = "usb";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later

#include "ste-dbx5x0.dtsi"

/ {
	cpus {
		cpu@300 {
			operating-points = <998400 0
					    798720 0
					    399360 0
					    199680 0>;
		};
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* Modem trace memory */
		ram@6000000 {
			reg = <0x06000000 0x00f00000>;
			no-map;
		};

		/* Modem shared memory */
		ram@6f00000 {
			reg = <0x06f00000 0x00100000>;
			no-map;
		};

		/* Modem private memory */
		ram@7000000 {
			reg = <0x07000000 0x01000000>;
			no-map;
		};

		/*
		 * Initial Secure Software ISSW memory
		 *
		 * This is probably only used if the kernel tries
		 * to actually call into trustzone to run secure
		 * applications, which the mainline kernel probably
		 * will not do on this old chipset. But you can never
		 * be too careful, so reserve this memory anyway.
		 */
		ram@17f00000 {
			reg = <0x17f00000 0x00100000>;
			no-map;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later

#include "ste-dbx5x0.dtsi"

/ {
	cpus {
		cpu@300 {
			operating-points = <1152000 0
					    798720 0
					    399360 0
					    199680 0>;
		};
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* Modem trace memory */
		ram@6000000 {
			reg = <0x06000000 0x00f00000>;
			no-map;
		};

		/* Modem shared memory */
		ram@6f00000 {
			reg = <0x06f00000 0x00100000>;
			no-map;
		};

		/* Modem private memory */
		ram@7000000 {
			reg = <0x07000000 0x01000000>;
			no-map;
		};

		/*
		 * Initial Secure Software ISSW memory
		 *
		 * This is probably only used if the kernel tries
		 * to actually call into trustzone to run secure
		 * applications, which the mainline kernel probably
		 * will not do on this old chipset. But you can never
		 * be too careful, so reserve this memory anyway.
		 */
		ram@17f00000 {
			reg = <0x17f00000 0x00100000>;
			no-map;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later

#include "ste-dbx5x0.dtsi"

/ {
	cpus {
		cpu@300 {
			operating-points = <998400 0
					    798720 0
					    399360 0
					    199680 0>;
		};
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/*
		 * Initial Secure Software ISSW memory
		 *
		 * This is probably only used if the kernel tries
		 * to actually call into trustzone to run secure
		 * applications, which the mainline kernel probably
		 * will not do on this old chipset. But you can never
		 * be too careful, so reserve this memory anyway.
		 */
		ram@17f00000 {
			reg = <0x17f00000 0x00100000>;
			no-map;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2013 Linaro Ltd.
 */

#include "ste-nomadik-pinctrl.dtsi"

&pinctrl {
	/* Settings for all UART default and sleep states */
	uart0 {
		u0_a_1_default: u0_a_1_default {
			default_mux {
				function = "u0";
				groups = "u0_a_1";
			};
			default_cfg1 {
				pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
				ste,config = <&in_pu>;
			};
			default_cfg2 {
				pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
				ste,config = <&out_hi>;
			};
		};

		u0_a_1_sleep: u0_a_1_sleep {
			sleep_cfg1 {
				pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
				ste,config = <&slpm_in_wkup_pdis>;
			};
			sleep_cfg2 {
				pins = "GPIO1_AJ3"; /* RTS */
				ste,config = <&slpm_out_hi_wkup_pdis>;
			};
			sleep_cfg3 {
				pins = "GPIO3_AH3"; /* TXD */
				ste,config = <&slpm_out_wkup_pdis>;
			};
		};
	};

	uart1 {
		u1rxtx_a_1_default: u1rxtx_a_1_default {
			default_mux {
				function = "u1";
				groups = "u1rxtx_a_1";
			};
			default_cfg1 {
				pins = "GPIO4_AH6"; /* RXD */
				ste,config = <&in_pu>;
			};
			default_cfg2 {
				pins = "GPIO5_AG6"; /* TXD */
				ste,config = <&out_hi>;
			};
		};

		u1rxtx_a_1_sleep: u1rxtx_a_1_sleep {
			sleep_cfg1 {
				pins = "GPIO4_AH6"; /* RXD */
				ste,config = <&slpm_in_wkup_pdis>;
			};
			sleep_cfg2 {
				pins = "GPIO5_AG6"; /* TXD */
				ste,config = <&slpm_out_wkup_pdis>;
			};
		};

		u1ctsrts_a_1_default: u1ctsrts_a_1_default {
			default_mux {
				function = "u1";
				groups = "u1ctsrts_a_1";
			};
			default_cfg1 {
				pins = "GPIO6_AF6"; /* CTS */
				ste,config = <&in_pu>;
			};
			default_cfg2 {
				pins = "GPIO7_AG5"; /* RTS */
				ste,config = <&out_hi>;
			};
		};

		u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep {
			sleep_cfg1 {
				pins = "GPIO6_AF6"; /* CTS */
				ste,config = <&slpm_in_wkup_pdis>;
			};
			sleep_cfg2 {
				pins = "GPIO7_AG5"; /* RTS */
				ste,config = <&slpm_out_hi_wkup_pdis>;
			};
		};
	};

	uart2 {
		u2rxtx_c_1_default: u2rxtx_c_1_default {
			default_mux {
				function = "u2";
				groups = "u2rxtx_c_1";
			};
			default_cfg1 {
				pins = "GPIO29_W2"; /* RXD */
				ste,config = <&in_pu>;
			};
			default_cfg2 {
				pins = "GPIO30_W3"; /* TXD */
				ste,config = <&out_hi>;
			};
		};

		u2rxtx_c_1_sleep: u2rxtx_c_1_sleep {
			sleep_cfg1 {
				pins = "GPIO29_W2"; /* RXD */
				ste,config = <&in_wkup_pdis>;
			};
			sleep_cfg2 {
				pins = "GPIO30_W3"; /* TXD */
				ste,config = <&out_wkup_pdis>;
			};
		};
	};

	/* Settings for all I2C default and sleep states */
	i2c0 {
		i2c0_a_1_default: i2c0_a_1_default {
			default_mux {
				function = "i2c0";
				groups = "i2c0_a_1";
			};
			default_cfg1 {
				pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
				ste,config = <&in_nopull>;
			};
		};

		i2c0_a_1_sleep: i2c0_a_1_sleep {
			sleep_cfg1 {
				pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
				ste,config = <&slpm_in_wkup_pdis>;
			};
		};
	};

	i2c1 {
		i2c1_b_2_default: i2c1_b_2_default {
			default_mux {
				function = "i2c1";
				groups = "i2c1_b_2";
			};
			default_cfg1 {
				pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
				ste,config = <&in_nopull>;
			};
		};

		i2c1_b_2_sleep: i2c1_b_2_sleep {
			sleep_cfg1 {
				pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
				ste,config = <&slpm_in_wkup_pdis>;
			};
		};
	};

	i2c2 {
		i2c2_b_1_default: i2c2_b_1_default {
			default_mux {
				function = "i2c2";
				groups = "i2c2_b_1";
			};
			default_cfg1 {
				pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */
				ste,config = <&in_nopull>;
			};
		};

		i2c2_b_1_sleep: i2c2_b_1_sleep {
			sleep_cfg1 {
				pins = "GPIO8_AD5", "GPIO9_AE4"; /* SDA/SCL */
				ste,config = <&slpm_in_wkup_pdis>;
			};
		};

		i2c2_b_2_default: i2c2_b_2_default {
			default_mux {
				function = "i2c2";
				groups = "i2c2_b_2";
			};
			default_cfg1 {
				pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
				ste,config = <&in_nopull>;
			};
		};

		i2c2_b_2_sleep: i2c2_b_2_sleep {
			sleep_cfg1 {
				pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
				ste,config = <&slpm_in_wkup_pdis>;
			};
		};
	};

	i2c3 {
		i2c3_c_2_default: i2c3_c_2_default {
			default_mux {
				function = "i2c3";
				groups = "i2c3_c_2";
			};
			default_cfg1 {
				pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
				ste,config = <&in_nopull>;
			};
		};

		i2c3_c_2_sleep: i2c3_c_2_sleep {
			sleep_cfg1 {
				pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
				ste,config = <&slpm_in_wkup_pdis>;
			};
		};
	};

	/*
	 * Activating I2C4 will conflict with UART1 about the same pins so do not
	 * enable I2C4 and UART1 at the same time.
	 */
	i2c4 {
		i2c4_b_1_default: i2c4_b_1_default {
			default_mux {
				function = "i2c4";
				groups = "i2c4_b_1";
			};
			default_cfg1 {
				pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
				ste,config = <&in_nopull>;
			};
		};

		i2c4_b_1_sleep: i2c4_b_1_sleep {
			sleep_cfg1 {
				pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
				ste,config = <&slpm_in_wkup_pdis>;
			};
		};
	};

	/* Settings for all MMC/SD/SDIO default and sleep states */
	sdi0 {
		/* This is the external SD card slot, 4 bits wide */
		mc0_a_1_default: mc0_a_1_default {
			default_mux {
				function = "mc0";
				groups = "mc0_a_1";
			};
			default_cfg1 {
				pins =
				"GPIO18_AC2", /* CMDDIR */
				"GPIO19_AC1", /* DAT0DIR */
				"GPIO20_AB4"; /* DAT2DIR */
				ste,config = <&out_hi>;
			};
			default_cfg2 {
				pins = "GPIO22_AA3"; /* FBCLK */
				ste,config = <&in_nopull>;
			};
			default_cfg3 {
				pins = "GPIO23_AA4"; /* CLK */
				ste,config = <&out_lo>;
			};
			default_cfg4 {
				pins =
				"GPIO24_AB2", /* CMD */
				"GPIO25_Y4", /* DAT0 */
				"GPIO26_Y2", /* DAT1 */
				"GPIO27_AA2", /* DAT2 */
				"GPIO28_AA1"; /* DAT3 */
				ste,config = <&in_pu>;
			};
		};

		mc0_a_1_sleep: mc0_a_1_sleep {
			sleep_cfg1 {
				pins =
				"GPIO18_AC2", /* CMDDIR */
				"GPIO19_AC1", /* DAT0DIR */
				"GPIO20_AB4"; /* DAT2DIR */
				ste,config = <&slpm_out_hi_wkup_pdis>;
			};
			sleep_cfg2 {
				pins =
				"GPIO22_AA3", /* FBCLK */
				"GPIO24_AB2", /* CMD */
				"GPIO25_Y4", /* DAT0 */
				"GPIO26_Y2", /* DAT1 */
				"GPIO27_AA2", /* DAT2 */
				"GPIO28_AA1"; /* DAT3 */
				ste,config = <&slpm_in_wkup_pdis>;
			};
			sleep_cfg3 {
				pins = "GPIO23_AA4"; /* CLK */
				ste,config = <&slpm_out_lo_wkup_pdis>;
			};
		};

		mc0_a_2_default: mc0_a_2_default {
			default_mux {
				function = "mc0";
				groups = "mc0_a_2";
			};
			default_cfg1 {
				pins = "GPIO22_AA3"; /* FBCLK */
				ste,config = <&in_nopull>;
			};
			default_cfg2 {
				pins = "GPIO23_AA4"; /* CLK */
				ste,config = <&out_lo>;
			};
			default_cfg3 {
				pins =
				"GPIO24_AB2", /* CMD */
				"GPIO25_Y4", /* DAT0 */
				"GPIO26_Y2", /* DAT1 */
				"GPIO27_AA2", /* DAT2 */
				"GPIO28_AA1"; /* DAT3 */
				ste,config = <&in_pu>;
			};
		};

		mc0_a_2_sleep: mc0_a_2_sleep {
			sleep_cfg1 {
				pins =
				"GPIO22_AA3", /* FBCLK */
				"GPIO24_AB2", /* CMD */
				"GPIO25_Y4", /* DAT0 */
				"GPIO26_Y2", /* DAT1 */
				"GPIO27_AA2", /* DAT2 */
				"GPIO28_AA1"; /* DAT3 */
				ste,config = <&slpm_in_wkup_pdis>;
			};
			sleep_cfg2 {
				pins = "GPIO23_AA4"; /* CLK */
				ste,config = <&slpm_out_lo_wkup_pdis>;
			};
		};
	};

	sdi1 {
		/* This is the WLAN SDIO 4 bits wide */
		mc1_a_1_default: mc1_a_1_default {
			default_mux {
				function = "mc1";
				groups = "mc1_a_1";
			};
			default_cfg1 {
				pins = "GPIO208_AH16"; /* CLK */
				ste,config = <&out_lo>;
			};
			default_cfg2 {
				pins = "GPIO209_AG15"; /* FBCLK */
				ste,config = <&in_nopull>;
			};
			default_cfg3 {
				pins =
				"GPIO210_AJ15", /* CMD */
				"GPIO211_AG14", /* DAT0 */
				"GPIO212_AF13", /* DAT1 */
				"GPIO213_AG13", /* DAT2 */
				"GPIO214_AH15"; /* DAT3 */
				ste,config = <&in_pu>;
			};
		};

		mc1_a_1_sleep: mc1_a_1_sleep {
			sleep_cfg1 {
				pins = "GPIO208_AH16"; /* CLK */
				ste,config = <&slpm_out_lo_wkup_pdis>;
			};
			sleep_cfg2 {
				pins =
				"GPIO209_AG15", /* FBCLK */
				"GPIO210_AJ15", /* CMD */
				"GPIO211_AG14", /* DAT0 */
				"GPIO212_AF13", /* DAT1 */
				"GPIO213_AG13", /* DAT2 */
				"GPIO214_AH15"; /* DAT3 */
				ste,config = <&slpm_in_wkup_pdis>;
			};
		};

		mc1_a_2_default: mc1_a_2_default {
			default_mux {
				function = "mc1";
				groups = "mc1_a_2";
			};
			default_cfg1 {
				pins = "GPIO208_AH16"; /* CLK */
				ste,config = <&out_lo>;
			};
			default_cfg2 {
				pins =
				"GPIO210_AJ15", /* CMD */
				"GPIO211_AG14", /* DAT0 */
				"GPIO212_AF13", /* DAT1 */
				"GPIO213_AG13", /* DAT2 */
				"GPIO214_AH15"; /* DAT3 */
				ste,config = <&in_pu>;
			};
		};

		mc1_a_2_sleep: mc1_a_2_sleep {
			sleep_cfg1 {
				pins = "GPIO208_AH16"; /* CLK */
				ste,config = <&slpm_out_lo_wkup_pdis>;
			};
			sleep_cfg2 {
				pins =
				"GPIO210_AJ15", /* CMD */
				"GPIO211_AG14", /* DAT0 */
				"GPIO212_AF13", /* DAT1 */
				"GPIO213_AG13", /* DAT2 */
				"GPIO214_AH15"; /* DAT3 */
				ste,config = <&slpm_in_wkup_pdis>;
			};
		};
	};

	sdi2 {
		/* This is the eMMC 8 bits wide, usually PoP eMMC */
		mc2_a_1_default: mc2_a_1_default {
			default_mux {
				function = "mc2";
				groups = "mc2_a_1";
			};
			default_cfg1 {
				pins = "GPIO128_A5"; /* CLK */
				ste,config = <&out_lo>;
			};
			default_cfg2 {
				pins = "GPIO130_C8"; /* FBCLK */
				ste,config = <&in_nopull>;
			};
			default_cfg3 {
				pins =
				"GPIO129_B4", /* CMD */
				"GPIO131_A12", /* DAT0 */
				"GPIO132_C10", /* DAT1 */
				"GPIO133_B10", /* DAT2 */
				"GPIO134_B9", /* DAT3 */
				"GPIO135_A9", /* DAT4 */
				"GPIO136_C7", /* DAT5 */
				"GPIO137_A7", /* DAT6 */
				"GPIO138_C5"; /* DAT7 */
				ste,config = <&in_pu>;
			};
		};

		mc2_a_1_sleep: mc2_a_1_sleep {
			sleep_cfg1 {
				pins = "GPIO128_A5"; /* CLK */
				ste,config = <&out_lo_wkup_pdis>;
			};
			sleep_cfg2 {
				pins =
				"GPIO130_C8", /* FBCLK */
				"GPIO129_B4"; /* CMD */
				ste,config = <&in_wkup_pdis_en>;
			};
			sleep_cfg3 {
				pins =
				"GPIO131_A12", /* DAT0 */
				"GPIO132_C10", /* DAT1 */
				"GPIO133_B10", /* DAT2 */
				"GPIO134_B9", /* DAT3 */
				"GPIO135_A9", /* DAT4 */
				"GPIO136_C7", /* DAT5 */
				"GPIO137_A7", /* DAT6 */
				"GPIO138_C5"; /* DAT7 */
				ste,config = <&in_wkup_pdis>;
			};
		};
	};

	sdi4 {
		/* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
		mc4_a_1_default: mc4_a_1_default {
			default_mux {
				function = "mc4";
				groups = "mc4_a_1";
			};
			default_cfg1 {
				pins = "GPIO203_AE23"; /* CLK */
				ste,config = <&out_lo>;
			};
			default_cfg2 {
				pins = "GPIO202_AF25"; /* FBCLK */
				ste,config = <&in_nopull>;
			};
			default_cfg3 {
				pins =
				"GPIO201_AF24", /* CMD */
				"GPIO200_AH26", /* DAT0 */
				"GPIO199_AH23", /* DAT1 */
				"GPIO198_AG25", /* DAT2 */
				"GPIO197_AH24", /* DAT3 */
				"GPIO207_AJ23", /* DAT4 */
				"GPIO206_AG24", /* DAT5 */
				"GPIO205_AG23", /* DAT6 */
				"GPIO204_AF23"; /* DAT7 */
				ste,config = <&in_pu>;
			};
		};

		mc4_a_1_sleep: mc4_a_1_sleep {
			sleep_cfg1 {
				pins = "GPIO203_AE23"; /* CLK */
				ste,config = <&out_lo_wkup_pdis>;
			};
			sleep_cfg2 {
				pins =
				"GPIO202_AF25", /* FBCLK */
				"GPIO201_AF24", /* CMD */
				"GPIO200_AH26", /* DAT0 */
				"GPIO199_AH23", /* DAT1 */
				"GPIO198_AG25", /* DAT2 */
				"GPIO197_AH24", /* DAT3 */
				"GPIO207_AJ23", /* DAT4 */
				"GPIO206_AG24", /* DAT5 */
				"GPIO205_AG23", /* DAT6 */
				"GPIO204_AF23"; /* DAT7 */
				ste,config = <&slpm_in_wkup_pdis>;
			};
		};
	};

	/*
	 * Multi-rate serial ports (MSPs) - MSP3 output is internal and
	 * cannot be muxed onto any pins.
	 */
	msp0 {
		msp0txrxtfstck_a_1_default: msp0txrxtfstck_a_1_default {
			default_msp0_mux {
				function = "msp0";
				groups = "msp0txrx_a_1", "msp0tfstck_a_1";
			};
			default_msp0_cfg {
				pins =
				"GPIO12_AC4", /* TXD */
				"GPIO15_AC3", /* RXD */
				"GPIO13_AF3", /* TFS */
				"GPIO14_AE3"; /* TCK */
				ste,config = <&in_nopull>;
			};
		};
	};

	msp1 {
		msp1txrx_a_1_default: msp1txrx_a_1_default {
			default_mux {
				function = "msp1";
				groups = "msp1txrx_a_1", "msp1_a_1";
			};
			default_cfg1 {
				pins = "GPIO33_AF2";
				ste,config = <&out_lo>;
			};
			default_cfg2 {
				pins =
				"GPIO34_AE1",
				"GPIO35_AE2",
				"GPIO36_AG2";
				ste,config = <&in_nopull>;
			};
		};
	};

	msp2 {
		msp2_a_1_default: msp2_a_1_default {
			/* MSP2 usually used for HDMI audio */
			default_mux {
				function = "msp2";
				groups = "msp2_a_1";
			};
			default_cfg1 {
				pins =
				"GPIO193_AH27", /* TXD */
				"GPIO194_AF27", /* TCK */
				"GPIO195_AG28"; /* TFS */
				ste,config = <&in_pd>;
			};
			default_cfg2 {
				pins = "GPIO196_AG26"; /* RXD */
				ste,config = <&out_lo>;
			};
		};
	};

	musb {
		usb_a_1_default: usb_a_1_default {
			default_mux {
				function = "usb";
				groups = "usb_a_1";
			};
			default_cfg1 {
				pins =
				"GPIO256_AF28", /* NXT */
				"GPIO258_AD29", /* XCLK */
				"GPIO259_AC29", /* DIR */
				"GPIO260_AD28", /* DAT7 */
				"GPIO261_AD26", /* DAT6 */
				"GPIO262_AE26", /* DAT5 */
				"GPIO263_AG29", /* DAT4 */
				"GPIO264_AE27", /* DAT3 */
				"GPIO265_AD27", /* DAT2 */
				"GPIO266_AC28", /* DAT1 */
				"GPIO267_AC27"; /* DAT0 */
				ste,config = <&in_nopull>;
			};
			default_cfg2 {
				pins = "GPIO257_AE29"; /* STP */
				ste,config = <&out_hi>;
			};
		};

		usb_a_1_sleep: usb_a_1_sleep {
			sleep_cfg1 {
				pins =
				"GPIO256_AF28", /* NXT */
				"GPIO258_AD29", /* XCLK */
				"GPIO259_AC29"; /* DIR */
				ste,config = <&slpm_wkup_pdis_en>;
			};
			sleep_cfg2 {
				pins = "GPIO257_AE29"; /* STP */
				ste,config = <&slpm_out_hi_wkup_pdis>;
			};
			sleep_cfg3 {
				pins =
				"GPIO260_AD28", /* DAT7 */
				"GPIO261_AD26", /* DAT6 */
				"GPIO262_AE26", /* DAT5 */
				"GPIO263_AG29", /* DAT4 */
				"GPIO264_AE27", /* DAT3 */
				"GPIO265_AD27", /* DAT2 */
				"GPIO266_AC28", /* DAT1 */
				"GPIO267_AC27"; /* DAT0 */
				ste,config = <&slpm_in_wkup_pdis_en>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Linaro Ltd
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
#include <dt-bindings/mfd/dbx500-prcmu.h>
#include <dt-bindings/arm/ux500_pm_domains.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	/* This stablilizes the device enumeration */
	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
	};

	chosen {
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "ste,dbx500-smp";

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
				core1 {
					cpu = <&CPU1>;
				};
			};
		};
		CPU0: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x300>;
			clocks = <&prcmu_clk PRCMU_ARMSS>;
			clock-names = "cpu";
			clock-latency = <20000>;
			#cooling-cells = <2>;
		};
		CPU1: cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x301>;
		};
	};

	thermal-zones {
		/*
		 * Thermal zone for the SoC, using the thermal sensor in the
		 * PRCMU for temperature and the cpufreq driver for passive
		 * cooling.
		 */
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <250>;
			/*
			 * This sensor fires interrupts to update the thermal
			 * zone, so no polling is needed.
			 */
			polling-delay = <0>;

			thermal-sensors = <&thermal>;

			trips {
				cpu_alert: cpu-alert {
					temperature = <70000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu-crit {
					temperature = <85000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
				trip = <&cpu_alert>;
				cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				contribution = <100>;
			};
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "stericsson,db8500", "simple-bus";
		interrupt-parent = <&intc>;
		ranges;

		ptm@801ae000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x801ae000 0x1000>;

			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
			clock-names = "apb_pclk", "atclk";
			cpu = <&CPU0>;
			out-ports {
				port {
					ptm0_out_port: endpoint {
						remote-endpoint = <&funnel_in_port0>;
					};
				};
			};
		};

		ptm@801af000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x801af000 0x1000>;

			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
			clock-names = "apb_pclk", "atclk";
			cpu = <&CPU1>;
			out-ports {
				port {
					ptm1_out_port: endpoint {
						remote-endpoint = <&funnel_in_port1>;
					};
				};
			};
		};

		funnel@801a6000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x801a6000 0x1000>;

			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
			clock-names = "apb_pclk", "atclk";
			out-ports {
				port {
					funnel_out_port: endpoint {
						remote-endpoint =
							<&replicator_in_port0>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					funnel_in_port0: endpoint {
						remote-endpoint = <&ptm0_out_port>;
					};
				};

				port@1 {
					reg = <1>;
					funnel_in_port1: endpoint {
						remote-endpoint = <&ptm1_out_port>;
					};
				};
			};
		};

		replicator {
			compatible = "arm,coresight-static-replicator";
			clocks = <&prcmu_clk PRCMU_APEATCLK>;
			clock-names = "atclk";

			out-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					replicator_out_port0: endpoint {
						remote-endpoint = <&tpiu_in_port>;
					};
				};
				port@1 {
					reg = <1>;
					replicator_out_port1: endpoint {
						remote-endpoint = <&etb_in_port>;
					};
				};
			};

			in-ports {
				port {
					replicator_in_port0: endpoint {
						remote-endpoint = <&funnel_out_port>;
					};
				};
			};
		};

		tpiu@80190000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0x80190000 0x1000>;

			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
			clock-names = "apb_pclk", "atclk";
			in-ports {
				port {
					tpiu_in_port: endpoint {
						remote-endpoint = <&replicator_out_port0>;
					};
				};
			};
		};

		etb@801a4000 {
			compatible = "arm,coresight-etb10", "arm,primecell";
			reg = <0x801a4000 0x1000>;

			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
			clock-names = "apb_pclk", "atclk";
			in-ports {
				port {
					etb_in_port: endpoint {
						remote-endpoint = <&replicator_out_port1>;
					};
				};
			};
		};

		intc: interrupt-controller@a0411000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			interrupt-controller;
			reg = <0xa0411000 0x1000>,
			      <0xa0410100 0x100>;
		};

		scu@a0410000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xa0410000 0x100>;
		};

		/*
		 * The backup RAM is used for retention during sleep
		 * and various things like spin tables
		 */
		backupram@80150000 {
			compatible = "ste,dbx500-backupram";
			reg = <0x80150000 0x2000>;
		};

		L2: cache-controller {
			compatible = "arm,pl310-cache";
			reg = <0xa0412000 0x1000>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-level = <2>;
		};

		pmu {
			compatible = "arm,cortex-a9-pmu";
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		};

		pm_domains: pm_domains0 {
			compatible = "stericsson,ux500-pm-domains";
			#power-domain-cells = <1>;
		};

		clocks {
			compatible = "stericsson,u8500-clks";
			/*
			 * Registers for the CLKRST block on peripheral
			 * groups 1, 2, 3, 5, 6,
			 */
			reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
			    <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
			    <0xa03cf000 0x1000>;

			prcmu_clk: prcmu-clock {
				#clock-cells = <1>;
			};

			prcc_pclk: prcc-periph-clock {
				#clock-cells = <2>;
			};

			prcc_kclk: prcc-kernel-clock {
				#clock-cells = <2>;
			};

			prcc_reset: prcc-reset-controller {
				#reset-cells = <2>;
			};

			rtc_clk: rtc32k-clock {
				#clock-cells = <0>;
			};

			smp_twd_clk: smp-twd-clock {
				#clock-cells = <0>;
			};
		};

		mtu@a03c6000 {
			/* Nomadik System Timer */
			compatible = "st,nomadik-mtu";
			reg = <0xa03c6000 0x1000>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
			clock-names = "timclk", "apb_pclk";
		};

		timer@a0410600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xa0410600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;

			clocks = <&smp_twd_clk>;
		};

		watchdog@a0410620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0xa0410620 0x20>;
			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&smp_twd_clk>;
		};

		rtc@80154000 {
			compatible = "arm,pl031", "arm,primecell";
			reg = <0x80154000 0x1000>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rtc_clk>;
			clock-names = "apb_pclk";
		};

		gpio0: gpio@8012e000 {
			compatible = "stericsson,db8500-gpio",
				"st,nomadik-gpio";
			reg =  <0x8012e000 0x80>;
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			st,supports-sleepmode;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-bank = <0>;
			gpio-ranges = <&pinctrl 0 0 32>;
			clocks = <&prcc_pclk 1 9>;
		};

		gpio1: gpio@8012e080 {
			compatible = "stericsson,db8500-gpio",
				"st,nomadik-gpio";
			reg =  <0x8012e080 0x80>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			st,supports-sleepmode;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-bank = <1>;
			gpio-ranges = <&pinctrl 0 32 5>;
			clocks = <&prcc_pclk 1 9>;
		};

		gpio2: gpio@8000e000 {
			compatible = "stericsson,db8500-gpio",
				"st,nomadik-gpio";
			reg =  <0x8000e000 0x80>;
			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			st,supports-sleepmode;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-bank = <2>;
			gpio-ranges = <&pinctrl 0 64 32>;
			clocks = <&prcc_pclk 3 8>;
		};

		gpio3: gpio@8000e080 {
			compatible = "stericsson,db8500-gpio",
				"st,nomadik-gpio";
			reg =  <0x8000e080 0x80>;
			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			st,supports-sleepmode;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-bank = <3>;
			gpio-ranges = <&pinctrl 0 96 2>;
			clocks = <&prcc_pclk 3 8>;
		};

		gpio4: gpio@8000e100 {
			compatible = "stericsson,db8500-gpio",
				"st,nomadik-gpio";
			reg =  <0x8000e100 0x80>;
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			st,supports-sleepmode;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-bank = <4>;
			gpio-ranges = <&pinctrl 0 128 32>;
			clocks = <&prcc_pclk 3 8>;
		};

		gpio5: gpio@8000e180 {
			compatible = "stericsson,db8500-gpio",
				"st,nomadik-gpio";
			reg =  <0x8000e180 0x80>;
			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			st,supports-sleepmode;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-bank = <5>;
			gpio-ranges = <&pinctrl 0 160 12>;
			clocks = <&prcc_pclk 3 8>;
		};

		gpio6: gpio@8011e000 {
			compatible = "stericsson,db8500-gpio",
				"st,nomadik-gpio";
			reg =  <0x8011e000 0x80>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			st,supports-sleepmode;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-bank = <6>;
			gpio-ranges = <&pinctrl 0 192 32>;
			clocks = <&prcc_pclk 2 11>;
		};

		gpio7: gpio@8011e080 {
			compatible = "stericsson,db8500-gpio",
				"st,nomadik-gpio";
			reg =  <0x8011e080 0x80>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			st,supports-sleepmode;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-bank = <7>;
			gpio-ranges = <&pinctrl 0 224 7>;
			clocks = <&prcc_pclk 2 11>;
		};

		gpio8: gpio@a03fe000 {
			compatible = "stericsson,db8500-gpio",
				"st,nomadik-gpio";
			reg =  <0xa03fe000 0x80>;
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			st,supports-sleepmode;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-bank = <8>;
			gpio-ranges = <&pinctrl 0 256 12>;
			clocks = <&prcc_pclk 5 1>;
		};

		pinctrl: pinctrl {
			compatible = "stericsson,db8500-pinctrl";
			nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
						<&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
						<&gpio8>;
			prcm = <&prcmu>;
		};

		usb_per5@a03e0000 {
			compatible = "stericsson,db8500-musb";
			reg = <0xa03e0000 0x10000>;
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mc";

			dr_mode = "otg";

			dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
			       <&dma 38 0 0x0>, /* Logical - MemToDev */
			       <&dma 37 0 0x2>, /* Logical - DevToMem */
			       <&dma 37 0 0x0>, /* Logical - MemToDev */
			       <&dma 36 0 0x2>, /* Logical - DevToMem */
			       <&dma 36 0 0x0>, /* Logical - MemToDev */
			       <&dma 19 0 0x2>, /* Logical - DevToMem */
			       <&dma 19 0 0x0>, /* Logical - MemToDev */
			       <&dma 18 0 0x2>, /* Logical - DevToMem */
			       <&dma 18 0 0x0>, /* Logical - MemToDev */
			       <&dma 17 0 0x2>, /* Logical - DevToMem */
			       <&dma 17 0 0x0>, /* Logical - MemToDev */
			       <&dma 16 0 0x2>, /* Logical - DevToMem */
			       <&dma 16 0 0x0>, /* Logical - MemToDev */
			       <&dma 39 0 0x2>, /* Logical - DevToMem */
			       <&dma 39 0 0x0>; /* Logical - MemToDev */

			dma-names = "iep_1_9",  "oep_1_9",
				    "iep_2_10", "oep_2_10",
				    "iep_3_11", "oep_3_11",
				    "iep_4_12", "oep_4_12",
				    "iep_5_13", "oep_5_13",
				    "iep_6_14", "oep_6_14",
				    "iep_7_15", "oep_7_15",
				    "iep_8",    "oep_8";

			clocks = <&prcc_pclk 5 0>;
		};

		dma: dma-controller@801C0000 {
			compatible = "stericsson,db8500-dma40", "stericsson,dma40";
			reg = <0x801C0000 0x1000 0x40010000 0x800>;
			reg-names = "base", "lcpa";
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

			#dma-cells = <3>;
			memcpy-channels = <56 57 58 59 60>;

			clocks = <&prcmu_clk PRCMU_DMACLK>;
		};

		prcmu: prcmu@80157000 {
			compatible = "stericsson,db8500-prcmu", "syscon";
			reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
			reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ranges;

			prcmu-timer-4@80157450 {
				compatible = "stericsson,db8500-prcmu-timer-4";
				reg = <0x80157450 0xC>;
			};

			thermal: thermal@801573c0 {
				compatible = "stericsson,db8500-thermal";
				reg = <0x801573c0 0x40>;
				interrupt-parent = <&prcmu>;
				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
					     <22 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
				#thermal-sensor-cells = <0>;
			};

			db8500-prcmu-regulators {
				compatible = "stericsson,db8500-prcmu-regulator";

				// DB8500_REGULATOR_VAPE
				db8500_vape_reg: db8500_vape {
					regulator-always-on;
				};

				// DB8500_REGULATOR_VARM
				db8500_varm_reg: db8500_varm {
				};

				// DB8500_REGULATOR_VMODEM
				db8500_vmodem_reg: db8500_vmodem {
				};

				// DB8500_REGULATOR_VPLL
				db8500_vpll_reg: db8500_vpll {
				};

				// DB8500_REGULATOR_VSMPS1
				db8500_vsmps1_reg: db8500_vsmps1 {
				};

				// DB8500_REGULATOR_VSMPS2
				db8500_vsmps2_reg: db8500_vsmps2 {
				};

				// DB8500_REGULATOR_VSMPS3
				db8500_vsmps3_reg: db8500_vsmps3 {
				};

				// DB8500_REGULATOR_VRF1
				db8500_vrf1_reg: db8500_vrf1 {
				};

				// DB8500_REGULATOR_SWITCH_SVAMMDSP
				db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
				};

				// DB8500_REGULATOR_SWITCH_SVAMMDSPRET
				db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
				};

				// DB8500_REGULATOR_SWITCH_SVAPIPE
				db8500_sva_pipe_reg: db8500_sva_pipe {
				};

				// DB8500_REGULATOR_SWITCH_SIAMMDSP
				db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
				};

				// DB8500_REGULATOR_SWITCH_SIAMMDSPRET
				db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
				};

				// DB8500_REGULATOR_SWITCH_SIAPIPE
				db8500_sia_pipe_reg: db8500_sia_pipe {
				};

				// DB8500_REGULATOR_SWITCH_SGA
				db8500_sga_reg: db8500_sga {
					vin-supply = <&db8500_vape_reg>;
				};

				// DB8500_REGULATOR_SWITCH_B2R2_MCDE
				db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
					vin-supply = <&db8500_vape_reg>;
				};

				// DB8500_REGULATOR_SWITCH_ESRAM12
				db8500_esram12_reg: db8500_esram12 {
				};

				// DB8500_REGULATOR_SWITCH_ESRAM12RET
				db8500_esram12_ret_reg: db8500_esram12_ret {
				};

				// DB8500_REGULATOR_SWITCH_ESRAM34
				db8500_esram34_reg: db8500_esram34 {
				};

				// DB8500_REGULATOR_SWITCH_ESRAM34RET
				db8500_esram34_ret_reg: db8500_esram34_ret {
				};
			};
		};

		i2c0: i2c@80004000 {
			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
			reg = <0x80004000 0x1000>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			clock-frequency = <400000>;
			clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
			clock-names = "i2cclk", "apb_pclk";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>;

			status = "disabled";
		};

		i2c1: i2c@80122000 {
			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
			reg = <0x80122000 0x1000>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			clock-frequency = <400000>;

			clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
			clock-names = "i2cclk", "apb_pclk";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>;

			status = "disabled";
		};

		i2c2: i2c@80128000 {
			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
			reg = <0x80128000 0x1000>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			clock-frequency = <400000>;

			clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
			clock-names = "i2cclk", "apb_pclk";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>;

			status = "disabled";
		};

		i2c3: i2c@80110000 {
			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
			reg = <0x80110000 0x1000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			clock-frequency = <400000>;

			clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
			clock-names = "i2cclk", "apb_pclk";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>;

			status = "disabled";
		};

		i2c4: i2c@8012a000 {
			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
			reg = <0x8012a000 0x1000>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			clock-frequency = <400000>;

			clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
			clock-names = "i2cclk", "apb_pclk";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>;

			status = "disabled";
		};

		ssp0: spi@80002000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x80002000 0x1000>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
			clock-names = "sspclk", "apb_pclk";
			dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
			       <&dma 8 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>;

			status = "disabled";
		};

		ssp1: spi@80003000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x80003000 0x1000>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
			clock-names = "sspclk", "apb_pclk";
			dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
			       <&dma 9 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>;

			status = "disabled";
		};

		spi0: spi@8011a000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x8011a000 0x1000>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			/* Same clock wired to kernel and pclk */
			clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
			clock-names = "sspclk", "apb_pclk";
			dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
			       <&dma 0 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";
			power-domains = <&pm_domains DOMAIN_VAPE>;

			status = "disabled";
		};

		spi1: spi@80112000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x80112000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			/* Same clock wired to kernel and pclk */
			clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
			clock-names = "sspclk", "apb_pclk";
			dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
			       <&dma 35 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";
			power-domains = <&pm_domains DOMAIN_VAPE>;

			status = "disabled";
		};

		spi2: spi@80111000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x80111000 0x1000>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			/* Same clock wired to kernel and pclk */
			clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
			clock-names = "sspclk", "apb_pclk";
			dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
			       <&dma 33 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";
			power-domains = <&pm_domains DOMAIN_VAPE>;

			status = "disabled";
		};

		spi3: spi@80129000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x80129000 0x1000>;
			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			/* Same clock wired to kernel and pclk */
			clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
			clock-names = "sspclk", "apb_pclk";
			dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
			       <&dma 40 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>;

			status = "disabled";
		};

		serial0: uart@80120000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x80120000 0x1000>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

			dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
			       <&dma 13 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";

			clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
			clock-names = "uart", "apb_pclk";
			resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>;

			status = "disabled";
		};

		serial1: uart@80121000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x80121000 0x1000>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

			dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
			       <&dma 12 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";

			clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
			clock-names = "uart", "apb_pclk";
			resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>;

			status = "disabled";
		};

		serial2: uart@80007000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x80007000 0x1000>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;

			dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
			       <&dma 11 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";

			clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
			clock-names = "uart", "apb_pclk";
			resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>;

			status = "disabled";
		};

		mmc@80126000 {
			compatible = "arm,pl18x", "arm,primecell";
			reg = <0x80126000 0x1000>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;

			dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
			       <&dma 29 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";

			clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
			clock-names = "sdi", "apb_pclk";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>;

			status = "disabled";
		};

		mmc@80118000 {
			compatible = "arm,pl18x", "arm,primecell";
			reg = <0x80118000 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;

			dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
			       <&dma 32 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";

			clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
			clock-names = "sdi", "apb_pclk";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>;

			status = "disabled";
		};

		mmc@80005000 {
			compatible = "arm,pl18x", "arm,primecell";
			reg = <0x80005000 0x1000>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;

			dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
			       <&dma 28 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";

			clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
			clock-names = "sdi", "apb_pclk";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>;

			status = "disabled";
		};

		mmc@80119000 {
			compatible = "arm,pl18x", "arm,primecell";
			reg = <0x80119000 0x1000>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;

			dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
			       <&dma 41 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";

			clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
			clock-names = "sdi", "apb_pclk";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>;

			status = "disabled";
		};

		mmc@80114000 {
			compatible = "arm,pl18x", "arm,primecell";
			reg = <0x80114000 0x1000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

			dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
			       <&dma 42 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";

			clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
			clock-names = "sdi", "apb_pclk";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>;

			status = "disabled";
		};

		mmc@80008000 {
			compatible = "arm,pl18x", "arm,primecell";
			reg = <0x80008000 0x1000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

			dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
			       <&dma 43 0 0x0>; /* Logical - MemToDev */
			dma-names = "rx", "tx";

			clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
			clock-names = "sdi", "apb_pclk";
			power-domains = <&pm_domains DOMAIN_VAPE>;
			resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>;

			status = "disabled";
		};

		sound {
			compatible = "stericsson,snd-soc-mop500";
			stericsson,cpu-dai = <&msp1 &msp3>;
		};

		msp0: msp@80123000 {
			compatible = "stericsson,ux500-msp-i2s";
			reg = <0x80123000 0x1000>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			v-ape-supply = <&db8500_vape_reg>;

			dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
			       <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
			dma-names = "rx", "tx";

			clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
			clock-names = "msp", "apb_pclk";
			resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>;

			status = "disabled";
		};

		msp1: msp@80124000 {
			compatible = "stericsson,ux500-msp-i2s";
			reg = <0x80124000 0x1000>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			v-ape-supply = <&db8500_vape_reg>;

			/* This DMA channel only exist on DB8500 v1 */
			dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
			dma-names = "tx";

			clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
			clock-names = "msp", "apb_pclk";
			resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>;

			status = "disabled";
		};

		// HDMI sound
		msp2: msp@80117000 {
			compatible = "stericsson,ux500-msp-i2s";
			reg = <0x80117000 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			v-ape-supply = <&db8500_vape_reg>;

			dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
			       <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
                                                    HighPrio - Fixed */
			dma-names = "rx", "tx";

			clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
			clock-names = "msp", "apb_pclk";
			resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>;

			status = "disabled";
		};

		msp3: msp@80125000 {
			compatible = "stericsson,ux500-msp-i2s";
			reg = <0x80125000 0x1000>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			v-ape-supply = <&db8500_vape_reg>;

			/* This DMA channel only exist on DB8500 v2 */
			dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
			dma-names = "rx";

			clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
			clock-names = "msp", "apb_pclk";
			resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>;

			status = "disabled";
		};

		external-bus@50000000 {
			compatible = "simple-bus";
			reg = <0x50000000 0x4000000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x50000000 0x4000000>;
			status = "disabled";
		};

		gpu@a0300000 {
			/*
			 * This block is referred to as "Smart Graphics Adapter SGA500"
			 * in documentation but is in practice a pretty straight-forward
			 * MALI-400 GPU block.
			 */
			compatible = "stericsson,db8500-mali", "arm,mali-400";
			reg = <0xa0300000 0x10000>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gp",
					  "gpmmu",
					  "pp0",
					  "ppmmu0",
					  "combined";
			clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>;
			clock-names = "bus", "core";
			mali-supply = <&db8500_sga_reg>;
			power-domains = <&pm_domains DOMAIN_VAPE>;
		};

		mcde@a0350000 {
			compatible = "ste,mcde";
			reg = <0xa0350000 0x1000>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			epod-supply = <&db8500_b2r2_mcde_reg>;
			clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
				 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
				 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
			clock-names = "mcde", "lcd", "hdmi";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			dsi0: dsi@a0351000 {
				compatible = "ste,mcde-dsi";
				reg = <0xa0351000 0x1000>;
				clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
				clock-names = "hs", "lp";
				#address-cells = <1>;
				#size-cells = <0>;
			};
			dsi1: dsi@a0352000 {
				compatible = "ste,mcde-dsi";
				reg = <0xa0352000 0x1000>;
				clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
				clock-names = "hs", "lp";
				#address-cells = <1>;
				#size-cells = <0>;
			};
			dsi2: dsi@a0353000 {
				compatible = "ste,mcde-dsi";
				reg = <0xa0353000 0x1000>;
				/* This DSI port only has the Low Power / Energy Save clock */
				clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
				clock-names = "lp";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		cryp@a03cb000 {
			compatible = "stericsson,ux500-cryp";
			reg = <0xa03cb000 0x1000>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&prcc_pclk 6 1>;
			power-domains = <&pm_domains DOMAIN_VAPE>;
		};

		hash@a03c2000 {
			compatible = "stericsson,ux500-hash";
			reg = <0xa03c2000 0x1000>;
			clocks = <&prcc_pclk 6 2>;
			power-domains = <&pm_domains DOMAIN_VAPE>;
		};
	};
};