code:
=====================================================================
SEC 4 Device Tree Binding
Copyright (C) 2008-2011 Freescale Semiconductor Inc.

 CONTENTS
   -Overview
   -SEC 4 Node
   -Job Ring Node
   -Run Time Integrity Check (RTIC) Node
   -Run Time Integrity Check (RTIC) Memory Node
   -Secure Non-Volatile Storage (SNVS) Node
   -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
   -Full Example

NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
Accelerator and Assurance Module (CAAM).

=====================================================================
Overview

DESCRIPTION

SEC 4 h/w can process requests from 2 types of sources.
1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
2. Job Rings (HW interface between cores & SEC 4 registers).

High Speed Data Path Configuration:

HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
such as the P4080.  The number of simultaneous dequeues the QI can make is
equal to the number of Descriptor Controller (DECO) engines in a particular
SEC version.  E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
dequeue from 5 subportals simultaneously.

Job Ring Data Path Configuration:

Each JR is located on a separate 4k page, they may (or may not) be made visible
in the memory partition devoted to a particular core.  The P4080 has 4 JRs, so
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.

=====================================================================
SEC 4 Node

Description

    Node defines the base address of the SEC 4 block.
    This block specifies the address range of all global
    configuration registers for the SEC 4 block.  It
    also receives interrupts from the Run Time Integrity Check
    (RTIC) function within the SEC 4 block.

PROPERTIES

   - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0"

   - fsl,sec-era
      Usage: optional
      Value type: <u32>
      Definition: A standard property. Define the 'ERA' of the SEC
          device.

   - #address-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing physical addresses in child nodes.

   - #size-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing the size of physical addresses in
           child nodes.

   - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies the physical
          address and length of the SEC4 configuration registers.
          registers

   - ranges
       Usage: required
       Value type: <prop-encoded-array>
       Definition: A standard property.  Specifies the physical address
           range of the SEC 4.0 register space (-SNVS not included).  A
           triplet that includes the child address, parent address, &
           length.

   - interrupts
      Usage: required
      Value type: <prop_encoded-array>
      Definition:  Specifies the interrupts generated by this
           device.  The value of the interrupts property
           consists of one interrupt specifier. The format
           of the specifier is defined by the binding document
           describing the node's interrupt parent.

   - clocks
      Usage: required if SEC 4.0 requires explicit enablement of clocks
      Value type: <prop_encoded-array>
      Definition:  A list of phandle and clock specifier pairs describing
          the clocks required for enabling and disabling SEC 4.0.

   - clock-names
      Usage: required if SEC 4.0 requires explicit enablement of clocks
      Value type: <string>
      Definition: A list of clock name strings in the same order as the
          clocks property.

   Note: All other standard properties (see the Devicetree Specification)
   are allowed but are optional.

EXAMPLE

iMX6QDL/SX requires four clocks

	crypto@300000 {
		compatible = "fsl,sec-v4.0";
		fsl,sec-era = <2>;
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x300000 0x10000>;
		ranges = <0 0x300000 0x10000>;
		interrupt-parent = <&mpic>;
		interrupts = <92 2>;
		clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
			 <&clks IMX6QDL_CLK_CAAM_ACLK>,
			 <&clks IMX6QDL_CLK_CAAM_IPG>,
			 <&clks IMX6QDL_CLK_EIM_SLOW>;
		clock-names = "mem", "aclk", "ipg", "emi_slow";
	};

iMX6UL does only require three clocks

	crypto: crypto@2140000 {
		compatible = "fsl,sec-v4.0";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x2140000 0x3c000>;
		ranges = <0 0x2140000 0x3c000>;
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clks IMX6UL_CLK_CAAM_MEM>,
			 <&clks IMX6UL_CLK_CAAM_ACLK>,
			 <&clks IMX6UL_CLK_CAAM_IPG>;
		clock-names = "mem", "aclk", "ipg";
	};

=====================================================================
Job Ring (JR) Node

    Child of the crypto node defines data processing interface to SEC 4
    across the peripheral bus for purposes of processing
    cryptographic descriptors. The specified address
    range can be made visible to one (or more) cores.
    The interrupt defined for this node is controlled within
    the address range of this node.

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-job-ring"

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: Specifies a two JR parameters:  an offset from
          the parent physical address and the length the JR registers.

   - fsl,liodn
       Usage: optional-but-recommended
       Value type: <prop-encoded-array>
       Definition:
           Specifies the LIODN to be used in conjunction with
           the ppid-to-liodn table that specifies the PPID to LIODN mapping.
           Needed if the PAMU is used.  Value is a 12 bit value
           where value is a LIODN ID for this JR. This property is
           normally set by boot firmware.

   - interrupts
      Usage: required
      Value type: <prop_encoded-array>
      Definition:  Specifies the interrupts generated by this
           device.  The value of the interrupts property
           consists of one interrupt specifier. The format
           of the specifier is defined by the binding document
           describing the node's interrupt parent.

EXAMPLE
	jr@1000 {
		compatible = "fsl,sec-v4.0-job-ring";
		reg = <0x1000 0x1000>;
		fsl,liodn = <0x081>;
		interrupt-parent = <&mpic>;
		interrupts = <88 2>;
	};

=====================================================================
Run Time Integrity Check (RTIC) Node

  Child node of the crypto node.  Defines a register space that
  contains up to 5 sets of addresses and their lengths (sizes) that
  will be checked at run time.  After an initial hash result is
  calculated, these addresses are checked by HW to monitor any
  change.  If any memory is modified, a Security Violation is
  triggered (see SNVS definition).

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-rtic".

   - #address-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing physical addresses in child nodes.  Must
           have a value of 1.

   - #size-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing the size of physical addresses in
           child nodes.  Must have a value of 1.

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies a two parameters:
          an offset from the parent physical address and the length
          the SEC4 registers.

   - ranges
       Usage: required
       Value type: <prop-encoded-array>
       Definition: A standard property.  Specifies the physical address
           range of the SEC 4 register space (-SNVS not included).  A
           triplet that includes the child address, parent address, &
           length.

EXAMPLE
	rtic@6000 {
		compatible = "fsl,sec-v4.0-rtic";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x6000 0x100>;
		ranges = <0x0 0x6100 0xe00>;
	};

=====================================================================
Run Time Integrity Check (RTIC) Memory Node
  A child node that defines individual RTIC memory regions that are used to
  perform run-time integrity check of memory areas that should not modified.
  The node defines a register that contains the memory address &
  length (combined) and a second register that contains the hash result
  in big endian format.

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-rtic-memory".

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies two parameters:
          an offset from the parent physical address and the length:

          1. The location of the RTIC memory address & length registers.
          2. The location RTIC hash result.

  - fsl,rtic-region
       Usage: optional-but-recommended
       Value type: <prop-encoded-array>
       Definition:
           Specifies the HW address (36 bit address) for this region
           followed by the length of the HW partition to be checked;
           the address is represented as a 64 bit quantity followed
           by a 32 bit length.

   - fsl,liodn
       Usage: optional-but-recommended
       Value type: <prop-encoded-array>
       Definition:
           Specifies the LIODN to be used in conjunction with
           the ppid-to-liodn table that specifies the PPID to LIODN
           mapping.  Needed if the PAMU is used.  Value is a 12 bit value
           where value is a LIODN ID for this RTIC memory region. This
           property is normally set by boot firmware.

EXAMPLE
	rtic-a@0 {
		compatible = "fsl,sec-v4.0-rtic-memory";
		reg = <0x00 0x20 0x100 0x80>;
		fsl,liodn   = <0x03c>;
		fsl,rtic-region  = <0x12345678 0x12345678 0x12345678>;
	};

=====================================================================
Secure Non-Volatile Storage (SNVS) Node

    Node defines address range and the associated
    interrupt for the SNVS function.  This function
    monitors security state information & reports
    security violations. This also included rtc,
    system power off and ON/OFF key.

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-mon" and "syscon".

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies the physical
          address and length of the SEC4 configuration
          registers.

   - #address-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing physical addresses in child nodes.  Must
           have a value of 1.

   - #size-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing the size of physical addresses in
           child nodes.  Must have a value of 1.

   - ranges
       Usage: required
       Value type: <prop-encoded-array>
       Definition: A standard property.  Specifies the physical address
           range of the SNVS register space.  A triplet that includes
           the child address, parent address, & length.

   - interrupts
      Usage: optional
      Value type: <prop_encoded-array>
      Definition:  Specifies the interrupts generated by this
           device.  The value of the interrupts property
           consists of one interrupt specifier. The format
           of the specifier is defined by the binding document
           describing the node's interrupt parent.

EXAMPLE
	sec_mon@314000 {
		compatible = "fsl,sec-v4.0-mon", "syscon";
		reg = <0x314000 0x1000>;
		ranges = <0 0x314000 0x1000>;
		interrupt-parent = <&mpic>;
		interrupts = <93 2>;
	};

=====================================================================
Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node

  A SNVS child node that defines SNVS LP RTC.

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".

  - interrupts
      Usage: required
      Value type: <prop_encoded-array>
      Definition: Specifies the interrupts generated by this
	   device.  The value of the interrupts property
	   consists of one interrupt specifier. The format
	   of the specifier is defined by the binding document
	   describing the node's interrupt parent.

 - regmap
	Usage: required
	Value type: <phandle>
	Definition: this is phandle to the register map node.

 - offset
	Usage: option
	value type: <u32>
	Definition: LP register offset. default it is 0x34.

   - clocks
      Usage: optional, required if SNVS LP RTC requires explicit
          enablement of clocks
      Value type: <prop_encoded-array>
      Definition:  a clock specifier describing the clock required for
          enabling and disabling SNVS LP RTC.

   - clock-names
      Usage: optional, required if SNVS LP RTC requires explicit
          enablement of clocks
      Value type: <string>
      Definition: clock name string should be "snvs-rtc".

EXAMPLE
	sec_mon_rtc_lp@1 {
		compatible = "fsl,sec-v4.0-mon-rtc-lp";
		interrupts = <93 2>;
		regmap = <&snvs>;
		offset = <0x34>;
		clocks = <&clks IMX7D_SNVS_CLK>;
		clock-names = "snvs-rtc";
	};

=====================================================================
System ON/OFF key driver

  The snvs-pwrkey is designed to enable POWER key function which controlled
  by SNVS ONOFF, the driver can report the status of POWER key and wakeup
  system if pressed after system suspend.

  - compatible:
      Usage: required
      Value type: <string>
      Definition: Mush include "fsl,sec-v4.0-pwrkey".

  - interrupts:
      Usage: required
      Value type: <prop_encoded-array>
      Definition: The SNVS ON/OFF interrupt number to the CPU(s).

  - linux,keycode:
      Usage: option
      Value type: <int>
      Definition: Keycode to emit, KEY_POWER by default.

  - wakeup-source:
      Usage: option
      Value type: <boo>
      Definition: Button can wake-up the system.

 - regmap:
      Usage: required:
      Value type: <phandle>
      Definition: this is phandle to the register map node.

EXAMPLE:
	snvs-pwrkey@020cc000 {
		compatible = "fsl,sec-v4.0-pwrkey";
		regmap = <&snvs>;
		interrupts = <0 4 0x4>
	        linux,keycode = <116>; /* KEY_POWER */
		wakeup-source;
	};

=====================================================================
FULL EXAMPLE

	crypto: crypto@300000 {
		compatible = "fsl,sec-v4.0";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x300000 0x10000>;
		ranges = <0 0x300000 0x10000>;
		interrupt-parent = <&mpic>;
		interrupts = <92 2>;

		sec_jr0: jr@1000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x1000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <88 2>;
		};

		sec_jr1: jr@2000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <89 2>;
		};

		sec_jr2: jr@3000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x3000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <90 2>;
		};

		sec_jr3: jr@4000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x4000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <91 2>;
		};

		rtic@6000 {
			compatible = "fsl,sec-v4.0-rtic";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x6000 0x100>;
			ranges = <0x0 0x6100 0xe00>;

			rtic_a: rtic-a@0 {
				compatible = "fsl,sec-v4.0-rtic-memory";
				reg = <0x00 0x20 0x100 0x80>;
			};

			rtic_b: rtic-b@20 {
				compatible = "fsl,sec-v4.0-rtic-memory";
				reg = <0x20 0x20 0x200 0x80>;
			};

			rtic_c: rtic-c@40 {
				compatible = "fsl,sec-v4.0-rtic-memory";
				reg = <0x40 0x20 0x300 0x80>;
			};

			rtic_d: rtic-d@60 {
				compatible = "fsl,sec-v4.0-rtic-memory";
				reg = <0x60 0x20 0x500 0x80>;
			};
		};
	};

	sec_mon: sec_mon@314000 {
		compatible = "fsl,sec-v4.0-mon";
		reg = <0x314000 0x1000>;
		ranges = <0 0x314000 0x1000>;

		sec_mon_rtc_lp@34 {
			compatible = "fsl,sec-v4.0-mon-rtc-lp";
			regmap = <&sec_mon>;
			offset = <0x34>;
			interrupts = <93 2>;
			clocks = <&clks IMX7D_SNVS_CLK>;
			clock-names = "snvs-rtc";
		};

		snvs-pwrkey@020cc000 {
			compatible = "fsl,sec-v4.0-pwrkey";
			regmap = <&sec_mon>;
			interrupts = <0 4 0x4>;
			linux,keycode = <116>; /* KEY_POWER */
			wakeup-source;
		};
	};

=====================================================================


code:
SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
Currently Freescale powerpc chip C29X is embedded with SEC 6.
SEC 6 device tree binding include:
   -SEC 6 Node
   -Job Ring Node
   -Full Example

=====================================================================
SEC 6 Node

Description

    Node defines the base address of the SEC 6 block.
    This block specifies the address range of all global
    configuration registers for the SEC 6 block.
    For example, In C293, we could see three SEC 6 node.

PROPERTIES

   - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v6.0".

   - fsl,sec-era
      Usage: optional
      Value type: <u32>
      Definition: A standard property. Define the 'ERA' of the SEC
          device.

   - #address-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing physical addresses in child nodes.

   - #size-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing the size of physical addresses in
           child nodes.

   - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies the physical
          address and length of the SEC 6 configuration registers.

   - ranges
       Usage: required
       Value type: <prop-encoded-array>
       Definition: A standard property.  Specifies the physical address
           range of the SEC 6.0 register space (-SNVS not included).  A
           triplet that includes the child address, parent address, &
           length.

   Note: All other standard properties (see the Devicetree Specification)
   are allowed but are optional.

EXAMPLE
	crypto@a0000 {
		compatible = "fsl,sec-v6.0";
		fsl,sec-era = <6>;
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0xa0000 0x20000>;
		ranges = <0 0xa0000 0x20000>;
	};

=====================================================================
Job Ring (JR) Node

    Child of the crypto node defines data processing interface to SEC 6
    across the peripheral bus for purposes of processing
    cryptographic descriptors. The specified address
    range can be made visible to one (or more) cores.
    The interrupt defined for this node is controlled within
    the address range of this node.

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v6.0-job-ring".

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: Specifies a two JR parameters:  an offset from
           the parent physical address and the length the JR registers.

   - interrupts
      Usage: required
      Value type: <prop_encoded-array>
      Definition:  Specifies the interrupts generated by this
           device.  The value of the interrupts property
           consists of one interrupt specifier. The format
           of the specifier is defined by the binding document
           describing the node's interrupt parent.

EXAMPLE
	jr@1000 {
		compatible = "fsl,sec-v6.0-job-ring";
		reg = <0x1000 0x1000>;
		interrupts = <49 2 0 0>;
	};

===================================================================
Full Example

Since some chips may contain more than one SEC, the dtsi contains
only the node contents, not the node itself.  A chip using the SEC
should include the dtsi inside each SEC node.  Example:

In qoriq-sec6.0.dtsi:

	compatible = "fsl,sec-v6.0";
	fsl,sec-era = <6>;
	#address-cells = <1>;
	#size-cells = <1>;

	jr@1000 {
		compatible = "fsl,sec-v6.0-job-ring",
			     "fsl,sec-v5.2-job-ring",
			     "fsl,sec-v5.0-job-ring",
			     "fsl,sec-v4.4-job-ring",
			     "fsl,sec-v4.0-job-ring";
		reg	   = <0x1000 0x1000>;
	};

	jr@2000 {
		compatible = "fsl,sec-v6.0-job-ring",
			     "fsl,sec-v5.2-job-ring",
			     "fsl,sec-v5.0-job-ring",
			     "fsl,sec-v4.4-job-ring",
			     "fsl,sec-v4.0-job-ring";
		reg	   = <0x2000 0x1000>;
	};

In the C293 device tree, we add the include of public property:

	crypto@a0000 {
		/include/ "qoriq-sec6.0.dtsi"
	}

	crypto@a0000 {
		reg = <0xa0000 0x20000>;
		ranges = <0 0xa0000 0x20000>;

		jr@1000 {
			interrupts = <49 2 0 0>;
		};

		jr@2000 {
			interrupts = <50 2 0 0>;
		};
	};

repo_name: angery/linux


code:
* Hisilicon hip07 Security Accelerator (SEC)

Required properties:
- compatible: Must contain one of
  - "hisilicon,hip06-sec"
  - "hisilicon,hip07-sec"
- reg: Memory addresses and lengths of the memory regions through which
  this device is controlled.
  Region 0 has registers to control the backend processing engines.
  Region 1 has registers for functionality common to all queues.
  Regions 2-18 have registers for the 16 individual queues which are isolated
  both in hardware and within the driver.
- interrupts: Interrupt specifiers.
  Refer to interrupt-controller/interrupts.txt for generic interrupt client node
  bindings.
  Interrupt 0 is for the SEC unit error queue.
  Interrupt 2N + 1 is the completion interrupt for queue N.
  Interrupt 2N + 2 is the error interrupt for queue N.
- dma-coherent:  The driver assumes coherent dma is possible.

Optional properties:
- iommus: The SEC units are behind smmu-v3 iommus.
  Refer to iommu/arm,smmu-v3.txt for more information.

Example:

p1_sec_a: crypto@400d2000000 {
	compatible = "hisilicon,hip07-sec";
	reg = <0x400 0xd0000000 0x0 0x10000
	       0x400 0xd2000000 0x0 0x10000
	       0x400 0xd2010000 0x0 0x10000
	       0x400 0xd2020000 0x0 0x10000
	       0x400 0xd2030000 0x0 0x10000
	       0x400 0xd2040000 0x0 0x10000
	       0x400 0xd2050000 0x0 0x10000
	       0x400 0xd2060000 0x0 0x10000
	       0x400 0xd2070000 0x0 0x10000
	       0x400 0xd2080000 0x0 0x10000
	       0x400 0xd2090000 0x0 0x10000
	       0x400 0xd20a0000 0x0 0x10000
	       0x400 0xd20b0000 0x0 0x10000
	       0x400 0xd20c0000 0x0 0x10000
	       0x400 0xd20d0000 0x0 0x10000
	       0x400 0xd20e0000 0x0 0x10000
	       0x400 0xd20f0000 0x0 0x10000
	       0x400 0xd2100000 0x0 0x10000>;
	interrupt-parent = <&p1_mbigen_sec_a>;
	iommus = <&p1_smmu_alg_a 0x600>;
	dma-coherent;
	interrupts = <576 4>,
		     <577 1>, <578 4>,
		     <579 1>, <580 4>,
		     <581 1>, <582 4>,
		     <583 1>, <584 4>,
		     <585 1>, <586 4>,
		     <587 1>, <588 4>,
		     <589 1>, <590 4>,
		     <591 1>, <592 4>,
		     <593 1>, <594 4>,
		     <595 1>, <596 4>,
		     <597 1>, <598 4>,
		     <599 1>, <600 4>,
		     <601 1>, <602 4>,
		     <603 1>, <604 4>,
		     <605 1>, <606 4>,
		     <607 1>, <608 4>;
};


code:
Imagination Technologies hardware hash accelerator

The hash accelerator provides hardware hashing acceleration for
SHA1, SHA224, SHA256 and MD5 hashes

Required properties:

- compatible : "img,hash-accelerator"
- reg : Offset and length of the register set for the module, and the DMA port
- interrupts : The designated IRQ line for the hashing module.
- dmas : DMA specifier as per Documentation/devicetree/bindings/dma/dma.txt
- dma-names : Should be "tx"
- clocks : Clock specifiers
- clock-names : "sys" Used to clock the hash block registers
		"hash" Used to clock data through the accelerator

Example:

	hash: hash@18149600 {
	compatible = "img,hash-accelerator";
		reg = <0x18149600 0x100>, <0x18101100 0x4>;
		interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
		dmas = <&dma 8 0xffffffff 0>;
		dma-names = "tx";
		clocks = <&cr_periph SYS_CLK_HASH>, <&clk_periph PERIPH_CLK_ROM>;
		clock-names = "sys", "hash";
	};


code:
Inside Secure SafeXcel cryptographic engine

Required properties:
- compatible: Should be "inside-secure,safexcel-eip197b",
	      "inside-secure,safexcel-eip197d" or
              "inside-secure,safexcel-eip97ies".
- reg: Base physical address of the engine and length of memory mapped region.
- interrupts: Interrupt numbers for the rings and engine.
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".

Optional properties:
- clocks: Reference to the crypto engine clocks, the second clock is
          needed for the Armada 7K/8K SoCs.
- clock-names: mandatory if there is a second clock, in this case the
               name must be "core" for the first clock and "reg" for
               the second one.

Backward compatibility:
Two compatibles are kept for backward compatibility, but shouldn't be used for
new submissions:
- "inside-secure,safexcel-eip197" is equivalent to
  "inside-secure,safexcel-eip197b".
- "inside-secure,safexcel-eip97" is equivalent to
  "inside-secure,safexcel-eip97ies".

Example:

	crypto: crypto@800000 {
		compatible = "inside-secure,safexcel-eip197b";
		reg = <0x800000 0x200000>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
				  "eip";
		clocks = <&cpm_syscon0 1 26>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel IXP4xx cryptographic engine

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
  (Network Processing Engine). Since it is not a device on its own
  it is defined as a subnode of the NPE, if crypto support is
  available on the platform.

properties:
  compatible:
    const: intel,ixp4xx-crypto

  intel,npe-handle:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    items:
      - items:
          - description: phandle to the NPE this crypto engine
          - description: the NPE instance number
    description: phandle to the NPE this crypto engine is using, the cell
      describing the NPE instance to be used.

  queue-rx:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to the RX queue on the NPE
          - description: the queue instance number
    description: phandle to the RX queue on the NPE, the cell describing
      the queue instance to be used.

  queue-txready:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to the TX READY queue on the NPE
          - description: the queue instance number
    description: phandle to the TX READY queue on the NPE, the cell describing
      the queue instance to be used.

required:
  - compatible
  - intel,npe-handle
  - queue-rx
  - queue-txready

additionalProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-aes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Keem Bay OCS AES

maintainers:
  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>

description:
  The Intel Keem Bay Offload and Crypto Subsystem (OCS) AES engine provides
  hardware-accelerated AES/SM4 encryption/decryption.

properties:
  compatible:
    const: intel,keembay-ocs-aes

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    crypto@30008000 {
      compatible = "intel,keembay-ocs-aes";
      reg = <0x30008000 0x1000>;
      interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&scmi_clk 95>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-ecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Keem Bay OCS ECC

maintainers:
  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
  - Prabhjot Khurana <prabhjot.khurana@intel.com>

description:
  The Intel Keem Bay Offload and Crypto Subsystem (OCS) Elliptic Curve
  Cryptography (ECC) device provides hardware acceleration for elliptic curve
  cryptography using the NIST P-256 and NIST P-384 elliptic curves.

properties:
  compatible:
    const: intel,keembay-ocs-ecc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    crypto@30001000 {
      compatible = "intel,keembay-ocs-ecc";
      reg = <0x30001000 0x1000>;
      interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&scmi_clk 95>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-hcu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Keem Bay OCS HCU

maintainers:
  - Declan Murphy <declan.murphy@intel.com>
  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>

description:
  The Intel Keem Bay Offload and Crypto Subsystem (OCS) Hash Control Unit (HCU)
  provides hardware-accelerated hashing and HMAC.

properties:
  compatible:
    const: intel,keembay-ocs-hcu

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    crypto@3000b000 {
      compatible = "intel,keembay-ocs-hcu";
      reg = <0x3000b000 0x1000>;
      interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&scmi_clk 94>;
    };


code:
Marvell Cryptographic Engines And Security Accelerator

Required properties:
- compatible: should be one of the following string
	      "marvell,orion-crypto"
	      "marvell,kirkwood-crypto"
	      "marvell,dove-crypto"
	      "marvell,armada-370-crypto"
	      "marvell,armada-xp-crypto"
	      "marvell,armada-375-crypto"
	      "marvell,armada-38x-crypto"
- reg: base physical address of the engine and length of memory mapped
       region. Can also contain an entry for the SRAM attached to the CESA,
       but this representation is deprecated and marvell,crypto-srams should
       be used instead
- reg-names: "regs". Can contain an "sram" entry, but this representation
	     is deprecated and marvell,crypto-srams should be used instead
- interrupts: interrupt number
- clocks: reference to the crypto engines clocks. This property is not
	  required for orion and kirkwood platforms
- clock-names: "cesaX" and "cesazX", X should be replaced by the crypto engine
	       id.
	       This property is not required for the orion and kirkwoord
	       platforms.
	       "cesazX" clocks are not required on armada-370 platforms
- marvell,crypto-srams: phandle to crypto SRAM definitions

Optional properties:
- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
			    specified the whole SRAM is used (2KB)

Examples:

	crypto@90000 {
		compatible = "marvell,armada-xp-crypto";
		reg = <0x90000 0x10000>;
		reg-names = "regs";
		interrupts = <48>, <49>;
		clocks = <&gateclk 23>, <&gateclk 23>;
		clock-names = "cesa0", "cesa1";
		marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>;
		marvell,crypto-sram-size = <0x600>;
	};


code:
MediaTek cryptographic accelerators

Required properties:
- compatible: Should be "mediatek,eip97-crypto"
- reg: Address and length of the register set for the device
- interrupts: Should contain the five crypto engines interrupts in numeric
	order. These are global system and four descriptor rings.
- clocks: the clock used by the core
- clock-names: Must contain "cryp".
- power-domains: Must contain a reference to the PM domain.

Example:
	crypto: crypto@1b240000 {
		compatible = "mediatek,eip97-crypto";
		reg = <0 0x1b240000 0 0x20000>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
		clock-names = "cryp";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
	};


code:
Marvell Cryptographic Engines And Security Accelerator

Required properties:
- compatible: should be one of the following string
	      "marvell,orion-crypto"
	      "marvell,kirkwood-crypto"
	      "marvell,dove-crypto"
- reg: base physical address of the engine and length of memory mapped
       region. Can also contain an entry for the SRAM attached to the CESA,
       but this representation is deprecated and marvell,crypto-srams should
       be used instead
- reg-names: "regs". Can contain an "sram" entry, but this representation
	     is deprecated and marvell,crypto-srams should be used instead
- interrupts: interrupt number
- clocks: reference to the crypto engines clocks. This property is only
	  required for Dove platforms
- marvell,crypto-srams: phandle to crypto SRAM definitions

Optional properties:
- marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
			    specified the whole SRAM is used (2KB)

Examples:

	crypto@30000 {
		compatible = "marvell,orion-crypto";
		reg = <0x30000 0x10000>;
		reg-names = "regs";
		interrupts = <22>;
		marvell,crypto-srams = <&crypto_sram>;
		marvell,crypto-sram-size = <0x600>;
	};


code:
OMAP SoC AES crypto Module

Required properties:

- compatible : Should contain entries for this and backward compatible
  AES versions:
  - "ti,omap2-aes" for OMAP2.
  - "ti,omap3-aes" for OMAP3.
  - "ti,omap4-aes" for OMAP4 and AM33XX.
  Note that the OMAP2 and 3 versions are compatible (OMAP3 supports
  more algorithms) but they are incompatible with OMAP4.
- ti,hwmods: Name of the hwmod associated with the AES module
- reg : Offset and length of the register set for the module
- interrupts : the interrupt-specifier for the AES module.

Optional properties:
- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
	Documentation/devicetree/bindings/dma/dma.txt
- dma-names: DMA request names should include "tx" and "rx" if present.

Example:
	/* AM335x */
	aes: aes@53500000 {
		compatible = "ti,omap4-aes";
		ti,hwmods = "aes";
		reg = <0x53500000 0xa0>;
		interrupts = <102>;
		dmas = <&edma 6>,
		       <&edma 5>;
		dma-names = "tx", "rx";
	};


code:
OMAP SoC DES crypto Module

Required properties:

- compatible : Should contain "ti,omap4-des"
- ti,hwmods: Name of the hwmod associated with the DES module
- reg : Offset and length of the register set for the module
- interrupts : the interrupt-specifier for the DES module
- clocks : A phandle to the functional clock node of the DES module
           corresponding to each entry in clock-names
- clock-names : Name of the functional clock, should be "fck"

Optional properties:
- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
	Documentation/devicetree/bindings/dma/dma.txt
	Each entry corresponds to an entry in dma-names
- dma-names: DMA request names should include "tx" and "rx" if present

Example:
	/* DRA7xx SoC */
	des: des@480a5000 {
		compatible = "ti,omap4-des";
		ti,hwmods = "des";
		reg = <0x480a5000 0xa0>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		dmas = <&sdma 117>, <&sdma 116>;
		dma-names = "tx", "rx";
		clocks = <&l3_iclk_div>;
		clock-names = "fck";
	};


code:
OMAP SoC SHA crypto Module

Required properties:

- compatible : Should contain entries for this and backward compatible
  SHAM versions:
  - "ti,omap2-sham" for OMAP2 & OMAP3.
  - "ti,omap4-sham" for OMAP4 and AM33XX.
  - "ti,omap5-sham" for OMAP5, DRA7 and AM43XX.
- ti,hwmods: Name of the hwmod associated with the SHAM module
- reg : Offset and length of the register set for the module
- interrupts : the interrupt-specifier for the SHAM module.

Optional properties:
- dmas: DMA specifiers for the rx dma. See the DMA client binding,
	Documentation/devicetree/bindings/dma/dma.txt
- dma-names: DMA request name. Should be "rx" if a dma is present.

Example:
	/* AM335x */
	sham: sham@53100000 {
		compatible = "ti,omap4-sham";
		ti,hwmods = "sham";
		reg = <0x53100000 0x200>;
		interrupts = <109>;
		dmas = <&edma 36>;
		dma-names = "rx";
	};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/qcom,prng.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Pseudo Random Number Generator

maintainers:
  - Vinod Koul <vkoul@kernel.org>

properties:
  compatible:
    enum:
      - qcom,prng  # 8916 etc.
      - qcom,prng-ee  # 8996 and later using EE

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: core

required:
  - compatible
  - reg
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    rng@f9bff000 {
        compatible = "qcom,prng";
        reg = <0xf9bff000 0x200>;
        clocks = <&clk 125>;
        clock-names = "core";
    };


code:
Qualcomm crypto engine driver

Required properties:

- compatible  : should be "qcom,crypto-v5.1"
- reg         : specifies base physical address and size of the registers map
- clocks      : phandle to clock-controller plus clock-specifier pair
- clock-names : "iface" clocks register interface
                "bus" clocks data transfer interface
                "core" clocks rest of the crypto block
- dmas        : DMA specifiers for tx and rx dma channels. For more see
                Documentation/devicetree/bindings/dma/dma.txt
- dma-names   : DMA request names should be "rx" and "tx"

Example:
	crypto@fd45a000 {
		compatible = "qcom,crypto-v5.1";
		reg = <0xfd45a000 0x6000>;
		clocks = <&gcc GCC_CE2_AHB_CLK>,
			 <&gcc GCC_CE2_AXI_CLK>,
			 <&gcc GCC_CE2_CLK>;
		clock-names = "iface", "bus", "core";
		dmas = <&cryptobam 2>, <&cryptobam 3>;
		dma-names = "rx", "tx";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/rockchip,rk3288-crypto.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip Electronics Security Accelerator

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    enum:
      - rockchip,rk3288-crypto
      - rockchip,rk3328-crypto
      - rockchip,rk3399-crypto

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    maxItems: 4

  clock-names:
    minItems: 3
    maxItems: 4

  resets:
    minItems: 1
    maxItems: 3

  reset-names:
    minItems: 1
    maxItems: 3

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: rockchip,rk3288-crypto
    then:
      properties:
        clocks:
          minItems: 4
        clock-names:
          items:
            - const: aclk
            - const: hclk
            - const: sclk
            - const: apb_pclk
        resets:
          maxItems: 1
        reset-names:
          items:
            - const: crypto-rst
  - if:
      properties:
        compatible:
          contains:
            const: rockchip,rk3328-crypto
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          items:
            - const: hclk_master
            - const: hclk_slave
            - const: sclk
        resets:
          maxItems: 1
        reset-names:
          items:
            - const: crypto-rst
  - if:
      properties:
        compatible:
          contains:
            const: rockchip,rk3399-crypto
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          items:
            - const: hclk_master
            - const: hclk_slave
            - const: sclk
        resets:
          minItems: 3
        reset-names:
          items:
            - const: master
            - const: slave
            - const: crypto-rst

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/rk3288-cru.h>
    crypto@ff8a0000 {
      compatible = "rockchip,rk3288-crypto";
      reg = <0xff8a0000 0x4000>;
      interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
               <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
      clock-names = "aclk", "hclk", "sclk", "apb_pclk";
      resets = <&cru SRST_CRYPTO>;
      reset-names = "crypto-rst";
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/samsung-slimsss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC SlimSSS (Slim Security SubSystem) module

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |+
  The SlimSSS module in Exynos5433 SoC supports the following:
  -- Feeder (FeedCtrl)
  -- Advanced Encryption Standard (AES) with ECB,CBC,CTR,XTS and (CBC/XTS)/CTS
  -- SHA-1/SHA-256 and (SHA-1/SHA-256)/HMAC

properties:
  compatible:
    items:
      - const: samsung,exynos5433-slim-sss

  reg:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: pclk
      - const: aclk

  interrupts:
    description: One feed control interrupt.
    maxItems: 1

required:
  - compatible
  - reg
  - clock-names
  - clocks
  - interrupts

additionalProperties: false


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/samsung-sss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC SSS (Security SubSystem) module

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |+
  The SSS module in S5PV210 SoC supports the following:
  -- Feeder (FeedCtrl)
  -- Advanced Encryption Standard (AES)
  -- Data Encryption Standard (DES)/3DES
  -- Public Key Accelerator (PKA)
  -- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
  -- PRNG: Pseudo Random Number Generator

  The SSS module in Exynos4 (Exynos4210) and Exynos5 (Exynos5420 and Exynos5250)
  SoCs supports the following also:
  -- ARCFOUR (ARC4)
  -- True Random Number Generator (TRNG)
  -- Secure Key Manager

properties:
  compatible:
    items:
      - enum:
          - samsung,s5pv210-secss           # for S5PV210
          - samsung,exynos4210-secss        # for Exynos4210, Exynos4212,
                                            # Exynos4412, Exynos5250,
                                            # Exynos5260 and Exynos5420

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: secss

  interrupts:
    description: One feed control interrupt.
    maxItems: 1

required:
  - compatible
  - reg
  - clock-names
  - clocks
  - interrupts

additionalProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/st,stm32-crc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 CRC bindings

maintainers:
  - Lionel Debieve <lionel.debieve@foss.st.com>

properties:
  compatible:
    const: st,stm32f7-crc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/stm32mp1-clks.h>
    crc@40023000 {
      compatible = "st,stm32f7-crc";
      reg = <0x40023000 0x400>;
      clocks = <&rcc 0 12>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/st,stm32-cryp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 CRYP bindings

description: The STM32 CRYP block is built on the CRYP block found in
  the STn8820 SoC introduced in 2007, and subsequently used in the U8500
  SoC in 2010.

maintainers:
  - Lionel Debieve <lionel.debieve@foss.st.com>

properties:
  compatible:
    enum:
      - st,stn8820-cryp
      - stericsson,ux500-cryp
      - st,stm32f756-cryp
      - st,stm32mp1-cryp

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  resets:
    maxItems: 1

  dmas:
    items:
      - description: mem2cryp DMA channel
      - description: cryp2mem DMA channel

  dma-names:
    items:
      - const: mem2cryp
      - const: cryp2mem

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    cryp@54001000 {
      compatible = "st,stm32mp1-cryp";
      reg = <0x54001000 0x400>;
      interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&rcc CRYP1>;
      resets = <&rcc CRYP1_R>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/st,stm32-hash.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 HASH bindings

maintainers:
  - Lionel Debieve <lionel.debieve@foss.st.com>

properties:
  compatible:
    enum:
      - st,stm32f456-hash
      - st,stm32f756-hash

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  resets:
    maxItems: 1

  dmas:
    maxItems: 1

  dma-names:
    items:
      - const: in

  dma-maxburst:
    description: Set number of maximum dma burst supported
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 2
    default: 0

required:
  - compatible
  - reg
  - clocks
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    hash@54002000 {
      compatible = "st,stm32f756-hash";
      reg = <0x54002000 0x400>;
      interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&rcc HASH1>;
      resets = <&rcc HASH1_R>;
      dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
      dma-names = "in";
      dma-maxburst = <2>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/ti,sa2ul.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: K3 SoC SA2UL crypto module

maintainers:
  - Tero Kristo <t-kristo@ti.com>

properties:
  compatible:
    enum:
      - ti,j721e-sa2ul
      - ti,am654-sa2ul
      - ti,am64-sa2ul
      - ti,am62-sa3ul

  reg:
    maxItems: 1

  power-domains:
    maxItems: 1

  dmas:
    items:
      - description: TX DMA Channel
      - description: RX DMA Channel #1
      - description: RX DMA Channel #2

  dma-names:
    items:
      - const: tx
      - const: rx1
      - const: rx2

  "#address-cells":
    const: 2

  "#size-cells":
    const: 2

  ranges:
    description:
      Address translation for the possible RNG child node for SA2UL

  clocks:
    items:
      - description: Clock used by PKA
      - description: Main Input Clock
      - description: Clock used by rng

  clock-names:
    items:
      - const: pka_in_clk
      - const: x1_clk
      - const: x2_clk

patternProperties:
  "^rng@[a-f0-9]+$":
    type: object
    description:
      Child RNG node for SA2UL

required:
  - compatible
  - reg
  - power-domains
  - dmas
  - dma-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    main_crypto: crypto@4e00000 {
        compatible = "ti,j721e-sa2ul";
        reg = <0x4e00000 0x1200>;
        power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
        dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
               <&main_udmap 0x4001>;
        dma-names = "tx", "rx1", "rx2";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx ZynqMP AES-GCM Hardware Accelerator

maintainers:
  - Kalyani Akula <kalyani.akula@xilinx.com>
  - Michal Simek <michal.simek@xilinx.com>

description: |
  The ZynqMP AES-GCM hardened cryptographic accelerator is used to
  encrypt or decrypt the data with provided key and initialization vector.

properties:
  compatible:
    const: xlnx,zynqmp-aes

required:
  - compatible

additionalProperties: false

examples:
  - |
    firmware {
      zynqmp_firmware: zynqmp-firmware {
        compatible = "xlnx,zynqmp-firmware";
        method = "smc";
        xlnx_aes: zynqmp-aes {
          compatible = "xlnx,zynqmp-aes";
        };
      };
    };
...


code:
==================
C-SKY CPU Bindings
==================

The device tree allows to describe the layout of CPUs in a system through
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
defining properties for every cpu.

Only SMP system need to care about the cpus node and single processor
needn't define cpus node at all.

=====================================
cpus and cpu node bindings definition
=====================================

- cpus node

	Description: Container of cpu nodes

	The node name must be "cpus".

	A cpus node must define the following properties:

	- #address-cells
		Usage: required
		Value type: <u32>
		Definition: must be set to 1
	- #size-cells
		Usage: required
		Value type: <u32>
		Definition: must be set to 0

- cpu node

	Description: Describes one of SMP cores

	PROPERTIES

	- device_type
		Usage: required
		Value type: <string>
		Definition: must be "cpu"
	- reg
		Usage: required
		Value type: <u32>
		Definition: CPU index
	- compatible:
		Usage: required
		Value type: <string>
		Definition: must contain "csky", eg:
			"csky,610"
			"csky,807"
			"csky,810"
			"csky,860"

Example:
--------

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			reg = <0>;
			status = "ok";
		};

		cpu@1 {
			device_type = "cpu";
			reg = <1>;
			status = "ok";
		};
	};


code:
===============================
C-SKY Performance Monitor Units
===============================

C-SKY Performance Monitor is designed for ck807/ck810/ck860 SMP soc and
it could count cpu's events for helping analysis performance issues.

============================
PMU node bindings definition
============================

	Description: Describes PMU

	PROPERTIES

	- compatible
		Usage: required
		Value type: <string>
		Definition: must be "csky,csky-pmu"
	- interrupts
		Usage: required
		Value type: <u32 IRQ_TYPE_XXX>
		Definition: must be pmu irq num defined by soc
	- count-width
		Usage: optional
		Value type: <u32>
		Definition: the width of pmu counter

Examples:
---------
#include <dt-bindings/interrupt-controller/irq.h>

	pmu: performace-monitor {
		compatible = "csky,csky-pmu";
		interrupts = <23 IRQ_TYPE_EDGE_RISING>;
		interrupt-parent = <&intc>;
		count-width = <48>;
        };


code:
* Rockchip rk3399 DFI device

Required properties:
- compatible: Must be "rockchip,rk3399-dfi".
- reg: physical base address of each DFI and length of memory mapped region
- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
- clocks: phandles for clock specified in "clock-names" property
- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";

Example:
	dfi: dfi@ff630000 {
		compatible = "rockchip,rk3399-dfi";
		reg = <0x00 0xff630000 0x00 0x4000>;
		rockchip,pmu = <&pmugrf>;
		clocks = <&cru PCLK_DDR_MON>;
		clock-names = "pclk_ddr_mon";
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-nocp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos NoC (Network on Chip) Probe

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.
  NoC provides the primitive values to get the performance data. The packets
  that the Network on Chip (NoC) probes detects are transported over the
  network infrastructure to observer units. You can configure probes to capture
  packets with header or data on the data request response network, or as
  traffic debug or statistic collectors. Exynos542x bus has multiple NoC probes
  to provide bandwidth information about behavior of the SoC that you can use
  while analyzing system performance.

properties:
  compatible:
    const: samsung,exynos5420-nocp

  clock-names:
    items:
      - const: nocp

  clocks:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    nocp_mem0_0: nocp@10ca1000 {
        compatible = "samsung,exynos5420-nocp";
        reg = <0x10ca1000 0x200>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-ppmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit)

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for
  each IP. PPMU provides the primitive values to get performance data. These
  PPMU events provide information of the SoC's behaviors so that you may use to
  analyze system performance, to make behaviors visible and to count usages of
  each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC).  The
  Exynos PPMU driver uses the devfreq-event class to provide event data to
  various devfreq devices. The devfreq devices would use the event data when
  derterming the current state of each IP.

properties:
  compatible:
    enum:
      - samsung,exynos-ppmu
      - samsung,exynos-ppmu-v2

  clock-names:
    items:
      - const: ppmu

  clocks:
    maxItems: 1

  reg:
    maxItems: 1

  events:
    type: object

    patternProperties:
      '^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':
        type: object
        properties:
          event-name:
            description: |
              The unique event name among PPMU device
            $ref: /schemas/types.yaml#/definitions/string

          event-data-type:
            description: |
              Define the type of data which shell be counted by the counter.
              You can check include/dt-bindings/pmu/exynos_ppmu.h for all
              possible type, i.e. count read requests, count write data in
              bytes, etc.  This field is optional and when it is missing, the
              driver code will use default data type.
            $ref: /schemas/types.yaml#/definitions/uint32

        required:
          - event-name

        additionalProperties: false

    additionalProperties: false

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    // PPMUv1 nodes for Exynos3250 (although the board DTS defines events)
    #include <dt-bindings/clock/exynos3250.h>

    ppmu_dmc0: ppmu@106a0000 {
        compatible = "samsung,exynos-ppmu";
        reg = <0x106a0000 0x2000>;

        events {
            ppmu_dmc0_3: ppmu-event3-dmc0 {
                event-name = "ppmu-event3-dmc0";
            };

            ppmu_dmc0_2: ppmu-event2-dmc0 {
                event-name = "ppmu-event2-dmc0";
            };

            ppmu_dmc0_1: ppmu-event1-dmc0 {
                event-name = "ppmu-event1-dmc0";
            };

            ppmu_dmc0_0: ppmu-event0-dmc0 {
                event-name = "ppmu-event0-dmc0";
            };
        };
    };

    ppmu_rightbus: ppmu@112a0000 {
        compatible = "samsung,exynos-ppmu";
        reg = <0x112a0000 0x2000>;
        clocks = <&cmu CLK_PPMURIGHT>;
        clock-names = "ppmu";

        events {
            ppmu_rightbus_3: ppmu-event3-rightbus {
                event-name = "ppmu-event3-rightbus";
            };
        };
    };

  - |
    // PPMUv2 nodes in Exynos5433
    ppmu_d0_cpu: ppmu@10480000 {
        compatible = "samsung,exynos-ppmu-v2";
        reg = <0x10480000 0x2000>;
    };

    ppmu_d0_general: ppmu@10490000 {
        compatible = "samsung,exynos-ppmu-v2";
        reg = <0x10490000 0x2000>;

        events {
            ppmu_event0_d0_general: ppmu-event0-d0-general {
                event-name = "ppmu-event0-d0-general";
            };
        };
    };

    ppmu_d0_rt: ppmu@104a0000 {
        compatible = "samsung,exynos-ppmu-v2";
        reg = <0x104a0000 0x2000>;
    };

    ppmu_d1_cpu: ppmu@104b0000 {
        compatible = "samsung,exynos-ppmu-v2";
        reg = <0x104b0000 0x2000>;
    };

    ppmu_d1_general: ppmu@104c0000 {
        compatible = "samsung,exynos-ppmu-v2";
        reg = <0x104c0000 0x2000>;
    };

    ppmu_d1_rt: ppmu@104d0000 {
        compatible = "samsung,exynos-ppmu-v2";
        reg = <0x104d0000 0x2000>;
    };

  - |
    // PPMUv1 nodes with event-data-type for Exynos4412
    #include <dt-bindings/pmu/exynos_ppmu.h>

    ppmu@106a0000 {
        compatible = "samsung,exynos-ppmu";
        reg = <0x106a0000 0x2000>;
        clocks = <&clock 400>;
        clock-names = "ppmu";

        events {
            ppmu-event3-dmc0 {
                event-name = "ppmu-event3-dmc0";
                event-data-type = <(PPMU_RO_DATA_CNT |
                                    PPMU_WO_DATA_CNT)>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra30 Activity Monitor

maintainers:
  - Dmitry Osipenko <digetx@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  The activity monitor block collects statistics about the behaviour of other
  components in the system. This information can be used to derive the rate at
  which the external memory needs to be clocked in order to serve all requests
  from the monitored clients.

properties:
  compatible:
    enum:
      - nvidia,tegra30-actmon
      - nvidia,tegra114-actmon
      - nvidia,tegra124-actmon
      - nvidia,tegra210-actmon

  reg:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: actmon
      - const: emc

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: actmon

  interrupts:
    maxItems: 1

  interconnects:
    minItems: 1
    maxItems: 12

  interconnect-names:
    minItems: 1
    maxItems: 12
    description:
      Should include name of the interconnect path for each interconnect
      entry. Consult TRM documentation for information about available
      memory clients, see MEMORY CONTROLLER and ACTIVITY MONITOR sections.

  operating-points-v2:
    description:
      Should contain freqs and voltages and opp-supported-hw property, which
      is a bitfield indicating SoC speedo ID mask.

  "#cooling-cells":
    const: 2

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - interrupts
  - interconnects
  - interconnect-names
  - operating-points-v2
  - "#cooling-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/memory/tegra30-mc.h>

    mc: memory-controller@7000f000 {
        compatible = "nvidia,tegra30-mc";
        reg = <0x7000f000 0x400>;
        clocks = <&clk 32>;
        clock-names = "mc";

        interrupts = <0 77 4>;

        #iommu-cells = <1>;
        #reset-cells = <1>;
        #interconnect-cells = <1>;
    };

    emc: external-memory-controller@7000f400 {
        compatible = "nvidia,tegra30-emc";
        reg = <0x7000f400 0x400>;
        interrupts = <0 78 4>;
        clocks = <&clk 57>;

        nvidia,memory-controller = <&mc>;
        operating-points-v2 = <&dvfs_opp_table>;
        power-domains = <&domain>;

        #interconnect-cells = <0>;
    };

    actmon@6000c800 {
        compatible = "nvidia,tegra30-actmon";
        reg = <0x6000c800 0x400>;
        interrupts = <0 45 4>;
        clocks = <&clk 119>, <&clk 57>;
        clock-names = "actmon", "emc";
        resets = <&rst 119>;
        reset-names = "actmon";
        operating-points-v2 = <&dvfs_opp_table>;
        interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
        interconnect-names = "cpu-read";
        #cooling-cells = <2>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 Display Engine Backend

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |
  The display engine backend exposes layers and sprites to the system.

properties:
  compatible:
    enum:
      - allwinner,sun4i-a10-display-backend
      - allwinner,sun5i-a13-display-backend
      - allwinner,sun6i-a31-display-backend
      - allwinner,sun7i-a20-display-backend
      - allwinner,sun8i-a23-display-backend
      - allwinner,sun8i-a33-display-backend
      - allwinner,sun9i-a80-display-backend

  reg:
    minItems: 1
    items:
      - description: Display Backend registers
      - description: SAT registers

  reg-names:
    minItems: 1
    items:
      - const: be
      - const: sat

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    items:
      - description: The backend interface clock
      - description: The backend module clock
      - description: The backend DRAM clock
      - description: The SAT clock

  clock-names:
    minItems: 3
    items:
      - const: ahb
      - const: mod
      - const: ram
      - const: sat

  resets:
    minItems: 1
    items:
      - description: The Backend reset line
      - description: The SAT reset line

  reset-names:
    minItems: 1
    items:
      - const: be
      - const: sat

  # FIXME: This should be made required eventually once every SoC will
  # have the MBUS declared.
  interconnects:
    maxItems: 1

  # FIXME: This should be made required eventually once every SoC will
  # have the MBUS declared.
  interconnect-names:
    const: dma-mem

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Input endpoints of the controller.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Output endpoints of the controller.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - ports

additionalProperties: false

if:
  properties:
    compatible:
      contains:
        const: allwinner,sun8i-a33-display-backend

then:
  properties:
    reg:
      minItems: 2

    reg-names:
      minItems: 2

    clocks:
      minItems: 4

    clock-names:
      minItems: 4

    resets:
      minItems: 2

    reset-names:
      minItems: 2

  required:
    - reg-names
    - reset-names

else:
  properties:
    reg:
      maxItems: 1

    reg-names:
      maxItems: 1

    clocks:
      maxItems: 3

    clock-names:
      maxItems: 3

    resets:
      maxItems: 1

    reset-names:
      maxItems: 1

examples:
  - |
    /*
     * This comes from the clock/sun4i-a10-ccu.h and
     * reset/sun4i-a10-ccu.h headers, but we can't include them since
     * it would trigger a bunch of warnings for redefinitions of
     * symbols with the other example.
     */

    #define CLK_AHB_DE_BE0	42
    #define CLK_DRAM_DE_BE0	140
    #define CLK_DE_BE0		144
    #define RST_DE_BE0		5

    display-backend@1e60000 {
        compatible = "allwinner,sun4i-a10-display-backend";
        reg = <0x01e60000 0x10000>;
        interrupts = <47>;
        clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
                 <&ccu CLK_DRAM_DE_BE0>;
        clock-names = "ahb", "mod",
                      "ram";
        resets = <&ccu RST_DE_BE0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;

                endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&fe0_out_be0>;
                };

                endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&fe1_out_be0>;
                };
            };

            port@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;

                endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&tcon0_in_be0>;
                };

                endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&tcon1_in_be0>;
                };
            };
        };
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    /*
     * This comes from the clock/sun8i-a23-a33-ccu.h and
     * reset/sun8i-a23-a33-ccu.h headers, but we can't include them
     * since it would trigger a bunch of warnings for redefinitions of
     * symbols with the other example.
     */

    #define CLK_BUS_DE_BE	40
    #define CLK_BUS_SAT		46
    #define CLK_DRAM_DE_BE	84
    #define CLK_DE_BE		85
    #define RST_BUS_DE_BE	21
    #define RST_BUS_SAT		27

    display-backend@1e60000 {
        compatible = "allwinner,sun8i-a33-display-backend";
        reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
        reg-names = "be", "sat";
        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
                 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
        clock-names = "ahb", "mod",
                      "ram", "sat";
        resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
        reset-names = "be", "sat";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                endpoint {
                    remote-endpoint = <&fe0_out_be0>;
                };
            };

            port@1 {
                reg = <1>;

                endpoint {
                    remote-endpoint = <&drc0_in_be0>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 Display Engine Pipeline

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |
  The display engine pipeline (and its entry point, since it can be
  either directly the backend or the frontend) is represented as an
  extra node.

  The Allwinner A10 Display pipeline is composed of several components
  that are going to be documented below:

  For all connections between components up to the TCONs in the
  display pipeline, when there are multiple components of the same
  type at the same depth, the local endpoint ID must be the same as
  the remote component's index. For example, if the remote endpoint is
  Frontend 1, then the local endpoint ID must be 1.

  Frontend 0  [0] ------- [0]  Backend 0  [0] ------- [0]  TCON 0
              [1] --   -- [1]             [1] --   -- [1]
                    \ /                         \ /
                     X                           X
                    / \                         / \
              [0] --   -- [0]             [0] --   -- [0]
  Frontend 1  [1] ------- [1]  Backend 1  [1] ------- [1]  TCON 1

  For a two pipeline system such as the one depicted above, the lines
  represent the connections between the components, while the numbers
  within the square brackets corresponds to the ID of the local endpoint.

  The same rule also applies to DE 2.0 mixer-TCON connections:

  Mixer 0  [0] ----------- [0]  TCON 0
           [1] ----   ---- [1]
                   \ /
                    X
                   / \
           [0] ----   ---- [0]
  Mixer 1  [1] ----------- [1]  TCON 1

properties:
  compatible:
    enum:
      - allwinner,sun4i-a10-display-engine
      - allwinner,sun5i-a10s-display-engine
      - allwinner,sun5i-a13-display-engine
      - allwinner,sun6i-a31-display-engine
      - allwinner,sun6i-a31s-display-engine
      - allwinner,sun7i-a20-display-engine
      - allwinner,sun8i-a23-display-engine
      - allwinner,sun8i-a33-display-engine
      - allwinner,sun8i-a83t-display-engine
      - allwinner,sun8i-h3-display-engine
      - allwinner,sun8i-r40-display-engine
      - allwinner,sun8i-v3s-display-engine
      - allwinner,sun9i-a80-display-engine
      - allwinner,sun20i-d1-display-engine
      - allwinner,sun50i-a64-display-engine
      - allwinner,sun50i-h6-display-engine

  allwinner,pipelines:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 1
    maxItems: 2
    items:
      maxItems: 1
    description: |
      Available display engine frontends (DE 1.0) or mixers (DE
      2.0/3.0) available.

required:
  - compatible
  - allwinner,pipelines

additionalProperties: false

if:
  properties:
    compatible:
      contains:
        enum:
          - allwinner,sun4i-a10-display-engine
          - allwinner,sun6i-a31-display-engine
          - allwinner,sun6i-a31s-display-engine
          - allwinner,sun7i-a20-display-engine
          - allwinner,sun8i-a83t-display-engine
          - allwinner,sun8i-r40-display-engine
          - allwinner,sun9i-a80-display-engine
          - allwinner,sun20i-d1-display-engine
          - allwinner,sun50i-a64-display-engine

then:
  properties:
    allwinner,pipelines:
      minItems: 2

else:
  properties:
    allwinner,pipelines:
      maxItems: 1

examples:
  - |
      de: display-engine {
          compatible = "allwinner,sun4i-a10-display-engine";
          allwinner,pipelines = <&fe0>, <&fe1>;
      };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 Display Engine Frontend

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |
  The display engine frontend does formats conversion, scaling,
  deinterlacing and color space conversion.

properties:
  compatible:
    enum:
      - allwinner,sun4i-a10-display-frontend
      - allwinner,sun5i-a13-display-frontend
      - allwinner,sun6i-a31-display-frontend
      - allwinner,sun7i-a20-display-frontend
      - allwinner,sun8i-a23-display-frontend
      - allwinner,sun8i-a33-display-frontend
      - allwinner,sun9i-a80-display-frontend

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: The frontend interface clock
      - description: The frontend module clock
      - description: The frontend DRAM clock

  clock-names:
    items:
      - const: ahb
      - const: mod
      - const: ram

  # FIXME: This should be made required eventually once every SoC will
  # have the MBUS declared.
  interconnects:
    maxItems: 1

  # FIXME: This should be made required eventually once every SoC will
  # have the MBUS declared.
  interconnect-names:
    const: dma-mem

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Input endpoints of the controller.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Output endpoints of the controller.

    required:
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/sun4i-a10-ccu.h>
    #include <dt-bindings/reset/sun4i-a10-ccu.h>

    fe0: display-frontend@1e00000 {
        compatible = "allwinner,sun4i-a10-display-frontend";
        reg = <0x01e00000 0x20000>;
        interrupts = <47>;
        clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
                 <&ccu CLK_DRAM_DE_FE0>;
        clock-names = "ahb", "mod",
                      "ram";
        resets = <&ccu RST_DE_FE0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            fe0_out: port@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;

                fe0_out_be0: endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&be0_in_fe0>;
                };

                fe0_out_be1: endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&be1_in_fe0>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 HDMI Controller

description: |
  The HDMI Encoder supports the HDMI video and audio outputs, and does
  CEC. It is one end of the pipeline.

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    oneOf:
      - const: allwinner,sun4i-a10-hdmi
      - const: allwinner,sun5i-a10s-hdmi
      - const: allwinner,sun6i-a31-hdmi
      - items:
          - const: allwinner,sun7i-a20-hdmi
          - const: allwinner,sun5i-a10s-hdmi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    oneOf:
      - items:
          - description: The HDMI interface clock
          - description: The HDMI module clock
          - description: The first video PLL
          - description: The second video PLL

      - items:
          - description: The HDMI interface clock
          - description: The HDMI module clock
          - description: The HDMI DDC clock
          - description: The first video PLL
          - description: The second video PLL

  clock-names:
    oneOf:
      - items:
          - const: ahb
          - const: mod
          - const: pll-0
          - const: pll-1

      - items:
          - const: ahb
          - const: mod
          - const: ddc
          - const: pll-0
          - const: pll-1

  resets:
    maxItems: 1

  dmas:
    items:
      - description: DDC Transmission DMA Channel
      - description: DDC Reception DMA Channel
      - description: Audio Transmission DMA Channel

  dma-names:
    items:
      - const: ddc-tx
      - const: ddc-rx
      - const: audio-tx

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Input endpoints of the controller.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Output endpoints of the controller. Usually an HDMI
          connector.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - dmas
  - dma-names

if:
  properties:
    compatible:
      contains:
        const: allwinner,sun6i-a31-hdmi

then:
  properties:
    clocks:
      minItems: 5

    clock-names:
      minItems: 5

  required:
    - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/sun4i-a10-ccu.h>
    #include <dt-bindings/dma/sun4i-a10.h>
    #include <dt-bindings/reset/sun4i-a10-ccu.h>

    hdmi: hdmi@1c16000 {
        compatible = "allwinner,sun4i-a10-hdmi";
        reg = <0x01c16000 0x1000>;
        interrupts = <58>;
        clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
                 <&ccu CLK_PLL_VIDEO0_2X>,
                 <&ccu CLK_PLL_VIDEO1_2X>;
        clock-names = "ahb", "mod", "pll-0", "pll-1";
        dmas = <&dma SUN4I_DMA_NORMAL 16>,
               <&dma SUN4I_DMA_NORMAL 16>,
               <&dma SUN4I_DMA_DEDICATED 24>;
        dma-names = "ddc-tx", "ddc-rx", "audio-tx";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            hdmi_in: port@0 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;

                hdmi_in_tcon0: endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&tcon0_out_hdmi>;
                };

                hdmi_in_tcon1: endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&tcon1_out_hdmi>;
                };
            };

            hdmi_out: port@1 {
                reg = <1>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tcon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 Timings Controller (TCON)

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |
  The TCON acts as a timing controller for RGB, LVDS and TV
  interfaces.

properties:
  "#clock-cells":
    const: 0

  compatible:
    oneOf:
      - const: allwinner,sun4i-a10-tcon
      - const: allwinner,sun5i-a13-tcon
      - const: allwinner,sun6i-a31-tcon
      - const: allwinner,sun6i-a31s-tcon
      - const: allwinner,sun7i-a20-tcon
      - const: allwinner,sun8i-a23-tcon
      - const: allwinner,sun8i-a33-tcon
      - const: allwinner,sun8i-a83t-tcon-lcd
      - const: allwinner,sun8i-a83t-tcon-tv
      - const: allwinner,sun8i-r40-tcon-tv
      - const: allwinner,sun8i-v3s-tcon
      - const: allwinner,sun9i-a80-tcon-lcd
      - const: allwinner,sun9i-a80-tcon-tv
      - const: allwinner,sun20i-d1-tcon-lcd
      - const: allwinner,sun20i-d1-tcon-tv

      - items:
          - enum:
              - allwinner,sun7i-a20-tcon0
              - allwinner,sun7i-a20-tcon1
          - const: allwinner,sun7i-a20-tcon

      - items:
          - enum:
              - allwinner,sun50i-a64-tcon-lcd
          - const: allwinner,sun8i-a83t-tcon-lcd

      - items:
          - enum:
              - allwinner,sun8i-h3-tcon-tv
              - allwinner,sun50i-a64-tcon-tv
          - const: allwinner,sun8i-a83t-tcon-tv

      - items:
          - enum:
              - allwinner,sun50i-h6-tcon-tv
          - const: allwinner,sun8i-r40-tcon-tv

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 4

  clock-names:
    minItems: 1
    maxItems: 4

  clock-output-names:
    description:
      Name of the LCD pixel clock created.
    maxItems: 1

  dmas:
    maxItems: 1

  resets:
    anyOf:
      - items:
          - description: TCON Reset Line

      - items:
          - description: TCON Reset Line
          - description: TCON LVDS Reset Line

      - items:
          - description: TCON Reset Line
          - description: TCON eDP Reset Line

      - items:
          - description: TCON Reset Line
          - description: TCON eDP Reset Line
          - description: TCON LVDS Reset Line

  reset-names:
    oneOf:
      - const: lcd

      - items:
          - const: lcd
          - const: lvds

      - items:
          - const: lcd
          - const: edp

      - items:
          - const: lcd
          - const: edp
          - const: lvds

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Input endpoints of the controller.

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: |
          Output endpoints of the controller.

        patternProperties:
          "^endpoint(@[0-9])$":
            $ref: /schemas/graph.yaml#/$defs/endpoint-base
            unevaluatedProperties: false

            properties:
              allwinner,tcon-channel:
                $ref: /schemas/types.yaml#/definitions/uint32
                description: |
                  TCON can have 1 or 2 channels, usually with the
                  first channel being used for the panels interfaces
                  (RGB, LVDS, etc.), and the second being used for the
                  outputs that require another controller (TV Encoder,
                  HDMI, etc.).

                  If that property is present, specifies the TCON
                  channel the endpoint is associated to. If that
                  property is not present, the endpoint number will be
                  used as the channel number.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - ports

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun4i-a10-tcon
              - allwinner,sun5i-a13-tcon
              - allwinner,sun7i-a20-tcon

    then:
      properties:
        clocks:
          minItems: 3

        clock-names:
          items:
            - const: ahb
            - const: tcon-ch0
            - const: tcon-ch1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun6i-a31-tcon
              - allwinner,sun6i-a31s-tcon

    then:
      properties:
        clocks:
          minItems: 4

        clock-names:
          items:
            - const: ahb
            - const: tcon-ch0
            - const: tcon-ch1
            - const: lvds-alt

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun8i-a23-tcon
              - allwinner,sun8i-a33-tcon

    then:
      properties:
        clocks:
          minItems: 3

        clock-names:
          items:
            - const: ahb
            - const: tcon-ch0
            - const: lvds-alt

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun8i-a83t-tcon-lcd
              - allwinner,sun8i-v3s-tcon
              - allwinner,sun9i-a80-tcon-lcd
              - allwinner,sun20i-d1-tcon-lcd

    then:
      properties:
        clocks:
          minItems: 2

        clock-names:
          items:
            - const: ahb
            - const: tcon-ch0

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun8i-a83t-tcon-tv
              - allwinner,sun8i-r40-tcon-tv
              - allwinner,sun9i-a80-tcon-tv
              - allwinner,sun20i-d1-tcon-tv

    then:
      properties:
        clocks:
          minItems: 2

        clock-names:
          items:
            - const: ahb
            - const: tcon-ch1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun5i-a13-tcon
              - allwinner,sun6i-a31-tcon
              - allwinner,sun6i-a31s-tcon
              - allwinner,sun7i-a20-tcon
              - allwinner,sun8i-a23-tcon
              - allwinner,sun8i-a33-tcon
              - allwinner,sun8i-v3s-tcon
              - allwinner,sun9i-a80-tcon-lcd
              - allwinner,sun4i-a10-tcon
              - allwinner,sun8i-a83t-tcon-lcd
              - allwinner,sun20i-d1-tcon-lcd

    then:
      required:
        - "#clock-cells"
        - clock-output-names

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun6i-a31-tcon
              - allwinner,sun6i-a31s-tcon
              - allwinner,sun8i-a23-tcon
              - allwinner,sun8i-a33-tcon
              - allwinner,sun8i-a83t-tcon-lcd
              - allwinner,sun20i-d1-tcon-lcd

    then:
      properties:
        resets:
          minItems: 2

        reset-names:
          items:
            - const: lcd
            - const: lvds

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun9i-a80-tcon-lcd

    then:
      properties:
        resets:
          minItems: 3

        reset-names:
          items:
            - const: lcd
            - const: edp
            - const: lvds

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun9i-a80-tcon-tv

    then:
      properties:
        resets:
          minItems: 2

        reset-names:
          items:
            - const: lcd
            - const: edp

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun4i-a10-tcon
              - allwinner,sun5i-a13-tcon
              - allwinner,sun6i-a31-tcon
              - allwinner,sun6i-a31s-tcon
              - allwinner,sun7i-a20-tcon
              - allwinner,sun8i-a23-tcon
              - allwinner,sun8i-a33-tcon

    then:
      required:
        - dmas

examples:
  - |
    #include <dt-bindings/dma/sun4i-a10.h>

    /*
     * This comes from the clock/sun4i-a10-ccu.h and
     * reset/sun4i-a10-ccu.h headers, but we can't include them since
     * it would trigger a bunch of warnings for redefinitions of
     * symbols with the other example.
     */

    #define CLK_AHB_LCD0	56
    #define CLK_TCON0_CH0	149
    #define CLK_TCON0_CH1	155
    #define RST_TCON0		11

    lcd-controller@1c0c000 {
        compatible = "allwinner,sun4i-a10-tcon";
        reg = <0x01c0c000 0x1000>;
        interrupts = <44>;
        resets = <&ccu RST_TCON0>;
        reset-names = "lcd";
        clocks = <&ccu CLK_AHB_LCD0>,
                 <&ccu CLK_TCON0_CH0>,
                 <&ccu CLK_TCON0_CH1>;
        clock-names = "ahb",
                      "tcon-ch0",
                      "tcon-ch1";
        clock-output-names = "tcon0-pixel-clock";
        #clock-cells = <0>;
        dmas = <&dma SUN4I_DMA_DEDICATED 14>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;

                endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&be0_out_tcon0>;
                };

                endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&be1_out_tcon0>;
                };
            };

            port@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;

                endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&hdmi_in_tcon0>;
                    allwinner,tcon-channel = <1>;
                };
            };
        };
    };

    #undef CLK_AHB_LCD0
    #undef CLK_TCON0_CH0
    #undef CLK_TCON0_CH1
    #undef RST_TCON0

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    /*
     * This comes from the clock/sun6i-a31-ccu.h and
     * reset/sun6i-a31-ccu.h headers, but we can't include them since
     * it would trigger a bunch of warnings for redefinitions of
     * symbols with the other example.
     */

    #define CLK_PLL_MIPI	15
    #define CLK_AHB1_LCD0	47
    #define CLK_LCD0_CH0	127
    #define CLK_LCD0_CH1	129
    #define RST_AHB1_LCD0	27
    #define RST_AHB1_LVDS	41

    lcd-controller@1c0c000 {
        compatible = "allwinner,sun6i-a31-tcon";
        reg = <0x01c0c000 0x1000>;
        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
        dmas = <&dma 11>;
        resets = <&ccu RST_AHB1_LCD0>, <&ccu RST_AHB1_LVDS>;
        reset-names = "lcd", "lvds";
        clocks = <&ccu CLK_AHB1_LCD0>,
                 <&ccu CLK_LCD0_CH0>,
                 <&ccu CLK_LCD0_CH1>,
                 <&ccu CLK_PLL_MIPI>;
        clock-names = "ahb",
                      "tcon-ch0",
                      "tcon-ch1",
                      "lvds-alt";
        clock-output-names = "tcon0-pixel-clock";
        #clock-cells = <0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;

                endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&drc0_out_tcon0>;
                };

                endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&drc1_out_tcon0>;
                };
            };

            port@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;

                endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&hdmi_in_tcon0>;
                    allwinner,tcon-channel = <1>;
                };
            };
        };
    };

    #undef CLK_PLL_MIPI
    #undef CLK_AHB1_LCD0
    #undef CLK_LCD0_CH0
    #undef CLK_LCD0_CH1
    #undef RST_AHB1_LCD0
    #undef RST_AHB1_LVDS

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    /*
     * This comes from the clock/sun9i-a80-ccu.h and
     * reset/sun9i-a80-ccu.h headers, but we can't include them since
     * it would trigger a bunch of warnings for redefinitions of
     * symbols with the other example.
     */

    #define CLK_BUS_LCD0	102
    #define CLK_LCD0		58
    #define RST_BUS_LCD0	22
    #define RST_BUS_EDP		24
    #define RST_BUS_LVDS	25

    lcd-controller@3c00000 {
        compatible = "allwinner,sun9i-a80-tcon-lcd";
        reg = <0x03c00000 0x10000>;
        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
        clock-names = "ahb", "tcon-ch0";
        resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>, <&ccu RST_BUS_LVDS>;
        reset-names = "lcd", "edp", "lvds";
        clock-output-names = "tcon0-pixel-clock";
        #clock-cells = <0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                endpoint {
                    remote-endpoint = <&drc0_out_tcon0>;
                };
            };

            port@1 {
                reg = <1>;
            };
        };
    };

    #undef CLK_BUS_TCON0
    #undef CLK_TCON0
    #undef RST_BUS_TCON0
    #undef RST_BUS_EDP
    #undef RST_BUS_LVDS

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    /*
     * This comes from the clock/sun8i-a83t-ccu.h and
     * reset/sun8i-a83t-ccu.h headers, but we can't include them since
     * it would trigger a bunch of warnings for redefinitions of
     * symbols with the other example.
     */

    #define CLK_BUS_TCON0	36
    #define CLK_TCON0		85
    #define RST_BUS_TCON0	22
    #define RST_BUS_LVDS	31

    lcd-controller@1c0c000 {
        compatible = "allwinner,sun8i-a83t-tcon-lcd";
        reg = <0x01c0c000 0x1000>;
        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
        clock-names = "ahb", "tcon-ch0";
        clock-output-names = "tcon-pixel-clock";
        #clock-cells = <0>;
        resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
        reset-names = "lcd", "lvds";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;

                endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&mixer0_out_tcon0>;
                };

                endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&mixer1_out_tcon0>;
                };
            };

            port@1 {
                reg = <1>;
            };
        };
    };

    #undef CLK_BUS_TCON0
    #undef CLK_TCON0
    #undef RST_BUS_TCON0
    #undef RST_BUS_LVDS

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    /*
     * This comes from the clock/sun8i-r40-ccu.h and
     * reset/sun8i-r40-ccu.h headers, but we can't include them since
     * it would trigger a bunch of warnings for redefinitions of
     * symbols with the other example.
     */

    #define CLK_BUS_TCON_TV0	73
    #define RST_BUS_TCON_TV0	49

    tcon_tv0: lcd-controller@1c73000 {
        compatible = "allwinner,sun8i-r40-tcon-tv";
        reg = <0x01c73000 0x1000>;
        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
        clock-names = "ahb", "tcon-ch1";
        resets = <&ccu RST_BUS_TCON_TV0>;
        reset-names = "lcd";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;

                endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
                };

                endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
                };
            };

            tcon_tv0_out: port@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;

                endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
                };
            };
        };
    };

    #undef CLK_BUS_TCON_TV0
    #undef RST_BUS_TCON_TV0

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-tv-encoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 TV Encoder

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    const: allwinner,sun4i-a10-tv-encoder

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      The first port should be the input endpoint, usually coming from the
      associated TCON.

required:
  - compatible
  - reg
  - clocks
  - resets
  - port

additionalProperties: false

examples:
  - |
    tve0: tv-encoder@1c0a000 {
        compatible = "allwinner,sun4i-a10-tv-encoder";
        reg = <0x01c0a000 0x1000>;
        clocks = <&ahb_gates 34>;
        resets = <&tcon_ch0_clk 0>;

        port {
            tve0_in_tcon0: endpoint {
                remote-endpoint = <&tcon0_out_tve0>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-drc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 Dynamic Range Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |
  The DRC (Dynamic Range Controller) allows to dynamically adjust
  pixel brightness/contrast based on histogram measurements for LCD
  content adaptive backlight control.

properties:
  compatible:
    enum:
      - allwinner,sun6i-a31-drc
      - allwinner,sun6i-a31s-drc
      - allwinner,sun8i-a23-drc
      - allwinner,sun8i-a33-drc
      - allwinner,sun9i-a80-drc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: The DRC interface clock
      - description: The DRC module clock
      - description: The DRC DRAM clock

  clock-names:
    items:
      - const: ahb
      - const: mod
      - const: ram

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Input endpoints of the controller.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Output endpoints of the controller.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/sun6i-a31-ccu.h>
    #include <dt-bindings/reset/sun6i-a31-ccu.h>

    drc0: drc@1e70000 {
        compatible = "allwinner,sun6i-a31-drc";
        reg = <0x01e70000 0x10000>;
        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
                 <&ccu CLK_DRAM_DRC0>;
        clock-names = "ahb", "mod",
                      "ram";
        resets = <&ccu RST_AHB1_DRC0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            drc0_in: port@0 {
                reg = <0>;

                drc0_in_be0: endpoint {
                    remote-endpoint = <&be0_out_drc0>;
                };
            };

            drc0_out: port@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;

                drc0_out_tcon0: endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&tcon0_in_drc0>;
                };

                drc0_out_tcon1: endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&tcon1_in_drc0>;
                };
            };
        };
    };

...