code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm RPMh Network-On-Chip Interconnect

maintainers:
  - Georgi Djakov <georgi.djakov@linaro.org>
  - Odelu Kukatla <okukatla@codeaurora.org>

description: |
   RPMh interconnect providers support system bandwidth requirements through
   RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
   able to communicate with the BCM through the Resource State Coordinator (RSC)
   associated with each execution environment. Provider nodes must point to at
   least one RPMh device child node pertaining to their RSC and each provider
   can map to multiple RPMh resources.

allOf:
  - $ref: qcom,rpmh-common.yaml#

properties:
  reg:
    maxItems: 1

  compatible:
    enum:
      - qcom,sc7180-aggre1-noc
      - qcom,sc7180-aggre2-noc
      - qcom,sc7180-camnoc-virt
      - qcom,sc7180-compute-noc
      - qcom,sc7180-config-noc
      - qcom,sc7180-dc-noc
      - qcom,sc7180-gem-noc
      - qcom,sc7180-mc-virt
      - qcom,sc7180-mmss-noc
      - qcom,sc7180-npu-noc
      - qcom,sc7180-qup-virt
      - qcom,sc7180-system-noc
      - qcom,sc7280-aggre1-noc
      - qcom,sc7280-aggre2-noc
      - qcom,sc7280-clk-virt
      - qcom,sc7280-cnoc2
      - qcom,sc7280-cnoc3
      - qcom,sc7280-dc-noc
      - qcom,sc7280-gem-noc
      - qcom,sc7280-lpass-ag-noc
      - qcom,sc7280-mc-virt
      - qcom,sc7280-mmss-noc
      - qcom,sc7280-nsp-noc
      - qcom,sc7280-system-noc
      - qcom,sc8180x-aggre1-noc
      - qcom,sc8180x-aggre2-noc
      - qcom,sc8180x-camnoc-virt
      - qcom,sc8180x-compute-noc
      - qcom,sc8180x-config-noc
      - qcom,sc8180x-dc-noc
      - qcom,sc8180x-gem-noc
      - qcom,sc8180x-ipa-virt
      - qcom,sc8180x-mc-virt
      - qcom,sc8180x-mmss-noc
      - qcom,sc8180x-qup-virt
      - qcom,sc8180x-system-noc
      - qcom,sc8280xp-aggre1-noc
      - qcom,sc8280xp-aggre2-noc
      - qcom,sc8280xp-clk-virt
      - qcom,sc8280xp-config-noc
      - qcom,sc8280xp-dc-noc
      - qcom,sc8280xp-gem-noc
      - qcom,sc8280xp-lpass-ag-noc
      - qcom,sc8280xp-mc-virt
      - qcom,sc8280xp-mmss-noc
      - qcom,sc8280xp-nspa-noc
      - qcom,sc8280xp-nspb-noc
      - qcom,sc8280xp-system-noc
      - qcom,sdm845-aggre1-noc
      - qcom,sdm845-aggre2-noc
      - qcom,sdm845-config-noc
      - qcom,sdm845-dc-noc
      - qcom,sdm845-gladiator-noc
      - qcom,sdm845-mem-noc
      - qcom,sdm845-mmss-noc
      - qcom,sdm845-system-noc
      - qcom,sdx55-mc-virt
      - qcom,sdx55-mem-noc
      - qcom,sdx55-system-noc
      - qcom,sdx65-mc-virt
      - qcom,sdx65-mem-noc
      - qcom,sdx65-system-noc
      - qcom,sm8150-aggre1-noc
      - qcom,sm8150-aggre2-noc
      - qcom,sm8150-camnoc-noc
      - qcom,sm8150-compute-noc
      - qcom,sm8150-config-noc
      - qcom,sm8150-dc-noc
      - qcom,sm8150-gem-noc
      - qcom,sm8150-ipa-virt
      - qcom,sm8150-mc-virt
      - qcom,sm8150-mmss-noc
      - qcom,sm8150-system-noc
      - qcom,sm8250-aggre1-noc
      - qcom,sm8250-aggre2-noc
      - qcom,sm8250-compute-noc
      - qcom,sm8250-config-noc
      - qcom,sm8250-dc-noc
      - qcom,sm8250-gem-noc
      - qcom,sm8250-ipa-virt
      - qcom,sm8250-mc-virt
      - qcom,sm8250-mmss-noc
      - qcom,sm8250-npu-noc
      - qcom,sm8250-system-noc
      - qcom,sm8350-aggre1-noc
      - qcom,sm8350-aggre2-noc
      - qcom,sm8350-config-noc
      - qcom,sm8350-dc-noc
      - qcom,sm8350-gem-noc
      - qcom,sm8350-lpass-ag-noc
      - qcom,sm8350-mc-virt
      - qcom,sm8350-mmss-noc
      - qcom,sm8350-compute-noc
      - qcom,sm8350-system-noc
      - qcom,sm8450-aggre1-noc
      - qcom,sm8450-aggre2-noc
      - qcom,sm8450-clk-virt
      - qcom,sm8450-config-noc
      - qcom,sm8450-gem-noc
      - qcom,sm8450-lpass-ag-noc
      - qcom,sm8450-mc-virt
      - qcom,sm8450-mmss-noc
      - qcom,sm8450-nsp-noc
      - qcom,sm8450-pcie-anoc
      - qcom,sm8450-system-noc

  '#interconnect-cells': true

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
      #include <dt-bindings/interconnect/qcom,sdm845.h>

      mem_noc: interconnect@1380000 {
             compatible = "qcom,sdm845-mem-noc";
             reg = <0x01380000 0x27200>;
             #interconnect-cells = <1>;
             qcom,bcm-voters = <&apps_bcm_voter>;
      };

      mmss_noc: interconnect@1740000 {
             compatible = "qcom,sdm845-mmss-noc";
             reg = <0x01740000 0x1c1000>;
             #interconnect-cells = <1>;
             qcom,bcm-voter-names = "apps", "disp";
             qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
      };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sm6350-rpmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM6350 RPMh Network-On-Chip Interconnect

maintainers:
  - Luca Weiss <luca.weiss@fairphone.com>

description:
  Qualcomm RPMh-based interconnect provider on SM6350.

allOf:
  - $ref: qcom,rpmh-common.yaml#

properties:
  compatible:
    enum:
      - qcom,sm6350-aggre1-noc
      - qcom,sm6350-aggre2-noc
      - qcom,sm6350-config-noc
      - qcom,sm6350-dc-noc
      - qcom,sm6350-gem-noc
      - qcom,sm6350-mmss-noc
      - qcom,sm6350-npu-noc
      - qcom,sm6350-system-noc

  reg:
    maxItems: 1

  '#interconnect-cells': true

patternProperties:
  '^interconnect-[a-z0-9\-]+$':
    type: object
    description:
      The interconnect providers do not have a separate QoS register space,
      but share parent's space.
    $ref: qcom,rpmh-common.yaml#

    properties:
      compatible:
        enum:
          - qcom,sm6350-clk-virt
          - qcom,sm6350-compute-noc

      '#interconnect-cells': true

    required:
      - compatible

    unevaluatedProperties: false

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    config_noc: interconnect@1500000 {
        compatible = "qcom,sm6350-config-noc";
        reg = <0x01500000 0x28000>;
        #interconnect-cells = <2>;
        qcom,bcm-voters = <&apps_bcm_voter>;
    };

    system_noc: interconnect@1620000 {
        compatible = "qcom,sm6350-system-noc";
        reg = <0x01620000 0x17080>;
        #interconnect-cells = <2>;
        qcom,bcm-voters = <&apps_bcm_voter>;

        clk_virt: interconnect-clk-virt {
            compatible = "qcom,sm6350-clk-virt";
            #interconnect-cells = <2>;
            qcom,bcm-voters = <&apps_bcm_voter>;
        };
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC Bus and Interconnect

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  The Samsung Exynos SoC has many buses for data transfer between DRAM and
  sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
  Generally, each bus of Exynos SoC includes a source clock and a power line,
  which are able to change the clock frequency of the bus in runtime. To
  monitor the usage of each bus in runtime, the driver uses the PPMU (Platform
  Performance Monitoring Unit), which is able to measure the current load of
  sub-blocks.

  The Exynos SoC includes the various sub-blocks which have the each AXI bus.
  The each AXI bus has the owned source clock but, has not the only owned power
  line. The power line might be shared among one more sub-blocks.  So, we can
  divide into two type of device as the role of each sub-block.  There are two
  type of bus devices as following::
   - parent bus device
   - passive bus device

  Basically, parent and passive bus device share the same power line.  The
  parent bus device can only change the voltage of shared power line and the
  rest bus devices (passive bus device) depend on the decision of the parent
  bus device. If there are three blocks which share the VDD_xxx power line,
  Only one block should be parent device and then the rest blocks should depend
  on the parent device as passive device.

    VDD_xxx |--- A block (parent)
      |--- B block (passive)
      |--- C block (passive)

  There are a little different composition among Exynos SoC because each Exynos
  SoC has different sub-blocks. Therefore, such difference should be specified
  in devicetree file instead of each device driver. In result, this driver is
  able to support the bus frequency for all Exynos SoCs.

  Detailed correlation between sub-blocks and power line according
  to Exynos SoC::
   - In case of Exynos3250, there are two power line as following::
     VDD_MIF |--- DMC (Dynamic Memory Controller)

     VDD_INT |--- LEFTBUS (parent device)
       |--- PERIL
       |--- MFC
       |--- G3D
       |--- RIGHTBUS
       |--- PERIR
       |--- FSYS
       |--- LCD0
       |--- PERIR
       |--- ISP
       |--- CAM

     - MIF bus's frequency/voltage table
       -----------------------
       |Lv| Freq   | Voltage |
       -----------------------
       |L1| 50000  |800000   |
       |L2| 100000 |800000   |
       |L3| 134000 |800000   |
       |L4| 200000 |825000   |
       |L5| 400000 |875000   |
       -----------------------

     - INT bus's frequency/voltage table
       ----------------------------------------------------------
       |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |
       | name|       |LCD0    |       |       |       ||        |
       |     |       |FSYS    |       |       |       ||        |
       |     |       |MFC     |       |       |       ||        |
       ----------------------------------------------------------
       |Mode |*parent|passive |passive|passive|passive||        |
       ----------------------------------------------------------
       |Lv   |Frequency                               ||Voltage |
       ----------------------------------------------------------
       |L1   |50000  |50000   |50000  |50000  |50000  ||900000  |
       |L2   |80000  |80000   |80000  |80000  |80000  ||900000  |
       |L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |
       |L4   |134000 |134000  |200000 |200000 |       ||1000000 |
       |L5   |200000 |200000  |400000 |300000 |       ||1000000 |
       ----------------------------------------------------------

   - In case of Exynos4210, there is one power line as following::
     VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
       |--- LEFTBUS
       |--- PERIL
       |--- MFC(L)
       |--- G3D
       |--- TV
       |--- LCD0
       |--- RIGHTBUS
       |--- PERIR
       |--- MFC(R)
       |--- CAM
       |--- FSYS
       |--- GPS
       |--- LCD0
       |--- LCD1

   - In case of Exynos4x12, there are two power line as following::
     VDD_MIF |--- DMC (Dynamic Memory Controller)

     VDD_INT |--- LEFTBUS (parent device)
       |--- PERIL
       |--- MFC(L)
       |--- G3D
       |--- TV
       |--- IMAGE
       |--- RIGHTBUS
       |--- PERIR
       |--- MFC(R)
       |--- CAM
       |--- FSYS
       |--- GPS
       |--- LCD0
       |--- ISP

   - In case of Exynos5422, there are two power line as following::
     VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
             |--- DREX 1

     VDD_INT |--- NoC_Core (parent device)
       |--- G2D
       |--- G3D
       |--- DISP1
       |--- NoC_WCORE
       |--- GSCL
       |--- MSCL
       |--- ISP
       |--- MFC
       |--- GEN
       |--- PERIS
       |--- PERIC
       |--- FSYS
       |--- FSYS2

   - In case of Exynos5433, there is VDD_INT power line as following::
     VDD_INT |--- G2D (parent device)
       |--- MSCL
       |--- GSCL
       |--- JPEG
       |--- MFC
       |--- HEVC
       |--- BUS0
       |--- BUS1
       |--- BUS2
       |--- PERIS (Fixed clock rate)
       |--- PERIC (Fixed clock rate)
       |--- FSYS  (Fixed clock rate)

properties:
  compatible:
    enum:
      - samsung,exynos-bus

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: bus

  devfreq:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Parent bus device. Valid and required only for the passive bus devices.

  devfreq-events:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 1
    maxItems: 4
    description:
      Devfreq-event device to monitor the current utilization of buses. Valid
      and required only for the parent bus devices.

  exynos,saturation-ratio:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Percentage value which is used to calibrate the performance count against
      total cycle count.  Valid only for the parent bus devices.

  '#interconnect-cells':
    const: 0

  interconnects:
    minItems: 1
    maxItems: 2

  operating-points-v2: true

  samsung,data-clock-ratio:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 8
    description:
      Ratio of the data throughput in B/s to minimum data clock frequency in
      Hz.

  vdd-supply:
    description:
      Main bus power rail. Valid and required only for the parent bus devices.

required:
  - compatible
  - clocks
  - clock-names
  - operating-points-v2

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos3250.h>

    bus-dmc {
        compatible = "samsung,exynos-bus";
        clocks = <&cmu_dmc CLK_DIV_DMC>;
        clock-names = "bus";
        operating-points-v2 = <&bus_dmc_opp_table>;
        devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
        vdd-supply = <&buck1_reg>;
    };

    ppmu_dmc0: ppmu@106a0000 {
        compatible = "samsung,exynos-ppmu";
        reg = <0x106a0000 0x2000>;
        events {
            ppmu_dmc0_3: ppmu-event3-dmc0 {
                event-name = "ppmu-event3-dmc0";
            };
        };
    };

    bus_leftbus: bus-leftbus {
        compatible = "samsung,exynos-bus";
        clocks = <&cmu CLK_DIV_GDL>;
        clock-names = "bus";
        operating-points-v2 = <&bus_leftbus_opp_table>;
        devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
        vdd-supply = <&buck3_reg>;
    };

    bus-rightbus {
        compatible = "samsung,exynos-bus";
        clocks = <&cmu CLK_DIV_GDR>;
        clock-names = "bus";
        operating-points-v2 = <&bus_leftbus_opp_table>;
        devfreq = <&bus_leftbus>;
    };

  - |
    dmc: bus-dmc {
        compatible = "samsung,exynos-bus";
        clocks = <&clock CLK_DIV_DMC>;
        clock-names = "bus";
        operating-points-v2 = <&bus_dmc_opp_table>;
        samsung,data-clock-ratio = <4>;
        #interconnect-cells = <0>;
        devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
        vdd-supply = <&buck1_reg>;
    };

    leftbus: bus-leftbus {
        compatible = "samsung,exynos-bus";
        clocks = <&clock CLK_DIV_GDL>;
        clock-names = "bus";
        operating-points-v2 = <&bus_leftbus_opp_table>;
        interconnects = <&dmc>;
        #interconnect-cells = <0>;
        devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
        vdd-supply = <&buck3_reg>;
    };

    display: bus-display {
        compatible = "samsung,exynos-bus";
        clocks = <&clock CLK_DIV_ACLK_266>;
        clock-names = "bus";
        operating-points-v2 = <&bus_display_opp_table>;
        interconnects = <&leftbus &dmc>;
        #interconnect-cells = <0>;
        devfreq = <&leftbus>;
    };


code:
TB10x Top Level Interrupt Controller
====================================

The Abilis TB10x SOC contains a custom interrupt controller. It performs
one-to-one mapping of external interrupt sources to CPU interrupts and
provides support for reconfigurable trigger modes.

Required properties
-------------------

- compatible: Should be "abilis,tb10x-ictl"
- reg: specifies physical base address and size of register range.
- interrupt-congroller: Identifies the node as an interrupt controller.
- #interrupt cells: Specifies the number of cells used to encode an interrupt
  source connected to this controller. The value shall be 2.
- interrupts: Specifies the list of interrupt lines which are handled by
  the interrupt controller in the parent controller's notation. Interrupts
  are mapped one-to-one to parent interrupts.

Example
-------

intc: interrupt-controller {	/* Parent interrupt controller */
	interrupt-controller;
	#interrupt-cells = <1>;	/* For example below */
	/* ... */
};

tb10x_ictl: pic@2000 {		/* TB10x interrupt controller */
	compatible = "abilis,tb10x-ictl";
	reg = <0x2000 0x20>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupt-parent = <&intc>;
	interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
			20 21 22 23 24 25 26 27 28 29 30 31>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Actions Semi Owl SoCs SIRQ interrupt controller

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

description: |
  This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
  and S900) and provides support for handling up to 3 external interrupt lines.

properties:
  compatible:
    enum:
      - actions,s500-sirq
      - actions,s700-sirq
      - actions,s900-sirq

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2
    description:
      The first cell is the input IRQ number, between 0 and 2, while the second
      cell is the trigger type as defined in interrupt.txt in this directory.

  'interrupts':
    description: |
      Contains the GIC SPI IRQs mapped to the external interrupt lines.
      They shall be specified sequentially from output 0 to 2.
    minItems: 3
    maxItems: 3

required:
  - compatible
  - reg
  - interrupt-controller
  - '#interrupt-cells'
  - 'interrupts'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    sirq: interrupt-controller@b01b0200 {
      compatible = "actions,s500-sirq";
      reg = <0xb01b0200 0x4>;
      interrupt-controller;
      #interrupt-cells = <2>;
      interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
                   <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
                   <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
    };

...


code:
Alpine MSIX controller

See arm,gic-v3.txt for SPI and MSI definitions.

Required properties:

- compatible: should be "al,alpine-msix"
- reg: physical base address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
- msi-controller: identifies the node as an PCI Message Signaled Interrupt
		  controller
- al,msi-base-spi: SPI base of the MSI frame
- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0

Example:

msix: msix {
	compatible = "al,alpine-msix";
	reg = <0x0 0xfbe00000 0x0 0x100000>;
	interrupt-parent = <&gic>;
	interrupt-controller;
	msi-controller;
	al,msi-base-spi = <160>;
	al,msi-num-spis = <160>;
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun4i-a10-ic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 Interrupt Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  "#interrupt-cells":
    const: 1

  compatible:
    enum:
      - allwinner,sun4i-a10-ic
      - allwinner,suniv-f1c100s-ic

  reg:
    maxItems: 1

  interrupt-controller: true

required:
  - "#interrupt-cells"
  - compatible
  - reg
  - interrupt-controller

additionalProperties: false

examples:
  - |
    intc: interrupt-controller@1c20400 {
        compatible = "allwinner,sun4i-a10-ic";
        reg = <0x01c20400 0x400>;
        interrupt-controller;
        #interrupt-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 NMI/Wakeup Interrupt Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  "#interrupt-cells":
    const: 3
    description:
      The first cell is GIC_SPI (0), the second cell is the IRQ number, and
      the third cell is the trigger type as defined in interrupt.txt in this
      directory.

  compatible:
    oneOf:
      - const: allwinner,sun6i-a31-r-intc
      - items:
          - enum:
              - allwinner,sun8i-a83t-r-intc
              - allwinner,sun8i-h3-r-intc
              - allwinner,sun50i-a64-r-intc
          - const: allwinner,sun6i-a31-r-intc
      - const: allwinner,sun50i-h6-r-intc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1
    description:
      The GIC interrupt labeled as "External NMI".

  interrupt-controller: true

required:
  - "#interrupt-cells"
  - compatible
  - reg
  - interrupts
  - interrupt-controller

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    r_intc: interrupt-controller@1f00c00 {
            compatible = "allwinner,sun50i-a64-r-intc",
                         "allwinner,sun6i-a31-r-intc";
            interrupt-controller;
            #interrupt-cells = <3>;
            reg = <0x01f00c00 0x400>;
            interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A20 Non-Maskable Interrupt Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  "#interrupt-cells":
    const: 2
    description:
      The first cell is the IRQ number, the second cell the trigger
      type as defined in interrupt.txt in this directory.

  compatible:
    oneOf:
      - const: allwinner,sun6i-a31-sc-nmi
        deprecated: true
      - const: allwinner,sun7i-a20-sc-nmi
      - items:
          - const: allwinner,sun8i-v3s-nmi
          - const: allwinner,sun9i-a80-nmi
      - const: allwinner,sun9i-a80-nmi
      - items:
          - const: allwinner,sun50i-a100-nmi
          - const: allwinner,sun9i-a80-nmi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-controller: true

required:
  - "#interrupt-cells"
  - compatible
  - reg
  - interrupts
  - interrupt-controller

unevaluatedProperties: false

examples:
  - |
    interrupt-controller@1c00030 {
        compatible = "allwinner,sun7i-a20-sc-nmi";
        interrupt-controller;
        #interrupt-cells = <2>;
        reg = <0x01c00030 0x0c>;
        interrupt-parent = <&gic>;
        interrupts = <0 0 4>;
    };

...


code:
Amazon's Annapurna Labs Fabric Interrupt Controller

Required properties:

- compatible: should be "amazon,al-fic"
- reg: physical base address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells : must be 2. Specifies the number of cells needed to encode
  an interrupt source. Supported trigger types are low-to-high edge
  triggered and active high level-sensitive.
- interrupts: describes which input line in the interrupt parent, this
  fic's output is connected to. This field property depends on the parent's
  binding

Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.

Example:

amazon_fic: interrupt-controller@fd8a8500 {
	compatible = "amazon,al-fic";
	interrupt-controller;
	#interrupt-cells = <2>;
	reg = <0x0 0xfd8a8500 0x0 0x1000>;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 0x0 IRQ_TYPE_LEVEL_HIGH>;
};


code:
Amlogic meson GPIO interrupt controller

Meson SoCs contains an interrupt controller which is able to watch the SoC
pads and generate an interrupt on edge or level. The controller is essentially
a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
or level and polarity. It does not expose all 256 mux inputs because the
documentation shows that the upper part is not mapped to any pad. The actual
number of interrupt exposed depends on the SoC.

Required properties:

- compatible : must have "amlogic,meson8-gpio-intc" and either
    "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
    "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
    "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
    "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
    "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
    "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
    "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
    "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
    "amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
   interrupt source. The value must be 2.
- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These
   are the hwirqs used on the parent interrupt controller.

Example:

gpio_interrupt: interrupt-controller@9880 {
	compatible = "amlogic,meson-gxbb-gpio-intc",
		     "amlogic,meson-gpio-intc";
	reg = <0x0 0x9880 0x0 0x10>;
	interrupt-controller;
	#interrupt-cells = <2>;
	meson,channel-interrupts = <64 65 66 67 68 69 70 71>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple Interrupt Controller

maintainers:
  - Hector Martin <marcan@marcan.st>

description: |
  The Apple Interrupt Controller is a simple interrupt controller present on
  Apple ARM SoC platforms, including various iPhone and iPad devices and the
  "Apple Silicon" Macs.

  It provides the following features:

  - Level-triggered hardware IRQs wired to SoC blocks
    - Single mask bit per IRQ
    - Per-IRQ affinity setting
    - Automatic masking on event delivery (auto-ack)
    - Software triggering (ORed with hw line)
  - 2 per-CPU IPIs (meant as "self" and "other", but they are interchangeable
    if not symmetric)
  - Automatic prioritization (single event/ack register per CPU, lower IRQs =
    higher priority)
  - Automatic masking on ack
  - Default "this CPU" register view and explicit per-CPU views

  This device also represents the FIQ interrupt sources on platforms using AIC,
  which do not go through a discrete interrupt controller.

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    items:
      - const: apple,t8103-aic
      - const: apple,aic

  interrupt-controller: true

  '#interrupt-cells':
    const: 3
    description: |
      The 1st cell contains the interrupt type:
        - 0: Hardware IRQ
        - 1: FIQ

      The 2nd cell contains the interrupt number.
        - HW IRQs: interrupt number
        - FIQs:
          - 0: physical HV timer
          - 1: virtual HV timer
          - 2: physical guest timer
          - 3: virtual guest timer
          - 4: 'efficient' CPU PMU
          - 5: 'performance' CPU PMU

      The 3rd cell contains the interrupt flags. This is normally
      IRQ_TYPE_LEVEL_HIGH (4).

  reg:
    description: |
      Specifies base physical address and size of the AIC registers.
    maxItems: 1

  power-domains:
    maxItems: 1

  affinities:
    type: object
    additionalProperties: false
    description:
      FIQ affinity can be expressed as a single "affinities" node,
      containing a set of sub-nodes, one per FIQ with a non-default
      affinity.
    patternProperties:
      "^.+-affinity$":
        type: object
        additionalProperties: false
        properties:
          apple,fiq-index:
            description:
              The interrupt number specified as a FIQ, and for which
              the affinity is not the default.
            $ref: /schemas/types.yaml#/definitions/uint32
            maximum: 5

          cpus:
            description:
              Should be a list of phandles to CPU nodes (as described in
              Documentation/devicetree/bindings/arm/cpus.yaml).

        required:
          - apple,fiq-index
          - cpus

required:
  - compatible
  - '#interrupt-cells'
  - interrupt-controller
  - reg

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        aic: interrupt-controller@23b100000 {
            compatible = "apple,t8103-aic", "apple,aic";
            #interrupt-cells = <3>;
            interrupt-controller;
            reg = <0x2 0x3b100000 0x0 0x8000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple Interrupt Controller 2

maintainers:
  - Hector Martin <marcan@marcan.st>

description: |
  The Apple Interrupt Controller 2 is a simple interrupt controller present on
  Apple ARM SoC platforms starting with t600x (M1 Pro and Max).

  It provides the following features:

  - Level-triggered hardware IRQs wired to SoC blocks
    - Single mask bit per IRQ
    - Automatic masking on event delivery (auto-ack)
    - Software triggering (ORed with hw line)
  - Automatic prioritization (single event/ack register per CPU, lower IRQs =
    higher priority)
  - Automatic masking on ack
  - Support for multiple dies

  This device also represents the FIQ interrupt sources on platforms using AIC,
  which do not go through a discrete interrupt controller. It also handles
  FIQ-based Fast IPIs.

properties:
  compatible:
    items:
      - const: apple,t6000-aic
      - const: apple,aic2

  interrupt-controller: true

  '#interrupt-cells':
    const: 4
    description: |
      The 1st cell contains the interrupt type:
        - 0: Hardware IRQ
        - 1: FIQ

      The 2nd cell contains the die ID.

      The next cell contains the interrupt number.
        - HW IRQs: interrupt number
        - FIQs:
          - 0: physical HV timer
          - 1: virtual HV timer
          - 2: physical guest timer
          - 3: virtual guest timer

      The last cell contains the interrupt flags. This is normally
      IRQ_TYPE_LEVEL_HIGH (4).

  reg:
    items:
      - description: Address and size of the main AIC2 registers.
      - description: Address and size of the AIC2 Event register.

  reg-names:
    items:
      - const: core
      - const: event

  power-domains:
    maxItems: 1

  affinities:
    type: object
    additionalProperties: false
    description:
      FIQ affinity can be expressed as a single "affinities" node,
      containing a set of sub-nodes, one per FIQ with a non-default
      affinity.
    patternProperties:
      "^.+-affinity$":
        type: object
        additionalProperties: false
        properties:
          apple,fiq-index:
            description:
              The interrupt number specified as a FIQ, and for which
              the affinity is not the default.
            $ref: /schemas/types.yaml#/definitions/uint32
            maximum: 5

          cpus:
            $ref: /schemas/types.yaml#/definitions/phandle-array
            description:
              Should be a list of phandles to CPU nodes (as described in
              Documentation/devicetree/bindings/arm/cpus.yaml).

        required:
          - apple,fiq-index
          - cpus

required:
  - compatible
  - '#interrupt-cells'
  - interrupt-controller
  - reg
  - reg-names

additionalProperties: false

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        aic: interrupt-controller@28e100000 {
            compatible = "apple,t6000-aic", "apple,aic2";
            #interrupt-cells = <4>;
            interrupt-controller;
            reg = <0x2 0x8e100000 0x0 0xc000>,
                  <0x2 0x8e10c000 0x0 0x4>;
            reg-names = "core", "event";
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Generic Interrupt Controller, version 3

maintainers:
  - Marc Zyngier <maz@kernel.org>

description: |
  AArch64 SMP cores are often associated with a GICv3, providing Private
  Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
  Software Generated Interrupts (SGI), and Locality-specific Peripheral
  Interrupts (LPI).

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - qcom,msm8996-gic-v3
          - const: arm,gic-v3
      - const: arm,gic-v3

  interrupt-controller: true

  "#address-cells":
    enum: [ 0, 1, 2 ]
  "#size-cells":
    enum: [ 1, 2 ]

  ranges: true

  "#interrupt-cells":
    description: |
      Specifies the number of cells needed to encode an interrupt source.
      Must be a single cell with a value of at least 3.
      If the system requires describing PPI affinity, then the value must
      be at least 4.

      The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
      interrupts, 2 for interrupts in the Extended SPI range, 3 for the
      Extended PPI range. Other values are reserved for future use.

      The 2nd cell contains the interrupt number for the interrupt type.
      SPI interrupts are in the range [0-987]. PPI interrupts are in the
      range [0-15]. Extented SPI interrupts are in the range [0-1023].
      Extended PPI interrupts are in the range [0-127].

      The 3rd cell is the flags, encoded as follows:
      bits[3:0] trigger type and level flags.
        1 = edge triggered
        4 = level triggered

      The 4th cell is a phandle to a node describing a set of CPUs this
      interrupt is affine to. The interrupt must be a PPI, and the node
      pointed must be a subnode of the "ppi-partitions" subnode. For
      interrupt types other than PPI or PPIs that are not partitionned,
      this cell must be zero. See the "ppi-partitions" node description
      below.

      Cells 5 and beyond are reserved for future use and must have a value
      of 0 if present.
    enum: [ 3, 4 ]

  reg:
    description: |
      Specifies base physical address(s) and size of the GIC
      registers, in the following order:
      - GIC Distributor interface (GICD)
      - GIC Redistributors (GICR), one range per redistributor region
      - GIC CPU interface (GICC)
      - GIC Hypervisor interface (GICH)
      - GIC Virtual CPU interface (GICV)

      GICC, GICH and GICV are optional, but must be described if the CPUs
      support them. Examples of such CPUs are ARM's implementations of the
      ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
      A73 (this list is not exhaustive).

    minItems: 2
    maxItems: 4096   # Should be enough?

  interrupts:
    description:
      Interrupt source of the VGIC maintenance interrupt.
    maxItems: 1

  redistributor-stride:
    description:
      If using padding pages, specifies the stride of consecutive
      redistributors. Must be a multiple of 64kB.
    $ref: /schemas/types.yaml#/definitions/uint64
    multipleOf: 0x10000
    exclusiveMinimum: 0

  "#redistributor-regions":
    description:
      The number of independent contiguous regions occupied by the
      redistributors. Required if more than one such region is present.
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 4096

  msi-controller:
    description:
      Only present if the Message Based Interrupt functionnality is
      being exposed by the HW, and the mbi-ranges property present.

  mbi-ranges:
    description:
      A list of pairs <intid span>, where "intid" is the first SPI of a range
      that can be used an MBI, and "span" the size of that range. Multiple
      ranges can be provided.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    items:
      minItems: 2
      maxItems: 2

  mbi-alias:
    description:
      Address property. Base address of an alias of the GICD region containing
      only the {SET,CLR}SPI registers to be used if isolation is required,
      and if supported by the HW.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    items:
      minItems: 1
      maxItems: 2

  ppi-partitions:
    type: object
    description:
      PPI affinity can be expressed as a single "ppi-partitions" node,
      containing a set of sub-nodes.
    patternProperties:
      "^interrupt-partition-[0-9]+$":
        type: object
        properties:
          affinity:
            $ref: /schemas/types.yaml#/definitions/phandle-array
            items:
              maxItems: 1
            description:
              Should be a list of phandles to CPU nodes (as described in
              Documentation/devicetree/bindings/arm/cpus.yaml).

        required:
          - affinity

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: aclk

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

dependencies:
  mbi-ranges: [ msi-controller ]
  msi-controller: [ mbi-ranges ]

required:
  - compatible
  - reg

patternProperties:
  "^gic-its@": false
  "^interrupt-controller@[0-9a-f]+$": false
  # msi-controller is preferred, but allow other names
  "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
    type: object
    description:
      GICv3 has one or more Interrupt Translation Services (ITS) that are
      used to route Message Signalled Interrupts (MSI) to the CPUs.
    properties:
      compatible:
        const: arm,gic-v3-its

      msi-controller: true

      "#msi-cells":
        description:
          The single msi-cell is the DeviceID of the device which will generate
          the MSI.
        const: 1

      reg:
        description:
          Specifies the base physical address and size of the ITS registers.
        maxItems: 1

      socionext,synquacer-pre-its:
        description:
          (u32, u32) tuple describing the untranslated
          address and size of the pre-ITS window.
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          minItems: 2
          maxItems: 2

    required:
      - compatible
      - msi-controller
      - "#msi-cells"
      - reg

    additionalProperties: false

additionalProperties: false

examples:
  - |
    gic: interrupt-controller@2cf00000 {
      compatible = "arm,gic-v3";
      #interrupt-cells = <3>;
      #address-cells = <1>;
      #size-cells = <1>;
      ranges;
      interrupt-controller;
      reg = <0x2f000000 0x10000>,  // GICD
            <0x2f100000 0x200000>,  // GICR
            <0x2c000000 0x2000>,  // GICC
            <0x2c010000 0x2000>,  // GICH
            <0x2c020000 0x2000>;  // GICV
      interrupts = <1 9 4>;

      msi-controller;
      mbi-ranges = <256 128>;

      msi-controller@2c200000 {
        compatible = "arm,gic-v3-its";
        msi-controller;
        #msi-cells = <1>;
        reg = <0x2c200000 0x20000>;
      };
    };

  - |
    interrupt-controller@2c010000 {
      compatible = "arm,gic-v3";
      #interrupt-cells = <4>;
      #address-cells = <1>;
      #size-cells = <1>;
      ranges;
      interrupt-controller;
      redistributor-stride = <0x0 0x40000>;  // 256kB stride
      #redistributor-regions = <2>;
      reg = <0x2c010000 0x10000>,  // GICD
            <0x2d000000 0x800000>,  // GICR 1: CPUs 0-31
            <0x2e000000 0x800000>,  // GICR 2: CPUs 32-63
            <0x2c040000 0x2000>,  // GICC
            <0x2c060000 0x2000>,  // GICH
            <0x2c080000 0x2000>;  // GICV
      interrupts = <1 9 4 0>;

      msi-controller@2c200000 {
        compatible = "arm,gic-v3-its";
        msi-controller;
        #msi-cells = <1>;
        reg = <0x2c200000 0x20000>;
      };

      msi-controller@2c400000 {
        compatible = "arm,gic-v3-its";
        msi-controller;
        #msi-cells = <1>;
        reg = <0x2c400000 0x20000>;
      };

      ppi-partitions {
        part0: interrupt-partition-0 {
          affinity = <&cpu0>, <&cpu2>;
        };

        part1: interrupt-partition-1 {
          affinity = <&cpu1>, <&cpu3>;
        };
      };
    };

    device@0 {
      reg = <0 4>;
      interrupts = <1 1 4 &part0>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Generic Interrupt Controller v1 and v2

maintainers:
  - Marc Zyngier <marc.zyngier@arm.com>

description: |+
  ARM SMP cores are often associated with a GIC, providing per processor
  interrupts (PPI), shared processor interrupts (SPI) and software
  generated interrupts (SGI).

  Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
  Secondary GICs are cascaded into the upward interrupt controller and do not
  have PPIs or SGIs.

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - arm,arm11mp-gic
              - arm,cortex-a15-gic
              - arm,cortex-a7-gic
              - arm,cortex-a5-gic
              - arm,cortex-a9-gic
              - arm,eb11mp-gic
              - arm,gic-400
              - arm,pl390
              - arm,tc11mp-gic
              - qcom,msm-8660-qgic
              - qcom,msm-qgic2

      - items:
          - const: arm,gic-400
          - enum:
              - arm,cortex-a15-gic
              - arm,cortex-a7-gic

      - items:
          - const: arm,arm1176jzf-devchip-gic
          - const: arm,arm11mp-gic

      - items:
          - const: brcm,brahma-b15-gic
          - const: arm,cortex-a15-gic

      - oneOf:
          - const: nvidia,tegra210-agic
          - items:
              - enum:
                  - nvidia,tegra186-agic
                  - nvidia,tegra194-agic
                  - nvidia,tegra234-agic
              - const: nvidia,tegra210-agic

  interrupt-controller: true

  "#address-cells":
    enum: [ 0, 1, 2 ]
  "#size-cells":
    enum: [ 1, 2 ]

  "#interrupt-cells":
    const: 3
    description: |
      The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
      interrupts.

      The 2nd cell contains the interrupt number for the interrupt type.
      SPI interrupts are in the range [0-987].  PPI interrupts are in the
      range [0-15].

      The 3rd cell is the flags, encoded as follows:
        bits[3:0] trigger type and level flags.
          1 = low-to-high edge triggered
          2 = high-to-low edge triggered (invalid for SPIs)
          4 = active high level-sensitive
          8 = active low level-sensitive (invalid for SPIs).
        bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
        the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
        the interrupt is wired to that CPU.  Only valid for PPI interrupts.
        Also note that the configurability of PPI interrupts is IMPLEMENTATION
        DEFINED and as such not guaranteed to be present (most SoC available
        in 2014 seem to ignore the setting of this flag and use the hardware
        default value).

  reg:
    description: |
      Specifies base physical address(s) and size of the GIC registers. The
      first region is the GIC distributor register base and size. The 2nd region
      is the GIC cpu interface register base and size.

      For GICv2 with virtualization extensions, additional regions are
      required for specifying the base physical address and size of the VGIC
      registers. The first additional region is the GIC virtual interface
      control register base and size. The 2nd additional region is the GIC
      virtual cpu interface register base and size.
    minItems: 2
    maxItems: 4

  ranges: true

  interrupts:
    description: Interrupt source of the parent interrupt controller on
      secondary GICs, or VGIC maintenance interrupt on primary GIC (see
      below).
    maxItems: 1

  cpu-offset:
    description: per-cpu offset within the distributor and cpu interface
      regions, used when the GIC doesn't have banked registers. The offset
      is cpu-offset * cpu-nr.
    $ref: /schemas/types.yaml#/definitions/uint32

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    description: List of names for the GIC clock input(s). Valid clock names
      depend on the GIC variant.
    oneOf:
      - const: ic_clk # for "arm,arm11mp-gic"
      - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
      - items: # for "arm,cortex-a9-gic"
          - const: PERIPHCLK
          - const: PERIPHCLKEN
      - const: clk # for "arm,gic-400" and "nvidia,tegra210"
      - const: gclk #for "arm,pl390"

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg

patternProperties:
  "^v2m@[0-9a-f]+$":
    type: object
    description: |
      * GICv2m extension for MSI/MSI-x support (Optional)

      Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
      This is enabled by specifying v2m sub-node(s).

    properties:
      compatible:
        const: arm,gic-v2m-frame

      msi-controller: true

      reg:
        maxItems: 1
        description: GICv2m MSI interface register base and size

      arm,msi-base-spi:
        description: When the MSI_TYPER register contains an incorrect value,
          this property should contain the SPI base of the MSI frame, overriding
          the HW value.
        $ref: /schemas/types.yaml#/definitions/uint32

      arm,msi-num-spis:
        description: When the MSI_TYPER register contains an incorrect value,
          this property should contain the number of SPIs assigned to the
          frame, overriding the HW value.
        $ref: /schemas/types.yaml#/definitions/uint32

    required:
      - compatible
      - msi-controller
      - reg

    additionalProperties: false

additionalProperties: false

examples:
  - |
    // GICv1
    intc: interrupt-controller@fff11000 {
      compatible = "arm,cortex-a9-gic";
      #interrupt-cells = <3>;
      #address-cells = <1>;
      interrupt-controller;
      reg = <0xfff11000 0x1000>,
            <0xfff10100 0x100>;
    };

  - |
    // GICv2
    interrupt-controller@2c001000 {
      compatible = "arm,cortex-a15-gic";
      #interrupt-cells = <3>;
      interrupt-controller;
      reg = <0x2c001000 0x1000>,
            <0x2c002000 0x2000>,
            <0x2c004000 0x2000>,
            <0x2c006000 0x2000>;
      interrupts = <1 9 0xf04>;
    };

  - |
    // GICv2m extension for MSI/MSI-x support
    interrupt-controller@e1101000 {
      compatible = "arm,gic-400";
      #interrupt-cells = <3>;
      #address-cells = <1>;
      #size-cells = <1>;
      interrupt-controller;
      interrupts = <1 8 0xf04>;
      ranges = <0 0xe1100000 0x100000>;
      reg = <0xe1110000 0x01000>,
            <0xe112f000 0x02000>,
            <0xe1140000 0x10000>,
            <0xe1160000 0x10000>;

      v2m0: v2m@80000 {
        compatible = "arm,gic-v2m-frame";
        msi-controller;
        reg = <0x80000 0x1000>;
      };

      //...

      v2mN: v2m@90000 {
        compatible = "arm,gic-v2m-frame";
        msi-controller;
        reg = <0x90000 0x1000>;
      };
    };
...


code:
* ARM Nested Vector Interrupt Controller (NVIC)

The NVIC provides an interrupt controller that is tightly coupled to
Cortex-M based processor cores.  The NVIC implemented on different SoCs
vary in the number of interrupts and priority bits per interrupt.

Main node required properties:

- compatible : should be one of:
	"arm,v6m-nvic"
	"arm,v7m-nvic"
	"arm,v8m-nvic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source.  The type shall be a <u32> and the value shall be 2.

  The 1st cell contains the interrupt number for the interrupt type.

  The 2nd cell is the priority of the interrupt.

- reg : Specifies base physical address(s) and size of the NVIC registers.
  This is at a fixed address (0xe000e100) and size (0xc00).

- arm,num-irq-priority-bits: The number of priority bits implemented by the
  given SoC

Example:

	intc: interrupt-controller@e000e100 {
		compatible = "arm,v7m-nvic";
		#interrupt-cells = <2>;
		#address-cells = <1>;
		interrupt-controller;
		reg = <0xe000e100 0xc00>;
		arm,num-irq-priority-bits = <4>;
	};


code:
* ARM Versatile FPGA interrupt controller

One or more FPGA IRQ controllers can be synthesized in an ARM reference board
such as the Integrator or Versatile family. The output of these different
controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
instance can handle up to 32 interrupts.

Required properties:
- compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq"
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: The number of cells to define the interrupts.  Must be 1
  as the FPGA IRQ controller has no configuration options for interrupt
  sources.  The cell is a u32 and defines the interrupt number.
- reg: The register bank for the FPGA interrupt controller.
- clear-mask: a u32 number representing the mask written to clear all IRQs
  on the controller at boot for example.
- valid-mask: a u32 number representing a bit mask determining which of
  the interrupts are valid. Unconnected/unused lines are set to 0, and
  the system till not make it possible for devices to request these
  interrupts.

Example:

pic: pic@14000000 {
        compatible = "arm,versatile-fpga-irq";
        #interrupt-cells = <1>;
        interrupt-controller;
        reg = <0x14000000 0x100>;
        clear-mask = <0xffffffff>;
        valid-mask = <0x003fffff>;
};

Optional properties:
- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
  output is simply connected to the input of another IRQ controller,
  then the parent IRQ shall be specified in this property.


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Vectored Interrupt Controller

maintainers:
  - Rob Herring <robh@kernel.org>

description: |+
  One or more Vectored Interrupt Controllers (VIC's) can be connected in an
  ARM system for interrupt routing.  For multiple controllers they can either
  be nested or have the outputs wire-OR'd together.

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    enum:
      - arm,pl190-vic
      - arm,pl192-vic
      - arm,versatile-vic

  interrupt-controller: true

  "#interrupt-cells":
    const: 1
    description:
      The number of cells to define the interrupts.  It must be 1 as the
      VIC has no configuration options for interrupt sources. The single
      cell defines the interrupt number.

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  valid-mask:
    description:
      A one cell big bit mask of valid interrupt sources. Each bit
      represents single interrupt source, starting from source 0 at
      LSb and ending at source 31 at MSb. A bit that is set means
      that the source is wired and clear means otherwise. If unspecified,
      defaults to all valid.
    $ref: /schemas/types.yaml#/definitions/uint32

  valid-wakeup-mask:
    description:
      A one cell big bit mask of interrupt sources that can be configured
      as wake up source for the system. Order of bits is the same as for
      valid-mask property. A set bit means that this interrupt source
      can be configured as a wake up source for the system. If unspecied,
      defaults to all interrupt sources configurable as wake up sources.
    $ref: /schemas/types.yaml#/definitions/uint32

required:
  - compatible
  - reg
  - interrupt-controller
  - "#interrupt-cells"

additionalProperties: false

examples:
  - |
    // PL192 VIC
    vic0: interrupt-controller@60000 {
      compatible = "arm,pl192-vic";
      interrupt-controller;
      #interrupt-cells = <1>;
      reg = <0x60000 0x1000>;

      valid-mask = <0xffffff7f>;
      valid-wakeup-mask = <0x0000ff7f>;
    };

...


code:
Device tree configuration for the I2C Interrupt Controller on the AST24XX and
AST25XX SoCs.

Required Properties:
- #address-cells	: should be 1
- #size-cells 		: should be 1
- #interrupt-cells 	: should be 1
- compatible 		: should be "aspeed,ast2400-i2c-ic"
			  or "aspeed,ast2500-i2c-ic"
- reg			: address start and range of controller
- interrupts		: interrupt number
- interrupt-controller	: denotes that the controller receives and fires
			  new interrupts for child busses

Example:

i2c_ic: interrupt-controller@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	#interrupt-cells = <1>;
	compatible = "aspeed,ast2400-i2c-ic";
	reg = <0x0 0x40>;
	interrupts = <12>;
	interrupt-controller;
};


code:
Aspeed Vectored Interrupt Controller

These bindings are for the Aspeed interrupt controller. The AST2400 and
AST2500 SoC families include a legacy register layout before a re-designed
layout, but the bindings do not prescribe the use of one or the other.

Required properties:

- compatible : "aspeed,ast2400-vic"
               "aspeed,ast2500-vic"

- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The value shall be 1.

Example:

 vic: interrupt-controller@1e6c0080 {
      compatible = "aspeed,ast2400-vic";
      interrupt-controller;
      #interrupt-cells = <1>;
      reg = <0x1e6c0080 0x80>;
 };


code:
Aspeed AST25XX and AST26XX SCU Interrupt Controller

Required Properties:
 - #interrupt-cells		: must be 1
 - compatible			: must be "aspeed,ast2500-scu-ic",
				  "aspeed,ast2600-scu-ic0" or
				  "aspeed,ast2600-scu-ic1"
 - interrupts			: interrupt from the parent controller
 - interrupt-controller		: indicates that the controller receives and
				  fires new interrupts for child busses

Example:

    syscon@1e6e2000 {
        ranges = <0 0x1e6e2000 0x1a8>;

        scu_ic: interrupt-controller@18 {
            #interrupt-cells = <1>;
            compatible = "aspeed,ast2500-scu-ic";
            interrupts = <21>;
            interrupt-controller;
        };
    };


code:
* Advanced Interrupt Controller (AIC)

Required properties:
- compatible: Should be:
    - "atmel,<chip>-aic" where  <chip> can be "at91rm9200", "sama5d2",
      "sama5d3" or "sama5d4"
    - "microchip,<chip>-aic" where <chip> can be "sam9x60"

- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
  The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
  The second cell is used to specify flags:
    bits[3:0] trigger type and level flags:
      1 = low-to-high edge triggered.
      2 = high-to-low edge triggered.
      4 = active high level-sensitive.
      8 = active low level-sensitive.
      Valid combinations are 1, 2, 3, 4, 8.
      Default flag for internal sources should be set to 4 (active high).
  The third cell is used to specify the irq priority from 0 (lowest) to 7
  (highest).
- reg: Should contain AIC registers location and length
- atmel,external-irqs: u32 array of external irqs.

Examples:
	/*
	 * AIC
	 */
	aic: interrupt-controller@fffff000 {
		compatible = "atmel,at91rm9200-aic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0xfffff000 0x200>;
	};

	/*
	 * An interrupt generating device that is wired to an AIC.
	 */
	dma: dma-controller@ffffec00 {
		compatible = "atmel,at91sam9g45-dma";
		reg = <0xffffec00 0x200>;
		interrupts = <21 4 5>;
	};


code:
BCM2835 Top-Level ("ARMCTRL") Interrupt Controller

The BCM2835 contains a custom top-level interrupt controller, which supports
72 interrupt sources using a 2-level register scheme. The interrupt
controller, or the HW block containing it, is referred to occasionally
as "armctrl" in the SoC documentation, hence naming of this binding.

The BCM2836 contains the same interrupt controller with the same
interrupts, but the per-CPU interrupt controller is the root, and an
interrupt there indicates that the ARMCTRL has an interrupt to handle.

Required properties:

- compatible : should be "brcm,bcm2835-armctrl-ic" or
                 "brcm,bcm2836-armctrl-ic"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The value shall be 2.

  The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
  pending" register, or 1/2 respectively for interrupts in the "IRQ pending
  1/2" register.

  The 2nd cell contains the interrupt number within the bank. Valid values
  are 0..7 for bank 0, and 0..31 for bank 1.

Additional required properties for brcm,bcm2836-armctrl-ic:
- interrupts : Specifies the interrupt on the parent for this interrupt
  controller to handle.

The interrupt sources are as follows:

Bank 0:
0: ARM_TIMER
1: ARM_MAILBOX
2: ARM_DOORBELL_0
3: ARM_DOORBELL_1
4: VPU0_HALTED
5: VPU1_HALTED
6: ILLEGAL_TYPE0
7: ILLEGAL_TYPE1

Bank 1:
0: TIMER0
1: TIMER1
2: TIMER2
3: TIMER3
4: CODEC0
5: CODEC1
6: CODEC2
7: VC_JPEG
8: ISP
9: VC_USB
10: VC_3D
11: TRANSPOSER
12: MULTICORESYNC0
13: MULTICORESYNC1
14: MULTICORESYNC2
15: MULTICORESYNC3
16: DMA0
17: DMA1
18: VC_DMA2
19: VC_DMA3
20: DMA4
21: DMA5
22: DMA6
23: DMA7
24: DMA8
25: DMA9
26: DMA10
27: DMA11-14 - shared interrupt for DMA 11 to 14
28: DMAALL - triggers on all dma interrupts (including chanel 15)
29: AUX
30: ARM
31: VPUDMA

Bank 2:
0: HOSTPORT
1: VIDEOSCALER
2: CCP2TX
3: SDC
4: DSI0
5: AVE
6: CAM0
7: CAM1
8: HDMI0
9: HDMI1
10: PIXELVALVE1
11: I2CSPISLV
12: DSI1
13: PWA0
14: PWA1
15: CPR
16: SMI
17: GPIO0
18: GPIO1
19: GPIO2
20: GPIO3
21: VC_I2C
22: VC_SPI
23: VC_I2SPCM
24: VC_SDIO
25: VC_UART
26: SLIMBUS
27: VEC
28: CPG
29: RNG
30: VC_ARASANSDIO
31: AVSPMON

Example:

/* BCM2835, first level */
intc: interrupt-controller {
	compatible = "brcm,bcm2835-armctrl-ic";
	reg = <0x7e00b200 0x200>;
	interrupt-controller;
	#interrupt-cells = <2>;
};

/* BCM2836, second level */
intc: interrupt-controller {
	compatible = "brcm,bcm2836-armctrl-ic";
	reg = <0x7e00b200 0x200>;
	interrupt-controller;
	#interrupt-cells = <2>;

	interrupt-parent = <&local_intc>;
	interrupts = <8>;
};


code:
BCM2836 per-CPU interrupt controller

The BCM2836 has a per-cpu interrupt controller for the timer, PMU
events, and SMP IPIs.  One of the CPUs may receive interrupts for the
peripheral (GPU) events, which chain to the BCM2835-style interrupt
controller.

Required properties:

- compatible:	 	Should be "brcm,bcm2836-l1-intc"
- reg:			Specifies base physical address and size of the
			  registers
- interrupt-controller:	Identifies the node as an interrupt controller
- #interrupt-cells:	Specifies the number of cells needed to encode an
			  interrupt source. The value shall be 2

Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.

The interrupt sources are as follows:

0: CNTPSIRQ
1: CNTPNSIRQ
2: CNTHPIRQ
3: CNTVIRQ
8: GPU_FAST
9: PMU_FAST

Example:

local_intc: local_intc {
	compatible = "brcm,bcm2836-l1-intc";
	reg = <0x40000000 0x100>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupt-parent = <&local_intc>;
};


code:
Broadcom BCM6345-style Level 1 interrupt controller

This block is a first level interrupt controller that is typically connected
directly to one of the HW INT lines on each CPU.

Key elements of the hardware design include:

- 32, 64 or 128 incoming level IRQ lines

- Most onchip peripherals are wired directly to an L1 input

- A separate instance of the register set for each CPU, allowing individual
  peripheral IRQs to be routed to any CPU

- Contains one or more enable/status word pairs per CPU

- No atomic set/clear operations

- No polarity/level/edge settings

- No FIFO or priority encoder logic; software is expected to read all
  2-4 status words to determine which IRQs are pending

Required properties:

- compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc"
- reg: specifies the base physical address and size of the registers;
  the number of supported IRQs is inferred from the size argument
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
  source, should be 1.
- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
  node; valid values depend on the type of parent interrupt controller

If multiple reg ranges and interrupt-parent entries are present on an SMP
system, the driver will allow IRQ SMP affinity to be set up through the
/proc/irq/ interface.  In the simplest possible configuration, only one
reg range and one interrupt-parent is needed.

The driver operates in native CPU endian by default, there is no support for
specifying an alternative endianness.

Example:

periph_intc: interrupt-controller@10000000 {
        compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc";
        reg = <0x10000020 0x20>,
              <0x10000040 0x20>;

        interrupt-controller;
        #interrupt-cells = <1>;

        interrupt-parent = <&cpu_intc>;
        interrupts = <2>, <3>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM7038-style Level 1 interrupt controller

description: >
  This block is a first level interrupt controller that is typically connected
  directly to one of the HW INT lines on each CPU.  Every BCM7xxx set-top chip
  since BCM7038 has contained this hardware.

  Key elements of the hardware design include:

   - 64, 96, 128, or 160 incoming level IRQ lines

   - Most onchip peripherals are wired directly to an L1 input

   - A separate instance of the register set for each CPU, allowing individual
     peripheral IRQs to be routed to any CPU

   - Atomic mask/unmask operations

   - No polarity/level/edge settings

   - No FIFO or priority encoder logic; software is expected to read all
     2-5 status words to determine which IRQs are pending

   If multiple reg ranges and interrupt-parent entries are present on an SMP
   system, the driver will allow IRQ SMP affinity to be set up through the
   /proc/irq/ interface.  In the simplest possible configuration, only one
   reg range and one interrupt-parent is needed.

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    const: brcm,bcm7038-l1-intc

  reg:
    description: >
      Specifies the base physical address and size of the registers
      the number of supported IRQs is inferred from the size argument

  interrupt-controller: true

  "#interrupt-cells":
    const: 1

  interrupts:
    description: >
     Specifies the interrupt line(s) in the interrupt-parent controller node;
     valid values depend on the type of parent interrupt controller

  brcm,irq-can-wake:
    type: boolean
    description: >
      If present, this means the L1 controller can be used as a
      wakeup source for system suspend/resume.

  brcm,int-fwd-mask:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description:
      If present, a bit mask to indicate which interrupts have already been
      configured by the firmware and should be left unmanaged. This should
      have one 32-bit word per status/set/clear/mask group.

required:
  - compatible
  - reg
  - interrupt-controller
  - "#interrupt-cells"
  - interrupts

additionalProperties: false

examples:
  - |
    periph_intc: interrupt-controller@1041a400 {
      compatible = "brcm,bcm7038-l1-intc";
      reg = <0x1041a400 0x30>, <0x1041a600 0x30>;
      interrupt-controller;
      #interrupt-cells = <1>;
      interrupt-parent = <&cpu_intc>;
      interrupts = <2>, <3>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

description: >
  This interrupt controller hardware is a second level interrupt controller that
  is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
  platforms. It can be found on BCM7xxx products starting with BCM7120.

  Such an interrupt controller has the following hardware design:

  - outputs multiple interrupts signals towards its interrupt controller parent

  - controls how some of the interrupts will be flowing, whether they will
    directly output an interrupt signal towards the interrupt controller parent,
    or if they will output an interrupt signal at this 2nd level interrupt
    controller, in particular for UARTs

  - has one 32-bit enable word and one 32-bit status word

  - no atomic set/clear operations

  - not all bits within the interrupt controller actually map to an interrupt

  The typical hardware layout for this controller is represented below:

  2nd level interrupt line		Outputs for the parent controller (e.g: ARM GIC)

  0 -----[ MUX ] ------------|==========> GIC interrupt 75
            \-----------\
                         |
  1 -----[ MUX ] --------)---|==========> GIC interrupt 76
            \------------|
                         |
  2 -----[ MUX ] --------)---|==========> GIC interrupt 77
            \------------|
                         |
  3 ---------------------|
  4 ---------------------|
  5 ---------------------|
  7 ---------------------|---|===========> GIC interrupt 66
  9 ---------------------|
  10 --------------------|
  11 --------------------/

  6 ------------------------\
                            |===========> GIC interrupt 64
  8 ------------------------/

  12 ........................ X
  13 ........................ X           (not connected)
  ..
  31 ........................ X

  The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms
  on many BCM338x/BCM63xx chipsets. It has the following properties:

  - outputs a single interrupt signal to its interrupt controller parent

  - contains one or more enable/status word pairs, which often appear at
    different offsets in different blocks

  - no atomic set/clear operations

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - brcm,bcm7120-l2-intc
          - brcm,bcm3380-l2-intc

  reg:
    minItems: 1
    maxItems: 4
    description: >
      Specifies the base physical address and size of the registers

  interrupt-controller: true

  "#interrupt-cells":
    const: 1

  interrupts:
    minItems: 1
    maxItems: 32

  brcm,int-map-mask:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: >
      32-bits bit mask describing how many and which interrupts are wired to
      this 2nd level interrupt controller, and how they match their respective
      interrupt parents. Should match exactly the number of interrupts
      specified in the 'interrupts' property.

  brcm,irq-can-wake:
    type: boolean
    description: >
      If present, this means the L2 controller can be used as a wakeup source
      for system suspend/resume.

  brcm,int-fwd-mask:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: >
      if present, a bit mask to configure the interrupts which have a mux gate,
      typically UARTs. Setting these bits will make their respective interrupt
      outputs bypass this 2nd level interrupt controller completely; it is
      completely transparent for the interrupt controller parent. This should
      have one 32-bit word per enable/status pair.

additionalProperties: false

required:
  - compatible
  - reg
  - interrupt-controller
  - "#interrupt-cells"
  - interrupts

examples:
  - |
    irq0_intc: interrupt-controller@f0406800 {
      compatible = "brcm,bcm7120-l2-intc";
      interrupt-parent = <&intc>;
      #interrupt-cells = <1>;
      reg = <0xf0406800 0x8>;
      interrupt-controller;
      interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
      brcm,int-map-mask = <0xeb8>, <0x140>;
      brcm,int-fwd-mask = <0x7>;
    };

  - |
    irq1_intc: interrupt-controller@10000020 {
       compatible = "brcm,bcm3380-l2-intc";
       reg = <0x10000024 0x4>, <0x1000002c 0x4>,
             <0x10000020 0x4>, <0x10000028 0x4>;
       interrupt-controller;
       #interrupt-cells = <1>;
       interrupt-parent = <&cpu_intc>;
       interrupts = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/brcm,l2-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Generic Level 2 Interrupt Controller

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - brcm,hif-spi-l2-intc
              - brcm,upg-aux-aon-l2-intc
          - const: brcm,l2-intc
      - items:
          - enum:
              - brcm,bcm2711-l2-intc
          - const: brcm,l2-intc
      - items:
          - const: brcm,bcm7271-l2-intc
      - items:
          - const: brcm,l2-intc

  reg:
    maxItems: 1
    description: >
      Specifies the base physical address and size of the registers

  interrupt-controller: true

  "#interrupt-cells":
    const: 1

  interrupts:
    maxItems: 1

  interrupt-names:
    maxItems: 1

  brcm,irq-can-wake:
    type: boolean
    description: >
      If present, this means the L2 controller can be used as a wakeup source
      for system suspend/resume.

additionalProperties: false

required:
  - compatible
  - reg
  - interrupt-controller
  - "#interrupt-cells"
  - interrupts

examples:
  - |
    hif_intr2_intc: interrupt-controller@f0441000 {
      compatible = "brcm,l2-intc";
      reg = <0xf0441000 0x30>;
      interrupt-controller;
      #interrupt-cells = <1>;
      interrupt-parent = <&intc>;
      interrupts = <0x0 0x20 0x0>;
    };


code:
* Xtensa Interrupt Distributor and Programmable Interrupt Controller (MX)

Required properties:
- compatible: Should be "cdns,xtensa-mx".

Remaining properties have exact same meaning as in Xtensa PIC
(see cdns,xtensa-pic.txt).

Examples:
	pic: pic {
		compatible = "cdns,xtensa-mx";
		/* one cell: internal irq number,
		 * two cells: second cell == 0: internal irq number
		 *            second cell == 1: external irq number
		 */
		#interrupt-cells = <2>;
		interrupt-controller;
	};


code:
* Xtensa built-in Programmable Interrupt Controller (PIC)

Required properties:
- compatible: Should be "cdns,xtensa-pic".
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: The number of cells to define the interrupts.
  It may be either 1 or 2.
  When it's 1, the first cell is the internal IRQ number.
  When it's 2, the first cell is the IRQ number, and the second cell
  specifies whether it's internal (0) or external (1).
  Periferals are usually connected to a fixed external IRQ, but for different
  core variants it may be mapped to different internal IRQ.
  IRQ sensitivity and priority are fixed for each core variant and may not be
  changed at runtime.

Examples:
	pic: pic {
		compatible = "cdns,xtensa-pic";
		/* one cell: internal irq number,
		 * two cells: second cell == 0: internal irq number
		 *            second cell == 1: external irq number
		 */
		#interrupt-cells = <2>;
		interrupt-controller;
	};


code:
Cirrus Logic CLPS711X Interrupt Controller

Required properties:

- compatible: Should be "cirrus,ep7209-intc".
- reg: Specifies base physical address of the registers set.
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
  interrupt source. The value shall be 1.

The interrupt sources are as follows:
ID	Name	Description
---------------------------
1:	BLINT	Battery low (FIQ)
3:	MCINT	Media changed (FIQ)
4:	CSINT	CODEC sound
5:	EINT1	External 1
6:	EINT2	External 2
7:	EINT3	External 3
8:	TC1OI	TC1 under flow
9:	TC2OI	TC2 under flow
10:	RTCMI	RTC compare match
11:	TINT	64Hz tick
12:	UTXINT1	UART1 transmit FIFO half empty
13:	URXINT1	UART1 receive FIFO half full
14:	UMSINT	UART1 modem status changed
15:	SSEOTI	SSI1 end of transfer
16:	KBDINT	Keyboard
17:	SS2RX	SSI2 receive FIFO half or greater full
18:	SS2TX	SSI2 transmit FIFO less than half empty
28:	UTXINT2	UART2 transmit FIFO half empty
29:	URXINT2	UART2 receive FIFO half full
32:	DAIINT	DAI interface (FIQ)

Example:
	intc: interrupt-controller {
		compatible = "cirrus,ep7312-intc", "cirrus,ep7209-intc";
		reg = <0x80000000 0x4000>;
		interrupt-controller;
		#interrupt-cells = <1>;
	};


code:
==============================
C-SKY APB Interrupt Controller
==============================

C-SKY APB Interrupt Controller is a simple soc interrupt controller
on the apb bus and we only use it as root irq controller.

 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.

=============================
intc node bindings definition
=============================

	Description: Describes APB interrupt controller

	PROPERTIES

	- compatible
		Usage: required
		Value type: <string>
		Definition: must be "csky,apb-intc"
				    "csky,dual-apb-intc"
				    "csky,gx6605s-intc"
	- #interrupt-cells
		Usage: required
		Value type: <u32>
		Definition: must be <1>
	- reg
		Usage: required
		Value type: <u32 u32>
		Definition: <phyaddr size> in soc from cpu view
	- interrupt-controller:
		Usage: required
	- csky,support-pulse-signal:
		Usage: select
		Description: to support pulse signal flag

Examples:
---------

	intc: interrupt-controller@500000 {
		compatible = "csky,apb-intc";
		#interrupt-cells = <1>;
		reg = <0x00500000 0x400>;
		interrupt-controller;
	};

	intc: interrupt-controller@500000 {
		compatible = "csky,dual-apb-intc";
		#interrupt-cells = <1>;
		reg = <0x00500000 0x400>;
		interrupt-controller;
	};

	intc: interrupt-controller@500000 {
		compatible = "csky,gx6605s-intc";
		#interrupt-cells = <1>;
		reg = <0x00500000 0x400>;
		interrupt-controller;
	};


code:
===========================================
C-SKY Multi-processors Interrupt Controller
===========================================

C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860
SMP soc, and it also could be used in non-SMP system.

Interrupt number definition:
  0-15  : software irq, and we use 15 as our IPI_IRQ.
 16-31  : private  irq, and we use 16 as the co-processor timer.
 31-1024: common irq for soc ip.

Interrupt trigger mode: (Defined in dt-bindings/interrupt-controller/irq.h)
 IRQ_TYPE_LEVEL_HIGH (default)
 IRQ_TYPE_LEVEL_LOW
 IRQ_TYPE_EDGE_RISING
 IRQ_TYPE_EDGE_FALLING

=============================
intc node bindings definition
=============================

	Description: Describes SMP interrupt controller

	PROPERTIES

	- compatible
		Usage: required
		Value type: <string>
		Definition: must be "csky,mpintc"
	- #interrupt-cells
		Usage: required
		Value type: <u32>
		Definition: <2>
	- interrupt-controller:
		Usage: required

Examples: ("interrupts = <irq_num IRQ_TYPE_XXX>")
---------
#include <dt-bindings/interrupt-controller/irq.h>

	intc: interrupt-controller {
		compatible = "csky,mpintc";
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	device: device-example {
		...
		interrupts = <34 IRQ_TYPE_EDGE_RISING>;
		interrupt-parent = <&intc>;
	};


code:
Conexant Digicolor Interrupt Controller

Required properties:

- compatible : should be "cnxt,cx92755-ic"
- reg : Specifies base physical address and size of the interrupt controller
  registers (IC) area
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The value shall be 1.
- syscon: A phandle to the syscon node describing UC registers

Example:

	intc: interrupt-controller@f0000040 {
		compatible = "cnxt,cx92755-ic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0xf0000040 0x40>;
		syscon = <&uc_regs>;
	};


code:
EZchip NPS Interrupt Controller

Required properties:

- compatible : should be "ezchip,nps400-ic"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The value shall be 1.

Example:

intc: interrupt-controller {
	compatible = "ezchip,nps400-ic";
	interrupt-controller;
	#interrupt-cells = <1>;
};


code:
* Faraday Technologt FTINTC010 interrupt controller

This interrupt controller is a stock IP block from Faraday Technology found
in the Gemini SoCs and other designs.

Required properties:
- compatible: must be one of
  "faraday,ftintc010"
  "cortina,gemini-interrupt-controller" (deprecated)
- reg: The register bank for the interrupt controller.
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: The number of cells to define the interrupts.
  Must be 2 as the controller can specify level or rising edge
  IRQs. The bindings follows the standard binding for controllers
  with two cells specified in
  interrupt-controller/interrupts.txt

Example:

interrupt-controller@48000000 {
	compatible = "faraday,ftintc010"
	reg = <0x48000000 0x1000>;
	interrupt-controller;
	#interrupt-cells = <2>;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,intmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale INTMUX interrupt multiplexer

maintainers:
  - Shawn Guo <shawnguo@kernel.org>
  - NXP Linux Team <linux-imx@nxp.com>

properties:
  compatible:
    const: fsl,imx-intmux

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 8
    description: |
      Should contain the parent interrupt lines (up to 8) used to multiplex
      the input interrupts.

  interrupt-controller: true

  '#interrupt-cells':
    const: 2
    description: |
      The 1st cell is hw interrupt number, the 2nd cell is channel index.

  clocks:
    maxItems: 1

  clock-names:
    const: ipg

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    interrupt-controller@37400000 {
        compatible = "fsl,imx-intmux";
        reg = <0x37400000 0x1000>;
        interrupts = <0 16 4>,
                     <0 17 4>,
                     <0 18 4>,
                     <0 19 4>,
                     <0 20 4>,
                     <0 21 4>,
                     <0 22 4>,
                     <0 23 4>;
        interrupt-controller;
        interrupt-parent = <&gic>;
        #interrupt-cells = <2>;
        clocks = <&clk>;
        clock-names = "ipg";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale IRQSTEER Interrupt Multiplexer

maintainers:
  - Lucas Stach <l.stach@pengutronix.de>

properties:
  compatible:
    oneOf:
      - const: fsl,imx-irqsteer
      - items:
          - const: fsl,imx8m-irqsteer
          - const: fsl,imx-irqsteer

  reg:
    maxItems: 1

  interrupts:
    description: |
      should contain the up to 8 parent interrupt lines used to multiplex
      the input interrupts. They should be specified sequentially from
      output 0 to 7.
    items:
      - description: output interrupt 0
      - description: output interrupt 1
      - description: output interrupt 2
      - description: output interrupt 3
      - description: output interrupt 4
      - description: output interrupt 5
      - description: output interrupt 6
      - description: output interrupt 7
    minItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: ipg

  interrupt-controller: true

  "#interrupt-cells":
    const: 1

  fsl,channel:
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description: |
      u32 value representing the output channel that all input IRQs should be
      steered into.

  fsl,num-irqs:
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description: |
      u32 value representing the number of input interrupts of this channel,
      should be multiple of 32 input interrupts and up to 512 interrupts.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - interrupt-controller
  - "#interrupt-cells"
  - fsl,channel
  - fsl,num-irqs

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mq-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    interrupt-controller@32e2d000 {
        compatible = "fsl,imx-irqsteer";
        reg = <0x32e2d000 0x1000>;
        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
        clock-names = "ipg";
        fsl,channel = <0>;
        fsl,num-irqs = <64>;
        interrupt-controller;
        #interrupt-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Layerscape External Interrupt Controller

maintainers:
  - Shawn Guo <shawnguo@kernel.org>
  - Li Yang <leoyang.li@nxp.com>

description: |
  Some Layerscape SOCs (LS1021A, LS1043A, LS1046A LS1088A, LS208xA,
  LX216xA) support inverting the polarity of certain external interrupt
  lines.

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,ls1021a-extirq
          - fsl,ls1043a-extirq
          - fsl,ls1088a-extirq
      - items:
          - enum:
              - fsl,ls1046a-extirq
          - const: fsl,ls1043a-extirq
      - items:
          - enum:
              - fsl,ls2080a-extirq
              - fsl,lx2160a-extirq
          - const: fsl,ls1088a-extirq

  '#interrupt-cells':
    const: 2

  '#address-cells':
    const: 0

  interrupt-controller: true

  reg:
    maxItems: 1
    description:
      Specifies the Interrupt Polarity Control Register (INTPCR) in the
      SCFG or the External Interrupt Control Register (IRQCR) in the ISC.

  interrupt-map:
    description: Specifies the mapping from external interrupts to GIC interrupts.

  interrupt-map-mask: true

required:
  - compatible
  - '#interrupt-cells'
  - '#address-cells'
  - interrupt-controller
  - reg
  - interrupt-map
  - interrupt-map-mask

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,ls1021a-extirq
    then:
      properties:
        interrupt-map:
          minItems: 6
          maxItems: 6
        interrupt-map-mask:
          items:
            - const: 0x7
            - const: 0
  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,ls1043a-extirq
              - fsl,ls1046a-extirq
              - fsl,ls1088a-extirq
              - fsl,ls2080a-extirq
              - fsl,lx2160a-extirq
    then:
      properties:
        interrupt-map:
          minItems: 12
          maxItems: 12
        interrupt-map-mask:
          items:
            - const: 0xf
            - const: 0

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    interrupt-controller@1ac {
            compatible = "fsl,ls1021a-extirq";
            #interrupt-cells = <2>;
            #address-cells = <0>;
            interrupt-controller;
            reg = <0x1ac 4>;
            interrupt-map =
                    <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
                    <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
                    <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
                    <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
                    <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
                    <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-map-mask = <0x7 0x0>;
    };


code:
* Freescale Layerscape SCFG PCIe MSI controller

Required properties:

- compatible: should be "fsl,<soc-name>-msi" to identify
	      Layerscape PCIe MSI controller block such as:
              "fsl,ls1021a-msi"
              "fsl,ls1043a-msi"
              "fsl,ls1046a-msi"
              "fsl,ls1043a-v1.1-msi"
              "fsl,ls1012a-msi"
- msi-controller: indicates that this is a PCIe MSI controller node
- reg: physical base address of the controller and length of memory mapped.
- interrupts: an interrupt to the parent interrupt controller.

This interrupt controller hardware is a second level interrupt controller that
is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
platforms. If interrupt-parent is not provided, the default parent interrupt
controller will be used.
Each PCIe node needs to have property msi-parent that points to
MSI controller node

Examples:

	msi1: msi-controller@1571000 {
		compatible = "fsl,ls1043a-msi";
		reg = <0x0 0x1571000 0x0 0x8>,
		msi-controller;
		interrupts = <0 116 0x4>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller

maintainers:
  - Frank Li <Frank.Li@nxp.com>

description: |
  The Messaging Unit module enables two processors within the SoC to
  communicate and coordinate by passing messages (e.g. data, status
  and control) through the MU interface. The MU also provides the ability
  for one processor (A side) to signal the other processor (B side) using
  interrupts.

  Because the MU manages the messaging between processors, the MU uses
  different clocks (from each side of the different peripheral buses).
  Therefore, the MU must synchronize the accesses from one side to the
  other. The MU accomplishes synchronization using two sets of matching
  registers (Processor A-side, Processor B-side).

  MU can work as msi interrupt controller to do doorbell

allOf:
  - $ref: /schemas/interrupt-controller/msi-controller.yaml#

properties:
  compatible:
    enum:
      - fsl,imx6sx-mu-msi
      - fsl,imx7ulp-mu-msi
      - fsl,imx8ulp-mu-msi
      - fsl,imx8ulp-mu-msi-s4

  reg:
    items:
      - description: a side register base address
      - description: b side register base address

  reg-names:
    items:
      - const: processor-a-side
      - const: processor-b-side

  interrupts:
    description: a side interrupt number.
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    items:
      - description: a side power domain
      - description: b side power domain

  power-domain-names:
    items:
      - const: processor-a-side
      - const: processor-b-side

  interrupt-controller: true

  msi-controller: true

  "#msi-cells":
    const: 0

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - msi-controller
  - "#msi-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/firmware/imx/rsrc.h>

    msi-controller@5d270000 {
        compatible = "fsl,imx6sx-mu-msi";
        msi-controller;
        #msi-cells = <0>;
        interrupt-controller;
        reg = <0x5d270000 0x10000>,     /* A side */
              <0x5d300000 0x10000>;     /* B side */
        reg-names = "processor-a-side", "processor-b-side";
        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
        power-domains = <&pd IMX_SC_R_MU_12A>,
                        <&pd IMX_SC_R_MU_12B>;
        power-domain-names = "processor-a-side", "processor-b-side";
    };


code:
Android Goldfish PIC

Android Goldfish programmable interrupt device used by Android
emulator.

Required properties:

- compatible : should contain "google,goldfish-pic"
- reg        : <registers mapping>
- interrupts : <interrupt mapping>

Example for mips when used in cascade mode:

        cpuintc {
                #interrupt-cells = <0x1>;
                #address-cells = <0>;
                interrupt-controller;
                compatible = "mti,cpu-interrupt-controller";
        };

        interrupt-controller@1f000000 {
                compatible = "google,goldfish-pic";
                reg = <0x1f000000 0x1000>;

                interrupt-controller;
                #interrupt-cells = <0x1>;

                interrupt-parent = <&cpuintc>;
                interrupts = <0x2>;
        };


code:
Hisilicon mbigen device tree bindings.
=======================================

Mbigen means: message based interrupt generator.

MBI is kind of msi interrupt only used on Non-PCI devices.

To reduce the wired interrupt number connected to GIC,
Hisilicon designed mbigen to collect and generate interrupt.

Non-pci devices can connect to mbigen and generate the
interrupt by writing ITS register.

The mbigen chip and devices connect to mbigen have the following properties:

Mbigen main node required properties:
-------------------------------------------
- compatible: Should be "hisilicon,mbigen-v2"

- reg: Specifies the base physical address and size of the Mbigen
  registers.

Mbigen sub node required properties:
------------------------------------------
- interrupt controller: Identifies the node as an interrupt controller

- msi-parent: Specifies the MSI controller this mbigen use.
  For more detail information,please refer to the generic msi-parent binding in
  Documentation/devicetree/bindings/interrupt-controller/msi.txt.

- num-pins: the total number of pins implemented in this Mbigen
  instance.

- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The value must be 2.

  The 1st cell is hardware pin number of the interrupt.This number is local to
  each mbigen chip and in the range from 0 to the maximum interrupts number
  of the mbigen.

  The 2nd cell is the interrupt trigger type.
	The value of this cell should be:
	1: rising edge triggered
	or
	4: high level triggered

Examples:

	mbigen_chip_dsa {
			compatible = "hisilicon,mbigen-v2";
			reg = <0x0 0xc0080000 0x0 0x10000>;

			mbigen_gmac:intc_gmac {
				interrupt-controller;
				msi-parent = <&its_dsa 0x40b1c>;
				num-pins = <9>;
				#interrupt-cells = <2>;
			};

			mbigen_i2c:intc_i2c {
				interrupt-controller;
				msi-parent = <&its_dsa 0x40b0e>;
				num-pins = <2>;
				#interrupt-cells = <2>;
			};
	};

Devices connect to mbigen required properties:
----------------------------------------------------
-interrupts:Specifies the interrupt source.
 For the specific information of each cell in this property,please refer to
 the "interrupt-cells" description mentioned above.

Examples:
	gmac0: ethernet@c2080000 {
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0xc2080000 0 0x20000>,
		      <0 0xc0000000 0 0x1000>;
		interrupt-parent  = <&mbigen_device_gmac>;
		interrupts =	<656 1>,
				<657 1>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/idt,32434-pic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: IDT 79RC32434 Interrupt Controller

maintainers:
  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  "#interrupt-cells":
    const: 1

  compatible:
    const: idt,32434-pic

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-controller: true

required:
  - "#interrupt-cells"
  - compatible
  - reg
  - interrupt-controller
  - interrupts

additionalProperties: false

examples:
  - |
    idtpic3: interrupt-controller@3800c {
        compatible = "idt,32434-pic";
        reg = <0x3800c 0x0c>;

        interrupt-controller;
        #interrupt-cells = <1>;

        interrupt-parent = <&cpuintc>;
        interrupts = <3>;
    };

...


code:
* ImgTec Powerdown Controller (PDC) Interrupt Controller Binding

This binding specifies what properties must be available in the device tree
representation of a PDC IRQ controller. This has a number of input interrupt
lines which can wake the system, and are passed on through output interrupt
lines.

Required properties:

    - compatible: Specifies the compatibility list for the interrupt controller.
      The type shall be <string> and the value shall include "img,pdc-intc".

    - reg: Specifies the base PDC physical address(s) and size(s) of the
      addressable register space. The type shall be <prop-encoded-array>.

    - interrupt-controller: The presence of this property identifies the node
      as an interrupt controller. No property value shall be defined.

    - #interrupt-cells: Specifies the number of cells needed to encode an
      interrupt source. The type shall be a <u32> and the value shall be 2.

    - num-perips: Number of waking peripherals.

    - num-syswakes: Number of SysWake inputs.

    - interrupts: List of interrupt specifiers. The first specifier shall be the
      shared SysWake interrupt, and remaining specifies shall be PDC peripheral
      interrupts in order.

* Interrupt Specifier Definition

  Interrupt specifiers consists of 2 cells encoded as follows:

    - <1st-cell>: The interrupt-number that identifies the interrupt source.
                    0-7:  Peripheral interrupts
                    8-15: SysWake interrupts

    - <2nd-cell>: The level-sense information, encoded using the Linux interrupt
                  flags as follows (only 4 valid for peripheral interrupts):
                    0 = none (decided by software)
                    1 = low-to-high edge triggered
                    2 = high-to-low edge triggered
                    3 = both edge triggered
                    4 = active-high level-sensitive (required for perip irqs)
                    8 = active-low level-sensitive

* Examples

Example 1:

	/*
	 * TZ1090 PDC block
	 */
	pdc: pdc@02006000 {
		// This is an interrupt controller node.
		interrupt-controller;

		// Three cells to encode interrupt sources.
		#interrupt-cells = <2>;

		// Offset address of 0x02006000 and size of 0x1000.
		reg = <0x02006000 0x1000>;

		// Compatible with Meta hardware trigger block.
		compatible = "img,pdc-intc";

		// Three peripherals are connected.
		num-perips = <3>;

		// Four SysWakes are connected.
		num-syswakes = <4>;

		interrupts = <18 4 /* level */>, /* Syswakes */
			     <30 4 /* level */>, /* Peripheral 0 (RTC) */
			     <29 4 /* level */>, /* Peripheral 1 (IR) */
			     <31 4 /* level */>; /* Peripheral 2 (WDT) */
	};

Example 2:

	/*
	 * An SoC peripheral that is wired through the PDC.
	 */
	rtc0 {
		// The interrupt controller that this device is wired to.
		interrupt-parent = <&pdc>;

		// Interrupt source Peripheral 0
		interrupts = <0   /* Peripheral 0 (RTC) */
		              4>  /* IRQ_TYPE_LEVEL_HIGH */
	};

Example 3:

	/*
	 * An interrupt generating device that is wired to a SysWake pin.
	 */
	touchscreen0 {
		// The interrupt controller that this device is wired to.
		interrupt-parent = <&pdc>;

		// Interrupt source SysWake 0 that is active-low level-sensitive
		interrupts = <8 /* SysWake0 */
			      8 /* IRQ_TYPE_LEVEL_LOW */>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/ingenic,intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs interrupt controller devicetree bindings

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

properties:
  $nodename:
    pattern: "^interrupt-controller@[0-9a-f]+$"

  compatible:
    oneOf:
      - enum:
          - ingenic,jz4740-intc
          - ingenic,jz4760-intc
          - ingenic,jz4780-intc
      - items:
          - enum:
              - ingenic,jz4775-intc
              - ingenic,jz4770-intc
              - ingenic,jz4760b-intc
          - const: ingenic,jz4760-intc
      - items:
          - const: ingenic,x1000-intc
          - const: ingenic,jz4780-intc
      - items:
          - const: ingenic,jz4725b-intc
          - const: ingenic,jz4740-intc

  "#interrupt-cells":
    const: 1

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-controller: true

required:
  - compatible
  - reg
  - interrupts
  - "#interrupt-cells"
  - interrupt-controller

additionalProperties: false

examples:
  - |
    intc: interrupt-controller@10001000 {
      compatible = "ingenic,jz4770-intc", "ingenic,jz4760-intc";
      reg = <0x10001000 0x40>;

      interrupt-controller;
      #interrupt-cells = <1>;

      interrupt-parent = <&cpuintc>;
      interrupts = <2>;
    };