code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP FMan MAC

maintainers:
  - Madalin Bucur <madalin.bucur@nxp.com>

description: |
  Each FMan has several MACs, each implementing an Ethernet interface. Earlier
  versions of FMan used the Datapath Three Speed Ethernet Controller (dTSEC) for
  10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
  (10GEC) for 10 Gbit/s speeds. Later versions of FMan use the Multirate
  Ethernet Media Access Controller (mEMAC) to handle all speeds.

properties:
  compatible:
    enum:
      - fsl,fman-dtsec
      - fsl,fman-xgec
      - fsl,fman-memac

  cell-index:
    maximum: 64
    description: |
      FManV2:
      register[bit]           MAC             cell-index
      ============================================================
      FM_EPI[16]              XGEC            8
      FM_EPI[16+n]            dTSECn          n-1
      FM_NPI[11+n]            dTSECn          n-1
              n = 1,..,5

      FManV3:
      register[bit]           MAC             cell-index
      ============================================================
      FM_EPI[16+n]            mEMACn          n-1
      FM_EPI[25]              mEMAC10         9

      FM_NPI[11+n]            mEMACn          n-1
      FM_NPI[10]              mEMAC10         9
      FM_NPI[11]              mEMAC9          8
              n = 1,..8

      FM_EPI and FM_NPI are located in the FMan memory map.

      2. SoC registers:

      - P2041, P3041, P4080 P5020, P5040:
      register[bit]           FMan            MAC             cell
                              Unit                            index
      ============================================================
      DCFG_DEVDISR2[7]        1               XGEC            8
      DCFG_DEVDISR2[7+n]      1               dTSECn          n-1
      DCFG_DEVDISR2[15]       2               XGEC            8
      DCFG_DEVDISR2[15+n]     2               dTSECn          n-1
              n = 1,..5

      - T1040, T2080, T4240, B4860:
      register[bit]                   FMan    MAC             cell
                                      Unit                    index
      ============================================================
      DCFG_CCSR_DEVDISR2[n-1]         1       mEMACn          n-1
      DCFG_CCSR_DEVDISR2[11+n]        2       mEMACn          n-1
              n = 1,..6,9,10

      EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
      the specific SoC "Device Configuration/Pin Control" Memory
      Map.

  reg:
    maxItems: 1

  fsl,fman-ports:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 2
    description: |
      An array of two references: the first is the FMan RX port and the second
      is the TX port used by this MAC.

  ptp-timer:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: A reference to the IEEE1588 timer

  phys:
    description: A reference to the SerDes lane(s)
    maxItems: 1

  phy-names:
    items:
      - const: serdes

  pcsphy-handle:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 1
    maxItems: 3
    deprecated: true
    description: See pcs-handle.

  pcs-handle:
    minItems: 1
    maxItems: 3
    description: |
      A reference to the various PCSs (typically found on the SerDes). If
      pcs-handle-names is absent, and phy-connection-type is "xgmii", then the first
      reference will be assumed to be for "xfi". Otherwise, if pcs-handle-names is
      absent, then the first reference will be assumed to be for "sgmii".

  pcs-handle-names:
    minItems: 1
    maxItems: 3
    items:
      enum:
        - sgmii
        - qsgmii
        - xfi
    description: The type of each PCS in pcsphy-handle.

  tbi-handle:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: A reference to the (TBI-based) PCS

required:
  - compatible
  - cell-index
  - reg
  - fsl,fman-ports
  - ptp-timer

dependencies:
  pcs-handle-names:
    - pcs-handle

allOf:
  - $ref: ethernet-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: fsl,fman-dtsec
    then:
      required:
        - tbi-handle

unevaluatedProperties: false

examples:
  - |
    ethernet@e0000 {
            compatible = "fsl,fman-dtsec";
            cell-index = <0>;
            reg = <0xe0000 0x1000>;
            fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
            ptp-timer = <&ptp_timer>;
            tbi-handle = <&tbi0>;
    };
  - |
    ethernet@e8000 {
            cell-index = <4>;
            compatible = "fsl,fman-memac";
            reg = <0xe8000 0x1000>;
            fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
            ptp-timer = <&ptp_timer0>;
            pcs-handle = <&pcsphy4>, <&qsgmiib_pcs1>;
            pcs-handle-names = "sgmii", "qsgmii";
            phys = <&serdes1 1>;
            phy-names = "serdes";
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DPAA2 MAC bindings

maintainers:
  - Ioana Ciornei <ioana.ciornei@nxp.com>

description:
  This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
  located under the 'dpmacs' node for the fsl-mc bus DTS node.

allOf:
  - $ref: "ethernet-controller.yaml#"

properties:
  compatible:
    const: fsl,qoriq-mc-dpmac

  reg:
    maxItems: 1
    description: The DPMAC number

  phy-handle: true

  phy-connection-type: true

  phy-mode: true

  pcs-handle:
    maxItems: 1
    description:
      A reference to a node representing a PCS PHY device found on
      the internal MDIO bus.

  managed: true

required:
  - reg

additionalProperties: false

examples:
  - |
    dpmacs {
      #address-cells = <1>;
      #size-cells = <0>;

      ethernet@4 {
        compatible = "fsl,qoriq-mc-dpmac";
        reg = <0x4>;
        phy-handle = <&mdio1_phy6>;
        phy-connection-type = "qsgmii";
        managed = "in-band-status";
        pcs-handle = <&pcs3_1>;
      };
    };

repo_name: angery/linux


code:
* ENETC ethernet device tree bindings

Depending on board design and ENETC port type (internal or
external) there are two supported link modes specified by
below device tree bindings.

Required properties:

- reg		: Specifies PCIe Device Number and Function
		  Number of the ENETC endpoint device, according
		  to parent node bindings.
- compatible	: Should be "fsl,enetc".

1. The ENETC external port is connected to a MDIO configurable phy

1.1. Using the local ENETC Port MDIO interface

In this case, the ENETC node should include a "mdio" sub-node
that in turn should contain the "ethernet-phy" node describing the
external phy.  Below properties are required, their bindings
already defined in Documentation/devicetree/bindings/net/ethernet.txt or
Documentation/devicetree/bindings/net/phy.txt.

Required:

- phy-handle		: Phandle to a PHY on the MDIO bus.
			  Defined in ethernet.txt.

- phy-connection-type	: Defined in ethernet.txt.

- mdio			: "mdio" node, defined in mdio.txt.

- ethernet-phy		: "ethernet-phy" node, defined in phy.txt.

Example:

	ethernet@0,0 {
		compatible = "fsl,enetc";
		reg = <0x000000 0 0 0 0>;
		phy-handle = <&sgmii_phy0>;
		phy-connection-type = "sgmii";

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;
			sgmii_phy0: ethernet-phy@2 {
				reg = <0x2>;
			};
		};
	};

1.2. Using the central MDIO PCIe endpoint device

In this case, the mdio node should be defined as another PCIe
endpoint node, at the same level with the ENETC port nodes.

Required properties:

- reg		: Specifies PCIe Device Number and Function
		  Number of the ENETC endpoint device, according
		  to parent node bindings.
- compatible	: Should be "fsl,enetc-mdio".

The remaining required mdio bus properties are standard, their bindings
already defined in Documentation/devicetree/bindings/net/mdio.txt.

Example:

	ethernet@0,0 {
		compatible = "fsl,enetc";
		reg = <0x000000 0 0 0 0>;
		phy-handle = <&sgmii_phy0>;
		phy-connection-type = "sgmii";
	};

	mdio@0,3 {
		compatible = "fsl,enetc-mdio";
		reg = <0x000300 0 0 0 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		sgmii_phy0: ethernet-phy@2 {
			reg = <0x2>;
		};
	};

2. The ENETC port is an internal port or has a fixed-link external
connection

In this case, the ENETC port node defines a fixed link connection,
as specified by Documentation/devicetree/bindings/net/fixed-link.txt.

Required:

- fixed-link	: "fixed-link" node, defined in "fixed-link.txt".

Example:
	ethernet@0,2 {
		compatible = "fsl,enetc";
		reg = <0x000200 0 0 0 0>;
		fixed-link {
			speed = <1000>;
			full-duplex;
		};
	};

* Integrated Endpoint Register Block bindings

Optionally, the fsl_enetc driver can probe on the Integrated Endpoint Register
Block, which preconfigures the FIFO limits for the ENETC ports. This is a node
with the following properties:

- reg		: Specifies the address in the SoC memory space.
- compatible	: Must be "fsl,ls1028a-enetc-ierb".

Example:
	ierb@1f0800000 {
		compatible = "fsl,ls1028a-enetc-ierb";
		reg = <0x01 0xf0800000 0x0 0x10000>;
	};


code:
=============================================================================
Freescale Frame Manager Device Bindings

CONTENTS
  - FMan Node
  - FMan Port Node
  - FMan MURAM Node
  - FMan dTSEC/XGEC/mEMAC Node
  - FMan IEEE 1588 Node
  - FMan MDIO Node
  - Example

=============================================================================
FMan Node

DESCRIPTION

Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
etc.) the FMan node will have child nodes for each of them.

PROPERTIES

- compatible
		Usage: required
		Value type: <stringlist>
		Definition: Must include "fsl,fman"
		FMan version can be determined via FM_IP_REV_1 register in the
		FMan block. The offset is 0xc4 from the beginning of the
		Frame Processing Manager memory map (0xc3000 from the
		beginning of the FMan node).

- cell-index
		Usage: required
		Value type: <u32>
		Definition: Specifies the index of the FMan unit.

		The cell-index value may be used by the SoC, to identify the
		FMan unit in the SoC memory map. In the table below,
		there's a description of the cell-index use in each SoC:

		- P1023:
		register[bit]			FMan unit	cell-index
		============================================================
		DEVDISR[1]			1		0

		- P2041, P3041, P4080 P5020, P5040:
		register[bit]			FMan unit	cell-index
		============================================================
		DCFG_DEVDISR2[6]		1		0
		DCFG_DEVDISR2[14]		2		1
			(Second FM available only in P4080 and P5040)

		- B4860, T1040, T2080, T4240:
		register[bit]			FMan unit	cell-index
		============================================================
		DCFG_CCSR_DEVDISR2[24]		1		0
		DCFG_CCSR_DEVDISR2[25]		2		1
			(Second FM available only in T4240)

		DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
		the specific SoC "Device Configuration/Pin Control" Memory
		Map.

- reg
		Usage: required
		Value type: <prop-encoded-array>
		Definition: A standard property. Specifies the offset of the
		following configuration registers:
		- BMI configuration registers.
		- QMI configuration registers.
		- DMA configuration registers.
		- FPM configuration registers.
		- FMan controller configuration registers.

- ranges
		Usage: required
		Value type: <prop-encoded-array>
		Definition: A standard property.

- clocks
		Usage: required
		Value type: <prop-encoded-array>
		Definition: phandle for the fman input clock.

- clock-names
		usage: required
		Value type: <stringlist>
		Definition: "fmanclk" for the fman input clock.

- interrupts
		Usage: required
		Value type: <prop-encoded-array>
		Definition: A pair of IRQs are specified in this property.
		The first element is associated with the event interrupts and
		the second element is associated with the error interrupts.

- fsl,qman-channel-range
		Usage: required
		Value type: <prop-encoded-array>
		Definition: Specifies the range of the available dedicated
		channels in the FMan. The first cell specifies the beginning
		of the range and the second cell specifies the number of
		channels.
		Further information available at:
		"Work Queue (WQ) Channel Assignments in the QMan" section
		in DPAA Reference Manual.

- fsl,qman
- fsl,bman
		Usage: required
		Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt

- fsl,erratum-a050385
		Usage: optional
		Value type: boolean
		Definition: A boolean property. Indicates the presence of the
		erratum A050385 which indicates that DMA transactions that are
		split can result in a FMan lock.

=============================================================================
FMan MURAM Node

DESCRIPTION

FMan Internal memory - shared between all the FMan modules.
It contains data structures that are common and written to or read by
the modules.
FMan internal memory is split into the following parts:
	Packet buffering (Tx/Rx FIFOs)
	Frames internal context

PROPERTIES

- compatible
		Usage: required
		Value type: <stringlist>
		Definition: Must include "fsl,fman-muram"

- ranges
		Usage: required
		Value type: <prop-encoded-array>
		Definition: A standard property.
		Specifies the multi-user memory offset and the size within
		the FMan.

EXAMPLE

muram@0 {
	compatible = "fsl,fman-muram";
	ranges = <0 0x000000 0x28000>;
};

=============================================================================
FMan Port Node

DESCRIPTION

The Frame Manager (FMan) supports several types of hardware ports:
	Ethernet receiver (RX)
	Ethernet transmitter (TX)
	Offline/Host command (O/H)

PROPERTIES

- compatible
		Usage: required
		Value type: <stringlist>
		Definition: A standard property.
		Must include one of the following:
			- "fsl,fman-v2-port-oh" for FManV2 OH ports
			- "fsl,fman-v2-port-rx" for FManV2 RX ports
			- "fsl,fman-v2-port-tx" for FManV2 TX ports
			- "fsl,fman-v3-port-oh" for FManV3 OH ports
			- "fsl,fman-v3-port-rx" for FManV3 RX ports
			- "fsl,fman-v3-port-tx" for FManV3 TX ports

- cell-index
		Usage: required
		Value type: <u32>
		Definition: Specifies the hardware port id.
		Each hardware port on the FMan has its own hardware PortID.
		Super set of all hardware Port IDs available at FMan Reference
		Manual under "FMan Hardware Ports in Freescale Devices" table.

		Each hardware port is assigned a 4KB, port-specific page in
		the FMan hardware port memory region (which is part of the
		FMan memory map). The first 4 KB in the FMan hardware ports
		memory region is used for what are called common registers.
		The subsequent 63 4KB pages are allocated to the hardware
		ports.
		The page of a specific port is determined by the cell-index.

- reg
		Usage: required
		Value type: <prop-encoded-array>
		Definition: There is one reg region describing the port
		configuration registers.

- fsl,fman-10g-port
		Usage: optional
		Value type: boolean
		Definition: The default port rate is 1G.
		If this property exists, the port is s 10G port.

- fsl,fman-best-effort-port
		Usage: optional
		Value type: boolean
		Definition: Can be defined only if 10G-support is set.
		This property marks a best-effort 10G port (10G port that
		may not be capable of line rate).

EXAMPLE

port@a8000 {
	cell-index = <0x28>;
	compatible = "fsl,fman-v2-port-tx";
	reg = <0xa8000 0x1000>;
};

port@88000 {
	cell-index = <0x8>;
	compatible = "fsl,fman-v2-port-rx";
	reg = <0x88000 0x1000>;
};

port@81000 {
	cell-index = <0x1>;
	compatible = "fsl,fman-v2-port-oh";
	reg = <0x81000 0x1000>;
};

=============================================================================
FMan dTSEC/XGEC/mEMAC Node

Refer to Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml

============================================================================
FMan IEEE 1588 Node

Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt

=============================================================================
FMan MDIO Node

DESCRIPTION

The MDIO is a bus to which the PHY devices are connected.

PROPERTIES

- compatible
		Usage: required
		Value type: <stringlist>
		Definition: A standard property.
		Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
		Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
		Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
		FMan v3.

- reg
		Usage: required
		Value type: <prop-encoded-array>
		Definition: A standard property.

- clocks
		Usage: optional
		Value type: <phandle>
		Definition: A reference to the input clock of the controller
		from which the MDC frequency is derived.

- clock-frequency
		Usage: optional
		Value type: <u32>
		Definition: Specifies the external MDC frequency, in Hertz, to
		be used. Requires that the input clock is specified in the
		"clocks" property. See also: mdio.yaml.

- suppress-preamble
		Usage: optional
		Value type: <boolean>
		Definition: Disable generation of preamble bits. See also:
		mdio.yaml.

- interrupts
		Usage: required for external MDIO
		Value type: <prop-encoded-array>
		Definition: Event interrupt of external MDIO controller.

- fsl,fman-internal-mdio
		Usage: required for internal MDIO
		Value type: boolean
		Definition: Fman has internal MDIO for internal PCS(Physical
		Coding Sublayer) PHYs and external MDIO for external PHYs.
		The settings and programming routines for internal/external
		MDIO are different. Must be included for internal MDIO.

- fsl,erratum-a009885
		Usage: optional
		Value type: <boolean>
		Definition: Indicates the presence of the A009885
		erratum describing that the contents of MDIO_DATA may
		become corrupt unless it is read within 16 MDC cycles
		of MDIO_CFG[BSY] being cleared, when performing an
		MDIO read operation.

- fsl,erratum-a011043
		Usage: optional
		Value type: <boolean>
		Definition: Indicates the presence of the A011043 erratum
		describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely
		set when reading internal PCS registers. MDIO reads to
		internal PCS registers may result in having the
		MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and
		read data (MDIO_DATA[MDIO_DATA]) is correct.
		Software may get false read error when reading internal
		PCS registers through MDIO. As a workaround, all internal
		MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.

For internal PHY device on internal mdio bus, a PHY node should be created.
See the definition of the PHY node in booting-without-of.txt for an
example of how to define a PHY (Internal PHY has no interrupt line).
- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.
  The PCS PHY address should correspond to the value of the appropriate
  MDEV_PORT.

EXAMPLE

Example for FMan v2 external MDIO:

mdio@f1000 {
	compatible = "fsl,fman-xmdio";
	reg = <0xf1000 0x1000>;
	interrupts = <101 2 0 0>;
};

Example for FMan v2 internal MDIO:

mdio@e3120 {
	compatible = "fsl,fman-mdio";
	reg = <0xe3120 0xee0>;
	fsl,fman-internal-mdio;

	tbi1: tbi-phy@8 {
		reg = <0x8>;
		device_type = "tbi-phy";
	};
};

Example for FMan v3 internal MDIO:

mdio@f1000 {
	compatible = "fsl,fman-memac-mdio";
	reg = <0xf1000 0x1000>;
	fsl,fman-internal-mdio;

	pcsphy6: ethernet-phy@0 {
		reg = <0x0>;
	};
};

=============================================================================
Example

fman@400000 {
	#address-cells = <1>;
	#size-cells = <1>;
	cell-index = <1>;
	compatible = "fsl,fman"
	ranges = <0 0x400000 0x100000>;
	reg = <0x400000 0x100000>;
	clocks = <&fman_clk>;
	clock-names = "fmanclk";
	interrupts = <
		96 2 0 0
		16 2 1 1>;
	fsl,qman-channel-range = <0x40 0xc>;

	muram@0 {
		compatible = "fsl,fman-muram";
		reg = <0x0 0x28000>;
	};

	port@81000 {
		cell-index = <1>;
		compatible = "fsl,fman-v2-port-oh";
		reg = <0x81000 0x1000>;
	};

	port@82000 {
		cell-index = <2>;
		compatible = "fsl,fman-v2-port-oh";
		reg = <0x82000 0x1000>;
	};

	port@83000 {
		cell-index = <3>;
		compatible = "fsl,fman-v2-port-oh";
		reg = <0x83000 0x1000>;
	};

	port@84000 {
		cell-index = <4>;
		compatible = "fsl,fman-v2-port-oh";
		reg = <0x84000 0x1000>;
	};

	port@85000 {
		cell-index = <5>;
		compatible = "fsl,fman-v2-port-oh";
		reg = <0x85000 0x1000>;
	};

	port@86000 {
		cell-index = <6>;
		compatible = "fsl,fman-v2-port-oh";
		reg = <0x86000 0x1000>;
	};

	fman1_rx_0x8: port@88000 {
		cell-index = <0x8>;
		compatible = "fsl,fman-v2-port-rx";
		reg = <0x88000 0x1000>;
	};

	fman1_rx_0x9: port@89000 {
		cell-index = <0x9>;
		compatible = "fsl,fman-v2-port-rx";
		reg = <0x89000 0x1000>;
	};

	fman1_rx_0xa: port@8a000 {
		cell-index = <0xa>;
		compatible = "fsl,fman-v2-port-rx";
		reg = <0x8a000 0x1000>;
	};

	fman1_rx_0xb: port@8b000 {
		cell-index = <0xb>;
		compatible = "fsl,fman-v2-port-rx";
		reg = <0x8b000 0x1000>;
	};

	fman1_rx_0xc: port@8c000 {
		cell-index = <0xc>;
		compatible = "fsl,fman-v2-port-rx";
		reg = <0x8c000 0x1000>;
	};

	fman1_rx_0x10: port@90000 {
		cell-index = <0x10>;
		compatible = "fsl,fman-v2-port-rx";
		reg = <0x90000 0x1000>;
	};

	fman1_tx_0x28: port@a8000 {
		cell-index = <0x28>;
		compatible = "fsl,fman-v2-port-tx";
		reg = <0xa8000 0x1000>;
	};

	fman1_tx_0x29: port@a9000 {
		cell-index = <0x29>;
		compatible = "fsl,fman-v2-port-tx";
		reg = <0xa9000 0x1000>;
	};

	fman1_tx_0x2a: port@aa000 {
		cell-index = <0x2a>;
		compatible = "fsl,fman-v2-port-tx";
		reg = <0xaa000 0x1000>;
	};

	fman1_tx_0x2b: port@ab000 {
		cell-index = <0x2b>;
		compatible = "fsl,fman-v2-port-tx";
		reg = <0xab000 0x1000>;
	};

	fman1_tx_0x2c: port@ac0000 {
		cell-index = <0x2c>;
		compatible = "fsl,fman-v2-port-tx";
		reg = <0xac000 0x1000>;
	};

	fman1_tx_0x30: port@b0000 {
		cell-index = <0x30>;
		compatible = "fsl,fman-v2-port-tx";
		reg = <0xb0000 0x1000>;
	};

	ethernet@e0000 {
		compatible = "fsl,fman-dtsec";
		cell-index = <0>;
		reg = <0xe0000 0x1000>;
		fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
		tbi-handle = <&tbi5>;
	};

	ethernet@e2000 {
		compatible = "fsl,fman-dtsec";
		cell-index = <1>;
		reg = <0xe2000 0x1000>;
		fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
		tbi-handle = <&tbi6>;
	};

	ethernet@e4000 {
		compatible = "fsl,fman-dtsec";
		cell-index = <2>;
		reg = <0xe4000 0x1000>;
		fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
		tbi-handle = <&tbi7>;
	};

	ethernet@e6000 {
		compatible = "fsl,fman-dtsec";
		cell-index = <3>;
		reg = <0xe6000 0x1000>;
		fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
		tbi-handle = <&tbi8>;
	};

	ethernet@e8000 {
		compatible = "fsl,fman-dtsec";
		cell-index = <4>;
		reg = <0xf0000 0x1000>;
		fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
		tbi-handle = <&tbi9>;

	ethernet@f0000 {
		cell-index = <8>;
		compatible = "fsl,fman-xgec";
		reg = <0xf0000 0x1000>;
		fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
	};

	ptp-timer@fe000 {
		compatible = "fsl,fman-ptp-timer";
		reg = <0xfe000 0x1000>;
	};

	mdio@f1000 {
		compatible = "fsl,fman-xmdio";
		reg = <0xf1000 0x1000>;
		interrupts = <101 2 0 0>;
	};
};


code:
* MDIO IO device

The MDIO is a bus to which the PHY devices are connected.  For each
device that exists on this bus, a child node should be created.  See
the definition of the PHY node in booting-without-of.txt for an example
of how to define a PHY.

Required properties:
  - reg : Offset and length of the register set for the device, and optionally
          the offset and length of the TBIPA register (TBI PHY address
	  register).  If TBIPA register is not specified, the driver will
	  attempt to infer it from the register set specified (your mileage may
	  vary).
  - compatible : Should define the compatible device type for the
    mdio. Currently supported strings/devices are:
	- "fsl,gianfar-tbi"
	- "fsl,gianfar-mdio"
	- "fsl,etsec2-tbi"
	- "fsl,etsec2-mdio"
	- "fsl,ucc-mdio"
	- "fsl,fman-mdio"
    When device_type is "mdio", the following strings are also considered:
	- "gianfar"
	- "ucc_geth_phy"

Example:

	mdio@24520 {
		reg = <24520 20>;
		compatible = "fsl,gianfar-mdio";

		ethernet-phy@0 {
			......
		};
	};

* TBI Internal MDIO bus

As of this writing, every tsec is associated with an internal TBI PHY.
This PHY is accessed through the local MDIO bus.  These buses are defined
similarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi".
The TBI PHYs underneath them are similar to normal PHYs, but the reg property
is considered instructive, rather than descriptive.  The reg property should
be chosen so it doesn't interfere with other PHYs on the bus.

* Gianfar-compatible ethernet nodes

Properties:

  - device_type : Should be "network"
  - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
  - compatible : Should be "gianfar"
  - reg : Offset and length of the register set for the device
  - interrupts : For FEC devices, the first interrupt is the device's
    interrupt.  For TSEC and eTSEC devices, the first interrupt is
    transmit, the second is receive, and the third is error.
  - phy-handle : See ethernet.txt file in the same directory.
  - fixed-link : See fixed-link.txt in the same directory.
  - phy-connection-type : See ethernet.txt file in the same directory.
    This property is only really needed if the connection is of type
    "rgmii-id", as all other connection types are detected by hardware.
  - fsl,magic-packet : If present, indicates that the hardware supports
    waking up via magic packet.
  - fsl,wake-on-filer : If present, indicates that the hardware supports
    waking up by Filer General Purpose Interrupt (FGPI) asserted on the
    Rx int line.  This is an advanced power management capability allowing
    certain packet types (user) defined by filer rules to wake up the system.
  - bd-stash : If present, indicates that the hardware supports stashing
    buffer descriptors in the L2.
  - rx-stash-len : Denotes the number of bytes of a received buffer to stash
    in the L2.
  - rx-stash-idx : Denotes the index of the first byte from the received
    buffer to stash in the L2.

Example:
	ethernet@24000 {
		device_type = "network";
		model = "TSEC";
		compatible = "gianfar";
		reg = <0x24000 0x1000>;
		local-mac-address = [ 00 E0 0C 00 73 00 ];
		interrupts = <29 2 30 2 34 2>;
		interrupt-parent = <&mpic>;
		phy-handle = <&phy0>
	};

* Gianfar PTP clock nodes

Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt


code:
* Faraday Technology FTGMAC100 gigabit ethernet controller

Required properties:
- compatible: "faraday,ftgmac100"

  Must also contain one of these if used as part of an Aspeed AST2400
  or 2500 family SoC as they have some subtle tweaks to the
  implementation:

     - "aspeed,ast2400-mac"
     - "aspeed,ast2500-mac"
     - "aspeed,ast2600-mac"

- reg: Address and length of the register set for the device
- interrupts: Should contain ethernet controller interrupt

Optional properties:
- phy-handle: See ethernet.txt file in the same directory.
- phy-mode: See ethernet.txt file in the same directory. If the property is
  absent, "rgmii" is assumed. Supported values are "rgmii*" and "rmii" for
  aspeed parts. Other (unknown) parts will accept any value.
- use-ncsi: Use the NC-SI stack instead of an MDIO PHY. Currently assumes
  rmii (100bT) but kept as a separate property in case NC-SI grows support
  for a gigabit link.
- no-hw-checksum: Used to disable HW checksum support. Here for backward
  compatibility as the driver now should have correct defaults based on
  the SoC.
- clocks: In accordance with the generic clock bindings. Must describe the MAC
  IP clock, and optionally an RMII RCLK gate for the AST2500/AST2600. The
  required MAC clock must be the first cell.
- clock-names:

      - "MACCLK": The MAC IP clock
      - "RCLK": Clock gate for the RMII RCLK

Optional subnodes:
- mdio: See mdio.txt file in the same directory.

Example:

	mac0: ethernet@1e660000 {
		compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
		reg = <0x1e660000 0x180>;
		interrupts = <2>;
		use-ncsi;
	};

Example with phy-handle:

	mac1: ethernet@1e680000 {
		compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
		reg = <0x1e680000 0x180>;
		interrupts = <2>;

		phy-handle = <&phy>;
		phy-mode = "rgmii";

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			phy: ethernet-phy@1 {
				compatible = "ethernet-phy-ieee802.3-c22";
				reg = <1>;
			};
		};
	};


code:
Hisilicon Fast Ethernet MDIO Controller interface

Required properties:
- compatible: should be "hisilicon,hisi-femac-mdio".
- reg: address and length of the register set for the device.
- clocks: A phandle to the reference clock for this device.

- PHY subnode: inherits from phy binding [1]
[1] Documentation/devicetree/bindings/net/phy.txt

Example:
mdio: mdio@10091100 {
	compatible = "hisilicon,hisi-femac-mdio";
	reg = <0x10091100 0x10>;
	clocks = <&crg HI3516CV300_MDIO_CLK>;
	#address-cells = <1>;
	#size-cells = <0>;

	phy0: phy@1 {
		reg = <1>;
	};
};


code:
Hisilicon Fast Ethernet MAC controller

Required properties:
- compatible: should contain one of the following version strings:
	* "hisilicon,hisi-femac-v1"
	* "hisilicon,hisi-femac-v2"
	and the soc string "hisilicon,hi3516cv300-femac".
- reg: specifies base physical address(s) and size of the device registers.
  The first region is the MAC core register base and size.
  The second region is the global MAC control register.
- interrupts: should contain the MAC interrupt.
- clocks: A phandle to the MAC main clock.
- resets: should contain the phandle to the MAC reset signal(required) and
	the PHY reset signal(optional).
- reset-names: should contain the reset signal name "mac"(required)
	and "phy"(optional).
- phy-mode: see ethernet.txt [1].
- phy-handle: see ethernet.txt [1].
- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
	The 1st cell is reset pre-delay in micro seconds.
	The 2nd cell is reset pulse in micro seconds.
	The 3rd cell is reset post-delay in micro seconds.

The MAC address will be determined using the optional properties
defined in ethernet.txt[1].

[1] Documentation/devicetree/bindings/net/ethernet.txt

Example:
	hisi_femac: ethernet@10090000 {
		compatible = "hisilicon,hi3516cv300-femac","hisilicon,hisi-femac-v2";
		reg = <0x10090000 0x1000>,<0x10091300 0x200>;
		interrupts = <12>;
		clocks = <&crg HI3518EV200_ETH_CLK>;
		resets = <&crg 0xec 0>,<&crg 0xec 3>;
		reset-names = "mac","phy";
		mac-address = [00 00 00 00 00 00];
		phy-mode = "mii";
		phy-handle = <&phy0>;
		hisilicon,phy-reset-delays-us = <10000 20000 20000>;
	};


code:
Hisilicon hip04 Ethernet Controller

* Ethernet controller node

Required properties:
- compatible: should be "hisilicon,hip04-mac".
- reg: address and length of the register set for the device.
- interrupts: interrupt for the device.
- port-handle: <phandle port channel>
	phandle, specifies a reference to the syscon ppe node
	port, port number connected to the controller
	channel, recv channel start from channel * number (RX_DESC_NUM)
	group, field in the pkg desc, in general, it is the same as the port.
- phy-mode: see ethernet.txt [1].

Optional properties:
- phy-handle: see ethernet.txt [1].

[1] Documentation/devicetree/bindings/net/ethernet.txt

* Ethernet ppe node:
Control rx & tx fifos of all ethernet controllers.
Have 2048 recv channels shared by all ethernet controllers, only if no overlap.
Each controller's recv channel start from channel * number (RX_DESC_NUM).

Required properties:
- compatible: "hisilicon,hip04-ppe", "syscon".
- reg: address and length of the register set for the device.

* MDIO bus node:

Required properties:

- compatible: should be "hisilicon,mdio".
- Inherits from MDIO bus node binding [2]
[2] Documentation/devicetree/bindings/net/phy.txt

Example:
	mdio {
		compatible = "hisilicon,mdio";
		reg = <0x28f1000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;

		phy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			marvell,reg-init = <18 0x14 0 0x8001>;
		};

		phy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			marvell,reg-init = <18 0x14 0 0x8001>;
		};
	};

	ppe: ppe@28c0000 {
		compatible = "hisilicon,hip04-ppe", "syscon";
		reg = <0x28c0000 0x10000>;
	};

	fe: ethernet@28b0000 {
		compatible = "hisilicon,hip04-mac";
		reg = <0x28b0000 0x10000>;
		interrupts = <0 413 4>;
		phy-mode = "mii";
		port-handle = <&ppe 31 0 31>;
	};

	ge0: ethernet@2800000 {
		compatible = "hisilicon,hip04-mac";
		reg = <0x2800000 0x10000>;
		interrupts = <0 402 4>;
		phy-mode = "sgmii";
		port-handle = <&ppe 0 1 0>;
		phy-handle = <&phy0>;
	};

	ge8: ethernet@2880000 {
		compatible = "hisilicon,hip04-mac";
		reg = <0x2880000 0x10000>;
		interrupts = <0 410 4>;
		phy-mode = "sgmii";
		port-handle = <&ppe 8 2 8>;
		phy-handle = <&phy1>;
	};


code:
Hisilicon hix5hd2 gmac controller

Required properties:
- compatible: should contain one of the following SoC strings:
	* "hisilicon,hix5hd2-gmac"
	* "hisilicon,hi3798cv200-gmac"
	* "hisilicon,hi3516a-gmac"
	and one of the following version string:
	* "hisilicon,hisi-gmac-v1"
	* "hisilicon,hisi-gmac-v2"
  The version v1 includes SoCs hix5hd2.
  The version v2 includes SoCs hi3798cv200, hi3516a.
- reg: specifies base physical address(s) and size of the device registers.
  The first region is the MAC register base and size.
  The second region is external interface control register.
- interrupts: should contain the MAC interrupt.
- #address-cells: must be <1>.
- #size-cells: must be <0>.
- phy-mode: see ethernet.txt [1].
- phy-handle: see ethernet.txt [1].
- clocks: clock phandle and specifier pair.
- clock-names: contain the clock name "mac_core"(required) and "mac_ifc"(optional).
- resets: should contain the phandle to the MAC core reset signal(optional),
	the MAC interface reset signal(optional)
	and the PHY reset signal(optional).
- reset-names: contain the reset signal name "mac_core"(optional),
	"mac_ifc"(optional) and "phy"(optional).
- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
	The 1st cell is reset pre-delay in micro seconds.
	The 2nd cell is reset pulse in micro seconds.
	The 3rd cell is reset post-delay in micro seconds.

The MAC address will be determined using the properties defined in
ethernet.txt[1].

- PHY subnode: inherits from phy binding [2]

[1] Documentation/devicetree/bindings/net/ethernet.txt
[2] Documentation/devicetree/bindings/net/phy.txt

Example:
	gmac0: ethernet@f9840000 {
		compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
		reg = <0xf9840000 0x1000>,<0xf984300c 0x4>;
		interrupts = <0 71 4>;
		#address-cells = <1>;
		#size-cells = <0>;
		phy-mode = "rgmii";
		phy-handle = <&phy2>;
		mac-address = [00 00 00 00 00 00];
		clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>;
		clock-names = "mac_core", "mac_ifc";
		resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&crg 0xcc 12>;
		reset-names = "mac_core", "mac_ifc", "phy";
		hisilicon,phy-reset-delays-us = <10000 10000 30000>;

		phy2: ethernet-phy@2 {
			reg = <2>;
		};
	};


code:
Hisilicon DSA Fabric device controller

Required properties:
- compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
  "hisilicon,hns-dsaf-v1" is for hip05.
  "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
- mode: dsa fabric mode string. only support one of dsaf modes like these:
		"2port-64vf",
		"6port-16rss",
		"6port-16vf",
		"single-port".
- interrupts: should contain the DSA Fabric and rcb interrupt.
- reg: specifies base physical address(es) and size of the device registers.
  The first region is external interface control register base and size(optional,
  only used when subctrl-syscon does not exist). It is recommended using
  subctrl-syscon rather than this address.
  The second region is SerDes base register and size(optional, only used when
  serdes-syscon in port node does not exist). It is recommended using
  serdes-syscon rather than this address.
  The third region is the PPE register base and size.
  The fourth region is dsa fabric base register and size. It is not required for
  single-port mode.
- reg-names: may be ppe-base and(or) dsaf-base. It is used to find the
  corresponding reg's index.

- phy-handle: phy handle of physical port, 0 if not any phy device. It is optional
  attribute. If port node exists, phy-handle in each port node will be used.
  see ethernet.txt [1].
- subctrl-syscon: is syscon handle for external interface control register.
- reset-field-offset: is offset of reset field. Its value depends on the hardware
  user manual.
- buf-size: rx buffer size, should be 16-1024.
- desc-num: number of description in TX and RX queue, should be 512, 1024, 2048 or 4096.

- port: subnodes of dsaf. A dsaf node may contain several port nodes(Depending
  on mode of dsaf). Port node contain some attributes listed below:
- reg: is physical port index in one dsaf.
- phy-handle: phy handle of physical port. It is not required if there isn't
  phy device. see ethernet.txt [1].
- serdes-syscon: is syscon handle for SerDes register.
- cpld-syscon: is syscon handle + register offset pair for cpld register. It is
  not required if there isn't cpld device.
- port-rst-offset: is offset of reset field for each port in dsaf. Its value
  depends on the hardware user manual.
- port-mode-offset: is offset of port mode field for each port in dsaf. Its
  value depends on the hardware user manual.
- mc-mac-mask: mask of multicast address, determines bit in multicast address
  to set:
  1 stands for this bit will be precisely matched, TCAM will check this bit of
    MAC address.
  0 stands for this bit will be fuzzy matched, TCAM won't care about this bit
    of MAC address.

[1] Documentation/devicetree/bindings/net/phy.txt

Example:

dsaf0: dsa@c7000000 {
	compatible = "hisilicon,hns-dsaf-v1";
	mode = "6port-16rss";
	interrupt-parent = <&mbigen_dsa>;
	reg = <0x0 0xc5000000 0x0 0x890000
	       0x0 0xc7000000 0x0 0x60000>;
	reg-names = "ppe-base", "dsaf-base";
	subctrl-syscon = <&subctrl>;
	reset-field-offset = 0;
	interrupts = <131 4>,<132 4>, <133 4>,<134 4>,
		     <135 4>,<136 4>, <137 4>,<138 4>,
		     <139 4>,<140 4>, <141 4>,<142 4>,
		     <143 4>,<144 4>, <145 4>,<146 4>,
		     <147 4>,<148 4>, <384 1>,<385 1>,
		     <386 1>,<387 1>, <388 1>,<389 1>,
		     <390 1>,<391 1>,
	buf-size = <4096>;
	desc-num = <1024>;
	dma-coherent;

	port@0 {
		reg = 0;
		phy-handle = <&phy0>;
		serdes-syscon = <&serdes>;
		mc-mac-mask = [ff f0 00 00 00 00];
	};

	port@1 {
                reg = 1;
                serdes-syscon = <&serdes>;
		mc-mac-mask = [ff f0 00 00 00 00];
        };
};


code:
Hisilicon MDIO bus controller

Properties:
- compatible: can be one of:
	"hisilicon,hns-mdio"
	"hisilicon,mdio"
  "hisilicon,hns-mdio" is recommended to be used for hip05 and later SOCs,
  while "hisilicon,mdio" is optional for backwards compatibility only on
  hip04 Soc.
- reg: The base address of the MDIO bus controller register bank.
- #address-cells: Must be <1>.
- #size-cells: Must be <0>.  MDIO addresses have no size component.

Typically an MDIO bus might have several children.

Example:
         mdio@803c0000 {
                   #address-cells = <1>;
                   #size-cells = <0>;
                   compatible = "hisilicon,hns-mdio","hisilicon,mdio";
                   reg = <0x0 0x803c0000 0x0 0x10000>;

                   ethernet-phy@0 {
                            ...
                            reg = <0>;
                   };
         };


code:
Hisilicon Network Subsystem NIC controller

Required properties:
- compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
  "hisilicon,hns-nic-v1" is for hip05.
  "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
- ae-handle: accelerator engine handle for hns,
  specifies a reference to the associating hardware driver node.
  see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
- port-id: is the index of port provided by DSAF (the accelerator). DSAF can
  connect to 8 PHYs. Port 0 to 1 are both used for administration purpose. They
  are called debug ports.

  The remaining 6 PHYs are taken according to the mode of DSAF.

  In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The
  port-id can be 2 to 7. Here is the diagram:
            +-----+---------------+
            |            CPU      |
            +-+-+-+---+-+-+-+-+-+-+
              | |     | | | | | |
             debug       service
             port         port
             (0,1)       (2-7)

  In Switch mode of DSAF, all 6 PHYs are taken as physical ports connect to a
  LAN Switch while the CPU side assume itself have one single NIC connect to
  this switch. In this case, the port-id will be 2 only.
            +-----+---------------+
            |            CPU      |
            +-+-+-+---+-+-+-+-+-+-+
              | |   service| port(2)
             debug   +------------+
             port    |   switch   |
             (0,1)   +-+-+-+-+-+-++
                       | | | | | |
                      external port

  This attribute is remained for compatible purpose. It is not recommended to
  use it in new code.

- port-idx-in-ae: is the index of port provided by AE.
  In NIC mode of DSAF, all 6 PHYs of service DSAF are taken as ethernet ports
  to the CPU. The port-idx-in-ae can be 0 to 5. Here is the diagram:
            +-----+---------------+
            |            CPU      |
            +-+-+-+---+-+-+-+-+-+-+
              |    |   | | | | | |
           debug debug   service
           port  port     port
           (0)   (0)     (0-5)

  In Switch mode of DSAF, all 6 PHYs of service DSAF are taken as physical
  ports connected to a LAN Switch while the CPU side assume itself have one
  single NIC connected to this switch. In this case, the port-idx-in-ae
  will be 0 only.
            +-----+-----+------+------+
            |                CPU      |
            +-+-+-+-+-+-+-+-+-+-+-+-+-+
              |    |     service| port(0)
            debug debug  +------------+
            port  port   |   switch   |
            (0)   (0)    +-+-+-+-+-+-++
                          | | | | | |
                         external port

- local-mac-address: mac addr of the ethernet interface

Example:

	ethernet@0{
		compatible = "hisilicon,hns-nic-v1";
		ae-handle = <&dsaf0>;
		port-idx-in-ae = <0>;
		local-mac-address = [a2 14 e4 4b 56 76];
	};


code:
    4xx/Axon EMAC ethernet nodes

    The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
    the Axon bridge.  To operate this needs to interact with a this
    special McMAL DMA controller, and sometimes an RGMII or ZMII
    interface.  In addition to the nodes and properties described
    below, the node for the OPB bus on which the EMAC sits must have a
    correct clock-frequency property.

      i) The EMAC node itself

    Required properties:
    - device_type       : "network"

    - compatible        : compatible list, contains 2 entries, first is
			  "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
			  405gp, Axon) and second is either "ibm,emac" or
			  "ibm,emac4".  For Axon, thus, we have: "ibm,emac-axon",
			  "ibm,emac4"
    - interrupts        : <interrupt mapping for EMAC IRQ and WOL IRQ>
    - reg               : <registers mapping>
    - local-mac-address : 6 bytes, MAC address
    - mal-device        : phandle of the associated McMAL node
    - mal-tx-channel    : 1 cell, index of the tx channel on McMAL associated
			  with this EMAC
    - mal-rx-channel    : 1 cell, index of the rx channel on McMAL associated
			  with this EMAC
    - cell-index        : 1 cell, hardware index of the EMAC cell on a given
			  ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
			  each Axon chip)
    - max-frame-size    : 1 cell, maximum frame size supported in bytes
    - rx-fifo-size      : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
			  operations.
			  For Axon, 2048
    - tx-fifo-size      : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
			  operations.
			  For Axon, 2048.
    - fifo-entry-size   : 1 cell, size of a fifo entry (used to calculate
			  thresholds).
			  For Axon, 0x00000010
    - mal-burst-size    : 1 cell, MAL burst size (used to calculate thresholds)
			  in bytes.
			  For Axon, 0x00000100 (I think ...)
    - phy-mode          : string, mode of operations of the PHY interface.
			  Supported values are: "mii", "rmii", "smii", "rgmii",
			  "tbi", "gmii", rtbi", "sgmii".
			  For Axon on CAB, it is "rgmii"
    - mdio-device       : 1 cell, required iff using shared MDIO registers
			  (440EP).  phandle of the EMAC to use to drive the
			  MDIO lines for the PHY used by this EMAC.
    - zmii-device       : 1 cell, required iff connected to a ZMII.  phandle of
			  the ZMII device node
    - zmii-channel      : 1 cell, required iff connected to a ZMII.  Which ZMII
			  channel or 0xffffffff if ZMII is only used for MDIO.
    - rgmii-device      : 1 cell, required iff connected to an RGMII. phandle
			  of the RGMII device node.
			  For Axon: phandle of plb5/plb4/opb/rgmii
    - rgmii-channel     : 1 cell, required iff connected to an RGMII.  Which
			  RGMII channel is used by this EMAC.
			  Fox Axon: present, whatever value is appropriate for each
			  EMAC, that is the content of the current (bogus) "phy-port"
			  property.

    Optional properties:
    - phy-address       : 1 cell, optional, MDIO address of the PHY. If absent,
			  a search is performed.
    - phy-map           : 1 cell, optional, bitmap of addresses to probe the PHY
			  for, used if phy-address is absent. bit 0x00000001 is
			  MDIO address 0.
			  For Axon it can be absent, though my current driver
			  doesn't handle phy-address yet so for now, keep
			  0x00ffffff in it.
    - phy-handle	: Used to describe configurations where a external PHY
			  is used. Please refer to:
			  Documentation/devicetree/bindings/net/ethernet.txt
    - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
			  operations (if absent the value is the same as
			  rx-fifo-size).  For Axon, either absent or 2048.
    - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
			  operations (if absent the value is the same as
			  tx-fifo-size). For Axon, either absent or 2048.
    - tah-device        : 1 cell, optional. If connected to a TAH engine for
			  offload, phandle of the TAH device node.
    - tah-channel       : 1 cell, optional. If appropriate, channel used on the
			  TAH engine.
    - fixed-link	: Fixed-link subnode describing a link to a non-MDIO
			  managed entity. See
			  Documentation/devicetree/bindings/net/fixed-link.txt
			  for details.
    - mdio subnode	: When the EMAC has a phy connected to its local
			  mdio, which us supported by the kernel's network
			  PHY library in drivers/net/phy, there must be device
			  tree subnode with the following required properties:
				- #address-cells: Must be <1>.
				- #size-cells: Must be <0>.

			  For PHY definitions: Please refer to
			  Documentation/devicetree/bindings/net/phy.txt and
			  Documentation/devicetree/bindings/net/ethernet.txt

    Examples:

	EMAC0: ethernet@40000800 {
		device_type = "network";
		compatible = "ibm,emac-440gp", "ibm,emac";
		interrupt-parent = <&UIC1>;
		interrupts = <1c 4 1d 4>;
		reg = <40000800 70>;
		local-mac-address = [00 04 AC E3 1B 1E];
		mal-device = <&MAL0>;
		mal-tx-channel = <0 1>;
		mal-rx-channel = <0>;
		cell-index = <0>;
		max-frame-size = <5dc>;
		rx-fifo-size = <1000>;
		tx-fifo-size = <800>;
		phy-mode = "rmii";
		phy-map = <00000001>;
		zmii-device = <&ZMII0>;
		zmii-channel = <0>;
	};

	EMAC1: ethernet@ef600c00 {
		device_type = "network";
		compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
		interrupt-parent = <&EMAC1>;
		interrupts = <0 1>;
		#interrupt-cells = <1>;
		#address-cells = <0>;
		#size-cells = <0>;
		interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH /* Status */
				 1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH /* Wake */>;
		reg = <0xef600c00 0x000000c4>;
		local-mac-address = [000000000000]; /* Filled in by U-Boot */
		mal-device = <&MAL0>;
		mal-tx-channel = <0>;
		mal-rx-channel = <0>;
		cell-index = <0>;
		max-frame-size = <9000>;
		rx-fifo-size = <16384>;
		tx-fifo-size = <2048>;
		fifo-entry-size = <10>;
		phy-mode = "rgmii";
		phy-handle = <&phy0>;
		phy-map = <0x00000000>;
		rgmii-device = <&RGMII0>;
		rgmii-channel = <0>;
		tah-device = <&TAH0>;
		tah-channel = <0>;
		has-inverted-stacr-oc;
		has-new-stacr-staopc;

	        mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			phy0: ethernet-phy@0 {
				compatible = "ethernet-phy-ieee802.3-c22";
				reg = <0>;
			};
		};
	};

      ii) McMAL node

    Required properties:
    - device_type        : "dma-controller"
    - compatible         : compatible list, containing 2 entries, first is
			   "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
			   emac) and the second is either "ibm,mcmal" or
			   "ibm,mcmal2".
			   For Axon, "ibm,mcmal-axon","ibm,mcmal2"
    - interrupts         : <interrupt mapping for the MAL interrupts sources:
                           5 sources: tx_eob, rx_eob, serr, txde, rxde>.
                           For Axon: This is _different_ from the current
			   firmware.  We use the "delayed" interrupts for txeob
			   and rxeob. Thus we end up with mapping those 5 MPIC
			   interrupts, all level positive sensitive: 10, 11, 32,
			   33, 34 (in decimal)
    - dcr-reg            : < DCR registers range >
    - dcr-parent         : if needed for dcr-reg
    - num-tx-chans       : 1 cell, number of Tx channels
    - num-rx-chans       : 1 cell, number of Rx channels

      iii) ZMII node

    Required properties:
    - compatible         : compatible list, containing 2 entries, first is
			   "ibm,zmii-CHIP" where CHIP is the host ASIC (like
			   EMAC) and the second is "ibm,zmii".
			   For Axon, there is no ZMII node.
    - reg                : <registers mapping>

      iv) RGMII node

    Required properties:
    - compatible         : compatible list, containing 2 entries, first is
			   "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
			   EMAC) and the second is "ibm,rgmii".
                           For Axon, "ibm,rgmii-axon","ibm,rgmii"
    - reg                : <registers mapping>
    - revision           : as provided by the RGMII new version register if
			   available.
			   For Axon: 0x0000012a


code:
IC Plus Corp. IP101A / IP101G Ethernet PHYs

There are different models of the IP101G Ethernet PHY:
- IP101GR (32-pin QFN package)
- IP101G (die only, no package)
- IP101GA (48-pin LQFP package)

There are different models of the IP101A Ethernet PHY (which is the
predecessor of the IP101G):
- IP101A (48-pin LQFP package)
- IP101AH (48-pin LQFP package)

Optional properties for the IP101GR (32-pin QFN package):

- icplus,select-rx-error:
  pin 21 ("RXER/INTR_32") will output the receive error status.
  interrupts are not routed outside the PHY in this mode.
- icplus,select-interrupt:
  pin 21 ("RXER/INTR_32") will output the interrupt signal.


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/idt,3243x-emac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: IDT 79rc3243x Ethernet controller

description: Ethernet controller integrated into IDT 79RC3243x family SoCs

maintainers:
  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    const: idt,3243x-emac

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: emac
      - const: dma_rx
      - const: dma_tx

  interrupts:
    items:
      - description: RX interrupt
      - description: TX interrupt

  interrupt-names:
    items:
      - const: rx
      - const: tx

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: mdioclk

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |

    ethernet@60000 {
        compatible = "idt,3243x-emac";

        reg = <0x60000 0x10000>,
              <0x40000 0x14>,
              <0x40014 0x14>;
        reg-names = "emac", "dma_rx", "dma_tx";

        interrupt-parent = <&rcpic3>;
        interrupts = <0>, <1>;
        interrupt-names = "rx", "tx";

        clocks = <&iclk>;
        clock-names = "mdioclk";
    };


code:
* ADF7242 IEEE 802.15.4 *

Required properties:
  - compatible:		should be "adi,adf7242", "adi,adf7241"
  - spi-max-frequency:	maximal bus speed (12.5 MHz)
  - reg:		the chipselect index
  - interrupts:		the interrupt generated by the device via pin IRQ1.
			IRQ_TYPE_LEVEL_HIGH (4) or IRQ_TYPE_EDGE_FALLING (1)

Example:

	adf7242@0 {
		compatible = "adi,adf7242";
		spi-max-frequency = <10000000>;
		reg = <0>;
		interrupts = <98 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gpio3>;
	};


code:
* AT86RF230 IEEE 802.15.4 *

Required properties:
  - compatible:		should be "atmel,at86rf230", "atmel,at86rf231",
			"atmel,at86rf233" or "atmel,at86rf212"
  - spi-max-frequency:	maximal bus speed, should be set to 7500000 depends
			sync or async operation mode
  - reg:		the chipselect index
  - interrupts:		the interrupt generated by the device. Non high-level
			can occur deadlocks while handling isr.

Optional properties:
  - reset-gpio:		GPIO spec for the rstn pin
  - sleep-gpio:		GPIO spec for the slp_tr pin
  - xtal-trim:		u8 value for fine tuning the internal capacitance
			arrays of xtal pins: 0 = +0 pF, 0xf = +4.5 pF

Example:

	at86rf231@0 {
		compatible = "atmel,at86rf231";
		spi-max-frequency = <7500000>;
		reg = <0>;
		interrupts = <19 4>;
		interrupt-parent = <&gpio3>;
		xtal-trim = /bits/ 8 <0x06>;
	};


code:
* CA8210 IEEE 802.15.4 *

Required properties:
	- compatible:           Should be "cascoda,ca8210"
	- reg:                  Controlling chip select
	- spi-max-frequency:    Maximum clock speed, should be *less than*
	                        4000000
	- spi-cpol:             Requires inverted clock polarity
	- reset-gpio:           GPIO attached to reset
	- irq-gpio:             GPIO attached to IRQ
Optional properties:
	- extclock-enable:      Include for the ca8210 to route its 16MHz clock
	                        to an output
	- extclock-freq:        Frequency in Hz of the external clock
	- extclock-gpio:        GPIO of the ca8210 to output the clock on

Example:
	ca8210@0 {
		compatible = "cascoda,ca8210";
		reg = <0>;
		spi-max-frequency = <3000000>;
		spi-cpol;
		reset-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
		irq-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
		extclock-enable;
		extclock-freq = 16000000;
		extclock-gpio = 2;
	};


code:
*CC2520 IEEE 802.15.4 Compatible Radio*

Required properties:
	- compatible: 		should be "ti,cc2520"
	- spi-max-frequency:	maximal bus speed (8000000), should be set to 4000000 depends
				sync or async operation mode
	- reg:			the chipselect index
	- pinctrl-0: 		pin control group to be used for this controller.
	- pinctrl-names: 	must contain a "default" entry.
	- fifo-gpio:		GPIO spec for the FIFO pin
	- fifop-gpio:		GPIO spec for the FIFOP pin
	- sfd-gpio:		GPIO spec for the SFD pin
	- cca-gpio:		GPIO spec for the CCA pin
	- vreg-gpio:		GPIO spec for the VREG pin
	- reset-gpio:		GPIO spec for the RESET pin
Optional properties:
	- amplified:		include if the CC2520 is connected to a CC2591 amplifier

Example:
	cc2520@0 {
		compatible = "ti,cc2520";
		reg = <0>;
		spi-max-frequency = <4000000>;
		amplified;
		pinctrl-names = "default";
		pinctrl-0 = <&cc2520_cape_pins>;
		fifo-gpio = <&gpio1 18 0>;
		fifop-gpio = <&gpio1 19 0>;
		sfd-gpio = <&gpio1 13 0>;
		cca-gpio = <&gpio1 16 0>;
		vreg-gpio = <&gpio0 31 0>;
		reset-gpio = <&gpio1 12 0>;
	};


code:
* MCR20A IEEE 802.15.4 *

Required properties:
  - compatible:		should be "nxp,mcr20a"
  - spi-max-frequency:	maximal bus speed, should be set to a frequency
			lower than 9000000 depends sync or async operation mode
  - reg:		the chipselect index
  - interrupts:		the interrupt generated by the device. Non high-level
			can occur deadlocks while handling isr.

Optional properties:
  - rst_b-gpio:		GPIO spec for the RST_B pin

Example:

	mcr20a@0 {
		compatible = "nxp,mcr20a";
		spi-max-frequency = <9000000>;
		reg = <0>;
		interrupts = <17 2>;
		interrupt-parent = <&gpio>;
		rst_b-gpio = <&gpio 27 1>
	};


code:
* MRF24J40 IEEE 802.15.4 *

Required properties:
  - compatible:		should be "microchip,mrf24j40", "microchip,mrf24j40ma",
			or "microchip,mrf24j40mc" depends on your transceiver
			board
  - spi-max-frequency:	maximal bus speed, should be set something under or equal
			10000000
  - reg:		the chipselect index
  - interrupts:		the interrupt generated by the device.

Example:

	mrf24j40ma@0 {
		compatible = "microchip,mrf24j40ma";
		spi-max-frequency = <8500000>;
		reg = <0>;
		interrupts = <19 8>;
		interrupt-parent = <&gpio3>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ingenic,mac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Bindings for MAC in Ingenic SoCs

maintainers:
  - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

description:
  The Ethernet Media Access Controller in Ingenic SoCs.

properties:
  compatible:
    enum:
      - ingenic,jz4775-mac
      - ingenic,x1000-mac
      - ingenic,x1600-mac
      - ingenic,x1830-mac
      - ingenic,x2000-mac

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-names:
    const: macirq

  clocks:
    maxItems: 1

  clock-names:
    const: stmmaceth

  mode-reg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: An extra syscon register that control ethernet interface and timing delay

  rx-clk-delay-ps:
    description: RGMII receive clock delay defined in pico seconds

  tx-clk-delay-ps:
    description: RGMII transmit clock delay defined in pico seconds

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - mode-reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,x1000-cgu.h>

    mac: ethernet@134b0000 {
        compatible = "ingenic,x1000-mac";
        reg = <0x134b0000 0x2000>;

        interrupt-parent = <&intc>;
        interrupts = <55>;
        interrupt-names = "macirq";

        clocks = <&cgu X1000_CLK_MAC>;
        clock-names = "stmmaceth";

        mode-reg = <&mac_phy_ctrl>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel DWMAC glue layer

maintainers:
  - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>

select:
  properties:
    compatible:
      contains:
        enum:
          - intel,keembay-dwmac
  required:
    - compatible

allOf:
  - $ref: "snps,dwmac.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - intel,keembay-dwmac
          - const: snps,dwmac-4.10a

  clocks:
    items:
      - description: GMAC main clock
      - description: PTP reference clock
      - description: Tx clock

  clock-names:
    items:
      - const: stmmaceth
      - const: ptp_ref
      - const: tx_clk

required:
  - compatible
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
# FIXME: Remove defines and include the correct header file
# once it is available in mainline.
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #define MOVISOC_KMB_PSS_GBE
    #define MOVISOC_KMB_PSS_AUX_GBE_PTP
    #define MOVISOC_KMB_PSS_AUX_GBE_TX

    stmmac_axi_setup: stmmac-axi-config {
        snps,lpi_en;
        snps,wr_osr_lmt = <0x0>;
        snps,rd_osr_lmt = <0x2>;
        snps,blen = <0 0 0 0 16 8 4>;
    };

    mtl_rx_setup: rx-queues-config {
        snps,rx-queues-to-use = <2>;
        snps,rx-sched-sp;
        queue0 {
            snps,dcb-algorithm;
            snps,map-to-dma-channel = <0x0>;
            snps,priority = <0x0>;
        };

        queue1 {
            snps,dcb-algorithm;
            snps,map-to-dma-channel = <0x1>;
            snps,priority = <0x1>;
        };
    };

    mtl_tx_setup: tx-queues-config {
        snps,tx-queues-to-use = <2>;
        snps,tx-sched-wrr;
        queue0 {
           snps,weight = <0x10>;
           snps,dcb-algorithm;
           snps,priority = <0x0>;
        };

        queue1 {
            snps,weight = <0x10>;
            snps,dcb-algorithm;
            snps,priority = <0x1>;
        };
    };

    gmac0: ethernet@3a000000 {
        compatible = "intel,keembay-dwmac", "snps,dwmac-4.10a";
        interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "macirq";
        reg = <0x3a000000 0x8000>;
        snps,perfect-filter-entries = <128>;
        phy-handle = <&eth_phy0>;
        phy-mode = "rgmii";
        rx-fifo-depth = <4096>;
        tx-fifo-depth = <4096>;
        clock-names = "stmmaceth", "ptp_ref", "tx_clk";
        clocks = <&scmi_clk MOVISOC_KMB_PSS_GBE>,
                 <&scmi_clk MOVISOC_KMB_PSS_AUX_GBE_PTP>,
                 <&scmi_clk MOVISOC_KMB_PSS_AUX_GBE_TX>;
        snps,pbl = <0x4>;
        snps,axi-config = <&stmmac_axi_setup>;
        snps,mtl-rx-config = <&mtl_rx_setup>;
        snps,mtl-tx-config = <&mtl_tx_setup>;
        snps,tso;

        mdio {
            #address-cells = <1>;
            #size-cells = <0>;
            compatible = "snps,dwmac-mdio";

            ethernet-phy@0 {
                reg = <0>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/intel,ixp46x-ptp-timer.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel IXP46x PTP Timer (TSYNC)

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  The Intel IXP46x PTP timer is known in the manual as IEEE1588 Hardware
  Assist and Time Synchronization Hardware Assist TSYNC provides a PTP
  timer. It exists in the Intel IXP45x and IXP46x XScale SoCs.

properties:
  compatible:
    const: intel,ixp46x-ptp-timer

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: Interrupt to trigger master mode snapshot from the
          PRP timer, usually a GPIO interrupt.
      - description: Interrupt to trigger slave mode snapshot from the
          PRP timer, usually a GPIO interrupt.

  interrupt-names:
    items:
      - const: master
      - const: slave

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    ptp-timer@c8010000 {
        compatible = "intel,ixp46x-ptp-timer";
        reg = <0xc8010000 0x1000>;
        interrupt-parent = <&gpio0>;
        interrupts = <8 IRQ_TYPE_EDGE_FALLING>, <7 IRQ_TYPE_EDGE_FALLING>;
        interrupt-names = "master", "slave";
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel IXP4xx ethernet

allOf:
  - $ref: "ethernet-controller.yaml#"

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  The Intel IXP4xx ethernet makes use of the IXP4xx NPE (Network
  Processing Engine) and the IXP4xx Queue Manager to process
  the ethernet frames. It can optionally contain an MDIO bus to
  talk to PHYs.

properties:
  compatible:
    const: intel,ixp4xx-ethernet

  reg:
    maxItems: 1
    description: Ethernet MMIO address range

  queue-rx:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    items:
      - items:
          - description: phandle to the RX queue node
          - description: RX queue instance to use
    description: phandle to the RX queue on the NPE

  queue-txready:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    items:
      - items:
          - description: phandle to the TX READY queue node
          - description: TX READY queue instance to use
    description: phandle to the TX READY queue on the NPE

  phy-mode: true

  phy-handle: true

  intel,npe-handle:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    items:
      - items:
          - description: phandle to the NPE this ethernet instance is using
          - description: the NPE instance to use
    description: phandle to the NPE this ethernet instance is using
      and the instance to use in the second cell

  mdio:
    $ref: mdio.yaml#
    unevaluatedProperties: false
    description: optional node for embedded MDIO controller

required:
  - compatible
  - reg
  - queue-rx
  - queue-txready
  - intel,npe-handle

additionalProperties: false

examples:
  - |
    npe: npe@c8006000 {
      compatible = "intel,ixp4xx-network-processing-engine";
      reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
    };

    ethernet@c8009000 {
      compatible = "intel,ixp4xx-ethernet";
      reg = <0xc8009000 0x1000>;
      queue-rx = <&qmgr 4>;
      queue-txready = <&qmgr 21>;
      intel,npe-handle = <&npe 1>;
      phy-mode = "rgmii";
      phy-handle = <&phy1>;
    };

    ethernet@c800c000 {
      compatible = "intel,ixp4xx-ethernet";
      reg = <0xc800c000 0x1000>;
      queue-rx = <&qmgr 3>;
      queue-txready = <&qmgr 20>;
      intel,npe-handle = <&npe 2>;
      phy-mode = "rgmii";
      phy-handle = <&phy2>;

      mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy1: ethernet-phy@1 {
          reg = <1>;
        };
        phy2: ethernet-phy@2 {
          reg = <2>;
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2021 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel IXP4xx V.35 WAN High Speed Serial Link (HSS)

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  The Intel IXP4xx HSS makes use of the IXP4xx NPE (Network
  Processing Engine) and the IXP4xx Queue Manager to process
  V.35 Wideband Modem (WAN) links.

properties:
  compatible:
    const: intel,ixp4xx-hss

  reg:
    maxItems: 1
    description: The HSS instance

  intel,npe-handle:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    items:
      items:
        - description: phandle to the NPE this HSS instance is using
        - description: the NPE instance number
    description: phandle to the NPE this HSS instance is using
      and the instance to use in the second cell

  intel,queue-chl-rxtrig:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    items:
      - items:
          - description: phandle to the RX trigger queue on the NPE
          - description: the queue instance number
    description: phandle to the RX trigger queue on the NPE

  intel,queue-chl-txready:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    items:
      - items:
          - description: phandle to the TX ready queue on the NPE
          - description: the queue instance number
    description: phandle to the TX ready queue on the NPE

  intel,queue-pkt-rx:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    items:
      - items:
          - description: phandle to the RX queue on the NPE
          - description: the queue instance number
    description: phandle to the packet RX queue on the NPE

  intel,queue-pkt-tx:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    maxItems: 4
    items:
      items:
        - description: phandle to the TX queue on the NPE
        - description: the queue instance number
    description: phandle to the packet TX0, TX1, TX2 and TX3 queues on the NPE

  intel,queue-pkt-rxfree:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    maxItems: 4
    items:
      items:
        - description: phandle to the RXFREE queue on the NPE
        - description: the queue instance number
    description: phandle to the packet RXFREE0, RXFREE1, RXFREE2 and
      RXFREE3 queues on the NPE

  intel,queue-pkt-txdone:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    items:
      - items:
          - description: phandle to the TXDONE queue on the NPE
          - description: the queue instance number
    description: phandle to the packet TXDONE queue on the NPE

  cts-gpios:
    maxItems: 1
    description: Clear To Send (CTS) GPIO line

  rts-gpios:
    maxItems: 1
    description: Ready To Send (RTS) GPIO line

  dcd-gpios:
    maxItems: 1
    description: Data Carrier Detect (DCD) GPIO line

  dtr-gpios:
    maxItems: 1
    description: Data Terminal Ready (DTR) GPIO line

  clk-internal-gpios:
    maxItems: 1
    description: Clock internal GPIO line, driving this high will make the HSS
      use internal clocking as opposed to external clocking

required:
  - compatible
  - reg
  - intel,npe-handle
  - intel,queue-chl-rxtrig
  - intel,queue-chl-txready
  - intel,queue-pkt-rx
  - intel,queue-pkt-tx
  - intel,queue-pkt-rxfree
  - intel,queue-pkt-txdone
  - cts-gpios
  - rts-gpios
  - dcd-gpios
  - dtr-gpios
  - clk-internal-gpios

additionalProperties: false


code:
* IPQ806x DWMAC Ethernet controller

The device inherits all the properties of the dwmac/stmmac devices
described in the file net/stmmac.txt with the following changes.

Required properties:

- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
	      and any applicable more detailed version number
	      described in net/stmmac.txt

- qcom,nss-common: should contain a phandle to a syscon device mapping the
		   nss-common registers.

- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
		   qsgmii-csr registers.

Example:

	gmac: ethernet@37000000 {
		device_type = "network";
		compatible = "qcom,ipq806x-gmac";
		reg = <0x37000000 0x200000>;
		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq";

		qcom,nss-common = <&nss_common>;
		qcom,qsgmii-csr = <&qsgmii_csr>;

		clocks = <&gcc GMAC_CORE1_CLK>;
		clock-names = "stmmaceth";

		resets = <&gcc GMAC_CORE1_RESET>;
		reset-names = "stmmaceth";
	};


code:
This document describes the device tree bindings associated with the
keystone network coprocessor(NetCP) driver support.

The network coprocessor (NetCP) is a hardware accelerator that processes
Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet
switch sub-module to send and receive packets. NetCP also includes a packet
accelerator (PA) module to perform packet classification operations such as
header matching, and packet modification operations such as checksum
generation. NetCP can also optionally include a Security Accelerator (SA)
capable of performing IPSec operations on ingress/egress packets.

Keystone II SoC's also have a 10 Gigabit Ethernet Subsystem (XGbE) which
includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
per Ethernet port.

Keystone NetCP driver has a plug-in module architecture where each of the NetCP
sub-modules exist as a loadable kernel module which plug in to the netcp core.
These sub-modules are represented as "netcp-devices" in the dts bindings. It is
mandatory to have the ethernet switch sub-module for the ethernet interface to
be operational. Any other sub-module like the PA is optional.

NetCP Ethernet SubSystem Layout:

-----------------------------
  NetCP subsystem(10G or 1G)
-----------------------------
	|
	|-> NetCP Devices ->	|
	|			|-> GBE/XGBE Switch
	|			|
	|			|-> Packet Accelerator
	|			|
	|			|-> Security Accelerator
	|
	|
	|
	|-> NetCP Interfaces ->	|
				|-> Ethernet Port 0
				|
				|-> Ethernet Port 1
				|
				|-> Ethernet Port 2
				|
				|-> Ethernet Port 3

NetCP subsystem properties:
Required properties:
- compatible:	Should be "ti,netcp-1.0"
- clocks:	phandle to the reference clocks for the subsystem.
- dma-id:	Navigator packet dma instance id.
- ranges:	address range of NetCP (includes, Ethernet SS, PA and SA)

Optional properties:
- reg:		register location and the size for the following register
		regions in the specified order.
		- Efuse MAC address register
- dma-coherent:	Present if dma operations are coherent
- big-endian:	Keystone devices can be operated in a mode where the DSP is in
		the big endian mode. In such cases enable this option. This
		option should also be enabled if the ARM is operated in
		big endian mode with the DSP in little endian.

NetCP device properties: Device specification for NetCP sub-modules.
1Gb/10Gb (gbe/xgbe) ethernet switch sub-module specifications.
Required properties:
- label:	Must be "netcp-gbe" for 1Gb & "netcp-xgbe" for 10Gb.
- compatible:	Must be one of below:-
		"ti,netcp-gbe" for 1GbE on NetCP 1.4
		"ti,netcp-gbe-5" for 1GbE N NetCP 1.5 (N=5)
		"ti,netcp-gbe-9" for 1GbE N NetCP 1.5 (N=9)
		"ti,netcp-gbe-2" for 1GbE N NetCP 1.5 (N=2)
		"ti,netcp-xgbe" for 10 GbE

- reg:		register location and the size for the following register
		regions in the specified order.
		- switch subsystem registers
		- sgmii port3/4 module registers (only for NetCP 1.4)
		- switch module registers
		- serdes registers (only for 10G)

		NetCP 1.4 ethss, here is the order
			index #0 - switch subsystem registers
			index #1 - sgmii port3/4 module registers
			index #2 - switch module registers

		NetCP 1.5 ethss 9 port, 5 port and 2 port
			index #0 - switch subsystem registers
			index #1 - switch module registers
			index #2 - serdes registers

- tx-channel:	the navigator packet dma channel name for tx.
- tx-queue:	the navigator queue number associated with the tx dma channel.
- interfaces:	specification for each of the switch port to be registered as a
		network interface in the stack.
-- slave-port:	Switch port number, 0 based numbering.
-- link-interface:	type of link interface, supported options are
			- mac<->mac auto negotiate mode: 0
			- mac<->phy mode: 1
			- mac<->mac forced mode: 2
			- mac<->fiber mode: 3
			- mac<->phy mode with no mdio: 4
			- 10Gb mac<->phy mode : 10
			- 10Gb mac<->mac forced mode : 11
----phy-handle:	phandle to PHY device

- cpts:		sub-node time synchronization (CPTS) submodule configuration
-- clocks:	CPTS reference clock. Should point on cpts-refclk-mux clock.
-- clock-names: should be "cpts"
-- cpts-refclk-mux: multiplexer clock definition sub-node for CPTS reference (RFTCLK) clock
--- #clock-cells: should be 0
--- clocks:	list of CPTS reference (RFTCLK) clock's parents as defined in Data manual
--- ti,mux-tbl: array of multiplexer indexes as defined in Data manual
--- assigned-clocks: should point on cpts-refclk-mux clock
--- assigned-clock-parents: should point on required RFTCLK clock parent to be selected
-- cpts_clock_mult: (optional) Numerator to convert input clock ticks
		into nanoseconds
-- cpts_clock_shift: (optional) Denominator to convert input clock ticks into
		nanoseconds.
		Mult and shift will be calculated basing on CPTS
		rftclk frequency if both cpts_clock_shift and
		cpts_clock_mult properties are not provided.

Optional properties:
- enable-ale:	NetCP driver keeps the address learning feature in the ethernet
		switch module disabled. This attribute is to enable the address
		learning.
- secondary-slave-ports:	specification for each of the switch port not be
				registered as a network interface. NetCP driver
				will only initialize these ports and attach PHY
				driver to them if needed.

NetCP interface properties: Interface specification for NetCP sub-modules.
Required properties:
- rx-channel:	the navigator packet dma channel name for rx.
- rx-queue:	the navigator queue number associated with rx dma channel.
- rx-pool:	specifies the number of descriptors to be used & the region-id
		for creating the rx descriptor pool.
- tx-pool:	specifies the number of descriptors to be used & the region-id
		for creating the tx descriptor pool.
- rx-queue-depth:	number of descriptors in each of the free descriptor
			queue (FDQ) for the pktdma Rx flow. There can be at
			present a maximum of 4 queues per Rx flow.
- rx-buffer-size:	the buffer size for each of the Rx flow FDQ.
- tx-completion-queue:	the navigator queue number where the descriptors are
			recycled after Tx DMA completion.

Optional properties:
- efuse-mac:	If this is 1, then the MAC address for the interface is
		obtained from the device efuse mac address register.
		If this is 2, the two DWORDs occupied by the MAC address
		are swapped.  The netcp driver will swap the two DWORDs
		back to the proper order when this property is set to 2
		when it obtains the mac address from efuse.
- "netcp-device label":	phandle to the device specification for each of NetCP
			sub-module attached to this interface.

The MAC address will be determined using the optional properties defined in
ethernet.txt and only if efuse-mac is set to 0. If all of the optional MAC
address properties are not present, then the driver will use a random MAC
address.

Example binding:

netcp: netcp@2000000 {
	reg = <0x2620110 0x8>;
	reg-names = "efuse";
	compatible = "ti,netcp-1.0";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges  = <0 0x2000000 0xfffff>;
	clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>;
	dma-coherent;
	/* big-endian; */
	dma-id = <0>;

	netcp-devices {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		gbe@90000 {
			label = "netcp-gbe";
			reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>;
			/* enable-ale; */
			tx-queue = <648>;
			tx-channel = <8>;

			cpts {
				clocks = <&cpts_refclk_mux>;
				clock-names = "cpts";

				cpts_refclk_mux: cpts-refclk-mux {
					#clock-cells = <0>;
					clocks = <&chipclk12>, <&chipclk13>,
						 <&timi0>, <&timi1>,
						 <&tsipclka>, <&tsrefclk>,
						 <&tsipclkb>;
					ti,mux-tbl = <0x0>, <0x1>, <0x2>,
						<0x3>, <0x4>, <0x8>, <0xC>;
					assigned-clocks = <&cpts_refclk_mux>;
					assigned-clock-parents = <&chipclk12>;
				};
			};

			interfaces {
				gbe0: interface-0 {
					slave-port = <0>;
					link-interface	= <4>;
				};
				gbe1: interface-1 {
					slave-port = <1>;
					link-interface	= <4>;
				};
			};

			secondary-slave-ports {
				port-2 {
					slave-port = <2>;
					link-interface	= <2>;
				};
				port-3 {
					slave-port = <3>;
					link-interface	= <2>;
				};
			};
		};
	};

	netcp-interfaces {
		interface-0 {
			rx-channel = <22>;
			rx-pool = <1024 12>;
			tx-pool = <1024 12>;
			rx-queue-depth = <128 128 0 0>;
			rx-buffer-size = <1518 4096 0 0>;
			rx-queue = <8704>;
			tx-completion-queue = <8706>;
			efuse-mac = <1>;
			netcp-gbe = <&gbe0>;

		};
		interface-1 {
			rx-channel = <23>;
			rx-pool = <1024 12>;
			tx-pool = <1024 12>;
			rx-queue-depth = <128 128 0 0>;
			rx-buffer-size = <1518 4096 0 0>;
			rx-queue = <8705>;
			tx-completion-queue = <8707>;
			efuse-mac = <0>;
			local-mac-address = [02 18 31 7e 3e 6f];
			netcp-gbe = <&gbe1>;
		};
	};
};

CPTS board configuration - select external CPTS RFTCLK:

&tsrefclk{
	clock-frequency = <500000000>;
};

&cpts_refclk_mux {
	assigned-clock-parents = <&tsrefclk>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/lantiq,etop-xway.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Lantiq Xway ETOP Ethernet driver

maintainers:
  - John Crispin <john@phrozen.org>

properties:
  $nodename:
    pattern: "^ethernet@[0-9a-f]+$"

  compatible:
    const: lantiq,etop-xway

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: TX interrupt
      - description: RX interrupt

  interrupt-names:
    items:
      - const: tx
      - const: rx

  lantiq,tx-burst-length:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      TX programmable burst length.
    enum: [2, 4, 8]

  lantiq,rx-burst-length:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      RX programmable burst length.
    enum: [2, 4, 8]

  phy-mode: true

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - lantiq,tx-burst-length
  - lantiq,rx-burst-length
  - phy-mode

additionalProperties: false

examples:
  - |
    ethernet@e180000 {
        compatible = "lantiq,etop-xway";
        reg = <0xe180000 0x40000>;
        interrupt-parent = <&icu0>;
        interrupts = <73>, <78>;
        interrupt-names = "tx", "rx";
        lantiq,tx-burst-length = <8>;
        lantiq,rx-burst-length = <8>;
        phy-mode = "rmii";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/lantiq,xrx200-net.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Lantiq xRX200 GSWIP PMAC Ethernet driver

maintainers:
  - Hauke Mehrtens <hauke@hauke-m.de>

properties:
  $nodename:
    pattern: "^ethernet@[0-9a-f]+$"

  compatible:
    const: lantiq,xrx200-net

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: TX interrupt
      - description: RX interrupt

  interrupt-names:
    items:
      - const: tx
      - const: rx

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:
  - |
    ethernet@e10b308 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "lantiq,xrx200-net";
        reg = <0xe10b308 0xcf8>;
        interrupt-parent = <&icu0>;
        interrupts = <73>, <72>;
        interrupt-names = "tx", "rx";
    };


code:
# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/litex,liteeth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LiteX LiteETH ethernet device

maintainers:
  - Joel Stanley <joel@jms.id.au>

description: |
  LiteETH is a small footprint and configurable Ethernet core for FPGA based
  system on chips.

  The hardware source is Open Source and can be found on at
  https://github.com/enjoy-digital/liteeth/.

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    const: litex,liteeth

  reg:
    items:
      - description: MAC registers
      - description: MDIO registers
      - description: Packet buffer

  reg-names:
    items:
      - const: mac
      - const: mdio
      - const: buffer

  interrupts:
    maxItems: 1

  litex,rx-slots:
    description: Number of slots in the receive buffer
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    default: 2

  litex,tx-slots:
    description: Number of slots in the transmit buffer
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    default: 2

  litex,slot-size:
    description: Size in bytes of a slot in the tx/rx buffer
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0x800
    default: 0x800

  mac-address: true
  local-mac-address: true
  phy-handle: true

  mdio:
    $ref: mdio.yaml#
    unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    mac: ethernet@8020000 {
        compatible = "litex,liteeth";
        reg = <0x8021000 0x100>,
              <0x8020800 0x100>,
              <0x8030000 0x2000>;
        reg-names = "mac", "mdio", "buffer";
        litex,rx-slots = <2>;
        litex,tx-slots = <2>;
        litex,slot-size = <0x800>;
        interrupts = <0x11 0x1>;
        phy-handle = <&eth_phy>;

        mdio {
          #address-cells = <1>;
          #size-cells = <0>;

          eth_phy: ethernet-phy@0 {
            reg = <0>;
          };
        };
    };
...

#  vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :


code:
* NXP LPC32xx SoC Ethernet Controller

Required properties:
- compatible: Should be "nxp,lpc-eth"
- reg: Address and length of the register set for the device
- interrupts: Should contain ethernet controller interrupt

Optional properties:
- phy-mode: See ethernet.txt file in the same directory. If the property is
  absent, "rmii" is assumed.
- use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering

Optional subnodes:
- mdio : specifies the mdio bus, used as a container for phy nodes according to
  phy.txt in the same directory

Example:

	mac: ethernet@31060000 {
		compatible = "nxp,lpc-eth";
		reg = <0x31060000 0x1000>;
		interrupt-parent = <&mic>;
		interrupts = <29 0>;

		phy-mode = "rmii";
		use-iram;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/marvell,dfx-server.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell Prestera DFX server

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

select:
  properties:
    compatible:
      contains:
        const: marvell,dfx-server
  required:
    - compatible

properties:
  compatible:
    items:
      - const: marvell,dfx-server
      - const: simple-bus

  reg:
    maxItems: 1

  ranges: true

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

required:
  - compatible
  - reg
  - ranges

# The DFX server may expose clocks described as subnodes
additionalProperties:
  type: object

examples:
  - |

    #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
    bus@0 {
        reg = <0 0>;
        #address-cells = <2>;
        #size-cells = <1>;

        dfx-bus@ac000000 {
            compatible = "marvell,dfx-server", "simple-bus";
            #address-cells = <1>;
            #size-cells = <1>;
            ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
            reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/marvell,mvusb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell USB to MDIO Controller

maintainers:
  - Tobias Waldekranz <tobias@waldekranz.com>

description: |+
  This controller is mounted on development boards for Marvell's Link Street
  family of Ethernet switches. It allows you to configure the switch's registers
  using the standard MDIO interface.

  Since the device is connected over USB, there is no strict requirement of
  having a device tree representation of the device. But in order to use it with
  the mv88e6xxx driver, you need a device tree node in which to place the switch
  definition.

allOf:
  - $ref: "mdio.yaml#"

properties:
  compatible:
    const: usb1286,1fa4
  reg:
    maxItems: 1
    description: The USB port number on the host controller

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"

unevaluatedProperties: false

examples:
  - |
    /* USB host controller */
    usb {
            #address-cells = <1>;
            #size-cells = <0>;

            mdio@1 {
                    compatible = "usb1286,1fa4";
                    reg = <1>;
                    #address-cells = <1>;
                    #size-cells = <0>;

                    switch@0 {
                            compatible = "marvell,mv88e6190";
                            reg = <0x0>;

                            ports {
                                    /* Port definitions */
                            };

                            mdio {
                                    /* PHY definitions */
                            };
                    };
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/marvell,orion-mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell MDIO Ethernet Controller interface

maintainers:
  - Andrew Lunn <andrew@lunn.ch>

description: |
  The Ethernet controllers of the Marvel Kirkwood, Dove, Orion5x, MV78xx0,
  Armada 370, Armada XP, Armada 7k and Armada 8k have an identical unit that
  provides an interface with the MDIO bus. Additionally, Armada 7k and Armada
  8k has a second unit which provides an interface with the xMDIO bus. This
  driver handles these interfaces.

allOf:
  - $ref: "mdio.yaml#"

properties:
  compatible:
    enum:
      - marvell,orion-mdio
      - marvell,xmdio

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 4

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    mdio@d0072004 {
      compatible = "marvell,orion-mdio";
      reg = <0xd0072004 0x4>;
      #address-cells = <1>;
      #size-cells = <0>;
      interrupts = <30>;

      phy0: ethernet-phy@0 {
        reg = <0>;
      };

      phy1: ethernet-phy@1 {
        reg = <1>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/marvell,pp2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell CN913X / Marvell Armada 375, 7K, 8K Ethernet Controller

maintainers:
  - Marcin Wojtas <mw@semihalf.com>
  - Russell King <linux@armlinux.org>

description: |
  Marvell Armada 375 Ethernet Controller (PPv2.1)
  Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
  Marvell CN913X Ethernet Controller (PPv2.3)

properties:
  compatible:
    enum:
      - marvell,armada-375-pp2
      - marvell,armada-7k-pp22

  reg:
    minItems: 3
    maxItems: 4

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  clocks:
    minItems: 2
    items:
      - description: main controller clock
      - description: GOP clock
      - description: MG clock
      - description: MG Core clock
      - description: AXI clock

  clock-names:
    minItems: 2
    items:
      - const: pp_clk
      - const: gop_clk
      - const: mg_clk
      - const: mg_core_clk
      - const: axi_clk

  dma-coherent: true

  marvell,system-controller:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: a phandle to the system controller.

patternProperties:
  '^(ethernet-)?port@[0-2]$':
    type: object
    description: subnode for each ethernet port.
    $ref: ethernet-controller.yaml#
    unevaluatedProperties: false

    properties:
      reg:
        description: ID of the port from the MAC point of view.
        maximum: 2

      interrupts:
        minItems: 1
        maxItems: 10
        description: interrupt(s) for the port

      interrupt-names:
        minItems: 1
        items:
          - const: hif0
          - const: hif1
          - const: hif2
          - const: hif3
          - const: hif4
          - const: hif5
          - const: hif6
          - const: hif7
          - const: hif8
          - const: link

        description: >
          if more than a single interrupt for is given, must be the
          name associated to the interrupts listed. Valid names are:
          "hifX", with X in [0..8], and "link". The names "tx-cpu0",
          "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported
          for backward compatibility but shouldn't be used for new
          additions.

      phys:
        minItems: 1
        maxItems: 2
        description: >
          Generic PHY, providing SerDes connectivity. For most modes,
          one lane is sufficient, but some (e.g. RXAUI) may require two.

      phy-mode:
        enum:
          - gmii
          - sgmii
          - rgmii-id
          - 1000base-x
          - 2500base-x
          - 5gbase-r
          - rxaui
          - 10gbase-r

      port-id:
        $ref: /schemas/types.yaml#/definitions/uint32
        deprecated: true
        description: >
          ID of the port from the MAC point of view.
          Legacy binding for backward compatibility.

      marvell,loopback:
        $ref: /schemas/types.yaml#/definitions/flag
        description: port is loopback mode.

      gop-port-id:
        $ref: /schemas/types.yaml#/definitions/uint32
        description: >
          only for marvell,armada-7k-pp22, ID of the port from the
          GOP (Group Of Ports) point of view. This ID is used to index the
          per-port registers in the second register area.

    required:
      - reg
      - interrupts
      - phy-mode
      - port-id

required:
  - compatible
  - reg
  - clocks
  - clock-names

allOf:
  - if:
      properties:
        compatible:
          const: marvell,armada-7k-pp22
    then:
      properties:
        reg:
          items:
            - description: Packet Processor registers
            - description: Networking interfaces registers
            - description: CM3 address space used for TX Flow Control

        clocks:
          minItems: 5

        clock-names:
          minItems: 5

      patternProperties:
        '^(ethernet-)?port@[0-2]$':
          required:
            - gop-port-id

      required:
        - marvell,system-controller
    else:
      properties:
        reg:
          items:
            - description: Packet Processor registers
            - description: LMS registers
            - description: Register area per eth0
            - description: Register area per eth1

        clocks:
          maxItems: 2

        clock-names:
          maxItems: 2

      patternProperties:
        '^(ethernet-)?port@[0-1]$':
          properties:
            reg:
              maximum: 1

            gop-port-id: false

additionalProperties: false

examples:
  - |
    // For Armada 375 variant
    #include <dt-bindings/interrupt-controller/mvebu-icu.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    ethernet@f0000 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "marvell,armada-375-pp2";
        reg = <0xf0000 0xa000>,
              <0xc0000 0x3060>,
              <0xc4000 0x100>,
              <0xc5000 0x100>;
        clocks = <&gateclk 3>, <&gateclk 19>;
        clock-names = "pp_clk", "gop_clk";

        ethernet-port@0 {
            interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
            reg = <0>;
            port-id = <0>; /* For backward compatibility. */
            phy = <&phy0>;
            phy-mode = "rgmii-id";
        };

        ethernet-port@1 {
            interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
            reg = <1>;
            port-id = <1>; /* For backward compatibility. */
            phy = <&phy3>;
            phy-mode = "gmii";
        };
    };

  - |
    // For Armada 7k/8k and Cn913x variants
    #include <dt-bindings/interrupt-controller/mvebu-icu.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    ethernet@0 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "marvell,armada-7k-pp22";
        reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
        clocks = <&cp0_clk 1 3>, <&cp0_clk 1 9>,
                 <&cp0_clk 1 5>, <&cp0_clk 1 6>, <&cp0_clk 1 18>;
        clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";
        marvell,system-controller = <&cp0_syscon0>;

        ethernet-port@0 {
            interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 59 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 63 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 67 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 71 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
                              "hif5", "hif6", "hif7", "hif8", "link";
            phy-mode = "10gbase-r";
            phys = <&cp0_comphy4 0>;
            reg = <0>;
            port-id = <0>; /* For backward compatibility. */
            gop-port-id = <0>;
        };

        ethernet-port@1 {
            interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 60 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 64 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 68 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 72 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
                              "hif5", "hif6", "hif7", "hif8", "link";
            phy-mode = "rgmii-id";
            reg = <1>;
            port-id = <1>; /* For backward compatibility. */
            gop-port-id = <2>;
        };

        ethernet-port@2 {
            interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 61 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 65 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 69 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 73 IRQ_TYPE_LEVEL_HIGH>,
                         <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",
                              "hif5", "hif6", "hif7", "hif8", "link";
            phy-mode = "2500base-x";
            managed = "in-band-status";
            phys = <&cp0_comphy5 2>;
            sfp = <&sfp_eth3>;
            reg = <2>;
            port-id = <2>; /* For backward compatibility. */
            gop-port-id = <3>;
        };
    };