code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019~2020, 2022 NXP
 */

/dts-v1/;

#include "imx8dxl.dtsi"

/ {
	model = "Freescale i.MX8DXL EVK";
	compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";

	aliases {
		i2c2 = &i2c2;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		serial0 = &lpuart0;
	};

	chosen {
		stdout-path = &lpuart0;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * Memory reserved for optee usage. Please do not use.
		 * This will be automatically added to dtb if OP-TEE is installed.
		 * optee@96000000 {
		 *     reg = <0 0x96000000 0 0x2000000>;
		 *     no-map;
		 * };
		 */

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0 0x14000000>;
			alloc-ranges = <0 0x98000000 0 0x14000000>;
			linux,cma-default;
		};
	};

	mux3_en: regulator-0 {
		compatible = "regulator-fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-name = "mux3_en";
		gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
		regulator-always-on;
	};

	reg_fec1_sel: regulator-1 {
		compatible = "regulator-fixed";
		regulator-name = "fec1_supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
		regulator-always-on;
		status = "disabled";
	};

	reg_fec1_io: regulator-2 {
		compatible = "regulator-fixed";
		regulator-name = "fec1_io_supply";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
		status = "disabled";
	};

	reg_usdhc2_vmmc: regulator-3 {
		compatible = "regulator-fixed";
		regulator-name = "SD1_SPWR";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		off-on-delay-us = <3480>;
	};

	reg_vref_1v8: regulator-adc-vref {
		compatible = "regulator-fixed";
		regulator-name = "vref_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	mii_select: regulator-4 {
		compatible = "regulator-fixed";
		regulator-name = "mii-select";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};
};

&adc0 {
	vref-supply = <&reg_vref_1v8>;
	status = "okay";
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	nvmem-cells = <&fec_mac1>;
	nvmem-cell-names = "mac-address";
	snps,reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
	snps,reset-delays-us = <10 20 200000>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			eee-broken-1000t;
			qca,disable-smarteee;
			vddio-supply = <&vddio0>;

			vddio0: vddio-regulator {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};
		};
	};
};

/*
 * fec1 shares the some PINs with usdhc2.
 * by default usdhc2 is enabled in this dts.
 * Please disable usdhc2 to enable fec1
 */
&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-txid";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	rx-internal-delay-ps = <2000>;
	nvmem-cells = <&fec_mac0>;
	nvmem-cell-names = "mac-address";
	status = "disabled";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			qca,disable-smarteee;
			vddio-supply = <&vddio1>;

			vddio1: vddio-regulator {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};
		};
	};
};

&flexspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	nxp,fspi-dll-slvdly = <4>;
	status = "okay";

	mt35xu512aba0: flash@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <133000000>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
	};
};

&i2c2 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pca6416_1: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca6416_2: gpio@21 {
		compatible = "ti,tca6416";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9548_1: i2c-mux@70 {
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0>;

			max7322: gpio@68 {
				compatible = "maxim,max7322";
				reg = <0x68>;
				gpio-controller;
				#gpio-cells = <2>;
				status = "disabled";
			};
		};

		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x4>;
		};

		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x5>;
		};

		i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x6>;
		};
	};
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&lsio_gpio4 {
	status = "okay";
};

&lsio_gpio5 {
	status = "okay";
};

&thermal_zones {
	pmic-thermal0 {
		polling-delay-passive = <250>;
		polling-delay = <2000>;
		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;

		trips {
			pmic_alert0: trip0 {
				temperature = <110000>;
				hysteresis = <2000>;
				type = "passive";
			};

			pmic_crit0: trip1 {
				temperature = <125000>;
				hysteresis = <2000>;
				type = "critical";
			};
		};

		cooling-maps {
			map0 {
				trip = <&pmic_alert0>;
				cooling-device =
					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};
	};
};

&usbphy1 {
	/* USB eye diagram tests result */
	fsl,tx-d-cal = <114>;
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	srp-disable;
	hnp-disable;
	adp-disable;
	power-active-high;
	disable-over-current;
	status = "okay";
};

&usbphy2 {
	/* USB eye diagram tests result */
	fsl,tx-d-cal = <111>;
	status = "okay";
};

&usbotg2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg2>;
	srp-disable;
	hnp-disable;
	adp-disable;
	power-active-high;
	disable-over-current;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
	wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&lpspi3 {
	fsl,spi-num-chipselects = <1>;
	fsl,spi-only-use-cs1-sel;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi3>;
	pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
	status = "okay";

	spidev0: spi@0 {
		reg = <0>;
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <30000000>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD	0x000014a0
			IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1		0x0600004c
			IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN	0x0600004c
		>;
	};

	pinctrl_usbotg1: usbotg1grp {
		fsl,pins = <
			IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
		>;
	};

	pinctrl_usbotg2: usbotg2grp {
		fsl,pins = <
			IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR		0x00000021
		>;
	};

	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			IMX8DXL_ENET0_MDC_CONN_EQOS_MDC				0x06000020
			IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO			0x06000020
			IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC		0x06000020
			IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0		0x06000020
			IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1		0x06000020
			IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2		0x06000020
			IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3		0x06000020
			IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL	0x06000020
			IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC		0x06000020
			IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0		0x06000020
			IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1		0x06000020
			IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2		0x06000020
			IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3		0x06000020
			IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL	0x06000020
		>;
	};

	pinctrl_flexspi0: flexspi0grp {
		fsl,pins = <
			IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0     0x06000021
			IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1     0x06000021
			IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2     0x06000021
			IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3     0x06000021
			IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS         0x06000021
			IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B     0x06000021
			IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK       0x06000021
			IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK       0x06000021
			IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0     0x06000021
			IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1     0x06000021
			IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2     0x06000021
			IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3     0x06000021
			IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS         0x06000021
			IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B     0x06000021
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD		0x000014a0
			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD		0x000014a0
			IMX8DXL_ENET0_MDC_CONN_ENET0_MDC			0x06000020
			IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
			IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x00000060
			IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x00000060
			IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x00000060
			IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x00000060
			IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x00000060
			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
			IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x00000060
			IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x00000060
			IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x00000060
			IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x00000060
			IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x00000060
			IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
		>;
	};

	pinctrl_lpspi3: lpspi3grp {
		fsl,pins = <
			IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK		0x6000040
			IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO		0x6000040
			IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI		0x6000040
			IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1		0x6000040
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA		0x06000021
			IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL		0x06000021
		>;
	};

	pinctrl_cm40_lpuart: cm40lpuartgrp {
		fsl,pins = <
			IMX8DXL_ADC_IN2_M40_UART0_RX		0x06000020
			IMX8DXL_ADC_IN3_M40_UART0_TX		0x06000020
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA		0x06000021
			IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL		0x06000021
		>;
	};

	pinctrl_lpuart0: lpuart0grp {
		fsl,pins = <
			IMX8DXL_UART0_RX_ADMA_UART0_RX		0x06000020
			IMX8DXL_UART0_TX_ADMA_UART0_TX		0x06000020
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000040 /* RESET_B */
			IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x00000021 /* WP */
			IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019~2020, 2022 NXP
 */

&audio_ipg_clk {
	clock-frequency = <160000000>;
};

&dma_ipg_clk {
	clock-frequency = <160000000>;
};

&adc0 {
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
};

&i2c0 {
	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
};

&i2c1 {
	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
};

&i2c2 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
	interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
};

&i2c3 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
};

&lpuart0 {
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
	interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
};

&lpuart1 {
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
	interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
};

&lpuart2 {
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
	interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
};

&lpuart3 {
	compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
	interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
};

&lpspi0 {
	interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
};

&lpspi1 {
	interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
};

&lpspi2 {
	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
};

&lpspi3 {
	interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019~2020, 2022 NXP
 */

/delete-node/ &enet1_lpcg;
/delete-node/ &fec2;

&conn_subsys {
	conn_enet0_root_clk: clock-conn-enet0-root {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <250000000>;
		clock-output-names = "conn_enet0_root_clk";
	};

	eqos: ethernet@5b050000 {
		compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
		reg = <0x5b050000 0x10000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "eth_wake_irq", "macirq";
		clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
			 <&eqos_lpcg IMX_LPCG_CLK_6>,
			 <&eqos_lpcg IMX_LPCG_CLK_0>,
			 <&eqos_lpcg IMX_LPCG_CLK_5>,
			 <&eqos_lpcg IMX_LPCG_CLK_2>;
		clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
		assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
		assigned-clock-rates = <125000000>;
		power-domains = <&pd IMX_SC_R_ENET_1>;
		status = "disabled";
	};

	usbotg2: usb@5b0e0000 {
		compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
		reg = <0x5b0e0000 0x200>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
		fsl,usbphy = <&usbphy2>;
		fsl,usbmisc = <&usbmisc2 0>;
		/*
		 * usbotg1 and usbotg2 share one clcok.
		 * scu firmware disables the access to the clock and keeps
		 * it always on in case other core (M4) uses one of these.
		 */
		clocks = <&clk_dummy>;
		ahb-burst-config = <0x0>;
		tx-burst-size-dword = <0x10>;
		rx-burst-size-dword = <0x10>;
		#stream-id-cells = <1>;
		power-domains = <&pd IMX_SC_R_USB_1>;
		status = "disabled";

		clk_dummy: clock-dummy {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "clk_dummy";
		};
	};

	usbmisc2: usbmisc@5b0e0200 {
		#index-cells = <1>;
		compatible = "fsl,imx7ulp-usbmisc";
		reg = <0x5b0e0200 0x200>;
	};

	usbphy2: usbphy@0x5b110000 {
		compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
		reg = <0x5b110000 0x1000>;
		clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>;
		power-domains = <&pd IMX_SC_R_USB_1_PHY>;
		status = "disabled";
	};

	eqos_lpcg: clock-controller@5b240000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b240000 0x10000>;
		#clock-cells = <1>;
		clocks = <&conn_enet0_root_clk>,
			 <&conn_axi_clk>,
			 <&conn_axi_clk>,
			 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
			 <&conn_ipg_clk>;
		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>,
				<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
				<IMX_LPCG_CLK_6>;
		clock-output-names = "eqos_ptp",
				     "eqos_mem_clk",
				     "eqos_aclk",
				     "eqos_clk",
				     "eqos_csr_clk";
		power-domains = <&pd IMX_SC_R_ENET_1>;
	};

	usb2_2_lpcg: clock-controller@5b280000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x5b280000 0x10000>;
		#clock-cells = <1>;
		clock-indices = <IMX_LPCG_CLK_7>;
		clocks = <&conn_ipg_clk>;
		clock-output-names = "usboh3_2_phy_ipg_clk";
		power-domains = <&pd IMX_SC_R_USB_1_PHY>;
	};

};

&enet0_lpcg {
	clocks = <&conn_enet0_root_clk>,
		 <&conn_enet0_root_clk>,
		 <&conn_axi_clk>,
		 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
		 <&conn_ipg_clk>,
		 <&conn_ipg_clk>;
};

&fec1 {
	compatible = "fsl,imx8qm-fec";
	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
	assigned-clock-rates = <125000000>;
};

&usdhc1 {
	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
};

&usdhc2 {
	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
};

&usdhc3 {
	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};

&usbotg1 {
	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	/*
	 * usbotg1 and usbotg2 share one clock
	 * scfw disable clock access and keep it always on
	 * in case other core (M4) use one of these.
	 */
	clocks = <&clk_dummy>;
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2020 NXP
 */

&ddr_pmu0 {
	compatible = "fsl,imx8-ddr-pmu";
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019~2020, 2022 NXP
 */

&flexspi0 {
	compatible = "nxp,imx8dxl-fspi";
	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};

&lsio_gpio0 {
	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	gpio-ranges = <&iomuxc 0 47 13>,
		      <&iomuxc 13 61 4>,
		      <&iomuxc 19 67 4>,
		      <&iomuxc 24 72 1>;
};

&lsio_gpio1 {
	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	gpio-ranges = <&iomuxc 4 74 5>,
		      <&iomuxc 9 80 16>;
};

&lsio_gpio2 {
	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	gpio-ranges = <&iomuxc 1 98 2>,
		      <&iomuxc 3 101 1>,
		      <&iomuxc 5 107 8>;
};

&lsio_gpio3 {
	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	gpio-ranges = <&iomuxc 0 115 4>,
		      <&iomuxc 9 121 1>,
		      <&iomuxc 10 120 1>,
		      <&iomuxc 11 123 1>,
		      <&iomuxc 12 122 1>,
		      <&iomuxc 13 125 1>,
		      <&iomuxc 14 124 1>,
		      <&iomuxc 16 126 1>,
		      <&iomuxc 17 128 1>,
		      <&iomuxc 18 131 1>,
		      <&iomuxc 19 130 1>,
		      <&iomuxc 20 133 1>,
		      <&iomuxc 21 132 1>,
		      <&iomuxc 22 129 1>,
		      <&iomuxc 23 134 1>;
};

&lsio_gpio4 {
	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	gpio-ranges = <&iomuxc 0 0 3>,
		      <&iomuxc 3 4 4>,
		      <&iomuxc 7 9 12>,
		      <&iomuxc 19 22 2>,
		      <&iomuxc 21 25 2>,
		      <&iomuxc 29 29 3>;
};

&lsio_gpio5 {
	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	gpio-ranges = <&iomuxc 0 32 3>,
		      <&iomuxc 3 36 6>,
		      <&iomuxc 9 43 3>;
};

&lsio_gpio6 {
	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	gpio-ranges = <&iomuxc 0 53 7>,
		      <&iomuxc 8 86 10>,
		      <&iomuxc 19 107 8>;
};

&lsio_gpio7 {
	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	gpio-ranges = <&iomuxc 0 0 3>,
		      <&iomuxc 3 4 4>,
		      <&iomuxc 8 22 2>,
		      <&iomuxc 10 25 2>,
		      <&iomuxc 16 44 2>;
};

&lsio_mu0 {
	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
};

&lsio_mu1 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
};

&lsio_mu2 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
};

&lsio_mu3 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
};

&lsio_mu4 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
};

&lsio_mu5 {
	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019~2020, 2022 NXP
 */

#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/pads-imx8dxl.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec1;
		ethernet1 = &eqos;
		gpio0 = &lsio_gpio0;
		gpio1 = &lsio_gpio1;
		gpio2 = &lsio_gpio2;
		gpio3 = &lsio_gpio3;
		gpio4 = &lsio_gpio4;
		gpio5 = &lsio_gpio5;
		gpio6 = &lsio_gpio6;
		gpio7 = &lsio_gpio7;
		mu1 = &lsio_mu1;
	};

	cpus: cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		/* We have 1 clusters with 2 Cortex-A35 cores */
		A35_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&A35_L2>;
			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
			#cooling-cells = <2>;
			operating-points-v2 = <&a35_opp_table>;
		};

		A35_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&A35_L2>;
			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
			#cooling-cells = <2>;
			operating-points-v2 = <&a35_opp_table>;
		};

		A35_L2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	a35_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-900000000 {
			opp-hz = /bits/ 64 <900000000>;
			opp-microvolt = <1000000>;
			clock-latency-ns = <150000>;
		};

		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <1100000>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};
	};

	gic: interrupt-controller@51a00000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
		      <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp_reserved: dsp@92400000 {
			reg = <0 0x92400000 0 0x2000000>;
			no-map;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	system-controller {
		compatible = "fsl,imx-scu";
		mbox-names = "tx0",
			     "rx0",
			     "gip3";
		mboxes = <&lsio_mu1 0 0
			  &lsio_mu1 1 0
			  &lsio_mu1 3 3>;

		pd: power-controller {
			compatible = "fsl,scu-pd";
			#power-domain-cells = <1>;
			wakeup-irq = <160 163 235 236 237 228 229 230 231 238
				     239 240 166 169>;
		};

		clk: clock-controller {
			compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
			#clock-cells = <2>;
			clocks = <&xtal32k &xtal24m>;
			clock-names = "xtal_32KHz", "xtal_24Mhz";
		};

		scu_gpio: gpio {
			compatible = "fsl,imx8qxp-sc-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		iomuxc: pinctrl {
			compatible = "fsl,imx8dxl-iomuxc";
		};

		ocotp: ocotp {
			compatible = "fsl,imx8qxp-scu-ocotp";
			#address-cells = <1>;
			#size-cells = <1>;

			fec_mac0: mac@2c4 {
				reg = <0x2c4 6>;
			};

			fec_mac1: mac@2c6 {
				reg = <0x2c6 6>;
			};
		};

		rtc: rtc {
			compatible = "fsl,imx8qxp-sc-rtc";
		};

		sc_pwrkey: keys {
			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
			linux,keycode = <KEY_POWER>;
			wakeup-source;
		};

		watchdog {
			compatible = "fsl,imx-sc-wdt";
			timeout-sec = <60>;
		};

		tsens: thermal-sensor {
			compatible = "fsl,imx-sc-thermal";
			#thermal-sensor-cells = <1>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
	};

	thermal_zones: thermal-zones {
		cpu-thermal0 {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;

			trips {
				cpu_alert0: trip0 {
					temperature = <107000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip1 {
					temperature = <127000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	/* The two values below cannot be changed by the board */
	xtal32k: clock-xtal32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "xtal_32KHz";
	};

	xtal24m: clock-xtal24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "xtal_24MHz";
	};

	/* sorted in register address */
	#include "imx8-ss-adma.dtsi"
	#include "imx8-ss-conn.dtsi"
	#include "imx8-ss-ddr.dtsi"
	#include "imx8-ss-lsio.dtsi"
};

#include "imx8dxl-ss-adma.dtsi"
#include "imx8dxl-ss-conn.dtsi"
#include "imx8dxl-ss-lsio.dtsi"
#include "imx8dxl-ss-ddr.dtsi"


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Compass Electronics Group, LLC
 */

#include <dt-bindings/phy/phy-imx8-pcie.h>

/ {
	leds {
		compatible = "gpio-leds";

		led0 {
			label = "gen_led0";
			gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led1 {
			label = "gen_led1";
			gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led2 {
			label = "gen_led2";
			gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led3 {
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_led3>;
			label = "heartbeat";
			gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pcie0_refclk_gated:  pcie0-refclk-gated {
		compatible = "gpio-gate-clock";
		clocks = <&pcie0_refclk>;
		#clock-cells = <0>;
		enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
	};

	reg_audio: regulator-audio {
		compatible = "regulator-fixed";
		regulator-name = "3v3_aud";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usbotg1: regulator-usbotg1 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb_otg1>;
		regulator-name = "usb_otg_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_camera: regulator-camera {
		compatible = "regulator-fixed";
		regulator-name = "mipi_pwr";
		regulator-min-microvolt = <2800000>;
		regulator-max-microvolt = <2800000>;
		gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100000>;
	};

	reg_pcie0: regulator-pcie {
		compatible = "regulator-fixed";
		regulator-name = "pci_pwr_en";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
		gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
		startup-delay-us = <100000>;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	sound {
		compatible = "fsl,imx-audio-wm8962";
		model = "wm8962-audio";
		audio-cpu = <&sai3>;
		audio-codec = <&wm8962>;
		audio-routing =
			"Headphone Jack", "HPOUTL",
			"Headphone Jack", "HPOUTR",
			"Ext Spk", "SPKOUTL",
			"Ext Spk", "SPKOUTR",
			"AMIC", "MICBIAS",
			"IN3R", "AMIC";
	};
};

&csi {
	status = "okay";
};

&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_espi2>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	status = "okay";

	eeprom@0 {
		compatible = "microchip,at25160bn", "atmel,at25";
		reg = <0>;
		spi-max-frequency = <5000000>;
		spi-cpha;
		spi-cpol;
		pagesize = <32>;
		size = <2048>;
		address-width = <16>;
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	camera@3c {
		compatible = "ovti,ov5640";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ov5640>;
		reg = <0x3c>;
		clocks = <&clk IMX8MM_CLK_CLKO1>;
		clock-names = "xclk";
		assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
		assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
		assigned-clock-rates = <24000000>;
		AVDD-supply = <&reg_camera>;  /* 2.8v */
		powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;

		port {
			/* MIPI CSI-2 bus endpoint */
			ov5640_to_mipi_csi2: endpoint {
				remote-endpoint = <&imx8mm_mipi_csi_in>;
				clock-lanes = <0>;
				data-lanes = <1 2>;
			};
		};
	};
};

&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	wm8962: audio-codec@1a {
		compatible = "wlf,wm8962";
		reg = <0x1a>;
		clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
		DCVDD-supply = <&reg_audio>;
		DBVDD-supply = <&reg_audio>;
		AVDD-supply = <&reg_audio>;
		CPVDD-supply = <&reg_audio>;
		MICVDD-supply = <&reg_audio>;
		PLLVDD-supply = <&reg_audio>;
		SPKVDD1-supply = <&reg_audio>;
		SPKVDD2-supply = <&reg_audio>;
		gpio-cfg = <
			0x0000 /* 0:Default */
			0x0000 /* 1:Default */
			0x0000 /* 2:FN_DMICCLK */
			0x0000 /* 3:Default */
			0x0000 /* 4:FN_DMICCDAT */
			0x0000 /* 5:Default */
		>;
	};

	pca6416_0: gpio@20 {
		compatible = "nxp,pcal6416";
		reg = <0x20>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pcal6414>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio4>;
		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
	};

	pca6416_1: gpio@21 {
		compatible = "nxp,pcal6416";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio4>;
		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
	};
};

&mipi_csi {
	status = "okay";
	ports {
		port@0 {
			imx8mm_mipi_csi_in: endpoint {
				remote-endpoint = <&ov5640_to_mipi_csi2>;
				data-lanes = <1 2>;
			};
		};
	};
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,tx-deemph-gen1 = <0x2d>;
	fsl,tx-deemph-gen2 = <0xf>;
	fsl,clkreq-unsupported;
	clocks = <&pcie0_refclk_gated>;
	clock-names = "ref";
	status = "okay";
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
		 <&pcie0_refclk_gated>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_250M>;
	vpcie-supply = <&reg_pcie0>;
	status = "okay";
};

&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	fsl,sai-mclk-direction-output;
	status = "okay";
};

&snvs_pwrkey {
	status = "okay";
};

&uart2 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clk IMX8MM_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
	uart-has-rtscts;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usbotg1>;
	disable-over-current;
	dr_mode = "otg";
	status = "okay";
};

&usbotg2 {
	pinctrl-names = "default";
	disable-over-current;
	dr_mode = "host";
	status = "okay";
};

&usbphynop2 {
	reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&iomuxc {
	pinctrl_espi2: espi2grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x41
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
		>;
	};

	pinctrl_led3: led3grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x41
		>;
	};

	pinctrl_ov5640: ov5640grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
			MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59
		>;
	};

	pinctrl_pcal6414: pcal6414-gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19
		>;
	};

	pinctrl_reg_usb_otg1: usbotg1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29     0x19
		>;
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX	0x40
			MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX	0x40
			MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x40
			MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x40
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41
			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Compass Electronics Group, LLC
 */

/dts-v1/;

#include "imx8mm.dtsi"
#include "imx8mm-beacon-som.dtsi"
#include "imx8mm-beacon-baseboard.dtsi"

/ {
	model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit";
	compatible = "beacon,imx8mm-beacon-kit", "fsl,imx8mm";

	chosen {
		stdout-path = &uart2;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Compass Electronics Group, LLC
 */

/ {
	aliases {
		rtc0 = &rtc;
		rtc1 = &snvs_rtc;
	};

	usdhc1_pwrseq: usdhc1_pwrseq {
		compatible = "mmc-pwrseq-simple";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
		clocks = <&osc_32k>;
		clock-names = "ext_clock";
		post-power-on-delay-ms = <80>;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&A53_1 {
	cpu-supply = <&buck2_reg>;
};

&A53_2 {
	cpu-supply = <&buck2_reg>;
};

&A53_3 {
	cpu-supply = <&buck2_reg>;
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};
	};
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi>;
	status = "okay";

	flash@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <80000000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
		rohm,reset-snvs-powered;

		#clock-cells = <0>;
		clocks = <&osc_32k 0>;
		clock-output-names = "clk-32k-out";

		regulators {
			buck1_reg: BUCK1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			buck2_reg: BUCK2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <900000>;
			};

			buck3_reg: BUCK3 {
				// BUCK5 in datasheet
				regulator-name = "buck3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck4_reg: BUCK4 {
				// BUCK6 in datasheet
				regulator-name = "buck4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5_reg: BUCK5 {
				// BUCK7 in datasheet
				regulator-name = "buck5";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6_reg: BUCK6 {
				// BUCK8 in datasheet
				regulator-name = "buck6";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: LDO1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2_reg: LDO2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_reg: LDO3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4_reg: LDO4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo6_reg: LDO6 {
				regulator-name = "ldo6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	eeprom@50 {
		compatible = "microchip,24c64", "atmel,24c64";
		pagesize = <32>;
		read-only;	/* Manufacturing EEPROM programmed at factory */
		reg = <0x50>;
	};

	rtc: rtc@51 {
		compatible = "nxp,pcf85263";
		reg = <0x51>;
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
		compatible = "brcm,bcm43438-bt";
		shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
		clocks = <&osc_32k>;
		max-speed = <4000000>;
		clock-names = "extclk";
	};
};

&usdhc1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <4>;
	non-removable;
	cap-power-off-card;
	keep-power-in-suspend;
	mmc-pwrseq = <&usdhc1_pwrseq>;
	status = "okay";

	brcmf: bcrmf@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_wlan>;
		interrupt-parent = <&gpio2>;
		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "host-wake";
	};
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_flexspi: flexspigrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
		>;
	};

	pinctrl_pmic: pmicirqgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
			MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
			MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19
			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x19
			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x19
			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x141
		>;
	};

	pinctrl_usdhc1_gpio: usdhc1gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
		>;
	};

	pinctrl_wlan: wlangrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9		0x111
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Marek Vasut <marex@denx.de>
 */

/dts-v1/;

#include <dt-bindings/net/qca-ar803x.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm.dtsi"

/ {
	model = "Data Modul i.MX8M Mini eDM SBC";
	compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";

	aliases {
		rtc0 = &rtc;
		rtc1 = &snvs_rtc;
	};

	chosen {
		stdout-path = &uart3;
	};

	memory@40000000 {
		device_type = "memory";
		/* There are 1/2/4 GiB options, adjusted by bootloader. */
		reg = <0x0 0x40000000 0 0x40000000>;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_panel_backlight>;
		brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
		default-brightness-level = <7>;
		enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
		pwms = <&pwm1 0 5000000 0>;
		/* Disabled by default, unless display board plugged in. */
		status = "disabled";
	};

	clk_xtal25: clk-xtal25 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	clk_xtal32k: clk-xtal32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
	};

	panel: panel {
		backlight = <&backlight>;
		power-supply = <&reg_panel_vcc>;
		/* Disabled by default, unless display board plugged in. */
		status = "disabled";
	};

	reg_panel_vcc: regulator-panel-vcc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_panel_vcc_reg>;
		regulator-name = "PANEL_VCC";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio3 6 0>;
		enable-active-high;
		/* Disabled by default, unless display board plugged in. */
		status = "disabled";
	};

	reg_usdhc2_vcc: regulator-usdhc2-vcc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
		regulator-name = "V_3V3_SD";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 0>;
		enable-active-high;
	};

	watchdog {
		/* TPS3813 */
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_watchdog_gpio>;
		compatible = "linux,wdt-gpio";
		gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
		hw_algo = "level";
		/* Reset triggers in 2..3 seconds */
		hw_margin_ms = <1500>;
		/* Disabled by default */
		status = "disabled";
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&A53_1 {
	cpu-supply = <&buck2_reg>;
};

&A53_2 {
	cpu-supply = <&buck2_reg>;
};

&A53_3 {
	cpu-supply = <&buck2_reg>;
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	status = "okay";

	flash@0 {	/* W25Q128FVSI */
		compatible = "jedec,spi-nor";
		m25p,fast-read;
		spi-max-frequency = <50000000>;
		reg = <0>;
	};
};

&ecspi2 {	/* Feature connector SPI */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	/* Disabled by default, unless feature board plugged in. */
	status = "disabled";
};

&ecspi3 {	/* Display connector SPI */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
	/* Disabled by default, unless display board plugged in. */
	status = "disabled";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&fec1_phy>;
	phy-supply = <&buck4_reg>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		/* Atheros AR8031 PHY */
		fec1_phy: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			/*
			 * Dedicated ENET_WOL# signal is unused, the PHY
			 * can wake the SoC up via INT signal as well.
			 */
			interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>;
			reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			reset-deassert-us = <10000>;
			qca,keep-pll-enabled;
			vddio-supply = <&vddio>;

			vddio: vddio-regulator {
				regulator-name = "VDDIO";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};

			vddh: vddh-regulator {
				regulator-name = "VDDH";
			};
		};
	};
};

&gpio1 {
	gpio-line-names =
		"", "ENET_RST#", "WDOG_B#", "PMIC_INT#",
		"", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#",
		"WDOG_KICK#", "M2-B_PCIE_CLKREQ#",
		"USB1_OTG_ID_3V3", "ENET_WOL#",
		"", "", "", "ENET_INT#",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio2 {
	gpio-line-names =
		"MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#",
		"M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#",
		"PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#",
		"MEMCFG0", "WDOG_EN",
		"M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#",
		"", "", "", "",
		"", "", "", "SD2_RESET#", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio3 {
	gpio-line-names =
		"BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
		"", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
		"CSI_PD_1V8", "CSI_RESET_1V8#", "", "",
		"", "", "", "",
		"", "", "", "M2-B_WAKE_WWAN_1V8#",
		"M2-B_RESET_1V8#", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio4 {
	gpio-line-names =
		"NC0", "NC1", "BOOTCFG0", "BOOTCFG1",
		"BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5",
		"BOOTCFG6", "BOOTCFG7", "NC10", "NC11",
		"BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11",
		"BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15",
		"NC20", "", "", "",
		"", "CAN_INT#", "CAN_RST#", "GPIO4_IO27",
		"DIS_USB_DN2", "", "", "";
};

&gpio5 {
	gpio-line-names =
		"", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03",
		"GPIO5_IO04", "", "", "",
		"", "SPI1_CS#", "", "",
		"", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
		"I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
		"I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "",
		"", "SPI3_CS#", "", "", "", "", "", "";
};

&i2c1 {
	/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	pmic: pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		#clock-cells = <0>;
		clocks = <&clk_xtal32k 0>;
		clock-output-names = "clk-32k-out";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
		rohm,reset-snvs-powered;

		/*
		 * i.MX 8M Mini Data Sheet for Consumer Products
		 * 3.1.3 Operating ranges
		 * MIMX8MM4DVTLZAA
		 */
		regulators {
			/* VDD_SOC */
			buck1_reg: BUCK1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <850000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			/* VDD_ARM */
			buck2_reg: BUCK2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1050000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <950000>;
			};

			/* VDD_DRAM, BUCK5 */
			buck3_reg: BUCK3 {
				regulator-name = "buck3";
				/* 1.5 GHz DDR bus clock */
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* 3V3_VDD, BUCK6 */
			buck4_reg: BUCK4 {
				regulator-name = "buck4";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* 1V8_VDD, BUCK7 */
			buck5_reg: BUCK5 {
				regulator-name = "buck5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* 1V1_NVCC_DRAM, BUCK8 */
			buck6_reg: BUCK6 {
				regulator-name = "buck6";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* 1V8_NVCC_SNVS */
			ldo1_reg: LDO1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* 0V8_VDD_SNVS */
			ldo2_reg: LDO2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* 1V8_VDDA */
			ldo3_reg: LDO3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* 0V9_VDD_PHY */
			ldo4_reg: LDO4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* 1V2_VDD_PHY */
			ldo6_reg: LDO6 {
				regulator-name = "ldo6";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c2 {
	/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	usb-hub@2c {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb_hub>;
		compatible = "microchip,usb2514bi";
		reg = <0x2c>;
		individual-port-switching;
		reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
		self-powered;
	};

	eeprom: eeprom@50 {
		compatible = "atmel,24c32";
		reg = <0x50>;
		pagesize = <32>;
	};

	rtc: rtc@68 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_rtc>;
		compatible = "st,m41t62";
		reg = <0x68>;
		interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>;
	};

	pcieclk: clk@6a {
		compatible = "renesas,9fgv0241";
		reg = <0x6a>;
		clocks = <&clk_xtal25>;
		#clock-cells = <1>;
	};
};

&i2c3 {	/* Display connector I2C */
	/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
	clock-frequency = <320000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&i2c4 {	/* Feature connector I2C */
	/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
	clock-frequency = <320000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
		    <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
		    <&pinctrl_panel_expansion>;

	pinctrl_ecspi1: ecspi1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x44
			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x44
			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x44
			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x40
		>;
	};

	pinctrl_ecspi2: ecspi2-grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x44
			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x44
			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x44
			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x40
		>;
	};

	pinctrl_ecspi3: ecspi3-grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x44
			MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x44
			MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x44
			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x40
		>;
	};

	pinctrl_fec1: fec1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			/* ENET_RST# */
			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x6
			/* ENET_WOL# */
			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x40000090
			/* ENET_INT# */
			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x40000090
		>;
	};

	pinctrl_hog_feature: hog-feature-grp {
		fsl,pins = <
			/* GPIO4_IO27 */
			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x40000006
			/* GPIO5_IO03 */
			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3			0x40000006
			/* GPIO5_IO04 */
			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4			0x40000006

			/* CAN_INT# */
			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25		0x40000090
			/* CAN_RST# */
			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26		0x26
		>;
	};

	pinctrl_hog_panel: hog-panel-grp {
		fsl,pins = <
			/* GRAPHICS_GPIO0_1V8 */
			MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7		0x26
		>;
	};

	pinctrl_hog_misc: hog-misc-grp {
		fsl,pins = <
			/* PG_V_IN_VAR# */
			MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x40000000
			/* CSI_PD_1V8 */
			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8		0x0
			/* CSI_RESET_1V8# */
			MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9		0x0

			/* DIS_USB_DN1 */
			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1			0x0
			/* DIS_USB_DN2 */
			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x0

			/* EEPROM_WP_1V8# */
			MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5		0x100
			/* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6		0x0
			/* GRAPHICS_PRSNT_1V8# */
			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7		0x40000000

			/* CLK_CCM_CLKO1_3V3 */
			MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x10
		>;
	};

	pinctrl_hog_sbc: hog-sbc-grp {
		fsl,pins = <
			/* MEMCFG[0..2] straps */
			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8		0x40000140
			MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1			0x40000140
			MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0			0x40000140

			/* BOOT_CFG[0..15] straps */
			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2		0x40000000
			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3		0x40000000
			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4		0x40000000
			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5		0x40000000
			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6		0x40000000
			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x40000000
			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x40000000
			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x40000000
			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12		0x40000000
			MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13		0x40000000
			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x40000000
			MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x40000000
			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x40000000
			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x40000000
			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x40000000
			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x40000000

			/* Not connected pins */
			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20		0x0
			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x0
			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11		0x0
			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0		0x0
			MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1			0x0
		>;
	};

	pinctrl_i2c1: i2c1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000084
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x40000084
		>;
	};

	pinctrl_i2c1_gpio: i2c1-gpio-grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14		0x84
			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15		0x84
		>;
	};

	pinctrl_i2c2: i2c2-grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000084
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x40000084
		>;
	};

	pinctrl_i2c2_gpio: i2c2-gpio-grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x84
			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x84
		>;
	};

	pinctrl_i2c3: i2c3-grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000084
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000084
		>;
	};

	pinctrl_i2c3_gpio: i2c3-gpio-grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x84
			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x84
		>;
	};

	pinctrl_i2c4: i2c4-grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000084
			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000084
		>;
	};

	pinctrl_i2c4_gpio: i2c4-gpio-grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20		0x84
			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21		0x84
		>;
	};

	pinctrl_panel_backlight: panel-backlight-grp {
		fsl,pins = <
			/* BL_ENABLE_1V8 */
			MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0			0x104
		>;
	};

	pinctrl_panel_expansion: panel-expansion-grp {
		fsl,pins = <
			/* DSI_RESET_1V8# */
			MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2		0x2
			/* DSI_IRQ_1V8# */
			MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3		0x40000090
		>;
	};

	pinctrl_panel_vcc_reg: panel-vcc-grp {
		fsl,pins = <
			/* TFT_ENABLE_1V8 */
			MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6		0x104
		>;
	};

	pinctrl_panel_pwm: panel-pwm-grp {
		fsl,pins = <
			/* BL_PWM_3V3 */
			MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT		0x12
		>;
	};

	pinctrl_pcie0: pcie-grp {
		fsl,pins = <
			/* M2-B_RESET_1V8# */
			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20		0x102
			/* M2-B_PCIE_RST# */
			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x2
			/* M2-B_FULL_CARD_PWROFF_1V8# */
			MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4		0x102
			/* M2-B_W_DISABLE1_WWAN_1V8# */
			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10		0x102
			/* M2-B_W_DISABLE2_GPS_1V8# */
			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11		0x102
			/* CLK_M2_32K768 */
			MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x14
			/* M2-B_WAKE_WWAN_1V8# */
			MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x40000140
			/* M2-B_PCIE_WAKE# */
			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x40000140
			/* M2-B_PCIE_CLKREQ# */
			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x40000140
		>;
	};

	pinctrl_pmic: pmic-grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x40000090
		>;
	};

	pinctrl_rtc: rtc-grp {
		fsl,pins = <
			/* RTC_IRQ# */
			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x40000090
		>;
	};

	pinctrl_sai5: sai5-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK		0x100
			MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0		0x0
			MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC		0x100
			MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK		0x100
			MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0		0x100
		>;
	};

	pinctrl_uart1: uart1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX		0x90
			MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B		0x90
			MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX		0x50
			MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B		0x50
		>;
	};

	pinctrl_uart2: uart2-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x50
			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x90
			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x50
			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x90
		>;
	};

	pinctrl_uart3: uart3-grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x40
			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x40
		>;
	};

	pinctrl_uart4: uart4-grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x40
			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x40
		>;
	};

	pinctrl_usb_hub: usb-hub-grp {
		fsl,pins = <
			/* USBHUB_RESET# */
			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x4
		>;
	};

	pinctrl_usb_otg1: usb-otg1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x40000000
			MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR		0x4
			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x40000090
		>;
	};

	pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x4
		>;
	};

	pinctrl_usdhc2: usdhc2-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
			MX8MM_IOMUXC_SD2_WP_USDHC2_WP			0x400000d6
			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B		0x0d6
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
			MX8MM_IOMUXC_SD2_WP_USDHC2_WP			0x400000d6
			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B		0x0d6
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
			MX8MM_IOMUXC_SD2_WP_USDHC2_WP			0x400000d6
			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B		0x0d6
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3-grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
			MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B		0x40
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
			MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B		0x40
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
			MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B		0x40
		>;
	};

	pinctrl_watchdog_gpio: watchdog-gpio-grp {
		fsl,pins = <
			/* WDOG_B# */
			MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2		0x26
			/* WDOG_EN -- ungate WDT RESET# signal propagation */
			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9		0x6
			/* WDOG_KICK# / WDI */
			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x26
		>;
	};
};

&pcie_phy {
	fsl,clkreq-unsupported;	/* CLKREQ_B is not connected to suitable input */
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,tx-deemph-gen1 = <0x2d>;
	fsl,tx-deemph-gen2 = <0xf>;
	clocks = <&pcieclk 0>;
	status = "okay";
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
		 <&pcieclk 0>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_250M>;
	status = "okay";
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_panel_pwm>;
	/* Disabled by default, unless display board plugged in. */
	status = "disabled";
};

&sai5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai5>;
	fsl,sai-mclk-direction-output;
	/* Input into codec PLL */
	assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
	assigned-clock-rates = <22579200>;
	/* Disabled by default, unless display board plugged in. */
	status = "disabled";
};

&snvs_rtc {
	clocks = <&pmic>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	uart-has-rtscts;
	status = "disabled";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "disabled";
};

&uart3 {	/* A53 Debug */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&uart4 {	/* M4 Debug */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	/* UART4 is reserved for CM and RDC blocks CA access to UART4. */
	status = "disabled";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1>;
	dr_mode = "otg";
	status = "okay";
};

&usbotg2 {
	disable-over-current;
	dr_mode = "host";
	status = "okay";
};

&usdhc2 {	/* MicroSD */
	assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vcc>;
	status = "okay";
};

&usdhc3 {	/* eMMC */
	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	vmmc-supply = <&buck4_reg>;
	vqmmc-supply = <&buck5_reg>;
	status = "okay";
};

&wdog1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2020 NXP
 */

/dts-v1/;

#include "imx8mm-evk.dtsi"

/ {
	model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board";
	compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm";

	leds {
		pinctrl-0 = <&pinctrl_gpio_led_2>;

		status {
			gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
		};
	};
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	status = "okay";
};

&iomuxc {
	pinctrl_gpmi_nand: gpmi-nand {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE		0x00000096
			MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B		0x00000096
			MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B		0x00000096
			MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE		0x00000096
			MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00		0x00000096
			MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01		0x00000096
			MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02		0x00000096
			MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03		0x00000096
			MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04		0x00000096
			MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05		0x00000096
			MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06		0x00000096
			MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07		0x00000096
			MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B		0x00000096
			MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B	0x00000056
			MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B		0x00000096
			MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B		0x00000096
		>;
	};

	pinctrl_gpio_led_2: gpioled2grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x19
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 or MIT)
//
// Copyright (c) 2021 emtrion GmbH
// Author: Frank Erdrich <frank.erdrich@emtrion.com>
//

/dts-v1/;

#include "imx8mm-emcon.dtsi"
#include "imx8mm-emcon-avari.dtsi"

/ {
	model = "emtrion SoM emCON-MX8M mini on Avari";
	compatible = "emtrion,emcon-mx8mm-avari", "fsl,imx8mm";
};

&lvds_backlight {
	status = "okay";
};

&pwm1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0 or MIT)
//
// Copyright (C) 2021 emtrion GmbH
// Author: Frank Erdrich <frank.erdrich@emtrion.com>
//

/ {
	aliases {
		boardid = &boardID;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
	};

	chosen {
		stdout-path = &uart1;
	};

	reg_wall_5p0: regulator-wall5p0 {
		compatible = "regulator-fixed";
		regulator-name = "Main-Supply";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_base3p3: regulator-base3p3 {
		compatible = "regulator-fixed";
		vin-supply = <&reg_wall_5p0>;
		regulator-name = "3V3-avari";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_base1p5: regulator-base1p5 {
		compatible = "regulator-fixed";
		vin-supply = <&reg_base3p3>;
		regulator-name = "1V5-avari";
		regulator-min-microvolt = <1500000>;
		regulator-max-microvolt = <1500000>;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_usb_otg: regulator-otgvbus {
		compatible = "regulator-fixed";
		vin-supply = <&reg_wall_5p0>;
		regulator-name = "OTG_VBUS";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
		regulator-always-on;
	};

	clk_codec: clock-codec {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <12000000>;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "SGTL5000-Card";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&codec_dai>;
		simple-audio-card,frame-master = <&codec_dai>;
		simple-audio-card,widgets = "Headphone", "Headphone Jack";
		simple-audio-card,routing = "Headphone Jack", "HP_OUT";

		cpu_dai: simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};

		codec_dai: simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
		};
	};
};

&ecspi1 {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	status = "okay";

	sgtl5000: audio-codec@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		#sound-dai-cells = <0>;
		clocks = <&clk_codec>;
		VDDA-supply = <&reg_base3p3>;
		VDDIO-supply = <&reg_base3p3>;
	};

	boardID: gpio@3a {
		compatible = "nxp,pca8574";
		reg = <0x3a>;
		gpio-controller;
		#gpio-cells = <1>;
	};
};

&sai2 {
	status = "okay";
};

&uart2 {
	uart-has-rtscts;
	status = "okay";
};

&uart3 {
	status = "okay";
};

&uart4 {
	status = "okay";
};

&usbotg1 {
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	status = "disabled";
};

&usdhc2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0 or MIT)
//
// Copyright 2018 NXP
// Copyright (C) 2021 emtrion GmbH
//

/dts-v1/;

#include "imx8mm.dtsi"

/ {
	chosen {
		stdout-path = &uart1;
	};

	som_leds: leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_led>;

		green {
			label = "som:green";
			gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};

		red {
			label = "som:red";
			gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	lvds_backlight: lvds-backlight {
		compatible = "pwm-backlight";
		enable-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
		pwms = <&pwm1 0 50000 0>;
		brightness-levels = <
			0 4 8 16 32 64 80 96 112
			128 144 160 176 250
		>;
		default-brightness-level = <9>;
		status = "disabled";
	};

	reg_usdhc1_vmmc: regulator-emmc {
		compatible = "regulator-fixed";
		regulator-name = "eMMC";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		regulator-name = "sdcard_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
				<&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
		};
	};
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	pinctrl-1 = <&pinctrl_flexspi1>;
	status = "okay";

	flash0: flash@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <40000000>;
	};
};

&iomuxc {
	pinctrl-names = "default";

	pinctrl_csi_pwn: csi-pwn-grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
		>;
	};

	pinctrl_ecspi1: ecspi1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x82
			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x82
			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x82
		>;
	};

	pinctrl_ecspi1_cs: ecspi1-cs {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x40000
			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x40000
		>;
	};

	pinctrl_fec1: fec1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC				0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO			0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9			0x19
		>;
	};

	pinctrl_flexspi0: flexspi0-grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x1c2
			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
			MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS		0x82
		>;
	};

	pinctrl_flexspi1: flexspi1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK		0x1c2
			MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B	0x82
			MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0	0x82
			MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1	0x82
			MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2	0x82
			MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3	0x82
		>;
	};

	pinctrl_gpio_led: gpio-led-grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10		0x19
			MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x19
		>;
	};

	pinctrl_i2c1: i2c1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3-grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
		>;
	};

	pinctrl_lvds: lvds-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x06
		>;
	};

	pinctrl_pcie0: pcie0-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20		0x41
			MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x41
		>;
	};

	pinctrl_pmic: pmic-irq {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x41
		>;
	};

	pinctrl_pwm1: pwm1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT		0x06
		>;
	};

	pinctrl_sai2: sai2-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK		0xd6
			MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK		0xd6
			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6
			MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC		0xd6
			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6
			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6
		>;
	};

	pinctrl_spdif1: spdif1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT		0xd6
			MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN			0xd6
		>;
	};

	pinctrl_uart1: uart1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX		0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX		0x140
		>;
	};

	pinctrl_uart2: uart2-grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x140

			/* rts and cts */
			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x140
			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140
		>;
	};

	pinctrl_uart3: uart3-grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x140
			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x140
		>;
	};

	pinctrl_uart4: uart4-grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x140
			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x140
		>;
	};

	pinctrl_usdhc1: usdhc1-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x190
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d0
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0
			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d0
			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d0
			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d0
			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d0
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x194
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d4
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4
			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d4
			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d4
			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d4
			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d4
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x196
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d6
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6
			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d6
			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d6
			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d6
			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d6
		>;
	};

	pinctrl_usdhc1_gpio: usdhc1-gpio-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x41
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x1c4
		>;
	};

	pinctrl_usdhc2: usdhc2-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK			0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD			0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	/* no reset for sdhc2 interface */
	pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x1c4
			MX8MM_IOMUXC_SD2_WP_USDHC2_WP			0x1c4
		>;
	};

	pinctrl_wdog: wdog-grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
		>;
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	bd71847: pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio3>;
		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
		rohm,reset-snvs-powered;

		regulators {
			buck1_reg: BUCK1 {
				regulator-name = "BUCK1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			buck2_reg: BUCK2 {
				regulator-name = "BUCK2";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <900000>;
			};

			buck3_reg: BUCK3 {
				// BUCK5 in datasheet
				regulator-name = "BUCK3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck4_reg: BUCK4 {
				// BUCK6 in datasheet
				regulator-name = "BUCK4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5_reg: BUCK5 {
				// BUCK7 in datasheet
				regulator-name = "BUCK5";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6_reg: BUCK6 {
				// BUCK8 in datasheet
				regulator-name = "BUCK6";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: LDO1 {
				regulator-name = "LDO1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <1900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2_reg: LDO2 {
				regulator-name = "LDO2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_reg: LDO3 {
				regulator-name = "LDO3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4_reg: LDO4 {
				regulator-name = "LDO4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo6_reg: LDO6 {
				regulator-name = "LDO6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};

	rv1805: rtc@69 {
		compatible = "abracon,ab1805";
		reg = <0x69>;
	};
};

&mu {
	status = "okay";
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
};

&sai2 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <12000000>;
	status = "disabled";
};

&spdif1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif1>;
	assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
		<&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
		<&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
		<&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
	clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
		"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
	status = "disabled";
};

&uart1 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	assigned-clocks = <&clk IMX8MM_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clk IMX8MM_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	assigned-clocks = <&clk IMX8MM_CLK_UART4>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	over-current-active-low;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "disabled";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
	bus-width = <8>;
	vmmc-supply = <&reg_usdhc1_vmmc>;
	keep-power-in-suspend;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	no-1-8-v;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019-2020 NXP
 */

/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include "imx8mm-evk.dtsi"

/ {
	model = "FSL i.MX8MM EVK board";
	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";

	aliases {
		spi0 = &flexspi;
	};
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi>;
	status = "okay";

	flash@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <80000000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
	};
};

&usdhc3 {
	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&iomuxc {
	pinctrl_flexspi: flexspigrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
		>;
	};
};