code:
// SPDX-License-Identifier: GPL-2.0
/*
 * pinctrl dts fils for Hislicon HiKey development board
 *
 */
#include <dt-bindings/pinctrl/hisi.h>

/ {
	soc {
		pmx0: pinmux@f7010000 {
			pinctrl-names = "default";
			pinctrl-0 = <
				&boot_sel_pmx_func
				&hkadc_ssi_pmx_func
				&codec_clk_pmx_func
				&pwm_in_pmx_func
				&bl_pwm_pmx_func
				>;

			boot_sel_pmx_func: boot_sel_pmx_func {
				pinctrl-single,pins = <
					0x0    MUX_M0	/* BOOT_SEL     (IOMG000) */
				>;
			};

			emmc_pmx_func: emmc_pmx_func {
				pinctrl-single,pins = <
					0x100  MUX_M0	/* EMMC_CLK     (IOMG064) */
					0x104  MUX_M0	/* EMMC_CMD     (IOMG065) */
					0x108  MUX_M0	/* EMMC_DATA0   (IOMG066) */
					0x10c  MUX_M0	/* EMMC_DATA1   (IOMG067) */
					0x110  MUX_M0	/* EMMC_DATA2   (IOMG068) */
					0x114  MUX_M0	/* EMMC_DATA3   (IOMG069) */
					0x118  MUX_M0	/* EMMC_DATA4   (IOMG070) */
					0x11c  MUX_M0	/* EMMC_DATA5   (IOMG071) */
					0x120  MUX_M0	/* EMMC_DATA6   (IOMG072) */
					0x124  MUX_M0	/* EMMC_DATA7   (IOMG073) */
				>;
			};

			sd_pmx_func: sd_pmx_func {
				pinctrl-single,pins = <
					0xc    MUX_M0	/* SD_CLK       (IOMG003) */
					0x10   MUX_M0	/* SD_CMD       (IOMG004) */
					0x14   MUX_M0	/* SD_DATA0     (IOMG005) */
					0x18   MUX_M0	/* SD_DATA1     (IOMG006) */
					0x1c   MUX_M0	/* SD_DATA2     (IOMG007) */
					0x20   MUX_M0	/* SD_DATA3     (IOMG008) */
				>;
			};
			sd_pmx_idle: sd_pmx_idle {
				pinctrl-single,pins = <
					0xc    MUX_M1	/* SD_CLK       (IOMG003) */
					0x10   MUX_M1	/* SD_CMD       (IOMG004) */
					0x14   MUX_M1	/* SD_DATA0     (IOMG005) */
					0x18   MUX_M1	/* SD_DATA1     (IOMG006) */
					0x1c   MUX_M1	/* SD_DATA2     (IOMG007) */
					0x20   MUX_M1	/* SD_DATA3     (IOMG008) */
				>;
			};

			sdio_pmx_func: sdio_pmx_func {
				pinctrl-single,pins = <
					0x128  MUX_M0	/* SDIO_CLK     (IOMG074) */
					0x12c  MUX_M0	/* SDIO_CMD     (IOMG075) */
					0x130  MUX_M0	/* SDIO_DATA0   (IOMG076) */
					0x134  MUX_M0	/* SDIO_DATA1   (IOMG077) */
					0x138  MUX_M0	/* SDIO_DATA2   (IOMG078) */
					0x13c  MUX_M0	/* SDIO_DATA3   (IOMG079) */
				>;
			};
			sdio_pmx_idle: sdio_pmx_idle {
				pinctrl-single,pins = <
					0x128  MUX_M1	/* SDIO_CLK     (IOMG074) */
					0x12c  MUX_M1	/* SDIO_CMD     (IOMG075) */
					0x130  MUX_M1	/* SDIO_DATA0   (IOMG076) */
					0x134  MUX_M1	/* SDIO_DATA1   (IOMG077) */
					0x138  MUX_M1	/* SDIO_DATA2   (IOMG078) */
					0x13c  MUX_M1	/* SDIO_DATA3   (IOMG079) */
				>;
			};

			isp_pmx_func: isp_pmx_func {
				pinctrl-single,pins = <
					0x24   MUX_M0	/* ISP_PWDN0    (IOMG009) */
					0x28   MUX_M0	/* ISP_PWDN1    (IOMG010) */
					0x2c   MUX_M0	/* ISP_PWDN2    (IOMG011) */
					0x30   MUX_M1	/* ISP_SHUTTER0 (IOMG012) */
					0x34   MUX_M1	/* ISP_SHUTTER1 (IOMG013) */
					0x38   MUX_M1	/* ISP_PWM      (IOMG014) */
					0x3c   MUX_M0	/* ISP_CCLK0    (IOMG015) */
					0x40   MUX_M0	/* ISP_CCLK1    (IOMG016) */
					0x44   MUX_M0	/* ISP_RESETB0  (IOMG017) */
					0x48   MUX_M0	/* ISP_RESETB1  (IOMG018) */
					0x4c   MUX_M1	/* ISP_STROBE0  (IOMG019) */
					0x50   MUX_M1	/* ISP_STROBE1  (IOMG020) */
					0x54   MUX_M0	/* ISP_SDA0     (IOMG021) */
					0x58   MUX_M0	/* ISP_SCL0     (IOMG022) */
					0x5c   MUX_M0	/* ISP_SDA1     (IOMG023) */
					0x60   MUX_M0	/* ISP_SCL1     (IOMG024) */
				>;
			};

			hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {
				pinctrl-single,pins = <
					0x68   MUX_M0	/* HKADC_SSI    (IOMG026) */
				>;
			};

			codec_clk_pmx_func: codec_clk_pmx_func {
				pinctrl-single,pins = <
					0x6c   MUX_M0	/* CODEC_CLK    (IOMG027) */
				>;
			};

			codec_pmx_func: codec_pmx_func {
				pinctrl-single,pins = <
					0x70   MUX_M1	/* DMIC_CLK     (IOMG028) */
					0x74   MUX_M0	/* CODEC_SYNC   (IOMG029) */
					0x78   MUX_M0	/* CODEC_DI     (IOMG030) */
					0x7c   MUX_M0	/* CODEC_DO     (IOMG031) */
				>;
			};

			fm_pmx_func: fm_pmx_func {
				pinctrl-single,pins = <
					0x80   MUX_M1	/* FM_XCLK      (IOMG032) */
					0x84   MUX_M1	/* FM_XFS       (IOMG033) */
					0x88   MUX_M1	/* FM_DI        (IOMG034) */
					0x8c   MUX_M1	/* FM_DO        (IOMG035) */
				>;
			};

			bt_pmx_func: bt_pmx_func {
				pinctrl-single,pins = <
					0x90   MUX_M0	/* BT_XCLK      (IOMG036) */
					0x94   MUX_M0	/* BT_XFS       (IOMG037) */
					0x98   MUX_M0	/* BT_DI        (IOMG038) */
					0x9c   MUX_M0	/* BT_DO        (IOMG039) */
				>;
			};

			pwm_in_pmx_func: pwm_in_pmx_func {
				pinctrl-single,pins = <
					0xb8   MUX_M1	/* PWM_IN       (IOMG046) */
				>;
			};

			bl_pwm_pmx_func: bl_pwm_pmx_func {
				pinctrl-single,pins = <
					0xbc   MUX_M1	/* BL_PWM       (IOMG047) */
				>;
			};

			uart0_pmx_func: uart0_pmx_func {
				pinctrl-single,pins = <
					0xc0   MUX_M0	/* UART0_RXD    (IOMG048) */
					0xc4   MUX_M0	/* UART0_TXD    (IOMG049) */
				>;
			};

			uart1_pmx_func: uart1_pmx_func {
				pinctrl-single,pins = <
					0xc8   MUX_M0	/* UART1_CTS_N  (IOMG050) */
					0xcc   MUX_M0	/* UART1_RTS_N  (IOMG051) */
					0xd0   MUX_M0	/* UART1_RXD    (IOMG052) */
					0xd4   MUX_M0	/* UART1_TXD    (IOMG053) */
				>;
			};

			uart2_pmx_func: uart2_pmx_func {
				pinctrl-single,pins = <
					0xd8   MUX_M0	/* UART2_CTS_N  (IOMG054) */
					0xdc   MUX_M0	/* UART2_RTS_N  (IOMG055) */
					0xe0   MUX_M0	/* UART2_RXD    (IOMG056) */
					0xe4   MUX_M0	/* UART2_TXD    (IOMG057) */
				>;
			};

			uart3_pmx_func: uart3_pmx_func {
				pinctrl-single,pins = <
					0x180  MUX_M1	/* UART3_CTS_N  (IOMG096) */
					0x184  MUX_M1	/* UART3_RTS_N  (IOMG097) */
					0x188  MUX_M1	/* UART3_RXD    (IOMG098) */
					0x18c  MUX_M1	/* UART3_TXD    (IOMG099) */
				>;
			};

			uart4_pmx_func: uart4_pmx_func {
				pinctrl-single,pins = <
					0x1d0  MUX_M1	/* UART4_CTS_N  (IOMG116) */
					0x1d4  MUX_M1	/* UART4_RTS_N  (IOMG117) */
					0x1d8  MUX_M1	/* UART4_RXD    (IOMG118) */
					0x1dc  MUX_M1	/* UART4_TXD    (IOMG119) */
				>;
			};

			uart5_pmx_func: uart5_pmx_func {
				pinctrl-single,pins = <
					0x1c8  MUX_M1	/* UART5_RXD    (IOMG114) */
					0x1cc  MUX_M1	/* UART5_TXD    (IOMG115) */
				>;
			};

			i2c0_pmx_func: i2c0_pmx_func {
				pinctrl-single,pins = <
					0xe8   MUX_M0	/* I2C0_SCL     (IOMG058) */
					0xec   MUX_M0	/* I2C0_SDA     (IOMG059) */
				>;
			};

			i2c1_pmx_func: i2c1_pmx_func {
				pinctrl-single,pins = <
					0xf0   MUX_M0	/* I2C1_SCL     (IOMG060) */
					0xf4   MUX_M0	/* I2C1_SDA     (IOMG061) */
				>;
			};

			i2c2_pmx_func: i2c2_pmx_func {
				pinctrl-single,pins = <
					0xf8   MUX_M0	/* I2C2_SCL     (IOMG062) */
					0xfc   MUX_M0	/* I2C2_SDA     (IOMG063) */
				>;
			};

			spi0_pmx_func: spi0_pmx_func {
				pinctrl-single,pins = <
					0x1a0  MUX_M1   /* SPI0_DI      (IOMG104) */
					0x1a4  MUX_M1	/* SPI0_DO	(IOMG105) */
					0x1a8  MUX_M1	/* SPI0_CS_N	(IOMG106) */
					0x1ac  MUX_M1	/* SPI0_CLK	(IOMG107) */
				>;
			};
		};

		pmx1: pinmux@f7010800 {

			pinctrl-names = "default";
			pinctrl-0 = <
				&boot_sel_cfg_func
				&hkadc_ssi_cfg_func
				&codec_clk_cfg_func
				&pwm_in_cfg_func
				&bl_pwm_cfg_func
				>;

			boot_sel_cfg_func: boot_sel_cfg_func {
				pinctrl-single,pins = <
					0x0    0x0	/* BOOT_SEL     (IOCFG000) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {
				pinctrl-single,pins = <
					0x6c   0x0	/* HKADC_SSI    (IOCFG027) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			emmc_clk_cfg_func: emmc_clk_cfg_func {
				pinctrl-single,pins = <
					0x104  0x0	/* EMMC_CLK     (IOCFG065) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
			};

			emmc_cfg_func: emmc_cfg_func {
				pinctrl-single,pins = <
					0x108  0x0	/* EMMC_CMD     (IOCFG066) */
					0x10c  0x0	/* EMMC_DATA0   (IOCFG067) */
					0x110  0x0	/* EMMC_DATA1   (IOCFG068) */
					0x114  0x0	/* EMMC_DATA2   (IOCFG069) */
					0x118  0x0	/* EMMC_DATA3   (IOCFG070) */
					0x11c  0x0	/* EMMC_DATA4   (IOCFG071) */
					0x120  0x0	/* EMMC_DATA5   (IOCFG072) */
					0x124  0x0	/* EMMC_DATA6   (IOCFG073) */
					0x128  0x0	/* EMMC_DATA7   (IOCFG074) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
			};

			emmc_rst_cfg_func: emmc_rst_cfg_func {
				pinctrl-single,pins = <
					0x12c  0x0	/* EMMC_RST_N   (IOCFG075) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
			};

			sd_clk_cfg_func: sd_clk_cfg_func {
				pinctrl-single,pins = <
					0xc    0x0	/* SD_CLK       (IOCFG003) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>;
			};
			sd_clk_cfg_idle: sd_clk_cfg_idle {
				pinctrl-single,pins = <
					0xc    0x0	/* SD_CLK       (IOCFG003) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			sd_cfg_func: sd_cfg_func {
				pinctrl-single,pins = <
					0x10   0x0	/* SD_CMD       (IOCFG004) */
					0x14   0x0	/* SD_DATA0     (IOCFG005) */
					0x18   0x0	/* SD_DATA1     (IOCFG006) */
					0x1c   0x0	/* SD_DATA2     (IOCFG007) */
					0x20   0x0	/* SD_DATA3     (IOCFG008) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
			};
			sd_cfg_idle: sd_cfg_idle {
				pinctrl-single,pins = <
					0x10   0x0	/* SD_CMD       (IOCFG004) */
					0x14   0x0	/* SD_DATA0     (IOCFG005) */
					0x18   0x0	/* SD_DATA1     (IOCFG006) */
					0x1c   0x0	/* SD_DATA2     (IOCFG007) */
					0x20   0x0	/* SD_DATA3     (IOCFG008) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			sdio_clk_cfg_func: sdio_clk_cfg_func {
				pinctrl-single,pins = <
					0x134  0x0	/* SDIO_CLK     (IOCFG077) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
			};
			sdio_clk_cfg_idle: sdio_clk_cfg_idle {
				pinctrl-single,pins = <
					0x134  0x0	/* SDIO_CLK     (IOCFG077) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			sdio_cfg_func: sdio_cfg_func {
				pinctrl-single,pins = <
					0x138  0x0	/* SDIO_CMD     (IOCFG078) */
					0x13c  0x0	/* SDIO_DATA0   (IOCFG079) */
					0x140  0x0	/* SDIO_DATA1   (IOCFG080) */
					0x144  0x0	/* SDIO_DATA2   (IOCFG081) */
					0x148  0x0	/* SDIO_DATA3   (IOCFG082) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
			};
			sdio_cfg_idle: sdio_cfg_idle {
				pinctrl-single,pins = <
					0x138  0x0	/* SDIO_CMD     (IOCFG078) */
					0x13c  0x0	/* SDIO_DATA0   (IOCFG079) */
					0x140  0x0	/* SDIO_DATA1   (IOCFG080) */
					0x144  0x0	/* SDIO_DATA2   (IOCFG081) */
					0x148  0x0	/* SDIO_DATA3   (IOCFG082) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			isp_cfg_func1: isp_cfg_func1 {
				pinctrl-single,pins = <
					0x28   0x0	/* ISP_PWDN0    (IOCFG010) */
					0x2c   0x0	/* ISP_PWDN1    (IOCFG011) */
					0x30   0x0	/* ISP_PWDN2    (IOCFG012) */
					0x34   0x0	/* ISP_SHUTTER0 (IOCFG013) */
					0x38   0x0	/* ISP_SHUTTER1 (IOCFG014) */
					0x3c   0x0	/* ISP_PWM      (IOCFG015) */
					0x40   0x0	/* ISP_CCLK0    (IOCFG016) */
					0x44   0x0	/* ISP_CCLK1    (IOCFG017) */
					0x48   0x0	/* ISP_RESETB0  (IOCFG018) */
					0x4c   0x0	/* ISP_RESETB1  (IOCFG019) */
					0x50   0x0	/* ISP_STROBE0  (IOCFG020) */
					0x58   0x0	/* ISP_SDA0     (IOCFG022) */
					0x5c   0x0	/* ISP_SCL0     (IOCFG023) */
					0x60   0x0	/* ISP_SDA1     (IOCFG024) */
					0x64   0x0	/* ISP_SCL1     (IOCFG025) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};
			isp_cfg_idle1: isp_cfg_idle1 {
				pinctrl-single,pins = <
					0x34   0x0	/* ISP_SHUTTER0 (IOCFG013) */
					0x38   0x0	/* ISP_SHUTTER1 (IOCFG014) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			isp_cfg_func2: isp_cfg_func2 {
				pinctrl-single,pins = <
					0x54   0x0	/* ISP_STROBE1  (IOCFG021) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			codec_clk_cfg_func: codec_clk_cfg_func {
				pinctrl-single,pins = <
					0x70   0x0	/* CODEC_CLK    (IOCFG028) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
			};
			codec_clk_cfg_idle: codec_clk_cfg_idle {
				pinctrl-single,pins = <
					0x70   0x0	/* CODEC_CLK    (IOCFG028) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			codec_cfg_func1: codec_cfg_func1 {
				pinctrl-single,pins = <
					0x74   0x0	/* DMIC_CLK     (IOCFG029) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			codec_cfg_func2: codec_cfg_func2 {
				pinctrl-single,pins = <
					0x78   0x0	/* CODEC_SYNC   (IOCFG030) */
					0x7c   0x0	/* CODEC_DI     (IOCFG031) */
					0x80   0x0	/* CODEC_DO     (IOCFG032) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
			};
			codec_cfg_idle2: codec_cfg_idle2 {
				pinctrl-single,pins = <
					0x78   0x0	/* CODEC_SYNC   (IOCFG030) */
					0x7c   0x0	/* CODEC_DI     (IOCFG031) */
					0x80   0x0	/* CODEC_DO     (IOCFG032) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			fm_cfg_func: fm_cfg_func {
				pinctrl-single,pins = <
					0x84   0x0	/* FM_XCLK      (IOCFG033) */
					0x88   0x0	/* FM_XFS       (IOCFG034) */
					0x8c   0x0	/* FM_DI        (IOCFG035) */
					0x90   0x0	/* FM_DO        (IOCFG036) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			bt_cfg_func: bt_cfg_func {
				pinctrl-single,pins = <
					0x94   0x0	/* BT_XCLK      (IOCFG037) */
					0x98   0x0	/* BT_XFS       (IOCFG038) */
					0x9c   0x0	/* BT_DI        (IOCFG039) */
					0xa0   0x0	/* BT_DO        (IOCFG040) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};
			bt_cfg_idle: bt_cfg_idle {
				pinctrl-single,pins = <
					0x94   0x0	/* BT_XCLK      (IOCFG037) */
					0x98   0x0	/* BT_XFS       (IOCFG038) */
					0x9c   0x0	/* BT_DI        (IOCFG039) */
					0xa0   0x0	/* BT_DO        (IOCFG040) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			pwm_in_cfg_func: pwm_in_cfg_func {
				pinctrl-single,pins = <
					0xbc   0x0	/* PWM_IN       (IOCFG047) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			bl_pwm_cfg_func: bl_pwm_cfg_func {
				pinctrl-single,pins = <
					0xc0   0x0	/* BL_PWM       (IOCFG048) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			uart0_cfg_func1: uart0_cfg_func1 {
				pinctrl-single,pins = <
					0xc4   0x0	/* UART0_RXD    (IOCFG049) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			uart0_cfg_func2: uart0_cfg_func2 {
				pinctrl-single,pins = <
					0xc8   0x0	/* UART0_TXD    (IOCFG050) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
			};

			uart1_cfg_func1: uart1_cfg_func1 {
				pinctrl-single,pins = <
					0xcc   0x0	/* UART1_CTS_N  (IOCFG051) */
					0xd4   0x0	/* UART1_RXD    (IOCFG053) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			uart1_cfg_func2: uart1_cfg_func2 {
				pinctrl-single,pins = <
					0xd0   0x0	/* UART1_RTS_N  (IOCFG052) */
					0xd8   0x0	/* UART1_TXD    (IOCFG054) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			uart2_cfg_func: uart2_cfg_func {
				pinctrl-single,pins = <
					0xdc   0x0	/* UART2_CTS_N  (IOCFG055) */
					0xe0   0x0	/* UART2_RTS_N  (IOCFG056) */
					0xe4   0x0	/* UART2_RXD    (IOCFG057) */
					0xe8   0x0	/* UART2_TXD    (IOCFG058) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			uart3_cfg_func: uart3_cfg_func {
				pinctrl-single,pins = <
					0x190  0x0	/* UART3_CTS_N  (IOCFG100) */
					0x194  0x0	/* UART3_RTS_N  (IOCFG101) */
					0x198  0x0	/* UART3_RXD    (IOCFG102) */
					0x19c  0x0	/* UART3_TXD    (IOCFG103) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			uart4_cfg_func: uart4_cfg_func {
				pinctrl-single,pins = <
					0x1e0  0x0	/* UART4_CTS_N  (IOCFG120) */
					0x1e4  0x0	/* UART4_RTS_N  (IOCFG121) */
					0x1e8  0x0	/* UART4_RXD    (IOCFG122) */
					0x1ec  0x0	/* UART4_TXD    (IOCFG123) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			uart5_cfg_func: uart5_cfg_func {
				pinctrl-single,pins = <
					0x1d8  0x0	/* UART4_RXD    (IOCFG118) */
					0x1dc  0x0	/* UART4_TXD    (IOCFG119) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			i2c0_cfg_func: i2c0_cfg_func {
				pinctrl-single,pins = <
					0xec   0x0	/* I2C0_SCL     (IOCFG059) */
					0xf0   0x0	/* I2C0_SDA     (IOCFG060) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			i2c1_cfg_func: i2c1_cfg_func {
				pinctrl-single,pins = <
					0xf4   0x0	/* I2C1_SCL     (IOCFG061) */
					0xf8   0x0	/* I2C1_SDA     (IOCFG062) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			i2c2_cfg_func: i2c2_cfg_func {
				pinctrl-single,pins = <
					0xfc   0x0	/* I2C2_SCL     (IOCFG063) */
					0x100  0x0	/* I2C2_SDA     (IOCFG064) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			spi0_cfg_func: spi0_cfg_func {
				pinctrl-single,pins = <
					0x1b0  0x0	/* SPI0_DI	(IOCFG108) */
					0x1b4  0x0	/* SPI0_DO	(IOCFG109) */
					0x1b8  0x0	/* SPI0_CS_N	(IOCFG110) */
					0x1bc  0x0	/* SPI0_CLK	(IOCFG111) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};
		};

		pmx2: pinmux@f8001800 {

			pinctrl-names = "default";
			pinctrl-0 = <
				&rstout_n_cfg_func
				>;

			rstout_n_cfg_func: rstout_n_cfg_func {
				pinctrl-single,pins = <
					0x0    0x0	/* RSTOUT_N     (IOCFG000) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {
				pinctrl-single,pins = <
					0x4    0x0	/* PMU_PERI_EN  (IOCFG001) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			sysclk0_en_cfg_func: sysclk0_en_cfg_func {
				pinctrl-single,pins = <
					0x8    0x0	/* SYSCLK0_EN   (IOCFG002) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};

			jtag_tdo_cfg_func: jtag_tdo_cfg_func {
				pinctrl-single,pins = <
					0xc    0x0	/* JTAG_TDO     (IOCFG003) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
			};

			rf_reset_cfg_func: rf_reset_cfg_func {
				pinctrl-single,pins = <
					0x70   0x0	/* RF_RESET0    (IOCFG028) */
					0x74   0x0	/* RF_RESET1    (IOCFG029) */
				>;
				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * pinctrl dts fils for Hislicon HiKey960 development board
 *
 */

#include <dt-bindings/pinctrl/hisi.h>

/ {
	soc {
		/* [IOMG_000, IOMG_123] */
		range: gpio-range {
			#pinctrl-single,gpio-range-cells = <3>;
		};

		pmx0: pinmux@e896c000 {
			compatible = "pinctrl-single";
			reg = <0x0 0xe896c000 0x0 0x1f0>;
			#pinctrl-cells = <1>;
			#gpio-range-cells = <0x3>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x7>;
			/* pin base, nr pins & gpio function */
			pinctrl-single,gpio-range = <
				&range 0 7 0
				&range 8 116 0>;

			pmu_pmx_func: pmu_pmx_func {
				pinctrl-single,pins = <
					0x008 MUX_M1 /* PMU1_SSI */
					0x00c MUX_M1 /* PMU2_SSI */
					0x010 MUX_M1 /* PMU_CLKOUT */
					0x100 MUX_M1 /* PMU_HKADC_SSI */
				>;
			};

			csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func {
				pinctrl-single,pins = <
					0x044 MUX_M0 /* CSI0_PWD_N */
				>;
			};

			csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func {
				pinctrl-single,pins = <
					0x04c MUX_M0 /* CSI1_PWD_N */
				>;
			};

			isp0_pmx_func: isp0_pmx_func {
				pinctrl-single,pins = <
					0x058 MUX_M1 /* ISP_CLK0 */
					0x064 MUX_M1 /* ISP_SCL0 */
					0x068 MUX_M1 /* ISP_SDA0 */
				>;
			};

			isp1_pmx_func: isp1_pmx_func {
				pinctrl-single,pins = <
					0x05c MUX_M1 /* ISP_CLK1 */
					0x06c MUX_M1 /* ISP_SCL1 */
					0x070 MUX_M1 /* ISP_SDA1 */
				>;
			};

			pwr_key_pmx_func: pwr_key_pmx_func {
				pinctrl-single,pins = <
					0x080 MUX_M0 /* GPIO_034 */
				>;
			};

			i2c3_pmx_func: i2c3_pmx_func {
				pinctrl-single,pins = <
					0x02c MUX_M1 /* I2C3_SCL */
					0x030 MUX_M1 /* I2C3_SDA */
				>;
			};

			i2c4_pmx_func: i2c4_pmx_func {
				pinctrl-single,pins = <
					0x090 MUX_M1 /* I2C4_SCL */
					0x094 MUX_M1 /* I2C4_SDA */
				>;
			};

			pcie_perstn_pmx_func: pcie_perstn_pmx_func {
				pinctrl-single,pins = <
					0x15c MUX_M1 /* PCIE_PERST_N */
				>;
			};

			usbhub5734_pmx_func: usbhub5734_pmx_func {
				pinctrl-single,pins = <
					0x11c MUX_M0 /* GPIO_073 */
					0x120 MUX_M0 /* GPIO_074 */
				>;
			};

			uart0_pmx_func: uart0_pmx_func {
				pinctrl-single,pins = <
					0x0cc MUX_M2 /* UART0_RXD */
					0x0d0 MUX_M2 /* UART0_TXD */
				>;
			};

			uart1_pmx_func: uart1_pmx_func {
				pinctrl-single,pins = <
					0x0b0 MUX_M2 /* UART1_CTS_N */
					0x0b4 MUX_M2 /* UART1_RTS_N */
					0x0a8 MUX_M2 /* UART1_RXD */
					0x0ac MUX_M2 /* UART1_TXD */
				>;
			};

			uart2_pmx_func: uart2_pmx_func {
				pinctrl-single,pins = <
					0x0bc MUX_M2 /* UART2_CTS_N */
					0x0c0 MUX_M2 /* UART2_RTS_N */
					0x0c8 MUX_M2 /* UART2_RXD */
					0x0c4 MUX_M2 /* UART2_TXD */
				>;
			};

			uart3_pmx_func: uart3_pmx_func {
				pinctrl-single,pins = <
					0x0dc MUX_M1 /* UART3_CTS_N */
					0x0e0 MUX_M1 /* UART3_RTS_N */
					0x0e4 MUX_M1 /* UART3_RXD */
					0x0e8 MUX_M1 /* UART3_TXD */
				>;
			};

			uart4_pmx_func: uart4_pmx_func {
				pinctrl-single,pins = <
					0x0ec MUX_M1 /* UART4_CTS_N */
					0x0f0 MUX_M1 /* UART4_RTS_N */
					0x0f4 MUX_M1 /* UART4_RXD */
					0x0f8 MUX_M1 /* UART4_TXD */
				>;
			};

			uart5_pmx_func: uart5_pmx_func {
				pinctrl-single,pins = <
					0x0c4 MUX_M3 /* UART5_CTS_N */
					0x0c8 MUX_M3 /* UART5_RTS_N */
					0x0bc MUX_M3 /* UART5_RXD */
					0x0c0 MUX_M3 /* UART5_TXD */
				>;
			};

			uart6_pmx_func: uart6_pmx_func {
				pinctrl-single,pins = <
					0x0cc MUX_M1 /* UART6_CTS_N */
					0x0d0 MUX_M1 /* UART6_RTS_N */
					0x0d4 MUX_M1 /* UART6_RXD */
					0x0d8 MUX_M1 /* UART6_TXD */
				>;
			};

			cam0_rst_pmx_func: cam0_rst_pmx_func {
				pinctrl-single,pins = <
					0x0c8 MUX_M0 /* CAM0_RST */
				>;
			};

			cam1_rst_pmx_func: cam1_rst_pmx_func {
				pinctrl-single,pins = <
					0x124 MUX_M0 /* CAM1_RST */
				>;
			};
		};

		/* [IOMG_MMC0_000, IOMG_MMC0_005] */
		pmx1: pinmux@ff37e000 {
			compatible = "pinctrl-single";
			reg = <0x0 0xff37e000 0x0 0x18>;
			#gpio-range-cells = <0x3>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x7>;
			/* pin base, nr pins & gpio function */
			pinctrl-single,gpio-range = <&range 0 6 0>;

			sd_pmx_func: sd_pmx_func {
				pinctrl-single,pins = <
					0x000 MUX_M1 /* SD_CLK */
					0x004 MUX_M1 /* SD_CMD */
					0x008 MUX_M1 /* SD_DATA0 */
					0x00c MUX_M1 /* SD_DATA1 */
					0x010 MUX_M1 /* SD_DATA2 */
					0x014 MUX_M1 /* SD_DATA3 */
				>;
			};
		};

		/* [IOMG_FIX_000, IOMG_FIX_011] */
		pmx2: pinmux@ff3b6000 {
			compatible = "pinctrl-single";
			reg = <0x0 0xff3b6000 0x0 0x30>;
			#pinctrl-cells = <1>;
			#gpio-range-cells = <0x3>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x7>;
			/* pin base, nr pins & gpio function */
			pinctrl-single,gpio-range = <&range 0 12 0>;

			ufs_pmx_func: ufs_pmx_func {
				pinctrl-single,pins = <
					0x000 MUX_M1 /* UFS_REF_CLK */
					0x004 MUX_M1 /* UFS_RST_N */
				>;
			};

			spi3_pmx_func: spi3_pmx_func {
				pinctrl-single,pins = <
					0x008 MUX_M1 /* SPI3_CLK */
					0x00c MUX_M1 /* SPI3_DI */
					0x010 MUX_M1 /* SPI3_DO */
					0x014 MUX_M1 /* SPI3_CS0_N */
				>;
			};
		};

		/* [IOMG_MMC1_000, IOMG_MMC1_005] */
		pmx3: pinmux@ff3fd000 {
			compatible = "pinctrl-single";
			reg = <0x0 0xff3fd000 0x0 0x18>;
			#pinctrl-cells = <1>;
			#gpio-range-cells = <0x3>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x7>;
			/* pin base, nr pins & gpio function */
			pinctrl-single,gpio-range = <&range 0 6 0>;

			sdio_pmx_func: sdio_pmx_func {
				pinctrl-single,pins = <
					0x000 MUX_M1 /* SDIO_CLK */
					0x004 MUX_M1 /* SDIO_CMD */
					0x008 MUX_M1 /* SDIO_DATA0 */
					0x00c MUX_M1 /* SDIO_DATA1 */
					0x010 MUX_M1 /* SDIO_DATA2 */
					0x014 MUX_M1 /* SDIO_DATA3 */
				>;
			};
		};

		/* [IOMG_AO_000, IOMG_AO_041] */
		pmx4: pinmux@fff11000 {
			compatible = "pinctrl-single";
			reg = <0x0 0xfff11000 0x0 0xa8>;
			#pinctrl-cells = <1>;
			#gpio-range-cells = <0x3>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x7>;
			/* pin base in node, nr pins & gpio function */
			pinctrl-single,gpio-range = <&range 0 42 0>;

			i2s2_pmx_func: i2s2_pmx_func {
				pinctrl-single,pins = <
					0x044 MUX_M1 /* I2S2_DI */
					0x048 MUX_M1 /* I2S2_DO */
					0x04c MUX_M1 /* I2S2_XCLK */
					0x050 MUX_M1 /* I2S2_XFS */
				>;
			};

			slimbus_pmx_func: slimbus_pmx_func {
				pinctrl-single,pins = <
					0x02c MUX_M1 /* SLIMBUS_CLK */
					0x030 MUX_M1 /* SLIMBUS_DATA */
				>;
			};

			i2c0_pmx_func: i2c0_pmx_func {
				pinctrl-single,pins = <
					0x014 MUX_M1 /* I2C0_SCL */
					0x018 MUX_M1 /* I2C0_SDA */
				>;
			};

			i2c1_pmx_func: i2c1_pmx_func {
				pinctrl-single,pins = <
					0x01c MUX_M1 /* I2C1_SCL */
					0x020 MUX_M1 /* I2C1_SDA */
				>;
			};

			i2c7_pmx_func: i2c7_pmx_func {
				pinctrl-single,pins = <
					0x024 MUX_M3 /* I2C7_SCL */
					0x028 MUX_M3 /* I2C7_SDA */
				>;
			};

			pcie_pmx_func: pcie_pmx_func {
				pinctrl-single,pins = <
					0x084 MUX_M1 /* PCIE_CLKREQ_N */
					0x088 MUX_M1 /* PCIE_WAKE_N */
				>;
			};

			spi2_pmx_func: spi2_pmx_func {
				pinctrl-single,pins = <
					0x08c MUX_M1 /* SPI2_CLK */
					0x090 MUX_M1 /* SPI2_DI */
					0x094 MUX_M1 /* SPI2_DO */
					0x098 MUX_M1 /* SPI2_CS0_N */
				>;
			};

			i2s0_pmx_func: i2s0_pmx_func {
				pinctrl-single,pins = <
					0x034 MUX_M1 /* I2S0_DI */
					0x038 MUX_M1 /* I2S0_DO */
					0x03c MUX_M1 /* I2S0_XCLK */
					0x040 MUX_M1 /* I2S0_XFS */
				>;
			};
		};

		pmx5: pinmux@e896c800 {
			compatible = "pinconf-single";
			reg = <0x0 0xe896c800 0x0 0x200>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;

			pmu_cfg_func: pmu_cfg_func {
				pinctrl-single,pins = <
					0x010 0x0 /* PMU1_SSI */
					0x014 0x0 /* PMU2_SSI */
					0x018 0x0 /* PMU_CLKOUT */
					0x10c 0x0 /* PMU_HKADC_SSI */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_06MA DRIVE6_MASK
				>;
			};

			i2c3_cfg_func: i2c3_cfg_func {
				pinctrl-single,pins = <
					0x038 0x0 /* I2C3_SCL */
					0x03c 0x0 /* I2C3_SDA */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func {
				pinctrl-single,pins = <
					0x050 0x0 /* CSI0_PWD_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func {
				pinctrl-single,pins = <
					0x058 0x0 /* CSI1_PWD_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			isp0_cfg_func: isp0_cfg_func {
				pinctrl-single,pins = <
					0x064 0x0 /* ISP_CLK0 */
					0x070 0x0 /* ISP_SCL0 */
					0x074 0x0 /* ISP_SDA0 */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK>;
			};

			isp1_cfg_func: isp1_cfg_func {
				pinctrl-single,pins = <
					0x068 0x0 /* ISP_CLK1 */
					0x078 0x0 /* ISP_SCL1 */
					0x07c 0x0 /* ISP_SDA1 */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			pwr_key_cfg_func: pwr_key_cfg_func {
				pinctrl-single,pins = <
					0x08c 0x0 /* GPIO_034 */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			uart1_cfg_func: uart1_cfg_func {
				pinctrl-single,pins = <
					0x0b4 0x0 /* UART1_RXD */
					0x0b8 0x0 /* UART1_TXD */
					0x0bc 0x0 /* UART1_CTS_N */
					0x0c0 0x0 /* UART1_RTS_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			uart2_cfg_func: uart2_cfg_func {
				pinctrl-single,pins = <
					0x0c8 0x0 /* UART2_CTS_N */
					0x0cc 0x0 /* UART2_RTS_N */
					0x0d0 0x0 /* UART2_TXD */
					0x0d4 0x0 /* UART2_RXD */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			uart5_cfg_func: uart5_cfg_func {
				pinctrl-single,pins = <
					0x0c8 0x0 /* UART5_RXD */
					0x0cc 0x0 /* UART5_TXD */
					0x0d0 0x0 /* UART5_CTS_N */
					0x0d4 0x0 /* UART5_RTS_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			cam0_rst_cfg_func: cam0_rst_cfg_func {
				pinctrl-single,pins = <
					0x0d4 0x0 /* CAM0_RST */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			uart0_cfg_func: uart0_cfg_func {
				pinctrl-single,pins = <
					0x0d8 0x0 /* UART0_RXD */
					0x0dc 0x0 /* UART0_TXD */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			uart6_cfg_func: uart6_cfg_func {
				pinctrl-single,pins = <
					0x0d8 0x0 /* UART6_CTS_N */
					0x0dc 0x0 /* UART6_RTS_N */
					0x0e0 0x0 /* UART6_RXD */
					0x0e4 0x0 /* UART6_TXD */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			uart3_cfg_func: uart3_cfg_func {
				pinctrl-single,pins = <
					0x0e8 0x0 /* UART3_CTS_N */
					0x0ec 0x0 /* UART3_RTS_N */
					0x0f0 0x0 /* UART3_RXD */
					0x0f4 0x0 /* UART3_TXD */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			uart4_cfg_func: uart4_cfg_func {
				pinctrl-single,pins = <
					0x0f8 0x0 /* UART4_CTS_N */
					0x0fc 0x0 /* UART4_RTS_N */
					0x100 0x0 /* UART4_RXD */
					0x104 0x0 /* UART4_TXD */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			cam1_rst_cfg_func: cam1_rst_cfg_func {
				pinctrl-single,pins = <
					0x130 0x0 /* CAM1_RST */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};
		};

		pmx6: pinmux@ff3b6800 {
			compatible = "pinconf-single";
			reg = <0x0 0xff3b6800 0x0 0x18>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;

			ufs_cfg_func: ufs_cfg_func {
				pinctrl-single,pins = <
					0x000 0x0 /* UFS_REF_CLK */
					0x004 0x0 /* UFS_RST_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_08MA DRIVE6_MASK
				>;
			};

			spi3_cfg_func: spi3_cfg_func {
				pinctrl-single,pins = <
					0x008 0x0 /* SPI3_CLK */
					0x00c 0x0 /* SPI3_DI */
					0x010 0x0 /* SPI3_DO */
					0x014 0x0 /* SPI3_CS0_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_06MA DRIVE6_MASK
				>;
			};
		};

		pmx7: pinmux@ff3fd800 {
			compatible = "pinconf-single";
			reg = <0x0 0xff3fd800 0x0 0x18>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;

			sdio_clk_cfg_func: sdio_clk_cfg_func {
				pinctrl-single,pins = <
					0x000 0x0 /* SDIO_CLK */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE6_32MA DRIVE6_MASK
				>;
			};

			sdio_cfg_func: sdio_cfg_func {
				pinctrl-single,pins = <
					0x004 0x0 /* SDIO_CMD */
					0x008 0x0 /* SDIO_DATA0 */
					0x00c 0x0 /* SDIO_DATA1 */
					0x010 0x0 /* SDIO_DATA2 */
					0x014 0x0 /* SDIO_DATA3 */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE6_19MA DRIVE6_MASK
				>;
			};
		};

		pmx8: pinmux@ff37e800 {
			compatible = "pinconf-single";
			reg = <0x0 0xff37e800 0x0 0x18>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;

			sd_clk_cfg_func: sd_clk_cfg_func {
				pinctrl-single,pins = <
					0x000 0x0 /* SD_CLK */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE6_32MA
					DRIVE6_MASK
				>;
			};

			sd_cfg_func: sd_cfg_func {
				pinctrl-single,pins = <
					0x004 0x0 /* SD_CMD */
					0x008 0x0 /* SD_DATA0 */
					0x00c 0x0 /* SD_DATA1 */
					0x010 0x0 /* SD_DATA2 */
					0x014 0x0 /* SD_DATA3 */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE6_19MA
					DRIVE6_MASK
				>;
			};
		};

		pmx9: pinmux@fff11800 {
			compatible = "pinconf-single";
			reg = <0x0 0xfff11800 0x0 0xbc>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;

			i2c0_cfg_func: i2c0_cfg_func {
				pinctrl-single,pins = <
					0x01c 0x0 /* I2C0_SCL */
					0x020 0x0 /* I2C0_SDA */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			i2c1_cfg_func: i2c1_cfg_func {
				pinctrl-single,pins = <
					0x024 0x0 /* I2C1_SCL */
					0x028 0x0 /* I2C1_SDA */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			i2c7_cfg_func: i2c7_cfg_func {
				pinctrl-single,pins = <
					0x02c 0x0 /* I2C7_SCL */
					0x030 0x0 /* I2C7_SDA */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			slimbus_cfg_func: slimbus_cfg_func {
				pinctrl-single,pins = <
					0x034 0x0 /* SLIMBUS_CLK */
					0x038 0x0 /* SLIMBUS_DATA */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			i2s0_cfg_func: i2s0_cfg_func {
				pinctrl-single,pins = <
					0x040 0x0 /* I2S0_DI */
					0x044 0x0 /* I2S0_DO */
					0x048 0x0 /* I2S0_XCLK */
					0x04c 0x0 /* I2S0_XFS */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			i2s2_cfg_func: i2s2_cfg_func {
				pinctrl-single,pins = <
					0x050 0x0 /* I2S2_DI */
					0x054 0x0 /* I2S2_DO */
					0x058 0x0 /* I2S2_XCLK */
					0x05c 0x0 /* I2S2_XFS */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			pcie_cfg_func: pcie_cfg_func {
				pinctrl-single,pins = <
					0x094 0x0 /* PCIE_CLKREQ_N */
					0x098 0x0 /* PCIE_WAKE_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			spi2_cfg_func: spi2_cfg_func {
				pinctrl-single,pins = <
					0x09c 0x0 /* SPI2_CLK */
					0x0a0 0x0 /* SPI2_DI */
					0x0a4 0x0 /* SPI2_DO */
					0x0a8 0x0 /* SPI2_CS0_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_06MA DRIVE6_MASK
				>;
			};

			usb_cfg_func: usb_cfg_func {
				pinctrl-single,pins = <
					0x0ac 0x0 /* GPIO_219 */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Pinctrl dts file for HiSilicon HiKey970 development board
 */

#include <dt-bindings/pinctrl/hisi.h>

/ {
	soc {
		range: gpio-range {
			#pinctrl-single,gpio-range-cells = <3>;
		};

		pmx0: pinmux@e896c000 {
			compatible = "pinctrl-single";
			reg = <0x0 0xe896c000 0x0 0x72c>;
			#pinctrl-cells = <1>;
			#gpio-range-cells = <0x3>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x7>;
			/* pin base, nr pins & gpio function */
			pinctrl-single,gpio-range = <&range 0 82 0>;

			uart0_pmx_func: uart0_pmx_func {
				pinctrl-single,pins = <
					0x054 MUX_M2 /* UART0_RXD */
					0x058 MUX_M2 /* UART0_TXD */
				>;
			};

			uart2_pmx_func: uart2_pmx_func {
				pinctrl-single,pins = <
					0x700 MUX_M2 /* UART2_CTS_N */
					0x704 MUX_M2 /* UART2_RTS_N */
					0x708 MUX_M2 /* UART2_RXD */
					0x70c MUX_M2 /* UART2_TXD */
				>;
			};

			uart3_pmx_func: uart3_pmx_func {
				pinctrl-single,pins = <
					0x064 MUX_M1 /* UART3_CTS_N */
					0x068 MUX_M1 /* UART3_RTS_N */
					0x06c MUX_M1 /* UART3_RXD */
					0x070 MUX_M1 /* UART3_TXD */
				>;
			};

			uart4_pmx_func: uart4_pmx_func {
				pinctrl-single,pins = <
					0x074 MUX_M1 /* UART4_CTS_N */
					0x078 MUX_M1 /* UART4_RTS_N */
					0x07c MUX_M1 /* UART4_RXD */
					0x080 MUX_M1 /* UART4_TXD */
				>;
			};

			uart6_pmx_func: uart6_pmx_func {
				pinctrl-single,pins = <
					0x05c MUX_M1 /* UART6_RXD */
					0x060 MUX_M1 /* UART6_TXD */
				>;
			};

			i2c3_pmx_func: i2c3_pmx_func {
				pinctrl-single,pins = <
					0x010 MUX_M1 /* I2C3_SCL */
					0x014 MUX_M1 /* I2C3_SDA */
				>;
			};

			i2c4_pmx_func: i2c4_pmx_func {
				pinctrl-single,pins = <
					0x03c MUX_M1 /* I2C4_SCL */
					0x040 MUX_M1 /* I2C4_SDA */
				>;
			};

			cam0_rst_pmx_func: cam0_rst_pmx_func {
				pinctrl-single,pins = <
					0x714 MUX_M0 /* CAM0_RST */
				>;
			};

			cam1_rst_pmx_func: cam1_rst_pmx_func {
				pinctrl-single,pins = <
					0x048 MUX_M0 /* CAM1_RST */
				>;
			};

			cam0_pwd_n_pmx_func: cam0_pwd_n_pmx_func {
				pinctrl-single,pins = <
					0x098 MUX_M0 /* CAM0_PWD_N */
				>;
			};

			cam1_pwd_n_pmx_func: cam1_pwd_n_pmx_func {
				pinctrl-single,pins = <
					0x044 MUX_M0 /* CAM1_PWD_N */
				>;
			};

			isp0_pmx_func: isp0_pmx_func {
				pinctrl-single,pins = <
					0x018 MUX_M1 /* ISP_CLK0 */
					0x024 MUX_M1 /* ISP_SCL0 */
					0x028 MUX_M1 /* ISP_SDA0 */
				>;
			};

			isp1_pmx_func: isp1_pmx_func {
				pinctrl-single,pins = <
					0x01c MUX_M1 /* ISP_CLK1 */
					0x02c MUX_M1 /* ISP_SCL1 */
					0x030 MUX_M1 /* ISP_SDA1 */
				>;
			};
		};

		pmx1: pinmux@fff11000 {
			compatible = "pinctrl-single";
			reg = <0x0 0xfff11000 0x0 0x73c>;
			#gpio-range-cells = <0x3>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x7>;
			/* pin base, nr pins & gpio function */
			pinctrl-single,gpio-range = <&range 0 46 0>;

			pwr_key_pmx_func: pwr_key_pmx_func {
				pinctrl-single,pins = <
					0x064 MUX_M0 /* GPIO_203 */
				>;
			};

			pd_pmx_func: pd_pmx_func{
				pinctrl-single,pins = <
					0x080 MUX_M0 /* GPIO_221 */
				>;
			};

			i2s2_pmx_func: i2s2_pmx_func {
			    pinctrl-single,pins = <
					0x050 MUX_M1 /* I2S2_DI */
					0x054 MUX_M1 /* I2S2_DO */
					0x058 MUX_M1 /* I2S2_XCLK */
					0x05c MUX_M1 /* I2S2_XFS */
			    >;
			};

			spi0_pmx_func: spi0_pmx_func {
				pinctrl-single,pins = <
					0x094 MUX_M1 /* SPI0_CLK */
					0x098 MUX_M1 /* SPI0_DI */
					0x09c MUX_M1 /* SPI0_DO */
					0x0a0 MUX_M1 /* SPI0_CS0_N */
				>;
			};

			spi2_pmx_func: spi2_pmx_func {
				pinctrl-single,pins = <
					0x710 MUX_M1 /* SPI2_CLK */
					0x714 MUX_M1 /* SPI2_DI */
					0x718 MUX_M1 /* SPI2_DO */
					0x71c MUX_M1 /* SPI2_CS0_N */
				>;
			};

			spi3_pmx_func: spi3_pmx_func {
				pinctrl-single,pins = <
					0x72c MUX_M1 /* SPI3_CLK */
					0x730 MUX_M1 /* SPI3_DI */
					0x734 MUX_M1 /* SPI3_DO */
					0x738 MUX_M1 /* SPI3_CS0_N */
				>;
			};

			i2c0_pmx_func: i2c0_pmx_func {
				pinctrl-single,pins = <
					0x020 MUX_M1 /* I2C0_SCL */
					0x024 MUX_M1 /* I2C0_SDA */
				>;
			};

			i2c1_pmx_func: i2c1_pmx_func {
				pinctrl-single,pins = <
					0x028 MUX_M1 /* I2C1_SCL */
					0x02c MUX_M1 /* I2C1_SDA */
				>;
			};
			i2c2_pmx_func: i2c2_pmx_func {
				pinctrl-single,pins = <
					0x030 MUX_M1 /* I2C2_SCL */
					0x034 MUX_M1 /* I2C2_SDA */
				>;
			};

			pcie_clkreq_pmx_func: pcie_clkreq_pmx_func {
				pinctrl-single,pins = <
					0x084 MUX_M1 /* PCIE0_CLKREQ_N */
				>;
			};

			gpio185_pmx_func: gpio185_pmx_func {
				pinctrl-single,pins = <0x01C    0x1>;
			};

			gpio185_pmx_idle: gpio185_pmx_idle {
				pinctrl-single,pins = <0x01C    0x0>;
			};
		};

		pmx2: pinmux@e896c800 {
			compatible = "pinconf-single";
			reg = <0x0 0xe896c800 0x0 0x72c>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;

			uart0_cfg_func: uart0_cfg_func {
				pinctrl-single,pins = <
					0x058 0x0 /* UART0_RXD */
					0x05c 0x0 /* UART0_TXD */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			uart2_cfg_func: uart2_cfg_func {
				pinctrl-single,pins = <
					0x700 0x0 /* UART2_CTS_N */
					0x704 0x0 /* UART2_RTS_N */
					0x708 0x0 /* UART2_RXD */
					0x70c 0x0 /* UART2_TXD */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			uart3_cfg_func: uart3_cfg_func {
				pinctrl-single,pins = <
					0x068 0x0 /* UART3_CTS_N */
					0x06c 0x0 /* UART3_RTS_N */
					0x070 0x0 /* UART3_RXD */
					0x074 0x0 /* UART3_TXD */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			uart4_cfg_func: uart4_cfg_func {
				pinctrl-single,pins = <
					0x078 0x0 /* UART4_CTS_N */
					0x07c 0x0 /* UART4_RTS_N */
					0x080 0x0 /* UART4_RXD */
					0x084 0x0 /* UART4_TXD */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			uart6_cfg_func: uart6_cfg_func {
				pinctrl-single,pins = <
					0x060 0x0 /* UART6_RXD */
					0x064 0x0 /* UART6_TXD */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			i2c3_cfg_func: i2c3_cfg_func {
				pinctrl-single,pins = <
					0x014 0x0 /* I2C3_SCL */
					0x018 0x0 /* I2C3_SDA */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			i2c4_cfg_func: i2c4_cfg_func {
				pinctrl-single,pins = <
					0x040 0x0 /* I2C4_SCL */
					0x044 0x0 /* I2C4_SDA */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			cam0_rst_cfg_func: cam0_rst_cfg_func {
				pinctrl-single,pins = <
					0x714 0x0 /* CAM0_RST */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			cam1_rst_cfg_func: cam1_rst_cfg_func {
				pinctrl-single,pins = <
					0x04C 0x0 /* CAM1_RST */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			cam0_pwd_n_cfg_func: cam0_pwd_n_cfg_func {
				pinctrl-single,pins = <
					0x09C 0x0 /* CAM0_PWD_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			cam1_pwd_n_cfg_func: cam1_pwd_n_cfg_func {
				pinctrl-single,pins = <
					0x048 0x0 /* CAM1_PWD_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			isp0_cfg_func: isp0_cfg_func {
				pinctrl-single,pins = <
					0x01C 0x0 /* ISP_CLK0 */
					0x028 0x0 /* ISP_SCL0 */
					0x02C 0x0 /* ISP_SDA0 */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			isp1_cfg_func: isp1_cfg_func {
				pinctrl-single,pins = <
					0x020 0x0 /* ISP_CLK1 */
					0x030 0x0 /* ISP_SCL1 */
					0x034 0x0 /* ISP_SDA1 */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};
		};

		pmx5: pinmux@fc182000 {
			compatible = "pinctrl-single";
			reg = <0x0 0xfc182000 0x0 0x028>;
			#gpio-range-cells = <3>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <0x7>;
			/* pin base, nr pins & gpio function */
			pinctrl-single,gpio-range = <&range 0 10 0>;

			sdio_pmx_func: sdio_pmx_func {
				pinctrl-single,pins = <
					0x000 MUX_M1 /* SDIO_CLK */
					0x004 MUX_M1 /* SDIO_CMD */
					0x008 MUX_M1 /* SDIO_DATA0 */
					0x00c MUX_M1 /* SDIO_DATA1 */
					0x010 MUX_M1 /* SDIO_DATA2 */
					0x014 MUX_M1 /* SDIO_DATA3 */
				>;
			};
		};

		pmx6: pinmux@fc182800 {
			compatible = "pinconf-single";
			reg = <0x0 0xfc182800 0x0 0x028>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;

			sdio_clk_cfg_func: sdio_clk_cfg_func {
				pinctrl-single,pins = <
					0x000 0x0 /* SDIO_CLK */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE6_32MA DRIVE6_MASK
				>;
			};

			sdio_cfg_func: sdio_cfg_func {
				pinctrl-single,pins = <
					0x004 0x0 /* SDIO_CMD */
					0x008 0x0 /* SDIO_DATA0 */
					0x00c 0x0 /* SDIO_DATA1 */
					0x010 0x0 /* SDIO_DATA2 */
					0x014 0x0 /* SDIO_DATA3 */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE6_19MA DRIVE6_MASK
				>;
			};
		};

		pmx7: pinmux@ff37e000 {
			compatible = "pinctrl-single";
			reg = <0x0 0xff37e000 0x0 0x030>;
			#gpio-range-cells = <3>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;
			pinctrl-single,function-mask = <7>;
			/* pin base, nr pins & gpio function */
			pinctrl-single,gpio-range = <&range 0 12 0>;

			sd_pmx_func: sd_pmx_func {
				pinctrl-single,pins = <
					0x000 MUX_M1 /* SD_CLK */
					0x004 MUX_M1 /* SD_CMD */
					0x008 MUX_M1 /* SD_DATA0 */
					0x00c MUX_M1 /* SD_DATA1 */
					0x010 MUX_M1 /* SD_DATA2 */
					0x014 MUX_M1 /* SD_DATA3 */
				>;
			};
		};

		pmx8: pinmux@ff37e800 {
			compatible = "pinconf-single";
			reg = <0x0 0xff37e800 0x0 0x030>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;

			sd_clk_cfg_func: sd_clk_cfg_func {
				pinctrl-single,pins = <
					0x000 0x0 /* SD_CLK */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE6_32MA
					DRIVE6_MASK
				>;
			};

			sd_cfg_func: sd_cfg_func {
				pinctrl-single,pins = <
					0x004 0x0 /* SD_CMD */
					0x008 0x0 /* SD_DATA0 */
					0x00c 0x0 /* SD_DATA1 */
					0x010 0x0 /* SD_DATA2 */
					0x014 0x0 /* SD_DATA3 */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE6_19MA
					DRIVE6_MASK
				>;
			};
		};

		pmx16: pinmux@fff11800 {
			compatible = "pinconf-single";
			reg = <0x0 0xfff11800 0x0 0x73c>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <0x20>;

			pwr_key_cfg_func: pwr_key_cfg_func {
				pinctrl-single,pins = <
					0x090 0x0 /* GPIO_203 */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			usb_cfg_func: usb_cfg_func {
				pinctrl-single,pins = <
					0x0AC 0x0 /* GPIO_221 */
				>;
				pinctrl-single,bias-pulldown  = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup    = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			spi0_cfg_func: spi0_cfg_func {
				pinctrl-single,pins = <
					0x0c8 0x0 /* SPI0_DI */
					0x0cc 0x0 /* SPI0_DO */
					0x0d0 0x0 /* SPI0_CS0_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_06MA DRIVE6_MASK
				>;
			};

			spi2_cfg_func: spi2_cfg_func {
				pinctrl-single,pins = <
					0x714 0x0 /* SPI2_DI */
					0x718 0x0 /* SPI2_DO */
					0x71c 0x0 /* SPI2_CS0_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_06MA DRIVE6_MASK
				>;
			};

			spi3_cfg_func: spi3_cfg_func {
				pinctrl-single,pins = <
					0x730 0x0 /* SPI3_DI */
					0x734 0x0 /* SPI3_DO */
					0x738 0x0 /* SPI3_CS0_N */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_06MA DRIVE6_MASK
				>;
			};

			spi0_clk_cfg_func: spi0_clk_cfg_func {
				pinctrl-single,pins = <
					0x0c4 0x0 /* SPI0_CLK */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_10MA DRIVE6_MASK
				>;
			};

			spi2_clk_cfg_func: spi2_clk_cfg_func {
				pinctrl-single,pins = <
					0x710 0x0 /* SPI2_CLK */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_10MA DRIVE6_MASK
				>;
			};

			spi3_clk_cfg_func: spi3_clk_cfg_func {
				pinctrl-single,pins = <
					0x72c 0x0 /* SPI3_CLK */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_10MA DRIVE6_MASK
				>;
			};

			i2c0_cfg_func: i2c0_cfg_func {
				pinctrl-single,pins = <
					0x04c 0x0 /* I2C0_SCL */
					0x050 0x0 /* I2C0_SDA */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			i2c1_cfg_func: i2c1_cfg_func {
				pinctrl-single,pins = <
					0x054 0x0 /* I2C1_SCL */
					0x058 0x0 /* I2C1_SDA */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			i2c2_cfg_func: i2c2_cfg_func {
				pinctrl-single,pins = <
					0x05c 0x0 /* I2C2_SCL */
					0x060 0x0 /* I2C2_SDA */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_04MA DRIVE6_MASK
				>;
			};

			pcie_clkreq_cfg_func: pcie_clkreq_cfg_func {
				pinctrl-single,pins = <
					0x0b0 0x0
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_DIS
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_06MA DRIVE6_MASK
				>;
			};
			i2s2_cfg_func: i2s2_cfg_func {
				pinctrl-single,pins = <
					0x07c 0x0 /* I2S2_DI */
					0x080 0x0 /* I2S2_DO */
					0x084 0x0 /* I2S2_XCLK */
					0x088 0x0 /* I2S2_XFS */
				>;
				pinctrl-single,bias-pulldown = <
					PULL_DIS
					PULL_DOWN
					PULL_DIS
					PULL_DOWN
				>;
				pinctrl-single,bias-pullup = <
					PULL_UP
					PULL_UP
					PULL_DIS
					PULL_UP
				>;
				pinctrl-single,drive-strength = <
					DRIVE7_02MA DRIVE6_MASK
				>;
			};

			gpio185_cfg_func: gpio185_cfg_func {
				pinctrl-single,pins = <0x048  0>;
				pinctrl-single,bias-pulldown = <0 2 0 2>;
				pinctrl-single,bias-pullup = <0 1 0 1>;
				pinctrl-single,drive-strength = <0x00 0x70>;
				pinctrl-single,slew-rate = <0x0 0x80>;
			};

			gpio185_cfg_idle: gpio185_cfg_idle {
				pinctrl-single,pins = <0x048  0>;
				pinctrl-single,bias-pulldown = <2 2 0 2>;
				pinctrl-single,bias-pullup = <0 1 0 1>;
				pinctrl-single,drive-strength = <0x00 0x70>;
				pinctrl-single,slew-rate = <0x0 0x80>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Hi6421v600 SPMI PMIC used at the HiKey970 Development Board
 *
 * Copyright (C) 2020, Huawei Tech. Co., Ltd.
 */

#include <dt-bindings/spmi/spmi.h>

/ {
	spmi: spmi@fff24000 {
		compatible = "hisilicon,kirin970-spmi-controller";
		#address-cells = <2>;
		#size-cells = <0>;
		status = "okay";
		reg = <0x0 0xfff24000 0x0 0x1000>;
		hisilicon,spmi-channel = <2>;

		pmic: pmic@0 {
			compatible = "hisilicon,hi6421-spmi";
			reg = <0 SPMI_USID>;

			#interrupt-cells = <2>;
			interrupt-controller;
			gpios = <&gpio28 0 0>;

			regulators {
				#address-cells = <1>;
				#size-cells = <0>;

				ldo3: ldo3 { /* HDMI */
					regulator-name = "ldo3";
					regulator-min-microvolt = <1500000>;
					regulator-max-microvolt = <2000000>;
					regulator-boot-on;
				};

				ldo4: ldo4 { /* 40 PIN */
					regulator-name = "ldo4";
					regulator-min-microvolt = <1725000>;
					regulator-max-microvolt = <1900000>;
					regulator-boot-on;
				};

				ldo9: ldo9 { /* SDCARD I/O */
					regulator-name = "ldo9";
					regulator-min-microvolt = <1750000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
				};

				ldo15: ldo15 { /* UFS */
					regulator-name = "ldo15";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3000000>;
					regulator-always-on;
				};

				ldo16: ldo16 { /* SD */
					regulator-name = "ldo16";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3000000>;
					regulator-boot-on;
				};

				ldo17: ldo17 { /* USB HUB */
					regulator-name = "ldo17";
					regulator-min-microvolt = <2500000>;
					regulator-max-microvolt = <3300000>;
				};

				ldo33: ldo33 { /* PEX8606 */
					regulator-name = "ldo33";
					regulator-min-microvolt = <2500000>;
					regulator-max-microvolt = <3300000>;
				};

				ldo34: ldo34 { /* GPS AUX IN VDD */
					regulator-name = "ldo34";
					regulator-min-microvolt = <2600000>;
					regulator-max-microvolt = <3300000>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/**
 * dts file for Hisilicon D02 Development Board
 *
 * Copyright (C) 2014,2015 HiSilicon Ltd.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include "hip05.dtsi"

/ {
	model = "Hisilicon Hip05 D02 Development Board";
	compatible = "hisilicon,hip05-d02";

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x00000000 0x0 0x80000000>;
	};

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	gpio-keys {
		compatible = "gpio-keys";

		pwr-button {
			label = "Power Button";
			gpios = <&porta 8 GPIO_ACTIVE_LOW>;
			linux,code = <116>;
			debounce-interval = <0>;
		};
	};
};

&uart0 {
	status = "okay";
};

&peri_gpio0 {
	status = "okay";
};

&lbc {
	status = "okay";
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x0 0x90000000 0x08000000>,
		 <1 0 0x0 0x98000000 0x08000000>;

	nor-flash@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "numonyx,js28f00a", "cfi-flash";
		reg = <0 0x0 0x08000000>;
		bank-width = <2>;
		/* The three parts may not used */
		partition@0 {
			label = "BIOS";
			reg = <0x0 0x300000>;
		};
		partition@300000 {
			label = "Linux";
			reg = <0x300000 0xa00000>;
		};
		partition@1000000 {
			label = "Rootfs";
			reg = <0x01000000 0x02000000>;
		};
	};

	cpld@1,0 {
		compatible = "hisilicon,hip05-cpld";
		reg = <1 0x0 0x100>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/**
 * dts file for Hisilicon D02 Development Board
 *
 * Copyright (C) 2014,2015 HiSilicon Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "hisilicon,hip05-d02";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
			cluster2 {
				core0 {
					cpu = <&cpu8>;
				};
				core1 {
					cpu = <&cpu9>;
				};
				core2 {
					cpu = <&cpu10>;
				};
				core3 {
					cpu = <&cpu11>;
				};
			};
			cluster3 {
				core0 {
					cpu = <&cpu12>;
				};
				core1 {
					cpu = <&cpu13>;
				};
				core2 {
					cpu = <&cpu14>;
				};
				core3 {
					cpu = <&cpu15>;
				};
			};
		};

		cpu0: cpu@20000 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20000>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu1: cpu@20001 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20001>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu2: cpu@20002 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20002>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu3: cpu@20003 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20003>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu4: cpu@20100 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20100>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu5: cpu@20101 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20101>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu6: cpu@20102 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20102>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu7: cpu@20103 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20103>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu8: cpu@20200 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20200>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu9: cpu@20201 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20201>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu10: cpu@20202 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20202>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu11: cpu@20203 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20203>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu12: cpu@20300 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20300>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cpu13: cpu@20301 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20301>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cpu14: cpu@20302 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20302>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cpu15: cpu@20303 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20303>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cluster0_l2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};

		cluster1_l2: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
		};

		cluster2_l2: l2-cache2 {
			compatible = "cache";
			cache-level = <2>;
		};

		cluster3_l2: l2-cache3 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	gic: interrupt-controller@8d000000 {
		compatible = "arm,gic-v3";
                #interrupt-cells = <3>;
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
                interrupt-controller;
                #redistributor-regions = <1>;
                redistributor-stride = <0x0 0x30000>;
		reg = <0x0 0x8d000000 0 0x10000>,	/* GICD */
		      <0x0 0x8d100000 0 0x300000>,	/* GICR */
		      <0x0 0xfe000000 0 0x10000>,	/* GICC */
		      <0x0 0xfe010000 0 0x10000>,       /* GICH */
		      <0x0 0xfe020000 0 0x10000>;       /* GICV */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		its_peri: msi-controller@8c000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0x8c000000 0x0 0x40000>;
		};

		its_m3: msi-controller@a3000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0xa3000000 0x0 0x40000>;
		};

		its_pcie: msi-controller@b7000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0xb7000000 0x0 0x40000>;
		};

		its_dsa: msi-controller@c6000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0xc6000000 0x0 0x40000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	pmu {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		refclk200mhz: refclk200mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};

		uart0: serial@80300000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x80300000 0x0 0x10000>;
			interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&refclk200mhz>, <&refclk200mhz>;
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart1: serial@80310000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x80310000 0x0 0x10000>;
			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&refclk200mhz>, <&refclk200mhz>;
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		lbc: local-bus@80380000 {
			compatible = "hisilicon,hisi-localbus", "simple-bus";
			reg = <0x0 0x80380000 0x0 0x10000>;
			status = "disabled";
		};

		peri_gpio0: gpio@802e0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x0 0x802e0000 0x0 0x10000>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		peri_gpio1: gpio@802f0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x0 0x802f0000 0x0 0x10000>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/**
 * dts file for Hisilicon D03 Development Board
 *
 * Copyright (C) 2016 HiSilicon Ltd.
 */

/dts-v1/;

#include "hip06.dtsi"

/ {
	model = "Hisilicon Hip06 D03 Development Board";
	compatible = "hisilicon,hip06-d03";

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x00000000 0x0 0x40000000>;
	};

	chosen { };
};

&ipmi0 {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&eth0 {
	status = "okay";
};

&eth1 {
	status = "okay";
};

&eth2 {
	status = "okay";
};

&eth3 {
	status = "okay";
};

&sas1 {
	status = "okay";
};

&usb_ohci {
	status = "okay";
};

&usb_ehci {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/**
 * dts file for Hisilicon D03 Development Board
 *
 * Copyright (C) 2016 HiSilicon Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "hisilicon,hip06-d03";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
			cluster2 {
				core0 {
					cpu = <&cpu8>;
				};
				core1 {
					cpu = <&cpu9>;
				};
				core2 {
					cpu = <&cpu10>;
				};
				core3 {
					cpu = <&cpu11>;
				};
			};
			cluster3 {
				core0 {
					cpu = <&cpu12>;
				};
				core1 {
					cpu = <&cpu13>;
				};
				core2 {
					cpu = <&cpu14>;
				};
				core3 {
					cpu = <&cpu15>;
				};
			};
		};

		cpu0: cpu@10000 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10000>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu1: cpu@10001 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10001>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu2: cpu@10002 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10002>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu3: cpu@10003 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10003>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu4: cpu@10100 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10100>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu5: cpu@10101 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10101>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu6: cpu@10102 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10102>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu7: cpu@10103 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10103>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu8: cpu@10200 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10200>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu9: cpu@10201 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10201>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu10: cpu@10202 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10202>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu11: cpu@10203 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10203>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu12: cpu@10300 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10300>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cpu13: cpu@10301 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10301>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cpu14: cpu@10302 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10302>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cpu15: cpu@10303 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x10303>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cluster0_l2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};

		cluster1_l2: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
		};

		cluster2_l2: l2-cache2 {
			compatible = "cache";
			cache-level = <2>;
		};

		cluster3_l2: l2-cache3 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	gic: interrupt-controller@4d000000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x30000>;
		reg = <0x0 0x4d000000 0 0x10000>,	/* GICD */
		      <0x0 0x4d100000 0 0x300000>,	/* GICR */
		      <0x0 0xfe000000 0 0x10000>,	/* GICC */
		      <0x0 0xfe010000 0 0x10000>,       /* GICH */
		      <0x0 0xfe020000 0 0x10000>;       /* GICV */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		its_dsa: msi-controller@c6000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0xc6000000 0x0 0x40000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	pmu {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	mbigen_pcie@a0080000 {
		compatible = "hisilicon,mbigen-v2";
		reg = <0x0 0xa0080000 0x0 0x10000>;

		mbigen_usb: intc_usb {
			msi-parent = <&its_dsa 0x40080>;
			interrupt-controller;
			#interrupt-cells = <2>;
			num-pins = <2>;
		};

		mbigen_sas1: intc_sas1 {
			msi-parent = <&its_dsa 0x40000>;
			interrupt-controller;
			#interrupt-cells = <2>;
			num-pins = <128>;
		};

		mbigen_sas2: intc_sas2 {
			msi-parent = <&its_dsa 0x40040>;
			interrupt-controller;
			#interrupt-cells = <2>;
			num-pins = <128>;
		};

		mbigen_pcie0: intc_pcie0 {
			msi-parent = <&its_dsa 0x40085>;
			interrupt-controller;
			#interrupt-cells = <2>;
			num-pins = <10>;
		};
	};

	mbigen_dsa@c0080000 {
		compatible = "hisilicon,mbigen-v2";
		reg = <0x0 0xc0080000 0x0 0x10000>;

		mbigen_dsaf0: intc_dsaf0 {
			msi-parent = <&its_dsa 0x40800>;
			interrupt-controller;
			#interrupt-cells = <2>;
			num-pins = <409>;
		};

		mbigen_sas0: intc-sas0 {
			msi-parent = <&its_dsa 0x40900>;
			interrupt-controller;
			#interrupt-cells = <2>;
			num-pins = <128>;
		};
	};

	/**
	 *  HiSilicon erratum 161010801: This describes the limitation
	 *  of HiSilicon platforms hip06/hip07 to support the SMMUv3
	 *  mappings for PCIe MSI transactions.
	 *  PCIe controller on these platforms has to differentiate the
	 *  MSI payload against other DMA payload and has to modify the
	 *  MSI payload. This makes it difficult for these platforms to
	 *  have a SMMU translation for MSI. In order to workaround this,
	 *  ARM SMMUv3 driver requires a quirk to treat the MSI regions
	 *  separately. Such a quirk is currently missing for DT based
	 *  systems. Hence please make sure that the smmu pcie node on
	 *  hip06 is disabled as this will break the PCIe functionality
	 *  when iommu-map entry is used along with the PCIe node.
	 *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
	 */
	smmu0: iommu@a0040000 {
		compatible = "arm,smmu-v3";
		reg = <0x0 0xa0040000 0x0 0x20000>;
		#iommu-cells = <1>;
		dma-coherent;
		hisilicon,broken-prefetch-cmd;
		status = "disabled";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		isa@a01b0000 {
			compatible = "hisilicon,hip06-lpc";
			#size-cells = <1>;
			#address-cells = <2>;
			reg = <0x0 0xa01b0000 0x0 0x1000>;

			ipmi0: bt@e4 {
				compatible = "ipmi-bt";
				device_type = "ipmi";
				reg = <0x01 0xe4 0x04>;
				status = "disabled";
			};

			uart0: serial@2f8 {
				compatible = "ns16550a";
				clock-frequency = <1843200>;
				reg = <0x01 0x2f8 0x08>;
				status = "disabled";
			};
		};

		refclk: refclk {
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
			#clock-cells = <0>;
		};

		usb_ohci: usb@a7030000 {
			compatible = "generic-ohci";
			reg = <0x0 0xa7030000 0x0 0x10000>;
			interrupt-parent = <&mbigen_usb>;
			interrupts = <640 4>;
			dma-coherent;
			status = "disabled";
		};

		usb_ehci: usb@a7020000 {
			compatible = "generic-ehci";
			reg = <0x0 0xa7020000 0x0 0x10000>;
			interrupt-parent = <&mbigen_usb>;
			interrupts = <641 4>;
			dma-coherent;
			status = "disabled";
		};

		peri_c_subctrl: sub_ctrl_c@60000000 {
			compatible = "hisilicon,peri-subctrl","syscon";
			reg = <0 0x60000000 0x0 0x10000>;
		};

		dsa_subctrl: dsa_subctrl@c0000000 {
			compatible = "hisilicon,dsa-subctrl", "syscon";
			reg = <0x0 0xc0000000 0x0 0x10000>;
		};

		pcie_subctl: pcie_subctl@a0000000 {
			compatible = "hisilicon,pcie-sas-subctrl", "syscon";
			reg = <0x0 0xa0000000 0x0 0x10000>;
		};

		serdes_ctrl: sds_ctrl@c2200000 {
			compatible = "syscon";
			reg = <0 0xc2200000 0x0 0x80000>;
		};

		mdio@603c0000 {
			compatible = "hisilicon,hns-mdio";
			reg = <0x0 0x603c0000 0x0 0x1000>;
			subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
			#address-cells = <1>;
			#size-cells = <0>;

			phy0: ethernet-phy@0 {
				compatible = "ethernet-phy-ieee802.3-c22";
				reg = <0>;
			};

			phy1: ethernet-phy@1 {
				compatible = "ethernet-phy-ieee802.3-c22";
				reg = <1>;
			};
		};

		dsaf0: dsa@c7000000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "hisilicon,hns-dsaf-v2";
			mode = "6port-16rss";
			reg = <0x0 0xc5000000 0x0 0x890000>,
			      <0x0 0xc7000000 0x0 0x600000>;
			reg-names = "ppe-base", "dsaf-base";
			interrupt-parent = <&mbigen_dsaf0>;
			subctrl-syscon = <&dsa_subctrl>;
			reset-field-offset = <0>;
			interrupts =
			<576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
			<581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
			<586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
			<591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
			<596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
			<960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
			<965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
			<970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
			<975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
			<980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
			<985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
			<990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
			<995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
			<1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
			<1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
			<1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
			<1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
			<1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
			<1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
			<1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
			<1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
			<1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
			<1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
			<1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
			<1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
			<1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
			<1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
			<1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
			<1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
			<1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
			<1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
			<1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
			<1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
			<1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
			<1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
			<1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
			<1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
			<1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
			<1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
			<1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
			<1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
			<1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
			<1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
			<1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
			<1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
			<1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
			<1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
			<1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
			<1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
			<1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
			<1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
			<1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
			<1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
			<1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
			<1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
			<1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
			<1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
			<1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
			<1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
			<1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
			<1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
			<1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
			<1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
			<1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
			<1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
			<1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
			<1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
			<1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
			<1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
			<1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
			<1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
			<1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
			<1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
			<1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
			<1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
			<1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
			<1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
			<1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
			<1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
			<1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
			<1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
			<1340 1>, <1341 1>, <1342 1>, <1343 1>;

			desc-num = <0x400>;
			buf-size = <0x1000>;
			dma-coherent;

			port@0 {
				reg = <0>;
				serdes-syscon = <&serdes_ctrl>;
				port-rst-offset = <0>;
				port-mode-offset = <0>;
				media-type = "fiber";
			};

			port@1 {
				reg = <1>;
				serdes-syscon = <&serdes_ctrl>;
				port-rst-offset = <1>;
				port-mode-offset = <1>;
				media-type = "fiber";
			};

			port@4 {
				reg = <4>;
				phy-handle = <&phy0>;
				serdes-syscon = <&serdes_ctrl>;
				port-rst-offset = <4>;
				port-mode-offset = <2>;
				media-type = "copper";
			};

			port@5 {
				reg = <5>;
				phy-handle = <&phy1>;
				serdes-syscon = <&serdes_ctrl>;
				port-rst-offset = <5>;
				port-mode-offset = <3>;
				media-type = "copper";
			};
		};

		eth0: ethernet-4{
			compatible = "hisilicon,hns-nic-v2";
			ae-handle = <&dsaf0>;
			port-idx-in-ae = <4>;
			local-mac-address = [00 00 00 00 00 00];
			status = "disabled";
			dma-coherent;
		};

		eth1: ethernet-5{
			compatible = "hisilicon,hns-nic-v2";
			ae-handle = <&dsaf0>;
			port-idx-in-ae = <5>;
			local-mac-address = [00 00 00 00 00 00];
			status = "disabled";
			dma-coherent;
		};

		eth2: ethernet-0{
			compatible = "hisilicon,hns-nic-v2";
			ae-handle = <&dsaf0>;
			port-idx-in-ae = <0>;
			local-mac-address = [00 00 00 00 00 00];
			status = "disabled";
			dma-coherent;
		};

		eth3: ethernet-1{
			compatible = "hisilicon,hns-nic-v2";
			ae-handle = <&dsaf0>;
			port-idx-in-ae = <1>;
			local-mac-address = [00 00 00 00 00 00];
			status = "disabled";
			dma-coherent;
		};

		sas0: sas@c3000000 {
			compatible = "hisilicon,hip06-sas-v2";
			reg = <0 0xc3000000 0 0x10000>;
			sas-addr = [50 01 88 20 16 00 00 00];
			hisilicon,sas-syscon = <&dsa_subctrl>;
			ctrl-reset-reg = <0xa60>;
			ctrl-reset-sts-reg = <0x5a30>;
			ctrl-clock-ena-reg = <0x338>;
			clocks = <&refclk 0>;
			queue-count = <16>;
			phy-count = <8>;
			dma-coherent;
			interrupt-parent = <&mbigen_sas0>;
			interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
				     <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
				     <75 4>,<76 4>,<77 4>,<78 4>,<79 4>,
				     <80 4>,<81 4>,<82 4>,<83 4>,<84 4>,
				     <85 4>,<86 4>,<87 4>,<88 4>,<89 4>,
				     <90 4>,<91 4>,<92 4>,<93 4>,<94 4>,
				     <95 4>,<96 4>,<97 4>,<98 4>,<99 4>,
				     <100 4>,<101 4>,<102 4>,<103 4>,<104 4>,
				     <105 4>,<106 4>,<107 4>,<108 4>,<109 4>,
				     <110 4>,<111 4>,<112 4>,<113 4>,<114 4>,
				     <115 4>,<116 4>,<117 4>,<118 4>,<119 4>,
				     <120 4>,<121 4>,<122 4>,<123 4>,<124 4>,
				     <125 4>,<126 4>,<127 4>,<128 4>,<129 4>,
				     <130 4>,<131 4>,<132 4>,<133 4>,<134 4>,
				     <135 4>,<136 4>,<137 4>,<138 4>,<139 4>,
				     <140 4>,<141 4>,<142 4>,<143 4>,<144 4>,
				     <145 4>,<146 4>,<147 4>,<148 4>,<149 4>,
				     <150 4>,<151 4>,<152 4>,<153 4>,<154 4>,
				     <155 4>,<156 4>,<157 4>,<158 4>,<159 4>,
				     <160 4>,<601 1>,<602 1>,<603 1>,<604 1>,
				     <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
				     <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
				     <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
				     <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
				     <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
				     <630 1>,<631 1>,<632 1>;
			status = "disabled";
		};

		sas1: sas@a2000000 {
			compatible = "hisilicon,hip06-sas-v2";
			reg = <0 0xa2000000 0 0x10000>;
			sas-addr = [50 01 88 20 16 00 00 00];
			hisilicon,sas-syscon = <&pcie_subctl>;
			hip06-sas-v2-quirk-amt;
			ctrl-reset-reg = <0xa18>;
			ctrl-reset-sts-reg = <0x5a0c>;
			ctrl-clock-ena-reg = <0x318>;
			clocks = <&refclk 0>;
			queue-count = <16>;
			phy-count = <8>;
			dma-coherent;
			interrupt-parent = <&mbigen_sas1>;
			interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
				     <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
				     <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
				     <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
				     <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
				     <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
				     <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
				     <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
				     <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
				     <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
				     <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
				     <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
				     <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
				     <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
				     <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
				     <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
				     <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
				     <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
				     <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
				     <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
				     <580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
				     <585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
				     <590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
				     <595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
				     <600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
				     <605 1>,<606 1>,<607 1>;
			status = "disabled";
		};

		sas2: sas@a3000000 {
			compatible = "hisilicon,hip06-sas-v2";
			reg = <0 0xa3000000 0 0x10000>;
			sas-addr = [50 01 88 20 16 00 00 00];
			hisilicon,sas-syscon = <&pcie_subctl>;
			ctrl-reset-reg = <0xae0>;
			ctrl-reset-sts-reg = <0x5a70>;
			ctrl-clock-ena-reg = <0x3a8>;
			clocks = <&refclk 0>;
			queue-count = <16>;
			phy-count = <9>;
			dma-coherent;
			interrupt-parent = <&mbigen_sas2>;
			interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
				     <197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
				     <202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
				     <207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
				     <212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
				     <217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
				     <222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
				     <227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
				     <232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
				     <237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
				     <242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
				     <247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
				     <252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
				     <257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
				     <262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
				     <267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
				     <272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
				     <277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
				     <282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
				     <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
				     <612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
				     <617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
				     <622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
				     <627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
				     <632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
				     <637 1>,<638 1>,<639 1>;
			status = "disabled";
		};

		pcie0: pcie@a0090000 {
			compatible = "hisilicon,hip06-pcie-ecam";
			reg = <0 0xb0000000 0 0x2000000>,
			      <0 0xa0090000 0 0x10000>;
			bus-range = <0  31>;
			msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
			msi-map-mask = <0xffff>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000>,
				 <0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
					0x0 0 0 2 &mbigen_pcie0 650 4
					0x0 0 0 3 &mbigen_pcie0 650 4
					0x0 0 0 4 &mbigen_pcie0 650 4>;
			status = "disabled";
		};

	};

};