code:
Binding for Texas Instruments APLL clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1].  It assumes a
register-mapped APLL with usually two selectable input clocks
(reference clock and bypass clock), with analog phase locked
loop logic for multiplying the input clock to a desired output
clock. This clock also typically supports different operation
modes (locked, low power stop etc.) APLL mostly behaves like
a subtype of a DPLL [2], although a simplified one at that.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/dpll.txt

Required properties:
- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
- reg : address and length of the register set for controlling the APLL.
  It contains the information of registers in the following order:
	"control" - contains the control register offset
	"idlest" - contains the idlest register offset
	"autoidle" - contains the autoidle register offset (OMAP2 only)
- ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)

Examples:
	apll_pcie_ck: apll_pcie_ck {
		#clock-cells = <0>;
		clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
		reg = <0x021c>, <0x0220>;
		compatible = "ti,dra7-apll-clock";
	};

	apll96_ck: apll96_ck {
		#clock-cells = <0>;
		compatible = "ti,omap2-apll-clock";
		clocks = <&sys_ck>;
		ti,bit-shift = <2>;
		ti,idlest-shift = <8>;
		ti,clock-frequency = <96000000>;
		reg = <0x0500>, <0x0530>, <0x0520>;
	};


code:
Binding for Texas Instruments autoidle clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1]. It assumes a register mapped
clock which can be put to idle automatically by hardware based on the usage
and a configuration bit setting. Autoidle clock is never an individual
clock, it is always a derivative of some basic clock like a gate, divider,
or fixed-factor.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- reg : offset for the register controlling the autoidle
- ti,autoidle-shift : bit shift of the autoidle enable bit
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0

Examples:
	dpll_core_m4_ck: dpll_core_m4_ck {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <31>;
		ti,autoidle-shift = <8>;
		reg = <0x2d38>;
		ti,index-starts-at-one;
		ti,invert-autoidle-bit;
	};

	dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
		#clock-cells = <0>;
		compatible = "ti,fixed-factor-clock";
		clocks = <&dpll_usb_ck>;
		ti,clock-div = <1>;
		ti,autoidle-shift = <8>;
		reg = <0x01b4>;
		ti,clock-mult = <1>;
		ti,invert-autoidle-bit;
	};

repo_name: angery/linux


code:
Binding for Texas Instruments clockdomain.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1] in consumer role.
Every clock on TI SoC belongs to one clockdomain, but software
only needs this information for specific clocks which require
their parent clockdomain to be controlled when the clock is
enabled/disabled. This binding doesn't define a new clock
binding type, it is used to group existing clock nodes under
hardware hierarchy.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be "ti,clockdomain"
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of clocks within this domain

Optional properties:
- clock-output-names : from common clock binding.

Examples:
	dss_clkdm: dss_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
	};


code:
Binding for TI composite clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1]. It assumes a
register-mapped composite clock with multiple different sub-types;

a multiplexer clock with multiple input clock signals or parents, one
of which can be selected as output, this behaves exactly as [2]

an adjustable clock rate divider, this behaves exactly as [3]

a gating function which can be used to enable and disable the output
clock, this behaves exactly as [4]

The binding must provide a list of the component clocks that shall be
merged to this clock. The component clocks shall be of one of the
"ti,*composite*-clock" types.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/mux.txt
[3] Documentation/devicetree/bindings/clock/ti/divider.txt
[4] Documentation/devicetree/bindings/clock/ti/gate.txt

Required properties:
- compatible : shall be: "ti,composite-clock"
- clocks : link phandles of component clocks
- #clock-cells : from common clock binding; shall be set to 0.

Optional properties:
- clock-output-names : from common clock binding.

Examples:

usb_l4_gate_ick: usb_l4_gate_ick {
	#clock-cells = <0>;
	compatible = "ti,composite-interface-clock";
	clocks = <&l4_ick>;
	ti,bit-shift = <5>;
	reg = <0x0a10>;
};

usb_l4_div_ick: usb_l4_div_ick {
	#clock-cells = <0>;
	compatible = "ti,composite-divider-clock";
	clocks = <&l4_ick>;
	ti,bit-shift = <4>;
	ti,max-div = <1>;
	reg = <0x0a40>;
	ti,index-starts-at-one;
};

usb_l4_ick: usb_l4_ick {
	#clock-cells = <0>;
	compatible = "ti,composite-clock";
	clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
};


code:
Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks

TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
registers call CFGCHIPn. Some of these registers function as clock
gates. This document describes the bindings for those clocks.

All of the clock nodes described below must be child nodes of a CFGCHIP node
(compatible = "ti,da830-cfgchip").

USB PHY clocks
--------------
Required properties:
- compatible: shall be "ti,da830-usb-phy-clocks".
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: phandles to the parent clocks corresponding to clock-names
- clock-names: shall be "fck", "usb_refclkin", "auxclk"

This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.

eHRPWM Time Base Clock (TBCLK)
------------------------------
Required properties:
- compatible: shall be "ti,da830-tbclksync".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandle to the parent clock
- clock-names: shall be "fck"

PLL DIV4.5 divider
------------------
Required properties:
- compatible: shall be "ti,da830-div4p5ena".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandle to the parent clock
- clock-names: shall be "pll0_pllout"

EMIFA clock source (ASYNC1)
---------------------------
Required properties:
- compatible: shall be "ti,da850-async1-clksrc".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandles to the parent clocks corresponding to clock-names
- clock-names: shall be "pll0_sysclk3", "div4.5"

ASYNC3 clock source
-------------------
Required properties:
- compatible: shall be "ti,da850-async3-clksrc".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandles to the parent clocks corresponding to clock-names
- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"

Examples:

	cfgchip: syscon@1417c {
		compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
		reg = <0x1417c 0x14>;

		usb_phy_clk: usb-phy-clocks {
			compatible = "ti,da830-usb-phy-clocks";
			#clock-cells = <1>;
			clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;
			clock-names = "fck", "usb_refclkin", "auxclk";
		};
		ehrpwm_tbclk: ehrpwm_tbclk {
			compatible = "ti,da830-tbclksync";
			#clock-cells = <0>;
			clocks = <&psc1 17>;
			clock-names = "fck";
		};
		div4p5_clk: div4.5 {
			compatible = "ti,da830-div4p5ena";
			#clock-cells = <0>;
			clocks = <&pll0_pllout>;
			clock-names = "pll0_pllout";
		};
		async1_clk: async1 {
			compatible = "ti,da850-async1-clksrc";
			#clock-cells = <0>;
			clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
			clock-names = "pll0_sysclk3", "div4.5";
		};
		async3_clk: async3 {
			compatible = "ti,da850-async3-clksrc";
			#clock-cells = <0>;
			clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
			clock-names = "pll0_sysclk2", "pll1_sysclk2";
		};
	};

Also see:
- Documentation/devicetree/bindings/clock/clock-bindings.txt


code:
Binding for TI DaVinci PLL Controllers

The PLL provides clocks to most of the components on the SoC. In addition
to the PLL itself, this controller also contains bypasses, gates, dividers,
an multiplexers for various clock signals.

Required properties:
- compatible: shall be one of:
	- "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
	- "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
- reg: physical base address and size of the controller's register area.
- clocks: phandles corresponding to the clock names
- clock-names: names of the clock sources - depends on compatible string
	- for "ti,da850-pll0", shall be "clksrc", "extclksrc"
	- for "ti,da850-pll1", shall be "clksrc"

Optional properties:
- ti,clkmode-square-wave: Indicates that the board is supplying a square
	wave input on the OSCIN pin instead of using a crystal oscillator.
	This property is only valid when compatible = "ti,da850-pll0".

Optional child nodes:

pllout
	Describes the main PLL clock output (before POSTDIV). The node name must
	be "pllout".

	Required properties:
	- #clock-cells: shall be 0

sysclk
	Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
	domains. The node name must be "sysclk". Consumers of this node should
	use "n" in "SYSCLKn" as the index parameter for the clock cell.

	Required properties:
	- #clock-cells: shall be 1

auxclk
	Describes the AUXCLK output of the PLL. The node name must be "auxclk".
	This child node is only valid when compatible = "ti,da850-pll0".

	Required properties:
	- #clock-cells: shall be 0

obsclk
	Describes the OBSCLK output of the PLL. The node name must be "obsclk".

	Required properties:
	- #clock-cells: shall be 0

Examples:

	pll0: clock-controller@11000 {
		compatible = "ti,da850-pll0";
		reg = <0x11000 0x1000>;
		clocks = <&ref_clk>, <&pll1_sysclk 3>;
		clock-names = "clksrc", "extclksrc";
		ti,clkmode-square-wave;

		pll0_pllout: pllout {
			#clock-cells = <0>;
		};

		pll0_sysclk: sysclk {
			#clock-cells = <1>;
		};

		pll0_auxclk: auxclk {
			#clock-cells = <0>;
		};

		pll0_obsclk: obsclk {
			#clock-cells = <0>;
		};
	};

	pll1: clock-controller@21a000 {
		compatible = "ti,da850-pll1";
		reg = <0x21a000 0x1000>;
		clocks = <&ref_clk>;
		clock-names = "clksrc";

		pll0_sysclk: sysclk {
			#clock-cells = <1>;
		};

		pll0_obsclk: obsclk {
			#clock-cells = <0>;
		};
	};

Also see:
- Documentation/devicetree/bindings/clock/clock-bindings.txt


code:
Binding for TI DaVinci Power Sleep Controller (PSC)

The PSC provides power management, clock gating and reset functionality. It is
primarily used for clocking.

Required properties:
- compatible: shall be one of:
	- "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
	- "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
- reg: physical base address and size of the controller's register area
- #clock-cells: from common clock binding; shall be set to 1
- #power-domain-cells: from generic power domain binding; shall be set to 1.
- clocks: phandles to clocks corresponding to the clock-names property
- clock-names: list of parent clock names - depends on compatible value
	- for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
	  "pll0_sysclk4", "pll0_sysclk6", "async1"
	- for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"

Optional properties:
- #reset-cells: from reset binding; shall be set to 1 - only applicable when
  at least one local domain provides a local reset.

Consumers:

	Clock, power domain and reset consumers shall use the local power domain
	module ID (LPSC) as the index corresponding to the clock cell. Refer to
	the device-specific datasheet to find these numbers. NB: Most local
	domains	only provide a clock/power domain and not a reset.

Examples:

	psc0: clock-controller@10000 {
		compatible = "ti,da850-psc0";
		reg = <0x10000 0x1000>;
		#clock-cells = <1>;
		#power-domain-cells = <1>;
		#reset-cells = <1>;
		clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
			 <&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>;
		clock_names = "pll0_sysclk1", "pll0_sysclk2",
			      "pll0_sysclk4", "pll0_sysclk6", "async1";
	};
	psc1: clock-controller@227000 {
		compatible = "ti,da850-psc1";
		reg = <0x227000 0x1000>;
		#clock-cells = <1>;
		#power-domain-cells = <1>;
		clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>;
		clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3";
	};

	/* consumer */
	dsp: dsp@11800000 {
		compatible = "ti,da850-dsp";
		reg = <0x11800000 0x40000>,
		      <0x11e00000 0x8000>,
		      <0x11f00000 0x8000>,
		      <0x01c14044 0x4>,
		      <0x01c14174 0x8>;
		reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
		interrupt-parent = <&intc>;
		interrupts = <28>;
		clocks = <&psc0 15>;
		power-domains = <&psc0 15>;
		resets = <&psc0 15>;
	};

Also see:
- Documentation/devicetree/bindings/clock/clock-bindings.txt
- Documentation/devicetree/bindings/power/power-domain.yaml
- Documentation/devicetree/bindings/reset/reset.txt


code:
Binding for TI divider clock

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1].  It assumes a
register-mapped adjustable clock rate divider that does not gate and has
only one input clock or parent.  By default the value programmed into
the register is one less than the actual divisor value.  E.g:

register value		actual divisor value
0			1
1			2
2			3

This assumption may be modified by the following optional properties:

ti,index-starts-at-one - valid divisor values start at 1, not the default
of 0.  E.g:
register value		actual divisor value
1			1
2			2
3			3

ti,index-power-of-two - valid divisor values are powers of two.  E.g:
register value		actual divisor value
0			1
1			2
2			4

Additionally an array of valid dividers may be supplied like so:

	ti,dividers = <4>, <8>, <0>, <16>;

Which will map the resulting values to a divisor table by their index:
register value		actual divisor value
0			4
1			8
2			<invalid divisor, skipped>
3			16

Any zero value in this array means the corresponding bit-value is invalid
and must not be used.

The binding must also provide the register to control the divider and
unless the divider array is provided, min and max dividers. Optionally
the number of bits to shift that mask, if necessary. If the shift value
is missing it is the same as supplying a zero shift.

This binding can also optionally provide support to the hardware autoidle
feature, see [2].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt

Required properties:
- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link to phandle of parent clock
- reg : offset for register controlling adjustable divider

Optional properties:
- clock-output-names : from common clock binding.
- ti,dividers : array of integers defining divisors
- ti,bit-shift : number of bits to shift the divider value, defaults to 0
- ti,min-div : min divisor for dividing the input clock rate, only
  needed if the first divisor is offset from the default value (1)
- ti,max-div : max divisor for dividing the input clock rate, only needed
  if ti,dividers is not defined.
- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
  only valid if ti,dividers is not defined.
- ti,index-power-of-two : valid divisor programming must be a power of two,
  only valid if ti,dividers is not defined.
- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
  see [2]
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
  see [2]
- ti,set-rate-parent : clk_set_rate is propagated to parent
- ti,latch-bit : latch the divider value to HW, only needed if the register
  access requires this. As an example dra76x DPLL_GMAC H14 divider implements
  such behavior.

Examples:
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
	#clock-cells = <0>;
	compatible = "ti,divider-clock";
	clocks = <&dpll_usb_ck>;
	ti,max-div = <127>;
	reg = <0x190>;
	ti,index-starts-at-one;
};

aess_fclk: aess_fclk@4a004528 {
	#clock-cells = <0>;
	compatible = "ti,divider-clock";
	clocks = <&abe_clk>;
	ti,bit-shift = <24>;
	reg = <0x528>;
	ti,max-div = <2>;
};

dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
	#clock-cells = <0>;
	compatible = "ti,composite-divider-clock";
	clocks = <&dpll_core_x2_ck>;
	ti,max-div = <31>;
	reg = <0x0134>;
	ti,index-starts-at-one;
};

ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
	#clock-cells = <0>;
	compatible = "ti,composite-divider-clock";
	clocks = <&corex2_fck>;
	ti,bit-shift = <8>;
	reg = <0x0a40>;
	ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};


code:
Binding for Texas Instruments DPLL clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1].  It assumes a
register-mapped DPLL with usually two selectable input clocks
(reference clock and bypass clock), with digital phase locked
loop logic for multiplying the input clock to a desired output
clock. This clock also typically supports different operation
modes (locked, low power stop etc.) This binding has several
sub-types, which effectively result in slightly different setup
for the actual DPLL clock.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be one of:
		"ti,omap3-dpll-clock",
		"ti,omap3-dpll-core-clock",
		"ti,omap3-dpll-per-clock",
		"ti,omap3-dpll-per-j-type-clock",
		"ti,omap4-dpll-clock",
		"ti,omap4-dpll-x2-clock",
		"ti,omap4-dpll-core-clock",
		"ti,omap4-dpll-m4xen-clock",
		"ti,omap4-dpll-j-type-clock",
		"ti,omap5-mpu-dpll-clock",
		"ti,am3-dpll-no-gate-clock",
		"ti,am3-dpll-j-type-clock",
		"ti,am3-dpll-no-gate-j-type-clock",
		"ti,am3-dpll-clock",
		"ti,am3-dpll-core-clock",
		"ti,am3-dpll-x2-clock",
		"ti,omap2-dpll-core-clock",

- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks, first entry lists reference clock
  and second entry bypass clock
- reg : offsets for the register set for controlling the DPLL.
  Registers are listed in following order:
	"control" - contains the control register base address
	"idlest" - contains the idle status register base address
	"mult-div1" - contains the multiplier / divider register base address
	"autoidle" - contains the autoidle register base address (optional)
	"ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
		       the frequency spreading register base address (optional)
	"ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
		        the modulation frequency register base address
			(optional)
  ti,am3-* dpll types do not have autoidle register
  ti,omap2-* dpll type does not support idlest / autoidle registers

Optional properties:
- DPLL mode setting - defining any one or more of the following overrides
  default setting.
	- ti,low-power-stop : DPLL supports low power stop mode, gating output
	- ti,low-power-bypass : DPLL output matches rate of parent bypass clock
	- ti,lock : DPLL locks in programmed rate
	- ti,min-div : the minimum divisor to start from to round the DPLL
		       target rate
	- ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
			  spreading in permille (10th of a percent)
	- ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
			      spectrum modulation frequency
	- ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
			      to enable the downspread feature

Examples:
	dpll_core_ck: dpll_core_ck@44e00490 {
		#clock-cells = <0>;
		compatible = "ti,omap4-dpll-core-clock";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x490>, <0x45c>, <0x488>, <0x468>;
	};

	dpll2_ck: dpll2_ck@48004004 {
		#clock-cells = <0>;
		compatible = "ti,omap3-dpll-clock";
		clocks = <&sys_ck>, <&dpll2_fck>;
		ti,low-power-stop;
		ti,low-power-bypass;
		ti,lock;
		reg = <0x4>, <0x24>, <0x34>, <0x40>;
	};

	dpll_core_ck: dpll_core_ck@44e00490 {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-core-clock";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x90>, <0x5c>, <0x68>;
	};

	dpll_ck: dpll_ck {
		#clock-cells = <0>;
		compatible = "ti,omap2-dpll-core-clock";
		clocks = <&sys_ck>, <&sys_ck>;
		reg = <0x0500>, <0x0540>;
	};

	dpll_disp_ck: dpll_disp_ck {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-no-gate-clock";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
	};


code:
Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.

The ATL IP is used to generate clock to be used to synchronize baseband and
audio codec. A single ATL IP provides four ATL clock instances sharing the same
functional clock but can be configured to provide different clocks.
ATL can maintain a clock averages to some desired frequency based on the bws/aws
signals - can compensate the drift between the two ws signal.

In order to provide the support for ATL and its output clocks (which can be used
internally within the SoC or external components) two sets of bindings is needed:

Clock tree binding:
This binding uses the common clock binding[1].
To be able to integrate the ATL clocks with DT clock tree.
Provides ccf level representation of the ATL clocks to be used by drivers.
Since the clock instances are part of a single IP this binding is used as a node
for the DT clock tree, the IP driver is needed to handle the actual configuration
of the IP.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be "ti,dra7-atl-clock"
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles to functional clock of ATL

Binding for the IP driver:
This binding is used to configure the IP driver which is going to handle the
configuration of the IP for the ATL clock instances.

Required properties:
- compatible : shall be "ti,dra7-atl"
- reg : base address for the ATL IP
- ti,provided-clocks : List of phandles to the clocks associated with the ATL
- clocks : link phandles to functional clock of ATL
- clock-names : Shall be set to "fck"
- ti,hwmods : Shall be set to "atl"

Optional properties:
Configuration of ATL instances:
- atl{0/1/2/3} {
	- bws : Baseband word select signal selection
	- aws : Audio word select signal selection
};

For valid word select signals, see the dt-bindings/clock/ti-dra7-atl.h include
file.

Examples:
/* clock bindings for atl provided clocks */
atl_clkin0_ck: atl_clkin0_ck {
	#clock-cells = <0>;
	compatible = "ti,dra7-atl-clock";
	clocks = <&atl_gfclk_mux>;
};

atl_clkin1_ck: atl_clkin1_ck {
	#clock-cells = <0>;
	compatible = "ti,dra7-atl-clock";
	clocks = <&atl_gfclk_mux>;
};

atl_clkin2_ck: atl_clkin2_ck {
	#clock-cells = <0>;
	compatible = "ti,dra7-atl-clock";
	clocks = <&atl_gfclk_mux>;
};

atl_clkin3_ck: atl_clkin3_ck {
	#clock-cells = <0>;
	compatible = "ti,dra7-atl-clock";
	clocks = <&atl_gfclk_mux>;
};

/* binding for the IP */
atl: atl@4843c000 {
	compatible = "ti,dra7-atl";
	reg = <0x4843c000 0x3ff>;
	ti,hwmods = "atl";
	ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
				<&atl_clkin2_ck>, <&atl_clkin3_ck>;
	clocks = <&atl_gfclk_mux>;
	clock-names = "fck";
};

#include <dt-bindings/clock/ti-dra7-atl.h>

&atl {

	atl2 {
		bws = <DRA7_ATL_WS_MCASP2_FSX>;
		aws = <DRA7_ATL_WS_MCASP3_FSX>;
	};
};


code:
Binding for Texas Instruments FAPLL clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1]. It assumes a
register-mapped FAPLL with usually two selectable input clocks
(reference clock and bypass clock), and one or more child
syntesizers.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be "ti,dm816-fapll-clock"
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
- reg : address and length of the register set for controlling the FAPLL.

Examples:
	main_fapll: main_fapll {
		#clock-cells = <1>;
		compatible = "ti,dm816-fapll-clock";
		reg = <0x400 0x40>;
		clocks = <&sys_clkin_ck &sys_clkin_ck>;
		clock-indices = <1>, <2>, <3>, <4>, <5>,
				<6>, <7>;
		clock-output-names = "main_pll_clk1",
				     "main_pll_clk2",
				     "main_pll_clk3",
				     "main_pll_clk4",
				     "main_pll_clk5",
				     "main_pll_clk6",
				     "main_pll_clk7";
	};


code:
Binding for TI fixed factor rate clock sources.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1], and also uses the autoidle
support from TI autoidle clock [2].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt

Required properties:
- compatible : shall be "ti,fixed-factor-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- ti,clock-div: fixed divider.
- ti,clock-mult: fixed multiplier.
- clocks: parent clock.

Optional properties:
- clock-output-names : from common clock binding.
- ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
  see [2]
- reg: offset for the autoidle register of this clock, see [2]
- ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0, see [2]
- ti,set-rate-parent: clk_set_rate is propagated to parent

Example:
	clock {
		compatible = "ti,fixed-factor-clock";
		clocks = <&parentclk>;
		#clock-cells = <0>;
		ti,clock-div = <2>;
		ti,clock-mult = <1>;
	};

	dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
		#clock-cells = <0>;
		compatible = "ti,fixed-factor-clock";
		clocks = <&dpll_usb_ck>;
		ti,clock-div = <1>;
		ti,autoidle-shift = <8>;
		reg = <0x01b4>;
		ti,clock-mult = <1>;
		ti,invert-autoidle-bit;
	};


code:
Binding for Texas Instruments gate clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1]. This clock is
quite much similar to the basic gate-clock [2], however,
it supports a number of additional features. If no register
is provided for this clock, the code assumes that a clockdomain
will be controlled instead and the corresponding hw-ops for
that is used.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt

Required properties:
- compatible : shall be one of:
  "ti,gate-clock" - basic gate clock
  "ti,wait-gate-clock" - gate clock which waits until clock is active before
			 returning from clk_enable()
  "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
  "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
  "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
			  clock directly from a clockdomain, see [3] how
			  to map clockdomains properly
  "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
			  required for a hardware errata
  "ti,composite-gate-clock" - composite gate clock, to be part of composite
			      clock
  "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
				      for clock to be active before returning
				      from clk_enable()
- #clock-cells : from common clock binding; shall be set to 0
- clocks : link to phandle of parent clock
- reg : offset for register controlling adjustable gate, not needed for
	ti,clkdm-gate-clock type

Optional properties:
- clock-output-names : from common clock binding.
- ti,bit-shift : bit shift for programming the clock gate, invalid for
		 ti,clkdm-gate-clock type
- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
  gates the clock and clearing the bit ungates the clock.

Examples:
	mmchs2_fck: mmchs2_fck@48004a00 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&core_96m_fck>;
		reg = <0x0a00>;
		ti,bit-shift = <25>;
	};

	uart4_fck_am35xx: uart4_fck_am35xx {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&core_48m_fck>;
		reg = <0x0a00>;
		ti,bit-shift = <23>;
	};

	dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
		#clock-cells = <0>;
		compatible = "ti,dss-gate-clock";
		clocks = <&dpll4_m4x2_ck>;
		reg = <0x0e00>;
		ti,bit-shift = <0>;
	};

	emac_ick: emac_ick@4800259c {
		#clock-cells = <0>;
		compatible = "ti,am35xx-gate-clock";
		clocks = <&ipss_ick>;
		reg = <0x059c>;
		ti,bit-shift = <1>;
	};

	emu_src_ck: emu_src_ck {
		#clock-cells = <0>;
		compatible = "ti,clkdm-gate-clock";
		clocks = <&emu_src_mux_ck>;
	};

	dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
		#clock-cells = <0>;
		compatible = "ti,hsdiv-gate-clock";
		clocks = <&dpll4_m2x2_mul_ck>;
		ti,bit-shift = <0x1b>;
		reg = <0x0d00>;
		ti,set-bit-to-disable;
	};

	vlynq_gate_fck: vlynq_gate_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-gate-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <3>;
		reg = <0x0200>;
	};

	sys_clkout2_src_gate: sys_clkout2_src_gate {
		#clock-cells = <0>;
		compatible = "ti,composite-no-wait-gate-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <15>;
		reg = <0x0070>;
	};


code:
Binding for Texas Instruments interface clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1]. This clock is
quite much similar to the basic gate-clock [2], however,
it supports a number of additional features, including
companion clock finding (match corresponding functional gate
clock) and hardware autoidle enable / disable.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml

Required properties:
- compatible : shall be one of:
  "ti,omap3-interface-clock" - basic OMAP3 interface clock
  "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
				       capability for waiting clock to be ready
  "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
					handling
  "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
  "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
  "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
  "ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
				  handling
- #clock-cells : from common clock binding; shall be set to 0
- clocks : link to phandle of parent clock
- reg : base address for the control register

Optional properties:
- clock-output-names : from common clock binding.
- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)

Examples:
	aes1_ick: aes1_ick@48004a14 {
		#clock-cells = <0>;
		compatible = "ti,omap3-interface-clock";
		clocks = <&security_l4_ick2>;
		reg = <0x48004a14 0x4>;
		ti,bit-shift = <3>;
	};

	cam_ick: cam_ick@48004f10 {
		#clock-cells = <0>;
		compatible = "ti,omap3-no-wait-interface-clock";
		clocks = <&l4_ick>;
		reg = <0x48004f10 0x4>;
		ti,bit-shift = <0>;
	};

	ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
		#clock-cells = <0>;
		compatible = "ti,omap3-ssi-interface-clock";
		clocks = <&ssi_l4_ick>;
		reg = <0x48004a10 0x4>;
		ti,bit-shift = <0>;
	};


code:
Binding for TI mux clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1].  It assumes a
register-mapped multiplexer with multiple input clock signals or
parents, one of which can be selected as output.  This clock does not
gate or adjust the parent rate via a divider or multiplier.

By default the "clocks" property lists the parents in the same order
as they are programmed into the regster.  E.g:

	clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;

results in programming the register as follows:

register value		selected parent clock
0			foo_clock
1			bar_clock
2			baz_clock

Some clock controller IPs do not allow a value of zero to be programmed
into the register, instead indexing begins at 1.  The optional property
"index-starts-at-one" modified the scheme as follows:

register value		selected clock parent
1			foo_clock
2			bar_clock
3			baz_clock

The binding must provide the register to control the mux. Optionally
the number of bits to shift the control field in the register can be
supplied. If the shift value is missing it is the same as supplying
a zero shift.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks
- reg : register offset for register controlling adjustable mux

Optional properties:
- clock-output-names : from common clock binding.
- ti,bit-shift : number of bits to shift the bit-mask, defaults to
  0 if not present
- ti,index-starts-at-one : valid input select programming starts at 1, not
  zero
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
  not supported by the composite-mux-clock subtype
- ti,latch-bit : latch the mux value to HW, only needed if the register
  access requires this. As an example, dra7x DPLL_GMAC H14 muxing
  implements such behavior.

Examples:

sys_clkin_ck: sys_clkin_ck@4a306110 {
	#clock-cells = <0>;
	compatible = "ti,mux-clock";
	clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
	reg = <0x0110>;
	ti,index-starts-at-one;
};

abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
	#clock-cells = <0>;
	compatible = "ti,mux-clock";
	clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
	ti,bit-shift = <24>;
	reg = <0x0108>;
};

mcbsp5_mux_fck: mcbsp5_mux_fck {
	#clock-cells = <0>;
	compatible = "ti,composite-mux-clock";
	clocks = <&core_96m_fck>, <&mcbsp_clks>;
	ti,bit-shift = <4>;
	reg = <0x02d8>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Binding for TI clksel clock

maintainers:
  - Tony Lindgren <tony@atomide.com>

description: |
  The TI CLKSEL clocks consist of consist of input clock mux bits, and in some
  cases also has divider, multiplier and gate bits.

properties:
  compatible:
    const: ti,clksel

  reg:
    maxItems: 1
    description: The CLKSEL register range

  '#address-cells':
    enum: [ 0, 1, 2 ]

  '#size-cells':
    enum: [ 0, 1, 2 ]

  ranges: true

  "#clock-cells":
    const: 2
    description: The CLKSEL register and bit offset

required:
  - compatible
  - reg
  - "#clock-cells"

additionalProperties:
  type: object

examples:
  - |
    clksel_gfx_fclk: clock@52c {
      compatible = "ti,clksel";
      reg = <0x25c 0x4>;
      #clock-cells = <2>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pipllct.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Toshiba Visconti5 TMPV770X PLL Controller

maintainers:
  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

description:
  Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X.

properties:
  compatible:
    const: toshiba,tmpv7708-pipllct

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  clocks:
    description: External reference clock (OSC2)
    maxItems: 1

required:
  - compatible
  - reg
  - "#clock-cells"
  - clocks

additionalProperties: false

examples:
  - |

    osc2_clk: osc2-clk {
      compatible = "fixed-clock";
      clock-frequency = <20000000>;
      #clock-cells = <0>;
    };

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pipllct: clock-controller@24220000 {
            compatible = "toshiba,tmpv7708-pipllct";
            reg = <0 0x24220000 0 0x820>;
            #clock-cells = <1>;
            clocks = <&osc2_clk>;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Toshiba Visconti5 TMPV770x SMU controller

maintainers:
  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

description:
  Toshia Visconti5 SMU (System Management Unit) which supports the clock
  and resets on TMPV770x.

properties:
  compatible:
    items:
      - const: toshiba,tmpv7708-pismu
      - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pismu: syscon@24200000 {
            compatible = "toshiba,tmpv7708-pismu", "syscon";
            reg = <0 0x24200000 0 0x2140>;
            #clock-cells = <1>;
            #reset-cells = <1>;
        };
    };
...


code:
* Clock bindings for Freescale Vybrid VF610 SOC

Required properties:
- compatible: Should be "fsl,vf610-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>

Optional properties:
- clocks: list of clock identifiers which are external input clocks to the
	given clock controller. Please refer the next section to find
	the input clocks for a given controller.
- clock-names: list of names of clocks which are exteral input clocks to the
	given clock controller.

Input clocks for top clock controller:
	- sxosc (external crystal oscillator 32KHz, recommended)
	- fxosc (external crystal oscillator 24MHz, recommended)
	- audio_ext
	- enet_ext

The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
for the full list of VF610 clock IDs.

Examples:

clks: ccm@4006b000 {
	compatible = "fsl,vf610-ccm";
	reg = <0x4006b000 0x1000>;
	#clock-cells = <1>;
	clocks = <&sxosc>, <&fxosc>;
	clock-names = "sxosc", "fxosc";
};

uart1: serial@40028000 {
	compatible = "fsl,vf610-uart";
	reg = <0x40028000 0x1000>;
	interrupts = <0 62 0x04>;
	clocks = <&clks VF610_CLK_UART1>;
	clock-names = "ipg";
};


code:
Device Tree Clock bindings for arch-vt8500

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be one of the following:
	"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
	"wm,wm8650-pll-clock" - for a WM8650 PLL clock
	"wm,wm8750-pll-clock" - for a WM8750 PLL clock
	"wm,wm8850-pll-clock" - for a WM8850 PLL clock
	"via,vt8500-device-clock" - for a VT/WM device clock

Required properties for PLL clocks:
- reg : shall be the control register offset from PMC base for the pll clock.
- clocks : shall be the input parent clock phandle for the clock. This should
	be the reference clock.
- #clock-cells : from common clock binding; shall be set to 0.

Required properties for device clocks:
- clocks : shall be the input parent clock phandle for the clock. This should
	be a pll output.
- #clock-cells : from common clock binding; shall be set to 0.

Device Clocks

Device clocks are required to have one or both of the following sets of
properties:

Gated device clocks:

Required properties:
- enable-reg : shall be the register offset from PMC base for the enable
	register.
- enable-bit : shall be the bit within enable-reg to enable/disable the clock.

Divisor device clocks:

Required property:
- divisor-reg : shall be the register offset from PMC base for the divisor
	register.
Optional property:
- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
	if not specified.

For example:

ref25: ref25M {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <25000000>;
};

plla: plla {
	#clock-cells = <0>;
	compatible = "wm,wm8650-pll-clock";
	clocks = <&ref25>;
	reg = <0x200>;
};

sdhc: sdhc {
	#clock-cells = <0>;
	compatible = "via,vt8500-device-clock";
	clocks = <&pllb>;
	divisor-reg = <0x328>;
	divisor-mask = <0x3f>;
	enable-reg = <0x254>;
	enable-bit = <18>;
};


code:
Device Tree Clock bindings for APM X-Gene

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be one of the following:
	"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
	"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
	"apm,xgene-pmd-clock" - for a X-Gene PMD clock
	"apm,xgene-device-clock" - for a X-Gene device clock
	"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
	"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock

Required properties for SoC or PCP PLL clocks:
- reg : shall be the physical PLL register address for the pll clock.
- clocks : shall be the input parent clock phandle for the clock. This should
	be the reference clock.
- #clock-cells : shall be set to 1.
- clock-output-names : shall be the name of the PLL referenced by derive
  clock.
Optional properties for PLL clocks:
- clock-names : shall be the name of the PLL. If missing, use the device name.

Required properties for PMD clocks:
- reg : shall be the physical register address for the pmd clock.
- clocks : shall be the input parent clock phandle for the clock.
- #clock-cells : shall be set to 1.
- clock-output-names : shall be the name of the clock referenced by derive
  clock.
Optional properties for PLL clocks:
- clock-names : shall be the name of the clock. If missing, use the device name.

Required properties for device clocks:
- reg : shall be a list of address and length pairs describing the CSR
         reset and/or the divider. Either may be omitted, but at least
         one must be present.
 - reg-names : shall be a string list describing the reg resource. This
               may include "csr-reg" and/or "div-reg". If this property
               is not present, the reg property is assumed to describe
               only "csr-reg".
- clocks : shall be the input parent clock phandle for the clock.
- #clock-cells : shall be set to 1.
- clock-output-names : shall be the name of the device referenced.
Optional properties for device clocks:
- clock-names : shall be the name of the device clock. If missing, use the
                device name.
- csr-offset : Offset to the CSR reset register from the reset address base.
               Default is 0.
- csr-mask : CSR reset mask bit. Default is 0xF.
- enable-offset : Offset to the enable register from the reset address base.
                  Default is 0x8.
- enable-mask : CSR enable mask bit. Default is 0xF.
- divider-offset : Offset to the divider CSR register from the divider base.
                   Default is 0x0.
- divider-width : Width of the divider register. Default is 0.
- divider-shift : Bit shift of the divider register. Default is 0.

For example:

	pcppll: pcppll@17000100 {
		compatible = "apm,xgene-pcppll-clock";
		#clock-cells = <1>;
		clocks = <&refclk 0>;
		clock-names = "pcppll";
		reg = <0x0 0x17000100 0x0 0x1000>;
		clock-output-names = "pcppll";
		type = <0>;
	};

	pmd0clk: pmd0clk@7e200200 {
		compatible = "apm,xgene-pmd-clock";
		#clock-cells = <1>;
		clocks = <&pmdpll 0>;
		reg = <0x0 0x7e200200 0x0 0x10>;
		clock-output-names = "pmd0clk";
	};

	socpll: socpll@17000120 {
		compatible = "apm,xgene-socpll-clock";
		#clock-cells = <1>;
		clocks = <&refclk 0>;
		clock-names = "socpll";
		reg = <0x0 0x17000120 0x0 0x1000>;
		clock-output-names = "socpll";
		type = <1>;
	};

	qmlclk: qmlclk {
		compatible = "apm,xgene-device-clock";
		#clock-cells = <1>;
		clocks = <&socplldiv2 0>;
		clock-names = "qmlclk";
		reg = <0x0 0x1703C000 0x0 0x1000>;
		reg-name = "csr-reg";
		clock-output-names = "qmlclk";
	};

	ethclk: ethclk {
		compatible = "apm,xgene-device-clock";
		#clock-cells = <1>;
		clocks = <&socplldiv2 0>;
		clock-names = "ethclk";
		reg = <0x0 0x17000000 0x0 0x1000>;
		reg-names = "div-reg";
		divider-offset = <0x238>;
		divider-width = <0x9>;
		divider-shift = <0x0>;
		clock-output-names = "ethclk";
	};

	apbclk: apbclk {
		compatible = "apm,xgene-device-clock";
		#clock-cells = <1>;
		clocks = <&ahbclk 0>;
		clock-names = "apbclk";
		reg = <0x0 0x1F2AC000 0x0 0x1000
			0x0 0x1F2AC000 0x0 0x1000>;
		reg-names = "csr-reg", "div-reg";
		csr-offset = <0x0>;
		csr-mask = <0x200>;
		enable-offset = <0x8>;
		enable-mask = <0x200>;
		divider-offset = <0x10>;
		divider-width = <0x2>;
		divider-shift = <0x0>;
		flags = <0x8>;
		clock-output-names = "apbclk";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Xilinx clocking wizard

maintainers:
  - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>

description:
  The clocking wizard is a soft ip clocking block of Xilinx versal. It
  reads required input clock frequencies from the devicetree and acts as clock
  clock output.

properties:
  compatible:
    enum:
      - xlnx,clocking-wizard
      - xlnx,clocking-wizard-v5.2
      - xlnx,clocking-wizard-v6.0

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  clocks:
    items:
      - description: clock input
      - description: axi clock

  clock-names:
    items:
      - const: clk_in1
      - const: s_axi_aclk

  xlnx,speed-grade:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2, 3]
    description:
      Speed grade of the device. Higher the speed grade faster is the FPGA device.

  xlnx,nr-outputs:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 8
    description:
      Number of outputs.

required:
  - compatible
  - reg
  - "#clock-cells"
  - clocks
  - clock-names
  - xlnx,speed-grade
  - xlnx,nr-outputs

additionalProperties: false

examples:
  - |
    clock-controller@b0000000  {
        compatible = "xlnx,clocking-wizard";
        reg = <0xb0000000 0x10000>;
        #clock-cells = <1>;
        xlnx,speed-grade = <1>;
        xlnx,nr-outputs = <6>;
        clock-names = "clk_in1", "s_axi_aclk";
        clocks = <&clkc 15>, <&clkc 15>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Versal clock controller

maintainers:
  - Michal Simek <michal.simek@xilinx.com>
  - Jolly Shah <jolly.shah@xilinx.com>
  - Rajan Vaja <rajan.vaja@xilinx.com>

description: |
  The clock controller is a hardware block of Xilinx versal clock tree. It
  reads required input clock frequencies from the devicetree and acts as clock
  provider for all clock consumers of PS clocks.

select: false

properties:
  compatible:
    const: xlnx,versal-clk

  "#clock-cells":
    const: 1

  clocks:
    description: List of clock specifiers which are external input
      clocks to the given clock controller.
    items:
      - description: reference clock
      - description: alternate reference clock
      - description: alternate reference clock for programmable logic

  clock-names:
    items:
      - const: ref
      - const: alt_ref
      - const: pl_alt_ref

required:
  - compatible
  - "#clock-cells"
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    firmware {
      zynqmp_firmware: zynqmp-firmware {
        compatible = "xlnx,zynqmp-firmware";
        method = "smc";
        versal_clk: clock-controller {
          #clock-cells = <1>;
          compatible = "xlnx,versal-clk";
          clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
          clock-names = "ref", "alt_ref", "pl_alt_ref";
        };
      };
    };
...


code:
--------------------------------------------------------------------------
Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
Zynq MPSoC firmware interface
--------------------------------------------------------------------------
The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
tree. It reads required input clock frequencies from the devicetree and acts
as clock provider for all clock consumers of PS clocks.

See clock_bindings.txt for more information on the generic clock bindings.

Required properties:
 - #clock-cells:	Must be 1
 - compatible:		Must contain:	"xlnx,zynqmp-clk"
 - clocks:		List of clock specifiers which are external input
			clocks to the given clock controller. Please refer
			the next section to find the input clocks for a
			given controller.
 - clock-names:		List of clock names which are exteral input clocks
			to the given clock controller. Please refer to the
			clock bindings for more details.

Input clocks for zynqmp Ultrascale+ clock controller:

The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
inputs. These required clock inputs are:
 - pss_ref_clk (PS reference clock)
 - video_clk (reference clock for video system )
 - pss_alt_ref_clk (alternative PS reference clock)
 - aux_ref_clk
 - gt_crx_ref_clk (transceiver reference clock)

The following strings are optional parameters to the 'clock-names' property in
order to provide an optional (E)MIO clock source:
 - swdt0_ext_clk
 - swdt1_ext_clk
 - gem0_emio_clk
 - gem1_emio_clk
 - gem2_emio_clk
 - gem3_emio_clk
 - mio_clk_XX		# with XX = 00..77
 - mio_clk_50_or_51	#for the mux clock to gem tsu from 50 or 51

Output clocks are registered based on clock information received
from firmware. Output clocks indexes are mentioned in
include/dt-bindings/clock/xlnx-zynqmp-clk.h.

-------
Example
-------

firmware {
	zynqmp_firmware: zynqmp-firmware {
		compatible = "xlnx,zynqmp-firmware";
		method = "smc";
		zynqmp_clk: clock-controller {
			#clock-cells = <1>;
			compatible = "xlnx,zynqmp-clk";
			clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
		};
	};
};


code:
Device Tree Clock bindings for the Zynq 7000 EPP

The Zynq EPP has several different clk providers, each with there own bindings.
The purpose of this document is to document their usage.

See clock_bindings.txt for more information on the generic clock bindings.
See Chapter 25 of Zynq TRM for more information about Zynq clocks.

== Clock Controller ==
The clock controller is a logical abstraction of Zynq's clock tree. It reads
required input clock frequencies from the devicetree and acts as clock provider
for all clock consumers of PS clocks.

Required properties:
 - #clock-cells : Must be 1
 - compatible : "xlnx,ps7-clkc"
 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
		      (usually 33 MHz oscillators are used for Zynq platforms)
 - clock-output-names : List of strings used to name the clock outputs. Shall be
			a list of the outputs given below.

Optional properties:
 - clocks : as described in the clock bindings
 - clock-names : as described in the clock bindings
 - fclk-enable : Bit mask to enable FCLKs statically at boot time.
		 Bit [0..3] correspond to FCLK0..FCLK3. The corresponding
		 FCLK will only be enabled if it is actually running at
		 boot time.

Clock inputs:
The following strings are optional parameters to the 'clock-names' property in
order to provide an optional (E)MIO clock source.
 - swdt_ext_clk
 - gem0_emio_clk
 - gem1_emio_clk
 - mio_clk_XX		# with XX = 00..53
...

Clock outputs:
 0:  armpll
 1:  ddrpll
 2:  iopll
 3:  cpu_6or4x
 4:  cpu_3or2x
 5:  cpu_2x
 6:  cpu_1x
 7:  ddr2x
 8:  ddr3x
 9:  dci
 10: lqspi
 11: smc
 12: pcap
 13: gem0
 14: gem1
 15: fclk0
 16: fclk1
 17: fclk2
 18: fclk3
 19: can0
 20: can1
 21: sdio0
 22: sdio1
 23: uart0
 24: uart1
 25: spi0
 26: spi1
 27: dma
 28: usb0_aper
 29: usb1_aper
 30: gem0_aper
 31: gem1_aper
 32: sdio0_aper
 33: sdio1_aper
 34: spi0_aper
 35: spi1_aper
 36: can0_aper
 37: can1_aper
 38: i2c0_aper
 39: i2c1_aper
 40: uart0_aper
 41: uart1_aper
 42: gpio_aper
 43: lqspi_aper
 44: smc_aper
 45: swdt
 46: dbg_trc
 47: dbg_apb

Example:
	clkc: clkc@100 {
		#clock-cells = <1>;
		compatible = "xlnx,ps7-clkc";
		ps-clk-frequency = <33333333>;
		reg = <0x100 0x100>;
		clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
				"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
				"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
				"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
				"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
				"dma", "usb0_aper", "usb1_aper", "gem0_aper",
				"gem1_aper", "sdio0_aper", "sdio1_aper",
				"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
				"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
				"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
				"dbg_trc", "dbg_apb";
		# optional props
		clocks = <&clkc 16>, <&clk_foo>;
		clock-names = "gem1_emio_clk", "can_mio_clk_23";
	};


code:
Common properties
=================

Endianness
----------

The Devicetree Specification does not define any properties related to hardware
byte swapping, but endianness issues show up frequently in porting drivers to
different machine types.  This document attempts to provide a consistent
way of handling byte swapping across drivers.

Optional properties:
 - big-endian: Boolean; force big endian register accesses
   unconditionally (e.g. ioread32be/iowrite32be).  Use this if you
   know the peripheral always needs to be accessed in big endian (BE) mode.
 - little-endian: Boolean; force little endian register accesses
   unconditionally (e.g. readl/writel).  Use this if you know the
   peripheral always needs to be accessed in little endian (LE) mode.
 - native-endian: Boolean; always use register accesses matched to the
   endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,
   BE vmlinux -> ioread32be/iowrite32be).  In this case no byte swaps
   will ever be performed.  Use this if the hardware "self-adjusts"
   register endianness based on the CPU's configured endianness.

If a binding supports these properties, then the binding should also
specify the default behavior if none of these properties are present.
In such cases, little-endian is the preferred default, but it is not
a requirement.  Some implementations assume that little-endian is
the default, because most existing (PCI-based) drivers implicitly
default to LE for their MMIO accesses.

Examples:
Scenario 1 : CPU in LE mode & device in LE mode.
dev: dev@40031000 {
	      compatible = "name";
	      reg = <0x40031000 0x1000>;
	      ...
	      native-endian;
};

Scenario 2 : CPU in LE mode & device in BE mode.
dev: dev@40031000 {
	      compatible = "name";
	      reg = <0x40031000 0x1000>;
	      ...
	      big-endian;
};

Scenario 3 : CPU in BE mode & device in BE mode.
dev: dev@40031000 {
	      compatible = "name";
	      reg = <0x40031000 0x1000>;
	      ...
	      native-endian;
};

Scenario 4 : CPU in BE mode & device in LE mode.
dev: dev@40031000 {
	      compatible = "name";
	      reg = <0x40031000 0x1000>;
	      ...
	      little-endian;
};

Daisy-chained devices
---------------------

Many serially-attached GPIO and IIO devices are daisy-chainable.  To the
host controller, a daisy-chain appears as a single device, but the number
of inputs and outputs it provides is the sum of inputs and outputs provided
by all of its devices.  The driver needs to know how many devices the
daisy-chain comprises to determine the amount of data exchanged, how many
inputs and outputs to register and so on.

Optional properties:
 - #daisy-chained-devices: Number of devices in the daisy-chain (default is 1).

Example:
gpio@0 {
	      compatible = "name";
	      reg = <0>;
	      gpio-controller;
	      #gpio-cells = <2>;
	      #daisy-chained-devices = <3>;
};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/connector/usb-connector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: USB Connector

maintainers:
  - Rob Herring <robh@kernel.org>

description:
  A USB connector node represents a physical USB connector. It should be a child
  of a USB interface controller or a separate node when it is attached to both
  MUX and USB interface controller.

properties:
  compatible:
    oneOf:
      - enum:
          - usb-a-connector
          - usb-b-connector
          - usb-c-connector

      - items:
          - const: gpio-usb-b-connector
          - const: usb-b-connector

      - items:
          - const: samsung,usb-connector-11pin
          - const: usb-b-connector

  label:
    description: Symbolic name for the connector.

  type:
    description: Size of the connector, should be specified in case of
      non-fullsize 'usb-a-connector' or 'usb-b-connector' compatible
      connectors.
    $ref: /schemas/types.yaml#/definitions/string

    enum:
      - mini
      - micro

  self-powered:
    description: Set this property if the USB device has its own power source.
    type: boolean

  # The following are optional properties for "usb-b-connector".
  id-gpios:
    description: An input gpio for USB ID pin.
    maxItems: 1

  vbus-gpios:
    description: An input gpio for USB VBus pin, used to detect presence of
      VBUS 5V.
    maxItems: 1

  vbus-supply:
    description: A phandle to the regulator for USB VBUS if needed when host
      mode or dual role mode is supported.
      Particularly, if use an output GPIO to control a VBUS regulator, should
      model it as a regulator. See bindings/regulator/fixed-regulator.yaml

  # The following are optional properties for "usb-c-connector".
  power-role:
    description: Determines the power role that the Type C connector will
      support. "dual" refers to Dual Role Port (DRP).
    $ref: /schemas/types.yaml#/definitions/string

    enum:
      - source
      - sink
      - dual

  try-power-role:
    description: Preferred power role.
    $ref: /schemas/types.yaml#/definitions/string

    enum:
      - source
      - sink
      - dual

  data-role:
    description: Data role if Type C connector supports USB data. "dual" refers
      Dual Role Device (DRD).
    $ref: /schemas/types.yaml#/definitions/string

    enum:
      - host
      - device
      - dual

  typec-power-opmode:
    description: Determines the power operation mode that the Type C connector
      will support and will advertise through CC pins when it has no power
      delivery support.
      - "default" corresponds to default USB voltage and current defined by the
        USB 2.0 and USB 3.2 specifications, 5V 500mA for USB 2.0 ports and
        5V 900mA or 1500mA for USB 3.2 ports in single-lane or dual-lane
        operation respectively.
      - "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB
        Type-C Cable and Connector specification, when Power Delivery is not
        supported.
    $ref: /schemas/types.yaml#/definitions/string
    enum:
      - default
      - 1.5A
      - 3.0A

  pd-disable:
    description: Set this property if the Type-C connector has no power delivery support.
    type: boolean

  # The following are optional properties for "usb-c-connector" with power
  # delivery support.
  source-pdos:
    description: An array of u32 with each entry providing supported power
      source data object(PDO), the detailed bit definitions of PDO can be found
      in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
      Source_Capabilities Message, the order of each entry(PDO) should follow
      the PD spec chapter 6.4.1. Required for power source and power dual role.
      User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO()
      defined in dt-bindings/usb/pd.h.
    minItems: 1
    maxItems: 7
    $ref: /schemas/types.yaml#/definitions/uint32-array

  sink-pdos:
    description: An array of u32 with each entry providing supported power sink
      data object(PDO), the detailed bit definitions of PDO can be found in
      "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
      Sink Capabilities Message, the order of each entry(PDO) should follow the
      PD spec chapter 6.4.1. Required for power sink and power dual role. User
      can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
      in dt-bindings/usb/pd.h.
    minItems: 1
    maxItems: 7
    $ref: /schemas/types.yaml#/definitions/uint32-array

  sink-vdos:
    description: An array of u32 with each entry, a Vendor Defined Message Object (VDO),
      providing additional information corresponding to the product, the detailed bit
      definitions and the order of each VDO can be found in
      "USB Power Delivery Specification Revision 3.0, Version 2.0 + ECNs 2020-12-10"
      chapter 6.4.4.3.1 Discover Identity. User can specify the VDO array via
      VDO_IDH/_CERT/_PRODUCT/_UFP/_DFP/_PCABLE/_ACABLE(1/2)/_VPD() defined in
      dt-bindings/usb/pd.h.
    minItems: 3
    maxItems: 6
    $ref: /schemas/types.yaml#/definitions/uint32-array

  sink-vdos-v1:
    description: An array of u32 with each entry, a Vendor Defined Message Object (VDO),
      providing additional information corresponding to the product, the detailed bit
      definitions and the order of each VDO can be found in
      "USB Power Delivery Specification Revision 2.0, Version 1.3" chapter 6.4.4.3.1 Discover
      Identity. User can specify the VDO array via VDO_IDH/_CERT/_PRODUCT/_CABLE/_AMA defined in
      dt-bindings/usb/pd.h.
    minItems: 3
    maxItems: 6
    $ref: /schemas/types.yaml#/definitions/uint32-array

  op-sink-microwatt:
    description: Sink required operating power in microwatt, if source can't
      offer the power, Capability Mismatch is set. Required for power sink and
      power dual role.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description: OF graph bindings modeling any data bus to the connector
      unless the bus is between parent node and the connector. Since a single
      connector can have multiple data buses every bus has an assigned OF graph
      port number as described below.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: High Speed (HS), present in all connectors.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Super Speed (SS), present in SS capable connectors.

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: Sideband Use (SBU), present in USB-C. This describes the
          alternate mode connection of which SBU is a part.

    required:
      - port@0

  new-source-frs-typec-current:
    description: Initial current capability of the new source when vSafe5V
      is applied during PD3.0 Fast Role Swap. "Table 6-14 Fixed Supply PDO - Sink"
      of "USB Power Delivery Specification Revision 3.0, Version 1.2" provides the
      different power levels and "6.4.1.3.1.6 Fast Role Swap USB Type-C Current"
      provides a detailed description of the field. The sink PDO from current source
      reflects the current source's(i.e. transmitter of the FRS signal) power
      requirement during fr swap. The current sink (i.e. receiver of the FRS signal),
      a.k.a new source, should check if it will be able to satisfy the current source's,
      new sink's, requirement during frswap before enabling the frs signal reception.
      This property refers to maximum current capability that the current sink can
      satisfy. During FRS, VBUS voltage is at 5V, as the partners are in implicit
      contract, hence, the power level is only a function of the current capability.
      "1" refers to default USB power level as described by "Table 6-14 Fixed Supply PDO - Sink".
      "2" refers to 1.5A@5V.
      "3" refers to 3.0A@5V.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2, 3]

  slow-charger-loop:
    description: Allows PMIC charger loops which are slow(i.e. cannot meet the 15ms deadline) to
      still comply to pSnkStby i.e Maximum power that can be consumed by sink while in Sink Standby
      state as defined in 7.4.2 Sink Electrical Parameters of USB Power Delivery Specification
      Revision 3.0, Version 1.2. When the property is set, the port requests pSnkStby(2.5W -
      5V@500mA) upon entering SNK_DISCOVERY(instead of 3A or the 1.5A, Rp current advertised, during
      SNK_DISCOVERY) and the actual currrent limit after reception of PS_Ready for PD link or during
      SNK_READY for non-pd link.
    type: boolean

dependencies:
  sink-vdos-v1: [ 'sink-vdos' ]
  sink-vdos: [ 'sink-vdos-v1' ]

required:
  - compatible

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: gpio-usb-b-connector
    then:
      anyOf:
        - required:
            - vbus-gpios
        - required:
            - id-gpios

  - if:
      properties:
        compatible:
          contains:
            const: samsung,usb-connector-11pin
    then:
      properties:
        type:
          const: micro

anyOf:
  - not:
      required:
        - typec-power-opmode
        - new-source-frs-typec-current

additionalProperties: true

examples:
  # Micro-USB connector with HS lines routed via controller (MUIC).
  - |
    muic-max77843 {
        usb_con1: connector {
            compatible = "usb-b-connector";
            label = "micro-USB";
            type = "micro";
        };
    };

  # USB-C connector attached to CC controller (s2mm005), HS lines routed
  # to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
  # DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
  - |
    ccic: s2mm005 {
        usb_con2: connector {
            compatible = "usb-c-connector";
            label = "USB-C";

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    usb_con_hs: endpoint {
                        remote-endpoint = <&max77865_usbc_hs>;
                    };
                };
                port@1 {
                    reg = <1>;
                    usb_con_ss: endpoint {
                        remote-endpoint = <&usbdrd_phy_ss>;
                    };
                };
                port@2 {
                    reg = <2>;
                    usb_con_sbu: endpoint {
                        remote-endpoint = <&dp_aux>;
                    };
                };
            };
        };
    };

  # USB-C connector attached to a typec port controller(ptn5110), which has
  # power delivery support and enables drp.
  - |
    #include <dt-bindings/usb/pd.h>
    typec: ptn5110 {
        usb_con3: connector {
            compatible = "usb-c-connector";
            label = "USB-C";
            power-role = "dual";
            try-power-role = "sink";
            source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
            sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
                         PDO_VAR(5000, 12000, 2000)>;
            op-sink-microwatt = <10000000>;
        };
    };

  # USB-C connector attached to SoC and USB3 typec port controller(hd3ss3220)
  # with SS 2:1 MUX. HS lines routed to SoC, SS lines routed to the MUX and
  # the output of MUX is connected to the SoC.
  - |
    connector {
        compatible = "usb-c-connector";
        label = "USB-C";
        data-role = "dual";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@0 {
                reg = <0>;
                hs_ep: endpoint {
                    remote-endpoint = <&usb3_hs_ep>;
                };
            };
            port@1 {
                reg = <1>;
                ss_ep: endpoint {
                    remote-endpoint = <&hd3ss3220_in_ep>;
                };
            };
        };
    };

  # USB connector with GPIO control lines
  - |
    #include <dt-bindings/gpio/gpio.h>

    usb {
        connector {
            compatible = "gpio-usb-b-connector", "usb-b-connector";
            type = "micro";
            id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
            vbus-supply = <&usb_p0_vbus>;
        };
    };

  # Micro-USB connector with HS lines routed via controller (MUIC) and MHL
  # lines connected to HDMI-MHL bridge (sii8620) on Samsung Exynos5433-based
  # mobile phone
  - |
    muic-max77843 {
        usb_con4: connector {
            compatible = "samsung,usb-connector-11pin", "usb-b-connector";
            label = "micro-USB";
            type = "micro";

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    muic_to_usb: endpoint {
                        remote-endpoint = <&usb_to_muic>;
                    };
                };
                port@3 {
                    reg = <3>;
                    usb_con_mhl: endpoint {
                        remote-endpoint = <&sii8620_mhl>;
                    };
                };
            };
        };
    };


code:
FlexTimer Quadrature decoder counter

This driver exposes a simple counter for the quadrature decoder mode.

Required properties:
- compatible:		Must be "fsl,ftm-quaddec".
- reg:			Must be set to the memory region of the flextimer.

Optional property:
- big-endian:		Access the device registers in big-endian mode.

Example:
		counter0: counter@29d0000 {
			compatible = "fsl,ftm-quaddec";
			reg = <0x0 0x29d0000 0x0 0x10000>;
			big-endian;
			status = "disabled";
		};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Interrupt counter

maintainers:
  - Oleksij Rempel <o.rempel@pengutronix.de>

description: |
  A generic interrupt counter to measure interrupt frequency. It was developed
  and used for agricultural devices to measure rotation speed of wheels or
  other tools. Since the direction of rotation is not important, only one
  signal line is needed.
  Interrupts or gpios are required. If both are defined, the interrupt will
  take precedence for counting interrupts.

properties:
  compatible:
    const: interrupt-counter

  interrupts:
    maxItems: 1

  gpios:
    maxItems: 1

required:
  - compatible

anyOf:
  - required: [ interrupts-extended ]
  - required: [ interrupts ]
  - required: [ gpios ]

additionalProperties: false

examples:
  - |

    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>

    counter-0 {
        compatible = "interrupt-counter";
        interrupts-extended = <&gpio 0 IRQ_TYPE_EDGE_RISING>;
    };

    counter-1 {
        compatible = "interrupt-counter";
        gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
    };

    counter-2 {
        compatible = "interrupt-counter";
        interrupts-extended = <&gpio 2 IRQ_TYPE_EDGE_RISING>;
        gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/counter/ti,am62-ecap-capture.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments Enhanced Capture (eCAP) Module

maintainers:
  - Julien Panis <jpanis@baylibre.com>

description: |
  The eCAP module resources can be used to capture timestamps
  on input signal events (falling/rising edges).

properties:
  compatible:
    const: ti,am62-ecap-capture

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: fck

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        capture@23100000 { /* eCAP in capture mode on am62x */
            compatible = "ti,am62-ecap-capture";
            reg = <0x00 0x23100000 0x00 0x100>;
            interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
            power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
            clocks = <&k3_clks 51 0>;
            clock-names = "fck";
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/counter/ti-eqep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP) Module

maintainers:
  - David Lechner <david@lechnology.com>

properties:
  compatible:
    const: ti,am3352-eqep

  reg:
    maxItems: 1

  interrupts:
    description: The eQEP event interrupt
    maxItems: 1

  clocks:
    description: The clock that determines the SYSCLKOUT rate for the eQEP
      peripheral.
    maxItems: 1

  clock-names:
    const: sysclkout

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    eqep0: counter@180 {
        compatible = "ti,am3352-eqep";
        reg = <0x180 0x80>;
        clocks = <&l4ls_gclk>;
        clock-names = "sysclkout";
        interrupts = <79>;
    };

...


code:
===========================================
CPU topology binding description
===========================================

===========================================
1 - Introduction
===========================================

In a SMP system, the hierarchy of CPUs is defined through three entities that
are used to describe the layout of physical CPUs in the system:

- socket
- cluster
- core
- thread

The bottom hierarchy level sits at core or thread level depending on whether
symmetric multi-threading (SMT) is supported or not.

For instance in a system where CPUs support SMT, "cpu" nodes represent all
threads existing in the system and map to the hierarchy level "thread" above.
In systems where SMT is not supported "cpu" nodes represent all cores present
in the system and map to the hierarchy level "core" above.

CPU topology bindings allow one to associate cpu nodes with hierarchical groups
corresponding to the system hierarchy; syntactically they are defined as device
tree nodes.

Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
used for any other architecture as well.

The cpu nodes, as per bindings defined in [4], represent the devices that
correspond to physical CPUs and are to be mapped to the hierarchy levels.

A topology description containing phandles to cpu nodes that are not compliant
with bindings standardized in [4] is therefore considered invalid.

===========================================
2 - cpu-map node
===========================================

The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
child of the cpus node and provides a container where the actual topology
nodes are listed.

- cpu-map node

	Usage: Optional - On SMP systems provide CPUs topology to the OS.
			  Uniprocessor systems do not require a topology
			  description and therefore should not define a
			  cpu-map node.

	Description: The cpu-map node is just a container node where its
		     subnodes describe the CPU topology.

	Node name must be "cpu-map".

	The cpu-map node's parent node must be the cpus node.

	The cpu-map node's child nodes can be:

	- one or more cluster nodes or
	- one or more socket nodes in a multi-socket system

	Any other configuration is considered invalid.

The cpu-map node can only contain 4 types of child nodes:

- socket node
- cluster node
- core node
- thread node

whose bindings are described in paragraph 3.

The nodes describing the CPU topology (socket/cluster/core/thread) can
only be defined within the cpu-map node and every core/thread in the
system must be defined within the topology.  Any other configuration is
invalid and therefore must be ignored.

===========================================
2.1 - cpu-map child nodes naming convention
===========================================

cpu-map child nodes must follow a naming convention where the node name
must be "socketN", "clusterN", "coreN", "threadN" depending on the node type
(ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
which are siblings within a single common parent node must be given a unique and
sequential N value, starting from 0).
cpu-map child nodes which do not share a common parent node can have the same
name (ie same number N as other cpu-map child nodes at different device tree
levels) since name uniqueness will be guaranteed by the device tree hierarchy.

===========================================
3 - socket/cluster/core/thread node bindings
===========================================

Bindings for socket/cluster/cpu/thread nodes are defined as follows:

- socket node

	 Description: must be declared within a cpu-map node, one node
		      per physical socket in the system. A system can
		      contain single or multiple physical socket.
		      The association of sockets and NUMA nodes is beyond
		      the scope of this bindings, please refer [2] for
		      NUMA bindings.

	This node is optional for a single socket system.

	The socket node name must be "socketN" as described in 2.1 above.
	A socket node can not be a leaf node.

	A socket node's child nodes must be one or more cluster nodes.

	Any other configuration is considered invalid.

- cluster node

	 Description: must be declared within a cpu-map node, one node
		      per cluster. A system can contain several layers of
		      clustering within a single physical socket and cluster
		      nodes can be contained in parent cluster nodes.

	The cluster node name must be "clusterN" as described in 2.1 above.
	A cluster node can not be a leaf node.

	A cluster node's child nodes must be:

	- one or more cluster nodes; or
	- one or more core nodes

	Any other configuration is considered invalid.

- core node

	Description: must be declared in a cluster node, one node per core in
		     the cluster. If the system does not support SMT, core
		     nodes are leaf nodes, otherwise they become containers of
		     thread nodes.

	The core node name must be "coreN" as described in 2.1 above.

	A core node must be a leaf node if SMT is not supported.

	Properties for core nodes that are leaf nodes:

	- cpu
		Usage: required
		Value type: <phandle>
		Definition: a phandle to the cpu node that corresponds to the
			    core node.

	If a core node is not a leaf node (CPUs supporting SMT) a core node's
	child nodes can be:

	- one or more thread nodes

	Any other configuration is considered invalid.

- thread node

	Description: must be declared in a core node, one node per thread
		     in the core if the system supports SMT. Thread nodes are
		     always leaf nodes in the device tree.

	The thread node name must be "threadN" as described in 2.1 above.

	A thread node must be a leaf node.

	A thread node must contain the following property:

	- cpu
		Usage: required
		Value type: <phandle>
		Definition: a phandle to the cpu node that corresponds to
			    the thread node.

===========================================
4 - Example dts
===========================================

Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters in a single
physical socket):

cpus {
	#size-cells = <0>;
	#address-cells = <2>;

	cpu-map {
		socket0 {
			cluster0 {
				cluster0 {
					core0 {
						thread0 {
							cpu = <&CPU0>;
						};
						thread1 {
							cpu = <&CPU1>;
						};
					};

					core1 {
						thread0 {
							cpu = <&CPU2>;
						};
						thread1 {
							cpu = <&CPU3>;
						};
					};
				};

				cluster1 {
					core0 {
						thread0 {
							cpu = <&CPU4>;
						};
						thread1 {
							cpu = <&CPU5>;
						};
					};

					core1 {
						thread0 {
							cpu = <&CPU6>;
						};
						thread1 {
							cpu = <&CPU7>;
						};
					};
				};
			};

			cluster1 {
				cluster0 {
					core0 {
						thread0 {
							cpu = <&CPU8>;
						};
						thread1 {
							cpu = <&CPU9>;
						};
					};
					core1 {
						thread0 {
							cpu = <&CPU10>;
						};
						thread1 {
							cpu = <&CPU11>;
						};
					};
				};

				cluster1 {
					core0 {
						thread0 {
							cpu = <&CPU12>;
						};
						thread1 {
							cpu = <&CPU13>;
						};
					};
					core1 {
						thread0 {
							cpu = <&CPU14>;
						};
						thread1 {
							cpu = <&CPU15>;
						};
					};
				};
			};
		};
	};

	CPU0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x0>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x1>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU2: cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x100>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU3: cpu@101 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x101>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU4: cpu@10000 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x10000>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU5: cpu@10001 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x10001>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU6: cpu@10100 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x10100>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU7: cpu@10101 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0 0x10101>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU8: cpu@100000000 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x0>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU9: cpu@100000001 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x1>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU10: cpu@100000100 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x100>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU11: cpu@100000101 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x101>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU12: cpu@100010000 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x10000>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU13: cpu@100010001 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x10001>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU14: cpu@100010100 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x10100>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};

	CPU15: cpu@100010101 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1 0x10101>;
		enable-method = "spin-table";
		cpu-release-addr = <0 0x20000000>;
	};
};

Example 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT):

cpus {
	#size-cells = <0>;
	#address-cells = <1>;

	cpu-map {
		cluster0 {
			core0 {
				cpu = <&CPU0>;
			};
			core1 {
				cpu = <&CPU1>;
			};
			core2 {
				cpu = <&CPU2>;
			};
			core3 {
				cpu = <&CPU3>;
			};
		};

		cluster1 {
			core0 {
				cpu = <&CPU4>;
			};
			core1 {
				cpu = <&CPU5>;
			};
			core2 {
				cpu = <&CPU6>;
			};
			core3 {
				cpu = <&CPU7>;
			};
		};
	};

	CPU0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a15";
		reg = <0x0>;
	};

	CPU1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a15";
		reg = <0x1>;
	};

	CPU2: cpu@2 {
		device_type = "cpu";
		compatible = "arm,cortex-a15";
		reg = <0x2>;
	};

	CPU3: cpu@3 {
		device_type = "cpu";
		compatible = "arm,cortex-a15";
		reg = <0x3>;
	};

	CPU4: cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a7";
		reg = <0x100>;
	};

	CPU5: cpu@101 {
		device_type = "cpu";
		compatible = "arm,cortex-a7";
		reg = <0x101>;
	};

	CPU6: cpu@102 {
		device_type = "cpu";
		compatible = "arm,cortex-a7";
		reg = <0x102>;
	};

	CPU7: cpu@103 {
		device_type = "cpu";
		compatible = "arm,cortex-a7";
		reg = <0x103>;
	};
};

Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system)

{
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "sifive,fu540g", "sifive,fu500";
	model = "sifive,hifive-unleashed-a00";

	...
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu-map {
			socket0 {
				cluster0 {
					core0 {
						cpu = <&CPU1>;
					};
					core1 {
						cpu = <&CPU2>;
					};
					core2 {
						cpu0 = <&CPU2>;
					};
					core3 {
						cpu0 = <&CPU3>;
					};
				};
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "sifive,rocket0", "riscv";
			reg = <0x1>;
		}

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "sifive,rocket0", "riscv";
			reg = <0x2>;
		}
		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "sifive,rocket0", "riscv";
			reg = <0x3>;
		}
		CPU4: cpu@4 {
			device_type = "cpu";
			compatible = "sifive,rocket0", "riscv";
			reg = <0x4>;
		}
	}
};
===============================================================================
[1] ARM Linux kernel documentation
    Documentation/devicetree/bindings/arm/cpus.yaml
[2] Devicetree NUMA binding description
    Documentation/devicetree/bindings/numa.txt
[3] RISC-V Linux kernel documentation
    Documentation/devicetree/bindings/riscv/cpus.yaml
[4] https://www.devicetree.org/specifications/