code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2019 Phytec Messtechnik GmbH
 * Author: Teresa Remmet <t.remmet@phytec.de>
 *
 */

/ {
	model = "Phytec AM335x phyBOARD-REGOR";
	compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx";

	vcc3v3: fixedregulator@1 {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
	};

	/* User IO */
	user_leds: user_leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&user_leds_pins>;

		run_stop-led {
			gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "gpio";
			default-state = "off";
		};

		error-led {
			gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "gpio";
			default-state = "off";
		};
	};
};

/* User Leds */
&am33xx_pinmux {
	user_leds_pins: pinmux_user_leds {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* lcd_hsync.gpio2_22 */
			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* mcasp0_fsx.gpio3_15 */
		>;
	};
};

/* CAN Busses */
&am33xx_pinmux {
	dcan1_pins: pinmux_dcan1 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2)	/* uart0_ctsn.d_can1_tx */
			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2)	/* uart0_rtsn.d_can1_rx */
		>;
	};
};

&dcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan1_pins>;
	status = "okay";
};

/* Ethernet */
&am33xx_pinmux {
	ethernet1_pins: pinmux_ethernet1 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a0.mii2_txen */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a1.mii2_rxdv */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a2.mii2_txd3 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a3.mii2_txd2 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a4.mii2_txd1 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a5.mii2_txd0 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a6.mii2_txclk */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a7.mii2_rxclk */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a8.mii2_rxd3 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1)	 /* gpmc_a9.mii2_rxd2 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a10.mii2_rxd1 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a11.mii2_rxd0 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_wpn.mii2_rxerr */
			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_ben1.mii2_col */
		>;
	};
};

&cpsw_port2 {
	status = "okay";
	phy-handle = <&phy1>;
	phy-mode = "mii";
	ti,dual-emac-pvid = <2>;
};

&davinci_mdio_sw {
	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&mac_sw {
	pinctrl-names = "default";
	pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
};

/* GPIOs */
&am33xx_pinmux {
	pinctrl-names = "default";
	pinctrl-0 = <&user_gpios_pins>;

	user_gpios_pins: pinmux_user_gpios {
		pinctrl-single,pins = <
			/* DIGIN 1-4 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7)		/* gpmc_ad11.gpio0_27 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7)		/* gpmc_ad10.gpio0_26 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7)		/* gpmc_ad9.gpio0_23 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7)		/* gpmc_ad8.gpio0_22 */
			/* DIGOUT 1-4 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7)		/* gpmc_ad15.gpio1_15 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7)		/* gpmc_ad14.gpio1_14 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7)		/* gpmc_ad13.gpio1_13 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7)		/* gpmc_ad12.gpio1_12 */
		>;
	};
};

/* MMC */
&am33xx_pinmux {
	mmc1_pins: pinmux_mmc1 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)	/* spi0_cs1.mmc0_sdcd */
		>;
	};
};

&mmc1 {
	vmmc-supply = <&vcc3v3>;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
	status = "okay";
};

/* RTC */
&i2c_rtc {
	status = "okay";
};

/* UARTs */
&am33xx_pinmux {
	uart0_pins: pinmux_uart0 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
		>;
	};

	uart2_pins: pinmux_uart2 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_tx_clk.uart2_rxd */
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_rx_clk.uart2_txd */
		>;
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
	status = "okay";
};

/* RS485 - UART1 */
&am33xx_pinmux {
	uart1_rs485_pins: pinmux_uart1_rs485_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0)
		>;
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_rs485_pins>;
	status = "okay";
	linux,rs485-enabled-at-boot-time;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 */

&am33xx_pinmux {
	cpsw_default: cpsw_default {
		pinctrl-single,pins = <
			/* Slave 1 */
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
		>;
	};

	cpsw_sleep: cpsw_sleep {
		pinctrl-single,pins = <
			/* Slave 1 reset value */
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
		>;
	};

	usb_hub_ctrl: usb_hub_ctrl {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)     /* rmii1_refclk.gpio0_29 */
		>;
	};
};

&mac_sw {
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
};

&cpsw_port1 {
	phy-mode = "rgmii-id";
};

&i2c0 {
	usb2512b: usb-hub@2c {
		pinctrl-names = "default";
		pinctrl-0 = <&usb_hub_ctrl>;
		compatible = "microchip,usb2512b";
		reg = <0x2c>;
		reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2021 Sancloud Ltd
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 */
/dts-v1/;

#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
#include "am335x-boneblack-common.dtsi"
#include "am335x-sancloud-bbe-common.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "SanCloud BeagleBone Enhanced Extended WiFi";
	compatible = "sancloud,am335x-boneenhanced",
		     "ti,am335x-bone-black",
		     "ti,am335x-bone",
		     "ti,am33xx";

	wlan_en_reg: fixedregulator@2 {
		compatible = "regulator-fixed";
		regulator-name = "wlan-en-regulator";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		startup-delay-us = <100000>;
	};
};

&am33xx_pinmux {
	mmc3_pins: pinmux_mmc3_pins {
		pinctrl-single,pins = <
			/* gpmc_a9.gpio1_25: RADIO_EN */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_OUTPUT_PULLUP, MUX_MODE7)

			/* gpmc_ad12.mmc2_dat0 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3)

			/* gpmc_ad13.mmc2_dat1 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3)

			/* gpmc_ad14.mmc2_dat2 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3)

			/* gpmc_ad15.mmc2_dat3 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3)

			/* gpmc_csn3.mmc2_cmd */
			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)

			/* gpmc_clk.mmc2_clk */
			AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)
		>;
	};

	bluetooth_pins: pinmux_bluetooth_pins {
		pinctrl-single,pins = <
			/* event_intr0.gpio0_19 */
			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE7)
		>;
	};

	uart1_pins: pinmux_uart1_pins {
		pinctrl-single,pins = <
			/* uart1_rxd */
			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)

			/* uart1_txd */
			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)

			/* uart1_ctsn */
			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)

			/* uart1_rtsn */
			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
		>;
	};
};

&i2c2 {
	status = "disabled";
};

&mmc3 {
	status = "okay";
	vmmc-supply = <&wlan_en_reg>;
	bus-width = <4>;
	non-removable;
	cap-power-off-card;
	ti,needs-special-hs-handling;
	keep-power-in-suspend;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc3_pins>;
	dmas = <&edma_xbar 12 0 1
		&edma_xbar 13 0 2>;
	dma-names = "tx", "rx";
	clock-frequency = <50000000>;
	max-frequency = <50000000>;
};

&uart1 {
	status = "okay";

	bluetooth {
		pinctrl-names = "default";
		pinctrl-0 = <&uart1_pins &bluetooth_pins>;
		compatible = "qcom,qca6174-bt";
		enable-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
		clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>;
		interrupt-parent = <&gpio0>;
		interrupts = <19 IRQ_TYPE_EDGE_RISING>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 * Copyright (C) 2021 SanCloud Ltd
 */
/dts-v1/;

#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
#include "am335x-boneblack-common.dtsi"
#include "am335x-sancloud-bbe-common.dtsi"

/ {
	model = "SanCloud BeagleBone Enhanced Lite";
	compatible = "sancloud,am335x-boneenhanced",
		     "ti,am335x-bone-black",
		     "ti,am335x-bone",
		     "ti,am33xx";
};

&am33xx_pinmux {
	bb_spi0_pins: pinmux_bb_spi0_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0)
		>;
	};
};

&spi0 {
	#address-cells = <1>;
	#size-cells = <0>;

	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&bb_spi0_pins>;

	channel@0 {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "micron,spi-authenta";

		reg = <0>;
		spi-max-frequency = <16000000>;
		spi-cpha;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 */
/dts-v1/;

#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
#include "am335x-boneblack-common.dtsi"
#include "am335x-boneblack-hdmi.dtsi"
#include "am335x-sancloud-bbe-common.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "SanCloud BeagleBone Enhanced";
	compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
};

&am33xx_pinmux {
	mpu6050_pins: pinmux_mpu6050_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7)    /* uart0_ctsn.gpio1_8 */
		>;
	};

	lps3331ap_pins: pinmux_lps3331ap_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)     /* gpmc_a10.gpio1_26 */
		>;
	};
};

&i2c0 {
	lps331ap: barometer@5c {
		pinctrl-names = "default";
		pinctrl-0 = <&lps3331ap_pins>;
		compatible = "st,lps331ap-press";
		st,drdy-int-pin = <1>;
		reg = <0x5c>;
		interrupt-parent = <&gpio1>;
		interrupts = <26 IRQ_TYPE_EDGE_RISING>;
	};

	mpu6050: accelerometer@68 {
		pinctrl-names = "default";
		pinctrl-0 = <&mpu6050_pins>;
		compatible = "invensense,mpu6050";
		reg = <0x68>;
		interrupt-parent = <&gpio0>;
		interrupts = <2 IRQ_TYPE_EDGE_RISING>;
		orientation = <0xff 0 0 0 1 0 0 0 0xff>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335
 *
 * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/
 */

#include "am335x-cm-t335.dts"

/ {
	model = "CompuLab CM-T335 on SB-T335";
	compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx";

	/* DRM display driver */
	panel {
		compatible = "ti,tilcdc,panel";
		status = "okay";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&lcd_pins_default>;
		pinctrl-1 = <&lcd_pins_sleep>;

		panel-info {
			ac-bias           = <255>;
			ac-bias-intrpt    = <0>;
			dma-burst-sz      = <16>;
			bpp               = <32>;
			fdd               = <0x80>;
			sync-edge         = <0>;
			sync-ctrl         = <1>;
			raster-order      = <0>;
			fifo-th           = <0>;
		};
		display-timings {
			/* Timing selection performed by U-Boot */
			timing0: lcd {/* 800x480p62 */
				clock-frequency = <30000000>;
				hactive = <800>;
				vactive = <480>;
				hfront-porch = <39>;
				hback-porch = <39>;
				hsync-len = <47>;
				vback-porch = <29>;
				vfront-porch = <13>;
				vsync-len = <2>;
				hsync-active = <1>;
				vsync-active = <1>;
			};
			timing1: dvi { /* 1024x768p60 */
				clock-frequency = <65000000>;
				hactive = <1024>;
				hfront-porch = <24>;
				hback-porch = <160>;
				hsync-len = <136>;
				vactive = <768>;
				vfront-porch = <3>;
				vback-porch = <29>;
				vsync-len = <6>;
				hsync-active = <0>;
				vsync-active = <0>;
			};
		};
	};
};

&am33xx_pinmux {
	/* Display */
	lcd_pins_default: lcd_pins_default {
		pinctrl-single,pins = <
			/* gpmc_ad8.lcd_data23 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)
			/* gpmc_ad9.lcd_data22 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)
			/* gpmc_ad10.lcd_data21 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)
			/* gpmc_ad11.lcd_data20 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)
			/* gpmc_ad12.lcd_data19 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)
			/* gpmc_ad13.lcd_data18 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)
			/* gpmc_ad14.lcd_data17 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)
			/* gpmc_ad15.lcd_data16 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
		>;
	};

	lcd_pins_sleep: lcd_pins_sleep {
		pinctrl-single,pins = <
			/* gpmc_ad8.lcd_data23 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7)
			/* gpmc_ad9.lcd_data22 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7)
			/* gpmc_ad10.lcd_data21 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7)
			/* gpmc_ad11.lcd_data20 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)
			/* gpmc_ad12.lcd_data19 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)
			/* gpmc_ad13.lcd_data18 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)
			/* gpmc_ad14.lcd_data17 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)
			/* gpmc_ad15.lcd_data16 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
		>;
	};
};

&i2c0 {
	/* GPIO extender */
	gpio_ext: pca9555@26 {
		compatible = "nxp,pca9555";
		pinctrl-names = "default";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x26>;
		dvi-ena-hog {
			gpio-hog;
			gpios = <13 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "dvi-enable";
		};
		lcd-ena-hog {
			gpio-hog;
			gpios = <11 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "lcd-enable";
		};
	};
};

/* Display */
&lcdc {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * support for the bosch am335x based shc c3 board
 *
 * Copyright, C) 2015 Heiko Schocher <hs@denx.de>
 *
 */
/dts-v1/;

#include "am33xx.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Bosch SHC";
	compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx";

	aliases {
		mmcblk0 = &mmc1;
		mmcblk1 = &mmc2;
	};

	cpus {
		cpu@0 {
			/*
			 * To consider voltage drop between PMIC and SoC,
			 * tolerance value is reduced to 2% from 4% and
			 * voltage value is increased as a precaution.
			 */
			operating-points = <
				/* kHz    uV */
				594000  1225000
				294000  1125000
			>;
			voltage-tolerance = <2>; /* 2 percentage */
			cpu0-supply = <&dcdc2_reg>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		back-button {
			label = "Back Button";
			gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_BACK>;
			debounce-interval = <1000>;
			wakeup-source;
		};

		front-button {
			label = "Front Button";
			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_FRONT>;
			debounce-interval = <1000>;
			wakeup-source;
		};
	};

	leds {
		pinctrl-names = "default";
		pinctrl-0 = <&user_leds_s0>;

		compatible = "gpio-leds";

		led1 {
			label = "shc:power:red";
			gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led2 {
			label = "shc:power:bl";
			gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "timer";
			default-state = "on";
		};

		led3 {
			label = "shc:lan:red";
			gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led4 {
			label = "shc:lan:bl";
			gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led5 {
			label = "shc:cloud:red";
			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led6 {
			label = "shc:cloud:bl";
			gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>; /* 512 MB */
	};

	vmmcsd_fixed: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "vmmcsd_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&aes {
	status = "okay";
};

&epwmss1 {
	status = "okay";

	ehrpwm1: pwm@200 {
		pinctrl-names = "default";
		pinctrl-0 = <&ehrpwm1_pins>;
		status = "okay";
	};
};

&gpio1 {
	hmtc-rst-hog {
		gpio-hog;
		gpios = <24 GPIO_ACTIVE_LOW>;
		output-high;
		line-name = "homematic_reset";
	};

	hmtc-prog-hog {
		gpio-hog;
		gpios = <27 GPIO_ACTIVE_LOW>;
		output-high;
		line-name = "homematic_program";
	};
};

&gpio3 {
	zgb-rst-hog {
		gpio-hog;
		gpios = <18 GPIO_ACTIVE_LOW>;
		output-low;
		line-name = "zigbee_reset";
	};

	zgb-boot-hog {
		gpio-hog;
		gpios = <19 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "zigbee_boot";
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "okay";
	clock-frequency = <400000>;

	tps: tps@24 {
		reg = <0x24>;
	};

	at24@50 {
		compatible = "atmel,24c32";
		pagesize = <32>;
		reg = <0x50>;
	};

	pcf8563@51 {
		compatible = "nxp,pcf8563";
		reg = <0x51>;
	};
};

&mac_sw {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	status = "okay";
};

&cpsw_port1 {
	phy-mode = "mii";
	phy-handle = <&ethernetphy0>;
	ti,dual-emac-pvid = <1>;
};

&cpsw_port2 {
	status = "disabled";
};

&davinci_mdio_sw {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;

	ethernetphy0: ethernet-phy@0 {
		reg = <0>;
		smsc,disable-energy-detect;
	};
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	bus-width = <0x4>;
	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
	cd-inverted;
	max-frequency = <26000000>;
	vmmc-supply = <&vmmcsd_fixed>;
	status = "okay";
};

&mmc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_pins>;
	bus-width = <8>;
	max-frequency = <26000000>;
	sd-uhs-sdr25;
	vmmc-supply = <&vmmcsd_fixed>;
	status = "okay";
};

&mmc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc3_pins>;
	bus-width = <4>;
	cap-power-off-card;
	max-frequency = <26000000>;
	sd-uhs-sdr25;
	vmmc-supply = <&vmmcsd_fixed>;
	status = "okay";
};

&rtc {
	ti,no-init;
};

&sham {
	status = "okay";
};

&tps {
	compatible = "ti,tps65217";
	ti,pmic-shutdown-controller;

	regulators {
		#address-cells = <1>;
		#size-cells = <0>;

		dcdc1_reg: regulator@0 {
			reg = <0>;
			regulator-name = "vdds_dpr";
			regulator-compatible = "dcdc1";
			regulator-min-microvolt = <1300000>;
			regulator-max-microvolt = <1450000>;
			regulator-boot-on;
			regulator-always-on;
		};

		dcdc2_reg: regulator@1 {
			reg = <1>;
			/*
			 * VDD_MPU voltage limits 0.95V - 1.26V with
			 * +/-4% tolerance
			 */
			regulator-compatible = "dcdc2";
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <925000>;
			regulator-max-microvolt = <1375000>;
			regulator-boot-on;
			regulator-always-on;
			regulator-ramp-delay = <70000>;
		};

		dcdc3_reg: regulator@2 {
			reg = <2>;
			/*
			 * VDD_CORE voltage limits 0.95V - 1.1V with
			 * +/-4% tolerance
			 */
			regulator-name = "vdd_core";
			regulator-compatible = "dcdc3";
			regulator-min-microvolt = <925000>;
			regulator-max-microvolt = <1125000>;
			regulator-boot-on;
			regulator-always-on;
		};

		ldo1_reg: regulator@3 {
			reg = <3>;
			regulator-name = "vio,vrtc,vdds";
			regulator-compatible = "ldo1";
			regulator-min-microvolt = <1000000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
		};

		ldo2_reg: regulator@4 {
			reg = <4>;
			regulator-name = "vdd_3v3aux";
			regulator-compatible = "ldo2";
			regulator-min-microvolt = <900000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		ldo3_reg: regulator@5 {
			reg = <5>;
			regulator-name = "vdd_1v8";
			regulator-compatible = "ldo3";
			regulator-min-microvolt = <900000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
		};

		ldo4_reg: regulator@6 {
			reg = <6>;
			regulator-name = "vdd_3v3a";
			regulator-compatible = "ldo4";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins>;
	status = "okay";
};

&usb1 {
	dr_mode = "host";
};

&am33xx_pinmux {
	pinctrl-names = "default";
	pinctrl-0 = <&clkout2_pin>;

	clkout2_pin: pinmux_clkout2_pin {
		pinctrl-single,pins = <
			/* xdma_event_intr1.clkout2 */
			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6)
		>;
	};

	cpsw_default: cpsw_default {
		pinctrl-single,pins = <
			/* Slave 1 */
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
		>;
	};

	cpsw_sleep: cpsw_sleep {
		pinctrl-single,pins = <
			/* Slave 1 reset value */
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
		>;
	};

	davinci_mdio_default: davinci_mdio_default {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
		>;
	};

	davinci_mdio_sleep: davinci_mdio_sleep {
		pinctrl-single,pins = <
			/* MDIO reset value */
			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
		>;
	};

	ehrpwm1_pins: pinmux_ehrpwm1 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */
		>;
	};

	emmc_pins: pinmux_emmc_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2)
			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)
		>;
	};

	i2c0_pins: pinmux_i2c0_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
		>;
	};

	mmc1_pins: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5)
		>;
	};

	mmc3_pins: pinmux_mmc3_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3)
			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3)
			AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3)
		>;
	};

	uart0_pins: pinmux_uart0_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0)
		>;
	};

	uart1_pins: pinmux_uart1 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
		>;
	};

	uart2_pins: pinmux_uart2_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)
			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)
		>;
	};

	uart4_pins: pinmux_uart4_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)
			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6)
		>;
	};

	user_leds_s0: user_leds_s0 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7)
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/
 */
/dts-v1/;

#include "am33xx.dtsi"
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "Toby Churchill SL50 Series";
	compatible = "tcl,am335x-sl50", "ti,am33xx";

	cpus {
		cpu@0 {
			cpu0-supply = <&dcdc2_reg>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>; /* 512 MB */
	};

	chosen {
		stdout-path = &uart0;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&led_pins>;

		led0 {
			label = "sl50:red:usr0";
			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led1 {
			label = "sl50:green:usr1";
			gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led2 {
			label = "sl50:red:usr2";
			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led3 {
			label = "sl50:green:usr3";
			gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};

	backlight0: disp0 {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&backlight0_pins>;
		pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>;
		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <50>;
		enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
		power-supply = <&vdd_sys_reg>;
	};

	backlight1: disp1 {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&backlight1_pins>;
		pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>;
		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <50>;
		enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
		power-supply = <&vdd_sys_reg>;
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		/* audio external oscillator */
		audio_mclk_fixed: oscillator@0 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency  = <24576000>;	/* 24.576MHz */
		};

		audio_mclk: audio_mclk_gate@0 {
			compatible = "gpio-gate-clock";
			#clock-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&audio_mclk_pins>;
			clocks = <&audio_mclk_fixed>;
			enable-gpios = <&gpio1 27 0>;
		};
	};

	panel: lcd_panel {
		compatible = "ti,tilcdc,panel";
		pinctrl-names = "default";
		pinctrl-0 = <&lcd_pins>;

		panel-info {
			ac-bias = <255>;
			ac-bias-intrpt = <0>;
			dma-burst-sz = <16>;
			bpp = <16>;
			fdd = <0x80>;
			tft-alt-mode = <0>;
			mono-8bit-mode = <0>;
			sync-edge = <0>;
			sync-ctrl = <1>;
			raster-order = <0>;
			fifo-th = <0>;
		};

		display-timings {
			native-mode = <&timing0>;
			timing0: 960x128 {
				clock-frequency = <18000000>;
				hactive = <960>;
				vactive = <272>;

				hback-porch = <40>;
				hfront-porch = <16>;
				hsync-len = <24>;
				hsync-active = <0>;

				vback-porch = <3>;
				vfront-porch = <8>;
				vsync-len = <4>;
				vsync-active = <0>;
			};
		};
	};

	sound {
		compatible = "audio-graph-card";
		label = "sound-card";
		pinctrl-names = "default";
		pinctrl-0 = <&audio_pa_pins>;

		widgets = "Headphone", "Headphone Jack",
			  "Speaker", "Speaker External",
			  "Line", "Line In",
			  "Microphone", "Microphone Jack";

		routing = "Headphone Jack",	"HPLOUT",
			  "Headphone Jack",	"HPROUT",
			  "Amplifier",		"MONO_LOUT",
			  "Speaker External",	"Amplifier",
			  "LINE1R",		"Line In",
			  "LINE1L",		"Line In",
			  "MIC3L",		"Microphone Jack",
			  "MIC3R",		"Microphone Jack",
			  "Microphone Jack",	"Mic Bias";

		dais = <&cpu_port>;

		pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
	};

	emmc_pwrseq: pwrseq@0 {
		compatible = "mmc-pwrseq-emmc";
		pinctrl-names = "default";
		pinctrl-0 = <&emmc_pwrseq_pins>;
		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
	};

	vdd_sys_reg: regulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "vdd_sys_reg";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
	};

	vmmcsd_fixed: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "vmmcsd_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&am33xx_pinmux {
	pinctrl-names = "default";
	pinctrl-0 = <&lwb_pins>;

	audio_pins: pinmux_audio_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
		>;
	};

	audio_pa_pins: pinmux_audio_pa_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* SoundPA_en - mcasp0_aclkr.gpio3_18 */
		>;
	};

	audio_mclk_pins: pinmux_audio_mclk_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a11.gpio1_27 */
		>;
	};

	backlight0_pins: pinmux_backlight0_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7)	/* gpmc_wen.gpio2_4 */
		>;
	};

	backlight1_pins: pinmux_backlight1_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7)     /* gpmc_ad10.gpio0_26 */
		>;
	};

	lcd_pins: pinmux_lcd_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
		>;
	};

	led_pins: pinmux_led_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)	/* gpmc_a5.gpio1_21 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)	/* gpmc_a6.gpio1_22 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)	/* gpmc_a7.gpio1_23 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)	/* gpmc_a8.gpio1_24 */
		>;
	};

	uart0_pins: pinmux_uart0_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
		>;
	};

	uart1_pins: pinmux_uart1_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
		>;
	};

	uart4_pins: pinmux_uart4_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)	/* gpmc_wait0.uart4_rxd */
			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)	/* gpmc_wpn.uart4_txd */
		>;
	};

	i2c0_pins: pinmux_i2c0_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
		>;
	};

	i2c2_pins: pinmux_i2c2_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* uart1_ctsn.i2c2_sda */
			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* uart1_rtsn.i2c2_scl */
		>;
	};

	cpsw_default: cpsw_default {
		pinctrl-single,pins = <
			/* Slave 1 */
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0)
		>;
	};

	cpsw_sleep: cpsw_sleep {
		pinctrl-single,pins = <
			/* Slave 1 reset value */
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
		>;
	};

	davinci_mdio_default: davinci_mdio_default {
		pinctrl-single,pins = <
			/* MDIO */
			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
			/* Ethernet */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7)	/* Ethernet_nRST - gpmc_ad14.gpio1_14 */
		>;
	};

	davinci_mdio_sleep: davinci_mdio_sleep {
		pinctrl-single,pins = <
			/* MDIO reset value */
			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
		>;
	};

	mmc1_pins: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7)		/* uart0_rtsn.gpio1_9 */
		>;
	};

	emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* gpmc_a4.gpio1_20 */
		>;
	};

	emmc_pins: pinmux_emmc_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)	/* gpmc_csn1.mmc1_clk */
			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)	/* gpmc_csn2.mmc1_cmd */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad0.mmc1_dat0 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad1.mmc1_dat1 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad2.mmc1_dat2 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad3.mmc1_dat3 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad4.mmc1_dat4 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) 	/* gpmc_ad5.mmc1_dat5 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad6.mmc1_dat6 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad7.mmc1_dat7 */
		>;
	};

	ehrpwm1_pins: pinmux_ehrpwm1a_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6)	/* gpmc_a2.ehrpwm1a */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6)	/* gpmc_a3.ehrpwm1b */
		>;
	};

	rtc0_irq_pins: pinmux_rtc0_irq_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7)     /* gpmc_ad9.gpio0_23 */
		>;
	};

	spi0_pins: pinmux_spi0_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)	/* SPI0_MOSI */
			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)	/* SPI0_MISO */
			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)	/* SPI0_CS0 (NBATTSS) */
			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0)	/* SPI0_CS1 (FPGA_FLASH_NCS) */
		>;
	};

	lwb_pins: pinmux_lwb_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7)	/* nKbdInt - gpmc_ad12.gpio1_12 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7)	/* nKbdReset - gpmc_ad13.gpio1_13 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7)	/* USB1_enPower - gpmc_a1.gpio1_17 */
			/* PDI Bus - Battery system */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7)	/* nBattReset  gpmc_a0.gpio1_16 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7)	/* BattPDIData gpmc_ad15.gpio1_15 */
			/* FPGA */
			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE7)	/* FPGA_DONE - gpmc_ad8.gpio0_22 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7)	/* FPGA_NRST - gpmc_a0.gpio1_16 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* FPGA_RUN - gpmc_a1.gpio1_17 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7)	/* ENFPGA - gpmc_a9.gpio1_25 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* FPGA_PROGRAM - gpmc_a10.gpio1_26 */
		>;
	};
};

&i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;

	clock-frequency = <400000>;

	tps: tps@24 {
		reg = <0x24>;
	};

	rtc0: rtc@68 {
		compatible = "dallas,ds1339";
		pinctrl-names = "default";
		pinctrl-0 = <&rtc0_irq_pins>;
		interrupt-parent = <&gpio0>;
		interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */
		wakeup-source;
		trickle-resistor-ohms = <2000>;
		reg = <0x68>;
	};

	eeprom: eeprom@50 {
		compatible = "atmel,24c256";
		reg = <0x50>;
	};

	gpio_exp: mcp23017@20 {
		compatible = "microchip,mcp23017";
		reg = <0x20>;
	};

};

&i2c2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;

	clock-frequency = <400000>;

	audio_codec: tlv320aic3106@1b {
		status = "okay";
		compatible = "ti,tlv320aic3106";
		#sound-dai-cells = <0>;
		reg = <0x1b>;
		ai3x-micbias-vg = <2>;  /* 2.5V */

		AVDD-supply = <&ldo4_reg>;
		IOVDD-supply = <&ldo4_reg>;
		DRVDD-supply = <&ldo4_reg>;
		DVDD-supply = <&ldo3_reg>;

		codec_port: port {
			codec_endpoint: endpoint {
				remote-endpoint = <&cpu_endpoint>;
				clocks = <&audio_mclk>;
			};
		};
	};

	/* Ambient Light Sensor */
	als: isl29023@44 {
		compatible = "isil,isl29023";
		reg = <0x44>;
	};
};

&rtc {
	status = "disabled";
};

&usb0 {
	dr_mode = "otg";
};

&usb1 {
	dr_mode = "host";
};

&mmc1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	bus-width = <4>;
	cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&vmmcsd_fixed>;
};

&mmc2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_pins>;
	bus-width = <8>;
	vmmc-supply = <&vmmcsd_fixed>;
	mmc-pwrseq = <&emmc_pwrseq>;
};

&mcasp0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&audio_pins>;
	#sound-dai-cells = <0>;
	op-mode = <0>;  /* MCASP_ISS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
		0 0 1 2
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;

	cpu_port: port {
		cpu_endpoint: endpoint {
			remote-endpoint = <&codec_endpoint>;

			dai-format = "dsp_b";
			bitclock-master = <&codec_port>;
			frame-master = <&codec_port>;
			bitclock-inversion;
			clocks = <&audio_mclk>;
		};
	};
};

&uart0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
};

&uart1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
};

&uart4 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins>;
};

&spi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins>;

	flash: flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q032";
		reg = <1>;
		spi-max-frequency = <5000000>;
	};
};

#include "tps65217.dtsi"

&tps {
	ti,pmic-shutdown-controller;

	interrupt-parent = <&intc>;
	interrupts = <7>;	/* NNMI */

	regulators {
		dcdc1_reg: regulator@0 {
			/* VDDS_DDR */
			regulator-min-microvolt = <1500000>;
			regulator-max-microvolt = <1500000>;
			regulator-always-on;
		};

		dcdc2_reg: regulator@1 {
			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <925000>;
			regulator-max-microvolt = <1325000>;
			regulator-boot-on;
			regulator-always-on;
		};

		dcdc3_reg: regulator@2 {
			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
			regulator-name = "vdd_core";
			regulator-min-microvolt = <925000>;
			regulator-max-microvolt = <1150000>;
			regulator-boot-on;
			regulator-always-on;
		};

		ldo1_reg: regulator@3 {
			/* VRTC / VIO / VDDS*/
			regulator-always-on;
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};

		ldo2_reg: regulator@4 {
			/* VDD_3V3AUX */
			regulator-always-on;
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};

		ldo3_reg: regulator@5 {
			/* VDD_1V8 */
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
		};

		ldo4_reg: regulator@6 {
			/* VDD_3V3A */
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};
};

&cpsw_port1 {
	phy-mode = "mii";
	phy-handle = <&ethphy0>;
	ti,dual-emac-pvid = <1>;
};

&cpsw_port2 {
	status = "disabled";
};

&mac_sw {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
};

&davinci_mdio_sw {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
	reset-delay-us = <100>;   /* PHY datasheet states 100us min */

	ethphy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&sham {
	status = "okay";
};

&aes {
	status = "okay";
};

&epwmss1 {
	status = "okay";
};

&ehrpwm1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&ehrpwm1_pins>;
};

&lcdc {
	status = "okay";
};

&tscadc {
	status = "okay";
};

&am335x_adc {
	ti,adc-channels = <0 1 2 3 4 5 6 7>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 Phytec Messtechnik GmbH
 * Author: Teresa Remmet <t.remmet@phytec.de>
 */

/dts-v1/;

#include "am335x-phycore-som.dtsi"
#include "am335x-wega.dtsi"

/* SoM */
&gpmc {
	status = "okay";
};

&i2c_eeprom {
	status = "okay";
};

&i2c_rtc {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 Phytec Messtechnik GmbH
 * Author: Teresa Remmet <t.remmet@phytec.de>
 */

/ {
	model = "Phytec AM335x phyBOARD-WEGA";
	compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";

	sound: sound_iface {
		compatible = "ti,da830-evm-audio";
	};

	vcc3v3: fixedregulator1 {
		compatible = "regulator-fixed";
		regulator-name = "vcc3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
	};
};

/* Audio */
&am33xx_pinmux {
	mcasp0_pins: pinmux_mcasp0 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
		>;
	};
};

&i2c0 {
	tlv320aic3007: tlv320aic3007@18 {
		compatible = "ti,tlv320aic3007";
		reg = <0x18>;
		AVDD-supply = <&vcc3v3>;
		IOVDD-supply = <&vcc3v3>;
		DRVDD-supply = <&vcc3v3>;
		DVDD-supply = <&vdig1_reg>;
		status = "okay";
	};
};

&mcasp0 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcasp0_pins>;
	op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
	tdm-slots = <2>;
	serial-dir = <
		2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */
	>;
	tx-num-evt = <16>;
	rx-num-evt = <16>;
	status = "okay";
};

&sound {
	ti,model = "AM335x-Wega";
	ti,audio-codec = <&tlv320aic3007>;
	ti,mcasp-controller = <&mcasp0>;
	ti,audio-routing =
		"Line Out",		"LLOUT",
		"Line Out",		"RLOUT",
		"LINE1L",		"Line In",
		"LINE1R",		"Line In";
	clocks = <&mcasp0_fck>;
	clock-names = "mclk";
	status = "okay";
};

/* CAN Busses */
&am33xx_pinmux {
	dcan1_pins: pinmux_dcan1 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
		>;
	};
};

&dcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan1_pins>;
	status = "okay";
};

/* Ethernet */
&am33xx_pinmux {
	ethernet1_pins: pinmux_ethernet1 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a0.mii2_txen */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a1.mii2_rxdv */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a2.mii2_txd3 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a3.mii2_txd2 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a4.mii2_txd1 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)		/* gpmc_a5.mii2_txd0 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a6.mii2_txclk */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a7.mii2_rxclk */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a8.mii2_rxd3 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a9.mii2_rxd2 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a10.mii2_rxd1 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_a11.mii2_rxd0 */
			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_wpn.mii2_rxerr */
			AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1)	/* gpmc_ben1.mii2_col */
		>;
	};
};

&cpsw_port2 {
	status = "okay";
	phy-handle = <&phy1>;
	phy-mode = "mii";
	ti,dual-emac-pvid = <2>;
};

&davinci_mdio_sw {
	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&mac_sw {
	pinctrl-names = "default";
	pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
};

/* MMC */
&am33xx_pinmux {
	mmc1_pins: pinmux_mmc1 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)	/* spi0_cs1.mmc0_sdcd */
		>;
	};
};

&mmc1 {
	vmmc-supply = <&vcc3v3>;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;
	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
	status = "okay";
};

/* Power */
&vdig1_reg {
	regulator-boot-on;
	regulator-always-on;
};

/* UARTs */
&am33xx_pinmux {
	uart0_pins: pinmux_uart0 {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
		>;
	};

	uart1_pins: pinmux_uart1_pins {
		pinctrl-single,pins = <
			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
		>;
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	status = "okay";
};

&usb1 {
	dr_mode = "host";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for AM33xx clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 */
&scm_clocks {
	sys_clkin_ck: clock-sys-clkin-22@40 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "sys_clkin_ck";
		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
		ti,bit-shift = <22>;
		reg = <0x0040>;
	};

	adc_tsc_fck: clock-adc-tsc-fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "adc_tsc_fck";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dcan0_fck: clock-dcan0-fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "dcan0_fck";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dcan1_fck: clock-dcan1-fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "dcan1_fck";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	mcasp0_fck: clock-mcasp0-fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "mcasp0_fck";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	mcasp1_fck: clock-mcasp1-fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "mcasp1_fck";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	smartreflex0_fck: clock-smartreflex0-fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "smartreflex0_fck";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	smartreflex1_fck: clock-smartreflex1-fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "smartreflex1_fck";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	sha0_fck: clock-sha0-fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "sha0_fck";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	aes0_fck: clock-aes0-fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "aes0_fck";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	rng_fck: clock-rng-fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "rng_fck";
		clocks = <&sys_clkin_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	clock@664 {
		compatible = "ti,clksel";
		reg = <0x664>;
		#clock-cells = <2>;
		#address-cells = <0>;

		ehrpwm0_tbclk: clock-ehrpwm0-tbclk {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "ehrpwm0_tbclk";
			clocks = <&l4ls_gclk>;
			ti,bit-shift = <0>;
		};

		ehrpwm1_tbclk: clock-ehrpwm1-tbclk {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "ehrpwm1_tbclk";
			clocks = <&l4ls_gclk>;
			ti,bit-shift = <1>;
		};

		ehrpwm2_tbclk: clock-ehrpwm2-tbclk {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "ehrpwm2_tbclk";
			clocks = <&l4ls_gclk>;
			ti,bit-shift = <2>;
		};
	};
};
&prcm_clocks {
	clk_32768_ck: clock-clk-32768 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "clk_32768_ck";
		clock-frequency = <32768>;
	};

	clk_rc32k_ck: clock-clk-rc32k {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "clk_rc32k_ck";
		clock-frequency = <32000>;
	};

	virt_19200000_ck: clock-virt-19200000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_19200000_ck";
		clock-frequency = <19200000>;
	};

	virt_24000000_ck: clock-virt-24000000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_24000000_ck";
		clock-frequency = <24000000>;
	};

	virt_25000000_ck: clock-virt-25000000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_25000000_ck";
		clock-frequency = <25000000>;
	};

	virt_26000000_ck: clock-virt-26000000 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "virt_26000000_ck";
		clock-frequency = <26000000>;
	};

	tclkin_ck: clock-tclkin {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-output-names = "tclkin_ck";
		clock-frequency = <12000000>;
	};

	dpll_core_ck: clock@490 {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-core-clock";
		clock-output-names = "dpll_core_ck";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
	};

	dpll_core_x2_ck: clock-dpll-core-x2 {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-x2-clock";
		clock-output-names = "dpll_core_x2_ck";
		clocks = <&dpll_core_ck>;
	};

	dpll_core_m4_ck: clock-dpll-core-m4@480 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_m4_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <31>;
		reg = <0x0480>;
		ti,index-starts-at-one;
	};

	dpll_core_m5_ck: clock-dpll-core-m5@484 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_m5_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <31>;
		reg = <0x0484>;
		ti,index-starts-at-one;
	};

	dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_core_m6_ck";
		clocks = <&dpll_core_x2_ck>;
		ti,max-div = <31>;
		reg = <0x04d8>;
		ti,index-starts-at-one;
	};

	dpll_mpu_ck: clock@488 {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-clock";
		clock-output-names = "dpll_mpu_ck";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
	};

	dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_mpu_m2_ck";
		clocks = <&dpll_mpu_ck>;
		ti,max-div = <31>;
		reg = <0x04a8>;
		ti,index-starts-at-one;
	};

	dpll_ddr_ck: clock@494 {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-no-gate-clock";
		clock-output-names = "dpll_ddr_ck";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
	};

	dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_ddr_m2_ck";
		clocks = <&dpll_ddr_ck>;
		ti,max-div = <31>;
		reg = <0x04a0>;
		ti,index-starts-at-one;
	};

	dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "dpll_ddr_m2_div2_ck";
		clocks = <&dpll_ddr_m2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	dpll_disp_ck: clock@498 {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-no-gate-clock";
		clock-output-names = "dpll_disp_ck";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
	};

	dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_disp_m2_ck";
		clocks = <&dpll_disp_ck>;
		ti,max-div = <31>;
		reg = <0x04a4>;
		ti,index-starts-at-one;
		ti,set-rate-parent;
	};

	dpll_per_ck: clock@48c {
		#clock-cells = <0>;
		compatible = "ti,am3-dpll-no-gate-j-type-clock";
		clock-output-names = "dpll_per_ck";
		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
		reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
	};

	dpll_per_m2_ck: clock-dpll-per-m2@4ac {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clock-output-names = "dpll_per_m2_ck";
		clocks = <&dpll_per_ck>;
		ti,max-div = <31>;
		reg = <0x04ac>;
		ti,index-starts-at-one;
	};

	dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
		clocks = <&dpll_per_m2_ck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "dpll_per_m2_div4_ck";
		clocks = <&dpll_per_m2_ck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	clk_24mhz: clock-clk-24mhz {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "clk_24mhz";
		clocks = <&dpll_per_m2_ck>;
		clock-mult = <1>;
		clock-div = <8>;
	};

	clkdiv32k_ck: clock-clkdiv32k {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "clkdiv32k_ck";
		clocks = <&clk_24mhz>;
		clock-mult = <1>;
		clock-div = <732>;
	};

	l3_gclk: clock-l3-gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "l3_gclk";
		clocks = <&dpll_core_m4_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "pruss_ocp_gclk";
		clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
		reg = <0x0530>;
	};

	mmu_fck: clock-mmu-fck-1@914 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "mmu_fck";
		clocks = <&dpll_core_m4_ck>;
		ti,bit-shift = <1>;
		reg = <0x0914>;
	};

	timer1_fck: clock-timer1-fck@528 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "timer1_fck";
		clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
		reg = <0x0528>;
	};

	timer2_fck: clock-timer2-fck@508 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "timer2_fck";
		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x0508>;
	};

	timer3_fck: clock-timer3-fck@50c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "timer3_fck";
		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x050c>;
	};

	timer4_fck: clock-timer4-fck@510 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "timer4_fck";
		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x0510>;
	};

	timer5_fck: clock-timer5-fck@518 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "timer5_fck";
		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x0518>;
	};

	timer6_fck: clock-timer6-fck@51c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "timer6_fck";
		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x051c>;
	};

	timer7_fck: clock-timer7-fck@504 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "timer7_fck";
		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x0504>;
	};

	usbotg_fck: clock-usbotg-fck-8@47c {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "usbotg_fck";
		clocks = <&dpll_per_ck>;
		ti,bit-shift = <8>;
		reg = <0x047c>;
	};

	dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "dpll_core_m4_div2_ck";
		clocks = <&dpll_core_m4_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	ieee5000_fck: clock-ieee5000-fck-1@e4 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clock-output-names = "ieee5000_fck";
		clocks = <&dpll_core_m4_div2_ck>;
		ti,bit-shift = <1>;
		reg = <0x00e4>;
	};

	wdt1_fck: clock-wdt1-fck@538 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "wdt1_fck";
		clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x0538>;
	};

	l4_rtc_gclk: clock-l4-rtc-gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "l4_rtc_gclk";
		clocks = <&dpll_core_m4_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	l4hs_gclk: clock-l4hs-gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "l4hs_gclk";
		clocks = <&dpll_core_m4_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	l3s_gclk: clock-l3s-gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "l3s_gclk";
		clocks = <&dpll_core_m4_div2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	l4fw_gclk: clock-l4fw-gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "l4fw_gclk";
		clocks = <&dpll_core_m4_div2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	l4ls_gclk: clock-l4ls-gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "l4ls_gclk";
		clocks = <&dpll_core_m4_div2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	sysclk_div_ck: clock-sysclk-div {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "sysclk_div_ck";
		clocks = <&dpll_core_m4_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "cpsw_125mhz_gclk";
		clocks = <&dpll_core_m5_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "cpsw_cpts_rft_clk";
		clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
		reg = <0x0520>;
	};

	gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "gpio0_dbclk_mux_ck";
		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
		reg = <0x053c>;
	};

	lcd_gclk: clock-lcd-gclk@534 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clock-output-names = "lcd_gclk";
		clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
		reg = <0x0534>;
		ti,set-rate-parent;
	};

	mmc_clk: clock-mmc {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-output-names = "mmc_clk";
		clocks = <&dpll_per_m2_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	clock@52c {
		compatible = "ti,clksel";
		reg = <0x52c>;
		#clock-cells = <2>;
		#address-cells = <0>;

		gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
			#clock-cells = <0>;
			compatible = "ti,mux-clock";
			clock-output-names = "gfx_fclk_clksel_ck";
			clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
			ti,bit-shift = <1>;
		};

		gfx_fck_div_ck: clock-gfx-fck-div {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "gfx_fck_div_ck";
			clocks = <&gfx_fclk_clksel_ck>;
			ti,max-div = <2>;
		};
	};

	clock@700 {
		compatible = "ti,clksel";
		reg = <0x700>;
		#clock-cells = <2>;
		#address-cells = <0>;

		sysclkout_pre_ck: clock-sysclkout-pre {
			#clock-cells = <0>;
			compatible = "ti,mux-clock";
			clock-output-names = "sysclkout_pre_ck";
			clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
		};

		clkout2_div_ck: clock-clkout2-div {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "clkout2_div_ck";
			clocks = <&sysclkout_pre_ck>;
			ti,bit-shift = <3>;
			ti,max-div = <8>;
		};

		clkout2_ck: clock-clkout2 {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "clkout2_ck";
			clocks = <&clkout2_div_ck>;
			ti,bit-shift = <7>;
		};
	};
};

&prcm {
	per_cm: clock@0 {
		compatible = "ti,omap4-cm";
		clock-output-names = "per_cm";
		reg = <0x0 0x400>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x0 0x400>;

		l4ls_clkctrl: clock@38 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4ls_clkctrl";
			reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
			#clock-cells = <2>;
		};

		l3s_clkctrl: clock@1c {
			compatible = "ti,clkctrl";
			clock-output-names = "l3s_clkctrl";
			reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
			#clock-cells = <2>;
		};

		l3_clkctrl: clock@24 {
			compatible = "ti,clkctrl";
			clock-output-names = "l3_clkctrl";
			reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
			#clock-cells = <2>;
		};

		l4hs_clkctrl: clock@120 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4hs_clkctrl";
			reg = <0x120 0x4>;
			#clock-cells = <2>;
		};

		pruss_ocp_clkctrl: clock@e8 {
			compatible = "ti,clkctrl";
			clock-output-names = "pruss_ocp_clkctrl";
			reg = <0xe8 0x4>;
			#clock-cells = <2>;
		};

		cpsw_125mhz_clkctrl: clock@0 {
			compatible = "ti,clkctrl";
			clock-output-names = "cpsw_125mhz_clkctrl";
			reg = <0x0 0x18>;
			#clock-cells = <2>;
		};

		lcdc_clkctrl: clock@18 {
			compatible = "ti,clkctrl";
			clock-output-names = "lcdc_clkctrl";
			reg = <0x18 0x4>;
			#clock-cells = <2>;
		};

		clk_24mhz_clkctrl: clock@14c {
			compatible = "ti,clkctrl";
			clock-output-names = "clk_24mhz_clkctrl";
			reg = <0x14c 0x4>;
			#clock-cells = <2>;
		};
	};

	wkup_cm: clock@400 {
		compatible = "ti,omap4-cm";
		clock-output-names = "wkup_cm";
		reg = <0x400 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x400 0x100>;

		l4_wkup_clkctrl: clock@0 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4_wkup_clkctrl";
			reg = <0x0 0x10>, <0xb4 0x24>;
			#clock-cells = <2>;
		};

		l3_aon_clkctrl: clock@14 {
			compatible = "ti,clkctrl";
			clock-output-names = "l3_aon_clkctrl";
			reg = <0x14 0x4>;
			#clock-cells = <2>;
		};

		l4_wkup_aon_clkctrl: clock@b0 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4_wkup_aon_clkctrl";
			reg = <0xb0 0x4>;
			#clock-cells = <2>;
		};
	};

	mpu_cm: clock@600 {
		compatible = "ti,omap4-cm";
		clock-output-names = "mpu_cm";
		reg = <0x600 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x600 0x100>;

		mpu_clkctrl: clock@0 {
			compatible = "ti,clkctrl";
			clock-output-names = "mpu_clkctrl";
			reg = <0x0 0x8>;
			#clock-cells = <2>;
		};
	};

	l4_rtc_cm: clock@800 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l4_rtc_cm";
		reg = <0x800 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x800 0x100>;

		l4_rtc_clkctrl: clock@0 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4_rtc_clkctrl";
			reg = <0x0 0x4>;
			#clock-cells = <2>;
		};
	};

	gfx_l3_cm: clock@900 {
		compatible = "ti,omap4-cm";
		clock-output-names = "gfx_l3_cm";
		reg = <0x900 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x900 0x100>;

		gfx_l3_clkctrl: clock@0 {
			compatible = "ti,clkctrl";
			clock-output-names = "gfx_l3_clkctrl";
			reg = <0x0 0x8>;
			#clock-cells = <2>;
		};
	};

	l4_cefuse_cm: clock@a00 {
		compatible = "ti,omap4-cm";
		clock-output-names = "l4_cefuse_cm";
		reg = <0xa00 0x100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xa00 0x100>;

		l4_cefuse_clkctrl: clock@0 {
			compatible = "ti,clkctrl";
			clock-output-names = "l4_cefuse_clkctrl";
			reg = <0x0 0x24>;
			#clock-cells = <2>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for AM33XX SoC
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
#include <dt-bindings/clock/am3.h>

/ {
	compatible = "ti,am33xx";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		d-can0 = &dcan0;
		d-can1 = &dcan1;
		usb0 = &usb0;
		usb1 = &usb1;
		phy0 = &usb0_phy;
		phy1 = &usb1_phy;
		ethernet0 = &cpsw_port1;
		ethernet1 = &cpsw_port2;
		spi0 = &spi0;
		spi1 = &spi1;
		mmc0 = &mmc1;
		mmc1 = &mmc2;
		mmc2 = &mmc3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "arm,cortex-a8";
			enable-method = "ti,am3352";
			device_type = "cpu";
			reg = <0>;

			operating-points-v2 = <&cpu0_opp_table>;

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */
			cpu-idle-states = <&mpu_gate>;
		};

		idle-states {
			mpu_gate: mpu_gate {
				compatible = "arm,idle-state";
				entry-latency-us = <40>;
				exit-latency-us = <90>;
				min-residency-us = <300>;
				ti,idle-wkup-m3;
			};
		};
	};

	cpu0_opp_table: opp-table {
		compatible = "operating-points-v2-ti-cpu";
		syscon = <&scm_conf>;

		/*
		 * The three following nodes are marked with opp-suspend
		 * because the can not be enabled simultaneously on a
		 * single SoC.
		 */
		opp50-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <950000 931000 969000>;
			opp-supported-hw = <0x06 0x0010>;
			opp-suspend;
		};

		opp100-275000000 {
			opp-hz = /bits/ 64 <275000000>;
			opp-microvolt = <1100000 1078000 1122000>;
			opp-supported-hw = <0x01 0x00FF>;
			opp-suspend;
		};

		opp100-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <1100000 1078000 1122000>;
			opp-supported-hw = <0x06 0x0020>;
			opp-suspend;
		};

		opp100-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <1100000 1078000 1122000>;
			opp-supported-hw = <0x01 0xFFFF>;
		};

		opp100-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1100000 1078000 1122000>;
			opp-supported-hw = <0x06 0x0040>;
		};

		opp120-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1200000 1176000 1224000>;
			opp-supported-hw = <0x01 0xFFFF>;
		};

		opp120-720000000 {
			opp-hz = /bits/ 64 <720000000>;
			opp-microvolt = <1200000 1176000 1224000>;
			opp-supported-hw = <0x06 0x0080>;
		};

		oppturbo-720000000 {
			opp-hz = /bits/ 64 <720000000>;
			opp-microvolt = <1260000 1234800 1285200>;
			opp-supported-hw = <0x01 0xFFFF>;
		};

		oppturbo-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <1260000 1234800 1285200>;
			opp-supported-hw = <0x06 0x0100>;
		};

		oppnitro-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <1325000 1298500 1351500>;
			opp-supported-hw = <0x04 0x0200>;
		};
	};

	target-module@4b000000 {
		compatible = "ti,sysc-omap4-simple", "ti,sysc";
		clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
		clock-names = "fck";
		ti,no-idle;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x4b000000 0x1000000>;

		target-module@140000 {
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x140000 0xec0000>;

			pmu@0 {
				compatible = "arm,cortex-a8-pmu";
				interrupts = <3>;
			};
		};
	};

	/*
	 * The soc node represents the soc top level view. It is used for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
	};

	/*
	 * XXX: Use a flat representation of the AM33XX interconnect.
	 * The real AM33XX interconnect network is quite complex. Since
	 * it will not bring real advantage to represent that in DT
	 * for the moment, just use a fake OCP bus entry to represent
	 * the whole bus hierarchy.
	 */
	ocp: ocp {
		compatible = "simple-pm-bus";
		power-domains = <&prm_per>;
		clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
		clock-names = "fck";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		l4_wkup: interconnect@44c00000 {
		};
		l4_per: interconnect@48000000 {
		};
		l4_fw: interconnect@47c00000 {
		};
		l4_fast: interconnect@4a000000 {
		};
		l4_mpuss: interconnect@4b140000 {
		};

		intc: interrupt-controller@48200000 {
			compatible = "ti,am33xx-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x48200000 0x1000>;
		};

		target-module@49000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49000000 0x4>;
			reg-names = "rev";
			clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49000000 0x10000>;

			edma: dma@0 {
				compatible = "ti,edma3-tpcc";
				reg = <0 0x10000>;
				reg-names = "edma3_cc";
				interrupts = <12 13 14>;
				interrupt-names = "edma3_ccint", "edma3_mperr",
						  "edma3_ccerrint";
				dma-requests = <64>;
				#dma-cells = <2>;

				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
					   <&edma_tptc2 0>;

				ti,edma-memcpy-channels = <20 21>;
			};
		};

		target-module@49800000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49800000 0x4>,
			      <0x49800010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49800000 0x100000>;

			edma_tptc0: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <112>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@49900000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49900000 0x4>,
			      <0x49900010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49900000 0x100000>;

			edma_tptc1: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <113>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@49a00000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49a00000 0x4>,
			      <0x49a00010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49a00000 0x100000>;

			edma_tptc2: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <114>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@47810000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x478102fc 0x4>,
			      <0x47810110 0x4>,
			      <0x47810114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_ENAWAKEUP |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x47810000 0x1000>;

			mmc3: mmc@0 {
				compatible = "ti,am335-sdhci";
				ti,needs-special-reset;
				interrupts = <29>;
				reg = <0x0 0x1000>;
				status = "disabled";
			};
		};

		usb: target-module@47400000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x47400000 0x4>,
			      <0x47400010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
					 SYSC_OMAP4_SOFTRESET)>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x47400000 0x8000>;

			usb0_phy: usb-phy@1300 {
				compatible = "ti,am335x-usb-phy";
				reg = <0x1300 0x100>;
				reg-names = "phy";
				ti,ctrl_mod = <&usb_ctrl_mod>;
				#phy-cells = <0>;
			};

			usb0: usb@1400 {
				compatible = "ti,musb-am33xx";
				reg = <0x1400 0x400>,
				      <0x1000 0x200>;
				reg-names = "mc", "control";

				interrupts = <18>;
				interrupt-names = "mc";
				dr_mode = "otg";
				mentor,multipoint = <1>;
				mentor,num-eps = <16>;
				mentor,ram-bits = <12>;
				mentor,power = <500>;
				phys = <&usb0_phy>;

				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
					&cppi41dma  2 0 &cppi41dma  3 0
					&cppi41dma  4 0 &cppi41dma  5 0
					&cppi41dma  6 0 &cppi41dma  7 0
					&cppi41dma  8 0 &cppi41dma  9 0
					&cppi41dma 10 0 &cppi41dma 11 0
					&cppi41dma 12 0 &cppi41dma 13 0
					&cppi41dma 14 0 &cppi41dma  0 1
					&cppi41dma  1 1 &cppi41dma  2 1
					&cppi41dma  3 1 &cppi41dma  4 1
					&cppi41dma  5 1 &cppi41dma  6 1
					&cppi41dma  7 1 &cppi41dma  8 1
					&cppi41dma  9 1 &cppi41dma 10 1
					&cppi41dma 11 1 &cppi41dma 12 1
					&cppi41dma 13 1 &cppi41dma 14 1>;
				dma-names =
					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
					"rx14", "rx15",
					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
					"tx14", "tx15";
			};

			usb1_phy: usb-phy@1b00 {
				compatible = "ti,am335x-usb-phy";
				reg = <0x1b00 0x100>;
				reg-names = "phy";
				ti,ctrl_mod = <&usb_ctrl_mod>;
				#phy-cells = <0>;
			};

			usb1: usb@1800 {
				compatible = "ti,musb-am33xx";
				reg = <0x1c00 0x400>,
				      <0x1800 0x200>;
				reg-names = "mc", "control";
				interrupts = <19>;
				interrupt-names = "mc";
				dr_mode = "otg";
				mentor,multipoint = <1>;
				mentor,num-eps = <16>;
				mentor,ram-bits = <12>;
				mentor,power = <500>;
				phys = <&usb1_phy>;

				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
					&cppi41dma 17 0 &cppi41dma 18 0
					&cppi41dma 19 0 &cppi41dma 20 0
					&cppi41dma 21 0 &cppi41dma 22 0
					&cppi41dma 23 0 &cppi41dma 24 0
					&cppi41dma 25 0 &cppi41dma 26 0
					&cppi41dma 27 0 &cppi41dma 28 0
					&cppi41dma 29 0 &cppi41dma 15 1
					&cppi41dma 16 1 &cppi41dma 17 1
					&cppi41dma 18 1 &cppi41dma 19 1
					&cppi41dma 20 1 &cppi41dma 21 1
					&cppi41dma 22 1 &cppi41dma 23 1
					&cppi41dma 24 1 &cppi41dma 25 1
					&cppi41dma 26 1 &cppi41dma 27 1
					&cppi41dma 28 1 &cppi41dma 29 1>;
				dma-names =
					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
					"rx14", "rx15",
					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
					"tx14", "tx15";
			};

			cppi41dma: dma-controller@2000 {
				compatible = "ti,am3359-cppi41";
				reg =  <0x0000 0x1000>,
				       <0x2000 0x1000>,
				       <0x3000 0x1000>,
				       <0x4000 0x4000>;
				reg-names = "glue", "controller", "scheduler", "queuemgr";
				interrupts = <17>;
				interrupt-names = "glue";
				#dma-cells = <2>;
				/* For backwards compatibility: */
				#dma-channels = <30>;
				dma-channels = <30>;
				#dma-requests = <256>;
				dma-requests = <256>;
			};
		};

		target-module@40300000 {
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;
			clock-names = "fck";
			ti,no-idle;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x40300000 0x10000>;

			ocmcram: sram@0 {
				compatible = "mmio-sram";
				reg = <0 0x10000>; /* 64k */
				ranges = <0 0 0x10000>;
				#address-cells = <1>;
				#size-cells = <1>;

				pm_sram_code: pm-code-sram@0 {
					compatible = "ti,sram";
					reg = <0x0 0x1000>;
					protect-exec;
				};

				pm_sram_data: pm-data-sram@1000 {
					compatible = "ti,sram";
					reg = <0x1000 0x1000>;
					pool;
				};
			};
		};

		target-module@4c000000 {
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			reg = <0x4c000000 0x4>;
			reg-names = "rev";
			clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;
			clock-names = "fck";
			ti,no-idle;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4c000000 0x1000000>;

			emif: emif@0 {
				compatible = "ti,emif-am3352";
				reg = <0 0x1000000>;
				interrupts = <101>;
				sram = <&pm_sram_code
					&pm_sram_data>;
			};
		};

		target-module@50000000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x50000000 4>,
			      <0x50000010 4>,
			      <0x50000014 4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
				 <0x00000000 0x00000000 0x40000000>; /* data */

			gpmc: gpmc@50000000 {
				compatible = "ti,am3352-gpmc";
				reg = <0x50000000 0x2000>;
				interrupts = <100>;
				dmas = <&edma 52 0>;
				dma-names = "rxtx";
				gpmc,num-cs = <7>;
				gpmc,num-waitpins = <2>;
				#address-cells = <2>;
				#size-cells = <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-controller;
				#gpio-cells = <2>;
				status = "disabled";
			};
		};

		sham_target: target-module@53100000 {
			compatible = "ti,sysc-omap3-sham", "ti,sysc";
			reg = <0x53100100 0x4>,
			      <0x53100110 0x4>,
			      <0x53100114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l3_clkdm */
			clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x53100000 0x1000>;

			sham: sham@0 {
				compatible = "ti,omap4-sham";
				reg = <0 0x200>;
				interrupts = <109>;
				dmas = <&edma 36 0>;
				dma-names = "rx";
			};
		};

		aes_target: target-module@53500000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x53500080 0x4>,
			      <0x53500084 0x4>,
			      <0x53500088 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l3_clkdm */
			clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x53500000 0x1000>;

			aes: aes@0 {
				compatible = "ti,omap4-aes";
				reg = <0 0xa0>;
				interrupts = <103>;
				dmas = <&edma 6 0>,
				       <&edma 5 0>;
				dma-names = "tx", "rx";
			};
		};

		target-module@56000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x5600fe00 0x4>,
			      <0x5600fe10 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
			clock-names = "fck";
			power-domains = <&prm_gfx>;
			resets = <&prm_gfx 0>;
			reset-names = "rstctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x56000000 0x1000000>;

			/*
			 * Closed source PowerVR driver, no child device
			 * binding or driver in mainline
			 */
		};
	};
};

#include "am33xx-l4.dtsi"
#include "am33xx-clocks.dtsi"

&prcm {
	prm_per: prm@c00 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0xc00 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_wkup: prm@d00 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0xd00 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_mpu: prm@e00 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0xe00 0x100>;
		#power-domain-cells = <0>;
	};

	prm_device: prm@f00 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0xf00 0x100>;
		#reset-cells = <1>;
	};

	prm_rtc: prm@1000 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0x1000 0x100>;
		#power-domain-cells = <0>;
	};

	prm_gfx: prm@1100 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0x1100 0x100>;
		#power-domain-cells = <0>;
		#reset-cells = <1>;
	};

	prm_cefuse: prm@1200 {
		compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
		reg = <0x1200 0x100>;
		#power-domain-cells = <0>;
	};
};

/* Preferred always-on timer for clocksource */
&timer1_target {
	clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
		 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
	clock-names = "fck", "ick";
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&timer1_fck>;
		assigned-clock-parents = <&sys_clkin_ck>;
	};
};

/* Preferred timer for clockevent */
&timer2_target {
	clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
		 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
	clock-names = "fck", "ick";
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&timer2_fck>;
		assigned-clock-parents = <&sys_clkin_ck>;
	};
};