code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8MN DISP blk-ctrl

maintainers:
  - Lucas Stach <l.stach@pengutronix.de>

description:
  The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
  the NoC and ensuring proper power sequencing of the display and MIPI CSI
  peripherals located in the DISP domain of the SoC.

properties:
  compatible:
    items:
      - const: fsl,imx8mn-disp-blk-ctrl
      - const: syscon

  reg:
    maxItems: 1

  '#power-domain-cells':
    const: 1

  power-domains:
    minItems: 5
    maxItems: 5

  power-domain-names:
    items:
      - const: bus
      - const: isi
      - const: lcdif
      - const: mipi-dsi
      - const: mipi-csi

  clocks:
    minItems: 11
    maxItems: 11

  clock-names:
    items:
      - const: disp_axi
      - const: disp_apb
      - const: disp_axi_root
      - const: disp_apb_root
      - const: lcdif-axi
      - const: lcdif-apb
      - const: lcdif-pix
      - const: dsi-pclk
      - const: dsi-ref
      - const: csi-aclk
      - const: csi-pclk

required:
  - compatible
  - reg
  - power-domains
  - power-domain-names
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mn-clock.h>
    #include <dt-bindings/power/imx8mn-power.h>

    disp_blk_ctl: blk_ctrl@32e28000 {
      compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
      reg = <0x32e28000 0x100>;
      power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
                      <&pgc_dispmix>, <&pgc_mipi>,
                      <&pgc_mipi>;
      power-domain-names = "bus", "isi", "lcdif", "mipi-dsi",
                           "mipi-csi";
      clocks = <&clk IMX8MN_CLK_DISP_AXI>,
               <&clk IMX8MN_CLK_DISP_APB>,
               <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
               <&clk IMX8MN_CLK_DISP_APB_ROOT>,
               <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
               <&clk IMX8MN_CLK_DISP_APB_ROOT>,
               <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
               <&clk IMX8MN_CLK_DSI_CORE>,
               <&clk IMX8MN_CLK_DSI_PHY_REF>,
               <&clk IMX8MN_CLK_CSI1_PHY_REF>,
               <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
       clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root",
                     "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
                     "dsi-ref", "csi-aclk", "csi-pclk";
       #power-domain-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8MP HDMI blk-ctrl

maintainers:
  - Lucas Stach <l.stach@pengutronix.de>

description:
  The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to
  the NoC and ensuring proper power sequencing of the display pipeline
  peripherals located in the HDMI domain of the SoC.

properties:
  compatible:
    items:
      - const: fsl,imx8mp-hdmi-blk-ctrl
      - const: syscon

  reg:
    maxItems: 1

  '#power-domain-cells':
    const: 1

  power-domains:
    minItems: 8
    maxItems: 8

  power-domain-names:
    items:
      - const: bus
      - const: irqsteer
      - const: lcdif
      - const: pai
      - const: pvi
      - const: trng
      - const: hdmi-tx
      - const: hdmi-tx-phy

  clocks:
    minItems: 4
    maxItems: 4

  clock-names:
    items:
      - const: apb
      - const: axi
      - const: ref_266m
      - const: ref_24m

  interconnects:
    maxItems: 3

  interconnect-names:
    items:
      - const: hrv
      - const: lcdif-hdmi
      - const: hdcp

required:
  - compatible
  - reg
  - power-domains
  - power-domain-names
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mp-clock.h>
    #include <dt-bindings/power/imx8mp-power.h>

    blk-ctrl@32fc0000 {
        compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
        reg = <0x32fc0000 0x23c>;
        clocks = <&clk IMX8MP_CLK_HDMI_APB>,
                 <&clk IMX8MP_CLK_HDMI_ROOT>,
                 <&clk IMX8MP_CLK_HDMI_REF_266M>,
                 <&clk IMX8MP_CLK_HDMI_24M>;
        clock-names = "apb", "axi", "ref_266m", "ref_24m";
        power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,
                        <&pgc_hdmimix>, <&pgc_hdmimix>, <&pgc_hdmimix>,
                        <&pgc_hdmimix>, <&pgc_hdmi_phy>;
        power-domain-names = "bus", "irqsteer", "lcdif", "pai", "pvi", "trng",
                             "hdmi-tx", "hdmi-tx-phy";
        #power-domain-cells = <1>;
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8MP HSIO blk-ctrl

maintainers:
  - Lucas Stach <l.stach@pengutronix.de>

description:
  The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
  the NoC and ensuring proper power sequencing of the high-speed IO
  (USB an PCIe) peripherals located in the HSIO domain of the SoC.

properties:
  compatible:
    items:
      - const: fsl,imx8mp-hsio-blk-ctrl
      - const: syscon

  reg:
    maxItems: 1

  '#power-domain-cells':
    const: 1

  power-domains:
    minItems: 6
    maxItems: 6

  power-domain-names:
    items:
      - const: bus
      - const: usb
      - const: usb-phy1
      - const: usb-phy2
      - const: pcie
      - const: pcie-phy

  clocks:
    minItems: 2
    maxItems: 2

  clock-names:
    items:
      - const: usb
      - const: pcie

  interconnects:
    maxItems: 4

  interconnect-names:
    items:
      - const: noc-pcie
      - const: usb1
      - const: usb2
      - const: pcie

required:
  - compatible
  - reg
  - power-domains
  - power-domain-names
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mp-clock.h>
    #include <dt-bindings/power/imx8mp-power.h>

    hsio_blk_ctrl: blk-ctrl@32f10000 {
        compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
        reg = <0x32f10000 0x24>;
        clocks = <&clk IMX8MP_CLK_USB_ROOT>,
                 <&clk IMX8MP_CLK_PCIE_ROOT>;
        clock-names = "usb", "pcie";
        power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
                        <&pgc_usb1_phy>, <&pgc_usb2_phy>,
                        <&pgc_hsiomix>, <&pgc_pcie_phy>;
        power-domain-names = "bus", "usb", "usb-phy1",
                             "usb-phy2", "pcie", "pcie-phy";
        #power-domain-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8MP Media Block Control

maintainers:
  - Paul Elder <paul.elder@ideasonboard.com>

description:
  The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
  providing access to the NoC and ensuring proper power sequencing of the
  peripherals within the MEDIAMIX domain.

properties:
  compatible:
    items:
      - const: fsl,imx8mp-media-blk-ctrl
      - const: syscon

  reg:
    maxItems: 1

  '#power-domain-cells':
    const: 1

  power-domains:
    maxItems: 10

  power-domain-names:
    items:
      - const: bus
      - const: mipi-dsi1
      - const: mipi-csi1
      - const: lcdif1
      - const: isi
      - const: mipi-csi2
      - const: lcdif2
      - const: isp
      - const: dwe
      - const: mipi-dsi2

  clocks:
    items:
      - description: The APB clock
      - description: The AXI clock
      - description: The pixel clock for the first CSI2 receiver (aclk)
      - description: The pixel clock for the second CSI2 receiver (aclk)
      - description: The pixel clock for the first LCDIF (pix_clk)
      - description: The pixel clock for the second LCDIF (pix_clk)
      - description: The core clock for the ISP (clk)
      - description: The MIPI-PHY reference clock used by DSI

  clock-names:
    items:
      - const: apb
      - const: axi
      - const: cam1
      - const: cam2
      - const: disp1
      - const: disp2
      - const: isp
      - const: phy

  interconnects:
    maxItems: 8

  interconnect-names:
    items:
      - const: lcdif-rd
      - const: lcdif-wr
      - const: isi0
      - const: isi1
      - const: isi2
      - const: isp0
      - const: isp1
      - const: dwe

required:
  - compatible
  - reg
  - '#power-domain-cells'
  - power-domains
  - power-domain-names
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mp-clock.h>
    #include <dt-bindings/power/imx8mp-power.h>

    media_blk_ctl: blk-ctl@32ec0000 {
        compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
        reg = <0x32ec0000 0x138>;
        power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
                        <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
                        <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
                        <&mipi_phy2_pd>;
        power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
                             "mipi-csi2", "lcdif2", "isp", "dwe", "mipi-dsi2";
        clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
                 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
                 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
                 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
                 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
                 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
                 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
                 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
        clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
                      "isp", "phy";
        #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8MQ VPU blk-ctrl

maintainers:
  - Lucas Stach <l.stach@pengutronix.de>

description:
  The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to
  the NoC and ensuring proper power sequencing of the VPU peripherals
  located in the VPU domain of the SoC.

properties:
  compatible:
    items:
      - const: fsl,imx8mq-vpu-blk-ctrl

  reg:
    maxItems: 1

  '#power-domain-cells':
    const: 1

  power-domains:
    minItems: 3
    maxItems: 3

  power-domain-names:
    items:
      - const: bus
      - const: g1
      - const: g2

  clocks:
    minItems: 2
    maxItems: 2

  clock-names:
    items:
      - const: g1
      - const: g2

required:
  - compatible
  - reg
  - power-domains
  - power-domain-names
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mq-clock.h>
    #include <dt-bindings/power/imx8mq-power.h>

    vpu_blk_ctrl: blk-ctrl@38320000 {
      compatible = "fsl,imx8mq-vpu-blk-ctrl";
      reg = <0x38320000 0x100>;
      power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
      power-domain-names = "bus", "g1", "g2";
      clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
               <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
      clock-names = "g1", "g2";
      #power-domain-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx93-media-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX93 Media blk-ctrl

maintainers:
  - Peng Fan <peng.fan@nxp.com>

description:
  The i.MX93 MEDIAMIX domain contains control and status registers known
  as MEDIAMIX Block Control (MEDIAMIX BLK_CTRL). These registers include
  clocking, reset, and miscellaneous top-level controls for peripherals
  within the MEDIAMIX domain

properties:
  compatible:
    items:
      - const: fsl,imx93-media-blk-ctrl
      - const: syscon

  reg:
    maxItems: 1

  '#power-domain-cells':
    const: 1

  power-domains:
    maxItems: 1

  clocks:
    maxItems: 10

  clock-names:
    items:
      - const: apb
      - const: axi
      - const: nic
      - const: disp
      - const: cam
      - const: pxp
      - const: lcdif
      - const: isi
      - const: csi
      - const: dsi

required:
  - compatible
  - reg
  - power-domains
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx93-clock.h>
    #include <dt-bindings/power/fsl,imx93-power.h>

    media_blk_ctrl: system-controller@4ac10000 {
      compatible = "fsl,imx93-media-blk-ctrl", "syscon";
      reg = <0x4ac10000 0x10000>;
      power-domains = <&mediamix>;
      clocks = <&clk IMX93_CLK_MEDIA_APB>,
               <&clk IMX93_CLK_MEDIA_AXI>,
               <&clk IMX93_CLK_NIC_MEDIA_GATE>,
               <&clk IMX93_CLK_MEDIA_DISP_PIX>,
               <&clk IMX93_CLK_CAM_PIX>,
               <&clk IMX93_CLK_PXP_GATE>,
               <&clk IMX93_CLK_LCDIF_GATE>,
               <&clk IMX93_CLK_ISI_GATE>,
               <&clk IMX93_CLK_MIPI_CSI_GATE>,
               <&clk IMX93_CLK_MIPI_DSI_GATE>;
               clock-names = "apb", "axi", "nic", "disp", "cam",
                             "pxp", "lcdif", "isi", "csi", "dsi";
      #power-domain-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx93-src.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX93 System Reset Controller

maintainers:
  - Peng Fan <peng.fan@nxp.com>

description: |
  The System Reset Controller (SRC) is responsible for the generation of
  all the system reset signals and boot argument latching.

  Its main functions are as follows,
  - Deals with all global system reset sources from other modules,
    and generates global system reset.
  - Responsible for power gating of MIXs (Slices) and their memory
    low power control.

properties:
  compatible:
    items:
      - const: fsl,imx93-src
      - const: syscon

  reg:
    maxItems: 1

  ranges: true

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

patternProperties:
  "power-domain@[0-9a-f]+$":

    type: object
    properties:
      compatible:
        items:
          - const: fsl,imx93-src-slice

      '#power-domain-cells':
        const: 0

      reg:
        items:
          - description: mix slice register region
          - description: mem slice register region

      clocks:
        description: |
          A number of phandles to clocks that need to be enabled
          during domain power-up sequencing to ensure reset
          propagation into devices located inside this power domain.
        minItems: 1
        maxItems: 5

    required:
      - compatible
      - '#power-domain-cells'
      - reg

required:
  - compatible
  - reg
  - ranges
  - '#address-cells'
  - '#size-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx93-clock.h>

    system-controller@44460000 {
        compatible = "fsl,imx93-src", "syscon";
        reg = <0x44460000 0x10000>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        mediamix: power-domain@0 {
            compatible = "fsl,imx93-src-slice";
            reg = <0x44462400 0x400>, <0x44465800 0x400>;
            #power-domain-cells = <0>;
            clocks = <&clk IMX93_CLK_MEDIA_AXI>,
                     <&clk IMX93_CLK_MEDIA_APB>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/imx8m-soc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8M Series SoC

maintainers:
  - Alice Guo <alice.guo@nxp.com>

description: |
  NXP i.MX8M series SoCs contain fuse entries from which SoC Unique ID can be
  obtained.

select:
  properties:
    compatible:
      contains:
        enum:
          - fsl,imx8mm
          - fsl,imx8mn
          - fsl,imx8mp
          - fsl,imx8mq
  required:
    - compatible

patternProperties:
  "^soc@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        items:
          - enum:
              - fsl,imx8mm-soc
              - fsl,imx8mn-soc
              - fsl,imx8mp-soc
              - fsl,imx8mq-soc
          - const: simple-bus

      "#address-cells":
        const: 1

      "#size-cells":
        const: 1

      ranges: true

      dma-ranges: true

      nvmem-cells:
        maxItems: 1
        description: Phandle to the SOC Unique ID provided by a nvmem node

      nvmem-cell-names:
        const: soc_unique_id

    required:
      - compatible
      - nvmem-cells
      - nvmem-cell-names

    additionalProperties:
      type: object

additionalProperties: true

examples:
  - |
    / {
        model = "FSL i.MX8MM EVK board";
        compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
        #address-cells = <2>;
        #size-cells = <2>;

        soc@0 {
            compatible = "fsl,imx8mm-soc", "simple-bus";
            #address-cells = <1>;
            #size-cells = <1>;
            ranges = <0x0 0x0 0x0 0x3e000000>;
            nvmem-cells = <&imx8mm_uid>;
            nvmem-cell-names = "soc_unique_id";
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2022, Intel Corporation
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel HPS Copy Engine

maintainers:
  - Matthew Gerlach <matthew.gerlach@linux.intel.com>

description: |
  The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
  a bootable image from host memory to HPS DDR.  Additionally, there is a
  register the HPS can use to indicate the state of booting the copied image as
  well as a keep-a-live indication to the host.

properties:
  compatible:
    const: intel,hps-copy-engine

  '#dma-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    bus@80000000 {
        compatible = "simple-bus";
        reg = <0x80000000 0x60000000>,
              <0xf9000000 0x00100000>;
        reg-names = "axi_h2f", "axi_h2f_lw";
        #address-cells = <2>;
        #size-cells = <1>;
        ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;

        dma-controller@0 {
            compatible = "intel,hps-copy-engine";
            reg = <0x00000000 0x00000000 0x00001000>;
            #dma-cells = <1>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright 2020 Antmicro <www.antmicro.com>
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/litex/litex,soc-controller.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: LiteX SoC Controller driver

description: |
  This is the SoC Controller driver for the LiteX SoC Builder.
  Its purpose is to verify LiteX CSR (Control&Status Register) access
  operations and provide functions for other drivers to read/write CSRs
  and to check if those accessors are ready to be used.

maintainers:
  - Karol Gugala <kgugala@antmicro.com>
  - Mateusz Holenko <mholenko@antmicro.com>

properties:
  compatible:
    const: litex,soc-controller

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    soc_ctrl0: soc-controller@f0000000 {
        compatible = "litex,soc-controller";
        reg = <0xf0000000 0xc>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# # Copyright 2020 MediaTek Inc.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/mediatek/devapc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: MediaTek Device Access Permission Control driver

description: |
  MediaTek bus fabric provides TrustZone security support and data
  protection to prevent slaves from being accessed by unexpected masters.
  The security violation is logged and sent to the processor for further
  analysis and countermeasures.

maintainers:
  - Neal Liu <neal.liu@mediatek.com>

properties:
  compatible:
    enum:
      - mediatek,mt6779-devapc
      - mediatek,mt8186-devapc

  reg:
    description: The base address of devapc register bank
    maxItems: 1

  interrupts:
    description: A single interrupt specifier
    maxItems: 1

  clocks:
    description: Contains module clock source and clock names
    maxItems: 1

  clock-names:
    description: Names of the clocks list in clocks property
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt6779-clk.h>

    devapc: devapc@10207000 {
      compatible = "mediatek,mt6779-devapc";
      reg = <0x10207000 0x1000>;
      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
      clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
      clock-names = "devapc-infra-clock";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek color correction

maintainers:
  - Matthias Brugger <matthias.bgg@gmail.com>
  - Moudy Ho <moudy.ho@mediatek.com>

description: |
  MediaTek color correction with 3X3 matrix.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8183-mdp3-ccorr

  reg:
    maxItems: 1

  mediatek,gce-client-reg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      items:
        - description: phandle of GCE
        - description: GCE subsys id
        - description: register offset
        - description: register size
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property. Each GCE subsys id is mapping to
      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.

  mediatek,gce-events:
    description:
      The event id which is mapping to the specific hardware event signal
      to gce. The event id is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h of each chips.
    $ref: /schemas/types.yaml#/definitions/uint32-array

  clocks:
    minItems: 1

required:
  - compatible
  - reg
  - mediatek,gce-client-reg
  - mediatek,gce-events
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/gce/mt8183-gce.h>

    mdp3_ccorr: mdp3-ccorr@1401c000 {
      compatible = "mediatek,mt8183-mdp3-ccorr";
      reg = <0x1401c000 0x1000>;
      mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
      mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>,
                            <CMDQ_EVENT_MDP_CCORR_EOF>;
      clocks = <&mmsys CLK_MM_MDP_CCORR>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mt7986-wo-ccif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Wireless Ethernet Dispatch (WED) WO controller interface for MT7986

maintainers:
  - Lorenzo Bianconi <lorenzo@kernel.org>
  - Felix Fietkau <nbd@nbd.name>

description:
  The MediaTek wo-ccif provides a configuration interface for WED WO
  controller used to perfrom offload rx packet processing (e.g. 802.11
  aggregation packet reordering or rx header translation) on MT7986 soc.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt7986-wo-ccif
      - const: syscon

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      syscon@151a5000 {
        compatible = "mediatek,mt7986-wo-ccif", "syscon";
        reg = <0 0x151a5000 0 0x1000>;
        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek mutex

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
  data path or MDP data path.
  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
  the shadow register.
  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    enum:
      - mediatek,mt2701-disp-mutex
      - mediatek,mt2712-disp-mutex
      - mediatek,mt6795-disp-mutex
      - mediatek,mt8167-disp-mutex
      - mediatek,mt8173-disp-mutex
      - mediatek,mt8183-disp-mutex
      - mediatek,mt8186-disp-mutex
      - mediatek,mt8186-mdp3-mutex
      - mediatek,mt8192-disp-mutex
      - mediatek,mt8195-disp-mutex

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: MUTEX Clock

  mediatek,gce-events:
    description:
      The event id which is mapping to the specific hardware event signal
      to gce. The event id is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h of each chips.
    $ref: /schemas/types.yaml#/definitions/uint32-array

  mediatek,gce-client-reg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      items:
        - description: phandle of GCE
        - description: GCE subsys id
        - description: register offset
        - description: register size
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property. Each GCE subsys id is mapping to
      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>
    #include <dt-bindings/gce/mt8173-gce.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        mutex: mutex@14020000 {
            compatible = "mediatek,mt8173-disp-mutex";
            reg = <0 0x14020000 0 0x1000>;
            interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
            clocks = <&mmsys CLK_MM_MUTEX_32K>;
            mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
                                  <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Write Direct Memory Access

maintainers:
  - Matthias Brugger <matthias.bgg@gmail.com>
  - Moudy Ho <moudy.ho@mediatek.com>

description: |
  MediaTek Write Direct Memory Access(WDMA) component used to write
  the data into DMA.

properties:
  compatible:
    items:
      - enum:
          - mediatek,mt8183-mdp3-wdma

  reg:
    maxItems: 1

  mediatek,gce-client-reg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      items:
        - description: phandle of GCE
        - description: GCE subsys id
        - description: register offset
        - description: register size
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property. Each GCE subsys id is mapping to
      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.

  mediatek,gce-events:
    description:
      The event id which is mapping to the specific hardware event signal
      to gce. The event id is defined in the gce header
      include/dt-bindings/gce/<chip>-gce.h of each chips.
    $ref: /schemas/types.yaml#/definitions/uint32-array

  power-domains:
    maxItems: 1

  clocks:
    minItems: 1

  iommus:
    maxItems: 1

required:
  - compatible
  - reg
  - mediatek,gce-client-reg
  - mediatek,gce-events
  - power-domains
  - clocks
  - iommus

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/gce/mt8183-gce.h>
    #include <dt-bindings/power/mt8183-power.h>
    #include <dt-bindings/memory/mt8183-larb-port.h>

    mdp3_wdma: mdp3-wdma@14006000 {
      compatible = "mediatek,mt8183-mdp3-wdma";
      reg = <0x14006000 0x1000>;
      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
      mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>,
                            <CMDQ_EVENT_MDP_WDMA0_EOF>;
      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
      clocks = <&mmsys CLK_MM_MDP_WDMA0>;
      iommus = <&iommu>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Smart Voltage Scaling (SVS) Device Tree Bindings

maintainers:
  - Roger Lu <roger.lu@mediatek.com>
  - Matthias Brugger <matthias.bgg@gmail.com>
  - Kevin Hilman <khilman@kernel.org>

description: |+
  The SVS engine is a piece of hardware which has several
  controllers(banks) for calculating suitable voltage to
  different power domains(CPU/GPU/CCI) according to
  chip process corner, temperatures and other factors. Then DVFS
  driver could apply SVS bank voltage to PMIC/Buck.

properties:
  compatible:
    enum:
      - mediatek,mt8183-svs
      - mediatek,mt8192-svs

  reg:
    maxItems: 1
    description: Address range of the MTK SVS controller.

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1
    description: Main clock for MTK SVS controller to work.

  clock-names:
    const: main

  nvmem-cells:
    minItems: 1
    description:
      Phandle to the calibration data provided by a nvmem device.
    items:
      - description: SVS efuse for SVS controller
      - description: Thermal efuse for SVS controller

  nvmem-cell-names:
    items:
      - const: svs-calibration-data
      - const: t-calibration-data

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: svs_rst

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - nvmem-cells
  - nvmem-cell-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        svs@1100b000 {
            compatible = "mediatek,mt8183-svs";
            reg = <0 0x1100b000 0 0x1000>;
            interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
            clocks = <&infracfg CLK_INFRA_THERM>;
            clock-names = "main";
            nvmem-cells = <&svs_calibration>, <&thermal_calibration>;
            nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
        };
    };


code:
MediaTek PMIC Wrapper Driver

This document describes the binding for the MediaTek PMIC wrapper.

On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface
is not directly visible to the CPU, but only through the PMIC wrapper
inside the SoC. The communication between the SoC and the PMIC can
optionally be encrypted. Also a non standard Dual IO SPI mode can be
used to increase speed.

IP Pairing

on MT8135 the pins of some SoC internal peripherals can be on the PMIC.
The signals of these pins are routed over the SPI bus using the pwrap
bridge. In the binding description below the properties needed for bridging
are marked with "IP Pairing". These are optional on SoCs which do not support
IP Pairing

Required properties in pwrap device node.
- compatible:
	"mediatek,mt2701-pwrap" for MT2701/7623 SoCs
	"mediatek,mt6765-pwrap" for MT6765 SoCs
	"mediatek,mt6779-pwrap" for MT6779 SoCs
	"mediatek,mt6797-pwrap" for MT6797 SoCs
	"mediatek,mt6873-pwrap" for MT6873/8192 SoCs
	"mediatek,mt7622-pwrap" for MT7622 SoCs
	"mediatek,mt8135-pwrap" for MT8135 SoCs
	"mediatek,mt8173-pwrap" for MT8173 SoCs
	"mediatek,mt8183-pwrap" for MT8183 SoCs
	"mediatek,mt8186-pwrap" for MT8186 SoCs
	"mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs
	"mediatek,mt8195-pwrap" for MT8195 SoCs
	"mediatek,mt8365-pwrap" for MT8365 SoCs
	"mediatek,mt8516-pwrap" for MT8516 SoCs
- interrupts: IRQ for pwrap in SOC
- reg-names: "pwrap" is required; "pwrap-bridge" is optional.
  "pwrap": Main registers base
  "pwrap-bridge": bridge base (IP Pairing)
- reg: Must contain an entry for each entry in reg-names.
- clock-names: Must include the following entries:
  "spi": SPI bus clock
  "wrap": Main module clock
  "sys": Optional system module clock
  "tmr": Optional timer module clock
- clocks: Must contain an entry for each entry in clock-names.

Optional properities:
- reset-names: Some SoCs include the following entries:
  "pwrap"
  "pwrap-bridge" (IP Pairing)
- resets: Must contain an entry for each entry in reset-names.
- pmic: Using either MediaTek PMIC MFD as the child device of pwrap
  See the following for child node definitions:
  Documentation/devicetree/bindings/mfd/mt6397.txt
  or the regulator-only device as the child device of pwrap, such as MT6380.
  See the following definitions for such kinds of devices.
  Documentation/devicetree/bindings/regulator/mt6380-regulator.txt

Example:
	pwrap: pwrap@1000f000 {
		compatible = "mediatek,mt8135-pwrap";
		reg = <0 0x1000f000 0 0x1000>,
			<0 0x11017000 0 0x1000>;
		reg-names = "pwrap", "pwrap-bridge";
		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
		resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
				<&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
		reset-names = "pwrap", "pwrap-bridge";
		clocks = <&clk26m>, <&clk26m>;
		clock-names = "spi", "wrap";

		pmic {
			compatible = "mediatek,mt6397";
		};
	};


code:
MediaTek SCPSYS
===============

The System Control Processor System (SCPSYS) has several power management
related tasks in the system. The tasks include thermal measurement, dynamic
voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control.
The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power
domain control.

The driver implements the Generic PM domain bindings described in
power/power-domain.yaml. It provides the power domains defined in
- include/dt-bindings/power/mt8173-power.h
- include/dt-bindings/power/mt6797-power.h
- include/dt-bindings/power/mt6765-power.h
- include/dt-bindings/power/mt2701-power.h
- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt7622-power.h

Required properties:
- compatible: Should be one of:
	- "mediatek,mt2701-scpsys"
	- "mediatek,mt2712-scpsys"
	- "mediatek,mt6765-scpsys"
	- "mediatek,mt6797-scpsys"
	- "mediatek,mt7622-scpsys"
	- "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
	- "mediatek,mt7623a-scpsys": For MT7623A SoC
	- "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
	- "mediatek,mt8173-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
- infracfg: must contain a phandle to the infracfg controller
- clock, clock-names: clocks according to the common clock binding.
                      These are clocks which hardware needs to be
                      enabled before enabling certain power domains.
	Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
	Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
	Required clocks for MT6765: MUX: "mm", "mfg"
				    CG: "mm-0", "mm-1", "mm-2", "mm-3", "isp-0",
					"isp-1", "cam-0", "cam-1", "cam-2",
					"cam-3","cam-4"
	Required clocks for MT6797: "mm", "mfg", "vdec"
	Required clocks for MT7622 or MT7629: "hif_sel"
	Required clocks for MT7623A: "ethif"
	Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"

Optional properties:
- vdec-supply: Power supply for the vdec power domain
- venc-supply: Power supply for the venc power domain
- isp-supply: Power supply for the isp power domain
- mm-supply: Power supply for the mm power domain
- venc_lt-supply: Power supply for the venc_lt power domain
- audio-supply: Power supply for the audio power domain
- usb-supply: Power supply for the usb power domain
- mfg_async-supply: Power supply for the mfg_async power domain
- mfg_2d-supply: Power supply for the mfg_2d power domain
- mfg-supply: Power supply for the mfg power domain

Example:

	scpsys: scpsys@10006000 {
		#power-domain-cells = <1>;
		compatible = "mediatek,mt8173-scpsys";
		reg = <0 0x10006000 0 0x1000>;
		infracfg = <&infracfg>;
		clocks = <&clk26m>,
			 <&topckgen CLK_TOP_MM_SEL>;
			 <&topckgen CLK_TOP_VENC_SEL>,
			 <&topckgen CLK_TOP_VENC_LT_SEL>;
		clock-names = "mfg", "mm", "venc", "venc_lt";
	};

Example consumer:

	afe: mt8173-afe-pcm@11220000 {
		compatible = "mediatek,mt8173-afe-pcm";
		power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Atmel Timer Counter Block

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

description: |
  The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
  timer has three channels with two counters each.

properties:
  compatible:
    items:
      - enum:
          - atmel,at91rm9200-tcb
          - atmel,at91sam9x5-tcb
          - atmel,sama5d2-tcb
      - const: simple-mfd
      - const: syscon

  reg:
    maxItems: 1

  interrupts:
    description:
      List of interrupts. One interrupt per TCB channel if available or one
      interrupt for the TC block
    minItems: 1
    maxItems: 3

  clock-names:
    description:
      List of clock names. Always includes t0_clk and slow clk. Also includes
      t1_clk and t2_clk if a clock per channel is available.
    minItems: 2
    maxItems: 4

  clocks:
    minItems: 2
    maxItems: 4

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

patternProperties:
  "^timer@[0-2]$":
    description: The timer block channels that are used as timers or counters.
    type: object
    properties:
      compatible:
        items:
          - enum:
              - atmel,tcb-timer
              - atmel,tcb-pwm
              - microchip,tcb-capture
      reg:
        description:
          List of channels to use for this particular timer. In Microchip TCB capture
          mode channels are registered as a counter devices, for the qdec mode TCB0's
          channel <0> and <1> are required.

        minItems: 1
        maxItems: 3
    required:
      - compatible
      - reg

  "^pwm@[0-2]$":
    description: The timer block channels that are used as PWMs.
    $ref: /schemas/pwm/pwm.yaml#
    type: object
    properties:
      compatible:
        const: atmel,tcb-pwm
      reg:
        description:
          TCB channel to use for this PWM.
        enum: [ 0, 1, 2 ]

      "#pwm-cells":
        description:
          The only third cell flag supported by this binding is
          PWM_POLARITY_INVERTED.
        const: 3

    required:
      - compatible
      - reg
      - "#pwm-cells"

    additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: atmel,sama5d2-tcb
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: t0_clk
            - const: gclk
            - const: slow_clk
    else:
      properties:
        clocks:
          minItems: 2
          maxItems: 4
        clock-names:
          oneOf:
            - items:
                - const: t0_clk
                - const: slow_clk
            - items:
                - const: t0_clk
                - const: t1_clk
                - const: t2_clk
                - const: slow_clk

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - '#address-cells'
  - '#size-cells'

additionalProperties: false

examples:
  - |
    /* One interrupt per TC block: */
        tcb0: timer@fff7c000 {
                compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0xfff7c000 0x100>;
                interrupts = <18 4>;
                clocks = <&tcb0_clk>, <&clk32k>;
                clock-names = "t0_clk", "slow_clk";

                timer@0 {
                        compatible = "atmel,tcb-timer";
                        reg = <0>, <1>;
                };

                timer@2 {
                        compatible = "atmel,tcb-timer";
                        reg = <2>;
                };
        };

    /* One interrupt per TC channel in a TC block: */
        tcb1: timer@fffdc000 {
                compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0xfffdc000 0x100>;
                interrupts = <26 4>, <27 4>, <28 4>;
                clocks = <&tcb1_clk>, <&clk32k>;
                clock-names = "t0_clk", "slow_clk";

                timer@0 {
                        compatible = "atmel,tcb-timer";
                        reg = <0>;
                };

                timer@1 {
                        compatible = "atmel,tcb-timer";
                        reg = <1>;
                };

                pwm@2 {
                        compatible = "atmel,tcb-pwm";
                        reg = <2>;
                        #pwm-cells = <3>;
                };
         };
    /* TCB0 Capture with QDEC: */
        timer@f800c000 {
                compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0xfff7c000 0x100>;
                interrupts = <18 4>;
                clocks = <&tcb0_clk>, <&clk32k>;
                clock-names = "t0_clk", "slow_clk";

                timer@0 {
                        compatible = "microchip,tcb-capture";
                        reg = <0>, <1>;
                };

                timer@2 {
                        compatible = "atmel,tcb-timer";
                        reg = <2>;
                };
        };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller

maintainers:
  - Conor Dooley <conor.dooley@microchip.com>

description: |
  PolarFire SoC devices include a microcontroller acting as the system controller,
  which provides "services" to the main processor and to the FPGA fabric. These
  services include hardware rng, reprogramming of the FPGA and verfification of the
  eNVM contents etc. More information on these services can be found online, at
  https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html

  Communication with the system controller is done via a mailbox, of which the client
  portion is documented here.

properties:
  mboxes:
    maxItems: 1

  compatible:
    const: microchip,mpfs-sys-controller

required:
  - compatible
  - mboxes

additionalProperties: false

examples:
  - |
    syscontroller {
      compatible = "microchip,mpfs-sys-controller";
      mboxes = <&mbox 0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,aoss-qmp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Always-On Subsystem side channel binding

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  This binding describes the hardware component responsible for side channel
  requests to the always-on subsystem (AOSS), used for certain power management
  requests that is not handled by the standard RPMh interface. Each client in the
  SoC has its own block of message RAM and IRQ for communication with the AOSS.
  The protocol used to communicate in the message RAM is known as Qualcomm
  Messaging Protocol (QMP)

  The AOSS side channel exposes control over a set of resources, used to control
  a set of debug related clocks and to affect the low power state of resources
  related to the secondary subsystems.

properties:
  compatible:
    items:
      - enum:
          - qcom,sc7180-aoss-qmp
          - qcom,sc7280-aoss-qmp
          - qcom,sc8180x-aoss-qmp
          - qcom,sc8280xp-aoss-qmp
          - qcom,sdm845-aoss-qmp
          - qcom,sm6350-aoss-qmp
          - qcom,sm8150-aoss-qmp
          - qcom,sm8250-aoss-qmp
          - qcom,sm8350-aoss-qmp
          - qcom,sm8450-aoss-qmp
          - qcom,sm8550-aoss-qmp
      - const: qcom,aoss-qmp

  reg:
    maxItems: 1
    description:
      The base address and size of the message RAM for this client's
      communication with the AOSS

  interrupts:
    maxItems: 1
    description:
      Should specify the AOSS message IRQ for this client

  mboxes:
    maxItems: 1
    description:
      Reference to the mailbox representing the outgoing doorbell in APCS for
      this client, as described in mailbox/mailbox.txt

  "#clock-cells":
    const: 0
    description:
      The single clock represents the QDSS clock.

required:
  - compatible
  - reg
  - interrupts
  - mboxes
  - "#clock-cells"

additionalProperties: false

patternProperties:
  "^(cx|mx|ebi)$":
    type: object
    description:
      The AOSS side channel also provides the controls for three cooling devices,
      these are expressed as subnodes of the QMP node. The name of the node is
      used to identify the resource and must therefor be "cx", "mx" or "ebi".

    properties:
      "#cooling-cells":
        const: 2

    required:
      - "#cooling-cells"

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    aoss_qmp: qmp@c300000 {
      compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
      reg = <0x0c300000 0x100000>;
      interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
      mboxes = <&apss_shared 0>;

      #clock-cells = <0>;

      cx_cdev: cx {
        #cooling-cells = <2>;
      };

      mx_cdev: mx {
        #cooling-cells = <2>;
      };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,apr-services.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm APR/GPR services shared parts

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description:
  Common parts of a static service in Qualcomm APR/GPR (Asynchronous/Generic
  Packet Router).

properties:
  reg:
    minimum: 1
    maximum: 13
    description: |
      APR Service ID
        3 = DSP Core Service
        4 = Audio  Front End Service.
        5 = Voice Stream Manager Service.
        6 = Voice processing manager.
        7 = Audio Stream Manager Service.
        8 = Audio Device Manager Service.
        9 = Multimode voice manager.
        10 = Core voice stream.
        11 = Core voice processor.
        12 = Ultrasound stream manager.
        13 = Listen stream manager.
      GPR Service ID
        1 = Audio Process Manager Service
        2 = Proxy Resource Manager Service.
        3 = AMDB Service.
        4 = Voice processing manager.

  qcom,protection-domain:
    $ref: /schemas/types.yaml#/definitions/string-array
    description: |
      Protection domain service name and path for APR service
      possible values are::
      "avs/audio", "msm/adsp/audio_pd".
      "kernel/elf_loader", "msm/modem/wlan_pd".
      "tms/servreg", "msm/adsp/audio_pd".
      "tms/servreg", "msm/modem/wlan_pd".
      "tms/servreg", "msm/slpi/sensor_pd".

required:
  - reg
  - qcom,protection-domain

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,apr.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm APR/GPR (Asynchronous/Generic Packet Router) binding

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description: |
  This binding describes the Qualcomm APR/GPR, APR/GPR is a IPC protocol for
  communication between Application processor and QDSP. APR/GPR is mainly
  used for audio/voice services on the QDSP.

properties:
  compatible:
    enum:
      - qcom,apr
      - qcom,apr-v2
      - qcom,gpr

  power-domains:
    maxItems: 1

  qcom,apr-domain:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2, 3, 4, 5, 6, 7]
    description:
      Selects the processor domain for apr
        1 = APR simulator
        2 = PC Domain
        3 = Modem Domain
        4 = ADSP Domain
        5 = Application processor Domain
        6 = Modem2 Domain
        7 = Application Processor2 Domain
    deprecated: true

  qcom,domain:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 7
    description:
      Selects the processor domain for apr
        1 = APR simulator
        2 = PC Domain
        3 = Modem Domain
        4 = ADSP Domain
        5 = Application processor Domain
        6 = Modem2 Domain
        7 = Application Processor2 Domain
      Selects the processor domain for gpr
        1 = Modem Domain
        2 = Audio DSP Domain
        3 = Application Processor Domain

  qcom,glink-channels:
    $ref: /schemas/types.yaml#/definitions/string-array
    description: Channel name used for the communication
    maxItems: 1

  qcom,intents:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description:
      List of (size, amount) pairs describing what intents should be
      preallocated for this virtual channel. This can be used to tweak the
      default intents available for the channel to meet expectations of the
      remote.

  qcom,smd-channels:
    $ref: /schemas/types.yaml#/definitions/string-array
    description: Channel name used for the communication
    items:
      - const: apr_audio_svc

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

patternProperties:
  "^service@[1-9a-d]$":
    type: object
    $ref: /schemas/soc/qcom/qcom,apr-services.yaml
    additionalProperties: true
    description:
      APR/GPR static port services.

    properties:
      compatible:
        enum:
          - qcom,q6core
          - qcom,q6asm
          - qcom,q6afe
          - qcom,q6adm
          - qcom,q6apm
          - qcom,q6prm

required:
  - compatible
  - qcom,domain

allOf:
  - if:
      properties:
        compatible:
          enum:
            - qcom,gpr
    then:
      properties:
        qcom,glink-channels:
          items:
            - const: adsp_apps
        power-domains: false
    else:
      properties:
        qcom,glink-channels:
          items:
            - const: apr_audio_svc

  - if:
      required:
        - qcom,glink-channels
    then:
      properties:
        qcom,smd-channels: false

  - if:
      required:
        - qcom,smd-channels
    then:
      properties:
        qcom,glink-channels: false

additionalProperties: false

examples:
  - |
    #include <dt-bindings/soc/qcom,apr.h>
    apr {
        compatible = "qcom,apr-v2";
        qcom,domain = <APR_DOMAIN_ADSP>;
        qcom,glink-channels = "apr_audio_svc";
        qcom,intents = <512 20>;
        #address-cells = <1>;
        #size-cells = <0>;

        q6core: service@3 {
            compatible = "qcom,q6core";
            reg = <APR_SVC_ADSP_CORE>;
            qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
        };

        service@4 {
            compatible = "qcom,q6afe";
            reg = <APR_SVC_AFE>;
            qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";

            clock-controller {
                compatible = "qcom,q6afe-clocks";
                #clock-cells = <2>;
            };

            dais {
                compatible = "qcom,q6afe-dais";
                #address-cells = <1>;
                #size-cells = <0>;
                #sound-dai-cells = <1>;
                /* ... */
            };
            /* ... */
        };
    };

  - |
    #include <dt-bindings/soc/qcom,gpr.h>
    gpr {
        compatible = "qcom,gpr";
        qcom,domain = <GPR_DOMAIN_ID_ADSP>;
        qcom,glink-channels = "adsp_apps";
        qcom,intents = <512 20>;
        #address-cells = <1>;
        #size-cells = <0>;

        service@1 {
            compatible = "qcom,q6apm";
            reg = <GPR_APM_MODULE_IID>;
            #sound-dai-cells = <0>;
            qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";

            dais {
                compatible = "qcom,q6apm-dais";
                iommus = <&apps_smmu 0x1801 0x0>;
            };

            bedais {
                compatible = "qcom,q6apm-lpass-dais";
                #sound-dai-cells = <1>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,eud.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Embedded USB Debugger

maintainers:
  - Souradeep Chowdhury <quic_schowdhu@quicinc.com>

description:
  This binding is used to describe the Qualcomm Embedded USB Debugger, which is
  mini USB-hub implemented on chip to support USB-based debug capabilities.

properties:
  compatible:
    items:
      - enum:
          - qcom,sc7280-eud
      - const: qcom,eud

  reg:
    items:
      - description: EUD Base Register Region
      - description: EUD Mode Manager Register

  interrupts:
    description: EUD interrupt
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description:
      These ports is to be attached to the endpoint of the DWC3 controller node
      and type C connector node. The controller has the "usb-role-switch"
      property.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: This port is to be attached to the DWC3 controller.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: This port is to be attached to the type C connector.

required:
  - compatible
  - reg
  - ports

additionalProperties: false

examples:
  - |
    eud@88e0000 {
           compatible = "qcom,sc7280-eud","qcom,eud";
           reg = <0x88e0000 0x2000>,
                 <0x88e2000 0x1000>;
           ports {
                   #address-cells = <1>;
                   #size-cells = <0>;
                   port@0 {
                           reg = <0>;
                           eud_ep: endpoint {
                                   remote-endpoint = <&usb2_role_switch>;
                           };
                   };
                   port@1 {
                           reg = <1>;
                           eud_con: endpoint {
                                   remote-endpoint = <&con_eud>;
                           };
                   };
           };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: GENI Serial Engine QUP Wrapper Controller

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |
 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
 is a programmable module for supporting a wide range of serial interfaces
 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
 Wrapper controller is modeled as a node with zero or more child nodes each
 representing a serial engine.

properties:
  compatible:
    enum:
      - qcom,geni-se-qup
      - qcom,geni-se-i2c-master-hub

  reg:
    description: QUP wrapper common register address and length.
    maxItems: 1

  clock-names:
    minItems: 1
    maxItems: 2

  clocks:
    minItems: 1
    maxItems: 2

  "#address-cells":
    const: 2

  "#size-cells":
    const: 2

  ranges: true

  interconnects:
    maxItems: 1

  interconnect-names:
    const: qup-core

  iommus:
    maxItems: 1

required:
  - compatible
  - reg
  - clock-names
  - clocks
  - "#address-cells"
  - "#size-cells"
  - ranges

patternProperties:
  "spi@[0-9a-f]+$":
    type: object
    description: GENI serial engine based SPI controller. SPI in master mode
                 supports up to 50MHz, up to four chip selects, programmable
                 data path from 4 bits to 32 bits and numerous protocol
                 variants.
    $ref: /schemas/spi/qcom,spi-geni-qcom.yaml#

  "i2c@[0-9a-f]+$":
    type: object
    description: GENI serial engine based I2C controller.
    $ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml#

  "serial@[0-9a-f]+$":
    type: object
    description: GENI Serial Engine based UART Controller.
    $ref: /schemas/serial/qcom,serial-geni-qcom.yaml#

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: qcom,geni-se-i2c-master-hub
    then:
      properties:
        clock-names:
          items:
            - const: s-ahb

        clocks:
          items:
            - description: Slave AHB Clock

        iommus: false

      patternProperties:
        "spi@[0-9a-f]+$": false
        "serial@[0-9a-f]+$": false
    else:
      properties:
        clock-names:
          items:
            - const: m-ahb
            - const: s-ahb

        clocks:
          items:
            - description: Master AHB Clock
            - description: Slave AHB Clock

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        geniqup@8c0000 {
            compatible = "qcom,geni-se-qup";
            reg = <0 0x008c0000 0 0x6000>;
            clock-names = "m-ahb", "s-ahb";
            clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
                <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
            #address-cells = <2>;
            #size-cells = <2>;
            ranges;

            i2c0: i2c@a94000 {
                compatible = "qcom,geni-i2c";
                reg = <0 0xa94000 0 0x4000>;
                interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
                clock-names = "se";
                clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
                pinctrl-names = "default", "sleep";
                pinctrl-0 = <&qup_1_i2c_5_active>;
                pinctrl-1 = <&qup_1_i2c_5_sleep>;
                #address-cells = <1>;
                #size-cells = <0>;
            };

            uart0: serial@a88000 {
                compatible = "qcom,geni-uart";
                reg = <0 0xa88000 0 0x7000>;
                interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
                clock-names = "se";
                clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
                pinctrl-names = "default", "sleep";
                pinctrl-0 = <&qup_1_uart_3_active>;
                pinctrl-1 = <&qup_1_uart_3_sleep>;
            };
        };
    };

...


code:
Qualcomm GLINK edge binding

This binding describes a Qualcomm GLINK edge, a fifo based mechanism for
communication between subsystem-pairs on various Qualcomm platforms. Two types
of edges can be described by the binding; the GLINK RPM edge and a SMEM based
edge.

- compatible:
	Usage: required for glink-rpm
	Value type: <stringlist>
	Definition: must be "qcom,glink-rpm"

- label:
	Usage: optional
	Value type: <string>
	Definition: should specify the subsystem name this edge corresponds to.

- interrupts:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: should specify the IRQ used by the remote processor to
		    signal this processor about communication related events

- qcom,remote-pid:
	Usage: required for glink-smem
	Value type: <u32>
	Definition: specifies the identifier of the remote endpoint of this edge

- qcom,rpm-msg-ram:
	Usage: required for glink-rpm
	Value type: <prop-encoded-array>
	Definition: handle to RPM message memory resource

- mboxes:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: reference to the "rpm_hlos" mailbox in APCS, as described
		    in mailbox/mailbox.txt

= GLINK DEVICES
Each subnode of the GLINK node represent function tied to a virtual
communication channel. The name of the nodes are not important. The properties
of these nodes are defined by the individual bindings for the specific function
- but must contain the following property:

- qcom,glink-channels:
	Usage: required
	Value type: <stringlist>
	Definition: a list of channels tied to this function, used for matching
		    the function to a set of virtual channels

- qcom,intents:
	Usage: optional
	Value type: <prop-encoded-array>
	Definition: a list of size,amount pairs describing what intents should
		    be preallocated for this virtual channel. This can be used
		    to tweak the default intents available for the channel to
		    meet expectations of the remote.

= EXAMPLE
The following example represents the GLINK RPM node on a MSM8996 device, with
the function for the "rpm_request" channel defined, which is used for
regulators and root clocks.

	apcs_glb: mailbox@9820000 {
		compatible = "qcom,msm8996-apcs-hmss-global";
		reg = <0x9820000 0x1000>;

		#mbox-cells = <1>;
	};

	rpm_msg_ram: memory@68000 {
		compatible = "qcom,rpm-msg-ram";
		reg = <0x68000 0x6000>;
	};

	rpm-glink {
		compatible = "qcom,glink-rpm";

		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;

		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		mboxes = <&apcs_glb 0>;

		rpm-requests {
			compatible = "qcom,rpm-msm8996";
			qcom,glink-channels = "rpm_requests";

			qcom,intents = <0x400 5
					0x800 1>;
			...
		};
	};


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm General Serial Bus Interface (GSBI)

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  The GSBI controller is modeled as a node with zero or more child nodes, each
  representing a serial sub-node device that is mux'd as part of the GSBI
  configuration settings.  The mode setting will govern the input/output mode
  of the 4 GSBI IOs.

  A GSBI controller node can contain 0 or more child nodes representing serial
  devices.  These serial devices can be a QCOM UART, I2C controller, spi
  controller, or some combination of aforementioned devices.

properties:
  compatible:
    const: qcom,gsbi-v1.0.0

  '#address-cells':
    const: 1

  cell-index:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The GSBI index.

  clocks:
    maxItems: 1

  clock-names:
    const: iface

  qcom,crci:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      CRCI MUX value for QUP CRCI ports.  Please reference
      include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.

  qcom,mode:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      MUX value for configuration of the serial interface.  Please reference
      include/dt-bindings/soc/qcom,gsbi.h for valid mux values.

  '#size-cells':
    const: 1

  syscon-tcsr:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle of TCSR syscon node.Required if child uses dma.

  ranges: true

  reg:
    maxItems: 1

patternProperties:
  "spi@[0-9a-f]+$":
    type: object
    $ref: /schemas/spi/qcom,spi-qup.yaml#

  "i2c@[0-9a-f]+$":
    type: object
    $ref: /schemas/i2c/qcom,i2c-qup.yaml#

  "serial@[0-9a-f]+$":
    type: object
    $ref: /schemas/serial/qcom,msm-uartdm.yaml#

required:
  - compatible
  - cell-index
  - clocks
  - clock-names
  - qcom,mode
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8960.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/soc/qcom,gsbi.h>

    gsbi@12440000 {
        compatible = "qcom,gsbi-v1.0.0";
        reg = <0x12440000 0x100>;
        cell-index = <1>;
        clocks = <&gcc GSBI1_H_CLK>;
        clock-names = "iface";
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        syscon-tcsr = <&tcsr>;
        qcom,mode = <GSBI_PROT_I2C_UART>;

        serial@12450000 {
            compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
            reg = <0x12450000 0x100>,
                  <0x12400000 0x03>;
            interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
            clock-names = "core", "iface";
        };

        i2c@12460000 {
            compatible = "qcom,i2c-qup-v1.1.1";
            reg = <0x12460000 0x1000>;
            pinctrl-0 = <&i2c1_pins>;
            pinctrl-1 = <&i2c1_pins_sleep>;
            pinctrl-names = "default", "sleep";
            interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
            clock-names = "core", "iface";
            #address-cells = <1>;
            #size-cells = <0>;

            status = "disabled"; /* UART chosen */
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm RPMH RSC

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |
  Resource Power Manager Hardened (RPMH) is the mechanism for communicating
  with the hardened resource accelerators on Qualcomm SoCs. Requests to the
  resources can be written to the Trigger Command Set (TCS)  registers and
  using a (addr, val) pair and triggered. Messages in the TCS are then sent in
  sequence over an internal bus.

  The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
  (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
  active/wake resource requests. Multiple such DRVs can exist in a SoC and can
  be written to from Linux. The structure of each DRV follows the same template
  with a few variations that are captured by the properties here.

  A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
  have powered off to facilitate idle power saving. TCS could be classified as::
    ACTIVE  - Triggered by Linux
    SLEEP   - Triggered by F/W
    WAKE    - Triggered by F/W
    CONTROL - Triggered by F/W
  See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>

  The order in which they are described in the DT, should match the hardware
  configuration.

  Requests can be made for the state of a resource, when the subsystem is
  active or idle. When all subsystems like Modem, GPU, CPU are idle, the
  resource state will be an aggregate of the sleep votes from each of those
  subsystems. Clients may request a sleep value for their shared resources in
  addition to the active mode requests.

  Drivers that want to use the RSC to communicate with RPMH must specify their
  bindings as child nodes of the RSC controllers they wish to communicate with.

properties:
  compatible:
    const: qcom,rpmh-rsc

  interrupts:
    minItems: 1
    maxItems: 4
    description:
      The interrupt that trips when a message complete/response is received for
      this DRV from the accelerators.
      Number of interrupts must match number of DRV blocks.

  label:
    description:
      Name for the RSC. The name would be used in trace logs.

  qcom,drv-id:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The ID of the DRV in the RSC block that will be used by this controller.

  qcom,tcs-config:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    minItems: 4
    maxItems: 4
    items:
      items:
        - description: |
            TCS type::
             - ACTIVE_TCS
             - SLEEP_TCS
             - WAKE_TCS
             - CONTROL_TCS
          enum: [ 0, 1, 2, 3 ]
        - description: Number of TCS
    description: |
      The tuple defining the configuration of TCS. Must have two cells which
      describe each TCS type.  The order of the TCS must match the hardware
      configuration.

  qcom,tcs-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The offset of the TCS blocks.

  reg:
    minItems: 1
    maxItems: 4

  reg-names:
    minItems: 1
    items:
      - const: drv-0
      - const: drv-1
      - const: drv-2
      - const: drv-3

  power-domains:
    maxItems: 1

  bcm-voter:
    $ref: /schemas/interconnect/qcom,bcm-voter.yaml#

  clock-controller:
    $ref: /schemas/clock/qcom,rpmhcc.yaml#

  power-controller:
    $ref: /schemas/power/qcom,rpmpd.yaml#

patternProperties:
  '-regulators$':
    $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#

required:
  - compatible
  - interrupts
  - qcom,drv-id
  - qcom,tcs-config
  - qcom,tcs-offset
  - reg
  - reg-names

additionalProperties: false

examples:
  - |
    // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
    // 2, the register offsets for DRV2 start at 0D00, the register
    // calculations are like this::
    // DRV0: 0x179C0000
    // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
    // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
    // TCS-OFFSET: 0xD00
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/soc/qcom,rpmh-rsc.h>

    rsc@179c0000 {
        compatible = "qcom,rpmh-rsc";
        reg = <0x179c0000 0x10000>,
              <0x179d0000 0x10000>,
              <0x179e0000 0x10000>;
        reg-names = "drv-0", "drv-1", "drv-2";
        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
        label = "apps_rsc";
        qcom,tcs-offset = <0xd00>;
        qcom,drv-id = <2>;
        qcom,tcs-config = <ACTIVE_TCS  2>,
                          <SLEEP_TCS   3>,
                          <WAKE_TCS    3>,
                          <CONTROL_TCS 1>;
        power-domains = <&CLUSTER_PD>;
      };

  - |
    // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
    // register offsets for DRV0 start at 01C00, the register calculations are
    // like this::
    // DRV0: 0xAF20000
    // TCS-OFFSET: 0x1C00
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/soc/qcom,rpmh-rsc.h>

    rsc@af20000 {
        compatible = "qcom,rpmh-rsc";
        reg = <0xaf20000 0x10000>;
        reg-names = "drv-0";
        interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
        label = "disp_rsc";
        qcom,tcs-offset = <0x1c00>;
        qcom,drv-id = <0>;
        qcom,tcs-config = <ACTIVE_TCS  0>,
                          <SLEEP_TCS   1>,
                          <WAKE_TCS    1>,
                          <CONTROL_TCS 0>;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    rsc@18200000 {
        compatible = "qcom,rpmh-rsc";
        reg = <0x18200000 0x10000>,
              <0x18210000 0x10000>,
              <0x18220000 0x10000>;
        reg-names = "drv-0", "drv-1", "drv-2";
        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
        label = "apps_rsc";
        qcom,tcs-offset = <0xd00>;
        qcom,drv-id = <2>;
        qcom,tcs-config = <ACTIVE_TCS  2>,
                          <SLEEP_TCS   3>,
                          <WAKE_TCS    3>,
                          <CONTROL_TCS 0>;
        power-domains = <&CLUSTER_PD>;

        clock-controller {
            compatible = "qcom,sm8350-rpmh-clk";
            #clock-cells = <1>;
            clock-names = "xo";
            clocks = <&xo_board>;
        };

        power-controller {
            compatible = "qcom,sm8350-rpmhpd";
            #power-domain-cells = <1>;
            operating-points-v2 = <&rpmhpd_opp_table>;

            rpmhpd_opp_table: opp-table {
                compatible = "operating-points-v2";

                rpmhpd_opp_ret: opp1 {
                    opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
                };

                rpmhpd_opp_min_svs: opp2 {
                    opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
                };

                rpmhpd_opp_low_svs: opp3 {
                    opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
                };

                rpmhpd_opp_svs: opp4 {
                    opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
                };

                rpmhpd_opp_svs_l1: opp5 {
                    opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
                };

                rpmhpd_opp_nom: opp6 {
                    opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
                };

                rpmhpd_opp_nom_l1: opp7 {
                    opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
                };

                rpmhpd_opp_nom_l2: opp8 {
                    opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
                };

                rpmhpd_opp_turbo: opp9 {
                    opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
                };

                rpmhpd_opp_turbo_l1: opp10 {
                    opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
                };
            };
        };

        bcm-voter {
            compatible = "qcom,bcm-voter";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,smd-rpm.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Resource Power Manager (RPM) over SMD/GLINK

description: |
  This driver is used to interface with the Resource Power Manager (RPM) found
  in various Qualcomm platforms. The RPM allows each component in the system
  to vote for state of the system resources, such as clocks, regulators and bus
  frequencies.

  The SMD or GLINK information for the RPM edge should be filled out.  See
  qcom,smd.yaml for the required edge properties.  All SMD/GLINK related
  properties will reside within the RPM node itself.

  The RPM exposes resources to its subnodes.  The rpm_requests node must be
  present and this subnode may contain children that designate regulator
  resources.

  Refer to Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml
  for information on the regulator subnodes that can exist under the
  rpm_requests.

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>

properties:
  compatible:
    enum:
      - qcom,rpm-apq8084
      - qcom,rpm-ipq6018
      - qcom,rpm-msm8226
      - qcom,rpm-msm8909
      - qcom,rpm-msm8916
      - qcom,rpm-msm8936
      - qcom,rpm-msm8953
      - qcom,rpm-msm8974
      - qcom,rpm-msm8976
      - qcom,rpm-msm8996
      - qcom,rpm-msm8998
      - qcom,rpm-sdm660
      - qcom,rpm-sm6115
      - qcom,rpm-sm6125
      - qcom,rpm-sm6375
      - qcom,rpm-qcm2290
      - qcom,rpm-qcs404

  clock-controller:
    $ref: /schemas/clock/qcom,rpmcc.yaml#
    unevaluatedProperties: false

  power-controller:
    $ref: /schemas/power/qcom,rpmpd.yaml#

  qcom,glink-channels:
    $ref: /schemas/types.yaml#/definitions/string-array
    description: Channel name used for the RPM communication
    items:
      - const: rpm_requests

  qcom,smd-channels:
    $ref: /schemas/types.yaml#/definitions/string-array
    description: Channel name used for the RPM communication
    items:
      - const: rpm_requests

patternProperties:
  "^regulators(-[01])?$":
    $ref: /schemas/regulator/qcom,smd-rpm-regulator.yaml#
    unevaluatedProperties: false

if:
  properties:
    compatible:
      contains:
        enum:
          - qcom,rpm-apq8084
          - qcom,rpm-msm8916
          - qcom,rpm-msm8974
          - qcom,rpm-msm8976
          - qcom,rpm-msm8953
then:
  properties:
    qcom,glink-channels: false
  required:
    - qcom,smd-channels
else:
  properties:
    qcom,smd-channels: false
  required:
    - qcom,glink-channels

required:
  - compatible

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    smd {
        compatible = "qcom,smd";

        rpm {
            interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
            qcom,ipc = <&apcs 8 0>;
            qcom,smd-edge = <15>;

            rpm-requests {
                compatible = "qcom,rpm-msm8916";
                qcom,smd-channels = "rpm_requests";

                clock-controller {
                    compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
                    #clock-cells = <1>;
                    clocks = <&xo_board>;
                    clock-names = "xo";
                };

                power-controller {
                    compatible = "qcom,msm8916-rpmpd";
                    #power-domain-cells = <1>;
                    operating-points-v2 = <&rpmpd_opp_table>;

                    rpmpd_opp_table: opp-table {
                        compatible = "operating-points-v2";

                        opp-1 {
                            opp-level = <1>;
                        };
                        opp-2 {
                            opp-level = <2>;
                        };
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,smd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Shared Memory Driver

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  The Qualcomm Shared Memory Driver is a FIFO based communication channel for
  sending data between the various subsystems in Qualcomm platforms.

properties:
  compatible:
    const: qcom,smd

patternProperties:
  "^smd-edge|rpm$":
    $ref: /schemas/remoteproc/qcom,smd-edge.yaml#
    unevaluatedProperties: false
    description:
      Each subnode of the SMD node represents a remote subsystem or a remote
      processor of some sort - or in SMD language an "edge". The name of the
      edges are not important.

required:
  - compatible

additionalProperties: false

examples:
  # The following example represents a smd node, with one edge representing the
  # "rpm" subsystem. For the "rpm" subsystem we have a device tied to the
  # "rpm_request" channel.
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    shared-memory {
        compatible = "qcom,smd";

        rpm {
            interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
            qcom,ipc = <&apcs 8 0>;
            qcom,smd-edge = <15>;

            rpm-requests {
                compatible = "qcom,rpm-msm8974";
                qcom,smd-channels = "rpm_requests";

                clock-controller {
                    compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
                    #clock-cells = <1>;
                };

            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,smem.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Shared Memory Manager binding

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  This binding describes the Qualcomm Shared Memory Manager, a region of
  reserved-memory used to share data between various subsystems and OSes in
  Qualcomm platforms.

properties:
  compatible:
    const: qcom,smem

  reg:
    maxItems: 1

  memory-region:
    maxItems: 1
    description: handle to memory reservation for main SMEM memory region.

  hwlocks:
    maxItems: 1

  qcom,rpm-msg-ram:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: handle to RPM message memory resource

  no-map: true

required:
  - compatible
  - hwlocks

oneOf:
  - required:
      - reg
      - no-map
  - required:
      - memory-region

additionalProperties: false

examples:
  - |
    reserved-memory {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        smem@fa00000 {
            compatible = "qcom,smem";
            reg = <0xfa00000 0x200000>;
            no-map;

            hwlocks = <&tcsr_mutex 3>;
        };
    };
  - |
    reserved-memory {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        smem_region: smem@fa00000 {
            reg = <0xfa00000 0x200000>;
            no-map;
        };
    };

    smem {
        compatible = "qcom,smem";

        memory-region = <&smem_region>;
        qcom,rpm-msg-ram = <&rpm_msg_ram>;

        hwlocks = <&tcsr_mutex 3>;
    };

    soc {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        rpm_msg_ram: sram@fc428000 {
            compatible = "qcom,rpm-msg-ram";
            reg = <0xfc428000 0x4000>;
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,smp2p.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Shared Memory Point 2 Point

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  The Shared Memory Point to Point (SMP2P) protocol facilitates communication
  of a single 32-bit value between two processors.  Each value has a single
  writer (the local side) and a single reader (the remote side).  Values are
  uniquely identified in the system by the directed edge (local processor ID to
  remote processor ID) and a string identifier.

properties:
  compatible:
    const: qcom,smp2p

  interrupts:
    maxItems: 1

  mboxes:
    maxItems: 1
    description:
      Reference to the mailbox representing the outgoing doorbell in APCS for
      this client.

  qcom,ipc:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to a syscon node representing the APCS registers
          - description: u32 representing offset to the register within the syscon
          - description: u32 representing the ipc bit within the register
    description:
      Three entries specifying the outgoing ipc bit used for signaling the
      remote end of the smp2p edge.

  qcom,local-pid:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The identifier of the local endpoint of this edge.

  qcom,remote-pid:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The identifier of the remote endpoint of this edge.

  qcom,smem:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    items:
      maxItems: 2
    description:
      Two identifiers of the inbound and outbound smem items used for this edge.

patternProperties:
  "^master-kernel|slave-kernel|ipa-ap-to-modem|ipa-modem-to-ap|wlan-ap-to-wpss|wlan-wpss-to-ap$":
    type: object
    description:
      Each SMP2P pair contain a set of inbound and outbound entries, these are
      described in subnodes of the smp2p device node. The node names are not
      important.

    properties:
      interrupt-controller:
        description:
          Marks the entry as inbound; the node should be specified as a two
          cell interrupt-controller.  If not specified this node will denote
          the outgoing entry.

      '#interrupt-cells':
        const: 2

      qcom,entry-name:
        $ref: /schemas/types.yaml#/definitions/string
        description:
          The name of this entry, for inbound entries this will be used to
          match against the remotely allocated entry and for outbound entries
          this name is used for allocating entries.

      '#qcom,smem-state-cells':
        $ref: /schemas/types.yaml#/definitions/uint32
        const: 1
        description:
          Required for outgoing entries.

    required:
      - qcom,entry-name

    oneOf:
      - required:
          - interrupt-controller
          - '#interrupt-cells'
      - required:
          - '#qcom,smem-state-cells'

    additionalProperties: false

required:
  - compatible
  - interrupts
  - qcom,local-pid
  - qcom,remote-pid
  - qcom,smem

oneOf:
  - required:
      - mboxes
  - required:
      - qcom,ipc

additionalProperties: false

examples:
  # The following example shows the SMP2P setup with the wireless processor,
  # defined from the 8974 apps processor's point-of-view. It encompasses one
  # inbound and one outbound entry.
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    shared-memory {
        compatible = "qcom,smp2p";
        qcom,smem = <431>, <451>;
        interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
        qcom,ipc = <&apcs 8 18>;
        qcom,local-pid = <0>;
        qcom,remote-pid = <4>;

        wcnss_smp2p_out: master-kernel {
            qcom,entry-name = "master-kernel";
            #qcom,smem-state-cells = <1>;
        };

        wcnss_smp2p_in: slave-kernel {
            qcom,entry-name = "slave-kernel";
            interrupt-controller;
            #interrupt-cells = <2>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,smsm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Shared Memory State Machine

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  The Shared Memory State Machine facilitates broadcasting of single bit state
  information between the processors in a Qualcomm SoC. Each processor is
  assigned 32 bits of state that can be modified. A processor can through a
  matrix of bitmaps signal subscription of notifications upon changes to a
  certain bit owned by a certain remote processor.

properties:
  compatible:
    const: qcom,smsm

  '#address-cells':
    const: 1

  qcom,local-host:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0
    description:
      Identifier of the local processor in the list of hosts, or in other words
      specifier of the column in the subscription matrix representing the local
      processor.

  '#size-cells':
    const: 0

patternProperties:
  "^qcom,ipc-[1-4]$":
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to a syscon node representing the APCS registers
          - description: u32 representing offset to the register within the syscon
          - description: u32 representing the ipc bit within the register
    description:
      Three entries specifying the outgoing ipc bit used for signaling the N:th
      remote processor.

  "@[0-9a-f]$":
    type: object
    description:
      Each processor's state bits are described by a subnode of the SMSM device
      node.  Nodes can either be flagged as an interrupt-controller to denote a
      remote processor's state bits or the local processors bits.  The node
      names are not important.

    properties:
      reg:
        maxItems: 1

      interrupt-controller:
        description:
          Marks the entry as a interrupt-controller and the state bits to
          belong to a remote processor.

      '#interrupt-cells':
        const: 2

      interrupts:
        maxItems: 1
        description:
          One entry specifying remote IRQ used by the remote processor to
          signal changes of its state bits.

      '#qcom,smem-state-cells':
        $ref: /schemas/types.yaml#/definitions/uint32
        const: 1
        description:
          Required for local entry. Denotes bit number.

    required:
      - reg

    oneOf:
      - required:
          - '#qcom,smem-state-cells'
      - required:
          - interrupt-controller
          - '#interrupt-cells'
          - interrupts

    additionalProperties: false

required:
  - compatible
  - '#address-cells'
  - '#size-cells'

anyOf:
  - required:
      - qcom,ipc-1
  - required:
      - qcom,ipc-2
  - required:
      - qcom,ipc-3
  - required:
      - qcom,ipc-4

additionalProperties: false

examples:
  # The following example shows the SMEM setup for controlling properties of
  # the wireless processor, defined from the 8974 apps processor's
  # point-of-view. It encompasses one outbound entry and the outgoing interrupt
  # for the wireless processor.
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    shared-memory {
        compatible = "qcom,smsm";
        #address-cells = <1>;
        #size-cells = <0>;
        qcom,ipc-3 = <&apcs 8 19>;

        apps_smsm: apps@0 {
            reg = <0>;
            #qcom,smem-state-cells = <1>;
        };

        wcnss_smsm: wcnss@7 {
            reg = <7>;
            interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
            interrupt-controller;
            #interrupt-cells = <2>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Subsystem Power Manager binding

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |
  This binding describes the Qualcomm Subsystem Power Manager, used to control
  the peripheral logic surrounding the application cores in Qualcomm platforms.

properties:
  compatible:
    items:
      - enum:
          - qcom,sdm660-gold-saw2-v4.1-l2
          - qcom,sdm660-silver-saw2-v4.1-l2
          - qcom,msm8998-gold-saw2-v4.1-l2
          - qcom,msm8998-silver-saw2-v4.1-l2
          - qcom,msm8909-saw2-v3.0-cpu
          - qcom,msm8916-saw2-v3.0-cpu
          - qcom,msm8939-saw2-v3.0-cpu
          - qcom,msm8226-saw2-v2.1-cpu
          - qcom,msm8974-saw2-v2.1-cpu
          - qcom,msm8976-gold-saw2-v2.3-l2
          - qcom,msm8976-silver-saw2-v2.3-l2
          - qcom,apq8084-saw2-v2.1-cpu
          - qcom,apq8064-saw2-v1.1-cpu
      - const: qcom,saw2

  reg:
    description: Base address and size of the SPM register region
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |

    /* Example 1: SoC using SAW2 and kpss-acc-v2 CPUIdle */
    cpus {
        #address-cells = <1>;
        #size-cells = <0>;

        cpu@0 {
            compatible = "qcom,kryo";
            device_type = "cpu";
            enable-method = "qcom,kpss-acc-v2";
            qcom,saw = <&saw0>;
            reg = <0x0>;
            operating-points-v2 = <&cpu_opp_table>;
        };
    };

    saw0: power-manager@f9089000 {
        compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
        reg = <0xf9089000 0x1000>;
    };

  - |

    /*
     * Example 2: New-gen multi cluster SoC using SAW only for L2;
     * This does not require any cpuidle driver, nor any cpu phandle.
     */
    power-manager@17812000 {
        compatible = "qcom,msm8998-gold-saw2-v4.1-l2", "qcom,saw2";
        reg = <0x17812000 0x1000>;
    };

    power-manager@17912000 {
        compatible = "qcom,msm8998-silver-saw2-v4.1-l2", "qcom,saw2";
        reg = <0x17912000 0x1000>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,wcnss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm WCNSS

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  The Qualcomm WCNSS hardware consists of control block and a BT, WiFi and FM
  radio block, all using SMD as command channels.

properties:
  compatible:
    const: qcom,wcnss

  firmware-name:
    $ref: /schemas/types.yaml#/definitions/string
    default: "wlan/prima/WCNSS_qcom_wlan_nv.bin"
    description:
      Relative firmware image path for the WLAN NV blob.

  qcom,mmio:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      Reference to a node specifying the wcnss "ccu" and "dxe" register blocks.
      The node must be compatible with one of the following::
           - qcom,riva"
           - qcom,pronto"

  qcom,smd-channels:
    $ref: /schemas/types.yaml#/definitions/string
    const: WCNSS_CTRL
    description:
      Standard SMD property specifying the SMD channel used for communication
      with the WiFi firmware.

  bluetooth:
    type: object
    additionalProperties: false
    allOf:
      - $ref: /schemas/net/bluetooth/bluetooth-controller.yaml#
    properties:
      compatible:
        const: qcom,wcnss-bt

      local-bd-address: true

    required:
      - compatible

  wifi:
    additionalProperties: false
    type: object
    properties:
      compatible:
        const: qcom,wcnss-wlan

      interrupts:
        maxItems: 2

      interrupt-names:
        items:
          - const: tx
          - const: rx

      qcom,smem-states:
        $ref: /schemas/types.yaml#/definitions/phandle-array
        maxItems: 2
        description:
          Should reference the tx-enable and tx-rings-empty SMEM states.

      qcom,smem-state-names:
        items:
          - const: tx-enable
          - const: tx-rings-empty
        description:
          Names of SMEM states.

    required:
      - compatible
      - interrupts
      - interrupt-names
      - qcom,smem-states
      - qcom,smem-state-names

required:
  - compatible
  - qcom,mmio
  - qcom,smd-channels

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    smd-edge {
        interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;

        qcom,ipc = <&apcs 8 17>;
        qcom,smd-edge = <6>;
        qcom,remote-pid = <4>;

        label = "pronto";

        wcnss {
            compatible = "qcom,wcnss";
            qcom,smd-channels = "WCNSS_CTRL";

            qcom,mmio = <&pronto>;

            bluetooth {
                compatible = "qcom,wcnss-bt";
                /* BD address 00:11:22:33:44:55 */
                local-bd-address = [ 55 44 33 22 11 00 ];
            };

            wifi {
                compatible = "qcom,wcnss-wlan";

                interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "tx", "rx";

                qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
                qcom,smem-state-names = "tx-enable", "tx-rings-empty";
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom-stats.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. (QTI) Stats bindings

maintainers:
  - Maulik Shah <mkshah@codeaurora.org>

description:
  Always On Processor/Resource Power Manager maintains statistics of the SoC
  sleep modes involving powering down of the rails and oscillator clock.

  Statistics includes SoC sleep mode type, number of times low power mode were
  entered, time of last entry, time of last exit and accumulated sleep duration.

properties:
  compatible:
    enum:
      - qcom,rpmh-stats
      - qcom,sdm845-rpmh-stats
      - qcom,rpm-stats
      # For older RPM firmware versions with fixed offset for the sleep stats
      - qcom,apq8084-rpm-stats
      - qcom,msm8226-rpm-stats
      - qcom,msm8916-rpm-stats
      - qcom,msm8974-rpm-stats

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  # Example of rpmh sleep stats
  - |
    sram@c3f0000 {
      compatible = "qcom,rpmh-stats";
      reg = <0x0c3f0000 0x400>;
    };
  # Example of rpm sleep stats
  - |
    sram@4690000 {
      compatible = "qcom,rpm-stats";
      reg = <0x04690000 0x10000>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g011-sys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/V2M System Configuration (SYS)

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

description:
  The RZ/V2M-alike SYS (System Configuration) controls the overall
  configuration of the LSI and supports the following functions,
  - Bank address settings for DMAC
  - Bank address settings of the units for ICB
  - ETHER AxCACHE[1] (C bit) control function
  - RAMA initialization control
  - MD[7:0] pin monitoring
  - LSI version
  - PCIe related settings
  - WDT stop control
  - Temperature sensor (TSU) monitor

properties:
  compatible:
    const: renesas,r9a09g011-sys

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    sys: system-controller@a3f03000 {
      compatible = "renesas,r9a09g011-sys";
      reg = <0xa3f03000 0x400>;
    };