code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Apple T8103 "M1" SoC
 *
 * Other names: H13G, "Tonga"
 *
 * Copyright The Asahi Linux Contributors
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>

/ {
	compatible = "apple,t8103", "apple,arm-platform";

	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu_e0>;
				};
				core1 {
					cpu = <&cpu_e1>;
				};
				core2 {
					cpu = <&cpu_e2>;
				};
				core3 {
					cpu = <&cpu_e3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu_p0>;
				};
				core1 {
					cpu = <&cpu_p1>;
				};
				core2 {
					cpu = <&cpu_p2>;
				};
				core3 {
					cpu = <&cpu_p3>;
				};
			};
		};

		cpu_e0: cpu@0 {
			compatible = "apple,icestorm";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			operating-points-v2 = <&ecluster_opp>;
			capacity-dmips-mhz = <714>;
			performance-domains = <&cpufreq_e>;
			next-level-cache = <&l2_cache_0>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
		};

		cpu_e1: cpu@1 {
			compatible = "apple,icestorm";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			operating-points-v2 = <&ecluster_opp>;
			capacity-dmips-mhz = <714>;
			performance-domains = <&cpufreq_e>;
			next-level-cache = <&l2_cache_0>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
		};

		cpu_e2: cpu@2 {
			compatible = "apple,icestorm";
			device_type = "cpu";
			reg = <0x0 0x2>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			operating-points-v2 = <&ecluster_opp>;
			capacity-dmips-mhz = <714>;
			performance-domains = <&cpufreq_e>;
			next-level-cache = <&l2_cache_0>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
		};

		cpu_e3: cpu@3 {
			compatible = "apple,icestorm";
			device_type = "cpu";
			reg = <0x0 0x3>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			operating-points-v2 = <&ecluster_opp>;
			capacity-dmips-mhz = <714>;
			performance-domains = <&cpufreq_e>;
			next-level-cache = <&l2_cache_0>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
		};

		cpu_p0: cpu@10100 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10100>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			operating-points-v2 = <&pcluster_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p>;
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
		};

		cpu_p1: cpu@10101 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10101>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			operating-points-v2 = <&pcluster_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p>;
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
		};

		cpu_p2: cpu@10102 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10102>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			operating-points-v2 = <&pcluster_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p>;
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
		};

		cpu_p3: cpu@10103 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10103>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			operating-points-v2 = <&pcluster_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p>;
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
		};

		l2_cache_0: l2-cache-0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x400000>;
		};

		l2_cache_1: l2-cache-1 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0xc00000>;
		};
	};

	ecluster_opp: opp-table-0 {
		compatible = "operating-points-v2";

		opp01 {
			opp-hz = /bits/ 64 <600000000>;
			opp-level = <1>;
			clock-latency-ns = <7500>;
		};
		opp02 {
			opp-hz = /bits/ 64 <972000000>;
			opp-level = <2>;
			clock-latency-ns = <22000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <1332000000>;
			opp-level = <3>;
			clock-latency-ns = <27000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1704000000>;
			opp-level = <4>;
			clock-latency-ns = <33000>;
		};
		opp05 {
			opp-hz = /bits/ 64 <2064000000>;
			opp-level = <5>;
			clock-latency-ns = <50000>;
		};
	};

	pcluster_opp: opp-table-1 {
		compatible = "operating-points-v2";

		opp01 {
			opp-hz = /bits/ 64 <600000000>;
			opp-level = <1>;
			clock-latency-ns = <8000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <828000000>;
			opp-level = <2>;
			clock-latency-ns = <19000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <1056000000>;
			opp-level = <3>;
			clock-latency-ns = <21000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1284000000>;
			opp-level = <4>;
			clock-latency-ns = <23000>;
		};
		opp05 {
			opp-hz = /bits/ 64 <1500000000>;
			opp-level = <5>;
			clock-latency-ns = <24000>;
		};
		opp06 {
			opp-hz = /bits/ 64 <1728000000>;
			opp-level = <6>;
			clock-latency-ns = <29000>;
		};
		opp07 {
			opp-hz = /bits/ 64 <1956000000>;
			opp-level = <7>;
			clock-latency-ns = <31000>;
		};
		opp08 {
			opp-hz = /bits/ 64 <2184000000>;
			opp-level = <8>;
			clock-latency-ns = <34000>;
		};
		opp09 {
			opp-hz = /bits/ 64 <2388000000>;
			opp-level = <9>;
			clock-latency-ns = <36000>;
		};
		opp10 {
			opp-hz = /bits/ 64 <2592000000>;
			opp-level = <10>;
			clock-latency-ns = <51000>;
		};
		opp11 {
			opp-hz = /bits/ 64 <2772000000>;
			opp-level = <11>;
			clock-latency-ns = <54000>;
		};
		opp12 {
			opp-hz = /bits/ 64 <2988000000>;
			opp-level = <12>;
			clock-latency-ns = <55000>;
		};
#if 0
		/* Not available until CPU deep sleep is implemented */
		opp13 {
			opp-hz = /bits/ 64 <3096000000>;
			opp-level = <13>;
			clock-latency-ns = <55000>;
			turbo-mode;
		};
		opp14 {
			opp-hz = /bits/ 64 <3144000000>;
			opp-level = <14>;
			clock-latency-ns = <56000>;
			turbo-mode;
		};
		opp15 {
			opp-hz = /bits/ 64 <3204000000>;
			opp-level = <15>;
			clock-latency-ns = <56000>;
			turbo-mode;
		};
#endif
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&aic>;
		interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
		interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
	};

	pmu-e {
		compatible = "apple,icestorm-pmu";
		interrupt-parent = <&aic>;
		interrupts = <AIC_FIQ AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
	};

	pmu-p {
		compatible = "apple,firestorm-pmu";
		interrupt-parent = <&aic>;
		interrupts = <AIC_FIQ AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
	};

	clkref: clock-ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "clkref";
	};

	/*
	 * This is a fabulated representation of the input clock
	 * to NCO since we don't know the true clock tree.
	 */
	nco_clkref: clock-ref-nco {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "nco_ref";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;

		ranges;
		nonposted-mmio;

		cpufreq_e: performance-controller@210e20000 {
			compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
			reg = <0x2 0x10e20000 0 0x1000>;
			#performance-domain-cells = <0>;
		};

		cpufreq_p: performance-controller@211e20000 {
			compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
			reg = <0x2 0x11e20000 0 0x1000>;
			#performance-domain-cells = <0>;
		};

		sio_dart: iommu@235004000 {
			compatible = "apple,t8103-dart";
			reg = <0x2 0x35004000 0x0 0x4000>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
			power-domains = <&ps_sio_cpu>;
		};

		i2c0: i2c@235010000 {
			compatible = "apple,t8103-i2c", "apple,i2c";
			reg = <0x2 0x35010000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&i2c0_pins>;
			pinctrl-names = "default";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			power-domains = <&ps_i2c0>;
		};

		i2c1: i2c@235014000 {
			compatible = "apple,t8103-i2c", "apple,i2c";
			reg = <0x2 0x35014000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 628 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&i2c1_pins>;
			pinctrl-names = "default";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			power-domains = <&ps_i2c1>;
		};

		i2c2: i2c@235018000 {
			compatible = "apple,t8103-i2c", "apple,i2c";
			reg = <0x2 0x35018000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 629 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&i2c2_pins>;
			pinctrl-names = "default";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled"; /* not used in all devices */
			power-domains = <&ps_i2c2>;
		};

		i2c3: i2c@23501c000 {
			compatible = "apple,t8103-i2c", "apple,i2c";
			reg = <0x2 0x3501c000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 630 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&i2c3_pins>;
			pinctrl-names = "default";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			power-domains = <&ps_i2c3>;
		};

		i2c4: i2c@235020000 {
			compatible = "apple,t8103-i2c", "apple,i2c";
			reg = <0x2 0x35020000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 631 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&i2c4_pins>;
			pinctrl-names = "default";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			power-domains = <&ps_i2c4>;
			status = "disabled"; /* only used in J293 */
		};

		serial0: serial@235200000 {
			compatible = "apple,s5l-uart";
			reg = <0x2 0x35200000 0x0 0x1000>;
			reg-io-width = <4>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>;
			/*
			 * TODO: figure out the clocking properly, there may
			 * be a third selectable clock.
			 */
			clocks = <&clkref>, <&clkref>;
			clock-names = "uart", "clk_uart_baud0";
			power-domains = <&ps_uart0>;
			status = "disabled";
		};

		serial2: serial@235208000 {
			compatible = "apple,s5l-uart";
			reg = <0x2 0x35208000 0x0 0x1000>;
			reg-io-width = <4>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkref>, <&clkref>;
			clock-names = "uart", "clk_uart_baud0";
			power-domains = <&ps_uart2>;
			status = "disabled";
		};

		admac: dma-controller@238200000 {
			compatible = "apple,t8103-admac", "apple,admac";
			reg = <0x2 0x38200000 0x0 0x34000>;
			dma-channels = <24>;
			interrupts-extended = <0>,
					      <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>,
					      <0>,
					      <0>;
			#dma-cells = <1>;
			iommus = <&sio_dart 2>;
			power-domains = <&ps_sio_adma>;
			resets = <&ps_audio_p>;
		};

		mca: i2s@238400000 {
			compatible = "apple,t8103-mca", "apple,mca";
			reg = <0x2 0x38400000 0x0 0x18000>,
			      <0x2 0x38300000 0x0 0x30000>;

			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 619 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 620 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 621 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 622 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 623 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 624 IRQ_TYPE_LEVEL_HIGH>;

			resets = <&ps_audio_p>;
			clocks = <&nco 0>, <&nco 1>, <&nco 2>,
				 <&nco 3>, <&nco 4>, <&nco 4>;
			power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
					<&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>;
			dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>,
			       <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>,
			       <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>,
			       <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>,
			       <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>,
			       <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>;
			dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
				"tx1a", "rx1a", "tx1b", "rx1b",
				"tx2a", "rx2a", "tx2b", "rx2b",
				"tx3a", "rx3a", "tx3b", "rx3b",
				"tx4a", "rx4a", "tx4b", "rx4b",
				"tx5a", "rx5a", "tx5b", "rx5b";

			#sound-dai-cells = <1>;
		};

		nco: clock-controller@23b044000 {
			compatible = "apple,t8103-nco", "apple,nco";
			reg = <0x2 0x3b044000 0x0 0x14000>;
			clocks = <&nco_clkref>;
			#clock-cells = <1>;
		};

		aic: interrupt-controller@23b100000 {
			compatible = "apple,t8103-aic", "apple,aic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x2 0x3b100000 0x0 0x8000>;
			power-domains = <&ps_aic>;

			affinities {
				e-core-pmu-affinity {
					apple,fiq-index = <AIC_CPU_PMU_E>;
					cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>;
				};

				p-core-pmu-affinity {
					apple,fiq-index = <AIC_CPU_PMU_P>;
					cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>;
				};
			};
		};

		pmgr: power-management@23b700000 {
			compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2 0x3b700000 0 0x14000>;
		};

		pinctrl_ap: pinctrl@23c100000 {
			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
			reg = <0x2 0x3c100000 0x0 0x100000>;
			power-domains = <&ps_gpio>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_ap 0 0 212>;
			apple,npins = <212>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>;

			i2c0_pins: i2c0-pins {
				pinmux = <APPLE_PINMUX(192, 1)>,
					 <APPLE_PINMUX(188, 1)>;
			};

			i2c1_pins: i2c1-pins {
				pinmux = <APPLE_PINMUX(201, 1)>,
					 <APPLE_PINMUX(199, 1)>;
			};

			i2c2_pins: i2c2-pins {
				pinmux = <APPLE_PINMUX(163, 1)>,
					 <APPLE_PINMUX(162, 1)>;
			};

			i2c3_pins: i2c3-pins {
				pinmux = <APPLE_PINMUX(73, 1)>,
					 <APPLE_PINMUX(72, 1)>;
			};

			i2c4_pins: i2c4-pins {
				pinmux = <APPLE_PINMUX(135, 1)>,
					 <APPLE_PINMUX(134, 1)>;
			};

			pcie_pins: pcie-pins {
				pinmux = <APPLE_PINMUX(150, 1)>,
					 <APPLE_PINMUX(151, 1)>,
					 <APPLE_PINMUX(32, 1)>;
			};
		};

		pinctrl_nub: pinctrl@23d1f0000 {
			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
			reg = <0x2 0x3d1f0000 0x0 0x4000>;
			power-domains = <&ps_nub_gpio>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_nub 0 0 23>;
			apple,npins = <23>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>;
		};

		pmgr_mini: power-management@23d280000 {
			compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x2 0x3d280000 0 0x4000>;
		};

		wdt: watchdog@23d2b0000 {
			compatible = "apple,t8103-wdt", "apple,wdt";
			reg = <0x2 0x3d2b0000 0x0 0x4000>;
			clocks = <&clkref>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 338 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_smc: pinctrl@23e820000 {
			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
			reg = <0x2 0x3e820000 0x0 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_smc 0 0 16>;
			apple,npins = <16>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_aop: pinctrl@24a820000 {
			compatible = "apple,t8103-pinctrl", "apple,pinctrl";
			reg = <0x2 0x4a820000 0x0 0x4000>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl_aop 0 0 42>;
			apple,npins = <42>;

			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>;
		};

		ans_mbox: mbox@277408000 {
			compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
			reg = <0x2 0x77408000 0x0 0x4000>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ 584 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ 585 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "send-empty", "send-not-empty",
				"recv-empty", "recv-not-empty";
			#mbox-cells = <0>;
			power-domains = <&ps_ans2>;
		};

		sart: iommu@27bc50000 {
			compatible = "apple,t8103-sart";
			reg = <0x2 0x7bc50000 0x0 0x10000>;
			power-domains = <&ps_ans2>;
		};

		nvme@27bcc0000 {
			compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";
			reg = <0x2 0x7bcc0000 0x0 0x40000>,
				<0x2 0x77400000 0x0 0x4000>;
			reg-names = "nvme", "ans";
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>;
			mboxes = <&ans_mbox>;
			apple,sart = <&sart>;
			power-domains = <&ps_ans2>, <&ps_apcie_st>;
			power-domain-names = "ans", "apcie0";
			resets = <&ps_ans2>;
		};

		pcie0_dart_0: iommu@681008000 {
			compatible = "apple,t8103-dart";
			reg = <0x6 0x81008000 0x0 0x4000>;
			#iommu-cells = <1>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&ps_apcie_gp>;
		};

		pcie0_dart_1: iommu@682008000 {
			compatible = "apple,t8103-dart";
			reg = <0x6 0x82008000 0x0 0x4000>;
			#iommu-cells = <1>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&ps_apcie_gp>;
		};

		pcie0_dart_2: iommu@683008000 {
			compatible = "apple,t8103-dart";
			reg = <0x6 0x83008000 0x0 0x4000>;
			#iommu-cells = <1>;
			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&ps_apcie_gp>;
		};

		pcie0: pcie@690000000 {
			compatible = "apple,t8103-pcie", "apple,pcie";
			device_type = "pci";

			reg = <0x6 0x90000000 0x0 0x1000000>,
			      <0x6 0x80000000 0x0 0x100000>,
			      <0x6 0x81000000 0x0 0x4000>,
			      <0x6 0x82000000 0x0 0x4000>,
			      <0x6 0x83000000 0x0 0x4000>;
			reg-names = "config", "rc", "port0", "port1", "port2";

			interrupt-parent = <&aic>;
			interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
				     <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;

			msi-controller;
			msi-parent = <&pcie0>;
			msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;

			iommu-map = <0x100 &pcie0_dart_0 1 1>,
				    <0x200 &pcie0_dart_1 1 1>,
				    <0x300 &pcie0_dart_2 1 1>;
			iommu-map-mask = <0xff00>;

			bus-range = <0 3>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
				 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;

			power-domains = <&ps_apcie_gp>;
			pinctrl-0 = <&pcie_pins>;
			pinctrl-names = "default";

			port00: pci@0,0 {
				device_type = "pci";
				reg = <0x0 0x0 0x0 0x0 0x0>;
				reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges;

				interrupt-controller;
				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
						<0 0 0 2 &port00 0 0 0 1>,
						<0 0 0 3 &port00 0 0 0 2>,
						<0 0 0 4 &port00 0 0 0 3>;
			};

			port01: pci@1,0 {
				device_type = "pci";
				reg = <0x800 0x0 0x0 0x0 0x0>;
				reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges;

				interrupt-controller;
				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
						<0 0 0 2 &port01 0 0 0 1>,
						<0 0 0 3 &port01 0 0 0 2>,
						<0 0 0 4 &port01 0 0 0 3>;
			};

			port02: pci@2,0 {
				device_type = "pci";
				reg = <0x1000 0x0 0x0 0x0 0x0>;
				reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges;

				interrupt-controller;
				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
						<0 0 0 2 &port02 0 0 0 1>,
						<0 0 0 3 &port02 0 0 0 2>,
						<0 0 0 4 &port02 0 0 0 3>;
			};
		};
	};
};

#include "t8103-pmgr.dtsi"


code:
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_VEXPRESS) += \
	foundation-v8.dtb foundation-v8-psci.dtb \
	foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb juno-r1-scmi.dtb juno-r2-scmi.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0 or MIT
/*
 * Copyright (c) 2022, Arm Limited. All rights reserved.
 * Copyright (c) 2022, Linaro Limited. All rights reserved.
 *
 */

/dts-v1/;

#include "corstone1000.dtsi"

/ {
	model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
	compatible = "arm,corstone1000-fvp";

	smsc: ethernet@4010000 {
		compatible = "smsc,lan91c111";
		reg = <0x40100000 0x10000>;
		phy-mode = "mii";
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		reg-io-width = <2>;
	};

	vmmc_v3_3d: fixed_v3_3d {
		compatible = "regulator-fixed";
		regulator-name = "vmmc_supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	sdmmc0: mmc@40300000 {
		compatible = "arm,pl18x", "arm,primecell";
		reg = <0x40300000 0x1000>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		max-frequency = <12000000>;
		vmmc-supply = <&vmmc_v3_3d>;
		clocks = <&smbclk>, <&refclk100mhz>;
		clock-names = "smclk", "apb_pclk";
	};

	sdmmc1: mmc@50000000 {
		compatible = "arm,pl18x", "arm,primecell";
		reg = <0x50000000 0x10000>;
		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
		max-frequency = <12000000>;
		vmmc-supply = <&vmmc_v3_3d>;
		clocks = <&smbclk>, <&refclk100mhz>;
		clock-names = "smclk", "apb_pclk";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0 or MIT
/*
 * Copyright (c) 2022, Arm Limited. All rights reserved.
 * Copyright (c) 2022, Linaro Limited. All rights reserved.
 *
 */

/dts-v1/;

#include "corstone1000.dtsi"

/ {
	model = "ARM Corstone1000 FPGA MPS3 board";
	compatible = "arm,corstone1000-mps3";

	smsc: ethernet@4010000 {
		compatible = "smsc,lan9220", "smsc,lan9115";
		reg = <0x40100000 0x10000>;
		phy-mode = "mii";
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		reg-io-width = <2>;
		smsc,irq-push-pull;
	};

	usb_host: usb@40200000 {
		compatible = "nxp,usb-isp1763";
		reg = <0x40200000 0x100000>;
		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
		bus-width = <16>;
		dr_mode = "host";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0 or MIT
/*
 * Copyright (c) 2022, Arm Limited. All rights reserved.
 * Copyright (c) 2022, Linaro Limited. All rights reserved.
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0>;
			next-level-cache = <&L2_0>;
		};
	};

	memory@88200000 {
		device_type = "memory";
		reg = <0x88200000 0x77e00000>;
	};

	gic: interrupt-controller@1c000000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg =	<0x1c010000 0x1000>,
			<0x1c02f000 0x2000>,
			<0x1c04f000 0x1000>,
			<0x1c06f000 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
			      IRQ_TYPE_LEVEL_LOW)>;
	};

	L2_0: l2-cache0 {
		compatible = "cache";
		cache-unified;
		cache-level = <2>;
		cache-size = <0x80000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
	};

	refclk100mhz: refclk100mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "apb_pclk";
	};

	smbclk: refclk24mhzx2 {
		/* Reference 24MHz clock x 2 */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <48000000>;
		clock-output-names = "smclk";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts =	<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
				 IRQ_TYPE_LEVEL_LOW)>,
				<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
				 IRQ_TYPE_LEVEL_LOW)>,
				<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
				 IRQ_TYPE_LEVEL_LOW)>,
				<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
				 IRQ_TYPE_LEVEL_LOW)>;
	};

	uartclk: uartclk {
		/* UART clock - 50MHz */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
		clock-output-names = "uartclk";
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;
		ranges;

		timer@1a220000 {
			compatible = "arm,armv7-timer-mem";
			reg = <0x1a220000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			clock-frequency = <50000000>;
			ranges;

			frame@1a230000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x1a230000 0x1000>;
			};
		};

		uart0: serial@1a510000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x1a510000 0x1000>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&refclk100mhz>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart1: serial@1a520000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x1a520000 0x1000>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&refclk100mhz>;
			clock-names = "uartclk", "apb_pclk";
		};

		mhu_hse1: mailbox@1b820000 {
			compatible = "arm,mhuv2-tx", "arm,primecell";
			reg = <0x1b820000 0x1000>;
			clocks = <&refclk100mhz>;
			clock-names = "apb_pclk";
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			#mbox-cells = <2>;
			arm,mhuv2-protocols = <0 0>;
			secure-status = "okay";     /* secure-world-only */
			status = "disabled";
		};

		mhu_seh1: mailbox@1b830000 {
			compatible = "arm,mhuv2-rx", "arm,primecell";
			reg = <0x1b830000 0x1000>;
			clocks = <&refclk100mhz>;
			clock-names = "apb_pclk";
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			#mbox-cells = <2>;
			arm,mhuv2-protocols = <0 0>;
			secure-status = "okay";     /* secure-world-only */
			status = "disabled";
		};
	};
};


code:
/*
 * ARM Ltd.
 *
 * ARMv8 Foundation model DTS (GICv2 configuration)
 */

/ {
	gic: interrupt-controller@2c001000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <1>;
		interrupt-controller;
		reg = <0x0 0x2c001000 0 0x1000>,
		      <0x0 0x2c002000 0 0x2000>,
		      <0x0 0x2c004000 0 0x2000>,
		      <0x0 0x2c006000 0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};
};


code:
/*
 * ARM Ltd.
 *
 * ARMv8 Foundation model DTS (GICv3+PSCI configuration)
 */

#include "foundation-v8.dtsi"
#include "foundation-v8-gicv3.dtsi"
#include "foundation-v8-psci.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd.
 *
 * ARMv8 Foundation model DTS (GICv3 configuration)
 */

#include "foundation-v8.dtsi"
#include "foundation-v8-gicv3.dtsi"
#include "foundation-v8-spin-table.dtsi"


code:
/*
 * ARM Ltd.
 *
 * ARMv8 Foundation model DTS (GICv3 configuration)
 */

/ {
	gic: interrupt-controller@2f000000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x2f000000 0x100000>;
		interrupt-controller;
		reg =	<0x0 0x2f000000 0x0 0x10000>,
			<0x0 0x2f100000 0x0 0x200000>,
			<0x0 0x2c000000 0x0 0x2000>,
			<0x0 0x2c010000 0x0 0x2000>,
			<0x0 0x2c02f000 0x0 0x2000>;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		its: msi-controller@2f020000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x20000 0x20000>;
		};
	};
};


code:
/*
 * ARM Ltd.
 *
 * ARMv8 Foundation model DTS (GICv2+PSCI configuration)
 */

#include "foundation-v8.dtsi"
#include "foundation-v8-gicv2.dtsi"
#include "foundation-v8-psci.dtsi"


code:
/*
 * ARM Ltd.
 *
 * ARMv8 Foundation model DTS (PSCI configuration)
 */

/ {
	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};
};

&cpu0 {
	enable-method = "psci";
};

&cpu1 {
	enable-method = "psci";
};

&cpu2 {
	enable-method = "psci";
};

&cpu3 {
	enable-method = "psci";
};


code:
/*
 * ARM Ltd.
 *
 * ARMv8 Foundation model DTS (spin table configuration)
 */

&cpu0 {
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x8000fff8>;
};

&cpu1 {
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x8000fff8>;
};

&cpu2 {
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x8000fff8>;
};

&cpu3 {
	enable-method = "spin-table";
	cpu-release-addr = <0x0 0x8000fff8>;
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd.
 *
 * ARMv8 Foundation model DTS (GICv2 configuration)
 */

#include "foundation-v8.dtsi"
#include "foundation-v8-gicv2.dtsi"
#include "foundation-v8-spin-table.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd.
 *
 * ARMv8 Foundation model DTS
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>

/memreserve/ 0x80000000 0x00010000;

/ {
	model = "Foundation-v8A";
	compatible = "arm,foundation-aarch64", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			next-level-cache = <&L2_0>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x1>;
			next-level-cache = <&L2_0>;
		};
		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x2>;
			next-level-cache = <&L2_0>;
		};
		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x3>;
			next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x80000000>,
		      <0x00000008 0x80000000 0 0x80000000>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <100000000>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	};

	spe-pmu {
		compatible = "arm,statistical-profiling-extension-v1";
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	watchdog@2a440000 {
		compatible = "arm,sbsa-gwdt";
		reg = <0x0 0x2a440000 0 0x1000>,
			<0x0 0x2a450000 0 0x1000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
		timeout-sec = <30>;
	};

	v2m_clk24mhz: clk24mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "v2m:clk24mhz";
	};

	v2m_refclk1mhz: refclk1mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <1000000>;
		clock-output-names = "v2m:refclk1mhz";
	};

	v2m_refclk32khz: refclk32khz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "v2m:refclk32khz";
	};

	bus@8000000 {
		compatible = "arm,vexpress,v2m-p1", "simple-bus";
		#address-cells = <2>; /* SMB chipselect number and offset */
		#size-cells = <1>;

		ranges = <0 0 0 0x08000000 0x04000000>,
			 <1 0 0 0x14000000 0x04000000>,
			 <2 0 0 0x18000000 0x04000000>,
			 <3 0 0 0x1c000000 0x04000000>,
			 <4 0 0 0x0c000000 0x04000000>,
			 <5 0 0 0x10000000 0x04000000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  1 &gic 0 GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  2 &gic 0 GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  3 &gic 0 GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  4 &gic 0 GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  5 &gic 0 GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  6 &gic 0 GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  7 &gic 0 GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  8 &gic 0 GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  9 &gic 0 GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;

		ethernet@202000000 {
			compatible = "smsc,lan91c111";
			reg = <2 0x02000000 0x10000>;
			interrupts = <15>;
		};

		iofpga-bus@300000000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 3 0 0x200000>;

			v2m_sysreg: sysreg@10000 {
				compatible = "arm,vexpress-sysreg";
				reg = <0x010000 0x1000>;
			};

			v2m_serial0: serial@90000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x090000 0x1000>;
				interrupts = <5>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial1: serial@a0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0a0000 0x1000>;
				interrupts = <6>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial2: serial@b0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0b0000 0x1000>;
				interrupts = <7>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial3: serial@c0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0c0000 0x1000>;
				interrupts = <8>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
			};

			virtio@130000 {
				compatible = "virtio,mmio";
				reg = <0x130000 0x200>;
				interrupts = <42>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Fast Models
 *
 * Architecture Envelope Model (AEM) ARMv8-A
 * ARMAEMv8AMPCT
 *
 * FVP Base RevC
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>

/memreserve/ 0x80000000 0x00010000;

#include "rtsm_ve-motherboard.dtsi"
#include "rtsm_ve-motherboard-rs2.dtsi"

/ {
	model = "FVP Base RevC";
	compatible = "arm,fvp-base-revc", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x000>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&C0_L2>;
		};
		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&C0_L2>;
		};
		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&C0_L2>;
		};
		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&C0_L2>;
		};
		cpu4: cpu@10000 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x10000>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&C1_L2>;
		};
		cpu5: cpu@10100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x10100>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&C1_L2>;
		};
		cpu6: cpu@10200 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x10200>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&C1_L2>;
		};
		cpu7: cpu@10300 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x10300>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&C1_L2>;
		};
		C0_L2: l2-cache0 {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-level = <2>;
			cache-unified;
		};

		C1_L2: l2-cache1 {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-level = <2>;
			cache-unified;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x80000000>,
		      <0x00000008 0x80000000 0 0x80000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* Chipselect 2,00000000 is physically at 0x18000000 */
		vram: vram@18000000 {
			/* 8 MB of designated video RAM */
			compatible = "shared-dma-pool";
			reg = <0x00000000 0x18000000 0 0x00800000>;
			no-map;
		};
	};

	gic: interrupt-controller@2f000000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-controller;
		reg = <0x0 0x2f000000 0 0x10000>,	// GICD
		      <0x0 0x2f100000 0 0x200000>,	// GICR
		      <0x0 0x2c000000 0 0x2000>,	// GICC
		      <0x0 0x2c010000 0 0x2000>,	// GICH
		      <0x0 0x2c02f000 0 0x2000>;	// GICV
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		its: msi-controller@2f020000 {
			#msi-cells = <1>;
			compatible = "arm,gic-v3-its";
			reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
			msi-controller;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	spe-pmu {
		compatible = "arm,statistical-profiling-extension-v1";
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	pci: pci@40000000 {
		#address-cells = <0x3>;
		#size-cells = <0x2>;
		#interrupt-cells = <0x1>;
		compatible = "pci-host-ecam-generic";
		device_type = "pci";
		bus-range = <0x0 0x1>;
		reg = <0x0 0x40000000 0x0 0x10000000>;
		ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;
		interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-map-mask = <0x0 0x0 0x0 0x7>;
		msi-map = <0x0 &its 0x0 0x10000>;
		iommu-map = <0x0 &smmu 0x0 0x10000>;

		dma-coherent;
	};

	smmu: iommu@2b400000 {
		compatible = "arm,smmu-v3";
		reg = <0x0 0x2b400000 0x0 0x100000>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
		dma-coherent;
		#iommu-cells = <1>;
		msi-parent = <&its 0x10000>;
	};

	panel {
		compatible = "arm,rtsm-display";
		port {
			panel_in: endpoint {
				remote-endpoint = <&clcd_pads>;
			};
		};
	};

	bus@8000000 {
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic 0 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  1 &gic 0 0 GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  2 &gic 0 0 GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  3 &gic 0 0 GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  4 &gic 0 0 GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  5 &gic 0 0 GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  6 &gic 0 0 GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  7 &gic 0 0 GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  8 &gic 0 0 GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  9 &gic 0 0 GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
#include "juno-clocks.dtsi"
#include "juno-motherboard.dtsi"

/ {
	/*
	 *  Devices shared by all Juno boards
	 */

	memtimer: timer@2a810000 {
		compatible = "arm,armv7-timer-mem";
		reg = <0x0 0x2a810000 0x0 0x10000>;
		clock-frequency = <50000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x0 0x2a820000 0x20000>;
		status = "disabled";
		frame@2a830000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x10000 0x10000>;
		};
	};

	mailbox: mhu@2b1f0000 {
		compatible = "arm,mhu", "arm,primecell";
		reg = <0x0 0x2b1f0000 0x0 0x1000>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <1>;
		clocks = <&soc_refclk100mhz>;
		clock-names = "apb_pclk";
	};

	smmu_gpu: iommu@2b400000 {
		compatible = "arm,mmu-400", "arm,smmu-v1";
		reg = <0x0 0x2b400000 0x0 0x10000>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		#global-interrupts = <1>;
		power-domains = <&scpi_devpd 1>;
		dma-coherent;
		status = "disabled";
	};

	smmu_pcie: iommu@2b500000 {
		compatible = "arm,mmu-401", "arm,smmu-v1";
		reg = <0x0 0x2b500000 0x0 0x10000>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		#global-interrupts = <1>;
		dma-coherent;
		status = "disabled";
	};

	smmu_etr: iommu@2b600000 {
		compatible = "arm,mmu-401", "arm,smmu-v1";
		reg = <0x0 0x2b600000 0x0 0x10000>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		#global-interrupts = <1>;
		dma-coherent;
		power-domains = <&scpi_devpd 0>;
	};

	gic: interrupt-controller@2c010000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		reg = <0x0 0x2c010000 0 0x1000>,
		      <0x0 0x2c02f000 0 0x2000>,
		      <0x0 0x2c04f000 0 0x2000>,
		      <0x0 0x2c06f000 0 0x2000>;
		#address-cells = <1>;
		#interrupt-cells = <3>;
		#size-cells = <1>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
		ranges = <0 0 0x2c1c0000 0x40000>;

		v2m_0: v2m@0 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0 0x10000>;
		};

		v2m@10000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x10000 0x10000>;
		};

		v2m@20000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x20000 0x10000>;
		};

		v2m@30000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x30000 0x10000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
	};

	/*
	 * Juno TRMs specify the size for these coresight components as 64K.
	 * The actual size is just 4K though 64K is reserved. Access to the
	 * unmapped reserved region results in a DECERR response.
	 */
	etf_sys0: etf@20010000 { /* etf0 */
		compatible = "arm,coresight-tmc", "arm,primecell";
		reg = <0 0x20010000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;

		in-ports {
			port {
				etf0_in_port: endpoint {
					remote-endpoint = <&main_funnel_out_port>;
				};
			};
		};

		out-ports {
			port {
				etf0_out_port: endpoint {
				};
			};
		};
	};

	tpiu_sys: tpiu@20030000 {
		compatible = "arm,coresight-tpiu", "arm,primecell";
		reg = <0 0x20030000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		in-ports {
			port {
				tpiu_in_port: endpoint {
					remote-endpoint = <&replicator_out_port0>;
				};
			};
		};
	};

	/* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
	main_funnel: funnel@20040000 {
		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
		reg = <0 0x20040000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;

		out-ports {
			port {
				main_funnel_out_port: endpoint {
					remote-endpoint = <&etf0_in_port>;
				};
			};
		};

		main_funnel_in_ports: in-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				main_funnel_in_port0: endpoint {
					remote-endpoint = <&cluster0_funnel_out_port>;
				};
			};

			port@1 {
				reg = <1>;
				main_funnel_in_port1: endpoint {
					remote-endpoint = <&cluster1_funnel_out_port>;
				};
			};
		};
	};

	etr_sys: etr@20070000 {
		compatible = "arm,coresight-tmc", "arm,primecell";
		reg = <0 0x20070000 0 0x1000>;
		iommus = <&smmu_etr 0>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		arm,scatter-gather;
		in-ports {
			port {
				etr_in_port: endpoint {
					remote-endpoint = <&replicator_out_port1>;
				};
			};
		};
	};

	stm_sys: stm@20100000 {
		compatible = "arm,coresight-stm", "arm,primecell";
		reg = <0 0x20100000 0 0x1000>,
		      <0 0x28000000 0 0x1000000>;
		reg-names = "stm-base", "stm-stimulus-base";

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		out-ports {
			port {
				stm_out_port: endpoint {
				};
			};
		};
	};

	replicator@20120000 {
		compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
		reg = <0 0x20120000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;

		out-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* replicator output ports */
			port@0 {
				reg = <0>;
				replicator_out_port0: endpoint {
					remote-endpoint = <&tpiu_in_port>;
				};
			};

			port@1 {
				reg = <1>;
				replicator_out_port1: endpoint {
					remote-endpoint = <&etr_in_port>;
				};
			};
		};
		in-ports {
			port {
				replicator_in_port0: endpoint {
				};
			};
		};
	};

	cpu_debug0: cpu-debug@22010000 {
		compatible = "arm,coresight-cpu-debug", "arm,primecell";
		reg = <0x0 0x22010000 0x0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
	};

	etm0: etm@22040000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x22040000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		out-ports {
			port {
				cluster0_etm0_out_port: endpoint {
					remote-endpoint = <&cluster0_funnel_in_port0>;
				};
			};
		};
	};

	cti0: cti@22020000 {
		compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
			     "arm,primecell";
		reg = <0 0x22020000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;

		arm,cs-dev-assoc = <&etm0>;
	};

	funnel@220c0000 { /* cluster0 funnel */
		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
		reg = <0 0x220c0000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		out-ports {
			port {
				cluster0_funnel_out_port: endpoint {
					remote-endpoint = <&main_funnel_in_port0>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				cluster0_funnel_in_port0: endpoint {
					remote-endpoint = <&cluster0_etm0_out_port>;
				};
			};

			port@1 {
				reg = <1>;
				cluster0_funnel_in_port1: endpoint {
					remote-endpoint = <&cluster0_etm1_out_port>;
				};
			};
		};
	};

	cpu_debug1: cpu-debug@22110000 {
		compatible = "arm,coresight-cpu-debug", "arm,primecell";
		reg = <0x0 0x22110000 0x0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
	};

	etm1: etm@22140000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x22140000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		out-ports {
			port {
				cluster0_etm1_out_port: endpoint {
					remote-endpoint = <&cluster0_funnel_in_port1>;
				};
			};
		};
	};

	cti1: cti@22120000 {
		compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
			     "arm,primecell";
		reg = <0 0x22120000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;

		arm,cs-dev-assoc = <&etm1>;
	};

	cpu_debug2: cpu-debug@23010000 {
		compatible = "arm,coresight-cpu-debug", "arm,primecell";
		reg = <0x0 0x23010000 0x0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
	};

	etm2: etm@23040000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x23040000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		out-ports {
			port {
				cluster1_etm0_out_port: endpoint {
					remote-endpoint = <&cluster1_funnel_in_port0>;
				};
			};
		};
	};

	cti2: cti@23020000 {
		compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
			     "arm,primecell";
		reg = <0 0x23020000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;

		arm,cs-dev-assoc = <&etm2>;
	};

	funnel@230c0000 { /* cluster1 funnel */
		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
		reg = <0 0x230c0000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		out-ports {
			port {
				cluster1_funnel_out_port: endpoint {
					remote-endpoint = <&main_funnel_in_port1>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				cluster1_funnel_in_port0: endpoint {
					remote-endpoint = <&cluster1_etm0_out_port>;
				};
			};

			port@1 {
				reg = <1>;
				cluster1_funnel_in_port1: endpoint {
					remote-endpoint = <&cluster1_etm1_out_port>;
				};
			};
			port@2 {
				reg = <2>;
				cluster1_funnel_in_port2: endpoint {
					remote-endpoint = <&cluster1_etm2_out_port>;
				};
			};
			port@3 {
				reg = <3>;
				cluster1_funnel_in_port3: endpoint {
					remote-endpoint = <&cluster1_etm3_out_port>;
				};
			};
		};
	};

	cpu_debug3: cpu-debug@23110000 {
		compatible = "arm,coresight-cpu-debug", "arm,primecell";
		reg = <0x0 0x23110000 0x0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
	};

	etm3: etm@23140000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x23140000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		out-ports {
			port {
				cluster1_etm1_out_port: endpoint {
					remote-endpoint = <&cluster1_funnel_in_port1>;
				};
			};
		};
	};

	cti3: cti@23120000 {
		compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
			     "arm,primecell";
		reg = <0 0x23120000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;

		arm,cs-dev-assoc = <&etm3>;
	};

	cpu_debug4: cpu-debug@23210000 {
		compatible = "arm,coresight-cpu-debug", "arm,primecell";
		reg = <0x0 0x23210000 0x0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
	};

	etm4: etm@23240000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x23240000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		out-ports {
			port {
				cluster1_etm2_out_port: endpoint {
					remote-endpoint = <&cluster1_funnel_in_port2>;
				};
			};
		};
	};

	cti4: cti@23220000 {
		compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
			     "arm,primecell";
		reg = <0 0x23220000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;

		arm,cs-dev-assoc = <&etm4>;
	};

	cpu_debug5: cpu-debug@23310000 {
		compatible = "arm,coresight-cpu-debug", "arm,primecell";
		reg = <0x0 0x23310000 0x0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
	};

	etm5: etm@23340000 {
		compatible = "arm,coresight-etm4x", "arm,primecell";
		reg = <0 0x23340000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		out-ports {
			port {
				cluster1_etm3_out_port: endpoint {
					remote-endpoint = <&cluster1_funnel_in_port3>;
				};
			};
		};
	};

	cti5: cti@23320000 {
		compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
			     "arm,primecell";
		reg = <0 0x23320000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;

		arm,cs-dev-assoc = <&etm5>;
	};

	cti_sys0: cti@20020000 { /* sys_cti_0 */
		compatible = "arm,coresight-cti", "arm,primecell";
		reg = <0 0x20020000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;

		#address-cells = <1>;
		#size-cells = <0>;

		trig-conns@0 {
			reg = <0>;
			arm,trig-in-sigs = <2 3>;
			arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
			arm,trig-out-sigs = <0 1>;
			arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
			arm,cs-dev-assoc = <&etr_sys>;
		};

		trig-conns@1 {
			reg = <1>;
			arm,trig-in-sigs = <0 1>;
			arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
			arm,trig-out-sigs = <7 6>;
			arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
			arm,cs-dev-assoc = <&etf_sys0>;
		};

		trig-conns@2 {
			reg = <2>;
			arm,trig-in-sigs = <4 5 6 7>;
			arm,trig-in-types = <STM_TOUT_SPTE STM_TOUT_SW
					   STM_TOUT_HETE STM_ASYNCOUT>;
			arm,trig-out-sigs = <4 5>;
			arm,trig-out-types = <STM_HWEVENT STM_HWEVENT>;
			arm,cs-dev-assoc = <&stm_sys>;
		};

		trig-conns@3 {
			reg = <3>;
			arm,trig-out-sigs = <2 3>;
			arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
			arm,cs-dev-assoc = <&tpiu_sys>;
		};
	};

	cti_sys1: cti@20110000 { /* sys_cti_1 */
		compatible = "arm,coresight-cti", "arm,primecell";
		reg = <0 0x20110000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;

		#address-cells = <1>;
		#size-cells = <0>;

		trig-conns@0 {
			reg = <0>;
			arm,trig-in-sigs = <0>;
			arm,trig-in-types = <GEN_INTREQ>;
			arm,trig-out-sigs = <0>;
			arm,trig-out-types = <GEN_HALTREQ>;
			arm,trig-conn-name = "sys_profiler";
		};

		trig-conns@1 {
			reg = <1>;
			arm,trig-out-sigs = <2 3>;
			arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
			arm,trig-conn-name = "watchdog";
		};

		trig-conns@2 {
			reg = <2>;
			arm,trig-out-sigs = <1 6>;
			arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
			arm,trig-conn-name = "g_counter";
		};
	};

	gpu: gpu@2d000000 {
		compatible = "arm,juno-mali", "arm,mali-t624";
		reg = <0 0x2d000000 0 0x10000>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "job", "mmu", "gpu";
		clocks = <&scpi_dvfs 2>;
		power-domains = <&scpi_devpd 1>;
		dma-coherent;
		/* The SMMU is only really of interest to bare-metal hypervisors */
		/* iommus = <&smmu_gpu 0>; */
		status = "disabled";
	};

	sram: sram@2e000000 {
		compatible = "arm,juno-sram-ns", "mmio-sram";
		reg = <0x0 0x2e000000 0x0 0x8000>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x0 0x2e000000 0x8000>;

		cpu_scp_lpri: scp-sram@0 {
			compatible = "arm,juno-scp-shmem";
			reg = <0x0 0x200>;
		};

		cpu_scp_hpri: scp-sram@200 {
			compatible = "arm,juno-scp-shmem";
			reg = <0x200 0x200>;
		};
	};

	pcie_ctlr: pcie@40000000 {
		compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
		device_type = "pci";
		reg = <0 0x40000000 0 0x10000000>;	/* ECAM config space */
		bus-range = <0 255>;
		linux,pci-domain = <0>;
		#address-cells = <3>;
		#size-cells = <2>;
		dma-coherent;
		ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
			 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
			 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
		/* Standard AXI Translation entries as programmed by EDK2 */
		dma-ranges = <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>,
			     <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
		msi-parent = <&v2m_0>;
		status = "disabled";
		iommu-map-mask = <0x0>;	/* RC has no means to output PCI RID */
		iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
	};

	scpi {
		compatible = "arm,scpi";
		mboxes = <&mailbox 1>;
		shmem = <&cpu_scp_hpri>;

		clocks {
			compatible = "arm,scpi-clocks";

			scpi_dvfs: clocks-0 {
				compatible = "arm,scpi-dvfs-clocks";
				#clock-cells = <1>;
				clock-indices = <0>, <1>, <2>;
				clock-output-names = "atlclk", "aplclk","gpuclk";
			};
			scpi_clk: clocks-1 {
				compatible = "arm,scpi-variable-clocks";
				#clock-cells = <1>;
				clock-indices = <3>;
				clock-output-names = "pxlclk";
			};
		};

		scpi_devpd: power-controller {
			compatible = "arm,scpi-power-domains";
			num-domains = <2>;
			#power-domain-cells = <1>;
		};

		scpi_sensors0: sensors {
			compatible = "arm,scpi-sensors";
			#thermal-sensor-cells = <1>;
		};
	};

	thermal-zones {
		pmic {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			thermal-sensors = <&scpi_sensors0 0>;
			trips {
				pmic_crit0: trip0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		soc {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			thermal-sensors = <&scpi_sensors0 3>;
			trips {
				soc_crit0: trip0 {
					temperature = <80000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		big_cluster_thermal_zone: big-cluster {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			thermal-sensors = <&scpi_sensors0 21>;
			status = "disabled";
		};

		little_cluster_thermal_zone: little-cluster {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			thermal-sensors = <&scpi_sensors0 22>;
			status = "disabled";
		};

		gpu0_thermal_zone: gpu0 {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			thermal-sensors = <&scpi_sensors0 23>;
			status = "disabled";
		};

		gpu1_thermal_zone: gpu1 {
			polling-delay = <1000>;
			polling-delay-passive = <100>;
			thermal-sensors = <&scpi_sensors0 24>;
			status = "disabled";
		};
	};

	smmu_dma: iommu@7fb00000 {
		compatible = "arm,mmu-401", "arm,smmu-v1";
		reg = <0x0 0x7fb00000 0x0 0x10000>;
		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		#global-interrupts = <1>;
		dma-coherent;
	};

	smmu_hdlcd1: iommu@7fb10000 {
		compatible = "arm,mmu-401", "arm,smmu-v1";
		reg = <0x0 0x7fb10000 0x0 0x10000>;
		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		#global-interrupts = <1>;
	};

	smmu_hdlcd0: iommu@7fb20000 {
		compatible = "arm,mmu-401", "arm,smmu-v1";
		reg = <0x0 0x7fb20000 0x0 0x10000>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		#global-interrupts = <1>;
	};

	smmu_usb: iommu@7fb30000 {
		compatible = "arm,mmu-401", "arm,smmu-v1";
		reg = <0x0 0x7fb30000 0x0 0x10000>;
		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		#global-interrupts = <1>;
		dma-coherent;
	};

	dma-controller@7ff00000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x0 0x7ff00000 0 0x1000>;
		#dma-cells = <1>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
		iommus = <&smmu_dma 0>,
			 <&smmu_dma 1>,
			 <&smmu_dma 2>,
			 <&smmu_dma 3>,
			 <&smmu_dma 4>,
			 <&smmu_dma 5>,
			 <&smmu_dma 6>,
			 <&smmu_dma 7>,
			 <&smmu_dma 8>;
		clocks = <&soc_faxiclk>;
		clock-names = "apb_pclk";
	};

	hdlcd@7ff50000 {
		compatible = "arm,hdlcd";
		reg = <0 0x7ff50000 0 0x1000>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		iommus = <&smmu_hdlcd1 0>;
		clocks = <&scpi_clk 3>;
		clock-names = "pxlclk";

		port {
			hdlcd1_output: endpoint {
				remote-endpoint = <&tda998x_1_input>;
			};
		};
	};

	hdlcd@7ff60000 {
		compatible = "arm,hdlcd";
		reg = <0 0x7ff60000 0 0x1000>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		iommus = <&smmu_hdlcd0 0>;
		clocks = <&scpi_clk 3>;
		clock-names = "pxlclk";

		port {
			hdlcd0_output: endpoint {
				remote-endpoint = <&tda998x_0_input>;
			};
		};
	};

	soc_uart0: serial@7ff80000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x0 0x7ff80000 0x0 0x1000>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
		clock-names = "uartclk", "apb_pclk";
	};

	i2c@7ffa0000 {
		compatible = "snps,designware-i2c";
		reg = <0x0 0x7ffa0000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <400000>;
		i2c-sda-hold-time-ns = <500>;
		clocks = <&soc_smc50mhz>;

		hdmi-transmitter@70 {
			compatible = "nxp,tda998x";
			reg = <0x70>;
			port {
				tda998x_0_input: endpoint {
					remote-endpoint = <&hdlcd0_output>;
				};
			};
		};

		hdmi-transmitter@71 {
			compatible = "nxp,tda998x";
			reg = <0x71>;
			port {
				tda998x_1_input: endpoint {
					remote-endpoint = <&hdlcd1_output>;
				};
			};
		};
	};

	usb@7ffb0000 {
		compatible = "generic-ohci";
		reg = <0x0 0x7ffb0000 0x0 0x10000>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		iommus = <&smmu_usb 0>;
		clocks = <&soc_usb48mhz>;
	};

	usb@7ffc0000 {
		compatible = "generic-ehci";
		reg = <0x0 0x7ffc0000 0x0 0x10000>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		iommus = <&smmu_usb 0>;
		clocks = <&soc_usb48mhz>;
	};

	memory-controller@7ffd0000 {
		compatible = "arm,pl354", "arm,primecell";
		reg = <0 0x7ffd0000 0 0x1000>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
	};

	memory@80000000 {
		device_type = "memory";
		/* last 16MB of the first memory area is reserved for secure world use by firmware */
		reg = <0x00000000 0x80000000 0x0 0x7f000000>,
		      <0x00000008 0x80000000 0x1 0x80000000>;
	};

	bus@8000000 {
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 15>;
		interrupt-map = <0 0  0 &gic 0 GIC_SPI  68 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  1 &gic 0 GIC_SPI  69 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  2 &gic 0 GIC_SPI  70 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
	};

	site2: tlx-bus@60000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x60000000 0x10000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0>;
		interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
	};
};


code:
/*
 * ARM Juno Platform clocks
 *
 * Copyright (c) 2013-2014 ARM Ltd
 *
 * This file is licensed under a dual GPLv2 or BSD license.
 *
 */
/ {
	/* SoC fixed clocks */
	soc_uartclk: refclk7372800hz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <7372800>;
		clock-output-names = "juno:uartclk";
	};

	soc_usb48mhz: clk48mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <48000000>;
		clock-output-names = "clk48mhz";
	};

	soc_smc50mhz: clk50mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
		clock-output-names = "smc_clk";
	};

	soc_refclk100mhz: refclk100mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "apb_pclk";
	};

	soc_faxiclk: refclk400mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <400000000>;
		clock-output-names = "faxi_clk";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/ {
	funnel@20130000 { /* cssys1 */
		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
		reg = <0 0x20130000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		out-ports {
			port {
				csys1_funnel_out_port: endpoint {
					remote-endpoint = <&etf1_in_port>;
				};
			};
		};
		in-ports {
			port {
				csys1_funnel_in_port0: endpoint {
				};
			};

		};
	};

	etf_sys1: etf@20140000 { /* etf1 */
		compatible = "arm,coresight-tmc", "arm,primecell";
		reg = <0 0x20140000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		in-ports {
			port {
				etf1_in_port: endpoint {
					remote-endpoint = <&csys1_funnel_out_port>;
				};
			};
		};
		out-ports {
			port {
				etf1_out_port: endpoint {
					remote-endpoint = <&csys2_funnel_in_port1>;
				};
			};
		};
	};

	funnel@20150000 { /* cssys2 */
		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
		reg = <0 0x20150000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;
		out-ports {
			port {
				csys2_funnel_out_port: endpoint {
					remote-endpoint = <&replicator_in_port0>;
				};
			};
		};

		in-ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				csys2_funnel_in_port0: endpoint {
					remote-endpoint = <&etf0_out_port>;
				};
			};

			port@1 {
				reg = <1>;
				csys2_funnel_in_port1: endpoint {
					remote-endpoint = <&etf1_out_port>;
				};
			};

		};
	};

	cti_sys2: cti@20160000 { /* sys_cti_2 */
		compatible = "arm,coresight-cti", "arm,primecell";
		reg = <0 0x20160000 0 0x1000>;

		clocks = <&soc_smc50mhz>;
		clock-names = "apb_pclk";
		power-domains = <&scpi_devpd 0>;

		#address-cells = <1>;
		#size-cells = <0>;

		trig-conns@0 {
			reg = <0>;
			arm,trig-in-sigs = <0 1>;
			arm,trig-in-types = <SNK_FULL SNK_ACQCOMP>;
			arm,trig-out-sigs = <0 1>;
			arm,trig-out-types = <SNK_FLUSHIN SNK_TRIGIN>;
			arm,cs-dev-assoc = <&etf_sys1>;
		};

		trig-conns@1 {
			reg = <1>;
			arm,trig-in-sigs = <2 3 4>;
			arm,trig-in-types = <ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
			arm,trig-conn-name = "ela_clus_0";
		};

		trig-conns@2 {
			reg = <2>;
			arm,trig-in-sigs = <5 6 7>;
			arm,trig-in-types = <ELA_DBGREQ ELA_TSTART ELA_TSTOP>;
			arm,trig-conn-name = "ela_clus_1";
		};
	};
};


code:
/*
 * ARM Juno Platform motherboard peripherals
 *
 * Copyright (c) 2013-2014 ARM Ltd
 *
 * This file is licensed under a dual GPLv2 or BSD license.
 *
 */

/ {
	mb_clk24mhz: clk24mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "juno_mb:clk24mhz";
	};

	mb_clk25mhz: clk25mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
		clock-output-names = "juno_mb:clk25mhz";
	};

	v2m_refclk1mhz: refclk1mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <1000000>;
		clock-output-names = "juno_mb:refclk1mhz";
	};

	v2m_refclk32khz: refclk32khz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "juno_mb:refclk32khz";
	};

	mb_fixed_3v3: mcc-sb-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "MCC_SB_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	gpio-keys {
		compatible = "gpio-keys";

		power-button {
			debounce-interval = <50>;
			wakeup-source;
			linux,code = <116>;
			label = "POWER";
			gpios = <&iofpga_gpio0 0 0x4>;
		};
		home-button {
			debounce-interval = <50>;
			wakeup-source;
			linux,code = <102>;
			label = "HOME";
			gpios = <&iofpga_gpio0 1 0x4>;
		};
		rlock-button {
			debounce-interval = <50>;
			wakeup-source;
			linux,code = <152>;
			label = "RLOCK";
			gpios = <&iofpga_gpio0 2 0x4>;
		};
		vol-up-button {
			debounce-interval = <50>;
			wakeup-source;
			linux,code = <115>;
			label = "VOL+";
			gpios = <&iofpga_gpio0 3 0x4>;
		};
		vol-down-button {
			debounce-interval = <50>;
			wakeup-source;
			linux,code = <114>;
			label = "VOL-";
			gpios = <&iofpga_gpio0 4 0x4>;
		};
		nmi-button {
			debounce-interval = <50>;
			wakeup-source;
			linux,code = <99>;
			label = "NMI";
			gpios = <&iofpga_gpio0 5 0x4>;
		};
	};

	bus@8000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0x8000000 0 0x8000000 0x18000000>;

		motherboard-bus@8000000 {
			compatible = "arm,vexpress,v2p-p1", "simple-bus";
			#address-cells = <2>;  /* SMB chipselect number and offset */
			#size-cells = <1>;
			ranges = <0 0 0 0x08000000 0x04000000>,
				 <1 0 0 0x14000000 0x04000000>,
				 <2 0 0 0x18000000 0x04000000>,
				 <3 0 0 0x1c000000 0x04000000>,
				 <4 0 0 0x0c000000 0x04000000>,
				 <5 0 0 0x10000000 0x04000000>;
			arm,hbi = <0x252>;
			arm,vexpress,site = <0>;

			flash@0 {
				/* 2 * 32MiB NOR Flash memory mounted on CS0 */
				compatible = "arm,vexpress-flash", "cfi-flash";
				reg = <0 0x00000000 0x04000000>;
				bank-width = <4>;
				/*
				 * Unfortunately, accessing the flash disturbs
				 * the CPU idle states (suspend) and CPU
				 * hotplug of the platform. For this reason,
				 * flash hardware access is disabled by default.
				 */
				status = "disabled";
				partitions {
					compatible = "arm,arm-firmware-suite";
				};
			};

			ethernet@200000000 {
				compatible = "smsc,lan9118", "smsc,lan9115";
				reg = <2 0x00000000 0x10000>;
				interrupts = <3>;
				phy-mode = "mii";
				reg-io-width = <4>;
				smsc,irq-active-high;
				smsc,irq-push-pull;
				clocks = <&mb_clk25mhz>;
				vdd33a-supply = <&mb_fixed_3v3>;
				vddvario-supply = <&mb_fixed_3v3>;
			};

			iofpga-bus@300000000 {
				compatible = "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 3 0 0x200000>;

				v2m_sysctl: sysctl@20000 {
					compatible = "arm,sp810", "arm,primecell";
					reg = <0x020000 0x1000>;
					clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
					clock-names = "refclk", "timclk", "apb_pclk";
					#clock-cells = <1>;
					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
					assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
					assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
				};

				apbregs@10000 {
					compatible = "syscon", "simple-mfd";
					reg = <0x010000 0x1000>;
					ranges = <0x0 0x10000 0x1000>;
					#address-cells = <1>;
					#size-cells = <1>;

					led@8,0 {
						compatible = "register-bit-led";
						reg = <0x08 0x04>;
						offset = <0x08>;
						mask = <0x01>;
						label = "vexpress:0";
						linux,default-trigger = "heartbeat";
						default-state = "on";
					};
					led@8,1 {
						compatible = "register-bit-led";
						reg = <0x08 0x04>;
						offset = <0x08>;
						mask = <0x02>;
						label = "vexpress:1";
						linux,default-trigger = "mmc0";
						default-state = "off";
					};
					led@8,2 {
						compatible = "register-bit-led";
						reg = <0x08 0x04>;
						offset = <0x08>;
						mask = <0x04>;
						label = "vexpress:2";
						linux,default-trigger = "cpu0";
						default-state = "off";
					};
					led@8,3 {
						compatible = "register-bit-led";
						reg = <0x08 0x04>;
						offset = <0x08>;
						mask = <0x08>;
						label = "vexpress:3";
						linux,default-trigger = "cpu1";
						default-state = "off";
					};
					led@8,4 {
						compatible = "register-bit-led";
						reg = <0x08 0x04>;
						offset = <0x08>;
						mask = <0x10>;
						label = "vexpress:4";
						linux,default-trigger = "cpu2";
						default-state = "off";
					};
					led@8,5 {
						compatible = "register-bit-led";
						reg = <0x08 0x04>;
						offset = <0x08>;
						mask = <0x20>;
						label = "vexpress:5";
						linux,default-trigger = "cpu3";
						default-state = "off";
					};
					led@8,6 {
						compatible = "register-bit-led";
						reg = <0x08 0x04>;
						offset = <0x08>;
						mask = <0x40>;
						label = "vexpress:6";
						default-state = "off";
					};
					led@8,7 {
						compatible = "register-bit-led";
						reg = <0x08 0x04>;
						offset = <0x08>;
						mask = <0x80>;
						label = "vexpress:7";
						default-state = "off";
					};
				};

				mmc@50000 {
					compatible = "arm,pl180", "arm,primecell";
					reg = <0x050000 0x1000>;
					interrupts = <5>;
					/* cd-gpios = <&v2m_mmc_gpios 0 0>;
					wp-gpios = <&v2m_mmc_gpios 1 0>; */
					max-frequency = <12000000>;
					vmmc-supply = <&mb_fixed_3v3>;
					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
					clock-names = "mclk", "apb_pclk";
				};

				kmi@60000 {
					compatible = "arm,pl050", "arm,primecell";
					reg = <0x060000 0x1000>;
					interrupts = <8>;
					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
					clock-names = "KMIREFCLK", "apb_pclk";
				};

				kmi@70000 {
					compatible = "arm,pl050", "arm,primecell";
					reg = <0x070000 0x1000>;
					interrupts = <8>;
					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
					clock-names = "KMIREFCLK", "apb_pclk";
				};

				watchdog@f0000 {
					compatible = "arm,sp805", "arm,primecell";
					reg = <0x0f0000 0x10000>;
					interrupts = <7>;
					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
					clock-names = "wdog_clk", "apb_pclk";
				};

				v2m_timer01: timer@110000 {
					compatible = "arm,sp804", "arm,primecell";
					reg = <0x110000 0x10000>;
					interrupts = <9>;
					clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
					clock-names = "timclken1", "timclken2", "apb_pclk";
				};

				v2m_timer23: timer@120000 {
					compatible = "arm,sp804", "arm,primecell";
					reg = <0x120000 0x10000>;
					interrupts = <9>;
					clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
					clock-names = "timclken1", "timclken2", "apb_pclk";
				};

				rtc@170000 {
					compatible = "arm,pl031", "arm,primecell";
					reg = <0x170000 0x10000>;
					interrupts = <0>;
					clocks = <&soc_smc50mhz>;
					clock-names = "apb_pclk";
				};

				iofpga_gpio0: gpio@1d0000 {
					compatible = "arm,pl061", "arm,primecell";
					reg = <0x1d0000 0x1000>;
					interrupts = <6>;
					clocks = <&soc_smc50mhz>;
					clock-names = "apb_pclk";
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};
			};
		};
	};
};


code:
#include "juno-r1.dts"
#include "juno-scmi.dtsi"

/ {
	funnel@20130000 {
		power-domains = <&scmi_devpd 8>;
	};

	etf@20140000 {
		power-domains = <&scmi_devpd 8>;
	};

	funnel@20150000 {
		power-domains = <&scmi_devpd 8>;
	};
};

&cti_sys2 {
	power-domains = <&scmi_devpd 8>;
};

&A57_0 {
	clocks = <&scmi_dvfs 0>;
};
&A57_1 {
	clocks = <&scmi_dvfs 0>;
};


code:
/*
 * ARM Ltd. Juno Platform
 *
 * Copyright (c) 2015 ARM Ltd.
 *
 * This file is licensed under a dual GPLv2 or BSD license.
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/arm/coresight-cti-dt.h>
#include "juno-base.dtsi"
#include "juno-cs-r1r2.dtsi"

/ {
	model = "ARM Juno development board (r1)";
	compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &soc_uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&A57_0>;
				};
				core1 {
					cpu = <&A57_1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&A53_0>;
				};
				core1 {
					cpu = <&A53_1>;
				};
				core2 {
					cpu = <&A53_2>;
				};
				core3 {
					cpu = <&A53_3>;
				};
			};
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				local-timer-stop;
				entry-latency-us = <300>;
				exit-latency-us = <1200>;
				min-residency-us = <2000>;
			};

			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x1010000>;
				local-timer-stop;
				entry-latency-us = <400>;
				exit-latency-us = <1200>;
				min-residency-us = <2500>;
			};
		};

		A57_0: cpu@0 {
			compatible = "arm,cortex-a57";
			reg = <0x0 0x0>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&A57_L2>;
			clocks = <&scpi_dvfs 0>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <1024>;
		};

		A57_1: cpu@1 {
			compatible = "arm,cortex-a57";
			reg = <0x0 0x1>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&A57_L2>;
			clocks = <&scpi_dvfs 0>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <1024>;
		};

		A53_0: cpu@100 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <578>;
		};

		A53_1: cpu@101 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x101>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <578>;
		};

		A53_2: cpu@102 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x102>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <578>;
		};

		A53_3: cpu@103 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x103>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <578>;
		};

		A57_L2: l2-cache0 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
			cache-level = <2>;
		};

		A53_L2: l2-cache1 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x100000>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-level = <2>;
		};
	};

	pmu-a57 {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A57_0>,
				     <&A57_1>;
	};

	pmu-a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A53_0>,
				     <&A53_1>,
				     <&A53_2>,
				     <&A53_3>;
	};
};

&memtimer {
	status = "okay";
};

&pcie_ctlr {
	status = "okay";
};

&smmu_pcie {
	status = "okay";
};

&etm0 {
	cpu = <&A57_0>;
};

&etm1 {
	cpu = <&A57_1>;
};

&etm2 {
	cpu = <&A53_0>;
};

&etm3 {
	cpu = <&A53_1>;
};

&etm4 {
	cpu = <&A53_2>;
};

&etm5 {
	cpu = <&A53_3>;
};

&big_cluster_thermal_zone {
	status = "okay";
};

&little_cluster_thermal_zone {
	status = "okay";
};

&gpu0_thermal_zone {
	status = "okay";
};

&gpu1_thermal_zone {
	status = "okay";
};

&etf0_out_port {
	remote-endpoint = <&csys2_funnel_in_port0>;
};

&replicator_in_port0 {
	remote-endpoint = <&csys2_funnel_out_port>;
};

&csys1_funnel_in_port0 {
	remote-endpoint = <&stm_out_port>;
};

&stm_out_port {
	remote-endpoint = <&csys1_funnel_in_port0>;
};

&cpu_debug0 {
	cpu = <&A57_0>;
};

&cpu_debug1 {
	cpu = <&A57_1>;
};

&cpu_debug2 {
	cpu = <&A53_0>;
};

&cpu_debug3 {
	cpu = <&A53_1>;
};

&cpu_debug4 {
	cpu = <&A53_2>;
};

&cpu_debug5 {
	cpu = <&A53_3>;
};

&cti0 {
	cpu = <&A57_0>;
};

&cti1 {
	cpu = <&A57_1>;
};

&cti2 {
	cpu = <&A53_0>;
};

&cti3 {
	cpu = <&A53_1>;
};

&cti4 {
	cpu = <&A53_2>;
};

&cti5 {
	cpu = <&A53_3>;
};


code:
#include "juno-r2.dts"
#include "juno-scmi.dtsi"

/ {
	funnel@20130000 {
		power-domains = <&scmi_devpd 8>;
	};

	etf@20140000 {
		power-domains = <&scmi_devpd 8>;
	};

	funnel@20150000 {
		power-domains = <&scmi_devpd 8>;
	};
};

&cti_sys2 {
	power-domains = <&scmi_devpd 8>;
};

&A72_0 {
	clocks = <&scmi_dvfs 0>;
};
&A72_1 {
	clocks = <&scmi_dvfs 0>;
};


code:
/*
 * ARM Ltd. Juno Platform
 *
 * Copyright (c) 2015 ARM Ltd.
 *
 * This file is licensed under a dual GPLv2 or BSD license.
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/arm/coresight-cti-dt.h>
#include "juno-base.dtsi"
#include "juno-cs-r1r2.dtsi"

/ {
	model = "ARM Juno development board (r2)";
	compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &soc_uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&A72_0>;
				};
				core1 {
					cpu = <&A72_1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&A53_0>;
				};
				core1 {
					cpu = <&A53_1>;
				};
				core2 {
					cpu = <&A53_2>;
				};
				core3 {
					cpu = <&A53_3>;
				};
			};
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				local-timer-stop;
				entry-latency-us = <300>;
				exit-latency-us = <1200>;
				min-residency-us = <2000>;
			};

			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x1010000>;
				local-timer-stop;
				entry-latency-us = <400>;
				exit-latency-us = <1200>;
				min-residency-us = <2500>;
			};
		};

		A72_0: cpu@0 {
			compatible = "arm,cortex-a72";
			reg = <0x0 0x0>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&A72_L2>;
			clocks = <&scpi_dvfs 0>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <450>;
		};

		A72_1: cpu@1 {
			compatible = "arm,cortex-a72";
			reg = <0x0 0x1>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&A72_L2>;
			clocks = <&scpi_dvfs 0>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <450>;
		};

		A53_0: cpu@100 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <485>;
			dynamic-power-coefficient = <140>;
		};

		A53_1: cpu@101 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x101>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <485>;
			dynamic-power-coefficient = <140>;
		};

		A53_2: cpu@102 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x102>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <485>;
			dynamic-power-coefficient = <140>;
		};

		A53_3: cpu@103 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x103>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <485>;
			dynamic-power-coefficient = <140>;
		};

		A72_L2: l2-cache0 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
			cache-level = <2>;
		};

		A53_L2: l2-cache1 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x100000>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-level = <2>;
		};
	};

	pmu-a72 {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A72_0>,
				     <&A72_1>;
	};

	pmu-a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A53_0>,
				     <&A53_1>,
				     <&A53_2>,
				     <&A53_3>;
	};
};

&memtimer {
	status = "okay";
};

&pcie_ctlr {
	status = "okay";
};

&smmu_pcie {
	status = "okay";
};

&etm0 {
	cpu = <&A72_0>;
};

&etm1 {
	cpu = <&A72_1>;
};

&etm2 {
	cpu = <&A53_0>;
};

&etm3 {
	cpu = <&A53_1>;
};

&etm4 {
	cpu = <&A53_2>;
};

&etm5 {
	cpu = <&A53_3>;
};

&big_cluster_thermal_zone {
	status = "okay";
};

&little_cluster_thermal_zone {
	status = "okay";
};

&gpu0_thermal_zone {
	status = "okay";
};

&gpu1_thermal_zone {
	status = "okay";
};

&etf0_out_port {
	remote-endpoint = <&csys2_funnel_in_port0>;
};

&replicator_in_port0 {
	remote-endpoint = <&csys2_funnel_out_port>;
};

&csys1_funnel_in_port0 {
	remote-endpoint = <&stm_out_port>;
};

&stm_out_port {
	remote-endpoint = <&csys1_funnel_in_port0>;
};

&cpu_debug0 {
	cpu = <&A72_0>;
};

&cpu_debug1 {
	cpu = <&A72_1>;
};

&cpu_debug2 {
	cpu = <&A53_0>;
};

&cpu_debug3 {
	cpu = <&A53_1>;
};

&cpu_debug4 {
	cpu = <&A53_2>;
};

&cpu_debug5 {
	cpu = <&A53_3>;
};

&cti0 {
	cpu = <&A72_0>;
};

&cti1 {
	cpu = <&A72_1>;
};

&cti2 {
	cpu = <&A53_0>;
};

&cti3 {
	cpu = <&A53_1>;
};

&cti4 {
	cpu = <&A53_2>;
};

&cti5 {
	cpu = <&A53_3>;
};


code:
#include "juno.dts"
#include "juno-scmi.dtsi"

&A57_0 {
	clocks = <&scmi_dvfs 0>;
};
&A57_1 {
	clocks = <&scmi_dvfs 0>;
};


code:
/ {
	etf@20010000 {
		power-domains = <&scmi_devpd 8>;
	};

	tpiu@20030000 {
		power-domains = <&scmi_devpd 8>;
	};

	funnel@20040000 {
		power-domains = <&scmi_devpd 8>;
	};

	etr@20070000 {
		power-domains = <&scmi_devpd 8>;
	};

	stm@20100000 {
		power-domains = <&scmi_devpd 8>;
	};

	replicator@20120000 {
		power-domains = <&scmi_devpd 8>;
	};

	funnel@220c0000 {
		power-domains = <&scmi_devpd 8>;
	};

	funnel@230c0000 {
		power-domains = <&scmi_devpd 8>;
	};

	hdlcd@7ff50000 {
		clocks = <&scmi_clk 3>;
	};

	hdlcd@7ff60000 {
		clocks = <&scmi_clk 3>;
	};

	/delete-node/ scpi;

	firmware {
		scmi {
			compatible = "arm,scmi";
			mbox-names = "tx", "rx";
			mboxes = <&mailbox 0 0 &mailbox 0 1>;
			shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>;
			#address-cells = <1>;
			#size-cells = <0>;

			scmi_devpd: protocol@11 {
				reg = <0x11>;
				#power-domain-cells = <1>;
			};

			scmi_dvfs: protocol@13 {
				reg = <0x13>;
				#clock-cells = <1>;
				mbox-names = "tx", "rx";
				mboxes = <&mailbox 1 0 &mailbox 1 1>;
				shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
			};

			scmi_clk: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};

			scmi_sensors0: protocol@15 {
				reg = <0x15>;
				#thermal-sensor-cells = <1>;
			};
		};
	};

	thermal-zones {
		pmic {
			thermal-sensors = <&scmi_sensors0 0>;
		};

		soc {
			thermal-sensors = <&scmi_sensors0 3>;
		};

		big-cluster {
			thermal-sensors = <&scmi_sensors0 21>;
		};

		little-cluster {
			thermal-sensors = <&scmi_sensors0 22>;
		};

		gpu0 {
			thermal-sensors = <&scmi_sensors0 23>;
		};

		gpu1 {
			thermal-sensors = <&scmi_sensors0 24>;
		};
	};

};

&A53_0 {
	clocks = <&scmi_dvfs 1>;
};
&A53_1 {
	clocks = <&scmi_dvfs 1>;
};
&A53_2 {
	clocks = <&scmi_dvfs 1>;
};
&A53_3 {
	clocks = <&scmi_dvfs 1>;
};

&cpu_debug0 {
	power-domains = <&scmi_devpd 8>;
};
&cpu_debug1 {
	power-domains = <&scmi_devpd 8>;
};
&cpu_debug2 {
	power-domains = <&scmi_devpd 8>;
};
&cpu_debug3 {
	power-domains = <&scmi_devpd 8>;
};
&cpu_debug4 {
	power-domains = <&scmi_devpd 8>;
};
&cpu_debug5 {
	power-domains = <&scmi_devpd 8>;
};

&etm0 {
	power-domains = <&scmi_devpd 8>;
};
&etm1 {
	power-domains = <&scmi_devpd 8>;
};
&etm2 {
	power-domains = <&scmi_devpd 8>;
};
&etm3 {
	power-domains = <&scmi_devpd 8>;
};
&etm4 {
	power-domains = <&scmi_devpd 8>;
};
&etm5 {
	power-domains = <&scmi_devpd 8>;
};

&cti0 {
	power-domains = <&scmi_devpd 8>;
};
&cti1 {
	power-domains = <&scmi_devpd 8>;
};
&cti2 {
	power-domains = <&scmi_devpd 8>;
};
&cti3 {
	power-domains = <&scmi_devpd 8>;
};
&cti4 {
	power-domains = <&scmi_devpd 8>;
};
&cti5 {
	power-domains = <&scmi_devpd 8>;
};
&cti_sys0 {
	power-domains = <&scmi_devpd 8>;
};
&cti_sys1 {
	power-domains = <&scmi_devpd 8>;
};

&gpu {
	clocks = <&scmi_dvfs 2>;
	power-domains = <&scmi_devpd 9>;
};

&mailbox {
	compatible = "arm,mhu-doorbell", "arm,primecell";
	#mbox-cells = <2>;
};

&smmu_etr {
	power-domains = <&scmi_devpd 8>;
};

&smmu_gpu {
	power-domains = <&scmi_devpd 9>;
};

&sram {
	/delete-node/ scp-sram@0;
	/delete-node/ scp-sram@200;

	cpu_scp_lpri0: scp-sram@0 {
		compatible = "arm,scmi-shmem";
		reg = <0x0 0x80>;
	};

	cpu_scp_lpri1: scp-sram@80 {
		compatible = "arm,scmi-shmem";
		reg = <0x80 0x80>;
	};

	cpu_scp_hpri0: scp-sram@100 {
		compatible = "arm,scmi-shmem";
		reg = <0x100 0x80>;
	};

	cpu_scp_hpri1: scp-sram@180 {
		compatible = "arm,scmi-shmem";
		reg = <0x180 0x80>;
	};
};