code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
 *
 * Copyright (C) 2015, Applied Micro Circuits Corporation
 */

/ {
	compatible = "apm,xgene-shadowcat";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "apm,strega";
			reg = <0x0 0x000>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_0>;
			#clock-cells = <1>;
			clocks = <&pmd0clk 0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "apm,strega";
			reg = <0x0 0x001>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_0>;
			#clock-cells = <1>;
			clocks = <&pmd0clk 0>;
		};
		cpu@100 {
			device_type = "cpu";
			compatible = "apm,strega";
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_1>;
			#clock-cells = <1>;
			clocks = <&pmd1clk 0>;
		};
		cpu@101 {
			device_type = "cpu";
			compatible = "apm,strega";
			reg = <0x0 0x101>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_1>;
			#clock-cells = <1>;
			clocks = <&pmd1clk 0>;
		};
		cpu@200 {
			device_type = "cpu";
			compatible = "apm,strega";
			reg = <0x0 0x200>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_2>;
			#clock-cells = <1>;
			clocks = <&pmd2clk 0>;
		};
		cpu@201 {
			device_type = "cpu";
			compatible = "apm,strega";
			reg = <0x0 0x201>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_2>;
			#clock-cells = <1>;
			clocks = <&pmd2clk 0>;
		};
		cpu@300 {
			device_type = "cpu";
			compatible = "apm,strega";
			reg = <0x0 0x300>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_3>;
			#clock-cells = <1>;
			clocks = <&pmd3clk 0>;
		};
		cpu@301 {
			device_type = "cpu";
			compatible = "apm,strega";
			reg = <0x0 0x301>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_3>;
			#clock-cells = <1>;
			clocks = <&pmd3clk 0>;
		};
		xgene_L2_0: l2-cache-0 {
			compatible = "cache";
		};
		xgene_L2_1: l2-cache-1 {
			compatible = "cache";
		};
		xgene_L2_2: l2-cache-2 {
			compatible = "cache";
		};
		xgene_L2_3: l2-cache-3 {
			compatible = "cache";
		};
	};

	gic: interrupt-controller@78090000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		interrupt-controller;
		interrupts = <1 9 0xf04>;	/* GIC Maintenence IRQ */
		ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
		reg = <0x0 0x78090000 0x0 0x10000>,	/* GIC Dist */
		      <0x0 0x780a0000 0x0 0x20000>,	/* GIC CPU */
		      <0x0 0x780c0000 0x0 0x10000>,	/* GIC VCPU Control */
		      <0x0 0x780e0000 0x0 0x20000>;	/* GIC VCPU */
		v2m0: v2m@0 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0x0 0x0 0x1000>;
		};
		v2m1: v2m@10000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0x10000 0x0 0x1000>;
		};
		v2m2: v2m@20000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0x20000 0x0 0x1000>;
		};
		v2m3: v2m@30000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0x30000 0x0 0x1000>;
		};
		v2m4: v2m@40000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0x40000 0x0 0x1000>;
		};
		v2m5: v2m@50000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0x50000 0x0 0x1000>;
		};
		v2m6: v2m@60000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0x60000 0x0 0x1000>;
		};
		v2m7: v2m@70000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0x70000 0x0 0x1000>;
		};
		v2m8: v2m@80000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0x80000 0x0 0x1000>;
		};
		v2m9: v2m@90000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0x90000 0x0 0x1000>;
		};
		v2m10: v2m@a0000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0xa0000 0x0 0x1000>;
		};
		v2m11: v2m@b0000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0xb0000 0x0 0x1000>;
		};
		v2m12: v2m@c0000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0xc0000 0x0 0x1000>;
		};
		v2m13: v2m@d0000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0xd0000 0x0 0x1000>;
		};
		v2m14: v2m@e0000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0xe0000 0x0 0x1000>;
		};
		v2m15: v2m@f0000 {
			compatible = "arm,gic-v2m-frame";
			msi-controller;
			reg = <0x0 0xf0000 0x0 0x1000>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <1 12 0xff04>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 0 0xff08>,	/* Secure Phys IRQ */
			     <1 13 0xff08>,	/* Non-secure Phys IRQ */
			     <1 14 0xff08>,	/* Virt IRQ */
			     <1 15 0xff08>;	/* Hyp IRQ */
		clock-frequency = <50000000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		clocks {
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			refclk: refclk {
				compatible = "fixed-clock";
				#clock-cells = <1>;
				clock-frequency = <100000000>;
				clock-output-names = "refclk";
			};

			pmdpll: pmdpll@170000f0 {
				compatible = "apm,xgene-pcppll-v2-clock";
				#clock-cells = <1>;
				clocks = <&refclk 0>;
				reg = <0x0 0x170000f0 0x0 0x10>;
				clock-output-names = "pmdpll";
			};

			pmd0clk: pmd0clk@7e200200 {
				compatible = "apm,xgene-pmd-clock";
				#clock-cells = <1>;
				clocks = <&pmdpll 0>;
				reg = <0x0 0x7e200200 0x0 0x10>;
				clock-output-names = "pmd0clk";
			};

			pmd1clk: pmd1clk@7e200210 {
				compatible = "apm,xgene-pmd-clock";
				#clock-cells = <1>;
				clocks = <&pmdpll 0>;
				reg = <0x0 0x7e200210 0x0 0x10>;
				clock-output-names = "pmd1clk";
			};

			pmd2clk: pmd2clk@7e200220 {
				compatible = "apm,xgene-pmd-clock";
				#clock-cells = <1>;
				clocks = <&pmdpll 0>;
				reg = <0x0 0x7e200220 0x0 0x10>;
				clock-output-names = "pmd2clk";
			};

			pmd3clk: pmd3clk@7e200230 {
				compatible = "apm,xgene-pmd-clock";
				#clock-cells = <1>;
				clocks = <&pmdpll 0>;
				reg = <0x0 0x7e200230 0x0 0x10>;
				clock-output-names = "pmd3clk";
			};

			socpll: socpll@17000120 {
				compatible = "apm,xgene-socpll-v2-clock";
				#clock-cells = <1>;
				clocks = <&refclk 0>;
				reg = <0x0 0x17000120 0x0 0x1000>;
				clock-output-names = "socpll";
			};

			socplldiv2: socplldiv2  {
				compatible = "fixed-factor-clock";
				#clock-cells = <1>;
				clocks = <&socpll 0>;
				clock-mult = <1>;
				clock-div = <2>;
				clock-output-names = "socplldiv2";
			};

			ahbclk: ahbclk@17000000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x17000000 0x0 0x2000>;
				reg-names = "div-reg";
				divider-offset = <0x164>;
				divider-width = <0x5>;
				divider-shift = <0x0>;
				clock-output-names = "ahbclk";
			};

			sbapbclk: sbapbclk@1704c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&ahbclk 0>;
				reg = <0x0 0x1704c000 0x0 0x2000>;
				reg-names = "div-reg";
				divider-offset = <0x10>;
				divider-width = <0x2>;
				divider-shift = <0x0>;
				clock-output-names = "sbapbclk";
			};

			sdioclk: sdioclk@1f2ac000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2ac000 0x0 0x1000
					0x0 0x17000000 0x0 0x2000>;
				reg-names = "csr-reg", "div-reg";
				csr-offset = <0x0>;
				csr-mask = <0x2>;
				enable-offset = <0x8>;
				enable-mask = <0x2>;
				divider-offset = <0x178>;
				divider-width = <0x8>;
				divider-shift = <0x0>;
				clock-output-names = "sdioclk";
			};

			pcie0clk: pcie0clk@1f2bc000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2bc000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie0clk";
			};

			pcie1clk: pcie1clk@1f2cc000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2cc000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie1clk";
			};

			xge0clk: xge0clk@1f61c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f61c000 0x0 0x1000>;
				reg-names = "csr-reg";
				enable-mask = <0x3>;
				csr-mask = <0x3>;
				clock-output-names = "xge0clk";
			};

			xge1clk: xge1clk@1f62c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f62c000 0x0 0x1000>;
				reg-names = "csr-reg";
				enable-mask = <0x3>;
				csr-mask = <0x3>;
				clock-output-names = "xge1clk";
			};

			rngpkaclk: rngpkaclk@17000000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x17000000 0x0 0x2000>;
				reg-names = "csr-reg";
				csr-offset = <0xc>;
				csr-mask = <0x10>;
				enable-offset = <0x10>;
				enable-mask = <0x10>;
				clock-output-names = "rngpkaclk";
			};

			i2c4clk: i2c4clk@1704c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&sbapbclk 0>;
				reg = <0x0 0x1704c000 0x0 0x1000>;
				reg-names = "csr-reg";
				csr-offset = <0x0>;
				csr-mask = <0x40>;
				enable-offset = <0x8>;
				enable-mask = <0x40>;
				clock-output-names = "i2c4clk";
			};
		};

		scu: system-clk-controller@17000000 {
			compatible = "apm,xgene-scu","syscon";
			reg = <0x0 0x17000000 0x0 0x400>;
		};

		reboot: reboot@17000014 {
			compatible = "syscon-reboot";
			regmap = <&scu>;
			offset = <0x14>;
			mask = <0x1>;
		};

		csw: csw@7e200000 {
			compatible = "apm,xgene-csw", "syscon";
			reg = <0x0 0x7e200000 0x0 0x1000>;
		};

		mcba: mcba@7e700000 {
			compatible = "apm,xgene-mcb", "syscon";
			reg = <0x0 0x7e700000 0x0 0x1000>;
		};

		mcbb: mcbb@7e720000 {
			compatible = "apm,xgene-mcb", "syscon";
			reg = <0x0 0x7e720000 0x0 0x1000>;
		};

		efuse: efuse@1054a000 {
			compatible = "apm,xgene-efuse", "syscon";
			reg = <0x0 0x1054a000 0x0 0x20>;
		};

		edac@78800000 {
			compatible = "apm,xgene-edac";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			regmap-csw = <&csw>;
			regmap-mcba = <&mcba>;
			regmap-mcbb = <&mcbb>;
			regmap-efuse = <&efuse>;
			reg = <0x0 0x78800000 0x0 0x100>;
			interrupts = <0x0 0x20 0x4>,
				     <0x0 0x21 0x4>,
				     <0x0 0x27 0x4>;

			edacmc@7e800000 {
				compatible = "apm,xgene-edac-mc";
				reg = <0x0 0x7e800000 0x0 0x1000>;
				memory-controller = <0>;
			};

			edacmc@7e840000 {
				compatible = "apm,xgene-edac-mc";
				reg = <0x0 0x7e840000 0x0 0x1000>;
				memory-controller = <1>;
			};

			edacmc@7e880000 {
				compatible = "apm,xgene-edac-mc";
				reg = <0x0 0x7e880000 0x0 0x1000>;
				memory-controller = <2>;
			};

			edacmc@7e8c0000 {
				compatible = "apm,xgene-edac-mc";
				reg = <0x0 0x7e8c0000 0x0 0x1000>;
				memory-controller = <3>;
			};

			edacpmd@7c000000 {
				compatible = "apm,xgene-edac-pmd";
				reg = <0x0 0x7c000000 0x0 0x200000>;
				pmd-controller = <0>;
			};

			edacpmd@7c200000 {
				compatible = "apm,xgene-edac-pmd";
				reg = <0x0 0x7c200000 0x0 0x200000>;
				pmd-controller = <1>;
			};

			edacpmd@7c400000 {
				compatible = "apm,xgene-edac-pmd";
				reg = <0x0 0x7c400000 0x0 0x200000>;
				pmd-controller = <2>;
			};

			edacpmd@7c600000 {
				compatible = "apm,xgene-edac-pmd";
				reg = <0x0 0x7c600000 0x0 0x200000>;
				pmd-controller = <3>;
			};

			edacl3@7e600000 {
				compatible = "apm,xgene-edac-l3-v2";
				reg = <0x0 0x7e600000 0x0 0x1000>;
			};

			edacsoc@7e930000 {
				compatible = "apm,xgene-edac-soc";
				reg = <0x0 0x7e930000 0x0 0x1000>;
			};
		};

		pmu: pmu@78810000 {
			compatible = "apm,xgene-pmu-v2";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			regmap-csw = <&csw>;
			regmap-mcba = <&mcba>;
			regmap-mcbb = <&mcbb>;
			reg = <0x0 0x78810000 0x0 0x1000>;
			interrupts = <0x0 0x22 0x4>;

			pmul3c@7e610000 {
				compatible = "apm,xgene-pmu-l3c";
				reg = <0x0 0x7e610000 0x0 0x1000>;
			};

			pmuiob@7e940000 {
				compatible = "apm,xgene-pmu-iob";
				reg = <0x0 0x7e940000 0x0 0x1000>;
			};

			pmucmcb@7e710000 {
				compatible = "apm,xgene-pmu-mcb";
				reg = <0x0 0x7e710000 0x0 0x1000>;
				enable-bit-index = <0>;
			};

			pmucmcb@7e730000 {
				compatible = "apm,xgene-pmu-mcb";
				reg = <0x0 0x7e730000 0x0 0x1000>;
				enable-bit-index = <1>;
			};

			pmucmc@7e810000 {
				compatible = "apm,xgene-pmu-mc";
				reg = <0x0 0x7e810000 0x0 0x1000>;
				enable-bit-index = <0>;
			};

			pmucmc@7e850000 {
				compatible = "apm,xgene-pmu-mc";
				reg = <0x0 0x7e850000 0x0 0x1000>;
				enable-bit-index = <1>;
			};

			pmucmc@7e890000 {
				compatible = "apm,xgene-pmu-mc";
				reg = <0x0 0x7e890000 0x0 0x1000>;
				enable-bit-index = <2>;
			};

			pmucmc@7e8d0000 {
				compatible = "apm,xgene-pmu-mc";
				reg = <0x0 0x7e8d0000 0x0 0x1000>;
				enable-bit-index = <3>;
			};
		};

		mailbox: mailbox@10540000 {
			compatible = "apm,xgene-slimpro-mbox";
			reg = <0x0 0x10540000 0x0 0x8000>;
			#mbox-cells = <1>;
			interrupts =   <0x0 0x0 0x4
					0x0 0x1 0x4
					0x0 0x2 0x4
					0x0 0x3 0x4
					0x0 0x4 0x4
					0x0 0x5 0x4
					0x0 0x6 0x4
					0x0 0x7 0x4>;
		};

		i2cslimpro {
			compatible = "apm,xgene-slimpro-i2c";
			mboxes = <&mailbox 0>;
		};

		hwmonslimpro {
			compatible = "apm,xgene-slimpro-hwmon";
			mboxes = <&mailbox 7>;
		};

		serial0: serial@10600000 {
			device_type = "serial";
			compatible = "ns16550";
			reg = <0 0x10600000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>;
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4c 0x4>;
		};

		/* Node-name might need to be coded as dwusb for backward compatibility */
		usb0: usb@19000000 {
			status = "disabled";
			compatible = "snps,dwc3";
			reg = <0x0 0x19000000 0x0 0x100000>;
			interrupts = <0x0 0x5d 0x4>;
			dma-coherent;
			dr_mode = "host";
		};

		pcie0: pcie@1f2b0000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
				0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io */
				  0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000   /* mem */
				  0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			bus-range = <0x00 0xff>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
					 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
					 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4
					 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>;
			dma-coherent;
			clocks = <&pcie0clk 0>;
			msi-parent = <&v2m0>;
		};

		pcie1: pcie@1f2c0000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
				0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io */
				  0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000   /* mem */
				  0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			bus-range = <0x00 0xff>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
					 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
					 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4
					 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>;
			dma-coherent;
			clocks = <&pcie1clk 0>;
			msi-parent = <&v2m0>;
		};

		sata1: sata@1a000000 {
			compatible = "apm,xgene-ahci-v2";
			reg = <0x0 0x1a000000 0x0 0x1000>,
			      <0x0 0x1f200000 0x0 0x1000>,
			      <0x0 0x1f20d000 0x0 0x1000>,
			      <0x0 0x1f20e000 0x0 0x1000>;
			interrupts = <0x0 0x5a 0x4>;
			dma-coherent;
		};

		sata2: sata@1a200000 {
			compatible = "apm,xgene-ahci-v2";
			reg = <0x0 0x1a200000 0x0 0x1000>,
			      <0x0 0x1f210000 0x0 0x1000>,
			      <0x0 0x1f21d000 0x0 0x1000>,
			      <0x0 0x1f21e000 0x0 0x1000>;
			interrupts = <0x0 0x5b 0x4>;
			dma-coherent;
		};

		sata3: sata@1a400000 {
			compatible = "apm,xgene-ahci-v2";
			reg = <0x0 0x1a400000 0x0 0x1000>,
			      <0x0 0x1f220000 0x0 0x1000>,
			      <0x0 0x1f22d000 0x0 0x1000>,
			      <0x0 0x1f22e000 0x0 0x1000>;
			interrupts = <0x0 0x5c 0x4>;
			dma-coherent;
		};

		mmc0: mmc@1c000000 {
			compatible = "arasan,sdhci-4.9a";
			reg = <0x0 0x1c000000 0x0 0x100>;
			interrupts = <0x0 0x49 0x4>;
			dma-coherent;
			no-1-8-v;
			clock-names = "clk_xin", "clk_ahb";
			clocks = <&sdioclk 0>, <&ahbclk 0>;
		};

		gfcgpio: gpio@1f63c000 {
			compatible = "apm,xgene-gpio";
			reg = <0x0 0x1f63c000 0x0 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		dwgpio: gpio@1c024000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x0 0x1c024000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
			};
		};

		sbgpio: gpio@17001000{
			compatible = "apm,xgene-gpio-sb";
			reg = <0x0 0x17001000 0x0 0x400>;
			#gpio-cells = <2>;
			gpio-controller;
			interrupts = <0x0 0x28 0x1>,
				     <0x0 0x29 0x1>,
				     <0x0 0x2a 0x1>,
				     <0x0 0x2b 0x1>,
				     <0x0 0x2c 0x1>,
				     <0x0 0x2d 0x1>,
				     <0x0 0x2e 0x1>,
				     <0x0 0x2f 0x1>;
			interrupt-parent = <&gic>;
			#interrupt-cells = <2>;
			interrupt-controller;
			apm,nr-gpios = <22>;
			apm,nr-irqs = <8>;
			apm,irq-start = <8>;
		};

		mdio: mdio@1f610000 {
			compatible = "apm,xgene-mdio-xfi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x1f610000 0x0 0xd100>;
			clocks = <&xge0clk 0>;
		};

		sgenet0: ethernet@1f610000 {
			compatible = "apm,xgene2-sgenet";
			status = "disabled";
			reg = <0x0 0x1f610000 0x0 0xd100>,
			      <0x0 0x1f600000 0x0 0xd100>,
			      <0x0 0x20000000 0x0 0x20000>;
			interrupts = <0 96 4>,
				     <0 97 4>;
			dma-coherent;
			clocks = <&xge0clk 0>;
			local-mac-address = [00 01 73 00 00 01];
			phy-connection-type = "sgmii";
			phy-handle = <&sgenet0phy>;
		};

		xgenet1: ethernet@1f620000 {
			compatible = "apm,xgene2-xgenet";
			status = "disabled";
			reg = <0x0 0x1f620000 0x0 0x10000>,
			      <0x0 0x1f600000 0x0 0xd100>,
			      <0x0 0x20000000 0x0 0x220000>;
			interrupts = <0 108 4>,
				     <0 109 4>,
				     <0 110 4>,
				     <0 111 4>,
				     <0 112 4>,
				     <0 113 4>,
				     <0 114 4>,
				     <0 115 4>;
			channel = <12>;
			port-id = <1>;
			dma-coherent;
			clocks = <&xge1clk 0>;
			local-mac-address = [00 01 73 00 00 02];
			phy-connection-type = "xgmii";
		};

		rng: rng@10520000 {
			compatible = "apm,xgene-rng";
			reg = <0x0 0x10520000 0x0 0x100>;
			interrupts = <0x0 0x41 0x4>;
			clocks = <&rngpkaclk 0>;
		};

		i2c1: i2c@10511000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x0 0x10511000 0x0 0x1000>;
			interrupts = <0 0x45 0x4>;
			#clock-cells = <1>;
			clocks = <&sbapbclk 0>;
			bus_num = <1>;
		};

		i2c4: i2c@10640000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x0 0x10640000 0x0 0x1000>;
			interrupts = <0 0x3a 0x4>;
			clocks = <&i2c4clk 0>;
			bus_num = <4>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * dts file for AppliedMicro (APM) X-Gene Storm SOC
 *
 * Copyright (C) 2013, Applied Micro Circuits Corporation
 */

/ {
	compatible = "apm,xgene-storm";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "apm,potenza";
			reg = <0x0 0x000>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "apm,potenza";
			reg = <0x0 0x001>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_0>;
		};
		cpu@100 {
			device_type = "cpu";
			compatible = "apm,potenza";
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_1>;
		};
		cpu@101 {
			device_type = "cpu";
			compatible = "apm,potenza";
			reg = <0x0 0x101>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_1>;
		};
		cpu@200 {
			device_type = "cpu";
			compatible = "apm,potenza";
			reg = <0x0 0x200>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_2>;
		};
		cpu@201 {
			device_type = "cpu";
			compatible = "apm,potenza";
			reg = <0x0 0x201>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_2>;
		};
		cpu@300 {
			device_type = "cpu";
			compatible = "apm,potenza";
			reg = <0x0 0x300>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_3>;
		};
		cpu@301 {
			device_type = "cpu";
			compatible = "apm,potenza";
			reg = <0x0 0x301>;
			enable-method = "spin-table";
			cpu-release-addr = <0x1 0x0000fff8>;
			next-level-cache = <&xgene_L2_3>;
		};
		xgene_L2_0: l2-cache-0 {
			compatible = "cache";
		};
		xgene_L2_1: l2-cache-1 {
			compatible = "cache";
		};
		xgene_L2_2: l2-cache-2 {
			compatible = "cache";
		};
		xgene_L2_3: l2-cache-3 {
			compatible = "cache";
		};
	};

	gic: interrupt-controller@78010000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x78010000 0x0 0x1000>,	/* GIC Dist */
		      <0x0 0x78020000 0x0 0x1000>,	/* GIC CPU */
		      <0x0 0x78040000 0x0 0x2000>,	/* GIC VCPU Control */
		      <0x0 0x78060000 0x0 0x2000>;	/* GIC VCPU */
		interrupts = <1 9 0xf04>;	/* GIC Maintenence IRQ */
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 0 0xff08>,	/* Secure Phys IRQ */
			     <1 13 0xff08>,	/* Non-secure Phys IRQ */
			     <1 14 0xff08>,	/* Virt IRQ */
			     <1 15 0xff08>;	/* Hyp IRQ */
		clock-frequency = <50000000>;
	};

	pmu {
		compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
		interrupts = <1 12 0xff04>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;

		clocks {
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			refclk: refclk {
				compatible = "fixed-clock";
				#clock-cells = <1>;
				clock-frequency = <100000000>;
				clock-output-names = "refclk";
			};

			pcppll: pcppll@17000100 {
				compatible = "apm,xgene-pcppll-clock";
				#clock-cells = <1>;
				clocks = <&refclk 0>;
				clock-names = "pcppll";
				reg = <0x0 0x17000100 0x0 0x1000>;
				clock-output-names = "pcppll";
				type = <0>;
			};

			socpll: socpll@17000120 {
				compatible = "apm,xgene-socpll-clock";
				#clock-cells = <1>;
				clocks = <&refclk 0>;
				clock-names = "socpll";
				reg = <0x0 0x17000120 0x0 0x1000>;
				clock-output-names = "socpll";
				type = <1>;
			};

			socplldiv2: socplldiv2  {
				compatible = "fixed-factor-clock";
				#clock-cells = <1>;
				clocks = <&socpll 0>;
				clock-names = "socplldiv2";
				clock-mult = <1>;
				clock-div = <2>;
				clock-output-names = "socplldiv2";
			};

			ahbclk: ahbclk@17000000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x17000000 0x0 0x2000>;
				reg-names = "div-reg";
				divider-offset = <0x164>;
				divider-width = <0x5>;
				divider-shift = <0x0>;
				clock-output-names = "ahbclk";
			};

			sdioclk: sdioclk@1f2ac000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2ac000 0x0 0x1000
					0x0 0x17000000 0x0 0x2000>;
				reg-names = "csr-reg", "div-reg";
				csr-offset = <0x0>;
				csr-mask = <0x2>;
				enable-offset = <0x8>;
				enable-mask = <0x2>;
				divider-offset = <0x178>;
				divider-width = <0x8>;
				divider-shift = <0x0>;
				clock-output-names = "sdioclk";
			};

			ethclk: ethclk {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				clock-names = "ethclk";
				reg = <0x0 0x17000000 0x0 0x1000>;
				reg-names = "div-reg";
				divider-offset = <0x238>;
				divider-width = <0x9>;
				divider-shift = <0x0>;
				clock-output-names = "ethclk";
			};

			menetclk: menetclk {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&ethclk 0>;
				reg = <0x0 0x1702c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "menetclk";
			};

			sge0clk: sge0clk@1f21c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				reg-names = "csr-reg";
				csr-mask = <0xa>;
				enable-mask = <0xf>;
				clock-output-names = "sge0clk";
			};

			xge0clk: xge0clk@1f61c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f61c000 0x0 0x1000>;
				reg-names = "csr-reg";
				csr-mask = <0x3>;
				clock-output-names = "xge0clk";
			};

			xge1clk: xge1clk@1f62c000 {
				compatible = "apm,xgene-device-clock";
				status = "disabled";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f62c000 0x0 0x1000>;
				reg-names = "csr-reg";
				csr-mask = <0x3>;
				clock-output-names = "xge1clk";
			};

			sataphy1clk: sataphy1clk@1f21c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sataphy1clk";
				status = "disabled";
				csr-offset = <0x4>;
				csr-mask = <0x00>;
				enable-offset = <0x0>;
				enable-mask = <0x06>;
			};

			sataphy2clk: sataphy1clk@1f22c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f22c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sataphy2clk";
				status = "ok";
				csr-offset = <0x4>;
				csr-mask = <0x3a>;
				enable-offset = <0x0>;
				enable-mask = <0x06>;
			};

			sataphy3clk: sataphy1clk@1f23c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f23c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sataphy3clk";
				status = "ok";
				csr-offset = <0x4>;
				csr-mask = <0x3a>;
				enable-offset = <0x0>;
				enable-mask = <0x06>;
			};

			sata01clk: sata01clk@1f21c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f21c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sata01clk";
				csr-offset = <0x4>;
				csr-mask = <0x05>;
				enable-offset = <0x0>;
				enable-mask = <0x39>;
			};

			sata23clk: sata23clk@1f22c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f22c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sata23clk";
				csr-offset = <0x4>;
				csr-mask = <0x05>;
				enable-offset = <0x0>;
				enable-mask = <0x39>;
			};

			sata45clk: sata45clk@1f23c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f23c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "sata45clk";
				csr-offset = <0x4>;
				csr-mask = <0x05>;
				enable-offset = <0x0>;
				enable-mask = <0x39>;
			};

			rtcclk: rtcclk@17000000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x17000000 0x0 0x2000>;
				reg-names = "csr-reg";
				csr-offset = <0xc>;
				csr-mask = <0x2>;
				enable-offset = <0x10>;
				enable-mask = <0x2>;
				clock-output-names = "rtcclk";
			};

			rngpkaclk: rngpkaclk@17000000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x17000000 0x0 0x2000>;
				reg-names = "csr-reg";
				csr-offset = <0xc>;
				csr-mask = <0x10>;
				enable-offset = <0x10>;
				enable-mask = <0x10>;
				clock-output-names = "rngpkaclk";
			};

			pcie0clk: pcie0clk@1f2bc000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2bc000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie0clk";
			};

			pcie1clk: pcie1clk@1f2cc000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2cc000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie1clk";
			};

			pcie2clk: pcie2clk@1f2dc000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f2dc000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie2clk";
			};

			pcie3clk: pcie3clk@1f50c000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f50c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie3clk";
			};

			pcie4clk: pcie4clk@1f51c000 {
				status = "disabled";
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f51c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "pcie4clk";
			};

			dmaclk: dmaclk@1f27c000 {
				compatible = "apm,xgene-device-clock";
				#clock-cells = <1>;
				clocks = <&socplldiv2 0>;
				reg = <0x0 0x1f27c000 0x0 0x1000>;
				reg-names = "csr-reg";
				clock-output-names = "dmaclk";
			};
		};

		msi: msi@79000000 {
			compatible = "apm,xgene1-msi";
			msi-controller;
			reg = <0x00 0x79000000 0x0 0x900000>;
			interrupts = <  0x0 0x10 0x4
					0x0 0x11 0x4
					0x0 0x12 0x4
					0x0 0x13 0x4
					0x0 0x14 0x4
					0x0 0x15 0x4
					0x0 0x16 0x4
					0x0 0x17 0x4
					0x0 0x18 0x4
					0x0 0x19 0x4
					0x0 0x1a 0x4
					0x0 0x1b 0x4
					0x0 0x1c 0x4
					0x0 0x1d 0x4
					0x0 0x1e 0x4
					0x0 0x1f 0x4>;
		};

		scu: system-clk-controller@17000000 {
			compatible = "apm,xgene-scu","syscon";
			reg = <0x0 0x17000000 0x0 0x400>;
		};

		reboot: reboot@17000014 {
			compatible = "syscon-reboot";
			regmap = <&scu>;
			offset = <0x14>;
			mask = <0x1>;
		};

		csw: csw@7e200000 {
			compatible = "apm,xgene-csw", "syscon";
			reg = <0x0 0x7e200000 0x0 0x1000>;
		};

		mcba: mcba@7e700000 {
			compatible = "apm,xgene-mcb", "syscon";
			reg = <0x0 0x7e700000 0x0 0x1000>;
		};

		mcbb: mcbb@7e720000 {
			compatible = "apm,xgene-mcb", "syscon";
			reg = <0x0 0x7e720000 0x0 0x1000>;
		};

		efuse: efuse@1054a000 {
			compatible = "apm,xgene-efuse", "syscon";
			reg = <0x0 0x1054a000 0x0 0x20>;
		};

		rb: rb@7e000000 {
			compatible = "apm,xgene-rb", "syscon";
			reg = <0x0 0x7e000000 0x0 0x10>;
		};

		edac@78800000 {
			compatible = "apm,xgene-edac";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			regmap-csw = <&csw>;
			regmap-mcba = <&mcba>;
			regmap-mcbb = <&mcbb>;
			regmap-efuse = <&efuse>;
			regmap-rb = <&rb>;
			reg = <0x0 0x78800000 0x0 0x100>;
			interrupts = <0x0 0x20 0x4>,
				     <0x0 0x21 0x4>,
				     <0x0 0x27 0x4>;

			edacmc@7e800000 {
				compatible = "apm,xgene-edac-mc";
				reg = <0x0 0x7e800000 0x0 0x1000>;
				memory-controller = <0>;
			};

			edacmc@7e840000 {
				compatible = "apm,xgene-edac-mc";
				reg = <0x0 0x7e840000 0x0 0x1000>;
				memory-controller = <1>;
			};

			edacmc@7e880000 {
				compatible = "apm,xgene-edac-mc";
				reg = <0x0 0x7e880000 0x0 0x1000>;
				memory-controller = <2>;
			};

			edacmc@7e8c0000 {
				compatible = "apm,xgene-edac-mc";
				reg = <0x0 0x7e8c0000 0x0 0x1000>;
				memory-controller = <3>;
			};

			edacpmd@7c000000 {
				compatible = "apm,xgene-edac-pmd";
				reg = <0x0 0x7c000000 0x0 0x200000>;
				pmd-controller = <0>;
			};

			edacpmd@7c200000 {
				compatible = "apm,xgene-edac-pmd";
				reg = <0x0 0x7c200000 0x0 0x200000>;
				pmd-controller = <1>;
			};

			edacpmd@7c400000 {
				compatible = "apm,xgene-edac-pmd";
				reg = <0x0 0x7c400000 0x0 0x200000>;
				pmd-controller = <2>;
			};

			edacpmd@7c600000 {
				compatible = "apm,xgene-edac-pmd";
				reg = <0x0 0x7c600000 0x0 0x200000>;
				pmd-controller = <3>;
			};

			edacl3@7e600000 {
				compatible = "apm,xgene-edac-l3";
				reg = <0x0 0x7e600000 0x0 0x1000>;
			};

			edacsoc@7e930000 {
				compatible = "apm,xgene-edac-soc-v1";
				reg = <0x0 0x7e930000 0x0 0x1000>;
			};
		};

		pmu: pmu@78810000 {
			compatible = "apm,xgene-pmu-v2";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			regmap-csw = <&csw>;
			regmap-mcba = <&mcba>;
			regmap-mcbb = <&mcbb>;
			reg = <0x0 0x78810000 0x0 0x1000>;
			interrupts = <0x0 0x22 0x4>;

			pmul3c@7e610000 {
				compatible = "apm,xgene-pmu-l3c";
				reg = <0x0 0x7e610000 0x0 0x1000>;
			};

			pmuiob@7e940000 {
				compatible = "apm,xgene-pmu-iob";
				reg = <0x0 0x7e940000 0x0 0x1000>;
			};

			pmucmcb@7e710000 {
				compatible = "apm,xgene-pmu-mcb";
				reg = <0x0 0x7e710000 0x0 0x1000>;
				enable-bit-index = <0>;
			};

			pmucmcb@7e730000 {
				compatible = "apm,xgene-pmu-mcb";
				reg = <0x0 0x7e730000 0x0 0x1000>;
				enable-bit-index = <1>;
			};

			pmucmc@7e810000 {
				compatible = "apm,xgene-pmu-mc";
				reg = <0x0 0x7e810000 0x0 0x1000>;
				enable-bit-index = <0>;
			};

			pmucmc@7e850000 {
				compatible = "apm,xgene-pmu-mc";
				reg = <0x0 0x7e850000 0x0 0x1000>;
				enable-bit-index = <1>;
			};

			pmucmc@7e890000 {
				compatible = "apm,xgene-pmu-mc";
				reg = <0x0 0x7e890000 0x0 0x1000>;
				enable-bit-index = <2>;
			};

			pmucmc@7e8d0000 {
				compatible = "apm,xgene-pmu-mc";
				reg = <0x0 0x7e8d0000 0x0 0x1000>;
				enable-bit-index = <3>;
			};
		};

		pcie0: pcie@1f2b0000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
				0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
				  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
				  0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			bus-range = <0x00 0xff>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
					 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
					 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
					 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
			dma-coherent;
			clocks = <&pcie0clk 0>;
			msi-parent = <&msi>;
		};

		pcie1: pcie@1f2c0000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
				0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
				  0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
				  0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			bus-range = <0x00 0xff>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
					 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
					 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
					 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
			dma-coherent;
			clocks = <&pcie1clk 0>;
			msi-parent = <&msi>;
		};

		pcie2: pcie@1f2d0000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
				 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
				  0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
				  0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			bus-range = <0x00 0xff>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
					 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
					 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
					 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
			dma-coherent;
			clocks = <&pcie2clk 0>;
			msi-parent = <&msi>;
		};

		pcie3: pcie@1f500000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
				0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
				  0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
				  0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			bus-range = <0x00 0xff>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
					 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
					 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
					 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
			dma-coherent;
			clocks = <&pcie3clk 0>;
			msi-parent = <&msi>;
		};

		pcie4: pcie@1f510000 {
			status = "disabled";
			device_type = "pci";
			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
				0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
			reg-names = "csr", "cfg";
			ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
				  0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
				  0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
			bus-range = <0x00 0xff>;
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
					 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
					 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
					 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
			dma-coherent;
			clocks = <&pcie4clk 0>;
			msi-parent = <&msi>;
		};

		mailbox: mailbox@10540000 {
			compatible = "apm,xgene-slimpro-mbox";
			reg = <0x0 0x10540000 0x0 0xa000>;
			#mbox-cells = <1>;
			interrupts =    <0x0 0x0 0x4>,
					<0x0 0x1 0x4>,
					<0x0 0x2 0x4>,
					<0x0 0x3 0x4>,
					<0x0 0x4 0x4>,
					<0x0 0x5 0x4>,
					<0x0 0x6 0x4>,
					<0x0 0x7 0x4>;
		};

		i2cslimpro {
			compatible = "apm,xgene-slimpro-i2c";
			mboxes = <&mailbox 0>;
		};

		hwmonslimpro {
			compatible = "apm,xgene-slimpro-hwmon";
			mboxes = <&mailbox 7>;
		};

		serial0: serial@1c020000 {
			status = "disabled";
			device_type = "serial";
			compatible = "ns16550a";
			reg = <0 0x1c020000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>; /* Updated by bootloader */
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4c 0x4>;
		};

		serial1: serial@1c021000 {
			status = "disabled";
			device_type = "serial";
			compatible = "ns16550a";
			reg = <0 0x1c021000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>; /* Updated by bootloader */
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4d 0x4>;
		};

		serial2: serial@1c022000 {
			status = "disabled";
			device_type = "serial";
			compatible = "ns16550a";
			reg = <0 0x1c022000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>; /* Updated by bootloader */
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4e 0x4>;
		};

		serial3: serial@1c023000 {
			status = "disabled";
			device_type = "serial";
			compatible = "ns16550a";
			reg = <0 0x1c023000 0x0 0x1000>;
			reg-shift = <2>;
			clock-frequency = <10000000>; /* Updated by bootloader */
			interrupt-parent = <&gic>;
			interrupts = <0x0 0x4f 0x4>;
		};

		mmc0: mmc@1c000000 {
			compatible = "arasan,sdhci-4.9a";
			reg = <0x0 0x1c000000 0x0 0x100>;
			interrupts = <0x0 0x49 0x4>;
			dma-coherent;
			no-1-8-v;
			clock-names = "clk_xin", "clk_ahb";
			clocks = <&sdioclk 0>, <&ahbclk 0>;
		};

		gfcgpio: gpio0@1701c000 {
			compatible = "apm,xgene-gpio";
			reg = <0x0 0x1701c000 0x0 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		dwgpio: gpio@1c024000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x0 0x1c024000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
			};
		};

		i2c0: i2c@10512000 {
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x0 0x10512000 0x0 0x1000>;
			interrupts = <0 0x44 0x4>;
			#clock-cells = <1>;
			clocks = <&ahbclk 0>;
			bus_num = <0>;
		};

		phy1: phy@1f21a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f21a000 0x0 0x100>;
			#phy-cells = <1>;
			clocks = <&sataphy1clk 0>;
			status = "disabled";
			apm,tx-boost-gain = <30 30 30 30 30 30>;
			apm,tx-eye-tuning = <2 10 10 2 10 10>;
		};

		phy2: phy@1f22a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f22a000 0x0 0x100>;
			#phy-cells = <1>;
			clocks = <&sataphy2clk 0>;
			status = "ok";
			apm,tx-boost-gain = <30 30 30 30 30 30>;
			apm,tx-eye-tuning = <1 10 10 2 10 10>;
		};

		phy3: phy@1f23a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f23a000 0x0 0x100>;
			#phy-cells = <1>;
			clocks = <&sataphy3clk 0>;
			status = "ok";
			apm,tx-boost-gain = <31 31 31 31 31 31>;
			apm,tx-eye-tuning = <2 10 10 2 10 10>;
		};

		sata1: sata@1a000000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a000000 0x0 0x1000>,
			      <0x0 0x1f210000 0x0 0x1000>,
			      <0x0 0x1f21d000 0x0 0x1000>,
			      <0x0 0x1f21e000 0x0 0x1000>,
			      <0x0 0x1f217000 0x0 0x1000>;
			interrupts = <0x0 0x86 0x4>;
			dma-coherent;
			status = "disabled";
			clocks = <&sata01clk 0>;
			phys = <&phy1 0>;
			phy-names = "sata-phy";
		};

		sata2: sata@1a400000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a400000 0x0 0x1000>,
			      <0x0 0x1f220000 0x0 0x1000>,
			      <0x0 0x1f22d000 0x0 0x1000>,
			      <0x0 0x1f22e000 0x0 0x1000>,
			      <0x0 0x1f227000 0x0 0x1000>;
			interrupts = <0x0 0x87 0x4>;
			dma-coherent;
			status = "ok";
			clocks = <&sata23clk 0>;
			phys = <&phy2 0>;
			phy-names = "sata-phy";
		};

		sata3: sata@1a800000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a800000 0x0 0x1000>,
			      <0x0 0x1f230000 0x0 0x1000>,
			      <0x0 0x1f23d000 0x0 0x1000>,
			      <0x0 0x1f23e000 0x0 0x1000>;
			interrupts = <0x0 0x88 0x4>;
			dma-coherent;
			status = "ok";
			clocks = <&sata45clk 0>;
			phys = <&phy3 0>;
			phy-names = "sata-phy";
		};

		/* Node-name might need to be coded as dwusb for backward compatibility */
		usb0: usb@19000000 {
			status = "disabled";
			compatible = "snps,dwc3";
			reg = <0x0 0x19000000 0x0 0x100000>;
			interrupts = <0x0 0x89 0x4>;
			dma-coherent;
			dr_mode = "host";
		};

		usb1: usb@19800000 {
			status = "disabled";
			compatible = "snps,dwc3";
			reg = <0x0 0x19800000 0x0 0x100000>;
			interrupts = <0x0 0x8a 0x4>;
			dma-coherent;
			dr_mode = "host";
		};

		sbgpio: gpio@17001000{
			compatible = "apm,xgene-gpio-sb";
			reg = <0x0 0x17001000 0x0 0x400>;
			#gpio-cells = <2>;
			gpio-controller;
			interrupts = 	<0x0 0x28 0x1>,
					<0x0 0x29 0x1>,
					<0x0 0x2a 0x1>,
					<0x0 0x2b 0x1>,
					<0x0 0x2c 0x1>,
					<0x0 0x2d 0x1>;
			interrupt-parent = <&gic>;
			#interrupt-cells = <2>;
			interrupt-controller;
		};

		rtc: rtc@10510000 {
			compatible = "apm,xgene-rtc";
			reg = <0x0 0x10510000 0x0 0x400>;
			interrupts = <0x0 0x46 0x4>;
			#clock-cells = <1>;
			clocks = <&rtcclk 0>;
		};

		mdio: mdio@17020000 {
			compatible = "apm,xgene-mdio-rgmii";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x17020000 0x0 0xd100>;
			clocks = <&menetclk 0>;
		};

		menet: ethernet@17020000 {
			compatible = "apm,xgene-enet";
			status = "disabled";
			reg = <0x0 0x17020000 0x0 0xd100>,
			      <0x0 0x17030000 0x0 0xc300>,
			      <0x0 0x10000000 0x0 0x200>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0x3c 0x4>;
			dma-coherent;
			clocks = <&menetclk 0>;
			/* mac address will be overwritten by the bootloader */
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "rgmii";
			phy-handle = <&menetphy>,<&menet0phy>;
			mdio {
				compatible = "apm,xgene-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
				menetphy: menetphy@3 {
					compatible = "ethernet-phy-id001c.c915";
					reg = <0x3>;
				};

			};
		};

		sgenet0: ethernet@1f210000 {
			compatible = "apm,xgene1-sgenet";
			status = "disabled";
			reg = <0x0 0x1f210000 0x0 0xd100>,
			      <0x0 0x1f200000 0x0 0xc300>,
			      <0x0 0x1b000000 0x0 0x200>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0xa0 0x4>,
				     <0x0 0xa1 0x4>;
			dma-coherent;
			clocks = <&sge0clk 0>;
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "sgmii";
			phy-handle = <&sgenet0phy>;
		};

		sgenet1: ethernet@1f210030 {
			compatible = "apm,xgene1-sgenet";
			status = "disabled";
			reg = <0x0 0x1f210030 0x0 0xd100>,
			      <0x0 0x1f200000 0x0 0xc300>,
			      <0x0 0x1b000000 0x0 0x8000>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0xac 0x4>,
				     <0x0 0xad 0x4>;
			port-id = <1>;
			dma-coherent;
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "sgmii";
			phy-handle = <&sgenet1phy>;
		};

		xgenet: ethernet@1f610000 {
			compatible = "apm,xgene1-xgenet";
			status = "disabled";
			reg = <0x0 0x1f610000 0x0 0xd100>,
			      <0x0 0x1f600000 0x0 0xc300>,
			      <0x0 0x18000000 0x0 0x200>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0x60 0x4>,
				     <0x0 0x61 0x4>,
				     <0x0 0x62 0x4>,
				     <0x0 0x63 0x4>,
				     <0x0 0x64 0x4>,
				     <0x0 0x65 0x4>,
				     <0x0 0x66 0x4>,
				     <0x0 0x67 0x4>;
			channel = <0>;
			dma-coherent;
			clocks = <&xge0clk 0>;
			/* mac address will be overwritten by the bootloader */
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "xgmii";
		};

		xgenet1: ethernet@1f620000 {
			compatible = "apm,xgene1-xgenet";
			status = "disabled";
			reg = <0x0 0x1f620000 0x0 0xd100>,
			      <0x0 0x1f600000 0x0 0xc300>,
			      <0x0 0x18000000 0x0 0x8000>;
			reg-names = "enet_csr", "ring_csr", "ring_cmd";
			interrupts = <0x0 0x6c 0x4>,
				     <0x0 0x6d 0x4>;
			port-id = <1>;
			dma-coherent;
			clocks = <&xge1clk 0>;
			/* mac address will be overwritten by the bootloader */
			local-mac-address = [00 00 00 00 00 00];
			phy-connection-type = "xgmii";
		};

		rng: rng@10520000 {
			compatible = "apm,xgene-rng";
			reg = <0x0 0x10520000 0x0 0x100>;
			interrupts = <0x0 0x41 0x4>;
			clocks = <&rngpkaclk 0>;
		};

		dma: dma@1f270000 {
			compatible = "apm,xgene-storm-dma";
			device_type = "dma";
			reg = <0x0 0x1f270000 0x0 0x10000>,
			      <0x0 0x1f200000 0x0 0x10000>,
			      <0x0 0x1b000000 0x0 0x400000>,
			      <0x0 0x1054a000 0x0 0x100>;
			interrupts = <0x0 0x82 0x4>,
				     <0x0 0xb8 0x4>,
				     <0x0 0xb9 0x4>,
				     <0x0 0xba 0x4>,
				     <0x0 0xbb 0x4>;
			dma-coherent;
			clocks = <&dmaclk 0>;
		};
	};
};

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_APPLE) += t8103-j274.dtb
dtb-$(CONFIG_ARCH_APPLE) += t8103-j293.dtb
dtb-$(CONFIG_ARCH_APPLE) += t8103-j313.dtb
dtb-$(CONFIG_ARCH_APPLE) += t8103-j456.dtb
dtb-$(CONFIG_ARCH_APPLE) += t8103-j457.dtb
dtb-$(CONFIG_ARCH_APPLE) += t6000-j314s.dtb
dtb-$(CONFIG_ARCH_APPLE) += t6001-j314c.dtb
dtb-$(CONFIG_ARCH_APPLE) += t6000-j316s.dtb
dtb-$(CONFIG_ARCH_APPLE) += t6001-j316c.dtb
dtb-$(CONFIG_ARCH_APPLE) += t6001-j375c.dtb
dtb-$(CONFIG_ARCH_APPLE) += t6002-j375d.dtb


code:
/* SPDX-License-Identifier: GPL-2.0+ OR MIT
 *
 * C preprocessor macros for t600x multi die support.
 */

#ifndef __DTS_APPLE_MULTI_DIE_CPP_H
#define __DTS_APPLE_MULTI_DIE_CPP_H

#ifndef __stringify
#define __stringify_1(x...)     #x
#define __stringify(x...)       __stringify_1(x)
#endif

#ifndef __concat
#define __concat_1(x, y...)     x ## y
#define __concat(x, y...)       __concat_1(x, y)
#endif

#define DIE_NODE(a) __concat(a, DIE)
#define DIE_LABEL(a) __stringify(__concat(a, DIE))

#endif /* !__DTS_APPLE_MULTI_DIE_CPP_H */


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * MacBook Pro (14-inch, M1 Pro, 2021)
 *
 * target-type: J314s
 *
 * Copyright The Asahi Linux Contributors
 */

/dts-v1/;

#include "t6000.dtsi"
#include "t600x-j314-j316.dtsi"

/ {
	compatible = "apple,j314s", "apple,t6000", "apple,arm-platform";
	model = "Apple MacBook Pro (14-inch, M1 Pro, 2021)";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * MacBook Pro (16-inch, M1 Pro, 2021)
 *
 * target-type: J316s
 *
 * Copyright The Asahi Linux Contributors
 */

/dts-v1/;

#include "t6000.dtsi"
#include "t600x-j314-j316.dtsi"

/ {
	compatible = "apple,j316s", "apple,t6000", "apple,arm-platform";
	model = "Apple MacBook Pro (16-inch, M1 Pro, 2021)";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Apple T6000 "M1 Pro" SoC
 *
 * Other names: H13J, "Jade Chop"
 *
 * Copyright The Asahi Linux Contributors
 */

/* This chip is just a cut down version of t6001, so include it and disable the missing parts */

#include "t6001.dtsi"

/ {
	compatible = "apple,t6000", "apple,arm-platform";
};

/delete-node/ &pmgr_south;


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * MacBook Pro (14-inch, M1 Max, 2021)
 *
 * target-type: J314c
 *
 * Copyright The Asahi Linux Contributors
 */

/dts-v1/;

#include "t6001.dtsi"
#include "t600x-j314-j316.dtsi"

/ {
	compatible = "apple,j314c", "apple,t6001", "apple,arm-platform";
	model = "Apple MacBook Pro (14-inch, M1 Max, 2021)";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * MacBook Pro (16-inch, M1 Max, 2021)
 *
 * target-type: J316c
 *
 * Copyright The Asahi Linux Contributors
 */

/dts-v1/;

#include "t6001.dtsi"
#include "t600x-j314-j316.dtsi"

/ {
	compatible = "apple,j316c", "apple,t6001", "apple,arm-platform";
	model = "Apple MacBook Pro (16-inch, M1 Max, 2021)";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Mac Studio (M1 Max, 2022)
 *
 * target-type: J375c
 *
 * Copyright The Asahi Linux Contributors
 */

/dts-v1/;

#include "t6001.dtsi"
#include "t600x-j375.dtsi"

/ {
	compatible = "apple,j375c", "apple,t6001", "apple,arm-platform";
	model = "Apple Mac Studio (M1 Max, 2022)";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Apple T6001 "M1 Max" SoC
 *
 * Other names: H13J, "Jade"
 *
 * Copyright The Asahi Linux Contributors
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>

#include "multi-die-cpp.h"

#include "t600x-common.dtsi"

/ {
	compatible = "apple,t6001", "apple,arm-platform";

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;

		ranges;
		nonposted-mmio;

		// filled via templated includes at the end of the file
	};
};

#define DIE
#define DIE_NO 0

&{/soc} {
	#include "t600x-die0.dtsi"
	#include "t600x-dieX.dtsi"
	#include "t600x-nvme.dtsi"
};

#include "t600x-gpio-pins.dtsi"
#include "t600x-pmgr.dtsi"

#undef DIE
#undef DIE_NO

&aic {
	affinities {
		e-core-pmu-affinity {
			apple,fiq-index = <AIC_CPU_PMU_E>;
			cpus = <&cpu_e00 &cpu_e01>;
		};

		p-core-pmu-affinity {
			apple,fiq-index = <AIC_CPU_PMU_P>;
			cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03
				&cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Mac Studio (M1 Ultra, 2022)
 *
 * target-type: J375d
 *
 * Copyright The Asahi Linux Contributors
 */

/dts-v1/;

#include "t6002.dtsi"
#include "t600x-j375.dtsi"

/ {
	compatible = "apple,j375d", "apple,t6002", "apple,arm-platform";
	model = "Apple Mac Studio (M1 Ultra, 2022)";
};

/* USB Type C */
&i2c0 {
	/* front-right */
	hpm4: usb-pd@39 {
		compatible = "apple,cd321x";
		reg = <0x39>;
		interrupt-parent = <&pinctrl_ap>;
		interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "irq";
	};

	/* front-left */
	hpm5: usb-pd@3a {
		compatible = "apple,cd321x";
		reg = <0x3a>;
		interrupt-parent = <&pinctrl_ap>;
		interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "irq";
	};
};

/* delete unused always-on power-domains on die 1 */

/delete-node/ &ps_atc2_usb_aon_die1;
/delete-node/ &ps_atc2_usb_die1;

/delete-node/ &ps_atc3_usb_aon_die1;
/delete-node/ &ps_atc3_usb_die1;

/delete-node/ &ps_disp0_cpu0_die1;
/delete-node/ &ps_disp0_fe_die1;


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Apple T6002 "M1 Ultra" SoC
 *
 * Other names: H13J, "Jade 2C"
 *
 * Copyright The Asahi Linux Contributors
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/apple.h>

#include "multi-die-cpp.h"

#include "t600x-common.dtsi"

/ {
	compatible = "apple,t6002", "apple,arm-platform";

	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		cpu-map {
			cluster3 {
				core0 {
					cpu = <&cpu_e10>;
				};
				core1 {
					cpu = <&cpu_e11>;
				};
			};

			cluster4 {
				core0 {
					cpu = <&cpu_p20>;
				};
				core1 {
					cpu = <&cpu_p21>;
				};
				core2 {
					cpu = <&cpu_p22>;
				};
				core3 {
					cpu = <&cpu_p23>;
				};
			};

			cluster5 {
				core0 {
					cpu = <&cpu_p30>;
				};
				core1 {
					cpu = <&cpu_p31>;
				};
				core2 {
					cpu = <&cpu_p32>;
				};
				core3 {
					cpu = <&cpu_p33>;
				};
			};
		};

		cpu_e10: cpu@800 {
			compatible = "apple,icestorm";
			device_type = "cpu";
			reg = <0x0 0x800>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_3>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
			operating-points-v2 = <&icestorm_opp>;
			capacity-dmips-mhz = <714>;
			performance-domains = <&cpufreq_e_die1>;
		};

		cpu_e11: cpu@801 {
			compatible = "apple,icestorm";
			device_type = "cpu";
			reg = <0x0 0x801>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_3>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
			operating-points-v2 = <&icestorm_opp>;
			capacity-dmips-mhz = <714>;
			performance-domains = <&cpufreq_e_die1>;
		};

		cpu_p20: cpu@10900 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10900>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_4>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p0_die1>;
		};

		cpu_p21: cpu@10901 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10901>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_4>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p0_die1>;
		};

		cpu_p22: cpu@10902 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10902>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_4>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p0_die1>;
		};

		cpu_p23: cpu@10903 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10903>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_4>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p0_die1>;
		};

		cpu_p30: cpu@10a00 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10a00>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_5>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p1_die1>;
		};

		cpu_p31: cpu@10a01 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10a01>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_5>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p1_die1>;
		};

		cpu_p32: cpu@10a02 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10a02>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_5>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p1_die1>;
		};

		cpu_p33: cpu@10a03 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10a03>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_5>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p1_die1>;
		};

		l2_cache_3: l2-cache-3 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x400000>;
		};

		l2_cache_4: l2-cache-4 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0xc00000>;
		};

		l2_cache_5: l2-cache-5 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0xc00000>;
		};
	};

	die0: soc@200000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x2 0x0 0x2 0x0 0x4 0x0>,
			 <0x5 0x80000000 0x5 0x80000000 0x1 0x80000000>,
			 <0x7 0x0 0x7 0x0 0xf 0x80000000>;
		nonposted-mmio;

		// filled via templated includes at the end of the file
	};

	die1: soc@2200000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x2 0x0 0x22 0x0 0x4 0x0>,
			 <0x7 0x0 0x27 0x0 0xf 0x80000000>;
		nonposted-mmio;

		// filled via templated includes at the end of the file
	};
};

#define DIE
#define DIE_NO 0

&die0 {
	#include "t600x-die0.dtsi"
	#include "t600x-dieX.dtsi"
};

#include "t600x-pmgr.dtsi"
#include "t600x-gpio-pins.dtsi"

#undef DIE
#undef DIE_NO

#define DIE _die1
#define DIE_NO 1

&die1 {
	#include "t600x-dieX.dtsi"
	#include "t600x-nvme.dtsi"
};

#include "t600x-pmgr.dtsi"

#undef DIE
#undef DIE_NO

&aic {
	affinities {
		e-core-pmu-affinity {
			apple,fiq-index = <AIC_CPU_PMU_E>;
			cpus = <&cpu_e00 &cpu_e01
				&cpu_e10 &cpu_e11>;
		};

		p-core-pmu-affinity {
			apple,fiq-index = <AIC_CPU_PMU_P>;
			cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03
				&cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13
				&cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23
				&cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>;
		};
	};
};

&ps_gfx {
	// On t6002, the die0 GPU power domain needs both AFR power domains
	power-domains = <&ps_afr>, <&ps_afr_die1>;
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Common Apple T6000 / T6001 / T6002 "M1 Pro/Max/Ultra" SoC
 *
 * Other names: H13J, "Jade Chop", "Jade", "Jade 2C"
 *
 * Copyright The Asahi Linux Contributors
 */

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu_e00>;
				};
				core1 {
					cpu = <&cpu_e01>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu_p00>;
				};
				core1 {
					cpu = <&cpu_p01>;
				};
				core2 {
					cpu = <&cpu_p02>;
				};
				core3 {
					cpu = <&cpu_p03>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&cpu_p10>;
				};
				core1 {
					cpu = <&cpu_p11>;
				};
				core2 {
					cpu = <&cpu_p12>;
				};
				core3 {
					cpu = <&cpu_p13>;
				};
			};
		};

		cpu_e00: cpu@0 {
			compatible = "apple,icestorm";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_0>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
			operating-points-v2 = <&icestorm_opp>;
			capacity-dmips-mhz = <714>;
			performance-domains = <&cpufreq_e>;
		};

		cpu_e01: cpu@1 {
			compatible = "apple,icestorm";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_0>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
			operating-points-v2 = <&icestorm_opp>;
			capacity-dmips-mhz = <714>;
			performance-domains = <&cpufreq_e>;
		};

		cpu_p00: cpu@10100 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10100>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p0>;
		};

		cpu_p01: cpu@10101 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10101>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p0>;
		};

		cpu_p02: cpu@10102 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10102>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p0>;
		};

		cpu_p03: cpu@10103 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10103>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p0>;
		};

		cpu_p10: cpu@10200 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10200>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_2>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p1>;
		};

		cpu_p11: cpu@10201 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10201>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_2>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p1>;
		};

		cpu_p12: cpu@10202 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10202>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_2>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p1>;
		};

		cpu_p13: cpu@10203 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10203>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_2>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p1>;
		};

		l2_cache_0: l2-cache-0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x400000>;
		};

		l2_cache_1: l2-cache-1 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0xc00000>;
		};

		l2_cache_2: l2-cache-2 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0xc00000>;
		};
	};

	icestorm_opp: opp-table-0 {
		compatible = "operating-points-v2";

		opp01 {
			opp-hz = /bits/ 64 <600000000>;
			opp-level = <1>;
			clock-latency-ns = <7500>;
		};
		opp02 {
			opp-hz = /bits/ 64 <972000000>;
			opp-level = <2>;
			clock-latency-ns = <23000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <1332000000>;
			opp-level = <3>;
			clock-latency-ns = <29000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1704000000>;
			opp-level = <4>;
			clock-latency-ns = <40000>;
		};
		opp05 {
			opp-hz = /bits/ 64 <2064000000>;
			opp-level = <5>;
			clock-latency-ns = <50000>;
		};
	};

	firestorm_opp: opp-table-1 {
		compatible = "operating-points-v2";

		opp01 {
			opp-hz = /bits/ 64 <600000000>;
			opp-level = <1>;
			clock-latency-ns = <8000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <828000000>;
			opp-level = <2>;
			clock-latency-ns = <18000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <1056000000>;
			opp-level = <3>;
			clock-latency-ns = <19000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1296000000>;
			opp-level = <4>;
			clock-latency-ns = <23000>;
		};
		opp05 {
			opp-hz = /bits/ 64 <1524000000>;
			opp-level = <5>;
			clock-latency-ns = <24000>;
		};
		opp06 {
			opp-hz = /bits/ 64 <1752000000>;
			opp-level = <6>;
			clock-latency-ns = <28000>;
		};
		opp07 {
			opp-hz = /bits/ 64 <1980000000>;
			opp-level = <7>;
			clock-latency-ns = <31000>;
		};
		opp08 {
			opp-hz = /bits/ 64 <2208000000>;
			opp-level = <8>;
			clock-latency-ns = <45000>;
		};
		opp09 {
			opp-hz = /bits/ 64 <2448000000>;
			opp-level = <9>;
			clock-latency-ns = <49000>;
		};
		opp10 {
			opp-hz = /bits/ 64 <2676000000>;
			opp-level = <10>;
			clock-latency-ns = <53000>;
		};
		opp11 {
			opp-hz = /bits/ 64 <2904000000>;
			opp-level = <11>;
			clock-latency-ns = <56000>;
		};
		opp12 {
			opp-hz = /bits/ 64 <3036000000>;
			opp-level = <12>;
			clock-latency-ns = <56000>;
		};
		/* Not available until CPU deep sleep is implemented
		opp13 {
			opp-hz = /bits/ 64 <3132000000>;
			opp-level = <13>;
			clock-latency-ns = <56000>;
			turbo-mode;
		};
		opp14 {
			opp-hz = /bits/ 64 <3168000000>;
			opp-level = <14>;
			clock-latency-ns = <56000>;
			turbo-mode;
		};
		opp15 {
			opp-hz = /bits/ 64 <3228000000>;
			opp-level = <15>;
			clock-latency-ns = <56000>;
			turbo-mode;
		};
		*/
	};

	pmu-e {
		compatible = "apple,icestorm-pmu";
		interrupt-parent = <&aic>;
		interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
	};

	pmu-p {
		compatible = "apple,firestorm-pmu";
		interrupt-parent = <&aic>;
		interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&aic>;
		interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
		interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
	};

	clkref: clock-ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "clkref";
	};

	/*
	 * This is a fabulated representation of the input clock
	 * to NCO since we don't know the true clock tree.
	 */
	nco_clkref: clock-ref-nco {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "nco_ref";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Devices used on die 0 on the Apple T6002 "M1 Ultra" SoC and present on
 * Apple T6000 / T6001 "M1 Pro" / "M1 Max".
 *
 * Copyright The Asahi Linux Contributors
 */

	nco: clock-controller@28e03c000 {
		compatible = "apple,t6000-nco", "apple,nco";
		reg = <0x2 0x8e03c000 0x0 0x14000>;
		clocks = <&nco_clkref>;
		#clock-cells = <1>;
	};

	aic: interrupt-controller@28e100000 {
		compatible = "apple,t6000-aic", "apple,aic2";
		#interrupt-cells = <4>;
		interrupt-controller;
		reg = <0x2 0x8e100000 0x0 0xc000>,
			<0x2 0x8e10c000 0x0 0x4>;
		reg-names = "core", "event";
		power-domains = <&ps_aic>;
	};

	pinctrl_smc: pinctrl@290820000 {
		compatible = "apple,t6000-pinctrl", "apple,pinctrl";
		reg = <0x2 0x90820000 0x0 0x4000>;

		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&pinctrl_smc 0 0 30>;
		apple,npins = <30>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 743 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ 0 744 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ 0 745 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ 0 746 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ 0 747 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ 0 748 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ 0 749 IRQ_TYPE_LEVEL_HIGH>;
	};

	wdt: watchdog@2922b0000 {
		compatible = "apple,t6000-wdt", "apple,wdt";
		reg = <0x2 0x922b0000 0x0 0x4000>;
		clocks = <&clkref>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 631 IRQ_TYPE_LEVEL_HIGH>;
	};

	sio_dart_0: iommu@39b004000 {
		compatible = "apple,t6000-dart";
		reg = <0x3 0x9b004000 0x0 0x4000>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1130 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		power-domains = <&ps_sio_cpu>;
	};

	sio_dart_1: iommu@39b008000 {
		compatible = "apple,t6000-dart";
		reg = <0x3 0x9b008000 0x0 0x8000>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1130 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		power-domains = <&ps_sio_cpu>;
	};

	i2c0: i2c@39b040000 {
		compatible = "apple,t6000-i2c", "apple,i2c";
		reg = <0x3 0x9b040000 0x0 0x4000>;
		clocks = <&clkref>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1119 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-0 = <&i2c0_pins>;
		pinctrl-names = "default";
		power-domains = <&ps_i2c0>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
	};

	i2c1: i2c@39b044000 {
		compatible = "apple,t6000-i2c", "apple,i2c";
		reg = <0x3 0x9b044000 0x0 0x4000>;
		clocks = <&clkref>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1120 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-0 = <&i2c1_pins>;
		pinctrl-names = "default";
		power-domains = <&ps_i2c1>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		status = "disabled";
	};

	i2c2: i2c@39b048000 {
		compatible = "apple,t6000-i2c", "apple,i2c";
		reg = <0x3 0x9b048000 0x0 0x4000>;
		clocks = <&clkref>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1121 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-0 = <&i2c2_pins>;
		pinctrl-names = "default";
		power-domains = <&ps_i2c2>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		status = "disabled";
	};

	i2c3: i2c@39b04c000 {
		compatible = "apple,t6000-i2c", "apple,i2c";
		reg = <0x3 0x9b04c000 0x0 0x4000>;
		clocks = <&clkref>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1122 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-0 = <&i2c3_pins>;
		pinctrl-names = "default";
		power-domains = <&ps_i2c3>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		status = "disabled";
	};

	i2c4: i2c@39b050000 {
		compatible = "apple,t6000-i2c", "apple,i2c";
		reg = <0x3 0x9b050000 0x0 0x4000>;
		clocks = <&clkref>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1123 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-0 = <&i2c4_pins>;
		pinctrl-names = "default";
		power-domains = <&ps_i2c4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		status = "disabled";
	};

	i2c5: i2c@39b054000 {
		compatible = "apple,t6000-i2c", "apple,i2c";
		reg = <0x3 0x9b054000 0x0 0x4000>;
		clocks = <&clkref>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1124 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-0 = <&i2c5_pins>;
		pinctrl-names = "default";
		power-domains = <&ps_i2c5>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		status = "disabled";
	};

	serial0: serial@39b200000 {
		compatible = "apple,s5l-uart";
		reg = <0x3 0x9b200000 0x0 0x1000>;
		reg-io-width = <4>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1097 IRQ_TYPE_LEVEL_HIGH>;
		/*
		 * TODO: figure out the clocking properly, there may
		 * be a third selectable clock.
		 */
		clocks = <&clkref>, <&clkref>;
		clock-names = "uart", "clk_uart_baud0";
		power-domains = <&ps_uart0>;
		status = "disabled";
	};

	admac: dma-controller@39b400000 {
		compatible = "apple,t6000-admac", "apple,admac";
		reg = <0x3 0x9b400000 0x0 0x34000>;
		#dma-cells = <1>;
		dma-channels = <16>;
		interrupts-extended = <0>,
				      <&aic AIC_IRQ 0 1118 IRQ_TYPE_LEVEL_HIGH>,
				      <0>,
				      <0>;
		iommus = <&sio_dart_0 2>, <&sio_dart_1 2>;
		power-domains = <&ps_sio_adma>;
		resets = <&ps_audio_p>;
	};

	mca: mca@39b600000 {
		compatible = "apple,t6000-mca", "apple,mca";
		reg = <0x3 0x9b600000 0x0 0x10000>,
		      <0x3 0x9b500000 0x0 0x20000>;
		clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>;
		dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>,
		       <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>,
		       <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>,
		       <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>;
		dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
			    "tx1a", "rx1a", "tx1b", "rx1b",
			    "tx2a", "rx2a", "tx2b", "rx2b",
			    "tx3a", "rx3a", "tx3b", "rx3b";
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1112 IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_IRQ 0 1113 IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_IRQ 0 1114 IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_IRQ 0 1115 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
				<&ps_mca2>, <&ps_mca3>;
		resets = <&ps_audio_p>;
		#sound-dai-cells = <1>;
	};

	pcie0_dart_0: iommu@581008000 {
		compatible = "apple,t6000-dart";
		reg = <0x5 0x81008000 0x0 0x4000>;
		#iommu-cells = <1>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1271 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&ps_apcie_gp_sys>;
	};

	pcie0_dart_1: iommu@582008000 {
		compatible = "apple,t6000-dart";
		reg = <0x5 0x82008000 0x0 0x4000>;
		#iommu-cells = <1>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1274 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&ps_apcie_gp_sys>;
	};

	pcie0_dart_2: iommu@583008000 {
		compatible = "apple,t6000-dart";
		reg = <0x5 0x83008000 0x0 0x4000>;
		#iommu-cells = <1>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1277 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&ps_apcie_gp_sys>;
	};

	pcie0_dart_3: iommu@584008000 {
		compatible = "apple,t6000-dart";
		reg = <0x5 0x84008000 0x0 0x4000>;
		#iommu-cells = <1>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1280 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&ps_apcie_gp_sys>;
	};

	pcie0: pcie@590000000 {
		compatible = "apple,t6000-pcie", "apple,pcie";
		device_type = "pci";

		reg = <0x5 0x90000000 0x0 0x1000000>,
			<0x5 0x80000000 0x0 0x100000>,
			<0x5 0x81000000 0x0 0x4000>,
			<0x5 0x82000000 0x0 0x4000>,
			<0x5 0x83000000 0x0 0x4000>,
			<0x5 0x84000000 0x0 0x4000>;
		reg-names = "config", "rc", "port0", "port1", "port2", "port3";

		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ 0 1270 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ 0 1273 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ 0 1276 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ 0 1279 IRQ_TYPE_LEVEL_HIGH>;

		msi-controller;
		msi-parent = <&pcie0>;
		msi-ranges = <&aic AIC_IRQ 0 1581 IRQ_TYPE_EDGE_RISING 32>;

		iommu-map = <0x100 &pcie0_dart_0 1 1>,
				<0x200 &pcie0_dart_1 1 1>,
				<0x300 &pcie0_dart_2 1 1>,
				<0x400 &pcie0_dart_3 1 1>;
		iommu-map-mask = <0xff00>;

		bus-range = <0 4>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>,
				<0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>;

		power-domains = <&ps_apcie_gp_sys>;
		pinctrl-0 = <&pcie_pins>;
		pinctrl-names = "default";

		port00: pci@0,0 {
			device_type = "pci";
			reg = <0x0 0x0 0x0 0x0 0x0>;
			reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>;

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
					<0 0 0 2 &port00 0 0 0 1>,
					<0 0 0 3 &port00 0 0 0 2>,
					<0 0 0 4 &port00 0 0 0 3>;
		};

		port01: pci@1,0 {
			device_type = "pci";
			reg = <0x800 0x0 0x0 0x0 0x0>;
			reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>;

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
					<0 0 0 2 &port01 0 0 0 1>,
					<0 0 0 3 &port01 0 0 0 2>,
					<0 0 0 4 &port01 0 0 0 3>;
		};

		port02: pci@2,0 {
			device_type = "pci";
			reg = <0x1000 0x0 0x0 0x0 0x0>;
			reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>;

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
					<0 0 0 2 &port02 0 0 0 1>,
					<0 0 0 3 &port02 0 0 0 2>,
					<0 0 0 4 &port02 0 0 0 3>;
		};

		port03: pci@3,0 {
			device_type = "pci";
			reg = <0x1800 0x0 0x0 0x0 0x0>;
			reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>;

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &port03 0 0 0 0>,
					<0 0 0 2 &port03 0 0 0 1>,
					<0 0 0 3 &port03 0 0 0 2>,
					<0 0 0 4 &port03 0 0 0 3>;
		};
	};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Devices used on both dies on the Apple T6002 "M1 Ultra" and present on
 * Apple T6000/T6001 "M1 Pro/Max".
 *
 * Copyright The Asahi Linux Contributors
 */

	DIE_NODE(cpufreq_e): cpufreq@210e20000 {
		compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
		reg = <0x2 0x10e20000 0 0x1000>;
		#performance-domain-cells = <0>;
	};

	DIE_NODE(cpufreq_p0): cpufreq@211e20000 {
		compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
		reg = <0x2 0x11e20000 0 0x1000>;
		#performance-domain-cells = <0>;
	};

	DIE_NODE(cpufreq_p1): cpufreq@212e20000 {
		compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
		reg = <0x2 0x12e20000 0 0x1000>;
		#performance-domain-cells = <0>;
	};

	DIE_NODE(pmgr): power-management@28e080000 {
		compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x2 0x8e080000 0 0x4000>;
	};

	DIE_NODE(pmgr_east): power-management@28e580000 {
		compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x2 0x8e580000 0 0xc000>;
	};

	DIE_NODE(pmgr_south): power-management@28e680000 {
		compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x2 0x8e680000 0 0xc000>;
	};

	DIE_NODE(pinctrl_nub): pinctrl@2921f0000 {
		compatible = "apple,t6000-pinctrl", "apple,pinctrl";
		reg = <0x2 0x921f0000 0x0 0x4000>;
		power-domains = <&DIE_NODE(ps_nub_gpio)>;

		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&DIE_NODE(pinctrl_nub) 0 0 16>;
		apple,npins = <16>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ DIE_NO 623 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 624 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 625 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 626 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 627 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 628 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 629 IRQ_TYPE_LEVEL_HIGH>;
	};

	DIE_NODE(pmgr_mini): power-management@292280000 {
		compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x2 0x92280000 0 0x4000>;
	};

	DIE_NODE(pinctrl_aop): pinctrl@293820000 {
		compatible = "apple,t6000-pinctrl", "apple,pinctrl";
		reg = <0x2 0x93820000 0x0 0x4000>;

		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&DIE_NODE(pinctrl_aop) 0 0 63>;
		apple,npins = <63>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ DIE_NO 567 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 568 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 569 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 570 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 571 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 572 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 573 IRQ_TYPE_LEVEL_HIGH>;
	};

	DIE_NODE(pinctrl_ap): pinctrl@39b028000 {
		compatible = "apple,t6000-pinctrl", "apple,pinctrl";
		reg = <0x3 0x9b028000 0x0 0x4000>;

		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ DIE_NO 427 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 428 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 429 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 430 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 431 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 432 IRQ_TYPE_LEVEL_HIGH>,
				<AIC_IRQ DIE_NO 433 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clkref>;
		power-domains = <&DIE_NODE(ps_gpio)>;

		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&DIE_NODE(pinctrl_ap) 0 0 255>;
		apple,npins = <255>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * GPIO pin mappings for Apple T600x SoCs.
 *
 * Copyright The Asahi Linux Contributors
 */

&pinctrl_ap {
	i2c0_pins: i2c0-pins {
		pinmux = <APPLE_PINMUX(92, 1)>,
			<APPLE_PINMUX(93, 1)>;
	};

	i2c1_pins: i2c1-pins {
		pinmux = <APPLE_PINMUX(94, 1)>,
			<APPLE_PINMUX(95, 1)>;
	};

	i2c2_pins: i2c2-pins {
		pinmux = <APPLE_PINMUX(96, 1)>,
			<APPLE_PINMUX(97, 1)>;
	};

	i2c3_pins: i2c3-pins {
		pinmux = <APPLE_PINMUX(98, 1)>,
			<APPLE_PINMUX(99, 1)>;
	};

	i2c4_pins: i2c4-pins {
		pinmux = <APPLE_PINMUX(8, 1)>,
			<APPLE_PINMUX(9, 1)>;
	};

	i2c5_pins: i2c5-pins {
		pinmux = <APPLE_PINMUX(100, 1)>,
			<APPLE_PINMUX(101, 1)>;
	};

	pcie_pins: pcie-pins {
		pinmux = <APPLE_PINMUX(0, 1)>,
				<APPLE_PINMUX(1, 1)>,
				<APPLE_PINMUX(2, 1)>,
				<APPLE_PINMUX(3, 1)>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * MacBook Pro (14/16-inch, 2021)
 *
 * This file contains the parts common to J314 and J316 devices with both t6000 and t6001.
 *
 * target-type: J314s / J314c / J316s / J316c
 *
 * Copyright The Asahi Linux Contributors
 */

/ {
	aliases {
		serial0 = &serial0;
		wifi0 = &wifi0;
	};

	chosen {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		stdout-path = "serial0";

		framebuffer0: framebuffer@0 {
			compatible = "apple,simple-framebuffer", "simple-framebuffer";
			reg = <0 0 0 0>; /* To be filled by loader */
			/* Format properties will be added by loader */
			status = "disabled";
		};
	};

	memory@10000000000 {
		device_type = "memory";
		reg = <0x100 0 0x2 0>; /* To be filled by loader */
	};
};

&serial0 {
	status = "okay";
};

/* USB Type C */
&i2c0 {
	hpm0: usb-pd@38 {
		compatible = "apple,cd321x";
		reg = <0x38>;
		interrupt-parent = <&pinctrl_ap>;
		interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "irq";
	};

	hpm1: usb-pd@3f {
		compatible = "apple,cd321x";
		reg = <0x3f>;
		interrupt-parent = <&pinctrl_ap>;
		interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "irq";
	};

	hpm2: usb-pd@3b {
		compatible = "apple,cd321x";
		reg = <0x3b>;
		interrupt-parent = <&pinctrl_ap>;
		interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "irq";
	};

	/* MagSafe port */
	hpm5: usb-pd@3a {
		compatible = "apple,cd321x";
		reg = <0x3a>;
		interrupt-parent = <&pinctrl_ap>;
		interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "irq";
	};
};

&nco_clkref {
	clock-frequency = <1068000000>;
};

/* PCIe devices */
&port00 {
	/* WLAN */
	bus-range = <1 1>;
	wifi0: wifi@0,0 {
		reg = <0x10000 0x0 0x0 0x0 0x0>;
		/* To be filled by the loader */
		local-mac-address = [00 10 18 00 00 10];
	};
};

&port01 {
	/* SD card reader */
	bus-range = <2 2>;
	sdhci0: mmc@0,0 {
		compatible = "pci17a0,9755";
		reg = <0x20000 0x0 0x0 0x0 0x0>;
		cd-inverted;
		wp-inverted;
	};
};

&pcie0_dart_2 {
	status = "disabled";
};

&pcie0_dart_3 {
	status = "disabled";
};

/delete-node/ &port02;
/delete-node/ &port03;


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Mac Studio (2022)
 *
 * This file contains the parts common to J375 devices with both t6001 and t6002.
 *
 * target-type: J375c / J375d
 *
 * Copyright The Asahi Linux Contributors
 */

/ {
	aliases {
		serial0 = &serial0;
		wifi0 = &wifi0;
	};

	chosen {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		stdout-path = "serial0";

		framebuffer0: framebuffer@0 {
			compatible = "apple,simple-framebuffer", "simple-framebuffer";
			reg = <0 0 0 0>; /* To be filled by loader */
			/* Format properties will be added by loader */
			status = "disabled";
		};
	};

	memory@10000000000 {
		device_type = "memory";
		reg = <0x100 0 0x2 0>; /* To be filled by loader */
	};
};

&serial0 {
	status = "okay";
};

/* USB Type C */
&i2c0 {
	hpm0: usb-pd@38 {
		compatible = "apple,cd321x";
		reg = <0x38>;
		interrupt-parent = <&pinctrl_ap>;
		interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "irq";
	};

	hpm1: usb-pd@3f {
		compatible = "apple,cd321x";
		reg = <0x3f>;
		interrupt-parent = <&pinctrl_ap>;
		interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "irq";
	};

	hpm2: usb-pd@3b {
		compatible = "apple,cd321x";
		reg = <0x3b>;
		interrupt-parent = <&pinctrl_ap>;
		interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "irq";
	};

	hpm3: usb-pd@3c {
		compatible = "apple,cd321x";
		reg = <0x3c>;
		interrupt-parent = <&pinctrl_ap>;
		interrupts = <174 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "irq";
	};
};

&nco_clkref {
	clock-frequency = <1068000000>;
};

/* PCIe devices */
&port00 {
	/* WLAN */
	bus-range = <1 1>;
	wifi0: wifi@0,0 {
		reg = <0x10000 0x0 0x0 0x0 0x0>;
		/* To be filled by the loader */
		local-mac-address = [00 10 18 00 00 10];
	};
};

&port01 {
	/* SD card reader */
	bus-range = <2 2>;
	sdhci0: mmc@0,0 {
		compatible = "pci17a0,9755";
		reg = <0x20000 0x0 0x0 0x0 0x0>;
		cd-inverted;
		wp-inverted;
	};
};

&port02 {
	/* 10 Gbit Ethernet */
	bus-range = <3 3>;
	ethernet0: ethernet@0,0 {
		reg = <0x30000 0x0 0x0 0x0 0x0>;
		/* To be filled by the loader */
		local-mac-address = [00 10 18 00 00 00];
	};
};

&port03 {
	/* USB xHCI */
	bus-range = <4 4>;
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * NVMe related devices for Apple T600x SoCs.
 *
 * Copyright The Asahi Linux Contributors
 */

	DIE_NODE(ans_mbox): mbox@38f408000 {
		compatible = "apple,t6000-asc-mailbox", "apple,asc-mailbox-v4";
		reg = <0x3 0x8f408000 0x0 0x4000>;
		interrupt-parent = <&aic>;
		interrupts = <AIC_IRQ DIE_NO 1069 IRQ_TYPE_LEVEL_HIGH>,
			<AIC_IRQ DIE_NO 1070 IRQ_TYPE_LEVEL_HIGH>,
			<AIC_IRQ DIE_NO 1071 IRQ_TYPE_LEVEL_HIGH>,
			<AIC_IRQ DIE_NO 1072 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "send-empty", "send-not-empty",
			"recv-empty", "recv-not-empty";
		power-domains = <&DIE_NODE(ps_ans2)>;
		#mbox-cells = <0>;
	};

	DIE_NODE(sart): sart@393c50000 {
		compatible = "apple,t6000-sart";
		reg = <0x3 0x93c50000 0x0 0x10000>;
		power-domains = <&DIE_NODE(ps_ans2)>;
	};

	DIE_NODE(nvme): nvme@393cc0000 {
		compatible = "apple,t6000-nvme-ans2", "apple,nvme-ans2";
		reg = <0x3 0x93cc0000 0x0 0x40000>, <0x3 0x8f400000 0x0 0x4000>;
		reg-names = "nvme", "ans";
		interrupt-parent = <&aic>;
		/* The NVME interrupt is always routed to die */
		interrupts = <AIC_IRQ 0 1613 IRQ_TYPE_LEVEL_HIGH>;
		mboxes = <&DIE_NODE(ans_mbox)>;
		apple,sart = <&DIE_NODE(sart)>;
		power-domains = <&DIE_NODE(ps_ans2)>,
			<&DIE_NODE(ps_apcie_st_sys)>,
			<&DIE_NODE(ps_apcie_st1_sys)>;
		power-domain-names = "ans", "apcie0", "apcie1";
		resets = <&DIE_NODE(ps_ans2)>;
	};