code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm CAMSS ISP

maintainers:
  - Robert Foss <robert.foss@linaro.org>

description: |
  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.

properties:
  compatible:
    const: qcom,sm8250-camss

  clocks:
    minItems: 37
    maxItems: 37

  clock-names:
    items:
      - const: cam_ahb_clk
      - const: cam_hf_axi
      - const: cam_sf_axi
      - const: camnoc_axi
      - const: camnoc_axi_src
      - const: core_ahb
      - const: cpas_ahb
      - const: csiphy0
      - const: csiphy0_timer
      - const: csiphy1
      - const: csiphy1_timer
      - const: csiphy2
      - const: csiphy2_timer
      - const: csiphy3
      - const: csiphy3_timer
      - const: csiphy4
      - const: csiphy4_timer
      - const: csiphy5
      - const: csiphy5_timer
      - const: slow_ahb_src
      - const: vfe0_ahb
      - const: vfe0_axi
      - const: vfe0
      - const: vfe0_cphy_rx
      - const: vfe0_csid
      - const: vfe0_areg
      - const: vfe1_ahb
      - const: vfe1_axi
      - const: vfe1
      - const: vfe1_cphy_rx
      - const: vfe1_csid
      - const: vfe1_areg
      - const: vfe_lite_ahb
      - const: vfe_lite_axi
      - const: vfe_lite
      - const: vfe_lite_cphy_rx
      - const: vfe_lite_csid

  interrupts:
    minItems: 14
    maxItems: 14

  interrupt-names:
    items:
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: csiphy3
      - const: csiphy4
      - const: csiphy5
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csid3
      - const: vfe0
      - const: vfe1
      - const: vfe_lite0
      - const: vfe_lite1

  iommus:
    minItems: 8
    maxItems: 8

  interconnects:
    minItems: 4
    maxItems: 4

  interconnect-names:
    items:
      - const: cam_ahb
      - const: cam_hf_0_mnoc
      - const: cam_sf_0_mnoc
      - const: cam_sf_icp_mnoc

  power-domains:
    items:
      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    description:
      CSI input ports.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - clock-lanes
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - clock-lanes
              - data-lanes

      port@2:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - clock-lanes
              - data-lanes

      port@3:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - clock-lanes
              - data-lanes

      port@4:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - clock-lanes
              - data-lanes

      port@5:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - clock-lanes
              - data-lanes

  reg:
    minItems: 10
    maxItems: 10

  reg-names:
    items:
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: csiphy3
      - const: csiphy4
      - const: csiphy5
      - const: vfe0
      - const: vfe1
      - const: vfe_lite0
      - const: vfe_lite1

  vdda-phy-supply:
    description:
      Phandle to a regulator supply to PHY core block.

  vdda-pll-supply:
    description:
      Phandle to 1.8V regulator supply to PHY refclk pll block.

required:
  - clock-names
  - clocks
  - compatible
  - interconnects
  - interconnect-names
  - interrupts
  - interrupt-names
  - iommus
  - power-domains
  - reg
  - reg-names
  - vdda-phy-supply
  - vdda-pll-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,camcc-sm8250.h>
    #include <dt-bindings/interconnect/qcom,sm8250.h>
    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        camss: camss@ac6a000 {
            compatible = "qcom,sm8250-camss";

            reg = <0 0xac6a000 0 0x2000>,
                  <0 0xac6c000 0 0x2000>,
                  <0 0xac6e000 0 0x1000>,
                  <0 0xac70000 0 0x1000>,
                  <0 0xac72000 0 0x1000>,
                  <0 0xac74000 0 0x1000>,
                  <0 0xacb4000 0 0xd000>,
                  <0 0xacc3000 0 0xd000>,
                  <0 0xacd9000 0 0x2200>,
                  <0 0xacdb200 0 0x2200>;
            reg-names = "csiphy0",
                        "csiphy1",
                        "csiphy2",
                        "csiphy3",
                        "csiphy4",
                        "csiphy5",
                        "vfe0",
                        "vfe1",
                        "vfe_lite0",
                        "vfe_lite1";

            vdda-phy-supply = <&vreg_l5a_0p88>;
            vdda-pll-supply = <&vreg_l9a_1p2>;

            interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "csiphy0",
                              "csiphy1",
                              "csiphy2",
                              "csiphy3",
                              "csiphy4",
                              "csiphy5",
                              "csid0",
                              "csid1",
                              "csid2",
                              "csid3",
                              "vfe0",
                              "vfe1",
                              "vfe_lite0",
                              "vfe_lite1";

            power-domains = <&camcc IFE_0_GDSC>,
                            <&camcc IFE_1_GDSC>,
                            <&camcc TITAN_TOP_GDSC>;

            clocks = <&gcc GCC_CAMERA_AHB_CLK>,
                     <&gcc GCC_CAMERA_HF_AXI_CLK>,
                     <&gcc GCC_CAMERA_SF_AXI_CLK>,
                     <&camcc CAM_CC_CAMNOC_AXI_CLK>,
                     <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
                     <&camcc CAM_CC_CORE_AHB_CLK>,
                     <&camcc CAM_CC_CPAS_AHB_CLK>,
                     <&camcc CAM_CC_CSIPHY0_CLK>,
                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY1_CLK>,
                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY2_CLK>,
                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY3_CLK>,
                     <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY4_CLK>,
                     <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY5_CLK>,
                     <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
                     <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
                     <&camcc CAM_CC_IFE_0_AHB_CLK>,
                     <&camcc CAM_CC_IFE_0_AXI_CLK>,
                     <&camcc CAM_CC_IFE_0_CLK>,
                     <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
                     <&camcc CAM_CC_IFE_0_CSID_CLK>,
                     <&camcc CAM_CC_IFE_0_AREG_CLK>,
                     <&camcc CAM_CC_IFE_1_AHB_CLK>,
                     <&camcc CAM_CC_IFE_1_AXI_CLK>,
                     <&camcc CAM_CC_IFE_1_CLK>,
                     <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
                     <&camcc CAM_CC_IFE_1_CSID_CLK>,
                     <&camcc CAM_CC_IFE_1_AREG_CLK>,
                     <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
                     <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
                     <&camcc CAM_CC_IFE_LITE_CLK>,
                     <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
                     <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
            clock-names = "cam_ahb_clk",
                          "cam_hf_axi",
                          "cam_sf_axi",
                          "camnoc_axi",
                          "camnoc_axi_src",
                          "core_ahb",
                          "cpas_ahb",
                          "csiphy0",
                          "csiphy0_timer",
                          "csiphy1",
                          "csiphy1_timer",
                          "csiphy2",
                          "csiphy2_timer",
                          "csiphy3",
                          "csiphy3_timer",
                          "csiphy4",
                          "csiphy4_timer",
                          "csiphy5",
                          "csiphy5_timer",
                          "slow_ahb_src",
                          "vfe0_ahb",
                          "vfe0_axi",
                          "vfe0",
                          "vfe0_cphy_rx",
                          "vfe0_csid",
                          "vfe0_areg",
                          "vfe1_ahb",
                          "vfe1_axi",
                          "vfe1",
                          "vfe1_cphy_rx",
                          "vfe1_csid",
                          "vfe1_areg",
                          "vfe_lite_ahb",
                          "vfe_lite_axi",
                          "vfe_lite",
                          "vfe_lite_cphy_rx",
                          "vfe_lite_csid";

            iommus = <&apps_smmu 0x800 0x400>,
                     <&apps_smmu 0x801 0x400>,
                     <&apps_smmu 0x840 0x400>,
                     <&apps_smmu 0x841 0x400>,
                     <&apps_smmu 0xC00 0x400>,
                     <&apps_smmu 0xC01 0x400>,
                     <&apps_smmu 0xC40 0x400>,
                     <&apps_smmu 0xC41 0x400>;

            interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
                            <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
                            <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
                            <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
            interconnect-names = "cam_ahb",
                                 "cam_hf_0_mnoc",
                                 "cam_sf_0_mnoc",
                                 "cam_sf_icp_mnoc";

            ports {
                #address-cells = <1>;
                #size-cells = <0>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,sm8250-venus.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Venus video encode and decode accelerators

maintainers:
  - Stanimir Varbanov <stanimir.varbanov@linaro.org>

description: |
  The Venus IP is a video encode and decode accelerator present
  on Qualcomm platforms

properties:
  compatible:
    const: qcom,sm8250-venus

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    minItems: 2
    maxItems: 3

  power-domain-names:
    minItems: 2
    items:
      - const: venus
      - const: vcodec0
      - const: mx

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: iface
      - const: core
      - const: vcodec0_core

  iommus:
    maxItems: 1

  memory-region:
    maxItems: 1

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: cpu-cfg
      - const: video-mem

  resets:
    maxItems: 2

  reset-names:
    items:
      - const: bus
      - const: core

  video-decoder:
    type: object

    properties:
      compatible:
        const: venus-decoder

    required:
      - compatible

    additionalProperties: false

  video-encoder:
    type: object

    properties:
      compatible:
        const: venus-encoder

    required:
      - compatible

    additionalProperties: false

  video-firmware:
    type: object
    additionalProperties: false

    description: |
      Firmware subnode is needed when the platform does not
      have TrustZone.

    properties:
      iommus:
        maxItems: 1

    required:
      - iommus

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - power-domain-names
  - clocks
  - clock-names
  - interconnects
  - interconnect-names
  - iommus
  - memory-region
  - resets
  - reset-names
  - video-decoder
  - video-encoder

additionalProperties: false

examples:
  - |
        #include <dt-bindings/interrupt-controller/arm-gic.h>
        #include <dt-bindings/clock/qcom,videocc-sm8250.h>
        #include <dt-bindings/interconnect/qcom,sm8250.h>
        #include <dt-bindings/clock/qcom,gcc-sm8250.h>
        #include <dt-bindings/power/qcom-rpmpd.h>

        venus: video-codec@aa00000 {
            compatible = "qcom,sm8250-venus";
            reg = <0x0aa00000 0xff000>;
            interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
            power-domains = <&videocc MVS0C_GDSC>,
                            <&videocc MVS0_GDSC>,
                            <&rpmhpd SM8250_MX>;
            power-domain-names = "venus", "vcodec0", "mx";

            clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
                     <&videocc VIDEO_CC_MVS0C_CLK>,
                     <&videocc VIDEO_CC_MVS0_CLK>;
            clock-names = "iface", "core", "vcodec0_core";

            interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
                            <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
            interconnect-names = "cpu-cfg", "video-mem";

            iommus = <&apps_smmu 0x2100 0x0400>;
            memory-region = <&video_mem>;

            resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
                     <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
            reset-names = "bus", "core";

            video-decoder {
                compatible = "venus-decoder";
            };

            video-encoder {
                compatible = "venus-encoder";
            };
        };

repo_name: angery/linux


code: This file has been moved to rc.yaml.


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/rc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic Infrared Remote Controller

maintainers:
  - Mauro Carvalho Chehab <mchehab@kernel.org>
  - Sean Young <sean@mess.org>

properties:
  $nodename:
    pattern: "^ir(-receiver)?(@[a-f0-9]+)?$"

  linux,rc-map-name:
    description:
      Specifies the scancode/key mapping table defined in-kernel for
      the remote controller.
    $ref: '/schemas/types.yaml#/definitions/string'
    enum:
      - rc-adstech-dvb-t-pci
      - rc-alink-dtu-m
      - rc-anysee
      - rc-apac-viewcomp
      - rc-astrometa-t2hybrid
      - rc-asus-pc39
      - rc-asus-ps3-100
      - rc-ati-tv-wonder-hd-600
      - rc-ati-x10
      - rc-avermedia
      - rc-avermedia-a16d
      - rc-avermedia-cardbus
      - rc-avermedia-dvbt
      - rc-avermedia-m135a
      - rc-avermedia-m733a-rm-k6
      - rc-avermedia-rm-ks
      - rc-avertv-303
      - rc-azurewave-ad-tu700
      - rc-beelink-gs1
      - rc-behold
      - rc-behold-columbus
      - rc-budget-ci-old
      - rc-cec
      - rc-cinergy
      - rc-cinergy-1400
      - rc-ct-90405
      - rc-d680-dmb
      - rc-delock-61959
      - rc-dib0700-nec
      - rc-dib0700-rc5
      - rc-digitalnow-tinytwin
      - rc-digittrade
      - rc-dm1105-nec
      - rc-dntv-live-dvb-t
      - rc-dntv-live-dvbt-pro
      - rc-dtt200u
      - rc-dvbsky
      - rc-dvico-mce
      - rc-dvico-portable
      - rc-em-terratec
      - rc-empty
      - rc-encore-enltv
      - rc-encore-enltv-fm53
      - rc-encore-enltv2
      - rc-evga-indtube
      - rc-eztv
      - rc-flydvb
      - rc-flyvideo
      - rc-fusionhdtv-mce
      - rc-gadmei-rm008z
      - rc-geekbox
      - rc-genius-tvgo-a11mce
      - rc-gotview7135
      - rc-hauppauge
      - rc-hisi-poplar
      - rc-hisi-tv-demo
      - rc-imon-mce
      - rc-imon-pad
      - rc-imon-rsc
      - rc-iodata-bctv7e
      - rc-it913x-v1
      - rc-it913x-v2
      - rc-kaiomy
      - rc-khadas
      - rc-khamsin
      - rc-kworld-315u
      - rc-kworld-pc150u
      - rc-kworld-plus-tv-analog
      - rc-leadtek-y04g0051
      - rc-lme2510
      - rc-manli
      - rc-mecool-kii-pro
      - rc-mecool-kiii-pro
      - rc-medion-x10
      - rc-medion-x10-digitainer
      - rc-medion-x10-or2x
      - rc-minix-neo
      - rc-msi-digivox-ii
      - rc-msi-digivox-iii
      - rc-msi-tvanywhere
      - rc-msi-tvanywhere-plus
      - rc-nebula
      - rc-nec-terratec-cinergy-xs
      - rc-norwood
      - rc-npgtech
      - rc-odroid
      - rc-pctv-sedna
      - rc-pine64
      - rc-pinnacle-color
      - rc-pinnacle-grey
      - rc-pinnacle-pctv-hd
      - rc-pixelview
      - rc-pixelview-002t
      - rc-pixelview-mk12
      - rc-pixelview-new
      - rc-powercolor-real-angel
      - rc-proteus-2309
      - rc-purpletv
      - rc-pv951
      - rc-rc5-tv
      - rc-rc6-mce
      - rc-real-audio-220-32-keys
      - rc-reddo
      - rc-snapstream-firefly
      - rc-streamzap
      - rc-su3000
      - rc-tanix-tx3mini
      - rc-tanix-tx5max
      - rc-tbs-nec
      - rc-technisat-ts35
      - rc-technisat-usb2
      - rc-terratec-cinergy-c-pci
      - rc-terratec-cinergy-s2-hd
      - rc-terratec-cinergy-xs
      - rc-terratec-slim
      - rc-terratec-slim-2
      - rc-tevii-nec
      - rc-tivo
      - rc-total-media-in-hand
      - rc-total-media-in-hand-02
      - rc-trekstor
      - rc-tt-1500
      - rc-twinhan-dtv-cab-ci
      - rc-twinhan1027
      - rc-videomate-k100
      - rc-videomate-s350
      - rc-videomate-tv-pvr
      - rc-videostrong-kii-pro
      - rc-vega-s9x
      - rc-wetek-hub
      - rc-wetek-play2
      - rc-winfast
      - rc-winfast-usbii-deluxe
      - rc-x96max
      - rc-xbox-360
      - rc-xbox-dvd
      - rc-zx-irdec

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,ceu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Capture Engine Unit (CEU) Bindings

maintainers:
  - Jacopo Mondi <jacopo+renesas@jmondi.org>
  - linux-renesas-soc@vger.kernel.org

description: |+
  The Capture Engine Unit is the image capture interface found in the Renesas SH
  Mobile, R-Mobile and RZ SoCs. The interface supports a single parallel input
  with data bus width of 8 or 16 bits.

properties:
  compatible:
    enum:
      - renesas,r7s72100-ceu
      - renesas,r8a7740-ceu

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    unevaluatedProperties: false

    properties:
      endpoint:
        $ref: video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          hsync-active: true
          vsync-active: true
          field-even-active: false
          bus-width:
            enum: [8, 16]
            default: 8

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/r7s72100-clock.h>

    ceu: ceu@e8210000 {
        reg = <0xe8210000 0x209c>;
        compatible = "renesas,r7s72100-ceu";
        interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&mstp6_clks R7S72100_CLK_CEU>;
        power-domains = <&cpg_clocks>;

        port {
            ceu_in: endpoint {
                remote-endpoint = <&ov7670_out>;
                hsync-active = <1>;
                vsync-active = <0>;
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
# Copyright (C) 2020 Renesas Electronics Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car MIPI CSI-2 receiver

maintainers:
  - Niklas Söderlund <niklas.soderlund@ragnatech.se>

description:
  The R-Car CSI-2 receiver device provides MIPI CSI-2 capabilities for the
  Renesas R-Car and RZ/G2 family of devices. It is used in conjunction with the
  R-Car VIN module, which provides the video capture capabilities.

properties:
  compatible:
    items:
      - enum:
          - renesas,r8a774a1-csi2 # RZ/G2M
          - renesas,r8a774b1-csi2 # RZ/G2N
          - renesas,r8a774c0-csi2 # RZ/G2E
          - renesas,r8a774e1-csi2 # RZ/G2H
          - renesas,r8a7795-csi2  # R-Car H3
          - renesas,r8a7796-csi2  # R-Car M3-W
          - renesas,r8a77961-csi2 # R-Car M3-W+
          - renesas,r8a77965-csi2 # R-Car M3-N
          - renesas,r8a77970-csi2 # R-Car V3M
          - renesas,r8a77980-csi2 # R-Car V3H
          - renesas,r8a77990-csi2 # R-Car E3
          - renesas,r8a779a0-csi2 # R-Car V3U

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port node, single endpoint describing the CSI-2 transmitter.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4
                items:
                  maximum: 4

            required:
              - clock-lanes
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Output port node, multiple endpoints describing all the R-Car VIN
          modules connected the CSI-2 receiver.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains
  - resets
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7796-sysc.h>

    csi20: csi2@fea80000 {
            compatible = "renesas,r8a7796-csi2";
            reg = <0xfea80000 0x10000>;
            interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 714>;
            power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
            resets = <&cpg 714>;

            ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@0 {
                            reg = <0>;

                            csi20_in: endpoint {
                                    clock-lanes = <0>;
                                    data-lanes = <1>;
                                    remote-endpoint = <&adv7482_txb>;
                            };
                    };

                    port@1 {
                            #address-cells = <1>;
                            #size-cells = <0>;

                            reg = <1>;

                            csi20vin0: endpoint@0 {
                                    reg = <0>;
                                    remote-endpoint = <&vin0csi20>;
                            };
                            csi20vin1: endpoint@1 {
                                    reg = <1>;
                                    remote-endpoint = <&vin1csi20>;
                            };
                            csi20vin2: endpoint@2 {
                                    reg = <2>;
                                    remote-endpoint = <&vin2csi20>;
                            };
                            csi20vin3: endpoint@3 {
                                    reg = <3>;
                                    remote-endpoint = <&vin3csi20>;
                            };
                            csi20vin4: endpoint@4 {
                                    reg = <4>;
                                    remote-endpoint = <&vin4csi20>;
                            };
                            csi20vin5: endpoint@5 {
                                    reg = <5>;
                                    remote-endpoint = <&vin5csi20>;
                            };
                            csi20vin6: endpoint@6 {
                                    reg = <6>;
                                    remote-endpoint = <&vin6csi20>;
                            };
                            csi20vin7: endpoint@7 {
                                    reg = <7>;
                                    remote-endpoint = <&vin7csi20>;
                            };
                    };
            };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,drif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)

maintainers:
  - Ramesh Shanmugasundaram <rashanmu@gmail.com>
  - Fabrizio Castro <fabrizio.castro.jz@renesas.com>

description: |
  R-Car Gen3 DRIF is a SPI like receive only slave device. A general
  representation of DRIF interfacing with a master device is shown below.

  +---------------------+                +---------------------+
  |                     |-----SCK------->|CLK                  |
  |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
  |                     |-----SD0------->|D0                   |
  |                     |-----SD1------->|D1                   |
  +---------------------+                +---------------------+

  As per datasheet, each DRIF channel (drifn) is made up of two internal
  channels (drifn0 & drifn1). These two internal channels share the common
  CLK & SYNC. Each internal channel has its own dedicated resources like
  irq, dma channels, address space & clock. This internal split is not
  visible to the external master device.

  The device tree model represents each internal channel as a separate node.
  The internal channels sharing the CLK & SYNC are tied together by their
  phandles using a property called "renesas,bonding". For the rest of
  the documentation, unless explicitly stated, the word channel implies an
  internal channel.

  When both internal channels are enabled they need to be managed together
  as one (i.e.) they cannot operate alone as independent devices. Out of the
  two, one of them needs to act as a primary device that accepts common
  properties of both the internal channels. This channel is identified by a
  property called "renesas,primary-bond".

  To summarize,
     * When both the internal channels that are bonded together are enabled,
       the zeroth channel is selected as primary-bond. This channels accepts
       properties common to all the members of the bond.
     * When only one of the bonded channels need to be enabled, the property
       "renesas,bonding" or "renesas,primary-bond" will have no effect. That
       enabled channel can act alone as any other independent device.

properties:
  compatible:
    items:
      - enum:
          - renesas,r8a7795-drif        # R-Car H3
          - renesas,r8a7796-drif        # R-Car M3-W
          - renesas,r8a77965-drif       # R-Car M3-N
          - renesas,r8a77990-drif       # R-Car E3
      - const: renesas,rcar-gen3-drif   # Generic R-Car Gen3 compatible device

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: fck

  resets:
    maxItems: 1

  dmas:
    minItems: 1
    maxItems: 2

  dma-names:
    minItems: 1
    items:
      - const: rx
      - const: rx

  renesas,bonding:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      The phandle to the other internal channel of DRIF

  power-domains:
    maxItems: 1

  renesas,primary-bond:
    type: boolean
    description:
      Indicates that the channel acts as primary among the bonded channels.

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    unevaluatedProperties: false
    description:
      Child port node corresponding to the data input. The port node must
      contain at least one endpoint.

    properties:
      endpoint:
        $ref: /schemas/graph.yaml#/$defs/endpoint-base
        unevaluatedProperties: false

        properties:
          sync-active:
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [0, 1]
            description:
              Indicates sync signal polarity, 0/1 for low/high respectively.
              This property maps to SYNCAC bit in the hardware manual. The
              default is 1 (active high).

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - dmas
  - dma-names
  - renesas,bonding
  - power-domains

allOf:
  - if:
      required:
        - renesas,primary-bond
    then:
      required:
        - pinctrl-0
        - pinctrl-names
        - port

  - if:
      required:
        - port
    then:
      required:
        - pinctrl-0
        - pinctrl-names
    else:
      properties:
        pinctrl-0: false
        pinctrl-names: false

additionalProperties: false

examples:
  # Example with both internal channels enabled.
  #
  # When interfacing with a third party tuner device with two data pins as shown
  # below.
  #
  # +---------------------+                +---------------------+
  # |                     |-----SCK------->|CLK                  |
  # |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
  # |                     |-----SD0------->|D0                   |
  # |                     |-----SD1------->|D1                   |
  # +---------------------+                +---------------------+
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    soc {
            #address-cells = <2>;
            #size-cells = <2>;

            drif00: rif@e6f40000 {
                    compatible = "renesas,r8a7795-drif",
                                 "renesas,rcar-gen3-drif";
                    reg = <0 0xe6f40000 0 0x64>;
                    interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                    clocks = <&cpg CPG_MOD 515>;
                    clock-names = "fck";
                    dmas = <&dmac1 0x20>, <&dmac2 0x20>;
                    dma-names = "rx", "rx";
                    power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                    renesas,bonding = <&drif01>;
                    resets = <&cpg 515>;
                    renesas,primary-bond;
                    pinctrl-0 = <&drif0_pins>;
                    pinctrl-names = "default";
                    port {
                            drif0_ep: endpoint {
                                 remote-endpoint = <&tuner_ep>;
                            };
                    };
            };

            drif01: rif@e6f50000 {
                    compatible = "renesas,r8a7795-drif",
                                 "renesas,rcar-gen3-drif";
                    reg = <0 0xe6f50000 0 0x64>;
                    interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                    clocks = <&cpg CPG_MOD 514>;
                    clock-names = "fck";
                    dmas = <&dmac1 0x22>, <&dmac2 0x22>;
                    dma-names = "rx", "rx";
                    power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                    renesas,bonding = <&drif00>;
                    resets = <&cpg 514>;
            };
    };

  # Example with internal channel 1 alone enabled.
  #
  # When interfacing with a third party tuner device with one data pin as shown
  # below.
  #
  # +---------------------+                +---------------------+
  # |                     |-----SCK------->|CLK                  |
  # |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
  # |                     |                |D0 (unused)          |
  # |                     |-----SD-------->|D1                   |
  # +---------------------+                +---------------------+
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    soc {
            #address-cells = <2>;
            #size-cells = <2>;

            drif10: rif@e6f60000 {
                    compatible = "renesas,r8a7795-drif",
                                 "renesas,rcar-gen3-drif";
                    reg = <0 0xe6f60000 0 0x64>;
                    interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                    clocks = <&cpg CPG_MOD 513>;
                    clock-names = "fck";
                    dmas = <&dmac1 0x24>, <&dmac2 0x24>;
                    dma-names = "rx", "rx";
                    power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                    resets = <&cpg 513>;
                    renesas,bonding = <&drif11>;
            };

            drif11: rif@e6f70000 {
                    compatible = "renesas,r8a7795-drif",
                                 "renesas,rcar-gen3-drif";
                    reg = <0 0xe6f70000 0 0x64>;
                    interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                    clocks = <&cpg CPG_MOD 512>;
                    clock-names = "fck";
                    dmas = <&dmac1 0x26>, <&dmac2 0x26>;
                    dma-names = "rx", "rx";
                    power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                    resets = <&cpg 512>;
                    renesas,bonding = <&drif10>;
                    pinctrl-0 = <&drif1_pins>;
                    pinctrl-names = "default";
                    port {
                            drif1_ep: endpoint {
                                 remote-endpoint = <&tuner_ep1>;
                                 sync-active = <0>;
                            };
                    };
            };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,fcp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car Frame Compression Processor (FCP)

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description: |
  The FCP is a companion module of video processing modules in the Renesas
  R-Car Gen3 and RZ/G2 SoCs. It provides data compression and decompression,
  data caching, and conversion of AXI transactions in order to reduce the
  memory bandwidth.

  There are three types of FCP: FCP for Codec (FCPC), FCP for VSP (FCPV) and
  FCP for FDP (FCPF). Their configuration and behaviour depend on the module
  they are paired with. These DT bindings currently support the FCPV and FCPF.

properties:
  compatible:
    enum:
      - renesas,fcpv # FCP for VSP
      - renesas,fcpf # FCP for FDP

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - power-domains
  - resets

additionalProperties: false

examples:
  # R8A7795 (R-Car H3) FCP for VSP-D1
  - |
    #include <dt-bindings/clock/renesas-cpg-mssr.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    fcp@fea2f000 {
        compatible = "renesas,fcpv";
        reg = <0xfea2f000 0x200>;
        clocks = <&cpg CPG_MOD 602>;
        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
        resets = <&cpg 602>;
        iommus = <&ipmmu_vi0 9>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,fdp1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car Fine Display Processor (FDP1)

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description:
  The FDP1 is a de-interlacing module which converts interlaced video to
  progressive video. It is capable of performing pixel format conversion
  between YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are
  supported as an input to the module.

properties:
  compatible:
    enum:
      - renesas,fdp1

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  renesas,fcp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      A phandle referencing the FCP that handles memory accesses for the FDP1.
      Not allowed on R-Car Gen2, mandatory on R-Car Gen3.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/renesas-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    fdp1@fe940000 {
        compatible = "renesas,fdp1";
        reg = <0xfe940000 0x2400>;
        interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD 119>;
        power-domains = <&sysc R8A7795_PD_A3VP>;
        resets = <&cpg 119>;
        renesas,fcp = <&fcpf0>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,imr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car Image Renderer (Distortion Correction Engine)

maintainers:
  - Sergei Shtylyov <sergei.shtylyov@gmail.com>

description: |
  The image renderer, or the distortion correction engine, is a drawing
  processor with a simple instruction system capable of referencing video
  capture data or data in an external memory as 2D texture data and performing
  texture mapping and drawing with respect to any shape that is split into
  triangular objects.

  The image renderer light extended 4 (IMR-LX4) is found in R-Car Gen3 SoCs.

properties:
  compatible:
    items:
      - enum:
          - renesas,r8a7795-imr-lx4 # R-Car H3
          - renesas,r8a7796-imr-lx4 # R-Car M3-W
      - const: renesas,imr-lx4      # R-Car Gen3

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    imr-lx4@fe860000 {
            compatible = "renesas,r8a7795-imr-lx4", "renesas,imr-lx4";
            reg = <0xfe860000 0x2000>;
            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 823>;
            power-domains = <&sysc R8A7795_PD_A3VC>;
            resets = <&cpg 823>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (C) 2021 Renesas Electronics Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,isp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car ISP Channel Selector

maintainers:
  - Niklas Söderlund <niklas.soderlund@ragnatech.se>

description:
  The R-Car ISP Channel Selector provides MIPI CSI-2 VC and DT filtering
  capabilities for the Renesas R-Car family of devices. It is used in
  conjunction with the R-Car VIN and CSI-2 modules, which provides the video
  capture capabilities.

properties:
  compatible:
    items:
      - enum:
          - renesas,r8a779a0-isp # V3U
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Input port node, multiple endpoints describing the connected R-Car
          CSI-2 receivers.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Single endpoint describing the R-Car VIN connected to output port 0.

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Single endpoint describing the R-Car VIN connected to output port 1.

      port@3:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Single endpoint describing the R-Car VIN connected to output port 2.

      port@4:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Single endpoint describing the R-Car VIN connected to output port 3.

      port@5:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Single endpoint describing the R-Car VIN connected to output port 4.

      port@6:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Single endpoint describing the R-Car VIN connected to output port 5.

      port@7:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Single endpoint describing the R-Car VIN connected to output port 6.

      port@8:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Single endpoint describing the R-Car VIN connected to output port 7.

    required:
      - port@0
      - port@1
      - port@2
      - port@3
      - port@4
      - port@5
      - port@6
      - port@7
      - port@8

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains
  - resets
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a779a0-sysc.h>

    isp1: isp@fed20000 {
            compatible = "renesas,r8a779a0-isp";
            reg = <0xfed20000 0x10000>;
            interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 613>;
            power-domains = <&sysc R8A779A0_PD_A3ISP01>;
            resets = <&cpg 613>;

            ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@0 {
                            #address-cells = <1>;
                            #size-cells = <0>;

                            reg = <0>;
                            isp1csi41: endpoint@1 {
                                    reg = <1>;
                                    remote-endpoint = <&csi41isp1>;
                            };
                    };

                    port@1 {
                            reg = <1>;
                            isp1vin08: endpoint {
                                    remote-endpoint = <&vin08isp1>;
                            };
                    };

                    port@2 {
                            reg = <2>;
                            isp1vin09: endpoint {
                                    remote-endpoint = <&vin09isp1>;
                            };
                    };

                    port@3 {
                            reg = <3>;
                            isp1vin10: endpoint {
                                    remote-endpoint = <&vin10isp1>;
                            };
                    };

                    port@4 {
                            reg = <4>;
                            isp1vin11: endpoint {
                                    remote-endpoint = <&vin11isp1>;
                            };
                    };

                    port@5 {
                            reg = <5>;
                            isp1vin12: endpoint {
                                    remote-endpoint = <&vin12isp1>;
                            };
                    };

                    port@6 {
                            reg = <6>;
                            isp1vin13: endpoint {
                                    remote-endpoint = <&vin13isp1>;
                            };
                    };

                    port@7 {
                            reg = <7>;
                            isp1vin14: endpoint {
                                    remote-endpoint = <&vin14isp1>;
                            };
                    };

                    port@8 {
                            reg = <8>;
                            isp1vin15: endpoint {
                                    remote-endpoint = <&vin15isp1>;
                            };
                    };
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,jpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas JPEG Processing Unit

maintainers:
  - Mikhail Ulyanov <mikhail.ulyanov@cogentembedded.com>

description:
  The JPEG processing unit (JPU) incorporates the JPEG codec with an encoding
  and decoding function conforming to the JPEG baseline process, so that the
  JPU can encode image data and decode JPEG data quickly.

properties:
  compatible:
    items:
      - enum:
          - renesas,jpu-r8a7790      # R-Car H2
          - renesas,jpu-r8a7791      # R-Car M2-W
          - renesas,jpu-r8a7792      # R-Car V2H
          - renesas,jpu-r8a7793      # R-Car M2-N
      - const: renesas,rcar-gen2-jpu # R-Car Gen2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>

    jpeg-codec@fe980000 {
            compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
            reg = <0xfe980000 0x10300>;
            interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 106>;
            power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
            resets = <&cpg 106>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2022 Renesas Electronics Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing

maintainers:
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

description:
  The CRU image processing module is a data conversion module equipped with pixel
  color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and
  parallel (including ITU-R BT.656) input are provided as the image sensor interface.

properties:
  compatible:
    items:
      - enum:
          - renesas,r9a07g044-cru       # RZ/G2{L,LC}
          - renesas,r9a07g054-cru       # RZ/V2L
      - const: renesas,rzg2l-cru

  reg:
    maxItems: 1

  interrupts:
    maxItems: 3

  interrupt-names:
    items:
      - const: image_conv
      - const: image_conv_err
      - const: axi_mst_err

  clocks:
    items:
      - description: CRU Main clock
      - description: CRU Register access clock
      - description: CRU image transfer clock

  clock-names:
    items:
      - const: video
      - const: apb
      - const: axi

  power-domains:
    maxItems: 1

  resets:
    items:
      - description: CRU_PRESETN reset terminal
      - description: CRU_ARESETN reset terminal

  reset-names:
    items:
      - const: presetn
      - const: aresetn

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port node, single endpoint describing a parallel input source.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              hsync-active: true
              vsync-active: true
              bus-width: true
              data-shift: true

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Input port node, describing the Image Processing module connected to the
          CSI-2 receiver.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - resets
  - reset-names
  - power-domains

additionalProperties: false

examples:
  # Device node example with CSI-2
  - |
    #include <dt-bindings/clock/r9a07g044-cpg.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    cru: video@10830000 {
        compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
        reg = <0x10830000 0x400>;
        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
        clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
                 <&cpg CPG_MOD R9A07G044_CRU_PCLK>,
                 <&cpg CPG_MOD R9A07G044_CRU_ACLK>;
        clock-names = "video", "apb", "axi";
        power-domains = <&cpg>;
        resets = <&cpg R9A07G044_CRU_PRESETN>,
                 <&cpg R9A07G044_CRU_ARESETN>;
        reset-names = "presetn", "aresetn";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;

                cru_parallel_in: endpoint@0 {
                    reg = <0>;
                    remote-endpoint= <&ov5642>;
                    hsync-active = <1>;
                    vsync-active = <1>;
                };
            };

            port@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;

                cru_csi_in: endpoint@0 {
                    reg = <0>;
                    remote-endpoint= <&csi_cru_in>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2022 Renesas Electronics Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver

maintainers:
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

description:
  The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L
  (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction
  with the Image Processing module, which provides the video capture capabilities.

properties:
  compatible:
    items:
      - enum:
          - renesas,r9a07g044-csi2       # RZ/G2{L,LC}
          - renesas,r9a07g054-csi2       # RZ/V2L
      - const: renesas,rzg2l-csi2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Internal clock for connecting CRU and MIPI
      - description: CRU Main clock
      - description: CRU Register access clock

  clock-names:
    items:
      - const: system
      - const: video
      - const: apb

  power-domains:
    maxItems: 1

  resets:
    items:
      - description: CRU_PRESETN reset terminal
      - description: CRU_CMN_RSTB reset terminal

  reset-names:
    items:
      - const: presetn
      - const: cmn-rstb

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port node, single endpoint describing the CSI-2 transmitter.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4
                items:
                  maximum: 4

            required:
              - clock-lanes
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Output port node, Image Processing block connected to the CSI-2 receiver.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains
  - resets
  - reset-names
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r9a07g044-cpg.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    csi: csi@10830400 {
        compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
        reg = <0x10830400 0xfc00>;
        interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
                 <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
                 <&cpg CPG_MOD R9A07G044_CRU_PCLK>;
        clock-names = "system", "video", "apb";
        power-domains = <&cpg>;
        resets = <&cpg R9A07G044_CRU_PRESETN>,
                 <&cpg R9A07G044_CRU_CMN_RSTB>;
        reset-names = "presetn", "cmn-rstb";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                csi2_in: endpoint {
                    clock-lanes = <0>;
                    data-lanes = <1 2>;
                    remote-endpoint = <&ov5645_ep>;
                };
            };

            port@1 {
                #address-cells = <1>;
                #size-cells = <0>;

                reg = <1>;

                csi2cru: endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&crucsi2>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
# Copyright (C) 2020 Renesas Electronics Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,vin.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car Video Input (VIN)

maintainers:
  - Niklas Söderlund <niklas.soderlund@ragnatech.se>

description:
  The R-Car Video Input (VIN) device provides video input capabilities for the
  Renesas R-Car family of devices.

  Each VIN instance has a single parallel input that supports RGB and YUV video,
  with both external synchronization and BT.656 synchronization for the latter.
  Depending on the instance the VIN input is connected to external SoC pins, or
  on Gen3 and RZ/G2 platforms to a CSI-2 receiver.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,vin-r8a7742  # RZ/G1H
              - renesas,vin-r8a7743  # RZ/G1M
              - renesas,vin-r8a7744  # RZ/G1N
              - renesas,vin-r8a7745  # RZ/G1E
              - renesas,vin-r8a77470 # RZ/G1C
              - renesas,vin-r8a7790  # R-Car H2
              - renesas,vin-r8a7791  # R-Car M2-W
              - renesas,vin-r8a7792  # R-Car V2H
              - renesas,vin-r8a7793  # R-Car M2-N
              - renesas,vin-r8a7794  # R-Car E2
          - const: renesas,rcar-gen2-vin # Generic R-Car Gen2 or RZ/G1

      - items:
          - enum:
              - renesas,vin-r8a774a1 # RZ/G2M
              - renesas,vin-r8a774b1 # RZ/G2N
              - renesas,vin-r8a774c0 # RZ/G2E
              - renesas,vin-r8a774e1 # RZ/G2H
              - renesas,vin-r8a7778  # R-Car M1
              - renesas,vin-r8a7779  # R-Car H1
              - renesas,vin-r8a7795  # R-Car H3
              - renesas,vin-r8a7796  # R-Car M3-W
              - renesas,vin-r8a77961 # R-Car M3-W+
              - renesas,vin-r8a77965 # R-Car M3-N
              - renesas,vin-r8a77970 # R-Car V3M
              - renesas,vin-r8a77980 # R-Car V3H
              - renesas,vin-r8a77990 # R-Car E3
              - renesas,vin-r8a77995 # R-Car D3
              - renesas,vin-r8a779a0 # R-Car V3U

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  #The per-board settings for Gen2 and RZ/G1 platforms:
  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    unevaluatedProperties: false
    description:
      A node containing a parallel input

    properties:
      endpoint:
        $ref: video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          hsync-active:
            description:
              If both HSYNC and VSYNC polarities are not specified, embedded
              synchronization is selected.
            default: 1

          vsync-active:
            description:
              If both HSYNC and VSYNC polarities are not specified, embedded
              synchronization is selected.
            default: 1

          field-active-even: true

          bus-width: true

          data-shift: true

          data-enable-active:
            description: Polarity of CLKENB signal
            default: 1

          pclk-sample: true

          data-active: true

  #The per-board settings for Gen3 and RZ/G2 platforms:
  renesas,id:
    description: VIN channel number
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 31

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port node, single endpoint describing a parallel input source.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              hsync-active:
                description:
                  If both HSYNC and VSYNC polarities are not specified, embedded
                  synchronization is selected.
                default: 1

              vsync-active:
                description:
                  If both HSYNC and VSYNC polarities are not specified, embedded
                  synchronization is selected.
                default: 1

              field-active-even: true

              bus-width: true

              data-shift: true

              data-enable-active:
                description: Polarity of CLKENB signal
                default: 1

              pclk-sample: true

              data-active: true

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Input port node, multiple endpoints describing all the R-Car CSI-2
          modules connected the VIN.

        properties:
          endpoint@0:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: Endpoint connected to CSI20.

          endpoint@1:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: Endpoint connected to CSI21.

          endpoint@2:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: Endpoint connected to CSI40.

          endpoint@3:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: Endpoint connected to CSI41.

        anyOf:
          - required:
              - endpoint@0
          - required:
              - endpoint@1
          - required:
              - endpoint@2
          - required:
              - endpoint@3

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Input port node, multiple endpoints describing all the R-Car ISP
          modules connected the VIN.

        properties:
          endpoint@0:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: Endpoint connected to ISP0.

          endpoint@1:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: Endpoint connected to ISP1.

          endpoint@2:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: Endpoint connected to ISP2.

          endpoint@3:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: Endpoint connected to ISP3.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains

allOf:
  - if:
      not:
        properties:
          compatible:
            contains:
              enum:
                - renesas,vin-r8a7778
                - renesas,vin-r8a7779
    then:
      required:
        - resets

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,vin-r8a7778
              - renesas,vin-r8a7779
              - renesas,rcar-gen2-vin
    then:
      required:
        - port
    else:
      required:
        - renesas,id
        - ports

additionalProperties: false

examples:
  # Device node example for Gen2 platform
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>

    vin1: vin@e6ef1000 {
            compatible = "renesas,vin-r8a7790",
                         "renesas,rcar-gen2-vin";
            reg = <0xe6ef1000 0x1000>;
            interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 810>;
            power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
            resets = <&cpg 810>;

            port {
                    vin1ep0: endpoint {
                            remote-endpoint = <&adv7180>;
                            bus-width = <8>;
                    };
            };
    };

  # Device node example for Gen3 platform with only CSI-2
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    vin0: video@e6ef0000 {
            compatible = "renesas,vin-r8a7795";
            reg = <0xe6ef0000 0x1000>;
            interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 811>;
            power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
            resets = <&cpg 811>;
            renesas,id = <0>;

            ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@1 {
                            #address-cells = <1>;
                            #size-cells = <0>;

                            reg = <1>;

                            vin0csi20: endpoint@0 {
                                    reg = <0>;
                                    remote-endpoint= <&csi20vin0>;
                            };
                            vin0csi40: endpoint@2 {
                                    reg = <2>;
                                    remote-endpoint= <&csi40vin0>;
                            };
                    };
            };
    };

  # Device node example for Gen3 platform with CSI-2 and parallel
  - |
    #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a77970-sysc.h>

    vin2: video@e6ef2000 {
            compatible = "renesas,vin-r8a77970";
            reg = <0xe6ef2000 0x1000>;
            interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 809>;
            power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
            resets = <&cpg 809>;
            renesas,id = <2>;

            ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@0 {
                            reg = <0>;

                            vin2_in: endpoint {
                                    remote-endpoint = <&adv7612_out>;
                                    hsync-active = <0>;
                                    vsync-active = <0>;
                            };
                    };

                    port@1 {
                            #address-cells = <1>;
                            #size-cells = <0>;

                            reg = <1>;

                            vin2csi40: endpoint@2 {
                                    reg = <2>;
                                    remote-endpoint = <&csi40vin2>;
                            };
                    };
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,vsp1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas VSP Video Processing Engine

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description:
  The VSP is a video processing engine that supports up-/down-scaling, alpha
  blending, color space conversion and various other image processing features.
  It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.

properties:
  compatible:
    enum:
      - renesas,r9a07g044-vsp2 # RZ/G2L
      - renesas,vsp1 # R-Car Gen2 and RZ/G1
      - renesas,vsp2 # R-Car Gen3 and RZ/G2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks: true
  clock-names: true

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  renesas,fcp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      A phandle referencing the FCP that handles memory accesses for the VSP.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains
  - resets

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: renesas,vsp1
    then:
      properties:
        renesas,fcp: false
    else:
      required:
        - renesas,fcp

  - if:
      properties:
        compatible:
          contains:
            const: renesas,r9a07g044-vsp2
    then:
      properties:
        clocks:
          items:
            - description: Main clock
            - description: Register access clock
            - description: Video clock
        clock-names:
          items:
            - const: aclk
            - const: pclk
            - const: vclk
      required:
        - clock-names
    else:
      properties:
        clocks:
          maxItems: 1
        clock-names: false

examples:
  # R8A7790 (R-Car H2) VSP1-S
  - |
    #include <dt-bindings/clock/renesas-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>

    vsp@fe928000 {
        compatible = "renesas,vsp1";
        reg = <0xfe928000 0x8000>;
        interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD 131>;
        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
        resets = <&cpg 131>;
    };

  # R8A77951 (R-Car H3) VSP2-BC
  - |
    #include <dt-bindings/clock/renesas-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    vsp@fe920000 {
        compatible = "renesas,vsp2";
        reg = <0xfe920000 0x8000>;
        interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD 624>;
        power-domains = <&sysc R8A7795_PD_A3VP>;
        resets = <&cpg 624>;

        renesas,fcp = <&fcpvb1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/rockchip,rk3568-vepu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Hantro G1 VPU encoders implemented on Rockchip SoCs

maintainers:
  - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>

description:
  Hantro G1 video encode-only accelerators present on Rockchip SoCs.

properties:
  compatible:
    enum:
      - rockchip,rk3568-vepu

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: aclk
      - const: hclk

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3568-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/rk3568-power.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        vepu: video-codec@fdee0000 {
            compatible = "rockchip,rk3568-vepu";
            reg = <0x0 0xfdee0000 0x0 0x800>;
            interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
            clock-names = "aclk", "hclk";
            iommus = <&vepu_mmu>;
            power-domains = <&power RK3568_PD_RGA>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/rockchip,vdec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip Video Decoder (VDec)

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

description: |-
  The Rockchip rk3399 has a stateless Video Decoder that can decodes H.264,
  HEVC an VP9 streams.

properties:
  compatible:
    oneOf:
      - const: rockchip,rk3399-vdec
      - items:
          - enum:
              - rockchip,rk3228-vdec
              - rockchip,rk3328-vdec
          - const: rockchip,rk3399-vdec

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: The Video Decoder AXI interface clock
      - description: The Video Decoder AHB interface clock
      - description: The Video Decoded CABAC clock
      - description: The Video Decoder core clock

  clock-names:
    items:
      - const: axi
      - const: ahb
      - const: cabac
      - const: core

  assigned-clocks: true

  assigned-clock-rates: true

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/rk3399-cru.h>
    #include <dt-bindings/power/rk3399-power.h>

    vdec: video-codec@ff660000 {
        compatible = "rockchip,rk3399-vdec";
        reg = <0xff660000 0x400>;
        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
        clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
                 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
        clock-names = "axi", "ahb", "cabac", "core";
        power-domains = <&power RK3399_PD_VDU>;
        iommus = <&vdec_mmu>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip SoC Image Signal Processing unit v1

maintainers:
  - Helen Koike <helen.koike@collabora.com>

description: |
  Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
  which contains image processing, scaling, and compression functions.

properties:
  compatible:
    enum:
      - rockchip,px30-cif-isp
      - rockchip,rk3399-cif-isp

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 3

  interrupt-names:
    items:
      - const: isp
      - const: mi
      - const: mipi

  clocks:
    minItems: 3
    items:
      # isp0 and isp1
      - description: ISP clock
      - description: ISP AXI clock
      - description: ISP AHB clock
      # only for isp1
      - description: ISP Pixel clock

  clock-names:
    minItems: 3
    items:
      # isp0 and isp1
      - const: isp
      - const: aclk
      - const: hclk
      # only for isp1
      - const: pclk

  iommus:
    maxItems: 1

  phys:
    maxItems: 1
    description: phandle for the PHY port

  phy-names:
    const: dphy

  power-domains:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: connection point for sensors at MIPI-DPHY RX0

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: connection point for input on the parallel interface

        properties:
          bus-type:
            enum: [5, 6]

          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

        required:
          - bus-type

    anyOf:
      - required:
          - port@0
      - required:
          - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - iommus
  - phys
  - phy-names
  - power-domains
  - ports

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: rockchip,rk3399-cif-isp
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 4
        clock-names:
          minItems: 3
          maxItems: 4

  - if:
      properties:
        compatible:
          contains:
            const: rockchip,px30-cif-isp
    then:
      required:
        - interrupt-names

additionalProperties: false

examples:
  - |

    #include <dt-bindings/clock/rk3399-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/rk3399-power.h>

    parent0: parent {
        #address-cells = <2>;
        #size-cells = <2>;

        isp0: isp0@ff910000 {
            compatible = "rockchip,rk3399-cif-isp";
            reg = <0x0 0xff910000 0x0 0x4000>;
            interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
            clocks = <&cru SCLK_ISP0>,
                     <&cru ACLK_ISP0_WRAPPER>,
                     <&cru HCLK_ISP0_WRAPPER>;
            clock-names = "isp", "aclk", "hclk";
            iommus = <&isp0_mmu>;
            phys = <&dphy>;
            phy-names = "dphy";
            power-domains = <&power RK3399_PD_ISP0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    #address-cells = <1>;
                    #size-cells = <0>;

                    mipi_in_wcam: endpoint@0 {
                        reg = <0>;
                        remote-endpoint = <&wcam_out>;
                        data-lanes = <1 2>;
                    };

                    mipi_in_ucam: endpoint@1 {
                        reg = <1>;
                        remote-endpoint = <&ucam_out>;
                        data-lanes = <1>;
                    };
                };
            };
        };

        i2c7: i2c {
            #address-cells = <1>;
            #size-cells = <0>;

            wcam: camera@36 {
                compatible = "ovti,ov5695";
                reg = <0x36>;

                port {
                    wcam_out: endpoint {
                        remote-endpoint = <&mipi_in_wcam>;
                        data-lanes = <1 2>;
                    };
                };
            };

            ucam: camera@3c {
                compatible = "ovti,ov2685";
                reg = <0x3c>;

                  port {
                      ucam_out: endpoint {
                          remote-endpoint = <&mipi_in_ucam>;
                          data-lanes = <1>;
                      };
                  };
            };
        };
    };

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/px30-power.h>

    parent1: parent {
        #address-cells = <2>;
        #size-cells = <2>;

        isp: isp@ff4a0000 {
            compatible = "rockchip,px30-cif-isp";
            reg = <0x0 0xff4a0000 0x0 0x8000>;
            interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "isp", "mi", "mipi";
            clocks = <&cru SCLK_ISP0>,
                     <&cru ACLK_ISP0_WRAPPER>,
                     <&cru HCLK_ISP0_WRAPPER>,
                     <&cru PCLK_ISP1_WRAPPER>;
            clock-names = "isp", "aclk", "hclk", "pclk";
            iommus = <&isp_mmu>;
            phys = <&csi_dphy>;
            phy-names = "dphy";
            power-domains = <&power PX30_PD_VI>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    #address-cells = <1>;
                    #size-cells = <0>;

                    mipi_in_ucam1: endpoint@0 {
                        reg = <0>;
                        remote-endpoint = <&ucam1_out>;
                        data-lanes = <1 2>;
                    };
                };
            };
        };

        i2c2: i2c {
            #address-cells = <1>;
            #size-cells = <0>;

            ov5695: camera@36 {
                compatible = "ovti,ov5647";
                reg = <0x36>;
                clocks = <&cru SCLK_CIF_OUT>;

                port {
                    ucam1_out: endpoint {
                        remote-endpoint = <&mipi_in_ucam1>;
                        data-lanes = <1 2>;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/rockchip-rga.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip 2D raster graphic acceleration controller (RGA)

description:
  RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D
  graphics operations, such as point/line drawing, image scaling, rotation,
  BitBLT, alpha blending and image blur/sharpness.

maintainers:
  - Jacob Chen <jacob-chen@iotwrt.com>
  - Ezequiel Garcia <ezequiel@collabora.com>

properties:
  compatible:
    oneOf:
      - const: rockchip,rk3288-rga
      - const: rockchip,rk3399-rga
      - items:
          - const: rockchip,rk3228-rga
          - const: rockchip,rk3288-rga

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: aclk
      - const: hclk
      - const: sclk

  power-domains:
    maxItems: 1

  resets:
    maxItems: 3

  reset-names:
    items:
      - const: core
      - const: axi
      - const: ahb

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3399-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/rk3399-power.h>
    rga: rga@ff680000 {
      compatible = "rockchip,rk3399-rga";
      reg = <0xff680000 0x10000>;
      interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&cru ACLK_RGA>,
               <&cru HCLK_RGA>,
               <&cru SCLK_RGA_CORE>;
      clock-names = "aclk", "hclk", "sclk";
      power-domains = <&power RK3399_PD_RGA>;
      resets = <&cru SRST_RGA_CORE>,
               <&cru SRST_A_RGA>,
               <&cru SRST_H_RGA>;
      reset-names = "core", "axi", "ahb";
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/rockchip-vpu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Hantro G1 VPU codecs implemented on Rockchip SoCs

maintainers:
  - Ezequiel Garcia <ezequiel@collabora.com>

description:
  Hantro G1 video encode and decode accelerators present on Rockchip SoCs.

properties:
  compatible:
    oneOf:
      - enum:
          - rockchip,rk3036-vpu
          - rockchip,rk3066-vpu
          - rockchip,rk3288-vpu
          - rockchip,rk3328-vpu
          - rockchip,rk3399-vpu
          - rockchip,px30-vpu
          - rockchip,rk3568-vpu
      - items:
          - const: rockchip,rk3188-vpu
          - const: rockchip,rk3066-vpu
      - items:
          - const: rockchip,rk3228-vpu
          - const: rockchip,rk3399-vpu

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 2

  interrupt-names:
    oneOf:
      - const: vdpu
      - items:
          - const: vepu
          - const: vdpu

  clocks:
    oneOf:
      - maxItems: 2
      - maxItems: 4

  clock-names:
    oneOf:
      - items:
          - const: aclk
          - const: hclk
      - items:
          - const: aclk_vdpu
          - const: hclk_vdpu
          - const: aclk_vepu
          - const: hclk_vepu

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
        #include <dt-bindings/clock/rk3288-cru.h>
        #include <dt-bindings/interrupt-controller/arm-gic.h>
        #include <dt-bindings/power/rk3288-power.h>

        vpu: video-codec@ff9a0000 {
                compatible = "rockchip,rk3288-vpu";
                reg = <0xff9a0000 0x800>;
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "vepu", "vdpu";
                clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
                clock-names = "aclk", "hclk";
                power-domains = <&power RK3288_PD_VIDEO>;
                iommus = <&vpu_mmu>;
        };


code:
* Samsung HDMI CEC driver

The HDMI CEC module is present is Samsung SoCs and its purpose is to
handle communication between HDMI connected devices over the CEC bus.

Required properties:
  - compatible : value should be following
	"samsung,s5p-cec"

  - reg : Physical base address of the IP registers and length of memory
	  mapped region.

  - interrupts : HDMI CEC interrupt number to the CPU.
  - clocks : from common clock binding: handle to HDMI CEC clock.
  - clock-names : from common clock binding: must contain "hdmicec",
		  corresponding to entry in the clocks property.
  - samsung,syscon-phandle - phandle to the PMU system controller
  - hdmi-phandle - phandle to the HDMI controller, see also cec.txt.

Optional:
  - needs-hpd : if present the CEC support is only available when the HPD
		is high. See cec.txt for more details.

Example:

hdmicec: cec@100b0000 {
	compatible = "samsung,s5p-cec";
	reg = <0x100B0000 0x200>;
	interrupts = <0 114 0>;
	clocks = <&clock CLK_HDMI_CEC>;
	clock-names = "hdmicec";
	samsung,syscon-phandle = <&pmu_system_controller>;
	hdmi-phandle = <&hdmi>;
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_cec>;
};


code:
* Samsung Multi Format Codec (MFC)

Multi Format Codec (MFC) is the IP present in Samsung SoCs which
supports high resolution decoding and encoding functionalities.
The MFC device driver is a v4l2 driver which can encode/decode
video raw/elementary streams and has support for all popular
video codecs.

Required properties:
  - compatible : value should be either one among the following
	(a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
	(b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
	(c) "samsung,exynos3250-mfc", "samsung,mfc-v7" for MFC v7
	     present in Exynos3250 SoC
	(d) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
	(e) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
	(f) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
	(g) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC

  - reg : Physical base address of the IP registers and length of memory
	  mapped region.

  - interrupts : MFC interrupt number to the CPU.
  - clocks : from common clock binding: handle to mfc clock.
  - clock-names : from common clock binding: must contain "mfc",
		  corresponding to entry in the clocks property.

Optional properties:
  - power-domains : power-domain property defined with a phandle
			   to respective power domain.
  - memory-region : from reserved memory binding: phandles to two reserved
	memory regions, first is for "left" mfc memory bus interfaces,
	second if for the "right" mfc memory bus, used when no SYSMMU
	support is available; used only by MFC v5 present in Exynos4 SoCs

Obsolete properties:
  - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region
	property instead

Example:
SoC specific DT entry:

mfc: codec@13400000 {
	compatible = "samsung,mfc-v5";
	reg = <0x13400000 0x10000>;
	interrupts = <0 94 0>;
	power-domains = <&pd_mfc>;
	clocks = <&clock 273>;
	clock-names = "mfc";
};

Reserved memory specific DT entry for given board (see reserved memory binding
for more information):

reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	mfc_left: region@51000000 {
		compatible = "shared-dma-pool";
		no-map;
		reg = <0x51000000 0x800000>;
	};

	mfc_right: region@43000000 {
		compatible = "shared-dma-pool";
		no-map;
		reg = <0x43000000 0x800000>;
	};
};

Board specific DT entry:

codec@13400000 {
	memory-region = <&mfc_left>, <&mfc_right>;
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/samsung,exynos5250-gsc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC G-Scaler

maintainers:
  - Inki Dae <inki.dae@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Seung-Woo Kim <sw0312.kim@samsung.com

description:
  G-Scaler is used for scaling and color space conversion on Samsung Exynos
  SoCs.

  Each G-Scaler node should have a numbered alias in the aliases node, in the
  form of gscN, N = 0...3.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - samsung,exynos5250-gsc
              - samsung,exynos5420-gsc
          - const: samsung,exynos5-gsc
      - enum:
          - samsung,exynos5433-gsc
      - const: samsung,exynos5-gsc
        deprecated: True

  clocks:
    minItems: 1
    maxItems: 5

  clock-names:
    minItems: 1
    maxItems: 5

  interrupts:
    maxItems: 1

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

  samsung,sysreg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Syscon used to control the system registers to set writeback input and destination.

required:
  - compatible
  - clocks
  - clock-names
  - interrupts
  - reg

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos5-gsc
              - samsung,exynos5250-gsc
              - samsung,exynos5420-gsc
    then:
      properties:
        clocks:
          maxItems: 1
        clock-names:
          items:
            - const: gscl
    else:
      properties:
        clocks:
          minItems: 5
        clock-names:
          items:
            - const: pclk
            - const: aclk
            - const: aclk_xiu
            - const: aclk_gsclbend
            - const: gsd

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5250.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    video-scaler@13e00000 {
        compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
        reg = <0x13e00000 0x1000>;
        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
        power-domains = <&pd_gsc>;
        clocks = <&clock CLK_GSCL0>;
        clock-names = "gscl";
        iommus = <&sysmmu_gsc0>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/samsung,s5pv210-jpeg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S5PV210 and Exynos SoC JPEG codec

maintainers:
  - Jacek Anaszewski <jacek.anaszewski@gmail.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Andrzej Pietrasiewicz <andrzejtp2010@gmail.com>

properties:
  compatible:
    enum:
      - samsung,s5pv210-jpeg
      - samsung,exynos3250-jpeg
      - samsung,exynos4210-jpeg
      - samsung,exynos4212-jpeg
      - samsung,exynos5420-jpeg
      - samsung,exynos5433-jpeg

  clocks:
    minItems: 1
    maxItems: 4

  clock-names:
    minItems: 1
    maxItems: 4

  interrupts:
    maxItems: 1

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - clocks
  - clock-names
  - interrupts
  - reg

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,s5pv210-jpeg
              - samsung,exynos4210-jpeg
              - samsung,exynos4212-jpeg
              - samsung,exynos5420-jpeg
    then:
      properties:
        clocks:
          maxItems: 1
        clock-names:
          items:
            - const: jpeg

  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos3250-jpeg
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: jpeg
            - const: sclk

  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos5433-jpeg
    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4
        clock-names:
          items:
            - const: pclk
            - const: aclk
            - const: aclk_xiu
            - const: sclk

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5433.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    codec@15020000 {
        compatible = "samsung,exynos5433-jpeg";
        reg = <0x15020000 0x10000>;
        interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
        clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
        clocks = <&cmu_mscl CLK_PCLK_JPEG>,
                 <&cmu_mscl CLK_ACLK_JPEG>,
                 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
                 <&cmu_mscl CLK_SCLK_JPEG>;
        iommus = <&sysmmu_jpeg>;
        power-domains = <&pd_mscl>;
    };