code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8qm/qxp LVDS Display Bridge

maintainers:
  - Liu Ying <victor.liu@nxp.com>

description: |
  The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.

  The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
  The CSR module, as a system controller, contains the LDB's configuration
  registers.

  For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
  format and can map the input to VESA or JEIDA standards.  The two channels
  cannot be used simultaneously, that is to say, the user should pick one of
  them to use.  Two LDB channels from two LDB instances can work together in
  LDB split mode to support a dual link LVDS display.  The channel indexes
  have to be different.  Channel0 outputs odd pixels and channel1 outputs
  even pixels.

  For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
  input color format.  The two channels can be used simultaneously, either
  in dual mode or split mode.  In dual mode, the two channels output identical
  data.  In split mode, channel0 outputs odd pixels and channel1 outputs even
  pixels.

  A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
  the SoC reference manuals.  The pixel mapper uses logic of LDBs embedded in
  i.MX6qdl/sx SoCs, i.e., it is essentially based on them.  To keep the naming
  consistency, this binding calls it LDB.

properties:
  compatible:
    enum:
      - fsl,imx8qm-ldb
      - fsl,imx8qxp-ldb

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  clocks:
    items:
      - description: pixel clock
      - description: bypass clock

  clock-names:
    items:
      - const: pixel
      - const: bypass

  power-domains:
    maxItems: 1

  fsl,companion-ldb:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      A phandle which points to companion LDB which is used in LDB split mode.

patternProperties:
  "^channel@[0-1]$":
    type: object
    description: Represents a channel of LDB.

    properties:
      "#address-cells":
        const: 1

      "#size-cells":
        const: 0

      reg:
        description: The channel index.
        enum: [ 0, 1 ]

      phys:
        description: A phandle to the phy module representing the LVDS PHY.
        maxItems: 1

      phy-names:
        const: lvds_phy

      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Input port of the channel.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Output port of the channel.

    required:
      - "#address-cells"
      - "#size-cells"
      - reg
      - phys
      - phy-names

    additionalProperties: false

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - clocks
  - clock-names
  - power-domains
  - channel@0
  - channel@1

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8qm-ldb
    then:
      properties:
        fsl,companion-ldb: false

additionalProperties: false

examples:
  - |
    #include <dt-bindings/firmware/imx/rsrc.h>
    ldb {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "fsl,imx8qxp-ldb";
        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
                 <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
        clock-names = "pixel", "bypass";
        power-domains = <&pd IMX_SC_R_LVDS_0>;

        channel@0 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
            phys = <&mipi_lvds_0_phy>;
            phy-names = "lvds_phy";

            port@0 {
                reg = <0>;

                mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
                };
            };
        };

        channel@1 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
            phys = <&mipi_lvds_0_phy>;
            phy-names = "lvds_phy";

            port@0 {
                reg = <0>;

                mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8qm/qxp Pixel Combiner

maintainers:
  - Liu Ying <victor.liu@nxp.com>

description: |
  The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
  single display controller and manipulates the two streams to support a number
  of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
  either one screen, two screens, or virtual screens.  The pixel combiner is
  also responsible for generating some of the control signals for the pixel link
  output channel.

properties:
  compatible:
    enum:
      - fsl,imx8qm-pixel-combiner
      - fsl,imx8qxp-pixel-combiner

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: apb

  power-domains:
    maxItems: 1

patternProperties:
  "^channel@[0-1]$":
    type: object
    description: Represents a display stream of pixel combiner.

    properties:
      "#address-cells":
        const: 1

      "#size-cells":
        const: 0

      reg:
        description: The display stream index.
        enum: [ 0, 1 ]

      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Input endpoint of the display stream.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Output endpoint of the display stream.

    required:
      - "#address-cells"
      - "#size-cells"
      - reg
      - port@0
      - port@1

    additionalProperties: false

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - reg
  - clocks
  - clock-names
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8-lpcg.h>
    #include <dt-bindings/firmware/imx/rsrc.h>
    pixel-combiner@56020000 {
        compatible = "fsl,imx8qxp-pixel-combiner";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x56020000 0x10000>;
        clocks = <&dc0_pixel_combiner_lpcg IMX_LPCG_CLK_4>;
        clock-names = "apb";
        power-domains = <&pd IMX_SC_R_DC_0>;

        channel@0 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;

            port@0 {
                reg = <0>;

                dc0_pixel_combiner_ch0_dc0_dpu_disp0: endpoint {
                    remote-endpoint = <&dc0_dpu_disp0_dc0_pixel_combiner_ch0>;
                };
            };

            port@1 {
                reg = <1>;

                dc0_pixel_combiner_ch0_dc0_pixel_link0: endpoint {
                    remote-endpoint = <&dc0_pixel_link0_dc0_pixel_combiner_ch0>;
                };
            };
        };

        channel@1 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;

            port@0 {
                reg = <0>;

                dc0_pixel_combiner_ch1_dc0_dpu_disp1: endpoint {
                    remote-endpoint = <&dc0_dpu_disp1_dc0_pixel_combiner_ch1>;
                };
            };

            port@1 {
                reg = <1>;

                dc0_pixel_combiner_ch1_dc0_pixel_link1: endpoint {
                    remote-endpoint = <&dc0_pixel_link1_dc0_pixel_combiner_ch1>;
                };
            };
        };
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8qm/qxp Display Pixel Link

maintainers:
  - Liu Ying <victor.liu@nxp.com>

description: |
  The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
  asynchronous linkage between pixel sources(display controller or
  camera module) and pixel consumers(imaging or displays).
  It consists of two distinct functions, a pixel transfer function and a
  control interface.  Multiple pixel channels can exist per one control channel.
  This binding documentation is only for pixel links whose pixel sources are
  display controllers.

  The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
  firmware.

properties:
  compatible:
    enum:
      - fsl,imx8qm-dc-pixel-link
      - fsl,imx8qxp-dc-pixel-link

  fsl,dc-id:
    $ref: /schemas/types.yaml#/definitions/uint8
    description: |
      u8 value representing the display controller index that the pixel link
      connects to.

  fsl,dc-stream-id:
    $ref: /schemas/types.yaml#/definitions/uint8
    description: |
      u8 value representing the display controller stream index that the pixel
      link connects to.
    enum: [0, 1]

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: The pixel link input port node from upstream video source.

    patternProperties:
      "^port@[1-4]$":
        $ref: /schemas/graph.yaml#/properties/port
        description: The pixel link output port node to downstream bridge.

    required:
      - port@0
      - port@1
      - port@2
      - port@3
      - port@4

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8qxp-dc-pixel-link
    then:
      properties:
        fsl,dc-id:
          const: 0

  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8qm-dc-pixel-link
    then:
      properties:
        fsl,dc-id:
          enum: [0, 1]

required:
  - compatible
  - fsl,dc-id
  - fsl,dc-stream-id
  - ports

additionalProperties: false

examples:
  - |
    dc0-pixel-link0 {
        compatible = "fsl,imx8qxp-dc-pixel-link";
        fsl,dc-id = /bits/ 8 <0>;
        fsl,dc-stream-id = /bits/ 8 <0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            /* from dc0 pixel combiner channel0 */
            port@0 {
                reg = <0>;

                dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
                    remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
                };
            };

            /* to PXL2DPIs in MIPI/LVDS combo subsystems */
            port@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;

                dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
                };

                dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
                };
            };

            /* unused */
            port@2 {
                reg = <2>;
            };

            /* unused */
            port@3 {
                reg = <3>;
            };

            /* to imaging subsystem */
            port@4 {
                reg = <4>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface

maintainers:
  - Liu Ying <victor.liu@nxp.com>

description: |
  The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
  interfaces the pixel link 36-bit data output and the DSI controller’s
  MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
  used in LVDS mode, to remap the pixel color codings between those modules.
  This module is purely combinatorial.

  The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
  The CSR module, as a system controller, contains the PXL2DPI's configuration
  register.

properties:
  compatible:
    const: fsl,imx8qxp-pxl2dpi

  fsl,sc-resource:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The SCU resource ID associated with this PXL2DPI instance.

  power-domains:
    maxItems: 1

  fsl,companion-pxl2dpi:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      A phandle which points to companion PXL2DPI which is used by downstream
      LVDS Display Bridge(LDB) in split mode.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: The PXL2DPI input port node from pixel link.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: The PXL2DPI output port node to downstream bridge.

    required:
      - port@0
      - port@1

required:
  - compatible
  - fsl,sc-resource
  - power-domains
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/firmware/imx/rsrc.h>
    pxl2dpi {
        compatible = "fsl,imx8qxp-pxl2dpi";
        fsl,sc-resource = <IMX_SC_R_MIPI_0>;
        power-domains = <&pd IMX_SC_R_MIPI_0>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;

                mipi_lvds_0_pxl2dpi_dc_pixel_link0: endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&dc_pixel_link0_mipi_lvds_0_pxl2dpi>;
                };

                mipi_lvds_0_pxl2dpi_dc_pixel_link1: endpoint@1 {
                     reg = <1>;
                     remote-endpoint = <&dc_pixel_link1_mipi_lvds_0_pxl2dpi>;
                };
            };

            port@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;

                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
                    reg = <0>;
                    remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
                };

                mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
                    reg = <1>;
                    remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,ldb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8MP DPI to LVDS bridge chip

maintainers:
  - Marek Vasut <marex@denx.de>

description: |
  The i.MX8MP mediamix contains two registers which are responsible
  for configuring the on-SoC DPI-to-LVDS serializer. This describes
  those registers as bridge within the DT.

properties:
  compatible:
    const: fsl,imx8mp-ldb

  clocks:
    maxItems: 1

  clock-names:
    const: ldb

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: ldb
      - const: lvds

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Video port for DPI input.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Video port for LVDS Channel-A output (panel or bridge).

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: Video port for LVDS Channel-B output (panel or bridge).

    required:
      - port@0
      - port@1

required:
  - compatible
  - clocks
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mp-clock.h>

    blk-ctrl {
        #address-cells = <1>;
        #size-cells = <1>;

        bridge@5c {
            compatible = "fsl,imx8mp-ldb";
            clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
            clock-names = "ldb";
            reg = <0x5c 0x4>, <0x128 0x4>;
            reg-names = "ldb", "lvds";

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;

                    ldb_from_lcdif2: endpoint {
                        remote-endpoint = <&lcdif2_to_ldb>;
                    };
                };

                port@1 {
                    reg = <1>;

                    ldb_lvds_ch0: endpoint {
                        remote-endpoint = <&ldb_to_lvdsx4panel>;
                    };
                };

                port@2 {
                    reg = <2>;

                    ldb_lvds_ch1: endpoint {
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/google,cros-ec-anx7688.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port

maintainers:
  - Nicolas Boichat <drinkcat@chromium.org>

description: |
  ChromeOS EC ANX7688 is a display bridge that converts HDMI 2.0 to
  DisplayPort 1.3 Ultra-HDi (4096x2160p60). It is an Analogix ANX7688 chip
  which is connected to and operated by the ChromeOS Embedded Controller
  (See google,cros-ec.yaml). It is accessed using I2C tunneling through
  the EC and therefore its node should be a child of an EC I2C tunnel node
  (See google,cros-ec-i2c-tunnel.yaml).

properties:
  compatible:
    const: google,cros-ec-anx7688

  reg:
    maxItems: 1
    description: I2C address of the device.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Video port for HDMI input.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: USB Type-c connector.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - ports

additionalProperties: false

examples:
  - |
    i2c_tunnel_b: i2c-tunnel1 {
        compatible = "google,cros-ec-i2c-tunnel";
        google,remote-bus = <1>;
        #address-cells = <1>;
        #size-cells = <0>;

        anx7688: anx7688@2c {
            compatible = "google,cros-ec-anx7688";
            reg = <0x2c>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;
                port@0 {
                    reg = <0>;
                    anx7688_in: endpoint {
                        remote-endpoint = <&hdmi0_out>;
                    };
                };
                port@1 {
                    reg = <1>;
                    anx7688_out: endpoint {
                        remote-endpoint = <&typec_connector>;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ingenic,jz4780-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Bindings for Ingenic JZ4780 HDMI Transmitter

maintainers:
  - H. Nikolaus Schaller <hns@goldelico.com>

description: |
  The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4
  TX controller IP with accompanying PHY IP.

allOf:
  - $ref: synopsys,dw-hdmi.yaml#

properties:
  compatible:
    const: ingenic,jz4780-dw-hdmi

  reg-io-width:
    const: 4

  clocks:
    maxItems: 2

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Input from LCD controller output.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Link to the HDMI connector.

required:
  - compatible
  - clocks
  - clock-names
  - ports
  - reg-io-width

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>

    hdmi: hdmi@10180000 {
        compatible = "ingenic,jz4780-dw-hdmi";
        reg = <0x10180000 0x8000>;
        reg-io-width = <4>;
        interrupt-parent = <&intc>;
        interrupts = <3>;
        clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
        clock-names = "iahb", "isfr";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            hdmi_in: port@0 {
                reg = <0>;
                dw_hdmi_in: endpoint {
                    remote-endpoint = <&jz4780_lcd_out>;
                };
            };
            hdmi_out: port@1 {
                reg = <1>;
                dw_hdmi_out: endpoint {
                    remote-endpoint = <&hdmi_con>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/intel,keembay-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Devicetree bindings for Intel Keem Bay mipi dsi controller

maintainers:
  - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
  - Edmond J Dea <edmund.j.dea@intel.com>

properties:
  compatible:
    const: intel,keembay-dsi

  reg:
    items:
      - description: MIPI registers range

  reg-names:
    items:
      - const: mipi

  clocks:
    items:
      - description: MIPI DSI clock
      - description: MIPI DSI econfig clock
      - description: MIPI DSI config clock

  clock-names:
    items:
      - const: clk_mipi
      - const: clk_mipi_ecfg
      - const: clk_mipi_cfg

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: MIPI DSI input port.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: DSI output port.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - ports

additionalProperties: false

examples:
  - |
    mipi-dsi@20900000 {
        compatible = "intel,keembay-dsi";
        reg = <0x20900000 0x4000>;
        reg-names = "mipi";
        clocks = <&scmi_clk 0x86>,
                 <&scmi_clk 0x88>,
                 <&scmi_clk 0x89>;
        clock-names = "clk_mipi", "clk_mipi_ecfg",
                      "clk_mipi_cfg";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                dsi_in: endpoint {
                    remote-endpoint = <&disp_out>;
                };
            };

            port@1 {
                reg = <1>;
                dsi_out: endpoint {
                    remote-endpoint = <&adv7535_input>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ite,it6505.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ITE it6505 Device Tree Bindings

maintainers:
  - Allen Chen <allen.chen@ite.com.tw>

description: |
  The IT6505 is a high-performance DisplayPort 1.1a transmitter,
  fully compliant with DisplayPort 1.1a, HDCP 1.3 specifications.
  The IT6505 supports color depth of up to 36 bits (12 bits/color)
  and ensures robust transmission of high-quality uncompressed video
  content, along with uncompressed and compressed digital audio content.

  Aside from the various video output formats supported, the IT6505
  also encodes and transmits up to 8 channels of I2S digital audio,
  with sampling rate up to 192kHz and sample size up to 24 bits.
  In addition, an S/PDIF input port takes in compressed audio of up to
  192kHz frame rate.

  Each IT6505 chip comes preprogrammed with an unique HDCP key,
  in compliance with the HDCP 1.3 standard so as to provide secure
  transmission of high-definition content. Users of the IT6505 need not
  purchase any HDCP keys or ROMs.

properties:
  compatible:
    const: ite,it6505

  reg:
    maxItems: 1

  ovdd-supply:
    description: I/O voltage

  pwr18-supply:
    description: core voltage

  interrupts:
    maxItems: 1
    description: interrupt specifier of INT pin

  reset-gpios:
    maxItems: 1
    description: gpio specifier of RESET pin

  extcon:
    maxItems: 1
    description: extcon specifier for the Power Delivery

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description: A port node pointing to DPI host port node

required:
  - compatible
  - ovdd-supply
  - pwr18-supply
  - interrupts
  - reset-gpios
  - extcon

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        dp-bridge@5c {
            compatible = "ite,it6505";
            interrupts = <152 IRQ_TYPE_EDGE_FALLING 152 0>;
            reg = <0x5c>;
            pinctrl-names = "default";
            pinctrl-0 = <&it6505_pins>;
            ovdd-supply = <&mt6358_vsim1_reg>;
            pwr18-supply = <&it6505_pp18_reg>;
            reset-gpios = <&pio 179 1>;
            extcon = <&usbc_extcon>;

            port {
                it6505_in: endpoint {
                    remote-endpoint = <&dpi_out>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ite,it66121.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ITE it66121 HDMI bridge Device Tree Bindings

maintainers:
  - Phong LE <ple@baylibre.com>
  - Neil Armstrong <neil.armstrong@linaro.org>

description: |
  The IT66121 is a high-performance and low-power single channel HDMI
  transmitter, fully compliant with HDMI 1.3a, HDCP 1.2 and backward compatible
  to DVI 1.0 specifications.

properties:
  compatible:
    const: ite,it66121

  reg:
    maxItems: 1

  reset-gpios:
    maxItems: 1
    description: GPIO connected to active low reset

  vrf12-supply:
    description: Regulator for 1.2V analog core power.

  vcn33-supply:
    description: Regulator for 3.3V digital core power.

  vcn18-supply:
    description: Regulator for 1.8V IO core power.

  interrupts:
    maxItems: 1

  "#sound-dai-cells":
    const: 0

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: DPI input port.

        properties:
          endpoint:
            $ref: /schemas/graph.yaml#/$defs/endpoint-base
            unevaluatedProperties: false

            properties:
              bus-width:
                description:
                  Endpoint bus width.
                enum:
                  - 12  # 12 data lines connected and dual-edge mode
                  - 24  # 24 data lines connected and single-edge mode
                default: 24

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: HDMI Connector port.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - reset-gpios
  - vrf12-supply
  - vcn33-supply
  - vcn18-supply
  - interrupts
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        it66121hdmitx: hdmitx@4c {
            compatible = "ite,it66121";
            pinctrl-names = "default";
            pinctrl-0 = <&ite_pins_default>;
            vcn33-supply = <&mt6358_vcn33_wifi_reg>;
            vcn18-supply = <&mt6358_vcn18_reg>;
            vrf12-supply = <&mt6358_vrf12_reg>;
            reset-gpios = <&pio 160 GPIO_ACTIVE_LOW>;
            interrupt-parent = <&pio>;
            interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
            reg = <0x4c>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    it66121_in: endpoint {
                        bus-width = <12>;
                        remote-endpoint = <&display_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    hdmi_conn_out: endpoint {
                        remote-endpoint = <&hdmi_conn_in>;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/lontium,lt8912b.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Lontium LT8912B MIPI to HDMI Bridge

maintainers:
  - Adrien Grassein <adrien.grassein@gmail.com>

description: |
  The LT8912B is a bridge device which convert DSI to HDMI

properties:
  compatible:
    enum:
      - lontium,lt8912b

  reg:
    maxItems: 1

  reset-gpios:
    maxItems: 1
    description: GPIO connected to active high RESET pin.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Primary MIPI port for MIPI input

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes: true

            required:
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          HDMI port, should be connected to a node compatible with the
          hdmi-connector binding.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - reset-gpios
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    i2c4 {
      #address-cells = <1>;
      #size-cells = <0>;

      hdmi-bridge@48 {
        compatible = "lontium,lt8912b";
        reg = <0x48>;
        reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>;

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;

            hdmi_out_in: endpoint {
              data-lanes = <0 1 2 3>;
              remote-endpoint = <&mipi_dsi_out>;
            };
          };

          port@1 {
              reg = <1>;

              endpoint {
                  remote-endpoint = <&hdmi_in>;
              };
          };
        };
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/lontium,lt9211.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge.

maintainers:
  - Marek Vasut <marex@denx.de>

description: |
  The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
  or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.

properties:
  compatible:
    enum:
      - lontium,lt9211

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  reset-gpios:
    maxItems: 1
    description: GPIO connected to active high RESET pin.

  vccio-supply:
    description: Regulator for 1.8V IO power.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Primary MIPI DSI port-1 for MIPI input or
          LVDS port-1 for LVDS input or DPI input.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Additional MIPI port-2 for MIPI input or LVDS port-2
          for LVDS input. Used in combination with primary
          port-1 to drive higher resolution displays

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Primary MIPI DSI port-1 for MIPI output or
          LVDS port-1 for LVDS output or DPI output.

      port@3:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Additional MIPI port-2 for MIPI output or LVDS port-2
          for LVDS output. Used in combination with primary
          port-1 to drive higher resolution displays.

    required:
      - port@0
      - port@2

required:
  - compatible
  - reg
  - vccio-supply
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      hdmi-bridge@3b {
        compatible = "lontium,lt9211";
        reg = <0x3b>;

        reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>;
        interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>;

        vccio-supply = <&lt9211_1v8>;

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;

            endpoint {
              remote-endpoint = <&dsi0_out>;
            };
          };

          port@2 {
            reg = <2>;

            endpoint {
              remote-endpoint = <&panel_in_lvds>;
            };
          };
        };
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/lontium,lt9611.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Lontium LT9611(UXC) 2 Port MIPI to HDMI Bridge

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description: |
  The LT9611 and LT9611UXC are bridge devices which convert DSI to HDMI

properties:
  compatible:
    enum:
      - lontium,lt9611
      - lontium,lt9611uxc

  reg:
    maxItems: 1

  "#sound-dai-cells":
    const: 1

  interrupts:
    maxItems: 1

  reset-gpios:
    maxItems: 1
    description: GPIO connected to active high RESET pin.

  vdd-supply:
    description: Regulator for 1.8V MIPI phy power.

  vcc-supply:
    description: Regulator for 3.3V IO power.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Primary MIPI port-1 for MIPI input

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Additional MIPI port-2 for MIPI input, used in combination
          with primary MIPI port-1 to drive higher resolution displays

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          HDMI port for HDMI output

    required:
      - port@0
      - port@2

required:
  - compatible
  - reg
  - interrupts
  - vdd-supply
  - vcc-supply
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c10 {
      #address-cells = <1>;
      #size-cells = <0>;

      hdmi-bridge@3b {
        compatible = "lontium,lt9611";
        reg = <0x3b>;

        reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>;
        interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>;

        vdd-supply = <&lt9611_1v8>;
        vcc-supply = <&lt9611_3v3>;

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;
            lt9611_a: endpoint {
              remote-endpoint = <&dsi0_out>;
            };
          };

          port@1 {
            reg = <1>;
            lt9611_b: endpoint {
              remote-endpoint = <&dsi1_out>;
            };
          };

          port@2 {
            reg = <2>;
            lt9611_out: endpoint {
              remote-endpoint = <&hdmi_con>;
            };
          };
        };
      };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/lvds-codec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Transparent LVDS encoders and decoders

maintainers:
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

description: |
  This binding supports transparent LVDS encoders and decoders that don't
  require any configuration.

  LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
  incompatible data link layers have been used over time to transmit image data
  to LVDS panels. This binding targets devices compatible with the following
  specifications only.

  [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
  1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
  [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
  Semiconductor
  [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
  Electronics Standards Association (VESA)

  Those devices have been marketed under the FPD-Link and FlatLink brand names
  among others.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - ti,ds90c185   # For the TI DS90C185 FPD-Link Serializer
              - ti,ds90c187   # For the TI DS90C187 FPD-Link Serializer
              - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter
          - const: lvds-encoder # Generic LVDS encoder compatible fallback
      - items:
          - enum:
              - ti,ds90cf364a # For the DS90CF364A FPD-Link LVDS Receiver
              - ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver
          - const: lvds-decoder # Generic LVDS decoders compatible fallback
      - enum:
          - thine,thc63lvdm83d # For the THC63LVDM83D LVDS serializer

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: |
          For LVDS encoders, port 0 is the parallel input
          For LVDS decoders, port 0 is the LVDS input

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-mapping:
                enum:
                  - jeida-18
                  - jeida-24
                  - vesa-24
                description: |
                  The color signals mapping order. See details in
                  Documentation/devicetree/bindings/display/lvds.yaml

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          For LVDS encoders, port 1 is the LVDS output
          For LVDS decoders, port 1 is the parallel output

    required:
      - port@0
      - port@1

  pclk-sample:
    description:
      Data sampling on rising or falling edge.
    enum:
      - 0  # Falling edge
      - 1  # Rising edge
    default: 0

  powerdown-gpios:
    description:
      The GPIO used to control the power down line of this device.
    maxItems: 1

  power-supply: true

allOf:
  - if:
      not:
        properties:
          compatible:
            contains:
              const: lvds-decoder
    then:
      properties:
        ports:
          properties:
            port@0:
              properties:
                endpoint:
                  properties:
                    data-mapping: false

  - if:
      not:
        properties:
          compatible:
            contains:
              const: lvds-encoder
    then:
      properties:
        pclk-sample: false

required:
  - compatible
  - ports

additionalProperties: false

examples:
  - |
    lvds-encoder {
      compatible = "ti,ds90c185", "lvds-encoder";

      ports {
        #address-cells = <1>;
        #size-cells = <0>;

        port@0 {
          reg = <0>;

          lvds_enc_in: endpoint {
            remote-endpoint = <&display_out_rgb>;
          };
        };

        port@1 {
          reg = <1>;

          lvds_enc_out: endpoint {
            remote-endpoint = <&lvds_panel_in>;
          };
        };
      };
    };

  - |
    lvds-decoder {
      compatible = "ti,ds90cf384a", "lvds-decoder";

      ports {
        #address-cells = <1>;
        #size-cells = <0>;

        port@0 {
          reg = <0>;

          lvds_dec_in: endpoint {
            remote-endpoint = <&display_out_lvds>;
          };
        };

        port@1 {
          reg = <1>;

          lvds_dec_out: endpoint {
            remote-endpoint = <&rgb_panel_in>;
          };
        };
      };
    };

...


code:
Drivers for the second video output of the GE B850v3:
   STDP4028-ge-b850v3-fw bridges (LVDS-DP)
   STDP2690-ge-b850v3-fw bridges (DP-DP++)

The video processing pipeline on the second output on the GE B850v3:

   Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output

Each bridge has a dedicated flash containing firmware for supporting the custom
design. The result is that, in this design, neither the STDP4028 nor the
STDP2690 behave as the stock bridges would. The compatible strings include the
suffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with
the firmware specific for the GE B850v3.

The hardware do not provide control over the video processing pipeline, as the
two bridges behaves as a single one. The only interfaces exposed by the
hardware are EDID, HPD, and interrupts.

stdp4028-ge-b850v3-fw required properties:
  - compatible : "megachips,stdp4028-ge-b850v3-fw"
  - reg : I2C bus address
  - interrupts : one interrupt should be described here, as in
    <0 IRQ_TYPE_LEVEL_HIGH>
  - ports : One input port(reg = <0>) and one output port(reg = <1>)

stdp2690-ge-b850v3-fw required properties:
    compatible : "megachips,stdp2690-ge-b850v3-fw"
  - reg : I2C bus address
  - ports : One input port(reg = <0>) and one output port(reg = <1>)

Example:

&mux2_i2c2 {
	clock-frequency = <100000>;

	stdp4028@73 {
		compatible = "megachips,stdp4028-ge-b850v3-fw";
		#address-cells = <1>;
		#size-cells = <0>;

		reg = <0x73>;

		interrupt-parent = <&gpio2>;
		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				stdp4028_in: endpoint {
					remote-endpoint = <&lvds0_out>;
				};
			};
			port@1 {
				reg = <1>;
				stdp4028_out: endpoint {
					remote-endpoint = <&stdp2690_in>;
				};
			};
		};
	};

	stdp2690@72 {
		compatible = "megachips,stdp2690-ge-b850v3-fw";
		#address-cells = <1>;
		#size-cells = <0>;

		reg = <0x72>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				stdp2690_in: endpoint {
					remote-endpoint = <&stdp4028_out>;
				};
			};

			port@1 {
				reg = <1>;
				stdp2690_out: endpoint {
					/* Connector for external display */
				};
			};
		};
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Northwest Logic MIPI-DSI controller on i.MX SoCs

maintainers:
  - Guido Gúnther <agx@sigxcpu.org>
  - Robert Chiras <robert.chiras@nxp.com>

description: |
  NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
  the SOCs NWL MIPI-DSI host controller.

allOf:
  - $ref: ../dsi-controller.yaml#

properties:
  compatible:
    const: fsl,imx8mq-nwl-dsi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  assigned-clock-parents: true
  assigned-clock-rates: true
  assigned-clocks: true

  clocks:
    items:
      - description: DSI core clock
      - description: RX_ESC clock (used in escape mode)
      - description: TX_ESC clock (used in escape mode)
      - description: PHY_REF clock
      - description: LCDIF clock

  clock-names:
    items:
      - const: core
      - const: rx_esc
      - const: tx_esc
      - const: phy_ref
      - const: lcdif

  mux-controls:
    description:
      mux controller node to use for operating the input mux

  phys:
    maxItems: 1
    description:
      A phandle to the phy module representing the DPHY

  phy-names:
    items:
      - const: dphy

  power-domains:
    maxItems: 1

  resets:
    items:
      - description: dsi byte reset line
      - description: dsi dpi reset line
      - description: dsi esc reset line
      - description: dsi pclk reset line

  reset-names:
    items:
      - const: byte
      - const: dpi
      - const: esc
      - const: pclk

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        description:
          Input port node to receive pixel data from the
          display controller. Exactly one endpoint must be
          specified.
        properties:
          endpoint@0:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: sub-node describing the input from LCDIF

          endpoint@1:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: sub-node describing the input from DCSS

        oneOf:
          - required:
              - endpoint@0
          - required:
              - endpoint@1

        unevaluatedProperties: false

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          DSI output port node to the panel or the next bridge
          in the chain

    required:
      - port@0
      - port@1

required:
  - '#address-cells'
  - '#size-cells'
  - clock-names
  - clocks
  - compatible
  - interrupts
  - mux-controls
  - phy-names
  - phys
  - ports
  - reg
  - reset-names
  - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mq-clock.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/reset/imx8mq-reset.h>

    dsi@30a00000 {
              #address-cells = <1>;
              #size-cells = <0>;
              compatible = "fsl,imx8mq-nwl-dsi";
              reg = <0x30A00000 0x300>;
              clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
                       <&clk IMX8MQ_CLK_DSI_AHB>,
                       <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
                       <&clk IMX8MQ_CLK_DSI_PHY_REF>,
                       <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
              clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
              interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
              mux-controls = <&mux 0>;
              power-domains = <&pgc_mipi>;
              resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
                       <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
                       <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
                       <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
              reset-names = "byte", "dpi", "esc", "pclk";
              phys = <&dphy>;
              phy-names = "dphy";

              panel@0 {
                      compatible = "rocktech,jh057n00900";
                      reg = <0>;
                      vcc-supply = <&reg_2v8_p>;
                      iovcc-supply = <&reg_1v8_p>;
                      reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
                      port {
                           panel_in: endpoint {
                                     remote-endpoint = <&mipi_dsi_out>;
                           };
                      };
              };

              ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@0 {
                           #size-cells = <0>;
                           #address-cells = <1>;
                           reg = <0>;
                           mipi_dsi_in: endpoint@0 {
                                        reg = <0>;
                                        remote-endpoint = <&lcdif_mipi_dsi>;
                           };
                    };
                    port@1 {
                           reg = <1>;
                           mipi_dsi_out: endpoint {
                                         remote-endpoint = <&panel_in>;
                           };
                    };
              };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/nxp,ptn3460.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP PTN3460 eDP to LVDS bridge

maintainers:
  - Sean Paul <seanpaul@chromium.org>

properties:
  compatible:
    const: nxp,ptn3460

  reg:
    description: I2C address of the bridge
    maxItems: 1

  edid-emulation:
    $ref: "/schemas/types.yaml#/definitions/uint32"
    description:
      The EDID emulation entry to use
      Value  Resolution  Description
        0     1024x768   NXP Generic
        1     1920x1080  NXP Generic
        2     1920x1080  NXP Generic
        3     1600x900   Samsung LTM200KT
        4     1920x1080  Samsung LTM230HT
        5     1366x768   NXP Generic
        6     1600x900   ChiMei M215HGE
    enum: [0, 1, 2, 3, 4, 5, 6]

  powerdown-gpios:
    description: GPIO connected to the PD_N signal.
    maxItems: 1

  reset-gpios:
    description: GPIO connected to the RST_N signal.
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for LVDS output

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for eDP input

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - edid-emulation
  - powerdown-gpios
  - reset-gpios
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    i2c1 {
      #address-cells = <1>;
      #size-cells = <0>;

      bridge@20 {
        compatible = "nxp,ptn3460";
        reg = <0x20>;
        edid-emulation = <5>;
        powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>;
        reset-gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;
            bridge_out: endpoint {
              remote-endpoint = <&panel_in>;
            };
          };

          port@1 {
            reg = <1>;
            bridge_in: endpoint {
              remote-endpoint = <&dp_out>;
            };
          };
        };
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/nxp,tda998x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP TDA998x HDMI transmitter

maintainers:
  - Russell King <linux@armlinux.org.uk>

properties:
  compatible:
    const: nxp,tda998x

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  video-ports:
    default: 0x230145
    maximum: 0xffffff
    description:
      24 bits value which defines how the video controller output is wired to
      the TDA998x input.

  audio-ports:
    description:
      Array of 8-bit values, 2 values per DAI (Documentation/sound/soc/dai.rst).
      The implementation allows one or two DAIs.
      If two DAIs are defined, they must be of different type.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    items:
      minItems: 1
      items:
        - description: |
            The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S
            (see include/dt-bindings/display/tda998x.h).
        - description:
            The second value defines the tda998x AP_ENA reg content when the
            DAI in question is used.

  '#sound-dai-cells':
    enum: [ 0, 1 ]

  nxp,calib-gpios:
    maxItems: 1
    description:
      Calibration GPIO, which must correspond with the gpio used for the
      TDA998x interrupt pin.

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description: Parallel input port

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        type: object
        description: Parallel input port

      port@1:
        type: object
        description: HDMI output port

required:
  - compatible
  - reg

oneOf:
  - required:
      - port
  - required:
      - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/display/tda998x.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        tda998x: hdmi-encoder@70 {
            compatible = "nxp,tda998x";
            reg = <0x70>;
            interrupt-parent = <&gpio0>;
            interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
            video-ports = <0x230145>;

            #sound-dai-cells = <1>;
                         /* DAI-format / AP_ENA reg value */
            audio-ports = <TDA998x_SPDIF 0x04>,
                          <TDA998x_I2S 0x03>;

            port {
                tda998x_in: endpoint {
                    remote-endpoint = <&lcdc_0>;
                };
            };
        };
    };


code:
ps8622-bridge bindings

Required properties:
	- compatible: "parade,ps8622" or "parade,ps8625"
	- reg: first i2c address of the bridge
	- sleep-gpios: OF device-tree gpio specification for PD_ pin.
	- reset-gpios: OF device-tree gpio specification for RST_ pin.

Optional properties:
	- lane-count: number of DP lanes to use
	- use-external-pwm: backlight will be controlled by an external PWM
	- video interfaces: Device node can contain video interface port
			    nodes for panel according to [1].

[1]: Documentation/devicetree/bindings/media/video-interfaces.txt

Example:
	lvds-bridge@48 {
		compatible = "parade,ps8622";
		reg = <0x48>;
		sleep-gpios = <&gpc3 6 1 0 0>;
		reset-gpios = <&gpc3 1 1 0 0>;
		lane-count = <1>;
		ports {
			port@0 {
				bridge_out: endpoint {
					remote-endpoint = <&panel_in>;
				};
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ps8640.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MIPI DSI to eDP Video Format Converter Device Tree Bindings

maintainers:
  - Nicolas Boichat <drinkcat@chromium.org>

description: |
  The PS8640 is a low power MIPI-to-eDP video format converter supporting
  mobile devices with embedded panel resolutions up to 2048 x 1536. The
  device accepts a single channel of MIPI DSI v1.1, with up to four lanes
  plus clock, at a transmission rate up to 1.5Gbit/sec per lane. The
  device outputs eDP v1.4, one or two lanes, at a link rate of up to
  3.24Gbit/sec per lane.

properties:
  compatible:
    const: parade,ps8640

  reg:
    maxItems: 1
    description: Base I2C address of the device.

  powerdown-gpios:
    maxItems: 1
    description: GPIO connected to active low powerdown.

  reset-gpios:
    maxItems: 1
    description: GPIO connected to active low reset.

  vdd12-supply:
    description: Regulator for 1.2V digital core power.

  vdd33-supply:
    description: Regulator for 3.3V digital core power.

  aux-bus:
    $ref: /schemas/display/dp-aux-bus.yaml#

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for DSI input

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for eDP output (panel or connector).

    required:
      - port@0

required:
  - compatible
  - reg
  - powerdown-gpios
  - reset-gpios
  - vdd12-supply
  - vdd33-supply
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        ps8640: edp-bridge@18 {
            compatible = "parade,ps8640";
            reg = <0x18>;
            powerdown-gpios = <&pio 116 GPIO_ACTIVE_LOW>;
            reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
            vdd12-supply = <&ps8640_fixed_1v2>;
            vdd33-supply = <&mt6397_vgp2_reg>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    ps8640_in: endpoint {
                        remote-endpoint = <&dsi0_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    ps8640_out: endpoint {
                        remote-endpoint = <&panel_in>;
                    };
                };
            };

            aux-bus {
                panel {
                    compatible = "boe,nv133fhm-n62";
                    power-supply = <&pp3300_dx_edp>;
                    backlight = <&backlight>;

                    port {
                        panel_in: endpoint {
                            remote-endpoint = <&ps8640_out>;
                        };
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car MIPI DSI/CSI-2 Encoder

maintainers:
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

description: |
  This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
  R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up
  to four data lanes.

properties:
  compatible:
    enum:
      - renesas,r8a779a0-dsi-csi2-tx    # for V3U

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Functional clock
      - description: DSI (and CSI-2) functional clock
      - description: PLL reference clock

  clock-names:
    items:
      - const: fck
      - const: dsi
      - const: pll

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Parallel input port

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: DSI/CSI-2 output port

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - clocks
  - power-domains
  - resets
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
    #include <dt-bindings/power/r8a779a0-sysc.h>

    dsi0: dsi-encoder@fed80000 {
        compatible = "renesas,r8a779a0-dsi-csi2-tx";
        reg = <0xfed80000 0x10000>;
        power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
        clocks = <&cpg CPG_MOD 415>,
                 <&cpg CPG_CORE R8A779A0_CLK_DSI>,
                 <&cpg CPG_CORE R8A779A0_CLK_CP>;
        clock-names = "fck", "dsi", "pll";
        resets = <&cpg 415>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                dsi0_in: endpoint {
                    remote-endpoint = <&du_out_dsi0>;
                };
            };

            port@1 {
                reg = <1>;
                dsi0_out: endpoint {
                    data-lanes = <1 2>;
                    remote-endpoint = <&sn65dsi86_in>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G2L MIPI DSI Encoder

maintainers:
  - Biju Das <biju.das.jz@bp.renesas.com>

description: |
  This binding describes the MIPI DSI encoder embedded in the Renesas
  RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
  up to four data lanes.

allOf:
  - $ref: /schemas/display/dsi-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
      - const: renesas,rzg2l-mipi-dsi

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: Sequence operation channel 0 interrupt
      - description: Sequence operation channel 1 interrupt
      - description: Video-Input operation channel 1 interrupt
      - description: DSI Packet Receive interrupt
      - description: DSI Fatal Error interrupt
      - description: DSI D-PHY PPI interrupt
      - description: Debug interrupt

  interrupt-names:
    items:
      - const: seq0
      - const: seq1
      - const: vin1
      - const: rcv
      - const: ferr
      - const: ppi
      - const: debug

  clocks:
    items:
      - description: DSI D-PHY PLL multiplied clock
      - description: DSI D-PHY system clock
      - description: DSI AXI bus clock
      - description: DSI Register access clock
      - description: DSI Video clock
      - description: DSI D-PHY Escape mode transmit clock

  clock-names:
    items:
      - const: pllclk
      - const: sysclk
      - const: aclk
      - const: pclk
      - const: vclk
      - const: lpclk

  resets:
    items:
      - description: MIPI_DSI_CMN_RSTB
      - description: MIPI_DSI_ARESET_N
      - description: MIPI_DSI_PRESET_N

  reset-names:
    items:
      - const: rst
      - const: arst
      - const: prst

  power-domains:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Parallel input port

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: DSI output port

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description: array of physical DSI data lane indexes.
                minItems: 1
                items:
                  - const: 1
                  - const: 2
                  - const: 3
                  - const: 4

            required:
              - data-lanes

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - resets
  - reset-names
  - power-domains
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r9a07g044-cpg.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    dsi0: dsi@10850000 {
        compatible = "renesas,r9a07g044-mipi-dsi", "renesas,rzg2l-mipi-dsi";
        reg = <0x10850000 0x20000>;
        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "seq0", "seq1", "vin1", "rcv",
                          "ferr", "ppi", "debug";
        clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
                 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
        clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
        resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
                 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
                 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
        reset-names = "rst", "arst", "prst";
        power-domains = <&cpg>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                dsi0_in: endpoint {
                    remote-endpoint = <&du_out_dsi0>;
                };
            };

            port@1 {
                reg = <1>;
                dsi0_out: endpoint {
                    data-lanes = <1 2 3 4>;
                    remote-endpoint = <&adv7535_in>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car DWC HDMI TX Encoder

maintainers:
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

description: |
  The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
  with a companion PHY IP.

allOf:
  - $ref: synopsys,dw-hdmi.yaml#

properties:
  compatible:
    items:
      - enum:
          - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
          - renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX
          - renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX
          - renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX
          - renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX
          - renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX
          - renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX
      - const: renesas,rcar-gen3-hdmi

  reg-io-width:
    const: 1

  clocks:
    maxItems: 2

  clock-names:
    maxItems: 2

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Parallel RGB input port

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: HDMI output port

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: Sound input port

    required:
      - port@0
      - port@1
      - port@2

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - interrupts
  - ports

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    hdmi@fead0000 {
        compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
        reg = <0xfead0000 0x10000>;
        interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
        clock-names = "iahb", "isfr";
        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
        resets = <&cpg 729>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@0 {
                reg = <0>;
                dw_hdmi0_in: endpoint {
                    remote-endpoint = <&du_out_hdmi0>;
                };
            };
            port@1 {
                reg = <1>;
                rcar_dw_hdmi0_out: endpoint {
                    remote-endpoint = <&hdmi0_con>;
                };
            };
            port@2 {
                reg = <2>;
                rcar_dw_hdmi0_sound_in: endpoint {
                    remote-endpoint = <&hdmi_sound_out>;
                };
            };
        };
    };

    hdmi0-out {
        compatible = "hdmi-connector";
        label = "HDMI0 OUT";
        type = "a";

        port {
            hdmi0_con: endpoint {
                remote-endpoint = <&rcar_dw_hdmi0_out>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/renesas,lvds.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car LVDS Encoder

maintainers:
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

description: |
  These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
  Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.

properties:
  compatible:
    enum:
      - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
      - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
      - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
      - renesas,r8a774a1-lvds # for RZ/G2M compatible LVDS encoders
      - renesas,r8a774b1-lvds # for RZ/G2N compatible LVDS encoders
      - renesas,r8a774c0-lvds # for RZ/G2E compatible LVDS encoders
      - renesas,r8a774e1-lvds # for RZ/G2H compatible LVDS encoders
      - renesas,r8a7790-lvds # for R-Car H2 compatible LVDS encoders
      - renesas,r8a7791-lvds # for R-Car M2-W compatible LVDS encoders
      - renesas,r8a7793-lvds # for R-Car M2-N compatible LVDS encoders
      - renesas,r8a7795-lvds # for R-Car H3 compatible LVDS encoders
      - renesas,r8a7796-lvds # for R-Car M3-W compatible LVDS encoders
      - renesas,r8a77961-lvds # for R-Car M3-W+ compatible LVDS encoders
      - renesas,r8a77965-lvds # for R-Car M3-N compatible LVDS encoders
      - renesas,r8a77970-lvds # for R-Car V3M compatible LVDS encoders
      - renesas,r8a77980-lvds # for R-Car V3H compatible LVDS encoders
      - renesas,r8a77990-lvds # for R-Car E3 compatible LVDS encoders
      - renesas,r8a77995-lvds # for R-Car D3 compatible LVDS encoders

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 4

  clock-names:
    minItems: 1
    maxItems: 4

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Parallel RGB input port

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: LVDS output port

    required:
      - port@0
      - port@1

  power-domains:
    maxItems: 1

  renesas,companion:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle to the companion LVDS encoder. This property is mandatory
      for the first LVDS encoder on R-Car D3 and E3, and RZ/G2E SoCs, and shall
      point to the second encoder to be used as a companion in dual-link mode.
      It shall not be set for any other LVDS encoder.

required:
  - compatible
  - reg
  - clocks
  - power-domains
  - resets
  - ports

if:
  properties:
    compatible:
      enum:
        - renesas,r8a774c0-lvds
        - renesas,r8a77990-lvds
        - renesas,r8a77995-lvds
then:
  properties:
    clocks:
      minItems: 1
      items:
        - description: Functional clock
        - description: EXTAL input clock
        - description: DU_DOTCLKIN0 input clock
        - description: DU_DOTCLKIN1 input clock

    clock-names:
      minItems: 1
      items:
        - const: fck
        # The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
        # These clocks are optional.
        - enum:
            - extal
            - dclkin.0
            - dclkin.1
        - enum:
            - extal
            - dclkin.0
            - dclkin.1
        - enum:
            - extal
            - dclkin.0
            - dclkin.1

  required:
    - clock-names

else:
  properties:
    clocks:
      items:
        - description: Functional clock

    clock-names:
      items:
        - const: fck

    renesas,companion: false

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/renesas-cpg-mssr.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    lvds@feb90000 {
        compatible = "renesas,r8a7795-lvds";
        reg = <0xfeb90000 0x14>;
        clocks = <&cpg CPG_MOD 727>;
        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
        resets = <&cpg 727>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                lvds_in: endpoint {
                    remote-endpoint = <&du_out_lvds0>;
                };
            };
            port@1 {
                reg = <1>;
                lvds_out: endpoint {
                    remote-endpoint = <&panel_in>;
                };
            };
        };
    };

  - |
    #include <dt-bindings/clock/renesas-cpg-mssr.h>
    #include <dt-bindings/power/r8a77990-sysc.h>

    lvds0: lvds@feb90000 {
        compatible = "renesas,r8a77990-lvds";
        reg = <0xfeb90000 0x20>;
        clocks = <&cpg CPG_MOD 727>,
                 <&x13_clk>,
                 <&extal_clk>;
        clock-names = "fck", "dclkin.0", "extal";
        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
        resets = <&cpg 727>;

        renesas,companion = <&lvds1>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                lvds0_in: endpoint {
                    remote-endpoint = <&du_out_lvds0>;
                };
            };
            port@1 {
                reg = <1>;
                lvds0_out: endpoint {
                    remote-endpoint = <&panel_in1>;
                };
            };
        };
    };

    lvds1: lvds@feb90100 {
        compatible = "renesas,r8a77990-lvds";
        reg = <0xfeb90100 0x20>;
        clocks = <&cpg CPG_MOD 727>,
                 <&x13_clk>,
                 <&extal_clk>;
        clock-names = "fck", "dclkin.0", "extal";
        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
        resets = <&cpg 726>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                lvds1_in: endpoint {
                    remote-endpoint = <&du_out_lvds1>;
                };
            };
            port@1 {
                reg = <1>;
                lvds1_out: endpoint {
                    remote-endpoint = <&panel_in2>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/sil,sii9022.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Silicon Image sii902x HDMI bridge

maintainers:
  - Boris Brezillon <bbrezillon@kernel.org>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - sil,sii9022-cpi # CEC Programming Interface
              - sil,sii9022-tpi # Transmitter Programming Interface
          - const: sil,sii9022
      - const: sil,sii9022

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1
    description: Interrupt line used to inform the host about hotplug events.

  reset-gpios:
    maxItems: 1

  iovcc-supply:
    description: I/O Supply Voltage (1.8V or 3.3V)

  cvcc12-supply:
    description: Digital Core Supply Voltage (1.2V)

  '#sound-dai-cells':
    enum: [ 0, 1 ]
    description: |
      <0> if only I2S or S/PDIF pin is wired,
      <1> if both are wired.
      HDMI audio is configured only if this property is found.
      If HDMI audio is configured, the sii902x device becomes an I2S and/or
      S/PDIF audio codec component (e.g. a digital audio sink), that can be
      used in configuring full audio devices with simple-card or
      audio-graph-card bindings. See their binding documents on how to describe
      the way the
      sii902x device is connected to the rest of the audio system:
      Documentation/devicetree/bindings/sound/simple-card.yaml
      Documentation/devicetree/bindings/sound/audio-graph-card.yaml
      Note: In case of the audio-graph-card binding the used port index should
      be 3.

  sil,i2s-data-lanes:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 4
    uniqueItems: true
    items:
      enum: [ 0, 1, 2, 3 ]
    description:
      Each integer indicates which I2S pin is connected to which audio FIFO.
      The first integer selects the I2S audio pin for the first audio FIFO#0
      (HDMI channels 1&2), the second for FIFO#1 (HDMI channels 3&4), and so
      on. There are 4 FIFOs and 4 I2S pins (SD0 - SD3). Any I2S pin can be
      connected to any FIFO, but there can be no gaps. E.g. an I2S pin must be
      mapped to FIFO#0 and FIFO#1 before mapping a channel to FIFO#2. The
      default value is <0>, describing SD0 pin being routed to HDMI audio
      FIFO#0.

  clocks:
    maxItems: 1
    description: MCLK input. MCLK can be used to produce HDMI audio CTS values.

  clock-names:
    const: mclk

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Parallel RGB input port

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: HDMI output port

      port@3:
        $ref: /schemas/graph.yaml#/properties/port
        description: Sound input port

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        hdmi-bridge@39 {
            compatible = "sil,sii9022";
            reg = <0x39>;
            reset-gpios = <&pioA 1 0>;
            iovcc-supply = <&v3v3_hdmi>;
            cvcc12-supply = <&v1v2_hdmi>;

            #sound-dai-cells = <0>;
            sil,i2s-data-lanes = < 0 1 2 >;
            clocks = <&mclk>;
            clock-names = "mclk";

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    bridge_in: endpoint {
                        remote-endpoint = <&dc_out>;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/sil,sii9234.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Silicon Image SiI9234 HDMI/MHL bridge

maintainers:
  - Maciej Purski <m.purski@samsung.com>

properties:
  compatible:
    const: sil,sii9234

  reg:
    description: I2C address for TPI interface
    maxItems: 1

  avcc12-supply:
    description: TMDS Analog Supply Voltage, 1.2V

  avcc33-supply:
    description: MHL/USB Switch Supply Voltage, 3.3V

  cvcc12-supply:
    description: Digital Core Supply Voltage, 1.2V

  iovcc18-supply:
    description: I/O voltage supply, 1.8V

  interrupts:
    maxItems: 1

  reset-gpios:
    description: GPIO connected to the reset pin.
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for HDMI (encoder) input

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          MHL to connector port

    required:
      - port@0

required:
  - compatible
  - reg
  - avcc12-supply
  - avcc33-supply
  - cvcc12-supply
  - iovcc18-supply
  - interrupts
  - reset-gpios
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c1 {
      #address-cells = <1>;
      #size-cells = <0>;

      bridge@39 {
        compatible = "sil,sii9234";
        reg = <0x39>;
        avcc12-supply = <&vsil12>;
        avcc33-supply = <&vcc33mhl>;
        cvcc12-supply = <&vsil12>;
        iovcc18-supply = <&vcc18mhl>;
        interrupt-parent = <&gpf3>;
        interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
        reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>;

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;
            mhl_to_hdmi: endpoint {
              remote-endpoint = <&hdmi_to_mhl>;
            };
          };

          port@1 {
            reg = <1>;
            mhl_to_connector: endpoint {
              remote-endpoint = <&connector_to_mhl>;
            };
          };
        };
      };
    };

...


code:
Silicon Image SiI8620 HDMI/MHL bridge bindings

Required properties:
	- compatible: "sil,sii8620"
	- reg: i2c address of the bridge
	- cvcc10-supply: Digital Core Supply Voltage (1.0V)
	- iovcc18-supply: I/O Supply Voltage (1.8V)
	- interrupts: interrupt specifier of INT pin
	- reset-gpios: gpio specifier of RESET pin
	- clocks, clock-names: specification and name of "xtal" clock
	- video interfaces: Device node can contain video interface port
			    node for HDMI encoder according to [1].

[1]: Documentation/devicetree/bindings/media/video-interfaces.txt

Example:
	sii8620@39 {
		reg = <0x39>;
		compatible = "sil,sii8620";
		cvcc10-supply = <&ldo36_reg>;
		iovcc18-supply = <&ldo34_reg>;
		interrupt-parent = <&gpf0>;
		interrupts = <2 0>;
		reset-gpio = <&gpv7 0 0>;
		clocks = <&pmu_system_controller 0>;
		clock-names = "xtal";

		port {
			mhl_to_hdmi: endpoint {
				remote-endpoint = <&hdmi_to_mhl>;
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/simple-bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Transparent non-programmable DRM bridges

maintainers:
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
  - Maxime Ripard <mripard@kernel.org>

description: |
  This binding supports transparent non-programmable bridges that don't require
  any configuration, with a single input and a single output.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - ti,ths8134a
              - ti,ths8134b
          - const: ti,ths8134
      - items:
          - const: corpro,gm7123
          - const: adi,adv7123
      - enum:
          - adi,adv7123
          - dumb-vga-dac
          - ti,opa362
          - ti,ths8134
          - ti,ths8135

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: The bridge input

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: The bridge output

    required:
      - port@0
      - port@1

  enable-gpios:
    maxItems: 1
    description: GPIO controlling bridge enable

  vdd-supply:
    description: Power supply for the bridge

required:
  - compatible
  - ports

additionalProperties: false

examples:
  - |
    bridge {
        compatible = "ti,ths8134a", "ti,ths8134";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                vga_bridge_in: endpoint {
                    remote-endpoint = <&tcon0_out_vga>;
                };
            };

            port@1 {
                reg = <1>;

                vga_bridge_out: endpoint {
                    remote-endpoint = <&vga_con_in>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare MIPI DSI host controller

maintainers:
  - Philippe CORNU <philippe.cornu@foss.st.com>

description: |
  This document defines device tree properties for the Synopsys DesignWare MIPI
  DSI host controller. It doesn't constitue a device tree binding specification
  by itself but is meant to be referenced by platform-specific device tree
  bindings.

  When referenced from platform device tree bindings the properties defined in
  this document are defined as follows. The platform device tree bindings are
  responsible for defining whether each property is required or optional.

allOf:
  - $ref: ../dsi-controller.yaml#

properties:
  reg:
    maxItems: 1

  clocks:
    items:
      - description: Module clock
      - description: DSI bus clock for either AHB and APB
      - description: Pixel clock for the DPI/RGB input
    minItems: 2

  clock-names:
    items:
      - const: ref
      - const: pclk
      - const: px_clk
    minItems: 2

  resets:
    maxItems: 1

  reset-names:
    const: apb

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Input node to receive pixel data.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: DSI output node to panel.

    required:
      - port@0
      - port@1

required:
  - clock-names
  - clocks
  - ports
  - reg

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common Properties for Synopsys DesignWare HDMI TX Controller

maintainers:
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

description: |
  This document defines device tree properties for the Synopsys DesignWare HDMI
  TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
  binding specification by itself but is meant to be referenced by device tree
  bindings for the platform-specific integrations of the DWC HDMI TX.

  When referenced from platform device tree bindings the properties defined in
  this document are defined as follows. The platform device tree bindings are
  responsible for defining whether each property is required or optional.

properties:
  reg:
    maxItems: 1

  reg-io-width:
    description:
      Width (in bytes) of the registers specified by the reg property.
    enum: [1, 4]
    default: 1

  clocks:
    minItems: 2
    maxItems: 5
    items:
      - description: The bus clock for either AHB and APB
      - description: The internal register configuration clock
    additionalItems: true

  clock-names:
    minItems: 2
    maxItems: 5
    items:
      - const: iahb
      - const: isfr
    additionalItems: true

  interrupts:
    maxItems: 1

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/thine,thc63lvd1024.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Thine Electronics THC63LVD1024 LVDS Decoder

maintainers:
  - Jacopo Mondi <jacopo+renesas@jmondi.org>
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

description: |
  The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS
  streams to parallel data outputs. The chip supports single/dual input/output
  modes, handling up to two LVDS input streams and up to two digital CMOS/TTL
  outputs.

  Single or dual operation mode, output data mapping and DDR output modes are
  configured through input signals and the chip does not expose any control
  bus.

properties:
  compatible:
    const: thine,thc63lvd1024

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description: |
      The device can operate in single or dual input and output modes.

      When operating in single input mode, all pixels are received on port@0,
      and port@1 shall not contain any endpoint. In dual input mode,
      even-numbered pixels are received on port@0 and odd-numbered pixels on
      port@1, and both port@0 and port@1 shall contain endpoints.

      When operating in single output mode all pixels are output from the first
      CMOS/TTL port and port@3 shall not contain any endpoint. In dual output
      mode pixels are output from both CMOS/TTL ports and both port@2 and
      port@3 shall contain endpoints.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: First LVDS input port

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Second LVDS input port

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: First digital CMOS/TTL parallel output

      port@3:
        $ref: /schemas/graph.yaml#/properties/port
        description: Second digital CMOS/TTL parallel output

    required:
      - port@0
      - port@2

  oe-gpios:
    maxItems: 1
    description: Output enable GPIO signal, pin name "OE", active high.

  powerdown-gpios:
    maxItems: 1
    description: Power down GPIO signal, pin name "/PDWN", active low.

  vcc-supply:
    description:
      Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and
      digital circuitry.

required:
  - compatible
  - ports
  - vcc-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    lvds-decoder {
        compatible = "thine,thc63lvd1024";

        vcc-supply = <&reg_lvds_vcc>;
        powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                lvds_dec_in_0: endpoint {
                    remote-endpoint = <&lvds_out>;
                };
            };

            port@2 {
                reg = <2>;

                lvds_dec_out_2: endpoint {
                    remote-endpoint = <&adv7511_in>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ti,dlpc3433.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI DLPC3433 MIPI DSI to DMD bridge

maintainers:
  - Jagan Teki <jagan@amarulasolutions.com>
  - Christopher Vollo <chris@renewoutreach.org>

description: |
  TI DLPC3433 is a MIPI DSI based display controller bridge
  for processing high resolution DMD based projectors.

  It has a flexible configuration of MIPI DSI and DPI signal
  input that produces a DMD output in RGB565, RGB666, RGB888
  formats.

  It supports upto 720p resolution with 60 and 120 Hz refresh
  rates.

properties:
  compatible:
    const: ti,dlpc3433

  reg:
    enum:
      - 0x1b
      - 0x1d

  enable-gpios:
    description: PROJ_ON pin, chip powers up PROJ_ON is high.

  vcc_intf-supply:
    description: A 1.8V/3.3V supply that power the Host I/O.

  vcc_flsh-supply:
    description: A 1.8V/3.3V supply that power the Flash I/O.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: Video port for MIPI DSI input.

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description: array of physical DSI data lane indexes.
                minItems: 1
                items:
                  - const: 1
                  - const: 2
                  - const: 3
                  - const: 4

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Video port for DMD output.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - enable-gpios
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    i2c1 {
        #address-cells = <1>;
        #size-cells = <0>;

        bridge@1b {
            compatible = "ti,dlpc3433";
            reg = <0x1b>;
            enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;

                    bridge_in_dsi: endpoint {
                        remote-endpoint = <&dsi_out_bridge>;
                        data-lanes = <1 2 3 4>;
                    };
                };

                port@1 {
                    reg = <1>;

                    bridge_out_panel: endpoint {
                        remote-endpoint = <&panel_out_bridge>;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi83.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip

maintainers:
  - Marek Vasut <marex@denx.de>

description: |
  Texas Instruments SN65DSI83 1x Single-link MIPI DSI
  to 1x Single-link LVDS
  https://www.ti.com/lit/gpn/sn65dsi83
  Texas Instruments SN65DSI84 1x Single-link MIPI DSI
  to 1x Dual-link or 2x Single-link LVDS
  https://www.ti.com/lit/gpn/sn65dsi84

properties:
  compatible:
    enum:
      - ti,sn65dsi83
      - ti,sn65dsi84

  reg:
    enum:
      - 0x2c
      - 0x2d

  enable-gpios:
    maxItems: 1
    description: GPIO specifier for bridge_en pin (active high).

  vcc-supply:
    description: A 1.8V power supply (see regulator/regulator.yaml).

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: Video port for MIPI DSI Channel-A input

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description: array of physical DSI data lane indexes.
                minItems: 1
                items:
                  - const: 1
                  - const: 2
                  - const: 3
                  - const: 4

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: Video port for MIPI DSI Channel-B input

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description: array of physical DSI data lane indexes.
                minItems: 1
                items:
                  - const: 1
                  - const: 2
                  - const: 3
                  - const: 4

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: Video port for LVDS Channel-A output (panel or bridge).

      port@3:
        $ref: /schemas/graph.yaml#/properties/port
        description: Video port for LVDS Channel-B output (panel or bridge).

    required:
      - port@0
      - port@2

required:
  - compatible
  - reg
  - ports

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: ti,sn65dsi83
    then:
      properties:
        ports:
          properties:
            port@1: false
            port@3: false

  - if:
      properties:
        compatible:
          contains:
            const: ti,sn65dsi84
    then:
      properties:
        ports:
          properties:
            port@1: false

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        bridge@2d {
            compatible = "ti,sn65dsi83";
            reg = <0x2d>;

            enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
            vcc-supply = <&reg_sn65dsi83_1v8>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;

                    endpoint {
                        remote-endpoint = <&dsi0_out>;
                        data-lanes = <1 2 3 4>;
                    };
                };

                port@2 {
                    reg = <2>;

                    endpoint {
                        remote-endpoint = <&panel_in_lvds>;
                    };
                };
            };
        };
    };