code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,9series.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Binding for Renesas 9-series I2C PCIe clock generators

description: |
  The Renesas 9-series are I2C PCIe clock generators providing
  from 1 to 20 output clocks.

  When referencing the provided clock in the DT using phandle
  and clock specifier, the following mapping applies:

  - 9FGV0241:
    0 -- DIF0
    1 -- DIF1

maintainers:
  - Marek Vasut <marex@denx.de>

properties:
  compatible:
    enum:
      - renesas,9fgv0241

  reg:
    description: I2C device address
    enum: [ 0x68, 0x6a ]

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: XTal input clock

  renesas,out-amplitude-microvolt:
    enum: [ 600000, 700000, 800000, 900000 ]
    description: Output clock signal amplitude

  renesas,out-spread-spectrum:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 100000, 99750, 99500 ]
    description: Output clock down spread in pcm (1/1000 of percent)

patternProperties:
  "^DIF[0-19]$":
    type: object
    description:
      Description of one of the outputs (DIF0..DIF19).

    properties:
      renesas,slew-rate:
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [ 2000000, 3000000 ]
        description: Output clock slew rate select in V/ns

    additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    /* 25MHz reference crystal */
    ref25: ref25m {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <25000000>;
    };

    i2c@0 {
        reg = <0x0 0x100>;
        #address-cells = <1>;
        #size-cells = <0>;

        rs9: clock-generator@6a {
            compatible = "renesas,9fgv0241";
            reg = <0x6a>;
            #clock-cells = <1>;

            clocks = <&ref25m>;

            DIF0 {
                renesas,slew-rate = <3000000>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Clock Pulse Generator (CPG)

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

description:
  The Clock Pulse Generator (CPG) generates core clocks for the SoC.  It
  includes PLLs, and fixed and variable ratio dividers.

  The CPG may also provide a Clock Domain for SoC devices, in combination with
  the CPG Module Stop (MSTP) Clocks.

properties:
  compatible:
    oneOf:
      - const: renesas,r8a73a4-cpg-clocks     # R-Mobile APE6
      - const: renesas,r8a7740-cpg-clocks     # R-Mobile A1
      - const: renesas,r8a7778-cpg-clocks     # R-Car M1
      - const: renesas,r8a7779-cpg-clocks     # R-Car H1
      - items:
          - enum:
              - renesas,r7s72100-cpg-clocks   # RZ/A1H
          - const: renesas,rz-cpg-clocks      # RZ/A1
      - const: renesas,sh73a0-cpg-clocks      # SH-Mobile AG5

  reg:
    maxItems: 1

  clocks: true

  '#clock-cells':
    const: 1

  clock-output-names: true

  renesas,mode:
    description: Board-specific settings of the MD_CK* bits on R-Mobile A1
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 7

  '#power-domain-cells':
    const: 0

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'
  - clock-output-names

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: renesas,r8a73a4-cpg-clocks
    then:
      properties:
        clocks:
          items:
            - description: extal1
            - description: extal2

        clock-output-names:
          items:
            - const: main
            - const: pll0
            - const: pll1
            - const: pll2
            - const: pll2s
            - const: pll2h
            - const: z
            - const: z2
            - const: i
            - const: m3
            - const: b
            - const: m1
            - const: m2
            - const: zx
            - const: zs
            - const: hp

  - if:
      properties:
        compatible:
          contains:
            const: renesas,r8a7740-cpg-clocks
    then:
      properties:
        clocks:
          items:
            - description: extal1
            - description: extal2
            - description: extalr

        clock-output-names:
          items:
            - const: system
            - const: pllc0
            - const: pllc1
            - const: pllc2
            - const: r
            - const: usb24s
            - const: i
            - const: zg
            - const: b
            - const: m1
            - const: hp
            - const: hpp
            - const: usbp
            - const: s
            - const: zb
            - const: m3
            - const: cp

      required:
        - renesas,mode

  - if:
      properties:
        compatible:
          contains:
            const: renesas,r8a7778-cpg-clocks
    then:
      properties:
        clocks:
          maxItems: 1

        clock-output-names:
          items:
            - const: plla
            - const: pllb
            - const: b
            - const: out
            - const: p
            - const: s
            - const: s1

  - if:
      properties:
        compatible:
          contains:
            const: renesas,r8a7779-cpg-clocks
    then:
      properties:
        clocks:
          maxItems: 1

        clock-output-names:
          items:
            - const: plla
            - const: z
            - const: zs
            - const: s
            - const: s1
            - const: p
            - const: b
            - const: out

  - if:
      properties:
        compatible:
          contains:
            const: renesas,r7s72100-cpg-clocks
    then:
      properties:
        clocks:
          items:
            - description: extal1
            - description: usb_x1

        clock-output-names:
          items:
            - const: pll
            - const: i
            - const: g

  - if:
      properties:
        compatible:
          contains:
            const: renesas,sh73a0-cpg-clocks
    then:
      properties:
        clocks:
          items:
            - description: extal1
            - description: extal2

        clock-output-names:
          items:
            - const: main
            - const: pll0
            - const: pll1
            - const: pll2
            - const: pll3
            - const: dsi0phy
            - const: dsi1phy
            - const: zg
            - const: m3
            - const: b
            - const: m1
            - const: m2
            - const: z
            - const: zx
            - const: hp

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,r8a7778-cpg-clocks
              - renesas,r8a7779-cpg-clocks
              - renesas,rz-cpg-clocks
    then:
      required:
        - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7740-clock.h>
    cpg_clocks: cpg_clocks@e6150000 {
            compatible = "renesas,r8a7740-cpg-clocks";
            reg = <0xe6150000 0x10000>;
            clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
            #clock-cells = <1>;
            clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
                                 "usb24s", "i", "zg", "b", "m1", "hp", "hpp",
                                 "usbp", "s", "zb", "m3", "cp";
            renesas,mode = <0x05>;
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas CPG DIV6 Clock

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

description:
  The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
  Generator (CPG). Their clock input is divided by a configurable factor from 1
  to 64.

properties:
  compatible:
    items:
      - enum:
          - renesas,r8a73a4-div6-clock # R-Mobile APE6
          - renesas,r8a7740-div6-clock # R-Mobile A1
          - renesas,sh73a0-div6-clock  # SH-Mobile AG5
      - const: renesas,cpg-div6-clock

  reg:
    maxItems: 1

  clocks:
    oneOf:
      - maxItems: 1
      - maxItems: 4
      - maxItems: 8
    description:
      For clocks with multiple parents, invalid settings must be specified as
      "<0>".

  '#clock-cells':
    const: 0

  clock-output-names: true

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a73a4-clock.h>

    cpg_clocks: cpg_clocks@e6150000 {
            compatible = "renesas,r8a73a4-cpg-clocks";
            reg = <0xe6150000 0x10000>;
            clocks = <&extal1_clk>, <&extal2_clk>;
            #clock-cells = <1>;
            clock-output-names = "main", "pll0", "pll1", "pll2",
                                  "pll2s", "pll2h", "z", "z2",
                                  "i", "m3", "b", "m1", "m2",
                                  "zx", "zs", "hp";
    };

    sdhi2_clk: sdhi2_clk@e615007c {
            compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
            reg = <0xe615007c 4>;
            clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
                     <&extal2_clk>;
            #clock-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Renesas Clock Pulse Generator / Module Standby and Software Reset

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

description: |
  On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
  and MSSR (Module Standby and Software Reset) blocks are intimately connected,
  and share the same register block.

  They provide the following functionalities:
    - The CPG block generates various core clocks,
    - The MSSR block provides two functions:
        1. Module Standby, providing a Clock Domain to control the clock supply
           to individual SoC devices,
        2. Reset Control, to perform a software reset of individual SoC devices.

properties:
  compatible:
    enum:
      - renesas,r7s9210-cpg-mssr  # RZ/A2
      - renesas,r8a7742-cpg-mssr  # RZ/G1H
      - renesas,r8a7743-cpg-mssr  # RZ/G1M
      - renesas,r8a7744-cpg-mssr  # RZ/G1N
      - renesas,r8a7745-cpg-mssr  # RZ/G1E
      - renesas,r8a77470-cpg-mssr # RZ/G1C
      - renesas,r8a774a1-cpg-mssr # RZ/G2M
      - renesas,r8a774b1-cpg-mssr # RZ/G2N
      - renesas,r8a774c0-cpg-mssr # RZ/G2E
      - renesas,r8a774e1-cpg-mssr # RZ/G2H
      - renesas,r8a7790-cpg-mssr  # R-Car H2
      - renesas,r8a7791-cpg-mssr  # R-Car M2-W
      - renesas,r8a7792-cpg-mssr  # R-Car V2H
      - renesas,r8a7793-cpg-mssr  # R-Car M2-N
      - renesas,r8a7794-cpg-mssr  # R-Car E2
      - renesas,r8a7795-cpg-mssr  # R-Car H3
      - renesas,r8a7796-cpg-mssr  # R-Car M3-W
      - renesas,r8a77961-cpg-mssr # R-Car M3-W+
      - renesas,r8a77965-cpg-mssr # R-Car M3-N
      - renesas,r8a77970-cpg-mssr # R-Car V3M
      - renesas,r8a77980-cpg-mssr # R-Car V3H
      - renesas,r8a77990-cpg-mssr # R-Car E3
      - renesas,r8a77995-cpg-mssr # R-Car D3
      - renesas,r8a779a0-cpg-mssr # R-Car V3U
      - renesas,r8a779f0-cpg-mssr # R-Car S4-8
      - renesas,r8a779g0-cpg-mssr # R-Car V4H

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    maxItems: 2
    items:
      enum:
        - extal     # All
        - extalr    # Most R-Car Gen3 and RZ/G2
        - usb_extal # Most R-Car Gen2 and RZ/G1

  '#clock-cells':
    description: |
      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
        and a core clock reference, as defined in
        <dt-bindings/clock/*-cpg-mssr.h>
      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
        a module number, as defined in the datasheet.
    const: 2

  '#power-domain-cells':
    description:
      SoC devices that are part of the CPG/MSSR Clock Domain and can be
      power-managed through Module Standby should refer to the CPG device node
      in their "power-domains" property, as documented by the generic PM Domain
      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
    const: 0

  '#reset-cells':
    description:
      The single reset specifier cell must be the module number, as defined in
      the datasheet.
    const: 1

if:
  not:
    properties:
      compatible:
        items:
          enum:
            - renesas,r7s9210-cpg-mssr
then:
  required:
    - '#reset-cells'

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    cpg: clock-controller@e6150000 {
            compatible = "renesas,r8a7795-cpg-mssr";
            reg = <0xe6150000 0x1000>;
            clocks = <&extal_clk>, <&extalr_clk>;
            clock-names = "extal", "extalr";
            #clock-cells = <2>;
            #power-domain-cells = <0>;
            #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

description:
  The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
  organized in groups of up to 32 gates.

  This device tree binding describes a single 32 gate clocks group per node.
  Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
  and the clock index in the group, from 0 to 31.

properties:
  compatible:
    items:
      - enum:
          - renesas,r7s72100-mstp-clocks # RZ/A1
          - renesas,r8a73a4-mstp-clocks  # R-Mobile APE6
          - renesas,r8a7740-mstp-clocks  # R-Mobile A1
          - renesas,r8a7778-mstp-clocks  # R-Car M1
          - renesas,r8a7779-mstp-clocks  # R-Car H1
          - renesas,sh73a0-mstp-clocks   # SH-Mobile AG5
      - const: renesas,cpg-mstp-clocks

  reg:
    minItems: 1
    items:
      - description: Module Stop Control Register (MSTPCR)
      - description: Module Stop Status Register (MSTPSR)

  clocks:
    minItems: 1
    maxItems: 32

  '#clock-cells':
    const: 1

  clock-indices:
    minItems: 1
    maxItems: 32

  clock-output-names:
    minItems: 1
    maxItems: 32

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'
  - clock-indices
  - clock-output-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a73a4-clock.h>
    mstp2_clks: mstp2_clks@e6150138 {
            compatible = "renesas,r8a73a4-mstp-clocks",
                         "renesas,cpg-mstp-clocks";
            reg = <0xe6150138 4>, <0xe6150040 4>;
            clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
                     <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
            #clock-cells = <1>;
            clock-indices = <
                    R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
                    R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
                    R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
                    R8A73A4_CLK_DMAC
            >;
            clock-output-names =
                    "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3",
                    "dmac";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas EMMA Mobile EV2 System Management Unit

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>
  - Magnus Damm <magnus.damm@gmail.com>

description: |
  The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
  This is not a clock provider, but clocks under SMU depend on it.

properties:
  compatible:
    const: renesas,emev2-smu

  reg:
    maxItems: 1

  '#address-cells':
    const: 2

  '#size-cells':
    const: 0

required:
  - compatible
  - reg
  - '#address-cells'
  - '#size-cells'

patternProperties:
  ".*sclkdiv@.*":
    type: object

    description: |
      Function block with an input mux and a divider, which corresponds to
      "Serial clock generator" in fig. "Clock System Overview" of the manual,
      and "xxx frequency division setting register" (XXXCLKDIV) registers.
      This makes internal (neither input nor output) clock that is provided
      to input of xxxGCLK block.

    properties:
      compatible:
        const: renesas,emev2-smu-clkdiv

      reg:
        maxItems: 1
        description:
          Byte offset from SMU base and Bit position in the register.

      clocks:
        minItems: 1
        maxItems: 4

      '#clock-cells':
        const: 0

    required:
      - compatible
      - reg
      - clocks
      - '#clock-cells'

    additionalProperties: false

  ".*sclk@.*":
    type: object

    description: |
      Clock gating node shown as "Clock stop processing block" in the
      fig. "Clock System Overview" of the manual.
      Registers are "xxx clock gate control register" (XXXGCLKCTRL).

    properties:
      compatible:
        const: renesas,emev2-smu-gclk

      reg:
        maxItems: 1
        description:
          Byte offset from SMU base and Bit position in the register.

      clocks:
        maxItems: 1

      '#clock-cells':
        const: 0

    required:
      - compatible
      - reg
      - clocks
      - '#clock-cells'

    additionalProperties: false

additionalProperties: true

examples:
  - |
    // Example of clock-tree description:
    //
    //  This describes a clock path in the clock tree
    //   c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
    clocks@e0110000 {
            compatible = "renesas,emev2-smu";
            reg = <0xe0110000 0x10000>;
            #address-cells = <2>;
            #size-cells = <0>;

            c32ki: c32ki {
                    compatible = "fixed-clock";
                    clock-frequency = <32768>;
                    #clock-cells = <0>;
            };
            pll3_fo: pll3_fo {
                    compatible = "fixed-factor-clock";
                    clocks = <&c32ki>;
                    clock-div = <1>;
                    clock-mult = <7000>;
                    #clock-cells = <0>;
            };
            usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
                    compatible = "renesas,emev2-smu-clkdiv";
                    reg = <0x610 0>;
                    clocks = <&pll3_fo>;
                    #clock-cells = <0>;
            };
            usia_u0_sclk: usia_u0_sclk@4a0,1 {
                    compatible = "renesas,emev2-smu-gclk";
                    reg = <0x4a0 1>;
                    clocks = <&usia_u0_sclkdiv>;
                    #clock-cells = <0>;
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/N1D (R9A06G032) System Controller

maintainers:
  - Gareth Williams <gareth.williams.jx@renesas.com>
  - Geert Uytterhoeven <geert+renesas@glider.be>

properties:
  compatible:
    const: renesas,r9a06g032-sysctrl

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: External 40 MHz crystal
      - description: Optional external 32.768 kHz crystal
      - description: Optional external JTAG input
      - description: Optional external RGMII_REFCLK

  clock-names:
    minItems: 1
    items:
      - const: mclk
      - const: rtc
      - const: jtag
      - const: rgmii_ref_ext

  '#clock-cells':
    const: 1

  '#power-domain-cells':
    const: 0

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

patternProperties:
  "^dma-router@[a-f0-9]+$":
    type: object
    $ref: "../dma/renesas,rzn1-dmamux.yaml#"

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    sysctrl: system-controller@4000c000 {
            compatible = "renesas,r9a06g032-sysctrl";
            reg = <0x4000c000 0x1000>;
            clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>,
                     <&ext_rgmii_ref>;
            clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
            #clock-cells = <1>;
            #power-domain-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Renesas R-Car USB 2.0 clock selector

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

description: |
  If you connect an external clock to the USB_EXTAL pin only, you should set
  the clock rate to "usb_extal" node only.
  If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
  is not needed because this is default setting. (Of course, you can set the
  clock rates to both "usb_extal" and "usb_xtal" nodes.

  Case 1: An external clock connects to R-Car SoC
    +----------+   +--- R-Car ---------------------+
    |External  |---|USB_EXTAL ---> all usb channels|
    |clock     |   |USB_XTAL                       |
    +----------+   +-------------------------------+

  In this case, we need this driver with "usb_extal" clock.

  Case 2: An oscillator connects to R-Car SoC
    +----------+   +--- R-Car ---------------------+
    |Oscillator|---|USB_EXTAL -+-> all usb channels|
    |          |---|USB_XTAL --+                   |
    +----------+   +-------------------------------+
  In this case, we don't need this selector.

properties:
  compatible:
    items:
      - enum:
          - renesas,r8a774a1-rcar-usb2-clock-sel # RZ/G2M
          - renesas,r8a774b1-rcar-usb2-clock-sel # RZ/G2N
          - renesas,r8a774e1-rcar-usb2-clock-sel # RZ/G2H
          - renesas,r8a7795-rcar-usb2-clock-sel  # R-Car H3
          - renesas,r8a7796-rcar-usb2-clock-sel  # R-Car M3-W
          - renesas,r8a77961-rcar-usb2-clock-sel # R-Car M3-W+
      - const: renesas,rcar-gen3-usb2-clock-sel

  reg:
    maxItems: 1

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: ehci_ohci
      - const: hs-usb-if
      - const: usb_extal
      - const: usb_xtal

  '#clock-cells':
    const: 0

  power-domains:
    maxItems: 1

  resets:
    maxItems: 2

  reset-names:
    items:
      - const: ehci_ohci
      - const: hs-usb-if

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - power-domains
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    usb2_clksel: clock-controller@e6590630 {
        compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
                     "renesas,rcar-gen3-usb2-clock-sel";
        reg = <0xe6590630 0x02>;
        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
                 <&usb_extal>, <&usb_xtal>;
        clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal";
        #clock-cells = <0>;
        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
        resets = <&cpg 703>, <&cpg 704>;
        reset-names = "ehci_ohci", "hs-usb-if";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

description: |
  On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
  Standby Mode share the same register block. On RZ/V2M, the functionality is
  similar, but does not have Clock Monitor Registers.

  They provide the following functionalities:
    - The CPG block generates various core clocks,
    - The Module Standby Mode block provides two functions:
        1. Module Standby, providing a Clock Domain to control the clock supply
           to individual SoC devices,
        2. Reset Control, to perform a software reset of individual SoC devices.

properties:
  compatible:
    enum:
      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
      - renesas,r9a07g044-cpg # RZ/G2{L,LC}
      - renesas,r9a07g054-cpg # RZ/V2L
      - renesas,r9a09g011-cpg # RZ/V2M

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    description:
      Clock source to CPG can be either from external clock input (EXCLK) or
      crystal oscillator (XIN/XOUT).
    const: extal

  '#clock-cells':
    description: |
      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
        and a core clock reference, as defined in
        <dt-bindings/clock/r9a0*-cpg.h>,
      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
        a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
    const: 2

  '#power-domain-cells':
    description:
      SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
      can be power-managed through Module Standby should refer to the CPG device
      node in their "power-domains" property, as documented by the generic PM
      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
    const: 0

  '#reset-cells':
    description:
      The single reset specifier cell must be the module number, as defined in
      <dt-bindings/clock/r9a0*-cpg.h>.
    const: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#power-domain-cells'
  - '#reset-cells'

additionalProperties: false

examples:
  - |
    cpg: clock-controller@11010000 {
            compatible = "renesas,r9a07g044-cpg";
            reg = <0x11010000 0x10000>;
            clocks = <&extal_clk>;
            clock-names = "extal";
            #clock-cells = <2>;
            #power-domain-cells = <0>;
            #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,versaclock7.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Versaclock7 Programmable Clock Device Tree Bindings

maintainers:
  - Alex Helms <alexander.helms.jy@renesas.com>

description: |
  Renesas Versaclock7 is a family of configurable clock generator and
  jitter attenuator ICs with fractional and integer dividers.

properties:
  '#clock-cells':
    const: 1

  compatible:
    enum:
      - renesas,rc21008a

  reg:
    maxItems: 1

  clocks:
    items:
      - description: External crystal or oscillator

  clock-names:
    items:
      - const: xin

required:
  - '#clock-cells'
  - compatible
  - reg
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    vc7_xin: clock {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <49152000>;
    };

    i2c@0 {
        reg = <0x0 0x100>;
        #address-cells = <1>;
        #size-cells = <0>;

        vc7: clock-controller@9 {
            compatible = "renesas,rc21008a";
            reg = <0x9>;
            #clock-cells = <1>;
            clocks = <&vc7_xin>;
            clock-names = "xin";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip PX30 Clock and Reset Unit (CRU)

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The PX30 clock controller generates and supplies clocks to various
  controllers within the SoC and also implements a reset controller for SoC
  peripherals.
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
  used in device tree sources. Similar macros exist for the reset sources in
  these files.
  There are several clocks that are generated outside the SoC. It is expected
  that they are defined using standard clock bindings with following
  clock-output-names:
    - "xin24m"     - crystal input       - required
    - "xin32k"     - rtc clock           - optional
    - "i2sx_clkin" - external I2S clock  - optional
    - "gmac_clkin" - external GMAC clock - optional

properties:
  compatible:
    enum:
      - rockchip,px30-cru
      - rockchip,px30-pmucru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    minItems: 1
    items:
      - description: Clock for both PMUCRU and CRU
      - description: Clock for CRU (sourced from PMUCRU)

  clock-names:
    minItems: 1
    items:
      - const: xin24m
      - const: gpll

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#clock-cells"
  - "#reset-cells"

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: rockchip,px30-cru

    then:
      properties:
        clocks:
          minItems: 2

        clock-names:
          minItems: 2

    else:
      properties:
        clocks:
          maxItems: 1

        clock-names:
          maxItems: 1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/px30-cru.h>

    pmucru: clock-controller@ff2bc000 {
      compatible = "rockchip,px30-pmucru";
      reg = <0xff2bc000 0x1000>;
      clocks = <&xin24m>;
      clock-names = "xin24m";
      rockchip,grf = <&grf>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };

    cru: clock-controller@ff2b0000 {
      compatible = "rockchip,px30-cru";
      reg = <0xff2b0000 0x1000>;
      clocks = <&xin24m>, <&pmucru PLL_GPLL>;
      clock-names = "xin24m", "gpll";
      rockchip,grf = <&grf>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3036 Clock and Reset Unit (CRU)

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3036 clock controller generates and supplies clocks to various
  controllers within the SoC and also implements a reset controller for SoC
  peripherals.
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
  used in device tree sources. Similar macros exist for the reset sources in
  these files.
  There are several clocks that are generated outside the SoC. It is expected
  that they are defined using standard clock bindings with following
  clock-output-names:
    - "xin24m"     - crystal input       - required
    - "ext_i2s"    - external I2S clock  - optional
    - "rmii_clkin" - external EMAC clock - optional

properties:
  compatible:
    enum:
      - rockchip,rk3036-cru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xin24m

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    cru: clock-controller@20000000 {
      compatible = "rockchip,rk3036-cru";
      reg = <0x20000000 0x1000>;
      rockchip,grf = <&grf>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3128-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3126/RK3128 Clock and Reset Unit (CRU)

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3126/RK3128 clock controller generates and supplies clock to various
  controllers within the SoC and also implements a reset controller for SoC
  peripherals.
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
  used in device tree sources. Similar macros exist for the reset sources in
  these files.

properties:
  compatible:
    enum:
      - rockchip,rk3126-cru
      - rockchip,rk3128-cru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    minItems: 1
    maxItems: 3

  clock-names:
    minItems: 1
    items:
      - const: xin24m
      - enum:
          - ext_i2s
          - gmac_clkin
      - enum:
          - ext_i2s
          - gmac_clkin

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    cru: clock-controller@20000000 {
      compatible = "rockchip,rk3128-cru";
      reg = <0x20000000 0x1000>;
      rockchip,grf = <&grf>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU)

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3188/RK3066 clock controller generates and supplies clocks to various
  controllers within the SoC and also implements a reset controller for SoC
  peripherals.
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
  dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
  Similar macros exist for the reset sources in these files.
  There are several clocks that are generated outside the SoC. It is expected
  that they are defined using standard clock bindings with following
  clock-output-names:
    - "xin24m"    - crystal input                 - required
    - "xin32k"    - RTC clock                     - optional
    - "xin27m"    - 27mhz crystal input on RK3066 - optional
    - "ext_hsadc" - external HSADC clock          - optional
    - "ext_cif0"  - external camera clock         - optional
    - "ext_rmii"  - external RMII clock           - optional
    - "ext_jtag"  - external JTAG clock           - optional

properties:
  compatible:
    enum:
      - rockchip,rk3066a-cru
      - rockchip,rk3188-cru
      - rockchip,rk3188a-cru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xin24m

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    cru: clock-controller@20000000 {
      compatible = "rockchip,rk3188-cru";
      reg = <0x20000000 0x1000>;
      rockchip,grf = <&grf>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3228 Clock and Reset Unit (CRU)

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3228 clock controller generates and supplies clocks to various
  controllers within the SoC and also implements a reset controller for SoC
  peripherals.
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
  used in device tree sources. Similar macros exist for the reset sources in
  these files.
  There are several clocks that are generated outside the SoC. It is expected
  that they are defined using standard clock bindings with following
  clock-output-names:
    - "xin24m"      - crystal input                          - required
    - "ext_i2s"     - external I2S clock                     - optional
    - "ext_gmac"    - external GMAC clock                    - optional
    - "ext_hsadc"   - external HSADC clock                   - optional
    - "phy_50m_out" - output clock of the pll in the mac phy

properties:
  compatible:
    enum:
      - rockchip,rk3228-cru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xin24m

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    cru: clock-controller@20000000 {
      compatible = "rockchip,rk3228-cru";
      reg = <0x20000000 0x1000>;
      rockchip,grf = <&grf>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3288 Clock and Reset Unit (CRU)

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3288 clock controller generates and supplies clocks to various
  controllers within the SoC and also implements a reset controller for SoC
  peripherals.

  A revision of this SoC is available: rk3288w. The clock tree is a bit
  different so another dt-compatible is available. Noticed that it is only
  setting the difference but there is no automatic revision detection. This
  should be performed by boot loaders.

  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
  used in device tree sources. Similar macros exist for the reset sources in
  these files.

  There are several clocks that are generated outside the SoC. It is expected
  that they are defined using standard clock bindings with following
  clock-output-names:
    - "xin24m"      - crystal input               - required,
    - "xin32k"      - rtc clock                   - optional,
    - "ext_i2s"     - external I2S clock          - optional,
    - "ext_hsadc"   - external HSADC clock        - optional,
    - "ext_edp_24m" - external display port clock - optional,
    - "ext_vip"     - external VIP clock          - optional,
    - "ext_isp"     - external ISP clock          - optional,
    - "ext_jtag"    - external JTAG clock         - optional

properties:
  compatible:
    enum:
      - rockchip,rk3288-cru
      - rockchip,rk3288w-cru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xin24m

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    cru: clock-controller@ff760000 {
      compatible = "rockchip,rk3288-cru";
      reg = <0xff760000 0x1000>;
      rockchip,grf = <&grf>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3308 Clock and Reset Unit (CRU)

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3308 clock controller generates and supplies clocks to various
  controllers within the SoC and also implements a reset controller for SoC
  peripherals.
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
  used in device tree sources. Similar macros exist for the reset sources in
  these files.
  There are several clocks that are generated outside the SoC. It is expected
  that they are defined using standard clock bindings with following
  clock-output-names:
    - "xin24m"                               - crystal input      - required
    - "xin32k"                               - rtc clock          - optional
    - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in",
      "mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in",
      "mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - external I2S or
                                               SPDIF clock        - optional
    - "mac_clkin"                            - external MAC clock - optional

properties:
  compatible:
    enum:
      - rockchip,rk3308-cru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xin24m

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    cru: clock-controller@ff500000 {
      compatible = "rockchip,rk3308-cru";
      reg = <0xff500000 0x1000>;
      rockchip,grf = <&grf>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
* Rockchip RK3328 Clock and Reset Unit

The RK3328 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.

Required Properties:

- compatible: should be "rockchip,rk3328-cru"
- reg: physical base address of the controller and length of memory mapped
  region.
- #clock-cells: should be 1.
- #reset-cells: should be 1.

Optional Properties:

- rockchip,grf: phandle to the syscon managing the "general register files"
  If missing pll rates are not changeable, due to the missing pll lock status.

Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
used in device tree sources. Similar macros exist for the reset sources in
these files.

External clocks:

There are several clocks that are generated outside the SoC. It is expected
that they are defined using standard clock bindings with following
clock-output-names:
 - "xin24m" - crystal input - required,
 - "clkin_i2s" - external I2S clock - optional,
 - "gmac_clkin" - external GMAC clock - optional
 - "phy_50m_out" - output clock of the pll in the mac phy
 - "hdmi_phy" - output clock of the hdmi phy pll - optional

Example: Clock controller node:

	cru: clock-controller@ff440000 {
		compatible = "rockchip,rk3328-cru";
		reg = <0x0 0xff440000 0x0 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
	};

Example: UART controller node that consumes the clock generated by the clock
  controller:

	uart0: serial@ff120000 {
		compatible = "snps,dw-apb-uart";
		reg = <0xff120000 0x100>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clocks = <&cru SCLK_UART0>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3368 Clock and Reset Unit (CRU)

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3368 clock controller generates and supplies clocks to various
  controllers within the SoC and also implements a reset controller for SoC
  peripherals.
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
  used in device tree sources. Similar macros exist for the reset sources in
  these files.
  There are several clocks that are generated outside the SoC. It is expected
  that they are defined using standard clock bindings with following
  clock-output-names:
    - "xin24m"     - crystal input                          - required
    - "xin32k"     - rtc clock                              - optional
    - "ext_i2s"    - external I2S clock                     - optional
    - "ext_gmac"   - external GMAC clock                    - optional
    - "ext_hsadc"  - external HSADC clock                   - optional
    - "ext_isp"    - external ISP clock                     - optional
    - "ext_jtag"   - external JTAG clock                    - optional
    - "ext_vip"    - external VIP clock                     - optional
    - "usbotg_out" - output clock of the pll in the otg phy

properties:
  compatible:
    enum:
      - rockchip,rk3368-cru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xin24m

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    cru: clock-controller@ff760000 {
      compatible = "rockchip,rk3368-cru";
      reg = <0xff760000 0x1000>;
      rockchip,grf = <&grf>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3399 Clock and Reset Unit

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3399 clock controller generates and supplies clock to various
  controllers within the SoC and also implements a reset controller for SoC
  peripherals.
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
  used in device tree sources. Similar macros exist for the reset sources in
  these files.
  There are several clocks that are generated outside the SoC. It is expected
  that they are defined using standard clock bindings with following
  clock-output-names:
    - "xin24m"           - crystal input                          - required,
    - "xin32k"           - rtc clock                              - optional,
    - "clkin_gmac"       - external GMAC clock                    - optional,
    - "clkin_i2s"        - external I2S clock                     - optional,
    - "pclkin_cif"       - external ISP clock                     - optional,
    - "clk_usbphy0_480m" - output clock of the pll in the usbphy0
    - "clk_usbphy1_480m" - output clock of the pll in the usbphy1

properties:
  compatible:
    enum:
      - rockchip,rk3399-pmucru
      - rockchip,rk3399-cru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xin24m

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files". It is used
      for GRF muxes, if missing any muxes present in the GRF will not be
      available.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    pmucru: clock-controller@ff750000 {
      compatible = "rockchip,rk3399-pmucru";
      reg = <0xff750000 0x1000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };
  - |
    cru: clock-controller@ff760000 {
      compatible = "rockchip,rk3399-cru";
      reg = <0xff760000 0x1000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ROCKCHIP rk3568 Family Clock Control Module Binding

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3568 clock controller generates the clock and also implements a
  reset controller for SoC peripherals.
  (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module)
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
  used in device tree sources.

properties:
  compatible:
    enum:
      - rockchip,rk3568-cru
      - rockchip,rk3568-pmucru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xin24m

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  # Clock Control Module node:
  - |
    pmucru: clock-controller@fdd00000 {
      compatible = "rockchip,rk3568-pmucru";
      reg = <0xfdd00000 0x1000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };
  - |
    cru: clock-controller@fdd20000 {
      compatible = "rockchip,rk3568-cru";
      reg = <0xfdd20000 0x1000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip rk3588 Family Clock and Reset Control Module

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3588 clock controller generates the clock and also implements a reset
  controller for SoC peripherals. For example it provides SCLK_UART2 and
  PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
  module.
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clock and reset IDs
  are defined as preprocessor macros in dt-binding headers.

properties:
  compatible:
    enum:
      - rockchip,rk3588-cru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    minItems: 2
    maxItems: 2

  clock-names:
    items:
      - const: xin24m
      - const: xin32k

  assigned-clocks: true

  assigned-clock-rates: true

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: >
      phandle to the syscon managing the "general register files". It is used
      for GRF muxes, if missing any muxes present in the GRF will not be
      available.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    cru: clock-controller@fd7c0000 {
      compatible = "rockchip,rk3588-cru";
      reg = <0xfd7c0000 0x5c000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RV1108 Clock and Reset Unit (CRU)

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RV1108 clock controller generates and supplies clocks to various
  controllers within the SoC and also implements a reset controller for SoC
  peripherals.
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
  used in device tree sources. Similar macros exist for the reset sources in
  these files.
  There are several clocks that are generated outside the SoC. It is expected
  that they are defined using standard clock bindings with following
  clock-output-names:
    - "xin24m"   - crystal input                              - required
    - "ext_vip"  - external VIP clock                         - optional
    - "ext_i2s"  - external I2S clock                         - optional
    - "ext_gmac" - external GMAC clock                        - optional
    - "hdmiphy"  - external clock input derived from HDMI PHY - optional
    - "usbphy"   - external clock input derived from USB PHY  - optional

properties:
  compatible:
    enum:
      - rockchip,rv1108-cru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xin24m

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    cru: clock-controller@20200000 {
      compatible = "rockchip,rv1108-cru";
      reg = <0x20200000 0x1000>;
      rockchip,grf = <&grf>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RV1126 Clock and Reset Unit

maintainers:
  - Jagan Teki <jagan@edgeble.ai>
  - Finley Xiao <finley.xiao@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description:
  The RV1126 clock controller generates the clock and also implements a
  reset controller for SoC peripherals.

properties:
  compatible:
    enum:
      - rockchip,rv1126-cru
      - rockchip,rv1126-pmucru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    const: xin24m

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    cru: clock-controller@ff490000 {
      compatible = "rockchip,rv1126-cru";
      reg = <0xff490000 0x1000>;
      rockchip,grf = <&grf>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC Audio SubSystem clock controller

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  All available clocks are defined as preprocessor macros in
  include/dt-bindings/clock/exynos-audss-clk.h header.

properties:
  compatible:
    enum:
      - samsung,exynos4210-audss-clock
      - samsung,exynos5250-audss-clock
      - samsung,exynos5410-audss-clock
      - samsung,exynos5420-audss-clock

  clocks:
    minItems: 2
    items:
      - description:
          Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
          used if not specified.
      - description:
          Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
          used if not specified.
      - description:
          Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if not
          specified.
      - description:
          PCM clock, parent of sclk_pcm.  "sclk_pcm0" is used if not specified.
      - description:
          External i2s clock, parent of mout_i2s. "cdclk0" is used if not
          specified.

  clock-names:
    minItems: 2
    items:
      - const: pll_ref
      - const: pll_in
      - const: sclk_audio
      - const: sclk_pcm_in
      - const: cdclk

  "#clock-cells":
    const: 1

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - clocks
  - clock-names
  - "#clock-cells"
  - reg

additionalProperties: false

examples:
  - |
    clock-controller@3810000 {
        compatible = "samsung,exynos5250-audss-clock";
        reg = <0x03810000 0x0c>;
        #clock-cells = <1>;
        clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, <&ext_i2s_clk>;
        clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC clock controller

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  All available clocks are defined as preprocessor macros in
  dt-bindings/clock/ headers.

properties:
  compatible:
    oneOf:
      - enum:
          - samsung,exynos3250-cmu
          - samsung,exynos3250-cmu-dmc
          - samsung,exynos3250-cmu-isp
          - samsung,exynos4210-clock
          - samsung,exynos4412-clock
          - samsung,exynos5250-clock
      - items:
          - enum:
              - samsung,exynos5420-clock
              - samsung,exynos5800-clock
          - const: syscon

  clocks:
    minItems: 1
    maxItems: 4

  "#clock-cells":
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - "#clock-cells"
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5250.h>
    clock: clock-controller@10010000 {
        compatible = "samsung,exynos5250-clock";
        reg = <0x10010000 0x30000>;
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos-ext-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung SoC external/osc/XXTI/XusbXTI clock

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  Samsung SoCs require an external clock supplied through XXTI or XusbXTI pins.

properties:
  compatible:
    enum:
      - samsung,clock-xxti
      - samsung,clock-xusbxti
      - samsung,exynos5420-oscclk

  "#clock-cells":
    const: 0

  clock-frequency: true

  clock-output-names:
    maxItems: 1

required:
  - compatible
  - clock-frequency

additionalProperties: false

examples:
  - |
    fixed-rate-clocks {
        clock {
            compatible = "samsung,clock-xxti";
            clock-frequency = <24000000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos4412-isp-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos4412 SoC ISP clock controller

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  Clock controller for Samsung Exynos4412 SoC FIMC-ISP (Camera ISP)
  All available clocks are defined as preprocessor macros in
  dt-bindings/clock/ headers.

properties:
  compatible:
    const: samsung,exynos4412-isp-clock

  clocks:
    items:
      - description: CLK_ACLK200 from the main clock controller
      - description: CLK_ACLK400_MCUISP from the main clock controller

  clock-names:
    items:
      - const: aclk200
      - const: aclk400_mcuisp

  "#clock-cells":
    const: 1

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - "#clock-cells"
  - clocks
  - clock-names
  - power-domains
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos4.h>
    clock-controller@10048000 {
        compatible = "samsung,exynos4412-isp-clock";
        reg = <0x10048000 0x1000>;
        #clock-cells = <1>;
        power-domains = <&pd_isp>;
        clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
        clock-names = "aclk200", "aclk400_mcuisp";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos5260 SoC clock controller

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  Expected external clocks, defined in DTS as fixed-rate clocks with a matching
  name::
    - "fin_pll" - PLL input clock from XXTI
    - "xrtcxti" - input clock from XRTCXTI
    - "ioclk_pcm_extclk" - pcm external operation clock
    - "ioclk_spdif_extclk" - spdif external operation clock
    - "ioclk_i2s_cdclk" - i2s0 codec clock

  Phy clocks::
  There are several clocks which are generated by specific PHYs.  These clocks
  are fed into the clock controller and then routed to the hardware blocks.
  These clocks are defined as fixed clocks in the driver with following names::
    - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
    - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
    - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
    - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
    - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
    - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
    - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
    - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
    - "phyclk_dptx_phy_clk_div2"
    - "phyclk_mipi_dphy_4l_m_rxclkesc0"
    - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
    - "phyclk_usbhost20_phy_freeclk"
    - "phyclk_usbhost20_phy_clk48mohci"
    - "phyclk_usbdrd30_udrd30_pipe_pclk"
    - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock

  All available clocks are defined as preprocessor macros in
  include/dt-bindings/clock/exynos5260-clk.h header.

properties:
  compatible:
    enum:
      - samsung,exynos5260-clock-top
      - samsung,exynos5260-clock-peri
      - samsung,exynos5260-clock-egl
      - samsung,exynos5260-clock-kfc
      - samsung,exynos5260-clock-g2d
      - samsung,exynos5260-clock-mif
      - samsung,exynos5260-clock-mfc
      - samsung,exynos5260-clock-g3d
      - samsung,exynos5260-clock-fsys
      - samsung,exynos5260-clock-aud
      - samsung,exynos5260-clock-isp
      - samsung,exynos5260-clock-gscl
      - samsung,exynos5260-clock-disp

  clocks:
    minItems: 1
    maxItems: 19

  clock-names:
    minItems: 1
    maxItems: 19

  "#clock-cells":
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - "#clock-cells"
  - reg

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-top
    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4
        clock-names:
          items:
            - const: fin_pll
            - const: dout_mem_pll
            - const: dout_bus_pll
            - const: dout_media_pll
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-peri
    then:
      properties:
        clocks:
          minItems: 13
          maxItems: 13
        clock-names:
          items:
            - const: fin_pll
            - const: ioclk_pcm_extclk
            - const: ioclk_i2s_cdclk
            - const: ioclk_spdif_extclk
            - const: phyclk_hdmi_phy_ref_cko
            - const: dout_aclk_peri_66
            - const: dout_sclk_peri_uart0
            - const: dout_sclk_peri_uart1
            - const: dout_sclk_peri_uart2
            - const: dout_sclk_peri_spi0_b
            - const: dout_sclk_peri_spi1_b
            - const: dout_sclk_peri_spi2_b
            - const: dout_aclk_peri_aud
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-egl
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: fin_pll
            - const: dout_bus_pll
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-kfc
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: fin_pll
            - const: dout_media_pll
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-g2d
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: fin_pll
            - const: dout_aclk_g2d_333
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-mif
    then:
      properties:
        clocks:
          minItems: 1
          maxItems: 1
        clock-names:
          items:
            - const: fin_pll
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-mfc
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: fin_pll
            - const: dout_aclk_mfc_333
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-g3d
    then:
      properties:
        clocks:
          minItems: 1
          maxItems: 1
        clock-names:
          items:
            - const: fin_pll
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-fsys
    then:
      properties:
        clocks:
          minItems: 7
          maxItems: 7
        clock-names:
          items:
            - const: fin_pll
            - const: phyclk_usbhost20_phy_phyclock
            - const: phyclk_usbhost20_phy_freeclk
            - const: phyclk_usbhost20_phy_clk48mohci
            - const: phyclk_usbdrd30_udrd30_pipe_pclk
            - const: phyclk_usbdrd30_udrd30_phyclock
            - const: dout_aclk_fsys_200
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-aud
    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4
        clock-names:
          items:
            - const: fin_pll
            - const: fout_aud_pll
            - const: ioclk_i2s_cdclk
            - const: ioclk_pcm_extclk
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-isp
    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4
        clock-names:
          items:
            - const: fin_pll
            - const: dout_aclk_isp1_266
            - const: dout_aclk_isp1_400
            - const: mout_aclk_isp1_266

      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-gscl
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: fin_pll
            - const: dout_aclk_gscl_400
            - const: dout_aclk_gscl_333
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5260-clock-disp
    then:
      properties:
        clocks:
          minItems: 19
          maxItems: 19
        clock-names:
          items:
            - const: fin_pll
            - const: phyclk_dptx_phy_ch3_txd_clk
            - const: phyclk_dptx_phy_ch2_txd_clk
            - const: phyclk_dptx_phy_ch1_txd_clk
            - const: phyclk_dptx_phy_ch0_txd_clk
            - const: phyclk_hdmi_phy_tmds_clko
            - const: phyclk_hdmi_phy_ref_clko
            - const: phyclk_hdmi_phy_pixel_clko
            - const: phyclk_hdmi_link_o_tmds_clkhi
            - const: phyclk_mipi_dphy_4l_m_txbyte_clkhs
            - const: phyclk_dptx_phy_o_ref_clk_24m
            - const: phyclk_dptx_phy_clk_div2
            - const: phyclk_mipi_dphy_4l_m_rxclkesc0
            - const: phyclk_hdmi_phy_ref_cko
            - const: ioclk_spdif_extclk
            - const: dout_aclk_peri_aud
            - const: dout_aclk_disp_222
            - const: dout_sclk_disp_pixel
            - const: dout_aclk_disp_333
      required:
        - clock-names
        - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5260-clk.h>

    fin_pll: clock {
        compatible = "fixed-clock";
        clock-output-names = "fin_pll";
        #clock-cells = <0>;
        clock-frequency = <24000000>;
    };

    clock-controller@10010000 {
        compatible = "samsung,exynos5260-clock-top";
        reg = <0x10010000 0x10000>;
        #clock-cells = <1>;
        clocks = <&fin_pll>,
                 <&clock_mif MIF_DOUT_MEM_PLL>,
                 <&clock_mif MIF_DOUT_BUS_PLL>,
                 <&clock_mif MIF_DOUT_MEDIA_PLL>;
        clock-names = "fin_pll",
                      "dout_mem_pll",
                      "dout_bus_pll",
                      "dout_media_pll";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos5410 SoC clock controller

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  Expected external clocks, defined in DTS as fixed-rate clocks with a matching
  name::
    - "fin_pll" - PLL input clock from XXTI

  All available clocks are defined as preprocessor macros in
  include/dt-bindings/clock/exynos5410.h header.

properties:
  compatible:
    oneOf:
      - enum:
          - samsung,exynos5410-clock

  clocks:
    description:
      Should contain an entry specifying the root clock from external
      oscillator supplied through XXTI or XusbXTI pin.  This clock should be
      defined using standard clock bindings with "fin_pll" clock-output-name.
      That clock is being passed internally to the 9 PLLs.
    maxItems: 1

  "#clock-cells":
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - "#clock-cells"
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5410.h>

    fin_pll: osc-clock {
        compatible = "fixed-clock";
        clock-frequency = <24000000>;
        clock-output-names = "fin_pll";
        #clock-cells = <0>;
    };

    clock-controller@10010000 {
        compatible = "samsung,exynos5410-clock";
        reg = <0x10010000 0x30000>;
        #clock-cells = <1>;
        clocks = <&fin_pll>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos5433 SoC clock controller

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  Expected external clocks, defined in DTS as fixed-rate clocks with a matching
  name::
    - "oscclk" - PLL input clock from XXTI

  All available clocks are defined as preprocessor macros in
  include/dt-bindings/clock/exynos5433.h header.

properties:
  compatible:
    enum:
        # CMU_TOP which generates clocks for
        # IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus
        # clocks
      - samsung,exynos5433-cmu-top
        # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP
      - samsung,exynos5433-cmu-cpif
        # CMU_MIF which generates clocks for DRAM Memory Controller domain
      - samsung,exynos5433-cmu-mif
        # CMU_PERIC which generates clocks for
        # UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs
      - samsung,exynos5433-cmu-peric
        # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
      - samsung,exynos5433-cmu-peris
        # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
      - samsung,exynos5433-cmu-fsys
      - samsung,exynos5433-cmu-g2d
        # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
      - samsung,exynos5433-cmu-disp
      - samsung,exynos5433-cmu-aud
      - samsung,exynos5433-cmu-bus0
      - samsung,exynos5433-cmu-bus1
      - samsung,exynos5433-cmu-bus2
      - samsung,exynos5433-cmu-g3d
      - samsung,exynos5433-cmu-gscl
      - samsung,exynos5433-cmu-apollo
        # CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor,
        # CoreSight and  L2 cache controller
      - samsung,exynos5433-cmu-atlas
        # CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and
        # JPEG IPs
      - samsung,exynos5433-cmu-mscl
      - samsung,exynos5433-cmu-mfc
      - samsung,exynos5433-cmu-hevc
        # CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs
      - samsung,exynos5433-cmu-isp
        # CMU_CAM0 which generates clocks for
        # MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs
      - samsung,exynos5433-cmu-cam0
        # CMU_CAM1 which generates clocks for
        # Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs
      - samsung,exynos5433-cmu-cam1
        # CMU_IMEM which generates clocks for SSS (Security SubSystem) and
        # SlimSSS IPs
      - samsung,exynos5433-cmu-imem

  clocks:
    minItems: 1
    maxItems: 10

  clock-names:
    minItems: 1
    maxItems: 10

  "#clock-cells":
    const: 1

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - "#clock-cells"
  - reg

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-top
    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4
        clock-names:
          items:
            - const: oscclk
            - const: sclk_mphy_pll
            - const: sclk_mfc_pll
            - const: sclk_bus_pll
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-cpif
    then:
      properties:
        clocks:
          minItems: 1
          maxItems: 1
        clock-names:
          items:
            - const: oscclk
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-mif
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: oscclk
            - const: sclk_mphy_pll
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-fsys
    then:
      properties:
        clocks:
          minItems: 10
          maxItems: 10
        clock-names:
          items:
            - const: oscclk
            - const: sclk_ufs_mphy
            - const: aclk_fsys_200
            - const: sclk_pcie_100_fsys
            - const: sclk_ufsunipro_fsys
            - const: sclk_mmc2_fsys
            - const: sclk_mmc1_fsys
            - const: sclk_mmc0_fsys
            - const: sclk_usbhost30_fsys
            - const: sclk_usbdrd30_fsys
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-g2d
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: oscclk
            - const: aclk_g2d_266
            - const: aclk_g2d_400
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-disp
    then:
      properties:
        clocks:
          minItems: 9
          maxItems: 9
        clock-names:
          items:
            - const: oscclk
            - const: sclk_dsim1_disp
            - const: sclk_dsim0_disp
            - const: sclk_dsd_disp
            - const: sclk_decon_tv_eclk_disp
            - const: sclk_decon_vclk_disp
            - const: sclk_decon_eclk_disp
            - const: sclk_decon_tv_vclk_disp
            - const: aclk_disp_333
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-aud
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: oscclk
            - const: fout_aud_pll
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-bus0
    then:
      properties:
        clocks:
          minItems: 1
          maxItems: 1
        clock-names:
          items:
            - const: aclk_bus0_400
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-bus1
    then:
      properties:
        clocks:
          minItems: 1
          maxItems: 1
        clock-names:
          items:
            - const: aclk_bus1_400
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-bus2
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: oscclk
            - const: aclk_bus2_400
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-g3d
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: oscclk
            - const: aclk_g3d_400
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-gscl
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: oscclk
            - const: aclk_gscl_111
            - const: aclk_gscl_333
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-apollo
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: oscclk
            - const: sclk_bus_pll_apollo
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-atlas
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: oscclk
            - const: sclk_bus_pll_atlas
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-mscl
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: oscclk
            - const: sclk_jpeg_mscl
            - const: aclk_mscl_400
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-mfc
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: oscclk
            - const: aclk_mfc_400
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-hevc
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: oscclk
            - const: aclk_hevc_400
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-isp
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: oscclk
            - const: aclk_isp_dis_400
            - const: aclk_isp_400
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-cam0
    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4
        clock-names:
          items:
            - const: oscclk
            - const: aclk_cam0_333
            - const: aclk_cam0_400
            - const: aclk_cam0_552
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-cam1
    then:
      properties:
        clocks:
          minItems: 7
          maxItems: 7
        clock-names:
          items:
            - const: oscclk
            - const: sclk_isp_uart_cam1
            - const: sclk_isp_spi1_cam1
            - const: sclk_isp_spi0_cam1
            - const: aclk_cam1_333
            - const: aclk_cam1_400
            - const: aclk_cam1_552
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-cmu-imem
    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4
        clock-names:
          items:
            - const: oscclk
            - const: aclk_imem_sssx_266
            - const: aclk_imem_266
            - const: aclk_imem_200
      required:
        - clock-names
        - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5433.h>
    xxti: clock {
        compatible = "fixed-clock";
        clock-output-names = "oscclk";
        #clock-cells = <0>;
        clock-frequency = <24000000>;
    };

    clock-controller@10030000 {
        compatible = "samsung,exynos5433-cmu-top";
        reg = <0x10030000 0x1000>;
        #clock-cells = <1>;

        clock-names = "oscclk",
                      "sclk_mphy_pll",
                      "sclk_mfc_pll",
                      "sclk_bus_pll";
        clocks = <&xxti>,
                 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
                 <&cmu_mif CLK_SCLK_MFC_PLL>,
                 <&cmu_mif CLK_SCLK_BUS_PLL>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos7 SoC clock controller

maintainers:
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  Expected external clocks, defined in DTS as fixed-rate clocks with a matching
  name::
    - "fin_pll" - PLL input clock from XXTI

  All available clocks are defined as preprocessor macros in
  include/dt-bindings/clock/exynos7-clk.h header.

properties:
  compatible:
    enum:
      - samsung,exynos7-clock-topc
      - samsung,exynos7-clock-top0
      - samsung,exynos7-clock-top1
      - samsung,exynos7-clock-ccore
      - samsung,exynos7-clock-peric0
      - samsung,exynos7-clock-peric1
      - samsung,exynos7-clock-peris
      - samsung,exynos7-clock-fsys0
      - samsung,exynos7-clock-fsys1
      - samsung,exynos7-clock-mscl
      - samsung,exynos7-clock-aud

  clocks:
    minItems: 1
    maxItems: 13

  clock-names:
    minItems: 1
    maxItems: 13

  "#clock-cells":
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - "#clock-cells"
  - reg

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7-clock-top0
    then:
      properties:
        clocks:
          minItems: 6
          maxItems: 6
        clock-names:
          items:
            - const: fin_pll
            - const: dout_sclk_bus0_pll
            - const: dout_sclk_bus1_pll
            - const: dout_sclk_cc_pll
            - const: dout_sclk_mfc_pll
            - const: dout_sclk_aud_pll
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7-clock-top1
    then:
      properties:
        clocks:
          minItems: 5
          maxItems: 5
        clock-names:
          items:
            - const: fin_pll
            - const: dout_sclk_bus0_pll
            - const: dout_sclk_bus1_pll
            - const: dout_sclk_cc_pll
            - const: dout_sclk_mfc_pll
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7-clock-ccore
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: fin_pll
            - const: dout_aclk_ccore_133
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7-clock-peric0
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: fin_pll
            - const: dout_aclk_peric0_66
            - const: sclk_uart0
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7-clock-peric1
    then:
      properties:
        clocks:
          minItems: 13
          maxItems: 13
        clock-names:
          items:
            - const: fin_pll
            - const: dout_aclk_peric1_66
            - const: sclk_uart1
            - const: sclk_uart2
            - const: sclk_uart3
            - const: sclk_spi0
            - const: sclk_spi1
            - const: sclk_spi2
            - const: sclk_spi3
            - const: sclk_spi4
            - const: sclk_i2s1
            - const: sclk_pcm1
            - const: sclk_spdif
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7-clock-peris
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: fin_pll
            - const: dout_aclk_peris_66
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7-clock-fsys0
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: fin_pll
            - const: dout_aclk_fsys0_200
            - const: dout_sclk_mmc2
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7-clock-fsys1
    then:
      properties:
        clocks:
          minItems: 7
          maxItems: 7
        clock-names:
          items:
            - const: fin_pll
            - const: dout_aclk_fsys1_200
            - const: dout_sclk_mmc0
            - const: dout_sclk_mmc1
            - const: dout_sclk_ufsunipro20
            - const: dout_sclk_phy_fsys1
            - const: dout_sclk_phy_fsys1_26m
      required:
        - clock-names
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7-clock-aud
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: fin_pll
            - const: fout_aud_pll
      required:
        - clock-names
        - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos7-clk.h>

    fin_pll: clock {
        compatible = "fixed-clock";
        clock-output-names = "fin_pll";
        #clock-cells = <0>;
        clock-frequency = <24000000>;
    };

    clock-controller@105e0000 {
        compatible = "samsung,exynos7-clock-top1";
        reg = <0x105e0000 0xb000>;
        #clock-cells = <1>;
        clocks = <&fin_pll>,
                 <&clock_topc DOUT_SCLK_BUS0_PLL>,
                 <&clock_topc DOUT_SCLK_BUS1_PLL>,
                 <&clock_topc DOUT_SCLK_CC_PLL>,
                 <&clock_topc DOUT_SCLK_MFC_PLL>;
        clock-names = "fin_pll",
                      "dout_sclk_bus0_pll",
                      "dout_sclk_bus1_pll",
                      "dout_sclk_cc_pll",
                      "dout_sclk_mfc_pll";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos7885 SoC clock controller

maintainers:
  - Dávid Virág <virag.david003@gmail.com>
  - Chanwoo Choi <cw00.choi@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  Exynos7885 clock controller is comprised of several CMU units, generating
  clocks for different domains. Those CMU units are modeled as separate device
  tree nodes, and might depend on each other. The root clock in that root tree
  is an external clock: OSCCLK (26 MHz). This external clock must be defined
  as a fixed-rate clock in dts.

  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.

  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All clocks available for usage
  in clock consumer nodes are defined as preprocessor macros in
  'dt-bindings/clock/exynos7885.h' header.

properties:
  compatible:
    enum:
      - samsung,exynos7885-cmu-top
      - samsung,exynos7885-cmu-core
      - samsung,exynos7885-cmu-fsys
      - samsung,exynos7885-cmu-peri

  clocks:
    minItems: 1
    maxItems: 10

  clock-names:
    minItems: 1
    maxItems: 10

  "#clock-cells":
    const: 1

  reg:
    maxItems: 1

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7885-cmu-top

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)

        clock-names:
          items:
            - const: oscclk

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7885-cmu-core

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_CORE bus clock (from CMU_TOP)
            - description: CCI clock (from CMU_TOP)
            - description: G3D clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_core_bus
            - const: dout_core_cci
            - const: dout_core_g3d

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7885-cmu-fsys

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_FSYS bus clock (from CMU_TOP)
            - description: MMC_CARD clock (from CMU_TOP)
            - description: MMC_EMBD clock (from CMU_TOP)
            - description: MMC_SDIO clock (from CMU_TOP)
            - description: USB30DRD clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_fsys_bus
            - const: dout_fsys_mmc_card
            - const: dout_fsys_mmc_embd
            - const: dout_fsys_mmc_sdio
            - const: dout_fsys_usb30drd

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7885-cmu-peri

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (26 MHz)
            - description: CMU_PERI bus clock (from CMU_TOP)
            - description: SPI0 clock (from CMU_TOP)
            - description: SPI1 clock (from CMU_TOP)
            - description: UART0 clock (from CMU_TOP)
            - description: UART1 clock (from CMU_TOP)
            - description: UART2 clock (from CMU_TOP)
            - description: USI0 clock (from CMU_TOP)
            - description: USI1 clock (from CMU_TOP)
            - description: USI2 clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: dout_peri_bus
            - const: dout_peri_spi0
            - const: dout_peri_spi1
            - const: dout_peri_uart0
            - const: dout_peri_uart1
            - const: dout_peri_uart2
            - const: dout_peri_usi0
            - const: dout_peri_usi1
            - const: dout_peri_usi2

required:
  - compatible
  - "#clock-cells"
  - clocks
  - clock-names
  - reg

additionalProperties: false

examples:
  # Clock controller node for CMU_PERI
  - |
    #include <dt-bindings/clock/exynos7885.h>

    cmu_peri: clock-controller@10010000 {
        compatible = "samsung,exynos7885-cmu-peri";
        reg = <0x10010000 0x8000>;
        #clock-cells = <1>;

        clocks = <&oscclk>,
                 <&cmu_top CLK_DOUT_PERI_BUS>,
                 <&cmu_top CLK_DOUT_PERI_SPI0>,
                 <&cmu_top CLK_DOUT_PERI_SPI1>,
                 <&cmu_top CLK_DOUT_PERI_UART0>,
                 <&cmu_top CLK_DOUT_PERI_UART1>,
                 <&cmu_top CLK_DOUT_PERI_UART2>,
                 <&cmu_top CLK_DOUT_PERI_USI0>,
                 <&cmu_top CLK_DOUT_PERI_USI1>,
                 <&cmu_top CLK_DOUT_PERI_USI2>;
        clock-names = "oscclk",
                      "dout_peri_bus",
                      "dout_peri_spi0",
                      "dout_peri_spi1",
                      "dout_peri_uart0",
                      "dout_peri_uart1",
                      "dout_peri_uart2",
                      "dout_peri_usi0",
                      "dout_peri_usi1",
                      "dout_peri_usi2";
    };

...