code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung Exynos7 SoC device tree source
 *
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 */

#include <dt-bindings/clock/exynos7-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "samsung,exynos7";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		pinctrl0 = &pinctrl_alive;
		pinctrl1 = &pinctrl_bus0;
		pinctrl2 = &pinctrl_nfc;
		pinctrl3 = &pinctrl_touch;
		pinctrl4 = &pinctrl_ff;
		pinctrl5 = &pinctrl_ese;
		pinctrl6 = &pinctrl_fsys0;
		pinctrl7 = &pinctrl_fsys1;
		pinctrl8 = &pinctrl_bus1;
		tmuctrl0 = &tmuctrl_0;
	};

	arm-pmu {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
				     <&cpu_atlas2>, <&cpu_atlas3>;
	};

	fin_pll: clock {
		/* XXTI */
		compatible = "fixed-clock";
		clock-output-names = "fin_pll";
		#clock-cells = <0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu_atlas0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0>;
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&atlas_l2>;
		};

		cpu_atlas1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x1>;
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&atlas_l2>;
		};

		cpu_atlas2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x2>;
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&atlas_l2>;
		};

		cpu_atlas3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x3>;
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&atlas_l2>;
		};

		atlas_l2: l2-cache0 {
			compatible = "cache";
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
		};
	};

	psci {
		compatible = "arm,psci";
		method = "smc";
		cpu_off = <0x84000002>;
		cpu_on = <0xC4000003>;
	};

	soc: soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0x18000000>;

		chipid@10000000 {
			compatible = "samsung,exynos4210-chipid";
			reg = <0x10000000 0x100>;
		};

		gic: interrupt-controller@11001000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg =	<0x11001000 0x1000>,
				<0x11002000 0x2000>,
				<0x11004000 0x2000>,
				<0x11006000 0x2000>;
		};

		pdma0: dma-controller@10e10000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x10E10000 0x1000>;
			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_fsys0 ACLK_PDMA0>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
		};

		pdma1: dma-controller@10eb0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x10EB0000 0x1000>;
			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_fsys0 ACLK_PDMA1>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
		};

		clock_topc: clock-controller@10570000 {
			compatible = "samsung,exynos7-clock-topc";
			reg = <0x10570000 0x10000>;
			#clock-cells = <1>;
		};

		clock_top0: clock-controller@105d0000 {
			compatible = "samsung,exynos7-clock-top0";
			reg = <0x105d0000 0xb000>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
				 <&clock_topc DOUT_SCLK_BUS1_PLL>,
				 <&clock_topc DOUT_SCLK_CC_PLL>,
				 <&clock_topc DOUT_SCLK_MFC_PLL>,
				 <&clock_topc DOUT_SCLK_AUD_PLL>;
			clock-names = "fin_pll", "dout_sclk_bus0_pll",
				      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
				      "dout_sclk_mfc_pll", "dout_sclk_aud_pll";
		};

		clock_top1: clock-controller@105e0000 {
			compatible = "samsung,exynos7-clock-top1";
			reg = <0x105e0000 0xb000>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
				 <&clock_topc DOUT_SCLK_BUS1_PLL>,
				 <&clock_topc DOUT_SCLK_CC_PLL>,
				 <&clock_topc DOUT_SCLK_MFC_PLL>;
			clock-names = "fin_pll", "dout_sclk_bus0_pll",
				      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
				      "dout_sclk_mfc_pll";
		};

		clock_ccore: clock-controller@105b0000 {
			compatible = "samsung,exynos7-clock-ccore";
			reg = <0x105b0000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
			clock-names = "fin_pll", "dout_aclk_ccore_133";
		};

		clock_peric0: clock-controller@13610000 {
			compatible = "samsung,exynos7-clock-peric0";
			reg = <0x13610000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
				 <&clock_top0 CLK_SCLK_UART0>;
			clock-names = "fin_pll", "dout_aclk_peric0_66",
				      "sclk_uart0";
		};

		clock_peric1: clock-controller@14c80000 {
			compatible = "samsung,exynos7-clock-peric1";
			reg = <0x14c80000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>,
				 <&clock_top0 DOUT_ACLK_PERIC1>,
				 <&clock_top0 CLK_SCLK_UART1>,
				 <&clock_top0 CLK_SCLK_UART2>,
				 <&clock_top0 CLK_SCLK_UART3>,
				 <&clock_top0 CLK_SCLK_SPI0>,
				 <&clock_top0 CLK_SCLK_SPI1>,
				 <&clock_top0 CLK_SCLK_SPI2>,
				 <&clock_top0 CLK_SCLK_SPI3>,
				 <&clock_top0 CLK_SCLK_SPI4>,
				 <&clock_top0 CLK_SCLK_I2S1>,
				 <&clock_top0 CLK_SCLK_PCM1>,
				 <&clock_top0 CLK_SCLK_SPDIF>;
			clock-names = "fin_pll",
				      "dout_aclk_peric1_66",
				      "sclk_uart1",
				      "sclk_uart2",
				      "sclk_uart3",
				      "sclk_spi0",
				      "sclk_spi1",
				      "sclk_spi2",
				      "sclk_spi3",
				      "sclk_spi4",
				      "sclk_i2s1",
				      "sclk_pcm1",
				      "sclk_spdif";
		};

		clock_peris: clock-controller@10040000 {
			compatible = "samsung,exynos7-clock-peris";
			reg = <0x10040000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
			clock-names = "fin_pll", "dout_aclk_peris_66";
		};

		clock_fsys0: clock-controller@10e90000 {
			compatible = "samsung,exynos7-clock-fsys0";
			reg = <0x10e90000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
				 <&clock_top1 DOUT_SCLK_MMC2>;
			clock-names = "fin_pll", "dout_aclk_fsys0_200",
				      "dout_sclk_mmc2";
		};

		clock_fsys1: clock-controller@156e0000 {
			compatible = "samsung,exynos7-clock-fsys1";
			reg = <0x156e0000 0xd00>;
			#clock-cells = <1>;
			clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
				 <&clock_top1 DOUT_SCLK_MMC0>,
				 <&clock_top1 DOUT_SCLK_MMC1>,
				 <&clock_top1 DOUT_SCLK_UFSUNIPRO20>,
				 <&clock_top1 DOUT_SCLK_PHY_FSYS1>,
				 <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>;
			clock-names = "fin_pll", "dout_aclk_fsys1_200",
				      "dout_sclk_mmc0", "dout_sclk_mmc1",
				      "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1",
				      "dout_sclk_phy_fsys1_26m";
		};

		serial_0: serial@13630000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x13630000 0x100>;
			interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peric0 PCLK_UART0>,
				 <&clock_peric0 SCLK_UART0>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_1: serial@14c20000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x14c20000 0x100>;
			interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peric1 PCLK_UART1>,
				 <&clock_peric1 SCLK_UART1>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_2: serial@14c30000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x14c30000 0x100>;
			interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peric1 PCLK_UART2>,
				 <&clock_peric1 SCLK_UART2>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		serial_3: serial@14c40000 {
			compatible = "samsung,exynos4210-uart";
			reg = <0x14c40000 0x100>;
			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peric1 PCLK_UART3>,
				 <&clock_peric1 SCLK_UART3>;
			clock-names = "uart", "clk_uart_baud0";
			status = "disabled";
		};

		pinctrl_alive: pinctrl@10580000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x10580000 0x1000>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos7-wakeup-eint";
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		pinctrl_bus0: pinctrl@13470000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x13470000 0x1000>;
			interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_nfc: pinctrl@14cd0000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x14cd0000 0x1000>;
			interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_touch: pinctrl@14ce0000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x14ce0000 0x1000>;
			interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_ff: pinctrl@14c90000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x14c90000 0x1000>;
			interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_ese: pinctrl@14ca0000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x14ca0000 0x1000>;
			interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_fsys0: pinctrl@10e60000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x10e60000 0x1000>;
			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_fsys1: pinctrl@15690000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x15690000 0x1000>;
			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_bus1: pinctrl@14870000 {
			compatible = "samsung,exynos7-pinctrl";
			reg = <0x14870000 0x1000>;
			interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
		};

		hsi2c_0: i2c@13640000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13640000 0x1000>;
			interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c0_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C0>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_1: i2c@13650000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13650000 0x1000>;
			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c1_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C1>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_2: i2c@14e60000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x14e60000 0x1000>;
			interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c2_bus>;
			clocks = <&clock_peric1 PCLK_HSI2C2>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_3: i2c@14e70000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x14e70000 0x1000>;
			interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c3_bus>;
			clocks = <&clock_peric1 PCLK_HSI2C3>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_4: i2c@13660000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13660000 0x1000>;
			interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c4_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C4>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_5: i2c@13670000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13670000 0x1000>;
			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c5_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C5>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_6: i2c@14e00000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x14e00000 0x1000>;
			interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c6_bus>;
			clocks = <&clock_peric1 PCLK_HSI2C6>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_7: i2c@13e10000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13e10000 0x1000>;
			interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c7_bus>;
			clocks = <&clock_peric1 PCLK_HSI2C7>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_8: i2c@14e20000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x14e20000 0x1000>;
			interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c8_bus>;
			clocks = <&clock_peric1 PCLK_HSI2C8>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_9: i2c@13680000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13680000 0x1000>;
			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c9_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C9>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_10: i2c@13690000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x13690000 0x1000>;
			interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c10_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C10>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		hsi2c_11: i2c@136a0000 {
			compatible = "samsung,exynos7-hsi2c";
			reg = <0x136a0000 0x1000>;
			interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&hs_i2c11_bus>;
			clocks = <&clock_peric0 PCLK_HSI2C11>;
			clock-names = "hsi2c";
			status = "disabled";
		};

		pmu_system_controller: system-controller@105c0000 {
			compatible = "samsung,exynos7-pmu", "syscon";
			reg = <0x105c0000 0x5000>;
		};

		rtc: rtc@10590000 {
			compatible = "samsung,s3c6410-rtc";
			reg = <0x10590000 0x100>;
			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_ccore PCLK_RTC>;
			clock-names = "rtc";
			status = "disabled";
		};

		watchdog: watchdog@101d0000 {
			compatible = "samsung,exynos7-wdt";
			reg = <0x101d0000 0x100>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peris PCLK_WDT>;
			clock-names = "watchdog";
			samsung,syscon-phandle = <&pmu_system_controller>;
			status = "disabled";
		};

		gpu: gpu@14ac0000 {
			compatible = "samsung,exynos5433-mali", "arm,mali-t760";
			reg = <0x14ac0000 0x5000>;
			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "job", "mmu", "gpu";
			status = "disabled";
			/* TODO: operating points for DVFS, cooling device */
		};

		mmc_0: mmc@15740000 {
			compatible = "samsung,exynos7-dw-mshc-smu";
			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x15740000 0x2000>;
			clocks = <&clock_fsys1 ACLK_MMC0>,
				 <&clock_top1 CLK_SCLK_MMC0>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x40>;
			status = "disabled";
		};

		mmc_1: mmc@15750000 {
			compatible = "samsung,exynos7-dw-mshc";
			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x15750000 0x2000>;
			clocks = <&clock_fsys1 ACLK_MMC1>,
				 <&clock_top1 CLK_SCLK_MMC1>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x40>;
			status = "disabled";
		};

		mmc_2: mmc@15560000 {
			compatible = "samsung,exynos7-dw-mshc-smu";
			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x15560000 0x2000>;
			clocks = <&clock_fsys0 ACLK_MMC2>,
				 <&clock_top1 CLK_SCLK_MMC2>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x40>;
			status = "disabled";
		};

		adc: adc@13620000 {
			compatible = "samsung,exynos7-adc";
			reg = <0x13620000 0x100>;
			interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peric0 PCLK_ADCIF>;
			clock-names = "adc";
			#io-channel-cells = <1>;
			status = "disabled";
		};

		pwm: pwm@136c0000 {
			compatible = "samsung,exynos4210-pwm";
			reg = <0x136c0000 0x100>;
			interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
			#pwm-cells = <3>;
			clocks = <&clock_peric0 PCLK_PWM>;
			clock-names = "timers";
		};

		tmuctrl_0: tmu@10060000 {
			compatible = "samsung,exynos7-tmu";
			reg = <0x10060000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_peris PCLK_TMU>,
				 <&clock_peris SCLK_TMU>;
			clock-names = "tmu_apbif", "tmu_sclk";
			#thermal-sensor-cells = <0>;
		};

		ufs: ufs@15570000 {
			compatible = "samsung,exynos7-ufs";
			reg = <0x15570000 0x100>,  /* 0: HCI standard */
				<0x15570100 0x100>,  /* 1: Vendor specificed */
				<0x15571000 0x200>,  /* 2: UNIPRO */
				<0x15572000 0x300>;  /* 3: UFS protector */
			reg-names = "hci", "vs_hci", "unipro", "ufsp";
			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
				<&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
			clock-names = "core_clk", "sclk_unipro_main";
			freq-table-hz = <0 0>, <0 0>;
			pinctrl-names = "default";
			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
			phys = <&ufs_phy>;
			phy-names = "ufs-phy";
			status = "disabled";
		};

		ufs_phy: ufs-phy@15571800 {
			compatible = "samsung,exynos7-ufs-phy";
			reg = <0x15571800 0x240>;
			reg-names = "phy-pma";
			samsung,pmu-syscon = <&pmu_system_controller>;
			#phy-cells = <0>;
			clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
				 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
				 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
				 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
			clock-names = "ref_clk", "rx1_symbol_clk",
				      "rx0_symbol_clk",
				      "tx0_symbol_clk";
		};

		usbdrd_phy: phy@15500000 {
			compatible = "samsung,exynos7-usbdrd-phy";
			reg = <0x15500000 0x100>;
			clocks = <&clock_fsys0 ACLK_USBDRD300>,
			       <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
			       <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
			       <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
			       <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
			clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp";
			samsung,pmu-syscon = <&pmu_system_controller>;
			#phy-cells = <1>;
		};

		usbdrd: usb {
			compatible = "samsung,exynos7-dwusb3";
			clocks = <&clock_fsys0 ACLK_USBDRD300>,
			       <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
			       <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
			clock-names = "usbdrd30", "usbdrd30_susp_clk",
				"usbdrd30_axius_clk";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			usb@15400000 {
				compatible = "snps,dwc3";
				reg = <0x15400000 0x10000>;
				interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
				phy-names = "usb2-phy", "usb3-phy";
			};
		};
	};

	thermal-zones {
		atlas_thermal: cluster0-thermal {
			polling-delay-passive = <0>; /* milliseconds */
			polling-delay = <0>; /* milliseconds */
			thermal-sensors = <&tmuctrl_0>;
			#include "exynos7-trip-points.dtsi"
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};
};

#include "exynos7-pinctrl.dtsi"
#include "arm/exynos-syscon-restart.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
 *
 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
 * Copyright (c) 2021 Dávid Virág
 */

/dts-v1/;
#include "exynos7885.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "Samsung Galaxy A8 (2018)";
	compatible = "samsung,jackpotlte", "samsung,exynos7885";
	chassis-type = "handset";

	aliases {
		serial0 = &serial_0;
		serial1 = &serial_1;
		serial2 = &serial_2;
	};

	chosen {
		stdout-path = &serial_2;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x3da00000>,
		      <0x0 0xc0000000 0x40000000>,
		      <0x8 0x80000000 0x40000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&key_volup &key_voldown &key_power>;

		volup-key {
			label = "Volume Up";
			linux,code = <KEY_VOLUMEUP>;
			gpios = <&gpa1 5 GPIO_ACTIVE_LOW>;
		};

		voldown-key {
			label = "Volume Down";
			linux,code = <KEY_VOLUMEDOWN>;
			gpios = <&gpa1 6 GPIO_ACTIVE_LOW>;
		};

		power-key {
			label = "Power";
			linux,code = <KEY_POWER>;
			gpios = <&gpa1 7 GPIO_ACTIVE_LOW>;
			wakeup-source;
		};
	};
};

&mmc_0 {
	status = "okay";
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	cap-mmc-highspeed;
	non-removable;
	mmc-hs400-enhanced-strobe;
	card-detect-delay = <200>;
	clock-frequency = <800000000>;
	bus-width = <8>;
	samsung,dw-mshc-ciu-div = <3>;
	samsung,dw-mshc-sdr-timing = <0 4>;
	samsung,dw-mshc-ddr-timing = <2 4>;
	samsung,dw-mshc-hs400-timing = <0 2>;

	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk_fast_slew_rate_3x &sd0_cmd &sd0_rdqs
		     &sd0_bus1 &sd0_bus4 &sd0_bus8>;
};

&oscclk {
	clock-frequency = <26000000>;
};

&pinctrl_alive {
	key_volup: key-volup-pins {
		samsung,pins = "gpa1-5";
		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	key_voldown: key-voldown-pins {
		samsung,pins = "gpa1-6";
		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	key_power: key-power-pins {
		samsung,pins = "gpa1-7";
		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};
};

&serial_2 {
	status = "okay";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
 *
 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
 * Copyright (c) 2021 Dávid Virág
 *
 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
 * device tree nodes in this file.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "exynos-pinctrl.h"

&pinctrl_alive {
	etc0: etc0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	etc1: etc1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpa0: gpa0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpa1: gpa1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpa2: gpa2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpq0: gpq0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	sim1_det_gpio: sim1-det-gpio-pins {
		samsung,pins = "gpa2-5";
		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	sim0_det_gpio: sim0-det-gpio-pins {
		samsung,pins = "gpa2-6";
		samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	speedy_bus: speedy-bus-pins {
		samsung,pins = "gpq0-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* UART_DEBUG */
	uart2_bus: uart2-bus-pins {
		samsung,pins = "gpq0-4", "gpq0-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};
};

&pinctrl_dispaud {
	gpb0: gpb0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpb1: gpb1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpb2: gpb2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	aud_codec_mclk: aud-codec-mclk-pins {
		samsung,pins = "gpb0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_codec_mclk_idle: aud-codec-mclk-idle-pins {
		samsung,pins = "gpb0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_codec_bus: aud-codec-bus-pins {
		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_codec_bus_idle: aud-codec-bus-idle-pins {
		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_loopback_bus: aud-loopback-bus-pins {
		samsung,pins = "gpb1-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_loopback_bus_idle: aud-loopback-bus-idle-pins {
		samsung,pins = "gpb1-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_fm_bus: aud-fm-bus-pins {
		samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_fm_bus_idle: aud-fm-bus-idle-pins {
		samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_spk_bus: aud-spk-bus-pins {
		samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_spk_bus_idle: aud-spk-bus-idle-pins {
		samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};
};

&pinctrl_fsys {
	gpf0: gpf0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpf2: gpf2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpf3: gpf3-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpf4: gpf4-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	sd0_clk: sd0-clk-pins {
		samsung,pins = "gpf0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x-pins {
		samsung,pins = "gpf0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x-pins {
		samsung,pins = "gpf0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV2>;
	};

	sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x-pins {
		samsung,pins = "gpf0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x-pins {
		samsung,pins = "gpf0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd0_cmd: sd0-cmd-pins {
		samsung,pins = "gpf0-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd0_rdqs: sd0-rdqs-pins {
		samsung,pins = "gpf0-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd0_bus1: sd0-bus-width1-pins {
		samsung,pins = "gpf2-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd0_bus4: sd0-bus-width4-pins {
		samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd0_bus8: sd0-bus-width8-pins {
		samsung,pins = "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd1_clk: sd1-clk-pins {
		samsung,pins = "gpf3-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sd1_clk_fast_slew_rate_1x: sd1-clk-fast-slew-rate-1x-pins {
		samsung,pins = "gpf3-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	sd1_clk_fast_slew_rate_2x: sd1-clk-fast-slew-rate-2x-pins {
		samsung,pins = "gpf3-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV2>;
	};

	sd1_clk_fast_slew_rate_3x: sd1-clk-fast-slew-rate-3x-pins {
		samsung,pins = "gpf3-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sd1_clk_fast_slew_rate_4x: sd1-clk-fast-slew-rate-4x-pins {
		samsung,pins = "gpf3-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd1_cmd: sd1-cmd-pins {
		samsung,pins = "gpf3-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sd1_bus1: sd1-bus-width1-pins {
		samsung,pins = "gpf3-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sd1_bus4: sd1-bus-width4-pins {
		samsung,pins = "gpf3-3", "gpf3-5";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sd2_clk: sd2-clk-pins {
		samsung,pins = "gpf4-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
		samsung,pins = "gpf4-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
		samsung,pins = "gpf4-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV2>;
	};

	sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
		samsung,pins = "gpf4-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
		samsung,pins = "gpf4-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd2_cmd: sd2-cmd-pins {
		samsung,pins = "gpf4-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sd2_bus1: sd2-bus-width1-pins {
		samsung,pins = "gpf4-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sd2_bus4: sd2-bus-width4-pins {
		samsung,pins = "gpf4-3", "gpf4-4", "gpf4-5";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};
};

&pinctrl_top {
	gpc0: gpc0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpc1: gpc1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpc2: gpc2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpg0: gpg0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpg1: gpg1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpg2: gpg2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpg3: gpg3-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpg4: gpg4-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpp0: gpp0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpp1: gpp1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpp2: gpp2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpp3: gpp3-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpp4: gpp4-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpp5: gpp5-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpp6: gpp6-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpp7: gpp7-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpp8: gpp8-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	hs_i2c0_bus: hs-i2c0-bus-pins {
		samsung,pins = "gpc1-1", "gpc1-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
		samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	hs_i2c1_bus: hs-i2c1-bus-pins {
		samsung,pins = "gpc1-3", "gpc1-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
		samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
	};

	hs_i2c2_bus: hs-i2c2-bus-pins {
		samsung,pins = "gpc1-5", "gpc1-4";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
		samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
	};

	hs_i2c3_bus: hs-i2c3-bus-pins {
		samsung,pins = "gpc1-7", "gpc1-6";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
		samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
	};

	/* USI0 UART */
	uart3_bus_single: uart3-bus-single-pins {
		samsung,pins = "gpc2-3", "gpc2-2", "gpc2-1", "gpc2-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	/* USI0 UART_HSI2C1 */
	uart3_bus_dual: uart3-bus-dual-pins {
		samsung,pins = "gpc2-1", "gpc2-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	/* USI0 HSI2C0 */
	hs_i2c4_bus: hs-i2c4-bus-pins {
		samsung,pins = "gpc2-1", "gpc2-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
		samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
	};

	/* USI0 HSI2C1 */
	hs_i2c5_bus: hs-i2c5-bus-pins {
		samsung,pins = "gpc2-3", "gpc2-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
		samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
	};

	/* USI0 SPI */
	spi2_bus: spi2-bus-pins {
		samsung,pins = "gpc2-1", "gpc2-0", "gpc2-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	spi2_cs: spi2-cs-pins {
		samsung,pins = "gpc2-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* USI1 UART */
	uart4_bus_single: uart4-bus-single-pins {
		samsung,pins = "gpc2-7", "gpc2-6", "gpc2-5", "gpc2-4";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	/* USI1 UART_HSI2C1*/
	uart4_bus_dual: uart4-bus-dual-pins {
		samsung,pins = "gpc2-5", "gpc2-4";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	/* USI1 HSI2C0 */
	hs_i2c6_bus: hs-i2c6-bus-pins {
		samsung,pins = "gpc2-5", "gpc2-4";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
		samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
	};

	/* USI1 HSI2C1 */
	hs_i2c7_bus: hs-i2c7-bus-pins {
		samsung,pins = "gpc2-7", "gpc2-6";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
		samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
	};

	/* USI1 SPI */
	spi3_bus: spi3-bus-pins {
		samsung,pins = "gpc2-5", "gpc2-4", "gpc2-7";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	spi3_cs: spi3-cs-pins {
		samsung,pins = "gpc2-6";
		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	fm_lna_en: fm-lna-en-pins {
		samsung,pins = "gpg0-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
		samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-val = <1>;
	};

	uart1_bus: uart1-bus-pins {
		samsung,pins = "gpg1-3", "gpg1-2", "gpg1-1", "gpg1-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	i2c7_bus: i2c7-bus-pins {
		samsung,pins = "gpg1-5", "gpg1-4";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	aud_dmic_on: aud-dmic-on-pins {
		samsung,pins = "gpg2-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
		samsung,pin-val = <1>;
	};

	aud_dmic_off: aud-dmic-off-pins {
		samsung,pins = "gpg2-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
		samsung,pin-val = <0>;
	};

	/* UART_HEALTH */
	uart0_bus: uart0-bus-pins {
		samsung,pins = "gpp0-3", "gpp0-2", "gpp0-1", "gpp0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	i2c0_bus: i2c0-bus-pins {
		samsung,pins = "gpp1-1", "gpp1-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	i2c1_bus: i2c1-bus-pins {
		samsung,pins = "gpp1-3", "gpp1-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	i2c2_bus: i2c2-bus-pins {
		samsung,pins = "gpp2-1", "gpp2-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	i2c3_bus: i2c3-bus-pins {
		samsung,pins = "gpp3-1", "gpp3-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	i2c4_bus: i2c4-bus-pins {
		samsung,pins = "gpp4-1", "gpp4-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	i2c5_bus: i2c5-bus-pins {
		samsung,pins = "gpp4-3", "gpp4-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	i2c6_bus: i2c6-bus-pins {
		samsung,pins = "gpp4-5", "gpp4-4";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* SPI_ESE */
	spi0_bus: spi0-bus-pins {
		samsung,pins = "gpp5-3", "gpp5-2", "gpp5-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	spi0_cs: spi0-cs-pins {
		samsung,pins = "gpp5-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* SPI_FP */
	spi1_bus: spi1-bus-pins {
		samsung,pins = "gpp6-3", "gpp6-2", "gpp6-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	spi1_cs: spi1-cs-pins {
		samsung,pins = "gpp6-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* USI2 UART */
	uart5_bus_single: uart5-bus-single-pins {
		samsung,pins = "gpp8-1", "gpp8-0", "gpp7-1", "gpp7-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	  };

	/* USI2 UART_HSI2C1 */
	uart5_bus_dual: uart5-bus-dual-pins {
		samsung,pins = "gpp7-1", "gpp7-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	/* USI2 HSI2C0 */
	hs_i2c8_bus: hs-i2c8-bus-pins {
		samsung,pins = "gpp7-1", "gpp7-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
		samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
	};

	/* USI2 HSI2C1 */
	hs_i2c9_bus: hs-i2c9-bus-pins {
		samsung,pins = "gpp8-1", "gpp8-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
		samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
		samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
	};

	/* USI2 SPI */
	spi4_bus: spi4-bus-pins {
		samsung,pins = "gpp7-1", "gpp7-0", "gpp8-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	spi4_cs: spi4-cs-pins {
		samsung,pins = "gpp8-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung Exynos7885 SoC device tree source
 *
 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
 * Copyright (c) 2021 Dávid Virág
 */

#include <dt-bindings/clock/exynos7885.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "samsung,exynos7885";
	#address-cells = <2>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_alive;
		pinctrl1 = &pinctrl_dispaud;
		pinctrl2 = &pinctrl_fsys;
		pinctrl3 = &pinctrl_top;
	};

	arm-a53-pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>,
				     <&cpu4>,
				     <&cpu5>;
	};

	arm-a73-pmu {
		compatible = "arm,cortex-a73-pmu";
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu6>,
				     <&cpu7>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
				core4 {
					cpu = <&cpu4>;
				};
				core5 {
					cpu = <&cpu5>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu6>;
				};
				core1 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			enable-method = "psci";
		};

		cpu1: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			enable-method = "psci";
		};

		cpu2: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x102>;
			enable-method = "psci";
		};

		cpu3: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x103>;
			enable-method = "psci";
		};

		cpu4: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x200>;
			enable-method = "psci";
		};

		cpu5: cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x201>;
			enable-method = "psci";
		};

		cpu6: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0>;
			enable-method = "psci";
		};

		cpu7: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x1>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci";
		method = "smc";
		cpu_suspend = <0xc4000001>;
		cpu_off = <0x84000002>;
		cpu_on = <0xc4000003>;
	};

	timer {
		compatible = "arm,armv8-timer";
		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	fixed-rate-clocks {
		oscclk: osc-clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-output-names = "oscclk";
		};
	};

	soc: soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x20000000>;

		chipid@10000000 {
			compatible = "samsung,exynos850-chipid";
			reg = <0x10000000 0x24>;
		};

		gic: interrupt-controller@12301000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x12301000 0x1000>,
			      <0x12302000 0x2000>,
			      <0x12304000 0x2000>,
			      <0x12306000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
						 IRQ_TYPE_LEVEL_HIGH)>;
		};

		cmu_peri: clock-controller@10010000 {
			compatible = "samsung,exynos7885-cmu-peri";
			reg = <0x10010000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>,
				 <&cmu_top CLK_DOUT_PERI_BUS>,
				 <&cmu_top CLK_DOUT_PERI_SPI0>,
				 <&cmu_top CLK_DOUT_PERI_SPI1>,
				 <&cmu_top CLK_DOUT_PERI_UART0>,
				 <&cmu_top CLK_DOUT_PERI_UART1>,
				 <&cmu_top CLK_DOUT_PERI_UART2>,
				 <&cmu_top CLK_DOUT_PERI_USI0>,
				 <&cmu_top CLK_DOUT_PERI_USI1>,
				 <&cmu_top CLK_DOUT_PERI_USI2>;
			clock-names = "oscclk",
				      "dout_peri_bus",
				      "dout_peri_spi0",
				      "dout_peri_spi1",
				      "dout_peri_uart0",
				      "dout_peri_uart1",
				      "dout_peri_uart2",
				      "dout_peri_usi0",
				      "dout_peri_usi1",
				      "dout_peri_usi2";
		};

		cmu_core: clock-controller@12000000 {
			compatible = "samsung,exynos7885-cmu-core";
			reg = <0x12000000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>,
				 <&cmu_top CLK_DOUT_CORE_BUS>,
				 <&cmu_top CLK_DOUT_CORE_CCI>,
				 <&cmu_top CLK_DOUT_CORE_G3D>;
			clock-names = "oscclk",
				      "dout_core_bus",
				      "dout_core_cci",
				      "dout_core_g3d";
		};

		cmu_top: clock-controller@12060000 {
			compatible = "samsung,exynos7885-cmu-top";
			reg = <0x12060000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>;
			clock-names = "oscclk";
		};

		cmu_fsys: clock-controller@13400000 {
			compatible = "samsung,exynos7885-cmu-fsys";
			reg = <0x13400000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>,
				 <&cmu_top CLK_DOUT_FSYS_BUS>,
				 <&cmu_top CLK_DOUT_FSYS_MMC_CARD>,
				 <&cmu_top CLK_DOUT_FSYS_MMC_EMBD>,
				 <&cmu_top CLK_DOUT_FSYS_MMC_SDIO>,
				 <&cmu_top CLK_DOUT_FSYS_USB30DRD>;
			clock-names = "oscclk",
				      "dout_fsys_bus",
				      "dout_fsys_mmc_card",
				      "dout_fsys_mmc_embd",
				      "dout_fsys_mmc_sdio",
				      "dout_fsys_usb30drd";
		};

		pinctrl_alive: pinctrl@11cb0000 {
			compatible = "samsung,exynos7885-pinctrl";
			reg = <0x11cb0000 0x1000>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos7-wakeup-eint";
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		pinctrl_fsys: pinctrl@13430000 {
			compatible = "samsung,exynos7885-pinctrl";
			reg = <0x13430000 0x1000>;
			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_top: pinctrl@139b0000 {
			compatible = "samsung,exynos7885-pinctrl";
			reg = <0x139b0000 0x1000>;
			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_dispaud: pinctrl@148f0000 {
			compatible = "samsung,exynos7885-pinctrl";
			reg = <0x148f0000 0x1000>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
		};

		pmu_system_controller: system-controller@11c80000 {
			compatible = "samsung,exynos7-pmu", "syscon";
			reg = <0x11c80000 0x10000>;
		};

		mmc_0: mmc@13500000 {
			compatible = "samsung,exynos7-dw-mshc-smu";
			reg = <0x13500000 0x2000>;
			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>,
				 <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x40>;
			status = "disabled";
		};

		serial_0: serial@13800000 {
			compatible = "samsung,exynos5433-uart";
			reg = <0x13800000 0x100>;
			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_bus>;
			clocks = <&cmu_peri CLK_GOUT_UART0_PCLK>,
				 <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>;
			clock-names = "uart", "clk_uart_baud0";
			samsung,uart-fifosize = <64>;
			status = "disabled";
		};

		serial_1: serial@13810000 {
			compatible = "samsung,exynos5433-uart";
			reg = <0x13810000 0x100>;
			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart1_bus>;
			clocks = <&cmu_peri CLK_GOUT_UART1_PCLK>,
				 <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>;
			clock-names = "uart", "clk_uart_baud0";
			samsung,uart-fifosize = <256>;
			status = "disabled";
		};

		serial_2: serial@13820000 {
			compatible = "samsung,exynos5433-uart";
			reg = <0x13820000 0x100>;
			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&uart2_bus>;
			clocks = <&cmu_peri CLK_GOUT_UART2_PCLK>,
				 <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>;
			clock-names = "uart", "clk_uart_baud0";
			samsung,uart-fifosize = <256>;
			status = "disabled";
		};

		i2c_0: i2c@13830000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13830000 0x100>;
			interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_bus>;
			clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		i2c_1: i2c@13840000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13840000 0x100>;
			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_bus>;
			clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		i2c_2: i2c@13850000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13850000 0x100>;
			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_bus>;
			clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		i2c_3: i2c@13860000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13860000 0x100>;
			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_bus>;
			clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		i2c_4: i2c@13870000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13870000 0x100>;
			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4_bus>;
			clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		i2c_5: i2c@13880000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13880000 0x100>;
			interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c5_bus>;
			clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		i2c_6: i2c@13890000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13890000 0x100>;
			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c6_bus>;
			clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		i2c_7: i2c@11cd0000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x11cd0000 0x100>;
			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c7_bus>;
			clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};
	};
};

#include "exynos7885-pinctrl.dtsi"
#include "arm/exynos-syscon-restart.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * WinLink E850-96 board device tree source
 *
 * Copyright (C) 2018 Samsung Electronics Co., Ltd.
 * Copyright (C) 2021 Linaro Ltd.
 *
 * Device tree source file for WinLink's E850-96 board which is based on
 * Samsung Exynos850 SoC.
 */

/dts-v1/;

#include "exynos850.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

/ {
	model = "WinLink E850-96 board";
	compatible = "winlink,e850-96", "samsung,exynos850";

	aliases {
		mmc0 = &mmc_0;
		serial0 = &serial_0;
	};

	chosen {
		stdout-path = &serial_0;
	};

	/*
	 * RAM: 4 GiB (eMCP):
	 *   - 2 GiB at 0x80000000
	 *   - 2 GiB at 0x880000000
	 *
	 * 0xbab00000..0xbfffffff: secure memory (85 MiB).
	 */
	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x3ab00000>,
		      <0x0 0xc0000000 0x40000000>,
		      <0x8 0x80000000 0x80000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&key_voldown_pins &key_volup_pins>;

		volume-down-key {
			label = "Volume Down";
			linux,code = <KEY_VOLUMEDOWN>;
			gpios = <&gpa1 0 GPIO_ACTIVE_LOW>;
		};

		volume-up-key {
			label = "Volume Up";
			linux,code = <KEY_VOLUMEUP>;
			gpios = <&gpa0 7 GPIO_ACTIVE_LOW>;
		};
	};

	leds {
		compatible = "gpio-leds";

		/* HEART_BEAT_LED */
		user_led1: led-1 {
			label = "yellow:user1";
			gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_YELLOW>;
			function = LED_FUNCTION_HEARTBEAT;
			linux,default-trigger = "heartbeat";
		};

		/* eMMC_LED */
		user_led2: led-2 {
			label = "yellow:user2";
			gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_YELLOW>;
			linux,default-trigger = "mmc0";
		};

		/* SD_LED */
		user_led3: led-3 {
			label = "white:user3";
			gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_WHITE>;
			function = LED_FUNCTION_SD;
			linux,default-trigger = "mmc2";
		};

		/* WIFI_LED */
		wlan_active_led: led-4 {
			label = "yellow:wlan";
			gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_YELLOW>;
			function = LED_FUNCTION_WLAN;
			linux,default-trigger = "phy0tx";
			default-state = "off";
		};

		/* BLUETOOTH_LED */
		bt_active_led: led-5 {
			label = "blue:bt";
			gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>;
			color = <LED_COLOR_ID_BLUE>;
			function = LED_FUNCTION_BLUETOOTH;
			linux,default-trigger = "hci0rx";
			default-state = "off";
		};
	};

	/*
	 * RTC clock (XrtcXTI); external, must be 32.768 kHz.
	 *
	 * TODO: Remove this once RTC clock is implemented properly as part of
	 *       PMIC driver.
	 */
	rtcclk: clock-rtcclk {
		compatible = "fixed-clock";
		clock-output-names = "rtcclk";
		#clock-cells = <0>;
		clock-frequency = <32768>;
	};
};

&cmu_hsi {
	clocks = <&oscclk>, <&rtcclk>,
		 <&cmu_top CLK_DOUT_HSI_BUS>,
		 <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
		 <&cmu_top CLK_DOUT_HSI_USB20DRD>;
	clock-names = "oscclk", "rtcclk", "dout_hsi_bus",
		      "dout_hsi_mmc_card", "dout_hsi_usb20drd";
};

&mmc_0 {
	status = "okay";
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	cap-mmc-highspeed;
	non-removable;
	mmc-hs400-enhanced-strobe;
	card-detect-delay = <200>;
	clock-frequency = <800000000>;
	bus-width = <8>;
	samsung,dw-mshc-ciu-div = <3>;
	samsung,dw-mshc-sdr-timing = <0 4>;
	samsung,dw-mshc-ddr-timing = <2 4>;
	samsung,dw-mshc-hs400-timing = <0 2>;

	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins
		     &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>;
};

&oscclk {
	clock-frequency = <26000000>;
};

&pinctrl_alive {
	key_voldown_pins: key-voldown-pins {
		samsung,pins = "gpa1-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	key_volup_pins: key-volup-pins {
		samsung,pins = "gpa0-7";
		samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};
};

&rtc {
	status = "okay";
	clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>;
	clock-names = "rtc", "rtc_src";
};

&serial_0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
};

&usi_uart {
	samsung,clkreq-on; /* needed for UART mode */
	status = "okay";
};

&watchdog_cl0 {
	status = "okay";
};

&watchdog_cl1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
 *
 * Copyright (C) 2017 Samsung Electronics Co., Ltd.
 * Copyright (C) 2021 Linaro Ltd.
 *
 * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
 * tree nodes in this file.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "exynos-pinctrl.h"

&pinctrl_alive {
	gpa0: gpa0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpa1: gpa1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpa2: gpa2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpa3: gpa3-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpa4: gpa4-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpq0: gpq0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	/* I2C5 (also called CAM_PMIC_I2C in TRM) */
	i2c5_pins: i2c5-pins {
		samsung,pins = "gpa3-5", "gpa3-6";
		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* I2C6 (also called MOTOR_I2C in TRM) */
	i2c6_pins: i2c6-pins {
		samsung,pins = "gpa3-7", "gpa4-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* USI: UART_DEBUG_0 pins */
	uart0_pins: uart0-pins {
		samsung,pins = "gpq0-0", "gpq0-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	/* USI: UART_DEBUG_1 pins */
	uart1_pins: uart1-pins {
		samsung,pins = "gpa3-7", "gpa4-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};
};

&pinctrl_cmgp {
	gpm0: gpm0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpm1: gpm1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpm2: gpm2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpm3: gpm3-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpm4: gpm4-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpm5: gpm5-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpm6: gpm6-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpm7: gpm7-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	};

	/* USI_CMGP0: HSI2C function */
	hsi2c3_pins: hsi2c3-pins {
		samsung,pins = "gpm0-0", "gpm1-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* USI_CMGP0: UART function (4 pins, Auto Flow Control) */
	uart1_single_pins: uart1-single-pins {
		samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	/* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */
	uart1_dual_pins: uart1-dual-pins {
		samsung,pins = "gpm0-0", "gpm1-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	/* USI_CMGP0: SPI function */
	spi1_pins: spi1-pins {
		samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* USI_CMGP1: HSI2C function */
	hsi2c4_pins: hsi2c4-pins {
		samsung,pins = "gpm4-0", "gpm5-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* USI_CMGP1: UART function (4 pins, Auto Flow Control) */
	uart2_single_pins: uart2-single-pins {
		samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	/* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */
	uart2_dual_pins: uart2-dual-pins {
		samsung,pins = "gpm4-0", "gpm5-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};

	/* USI_CMGP1: SPI function */
	spi2_pins: spi2-pins {
		samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};
};

&pinctrl_aud {
	gpb0: gpb0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpb1: gpb1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	aud_codec_mclk_pins: aud-codec-mclk-pins {
		samsung,pins = "gpb0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins {
		samsung,pins = "gpb0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_i2s0_pins: aud-i2s0-pins {
		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_i2s0_idle_pins: aud-i2s0-idle-pins {
		samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_i2s1_pins: aud-i2s1-pins {
		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_i2s1_idle_pins: aud-i2s1-idle-pins {
		samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_fm_pins: aud-fm-pins {
		samsung,pins = "gpb1-4";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};

	aud_fm_idle_pins: aud-fm-idle-pins {
		samsung,pins = "gpb1-4";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};
};

&pinctrl_hsi {
	gpf2: gpf2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	sd2_clk_pins: sd2-clk-pins {
		samsung,pins = "gpf2-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
	};

	sd2_cmd_pins: sd2-cmd-pins {
		samsung,pins = "gpf2-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
	 };

	sd2_bus1_pins: sd2-bus1-pins {
		samsung,pins = "gpf2-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
	};

	sd2_bus4_pins: sd2-bus4-pins {
		samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS850_HSI_PIN_DRV_LV2>;
	};

	sd2_pdn_pins: sd2-pdn-pins {
		samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
			       "gpf2-4", "gpf2-5";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
	};
};

&pinctrl_core {
	gpf0: gpf0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpf1: gpf1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	sd0_clk_pins: sd0-clk-pins {
		samsung,pins = "gpf0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd0_cmd_pins: sd0-cmd-pins {
		samsung,pins = "gpf0-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd0_rdqs_pins: sd0-rdqs-pins {
		samsung,pins = "gpf0-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd0_nreset_pins: sd0-nreset-pins {
		samsung,pins = "gpf0-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd0_bus1_pins: sd0-bus1-pins {
		samsung,pins = "gpf1-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd0_bus4_pins: sd0-bus4-pins {
		samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};

	sd0_bus8_pins: sd0-bus8-pins {
		samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
	};
};

&pinctrl_peri {
	gpc0: gpc0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpc1: gpc1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpg0: gpg0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpg1: gpg1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpg2: gpg2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpg3: gpg3-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpp0: gpp0-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};
	gpp1: gpp1-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpp2: gpp2-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	sensor_mclk0_in_pins: sensor-mclk0-in-pins {
		samsung,pins = "gpc0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sensor_mclk0_out_pins: sensor-mclk0-out-pins {
		samsung,pins = "gpc0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sensor_mclk0_fn_pins: sensor-mclk0-fn-pins {
		samsung,pins = "gpc0-0";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sensor_mclk1_in_pins: sensor-mclk1-in-pins {
		samsung,pins = "gpc0-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sensor_mclk1_out_pins: sensor-mclk1-out-pins {
		samsung,pins = "gpc0-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sensor_mclk1_fn_pins: sensor-mclk1-fn-pins {
		samsung,pins = "gpc0-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sensor_mclk2_in_pins: sensor-mclk2-in-pins {
		samsung,pins = "gpc0-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sensor_mclk2_out_pins: sensor-mclk2-out-pins {
		samsung,pins = "gpc0-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	sensor_mclk2_fn_pins: sensor-mclk2-fn-pins {
		samsung,pins = "gpc0-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV3>;
	};

	/* USI: HSI2C0 */
	hsi2c0_pins: hsi2c0-pins {
		samsung,pins = "gpc1-0", "gpc1-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* USI: HSI2C1 */
	hsi2c1_pins: hsi2c1-pins {
		samsung,pins = "gpc1-2", "gpc1-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* USI: HSI2C2 */
	hsi2c2_pins: hsi2c2-pins {
		samsung,pins = "gpc1-4", "gpc1-5";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	/* USI: SPI */
	spi0_pins: spi0-pins {
		samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	i2c0_pins: i2c0-pins {
		samsung,pins = "gpp0-0", "gpp0-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	i2c1_pins: i2c1-pins {
		samsung,pins = "gpp0-2", "gpp0-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	i2c2_pins: i2c2-pins {
		samsung,pins = "gpp0-4", "gpp0-5";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	i2c3_pins: i2c3-pins {
		samsung,pins = "gpp1-0", "gpp1-1";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	i2c4_pins: i2c4-pins {
		samsung,pins = "gpp1-2", "gpp1-3";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
		samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
	};

	xclkout_pins: xclkout-pins {
		samsung,pins = "gpq0-2";
		samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
		samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung Exynos850 SoC device tree source
 *
 * Copyright (C) 2018 Samsung Electronics Co., Ltd.
 * Copyright (C) 2021 Linaro Ltd.
 *
 * Samsung Exynos850 SoC device nodes are listed in this file.
 * Exynos850 based board files can include this file and provide
 * values for board specific bindings.
 */

#include <dt-bindings/clock/exynos850.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/samsung,exynos-usi.h>

/ {
	/* Also known under engineering name Exynos3830 */
	compatible = "samsung,exynos850";
	#address-cells = <2>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	aliases {
		pinctrl0 = &pinctrl_alive;
		pinctrl1 = &pinctrl_cmgp;
		pinctrl2 = &pinctrl_aud;
		pinctrl3 = &pinctrl_hsi;
		pinctrl4 = &pinctrl_core;
		pinctrl5 = &pinctrl_peri;
	};

	arm-pmu {
		compatible = "arm,cortex-a55-pmu";
		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
				     <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
	};

	/* Main system clock (XTCXO); external, must be 26 MHz */
	oscclk: clock-oscclk {
		compatible = "fixed-clock";
		clock-output-names = "oscclk";
		#clock-cells = <0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0>;
			enable-method = "psci";
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x1>;
			enable-method = "psci";
		};
		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x2>;
			enable-method = "psci";
		};
		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x3>;
			enable-method = "psci";
		};
		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x100>;
			enable-method = "psci";
		};
		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x101>;
			enable-method = "psci";
		};
		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x102>;
			enable-method = "psci";
		};
		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x103>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		/* Hypervisor Virtual Timer interrupt is not wired to GIC */
		interrupts =
		     <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
		     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
		     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
		     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	soc: soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x20000000>;

		chipid@10000000 {
			compatible = "samsung,exynos850-chipid";
			reg = <0x10000000 0x100>;
		};

		timer@10040000 {
			compatible = "samsung,exynos850-mct",
				     "samsung,exynos4210-mct";
			reg = <0x10040000 0x800>;
			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>;
			clock-names = "fin_pll", "mct";
		};

		gic: interrupt-controller@12a01000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			reg = <0x12a01000 0x1000>,
			      <0x12a02000 0x2000>,
			      <0x12a04000 0x2000>,
			      <0x12a06000 0x2000>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
						 IRQ_TYPE_LEVEL_HIGH)>;
		};

		pmu_system_controller: system-controller@11860000 {
			compatible = "samsung,exynos850-pmu", "syscon";
			reg = <0x11860000 0x10000>;
			clocks = <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>;

			reboot: syscon-reboot {
				compatible = "syscon-reboot";
				regmap = <&pmu_system_controller>;
				offset = <0x3a00>; /* SYSTEM_CONFIGURATION */
				mask = <0x2>; /* SWRESET_SYSTEM */
				value = <0x2>; /* reset value */
			};
		};

		watchdog_cl0: watchdog@10050000 {
			compatible = "samsung,exynos850-wdt";
			reg = <0x10050000 0x100>;
			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;
			clock-names = "watchdog", "watchdog_src";
			samsung,syscon-phandle = <&pmu_system_controller>;
			samsung,cluster-index = <0>;
			status = "disabled";
		};

		watchdog_cl1: watchdog@10060000 {
			compatible = "samsung,exynos850-wdt";
			reg = <0x10060000 0x100>;
			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>;
			clock-names = "watchdog", "watchdog_src";
			samsung,syscon-phandle = <&pmu_system_controller>;
			samsung,cluster-index = <1>;
			status = "disabled";
		};

		cmu_peri: clock-controller@10030000 {
			compatible = "samsung,exynos850-cmu-peri";
			reg = <0x10030000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
				 <&cmu_top CLK_DOUT_PERI_UART>,
				 <&cmu_top CLK_DOUT_PERI_IP>;
			clock-names = "oscclk", "dout_peri_bus",
				      "dout_peri_uart", "dout_peri_ip";
		};

		cmu_apm: clock-controller@11800000 {
			compatible = "samsung,exynos850-cmu-apm";
			reg = <0x11800000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>;
			clock-names = "oscclk", "dout_clkcmu_apm_bus";
		};

		cmu_cmgp: clock-controller@11c00000 {
			compatible = "samsung,exynos850-cmu-cmgp";
			reg = <0x11c00000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>;
			clock-names = "oscclk", "gout_clkcmu_cmgp_bus";
		};

		cmu_core: clock-controller@12000000 {
			compatible = "samsung,exynos850-cmu-core";
			reg = <0x12000000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>,
				 <&cmu_top CLK_DOUT_CORE_CCI>,
				 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>,
				 <&cmu_top CLK_DOUT_CORE_SSS>;
			clock-names = "oscclk", "dout_core_bus",
				      "dout_core_cci", "dout_core_mmc_embd",
				      "dout_core_sss";
		};

		cmu_top: clock-controller@120e0000 {
			compatible = "samsung,exynos850-cmu-top";
			reg = <0x120e0000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>;
			clock-names = "oscclk";
		};

		cmu_mfcmscl: clock-controller@12c00000 {
			compatible = "samsung,exynos850-cmu-mfcmscl";
			reg = <0x12c00000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>,
				 <&cmu_top CLK_DOUT_MFCMSCL_MFC>,
				 <&cmu_top CLK_DOUT_MFCMSCL_M2M>,
				 <&cmu_top CLK_DOUT_MFCMSCL_MCSC>,
				 <&cmu_top CLK_DOUT_MFCMSCL_JPEG>;
			clock-names = "oscclk", "dout_mfcmscl_mfc",
				      "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc",
				      "dout_mfcmscl_jpeg";
		};

		cmu_dpu: clock-controller@13000000 {
			compatible = "samsung,exynos850-cmu-dpu";
			reg = <0x13000000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>;
			clock-names = "oscclk", "dout_dpu";
		};

		cmu_hsi: clock-controller@13400000 {
			compatible = "samsung,exynos850-cmu-hsi";
			reg = <0x13400000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>,
				 <&cmu_top CLK_DOUT_HSI_BUS>,
				 <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
				 <&cmu_top CLK_DOUT_HSI_USB20DRD>;
			clock-names = "oscclk", "dout_hsi_bus",
				      "dout_hsi_mmc_card", "dout_hsi_usb20drd";
		};

		cmu_is: clock-controller@14500000 {
			compatible = "samsung,exynos850-cmu-is";
			reg = <0x14500000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>,
				 <&cmu_top CLK_DOUT_IS_BUS>,
				 <&cmu_top CLK_DOUT_IS_ITP>,
				 <&cmu_top CLK_DOUT_IS_VRA>,
				 <&cmu_top CLK_DOUT_IS_GDC>;
			clock-names = "oscclk", "dout_is_bus", "dout_is_itp",
				      "dout_is_vra", "dout_is_gdc";
		};

		cmu_aud: clock-controller@14a00000 {
			compatible = "samsung,exynos850-cmu-aud";
			reg = <0x14a00000 0x8000>;
			#clock-cells = <1>;

			clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>;
			clock-names = "oscclk", "dout_aud";
		};

		pinctrl_alive: pinctrl@11850000 {
			compatible = "samsung,exynos850-pinctrl";
			reg = <0x11850000 0x1000>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos850-wakeup-eint";
			};
		};

		pinctrl_cmgp: pinctrl@11c30000 {
			compatible = "samsung,exynos850-pinctrl";
			reg = <0x11c30000 0x1000>;

			wakeup-interrupt-controller {
				compatible = "samsung,exynos850-wakeup-eint";
			};
		};

		pinctrl_core: pinctrl@12070000 {
			compatible = "samsung,exynos850-pinctrl";
			reg = <0x12070000 0x1000>;
			interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_hsi: pinctrl@13430000 {
			compatible = "samsung,exynos850-pinctrl";
			reg = <0x13430000 0x1000>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_peri: pinctrl@139b0000 {
			compatible = "samsung,exynos850-pinctrl";
			reg = <0x139b0000 0x1000>;
			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		};

		pinctrl_aud: pinctrl@14a60000 {
			compatible = "samsung,exynos850-pinctrl";
			reg = <0x14a60000 0x1000>;
		};

		rtc: rtc@11a30000 {
			compatible = "samsung,s3c6410-rtc";
			reg = <0x11a30000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>;
			clock-names = "rtc";
			status = "disabled";
		};

		mmc_0: mmc@12100000 {
			compatible = "samsung,exynos7-dw-mshc-smu";
			reg = <0x12100000 0x2000>;
			interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>,
				 <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>;
			clock-names = "biu", "ciu";
			fifo-depth = <0x40>;
			status = "disabled";
		};

		i2c_0: i2c@13830000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13830000 0x100>;
			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_pins>;
			clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		i2c_1: i2c@13840000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13840000 0x100>;
			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_pins>;
			clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		i2c_2: i2c@13850000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13850000 0x100>;
			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_pins>;
			clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		i2c_3: i2c@13860000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13860000 0x100>;
			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_pins>;
			clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		i2c_4: i2c@13870000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13870000 0x100>;
			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4_pins>;
			clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		/* I2C_5 (also called CAM_PMIC_I2C in TRM) */
		i2c_5: i2c@13880000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13880000 0x100>;
			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c5_pins>;
			clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		/* I2C_6 (also called MOTOR_I2C in TRM) */
		i2c_6: i2c@13890000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x13890000 0x100>;
			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c6_pins>;
			clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
			clock-names = "i2c";
			status = "disabled";
		};

		sysmmu_mfcmscl: sysmmu@12c50000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x12c50000 0x9000>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "sysmmu";
			clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>;
			#iommu-cells = <0>;
		};

		sysmmu_dpu: sysmmu@130c0000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x130c0000 0x9000>;
			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "sysmmu";
			clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>;
			#iommu-cells = <0>;
		};

		sysmmu_is0: sysmmu@14550000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x14550000 0x9000>;
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "sysmmu";
			clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>;
			#iommu-cells = <0>;
		};

		sysmmu_is1: sysmmu@14570000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x14570000 0x9000>;
			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "sysmmu";
			clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>;
			#iommu-cells = <0>;
		};

		sysmmu_aud: sysmmu@14850000 {
			compatible = "samsung,exynos-sysmmu";
			reg = <0x14850000 0x9000>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "sysmmu";
			clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>;
			#iommu-cells = <0>;
		};

		sysreg_peri: syscon@10020000 {
			compatible = "samsung,exynos850-sysreg", "syscon";
			reg = <0x10020000 0x10000>;
			clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>;
		};

		sysreg_cmgp: syscon@11c20000 {
			compatible = "samsung,exynos850-sysreg", "syscon";
			reg = <0x11c20000 0x10000>;
			clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
		};

		usi_uart: usi@138200c0 {
			compatible = "samsung,exynos850-usi";
			reg = <0x138200c0 0x20>;
			samsung,sysreg = <&sysreg_peri 0x1010>;
			samsung,mode = <USI_V2_UART>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
				 <&cmu_peri CLK_GOUT_UART_IPCLK>;
			clock-names = "pclk", "ipclk";
			status = "disabled";

			serial_0: serial@13820000 {
				compatible = "samsung,exynos850-uart";
				reg = <0x13820000 0xc0>;
				interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&uart0_pins>;
				clocks = <&cmu_peri CLK_GOUT_UART_PCLK>,
					 <&cmu_peri CLK_GOUT_UART_IPCLK>;
				clock-names = "uart", "clk_uart_baud0";
				status = "disabled";
			};
		};

		usi_hsi2c_0: usi@138a00c0 {
			compatible = "samsung,exynos850-usi";
			reg = <0x138a00c0 0x20>;
			samsung,sysreg = <&sysreg_peri 0x1020>;
			samsung,mode = <USI_V2_I2C>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>,
				 <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>;
			clock-names = "pclk", "ipclk";
			status = "disabled";

			hsi2c_0: i2c@138a0000 {
				compatible = "samsung,exynosautov9-hsi2c";
				reg = <0x138a0000 0xc0>;
				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				pinctrl-names = "default";
				pinctrl-0 = <&hsi2c0_pins>;
				clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>,
					 <&cmu_peri CLK_GOUT_HSI2C0_PCLK>;
				clock-names = "hsi2c", "hsi2c_pclk";
				status = "disabled";
			};
		};

		usi_hsi2c_1: usi@138b00c0 {
			compatible = "samsung,exynos850-usi";
			reg = <0x138b00c0 0x20>;
			samsung,sysreg = <&sysreg_peri 0x1030>;
			samsung,mode = <USI_V2_I2C>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>,
				 <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>;
			clock-names = "pclk", "ipclk";
			status = "disabled";

			hsi2c_1: i2c@138b0000 {
				compatible = "samsung,exynosautov9-hsi2c";
				reg = <0x138b0000 0xc0>;
				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				pinctrl-names = "default";
				pinctrl-0 = <&hsi2c1_pins>;
				clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>,
					 <&cmu_peri CLK_GOUT_HSI2C1_PCLK>;
				clock-names = "hsi2c", "hsi2c_pclk";
				status = "disabled";
			};
		};

		usi_hsi2c_2: usi@138c00c0 {
			compatible = "samsung,exynos850-usi";
			reg = <0x138c00c0 0x20>;
			samsung,sysreg = <&sysreg_peri 0x1040>;
			samsung,mode = <USI_V2_I2C>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>,
				 <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>;
			clock-names = "pclk", "ipclk";
			status = "disabled";

			hsi2c_2: i2c@138c0000 {
				compatible = "samsung,exynosautov9-hsi2c";
				reg = <0x138c0000 0xc0>;
				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				pinctrl-names = "default";
				pinctrl-0 = <&hsi2c2_pins>;
				clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>,
					 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>;
				clock-names = "hsi2c", "hsi2c_pclk";
				status = "disabled";
			};
		};

		usi_spi_0: usi@139400c0 {
			compatible = "samsung,exynos850-usi";
			reg = <0x139400c0 0x20>;
			samsung,sysreg = <&sysreg_peri 0x1050>;
			samsung,mode = <USI_V2_SPI>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>,
				 <&cmu_peri CLK_GOUT_SPI0_IPCLK>;
			clock-names = "pclk", "ipclk";
			status = "disabled";
		};

		usi_cmgp0: usi@11d000c0 {
			compatible = "samsung,exynos850-usi";
			reg = <0x11d000c0 0x20>;
			samsung,sysreg = <&sysreg_cmgp 0x2000>;
			samsung,mode = <USI_V2_I2C>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
				 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
			clock-names = "pclk", "ipclk";
			status = "disabled";

			hsi2c_3: i2c@11d00000 {
				compatible = "samsung,exynosautov9-hsi2c";
				reg = <0x11d00000 0xc0>;
				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				pinctrl-names = "default";
				pinctrl-0 = <&hsi2c3_pins>;
				clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>,
					 <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>;
				clock-names = "hsi2c", "hsi2c_pclk";
				status = "disabled";
			};

			serial_1: serial@11d00000 {
				compatible = "samsung,exynos850-uart";
				reg = <0x11d00000 0xc0>;
				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&uart1_single_pins>;
				clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>,
					 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>;
				clock-names = "uart", "clk_uart_baud0";
				status = "disabled";
			};
		};

		usi_cmgp1: usi@11d200c0 {
			compatible = "samsung,exynos850-usi";
			reg = <0x11d200c0 0x20>;
			samsung,sysreg = <&sysreg_cmgp 0x2010>;
			samsung,mode = <USI_V2_I2C>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
				 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
			clock-names = "pclk", "ipclk";
			status = "disabled";

			hsi2c_4: i2c@11d20000 {
				compatible = "samsung,exynosautov9-hsi2c";
				reg = <0x11d20000 0xc0>;
				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				pinctrl-names = "default";
				pinctrl-0 = <&hsi2c4_pins>;
				clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>,
					 <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>;
				clock-names = "hsi2c", "hsi2c_pclk";
				status = "disabled";
			};

			serial_2: serial@11d20000 {
				compatible = "samsung,exynos850-uart";
				reg = <0x11d20000 0xc0>;
				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&uart2_single_pins>;
				clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>,
					 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>;
				clock-names = "uart", "clk_uart_baud0";
				status = "disabled";
			};
		};
	};
};

#include "exynos850-pinctrl.dtsi"