code:
Qualcomm APQ8084 TLMM block

This binding describes the Top Level Mode Multiplexer block found in the
MSM8960 platform.

- compatible:
	Usage: required
	Value type: <string>
	Definition: must be "qcom,apq8084-pinctrl"

- reg:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: the base address and size of the TLMM register space.

- interrupts:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: should specify the TLMM summary IRQ.

- interrupt-controller:
	Usage: required
	Value type: <none>
	Definition: identifies this node as an interrupt controller

- #interrupt-cells:
	Usage: required
	Value type: <u32>
	Definition: must be 2. Specifying the pin number and flags, as defined
		    in <dt-bindings/interrupt-controller/irq.h>

- gpio-controller:
	Usage: required
	Value type: <none>
	Definition: identifies this node as a gpio controller

- #gpio-cells:
	Usage: required
	Value type: <u32>
	Definition: must be 2. Specifying the pin number and flags, as defined
		    in <dt-bindings/gpio/gpio.h>

- gpio-ranges:
	Usage: required
	Definition:  see ../gpio/gpio.txt

- gpio-reserved-ranges:
	Usage: optional
	Definition: see ../gpio/gpio.txt

Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.

PIN CONFIGURATION NODES:

The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.

The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:

- pins:
	Usage: required
	Value type: <string-array>
	Definition: List of gpio pins affected by the properties specified in
		    this subnode.  Valid pins are:
		    gpio0-gpio146,
		    sdc1_clk,
		    sdc1_cmd,
		    sdc1_data
		    sdc2_clk,
		    sdc2_cmd,
		    sdc2_data

- function:
	Usage: required
	Value type: <string>
	Definition: Specify the alternative function to be configured for the
		    specified pins. Functions are only valid for gpio pins.
		    Valid values are:
		    adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
		    blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
		    blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
		    blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
		    blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
		    blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3,
		    blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8,
		    blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
		    blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
		    blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
		    blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2,
		    cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
		    cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
		    edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i
		    gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio,
		    hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic,
		    ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst,
		    pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
		    qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
		    sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
		    spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1,
		    tsif2, uim, uim_batt_alarm

- bias-disable:
	Usage: optional
	Value type: <none>
	Definition: The specified pins should be configured as no pull.

- bias-pull-down:
	Usage: optional
	Value type: <none>
	Definition: The specified pins should be configured as pull down.

- bias-pull-up:
	Usage: optional
	Value type: <none>
	Definition: The specified pins should be configured as pull up.

- output-high:
	Usage: optional
	Value type: <none>
	Definition: The specified pins are configured in output mode, driven
		    high.
		    Not valid for sdc pins.

- output-low:
	Usage: optional
	Value type: <none>
	Definition: The specified pins are configured in output mode, driven
		    low.
		    Not valid for sdc pins.

- drive-strength:
	Usage: optional
	Value type: <u32>
	Definition: Selects the drive strength for the specified pins, in mA.
		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16

Example:

	tlmm: pinctrl@fd510000 {
		compatible = "qcom,apq8084-pinctrl";
		reg = <0xfd510000 0x4000>;

		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&tlmm 0 0 147>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <0 208 0>;

		uart2: uart2-default {
			mux {
				pins = "gpio4", "gpio5";
				function = "blsp_uart2";
			};

			tx {
				pins = "gpio4";
				drive-strength = <4>;
				bias-disable;
			};

			rx {
				pins = "gpio5";
				drive-strength = <2>;
				bias-pull-up;
			};
		};
	};


code:
Qualcomm Atheros IPQ4019 TLMM block

This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.

Required properties:
- compatible: "qcom,ipq4019-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
                The first cell is the gpio pin number and the
                second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt

Optional properties:

- gpio-reserved-ranges: see ../gpio/gpio.txt

Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.

The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.

The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
 pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,
 drive-strength.

Non-empty subnodes must specify the 'pins' property.
Note that not all properties are valid for all pins.

Valid values for qcom,pins are:
  gpio0-gpio99
    Supports mux, bias and drive-strength

Valid values for qcom,function are:
aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0,
blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11,
mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
smart2, smart3, tm, wifi0, wifi1

Example:

	tlmm: pinctrl@1000000 {
		compatible = "qcom,ipq4019-pinctrl";
		reg = <0x1000000 0x300000>;

		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&tlmm 0 0 100>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <0 208 0>;

		serial_pins: serial_pinmux {
			mux {
				pins = "gpio60", "gpio61";
				function = "blsp_uart0";
				bias-disable;
			};
		};
	};

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq6018-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. IPQ6018 TLMM block

maintainers:
  - Bjorn Andersson <andersson@kernel.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm IPQ6018 SoC.

properties:
  compatible:
    const: qcom,ipq6018-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-ipq6018-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-ipq6018-tlmm-state"
        additionalProperties: false

$defs:
  qcom-ipq6018-tlmm-state:
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
                      qdsd_data3 ]
        minItems: 1
        maxItems: 16

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.
        enum: [ adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char,
                atest_char0, atest_char1, atest_char2, atest_char3, atest_combodac,
                atest_gpsadc0, atest_gpsadc1, atest_tsens, atest_wlan0,
                atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, blsp0_i2c, blsp1_i2c,
                blsp2_i2c, blsp3_i2c, blsp4_i2c, blsp5_i2c, blsp0_spi, blsp1_spi,
                blsp1_spi_cs1, blsp1_spi_cs2, blsp1_spi_cs3, blsp2_spi,
                blsp2_spi_cs1, blsp2_spi_cs2, blsp2_spi_cs3, blsp3_spi,
                blsp3_spi_cs1, blsp3_spi_cs2, blsp3_spi_cs3, blsp4_spi, blsp5_spi,
                blsp0_uart, blsp1_uart, blsp2_uart, blsp1_uim, blsp2_uim, cam1_rst,
                cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0,
                cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, display_5v,
                dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us, ext_lpass,
                flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
                gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gpio, gsm0_tx0,
                gsm0_tx1, gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, kpsns1, kpsns2,
                ldo_en, ldo_update, mag_int, mdp_vsync, modem_tsync, m_voc,
                nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2, pri_mi2s,
                pri_mi2s_ws, prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
                pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
                pwr_nav_enabled_b, qdss_ctitrig_in_a0, qdss_ctitrig_in_a1,
                qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0,
                qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1,
                qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
                qdss_tracedata_a, qdss_tracedata_b, qpic_pad, reset_n, sd_card,
                sd_write, sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, uim1, uim2,
                uim3, uim_batt, wcss_bt, wcss_fm, wcss_wlan, webcam1_rst ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@1000000 {
        compatible = "qcom,ipq6018-pinctrl";
        reg = <0x01000000 0x300000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&tlmm 0 0 80>;

        serial3-state {
            pins = "gpio44", "gpio45";
            function = "blsp2_uart";
            drive-strength = <8>;
            bias-pull-down;
        };
    };


code:
Qualcomm IPQ8064 TLMM block

Required properties:
- compatible: "qcom,ipq8064-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
                The first cell is the gpio pin number and the
                second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt

Optional properties:

- gpio-reserved-ranges: see ../gpio/gpio.txt

Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

Qualcomm's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.

The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.

The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:

 pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength,
 output-low, output-high.

Non-empty subnodes must specify the 'pins' property.

Valid values for qcom,pins are:
  gpio0-gpio68
   Supports mux, bias, and drive-strength

  sdc3_clk, sdc3_cmd, sdc3_data
   Supports bias and drive-strength

Valid values for function are:
  mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
  gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
  spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
  pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
  pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
  pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
  pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold

Example:

	pinmux: pinctrl@800000 {
		compatible = "qcom,ipq8064-pinctrl";
		reg = <0x800000 0x4000>;

		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&pinmux 0 0 69>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <0 32 0x4>;

		pinctrl-names = "default";
		pinctrl-0 = <&gsbi5_uart_default>;

		gsbi5_uart_default: gsbi5_uart_default {
			mux {
				pins = "gpio18", "gpio19";
				function = "gsbi5";
			};

			tx {
				pins = "gpio18";
				drive-strength = <4>;
				bias-disable;
			};

			rx {
				pins = "gpio19";
				drive-strength = <2>;
				bias-pull-up;
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm IPQ8074 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC.

properties:
  compatible:
    const: qcom,ipq8074-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 35

  gpio-line-names:
    maxItems: 70

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-ipq8074-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-ipq8074-tlmm-state"
        additionalProperties: false

$defs:
  qcom-ipq8074-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          pattern: "^gpio([0-9]|[1-6][0-9]|70)$"
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2,
                atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync,
                audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync,
                audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c,
                blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart,
                blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2,
                blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0,
                blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi,
                blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, cxc0,
                cxc1, dbg_out, gcc_plltest, gcc_tlmm, ldo_en, ldo_update, led0,
                led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, mac1_sa1, mac1_sa2,
                mac1_sa3, mac2_sa0, mac2_sa1, mdc, mdio, pcie0_clk, pcie0_rst,
                pcie0_wake, pcie1_clk, pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx,
                pcm_fsync, pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0,
                pta1_1, pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3,
                qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
                qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
                qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
                qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
                qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
                qdss_tracedata_b, qpic, rx0, rx1, rx2, sd_card, sd_write,
                tsens_max, wci2a, wci2b, wci2c, wci2d ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@1000000 {
        compatible = "qcom,ipq8074-pinctrl";
        reg = <0x01000000 0x300000>;
        gpio-controller;
        #gpio-cells = <0x2>;
        gpio-ranges = <&tlmm 0 0 70>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <0x2>;

        serial4-state {
            pins = "gpio23", "gpio24";
            function = "blsp4_uart1";
            drive-strength = <8>;
            bias-disable;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. MDM9607 TLMM block

maintainers:
  - Konrad Dybcio <konrad.dybcio@somainline.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm MDM9607 SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,mdm9607-tlmm

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  gpio-reserved-ranges: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

required:
  - compatible
  - reg

additionalProperties: false

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-mdm9607-tlmm-state"
      - patternProperties:
          ".*":
            $ref: "#/$defs/qcom-mdm9607-tlmm-state"

$defs:
  qcom-mdm9607-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
                      qdsd_data3 ]
        minItems: 1
        maxItems: 16

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
                atest_char1, atest_char2, atest_char3,
                atest_combodac_to_gpio_native, atest_gpsadc_dtest0_native,
                atest_gpsadc_dtest1_native, atest_tsens, backlight_en_b,
                bimc_dte0, bimc_dte1, blsp1_spi, blsp2_spi, blsp3_spi,
                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
                blsp_i2c6, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4,
                blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uart3,
                blsp_uart4, blsp_uart5, blsp_uart6, blsp_uim1, blsp_uim2,
                codec_int, codec_rst, coex_uart, cri_trng, cri_trng0,
                cri_trng1, dbg_out, ebi0_wrcdc, ebi2_a, ebi2_a_d_8_b,
                ebi2_lcd, ebi2_lcd_cs_n_b, ebi2_lcd_te_b, eth_irq, eth_rst,
                gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b,
                gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gmac_mdio,
                gpio, gsm0_tx, lcd_rst, ldo_en, ldo_update, m_voc, modem_tsync,
                nav_ptp_pps_in_a, nav_ptp_pps_in_b, nav_tsync_out_a,
                nav_tsync_out_b, pa_indicator, pbs0, pbs1, pbs2,
                pri_mi2s_data0_a, pri_mi2s_data1_a, pri_mi2s_mclk_a,
                pri_mi2s_sck_a, pri_mi2s_ws_a, prng_rosc, ptp_pps_out_a,
                ptp_pps_out_b, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
                pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
                pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
                qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
                qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
                qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
                qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, rcm_marker1,
                rcm_marker2, sd_write, sec_mi2s, sensor_en, sensor_int2,
                sensor_int3, sensor_rst, ssbi1, ssbi2, touch_rst, ts_int,
                uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
                uim2_data, uim2_present, uim2_reset, uim_batt, wlan_en1, ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@1000000 {
        compatible = "qcom,mdm9607-tlmm";
        reg = <0x01000000 0x300000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        gpio-ranges = <&msmgpio 0 0 80>;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. MDM9615 TLMM block

maintainers:
  - Bjorn Andersson <andersson@kernel.org>

description: Top Level Mode Multiplexer pin controller in Qualcomm MDM9615 SoC.

$ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,mdm9615-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  '#interrupt-cells': true
  gpio-controller: true
  '#gpio-cells': true
  gpio-ranges: true

required:
  - compatible
  - reg

additionalProperties: false

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
        additionalProperties: false

$defs:
  qcom-mdm9615-pinctrl-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          pattern: "^gpio([0-9]|[1-7][0-9]|8[0-7])$"
        minItems: 1
        maxItems: 16

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart,
                sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, cdc_mclk, ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      output-high: true
      output-low: true
      input-enable: true

    required:
      - pins

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@1000000 {
      compatible = "qcom,mdm9615-pinctrl";
      reg = <0x01000000 0x300000>;
      interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
      gpio-controller;
      gpio-ranges = <&msmgpio 0 0 88>;
      #gpio-cells = <2>;
      interrupt-controller;
      #interrupt-cells = <2>;

      gsbi3-state {
        pins = "gpio8", "gpio9", "gpio10", "gpio11";
        function = "gsbi3";
        drive-strength = <8>;
        bias-disable;
      };

      gsbi5-i2c-state {
        sda-pins {
          pins = "gpio16";
          function = "gsbi5_i2c";
          drive-strength = <8>;
          bias-disable;
        };

        scl-pins {
          pins = "gpio17";
          function = "gsbi5_i2c";
          drive-strength = <2>;
          bias-disable;
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. MSM8226 TLMM block

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm MSM8226 SoC.

properties:
  compatible:
    const: qcom,msm8226-pinctrl

  reg:
    description: Specifies the base address and size of the TLMM register space
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true

  gpio-reserved-ranges:
    maxItems: 1

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-msm8226-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-msm8226-tlmm-state"
        additionalProperties: false

$defs:
  qcom-msm8226-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins. Functions are only valid for gpio pins.
        enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_spi1,
                blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
                blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1, sdc3,
                wlan ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    msmgpio: pinctrl@fd510000 {
        compatible = "qcom,msm8226-pinctrl";
        reg = <0xfd510000 0x4000>;

        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&msmgpio 0 0 117>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

        serial-state {
            pins = "gpio8", "gpio9";
            function = "blsp_uart3";
            drive-strength = <8>;
            bias-disable;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8660-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm MSM8660 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm MSM8660 SoC.

properties:
  compatible:
    const: qcom,msm8660-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 86

  gpio-line-names:
    maxItems: 173

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-msm8660-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-msm8660-tlmm-state"
        additionalProperties: false

$defs:
  qcom-msm8660-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-2])$"
            - enum: [ sdc3_clk, sdc3_cmd, sdc3_data, sdc4_clk, sdc4_cmd, sdc4_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a,
                gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n,
                gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2,
                gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, gsbi2_spi_cs3_n, gsbi3,
                gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, gsbi4,
                gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12,
                hdmi, i2s, lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2,
                sdc5, tsif1, tsif2, usb_fs1, usb_fs1_oe_n, usb_fs2,
                usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@800000 {
        compatible = "qcom,msm8660-pinctrl";
        reg = <0x800000 0x4000>;

        gpio-controller;
        gpio-ranges = <&tlmm 0 0 173>;
        #gpio-cells = <2>;
        interrupts = <0 16 0x4>;
        interrupt-controller;
        #interrupt-cells = <2>;

        gsbi3-i2c-state {
            pins = "gpio43", "gpio44";
            function = "gsbi3";
            drive-strength = <8>;
            bias-disable;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8909-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. MSM8909 TLMM block

maintainers:
  - Stephan Gerhold <stephan@gerhold.net>

description: |
  Top Level Mode Multiplexer pin controller in Qualcomm MSM8909 SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,msm8909-tlmm

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  gpio-reserved-ranges: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

required:
  - compatible
  - reg

additionalProperties: false

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-msm8909-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-msm8909-tlmm-state"
        additionalProperties: false

$defs:
  qcom-msm8909-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-7])$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
                      sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1,
                      qdsd_data2, qdsd_data3 ]
        minItems: 1
        maxItems: 16

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.
        enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0,
                atest_char1, atest_char2, atest_char3, atest_combodac,
                atest_gpsadc0, atest_gpsadc1, atest_wlan0, atest_wlan1,
                bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3,
                blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1,
                blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1,
                blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1,
                blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6,
                blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, cam_mclk,
                cci_async, cci_timer0, cci_timer1, cci_timer2, cdc_pdm0,
                dbg_out, dmic0_clk, dmic0_data, ebi0_wrcdc, ebi2_a, ebi2_lcd,
                ext_lpass, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
                gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gpio,
                gsm0_tx, ldo_en, ldo_update, m_voc, mdp_vsync, modem_tsync,
                nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2,
                pri_mi2s_data0_a, pri_mi2s_data0_b, pri_mi2s_data1_a,
                pri_mi2s_data1_b, pri_mi2s_mclk_a, pri_mi2s_mclk_b,
                pri_mi2s_sck_a, pri_mi2s_sck_b, pri_mi2s_ws_a, pri_mi2s_ws_b,
                prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
                pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
                pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
                qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
                qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
                qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,
                qdss_tracedata_a, qdss_tracedata_b, sd_write, sec_mi2s,
                smb_int, ssbi0, ssbi1, uim1_clk, uim1_data, uim1_present,
                uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
                uim3_clk, uim3_data, uim3_present, uim3_reset, uim_batt,
                wcss_bt, wcss_fm, wcss_wlan ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pinctrl@1000000 {
        compatible = "qcom,msm8909-tlmm";
        reg = <0x1000000 0x300000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&tlmm 0 0 117>;
        interrupt-controller;
        #interrupt-cells = <2>;

        gpio-wo-subnode-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-subnodes-state {
            rx-pins {
                pins = "gpio4";
                function = "blsp_uart1";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio5";
                function = "blsp_uart1";
                bias-disable;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8916-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm MSM8916 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm MSM8916 SoC.

properties:
  compatible:
    const: qcom,msm8916-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 61

  gpio-line-names:
    maxItems: 122

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-msm8916-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-msm8916-tlmm-state"
        additionalProperties: false

$defs:
  qcom-msm8916-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[01])$"
            - enum: [ qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
                      qdsd_data3, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
                      sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ gpio, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char,
                atest_char0, atest_char1, atest_char2, atest_char3,
                atest_combodac, atest_gpsadc0, atest_gpsadc1, atest_tsens,
                atest_wlan0, atest_wlan1, backlight_en, bimc_dte0, bimc_dte1,
                blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
                blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2,
                blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2,
                blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,
                blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_uart1,
                blsp_uart2, blsp_uim1, blsp_uim2, cam1_rst, cam1_standby,
                cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0,
                cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out,
                display_5v, dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc,
                euro_us, ext_lpass, flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b,
                gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b,
                gsm0_tx0, gsm0_tx1, gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0,
                kpsns1, kpsns2, ldo_en, ldo_update, mag_int, mdp_vsync,
                modem_tsync, m_voc, nav_pps, nav_tsync, pa_indicator, pbs0,
                pbs1, pbs2, pri_mi2s, pri_mi2s_ws, prng_rosc,
                pwr_crypto_enabled_a, pwr_crypto_enabled_b,
                pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
                pwr_nav_enabled_b, qdss_ctitrig_in_a0, qdss_ctitrig_in_a1,
                qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0,
                qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1,
                qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
                qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, reset_n,
                sd_card, sd_write, sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1,
                uim1, uim2, uim3, uim_batt, wcss_bt, wcss_fm, wcss_wlan,
                webcam1_rst ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    msmgpio: pinctrl@1000000 {
        compatible = "qcom,msm8916-pinctrl";
        reg = <0x01000000 0x300000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        gpio-ranges = <&msmgpio 0 0 122>;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;

        blsp1-uart2-sleep-state {
            pins = "gpio4", "gpio5";
            function = "gpio";

            drive-strength = <2>;
            bias-pull-down;
        };

        spi1-default-state {
            spi-pins {
                pins = "gpio0", "gpio1", "gpio3";
                function = "blsp_spi1";

                drive-strength = <12>;
                bias-disable;
            };

            cs-pins {
                pins = "gpio2";
                function = "gpio";

                drive-strength = <16>;
                bias-disable;
                output-high;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8953-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. MSM8953 TLMM block

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm MSM8953 SoC.

properties:
  compatible:
    const: qcom,msm8953-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  gpio-reserved-ranges: true
  "#gpio-cells": true
  gpio-ranges: true

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-msm8953-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-msm8953-tlmm-state"
        additionalProperties: false

$defs:
  qcom-msm8953-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
                      sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0,
                      qdsd_data1, qdsd_data2, qdsd_data3 ]
        minItems: 1
        maxItems: 16

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1,
                atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
                atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native, atest_tsens,
                atest_wlan0, atest_wlan1, bimc_dte0, bimc_dte1, blsp1_spi,
                blsp3_spi, blsp6_spi, blsp7_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3,
                blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1,
                blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7,
                blsp_spi8, blsp_uart2, blsp_uart4, blsp_uart5, blsp_uart6, cam0_ldo,
                cam1_ldo, cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam3_rst,
                cam3_standby, cam_irq, cam_mclk, cap_int, cci_async, cci_i2c,
                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
                cdc_pdm0, codec_int1, codec_int2, codec_reset, cri_trng, cri_trng0,
                cri_trng1, dac_calib0, dac_calib1, dac_calib10, dac_calib11,
                dac_calib12, dac_calib13, dac_calib14, dac_calib15, dac_calib16,
                dac_calib17, dac_calib18, dac_calib19, dac_calib2, dac_calib20,
                dac_calib21, dac_calib22, dac_calib23, dac_calib24, dac_calib25,
                dac_calib3, dac_calib4, dac_calib5, dac_calib6, dac_calib7,
                dac_calib8, dac_calib9, dbg_out, ddr_bist, dmic0_clk, dmic0_data,
                ebi_cdc, ebi_ch0, ext_lpass, flash_strobe, fp_int, gcc_gp1_clk_a,
                gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
                gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio, gsm0_tx, gsm1_tx,
                gyro_int, hall_int, hdmi_int, key_focus, key_home, key_snapshot,
                key_volp, ldo_en, ldo_update, lpass_slimbus, lpass_slimbus0,
                lpass_slimbus1, m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync,
                mss_lte, nav_pps, nav_pps_in_a, nav_pps_in_b, nav_tsync,
                nfc_disable, nfc_dwl, nfc_irq, ois_sync, pa_indicator, pbs0, pbs1,
                pbs2, pressure_int, pri_mi2s, pri_mi2s_mclk_a, pri_mi2s_mclk_b,
                pri_mi2s_ws, prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b,
                pwr_down, pwr_modem_enabled_a, pwr_modem_enabled_b,
                pwr_nav_enabled_a, pwr_nav_enabled_b, qdss_cti_trig_in_a0,
                qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
                qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
                qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
                qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
                qdss_tracedata_b, sd_write, sdcard_det, sec_mi2s, sec_mi2s_mclk_a,
                sec_mi2s_mclk_b, smb_int, ss_switch, ssbi_wtr1, ts_resout,
                ts_sample, ts_xvdd, tsens_max, uim1_clk, uim1_data, uim1_present,
                uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
                uim_batt, us_emitter, us_euro, wcss_bt, wcss_fm, wcss_wlan,
                wcss_wlan0, wcss_wlan1, wcss_wlan2, wsa_en, wsa_io, wsa_irq ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@1000000 {
        compatible = "qcom,msm8953-pinctrl";
        reg = <0x01000000 0x300000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&tlmm 0 0 142>;

        serial_default: serial-state {
            pins = "gpio4", "gpio5";
            function = "blsp_uart2";
            drive-strength = <2>;
            bias-disable;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8960-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm MSM8960 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm MSM8960 SoC.

properties:
  compatible:
    const: qcom,msm8960-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 76

  gpio-line-names:
    maxItems: 152

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-msm8960-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-msm8960-tlmm-state"
        additionalProperties: false

$defs:
  qcom-msm8960-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-1])$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc3_clk, sdc3_cmd,
                      sdc3_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ gpio, audio_pcm, bt, cam_mclk0, cam_mclk1, cam_mclk2,
                codec_mic_i2s, codec_spkr_i2s, ext_gps, fm, gps_blanking,
                gps_pps_in, gps_pps_out, gp_clk_0a, gp_clk_0b, gp_clk_1a,
                gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gp_pdm_0a, gp_pdm_0b,
                gp_pdm_1a, gp_pdm_1b, gp_pdm_2a, gp_pdm_2b, gsbi1,
                gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n,
                gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n,
                gsbi2_spi_cs3_n, gsbi3, gsbi4, gsbi4_3d_cam_i2c_l,
                gsbi4_3d_cam_i2c_r, gsbi5, gsbi5_3d_cam_i2c_l,
                gsbi5_3d_cam_i2c_r, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11,
                gsbi11_spi_cs1a_n, gsbi11_spi_cs1b_n, gsbi11_spi_cs2a_n,
                gsbi11_spi_cs2b_n, gsbi11_spi_cs3_n, gsbi12, hdmi_cec,
                hdmi_ddc_clock, hdmi_ddc_data, hdmi_hot_plug_detect, hsic,
                mdp_vsync, mi2s, mic_i2s, pmb_clk, pmb_ext_ctrl, ps_hold,
                rpm_wdog, sdc2, sdc4, sdc5, slimbus1, slimbus2, spkr_i2s,
                ssbi1, ssbi2, ssbi_ext_gps, ssbi_pmic2, ssbi_qpa1, ssbi_ts,
                tsif1, tsif2, ts_eoc, usb_fs1, usb_fs1_oe, usb_fs1_oe_n,
                usb_fs2, usb_fs2_oe, usb_fs2_oe_n, vfe_camif_timer1_a,
                vfe_camif_timer1_b, vfe_camif_timer2, vfe_camif_timer3_a,
                vfe_camif_timer3_b, vfe_camif_timer4_a, vfe_camif_timer4_b,
                vfe_camif_timer4_c, vfe_camif_timer5_a, vfe_camif_timer5_b,
                vfe_camif_timer6_a, vfe_camif_timer6_b, vfe_camif_timer6_c,
                vfe_camif_timer7_a, vfe_camif_timer7_b, vfe_camif_timer7_c,
                wlan ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    msmgpio: pinctrl@800000 {
        compatible = "qcom,msm8960-pinctrl";
        reg = <0x800000 0x4000>;
        #gpio-cells = <2>;
        gpio-controller;
        gpio-ranges = <&msmgpio 0 0 152>;
        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;

        spi1-default-state {
            mosi-pins {
                pins = "gpio6";
                function = "gsbi1";
                drive-strength = <12>;
                bias-disable;
            };

            miso-pins {
                pins = "gpio7";
                function = "gsbi1";
                drive-strength = <12>;
                bias-disable;
            };

            cs-pins {
                pins = "gpio8";
                function = "gpio";
                drive-strength = <12>;
                bias-disable;
                output-low;
            };

            clk-pins {
                pins = "gpio9";
                function = "gsbi1";
                drive-strength = <12>;
                bias-disable;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8974-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm MSM8974 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm MSM8974 SoC.

properties:
  compatible:
    const: qcom,msm8974-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 73

  gpio-line-names:
    maxItems: 146

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-msm8974-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-msm8974-tlmm-state"
        additionalProperties: false

$defs:
  qcom-msm8974-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$"
            - enum: [ hsic_data, hsic_strobe, sdc1_clk, sdc1_cmd, sdc1_data,
                      sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ gpio, cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm,
                blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1, blsp_uim2,
                blsp_uart2, blsp_i2c2, blsp_spi2, blsp_uim3, blsp_uart3,
                blsp_i2c3, blsp_spi3, blsp_uim4, blsp_uart4, blsp_i2c4,
                blsp_spi4, blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5,
                blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6, blsp_uim7,
                blsp_uart7, blsp_i2c7, blsp_spi7, blsp_uim8, blsp_uart8,
                blsp_i2c8, blsp_spi8, blsp_uim9, blsp_uart9, blsp_i2c9,
                blsp_spi9, blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10,
                blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11, blsp_uim12,
                blsp_uart12, blsp_i2c12, blsp_spi12, blsp_spi1_cs1,
                blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2
                blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3,
                sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0,
                cci_timer1, cci_timer2, cci_timer3, cci_async_in0,
                cci_async_in1, cci_async_in2, cam_mckl0, cam_mclk1, cam_mclk2,
                cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc, hdmi_hpd, edp_hpd,
                gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk, gp_mn,
                tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s,
                spkr_mi2s, ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    allOf:
      - if:
          properties:
            pins:
              contains:
                enum:
                  - hsic_data
                  - hsic_strobe
          required:
            - pins
        then:
          properties:
            bias-pull-down: false
            bias-pull-up: false
            bias-disable: false
            drive-strength: false
            input-enable: false
            output-high: false
            output-low: false

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@fd510000 {
        compatible = "qcom,msm8974-pinctrl";
        reg = <0xfd510000 0x4000>;
        gpio-controller;
        gpio-ranges = <&tlmm 0 0 146>;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

        sdc1-off-state {
            clk-pins {
                pins = "sdc1_clk";
                bias-disable;
                drive-strength = <2>;
            };

            cmd-pins {
                pins = "sdc1_cmd";
                bias-pull-up;
                drive-strength = <2>;
            };

            data-pins {
                pins = "sdc1_data";
                bias-pull-up;
                drive-strength = <2>;
            };
        };

        blsp2-uart1-sleep-state {
            pins = "gpio41", "gpio42", "gpio43", "gpio44";
            function = "gpio";
            drive-strength = <2>;
            bias-pull-down;
        };

        hsic-state {
            pins = "hsic_data", "hsic_strobe";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8976-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm MSM8976 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm MSM8976 SoC.

properties:
  compatible:
    const: qcom,msm8976-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 73

  gpio-line-names:
    maxItems: 145

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-msm8976-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-msm8976-tlmm-state"
        additionalProperties: false

$defs:
  qcom-msm8976-tlmm-state:
    type: object
    description:
      Desired pin configuration for a device or its specific state (like sleep
      or active).
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this state.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-4])$"
            - enum: [ qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
                      qdsd_data3, sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk,
                      sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ gpio, blsp_uart1, blsp_spi1, smb_int, blsp_i2c1, blsp_spi2,
                blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, blsp_spi3,
                qdss_tracedata_b, blsp_i2c3, gcc_gp2_clk_b, gcc_gp3_clk_b,
                blsp_spi4, cap_int, blsp_i2c4, blsp_spi5, blsp_uart5,
                qdss_traceclk_a, m_voc, blsp_i2c5, qdss_tracectl_a,
                qdss_tracedata_a, blsp_spi6, blsp_uart6, qdss_tracectl_b,
                blsp_i2c6, qdss_traceclk_b, mdp_vsync, pri_mi2s_mclk_a,
                sec_mi2s_mclk_a, cam_mclk, cci0_i2c, cci1_i2c, blsp1_spi,
                blsp3_spi, gcc_gp1_clk_a, gcc_gp2_clk_a, gcc_gp3_clk_a,
                uim_batt, sd_write, uim1_data, uim1_clk, uim1_reset,
                uim1_present, uim2_data, uim2_clk, uim2_reset, uim2_present,
                ts_xvdd, mipi_dsi0, us_euro, ts_resout, ts_sample,
                sec_mi2s_mclk_b, pri_mi2s, codec_reset, cdc_pdm0, us_emitter,
                pri_mi2s_mclk_b, pri_mi2s_mclk_c, lpass_slimbus,
                lpass_slimbus0, lpass_slimbus1, codec_int1, codec_int2,
                wcss_bt, sdc3, wcss_wlan2, wcss_wlan1, wcss_wlan0, wcss_wlan,
                wcss_fm, key_volp, key_snapshot, key_focus, key_home, pwr_down,
                dmic0_clk, hdmi_int, dmic0_data, wsa_vi, wsa_en, blsp_spi8,
                wsa_irq, blsp_i2c8, pa_indicator, modem_tsync, ssbi_wtr1,
                gsm1_tx, gsm0_tx, sdcard_det, sec_mi2s, ss_switch ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@1000000 {
        compatible = "qcom,msm8976-pinctrl";
        reg = <0x1000000 0x300000>;
        #gpio-cells = <2>;
        gpio-controller;
        gpio-ranges = <&tlmm 0 0 145>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;

        blsp1-uart2-active-state {
            pins = "gpio4", "gpio5", "gpio6", "gpio7";
            function = "blsp_uart2";
            drive-strength = <2>;
            bias-disable;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8994-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm MSM8994 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm MSM8994 SoC.

properties:
  compatible:
    enum:
      - qcom,msm8992-pinctrl
      - qcom,msm8994-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 75

  gpio-line-names:
    maxItems: 150

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-msm8994-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-msm8994-tlmm-state"
        additionalProperties: false

$defs:
  qcom-msm8994-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
                      sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ gpio, audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3,
                blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
                blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1,
                blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2,
                blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3,
                blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8,
                blsp_spi9, blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2,
                blsp_spi10_cs3, blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2,
                blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7,
                blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
                blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
                blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
                blsp_uim11, blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b,
                blsp11_uart_rx_b, blsp11_uart_tx_b, cam_mclk0, cam_mclk1,
                cam_mclk2, cam_mclk3, cci_async_in0, cci_async_in1,
                cci_async_in2, cci_i2c0, cci_i2c1, cci_timer0, cci_timer1,
                cci_timer2, cci_timer3, cci_timer4, gcc_gp1_clk_a,
                gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
                gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk,
                gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd,
                hdmi_rcv, mdp_vsync, mss_lte, nav_pps, nav_tsync,
                qdss_cti_trig_in_a, qdss_cti_trig_in_b, qdss_cti_trig_in_c,
                qdss_cti_trig_in_d, qdss_cti_trig_out_a, qdss_cti_trig_out_b,
                qdss_cti_trig_out_c, qdss_cti_trig_out_d, qdss_traceclk_a,
                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
                qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, pci_e1,
                pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1,
                tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4 ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@fd510000 {
        compatible = "qcom,msm8994-pinctrl";
        reg = <0xfd510000 0x4000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        gpio-ranges = <&tlmm 0 0 146>;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;

        blsp1-uart2-default-state {
            function = "blsp_uart2";
            pins = "gpio4", "gpio5";
            drive-strength = <16>;
            bias-disable;
        };

        blsp1-spi1-default-state {
            default-pins {
                pins = "gpio0", "gpio1", "gpio3";
                function = "blsp_spi1";
                drive-strength = <10>;
                bias-pull-down;
            };

            cs-pins {
                pins = "gpio8";
                function = "gpio";
                drive-strength = <2>;
                bias-disable;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8996-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm MSM8996 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm MSM8996 SoC.

properties:
  compatible:
    const: qcom,msm8996-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 75

  gpio-line-names:
    maxItems: 150

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-msm8996-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-msm8996-tlmm-state"
        additionalProperties: false

$defs:
  qcom-msm8996-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
                      sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ gpio, blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
                bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
                qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
                dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
                blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
                mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
                atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio,
                atest_char, cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8,
                qdss_tracedata_b, pll_reset, qdss_stm6, qdss_stm5, qdss_stm4,
                atest_usb2, cci_i2c, qdss_stm3, dac_calib3, atest_usb23,
                atest_char3, dac_calib4, qdss_stm2, atest_usb22, atest_char2,
                qdss_stm1, dac_calib5, atest_usb21, atest_char1, dbg_out,
                qdss_stm0, dac_calib6, atest_usb20, atest_char0, dac_calib10,
                qdss_stm10, qdss_cti_trig_in_a, cci_timer4, blsp_spi6,
                blsp_uart6, blsp_uim6, blsp2_spi, qdss_stm9,
                qdss_cti_trig_out_a, dac_calib11, qdss_stm8, cci_timer0,
                qdss_stm13, dac_calib7, cci_timer1, qdss_stm12, dac_calib8,
                cci_timer2, blsp1_spi, qdss_stm11, dac_calib9, cci_timer3,
                cci_async, dac_calib12, blsp_i2c6, qdss_tracectl_a,
                dac_calib13, qdss_traceclk_a, dac_calib14, dac_calib15,
                hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, dac_calib17,
                hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, dac_calib19,
                hdmi_hot, dac_calib20, dac_calib21, pci_e0, dac_calib22,
                dac_calib23, dac_calib24, tsif1_sync, dac_calib25, sd_write,
                tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, qdss_cti,
                blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, uim3,
                blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
                blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
                qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11,
                blsp_uart11, blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a,
                blsp_i2c11, cri_trng0, cri_trng1, cri_trng, qdss_stm18,
                pri_mi2s, qdss_stm17, blsp_spi4, blsp_uart4, blsp_uim4,
                qdss_stm16, qdss_stm15, blsp_i2c4, qdss_stm14, dac_calib26,
                spkr_i2s, audio_ref, lpass_slimbus, isense_dbg, tsense_pwm1,
                tsense_pwm2, btfm_slimbus, ter_mi2s, qdss_stm22, qdss_stm21,
                qdss_stm20, qdss_stm19, gcc_gp1_clk_b, sec_mi2s, blsp_spi5,
                blsp_uart5, blsp_uim5, gcc_gp2_clk_b, gcc_gp3_clk_b, blsp_i2c5,
                blsp_spi12, blsp_uart12, blsp_uim12, qdss_stm25, qdss_stm31,
                blsp_i2c12, qdss_stm30, qdss_stm29, tsif1_clk, qdss_stm28,
                tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, qdss_traceclk_b,
                tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, sdc4_clk,
                qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
                sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
                ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b,
                blsp11_uart_rx_b, blsp11_i2c_sda_b, prng_rosc,
                blsp11_i2c_scl_b, uim2, uim1, uim_batt, pci_e2, pa_indicator,
                adsp_ext, ddr_bist, qdss_tracedata_11, qdss_tracedata_12,
                modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, qspi_cs, ssbi2,
                ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3 ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@1010000 {
        compatible = "qcom,msm8996-pinctrl";
        reg = <0x01010000 0x300000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        gpio-ranges = <&tlmm 0 0 150>;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;

        blsp1-spi1-default-state {
            spi-pins {
                pins = "gpio0", "gpio1", "gpio3";
                function = "blsp_spi1";
                drive-strength = <12>;
                bias-disable;
            };

            cs-pins {
                pins = "gpio2";
                function = "gpio";
                drive-strength = <16>;
                bias-disable;
                output-high;
            };
        };

        blsp1-spi1-sleep-state {
            pins = "gpio0", "gpio1", "gpio2", "gpio3";
            function = "gpio";
            drive-strength = <2>;
            bias-pull-down;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8998-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm MSM8998 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm MSM8998 SoC.

properties:
  compatible:
    const: qcom,msm8998-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 75

  gpio-line-names:
    maxItems: 150

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-msm8998-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-msm8998-tlmm-state"
        additionalProperties: false

$defs:
  qcom-msm8998-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0,
                atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1,
                atest_usb10, atest_usb11, atest_usb12, atest_usb13, audio_ref,
                bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a, blsp10_spi_b,
                blsp11_i2c, blsp1_spi, blsp1_spi_a, blsp1_spi_b, blsp2_spi,
                blsp9_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,
                blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9,
                blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1, blsp_spi2,
                blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7,
                blsp_spi8, blsp_spi9, blsp_spi10, blsp_spi11, blsp_spi12,
                blsp_uart1_a, blsp_uart1_b, blsp_uart2_a, blsp_uart2_b,
                blsp_uart3_a, blsp_uart3_b, blsp_uart7_a, blsp_uart7_b,
                blsp_uart8, blsp_uart8_a, blsp_uart8_b, blsp_uart9_a,
                blsp_uart9_b, blsp_uim1_a, blsp_uim1_b, blsp_uim2_a,
                blsp_uim2_b, blsp_uim3_a, blsp_uim3_b, blsp_uim7_a,
                blsp_uim7_b, blsp_uim8_a, blsp_uim8_b, blsp_uim9_a,
                blsp_uim9_b, bt_reset, btfm_slimbus, cam_mclk, cci_async,
                cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
                cci_timer4, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
                edp_hot, edp_lcd, gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b,
                gcc_gp3_a, gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv,
                isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus,
                m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
                mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte,
                nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag,
                pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc,
                pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b,
                qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable, qlink_request,
                qua_mi2s, sd_card, sd_write, sdc40, sdc41, sdc42, sdc43,
                sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ssbi1, ssc_irq,
                ter_mi2s, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, tsif0,
                tsif1, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
                uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1,
                vsense_clkout, vsense_data0, vsense_data1, vsense_mode,
                wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1 ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@3400000 {
        compatible = "qcom,msm8998-pinctrl";
        reg = <0x03400000 0xc00000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-ranges = <&tlmm 0 0 150>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-reserved-ranges = <0 4>, <81 4>;

        sdc2-off-state {
            clk-pins {
                pins = "sdc2_clk";
                drive-strength = <2>;
                bias-disable;
            };

            cmd-pins {
                pins = "sdc2_cmd";
                drive-strength = <2>;
                bias-pull-up;
            };

            data-pins {
                pins = "sdc2_data";
                drive-strength = <2>;
                bias-pull-up;
            };
        };

        sdc2-cd-state {
            pins = "gpio95";
            function = "gpio";
            bias-pull-up;
            drive-strength = <2>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,pmic-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm PMIC GPIO block

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  This binding describes the GPIO block(s) found in the 8xxx series of
  PMIC's from Qualcomm.

properties:
  compatible:
    items:
      - enum:
          - qcom,pm2250-gpio
          - qcom,pm660-gpio
          - qcom,pm660l-gpio
          - qcom,pm6125-gpio
          - qcom,pm6150-gpio
          - qcom,pm6150l-gpio
          - qcom,pm6350-gpio
          - qcom,pm7250b-gpio
          - qcom,pm7325-gpio
          - qcom,pm8005-gpio
          - qcom,pm8008-gpio
          - qcom,pm8018-gpio
          - qcom,pm8019-gpio
          - qcom,pm8038-gpio
          - qcom,pm8058-gpio
          - qcom,pm8150-gpio
          - qcom,pm8150b-gpio
          - qcom,pm8150l-gpio
          - qcom,pm8226-gpio
          - qcom,pm8350-gpio
          - qcom,pm8350b-gpio
          - qcom,pm8350c-gpio
          - qcom,pm8450-gpio
          - qcom,pm8916-gpio
          - qcom,pm8917-gpio
          - qcom,pm8921-gpio
          - qcom,pm8941-gpio
          - qcom,pm8950-gpio
          - qcom,pm8994-gpio
          - qcom,pm8998-gpio
          - qcom,pma8084-gpio
          - qcom,pmi8950-gpio
          - qcom,pmi8994-gpio
          - qcom,pmi8998-gpio
          - qcom,pmk8350-gpio
          - qcom,pmm8155au-gpio
          - qcom,pmp8074-gpio
          - qcom,pmr735a-gpio
          - qcom,pmr735b-gpio
          - qcom,pms405-gpio
          - qcom,pmx55-gpio
          - qcom,pmx65-gpio

      - enum:
          - qcom,spmi-gpio
          - qcom,ssbi-gpio

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  gpio-controller: true

  gpio-ranges:
    maxItems: 1

  gpio-line-names:
    minItems: 2
    maxItems: 44

  gpio-reserved-ranges:
    minItems: 1
    # maxItems as half of total number of GPIOs, as there has to be at
    # least one usable GPIO between each reserved range.
    maxItems: 22

  '#gpio-cells':
    const: 2
    description:
      The first cell will be used to define gpio number and the
      second denotes the flags for this gpio

additionalProperties: false

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges
  - interrupt-controller

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm8008-gpio
              - qcom,pmi8950-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 2
          maxItems: 2
        gpio-reserved-ranges:
          maxItems: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm8005-gpio
              - qcom,pm8450-gpio
              - qcom,pm8916-gpio
              - qcom,pmk8350-gpio
              - qcom,pmr735a-gpio
              - qcom,pmr735b-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 4
          maxItems: 4
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 2

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm8018-gpio
              - qcom,pm8019-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 6
          maxItems: 6
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 3

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm8226-gpio
              - qcom,pm8350b-gpio
              - qcom,pm8950-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 8
          maxItems: 8
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 4

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm6350-gpio
              - qcom,pm8350c-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 9
          maxItems: 9
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 5

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm2250-gpio
              - qcom,pm6150-gpio
              - qcom,pm7325-gpio
              - qcom,pm8150-gpio
              - qcom,pm8350-gpio
              - qcom,pmc8180-gpio
              - qcom,pmi8994-gpio
              - qcom,pmm8155au-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 10
          maxItems: 10
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 5

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pmx55-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 11
          maxItems: 11
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 6

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm660l-gpio
              - qcom,pm6150l-gpio
              - qcom,pm7250b-gpio
              - qcom,pm8038-gpio
              - qcom,pm8150b-gpio
              - qcom,pm8150l-gpio
              - qcom,pmc8180c-gpio
              - qcom,pmp8074-gpio
              - qcom,pms405-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 12
          maxItems: 12
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 6

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm660-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 13
          maxItems: 13
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 7

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pmi8998-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 14
          maxItems: 14
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 7

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pmx65-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 16
          maxItems: 16
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 8

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm8994-gpio
              - qcom,pma8084-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 22
          maxItems: 22
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 11

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm8998-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 26
          maxItems: 26
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 13

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm8941-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 36
          maxItems: 36
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 18

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm8917-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 38
          maxItems: 38
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 19

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pm8058-gpio
              - qcom,pm8921-gpio
    then:
      properties:
        gpio-line-names:
          minItems: 44
          maxItems: 44
        gpio-reserved-ranges:
          minItems: 1
          maxItems: 22

patternProperties:
  '-state$':
    oneOf:
      - $ref: "#/$defs/qcom-pmic-gpio-state"
      - patternProperties:
          "(pinconf|-pins)$":
            $ref: "#/$defs/qcom-pmic-gpio-state"
        additionalProperties: false

$defs:
  qcom-pmic-gpio-state:
    type: object
    allOf:
      - $ref: "pinmux-node.yaml"
      - $ref: "pincfg-node.yaml"
    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in
          this subnode.  Valid pins are
                 - gpio1-gpio9 for pm6125
                 - gpio1-gpio10 for pm6150
                 - gpio1-gpio12 for pm6150l
                 - gpio1-gpio9 for pm6350
                 - gpio1-gpio12 for pm7250b
                 - gpio1-gpio10 for pm7325
                 - gpio1-gpio4 for pm8005
                 - gpio1-gpio2 for pm8008
                 - gpio1-gpio6 for pm8018
                 - gpio1-gpio12 for pm8038
                 - gpio1-gpio40 for pm8058
                 - gpio1-gpio10 for pm8150 (holes on gpio2, gpio5,
                                            gpio7 and gpio8)
                 - gpio1-gpio12 for pm8150b (holes on gpio3, gpio4
                                             and gpio7)
                 - gpio1-gpio12 for pm8150l (hole on gpio7)
                 - gpio1-gpio4 for pm8916
                 - gpio1-gpio10 for pm8350
                 - gpio1-gpio8 for pm8350b
                 - gpio1-gpio9 for pm8350c
                 - gpio1-gpio4 for pm8450
                 - gpio1-gpio38 for pm8917
                 - gpio1-gpio44 for pm8921
                 - gpio1-gpio36 for pm8941
                 - gpio1-gpio8 for pm8950 (hole on gpio3)
                 - gpio1-gpio22 for pm8994
                 - gpio1-gpio26 for pm8998
                 - gpio1-gpio22 for pma8084
                 - gpio1-gpio2 for pmi8950
                 - gpio1-gpio10 for pmi8994
                 - gpio1-gpio4 for pmk8350
                 - gpio1-gpio10 for pmm8155au
                 - gpio1-gpio12 for pmp8074 (holes on gpio1 and gpio12)
                 - gpio1-gpio4 for pmr735a
                 - gpio1-gpio4 for pmr735b
                 - gpio1-gpio12 for pms405 (holes on gpio1, gpio9
                                            and gpio10)
                 - gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
                                            and gpio11)
                 - gpio1-gpio16 for pmx65

        items:
          pattern: "^gpio([0-9]+)$"

      function:
        items:
          - enum:
              - normal
              - paired
              - func1
              - func2
              - dtest1
              - dtest2
              - dtest3
              - dtest4
              - func3  # supported by LV/MV GPIO subtypes
              - func4  # supported by LV/MV GPIO subtypes

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true

      qcom,pull-up-strength:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Specifies the strength to use for pull up, if selected.
          Valid values are defined in
          <dt-bindings/pinctrl/qcom,pmic-gpio.h>
          If this property is omitted 30uA strength will be used
          if pull up is selected
        enum: [0, 1, 2, 3]

      bias-high-impedance: true
      input-enable: true
      input-disable: true
      output-high: true
      output-low: true
      output-enable: true
      output-disable: true
      power-source: true

      qcom,drive-strength:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Selects the drive strength for the specified pins
          Valid drive strength values are defined in
          <dt-bindings/pinctrl/qcom,pmic-gpio.h>
        enum: [0, 1, 2, 3]

      drive-push-pull: true
      drive-open-drain: true
      drive-open-source: true

      qcom,analog-pass:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          The specified pins are configured in
          analog-pass-through mode.

      qcom,atest:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Selects ATEST rail to route to GPIO when it's
          configured in analog-pass-through mode.
        enum: [1, 2, 3, 4]

      qcom,dtest-buffer:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Selects DTEST rail to route to GPIO when it's
          configured as digital input.
        enum: [1, 2, 3, 4]

    required:
      - pins
      - function

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>

    pm8921_gpio: gpio@150 {
      compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio";
      reg = <0x150 0x160>;
      interrupt-controller;
      #interrupt-cells = <2>;
      gpio-controller;
      gpio-ranges = <&pm8921_gpio 0 0 44>;
      #gpio-cells = <2>;

      pm8921_gpio_keys: gpio-keys-state {
        volume-keys-pins {
          pins = "gpio20", "gpio21";
          function = "normal";

          input-enable;
          bias-pull-up;
          drive-push-pull;
          qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
          power-source = <PM8921_GPIO_S4>;
        };
      };
    };
...