code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pads-imx8qm.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		serial0 = &lpuart0;
		serial1 = &lpuart1;
		serial2 = &lpuart2;
		serial3 = &lpuart3;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&A53_0>;
				};
				core1 {
					cpu = <&A53_1>;
				};
				core2 {
					cpu = <&A53_2>;
				};
				core3 {
					cpu = <&A53_3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&A72_0>;
				};
				core1 {
					cpu = <&A72_1>;
				};
			};
		};

		A53_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
		};

		A53_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
		};

		A53_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x2>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
		};

		A53_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x3>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
		};

		A72_0: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x100>;
			enable-method = "psci";
			i-cache-size = <0xC000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&A72_L2>;
		};

		A72_1: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&A72_L2>;
		};

		A53_L2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x100000>;
			cache-line-size = <64>;
			cache-sets = <1024>;
		};

		A72_L2: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x100000>;
			cache-line-size = <64>;
			cache-sets = <1024>;
		};
	};

	gic: interrupt-controller@51a00000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
		      <0x0 0x51b00000 0 0xC0000>, /* GICR */
		      <0x0 0x52000000 0 0x2000>,  /* GICC */
		      <0x0 0x52010000 0 0x1000>,  /* GICH */
		      <0x0 0x52020000 0 0x20000>; /* GICV */
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
	};

	system-controller {
		compatible = "fsl,imx-scu";
		mbox-names = "tx0",
			     "rx0",
			     "gip3";
		mboxes = <&lsio_mu1 0 0
			  &lsio_mu1 1 0
			  &lsio_mu1 3 3>;

		pd: power-controller {
			compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
			#power-domain-cells = <1>;
		};

		clk: clock-controller {
			compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
			#clock-cells = <2>;
		};

		iomuxc: pinctrl {
			compatible = "fsl,imx8qm-iomuxc";
		};

		rtc: rtc {
			compatible = "fsl,imx8qxp-sc-rtc";
		};
	};

	/* sorted in register address */
	#include "imx8-ss-img.dtsi"
	#include "imx8-ss-dma.dtsi"
	#include "imx8-ss-conn.dtsi"
	#include "imx8-ss-lsio.dtsi"
};

#include "imx8qm-ss-img.dtsi"
#include "imx8qm-ss-dma.dtsi"
#include "imx8qm-ss-conn.dtsi"
#include "imx8qm-ss-lsio.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018 Einfochips
 * Copyright 2019 Linaro Ltd.
 */

/dts-v1/;

#include "imx8qxp.dtsi"

/ {
	model = "Einfochips i.MX8QXP AI_ML";
	compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";

	aliases {
		serial1 = &lpuart1;
		serial2 = &lpuart2;
		serial3 = &lpuart3;
	};

	chosen {
		stdout-path = &lpuart2;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x80000000>;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_leds>;

		user-led1 {
			label = "green:user1";
			gpios = <&lsio_gpio4 16 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};

		user-led2 {
			label = "green:user2";
			gpios = <&lsio_gpio0 6 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "none";
		};

		user-led3 {
			label = "green:user3";
			gpios = <&lsio_gpio0 7 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "mmc1";
			default-state = "off";
		};

		user-led4 {
			label = "green:user4";
			gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
			panic-indicator;
			linux,default-trigger = "none";
		};

		wlan-active-led {
			label = "yellow:wlan";
			gpios = <&lsio_gpio4 17 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "phy0tx";
			default-state = "off";
		};

		bt-active-led {
			label = "blue:bt";
			gpios = <&lsio_gpio4 18 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "hci0-power";
			default-state = "off";
		};
	};

	sdio_pwrseq: sdio-pwrseq {
		compatible = "mmc-pwrseq-simple";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_wifi_reg_on>;
		reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>;
	};
};

/* BT */
&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	uart-has-rtscts;
	status = "okay";
};

/* LS-UART0 */
&lpuart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart1>;
	status = "okay";
};

/* Debug */
&lpuart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
	status = "okay";
};

/* PCI-E UART */
&lpuart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};
	};
};

/* WiFi */
&usdhc1 {
	#address-cells = <1>;
	#size-cells = <0>;
	assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <4>;
	no-sd;
	non-removable;
	mmc-pwrseq = <&sdio_pwrseq>;
	status = "okay";

	brcmf: wifi@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
	};
};

/* SD */
&usdhc2 {
	assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&iomuxc {
	pinctrl_fec1: fec1grp {
		fsl,pins = <
			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020
			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
			IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
			IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
			IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
			IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
		>;
	};

	pinctrl_leds: ledsgrp{
		fsl,pins = <
			IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06			0x00000021
			IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07			0x00000021
			IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16			0x00000021
			IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21			0x00000021
			IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17			0x00000021
			IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18			0x00000021
		>;
	};

	pinctrl_lpuart0: lpuart0grp {
		fsl,pins = <
			IMX8QXP_UART0_RX_ADMA_UART0_RX				0X06000020
			IMX8QXP_UART0_TX_ADMA_UART0_TX				0X06000020
			IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B			0x06000020
			IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B			0x06000020
		>;
	};

	pinctrl_lpuart1: lpuart1grp {
		fsl,pins = <
			IMX8QXP_UART1_RX_ADMA_UART1_RX				0X06000020
			IMX8QXP_UART1_TX_ADMA_UART1_TX				0X06000020
		>;
	};

	pinctrl_lpuart2: lpuart2grp {
		fsl,pins = <
			IMX8QXP_UART2_RX_ADMA_UART2_RX				0X06000020
			IMX8QXP_UART2_TX_ADMA_UART2_TX				0X06000020
		>;
	};

	pinctrl_lpuart3: lpuart3grp {
		fsl,pins = <
			IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX			0X06000020
			IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX			0X06000020
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021
			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
			IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22			0x00000021
		>;
	};

	pinctrl_wifi_reg_on: wifiregongrp {
		fsl,pins = <
			IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24			0x00000021
		>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2019 Toradex
 */

/dts-v1/;

#include "imx8qxp-colibri.dtsi"
#include "imx8qxp-colibri-eval-v3.dtsi"

/ {
	model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3";
	compatible = "toradex,colibri-imx8x-eval-v3",
		     "toradex,colibri-imx8x", "fsl,imx8qxp";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2019 Toradex
 */

#include <dt-bindings/input/linux-event-codes.h>

/ {
	aliases {
		rtc0 = &rtc_i2c;
		rtc1 = &rtc;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpiokeys>;

		key-wakeup {
			label = "Wake-Up";
			gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_WAKEUP>;
			debounce-interval = <10>;
			wakeup-source;
		};
	};
};

&i2c1 {
	status = "okay";

	/* M41T0M6 real time clock on carrier board */
	rtc_i2c: rtc@68 {
		compatible = "st,m41t0";
		reg = <0x68>;
	};
};

/* Colibri UART_B */
&lpuart0 {
	status = "okay";
};

/* Colibri UART_C */
&lpuart2 {
	status = "okay";
};

/* Colibri UART_A */
&lpuart3 {
	status = "okay";
};

/* Colibri FastEthernet */
&fec1 {
	status = "okay";
};

/* Colibri SD/MMC Card */
&usdhc2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2019 Toradex
 */

#include "imx8qxp.dtsi"

/ {
	model = "Toradex Colibri iMX8QXP/DX Module";
	compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";

	chosen {
		stdout-path = &lpuart3;
	};

	reg_module_3v3: regulator-module-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

/* On-module I2C */
&i2c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
	status = "okay";

	/* Touch controller */
	touchscreen@2c {
		compatible = "adi,ad7879-1";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ad7879_int>;
		reg = <0x2c>;
		interrupt-parent = <&lsio_gpio3>;
		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
		touchscreen-max-pressure = <4096>;
		adi,resistance-plate-x = <120>;
		adi,first-conversion-delay = /bits/ 8 <3>;
		adi,acquisition-time = /bits/ 8 <1>;
		adi,median-filter-size = /bits/ 8 <2>;
		adi,averaging = /bits/ 8 <1>;
		adi,conversion-interval = /bits/ 8 <255>;
	};
};

/* Colibri I2C */
&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
};

/* Colibri UART_B */
&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
};

/* Colibri UART_C */
&lpuart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
};

/* Colibri UART_A */
&lpuart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
};

/* Colibri FastEthernet */
&fec1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_fec1>;
	pinctrl-1 = <&pinctrl_fec1_sleep>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			max-speed = <100>;
			reg = <2>;
		};
	};
};

/* On-module eMMC */
&usdhc1 {
	bus-width = <8>;
	non-removable;
	no-sd;
	no-sdio;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	status = "okay";
};

/* Colibri SD/MMC Card */
&usdhc2 {
	bus-width = <4>;
	cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_module_3v3>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
	disable-wp;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>;

	/* On-module touch pen-down interrupt */
	pinctrl_ad7879_int: ad7879intgrp {
		fsl,pins = <
			IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05	0x21
		>;
	};

	/* Colibri Analogue Inputs */
	pinctrl_adc0: adc0grp {
		fsl,pins = <
			IMX8QXP_ADC_IN0_ADMA_ADC_IN0			0x60		/* SODIMM   8 */
			IMX8QXP_ADC_IN1_ADMA_ADC_IN1			0x60		/* SODIMM   6 */
			IMX8QXP_ADC_IN4_ADMA_ADC_IN4			0x60		/* SODIMM   4 */
			IMX8QXP_ADC_IN5_ADMA_ADC_IN5			0x60		/* SODIMM   2 */
		>;
	};

	pinctrl_can_int: canintgrp {
		fsl,pins = <
			IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13		0x40		/* SODIMM  73 */
		>;
	};

	pinctrl_csi_ctl: csictlgrp {
		fsl,pins = <
			IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14		0x20		/* SODIMM  77 */
			IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15		0x20		/* SODIMM  89 */
		>;
	};

	pinctrl_ext_io0: extio0grp {
		fsl,pins = <
			IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08	0x06000040	/* SODIMM 135 */
		>;
	};

	/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
	pinctrl_fec1: fec1grp {
		fsl,pins = <
			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020
			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x61
			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT		0x06000061
			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x61
			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x61
			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x61
			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x61
			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x61
			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER		0x61
		>;
	};

	pinctrl_fec1_sleep: fec1slpgrp {
		fsl,pins = <
			IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11		0x06000041
			IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10		0x06000041
			IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x41
			IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29		0x41
			IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31	0x41
			IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x41
			IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04	0x41
			IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05	0x41
			IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06	0x41
			IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07	0x41
		>;
	};

	/* Colibri optional CAN on UART_B RTS/CTS */
	pinctrl_flexcan1: flexcan0grp {
		fsl,pins = <
			IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX		0x21		/* SODIMM  32 */
			IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX		0x21		/* SODIMM  34 */
		>;
	};

	/* Colibri optional CAN on PS2 */
	pinctrl_flexcan2: flexcan1grp {
		fsl,pins = <
			IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX		0x21		/* SODIMM  55 */
			IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX		0x21		/* SODIMM  63 */
		>;
	};

	/* Colibri optional CAN on UART_A TXD/RXD */
	pinctrl_flexcan3: flexcan2grp {
		fsl,pins = <
			IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX		0x21		/* SODIMM  35 */
			IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX		0x21		/* SODIMM  33 */
		>;
	};

	/* Colibri LCD Back-Light GPIO */
	pinctrl_gpio_bl_on: gpioblongrp {
		fsl,pins = <
			IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12		0x60		/* SODIMM  71 */
		>;
	};

	pinctrl_gpiokeys: gpiokeysgrp {
		fsl,pins = <
			IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10		0x06700041	/* SODIMM  45 */
		>;
	};

	pinctrl_hog0: hog0grp {
		fsl,pins = <
			IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02	0x06000020	/* SODIMM  65 */
			IMX8QXP_CSI_D07_CI_PI_D09			0x61		/* SODIMM  65 */
			IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11		0x20		/* SODIMM  69 */
			IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26		0x20		/* SODIMM  79 */
			IMX8QXP_CSI_D02_CI_PI_D04			0x61		/* SODIMM  79 */
			IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03		0x06000020	/* SODIMM  85 */
			IMX8QXP_CSI_D06_CI_PI_D08			0x61		/* SODIMM  85 */
			IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17		0x20		/* SODIMM  95 */
			IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27		0x20		/* SODIMM  97 */
			IMX8QXP_CSI_D03_CI_PI_D05			0x61		/* SODIMM  97 */
			IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18		0x20		/* SODIMM  99 */
			IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28		0x20		/* SODIMM 101 */
			IMX8QXP_CSI_D00_CI_PI_D02			0x61		/* SODIMM 101 */
			IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25		0x20		/* SODIMM 103 */
			IMX8QXP_CSI_D01_CI_PI_D03			0x61		/* SODIMM 103 */
			IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x20		/* SODIMM 105 */
			IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x20		/* SODIMM 107 */
			IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05		0x20		/* SODIMM 127 */
			IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06		0x20		/* SODIMM 131 */
			IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04		0x20		/* SODIMM 133 */
			IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00		0x20		/* SODIMM  96 */
			IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21		0x20		/* SODIMM  98 */
			IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31		0x20		/* SODIMM 100 */
			IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22		0x20		/* SODIMM 102 */
			IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20		/* SODIMM 104 */
			IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x20		/* SODIMM 106 */
		>;
	};

	pinctrl_hog1: hog1grp {
		fsl,pins = <
			IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01		0x20		/* SODIMM  75 */
			IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16		0x20		/* SODIMM  93 */
		>;
	};

	/*
	 * This pin is used in the SCFW as a UART. Using it from
	 * Linux would require rewritting the SCFW board file.
	 */
	pinctrl_hog_scfw: hogscfwgrp {
		fsl,pins = <
			IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03		0x20		/* SODIMM 144 */
		>;
	};

	/* On Module I2C */
	pinctrl_i2c0: i2c0grp {
		fsl,pins = <
			IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x06000021
			IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA	0x06000021
		>;
	};

	/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
	pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
		fsl,pins = <
			IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL	0xc6000020	/* SODIMM 140 */
			IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA	0xc6000020	/* SODIMM 142 */
		>;
	};

	/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
	pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
		fsl,pins = <
			IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL	0xc6000020	/* SODIMM 186 */
			IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA	0xc6000020	/* SODIMM 188 */
		>;
	};

	/* Colibri I2C */
	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021	/* SODIMM 196 */
			IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021	/* SODIMM 194 */
		>;
	};

	/* Colibri Parallel RGB LCD Interface */
	pinctrl_lcdif: lcdifgrp {
		fsl,pins = <
			IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK		0x60		/* SODIMM  56 */
			IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC		0x60		/* SODIMM  68 */
			IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC		0x60		/* SODIMM  82 */
			IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN			0x60		/* SODIMM  44 */
			IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19		0x60		/* SODIMM  44 */
			IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00		0x60		/* SODIMM  76 */
			IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21		0x60		/* SODIMM  76 */
			IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01		0x60		/* SODIMM  70 */
			IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02		0x60		/* SODIMM  60 */
			IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03		0x60		/* SODIMM  58 */
			IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04		0x60		/* SODIMM  78 */
			IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05		0x60		/* SODIMM  72 */
			IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06		0x60		/* SODIMM  80 */
			IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07		0x60		/* SODIMM  46 */
			IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08		0x60		/* SODIMM  62 */
			IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09		0x60		/* SODIMM  48 */
			IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10		0x60		/* SODIMM  74 */
			IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11		0x60		/* SODIMM  50 */
			IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12		0x60		/* SODIMM  52 */
			IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13			0x60		/* SODIMM  54 */
			IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14			0x60		/* SODIMM  66 */
			IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15			0x60		/* SODIMM  64 */
			IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16			0x60		/* SODIMM  57 */
			IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x60		/* SODIMM  57 */
			IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17		0x60		/* SODIMM  61 */
		>;
	};

	/* Colibri SPI */
	pinctrl_lpspi2: lpspi2grp {
		fsl,pins = <
			IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00		0x21		/* SODIMM  86 */
			IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO			0x06000040	/* SODIMM  92 */
			IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI			0x06000040	/* SODIMM  90 */
			IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK			0x06000040	/* SODIMM  88 */
		>;
	};

	/* Colibri UART_B */
	pinctrl_lpuart0: lpuart0grp {
		fsl,pins = <
			IMX8QXP_UART0_RX_ADMA_UART0_RX			0x06000020	/* SODIMM  36 */
			IMX8QXP_UART0_TX_ADMA_UART0_TX			0x06000020	/* SODIMM  38 */
			IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B		0x06000020	/* SODIMM  34 */
			IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B		0x06000020	/* SODIMM  32 */
		>;
	};

	/* Colibri UART_C */
	pinctrl_lpuart2: lpuart2grp {
		fsl,pins = <
			IMX8QXP_UART2_RX_ADMA_UART2_RX			0x06000020	/* SODIMM  19 */
			IMX8QXP_UART2_TX_ADMA_UART2_TX			0x06000020	/* SODIMM  21 */
		>;
	};

	/* Colibri UART_A */
	pinctrl_lpuart3: lpuart3grp {
		fsl,pins = <
			IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX		0x06000020	/* SODIMM  33 */
			IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX		0x06000020	/* SODIMM  35 */
		>;
	};

	/* Colibri UART_A Control */
	pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
		fsl,pins = <
			IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00	0x20		/* SODIMM  23 */
			IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29		0x20		/* SODIMM  25 */
			IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30		0x20		/* SODIMM  27 */
			IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03		0x20		/* SODIMM  29 */
			IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22		0x20		/* SODIMM  31 */
			IMX8QXP_CSI_EN_LSIO_GPIO3_IO02			0x20		/* SODIMM  37 */
		>;
	};

	/* On module wifi module */
	pinctrl_pcieb: pciebgrp {
		fsl,pins = <
			IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x04000061	/* SODIMM 178 */
			IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02	0x04000061	/* SODIMM  94 */
			IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00	0x60		/* SODIMM  81 */
		>;
	};

	/* Colibri PWM_A */
	pinctrl_pwm_a: pwmagrp {
	/* both pins are connected together, reserve the unused CSI_D05 */
		fsl,pins = <
			IMX8QXP_CSI_D05_CI_PI_D07			0x61		/* SODIMM  59 */
			IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT		0x60		/* SODIMM  59 */
		>;
	};

	/* Colibri PWM_B */
	pinctrl_pwm_b: pwmbgrp {
		fsl,pins = <
			IMX8QXP_UART1_TX_LSIO_PWM0_OUT			0x60		/* SODIMM  28 */
		>;
	};

	/* Colibri PWM_C */
	pinctrl_pwm_c: pwmcgrp {
		fsl,pins = <
			IMX8QXP_UART1_RX_LSIO_PWM1_OUT			0x60		/* SODIMM  30 */
		>;
	};

	/* Colibri PWM_D */
	pinctrl_pwm_d: pwmdgrp {
	/* both pins are connected together, reserve the unused CSI_D04 */
		fsl,pins = <
			IMX8QXP_CSI_D04_CI_PI_D06			0x61		/* SODIMM  67 */
			IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT		0x60		/* SODIMM  67 */
		>;
	};

	/* On-module I2S */
	pinctrl_sai0: sai0grp {
		fsl,pins = <
			IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD			0x06000040
			IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD			0x06000040
			IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC			0x06000040
			IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS			0x06000040
		>;
	};

	/* Colibri Audio Analogue Microphone GND */
	pinctrl_sgtl5000: sgtl5000grp {
		fsl,pins = <
			/* MIC GND EN */
			IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06	0x41
		>;
	};

	/* On-module SGTL5000 clock */
	pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
		fsl,pins = <
			IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0		0x21
		>;
	};

	/* On-module USB interrupt */
	pinctrl_usb3503a: usb3503agrp {
		fsl,pins = <
			IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04	0x61
		>;
	};

	/* Colibri USB Client Cable Detect */
	pinctrl_usbc_det: usbcdetgrp {
		fsl,pins = <
			IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000040	/* SODIMM 137 */
		>;
	};

	/* USB Host Power Enable */
	pinctrl_usbh1_reg: usbh1reggrp {
		fsl,pins = <
			IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03		0x06000040	/* SODIMM 129 */
		>;
	};

	/* On-module eMMC */
	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21
			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
			IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21
			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
			IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21
			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
			IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21
		>;
	};

	/* Colibri SD/MMC Card Detect */
	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x06000021	/* SODIMM  43 */
		>;
	};

	pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
		fsl,pins = <
			IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x60		/* SODIMM  43 */
		>;
	};

	/* Colibri SD/MMC Card */
	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */
			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */
			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */
			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */
			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */
			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */
			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */
			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */
			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */
			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */
			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */
			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */
			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */
			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */
			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */
			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */
			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */
			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */
			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
		>;
	};

	pinctrl_usdhc2_sleep: usdhc2slpgrp {
		fsl,pins = <
			IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23		0x60		/* SODIMM  47 */
			IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24		0x60		/* SODIMM 190 */
			IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25		0x60		/* SODIMM 192 */
			IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26		0x60		/* SODIMM  49 */
			IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27		0x60		/* SODIMM  51 */
			IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28		0x60		/* SODIMM  53 */
			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
		>;
	};

	pinctrl_wifi: wifigrp {
		fsl,pins = <
			IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x20
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2017~2018 NXP
 */

/dts-v1/;

#include "imx8qxp.dtsi"

/ {
	model = "Freescale i.MX8QXP MEK";
	compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";

	chosen {
		stdout-path = &lpuart0;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	reg_usdhc2_vmmc: usdhc2-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "SD1_SPWR";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&dsp {
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};
	};
};

&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
	status = "okay";

	i2c-switch@71 {
		compatible = "nxp,pca9646", "nxp,pca9546";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x71>;
		reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			max7322: gpio@68 {
				compatible = "maxim,max7322";
				reg = <0x68>;
				gpio-controller;
				#gpio-cells = <2>;
			};
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;

			pressure-sensor@60 {
				compatible = "fsl,mpl3115";
				reg = <0x60>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;

			pca9557_a: gpio@1a {
				compatible = "nxp,pca9557";
				reg = <0x1a>;
				gpio-controller;
				#gpio-cells = <2>;
			};

			pca9557_b: gpio@1d {
				compatible = "nxp,pca9557";
				reg = <0x1d>;
				gpio-controller;
				#gpio-cells = <2>;
			};

			light-sensor@44 {
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_isl29023>;
				compatible = "isil,isl29023";
				reg = <0x44>;
				interrupt-parent = <&lsio_gpio1>;
				interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
			};
		};
	};
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&mu_m0 {
	status = "okay";
};

&mu1_m0 {
	status = "okay";
};

&scu_key {
	status = "okay";
};

&thermal_zones {
	pmic-thermal0 {
		polling-delay-passive = <250>;
		polling-delay = <2000>;
		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;

		trips {
			pmic_alert0: trip0 {
				temperature = <110000>;
				hysteresis = <2000>;
				type = "passive";
			};

			pmic_crit0: trip1 {
				temperature = <125000>;
				hysteresis = <2000>;
				type = "critical";
			};
		};

		cooling-maps {
			map0 {
				trip = <&pmic_alert0>;
				cooling-device =
					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};
	};
};

&usdhc1 {
	assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
};

&usdhc2 {
	assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&vpu {
	compatible = "nxp,imx8qxp-vpu";
	status = "okay";
};

&vpu_core0 {
	reg = <0x2d040000 0x10000>;
	memory-region = <&decoder_boot>, <&decoder_rpc>;
	status = "okay";
};

&vpu_core1 {
	reg = <0x2d050000 0x10000>;
	memory-region = <&encoder_boot>, <&encoder_rpc>;
	status = "okay";
};

&iomuxc {
	pinctrl_fec1: fec1grp {
		fsl,pins = <
			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020
			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
			IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
			IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
			IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
			IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
		>;
	};

	pinctrl_ioexp_rst: ioexprstgrp {
		fsl,pins = <
			IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01			0x06000021
		>;
	};

	pinctrl_isl29023: isl29023grp {
		fsl,pins = <
			IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02			0x00000021
		>;
	};

	pinctrl_lpi2c1: lpi2c1grp {
		fsl,pins = <
			IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL			0x06000021
			IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA			0x06000021
		>;
	};

	pinctrl_lpuart0: lpuart0grp {
		fsl,pins = <
			IMX8QXP_UART0_RX_ADMA_UART0_RX				0x06000020
			IMX8QXP_UART0_TX_ADMA_UART0_TX				0x06000020
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021
			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2020 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

&lpuart0 {
	compatible = "fsl,imx8qxp-lpuart";
};

&lpuart1 {
	compatible = "fsl,imx8qxp-lpuart";
};

&lpuart2 {
	compatible = "fsl,imx8qxp-lpuart";
};

&lpuart3 {
	compatible = "fsl,imx8qxp-lpuart";
};

&i2c0 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};

&i2c1 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};

&i2c2 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};

&i2c3 {
	compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2020 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

&usdhc1 {
	compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};

&usdhc2 {
	compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};

&usdhc3 {
	compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};

&fec1 {
	compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";
};

&fec2 {
	compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2021 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

&jpegdec {
	compatible = "nxp,imx8qxp-jpgdec";
};

&jpegenc {
	compatible = "nxp,imx8qxp-jpgenc";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2020 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

&lsio_gpio0 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 1 56 12>,
		      <&iomuxc 13 69 4>,
		      <&iomuxc 19 75 4>,
		      <&iomuxc 24 80 1>,
		      <&iomuxc 25 82 7>;
};

&lsio_gpio1 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 0 89 9>,
		      <&iomuxc 9 99 16>,
		      <&iomuxc 25 116 7>;
};

&lsio_gpio2 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 0 123 1>,
		      <&iomuxc 1 126 2>,
		      <&iomuxc 3 129 1>;
};

&lsio_gpio3 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 0 146 4>,
		      <&iomuxc 4 151 13>,
		      <&iomuxc 17 165 8>;
};

&lsio_gpio4 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 0 0 3>,
		      <&iomuxc 3 4 4>,
		      <&iomuxc 7 9 6>,
		      <&iomuxc 13 16 6>,
		      <&iomuxc 19 23 2>,
		      <&iomuxc 21 26 2>,
		      <&iomuxc 23 30 6>,
		      <&iomuxc 29 37 3>;
};

&lsio_gpio5 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
	gpio-ranges = <&iomuxc 0 40 3>,
		      <&iomuxc 3 44 6>,
		      <&iomuxc 9 51 3>;
};

&lsio_gpio6 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
};

&lsio_gpio7 {
	compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
};

&lsio_mu0 {
	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};

&lsio_mu1 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};

&lsio_mu2 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};

&lsio_mu3 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};

&lsio_mu4 {
	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};

&lsio_mu5 {
	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};

&lsio_mu6 {
	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};

&lsio_mu13 {
	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017-2020 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec1;
		ethernet1 = &fec2;
		gpio0 = &lsio_gpio0;
		gpio1 = &lsio_gpio1;
		gpio2 = &lsio_gpio2;
		gpio3 = &lsio_gpio3;
		gpio4 = &lsio_gpio4;
		gpio5 = &lsio_gpio5;
		gpio6 = &lsio_gpio6;
		gpio7 = &lsio_gpio7;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		mu0 = &lsio_mu0;
		mu1 = &lsio_mu1;
		mu2 = &lsio_mu2;
		mu3 = &lsio_mu3;
		mu4 = &lsio_mu4;
		serial0 = &lpuart0;
		serial1 = &lpuart1;
		serial2 = &lpuart2;
		serial3 = &lpuart3;
		vpu_core0 = &vpu_core0;
		vpu_core1 = &vpu_core1;
		vpu_core2 = &vpu_core2;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		/* We have 1 clusters with 4 Cortex-A35 cores */
		A35_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A35_L2>;
			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
			operating-points-v2 = <&a35_opp_table>;
			#cooling-cells = <2>;
		};

		A35_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A35_L2>;
			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
			operating-points-v2 = <&a35_opp_table>;
			#cooling-cells = <2>;
		};

		A35_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x2>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A35_L2>;
			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
			operating-points-v2 = <&a35_opp_table>;
			#cooling-cells = <2>;
		};

		A35_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x3>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A35_L2>;
			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
			operating-points-v2 = <&a35_opp_table>;
			#cooling-cells = <2>;
		};

		A35_L2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <1024>;
		};
	};

	a35_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-900000000 {
			opp-hz = /bits/ 64 <900000000>;
			opp-microvolt = <1000000>;
			clock-latency-ns = <150000>;
		};

		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <1100000>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};
	};

	gic: interrupt-controller@51a00000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
		      <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		decoder_boot: decoder-boot@84000000 {
			reg = <0 0x84000000 0 0x2000000>;
			no-map;
		};

		encoder_boot: encoder-boot@86000000 {
			reg = <0 0x86000000 0 0x200000>;
			no-map;
		};

		decoder_rpc: decoder-rpc@92000000 {
			reg = <0 0x92000000 0 0x100000>;
			no-map;
		};

		dsp_reserved: dsp@92400000 {
			reg = <0 0x92400000 0 0x2000000>;
			no-map;
		};

		encoder_rpc: encoder-rpc@94400000 {
			reg = <0 0x94400000 0 0x700000>;
			no-map;
		};
	};

	pmu {
		compatible = "arm,cortex-a35-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	system-controller {
		compatible = "fsl,imx-scu";
		mbox-names = "tx0",
			     "rx0",
			     "gip3";
		mboxes = <&lsio_mu1 0 0
			  &lsio_mu1 1 0
			  &lsio_mu1 3 3>;

		pd: power-controller {
			compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
			#power-domain-cells = <1>;
		};

		clk: clock-controller {
			compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
			#clock-cells = <2>;
		};

		iomuxc: pinctrl {
			compatible = "fsl,imx8qxp-iomuxc";
		};

		ocotp: ocotp {
			compatible = "fsl,imx8qxp-scu-ocotp";
			#address-cells = <1>;
			#size-cells = <1>;
		};

		scu_key: keys {
			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
			linux,keycodes = <KEY_POWER>;
			status = "disabled";
		};

		rtc: rtc {
			compatible = "fsl,imx8qxp-sc-rtc";
		};

		watchdog {
			compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
			timeout-sec = <60>;
		};

		tsens: thermal-sensor {
			compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
			#thermal-sensor-cells = <1>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
	};

	xtal32k: clock-xtal32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "xtal_32KHz";
	};

	xtal24m: clock-xtal24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "xtal_24MHz";
	};

	thermal_zones: thermal-zones {
		cpu0-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;

			trips {
				cpu_alert0: trip0 {
					temperature = <107000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit0: trip1 {
					temperature = <127000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
						<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	/* sorted in register address */
	#include "imx8-ss-img.dtsi"
	#include "imx8-ss-vpu.dtsi"
	#include "imx8-ss-adma.dtsi"
	#include "imx8-ss-conn.dtsi"
	#include "imx8-ss-ddr.dtsi"
	#include "imx8-ss-lsio.dtsi"
};

#include "imx8qxp-ss-img.dtsi"
#include "imx8qxp-ss-adma.dtsi"
#include "imx8qxp-ss-conn.dtsi"
#include "imx8qxp-ss-lsio.dtsi"


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2021 NXP
 */

/dts-v1/;

#include "imx8ulp.dtsi"

/ {
	model = "NXP i.MX8ULP EVK";
	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";

	chosen {
		stdout-path = &lpuart5;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0 0x80000000>;
	};

	clock_ext_rmii: clock-ext-rmii {
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
		clock-output-names = "ext_rmii_clk";
		#clock-cells = <0>;
	};

	clock_ext_ts: clock-ext-ts {
		compatible = "fixed-clock";
		/* External ts clock is 50MHZ from PHY on EVK board. */
		clock-frequency = <50000000>;
		clock-output-names = "ext_ts_clk";
		#clock-cells = <0>;
	};
};

&lpuart5 {
	/* console */
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_lpuart5>;
	pinctrl-1 = <&pinctrl_lpuart5>;
	status = "okay";
};

&usdhc0 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_usdhc0>;
	pinctrl-1 = <&pinctrl_usdhc0>;
	non-removable;
	bus-width = <8>;
	status = "okay";
};

&fec {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_enet>;
	pinctrl-1 = <&pinctrl_enet>;
	clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
		 <&pcc4 IMX8ULP_CLK_ENET>,
		 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
		 <&clock_ext_rmii>;
	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
	assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
	assigned-clock-parents = <&clock_ext_ts>;
	phy-mode = "rmii";
	phy-handle = <&ethphy>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy: ethernet-phy@1 {
			reg = <1>;
			micrel,led-mode = <1>;
		};
	};
};

&iomuxc1 {
	pinctrl_enet: enetgrp {
		fsl,pins = <
			MX8ULP_PAD_PTE15__ENET0_MDC     0x43
			MX8ULP_PAD_PTE14__ENET0_MDIO    0x43
			MX8ULP_PAD_PTE17__ENET0_RXER    0x43
			MX8ULP_PAD_PTE18__ENET0_CRS_DV  0x43
			MX8ULP_PAD_PTF1__ENET0_RXD0     0x43
			MX8ULP_PAD_PTE20__ENET0_RXD1    0x43
			MX8ULP_PAD_PTE16__ENET0_TXEN    0x43
			MX8ULP_PAD_PTE23__ENET0_TXD0    0x43
			MX8ULP_PAD_PTE22__ENET0_TXD1    0x43
			MX8ULP_PAD_PTE19__ENET0_REFCLK  0x43
			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
		>;
	};

	pinctrl_lpuart5: lpuart5grp {
		fsl,pins = <
			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
			MX8ULP_PAD_PTF15__LPUART5_RX	0x3
		>;
	};

	pinctrl_usdhc0: usdhc0grp {
		fsl,pins = <
			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
		>;
	};
};