code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree For AC5.
 *
 * Copyright (C) 2021 Marvell
 * Copyright (C) 2022 Allied Telesis Labs
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell AC5 SoC";
	compatible = "marvell,ac5";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		l2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-ranges;

		internal-regs@7f000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			/* 16M internal register @ 0x7f00_0000 */
			ranges = <0x0 0x0 0x7f000000 0x1000000>;
			dma-coherent;

			uart0: serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&cnm_clock>;
				status = "okay";
			};

			uart1: serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x11000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&cnm_clock>;
				status = "disabled";
			};

			uart2: serial@12200 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12200 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&cnm_clock>;
				status = "disabled";
			};

			uart3: serial@12300 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12300 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&cnm_clock>;
				status = "disabled";
			};

			mdio: mdio@22004 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x22004 0x4>;
				clocks = <&cnm_clock>;
			};

			i2c0: i2c@11000{
				compatible = "marvell,mv78230-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;

				clocks = <&cnm_clock>;
				clock-names = "core";
				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
				clock-frequency=<100000>;

				pinctrl-names = "default", "gpio";
				pinctrl-0 = <&i2c0_pins>;
				pinctrl-1 = <&i2c0_gpio>;
				scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
				sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
				status = "disabled";
			};

			i2c1: i2c@11100{
				compatible = "marvell,mv78230-i2c";
				reg = <0x11100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;

				clocks = <&cnm_clock>;
				clock-names = "core";
				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
				clock-frequency=<100000>;

				pinctrl-names = "default", "gpio";
				pinctrl-0 = <&i2c1_pins>;
				pinctrl-1 = <&i2c1_gpio>;
				scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
				sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
				status = "disabled";
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl0 0 0 32>;
				marvell,pwm-offset = <0x1f0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio1: gpio@18140 {
				reg = <0x18140 0x40>;
				compatible = "marvell,orion-gpio";
				ngpios = <14>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl0 0 32 14>;
				marvell,pwm-offset = <0x1f0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		/*
		 * Dedicated section for devices behind 32bit controllers so we
		 * can configure specific DMA mapping for them
		 */
		behind-32bit-controller@7f000000 {
			compatible = "simple-bus";
			#address-cells = <0x2>;
			#size-cells = <0x2>;
			ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
			/* Host phy ram starts at 0x200M */
			dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
			dma-coherent;

			eth0: ethernet@20000 {
				compatible = "marvell,armada-ac5-neta";
				reg = <0x0 0x20000 0x0 0x4000>;
				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cnm_clock>;
				phy-mode = "sgmii";
				status = "disabled";
			};

			eth1: ethernet@24000 {
				compatible = "marvell,armada-ac5-neta";
				reg = <0x0 0x24000 0x0 0x4000>;
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cnm_clock>;
				phy-mode = "sgmii";
				status = "disabled";
			};

			usb0: usb@80000 {
				compatible = "marvell,orion-ehci";
				reg = <0x0 0x80000 0x0 0x500>;
				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			usb1: usb@a0000 {
				compatible = "marvell,orion-ehci";
				reg = <0x0 0xa0000 0x0 0x500>;
				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};
		};

		pinctrl0: pinctrl@80020100 {
			compatible = "marvell,ac5-pinctrl";
			reg = <0 0x80020100 0 0x20>;

			i2c0_pins: i2c0-pins {
				marvell,pins = "mpp26", "mpp27";
				marvell,function = "i2c0";
			};

			i2c0_gpio: i2c0-gpio-pins {
				marvell,pins = "mpp26", "mpp27";
				marvell,function = "gpio";
			};

			i2c1_pins: i2c1-pins {
				marvell,pins = "mpp20", "mpp21";
				marvell,function = "i2c1";
			};

			i2c1_gpio: i2c1-gpio-pins {
				marvell,pins = "mpp20", "mpp21";
				marvell,function = "i2c1";
			};
		};

		spi0: spi@805a0000 {
			compatible = "marvell,armada-3700-spi";
			reg = <0x0 0x805a0000 0x0 0x50>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clocks = <&spi_clock>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			num-cs = <1>;
			status = "disabled";
		};

		spi1: spi@805a8000 {
			compatible = "marvell,armada-3700-spi";
			reg = <0x0 0x805a8000 0x0 0x50>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clocks = <&spi_clock>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			num-cs = <1>;
			status = "disabled";
		};

		gic: interrupt-controller@80600000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
			      <0x0 0x80660000 0x0 0x40000>; /* GICR */
			interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	clocks {
		cnm_clock: cnm-clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <328000000>;
		};

		spi_clock: spi-clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree For RD-AC5X.
 *
 * Copyright (C) 2021 Marvell
 * Copyright (C) 2022 Allied Telesis Labs
 */
/*
 * Device Tree file for Marvell Alleycat 5X development board
 * This board file supports the B configuration of the board
 */

/dts-v1/;

#include "ac5-98dx35xx.dtsi"

/ {
	model = "Marvell RD-AC5X Board";
	compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";

	aliases {
		serial0 = &uart0;
		spiflash0 = &spiflash0;
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		ethernet0 = &eth0;
		ethernet1 = &eth1;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x2 0x00000000 0x0 0x40000000>;
	};

	usb1phy: usb-phy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};
};

&mdio {
	phy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";
};

&eth0 {
	status = "okay";
	phy-handle = <&phy0>;
};

/* USB0 is a host USB */
&usb0 {
	status = "okay";
};

/* USB1 is a peripheral USB */
&usb1 {
	status = "okay";
	phys = <&usb1phy>;
	phy-names = "usb-phy";
	dr_mode = "peripheral";
};

&spi0 {
	status = "okay";

	spiflash0: flash@0 {
		compatible = "jedec,spi-nor";
		spi-max-frequency = <50000000>;
		spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
		spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
		reg = <0>;

		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "spi_flash_part0";
			reg = <0x0 0x800000>;
		};

		parition@1 {
			label = "spi_flash_part1";
			reg = <0x800000 0x700000>;
		};

		parition@2 {
			label = "spi_flash_part2";
			reg = <0xF00000 0x100000>;
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree For AC5X.
 *
 * Copyright (C) 2022 Allied Telesis Labs
 */

#include "ac5-98dx25xx.dtsi"

/ {
	model = "Marvell AC5X SoC";
	compatible = "marvell,ac5x", "marvell,ac5";
};

&cnm_clock {
	clock-frequency = <325000000>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 371x family of SoCs
 * (also named 88F3710)
 *
 * Copyright (C) 2016 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 *
 */

#include "armada-37xx.dtsi"

/ {
	model = "Marvell Armada 3710 SoC";
	compatible = "marvell,armada3710", "marvell,armada3700";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell Armada 3720 development board
 * (DB-88F3720-DDR3)
 * Copyright (C) 2016 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 *
 * This file is compatible with the version 1.4 and the version 2.0 of
 * the board, however the CON numbers are different between the 2
 * version
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"

/ {
	model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3";
	compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
	};

	exp_usb3_vbus: usb3-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb3-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		regulator-always-on;
		gpio = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
	};

	usb3_phy: usb3-phy {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&exp_usb3_vbus>;
	};

	vcc_sd_reg1: regulator {
		compatible = "regulator-gpio";
		regulator-name = "vcc_sd1";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;

		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
		gpios-states = <0>;
		states = <1800000 0x1
			  3300000 0x0>;
		enable-active-high;
	};

	vcc_sd_reg2: regulator-vmcc {
		compatible = "regulator-fixed";
		regulator-name = "vcc_sd2";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
	};
};

/* Gigabit module on CON19(V2.0)/CON21(V1.4) */
&eth0 {
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	phy-mode = "rgmii-id";
	phy = <&phy0>;
	status = "okay";
};

/* Gigabit module on CON18(V2.0)/CON20(V1.4) */
&eth1 {
	phy-mode = "sgmii";
	phy = <&phy1>;
	status = "okay";
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	status = "okay";

	gpio_exp: pca9555@22 {
		compatible = "nxp,pca9555";
		gpio-controller;
		#gpio-cells = <2>;

		reg = <0x22>;
		/*
		 * IO0_0: PWR_EN_USB2	IO1_0: PWR_EN_VTT
		 * IO0_1: PWR_EN_USB23	IO1_1: MPCIE_WDISABLE
		 * IO0_2: PWR_EN_SATA	IO1_2: RGMII_DEV_RSTN
		 * IO0_3: PWR_EN_PCIE	IO1_3: SGMII_DEV_RSTN
		 * IO0_4: PWR_EN_SD
		 * IO0_5: PWR_EN_EMMC
		 * IO0_6: PWR_EN_RGMII	IO1_6: SATA_USB3.0_SEL
		 * IO0_7: PWR_EN_SGMII	IO1_7: PWR_MCI_PS
		 */
	};

	rtc@68  {
		/* PT7C4337A from pericom fully compatible with the ds1337 */
		compatible = "dallas,ds1337";
		reg = <0x68>;
	};
};

&mdio {
	status = "okay";
	phy0: ethernet-phy@0 {
		reg = <0>;
	};

	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
	status = "okay";
};

/* CON3 */
&sata {
	status = "okay";
};

&sdhci0 {
	non-removable;
	bus-width = <8>;
	mmc-ddr-1_8v;
	mmc-hs400-1_8v;
	marvell,pad-type = "fixed-1-8v";
	status = "okay";
};

/* SD slot module on CON14(V2.0)/CON15(V1.4) */
&sdhci1 {
	wp-inverted;
	cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	marvell,pad-type = "sd";
	vqmmc-supply = <&vcc_sd_reg1>;
	vmmc-supply = <&vcc_sd_reg2>;
	status = "okay";
};

&spi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi_quad_pins>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <108000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			partition@0 {
				label = "bootloader";
				reg = <0x0 0x200000>;
			};
			partition@200000 {
				label = "U-boot Env";
				reg = <0x200000 0x10000>;
			};
			partition@210000 {
				label = "Linux";
				reg = <0x210000 0xDF0000>;
			};
		};
	};
};

/*
 * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through
 * an FTDI (also on CON24(V2.0)/CON26(V1.4)).
 */
&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	status = "okay";
};

/* CON26(V2.0)/CON28(V1.4) */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
	status = "okay";
};

/* CON27(V2.0)/CON29(V1.4) */
&usb2 {
	status = "okay";
};

/* CON29(V2.0)/CON31(V1.4) */
&usb3 {
	status = "okay";
	usb-phy = <&usb3_phy>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/dts-v1/;

#include "armada-3720-uDPU.dtsi"

/ {
	model = "Methode eDPU Board";
	compatible = "methode,edpu", "marvell,armada3720", "marvell,armada3710";
};

&eth0 {
	phy-mode = "2500base-x";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC
 * Copyright (C) 2018 Marvell
 *
 * Romain Perier <romain.perier@free-electrons.com>
 * Konstantin Porotchkin <kostap@marvell.com>
 *
 */
/*
 * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
 */

/dts-v1/;

#include "armada-3720-espressobin.dtsi"

/ {
	model = "Globalscale Marvell ESPRESSOBin Board (eMMC)";
	compatible = "globalscale,espressobin-emmc", "globalscale,espressobin",
		     "marvell,armada3720", "marvell,armada3710";
};

&sdhci0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for ESPRESSObin-Ultra board.
 * Copyright (C) 2019 Globalscale technologies, Inc.
 *
 * Jason Hung <jhung@globalscaletechnologies.com>
 */

/dts-v1/;

#include "armada-3720-espressobin.dtsi"

/ {
	model = "Globalscale Marvell ESPRESSOBin Ultra Board";
	compatible = "globalscale,espressobin-ultra", "globalscale,espressobin",
		     "marvell,armada3720", "marvell,armada3710";

	aliases {
		/* ethernet1 is WAN port */
		ethernet1 = &switch0port5;
		ethernet2 = &switch0port1;
		ethernet3 = &switch0port2;
		ethernet4 = &switch0port3;
		ethernet5 = &switch0port4;
	};

	reg_usb3_vbus: usb3-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb3-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&gpionb 19 GPIO_ACTIVE_HIGH>;
	};

	usb3_phy: usb3-phy {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&reg_usb3_vbus>;
	};

	gpio-leds {
		pinctrl-names = "default";
		compatible = "gpio-leds";
		/* No assigned functions to the LEDs by default */
		led1 {
			label = "ebin-ultra:blue:led1";
			gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
		};
		led2 {
			label = "ebin-ultra:green:led2";
			gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
		};
		led3 {
			label = "ebin-ultra:red:led3";
			gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
		};
		led4 {
			label = "ebin-ultra:yellow:led4";
			gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
		};
	};
};

&sdhci0 {
	status = "okay";
};

&sdhci1 {
	status = "disabled";
};

&spi0 {
	flash@0 {
		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "firmware";
				reg = <0x0 0x3e0000>;
			};
			partition@3e0000 {
				label = "hw-info";
				reg = <0x3e0000 0x10000>;
				read-only;
			};
			partition@3f0000 {
				label = "u-boot-env";
				reg = <0x3f0000 0x10000>;
			};
		};
	};
};

&i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;

	clock-frequency = <100000>;

	rtc@51 {
		compatible = "nxp,pcf8563";
		reg = <0x51>;
	};
};

&usb3 {
	usb-phy = <&usb3_phy>;
};

&mdio {
	extphy: ethernet-phy@1 {
		reg = <1>;

		reset-gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
	};
};

&switch0 {
	reg = <3>;

	reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>;

	ports {
		switch0port1: port@1 {
			reg = <1>;
			label = "lan0";
			phy-handle = <&switch0phy0>;
		};

		switch0port2: port@2 {
			reg = <2>;
			label = "lan1";
			phy-handle = <&switch0phy1>;
		};

		switch0port3: port@3 {
			reg = <3>;
			label = "lan2";
			phy-handle = <&switch0phy2>;
		};

		switch0port4: port@4 {
			reg = <4>;
			label = "lan3";
			phy-handle = <&switch0phy3>;
		};

		switch0port5: port@5 {
			reg = <5>;
			label = "wan";
			phy-handle = <&extphy>;
			phy-mode = "sgmii";
		};
	};

	mdio {
		switch0phy3: switch0phy3@14 {
			reg = <0x14>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 with eMMC
 * Copyright (C) 2018 Marvell
 *
 * Romain Perier <romain.perier@free-electrons.com>
 * Konstantin Porotchkin <kostap@marvell.com>
 *
 */
/*
 * Schematic available at http://espressobin.net/wp-content/uploads/2020/05/ESPRESSObin_V7-0_Schematic.pdf
 */

/dts-v1/;

#include "armada-3720-espressobin.dtsi"

/ {
	model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)";
	compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7",
		     "globalscale,espressobin", "marvell,armada3720",
		     "marvell,armada3710";

	aliases {
		/* ethernet1 is wan port */
		ethernet1 = &switch0port3;
		ethernet3 = &switch0port1;
	};
};

&switch0port1 {
	label = "lan1";
};

&switch0port3 {
	label = "wan";
};

&sdhci0 {
	status = "okay";
};

&led2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7
 * Copyright (C) 2018 Marvell
 *
 * Romain Perier <romain.perier@free-electrons.com>
 * Konstantin Porotchkin <kostap@marvell.com>
 *
 */
/*
 * Schematic available at http://espressobin.net/wp-content/uploads/2020/05/ESPRESSObin_V7-0_Schematic.pdf
 */

/dts-v1/;

#include "armada-3720-espressobin.dtsi"

/ {
	model = "Globalscale Marvell ESPRESSOBin Board V7";
	compatible = "globalscale,espressobin-v7", "globalscale,espressobin",
		     "marvell,armada3720", "marvell,armada3710";

	aliases {
		/* ethernet1 is wan port */
		ethernet1 = &switch0port3;
		ethernet3 = &switch0port1;
	};
};

&switch0port1 {
	label = "lan1";
};

&switch0port3 {
	label = "wan";
};

&led2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Globalscale Marvell ESPRESSOBin Board
 * Copyright (C) 2016 Marvell
 *
 * Romain Perier <romain.perier@free-electrons.com>
 *
 */
/*
 * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
 */

/dts-v1/;

#include "armada-3720-espressobin.dtsi"

/ {
	model = "Globalscale Marvell ESPRESSOBin Board";
	compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Globalscale Marvell ESPRESSOBin Board
 * Copyright (C) 2016 Marvell
 *
 * Romain Perier <romain.perier@free-electrons.com>
 *
 */

#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"

/ {
	aliases {
		ethernet0 = &eth0;
		/* for dsa slave device */
		ethernet1 = &switch0port1;
		ethernet2 = &switch0port2;
		ethernet3 = &switch0port3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
	};

	vcc_sd_reg1: regulator {
		compatible = "regulator-gpio";
		regulator-name = "vcc_sd1";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;

		gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
		gpios-states = <0>;
		states = <1800000 0x1
			  3300000 0x0>;
		enable-active-high;
	};

	led2: gpio-led2 {
		/* led2 is working only on v7 board */
		status = "disabled";

		compatible = "gpio-leds";

		led2 {
			label = "led2";
			gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};
};

/* J9 */
&pcie0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
};

/* J6 */
&sata {
	status = "okay";
};

/* U11 */
&sdhci0 {
	/* Main DTS file for Espressobin is without eMMC */
	status = "disabled";

	non-removable;
	bus-width = <8>;
	mmc-ddr-1_8v;
	mmc-hs400-1_8v;
	marvell,xenon-emmc;
	marvell,xenon-tun-count = <9>;
	marvell,pad-type = "fixed-1-8v";

	pinctrl-names = "default";
	pinctrl-0 = <&mmc_pins>;

	#address-cells = <1>;
	#size-cells = <0>;
	mmccard: mmccard@0 {
		compatible = "mmc-card";
		reg = <0>;
	};
};

/* J1 */
&sdhci1 {
	wp-inverted;
	bus-width = <4>;
	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
	marvell,pad-type = "sd";
	vqmmc-supply = <&vcc_sd_reg1>;

	pinctrl-names = "default";
	pinctrl-0 = <&sdio_pins>;
	status = "okay";
};

&spi0 {
	status = "okay";

	flash@0 {
		reg = <0>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <104000000>;
		m25p,fast-read;
	};
};

/* Exported on the micro USB connector J5 through an FTDI */
&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	status = "okay";
};

/*
 * Connector J17 and J18 expose a number of different features. Some pins are
 * multiplexed. This is the case for instance for the following features:
 * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
 *   how to enable it. Beware that the signals are 1.8V TTL.
 * - I2C
 * - SPI
 * - MMC
 */

/* J7 */
&usb3 {
	status = "okay";
};

/* J8 */
&usb2 {
	status = "okay";
};

&mdio {
	switch0: switch0@1 {
		compatible = "marvell,mv88e6085";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <1>;

		dsa,member = <0 0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			switch0port0: port@0 {
				reg = <0>;
				label = "cpu";
				ethernet = <&eth0>;
				phy-mode = "rgmii-id";
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			switch0port1: port@1 {
				reg = <1>;
				label = "wan";
				phy-handle = <&switch0phy0>;
			};

			switch0port2: port@2 {
				reg = <2>;
				label = "lan0";
				phy-handle = <&switch0phy1>;
			};

			switch0port3: port@3 {
				reg = <3>;
				label = "lan1";
				phy-handle = <&switch0phy2>;
			};

		};

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch0phy0: switch0phy0@11 {
				reg = <0x11>;
			};
			switch0phy1: switch0phy1@12 {
				reg = <0x12>;
			};
			switch0phy2: switch0phy2@13 {
				reg = <0x13>;
			};
		};
	};
};

&eth0 {
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
	phy-mode = "rgmii-id";
	status = "okay";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for CZ.NIC Turris Mox Board
 * 2019 by Marek Behún <kabel@kernel.org>
 */

/dts-v1/;

#include <dt-bindings/bus/moxtet.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-372x.dtsi"

/ {
	model = "CZ.NIC Turris Mox Board";
	compatible = "cznic,turris-mox", "marvell,armada3720",
		     "marvell,armada3710";

	aliases {
		spi0 = &spi0;
		ethernet0 = &eth0;
		ethernet1 = &eth1;
		mmc0 = &sdhci0;
		mmc1 = &sdhci1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
	};

	leds {
		compatible = "gpio-leds";
		led {
			label = "mox:red:activity";
			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "default-on";
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-reset {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
			debounce-interval = <60>;
		};
	};

	exp_usb3_vbus: usb3-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb3-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		regulator-always-on;
		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
	};

	vsdc_reg: vsdc-reg {
		compatible = "regulator-gpio";
		regulator-name = "vsdc";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;

		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
		gpios-states = <0>;
		states = <1800000 0x1
			  3300000 0x0>;
		enable-active-high;
	};

	vsdio_reg: vsdio-reg {
		compatible = "regulator-gpio";
		regulator-name = "vsdio";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;

		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
		gpios-states = <0>;
		states = <1800000 0x1
			  3300000 0x0>;
		enable-active-high;
	};

	sdhci1_pwrseq: sdhci1-pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};

	sfp: sfp {
		compatible = "sff,sfp";
		i2c-bus = <&i2c0>;
		los-gpios = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
		rate-select0-gpios = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
		maximum-power-milliwatt = <3000>;

		/* enabled by U-Boot if SFP module is present */
		status = "disabled";
	};

	firmware {
		armada-3700-rwtm {
			compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
		};
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;
	clock-frequency = <100000>;
	/delete-property/ mrvl,i2c-fast-mode;
	status = "okay";

	/* MCP7940MT-I/MNY RTC */
	rtc@6f {
		compatible = "microchip,mcp7940x";
		reg = <0x6f>;
		interrupt-parent = <&gpiosb>;
		interrupts = <5 0>; /* GPIO2_5 */
	};
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
	status = "okay";
	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
	slot-power-limit-milliwatt = <10000>;
	/*
	 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
	 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
	 * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
	 * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
	 * no remapping) and that this address is the lowest from all specified ranges. If these
	 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
	 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
	 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
	 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
	 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
	 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
	 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
	 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
	 * Bug related to requirement of same child and parent addresses for first range is fixed
	 * in U-Boot version 2022.04 by following commit:
	 * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
	 */
	#address-cells = <3>;
	#size-cells = <2>;
	ranges = <0x81000000 0 0xe8000000   0 0xe8000000   0 0x01000000   /* Port 0 IO */
		  0x82000000 0 0xe9000000   0 0xe9000000   0 0x07000000>; /* Port 0 MEM */

	/* enabled by U-Boot if PCIe module is present */
	status = "disabled";
};

&uart0 {
	status = "okay";
};

&eth0 {
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	phy-mode = "rgmii-id";
	phy-handle = <&phy1>;
	status = "okay";
};

&eth1 {
	phy-mode = "2500base-x";
	managed = "in-band-status";
	phys = <&comphy0 1>;
};

&sdhci0 {
	wp-inverted;
	bus-width = <4>;
	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
	vqmmc-supply = <&vsdc_reg>;
	marvell,pad-type = "sd";
	status = "okay";
};

&sdhci1 {
	pinctrl-names = "default";
	pinctrl-0 = <&sdio_pins>;
	non-removable;
	bus-width = <4>;
	marvell,pad-type = "sd";
	vqmmc-supply = <&vsdio_reg>;
	mmc-pwrseq = <&sdhci1_pwrseq>;
	/* forbid SDR104 for FCC purposes */
	sdhci-caps-mask = <0x2 0x0>;
	status = "okay";
};

&spi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
	assigned-clocks = <&nb_periph_clk 7>;
	assigned-clock-parents = <&tbg 1>;
	assigned-clock-rates = <20000000>;

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <20000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "secure-firmware";
				reg = <0x0 0x20000>;
			};

			partition@20000 {
				label = "a53-firmware";
				reg = <0x20000 0x160000>;
			};

			partition@180000 {
				label = "u-boot-env";
				reg = <0x180000 0x10000>;
			};

			partition@190000 {
				label = "Rescue system";
				reg = <0x190000 0x660000>;
			};

			partition@7f0000 {
				label = "dtb";
				reg = <0x7f0000 0x10000>;
			};
		};
	};

	moxtet: moxtet@1 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "cznic,moxtet";
		reg = <1>;
		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
		spi-max-frequency = <10000000>;
		spi-cpol;
		spi-cpha;
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&gpiosb>;
		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
		status = "okay";

		moxtet_sfp: gpio@0 {
			compatible = "cznic,moxtet-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0>;
			status = "disabled";
		};
	};
};

&usb2 {
	status = "okay";
};

&comphy2 {
	connector {
		compatible = "usb-a-connector";
		phy-supply = <&exp_usb3_vbus>;
	};
};

&usb3 {
	status = "okay";
	phys = <&comphy2 0>;
};

&mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&smi_pins>;
	status = "okay";

	phy1: ethernet-phy@1 {
		reg = <1>;
	};

	/* switch nodes are enabled by U-Boot if modules are present */
	switch0@10 {
		compatible = "marvell,mv88e6190";
		reg = <0x10>;
		dsa,member = <0 0>;
		interrupt-parent = <&moxtet>;
		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
		status = "disabled";

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch0phy1: switch0phy1@1 {
				reg = <0x1>;
			};

			switch0phy2: switch0phy2@2 {
				reg = <0x2>;
			};

			switch0phy3: switch0phy3@3 {
				reg = <0x3>;
			};

			switch0phy4: switch0phy4@4 {
				reg = <0x4>;
			};

			switch0phy5: switch0phy5@5 {
				reg = <0x5>;
			};

			switch0phy6: switch0phy6@6 {
				reg = <0x6>;
			};

			switch0phy7: switch0phy7@7 {
				reg = <0x7>;
			};

			switch0phy8: switch0phy8@8 {
				reg = <0x8>;
			};
		};

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <0x1>;
				label = "lan1";
				phy-handle = <&switch0phy1>;
			};

			port@2 {
				reg = <0x2>;
				label = "lan2";
				phy-handle = <&switch0phy2>;
			};

			port@3 {
				reg = <0x3>;
				label = "lan3";
				phy-handle = <&switch0phy3>;
			};

			port@4 {
				reg = <0x4>;
				label = "lan4";
				phy-handle = <&switch0phy4>;
			};

			port@5 {
				reg = <0x5>;
				label = "lan5";
				phy-handle = <&switch0phy5>;
			};

			port@6 {
				reg = <0x6>;
				label = "lan6";
				phy-handle = <&switch0phy6>;
			};

			port@7 {
				reg = <0x7>;
				label = "lan7";
				phy-handle = <&switch0phy7>;
			};

			port@8 {
				reg = <0x8>;
				label = "lan8";
				phy-handle = <&switch0phy8>;
			};

			port@9 {
				reg = <0x9>;
				label = "cpu";
				ethernet = <&eth1>;
				phy-mode = "2500base-x";
				managed = "in-band-status";
			};

			switch0port10: port@a {
				reg = <0xa>;
				label = "dsa";
				phy-mode = "2500base-x";
				managed = "in-band-status";
				link = <&switch1port9 &switch2port9>;
				status = "disabled";
			};

			port-sfp@a {
				reg = <0xa>;
				label = "sfp";
				sfp = <&sfp>;
				phy-mode = "sgmii";
				managed = "in-band-status";
				status = "disabled";
			};
		};
	};

	switch0@2 {
		compatible = "marvell,mv88e6085";
		reg = <0x2>;
		dsa,member = <0 0>;
		interrupt-parent = <&moxtet>;
		interrupts = <MOXTET_IRQ_TOPAZ>;
		status = "disabled";

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch0phy1_topaz: switch0phy1@11 {
				reg = <0x11>;
			};

			switch0phy2_topaz: switch0phy2@12 {
				reg = <0x12>;
			};

			switch0phy3_topaz: switch0phy3@13 {
				reg = <0x13>;
			};

			switch0phy4_topaz: switch0phy4@14 {
				reg = <0x14>;
			};
		};

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <0x1>;
				label = "lan1";
				phy-handle = <&switch0phy1_topaz>;
			};

			port@2 {
				reg = <0x2>;
				label = "lan2";
				phy-handle = <&switch0phy2_topaz>;
			};

			port@3 {
				reg = <0x3>;
				label = "lan3";
				phy-handle = <&switch0phy3_topaz>;
			};

			port@4 {
				reg = <0x4>;
				label = "lan4";
				phy-handle = <&switch0phy4_topaz>;
			};

			port@5 {
				reg = <0x5>;
				label = "cpu";
				phy-mode = "2500base-x";
				managed = "in-band-status";
				ethernet = <&eth1>;
			};
		};
	};

	switch1@11 {
		compatible = "marvell,mv88e6190";
		reg = <0x11>;
		dsa,member = <0 1>;
		interrupt-parent = <&moxtet>;
		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
		status = "disabled";

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch1phy1: switch1phy1@1 {
				reg = <0x1>;
			};

			switch1phy2: switch1phy2@2 {
				reg = <0x2>;
			};

			switch1phy3: switch1phy3@3 {
				reg = <0x3>;
			};

			switch1phy4: switch1phy4@4 {
				reg = <0x4>;
			};

			switch1phy5: switch1phy5@5 {
				reg = <0x5>;
			};

			switch1phy6: switch1phy6@6 {
				reg = <0x6>;
			};

			switch1phy7: switch1phy7@7 {
				reg = <0x7>;
			};

			switch1phy8: switch1phy8@8 {
				reg = <0x8>;
			};
		};

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <0x1>;
				label = "lan9";
				phy-handle = <&switch1phy1>;
			};

			port@2 {
				reg = <0x2>;
				label = "lan10";
				phy-handle = <&switch1phy2>;
			};

			port@3 {
				reg = <0x3>;
				label = "lan11";
				phy-handle = <&switch1phy3>;
			};

			port@4 {
				reg = <0x4>;
				label = "lan12";
				phy-handle = <&switch1phy4>;
			};

			port@5 {
				reg = <0x5>;
				label = "lan13";
				phy-handle = <&switch1phy5>;
			};

			port@6 {
				reg = <0x6>;
				label = "lan14";
				phy-handle = <&switch1phy6>;
			};

			port@7 {
				reg = <0x7>;
				label = "lan15";
				phy-handle = <&switch1phy7>;
			};

			port@8 {
				reg = <0x8>;
				label = "lan16";
				phy-handle = <&switch1phy8>;
			};

			switch1port9: port@9 {
				reg = <0x9>;
				label = "dsa";
				phy-mode = "2500base-x";
				managed = "in-band-status";
				link = <&switch0port10>;
			};

			switch1port10: port@a {
				reg = <0xa>;
				label = "dsa";
				phy-mode = "2500base-x";
				managed = "in-band-status";
				link = <&switch2port9>;
				status = "disabled";
			};

			port-sfp@a {
				reg = <0xa>;
				label = "sfp";
				sfp = <&sfp>;
				phy-mode = "sgmii";
				managed = "in-band-status";
				status = "disabled";
			};
		};
	};

	switch1@2 {
		compatible = "marvell,mv88e6085";
		reg = <0x2>;
		dsa,member = <0 1>;
		interrupt-parent = <&moxtet>;
		interrupts = <MOXTET_IRQ_TOPAZ>;
		status = "disabled";

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch1phy1_topaz: switch1phy1@11 {
				reg = <0x11>;
			};

			switch1phy2_topaz: switch1phy2@12 {
				reg = <0x12>;
			};

			switch1phy3_topaz: switch1phy3@13 {
				reg = <0x13>;
			};

			switch1phy4_topaz: switch1phy4@14 {
				reg = <0x14>;
			};
		};

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <0x1>;
				label = "lan9";
				phy-handle = <&switch1phy1_topaz>;
			};

			port@2 {
				reg = <0x2>;
				label = "lan10";
				phy-handle = <&switch1phy2_topaz>;
			};

			port@3 {
				reg = <0x3>;
				label = "lan11";
				phy-handle = <&switch1phy3_topaz>;
			};

			port@4 {
				reg = <0x4>;
				label = "lan12";
				phy-handle = <&switch1phy4_topaz>;
			};

			port@5 {
				reg = <0x5>;
				label = "dsa";
				phy-mode = "2500base-x";
				managed = "in-band-status";
				link = <&switch0port10>;
			};
		};
	};

	switch2@12 {
		compatible = "marvell,mv88e6190";
		reg = <0x12>;
		dsa,member = <0 2>;
		interrupt-parent = <&moxtet>;
		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
		status = "disabled";

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch2phy1: switch2phy1@1 {
				reg = <0x1>;
			};

			switch2phy2: switch2phy2@2 {
				reg = <0x2>;
			};

			switch2phy3: switch2phy3@3 {
				reg = <0x3>;
			};

			switch2phy4: switch2phy4@4 {
				reg = <0x4>;
			};

			switch2phy5: switch2phy5@5 {
				reg = <0x5>;
			};

			switch2phy6: switch2phy6@6 {
				reg = <0x6>;
			};

			switch2phy7: switch2phy7@7 {
				reg = <0x7>;
			};

			switch2phy8: switch2phy8@8 {
				reg = <0x8>;
			};
		};

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <0x1>;
				label = "lan17";
				phy-handle = <&switch2phy1>;
			};

			port@2 {
				reg = <0x2>;
				label = "lan18";
				phy-handle = <&switch2phy2>;
			};

			port@3 {
				reg = <0x3>;
				label = "lan19";
				phy-handle = <&switch2phy3>;
			};

			port@4 {
				reg = <0x4>;
				label = "lan20";
				phy-handle = <&switch2phy4>;
			};

			port@5 {
				reg = <0x5>;
				label = "lan21";
				phy-handle = <&switch2phy5>;
			};

			port@6 {
				reg = <0x6>;
				label = "lan22";
				phy-handle = <&switch2phy6>;
			};

			port@7 {
				reg = <0x7>;
				label = "lan23";
				phy-handle = <&switch2phy7>;
			};

			port@8 {
				reg = <0x8>;
				label = "lan24";
				phy-handle = <&switch2phy8>;
			};

			switch2port9: port@9 {
				reg = <0x9>;
				label = "dsa";
				phy-mode = "2500base-x";
				managed = "in-band-status";
				link = <&switch1port10 &switch0port10>;
			};

			port-sfp@a {
				reg = <0xa>;
				label = "sfp";
				sfp = <&sfp>;
				phy-mode = "sgmii";
				managed = "in-band-status";
				status = "disabled";
			};
		};
	};

	switch2@2 {
		compatible = "marvell,mv88e6085";
		reg = <0x2>;
		dsa,member = <0 2>;
		interrupt-parent = <&moxtet>;
		interrupts = <MOXTET_IRQ_TOPAZ>;
		status = "disabled";

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch2phy1_topaz: switch2phy1@11 {
				reg = <0x11>;
			};

			switch2phy2_topaz: switch2phy2@12 {
				reg = <0x12>;
			};

			switch2phy3_topaz: switch2phy3@13 {
				reg = <0x13>;
			};

			switch2phy4_topaz: switch2phy4@14 {
				reg = <0x14>;
			};
		};

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <0x1>;
				label = "lan17";
				phy-handle = <&switch2phy1_topaz>;
			};

			port@2 {
				reg = <0x2>;
				label = "lan18";
				phy-handle = <&switch2phy2_topaz>;
			};

			port@3 {
				reg = <0x3>;
				label = "lan19";
				phy-handle = <&switch2phy3_topaz>;
			};

			port@4 {
				reg = <0x4>;
				label = "lan20";
				phy-handle = <&switch2phy4_topaz>;
			};

			port@5 {
				reg = <0x5>;
				label = "dsa";
				phy-mode = "2500base-x";
				managed = "in-band-status";
				link = <&switch1port10 &switch0port10>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/dts-v1/;

#include "armada-3720-uDPU.dtsi"

/ {
	model = "Methode uDPU Board";
	compatible = "methode,udpu", "marvell,armada3720", "marvell,armada3710";

	sfp_eth0: sfp-eth0 {
		compatible = "sff,sfp";
		i2c-bus = <&i2c0>;
		los-gpios = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
		maximum-power-milliwatt = <3000>;
	};
};

&pinctrl_nb {
	i2c1_recovery_pins: i2c1-recovery-pins {
		groups = "i2c1";
		function = "gpio";
	};
};

&i2c0 {
	status = "okay";
	pinctrl-names = "default", "recovery";
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-1 = <&i2c1_recovery_pins>;
	/delete-property/mrvl,i2c-fast-mode;
	scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};

&eth0 {
	phy-mode = "sgmii";
	sfp = <&sfp_eth0>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device tree for the uDPU board.
 * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
 * Copyright (C) 2016 Marvell
 * Copyright (C) 2019 Methode Electronics
 * Copyright (C) 2019 Telus
 *
 * Vladimir Vid <vladimir.vid@sartura.hr>
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include "armada-372x.dtsi"

/ {
	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
	};

	leds {
		compatible = "gpio-leds";

		led-power1 {
			label = "udpu:green:power";
			gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
		};

		led-power2 {
			label = "udpu:red:power";
			gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
		};

		led-network1 {
			label = "udpu:green:network";
			gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
		};

		led-network2 {
			label = "udpu:red:network";
			gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
		};

		led-alarm1 {
			label = "udpu:green:alarm";
			gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
		};

		led-alarm2 {
			label = "udpu:red:alarm";
			gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
		};
	};

	sfp_eth1: sfp-eth1 {
		compatible = "sff,sfp";
		i2c-bus = <&i2c1>;
		los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
		tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
		tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
		maximum-power-milliwatt = <3000>;
	};
};

&sdhci0 {
	status = "okay";
	bus-width = <8>;
	mmc-ddr-1_8v;
	mmc-hs400-1_8v;
	marvell,pad-type = "fixed-1-8v";
	non-removable;
	no-sd;
	no-sdio;
};

&spi0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi_quad_pins>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <54000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "firmware";
				reg = <0x0 0x180000>;
			};

			partition@180000 {
				label = "u-boot-env";
				reg = <0x180000 0x10000>;
			};
		};
	};
};

&pinctrl_nb {
	i2c2_recovery_pins: i2c2-recovery-pins {
		groups = "i2c2";
		function = "gpio";
	};
};

&i2c1 {
	status = "okay";
	pinctrl-names = "default", "recovery";
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-1 = <&i2c2_recovery_pins>;
	/delete-property/mrvl,i2c-fast-mode;
	scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	temp-sensor@48 {
		compatible = "ti,tmp75c";
		reg = <0x48>;
	};

	temp-sensor@49 {
		compatible = "ti,tmp75c";
		reg = <0x49>;
	};
};

&eth0 {
	status = "okay";
	managed = "in-band-status";
	phys = <&comphy1 0>;
};

&eth1 {
	phy-mode = "sgmii";
	status = "okay";
	managed = "in-band-status";
	phys = <&comphy0 1>;
	sfp = <&sfp_eth1>;
};

&usb3 {
	status = "okay";
	phys = <&usb2_utmi_otg_phy>;
	phy-names = "usb2-utmi-otg-phy";
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 372x family of SoCs
 * (also named 88F3720)
 *
 * Copyright (C) 2016 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 *
 */

#include "armada-37xx.dtsi"

/ {
	model = "Marvell Armada 3720 SoC";
	compatible = "marvell,armada3720", "marvell,armada3710";

	cpus {
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clocks = <&nb_periph_clk 16>;
			enable-method = "psci";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
 *
 * Copyright (C) 2016 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 37xx SoC";
	compatible = "marvell,armada3700";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * The PSCI firmware region depicted below is the default one
		 * and should be updated by the bootloader.
		 */
		psci-area@4000000 {
			reg = <0 0x4000000 0 0x200000>;
			no-map;
		};

		tee@4400000 {
			reg = <0 0x4400000 0 0x1000000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0>;
			clocks = <&nb_periph_clk 16>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		internal-regs@d0000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			/* 32M internal register @ 0xd000_0000 */
			ranges = <0x0 0x0 0xd0000000 0x2000000>;

			wdt: watchdog@8300 {
				compatible = "marvell,armada-3700-wdt";
				reg = <0x8300 0x40>;
				marvell,system-controller = <&cpu_misc>;
				clocks = <&xtalclk>;
			};

			cpu_misc: system-controller@d000 {
				compatible = "marvell,armada-3700-cpu-misc",
					     "syscon";
				reg = <0xd000 0x1000>;
			};

			spi0: spi@10600 {
				compatible = "marvell,armada-3700-spi";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x10600 0xA00>;
				clocks = <&nb_periph_clk 7>;
				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
				num-cs = <4>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,armada-3700-i2c";
				reg = <0x11000 0x24>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&nb_periph_clk 10>;
				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
				mrvl,i2c-fast-mode;
				status = "disabled";
			};

			i2c1: i2c@11080 {
				compatible = "marvell,armada-3700-i2c";
				reg = <0x11080 0x24>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&nb_periph_clk 9>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				mrvl,i2c-fast-mode;
				status = "disabled";
			};

			avs: avs@11500 {
				compatible = "marvell,armada-3700-avs",
					     "syscon";
				reg = <0x11500 0x40>;
			};

			uartclk: clock-controller@12010 {
				compatible = "marvell,armada-3700-uart-clock";
				reg = <0x12010 0x4>, <0x12210 0x4>;
				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
					 <&tbg 3>, <&xtalclk>;
				clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S",
					      "TBG-B-S", "xtal";
				#clock-cells = <1>;
			};

			uart0: serial@12000 {
				compatible = "marvell,armada-3700-uart";
				reg = <0x12000 0x18>;
				clocks = <&uartclk 0>;
				interrupts =
				<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "uart-sum", "uart-tx", "uart-rx";
				status = "disabled";
			};

			uart1: serial@12200 {
				compatible = "marvell,armada-3700-uart-ext";
				reg = <0x12200 0x30>;
				clocks = <&uartclk 1>;
				interrupts =
				<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
				interrupt-names = "uart-tx", "uart-rx";
				status = "disabled";
			};

			nb_periph_clk: nb-periph-clk@13000 {
				compatible = "marvell,armada-3700-periph-clock-nb",
					     "syscon";
				reg = <0x13000 0x100>;
				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
				<&tbg 3>, <&xtalclk>;
				#clock-cells = <1>;
			};

			sb_periph_clk: sb-periph-clk@18000 {
				compatible = "marvell,armada-3700-periph-clock-sb";
				reg = <0x18000 0x100>;
				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
				<&tbg 3>, <&xtalclk>;
				#clock-cells = <1>;
			};

			tbg: tbg@13200 {
				compatible = "marvell,armada-3700-tbg-clock";
				reg = <0x13200 0x100>;
				clocks = <&xtalclk>;
				#clock-cells = <1>;
			};

			pinctrl_nb: pinctrl@13800 {
				compatible = "marvell,armada3710-nb-pinctrl",
					     "syscon", "simple-mfd";
				reg = <0x13800 0x100>, <0x13C00 0x20>;
				/* MPP1[19:0] */
				gpionb: gpio {
					#gpio-cells = <2>;
					gpio-ranges = <&pinctrl_nb 0 0 36>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts =
					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
				};

				xtalclk: xtal-clk {
					compatible = "marvell,armada-3700-xtal-clock";
					clock-output-names = "xtal";
					#clock-cells = <0>;
				};

				spi_quad_pins: spi-quad-pins {
					groups = "spi_quad";
					function = "spi";
				};

				spi_cs1_pins: spi-cs1-pins {
					groups = "spi_cs1";
					function = "spi";
				};

				i2c1_pins: i2c1-pins {
					groups = "i2c1";
					function = "i2c";
				};

				i2c2_pins: i2c2-pins {
					groups = "i2c2";
					function = "i2c";
				};

				uart1_pins: uart1-pins {
					groups = "uart1";
					function = "uart";
				};

				uart2_pins: uart2-pins {
					groups = "uart2";
					function = "uart";
				};

				mmc_pins: mmc-pins {
					groups = "emmc_nb";
					function = "emmc";
				};
			};

			nb_pm: syscon@14000 {
				compatible = "marvell,armada-3700-nb-pm",
					     "syscon";
				reg = <0x14000 0x60>;
			};

			comphy: phy@18300 {
				compatible = "marvell,comphy-a3700";
				reg = <0x18300 0x300>,
				      <0x1F000 0x400>,
				      <0x5C000 0x400>,
				      <0xe0178 0x8>;
				reg-names = "comphy",
					    "lane1_pcie_gbe",
					    "lane0_usb3_gbe",
					    "lane2_sata_usb3";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&xtalclk>;
				clock-names = "xtal";

				comphy0: phy@0 {
					reg = <0>;
					#phy-cells = <1>;
				};

				comphy1: phy@1 {
					reg = <1>;
					#phy-cells = <1>;
				};

				comphy2: phy@2 {
					reg = <2>;
					#phy-cells = <1>;
				};
			};

			pinctrl_sb: pinctrl@18800 {
				compatible = "marvell,armada3710-sb-pinctrl",
					     "syscon", "simple-mfd";
				reg = <0x18800 0x100>, <0x18C00 0x20>;
				/* MPP2[23:0] */
				gpiosb: gpio {
					#gpio-cells = <2>;
					gpio-ranges = <&pinctrl_sb 0 0 30>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts =
					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
				};

				rgmii_pins: mii-pins {
					groups = "rgmii";
					function = "mii";
				};

				smi_pins: smi-pins {
					groups = "smi";
					function = "smi";
				};

				sdio_pins: sdio-pins {
					groups = "sdio_sb";
					function = "sdio";
				};

				pcie_reset_pins: pcie-reset-pins {
					groups = "pcie1"; /* this actually controls "pcie1_reset" */
					function = "gpio";
				};

				pcie_clkreq_pins: pcie-clkreq-pins {
					groups = "pcie1_clkreq";
					function = "pcie";
				};
			};

			eth0: ethernet@30000 {
				   compatible = "marvell,armada-3700-neta";
				   reg = <0x30000 0x4000>;
				   interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
				   clocks = <&sb_periph_clk 8>;
				   status = "disabled";
			};

			mdio: mdio@32004 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x32004 0x4>;
			};

			eth1: ethernet@40000 {
				compatible = "marvell,armada-3700-neta";
				reg = <0x40000 0x4000>;
				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&sb_periph_clk 7>;
				status = "disabled";
			};

			usb3: usb@58000 {
				compatible = "marvell,armada3700-xhci",
				"generic-xhci";
				reg = <0x58000 0x4000>;
				marvell,usb-misc-reg = <&usb32_syscon>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&sb_periph_clk 12>;
				phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
				phy-names = "usb3-phy", "usb2-utmi-otg-phy";
				status = "disabled";
			};

			usb2_utmi_otg_phy: phy@5d000 {
				compatible = "marvell,a3700-utmi-otg-phy";
				reg = <0x5d000 0x800>;
				marvell,usb-misc-reg = <&usb32_syscon>;
				#phy-cells = <0>;
			};

			usb32_syscon: system-controller@5d800 {
				compatible = "marvell,armada-3700-usb2-host-device-misc",
				"syscon";
				reg = <0x5d800 0x800>;
			};

			usb2: usb@5e000 {
				compatible = "marvell,armada-3700-ehci";
				reg = <0x5e000 0x1000>;
				marvell,usb-misc-reg = <&usb2_syscon>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usb2_utmi_host_phy>;
				phy-names = "usb2-utmi-host-phy";
				status = "disabled";
			};

			usb2_utmi_host_phy: phy@5f000 {
				compatible = "marvell,a3700-utmi-host-phy";
				reg = <0x5f000 0x800>;
				marvell,usb-misc-reg = <&usb2_syscon>;
				#phy-cells = <0>;
			};

			usb2_syscon: system-controller@5f800 {
				compatible = "marvell,armada-3700-usb2-host-misc",
				"syscon";
				reg = <0x5f800 0x800>;
			};

			xor@60900 {
				compatible = "marvell,armada-3700-xor";
				reg = <0x60900 0x100>,
				      <0x60b00 0x100>;

				xor10 {
					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				};
				xor11 {
					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			crypto: crypto@90000 {
				compatible = "inside-secure,safexcel-eip97ies";
				reg = <0x90000 0x20000>;
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "mem", "ring0", "ring1",
						  "ring2", "ring3", "eip";
				clocks = <&nb_periph_clk 15>;
			};

			rwtm: mailbox@b0000 {
				compatible = "marvell,armada-3700-rwtm-mailbox";
				reg = <0xb0000 0x100>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				#mbox-cells = <1>;
			};

			sdhci1: mmc@d0000 {
				compatible = "marvell,armada-3700-sdhci",
					     "marvell,sdhci-xenon";
				reg = <0xd0000 0x300>,
				      <0x1e808 0x4>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&nb_periph_clk 0>;
				clock-names = "core";
				status = "disabled";
			};

			sdhci0: mmc@d8000 {
				compatible = "marvell,armada-3700-sdhci",
					     "marvell,sdhci-xenon";
				reg = <0xd8000 0x300>,
				      <0x17808 0x4>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&nb_periph_clk 0>;
				clock-names = "core";
				status = "disabled";
			};

			sata: sata@e0000 {
				compatible = "marvell,armada-3700-ahci";
				reg = <0xe0000 0x178>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&nb_periph_clk 1>;
				phys = <&comphy2 0>;
				phy-names = "sata-phy";
				status = "disabled";
			};

			gic: interrupt-controller@1d00000 {
				compatible = "arm,gic-v3";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0x1d00000 0x10000>, /* GICD */
				      <0x1d40000 0x40000>, /* GICR */
				      <0x1d80000 0x2000>,  /* GICC */
				      <0x1d90000 0x2000>,  /* GICH */
				      <0x1da0000 0x20000>; /* GICV */
				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		pcie0: pcie@d0070000 {
			compatible = "marvell,armada-3700-pcie";
			device_type = "pci";
			status = "disabled";
			reg = <0 0xd0070000 0 0x20000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0x00 0xff>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <1>;
			clocks = <&sb_periph_clk 13>;
			msi-parent = <&pcie0>;
			msi-controller;
			/*
			 * The 128 MiB address range [0xe8000000-0xf0000000] is
			 * dedicated for PCIe and can be assigned to 8 windows
			 * with size a power of two. Use one 64 KiB window for
			 * IO at the end and the remaining seven windows
			 * (totaling 127 MiB) for MEM.
			 */
			ranges = <0x82000000 0 0xe8000000   0 0xe8000000   0 0x07f00000   /* Port 0 MEM */
				  0x81000000 0 0x00000000   0 0xefff0000   0 0x00010000>; /* Port 0 IO */
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc 0>,
					<0 0 0 2 &pcie_intc 1>,
					<0 0 0 3 &pcie_intc 2>,
					<0 0 0 4 &pcie_intc 3>;
			max-link-speed = <2>;
			phys = <&comphy1 0>;
			pcie_intc: interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};
	};

	firmware {
		armada-3700-rwtm {
			compatible = "marvell,armada-3700-rwtm-firmware";
			mboxes = <&rwtm 0>;
			status = "okay";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and
 * one CP110.
 */

#include "armada-ap806-dual.dtsi"
#include "armada-70x0.dtsi"

/ {
	model = "Marvell Armada 7020";
	compatible = "marvell,armada7020", "marvell,armada-ap806-dual",
		     "marvell,armada-ap806";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada 7040 Development board platform
 */

#include <dt-bindings/gpio/gpio.h>
#include "armada-7040.dtsi"

/ {
	model = "Marvell Armada 7040 DB board";
	compatible = "marvell,armada7040-db", "marvell,armada7040",
		     "marvell,armada-ap806-quad", "marvell,armada-ap806";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	aliases {
		ethernet0 = &cp0_eth0;
		ethernet1 = &cp0_eth1;
		ethernet2 = &cp0_eth2;
	};

	cp0_exp_usb3_0_current_regulator: gpio-regulator {
		compatible = "regulator-gpio";
		regulator-name = "cp0-usb3-0-current-regulator";
		regulator-type = "current";
		regulator-min-microamp = <500000>;
		regulator-max-microamp = <900000>;
		gpios = <&expander0 4 GPIO_ACTIVE_HIGH>;
		states = <500000 0x0
			  900000 0x1>;
		enable-active-high;
		gpios-states = <0>;
	};

	cp0_exp_usb3_1_current_regulator: gpio-regulator {
		compatible = "regulator-gpio";
		regulator-name = "cp0-usb3-1-current-regulator";
		regulator-type = "current";
		regulator-min-microamp = <500000>;
		regulator-max-microamp = <900000>;
		gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
		states = <500000 0x0
			  900000 0x1>;
		enable-active-high;
		gpios-states = <0>;
	};

	cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb3h0-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
		vin-supply = <&cp0_exp_usb3_0_current_regulator>;
	};

	cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb3h1-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
		vin-supply = <&cp0_exp_usb3_1_current_regulator>;
	};
};

&i2c0 {
	status = "okay";
	clock-frequency = <100000>;
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0 0x200000>;
			};
			partition@400000 {
				label = "Filesystem";
				reg = <0x200000 0xce0000>;
			};
		};
	};
};

&uart0 {
	status = "okay";
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
};

&cp0_pcie2 {
	status = "okay";
	phys = <&cp0_comphy5 2>;
	phy-names = "cp0-pcie2-x1-phy";
};

&cp0_i2c0 {
	status = "okay";
	clock-frequency = <100000>;

	expander0: pca9555@21 {
		compatible = "nxp,pca9555";
		pinctrl-names = "default";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x21>;
		/*
		 * IO0_0: USB3_PWR_EN0	IO1_0: USB_3_1_Dev_Detect
		 * IO0_1: USB3_PWR_EN1	IO1_1: USB2_1_current_limit
		 * IO0_2: DDR3_4_Detect	IO1_2: Hcon_IO_RstN
		 * IO0_3: USB2_DEVICE_DETECT
		 * IO0_4: GPIO_0	IO1_4: SD_Status
		 * IO0_5: GPIO_1	IO1_5: LDO_5V_Enable
		 * IO0_6: IHB_5V_Enable	IO1_6: PWR_EN_eMMC
		 * IO0_7:		IO1_7: SDIO_Vcntrl
		 */
	};
};

&cp0_nand_controller {
	/*
	 * SPI on CPM and NAND have common pins on this board. We can
	 * use only one at a time. To enable the NAND (which will
	 * disable the SPI), the "status = "okay";" line have to be
	 * added here.
	 */
	pinctrl-0 = <&nand_pins>, <&nand_rb>;
	pinctrl-names = "default";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0 0x200000>;
			};

			partition@200000 {
				label = "Linux";
				reg = <0x200000 0xe00000>;
			};

			partition@1000000 {
				label = "Filesystem";
				reg = <0x1000000 0x3f000000>;
			};

		};
	};
};

&cp0_spi1 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-max-frequency = <20000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0x0 0x200000>;
			};

			partition@400000 {
				label = "Filesystem";
				reg = <0x200000 0xe00000>;
			};
		};
	};
};

&cp0_sata0 {
	status = "okay";

	sata-port@1 {
		phys = <&cp0_comphy3 1>;
		phy-names = "cp0-sata0-1-phy";
	};
};

&cp0_utmi {
	status = "okay";
};

&cp0_comphy1 {
	cp0_usbh0_con: connector {
		compatible = "usb-a-connector";
		phy-supply = <&cp0_reg_usb3_0_vbus>;
	};
};

&cp0_usb3_0 {
	phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
	phy-names = "cp0-usb3h0-comphy", "utmi";
	dr_mode = "host";
	status = "okay";
};

&cp0_comphy4 {
	cp0_usbh1_con: connector {
		compatible = "usb-a-connector";
		phy-supply = <&cp0_reg_usb3_1_vbus>;
	};
};

&cp0_usb3_1 {
	phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
	phy-names = "cp0-usb3h1-comphy", "utmi";
	dr_mode = "host";
	status = "okay";
};

&ap_sdhci0 {
	status = "okay";
	bus-width = <4>;
	no-1-8-v;
	non-removable;
};

&cp0_sdhci0 {
	status = "okay";
	bus-width = <4>;
	no-1-8-v;
	cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
};

&cp0_mdio {
	status = "okay";

	phy0: ethernet-phy@0 {
		reg = <0>;
	};
	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&cp0_ethernet {
	status = "okay";
};

&cp0_eth0 {
	status = "okay";
	/* Network PHY */
	phy-mode = "10gbase-r";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy2 0>;

	fixed-link {
		speed = <10000>;
		full-duplex;
	};
};

&cp0_eth1 {
	status = "okay";
	/* Network PHY */
	phy = <&phy0>;
	phy-mode = "sgmii";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy0 1>;
};

&cp0_eth2 {
	status = "okay";
	phy = <&phy1>;
	phy-mode = "rgmii-id";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Device Tree file for Globalscale MOCHAbin
 * Copyright (C) 2019 Globalscale technologies, Inc.
 * Copyright (C) 2021 Sartura Ltd.
 *
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include "armada-7040.dtsi"

/ {
	model = "Globalscale MOCHAbin";
	compatible = "globalscale,mochabin", "marvell,armada7040",
		     "marvell,armada-ap806-quad", "marvell,armada-ap806";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		ethernet0 = &cp0_eth0;
		ethernet1 = &cp0_eth1;
		ethernet2 = &cp0_eth2;
		ethernet3 = &swport1;
		ethernet4 = &swport2;
		ethernet5 = &swport3;
		ethernet6 = &swport4;
	};

	/* SFP+ 10G */
	sfp_eth0: sfp-eth0 {
		compatible = "sff,sfp";
		i2c-bus = <&cp0_i2c1>;
		los-gpios = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
	};

	/* SFP 1G */
	sfp_eth2: sfp-eth2 {
		compatible = "sff,sfp";
		i2c-bus = <&cp0_i2c0>;
		los-gpios = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
	};
};

/* microUSB UART console */
&uart0 {
	status = "okay";

	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
};

/* eMMC */
&ap_sdhci0 {
	status = "okay";

	bus-width = <4>;
	non-removable;
	/delete-property/ marvell,xenon-phy-slow-mode;
	no-1-8-v;
};

&cp0_pinctrl {
	cp0_uart0_pins: cp0-uart0-pins {
		marvell,pins = "mpp6", "mpp7";
		marvell,function = "uart0";
	};

	cp0_spi0_pins: cp0-spi0-pins {
		marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
		marvell,function = "spi0";
	};

	cp0_spi1_pins: cp0-spi1-pins {
		marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
		marvell,function = "spi1";
	};

	cp0_i2c0_pins: cp0-i2c0-pins {
		marvell,pins = "mpp37", "mpp38";
		marvell,function = "i2c0";
	};

	cp0_i2c1_pins: cp0-i2c1-pins {
		marvell,pins = "mpp2", "mpp3";
		marvell,function = "i2c1";
	};

	pca9554_int_pins: pca9554-int-pins {
		marvell,pins = "mpp27";
		marvell,function = "gpio";
	};

	cp0_rgmii1_pins: cp0-rgmii1-pins {
		marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
			       "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
		marvell,function = "ge1";
	};

	is31_sdb_pins: is31-sdb-pins {
		marvell,pins = "mpp30";
		marvell,function = "gpio";
	};

	cp0_pcie_reset_pins: cp0-pcie-reset-pins {
		marvell,pins = "mpp9";
		marvell,function = "gpio";
	};

	cp0_pcie_clkreq_pins: cp0-pcie-clkreq-pins {
		marvell,pins = "mpp5";
		marvell,function = "pcie1";
	};

	cp0_switch_pins: cp0-switch-pins {
		marvell,pins = "mpp0", "mpp1";
		marvell,function = "gpio";
	};

	cp0_phy_pins: cp0-phy-pins {
		marvell,pins = "mpp12";
		marvell,function = "gpio";
	};
};

/* mikroBUS UART */
&cp0_uart0 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&cp0_uart0_pins>;
};

/* mikroBUS SPI */
&cp0_spi0 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&cp0_spi0_pins>;
};

/* SPI-NOR */
&cp0_spi1{
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&cp0_spi1_pins>;

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <20000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "firmware";
				reg = <0x0 0x3e0000>;
				read-only;
			};

			partition@3e0000 {
				label = "hw-info";
				reg = <0x3e0000 0x10000>;
				read-only;
			};

			partition@3f0000 {
				label = "u-boot-env";
				reg = <0x3f0000 0x10000>;
			};
		};
	};
};

/* mikroBUS, 1G SFP and GPIO expander */
&cp0_i2c0 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c0_pins>;
	clock-frequency = <100000>;

	sfp_gpio: pca9554@39 {
		compatible = "nxp,pca9554";
		pinctrl-names = "default";
		pinctrl-0 = <&pca9554_int_pins>;
		reg = <0x39>;

		interrupt-parent = <&cp0_gpio1>;
		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <2>;

		gpio-controller;
		#gpio-cells = <2>;

		/*
		 * IO0_0: SFP+_TX_FAULT
		 * IO0_1: SFP+_TX_DISABLE
		 * IO0_2: SFP+_PRSNT
		 * IO0_3: SFP+_LOSS
		 * IO0_4: SFP_TX_FAULT
		 * IO0_5: SFP_TX_DISABLE
		 * IO0_6: SFP_PRSNT
		 * IO0_7: SFP_LOSS
		 */
	};
};

/* IS31FL3199, mini-PCIe and 10G SFP+ */
&cp0_i2c1 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c1_pins>;
	clock-frequency = <100000>;

	leds@64 {
		compatible = "issi,is31fl3199";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&is31_sdb_pins>;
		shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
		reg = <0x64>;

		led1_red: led@1 {
			label = "red:led1";
			reg = <1>;
			led-max-microamp = <20000>;
		};

		led1_green: led@2 {
			label = "green:led1";
			reg = <2>;
		};

		led1_blue: led@3 {
			label = "blue:led1";
			reg = <3>;
		};

		led2_red: led@4 {
			label = "red:led2";
			reg = <4>;
		};

		led2_green: led@5 {
			label = "green:led2";
			reg = <5>;
		};

		led2_blue: led@6 {
			label = "blue:led2";
			reg = <6>;
		};

		led3_red: led@7 {
			label = "red:led3";
			reg = <7>;
		};

		led3_green: led@8 {
			label = "green:led3";
			reg = <8>;
		};

		led3_blue: led@9 {
			label = "blue:led3";
			reg = <9>;
		};
	};
};

&cp0_mdio {
	status = "okay";

	/* 88E1512 PHY */
	eth2phy: ethernet-phy@1 {
		reg = <1>;
		sfp = <&sfp_eth2>;

		pinctrl-names = "default";
		pinctrl-0 = <&cp0_phy_pins>;
		reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
	};

	/* 88E6141 Topaz switch */
	switch: switch@3 {
		compatible = "marvell,mv88e6085";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <3>;

		pinctrl-names = "default";
		pinctrl-0 = <&cp0_switch_pins>;
		reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;

		interrupt-parent = <&cp0_gpio1>;
		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			swport1: port@1 {
				reg = <1>;
				label = "lan0";
				phy-handle = <&swphy1>;
			};

			swport2: port@2 {
				reg = <2>;
				label = "lan1";
				phy-handle = <&swphy2>;
			};

			swport3: port@3 {
				reg = <3>;
				label = "lan2";
				phy-handle = <&swphy3>;
			};

			swport4: port@4 {
				reg = <4>;
				label = "lan3";
				phy-handle = <&swphy4>;
			};

			port@5 {
				reg = <5>;
				label = "cpu";
				ethernet = <&cp0_eth1>;
				phy-mode = "2500base-x";
				managed = "in-band-status";
			};
		};

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			swphy1: swphy1@17 {
				reg = <17>;
			};

			swphy2: swphy2@18 {
				reg = <18>;
			};

			swphy3: swphy3@19 {
				reg = <19>;
			};

			swphy4: swphy4@20 {
				reg = <20>;
			};
		};
	};
};

&cp0_ethernet {
	status = "okay";
};

/* 10G SFP+ */
&cp0_eth0 {
	status = "okay";

	phy-mode = "10gbase-r";
	phys = <&cp0_comphy4 0>;
	managed = "in-band-status";
	sfp = <&sfp_eth0>;
};

/* Topaz switch uplink */
&cp0_eth1 {
	status = "okay";

	phy-mode = "2500base-x";
	phys = <&cp0_comphy0 1>;

	fixed-link {
		speed = <2500>;
		full-duplex;
	};
};

/* 1G SFP or 1G RJ45 */
&cp0_eth2 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&cp0_rgmii1_pins>;

	phy = <&eth2phy>;
	phy-mode = "rgmii-id";
};

&cp0_utmi {
	status = "okay";
};

/* SMSC USB5434B hub */
&cp0_usb3_0 {
	status = "okay";

	phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
	phy-names = "cp0-usb3h0-comphy", "utmi";
};

/* miniPCI-E USB */
&cp0_usb3_1 {
	status = "okay";
};

&cp0_sata0 {
	status = "okay";

	/* 7 + 12 SATA connector (J24) */
	sata-port@0 {
		phys = <&cp0_comphy2 0>;
		phy-names = "cp0-sata0-0-phy";
	};

	/* M.2-2250 B-key (J39) */
	sata-port@1 {
		phys = <&cp0_comphy3 1>;
		phy-names = "cp0-sata0-1-phy";
	};
};

/* miniPCI-E (J5) */
&cp0_pcie2 {
	status = "okay";

	pinctrl-names = "default", "clkreq";
	pinctrl-0 = <&cp0_pcie_reset_pins>;
	pinctrl-1 = <&cp0_pcie_clkreq_pins>;
	phys = <&cp0_comphy5 2>;
	phy-names = "cp0-pcie2-x1-phy";
	reset-gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and
 * one CP110.
 */

#include "armada-ap806-quad.dtsi"
#include "armada-70x0.dtsi"

/ {
	model = "Marvell Armada 7040";
	compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
		     "marvell,armada-ap806";
};

&cp0_pcie0 {
	iommu-map =
		<0x0   &smmu 0x480 0x20>,
		<0x100 &smmu 0x4a0 0x20>,
		<0x200 &smmu 0x4c0 0x20>;
	iommu-map-mask = <0x031f>;
};

&cp0_sata0 {
	iommus = <&smmu 0x444>;
};

&cp0_sdhci0 {
	iommus = <&smmu 0x445>;
};

&cp0_usb3_0 {
	iommus = <&smmu 0x440>;
};

&cp0_usb3_1 {
	iommus = <&smmu 0x441>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2017 Marvell Technology Group Ltd.
 *
 * Device Tree file for the Armada 70x0 SoC
 */

/ {
	aliases {
		gpio1 = &cp0_gpio1;
		gpio2 = &cp0_gpio2;
		spi1 = &cp0_spi0;
		spi2 = &cp0_spi1;
	};
};

/*
 * Instantiate the CP110
 */
#define CP11X_NAME		cp0
#define CP11X_BASE		f2000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE	f2600000
#define CP11X_PCIE1_BASE	f2620000
#define CP11X_PCIE2_BASE	f2640000

#include "armada-cp110.dtsi"

#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE

&cp0_gpio1 {
	status = "okay";
};

&cp0_gpio2 {
	status = "okay";
};

&cp0_syscon0 {
	cp0_pinctrl: pinctrl {
		compatible = "marvell,armada-7k-pinctrl";

		nand_pins: nand-pins {
			marvell,pins =
			"mpp15", "mpp16", "mpp17", "mpp18",
			"mpp19", "mpp20", "mpp21", "mpp22",
			"mpp23", "mpp24", "mpp25", "mpp26",
			"mpp27";
			marvell,function = "dev";
		};

		nand_rb: nand-rb {
			marvell,pins = "mpp13";
			marvell,function = "nf";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
 * two CP110.
 */

#include "armada-ap806-dual.dtsi"
#include "armada-80x0.dtsi"

/ {
	model = "Marvell Armada 8020";
	compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
		     "marvell,armada-ap806";
};

/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
 * in CP master is not connected (by package) to the oscillator. So
 * disable it. However, the RTC clock in CP slave is connected to the
 * oscillator so this one is let enabled.
 */

&cp0_rtc {
	status = "disabled";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2018 SolidRun ltd.
 * Based on Marvell MACCHIATOBin board
 *
 * Device Tree file for SolidRun's ClearFog GT 8K
 */

#include "armada-8040.dtsi"

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "SolidRun ClearFog GT 8K";
	compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
			"marvell,armada-ap806-quad", "marvell,armada-ap806";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	aliases {
		ethernet0 = &cp1_eth1;
		ethernet1 = &cp0_eth0;
		ethernet2 = &cp1_eth2;
	};

	fan: pwm {
		compatible = "pwm-fan";
		/* 20% steps */
		cooling-levels = <0 51 102 153 204 255>;
		#cooling-cells = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp0_fan_pwm_pins>;
		pwms = <&cp0_gpio2 16 40000>;
	};

	v_3_3: regulator-3-3v {
		compatible = "regulator-fixed";
		regulator-name = "v_3_3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		status = "okay";
	};

	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
		compatible = "regulator-fixed";
		gpio = <&cp0_gpio2 15 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp0_xhci_vbus_pins>;
		regulator-name = "v_5v0_usb3_hst_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		status = "okay";
	};

	sfp_cp0_eth0: sfp-cp0-eth0 {
		compatible = "sff,sfp";
		i2c-bus = <&cp0_i2c1>;
		mod-def0-gpios = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>;
		maximum-power-milliwatt = <2000>;
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&cp0_led0_pins
			     &cp0_led1_pins>;
		pinctrl-names = "default";
		/* No designated function for these LEDs at the moment */
		led0 {
			label = "clearfog-gt-8k:green:led0";
			gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};
		led1 {
			label = "clearfog-gt-8k:green:led1";
			gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};
	};

	keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>;
		pinctrl-names = "default";

		button-0 {
			/* The rear button */
			label = "Rear Button";
			gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>;
			linux,can-disable;
			linux,code = <BTN_0>;
		};

		button-1 {
			/* The wps button */
			label = "WPS Button";
			gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>;
			linux,can-disable;
			linux,code = <KEY_WPS_BUTTON>;
		};
	};
};

&ap_thermal_ic {
	polling-delay = <1000>; /* milliseconds */
	trips {
		ap_active: trip-active {
			temperature = <40000>; /* millicelsius */
			hysteresis = <4000>; /* millicelsius */
			type = "active";
		};
	};
	cooling-maps {
		map0 {
			trip = <&ap_active>;
			cooling-device = <&fan THERMAL_NO_LIMIT 4>;
		};
		map1 {
			trip = <&ap_crit>;
			cooling-device = <&fan 4 5>;
		};
	};
};

&cp0_thermal_ic {
	polling-delay = <1000>; /* milliseconds */
	trips {
		cp0_active0: trip-active0 {
			temperature = <40000>; /* millicelsius */
			hysteresis = <2500>; /* millicelsius */
			type = "active";
		};
		cp0_active1: trip-active1 {
			temperature = <45000>; /* millicelsius */
			hysteresis = <2500>; /* millicelsius */
			type = "active";
		};
		cp0_active2: trip-active2 {
			temperature = <50000>; /* millicelsius */
			hysteresis = <2500>; /* millicelsius */
			type = "active";
		};
		cp0_active3: trip-active3 {
			temperature = <60000>; /* millicelsius */
			hysteresis = <2500>; /* millicelsius */
			type = "active";
		};
	};
	cooling-maps {
		map0 {
			trip = <&cp0_active0>;
			cooling-device = <&fan 0 1>;
		};
		map1 {
			trip = <&cp0_active1>;
			cooling-device = <&fan 1 2>;
		};
		map2 {
			trip = <&cp0_active2>;
			cooling-device = <&fan 2 3>;
		};
		map3 {
			trip = <&cp0_active3>;
			cooling-device = <&fan 3 4>;
		};
		map4 {
			trip = <&cp0_crit>;
			cooling-device = <&fan 4 5>;
		};
	};
};

&cp1_thermal_ic {
	polling-delay = <1000>; /* milliseconds */
	trips {
		cp1_active0: trip-active0 {
			temperature = <40000>; /* millicelsius */
			hysteresis = <2500>; /* millicelsius */
			type = "active";
		};
		cp1_active1: trip-active1 {
			temperature = <45000>; /* millicelsius */
			hysteresis = <2500>; /* millicelsius */
			type = "active";
		};
		cp1_active2: trip-active2 {
			temperature = <50000>; /* millicelsius */
			hysteresis = <2500>; /* millicelsius */
			type = "active";
		};
		cp1_active3: trip-active3 {
			temperature = <60000>; /* millicelsius */
			hysteresis = <2500>; /* millicelsius */
			type = "active";
		};
	};
	cooling-maps {
		map0 {
			trip = <&cp1_active0>;
			cooling-device = <&fan 0 1>;
		};
		map1 {
			trip = <&cp1_active1>;
			cooling-device = <&fan 1 2>;
		};
		map2 {
			trip = <&cp1_active2>;
			cooling-device = <&fan 2 3>;
		};
		map3 {
			trip = <&cp1_active3>;
			cooling-device = <&fan 3 4>;
		};
		map4 {
			trip = <&cp1_crit>;
			cooling-device = <&fan 4 5>;
		};
	};
};

&uart0 {
	status = "okay";
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
};

&ap_sdhci0 {
	bus-width = <8>;
	no-1-8-v;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
	vqmmc-supply = <&v_3_3>;
};

&cp0_i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c0_pins>;
	status = "okay";
};

&cp0_i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c1_pins>;
	status = "okay";
};

&cp0_pinctrl {
	/*
	 * MPP Bus:
	 * [0-31] = 0xff: Keep default CP0_shared_pins:
	 * [11] CLKOUT_MPP_11 (out)
	 * [23] LINK_RD_IN_CP2CP (in)
	 * [25] CLKOUT_MPP_25 (out)
	 * [29] AVS_FB_IN_CP2CP (in)
	 * [32, 33, 34] pci0/1/2 reset
	 * [35-38] CP0 I2C1 and I2C0
	 * [39] GPIO reset button
	 * [40,41] LED0 and LED1
	 * [43] 1512 phy reset
	 * [47] USB VBUS EN (active low)
	 * [48] FAN PWM
	 * [49] SFP+ present signal
	 * [50] TPM interrupt
	 * [51] WLAN0 disable
	 * [52] WLAN1 disable
	 * [53] LTE disable
	 * [54] NFC reset
	 * [55] Micro SD card detect
	 * [56-61] Micro SD
	 */

	cp0_pci0_reset_pins: pci0-reset-pins {
		marvell,pins = "mpp32";
		marvell,function = "gpio";
	};

	cp0_pci1_reset_pins: pci1-reset-pins {
		marvell,pins = "mpp33";
		marvell,function = "gpio";
	};

	cp0_pci2_reset_pins: pci2-reset-pins {
		marvell,pins = "mpp34";
		marvell,function = "gpio";
	};

	cp0_i2c1_pins: i2c1-pins {
		marvell,pins = "mpp35", "mpp36";
		marvell,function = "i2c1";
	};

	cp0_i2c0_pins: i2c0-pins {
		marvell,pins = "mpp37", "mpp38";
		marvell,function = "i2c0";
	};

	cp0_gpio_reset_pins: gpio-reset-pins {
		marvell,pins = "mpp39";
		marvell,function = "gpio";
	};

	cp0_led0_pins: led0-pins {
		marvell,pins = "mpp40";
		marvell,function = "gpio";
	};

	cp0_led1_pins: led1-pins {
		marvell,pins = "mpp41";
		marvell,function = "gpio";
	};

	cp0_copper_eth_phy_reset: copper-eth-phy-reset {
		marvell,pins = "mpp43";
		marvell,function = "gpio";
	};

	cp0_xhci_vbus_pins: xhci0-vbus-pins {
		marvell,pins = "mpp47";
		marvell,function = "gpio";
	};

	cp0_fan_pwm_pins: fan-pwm-pins {
		marvell,pins = "mpp48";
		marvell,function = "gpio";
	};

	cp0_sfp_present_pins: sfp-present-pins {
		marvell,pins = "mpp49";
		marvell,function = "gpio";
	};

	cp0_tpm_irq_pins: tpm-irq-pins {
		marvell,pins = "mpp50";
		marvell,function = "gpio";
	};

	cp0_wlan_disable_pins: wlan-disable-pins {
		marvell,pins = "mpp51";
		marvell,function = "gpio";
	};

	cp0_sdhci_pins: sdhci-pins {
		marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
			       "mpp60", "mpp61";
		marvell,function = "sdio";
	};
};

&cp0_pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_pci0_reset_pins &cp0_wlan_disable_pins>;
	reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
	phys = <&cp0_comphy0 0>;
	phy-names = "cp0-pcie0-x1-phy";
	status = "okay";
};

&cp0_gpio2 {
	sata_reset {
		gpio-hog;
		gpios = <1 GPIO_ACTIVE_HIGH>;
		output-high;
	};

	lte_reset {
		gpio-hog;
		gpios = <2 GPIO_ACTIVE_LOW>;
		output-low;
	};

	wlan_disable {
		gpio-hog;
		gpios = <19 GPIO_ACTIVE_LOW>;
		output-low;
	};

	lte_disable {
		gpio-hog;
		gpios = <21 GPIO_ACTIVE_LOW>;
		output-low;
	};
};

&cp0_ethernet {
	status = "okay";
};

/* SFP */
&cp0_eth0 {
	status = "okay";
	phy-mode = "10gbase-r";
	managed = "in-band-status";
	phys = <&cp0_comphy2 0>;
	sfp = <&sfp_cp0_eth0>;
};

&cp0_sdhci0 {
	broken-cd;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_sdhci_pins>;
	status = "okay";
	vqmmc-supply = <&v_3_3>;
};

&cp0_usb3_1 {
	status = "okay";
};

&cp1_pinctrl {
	/*
	 * MPP Bus:
	 * [0-5] TDM
	 * [6]   VHV Enable
	 * [7]   CP1 SPI0 CSn1 (FXS)
	 * [8]   CP1 SPI0 CSn0 (TPM)
	 * [9.11]CP1 SPI0 MOSI/MISO/CLK
	 * [13]  CP1 SPI1 MISO (TDM and SPI ROM shared)
	 * [14]  CP1 SPI1 CS0n (64Mb SPI ROM)
	 * [15]  CP1 SPI1 MOSI (TDM and SPI ROM shared)
	 * [16]  CP1 SPI1 CLK (TDM and SPI ROM shared)
	 * [24]  Topaz switch reset
	 * [26]  Buzzer
	 * [27]  CP1 SMI MDIO
	 * [28]  CP1 SMI MDC
	 * [29]  CP0 10G SFP TX Disable
	 * [30]  WPS button
	 * [31]  Front panel button
	 */

	cp1_spi1_pins: spi1-pins {
		marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
		marvell,function = "spi1";
	};

	cp1_switch_reset_pins: switch-reset-pins {
		marvell,pins = "mpp24";
		marvell,function = "gpio";
	};

	cp1_ge_mdio_pins: ge-mdio-pins {
		marvell,pins = "mpp27", "mpp28";
		marvell,function = "ge";
	};

	cp1_sfp_tx_disable_pins: sfp-tx-disable-pins {
		marvell,pins = "mpp29";
		marvell,function = "gpio";
	};

	cp1_wps_button_pins: wps-button-pins {
		marvell,pins = "mpp30";
		marvell,function = "gpio";
	};
};

&cp1_sata0 {
	pinctrl-0 = <&cp0_pci1_reset_pins>;
	status = "okay";

	sata-port@1 {
		phys = <&cp1_comphy0 1>;
		phy-names = "cp1-sata0-1-phy";
	};
};

&cp1_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_ge_mdio_pins>;
	status = "okay";

	ge_phy: ethernet-phy@0 {
		/* LED0 - GB link
		 * LED1 - on: link, blink: activity
		 */
		marvell,reg-init = <3 16 0 0x1017>;
		reg = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp0_copper_eth_phy_reset>;
		reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
		reset-assert-us = <10000>;
		reset-deassert-us = <10000>;
	};

	switch0: switch0@4 {
		compatible = "marvell,mv88e6085";
		reg = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp1_switch_reset_pins>;
		reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <1>;
				label = "lan2";
				phy-handle = <&switch0phy0>;
			};

			port@2 {
				reg = <2>;
				label = "lan1";
				phy-handle = <&switch0phy1>;
			};

			port@3 {
				reg = <3>;
				label = "lan4";
				phy-handle = <&switch0phy2>;
			};

			port@4 {
				reg = <4>;
				label = "lan3";
				phy-handle = <&switch0phy3>;
			};

			port@5 {
				reg = <5>;
				label = "cpu";
				ethernet = <&cp1_eth2>;
				phy-mode = "2500base-x";
				managed = "in-band-status";
			};
		};

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch0phy0: switch0phy0@11 {
				reg = <0x11>;
			};

			switch0phy1: switch0phy1@12 {
				reg = <0x12>;
			};

			switch0phy2: switch0phy2@13 {
				reg = <0x13>;
			};

			switch0phy3: switch0phy3@14 {
				reg = <0x14>;
			};
		};
	};
};

&cp1_ethernet {
	status = "okay";
};

/* 1G copper */
&cp1_eth1 {
	status = "okay";
	phy-mode = "sgmii";
	phy = <&ge_phy>;
	phys = <&cp1_comphy3 1>;
};

/* Switch uplink */
&cp1_eth2 {
	status = "okay";
	phy-mode = "2500base-x";
	phys = <&cp1_comphy5 2>;
	managed = "in-band-status";
};

&cp1_spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_spi1_pins>;
	status = "okay";

	flash@0 {
		compatible = "st,w25q32";
		spi-max-frequency = <50000000>;
		reg = <0>;
	};
};

&cp1_comphy2 {
	cp1_usbh0_con: connector {
		compatible = "usb-a-connector";
		phy-supply = <&v_5v0_usb3_hst_vbus>;
	};
};

&cp1_usb3_0 {
	phys = <&cp1_comphy2 0>;
	phy-names = "cp1-usb3h0-comphy";
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada 8040 Development board platform
 */

#include <dt-bindings/gpio/gpio.h>
#include "armada-8040.dtsi"

/ {
	model = "Marvell Armada 8040 DB board";
	compatible = "marvell,armada8040-db", "marvell,armada8040",
		     "marvell,armada-ap806-quad", "marvell,armada-ap806";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	aliases {
		ethernet0 = &cp0_eth0;
		ethernet1 = &cp0_eth2;
		ethernet2 = &cp1_eth0;
		ethernet3 = &cp1_eth1;
		i2c1 = &cp0_i2c0;
		i2c2 = &cp1_i2c0;
	};

	cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
		compatible = "regulator-fixed";
		regulator-name = "cp0-usb3h0-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
	};

	cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "cp0-usb3h1-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
	};

	cp0_usb3_0_phy: cp0-usb3-0-phy {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&cp0_reg_usb3_0_vbus>;
	};

	cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
		compatible = "regulator-fixed";
		regulator-name = "cp1-usb3h0-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
	};

	cp1_usb3_0_phy: cp1-usb3-0-phy {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&cp1_reg_usb3_0_vbus>;
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0 0x200000>;
			};
			partition@400000 {
				label = "Filesystem";
				reg = <0x200000 0xce0000>;
			};
		};
	};
};

/* Accessible over the mini-USB CON9 connector on the main board */
&uart0 {
	status = "okay";
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
};

/* CON6 on CP0 expansion */
&cp0_pcie0 {
	phys = <&cp0_comphy0 0>;
	phy-names = "cp0-pcie0-x1-phy";
	status = "okay";
};

/* CON5 on CP0 expansion */
&cp0_pcie2 {
	phys = <&cp0_comphy5 2>;
	phy-names = "cp0-pcie2-x1-phy";
	status = "okay";
};

&cp0_i2c0 {
	status = "okay";
	clock-frequency = <100000>;

	/* U31 */
	expander0: pca9555@21 {
		compatible = "nxp,pca9555";
		pinctrl-names = "default";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x21>;
	};

	/* U25 */
	expander1: pca9555@25 {
		compatible = "nxp,pca9555";
		pinctrl-names = "default";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x25>;
	};

};

/* CON4 on CP0 expansion */
&cp0_sata0 {
	status = "okay";

	sata-port@0 {
		phys = <&cp0_comphy1 0>;
		phy-names = "cp0-sata0-0-phy";
	};
	sata-port@1 {
		phys = <&cp0_comphy3 1>;
		phy-names = "cp0-sata0-1-phy";
	};
};

/* CON9 on CP0 expansion */
&cp0_utmi {
	status = "okay";
};

&cp0_usb3_0 {
	usb-phy = <&cp0_usb3_0_phy>;
	phys = <&cp0_utmi0>;
	phy-names = "utmi";
	dr_mode = "host";
	status = "okay";
};

&cp0_comphy4 {
	cp0_usbh1_con: connector {
		compatible = "usb-a-connector";
		phy-supply = <&cp0_reg_usb3_1_vbus>;
	};
};

/* CON10 on CP0 expansion */
&cp0_usb3_1 {
	phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
	phy-names = "usb", "utmi";
	dr_mode = "host";
	status = "okay";
};

&cp0_mdio {
	status = "okay";

	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&cp0_ethernet {
	status = "okay";
};

&cp0_eth0 {
	status = "okay";
	phy-mode = "10gbase-r";

	fixed-link {
		speed = <10000>;
		full-duplex;
	};
};

&cp0_eth2 {
	status = "okay";
	phy = <&phy1>;
	phy-mode = "rgmii-id";
};

/* CON6 on CP1 expansion */
&cp1_pcie0 {
	phys = <&cp1_comphy0 0>;
	phy-names = "cp1-pcie0-x1-phy";
	status = "okay";
};

/* CON7 on CP1 expansion */
&cp1_pcie1 {
	phys = <&cp1_comphy4 1>;
	phy-names = "cp1-pcie1-x1-phy";
	status = "okay";
};

/* CON5 on CP1 expansion */
&cp1_pcie2 {
	phys = <&cp1_comphy5 2>;
	phy-names = "cp1-pcie2-x1-phy";
	status = "okay";
};

&cp1_i2c0 {
	status = "okay";
	clock-frequency = <100000>;
};

&cp1_spi1 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-max-frequency = <20000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "Boot";
				reg = <0x0 0x200000>;
			};
			partition@200000 {
				label = "Filesystem";
				reg = <0x200000 0xd00000>;
			};
			partition@f00000 {
				label = "Boot_2nd";
				reg = <0xf00000 0x100000>;
			};
		};
	};
};

/*
 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
 * MDIO signal of CP1.
 */
&cp1_nand_controller {
	pinctrl-0 = <&nand_pins>, <&nand_rb>;
	pinctrl-names = "default";

	nand@0 {
		reg = <0>;
		nand-rb = <0>;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0 0x200000>;
			};
			partition@200000 {
				label = "Linux";
				reg = <0x200000 0xe00000>;
			};
			partition@1000000 {
				label = "Filesystem";
				reg = <0x1000000 0x3f000000>;
			};
		};
	};
};

/* CON4 on CP1 expansion */
&cp1_sata0 {
	status = "okay";

	sata-port@0 {
		phys = <&cp1_comphy1 0>;
		phy-names = "cp1-sata0-0-phy";
	};
	sata-port@1 {
		phys = <&cp1_comphy3 1>;
		phy-names = "cp1-sata0-1-phy";
	};
};

&cp1_utmi {
	status = "okay";
};

/* CON9 on CP1 expansion */
&cp1_usb3_0 {
	usb-phy = <&cp1_usb3_0_phy>;
	phys = <&cp1_utmi0>;
	phy-names = "utmi";
	dr_mode = "host";
	status = "okay";
};

/* CON10 on CP1 expansion */
&cp1_usb3_1 {
	phys = <&cp1_utmi1>;
	phy-names = "utmi";
	status = "okay";
};

&cp1_mdio {
	status = "okay";

	phy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&cp1_ethernet {
	status = "okay";
};

&cp1_eth0 {
	status = "okay";
	phy-mode = "10gbase-r";

	fixed-link {
		speed = <10000>;
		full-duplex;
	};
};

&cp1_eth1 {
	status = "okay";
	phy = <&phy0>;
	phy-mode = "rgmii-id";
};

&ap_sdhci0 {
	status = "okay";
	bus-width = <4>;
	non-removable;
};

&cp0_sdhci0 {
	status = "okay";
	bus-width = <8>;
	non-removable;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for MACCHIATOBin Armada 8040 community board platform
 */

#include <dt-bindings/leds/common.h>

#include "armada-8040-mcbin.dtsi"

/ {
	model = "Marvell 8040 MACCHIATOBin Single-shot";
	compatible = "marvell,armada8040-mcbin-singleshot",
			"marvell,armada8040-mcbin", "marvell,armada8040",
			"marvell,armada-ap806-quad", "marvell,armada-ap806";

	leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&cp0_led18_pins>;
		pinctrl-names = "default";

		led18 {
			gpios = <&cp0_gpio2 1 GPIO_ACTIVE_LOW>;
			function = LED_FUNCTION_HEARTBEAT;
			color = <LED_COLOR_ID_GREEN>;
			linux,default-trigger = "heartbeat";
		};
	};
};

&cp0_eth0 {
	status = "okay";
	phy-mode = "10gbase-r";
	managed = "in-band-status";
	sfp = <&sfp_eth0>;
};

&cp1_eth0 {
	status = "okay";
	phy-mode = "10gbase-r";
	managed = "in-band-status";
	sfp = <&sfp_eth1>;
};

&cp0_pinctrl {
	cp0_led18_pins: led18-pins {
		marvell,pins = "mpp33";
		marvell,function = "gpio";
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for MACCHIATOBin Armada 8040 community board platform
 */

#include "armada-8040-mcbin.dtsi"

/ {
	model = "Marvell 8040 MACCHIATOBin Double-shot";
	compatible = "marvell,armada8040-mcbin-doubleshot",
			"marvell,armada8040-mcbin", "marvell,armada8040",
			"marvell,armada-ap806-quad", "marvell,armada-ap806";
};

&cp0_xmdio {
	status = "okay";

	phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <0>;
		sfp = <&sfp_eth0>;
	};

	phy8: ethernet-phy@8 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <8>;
		sfp = <&sfp_eth1>;
	};
};

&cp0_eth0 {
	status = "okay";
	/* Network PHY */
	phy = <&phy0>;
	phy-mode = "10gbase-r";
};

&cp1_eth0 {
	status = "okay";
	/* Network PHY */
	phy = <&phy8>;
	phy-mode = "10gbase-r";
};