code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT7530 and MT7531 Ethernet Switches

maintainers:
  - Arınç ÜNAL <arinc.unal@arinc9.com>
  - Landen Chao <Landen.Chao@mediatek.com>
  - DENG Qingfang <dqfext@gmail.com>
  - Sean Wang <sean.wang@mediatek.com>

description: |
  There are two versions of MT7530, standalone and in a multi-chip module.

  MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN,
  MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs.

  MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs
  and the switch registers are directly mapped into SoC's memory map rather than
  using MDIO. The DSA driver currently doesn't support this.

  There is only the standalone version of MT7531.

  Port 5 on MT7530 has got various ways of configuration.

  For standalone MT7530:

    - Port 5 can be used as a CPU port.

    - PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC
      which port 5 is wired to. Usually used for connecting the wan port
      directly to the CPU to achieve 2 Gbps routing in total.

      The driver looks up the reg on the ethernet-phy node which the phy-handle
      property refers to on the gmac node to mux the specified phy.

      The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the
      compatible string and the reg must be 1. So, for now, only gmac1 of an
      MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this.
      Check out example 5 for a similar configuration.

    - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave.
      Check out example 7 for a similar configuration.

  For multi-chip module MT7530:

    - Port 5 can be used as a CPU port.

    - PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC.
      Usually used for connecting the wan port directly to the CPU to achieve 2
      Gbps routing in total.

      The driver looks up the reg on the ethernet-phy node which the phy-handle
      property refers to on the gmac node to mux the specified phy.

      For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.
      Check out example 5.

    - In case of an external phy wired to gmac1 of the SoC, port 5 must not be
      enabled.

      In case of muxing PHY 0 or 4, the external phy must not be enabled.

      For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.
      Check out example 6.

    - Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave.
      The external phy must be wired TX to TX to gmac1 of the SoC for this to
      work. Ubiquiti EdgeRouter X SFP is wired this way.

      Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX.

      For the MT7621 SoCs, rgmii2 group must be claimed with gpio function.
      Check out example 7.

properties:
  compatible:
    oneOf:
      - description:
          Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC
        const: mediatek,mt7530

      - description:
          Standalone MT7531
        const: mediatek,mt7531

      - description:
          Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs
        const: mediatek,mt7621

  reg:
    maxItems: 1

  core-supply:
    description:
      Phandle to the regulator node necessary for the core power.

  "#gpio-cells":
    const: 2

  gpio-controller:
    type: boolean
    description:
      If defined, LED controller of the MT7530 switch will run on GPIO mode.

      There are 15 controllable pins.
      port 0 LED 0..2 as GPIO 0..2
      port 1 LED 0..2 as GPIO 3..5
      port 2 LED 0..2 as GPIO 6..8
      port 3 LED 0..2 as GPIO 9..11
      port 4 LED 0..2 as GPIO 12..14

  "#interrupt-cells":
    const: 1

  interrupt-controller: true

  interrupts:
    maxItems: 1

  io-supply:
    description:
      Phandle to the regulator node necessary for the I/O power.
      See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for
      details for the regulator setup on these boards.

  mediatek,mcm:
    type: boolean
    description:
      Used for MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs which the MT7530
      switch is a part of the multi-chip module.

  reset-gpios:
    description:
      GPIO to reset the switch. Use this if mediatek,mcm is not used.
      This property is optional because some boards share the reset line with
      other components which makes it impossible to probe the switch if the
      reset line is used.
    maxItems: 1

  reset-names:
    const: mcm

  resets:
    description:
      Phandle pointing to the system reset controller with line index for the
      ethsys.
    maxItems: 1

patternProperties:
  "^(ethernet-)?ports$":
    type: object

    patternProperties:
      "^(ethernet-)?port@[0-9]+$":
        type: object
        description: Ethernet switch ports

        unevaluatedProperties: false

        properties:
          reg:
            description:
              Port address described must be 5 or 6 for CPU port and from 0 to 5
              for user ports.

        allOf:
          - $ref: dsa-port.yaml#
          - if:
              required: [ ethernet ]
            then:
              properties:
                reg:
                  enum:
                    - 5
                    - 6

required:
  - compatible
  - reg

$defs:
  mt7530-dsa-port:
    patternProperties:
      "^(ethernet-)?ports$":
        patternProperties:
          "^(ethernet-)?port@[0-9]+$":
            if:
              required: [ ethernet ]
            then:
              if:
                properties:
                  reg:
                    const: 5
              then:
                properties:
                  phy-mode:
                    enum:
                      - gmii
                      - mii
                      - rgmii
              else:
                properties:
                  phy-mode:
                    enum:
                      - rgmii
                      - trgmii

  mt7531-dsa-port:
    patternProperties:
      "^(ethernet-)?ports$":
        patternProperties:
          "^(ethernet-)?port@[0-9]+$":
            if:
              required: [ ethernet ]
            then:
              if:
                properties:
                  reg:
                    const: 5
              then:
                properties:
                  phy-mode:
                    enum:
                      - 1000base-x
                      - 2500base-x
                      - rgmii
                      - sgmii
              else:
                properties:
                  phy-mode:
                    enum:
                      - 1000base-x
                      - 2500base-x
                      - sgmii

allOf:
  - $ref: dsa.yaml#
  - if:
      required:
        - mediatek,mcm
    then:
      properties:
        reset-gpios: false

      required:
        - resets
        - reset-names

  - dependencies:
      interrupt-controller: [ interrupts ]

  - if:
      properties:
        compatible:
          const: mediatek,mt7530
    then:
      $ref: "#/$defs/mt7530-dsa-port"
      required:
        - core-supply
        - io-supply

  - if:
      properties:
        compatible:
          const: mediatek,mt7531
    then:
      $ref: "#/$defs/mt7531-dsa-port"
      properties:
        gpio-controller: false
        mediatek,mcm: false

  - if:
      properties:
        compatible:
          const: mediatek,mt7621
    then:
      $ref: "#/$defs/mt7530-dsa-port"
      required:
        - mediatek,mcm

unevaluatedProperties: false

examples:
  # Example 1: Standalone MT7530
  - |
    #include <dt-bindings/gpio/gpio.h>

    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        switch@1f {
            compatible = "mediatek,mt7530";
            reg = <0x1f>;

            reset-gpios = <&pio 33 0>;

            core-supply = <&mt6323_vpa_reg>;
            io-supply = <&mt6323_vemc3v3_reg>;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    label = "lan1";
                };

                port@1 {
                    reg = <1>;
                    label = "lan2";
                };

                port@2 {
                    reg = <2>;
                    label = "lan3";
                };

                port@3 {
                    reg = <3>;
                    label = "lan4";
                };

                port@4 {
                    reg = <4>;
                    label = "wan";
                };

                port@6 {
                    reg = <6>;
                    ethernet = <&gmac0>;
                    phy-mode = "rgmii";

                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                        pause;
                    };
                };
            };
        };
    };

  # Example 2: MT7530 in MT7623AI SoC
  - |
    #include <dt-bindings/reset/mt2701-resets.h>

    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        switch@1f {
            compatible = "mediatek,mt7530";
            reg = <0x1f>;

            mediatek,mcm;
            resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
            reset-names = "mcm";

            core-supply = <&mt6323_vpa_reg>;
            io-supply = <&mt6323_vemc3v3_reg>;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    label = "lan1";
                };

                port@1 {
                    reg = <1>;
                    label = "lan2";
                };

                port@2 {
                    reg = <2>;
                    label = "lan3";
                };

                port@3 {
                    reg = <3>;
                    label = "lan4";
                };

                port@4 {
                    reg = <4>;
                    label = "wan";
                };

                port@6 {
                    reg = <6>;
                    ethernet = <&gmac0>;
                    phy-mode = "trgmii";

                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                        pause;
                    };
                };
            };
        };
    };

  # Example 3: Standalone MT7531
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        switch@0 {
            compatible = "mediatek,mt7531";
            reg = <0>;

            reset-gpios = <&pio 54 0>;

            interrupt-controller;
            #interrupt-cells = <1>;
            interrupt-parent = <&pio>;
            interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    label = "lan1";
                };

                port@1 {
                    reg = <1>;
                    label = "lan2";
                };

                port@2 {
                    reg = <2>;
                    label = "lan3";
                };

                port@3 {
                    reg = <3>;
                    label = "lan4";
                };

                port@4 {
                    reg = <4>;
                    label = "wan";
                };

                port@6 {
                    reg = <6>;
                    ethernet = <&gmac0>;
                    phy-mode = "2500base-x";

                    fixed-link {
                        speed = <2500>;
                        full-duplex;
                        pause;
                    };
                };
            };
        };
    };

  # Example 4: MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs
  - |
    #include <dt-bindings/interrupt-controller/mips-gic.h>
    #include <dt-bindings/reset/mt7621-reset.h>

    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        switch@1f {
            compatible = "mediatek,mt7621";
            reg = <0x1f>;

            mediatek,mcm;
            resets = <&sysc MT7621_RST_MCM>;
            reset-names = "mcm";

            interrupt-controller;
            #interrupt-cells = <1>;
            interrupt-parent = <&gic>;
            interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    label = "lan1";
                };

                port@1 {
                    reg = <1>;
                    label = "lan2";
                };

                port@2 {
                    reg = <2>;
                    label = "lan3";
                };

                port@3 {
                    reg = <3>;
                    label = "lan4";
                };

                port@4 {
                    reg = <4>;
                    label = "wan";
                };

                port@6 {
                    reg = <6>;
                    ethernet = <&gmac0>;
                    phy-mode = "trgmii";

                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                        pause;
                    };
                };
            };
        };
    };

  # Example 5: MT7621: mux MT7530's phy4 to SoC's gmac1
  - |
    #include <dt-bindings/interrupt-controller/mips-gic.h>
    #include <dt-bindings/reset/mt7621-reset.h>

    ethernet {
        #address-cells = <1>;
        #size-cells = <0>;

        pinctrl-names = "default";
        pinctrl-0 = <&rgmii2_pins>;

        mac@1 {
            compatible = "mediatek,eth-mac";
            reg = <1>;

            phy-mode = "rgmii";
            phy-handle = <&example5_ethphy4>;
        };

        mdio {
            #address-cells = <1>;
            #size-cells = <0>;

            /* MT7530's phy4 */
            example5_ethphy4: ethernet-phy@4 {
                reg = <4>;
            };

            switch@1f {
                compatible = "mediatek,mt7621";
                reg = <0x1f>;

                mediatek,mcm;
                resets = <&sysc MT7621_RST_MCM>;
                reset-names = "mcm";

                interrupt-controller;
                #interrupt-cells = <1>;
                interrupt-parent = <&gic>;
                interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;

                ethernet-ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@0 {
                        reg = <0>;
                        label = "lan1";
                    };

                    port@1 {
                        reg = <1>;
                        label = "lan2";
                    };

                    port@2 {
                        reg = <2>;
                        label = "lan3";
                    };

                    port@3 {
                        reg = <3>;
                        label = "lan4";
                    };

                    /* Commented out, phy4 is muxed to gmac1.
                    port@4 {
                        reg = <4>;
                        label = "wan";
                    };
                    */

                    port@6 {
                        reg = <6>;
                        ethernet = <&gmac0>;
                        phy-mode = "trgmii";

                        fixed-link {
                            speed = <1000>;
                            full-duplex;
                            pause;
                        };
                    };
                };
            };
        };
    };

  # Example 6: MT7621: mux external phy to SoC's gmac1
  - |
    #include <dt-bindings/interrupt-controller/mips-gic.h>
    #include <dt-bindings/reset/mt7621-reset.h>

    ethernet {
        #address-cells = <1>;
        #size-cells = <0>;

        pinctrl-names = "default";
        pinctrl-0 = <&rgmii2_pins>;

        mac@1 {
            compatible = "mediatek,eth-mac";
            reg = <1>;

            phy-mode = "rgmii";
            phy-handle = <&example6_ethphy7>;
        };

        mdio {
            #address-cells = <1>;
            #size-cells = <0>;

            /* External PHY */
            example6_ethphy7: ethernet-phy@7 {
                reg = <7>;
                phy-mode = "rgmii";
            };

            switch@1f {
                compatible = "mediatek,mt7621";
                reg = <0x1f>;

                mediatek,mcm;
                resets = <&sysc MT7621_RST_MCM>;
                reset-names = "mcm";

                interrupt-controller;
                #interrupt-cells = <1>;
                interrupt-parent = <&gic>;
                interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;

                ethernet-ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@0 {
                        reg = <0>;
                        label = "lan1";
                    };

                    port@1 {
                        reg = <1>;
                        label = "lan2";
                    };

                    port@2 {
                        reg = <2>;
                        label = "lan3";
                    };

                    port@3 {
                        reg = <3>;
                        label = "lan4";
                    };

                    port@4 {
                        reg = <4>;
                        label = "wan";
                    };

                    port@6 {
                        reg = <6>;
                        ethernet = <&gmac0>;
                        phy-mode = "trgmii";

                        fixed-link {
                            speed = <1000>;
                            full-duplex;
                            pause;
                        };
                    };
                };
            };
        };
    };

  # Example 7: MT7621: mux external phy to MT7530's port 5
  - |
    #include <dt-bindings/interrupt-controller/mips-gic.h>
    #include <dt-bindings/reset/mt7621-reset.h>

    ethernet {
        #address-cells = <1>;
        #size-cells = <0>;

        pinctrl-names = "default";
        pinctrl-0 = <&rgmii2_pins>;

        mdio {
            #address-cells = <1>;
            #size-cells = <0>;

            /* External PHY */
            example7_ethphy7: ethernet-phy@7 {
                reg = <7>;
                phy-mode = "rgmii";
            };

            switch@1f {
                compatible = "mediatek,mt7621";
                reg = <0x1f>;

                mediatek,mcm;
                resets = <&sysc MT7621_RST_MCM>;
                reset-names = "mcm";

                interrupt-controller;
                #interrupt-cells = <1>;
                interrupt-parent = <&gic>;
                interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;

                ethernet-ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@0 {
                        reg = <0>;
                        label = "lan1";
                    };

                    port@1 {
                        reg = <1>;
                        label = "lan2";
                    };

                    port@2 {
                        reg = <2>;
                        label = "lan3";
                    };

                    port@3 {
                        reg = <3>;
                        label = "lan4";
                    };

                    port@4 {
                        reg = <4>;
                        label = "wan";
                    };

                    port@5 {
                        reg = <5>;
                        label = "extphy";
                        phy-mode = "rgmii-txid";
                        phy-handle = <&example7_ethphy7>;
                    };

                    port@6 {
                        reg = <6>;
                        ethernet = <&gmac0>;
                        phy-mode = "trgmii";

                        fixed-link {
                            speed = <1000>;
                            full-duplex;
                            pause;
                        };
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip KSZ Series Ethernet switches

maintainers:
  - Marek Vasut <marex@denx.de>
  - Woojung Huh <Woojung.Huh@microchip.com>

allOf:
  - $ref: dsa.yaml#
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

properties:
  # See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional
  # required and optional properties.
  compatible:
    enum:
      - microchip,ksz8765
      - microchip,ksz8794
      - microchip,ksz8795
      - microchip,ksz8863
      - microchip,ksz8873
      - microchip,ksz9477
      - microchip,ksz9897
      - microchip,ksz9896
      - microchip,ksz9567
      - microchip,ksz8565
      - microchip,ksz9893
      - microchip,ksz9563
      - microchip,ksz8563

  reset-gpios:
    description:
      Should be a gpio specifier for a reset line.
    maxItems: 1

  microchip,synclko-125:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.

  microchip,synclko-disable:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set if the output SYNCLKO clock should be disabled. Do not mix with
      microchip,synclko-125.

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    // Ethernet switch connected via SPI to the host, CPU port wired to eth0:
    eth0 {
        fixed-link {
            speed = <1000>;
            full-duplex;
        };
    };

    spi0 {
        #address-cells = <1>;
        #size-cells = <0>;

        pinctrl-0 = <&pinctrl_spi_ksz>;
        cs-gpios = <&pioC 25 0>;
        id = <1>;

        ksz9477: switch@0 {
            compatible = "microchip,ksz9477";
            reg = <0>;
            reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;

            spi-max-frequency = <44000000>;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;
                port@0 {
                    reg = <0>;
                    label = "lan1";
                };
                port@1 {
                    reg = <1>;
                    label = "lan2";
                };
                port@2 {
                    reg = <2>;
                    label = "lan3";
                };
                port@3 {
                    reg = <3>;
                    label = "lan4";
                };
                port@4 {
                    reg = <4>;
                    label = "lan5";
                };
                port@5 {
                    reg = <5>;
                    ethernet = <&eth0>;
                    phy-mode = "rgmii";

                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                    };
                };
            };
        };

        ksz8565: switch@1 {
            compatible = "microchip,ksz8565";
            reg = <1>;

            spi-max-frequency = <44000000>;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;
                port@0 {
                    reg = <0>;
                    label = "lan1";
                };
                port@1 {
                    reg = <1>;
                    label = "lan2";
                };
                port@2 {
                    reg = <2>;
                    label = "lan3";
                };
                port@3 {
                    reg = <3>;
                    label = "lan4";
                };
                port@6 {
                    reg = <6>;
                    ethernet = <&eth0>;
                    phy-mode = "rgmii";

                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                    };
                };
            };
        };
    };
...

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/microchip,lan937x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LAN937x Ethernet Switch Series Tree Bindings

maintainers:
  - UNGLinuxDriver@microchip.com

allOf:
  - $ref: dsa.yaml#

properties:
  compatible:
    enum:
      - microchip,lan9370
      - microchip,lan9371
      - microchip,lan9372
      - microchip,lan9373
      - microchip,lan9374

  reg:
    maxItems: 1

  spi-max-frequency:
    maximum: 50000000

  reset-gpios:
    description: Optional gpio specifier for a reset line
    maxItems: 1

  mdio:
    $ref: /schemas/net/mdio.yaml#
    unevaluatedProperties: false

patternProperties:
  "^(ethernet-)?ports$":
    patternProperties:
      "^(ethernet-)?port@[0-9]+$":
        allOf:
          - if:
              properties:
                phy-mode:
                  contains:
                    enum:
                      - rgmii
                      - rgmii-id
                      - rgmii-txid
                      - rgmii-rxid
            then:
              properties:
                rx-internal-delay-ps:
                  enum: [0, 2000]
                  default: 0
                tx-internal-delay-ps:
                  enum: [0, 2000]
                  default: 0

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    macb0 {
            #address-cells = <1>;
            #size-cells = <0>;

            fixed-link {
                    speed = <1000>;
                    full-duplex;
            };
    };

    spi {
            #address-cells = <1>;
            #size-cells = <0>;

            lan9374: switch@0 {
                    compatible = "microchip,lan9374";
                    reg = <0>;
                    spi-max-frequency = <44000000>;

                    ethernet-ports {
                            #address-cells = <1>;
                            #size-cells = <0>;

                            port@0 {
                                    reg = <0>;
                                    label = "lan1";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy0>;
                            };

                            port@1 {
                                    reg = <1>;
                                    label = "lan2";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy1>;
                            };

                            port@2 {
                                    reg = <2>;
                                    label = "lan4";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy2>;
                            };

                            port@3 {
                                    reg = <3>;
                                    label = "lan6";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy3>;
                            };

                            port@4 {
                                    reg = <4>;
                                    phy-mode = "rgmii";
                                    tx-internal-delay-ps = <2000>;
                                    rx-internal-delay-ps = <2000>;
                                    ethernet = <&macb0>;

                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };

                            port@5 {
                                    reg = <5>;
                                    label = "lan7";
                                    phy-mode = "rgmii";
                                    tx-internal-delay-ps = <2000>;
                                    rx-internal-delay-ps = <2000>;

                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };

                            port@6 {
                                    reg = <6>;
                                    label = "lan5";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy6>;
                            };

                            port@7 {
                                    reg = <7>;
                                    label = "lan3";
                                    phy-mode = "internal";
                                    phy-handle = <&t1phy7>;
                            };
                    };

                    mdio {
                            #address-cells = <1>;
                            #size-cells = <0>;

                            t1phy0: ethernet-phy@0{
                                    reg = <0x0>;
                            };

                            t1phy1: ethernet-phy@1{
                                    reg = <0x1>;
                            };

                            t1phy2: ethernet-phy@2{
                                    reg = <0x2>;
                            };

                            t1phy3: ethernet-phy@3{
                                    reg = <0x3>;
                            };

                            t1phy6: ethernet-phy@6{
                                    reg = <0x6>;
                            };

                            t1phy7: ethernet-phy@7{
                                    reg = <0x7>;
                            };
                    };
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/mscc,ocelot.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip Ocelot Switch Family Device Tree Bindings

maintainers:
  - Vladimir Oltean <vladimir.oltean@nxp.com>
  - Claudiu Manoil <claudiu.manoil@nxp.com>
  - Alexandre Belloni <alexandre.belloni@bootlin.com>
  - UNGLinuxDriver@microchip.com

description: |
  There are multiple switches which are either part of the Ocelot-1 family, or
  derivatives of this architecture. These switches can be found embedded in
  various SoCs and accessed using MMIO, or as discrete chips and accessed over
  SPI or PCIe. The present DSA binding shall be used when the host controlling
  them performs packet I/O primarily through an Ethernet port of the switch
  (which is attached to an Ethernet port of the host), rather than through
  Frame DMA or register-based I/O.

  VSC9953 (Seville):

    This is found in the NXP T1040, where it is a memory-mapped platform
    device.

    The following PHY interface types are supported:

      - phy-mode = "internal": on ports 8 and 9
      - phy-mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
      - phy-mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
      - phy-mode = "1000base-x": on ports 0, 1, 2, 3, 4, 5, 6, 7

  VSC9959 (Felix):

    This is found in the NXP LS1028A. It is a PCI device, part of the larger
    enetc root complex. As a result, the ethernet-switch node is a sub-node of
    the PCIe root complex node and its "reg" property conforms to the parent
    node bindings, describing it as PF 5 of device 0, bus 0.

    If any external switch port is enabled, the enetc PF2 (enetc_port2) should
    be enabled as well. This is because the internal MDIO bus (exposed through
    EA BAR 0) used to access the MAC PCS registers truly belongs to the enetc
    port 2 and not to Felix.

    The following PHY interface types are supported:

      - phy-mode = "internal": on ports 4 and 5
      - phy-mode = "sgmii": on ports 0, 1, 2, 3
      - phy-mode = "qsgmii": on ports 0, 1, 2, 3
      - phy-mode = "usxgmii": on ports 0, 1, 2, 3
      - phy-mode = "1000base-x": on ports 0, 1, 2, 3
      - phy-mode = "2500base-x": on ports 0, 1, 2, 3

properties:
  compatible:
    enum:
      - mscc,vsc9953-switch
      - pci1957,eef0

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

    description:
      Used to signal availability of PTP TX timestamps, and state changes of
      the MAC merge layer of ports that support Frame Preemption.

  little-endian: true
  big-endian: true

required:
  - compatible
  - reg

allOf:
  - $ref: dsa.yaml#
  - if:
      properties:
        compatible:
          const: pci1957,eef0
    then:
      required:
        - interrupts

unevaluatedProperties: false

examples:
  # Felix VSC9959 (NXP LS1028A)
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pcie { /* Integrated Endpoint Root Complex */
        #address-cells = <3>;
        #size-cells = <2>;

        ethernet-switch@0,5 {
            compatible = "pci1957,eef0";
            reg = <0x000500 0 0 0 0>;
            interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy0>;
                    managed = "in-band-status";
                };

                port@1 {
                    reg = <1>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy1>;
                    managed = "in-band-status";
                };

                port@2 {
                    reg = <2>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy2>;
                    managed = "in-band-status";
                };

                port@3 {
                    reg = <3>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy3>;
                    managed = "in-band-status";
                };

                port@4 {
                    reg = <4>;
                    ethernet = <&enetc_port2>;
                    phy-mode = "internal";

                    fixed-link {
                        speed = <2500>;
                        full-duplex;
                        pause;
                    };
                };

                port@5 {
                    reg = <5>;
                    ethernet = <&enetc_port3>;
                    phy-mode = "internal";

                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                        pause;
                    };
                };
            };
        };
    };
  # Seville VSC9953 (NXP T1040)
  - |
    soc {
        #address-cells = <1>;
        #size-cells = <1>;

        ethernet-switch@800000 {
            compatible = "mscc,vsc9953-switch";
            reg = <0x800000 0x290000>;
            little-endian;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy0>;
                    managed = "in-band-status";
                };

                port@1 {
                    reg = <1>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy1>;
                    managed = "in-band-status";
                };

                port@2 {
                    reg = <2>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy2>;
                    managed = "in-band-status";
                };

                port@3 {
                    reg = <3>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy3>;
                    managed = "in-band-status";
                };

                port@4 {
                    reg = <4>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy4>;
                    managed = "in-band-status";
                };

                port@5 {
                    reg = <5>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy5>;
                    managed = "in-band-status";
                };

                port@6 {
                    reg = <6>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy6>;
                    managed = "in-band-status";
                };

                port@7 {
                    reg = <7>;
                    phy-mode = "qsgmii";
                    phy-handle = <&phy7>;
                    managed = "in-band-status";
                };

                port@8 {
                    reg = <8>;
                    phy-mode = "internal";
                    ethernet = <&enet0>;

                    fixed-link {
                        speed = <2500>;
                        full-duplex;
                        pause;
                    };
                };

                port@9 {
                    reg = <9>;
                    phy-mode = "internal";
                    ethernet = <&enet1>;

                    fixed-link {
                        speed = <2500>;
                        full-duplex;
                        pause;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP SJA1105 Automotive Ethernet Switch Family Device Tree Bindings

description:
  The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
  least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
  cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed
  depends on the SPI bus master driver.

allOf:
  - $ref: "dsa.yaml#"
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

maintainers:
  - Vladimir Oltean <vladimir.oltean@nxp.com>

properties:
  compatible:
    enum:
      - nxp,sja1105e
      - nxp,sja1105t
      - nxp,sja1105p
      - nxp,sja1105q
      - nxp,sja1105r
      - nxp,sja1105s
      - nxp,sja1110a
      - nxp,sja1110b
      - nxp,sja1110c
      - nxp,sja1110d

  reg:
    maxItems: 1

  # Optional container node for the 2 internal MDIO buses of the SJA1110
  # (one for the internal 100base-T1 PHYs and the other for the single
  # 100base-TX PHY). The "reg" property does not have physical significance.
  # The PHY addresses to port correspondence is as follows: for 100base-T1,
  # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
  # PHY 1.
  mdios:
    type: object

    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    patternProperties:
      "^mdio@[0-1]$":
        $ref: /schemas/net/mdio.yaml#
        unevaluatedProperties: false

        properties:
          compatible:
            oneOf:
              - enum:
                  - nxp,sja1110-base-t1-mdio
                  - nxp,sja1110-base-tx-mdio

          reg:
            oneOf:
              - enum:
                  - 0
                  - 1

        required:
          - compatible
          - reg

patternProperties:
  "^(ethernet-)?ports$":
    patternProperties:
      "^(ethernet-)?port@[0-9]+$":
        allOf:
          - if:
              properties:
                phy-mode:
                  contains:
                    enum:
                      - rgmii
                      - rgmii-rxid
                      - rgmii-txid
                      - rgmii-id
            then:
              properties:
                rx-internal-delay-ps:
                  $ref: "#/$defs/internal-delay-ps"
                tx-internal-delay-ps:
                  $ref: "#/$defs/internal-delay-ps"

required:
  - compatible
  - reg

$defs:
  internal-delay-ps:
    description:
      Disable tunable delay lines using 0 ps, or enable them and select
      the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps
      (101.7 degree shift) in increments of 0.9 degrees (20 ps).
    enum:
      [0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840,
       1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080,
       2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260]

unevaluatedProperties: false

examples:
  - |
    spi {
            #address-cells = <1>;
            #size-cells = <0>;

            ethernet-switch@1 {
                    reg = <0x1>;
                    compatible = "nxp,sja1105t";

                    ethernet-ports {
                            #address-cells = <1>;
                            #size-cells = <0>;

                            port@0 {
                                    phy-handle = <&rgmii_phy6>;
                                    phy-mode = "rgmii-id";
                                    rx-internal-delay-ps = <0>;
                                    tx-internal-delay-ps = <0>;
                                    reg = <0>;
                            };

                            port@1 {
                                    phy-handle = <&rgmii_phy3>;
                                    phy-mode = "rgmii-id";
                                    rx-internal-delay-ps = <0>;
                                    tx-internal-delay-ps = <0>;
                                    reg = <1>;
                            };

                            port@2 {
                                    phy-handle = <&rgmii_phy4>;
                                    phy-mode = "rgmii-id";
                                    rx-internal-delay-ps = <0>;
                                    tx-internal-delay-ps = <0>;
                                    reg = <2>;
                            };

                            port@3 {
                                    phy-handle = <&rgmii_phy4>;
                                    phy-mode = "rgmii-id";
                                    rx-internal-delay-ps = <0>;
                                    tx-internal-delay-ps = <0>;
                                    reg = <3>;
                            };

                            port@4 {
                                    ethernet = <&enet2>;
                                    phy-mode = "rgmii";
                                    rx-internal-delay-ps = <0>;
                                    tx-internal-delay-ps = <0>;
                                    reg = <4>;

                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };
                    };
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Atheros QCA83xx switch family

maintainers:
  - John Crispin <john@phrozen.org>

description:
  If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
  describing a port needs to have a valid phandle referencing the internal PHY
  it is connected to. This is because there is no N:N mapping of port and PHY
  ID. To declare the internal mdio-bus configuration, declare an MDIO node in
  the switch node and declare the phandle for the port, referencing the internal
  PHY it is connected to. In this config, an internal mdio-bus is registered and
  the MDIO master is used for communication. Mixed external and internal
  mdio-bus configurations are not supported by the hardware.

properties:
  compatible:
    oneOf:
      - enum:
          - qca,qca8327
          - qca,qca8328
          - qca,qca8334
          - qca,qca8337
    description: |
      qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
      qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
      qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
      qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package

  reg:
    maxItems: 1

  reset-gpios:
    description:
      GPIO to be used to reset the whole device
    maxItems: 1

  qca,ignore-power-on-sel:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Ignore power-on pin strapping to configure LED open-drain or EEPROM
      presence. This is needed for devices with incorrect configuration or when
      the OEM has decided not to use pin strapping and falls back to SW regs.

  qca,led-open-drain:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
      be set, otherwise the driver will fail at probe. This is required if the
      OEM does not use pin strapping to set this mode and prefers to set it
      using SW regs. The pin strappings related to LED open-drain mode are
      B68 on the QCA832x and B49 on the QCA833x.

  mdio:
    $ref: /schemas/net/mdio.yaml#
    unevaluatedProperties: false
    description: Qca8k switch have an internal mdio to access switch port.
                 If this is not present, the legacy mapping is used and the
                 internal mdio access is used.
                 With the legacy mapping the reg corresponding to the internal
                 mdio is the switch reg with an offset of -1.

patternProperties:
  "^(ethernet-)?ports$":
    type: object
    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    patternProperties:
      "^(ethernet-)?port@[0-6]$":
        type: object
        description: Ethernet switch ports

        $ref: dsa-port.yaml#

        properties:
          qca,sgmii-rxclk-falling-edge:
            $ref: /schemas/types.yaml#/definitions/flag
            description:
              Set the receive clock phase to falling edge. Mostly commonly used on
              the QCA8327 with CPU port 0 set to SGMII.

          qca,sgmii-txclk-falling-edge:
            $ref: /schemas/types.yaml#/definitions/flag
            description:
              Set the transmit clock phase to falling edge.

          qca,sgmii-enable-pll:
            $ref: /schemas/types.yaml#/definitions/flag
            description:
              For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
              Signal Detection. On the QCA8327 this should not be enabled, otherwise
              the SGMII port will not initialize. When used on the QCA8337, revision 3
              or greater, a warning will be displayed. When the CPU port is set to
              SGMII on the QCA8337, it is advised to set this unless a communication
              issue is observed.

        unevaluatedProperties: false

oneOf:
  - required:
      - ports
  - required:
      - ethernet-ports

required:
  - compatible
  - reg

additionalProperties: true

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        external_phy_port1: ethernet-phy@0 {
            reg = <0>;
        };

        external_phy_port2: ethernet-phy@1 {
            reg = <1>;
        };

        external_phy_port3: ethernet-phy@2 {
            reg = <2>;
        };

        external_phy_port4: ethernet-phy@3 {
            reg = <3>;
        };

        external_phy_port5: ethernet-phy@4 {
            reg = <4>;
        };

        switch@10 {
            compatible = "qca,qca8337";
            #address-cells = <1>;
            #size-cells = <0>;
            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
            reg = <0x10>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    ethernet = <&gmac1>;
                    phy-mode = "rgmii";

                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                    };
                };

                port@1 {
                    reg = <1>;
                    label = "lan1";
                    phy-handle = <&external_phy_port1>;
                };

                port@2 {
                    reg = <2>;
                    label = "lan2";
                    phy-handle = <&external_phy_port2>;
                };

                port@3 {
                    reg = <3>;
                    label = "lan3";
                    phy-handle = <&external_phy_port3>;
                };

                port@4 {
                    reg = <4>;
                    label = "lan4";
                    phy-handle = <&external_phy_port4>;
                };

                port@5 {
                    reg = <5>;
                    label = "wan";
                    phy-handle = <&external_phy_port5>;
                };
            };
        };
    };
  - |
    #include <dt-bindings/gpio/gpio.h>

    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        switch@10 {
            compatible = "qca,qca8337";
            #address-cells = <1>;
            #size-cells = <0>;
            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
            reg = <0x10>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    ethernet = <&gmac1>;
                    phy-mode = "rgmii";

                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                    };
                };

                port@1 {
                    reg = <1>;
                    label = "lan1";
                    phy-mode = "internal";
                    phy-handle = <&internal_phy_port1>;
                };

                port@2 {
                    reg = <2>;
                    label = "lan2";
                    phy-mode = "internal";
                    phy-handle = <&internal_phy_port2>;
                };

                port@3 {
                    reg = <3>;
                    label = "lan3";
                    phy-mode = "internal";
                    phy-handle = <&internal_phy_port3>;
                };

                port@4 {
                    reg = <4>;
                    label = "lan4";
                    phy-mode = "internal";
                    phy-handle = <&internal_phy_port4>;
                };

                port@5 {
                    reg = <5>;
                    label = "wan";
                    phy-mode = "internal";
                    phy-handle = <&internal_phy_port5>;
                };

                port@6 {
                    reg = <0>;
                    ethernet = <&gmac1>;
                    phy-mode = "sgmii";

                    qca,sgmii-rxclk-falling-edge;

                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                    };
                };
            };

            mdio {
                #address-cells = <1>;
                #size-cells = <0>;

                internal_phy_port1: ethernet-phy@0 {
                    reg = <0>;
                };

                internal_phy_port2: ethernet-phy@1 {
                    reg = <1>;
                };

                internal_phy_port3: ethernet-phy@2 {
                    reg = <2>;
                };

                internal_phy_port4: ethernet-phy@3 {
                    reg = <3>;
                };

                internal_phy_port5: ethernet-phy@4 {
                    reg = <4>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/realtek.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Realtek switches for unmanaged switches

allOf:
  - $ref: dsa.yaml#

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description:
  Realtek advertises these chips as fast/gigabit switches or unmanaged
  switches. They can be controlled using different interfaces, like SMI,
  MDIO or SPI.

  The SMI "Simple Management Interface" is a two-wire protocol using
  bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
  not use the MDIO protocol. This binding defines how to specify the
  SMI-based Realtek devices. The realtek-smi driver is a platform driver
  and it must be inserted inside a platform node.

  The MDIO-connected switches use MDIO protocol to access their registers.
  The realtek-mdio driver is an MDIO driver and it must be inserted inside
  an MDIO node.

  The compatible string is only used to identify which (silicon) family the
  switch belongs to. Roughly speaking, a family is any set of Realtek switches
  whose chip identification register(s) have a common location and semantics.
  The different models in a given family can be automatically disambiguated by
  parsing the chip identification register(s) according to the given family,
  avoiding the need for a unique compatible string for each model.

properties:
  compatible:
    enum:
      - realtek,rtl8365mb
      - realtek,rtl8366rb
    description: |
      realtek,rtl8365mb:
        Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB,
        RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S,
        RTL8367SB, RTL8370MB, RTL8310SR
      realtek,rtl8366rb:
        Use with models RTL8366RB, RTL8366S

  mdc-gpios:
    description: GPIO line for the MDC clock line.
    maxItems: 1

  mdio-gpios:
    description: GPIO line for the MDIO data line.
    maxItems: 1

  reset-gpios:
    description: GPIO to be used to reset the whole device
    maxItems: 1

  realtek,disable-leds:
    type: boolean
    description: |
      if the LED drivers are not used in the hardware design,
      this will disable them so they are not turned on
      and wasting power.

  interrupt-controller:
    type: object
    description: |
      This defines an interrupt controller with an IRQ line (typically
      a GPIO) that will demultiplex and handle the interrupt from the single
      interrupt line coming out of one of the Realtek switch chips. It most
      importantly provides link up/down interrupts to the PHY blocks inside
      the ASIC.

    properties:

      interrupt-controller: true

      interrupts:
        maxItems: 1
        description:
          A single IRQ line from the switch, either active LOW or HIGH

      '#address-cells':
        const: 0

      '#interrupt-cells':
        const: 1

    required:
      - interrupt-controller
      - '#address-cells'
      - '#interrupt-cells'

  mdio:
    $ref: /schemas/net/mdio.yaml#
    unevaluatedProperties: false

    properties:
      compatible:
        const: realtek,smi-mdio

if:
  required:
    - reg

then:
  $ref: /schemas/spi/spi-peripheral-props.yaml#
  not:
    required:
      - mdc-gpios
      - mdio-gpios
      - mdio

  properties:
    mdc-gpios: false
    mdio-gpios: false
    mdio: false

else:
  required:
    - mdc-gpios
    - mdio-gpios
    - mdio
    - reset-gpios

required:
  - compatible

    #  - mdc-gpios
    #  - mdio-gpios
    #  - reset-gpios
    #  - mdio

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    platform {
            switch {
                    compatible = "realtek,rtl8366rb";
                    /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
                    mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
                    mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
                    reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;

                    switch_intc1: interrupt-controller {
                            /* GPIO 15 provides the interrupt */
                            interrupt-parent = <&gpio0>;
                            interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
                            interrupt-controller;
                            #address-cells = <0>;
                            #interrupt-cells = <1>;
                    };

                    ports {
                            #address-cells = <1>;
                            #size-cells = <0>;
                            port@0 {
                                    reg = <0>;
                                    label = "lan0";
                                    phy-handle = <&phy0>;
                            };
                            port@1 {
                                    reg = <1>;
                                    label = "lan1";
                                    phy-handle = <&phy1>;
                            };
                            port@2 {
                                    reg = <2>;
                                    label = "lan2";
                                    phy-handle = <&phy2>;
                            };
                            port@3 {
                                    reg = <3>;
                                    label = "lan3";
                                    phy-handle = <&phy3>;
                            };
                            port@4 {
                                    reg = <4>;
                                    label = "wan";
                                    phy-handle = <&phy4>;
                            };
                            port@5 {
                                    reg = <5>;
                                    ethernet = <&gmac0>;
                                    phy-mode = "rgmii";
                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };
                    };

                    mdio {
                            compatible = "realtek,smi-mdio";
                            #address-cells = <1>;
                            #size-cells = <0>;

                            phy0: ethernet-phy@0 {
                                    reg = <0>;
                                    interrupt-parent = <&switch_intc1>;
                                    interrupts = <0>;
                            };
                            phy1: ethernet-phy@1 {
                                    reg = <1>;
                                    interrupt-parent = <&switch_intc1>;
                                    interrupts = <1>;
                            };
                            phy2: ethernet-phy@2 {
                                    reg = <2>;
                                    interrupt-parent = <&switch_intc1>;
                                    interrupts = <2>;
                            };
                            phy3: ethernet-phy@3 {
                                    reg = <3>;
                                    interrupt-parent = <&switch_intc1>;
                                    interrupts = <3>;
                            };
                            phy4: ethernet-phy@4 {
                                    reg = <4>;
                                    interrupt-parent = <&switch_intc1>;
                                    interrupts = <12>;
                            };
                    };
            };
    };

  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    platform {
            switch {
                    compatible = "realtek,rtl8365mb";
                    mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
                    mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
                    reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;

                    switch_intc2: interrupt-controller {
                            interrupt-parent = <&gpio5>;
                            interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
                            interrupt-controller;
                            #address-cells = <0>;
                            #interrupt-cells = <1>;
                    };

                    ports {
                            #address-cells = <1>;
                            #size-cells = <0>;
                            port@0 {
                                    reg = <0>;
                                    label = "swp0";
                                    phy-handle = <&ethphy0>;
                            };
                            port@1 {
                                    reg = <1>;
                                    label = "swp1";
                                    phy-handle = <&ethphy1>;
                            };
                            port@2 {
                                    reg = <2>;
                                    label = "swp2";
                                    phy-handle = <&ethphy2>;
                            };
                            port@3 {
                                    reg = <3>;
                                    label = "swp3";
                                    phy-handle = <&ethphy3>;
                            };
                            port@6 {
                                    reg = <6>;
                                    ethernet = <&fec1>;
                                    phy-mode = "rgmii";
                                    tx-internal-delay-ps = <2000>;
                                    rx-internal-delay-ps = <2000>;

                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                            pause;
                                    };
                            };
                    };

                    mdio {
                            compatible = "realtek,smi-mdio";
                            #address-cells = <1>;
                            #size-cells = <0>;

                            ethphy0: ethernet-phy@0 {
                                    reg = <0>;
                                    interrupt-parent = <&switch_intc2>;
                                    interrupts = <0>;
                            };
                            ethphy1: ethernet-phy@1 {
                                    reg = <1>;
                                    interrupt-parent = <&switch_intc2>;
                                    interrupts = <1>;
                            };
                            ethphy2: ethernet-phy@2 {
                                    reg = <2>;
                                    interrupt-parent = <&switch_intc2>;
                                    interrupts = <2>;
                            };
                            ethphy3: ethernet-phy@3 {
                                    reg = <3>;
                                    interrupt-parent = <&switch_intc2>;
                                    interrupts = <3>;
                            };
                    };
            };
    };

  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    mdio {
            #address-cells = <1>;
            #size-cells = <0>;

            switch@29 {
                    compatible = "realtek,rtl8365mb";
                    reg = <29>;

                    reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;

                    switch_intc3: interrupt-controller {
                            interrupt-parent = <&gpio0>;
                            interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
                            interrupt-controller;
                            #address-cells = <0>;
                            #interrupt-cells = <1>;
                    };

                    ports {
                            #address-cells = <1>;
                            #size-cells = <0>;

                            port@0 {
                                    reg = <0>;
                                    label = "lan4";
                            };

                            port@1 {
                                    reg = <1>;
                                    label = "lan3";
                            };

                            port@2 {
                                    reg = <2>;
                                    label = "lan2";
                            };

                            port@3 {
                                    reg = <3>;
                                    label = "lan1";
                            };

                            port@4 {
                                    reg = <4>;
                                    label = "wan";
                            };

                            port@7 {
                                    reg = <7>;
                                    ethernet = <&ethernet>;
                                    phy-mode = "rgmii";
                                    tx-internal-delay-ps = <2000>;
                                    rx-internal-delay-ps = <0>;

                                    fixed-link {
                                            speed = <1000>;
                                            full-duplex;
                                    };
                            };
                    };
            };
      };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/N1 Advanced 5 ports ethernet switch

maintainers:
  - Clément Léger <clement.leger@bootlin.com>

description: |
  The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and
  handles 4 ports + 1 CPU management port.

allOf:
  - $ref: dsa.yaml#

properties:
  compatible:
    items:
      - enum:
          - renesas,r9a06g032-a5psw
      - const: renesas,rzn1-a5psw

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: Device Level Ring (DLR) interrupt
      - description: Switch interrupt
      - description: Parallel Redundancy Protocol (PRP) interrupt
      - description: Integrated HUB module interrupt
      - description: Receive Pattern Match interrupt

  interrupt-names:
    items:
      - const: dlr
      - const: switch
      - const: prp
      - const: hub
      - const: ptrn

  power-domains:
    maxItems: 1

  mdio:
    $ref: /schemas/net/mdio.yaml#
    unevaluatedProperties: false

  clocks:
    items:
      - description: AHB clock used for the switch register interface
      - description: Switch system clock

  clock-names:
    items:
      - const: hclk
      - const: clk

  ethernet-ports:
    type: object
    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    patternProperties:
      "^(ethernet-)?port@[0-4]$":
        type: object
        description: Ethernet switch ports

        properties:
          pcs-handle:
            maxItems: 1
            description:
              phandle pointing to a PCS sub-node compatible with
              renesas,rzn1-miic.yaml#

unevaluatedProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clock/r9a06g032-sysctrl.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    switch@44050000 {
        compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
        reg = <0x44050000 0x10000>;
        clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>;
        clock-names = "hclk", "clk";
        power-domains = <&sysctrl>;
        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "dlr", "switch", "prp", "hub", "ptrn";

        dsa,member = <0 0>;

        ethernet-ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                label = "lan0";
                phy-handle = <&switch0phy3>;
                pcs-handle = <&mii_conv4>;
            };

            port@1 {
                reg = <1>;
                label = "lan1";
                phy-handle = <&switch0phy1>;
                pcs-handle = <&mii_conv3>;
            };

            port@4 {
                reg = <4>;
                ethernet = <&gmac2>;
                phy-mode = "internal";

                fixed-link {
                  speed = <1000>;
                  full-duplex;
                };
            };
        };

        mdio {
            #address-cells = <1>;
            #size-cells = <0>;

            reset-gpios = <&gpio0a 2 GPIO_ACTIVE_HIGH>;
            reset-delay-us = <15>;
            clock-frequency = <2500000>;

            switch0phy1: ethernet-phy@1{
                reg = <1>;
            };

            switch0phy3: ethernet-phy@3{
                reg = <3>;
            };
        };
    };


code:
Vitesse VSC73xx Switches
========================

This defines device tree bindings for the Vitesse VSC73xx switch chips.
The Vitesse company has been acquired by Microsemi and Microsemi has
been acquired Microchip but retains this vendor branding.

The currently supported switch chips are:
Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch

This switch could have two different management interface.

If SPI interface is used, the device tree node is an SPI device so it must
reside inside a SPI bus device tree node, see spi/spi-bus.txt

When the chip is connected to a parallel memory bus and work in memory-mapped
I/O mode, a platform device is used to represent the vsc73xx. In this case it
must reside inside a platform bus device tree node.

Required properties:

- compatible: must be exactly one of:
	"vitesse,vsc7385"
	"vitesse,vsc7388"
	"vitesse,vsc7395"
	"vitesse,vsc7398"
- gpio-controller: indicates that this switch is also a GPIO controller,
  see gpio/gpio.txt
- #gpio-cells: this must be set to <2> and indicates that we are a twocell
  GPIO controller, see gpio/gpio.txt

Optional properties:

- reset-gpios: a handle to a GPIO line that can issue reset of the chip.
  It should be tagged as active low.

Required subnodes:

See net/dsa/dsa.txt for a list of additional required and optional properties
and subnodes of DSA switches.

Examples:

SPI:
switch@0 {
	compatible = "vitesse,vsc7395";
	reg = <0>;
	/* Specified for 2.5 MHz or below */
	spi-max-frequency = <2500000>;
	gpio-controller;
	#gpio-cells = <2>;

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			label = "lan1";
		};
		port@1 {
			reg = <1>;
			label = "lan2";
		};
		port@2 {
			reg = <2>;
			label = "lan3";
		};
		port@3 {
			reg = <3>;
			label = "lan4";
		};
		vsc: port@6 {
			reg = <6>;
			ethernet = <&gmac1>;
			phy-mode = "rgmii";
			fixed-link {
				speed = <1000>;
				full-duplex;
				pause;
			};
		};
	};
};

Platform:
switch@2,0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "vitesse,vsc7385";
	reg = <0x2 0x0 0x20000>;
	reset-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			label = "lan1";
		};
		port@1 {
			reg = <1>;
			label = "lan2";
		};
		port@2 {
			reg = <2>;
			label = "lan3";
		};
		port@3 {
			reg = <3>;
			label = "lan4";
		};
		vsc: port@6 {
			reg = <6>;
			ethernet = <&enet0>;
			phy-mode = "rgmii";
			fixed-link {
				speed = <1000>;
				full-duplex;
				pause;
			};
		};
	};

};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/engleder,tsnep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TSN endpoint Ethernet MAC binding

maintainers:
  - Gerhard Engleder <gerhard@engleder-embedded.com>

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    const: engleder,tsnep

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 8

  interrupt-names:
    minItems: 1
    items:
      - const: mac
      - const: txrx-1
      - const: txrx-2
      - const: txrx-3
      - const: txrx-4
      - const: txrx-5
      - const: txrx-6
      - const: txrx-7
    description:
      The main interrupt for basic MAC features and the first TX/RX queue pair
      is named "mac". "txrx-[1-7]" are the interrupts for additional TX/RX
      queue pairs.

  dma-coherent: true

  local-mac-address: true

  mac-address: true

  nvmem-cells: true

  nvmem-cell-names: true

  phy-connection-type:
    enum:
      - mii
      - gmii
      - rgmii
      - rgmii-id

  phy-mode: true

  phy-handle: true

  mdio:
    type: object
    $ref: "mdio.yaml#"
    description: optional node for embedded MDIO controller

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    axi {
        #address-cells = <2>;
        #size-cells = <2>;
        tsnep0: ethernet@a0000000 {
            compatible = "engleder,tsnep";
            reg = <0x0 0xa0000000 0x0 0x10000>;
            interrupts = <0 89 1>;
            interrupt-parent = <&gic>;
            local-mac-address = [00 00 00 00 00 00];
            phy-mode = "rgmii";
            phy-handle = <&phy0>;
            mdio {
                #address-cells = <1>;
                #size-cells = <0>;
                suppress-preamble;
                phy0: ethernet-phy@1 {
                    reg = <1>;
                    rxc-skew-ps = <1080>;
                };
            };
        };

        tsnep1: ethernet@a0010000 {
            compatible = "engleder,tsnep";
            reg = <0x0 0xa0010000 0x0 0x10000>;
            interrupts = <0 93 1>, <0 94 1>, <0 95 1>, <0 96 1>;
            interrupt-names = "mac", "txrx-1", "txrx-2", "txrx-3";
            interrupt-parent = <&gic>;
            local-mac-address = [00 00 00 00 00 00];
            phy-mode = "rgmii";
            phy-handle = <&phy1>;
            mdio {
                #address-cells = <1>;
                #size-cells = <0>;
                suppress-preamble;
                phy1: ethernet-phy@1 {
                    reg = <1>;
                    rxc-skew-ps = <1080>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ethernet Controller Generic Binding

maintainers:
  - David S. Miller <davem@davemloft.net>

properties:
  $nodename:
    pattern: "^ethernet(@.*)?$"

  label:
    $ref: /schemas/types.yaml#/definitions/string
    description: Human readable label on a port of a box.

  local-mac-address:
    description:
      Specifies the MAC address that was assigned to the network device.
    $ref: /schemas/types.yaml#/definitions/uint8-array
    minItems: 6
    maxItems: 6

  mac-address:
    description:
      Specifies the MAC address that was last used by the boot
      program; should be used in cases where the MAC address assigned
      to the device by the boot program is different from the
      local-mac-address property.
    $ref: /schemas/types.yaml#/definitions/uint8-array
    minItems: 6
    maxItems: 6

  max-frame-size:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Maximum transfer unit (IEEE defined MTU), rather than the
      maximum frame size (there\'s contradiction in the Devicetree
      Specification).

  max-speed:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Specifies maximum speed in Mbit/s supported by the device.

  nvmem-cells:
    maxItems: 1
    description:
      Reference to an nvmem node for the MAC address

  nvmem-cell-names:
    const: mac-address

  phy-connection-type:
    description:
      Specifies interface type between the Ethernet device and a physical
      layer (PHY) device.
    enum:
      # There is not a standard bus between the MAC and the PHY,
      # something proprietary is being used to embed the PHY in the
      # MAC.
      - internal
      - mii
      - gmii
      - sgmii
      - qsgmii
      - qusgmii
      - tbi
      - rev-mii
      - rmii
      - rev-rmii
      - moca

      # RX and TX delays are added by the MAC when required
      - rgmii

      # RGMII with internal RX and TX delays provided by the PHY,
      # the MAC should not add the RX or TX delays in this case
      - rgmii-id

      # RGMII with internal RX delay provided by the PHY, the MAC
      # should not add an RX delay in this case
      - rgmii-rxid

      # RGMII with internal TX delay provided by the PHY, the MAC
      # should not add an TX delay in this case
      - rgmii-txid
      - rtbi
      - smii
      - xgmii
      - trgmii
      - 1000base-x
      - 2500base-x
      - 5gbase-r
      - rxaui
      - xaui

      # 10GBASE-KR, XFI, SFI
      - 10gbase-kr
      - usxgmii
      - 10gbase-r
      - 25gbase-r

  phy-mode:
    $ref: "#/properties/phy-connection-type"

  pcs-handle:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      maxItems: 1
    description:
      Specifies a reference to a node representing a PCS PHY device on a MDIO
      bus to link with an external PHY (phy-handle) if exists.

  pcs-handle-names:
    description:
      The name of each PCS in pcs-handle.

  phy-handle:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Specifies a reference to a node representing a PHY device.

  phy:
    $ref: "#/properties/phy-handle"
    deprecated: true

  phy-device:
    $ref: "#/properties/phy-handle"
    deprecated: true

  rx-fifo-depth:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The size of the controller\'s receive fifo in bytes. This is used
      for components that can have configurable receive fifo sizes,
      and is useful for determining certain configuration settings
      such as flow control thresholds.

  sfp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Specifies a reference to a node representing a SFP cage.

  tx-fifo-depth:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The size of the controller\'s transmit fifo in bytes. This
      is used for components that can have configurable fifo sizes.

  managed:
    description:
      Specifies the PHY management type. If auto is set and fixed-link
      is not specified, it uses MDIO for management.
    $ref: /schemas/types.yaml#/definitions/string
    default: auto
    enum:
      - auto
      - in-band-status

  fixed-link:
    oneOf:
      - $ref: /schemas/types.yaml#/definitions/uint32-array
        deprecated: true
        items:
          - minimum: 0
            maximum: 31
            description:
              Emulated PHY ID, choose any but unique to the all
              specified fixed-links

          - enum: [0, 1]
            description:
              Duplex configuration. 0 for half duplex or 1 for
              full duplex

          - enum: [10, 100, 1000, 2500, 10000]
            description:
              Link speed in Mbits/sec.

          - enum: [0, 1]
            description:
              Pause configuration. 0 for no pause, 1 for pause

          - enum: [0, 1]
            description:
              Asymmetric pause configuration. 0 for no asymmetric
              pause, 1 for asymmetric pause
      - type: object
        additionalProperties: false
        properties:
          speed:
            description:
              Link speed.
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [10, 100, 1000, 2500, 10000]

          full-duplex:
            $ref: /schemas/types.yaml#/definitions/flag
            description:
              Indicates that full-duplex is used. When absent, half
              duplex is assumed.

          pause:
            $ref: /schemas/types.yaml#definitions/flag
            description:
              Indicates that pause should be enabled.

          asym-pause:
            $ref: /schemas/types.yaml#/definitions/flag
            description:
              Indicates that asym_pause should be enabled.

          link-gpios:
            maxItems: 1
            description:
              GPIO to determine if the link is up

        required:
          - speed

dependencies:
  pcs-handle-names: [pcs-handle]

allOf:
  - if:
      properties:
        phy-mode:
          contains:
            enum:
              - rgmii
              - rgmii-rxid
              - rgmii-txid
              - rgmii-id
    then:
      properties:
        rx-internal-delay-ps:
          description:
            RGMII Receive Clock Delay defined in pico seconds.This is used for
            controllers that have configurable RX internal delays. If this
            property is present then the MAC applies the RX delay.
        tx-internal-delay-ps:
          description:
            RGMII Transmit Clock Delay defined in pico seconds.This is used for
            controllers that have configurable TX internal delays. If this
            property is present then the MAC applies the TX delay.

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ethernet PHY Generic Binding

maintainers:
  - Andrew Lunn <andrew@lunn.ch>
  - Florian Fainelli <f.fainelli@gmail.com>
  - Heiner Kallweit <hkallweit1@gmail.com>

# The dt-schema tools will generate a select statement first by using
# the compatible, and second by using the node name if any. In our
# case, the node name is the one we want to match on, while the
# compatible is optional.
select:
  properties:
    $nodename:
      pattern: "^ethernet-phy(@[a-f0-9]+)?$"

  required:
    - $nodename

properties:
  $nodename:
    pattern: "^ethernet-phy(@[a-f0-9]+)?$"

  compatible:
    oneOf:
      - const: ethernet-phy-ieee802.3-c22
        description: PHYs that implement IEEE802.3 clause 22
      - const: ethernet-phy-ieee802.3-c45
        description: PHYs that implement IEEE802.3 clause 45
      - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
        description:
          If the PHY reports an incorrect ID (or none at all) then the
          compatible list may contain an entry with the correct PHY ID
          in the above form.
          The first group of digits is the 16 bit Phy Identifier 1
          register, this is the chip vendor OUI bits 3:18. The
          second group of digits is the Phy Identifier 2 register,
          this is the chip vendor OUI bits 19:24, followed by 10
          bits of a vendor specific ID.
      - items:
          - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
          - const: ethernet-phy-ieee802.3-c22
      - items:
          - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
          - const: ethernet-phy-ieee802.3-c45

  reg:
    minimum: 0
    maximum: 31
    description:
      The ID number for the PHY.

  interrupts:
    maxItems: 1

  max-speed:
    enum:
      - 10
      - 100
      - 1000
      - 2500
      - 5000
      - 10000
      - 20000
      - 25000
      - 40000
      - 50000
      - 56000
      - 100000
      - 200000
    description:
      Maximum PHY supported speed in Mbits / seconds.

  phy-10base-t1l-2.4vpp:
    description: |
      tristate, request/disable 2.4 Vpp operating mode. The values are:
      0: Disable 2.4 Vpp operating mode.
      1: Request 2.4 Vpp operating mode from link partner.
      Absence of this property will leave configuration to default values.
    $ref: "/schemas/types.yaml#/definitions/uint32"
    enum: [0, 1]

  broken-turn-around:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      If set, indicates the PHY device does not correctly release
      the turn around line low at end of the control phase of the
      MDIO transaction.

  enet-phy-lane-swap:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      If set, indicates the PHY will swap the TX/RX lanes to
      compensate for the board being designed with the lanes
      swapped.

  enet-phy-lane-no-swap:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      If set, indicates that PHY will disable swap of the
      TX/RX lanes. This property allows the PHY to work correcly after
      e.g. wrong bootstrap configuration caused by issues in PCB
      layout design.

  eee-broken-100tx:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Mark the corresponding energy efficient ethernet mode as
      broken and request the ethernet to stop advertising it.

  eee-broken-1000t:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Mark the corresponding energy efficient ethernet mode as
      broken and request the ethernet to stop advertising it.

  eee-broken-10gt:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Mark the corresponding energy efficient ethernet mode as
      broken and request the ethernet to stop advertising it.

  eee-broken-1000kx:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Mark the corresponding energy efficient ethernet mode as
      broken and request the ethernet to stop advertising it.

  eee-broken-10gkx4:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Mark the corresponding energy efficient ethernet mode as
      broken and request the ethernet to stop advertising it.

  eee-broken-10gkr:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Mark the corresponding energy efficient ethernet mode as
      broken and request the ethernet to stop advertising it.

  pses:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1
    description:
      Specifies a reference to a node representing a Power Sourcing Equipment.

  phy-is-integrated:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      If set, indicates that the PHY is integrated into the same
      physical package as the Ethernet MAC. If needed, muxers
      should be configured to ensure the integrated PHY is
      used. The absence of this property indicates the muxers
      should be configured so that the external PHY is used.

  resets:
    maxItems: 1

  reset-names:
    const: phy

  reset-gpios:
    maxItems: 1
    description:
      The GPIO phandle and specifier for the PHY reset signal.

  reset-assert-us:
    description:
      Delay after the reset was asserted in microseconds. If this
      property is missing the delay will be skipped.

  reset-deassert-us:
    description:
      Delay after the reset was deasserted in microseconds. If
      this property is missing the delay will be skipped.

  sfp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Specifies a reference to a node representing a SFP cage.

  rx-internal-delay-ps:
    description: |
      RGMII Receive PHY Clock Delay defined in pico seconds.  This is used for
      PHY's that have configurable RX internal delays.  If this property is
      present then the PHY applies the RX delay.

  tx-internal-delay-ps:
    description: |
      RGMII Transmit PHY Clock Delay defined in pico seconds.  This is used for
      PHY's that have configurable TX internal delays. If this property is
      present then the PHY applies the TX delay.

required:
  - reg

additionalProperties: true

examples:
  - |
    ethernet {
        #address-cells = <1>;
        #size-cells = <0>;

        ethernet-phy@0 {
            compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45";
            interrupt-parent = <&PIC>;
            interrupts = <35 1>;
            reg = <0>;

            resets = <&rst 8>;
            reset-names = "phy";
            reset-gpios = <&gpio1 4 1>;
            reset-assert-us = <1000>;
            reset-deassert-us = <2000>;
        };
    };


code: This file has moved to ethernet-controller.yaml.


code:
* EZchip NPS Management Ethernet port driver

Required properties:
- compatible: Should be "ezchip,nps-mgt-enet"
- reg: Address and length of the register set for the device
- interrupts: Should contain the ENET interrupt

Examples:

	ethernet@f0003000 {
		compatible = "ezchip,nps-mgt-enet";
		reg = <0xf0003000 0x44>;
		interrupts = <7>;
		mac-address = [ 00 11 22 33 44 55 ];
	};


code:
Faraday Ethernet Controller

Required properties:

- compatible : Must contain "faraday,ftmac", as well as one of
		the SoC specific identifiers:
		"andestech,atmac100"
		"moxa,moxart-mac"
- reg : Should contain register location and length
- interrupts : Should contain the mac interrupt number

Example:

	mac0: mac@90900000 {
		compatible = "moxa,moxart-mac";
		reg =	<0x90900000 0x100>;
		interrupts = <25 0>;
	};

	mac1: mac@92000000 {
		compatible = "moxa,moxart-mac";
		reg =	<0x92000000 0x100>;
		interrupts = <27 0>;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/fsl,fec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Fast Ethernet Controller (FEC)

maintainers:
  - Shawn Guo <shawnguo@kernel.org>
  - Wei Fang <wei.fang@nxp.com>
  - NXP Linux Team <linux-imx@nxp.com>

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx25-fec
          - fsl,imx27-fec
          - fsl,imx28-fec
          - fsl,imx6q-fec
          - fsl,mvf600-fec
          - fsl,s32v234-fec
      - items:
          - enum:
              - fsl,imx53-fec
              - fsl,imx6sl-fec
          - const: fsl,imx25-fec
      - items:
          - enum:
              - fsl,imx35-fec
              - fsl,imx51-fec
          - const: fsl,imx27-fec
      - items:
          - enum:
              - fsl,imx6ul-fec
              - fsl,imx6sx-fec
          - const: fsl,imx6q-fec
      - items:
          - enum:
              - fsl,imx7d-fec
          - const: fsl,imx6sx-fec
      - items:
          - const: fsl,imx8mq-fec
          - const: fsl,imx6sx-fec
      - items:
          - enum:
              - fsl,imx8mm-fec
              - fsl,imx8mn-fec
              - fsl,imx8mp-fec
          - const: fsl,imx8mq-fec
          - const: fsl,imx6sx-fec
      - items:
          - const: fsl,imx8qm-fec
          - const: fsl,imx6sx-fec
      - items:
          - enum:
              - fsl,imx8qxp-fec
          - const: fsl,imx8qm-fec
          - const: fsl,imx6sx-fec
      - items:
          - enum:
              - fsl,imx8ulp-fec
          - const: fsl,imx6ul-fec
          - const: fsl,imx6q-fec

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 4

  interrupt-names:
    oneOf:
      - items:
          - const: int0
      - items:
          - const: int0
          - const: pps
      - items:
          - const: int0
          - const: int1
          - const: int2
      - items:
          - const: int0
          - const: int1
          - const: int2
          - const: pps

  clocks:
    minItems: 2
    maxItems: 5
    description:
      The "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing.
      The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock.
      The "ptp"(option), for IEEE1588 timer clock that requires the clock.
      The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like
      RGMII TXC clock or RMII reference clock. It depends on board design,
      the clock is required if RGMII TXC and RMII reference clock source from
      SOC internal PLL.
      The "enet_out"(option), output clock for external device, like supply clock
      for PHY. The clock is required if PHY clock source from SOC.
      The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz.
      The clock is required if SoC RGMII enable clock delay.

  clock-names:
    minItems: 2
    maxItems: 5
    items:
      enum:
        - ipg
        - ahb
        - ptp
        - enet_clk_ref
        - enet_out
        - enet_2x_txclk

  phy-mode: true

  phy-handle: true

  fixed-link: true

  local-mac-address: true

  mac-address: true

  nvmem-cells: true

  nvmem-cell-names: true

  tx-internal-delay-ps:
    enum: [0, 2000]

  rx-internal-delay-ps:
    enum: [0, 2000]

  phy-supply:
    description:
      Regulator that powers the Ethernet PHY.

  fsl,num-tx-queues:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The property is valid for enet-avb IP, which supports hw multi queues.
      Should specify the tx queue number, otherwise set tx queue number to 1.
    enum: [1, 2, 3]

  fsl,num-rx-queues:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The property is valid for enet-avb IP, which supports hw multi queues.
      Should specify the rx queue number, otherwise set rx queue number to 1.
    enum: [1, 2, 3]

  fsl,magic-packet:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      If present, indicates that the hardware supports waking up via magic packet.

  fsl,err006687-workaround-present:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      If present indicates that the system has the hardware workaround for
      ERR006687 applied and does not need a software workaround.

  fsl,stop-mode:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to general purpose register node
          - description: the gpr register offset for ENET stop request
          - description: the gpr bit offset for ENET stop request
    description:
      Register bits of stop mode control, the format is <&gpr req_gpr req_bit>.

  mdio:
    $ref: mdio.yaml#
    unevaluatedProperties: false
    description:
      Specifies the mdio bus in the FEC, used as a container for phy nodes.

  # Deprecated optional properties:
  # To avoid these, create a phy node according to ethernet-phy.yaml in the same
  # directory, and point the FEC's "phy-handle" property to it. Then use
  # the phy's reset binding, again described by ethernet-phy.yaml.

  phy-reset-gpios:
    deprecated: true
    description:
      Should specify the gpio for phy reset.

  phy-reset-duration:
    $ref: /schemas/types.yaml#/definitions/uint32
    deprecated: true
    description:
      Reset duration in milliseconds.  Should present only if property
      "phy-reset-gpios" is available.  Missing the property will have the
      duration be 1 millisecond.  Numbers greater than 1000 are invalid
      and 1 millisecond will be used instead.

  phy-reset-active-high:
    type: boolean
    deprecated: true
    description:
      If present then the reset sequence using the GPIO specified in the
      "phy-reset-gpios" property is reversed (H=reset state, L=operation state).

  phy-reset-post-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    deprecated: true
    description:
      Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay
      milliseconds will be observed after the phy-reset-gpios has been toggled.
      Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms.
      Other delays are invalid.

required:
  - compatible
  - reg
  - interrupts

# FIXME: We had better set additionalProperties to false to avoid invalid or at
# least undocumented properties. However, PHY may have a deprecated option to
# place PHY OF properties in the MAC node, such as Micrel PHY, and we can find
# these boards which is based on i.MX6QDL.
unevaluatedProperties: false

examples:
  - |
    ethernet@83fec000 {
      compatible = "fsl,imx51-fec", "fsl,imx27-fec";
      reg = <0x83fec000 0x4000>;
      interrupts = <87>;
      phy-mode = "mii";
      phy-reset-gpios = <&gpio2 14 0>;
      phy-supply = <&reg_fec_supply>;
    };

    ethernet@83fed000 {
      compatible = "fsl,imx51-fec", "fsl,imx27-fec";
      reg = <0x83fed000 0x4000>;
      interrupts = <87>;
      phy-mode = "mii";
      phy-reset-gpios = <&gpio2 14 0>;
      phy-supply = <&reg_fec_supply>;
      phy-handle = <&ethphy0>;

      mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        ethphy0: ethernet-phy@0 {
          compatible = "ethernet-phy-ieee802.3-c22";
          reg = <0>;
        };
      };
    };