code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	aliases {
		ethernet0 = &emac;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		spi0 = &spi0;
		spi1 = &spi1;
	};

	xin24m: oscillator {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		#clock-cells = <0>;
		clock-output-names = "xin24m";
	};

	gpu: gpu@10090000 {
		compatible = "arm,mali-400";
		reg = <0x10090000 0x10000>;
		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
		clock-names = "bus", "core";
		assigned-clocks = <&cru ACLK_GPU>;
		assigned-clock-rates = <100000000>;
		resets = <&cru SRST_GPU>;
		status = "disabled";
	};

	vpu: video-codec@10104000 {
		compatible = "rockchip,rk3066-vpu";
		reg = <0x10104000 0x800>;
		interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vepu", "vdpu";
		clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
			 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
		clock-names = "aclk_vdpu", "hclk_vdpu",
			      "aclk_vepu", "hclk_vepu";
	};

	L2: cache-controller@10138000 {
		compatible = "arm,pl310-cache";
		reg = <0x10138000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	scu@1013c000 {
		compatible = "arm,cortex-a9-scu";
		reg = <0x1013c000 0x100>;
	};

	global_timer: global-timer@1013c200 {
		compatible = "arm,cortex-a9-global-timer";
		reg = <0x1013c200 0x20>;
		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&cru CORE_PERI>;
		status = "disabled";
		/* The clock source and the sched_clock provided by the arm_global_timer
		 * on Rockchip rk3066a/rk3188 are quite unstable because their rates
		 * depend on the CPU frequency.
		 * Keep the arm_global_timer disabled in order to have the
		 * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
		 */
	};

	local_timer: local-timer@1013c600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x1013c600 0x20>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&cru CORE_PERI>;
	};

	gic: interrupt-controller@1013d000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x1013d000 0x1000>,
		      <0x1013c100 0x0100>;
	};

	uart0: serial@10124000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x10124000 0x400>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <1>;
		clock-names = "baudclk", "apb_pclk";
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		status = "disabled";
	};

	uart1: serial@10126000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x10126000 0x400>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <1>;
		clock-names = "baudclk", "apb_pclk";
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		status = "disabled";
	};

	qos_gpu: qos@1012d000 {
		compatible = "rockchip,rk3066-qos", "syscon";
		reg = <0x1012d000 0x20>;
	};

	qos_vpu: qos@1012e000 {
		compatible = "rockchip,rk3066-qos", "syscon";
		reg = <0x1012e000 0x20>;
	};

	qos_lcdc0: qos@1012f000 {
		compatible = "rockchip,rk3066-qos", "syscon";
		reg = <0x1012f000 0x20>;
	};

	qos_cif0: qos@1012f080 {
		compatible = "rockchip,rk3066-qos", "syscon";
		reg = <0x1012f080 0x20>;
	};

	qos_ipp: qos@1012f100 {
		compatible = "rockchip,rk3066-qos", "syscon";
		reg = <0x1012f100 0x20>;
	};

	qos_lcdc1: qos@1012f180 {
		compatible = "rockchip,rk3066-qos", "syscon";
		reg = <0x1012f180 0x20>;
	};

	qos_cif1: qos@1012f200 {
		compatible = "rockchip,rk3066-qos", "syscon";
		reg = <0x1012f200 0x20>;
	};

	qos_rga: qos@1012f280 {
		compatible = "rockchip,rk3066-qos", "syscon";
		reg = <0x1012f280 0x20>;
	};

	usb_otg: usb@10180000 {
		compatible = "rockchip,rk3066-usb", "snps,dwc2";
		reg = <0x10180000 0x40000>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_OTG0>;
		clock-names = "otg";
		dr_mode = "otg";
		g-np-tx-fifo-size = <16>;
		g-rx-fifo-size = <275>;
		g-tx-fifo-size = <256 128 128 64 64 32>;
		phys = <&usbphy0>;
		phy-names = "usb2-phy";
		status = "disabled";
	};

	usb_host: usb@101c0000 {
		compatible = "snps,dwc2";
		reg = <0x101c0000 0x40000>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_OTG1>;
		clock-names = "otg";
		dr_mode = "host";
		phys = <&usbphy1>;
		phy-names = "usb2-phy";
		status = "disabled";
	};

	emac: ethernet@10204000 {
		compatible = "snps,arc-emac";
		reg = <0x10204000 0x3c>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

		rockchip,grf = <&grf>;

		clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
		clock-names = "hclk", "macref";
		max-speed = <100>;
		phy-mode = "rmii";

		status = "disabled";
	};

	mmc0: mmc@10214000 {
		compatible = "rockchip,rk2928-dw-mshc";
		reg = <0x10214000 0x1000>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
		clock-names = "biu", "ciu";
		dmas = <&dmac2 1>;
		dma-names = "rx-tx";
		fifo-depth = <256>;
		resets = <&cru SRST_SDMMC>;
		reset-names = "reset";
		status = "disabled";
	};

	mmc1: mmc@10218000 {
		compatible = "rockchip,rk2928-dw-mshc";
		reg = <0x10218000 0x1000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
		clock-names = "biu", "ciu";
		dmas = <&dmac2 3>;
		dma-names = "rx-tx";
		fifo-depth = <256>;
		resets = <&cru SRST_SDIO>;
		reset-names = "reset";
		status = "disabled";
	};

	emmc: mmc@1021c000 {
		compatible = "rockchip,rk2928-dw-mshc";
		reg = <0x1021c000 0x1000>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
		clock-names = "biu", "ciu";
		dmas = <&dmac2 4>;
		dma-names = "rx-tx";
		fifo-depth = <256>;
		resets = <&cru SRST_EMMC>;
		reset-names = "reset";
		status = "disabled";
	};

	nfc: nand-controller@10500000 {
		compatible = "rockchip,rk2928-nfc";
		reg = <0x10500000 0x4000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_NANDC0>;
		clock-names = "ahb";
		status = "disabled";
	};

	pmu: pmu@20004000 {
		compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
		reg = <0x20004000 0x100>;

		reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x40>;
			mode-normal = <BOOT_NORMAL>;
			mode-recovery = <BOOT_RECOVERY>;
			mode-bootloader = <BOOT_FASTBOOT>;
			mode-loader = <BOOT_BL_DOWNLOAD>;
		};
	};

	grf: grf@20008000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x20008000 0x200>;
	};

	dmac1_s: dma-controller@20018000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x20018000 0x4000>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		arm,pl330-broken-no-flushp;
		arm,pl330-periph-burst;
		clocks = <&cru ACLK_DMA1>;
		clock-names = "apb_pclk";
	};

	dmac1_ns: dma-controller@2001c000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x2001c000 0x4000>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		arm,pl330-broken-no-flushp;
		arm,pl330-periph-burst;
		clocks = <&cru ACLK_DMA1>;
		clock-names = "apb_pclk";
		status = "disabled";
	};

	i2c0: i2c@2002d000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x2002d000 0x1000>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clock-names = "i2c";
		clocks = <&cru PCLK_I2C0>;

		status = "disabled";
	};

	i2c1: i2c@2002f000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x2002f000 0x1000>;
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru PCLK_I2C1>;
		clock-names = "i2c";

		status = "disabled";
	};

	pwm0: pwm@20030000 {
		compatible = "rockchip,rk2928-pwm";
		reg = <0x20030000 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM01>;
		status = "disabled";
	};

	pwm1: pwm@20030010 {
		compatible = "rockchip,rk2928-pwm";
		reg = <0x20030010 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM01>;
		status = "disabled";
	};

	wdt: watchdog@2004c000 {
		compatible = "snps,dw-wdt";
		reg = <0x2004c000 0x100>;
		clocks = <&cru PCLK_WDT>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	pwm2: pwm@20050020 {
		compatible = "rockchip,rk2928-pwm";
		reg = <0x20050020 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM23>;
		status = "disabled";
	};

	pwm3: pwm@20050030 {
		compatible = "rockchip,rk2928-pwm";
		reg = <0x20050030 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM23>;
		status = "disabled";
	};

	i2c2: i2c@20056000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x20056000 0x1000>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru PCLK_I2C2>;
		clock-names = "i2c";

		status = "disabled";
	};

	i2c3: i2c@2005a000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x2005a000 0x1000>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru PCLK_I2C3>;
		clock-names = "i2c";

		status = "disabled";
	};

	i2c4: i2c@2005e000 {
		compatible = "rockchip,rk3066-i2c";
		reg = <0x2005e000 0x1000>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;

		rockchip,grf = <&grf>;

		clocks = <&cru PCLK_I2C4>;
		clock-names = "i2c";

		status = "disabled";
	};

	uart2: serial@20064000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x20064000 0x400>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <1>;
		clock-names = "baudclk", "apb_pclk";
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		status = "disabled";
	};

	uart3: serial@20068000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x20068000 0x400>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <1>;
		clock-names = "baudclk", "apb_pclk";
		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
		status = "disabled";
	};

	saradc: saradc@2006c000 {
		compatible = "rockchip,saradc";
		reg = <0x2006c000 0x100>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		#io-channel-cells = <1>;
		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
		clock-names = "saradc", "apb_pclk";
		resets = <&cru SRST_SARADC>;
		reset-names = "saradc-apb";
		status = "disabled";
	};

	spi0: spi@20070000 {
		compatible = "rockchip,rk3066-spi";
		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
		clock-names = "spiclk", "apb_pclk";
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x20070000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		dmas = <&dmac2 10>, <&dmac2 11>;
		dma-names = "tx", "rx";
		status = "disabled";
	};

	spi1: spi@20074000 {
		compatible = "rockchip,rk3066-spi";
		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
		clock-names = "spiclk", "apb_pclk";
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x20074000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		dmas = <&dmac2 12>, <&dmac2 13>;
		dma-names = "tx", "rx";
		status = "disabled";
	};

	dmac2: dma-controller@20078000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x20078000 0x4000>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		arm,pl330-broken-no-flushp;
		arm,pl330-periph-burst;
		clocks = <&cru ACLK_DMA2>;
		clock-names = "apb_pclk";
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
 * Copyright (c) 2019 Radxa Limited
 * Copyright (c) 2019 Amarula Solutions(India)
 */

#include <dt-bindings/pwm/pwm.h>

/ {
	clkin_gmac: external-gmac-clock {
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
		clock-output-names = "clkin_gmac";
		#clock-cells = <0>;
	};

	sdio_pwrseq: sdio-pwrseq {
		compatible = "mmc-pwrseq-simple";
		clocks = <&hym8563>;
		clock-names = "ext_clock";
		pinctrl-names = "default";
		pinctrl-0 = <&wifi_enable_h>;
	};

	vcc12v_dcin: vcc12v-dcin-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc12v_dcin";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
	};

	vcc5v0_sys: vcc5v0-sys-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&vcc12v_dcin>;
	};

	vbus_host: vbus-host {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&usb1_en_oc>;
		regulator-name = "vbus_host"; /* HOST-5V */
		regulator-always-on;
		vin-supply = <&vcc5v0_sys>;
	};

	vbus_typec: vbus-typec {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&usb0_en_oc>;
		regulator-name = "vbus_typec";
		regulator-always-on;
		vin-supply = <&vcc5v0_sys>;
	};
};

&gmac {
	assigned-clock-parents = <&clkin_gmac>;
	clock_in_out = "input";
	phy-mode = "rgmii";
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 50000>;
	tx_delay = <0x28>;
	rx_delay = <0x11>;
	status = "okay";
};

&hdmi {
	status = "okay";
};

&pwm0 {
	status = "okay";
};

&pwm2 {
	status = "okay";
};

&sdio0 {
	bus-width = <4>;
	cap-sd-highspeed;
	cap-sdio-irq;
	keep-power-in-suspend;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
	sd-uhs-sdr104;
	status = "okay";
};

&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	disable-wp;
	vqmmc-supply = <&vccio_sd>;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
	status = "okay";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer &uart0_cts>;
	status = "okay";
};

&uart2 {
	status = "okay";
};

&vopb {
	status = "okay";
};

&vopb_mmu {
	status = "okay";
};

&vopl {
	status = "okay";
};

&vopl_mmu {
	status = "okay";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
 * Copyright (c) 2019 Andreas Färber
 */

/dts-v1/;

#include "rtd1195.dtsi"

/ {
	compatible = "realtek,horseradish", "realtek,rtd1195";
	model = "Realtek Horseradish EVB";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@a800 {
		device_type = "memory";
		reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */
		      <0x18070000 0x00090000>, /* r-bus to NOR flash */
		      <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
 * Copyright (c) 2017-2019 Andreas Färber
 */

/dts-v1/;

#include "rtd1195.dtsi"

/ {
	compatible = "mele,x1000", "realtek,rtd1195";
	model = "MeLE X1000";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@a800 {
		device_type = "memory";
		reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */
		      <0x18070000 0x00090000>, /* r-bus to NOR flash */
		      <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
/*
 * Copyright (c) 2017-2019 Andreas Färber
 */

/memreserve/ 0x00000000 0x0000a800; /* boot code */
/memreserve/ 0x0000a800 0x000f5800;
/memreserve/ 0x17fff000 0x00001000;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/realtek,rtd1195.h>

/ {
	compatible = "realtek,rtd1195";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			clock-frequency = <1000000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			clock-frequency = <1000000000>;
		};
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		rpc_comm: rpc@b000 {
			reg = <0x0000b000 0x1000>;
		};

		audio@1b00000 {
			reg = <0x01b00000 0x400000>;
		};

		rpc_ringbuf: rpc@1ffe000 {
			reg = <0x01ffe000 0x4000>;
		};

		secure@10000000 {
			reg = <0x10000000 0x100000>;
			no-map;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <27000000>;
	};

	osc27M: osc {
		compatible = "fixed-clock";
		clock-frequency = <27000000>;
		#clock-cells = <0>;
		clock-output-names = "osc27M";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00000000 0x00000000 0x0000a800>,
			 <0x18000000 0x18000000 0x00070000>,
			 <0x18100000 0x18100000 0x01000000>,
			 <0x80000000 0x80000000 0x80000000>;

		rbus: bus@18000000 {
			compatible = "simple-bus";
			reg = <0x18000000 0x70000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x18000000 0x70000>;

			crt: syscon@0 {
				compatible = "syscon", "simple-mfd";
				reg = <0x0 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x0 0x1000>;
			};

			iso: syscon@7000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x7000 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x7000 0x1000>;
			};

			sb2: syscon@1a000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x1a000 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x1a000 0x1000>;
			};

			misc: syscon@1b000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x1b000 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x1b000 0x1000>;
			};

			scpu_wrapper: syscon@1d000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x1d000 0x1000>;
				reg-io-width = <4>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x1d000 0x1000>;
			};
		};

		gic: interrupt-controller@ff011000 {
			compatible = "arm,cortex-a7-gic";
			reg = <0xff011000 0x1000>,
			      <0xff012000 0x2000>,
			      <0xff014000 0x2000>,
			      <0xff016000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};
};

&crt {
	reset1: reset-controller@0 {
		compatible = "snps,dw-low-reset";
		reg = <0x0 0x4>;
		#reset-cells = <1>;
	};

	reset2: reset-controller@4 {
		compatible = "snps,dw-low-reset";
		reg = <0x4 0x4>;
		#reset-cells = <1>;
	};

	reset3: reset-controller@8 {
		compatible = "snps,dw-low-reset";
		reg = <0x8 0x4>;
		#reset-cells = <1>;
	};
};

&iso {
	iso_reset: reset-controller@88 {
		compatible = "snps,dw-low-reset";
		reg = <0x88 0x4>;
		#reset-cells = <1>;
	};

	wdt: watchdog@680 {
		compatible = "realtek,rtd1295-watchdog";
		reg = <0x680 0x100>;
		clocks = <&osc27M>;
	};

	uart0: serial@800 {
		compatible = "snps,dw-apb-uart";
		reg = <0x800 0x400>;
		reg-shift = <2>;
		reg-io-width = <4>;
		resets = <&iso_reset RTD1195_ISO_RSTN_UR0>;
		clock-frequency = <27000000>;
		status = "disabled";
	};
};

&misc {
	uart1: serial@200 {
		compatible = "snps,dw-apb-uart";
		reg = <0x200 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		resets = <&reset2 RTD1195_RSTN_UR1>;
		clock-frequency = <27000000>;
		status = "disabled";
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*
 * Copyright (C) 2018 O.S. Systems Software LTDA.
 */

/dts-v1/;

#include "rv1108.dtsi"

/ {
	model = "Elgin RV1108 R1 board";
	compatible = "elgin,rv1108-r1", "rockchip,rv1108";

	aliases {
		mmc0 = &emmc;
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x08000000>;
	};

	chosen {
		stdout-path = "serial2:1500000n8";
	};

	vcc_sys: vsys-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vsys";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
	};
};

&cpu0 {
	cpu-supply = <&vdd_core>;
};

&emmc {
	bus-width = <8>;
	cap-mmc-highspeed;
	no-sd;
	no-sdio;
	non-removable;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
	status = "okay";
};

&gmac {
	clock_in_out = "output";
	pinctrl-names = "default";
	pinctrl-0 = <&rmii_pins>;
	snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	status = "okay";
};

&i2c0 {
	clock-frequency = <400000>;
	i2c-scl-rising-time-ns = <275>;
	i2c-scl-falling-time-ns = <16>;
	status = "okay";

	rk805: pmic@18 {
		compatible = "rockchip,rk805";
		reg = <0x18>;
		interrupt-parent = <&gpio0>;
		interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
		rockchip,system-power-controller;
		#clock-cells = <0>;

		vcc1-supply = <&vcc_sys>;
		vcc2-supply = <&vcc_sys>;
		vcc3-supply = <&vcc_sys>;
		vcc4-supply = <&vcc_sys>;
		vcc5-supply = <&vdd_buck2>;
		vcc6-supply = <&vdd_buck2>;

		regulators {
			vdd_core: DCDC_REG1 {
				regulator-name = "vdd_core";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1500000>;
				regulator-always-on;
				regulator-boot-on;
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <900000>;
				};
			};

			vdd_buck2: DCDC_REG2 {
				regulator-name = "vdd_buck2";
				regulator-min-microvolt = <2200000>;
				regulator-max-microvolt = <2200000>;
				regulator-always-on;
				regulator-boot-on;
				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vcc_ddr: DCDC_REG3 {
				regulator-name = "vcc_ddr";
				regulator-always-on;
				regulator-boot-on;
				regulator-state-mem {
					regulator-on-in-suspend;
				};
			};

			vcc_io: DCDC_REG4 {
				regulator-name = "vcc_io";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				regulator-boot-on;
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <3300000>;
				};
			};

			vdd_10: LDO_REG1 {
				regulator-name = "vdd_10";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-always-on;
				regulator-boot-on;
				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vcc_18: LDO_REG2 {
				regulator-name = "vcc_18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdd10_pmu: LDO_REG3 {
				regulator-name = "vdd10_pmu";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-always-on;
				regulator-boot-on;
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1000000>;
				};
			};
		};
	};
};

&spi {
	pinctrl-names = "default";
	pinctrl-0 = <&spim1_clk &spim1_cs0 &spim1_tx &spim1_rx>;
	status = "okay";

	dh2228fv: dac@0 {
		compatible = "rohm,dh2228fv";
		reg = <0>;
		spi-max-frequency = <24000000>;
		spi-cpha;
		spi-cpol;
	};
};

&u2phy {
	status = "okay";

	u2phy_host: host-port {
		status = "okay";
	};

	u2phy_otg: otg-port {
		status = "okay";
	};
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
	status = "okay";
};

&uart2 {
	status = "okay";
};

&usb_host_ehci {
	status = "okay";
};

&usb_host_ohci {
	status = "okay";
};

&usb_otg {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/rv1108-cru.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/thermal/thermal.h>
/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "rockchip,rv1108";

	interrupt-parent = <&gic>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@f00 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf00>;
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <75>;
			operating-points-v2 = <&cpu_opp_table>;
		};
	};

	cpu_opp_table: opp-table-0 {
		compatible = "operating-points-v2";

		opp-408000000 {
			opp-hz = /bits/ 64 <408000000>;
			opp-microvolt = <975000>;
			clock-latency-ns = <40000>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <975000>;
			clock-latency-ns = <40000>;
		};
		opp-816000000 {
			opp-hz = /bits/ 64 <816000000>;
			opp-microvolt = <1025000>;
			clock-latency-ns = <40000>;
		};
		opp-1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <1150000>;
			clock-latency-ns = <40000>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
		arm,cpu-registers-not-fw-configured;
		clock-frequency = <24000000>;
	};

	xin24m: oscillator {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	bus_intmem: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x2000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x2000>;
	};

	uart2: serial@10210000 {
		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
		reg = <0x10210000 0x100>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&pdma 6>, <&pdma 7>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart2m0_xfer>;
		status = "disabled";
	};

	uart1: serial@10220000 {
		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
		reg = <0x10220000 0x100>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&pdma 4>, <&pdma 5>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart1_xfer>;
		status = "disabled";
	};

	uart0: serial@10230000 {
		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
		reg = <0x10230000 0x100>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		dmas = <&pdma 2>, <&pdma 3>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
		status = "disabled";
	};

	i2c1: i2c@10240000 {
		compatible = "rockchip,rv1108-i2c";
		reg = <0x10240000 0x1000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
		clock-names = "i2c", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_xfer>;
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	i2c2: i2c@10250000 {
		compatible = "rockchip,rv1108-i2c";
		reg = <0x10250000 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
		clock-names = "i2c", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2m1_xfer>;
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	i2c3: i2c@10260000 {
		compatible = "rockchip,rv1108-i2c";
		reg = <0x10260000 0x1000>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
		clock-names = "i2c", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c3_xfer>;
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	spi: spi@10270000 {
		compatible = "rockchip,rv1108-spi";
		reg = <0x10270000 0x1000>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&pdma 8>, <&pdma 9>;
		dma-names = "tx", "rx";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	pwm4: pwm@10280000 {
		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
		reg = <0x10280000 0x10>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
		clock-names = "pwm", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm4_pin>;
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm5: pwm@10280010 {
		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
		reg = <0x10280010 0x10>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
		clock-names = "pwm", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm5_pin>;
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm6: pwm@10280020 {
		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
		reg = <0x10280020 0x10>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
		clock-names = "pwm", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm6_pin>;
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm7: pwm@10280030 {
		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
		reg = <0x10280030 0x10>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
		clock-names = "pwm", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm7_pin>;
		#pwm-cells = <3>;
		status = "disabled";
	};

	pdma: dma-controller@102a0000 {
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x102a0000 0x4000>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		arm,pl330-broken-no-flushp;
		arm,pl330-periph-burst;
		clocks = <&cru ACLK_DMAC>;
		clock-names = "apb_pclk";
	};

	grf: syscon@10300000 {
		compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
		reg = <0x10300000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		io_domains: io-domains {
			compatible = "rockchip,rv1108-io-voltage-domain";
			status = "disabled";
		};

		u2phy: usb2phy@100 {
			compatible = "rockchip,rv1108-usb2phy";
			reg = <0x100 0x0c>;
			clocks = <&cru SCLK_USBPHY>;
			clock-names = "phyclk";
			#clock-cells = <0>;
			clock-output-names = "usbphy";
			rockchip,usbgrf = <&usbgrf>;
			status = "disabled";

			u2phy_otg: otg-port {
				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "otg-mux";
				#phy-cells = <0>;
				status = "disabled";
			};

			u2phy_host: host-port {
				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "linestate";
				#phy-cells = <0>;
				status = "disabled";
			};
		};
	};

	timer: timer@10350000 {
		compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
		reg = <0x10350000 0x20>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_TIMER>, <&xin24m>;
		clock-names = "pclk", "timer";
	};

	watchdog: watchdog@10360000 {
		compatible = "rockchip,rv1108-wdt", "snps,dw-wdt";
		reg = <0x10360000 0x100>;
		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_WDT>;
		status = "disabled";
	};

	thermal-zones {
		soc_thermal: soc-thermal {
			polling-delay-passive = <20>;
			polling-delay = <1000>;
			sustainable-power = <50>;
			thermal-sensors = <&tsadc 0>;

			trips {
				threshold: trip-point0 {
					temperature = <70000>;
					hysteresis = <2000>;
					type = "passive";
				};
				target: trip-point1 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};
				soc_crit: soc-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&target>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
					contribution = <4096>;
				};
			};
		};
	};

	tsadc: tsadc@10370000 {
		compatible = "rockchip,rv1108-tsadc";
		reg = <0x10370000 0x100>;
		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
		assigned-clocks = <&cru SCLK_TSADC>;
		assigned-clock-rates = <750000>;
		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
		clock-names = "tsadc", "apb_pclk";
		pinctrl-names = "init", "default", "sleep";
		pinctrl-0 = <&otp_pin>;
		pinctrl-1 = <&otp_out>;
		pinctrl-2 = <&otp_pin>;
		resets = <&cru SRST_TSADC>;
		reset-names = "tsadc-apb";
		rockchip,hw-tshut-temp = <120000>;
		#thermal-sensor-cells = <1>;
		status = "disabled";
	};

	adc: adc@1038c000 {
		compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
		reg = <0x1038c000 0x100>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		#io-channel-cells = <1>;
		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
		clock-names = "saradc", "apb_pclk";
		status = "disabled";
	};

	i2c0: i2c@20000000 {
		compatible = "rockchip,rv1108-i2c";
		reg = <0x20000000 0x1000>;
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
		clock-names = "i2c", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	pwm0: pwm@20040000 {
		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
		reg = <0x20040000 0x10>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
		clock-names = "pwm", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm0_pin>;
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm1: pwm@20040010 {
		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
		reg = <0x20040010 0x10>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
		clock-names = "pwm", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm1_pin>;
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm2: pwm@20040020 {
		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
		reg = <0x20040020 0x10>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
		clock-names = "pwm", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm2_pin>;
		#pwm-cells = <3>;
		status = "disabled";
	};

	pwm3: pwm@20040030 {
		compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
		reg = <0x20040030 0x10>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
		clock-names = "pwm", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm3_pin>;
		#pwm-cells = <3>;
		status = "disabled";
	};

	pmugrf: syscon@20060000 {
		compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd";
		reg = <0x20060000 0x1000>;

		pmu_io_domains: io-domains {
			compatible = "rockchip,rv1108-pmu-io-voltage-domain";
			status = "disabled";
		};
	};

	usbgrf: syscon@202a0000 {
		compatible = "rockchip,rv1108-usbgrf", "syscon";
		reg = <0x202a0000 0x1000>;
	};

	cru: clock-controller@20200000 {
		compatible = "rockchip,rv1108-cru";
		reg = <0x20200000 0x1000>;
		clocks = <&xin24m>;
		clock-names = "xin24m";
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	nfc: nand-controller@30100000 {
		compatible = "rockchip,rv1108-nfc";
		reg = <0x30100000  0x1000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
		clock-names = "ahb", "nfc";
		assigned-clocks = <&cru SCLK_NANDC>;
		assigned-clock-rates = <150000000>;
		status = "disabled";
	};

	emmc: mmc@30110000 {
		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x30110000 0x4000>;
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		max-frequency = <150000000>;
		status = "disabled";
	};

	sdio: mmc@30120000 {
		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x30120000 0x4000>;
		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		max-frequency = <150000000>;
		status = "disabled";
	};

	sdmmc: mmc@30130000 {
		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x30130000 0x4000>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		max-frequency = <100000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
		status = "disabled";
	};

	usb_host_ehci: usb@30140000 {
		compatible = "generic-ehci";
		reg = <0x30140000 0x20000>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_HOST0>, <&u2phy>;
		phys = <&u2phy_host>;
		phy-names = "usb";
		status = "disabled";
	};

	usb_host_ohci: usb@30160000 {
		compatible = "generic-ohci";
		reg = <0x30160000 0x20000>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_HOST0>, <&u2phy>;
		phys = <&u2phy_host>;
		phy-names = "usb";
		status = "disabled";
	};

	usb_otg: usb@30180000 {
		compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
			     "snps,dwc2";
		reg = <0x30180000 0x40000>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_OTG>;
		clock-names = "otg";
		dr_mode = "otg";
		g-np-tx-fifo-size = <16>;
		g-rx-fifo-size = <280>;
		g-tx-fifo-size = <256 128 128 64 32 16>;
		phys = <&u2phy_otg>;
		phy-names = "usb2-phy";
		status = "disabled";
	};

	sfc: spi@301c0000 {
		compatible = "rockchip,sfc";
		reg = <0x301c0000 0x4000>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
		clock-names = "clk_sfc", "hclk_sfc";
		pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
		pinctrl-names = "default";
		status = "disabled";
	};

	gmac: ethernet@30200000 {
		compatible = "rockchip,rv1108-gmac";
		reg = <0x30200000 0x10000>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq", "eth_wake_irq";
		clocks = <&cru SCLK_MAC>,
			<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
			<&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
			<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
		clock-names = "stmmaceth",
			"mac_clk_rx", "mac_clk_tx",
			"clk_mac_ref", "clk_mac_refout",
			"aclk_mac", "pclk_mac";
		/* rv1108 only supports an rmii interface */
		phy-mode = "rmii";
		pinctrl-names = "default";
		pinctrl-0 = <&rmii_pins>;
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	gic: interrupt-controller@32010000 {
		compatible = "arm,gic-400";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <0>;

		reg = <0x32011000 0x1000>,
		      <0x32012000 0x2000>,
		      <0x32014000 0x2000>,
		      <0x32016000 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rv1108-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmugrf>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio@20030000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20030000 0x100>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0_PMU>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@10310000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x10310000 0x100>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@10320000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x10320000 0x100>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@10330000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x10330000 0x100>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_up: pcfg-pull-up {
			bias-pull-up;
		};

		pcfg_pull_down: pcfg-pull-down {
			bias-pull-down;
		};

		pcfg_pull_none: pcfg-pull-none {
			bias-disable;
		};

		pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
			drive-strength = <8>;
		};

		pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
			drive-strength = <12>;
		};

		pcfg_pull_none_smt: pcfg-pull-none-smt {
			bias-disable;
			input-schmitt-enable;
		};

		pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
			bias-pull-up;
			drive-strength = <8>;
		};

		pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
			drive-strength = <4>;
		};

		pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
			bias-pull-up;
			drive-strength = <4>;
		};

		pcfg_output_high: pcfg-output-high {
			output-high;
		};

		pcfg_output_low: pcfg-output-low {
			output-low;
		};

		pcfg_input_high: pcfg-input-high {
			bias-pull-up;
			input-enable;
		};

		emmc {
			emmc_bus8: emmc-bus8 {
				rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
						<2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
						<2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
						<2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
						<2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
						<2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
						<2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
						<2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
			};

			emmc_clk: emmc-clk {
				rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
			};
		};

		sfc {
			sfc_bus4: sfc-bus4 {
				rockchip,pins =
					<2 RK_PA0 3 &pcfg_pull_none>,
					<2 RK_PA1 3 &pcfg_pull_none>,
					<2 RK_PA2 3 &pcfg_pull_none>,
					<2 RK_PA3 3 &pcfg_pull_none>;
			};

			sfc_bus2: sfc-bus2 {
				rockchip,pins =
					<2 RK_PA0 3 &pcfg_pull_none>,
					<2 RK_PA1 3 &pcfg_pull_none>;
			};

			sfc_cs0: sfc-cs0 {
				rockchip,pins =
					<2 RK_PB4 3 &pcfg_pull_none>;
			};

			sfc_clk: sfc-clk {
				rockchip,pins =
					<2 RK_PB7 2 &pcfg_pull_none>;
			};
		};

		gmac {
			rmii_pins: rmii-pins {
				rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
						<1 RK_PC3 2 &pcfg_pull_none>,
						<1 RK_PC4 2 &pcfg_pull_none>,
						<1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
						<1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
						<1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
						<1 RK_PB5 3 &pcfg_pull_none>,
						<1 RK_PB6 3 &pcfg_pull_none>,
						<1 RK_PB7 3 &pcfg_pull_none>,
						<1 RK_PC2 3 &pcfg_pull_none>;
			};
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
						<0 RK_PB2 1 &pcfg_pull_none_smt>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
						<2 RK_PD4 1 &pcfg_pull_up>;
			};
		};

		i2c2m1 {
			i2c2m1_xfer: i2c2m1-xfer {
				rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
						<0 RK_PC6 3 &pcfg_pull_none>;
			};

			i2c2m1_pins: i2c2m1-pins {
				rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
						<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
			};
		};

		i2c2m05v {
			i2c2m05v_xfer: i2c2m05v-xfer {
				rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
						<1 RK_PD4 2 &pcfg_pull_none>;
			};

			i2c2m05v_pins: i2c2m05v-pins {
				rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
						<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
						<0 RK_PC4 2 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_pin: pwm0-pin {
				rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_pin: pwm1-pin {
				rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_pin: pwm2-pin {
				rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_pin: pwm3-pin {
				rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
			};
		};

		pwm4 {
			pwm4_pin: pwm4-pin {
				rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
			};
		};

		pwm5 {
			pwm5_pin: pwm5-pin {
				rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
			};
		};

		pwm6 {
			pwm6_pin: pwm6-pin {
				rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
			};
		};

		pwm7 {
			pwm7_pin: pwm7-pin {
				rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
			};
		};

		sdmmc {
			sdmmc_clk: sdmmc-clk {
				rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
			};

			sdmmc_cmd: sdmmc-cmd {
				rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
			};

			sdmmc_cd: sdmmc-cd {
				rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
			};

			sdmmc_bus1: sdmmc-bus1 {
				rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
			};

			sdmmc_bus4: sdmmc-bus4 {
				rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
						<3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
						<3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
						<3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
			};
		};

		spim0 {
			spim0_clk: spim0-clk {
				rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
			};

			spim0_cs0: spim0-cs0 {
				rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
			};

			spim0_tx: spim0-tx {
				rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
			};

			spim0_rx: spim0-rx {
				rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
			};
		};

		spim1 {
			spim1_clk: spim1-clk {
				rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
			};

			spim1_cs0: spim1-cs0 {
				rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
			};

			spim1_rx: spim1-rx {
				rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
			};

			spim1_tx: spim1-tx {
				rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
			};
		};

		tsadc {
			otp_out: otp-out {
				rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
			};

			otp_pin: otp-pin {
				rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
						<3 RK_PA5 1 &pcfg_pull_none>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
			};

			uart0_rts_pin: uart0-rts-pin {
				rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
						<1 RK_PD2 1 &pcfg_pull_none>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
			};
		};

		uart2m0 {
			uart2m0_xfer: uart2m0-xfer {
				rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
						<2 RK_PD1 1 &pcfg_pull_none>;
			};
		};

		uart2m1 {
			uart2m1_xfer: uart2m1-xfer {
				rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
						<3 RK_PC2 2 &pcfg_pull_none>;
			};
		};

		uart2_5v {
			uart2_5v_cts: uart2_5v-cts {
				rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
			};

			uart2_5v_rts: uart2_5v-rts {
				rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;
			};
		};
	};
};


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Samsung S3C2410 DTS pinctrl constants
 *
 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 * Copyright (c) 2022 Linaro Ltd
 * Author: Krzysztof Kozlowski <krzk@kernel.org>
 */

#ifndef __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__
#define __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__

#define S3C2410_PIN_FUNC_INPUT		0
#define S3C2410_PIN_FUNC_OUTPUT		1
#define S3C2410_PIN_FUNC_2		2
#define S3C2410_PIN_FUNC_3		3

#endif /* __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ */


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung S3C2416 pinctrl settings
 *
 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
 */

#include "s3c2410-pinctrl.h"

&pinctrl_0 {
	/*
	 * Pin banks
	 */

	gpa: gpa-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpb: gpb-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpc: gpc-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpd: gpd-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpe: gpe-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpf: gpf-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpg: gpg-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gph: gph-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpj: gpj-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpk: gpk-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpl: gpl-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpm: gpm-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	/*
	 * Pin groups
	 */

	uart0_data: uart0-data-pins {
		samsung,pins = "gph-0", "gph-1";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	uart0_fctl: uart0-fctl-pins {
		samsung,pins = "gph-8", "gph-9";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	uart1_data: uart1-data-pins {
		samsung,pins = "gph-2", "gph-3";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	uart1_fctl: uart1-fctl-pins {
		samsung,pins = "gph-10", "gph-11";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	uart2_data: uart2-data-pins {
		samsung,pins = "gph-4", "gph-5";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	uart2_fctl: uart2-fctl-pins {
		samsung,pins = "gph-6", "gph-7";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	uart3_data: uart3-data-pins {
		samsung,pins = "gph-6", "gph-7";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	extuart_clk: extuart-clk-pins {
		samsung,pins = "gph-12";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	i2c0_bus: i2c0-bus-pins {
		samsung,pins = "gpe-14", "gpe-15";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	spi0_bus: spi0-bus-pins {
		samsung,pins = "gpe-11", "gpe-12", "gpe-13";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	sd0_clk: sd0-clk-pins {
		samsung,pins = "gpe-5";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	sd0_cmd: sd0-cmd-pins {
		samsung,pins = "gpe-6";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	sd0_bus1: sd0-bus1-pins {
		samsung,pins = "gpe-7";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	sd0_bus4: sd0-bus4-pins {
		samsung,pins = "gpe-8", "gpe-9", "gpe-10";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	sd1_cmd: sd1-cmd-pins {
		samsung,pins = "gpl-8";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	sd1_clk: sd1-clk-pins {
		samsung,pins = "gpl-9";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	sd1_bus1: sd1-bus1-pins {
		samsung,pins = "gpl-0";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};

	sd1_bus4: sd1-bus4-pins {
		samsung,pins = "gpl-1", "gpl-2", "gpl-3";
		samsung,pin-function = <S3C2410_PIN_FUNC_2>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung SMDK2416 board device tree source
 *
 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
 */

/dts-v1/;
#include "s3c2416.dtsi"

/ {
	model = "SMDK2416";
	compatible = "samsung,smdk2416", "samsung,s3c2416";

	memory@30000000 {
		device_type = "memory";
		reg =  <0x30000000 0x4000000>;
	};

	xti: clock-0 {
		compatible = "fixed-clock";
		clock-frequency = <12000000>;
		clock-output-names = "xti";
		#clock-cells = <0>;
	};
};

&rtc {
	status = "okay";
};

&sdhci_0 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd1_clk>, <&sd1_cmd>,
			<&sd1_bus1>, <&sd1_bus4>;
	bus-width = <4>;
	broken-cd;
	status = "okay";
};

&sdhci_1 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk>, <&sd0_cmd>,
			<&sd0_bus1>, <&sd0_bus4>;
	bus-width = <4>;
	cd-gpios = <&gpf 1 0>;
	cd-inverted;
	status = "okay";
};

&uart_0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
};

&uart_1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_data>, <&uart1_fctl>;
};

&uart_2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_data>;
};

&uart_3 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_data>;
};

&watchdog {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's S3C2416 SoC device tree source
 *
 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
 */

#include <dt-bindings/clock/s3c2443.h>
#include "s3c24xx.dtsi"
#include "s3c2416-pinctrl.dtsi"

/ {
	model = "Samsung S3C2416 SoC";
	compatible = "samsung,s3c2416";

	aliases {
		serial3 = &uart_3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
			reg = <0x0>;
		};
	};

	clocks: clock-controller@4c000000 {
		compatible = "samsung,s3c2416-clock";
		reg = <0x4c000000 0x40>;
		#clock-cells = <1>;
	};

	uart_3: serial@5000c000 {
		compatible = "samsung,s3c2440-uart";
		reg = <0x5000C000 0x4000>;
		interrupts = <1 18 24 4>, <1 18 25 4>;
		clock-names = "uart", "clk_uart_baud2",
				"clk_uart_baud3";
		clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
				<&clocks SCLK_UART>;
		status = "disabled";
	};

	sdhci_1: mmc@4ac00000 {
		compatible = "samsung,s3c6410-sdhci";
		reg = <0x4AC00000 0x100>;
		interrupts = <0 0 21 3>;
		clock-names = "hsmmc", "mmc_busclk.0",
				"mmc_busclk.2";
		clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
				<&clocks MUX_HSMMC0>;
		status = "disabled";
	};

	sdhci_0: mmc@4a800000 {
		compatible = "samsung,s3c6410-sdhci";
		reg = <0x4A800000 0x100>;
		interrupts = <0 0 20 3>;
		clock-names = "hsmmc", "mmc_busclk.0",
				"mmc_busclk.2";
		clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
				<&clocks MUX_HSMMC1>;
		status = "disabled";
	};
};

&i2c {
	compatible = "samsung,s3c2440-i2c";
	clocks = <&clocks PCLK_I2C0>;
	clock-names = "i2c";
};

&intc {
	compatible = "samsung,s3c2416-irq";
};

&pinctrl_0 {
	compatible = "samsung,s3c2416-pinctrl";
};

&rtc {
	compatible = "samsung,s3c2416-rtc";
	clocks = <&clocks PCLK_RTC>;
	clock-names = "rtc";
};

&timer {
	clocks = <&clocks PCLK_PWM>;
	clock-names = "timers";
};

&uart_0 {
	compatible = "samsung,s3c2440-uart";
	clock-names = "uart", "clk_uart_baud2",
			"clk_uart_baud3";
	clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
			<&clocks SCLK_UART>;
};

&uart_1 {
	compatible = "samsung,s3c2440-uart";
	clock-names = "uart", "clk_uart_baud2",
			"clk_uart_baud3";
	clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
			<&clocks SCLK_UART>;
};

&uart_2 {
	compatible = "samsung,s3c2440-uart";
	clock-names = "uart", "clk_uart_baud2",
			"clk_uart_baud3";
	clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
			<&clocks SCLK_UART>;
};

&watchdog {
	interrupts = <1 9 27 3>;
	clocks = <&clocks PCLK_WDT>;
	clock-names = "watchdog";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's S3C24XX family device tree source
 *
 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
 */

/ {
	compatible = "samsung,s3c24xx";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		pinctrl0 = &pinctrl_0;
		serial0 = &uart_0;
		serial1 = &uart_1;
		serial2 = &uart_2;
	};

	intc: interrupt-controller@4a000000 {
		compatible = "samsung,s3c2410-irq";
		reg = <0x4a000000 0x100>;
		interrupt-controller;
		#interrupt-cells = <4>;
	};

	pinctrl_0: pinctrl@56000000 {
		reg = <0x56000000 0x1000>;

		wakeup-interrupt-controller {
			compatible = "samsung,s3c2410-wakeup-eint";
			interrupts = <0 0 0 3>,
				     <0 0 1 3>,
				     <0 0 2 3>,
				     <0 0 3 3>,
				     <0 0 4 4>,
				     <0 0 5 4>;
		};
	};

	timer: pwm@51000000 {
		compatible = "samsung,s3c2410-pwm";
		reg = <0x51000000 0x1000>;
		interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>;
		#pwm-cells = <3>;
	};

	uart_0: serial@50000000 {
		compatible = "samsung,s3c2410-uart";
		reg = <0x50000000 0x4000>;
		interrupts = <1 28 0 4>, <1 28 1 4>;
		status = "disabled";
	};

	uart_1: serial@50004000 {
		compatible = "samsung,s3c2410-uart";
		reg = <0x50004000 0x4000>;
		interrupts = <1 23 3 4>, <1 23 4 4>;
		status = "disabled";
	};

	uart_2: serial@50008000 {
		compatible = "samsung,s3c2410-uart";
		reg = <0x50008000 0x4000>;
		interrupts = <1 15 6 4>, <1 15 7 4>;
		status = "disabled";
	};

	watchdog: watchdog@53000000 {
		compatible = "samsung,s3c2410-wdt";
		reg = <0x53000000 0x100>;
		interrupts = <0 0 9 3>;
		status = "disabled";
	};

	rtc: rtc@57000000 {
		compatible = "samsung,s3c2410-rtc";
		reg = <0x57000000 0x100>;
		interrupts = <0 0 30 3>, <0 0 8 3>;
		status = "disabled";
	};

	i2c: i2c@54000000 {
		compatible = "samsung,s3c2410-i2c";
		reg = <0x54000000 0x100>;
		interrupts = <0 0 27 3>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's S3C6400 SoC device tree source
 *
 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
 *
 * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional
 * nodes can be added to this file.
 */

#include "s3c64xx.dtsi"

/ {
	compatible = "samsung,s3c6400";
};

&vic0 {
	valid-mask = <0xfffffe1f>;
	valid-wakeup-mask = <0x00200004>;
};

&vic1 {
	valid-mask = <0xffffffff>;
	valid-wakeup-mask = <0x53020000>;
};

&soc {
	clocks: clock-controller@7e00f000 {
		compatible = "samsung,s3c6400-clock";
		reg = <0x7e00f000 0x1000>;
		#clock-cells = <1>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's S3C6410 based Mini6410 board device tree source
 *
 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
 *
 * Device tree source file for FriendlyARM Mini6410 board which is based on
 * Samsung's S3C6410 SoC.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

#include "s3c6410.dtsi"

/ {
	model = "FriendlyARM Mini6410 board based on S3C6410";
	compatible = "friendlyarm,mini6410", "samsung,s3c6410";

	memory@50000000 {
		device_type = "memory";
		reg = <0x50000000 0x10000000>;
	};

	chosen {
		bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1";
	};

	fin_pll: oscillator-0 {
		compatible = "fixed-clock";
		clock-frequency = <12000000>;
		clock-output-names = "fin_pll";
		#clock-cells = <0>;
	};

	xusbxti: oscillator-1 {
		compatible = "fixed-clock";
		clock-output-names = "xusbxti";
		clock-frequency = <48000000>;
		#clock-cells = <0>;
	};

	srom-cs1-bus@18000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x18000000 0x8000000>;
		ranges;

		ethernet@18000000 {
			compatible = "davicom,dm9000";
			reg = <0x18000000 0x2 0x18000004 0x2>;
			interrupt-parent = <&gpn>;
			interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
			davicom,no-eeprom;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&gpio_keys>;
		autorepeat;

		button-k1 {
			label = "K1";
			gpios = <&gpn 0 GPIO_ACTIVE_LOW>;
			linux,code = <2>;
			debounce-interval = <20>;
		};

		button-k2 {
			label = "K2";
			gpios = <&gpn 1 GPIO_ACTIVE_LOW>;
			linux,code = <3>;
			debounce-interval = <20>;
		};

		button-k3 {
			label = "K3";
			gpios = <&gpn 2 GPIO_ACTIVE_LOW>;
			linux,code = <4>;
			debounce-interval = <20>;
		};

		button-k4 {
			label = "K4";
			gpios = <&gpn 3 GPIO_ACTIVE_LOW>;
			linux,code = <5>;
			debounce-interval = <20>;
		};

		button-k5 {
			label = "K5";
			gpios = <&gpn 4 GPIO_ACTIVE_LOW>;
			linux,code = <6>;
			debounce-interval = <20>;
		};

		button-k6 {
			label = "K6";
			gpios = <&gpn 5 GPIO_ACTIVE_LOW>;
			linux,code = <7>;
			debounce-interval = <20>;
		};

		button-k7 {
			label = "K7";
			gpios = <&gpl 11 GPIO_ACTIVE_LOW>;
			linux,code = <8>;
			debounce-interval = <20>;
		};

		button-k8 {
			label = "K8";
			gpios = <&gpl 12 GPIO_ACTIVE_LOW>;
			linux,code = <9>;
			debounce-interval = <20>;
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&gpio_leds>;

		led-1 {
			label = "LED1";
			gpios = <&gpk 4 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
		};

		led-2 {
			label = "LED2";
			gpios = <&gpk 5 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "mmc0";
		};

		led-3 {
			label = "LED3";
			gpios = <&gpk 6 GPIO_ACTIVE_LOW>;
		};

		led-4 {
			label = "LED4";
			gpios = <&gpk 7 GPIO_ACTIVE_LOW>;
		};
	};

	buzzer {
		compatible = "pwm-beeper";
		pwms = <&pwm 0 1000000 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm0_out>;
	};
};

&clocks {
	clocks = <&fin_pll>;
};

&sdhci0 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
	bus-width = <4>;
	status = "okay";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_data>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_data>, <&uart1_fctl>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_data>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_data>;
	status = "okay";
};

&pinctrl0 {
	gpio_leds: gpio-leds-pins {
		samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7";
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	gpio_keys: gpio-keys-pins {
		samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3",
				"gpn-4", "gpn-5", "gpl-11", "gpl-12";
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_bus>;
	status = "okay";

	eeprom@50 {
		compatible = "atmel,24c08";
		reg = <0x50>;
		pagesize = <16>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung S3C6410 based SMDK6410 board device tree source.
 *
 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
 *
 * Device tree source file for Samsung SMDK6410 board which is based on
 * Samsung's S3C6410 SoC.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

#include "s3c6410.dtsi"

/ {
	model = "Samsung SMDK6410 board based on S3C6410";
	compatible = "samsung,smdk6410", "samsung,s3c6410";

	memory@50000000 {
		device_type = "memory";
		reg = <0x50000000 0x8000000>;
	};

	chosen {
		bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1";
	};

	fin_pll: oscillator-0 {
		compatible = "fixed-clock";
		clock-frequency = <12000000>;
		clock-output-names = "fin_pll";
		#clock-cells = <0>;
	};

	xusbxti: oscillator-1 {
		compatible = "fixed-clock";
		clock-output-names = "xusbxti";
		clock-frequency = <48000000>;
		#clock-cells = <0>;
	};

	srom-cs1-bus@18000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x18000000 0x8000000>;
		ranges;

		ethernet@18000000 {
			compatible = "smsc,lan9115";
			reg = <0x18000000 0x10000>;
			interrupt-parent = <&gpn>;
			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
			phy-mode = "mii";
			reg-io-width = <4>;
			smsc,force-internal-phy;
		};
	};
};

&clocks {
	clocks = <&fin_pll>;
};

&sdhci0 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
	bus-width = <4>;
	status = "okay";
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_data>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_data>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_data>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's S3C6410 SoC device tree source
 *
 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
 *
 * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional
 * nodes can be added to this file.
 */

#include "s3c64xx.dtsi"

/ {
	compatible = "samsung,s3c6410";

	aliases {
		i2c1 = &i2c1;
	};
};

&vic0 {
	valid-mask = <0xffffff7f>;
	valid-wakeup-mask = <0x00200004>;
};

&vic1 {
	valid-mask = <0xffffffff>;
	valid-wakeup-mask = <0x53020000>;
};

&soc {
	clocks: clock-controller@7e00f000 {
		compatible = "samsung,s3c6410-clock";
		reg = <0x7e00f000 0x1000>;
		#clock-cells = <1>;
	};

	i2c1: i2c@7f00f000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x7f00f000 0x1000>;
		interrupt-parent = <&vic0>;
		interrupts = <5>;
		clock-names = "i2c";
		clocks = <&clocks PCLK_IIC1>;
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <0>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's S3C64xx SoC series common device tree source
 * - pin control-related definitions
 *
 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
 *
 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
 * listed as device tree nodes in this file.
 */

#include "s3c64xx-pinctrl.h"

&pinctrl0 {
	/*
	 * Pin banks
	 */

	gpa: gpa-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpb: gpb-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpc: gpc-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpd: gpd-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpe: gpe-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpf: gpf-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpg: gpg-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gph: gph-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpi: gpi-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpj: gpj-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpk: gpk-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpl: gpl-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpm: gpm-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpn: gpn-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpo: gpo-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpp: gpp-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpq: gpq-gpio-bank {
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	/*
	 * Pin groups
	 */

	uart0_data: uart0-data-pins {
		samsung,pins = "gpa-0", "gpa-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	uart0_fctl: uart0-fctl-pins {
		samsung,pins = "gpa-2", "gpa-3";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	uart1_data: uart1-data-pins {
		samsung,pins = "gpa-4", "gpa-5";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	uart1_fctl: uart1-fctl-pins {
		samsung,pins = "gpa-6", "gpa-7";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	uart2_data: uart2-data-pins {
		samsung,pins = "gpb-0", "gpb-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	uart3_data: uart3-data-pins {
		samsung,pins = "gpb-2", "gpb-3";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	ext_dma_0: ext-dma-0-pins {
		samsung,pins = "gpb-0", "gpb-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	ext_dma_1: ext-dma-1-pins {
		samsung,pins = "gpb-2", "gpb-3";
		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	irda_data_0: irda-data-0-pins {
		samsung,pins = "gpb-0", "gpb-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	irda_data_1: irda-data-1-pins {
		samsung,pins = "gpb-2", "gpb-3";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	irda_sdbw: irda-sdbw-pins {
		samsung,pins = "gpb-4";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	i2c0_bus: i2c0-bus-pins {
		samsung,pins = "gpb-5", "gpb-6";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
	};

	i2c1_bus: i2c1-bus-pins {
		/* S3C6410-only */
		samsung,pins = "gpb-2", "gpb-3";
		samsung,pin-function = <S3C64XX_PIN_FUNC_6>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
	};

	spi0_bus: spi0-bus-pins {
		samsung,pins = "gpc-0", "gpc-1", "gpc-2";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
	};

	spi0_cs: spi0-cs-pins {
		samsung,pins = "gpc-3";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	spi1_bus: spi1-bus-pins {
		samsung,pins = "gpc-4", "gpc-5", "gpc-6";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
	};

	spi1_cs: spi1-cs-pins {
		samsung,pins = "gpc-7";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd0_cmd: sd0-cmd-pins {
		samsung,pins = "gpg-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd0_clk: sd0-clk-pins {
		samsung,pins = "gpg-0";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd0_bus1: sd0-bus1-pins {
		samsung,pins = "gpg-2";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd0_bus4: sd0-bus4-pins {
		samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd0_cd: sd0-cd-pins {
		samsung,pins = "gpg-6";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
	};

	sd1_cmd: sd1-cmd-pins {
		samsung,pins = "gph-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd1_clk: sd1-clk-pins {
		samsung,pins = "gph-0";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd1_bus1: sd1-bus1-pins {
		samsung,pins = "gph-2";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd1_bus4: sd1-bus4-pins {
		samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd1_bus8: sd1-bus8-pins {
		samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5",
				"gph-6", "gph-7", "gph-8", "gph-9";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd1_cd: sd1-cd-pins {
		samsung,pins = "gpg-6";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_UP>;
	};

	sd2_cmd: sd2-cmd-pins {
		samsung,pins = "gpc-4";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd2_clk: sd2-clk-pins {
		samsung,pins = "gpc-5";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd2_bus1: sd2-bus1-pins {
		samsung,pins = "gph-6";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	sd2_bus4: sd2-bus4-pins {
		samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	i2s0_bus: i2s0-bus-pins {
		samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	i2s0_cdclk: i2s0-cdclk-pins {
		samsung,pins = "gpd-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	i2s1_bus: i2s1-bus-pins {
		samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	i2s1_cdclk: i2s1-cdclk-pins {
		samsung,pins = "gpe-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	i2s2_bus: i2s2-bus-pins {
		/* S3C6410-only */
		samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6",
				"gph-8", "gph-9";
		samsung,pin-function = <S3C64XX_PIN_FUNC_5>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	i2s2_cdclk: i2s2-cdclk-pins {
		/* S3C6410-only */
		samsung,pins = "gph-7";
		samsung,pin-function = <S3C64XX_PIN_FUNC_5>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	pcm0_bus: pcm0-bus-pins {
		samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	pcm0_extclk: pcm0-extclk-pins {
		samsung,pins = "gpd-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	pcm1_bus: pcm1-bus-pins {
		samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	pcm1_extclk: pcm1-extclk-pins {
		samsung,pins = "gpe-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	ac97_bus_0: ac97-bus-0-pins {
		samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4";
		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	ac97_bus_1: ac97-bus-1-pins {
		samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4";
		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	cam_port: cam-port-pins {
		samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4",
				"gpf-5", "gpf-6", "gpf-7", "gpf-8",
				"gpf-9", "gpf-10", "gpf-11", "gpf-12";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	cam_rst: cam-rst-pins {
		samsung,pins = "gpf-3";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	cam_field: cam-field-pins {
		/* S3C6410-only */
		samsung,pins = "gpb-4";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	pwm_extclk: pwm-extclk-pins {
		samsung,pins = "gpf-13";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	pwm0_out: pwm0-out-pins {
		samsung,pins = "gpf-14";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	pwm1_out: pwm1-out-pins {
		samsung,pins = "gpf-15";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	clkout0: clkout-0-pins {
		samsung,pins = "gpf-14";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col0_0: keypad-col0-0-pins {
		samsung,pins = "gph-0";
		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col1_0: keypad-col1-0-pins {
		samsung,pins = "gph-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col2_0: keypad-col2-0-pins {
		samsung,pins = "gph-2";
		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col3_0: keypad-col3-0-pins {
		samsung,pins = "gph-3";
		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col4_0: keypad-col4-0-pins {
		samsung,pins = "gph-4";
		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col5_0: keypad-col5-0-pins {
		samsung,pins = "gph-5";
		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col6_0: keypad-col6-0-pins {
		samsung,pins = "gph-6";
		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col7_0: keypad-col7-0-pins {
		samsung,pins = "gph-7";
		samsung,pin-function = <S3C64XX_PIN_FUNC_4>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col0_1: keypad-col0-1-pins {
		samsung,pins = "gpl-0";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col1_1: keypad-col1-1-pins {
		samsung,pins = "gpl-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col2_1: keypad-col2-1-pins {
		samsung,pins = "gpl-2";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col3_1: keypad-col3-1-pins {
		samsung,pins = "gpl-3";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col4_1: keypad-col4-1-pins {
		samsung,pins = "gpl-4";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col5_1: keypad-col5-1-pins {
		samsung,pins = "gpl-5";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col6_1: keypad-col6-1-pins {
		samsung,pins = "gpl-6";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_col7_1: keypad-col7-1-pins {
		samsung,pins = "gpl-7";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row0_0: keypad-row0-0-pins {
		samsung,pins = "gpk-8";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row1_0: keypad-row1-0-pins {
		samsung,pins = "gpk-9";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row2_0: keypad-row2-0-pins {
		samsung,pins = "gpk-10";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row3_0: keypad-row3-0-pins {
		samsung,pins = "gpk-11";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row4_0: keypad-row4-0-pins {
		samsung,pins = "gpk-12";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row5_0: keypad-row5-0-pins {
		samsung,pins = "gpk-13";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row6_0: keypad-row6-0-pins {
		samsung,pins = "gpk-14";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row7_0: keypad-row7-0-pins {
		samsung,pins = "gpk-15";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row0_1: keypad-row0-1-pins {
		samsung,pins = "gpn-0";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row1_1: keypad-row1-1-pins {
		samsung,pins = "gpn-1";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row2_1: keypad-row2-1-pins {
		samsung,pins = "gpn-2";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row3_1: keypad-row3-1-pins {
		samsung,pins = "gpn-3";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row4_1: keypad-row4-1-pins {
		samsung,pins = "gpn-4";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row5_1: keypad-row5-1-pins {
		samsung,pins = "gpn-5";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row6_1: keypad-row6-1-pins {
		samsung,pins = "gpn-6";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	keypad_row7_1: keypad-row7-1-pins {
		samsung,pins = "gpn-7";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	lcd_ctrl: lcd-ctrl-pins {
		samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	lcd_data16: lcd-data-width16-pins {
		samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6",
				"gpi-7", "gpi-10", "gpi-11", "gpi-12",
				"gpi-13", "gpi-14", "gpi-15", "gpj-3",
				"gpj-4", "gpj-5", "gpj-6", "gpj-7";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	lcd_data18: lcd-data-width18-pins {
		samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5",
				"gpi-6", "gpi-7", "gpi-10", "gpi-11",
				"gpi-12", "gpi-13", "gpi-14", "gpi-15",
				"gpj-2", "gpj-3", "gpj-4", "gpj-5",
				"gpj-6", "gpj-7";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	lcd_data24: lcd-data-width24-pins {
		samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3",
				"gpi-4", "gpi-5", "gpi-6", "gpi-7",
				"gpi-8", "gpi-9", "gpi-10", "gpi-11",
				"gpi-12", "gpi-13", "gpi-14", "gpi-15",
				"gpj-0", "gpj-1", "gpj-2", "gpj-3",
				"gpj-4", "gpj-5", "gpj-6", "gpj-7";
		samsung,pin-function = <S3C64XX_PIN_FUNC_2>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};

	hsi_bus: hsi-bus-pins {
		samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3",
				"gpk-4", "gpk-5", "gpk-6", "gpk-7";
		samsung,pin-function = <S3C64XX_PIN_FUNC_3>;
		samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
	};
};


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Samsung S3C64xx DTS pinctrl constants
 *
 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 * Copyright (c) 2022 Linaro Ltd
 * Author: Krzysztof Kozlowski <krzk@kernel.org>
 */

#ifndef __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__
#define __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__

#define S3C64XX_PIN_PULL_NONE		0
#define S3C64XX_PIN_PULL_DOWN		1
#define S3C64XX_PIN_PULL_UP		2

#define S3C64XX_PIN_FUNC_INPUT		0
#define S3C64XX_PIN_FUNC_OUTPUT		1
#define S3C64XX_PIN_FUNC_2		2
#define S3C64XX_PIN_FUNC_3		3
#define S3C64XX_PIN_FUNC_4		4
#define S3C64XX_PIN_FUNC_5		5
#define S3C64XX_PIN_FUNC_6		6
#define S3C64XX_PIN_FUNC_EINT		7

#endif /* __DTS_ARM_SAMSUNG_S3C64XX_PINCTRL_H__ */


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's S3C64xx SoC series common device tree source
 *
 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
 *
 * Samsung's S3C64xx SoC series device nodes are listed in this file.
 * Particular SoCs from S3C64xx series can include this file and provide
 * values for SoCs specfic bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional
 * nodes can be added to this file.
 */

#include <dt-bindings/clock/samsung,s3c64xx-clock.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		i2c0 = &i2c0;
		pinctrl0 = &pinctrl0;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,arm1176jzf-s";
			reg = <0x0>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		vic0: interrupt-controller@71200000 {
			compatible = "arm,pl192-vic";
			interrupt-controller;
			reg = <0x71200000 0x1000>;
			#interrupt-cells = <1>;
		};

		vic1: interrupt-controller@71300000 {
			compatible = "arm,pl192-vic";
			interrupt-controller;
			reg = <0x71300000 0x1000>;
			#interrupt-cells = <1>;
		};

		sdhci0: mmc@7c200000 {
			compatible = "samsung,s3c6410-sdhci";
			reg = <0x7c200000 0x100>;
			interrupt-parent = <&vic1>;
			interrupts = <24>;
			clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
			clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
					<&clocks SCLK_MMC0>;
			status = "disabled";
		};

		sdhci1: mmc@7c300000 {
			compatible = "samsung,s3c6410-sdhci";
			reg = <0x7c300000 0x100>;
			interrupt-parent = <&vic1>;
			interrupts = <25>;
			clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
			clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
					<&clocks SCLK_MMC1>;
			status = "disabled";
		};

		sdhci2: mmc@7c400000 {
			compatible = "samsung,s3c6410-sdhci";
			reg = <0x7c400000 0x100>;
			interrupt-parent = <&vic1>;
			interrupts = <17>;
			clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
			clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
					<&clocks SCLK_MMC2>;
			status = "disabled";
		};

		watchdog: watchdog@7e004000 {
			compatible = "samsung,s3c6410-wdt";
			reg = <0x7e004000 0x1000>;
			interrupt-parent = <&vic0>;
			interrupts = <26>;
			clock-names = "watchdog";
			clocks = <&clocks PCLK_WDT>;
		};

		i2c0: i2c@7f004000 {
			compatible = "samsung,s3c2440-i2c";
			reg = <0x7f004000 0x1000>;
			interrupt-parent = <&vic1>;
			interrupts = <18>;
			clock-names = "i2c";
			clocks = <&clocks PCLK_IIC0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		uart0: serial@7f005000 {
			compatible = "samsung,s3c6400-uart";
			reg = <0x7f005000 0x100>;
			interrupt-parent = <&vic1>;
			interrupts = <5>;
			clock-names = "uart", "clk_uart_baud2",
					"clk_uart_baud3";
			clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
					<&clocks SCLK_UART>;
			status = "disabled";
		};

		uart1: serial@7f005400 {
			compatible = "samsung,s3c6400-uart";
			reg = <0x7f005400 0x100>;
			interrupt-parent = <&vic1>;
			interrupts = <6>;
			clock-names = "uart", "clk_uart_baud2",
					"clk_uart_baud3";
			clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
					<&clocks SCLK_UART>;
			status = "disabled";
		};

		uart2: serial@7f005800 {
			compatible = "samsung,s3c6400-uart";
			reg = <0x7f005800 0x100>;
			interrupt-parent = <&vic1>;
			interrupts = <7>;
			clock-names = "uart", "clk_uart_baud2",
					"clk_uart_baud3";
			clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
					<&clocks SCLK_UART>;
			status = "disabled";
		};

		uart3: serial@7f005c00 {
			compatible = "samsung,s3c6400-uart";
			reg = <0x7f005c00 0x100>;
			interrupt-parent = <&vic1>;
			interrupts = <8>;
			clock-names = "uart", "clk_uart_baud2",
					"clk_uart_baud3";
			clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
					<&clocks SCLK_UART>;
			status = "disabled";
		};

		pwm: pwm@7f006000 {
			compatible = "samsung,s3c6400-pwm";
			reg = <0x7f006000 0x1000>;
			interrupt-parent = <&vic0>;
			interrupts = <23>, <24>, <25>, <27>, <28>;
			clock-names = "timers";
			clocks = <&clocks PCLK_PWM>;
			samsung,pwm-outputs = <0>, <1>;
			#pwm-cells = <3>;
		};

		pinctrl0: pinctrl@7f008000 {
			compatible = "samsung,s3c64xx-pinctrl";
			reg = <0x7f008000 0x1000>;
			interrupt-parent = <&vic1>;
			interrupts = <21>;

			wakeup-interrupt-controller {
				compatible = "samsung,s3c64xx-wakeup-eint";
				interrupts-extended = <&vic0 0>,
						      <&vic0 1>,
						      <&vic1 0>,
						      <&vic1 1>;
			};
		};
	};
};

#include "s3c64xx-pinctrl.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's S5PV210 SoC device tree source
 *
 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
 *
 * Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
 * Tomasz Figa <t.figa@samsung.com>
 *
 * Board device tree source for Samsung Aquila board.
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "s5pv210.dtsi"

/ {
	model = "Samsung Aquila based on S5PC110";
	compatible = "samsung,aquila", "samsung,s5pv210";

	aliases {
		i2c3 = &i2c_pmic;
	};

	chosen {
		bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk1p5 rw rootwait ignore_loglevel earlyprintk";
	};

	memory@30000000 {
		device_type = "memory";
		reg = <0x30000000 0x05000000>, <0x40000000 0x18000000>;
	};

	pmic_ap_clk: clock-0 {
		/* Workaround for missing clock on PMIC */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
	};

	vtf_reg: regulator-0 {
		compatible = "regulator-fixed";
		regulator-name = "V_TF_2.8V";
		regulator-min-microvolt = <2800000>;
		regulator-max-microvolt = <2800000>;
		gpio = <&mp05 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	pda_reg: regulator-1 {
		compatible = "regulator-fixed";
		regulator-name = "VCC_1.8V_PDA";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	bat_reg: regulator-2 {
		compatible = "regulator-fixed";
		regulator-name = "V_BAT";
		regulator-min-microvolt = <3700000>;
		regulator-max-microvolt = <3700000>;
	};

	i2c_pmic: i2c-pmic {
		compatible = "i2c-gpio";
		sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>;
		scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>;
		i2c-gpio,delay-us = <2>;        /* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;

		pmic@66 {
			compatible = "national,lp3974";
			reg = <0x66>;

			max8998,pmic-buck1-default-dvs-idx = <0>;
			max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>,
							<&gph0 4 GPIO_ACTIVE_HIGH>;
			max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>,
							<1200000>, <1200000>;

			max8998,pmic-buck2-default-dvs-idx = <0>;
			max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>;
			max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>;

			regulators {
				ldo2_reg: LDO2 {
					regulator-name = "VALIVE_1.1V";
					regulator-min-microvolt = <1100000>;
					regulator-max-microvolt = <1100000>;
					regulator-always-on;
				};

				ldo3_reg: LDO3 {
					regulator-name = "VUSB+MIPI_1.1V";
					regulator-min-microvolt = <1100000>;
					regulator-max-microvolt = <1100000>;
					regulator-always-on;
				};

				ldo4_reg: LDO4 {
					regulator-name = "VADC_3.3V";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
				};

				ldo5_reg: LDO5 {
					regulator-name = "VTF_2.8V";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <2800000>;
					regulator-always-on;
				};

				ldo6_reg: LDO6 {
					regulator-name = "VCC_3.3V";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};

				ldo7_reg: LDO7 {
					regulator-name = "VCC_3.0V";
					regulator-min-microvolt = <3000000>;
					regulator-max-microvolt = <3000000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo8_reg: LDO8 {
					regulator-name = "VUSB+VDAC_3.3V";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};

				ldo9_reg: LDO9 {
					regulator-name = "VCC+VCAM_2.8V";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <2800000>;
					regulator-always-on;
				};

				ldo10_reg: LDO10 {
					regulator-name = "VPLL_1.1V";
					regulator-min-microvolt = <1100000>;
					regulator-max-microvolt = <1100000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo11_reg: LDO11 {
					regulator-name = "CAM_IO_2.8V";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <2800000>;
					regulator-always-on;
				};

				ldo12_reg: LDO12 {
					regulator-name = "CAM_ISP_1.2V";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
				};

				ldo13_reg: LDO13 {
					regulator-name = "CAM_A_2.8V";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <2800000>;
					regulator-always-on;
				};

				ldo14_reg: LDO14 {
					regulator-name = "CAM_CIF_1.8V";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
				};

				ldo15_reg: LDO15 {
					regulator-name = "CAM_AF_3.3V";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};

				ldo16_reg: LDO16 {
					regulator-name = "VMIPI_1.8V";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
				};

				ldo17_reg: LDO17 {
					regulator-name = "CAM_8M_1.8V";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
				};

				buck1_reg: BUCK1 {
					regulator-name = "VARM_1.2V";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
				};

				buck2_reg: BUCK2 {
					regulator-name = "VINT_1.2V";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
				};

				buck3_reg: BUCK3 {
					regulator-name = "VCC_1.8V";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
				};

				buck4_reg: BUCK4 {
					regulator-name = "CAM_CORE_1.2V";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
				};

				ap32khz_reg: EN32KHz-AP {
					regulator-name = "32KHz AP";
					regulator-always-on;
				};

				vichg_reg: ENVICHG {
					regulator-name = "VICHG";
				};

				safeout1_reg: ESAFEOUT1 {
					regulator-name = "SAFEOUT1";
					regulator-always-on;
				};

				safeout2_reg: ESAFEOUT2 {
					regulator-name = "SAFEOUT2";
					regulator-boot-on;
				};
			};
		};

	};

	gpio-keys {
		compatible = "gpio-keys";

		power-key {
			gpios = <&gph2 6 1>;
			linux,code = <KEY_POWER>;
			label = "power";
			debounce-interval = <1>;
			wakeup-source;
		};
	};
};

&xusbxti {
	clock-frequency = <24000000>;
};

&keypad {
	linux,input-no-autorepeat;
	wakeup-source;
	samsung,keypad-num-rows = <3>;
	samsung,keypad-num-columns = <3>;
	pinctrl-names = "default";
	pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
			<&keypad_col0>, <&keypad_col1>, <&keypad_col2>;
	status = "okay";

	key-1 {
		keypad,row = <0>;
		keypad,column = <1>;
		linux,code = <KEY_CONNECT>;
	};

	key-2 {
		keypad,row = <0>;
		keypad,column = <2>;
		linux,code = <KEY_BACK>;
	};

	key-3 {
		keypad,row = <1>;
		keypad,column = <1>;
		linux,code = <KEY_CAMERA_FOCUS>;
	};

	key-4 {
		keypad,row = <1>;
		keypad,column = <2>;
		linux,code = <KEY_VOLUMEUP>;
	};

	key-5 {
		keypad,row = <2>;
		keypad,column = <1>;
		linux,code = <KEY_CAMERA>;
	};

	key-6 {
		keypad,row = <2>;
		keypad,column = <2>;
		linux,code = <KEY_VOLUMEDOWN>;
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&rtc {
	clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>;
	clock-names = "rtc", "rtc_src";
};

&sdhci0 {
	bus-width = <4>;
	non-removable;
	status = "okay";
	vmmc-supply = <&ldo5_reg>;
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>;
	pinctrl-names = "default";
};

&sdhci2 {
	bus-width = <4>;
	cd-gpios = <&gph3 4 1>;
	vmmc-supply = <&vtf_reg>;
	cd-inverted;
	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &t_flash_detect>;
	pinctrl-names = "default";
	status = "okay";
};

&onenand {
	status = "okay";
};

&hsotg {
	vusb_a-supply = <&ldo3_reg>;
	vusb_d-supply = <&ldo8_reg>;
	dr_mode = "peripheral";
	status = "okay";
};

&usbphy {
	status = "okay";
};

&fimd {
	pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
	pinctrl-names = "default";
	status = "okay";

	display-timings {
		native-mode = <&timing0>;
		timing0: timing {
			clock-frequency = <0>;
			hactive = <800>;
			vactive = <480>;
			hfront-porch = <16>;
			hback-porch = <16>;
			hsync-len = <2>;
			vback-porch = <3>;
			vfront-porch = <28>;
			vsync-len = <1>;
		};
	};
};

&pinctrl0 {
	t_flash_detect: t-flash-detect-pins {
		samsung,pins = "gph3-4";
		samsung,pin-function = <S5PV210_PIN_FUNC_INPUT>;
		samsung,pin-pud = <S5PV210_PIN_PULL_NONE>;
	};
};