code:
======================
Linux Kernel Makefiles
======================

This document describes the Linux kernel Makefiles.

.. Table of Contents

	=== 1 Overview
	=== 2 Who does what
	=== 3 The kbuild files
	   --- 3.1 Goal definitions
	   --- 3.2 Built-in object goals - obj-y
	   --- 3.3 Loadable module goals - obj-m
	   --- 3.4 <deleted>
	   --- 3.5 Library file goals - lib-y
	   --- 3.6 Descending down in directories
	   --- 3.7 Non-builtin vmlinux targets - extra-y
	   --- 3.8 Always built goals - always-y
	   --- 3.9 Compilation flags
	   --- 3.10 Dependency tracking
	   --- 3.11 Custom Rules
	   --- 3.12 Command change detection
	   --- 3.13 $(CC) support functions
	   --- 3.14 $(LD) support functions
	   --- 3.15 Script Invocation

	=== 4 Host Program support
	   --- 4.1 Simple Host Program
	   --- 4.2 Composite Host Programs
	   --- 4.3 Using C++ for host programs
	   --- 4.4 Using Rust for host programs
	   --- 4.5 Controlling compiler options for host programs
	   --- 4.6 When host programs are actually built

	=== 5 Userspace Program support
	   --- 5.1 Simple Userspace Program
	   --- 5.2 Composite Userspace Programs
	   --- 5.3 Controlling compiler options for userspace programs
	   --- 5.4 When userspace programs are actually built

	=== 6 Kbuild clean infrastructure

	=== 7 Architecture Makefiles
	   --- 7.1 Set variables to tweak the build to the architecture
	   --- 7.2 Add prerequisites to archheaders
	   --- 7.3 Add prerequisites to archprepare
	   --- 7.4 List directories to visit when descending
	   --- 7.5 Architecture-specific boot images
	   --- 7.6 Building non-kbuild targets
	   --- 7.7 Commands useful for building a boot image
	   --- 7.8 <deleted>
	   --- 7.9 Preprocessing linker scripts
	   --- 7.10 Generic header files
	   --- 7.11 Post-link pass

	=== 8 Kbuild syntax for exported headers
		--- 8.1 no-export-headers
		--- 8.2 generic-y
		--- 8.3 generated-y
		--- 8.4 mandatory-y

	=== 9 Kbuild Variables
	=== 10 Makefile language
	=== 11 Credits
	=== 12 TODO

1 Overview
==========

The Makefiles have five parts::

	Makefile                    the top Makefile.
	.config                     the kernel configuration file.
	arch/$(SRCARCH)/Makefile    the arch Makefile.
	scripts/Makefile.*          common rules etc. for all kbuild Makefiles.
	kbuild Makefiles            exist in every subdirectory

The top Makefile reads the .config file, which comes from the kernel
configuration process.

The top Makefile is responsible for building two major products: vmlinux
(the resident kernel image) and modules (any module files).
It builds these goals by recursively descending into the subdirectories of
the kernel source tree.
The list of subdirectories which are visited depends upon the kernel
configuration. The top Makefile textually includes an arch Makefile
with the name arch/$(SRCARCH)/Makefile. The arch Makefile supplies
architecture-specific information to the top Makefile.

Each subdirectory has a kbuild Makefile which carries out the commands
passed down from above. The kbuild Makefile uses information from the
.config file to construct various file lists used by kbuild to build
any built-in or modular targets.

scripts/Makefile.* contains all the definitions/rules etc. that
are used to build the kernel based on the kbuild makefiles.

2 Who does what
===============

People have four different relationships with the kernel Makefiles.

*Users* are people who build kernels.  These people type commands such as
"make menuconfig" or "make".  They usually do not read or edit
any kernel Makefiles (or any other source files).

*Normal developers* are people who work on features such as device
drivers, file systems, and network protocols.  These people need to
maintain the kbuild Makefiles for the subsystem they are
working on.  In order to do this effectively, they need some overall
knowledge about the kernel Makefiles, plus detailed knowledge about the
public interface for kbuild.

*Arch developers* are people who work on an entire architecture, such
as sparc or ia64.  Arch developers need to know about the arch Makefile
as well as kbuild Makefiles.

*Kbuild developers* are people who work on the kernel build system itself.
These people need to know about all aspects of the kernel Makefiles.

This document is aimed towards normal developers and arch developers.

3 The kbuild files
==================

Most Makefiles within the kernel are kbuild Makefiles that use the
kbuild infrastructure. This chapter introduces the syntax used in the
kbuild makefiles.
The preferred name for the kbuild files are 'Makefile' but 'Kbuild' can
be used and if both a 'Makefile' and a 'Kbuild' file exists, then the 'Kbuild'
file will be used.

Section 3.1 "Goal definitions" is a quick intro; further chapters provide
more details, with real examples.

3.1 Goal definitions
--------------------

	Goal definitions are the main part (heart) of the kbuild Makefile.
	These lines define the files to be built, any special compilation
	options, and any subdirectories to be entered recursively.

	The most simple kbuild makefile contains one line:

	Example::

		obj-y += foo.o

	This tells kbuild that there is one object in that directory, named
	foo.o. foo.o will be built from foo.c or foo.S.

	If foo.o shall be built as a module, the variable obj-m is used.
	Therefore the following pattern is often used:

	Example::

		obj-$(CONFIG_FOO) += foo.o

	$(CONFIG_FOO) evaluates to either y (for built-in) or m (for module).
	If CONFIG_FOO is neither y nor m, then the file will not be compiled
	nor linked.

3.2 Built-in object goals - obj-y
---------------------------------

	The kbuild Makefile specifies object files for vmlinux
	in the $(obj-y) lists.  These lists depend on the kernel
	configuration.

	Kbuild compiles all the $(obj-y) files.  It then calls
	"$(AR) rcSTP" to merge these files into one built-in.a file.
	This is a thin archive without a symbol table. It will be later
	linked into vmlinux by scripts/link-vmlinux.sh

	The order of files in $(obj-y) is significant.  Duplicates in
	the lists are allowed: the first instance will be linked into
	built-in.a and succeeding instances will be ignored.

	Link order is significant, because certain functions
	(module_init() / __initcall) will be called during boot in the
	order they appear. So keep in mind that changing the link
	order may e.g. change the order in which your SCSI
	controllers are detected, and thus your disks are renumbered.

	Example::

		#drivers/isdn/i4l/Makefile
		# Makefile for the kernel ISDN subsystem and device drivers.
		# Each configuration option enables a list of files.
		obj-$(CONFIG_ISDN_I4L)         += isdn.o
		obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o

3.3 Loadable module goals - obj-m
---------------------------------

	$(obj-m) specifies object files which are built as loadable
	kernel modules.

	A module may be built from one source file or several source
	files. In the case of one source file, the kbuild makefile
	simply adds the file to $(obj-m).

	Example::

		#drivers/isdn/i4l/Makefile
		obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o

	Note: In this example $(CONFIG_ISDN_PPP_BSDCOMP) evaluates to 'm'

	If a kernel module is built from several source files, you specify
	that you want to build a module in the same way as above; however,
	kbuild needs to know which object files you want to build your
	module from, so you have to tell it by setting a $(<module_name>-y)
	variable.

	Example::

		#drivers/isdn/i4l/Makefile
		obj-$(CONFIG_ISDN_I4L) += isdn.o
		isdn-y := isdn_net_lib.o isdn_v110.o isdn_common.o

	In this example, the module name will be isdn.o. Kbuild will
	compile the objects listed in $(isdn-y) and then run
	"$(LD) -r" on the list of these files to generate isdn.o.

	Due to kbuild recognizing $(<module_name>-y) for composite objects,
	you can use the value of a `CONFIG_` symbol to optionally include an
	object file as part of a composite object.

	Example::

		#fs/ext2/Makefile
	        obj-$(CONFIG_EXT2_FS) += ext2.o
		ext2-y := balloc.o dir.o file.o ialloc.o inode.o ioctl.o \
			  namei.o super.o symlink.o
	        ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o xattr_user.o \
						xattr_trusted.o

	In this example, xattr.o, xattr_user.o and xattr_trusted.o are only
	part of the composite object ext2.o if $(CONFIG_EXT2_FS_XATTR)
	evaluates to 'y'.

	Note: Of course, when you are building objects into the kernel,
	the syntax above will also work. So, if you have CONFIG_EXT2_FS=y,
	kbuild will build an ext2.o file for you out of the individual
	parts and then link this into built-in.a, as you would expect.

3.5 Library file goals - lib-y
------------------------------

	Objects listed with obj-* are used for modules, or
	combined in a built-in.a for that specific directory.
	There is also the possibility to list objects that will
	be included in a library, lib.a.
	All objects listed with lib-y are combined in a single
	library for that directory.
	Objects that are listed in obj-y and additionally listed in
	lib-y will not be included in the library, since they will
	be accessible anyway.
	For consistency, objects listed in lib-m will be included in lib.a.

	Note that the same kbuild makefile may list files to be built-in
	and to be part of a library. Therefore the same directory
	may contain both a built-in.a and a lib.a file.

	Example::

		#arch/x86/lib/Makefile
		lib-y    := delay.o

	This will create a library lib.a based on delay.o. For kbuild to
	actually recognize that there is a lib.a being built, the directory
	shall be listed in libs-y.

	See also "7.4 List directories to visit when descending".

	Use of lib-y is normally restricted to `lib/` and `arch/*/lib`.

3.6 Descending down in directories
----------------------------------

	A Makefile is only responsible for building objects in its own
	directory. Files in subdirectories should be taken care of by
	Makefiles in these subdirs. The build system will automatically
	invoke make recursively in subdirectories, provided you let it know of
	them.

	To do so, obj-y and obj-m are used.
	ext2 lives in a separate directory, and the Makefile present in fs/
	tells kbuild to descend down using the following assignment.

	Example::

		#fs/Makefile
		obj-$(CONFIG_EXT2_FS) += ext2/

	If CONFIG_EXT2_FS is set to either 'y' (built-in) or 'm' (modular)
	the corresponding obj- variable will be set, and kbuild will descend
	down in the ext2 directory.

	Kbuild uses this information not only to decide that it needs to visit
	the directory, but also to decide whether or not to link objects from
	the directory into vmlinux.

	When Kbuild descends into the directory with 'y', all built-in objects
	from that directory are combined into the built-in.a, which will be
	eventually linked into vmlinux.

	When Kbuild descends into the directory with 'm', in contrast, nothing
	from that directory will be linked into vmlinux. If the Makefile in
	that directory specifies obj-y, those objects will be left orphan.
	It is very likely a bug of the Makefile or of dependencies in Kconfig.

	Kbuild also supports dedicated syntax, subdir-y and subdir-m, for
	descending into subdirectories. It is a good fit when you know they
	do not contain kernel-space objects at all. A typical usage is to let
	Kbuild descend into subdirectories to build tools.

	Examples::

		# scripts/Makefile
		subdir-$(CONFIG_GCC_PLUGINS) += gcc-plugins
		subdir-$(CONFIG_MODVERSIONS) += genksyms
		subdir-$(CONFIG_SECURITY_SELINUX) += selinux

	Unlike obj-y/m, subdir-y/m does not need the trailing slash since this
	syntax is always used for directories.

	It is good practice to use a `CONFIG_` variable when assigning directory
	names. This allows kbuild to totally skip the directory if the
	corresponding `CONFIG_` option is neither 'y' nor 'm'.

3.7 Non-builtin vmlinux targets - extra-y
-----------------------------------------

	extra-y specifies targets which are needed for building vmlinux,
	but not combined into built-in.a.

	Examples are:

	1) vmlinux linker script

	    The linker script for vmlinux is located at
	    arch/$(SRCARCH)/kernel/vmlinux.lds

	Example::

		# arch/x86/kernel/Makefile
		extra-y	+= vmlinux.lds

	$(extra-y) should only contain targets needed for vmlinux.

	Kbuild skips extra-y when vmlinux is apparently not a final goal.
	(e.g. 'make modules', or building external modules)

	If you intend to build targets unconditionally, always-y (explained
	in the next section) is the correct syntax to use.

3.8 Always built goals - always-y
---------------------------------

	always-y specifies targets which are literally always built when
	Kbuild visits the Makefile.

	Example::
	  # ./Kbuild
	  offsets-file := include/generated/asm-offsets.h
	  always-y += $(offsets-file)

3.9 Compilation flags
---------------------

    ccflags-y, asflags-y and ldflags-y
	These three flags apply only to the kbuild makefile in which they
	are assigned. They are used for all the normal cc, as and ld
	invocations happening during a recursive build.
	Note: Flags with the same behaviour were previously named:
	EXTRA_CFLAGS, EXTRA_AFLAGS and EXTRA_LDFLAGS.
	They are still supported but their usage is deprecated.

	ccflags-y specifies options for compiling with $(CC).

	Example::

		# drivers/acpi/acpica/Makefile
		ccflags-y			:= -Os -D_LINUX -DBUILDING_ACPICA
		ccflags-$(CONFIG_ACPI_DEBUG)	+= -DACPI_DEBUG_OUTPUT

	This variable is necessary because the top Makefile owns the
	variable $(KBUILD_CFLAGS) and uses it for compilation flags for the
	entire tree.

	asflags-y specifies assembler options.

	Example::

		#arch/sparc/kernel/Makefile
		asflags-y := -ansi

	ldflags-y specifies options for linking with $(LD).

	Example::

		#arch/cris/boot/compressed/Makefile
		ldflags-y += -T $(srctree)/$(src)/decompress_$(arch-y).lds

    subdir-ccflags-y, subdir-asflags-y
	The two flags listed above are similar to ccflags-y and asflags-y.
	The difference is that the subdir- variants have effect for the kbuild
	file where they are present and all subdirectories.
	Options specified using subdir-* are added to the commandline before
	the options specified using the non-subdir variants.

	Example::

		subdir-ccflags-y := -Werror

    ccflags-remove-y, asflags-remove-y
	These flags are used to remove particular flags for the compiler,
	assembler invocations.

	Example::

		ccflags-remove-$(CONFIG_MCOUNT) += -pg

    CFLAGS_$@, AFLAGS_$@
	CFLAGS_$@ and AFLAGS_$@ only apply to commands in current
	kbuild makefile.

	$(CFLAGS_$@) specifies per-file options for $(CC).  The $@
	part has a literal value which specifies the file that it is for.

	CFLAGS_$@ has the higher priority than ccflags-remove-y; CFLAGS_$@
	can re-add compiler flags that were removed by ccflags-remove-y.

	Example::

		# drivers/scsi/Makefile
		CFLAGS_aha152x.o =   -DAHA152X_STAT -DAUTOCONF

	This line specify compilation flags for aha152x.o.

	$(AFLAGS_$@) is a similar feature for source files in assembly
	languages.

	AFLAGS_$@ has the higher priority than asflags-remove-y; AFLAGS_$@
	can re-add assembler flags that were removed by asflags-remove-y.

	Example::

		# arch/arm/kernel/Makefile
		AFLAGS_head.o        := -DTEXT_OFFSET=$(TEXT_OFFSET)
		AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
		AFLAGS_iwmmxt.o      := -Wa,-mcpu=iwmmxt

3.10 Dependency tracking
------------------------

	Kbuild tracks dependencies on the following:

	1) All prerequisite files (both `*.c` and `*.h`)
	2) `CONFIG_` options used in all prerequisite files
	3) Command-line used to compile target

	Thus, if you change an option to $(CC) all affected files will
	be re-compiled.

3.11 Custom Rules
-----------------

	Custom rules are used when the kbuild infrastructure does
	not provide the required support. A typical example is
	header files generated during the build process.
	Another example are the architecture-specific Makefiles which
	need custom rules to prepare boot images etc.

	Custom rules are written as normal Make rules.
	Kbuild is not executing in the directory where the Makefile is
	located, so all custom rules shall use a relative
	path to prerequisite files and target files.

	Two variables are used when defining custom rules:

	$(src)
	    $(src) is a relative path which points to the directory
	    where the Makefile is located. Always use $(src) when
	    referring to files located in the src tree.

	$(obj)
	    $(obj) is a relative path which points to the directory
	    where the target is saved. Always use $(obj) when
	    referring to generated files.

	    Example::

		#drivers/scsi/Makefile
		$(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl
			$(CPP) -DCHIP=810 - < $< | ... $(src)/script_asm.pl

	    This is a custom rule, following the normal syntax
	    required by make.

	    The target file depends on two prerequisite files. References
	    to the target file are prefixed with $(obj), references
	    to prerequisites are referenced with $(src) (because they are not
	    generated files).

	$(kecho)
	    echoing information to user in a rule is often a good practice
	    but when execution "make -s" one does not expect to see any output
	    except for warnings/errors.
	    To support this kbuild defines $(kecho) which will echo out the
	    text following $(kecho) to stdout except if "make -s" is used.

	Example::

		# arch/arm/Makefile
		$(BOOT_TARGETS): vmlinux
			$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
			@$(kecho) '  Kernel: $(boot)/$@ is ready'

	When kbuild is executing with KBUILD_VERBOSE=0, then only a shorthand
	of a command is normally displayed.
	To enable this behaviour for custom commands kbuild requires
	two variables to be set::

		quiet_cmd_<command>	- what shall be echoed
		      cmd_<command>	- the command to execute

	Example::

		# lib/Makefile
		quiet_cmd_crc32 = GEN     $@
		      cmd_crc32 = $< > $@

		$(obj)/crc32table.h: $(obj)/gen_crc32table
			$(call cmd,crc32)

	When updating the $(obj)/crc32table.h target, the line:

		  GEN     lib/crc32table.h

	will be displayed with "make KBUILD_VERBOSE=0".

3.12 Command change detection
-----------------------------

	When the rule is evaluated, timestamps are compared between the target
	and its prerequisite files. GNU Make updates the target when any of the
	prerequisites is newer than that.

	The target should be rebuilt also when the command line has changed
	since the last invocation. This is not supported by Make itself, so
	Kbuild achieves this by a kind of meta-programming.

	if_changed is the macro used for this purpose, in the following form::

		quiet_cmd_<command> = ...
		      cmd_<command> = ...

		<target>: <source(s)> FORCE
			$(call if_changed,<command>)

	Any target that utilizes if_changed must be listed in $(targets),
	otherwise the command line check will fail, and the target will
	always be built.

	If the target is already listed in the recognized syntax such as
	obj-y/m, lib-y/m, extra-y/m, always-y/m, hostprogs, userprogs, Kbuild
	automatically adds it to $(targets). Otherwise, the target must be
	explicitly added to $(targets).

	Assignments to $(targets) are without $(obj)/ prefix. if_changed may be
	used in conjunction with custom rules as defined in "3.11 Custom Rules".

	Note: It is a typical mistake to forget the FORCE prerequisite.
	Another common pitfall is that whitespace is sometimes significant; for
	instance, the below will fail (note the extra space after the comma)::

		target: source(s) FORCE

	**WRONG!**	$(call if_changed, objcopy)

	Note:
		if_changed should not be used more than once per target.
		It stores the executed command in a corresponding .cmd
		file and multiple calls would result in overwrites and
		unwanted results when the target is up to date and only the
		tests on changed commands trigger execution of commands.

3.13 $(CC) support functions
----------------------------

	The kernel may be built with several different versions of
	$(CC), each supporting a unique set of features and options.
	kbuild provides basic support to check for valid options for $(CC).
	$(CC) is usually the gcc compiler, but other alternatives are
	available.

    as-option
	as-option is used to check if $(CC) -- when used to compile
	assembler (`*.S`) files -- supports the given option. An optional
	second option may be specified if the first option is not supported.

	Example::

		#arch/sh/Makefile
		cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),)

	In the above example, cflags-y will be assigned the option
	-Wa$(comma)-isa=$(isa-y) if it is supported by $(CC).
	The second argument is optional, and if supplied will be used
	if first argument is not supported.

    as-instr
	as-instr checks if the assembler reports a specific instruction
	and then outputs either option1 or option2
	C escapes are supported in the test instruction
	Note: as-instr-option uses KBUILD_AFLAGS for assembler options

    cc-option
	cc-option is used to check if $(CC) supports a given option, and if
	not supported to use an optional second option.

	Example::

		#arch/x86/Makefile
		cflags-y += $(call cc-option,-march=pentium-mmx,-march=i586)

	In the above example, cflags-y will be assigned the option
	-march=pentium-mmx if supported by $(CC), otherwise -march=i586.
	The second argument to cc-option is optional, and if omitted,
	cflags-y will be assigned no value if first option is not supported.
	Note: cc-option uses KBUILD_CFLAGS for $(CC) options

   cc-option-yn
	cc-option-yn is used to check if gcc supports a given option
	and return 'y' if supported, otherwise 'n'.

	Example::

		#arch/ppc/Makefile
		biarch := $(call cc-option-yn, -m32)
		aflags-$(biarch) += -a32
		cflags-$(biarch) += -m32

	In the above example, $(biarch) is set to y if $(CC) supports the -m32
	option. When $(biarch) equals 'y', the expanded variables $(aflags-y)
	and $(cflags-y) will be assigned the values -a32 and -m32,
	respectively.
	Note: cc-option-yn uses KBUILD_CFLAGS for $(CC) options

    cc-disable-warning
	cc-disable-warning checks if gcc supports a given warning and returns
	the commandline switch to disable it. This special function is needed,
	because gcc 4.4 and later accept any unknown -Wno-* option and only
	warn about it if there is another warning in the source file.

	Example::

		KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable)

	In the above example, -Wno-unused-but-set-variable will be added to
	KBUILD_CFLAGS only if gcc really accepts it.

    gcc-min-version
	gcc-min-version tests if the value of $(CONFIG_GCC_VERSION) is greater than
	or equal to the provided value and evaluates to y if so.

	Example::

		cflags-$(call gcc-min-version, 70100) := -foo

	In this example, cflags-y will be assigned the value -foo if $(CC) is gcc and
	$(CONFIG_GCC_VERSION) is >= 7.1.

    clang-min-version
	clang-min-version tests if the value of $(CONFIG_CLANG_VERSION) is greater
	than or equal to the provided value and evaluates to y if so.

	Example::

		cflags-$(call clang-min-version, 110000) := -foo

	In this example, cflags-y will be assigned the value -foo if $(CC) is clang
	and $(CONFIG_CLANG_VERSION) is >= 11.0.0.

    cc-cross-prefix
	cc-cross-prefix is used to check if there exists a $(CC) in path with
	one of the listed prefixes. The first prefix where there exist a
	prefix$(CC) in the PATH is returned - and if no prefix$(CC) is found
	then nothing is returned.
	Additional prefixes are separated by a single space in the
	call of cc-cross-prefix.
	This functionality is useful for architecture Makefiles that try
	to set CROSS_COMPILE to well-known values but may have several
	values to select between.
	It is recommended only to try to set CROSS_COMPILE if it is a cross
	build (host arch is different from target arch). And if CROSS_COMPILE
	is already set then leave it with the old value.

	Example::

		#arch/m68k/Makefile
		ifneq ($(SUBARCH),$(ARCH))
		        ifeq ($(CROSS_COMPILE),)
		               CROSS_COMPILE := $(call cc-cross-prefix, m68k-linux-gnu-)
			endif
		endif

3.14 $(LD) support functions
----------------------------

    ld-option
	ld-option is used to check if $(LD) supports the supplied option.
	ld-option takes two options as arguments.
	The second argument is an optional option that can be used if the
	first option is not supported by $(LD).

	Example::

		#Makefile
		LDFLAGS_vmlinux += $(call ld-option, -X)

3.15 Script invocation
----------------------

	Make rules may invoke scripts to build the kernel. The rules shall
	always provide the appropriate interpreter to execute the script. They
	shall not rely on the execute bits being set, and shall not invoke the
	script directly. For the convenience of manual script invocation, such
	as invoking ./scripts/checkpatch.pl, it is recommended to set execute
	bits on the scripts nonetheless.

	Kbuild provides variables $(CONFIG_SHELL), $(AWK), $(PERL),
	and $(PYTHON3) to refer to interpreters for the respective
	scripts.

	Example::

		#Makefile
		cmd_depmod = $(CONFIG_SHELL) $(srctree)/scripts/depmod.sh $(DEPMOD) \
			     $(KERNELRELEASE)

4 Host Program support
======================

Kbuild supports building executables on the host for use during the
compilation stage.
Two steps are required in order to use a host executable.

The first step is to tell kbuild that a host program exists. This is
done utilising the variable "hostprogs".

The second step is to add an explicit dependency to the executable.
This can be done in two ways. Either add the dependency in a rule,
or utilise the variable "always-y".
Both possibilities are described in the following.

4.1 Simple Host Program
-----------------------

	In some cases there is a need to compile and run a program on the
	computer where the build is running.
	The following line tells kbuild that the program bin2hex shall be
	built on the build host.

	Example::

		hostprogs := bin2hex

	Kbuild assumes in the above example that bin2hex is made from a single
	c-source file named bin2hex.c located in the same directory as
	the Makefile.

4.2 Composite Host Programs
---------------------------

	Host programs can be made up based on composite objects.
	The syntax used to define composite objects for host programs is
	similar to the syntax used for kernel objects.
	$(<executable>-objs) lists all objects used to link the final
	executable.

	Example::

		#scripts/lxdialog/Makefile
		hostprogs     := lxdialog
		lxdialog-objs := checklist.o lxdialog.o

	Objects with extension .o are compiled from the corresponding .c
	files. In the above example, checklist.c is compiled to checklist.o
	and lxdialog.c is compiled to lxdialog.o.

	Finally, the two .o files are linked to the executable, lxdialog.
	Note: The syntax <executable>-y is not permitted for host-programs.

4.3 Using C++ for host programs
-------------------------------

	kbuild offers support for host programs written in C++. This was
	introduced solely to support kconfig, and is not recommended
	for general use.

	Example::

		#scripts/kconfig/Makefile
		hostprogs     := qconf
		qconf-cxxobjs := qconf.o

	In the example above the executable is composed of the C++ file
	qconf.cc - identified by $(qconf-cxxobjs).

	If qconf is composed of a mixture of .c and .cc files, then an
	additional line can be used to identify this.

	Example::

		#scripts/kconfig/Makefile
		hostprogs     := qconf
		qconf-cxxobjs := qconf.o
		qconf-objs    := check.o

4.4 Using Rust for host programs
--------------------------------

	Kbuild offers support for host programs written in Rust. However,
	since a Rust toolchain is not mandatory for kernel compilation,
	it may only be used in scenarios where Rust is required to be
	available (e.g. when  ``CONFIG_RUST`` is enabled).

	Example::

		hostprogs     := target
		target-rust   := y

	Kbuild will compile ``target`` using ``target.rs`` as the crate root,
	located in the same directory as the ``Makefile``. The crate may
	consist of several source files (see ``samples/rust/hostprogs``).

4.5 Controlling compiler options for host programs
--------------------------------------------------

	When compiling host programs, it is possible to set specific flags.
	The programs will always be compiled utilising $(HOSTCC) passed
	the options specified in $(KBUILD_HOSTCFLAGS).
	To set flags that will take effect for all host programs created
	in that Makefile, use the variable HOST_EXTRACFLAGS.

	Example::

		#scripts/lxdialog/Makefile
		HOST_EXTRACFLAGS += -I/usr/include/ncurses

	To set specific flags for a single file the following construction
	is used:

	Example::

		#arch/ppc64/boot/Makefile
		HOSTCFLAGS_piggyback.o := -DKERNELBASE=$(KERNELBASE)

	It is also possible to specify additional options to the linker.

	Example::

		#scripts/kconfig/Makefile
		HOSTLDLIBS_qconf := -L$(QTDIR)/lib

	When linking qconf, it will be passed the extra option
	"-L$(QTDIR)/lib".

4.6 When host programs are actually built
-----------------------------------------

	Kbuild will only build host-programs when they are referenced
	as a prerequisite.
	This is possible in two ways:

	(1) List the prerequisite explicitly in a custom rule.

	Example::

		#drivers/pci/Makefile
		hostprogs := gen-devlist
		$(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
			( cd $(obj); ./gen-devlist ) < $<

	The target $(obj)/devlist.h will not be built before
	$(obj)/gen-devlist is updated. Note that references to
	the host programs in custom rules must be prefixed with $(obj).

	(2) Use always-y

	When there is no suitable custom rule, and the host program
	shall be built when a makefile is entered, the always-y
	variable shall be used.

	Example::

		#scripts/lxdialog/Makefile
		hostprogs     := lxdialog
		always-y      := $(hostprogs)

	Kbuild provides the following shorthand for this:

		hostprogs-always-y := lxdialog

	This will tell kbuild to build lxdialog even if not referenced in
	any rule.

5 Userspace Program support
===========================

Just like host programs, Kbuild also supports building userspace executables
for the target architecture (i.e. the same architecture as you are building
the kernel for).

The syntax is quite similar. The difference is to use "userprogs" instead of
"hostprogs".

5.1 Simple Userspace Program
----------------------------

	The following line tells kbuild that the program bpf-direct shall be
	built for the target architecture.

	Example::

		userprogs := bpf-direct

	Kbuild assumes in the above example that bpf-direct is made from a
	single C source file named bpf-direct.c located in the same directory
	as the Makefile.

5.2 Composite Userspace Programs
--------------------------------

	Userspace programs can be made up based on composite objects.
	The syntax used to define composite objects for userspace programs is
	similar to the syntax used for kernel objects.
	$(<executable>-objs) lists all objects used to link the final
	executable.

	Example::

		#samples/seccomp/Makefile
		userprogs      := bpf-fancy
		bpf-fancy-objs := bpf-fancy.o bpf-helper.o

	Objects with extension .o are compiled from the corresponding .c
	files. In the above example, bpf-fancy.c is compiled to bpf-fancy.o
	and bpf-helper.c is compiled to bpf-helper.o.

	Finally, the two .o files are linked to the executable, bpf-fancy.
	Note: The syntax <executable>-y is not permitted for userspace programs.

5.3 Controlling compiler options for userspace programs
-------------------------------------------------------

	When compiling userspace programs, it is possible to set specific flags.
	The programs will always be compiled utilising $(CC) passed
	the options specified in $(KBUILD_USERCFLAGS).
	To set flags that will take effect for all userspace programs created
	in that Makefile, use the variable userccflags.

	Example::

		# samples/seccomp/Makefile
		userccflags += -I usr/include

	To set specific flags for a single file the following construction
	is used:

	Example::

		bpf-helper-userccflags += -I user/include

	It is also possible to specify additional options to the linker.

	Example::

		# net/bpfilter/Makefile
		bpfilter_umh-userldflags += -static

	When linking bpfilter_umh, it will be passed the extra option -static.

	From command line, :ref:`USERCFLAGS and USERLDFLAGS <userkbuildflags>` will also be used.

5.4 When userspace programs are actually built
----------------------------------------------

	Kbuild builds userspace programs only when told to do so.
	There are two ways to do this.

	(1) Add it as the prerequisite of another file

	Example::

		#net/bpfilter/Makefile
		userprogs := bpfilter_umh
		$(obj)/bpfilter_umh_blob.o: $(obj)/bpfilter_umh

	$(obj)/bpfilter_umh is built before $(obj)/bpfilter_umh_blob.o

	(2) Use always-y

	Example::

		userprogs := binderfs_example
		always-y := $(userprogs)

	Kbuild provides the following shorthand for this:

		userprogs-always-y := binderfs_example

	This will tell Kbuild to build binderfs_example when it visits this
	Makefile.

6 Kbuild clean infrastructure
=============================

"make clean" deletes most generated files in the obj tree where the kernel
is compiled. This includes generated files such as host programs.
Kbuild knows targets listed in $(hostprogs), $(always-y), $(always-m),
$(always-), $(extra-y), $(extra-) and $(targets). They are all deleted
during "make clean". Files matching the patterns "*.[oas]", "*.ko", plus
some additional files generated by kbuild are deleted all over the kernel
source tree when "make clean" is executed.

Additional files or directories can be specified in kbuild makefiles by use of
$(clean-files).

	Example::

		#lib/Makefile
		clean-files := crc32table.h

When executing "make clean", the file "crc32table.h" will be deleted.
Kbuild will assume files to be in the same relative directory as the
Makefile, except if prefixed with $(objtree).

To exclude certain files or directories from make clean, use the
$(no-clean-files) variable.

Usually kbuild descends down in subdirectories due to "obj-* := dir/",
but in the architecture makefiles where the kbuild infrastructure
is not sufficient this sometimes needs to be explicit.

	Example::

		#arch/x86/boot/Makefile
		subdir- := compressed

The above assignment instructs kbuild to descend down in the
directory compressed/ when "make clean" is executed.

Note 1: arch/$(SRCARCH)/Makefile cannot use "subdir-", because that file is
included in the top level makefile. Instead, arch/$(SRCARCH)/Kbuild can use
"subdir-".

Note 2: All directories listed in core-y, libs-y, drivers-y and net-y will
be visited during "make clean".

7 Architecture Makefiles
========================

The top level Makefile sets up the environment and does the preparation,
before starting to descend down in the individual directories.
The top level makefile contains the generic part, whereas
arch/$(SRCARCH)/Makefile contains what is required to set up kbuild
for said architecture.
To do so, arch/$(SRCARCH)/Makefile sets up a number of variables and defines
a few targets.

When kbuild executes, the following steps are followed (roughly):

1) Configuration of the kernel => produce .config
2) Store kernel version in include/linux/version.h
3) Updating all other prerequisites to the target prepare:
   - Additional prerequisites are specified in arch/$(SRCARCH)/Makefile
4) Recursively descend down in all directories listed in
   init-* core* drivers-* net-* libs-* and build all targets.
   - The values of the above variables are expanded in arch/$(SRCARCH)/Makefile.
5) All object files are then linked and the resulting file vmlinux is
   located at the root of the obj tree.
   The very first objects linked are listed in scripts/head-object-list.txt.
6) Finally, the architecture-specific part does any required post processing
   and builds the final bootimage.
   - This includes building boot records
   - Preparing initrd images and the like

7.1 Set variables to tweak the build to the architecture
--------------------------------------------------------

    KBUILD_LDFLAGS
	Generic $(LD) options

	Flags used for all invocations of the linker.
	Often specifying the emulation is sufficient.

	Example::

		#arch/s390/Makefile
		KBUILD_LDFLAGS         := -m elf_s390

	Note: ldflags-y can be used to further customise
	the flags used. See section 3.7.

    LDFLAGS_vmlinux
	Options for $(LD) when linking vmlinux

	LDFLAGS_vmlinux is used to specify additional flags to pass to
	the linker when linking the final vmlinux image.
	LDFLAGS_vmlinux uses the LDFLAGS_$@ support.

	Example::

		#arch/x86/Makefile
		LDFLAGS_vmlinux := -e stext

    OBJCOPYFLAGS
	objcopy flags

	When $(call if_changed,objcopy) is used to translate a .o file,
	the flags specified in OBJCOPYFLAGS will be used.
	$(call if_changed,objcopy) is often used to generate raw binaries on
	vmlinux.

	Example::

		#arch/s390/Makefile
		OBJCOPYFLAGS := -O binary

		#arch/s390/boot/Makefile
		$(obj)/image: vmlinux FORCE
			$(call if_changed,objcopy)

	In this example, the binary $(obj)/image is a binary version of
	vmlinux. The usage of $(call if_changed,xxx) will be described later.

    KBUILD_AFLAGS
	Assembler flags

	Default value - see top level Makefile
	Append or modify as required per architecture.

	Example::

		#arch/sparc64/Makefile
		KBUILD_AFLAGS += -m64 -mcpu=ultrasparc

    KBUILD_CFLAGS
	$(CC) compiler flags

	Default value - see top level Makefile
	Append or modify as required per architecture.

	Often, the KBUILD_CFLAGS variable depends on the configuration.

	Example::

		#arch/x86/boot/compressed/Makefile
		cflags-$(CONFIG_X86_32) := -march=i386
		cflags-$(CONFIG_X86_64) := -mcmodel=small
		KBUILD_CFLAGS += $(cflags-y)

	Many arch Makefiles dynamically run the target C compiler to
	probe supported options::

		#arch/x86/Makefile

		...
		cflags-$(CONFIG_MPENTIUMII)     += $(call cc-option,\
						-march=pentium2,-march=i686)
		...
		# Disable unit-at-a-time mode ...
		KBUILD_CFLAGS += $(call cc-option,-fno-unit-at-a-time)
		...

	The first example utilises the trick that a config option expands
	to 'y' when selected.

    KBUILD_RUSTFLAGS
	$(RUSTC) compiler flags

	Default value - see top level Makefile
	Append or modify as required per architecture.

	Often, the KBUILD_RUSTFLAGS variable depends on the configuration.

	Note that target specification file generation (for ``--target``)
	is handled in ``scripts/generate_rust_target.rs``.

    KBUILD_AFLAGS_KERNEL
	Assembler options specific for built-in

	$(KBUILD_AFLAGS_KERNEL) contains extra C compiler flags used to compile
	resident kernel code.

    KBUILD_AFLAGS_MODULE
	Assembler options specific for modules

	$(KBUILD_AFLAGS_MODULE) is used to add arch-specific options that
	are used for assembler.

	From commandline AFLAGS_MODULE shall be used (see kbuild.rst).

    KBUILD_CFLAGS_KERNEL
	$(CC) options specific for built-in

	$(KBUILD_CFLAGS_KERNEL) contains extra C compiler flags used to compile
	resident kernel code.

    KBUILD_CFLAGS_MODULE
	Options for $(CC) when building modules

	$(KBUILD_CFLAGS_MODULE) is used to add arch-specific options that
	are used for $(CC).
	From commandline CFLAGS_MODULE shall be used (see kbuild.rst).

    KBUILD_RUSTFLAGS_KERNEL
	$(RUSTC) options specific for built-in

	$(KBUILD_RUSTFLAGS_KERNEL) contains extra Rust compiler flags used to
	compile resident kernel code.

    KBUILD_RUSTFLAGS_MODULE
	Options for $(RUSTC) when building modules

	$(KBUILD_RUSTFLAGS_MODULE) is used to add arch-specific options that
	are used for $(RUSTC).
	From commandline RUSTFLAGS_MODULE shall be used (see kbuild.rst).

    KBUILD_LDFLAGS_MODULE
	Options for $(LD) when linking modules

	$(KBUILD_LDFLAGS_MODULE) is used to add arch-specific options
	used when linking modules. This is often a linker script.

	From commandline LDFLAGS_MODULE shall be used (see kbuild.rst).

    KBUILD_LDS

	The linker script with full path. Assigned by the top-level Makefile.

    KBUILD_LDS_MODULE

	The module linker script with full path. Assigned by the top-level
	Makefile and additionally by the arch Makefile.

    KBUILD_VMLINUX_OBJS

	All object files for vmlinux. They are linked to vmlinux in the same
	order as listed in KBUILD_VMLINUX_OBJS.

	The objects listed in scripts/head-object-list.txt are exceptions;
	they are placed before the other objects.

    KBUILD_VMLINUX_LIBS

	All .a "lib" files for vmlinux. KBUILD_VMLINUX_OBJS and
	KBUILD_VMLINUX_LIBS together specify all the object files used to
	link vmlinux.

7.2 Add prerequisites to archheaders
------------------------------------

	The archheaders: rule is used to generate header files that
	may be installed into user space by "make header_install".

	It is run before "make archprepare" when run on the
	architecture itself.

7.3 Add prerequisites to archprepare
------------------------------------

	The archprepare: rule is used to list prerequisites that need to be
	built before starting to descend down in the subdirectories.
	This is usually used for header files containing assembler constants.

	Example::

		#arch/arm/Makefile
		archprepare: maketools

	In this example, the file target maketools will be processed
	before descending down in the subdirectories.
	See also chapter XXX-TODO that describes how kbuild supports
	generating offset header files.

7.4 List directories to visit when descending
---------------------------------------------

	An arch Makefile cooperates with the top Makefile to define variables
	which specify how to build the vmlinux file.  Note that there is no
	corresponding arch-specific section for modules; the module-building
	machinery is all architecture-independent.

	core-y, libs-y, drivers-y

	    $(libs-y) lists directories where a lib.a archive can be located.

	    The rest list directories where a built-in.a object file can be
	    located.

	    Then the rest follows in this order:

		$(core-y), $(libs-y), $(drivers-y)

	    The top level Makefile defines values for all generic directories,
	    and arch/$(SRCARCH)/Makefile only adds architecture-specific
	    directories.

	    Example::

		# arch/sparc/Makefile
		core-y                 += arch/sparc/

		libs-y                 += arch/sparc/prom/
		libs-y                 += arch/sparc/lib/

		drivers-$(CONFIG_PM) += arch/sparc/power/

7.5 Architecture-specific boot images
-------------------------------------

	An arch Makefile specifies goals that take the vmlinux file, compress
	it, wrap it in bootstrapping code, and copy the resulting files
	somewhere. This includes various kinds of installation commands.
	The actual goals are not standardized across architectures.

	It is common to locate any additional processing in a boot/
	directory below arch/$(SRCARCH)/.

	Kbuild does not provide any smart way to support building a
	target specified in boot/. Therefore arch/$(SRCARCH)/Makefile shall
	call make manually to build a target in boot/.

	The recommended approach is to include shortcuts in
	arch/$(SRCARCH)/Makefile, and use the full path when calling down
	into the arch/$(SRCARCH)/boot/Makefile.

	Example::

		#arch/x86/Makefile
		boot := arch/x86/boot
		bzImage: vmlinux
			$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@

	"$(Q)$(MAKE) $(build)=<dir>" is the recommended way to invoke
	make in a subdirectory.

	There are no rules for naming architecture-specific targets,
	but executing "make help" will list all relevant targets.
	To support this, $(archhelp) must be defined.

	Example::

		#arch/x86/Makefile
		define archhelp
		  echo  '* bzImage      - Compressed kernel image (arch/x86/boot/bzImage)'
		endif

	When make is executed without arguments, the first goal encountered
	will be built. In the top level Makefile the first goal present
	is all:.
	An architecture shall always, per default, build a bootable image.
	In "make help", the default goal is highlighted with a '*'.
	Add a new prerequisite to all: to select a default goal different
	from vmlinux.

	Example::

		#arch/x86/Makefile
		all: bzImage

	When "make" is executed without arguments, bzImage will be built.

7.7 Commands useful for building a boot image
---------------------------------------------

    Kbuild provides a few macros that are useful when building a
    boot image.

    ld
	Link target. Often, LDFLAGS_$@ is used to set specific options to ld.

	Example::

		#arch/x86/boot/Makefile
		LDFLAGS_bootsect := -Ttext 0x0 -s --oformat binary
		LDFLAGS_setup    := -Ttext 0x0 -s --oformat binary -e begtext

		targets += setup setup.o bootsect bootsect.o
		$(obj)/setup $(obj)/bootsect: %: %.o FORCE
			$(call if_changed,ld)

	In this example, there are two possible targets, requiring different
	options to the linker. The linker options are specified using the
	LDFLAGS_$@ syntax - one for each potential target.
	$(targets) are assigned all potential targets, by which kbuild knows
	the targets and will:

		1) check for commandline changes
		2) delete target during make clean

	The ": %: %.o" part of the prerequisite is a shorthand that
	frees us from listing the setup.o and bootsect.o files.

	Note:
	      It is a common mistake to forget the "targets :=" assignment,
	      resulting in the target file being recompiled for no
	      obvious reason.

    objcopy
	Copy binary. Uses OBJCOPYFLAGS usually specified in
	arch/$(SRCARCH)/Makefile.
	OBJCOPYFLAGS_$@ may be used to set additional options.

    gzip
	Compress target. Use maximum compression to compress target.

	Example::

		#arch/x86/boot/compressed/Makefile
		$(obj)/vmlinux.bin.gz: $(vmlinux.bin.all-y) FORCE
			$(call if_changed,gzip)

    dtc
	Create flattened device tree blob object suitable for linking
	into vmlinux. Device tree blobs linked into vmlinux are placed
	in an init section in the image. Platform code *must* copy the
	blob to non-init memory prior to calling unflatten_device_tree().

	To use this command, simply add `*.dtb` into obj-y or targets, or make
	some other target depend on `%.dtb`

	A central rule exists to create `$(obj)/%.dtb` from `$(src)/%.dts`;
	architecture Makefiles do no need to explicitly write out that rule.

	Example::

		targets += $(dtb-y)
		DTC_FLAGS ?= -p 1024

7.9 Preprocessing linker scripts
--------------------------------

	When the vmlinux image is built, the linker script
	arch/$(SRCARCH)/kernel/vmlinux.lds is used.
	The script is a preprocessed variant of the file vmlinux.lds.S
	located in the same directory.
	kbuild knows .lds files and includes a rule `*lds.S` -> `*lds`.

	Example::

		#arch/x86/kernel/Makefile
		extra-y := vmlinux.lds

	The assignment to extra-y is used to tell kbuild to build the
	target vmlinux.lds.
	The assignment to $(CPPFLAGS_vmlinux.lds) tells kbuild to use the
	specified options when building the target vmlinux.lds.

	When building the `*.lds` target, kbuild uses the variables::

		KBUILD_CPPFLAGS	: Set in top-level Makefile
		cppflags-y	: May be set in the kbuild makefile
		CPPFLAGS_$(@F)  : Target-specific flags.
				Note that the full filename is used in this
				assignment.

	The kbuild infrastructure for `*lds` files is used in several
	architecture-specific files.

7.10 Generic header files
-------------------------

	The directory include/asm-generic contains the header files
	that may be shared between individual architectures.
	The recommended approach how to use a generic header file is
	to list the file in the Kbuild file.
	See "8.2 generic-y" for further info on syntax etc.

7.11 Post-link pass
-------------------

	If the file arch/xxx/Makefile.postlink exists, this makefile
	will be invoked for post-link objects (vmlinux and modules.ko)
	for architectures to run post-link passes on. Must also handle
	the clean target.

	This pass runs after kallsyms generation. If the architecture
	needs to modify symbol locations, rather than manipulate the
	kallsyms, it may be easier to add another postlink target for
	.tmp_vmlinux? targets to be called from link-vmlinux.sh.

	For example, powerpc uses this to check relocation sanity of
	the linked vmlinux file.

8 Kbuild syntax for exported headers
------------------------------------

The kernel includes a set of headers that is exported to userspace.
Many headers can be exported as-is but other headers require a
minimal pre-processing before they are ready for user-space.
The pre-processing does:

- drop kernel-specific annotations
- drop include of compiler.h
- drop all sections that are kernel internal (guarded by `ifdef __KERNEL__`)

All headers under include/uapi/, include/generated/uapi/,
arch/<arch>/include/uapi/ and arch/<arch>/include/generated/uapi/
are exported.

A Kbuild file may be defined under arch/<arch>/include/uapi/asm/ and
arch/<arch>/include/asm/ to list asm files coming from asm-generic.
See subsequent chapter for the syntax of the Kbuild file.

8.1 no-export-headers
---------------------

	no-export-headers is essentially used by include/uapi/linux/Kbuild to
	avoid exporting specific headers (e.g. kvm.h) on architectures that do
	not support it. It should be avoided as much as possible.

8.2 generic-y
-------------

	If an architecture uses a verbatim copy of a header from
	include/asm-generic then this is listed in the file
	arch/$(SRCARCH)/include/asm/Kbuild like this:

		Example::

			#arch/x86/include/asm/Kbuild
			generic-y += termios.h
			generic-y += rtc.h

	During the prepare phase of the build a wrapper include
	file is generated in the directory::

		arch/$(SRCARCH)/include/generated/asm

	When a header is exported where the architecture uses
	the generic header a similar wrapper is generated as part
	of the set of exported headers in the directory::

		usr/include/asm

	The generated wrapper will in both cases look like the following:

		Example: termios.h::

			#include <asm-generic/termios.h>

8.3 generated-y
---------------

	If an architecture generates other header files alongside generic-y
	wrappers, generated-y specifies them.

	This prevents them being treated as stale asm-generic wrappers and
	removed.

		Example::

			#arch/x86/include/asm/Kbuild
			generated-y += syscalls_32.h

8.4 mandatory-y
---------------

	mandatory-y is essentially used by include/(uapi/)asm-generic/Kbuild
	to define the minimum set of ASM headers that all architectures must have.

	This works like optional generic-y. If a mandatory header is missing
	in arch/$(SRCARCH)/include/(uapi/)/asm, Kbuild will automatically
	generate a wrapper of the asm-generic one.

9 Kbuild Variables
==================

The top Makefile exports the following variables:

    VERSION, PATCHLEVEL, SUBLEVEL, EXTRAVERSION
	These variables define the current kernel version.  A few arch
	Makefiles actually use these values directly; they should use
	$(KERNELRELEASE) instead.

	$(VERSION), $(PATCHLEVEL), and $(SUBLEVEL) define the basic
	three-part version number, such as "2", "4", and "0".  These three
	values are always numeric.

	$(EXTRAVERSION) defines an even tinier sublevel for pre-patches
	or additional patches.	It is usually some non-numeric string
	such as "-pre4", and is often blank.

    KERNELRELEASE
	$(KERNELRELEASE) is a single string such as "2.4.0-pre4", suitable
	for constructing installation directory names or showing in
	version strings.  Some arch Makefiles use it for this purpose.

    ARCH
	This variable defines the target architecture, such as "i386",
	"arm", or "sparc". Some kbuild Makefiles test $(ARCH) to
	determine which files to compile.

	By default, the top Makefile sets $(ARCH) to be the same as the
	host system architecture.  For a cross build, a user may
	override the value of $(ARCH) on the command line::

	    make ARCH=m68k ...

    SRCARCH
	This variable specifies the directory in arch/ to build.

	ARCH and SRCARCH may not necessarily match. A couple of arch
	directories are biarch, that is, a single `arch/*/` directory supports
	both 32-bit and 64-bit.

	For example, you can pass in ARCH=i386, ARCH=x86_64, or ARCH=x86.
	For all of them, SRCARCH=x86 because arch/x86/ supports	both i386 and
	x86_64.

    INSTALL_PATH
	This variable defines a place for the arch Makefiles to install
	the resident kernel image and System.map file.
	Use this for architecture-specific install targets.

    INSTALL_MOD_PATH, MODLIB
	$(INSTALL_MOD_PATH) specifies a prefix to $(MODLIB) for module
	installation.  This variable is not defined in the Makefile but
	may be passed in by the user if desired.

	$(MODLIB) specifies the directory for module installation.
	The top Makefile defines $(MODLIB) to
	$(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE).  The user may
	override this value on the command line if desired.

    INSTALL_MOD_STRIP
	If this variable is specified, it will cause modules to be stripped
	after they are installed.  If INSTALL_MOD_STRIP is '1', then the
	default option --strip-debug will be used.  Otherwise, the
	INSTALL_MOD_STRIP value will be used as the option(s) to the strip
	command.

10 Makefile language
====================

The kernel Makefiles are designed to be run with GNU Make.  The Makefiles
use only the documented features of GNU Make, but they do use many
GNU extensions.

GNU Make supports elementary list-processing functions.  The kernel
Makefiles use a novel style of list building and manipulation with few
"if" statements.

GNU Make has two assignment operators, ":=" and "=".  ":=" performs
immediate evaluation of the right-hand side and stores an actual string
into the left-hand side.  "=" is like a formula definition; it stores the
right-hand side in an unevaluated form and then evaluates this form each
time the left-hand side is used.

There are some cases where "=" is appropriate.  Usually, though, ":="
is the right choice.

11 Credits
==========

- Original version made by Michael Elizabeth Chastain, <mailto:mec@shout.net>
- Updates by Kai Germaschewski <kai@tp1.ruhr-uni-bochum.de>
- Updates by Sam Ravnborg <sam@ravnborg.org>
- Language QA by Jan Engelhardt <jengelh@gmx.de>

12 TODO
=======

- Describe how kbuild supports shipped files with _shipped.
- Generating offset header files.
- Add more variables to chapters 7 or 9?


code:
=========================
Building External Modules
=========================

This document describes how to build an out-of-tree kernel module.

.. Table of Contents

	=== 1 Introduction
	=== 2 How to Build External Modules
	   --- 2.1 Command Syntax
	   --- 2.2 Options
	   --- 2.3 Targets
	   --- 2.4 Building Separate Files
	=== 3. Creating a Kbuild File for an External Module
	   --- 3.1 Shared Makefile
	   --- 3.2 Separate Kbuild file and Makefile
	   --- 3.3 Binary Blobs
	   --- 3.4 Building Multiple Modules
	=== 4. Include Files
	   --- 4.1 Kernel Includes
	   --- 4.2 Single Subdirectory
	   --- 4.3 Several Subdirectories
	=== 5. Module Installation
	   --- 5.1 INSTALL_MOD_PATH
	   --- 5.2 INSTALL_MOD_DIR
	=== 6. Module Versioning
	   --- 6.1 Symbols From the Kernel (vmlinux + modules)
	   --- 6.2 Symbols and External Modules
	   --- 6.3 Symbols From Another External Module
	=== 7. Tips & Tricks
	   --- 7.1 Testing for CONFIG_FOO_BAR

1. Introduction
===============

"kbuild" is the build system used by the Linux kernel. Modules must use
kbuild to stay compatible with changes in the build infrastructure and
to pick up the right flags to "gcc." Functionality for building modules
both in-tree and out-of-tree is provided. The method for building
either is similar, and all modules are initially developed and built
out-of-tree.

Covered in this document is information aimed at developers interested
in building out-of-tree (or "external") modules. The author of an
external module should supply a makefile that hides most of the
complexity, so one only has to type "make" to build the module. This is
easily accomplished, and a complete example will be presented in
section 3.

2. How to Build External Modules
================================

To build external modules, you must have a prebuilt kernel available
that contains the configuration and header files used in the build.
Also, the kernel must have been built with modules enabled. If you are
using a distribution kernel, there will be a package for the kernel you
are running provided by your distribution.

An alternative is to use the "make" target "modules_prepare." This will
make sure the kernel contains the information required. The target
exists solely as a simple way to prepare a kernel source tree for
building external modules.

NOTE: "modules_prepare" will not build Module.symvers even if
CONFIG_MODVERSIONS is set; therefore, a full kernel build needs to be
executed to make module versioning work.

2.1 Command Syntax
==================

	The command to build an external module is::

		$ make -C <path_to_kernel_src> M=$PWD

	The kbuild system knows that an external module is being built
	due to the "M=<dir>" option given in the command.

	To build against the running kernel use::

		$ make -C /lib/modules/`uname -r`/build M=$PWD

	Then to install the module(s) just built, add the target
	"modules_install" to the command::

		$ make -C /lib/modules/`uname -r`/build M=$PWD modules_install

2.2 Options
===========

	($KDIR refers to the path of the kernel source directory.)

	make -C $KDIR M=$PWD

	-C $KDIR
		The directory where the kernel source is located.
		"make" will actually change to the specified directory
		when executing and will change back when finished.

	M=$PWD
		Informs kbuild that an external module is being built.
		The value given to "M" is the absolute path of the
		directory where the external module (kbuild file) is
		located.

2.3 Targets
===========

	When building an external module, only a subset of the "make"
	targets are available.

	make -C $KDIR M=$PWD [target]

	The default will build the module(s) located in the current
	directory, so a target does not need to be specified. All
	output files will also be generated in this directory. No
	attempts are made to update the kernel source, and it is a
	precondition that a successful "make" has been executed for the
	kernel.

	modules
		The default target for external modules. It has the
		same functionality as if no target was specified. See
		description above.

	modules_install
		Install the external module(s). The default location is
		/lib/modules/<kernel_release>/extra/, but a prefix may
		be added with INSTALL_MOD_PATH (discussed in section 5).

	clean
		Remove all generated files in the module directory only.

	help
		List the available targets for external modules.

2.4 Building Separate Files
===========================

	It is possible to build single files that are part of a module.
	This works equally well for the kernel, a module, and even for
	external modules.

	Example (The module foo.ko, consist of bar.o and baz.o)::

		make -C $KDIR M=$PWD bar.lst
		make -C $KDIR M=$PWD baz.o
		make -C $KDIR M=$PWD foo.ko
		make -C $KDIR M=$PWD ./

3. Creating a Kbuild File for an External Module
================================================

In the last section we saw the command to build a module for the
running kernel. The module is not actually built, however, because a
build file is required. Contained in this file will be the name of
the module(s) being built, along with the list of requisite source
files. The file may be as simple as a single line::

	obj-m := <module_name>.o

The kbuild system will build <module_name>.o from <module_name>.c,
and, after linking, will result in the kernel module <module_name>.ko.
The above line can be put in either a "Kbuild" file or a "Makefile."
When the module is built from multiple sources, an additional line is
needed listing the files::

	<module_name>-y := <src1>.o <src2>.o ...

NOTE: Further documentation describing the syntax used by kbuild is
located in Documentation/kbuild/makefiles.rst.

The examples below demonstrate how to create a build file for the
module 8123.ko, which is built from the following files::

	8123_if.c
	8123_if.h
	8123_pci.c
	8123_bin.o_shipped	<= Binary blob

3.1 Shared Makefile
-------------------

	An external module always includes a wrapper makefile that
	supports building the module using "make" with no arguments.
	This target is not used by kbuild; it is only for convenience.
	Additional functionality, such as test targets, can be included
	but should be filtered out from kbuild due to possible name
	clashes.

	Example 1::

		--> filename: Makefile
		ifneq ($(KERNELRELEASE),)
		# kbuild part of makefile
		obj-m  := 8123.o
		8123-y := 8123_if.o 8123_pci.o 8123_bin.o

		else
		# normal makefile
		KDIR ?= /lib/modules/`uname -r`/build

		default:
			$(MAKE) -C $(KDIR) M=$$PWD

		# Module specific targets
		genbin:
			echo "X" > 8123_bin.o_shipped

		endif

	The check for KERNELRELEASE is used to separate the two parts
	of the makefile. In the example, kbuild will only see the two
	assignments, whereas "make" will see everything except these
	two assignments. This is due to two passes made on the file:
	the first pass is by the "make" instance run on the command
	line; the second pass is by the kbuild system, which is
	initiated by the parameterized "make" in the default target.

3.2 Separate Kbuild File and Makefile
-------------------------------------

	In newer versions of the kernel, kbuild will first look for a
	file named "Kbuild," and only if that is not found, will it
	then look for a makefile. Utilizing a "Kbuild" file allows us
	to split up the makefile from example 1 into two files:

	Example 2::

		--> filename: Kbuild
		obj-m  := 8123.o
		8123-y := 8123_if.o 8123_pci.o 8123_bin.o

		--> filename: Makefile
		KDIR ?= /lib/modules/`uname -r`/build

		default:
			$(MAKE) -C $(KDIR) M=$$PWD

		# Module specific targets
		genbin:
			echo "X" > 8123_bin.o_shipped

	The split in example 2 is questionable due to the simplicity of
	each file; however, some external modules use makefiles
	consisting of several hundred lines, and here it really pays
	off to separate the kbuild part from the rest.

	The next example shows a backward compatible version.

	Example 3::

		--> filename: Kbuild
		obj-m  := 8123.o
		8123-y := 8123_if.o 8123_pci.o 8123_bin.o

		--> filename: Makefile
		ifneq ($(KERNELRELEASE),)
		# kbuild part of makefile
		include Kbuild

		else
		# normal makefile
		KDIR ?= /lib/modules/`uname -r`/build

		default:
			$(MAKE) -C $(KDIR) M=$$PWD

		# Module specific targets
		genbin:
			echo "X" > 8123_bin.o_shipped

		endif

	Here the "Kbuild" file is included from the makefile. This
	allows an older version of kbuild, which only knows of
	makefiles, to be used when the "make" and kbuild parts are
	split into separate files.

3.3 Binary Blobs
----------------

	Some external modules need to include an object file as a blob.
	kbuild has support for this, but requires the blob file to be
	named <filename>_shipped. When the kbuild rules kick in, a copy
	of <filename>_shipped is created with _shipped stripped off,
	giving us <filename>. This shortened filename can be used in
	the assignment to the module.

	Throughout this section, 8123_bin.o_shipped has been used to
	build the kernel module 8123.ko; it has been included as
	8123_bin.o::

		8123-y := 8123_if.o 8123_pci.o 8123_bin.o

	Although there is no distinction between the ordinary source
	files and the binary file, kbuild will pick up different rules
	when creating the object file for the module.

3.4 Building Multiple Modules
=============================

	kbuild supports building multiple modules with a single build
	file. For example, if you wanted to build two modules, foo.ko
	and bar.ko, the kbuild lines would be::

		obj-m := foo.o bar.o
		foo-y := <foo_srcs>
		bar-y := <bar_srcs>

	It is that simple!

4. Include Files
================

Within the kernel, header files are kept in standard locations
according to the following rule:

	* If the header file only describes the internal interface of a
	  module, then the file is placed in the same directory as the
	  source files.
	* If the header file describes an interface used by other parts
	  of the kernel that are located in different directories, then
	  the file is placed in include/linux/.

	  NOTE:
	      There are two notable exceptions to this rule: larger
	      subsystems have their own directory under include/, such as
	      include/scsi; and architecture specific headers are located
	      under arch/$(SRCARCH)/include/.

4.1 Kernel Includes
-------------------

	To include a header file located under include/linux/, simply
	use::

		#include <linux/module.h>

	kbuild will add options to "gcc" so the relevant directories
	are searched.

4.2 Single Subdirectory
-----------------------

	External modules tend to place header files in a separate
	include/ directory where their source is located, although this
	is not the usual kernel style. To inform kbuild of the
	directory, use either ccflags-y or CFLAGS_<filename>.o.

	Using the example from section 3, if we moved 8123_if.h to a
	subdirectory named include, the resulting kbuild file would
	look like::

		--> filename: Kbuild
		obj-m := 8123.o

		ccflags-y := -Iinclude
		8123-y := 8123_if.o 8123_pci.o 8123_bin.o

	Note that in the assignment there is no space between -I and
	the path. This is a limitation of kbuild: there must be no
	space present.

4.3 Several Subdirectories
--------------------------

	kbuild can handle files that are spread over several directories.
	Consider the following example::

		.
		|__ src
		|   |__ complex_main.c
		|   |__ hal
		|	|__ hardwareif.c
		|	|__ include
		|	    |__ hardwareif.h
		|__ include
		|__ complex.h

	To build the module complex.ko, we then need the following
	kbuild file::

		--> filename: Kbuild
		obj-m := complex.o
		complex-y := src/complex_main.o
		complex-y += src/hal/hardwareif.o

		ccflags-y := -I$(src)/include
		ccflags-y += -I$(src)/src/hal/include

	As you can see, kbuild knows how to handle object files located
	in other directories. The trick is to specify the directory
	relative to the kbuild file's location. That being said, this
	is NOT recommended practice.

	For the header files, kbuild must be explicitly told where to
	look. When kbuild executes, the current directory is always the
	root of the kernel tree (the argument to "-C") and therefore an
	absolute path is needed. $(src) provides the absolute path by
	pointing to the directory where the currently executing kbuild
	file is located.

5. Module Installation
======================

Modules which are included in the kernel are installed in the
directory:

	/lib/modules/$(KERNELRELEASE)/kernel/

And external modules are installed in:

	/lib/modules/$(KERNELRELEASE)/extra/

5.1 INSTALL_MOD_PATH
--------------------

	Above are the default directories but as always some level of
	customization is possible. A prefix can be added to the
	installation path using the variable INSTALL_MOD_PATH::

		$ make INSTALL_MOD_PATH=/frodo modules_install
		=> Install dir: /frodo/lib/modules/$(KERNELRELEASE)/kernel/

	INSTALL_MOD_PATH may be set as an ordinary shell variable or,
	as shown above, can be specified on the command line when
	calling "make." This has effect when installing both in-tree
	and out-of-tree modules.

5.2 INSTALL_MOD_DIR
-------------------

	External modules are by default installed to a directory under
	/lib/modules/$(KERNELRELEASE)/extra/, but you may wish to
	locate modules for a specific functionality in a separate
	directory. For this purpose, use INSTALL_MOD_DIR to specify an
	alternative name to "extra."::

		$ make INSTALL_MOD_DIR=gandalf -C $KDIR \
		       M=$PWD modules_install
		=> Install dir: /lib/modules/$(KERNELRELEASE)/gandalf/

6. Module Versioning
====================

Module versioning is enabled by the CONFIG_MODVERSIONS tag, and is used
as a simple ABI consistency check. A CRC value of the full prototype
for an exported symbol is created. When a module is loaded/used, the
CRC values contained in the kernel are compared with similar values in
the module; if they are not equal, the kernel refuses to load the
module.

Module.symvers contains a list of all exported symbols from a kernel
build.

6.1 Symbols From the Kernel (vmlinux + modules)
-----------------------------------------------

	During a kernel build, a file named Module.symvers will be
	generated. Module.symvers contains all exported symbols from
	the kernel and compiled modules. For each symbol, the
	corresponding CRC value is also stored.

	The syntax of the Module.symvers file is::

		<CRC>       <Symbol>         <Module>                         <Export Type>     <Namespace>

		0xe1cc2a05  usb_stor_suspend drivers/usb/storage/usb-storage  EXPORT_SYMBOL_GPL USB_STORAGE

	The fields are separated by tabs and values may be empty (e.g.
	if no namespace is defined for an exported symbol).

	For a kernel build without CONFIG_MODVERSIONS enabled, the CRC
	would read 0x00000000.

	Module.symvers serves two purposes:

	1) It lists all exported symbols from vmlinux and all modules.
	2) It lists the CRC if CONFIG_MODVERSIONS is enabled.

6.2 Symbols and External Modules
--------------------------------

	When building an external module, the build system needs access
	to the symbols from the kernel to check if all external symbols
	are defined. This is done in the MODPOST step. modpost obtains
	the symbols by reading Module.symvers from the kernel source
	tree. During the MODPOST step, a new Module.symvers file will be
	written containing all exported symbols from that external module.

6.3 Symbols From Another External Module
----------------------------------------

	Sometimes, an external module uses exported symbols from
	another external module. Kbuild needs to have full knowledge of
	all symbols to avoid spitting out warnings about undefined
	symbols. Two solutions exist for this situation.

	NOTE: The method with a top-level kbuild file is recommended
	but may be impractical in certain situations.

	Use a top-level kbuild file
		If you have two modules, foo.ko and bar.ko, where
		foo.ko needs symbols from bar.ko, you can use a
		common top-level kbuild file so both modules are
		compiled in the same build. Consider the following
		directory layout::

			./foo/ <= contains foo.ko
			./bar/ <= contains bar.ko

		The top-level kbuild file would then look like::

			#./Kbuild (or ./Makefile):
				obj-m := foo/ bar/

		And executing::

			$ make -C $KDIR M=$PWD

		will then do the expected and compile both modules with
		full knowledge of symbols from either module.

	Use "make" variable KBUILD_EXTRA_SYMBOLS
		If it is impractical to add a top-level kbuild file,
		you can assign a space separated list
		of files to KBUILD_EXTRA_SYMBOLS in your build file.
		These files will be loaded by modpost during the
		initialization of its symbol tables.

7. Tips & Tricks
================

7.1 Testing for CONFIG_FOO_BAR
------------------------------

	Modules often need to check for certain `CONFIG_` options to
	decide if a specific feature is included in the module. In
	kbuild this is done by referencing the `CONFIG_` variable
	directly::

		#fs/ext2/Makefile
		obj-$(CONFIG_EXT2_FS) += ext2.o

		ext2-y := balloc.o bitmap.o dir.o
		ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o

	External modules have traditionally used "grep" to check for
	specific `CONFIG_` settings directly in .config. This usage is
	broken. As introduced before, external modules should use
	kbuild for building and can therefore use the same methods as
	in-tree modules when testing for `CONFIG_` definitions.

repo_name: angery/linux


code:
===================
Reproducible builds
===================

It is generally desirable that building the same source code with
the same set of tools is reproducible, i.e. the output is always
exactly the same.  This makes it possible to verify that the build
infrastructure for a binary distribution or embedded system has not
been subverted.  This can also make it easier to verify that a source
or tool change does not make any difference to the resulting binaries.

The `Reproducible Builds project`_ has more information about this
general topic.  This document covers the various reasons why building
the kernel may be unreproducible, and how to avoid them.

Timestamps
----------

The kernel embeds timestamps in three places:

* The version string exposed by ``uname()`` and included in
  ``/proc/version``

* File timestamps in the embedded initramfs

* If enabled via ``CONFIG_IKHEADERS``, file timestamps of kernel
  headers embedded in the kernel or respective module,
  exposed via ``/sys/kernel/kheaders.tar.xz``

By default the timestamp is the current time and in the case of
``kheaders`` the various files' modification times. This must
be overridden using the `KBUILD_BUILD_TIMESTAMP`_ variable.
If you are building from a git commit, you could use its commit date.

The kernel does *not* use the ``__DATE__`` and ``__TIME__`` macros,
and enables warnings if they are used.  If you incorporate external
code that does use these, you must override the timestamp they
correspond to by setting the `SOURCE_DATE_EPOCH`_ environment
variable.

User, host
----------

The kernel embeds the building user and host names in
``/proc/version``.  These must be overridden using the
`KBUILD_BUILD_USER and KBUILD_BUILD_HOST`_ variables.  If you are
building from a git commit, you could use its committer address.

Absolute filenames
------------------

When the kernel is built out-of-tree, debug information may include
absolute filenames for the source files.  This must be overridden by
including the ``-fdebug-prefix-map`` option in the `KCFLAGS`_ variable.

Depending on the compiler used, the ``__FILE__`` macro may also expand
to an absolute filename in an out-of-tree build.  Kbuild automatically
uses the ``-fmacro-prefix-map`` option to prevent this, if it is
supported.

The Reproducible Builds web site has more information about these
`prefix-map options`_.

Generated files in source packages
----------------------------------

The build processes for some programs under the ``tools/``
subdirectory do not completely support out-of-tree builds.  This may
cause a later source package build using e.g. ``make rpm-pkg`` to
include generated files.  You should ensure the source tree is
pristine by running ``make mrproper`` or ``git clean -d -f -x`` before
building a source package.

Module signing
--------------

If you enable ``CONFIG_MODULE_SIG_ALL``, the default behaviour is to
generate a different temporary key for each build, resulting in the
modules being unreproducible.  However, including a signing key with
your source would presumably defeat the purpose of signing modules.

One approach to this is to divide up the build process so that the
unreproducible parts can be treated as sources:

1. Generate a persistent signing key.  Add the certificate for the key
   to the kernel source.

2. Set the ``CONFIG_SYSTEM_TRUSTED_KEYS`` symbol to include the
   signing key's certificate, set ``CONFIG_MODULE_SIG_KEY`` to an
   empty string, and disable ``CONFIG_MODULE_SIG_ALL``.
   Build the kernel and modules.

3. Create detached signatures for the modules, and publish them as
   sources.

4. Perform a second build that attaches the module signatures.  It
   can either rebuild the modules or use the output of step 2.

Structure randomisation
-----------------------

If you enable ``CONFIG_RANDSTRUCT``, you will need to pre-generate
the random seed in ``scripts/basic/randstruct.seed`` so the same
value is used by each build. See ``scripts/gen-randstruct-seed.sh``
for details.

Debug info conflicts
--------------------

This is not a problem of unreproducibility, but of generated files
being *too* reproducible.

Once you set all the necessary variables for a reproducible build, a
vDSO's debug information may be identical even for different kernel
versions.  This can result in file conflicts between debug information
packages for the different kernel versions.

To avoid this, you can make the vDSO different for different
kernel versions by including an arbitrary string of "salt" in it.
This is specified by the Kconfig symbol ``CONFIG_BUILD_SALT``.

Git
---

Uncommitted changes or different commit ids in git can also lead
to different compilation results. For example, after executing
``git reset HEAD^``, even if the code is the same, the
``include/config/kernel.release`` generated during compilation
will be different, which will eventually lead to binary differences.
See ``scripts/setlocalversion`` for details.

.. _KBUILD_BUILD_TIMESTAMP: kbuild.html#kbuild-build-timestamp
.. _KBUILD_BUILD_USER and KBUILD_BUILD_HOST: kbuild.html#kbuild-build-user-kbuild-build-host
.. _KCFLAGS: kbuild.html#kcflags
.. _prefix-map options: https://reproducible-builds.org/docs/build-path/
.. _Reproducible Builds project: https://reproducible-builds.org/
.. _SOURCE_DATE_EPOCH: https://reproducible-builds.org/docs/source-date-epoch/