code:
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra210-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
#include <dt-bindings/soc/tegra-pmc.h>

/ {
	compatible = "nvidia,tegra210";
	interrupt-parent = <&lic>;
	#address-cells = <2>;
	#size-cells = <2>;

	pcie@1003000 {
		compatible = "nvidia,tegra210-pcie";
		device_type = "pci";
		reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
		      <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
		      <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
		reg-names = "pads", "afi", "cs";
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
		interrupt-names = "intr", "msi";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

		bus-range = <0x00 0xff>;
		#address-cells = <3>;
		#size-cells = <2>;

		ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
			 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
			 <0x01000000 0 0x0        0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
			 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
			 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */

		clocks = <&tegra_car TEGRA210_CLK_PCIE>,
			 <&tegra_car TEGRA210_CLK_AFI>,
			 <&tegra_car TEGRA210_CLK_PLL_E>,
			 <&tegra_car TEGRA210_CLK_CML0>;
		clock-names = "pex", "afi", "pll_e", "cml";
		resets = <&tegra_car 70>,
			 <&tegra_car 72>,
			 <&tegra_car 74>;
		reset-names = "pex", "afi", "pcie_x";

		pinctrl-names = "default", "idle";
		pinctrl-0 = <&pex_dpd_disable>;
		pinctrl-1 = <&pex_dpd_enable>;

		status = "disabled";

		pci@1,0 {
			device_type = "pci";
			assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
			reg = <0x000800 0 0 0 0>;
			bus-range = <0x00 0xff>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <4>;
		};

		pci@2,0 {
			device_type = "pci";
			assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
			reg = <0x001000 0 0 0 0>;
			bus-range = <0x00 0xff>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <1>;
		};
	};

	host1x@50000000 {
		compatible = "nvidia,tegra210-host1x";
		reg = <0x0 0x50000000 0x0 0x00034000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
		interrupt-names = "syncpt", "host1x";
		clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
		clock-names = "host1x";
		resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>;
		reset-names = "host1x", "mc";

		#address-cells = <2>;
		#size-cells = <2>;

		ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;

		iommus = <&mc TEGRA_SWGROUP_HC>;

		dpaux1: dpaux@54040000 {
			compatible = "nvidia,tegra210-dpaux";
			reg = <0x0 0x54040000 0x0 0x00040000>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
				 <&tegra_car TEGRA210_CLK_PLL_DP>;
			clock-names = "dpaux", "parent";
			resets = <&tegra_car 207>;
			reset-names = "dpaux";
			power-domains = <&pd_sor>;
			status = "disabled";

			state_dpaux1_aux: pinmux-aux {
				groups = "dpaux-io";
				function = "aux";
			};

			state_dpaux1_i2c: pinmux-i2c {
				groups = "dpaux-io";
				function = "i2c";
			};

			state_dpaux1_off: pinmux-off {
				groups = "dpaux-io";
				function = "off";
			};

			i2c-bus {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		vi@54080000 {
			compatible = "nvidia,tegra210-vi";
			reg = <0x0 0x54080000 0x0 0x700>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;

			clocks = <&tegra_car TEGRA210_CLK_VI>;
			power-domains = <&pd_venc>;

			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0x0 0x0 0x54080000 0x2000>;

			csi@838 {
				compatible = "nvidia,tegra210-csi";
				reg = <0x838 0x1300>;
				status = "disabled";
				assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
						  <&tegra_car TEGRA210_CLK_CILCD>,
						  <&tegra_car TEGRA210_CLK_CILE>,
						  <&tegra_car TEGRA210_CLK_CSI_TPG>;
				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
							 <&tegra_car TEGRA210_CLK_PLL_P>,
							 <&tegra_car TEGRA210_CLK_PLL_P>;
				assigned-clock-rates = <102000000>,
						       <102000000>,
						       <102000000>,
						       <972000000>;

				clocks = <&tegra_car TEGRA210_CLK_CSI>,
					 <&tegra_car TEGRA210_CLK_CILAB>,
					 <&tegra_car TEGRA210_CLK_CILCD>,
					 <&tegra_car TEGRA210_CLK_CILE>,
					 <&tegra_car TEGRA210_CLK_CSI_TPG>;
				clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
				power-domains = <&pd_sor>;
			};
		};

		tsec@54100000 {
			compatible = "nvidia,tegra210-tsec";
			reg = <0x0 0x54100000 0x0 0x00040000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA210_CLK_TSEC>;
			clock-names = "tsec";
			resets = <&tegra_car 83>;
			reset-names = "tsec";
			status = "disabled";
		};

		dc@54200000 {
			compatible = "nvidia,tegra210-dc";
			reg = <0x0 0x54200000 0x0 0x00040000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA210_CLK_DISP1>;
			clock-names = "dc";
			resets = <&tegra_car 27>;
			reset-names = "dc";

			iommus = <&mc TEGRA_SWGROUP_DC>;

			nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
			nvidia,head = <0>;
		};

		dc@54240000 {
			compatible = "nvidia,tegra210-dc";
			reg = <0x0 0x54240000 0x0 0x00040000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA210_CLK_DISP2>;
			clock-names = "dc";
			resets = <&tegra_car 26>;
			reset-names = "dc";

			iommus = <&mc TEGRA_SWGROUP_DCB>;

			nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
			nvidia,head = <1>;
		};

		dsia: dsi@54300000 {
			compatible = "nvidia,tegra210-dsi";
			reg = <0x0 0x54300000 0x0 0x00040000>;
			clocks = <&tegra_car TEGRA210_CLK_DSIA>,
				 <&tegra_car TEGRA210_CLK_DSIALP>,
				 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
			clock-names = "dsi", "lp", "parent";
			resets = <&tegra_car 48>;
			reset-names = "dsi";
			power-domains = <&pd_sor>;
			nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */

			status = "disabled";

			#address-cells = <1>;
			#size-cells = <0>;
		};

		vic@54340000 {
			compatible = "nvidia,tegra210-vic";
			reg = <0x0 0x54340000 0x0 0x00040000>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA210_CLK_VIC03>;
			clock-names = "vic";
			resets = <&tegra_car 178>;
			reset-names = "vic";

			iommus = <&mc TEGRA_SWGROUP_VIC>;
			power-domains = <&pd_vic>;
		};

		nvjpg@54380000 {
			compatible = "nvidia,tegra210-nvjpg";
			reg = <0x0 0x54380000 0x0 0x00040000>;
			status = "disabled";
		};

		dsib: dsi@54400000 {
			compatible = "nvidia,tegra210-dsi";
			reg = <0x0 0x54400000 0x0 0x00040000>;
			clocks = <&tegra_car TEGRA210_CLK_DSIB>,
				 <&tegra_car TEGRA210_CLK_DSIBLP>,
				 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
			clock-names = "dsi", "lp", "parent";
			resets = <&tegra_car 82>;
			reset-names = "dsi";
			power-domains = <&pd_sor>;
			nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */

			status = "disabled";

			#address-cells = <1>;
			#size-cells = <0>;
		};

		nvdec@54480000 {
			compatible = "nvidia,tegra210-nvdec";
			reg = <0x0 0x54480000 0x0 0x00040000>;
			status = "disabled";
		};

		nvenc@544c0000 {
			compatible = "nvidia,tegra210-nvenc";
			reg = <0x0 0x544c0000 0x0 0x00040000>;
			status = "disabled";
		};

		tsec@54500000 {
			compatible = "nvidia,tegra210-tsec";
			reg = <0x0 0x54500000 0x0 0x00040000>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA210_CLK_TSECB>;
			clock-names = "tsec";
			resets = <&tegra_car 206>;
			reset-names = "tsec";
			status = "disabled";
		};

		sor0: sor@54540000 {
			compatible = "nvidia,tegra210-sor";
			reg = <0x0 0x54540000 0x0 0x00040000>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA210_CLK_SOR0>,
				 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
				 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
				 <&tegra_car TEGRA210_CLK_PLL_DP>,
				 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
			clock-names = "sor", "out", "parent", "dp", "safe";
			resets = <&tegra_car 182>;
			reset-names = "sor";
			pinctrl-0 = <&state_dpaux_aux>;
			pinctrl-1 = <&state_dpaux_i2c>;
			pinctrl-2 = <&state_dpaux_off>;
			pinctrl-names = "aux", "i2c", "off";
			power-domains = <&pd_sor>;
			status = "disabled";
		};

		sor1: sor@54580000 {
			compatible = "nvidia,tegra210-sor1";
			reg = <0x0 0x54580000 0x0 0x00040000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA210_CLK_SOR1>,
				 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
				 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
				 <&tegra_car TEGRA210_CLK_PLL_DP>,
				 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
			clock-names = "sor", "out", "parent", "dp", "safe";
			resets = <&tegra_car 183>;
			reset-names = "sor";
			pinctrl-0 = <&state_dpaux1_aux>;
			pinctrl-1 = <&state_dpaux1_i2c>;
			pinctrl-2 = <&state_dpaux1_off>;
			pinctrl-names = "aux", "i2c", "off";
			power-domains = <&pd_sor>;
			status = "disabled";
		};

		dpaux: dpaux@545c0000 {
			compatible = "nvidia,tegra210-dpaux";
			reg = <0x0 0x545c0000 0x0 0x00040000>;
			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
				 <&tegra_car TEGRA210_CLK_PLL_DP>;
			clock-names = "dpaux", "parent";
			resets = <&tegra_car 181>;
			reset-names = "dpaux";
			power-domains = <&pd_sor>;
			status = "disabled";

			state_dpaux_aux: pinmux-aux {
				groups = "dpaux-io";
				function = "aux";
			};

			state_dpaux_i2c: pinmux-i2c {
				groups = "dpaux-io";
				function = "i2c";
			};

			state_dpaux_off: pinmux-off {
				groups = "dpaux-io";
				function = "off";
			};

			i2c-bus {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		isp@54600000 {
			compatible = "nvidia,tegra210-isp";
			reg = <0x0 0x54600000 0x0 0x00040000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA210_CLK_ISPA>;
			resets = <&tegra_car 23>;
			reset-names = "isp";
			status = "disabled";
		};

		isp@54680000 {
			compatible = "nvidia,tegra210-isp";
			reg = <0x0 0x54680000 0x0 0x00040000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA210_CLK_ISPB>;
			resets = <&tegra_car 3>;
			reset-names = "isp";
			status = "disabled";
		};

		i2c@546c0000 {
			compatible = "nvidia,tegra210-i2c-vi";
			reg = <0x0 0x546c0000 0x0 0x00040000>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA210_CLK_VI_I2C>,
				 <&tegra_car TEGRA210_CLK_I2CSLOW>;
			clock-names = "div-clk", "slow";
			resets = <&tegra_car 208>;
			reset-names = "i2c";
			power-domains = <&pd_venc>;
			status = "disabled";

			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	gic: interrupt-controller@50041000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x50041000 0x0 0x1000>,
		      <0x0 0x50042000 0x0 0x2000>,
		      <0x0 0x50044000 0x0 0x2000>,
		      <0x0 0x50046000 0x0 0x2000>;
		interrupts = <GIC_PPI 9
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-parent = <&gic>;
	};

	gpu@57000000 {
		compatible = "nvidia,gm20b";
		reg = <0x0 0x57000000 0x0 0x01000000>,
		      <0x0 0x58000000 0x0 0x01000000>;
		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "stall", "nonstall";
		clocks = <&tegra_car TEGRA210_CLK_GPU>,
			 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
			 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
		clock-names = "gpu", "pwr", "ref";
		resets = <&tegra_car 184>;
		reset-names = "gpu";

		iommus = <&mc TEGRA_SWGROUP_GPU>;

		status = "disabled";
	};

	lic: interrupt-controller@60004000 {
		compatible = "nvidia,tegra210-ictlr";
		reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
		      <0x0 0x60004100 0x0 0x40>, /* secondary controller */
		      <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
		      <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
		      <0x0 0x60004400 0x0 0x40>, /* quinary controller */
		      <0x0 0x60004500 0x0 0x40>; /* senary controller */
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra210-timer";
		reg = <0x0 0x60005000 0x0 0x400>;
		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_TIMER>;
		clock-names = "timer";
	};

	tegra_car: clock@60006000 {
		compatible = "nvidia,tegra210-car";
		reg = <0x0 0x60006000 0x0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	flow-controller@60007000 {
		compatible = "nvidia,tegra210-flowctrl";
		reg = <0x0 0x60007000 0x0 0x1000>;
	};

	gpio: gpio@6000d000 {
		compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
		reg = <0x0 0x6000d000 0x0 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	apbdma: dma@60020000 {
		compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
		reg = <0x0 0x60020000 0x0 0x1400>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
		clock-names = "dma";
		resets = <&tegra_car 34>;
		reset-names = "dma";
		#dma-cells = <1>;
	};

	apbmisc@70000800 {
		compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
		reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
		      <0x0 0x70000008 0x0 0x04>;   /* Strapping options */
	};

	pinmux: pinmux@700008d4 {
		compatible = "nvidia,tegra210-pinmux";
		reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
		      <0x0 0x70003000 0x0 0x294>; /* Mux registers */

		sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv {
			sdmmc1 {
				nvidia,pins = "drive_sdmmc1";
				nvidia,pull-down-strength = <0x8>;
				nvidia,pull-up-strength = <0x8>;
			};
		};

		sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv {
			sdmmc1 {
				nvidia,pins = "drive_sdmmc1";
				nvidia,pull-down-strength = <0x4>;
				nvidia,pull-up-strength = <0x3>;
			};
		};

		sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv {
			sdmmc2 {
				nvidia,pins = "drive_sdmmc2";
				nvidia,pull-down-strength = <0x10>;
				nvidia,pull-up-strength = <0x10>;
			};
		};

		sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv {
			sdmmc3 {
				nvidia,pins = "drive_sdmmc3";
				nvidia,pull-down-strength = <0x8>;
				nvidia,pull-up-strength = <0x8>;
			};
		};

		sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv {
			sdmmc3 {
				nvidia,pins = "drive_sdmmc3";
				nvidia,pull-down-strength = <0x4>;
				nvidia,pull-up-strength = <0x3>;
			};
		};

		sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv {
			sdmmc4 {
				nvidia,pins = "drive_sdmmc4";
				nvidia,pull-down-strength = <0x10>;
				nvidia,pull-up-strength = <0x10>;
			};
		};
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performance. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
	 * the APB DMA based serial driver, the compatible is
	 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x70006000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_UARTA>;
		clock-names = "serial";
		resets = <&tegra_car 6>;
		reset-names = "serial";
		dmas = <&apbdma 8>, <&apbdma 8>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x70006040 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_UARTB>;
		clock-names = "serial";
		resets = <&tegra_car 7>;
		reset-names = "serial";
		dmas = <&apbdma 9>, <&apbdma 9>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x70006200 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_UARTC>;
		clock-names = "serial";
		resets = <&tegra_car 55>;
		reset-names = "serial";
		dmas = <&apbdma 10>, <&apbdma 10>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x70006300 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_UARTD>;
		clock-names = "serial";
		resets = <&tegra_car 65>;
		reset-names = "serial";
		dmas = <&apbdma 19>, <&apbdma 19>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	pwm: pwm@7000a000 {
		compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
		reg = <0x0 0x7000a000 0x0 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car TEGRA210_CLK_PWM>;
		resets = <&tegra_car 17>;
		reset-names = "pwm";
		status = "disabled";
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
		reg = <0x0 0x7000c000 0x0 0x100>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA210_CLK_I2C1>;
		clock-names = "div-clk";
		resets = <&tegra_car 12>;
		reset-names = "i2c";
		dmas = <&apbdma 21>, <&apbdma 21>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
		reg = <0x0 0x7000c400 0x0 0x100>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA210_CLK_I2C2>;
		clock-names = "div-clk";
		resets = <&tegra_car 54>;
		reset-names = "i2c";
		dmas = <&apbdma 22>, <&apbdma 22>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
		reg = <0x0 0x7000c500 0x0 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA210_CLK_I2C3>;
		clock-names = "div-clk";
		resets = <&tegra_car 67>;
		reset-names = "i2c";
		dmas = <&apbdma 23>, <&apbdma 23>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
		reg = <0x0 0x7000c700 0x0 0x100>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA210_CLK_I2C4>;
		clock-names = "div-clk";
		resets = <&tegra_car 103>;
		reset-names = "i2c";
		dmas = <&apbdma 26>, <&apbdma 26>;
		dma-names = "rx", "tx";
		pinctrl-0 = <&state_dpaux1_i2c>;
		pinctrl-1 = <&state_dpaux1_off>;
		pinctrl-names = "default", "idle";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
		reg = <0x0 0x7000d000 0x0 0x100>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA210_CLK_I2C5>;
		clock-names = "div-clk";
		resets = <&tegra_car 47>;
		reset-names = "i2c";
		dmas = <&apbdma 24>, <&apbdma 24>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000d100 {
		compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
		reg = <0x0 0x7000d100 0x0 0x100>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA210_CLK_I2C6>;
		clock-names = "div-clk";
		resets = <&tegra_car 166>;
		reset-names = "i2c";
		dmas = <&apbdma 30>, <&apbdma 30>;
		dma-names = "rx", "tx";
		pinctrl-0 = <&state_dpaux_i2c>;
		pinctrl-1 = <&state_dpaux_off>;
		pinctrl-names = "default", "idle";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000d400 0x0 0x200>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA210_CLK_SBC1>;
		clock-names = "spi";
		resets = <&tegra_car 41>;
		reset-names = "spi";
		dmas = <&apbdma 15>, <&apbdma 15>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000d600 0x0 0x200>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA210_CLK_SBC2>;
		clock-names = "spi";
		resets = <&tegra_car 44>;
		reset-names = "spi";
		dmas = <&apbdma 16>, <&apbdma 16>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000d800 0x0 0x200>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA210_CLK_SBC3>;
		clock-names = "spi";
		resets = <&tegra_car 46>;
		reset-names = "spi";
		dmas = <&apbdma 17>, <&apbdma 17>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000da00 0x0 0x200>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA210_CLK_SBC4>;
		clock-names = "spi";
		resets = <&tegra_car 68>;
		reset-names = "spi";
		dmas = <&apbdma 18>, <&apbdma 18>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	rtc@7000e000 {
		compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
		reg = <0x0 0x7000e000 0x0 0x100>;
		interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&tegra_pmc>;
		clocks = <&tegra_car TEGRA210_CLK_RTC>;
		clock-names = "rtc";
	};

	tegra_pmc: pmc@7000e400 {
		compatible = "nvidia,tegra210-pmc";
		reg = <0x0 0x7000e400 0x0 0x400>;
		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
		#clock-cells = <1>;
		#interrupt-cells = <2>;
		interrupt-controller;

		powergates {
			pd_audio: aud {
				clocks = <&tegra_car TEGRA210_CLK_APE>,
					 <&tegra_car TEGRA210_CLK_APB2APE>;
				resets = <&tegra_car 198>;
				#power-domain-cells = <0>;
			};

			pd_sor: sor {
				clocks = <&tegra_car TEGRA210_CLK_SOR0>,
					 <&tegra_car TEGRA210_CLK_SOR1>,
					 <&tegra_car TEGRA210_CLK_CILAB>,
					 <&tegra_car TEGRA210_CLK_CILCD>,
					 <&tegra_car TEGRA210_CLK_CILE>,
					 <&tegra_car TEGRA210_CLK_DSIA>,
					 <&tegra_car TEGRA210_CLK_DSIB>,
					 <&tegra_car TEGRA210_CLK_DPAUX>,
					 <&tegra_car TEGRA210_CLK_DPAUX1>,
					 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
				resets = <&tegra_car TEGRA210_CLK_SOR0>,
					 <&tegra_car TEGRA210_CLK_SOR1>,
					 <&tegra_car TEGRA210_CLK_DSIA>,
					 <&tegra_car TEGRA210_CLK_DSIB>,
					 <&tegra_car TEGRA210_CLK_DPAUX>,
					 <&tegra_car TEGRA210_CLK_DPAUX1>,
					 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
				#power-domain-cells = <0>;
			};

			pd_xusbss: xusba {
				clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
				resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
				#power-domain-cells = <0>;
			};

			pd_xusbdev: xusbb {
				clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
				resets = <&tegra_car 95>;
				#power-domain-cells = <0>;
			};

			pd_xusbhost: xusbc {
				clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
				resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
				#power-domain-cells = <0>;
			};

			pd_vic: vic {
				clocks = <&tegra_car TEGRA210_CLK_VIC03>;
				clock-names = "vic";
				resets = <&tegra_car 178>;
				reset-names = "vic";
				#power-domain-cells = <0>;
			};

			pd_venc: venc {
				clocks = <&tegra_car TEGRA210_CLK_VI>,
					 <&tegra_car TEGRA210_CLK_CSI>;
				resets = <&mc TEGRA210_MC_RESET_VI>,
					 <&tegra_car 20>,
					 <&tegra_car 52>;
				#power-domain-cells = <0>;
			};
		};

		pinmux {
			sdmmc1_3v3: sdmmc1-3v3 {
				pins = "sdmmc1";
				power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
			};

			sdmmc1_1v8: sdmmc1-1v8 {
				pins = "sdmmc1";
				power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
			};

			sdmmc3_3v3: sdmmc3-3v3 {
				pins = "sdmmc3";
				power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
			};

			sdmmc3_1v8: sdmmc3-1v8 {
				pins = "sdmmc3";
				power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
			};

			pex_dpd_disable: pex-dpd-disable {
				pins = "pex-bias", "pex-clk1", "pex-clk2";
				low-power-disable;
			};

			pex_dpd_enable: pex-dpd-enable {
				pins = "pex-bias", "pex-clk1", "pex-clk2";
				low-power-enable;
			};
		};
	};

	fuse@7000f800 {
		compatible = "nvidia,tegra210-efuse";
		reg = <0x0 0x7000f800 0x0 0x400>;
		clocks = <&tegra_car TEGRA210_CLK_FUSE>;
		clock-names = "fuse";
		resets = <&tegra_car 39>;
		reset-names = "fuse";
	};

	mc: memory-controller@70019000 {
		compatible = "nvidia,tegra210-mc";
		reg = <0x0 0x70019000 0x0 0x1000>;
		clocks = <&tegra_car TEGRA210_CLK_MC>;
		clock-names = "mc";

		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;
		#reset-cells = <1>;
	};

	emc: external-memory-controller@7001b000 {
		compatible = "nvidia,tegra210-emc";
		reg = <0x0 0x7001b000 0x0 0x1000>,
		      <0x0 0x7001e000 0x0 0x1000>,
		      <0x0 0x7001f000 0x0 0x1000>;
		clocks = <&tegra_car TEGRA210_CLK_EMC>;
		clock-names = "emc";
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,memory-controller = <&mc>;
		#cooling-cells = <2>;
	};

	sata@70020000 {
		compatible = "nvidia,tegra210-ahci";
		reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
		      <0x0 0x70020000 0x0 0x7000>, /* SATA */
		      <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_SATA>,
			 <&tegra_car TEGRA210_CLK_SATA_OOB>;
		clock-names = "sata", "sata-oob";
		resets = <&tegra_car 124>,
			 <&tegra_car 129>,
			 <&tegra_car 123>;
		reset-names = "sata", "sata-cold", "sata-oob";
		status = "disabled";
	};

	hda@70030000 {
		compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
		reg = <0x0 0x70030000 0x0 0x10000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_HDA>,
		         <&tegra_car TEGRA210_CLK_HDA2HDMI>,
			 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
		resets = <&tegra_car 125>, /* hda */
			 <&tegra_car 128>, /* hda2hdmi */
			 <&tegra_car 111>; /* hda2codec_2x */
		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
		power-domains = <&pd_sor>;
		status = "disabled";
	};

	usb@70090000 {
		compatible = "nvidia,tegra210-xusb";
		reg = <0x0 0x70090000 0x0 0x8000>,
		      <0x0 0x70098000 0x0 0x1000>,
		      <0x0 0x70099000 0x0 0x1000>;
		reg-names = "hcd", "fpci", "ipfs";

		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
			 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
			 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
			 <&tegra_car TEGRA210_CLK_XUSB_SS>,
			 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
			 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
			 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
			 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
			 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
			 <&tegra_car TEGRA210_CLK_CLK_M>,
			 <&tegra_car TEGRA210_CLK_PLL_E>;
		clock-names = "xusb_host", "xusb_host_src",
			      "xusb_falcon_src", "xusb_ss",
			      "xusb_ss_div2", "xusb_ss_src",
			      "xusb_hs_src", "xusb_fs_src",
			      "pll_u_480m", "clk_m", "pll_e";
		resets = <&tegra_car 89>, <&tegra_car 156>,
			 <&tegra_car 143>;
		reset-names = "xusb_host", "xusb_ss", "xusb_src";
		power-domains = <&pd_xusbhost>, <&pd_xusbss>;
		power-domain-names = "xusb_host", "xusb_ss";

		nvidia,xusb-padctl = <&padctl>;

		status = "disabled";
	};

	padctl: padctl@7009f000 {
		compatible = "nvidia,tegra210-xusb-padctl";
		reg = <0x0 0x7009f000 0x0 0x1000>;
		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		resets = <&tegra_car 142>;
		reset-names = "padctl";
		nvidia,pmc = <&tegra_pmc>;

		status = "disabled";

		pads {
			usb2 {
				clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
				clock-names = "trk";
				status = "disabled";

				lanes {
					usb2-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb2-1 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb2-2 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb2-3 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			hsic {
				clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
				clock-names = "trk";
				status = "disabled";

				lanes {
					hsic-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					hsic-1 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			pcie {
				clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
				clock-names = "pll";
				resets = <&tegra_car 205>;
				reset-names = "phy";
				status = "disabled";

				lanes {
					pcie-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-1 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-2 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-3 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-4 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-5 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-6 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			sata {
				clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
				clock-names = "pll";
				resets = <&tegra_car 204>;
				reset-names = "phy";
				status = "disabled";

				lanes {
					sata-0 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};
		};

		ports {
			usb2-0 {
				status = "disabled";
			};

			usb2-1 {
				status = "disabled";
			};

			usb2-2 {
				status = "disabled";
			};

			usb2-3 {
				status = "disabled";
			};

			hsic-0 {
				status = "disabled";
			};

			usb3-0 {
				status = "disabled";
			};

			usb3-1 {
				status = "disabled";
			};

			usb3-2 {
				status = "disabled";
			};

			usb3-3 {
				status = "disabled";
			};
		};
	};

	mmc@700b0000 {
		compatible = "nvidia,tegra210-sdhci";
		reg = <0x0 0x700b0000 0x0 0x200>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
		clock-names = "sdhci", "tmclk";
		resets = <&tegra_car 14>;
		reset-names = "sdhci";
		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
				"sdmmc-3v3-drv", "sdmmc-1v8-drv";
		pinctrl-0 = <&sdmmc1_3v3>;
		pinctrl-1 = <&sdmmc1_1v8>;
		pinctrl-2 = <&sdmmc1_3v3_drv>;
		pinctrl-3 = <&sdmmc1_1v8_drv>;
		nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
		nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
		nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
		nvidia,default-tap = <0x2>;
		nvidia,default-trim = <0x4>;
		assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
				  <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
				  <&tegra_car TEGRA210_CLK_PLL_C4>;
		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
		assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
		status = "disabled";
	};

	mmc@700b0200 {
		compatible = "nvidia,tegra210-sdhci";
		reg = <0x0 0x700b0200 0x0 0x200>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
		clock-names = "sdhci", "tmclk";
		resets = <&tegra_car 9>;
		reset-names = "sdhci";
		pinctrl-names = "sdmmc-1v8-drv";
		pinctrl-0 = <&sdmmc2_1v8_drv>;
		nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
		nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
		nvidia,default-tap = <0x8>;
		nvidia,default-trim = <0x0>;
		status = "disabled";
	};

	mmc@700b0400 {
		compatible = "nvidia,tegra210-sdhci";
		reg = <0x0 0x700b0400 0x0 0x200>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
		clock-names = "sdhci", "tmclk";
		resets = <&tegra_car 69>;
		reset-names = "sdhci";
		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
				"sdmmc-3v3-drv", "sdmmc-1v8-drv";
		pinctrl-0 = <&sdmmc3_3v3>;
		pinctrl-1 = <&sdmmc3_1v8>;
		pinctrl-2 = <&sdmmc3_3v3_drv>;
		pinctrl-3 = <&sdmmc3_1v8_drv>;
		nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
		nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
		nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
		nvidia,default-tap = <0x3>;
		nvidia,default-trim = <0x3>;
		status = "disabled";
	};

	mmc@700b0600 {
		compatible = "nvidia,tegra210-sdhci";
		reg = <0x0 0x700b0600 0x0 0x200>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
		clock-names = "sdhci", "tmclk";
		resets = <&tegra_car 15>;
		reset-names = "sdhci";
		pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
		pinctrl-0 = <&sdmmc4_1v8_drv>;
		pinctrl-1 = <&sdmmc4_1v8_drv>;
		nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
		nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
		nvidia,default-tap = <0x8>;
		nvidia,default-trim = <0x0>;
		assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
				  <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
		nvidia,dqs-trim = <40>;
		mmc-hs400-1_8v;
		status = "disabled";
	};

	usb@700d0000 {
		compatible = "nvidia,tegra210-xudc";
		reg = <0x0 0x700d0000 0x0 0x8000>,
		      <0x0 0x700d8000 0x0 0x1000>,
		      <0x0 0x700d9000 0x0 0x1000>;
		reg-names = "base", "fpci", "ipfs";
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
			 <&tegra_car TEGRA210_CLK_XUSB_SS>,
			 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
			 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
			 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
		clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
		power-domains = <&pd_xusbdev>, <&pd_xusbss>;
		power-domain-names = "dev", "ss";
		nvidia,xusb-padctl = <&padctl>;
		status = "disabled";
	};

	soctherm: thermal-sensor@700e2000 {
		compatible = "nvidia,tegra210-soctherm";
		reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
		      <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
		reg-names = "soctherm-reg", "car-reg";
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "thermal", "edp";
		clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
			<&tegra_car TEGRA210_CLK_SOC_THERM>;
		clock-names = "tsensor", "soctherm";
		resets = <&tegra_car 78>;
		reset-names = "soctherm";
		#thermal-sensor-cells = <1>;

		throttle-cfgs {
			throttle_heavy: heavy {
				nvidia,priority = <100>;
				nvidia,cpu-throt-percent = <85>;
				nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;

				#cooling-cells = <2>;
			};
		};
	};

	mipi: mipi@700e3000 {
		compatible = "nvidia,tegra210-mipi";
		reg = <0x0 0x700e3000 0x0 0x100>;
		clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
		clock-names = "mipi-cal";
		power-domains = <&pd_sor>;
		#nvidia,mipi-calibrate-cells = <1>;
	};

	dfll: clock@70110000 {
		compatible = "nvidia,tegra210-dfll";
		reg = <0 0x70110000 0 0x100>, /* DFLL control */
		      <0 0x70110000 0 0x100>, /* I2C output control */
		      <0 0x70110100 0 0x100>, /* Integrated I2C controller */
		      <0 0x70110200 0 0x100>; /* Look-up table RAM */
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
			 <&tegra_car TEGRA210_CLK_DFLL_REF>,
			 <&tegra_car TEGRA210_CLK_I2C5>;
		clock-names = "soc", "ref", "i2c";
		resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>,
			 <&tegra_car 155>;
		reset-names = "dvco", "dfll";
		#clock-cells = <0>;
		clock-output-names = "dfllCPU_out";
		status = "disabled";
	};

	aconnect@702c0000 {
		compatible = "nvidia,tegra210-aconnect";
		clocks = <&tegra_car TEGRA210_CLK_APE>,
			 <&tegra_car TEGRA210_CLK_APB2APE>;
		clock-names = "ape", "apb2ape";
		power-domains = <&pd_audio>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
		status = "disabled";

		adma: dma-controller@702e2000 {
			compatible = "nvidia,tegra210-adma";
			reg = <0x702e2000 0x2000>;
			interrupt-parent = <&agic>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
			clock-names = "d_audio";
			status = "disabled";
		};

		agic: interrupt-controller@702f9000 {
			compatible = "nvidia,tegra210-agic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x702f9000 0x1000>,
			      <0x702fa000 0x2000>;
			interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&tegra_car TEGRA210_CLK_APE>;
			clock-names = "clk";
			status = "disabled";
		};

		tegra_ahub: ahub@702d0800 {
			compatible = "nvidia,tegra210-ahub";
			reg = <0x702d0800 0x800>;
			clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
			clock-names = "ahub";
			assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
			assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x702d0000 0x702d0000 0x0000e400>;
			status = "disabled";

			tegra_admaif: admaif@702d0000 {
				compatible = "nvidia,tegra210-admaif";
				reg = <0x702d0000 0x800>;
				dmas = <&adma 1>,  <&adma 1>,
				       <&adma 2>,  <&adma 2>,
				       <&adma 3>,  <&adma 3>,
				       <&adma 4>,  <&adma 4>,
				       <&adma 5>,  <&adma 5>,
				       <&adma 6>,  <&adma 6>,
				       <&adma 7>,  <&adma 7>,
				       <&adma 8>,  <&adma 8>,
				       <&adma 9>,  <&adma 9>,
				       <&adma 10>, <&adma 10>;
				dma-names = "rx1",  "tx1",
					    "rx2",  "tx2",
					    "rx3",  "tx3",
					    "rx4",  "tx4",
					    "rx5",  "tx5",
					    "rx6",  "tx6",
					    "rx7",  "tx7",
					    "rx8",  "tx8",
					    "rx9",  "tx9",
					    "rx10", "tx10";
				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					admaif1_port: port@0 {
						reg = <0>;

						admaif1_ep: endpoint {
							remote-endpoint = <&xbar_admaif1_ep>;
						};
					};

					admaif2_port: port@1 {
						reg = <1>;

						admaif2_ep: endpoint {
							remote-endpoint = <&xbar_admaif2_ep>;
						};
					};

					admaif3_port: port@2 {
						reg = <2>;

						admaif3_ep: endpoint {
							remote-endpoint = <&xbar_admaif3_ep>;
						};
					};

					admaif4_port: port@3 {
						reg = <3>;

						admaif4_ep: endpoint {
							remote-endpoint = <&xbar_admaif4_ep>;
						};
					};

					admaif5_port: port@4 {
						reg = <4>;

						admaif5_ep: endpoint {
							remote-endpoint = <&xbar_admaif5_ep>;
						};
					};

					admaif6_port: port@5 {
						reg = <5>;

						admaif6_ep: endpoint {
							remote-endpoint = <&xbar_admaif6_ep>;
						};
					};

					admaif7_port: port@6 {
						reg = <6>;

						admaif7_ep: endpoint {
							remote-endpoint = <&xbar_admaif7_ep>;
						};
					};

					admaif8_port: port@7 {
						reg = <7>;

						admaif8_ep: endpoint {
							remote-endpoint = <&xbar_admaif8_ep>;
						};
					};

					admaif9_port: port@8 {
						reg = <8>;

						admaif9_ep: endpoint {
							remote-endpoint = <&xbar_admaif9_ep>;
						};
					};

					admaif10_port: port@9 {
						reg = <9>;

						admaif10_ep: endpoint {
							remote-endpoint = <&xbar_admaif10_ep>;
						};
					};
				};
			};

			tegra_i2s1: i2s@702d1000 {
				compatible = "nvidia,tegra210-i2s";
				reg = <0x702d1000 0x100>;
				clocks = <&tegra_car TEGRA210_CLK_I2S0>,
					 <&tegra_car TEGRA210_CLK_I2S0_SYNC>;
				clock-names = "i2s", "sync_input";
				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
				assigned-clock-rates = <1536000>;
				sound-name-prefix = "I2S1";
				status = "disabled";
			};

			tegra_i2s2: i2s@702d1100 {
				compatible = "nvidia,tegra210-i2s";
				reg = <0x702d1100 0x100>;
				clocks = <&tegra_car TEGRA210_CLK_I2S1>,
					 <&tegra_car TEGRA210_CLK_I2S1_SYNC>;
				clock-names = "i2s", "sync_input";
				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>;
				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
				assigned-clock-rates = <1536000>;
				sound-name-prefix = "I2S2";
				status = "disabled";
			};

			tegra_i2s3: i2s@702d1200 {
				compatible = "nvidia,tegra210-i2s";
				reg = <0x702d1200 0x100>;
				clocks = <&tegra_car TEGRA210_CLK_I2S2>,
					 <&tegra_car TEGRA210_CLK_I2S2_SYNC>;
				clock-names = "i2s", "sync_input";
				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>;
				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
				assigned-clock-rates = <1536000>;
				sound-name-prefix = "I2S3";
				status = "disabled";
			};

			tegra_i2s4: i2s@702d1300 {
				compatible = "nvidia,tegra210-i2s";
				reg = <0x702d1300 0x100>;
				clocks = <&tegra_car TEGRA210_CLK_I2S3>,
					 <&tegra_car TEGRA210_CLK_I2S3_SYNC>;
				clock-names = "i2s", "sync_input";
				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>;
				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
				assigned-clock-rates = <1536000>;
				sound-name-prefix = "I2S4";
				status = "disabled";
			};

			tegra_i2s5: i2s@702d1400 {
				compatible = "nvidia,tegra210-i2s";
				reg = <0x702d1400 0x100>;
				clocks = <&tegra_car TEGRA210_CLK_I2S4>,
					 <&tegra_car TEGRA210_CLK_I2S4_SYNC>;
				clock-names = "i2s", "sync_input";
				assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>;
				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
				assigned-clock-rates = <1536000>;
				sound-name-prefix = "I2S5";
				status = "disabled";
			};

			tegra_dmic1: dmic@702d4000 {
				compatible = "nvidia,tegra210-dmic";
				reg = <0x702d4000 0x100>;
				clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
				clock-names = "dmic";
				assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
				assigned-clock-rates = <3072000>;
				sound-name-prefix = "DMIC1";
				status = "disabled";
			};

			tegra_dmic2: dmic@702d4100 {
				compatible = "nvidia,tegra210-dmic";
				reg = <0x702d4100 0x100>;
				clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
				clock-names = "dmic";
				assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
				assigned-clock-rates = <3072000>;
				sound-name-prefix = "DMIC2";
				status = "disabled";
			};

			tegra_dmic3: dmic@702d4200 {
				compatible = "nvidia,tegra210-dmic";
				reg = <0x702d4200 0x100>;
				clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
				clock-names = "dmic";
				assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
				assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
				assigned-clock-rates = <3072000>;
				sound-name-prefix = "DMIC3";
				status = "disabled";
			};

			tegra_sfc1: sfc@702d2000 {
				compatible = "nvidia,tegra210-sfc";
				reg = <0x702d2000 0x200>;
				sound-name-prefix = "SFC1";
				status = "disabled";
			};

			tegra_sfc2: sfc@702d2200 {
				compatible = "nvidia,tegra210-sfc";
				reg = <0x702d2200 0x200>;
				sound-name-prefix = "SFC2";
				status = "disabled";
			};

			tegra_sfc3: sfc@702d2400 {
				compatible = "nvidia,tegra210-sfc";
				reg = <0x702d2400 0x200>;
				sound-name-prefix = "SFC3";
				status = "disabled";
			};

			tegra_sfc4: sfc@702d2600 {
				compatible = "nvidia,tegra210-sfc";
				reg = <0x702d2600 0x200>;
				sound-name-prefix = "SFC4";
				status = "disabled";
			};

			tegra_mvc1: mvc@702da000 {
				compatible = "nvidia,tegra210-mvc";
				reg = <0x702da000 0x200>;
				sound-name-prefix = "MVC1";
				status = "disabled";
			};

			tegra_mvc2: mvc@702da200 {
				compatible = "nvidia,tegra210-mvc";
				reg = <0x702da200 0x200>;
				sound-name-prefix = "MVC2";
				status = "disabled";
			};

			tegra_amx1: amx@702d3000 {
				compatible = "nvidia,tegra210-amx";
				reg = <0x702d3000 0x100>;
				sound-name-prefix = "AMX1";
				status = "disabled";
			};

			tegra_amx2: amx@702d3100 {
				compatible = "nvidia,tegra210-amx";
				reg = <0x702d3100 0x100>;
				sound-name-prefix = "AMX2";
				status = "disabled";
			};

			tegra_adx1: adx@702d3800 {
				compatible = "nvidia,tegra210-adx";
				reg = <0x702d3800 0x100>;
				sound-name-prefix = "ADX1";
				status = "disabled";
			};

			tegra_adx2: adx@702d3900 {
				compatible = "nvidia,tegra210-adx";
				reg = <0x702d3900 0x100>;
				sound-name-prefix = "ADX2";
				status = "disabled";
			};

			tegra_ope1: processing-engine@702d8000 {
				compatible = "nvidia,tegra210-ope";
				reg = <0x702d8000 0x100>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;
				sound-name-prefix = "OPE1";
				status = "disabled";

				equalizer@702d8100 {
					compatible = "nvidia,tegra210-peq";
					reg = <0x702d8100 0x100>;
				};

				dynamic-range-compressor@702d8200 {
					compatible = "nvidia,tegra210-mbdrc";
					reg = <0x702d8200 0x200>;
				};
			};

			tegra_ope2: processing-engine@702d8400 {
				compatible = "nvidia,tegra210-ope";
				reg = <0x702d8400 0x100>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;
				sound-name-prefix = "OPE2";
				status = "disabled";

				equalizer@702d8500 {
					compatible = "nvidia,tegra210-peq";
					reg = <0x702d8500 0x100>;
				};

				dynamic-range-compressor@702d8600 {
					compatible = "nvidia,tegra210-mbdrc";
					reg = <0x702d8600 0x200>;
				};
			};

			tegra_amixer: amixer@702dbb00 {
				compatible = "nvidia,tegra210-amixer";
				reg = <0x702dbb00 0x800>;
				sound-name-prefix = "MIXER1";
				status = "disabled";
			};

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0x0>;

					xbar_admaif1_ep: endpoint {
						remote-endpoint = <&admaif1_ep>;
					};
				};

				port@1 {
					reg = <0x1>;

					xbar_admaif2_ep: endpoint {
						remote-endpoint = <&admaif2_ep>;
					};
				};

				port@2 {
					reg = <0x2>;

					xbar_admaif3_ep: endpoint {
						remote-endpoint = <&admaif3_ep>;
					};
				};

				port@3 {
					reg = <0x3>;

					xbar_admaif4_ep: endpoint {
						remote-endpoint = <&admaif4_ep>;
					};
				};

				port@4 {
					reg = <0x4>;
					xbar_admaif5_ep: endpoint {
						remote-endpoint = <&admaif5_ep>;
					};
				};
				port@5 {
					reg = <0x5>;

					xbar_admaif6_ep: endpoint {
						remote-endpoint = <&admaif6_ep>;
					};
				};

				port@6 {
					reg = <0x6>;

					xbar_admaif7_ep: endpoint {
						remote-endpoint = <&admaif7_ep>;
					};
				};

				port@7 {
					reg = <0x7>;

					xbar_admaif8_ep: endpoint {
						remote-endpoint = <&admaif8_ep>;
					};
				};

				port@8 {
					reg = <0x8>;

					xbar_admaif9_ep: endpoint {
						remote-endpoint = <&admaif9_ep>;
					};
				};

				port@9 {
					reg = <0x9>;

					xbar_admaif10_ep: endpoint {
						remote-endpoint = <&admaif10_ep>;
					};
				};
			};
		};
	};

	spi@70410000 {
		compatible = "nvidia,tegra210-qspi";
		reg = <0x0 0x70410000 0x0 0x1000>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA210_CLK_QSPI>,
			 <&tegra_car TEGRA210_CLK_QSPI_PM>;
		clock-names = "qspi", "qspi_out";
		resets = <&tegra_car 211>;
		dmas = <&apbdma 5>, <&apbdma 5>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	usb@7d000000 {
		compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci";
		reg = <0x0 0x7d000000 0x0 0x4000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA210_CLK_USBD>;
		clock-names = "usb";
		resets = <&tegra_car 22>;
		reset-names = "usb";
		nvidia,phy = <&phy1>;
		status = "disabled";
	};

	phy1: usb-phy@7d000000 {
		compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
		reg = <0x0 0x7d000000 0x0 0x4000>,
		      <0x0 0x7d000000 0x0 0x4000>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA210_CLK_USBD>,
			 <&tegra_car TEGRA210_CLK_PLL_U>,
			 <&tegra_car TEGRA210_CLK_USBD>;
		clock-names = "reg", "pll_u", "utmi-pads";
		resets = <&tegra_car 22>, <&tegra_car 22>;
		reset-names = "usb", "utmi-pads";
		nvidia,hssync-start-delay = <0>;
		nvidia,idle-wait-delay = <17>;
		nvidia,elastic-limit = <16>;
		nvidia,term-range-adj = <6>;
		nvidia,xcvr-setup = <9>;
		nvidia,xcvr-lsfslew = <0>;
		nvidia,xcvr-lsrslew = <3>;
		nvidia,hssquelch-level = <2>;
		nvidia,hsdiscon-level = <5>;
		nvidia,xcvr-hsslew = <12>;
		nvidia,has-utmi-pad-registers;
		status = "disabled";
	};

	usb@7d004000 {
		compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci";
		reg = <0x0 0x7d004000 0x0 0x4000>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA210_CLK_USB2>;
		clock-names = "usb";
		resets = <&tegra_car 58>;
		reset-names = "usb";
		nvidia,phy = <&phy2>;
		status = "disabled";
	};

	phy2: usb-phy@7d004000 {
		compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
		reg = <0x0 0x7d004000 0x0 0x4000>,
		      <0x0 0x7d000000 0x0 0x4000>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA210_CLK_USB2>,
			 <&tegra_car TEGRA210_CLK_PLL_U>,
			 <&tegra_car TEGRA210_CLK_USBD>;
		clock-names = "reg", "pll_u", "utmi-pads";
		resets = <&tegra_car 58>, <&tegra_car 22>;
		reset-names = "usb", "utmi-pads";
		nvidia,hssync-start-delay = <0>;
		nvidia,idle-wait-delay = <17>;
		nvidia,elastic-limit = <16>;
		nvidia,term-range-adj = <6>;
		nvidia,xcvr-setup = <9>;
		nvidia,xcvr-lsfslew = <0>;
		nvidia,xcvr-lsrslew = <3>;
		nvidia,hssquelch-level = <2>;
		nvidia,hsdiscon-level = <5>;
		nvidia,xcvr-hsslew = <12>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0>;
			clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
				 <&tegra_car TEGRA210_CLK_PLL_X>,
				 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
				 <&dfll>;
			clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
			clock-latency = <300000>;
			cpu-idle-states = <&CPU_SLEEP>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <1>;
			cpu-idle-states = <&CPU_SLEEP>;
			next-level-cache = <&L2>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <2>;
			cpu-idle-states = <&CPU_SLEEP>;
			next-level-cache = <&L2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <3>;
			cpu-idle-states = <&CPU_SLEEP>;
			next-level-cache = <&L2>;
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP: cpu-sleep {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x40000007>;
				entry-latency-us = <100>;
				exit-latency-us = <30>;
				min-residency-us = <1000>;
				wakeup-latency-us = <130>;
				idle-state-name = "cpu-sleep";
				status = "disabled";
			};
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
				      &{/cpus/cpu@2} &{/cpus/cpu@3}>;
	};

	sound {
		status = "disabled";

		clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
			 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
		clock-names = "pll_a", "plla_out0";

		assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
				  <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
				  <&tegra_car TEGRA210_CLK_EXTERN1>;
		assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
		assigned-clock-rates = <368640000>, <49152000>, <12288000>;
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <1000>;
			polling-delay = <0>;

			thermal-sensors =
				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;

			trips {
				cpu-shutdown-trip {
					temperature = <102500>;
					hysteresis = <0>;
					type = "critical";
				};

				cpu_throttle_trip: throttle-trip {
					temperature = <98500>;
					hysteresis = <1000>;
					type = "hot";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_throttle_trip>;
					cooling-device = <&throttle_heavy 1 1>;
				};
			};
		};

		mem-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;

			thermal-sensors =
				<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;

			trips {
				dram_nominal: mem-nominal-trip {
					temperature = <50000>;
					hysteresis = <1000>;
					type = "passive";
				};

				dram_throttle: mem-throttle-trip {
					temperature = <70000>;
					hysteresis = <1000>;
					type = "active";
				};

				mem-hot-trip {
					temperature = <100000>;
					hysteresis = <1000>;
					type = "hot";
				};

				mem-shutdown-trip {
					temperature = <103000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
				dram-passive {
					cooling-device = <&emc 0 0>;
					trip = <&dram_nominal>;
				};

				dram-active {
					cooling-device = <&emc 1 1>;
					trip = <&dram_throttle>;
				};
			};
		};

		gpu-thermal {
			polling-delay-passive = <1000>;
			polling-delay = <0>;

			thermal-sensors =
				<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;

			trips {
				gpu-shutdown-trip {
					temperature = <103000>;
					hysteresis = <0>;
					type = "critical";
				};

				gpu_throttle_trip: throttle-trip {
					temperature = <100000>;
					hysteresis = <1000>;
					type = "hot";
				};
			};

			cooling-maps {
				map0 {
					trip = <&gpu_throttle_trip>;
					cooling-device = <&throttle_heavy 1 1>;
				};
			};
		};

		pllx-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;

			thermal-sensors =
				<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;

			trips {
				pllx-shutdown-trip {
					temperature = <103000>;
					hysteresis = <0>;
					type = "critical";
				};

				pllx-throttle-trip {
					temperature = <100000>;
					hysteresis = <1000>;
					type = "hot";
				};
			};

			cooling-maps {
				/*
				 * There are currently no cooling maps,
				 * because there are no cooling devices.
				 */
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&gic>;
		arm,no-tick-in-suspend;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0

#include "tegra234.dtsi"

/ {
	model = "NVIDIA Jetson AGX Orin";
	compatible = "nvidia,p3701-0000", "nvidia,tegra234";

	vdd_1v8_ls: regulator-vdd-1v8-ls {
		compatible = "regulator-fixed";
		regulator-name = "VDD_1V8_LS";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	vdd_1v8_ao: regulator-vdd-1v8-ao {
		compatible = "regulator-fixed";
		regulator-name = "VDD_1V8_AO";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	vdd_3v3_pcie: regulator-vdd-3v3-pcie {
		compatible = "regulator-fixed";
		regulator-name = "VDD_3V3_PCIE";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio TEGRA234_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>;
		regulator-boot-on;
		enable-active-high;
	};

	vdd_12v_pcie: regulator-vdd-12v-pcie {
		compatible = "regulator-fixed";
		regulator-name = "VDD_12V_PCIE";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
		regulator-boot-on;
	};

	bus@0 {
		spi@3270000 {
			status = "okay";

			flash@0 {
				compatible = "jedec,spi-nor";
				reg = <0>;
				spi-max-frequency = <102000000>;
				spi-tx-bus-width = <4>;
				spi-rx-bus-width = <4>;
			};
		};

		mmc@3400000 {
			status = "okay";
			bus-width = <4>;
			cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
			disable-wp;
		};

		mmc@3460000 {
			status = "okay";
			bus-width = <8>;
			non-removable;
		};

		rtc@c2a0000 {
			status = "okay";
		};

		pmc@c360000 {
			nvidia,invert-interrupt;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/input/gpio-keys.h>

#include "tegra234-p3701-0000.dtsi"
#include "tegra234-p3737-0000.dtsi"

/ {
	model = "NVIDIA Jetson AGX Orin Developer Kit";
	compatible = "nvidia,p3737-0000+p3701-0000", "nvidia,p3701-0000", "nvidia,tegra234";

	aliases {
		mmc3 = "/bus@0/mmc@3460000";
		serial0 = &tcu;
		serial1 = &uarta;
	};

	bus@0 {
		aconnect@2900000 {
			status = "okay";

			ahub@2900800 {
				status = "okay";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0x0>;

						xbar_admaif0: endpoint {
							remote-endpoint = <&admaif0>;
						};
					};

					port@1 {
						reg = <0x1>;

						xbar_admaif1: endpoint {
							remote-endpoint = <&admaif1>;
						};
					};

					port@2 {
						reg = <0x2>;

						xbar_admaif2: endpoint {
							remote-endpoint = <&admaif2>;
						};
					};

					port@3 {
						reg = <0x3>;

						xbar_admaif3: endpoint {
							remote-endpoint = <&admaif3>;
						};
					};

					port@4 {
						reg = <0x4>;

						xbar_admaif4: endpoint {
							remote-endpoint = <&admaif4>;
						};
					};

					port@5 {
						reg = <0x5>;

						xbar_admaif5: endpoint {
							remote-endpoint = <&admaif5>;
						};
					};

					port@6 {
						reg = <0x6>;

						xbar_admaif6: endpoint {
							remote-endpoint = <&admaif6>;
						};
					};

					port@7 {
						reg = <0x7>;

						xbar_admaif7: endpoint {
							remote-endpoint = <&admaif7>;
						};
					};

					port@8 {
						reg = <0x8>;

						xbar_admaif8: endpoint {
							remote-endpoint = <&admaif8>;
						};
					};

					port@9 {
						reg = <0x9>;

						xbar_admaif9: endpoint {
							remote-endpoint = <&admaif9>;
						};
					};

					port@a {
						reg = <0xa>;

						xbar_admaif10: endpoint {
							remote-endpoint = <&admaif10>;
						};
					};

					port@b {
						reg = <0xb>;

						xbar_admaif11: endpoint {
							remote-endpoint = <&admaif11>;
						};
					};

					port@c {
						reg = <0xc>;

						xbar_admaif12: endpoint {
							remote-endpoint = <&admaif12>;
						};
					};

					port@d {
						reg = <0xd>;

						xbar_admaif13: endpoint {
							remote-endpoint = <&admaif13>;
						};
					};

					port@e {
						reg = <0xe>;

						xbar_admaif14: endpoint {
							remote-endpoint = <&admaif14>;
						};
					};

					port@f {
						reg = <0xf>;

						xbar_admaif15: endpoint {
							remote-endpoint = <&admaif15>;
						};
					};

					port@10 {
						reg = <0x10>;

						xbar_admaif16: endpoint {
							remote-endpoint = <&admaif16>;
						};
					};

					port@11 {
						reg = <0x11>;

						xbar_admaif17: endpoint {
							remote-endpoint = <&admaif17>;
						};
					};

					port@12 {
						reg = <0x12>;

						xbar_admaif18: endpoint {
							remote-endpoint = <&admaif18>;
						};
					};

					port@13 {
						reg = <0x13>;

						xbar_admaif19: endpoint {
							remote-endpoint = <&admaif19>;
						};
					};

					xbar_i2s1_port: port@14 {
						reg = <0x14>;

						xbar_i2s1: endpoint {
							remote-endpoint = <&i2s1_cif>;
						};
					};

					xbar_i2s2_port: port@15 {
						reg = <0x15>;

						xbar_i2s2: endpoint {
							remote-endpoint = <&i2s2_cif>;
						};
					};

					xbar_i2s4_port: port@17 {
						reg = <0x17>;

						xbar_i2s4: endpoint {
							remote-endpoint = <&i2s4_cif>;
						};
					};

					xbar_i2s6_port: port@19 {
						reg = <0x19>;

						xbar_i2s6: endpoint {
							remote-endpoint = <&i2s6_cif>;
						};
					};

					xbar_dmic3_port: port@1c {
						reg = <0x1c>;

						xbar_dmic3: endpoint {
							remote-endpoint = <&dmic3_cif>;
						};
					};

					xbar_sfc1_in_port: port@20 {
						reg = <0x20>;

						xbar_sfc1_in: endpoint {
							remote-endpoint = <&sfc1_cif_in>;
						};
					};

					port@21 {
						reg = <0x21>;

						xbar_sfc1_out: endpoint {
							remote-endpoint = <&sfc1_cif_out>;
						};
					};

					xbar_sfc2_in_port: port@22 {
						reg = <0x22>;

						xbar_sfc2_in: endpoint {
							remote-endpoint = <&sfc2_cif_in>;
						};
					};

					port@23 {
						reg = <0x23>;

						xbar_sfc2_out: endpoint {
							remote-endpoint = <&sfc2_cif_out>;
						};
					};

					xbar_sfc3_in_port: port@24 {
						reg = <0x24>;

						xbar_sfc3_in: endpoint {
							remote-endpoint = <&sfc3_cif_in>;
						};
					};

					port@25 {
						reg = <0x25>;

						xbar_sfc3_out: endpoint {
							remote-endpoint = <&sfc3_cif_out>;
						};
					};

					xbar_sfc4_in_port: port@26 {
						reg = <0x26>;

						xbar_sfc4_in: endpoint {
							remote-endpoint = <&sfc4_cif_in>;
						};
					};

					port@27 {
						reg = <0x27>;

						xbar_sfc4_out: endpoint {
							remote-endpoint = <&sfc4_cif_out>;
						};
					};

					xbar_mvc1_in_port: port@28 {
						reg = <0x28>;

						xbar_mvc1_in: endpoint {
							remote-endpoint = <&mvc1_cif_in>;
						};
					};

					port@29 {
						reg = <0x29>;

						xbar_mvc1_out: endpoint {
							remote-endpoint = <&mvc1_cif_out>;
						};
					};

					xbar_mvc2_in_port: port@2a {
						reg = <0x2a>;

						xbar_mvc2_in: endpoint {
							remote-endpoint = <&mvc2_cif_in>;
						};
					};

					port@2b {
						reg = <0x2b>;

						xbar_mvc2_out: endpoint {
							remote-endpoint = <&mvc2_cif_out>;
						};
					};

					xbar_amx1_in1_port: port@2c {
						reg = <0x2c>;

						xbar_amx1_in1: endpoint {
							remote-endpoint = <&amx1_in1>;
						};
					};

					xbar_amx1_in2_port: port@2d {
						reg = <0x2d>;

						xbar_amx1_in2: endpoint {
							remote-endpoint = <&amx1_in2>;
						};
					};

					xbar_amx1_in3_port: port@2e {
						reg = <0x2e>;

						xbar_amx1_in3: endpoint {
							remote-endpoint = <&amx1_in3>;
						};
					};

					xbar_amx1_in4_port: port@2f {
						reg = <0x2f>;

						xbar_amx1_in4: endpoint {
							remote-endpoint = <&amx1_in4>;
						};
					};

					port@30 {
						reg = <0x30>;

						xbar_amx1_out: endpoint {
							remote-endpoint = <&amx1_out>;
						};
					};

					xbar_amx2_in1_port: port@31 {
						reg = <0x31>;

						xbar_amx2_in1: endpoint {
							remote-endpoint = <&amx2_in1>;
						};
					};

					xbar_amx2_in2_port: port@32 {
						reg = <0x32>;

						xbar_amx2_in2: endpoint {
							remote-endpoint = <&amx2_in2>;
						};
					};

					xbar_amx2_in3_port: port@33 {
						reg = <0x33>;

						xbar_amx2_in3: endpoint {
							remote-endpoint = <&amx2_in3>;
						};
					};

					xbar_amx2_in4_port: port@34 {
						reg = <0x34>;

						xbar_amx2_in4: endpoint {
							remote-endpoint = <&amx2_in4>;
						};
					};

					port@35 {
						reg = <0x35>;

						xbar_amx2_out: endpoint {
							remote-endpoint = <&amx2_out>;
						};
					};

					xbar_amx3_in1_port: port@36 {
						reg = <0x36>;

						xbar_amx3_in1: endpoint {
							remote-endpoint = <&amx3_in1>;
						};
					};

					xbar_amx3_in2_port: port@37 {
						reg = <0x37>;

						xbar_amx3_in2: endpoint {
							remote-endpoint = <&amx3_in2>;
						};
					};

					xbar_amx3_in3_port: port@38 {
						reg = <0x38>;

						xbar_amx3_in3: endpoint {
							remote-endpoint = <&amx3_in3>;
						};
					};

					xbar_amx3_in4_port: port@39 {
						reg = <0x39>;

						xbar_amx3_in4: endpoint {
							remote-endpoint = <&amx3_in4>;
						};
					};

					port@3a {
						reg = <0x3a>;

						xbar_amx3_out: endpoint {
							remote-endpoint = <&amx3_out>;
						};
					};

					xbar_amx4_in1_port: port@3b {
						reg = <0x3b>;

						xbar_amx4_in1: endpoint {
							remote-endpoint = <&amx4_in1>;
						};
					};

					xbar_amx4_in2_port: port@3c {
						reg = <0x3c>;

						xbar_amx4_in2: endpoint {
							remote-endpoint = <&amx4_in2>;
						};
					};

					xbar_amx4_in3_port: port@3d {
						reg = <0x3d>;

						xbar_amx4_in3: endpoint {
							remote-endpoint = <&amx4_in3>;
						};
					};

					xbar_amx4_in4_port: port@3e {
						reg = <0x3e>;

						xbar_amx4_in4: endpoint {
							remote-endpoint = <&amx4_in4>;
						};
					};

					port@3f {
						reg = <0x3f>;

						xbar_amx4_out: endpoint {
							remote-endpoint = <&amx4_out>;
						};
					};

					xbar_adx1_in_port: port@40 {
						reg = <0x40>;

						xbar_adx1_in: endpoint {
							remote-endpoint = <&adx1_in>;
						};
					};

					port@41 {
						reg = <0x41>;

						xbar_adx1_out1: endpoint {
							remote-endpoint = <&adx1_out1>;
						};
					};

					port@42 {
						reg = <0x42>;

						xbar_adx1_out2: endpoint {
							remote-endpoint = <&adx1_out2>;
						};
					};

					port@43 {
						reg = <0x43>;

						xbar_adx1_out3: endpoint {
							remote-endpoint = <&adx1_out3>;
						};
					};

					port@44 {
						reg = <0x44>;

						xbar_adx1_out4: endpoint {
							remote-endpoint = <&adx1_out4>;
						};
					};

					xbar_adx2_in_port: port@45 {
						reg = <0x45>;

						xbar_adx2_in: endpoint {
							remote-endpoint = <&adx2_in>;
						};
					};

					port@46 {
						reg = <0x46>;

						xbar_adx2_out1: endpoint {
							remote-endpoint = <&adx2_out1>;
						};
					};

					port@47 {
						reg = <0x47>;

						xbar_adx2_out2: endpoint {
							remote-endpoint = <&adx2_out2>;
						};
					};

					port@48 {
						reg = <0x48>;

						xbar_adx2_out3: endpoint {
							remote-endpoint = <&adx2_out3>;
						};
					};

					port@49 {
						reg = <0x49>;

						xbar_adx2_out4: endpoint {
							remote-endpoint = <&adx2_out4>;
						};
					};

					xbar_adx3_in_port: port@4a {
						reg = <0x4a>;

						xbar_adx3_in: endpoint {
							remote-endpoint = <&adx3_in>;
						};
					};

					port@4b {
						reg = <0x4b>;

						xbar_adx3_out1: endpoint {
							remote-endpoint = <&adx3_out1>;
						};
					};

					port@4c {
						reg = <0x4c>;

						xbar_adx3_out2: endpoint {
							remote-endpoint = <&adx3_out2>;
						};
					};

					port@4d {
						reg = <0x4d>;

						xbar_adx3_out3: endpoint {
							remote-endpoint = <&adx3_out3>;
						};
					};

					port@4e {
						reg = <0x4e>;

						xbar_adx3_out4: endpoint {
							remote-endpoint = <&adx3_out4>;
						};
					};

					xbar_adx4_in_port: port@4f {
						reg = <0x4f>;

						xbar_adx4_in: endpoint {
							remote-endpoint = <&adx4_in>;
						};
					};

					port@50 {
						reg = <0x50>;

						xbar_adx4_out1: endpoint {
							remote-endpoint = <&adx4_out1>;
						};
					};

					port@51 {
						reg = <0x51>;

						xbar_adx4_out2: endpoint {
							remote-endpoint = <&adx4_out2>;
						};
					};

					port@52 {
						reg = <0x52>;

						xbar_adx4_out3: endpoint {
							remote-endpoint = <&adx4_out3>;
						};
					};

					port@53 {
						reg = <0x53>;

						xbar_adx4_out4: endpoint {
							remote-endpoint = <&adx4_out4>;
						};
					};

					xbar_mix_in1_port: port@54 {
						reg = <0x54>;

						xbar_mix_in1: endpoint {
							remote-endpoint = <&mix_in1>;
						};
					};

					xbar_mix_in2_port: port@55 {
						reg = <0x55>;

						xbar_mix_in2: endpoint {
							remote-endpoint = <&mix_in2>;
						};
					};

					xbar_mix_in3_port: port@56 {
						reg = <0x56>;

						xbar_mix_in3: endpoint {
							remote-endpoint = <&mix_in3>;
						};
					};

					xbar_mix_in4_port: port@57 {
						reg = <0x57>;

						xbar_mix_in4: endpoint {
							remote-endpoint = <&mix_in4>;
						};
					};

					xbar_mix_in5_port: port@58 {
						reg = <0x58>;

						xbar_mix_in5: endpoint {
							remote-endpoint = <&mix_in5>;
						};
					};

					xbar_mix_in6_port: port@59 {
						reg = <0x59>;

						xbar_mix_in6: endpoint {
							remote-endpoint = <&mix_in6>;
						};
					};

					xbar_mix_in7_port: port@5a {
						reg = <0x5a>;

						xbar_mix_in7: endpoint {
							remote-endpoint = <&mix_in7>;
						};
					};

					xbar_mix_in8_port: port@5b {
						reg = <0x5b>;

						xbar_mix_in8: endpoint {
							remote-endpoint = <&mix_in8>;
						};
					};

					xbar_mix_in9_port: port@5c {
						reg = <0x5c>;

						xbar_mix_in9: endpoint {
							remote-endpoint = <&mix_in9>;
						};
					};

					xbar_mix_in10_port: port@5d {
						reg = <0x5d>;

						xbar_mix_in10: endpoint {
							remote-endpoint = <&mix_in10>;
						};
					};

					port@5e {
						reg = <0x5e>;

						xbar_mix_out1: endpoint {
							remote-endpoint = <&mix_out1>;
						};
					};

					port@5f {
						reg = <0x5f>;

						xbar_mix_out2: endpoint {
							remote-endpoint = <&mix_out2>;
						};
					};

					port@60 {
						reg = <0x60>;

						xbar_mix_out3: endpoint {
							remote-endpoint = <&mix_out3>;
						};
					};

					port@61 {
						reg = <0x61>;

						xbar_mix_out4: endpoint {
							remote-endpoint = <&mix_out4>;
						};
					};

					port@62 {
						reg = <0x62>;

						xbar_mix_out5: endpoint {
							remote-endpoint = <&mix_out5>;
						};
					};

					xbar_asrc_in1_port: port@63 {
						reg = <0x63>;

						xbar_asrc_in1_ep: endpoint {
							remote-endpoint = <&asrc_in1_ep>;
						};
					};

					port@64 {
						reg = <0x64>;

						xbar_asrc_out1_ep: endpoint {
							remote-endpoint = <&asrc_out1_ep>;
						};
					};

					xbar_asrc_in2_port: port@65 {
						reg = <0x65>;

						xbar_asrc_in2_ep: endpoint {
							remote-endpoint = <&asrc_in2_ep>;
						};
					};

					port@66 {
						reg = <0x66>;

						xbar_asrc_out2_ep: endpoint {
							remote-endpoint = <&asrc_out2_ep>;
						};
					};

					xbar_asrc_in3_port: port@67 {
						reg = <0x67>;

						xbar_asrc_in3_ep: endpoint {
							remote-endpoint = <&asrc_in3_ep>;
						};
					};

					port@68 {
						reg = <0x68>;

						xbar_asrc_out3_ep: endpoint {
							remote-endpoint = <&asrc_out3_ep>;
						};
					};

					xbar_asrc_in4_port: port@69 {
						reg = <0x69>;

						xbar_asrc_in4_ep: endpoint {
							remote-endpoint = <&asrc_in4_ep>;
						};
					};

					port@6a {
						reg = <0x6a>;

						xbar_asrc_out4_ep: endpoint {
							remote-endpoint = <&asrc_out4_ep>;
						};
					};

					xbar_asrc_in5_port: port@6b {
						reg = <0x6b>;

						xbar_asrc_in5_ep: endpoint {
							remote-endpoint = <&asrc_in5_ep>;
						};
					};

					port@6c {
						reg = <0x6c>;

						xbar_asrc_out5_ep: endpoint {
							remote-endpoint = <&asrc_out5_ep>;
						};
					};

					xbar_asrc_in6_port: port@6d {
						reg = <0x6d>;

						xbar_asrc_in6_ep: endpoint {
							remote-endpoint = <&asrc_in6_ep>;
						};
					};

					port@6e {
						reg = <0x6e>;

						xbar_asrc_out6_ep: endpoint {
							remote-endpoint = <&asrc_out6_ep>;
						};
					};

					xbar_asrc_in7_port: port@6f {
						reg = <0x6f>;

						xbar_asrc_in7_ep: endpoint {
							remote-endpoint = <&asrc_in7_ep>;
						};
					};

					xbar_ope1_in_port: port@70 {
						reg = <0x70>;

						xbar_ope1_in_ep: endpoint {
							remote-endpoint = <&ope1_cif_in_ep>;
						};
					};

					port@71 {
						reg = <0x71>;

						xbar_ope1_out_ep: endpoint {
							remote-endpoint = <&ope1_cif_out_ep>;
						};
					};
				};

				i2s@2901000 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							i2s1_cif: endpoint {
								remote-endpoint = <&xbar_i2s1>;
							};
						};

						i2s1_port: port@1 {
							reg = <1>;

							i2s1_dap: endpoint {
								dai-format = "i2s";
								/* placeholder for external codec */
							};
						};
					};
				};

				i2s@2901100 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							i2s2_cif: endpoint {
								remote-endpoint = <&xbar_i2s2>;
							};
						};

						i2s2_port: port@1 {
							reg = <1>;

							i2s2_dap: endpoint {
								dai-format = "i2s";
								/* placeholder for external codec */
							};
						};
					};
				};

				i2s@2901300 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							i2s4_cif: endpoint {
								remote-endpoint = <&xbar_i2s4>;
							};
						};

						i2s4_port: port@1 {
							reg = <1>;

							i2s4_dap: endpoint {
								dai-format = "i2s";
								/* placeholder for external codec */
							};
						};
					};
				};

				i2s@2901500 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							i2s6_cif: endpoint {
								remote-endpoint = <&xbar_i2s6>;
							};
						};

						i2s6_port: port@1 {
							reg = <1>;

							i2s6_dap: endpoint {
								dai-format = "i2s";
								/* placeholder for external codec */
							};
						};
					};
				};

				sfc@2902000 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							sfc1_cif_in: endpoint {
								remote-endpoint = <&xbar_sfc1_in>;
							};
						};

						sfc1_out_port: port@1 {
							reg = <1>;

							sfc1_cif_out: endpoint {
								remote-endpoint = <&xbar_sfc1_out>;
							};
						};
					};
				};

				sfc@2902200 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							sfc2_cif_in: endpoint {
								remote-endpoint = <&xbar_sfc2_in>;
							};
						};

						sfc2_out_port: port@1 {
							reg = <1>;

							sfc2_cif_out: endpoint {
								remote-endpoint = <&xbar_sfc2_out>;
							};
						};
					};
				};

				sfc@2902400 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							sfc3_cif_in: endpoint {
								remote-endpoint = <&xbar_sfc3_in>;
							};
						};

						sfc3_out_port: port@1 {
							reg = <1>;

							sfc3_cif_out: endpoint {
								remote-endpoint = <&xbar_sfc3_out>;
							};
						};
					};
				};

				sfc@2902600 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							sfc4_cif_in: endpoint {
								remote-endpoint = <&xbar_sfc4_in>;
							};
						};

						sfc4_out_port: port@1 {
							reg = <1>;

							sfc4_cif_out: endpoint {
								remote-endpoint = <&xbar_sfc4_out>;
							};
						};
					};
				};

				amx@2903000 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							amx1_in1: endpoint {
								remote-endpoint = <&xbar_amx1_in1>;
							};
						};

						port@1 {
							reg = <1>;

							amx1_in2: endpoint {
								remote-endpoint = <&xbar_amx1_in2>;
							};
						};

						port@2 {
							reg = <2>;

							amx1_in3: endpoint {
								remote-endpoint = <&xbar_amx1_in3>;
							};
						};

						port@3 {
							reg = <3>;

							amx1_in4: endpoint {
								remote-endpoint = <&xbar_amx1_in4>;
							};
						};

						amx1_out_port: port@4 {
							reg = <4>;

							amx1_out: endpoint {
								remote-endpoint = <&xbar_amx1_out>;
							};
						};
					};
				};

				amx@2903100 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							amx2_in1: endpoint {
								remote-endpoint = <&xbar_amx2_in1>;
							};
						};

						port@1 {
							reg = <1>;

							amx2_in2: endpoint {
								remote-endpoint = <&xbar_amx2_in2>;
							};
						};

						port@2 {
							reg = <2>;

							amx2_in3: endpoint {
								remote-endpoint = <&xbar_amx2_in3>;
							};
						};

						port@3 {
							reg = <3>;

							amx2_in4: endpoint {
								remote-endpoint = <&xbar_amx2_in4>;
							};
						};

						amx2_out_port: port@4 {
							reg = <4>;

							amx2_out: endpoint {
								remote-endpoint = <&xbar_amx2_out>;
							};
						};
					};
				};

				amx@2903200 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							amx3_in1: endpoint {
								remote-endpoint = <&xbar_amx3_in1>;
							};
						};

						port@1 {
							reg = <1>;

							amx3_in2: endpoint {
								remote-endpoint = <&xbar_amx3_in2>;
							};
						};

						port@2 {
							reg = <2>;

							amx3_in3: endpoint {
								remote-endpoint = <&xbar_amx3_in3>;
							};
						};

						port@3 {
							reg = <3>;

							amx3_in4: endpoint {
								remote-endpoint = <&xbar_amx3_in4>;
							};
						};

						amx3_out_port: port@4 {
							reg = <4>;

							amx3_out: endpoint {
								remote-endpoint = <&xbar_amx3_out>;
							};
						};
					};
				};

				amx@2903300 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							amx4_in1: endpoint {
								remote-endpoint = <&xbar_amx4_in1>;
							};
						};

						port@1 {
							reg = <1>;

							amx4_in2: endpoint {
								remote-endpoint = <&xbar_amx4_in2>;
							};
						};

						port@2 {
							reg = <2>;

							amx4_in3: endpoint {
								remote-endpoint = <&xbar_amx4_in3>;
							};
						};

						port@3 {
							reg = <3>;

							amx4_in4: endpoint {
								remote-endpoint = <&xbar_amx4_in4>;
							};
						};

						amx4_out_port: port@4 {
							reg = <4>;

							amx4_out: endpoint {
								remote-endpoint = <&xbar_amx4_out>;
							};
						};
					};
				};

				adx@2903800 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							adx1_in: endpoint {
								remote-endpoint = <&xbar_adx1_in>;
							};
						};

						adx1_out1_port: port@1 {
							reg = <1>;

							adx1_out1: endpoint {
								remote-endpoint = <&xbar_adx1_out1>;
							};
						};

						adx1_out2_port: port@2 {
							reg = <2>;

							adx1_out2: endpoint {
								remote-endpoint = <&xbar_adx1_out2>;
							};
						};

						adx1_out3_port: port@3 {
							reg = <3>;

							adx1_out3: endpoint {
								remote-endpoint = <&xbar_adx1_out3>;
							};
						};

						adx1_out4_port: port@4 {
							reg = <4>;

							adx1_out4: endpoint {
								remote-endpoint = <&xbar_adx1_out4>;
							};
						};
					};
				};

				adx@2903900 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							adx2_in: endpoint {
								remote-endpoint = <&xbar_adx2_in>;
							};
						};

						adx2_out1_port: port@1 {
							reg = <1>;

							adx2_out1: endpoint {
								remote-endpoint = <&xbar_adx2_out1>;
							};
						};

						adx2_out2_port: port@2 {
							reg = <2>;

							adx2_out2: endpoint {
								remote-endpoint = <&xbar_adx2_out2>;
							};
						};

						adx2_out3_port: port@3 {
							reg = <3>;

							adx2_out3: endpoint {
								remote-endpoint = <&xbar_adx2_out3>;
							};
						};

						adx2_out4_port: port@4 {
							reg = <4>;

							adx2_out4: endpoint {
								remote-endpoint = <&xbar_adx2_out4>;
							};
						};
					};
				};

				adx@2903a00 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							adx3_in: endpoint {
								remote-endpoint = <&xbar_adx3_in>;
							};
						};

						adx3_out1_port: port@1 {
							reg = <1>;

							adx3_out1: endpoint {
								remote-endpoint = <&xbar_adx3_out1>;
							};
						};

						adx3_out2_port: port@2 {
							reg = <2>;

							adx3_out2: endpoint {
								remote-endpoint = <&xbar_adx3_out2>;
							};
						};

						adx3_out3_port: port@3 {
							reg = <3>;

							adx3_out3: endpoint {
								remote-endpoint = <&xbar_adx3_out3>;
							};
						};

						adx3_out4_port: port@4 {
							reg = <4>;

							adx3_out4: endpoint {
								remote-endpoint = <&xbar_adx3_out4>;
							};
						};
					};
				};

				adx@2903b00 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							adx4_in: endpoint {
								remote-endpoint = <&xbar_adx4_in>;
							};
						};

						adx4_out1_port: port@1 {
							reg = <1>;

							adx4_out1: endpoint {
								remote-endpoint = <&xbar_adx4_out1>;
							};
						};

						adx4_out2_port: port@2 {
							reg = <2>;

							adx4_out2: endpoint {
								remote-endpoint = <&xbar_adx4_out2>;
							};
						};

						adx4_out3_port: port@3 {
							reg = <3>;

							adx4_out3: endpoint {
								remote-endpoint = <&xbar_adx4_out3>;
							};
						};

						adx4_out4_port: port@4 {
							reg = <4>;

							adx4_out4: endpoint {
								remote-endpoint = <&xbar_adx4_out4>;
							};
						};
					};
				};

				dmic@2904200 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							dmic3_cif: endpoint {
								remote-endpoint = <&xbar_dmic3>;
							};
						};

						dmic3_port: port@1 {
							reg = <1>;

							dmic3_dap: endpoint {
								/* placeholder for external codec */
							};
						};
					};
				};

				processing-engine@2908000 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0x0>;

							ope1_cif_in_ep: endpoint {
								remote-endpoint = <&xbar_ope1_in_ep>;
							};
						};

						ope1_out_port: port@1 {
							reg = <0x1>;

							ope1_cif_out_ep: endpoint {
								remote-endpoint = <&xbar_ope1_out_ep>;
							};
						};
					};
				};

				mvc@290a000 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							mvc1_cif_in: endpoint {
								remote-endpoint = <&xbar_mvc1_in>;
							};
						};

						mvc1_out_port: port@1 {
							reg = <1>;

							mvc1_cif_out: endpoint {
								remote-endpoint = <&xbar_mvc1_out>;
							};
						};
					};
				};

				mvc@290a200 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0>;

							mvc2_cif_in: endpoint {
								remote-endpoint = <&xbar_mvc2_in>;
							};
						};

						mvc2_out_port: port@1 {
							reg = <1>;

							mvc2_cif_out: endpoint {
								remote-endpoint = <&xbar_mvc2_out>;
							};
						};
					};
				};

				amixer@290bb00 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0x0>;

							mix_in1: endpoint {
								remote-endpoint = <&xbar_mix_in1>;
							};
						};

						port@1 {
							reg = <0x1>;

							mix_in2: endpoint {
								remote-endpoint = <&xbar_mix_in2>;
							};
						};

						port@2 {
							reg = <0x2>;

							mix_in3: endpoint {
								remote-endpoint = <&xbar_mix_in3>;
							};
						};

						port@3 {
							reg = <0x3>;

							mix_in4: endpoint {
								remote-endpoint = <&xbar_mix_in4>;
							};
						};

						port@4 {
							reg = <0x4>;

							mix_in5: endpoint {
								remote-endpoint = <&xbar_mix_in5>;
							};
						};

						port@5 {
							reg = <0x5>;

							mix_in6: endpoint {
								remote-endpoint = <&xbar_mix_in6>;
							};
						};

						port@6 {
							reg = <0x6>;

							mix_in7: endpoint {
								remote-endpoint = <&xbar_mix_in7>;
							};
						};

						port@7 {
							reg = <0x7>;

							mix_in8: endpoint {
								remote-endpoint = <&xbar_mix_in8>;
							};
						};

						port@8 {
							reg = <0x8>;

							mix_in9: endpoint {
								remote-endpoint = <&xbar_mix_in9>;
							};
						};

						port@9 {
							reg = <0x9>;

							mix_in10: endpoint {
								remote-endpoint = <&xbar_mix_in10>;
							};
						};

						mix_out1_port: port@a {
							reg = <0xa>;

							mix_out1: endpoint {
								remote-endpoint = <&xbar_mix_out1>;
							};
						};

						mix_out2_port: port@b {
							reg = <0xb>;

							mix_out2: endpoint {
								remote-endpoint = <&xbar_mix_out2>;
							};
						};

						mix_out3_port: port@c {
							reg = <0xc>;

							mix_out3: endpoint {
								remote-endpoint = <&xbar_mix_out3>;
							};
						};

						mix_out4_port: port@d {
							reg = <0xd>;

							mix_out4: endpoint {
								remote-endpoint = <&xbar_mix_out4>;
							};
						};

						mix_out5_port: port@e {
							reg = <0xe>;

							mix_out5: endpoint {
								remote-endpoint = <&xbar_mix_out5>;
							};
						};
					};
				};

				admaif@290f000 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						admaif0_port: port@0 {
							reg = <0x0>;

							admaif0: endpoint {
								remote-endpoint = <&xbar_admaif0>;
							};
						};

						admaif1_port: port@1 {
							reg = <0x1>;

							admaif1: endpoint {
								remote-endpoint = <&xbar_admaif1>;
							};
						};

						admaif2_port: port@2 {
							reg = <0x2>;

							admaif2: endpoint {
								remote-endpoint = <&xbar_admaif2>;
							};
						};

						admaif3_port: port@3 {
							reg = <0x3>;

							admaif3: endpoint {
								remote-endpoint = <&xbar_admaif3>;
							};
						};

						admaif4_port: port@4 {
							reg = <0x4>;

							admaif4: endpoint {
								remote-endpoint = <&xbar_admaif4>;
							};
						};

						admaif5_port: port@5 {
							reg = <0x5>;

							admaif5: endpoint {
								remote-endpoint = <&xbar_admaif5>;
							};
						};

						admaif6_port: port@6 {
							reg = <0x6>;

							admaif6: endpoint {
								remote-endpoint = <&xbar_admaif6>;
							};
						};

						admaif7_port: port@7 {
							reg = <0x7>;

							admaif7: endpoint {
								remote-endpoint = <&xbar_admaif7>;
							};
						};

						admaif8_port: port@8 {
							reg = <0x8>;

							admaif8: endpoint {
								remote-endpoint = <&xbar_admaif8>;
							};
						};

						admaif9_port: port@9 {
							reg = <0x9>;

							admaif9: endpoint {
								remote-endpoint = <&xbar_admaif9>;
							};
						};

						admaif10_port: port@a {
							reg = <0xa>;

							admaif10: endpoint {
								remote-endpoint = <&xbar_admaif10>;
							};
						};

						admaif11_port: port@b {
							reg = <0xb>;

							admaif11: endpoint {
								remote-endpoint = <&xbar_admaif11>;
							};
						};

						admaif12_port: port@c {
							reg = <0xc>;

							admaif12: endpoint {
								remote-endpoint = <&xbar_admaif12>;
							};
						};

						admaif13_port: port@d {
							reg = <0xd>;

							admaif13: endpoint {
								remote-endpoint = <&xbar_admaif13>;
							};
						};

						admaif14_port: port@e {
							reg = <0xe>;

							admaif14: endpoint {
								remote-endpoint = <&xbar_admaif14>;
							};
						};

						admaif15_port: port@f {
							reg = <0xf>;

							admaif15: endpoint {
								remote-endpoint = <&xbar_admaif15>;
							};
						};

						admaif16_port: port@10 {
							reg = <0x10>;

							admaif16: endpoint {
								remote-endpoint = <&xbar_admaif16>;
							};
						};

						admaif17_port: port@11 {
							reg = <0x11>;

							admaif17: endpoint {
								remote-endpoint = <&xbar_admaif17>;
							};
						};

						admaif18_port: port@12 {
							reg = <0x12>;

							admaif18: endpoint {
								remote-endpoint = <&xbar_admaif18>;
							};
						};

						admaif19_port: port@13 {
							reg = <0x13>;

							admaif19: endpoint {
								remote-endpoint = <&xbar_admaif19>;
							};
						};
					};
				};

				asrc@2910000 {
					status = "okay";

					ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
							reg = <0x0>;

							asrc_in1_ep: endpoint {
								remote-endpoint = <&xbar_asrc_in1_ep>;
							};
						};

						port@1 {
							reg = <0x1>;

							asrc_in2_ep: endpoint {
								remote-endpoint = <&xbar_asrc_in2_ep>;
							};
						};

						port@2 {
							reg = <0x2>;

							asrc_in3_ep: endpoint {
								remote-endpoint = <&xbar_asrc_in3_ep>;
							};
						};

						port@3 {
							reg = <0x3>;

							asrc_in4_ep: endpoint {
								remote-endpoint = <&xbar_asrc_in4_ep>;
							};
						};

						port@4 {
							reg = <0x4>;

							asrc_in5_ep: endpoint {
								remote-endpoint = <&xbar_asrc_in5_ep>;
							};
						};

						port@5 {
							reg = <0x5>;

							asrc_in6_ep: endpoint {
								remote-endpoint = <&xbar_asrc_in6_ep>;
							};
						};

						port@6 {
							reg = <0x6>;

							asrc_in7_ep: endpoint {
								remote-endpoint = <&xbar_asrc_in7_ep>;
							};
						};

						asrc_out1_port: port@7 {
							reg = <0x7>;

							asrc_out1_ep: endpoint {
								remote-endpoint = <&xbar_asrc_out1_ep>;
							};
						};

						asrc_out2_port: port@8 {
							reg = <0x8>;

							asrc_out2_ep: endpoint {
								remote-endpoint = <&xbar_asrc_out2_ep>;
							};
						};

						asrc_out3_port: port@9 {
							reg = <0x9>;

							asrc_out3_ep: endpoint {
								remote-endpoint = <&xbar_asrc_out3_ep>;
							};
						};

						asrc_out4_port: port@a {
							reg = <0xa>;

							asrc_out4_ep: endpoint {
								remote-endpoint = <&xbar_asrc_out4_ep>;
							};
						};

						asrc_out5_port: port@b {
							reg = <0xb>;

							asrc_out5_ep: endpoint {
								remote-endpoint = <&xbar_asrc_out5_ep>;
							};
						};

						asrc_out6_port:	port@c {
							reg = <0xc>;

							asrc_out6_ep: endpoint {
								remote-endpoint = <&xbar_asrc_out6_ep>;
							};
						};
					};
				};
			};

			dma-controller@2930000 {
				status = "okay";
			};

			interrupt-controller@2a40000 {
				status = "okay";
			};
		};

		serial@3100000 {
			compatible = "nvidia,tegra194-hsuart";
			status = "okay";
		};

		serial@31d0000 {
			current-speed = <115200>;
			status = "okay";
		};

		pwm@32a0000 {
			assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
			status = "okay";
		};

		hda@3510000 {
			nvidia,model = "NVIDIA Jetson AGX Orin HDA";
			status = "okay";
		};
	};

	chosen {
		bootargs = "console=ttyTCU0,115200n8";
		stdout-path = "serial0:115200n8";
	};

	bus@0 {
		ethernet@6800000 {
			status = "okay";

			phy-handle = <&mgbe0_phy>;
			phy-mode = "usxgmii";

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				mgbe0_phy: phy@0 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x0>;

					#phy-cells = <0>;
				};
			};
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		status = "okay";

		key-force-recovery {
			label = "Force Recovery";
			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
			linux,input-type = <EV_KEY>;
			linux,code = <BTN_1>;
		};

		key-power {
			label = "Power";
			gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
			linux,input-type = <EV_KEY>;
			linux,code = <KEY_POWER>;
			wakeup-event-action = <EV_ACT_ASSERTED>;
			wakeup-source;
		};

		key-suspend {
			label = "Suspend";
			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>;
			linux,input-type = <EV_KEY>;
			linux,code = <KEY_SLEEP>;
		};
	};

	serial {
		status = "okay";
	};

	sound {
		status = "okay";

		compatible = "nvidia,tegra186-audio-graph-card";

		dais = /* ADMAIF (FE) Ports */
		       <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
		       <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
		       <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
		       <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
		       /* XBAR Ports */
		       <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>,
		       <&xbar_i2s6_port>, <&xbar_dmic3_port>,
		       <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
		       <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
		       <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
		       <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
		       <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
		       <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
		       <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
		       <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>,
		       <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>,
		       <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>,
		       <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>,
		       <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
		       <&xbar_adx3_in_port>, <&xbar_adx4_in_port>,
		       <&xbar_mix_in1_port>, <&xbar_mix_in2_port>,
		       <&xbar_mix_in3_port>, <&xbar_mix_in4_port>,
		       <&xbar_mix_in5_port>, <&xbar_mix_in6_port>,
		       <&xbar_mix_in7_port>, <&xbar_mix_in8_port>,
		       <&xbar_mix_in9_port>, <&xbar_mix_in10_port>,
		       <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>,
		       <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>,
		       <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>,
		       <&xbar_asrc_in7_port>,
		       <&xbar_ope1_in_port>,
		       /* HW accelerators */
		       <&sfc1_out_port>, <&sfc2_out_port>,
		       <&sfc3_out_port>, <&sfc4_out_port>,
		       <&mvc1_out_port>, <&mvc2_out_port>,
		       <&amx1_out_port>, <&amx2_out_port>,
		       <&amx3_out_port>, <&amx4_out_port>,
		       <&adx1_out1_port>, <&adx1_out2_port>,
		       <&adx1_out3_port>, <&adx1_out4_port>,
		       <&adx2_out1_port>, <&adx2_out2_port>,
		       <&adx2_out3_port>, <&adx2_out4_port>,
		       <&adx3_out1_port>, <&adx3_out2_port>,
		       <&adx3_out3_port>, <&adx3_out4_port>,
		       <&adx4_out1_port>, <&adx4_out2_port>,
		       <&adx4_out3_port>, <&adx4_out4_port>,
		       <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>,
		       <&mix_out4_port>, <&mix_out5_port>,
		       <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>,
		       <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>,
		       <&ope1_out_port>,
		       /* BE I/O Ports */
		       <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
		       <&dmic3_port>;

		label = "NVIDIA Jetson AGX Orin APE";
	};

	pcie@14100000 {
		status = "okay";

		vddio-pex-ctl-supply = <&vdd_1v8_ao>;

		phys = <&p2u_hsio_3>;
		phy-names = "p2u-0";
	};

	pcie@14160000 {
		status = "okay";

		vddio-pex-ctl-supply = <&vdd_1v8_ao>;

		phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
		       <&p2u_hsio_7>;
		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
	};

	pcie@141a0000 {
		status = "okay";

		vddio-pex-ctl-supply = <&vdd_1v8_ls>;
		vpcie3v3-supply = <&vdd_3v3_pcie>;
		vpcie12v-supply = <&vdd_12v_pcie>;

		phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
		       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
		       <&p2u_nvhs_6>, <&p2u_nvhs_7>;
		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
			    "p2u-5", "p2u-6", "p2u-7";
	};

	pcie-ep@141a0000 {
		status = "disabled";

		vddio-pex-ctl-supply = <&vdd_1v8_ls>;

		reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;

		nvidia,refclk-select-gpios = <&gpio_aon
					      TEGRA234_AON_GPIO(AA, 4)
					      GPIO_ACTIVE_HIGH>;

		phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
		       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
		       <&p2u_nvhs_6>, <&p2u_nvhs_7>;
		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
			    "p2u-5", "p2u-6", "p2u-7";
	};

	pwm-fan {
		compatible = "pwm-fan";
		pwms = <&pwm3 0 45334>;

		cooling-levels = <0 95 178 255>;
		#cooling-cells = <2>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0

/ {
	compatible = "nvidia,p3737-0000";

	bus@0 {
		pwm@3280000 {
			status = "okay";
		};

		pwm@32c0000 {
			status = "okay";
		};

		pwm@32f0000 {
			status = "okay";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include "tegra234.dtsi"

/ {
	model = "NVIDIA Tegra234 VDK";
	compatible = "nvidia,tegra234-vdk", "nvidia,tegra234";

	aliases {
		mmc3 = "/bus@0/mmc@3460000";
		serial0 = &uarta;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x03100000";
		stdout-path = "serial0:115200n8";
	};

	bus@0 {
		serial@3100000 {
			status = "okay";
		};

		mmc@3460000 {
			status = "okay";
			bus-width = <8>;
			non-removable;
		};

		rtc@c2a0000 {
			status = "okay";
		};

		pmc@c360000 {
			nvidia,invert-interrupt;
		};
	};
};