code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/qcom,qfprom.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies Inc, QFPROM Efuse bindings

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    items:
      - enum:
          - qcom,apq8064-qfprom
          - qcom,apq8084-qfprom
          - qcom,ipq8064-qfprom
          - qcom,msm8974-qfprom
          - qcom,msm8916-qfprom
          - qcom,msm8996-qfprom
          - qcom,msm8998-qfprom
          - qcom,qcs404-qfprom
          - qcom,sc7180-qfprom
          - qcom,sc7280-qfprom
          - qcom,sdm630-qfprom
          - qcom,sdm845-qfprom
          - qcom,sm6115-qfprom
      - const: qcom,qfprom

  reg:
    # If the QFPROM is read-only OS image then only the corrected region
    # needs to be provided.  If the QFPROM is writable then all 4 regions
    # must be provided.
    oneOf:
      - items:
          - description: The corrected region.
      - items:
          - description: The corrected region.
          - description: The raw region.
          - description: The config region.
          - description: The security control region.

  # Clock must be provided if QFPROM is writable from the OS image.
  clocks:
    maxItems: 1
  clock-names:
    const: core

  # Supply reference must be provided if QFPROM is writable from the OS image.
  vcc-supply:
    description: Our power supply.

  power-domains:
    maxItems: 1

  # Needed if any child nodes are present.
  "#address-cells":
    const: 1
  "#size-cells":
    const: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc7180.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      efuse@784000 {
        compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
        reg = <0 0x00784000 0 0x8ff>,
              <0 0x00780000 0 0x7a0>,
              <0 0x00782000 0 0x100>,
              <0 0x00786000 0 0x1fff>;
        clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
        clock-names = "core";
        #address-cells = <1>;
        #size-cells = <1>;

        vcc-supply = <&vreg_l11a_1p8>;

        hstx-trim-primary@25b {
          reg = <0x25b 0x1>;
          bits = <1 3>;
        };
      };
    };

  - |
    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      efuse@784000 {
        compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
        reg = <0 0x00784000 0 0x8ff>;
        #address-cells = <1>;
        #size-cells = <1>;

        hstx-trim-primary@1eb {
          reg = <0x1eb 0x1>;
          bits = <1 4>;
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/qcom,spmi-sdam.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SPMI SDAM DT bindings

maintainers:
  - Shyam Kumar Thella <sthella@codeaurora.org>

description: |
  The SDAM provides scratch register space for the PMIC clients. This
  memory can be used by software to store information or communicate
  to/from the PBUS.

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    enum:
      - qcom,spmi-sdam

  reg:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  ranges: true

required:
  - compatible
  - reg
  - ranges

unevaluatedProperties: false

examples:
  - |
      sdam_1: nvram@b000 {
          #address-cells = <1>;
          #size-cells = <1>;
          compatible = "qcom,spmi-sdam";
          reg = <0xb000 0x100>;
          ranges = <0 0xb000 0x100>;

          /* Data cells */
          restart_reason: restart@50 {
              reg = <0x50 0x1>;
              bits = <6 2>;
          };
      };
...

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/rmem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Reserved Memory Based nvmem Device

maintainers:
  - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    items:
      - enum:
          - raspberrypi,bootloader-config
      - const: nvmem-rmem

  reg:
    maxItems: 1

  no-map:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Avoid creating a virtual mapping of the region as part of the OS'
      standard mapping of system memory.

required:
  - compatible
  - no-map

unevaluatedProperties: false

examples:
  - |
        reserved-memory {
                #address-cells = <1>;
                #size-cells = <1>;

                blconfig: nvram@10000000 {
                        compatible = "raspberrypi,bootloader-config", "nvmem-rmem";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        reg = <0x10000000 0x1000>;
                        no-map;
                };
        };

...


code:
# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/rockchip-efuse.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip eFuse

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    enum:
      - rockchip,rk3066a-efuse
      - rockchip,rk3188-efuse
      - rockchip,rk3228-efuse
      - rockchip,rk3288-efuse
      - rockchip,rk3328-efuse
      - rockchip,rk3368-efuse
      - rockchip,rk3399-efuse

      # Deprecated: old compatible value for rk3066a, rk3188 and rk3288
      - rockchip,rockchip-efuse

  reg:
    description:
      Registers location and eFuse size.
    maxItems: 1

  clocks:
    description:
      eFuse clock id.
    maxItems: 1

  clock-names:
    const: pclk_efuse

  rockchip,efuse-size:
    description:
      eFuse size in bytes. The eFuse size in property <reg> will be invalid if
      this property is defined.
    $ref: /schemas/types.yaml#/definitions/uint32

required:
  - compatible
  - reg
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3288-cru.h>
    efuse: efuse@ffb40000 {
            compatible = "rockchip,rk3288-efuse";
            reg = <0xffb40000 0x20>;
            #address-cells = <1>;
            #size-cells = <1>;
            clocks = <&cru PCLK_EFUSE256>;
            clock-names = "pclk_efuse";

            /* Data cells */
            cpu_leakage: cpu_leakage@17 {
                    reg = <0x17 0x1>;
            };
    };
...


code:
Rockchip internal OTP (One Time Programmable) memory device tree bindings

Required properties:
- compatible: Should be one of the following.
  - "rockchip,px30-otp" - for PX30 SoCs.
  - "rockchip,rk3308-otp" - for RK3308 SoCs.
- reg: Should contain the registers location and size
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Should be "otp", "apb_pclk" and "phy".
- resets: Must contain an entry for each entry in reset-names.
  See ../../reset/reset.txt for details.
- reset-names: Should be "phy".

See nvmem.txt for more information.

Example:
	otp: otp@ff290000 {
		compatible = "rockchip,px30-otp";
		reg = <0x0 0xff290000 0x0 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;
		clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
			 <&cru PCLK_OTP_PHY>;
		clock-names = "otp", "apb_pclk", "phy";
	};


code:
= Spreadtrum SC27XX PMIC eFuse device tree bindings =

Required properties:
- compatible: Should be one of the following.
	"sprd,sc2720-efuse"
	"sprd,sc2721-efuse"
	"sprd,sc2723-efuse"
	"sprd,sc2730-efuse"
	"sprd,sc2731-efuse"
- reg: Specify the address offset of efuse controller.
- hwlocks: Reference to a phandle of a hwlock provider node.

= Data cells =
Are child nodes of eFuse, bindings of which as described in
bindings/nvmem/nvmem.txt

Example:

	sc2731_pmic: pmic@0 {
		compatible = "sprd,sc2731";
		reg = <0>;
		spi-max-frequency = <26000000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;
		#address-cells = <1>;
		#size-cells = <0>;

		efuse@380 {
			compatible = "sprd,sc2731-efuse";
			reg = <0x380>;
			#address-cells = <1>;
			#size-cells = <1>;
			hwlocks = <&hwlock 12>;

			/* Data cells */
			thermal_calib: calib@10 {
				reg = <0x10 0x2>;
			};
		};
	};

= Data consumers =
Are device nodes which consume nvmem data cells.

Example:

	thermal {
		...
		nvmem-cells = <&thermal_calib>;
		nvmem-cell-names = "calibration";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/snvs-lpgpr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Low Power General Purpose Register found in i.MX Secure Non-Volatile Storage

maintainers:
  - Oleksij Rempel <o.rempel@pengutronix.de>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - fsl,imx8mm-snvs-lpgpr
              - fsl,imx8mn-snvs-lpgpr
              - fsl,imx8mp-snvs-lpgpr
              - fsl,imx8mq-snvs-lpgpr
          - const: fsl,imx7d-snvs-lpgpr
      - enum:
          - fsl,imx6q-snvs-lpgpr
          - fsl,imx6ul-snvs-lpgpr
          - fsl,imx7d-snvs-lpgpr

required:
  - compatible

additionalProperties: false

examples:
  - |
    snvs@20cc000 {
        compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
        reg = <0x20cc000 0x4000>;

        snvs_lpgpr: snvs-lpgpr {
            compatible = "fsl,imx6q-snvs-lpgpr";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/socionext,uniphier-efuse.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier eFuse bindings

maintainers:
  - Keiji Hayashibara <hayashibara.keiji@socionext.com>
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  "#address-cells": true
  "#size-cells": true

  compatible:
    const: socionext,uniphier-efuse

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    // The UniPhier eFuse should be a subnode of a "soc-glue" node.

    soc-glue@5f900000 {
        compatible = "simple-mfd";
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x5f900000 0x2000>;

        efuse@100 {
            compatible = "socionext,uniphier-efuse";
            reg = <0x100 0x28>;
        };

        efuse@200 {
            compatible = "socionext,uniphier-efuse";
            reg = <0x200 0x68>;
            #address-cells = <1>;
            #size-cells = <1>;

            /* Data cells */
            usb_rterm0: trim@54,4 {
                reg = <0x54 1>;
                bits = <4 2>;
            };
            usb_rterm1: trim@55,4 {
                reg = <0x55 1>;
                bits = <4 2>;
            };
            usb_rterm2: trim@58,4 {
                reg = <0x58 1>;
                bits = <4 2>;
            };
            usb_rterm3: trim@59,4 {
                reg = <0x59 1>;
                bits = <4 2>;
            };
            usb_sel_t0: trim@54,0 {
                reg = <0x54 1>;
                bits = <0 4>;
            };
            usb_sel_t1: trim@55,0 {
                reg = <0x55 1>;
                bits = <0 4>;
            };
            usb_sel_t2: trim@58,0 {
                reg = <0x58 1>;
                bits = <0 4>;
            };
            usb_sel_t3: trim@59,0 {
                reg = <0x59 1>;
                bits = <0 4>;
            };
            usb_hs_i0: trim@56,0 {
                reg = <0x56 1>;
                bits = <0 4>;
            };
            usb_hs_i2: trim@5a,0 {
                reg = <0x5a 1>;
                bits = <0 4>;
            };
        };
    };


code:
= Spreadtrum eFuse device tree bindings =

Required properties:
- compatible: Should be "sprd,ums312-efuse".
- reg: Specify the address offset of efuse controller.
- clock-names: Should be "enable".
- clocks: The phandle and specifier referencing the controller's clock.
- hwlocks: Reference to a phandle of a hwlock provider node.

= Data cells =
Are child nodes of eFuse, bindings of which as described in
bindings/nvmem/nvmem.txt

Example:

	ap_efuse: efuse@32240000 {
		compatible = "sprd,ums312-efuse";
		reg = <0 0x32240000 0 0x10000>;
		clock-names = "enable";
		hwlocks = <&hwlock 8>;
		clocks = <&aonapb_gate CLK_EFUSE_EB>;

		/* Data cells */
		thermal_calib: calib@10 {
			reg = <0x10 0x2>;
		};
	};

= Data consumers =
Are device nodes which consume nvmem data cells.

Example:

	thermal {
		...

		nvmem-cells = <&thermal_calib>;
		nvmem-cell-names = "calibration";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 Factory-programmed data bindings

description: |
  This represents STM32 Factory-programmed read only non-volatile area: locked
  flash, OTP, read-only HW regs... This contains various information such as:
  analog calibration data for temperature sensor (e.g. TS_CAL1, TS_CAL2),
  internal vref (VREFIN_CAL), unique device ID...

maintainers:
  - Fabrice Gasnier <fabrice.gasnier@foss.st.com>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    enum:
      - st,stm32f4-otp
      - st,stm32mp13-bsec
      - st,stm32mp15-bsec

  reg:
    maxItems: 1

patternProperties:
  "^.*@[0-9a-f]+$":
    type: object

    properties:
      st,non-secure-otp:
        description: |
          This property explicits a factory programmed area that both secure
          and non-secure worlds can access. It is needed when, by default, the
          related area can only be reached by the secure world.
        type: boolean

required:
  - "#address-cells"
  - "#size-cells"
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    efuse@1fff7800 {
      compatible = "st,stm32f4-otp";
      reg = <0x1fff7800 0x400>;
      #address-cells = <1>;
      #size-cells = <1>;

      calib@22c {
        reg = <0x22c 0x2>;
      };

      mac_addr@e4 {
        reg = <0xe4 0x8>;
        st,non-secure-otp;
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/sunplus,sp7021-ocotp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: On-Chip OTP Memory for Sunplus SP7021

maintainers:
  - Vincent Shih <vincent.sunplus@gmail.com>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    const: sunplus,sp7021-ocotp

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: hb_gpio
      - const: otprx

  clocks:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  thermal-calibration:
    type: object
    description: thermal calibration values

  disconnect-voltage:
    type: object
    description: disconnect voltages of usb2 port 0 and port 1

  mac-address0:
    type: object
    description: MAC address of ethernet port 0

  mac-address1:
    type: object
    description: MAC address of ethernet port 1

required:
  - compatible
  - reg
  - reg-names
  - clocks

unevaluatedProperties: false

examples:
  - |
    otp: otp@9c00af00 {
        compatible = "sunplus,sp7021-ocotp";
        reg = <0x9c00af00 0x34>, <0x9c00af80 0x58>;
        reg-names = "hb_gpio", "otprx";
        clocks = <&clkc 0x15>;

        #address-cells = <1>;
        #size-cells = <1>;
        therm_calib: thermal-calibration@14 {
          reg = <0x14 0x3>;
        };
        disc_vol: disconnect-voltage@18 {
          reg = <0x18 0x2>;
        };
        mac_addr0: mac-address0@34 {
          reg = <0x34 0x6>;
        };
        mac_addr1: mac-address1@3a {
          reg = <0x3a 0x6>;
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/u-boot,env.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: U-Boot environment variables

description: |
  U-Boot uses environment variables to store device parameters and
  configuration. They may be used for booting process, setup or keeping end user
  info.

  Data is stored using U-Boot specific formats (variant specific header and NUL
  separated key-value pairs).

  Environment data can be stored on various storage entities, e.g.:
  1. Raw flash partition
  2. UBI volume

  This binding allows marking storage device (as containing env data) and
  specifying used format.

  Right now only flash partition case is covered but it may be extended to e.g.
  UBI volumes in the future.

  Variables can be defined as NVMEM device subnodes.

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

properties:
  compatible:
    oneOf:
      - description: A standalone env data block
        const: u-boot,env
      - description: Two redundant blocks with active one flagged
        const: u-boot,env-redundant-bool
      - description: Two redundant blocks with active having higher counter
        const: u-boot,env-redundant-count
      - description: Broadcom's variant with custom header
        const: brcm,env

  reg:
    maxItems: 1

  bootcmd:
    type: object
    description: Command to use for automatic booting

  ethaddr:
    type: object
    description: Ethernet interface's MAC address

additionalProperties: false

examples:
  - |
    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        partition@0 {
            reg = <0x0 0x40000>;
            label = "u-boot";
            read-only;
        };

        env: partition@40000 {
            compatible = "u-boot,env";
            reg = <0x40000 0x10000>;

            mac: ethaddr {
            };
        };
    };
  - |
    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        partition@0 {
            reg = <0x0 0x100000>;
            compatible = "brcm,u-boot";
            label = "u-boot";

            partition-u-boot-env {
                compatible = "brcm,env";

                ethaddr {
                };
            };
        };
    };


code:
On-Chip OTP Memory for Freescale Vybrid

Required Properties:
  compatible:
  - "fsl,vf610-ocotp", "syscon" for VF5xx/VF6xx
  #address-cells : Should be 1
  #size-cells : Should be 1
  reg : Address and length of OTP controller and fuse map registers
  clocks : ipg clock we associate with the OCOTP peripheral

Example for Vybrid VF5xx/VF6xx:

	ocotp: ocotp@400a5000 {
		compatible = "fsl,vf610-ocotp", "syscon";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x400a5000 0xCF0>;
		clocks = <&clks VF610_CLK_OCOTP>;
	};


code:
--------------------------------------------------------------------------
=  Zynq UltraScale+ MPSoC nvmem firmware driver binding =
--------------------------------------------------------------------------
The nvmem_firmware node provides access to the hardware related data
like soc revision, IDCODE... etc, By using the firmware interface.

Required properties:
- compatible: should be "xlnx,zynqmp-nvmem-fw"

= Data cells =
Are child nodes of silicon id, bindings of which as described in
bindings/nvmem/nvmem.txt

-------
 Example
-------
firmware {
	zynqmp_firmware: zynqmp-firmware {
		compatible = "xlnx,zynqmp-firmware";
		method = "smc";

		nvmem_firmware {
			compatible = "xlnx,zynqmp-nvmem-fw";
			#address-cells = <1>;
			#size-cells = <1>;

			/* Data cells */
			soc_revision: soc_revision {
				reg = <0x0 0x4>;
			};
		};
	};
};

= Data consumers =
Are device nodes which consume nvmem data cells.

For example:
	pcap {
		...

		nvmem-cells = <&soc_revision>;
		nvmem-cell-names = "soc_revision";

		...
	};


code:
Zodiac Inflight Innovations RAVE EEPROM Bindings

RAVE SP EEPROM device is a "MFD cell" device exposing physical EEPROM
attached to RAVE Supervisory Processor. It is expected that its Device
Tree node is specified as a child of the node corresponding to the
parent RAVE SP device (as documented in
Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)

Required properties:

- compatible: Should be "zii,rave-sp-eeprom"

Optional properties:

- zii,eeprom-name: Unique EEPROM identifier describing its function in the
  system. Will be used as created NVMEM deivce's name.

Data cells:

Data cells are child nodes of eerpom node, bindings for which are
documented in Documentation/devicetree/bindings/nvmem/nvmem.txt

Example:

	rave-sp {
		compatible = "zii,rave-sp-rdu1";
		current-speed = <38400>;

		eeprom@a4 {
			compatible = "zii,rave-sp-eeprom";
			reg = <0xa4 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			zii,eeprom-name = "main-eeprom";

			wdt_timeout: wdt-timeout@81 {
				reg = <0x81 2>;
			};
		};
	}


code:
OpenRISC Generic SoC
====================

Boards and FPGA SoC's which support the OpenRISC standard platform.  The
platform essentially follows the conventions of the OpenRISC architecture
specification, however some aspects, such as the boot protocol have been defined
by the Linux port.

Required properties
-------------------
 - compatible: Must include "opencores,or1ksim"

CPU nodes:
----------
A "cpus" node is required.  Required properties:
 - #address-cells: Must be 1.
 - #size-cells: Must be 0.
A CPU sub-node is also required for at least CPU 0.  Since the topology may
be probed via CPS, it is not necessary to specify secondary CPUs.  Required
properties:
 - compatible: Must be "opencores,or1200-rtlsvn481".
 - reg: CPU number.
 - clock-frequency: The CPU clock frequency in Hz.
Example:
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "opencores,or1200-rtlsvn481";
			reg = <0>;
			clock-frequency = <20000000>;
		};
	};

Boot protocol
-------------
The bootloader may pass the following arguments to the kernel:
 - r3:  address of a flattened device-tree blob or 0x0.


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner H6 CPU OPP

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |
  For some SoCs, the CPU frequency subset and voltage value of each
  OPP varies based on the silicon variant in use. Allwinner Process
  Voltage Scaling Tables defines the voltage and frequency value based
  on the speedbin blown in the efuse combination. The
  sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
  provide the OPP framework with required information.

allOf:
  - $ref: opp-v2-base.yaml#

properties:
  compatible:
    const: allwinner,sun50i-h6-operating-points

  nvmem-cells:
    description: |
      A phandle pointing to a nvmem-cells node representing the efuse
      registers that has information about the speedbin that is used
      to select the right frequency/voltage value pair. Please refer
      the for nvmem-cells bindings
      Documentation/devicetree/bindings/nvmem/nvmem.txt and also
      examples below.

  opp-shared: true

required:
  - compatible
  - nvmem-cells

patternProperties:
  "^opp-[0-9]+$":
    type: object

    properties:
      opp-hz: true
      clock-latency-ns: true

    patternProperties:
      "^opp-microvolt-speed[0-9]$": true

    required:
      - opp-hz
      - opp-microvolt-speed0
      - opp-microvolt-speed1
      - opp-microvolt-speed2

    unevaluatedProperties: false

additionalProperties: false

examples:
  - |
    cpu_opp_table: opp-table {
        compatible = "allwinner,sun50i-h6-operating-points";
        nvmem-cells = <&speedbin_efuse>;
        opp-shared;

        opp-480000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <480000000>;

            opp-microvolt-speed0 = <880000>;
            opp-microvolt-speed1 = <820000>;
            opp-microvolt-speed2 = <800000>;
        };

        opp-720000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <720000000>;

            opp-microvolt-speed0 = <880000>;
            opp-microvolt-speed1 = <820000>;
            opp-microvolt-speed2 = <800000>;
        };

        opp-816000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <816000000>;

            opp-microvolt-speed0 = <880000>;
            opp-microvolt-speed1 = <820000>;
            opp-microvolt-speed2 = <800000>;
        };

        opp-888000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <888000000>;

            opp-microvolt-speed0 = <940000>;
            opp-microvolt-speed1 = <820000>;
            opp-microvolt-speed2 = <800000>;
        };

        opp-1080000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <1080000000>;

            opp-microvolt-speed0 = <1060000>;
            opp-microvolt-speed1 = <880000>;
            opp-microvolt-speed2 = <840000>;
        };

        opp-1320000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <1320000000>;

            opp-microvolt-speed0 = <1160000>;
            opp-microvolt-speed1 = <940000>;
            opp-microvolt-speed2 = <900000>;
        };

        opp-1488000000 {
            clock-latency-ns = <244144>; /* 8 32k periods */
            opp-hz = /bits/ 64 <1488000000>;

            opp-microvolt-speed0 = <1160000>;
            opp-microvolt-speed1 = <1000000>;
            opp-microvolt-speed2 = <960000>;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/opp/opp-v1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic OPP (Operating Performance Points) v1 Bindings

maintainers:
  - Viresh Kumar <viresh.kumar@linaro.org>

description: |+
  Devices work at voltage-current-frequency combinations and some implementations
  have the liberty of choosing these. These combinations are called Operating
  Performance Points aka OPPs. This document defines bindings for these OPPs
  applicable across wide range of devices. For illustration purpose, this document
  uses CPU as a device.

  This binding only supports voltage-frequency pairs.

select: true

properties:
  operating-points:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    items:
      items:
        - description: Frequency in kHz
        - description: Voltage for OPP in uV

additionalProperties: true
examples:
  - |
    cpus {
        #address-cells = <1>;
        #size-cells = <0>;

        cpu@0 {
            compatible = "arm,cortex-a9";
            device_type = "cpu";
            reg = <0>;
            next-level-cache = <&L2>;
            operating-points =
                /* kHz    uV */
                <792000 1100000>,
                <396000 950000>,
                <198000 850000>;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/opp/opp-v2-base.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic OPP (Operating Performance Points) Common Binding

maintainers:
  - Viresh Kumar <viresh.kumar@linaro.org>

description: |
  Devices work at voltage-current-frequency combinations and some implementations
  have the liberty of choosing these. These combinations are called Operating
  Performance Points aka OPPs. This document defines bindings for these OPPs
  applicable across wide range of devices. For illustration purpose, this document
  uses CPU as a device.

  This describes the OPPs belonging to a device.

select: false

properties:
  $nodename:
    pattern: '^opp-table(-[a-z0-9]+)?$'

  opp-shared:
    description:
      Indicates that device nodes using this OPP Table Node's phandle switch
      their DVFS state together, i.e. they share clock/voltage/current lines.
      Missing property means devices have independent clock/voltage/current
      lines, but they share OPP tables.
    type: boolean

patternProperties:
  '^opp(-?[0-9]+)*$':
    type: object
    description:
      One or more OPP nodes describing voltage-current-frequency combinations.
      Their name isn't significant but their phandle can be used to reference an
      OPP. These are mandatory except for the case where the OPP table is
      present only to indicate dependency between devices using the opp-shared
      property.

    properties:
      opp-hz:
        description:
          Frequency in Hz, expressed as a 64-bit big-endian integer. This is a
          required property for all device nodes, unless another "required"
          property to uniquely identify the OPP nodes exists. Devices like power
          domains must have another (implementation dependent) property.

          Entries for multiple clocks shall be provided in the same field, as
          array of frequencies.  The OPP binding doesn't provide any provisions
          to relate the values to their clocks or the order in which the clocks
          need to be configured and that is left for the implementation
          specific binding.
        minItems: 1
        maxItems: 16
        items:
          maxItems: 1

      opp-microvolt:
        description: |
          Voltage for the OPP

          A single regulator's voltage is specified with an array of size one or three.
          Single entry is for target voltage and three entries are for <target min max>
          voltages.

          Entries for multiple regulators shall be provided in the same field separated
          by angular brackets <>. The OPP binding doesn't provide any provisions to
          relate the values to their power supplies or the order in which the supplies
          need to be configured and that is left for the implementation specific
          binding.

          Entries for all regulators shall be of the same size, i.e. either all use a
          single value or triplets.
        minItems: 1
        maxItems: 8   # Should be enough regulators
        items:
          minItems: 1
          maxItems: 3

      opp-microamp:
        description: |
          The maximum current drawn by the device in microamperes considering
          system specific parameters (such as transients, process, aging,
          maximum operating temperature range etc.) as necessary. This may be
          used to set the most efficient regulator operating mode.

          Should only be set if opp-microvolt or opp-microvolt-<name> is set for
          the OPP.

          Entries for multiple regulators shall be provided in the same field
          separated by angular brackets <>. If current values aren't required
          for a regulator, then it shall be filled with 0. If current values
          aren't required for any of the regulators, then this field is not
          required. The OPP binding doesn't provide any provisions to relate the
          values to their power supplies or the order in which the supplies need
          to be configured and that is left for the implementation specific
          binding.
        minItems: 1
        maxItems: 8   # Should be enough regulators

      opp-microwatt:
        description: |
          The power for the OPP in micro-Watts.

          Entries for multiple regulators shall be provided in the same field
          separated by angular brackets <>. If power values aren't required
          for a regulator, then it shall be filled with 0. If power values
          aren't required for any of the regulators, then this field is not
          required. The OPP binding doesn't provide any provisions to relate the
          values to their power supplies or the order in which the supplies need
          to be configured and that is left for the implementation specific
          binding.
        minItems: 1
        maxItems: 8   # Should be enough regulators

      opp-level:
        description:
          A value representing the performance level of the device.
        $ref: /schemas/types.yaml#/definitions/uint32

      opp-peak-kBps:
        description:
          Peak bandwidth in kilobytes per second, expressed as an array of
          32-bit big-endian integers. Each element of the array represents the
          peak bandwidth value of each interconnect path. The number of elements
          should match the number of interconnect paths.
        minItems: 1
        maxItems: 32  # Should be enough

      opp-avg-kBps:
        description:
          Average bandwidth in kilobytes per second, expressed as an array
          of 32-bit big-endian integers. Each element of the array represents the
          average bandwidth value of each interconnect path. The number of elements
          should match the number of interconnect paths. This property is only
          meaningful in OPP tables where opp-peak-kBps is present.
        minItems: 1
        maxItems: 32  # Should be enough

      clock-latency-ns:
        description:
          Specifies the maximum possible transition latency (in nanoseconds) for
          switching to this OPP from any other OPP.

      turbo-mode:
        description:
          Marks the OPP to be used only for turbo modes. Turbo mode is available
          on some platforms, where the device can run over its operating
          frequency for a short duration of time limited by the device's power,
          current and thermal limits.
        type: boolean

      opp-suspend:
        description:
          Marks the OPP to be used during device suspend. If multiple OPPs in
          the table have this, the OPP with highest opp-hz will be used.
        type: boolean

      opp-supported-hw:
        description: |
          This property allows a platform to enable only a subset of the OPPs
          from the larger set present in the OPP table, based on the current
          version of the hardware (already known to the operating system).

          Each block present in the array of blocks in this property, represents
          a sub-group of hardware versions supported by the OPP. i.e. <sub-group
          A>, <sub-group B>, etc. The OPP will be enabled if _any_ of these
          sub-groups match the hardware's version.

          Each sub-group is a platform defined array representing the hierarchy
          of hardware versions supported by the platform. For a platform with
          three hierarchical levels of version (X.Y.Z), this field shall look
          like

          opp-supported-hw = <X1 Y1 Z1>, <X2 Y2 Z2>, <X3 Y3 Z3>.

          Each level (eg. X1) in version hierarchy is represented by a 32 bit
          value, one bit per version and so there can be maximum 32 versions per
          level. Logical AND (&) operation is performed for each level with the
          hardware's level version and a non-zero output for _all_ the levels in
          a sub-group means the OPP is supported by hardware. A value of
          0xFFFFFFFF for each level in the sub-group will enable the OPP for all
          versions for the hardware.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        maxItems: 32
        items:
          minItems: 1
          maxItems: 4

      required-opps:
        description:
          This contains phandle to an OPP node in another device's OPP table. It
          may contain an array of phandles, where each phandle points to an OPP
          of a different device. It should not contain multiple phandles to the
          OPP nodes in the same OPP table. This specifies the minimum required
          OPP of the device(s), whose OPP's phandle is present in this property,
          for the functioning of the current device at the current OPP (where
          this property is present).
        $ref: /schemas/types.yaml#/definitions/phandle-array
        items:
          maxItems: 1

    patternProperties:
      '^opp-microvolt-':
        description:
          Named opp-microvolt property. This is exactly similar to the above
          opp-microvolt property, but allows multiple voltage ranges to be
          provided for the same OPP. At runtime, the platform can pick a <name>
          and matching opp-microvolt-<name> property will be enabled for all
          OPPs. If the platform doesn't pick a specific <name> or the <name>
          doesn't match with any opp-microvolt-<name> properties, then
          opp-microvolt property shall be used, if present.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        minItems: 1
        maxItems: 8   # Should be enough regulators
        items:
          minItems: 1
          maxItems: 3

      '^opp-microamp-':
        description:
          Named opp-microamp property. Similar to opp-microvolt-<name> property,
          but for microamp instead.
        $ref: /schemas/types.yaml#/definitions/uint32-array
        minItems: 1
        maxItems: 8   # Should be enough regulators

      '^opp-microwatt-':
        description:
          Named opp-microwatt property. Similar to opp-microamp-<name> property,
          but for microwatt instead.
        $ref: /schemas/types.yaml#/definitions/uint32-array
        minItems: 1
        maxItems: 8   # Should be enough regulators

    dependencies:
      opp-avg-kBps: [ opp-peak-kBps ]

required:
  - compatible

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. NVMEM OPP bindings

maintainers:
  - Ilia Lin <ilia.lin@kernel.org>

allOf:
  - $ref: opp-v2-base.yaml#

description: |
  In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996,
  the CPU frequencies subset and voltage value of each OPP varies based on
  the silicon variant in use.
  Qualcomm Technologies, Inc. Process Voltage Scaling Tables
  defines the voltage and frequency value based on the speedbin blown in
  the efuse combination.
  The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
  the OPP framework with required information (existing HW bitmap).
  This is used to determine the voltage and frequency value for each OPP of
  operating-points-v2 table when it is parsed by the OPP framework.

properties:
  compatible:
    const: operating-points-v2-kryo-cpu

  nvmem-cells:
    description: |
      A phandle pointing to a nvmem-cells node representing the
      efuse registers that has information about the
      speedbin that is used to select the right frequency/voltage
      value pair.

  opp-shared: true

patternProperties:
  '^opp-?[0-9]+$':
    type: object
    additionalProperties: false

    properties:
      opp-hz: true

      opp-microvolt: true

      opp-supported-hw:
        description: |
          A single 32 bit bitmap value, representing compatible HW.
          Bitmap:
          0:  MSM8996, speedbin 0
          1:  MSM8996, speedbin 1
          2:  MSM8996, speedbin 2
          3-31:  unused
        maximum: 0x7

      clock-latency-ns: true

      required-opps: true

    required:
      - opp-hz

required:
  - compatible

if:
  required:
    - nvmem-cells
then:
  patternProperties:
    '^opp-?[0-9]+$':
      required:
        - opp-supported-hw

additionalProperties: false

examples:
  - |
    / {
        model = "Qualcomm Technologies, Inc. DB820c";
        compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
        #address-cells = <2>;
        #size-cells = <2>;

        cpus {
            #address-cells = <2>;
            #size-cells = <0>;

            CPU0: cpu@0 {
                device_type = "cpu";
                compatible = "qcom,kryo";
                reg = <0x0 0x0>;
                enable-method = "psci";
                cpu-idle-states = <&CPU_SLEEP_0>;
                capacity-dmips-mhz = <1024>;
                clocks = <&kryocc 0>;
                operating-points-v2 = <&cluster0_opp>;
                power-domains = <&cpr>;
                power-domain-names = "cpr";
                #cooling-cells = <2>;
                next-level-cache = <&L2_0>;
                L2_0: l2-cache {
                    compatible = "cache";
                    cache-level = <2>;
                };
            };

            CPU1: cpu@1 {
                device_type = "cpu";
                compatible = "qcom,kryo";
                reg = <0x0 0x1>;
                enable-method = "psci";
                cpu-idle-states = <&CPU_SLEEP_0>;
                capacity-dmips-mhz = <1024>;
                clocks = <&kryocc 0>;
                operating-points-v2 = <&cluster0_opp>;
                power-domains = <&cpr>;
                power-domain-names = "cpr";
                #cooling-cells = <2>;
                next-level-cache = <&L2_0>;
            };

            CPU2: cpu@100 {
                device_type = "cpu";
                compatible = "qcom,kryo";
                reg = <0x0 0x100>;
                enable-method = "psci";
                cpu-idle-states = <&CPU_SLEEP_0>;
                capacity-dmips-mhz = <1024>;
                clocks = <&kryocc 1>;
                operating-points-v2 = <&cluster1_opp>;
                power-domains = <&cpr>;
                power-domain-names = "cpr";
                #cooling-cells = <2>;
                next-level-cache = <&L2_1>;
                L2_1: l2-cache {
                    compatible = "cache";
                    cache-level = <2>;
                };
            };

            CPU3: cpu@101 {
                device_type = "cpu";
                compatible = "qcom,kryo";
                reg = <0x0 0x101>;
                enable-method = "psci";
                cpu-idle-states = <&CPU_SLEEP_0>;
                capacity-dmips-mhz = <1024>;
                clocks = <&kryocc 1>;
                operating-points-v2 = <&cluster1_opp>;
                power-domains = <&cpr>;
                power-domain-names = "cpr";
                #cooling-cells = <2>;
                next-level-cache = <&L2_1>;
            };

            cpu-map {
                cluster0 {
                    core0 {
                        cpu = <&CPU0>;
                    };

                    core1 {
                        cpu = <&CPU1>;
                    };
                };

                cluster1 {
                    core0 {
                        cpu = <&CPU2>;
                    };

                    core1 {
                        cpu = <&CPU3>;
                    };
                };
            };
        };

        cluster0_opp: opp-table-0 {
            compatible = "operating-points-v2-kryo-cpu";
            nvmem-cells = <&speedbin_efuse>;
            opp-shared;

            opp-307200000 {
                opp-hz = /bits/ 64 <307200000>;
                opp-microvolt = <905000 905000 1140000>;
                opp-supported-hw = <0x7>;
                clock-latency-ns = <200000>;
                required-opps = <&cpr_opp1>;
            };
            opp-1401600000 {
                opp-hz = /bits/ 64 <1401600000>;
                opp-microvolt = <1140000 905000 1140000>;
                opp-supported-hw = <0x5>;
                clock-latency-ns = <200000>;
                required-opps = <&cpr_opp2>;
            };
            opp-1593600000 {
                opp-hz = /bits/ 64 <1593600000>;
                opp-microvolt = <1140000 905000 1140000>;
                opp-supported-hw = <0x1>;
                clock-latency-ns = <200000>;
                required-opps = <&cpr_opp3>;
            };
        };

        cluster1_opp: opp-table-1 {
            compatible = "operating-points-v2-kryo-cpu";
            nvmem-cells = <&speedbin_efuse>;
            opp-shared;

            opp-307200000 {
                opp-hz = /bits/ 64 <307200000>;
                opp-microvolt = <905000 905000 1140000>;
                opp-supported-hw = <0x7>;
                clock-latency-ns = <200000>;
                required-opps = <&cpr_opp1>;
            };
            opp-1804800000 {
                opp-hz = /bits/ 64 <1804800000>;
                opp-microvolt = <1140000 905000 1140000>;
                opp-supported-hw = <0x6>;
                clock-latency-ns = <200000>;
                required-opps = <&cpr_opp4>;
            };
            opp-1900800000 {
                opp-hz = /bits/ 64 <1900800000>;
                opp-microvolt = <1140000 905000 1140000>;
                opp-supported-hw = <0x4>;
                clock-latency-ns = <200000>;
                required-opps = <&cpr_opp5>;
            };
            opp-2150400000 {
                opp-hz = /bits/ 64 <2150400000>;
                opp-microvolt = <1140000 905000 1140000>;
                opp-supported-hw = <0x1>;
                clock-latency-ns = <200000>;
                required-opps = <&cpr_opp6>;
            };
        };

        smem {
            compatible = "qcom,smem";
            memory-region = <&smem_mem>;
            hwlocks = <&tcsr_mutex 3>;
        };

        soc {
            #address-cells = <1>;
            #size-cells = <1>;

            qfprom: qfprom@74000 {
                compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
                reg = <0x00074000 0x8ff>;
                #address-cells = <1>;
                #size-cells = <1>;

                speedbin_efuse: speedbin@133 {
                    reg = <0x133 0x1>;
                    bits = <5 3>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm OPP bindings to describe OPP nodes.

maintainers:
  - Niklas Cassel <nks@flawful.org>

allOf:
  - $ref: opp-v2-base.yaml#

properties:
  compatible:
    const: operating-points-v2-qcom-level

patternProperties:
  '^opp-?[0-9]+$':
    type: object
    additionalProperties: false

    properties:
      opp-level: true

      qcom,opp-fuse-level:
        description: |
          A positive value representing the fuse corner/level associated with
          this OPP node. Sometimes several corners/levels shares a certain fuse
          corner/level. A fuse corner/level contains e.g. ref uV, min uV,
          and max uV.
        $ref: /schemas/types.yaml#/definitions/uint32

    required:
      - opp-level
      - qcom,opp-fuse-level

required:
  - compatible

additionalProperties: false

examples:
  - |
    cpr_opp_table: opp-table-cpr {
        compatible = "operating-points-v2-qcom-level";

        cpr_opp1: opp1 {
            opp-level = <1>;
            qcom,opp-fuse-level = <1>;
        };
        cpr_opp2: opp2 {
            opp-level = <2>;
            qcom,opp-fuse-level = <2>;
        };
        cpr_opp3: opp3 {
            opp-level = <3>;
            qcom,opp-fuse-level = <3>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/opp/opp-v2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic OPP (Operating Performance Points) Bindings

maintainers:
  - Viresh Kumar <viresh.kumar@linaro.org>

allOf:
  - $ref: opp-v2-base.yaml#

properties:
  compatible:
    const: operating-points-v2

unevaluatedProperties: false

examples:
  - |
    /*
     * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
     * together.
     */
    cpus {
        #address-cells = <1>;
        #size-cells = <0>;

        cpu@0 {
            compatible = "arm,cortex-a9";
            device_type = "cpu";
            reg = <0>;
            next-level-cache = <&L2>;
            clocks = <&clk_controller 0>;
            clock-names = "cpu";
            cpu-supply = <&cpu_supply0>;
            operating-points-v2 = <&cpu0_opp_table0>;
        };

        cpu@1 {
            compatible = "arm,cortex-a9";
            device_type = "cpu";
            reg = <1>;
            next-level-cache = <&L2>;
            clocks = <&clk_controller 0>;
            clock-names = "cpu";
            cpu-supply = <&cpu_supply0>;
            operating-points-v2 = <&cpu0_opp_table0>;
        };
    };

    cpu0_opp_table0: opp-table {
        compatible = "operating-points-v2";
        opp-shared;

        opp-1000000000 {
            opp-hz = /bits/ 64 <1000000000>;
            opp-microvolt = <975000 970000 985000>;
            opp-microamp = <70000>;
            clock-latency-ns = <300000>;
            opp-suspend;
        };
        opp-1100000000 {
            opp-hz = /bits/ 64 <1100000000>;
            opp-microvolt = <1000000 980000 1010000>;
            opp-microamp = <80000>;
            clock-latency-ns = <310000>;
        };
        opp-1200000000 {
            opp-hz = /bits/ 64 <1200000000>;
            opp-microvolt = <1025000>;
            clock-latency-ns = <290000>;
            turbo-mode;
        };
    };

  - |
    /*
     * Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states
     * independently.
     */
    cpus {
        #address-cells = <1>;
        #size-cells = <0>;

        cpu@0 {
            compatible = "qcom,krait";
            device_type = "cpu";
            reg = <0>;
            next-level-cache = <&L2>;
            clocks = <&clk_controller 0>;
            clock-names = "cpu";
            cpu-supply = <&cpu_supply0>;
            operating-points-v2 = <&cpu_opp_table>;
        };

        cpu@1 {
            compatible = "qcom,krait";
            device_type = "cpu";
            reg = <1>;
            next-level-cache = <&L2>;
            clocks = <&clk_controller 1>;
            clock-names = "cpu";
            cpu-supply = <&cpu_supply1>;
            operating-points-v2 = <&cpu_opp_table>;
        };

        cpu@2 {
            compatible = "qcom,krait";
            device_type = "cpu";
            reg = <2>;
            next-level-cache = <&L2>;
            clocks = <&clk_controller 2>;
            clock-names = "cpu";
            cpu-supply = <&cpu_supply2>;
            operating-points-v2 = <&cpu_opp_table>;
        };

        cpu@3 {
            compatible = "qcom,krait";
            device_type = "cpu";
            reg = <3>;
            next-level-cache = <&L2>;
            clocks = <&clk_controller 3>;
            clock-names = "cpu";
            cpu-supply = <&cpu_supply3>;
            operating-points-v2 = <&cpu_opp_table>;
        };
    };

    cpu_opp_table: opp-table {
        compatible = "operating-points-v2";

        /*
         * Missing opp-shared property means CPUs switch DVFS states
         * independently.
         */

        opp-1000000000 {
            opp-hz = /bits/ 64 <1000000000>;
            opp-microvolt = <975000 970000 985000>;
            opp-microamp = <70000>;
            clock-latency-ns = <300000>;
            opp-suspend;
        };
        opp-1100000000 {
            opp-hz = /bits/ 64 <1100000000>;
            opp-microvolt = <1000000 980000 1010000>;
            opp-microamp = <80000>;
            clock-latency-ns = <310000>;
        };
        opp-1200000000 {
            opp-hz = /bits/ 64 <1200000000>;
            opp-microvolt = <1025000>;
            opp-microamp = <90000>;
            clock-latency-ns = <290000>;
            turbo-mode;
        };
    };

  - |
    /*
     * Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch
     * DVFS state together.
     */
    cpus {
        #address-cells = <1>;
        #size-cells = <0>;

        cpu@0 {
            compatible = "arm,cortex-a7";
            device_type = "cpu";
            reg = <0>;
            next-level-cache = <&L2>;
            clocks = <&clk_controller 0>;
            clock-names = "cpu";
            cpu-supply = <&cpu_supply0>;
            operating-points-v2 = <&cluster0_opp>;
        };

        cpu@1 {
            compatible = "arm,cortex-a7";
            device_type = "cpu";
            reg = <1>;
            next-level-cache = <&L2>;
            clocks = <&clk_controller 0>;
            clock-names = "cpu";
            cpu-supply = <&cpu_supply0>;
            operating-points-v2 = <&cluster0_opp>;
        };

        cpu@100 {
            compatible = "arm,cortex-a15";
            device_type = "cpu";
            reg = <100>;
            next-level-cache = <&L2>;
            clocks = <&clk_controller 1>;
            clock-names = "cpu";
            cpu-supply = <&cpu_supply1>;
            operating-points-v2 = <&cluster1_opp>;
        };

        cpu@101 {
            compatible = "arm,cortex-a15";
            device_type = "cpu";
            reg = <101>;
            next-level-cache = <&L2>;
            clocks = <&clk_controller 1>;
            clock-names = "cpu";
            cpu-supply = <&cpu_supply1>;
            operating-points-v2 = <&cluster1_opp>;
        };
    };

    cluster0_opp: opp-table-0 {
        compatible = "operating-points-v2";
        opp-shared;

        opp-1000000000 {
            opp-hz = /bits/ 64 <1000000000>;
            opp-microvolt = <975000 970000 985000>;
            opp-microamp = <70000>;
            clock-latency-ns = <300000>;
            opp-suspend;
        };
        opp-1100000000 {
            opp-hz = /bits/ 64 <1100000000>;
            opp-microvolt = <1000000 980000 1010000>;
            opp-microamp = <80000>;
            clock-latency-ns = <310000>;
        };
        opp-1200000000 {
            opp-hz = /bits/ 64 <1200000000>;
            opp-microvolt = <1025000>;
            opp-microamp = <90000>;
            clock-latency-ns = <290000>;
            turbo-mode;
        };
    };

    cluster1_opp: opp-table-1 {
        compatible = "operating-points-v2";
        opp-shared;

        opp-1300000000 {
            opp-hz = /bits/ 64 <1300000000>;
            opp-microvolt = <1050000 1045000 1055000>;
            opp-microamp = <95000>;
            clock-latency-ns = <400000>;
            opp-suspend;
        };
        opp-1400000000 {
            opp-hz = /bits/ 64 <1400000000>;
            opp-microvolt = <1075000>;
            opp-microamp = <100000>;
            clock-latency-ns = <400000>;
        };
        opp-1500000000 {
            opp-hz = /bits/ 64 <1500000000>;
            opp-microvolt = <1100000 1010000 1110000>;
            opp-microamp = <95000>;
            clock-latency-ns = <400000>;
            turbo-mode;
        };
    };

  - |
    /* Example 4: Handling multiple regulators */
    cpus {
        #address-cells = <1>;
        #size-cells = <0>;

        cpu@0 {
            compatible = "foo,cpu-type";
            device_type = "cpu";
            reg = <0>;

            vcc0-supply = <&cpu_supply0>;
            vcc1-supply = <&cpu_supply1>;
            vcc2-supply = <&cpu_supply2>;
            operating-points-v2 = <&cpu0_opp_table4>;
        };
    };

    cpu0_opp_table4: opp-table-0 {
        compatible = "operating-points-v2";
        opp-shared;

        opp-1000000000 {
            opp-hz = /bits/ 64 <1000000000>;
            opp-microvolt = <970000>, /* Supply 0 */
                            <960000>, /* Supply 1 */
                            <960000>; /* Supply 2 */
            opp-microamp =  <70000>,  /* Supply 0 */
                            <70000>,  /* Supply 1 */
                            <70000>;  /* Supply 2 */
            clock-latency-ns = <300000>;
        };

        /* OR */

        opp-1000000001 {
            opp-hz = /bits/ 64 <1000000001>;
            opp-microvolt = <975000 970000 985000>, /* Supply 0 */
                            <965000 960000 975000>, /* Supply 1 */
                            <965000 960000 975000>; /* Supply 2 */
            opp-microamp =  <70000>,    /* Supply 0 */
                <70000>,    /* Supply 1 */
                <70000>;    /* Supply 2 */
            clock-latency-ns = <300000>;
        };

        /* OR */

        opp-1000000002 {
            opp-hz = /bits/ 64 <1000000002>;
            opp-microvolt = <975000 970000 985000>, /* Supply 0 */
                <965000 960000 975000>, /* Supply 1 */
                <965000 960000 975000>; /* Supply 2 */
            opp-microamp =  <70000>,    /* Supply 0 */
                <0>,      /* Supply 1 doesn't need this */
                <70000>;    /* Supply 2 */
            clock-latency-ns = <300000>;
        };
    };

  - |
    /*
     * Example 5: opp-supported-hw
     * (example: three level hierarchy of versions: cuts, substrate and process)
     */
    cpus {
        #address-cells = <1>;
        #size-cells = <0>;

        cpu@0 {
            compatible = "arm,cortex-a7";
            device_type = "cpu";
            reg = <0>;
            cpu-supply = <&cpu_supply>;
            operating-points-v2 = <&cpu0_opp_table_slow>;
        };
    };

    cpu0_opp_table_slow: opp-table {
        compatible = "operating-points-v2";
        opp-shared;

        opp-600000000 {
            /*
             * Supports all substrate and process versions for 0xF
             * cuts, i.e. only first four cuts.
             */
            opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF>;
            opp-hz = /bits/ 64 <600000000>;
        };

        opp-800000000 {
            /*
             * Supports:
             * - cuts: only one, 6th cut (represented by 6th bit).
             * - substrate: supports 16 different substrate versions
             * - process: supports 9 different process versions
             */
            opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0>;
            opp-hz = /bits/ 64 <800000000>;
        };

        opp-900000000 {
            /*
             * Supports:
             * - All cuts and substrate where process version is 0x2.
             * - All cuts and process where substrate version is 0x2.
             */
            opp-supported-hw = <0xFFFFFFFF 0xFFFFFFFF 0x02>,
                               <0xFFFFFFFF 0x01 0xFFFFFFFF>;
            opp-hz = /bits/ 64 <900000000>;
        };
    };

  - |
    /*
     * Example 6: opp-microvolt-<name>, opp-microamp-<name>:
     * (example: device with two possible microvolt ranges: slow and fast)
     */
    cpus {
        #address-cells = <1>;
        #size-cells = <0>;

        cpu@0 {
            compatible = "arm,cortex-a7";
            device_type = "cpu";
            reg = <0>;
            operating-points-v2 = <&cpu0_opp_table6>;
        };
    };

    cpu0_opp_table6: opp-table-0 {
        compatible = "operating-points-v2";
        opp-shared;

        opp-1000000000 {
            opp-hz = /bits/ 64 <1000000000>;
            opp-microvolt-slow = <915000 900000 925000>;
            opp-microvolt-fast = <975000 970000 985000>;
            opp-microamp-slow =  <70000>;
            opp-microamp-fast =  <71000>;
        };

        opp-1200000000 {
            opp-hz = /bits/ 64 <1200000000>;
            opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */
                                 <925000 910000 935000>; /* Supply vcc1 */
            opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */
                                 <965000 960000 975000>; /* Supply vcc1 */
            opp-microamp =  <70000>; /* Will be used for both slow/fast */
        };
    };

  - |
    /*
     * Example 7: Single cluster Quad-core ARM cortex A53, OPP points from firmware,
     * distinct clock controls but two sets of clock/voltage/current lines.
     */
    cpus {
        #address-cells = <2>;
        #size-cells = <0>;

        cpu@0 {
            compatible = "arm,cortex-a53";
            device_type = "cpu";
            reg = <0x0 0x100>;
            next-level-cache = <&A53_L2>;
            clocks = <&dvfs_controller 0>;
            operating-points-v2 = <&cpu_opp0_table>;
        };
        cpu@1 {
            compatible = "arm,cortex-a53";
            device_type = "cpu";
            reg = <0x0 0x101>;
            next-level-cache = <&A53_L2>;
            clocks = <&dvfs_controller 1>;
            operating-points-v2 = <&cpu_opp0_table>;
        };
        cpu@2 {
            compatible = "arm,cortex-a53";
            device_type = "cpu";
            reg = <0x0 0x102>;
            next-level-cache = <&A53_L2>;
            clocks = <&dvfs_controller 2>;
            operating-points-v2 = <&cpu_opp1_table>;
        };
        cpu@3 {
            compatible = "arm,cortex-a53";
            device_type = "cpu";
            reg = <0x0 0x103>;
            next-level-cache = <&A53_L2>;
            clocks = <&dvfs_controller 3>;
            operating-points-v2 = <&cpu_opp1_table>;
        };

    };

    cpu_opp0_table: opp-table-0 {
        compatible = "operating-points-v2";
        opp-shared;
    };

    cpu_opp1_table: opp-table-1 {
        compatible = "operating-points-v2";
        opp-shared;
    };
...


code:
Texas Instruments OMAP compatible OPP supply description

OMAP5, DRA7, and AM57 family of SoCs have Class0 AVS eFuse registers which
contain data that can be used to adjust voltages programmed for some of their
supplies for more efficient operation. This binding provides the information
needed to read these values and use them to program the main regulator during
an OPP transitions.

Also, some supplies may have an associated vbb-supply which is an Adaptive Body
Bias regulator which much be transitioned in a specific sequence with regards
to the vdd-supply and clk when making an OPP transition. By supplying two
regulators to the device that will undergo OPP transitions we can make use
of the multi regulator binding that is part of the OPP core described here [1]
to describe both regulators needed by the platform.

[1] Documentation/devicetree/bindings/opp/opp-v2.yaml

Required Properties for Device Node:
- vdd-supply: phandle to regulator controlling VDD supply
- vbb-supply: phandle to regulator controlling Body Bias supply
	      (Usually Adaptive Body Bias regulator)

Required Properties for opp-supply node:
- compatible: Should be one of:
	"ti,omap-opp-supply" - basic OPP supply controlling VDD and VBB
	"ti,omap5-opp-supply" - OMAP5+ optimized voltages in efuse(class0)VDD
			    along with VBB
	"ti,omap5-core-opp-supply" - OMAP5+ optimized voltages in efuse(class0) VDD
			    but no VBB.
- reg: Address and length of the efuse register set for the device (mandatory
	only for "ti,omap5-opp-supply")
- ti,efuse-settings: An array of u32 tuple items providing information about
	optimized efuse configuration. Each item consists of the following:
	volt: voltage in uV - reference voltage (OPP voltage)
	efuse_offseet: efuse offset from reg where the optimized voltage is stored.
- ti,absolute-max-voltage-uv: absolute maximum voltage for the OPP supply.

Example:

/* Device Node (CPU)  */
cpus {
	cpu0: cpu@0 {
		device_type = "cpu";

		...

		vdd-supply = <&vcc>;
		vbb-supply = <&abb_mpu>;
	};
};

/* OMAP OPP Supply with Class0 registers */
opp_supply_mpu: opp_supply@4a003b20 {
	compatible = "ti,omap5-opp-supply";
	reg = <0x4a003b20 0x8>;
	ti,efuse-settings = <
	/* uV   offset */
	1060000 0x0
	1160000 0x4
	1210000 0x8
	>;
	ti,absolute-max-voltage-uv = <1500000>;
};


code:
* Freescale 83xx and 512x PCI bridges

Freescale 83xx and 512x SOCs include the same PCI bridge core.

83xx/512x specific notes:
- reg: should contain two address length tuples
    The first is for the internal PCI bridge registers
    The second is for the PCI config space access registers

Example (MPC8313ERDB)
	pci0: pci@e0008500 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
				/* IDSEL 0x0E -mini PCI */
				 0x7000 0x0 0x0 0x1 &ipic 18 0x8
				 0x7000 0x0 0x0 0x2 &ipic 18 0x8
				 0x7000 0x0 0x0 0x3 &ipic 18 0x8
				 0x7000 0x0 0x0 0x4 &ipic 18 0x8

				/* IDSEL 0x0F - PCI slot */
				 0x7800 0x0 0x0 0x1 &ipic 17 0x8
				 0x7800 0x0 0x0 0x2 &ipic 18 0x8
				 0x7800 0x0 0x0 0x3 &ipic 17 0x8
				 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0x0 0x0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100		/* internal registers */
		       0xe0008300 0x8>;		/* config space access registers */
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};


code:
Aardvark PCIe controller

This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.

The Device Tree node describing an Aardvark PCIe controller must
contain the following properties:

 - compatible: Should be "marvell,armada-3700-pcie"
 - reg: range of registers for the PCIe controller
 - interrupts: the interrupt line of the PCIe controller
 - #address-cells: set to <3>
 - #size-cells: set to <2>
 - device_type: set to "pci"
 - ranges: ranges for the PCI memory and I/O regions
 - #interrupt-cells: set to <1>
 - msi-controller: indicates that the PCIe controller can itself
   handle MSI interrupts
 - msi-parent: pointer to the MSI controller to be used
 - interrupt-map-mask and interrupt-map: standard PCI properties to
   define the mapping of the PCIe interface to interrupt numbers.
 - bus-range: PCI bus numbers covered
 - phys: the PCIe PHY handle
 - max-link-speed: see pci.txt
 - reset-gpios: see pci.txt

In addition, the Device Tree describing an Aardvark PCIe controller
must include a sub-node that describes the legacy interrupt controller
built into the PCIe controller. This sub-node must have the following
properties:

 - interrupt-controller
 - #interrupt-cells: set to <1>

Example:

	pcie0: pcie@d0070000 {
		compatible = "marvell,armada-3700-pcie";
		device_type = "pci";
		reg = <0 0xd0070000 0 0x20000>;
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x00 0xff>;
		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
		#interrupt-cells = <1>;
		msi-controller;
		msi-parent = <&pcie0>;
		ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */
			  0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc 0>,
				<0 0 0 2 &pcie_intc 1>,
				<0 0 0 3 &pcie_intc 2>,
				<0 0 0 4 &pcie_intc 3>;
		phys = <&comphy1 0>;
		pcie_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <1>;
		};
	};


code:
* Altera PCIe MSI controller

Required properties:
- compatible:	should contain "altr,msi-1.0"
- reg:		specifies the physical base address of the controller and
		the length of the memory mapped region.
- reg-names:	must include the following entries:
		"csr": CSR registers
		"vector_slave": vectors slave port region
- interrupts:	specifies the interrupt source of the parent interrupt
		controller. The format of the interrupt specifier depends on the
		parent interrupt controller.
- num-vectors:	number of vectors, range 1 to 32.
- msi-controller:	indicates that this is MSI controller node

Example
msi0: msi@0xFF200000 {
	compatible = "altr,msi-1.0";
	reg = <0xFF200000 0x00000010
		0xFF200010 0x00000080>;
	reg-names = "csr", "vector_slave";
	interrupt-parent = <&hps_0_arm_gic_0>;
	interrupts = <0 42 4>;
	msi-controller;
	num-vectors = <32>;
};


code:
* Altera PCIe controller

Required properties:
- compatible :	should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
- reg:		a list of physical base address and length for TXS and CRA.
		For "altr,pcie-root-port-2.0", additional HIP base address and length.
- reg-names:	must include the following entries:
		"Txs": TX slave port region
		"Cra": Control register access region
		"Hip": Hard IP region (if "altr,pcie-root-port-2.0")
- interrupts:	specifies the interrupt source of the parent interrupt
		controller.  The format of the interrupt specifier depends
		on the parent interrupt controller.
- device_type:	must be "pci"
- #address-cells:	set to <3>
- #size-cells:		set to <2>
- #interrupt-cells:	set to <1>
- ranges:	describes the translation of addresses for root ports and
		standard PCI regions.
- interrupt-map-mask and interrupt-map: standard PCI properties to define the
		mapping of the PCIe interface to interrupt numbers.

Optional properties:
- msi-parent:	Link to the hardware entity that serves as the MSI controller
		for this PCIe controller.
- bus-range:	PCI bus numbers covered

Example
	pcie_0: pcie@c00000000 {
		compatible = "altr,pcie-root-port-1.0";
		reg = <0xc0000000 0x20000000>,
			<0xff220000 0x00004000>;
		reg-names = "Txs", "Cra";
		interrupt-parent = <&hps_0_arm_gic_0>;
		interrupts = <0 40 4>;
		interrupt-controller;
		#interrupt-cells = <1>;
		bus-range = <0x0 0xFF>;
		device_type = "pci";
		msi-parent = <&msi_to_gic_gen_0>;
		#address-cells = <3>;
		#size-cells = <2>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_0 1>,
			            <0 0 0 2 &pcie_0 2>,
			            <0 0 0 3 &pcie_0 3>,
			            <0 0 0 4 &pcie_0 4>;
		ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
			  0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
	};


code:
Amlogic Meson AXG DWC PCIE SoC controller

Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and
inherits common properties defined in
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.

Additional properties are described here:

Required properties:
- compatible:
	should contain :
	- "amlogic,axg-pcie" for AXG SoC Family
	- "amlogic,g12a-pcie" for G12A SoC Family
	to identify the core.
- reg:
	should contain the configuration address space.
- reg-names: Must be
	- "elbi"	External local bus interface registers
	- "cfg"		Meson specific registers
	- "config"	PCIe configuration space
- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Must include the following entries:
	- "pclk"       PCIe GEN 100M PLL clock
	- "port"       PCIe_x(A or B) RC clock gate
	- "general"    PCIe Phy clock
- resets: phandle to the reset lines.
- reset-names: must contain "port" and "apb"
       - "port"        Port A or B reset
       - "apb"         Share APB reset
- phys: should contain a phandle to the PCIE phy
- phy-names: must contain "pcie"

- device_type:
	should be "pci". As specified in snps,dw-pcie.yaml

Example configuration:

	pcie: pcie@f9800000 {
			compatible = "amlogic,axg-pcie", "snps,dw-pcie";
			reg = <0x0 0xf9800000 0x0 0x400000
					0x0 0xff646000 0x0 0x2000
					0x0 0xf9f00000 0x0 0x100000>;
			reg-names = "elbi", "cfg", "config";
			reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
			interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
			bus-range = <0x0 0xff>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;

			clocks = <&clkc CLKID_USB
					&clkc CLKID_PCIE_A
					&clkc CLKID_PCIE_CML_EN0>;
			clock-names = "general",
					"pclk",
					"port";
			resets = <&reset RESET_PCIE_A>,
				<&reset RESET_PCIE_APB>;
			reset-names = "port",
					"apb";
			phys = <&pcie_phy>;
			phy-names = "pcie";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple PCIe host controller

maintainers:
  - Mark Kettenis <kettenis@openbsd.org>

description: |
  The Apple PCIe host controller is a PCIe host controller with
  multiple root ports present in Apple ARM SoC platforms, including
  various iPhone and iPad devices and the "Apple Silicon" Macs.
  The controller incorporates Synopsys DesigWare PCIe logic to
  implements its root ports.  But the ATU found on most DesignWare
  PCIe host bridges is absent.

  All root ports share a single ECAM space, but separate GPIOs are
  used to take the PCI devices on those ports out of reset.  Therefore
  the standard "reset-gpios" and "max-link-speed" properties appear on
  the child nodes that represent the PCI bridges that correspond to
  the individual root ports.

  MSIs are handled by the PCIe controller and translated into regular
  interrupts.  A range of 32 MSIs is provided.  These 32 MSIs can be
  distributed over the root ports as the OS sees fit by programming
  the PCIe controller's port registers.

properties:
  compatible:
    items:
      - enum:
          - apple,t8103-pcie
          - apple,t6000-pcie
      - const: apple,pcie

  reg:
    minItems: 3
    maxItems: 6

  reg-names:
    minItems: 3
    items:
      - const: config
      - const: rc
      - const: port0
      - const: port1
      - const: port2
      - const: port3

  ranges:
    minItems: 2
    maxItems: 2

  interrupts:
    description:
      Interrupt specifiers, one for each root port.
    minItems: 1
    maxItems: 4

  msi-parent: true

  msi-ranges:
    maxItems: 1

  iommu-map: true
  iommu-map-mask: true

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - bus-range
  - interrupts
  - msi-controller
  - msi-parent
  - msi-ranges

unevaluatedProperties: false

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#
  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: apple,t8103-pcie
    then:
      properties:
        reg:
          maxItems: 5
        interrupts:
          maxItems: 3

examples:
  - |
    #include <dt-bindings/interrupt-controller/apple-aic.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      pcie0: pcie@690000000 {
        compatible = "apple,t8103-pcie", "apple,pcie";
        device_type = "pci";

        reg = <0x6 0x90000000 0x0 0x1000000>,
              <0x6 0x80000000 0x0 0x100000>,
              <0x6 0x81000000 0x0 0x4000>,
              <0x6 0x82000000 0x0 0x4000>,
              <0x6 0x83000000 0x0 0x4000>;
        reg-names = "config", "rc", "port0", "port1", "port2";

        interrupt-parent = <&aic>;
        interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
                     <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
                     <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;

        msi-controller;
        msi-parent = <&pcie0>;
        msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;

        iommu-map = <0x100 &dart0 1 1>,
                    <0x200 &dart1 1 1>,
                    <0x300 &dart2 1 1>;
        iommu-map-mask = <0xff00>;

        bus-range = <0 3>;
        #address-cells = <3>;
        #size-cells = <2>;
        ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
                 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;

        power-domains = <&ps_apcie_gp>;
        pinctrl-0 = <&pcie_pins>;
        pinctrl-names = "default";

        pci@0,0 {
          device_type = "pci";
          reg = <0x0 0x0 0x0 0x0 0x0>;
          reset-gpios = <&pinctrl_ap 152 0>;

          #address-cells = <3>;
          #size-cells = <2>;
          ranges;
        };

        pci@1,0 {
          device_type = "pci";
          reg = <0x800 0x0 0x0 0x0 0x0>;
          reset-gpios = <&pinctrl_ap 153 0>;

          #address-cells = <3>;
          #size-cells = <2>;
          ranges;
        };

        pci@2,0 {
          device_type = "pci";
          reg = <0x1000 0x0 0x0 0x0 0x0>;
          reset-gpios = <&pinctrl_ap 33 0>;

          #address-cells = <3>;
          #size-cells = <2>;
          ranges;
        };
      };
    };


code:
* Axis ARTPEC-6 PCIe interface

This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in snps,dw-pcie.yaml.

Required properties:
- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
	      "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
	      "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
	      "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
- reg: base addresses and lengths of the PCIe controller (DBI),
	the PHY controller, and configuration address space.
- reg-names: Must include the following entries:
	- "dbi"
	- "phy"
	- "config"
- interrupts: A list of interrupt outputs of the controller. Must contain an
  entry for each entry in the interrupt-names property.
- interrupt-names: Must include the following entries:
	- "msi": The interrupt that is asserted when an MSI is received
- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
	used to enable and control the Synopsys IP.

Example:

	pcie@f8050000 {
		compatible = "axis,artpec6-pcie", "snps,dw-pcie";
		reg = <0xf8050000 0x2000
		       0xf8040000 0x1000
		       0xc0000000 0x2000>;
		reg-names = "dbi", "phy", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
			  /* downstream I/O */
		ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
			  /* non-prefetchable memory */
			  0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
		num-lanes = <2>;
		bus-range = <0x00 0xff>;
		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "msi";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0x7>;
		interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
		                <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
		                <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
		                <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		axis,syscon-pcie = <&syscon>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Baikal-T1 PCIe Root Port Controller

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description:
  Embedded into Baikal-T1 SoC Root Complex controller with a single port
  activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
  to have just a single Root Port function and is capable of establishing the
  link up to Gen.3 speed on x4 lanes. It doesn't have embedded clock and reset
  control module, so the proper interface initialization is supposed to be
  performed by software. There four in- and four outbound iATU regions
  which can be used to emit all required TLP types on the PCIe bus.

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    const: baikal,bt1-pcie

  reg:
    description:
      DBI, DBI2 and at least 4KB outbound iATU-capable region for the
      peripheral devices CFG-space access.
    maxItems: 3

  reg-names:
    items:
      - const: dbi
      - const: dbi2
      - const: config

  interrupts:
    description:
      MSI, AER, PME, Hot-plug, Link Bandwidth Management, Link Equalization
      request and eight Read/Write eDMA IRQ lines are available.
    maxItems: 14

  interrupt-names:
    items:
      - const: dma0
      - const: dma1
      - const: dma2
      - const: dma3
      - const: dma4
      - const: dma5
      - const: dma6
      - const: dma7
      - const: msi
      - const: aer
      - const: pme
      - const: hp
      - const: bw_mg
      - const: l_eq

  clocks:
    description:
      DBI (attached to the APB bus), AXI-bus master and slave interfaces
      are fed up by the dedicated application clocks. A common reference
      clock signal is supposed to be attached to the corresponding Ref-pad
      of the SoC. It will be redistributed amongst the controller core
      sub-modules (pipe, core, aux, etc).
    maxItems: 4

  clock-names:
    items:
      - const: dbi
      - const: mstr
      - const: slv
      - const: ref

  resets:
    description:
      A comprehensive controller reset logic is supposed to be implemented
      by software, so almost all the possible application and core reset
      signals are exposed via the system CCU module.
    maxItems: 9

  reset-names:
    items:
      - const: mstr
      - const: slv
      - const: pwr
      - const: hot
      - const: phy
      - const: core
      - const: pipe
      - const: sticky
      - const: non-sticky

  baikal,bt1-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the Baikal-T1 System Controller DT node. It's required to
      access some additional PM, Reset-related and LTSSM signals.

  num-lanes:
    maximum: 4

  max-link-speed:
    maximum: 3

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/mips-gic.h>
    #include <dt-bindings/gpio/gpio.h>

    pcie@1f052000 {
      compatible = "baikal,bt1-pcie";
      device_type = "pci";
      reg = <0x1f052000 0x1000>, <0x1f053000 0x1000>, <0x1bdbf000 0x1000>;
      reg-names = "dbi", "dbi2", "config";
      #address-cells = <3>;
      #size-cells = <2>;
      ranges = <0x81000000 0 0x00000000 0x1bdb0000 0 0x00008000>,
               <0x82000000 0 0x20000000 0x08000000 0 0x13db0000>;
      bus-range = <0x0 0xff>;

      interrupts = <GIC_SHARED 80 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 81 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 82 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 83 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 84 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 85 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 86 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 87 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 88 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 89 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 90 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 91 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 92 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 93 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "dma0", "dma1", "dma2", "dma3",
                        "dma4", "dma5", "dma6", "dma7",
                        "msi", "aer", "pme", "hp", "bw_mg",
                        "l_eq";

      clocks = <&ccu_sys 1>, <&ccu_axi 6>, <&ccu_axi 7>, <&clk_pcie>;
      clock-names = "dbi", "mstr", "slv", "ref";

      resets = <&ccu_axi 6>, <&ccu_axi 7>, <&ccu_sys 7>, <&ccu_sys 10>,
               <&ccu_sys 4>, <&ccu_sys 6>, <&ccu_sys 5>, <&ccu_sys 8>,
               <&ccu_sys 9>;
      reset-names = "mstr", "slv", "pwr", "hot", "phy", "core", "pipe",
                    "sticky", "non-sticky";

      reset-gpios = <&port0 0 GPIO_ACTIVE_LOW>;

      num-lanes = <4>;
      max-link-speed = <3>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom iProc PCIe controller with the platform bus interface

maintainers:
  - Ray Jui <ray.jui@broadcom.com>
  - Scott Branden <scott.branden@broadcom.com>

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#
  - $ref: /schemas/interrupt-controller/msi-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          # for the first generation of PAXB based controller, used in SoCs
          # including NSP, Cygnus, NS2, and Pegasus
          - brcm,iproc-pcie
          # for the second generation of PAXB-based controllers, used in
          # Stingray
          - brcm,iproc-pcie-paxb-v2
          # For the first generation of PAXC based controller, used in NS2
          - brcm,iproc-pcie-paxc
          # For the second generation of PAXC based controller, used in Stingray
          - brcm,iproc-pcie-paxc-v2

  reg:
    maxItems: 1
    description: >
       Base address and length of the PCIe controller I/O register space

  interrupt-map: true

  interrupt-map-mask: true

  "#interrupt-cells":
    const: 1

  ranges:
    minItems: 1
    maxItems: 2
    description: >
      Ranges for the PCI memory and I/O regions

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: pcie-phy

  bus-range: true

  dma-coherent: true

  "#address-cells": true

  "#size-cells": true

  device_type: true

  brcm,pcie-ob:
    type: boolean
    description: >
      Some iProc SoCs do not have the outbound address mapping done by the
      ASIC after power on reset. In this case, SW needs to configure it

  brcm,pcie-ob-axi-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: >
       The offset from the AXI address to the internal address used by the
       iProc PCIe core (not the PCIe address)

  msi:
    type: object
    properties:
      compatible:
        items:
          - const: brcm,iproc-msi

  msi-parent: true

  msi-controller: true

  brcm,pcie-msi-inten:
    type: boolean
    description: >
      Needs to be present for some older iProc platforms that require the
      interrupt enable registers to be set explicitly to enable MSI

dependencies:
  brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"]
  brcm,pcie-msi-inten: [msi-controller]

required:
  - compatible
  - reg
  - ranges

if:
  properties:
    compatible:
      contains:
        enum:
          - brcm,iproc-pcie
then:
  required:
    - interrupt-map
    - interrupt-map-mask

unevaluatedProperties: false

examples:
  - |
   #include <dt-bindings/interrupt-controller/arm-gic.h>

   bus {
      #address-cells = <1>;
      #size-cells = <1>;
           pcie0: pcie@18012000 {
              compatible = "brcm,iproc-pcie";
              reg = <0x18012000 0x1000>;

              #interrupt-cells = <1>;
              interrupt-map-mask = <0 0 0 0>;
              interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;

              linux,pci-domain = <0>;

              bus-range = <0x00 0xff>;

              #address-cells = <3>;
              #size-cells = <2>;
              device_type = "pci";
              ranges = <0x81000000 0 0     0x28000000 0 0x00010000>,
                   <0x82000000 0 0x20000000 0x20000000 0 0x04000000>;

              phys = <&phy 0 5>;
              phy-names = "pcie-phy";

              brcm,pcie-ob;
              brcm,pcie-ob-axi-offset = <0x00000000>;

              msi-parent = <&msi0>;

              /* iProc event queue based MSI */
              msi0: msi {
                 compatible = "brcm,iproc-msi";
                 msi-controller;
                 interrupt-parent = <&gic>;
                 interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
                         <GIC_SPI 97 IRQ_TYPE_NONE>,
                         <GIC_SPI 98 IRQ_TYPE_NONE>,
                         <GIC_SPI 99 IRQ_TYPE_NONE>;
              };
           };

           pcie1: pcie@18013000 {
              compatible = "brcm,iproc-pcie";
              reg = <0x18013000 0x1000>;

              #interrupt-cells = <1>;
              interrupt-map-mask = <0 0 0 0>;
              interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;

              linux,pci-domain = <1>;

              bus-range = <0x00 0xff>;

              #address-cells = <3>;
              #size-cells = <2>;
              device_type = "pci";
              ranges = <0x81000000 0 0     0x48000000 0 0x00010000>,
                   <0x82000000 0 0x40000000 0x40000000 0 0x04000000>;

              phys = <&phy 1 6>;
              phy-names = "pcie-phy";
           };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Brcmstb PCIe Host Controller

maintainers:
  - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>

properties:
  compatible:
    items:
      - enum:
          - brcm,bcm2711-pcie # The Raspberry Pi 4
          - brcm,bcm4908-pcie
          - brcm,bcm7211-pcie # Broadcom STB version of RPi4
          - brcm,bcm7278-pcie # Broadcom 7278 Arm
          - brcm,bcm7216-pcie # Broadcom 7216 Arm
          - brcm,bcm7445-pcie # Broadcom 7445 Arm
          - brcm,bcm7425-pcie # Broadcom 7425 MIPs
          - brcm,bcm7435-pcie # Broadcom 7435 MIPs

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    items:
      - description: PCIe host controller
      - description: builtin MSI controller

  interrupt-names:
    minItems: 1
    items:
      - const: pcie
      - const: msi

  ranges:
    minItems: 1
    maxItems: 4

  dma-ranges:
    minItems: 1
    maxItems: 6

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: sw_pcie

  msi-controller:
    description: Identifies the node as an MSI controller.

  msi-parent:
    description: MSI controller the device is capable of using.

  brcm,enable-ssc:
    description: Indicates usage of spread-spectrum clocking.
    type: boolean

  aspm-no-l0s: true

  brcm,scb-sizes:
    description: u64 giving the 64bit PCIe memory
      viewport size of a memory controller.  There may be up to
      three controllers, and each size must be a power of two
      with a size greater or equal to the amount of memory the
      controller supports.  Note that each memory controller
      may have two component regions -- base and extended -- so
      this information cannot be deduced from the dma-ranges.
    $ref: /schemas/types.yaml#/definitions/uint64-array
    items:
      minItems: 1
      maxItems: 3

required:
  - compatible
  - reg
  - ranges
  - dma-ranges
  - "#interrupt-cells"
  - interrupts
  - interrupt-names
  - interrupt-map-mask
  - interrupt-map
  - msi-controller

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#
  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: brcm,bcm4908-pcie
    then:
      properties:
        resets:
          items:
            - description: reset controller handling the PERST# signal

        reset-names:
          items:
            - const: perst

      required:
        - resets
        - reset-names
  - if:
      properties:
        compatible:
          contains:
            const: brcm,bcm7216-pcie
    then:
      properties:
        resets:
          items:
            - description: phandle pointing to the RESCAL reset controller

        reset-names:
          items:
            - const: rescal

      required:
        - resets
        - reset-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    scb {
            #address-cells = <2>;
            #size-cells = <1>;
            pcie0: pcie@7d500000 {
                    compatible = "brcm,bcm2711-pcie";
                    reg = <0x0 0x7d500000 0x9310>;
                    device_type = "pci";
                    #address-cells = <3>;
                    #size-cells = <2>;
                    #interrupt-cells = <1>;
                    interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
                                 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
                    interrupt-names = "pcie", "msi";
                    interrupt-map-mask = <0x0 0x0 0x0 0x7>;
                    interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
                                     0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
                                     0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
                                     0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;

                    msi-parent = <&pcie0>;
                    msi-controller;
                    ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
                    dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
                                 <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
                    brcm,enable-ssc;
                    brcm,scb-sizes =  <0x0000000080000000 0x0000000080000000>;

                    /* PCIe bridge, Root Port */
                    pci@0,0 {
                            #address-cells = <3>;
                            #size-cells = <2>;
                            reg = <0x0 0x0 0x0 0x0 0x0>;
                            compatible = "pciclass,0604";
                            device_type = "pci";
                            vpcie3v3-supply = <&vreg7>;
                            ranges;

                            /* PCIe endpoint */
                            pci-ep@0,0 {
                                    assigned-addresses =
                                        <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
                                    reg = <0x0 0x0 0x0 0x0 0x0>;
                                    compatible = "pci14e4,1688";
                            };
                    };
            };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence PCIe EP Controller

maintainers:
  - Tom Joseph <tjoseph@cadence.com>

allOf:
  - $ref: "cdns-pcie-ep.yaml#"

properties:
  compatible:
    const: cdns,cdns-pcie-ep

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: reg
      - const: mem

required:
  - reg
  - reg-names

unevaluatedProperties: false

examples:
  - |
    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie-ep@fc000000 {
                compatible = "cdns,cdns-pcie-ep";
                reg = <0x0 0xfc000000 0x0 0x01000000>,
                      <0x0 0x80000000 0x0 0x40000000>;
                reg-names = "reg", "mem";
                cdns,max-outbound-regions = <16>;
                max-functions = /bits/ 8 <8>;
                phys = <&pcie_phy0>;
                phy-names = "pcie-phy";
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence PCIe host controller

maintainers:
  - Tom Joseph <tjoseph@cadence.com>

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#
  - $ref: "cdns-pcie-host.yaml#"

properties:
  compatible:
    const: cdns,cdns-pcie-host

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: reg
      - const: cfg

  msi-parent: true

required:
  - reg
  - reg-names

unevaluatedProperties: false

examples:
  - |
    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie@fb000000 {
            compatible = "cdns,cdns-pcie-host";
            device_type = "pci";
            #address-cells = <3>;
            #size-cells = <2>;
            bus-range = <0x0 0xff>;
            linux,pci-domain = <0>;
            vendor-id = <0x17cd>;
            device-id = <0x0200>;

            reg = <0x0 0xfb000000  0x0 0x01000000>,
                  <0x0 0x41000000  0x0 0x00001000>;
            reg-names = "reg", "cfg";

            ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,
                     <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;
            dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;

            #interrupt-cells = <0x1>;

            interrupt-map = <0x0 0x0 0x0  0x1  &gic  0x0 0x0 0x0 14 0x1>,
                 <0x0 0x0 0x0  0x2  &gic  0x0 0x0 0x0 15 0x1>,
                 <0x0 0x0 0x0  0x3  &gic  0x0 0x0 0x0 16 0x1>,
                 <0x0 0x0 0x0  0x4  &gic  0x0 0x0 0x0 17 0x1>;

            interrupt-map-mask = <0x0 0x0 0x0  0x7>;

            msi-parent = <&its_pci>;

            phys = <&pcie_phy0>;
            phy-names = "pcie-phy";
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence PCIe Device

maintainers:
  - Tom Joseph <tjoseph@cadence.com>

allOf:
  - $ref: "cdns-pcie.yaml#"
  - $ref: "pci-ep.yaml#"

properties:
  cdns,max-outbound-regions:
    description: maximum number of outbound regions
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 32
    default: 32

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence PCIe Host

maintainers:
  - Tom Joseph <tjoseph@cadence.com>

allOf:
  - $ref: "/schemas/pci/pci-bus.yaml#"
  - $ref: "cdns-pcie.yaml#"

properties:
  cdns,max-outbound-regions:
    description: maximum number of outbound regions
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 32
    default: 32
    deprecated: true

  cdns,no-bar-match-nbits:
    description:
      Set into the no BAR match register to configure the number of least
      significant bits kept during inbound (PCIe -> AXI) address translations
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 64
    default: 32
    deprecated: true

  msi-parent: true

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence PCIe Core

maintainers:
  - Tom Joseph <tjoseph@cadence.com>

properties:
  phys:
    description:
      One per lane if more than one in the list. If only one PHY listed it must
      manage all lanes.
    minItems: 1
    maxItems: 16

  phy-names:
    items:
      - const: pcie-phy
    # FIXME: names when more than 1

additionalProperties: true