code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/amlogic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic MesonX

maintainers:
  - Kevin Hilman <khilman@baylibre.com>

description: |+
  Work in progress statement:

  Device tree files and bindings applying to Amlogic SoCs and boards are
  considered "unstable". Any Amlogic device tree binding may change at
  any time. Be sure to use a device tree binary and a kernel image
  generated from the same source tree.

  Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
  stable binding/ABI.

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: Boards with the Amlogic Meson6 SoC
        items:
          - enum:
              - geniatech,atv1200
          - const: amlogic,meson6

      - description: Boards with the Amlogic Meson8 SoC
        items:
          - enum:
              - minix,neo-x8
          - const: amlogic,meson8

      - description: Boards with the Amlogic Meson8m2 SoC
        items:
          - enum:
              - tronsmart,mxiii-plus
          - const: amlogic,meson8m2

      - description: Boards with the Amlogic Meson8b SoC
        items:
          - enum:
              - endless,ec100
              - hardkernel,odroid-c1
              - tronfy,mxq
          - const: amlogic,meson8b

      - description: Boards with the Amlogic Meson GXBaby SoC
        items:
          - enum:
              - amlogic,p200
              - amlogic,p201
              - friendlyarm,nanopi-k2
              - hardkernel,odroid-c2
              - nexbox,a95x
              - videostrong,kii-pro
              - wetek,hub
              - wetek,play2
          - const: amlogic,meson-gxbb

      - description: Tronsmart Vega S95 devices
        items:
          - enum:
              - tronsmart,vega-s95-pro
              - tronsmart,vega-s95-meta
              - tronsmart,vega-s95-telos
          - const: tronsmart,vega-s95
          - const: amlogic,meson-gxbb

      - description: Boards with the Amlogic Meson GXL S805X SoC
        items:
          - enum:
              - amlogic,p241
              - libretech,aml-s805x-ac
          - const: amlogic,s805x
          - const: amlogic,meson-gxl

      - description: Boards with the Amlogic Meson GXL S905W SoC
        items:
          - enum:
              - amlogic,p281
              - oranth,tx3-mini
              - jethome,jethub-j80
          - const: amlogic,s905w
          - const: amlogic,meson-gxl

      - description: Boards with the Amlogic Meson GXL S905X SoC
        items:
          - enum:
              - amlogic,p212
              - hwacom,amazetv
              - khadas,vim
              - libretech,aml-s905x-cc
              - libretech,aml-s905x-cc-v2
              - nexbox,a95x
          - const: amlogic,s905x
          - const: amlogic,meson-gxl

      - description: Boards with the Amlogic Meson GXL S905D SoC
        items:
          - enum:
              - amlogic,p230
              - amlogic,p231
              - libretech,aml-s905d-pc
              - osmc,vero4k-plus
              - phicomm,n1
              - smartlabs,sml5442tw
              - videostrong,gxl-kii-pro
          - const: amlogic,s905d
          - const: amlogic,meson-gxl

      - description: Boards with the Amlogic Meson GXM S912 SoC
        items:
          - enum:
              - amlogic,q200
              - amlogic,q201
              - azw,gt1-ultimate
              - khadas,vim2
              - kingnovel,r-box-pro
              - libretech,aml-s912-pc
              - minix,neo-u9h
              - nexbox,a1
              - tronsmart,vega-s96
              - videostrong,gxm-kiii-pro
              - wetek,core2
          - const: amlogic,s912
          - const: amlogic,meson-gxm

      - description: Boards with the Amlogic Meson AXG A113D SoC
        items:
          - enum:
              - amlogic,s400
              - jethome,jethub-j100
              - jethome,jethub-j110
          - const: amlogic,a113d
          - const: amlogic,meson-axg

      - description: Boards with the Amlogic Meson G12A S905D2/X2/Y2 SoC
        items:
          - enum:
              - amediatech,x96-max
              - amlogic,u200
              - radxa,zero
              - seirobotics,sei510
          - const: amlogic,g12a

      - description: Boards with the Amlogic Meson G12B A311D SoC
        items:
          - enum:
              - khadas,vim3
          - const: amlogic,a311d
          - const: amlogic,g12b

      - description: Boards with the Amlogic Meson G12B S922X SoC
        items:
          - enum:
              - azw,gsking-x
              - azw,gtking
              - azw,gtking-pro
              - hardkernel,odroid-go-ultra
              - hardkernel,odroid-n2
              - hardkernel,odroid-n2-plus
              - khadas,vim3
              - ugoos,am6
          - const: amlogic,s922x
          - const: amlogic,g12b

      - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
        items:
          - enum:
              - amediatech,x96-air
              - amediatech,x96-air-gbit
              - bananapi,bpi-m5
              - cyx,a95xf3-air
              - cyx,a95xf3-air-gbit
              - hardkernel,odroid-c4
              - hardkernel,odroid-hc4
              - haochuangyi,h96-max
              - khadas,vim3l
              - seirobotics,sei610
          - const: amlogic,sm1

      - description: Boards with the Amlogic Meson A1 A113L SoC
        items:
          - enum:
              - amlogic,ad401
          - const: amlogic,a1

      - description: Boards with the Amlogic Meson S4 S805X2 SoC
        items:
          - enum:
              - amlogic,aq222
          - const: amlogic,s4

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Meson Firmware registers Interface

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

description: |
  The Meson SoCs have a register bank with status and data shared with the
  secure firmware.

# We need a select here so we don't match all nodes with 'syscon'
select:
  properties:
    compatible:
      contains:
        const: amlogic,meson-gx-ao-secure
  required:
    - compatible

properties:
  compatible:
    items:
      - const: amlogic,meson-gx-ao-secure
      - const: syscon

  reg:
    maxItems: 1

  amlogic,has-chip-id:
    description: |
      A firmware register encodes the SoC type, package and revision
      information on the Meson GX SoCs. If present, the interface gives
      the current SoC version.
    type: boolean

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    ao-secure@140 {
          compatible = "amlogic,meson-gx-ao-secure", "syscon";
          reg = <0x140 0x140>;
          amlogic,has-chip-id;
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Meson8/Meson8b/Meson8m2 SECBUS2 register interface

maintainers:
  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>

description: |
  The Meson8/Meson8b/Meson8m2 SoCs have a register bank called SECBUS2 which
  contains registers for various IP blocks such as pin-controller bits for
  the BSD_EN and TEST_N GPIOs as well as some AO ARC core control bits.
  The registers can be accessed directly when not running in "secure mode".
  When "secure mode" is enabled then these registers have to be accessed
  through secure monitor calls.

properties:
  compatible:
    items:
      - enum:
          - amlogic,meson8-secbus2
          - amlogic,meson8b-secbus2
      - const: syscon

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    secbus2: system-controller@4000 {
      compatible = "amlogic,meson8-secbus2", "syscon";
      reg = <0x4000 0x2000>;
    };


code:
Amlogic Meson8 and Meson8b "analog top" registers:
--------------------------------------------------

The analog top registers contain information about the so-called
"metal revision" (which encodes the "minor version") of the SoC.

Required properties:
- reg: the register range of the analog top registers
- compatible: depending on the SoC this should be one of:
		- "amlogic,meson8-analog-top"
		- "amlogic,meson8b-analog-top"
		along with "syscon"

Example:

	analog_top: analog-top@81a8 {
		compatible = "amlogic,meson8-analog-top", "syscon";
		reg = <0x81a8 0x14>;
	};


code:
Amlogic Meson6/Meson8/Meson8b assist registers:
-----------------------------------------------

The assist registers contain basic information about the SoC,
for example the encoded SoC part number.

Required properties:
- reg: the register range of the assist registers
- compatible: should be "amlogic,meson-mx-assist" along with "syscon"

Example:

	assist: assist@7c00 {
		compatible = "amlogic,meson-mx-assist", "syscon";
		reg = <0x7c00 0x200>;
	};


code:
Amlogic Meson6/Meson8/Meson8b bootrom:
--------------------------------------

The bootrom register area can be used to access SoC specific
information, such as the "misc version".

Required properties:
- reg: the register range of the bootrom registers
- compatible: should be "amlogic,meson-mx-bootrom" along with "syscon"

Example:

	bootrom: bootrom@d9040000 {
		compatible = "amlogic,meson-mx-bootrom", "syscon";
		reg = <0xd9040000 0x10000>;
	};


code:
Amlogic Meson8 and Meson8b power-management-unit:
-------------------------------------------------

The pmu is used to turn off and on different power domains of the SoCs
This includes the power to the CPU cores.

Required node properties:
- compatible value : depending on the SoC this should be one of:
			"amlogic,meson8-pmu"
			"amlogic,meson8b-pmu"
- reg : physical base address and the size of the registers window

Example:

	pmu@c81000e4 {
		compatible = "amlogic,meson8b-pmu", "syscon";
		reg = <0xc81000e0 0x18>;
	};


code:
APM X-GENE SoC series SCU Registers

This system clock unit contain various register that control block resets,
clock enable/disables, clock divisors and other deepsleep registers.

Properties:
 - compatible : should contain two values. First value must be:
		   - "apm,xgene-scu"
		second value must be always "syscon".

 - reg : offset and length of the register set.

Example :
	scu: system-clk-controller@17000000 {
		compatible = "apm,xgene-scu","syscon";
		reg = <0x0 0x17000000 0x0 0x400>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/apple.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple ARM Machine

maintainers:
  - Hector Martin <marcan@marcan.st>

description: |
  ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".

  This currently includes devices based on the "M1" SoC:

  - Mac mini (M1, 2020)
  - MacBook Pro (13-inch, M1, 2020)
  - MacBook Air (M1, 2020)
  - iMac (24-inch, M1, 2021)

  And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs:

  - MacBook Pro (14-inch, M1 Pro, 2021)
  - MacBook Pro (14-inch, M1 Max, 2021)
  - MacBook Pro (16-inch, M1 Pro, 2021)
  - MacBook Pro (16-inch, M1 Max, 2021)
  - Mac Studio (M1 Max, 2022)
  - Mac Studio (M1 Ultra, 2022)

  The compatible property should follow this format:

  compatible = "apple,<targettype>", "apple,<socid>", "apple,arm-platform";

  <targettype> represents the board/device and comes from the `target-type`
  property of the root node of the Apple Device Tree, lowercased. It can be
  queried on macOS using the following command:

  $ ioreg -d2 -l | grep target-type

  <socid> is the lowercased SoC ID. Apple uses at least *five* different
  names for their SoCs:

  - Marketing name ("M1")
  - Internal name ("H13G")
  - Codename ("Tonga")
  - SoC ID ("T8103")
  - Package/IC part number ("APL1102")

  Devicetrees should use the lowercased SoC ID, to avoid confusion if
  multiple SoCs share the same marketing name. This can be obtained from
  the `compatible` property of the arm-io node of the Apple Device Tree,
  which can be queried as follows on macOS:

  $ ioreg -n arm-io | grep compatible

properties:
  $nodename:
    const: "/"
  compatible:
    oneOf:
      - description: Apple M1 SoC based platforms
        items:
          - enum:
              - apple,j274 # Mac mini (M1, 2020)
              - apple,j293 # MacBook Pro (13-inch, M1, 2020)
              - apple,j313 # MacBook Air (M1, 2020)
              - apple,j456 # iMac (24-inch, 4x USB-C, M1, 2021)
              - apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021)
          - const: apple,t8103
          - const: apple,arm-platform

      - description: Apple M1 Pro SoC based platforms
        items:
          - enum:
              - apple,j314s # MacBook Pro (14-inch, M1 Pro, 2021)
              - apple,j316s # MacBook Pro (16-inch, M1 Pro, 2021)
          - const: apple,t6000
          - const: apple,arm-platform

      - description: Apple M1 Max SoC based platforms
        items:
          - enum:
              - apple,j314c # MacBook Pro (14-inch, M1 Max, 2021)
              - apple,j316c # MacBook Pro (16-inch, M1 Max, 2021)
              - apple,j375c # Mac Studio (M1 Max, 2022)
          - const: apple,t6001
          - const: apple,arm-platform

      - description: Apple M1 Ultra SoC based platforms
        items:
          - enum:
              - apple,j375d # Mac Studio (M1 Ultra, 2022)
          - const: apple,t6002
          - const: apple,arm-platform

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/apple/apple,pmgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple SoC Power Manager (PMGR)

maintainers:
  - Hector Martin <marcan@marcan.st>

description: |
  Apple SoCs include PMGR blocks responsible for power management,
  which can control various clocks, resets, power states, and
  performance features. This node represents the PMGR as a syscon,
  with sub-nodes representing individual features.

properties:
  $nodename:
    pattern: "^power-management@[0-9a-f]+$"

  compatible:
    items:
      - enum:
          - apple,t8103-pmgr
          - apple,t6000-pmgr
      - const: apple,pmgr
      - const: syscon
      - const: simple-mfd

  reg:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

patternProperties:
  "power-controller@[0-9a-f]+$":
    description:
      The individual power management domains within this controller
    type: object
    $ref: /schemas/power/apple,pmgr-pwrstate.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        power-management@23b700000 {
            compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
            #address-cells = <1>;
            #size-cells = <1>;
            reg = <0x2 0x3b700000 0x0 0x14000>;

            ps_sio: power-controller@1c0 {
                compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
                reg = <0x1c0 8>;
                #power-domain-cells = <0>;
                #reset-cells = <0>;
                label = "sio";
                apple,always-on;
            };

            ps_uart_p: power-controller@220 {
                compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
                reg = <0x220 8>;
                #power-domain-cells = <0>;
                #reset-cells = <0>;
                label = "uart_p";
                power-domains = <&ps_sio>;
            };

            ps_uart0: power-controller@270 {
                compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
                reg = <0x270 8>;
                #power-domain-cells = <0>;
                #reset-cells = <0>;
                label = "uart0";
                power-domains = <&ps_uart_p>;
            };
        };

        power-management@23d280000 {
            compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
            #address-cells = <1>;
            #size-cells = <1>;
            reg = <0x2 0x3d280000 0x0 0xc000>;

            ps_aop_filter: power-controller@4000 {
                compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
                reg = <0x4000 8>;
                #power-domain-cells = <0>;
                #reset-cells = <0>;
                label = "aop_filter";
            };

            ps_aop_base: power-controller@4010 {
                compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
                reg = <0x4010 8>;
                #power-domain-cells = <0>;
                #reset-cells = <0>;
                label = "aop_base";
                power-domains = <&ps_aop_filter>;
            };

            ps_aop_shim: power-controller@4038 {
                compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
                reg = <0x4038 8>;
                #power-domain-cells = <0>;
                #reset-cells = <0>;
                label = "aop_shim";
                power-domains = <&ps_aop_base>;
            };

            ps_aop_uart0: power-controller@4048 {
                compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
                reg = <0x4048 8>;
                #power-domain-cells = <0>;
                #reset-cells = <0>;
                label = "aop_uart0";
                power-domains = <&ps_aop_shim>;
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM CCI Cache Coherent Interconnect

maintainers:
  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

description: >
  ARM multi-cluster systems maintain intra-cluster coherency through a cache
  coherent interconnect (CCI) that is capable of monitoring bus transactions
  and manage coherency, TLB invalidations and memory barriers.

  It allows snooping and distributed virtual memory message broadcast across
  clusters, through memory mapped interface, with a global control register
  space and multiple sets of interface control registers, one per slave
  interface.

properties:
  $nodename:
    pattern: "^cci(@[0-9a-f]+)?$"

  compatible:
    enum:
      - arm,cci-400
      - arm,cci-500
      - arm,cci-550

  reg:
    maxItems: 1
    description: >
      Specifies base physical address of CCI control registers common to all
      interfaces.

  "#address-cells": true
  "#size-cells": true
  ranges: true

patternProperties:
  "^slave-if@[0-9a-f]+$":
    type: object

    properties:
      compatible:
        const: arm,cci-400-ctrl-if

      interface-type:
        enum:
          - ace
          - ace-lite

      reg:
        maxItems: 1

    required:
      - compatible
      - interface-type
      - reg

    additionalProperties: false

  "^pmu@[0-9a-f]+$":
    type: object

    properties:
      compatible:
        oneOf:
          - const: arm,cci-400-pmu,r0
          - const: arm,cci-400-pmu,r1
          - const: arm,cci-400-pmu
            deprecated: true
            description: >
              Permitted only where OS has secure access to CCI registers
          - const: arm,cci-500-pmu,r0
          - const: arm,cci-550-pmu,r0

      interrupts:
        minItems: 1
        maxItems: 8
        description: >
          List of counter overflow interrupts, one per counter. The interrupts
          must be specified starting with the cycle counter overflow interrupt,
          followed by counter0 overflow interrupt, counter1 overflow
          interrupt,...  ,counterN overflow interrupt.

          The CCI PMU has an interrupt signal for each counter. The number of
          interrupts must be equal to the number of counters.

      reg:
        maxItems: 1

    required:
      - compatible
      - interrupts
      - reg

    additionalProperties: false

required:
  - "#address-cells"
  - "#size-cells"
  - compatible
  - ranges
  - reg

additionalProperties: false

examples:
  - |
      / {
          #address-cells = <2>;
          #size-cells = <2>;

          compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
          model = "V2P-CA15_CA7";
          arm,hbi = <0x249>;
          interrupt-parent = <&gic>;

          gic: interrupt-controller {
              interrupt-controller;
              #interrupt-cells = <3>;
          };

          /*
           * This CCI node corresponds to a CCI component whose control
           * registers sits at address 0x000000002c090000.
           *
           * CCI slave interface @0x000000002c091000 is connected to dma
           * controller dma0.
           *
           * CCI slave interface @0x000000002c094000 is connected to CPUs
           * {CPU0, CPU1};
           *
           * CCI slave interface @0x000000002c095000 is connected to CPUs
           * {CPU2, CPU3};
           */

          cpus {
              #size-cells = <0>;
              #address-cells = <1>;

              CPU0: cpu@0 {
                  device_type = "cpu";
                  compatible = "arm,cortex-a15";
                  cci-control-port = <&cci_control1>;
                  reg = <0x0>;
              };

              CPU1: cpu@1 {
                  device_type = "cpu";
                  compatible = "arm,cortex-a15";
                  cci-control-port = <&cci_control1>;
                  reg = <0x1>;
              };

              CPU2: cpu@100 {
                  device_type = "cpu";
                  compatible = "arm,cortex-a7";
                  cci-control-port = <&cci_control2>;
                  reg = <0x100>;
              };

              CPU3: cpu@101 {
                  device_type = "cpu";
                  compatible = "arm,cortex-a7";
                  cci-control-port = <&cci_control2>;
                  reg = <0x101>;
              };
          };

          cci@2c090000 {
              compatible = "arm,cci-400";
              #address-cells = <1>;
              #size-cells = <1>;
              reg = <0x0 0x2c090000 0 0x1000>;
              ranges = <0x0 0x0 0x2c090000 0x10000>;

              cci_control0: slave-if@1000 {
                  compatible = "arm,cci-400-ctrl-if";
                  interface-type = "ace-lite";
                  reg = <0x1000 0x1000>;
              };

              cci_control1: slave-if@4000 {
                  compatible = "arm,cci-400-ctrl-if";
                  interface-type = "ace";
                  reg = <0x4000 0x1000>;
              };

              cci_control2: slave-if@5000 {
                  compatible = "arm,cci-400-ctrl-if";
                  interface-type = "ace";
                  reg = <0x5000 0x1000>;
              };

              pmu@9000 {
                  compatible = "arm,cci-400-pmu";
                  reg = <0x9000 0x5000>;
                  interrupts = <0 101 4>,
                    <0 102 4>,
                    <0 103 4>,
                    <0 104 4>,
                    <0 105 4>;
              };
          };
      };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm Coresight Address Translation Unit (CATU)

maintainers:
  - Mathieu Poirier <mathieu.poirier@linaro.org>
  - Mike Leach <mike.leach@linaro.org>
  - Leo Yan <leo.yan@linaro.org>
  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |
  CoreSight components are compliant with the ARM CoreSight architecture
  specification and can be connected in various topologies to suit a particular
  SoCs tracing needs. These trace components can generally be classified as
  sinks, links and sources. Trace data produced by one or more sources flows
  through the intermediate links connecting the source to the currently selected
  sink.

  The CoreSight Address Translation Unit (CATU) translates addresses between an
  AXI master and system memory. The CATU is normally used along with the TMC to
  implement scattering of virtual trace buffers in physical memory. The CATU
  translates contiguous Virtual Addresses (VAs) from an AXI master into
  non-contiguous Physical Addresses (PAs) that are intended for system memory.

# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
  properties:
    compatible:
      contains:
        const: arm,coresight-catu
  required:
    - compatible

allOf:
  - $ref: /schemas/arm/primecell.yaml#

properties:
  compatible:
    items:
      - const: arm,coresight-catu
      - const: arm,primecell

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: apb_pclk
      - const: atclk

  interrupts:
    maxItems: 1
    description: Address translation error interrupt

  power-domains:
    maxItems: 1

  in-ports:
    $ref: /schemas/graph.yaml#/properties/ports
    additionalProperties: false

    properties:
      port:
        description: AXI Slave connected to another Coresight component
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - in-ports

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    catu@207e0000 {
        compatible = "arm,coresight-catu", "arm,primecell";
        reg = <0x207e0000 0x1000>;

        clocks = <&oscclk6a>;
        clock-names = "apb_pclk";

        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
        in-ports {
            port {
                catu_in_port: endpoint {
                    remote-endpoint = <&etr_out_port>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: CoreSight CPU Debug Component

maintainers:
  - Mathieu Poirier <mathieu.poirier@linaro.org>
  - Mike Leach <mike.leach@linaro.org>
  - Leo Yan <leo.yan@linaro.org>
  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |
  CoreSight CPU debug component are compliant with the ARMv8 architecture
  reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
  external debug module is mainly used for two modes: self-hosted debug and
  external debug, and it can be accessed from mmio region from Coresight and
  eventually the debug module connects with CPU for debugging. And the debug
  module provides sample-based profiling extension, which can be used to sample
  CPU program counter, secure state and exception level, etc; usually every CPU
  has one dedicated debug module to be connected.

select:
  properties:
    compatible:
      contains:
        const: arm,coresight-cpu-debug
  required:
    - compatible

allOf:
  - $ref: /schemas/arm/primecell.yaml#

properties:
  compatible:
    items:
      - const: arm,coresight-cpu-debug
      - const: arm,primecell

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    maxItems: 1

  cpu:
    description:
      A phandle to the cpu this debug component is bound to.
    $ref: /schemas/types.yaml#/definitions/phandle

  power-domains:
    maxItems: 1
    description:
      A phandle to the debug power domain if the debug logic has its own
      dedicated power domain. CPU idle states may also need to be separately
      constrained to keep CPU cores powered.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - cpu

unevaluatedProperties: false

examples:
  - |
    debug@f6590000 {
        compatible = "arm,coresight-cpu-debug", "arm,primecell";
        reg = <0xf6590000 0x1000>;
        clocks = <&sys_ctrl 1>;
        clock-names = "apb_pclk";
        cpu = <&cpu0>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Coresight Cross Trigger Interface (CTI) device.

description: |
  The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
  to one or more CoreSight components and/or a CPU, with CTIs interconnected in
  a star topology via the Cross Trigger Matrix (CTM), which is not programmable.
  The ECT components are not part of the trace generation data path and are thus
  not part of the CoreSight graph.

  The CTI component properties define the connections between the individual
  CTI and the components it is directly connected to, consisting of input and
  output hardware trigger signals. CTIs can have a maximum number of input and
  output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The
  number is defined at design time, the maximum of each defined in the DEVID
  register.

  CTIs are interconnected in a star topology via the CTM, using a number of
  programmable channels, usually 4, but again implementation defined and
  described in the DEVID register. The star topology is not required to be
  described in the bindings as the actual connections are software
  programmable.

  In general the connections between CTI and components via the trigger signals
  are implementation defined, except when the CTI is connected to an ARM v8
  architecture core and optional ETM.

  In this case the ARM v8 architecture defines the required signal connections
  between CTI and the CPU core and ETM if present. In the case of a v8
  architecturally connected CTI an additional compatible string is used to
  indicate this feature (arm,coresight-cti-v8-arch).

  When CTI trigger connection information is unavailable then a minimal driver
  binding can be declared with no explicit trigger signals. This will result
  the driver detecting the maximum available triggers and channels from the
  DEVID register and make them all available for use as a single default
  connection. Any user / client application will require additional information
  on the connections between the CTI and other components for correct operation.
  This information might be found by enabling the Integration Test registers in
  the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel
  configuration). These registers may be used to explore the trigger connections
  between CTI and other CoreSight components.

  Certain triggers between CoreSight devices and the CTI have specific types
  and usages. These can be defined along with the signal indexes with the
  constants defined in <dt-bindings/arm/coresight-cti-dt.h>

  For example a CTI connected to a core will usually have a DBGREQ signal. This
  is defined in the binding as type PE_EDBGREQ. These types will appear in an
  optional array alongside the signal indexes. Omitting types will default all
  signals to GEN_IO.

  Note that some hardware trigger signals can be connected to non-CoreSight
  components (e.g. UART etc) depending on hardware implementation.

maintainers:
  - Mike Leach <mike.leach@linaro.org>

allOf:
  - $ref: /schemas/arm/primecell.yaml#

# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
  properties:
    compatible:
      contains:
        enum:
          - arm,coresight-cti
  required:
    - compatible

properties:
  $nodename:
    pattern: "^cti(@[0-9a-f]+)$"
  compatible:
    oneOf:
      - items:
          - const: arm,coresight-cti
          - const: arm,primecell
      - items:
          - const: arm,coresight-cti-v8-arch
          - const: arm,coresight-cti
          - const: arm,primecell

  reg:
    maxItems: 1

  cpu:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Handle to cpu this device is associated with. This must appear in the
      base cti node if compatible string arm,coresight-cti-v8-arch is used,
      or may appear in a trig-conns child node when appropriate.

  power-domains:
    maxItems: 1

  arm,cti-ctm-id:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Defines the CTM this CTI is connected to, in large systems with multiple
      separate CTI/CTM nets. Typically multi-socket systems where the CTM is
      propagated between sockets.

  arm,cs-dev-assoc:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      defines a phandle reference to an associated CoreSight trace device.
      When the associated trace device is enabled, then the respective CTI
      will be enabled. Use in a trig-conns node, or in CTI base node when
      compatible string arm,coresight-cti-v8-arch used. If the associated
      device has not been registered then the node name will be stored as
      the connection name for later resolution. If the associated device is
      not a CoreSight device or not registered then the node name will remain
      the connection name and automatic enabling will not occur.

  # size cells and address cells required if trig-conns node present.
  "#size-cells":
    const: 0

  "#address-cells":
    const: 1

patternProperties:
  '^trig-conns@([0-9]+)$':
    type: object
    description:
      A trigger connections child node which describes the trigger signals
      between this CTI and another hardware device. This device may be a CPU,
      CoreSight device, any other hardware device or simple external IO lines.
      The connection may have both input and output triggers, or only one or the
      other.

    properties:
      reg:
        maxItems: 1

      arm,trig-in-sigs:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        minItems: 1
        maxItems: 32
        description:
          List of CTI trigger in signal numbers in use by a trig-conns node.

      arm,trig-in-types:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        minItems: 1
        maxItems: 32
        description:
          List of constants representing the types for the CTI trigger in
          signals. Types in this array match to the corresponding signal in the
          arm,trig-in-sigs array. If the -types array is smaller, or omitted
          completely, then the types will default to GEN_IO.

      arm,trig-out-sigs:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        minItems: 1
        maxItems: 32
        description:
          List of CTI trigger out signal numbers in use by a trig-conns node.

      arm,trig-out-types:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        minItems: 1
        maxItems: 32
        description:
          List of constants representing the types for the CTI trigger out
          signals. Types in this array match to the corresponding signal
          in the arm,trig-out-sigs array. If the "-types" array is smaller,
          or omitted completely, then the types will default to GEN_IO.

      arm,trig-filters:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        minItems: 1
        maxItems: 32
        description:
          List of CTI trigger out signals that will be blocked from becoming
          active, unless filtering is disabled on the driver.

      arm,trig-conn-name:
        $ref: /schemas/types.yaml#/definitions/string
        description:
          Defines a connection name that will be displayed, if the cpu or
          arm,cs-dev-assoc properties are not being used in this connection.
          Principle use for CTI that are connected to non-CoreSight devices, or
          external IO.

    anyOf:
      - required:
          - arm,trig-in-sigs
      - required:
          - arm,trig-out-sigs
    oneOf:
      - required:
          - arm,trig-conn-name
      - required:
          - cpu
      - required:
          - arm,cs-dev-assoc
    required:
      - reg

required:
  - compatible
  - reg
  - clocks
  - clock-names

if:
  properties:
    compatible:
      contains:
        const: arm,coresight-cti-v8-arch

then:
  required:
    - cpu

unevaluatedProperties: false

examples:
  # minimum CTI definition. DEVID register used to set number of triggers.
  - |
    cti@20020000 {
      compatible = "arm,coresight-cti", "arm,primecell";
      reg = <0x20020000 0x1000>;

      clocks = <&soc_smc50mhz>;
      clock-names = "apb_pclk";
    };
  #  v8 architecturally defined CTI - CPU + ETM connections generated by the
  #  driver according to the v8 architecture specification.
  - |
    cti@859000 {
      compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
                   "arm,primecell";
      reg = <0x859000 0x1000>;

      clocks = <&soc_smc50mhz>;
      clock-names = "apb_pclk";

      cpu = <&CPU1>;
      arm,cs-dev-assoc = <&etm1>;
    };
  # Implementation defined CTI - CPU + ETM connections explicitly defined..
  # Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h
  # #size-cells and #address-cells are required if trig-conns@ nodes present.
  - |
    #include <dt-bindings/arm/coresight-cti-dt.h>

    cti@858000 {
      compatible = "arm,coresight-cti", "arm,primecell";
      reg = <0x858000 0x1000>;

      clocks = <&soc_smc50mhz>;
      clock-names = "apb_pclk";

      arm,cti-ctm-id = <1>;

      #address-cells = <1>;
      #size-cells = <0>;

      trig-conns@0 {
            reg = <0>;
            arm,trig-in-sigs = <4 5 6 7>;
            arm,trig-in-types = <ETM_EXTOUT
                                 ETM_EXTOUT
                                 ETM_EXTOUT
                                 ETM_EXTOUT>;
            arm,trig-out-sigs = <4 5 6 7>;
            arm,trig-out-types = <ETM_EXTIN
                                  ETM_EXTIN
                                  ETM_EXTIN
                                  ETM_EXTIN>;
            arm,cs-dev-assoc = <&etm0>;
      };

      trig-conns@1 {
            reg = <1>;
            cpu = <&CPU0>;
            arm,trig-in-sigs = <0 1>;
            arm,trig-in-types = <PE_DBGTRIGGER
                                 PE_PMUIRQ>;
            arm,trig-out-sigs=<0 1 2 >;
            arm,trig-out-types = <PE_EDBGREQ
                                  PE_DBGRESTART
                                  PE_CTIIRQ>;

            arm,trig-filters = <0>;
      };
    };
  # Implementation defined CTI - non CoreSight component connections.
  - |
    cti@20110000 {
      compatible = "arm,coresight-cti", "arm,primecell";
      reg = <0x20110000 0x1000>;

      clocks = <&soc_smc50mhz>;
      clock-names = "apb_pclk";

      #address-cells = <1>;
      #size-cells = <0>;

      trig-conns@0 {
        reg = <0>;
        arm,trig-in-sigs=<0>;
        arm,trig-in-types=<GEN_INTREQ>;
        arm,trig-out-sigs=<0>;
        arm,trig-out-types=<GEN_HALTREQ>;
        arm,trig-conn-name = "sys_profiler";
      };

      trig-conns@1 {
        reg = <1>;
        arm,trig-out-sigs=<2 3>;
        arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
        arm,trig-conn-name = "watchdog";
      };

      trig-conns@2 {
        reg = <2>;
        arm,trig-in-sigs=<1 6>;
        arm,trig-in-types=<GEN_HALTREQ GEN_RESTARTREQ>;
        arm,trig-conn-name = "g_counter";
      };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-funnel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm CoreSight Programmable Trace Bus Funnel

maintainers:
  - Mathieu Poirier <mathieu.poirier@linaro.org>
  - Mike Leach <mike.leach@linaro.org>
  - Leo Yan <leo.yan@linaro.org>
  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |
  CoreSight components are compliant with the ARM CoreSight architecture
  specification and can be connected in various topologies to suit a particular
  SoCs tracing needs. These trace components can generally be classified as
  sinks, links and sources. Trace data produced by one or more sources flows
  through the intermediate links connecting the source to the currently selected
  sink.

  The Coresight funnel merges 2-8 trace sources into a single trace
  stream with programmable enable and priority of input ports.

# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
  properties:
    compatible:
      contains:
        const: arm,coresight-dynamic-funnel
  required:
    - compatible

allOf:
  - $ref: /schemas/arm/primecell.yaml#

properties:
  compatible:
    items:
      - const: arm,coresight-dynamic-funnel
      - const: arm,primecell

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: apb_pclk
      - const: atclk

  power-domains:
    maxItems: 1

  in-ports:
    $ref: /schemas/graph.yaml#/properties/ports

    patternProperties:
      '^port(@[0-7])?$':
        description: Input connections from CoreSight Trace bus
        $ref: /schemas/graph.yaml#/properties/port

  out-ports:
    $ref: /schemas/graph.yaml#/properties/ports
    additionalProperties: false

    properties:
      port:
        description: Output connection to CoreSight Trace bus
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - in-ports
  - out-ports

unevaluatedProperties: false

examples:
  - |
    funnel@20040000 {
        compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
        reg = <0x20040000 0x1000>;

        clocks = <&oscclk6a>;
        clock-names = "apb_pclk";
        out-ports {
            port {
                funnel_out_port0: endpoint {
                    remote-endpoint = <&replicator_in_port0>;
                };
            };
        };

        in-ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                funnel_in_port0: endpoint {
                    remote-endpoint = <&ptm0_out_port>;
                };
            };

            port@1 {
                reg = <1>;
                funnel_in_port1: endpoint {
                    remote-endpoint = <&ptm1_out_port>;
                };
            };

            port@2 {
                reg = <2>;
                funnel_in_port2: endpoint {
                    remote-endpoint = <&etm0_out_port>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dynamic-replicator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm Coresight Programmable Trace Bus Replicator

maintainers:
  - Mathieu Poirier <mathieu.poirier@linaro.org>
  - Mike Leach <mike.leach@linaro.org>
  - Leo Yan <leo.yan@linaro.org>
  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |
  CoreSight components are compliant with the ARM CoreSight architecture
  specification and can be connected in various topologies to suit a particular
  SoCs tracing needs. These trace components can generally be classified as
  sinks, links and sources. Trace data produced by one or more sources flows
  through the intermediate links connecting the source to the currently selected
  sink.

  The Coresight replicator splits a single trace stream into two trace streams
  for systems that have more than one trace sink component.

# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
  properties:
    compatible:
      contains:
        const: arm,coresight-dynamic-replicator
  required:
    - compatible

allOf:
  - $ref: /schemas/arm/primecell.yaml#

properties:
  compatible:
    items:
      - const: arm,coresight-dynamic-replicator
      - const: arm,primecell

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: apb_pclk
      - const: atclk

  power-domains:
    maxItems: 1

  qcom,replicator-loses-context:
    type: boolean
    description:
      Indicates that the replicator will lose register context when AMBA clock
      is removed which is observed in some replicator designs.

  in-ports:
    $ref: /schemas/graph.yaml#/properties/ports
    additionalProperties: false

    properties:
      port:
        description: Input connection from CoreSight Trace bus
        $ref: /schemas/graph.yaml#/properties/port

  out-ports:
    $ref: /schemas/graph.yaml#/properties/ports

    patternProperties:
      '^port(@[01])?$':
        description: Output connections to CoreSight Trace bus
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - in-ports
  - out-ports

unevaluatedProperties: false

examples:
  - |
    replicator@20120000 {
        compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
        reg = <0x20120000 0x1000>;

        clocks = <&soc_smc50mhz>;
        clock-names = "apb_pclk";

        out-ports {
            #address-cells = <1>;
            #size-cells = <0>;

            /* replicator output ports */
            port@0 {
                reg = <0>;
                replicator_out_port0: endpoint {
                    remote-endpoint = <&tpiu_in_port>;
                };
            };

            port@1 {
                reg = <1>;
                replicator_out_port1: endpoint {
                    remote-endpoint = <&etr_in_port>;
                };
            };
        };
        in-ports {
            port {
                replicator_in_port0: endpoint {
                    remote-endpoint = <&csys2_funnel_out_port>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-etb10.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm CoreSight Embedded Trace Buffer

maintainers:
  - Mathieu Poirier <mathieu.poirier@linaro.org>
  - Mike Leach <mike.leach@linaro.org>
  - Leo Yan <leo.yan@linaro.org>
  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |
  CoreSight components are compliant with the ARM CoreSight architecture
  specification and can be connected in various topologies to suit a particular
  SoCs tracing needs. These trace components can generally be classified as
  sinks, links and sources. Trace data produced by one or more sources flows
  through the intermediate links connecting the source to the currently selected
  sink.

  The CoreSight Embedded Trace Buffer stores traces in a dedicated SRAM that is
  used as a circular buffer.

# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
  properties:
    compatible:
      contains:
        const: arm,coresight-etb10
  required:
    - compatible

allOf:
  - $ref: /schemas/arm/primecell.yaml#

properties:
  compatible:
    items:
      - const: arm,coresight-etb10
      - const: arm,primecell

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: apb_pclk
      - const: atclk

  power-domains:
    maxItems: 1

  in-ports:
    $ref: /schemas/graph.yaml#/properties/ports
    additionalProperties: false

    properties:
      port:
        description: Input connection from CoreSight Trace bus.
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - in-ports

unevaluatedProperties: false

examples:
  - |
    etb@20010000 {
        compatible = "arm,coresight-etb10", "arm,primecell";
        reg = <0x20010000 0x1000>;

        clocks = <&oscclk6a>;
        clock-names = "apb_pclk";
        in-ports {
            port {
                etb_in_port: endpoint {
                    remote-endpoint = <&replicator_out_port0>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-etm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm CoreSight Embedded Trace MacroCell

maintainers:
  - Mathieu Poirier <mathieu.poirier@linaro.org>
  - Mike Leach <mike.leach@linaro.org>
  - Leo Yan <leo.yan@linaro.org>
  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |
  CoreSight components are compliant with the ARM CoreSight architecture
  specification and can be connected in various topologies to suit a particular
  SoCs tracing needs. These trace components can generally be classified as
  sinks, links and sources. Trace data produced by one or more sources flows
  through the intermediate links connecting the source to the currently selected
  sink.

  The Embedded Trace Macrocell (ETM) is a real-time trace module providing
  instruction and data tracing of a processor.

select:
  properties:
    compatible:
      contains:
        enum:
          - arm,coresight-etm3x
          - arm,coresight-etm4x
          - arm,coresight-etm4x-sysreg
  required:
    - compatible

allOf:
  - if:
      not:
        properties:
          compatible:
            contains:
              const: arm,coresight-etm4x-sysreg
    then:
      $ref: /schemas/arm/primecell.yaml#
      required:
        - reg

properties:
  compatible:
    oneOf:
      - description:
          Embedded Trace Macrocell with memory mapped access.
        items:
          - enum:
              - arm,coresight-etm3x
              - arm,coresight-etm4x
          - const: arm,primecell
      - description:
          Embedded Trace Macrocell (version 4.x), with system register access only
        const: arm,coresight-etm4x-sysreg

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: apb_pclk
      - const: atclk

  power-domains:
    maxItems: 1

  arm,coresight-loses-context-with-cpu:
    type: boolean
    description:
      Indicates that the hardware will lose register context on CPU power down
      (e.g. CPUIdle). An example of where this may be needed are systems which
      contain a coresight component and CPU in the same power domain. When the
      CPU powers down the coresight component also powers down and loses its
      context.

  arm,cp14:
    type: boolean
    description:
      Must be present if the system accesses ETM/PTM management registers via
      co-processor 14.

  qcom,skip-power-up:
    type: boolean
    description:
      Indicates that an implementation can skip powering up the trace unit.
      TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
      since ETMs are in the same power domain as their CPU cores. This property
      is required to identify such systems with hardware errata where the CPU
      watchdog counter is stopped when TRCPDCR.PU is set.

  cpu:
    description:
      phandle to the cpu this ETM is bound to.
    $ref: /schemas/types.yaml#/definitions/phandle

  out-ports:
    $ref: /schemas/graph.yaml#/properties/ports
    additionalProperties: false

    properties:
      port:
        description: Output connection from the ETM to CoreSight Trace bus.
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - clocks
  - clock-names
  - cpu
  - out-ports

unevaluatedProperties: false

examples:
  - |
    ptm@2201c000 {
        compatible = "arm,coresight-etm3x", "arm,primecell";
        reg = <0x2201c000 0x1000>;

        cpu = <&cpu0>;
        clocks = <&oscclk6a>;
        clock-names = "apb_pclk";
        out-ports {
            port {
                ptm0_out_port: endpoint {
                    remote-endpoint = <&funnel_in_port0>;
                };
            };
        };
    };

    ptm@2201d000 {
        compatible = "arm,coresight-etm3x", "arm,primecell";
        reg = <0x2201d000 0x1000>;

        cpu = <&cpu1>;
        clocks = <&oscclk6a>;
        clock-names = "apb_pclk";
        out-ports {
            port {
                ptm1_out_port: endpoint {
                    remote-endpoint = <&funnel_in_port1>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm CoreSight Static Trace Bus Funnel

maintainers:
  - Mathieu Poirier <mathieu.poirier@linaro.org>
  - Mike Leach <mike.leach@linaro.org>
  - Leo Yan <leo.yan@linaro.org>
  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |
  CoreSight components are compliant with the ARM CoreSight architecture
  specification and can be connected in various topologies to suit a particular
  SoCs tracing needs. These trace components can generally be classified as
  sinks, links and sources. Trace data produced by one or more sources flows
  through the intermediate links connecting the source to the currently selected
  sink.

  The Coresight static funnel merges 2-8 trace sources into a single trace
  stream.

properties:
  compatible:
    const: arm,coresight-static-funnel

  power-domains:
    maxItems: 1

  in-ports:
    $ref: /schemas/graph.yaml#/properties/ports

    patternProperties:
      '^port@[0-7]$':
        description: Input connections from CoreSight Trace bus
        $ref: /schemas/graph.yaml#/properties/port

  out-ports:
    $ref: /schemas/graph.yaml#/properties/ports
    additionalProperties: false

    properties:
      port:
        description: Output connection to CoreSight Trace bus
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - in-ports
  - out-ports

additionalProperties: false

examples:
  - |
    funnel {
        /*
         * non-configurable replicators don't show up on the
         * AMBA bus.  As such no need to add "arm,primecell".
         */
        compatible = "arm,coresight-static-funnel";

        out-ports {
            port {
                combo_funnel_out: endpoint {
                    remote-endpoint = <&top_funnel_in>;
                };
            };
        };

        in-ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                combo_funnel_in0: endpoint {
                    remote-endpoint = <&cluster0_etf_out>;
                };
            };

            port@1 {
                reg = <1>;
                combo_funnel_in1: endpoint {
                    remote-endpoint = <&cluster1_etf_out>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm CoreSight Static Trace Bus Replicator

maintainers:
  - Mathieu Poirier <mathieu.poirier@linaro.org>
  - Mike Leach <mike.leach@linaro.org>
  - Leo Yan <leo.yan@linaro.org>
  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |
  CoreSight components are compliant with the ARM CoreSight architecture
  specification and can be connected in various topologies to suit a particular
  SoCs tracing needs. These trace components can generally be classified as
  sinks, links and sources. Trace data produced by one or more sources flows
  through the intermediate links connecting the source to the currently selected
  sink.

  The Coresight replicator splits a single trace stream into two trace streams
  for systems that have more than one trace sink component.

properties:
  compatible:
    const: arm,coresight-static-replicator

  power-domains:
    maxItems: 1

  in-ports:
    $ref: /schemas/graph.yaml#/properties/ports
    additionalProperties: false

    properties:
      port:
        description: Input connection from CoreSight Trace bus
        $ref: /schemas/graph.yaml#/properties/port

  out-ports:
    $ref: /schemas/graph.yaml#/properties/ports

    patternProperties:
      '^port@[01]$':
        description: Output connections to CoreSight Trace bus
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - in-ports
  - out-ports

additionalProperties: false

examples:
  - |
    replicator {
        /*
         * non-configurable replicators don't show up on the
         * AMBA bus.  As such no need to add "arm,primecell".
         */
        compatible = "arm,coresight-static-replicator";

        out-ports {
            #address-cells = <1>;
            #size-cells = <0>;

            /* replicator output ports */
            port@0 {
                reg = <0>;
                replicator_out_port0: endpoint {
                    remote-endpoint = <&etb_in_port>;
                };
            };

            port@1 {
                reg = <1>;
                replicator_out_port1: endpoint {
                    remote-endpoint = <&tpiu_in_port>;
                };
            };
        };

        in-ports {
            port {
                replicator_in_port0: endpoint {
                    remote-endpoint = <&funnel_out_port0>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm CoreSight System Trace MacroCell

maintainers:
  - Mathieu Poirier <mathieu.poirier@linaro.org>
  - Mike Leach <mike.leach@linaro.org>
  - Leo Yan <leo.yan@linaro.org>
  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |
  CoreSight components are compliant with the ARM CoreSight architecture
  specification and can be connected in various topologies to suit a particular
  SoCs tracing needs. These trace components can generally be classified as
  sinks, links and sources. Trace data produced by one or more sources flows
  through the intermediate links connecting the source to the currently selected
  sink.

  The STM is a trace source that is integrated into a CoreSight system, designed
  primarily for high-bandwidth trace of instrumentation embedded into software.
  This instrumentation is made up of memory-mapped writes to the STM Advanced
  eXtensible Interface (AXI) slave, which carry information about the behavior
  of the software.

select:
  properties:
    compatible:
      contains:
        const: arm,coresight-stm
  required:
    - compatible

allOf:
  - $ref: /schemas/arm/primecell.yaml#

properties:
  compatible:
    items:
      - const: arm,coresight-stm
      - const: arm,primecell

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: stm-base
      - const: stm-stimulus-base

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: apb_pclk
      - const: atclk

  power-domains:
    maxItems: 1

  out-ports:
    $ref: /schemas/graph.yaml#/properties/ports
    additionalProperties: false

    properties:
      port:
        description: Output connection to the CoreSight Trace bus.
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - out-ports

unevaluatedProperties: false

examples:
  - |
    stm@20100000 {
        compatible = "arm,coresight-stm", "arm,primecell";
        reg = <0x20100000 0x1000>,
              <0x28000000 0x180000>;
        reg-names = "stm-base", "stm-stimulus-base";

        clocks = <&soc_smc50mhz>;
        clock-names = "apb_pclk";
        out-ports {
            port {
                stm_out_port: endpoint {
                    remote-endpoint = <&main_funnel_in_port2>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm CoreSight Trace Memory Controller

maintainers:
  - Mathieu Poirier <mathieu.poirier@linaro.org>
  - Mike Leach <mike.leach@linaro.org>
  - Leo Yan <leo.yan@linaro.org>
  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |
  CoreSight components are compliant with the ARM CoreSight architecture
  specification and can be connected in various topologies to suit a particular
  SoCs tracing needs. These trace components can generally be classified as
  sinks, links and sources. Trace data produced by one or more sources flows
  through the intermediate links connecting the source to the currently selected
  sink.

  Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
  FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
  mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.

# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
  properties:
    compatible:
      contains:
        const: arm,coresight-tmc
  required:
    - compatible

allOf:
  - $ref: /schemas/arm/primecell.yaml#

properties:
  compatible:
    items:
      - const: arm,coresight-tmc
      - const: arm,primecell

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: apb_pclk
      - const: atclk

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

  arm,buffer-size:
    $ref: /schemas/types.yaml#/definitions/uint32
    deprecated: true
    description:
      Size of contiguous buffer space for TMC ETR (embedded trace router). The
      buffer size can be configured dynamically via buffer_size property in
      sysfs instead.

  arm,scatter-gather:
    type: boolean
    description:
      Indicates that the TMC-ETR can safely use the SG mode on this system.

  arm,max-burst-size:
    description:
      The maximum burst size initiated by TMC on the AXI master interface. The
      burst size can be in the range [0..15], the setting supports one data
      transfer per burst up to a maximum of 16 data transfers per burst.
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15

  in-ports:
    $ref: /schemas/graph.yaml#/properties/ports
    additionalProperties: false

    properties:
      port:
        description: Input connection from the CoreSight Trace bus.
        $ref: /schemas/graph.yaml#/properties/port

  out-ports:
    $ref: /schemas/graph.yaml#/properties/ports
    additionalProperties: false

    properties:
      port:
        description: AXI or ATB Master output connection. Used for ETR
          and ETF configurations.
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - in-ports

unevaluatedProperties: false

examples:
  - |
    etr@20070000 {
        compatible = "arm,coresight-tmc", "arm,primecell";
        reg = <0x20070000 0x1000>;

        clocks = <&oscclk6a>;
        clock-names = "apb_pclk";
        in-ports {
            port {
                etr_in_port: endpoint {
                    remote-endpoint = <&replicator2_out_port0>;
                };
            };
        };

        out-ports {
            port {
                etr_out_port: endpoint {
                    remote-endpoint = <&catu_in_port>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm CoreSight Trace Port Interface Unit

maintainers:
  - Mathieu Poirier <mathieu.poirier@linaro.org>
  - Mike Leach <mike.leach@linaro.org>
  - Leo Yan <leo.yan@linaro.org>
  - Suzuki K Poulose <suzuki.poulose@arm.com>

description: |
  CoreSight components are compliant with the ARM CoreSight architecture
  specification and can be connected in various topologies to suit a particular
  SoCs tracing needs. These trace components can generally be classified as
  sinks, links and sources. Trace data produced by one or more sources flows
  through the intermediate links connecting the source to the currently selected
  sink.

  The CoreSight Trace Port Interface Unit captures trace data from the trace bus
  and outputs it to an external trace port.

# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
  properties:
    compatible:
      contains:
        const: arm,coresight-tpiu
  required:
    - compatible

allOf:
  - $ref: /schemas/arm/primecell.yaml#

properties:
  compatible:
    items:
      - const: arm,coresight-tpiu
      - const: arm,primecell

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: apb_pclk
      - const: atclk

  power-domains:
    maxItems: 1

  in-ports:
    $ref: /schemas/graph.yaml#/properties/ports
    additionalProperties: false

    properties:
      port:
        description: Input connection from the CoreSight Trace bus.
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - in-ports

unevaluatedProperties: false

examples:
  - |
    tpiu@e3c05000 {
        compatible = "arm,coresight-tpiu", "arm,primecell";
        reg = <0xe3c05000 0x1000>;

        clocks = <&clk_375m>;
        clock-names = "apb_pclk";
        in-ports {
            port {
                tpiu_in_port: endpoint {
                    remote-endpoint = <&funnel4_out_port0>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Corstone1000

maintainers:
  - Vishnu Banavath <vishnu.banavath@arm.com>
  - Rui Miguel Silva <rui.silva@linaro.org>

description: |+
  ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
  provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
  processors.

  Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
  systems for M-Class (or other) processors for adding sensors, connectivity,
  video, audio and machine learning at the edge System and security IPs to build
  a secure SoC for a range of rich IoT applications, for example gateways, smart
  cameras and embedded systems.

  Integrated Secure Enclave providing hardware Root of Trust and supporting
  seamless integration of the optional CryptoCell™-312 cryptographic
  accelerator.

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA
          implementation of the Corstone1000 in the MPS3 prototyping board. See
          ARM document DAI0550.
        items:
          - const: arm,corstone1000-mps3
      - description: Corstone1000 FVP is the Fixed Virtual Platform
          implementation of this system. See ARM ecosystems FVP's.
        items:
          - const: arm,corstone1000-fvp

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# Copyright 2021, Arm Ltd
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: ARM Embedded Trace Extensions

maintainers:
  - Suzuki K Poulose <suzuki.poulose@arm.com>
  - Mathieu Poirier <mathieu.poirier@linaro.org>

description: |
  Arm Embedded Trace Extension(ETE) is a per CPU trace component that
  allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
  architecture and has extended support for future architecture changes.
  The trace generated by the ETE could be stored via legacy CoreSight
  components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
  Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
  legacy CoreSight components, a node must be listed per instance, along
  with any optional connection graph as per the coresight bindings.

properties:
  $nodename:
    pattern: "^ete([0-9a-f]+)$"
  compatible:
    items:
      - const: arm,embedded-trace-extension

  cpu:
    description: |
      Handle to the cpu this ETE is bound to.
    $ref: /schemas/types.yaml#/definitions/phandle

  power-domains:
    maxItems: 1

  out-ports:
    description: |
      Output connections from the ETE to legacy CoreSight trace bus.
    $ref: /schemas/graph.yaml#/properties/ports
    properties:
      port:
        description: Output connection from the ETE to legacy CoreSight Trace bus.
        $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - cpu

additionalProperties: false

examples:

# An ETE node without legacy CoreSight connections
  - |
    ete0 {
      compatible = "arm,embedded-trace-extension";
      cpu = <&cpu_0>;
    };
# An ETE node with legacy CoreSight connections
  - |
   ete1 {
      compatible = "arm,embedded-trace-extension";
      cpu = <&cpu_1>;

      out-ports {        /* legacy coresight connection */
         port {
             ete1_out_port: endpoint {
                remote-endpoint = <&funnel_in_port0>;
             };
         };
      };
   };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,integrator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Integrator Boards

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |+
  These were the first ARM platforms officially supported by ARM Ltd.
  They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
  so the system is modular and can host a variety of CPU tiles called
  "core tiles" and referred to in the device tree as "core modules".

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: ARM Integrator Application Platform, this board has a PCI
          host and several PCI slots, as well as a number of slots for logical
          expansion modules, it is referred to as an "ASIC Development
          Motherboard" and is extended with custom FPGA and is intended for
          rapid prototyping. See ARM DUI 0098B. This board can physically come
          pre-packaged in a PC Tower form factor called Integrator/PP1 or a
          special metal fixture called Integrator/PP2, see ARM DUI 0169A.
        items:
          - const: arm,integrator-ap
      - description: ARM Integrator Compact Platform (HBI-0086), this board has
          a compact form factor and mainly consists of the bare minimum
          peripherals to make use of the core module. See ARM DUI 0159B.
        items:
          - const: arm,integrator-cp
      - description: ARM Integrator Standard Development Board (SDB) Platform,
          this board is a PCI-based board conforming to the Microsoft SDB
          (HARP) specification. See ARM DUI 0099A.
        items:
          - const: arm,integrator-sp

  core-module@10000000:
    type: object
    description: the root node in the Integrator platforms must contain
      a core module child node. They are always at physical address
      0x10000000 in all the Integrator variants.
    properties:
      compatible:
        items:
          - const: arm,core-module-integrator
          - const: syscon
          - const: simple-mfd
      reg:
        maxItems: 1

    required:
      - compatible
      - reg

patternProperties:
  "^syscon@[0-9a-f]+$":
    description: All Integrator boards must provide a system controller as a
      node in the root of the device tree.
    type: object
    properties:
      compatible:
        items:
          - enum:
              - arm,integrator-ap-syscon
              - arm,integrator-cp-syscon
              - arm,integrator-sp-syscon
          - const: syscon
      reg:
        maxItems: 1

    required:
      - compatible
      - reg

required:
  - compatible
  - core-module@10000000

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,realview.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM RealView Boards

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |+
  The ARM RealView series of reference designs were built to explore the ARM
  11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
  the earlier CPUs such as TrustZone and multicore (MPCore).

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: ARM RealView Emulation Baseboard (HBI-0140) was created
          as a generic platform to test different FPGA designs, and has
          pluggable CPU modules, see ARM DUI 0303E.
        items:
          - const: arm,realview-eb
      - description: ARM RealView Platform Baseboard for ARM1176JZF-S
          (HBI-0147) was created as a development board to test ARM TrustZone,
          CoreSight and Intelligent Energy Management (IEM) see ARM DUI 0425F.
        items:
          - const: arm,realview-pb1176
      - description: ARM RealView Platform Baseboard for ARM 11 MPCore
          (HBI-0159, HBI-0175 and HBI-0176) was created to showcase
          multiprocessing with ARM11 using MPCore using symmetric
          multiprocessing (SMP). See ARM DUI 0351E.
        items:
          - const: arm,realview-pb11mp
      - description: ARM RealView Platform Baseboard for Cortex-A8 (HBI-0178,
          HBI-0176 and HBI-0175) was the first reference platform for the
          Cortex CPU family, including a Cortex-A8 test chip.
        items:
          - const: arm,realview-pba8
      - description: ARM RealView Platform Baseboard Explore for Cortex-A9
          (HBI-0182 and HBI-0183) was the reference platform for the Cortex-A9
          CPU.
        items:
          - const: arm,realview-pbx

  soc:
    description: All RealView boards must provide a soc node in the root of the
      device tree, representing the System-on-Chip since these test chips are
      rather complex.
    type: object
    properties:
      compatible:
        oneOf:
          - items:
              - const: arm,realview-eb-soc
              - const: simple-bus
          - items:
              - const: arm,realview-pb1176-soc
              - const: simple-bus
          - items:
              - const: arm,realview-pb11mp-soc
              - const: simple-bus
          - items:
              - const: arm,realview-pba8-soc
              - const: simple-bus
          - items:
              - const: arm,realview-pbx-soc
              - const: simple-bus

    patternProperties:
      "^.*syscon@[0-9a-f]+$":
        type: object
        description: All RealView boards must provide a syscon system controller
          node inside the soc node.
        properties:
          compatible:
            oneOf:
              - items:
                  - const: arm,realview-eb11mp-revb-syscon
                  - const: arm,realview-eb-syscon
                  - const: syscon
                  - const: simple-mfd
              - items:
                  - const: arm,realview-eb11mp-revc-syscon
                  - const: arm,realview-eb-syscon
                  - const: syscon
                  - const: simple-mfd
              - items:
                  - const: arm,realview-eb-syscon
                  - const: syscon
                  - const: simple-mfd
              - items:
                  - const: arm,realview-pb1176-syscon
                  - const: syscon
                  - const: simple-mfd
              - items:
                  - const: arm,realview-pb11mp-syscon
                  - const: syscon
                  - const: simple-mfd
              - items:
                  - const: arm,realview-pba8-syscon
                  - const: syscon
                  - const: simple-mfd
              - items:
                  - const: arm,realview-pbx-syscon
                  - const: syscon
                  - const: simple-mfd

        required:
          - compatible
          - reg

    required:
      - compatible

required:
  - compatible
  - soc

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,scu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Snoop Control Unit (SCU)

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
  with a Snoop Control Unit. The register range is usually 256 (0x100)
  bytes.

  References:
    - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
      Revision r2p0
    - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
      Revision r0p1
    - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
      Manial Revision r2p0

properties:
  compatible:
    enum:
      - arm,cortex-a9-scu
      - arm,cortex-a5-scu
      - arm,arm11mp-scu

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    scu@a0410000 {
            compatible = "arm,cortex-a9-scu";
            reg = <0xa0410000 0x100>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# Copyright 2021, Arm Ltd
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: ARM Trace Buffer Extensions

maintainers:
  - Anshuman Khandual <anshuman.khandual@arm.com>

description: |
  Arm Trace Buffer Extension (TRBE) is a per CPU component
  for storing trace generated on the CPU to memory. It is
  accessed via CPU system registers. The software can verify
  if it is permitted to use the component by checking the
  TRBIDR register.

properties:
  $nodename:
    const: "trbe"
  compatible:
    items:
      - const: arm,trace-buffer-extension

  interrupts:
    description: |
       Exactly 1 PPI must be listed. For heterogeneous systems where
       TRBE is only supported on a subset of the CPUs, please consult
       the arm,gic-v3 binding for details on describing a PPI partition.
    maxItems: 1

required:
  - compatible
  - interrupts

additionalProperties: false

examples:

  - |
   #include <dt-bindings/interrupt-controller/arm-gic.h>

   trbe {
     compatible = "arm,trace-buffer-extension";
     interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
   };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,versatile-sysreg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm Versatile system registers

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description:
  This is a system control registers block, providing multiple low level
  platform functions like board detection and identification, software
  interrupt generation, MMC and NOR Flash control, etc.

properties:
  compatible:
    items:
      - const: arm,versatile-sysreg
      - const: syscon
      - const: simple-mfd

  reg:
    maxItems: 1

  panel:
    type: object

required:
  - compatible
  - reg

additionalProperties: false
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,versatile.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Versatile Boards

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |+
  The ARM Versatile boards are two variants of ARM926EJ-S evaluation boards
  with various pluggable interface boards, in essence the Versatile PB version
  is a superset of the Versatile AB version.

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: The ARM Versatile Application Baseboard (HBI-0118) is an
          evaluation board specifically for the ARM926EJ-S. It can be connected
          to an IB1 interface board for a touchscreen-type use case or an IB2
          for a candybar phone-type use case. See ARM DUI 0225D.
        items:
          - const: arm,versatile-ab
      - description: The ARM Versatile Platform Baseboard (HBI-0117) is an
          extension of the Versatile Application Baseboard that includes a
          PCI host controller. Like the sibling board, it is done specifically
          for ARM926EJ-S. See ARM DUI 0224B.
        items:
          - const: arm,versatile-pb

  core-module@10000000:
    type: object
    description: the root node in the Versatile platforms must contain
      a core module child node. They are always at physical address
      0x10000000 in all the Versatile variants.
    properties:
      compatible:
        items:
          - const: arm,core-module-versatile
          - const: syscon
          - const: simple-mfd
      reg:
        maxItems: 1

    required:
      - compatible
      - reg

patternProperties:
  "^syscon@[0-9a-f]+$":
    type: object
    description: When fitted with the IB2 Interface Board, the Versatile
      AB will present an optional system controller node which controls the
      extra peripherals on the interface board.
    properties:
      compatible:
        contains:
          const: arm,versatile-ib2-syscon
    required:
      - compatible
      - reg

required:
  - compatible
  - core-module@10000000

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Versatile Express and Juno Boards

maintainers:
  - Sudeep Holla <sudeep.holla@arm.com>
  - Linus Walleij <linus.walleij@linaro.org>

description: |+
  ARM's Versatile Express platform were built as reference designs for exploring
  multicore Cortex-A class systems. The Versatile Express family contains both
  32 bit (Aarch32) and 64 bit (Aarch64) systems.

  The board consist of a motherboard and one or more daughterboards (tiles). The
  motherboard provides a set of peripherals. Processor and RAM "live" on the
  tiles.

  The motherboard and each core tile should be described by a separate Device
  Tree source file, with the tile's description including the motherboard file
  using an include directive. As the motherboard can be initialized in one of
  two different configurations ("memory maps"), care must be taken to include
  the correct one.

  When a new generation of boards were introduced under the name "Juno", these
  shared to many common characteristics with the Versatile Express that the
  "arm,vexpress" compatible was retained in the root node, and these are
  included in this binding schema as well.

  The root node indicates the CPU SoC on the core tile, and this
  is a daughterboard to the main motherboard. The name used in the compatible
  string shall match the name given in the core tile's technical reference
  manual, followed by "arm,vexpress" as an additional compatible value. If
  further subvariants are released of the core tile, even more fine-granular
  compatible strings with up to three compatible strings are used.

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
          in MPCore configuration in a test chip on the core tile. See ARM
          DUI 0448I. This was the first Versatile Express platform.
        items:
          - const: arm,vexpress,v2p-ca9
          - const: arm,vexpress
      - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
          in a test chip on the core tile. It is intended to evaluate NEON, FPU
          and Jazelle support in the Cortex A5 family. See ARM DUI 0541C.
        items:
          - const: arm,vexpress,v2p-ca5s
          - const: arm,vexpress
      - description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU
          cores in a MPCore configuration in a test chip on the core tile. See
          ARM DUI 0604F.
        items:
          - const: arm,vexpress,v2p-ca15
          - const: arm,vexpress
      - description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex
          A15 CPU cores in a test chip on the core tile. This is the first test
          chip called "TC1".
        items:
          - const: arm,vexpress,v2p-ca15,tc1
          - const: arm,vexpress,v2p-ca15
          - const: arm,vexpress
      - description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15
          CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
          in a test chip on the core tile. See ARM DDI 0503I.
        items:
          - const: arm,vexpress,v2p-ca15_a7
          - const: arm,vexpress
      - description: LogicTile Express 20MG (V2F-1XV7) has 2 Cortex A53 CPU
          cores in a test chip on the core tile. See ARM DDI 0498D.
        items:
          - const: arm,vexpress,v2f-1xv7,ca53x2
          - const: arm,vexpress,v2f-1xv7
          - const: arm,vexpress
      - description: Arm Versatile Express Juno "r0" (the first Juno board,
          V2M-Juno) was introduced as a vehicle for evaluating big.LITTLE on
          AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
          cores in a big.LITTLE configuration. It also features the MALI T624
          GPU. See ARM document 100113_0000_07_en.
        items:
          - const: arm,juno
          - const: arm,vexpress
      - description: Arm Versatile Express Juno r1 Development Platform
          (V2M-Juno r1) was introduced mainly aimed at development of PCIe
          based systems. Juno r1 also has support for AXI masters placed on
          the TLX connectors to join the coherency domain. Otherwise it is the
          same configuration as Juno r0. See ARM document 100122_0100_06_en.
        items:
          - const: arm,juno-r1
          - const: arm,juno
          - const: arm,vexpress
      - description: Arm Versatile Express Juno r2 Development Platform
          (V2M-Juno r2). It has the same feature set as Juno r0 and r1. See
          ARM document 100114_0200_04_en.
        items:
          - const: arm,juno-r2
          - const: arm,juno
          - const: arm,vexpress
      - description: Arm AEMv8a Versatile Express Real-Time System Model
          (VE RTSM) is a programmers view of the Versatile Express with Arm
          v8A hardware. See ARM DUI 0575D.
        items:
          - const: arm,rtsm_ve,aemv8a
          - const: arm,vexpress
      - description: Arm FVP (Fixed Virtual Platform) base model revision C
          See ARM Document 100964_1190_00_en.
        items:
          - const: arm,fvp-base-revc
          - const: arm,vexpress
      - description: Arm Foundation model for Aarch64
        items:
          - const: arm,foundation-aarch64
          - const: arm,vexpress

  arm,vexpress,position:
    description: When daughterboards are stacked on one site, their position
      in the stack be be described this attribute.
    $ref: '/schemas/types.yaml#/definitions/uint32'
    minimum: 0
    maximum: 3

  arm,vexpress,dcc:
    description: When describing tiles consisting of more than one DCC, its
      number can be specified with this attribute.
    $ref: '/schemas/types.yaml#/definitions/uint32'
    minimum: 0
    maximum: 3

patternProperties:
  "^bus@[0-9a-f]+$":
    description: Static Memory Bus (SMB) node, if this exists it describes
      the connection between the motherboard and any tiles. Sometimes the
      compatible is placed directly under this node, sometimes it is placed
      in a subnode named "motherboard-bus". Sometimes the compatible includes
      "arm,vexpress,v2?-p1" sometimes (on software models) is is just
      "simple-bus". If the compatible is placed in the "motherboard-bus" node,
      it is stricter and always has two compatibles.
    type: object
    $ref: '/schemas/simple-bus.yaml'

    properties:
      compatible:
        oneOf:
          - items:
              - enum:
                  - arm,vexpress,v2m-p1
                  - arm,vexpress,v2p-p1
              - const: simple-bus
          - const: simple-bus

    patternProperties:
      '^motherboard-bus@':
        type: object
        description: The motherboard description provides a single "motherboard"
          node using 2 address cells corresponding to the Static Memory Bus
          used between the motherboard and the tile. The first cell defines the
          Chip Select (CS) line number, the second cell address offset within
          the CS. All interrupt lines between the motherboard and the tile
          are active high and are described using single cell.
        properties:
          "#address-cells":
            const: 2
          "#size-cells":
            const: 1
          ranges: true

          compatible:
            items:
              - enum:
                  - arm,vexpress,v2m-p1
                  - arm,vexpress,v2p-p1
              - const: simple-bus
          arm,v2m-memory-map:
            description: This describes the memory map type.
            $ref: '/schemas/types.yaml#/definitions/string'
            enum:
              - rs1
              - rs2

          arm,hbi:
            $ref: '/schemas/types.yaml#/definitions/uint32'
            description: This indicates the ARM HBI (Hardware Board ID), this is
              ARM's unique board model ID, visible on the PCB's silkscreen.

          arm,vexpress,site:
            description: As Versatile Express can be configured in number of physically
              different setups, the device tree should describe platform topology.
              For this reason the root node and main motherboard node must define this
              property, describing the physical location of the children nodes.
              0 means motherboard site, while 1 and 2 are daughterboard sites, and
              0xf means "sisterboard" which is the site containing the main CPU tile.
            $ref: '/schemas/types.yaml#/definitions/uint32'
            minimum: 0
            maximum: 15

        required:
          - compatible

        additionalProperties:
          type: object

    required:
      - compatible

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - arm,vexpress,v2p-ca9
              - arm,vexpress,v2p-ca5s
              - arm,vexpress,v2p-ca15
              - arm,vexpress,v2p-ca15_a7
              - arm,vexpress,v2f-1xv7,ca53x2
    then:
      required:
        - arm,hbi

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
# Copyright 2021 Joel Stanley, IBM Corp.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: ASPEED Secure Boot Controller

maintainers:
  - Joel Stanley <joel@jms.id.au>
  - Andrew Jeffery <andrew@aj.id.au>

description: |
  The ASPEED SoCs have a register bank for interacting with the secure boot
  controller.

properties:
  compatible:
    items:
      - const: aspeed,ast2600-sbc

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    sbc: secure-boot-controller@1e6f2000 {
            compatible = "aspeed,ast2600-sbc";
            reg = <0x1e6f2000 0x1000>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/aspeed/aspeed.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Aspeed SoC based boards

maintainers:
  - Joel Stanley <joel@jms.id.au>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: AST2400 based boards
        items:
          - enum:
              - delta,ahe50dc-bmc
              - facebook,galaxy100-bmc
              - facebook,wedge100-bmc
              - facebook,wedge40-bmc
              - microsoft,olympus-bmc
              - quanta,q71l-bmc
              - tyan,palmetto-bmc
              - yadro,vesnin-bmc
          - const: aspeed,ast2400

      - description: AST2500 based boards
        items:
          - enum:
              - amd,daytonax-bmc
              - amd,ethanolx-bmc
              - ampere,mtjade-bmc
              - aspeed,ast2500-evb
              - asrock,e3c246d4i-bmc
              - asrock,romed8hm3-bmc
              - bytedance,g220a-bmc
              - facebook,cmm-bmc
              - facebook,minipack-bmc
              - facebook,tiogapass-bmc
              - facebook,yamp-bmc
              - facebook,yosemitev2-bmc
              - facebook,wedge400-bmc
              - hxt,stardragon4800-rep2-bmc
              - ibm,mihawk-bmc
              - ibm,mowgli-bmc
              - ibm,romulus-bmc
              - ibm,swift-bmc
              - ibm,witherspoon-bmc
              - ingrasys,zaius-bmc
              - inspur,fp5280g2-bmc
              - inspur,nf5280m6-bmc
              - inspur,on5263m5-bmc
              - intel,s2600wf-bmc
              - inventec,lanyang-bmc
              - lenovo,hr630-bmc
              - lenovo,hr855xg2-bmc
              - portwell,neptune-bmc
              - qcom,centriq2400-rep-bmc
              - supermicro,x11spi-bmc
              - tyan,s7106-bmc
              - tyan,s8036-bmc
              - yadro,nicole-bmc
              - yadro,vegman-n110-bmc
              - yadro,vegman-rx20-bmc
              - yadro,vegman-sx20-bmc
          - const: aspeed,ast2500

      - description: AST2600 based boards
        items:
          - enum:
              - ampere,mtmitchell-bmc
              - aspeed,ast2600-evb
              - aspeed,ast2600-evb-a1
              - facebook,bletchley-bmc
              - facebook,cloudripper-bmc
              - facebook,elbert-bmc
              - facebook,fuji-bmc
              - ibm,everest-bmc
              - ibm,rainier-bmc
              - ibm,tacoma-bmc
              - inventec,transformer-bmc
              - jabil,rbp-bmc
              - qcom,dc-scm-v1-bmc
              - quanta,s6q-bmc
          - const: aspeed,ast2600

additionalProperties: true