code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2020-2021 TQ-Systems GmbH
 */

/dts-v1/;

#include "imx8mm-tqma8mqml.dtsi"
#include "mba8mx.dtsi"

/ {
	model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
	compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";

	aliases {
		eeprom0 = &eeprom3;
		mmc0 = &usdhc3;
		mmc1 = &usdhc2;
		mmc2 = &usdhc1;
		rtc0 = &pcf85063;
		rtc1 = &snvs_rtc;
	};

	reg_usdhc2_vmmc: regulator-vmmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
		off-on-delay-us = <12000>;
	};

	connector {
		compatible = "gpio-usb-b-connector", "usb-b-connector";
		type = "micro";
		label = "X19";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1_connector>;
		id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				usb_dr_connector: endpoint {
					remote-endpoint = <&usb1_drd_sw>;
				};
			};
		};
	};
};

&i2c1 {
	expander2: gpio@27 {
		compatible = "nxp,pca9555";
		reg = <0x27>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&reg_vcc_3v3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_expander>;
		interrupt-parent = <&gpio1>;
		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
};

&pcie_phy {
	clocks = <&pcie0_refclk>;
	status = "okay";
};

&pcie0 {
	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
		<&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
				<&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				<&clk IMX8MM_SYS_PLL2_250M>;
	status = "okay";
};

&sai3 {
	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
	clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
		<&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
		<&clk IMX8MM_AUDIO_PLL2_OUT>;
};

&tlv320aic3x04 {
	clock-names = "mclk";
	clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
};

&uart1 {
	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
};

&uart2 {
	assigned-clocks = <&clk IMX8MM_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	dr_mode = "otg";
	srp-disable;
	hnp-disable;
	adp-disable;
	power-active-high;
	over-current-active-low;
	usb-role-switch;
	status = "okay";

	port {
		usb1_drd_sw: endpoint {
			remote-endpoint = <&usb_dr_connector>;
		};
	};
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	vbus-supply = <&reg_hub_vbus>;
	status = "okay";
};

&iomuxc {
	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x00000006>,
			   <MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x00000006>,
			   <MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x00000006>,
			   <MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x00000006>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x00000006>,
			   <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x00000006>,
			   <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x00000006>,
			   <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x00000006>;
	};

	pinctrl_expander: expandergrp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x94>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x40000002>,
			   <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x40000002>,
			   <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x14>,
			   <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x14>,
			   <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x14>,
			   <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x14>,
			   <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x90>,
			   <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x90>,
			   <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x90>,
			   <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x90>,
			   <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x14>,
			   <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x90>,
			   <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x90>,
			   <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x14>;
	};

	pinctrl_gpiobutton: gpiobuttongrp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x84>,
			   <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x84>,
			   <MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x84>;
	};

	pinctrl_gpioled: gpioledgrp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x84>,
			   <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14		0x84>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x40000004>,
			   <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x40000004>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x40000004>,
			   <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x40000004>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x40000004>,
			   <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x40000004>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x40000004>,
			   <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x40000004>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT		0x14>;
	};

	pinctrl_pwm4: pwm4grp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT		0x14>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK		0x94>,
			   <MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0x94>,
			   <MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0x94>,
			   <MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0x94>,
			   <MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0x94>,
			   <MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0x94>,
			   <MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0x94>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX		0x16>,
			   <MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX		0x16>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x16>,
			   <MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x16>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x16>,
			   <MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x16>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x16>,
			   <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x16>;
	};

	pinctrl_usbotg1: usbotg1grp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR	0x84>,
			   <MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x84>;
	};

	pinctrl_usb1_connector: usb1-connectorgrp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x1c0>;
	};

	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
		fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x84>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2020-2021 TQ-Systems GmbH
 */

#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm.dtsi"

/ {
	model = "TQ-Systems GmbH i.MX8MM TQMa8MxML";
	compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm";

	memory@40000000 {
		device_type = "memory";
		/*  our minimum RAM config will be 1024 MiB */
		reg = <0x00000000 0x40000000 0 0x40000000>;
	};

	/* e-MMC IO, needed for HS modes */
	reg_vcc1v8: regulator-vcc1v8 {
		compatible = "regulator-fixed";
		regulator-name = "TQMA8MXML_VCC1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	/* identical to buck4_reg, but should never change */
	reg_vcc3v3: regulator-vcc3v3 {
		compatible = "regulator-fixed";
		regulator-name = "TQMA8MXML_VCC3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			/* 640 MiB */
			size = <0 0x28000000>;
			/*  1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
			alloc-ranges = <0 0x40000000 0 0x78000000>;
			linux,cma-default;
		};
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi>;
	status = "okay";

	flash0: flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <84000000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
	};
};

&gpu_2d {
	status = "okay";
};

&gpu_3d {
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	sensor0: temperature-sensor-eeprom@1b {
		compatible = "nxp,se97", "jedec,jc-42.4-temp";
		reg = <0x1b>;
	};

	pca9450: pmic@25 {
		compatible = "nxp,pca9450a";
		reg = <0x25>;

		/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
		pinctrl-0 = <&pinctrl_pmic>;
		pinctrl-names = "default";
		interrupt-parent = <&gpio1>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			/* V_0V85_SOC: 0.85 */
			buck1_reg: BUCK1 {
				regulator-name = "BUCK1";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <850000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			/* VDD_ARM */
			buck2_reg: BUCK2 {
				regulator-name = "BUCK2";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1000000>;
				regulator-boot-on;
				regulator-always-on;
				nxp,dvs-run-voltage = <950000>;
				nxp,dvs-standby-voltage = <850000>;
				regulator-ramp-delay = <3125>;
			};

			/* V_0V85_GPU / DRAM / VPU */
			buck3_reg: BUCK3 {
				regulator-name = "BUCK3";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <950000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <3125>;
			};

			/* VCC3V3 -> VMMC, ... must not be changed */
			buck4_reg: BUCK4 {
				regulator-name = "BUCK4";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
			buck5_reg: BUCK5 {
				regulator-name = "BUCK5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* V_1V1 -> RAM, ... must not be changed */
			buck6_reg: BUCK6 {
				regulator-name = "BUCK6";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* V_1V8_SNVS */
			ldo1_reg: LDO1 {
				regulator-name = "LDO1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* V_0V8_SNVS */
			ldo2_reg: LDO2 {
				regulator-name = "LDO2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <850000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* V_1V8_ANA */
			ldo3_reg: LDO3 {
				regulator-name = "LDO3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* V_0V9_MIPI */
			ldo4_reg: LDO4 {
				regulator-name = "LDO4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* VCC SD IO - switched using SD2 VSELECT */
			ldo5_reg: LDO5 {
				regulator-name = "LDO5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};

	pcf85063: rtc@51 {
		compatible = "nxp,pcf85063a";
		reg = <0x51>;
		quartz-load-femtofarads = <7000>;
	};

	eeprom1: eeprom@53 {
		compatible = "nxp,se97b", "atmel,24c02";
		read-only;
		reg = <0x53>;
		pagesize = <16>;
	};

	eeprom0: eeprom@57 {
		compatible = "atmel,24c64";
		reg = <0x57>;
		pagesize = <32>;
	};
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,clkreq-unsupported;
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	no-sd;
	no-sdio;
	vmmc-supply = <&reg_vcc3v3>;
	vqmmc-supply = <&reg_vcc1v8>;
	status = "okay";
};

/*
 * Attention:
 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.
 */
&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_flexspi: flexspigrp {
		fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x82>,
			   <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82>,
			   <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82>,
			   <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82>,
			   <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82>,
			   <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x40000004>,
			   <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x40000004>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14		0x40000004>,
			   <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15		0x40000004>;
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x94>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x84>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x1d4>,
			   <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d2>,
			   <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4>,
			   <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4>,
			   <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4>,
			   <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4>,
			   <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4>,
			   <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4>,
			   <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4>,
			   <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4>,
			   <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x84>,
			   /* option USDHC3_RESET_B not defined, only in RM */
			   <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x84>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x1d2>,
			   <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d2>,
			   <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4>,
			   <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4>,
			   <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4>,
			   <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4>,
			   <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4>,
			   <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4>,
			   <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4>,
			   <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4>,
			   <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x84>,
			   /* option USDHC3_RESET_B not defined, only in RM */
			   <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x84>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x1d6>,
			   <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d2>,
			   <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4>,
			   <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4>,
			   <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4>,
			   <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4>,
			   <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4>,
			   <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4>,
			   <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4>,
			   <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4>,
			   <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x84>,
			   /* option USDHC3_RESET_B not defined, only in RM */
			   <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x84>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x84>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
 */

/dts-v1/;

#include "imx8mm-var-som.dtsi"

/ {
	model = "Variscite VAR-SOM-MX8MM Symphony evaluation board";
	compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm";

	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>;
		regulator-name = "usb_otg2_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-back {
			label = "Back";
			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_BACK>;
		};

		key-home {
			label = "Home";
			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_HOME>;
		};

		key-menu {
			label = "Menu";
			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_MENU>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led {
			label = "Heartbeat";
			gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
		};
	};
};

&ethphy {
	reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pca9534: gpio@20 {
		compatible = "nxp,pca9534";
		reg = <0x20>;
		gpio-controller;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pca9534>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
		#gpio-cells = <2>;
		wakeup-source;

		/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
		usb3-sata-sel-hog {
			gpio-hog;
			gpios = <4 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "usb3_sata_sel";
		};

		som-vselect-hog {
			gpio-hog;
			gpios = <6 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "som_vselect";
		};

		enet-sel-hog {
			gpio-hog;
			gpios = <7 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "enet_sel";
		};
	};

	extcon_usbotg1: typec@3d {
		compatible = "nxp,ptn5150";
		reg = <0x3d>;
		interrupt-parent = <&gpio1>;
		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ptn5150>;
		status = "okay";
	};
};

&i2c3 {
	/* Capacitive touch controller */
	ft5x06_ts: touchscreen@38 {
		compatible = "edt,edt-ft5406";
		reg = <0x38>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_captouch>;
		interrupt-parent = <&gpio5>;
		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

		touchscreen-size-x = <800>;
		touchscreen-size-y = <480>;
		touchscreen-inverted-x;
		touchscreen-inverted-y;
	};

	rtc@68 {
		compatible = "dallas,ds1337";
		reg = <0x68>;
	};
};

/* Header */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* Header */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&usbotg1 {
	disable-over-current;
	extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
};

&usbotg2 {
	dr_mode = "host";
	vbus-supply = <&reg_usb_otg2_vbus>;
	srp-disable;
	hnp-disable;
	adp-disable;
	disable-over-current;
	/delete-property/ usb-role-switch;
	/*
	 * FIXME: having USB2 enabled hangs the boot just after:
	 * [    1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller
	 * [    1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1
	 * [    1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
	 * [    1.977203] hub 1-0:1.0: USB hub found
	 * [    1.980987] hub 1-0:1.0: 1 port detected
	 */
	status = "disabled";
};

&pinctrl_fec1 {
	fsl,pins = <
		MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
		MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
		MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
		MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
		MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
		MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
		MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
		MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
		MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
		MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
		MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
		MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
		MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
		MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
		/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
	>;
};

&iomuxc {
	pinctrl_captouch: captouchgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x16
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_pca9534: pca9534grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x16
		>;
	};

	pinctrl_ptn5150: ptn5150grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x16
		>;
	};

	pinctrl_reg_usb_otg2_vbus: regusbotg2vbusgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1		0x16
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
 */

#include "imx8mm.dtsi"

/ {
	model = "Variscite VAR-SOM-MX8MM module";
	compatible = "variscite,var-som-mx8mm", "fsl,imx8mm";

	chosen {
		stdout-path = &uart4;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	reg_eth_phy: regulator-eth-phy {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_eth_phy>;
		regulator-name = "eth_phy_pwr";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&A53_1 {
	cpu-supply = <&buck2_reg>;
};

&A53_2 {
	cpu-supply = <&buck2_reg>;
};

&A53_3 {
	cpu-supply = <&buck2_reg>;
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
		   <&gpio1  0 GPIO_ACTIVE_LOW>;
	/delete-property/ dmas;
	/delete-property/ dma-names;
	status = "okay";

	/* Resistive touch controller */
	touchscreen@0 {
		reg = <0>;
		compatible = "ti,ads7846";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_restouch>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;

		spi-max-frequency = <1500000>;
		pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;

		ti,x-min = /bits/ 16 <125>;
		touchscreen-size-x = <4008>;
		ti,y-min = /bits/ 16 <282>;
		touchscreen-size-y = <3864>;
		ti,x-plate-ohms = /bits/ 16 <180>;
		touchscreen-max-pressure = <255>;
		touchscreen-average-samples = <10>;
		ti,debounce-tol = /bits/ 16 <3>;
		ti,debounce-rep = /bits/ 16 <1>;
		ti,settle-delay-usec = /bits/ 16 <150>;
		ti,keep-vref-on;
		wakeup-source;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy>;
	phy-supply = <&reg_eth_phy>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy: ethernet-phy@4 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <4>;
			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			reset-deassert-us = <10000>;
		};
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio2>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		rohm,reset-snvs-powered;

		#clock-cells = <0>;
		clocks = <&osc_32k 0>;
		clock-output-names = "clk-32k-out";

		regulators {
			buck1_reg: BUCK1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			buck2_reg: BUCK2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <900000>;
			};

			buck3_reg: BUCK3 {
				regulator-name = "buck3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck4_reg: BUCK4 {
				regulator-name = "buck4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5_reg: BUCK5 {
				regulator-name = "buck5";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6_reg: BUCK6 {
				regulator-name = "buck6";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: LDO1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <1900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2_reg: LDO2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_reg: LDO3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4_reg: LDO4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo5_reg: LDO5 {
				regulator-compatible = "ldo5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			ldo6_reg: LDO6 {
				regulator-name = "ldo6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	/* TODO: configure audio, as of now just put a placeholder */
	wm8904: codec@1a {
		compatible = "wlf,wm8904";
		reg = <0x1a>;
		status = "disabled";
	};
};

&snvs_pwrkey {
	status = "okay";
};

/* Bluetooth */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	assigned-clocks = <&clk IMX8MM_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
	uart-has-rtscts;
	status = "okay";
};

/* Console */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	usb-role-switch;
	status = "okay";
};

&usbotg2 {
	dr_mode = "otg";
	usb-role-switch;
	status = "okay";
};

/* WIFI */
&usdhc1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <4>;
	non-removable;
	keep-power-in-suspend;
	status = "okay";

	brcmf: bcrmf@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
	};
};

/* SD */
&usdhc2 {
	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

/* eMMC */
&usdhc3 {
	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13
			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13
			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13
			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x13
			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x13
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_pmic: pmicirqgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x141
		>;
	};

	pinctrl_reg_eth_phy: regethphygrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9	0x41
		>;
	};

	pinctrl_restouch: restouchgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x1c0
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x140
			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x140
			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x140
			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0xc1
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2020 Gateworks Corporation
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/net/ti-dp83867.h>

/ {
	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-user-pb {
			label = "user_pb";
			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_0>;
		};

		key-user-pb1x {
			label = "user_pb1x";
			linux,code = <BTN_1>;
			interrupt-parent = <&gsc>;
			interrupts = <0>;
		};

		key-erased {
			label = "key_erased";
			linux,code = <BTN_2>;
			interrupt-parent = <&gsc>;
			interrupts = <1>;
		};

		key-eeprom-wp {
			label = "eeprom_wp";
			linux,code = <BTN_3>;
			interrupt-parent = <&gsc>;
			interrupts = <2>;
		};

		key-tamper {
			label = "tamper";
			linux,code = <BTN_4>;
			interrupt-parent = <&gsc>;
			interrupts = <5>;
		};

		switch-hold {
			label = "switch_hold";
			linux,code = <BTN_5>;
			interrupt-parent = <&gsc>;
			interrupts = <7>;
		};
	};
};

&A53_0 {
	cpu-supply = <&buck3_reg>;
};

&A53_1 {
	cpu-supply = <&buck3_reg>;
};

&A53_2 {
	cpu-supply = <&buck3_reg>;
};

&A53_3 {
	cpu-supply = <&buck3_reg>;
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		};
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	gsc: gsc@20 {
		compatible = "gw,gsc";
		reg = <0x20>;
		pinctrl-0 = <&pinctrl_gsc>;
		interrupt-parent = <&gpio2>;
		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		adc {
			compatible = "gw,gsc-adc";
			#address-cells = <1>;
			#size-cells = <0>;

			channel@6 {
				gw,mode = <0>;
				reg = <0x06>;
				label = "temp";
			};

			channel@8 {
				gw,mode = <1>;
				reg = <0x08>;
				label = "vdd_bat";
			};

			channel@16 {
				gw,mode = <4>;
				reg = <0x16>;
				label = "fan_tach";
			};

			channel@82 {
				gw,mode = <2>;
				reg = <0x82>;
				label = "vdd_vin";
				gw,voltage-divider-ohms = <22100 1000>;
			};

			channel@84 {
				gw,mode = <2>;
				reg = <0x84>;
				label = "vdd_adc1";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@86 {
				gw,mode = <2>;
				reg = <0x86>;
				label = "vdd_adc2";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@88 {
				gw,mode = <2>;
				reg = <0x88>;
				label = "vdd_dram";
			};

			channel@8c {
				gw,mode = <2>;
				reg = <0x8c>;
				label = "vdd_1p2";
			};

			channel@8e {
				gw,mode = <2>;
				reg = <0x8e>;
				label = "vdd_1p0";
			};

			channel@90 {
				gw,mode = <2>;
				reg = <0x90>;
				label = "vdd_2p5";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@92 {
				gw,mode = <2>;
				reg = <0x92>;
				label = "vdd_3p3";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@98 {
				gw,mode = <2>;
				reg = <0x98>;
				label = "vdd_0p95";
			};

			channel@9a {
				gw,mode = <2>;
				reg = <0x9a>;
				label = "vdd_1p8";
			};

			channel@a2 {
				gw,mode = <2>;
				reg = <0xa2>;
				label = "vdd_gsc";
				gw,voltage-divider-ohms = <10000 10000>;
			};
		};

		fan-controller@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "gw,gsc-fan";
			reg = <0x0a>;
		};
	};

	gpio: gpio@23 {
		compatible = "nxp,pca9555";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gsc>;
		interrupts = <4>;
	};

	eeprom@50 {
		compatible = "atmel,24c02";
		reg = <0x50>;
		pagesize = <16>;
	};

	eeprom@51 {
		compatible = "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
	};

	eeprom@52 {
		compatible = "atmel,24c02";
		reg = <0x52>;
		pagesize = <16>;
	};

	eeprom@53 {
		compatible = "atmel,24c02";
		reg = <0x53>;
		pagesize = <16>;
	};

	rtc@68 {
		compatible = "dallas,ds1672";
		reg = <0x68>;
	};

	pmic@69 {
		compatible = "mps,mp5416";
		reg = <0x69>;

		regulators {
			/* vdd_0p95: DRAM/GPU/VPU */
			buck1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1000000>;
				regulator-min-microamp = <3800000>;
				regulator-max-microamp = <6800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_soc */
			buck2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-min-microamp = <2200000>;
				regulator-max-microamp = <5200000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_arm */
			buck3_reg: buck3 {
				regulator-name = "buck3";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1000000>;
				regulator-min-microamp = <3800000>;
				regulator-max-microamp = <6800000>;
				regulator-always-on;
			};

			/* vdd_1p8 */
			buck4 {
				regulator-name = "buck4";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-min-microamp = <2200000>;
				regulator-max-microamp = <5200000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* nvcc_snvs_1p8 */
			ldo1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_snvs_0p8 */
			ldo2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_0p9 */
			ldo3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_1p8 */
			ldo4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	eeprom@52 {
		compatible = "atmel,24c32";
		reg = <0x52>;
		pagesize = <32>;
	};
};

/* console */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0			0x19
		>;
	};

	pinctrl_gsc: gscgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x159
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2020 Gateworks Corporation
 */

/dts-v1/;

#include "imx8mm.dtsi"
#include "imx8mm-venice-gw700x.dtsi"
#include "imx8mm-venice-gw71xx.dtsi"

/ {
	model = "Gateworks Venice GW71xx-0x i.MX8MM Development Kit";
	compatible = "gw,imx8mm-gw71xx-0x", "fsl,imx8mm";

	chosen {
		stdout-path = &uart2;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2020 Gateworks Corporation
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>

/ {
	aliases {
		usb0 = &usbotg1;
		usb1 = &usbotg2;
	};

	led-controller {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led-0 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};

		led-1 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pps {
		compatible = "pps-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pps>;
		gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};

	reg_usb_otg1_vbus: regulator-usb-otg1 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb1_en>;
		compatible = "regulator-fixed";
		regulator-name = "usb_otg1_vbus";
		gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};
};

/* off-board header */
&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi2>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&gpio1 {
	gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0",
		"", "dio1", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio4 {
	gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	accelerometer@19 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_accel>;
		compatible = "st,lis2de12";
		reg = <0x19>;
		st,drdy-int-pin = <1>;
		interrupt-parent = <&gpio4>;
		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "INT1";
	};
};

/* off-board header */
&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,clkreq-unsupported;
	clocks = <&pcie0_refclk>;
	clock-names = "ref";
	status = "okay";
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_250M>;
	status = "okay";
};

/* GPS */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* off-board header */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	over-current-active-low;
	vbus-supply = <&reg_usb_otg1_vbus>;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* PLUG_TEST */
			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* PCI_USBSEL */
			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000041 /* PCIE_WDIS# */
			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIO0 */
			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x40000041 /* DIO1 */
			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3	0x40000041 /* DIO2 */
			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4	0x40000041 /* DIO2 */
		>;
	};

	pinctrl_accel: accelgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x159
		>;
	};

	pinctrl_gpio_leds: gpioledgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x19
			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x19
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x41
		>;
	};

	pinctrl_pps: ppsgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x41
		>;
	};

	pinctrl_reg_usb1_en: regusb1grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x41
			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x141
			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x41
		>;
	};

	pinctrl_spi2: spi2grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6
			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Gateworks Corporation
 */

#include <dt-bindings/gpio/gpio.h>

#include "imx8mm-pinfunc.h"

/dts-v1/;
/plugin/;

&{/} {
	compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";

	reg_cam: regulator-cam {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_cam>;
		compatible = "regulator-fixed";
		regulator-name = "reg_cam";
		gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	cam24m: cam24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "cam24m";
	};
};

&csi {
	status = "okay";
};

&i2c3 {
	#address-cells = <1>;
	#size-cells = <0>;

	imx219: sensor@10 {
		compatible = "sony,imx219";
		reg = <0x10>;
		clocks = <&cam24m>;
		VDIG-supply = <&reg_cam>;

		port {
			/* MIPI CSI-2 bus endpoint */
			imx219_to_mipi_csi2: endpoint {
				remote-endpoint = <&imx8mm_mipi_csi_in>;
				clock-lanes = <0>;
				data-lanes = <1 2>;
				link-frequencies = /bits/ 64 <456000000>;
			};
		};
	};
};

&mipi_csi {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;

			imx8mm_mipi_csi_in: endpoint {
				remote-endpoint = <&imx219_to_mipi_csi2>;
				data-lanes = <1 2>;
			};
		};

		port@1 {
			reg = <1>;

			imx8mm_mipi_csi_out: endpoint {
				remote-endpoint = <&csi_in>;
			};
		};
	};
};

&iomuxc {
	pinctrl_reg_cam: regcamgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1	0x41
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Gateworks Corporation
 *
 * GW72xx RS232 with RTS/CTS hardware flow control:
 *  - GPIO4_0 rs485_en needs to be driven low (in-active)
 *  - UART4_TX becomes RTS
 *  - UART4_RX becomes CTS
 */

#include <dt-bindings/gpio/gpio.h>

#include "imx8mm-pinfunc.h"

/dts-v1/;
/plugin/;

&{/} {
	compatible = "gw,imx8mm-gw72xx-0x";
};

&gpio4 {
	rs485_en {
		gpio-hog;
		gpios = <0 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "rs485_en";
	};
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
	cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";
};

&uart4 {
	status = "disabled";
};

&iomuxc {
	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140
			MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28	0x140
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Gateworks Corporation
 *
 * GW72xx RS422 (RS485 full duplex):
 *  - GPIO1_0 rs485_term selects on-chip termination
 *  - GPIO4_0 rs485_en needs to be driven high (active)
 *  - GPIO4_2 rs485_hd needs to be driven low (in-active)
 *  - UART4_TX is DE for RS485 transmitter
 *  - RS485_EN needs to be pulled high
 *  - RS485_HALF needs to be low
 */

#include <dt-bindings/gpio/gpio.h>

#include "imx8mm-pinfunc.h"

/dts-v1/;
/plugin/;

&{/} {
	compatible = "gw,imx8mm-gw72xx-0x";
};

&gpio4 {
	rs485_en {
		gpio-hog;
		gpios = <0 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "rs485_en";
	};

	rs485_hd {
		gpio-hog;
		gpios = <2 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "rs485_hd";
	};
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
	linux,rs485-enabled-at-boot-time;
	status = "okay";
};

&uart4 {
	status = "disabled";
};

&iomuxc {
	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Gateworks Corporation
 *
 * GW72xx RS485 HD:
 *  - GPIO1_0 rs485_term selects on-chip termination
 *  - GPIO4_0 rs485_en needs to be driven high (active)
 *  - GPIO4_2 rs485_hd needs to be driven high (active)
 *  - UART4_TX is DE for RS485 transmitter
 *  - RS485_EN needs to be pulled high
 *  - RS485_HALF needs to be pulled high
 */

#include <dt-bindings/gpio/gpio.h>

#include "imx8mm-pinfunc.h"

/dts-v1/;
/plugin/;

&{/} {
	compatible = "gw,imx8mm-gw72xx-0x";
};

&gpio4 {
	rs485_en {
		gpio-hog;
		gpios = <0 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "rs485_en";
	};

	rs485_hd {
		gpio-hog;
		gpios = <2 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "rs485_hd";
	};
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
	linux,rs485-enabled-at-boot-time;
	status = "okay";
};

&uart4 {
	status = "disabled";
};

&iomuxc {
	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2020 Gateworks Corporation
 */

/dts-v1/;

#include "imx8mm.dtsi"
#include "imx8mm-venice-gw700x.dtsi"
#include "imx8mm-venice-gw72xx.dtsi"

/ {
	model = "Gateworks Venice GW72xx-0x i.MX8MM Development Kit";
	compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";

	chosen {
		stdout-path = &uart2;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2020 Gateworks Corporation
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>

/ {
	aliases {
		ethernet1 = &eth1;
		usb0 = &usbotg1;
		usb1 = &usbotg2;
	};

	led-controller {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led-0 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};

		led-1 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pps {
		compatible = "pps-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pps>;
		gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_usb_otg1_vbus: regulator-usb-otg1 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb1_en>;
		compatible = "regulator-fixed";
		regulator-name = "usb_otg1_vbus";
		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_usb_otg2_vbus: regulator-usb-otg2 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb2_en>;
		compatible = "regulator-fixed";
		regulator-name = "usb_otg2_vbus";
		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};
};

/* off-board header */
&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi2>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&gpio1 {
	gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
		"", "", "pci_usb_sel", "dio0",
		"", "dio1", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio4 {
	gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
		"mipi_gpio1", "", "", "pci_wdis#",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	accelerometer@19 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_accel>;
		compatible = "st,lis2de12";
		reg = <0x19>;
		st,drdy-int-pin = <1>;
		interrupt-parent = <&gpio4>;
		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "INT1";
	};
};

/* off-board header */
&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,clkreq-unsupported;
	clocks = <&pcie0_refclk>;
	clock-names = "ref";
	status = "okay";
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_250M>;
	status = "okay";

	pcie@0,0 {
		reg = <0x0000 0 0 0 0>;
		#address-cells = <1>;
		#size-cells = <0>;

		pcie@1,0 {
			reg = <0x0000 0 0 0 0>;
			#address-cells = <1>;
			#size-cells = <0>;

			pcie@2,3 {
				reg = <0x1800 0 0 0 0>;
				#address-cells = <1>;
				#size-cells = <0>;

				eth1: pcie@5,0 {
					reg = <0x0000 0 0 0 0>;
					#address-cells = <1>;
					#size-cells = <0>;

					local-mac-address = [00 00 00 00 00 00];
				};
			};
		};
	};
};

/* off-board header */
&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

/* GPS */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* off-board header */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

/* RS232 */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	over-current-active-low;
	vbus-supply = <&reg_usb_otg1_vbus>;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	vbus-supply = <&reg_usb_otg2_vbus>;
	status = "okay";
};

/* microSD */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* PLUG_TEST */
			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* PCI_USBSEL */
			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000041 /* PCIE_WDIS# */
			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIO0 */
			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x40000041 /* DIO1 */
			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x40000104 /* RS485_TERM */
			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x40000104 /* RS485 */
			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x40000104 /* RS485_HALF */
		>;
	};

	pinctrl_accel: accelgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x159
		>;
	};

	pinctrl_gpio_leds: gpioledgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x19
			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x19
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x41
		>;
	};

	pinctrl_pps: ppsgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x41
		>;
	};

	pinctrl_reg_usb1_en: regusb1grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x41
			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x41
		>;
	};

	pinctrl_reg_usb2_en: regusb2grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x41
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
		>;
	};

	pinctrl_spi2: spi2grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6
			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
			MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B	0x1d0
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Gateworks Corporation
 */

#include <dt-bindings/gpio/gpio.h>

#include "imx8mm-pinfunc.h"

/dts-v1/;
/plugin/;

&{/} {
	compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";

	reg_cam: regulator-cam {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_cam>;
		compatible = "regulator-fixed";
		regulator-name = "reg_cam";
		gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	cam24m: cam24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "cam24m";
	};
};

&csi {
	status = "okay";
};

&i2c3 {
	#address-cells = <1>;
	#size-cells = <0>;

	imx219: sensor@10 {
		compatible = "sony,imx219";
		reg = <0x10>;
		clocks = <&cam24m>;
		VDIG-supply = <&reg_cam>;

		port {
			/* MIPI CSI-2 bus endpoint */
			imx219_to_mipi_csi2: endpoint {
				remote-endpoint = <&imx8mm_mipi_csi_in>;
				clock-lanes = <0>;
				data-lanes = <1 2>;
				link-frequencies = /bits/ 64 <456000000>;
			};
		};
	};
};

&mipi_csi {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;

			imx8mm_mipi_csi_in: endpoint {
				remote-endpoint = <&imx219_to_mipi_csi2>;
				data-lanes = <1 2>;
			};
		};

		port@1 {
			reg = <1>;

			imx8mm_mipi_csi_out: endpoint {
				remote-endpoint = <&csi_in>;
			};
		};
	};
};

&iomuxc {
	pinctrl_reg_cam: regcamgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1	0x41
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Gateworks Corporation
 *
 * GW73xx RS232 with RTS/CTS hardware flow control:
 *  - GPIO4_0 rs485_en needs to be driven low (in-active)
 *  - UART4_TX becomes RTS
 *  - UART4_RX becomes CTS
 */

#include <dt-bindings/gpio/gpio.h>

#include "imx8mm-pinfunc.h"

/dts-v1/;
/plugin/;

&{/} {
	compatible = "gw,imx8mm-gw73xx-0x";
};

&gpio4 {
	rs485_en {
		gpio-hog;
		gpios = <0 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "rs485_en";
	};
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
	cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";
};

&uart4 {
	status = "disabled";
};

&iomuxc {
	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140
			MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28	0x140
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2021 Gateworks Corporation
 *
 * GW73xx RS422 (RS485 full duplex):
 *  - GPIO1_0 rs485_term selects on-chip termination
 *  - GPIO4_0 rs485_en needs to be driven high (active)
 *  - GPIO4_2 rs485_hd needs to be driven low (in-active)
 *  - UART4_TX is DE for RS485 transmitter
 *  - RS485_EN needs to be pulled high
 *  - RS485_HALF needs to be low
 */

#include <dt-bindings/gpio/gpio.h>

#include "imx8mm-pinfunc.h"

/dts-v1/;
/plugin/;

&{/} {
	compatible = "gw,imx8mm-gw73xx-0x";
};

&gpio4 {
	rs485_en {
		gpio-hog;
		gpios = <0 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "rs485_en";
	};

	rs485_hd {
		gpio-hog;
		gpios = <2 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "rs485_hd";
	};
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
	linux,rs485-enabled-at-boot-time;
	status = "okay";
};

&uart4 {
	status = "disabled";
};

&iomuxc {
	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2021 Gateworks Corporation
 *
 * GW73xx RS485 HD:
 *  - GPIO1_0 rs485_term selects on-chip termination
 *  - GPIO4_0 rs485_en needs to be driven high (active)
 *  - GPIO4_2 rs485_hd needs to be driven high (active)
 *  - UART4_TX is DE for RS485 transmitter
 *  - RS485_EN needs to be pulled high
 *  - RS485_HALF needs to be pulled high
 */

#include <dt-bindings/gpio/gpio.h>

#include "imx8mm-pinfunc.h"

/dts-v1/;
/plugin/;

&{/} {
	compatible = "gw,imx8mm-gw73xx-0x";
};

&gpio4 {
	rs485_en {
		gpio-hog;
		gpios = <0 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "rs485_en";
	};

	rs485_hd {
		gpio-hog;
		gpios = <2 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "rs485_hd";
	};
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
	linux,rs485-enabled-at-boot-time;
	status = "okay";
};

&uart4 {
	status = "disabled";
};

&iomuxc {
	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2020 Gateworks Corporation
 */

/dts-v1/;

#include "imx8mm.dtsi"
#include "imx8mm-venice-gw700x.dtsi"
#include "imx8mm-venice-gw73xx.dtsi"

/ {
	model = "Gateworks Venice GW73xx-0x i.MX8MM Development Kit";
	compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";

	chosen {
		stdout-path = &uart2;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2020 Gateworks Corporation
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>

/ {
	aliases {
		ethernet1 = &eth1;
		usb0 = &usbotg1;
		usb1 = &usbotg2;
	};

	led-controller {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led-0 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};

		led-1 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pps {
		compatible = "pps-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pps>;
		gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_usb_otg1_vbus: regulator-usb-otg1 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb1_en>;
		compatible = "regulator-fixed";
		regulator-name = "usb_otg1_vbus";
		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_usb_otg2_vbus: regulator-usb-otg2 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb2_en>;
		compatible = "regulator-fixed";
		regulator-name = "usb_otg2_vbus";
		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_wifi_en: regulator-wifi-en {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_wl>;
		compatible = "regulator-fixed";
		regulator-name = "wl";
		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
		startup-delay-us = <100>;
		enable-active-high;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

/* off-board header */
&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi2>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&gpio1 {
	gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
		"", "", "pci_usb_sel", "dio0",
		"", "dio1", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio4 {
	gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
		"mipi_gpio1", "", "", "pci_wdis#",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	accelerometer@19 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_accel>;
		compatible = "st,lis2de12";
		reg = <0x19>;
		st,drdy-int-pin = <1>;
		interrupt-parent = <&gpio4>;
		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "INT1";
	};
};

/* off-board header */
&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,clkreq-unsupported;
	clocks = <&pcie0_refclk>;
	clock-names = "ref";
	status = "okay";
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_250M>;
	status = "okay";

	pcie@0,0 {
		reg = <0x0000 0 0 0 0>;
		#address-cells = <1>;
		#size-cells = <0>;

		pcie@1,0 {
			reg = <0x0000 0 0 0 0>;
			#address-cells = <1>;
			#size-cells = <0>;

			pcie@2,4 {
				reg = <0x2000 0 0 0 0>;
				#address-cells = <1>;
				#size-cells = <0>;

				eth1: pcie@6,0 {
					reg = <0x0000 0 0 0 0>;
					#address-cells = <1>;
					#size-cells = <0>;

					local-mac-address = [00 00 00 00 00 00];
				};
			};
		};
	};
};

/* off-board header */
&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

/* GPS */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* bluetooth HCI */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
	cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
		compatible = "brcm,bcm4330-bt";
		shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
	};
};

/* RS232 */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	over-current-active-low;
	vbus-supply = <&reg_usb_otg1_vbus>;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	vbus-supply = <&reg_usb_otg2_vbus>;
	status = "okay";
};

/* SDIO WiFi */
&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <4>;
	non-removable;
	vmmc-supply = <&reg_wifi_en>;
	status = "okay";
};

/* microSD */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* PLUG_TEST */
			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* PCI_USBSEL */
			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000041 /* PCIE_WDIS# */
			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIO0 */
			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x40000041 /* DIO1 */
			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x40000104 /* RS485_TERM */
			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x40000104 /* RS485 */
			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x40000104 /* RS485_HALF */
		>;
	};

	pinctrl_accel: accelgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x159
		>;
	};

	pinctrl_bten: btengrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
		>;
	};

	pinctrl_gpio_leds: gpioledgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x19
			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x19
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x41
		>;
	};

	pinctrl_pps: ppsgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x41
		>;
	};

	pinctrl_reg_wl: regwlgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x41
		>;
	};

	pinctrl_reg_usb1_en: regusb1grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x41
			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x41
		>;
	};

	pinctrl_reg_usb2_en: regusb2grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x41
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
		>;
	};

	pinctrl_spi2: spi2grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6
			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
			MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8	0x140
			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x140
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
			MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B	0x1d0
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};
};