code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip designware mobile storage host controller

description:
  Rockchip uses the Synopsys designware mobile storage host controller
  to interface a SoC with storage medium such as eMMC or SD/MMC cards.
  This file documents the combined properties for the core Synopsys dw mshc
  controller that are not already included in the synopsys-dw-mshc-common.yaml
  file and the Rockchip specific extensions.

allOf:
  - $ref: "synopsys-dw-mshc-common.yaml#"

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

# Everything else is described in the common file
properties:
  compatible:
    oneOf:
      # for Rockchip RK2928 and before RK3288
      - const: rockchip,rk2928-dw-mshc
      # for Rockchip RK3288
      - const: rockchip,rk3288-dw-mshc
      - items:
          - enum:
              - rockchip,px30-dw-mshc
              - rockchip,rk1808-dw-mshc
              - rockchip,rk3036-dw-mshc
              - rockchip,rk3128-dw-mshc
              - rockchip,rk3228-dw-mshc
              - rockchip,rk3308-dw-mshc
              - rockchip,rk3328-dw-mshc
              - rockchip,rk3368-dw-mshc
              - rockchip,rk3399-dw-mshc
              - rockchip,rk3568-dw-mshc
              - rockchip,rv1108-dw-mshc
              - rockchip,rv1126-dw-mshc
          - const: rockchip,rk3288-dw-mshc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 4
    description:
      Handle to "biu" and "ciu" clocks for the bus interface unit clock and
      the card interface unit clock. If "ciu-drive" and "ciu-sample" are
      specified in clock-names, it should also contain
      handles to these clocks.

  clock-names:
    minItems: 2
    items:
      - const: biu
      - const: ciu
      - const: ciu-drive
      - const: ciu-sample
    description:
      Apart from the clock-names "biu" and "ciu" two more clocks
      "ciu-drive" and "ciu-sample" are supported. They are used
      to control the clock phases, "ciu-sample" is required for tuning
      high speed modes.

  power-domains:
    maxItems: 1

  rockchip,default-sample-phase:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 360
    default: 0
    description:
      The default phase to set "ciu-sample" at probing,
      low speeds or in case where all phases work at tuning time.
      If not specified 0 deg will be used.

  rockchip,desired-num-phases:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 360
    default: 360
    description:
      The desired number of times that the host execute tuning when needed.
      If not specified, the host will do tuning for 360 times,
      namely tuning for each degree.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3288-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    sdmmc: mmc@ff0c0000 {
      compatible = "rockchip,rk3288-dw-mshc";
      reg = <0xff0c0000 0x4000>;
      interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
               <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
      clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
      resets = <&cru SRST_MMC0>;
      reset-names = "reset";
      fifo-depth = <0x100>;
      max-frequency = <150000000>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title:
  Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile
  Storage Host Controller

maintainers:
  - Jaehoon Chung <jh80.chung@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - samsung,exynos4210-dw-mshc
      - samsung,exynos4412-dw-mshc
      - samsung,exynos5250-dw-mshc
      - samsung,exynos5420-dw-mshc
      - samsung,exynos5420-dw-mshc-smu
      - samsung,exynos7-dw-mshc
      - samsung,exynos7-dw-mshc-smu
      - axis,artpec8-dw-mshc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 2
    description:
      Handle to "biu" and "ciu" clocks for the
      bus interface unit clock and the card interface unit clock.

  clock-names:
    items:
      - const: biu
      - const: ciu

  samsung,dw-mshc-ciu-div:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 7
    description:
      The divider value for the card interface unit (ciu) clock.

  samsung,dw-mshc-ddr-timing:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    items:
      - description: CIU clock phase shift value for tx mode
        minimum: 0
        maximum: 7
      - description: CIU clock phase shift value for rx mode
        minimum: 0
        maximum: 7
    description:
      The value of CUI clock phase shift value in transmit mode and CIU clock
      phase shift value in receive mode for double data rate mode operation.
      See also samsung,dw-mshc-hs400-timing property.

  samsung,dw-mshc-hs400-timing:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    items:
      - description: CIU clock phase shift value for tx mode
        minimum: 0
        maximum: 7
      - description: CIU clock phase shift value for rx mode
        minimum: 0
        maximum: 7
    description: |
      The value of CIU TX and RX clock phase shift value for HS400 mode
      operation.
      Valid values for SDR and DDR CIU clock timing::
        - valid value for tx phase shift and rx phase shift is 0 to 7.
        - when CIU clock divider value is set to 3, all possible 8 phase shift
          values can be used.
        - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
          phase shift clocks should be 0.
      If missing, values from samsung,dw-mshc-ddr-timing property are used.

  samsung,dw-mshc-sdr-timing:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    items:
      - description: CIU clock phase shift value for tx mode
        minimum: 0
        maximum: 7
      - description: CIU clock phase shift value for rx mode
        minimum: 0
        maximum: 7
    description:
      The value of CIU clock phase shift value in transmit mode and CIU clock
      phase shift value in receive mode for single data rate mode operation.
      See also samsung,dw-mshc-hs400-timing property.

  samsung,read-strobe-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
      line in Read path). If missing, default from hardware is used.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - samsung,dw-mshc-ddr-timing
  - samsung,dw-mshc-sdr-timing

allOf:
  - $ref: "synopsys-dw-mshc-common.yaml#"
  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos5250-dw-mshc
              - samsung,exynos5420-dw-mshc
              - samsung,exynos7-dw-mshc
              - samsung,exynos7-dw-mshc-smu
              - axis,artpec8-dw-mshc
    then:
      required:
        - samsung,dw-mshc-ciu-div

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5420.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mmc@12220000 {
        compatible = "samsung,exynos5420-dw-mshc";
        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x12220000 0x1000>;
        clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
        clock-names = "biu", "ciu";
        fifo-depth = <0x40>;
        card-detect-delay = <200>;
        samsung,dw-mshc-ciu-div = <3>;
        samsung,dw-mshc-sdr-timing = <0 4>;
        samsung,dw-mshc-ddr-timing = <0 2>;
        pinctrl-names = "default";
        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
        bus-width = <4>;
        cap-sd-highspeed;
        max-frequency = <200000000>;
        vmmc-supply = <&ldo19_reg>;
        vqmmc-supply = <&ldo13_reg>;
        sd-uhs-sdr50;
        sd-uhs-sdr104;
        sd-uhs-ddr50;
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/samsung,s3c6410-sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung SoC SDHCI Controller

maintainers:
  - Jaehoon Chung <jh80.chung@samsung.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - samsung,s3c6410-sdhci
      - samsung,exynos4210-sdhci

  reg:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 5

  clock-names:
    minItems: 2
    items:
      - const: hsmmc
      - pattern: "^mmc_busclk.[0-3]$"
      - pattern: "^mmc_busclk.[0-3]$"
      - pattern: "^mmc_busclk.[0-3]$"
      - pattern: "^mmc_busclk.[0-3]$"

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

allOf:
  - $ref: mmc-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos4210-sdhci
    then:
      properties:
        clocks:
          maxItems: 2
        clock-names:
          items:
            - const: hsmmc
            - const: mmc_busclk.2

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos4.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mmc@12510000 {
        compatible = "samsung,exynos4210-sdhci";
        reg = <0x12510000 0x100>;
        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
        clock-names = "hsmmc", "mmc_busclk.2";
        bus-width = <4>;
        cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>;
        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>;
        pinctrl-names = "default";
        vmmc-supply = <&ldo21_reg>;
    };


code:
* Samsung's S3C24XX MMC/SD/SDIO controller device tree bindings

Samsung's S3C24XX MMC/SD/SDIO controller is used as a connectivity interface
with external MMC, SD and SDIO storage mediums.

This file documents differences between the core mmc properties described by
mmc.txt and the properties used by the Samsung S3C24XX MMC/SD/SDIO controller
implementation.

Required SoC Specific Properties:
- compatible: should be one of the following
  - "samsung,s3c2410-sdi": for controllers compatible with s3c2410
  - "samsung,s3c2412-sdi": for controllers compatible with s3c2412
  - "samsung,s3c2440-sdi": for controllers compatible with s3c2440
- reg: register location and length
- interrupts: mmc controller interrupt
- clocks: Should reference the controller clock
- clock-names: Should contain "sdi"

Required Board Specific Properties:
- pinctrl-0: Should specify pin control groups used for this controller.
- pinctrl-names: Should contain only one value - "default".

Optional Properties:
- bus-width: number of data lines (see mmc.txt)
- cd-gpios: gpio for card detection (see mmc.txt)
- wp-gpios: gpio for write protection (see mmc.txt)

Example:

	mmc0: mmc@5a000000 {
		compatible = "samsung,s3c2440-sdi";
		pinctrl-names = "default";
		pinctrl-0 = <&sdi_pins>;
		reg = <0x5a000000 0x100000>;
		interrupts = <0 0 21 3>;
		clocks = <&clocks PCLK_SDI>;
		clock-names = "sdi";
		bus-width = <4>;
		cd-gpios = <&gpg 8 GPIO_ACTIVE_LOW>;
		wp-gpios = <&gph 8 GPIO_ACTIVE_LOW>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI AM654 MMC Controller

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

allOf:
  - $ref: sdhci-common.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - ti,am62-sdhci
          - ti,am64-sdhci-4bit
          - ti,am64-sdhci-8bit
          - ti,am654-sdhci-5.1
          - ti,j721e-sdhci-4bit
          - ti,j721e-sdhci-8bit
      - items:
          - const: ti,j7200-sdhci-8bit
          - const: ti,j721e-sdhci-8bit
      - items:
          - const: ti,j7200-sdhci-4bit
          - const: ti,j721e-sdhci-4bit

  reg:
    maxItems: 2

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2
    description: Handles to input clocks

  clock-names:
    minItems: 1
    items:
      - const: clk_ahb
      - const: clk_xin

  dma-coherent:
    type: boolean

  # PHY output tap delays:
  # Used to delay the data valid window and align it to the sampling clock.
  # Binding needs to be provided for each supported speed mode otherwise the
  # corresponding mode will be disabled.

  ti,otap-del-sel-legacy:
    description: Output tap delay for SD/MMC legacy timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-mmc-hs:
    description: Output tap delay for MMC high speed timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-sd-hs:
    description: Output tap delay for SD high speed timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-sdr12:
    description: Output tap delay for SD UHS SDR12 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-sdr25:
    description: Output tap delay for SD UHS SDR25 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-sdr50:
    description: Output tap delay for SD UHS SDR50 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-sdr104:
    description: Output tap delay for SD UHS SDR104 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-ddr50:
    description: Output tap delay for SD UHS DDR50 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-ddr52:
    description: Output tap delay for eMMC DDR52 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-hs200:
    description: Output tap delay for eMMC HS200 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,otap-del-sel-hs400:
    description: Output tap delay for eMMC HS400 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  # PHY input tap delays:
  # Used to delay the data valid window and align it to the sampling clock for
  # modes that don't support tuning

  ti,itap-del-sel-legacy:
    description: Input tap delay for SD/MMC legacy timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,itap-del-sel-mmc-hs:
    description: Input tap delay for MMC high speed timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,itap-del-sel-sd-hs:
    description: Input tap delay for SD high speed timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,itap-del-sel-sdr12:
    description: Input tap delay for SD UHS SDR12 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,itap-del-sel-sdr25:
    description: Input tap delay for SD UHS SDR25 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,itap-del-sel-ddr50:
    description: Input tap delay for MMC DDR50 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,itap-del-sel-ddr52:
    description: Input tap delay for MMC DDR52 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  ti,trm-icp:
    description: DLL trim select
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0xf

  ti,driver-strength-ohm:
    description: DLL drive strength in ohms
    $ref: /schemas/types.yaml#/definitions/uint32
    enum:
      - 33
      - 40
      - 50
      - 66
      - 100

  ti,strobe-sel:
    description: strobe select delay for HS400 speed mode.
    $ref: /schemas/types.yaml#/definitions/uint32

  ti,clkbuf-sel:
    description: Clock Delay Buffer Select
    $ref: /schemas/types.yaml#/definitions/uint32

  ti,fails-without-test-cd:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      When present, indicates that the CD line is not connected
      and the controller is required to be forced into Test mode
      to set the TESTCD bit.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - ti,otap-del-sel-legacy

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        mmc0: mmc@4f80000 {
            compatible = "ti,am654-sdhci-5.1";
            reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
            power-domains = <&k3_pds 47>;
            clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
            clock-names = "clk_ahb", "clk_xin";
            interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
            sdhci-caps-mask = <0x80000007 0x0>;
            mmc-ddr-1_8v;
            ti,otap-del-sel-legacy = <0x0>;
            ti,otap-del-sel-mmc-hs = <0x0>;
            ti,otap-del-sel-ddr52 = <0x5>;
            ti,otap-del-sel-hs200 = <0x5>;
            ti,otap-del-sel-hs400 = <0x0>;
            ti,itap-del-sel-legacy = <0x10>;
            ti,itap-del-sel-mmc-hs = <0xa>;
            ti,itap-del-sel-ddr52 = <0x3>;
            ti,trm-icp = <0x8>;
        };
    };


code:
* Atmel SDHCI controller

This file documents the differences between the core properties in
Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the
sdhci-of-at91 driver.

Required properties:
- compatible:		Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci".
- clocks:		Phandlers to the clocks.
- clock-names:		Must be "hclock", "multclk", "baseclk" for
			"atmel,sama5d2-sdhci".
			Must be "hclock", "multclk" for "microchip,sam9x60-sdhci".

Optional properties:
- assigned-clocks:	The same with "multclk".
- assigned-clock-rates	The rate of "multclk" in order to not rely on the
			gck configuration set by previous components.
- microchip,sdcal-inverted: when present, polarity on the SDCAL SoC pin is
  inverted. The default polarity for this signal is described in the datasheet.
  For instance on SAMA5D2, the pin is usually tied to the GND with a resistor
  and a capacitor (see "SDMMC I/O Calibration" chapter).

Example:

mmc0: sdio-host@a0000000 {
	compatible = "atmel,sama5d2-sdhci";
	reg = <0xa0000000 0x300>;
	interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
	clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
	clock-names = "hclock", "multclk", "baseclk";
	assigned-clocks = <&sdmmc0_gclk>;
	assigned-clock-rates = <480000000>;
};


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/sdhci-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SDHCI Controller Common Properties

maintainers:
  - Adrian Hunter <adrian.hunter@intel.com>

description:
  Common properties present on Secure Digital Host Controller Interface (SDHCI)
  devices.

properties:
  sdhci-caps:
    $ref: /schemas/types.yaml#/definitions/uint64
    description:
      Additionally present SDHCI capabilities - values for SDHCI_CAPABILITIES
      and SDHCI_CAPABILITIES_1 registers.

  sdhci-caps-mask:
    $ref: /schemas/types.yaml#/definitions/uint64
    description:
      Masked SDHCI capabilities to remove from SDHCI_CAPABILITIES and
      SDHCI_CAPABILITIES_1 registers.

allOf:
  - $ref: mmc-controller.yaml#

additionalProperties: true


code:
* SOCIONEXT Milbeaut SDHCI controller

This file documents differences between the core properties in mmc.txt
and the properties used by the sdhci_milbeaut driver.

Required properties:
- compatible: "socionext,milbeaut-m10v-sdhci-3.0"
- clocks: Must contain an entry for each entry in clock-names. It is a
  list of phandles and clock-specifier pairs.
  See ../clocks/clock-bindings.txt for details.
- clock-names: Should contain the following two entries:
	"iface" - clock used for sdhci interface
	"core"  - core clock for sdhci controller

Optional properties:
- fujitsu,cmd-dat-delay-select: boolean property indicating that this host
  requires the CMD_DAT_DELAY control to be enabled.

Example:
	sdhci3: mmc@1b010000 {
		compatible = "socionext,milbeaut-m10v-sdhci-3.0";
		reg = <0x1b010000 0x10000>;
		interrupts = <0 265 0x4>;
		voltage-ranges = <3300 3300>;
		bus-width = <4>;
		clocks = <&clk 7>, <&ahb_clk>;
		clock-names = "core", "iface";
		cap-sdio-irq;
		fujitsu,cmd-dat-delay-select;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SDHCI controller (sdhci-msm)

maintainers:
  - Bhupesh Sharma <bhupesh.sharma@linaro.org>

description:
  Secure Digital Host Controller Interface (SDHCI) present on
  Qualcomm SOCs supports SD/MMC/SDIO devices.

properties:
  compatible:
    oneOf:
      - enum:
          - qcom,sdhci-msm-v4
        deprecated: true
      - items:
          - enum:
              - qcom,apq8084-sdhci
              - qcom,msm8226-sdhci
              - qcom,msm8953-sdhci
              - qcom,msm8974-sdhci
              - qcom,msm8976-sdhci
              - qcom,msm8916-sdhci
              - qcom,msm8992-sdhci
              - qcom,msm8994-sdhci
              - qcom,msm8996-sdhci
              - qcom,msm8998-sdhci
          - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
      - items:
          - enum:
              - qcom,qcs404-sdhci
              - qcom,sc7180-sdhci
              - qcom,sc7280-sdhci
              - qcom,sdm630-sdhci
              - qcom,sdm670-sdhci
              - qcom,sdm845-sdhci
              - qcom,sdx55-sdhci
              - qcom,sdx65-sdhci
              - qcom,sm6115-sdhci
              - qcom,sm6125-sdhci
              - qcom,sm6350-sdhci
              - qcom,sm6375-sdhci
              - qcom,sm8150-sdhci
              - qcom,sm8250-sdhci
              - qcom,sm8350-sdhci
              - qcom,sm8450-sdhci
              - qcom,sm8550-sdhci
          - const: qcom,sdhci-msm-v5 # for sdcc version 5.0

  reg:
    minItems: 1
    maxItems: 4

  reg-names:
    minItems: 1
    maxItems: 4

  clocks:
    minItems: 3
    items:
      - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
      - description: SDC MMC clock, MCLK
      - description: TCXO clock
      - description: clock for Inline Crypto Engine
      - description: SDCC bus voter clock
      - description: reference clock for RCLK delay calibration
      - description: sleep clock for RCLK delay calibration

  clock-names:
    minItems: 2
    items:
      - const: iface
      - const: core
      - const: xo
      - const: ice
      - const: bus
      - const: cal
      - const: sleep

  dma-coherent: true

  interrupts:
    maxItems: 2

  interrupt-names:
    items:
      - const: hc_irq
      - const: pwr_irq

  pinctrl-names:
    minItems: 1
    items:
      - const: default
      - const: sleep

  pinctrl-0:
    description:
      Should specify pin control groups used for this controller.

  pinctrl-1:
    description:
      Should specify sleep pin control groups used for this controller.

  resets:
    maxItems: 1

  qcom,ddr-config:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: platform specific settings for DDR_CONFIG reg.

  qcom,dll-config:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: platform specific settings for DLL_CONFIG reg.

  iommus:
    minItems: 1
    maxItems: 8
    description: |
      phandle to apps_smmu node with sid mask.

  interconnects:
    items:
      - description: data path, sdhc to ddr
      - description: config path, cpu to sdhc

  interconnect-names:
    items:
      - const: sdhc-ddr
      - const: cpu-sdhc

  power-domains:
    description: A phandle to sdhci power domain node
    maxItems: 1

  operating-points-v2: true

patternProperties:
  '^opp-table(-[a-z0-9]+)?$':
    if:
      properties:
        compatible:
          const: operating-points-v2
    then:
      patternProperties:
        '^opp-?[0-9]+$':
          required:
            - required-opps

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts

allOf:
  - $ref: sdhci-common.yaml#

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdhci-msm-v4
    then:
      properties:
        reg:
          minItems: 2
          items:
            - description: Host controller register map
            - description: SD Core register map
            - description: CQE register map
            - description: Inline Crypto Engine register map
        reg-names:
          minItems: 2
          items:
            - const: hc
            - const: core
            - const: cqhci
            - const: ice
    else:
      properties:
        reg:
          minItems: 1
          items:
            - description: Host controller register map
            - description: CQE register map
            - description: Inline Crypto Engine register map
        reg-names:
          minItems: 1
          items:
            - const: hc
            - const: cqhci
            - const: ice

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,gcc-sm8250.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    sdhc_2: mmc@8804000 {
      compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
      reg = <0 0x08804000 0 0x1000>;

      interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "hc_irq", "pwr_irq";

      clocks = <&gcc GCC_SDCC2_AHB_CLK>,
               <&gcc GCC_SDCC2_APPS_CLK>,
               <&rpmhcc RPMH_CXO_CLK>;
      clock-names = "iface", "core", "xo";
      iommus = <&apps_smmu 0x4a0 0x0>;
      qcom,dll-config = <0x0007642c>;
      qcom,ddr-config = <0x80040868>;
      power-domains = <&rpmhpd SM8250_CX>;

      operating-points-v2 = <&sdhc2_opp_table>;

      sdhc2_opp_table: opp-table {
        compatible = "operating-points-v2";

        opp-19200000 {
          opp-hz = /bits/ 64 <19200000>;
          required-opps = <&rpmhpd_opp_min_svs>;
        };

        opp-50000000 {
          opp-hz = /bits/ 64 <50000000>;
          required-opps = <&rpmhpd_opp_low_svs>;
        };

        opp-100000000 {
          opp-hz = /bits/ 64 <100000000>;
          required-opps = <&rpmhpd_opp_svs>;
        };

        opp-202000000 {
          opp-hz = /bits/ 64 <202000000>;
          required-opps = <&rpmhpd_opp_svs_l1>;
        };
      };
    };


code:
* TI OMAP SDHCI Controller

Refer to mmc.txt for standard MMC bindings.

For UHS devices which require tuning, the device tree should have a "cpu_thermal" node which maps to the appropriate thermal zone. This is used to get the temperature of the zone during tuning.

Required properties:
- compatible: Should be "ti,omap2430-sdhci" for omap2430 controllers
	      Should be "ti,omap3-sdhci" for omap3 controllers
	      Should be "ti,omap4-sdhci" for omap4 and ti81 controllers
	      Should be "ti,omap5-sdhci" for omap5 controllers
	      Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers
	      Should be "ti,k2g-sdhci" for K2G
	      Should be "ti,am335-sdhci" for am335x controllers
	      Should be "ti,am437-sdhci" for am437x controllers
- ti,hwmods: Must be "mmc<n>", <n> is controller instance starting 1
	     (Not required for K2G).
- pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50",
		 "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104",
		 "ddr_1_8v-rev11", "ddr_1_8v" or "ddr_3_3v", "hs200_1_8v-rev11",
		 "hs200_1_8v",
- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt

Optional properties:
- dmas:		List of DMA specifiers with the controller specific format as described
		in the generic DMA client binding. A tx and rx specifier is required.
- dma-names:	List of DMA request names. These strings correspond 1:1 with the
		DMA specifiers listed in dmas. The string naming is to be "tx"
		and "rx" for TX and RX DMA requests, respectively.

Deprecated properties:
- ti,non-removable: Compatible with the generic non-removable property

Example:
	mmc1: mmc@4809c000 {
		compatible = "ti,dra7-sdhci";
		reg = <0x4809c000 0x400>;
		ti,hwmods = "mmc1";
		bus-width = <4>;
		vmmc-supply = <&vmmc>; /* phandle to regulator node */
		dmas = <&sdma 61 &sdma 62>;
		dma-names = "tx", "rx";
	};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell PXA SDHCI v2/v3 bindings

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

allOf:
  - $ref: mmc-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: marvell,armada-380-sdhci
    then:
      properties:
        regs:
          minItems: 3
        reg-names:
          minItems: 3
      required:
        - reg-names
    else:
      properties:
        regs:
          maxItems: 1
        reg-names:
          maxItems: 1

properties:
  compatible:
    enum:
      - mrvl,pxav2-mmc
      - mrvl,pxav3-mmc
      - marvell,armada-380-sdhci

  reg:
    minItems: 1
    maxItems: 3

  reg-names:
    items:
      - const: sdhci
      - const: mbus
      - const: conf-sdio3

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: io
      - const: core

  mrvl,clk-delay-cycles:
    description: Specify a number of cycles to delay for tuning.
    $ref: /schemas/types.yaml#/definitions/uint32

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/berlin2.h>
    mmc@d4280800 {
        compatible = "mrvl,pxav3-mmc";
        reg = <0xd4280800 0x800>;
        bus-width = <8>;
        interrupts = <27>;
        clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
        clock-names = "io", "core";
        non-removable;
        mrvl,clk-delay-cycles = <31>;
    };
  - |
    mmc@d8000 {
        compatible = "marvell,armada-380-sdhci";
        reg-names = "sdhci", "mbus", "conf-sdio3";
        reg = <0xd8000 0x1000>,
              <0xdc000 0x100>,
              <0x18454 0x4>;
        interrupts = <0 25 0x4>;
        clocks = <&gateclk 17>;
        clock-names = "io";
        mrvl,clk-delay-cycles = <0x1F>;
    };

...


code:
* SPEAr SDHCI Controller

This file documents differences between the core properties in mmc.txt
and the properties used by the sdhci-spear driver.

Required properties:
- compatible: "st,spear300-sdhci"

Optional properties:
- cd-gpios: card detect gpio, with zero flags.

Example:

	sdhci@fc000000 {
		compatible = "st,spear300-sdhci";
		reg = <0xfc000000 0x1000>;
		cd-gpios = <&gpio0 6 0>;
	};


code:
* Spreadtrum SDHCI controller (sdhci-sprd)

The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface
for MMC, SD and SDIO types of cards.

This file documents differences between the core properties in mmc.txt
and the properties used by the sdhci-sprd driver.

Required properties:
- compatible: Should contain "sprd,sdhci-r11".
- reg: physical base address of the controller and length.
- interrupts: Interrupts used by the SDHCI controller.
- clocks: Should contain phandle for the clock feeding the SDHCI controller
- clock-names: Should contain the following:
	"sdio" - SDIO source clock (required)
	"enable" - gate clock which used for enabling/disabling the device (required)
	"2x_enable" - gate clock controlling the device for some special platforms (optional)

Optional properties:
- assigned-clocks: the same with "sdio" clock
- assigned-clock-parents: the default parent of "sdio" clock
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin control
- pinctrl-1: should contain uhs mode pin control

PHY DLL delays are used to delay the data valid window, and align the window
to sampling clock. PHY DLL delays can be configured by following properties,
and each property contains 4 cells which are used to configure the clock data
write line delay value, clock read command line delay value, clock read data
positive edge delay value and clock read data negative edge delay value.
Each cell's delay value unit is cycle of the PHY clock.

- sprd,phy-delay-legacy: Delay value for legacy timing.
- sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
- sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
- sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
- sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
- sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
- sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
- sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
- sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.

Examples:

sdio0: sdio@20600000 {
	compatible  = "sprd,sdhci-r11";
	reg = <0 0x20600000 0 0x1000>;
	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;

	clock-names = "sdio", "enable";
	clocks = <&ap_clk CLK_EMMC_2X>,
		 <&apahb_gate CLK_EMMC_EB>;
	assigned-clocks = <&ap_clk CLK_EMMC_2X>;
	assigned-clock-parents = <&rpll CLK_RPLL_390M>;

	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&sd0_pins_default>;
	pinctrl-1 = <&sd0_pins_uhs>;

	sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;
	bus-width = <8>;
	non-removable;
	no-sdio;
	no-sd;
	cap-mmc-hw-reset;
	status = "okay";
};


code:
* STMicroelectronics sdhci-st MMC/SD controller

This file documents the differences between the core properties in
Documentation/devicetree/bindings/mmc/mmc.txt and the properties
used by the sdhci-st driver.

Required properties:
- compatible:		Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
			to set the internal glue logic used for configuring the MMC
			subsystem (mmcss) inside the FlashSS (available in STiH407 SoC
			family).

- clock-names:		Should be "mmc" and "icn".  (NB: The latter is not compulsory)
			See: Documentation/devicetree/bindings/resource-names.txt
- clocks:		Phandle to the clock.
			See: Documentation/devicetree/bindings/clock/clock-bindings.txt

- interrupts:		One mmc interrupt should be described here.
- interrupt-names:	Should be "mmcirq".

- pinctrl-names:	A pinctrl state names "default" must be defined.
- pinctrl-0:		Phandle referencing pin configuration of the sd/emmc controller.
			See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

- reg:			This must provide the host controller base address and it can also
			contain the FlashSS Top register for TX/RX delay used by the driver
			to configure DLL inside the flashSS, if so reg-names must also be
			specified.

Optional properties:
- reg-names:		Should be "mmc" and "top-mmc-delay". "top-mmc-delay" is optional
			for eMMC on stih407 family silicon to configure DLL inside FlashSS.

- non-removable:	Non-removable slot. Also used for configuring mmcss in STiH407 SoC
			family.
			See:  Documentation/devicetree/bindings/mmc/mmc.txt.

- bus-width:		Number of data lines.
			See:  Documentation/devicetree/bindings/mmc/mmc.txt.

- max-frequency:	Can be 200MHz, 100MHz or 50MHz (default) and used for
			configuring the CCONFIG3 in the mmcss.
			See:  Documentation/devicetree/bindings/mmc/mmc.txt.

- resets:		Phandle and reset specifier pair to softreset line of HC IP.
			See: Documentation/devicetree/bindings/reset/reset.txt

- vqmmc-supply:		Phandle to the regulator dt node, mentioned as the vcc/vdd
			supply in eMMC/SD specs.

- sd-uhs-sdr50:	To enable the SDR50 in the mmcss.
			See:  Documentation/devicetree/bindings/mmc/mmc.txt.

- sd-uhs-sdr104:	To enable the SDR104 in the mmcss.
			See:  Documentation/devicetree/bindings/mmc/mmc.txt.

- sd-uhs-ddr50:		To enable the DDR50 in the mmcss.
			See:  Documentation/devicetree/bindings/mmc/mmc.txt.

Example:

/* Example stih416e eMMC configuration */

mmc0: sdhci@fe81e000 {
	compatible	= "st,sdhci";
	reg		= <0xfe81e000 0x1000>;
	interrupts	= <GIC_SPI 127 IRQ_TYPE_NONE>;
	interrupt-names	= "mmcirq";
	pinctrl-names	= "default";
	pinctrl-0	= <&pinctrl_mmc0>;
	clock-names	= "mmc";
	clocks		= <&clk_s_a1_ls 1>;
	bus-width	= <8>

/* Example SD stih407 family configuration */

mmc1: sdhci@9080000 {
	compatible	= "st,sdhci-stih407", "st,sdhci";
	reg		= <0x09080000 0x7ff>;
	reg-names	= "mmc";
	interrupts	= <GIC_SPI 90 IRQ_TYPE_NONE>;
	interrupt-names	= "mmcirq";
	pinctrl-names	= "default";
	pinctrl-0	= <&pinctrl_sd1>;
	clock-names	= "mmc";
	clocks		= <&clk_s_c0_flexgen CLK_MMC_1>;
	resets		= <&softreset STIH407_MMC1_SOFTRESET>;
	bus-width	= <4>;
};

/* Example eMMC stih407 family configuration */

mmc0: sdhci@9060000 {
	compatible	= "st,sdhci-stih407", "st,sdhci";
	reg		= <0x09060000 0x7ff>, <0x9061008 0x20>;
	reg-names	= "mmc", "top-mmc-delay";
	interrupts	= <GIC_SPI 92 IRQ_TYPE_NONE>;
	interrupt-names	= "mmcirq";
	pinctrl-names	= "default";
	pinctrl-0	= <&pinctrl_mmc0>;
	clock-names	= "mmc";
	clocks		= <&clk_s_c0_flexgen CLK_MMC_0>;
	vqmmc-supply	= <&vmmc_reg>;
	max-frequency	= <200000000>;
	bus-width	= <8>;
	non-removable;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	sd-uhs-ddr50;
};


code:
The properties specific for SD host controllers. For properties shared by MMC
host controllers refer to the mmc[1] bindings.

  [1] Documentation/devicetree/bindings/mmc/mmc.txt

Optional properties:
- sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
  property corresponds to the bits in the sdhci capability register. If the bit
  is on in the mask then the bit is incorrect in the register and should be
  turned off, before applying sdhci-caps.
- sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
  property corresponds to the bits in the sdhci capability register. If the
  bit is on in the property then the bit should be turned on.


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys Designware Mobile Storage Host Controller Binding

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>
  - Jisheng Zhang <Jisheng.Zhang@synaptics.com>

allOf:
  - $ref: mmc-controller.yaml#

properties:
  compatible:
    enum:
      - rockchip,rk3568-dwcmshc
      - rockchip,rk3588-dwcmshc
      - snps,dwcmshc-sdhci

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: core clock
      - description: bus clock for optional
      - description: axi clock for rockchip specified
      - description: block clock for rockchip specified
      - description: timer clock for rockchip specified

  clock-names:
    minItems: 1
    items:
      - const: core
      - const: bus
      - const: axi
      - const: block
      - const: timer

  resets:
    maxItems: 5

  reset-names:
    items:
      - const: core
      - const: bus
      - const: axi
      - const: block
      - const: timer

  rockchip,txclk-tapnum:
    description: Specify the number of delay for tx sampling.
    $ref: /schemas/types.yaml#/definitions/uint8

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    mmc@fe310000 {
      compatible = "rockchip,rk3568-dwcmshc";
      reg = <0xfe310000 0x10000>;
      interrupts = <0 25 0x4>;
      clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
      clock-names = "core", "bus", "axi", "block", "timer";
      bus-width = <8>;
      #address-cells = <1>;
      #size-cells = <0>;
    };
  - |
    mmc@aa0000 {
      compatible = "snps,dwcmshc-sdhci";
      reg = <0xaa000 0x1000>;
      interrupts = <0 25 0x4>;
      clocks = <&cru 17>, <&cru 18>;
      clock-names = "core", "bus";
      bus-width = <8>;
      #address-cells = <1>;
      #size-cells = <0>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/socionext,uniphier-sd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UniPhier SD/SDIO/eMMC controller

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

properties:
  compatible:
    description: version 2.91, 3.1, 3.1.1, respectively
    enum:
      - socionext,uniphier-sd-v2.91
      - socionext,uniphier-sd-v3.1
      - socionext,uniphier-sd-v3.1.1

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  dmas:
    maxItems: 1

  dma-names:
    const: rx-tx

  reset-names:
    description: |
      There are three reset signals at maximum
        host:   mandatory for all variants
        bridge: exist only for version 2.91
        hw:     optional. exist if eMMC hw reset line is available
    oneOf:
      - const: host
      - items:
          - const: host
          - const: bridge
      - items:
          - const: host
          - const: hw
      - items:
          - const: host
          - const: bridge
          - const: hw

  resets:
    minItems: 1
    maxItems: 3

allOf:
  - $ref: mmc-controller.yaml

  - if:
      properties:
        compatible:
          contains:
            const: socionext,uniphier-sd-v2.91
    then:
      properties:
        reset-names:
          contains:
            const: bridge
    else:
      properties:
        reset-names:
          not:
            contains:
              const: bridge

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - reset-names
  - resets

unevaluatedProperties: false

examples:
  - |
    sd: mmc@5a400000 {
        compatible = "socionext,uniphier-sd-v2.91";
        reg = <0x5a400000 0x200>;
        interrupts = <0 76 4>;
        pinctrl-names = "default", "uhs";
        pinctrl-0 = <&pinctrl_sd>;
        pinctrl-1 = <&pinctrl_sd_uhs>;
        clocks = <&mio_clk 0>;
        reset-names = "host", "bridge";
        resets = <&mio_rst 0>, <&mio_rst 3>;
        dma-names = "rx-tx";
        dmas = <&dmac 4>;
        bus-width = <4>;
        cap-sd-highspeed;
        sd-uhs-sdr12;
        sd-uhs-sdr25;
        sd-uhs-sdr50;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Ltd. Co. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/sunplus,mmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sunplus MMC Controller

maintainers:
  - Tony Huang <tonyhuang.sunplus@gmail.com>
  - Li-hao Kuo <lhjeff911@gmail.com>

allOf:
  - $ref: "mmc-controller.yaml"

properties:
  compatible:
    enum:
      - sunplus,sp7021-mmc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    mmc0: mmc@9c003b00 {
        compatible = "sunplus,sp7021-mmc";
        reg = <0x9c003b00 0x180>;
        interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clkc 0x4e>;
        resets = <&rstc 0x3e>;
        bus-width = <8>;
        max-frequency = <52000000>;
        non-removable;
        disable-wp;
        cap-mmc-highspeed;
        mmc-ddr-3_3v;
        no-sdio;
        no-sd;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys Designware Mobile Storage Host Controller Common Properties

allOf:
  - $ref: "mmc-controller.yaml#"

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

# Everything else is described in the common file
properties:
  resets:
    maxItems: 1

  reset-names:
    const: reset

  clock-frequency:
    description:
      Should be the frequency (in Hz) of the ciu clock.  If this
      is specified and the ciu clock is specified then we'll try to set the ciu
      clock to this at probe time.

  fifo-depth:
    description:
      The maximum size of the tx/rx fifo's. If this property is not
      specified, the default value of the fifo size is determined from the
      controller registers.
    $ref: /schemas/types.yaml#/definitions/uint32

  card-detect-delay:
    description:
      Delay in milli-seconds before detecting card after card
      insert event. The default value is 0.
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

  data-addr:
    description:
      Override fifo address with value provided by DT. The default FIFO reg
      offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A)
      by driver. If the controller does not follow this rule, please use
      this property to set fifo address in device tree.
    $ref: /schemas/types.yaml#/definitions/uint32

  fifo-watermark-aligned:
    description:
      Data done irq is expected if data length is less than
      watermark in PIO mode. But fifo watermark is requested to be aligned
      with data length in some SoC so that TX/RX irq can be generated with
      data done irq. Add this watermark quirk to mark this requirement and
      force fifo watermark setting accordingly.
    $ref: /schemas/types.yaml#/definitions/flag

  dmas:
    maxItems: 1

  dma-names:
    const: rx-tx

additionalProperties: true


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys Designware Mobile Storage Host Controller Binding

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

# Everything else is described in the common file
properties:
  compatible:
    enum:
      - altr,socfpga-dw-mshc
      - img,pistachio-dw-mshc
      - snps,dw-mshc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 2
    description:
      Handle to "biu" and "ciu" clocks for the
      bus interface unit clock and the card interface unit clock.

  clock-names:
    items:
      - const: biu
      - const: ciu

  altr,sysmgr-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to the sysmgr node
          - description: register offset that controls the SDMMC clock phase
          - description: register shift for the smplsel(drive in) setting
    description:
      This property is optional. Contains the phandle to System Manager block
      that contains the SDMMC clock-phase control register. The first value is
      the pointer to the sysmgr, the 2nd value is the register offset for the
      SDMMC clock phase register, and the 3rd value is the bit shift for the
      smplsel(drive in) setting.

allOf:
  - $ref: synopsys-dw-mshc-common.yaml#

  - if:
      properties:
        compatible:
          contains:
            const: altr,socfpga-dw-mshc
    then:
      properties:
        altr,sysmgr-syscon: true
    else:
      properties:
        altr,sysmgr-syscon: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    mmc@12200000 {
      compatible = "snps,dw-mshc";
      reg = <0x12200000 0x1000>;
      interrupts = <0 75 0>;
      clocks = <&clock 351>, <&clock 132>;
      clock-names = "biu", "ciu";
      dmas = <&pdma 12>;
      dma-names = "rx-tx";
      resets = <&rst 20>;
      reset-names = "reset";
      vmmc-supply = <&buck8>;
      #address-cells = <1>;
      #size-cells = <0>;
      broken-cd;
      bus-width = <8>;
      cap-mmc-highspeed;
      cap-sd-highspeed;
      card-detect-delay = <200>;
      max-frequency = <200000000>;
      clock-frequency = <400000000>;
      data-addr = <0x200>;
      fifo-depth = <0x80>;
      fifo-watermark-aligned;
    };


code:
* TI Highspeed MMC host controller for OMAP and 66AK2G family.

The Highspeed MMC Host Controller on TI OMAP and 66AK2G family
provides an interface for MMC, SD, and SDIO types of memory cards.

This file documents differences between the core properties described
by mmc.txt and the properties used by the omap_hsmmc driver.

Required properties:
--------------------
- compatible:
 Should be "ti,omap2-hsmmc", for OMAP2 controllers
 Should be "ti,omap3-hsmmc", for OMAP3 controllers
 Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
 Should be "ti,omap4-hsmmc", for OMAP4 controllers
 Should be "ti,am33xx-hsmmc", for AM335x controllers
 Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.

SoC specific required properties:
---------------------------------
The following are mandatory properties for OMAPs, AM33xx and AM43xx SoCs only:
- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.

The following are mandatory properties for 66AK2G SoCs only:
- power-domains:Should contain a phandle to a PM domain provider node
		and an args specifier containing the MMC device id
		value. This property is as per the binding,
		Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
- clocks:	Must contain an entry for each entry in clock-names. Should
		be defined as per the he appropriate clock bindings consumer
		usage in Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
- clock-names:	Shall be "fck" for the functional clock,
		and "mmchsdb_fck" for the debounce clock.

Optional properties:
--------------------
- ti,dual-volt:		boolean, supports dual voltage cards
- <supply-name>-supply:	phandle to the regulator device tree node
			  "supply-name" examples are "vmmc",
			  "vmmc_aux"(deprecated)/"vqmmc" etc
- ti,non-removable:	non-removable slot (like eMMC)
- ti,needs-special-reset:	Requires a special softreset sequence
- ti,needs-special-hs-handling:	HSMMC IP needs special setting
				  for handling High Speed
- dmas:			List of DMA specifiers with the controller specific
			format as described in the generic DMA client
			binding. A tx and rx specifier is required.
- dma-names:		List of DMA request names. These strings correspond
			1:1 with the DMA specifiers listed in dmas.
			The string naming is to be "rx" and "tx" for
			RX and TX DMA requests, respectively.

Examples:

[hwmod populated DMA resources]

	mmc1: mmc@4809c000 {
		compatible = "ti,omap4-hsmmc";
		reg = <0x4809c000 0x400>;
		ti,hwmods = "mmc1";
		ti,dual-volt;
		bus-width = <4>;
		vmmc-supply = <&vmmc>; /* phandle to regulator node */
		ti,non-removable;
	};

[generic DMA request binding]

	mmc1: mmc@4809c000 {
		compatible = "ti,omap4-hsmmc";
		reg = <0x4809c000 0x400>;
		ti,hwmods = "mmc1";
		ti,dual-volt;
		bus-width = <4>;
		vmmc-supply = <&vmmc>; /* phandle to regulator node */
		ti,non-removable;
		dmas = <&edma 24
			&edma 25>;
		dma-names = "tx", "rx";
	};

[workaround for missing swakeup on am33xx]

This SOC is missing the swakeup line, it will not detect SDIO irq
while in suspend.

                             ------
                             | PRCM |
                              ------
                               ^ |
                       swakeup | | fclk
                               | v
       ------                -------               -----
      | card | -- CIRQ -->  | hsmmc | -- IRQ -->  | CPU |
       ------                -------               -----

In suspend the fclk is off and the module is disfunctional. Even register reads
will fail. A small logic in the host will request fclk restore, when an
external event is detected. Once the clock is restored, the host detects the
event normally. Since am33xx doesn't have this line it never wakes from
suspend.

The workaround is to reconfigure the dat1 line as a GPIO upon suspend. To make
this work, we need to set the named pinctrl states "default" and "idle".
Prepare idle to remux dat1 as a gpio, and default to remux it back as sdio
dat1. The MMC driver will then toggle between idle and default state during
runtime.

In summary:
1. select matching 'compatible' section, see example below.
2. specify pinctrl states "default" and "idle", "sleep" is optional.
3. specify the gpio irq used for detecting sdio irq in suspend

If configuration is incomplete, a warning message is emitted "falling back to
polling". Also check the "sdio irq mode" in /sys/kernel/debug/mmc0/regs. Mind
not every application needs SDIO irq, e.g. MMC cards.

	mmc1: mmc@48060100 {
		compatible = "ti,am33xx-hsmmc";
		...
		pinctrl-names = "default", "idle", "sleep"
		pinctrl-0 = <&mmc1_pins>;
		pinctrl-1 = <&mmc1_idle>;
		pinctrl-2 = <&mmc1_sleep>;
		...
		interrupts-extended = <&intc 64 &gpio2 28 IRQ_TYPE_LEVEL_LOW>;
	};

	mmc1_idle : pinmux_cirq_pin {
		pinctrl-single,pins = <
		        0x0f8 0x3f      /* GPIO2_28 */
		>;
	};


code:
* TI MMC host controller for OMAP1 and 2420

The MMC Host Controller on TI OMAP1 and 2420 family provides
an interface for MMC, SD, and SDIO types of memory cards.

This file documents differences between the core properties described
by mmc.txt and the properties used by the omap mmc driver.

Note that this driver will not work with omap2430 or later omaps,
please see the omap hsmmc driver for the current omaps.

Required properties:
- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
  instance starting 1

Examples:

	msdi1: mmc@4809c000 {
		compatible = "ti,omap2420-mmc";
		ti,hwmods = "msdi1";
		reg = <0x4809c000 0x80>;
		interrupts = <83>;
		dmas = <&sdma 61 &sdma 62>;
		dma-names = "tx", "rx";
	};


code:
* Renesas usdhi6rol0 SD/SDIO host controller

Required properties:

- compatible:	must be
		"renesas,usdhi6rol0"
- interrupts:	3 interrupts, named "card detect", "data" and "SDIO" must be
		specified
- clocks:	a clock binding for the IMCLK input

Optional properties:

- vmmc-supply:	a phandle of a regulator, supplying Vcc to the card
- vqmmc-supply:	a phandle of a regulator, supplying VccQ to the card
- pinctrl-names: Can contain a "default" entry and a "state_uhs"
                 entry. The state_uhs entry is used together with the default
                 entry when the board requires distinct settings for UHS speeds.

- pinctrl-N: One property for each name listed in pinctrl-names, see
             ../pinctrl/pinctrl-bindings.txt.

Additionally any standard mmc bindings from mmc.txt can be used.

Example:

sd0: sd@ab000000 {
	compatible = "renesas,usdhi6rol0";
	reg = <0xab000000 0x200>;
	interrupts = <0 23 0x4
		      0 24 0x4
		      0 25 0x4>;
	interrupt-names = "card detect", "data", "SDIO";
	bus-width = <4>;
	max-frequency = <50000000>;
	cap-power-off-card;
	clocks = <&imclk>;
	vmmc-supply = <&vcc_sd0>;
	vqmmc-supply = <&vccq_sd0>;
};


code:
* Wondermedia WM8505/WM8650 SD/MMC Host Controller

This file documents differences between the core properties described
by mmc.txt and the properties used by the wmt-sdmmc driver.

Required properties:
- compatible: Should be "wm,wm8505-sdhc".
- interrupts: Two interrupts are required - regular irq and dma irq.

Optional properties:
- sdon-inverted: SD_ON bit is inverted on the controller

Examples:

sdhc@d800a000 {
	compatible = "wm,wm8505-sdhc";
	reg = <0xd800a000 0x1000>;
	interrupts = <20 21>;
	clocks = <&sdhc>;
	bus-width = <4>;
	sdon-inverted;
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 NAND Controller

allOf:
  - $ref: "nand-controller.yaml"

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    enum:
      - allwinner,sun4i-a10-nand
      - allwinner,sun8i-a23-nand-controller
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Bus Clock
      - description: Module Clock

  clock-names:
    items:
      - const: ahb
      - const: mod

  resets:
    maxItems: 1

  reset-names:
    const: ahb

  dmas:
    maxItems: 1

  dma-names:
    const: rxtx

patternProperties:
  "^nand@[a-f0-9]$":
    type: object
    properties:
      reg:
        minimum: 0
        maximum: 7

      nand-ecc-mode: true

      nand-ecc-algo:
        const: bch

      nand-ecc-step-size:
        enum: [ 512, 1024 ]

      nand-ecc-strength:
        maximum: 80

      allwinner,rb:
        description:
          Contains the native Ready/Busy IDs.
        $ref: /schemas/types.yaml#/definitions/uint32-array
        minItems: 1
        maxItems: 2
        items:
          minimum: 0
          maximum: 1

    additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun6i-rtc.h>
    #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
    #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>

    nand-controller@1c03000 {
        compatible = "allwinner,sun8i-a23-nand-controller";
        reg = <0x01c03000 0x1000>;
        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
        clock-names = "ahb", "mod";
        resets = <&ccu RST_BUS_NAND>;
        reset-names = "ahb";
        dmas = <&dma 5>;
        dma-names = "rxtx";
        pinctrl-names = "default";
        pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
        #address-cells = <1>;
        #size-cells = <0>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/amlogic,meson-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs

allOf:
  - $ref: nand-controller.yaml

maintainers:
  - liang.yang@amlogic.com

properties:
  compatible:
    enum:
      - amlogic,meson-gxl-nfc
      - amlogic,meson-axg-nfc

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: nfc
      - const: emmc

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2

  clock-names:
    items:
      - const: core
      - const: device

patternProperties:
  "^nand@[0-7]$":
    type: object
    properties:
      reg:
        minimum: 0
        maximum: 1

      nand-ecc-mode:
        const: hw

      nand-ecc-step-size:
        const: 1024

      nand-ecc-strength:
        enum: [8, 16, 24, 30, 40, 50, 60]
        description: |
          The ECC configurations that can be supported are as follows.
            meson-gxl-nfc 8, 16, 24, 30, 40, 50, 60
            meson-axg-nfc 8

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/axg-clkc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    nand-controller@ffe07800 {
      compatible = "amlogic,meson-axg-nfc";
      reg = <0xffe07800 0x100>, <0xffe07000 0x800>;
      reg-names = "nfc", "emmc";
      interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
      clocks = <&clkc CLKID_SD_EMMC_C>,  <&clkc CLKID_FCLK_DIV2>;
      clock-names = "core", "device";

      pinctrl-0 = <&nand_pins>;
      pinctrl-names = "default";

      #address-cells = <1>;
      #size-cells = <0>;

      nand@0 {
        reg = <0>;
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/arasan,nand-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arasan NAND Flash Controller with ONFI 3.1 support

allOf:
  - $ref: "nand-controller.yaml"

maintainers:
  - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>

properties:
  compatible:
    items:
      - enum:
          - xlnx,zynqmp-nand-controller
      - const: arasan,nfc-v3p10

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Controller clock
      - description: NAND bus clock

  clock-names:
    items:
      - const: controller
      - const: bus

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts

unevaluatedProperties: true

examples:
  - |
    nfc: nand-controller@ff100000 {
        compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
        reg = <0xff100000 0x1000>;
        clock-names = "controller", "bus";
        clocks = <&clk200>, <&clk100>;
        interrupt-parent = <&gic>;
        interrupts = <0 14 4>;
        #address-cells = <1>;
        #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/arm,pl353-nand-r2p1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PL353 NAND Controller

allOf:
  - $ref: "nand-controller.yaml"

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>
  - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>

properties:
  compatible:
    items:
      - const: arm,pl353-nand-r2p1

  reg:
    items:
      - items:
          - description: CS with regard to the parent ranges property
          - description: Offset of the memory region requested by the device
          - description: Length of the memory region requested by the device

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    smcc: memory-controller@e000e000 {
        compatible = "arm,pl353-smc-r2p1", "arm,primecell";
        reg = <0xe000e000 0x0001000>;
        clock-names = "memclk", "apb_pclk";
        clocks = <&clkc 11>, <&clkc 44>;
        ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
                  0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
                  0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
        #address-cells = <2>;
        #size-cells = <1>;

        nfc0: nand-controller@0,0 {
            compatible = "arm,pl353-nand-r2p1";
            reg = <0 0 0x1000000>;
            #address-cells = <1>;
            #size-cells = <0>;
        };
    };


code:
* Atmel Data Flash

Required properties:
- compatible : "atmel,<model>", "atmel,<series>", "atmel,dataflash".

The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.

Example:

flash@1 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
	spi-max-frequency = <25000000>;
	reg = <1>;
};


code:
Atmel NAND flash controller bindings

The NAND flash controller node should be defined under the EBI bus (see
Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
One or several NAND devices can be defined under this NAND controller.
The NAND controller might be connected to an ECC engine.

* NAND controller bindings:

Required properties:
- compatible: should be one of the following
	"atmel,at91rm9200-nand-controller"
	"atmel,at91sam9260-nand-controller"
	"atmel,at91sam9261-nand-controller"
	"atmel,at91sam9g45-nand-controller"
	"atmel,sama5d3-nand-controller"
	"microchip,sam9x60-nand-controller"
- ranges: empty ranges property to forward EBI ranges definitions.
- #address-cells: should be set to 2.
- #size-cells: should be set to 1.
- atmel,nfc-io: phandle to the NFC IO block. Only required for sama5d3
		controllers.
- atmel,nfc-sram: phandle to the NFC SRAM block. Only required for sama5d3
		  controllers.

Optional properties:
- ecc-engine: phandle to the PMECC block. Only meaningful if the SoC embeds
	      a PMECC engine.

* NAND device/chip bindings:

Required properties:
- reg: describes the CS lines assigned to the NAND device. If the NAND device
       exposes multiple CS lines (multi-dies chips), your reg property will
       contain X tuples of 3 entries.
       1st entry: the CS line this NAND chip is connected to
       2nd entry: the base offset of the memory region assigned to this
		  device (always 0)
       3rd entry: the memory region size (always 0x800000)

Optional properties:
- rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
- cs-gpios: the GPIO(s) used to control the CS line.
- det-gpios: the GPIO used to detect if a Smartmedia Card is present.
- atmel,rb: an integer identifying the native Ready/Busy pin. Only meaningful
	    on sama5 SoCs.

All generic properties are described in the generic yaml files under
Documentation/devicetree/bindings/mtd/.

* ECC engine (PMECC) bindings:

Required properties:
- compatible: should be one of the following
	"atmel,at91sam9g45-pmecc"
	"atmel,sama5d4-pmecc"
	"atmel,sama5d2-pmecc"
	"microchip,sam9x60-pmecc"
- reg: should contain 2 register ranges. The first one is pointing to the PMECC
       block, and the second one to the PMECC_ERRLOC block.

* SAMA5 NFC I/O bindings:

SAMA5 SoCs embed an advanced NAND controller logic to automate READ/WRITE page
operations. This interface to this logic is placed in a separate I/O range and
should thus have its own DT node.

- compatible: should be "atmel,sama5d3-nfc-io", "syscon".
- reg: should contain the I/O range used to interact with the NFC logic.

Example:

	nfc_io: nfc-io@70000000 {
		compatible = "atmel,sama5d3-nfc-io", "syscon";
		reg = <0x70000000 0x8000000>;
	};

	pmecc: ecc-engine@ffffc070 {
		compatible = "atmel,at91sam9g45-pmecc";
                reg = <0xffffc070 0x490>,
                      <0xffffc500 0x100>;
	};

	ebi: ebi@10000000 {
		compatible = "atmel,sama5d3-ebi";
		#address-cells = <2>;
		#size-cells = <1>;
		atmel,smc = <&hsmc>;
		reg = <0x10000000 0x10000000
		       0x40000000 0x30000000>;
		ranges = <0x0 0x0 0x10000000 0x10000000
			  0x1 0x0 0x40000000 0x10000000
			  0x2 0x0 0x50000000 0x10000000
			  0x3 0x0 0x60000000 0x10000000>;
		clocks = <&mck>;

                nand_controller: nand-controller {
			compatible = "atmel,sama5d3-nand-controller";
			atmel,nfc-sram = <&nfc_sram>;
			atmel,nfc-io = <&nfc_io>;
			ecc-engine = <&pmecc>;
			#address-cells = <2>;
			#size-cells = <1>;
			ranges;

			nand@3 {
				reg = <0x3 0x0 0x800000>;
				atmel,rb = <0>;

				/*
				 * Put generic NAND/MTD properties and
				 * subnodes here.
				 */
			};
		};
	};

-----------------------------------------------------------------------

Deprecated bindings (should not be used in new device trees):

Required properties:
- compatible: The possible values are:
	"atmel,at91rm9200-nand"
	"atmel,sama5d2-nand"
	"atmel,sama5d4-nand"
- reg : should specify localbus address and size used for the chip,
	and hardware ECC controller if available.
	If the hardware ECC is PMECC, it should contain address and size for
	PMECC and PMECC Error Location controller.
	The PMECC lookup table address and size in ROM is optional. If not
	specified, driver will build it in runtime.
- atmel,nand-addr-offset : offset for the address latch.
- atmel,nand-cmd-offset : offset for the command latch.
- #address-cells, #size-cells : Must be present if the device has sub-nodes
  representing partitions.

- gpios : specifies the gpio pins to control the NAND device. detect is an
  optional gpio and may be set to 0 if not present.

Optional properties:
- atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
  Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
  "soft_bch".
- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
  capable of BCH encoding and decoding, on devices where it is present.
- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
  Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
  is "atmel,sama5d2-nand", 32 is also valid.
- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
  are: 512, 1024.
- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
  for different sector size. First one is for sector size 512, the next is for
  sector size 1024. If not specified, driver will build the table in runtime.
- nand-bus-width : 8 or 16 bus width if not present 8
- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false

Nand Flash Controller(NFC) is an optional sub-node
Required properties:
- compatible : "atmel,sama5d3-nfc".
- reg : should specify the address and size used for NFC command registers,
        NFC registers and NFC SRAM. NFC SRAM address and size can be absent
        if don't want to use it.
- clocks: phandle to the peripheral clock
Optional properties:
- atmel,write-by-sram: boolean to enable NFC write by SRAM.

Examples:
nand0: nand@40000000,0 {
	compatible = "atmel,at91rm9200-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x40000000 0x10000000
	       0xffffe800 0x200
	      >;
	atmel,nand-addr-offset = <21>;	/* ale */
	atmel,nand-cmd-offset = <22>;	/* cle */
	nand-on-flash-bbt;
	nand-ecc-mode = "soft";
	gpios = <&pioC 13 0	/* rdy */
		 &pioC 14 0 	/* nce */
		 0		/* cd */
		>;
	partition@0 {
		...
	};
};

/* for PMECC supported chips */
nand0: nand@40000000 {
	compatible = "atmel,at91rm9200-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = < 0x40000000 0x10000000	/* bus addr & size */
		0xffffe000 0x00000600	/* PMECC addr & size */
		0xffffe600 0x00000200	/* PMECC ERRLOC addr & size */
		0x00100000 0x00100000	/* ROM addr & size */
		>;
	atmel,nand-addr-offset = <21>;	/* ale */
	atmel,nand-cmd-offset = <22>;	/* cle */
	nand-on-flash-bbt;
	nand-ecc-mode = "hw";
	atmel,has-pmecc;	/* enable PMECC */
	atmel,pmecc-cap = <2>;
	atmel,pmecc-sector-size = <512>;
	atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
	gpios = <&pioD 5 0	/* rdy */
		 &pioD 4 0	/* nce */
		 0		/* cd */
		>;
	partition@0 {
		...
	};
};

/* for NFC supported chips */
nand0: nand@40000000 {
	compatible = "atmel,at91rm9200-nand";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
        ...
        nfc@70000000 {
		compatible = "atmel,sama5d3-nfc";
		#address-cells = <1>;
		#size-cells = <1>;
		clocks = <&hsmc_clk>
		reg = <
			0x70000000 0x10000000	/* NFC Command Registers */
			0xffffc000 0x00000070	/* NFC HSMC regs */
			0x00200000 0x00100000	/* NFC SRAM banks */
		>;
	};
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/brcm,brcmnand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom STB NAND Controller

maintainers:
  - Brian Norris <computersforpeace@gmail.com>
  - Kamal Dasu <kdasu.kdev@gmail.com>

description: |
  The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
  flash chips. It has a memory-mapped register interface for both control
  registers and for its data input/output buffer. On some SoCs, this controller
  is paired with a custom DMA engine (inventively named "Flash DMA") which
  supports basic PROGRAM and READ functions, among other features.

  This controller was originally designed for STB SoCs (BCM7xxx) but is now
  available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
  iProc/Cygnus. Its history includes several similar (but not fully register
  compatible) versions.

  -- Additional SoC-specific NAND controller properties --

  The NAND controller is integrated differently on the variety of SoCs on which
  it is found. Part of this integration involves providing status and enable
  bits with which to control the 8 exposed NAND interrupts, as well as hardware
  for configuring the endianness of the data bus. On some SoCs, these features
  are handled via standard, modular components (e.g., their interrupts look like
  a normal IRQ chip), but on others, they are controlled in unique and
  interesting ways, sometimes with registers that lump multiple NAND-related
  functions together. The former case can be described simply by the standard
  interrupts properties in the main controller node. But for the latter
  exceptional cases, we define additional 'compatible' properties and associated
  register resources within the NAND controller node above.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - brcm,brcmnand-v2.1
              - brcm,brcmnand-v2.2
              - brcm,brcmnand-v4.0
              - brcm,brcmnand-v5.0
              - brcm,brcmnand-v6.0
              - brcm,brcmnand-v6.1
              - brcm,brcmnand-v6.2
              - brcm,brcmnand-v7.0
              - brcm,brcmnand-v7.1
              - brcm,brcmnand-v7.2
              - brcm,brcmnand-v7.3
          - const: brcm,brcmnand
      - description: BCM63138 SoC-specific NAND controller
        items:
          - const: brcm,nand-bcm63138
          - enum:
              - brcm,brcmnand-v7.0
              - brcm,brcmnand-v7.1
          - const: brcm,brcmnand
      - description: iProc SoC-specific NAND controller
        items:
          - const: brcm,nand-iproc
          - const: brcm,brcmnand-v6.1
          - const: brcm,brcmnand
      - description: BCM63168 SoC-specific NAND controller
        items:
          - const: brcm,nand-bcm63168
          - const: brcm,nand-bcm6368
          - const: brcm,brcmnand-v4.0
          - const: brcm,brcmnand

  reg:
    minItems: 1
    maxItems: 6

  reg-names:
    minItems: 1
    maxItems: 6
    items:
      enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ]

  interrupts:
    minItems: 1
    items:
      - description: NAND CTLRDY interrupt
      - description: FLASH_DMA_DONE (if flash DMA is available) or FLASH_EDU_DONE (if EDU is available)

  interrupt-names:
    minItems: 1
    items:
      - const: nand_ctlrdy
      - enum:
          - flash_dma_done
          - flash_edu_done

  clocks:
    maxItems: 1
    description: reference to the clock for the NAND controller

  clock-names:
    const: nand

  brcm,nand-has-wp:
    description: >
      Some versions of this IP include a write-protect
      (WP) control bit. It is always available on >=
      v7.0. Use this property to describe the rare
      earlier versions of this core that include WP
    type: boolean

patternProperties:
  "^nand@[a-f0-9]$":
    type: object
    properties:
      compatible:
        const: brcm,nandcs

      nand-ecc-step-size:
        enum: [ 512, 1024 ]

      brcm,nand-oob-sector-size:
        description: |
          integer, to denote the spare area sector size
          expected for the ECC layout in use. This size, in
          addition to the strength and step-size,
          determines how the hardware BCH engine will lay
          out the parity bytes it stores on the flash.
          This property can be automatically determined by
          the flash geometry (particularly the NAND page
          and OOB size) in many cases, but when booting
          from NAND, the boot controller has only a limited
          number of available options for its default ECC
          layout.
        $ref: /schemas/types.yaml#/definitions/uint32

allOf:
  - $ref: nand-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: brcm,nand-bcm63138
    then:
      properties:
        reg-names:
          items:
            - const: nand
            - const: nand-int-base
  - if:
      properties:
        compatible:
          contains:
            const: brcm,nand-bcm6368
    then:
      properties:
        reg-names:
          items:
            - const: nand
            - const: nand-int-base
            - const: nand-cache
  - if:
      properties:
        compatible:
          contains:
            const: brcm,nand-iproc
    then:
      properties:
        reg-names:
          items:
            - const: nand
            - const: iproc-idm
            - const: iproc-ext
  - if:
      properties:
        interrupts:
          minItems: 2
    then:
      required:
        - interrupt-names

unevaluatedProperties: false

required:
  - reg
  - reg-names
  - interrupts

examples:
  - |
    nand-controller@f0442800 {
        compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
        reg = <0xf0442800 0x600>,
              <0xf0443000 0x100>;
        reg-names = "nand", "flash-dma";
        interrupt-parent = <&hif_intr2_intc>;
        interrupts = <24>, <4>;
        interrupt-names = "nand_ctlrdy", "flash_dma_done";

        #address-cells = <1>;
        #size-cells = <0>;

        nand@1 {
            compatible = "brcm,nandcs";
            reg = <1>; // Chip select 1
            nand-on-flash-bbt;
            nand-ecc-strength = <12>;
            nand-ecc-step-size = <512>;

            #address-cells = <1>;
            #size-cells = <1>;
        };
    };
  - |
    nand-controller@10000200 {
        compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
                     "brcm,brcmnand-v4.0", "brcm,brcmnand";
        reg = <0x10000200 0x180>,
              <0x100000b0 0x10>,
              <0x10000600 0x200>;
        reg-names = "nand", "nand-int-base", "nand-cache";
        interrupt-parent = <&periph_intc>;
        interrupts = <50>;
        clocks = <&periph_clk 20>;
        clock-names = "nand";

        #address-cells = <1>;
        #size-cells = <0>;

        nand@0 {
            compatible = "brcm,nandcs";
            reg = <0>;
            nand-on-flash-bbt;
            nand-ecc-strength = <1>;
            nand-ecc-step-size = <512>;

            #address-cells = <1>;
            #size-cells = <1>;
        };
    };


code:
* Cadence NAND controller

Required properties:
  - compatible : "cdns,hp-nfc"
  - reg : Contains two entries, each of which is a tuple consisting of a
	  physical address and length. The first entry is the address and
	  length of the controller register set. The second entry is the
	  address and length of the Slave DMA data port.
  - reg-names: should contain "reg" and "sdma"
  - #address-cells: should be 1. The cell encodes the chip select connection.
  - #size-cells : should be 0.
  - interrupts : The interrupt number.
  - clocks: phandle of the controller core clock (nf_clk).

Optional properties:
  - dmas: shall reference DMA channel associated to the NAND controller
  - cdns,board-delay-ps : Estimated Board delay. The value includes the total
    round trip delay for the signals and is used for deciding on values
    associated with data read capture. The example formula for SDR mode is
    the following:
    board delay = RE#PAD delay + PCB trace to device + PCB trace from device
    + DQ PAD delay

Child nodes represent the available NAND chips.

Required properties of NAND chips:
  - reg: shall contain the native Chip Select ids from 0 to max supported by
    the cadence nand flash controller

See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
generic bindings.

Example:

nand_controller: nand-controller@60000000 {
	  compatible = "cdns,hp-nfc";
	  #address-cells = <1>;
	  #size-cells = <0>;
	  reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
	  reg-names = "reg", "sdma";
	  clocks = <&nf_clk>;
	  cdns,board-delay-ps = <4830>;
	  interrupts = <2 0>;
	  nand@0 {
	      reg = <0>;
	      label = "nand-1";
	  };
	  nand@1 {
	      reg = <1>;
	      label = "nand-2";
	  };

};


code:
Device tree bindings for Texas instruments Davinci/Keystone NAND controller

This file provides information, what the device node for the davinci/keystone
NAND interface contains.

Documentation:
Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf

Required properties:

- compatible:			"ti,davinci-nand"
				"ti,keystone-nand"

- reg:				Contains 2 offset/length values:
				- offset and length for the access window.
				- offset and length for accessing the AEMIF
				control registers.

- ti,davinci-chipselect:	number of chipselect. Indicates on the
				davinci_nand driver which chipselect is used
				for accessing the nand.
				Can be in the range [0-3].

Recommended properties :

- ti,davinci-mask-ale:		mask for ALE. Needed for executing address
				phase. These offset will be added to the base
				address for the chip select space the NAND Flash
				device is connected to.
				If not set equal to 0x08.

- ti,davinci-mask-cle:		mask for CLE. Needed for executing command
				phase. These offset will be added to the base
				address for the chip select space the NAND Flash
				device is connected to.
				If not set equal to 0x10.

- ti,davinci-mask-chipsel:	mask for chipselect address. Needed to mask
				addresses for given chipselect.

- nand-ecc-mode:		operation mode of the NAND ecc mode. ECC mode
				valid values for davinci driver:
				- "none"
				- "soft"
				- "hw"

- ti,davinci-ecc-bits:		used ECC bits, currently supported 1 or 4.

- nand-bus-width:		buswidth 8 or 16. If not present 8.

- nand-on-flash-bbt:		use flash based bad block table support. OOB
				identifier is saved in OOB area. If not present
				false.

Deprecated properties:

- ti,davinci-ecc-mode:		operation mode of the NAND ecc mode. ECC mode
				valid values for davinci driver:
				- "none"
				- "soft"
				- "hw"

- ti,davinci-nand-buswidth:	buswidth 8 or 16. If not present 8.

- ti,davinci-nand-use-bbt:	use flash based bad block table support. OOB
				identifier is saved in OOB area. If not present
				false.

Nand device bindings may contain additional sub-nodes describing partitions of
the address space. See partition.txt for more detail. The NAND Flash timing
values must be programmed in the chip select’s node of AEMIF
memory-controller (see Documentation/devicetree/bindings/memory-controllers/
davinci-aemif.txt).

Example(da850 EVM ):

nand_cs3@62000000 {
	compatible = "ti,davinci-nand";
	reg = <0x62000000 0x807ff
	       0x68000000 0x8000>;
	ti,davinci-chipselect = <1>;
	ti,davinci-mask-ale = <0>;
	ti,davinci-mask-cle = <0>;
	ti,davinci-mask-chipsel = <0>;
	nand-ecc-mode = "hw";
	ti,davinci-ecc-bits = <4>;
	nand-on-flash-bbt;

	partition@180000 {
		label = "ubifs";
		reg = <0x180000 0x7e80000>;
	};
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/denali,nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Denali NAND controller

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

properties:
  compatible:
    enum:
      - altr,socfpga-denali-nand
      - socionext,uniphier-denali-nand-v5a
      - socionext,uniphier-denali-nand-v5b

  reg-names:
    description: |
      There are two register regions:
        nand_data:  host data/command interface
        denali_reg: register interface
    items:
      - const: nand_data
      - const: denali_reg

  reg:
    minItems: 2
    maxItems: 2

  interrupts:
    maxItems: 1

  clock-names:
    description: |
      There are three clocks:
        nand:   controller core clock
        nand_x: bus interface clock
        ecc:    ECC circuit clock
    items:
      - const: nand
      - const: nand_x
      - const: ecc

  clocks:
    minItems: 3
    maxItems: 3

  reset-names:
    description: |
      There are two optional resets:
        nand: controller core reset
        reg:  register reset
    oneOf:
      - items:
          - const: nand
          - const: reg
      - const: nand
      - const: reg

  resets:
    minItems: 1
    maxItems: 2

allOf:
  - $ref: nand-controller.yaml

  - if:
      properties:
        compatible:
          contains:
            const: altr,socfpga-denali-nand
    then:
      patternProperties:
        "^nand@[a-f0-9]$":
          type: object
          properties:
            nand-ecc-strength:
              enum:
                - 8
                - 15
            nand-ecc-step-size:
              enum:
                - 512

  - if:
      properties:
        compatible:
          contains:
            const: socionext,uniphier-denali-nand-v5a
    then:
      patternProperties:
        "^nand@[a-f0-9]$":
          type: object
          properties:
            nand-ecc-strength:
              enum:
                - 8
                - 16
                - 24
            nand-ecc-step-size:
              enum:
                - 1024

  - if:
      properties:
        compatible:
          contains:
            const: socionext,uniphier-denali-nand-v5b
    then:
      patternProperties:
        "^nand@[a-f0-9]$":
          type: object
          properties:
            nand-ecc-strength:
              enum:
                - 8
                - 16
            nand-ecc-step-size:
              enum:
                - 1024

required:
  - compatible
  - reg
  - interrupts
  - clock-names
  - clocks

unevaluatedProperties: false

examples:
  - |
    nand-controller@ff900000 {
        compatible = "altr,socfpga-denali-nand";
        reg-names = "nand_data", "denali_reg";
        reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
        interrupts = <0 144 4>;
        clock-names = "nand", "nand_x", "ecc";
        clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
        reset-names = "nand", "reg";
        resets = <&nand_rst>, <&nand_reg_rst>;
        #address-cells = <1>;
        #size-cells = <0>;

        nand@0 {
            reg = <0>;
        };
    };


code:
M-Systems and Sandisk DiskOnChip devices

M-System DiskOnChip G3
======================
The Sandisk (formerly M-Systems) docg3 is a nand device of 64M to 256MB.

Required properties:
 - compatible: should be "m-systems,diskonchip-g3"
 - reg: register base and size

Example:
	docg3: flash@0 {
		compatible = "m-systems,diskonchip-g3";
		reg = <0x0 0x2000>;
	};


code:
FLCTL NAND controller

Required properties:
- compatible : "renesas,shmobile-flctl-sh7372"
- reg : Address range of the FLCTL
- interrupts : flste IRQ number
- nand-bus-width : bus width to NAND chip

Optional properties:
- dmas: DMA specifier(s)
- dma-names: name for each DMA specifier. Valid names are
	     "data_tx", "data_rx", "ecc_tx", "ecc_rx"

The DMA fields are not used yet in the driver but are listed here for
completing the bindings.

The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.

Example:

	flctl@e6a30000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "renesas,shmobile-flctl-sh7372";
		reg = <0xe6a30000 0x100>;
		interrupts = <0x0d80>;

		nand-bus-width = <16>;

		dmas = <&dmac 1 /* data_tx */
			&dmac 2;> /* data_rx */
		dma-names = "data_tx", "data_rx";

		system@0 {
			label = "system";
			reg = <0x0 0x8000000>;
		};

		userdata@8000000 {
			label = "userdata";
			reg = <0x8000000 0x10000000>;
		};

		cache@18000000 {
			label = "cache";
			reg = <0x18000000 0x8000000>;
		};
	};


code:
Freescale Localbus UPM programmed to work with NAND flash

Required properties:
- compatible : "fsl,upm-nand".
- reg : should specify localbus chip select and size used for the chip.
- fsl,upm-addr-offset : UPM pattern offset for the address latch.
- fsl,upm-cmd-offset : UPM pattern offset for the command latch.

Optional properties:
- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
	The corresponding address lines are used to select the chip.
- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
	(R/B#). For multi-chip devices, "n" GPIO definitions are required
	according to the number of chips.

Deprecated properties:
- fsl,upm-wait-flags : add chip-dependent short delays after running the
	UPM pattern (0x1), after writing a data byte (0x2) or after
	writing out a buffer (0x4).
- chip-delay : chip dependent delay for transferring data from array to
	read registers (tR). Required if property "gpios" is not used
	(R/B# pins not connected).

Each flash chip described may optionally contain additional sub-nodes
describing partitions of the address space. See partition.txt for more
detail.

Examples:

upm@1,0 {
	compatible = "fsl,upm-nand";
	reg = <1 0 1>;
	fsl,upm-addr-offset = <16>;
	fsl,upm-cmd-offset = <8>;
	gpios = <&qe_pio_e 18 0>;

	flash {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "...";

		partition@0 {
			...
		};
	};
};

upm@3,0 {
	#address-cells = <0>;
	#size-cells = <0>;
	compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
	reg = <3 0x0 0x800>;
	fsl,upm-addr-offset = <0x10>;
	fsl,upm-cmd-offset = <0x08>;
	/* Multi-chip NAND device */
	fsl,upm-addr-line-cs-offsets = <0x0 0x200>;

	nand@0 {
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			    label = "fs";
			    reg = <0x00000000 0x10000000>;
		};
	};
};


code:
ST Microelectronics Flexible Static Memory Controller (FSMC)
NAND Interface

Required properties:
- compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
- reg : Address range of the mtd chip
- reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"

Optional properties:
- bank-width : Width (in bytes) of the device.  If not present, the width
  defaults to 1 byte
- nand-skip-bbtscan: Indicates the BBT scanning should be skipped
- timings: array of 6 bytes for NAND timings. The meanings of these bytes
  are:
  byte 0 TCLR  : CLE to RE delay in number of AHB clock cycles, only 4 bits
                 are valid. Zero means one clockcycle, 15 means 16 clock
                 cycles.
  byte 1 TAR   : ALE to RE delay, 4 bits are valid. Same format as TCLR.
  byte 2 THIZ  : number of HCLK clock cycles during which the data bus is
                 kept in Hi-Z (tristate) after the start of a write access.
                 Only valid for write transactions. Zero means zero cycles,
                 255 means 255 cycles.
  byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
                 when writing) after the command deassertation. Zero means
                 one cycle, 255 means 256 cycles.
  byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
                 NAND flash in response to SMWAITn. Zero means 1 cycle,
                 255 means 256 cycles.
  byte 5 TSET  : number of HCLK clock cycles to assert the address before the
                 command is asserted. Zero means one cycle, 255 means 256
                 cycles.
- bank: default NAND bank to use (0-3 are valid, 0 is the default).
- nand-ecc-mode      : see nand-controller.yaml
- nand-ecc-strength  : see nand-controller.yaml
- nand-ecc-step-size : see nand-controller.yaml

Can support 1-bit HW ECC (default) or if stronger correction is required,
software-based BCH.

Example:

	fsmc: flash@d1800000 {
		compatible = "st,spear600-fsmc-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0xd1800000 0x1000	/* FSMC Register */
		       0xd2000000 0x0010	/* NAND Base DATA */
		       0xd2020000 0x0010	/* NAND Base ADDR */
		       0xd2010000 0x0010>;	/* NAND Base CMD */
		reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";

		bank-width = <1>;
		nand-skip-bbtscan;
		timings = /bits/ 8 <0 0 0 2 3 0>;
		bank = <1>;

		partition@0 {
			...
		};
	};


code:
GPIO assisted NAND flash

The GPIO assisted NAND flash uses a memory mapped interface to
read/write the NAND commands and data and GPIO pins for the control
signals.

Required properties:
- compatible : "gpio-control-nand"
- reg : should specify localbus chip select and size used for the chip.  The
  resource describes the data bus connected to the NAND flash and all accesses
  are made in native endianness.
- #address-cells, #size-cells : Must be present if the device has sub-nodes
  representing partitions.
- gpios : Specifies the GPIO pins to control the NAND device.  The order of
  GPIO references is:  RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional.

Optional properties:
- bank-width : Width (in bytes) of the device.  If not present, the width
  defaults to 1 byte.
- chip-delay : chip dependent delay for transferring data from array to
  read registers (tR).  If not present then a default of 20us is used.
- gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
  location used to guard against bus reordering with regards to accesses to
  the GPIO's and the NAND flash data bus.  If present, then after changing
  GPIO state and before and after command byte writes, this register will be
  read to ensure that the GPIO accesses have completed.

The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.

Examples:

gpio-nand@1,0 {
	compatible = "gpio-control-nand";
	reg = <1 0x0000 0x2>;
	#address-cells = <1>;
	#size-cells = <1>;
	gpios = <&banka 1 0>,	/* RDY */
		<0>, 		/* nCE */
		<&banka 3 0>, 	/* ALE */
		<&banka 4 0>, 	/* CLE */
		<0>;		/* nWP */

	partition@0 {
	...
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale General-Purpose Media Interface (GPMI) binding

maintainers:
  - Han Xu <han.xu@nxp.com>

description: |
  The GPMI nand controller provides an interface to control the NAND
  flash chips. The device tree may optionally contain sub-nodes
  describing partitions of the address space. See partition.txt for
  more detail.

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx23-gpmi-nand
          - fsl,imx28-gpmi-nand
          - fsl,imx6q-gpmi-nand
          - fsl,imx6sx-gpmi-nand
          - fsl,imx7d-gpmi-nand
      - items:
          - enum:
              - fsl,imx8mm-gpmi-nand
              - fsl,imx8mn-gpmi-nand
          - const: fsl,imx7d-gpmi-nand

  reg:
    items:
      - description: Address and length of gpmi block.
      - description: Address and length of bch block.

  reg-names:
    items:
      - const: gpmi-nand
      - const: bch

  interrupts:
    maxItems: 1

  interrupt-names:
    const: bch

  dmas:
    maxItems: 1

  dma-names:
    const: rx-tx

  clocks:
    minItems: 1
    maxItems: 5

  clock-names:
    minItems: 1
    maxItems: 5

  fsl,use-minimum-ecc:
    type: boolean
    description: |
      Protect this NAND flash with the minimum ECC strength required.
      The required ECC strength is automatically discoverable for some
      flash (e.g., according to the ONFI standard). However, note that
      if this strength is not discoverable or this property is not enabled,
      the software may chooses an implementation-defined ECC scheme.

  fsl,no-blockmark-swap:
    type: boolean
    description: |
      Don't swap the bad block marker from the OOB area with the byte in
      the data area but rely on the flash based BBT for identifying bad blocks.
      NOTE: this is only valid in conjunction with 'nand-on-flash-bbt'.
      WARNING: on i.MX28 blockmark swapping cannot be disabled for the BootROM
      in the FCB. Thus, partitions written from Linux with this feature turned
      on may not be accessible by the BootROM code.

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - dmas
  - dma-names

unevaluatedProperties: false

allOf:
  - $ref: "nand-controller.yaml"

  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,imx23-gpmi-nand
              - fsl,imx28-gpmi-nand
    then:
      properties:
        clocks:
          items:
            - description: SoC gpmi io clock
        clock-names:
          items:
            - const: gpmi_io

  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,imx6q-gpmi-nand
              - fsl,imx6sx-gpmi-nand
    then:
      properties:
        clocks:
          items:
            - description: SoC gpmi io clock
            - description: SoC gpmi apb clock
            - description: SoC gpmi bch clock
            - description: SoC gpmi bch apb clock
            - description: SoC per1 bch clock
        clock-names:
          items:
            - const: gpmi_io
            - const: gpmi_apb
            - const: gpmi_bch
            - const: gpmi_bch_apb
            - const: per1_bch

  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx7d-gpmi-nand
    then:
      properties:
        clocks:
          items:
            - description: SoC gpmi io clock
            - description: SoC gpmi bch apb clock
        clock-names:
          items:
            - const: gpmi_io
            - const: gpmi_bch_apb

examples:
  - |
    nand-controller@8000c000 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "fsl,imx28-gpmi-nand";
        reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
        reg-names = "gpmi-nand", "bch";
        interrupts = <41>;
        interrupt-names = "bch";
        clocks = <&clks 50>;
        clock-names = "gpmi_io";
        dmas = <&dma_apbh 4>;
        dma-names = "rx-tx";
    };


code:
Hisilicon Hip04 Soc NAND controller DT binding

Required properties:

- compatible:          Should be "hisilicon,504-nfc".
- reg:                 The first contains base physical address and size of
                       NAND controller's registers. The second contains base
                       physical address and size of NAND controller's buffer.
- interrupts:          Interrupt number for nfc.
- nand-bus-width:      See nand-controller.yaml.
- nand-ecc-mode:       Support none and hw ecc mode.
- #address-cells:      Partition address, should be set 1.
- #size-cells:         Partition size, should be set 1.

Optional properties:

- nand-ecc-strength:   Number of bits to correct per ECC step.
- nand-ecc-step-size:  Number of data bytes covered by a single ECC step.

The following ECC strength and step size are currently supported:

 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>

Flash chip may optionally contain additional sub-nodes describing partitions of
the address space. See partition.txt for more detail.

Example:

	nand: nand@4020000 {
		compatible = "hisilicon,504-nfc";
		reg = <0x4020000 0x10000>, <0x5000000 0x1000>;
		interrupts = <0 379 4>;
		nand-bus-width = <8>;
		nand-ecc-mode = "hw";
		nand-ecc-strength = <16>;
		nand-ecc-step-size = <1024>;
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "nand_text";
			reg = <0x00000000 0x00400000>;
		};

		...

	};