code:
# SPDX-License-Identifier: (GPL-2.0)
# Copyright 2020 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/thermal-zones.yaml#
$schema: http://devicetree.org/meta-schemas/base.yaml#

title: Thermal zone binding

maintainers:
  - Amit Kucheria <amitk@kernel.org>

description: |
  Thermal management is achieved in devicetree by describing the sensor hardware
  and the software abstraction of cooling devices and thermal zones required to
  take appropriate action to mitigate thermal overloads.

  The following node types are used to completely describe a thermal management
  system in devicetree:
   - thermal-sensor: device that measures temperature, has SoC-specific bindings
   - cooling-device: device used to dissipate heat either passively or actively
   - thermal-zones: a container of the following node types used to describe all
     thermal data for the platform

  This binding describes the thermal-zones.

  The polling-delay properties of a thermal-zone are bound to the maximum dT/dt
  (temperature derivative over time) in two situations for a thermal zone:
    1. when passive cooling is activated (polling-delay-passive)
    2. when the zone just needs to be monitored (polling-delay) or when
       active cooling is activated.

  The maximum dT/dt is highly bound to hardware power consumption and
  dissipation capability. The delays should be chosen to account for said
  max dT/dt, such that a device does not cross several trip boundaries
  unexpectedly between polls. Choosing the right polling delays shall avoid
  having the device in temperature ranges that may damage the silicon structures
  and reduce silicon lifetime.

properties:
  $nodename:
    const: thermal-zones
    description:
      A /thermal-zones node is required in order to use the thermal framework to
      manage input from the various thermal zones in the system in order to
      mitigate thermal overload conditions. It does not represent a real device
      in the system, but acts as a container to link a thermal sensor device,
      platform-data regarding temperature thresholds and the mitigation actions
      to take when the temperature crosses those thresholds.

patternProperties:
  "^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$":
    type: object
    description:
      Each thermal zone node contains information about how frequently it
      must be checked, the sensor responsible for reporting temperature for
      this zone, one sub-node containing the various trip points for this
      zone and one sub-node containing all the zone cooling-maps.

    properties:
      polling-delay:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          The maximum number of milliseconds to wait between polls when
          checking this thermal zone. Setting this to 0 disables the polling
          timers setup by the thermal framework and assumes that the thermal
          sensors in this zone support interrupts.

      polling-delay-passive:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          The maximum number of milliseconds to wait between polls when
          checking this thermal zone while doing passive cooling. Setting
          this to 0 disables the polling timers setup by the thermal
          framework and assumes that the thermal sensors in this zone
          support interrupts.

      thermal-sensors:
        $ref: /schemas/types.yaml#/definitions/phandle-array
        maxItems: 1
        description:
          The thermal sensor phandle and sensor specifier used to monitor this
          thermal zone.

      coefficients:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        description:
          An array of integers containing the coefficients of a linear equation
          that binds all the sensors listed in this thermal zone.

          The linear equation used is as follows,
            z = c0 * x0 + c1 * x1 + ... + c(n-1) * x(n-1) + cn
          where c0, c1, .., cn are the coefficients.

          Coefficients default to 1 in case this property is not specified. The
          coefficients are ordered and are matched with sensors by means of the
          sensor ID. Additional coefficients are interpreted as constant offset.

      sustainable-power:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          An estimate of the sustainable power (in mW) that this thermal zone
          can dissipate at the desired control temperature. For reference, the
          sustainable power of a 4-inch phone is typically 2000mW, while on a
          10-inch tablet is around 4500mW.

      trips:
        type: object
        description:
          This node describes a set of points in the temperature domain at
          which the thermal framework needs to take action. The actions to
          be taken are defined in another node called cooling-maps.

        patternProperties:
          "^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$":
            type: object

            properties:
              temperature:
                $ref: /schemas/types.yaml#/definitions/int32
                minimum: -273000
                maximum: 200000
                description:
                  An integer expressing the trip temperature in millicelsius.

              hysteresis:
                $ref: /schemas/types.yaml#/definitions/uint32
                description:
                  An unsigned integer expressing the hysteresis delta with
                  respect to the trip temperature property above, also in
                  millicelsius. Any cooling action initiated by the framework is
                  maintained until the temperature falls below
                  (trip temperature - hysteresis). This potentially prevents a
                  situation where the trip gets constantly triggered soon after
                  cooling action is removed.

              type:
                $ref: /schemas/types.yaml#/definitions/string
                enum:
                  - active   # enable active cooling e.g. fans
                  - passive  # enable passive cooling e.g. throttling cpu
                  - hot      # send notification to driver
                  - critical # send notification to driver, trigger shutdown
                description: |
                  There are four valid trip types: active, passive, hot,
                  critical.

                  The critical trip type is used to set the maximum
                  temperature threshold above which the HW becomes
                  unstable and underlying firmware might even trigger a
                  reboot. Hitting the critical threshold triggers a system
                  shutdown.

                  The hot trip type can be used to send a notification to
                  the thermal driver (if a .notify callback is registered).
                  The action to be taken is left to the driver.

                  The passive trip type can be used to slow down HW e.g. run
                  the CPU, GPU, bus at a lower frequency.

                  The active trip type can be used to control other HW to
                  help in cooling e.g. fans can be sped up or slowed down

            required:
              - temperature
              - hysteresis
              - type
            additionalProperties: false

        additionalProperties: false

      cooling-maps:
        type: object
        description:
          This node describes the action to be taken when a thermal zone
          crosses one of the temperature thresholds described in the trips
          node. The action takes the form of a mapping relation between a
          trip and the target cooling device state.

        patternProperties:
          "^map[-a-zA-Z0-9]*$":
            type: object

            properties:
              trip:
                $ref: /schemas/types.yaml#/definitions/phandle
                description:
                  A phandle of a trip point node within this thermal zone.

              cooling-device:
                $ref: /schemas/types.yaml#/definitions/phandle-array
                description:
                  A list of cooling device phandles along with the minimum
                  and maximum cooling state specifiers for each cooling
                  device. Using the THERMAL_NO_LIMIT (-1UL) constant in the
                  cooling-device phandle limit specifier lets the framework
                  use the minimum and maximum cooling state for that cooling
                  device automatically.

              contribution:
                $ref: /schemas/types.yaml#/definitions/uint32
                description:
                  The cooling contribution to the thermal zone of the referred
                  cooling device at the referred trip point. The contribution is
                  a ratio of the sum of all cooling contributions within a
                  thermal zone.

            required:
              - trip
              - cooling-device
            additionalProperties: false

    required:
      - polling-delay
      - polling-delay-passive
      - thermal-sensors
      - trips

    additionalProperties: false

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/thermal/thermal.h>

    // Example 1: SDM845 TSENS
    soc {
            #address-cells = <2>;
            #size-cells = <2>;

            /* ... */

            tsens0: thermal-sensor@c263000 {
                    compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
                    reg = <0 0x0c263000 0 0x1ff>, /* TM */
                          <0 0x0c222000 0 0x1ff>; /* SROT */
                    #qcom,sensors = <13>;
                    interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
                                 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
                    interrupt-names = "uplow", "critical";
                    #thermal-sensor-cells = <1>;
            };

            tsens1: thermal-sensor@c265000 {
                    compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
                    reg = <0 0x0c265000 0 0x1ff>, /* TM */
                          <0 0x0c223000 0 0x1ff>; /* SROT */
                    #qcom,sensors = <8>;
                    interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
                                 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
                    interrupt-names = "uplow", "critical";
                    #thermal-sensor-cells = <1>;
            };
    };

    /* ... */

    thermal-zones {
            cpu0-thermal {
                    polling-delay-passive = <250>;
                    polling-delay = <1000>;

                    thermal-sensors = <&tsens0 1>;

                    trips {
                            cpu0_alert0: trip-point0 {
                                    temperature = <90000>;
                                    hysteresis = <2000>;
                                    type = "passive";
                            };

                            cpu0_alert1: trip-point1 {
                                    temperature = <95000>;
                                    hysteresis = <2000>;
                                    type = "passive";
                            };

                            cpu0_crit: cpu_crit {
                                    temperature = <110000>;
                                    hysteresis = <1000>;
                                    type = "critical";
                            };
                    };

                    cooling-maps {
                            map0 {
                                    trip = <&cpu0_alert0>;
                                    /* Corresponds to 1400MHz in OPP table */
                                    cooling-device = <&CPU0 3 3>, <&CPU1 3 3>,
                                                     <&CPU2 3 3>, <&CPU3 3 3>;
                            };

                            map1 {
                                    trip = <&cpu0_alert1>;
                                    /* Corresponds to 1000MHz in OPP table */
                                    cooling-device = <&CPU0 5 5>, <&CPU1 5 5>,
                                                     <&CPU2 5 5>, <&CPU3 5 5>;
                            };
                    };
            };

            /* ... */

            cluster0-thermal {
                    polling-delay-passive = <250>;
                    polling-delay = <1000>;

                    thermal-sensors = <&tsens0 5>;

                    trips {
                            cluster0_alert0: trip-point0 {
                                    temperature = <90000>;
                                    hysteresis = <2000>;
                                    type = "hot";
                            };
                            cluster0_crit: cluster0_crit {
                                    temperature = <110000>;
                                    hysteresis = <2000>;
                                    type = "critical";
                            };
                    };
            };

            /* ... */

            gpu-top-thermal {
                    polling-delay-passive = <250>;
                    polling-delay = <1000>;

                    thermal-sensors = <&tsens0 11>;

                    trips {
                            gpu1_alert0: trip-point0 {
                                    temperature = <90000>;
                                    hysteresis = <2000>;
                                    type = "hot";
                            };
                    };
            };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/ti,am654-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments AM654 VTM (DTS) binding

maintainers:
  - Keerthy <j-keerthy@ti.com>

properties:
  compatible:
    const: ti,am654-vtm

  reg:
    maxItems: 1

  power-domains:
    maxItems: 1

  "#thermal-sensor-cells":
    const: 1

required:
  - compatible
  - reg
  - power-domains
  - "#thermal-sensor-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/soc/ti,sci_pm_domain.h>
    vtm: thermal@42050000 {
        compatible = "ti,am654-vtm";
        reg = <0x42050000 0x25c>;
        power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
        #thermal-sensor-cells = <1>;
    };

    mpu0_thermal: mpu0_thermal {
        polling-delay-passive = <250>; /* milliseconds */
        polling-delay = <500>; /* milliseconds */
        thermal-sensors = <&vtm0 0>;

        trips {
                mpu0_crit: mpu0_crit {
                        temperature = <125000>; /* milliCelsius */
                        hysteresis = <2000>; /* milliCelsius */
                        type = "critical";
                };
        };
    };
...

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/ti,j72xx-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments J72XX VTM (DTS) binding

maintainers:
  - Keerthy <j-keerthy@ti.com>

description: |
  The TI K3 family of SoCs typically have a Voltage & Thermal
  Management (VTM) device to control up to 8 temperature diode
  sensors to measure silicon junction temperatures from different
  hotspots of the chip as well as provide temperature, interrupt
  and alerting information.

  The following polynomial equation can then be used to convert
  value returned by this device into a temperature in Celsius

  Temp(C) = (-9.2627e-12) * x^4 + (6.0373e-08) * x^3 + \
            (-1.7058e-04) * x^2 + (3.2512e-01) * x   + (-4.9003e+01)

properties:
  compatible:
    enum:
      - ti,j721e-vtm
      - ti,j7200-vtm

  reg:
    items:
      - description: VTM cfg1 register space
      - description: VTM cfg2 register space
      - description: |
          A software trimming method must be applied to some Jacinto
          devices to function properly. This eFuse region provides
          the information needed for these SoCs to report
          temperatures accurately.
    minItems: 2

  power-domains:
    maxItems: 1

  "#thermal-sensor-cells":
    const: 1

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: ti,j721e-vtm
    then:
      properties:
        reg:
          minItems: 3
    else:
      properties:
        reg:
          maxItems: 2

required:
  - compatible
  - reg
  - power-domains
  - "#thermal-sensor-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/soc/ti,sci_pm_domain.h>
    wkup_vtm0: thermal-sensor@42040000 {
        compatible = "ti,j721e-vtm";
        reg = <0x42040000 0x350>,
              <0x42050000 0x350>,
              <0x43000300 0x10>;
        power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
        #thermal-sensor-cells = <1>;
    };

    mpu_thermal: mpu-thermal {
        polling-delay-passive = <250>; /* milliseconds */
        polling-delay = <500>; /* milliseconds */
        thermal-sensors = <&wkup_vtm0 0>;

        trips {
            mpu_crit: mpu-crit {
                temperature = <125000>; /* milliCelsius */
                hysteresis = <2000>; /* milliCelsius */
                type = "critical";
            };
        };
    };
...


code:
* Texas Instrument OMAP SCM bandgap bindings

In the System Control Module, OMAP supplies a voltage reference
and a temperature sensor feature that are gathered in the band
gap voltage and temperature sensor (VBGAPTS) module. The band
gap provides current and voltage reference for its internal
circuits and other analog IP blocks. The analog-to-digital
converter (ADC) produces an output value that is proportional
to the silicon temperature.

Required properties:
- compatible : Should be:
  - "ti,omap34xx-bandgap" : for OMAP34xx bandgap
  - "ti,omap36xx-bandgap" : for OMAP36xx bandgap
  - "ti,omap4430-bandgap" : for OMAP4430 bandgap
  - "ti,omap4460-bandgap" : for OMAP4460 bandgap
  - "ti,omap4470-bandgap" : for OMAP4470 bandgap
  - "ti,omap5430-bandgap" : for OMAP5430 bandgap
- interrupts : this entry should indicate which interrupt line
the talert signal is routed to;
Specific:
- gpios : this entry should be used to inform which GPIO
line the tshut signal is routed to. The informed GPIO will
be treated as an IRQ;
- regs : this entry must also be specified and it is specific
to each bandgap version, because the mapping may change from
soc to soc, apart of depending on available features.

Example:
OMAP34xx:
bandgap {
	reg = <0x48002524 0x4>;
	compatible = "ti,omap34xx-bandgap";
};

OMAP36xx:
bandgap {
	reg = <0x48002524 0x4>;
	compatible = "ti,omap36xx-bandgap";
};

OMAP4430:
bandgap {
	reg = <0x4a002260 0x4 0x4a00232C 0x4>;
	compatible = "ti,omap4430-bandgap";
};

OMAP4460:
bandgap {
	reg = <0x4a002260 0x4
		0x4a00232C 0x4
		0x4a002378 0x18>;
	compatible = "ti,omap4460-bandgap";
	interrupts = <0 126 4>; /* talert */
	gpios = <&gpio3 22 0>; /* tshut */
};

OMAP4470:
bandgap {
	reg = <0x4a002260 0x4
		0x4a00232C 0x4
		0x4a002378 0x18>;
	compatible = "ti,omap4470-bandgap";
	interrupts = <0 126 4>; /* talert */
	gpios = <&gpio3 22 0>; /* tshut */
};

OMAP5430:
bandgap {
	reg = <0x4a0021e0 0xc
		0x4a00232c 0xc
		0x4a002380 0x2c
		0x4a0023C0 0x3c>;
	compatible = "ti,omap5430-bandgap";
	interrupts = <0 126 4>; /* talert */
};

DRA752:
bandgap {
	reg = <0x4a0021e0 0xc
		0x4a00232c 0xc
		0x4a002380 0x2c
		0x4a0023C0 0x3c
		0x4a002564 0x8
		0x4a002574 0x50>;
	compatible = "ti,dra752-bandgap";
	interrupts = <0 126 4>; /* talert */
};


code:
Actions Semi Owl Timer

Required properties:
- compatible      :  "actions,s500-timer" for S500
                     "actions,s700-timer" for S700
                     "actions,s900-timer" for S900
- reg             :  Offset and length of the register set for the device.
- interrupts      :  Should contain the interrupts.
- interrupt-names :  Valid names are: "2hz0", "2hz1",
                                      "timer0", "timer1", "timer2", "timer3"
                     See ../resource-names.txt

Example:

		timer@b0168000 {
			compatible = "actions,s500-timer";
			reg = <0xb0168000 0x100>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
			             <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "timer0", "timer1";
		};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/allwinner,sun4i-a10-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 Timer

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    oneOf:
      - enum:
          - allwinner,sun4i-a10-timer
          - allwinner,sun8i-a23-timer
          - allwinner,sun8i-v3s-timer
          - allwinner,suniv-f1c100s-timer
      - items:
          - enum:
              - allwinner,sun20i-d1-timer
              - allwinner,sun50i-a64-timer
              - allwinner,sun50i-h6-timer
              - allwinner,sun50i-h616-timer
          - const: allwinner,sun8i-a23-timer

  reg:
    maxItems: 1

  interrupts:
    minItems: 2
    maxItems: 6
    description:
      List of timers interrupts

  clocks:
    maxItems: 1

allOf:
  - if:
      properties:
        compatible:
          enum:
            - allwinner,sun4i-a10-timer

    then:
      properties:
        interrupts:
          minItems: 6
          maxItems: 6

  - if:
      properties:
        compatible:
          enum:
            - allwinner,sun8i-a23-timer

    then:
      properties:
        interrupts:
          minItems: 2
          maxItems: 2

  - if:
      properties:
        compatible:
          enum:
            - allwinner,sun8i-v3s-timer
            - allwinner,suniv-f1c100s-timer

    then:
      properties:
        interrupts:
          minItems: 3
          maxItems: 3

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    timer@1c20c00 {
        compatible = "allwinner,sun4i-a10-timer";
        reg = <0x01c20c00 0x400>;
        interrupts = <22>,
                     <23>,
                     <24>,
                     <25>,
                     <67>,
                     <68>;
        clocks = <&osc>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/allwinner,sun5i-a13-hstimer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A13 High-Speed Timer

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    oneOf:
      - const: allwinner,sun5i-a13-hstimer
      - const: allwinner,sun7i-a20-hstimer
      - items:
          - const: allwinner,sun6i-a31-hstimer
          - const: allwinner,sun7i-a20-hstimer

  reg:
    maxItems: 1

  interrupts:
    minItems: 2
    items:
      - description: Timer 0 Interrupt
      - description: Timer 1 Interrupt
      - description: Timer 2 Interrupt
      - description: Timer 3 Interrupt

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

if:
  properties:
    compatible:
      const: allwinner,sun5i-a13-hstimer

then:
  properties:
    interrupts:
      minItems: 2
      maxItems: 2

else:
  properties:
    interrupts:
      minItems: 4
      maxItems: 4

additionalProperties: false

examples:
  - |
    timer@1c60000 {
        compatible = "allwinner,sun7i-a20-hstimer";
        reg = <0x01c60000 0x1000>;
        interrupts = <0 51 1>,
                     <0 52 1>,
                     <0 53 1>,
                     <0 54 1>;
        clocks = <&ahb1_gates 19>;
        resets = <&ahb1rst 19>;
    };

...


code:
Altera Timer

Required properties:

- compatible : should be "altr,timer-1.0"
- reg : Specifies base physical address and size of the registers.
- interrupts : Should contain the timer interrupt number
- clock-frequency : The frequency of the clock that drives the counter, in Hz.

Example:

timer {
	compatible = "altr,timer-1.0";
	reg = <0x00400000 0x00000020>;
	interrupt-parent = <&cpu>;
	interrupts = <11>;
	clock-frequency = <125000000>;
};


code:
Amlogic Meson6 SoCs Timer Controller

Required properties:

- compatible : should be "amlogic,meson6-timer"
- reg : Specifies base physical address and size of the registers.
- interrupts : The four interrupts, one for each timer event
- clocks : phandles to the pclk (system clock) and XTAL clocks
- clock-names : must contain "pclk" and "xtal"

Example:

timer@c1109940 {
	compatible = "amlogic,meson6-timer";
	reg = <0xc1109940 0x14>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
		     <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
		     <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
		     <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
	clocks = <&xtal>, <&clk81>;
	clock-names = "xtal", "pclk";
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM architected timer

maintainers:
  - Marc Zyngier <marc.zyngier@arm.com>
  - Mark Rutland <mark.rutland@arm.com>
description: |+
  ARM cores may have a per-core architected timer, which provides per-cpu timers,
  or a memory mapped architected timer, which provides up to 8 frames with a
  physical and optional virtual timer per frame.

  The per-core architected timer is attached to a GIC to deliver its
  per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
  to deliver its interrupts via SPIs.

properties:
  compatible:
    oneOf:
      - items:
          - const: arm,cortex-a15-timer
          - const: arm,armv7-timer
      - items:
          - enum:
              - arm,armv7-timer
              - arm,armv8-timer
      - items:
          - const: arm,armv8-timer
          - const: arm,armv7-timer

  interrupts:
    minItems: 1
    items:
      - description: secure timer irq
      - description: non-secure timer irq
      - description: virtual timer irq
      - description: hypervisor timer irq
      - description: hypervisor virtual timer irq

  interrupt-names:
    oneOf:
      - minItems: 2
        items:
          - const: phys
          - const: virt
          - const: hyp-phys
          - const: hyp-virt
      - minItems: 3
        items:
          - const: sec-phys
          - const: phys
          - const: virt
          - const: hyp-phys
          - const: hyp-virt

  clock-frequency:
    description: The frequency of the main counter, in Hz. Should be present
      only where necessary to work around broken firmware which does not configure
      CNTFRQ on all CPUs to a uniform correct value. Use of this property is
      strongly discouraged; fix your firmware unless absolutely impossible.

  always-on:
    type: boolean
    description: If present, the timer is powered through an always-on power
      domain, therefore it never loses context.

  allwinner,erratum-unknown1:
    type: boolean
    description: Indicates the presence of an erratum found in Allwinner SoCs,
      where reading certain values from the counter is unreliable. This also
      affects writes to the tval register, due to the implicit counter read.

  fsl,erratum-a008585:
    type: boolean
    description: Indicates the presence of QorIQ erratum A-008585, which says
      that reading the counter is unreliable unless the same value is returned
      by back-to-back reads. This also affects writes to the tval register, due
      to the implicit counter read.

  hisilicon,erratum-161010101:
    type: boolean
    description: Indicates the presence of Hisilicon erratum 161010101, which
      says that reading the counters is unreliable in some cases, and reads may
      return a value 32 beyond the correct value. This also affects writes to
      the tval registers, due to the implicit counter read.

  arm,cpu-registers-not-fw-configured:
    type: boolean
    description: Firmware does not initialize any of the generic timer CPU
      registers, which contain their architecturally-defined reset values. Only
      supported for 32-bit systems which follow the ARMv7 architected reset
      values.

  arm,no-tick-in-suspend:
    type: boolean
    description: The main counter does not tick when the system is in
      low-power system suspend on some SoCs. This behavior does not match the
      Architecture Reference Manual's specification that the system counter "must
      be implemented in an always-on power domain."

required:
  - compatible

additionalProperties: false

oneOf:
  - required:
      - interrupts
  - required:
      - interrupts-extended

examples:
  - |
    timer {
      compatible = "arm,cortex-a15-timer",
             "arm,armv7-timer";
      interrupts = <1 13 0xf08>,
             <1 14 0xf08>,
             <1 11 0xf08>,
             <1 10 0xf08>;
      clock-frequency = <100000000>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM memory mapped architected timer

maintainers:
  - Marc Zyngier <marc.zyngier@arm.com>
  - Mark Rutland <mark.rutland@arm.com>

description: |+
  ARM cores may have a memory mapped architected timer, which provides up to 8
  frames with a physical and optional virtual timer per frame.

  The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.

properties:
  compatible:
    items:
      - enum:
          - arm,armv7-timer-mem

  reg:
    maxItems: 1
    description: The control frame base address

  '#address-cells':
    enum: [1, 2]

  '#size-cells':
    const: 1

  ranges: true

  clock-frequency:
    description: The frequency of the main counter, in Hz. Should be present
      only where necessary to work around broken firmware which does not configure
      CNTFRQ on all CPUs to a uniform correct value. Use of this property is
      strongly discouraged; fix your firmware unless absolutely impossible.

  always-on:
    type: boolean
    description: If present, the timer is powered through an always-on power
      domain, therefore it never loses context.

  arm,cpu-registers-not-fw-configured:
    type: boolean
    description: Firmware does not initialize any of the generic timer CPU
      registers, which contain their architecturally-defined reset values. Only
      supported for 32-bit systems which follow the ARMv7 architected reset
      values.

  arm,no-tick-in-suspend:
    type: boolean
    description: The main counter does not tick when the system is in
      low-power system suspend on some SoCs. This behavior does not match the
      Architecture Reference Manual's specification that the system counter "must
      be implemented in an always-on power domain."

patternProperties:
  '^frame@[0-9a-z]*$':
    type: object
    additionalProperties: false
    description: A timer node has up to 8 frame sub-nodes, each with the following properties.
    properties:
      frame-number:
        $ref: "/schemas/types.yaml#/definitions/uint32"
        minimum: 0
        maximum: 7

      interrupts:
        minItems: 1
        items:
          - description: physical timer irq
          - description: virtual timer irq

      reg:
        minItems: 1
        items:
          - description: 1st view base address
          - description: 2nd optional view base address

    required:
      - frame-number
      - interrupts
      - reg

required:
  - compatible
  - reg
  - '#address-cells'
  - '#size-cells'

additionalProperties: false

examples:
  - |
    timer@f0000000 {
      compatible = "arm,armv7-timer-mem";
      #address-cells = <1>;
      #size-cells = <1>;
      ranges = <0 0xf0001000 0x1000>;
      reg = <0xf0000000 0x1000>;
      clock-frequency = <50000000>;

      frame@0 {
        frame-number = <0>;
        interrupts = <0 13 0x8>,
               <0 14 0x8>;
        reg = <0x0000 0x1000>,
              <0x1000 0x1000>;
      };

      frame@2000 {
        frame-number = <1>;
        interrupts = <0 15 0x8>;
        reg = <0x2000 0x1000>;
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/arm,armv7m-systick.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARMv7M System Timer

maintainers:
  - Alexandre Torgue <alexandre.torgue@foss.st.com>
  - Fabrice Gasnier <fabrice.gasnier@foss.st.com>

description: ARMv7-M includes a system timer, known as SysTick.

properties:
  compatible:
    const: arm,armv7m-systick

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-frequency: true

oneOf:
  - required:
      - clocks
  - required:
      - clock-frequency

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    timer@e000e010 {
        compatible = "arm,armv7m-systick";
        reg = <0xe000e010 0x10>;
        clocks = <&clk_systick>;
    };

  - |
    timer@e000e010 {
        compatible = "arm,armv7m-systick";
        reg = <0xe000e010 0x10>;
        clock-frequency = <90000000>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/arm,global_timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Global Timer

maintainers:
  - Stuart Menefy <stuart.menefy@st.com>

description:
  Cortex-A9 are often associated with a per-core Global timer.

properties:
  compatible:
    items:
      - enum:
          - arm,cortex-a5-global-timer
          - arm,cortex-a9-global-timer

    description: driver supports versions r2p0 and above.

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    timer@2c000600 {
      compatible = "arm,cortex-a9-global-timer";
      reg = <0x2c000600 0x20>;
      interrupts = <1 13 0xf01>;
      clocks = <&arm_periph_clk>;
    };
...


code:
ARM MPS2 timer

The MPS2 platform has simple general-purpose 32 bits timers.

Required properties:
- compatible	: Should be "arm,mps2-timer"
- reg		: Address and length of the register set
- interrupts	: Reference to the timer interrupt

Required clocking property, have to be one of:
- clocks	  : The input clock of the timer
- clock-frequency : The rate in HZ in input of the ARM MPS2 timer

Examples:

timer1: mps2-timer@40000000 {
	compatible = "arm,mps2-timer";
	reg = <0x40000000 0x1000>;
	interrupts = <8>;
	clocks = <&sysclk>;
};

timer2: mps2-timer@40001000 {
	compatible = "arm,mps2-timer";
	reg = <0x40001000 0x1000>;
	interrupts = <9>;
	clock-frequency = <25000000>;
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM sp804 Dual Timers

maintainers:
  - Haojian Zhuang <haojian.zhuang@linaro.org>

description: |+
  The Arm SP804 IP implements two independent timers, configurable for
  16 or 32 bit operation and capable of running in one-shot, periodic, or
  free-running mode. The input clock is shared, but can be gated and prescaled
  independently for each timer.

  There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
  SoCs, such as Hi1212, should use the dedicated compatible: "hisilicon,sp804".

# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
  properties:
    compatible:
      contains:
        enum:
          - arm,sp804
          - hisilicon,sp804
  required:
    - compatible

properties:
  compatible:
    items:
      - enum:
          - arm,sp804
          - hisilicon,sp804
      - const: arm,primecell

  interrupts:
    description: |
      If two interrupts are listed, those are the interrupts for timer
      1 and 2, respectively. If there is only a single interrupt, it is
      either a combined interrupt or the sole interrupt of one timer, as
      specified by the "arm,sp804-has-irq" property.
    minItems: 1
    maxItems: 2

  reg:
    description: The physical base address of the SP804 IP.
    maxItems: 1

  clocks:
    description: |
      Clocks driving the dual timer hardware. This list should
      be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
      clock, apb_pclk. A single clock can also be specified if the same
      clock is used for all clock inputs.
    oneOf:
      - items:
          - description: clock for timer 1
          - description: clock for timer 2
          - description: bus clock
      - items:
          - description: unified clock for both timers and the bus

  clock-names: true
    # The original binding did not specify any clock names, and there is no
    # consistent naming used in the existing DTs. The primecell binding
    # requires the "apb_pclk" name, so we need this property.
    # Use "timer0clk", "timer1clk", "apb_pclk" for new DTs.

  arm,sp804-has-irq:
    description: If only one interrupt line is connected to the interrupt
      controller, this property specifies which timer is connected to this
      line.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 2

required:
  - compatible
  - interrupts
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    timer0: timer@fc800000 {
        compatible = "arm,sp804", "arm,primecell";
        reg = <0xfc800000 0x1000>;
        interrupts = <0 0 4>, <0 1 4>;
        clocks = <&timclk1>, <&timclk2>, <&pclk>;
        clock-names = "timer1", "timer2", "apb_pclk";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Timer-Watchdog Timer

maintainers:
  - Rob Herring <robh@kernel.org>

description:
  ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
  Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
  and watchdog.

  The TWD is usually attached to a GIC to deliver its two per-processor
  interrupts.

properties:
  compatible:
    enum:
      - arm,cortex-a9-twd-timer
      - arm,cortex-a5-twd-timer
      - arm,arm11mp-twd-timer

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  always-on:
    description:
      If present, the timer is powered through an always-on power domain,
      therefore it never loses context.

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    timer@2c000600 {
            compatible = "arm,arm11mp-twd-timer";
            reg = <0x2c000600 0x20>;
            interrupts = <GIC_PPI 13 0xf01>;
    };


code:
BCM2835 System Timer

The System Timer peripheral provides four 32-bit timer channels and a
single 64-bit free running counter. Each channel has an output compare
register, which is compared against the 32 least significant bits of the
free running counter values, and generates an interrupt.

Required properties:

- compatible : should be "brcm,bcm2835-system-timer"
- reg : Specifies base physical address and size of the registers.
- interrupts : A list of 4 interrupt sinks; one per timer channel.
- clock-frequency : The frequency of the clock that drives the counter, in Hz.

Example:

timer {
	compatible = "brcm,bcm2835-system-timer";
	reg = <0x7e003000 0x1000>;
	interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
	clock-frequency = <1000000>;
};


code:
Broadcom Kona Family timer
-----------------------------------------------------
This timer is used in the following Broadcom SoCs:
 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155

Required properties:
- compatible : "brcm,kona-timer"
- DEPRECATED: compatible : "bcm,kona-timer"
- reg : Register range for the timer
- interrupts : interrupt for the timer
- clocks: phandle + clock specifier pair of the external clock
- clock-frequency: frequency that the clock operates

Only one of clocks or clock-frequency should be specified.

Refer to clocks/clock-bindings.txt for generic clock consumer properties.

Example:
	timer@35006000 {
		compatible = "brcm,kona-timer";
		reg = <0x35006000 0x1000>;
		interrupts = <0x0 7 0x4>;
		clocks = <&hub_timer_clk>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/cdns,ttc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence TTC - Triple Timer Counter

maintainers:
  - Michal Simek <michal.simek@xilinx.com>

properties:
  compatible:
    const: cdns,ttc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 3
    description: |
      A list of 3 interrupts; one per timer channel.

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  timer-width:
    $ref: "/schemas/types.yaml#/definitions/uint32"
    description: |
      Bit width of the timer, necessary if not 16.

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    ttc0: ttc0@f8001000 {
        interrupt-parent = <&intc>;
        interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
        compatible = "cdns,ttc";
        reg = <0xF8001000 0x1000>;
        clocks = <&cpu_clk 3>;
        timer-width = <32>;
    };


code:
* Cirrus Logic CLPS711X Timer Counter

Required properties:
- compatible: Shall contain "cirrus,ep7209-timer".
- reg       : Address and length of the register set.
- interrupts: The interrupt number of the timer.
- clocks    : phandle of timer reference clock.

Note: Each timer should have an alias correctly numbered in "aliases" node.

Example:
	aliases {
		timer0 = &timer1;
		timer1 = &timer2;
	};

	timer1: timer@80000300 {
		compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
		reg = <0x80000300 0x4>;
		interrupts = <8>;
		clocks = <&clks 5>;
	};

	timer2: timer@80000340 {
		compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
		reg = <0x80000340 0x4>;
		interrupts = <9>;
		clocks = <&clks 6>;
	};


code:
=================
gx6605s SOC Timer
=================

The timer is used in gx6605s soc as system timer and the driver
contain clk event and clk source.

==============================
timer node bindings definition
==============================

	Description: Describes gx6605s SOC timer

	PROPERTIES

	- compatible
		Usage: required
		Value type: <string>
		Definition: must be "csky,gx6605s-timer"
	- reg
		Usage: required
		Value type: <u32 u32>
		Definition: <phyaddr size> in soc from cpu view
	- clocks
		Usage: required
		Value type: phandle + clock specifier cells
		Definition: must be input clk node
	- interrupt
		Usage: required
		Value type: <u32>
		Definition: must be timer irq num defined by soc

Examples:
---------

	timer0: timer@20a000 {
		compatible = "csky,gx6605s-timer";
		reg = <0x0020a000 0x400>;
		clocks = <&dummy_apb_clk>;
		interrupts = <10>;
		interrupt-parent = <&intc>;
	};


code:
============================
C-SKY Multi-processors Timer
============================

C-SKY multi-processors timer is designed for C-SKY SMP system and the
regs is accessed by cpu co-processor 4 registers with mtcr/mfcr.

 - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer.
 - PTIM_TSR  "cr<1, 14>" Interrupt cleanup status reg.
 - PTIM_CCVR "cr<3, 14>" Current counter value reg.
 - PTIM_LVR  "cr<6, 14>" Window value reg to trigger next event.

==============================
timer node bindings definition
==============================

	Description: Describes SMP timer

	PROPERTIES

	- compatible
		Usage: required
		Value type: <string>
		Definition: must be "csky,mptimer"
	- clocks
		Usage: required
		Value type: <node>
		Definition: must be input clk node
	- interrupts
		Usage: required
		Value type: <u32>
		Definition: must be timer irq num defined by soc

Examples:
---------

	timer: timer {
		compatible = "csky,mptimer";
		clocks = <&dummy_apb_clk>;
		interrupts = <16>;
		interrupt-parent = <&intc>;
	};


code:
Conexant Digicolor SoCs Timer Controller

Required properties:

- compatible : should be "cnxt,cx92755-timer"
- reg : Specifies base physical address and size of the "Agent Communication"
  timer registers
- interrupts : Contains 8 interrupts, one for each timer
- clocks: phandle to the main clock

Example:

	timer@f0000fc0 {
		compatible = "cnxt,cx92755-timer";
		reg = <0xf0000fc0 0x40>;
		interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>;
		clocks = <&main_clk>;
	};


code:
NPS Network Processor

Required properties:

- compatible :	should be "ezchip,nps400-timer0"

Clocks required for compatible = "ezchip,nps400-timer0":
- interrupts : The interrupt of the first timer
- clocks : Must contain a single entry describing the clock input

Example:

timer {
	compatible = "ezchip,nps400-timer0";
	interrupts = <3>;
	clocks = <&sysclk>;
};


code:
NPS Network Processor

Required properties:

- compatible :	should be "ezchip,nps400-timer1"

Clocks required for compatible = "ezchip,nps400-timer1":
- clocks : Must contain a single entry describing the clock input

Example:

timer {
	compatible = "ezchip,nps400-timer1";
	clocks = <&sysclk>;
};


code:
Faraday Technology timer

This timer is a generic IP block from Faraday Technology, embedded in the
Cortina Systems Gemini SoCs and other designs.

Required properties:

- compatible : Must be one of
  "faraday,fttmr010"
  "cortina,gemini-timer", "faraday,fttmr010"
  "moxa,moxart-timer", "faraday,fttmr010"
  "aspeed,ast2400-timer"
  "aspeed,ast2500-timer"
  "aspeed,ast2600-timer"

- reg : Should contain registers location and length
- interrupts : Should contain the three timer interrupts usually with
  flags for falling edge

Optionally required properties:

- clocks : a clock to provide the tick rate for "faraday,fttmr010"
- clock-names : should be "EXTCLK" and "PCLK" for the external tick timer
  and peripheral clock respectively, for "faraday,fttmr010"
- syscon : a phandle to the global Gemini system controller if the compatible
  type is "cortina,gemini-timer"

Example:

timer@43000000 {
	compatible = "faraday,fttmr010";
	reg = <0x43000000 0x1000>;
	interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
		   <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
		   <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
	clocks = <&extclk>, <&pclk>;
	clock-names = "EXTCLK", "PCLK";
};


code:
Freescale FlexTimer Module (FTM) Timer

Required properties:

- compatible : should be "fsl,ftm-timer"
- reg : Specifies base physical address and size of the register sets for the
  clock event device and clock source device.
- interrupts : Should be the clock event device interrupt.
- clocks : The clocks provided by the SoC to drive the timer, must contain an
  entry for each entry in clock-names.
- clock-names : Must include the following entries:
  o "ftm-evt"
  o "ftm-src"
  o "ftm-evt-counter-en"
  o "ftm-src-counter-en"
- big-endian: One boolean property, the big endian mode will be in use if it is
  present, or the little endian mode will be in use for all the device registers.

Example:
ftm: ftm@400b8000 {
	compatible = "fsl,ftm-timer";
	reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
	interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "ftm-evt", "ftm-src",
		"ftm-evt-counter-en", "ftm-src-counter-en";
	clocks = <&clks VF610_CLK_FTM2>,
		<&clks VF610_CLK_FTM3>,
		<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
		<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
	big-endian;
};


code:
* Freescale General-purpose Timers Module

Required properties:
  - compatible : should be
    "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
    "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
    "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
  - reg : should contain gtm registers location and length (0x40).
  - interrupts : should contain four interrupts.
  - clock-frequency : specifies the frequency driving the timer.

Example:

timer@500 {
	compatible = "fsl,mpc8360-gtm", "fsl,gtm";
	reg = <0x500 0x40>;
	interrupts = <90 8 78 8 84 8 72 8>;
	interrupt-parent = <&ipic>;
	/* filled by u-boot */
	clock-frequency = <0>;
};

timer@440 {
	compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
	reg = <0x440 0x40>;
	interrupts = <12 13 14 15>;
	interrupt-parent = <&qeic>;
	/* filled by u-boot */
	clock-frequency = <0>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/fsl,imxgpt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX General Purpose Timer (GPT)

maintainers:
  - Sascha Hauer <s.hauer@pengutronix.de>

properties:
  compatible:
    oneOf:
      - const: fsl,imx1-gpt
      - const: fsl,imx21-gpt
      - items:
          - const: fsl,imx27-gpt
          - const: fsl,imx21-gpt
      - const: fsl,imx31-gpt
      - items:
          - enum:
              - fsl,imx25-gpt
              - fsl,imx50-gpt
              - fsl,imx51-gpt
              - fsl,imx53-gpt
              - fsl,imx6q-gpt
          - const: fsl,imx31-gpt
      - const: fsl,imx6dl-gpt
      - items:
          - enum:
              - fsl,imx6sl-gpt
              - fsl,imx6sx-gpt
              - fsl,imxrt1050-gpt
              - fsl,imxrt1170-gpt
          - const: fsl,imx6dl-gpt

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: SoC GPT ipg clock
      - description: SoC GPT per clock

  clock-names:
    items:
      - const: ipg
      - const: per

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx27-clock.h>

    timer@10003000 {
        compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
        reg = <0x10003000 0x1000>;
        interrupts = <26>;
        clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
                 <&clks IMX27_CLK_PER1_GATE>;
        clock-names = "ipg", "per";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/hpe,gxp-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: HPE GXP Timer

maintainers:
  - Nick Hawkins <nick.hawkins@hpe.com>
  - Jean-Marie Verdun <verdun@hpe.com>

properties:
  compatible:
    const: hpe,gxp-timer

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: iop

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    timer@c0000000 {
        compatible = "hpe,gxp-timer";
        reg = <0x80 0x16>;
        interrupts = <0>;
        interrupt-parent = <&vic0>;
        clocks = <&iopclk>;
        clock-names = "iop";
    };


code:
* Pistachio general-purpose timer based clocksource

Required properties:
 - compatible: "img,pistachio-gptimer".
 - reg: Address range of the timer registers.
 - interrupts: An interrupt for each of the four timers
 - clocks: Should contain a clock specifier for each entry in clock-names
 - clock-names: Should contain the following entries:
                "sys", interface clock
                "slow", slow counter clock
                "fast", fast counter clock
 - img,cr-periph: Must contain a phandle to the peripheral control
		  syscon node.

Example:
	timer: timer@18102000 {
		compatible = "img,pistachio-gptimer";
		reg = <0x18102000 0x100>;
		interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SHARED 61 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SHARED 62 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SHARED 63 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>,
		         <&clk_periph PERIPH_CLK_COUNTER_SLOW>,
			 <&cr_periph SYS_CLK_TIMER>;
		clock-names = "fast", "slow", "sys";
		img,cr-periph = <&cr_periph>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/ingenic,sysost.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Bindings for SYSOST in Ingenic XBurst family SoCs

maintainers:
  - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

description:
  The SYSOST in an Ingenic SoC provides one 64bit timer for clocksource
  and one or more 32bit timers for clockevent.

properties:
  "#clock-cells":
    const: 1

  compatible:
    enum:
      - ingenic,x1000-ost
      - ingenic,x2000-ost

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: ost

  interrupts:
    maxItems: 1

required:
  - "#clock-cells"
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,x1000-cgu.h>

    ost: timer@12000000 {
        compatible = "ingenic,x1000-ost";
        reg = <0x12000000 0x3c>;

        #clock-cells = <1>;

        clocks = <&cgu X1000_CLK_OST>;
        clock-names = "ost";

        interrupt-parent = <&cpuintc>;
        interrupts = <3>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/ingenic,tcu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs Timer/Counter Unit (TCU) devicetree bindings

description: |
  For a description of the TCU hardware and drivers, have a look at
  Documentation/mips/ingenic-tcu.rst.

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

select:
  properties:
    compatible:
      contains:
        enum:
          - ingenic,jz4740-tcu
          - ingenic,jz4725b-tcu
          - ingenic,jz4760-tcu
          - ingenic,jz4760b-tcu
          - ingenic,jz4770-tcu
          - ingenic,jz4780-tcu
          - ingenic,x1000-tcu
  required:
    - compatible

properties:
  $nodename:
    pattern: "^timer@[0-9a-f]+$"

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  "#clock-cells":
    const: 1

  "#interrupt-cells":
    const: 1

  interrupt-controller: true

  ranges: true

  compatible:
    oneOf:
      - items:
          - enum:
              - ingenic,jz4740-tcu
              - ingenic,jz4725b-tcu
              - ingenic,jz4760-tcu
              - ingenic,x1000-tcu
          - const: simple-mfd
      - items:
          - enum:
              - ingenic,jz4780-tcu
              - ingenic,jz4770-tcu
              - ingenic,jz4760b-tcu
          - const: ingenic,jz4760-tcu
          - const: simple-mfd

  reg:
    maxItems: 1

  clocks:
    items:
      - description: RTC clock
      - description: EXT clock
      - description: PCLK clock
      - description: TCU clock
    minItems: 3

  clock-names:
    items:
      - const: rtc
      - const: ext
      - const: pclk
      - const: tcu
    minItems: 3

  interrupts:
    items:
      - description: TCU0 interrupt
      - description: TCU1 interrupt
      - description: TCU2 interrupt
    minItems: 1

  assigned-clocks:
    minItems: 1
    maxItems: 8

  assigned-clock-parents:
    minItems: 1
    maxItems: 8

  assigned-clock-rates:
    minItems: 1
    maxItems: 8

  ingenic,pwm-channels-mask:
    description: Bitmask of TCU channels reserved for PWM use.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0x00
    maximum: 0xff
    default: 0xfc

patternProperties:
  "^watchdog@[a-f0-9]+$":
    type: object
    $ref: /schemas/watchdog/watchdog.yaml#
    unevaluatedProperties: false

    properties:
      compatible:
        oneOf:
          - enum:
              - ingenic,jz4740-watchdog
              - ingenic,jz4780-watchdog
          - items:
              - enum:
                  - ingenic,jz4770-watchdog
                  - ingenic,jz4760b-watchdog
                  - ingenic,jz4760-watchdog
                  - ingenic,jz4725b-watchdog
              - const: ingenic,jz4740-watchdog

      reg:
        maxItems: 1

      clocks:
        maxItems: 1

      clock-names:
        const: wdt

    required:
      - compatible
      - reg
      - clocks
      - clock-names

  "^pwm@[a-f0-9]+$":
    type: object
    $ref: /schemas/pwm/pwm.yaml#
    unevaluatedProperties: false

    properties:
      compatible:
        oneOf:
          - enum:
              - ingenic,jz4740-pwm
              - ingenic,jz4725b-pwm
              - ingenic,x1000-pwm
          - items:
              - enum:
                  - ingenic,jz4760-pwm
                  - ingenic,jz4760b-pwm
                  - ingenic,jz4770-pwm
                  - ingenic,jz4780-pwm
              - const: ingenic,jz4740-pwm

      reg:
        maxItems: 1

      clocks:
        minItems: 6
        maxItems: 8

      clock-names:
        items:
          - const: timer0
          - const: timer1
          - const: timer2
          - const: timer3
          - const: timer4
          - const: timer5
          - const: timer6
          - const: timer7
        minItems: 6

    required:
      - compatible
      - reg
      - clocks
      - clock-names

  "^timer@[a-f0-9]+$":
    type: object
    properties:
      compatible:
        oneOf:
          - enum:
              - ingenic,jz4725b-ost
              - ingenic,jz4760b-ost
          - items:
              - const: ingenic,jz4760-ost
              - const: ingenic,jz4725b-ost
          - items:
              - enum:
                  - ingenic,jz4780-ost
                  - ingenic,jz4770-ost
              - const: ingenic,jz4760b-ost

      reg:
        maxItems: 1

      clocks:
        maxItems: 1

      clock-names:
        const: ost

      interrupts:
        maxItems: 1

    required:
      - compatible
      - reg
      - clocks
      - clock-names
      - interrupts

    additionalProperties: false

required:
  - "#clock-cells"
  - "#interrupt-cells"
  - interrupt-controller
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
    #include <dt-bindings/clock/ingenic,tcu.h>
    tcu: timer@10002000 {
      compatible = "ingenic,jz4770-tcu", "ingenic,jz4760-tcu", "simple-mfd";
      reg = <0x10002000 0x1000>;
      #address-cells = <1>;
      #size-cells = <1>;
      ranges = <0x0 0x10002000 0x1000>;

      #clock-cells = <1>;

      clocks = <&cgu JZ4770_CLK_RTC>,
               <&cgu JZ4770_CLK_EXT>,
               <&cgu JZ4770_CLK_PCLK>;
      clock-names = "rtc", "ext", "pclk";

      interrupt-controller;
      #interrupt-cells = <1>;

      interrupt-parent = <&intc>;
      interrupts = <27 26 25>;

      watchdog: watchdog@0 {
        compatible = "ingenic,jz4770-watchdog", "ingenic,jz4740-watchdog";
        reg = <0x0 0xc>;

        clocks = <&tcu TCU_CLK_WDT>;
        clock-names = "wdt";
      };

      pwm: pwm@40 {
        compatible = "ingenic,jz4770-pwm", "ingenic,jz4740-pwm";
        reg = <0x40 0x80>;

        #pwm-cells = <3>;

        clocks = <&tcu TCU_CLK_TIMER0>,
                 <&tcu TCU_CLK_TIMER1>,
                 <&tcu TCU_CLK_TIMER2>,
                 <&tcu TCU_CLK_TIMER3>,
                 <&tcu TCU_CLK_TIMER4>,
                 <&tcu TCU_CLK_TIMER5>,
                 <&tcu TCU_CLK_TIMER6>,
                 <&tcu TCU_CLK_TIMER7>;
        clock-names = "timer0", "timer1", "timer2", "timer3",
                "timer4", "timer5", "timer6", "timer7";
      };

      ost: timer@e0 {
        compatible = "ingenic,jz4770-ost", "ingenic,jz4760b-ost";
        reg = <0xe0 0x20>;

        clocks = <&tcu TCU_CLK_OST>;
        clock-names = "ost";

        interrupts = <15>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/timer/intel,ixp4xx-timer.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel IXP4xx XScale Networking Processors Timers

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: This timer is found in the Intel IXP4xx processors.

properties:
  compatible:
    items:
      - const: intel,ixp4xx-timer

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    items:
      - description: Timer 1 interrupt
      - description: Timer 2 interrupt

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    timer@c8005000 {
        compatible = "intel,ixp4xx-timer";
        reg = <0xc8005000 0x100>;
        interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
    };


code:
J-Core Programmable Interval Timer and Clocksource

Required properties:

- compatible: Must be "jcore,pit".

- reg: Memory region(s) for timer/clocksource registers. For SMP,
  there should be one region per cpu, indexed by the sequential,
  zero-based hardware cpu number.

- interrupts: An interrupt to assign for the timer. The actual pit
  core is integrated with the aic and allows the timer interrupt
  assignment to be programmed by software, but this property is
  required in order to reserve an interrupt number that doesn't
  conflict with other devices.

Example:

timer@200 {
	compatible = "jcore,pit";
	reg = < 0x200 0x30 0x500 0x30 >;
	interrupts = < 0x48 >;
};


code:
TI-NSPIRE timer

Required properties:

- compatible : should be "lsi,zevio-timer".
- reg : The physical base address and size of the timer (always first).
- clocks: phandle to the source clock.

Optional properties:

- interrupts : The interrupt number of the first timer.
- reg : The interrupt acknowledgement registers
	(always after timer base address)

If any of the optional properties are not given, the timer is added as a
clock-source only.

Example:

timer {
	compatible = "lsi,zevio-timer";
	reg = <0x900D0000 0x1000>, <0x900A0020 0x8>;
	interrupts = <19>;
	clocks = <&timer_clk>;
};

Example (no clock-events):

timer {
	compatible = "lsi,zevio-timer";
	reg = <0x900D0000 0x1000>;
	clocks = <&timer_clk>;
};


code:
Marvell Armada 370 and Armada XP Timers
---------------------------------------

Required properties:
- compatible: Should be one of the following
              "marvell,armada-370-timer",
	      "marvell,armada-375-timer",
	      "marvell,armada-xp-timer".
- interrupts: Should contain the list of Global Timer interrupts and
  then local timer interrupts
- reg: Should contain location and length for timers register. First
  pair for the Global Timer registers, second pair for the
  local/private timers.

Clocks required for compatible = "marvell,armada-370-timer":
- clocks : Must contain a single entry describing the clock input

Clocks required for compatibles = "marvell,armada-xp-timer",
				  "marvell,armada-375-timer":
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
  "nbclk" (L2/coherency fabric clock),
  "fixed" (Reference 25 MHz fixed-clock).

Examples:

- Armada 370:

	timer {
		compatible = "marvell,armada-370-timer";
		reg = <0x20300 0x30>, <0x21040 0x30>;
		interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
		clocks = <&coreclk 2>;
	};

- Armada XP:

	timer {
		compatible = "marvell,armada-xp-timer";
		reg = <0x20300 0x30>, <0x21040 0x30>;
		interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
		clocks = <&coreclk 2>, <&refclk>;
		clock-names = "nbclk", "fixed";
	};


code:
Marvell Orion SoC timer

Required properties:
- compatible: shall be "marvell,orion-timer"
- reg: base address of the timer register starting with TIMERS CONTROL register
- interrupts: should contain the interrupts for Timer0 and Timer1
- clocks: phandle of timer reference clock (tclk)

Example:
	timer: timer {
		compatible = "marvell,orion-timer";
		reg = <0x20300 0x20>;
		interrupt-parent = <&bridge_intc>;
		interrupts = <1>, <2>;
		clocks = <&core_clk 0>;
	};


code:
MediaTek Timers
---------------

MediaTek SoCs have different timers on different platforms,
- CPUX (ARM/ARM64 System Timer)
- GPT (General Purpose Timer)
- SYST (System Timer)

The proper timer will be selected automatically by driver.

Required properties:
- compatible should contain:
	For those SoCs that use GPT
	* "mediatek,mt2701-timer" for MT2701 compatible timers (GPT)
	* "mediatek,mt6580-timer" for MT6580 compatible timers (GPT)
	* "mediatek,mt6582-timer" for MT6582 compatible timers (GPT)
	* "mediatek,mt6589-timer" for MT6589 compatible timers (GPT)
	* "mediatek,mt7623-timer" for MT7623 compatible timers (GPT)
	* "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
	* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
	* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
	* "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
	* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)

	For those SoCs that use SYST
	* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
	* "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
	* "mediatek,mt8188-timer" for MT8188 compatible timers (SYST)
	* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
	* "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
	* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
	* "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)

	For those SoCs that use CPUX
	* "mediatek,mt6795-systimer" for MT6795 compatible timers (CPUX)

- reg: Should contain location and length for timer register.
- clocks: Should contain system clock.

Examples:

	timer@10008000 {
		compatible = "mediatek,mt6577-timer";
		reg = <0x10008000 0x80>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/mrvl,mmp-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell MMP Timer bindings

maintainers:
  - Daniel Lezcano <daniel.lezcano@linaro.org>
  - Thomas Gleixner <tglx@linutronix.de>
  - Rob Herring <robh+dt@kernel.org>

properties:
  $nodename:
    pattern: '^timer@[a-f0-9]+$'

  compatible:
    const: mrvl,mmp-timer

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    timer@d4014000 {
        compatible = "mrvl,mmp-timer";
        reg = <0xd4014000 0x100>;
        interrupts = <13>;
        clocks = <&coreclk 2>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/mstar,msc313e-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mstar MSC313e Timer

maintainers:
  - Daniel Palmer <daniel@0x0f.com>
  - Romain Perier <romain.perier@gmail.com>

properties:
  compatible:
    enum:
      - mstar,msc313e-timer
      - sstar,ssd20xd-timer

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    timer@6040 {
        compatible = "mstar,msc313e-timer";
        reg = <0x6040 0x40>;
        clocks = <&xtal_div2>;
        interrupts-extended = <&intc_fiq GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/nuvoton,npcm7xx-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Nuvoton NPCM7xx timer

maintainers:
  - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
  - Tomer Maimon <tmaimon77@gmail.com>

properties:
  compatible:
    enum:
      - nuvoton,wpcm450-timer  # for Hermon WPCM450
      - nuvoton,npcm750-timer  # for Poleg NPCM750
      - nuvoton,npcm845-timer  # for Arbel NPCM845

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: The timer interrupt of timer 0

  clocks:
    items:
      - description: The reference clock for timer 0
      - description: The reference clock for timer 1
      - description: The reference clock for timer 2
      - description: The reference clock for timer 3
      - description: The reference clock for timer 4
    minItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
    timer@f0008000 {
        compatible = "nuvoton,npcm750-timer";
        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
        reg = <0xf0008000 0x50>;
        clocks = <&clk NPCM7XX_CLK_TIMER>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: "http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: NVIDIA Tegra timer

maintainers:
  - Stephen Warren <swarren@nvidia.com>

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra210-timer
    then:
      properties:
        interrupts:
          # Either a single combined interrupt or up to 14 individual interrupts
          minItems: 1
          maxItems: 14
          description: >
            A list of 14 interrupts; one per each timer channels 0 through 13

  - if:
      properties:
        compatible:
          oneOf:
            - items:
                - enum:
                    - nvidia,tegra114-timer
                    - nvidia,tegra124-timer
                    - nvidia,tegra132-timer
                - const: nvidia,tegra30-timer
            - items:
                - const: nvidia,tegra30-timer
                - const: nvidia,tegra20-timer
    then:
      properties:
        interrupts:
          # Either a single combined interrupt or up to 6 individual interrupts
          minItems: 1
          maxItems: 6
          description: >
            A list of 6 interrupts; one per each of timer channels 1 through 5,
            and one for the shared interrupt for the remaining channels.

  - if:
      properties:
        compatible:
          const: nvidia,tegra20-timer
    then:
      properties:
        interrupts:
          # Either a single combined interrupt or up to 4 individual interrupts
          minItems: 1
          maxItems: 4
          description: |
            A list of 4 interrupts; one per timer channel.

properties:
  compatible:
    oneOf:
      - const: nvidia,tegra210-timer
        description: >
          The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
          timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
          from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
          (TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
          or watchdog interrupts.
      - items:
          - enum:
              - nvidia,tegra114-timer
              - nvidia,tegra124-timer
              - nvidia,tegra132-timer
          - const: nvidia,tegra30-timer
      - items:
          - const: nvidia,tegra30-timer
          - const: nvidia,tegra20-timer
        description: >
          The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
          running counter, and 5 watchdog modules. The first two channels may also
          trigger a legacy watchdog reset.
      - const: nvidia,tegra20-timer
        description: >
          The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
          running counter. The first two channels may also trigger a watchdog reset.

  reg:
    maxItems: 1

  interrupts: true

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: timer

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    timer@60005000 {
        compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
        reg = <0x60005000 0x400>;
        interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
                     <0 1 IRQ_TYPE_LEVEL_HIGH>,
                     <0 41 IRQ_TYPE_LEVEL_HIGH>,
                     <0 42 IRQ_TYPE_LEVEL_HIGH>,
                     <0 121 IRQ_TYPE_LEVEL_HIGH>,
                     <0 122 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car 214>;
    };
  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    timer@60005000 {
        compatible = "nvidia,tegra210-timer";
        reg = <0x60005000 0x400>;
        interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&tegra_car TEGRA210_CLK_TIMER>;
        clock-names = "timer";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: NVIDIA Tegra186 timer

maintainers:
  - Thierry Reding <treding@nvidia.com>

description: >
  The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
  counter. Each NV timer selects its timing reference signal from the 1 MHz
  reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
  programmed to generate one-shot, periodic, or watchdog interrupts.

properties:
  compatible:
    oneOf:
      - const: nvidia,tegra186-timer
        description: >
          The Tegra186 timer provides ten 29-bit timer counters.
      - const: nvidia,tegra234-timer
        description: >
          The Tegra234 timer provides sixteen 29-bit timer counters.

  reg:
    maxItems: 1

  interrupts: true

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra186-timer
    then:
      properties:
        interrupts:
          maxItems: 10
          description: >
            One per each timer channels 0 through 9.

  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra234-timer
    then:
      properties:
        interrupts:
          maxItems: 16
          description: >
            One per each timer channels 0 through 15.

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    timer@3010000 {
        compatible = "nvidia,tegra186-timer";
        reg = <0x03010000 0x000e0000>;
        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    timer@2080000 {
        compatible = "nvidia,tegra234-timer";
        reg = <0x02080000 0x00121000>;
        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
    };


code:
* NXP LPC3220 timer

The NXP LPC3220 timer is used on a wide range of NXP SoCs. This
includes LPC32xx, LPC178x, LPC18xx and LPC43xx parts.

Required properties:
- compatible:
	Should be "nxp,lpc3220-timer".
- reg:
	Address and length of the register set.
- interrupts:
	Reference to the timer interrupt
- clocks:
	Should contain a reference to timer clock.
- clock-names:
	Should contain "timerclk".

Example:

timer1: timer@40085000 {
	compatible = "nxp,lpc3220-timer";
	reg = <0x40085000 0x1000>;
	interrupts = <13>;
	clocks = <&ccu1 CLK_CPU_TIMER1>;
	clock-names = "timerclk";
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP System Counter Module(sys_ctr)

maintainers:
  - Bai Ping <ping.bai@nxp.com>

description: |
  The system counter(sys_ctr) is a programmable system counter
  which provides a shared time base to Cortex A15, A7, A53, A73,
  etc. it is intended for use in applications where the counter
  is always powered and support multiple, unrelated clocks. The
  compare frame inside can be used for timer purpose.

properties:
  compatible:
    const: nxp,sysctr-timer

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: per

  nxp,no-divider:
    description: if present, means there is no internal base clk divider.
    type: boolean

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    timer@306a0000 {
        compatible = "nxp,sysctr-timer";
        reg = <0x306a0000 0x20000>;
        clocks = <&clk_8m>;
        clock-names = "per";
        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
     };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP Low Power Timer/Pulse Width Modulation Module (TPM)

maintainers:
  - Dong Aisheng <aisheng.dong@nxp.com>

description: |
  The Timer/PWM Module (TPM) supports input capture, output compare,
  and the generation of PWM signals to control electric motor and power
  management applications. The counter, compare and capture registers
  are clocked by an asynchronous clock that can remain enabled in low
  power modes. TPM can support global counter bus where one TPM drives
  the counter bus for the others, provided bit width is the same.

properties:
  compatible:
    oneOf:
      - const: fsl,imx7ulp-tpm
      - items:
          - const: fsl,imx8ulp-tpm
          - const: fsl,imx7ulp-tpm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: SoC TPM ipg clock
      - description: SoC TPM per clock

  clock-names:
    items:
      - const: ipg
      - const: per

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx7ulp-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    timer@40260000 {
        compatible = "fsl,imx7ulp-tpm";
        reg = <0x40260000 0x1000>;
        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
                 <&pcc2 IMX7ULP_CLK_LPTPM5>;
        clock-names = "ipg", "per";
    };


code:
Oxford Semiconductor OXNAS SoCs Family RPS Timer
================================================

Required properties:
- compatible: Should be "oxsemi,ox810se-rps-timer" or "oxsemi,ox820-rps-timer"
- reg : Specifies base physical address and size of the registers.
- interrupts : The interrupts of the two timers
- clocks : The phandle of the timer clock source

example:

timer0: timer@200 {
	compatible = "oxsemi,ox810se-rps-timer";
	reg = <0x200 0x40>;
	clocks = <&rpsclk>;
	interrupts = <4 5>;
};


code:
* MSM Timer

Properties:

- compatible : Should at least contain "qcom,msm-timer". More specific
               properties specify which subsystem the timers are paired with.

               "qcom,kpss-timer" - krait subsystem
               "qcom,scss-timer" - scorpion subsystem

- interrupts : Interrupts for the debug timer, the first general purpose
               timer, and optionally a second general purpose timer, and
               optionally as well, 2 watchdog interrupts, in that order.

- reg : Specifies the base address of the timer registers.

- clocks: Reference to the parent clocks, one per output clock. The parents
          must appear in the same order as the clock names.

- clock-names: The name of the clocks as free-form strings. They should be in
               the same order as the clocks.

- clock-frequency : The frequency of the debug timer and the general purpose
                    timer(s) in Hz in that order.

Optional:

- cpu-offset : per-cpu offset used when the timer is accessed without the
               CPU remapping facilities. The offset is
               cpu-offset + (0x10000 * cpu-nr).

Example:

       timer@200a000 {
               compatible = "qcom,scss-timer", "qcom,msm-timer";
               interrupts = <1 1 0x301>,
                            <1 2 0x301>,
                            <1 3 0x301>,
                            <1 4 0x301>,
                            <1 5 0x301>;
               reg = <0x0200a000 0x100>;
               clock-frequency = <19200000>,
                                 <32768>;
               clocks = <&sleep_clk>;
               clock-names = "sleep";
               cpu-offset = <0x40000>;
       };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/rda,8810pl-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RDA Micro RDA8810PL Timer

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

properties:
  compatible:
    const: rda,8810pl-timer

  reg:
    maxItems: 1

  interrupts:
    minItems: 2
    maxItems: 2

  interrupt-names:
    items:
      - const: hwtimer
      - const: ostimer

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    timer@20910000 {
      compatible = "rda,8810pl-timer";
      reg = <0x20910000 0x1000>;
      interrupts = <16 IRQ_TYPE_LEVEL_HIGH>,
                   <17 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "hwtimer", "ostimer";
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/renesas,cmt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Compare Match Timer (CMT)

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

description:
  The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
  inputs and programmable compare match.

  Channels share hardware resources but their counter and compare match values
  are independent. A particular CMT instance can implement only a subset of the
  channels supported by the CMT model. Channel indices represent the hardware
  position of the channel in the CMT and don't match the channel numbers in the
  datasheets.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,r8a7740-cmt0      # 32-bit CMT0 on R-Mobile A1
              - renesas,r8a7740-cmt1      # 48-bit CMT1 on R-Mobile A1
              - renesas,r8a7740-cmt2      # 32-bit CMT2 on R-Mobile A1
              - renesas,r8a7740-cmt3      # 32-bit CMT3 on R-Mobile A1
              - renesas,r8a7740-cmt4      # 32-bit CMT4 on R-Mobile A1
              - renesas,sh73a0-cmt0       # 32-bit CMT0 on SH-Mobile AG5
              - renesas,sh73a0-cmt1       # 48-bit CMT1 on SH-Mobile AG5
              - renesas,sh73a0-cmt2       # 32-bit CMT2 on SH-Mobile AG5
              - renesas,sh73a0-cmt3       # 32-bit CMT3 on SH-Mobile AG5
              - renesas,sh73a0-cmt4       # 32-bit CMT4 on SH-Mobile AG5

      - items:
          - enum:
              - renesas,r8a73a4-cmt0      # 32-bit CMT0 on R-Mobile APE6
              - renesas,r8a7742-cmt0      # 32-bit CMT0 on RZ/G1H
              - renesas,r8a7743-cmt0      # 32-bit CMT0 on RZ/G1M
              - renesas,r8a7744-cmt0      # 32-bit CMT0 on RZ/G1N
              - renesas,r8a7745-cmt0      # 32-bit CMT0 on RZ/G1E
              - renesas,r8a77470-cmt0     # 32-bit CMT0 on RZ/G1C
              - renesas,r8a7790-cmt0      # 32-bit CMT0 on R-Car H2
              - renesas,r8a7791-cmt0      # 32-bit CMT0 on R-Car M2-W
              - renesas,r8a7792-cmt0      # 32-bit CMT0 on R-Car V2H
              - renesas,r8a7793-cmt0      # 32-bit CMT0 on R-Car M2-N
              - renesas,r8a7794-cmt0      # 32-bit CMT0 on R-Car E2
          - const: renesas,rcar-gen2-cmt0 # 32-bit CMT0 on R-Mobile APE6, R-Car Gen2 and RZ/G1

      - items:
          - enum:
              - renesas,r8a73a4-cmt1      # 48-bit CMT1 on R-Mobile APE6
              - renesas,r8a7742-cmt1      # 48-bit CMT1 on RZ/G1H
              - renesas,r8a7743-cmt1      # 48-bit CMT1 on RZ/G1M
              - renesas,r8a7744-cmt1      # 48-bit CMT1 on RZ/G1N
              - renesas,r8a7745-cmt1      # 48-bit CMT1 on RZ/G1E
              - renesas,r8a77470-cmt1     # 48-bit CMT1 on RZ/G1C
              - renesas,r8a7790-cmt1      # 48-bit CMT1 on R-Car H2
              - renesas,r8a7791-cmt1      # 48-bit CMT1 on R-Car M2-W
              - renesas,r8a7792-cmt1      # 48-bit CMT1 on R-Car V2H
              - renesas,r8a7793-cmt1      # 48-bit CMT1 on R-Car M2-N
              - renesas,r8a7794-cmt1      # 48-bit CMT1 on R-Car E2
          - const: renesas,rcar-gen2-cmt1 # 48-bit CMT1 on R-Mobile APE6, R-Car Gen2 and RZ/G1

      - items:
          - enum:
              - renesas,r8a774a1-cmt0     # 32-bit CMT0 on RZ/G2M
              - renesas,r8a774b1-cmt0     # 32-bit CMT0 on RZ/G2N
              - renesas,r8a774c0-cmt0     # 32-bit CMT0 on RZ/G2E
              - renesas,r8a774e1-cmt0     # 32-bit CMT0 on RZ/G2H
              - renesas,r8a7795-cmt0      # 32-bit CMT0 on R-Car H3
              - renesas,r8a7796-cmt0      # 32-bit CMT0 on R-Car M3-W
              - renesas,r8a77961-cmt0     # 32-bit CMT0 on R-Car M3-W+
              - renesas,r8a77965-cmt0     # 32-bit CMT0 on R-Car M3-N
              - renesas,r8a77970-cmt0     # 32-bit CMT0 on R-Car V3M
              - renesas,r8a77980-cmt0     # 32-bit CMT0 on R-Car V3H
              - renesas,r8a77990-cmt0     # 32-bit CMT0 on R-Car E3
              - renesas,r8a77995-cmt0     # 32-bit CMT0 on R-Car D3
          - const: renesas,rcar-gen3-cmt0 # 32-bit CMT0 on R-Car Gen3 and RZ/G2

      - items:
          - enum:
              - renesas,r8a774a1-cmt1     # 48-bit CMT on RZ/G2M
              - renesas,r8a774b1-cmt1     # 48-bit CMT on RZ/G2N
              - renesas,r8a774c0-cmt1     # 48-bit CMT on RZ/G2E
              - renesas,r8a774e1-cmt1     # 48-bit CMT on RZ/G2H
              - renesas,r8a7795-cmt1      # 48-bit CMT on R-Car H3
              - renesas,r8a7796-cmt1      # 48-bit CMT on R-Car M3-W
              - renesas,r8a77961-cmt1     # 48-bit CMT on R-Car M3-W+
              - renesas,r8a77965-cmt1     # 48-bit CMT on R-Car M3-N
              - renesas,r8a77970-cmt1     # 48-bit CMT on R-Car V3M
              - renesas,r8a77980-cmt1     # 48-bit CMT on R-Car V3H
              - renesas,r8a77990-cmt1     # 48-bit CMT on R-Car E3
              - renesas,r8a77995-cmt1     # 48-bit CMT on R-Car D3
          - const: renesas,rcar-gen3-cmt1 # 48-bit CMT on R-Car Gen3 and RZ/G2

      - items:
          - enum:
              - renesas,r8a779a0-cmt0     # 32-bit CMT0 on R-Car V3U
              - renesas,r8a779f0-cmt0     # 32-bit CMT0 on R-Car S4-8
              - renesas,r8a779g0-cmt0     # 32-bit CMT0 on R-Car V4H
          - const: renesas,rcar-gen4-cmt0 # 32-bit CMT0 on R-Car Gen4

      - items:
          - enum:
              - renesas,r8a779a0-cmt1     # 48-bit CMT on R-Car V3U
              - renesas,r8a779f0-cmt1     # 48-bit CMT on R-Car S4-8
              - renesas,r8a779g0-cmt1     # 48-bit CMT on R-Car V4H
          - const: renesas,rcar-gen4-cmt1 # 48-bit CMT on R-Car Gen4

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 8

  clocks:
    maxItems: 1

  clock-names:
    const: fck

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,rcar-gen2-cmt0
              - renesas,rcar-gen3-cmt0
              - renesas,rcar-gen4-cmt0
    then:
      properties:
        interrupts:
          minItems: 2
          maxItems: 2

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,rcar-gen2-cmt1
              - renesas,rcar-gen3-cmt1
              - renesas,rcar-gen4-cmt1
    then:
      properties:
        interrupts:
          minItems: 8
          maxItems: 8

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>
    cmt0: timer@ffca0000 {
            compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
            reg = <0xffca0000 0x1004>;
            interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 124>;
            clock-names = "fck";
            power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
            resets = <&cpg 124>;
    };

    cmt1: timer@e6130000 {
            compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
            reg = <0xe6130000 0x1004>;
            interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 329>;
            clock-names = "fck";
            power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
            resets = <&cpg 329>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/renesas,em-sti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas EMMA Mobile System Timer

maintainers:
  - Magnus Damm <magnus.damm@gmail.com>

properties:
  compatible:
    const: renesas,em-sti

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: sclk

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    timer@e0180000 {
            compatible = "renesas,em-sti";
            reg = <0xe0180000 0x54>;
            interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&sti_sclk>;
            clock-names = "sclk";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/renesas,mtu2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Multi-Function Timer Pulse Unit 2 (MTU2)

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

description:
  The MTU2 is a multi-purpose, multi-channel timer/counter with configurable clock inputs
  and programmable compare match.

  Channels share hardware resources but their counter and compare match value are
  independent. The MTU2 hardware supports five channels indexed from 0 to 4.

properties:
  compatible:
    items:
      - enum:
          - renesas,mtu2-r7s72100 # RZ/A1H
      - const: renesas,mtu2

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 5
    description: One entry for each enabled channel.

  interrupt-names:
    minItems: 1
    items:
      - const: tgi0a
      - const: tgi1a
      - const: tgi2a
      - const: tgi3a
      - const: tgi4a

  clocks:
    maxItems: 1

  clock-names:
    const: fck

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r7s72100-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    mtu2: timer@fcff0000 {
            compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
            reg = <0xfcff0000 0x400>;
            interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "tgi0a";
            clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
            clock-names = "fck";
            power-domains = <&cpg_clocks>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/renesas,ostm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas OS Timer (OSTM)

maintainers:
  - Chris Brandt <chris.brandt@renesas.com>
  - Geert Uytterhoeven <geert+renesas@glider.be>

description:
  The OSTM is a multi-channel 32-bit timer/counter with fixed clock source that
  can operate in either interval count down timer or free-running compare match
  mode.

  Channels are independent from each other.

properties:
  compatible:
    items:
      - enum:
          - renesas,r7s72100-ostm  # RZ/A1H
          - renesas,r7s9210-ostm   # RZ/A2M
          - renesas,r9a07g043-ostm # RZ/G2UL
          - renesas,r9a07g044-ostm # RZ/G2{L,LC}
          - renesas,r9a07g054-ostm # RZ/V2L
      - const: renesas,ostm        # Generic

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains

if:
  properties:
    compatible:
      contains:
        enum:
          - renesas,r9a07g043-ostm
          - renesas,r9a07g044-ostm
          - renesas,r9a07g054-ostm
then:
  required:
    - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r7s72100-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    ostm0: timer@fcfec000 {
            compatible = "renesas,r7s72100-ostm", "renesas,ostm";
            reg = <0xfcfec000 0x30>;
            interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
            clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
            power-domains = <&cpg_clocks>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/renesas,tmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Mobile/R-Car Timer Unit (TMU)

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

description:
  The TMU is a 32-bit timer/counter with configurable clock inputs and
  programmable compare match.

  Channels share hardware resources but their counter and compare match value
  are independent. The TMU hardware supports up to three channels.

properties:
  compatible:
    items:
      - enum:
          - renesas,tmu-r8a7740  # R-Mobile A1
          - renesas,tmu-r8a774a1 # RZ/G2M
          - renesas,tmu-r8a774b1 # RZ/G2N
          - renesas,tmu-r8a774c0 # RZ/G2E
          - renesas,tmu-r8a774e1 # RZ/G2H
          - renesas,tmu-r8a7778  # R-Car M1A
          - renesas,tmu-r8a7779  # R-Car H1
          - renesas,tmu-r8a7795  # R-Car H3
          - renesas,tmu-r8a7796  # R-Car M3-W
          - renesas,tmu-r8a77961 # R-Car M3-W+
          - renesas,tmu-r8a77965 # R-Car M3-N
          - renesas,tmu-r8a77970 # R-Car V3M
          - renesas,tmu-r8a77980 # R-Car V3H
          - renesas,tmu-r8a77990 # R-Car E3
          - renesas,tmu-r8a77995 # R-Car D3
          - renesas,tmu-r8a779a0 # R-Car V3U
          - renesas,tmu-r8a779f0 # R-Car S4-8
          - renesas,tmu-r8a779g0 # R-Car V4H
      - const: renesas,tmu

  reg:
    maxItems: 1

  interrupts:
    minItems: 2
    maxItems: 3

  clocks:
    maxItems: 1

  clock-names:
    const: fck

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  '#renesas,channels':
    description:
      Number of channels implemented by the timer.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 2, 3 ]
    default: 3

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains

if:
  not:
    properties:
      compatible:
        contains:
          enum:
            - renesas,tmu-r8a7740
            - renesas,tmu-r8a7778
            - renesas,tmu-r8a7779
then:
  required:
    - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7779-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7779-sysc.h>
    tmu0: timer@ffd80000 {
            compatible = "renesas,tmu-r8a7779", "renesas,tmu";
            reg = <0xffd80000 0x30>;
            interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
            clock-names = "fck";
            power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
            #renesas,channels = <3>;
    };