code:
// SPDX-License-Identifier: GPL-2.0-only

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/dm816.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/omap.h>

/ {
	compatible = "ti,dm816";
	interrupt-parent = <&intc>;
	#address-cells = <1>;
	#size-cells = <1>;
	chosen { };

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		ethernet0 = &eth0;
		ethernet1 = &eth1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "arm,cortex-a8";
			device_type = "cpu";
			reg = <0>;
		};
	};

	pmu {
		compatible = "arm,cortex-a8-pmu";
		interrupts = <3>;
	};

	/*
	 * The soc node represents the soc top level view. It is used for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap3-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the dm816x interconnect.
	 * The real dm816x interconnect network is quite complex. Since
	 * it will not bring real advantage to represent that in DT
	 * for the moment, just use a fake OCP bus entry to represent
	 * the whole bus hierarchy.
	 */
	ocp {
		compatible = "simple-bus";
		reg = <0x44000000 0x10000>;
		interrupts = <9 10>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		prcm: prcm@48180000 {
			compatible = "ti,dm816-prcm", "simple-bus";
			reg = <0x48180000 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x48180000 0x4000>;

			prcm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			prcm_clockdomains: clockdomains {
			};
		};

		scrm: scrm@48140000 {
			compatible = "ti,dm816-scrm", "simple-bus";
			reg = <0x48140000 0x21000>;
			#address-cells = <1>;
			#size-cells = <1>;
			#pinctrl-cells = <1>;
			ranges = <0 0x48140000 0x21000>;

			dm816x_pinmux: pinmux@800 {
				compatible = "pinctrl-single";
				reg = <0x800 0x50a>;
				#address-cells = <1>;
				#size-cells = <0>;
				#pinctrl-cells = <1>;
				pinctrl-single,register-width = <16>;
				pinctrl-single,function-mask = <0xf>;
			};

			/* Device Configuration Registers */
			scm_conf: syscon@600 {
				compatible = "syscon", "simple-bus";
				reg = <0x600 0x110>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x600 0x110>;

				usb_phy0: usb-phy@20 {
					compatible = "ti,dm8168-usb-phy";
					reg = <0x20 0x8>;
					reg-names = "phy";
					clocks = <&main_fapll 6>;
					clock-names = "refclk";
					#phy-cells = <0>;
					syscon = <&scm_conf>;
				};

				usb_phy1: usb-phy@28 {
					compatible = "ti,dm8168-usb-phy";
					reg = <0x28 0x8>;
					reg-names = "phy";
					clocks = <&main_fapll 6>;
					clock-names = "refclk";
					#phy-cells = <0>;
					syscon = <&scm_conf>;
				};
			};

			scrm_clocks: clocks {
				#address-cells = <1>;
				#size-cells = <0>;
			};

			scrm_clockdomains: clockdomains {
			};
		};

		target-module@49000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49000000 0x4>;
			reg-names = "rev";
			clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49000000 0x10000>;

			edma: dma@0 {
				compatible = "ti,edma3-tpcc";
				reg = <0 0x10000>;
				reg-names = "edma3_cc";
				interrupts = <12 13 14>;
				interrupt-names = "edma3_ccint", "edma3_mperr",
						  "edma3_ccerrint";
				dma-requests = <64>;
				#dma-cells = <2>;

				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
					   <&edma_tptc2 3>, <&edma_tptc3 0>;

				ti,edma-memcpy-channels = <20 21>;
			};
		};

		target-module@49800000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49800000 0x4>,
			      <0x49800010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49800000 0x100000>;

			edma_tptc0: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <112>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@49900000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49900000 0x4>,
			      <0x49900010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49900000 0x100000>;

			edma_tptc1: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <113>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@49a00000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49a00000 0x4>,
			      <0x49a00010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49a00000 0x100000>;

			edma_tptc2: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <114>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@49b00000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x49b00000 0x4>,
			      <0x49b00010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-midle = <SYSC_IDLE_FORCE>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_SMART>;
			clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x49b00000 0x100000>;

			edma_tptc3: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <115>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		elm: elm@48080000 {
			compatible = "ti,am3352-elm";
			ti,hwmods = "elm";
			reg = <0x48080000 0x2000>;
			interrupts = <4>;
		};

		gpio1: gpio@48032000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio1";
			ti,gpio-always-on;
			reg = <0x48032000 0x1000>;
			interrupts = <96>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@4804c000 {
			compatible = "ti,omap4-gpio";
			ti,hwmods = "gpio2";
			ti,gpio-always-on;
			reg = <0x4804c000 0x1000>;
			interrupts = <98>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,am3352-gpmc";
			ti,hwmods = "gpmc";
			reg = <0x50000000 0x2000>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupts = <100>;
			dmas = <&edma 52 0>;
			dma-names = "rxtx";
			gpmc,num-cs = <6>;
			gpmc,num-waitpins = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		i2c1: i2c@48028000 {
			compatible = "ti,omap4-i2c";
			ti,hwmods = "i2c1";
			reg = <0x48028000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <70>;
		};

		i2c2: i2c@4802a000 {
			compatible = "ti,omap4-i2c";
			ti,hwmods = "i2c2";
			reg = <0x4802a000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <71>;
		};

		intc: interrupt-controller@48200000 {
			compatible = "ti,dm816-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x48200000 0x1000>;
		};

		rtc: rtc@480c0000 {
			compatible = "ti,am3352-rtc", "ti,da830-rtc";
			reg = <0x480c0000 0x1000>;
			interrupts = <75 76>;
			ti,hwmods = "rtc";
		};

		mailbox: mailbox@480c8000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x480c8000 0x2000>;
			interrupts = <77>;
			ti,hwmods = "mailbox";
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <12>;
			mbox_dsp: mbox-dsp {
				ti,mbox-tx = <3 0 0>;
				ti,mbox-rx = <0 0 0>;
			};
		};

		spinbox: spinbox@480ca000 {
			compatible = "ti,omap4-hwspinlock";
			reg = <0x480ca000 0x2000>;
			ti,hwmods = "spinbox";
			#hwlock-cells = <1>;
		};

		mdio: mdio@4a100800 {
			compatible = "ti,davinci_mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x4a100800 0x100>;
			ti,hwmods = "davinci_mdio";
			bus_freq = <1000000>;
			phy0: ethernet-phy@0 {
				reg = <1>;
			};
			phy1: ethernet-phy@1 {
				reg = <2>;
			};
		};

		eth0: ethernet@4a100000 {
			compatible = "ti,dm816-emac";
			ti,hwmods = "emac0";
			reg = <0x4a100000 0x800
			       0x4a100900 0x3700>;
			clocks = <&sysclk24_ck>;
			syscon = <&scm_conf>;
			ti,davinci-ctrl-reg-offset = <0>;
			ti,davinci-ctrl-mod-reg-offset = <0x900>;
			ti,davinci-ctrl-ram-offset = <0x2000>;
			ti,davinci-ctrl-ram-size = <0x2000>;
			interrupts = <40 41 42 43>;
			phy-handle = <&phy0>;
		};

		eth1: ethernet@4a120000 {
			compatible = "ti,dm816-emac";
			ti,hwmods = "emac1";
			reg = <0x4a120000 0x4000>;
			clocks = <&sysclk24_ck>;
			syscon = <&scm_conf>;
			ti,davinci-ctrl-reg-offset = <0>;
			ti,davinci-ctrl-mod-reg-offset = <0x900>;
			ti,davinci-ctrl-ram-offset = <0x2000>;
			ti,davinci-ctrl-ram-size = <0x2000>;
			interrupts = <44 45 46 47>;
			phy-handle = <&phy1>;
		};

		sata: sata@4a140000 {
			compatible = "ti,dm816-ahci";
			reg = <0x4a140000 0x10000>;
			interrupts = <16>;
			ti,hwmods = "sata";
		};

		mcspi1: spi@48030000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48030000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <65>;
			ti,spi-num-cs = <4>;
			ti,hwmods = "mcspi1";
			dmas = <&edma 16 0 &edma 17 0
				&edma 18 0 &edma 19 0
				&edma 20 0 &edma 21 0
				&edma 22 0 &edma 23 0>;
			dma-names = "tx0", "rx0", "tx1", "rx1",
				    "tx2", "rx2", "tx3", "rx3";
		};

		mmc1: mmc@48060000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x48060000 0x11000>;
			ti,hwmods = "mmc1";
			interrupts = <64>;
			dmas = <&edma 24 0 &edma 25 0>;
			dma-names = "tx", "rx";
		};

		timer1_target: target-module@4802e000 {
			compatible = "ti,sysc-omap4-timer", "ti,sysc";
			reg = <0x4802e000 0x4>,
			      <0x4802e010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4802e000 0x1000>;

			timer1: timer@0 {
				compatible = "ti,dm816-timer";
				reg = <0 0x1000>;
				interrupts = <67>;
				ti,timer-alwon;
				clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
				clock-names = "fck";
			};
		};

		timer2_target: target-module@48040000 {
			compatible = "ti,sysc-omap4-timer", "ti,sysc";
			reg = <0x48040000 0x4>,
			      <0x48040010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x48040000 0x1000>;

			timer2: timer@0 {
				compatible = "ti,dm816-timer";
				reg = <0 0x1000>;
				interrupts = <68>;
				clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
				clock-names = "fck";
			};
		};

		timer3: timer@48042000 {
			compatible = "ti,dm816-timer";
			reg = <0x48042000 0x2000>;
			interrupts = <69>;
			ti,hwmods = "timer3";
		};

		timer4: timer@48044000 {
			compatible = "ti,dm816-timer";
			reg = <0x48044000 0x2000>;
			interrupts = <92>;
			ti,hwmods = "timer4";
			ti,timer-pwm;
		};

		timer5: timer@48046000 {
			compatible = "ti,dm816-timer";
			reg = <0x48046000 0x2000>;
			interrupts = <93>;
			ti,hwmods = "timer5";
			ti,timer-pwm;
		};

		timer6: timer@48048000 {
			compatible = "ti,dm816-timer";
			reg = <0x48048000 0x2000>;
			interrupts = <94>;
			ti,hwmods = "timer6";
			ti,timer-pwm;
		};

		timer7: timer@4804a000 {
			compatible = "ti,dm816-timer";
			reg = <0x4804a000 0x2000>;
			interrupts = <95>;
			ti,hwmods = "timer7";
			ti,timer-pwm;
		};

		uart1: uart@48020000 {
			compatible = "ti,am3352-uart", "ti,omap3-uart";
			ti,hwmods = "uart1";
			reg = <0x48020000 0x2000>;
			clock-frequency = <48000000>;
			interrupts = <72>;
			dmas = <&edma 26 0 &edma 27 0>;
			dma-names = "tx", "rx";
		};

		uart2: uart@48022000 {
			compatible = "ti,am3352-uart", "ti,omap3-uart";
			ti,hwmods = "uart2";
			reg = <0x48022000 0x2000>;
			clock-frequency = <48000000>;
			interrupts = <73>;
			dmas = <&edma 28 0 &edma 29 0>;
			dma-names = "tx", "rx";
		};

		uart3: uart@48024000 {
			compatible = "ti,am3352-uart", "ti,omap3-uart";
			ti,hwmods = "uart3";
			reg = <0x48024000 0x2000>;
			clock-frequency = <48000000>;
			interrupts = <74>;
			dmas = <&edma 30 0 &edma 31 0>;
			dma-names = "tx", "rx";
		};

		/* NOTE: USB needs a transceiver driver for phys to work */
		usb: usb_otg_hs@47401000 {
			compatible = "ti,am33xx-usb";
			reg = <0x47401000 0x400000>;
			ranges;
			#address-cells = <1>;
			#size-cells = <1>;
			ti,hwmods = "usb_otg_hs";

			usb0: usb@47401000 {
				compatible = "ti,musb-dm816";
				reg = <0x47401400 0x400
				       0x47401000 0x200>;
				reg-names = "mc", "control";
				interrupts = <18>;
				interrupt-names = "mc";
				dr_mode = "host";
				interface-type = <0>;
				phys = <&usb_phy0>;
				phy-names = "usb2-phy";
				mentor,multipoint = <1>;
				mentor,num-eps = <16>;
				mentor,ram-bits = <12>;
				mentor,power = <500>;

				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
					&cppi41dma  2 0 &cppi41dma  3 0
					&cppi41dma  4 0 &cppi41dma  5 0
					&cppi41dma  6 0 &cppi41dma  7 0
					&cppi41dma  8 0 &cppi41dma  9 0
					&cppi41dma 10 0 &cppi41dma 11 0
					&cppi41dma 12 0 &cppi41dma 13 0
					&cppi41dma 14 0 &cppi41dma  0 1
					&cppi41dma  1 1 &cppi41dma  2 1
					&cppi41dma  3 1 &cppi41dma  4 1
					&cppi41dma  5 1 &cppi41dma  6 1
					&cppi41dma  7 1 &cppi41dma  8 1
					&cppi41dma  9 1 &cppi41dma 10 1
					&cppi41dma 11 1 &cppi41dma 12 1
					&cppi41dma 13 1 &cppi41dma 14 1>;
				dma-names =
					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
					"rx14", "rx15",
					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
					"tx14", "tx15";
			};

			usb1: usb@47401800 {
				compatible = "ti,musb-dm816";
				reg = <0x47401c00 0x400
				       0x47401800 0x200>;
				reg-names = "mc", "control";
				interrupts = <19>;
				interrupt-names = "mc";
				dr_mode = "host";
				interface-type = <0>;
				phys = <&usb_phy1>;
				phy-names = "usb2-phy";
				mentor,multipoint = <1>;
				mentor,num-eps = <16>;
				mentor,ram-bits = <12>;
				mentor,power = <500>;

				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
					&cppi41dma 17 0 &cppi41dma 18 0
					&cppi41dma 19 0 &cppi41dma 20 0
					&cppi41dma 21 0 &cppi41dma 22 0
					&cppi41dma 23 0 &cppi41dma 24 0
					&cppi41dma 25 0 &cppi41dma 26 0
					&cppi41dma 27 0 &cppi41dma 28 0
					&cppi41dma 29 0 &cppi41dma 15 1
					&cppi41dma 16 1 &cppi41dma 17 1
					&cppi41dma 18 1 &cppi41dma 19 1
					&cppi41dma 20 1 &cppi41dma 21 1
					&cppi41dma 22 1 &cppi41dma 23 1
					&cppi41dma 24 1 &cppi41dma 25 1
					&cppi41dma 26 1 &cppi41dma 27 1
					&cppi41dma 28 1 &cppi41dma 29 1>;
				dma-names =
					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
					"rx14", "rx15",
					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
					"tx14", "tx15";
			};

			cppi41dma: dma-controller@47402000 {
				compatible = "ti,am3359-cppi41";
				reg =  <0x47400000 0x1000
					0x47402000 0x1000
					0x47403000 0x1000
					0x47404000 0x4000>;
				reg-names = "glue", "controller", "scheduler", "queuemgr";
				interrupts = <17>;
				interrupt-names = "glue";
				#dma-cells = <2>;
				/* For backwards compatibility: */
				#dma-channels = <30>;
				dma-channels = <30>;
				#dma-requests = <256>;
				dma-requests = <256>;
			};
		};

		wd_timer2: wd_timer@480c2000 {
			compatible = "ti,omap3-wdt";
			ti,hwmods = "wd_timer";
			reg = <0x480c2000 0x1000>;
			interrupts = <0>;
		};
	};
};

#include "dm816x-clocks.dtsi"

/* Preferred always-on timer for clocksource */
&timer1_target {
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&timer1_fck>;
		assigned-clock-parents = <&sys_clkin_ck>;
	};
};

/* Preferred timer for clockevent */
&timer2_target {
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&timer2_fck>;
		assigned-clock-parents = <&sys_clkin_ck>;
	};
};


code:
/*
 * Device Tree include for Compulab CM-A510 System-on-Module
 *
 * Copyright (C) 2015, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; version 2 of the
 *     License.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * The CM-A510 comes with several optional components:
 *
 * Memory options:
 *  D512: 512M
 *  D1024: 1G
 *
 * NAND options:
 *  N512: 512M NAND
 *
 * Ethernet options:
 *  E1: PHY RTL8211D on internal GbE (SMI address 0x03)
 *  E2: Additional ethernet NIC RTL8111D on PCIe1
 *
 * Audio options:
 *  A: TI TLV320AIC23b audio codec (I2C address 0x1a)
 *
 * Touchscreen options:
 *  I: TI TSC2046 touchscreen controller (on SPI1)
 *
 * USB options:
 *  U2: 2 dual-role USB2.0 ports
 *  U4: 2 additional USB2.0 host ports (via USB1)
 *
 * WiFi options:
 *  W: Broadcom BCM4319 802.11b/g/n (USI WM-N-BM-01 on SDIO1)
 *
 * GPIOs used on CM-A510:
 *   1 GbE PHY reset (active low)
 *   3 WakeUp
 *   8 PowerOff (active low)
 *  13 Touchscreen pen irq (active low)
 *  65 System LED (active high)
 *  69 USB Hub reset (active low)
 *  70 WLAN reset (active low)
 *  71 WLAN regulator (active high)
 */

#include "dove.dtsi"

/ {
	model = "Compulab CM-A510";
	compatible = "compulab,cm-a510", "marvell,dove";

	/*
	 * Set the minimum memory size here and let the
	 * bootloader set the real size.
	 */
	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;
	};

	leds {
		compatible = "gpio-leds";
		/* Set upper NAND data bit to GPO */
		pinctrl-0 = <&pmx_nand_gpo>;
		pinctrl-names = "default";

		system {
			label = "cm-a510:system:green";
			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
			default-state = "keep";
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		wifi_power: regulator@1 {
			compatible = "regulator-fixed";
			regulator-name = "WiFi Power";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
		};
	};
};

/* Optional RTL8211D GbE PHY on SMI address 0x03 */
&ethphy {
	reg = <3>;
	status = "disabled";
};

&i2c0 {
	/* Optional TI TLV320AIC23b audio codec */
	opt_audio: audio@1a {
		compatible = "ti,tlv320aic23";
		reg = <0x1a>;
		status = "disabled";
	};
};

/* Optional RTL8111D GbE NIC on PCIe1 */
&pcie { status = "disabled"; };

&pcie1 {
	pinctrl-0 = <&pmx_pcie1_clkreq>;
	pinctrl-names = "default";
	status = "disabled";
};

&pinctrl {
	pmx_uart2: pmx-uart2 {
		marvell,pins = "mpp14", "mpp15";
		marvell,function = "uart2";
	};
};

/* Optional Broadcom BCM4319 802.11b/g/n WiFi module */
&sdio1 {
	non-removable;
	vmmc-supply = <&wifi_power>;
	reset-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
	status = "disabled";
};

&spi0 {
	status = "okay";

	/* 1M Flash Winbond W25Q80BL */
	flash@0 {
		compatible = "winbond,w25q80";
		spi-max-frequency = <80000000>;
		reg = <0>;
	};
};

&spi1 {
	pinctrl-0 = <&pmx_spi1_20_23>;
	pinctrl-names = "default";
	status = "disabled";

	/* Optional TI TSC2046 touchscreen controller */
	opt_touch: touchscreen@0 {
		compatible = "ti,tsc2046";
		spi-max-frequency = <2500000>;
		reg = <0>;
		pinctrl-0 = <&pmx_gpio_13>;
		pinctrl-names = "default";
		interrupts-extended = <&gpio0 13 IRQ_TYPE_EDGE_FALLING>;
	};
};

&uart2 {
	pinctrl-0 = <&pmx_uart2>;
	pinctrl-names = "default";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
#include "dove-cubox.dts"

/ {
	model = "SolidRun CuBox (Engineering Sample)";
	compatible = "solidrun,cubox-es", "solidrun,cubox", "marvell,dove";
};

&sdio0 {
	/* sdio0 card detect is connected to wrong pin on CuBox ES */
	cd-gpios = <&gpio0 12 1>;
	pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>;
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include "dove.dtsi"

/ {
	model = "SolidRun CuBox";
	compatible = "solidrun,cubox", "marvell,dove";

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 earlyprintk";
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pmx_gpio_18>;
		pinctrl-names = "default";

		power {
			label = "Power";
			gpios = <&gpio0 18 1>;
			default-state = "keep";
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		usb_power: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "USB Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio0 1 0>;
			pinctrl-0 = <&pmx_gpio_1>;
			pinctrl-names = "default";
		};
	};

	clocks {
		/* 25MHz reference crystal */
		ref25: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};

	ir_recv: ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <&gpio0 19 1>;
		pinctrl-0 = <&pmx_gpio_19>;
		pinctrl-names = "default";
	};

	gpu-subsystem {
		status = "okay";
	};
};

&uart0 { status = "okay"; };
&sata0 { status = "okay"; };
&mdio { status = "okay"; };
&eth { status = "okay"; };

&ethphy {
	compatible = "marvell,88e1310";
	reg = <1>;
};

&gpu {
	status = "okay";
};

&i2c0 {
	status = "okay";
	clock-frequency = <100000>;

	si5351: clock-generator@60 {
		compatible = "silabs,si5351a-msop";
		reg = <0x60>;
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;

		/* connect xtal input to 25MHz reference */
		clocks = <&ref25>;
		clock-names = "xtal";

		/* connect xtal input as source of pll0 and pll1 */
		silabs,pll-source = <0 0>, <1 0>;

		clkout0 {
			reg = <0>;
			silabs,drive-strength = <8>;
			silabs,multisynth-source = <0>;
			silabs,clock-source = <0>;
			silabs,pll-master;
		};

		clkout2 {
			reg = <2>;
			silabs,drive-strength = <8>;
			silabs,multisynth-source = <1>;
			silabs,clock-source = <0>;
			silabs,pll-master;
		};
	};
};

&sdio0 {
	status = "okay";
};

&spi0 {
	status = "okay";

	/* spi0.0: 4M Flash Winbond W25Q32BV */
	flash@0 {
		compatible = "st,w25q32";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&audio1 {
	status = "okay";
	clocks = <&gate_clk 13>, <&si5351 2>;
	clock-names = "internal", "extclk";
	pinctrl-0 = <&pmx_audio1_i2s1_spdifo &pmx_audio1_extclk>;
	pinctrl-names = "default";
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include "dove.dtsi"

/ {
	model = "Globalscale D2Plug";
	compatible = "globalscale,d2plug", "marvell,dove";

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 earlyprintk";
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>;
		pinctrl-names = "default";

		wlan-ap {
			label = "wlan-ap";
			gpios = <&gpio0 0 1>;
		};

		wlan-act {
			label = "wlan-act";
			gpios = <&gpio0 1 1>;
		};

		bluetooth-act {
			label = "bt-act";
			gpios = <&gpio0 2 1>;
		};
	};
};

&uart0 { status = "okay"; };
&sata0 { status = "okay"; };
&i2c0 { status = "okay"; };
&mdio { status = "okay"; };
&eth { status = "okay"; };

/* Samsung M8G2F eMMC */
&sdio0 {
	status = "okay";
	non-removable;
	bus-width = <4>;
};

/* Marvell SD8787 WLAN/BT */
&sdio1 {
	status = "okay";
	non-removable;
	bus-width = <4>;
};

&spi0 {
	status = "okay";

	/* spi0.0: 4M Flash Macronix MX25L3205D */
	flash@0 {
		compatible = "st,m25l3205d";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include "dove.dtsi"

/ {
	model = "Globalscale D3Plug";
	compatible = "globalscale,d3plug", "marvell,dove";

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p2 rw rootwait";
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>;
		pinctrl-names = "default";

		wlan-act {
			label = "wlan-act";
			gpios = <&gpio0 0 1>;
		};

		wlan-ap {
			label = "wlan-ap";
			gpios = <&gpio0 1 1>;
		};

		status {
			label = "status";
			gpios = <&gpio0 2 1>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		usb_power: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "USB Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio0 8 0>;
			pinctrl-0 = <&pmx_gpio_8>;
			pinctrl-names = "default";
		};
	};
};

&uart0 { status = "okay"; };
&sata0 { status = "okay"; };
&i2c0 { status = "okay"; };

/* Samsung M8G2F eMMC */
&sdio0 {
	status = "okay";
	non-removable;
	bus-width = <4>;
};

/* Marvell SD8787 WLAN/BT */
&sdio1 {
	status = "okay";
	non-removable;
};

&spi0 {
	status = "okay";

	/* spi0.0: 2M Flash Macronix MX25L1605D */
	flash@0 {
		compatible = "st,m25l1605d";
		spi-max-frequency = <86000000>;
		reg = <0>;
	};
};

&pcie {
	status = "okay";
	/* Fresco Logic USB3.0 xHCI controller */
	pcie@1 {
		status = "okay";
		reset-gpios = <&gpio0 26 1>;
		reset-delay-us = <20000>;
		pinctrl-0 = <&pmx_camera_gpio>;
		pinctrl-names = "default";
	};
	/* Mini-PCIe slot */
	pcie@2 {
		status = "okay";
		reset-gpios = <&gpio0 25 1>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include "dove.dtsi"

/ {
	model = "Marvell DB-MV88AP510-BP Development Board";
	compatible = "marvell,dove-db", "marvell,dove";

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 earlyprintk";
	};
};

&uart0 { status = "okay"; };
&uart1 { status = "okay"; };
&sdio0 { status = "okay"; };
&sdio1 { status = "okay"; };
&sata0 { status = "okay"; };

&spi0 {
	status = "okay";

	/* spi0.0: 4M Flash ST-M25P32-VMF6P */
	flash@0 {
		compatible = "st,m25p32";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&i2c0 {
	  status = "okay";
};


code:
/*
 * Device Tree file for Compulab SBC-A510 Single Board Computer
 *
 * Copyright (C) 2015, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; version 2 of the
 *     License.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * SBC-A510 comprises a PCA9555 I2C GPIO expander its GPIO lines connected to
 *
 * 0.0 USB0 VBUS_EN (active high)
 * 0.1 USB0 VBUS_GOOD
 * 0.2 DVI transmitter TI TFP410 MSEN
 * 0.3 DVI transmitter TI TFP410 PD# (active low power down)
 * 0.4 LVDS transmitter DS90C365 PD# (active low power down)
 * 0.5 LCD nRST (active low reset)
 * 0.6 PCIe0 nRST (active low reset)
 * 0.7 mini-PCIe slot W_DISABLE#
 *
 * 1.0 MMC WP
 * 1.1 Camera Input FPC FLASH_STB and P21.5
 * 1.2 Camera Input FPC WE        and P21.22
 * 1.3 MMC VCC_EN (active high)   and P21.7
 * 1.4 Camera Input FPC AFTR_RST  and P21.17
 * 1.5 Camera Input FPC OE        and P21.19
 * 1.6 Camera Input FPC SNPSHT    and P21.6
 * 1.7 Camera Input FPC SHTR      and P21.10
 */

/dts-v1/;

#include "dove-cm-a510.dtsi"

/ {
	model = "Compulab SBC-A510";
	compatible = "compulab,sbc-a510", "compulab,cm-a510", "marvell,dove";

	chosen {
		stdout-path = &uart0;
	};

	regulators {
		usb0_power: regulator@2 {
			compatible = "regulator-fixed";
			regulator-name = "USB Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio_ext 0 GPIO_ACTIVE_HIGH>;
		};

		mmc_power: regulator@3 {
			compatible = "regulator-fixed";
			regulator-name = "MMC Power";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio_ext 13 GPIO_ACTIVE_HIGH>;
		};
	};
};

/* Ethernet0 depends on CM-A510 option E1 */
&mdio { status = "disabled"; };
&eth { status = "disabled"; };
&ethphy { status = "disabled"; };

/*
 * USB port 0 can be powered and monitored by I2C GPIO expander:
 *  VBUS_ENABLE on GPIO0, VBUS_GOOD on GPIO1
 */
&ehci0 {
	status = "okay";
	vbus-supply = <&usb0_power>;
};

/* USB port 1 (and ports 2, 3 if CM-A510 has U4 option) */
&ehci1 { status = "okay"; };

/*
 * I2C bus layout:
 * i2c0:
 *  - Audio Codec, 0x1a (option from CM-A510)
 *  - DVI transmitter TI TFP410, 0x39
 *  - HDMI/DVI DDC channel
 * i2c1:
 *  - GPIO expander, NXP PCA9555, 0x20
 *  - VGA DDC channel
 */
&i2c {
	pinctrl-0 = <&pmx_i2c1>;
	pinctrl-names = "default";
};

&i2c0 {
	/* TI TFP410 DVI transmitter */
	dvi: video@39 {
		compatible = "ti,tfp410";
		reg = <0x39>;
		powerdown-gpio = <&gpio_ext 3 GPIO_ACTIVE_LOW>;
	};
};

&i2c1 {
	status = "okay";

	/* NXP PCA9555 GPIO expander */
	gpio_ext: gpio@20 {
		compatible = "nxp,pca9555";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&pcie { status = "okay"; };

/*
 * PCIe0 can be configured by Jumper E1 to be either connected to
 * a mini-PCIe slot or a Pericom PI7C9X111 PCIe-to-PCI bridge.
 */
&pcie0 {
	status = "okay";
	pinctrl-0 = <&pmx_pcie0_clkreq>;
	pinctrl-names = "default";
	reset-gpios = <&gpio_ext 6 GPIO_ACTIVE_LOW>;
};

/* Ethernet1 depends on CM-A510 option E2 */
&pcie1 { status = "disabled"; };

/* SATA connector */
&sata0 { status = "okay"; };

/*
 * SDIO0 is connected to a MMC/SD/SDIO socket, I2C GPIO expander has
 *  VCC_MMC_ENABLE on GPIO13, MMC_WP on GPIO10
 */
&sdio0 {
	vmmc-supply = <&mmc_power>;
	wp-gpios = <&gpio_ext 10 GPIO_ACTIVE_LOW>;
	status = "okay";
};

/* UART0 on RS232 mini-connector */
&uart0 { status = "okay"; };
/* UART2 on pin headers */
&uart2 { status = "okay"; };


code:
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "marvell,dove";
	model = "Marvell Armada 88AP510 SoC";
	interrupt-parent = <&intc>;

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "marvell,pj4a", "marvell,sheeva-v7";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};
	};

	l2: l2-cache {
		compatible = "marvell,tauros2-cache";
		marvell,tauros2-cache-features = <0>;
	};

	gpu-subsystem {
		compatible = "marvell,dove-gpu-subsystem";
		cores = <&gpu>;
		status = "disabled";
	};

	i2c-mux {
		compatible = "i2c-mux-pinctrl";
		#address-cells = <1>;
		#size-cells = <0>;

		i2c-parent = <&i2c>;

		pinctrl-names = "i2c0", "i2c1", "i2c2";
		pinctrl-0 = <&pmx_i2cmux_0>;
		pinctrl-1 = <&pmx_i2cmux_1>;
		pinctrl-2 = <&pmx_i2cmux_2>;

		i2c0: i2c@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "okay";
		};

		i2c1: i2c@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			/* Requires pmx_i2c1 on i2c controller node */
			status = "disabled";
		};

		i2c2: i2c@2 {
			reg = <2>;
			#address-cells = <1>;
			#size-cells = <0>;
			/* Requires pmx_i2c2 on i2c controller node */
			status = "disabled";
		};
	};

	mbus {
		compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
		pcie-io-aperture  = <0xf2000000 0x00200000>; /*   2M I/O space */

		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000   /* MBUS regs  1M */
			  MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000   /* AXI  regs 16M */
			  MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000   /* BootROM  128M */
			  MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000   /* CESA SRAM  1M */
			  MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU  SRAM  1M */

		pcie: pcie {
			compatible = "marvell,dove-pcie";
			status = "disabled";
			device_type = "pci";
			#address-cells = <3>;
			#size-cells = <2>;

			msi-parent = <&intc>;
			bus-range = <0x00 0xff>;

			ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
			          0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
				  0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0   /* Port 0.0 Mem */
				  0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0   /* Port 0.0 I/O */
				  0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0   /* Port 1.0 Mem */
				  0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */

			pcie0: pcie@1 {
				device_type = "pci";
				status = "disabled";
				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
				reg = <0x0800 0 0 0 0>;
				clocks = <&gate_clk 4>;
				marvell,pcie-port = <0>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
				          0x81000000 0 0 0x81000000 0x1 0 1 0>;
				bus-range = <0x00 0xff>;

				#interrupt-cells = <1>;
				interrupt-names = "intx", "error";
				interrupts = <16>, <15>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie0_intc 0>,
						<0 0 0 2 &pcie0_intc 1>,
						<0 0 0 3 &pcie0_intc 2>,
						<0 0 0 4 &pcie0_intc 3>;

				pcie0_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};

			pcie1: pcie@2 {
				device_type = "pci";
				status = "disabled";
				assigned-addresses = <0x82001000 0 0x80000 0 0x2000>;
				reg = <0x1000 0 0 0 0>;
				clocks = <&gate_clk 5>;
				marvell,pcie-port = <1>;

				#address-cells = <3>;
				#size-cells = <2>;
				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
				          0x81000000 0 0 0x81000000 0x2 0 1 0>;
				bus-range = <0x00 0xff>;

				#interrupt-cells = <1>;
				interrupt-names = "intx", "error";
				interrupts = <18>, <17>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
						<0 0 0 2 &pcie1_intc 1>,
						<0 0 0 3 &pcie1_intc 2>,
						<0 0 0 4 &pcie1_intc 3>;

				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#interrupt-cells = <1>;
				};
			};
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000   /* MBUS regs  1M */
				  0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000   /* AXI  regs 16M */
				  0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800   /* CESA SRAM  2k */
				  0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU  SRAM  2k */

			spi0: spi@10600 {
				compatible = "marvell,orion-spi";
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <6>;
				reg = <0x10600 0x28>;
				clocks = <&core_clk 0>;
				pinctrl-0 = <&pmx_spi0>;
				pinctrl-names = "default";
				status = "disabled";
			};

			i2c: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <11>;
				clock-frequency = <400000>;
				clocks = <&core_clk 0>;
				status = "okay";
			};

			uart0: serial@12000 {
				compatible = "ns16550a";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <7>;
				clocks = <&core_clk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "ns16550a";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <8>;
				clocks = <&core_clk 0>;
				pinctrl-0 = <&pmx_uart1>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart2: serial@12200 {
				compatible = "ns16550a";
				reg = <0x12200 0x100>;
				reg-shift = <2>;
				interrupts = <9>;
				clocks = <&core_clk 0>;
				status = "disabled";
			};

			uart3: serial@12300 {
				compatible = "ns16550a";
				reg = <0x12300 0x100>;
				reg-shift = <2>;
				interrupts = <10>;
				clocks = <&core_clk 0>;
				status = "disabled";
			};

			spi1: spi@14600 {
				compatible = "marvell,orion-spi";
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <1>;
				interrupts = <5>;
				reg = <0x14600 0x28>;
				clocks = <&core_clk 0>;
				status = "disabled";
			};

			mbusc: mbus-ctrl@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x80>, <0x800100 0x8>;
			};

			sysc: system-ctrl@20000 {
				compatible = "marvell,orion-system-controller";
				reg = <0x20000 0x110>;
			};

			bridge_intc: bridge-interrupt-ctrl@20110 {
				compatible = "marvell,orion-bridge-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x20110 0x8>;
				interrupts = <0>;
				marvell,#interrupts = <5>;
			};

			intc: interrupt-controller@20200 {
				compatible = "marvell,orion-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
				reg = <0x20200 0x10>, <0x20210 0x10>;
			};

			timer: timer@20300 {
				compatible = "marvell,orion-timer";
				reg = <0x20300 0x20>;
				interrupt-parent = <&bridge_intc>;
				interrupts = <1>, <2>;
				clocks = <&core_clk 0>;
			};

			watchdog@20300 {
				compatible = "marvell,orion-wdt";
				reg = <0x20300 0x28>, <0x20108 0x4>;
				interrupt-parent = <&bridge_intc>;
				interrupts = <3>;
				clocks = <&core_clk 0>;
			};

			crypto: crypto-engine@30000 {
				compatible = "marvell,dove-crypto";
				reg = <0x30000 0x10000>;
				reg-names = "regs";
				interrupts = <31>;
				clocks = <&gate_clk 15>;
				marvell,crypto-srams = <&crypto_sram>;
				marvell,crypto-sram-size = <0x800>;
				status = "okay";
			};

			ehci0: usb-host@50000 {
				compatible = "marvell,orion-ehci";
				reg = <0x50000 0x1000>;
				interrupts = <24>;
				clocks = <&gate_clk 0>;
				status = "okay";
			};

			ehci1: usb-host@51000 {
				compatible = "marvell,orion-ehci";
				reg = <0x51000 0x1000>;
				interrupts = <25>;
				clocks = <&gate_clk 1>;
				status = "okay";
			};

			xor0: dma-engine@60800 {
				compatible = "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60a00 0x100>;
				clocks = <&gate_clk 23>;
				status = "okay";

				channel0 {
					interrupts = <39>;
					dmacap,memcpy;
					dmacap,xor;
				};

				channel1 {
					interrupts = <40>;
					dmacap,memcpy;
					dmacap,xor;
				};
			};

			xor1: dma-engine@60900 {
				compatible = "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gate_clk 24>;
				status = "okay";

				channel0 {
					interrupts = <42>;
					dmacap,memcpy;
					dmacap,xor;
				};

				channel1 {
					interrupts = <43>;
					dmacap,memcpy;
					dmacap,xor;
				};
			};

			sdio1: sdio-host@90000 {
				compatible = "marvell,dove-sdhci";
				reg = <0x90000 0x100>;
				interrupts = <36>, <38>;
				clocks = <&gate_clk 9>;
				pinctrl-0 = <&pmx_sdio1>;
				pinctrl-names = "default";
				status = "disabled";
			};

			eth: ethernet-ctrl@72000 {
				compatible = "marvell,orion-eth";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x72000 0x4000>;
				clocks = <&gate_clk 2>;
				marvell,tx-checksum-limit = <1600>;
				status = "disabled";

				ethernet-port@0 {
					compatible = "marvell,orion-eth-port";
					reg = <0>;
					interrupts = <29>;
					/* overwrite MAC address in bootloader */
					local-mac-address = [00 00 00 00 00 00];
					phy-handle = <&ethphy>;
				};
			};

			mdio: mdio-bus@72004 {
				compatible = "marvell,orion-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x72004 0x84>;
				interrupts = <30>;
				clocks = <&gate_clk 2>;
				status = "disabled";

				ethphy: ethernet-phy {
					/* set phy address in board file */
				};
			};

			sdio0: sdio-host@92000 {
				compatible = "marvell,dove-sdhci";
				reg = <0x92000 0x100>;
				interrupts = <35>, <37>;
				clocks = <&gate_clk 8>;
				pinctrl-0 = <&pmx_sdio0>;
				pinctrl-names = "default";
				status = "disabled";
			};

			sata0: sata-host@a0000 {
				compatible = "marvell,orion-sata";
				reg = <0xa0000 0x2400>;
				interrupts = <62>;
				clocks = <&gate_clk 3>;
				phys = <&sata_phy0>;
				phy-names = "port0";
				nr-ports = <1>;
				status = "disabled";
			};

			sata_phy0: sata-phy@a2000 {
				compatible = "marvell,mvebu-sata-phy";
				reg = <0xa2000 0x0334>;
				clocks = <&gate_clk 3>;
				clock-names = "sata";
				#phy-cells = <0>;
				status = "ok";
			};

			audio0: audio-controller@b0000 {
				compatible = "marvell,dove-audio";
				reg = <0xb0000 0x2210>;
				interrupts = <19>, <20>;
				clocks = <&gate_clk 12>;
				clock-names = "internal";
				status = "disabled";
			};

			audio1: audio-controller@b4000 {
				compatible = "marvell,dove-audio";
				reg = <0xb4000 0x2210>;
				interrupts = <21>, <22>;
				clocks = <&gate_clk 13>;
				clock-names = "internal";
				status = "disabled";
			};

			pmu: power-management@d0000 {
				compatible = "marvell,dove-pmu", "simple-bus";
				reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
				ranges = <0x00000000 0x000d0000 0x8000
					  0x00008000 0x000d8000 0x8000>;
				interrupts = <33>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <1>;
				#interrupt-cells = <1>;
				#reset-cells = <1>;

				domains {
					vpu_domain: vpu-domain {
						#power-domain-cells = <0>;
						marvell,pmu_pwr_mask = <0x00000008>;
						marvell,pmu_iso_mask = <0x00000001>;
						resets = <&pmu 16>;
					};

					gpu_domain: gpu-domain {
						#power-domain-cells = <0>;
						marvell,pmu_pwr_mask = <0x00000004>;
						marvell,pmu_iso_mask = <0x00000002>;
						resets = <&pmu 18>;
					};
				};

				thermal: thermal-diode@1c {
					compatible = "marvell,dove-thermal";
					reg = <0x001c 0x0c>, <0x005c 0x08>;
				};

				gate_clk: clock-gating-ctrl@38 {
					compatible = "marvell,dove-gating-clock";
					reg = <0x0038 0x4>;
					clocks = <&core_clk 0>;
					#clock-cells = <1>;
				};

				divider_clk: core-clock@64 {
					compatible = "marvell,dove-divider-clock";
					reg = <0x0064 0x8>;
					#clock-cells = <1>;
				};

				pinctrl: pin-ctrl@200 {
					compatible = "marvell,dove-pinctrl";
					reg = <0x0200 0x14>,
					      <0x0440 0x04>;
					clocks = <&gate_clk 22>;

					pmx_gpio_0: pmx-gpio-0 {
						marvell,pins = "mpp0";
						marvell,function = "gpio";
					};

					pmx_gpio_1: pmx-gpio-1 {
						marvell,pins = "mpp1";
						marvell,function = "gpio";
					};

					pmx_gpio_2: pmx-gpio-2 {
						marvell,pins = "mpp2";
						marvell,function = "gpio";
					};

					pmx_gpio_3: pmx-gpio-3 {
						marvell,pins = "mpp3";
						marvell,function = "gpio";
					};

					pmx_gpio_4: pmx-gpio-4 {
						marvell,pins = "mpp4";
						marvell,function = "gpio";
					};

					pmx_gpio_5: pmx-gpio-5 {
						marvell,pins = "mpp5";
						marvell,function = "gpio";
					};

					pmx_gpio_6: pmx-gpio-6 {
						marvell,pins = "mpp6";
						marvell,function = "gpio";
					};

					pmx_gpio_7: pmx-gpio-7 {
						marvell,pins = "mpp7";
						marvell,function = "gpio";
					};

					pmx_gpio_8: pmx-gpio-8 {
						marvell,pins = "mpp8";
						marvell,function = "gpio";
					};

					pmx_gpio_9: pmx-gpio-9 {
						marvell,pins = "mpp9";
						marvell,function = "gpio";
					};

					pmx_pcie1_clkreq: pmx-pcie1-clkreq {
						marvell,pins = "mpp9";
						marvell,function = "pex1";
					};

					pmx_gpio_10: pmx-gpio-10 {
						marvell,pins = "mpp10";
						marvell,function = "gpio";
					};

					pmx_gpio_11: pmx-gpio-11 {
						marvell,pins = "mpp11";
						marvell,function = "gpio";
					};

					pmx_pcie0_clkreq: pmx-pcie0-clkreq {
						marvell,pins = "mpp11";
						marvell,function = "pex0";
					};

					pmx_gpio_12: pmx-gpio-12 {
						marvell,pins = "mpp12";
						marvell,function = "gpio";
					};

					pmx_gpio_13: pmx-gpio-13 {
						marvell,pins = "mpp13";
						marvell,function = "gpio";
					};

					pmx_audio1_extclk: pmx-audio1-extclk {
						marvell,pins = "mpp13";
						marvell,function = "audio1";
					};

					pmx_gpio_14: pmx-gpio-14 {
						marvell,pins = "mpp14";
						marvell,function = "gpio";
					};

					pmx_gpio_15: pmx-gpio-15 {
						marvell,pins = "mpp15";
						marvell,function = "gpio";
					};

					pmx_gpio_16: pmx-gpio-16 {
						marvell,pins = "mpp16";
						marvell,function = "gpio";
					};

					pmx_gpio_17: pmx-gpio-17 {
						marvell,pins = "mpp17";
						marvell,function = "gpio";
					};

					pmx_gpio_18: pmx-gpio-18 {
						marvell,pins = "mpp18";
						marvell,function = "gpio";
					};

					pmx_gpio_19: pmx-gpio-19 {
						marvell,pins = "mpp19";
						marvell,function = "gpio";
					};

					pmx_gpio_20: pmx-gpio-20 {
						marvell,pins = "mpp20";
						marvell,function = "gpio";
					};

					pmx_gpio_21: pmx-gpio-21 {
						marvell,pins = "mpp21";
						marvell,function = "gpio";
					};

					pmx_camera: pmx-camera {
						marvell,pins = "mpp_camera";
						marvell,function = "camera";
					};

					pmx_camera_gpio: pmx-camera-gpio {
						marvell,pins = "mpp_camera";
						marvell,function = "gpio";
					};

					pmx_sdio0: pmx-sdio0 {
						marvell,pins = "mpp_sdio0";
						marvell,function = "sdio0";
					};

					pmx_sdio0_gpio: pmx-sdio0-gpio {
						marvell,pins = "mpp_sdio0";
						marvell,function = "gpio";
					};

					pmx_sdio1: pmx-sdio1 {
						marvell,pins = "mpp_sdio1";
						marvell,function = "sdio1";
					};

					pmx_sdio1_gpio: pmx-sdio1-gpio {
						marvell,pins = "mpp_sdio1";
						marvell,function = "gpio";
					};

					pmx_audio1_gpio: pmx-audio1-gpio {
						marvell,pins = "mpp_audio1";
						marvell,function = "gpio";
					};

					pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
						marvell,pins = "mpp_audio1";
						marvell,function = "i2s1/spdifo";
					};

					pmx_spi0: pmx-spi0 {
						marvell,pins = "mpp_spi0";
						marvell,function = "spi0";
					};

					pmx_spi0_gpio: pmx-spi0-gpio {
						marvell,pins = "mpp_spi0";
						marvell,function = "gpio";
					};

					pmx_spi1_4_7: pmx-spi1-4-7 {
						marvell,pins = "mpp4", "mpp5",
							"mpp6", "mpp7";
						marvell,function = "spi1";
					};

					pmx_spi1_20_23: pmx-spi1-20-23 {
						marvell,pins = "mpp20", "mpp21",
							"mpp22", "mpp23";
						marvell,function = "spi1";
					};

					pmx_uart1: pmx-uart1 {
						marvell,pins = "mpp_uart1";
						marvell,function = "uart1";
					};

					pmx_uart1_gpio: pmx-uart1-gpio {
						marvell,pins = "mpp_uart1";
						marvell,function = "gpio";
					};

					pmx_nand: pmx-nand {
						marvell,pins = "mpp_nand";
						marvell,function = "nand";
					};

					pmx_nand_gpo: pmx-nand-gpo {
						marvell,pins = "mpp_nand";
						marvell,function = "gpo";
					};

					pmx_i2c1: pmx-i2c1 {
						marvell,pins = "mpp17", "mpp19";
						marvell,function = "twsi";
					};

					pmx_i2c2: pmx-i2c2 {
						marvell,pins = "mpp_audio1";
						marvell,function = "twsi";
					};

					pmx_ssp_i2c2: pmx-ssp-i2c2 {
						marvell,pins = "mpp_audio1";
						marvell,function = "ssp/twsi";
					};

					pmx_i2cmux_0: pmx-i2cmux-0 {
						marvell,pins = "twsi";
						marvell,function = "twsi-opt1";
					};

					pmx_i2cmux_1: pmx-i2cmux-1 {
						marvell,pins = "twsi";
						marvell,function = "twsi-opt2";
					};

					pmx_i2cmux_2: pmx-i2cmux-2 {
						marvell,pins = "twsi";
						marvell,function = "twsi-opt3";
					};
				};

				core_clk: core-clocks@214 {
					compatible = "marvell,dove-core-clock";
					reg = <0x0214 0x4>;
					#clock-cells = <1>;
				};

				gpio0: gpio-ctrl@400 {
					compatible = "marvell,orion-gpio";
					#gpio-cells = <2>;
					gpio-controller;
					reg = <0x0400 0x20>;
					ngpios = <32>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupt-parent = <&intc>;
					interrupts = <12>, <13>, <14>, <60>;
				};

				gpio1: gpio-ctrl@420 {
					compatible = "marvell,orion-gpio";
					#gpio-cells = <2>;
					gpio-controller;
					reg = <0x0420 0x20>;
					ngpios = <32>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupt-parent = <&intc>;
					interrupts = <61>;
				};

				rtc: real-time-clock@8500 {
					compatible = "marvell,orion-rtc";
					reg = <0x8500 0x20>;
					interrupts = <5>;
				};
			};

			gconf: global-config@e802c {
				compatible = "marvell,dove-global-config",
				             "syscon";
				reg = <0xe802c 0x14>;
			};

			gpio2: gpio-ctrl@e8400 {
				compatible = "marvell,orion-gpio";
				#gpio-cells = <2>;
				gpio-controller;
				reg = <0xe8400 0x0c>;
				ngpios = <8>;
			};

			lcd1: lcd-controller@810000 {
				compatible = "marvell,dove-lcd";
				reg = <0x810000 0x1000>;
				interrupts = <46>;
				status = "disabled";
			};

			lcd0: lcd-controller@820000 {
				compatible = "marvell,dove-lcd";
				reg = <0x820000 0x1000>;
				interrupts = <47>;
				status = "disabled";
			};

			crypto_sram: sram@ffffe000 {
				compatible = "mmio-sram";
				reg = <0xffffe000 0x800>;
				clocks = <&gate_clk 15>;
				#address-cells = <1>;
				#size-cells = <1>;
			};

			gpu: gpu@840000 {
				clocks = <&divider_clk 1>;
				clock-names = "core";
				compatible = "vivante,gc";
				interrupts = <48>;
				power-domains = <&gpu_domain>;
				reg = <0x840000 0x4000>;
				status = "disabled";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only

#include "dm814x-clocks.dtsi"

/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
&adpll_hdvic_ck {
	status = "disabled";
};

&adpll_l3_ck {
	status = "disabled";
};

&adpll_dss_ck {
	status = "disabled";
};

/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
&sysclk4_ck {
	clocks = <&adpll_isp_ck 1>;
};

&sysclk5_ck {
	clocks = <&adpll_isp_ck 1>;
};

&sysclk6_ck {
	clocks = <&adpll_isp_ck 1>;
};

/*
 * Compared to dm814x, dra62x has different shifts and more mux options.
 * Please add the extra options for ysclk_14 and 16 if really needed.
 */
&timer1_fck {
	clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
		  &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
	ti,bit-shift = <4>;
};

&timer2_fck {
	clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
		  &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
	ti,bit-shift = <8>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;

#include "dra62x.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "DRA62x J5 Eco EVM";
	compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;	/* 1 GB */
	};

	/* MIC94060YC6 controlled by SD1_POW pin */
	vmmcsd_fixed: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "vmmcsd_fixed";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&cpsw_emac0 {
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-id";
};

&cpsw_emac1 {
	phy-handle = <&ethphy1>;
	phy-mode = "rgmii-id";
};

&davinci_mdio {
	ethphy0: ethernet-phy@0 {
		reg = <0>;
	};

	ethphy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&gpmc {
	ranges = <0 0 0x04000000 0x01000000>;	/* CS0: 16MB for NAND */

	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>; /* termcount */
		linux,mtd-name = "micron,mt29f2g16aadwp";
		#address-cells = <1>;
		#size-cells = <1>;
		ti,nand-ecc-opt = "bch8";
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <44>;
		gpmc,cs-wr-off-ns = <44>;
		gpmc,adv-on-ns = <6>;
		gpmc,adv-rd-off-ns = <34>;
		gpmc,adv-wr-off-ns = <44>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <40>;
		gpmc,oe-on-ns = <0>;
		gpmc,oe-off-ns = <54>;
		gpmc,access-ns = <64>;
		gpmc,rd-cycle-ns = <82>;
		gpmc,wr-cycle-ns = <82>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-access-ns = <40>;
		gpmc,wr-data-mux-bus-ns = <0>;
		partition@0 {
			label = "X-Loader";
			reg = <0 0x80000>;
		};
		partition@80000 {
			label = "U-Boot";
			reg = <0x80000 0x1c0000>;
		};
		partition@1c0000 {
			label = "Environment";
			reg = <0x240000 0x40000>;
		};
		partition@280000 {
			label = "Kernel";
			reg = <0x280000 0x500000>;
		};
		partition@780000 {
			label = "Filesystem";
			reg = <0x780000 0xf880000>;
		};
	};
};

&mmc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd1_pins>;
	vmmc-supply = <&vmmcsd_fixed>;
	bus-width = <4>;
	cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
};

&pincntl {
	sd1_pins: pinmux_sd1_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x0800, PIN_INPUT | 0x1)	/* SD1_CLK */
			DM814X_IOPAD(0x0804, PIN_INPUT_PULLUP |  0x1)	/* SD1_CMD */
			DM814X_IOPAD(0x0808, PIN_INPUT_PULLUP |  0x1)	/* SD1_DAT[0] */
			DM814X_IOPAD(0x080c, PIN_INPUT_PULLUP |  0x1)	/* SD1_DAT[1] */
			DM814X_IOPAD(0x0810, PIN_INPUT_PULLUP |  0x1)	/* SD1_DAT[2] */
			DM814X_IOPAD(0x0814, PIN_INPUT_PULLUP |  0x1)	/* SD1_DAT[3] */
			DM814X_IOPAD(0x0924, PIN_OUTPUT |  0x40)	/* SD1_POW */
			DM814X_IOPAD(0x093C, PIN_INPUT_PULLUP |  0x80)	/* GP1[6] */
			>;
	};

	usb0_pins: pinmux_usb0_pins {
		pinctrl-single,pins = <
			DM814X_IOPAD(0x0c34, PIN_OUTPUT | 0x1)	/* USB0_DRVVBUS */
			>;
	};
};

/* USB0_ID pin state: SW10[1] = 0 cable detection, SW10[1] = 1 ID grounded */
&usb0 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb0_pins>;
	dr_mode = "otg";
};

&usb1_phy {
	status = "disabled";
};

&usb1 {
	status = "disabled";
};


code:
// SPDX-License-Identifier: GPL-2.0-only

#include "dm814x.dtsi"

/ {
	compatible = "ti,dra62x";
};

/* Compared to dm814x, dra62x has different offsets for Ethernet */
&mac {
	reg = <0 0x800>,
	      <0x1200 0x100>;
};

&davinci_mdio {
	reg = <0x1000 0x100>;
};

#include "dra62x-clocks.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for DRA7x SoC DSPEVE thermal
 *
 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/thermal/thermal.h>

dspeve_thermal: dspeve_thermal {
	polling-delay-passive = <250>; /* milliseconds */
	polling-delay = <500>; /* milliseconds */

			/* sensor       ID */
	thermal-sensors = <&bandgap     3>;

	trips {
		dspeve_crit: dspeve_crit {
			temperature = <125000>; /* milliCelsius */
			hysteresis = <2000>; /* milliCelsius */
			type = "critical";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "dra74-ipu-dsp-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/ti-dra7-atl.h>
#include <dt-bindings/input/input.h>

/ {
	chosen {
		stdout-path = &uart1;
	};

	extcon_usb1: extcon_usb1 {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
	};

	extcon_usb2: extcon_usb2 {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
	};

	sound0: sound0 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-EVM";
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Line", "Line Out",
			"Microphone", "Mic Jack",
			"Line", "Line In";
		simple-audio-card,routing =
			"Headphone Jack",	"HPLOUT",
			"Headphone Jack",	"HPROUT",
			"Line Out",		"LLOUT",
			"Line Out",		"RLOUT",
			"MIC3L",		"Mic Jack",
			"MIC3R",		"Mic Jack",
			"Mic Jack",		"Mic Bias",
			"LINE1L",		"Line In",
			"LINE1R",		"Line In";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&sound0_master>;
		simple-audio-card,frame-master = <&sound0_master>;
		simple-audio-card,bitclock-inversion;

		sound0_master: simple-audio-card,cpu {
			sound-dai = <&mcasp3>;
			system-clock-frequency = <5644800>;
		};

		simple-audio-card,codec {
			sound-dai = <&tlv320aic3106>;
			clocks = <&atl_clkin2_ck>;
		};
	};

	leds {
		compatible = "gpio-leds";
		led0 {
			label = "dra7:usr1";
			gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led1 {
			label = "dra7:usr2";
			gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led2 {
			label = "dra7:usr3";
			gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led3 {
			label = "dra7:usr4";
			gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};

	gpio_keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		#size-cells = <0>;
		autorepeat;

		USER1 {
			label = "btnUser1";
			linux,code = <BTN_0>;
			gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
		};

		USER2 {
			label = "btnUser2";
			linux,code = <BTN_1>;
			gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
		};
	};
};

&i2c3 {
	status = "okay";
	clock-frequency = <400000>;
};

&mcspi1 {
	status = "okay";
};

&mcspi2 {
	status = "okay";
};

&uart1 {
	status = "okay";
	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
			      <&dra7_pmx_core 0x3e0>;
};

&uart2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&qspi {
	status = "okay";

	spi-max-frequency = <76800000>;
	flash@0 {
		compatible = "s25fl256s1";
		spi-max-frequency = <76800000>;
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */
		partition@0 {
			label = "QSPI.SPL";
			reg = <0x00000000 0x00010000>;
		};
		partition@1 {
			label = "QSPI.SPL.backup1";
			reg = <0x00010000 0x00010000>;
		};
		partition@2 {
			label = "QSPI.SPL.backup2";
			reg = <0x00020000 0x00010000>;
		};
		partition@3 {
			label = "QSPI.SPL.backup3";
			reg = <0x00030000 0x00010000>;
		};
		partition@4 {
			label = "QSPI.u-boot";
			reg = <0x00040000 0x00100000>;
		};
		partition@5 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x00140000 0x00080000>;
		};
		partition@6 {
			label = "QSPI.u-boot-env";
			reg = <0x001c0000 0x00010000>;
		};
		partition@7 {
			label = "QSPI.u-boot-env.backup1";
			reg = <0x001d0000 0x0010000>;
		};
		partition@8 {
			label = "QSPI.kernel";
			reg = <0x001e0000 0x0800000>;
		};
		partition@9 {
			label = "QSPI.file-system";
			reg = <0x009e0000 0x01620000>;
		};
	};
};

&omap_dwc3_1 {
	extcon = <&extcon_usb1>;
};

&usb1 {
	dr_mode = "otg";
	extcon = <&extcon_usb1>;
};

&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
};

&usb2 {
	dr_mode = "host";
	extcon = <&extcon_usb2>;
};

&atl {
	assigned-clocks = <&abe_dpll_sys_clk_mux>,
			  <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>,
			  <&dpll_abe_ck>,
			  <&dpll_abe_m2x2_ck>,
			  <&atl_clkin2_ck>;
	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;

	status = "okay";

	atl2 {
		bws = <DRA7_ATL_WS_MCASP2_FSX>;
		aws = <DRA7_ATL_WS_MCASP3_FSX>;
	};
};

&mcasp3 {
	#sound-dai-cells = <0>;

	assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
	assigned-clock-parents = <&atl_clkin2_ck>;

	status = "okay";

	op-mode = <0>;          /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializer */
	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&pcie1_rc {
	status = "okay";
};

&mmc4 {
	bus-width = <4>;
	cap-power-off-card;
	keep-power-in-suspend;
	non-removable;
	#address-cells = <1>;
	#size-cells = <0>;
	wifi@2 {
		compatible = "ti,wl1835";
		reg = <2>;
		interrupt-parent = <&gpio5>;
		interrupts = <7 IRQ_TYPE_EDGE_RISING>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 */
/dts-v1/;

#include "dra74x.dtsi"
#include "dra7-evm-common.dtsi"
#include "dra74x-mmc-iodelay.dtsi"

/ {
	model = "TI DRA742";
	compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
	};

	evm_12v0: fixedregulator-evm_12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_1v8_sw: fixedregulator-evm_1v8 {
		compatible = "regulator-fixed";
		regulator-name = "evm_1v8";
		vin-supply = <&smps9_reg>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ipu2_memory_region: ipu2-memory@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x3800000>;
			reusable;
			status = "okay";
		};

		dsp1_memory_region: dsp1-memory@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_memory_region: ipu1-memory@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};

		dsp2_memory_region: dsp2-memory@9f000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9f000000 0x0 0x800000>;
			reusable;
			status = "okay";
		};
	};

	evm_3v3_sd: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
		gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
	};

	evm_3v3_sw: fixedregulator-evm_3v3_sw {
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3_sw";
		vin-supply = <&sysen1>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
		/* TPS77018DBVT */
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd";
		vin-supply = <&evm_3v3_sw>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output of Cntlr A of TPS43351-Q1 on dra7-evm */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_5v0: fixedregulator-evm_5v0 {
		/* Output of Cntlr B of TPS43351-Q1 on dra7-evm */
		compatible = "regulator-fixed";
		regulator-name = "evm_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_3v6: fixedregulator-evm_3v6 {
		compatible = "regulator-fixed";
		regulator-name = "evm_3v6";
		regulator-min-microvolt = <3600000>;
		regulator-max-microvolt = <3600000>;
		vin-supply = <&evm_5v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vmmcwl_fixed: fixedregulator-mmcwl {
		compatible = "regulator-fixed";
		regulator-name = "vmmcwl_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&gpio5 8 0>;
		startup-delay-us = <70000>;
		enable-active-high;
	};

	vtt_fixed: fixedregulator-vtt {
		compatible = "regulator-fixed";
		regulator-name = "vtt_fixed";
		regulator-min-microvolt = <1350000>;
		regulator-max-microvolt = <1350000>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&sysen2>;
		gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
	};

};

&dra7_pmx_core {
	dcan1_pins_default: dcan1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
			DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
		>;
	};

	dcan1_pins_sleep: dcan1_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
			DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP)	/* wakeup0.off */
		>;
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	tps659038: tps659038@58 {
		compatible = "ti,tps659038";
		reg = <0x58>;
		ti,palmas-override-powerhold;
		ti,system-power-controller;

		tps659038_pmic {
			compatible = "ti,tps659038-pmic";

			regulators {
				smps123_reg: smps123 {
					/* VDD_MPU */
					regulator-name = "smps123";
					regulator-min-microvolt = < 850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps45_reg: smps45 {
					/* VDD_DSPEVE */
					regulator-name = "smps45";
					regulator-min-microvolt = < 850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps6_reg: smps6 {
					/* VDD_GPU - over VDD_SMPS6 */
					regulator-name = "smps6";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps7_reg: smps7 {
					/* CORE_VDD */
					regulator-name = "smps7";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1150000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps8_reg: smps8 {
					/* VDD_IVAHD */
					regulator-name = "smps8";
					regulator-min-microvolt = < 850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps9_reg: smps9 {
					/* VDDS1V8 */
					regulator-name = "smps9";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo1_reg: ldo1 {
					/* LDO1_OUT --> SDIO  */
					regulator-name = "ldo1";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo2_reg: ldo2 {
					/* VDD_RTCIO */
					/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
					regulator-name = "ldo2";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo3_reg: ldo3 {
					/* VDDA_1V8_PHY */
					regulator-name = "ldo3";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo9_reg: ldo9 {
					/* VDD_RTC */
					regulator-name = "ldo9";
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
					regulator-always-on;
					regulator-boot-on;
					regulator-allow-bypass;
				};

				ldoln_reg: ldoln {
					/* VDDA_1V8_PLL */
					regulator-name = "ldoln";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldousb_reg: ldousb {
					/* VDDA_3V_USB: VDDA_USBHS33 */
					regulator-name = "ldousb";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
				};

				/* REGEN1 is unused */

				regen2: regen2 {
					/* Needed for PMIC internal resources */
					regulator-name = "regen2";
					regulator-boot-on;
					regulator-always-on;
				};

				/* REGEN3 is unused */

				sysen1: sysen1 {
					/* PMIC_REGEN_3V3 */
					regulator-name = "sysen1";
					regulator-boot-on;
					regulator-always-on;
				};

				sysen2: sysen2 {
					/* PMIC_REGEN_DDR */
					regulator-name = "sysen2";
					regulator-boot-on;
					regulator-always-on;
				};
			};
		};
	};

	pcf_lcd: gpio@20 {
		compatible = "nxp,pcf8575";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio6>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	pcf_gpio_21: gpio@21 {
		compatible = "nxp,pcf8575";
		reg = <0x21>;
		lines-initial-states = <0x1408>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio6>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	tlv320aic3106: tlv320aic3106@19 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x19>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;		/* 2.0V */
		status = "okay";

		/* Regulators */
		AVDD-supply = <&evm_3v3_sw>;
		IOVDD-supply = <&evm_3v3_sw>;
		DRVDD-supply = <&evm_3v3_sw>;
		DVDD-supply = <&aic_dvdd>;
	};
};

&i2c2 {
	status = "okay";
	clock-frequency = <400000>;

	pcf_hdmi: gpio@26 {
		compatible = "nxp,pcf8575";
		reg = <0x26>;
		gpio-controller;
		#gpio-cells = <2>;
		hdmi-audio-hog {
			/* vin6_sel_s0: high: VIN6, low: audio */
			gpio-hog;
			gpios = <1 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "vin6_sel_s0";
		};
	};
};

&mmc1 {
	status = "okay";
	vmmc-supply = <&evm_3v3_sd>;
	vqmmc-supply = <&ldo1_reg>;
	bus-width = <4>;
	/*
	 * SDCD signal is not being used here - using the fact that GPIO mode
	 * is always hardwired.
	 */
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	pinctrl-2 = <&mmc1_pins_sdr12>;
	pinctrl-3 = <&mmc1_pins_sdr25>;
	pinctrl-4 = <&mmc1_pins_sdr50>;
	pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
	pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
	pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};

&mmc2 {
	status = "okay";
	vmmc-supply = <&evm_1v8_sw>;
	vqmmc-supply = <&evm_1v8_sw>;
	bus-width = <8>;
	non-removable;
	pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>;
	pinctrl-3 = <&mmc2_pins_ddr_rev20>;
	pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>;
	pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
};

&mmc4 {
	status = "okay";
	vmmc-supply = <&evm_3v6>;
	vqmmc-supply = <&vmmcwl_fixed>;
	pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
	pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
	pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>;
	pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
	pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
	pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
	pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
};

&cpu0 {
	vdd-supply = <&smps123_reg>;
};

&elm {
	status = "okay";
};

&gpmc {
	/*
	* For the existing IOdelay configuration via U-Boot we don't
	* support NAND on dra7-evm. Keep it disabled. Enabling it
	* requires a different configuration by U-Boot.
	*/
	status = "disabled";
	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;		/* device IO registers */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>; /* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
		ti,nand-xfer-type = "prefetch-dma";
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <80>;
		gpmc,cs-wr-off-ns = <80>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <60>;
		gpmc,adv-wr-off-ns = <60>;
		gpmc,we-on-ns = <10>;
		gpmc,we-off-ns = <50>;
		gpmc,oe-on-ns = <4>;
		gpmc,oe-off-ns = <40>;
		gpmc,access-ns = <40>;
		gpmc,wr-access-ns = <80>;
		gpmc,rd-cycle-ns = <80>;
		gpmc,wr-cycle-ns = <80>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x00020000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00020000 0x00020000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00040000 0x00020000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x00060000 0x00020000>;
		};
		partition@4 {
			label = "NAND.u-boot-spl-os";
			reg = <0x00080000 0x00040000>;
		};
		partition@5 {
			label = "NAND.u-boot";
			reg = <0x000c0000 0x00100000>;
		};
		partition@6 {
			label = "NAND.u-boot-env";
			reg = <0x001c0000 0x00020000>;
		};
		partition@7 {
			label = "NAND.u-boot-env.backup1";
			reg = <0x001e0000 0x00020000>;
		};
		partition@8 {
			label = "NAND.kernel";
			reg = <0x00200000 0x00800000>;
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00a00000 0x0f600000>;
		};
	};
};

&usb2_phy1 {
	phy-supply = <&ldousb_reg>;
};

&usb2_phy2 {
	phy-supply = <&ldousb_reg>;
};

&gpio7_target {
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&mac_sw {
	status = "okay";
};

&cpsw_port1 {
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii";
	ti,dual-emac-pvid = <1>;
};

&cpsw_port2 {
	phy-handle = <&ethphy1>;
	phy-mode = "rgmii";
	ti,dual-emac-pvid = <2>;
};

&davinci_mdio_sw {
	ethphy0: ethernet-phy@2 {
		reg = <2>;
	};

	ethphy1: ethernet-phy@3 {
		reg = <3>;
	};
};

&dcan1 {
	status = "okay";
	pinctrl-names = "default", "sleep", "active";
	pinctrl-0 = <&dcan1_pins_sleep>;
	pinctrl-1 = <&dcan1_pins_sleep>;
	pinctrl-2 = <&dcan1_pins_default>;
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_memory_region>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_memory_region>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_memory_region>;
};

&dsp2 {
	status = "okay";
	memory-region = <&dsp2_memory_region>;
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Common IPU and DSP data for TI DRA7xx/AM57xx platforms
 */

&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
		status = "okay";
	};
	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
		status = "okay";
	};
};

&mailbox6 {
	status = "okay";
	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
		status = "okay";
	};
};

&ipu2 {
	mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
	ti,timers = <&timer3>;
	ti,watchdog-timers = <&timer4>, <&timer9>;
};

&ipu1 {
	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
	ti,timers = <&timer11>;
	ti,watchdog-timers = <&timer7>, <&timer8>;
};

&dsp1 {
	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
	ti,timers = <&timer5>;
	ti,watchdog-timers = <&timer10>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for DRA7x SoC IVA thermal
 *
 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/thermal/thermal.h>

iva_thermal: iva_thermal {
	polling-delay-passive = <250>; /* milliseconds */
	polling-delay = <500>; /* milliseconds */

			/* sensor       ID */
	thermal-sensors = <&bandgap     4>;

	trips {
		iva_crit: iva_crit {
			temperature = <125000>; /* milliCelsius */
			hysteresis = <2000>; /* milliCelsius */
			type = "critical";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * MMC IOdelay values for TI's DRA7xx SoCs.
 * Copyright (C) 2018 Texas Instruments
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 */

&dra7_pmx_core {
	mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
		>;
	};
};