code:
HiSilicon SPI-NOR Flash Controller

Required properties:
- compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings:
		"hisilicon,hi3519-spi-nor"
- address-cells : Should be 1.
- size-cells : Should be 0.
- reg : Offset and length of the register set for the controller device.
- reg-names : Must include the following two entries: "control", "memory".
- clocks : handle to spi-nor flash controller clock.

Example:
spi-nor-controller@10000000 {
	compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
	reg-names = "control", "memory";
	clocks = <&clock HI3519_FMC_CLK>;
	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
	};
};


code:
AMCC NDFC (NanD Flash Controller)

Required properties:
- compatible : "ibm,ndfc".
- reg : should specify chip select and size used for the chip (0x2000).

Optional properties:
- ccr : NDFC config and control register value (default 0).
- bank-settings : NDFC bank configuration register value (default 0).

Notes:
- partition(s) - follows the OF MTD standard for partitions

Example:

ndfc@1,0 {
	compatible = "ibm,ndfc";
	reg = <0x00000001 0x00000000 0x00002000>;
	ccr = <0x00001000>;
	bank-settings = <0x80002222>;
	#address-cells = <1>;
	#size-cells = <1>;

	nand {
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "kernel";
			reg = <0x00000000 0x00200000>;
		};
		partition@200000 {
			label = "root";
			reg = <0x00200000 0x03E00000>;
		};
	};
};

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs NAND controller devicetree bindings

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

allOf:
  - $ref: nand-controller.yaml#
  - $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#

properties:
  compatible:
    enum:
      - ingenic,jz4740-nand
      - ingenic,jz4725b-nand
      - ingenic,jz4780-nand

  reg:
    items:
      - description: Bank number, offset and size of first attached NAND chip
      - description: Bank number, offset and size of second attached NAND chip
      - description: Bank number, offset and size of third attached NAND chip
      - description: Bank number, offset and size of fourth attached NAND chip
    minItems: 1

  ecc-engine: true

  partitions:
    type: object
    deprecated: true
    description:
      Node containing description of fixed partitions.

patternProperties:
  "^nand@[a-f0-9]$":
    type: object
    properties:
      rb-gpios:
        description: GPIO specifier for the busy pin.
        maxItems: 1

      wp-gpios:
        description: GPIO specifier for the write-protect pin.
        maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
    memory-controller@13410000 {
        compatible = "ingenic,jz4780-nemc";
        reg = <0x13410000 0x10000>;
        #address-cells = <2>;
        #size-cells = <1>;
        ranges = <1 0 0x1b000000 0x1000000>,
                 <2 0 0x1a000000 0x1000000>,
                 <3 0 0x19000000 0x1000000>,
                 <4 0 0x18000000 0x1000000>,
                 <5 0 0x17000000 0x1000000>,
                 <6 0 0x16000000 0x1000000>;

        clocks = <&cgu JZ4780_CLK_NEMC>;

        nand-controller@1 {
            compatible = "ingenic,jz4780-nand";
            reg = <1 0 0x1000000>;

            #address-cells = <1>;
            #size-cells = <0>;

            ecc-engine = <&bch>;

            ingenic,nemc-tAS = <10>;
            ingenic,nemc-tAH = <5>;
            ingenic,nemc-tBP = <10>;
            ingenic,nemc-tAW = <15>;
            ingenic,nemc-tSTRV = <100>;

            pinctrl-names = "default";
            pinctrl-0 = <&pins_nemc>;

            nand@1 {
                reg = <1>;

                nand-ecc-step-size = <1024>;
                nand-ecc-strength = <24>;
                nand-ecc-mode = "hw";
                nand-on-flash-bbt;

                pinctrl-names = "default";
                pinctrl-0 = <&pins_nemc_cs1>;

                partitions {
                    compatible = "fixed-partitions";
                    #address-cells = <2>;
                    #size-cells = <2>;

                    partition@0 {
                        label = "u-boot-spl";
                        reg = <0x0 0x0 0x0 0x800000>;
                    };

                    partition@800000 {
                        label = "u-boot";
                        reg = <0x0 0x800000 0x0 0x200000>;
                    };

                    partition@a00000 {
                        label = "u-boot-env";
                        reg = <0x0 0xa00000 0x0 0x200000>;
                    };

                    partition@c00000 {
                        label = "boot";
                        reg = <0x0 0xc00000 0x0 0x4000000>;
                    };

                    partition@4c00000 {
                        label = "system";
                        reg = <0x0 0x4c00000 0x1 0xfb400000>;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/intel,lgm-ebunand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel LGM SoC NAND Controller

allOf:
  - $ref: "nand-controller.yaml"

maintainers:
  - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>

properties:
  compatible:
    const: intel,lgm-ebunand

  reg:
    maxItems: 6

  reg-names:
    items:
      - const: ebunand
      - const: hsnand
      - const: nand_cs0
      - const: nand_cs1
      - const: addr_sel0
      - const: addr_sel1

  clocks:
    maxItems: 1

  dmas:
    maxItems: 2

  dma-names:
    items:
      - const: tx
      - const: rx

patternProperties:
  "^nand@[a-f0-9]$":
    type: object
    properties:
      reg:
        minimum: 0
        maximum: 1

      nand-ecc-mode: true

      nand-ecc-algo:
        const: hw

    additionalProperties: false

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - dmas
  - dma-names

unevaluatedProperties: false

examples:
  - |
    nand-controller@e0f00000 {
        compatible = "intel,lgm-ebunand";
        reg = <0xe0f00000 0x100>,
              <0xe1000000 0x300>,
              <0xe1400000 0x8000>,
              <0xe1c00000 0x1000>,
              <0x17400000 0x4>,
              <0x17c00000 0x4>;
        reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1",
                    "addr_sel0", "addr_sel1";
        clocks = <&cgu0 125>;
        dmas = <&dma0 8>, <&dma0 9>;
        dma-names = "tx", "rx";
        #address-cells = <1>;
        #size-cells = <0>;

        nand@0 {
            reg = <0>;
            nand-ecc-mode = "hw";
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SPI NOR flash ST M25Pxx (and similar) serial flash chips

maintainers:
  - Rob Herring <robh@kernel.org>

allOf:
  - $ref: "mtd.yaml#"
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - pattern: "^((((micron|spansion|st),)?\
              (m25p(40|80|16|32|64|128)|\
              n25q(32b|064|128a11|128a13|256a|512a|164k)))|\
              atmel,at25df(321a|641|081a)|\
              everspin,mr25h(10|40|128|256)|\
              (mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|\
              (mxicy|macronix),mx25u(4033|4035)|\
              (spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|\
              (sst|microchip),sst25vf(016b|032b|040b)|\
              (sst,)?sst26wf016b|\
              (sst,)?sst25wf(040b|080)|\
              winbond,w25x(80|32)|\
              (winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$"
          - const: jedec,spi-nor
      - items:
          - enum:
              - issi,is25lp016d
              - micron,mt25qu02g
              - mxicy,mx25r1635f
              - mxicy,mx25u6435f
              - mxicy,mx25v8035f
              - spansion,s25sl12801
              - spansion,s25fs512s
          - const: jedec,spi-nor
      - const: jedec,spi-nor
    description:
      Must also include "jedec,spi-nor" for any SPI NOR flash that can be
      identified by the JEDEC READ ID opcode (0x9F).

  reg:
    minItems: 1
    maxItems: 2

  m25p,fast-read:
    type: boolean
    description:
      Use the "fast read" opcode to read data from the chip instead of the usual
      "read" opcode. This opcode is not supported by all chips and support for
      it can not be detected at runtime. Refer to your chips' datasheet to check
      if this is supported by your chip.

  broken-flash-reset:
    type: boolean
    description:
      Some flash devices utilize stateful addressing modes (e.g., for 32-bit
      addressing) which need to be managed carefully by a system. Because these
      sorts of flash don't have a standardized software reset command, and
      because some systems don't toggle the flash RESET# pin upon system reset
      (if the pin even exists at all), there are systems which cannot reboot
      properly if the flash is left in the "wrong" state. This boolean flag can
      be used on such systems, to denote the absence of a reliable reset
      mechanism.

  reset-gpios:
    description:
      A GPIO line connected to the RESET (active low) signal of the device.
      If "broken-flash-reset" is present then having this property does not
      make any difference.

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        flash@0 {
            compatible = "spansion,m25p80", "jedec,spi-nor";
            reg = <0>;
            spi-max-frequency = <40000000>;
            m25p,fast-read;
            reset-gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
        };
    };
...


code:
NXP LPC32xx SoC NAND MLC controller

Required properties:
- compatible: "nxp,lpc3220-mlc"
- reg: Address and size of the controller
- interrupts: The NAND interrupt specification
- gpios: GPIO specification for NAND write protect

The following required properties are very controller specific. See the LPC32xx
User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
Hz, to make them independent of actual clock speed and to provide for good
accuracy:)
- nxp,tcea_delay: TCEA_DELAY
- nxp,busy_delay: BUSY_DELAY
- nxp,nand_ta: NAND_TA
- nxp,rd_high: RD_HIGH
- nxp,rd_low: RD_LOW
- nxp,wr_high: WR_HIGH
- nxp,wr_low: WR_LOW

Optional subnodes:
- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml

Example:

	mlc: flash@200a8000 {
		compatible = "nxp,lpc3220-mlc";
		reg = <0x200A8000 0x11000>;
		interrupts = <11 0>;
		#address-cells = <1>;
		#size-cells = <1>;

		nxp,tcea-delay = <333333333>;
		nxp,busy-delay = <10000000>;
		nxp,nand-ta = <18181818>;
		nxp,rd-high = <31250000>;
		nxp,rd-low = <45454545>;
		nxp,wr-high = <40000000>;
		nxp,wr-low = <83333333>;
		gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */

		mtd0@00000000 {
			label = "boot";
			reg = <0x00000000 0x00064000>;
			read-only;
		};

		...

	};


code:
NXP LPC32xx SoC NAND SLC controller

Required properties:
- compatible: "nxp,lpc3220-slc"
- reg: Address and size of the controller
- nand-on-flash-bbt: Use bad block table on flash
- gpios: GPIO specification for NAND write protect

The following required properties are very controller specific. See the LPC32xx
User Manual:
- nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
- nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
(The following values are specified in Hz, to make them independent of actual
clock speed:)
- nxp,wwidth: Write pulse width (W_WIDTH)
- nxp,whold: Write hold time (W_HOLD)
- nxp,wsetup: Write setup time (W_SETUP)
- nxp,rwidth: Read pulse width (R_WIDTH)
- nxp,rhold: Read hold time (R_HOLD)
- nxp,rsetup: Read setup time (R_SETUP)

Optional subnodes:
- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml

Example:

	slc: flash@20020000 {
		compatible = "nxp,lpc3220-slc";
		reg = <0x20020000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		nxp,wdr-clks = <14>;
		nxp,wwidth = <40000000>;
		nxp,whold = <100000000>;
		nxp,wsetup = <100000000>;
		nxp,rdr-clks = <14>;
		nxp,rwidth = <40000000>;
		nxp,rhold = <66666666>;
		nxp,rsetup = <100000000>;
		nand-on-flash-bbt;
		gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */

		mtd0@00000000 {
			label = "phy3250-boot";
			reg = <0x00000000 0x00064000>;
			read-only;
		};

		...

	};


code:
Marvell NAND Flash Controller (NFC)

Required properties:
- compatible: can be one of the following:
    * "marvell,armada-8k-nand-controller"
    * "marvell,armada370-nand-controller"
    * "marvell,pxa3xx-nand-controller"
    * "marvell,armada-8k-nand" (deprecated)
    * "marvell,armada370-nand" (deprecated)
    * "marvell,pxa3xx-nand" (deprecated)
  Compatibles marked deprecated support only the old bindings described
  at the bottom.
- reg: NAND flash controller memory area.
- #address-cells: shall be set to 1. Encode the NAND CS.
- #size-cells: shall be set to 0.
- interrupts: shall define the NAND controller interrupt.
- clocks: shall reference the NAND controller clocks, the second one is
  is only needed for the Armada 7K/8K SoCs
- clock-names: mandatory if there is a second clock, in this case there
  should be one clock named "core" and another one named "reg"
- marvell,system-controller: Set to retrieve the syscon node that handles
  NAND controller related registers (only required with the
  "marvell,armada-8k-nand[-controller]" compatibles).

Optional properties:
- label: see partition.txt. New platforms shall omit this property.
- dmas: shall reference DMA channel associated to the NAND controller.
  This property is only used with "marvell,pxa3xx-nand[-controller]"
  compatible strings.
- dma-names: shall be "rxtx".
  This property is only used with "marvell,pxa3xx-nand[-controller]"
  compatible strings.

Optional children nodes:
Children nodes represent the available NAND chips.

Required properties:
- reg: shall contain the native Chip Select ids (0-3).
- nand-rb: see nand-controller.yaml (0-1).

Optional properties:
- marvell,nand-keep-config: orders the driver not to take the timings
  from the core and leaving them completely untouched. Bootloader
  timings will then be used.
- label: MTD name.
- nand-on-flash-bbt: see nand-controller.yaml.
- nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
- nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
  not using hardware ECC. Howerver, it may be added when using hardware
  ECC for clarification but will be ignored by the driver because ECC
  mode is chosen depending on the page size and the strength required by
  the NAND chip. This value may be overwritten with nand-ecc-strength
  property.
- nand-ecc-strength: see nand-controller.yaml.
- nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
  use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
  step size will shrink or grow in order to fit the required strength.
  Step sizes are not completely random for all and follow certain
  patterns described in AN-379, "Marvell SoC NFC ECC".

See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
generic bindings.

Example:
nand_controller: nand-controller@d0000 {
	compatible = "marvell,armada370-nand-controller";
	reg = <0xd0000 0x54>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&coredivclk 0>;

	nand@0 {
		reg = <0>;
		label = "main-storage";
		nand-rb = <0>;
		nand-ecc-mode = "hw";
		marvell,nand-keep-config;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "Rootfs";
				reg = <0x00000000 0x40000000>;
			};
		};
	};
};

Note on legacy bindings: One can find, in not-updated device trees,
bindings slightly different than described above with other properties
described below as well as the partitions node at the root of a so
called "nand" node (without clear controller/chip separation).

Legacy properties:
- marvell,nand-enable-arbiter: To enable the arbiter, all boards blindly
  used it, this bit was set by the bootloader for many boards and even if
  it is marked reserved in several datasheets, it might be needed to set
  it (otherwise it is harmless) so whether or not this property is set,
  the bit is selected by the driver.
- num-cs: Number of chip-select lines to use, all boards blindly set 1
  to this and for a reason, other values would have failed. The value of
  this property is ignored.

Example:

	nand0: nand@43100000 {
		compatible = "marvell,pxa3xx-nand";
		reg = <0x43100000 90>;
		interrupts = <45>;
		dmas = <&pdma 97 0>;
		dma-names = "rxtx";
		#address-cells = <1>;
		marvell,nand-keep-config;
		marvell,nand-enable-arbiter;
		num-cs = <1>;
		/* Partitions (optional) */
       };


code:
* MTD SPI driver for Microchip 23K256 (and similar) serial SRAM

Required properties:
- #address-cells, #size-cells : Must be present if the device has sub-nodes
  representing partitions.
- compatible : Must be one of "microchip,mchp23k256" or "microchip,mchp23lcv1024"
- reg : Chip-Select number
- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at

Example:

	spi-sram@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "microchip,mchp23k256";
		reg = <0>;
		spi-max-frequency = <20000000>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mtd/microchip,mchp48l640.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Microchip 48l640 (and similar) serial EERAM bindings

maintainers:
  - Heiko Schocher <hs@denx.de>

description: |
  The Microchip 48l640 is a 8KByte EERAM connected via SPI.

  datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/20006055B.pdf

properties:
  compatible:
    items:
      - const: microchip,48l640

  reg:
    maxItems: 1

required:
  - compatible
  - reg

allOf:
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

unevaluatedProperties: false

examples:
  - |
    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        eeram@0 {
            compatible = "microchip,48l640";
            reg = <0>;
            spi-max-frequency = <20000000>;
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)

maintainers:
  - Rob Herring <robh@kernel.org>

description: |
  Flash chips (Memory Technology Devices) are often used for solid state
  file systems on embedded devices.

allOf:
  - $ref: "mtd.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - amd,s29gl01gp
              - amd,s29gl032a
              - amd,s29gl256n
              - amd,s29gl512n
              - arm,versatile-flash
              - arm,vexpress-flash
              - cortina,gemini-flash
              - cypress,hyperflash
              - ge,imp3a-firmware-mirror
              - ge,imp3a-paged-flash
              - gef,ppc9a-firmware-mirror
              - gef,ppc9a-paged-flash
              - gef,sbc310-firmware-mirror
              - gef,sbc310-paged-flash
              - gef,sbc610-firmware-mirror
              - gef,sbc610-paged-flash
              - intel,28f128j3
              - intel,dt28f160
              - intel,ixp4xx-flash
              - intel,JS28F128
              - intel,JS28F640
              - intel,PC28F640P30T85
              - numonyx,js28f00a
              - numonyx,js28f128
              - sst,sst39vf320
              - xlnx,xps-mch-emc-2.00.a
          - enum:
              - cfi-flash
              - jedec-flash
      - items:
          - enum:
              - cypress,cy7c1019dv33-10zsxi
              - arm,vexpress-psram
          - const: mtd-ram
      - enum:
          - cfi-flash
          - jedec-flash
          - mtd-ram
          - mtd-rom

  reg:
    description: |
      It's possible to (optionally) define multiple "reg" tuples so that
      non-identical chips can be described in one node.
    minItems: 1
    maxItems: 8

  bank-width:
    description: Width (in bytes) of the bank.  Equal to the device width times
      the number of interleaved chips.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 1, 2, 4 ]

  device-width:
    description:
      Width of a single mtd chip. If omitted, assumed to be equal to 'bank-width'.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 1, 2 ]

  no-unaligned-direct-access:
    type: boolean
    description: |
      Disables the default direct mapping of the flash.

      On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause problems
      with JFFS2 usage, as the local bus (LPB) doesn't support unaligned
      accesses as implemented in the JFFS2 code via memcpy(). By defining
      "no-unaligned-direct-access", the flash will not be exposed directly to
      the MTD users (e.g. JFFS2) any more.

  linux,mtd-name:
    description:
      Allows specifying the mtd name for retro capability with physmap-flash
      drivers as boot loader pass the mtd partition via the old device name
      physmap-flash.
    $ref: /schemas/types.yaml#/definitions/string

  use-advanced-sector-protection:
    type: boolean
    description: |
      Enables support for the advanced sector protection (Spansion: PPB -
      Persistent Protection Bits) locking.

  erase-size:
    description: The chip's physical erase block size in bytes.
    $ref: /schemas/types.yaml#/definitions/uint32

  addr-gpios:
    description:
      List of GPIO descriptors that will be used to address the MSBs address
      lines. The order goes from LSB to MSB.
    minItems: 1
    maxItems: 8

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  big-endian: true
  little-endian: true

required:
  - compatible
  - reg

if:
  properties:
    compatible:
      contains:
        const: cortina,gemini-flash
then:
  properties:
    syscon:
      $ref: /schemas/types.yaml#/definitions/phandle
      description:
        Phandle to the syscon controller
  required:
    - syscon

# FIXME: A parent bus may define timing properties
additionalProperties: true

examples:
  - |

    flash@ff000000 {
        compatible = "cfi-flash";
        reg = <0xff000000 0x01000000>;
        bank-width = <4>;
        device-width = <1>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0xff000000 0x01000000>;

        fs@0 {
            label = "fs";
            reg = <0 0xf80000>;
        };
        firmware@f80000 {
            label ="firmware";
            reg = <0xf80000 0x80000>;
            read-only;
        };
    };

  - |
    /* An example with multiple "reg" tuples */

    flash@0 {
        compatible = "intel,PC28F640P30T85", "cfi-flash";
        reg = <0x00000000 0x02000000>,
              <0x02000000 0x02000000>;
        bank-width = <2>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0 0x04000000>;

        partition@0 {
            label = "test-part1";
            reg = <0 0x04000000>;
        };
    };

  - |
    /* An example using SRAM */
    bus {
        #address-cells = <2>;
        #size-cells = <1>;

        sram@2,0 {
            compatible = "mtd-ram";
            reg = <2 0 0x00200000>;
            bank-width = <2>;
        };
    };

  - |
    /* An example using addr-gpios */
    #include <dt-bindings/gpio/gpio.h>

    flash@20000000 {
        compatible = "cfi-flash";
        reg = <0x20000000 0x02000000>;
        bank-width = <2>;
        addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0x00000000 0x02000000>,
                 <1 0x02000000 0x02000000>;

        partition@0 {
            label = "test-part1";
            reg = <0 0x04000000>;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/mtd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MTD (Memory Technology Device)

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>
  - Richard Weinberger <richard@nod.at>

properties:
  $nodename:
    pattern: "^(flash|.*sram)(@.*)?$"

  label:
    description:
      User-defined MTD device name. Can be used to assign user friendly
      names to MTD devices (instead of the flash model or flash controller
      based name) in order to ease flash device identification and/or
      describe what they are used for.

  '#address-cells':
    deprecated: true

  '#size-cells':
    deprecated: true

  partitions:
    $ref: /schemas/mtd/partitions/partitions.yaml

    required:
      - compatible

patternProperties:
  "@[0-9a-f]+$":
    $ref: partitions/partition.yaml
    deprecated: true

  "^partition@[0-9a-f]+":
    $ref: partitions/partition.yaml
    deprecated: true

  "^otp(-[0-9]+)?$":
    $ref: ../nvmem/nvmem.yaml#

    description: |
      An OTP memory region. Some flashes provide a one-time-programmable
      memory whose content can either be programmed by a user or is already
      pre-programmed by the factory. Some flashes might provide both.

    properties:
      compatible:
        enum:
          - user-otp
          - factory-otp

    required:
      - compatible

# This is a generic file other binding inherit from
additionalProperties: true

examples:
  - |
    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        flash@0 {
            reg = <0>;
            compatible = "jedec,spi-nor";
            label = "System-firmware";
        };
    };

  - |
    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        flash@0 {
            reg = <0>;
            compatible = "jedec,spi-nor";

            otp-1 {
                compatible = "factory-otp";
                #address-cells = <1>;
                #size-cells = <1>;

                electronic-serial-number@0 {
                    reg = <0 8>;
                };
            };

            otp-2 {
                compatible = "user-otp";
                #address-cells = <1>;
                #size-cells = <1>;

                mac-address@0 {
                    reg = <0 6>;
                };
            };
        };
    };

...


code:
MTK SoCs NAND FLASH controller (NFC) DT binding

This file documents the device tree bindings for MTK SoCs NAND controllers.
The functional split of the controller requires two drivers to operate:
the nand controller interface driver and the ECC engine driver.

The hardware description for both devices must be captured as device
tree nodes.

1) NFC NAND Controller Interface (NFI):
=======================================

The first part of NFC is NAND Controller Interface (NFI) HW.
Required NFI properties:
- compatible:			Should be one of
				"mediatek,mt2701-nfc",
				"mediatek,mt2712-nfc",
				"mediatek,mt7622-nfc".
- reg:				Base physical address and size of NFI.
- interrupts:			Interrupts of NFI.
- clocks:			NFI required clocks.
- clock-names:			NFI clocks internal name.
- ecc-engine:			Required ECC Engine node.
- #address-cells:		NAND chip index, should be 1.
- #size-cells:			Should be 0.

Example:

	nandc: nfi@1100d000 {
		compatible = "mediatek,mt2701-nfc";
		reg = <0 0x1100d000 0 0x1000>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI>,
			 <&pericfg CLK_PERI_NFI_PAD>;
		clock-names = "nfi_clk", "pad_clk";
		ecc-engine = <&bch>;
		#address-cells = <1>;
		#size-cells = <0>;
        };

Platform related properties, should be set in {platform_name}.dts:
- children nodes:	NAND chips.

Children nodes properties:
- reg:			Chip Select Signal, default 0.
			Set as reg = <0>, <1> when need 2 CS.
Optional:
- nand-on-flash-bbt:	Store BBT on NAND Flash.
- nand-ecc-mode:	the NAND ecc mode (check driver for supported modes)
- nand-ecc-step-size:	Number of data bytes covered by a single ECC step.
			valid values:
			512 and 1024 on mt2701 and mt2712.
			512 only on mt7622.
			1024 is recommended for large page NANDs.
- nand-ecc-strength:	Number of bits to correct per ECC step.
			The valid values that each controller supports:
			mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
				32, 36, 40, 44, 48, 52, 56, 60.
			mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
				32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
			mt7622: 4, 6, 8, 10, 12, 14, 16.
			The strength should be calculated as follows:
			E = (S - F) * 8 / B
			S = O / (P / Q)
				E :	nand-ecc-strength.
				S :	spare size per sector.
				F :	FDM size, should be in the range [1,8].
					It is used to store free oob data.
				O :	oob size.
				P :	page size.
				Q :	nand-ecc-step-size.
				B :	number of parity bits needed to correct
					1 bitflip.
					According to MTK NAND controller design,
					this number depends on max ecc step size
					that MTK NAND controller supports.
					If max ecc step size supported is 1024,
					then it should be always 14. And if max
					ecc step size is 512, then it should be
					always 13.
			If the result does not match any one of the listed
			choices above, please select the smaller valid value from
			the list.
			(otherwise the driver will do the adjustment at runtime)
- pinctrl-names:	Default NAND pin GPIO setting name.
- pinctrl-0:		GPIO setting node.

Example:
	&pio {
		nand_pins_default: nanddefault {
			pins_dat {
				pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>,
					 <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>,
					 <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>,
					 <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>,
					 <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>,
					 <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>,
					 <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>,
					 <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>,
					 <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>;
				input-enable;
				drive-strength = <MTK_DRIVE_8mA>;
				bias-pull-up;
			};

			pins_we {
				pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>;
				drive-strength = <MTK_DRIVE_8mA>;
				bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
			};

			pins_ale {
				pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>;
				drive-strength = <MTK_DRIVE_8mA>;
				bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
			};
		};
	};

	&nandc {
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&nand_pins_default>;
		nand@0 {
			reg = <0>;
			nand-on-flash-bbt;
			nand-ecc-mode = "hw";
			nand-ecc-strength = <24>;
			nand-ecc-step-size = <1024>;
		};
	};

NAND chip optional subnodes:
- Partitions, see Documentation/devicetree/bindings/mtd/mtd.yaml

Example:
	nand@0 {
		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			preloader@0 {
				label = "pl";
				read-only;
				reg = <0x00000000 0x00400000>;
			};
			android@00400000 {
				label = "android";
				reg = <0x00400000 0x12c00000>;
			};
		};
	};

2) ECC Engine:
==============

Required BCH properties:
- compatible:	Should be one of
		"mediatek,mt2701-ecc",
		"mediatek,mt2712-ecc",
		"mediatek,mt7622-ecc".
- reg:		Base physical address and size of ECC.
- interrupts:	Interrupts of ECC.
- clocks:	ECC required clocks.
- clock-names:	ECC clocks internal name.

Example:

	bch: ecc@1100e000 {
		compatible = "mediatek,mt2701-ecc";
		reg = <0 0x1100e000 0 0x1000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI_ECC>;
		clock-names = "nfiecc_clk";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/mxc-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale's mxc_nand binding

maintainers:
  - Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

allOf:
  - $ref: "nand-controller.yaml"

properties:
  compatible:
    const: fsl,imx27-nand

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    nand-controller@d8000000 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "fsl,imx27-nand";
        reg = <0xd8000000 0x1000>;
        interrupts = <29>;
    };


code:
Macronix Raw NAND Controller Device Tree Bindings
-------------------------------------------------

Required properties:
- compatible: should be "mxic,multi-itfc-v009-nand-controller"
- reg: should contain 1 entry for the registers
- #address-cells: should be set to 1
- #size-cells: should be set to 0
- interrupts: interrupt line connected to this raw NAND controller
- clock-names: should contain "ps", "send" and "send_dly"
- clocks: should contain 3 phandles for the "ps", "send" and
	 "send_dly" clocks

Children nodes:
- children nodes represent the available NAND chips.

See Documentation/devicetree/bindings/mtd/nand-controller.yaml
for more details on generic bindings.

Example:

	nand: nand-controller@43c30000 {
		compatible = "mxic,multi-itfc-v009-nand-controller";
		reg = <0x43c30000 0x10000>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>;
		clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
		clock-names = "send", "send_dly", "ps";

		nand@0 {
			reg = <0>;
			nand-ecc-mode = "soft";
			nand-ecc-algo = "bch";
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Macronix NAND ECC engine

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

properties:
  compatible:
    const: mxicy,nand-ecc-engine-rev3

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    /* External configuration */
    spi_controller0: spi@43c30000 {
        compatible = "mxicy,mx25f0a-spi";
        reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
        reg-names = "regs", "dirmap";
        clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
        clock-names = "send_clk", "send_dly_clk", "ps_clk";
        #address-cells = <1>;
        #size-cells = <0>;

        flash@0 {
            compatible = "spi-nand";
            reg = <0>;
            nand-ecc-engine = <&ecc_engine0>;
        };
    };

    ecc_engine0: ecc@43c40000 {
        compatible = "mxicy,nand-ecc-engine-rev3";
        reg = <0x43c40000 0x10000>;
    };

  - |
    /* Pipelined configuration */
    spi_controller1: spi@43c30000 {
        compatible = "mxicy,mx25f0a-spi";
        reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
        reg-names = "regs", "dirmap";
        clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
        clock-names = "send_clk", "send_dly_clk", "ps_clk";
        #address-cells = <1>;
        #size-cells = <0>;
        nand-ecc-engine = <&ecc_engine1>;

        flash@0 {
            compatible = "spi-nand";
            reg = <0>;
            nand-ecc-engine = <&spi_controller1>;
        };
    };

    ecc_engine1: ecc@43c40000 {
        compatible = "mxicy,nand-ecc-engine-rev3";
        reg = <0x43c40000 0x10000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NAND Chip and NAND Controller Generic Binding

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

allOf:
  - $ref: "mtd.yaml#"

description: |
  This file covers the generic description of a NAND chip. It implies that the
  bus interface should not be taken into account: both raw NAND devices and
  SPI-NAND devices are concerned by this description.

properties:
  reg:
    description:
      Contains the chip-select IDs.

  nand-ecc-engine:
    description: |
      A phandle on the hardware ECC engine if any. There are
      basically three possibilities:
      1/ The ECC engine is part of the NAND controller, in this
      case the phandle should reference the parent node.
      2/ The ECC engine is part of the NAND part (on-die), in this
      case the phandle should reference the node itself.
      3/ The ECC engine is external, in this case the phandle should
      reference the specific ECC engine node.
    $ref: /schemas/types.yaml#/definitions/phandle

  nand-use-soft-ecc-engine:
    description: Use a software ECC engine.
    type: boolean

  nand-no-ecc-engine:
    description: Do not use any ECC correction.
    type: boolean

  nand-ecc-algo:
    description:
      Desired ECC algorithm.
    $ref: /schemas/types.yaml#/definitions/string
    enum: [hamming, bch, rs]

  nand-ecc-strength:
    description:
      Maximum number of bits that can be corrected per ECC step.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1

  nand-ecc-step-size:
    description:
      Number of data bytes covered by a single ECC step.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1

  secure-regions:
    description:
      Regions in the NAND chip which are protected using a secure element
      like Trustzone. This property contains the start address and size of
      the secure regions present.
    $ref: /schemas/types.yaml#/definitions/uint64-matrix

required:
  - reg

# This file can be referenced by more specific devices (like spi-nands)
additionalProperties: true


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NAND Chip and NAND Controller Generic Binding

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>
  - Richard Weinberger <richard@nod.at>

description: |
  The NAND controller should be represented with its own DT node, and
  all NAND chips attached to this controller should be defined as
  children nodes of the NAND controller. This representation should be
  enforced even for simple controllers supporting only one chip.

  The ECC strength and ECC step size properties define the user
  desires in terms of correction capability of a controller. Together,
  they request the ECC engine to correct {strength} bit errors per
  {size} bytes.

  The interpretation of these parameters is implementation-defined, so
  not all implementations must support all possible
  combinations. However, implementations are encouraged to further
  specify the value(s) they support.

properties:
  $nodename:
    pattern: "^nand-controller(@.*)?"

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  ranges: true

  cs-gpios:
    description:
      Array of chip-select available to the controller. The first
      entries are a 1:1 mapping of the available chip-select on the
      NAND controller (even if they are not used). As many additional
      chip-select as needed may follow and should be phandles of GPIO
      lines. 'reg' entries of the NAND chip subnodes become indexes of
      this array when this property is present.
    minItems: 1
    maxItems: 8

patternProperties:
  "^nand@[a-f0-9]$":
    $ref: "nand-chip.yaml#"

    properties:
      reg:
        description:
          Contains the chip-select IDs.

      nand-ecc-placement:
        description:
          Location of the ECC bytes. This location is unknown by default
          but can be explicitly set to "oob", if all ECC bytes are
          known to be stored in the OOB area, or "interleaved" if ECC
          bytes will be interleaved with regular data in the main area.
        $ref: /schemas/types.yaml#/definitions/string
        enum: [ oob, interleaved ]

      nand-bus-width:
        description:
          Bus width to the NAND chip
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [8, 16]
        default: 8

      nand-on-flash-bbt:
        description:
          With this property, the OS will search the device for a Bad
          Block Table (BBT). If not found, it will create one, reserve
          a few blocks at the end of the device to store it and update
          it as the device ages. Otherwise, the out-of-band area of a
          few pages of all the blocks will be scanned at boot time to
          find Bad Block Markers (BBM). These markers will help to
          build a volatile BBT in RAM.
        $ref: /schemas/types.yaml#/definitions/flag

      nand-ecc-maximize:
        description:
          Whether or not the ECC strength should be maximized. The
          maximum ECC strength is both controller and chip
          dependent. The ECC engine has to select the ECC config
          providing the best strength and taking the OOB area size
          constraint into account. This is particularly useful when
          only the in-band area is used by the upper layers, and you
          want to make your NAND as reliable as possible.
        $ref: /schemas/types.yaml#/definitions/flag

      nand-is-boot-medium:
        description:
          Whether or not the NAND chip is a boot medium. Drivers might
          use this information to select ECC algorithms supported by
          the boot ROM or similar restrictions.
        $ref: /schemas/types.yaml#/definitions/flag

      nand-rb:
        description:
          Contains the native Ready/Busy IDs.
        $ref: /schemas/types.yaml#/definitions/uint32-array

      rb-gpios:
        description:
          Contains one or more GPIO descriptor (the numper of descriptor
          depends on the number of R/B pins exposed by the flash) for the
          Ready/Busy pins. Active state refers to the NAND ready state and
          should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.

      wp-gpios:
        description:
          Contains one GPIO descriptor for the Write Protect pin.
          Active state refers to the NAND Write Protect state and should be
          set to GPIOD_ACTIVE_LOW unless the signal is inverted.
        maxItems: 1

    required:
      - reg

required:
  - "#address-cells"
  - "#size-cells"

# This is a generic file other binding inherit from and extend
additionalProperties: true

examples:
  - |
    nand-controller {
      #address-cells = <1>;
      #size-cells = <0>;
      cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */

      /* controller specific properties */

      nand@0 {
        reg = <0>; /* Native CS */
        /* NAND chip specific properties */
      };

      nand@1 {
        reg = <1>; /* GPIO CS */
      };
    };


code:
Macronix NANDs Device Tree Bindings
-----------------------------------

Macronix NANDs support randomizer operation for scrambling user data,
which can be enabled with a SET_FEATURE. The penalty when using the
randomizer are subpage accesses prohibited and more time period needed
for program operation, i.e., tPROG 300us to 340us (randomizer enabled).
Enabling the randomizer is a one time persistent and non reversible
operation.

For more high-reliability concern, if subpage write is not available
with hardware ECC and not enabled at UBI level, then enabling the
randomizer is recommended by default by adding a new specific property
in children nodes.

Required NAND chip properties in children mode:
- randomizer enable: should be "mxic,enable-randomizer-otp"

Example:

	nand: nand-controller@unit-address {

		nand@0 {
			reg = <0>;
			mxic,enable-randomizer-otp;
		};
	};


code:
NVIDIA Tegra NAND Flash controller

Required properties:
- compatible: Must be one of:
  - "nvidia,tegra20-nand"
- reg: MMIO address range
- interrupts: interrupt output of the NFC controller
- clocks: Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
  - nand
- resets: Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
  - nand

Optional children nodes:
Individual NAND chips are children of the NAND controller node. Currently
only one NAND chip supported.

Required children node properties:
- reg: An integer ranging from 1 to 6 representing the CS line to use.

Optional children node properties:
- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
		 "hw" is supported.
- nand-ecc-algo: string, algorithm of NAND ECC.
		 Supported values with "hw" ECC mode are: "rs", "bch".
- nand-bus-width : See nand-controller.yaml
- nand-on-flash-bbt: See nand-controller.yaml
- nand-ecc-strength: integer representing the number of bits to correct
		     per ECC step (always 512). Supported strength using HW ECC
		     modes are:
		     - RS: 4, 6, 8
		     - BCH: 4, 8, 14, 16
- nand-ecc-maximize: See nand-controller.yaml
- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
		       are chosen.
- wp-gpios: GPIO specifier for the write protect pin.

Optional child node of NAND chip nodes:
Partitions: see partition.txt

  Example:
	nand-controller@70008000 {
		compatible = "nvidia,tegra20-nand";
		reg = <0x70008000 0x100>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
		clock-names = "nand";
		resets = <&tegra_car 13>;
		reset-names = "nand";

		nand@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <1>;
			nand-bus-width = <8>;
			nand-on-flash-bbt;
			nand-ecc-algo = "bch";
			nand-ecc-strength = <8>;
			wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
		};
	};


code:
* NXP SPI Flash Interface (SPIFI)

NXP SPIFI is a specialized SPI interface for serial Flash devices.
It supports one Flash device with 1-, 2- and 4-bits width in SPI
mode 0 or 3. The controller operates in either command or memory
mode. In memory mode the Flash is accessible from the CPU as
normal memory.

Required properties:
  - compatible : Should be "nxp,lpc1773-spifi"
  - reg : the first contains the register location and length,
          the second contains the memory mapping address and length
  - reg-names: Should contain the reg names "spifi" and "flash"
  - interrupts : Should contain the interrupt for the device
  - clocks : The clocks needed by the SPIFI controller
  - clock-names : Should contain the clock names "spifi" and "reg"

Optional properties:
 - resets : phandle + reset specifier

The SPI Flash must be a child of the SPIFI node and must have a
compatible property as specified in bindings/mtd/jedec,spi-nor.txt

Optionally it can also contain the following properties.
 - spi-cpol : Controller only supports mode 0 and 3 so either
              both spi-cpol and spi-cpha should be present or
              none of them
 - spi-cpha : See above
 - spi-rx-bus-width : Used to select how many pins that are used
                      for input on the controller

See bindings/spi/spi-bus.txt for more information.

Example:
spifi: spifi@40003000 {
	compatible = "nxp,lpc1773-spifi";
	reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
	reg-names = "spifi", "flash";
	interrupts = <30>;
	clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
	clock-names = "spifi", "reg";
	resets = <&rgu 53>;

	flash@0 {
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		spi-rx-bus-width = <4>;
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "data";
			reg = <0 0x200000>;
		};
	};
};


code:
NAND support for Marvell Orion SoC platforms

Required properties:
- compatible : "marvell,orion-nand".
- reg : Base physical address of the NAND and length of memory mapped
	region

Optional properties:
- cle : Address line number connected to CLE. Default is 0
- ale : Address line number connected to ALE. Default is 1
- bank-width : Width in bytes of the device. Default is 1
- chip-delay : Chip dependent delay for transferring data from array to read
               registers in usecs

The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.

Example:

nand@f4000000 {
	#address-cells = <1>;
	#size-cells = <1>;
	cle = <0>;
	ale = <1>;
	bank-width = <1>;
	chip-delay = <25>;
	compatible = "marvell,orion-nand";
	reg = <0xf4000000 0x400>;

	partition@0 {
		label = "u-boot";
		reg = <0x0000000 0x100000>;
		read-only;
	};

	partition@100000 {
		label = "uImage";
		reg = <0x0100000 0x200000>;
	};

	partition@300000 {
		label = "dtb";
		reg = <0x0300000 0x100000>;
	};

	partition@400000 {
		label = "root";
		reg = <0x0400000 0x7d00000>;
	};
};


code:
* Oxford Semiconductor OXNAS NAND Controller

Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.

Required properties:
 - compatible: "oxsemi,ox820-nand"
 - reg: Base address and length for NAND mapped memory.

Optional Properties:
 - clocks: phandle to the NAND gate clock if needed.
 - resets: phandle to the NAND reset control if needed.

Example:

nandc: nand-controller@41000000 {
	compatible = "oxsemi,ox820-nand";
	reg = <0x41000000 0x100000>;
	clocks = <&stdclk CLK_820_NAND>;
	resets = <&reset RESET_NAND>;
	#address-cells = <1>;
	#size-cells = <0>;

	nand@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		nand-ecc-mode = "soft";
		nand-ecc-algo = "hamming";

		partition@0 {
			label = "boot";
			reg = <0x00000000 0x00e00000>;
			read-only;
		};

		partition@e00000 {
			label = "ubi";
			reg = <0x00e00000 0x07200000>;
		};
	};
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/arm,arm-firmware-suite.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Firmware Suite (AFS) Partitions

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

select: false

description: |
  The ARM Firmware Suite is a flash partitioning system found on the
  ARM reference designs: Integrator AP, Integrator CP, Versatile AB,
  Versatile PB, the RealView family, Versatile Express and Juno.

properties:
  compatible:
    const: arm,arm-firmware-suite

additionalProperties: false

examples:
  - |
    partitions {
        compatible = "arm,arm-firmware-suite";
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/brcm,bcm4908-partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM4908 partitioning

description: |
  Broadcom BCM4908 CFE bootloader supports two firmware partitions. One is used
  for regular booting, the other is treated as fallback.

  This binding allows defining all fixed partitions and marking those containing
  firmware. System can use that information e.g. for booting or flashing
  purposes.

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

select: false

properties:
  compatible:
    const: brcm,bcm4908-partitions

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

patternProperties:
  "^partition@[0-9a-f]+$":
    $ref: "partition.yaml#"
    properties:
      compatible:
        const: brcm,bcm4908-firmware
    unevaluatedProperties: false

required:
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:
  - |
    partitions {
        compatible = "brcm,bcm4908-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        partition@0 {
            label = "cferom";
            reg = <0x0 0x100000>;
        };

        partition@100000 {
            compatible = "brcm,bcm4908-firmware";
            reg = <0x100000 0xf00000>;
        };

        partition@1000000 {
            compatible = "brcm,bcm4908-firmware";
            reg = <0x1000000 0xf00000>;
        };

        partition@1f00000 {
            label = "calibration";
            reg = <0x1f00000 0x100000>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/brcm,bcm947xx-cfe-partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM47xx Partitions

description: |
  Broadcom is one of hardware manufacturers providing SoCs (BCM47xx) used in
  home routers. Their BCM947xx boards using CFE bootloader have several
  partitions without any on-flash partition table. On some devices their sizes
  and/or meanings can also vary so fixed partitioning can't be used.

  Discovering partitions on these devices is possible thanks to having a special
  header and/or magic signature at the beginning of each of them. They are also
  block aligned which is important for determinig a size.

  Most of partitions use ASCII text based magic for determining a type. More
  complex partitions (like TRX with its HDR0 magic) may include extra header
  containing some details, including a length.

  A list of supported partitions includes:
  1) Bootloader with Broadcom's CFE (Common Firmware Environment)
  2) NVRAM with configuration/calibration data
  3) Device manufacturer's data with some default values (e.g. SSIDs)
  4) TRX firmware container which can hold up to 4 subpartitions
  5) Backup TRX firmware used after failed upgrade

  As mentioned earlier, role of some partitions may depend on extra
  configuration. For example both: main firmware and backup firmware use the
  same TRX format with the same header. To distinguish currently used firmware a
  CFE's environment variable "bootpartition" is used.

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

select: false

properties:
  compatible:
    const: brcm,bcm947xx-cfe-partitions

additionalProperties: false

examples:
  - |
    partitions {
        compatible = "brcm,bcm947xx-cfe-partitions";
    };


code:
Broadcom BCM963XX CFE Loader NOR Flash Partitions
=================================================

Most Broadcom BCM63XX SoC based devices follow the Broadcom reference layout for
NOR. The first erase block used for the CFE bootloader, the last for an
NVRAM partition, and the remainder in-between for one to two firmware partitions
at fixed offsets. A valid firmware partition is identified by the ImageTag
header found at beginning of the second erase block, containing the rootfs and
kernel offsets and sizes within the firmware partition.

Required properties:
- compatible : must be "brcm,bcm963xx-cfe-nor-partitions"

Example:

flash@1fc00000 {
	compatible = "cfi-flash";
	reg = <0x1fc00000 0x400000>;
	bank-width = <2>;

	partitions {
		compatible = "brcm,bcm963xx-cfe-nor-partitions";
	};
};


code:
Broadcom BCM963XX ImageTag Partition Container
==============================================

Some Broadcom BCM63XX SoC based devices contain additional, non discoverable
partitions or non standard bootloader partition sizes. For these a mixed layout
needs to be used with an explicit firmware partition.

The BCM963XX ImageTag is a simple firmware header describing the offsets and
sizes of the rootfs and kernel parts contained in the firmware.

Required properties:
- compatible : must be "brcm,bcm963xx-imagetag"

Example:

flash@1e000000 {
	compatible = "cfi-flash";
	reg = <0x1e000000 0x2000000>;
	bank-width = <2>;

	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		cfe@0 {
			reg = <0x0 0x10000>;
			read-only;
		};

		firmware@10000 {
			reg = <0x10000 0x7d0000>;
			compatible = "brcm,bcm963xx-imagetag";
		};

		caldata@7e0000 {
			reg = <0x7e0000 0x10000>;
			read-only;
		};

		nvram@7f0000 {
			reg = <0x7f0000 0x10000>;
		};
	};
};


code:
Broadcom TRX Container Partition
================================

TRX is Broadcom's official firmware format for the BCM947xx boards. It's used by
most of the vendors building devices based on Broadcom's BCM47xx SoCs and is
supported by the CFE bootloader.

Design of the TRX format is very minimalistic. Its header contains
identification fields, CRC32 checksum and the locations of embedded partitions.
Its purpose is to store a few partitions in a format that can be distributed as
a standalone file and written in a flash memory.

Container can hold up to 4 partitions. The first partition has to contain a
device executable binary (e.g. a kernel) as it's what the CFE bootloader starts
executing. Other partitions can be used for operating system purposes. This is
useful for systems that keep kernel and rootfs separated.

TRX doesn't enforce any strict partition boundaries or size limits. All
partitions have to be less than the 4GiB max size limit.

There are two existing/known TRX variants:
1) v1 which contains 3 partitions
2) v2 which contains 4 partitions

There aren't separated compatible bindings for them as version can be trivialy
detected by a software parsing TRX header.

Required properties:
- compatible : (required) must be "brcm,trx"

Optional properties:

- brcm,trx-magic: TRX magic, if it is different from the default magic
		  0x30524448 as a u32.

Example:

flash@0 {
	partitions {
		compatible = "brcm,trx";
	};
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/fixed-partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Fixed partitions

description: |
  This binding can be used on platforms which have strong conventions about
  which portions of a flash are used for what purposes, but which don't use an
  on-flash partition table such as RedBoot.

  The partition table should be a node named "partitions". Partitions are then
  defined as subnodes.

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

properties:
  compatible:
    oneOf:
      - const: fixed-partitions
      - items:
          - const: sercomm,sc-partitions
          - const: fixed-partitions

  "#address-cells": true

  "#size-cells": true

patternProperties:
  "@[0-9a-f]+$":
    $ref: partition.yaml#

    properties:
      sercomm,scpart-id:
        description: Partition id in Sercomm partition map. Mtd parser
          uses this id to find a record in the partition map containing
          offset and size of the current partition. The values from
          partition map overrides partition offset and size defined in
          reg property of the dts. Frequently these values are the same,
          but may differ if device has bad eraseblocks on a flash.
        $ref: /schemas/types.yaml#/definitions/uint32

required:
  - "#address-cells"
  - "#size-cells"

additionalProperties: true

examples:
  - |
    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        partition@0 {
            label = "u-boot";
            reg = <0x0000000 0x100000>;
            read-only;
        };

        uimage@100000 {
            reg = <0x0100000 0x200000>;
        };
    };

  - |
    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <2>;

        /* a 4 GiB partition */
        partition@0 {
            label = "filesystem";
            reg = <0x00000000 0x1 0x00000000>;
            linux,rootfs;
        };
    };

  - |
    partitions {
        compatible = "fixed-partitions";
        #address-cells = <2>;
        #size-cells = <2>;

        /* an 8 GiB partition */
        partition@0 {
            label = "filesystem #1";
            reg = <0x0 0x00000000 0x2 0x00000000>;
        };

        /* a 4 GiB partition */
        partition@200000000 {
            label = "filesystem #2";
            reg = <0x2 0x00000000 0x1 0x00000000>;
        };
    };

  - |
    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        partition@0 {
            label = "bootloader";
            reg = <0x000000 0x100000>;
            read-only;
        };

        firmware@100000 {
            compatible = "brcm,trx";
            label = "firmware";
            reg = <0x100000 0xe00000>;
        };

        calibration@f00000 {
            compatible = "fixed-partitions";
            label = "calibration";
            reg = <0xf00000 0x100000>;
            ranges = <0 0xf00000 0x100000>;
            #address-cells = <1>;
            #size-cells = <1>;

            partition@0 {
                label = "wifi0";
                reg = <0x000000 0x080000>;
            };

            partition@80000 {
                label = "wifi1";
                reg = <0x080000 0x080000>;
            };
        };
    };

  - |
    partitions {
        compatible = "sercomm,sc-partitions", "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        partition@0 {
            label = "u-boot";
            reg = <0x0 0x100000>;
            sercomm,scpart-id = <0>;
            read-only;
        };

        partition@100000 {
            label = "dynamic partition map";
            reg = <0x100000 0x100000>;
            sercomm,scpart-id = <1>;
        };

        partition@200000 {
            label = "Factory";
            reg = <0x200000 0x100000>;
            sercomm,scpart-id = <2>;
            read-only;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/linksys,ns-partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Linksys Northstar partitioning

description: |
  Linksys devices based on Broadcom Northstar architecture often use two
  firmware partitions. One is used for regular booting, the other is treated as
  fallback.

  This binding allows defining all fixed partitions and marking those containing
  firmware. System can use that information e.g. for booting or flashing
  purposes.

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

select: false

properties:
  compatible:
    const: linksys,ns-partitions

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

patternProperties:
  "^partition@[0-9a-f]+$":
    $ref: "partition.yaml#"
    properties:
      compatible:
        items:
          - const: linksys,ns-firmware
          - const: brcm,trx
    unevaluatedProperties: false

required:
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:
  - |
    partitions {
        compatible = "linksys,ns-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        partition@0 {
            label = "boot";
            reg = <0x0 0x100000>;
            read-only;
        };

        partition@100000 {
            label = "nvram";
            reg = <0x100000 0x100000>;
        };

        partition@200000 {
            compatible = "linksys,ns-firmware", "brcm,trx";
            reg = <0x200000 0xf00000>;
        };

        partition@1100000 {
            compatible = "linksys,ns-firmware", "brcm,trx";
            reg = <0x1100000 0xf00000>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/nvmem-cells.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Nvmem cells

description: |
  Any partition containing the compatible "nvmem-cells" will register as a
  nvmem provider.
  Each direct subnodes represents a nvmem cell following the nvmem binding.
  Nvmem binding to declare nvmem-cells can be found in:
  Documentation/devicetree/bindings/nvmem/nvmem.yaml

maintainers:
  - Ansuel Smith <ansuelsmth@gmail.com>

allOf:
  - $ref: /schemas/mtd/partitions/partition.yaml#
  - $ref: /schemas/nvmem/nvmem.yaml#

properties:
  compatible:
    const: nvmem-cells

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    partitions {
      compatible = "fixed-partitions";
      #address-cells = <1>;
      #size-cells = <1>;

      /* ... */

      };
      art: art@1200000 {
        compatible = "nvmem-cells";
        reg = <0x1200000 0x0140000>;
        label = "art";
        read-only;
        #address-cells = <1>;
        #size-cells = <1>;

        macaddr_gmac1: macaddr_gmac1@0 {
          reg = <0x0 0x6>;
        };

        macaddr_gmac2: macaddr_gmac2@6 {
          reg = <0x6 0x6>;
        };

        pre_cal_24g: pre_cal_24g@1000 {
          reg = <0x1000 0x2f20>;
        };

        pre_cal_5g: pre_cal_5g@5000{
          reg = <0x5000 0x2f20>;
        };
      };
  - |
    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        partition@0 {
            label = "bootloader";
            reg = <0x000000 0x100000>;
            read-only;
        };

        firmware@100000 {
            compatible = "brcm,trx";
            label = "firmware";
            reg = <0x100000 0xe00000>;
        };

        calibration@f00000 {
            compatible = "nvmem-cells";
            label = "calibration";
            reg = <0xf00000 0x100000>;
            #address-cells = <1>;
            #size-cells = <1>;

            wifi0@0 {
                reg = <0x000000 0x080000>;
            };

            wifi1@80000 {
                reg = <0x080000 0x080000>;
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/partition.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Partition

description: |
  This binding describes a single flash partition. Each partition must have its
  relative offset and size specified. Depending on partition function extra
  properties can be used.

  A partition may be dynamically allocated by a specific parser at runtime.
  In this specific case, a specific suffix is required to the node name.
  Everything after 'partition-' will be used as the partition name to compare
  with the one dynamically allocated by the specific parser.
  If the partition contains invalid char a label can be provided that will
  be used instead of the node name to make the comparison.
  This is used to assign an OF node to the dynamiccally allocated partition
  so that subsystem like NVMEM can provide an OF node and declare NVMEM cells.
  The OF node will be assigned only if the partition label declared match the
  one assigned by the parser at runtime.

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

properties:
  reg:
    description: partition's offset and size within the flash
    maxItems: 1

  label:
    description: The label / name for this partition. If omitted, the label
      is taken from the node name (excluding the unit address).

  read-only:
    description: This parameter, if present, is a hint that this partition
      should only be mounted read-only. This is usually used for flash
      partitions containing early-boot firmware images or data which should
      not be clobbered.
    type: boolean

  lock:
    description: Do not unlock the partition at initialization time (not
      supported on all devices)
    type: boolean

  slc-mode:
    description: This parameter, if present, allows one to emulate SLC mode
      on a partition attached to an MLC NAND thus making this partition
      immune to paired-pages corruptions
    type: boolean

  linux,rootfs:
    description: Marks partition that contains root filesystem to mount and boot
      user space from

if:
  not:
    required: [ reg ]
then:
  properties:
    $nodename:
      pattern: '^partition-.*$'

# This is a generic file other binding inherit from and extend
additionalProperties: true


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Partitions

description: |
  This binding is generic and describes the content of the partitions container
  node. All partition parsers must be referenced here.

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

oneOf:
  - $ref: arm,arm-firmware-suite.yaml
  - $ref: brcm,bcm4908-partitions.yaml
  - $ref: brcm,bcm947xx-cfe-partitions.yaml
  - $ref: fixed-partitions.yaml
  - $ref: linksys,ns-partitions.yaml
  - $ref: qcom,smem-part.yaml
  - $ref: redboot-fis.yaml

properties:
  compatible: true

  '#address-cells':
    enum: [1, 2]

  '#size-cells':
    enum: [1, 2]

patternProperties:
  "partition(-.+|@[0-9a-f]+)":
    $ref: partition.yaml

required:
  - compatible

unevaluatedProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/qcom,smem-part.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SMEM NAND flash partition parser binding

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

description: |
  The Qualcomm SoCs supporting the NAND controller interface features a Shared
  Memory (SMEM) based partition table scheme. The maximum partitions supported
  varies between partition table revisions. V3 supports maximum 16 partitions
  and V4 supports 48 partitions.

select: false

properties:
  compatible:
    const: qcom,smem-part

patternProperties:
  "^partition-[0-9a-z]+$":
    $ref: nvmem-cells.yaml

required:
  - compatible

additionalProperties: false

examples:
  - |
    flash {
        partitions {
            compatible = "qcom,smem-part";
        };
    };

  - |
    /* Example declaring dynamic partition */
    flash {
        partitions {
            compatible = "qcom,smem-part";

            partition-art {
                compatible = "nvmem-cells";
                #address-cells = <1>;
                #size-cells = <1>;
                label = "0:art";

                macaddr_art_0: macaddr@0 {
                    reg = <0x0 0x6>;
                };

                macaddr_art_6: macaddr@6 {
                    reg = <0x6 0x6>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/redboot-fis.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RedBoot FLASH Image System (FIS) Partitions

description: The FLASH Image System (FIS) directory is a flash description
    format closely associated with the RedBoot boot loader.
    It uses one single flash eraseblock in the flash to store an index of
    all images in the flash.
    This block size will vary depending on flash but is typically
    32 KB in size.

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

select: false

properties:
  compatible:
    const: redboot-fis

  fis-index-block:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: a index to the eraseblock containing the FIS directory on this
      device. On a flash memory with 32KB eraseblocks, 0 means the first
      eraseblock at 0x00000000, 1 means the second eraseblock at 0x00008000 and so on.

  '#address-cells': false

  '#size-cells': false

required:
  - compatible
  - fis-index-block

additionalProperties: false

examples:
  - |
    flash {
      partitions {
        compatible = "redboot-fis";
        fis-index-block = <0>;
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/tplink,safeloader-partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TP-Link SafeLoader partitions

description: |
  TP-Link home routers store various data on flash (e.g. bootloader,
  flash layout, firmware, product info, configuration, calibration
  data). That requires flash partitioning.

  Flash space layout of TP-Link devices is stored on flash itself using
  a custom ASCII-based format. That format was first found in TP-Link
  devices with a custom SafeLoader bootloader. Later it was adapted to
  CFE and U-Boot bootloaders.

  Partitions specified in partitions table cover whole flash space. Some
  contain static data that shouldn't get modified (device's MAC or WiFi
  calibration data). Others are semi-static (like kernel). Finally some
  partitions contain fully changeable content (like rootfs).

  This binding describes partitioning method and defines offset of ASCII
  based partitions table. That offset is picked at manufacturing process
  and doesn't change.

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

properties:
  compatible:
    const: tplink,safeloader-partitions

  partitions-table-offset:
    description: Flash offset of partitions table
    $ref: /schemas/types.yaml#/definitions/uint32

patternProperties:
  "^partition-.*$":
    $ref: partition.yaml#

required:
  - partitions-table-offset

additionalProperties: false

examples:
  - |
    partitions {
        compatible = "tplink,safeloader-partitions";
        partitions-table-offset = <0x100000>;

        partition-file-system {
                linux,rootfs;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/u-boot.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: U-Boot bootloader partition

description: |
  U-Boot is a bootlodaer commonly used in embedded devices. It's almost always
  located on some kind of flash device.

  Device configuration is stored as a set of environment variables that are
  located in a (usually standalone) block of data.

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

allOf:
  - $ref: partition.yaml#

properties:
  compatible:
    oneOf:
      - const: brcm,u-boot
        description: |
          Broadcom stores environment variables inside a U-Boot partition. They
          can be identified by a custom header with magic value.

patternProperties:
  "^partition-.*$":
    $ref: partition.yaml#

unevaluatedProperties: false

examples:
  - |
    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        partition@0 {
            compatible = "brcm,u-boot";
            reg = <0x0 0x100000>;
            label = "u-boot";

            partition-u-boot-env {
            };
        };

        partition@100000 {
            reg = <0x100000 0x1ff00000>;
            label = "firmware";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm NAND controller

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

properties:
  compatible:
    enum:
      - qcom,ipq806x-nand
      - qcom,ipq4019-nand
      - qcom,ipq6018-nand
      - qcom,ipq8074-nand
      - qcom,sdx55-nand

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Core Clock
      - description: Always ON Clock

  clock-names:
    items:
      - const: core
      - const: aon

patternProperties:
  "^nand@[a-f0-9]$":
    type: object
    properties:
      nand-bus-width:
        const: 8

      nand-ecc-strength:
        enum: [1, 4, 8]

      nand-ecc-step-size:
        enum:
          - 512

allOf:
  - $ref: "nand-controller.yaml#"

  - if:
      properties:
        compatible:
          contains:
            const: qcom,ipq806x-nand
    then:
      properties:
        dmas:
          items:
            - description: rxtx DMA channel

        dma-names:
          items:
            - const: rxtx

        qcom,cmd-crci:
          $ref: /schemas/types.yaml#/definitions/uint32
          description:
            Must contain the ADM command type CRCI block instance number
            specified for the NAND controller on the given platform

        qcom,data-crci:
          $ref: /schemas/types.yaml#/definitions/uint32
          description:
            Must contain the ADM data type CRCI block instance number
            specified for the NAND controller on the given platform

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq4019-nand
              - qcom,ipq6018-nand
              - qcom,ipq8074-nand
              - qcom,sdx55-nand

    then:
      properties:
        dmas:
          items:
            - description: tx DMA channel
            - description: rx DMA channel
            - description: cmd DMA channel

        dma-names:
          items:
            - const: tx
            - const: rx
            - const: cmd

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq806x-nand

    then:
      properties:
        qcom,boot-partitions:
          $ref: /schemas/types.yaml#/definitions/uint32-matrix
          items:
            items:
              - description: offset
              - description: size
          description:
            Boot partition use a different layout where the 4 bytes of spare
            data are not protected by ECC. Use this to declare these special
            partitions by defining first the offset and then the size.

            It's in the form of <offset1 size1 offset2 size2 offset3 ...>
            and should be declared in ascending order.

            Refer to the ipq8064 example on how to use this special binding.

required:
  - compatible
  - reg
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
    nand-controller@1ac00000 {
        compatible = "qcom,ipq806x-nand";
        reg = <0x1ac00000 0x800>;

        clocks = <&gcc EBI2_CLK>,
                 <&gcc EBI2_AON_CLK>;
        clock-names = "core", "aon";

        dmas = <&adm_dma 3>;
        dma-names = "rxtx";
        qcom,cmd-crci = <15>;
        qcom,data-crci = <3>;

        #address-cells = <1>;
        #size-cells = <0>;

        nand@0 {
            reg = <0>;

            nand-ecc-strength = <4>;
            nand-bus-width = <8>;

            qcom,boot-partitions = <0x0 0x58a0000>;

            partitions {
                compatible = "fixed-partitions";
                #address-cells = <1>;
                #size-cells = <1>;

                partition@0 {
                    label = "boot-nand";
                    reg = <0 0x58a0000>;
                };

                partition@58a0000 {
                    label = "fs-nand";
                    reg = <0x58a0000 0x4000000>;
                };
            };
        };
    };

    #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
    nand-controller@79b0000 {
        compatible = "qcom,ipq4019-nand";
        reg = <0x79b0000 0x1000>;

        clocks = <&gcc GCC_QPIC_CLK>,
                 <&gcc GCC_QPIC_AHB_CLK>;
        clock-names = "core", "aon";

        dmas = <&qpicbam 0>,
               <&qpicbam 1>,
               <&qpicbam 2>;
        dma-names = "tx", "rx", "cmd";

        #address-cells = <1>;
        #size-cells = <0>;

        nand@0 {
            reg = <0>;
            nand-ecc-strength = <4>;
            nand-bus-width = <8>;

            partitions {
                compatible = "fixed-partitions";
                #address-cells = <1>;
                #size-cells = <1>;

                partition@0 {
                    label = "boot-nand";
                    reg = <0 0x58a0000>;
                };

                partition@58a0000 {
                    label = "fs-nand";
                    reg = <0x58a0000 0x4000000>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/renesas-nandc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car Gen3 & RZ/N1x NAND flash controller

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

allOf:
  - $ref: "nand-controller.yaml"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,r9a06g032-nandc
          - const: renesas,rzn1-nandc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: APB host controller clock
      - description: External NAND bus clock

  clock-names:
    items:
      - const: hclk
      - const: eclk

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/r9a06g032-sysctrl.h>

    nand-controller@40102000 {
        compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
        reg = <0x40102000 0x2000>;
        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
        clock-names = "hclk", "eclk";
        power-domains = <&sysctrl>;
        #address-cells = <1>;
        #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip SoCs NAND FLASH Controller (NFC)

allOf:
  - $ref: "nand-controller.yaml#"

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    oneOf:
      - const: rockchip,px30-nfc
      - const: rockchip,rk2928-nfc
      - const: rockchip,rv1108-nfc
      - items:
          - enum:
              - rockchip,rk3036-nfc
              - rockchip,rk3128-nfc
          - const: rockchip,rk2928-nfc
      - items:
          - const: rockchip,rk3308-nfc
          - const: rockchip,rv1108-nfc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: Bus Clock
      - description: Module Clock

  clock-names:
    minItems: 1
    items:
      - const: ahb
      - const: nfc

  assigned-clocks:
    maxItems: 1

  assigned-clock-rates:
    maxItems: 1

  power-domains:
    maxItems: 1

patternProperties:
  "^nand@[0-7]$":
    type: object
    properties:
      reg:
        minimum: 0
        maximum: 7

      nand-ecc-mode:
        const: hw

      nand-ecc-step-size:
        const: 1024

      nand-ecc-strength:
        enum: [16, 24, 40, 60, 70]
        description: |
          The ECC configurations that can be supported are as follows.
            NFC v600 ECC 16, 24, 40, 60
              RK2928, RK3066, RK3188

            NFC v622 ECC 16, 24, 40, 60
              RK3036, RK3128

            NFC v800 ECC 16
              RK3308, RV1108

            NFC v900 ECC 16, 40, 60, 70
              RK3326, PX30

      nand-bus-width:
        const: 8

      rockchip,boot-blks:
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 2
        default: 16
        description:
          The NFC driver need this information to select ECC
          algorithms supported by the boot ROM.
          Only used in combination with 'nand-is-boot-medium'.

      rockchip,boot-ecc-strength:
        enum: [16, 24, 40, 60, 70]
        $ref: /schemas/types.yaml#/definitions/uint32
        description: |
          If specified it indicates that a different BCH/ECC setting is
          supported by the boot ROM.
            NFC v600 ECC 16, 24
              RK2928, RK3066, RK3188

            NFC v622 ECC 16, 24, 40, 60
              RK3036, RK3128

            NFC v800 ECC 16
              RK3308, RV1108

            NFC v900 ECC 16, 70
              RK3326, PX30

          Only used in combination with 'nand-is-boot-medium'.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3308-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    nfc: nand-controller@ff4b0000 {
      compatible = "rockchip,rk3308-nfc",
                   "rockchip,rv1108-nfc";
      reg = <0xff4b0000 0x4000>;
      interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
      clock-names = "ahb", "nfc";
      assigned-clocks = <&clks SCLK_NANDC>;
      assigned-clock-rates = <150000000>;

      pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
                   &flash_rdn &flash_rdy &flash_wrn>;
      pinctrl-names = "default";

      #address-cells = <1>;
      #size-cells = <0>;

      nand@0 {
        reg = <0>;
        label = "rk-nand";
        nand-bus-width = <8>;
        nand-ecc-mode = "hw";
        nand-ecc-step-size = <1024>;
        nand-ecc-strength = <16>;
        nand-is-boot-medium;
        rockchip,boot-blks = <8>;
        rockchip,boot-ecc-strength = <16>;
      };
    };

...


code:
* Samsung S3C2410 and compatible NAND flash controller

Required properties:
- compatible : The possible values are:
	"samsung,s3c2410-nand"
	"samsung,s3c2412-nand"
	"samsung,s3c2440-nand"
- reg : register's location and length.
- #address-cells, #size-cells : see nand-controller.yaml
- clocks : phandle to the nand controller clock
- clock-names : must contain "nand"

Optional child nodes:
Child nodes representing the available nand chips.

Optional child properties:
- nand-ecc-mode : see nand-controller.yaml
- nand-on-flash-bbt : see nand-controller.yaml

Each child device node may optionally contain a 'partitions' sub-node,
which further contains sub-nodes describing the flash partition mapping.
See partition.txt for more detail.

Example:

nand-controller@4e000000 {
	compatible = "samsung,s3c2440-nand";
	reg = <0x4e000000 0x40>;

	#address-cells = <1>;
        #size-cells = <0>;

	clocks = <&clocks HCLK_NAND>;
	clock-names = "nand";

	nand {
		nand-ecc-mode = "soft";
		nand-on-flash-bbt;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0 0x040000>;
			};

			partition@40000 {
				label = "kernel";
				reg = <0x040000 0x500000>;
			};
		};
	};
};


code:
* SPEAr SMI

Required properties:
- compatible : "st,spear600-smi"
- reg : Address range of the mtd chip
- #address-cells, #size-cells : Must be present if the device has sub-nodes
  representing partitions.
- interrupts: Should contain the STMMAC interrupts
- clock-rate : Functional clock rate of SMI in Hz

Optional properties:
- st,smi-fast-mode : Flash supports read in fast mode

Example:

	smi: flash@fc000000 {
		compatible = "st,spear600-smi";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0xfc000000 0x1000>;
		interrupt-parent = <&vic1>;
		interrupts = <12>;
		clock-rate = <50000000>;	/* 50MHz */

		flash@f8000000 {
			st,smi-fast-mode;
			...
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/spi-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SPI-NAND flash

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

allOf:
  - $ref: "nand-chip.yaml#"
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

properties:
  compatible:
    const: spi-nand

  reg:
    description: Encode the chip-select line on the SPI bus
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings

maintainers:
  - Christophe Kerello <christophe.kerello@foss.st.com>

properties:
  compatible:
    enum:
      - st,stm32mp15-fmc2
      - st,stm32mp1-fmc2-nfc

  reg:
    minItems: 6
    maxItems: 7

  interrupts:
    maxItems: 1

  dmas:
    items:
      - description: tx DMA channel
      - description: rx DMA channel
      - description: ecc DMA channel

  dma-names:
    items:
      - const: tx
      - const: rx
      - const: ecc

patternProperties:
  "^nand@[a-f0-9]$":
    type: object
    properties:
      nand-ecc-step-size:
        const: 512

      nand-ecc-strength:
        enum: [1, 4, 8]

allOf:
  - $ref: "nand-controller.yaml#"

  - if:
      properties:
        compatible:
          contains:
            const: st,stm32mp15-fmc2
    then:
      properties:
        reg:
          items:
            - description: Registers
            - description: Chip select 0 data
            - description: Chip select 0 command
            - description: Chip select 0 address space
            - description: Chip select 1 data
            - description: Chip select 1 command
            - description: Chip select 1 address space

        clocks:
          maxItems: 1

        resets:
          maxItems: 1

      required:
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: st,stm32mp1-fmc2-nfc
    then:
      properties:
        reg:
          items:
            - description: Chip select 0 data
            - description: Chip select 0 command
            - description: Chip select 0 address space
            - description: Chip select 1 data
            - description: Chip select 1 command
            - description: Chip select 1 address space

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>

    nand-controller@58002000 {
        compatible = "st,stm32mp15-fmc2";
        reg = <0x58002000 0x1000>,
              <0x80000000 0x1000>,
              <0x88010000 0x1000>,
              <0x88020000 0x1000>,
              <0x81000000 0x1000>,
              <0x89010000 0x1000>,
              <0x89020000 0x1000>;
        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
        dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
               <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
               <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
        dma-names = "tx", "rx", "ecc";
        clocks = <&rcc FMC_K>;
        resets = <&rcc FMC_R>;
        #address-cells = <1>;
        #size-cells = <0>;

        nand@0 {
            reg = <0>;
            nand-on-flash-bbt;
            #address-cells = <1>;
            #size-cells = <1>;
        };
    };

...


code:
* ST-Microelectronics SPI FSM Serial (NOR) Flash Controller

Required properties:
  - compatible : Should be "st,spi-fsm"
  - reg        : Contains register's location and length.
  - reg-names  : Should contain the reg names "spi-fsm"
  - interrupts : The interrupt number
  - pinctrl-0  : Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)

Optional properties:
  - st,syscfg          : Phandle to boot-device system configuration registers
  - st,boot-device-reg : Address of the aforementioned boot-device register(s)
  - st,boot-device-spi : Expected boot-device value if booted via this device

Example:
	spifsm: spifsm@fe902000{
	        compatible         = "st,spi-fsm";
	        reg                =  <0xfe902000 0x1000>;
	        reg-names          = "spi-fsm";
	        pinctrl-0          = <&pinctrl_fsm>;
		st,syscfg	   = <&syscfg_rear>;
	        st,boot-device-reg = <0x958>;
	        st,boot-device-spi = <0x1a>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,am654-hbmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: HyperBus Memory Controller (HBMC) on TI's K3 family of SoCs

maintainers:
  - Vignesh Raghavendra <vigneshr@ti.com>

properties:
  compatible:
    const: ti,am654-hbmc

  reg:
    maxItems: 2

  power-domains: true
  '#address-cells': true
  '#size-cells': true
  ranges: true

  mux-controls:
    description: MMIO mux controller node to select b/w OSPI and HBMC.

  clocks:
    maxItems: 1

patternProperties:
  "^flash@[0-1],[0-9a-f]+$":
    type: object

required:
  - compatible
  - reg
  - ranges
  - clocks
  - '#address-cells'
  - '#size-cells'

additionalProperties: false

examples:
  - |
    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        hbmc: memory-controller@47034000 {
            compatible = "ti,am654-hbmc";
            reg = <0x0 0x47034000 0x0 0x100>,
                  <0x5 0x00000000 0x1 0x0000000>;
            ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
                     <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
            clocks = <&k3_clks 102 0>;
            #address-cells = <2>;
            #size-cells = <1>;
            power-domains = <&k3_pds 55>;
            mux-controls = <&hbmc_mux 0>;

            flash@0,0 {
                compatible = "cypress,hyperflash", "cfi-flash";
                reg = <0x0 0x0 0x4000000>;
                #address-cells = <1>;
                #size-cells = <1>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,elm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments Error Location Module (ELM).

maintainers:
  - Roger Quadros <rogerq@kernel.org>

description:
  ELM module is used together with GPMC and NAND Flash to detect
  errors and the location of the error based on BCH algorithms
  so they can be corrected if possible.

properties:
  compatible:
    enum:
      - ti,am3352-elm
      - ti,am64-elm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1
    description: Functional clock.

  clock-names:
    items:
      - const: fck

  power-domains:
    maxItems: 1

  ti,hwmods:
    description:
      Name of the HWMOD associated with ELM. This is for legacy
      platforms only.
    $ref: /schemas/types.yaml#/definitions/string
    deprecated: true

required:
  - compatible
  - reg
  - interrupts

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: ti,am64-elm
    then:
      required:
        - clocks
        - clock-names
        - power-domains

additionalProperties: false

examples:
  - |
    elm: ecc@0 {
        compatible = "ti,am3352-elm";
        reg = <0x0 0x2000>;
        interrupts = <4>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments GPMC NAND Flash controller.

maintainers:
  - Tony Lindgren <tony@atomide.com>
  - Roger Quadros <rogerq@kernel.org>

description:
  GPMC NAND controller/Flash is represented as a child of the
  GPMC controller node.

properties:
  compatible:
    items:
      - enum:
          - ti,am64-nand
          - ti,omap2-nand

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: Interrupt for fifoevent
      - description: Interrupt for termcount

  "#address-cells": true

  "#size-cells": true

  ti,nand-ecc-opt:
    description: Desired ECC algorithm
    $ref: /schemas/types.yaml#/definitions/string
    enum: [sw, ham1, bch4, bch8, bch16]

  ti,nand-xfer-type:
    description: Data transfer method between controller and chip.
    $ref: /schemas/types.yaml#/definitions/string
    enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq]
    default: prefetch-polled

  ti,elm-id:
    description:
      phandle to the ELM (Error Location Module).
    $ref: /schemas/types.yaml#/definitions/phandle

  nand-bus-width:
    description:
      Bus width to the NAND chip
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [8, 16]
    default: 8

  rb-gpios:
    description:
      GPIO connection to R/B signal from NAND chip
    maxItems: 1

patternProperties:
  "@[0-9a-f]+$":
    $ref: "/schemas/mtd/partitions/partition.yaml"

allOf:
  - $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml"

required:
  - compatible
  - reg
  - ti,nand-ecc-opt

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/gpio/gpio.h>

    gpmc: memory-controller@50000000 {
      compatible = "ti,am3352-gpmc";
      dmas = <&edma 52 0>;
      dma-names = "rxtx";
      clocks = <&l3s_gclk>;
      clock-names = "fck";
      reg = <0x50000000 0x2000>;
      interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
      gpmc,num-cs = <7>;
      gpmc,num-waitpins = <2>;
      #address-cells = <2>;
      #size-cells = <1>;
      interrupt-controller;
      #interrupt-cells = <2>;
      gpio-controller;
      #gpio-cells = <2>;

      ranges = <0 0 0x08000000 0x01000000>;   /* CS0 space. Min partition = 16MB */
      nand@0,0 {
        compatible = "ti,omap2-nand";
        reg = <0 0 4>;          /* device IO registers */
        interrupt-parent = <&gpmc>;
        interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                     <1 IRQ_TYPE_NONE>; /* termcount */
        ti,nand-xfer-type = "prefetch-dma";
        ti,nand-ecc-opt = "bch16";
        ti,elm-id = <&elm>;
        #address-cells = <1>;
        #size-cells = <1>;

        /* NAND generic properties */
        nand-bus-width = <8>;
        rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;  /* gpmc_wait0 */

        /* GPMC properties*/
        gpmc,device-width = <1>;

        partition@0 {
          label = "NAND.SPL";
          reg = <0x00000000 0x00040000>;
        };
        partition@1 {
          label = "NAND.SPL.backup1";
          reg = <0x00040000 0x00040000>;
        };
      };
    };