code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,glink-edge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm G-Link Edge communication channel nodes

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  Qualcomm G-Link subnode represents communication edge, channels and devices
  related to the remote processor.

properties:
  $nodename:
    const: "glink-edge"

  apr:
    $ref: /schemas/soc/qcom/qcom,apr.yaml#
    required:
      - qcom,glink-channels
    description:
      Qualcomm APR/GPR (Asynchronous/Generic Packet Router)

  fastrpc:
    $ref: /schemas/misc/qcom,fastrpc.yaml#
    required:
      - qcom,glink-channels
    description:
      Qualcomm FastRPC

  interrupts:
    maxItems: 1

  label:
    description: The names of the state bits used for SMP2P output

  mboxes:
    maxItems: 1

  qcom,remote-pid:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      ID of the shared memory used by GLINK for communication with remote
      processor.

required:
  - interrupts
  - label
  - mboxes
  - qcom,remote-pid

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/mailbox/qcom-ipcc.h>

    remoteproc@8a00000 {
        reg = <0x08a00000 0x10000>;
        // ...

        glink-edge {
            interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
                                         IPCC_MPROC_SIGNAL_GLINK_QMP
                                         IRQ_TYPE_EDGE_RISING>;
            mboxes = <&ipcc IPCC_CLIENT_WPSS
                            IPCC_MPROC_SIGNAL_GLINK_QMP>;

            label = "wpss";
            qcom,remote-pid = <13>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,pil-info.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm peripheral image loader relocation info binding

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  The Qualcomm peripheral image loader relocation memory region, in IMEM, is
  used for communicating remoteproc relocation information to post mortem
  debugging tools.

properties:
  compatible:
    const: qcom,pil-reloc-info

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    imem@146bf000 {
      compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
      reg = <0x146bf000 0x1000>;

      #address-cells = <1>;
      #size-cells = <1>;

      ranges = <0 0x146bf000 0x1000>;

      pil-reloc@94c {
        compatible = "qcom,pil-reloc-info";
        reg = <0x94c 0xc8>;
      };
    };
...

repo_name: angery/linux


code:
Qualcomm Hexagon Peripheral Image Loader

This document defines the binding for a component that loads and boots firmware
on the Qualcomm Hexagon core.

- compatible:
	Usage: required
	Value type: <string>
	Definition: must be one of:
		    "qcom,q6v5-pil",
		    "qcom,ipq8074-wcss-pil"
		    "qcom,qcs404-wcss-pil"
		    "qcom,msm8916-mss-pil",
		    "qcom,msm8974-mss-pil"
		    "qcom,msm8996-mss-pil"
		    "qcom,msm8998-mss-pil"
		    "qcom,sdm845-mss-pil"

- reg:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: must specify the base address and size of the qdsp6 and
		    rmb register blocks

- reg-names:
	Usage: required
	Value type: <stringlist>
	Definition: must be "q6dsp" and "rmb"

- interrupts-extended:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: reference to the interrupts that match interrupt-names

- interrupt-names:
	Usage: required
	Value type: <stringlist>
	Definition: The interrupts needed depends on the compatible
		    string:
	qcom,q6v5-pil:
	qcom,ipq8074-wcss-pil:
	qcom,qcs404-wcss-pil:
	qcom,msm8916-mss-pil:
	qcom,msm8974-mss-pil:
		    must be "wdog", "fatal", "ready", "handover", "stop-ack"
	qcom,msm8996-mss-pil:
	qcom,msm8998-mss-pil:
	qcom,sdm845-mss-pil:
		    must be "wdog", "fatal", "ready", "handover", "stop-ack",
		    "shutdown-ack"

- firmware-name:
	Usage: optional
	Value type: <stringlist>
	Definition: must list the relative firmware image paths for mba and
		    modem. They are used for booting and authenticating the
		    Hexagon core.

- clocks:
	Usage: required
	Value type: <phandle>
	Definition: reference to the clocks that match clock-names

- clock-names:
	Usage: required
	Value type: <stringlist>
	Definition: The clocks needed depend on the compatible string:
	qcom,ipq8074-wcss-pil:
		    no clock names required
	qcom,qcs404-wcss-pil:
		    must be "xo", "gcc_abhs_cbcr", "gcc_abhs_cbcr",
		    "gcc_axim_cbcr", "lcc_ahbfabric_cbc", "tcsr_lcc_cbc",
		    "lcc_abhs_cbc", "lcc_tcm_slave_cbc", "lcc_abhm_cbc",
		    "lcc_axim_cbc", "lcc_bcr_sleep"
	qcom,q6v5-pil:
	qcom,msm8916-mss-pil:
	qcom,msm8974-mss-pil:
		    must be "iface", "bus", "mem", "xo"
	qcom,msm8996-mss-pil:
		    must be "iface", "bus", "mem", "xo", "gpll0_mss",
		    "snoc_axi", "mnoc_axi", "pnoc", "qdss"
	qcom,msm8998-mss-pil:
		    must be "iface", "bus", "mem", "xo", "gpll0_mss",
		    "snoc_axi", "mnoc_axi", "qdss"
	qcom,sdm845-mss-pil:
		    must be "iface", "bus", "mem", "xo", "gpll0_mss",
		    "snoc_axi", "mnoc_axi", "prng"

- resets:
	Usage: required
	Value type: <phandle>
	Definition: reference to the reset-controller for the modem sub-system
		    reference to the list of 3 reset-controllers for the
		    wcss sub-system
		    reference to the list of 2 reset-controllers for the modem
		    sub-system on SDM845 SoCs

- reset-names:
	Usage: required
	Value type: <stringlist>
	Definition: must be "mss_restart" for the modem sub-system
		    must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset"
		    for the wcss sub-system
		    must be "mss_restart", "pdc_reset" for the modem
		    sub-system on SDM845 SoCs

For devices where the mba and mpss sub-nodes are not specified, mba/mpss region
should be referenced as follows:
- memory-region:
	Usage: required
	Value type: <phandle>
	Definition: reference to the reserved-memory for the mba region followed
		    by the mpss region

For the compatible strings below the following supplies are required:
  "qcom,q6v5-pil"
  "qcom,msm8916-mss-pil",
- cx-supply: (deprecated, use power domain instead)
- mx-supply: (deprecated, use power domain instead)
- pll-supply:
	Usage: required
	Value type: <phandle>
	Definition: reference to the regulators to be held on behalf of the
		    booting of the Hexagon core

For the compatible string below the following supplies are required:
  "qcom,msm8974-mss-pil"
- cx-supply: (deprecated, use power domain instead)
- mss-supply:
- mx-supply: (deprecated, use power domain instead)
- pll-supply:
	Usage: required
	Value type: <phandle>
	Definition: reference to the regulators to be held on behalf of the
		    booting of the Hexagon core

For the compatible string below the following supplies are required:
  "qcom,qcs404-wcss-pil"
- cx-supply:
	Usage: required
	Value type: <phandle>
	Definition: reference to the regulators to be held on behalf of the
		    booting of the Hexagon core

For the compatible string below the following supplies are required:
  "qcom,msm8996-mss-pil"
- pll-supply:
	Usage: required
	Value type: <phandle>
	Definition: reference to the regulators to be held on behalf of the
		    booting of the Hexagon core

- power-domains:
	Usage: required
	Value type: <phandle>
	Definition: reference to power-domains that match power-domain-names

- power-domain-names:
	Usage: required
	Value type: <stringlist>
	Definition: The power-domains needed depend on the compatible string:
	qcom,ipq8074-wcss-pil:
		    no power-domain names required
	qcom,q6v5-pil:
	qcom,msm8916-mss-pil:
	qcom,msm8974-mss-pil:
	qcom,msm8996-mss-pil:
	qcom,msm8998-mss-pil:
		    must be "cx", "mx"
	qcom,sdm845-mss-pil:
		    must be "cx", "mx", "mss"

- qcom,qmp:
	Usage: optional
	Value type: <phandle>
	Definition: reference to the AOSS side-channel message RAM.

- qcom,smem-states:
	Usage: required
	Value type: <phandle>
	Definition: reference to the smem state for requesting the Hexagon to
		    shut down

- qcom,smem-state-names:
	Usage: required
	Value type: <stringlist>
	Definition: must be "stop"

- qcom,halt-regs:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: a phandle reference to a syscon representing TCSR followed
		    by the three offsets within syscon for q6, modem and nc
		    halt registers.

The Hexagon node must contain iommus property as described in ../iommu/iommu.txt
on platforms which do not have TrustZone.

= SUBNODES:
The Hexagon node must contain two subnodes, named "mba" and "mpss" representing
the memory regions used by the Hexagon firmware. Each sub-node must contain:

- memory-region:
	Usage: required
	Value type: <phandle>
	Definition: reference to the reserved-memory for the region

The Hexagon node may also have an subnode named either "smd-edge" or
"glink-edge" that describes the communication edge, channels and devices
related to the Hexagon.  See ../soc/qcom/qcom,smd.yaml and
../soc/qcom/qcom,glink.txt for details on how to describe these.

= EXAMPLE
The following example describes the resources needed to boot control the
Hexagon, as it is found on MSM8974 boards.

	remoteproc@fc880000 {
		compatible = "qcom,msm8974-mss-pil";
		reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
		reg-names = "qdsp6", "rmb";

		interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
				      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
				      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
				      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
				      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

		clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
			 <&gcc GCC_MSS_CFG_AHB_CLK>,
			 <&gcc GCC_BOOT_ROM_AHB_CLK>,
			 <&xo_board>;
		clock-names = "iface", "bus", "mem", "xo";

		resets = <&gcc GCC_MSS_RESTART>;
		reset-names = "mss_restart";

		cx-supply = <&pm8841_s2>;
		mss-supply = <&pm8841_s3>;
		mx-supply = <&pm8841_s1>;
		pll-supply = <&pm8941_l12>;

		qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;

		qcom,smem-states = <&modem_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		mba {
			memory-region = <&mba_region>;
		};

		mpss {
			memory-region = <&mpss_region>;
		};

		smd-edge {
			interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;

			qcom,ipc = <&apcs 8 12>;
			qcom,smd-edge = <0>;

			label = "modem";
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-cdsp-pil.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm QCS404 CDSP Peripheral Image Loader

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  This document defines the binding for a component that loads and boots firmware
  on the Qualcomm Technology Inc. CDSP (Compute DSP).

properties:
  compatible:
    enum:
      - qcom,qcs404-cdsp-pil

  reg:
    maxItems: 1
    description:
      The base address and size of the qdsp6ss register

  interrupts:
    items:
      - description: Watchdog interrupt
      - description: Fatal interrupt
      - description: Ready interrupt
      - description: Handover interrupt
      - description: Stop acknowledge interrupt

  interrupt-names:
    items:
      - const: wdog
      - const: fatal
      - const: ready
      - const: handover
      - const: stop-ack

  clocks:
    items:
      - description: XO clock
      - description: SWAY clock
      - description: TBU clock
      - description: BIMC clock
      - description: AHB AON clock
      - description: Q6SS SLAVE clock
      - description: Q6SS MASTER clock
      - description: Q6 AXIM clock

  clock-names:
    items:
      - const: xo
      - const: sway
      - const: tbu
      - const: bimc
      - const: ahb_aon
      - const: q6ss_slave
      - const: q6ss_master
      - const: q6_axim

  power-domains:
    items:
      - description: CX power domain

  resets:
    items:
      - description: AOSS restart

  reset-names:
    items:
      - const: restart

  memory-region:
    maxItems: 1
    description: Reference to the reserved-memory for the Hexagon core

  qcom,halt-regs:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description:
      Phandle reference to a syscon representing TCSR followed by the
      three offsets within syscon for q6, modem and nc halt registers.

  qcom,smem-states:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: States used by the AP to signal the Hexagon core
    items:
      - description: Stop the modem

  qcom,smem-state-names:
    description: The names of the state bits used for SMP2P output
    items:
      - const: stop

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - power-domains
  - resets
  - reset-names
  - qcom,halt-regs
  - memory-region
  - qcom,smem-states
  - qcom,smem-state-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
    remoteproc@b00000 {
        compatible = "qcom,qcs404-cdsp-pil";
        reg = <0x00b00000 0x4040>;

        interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
                              <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
                              <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
                              <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
                              <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
        interrupt-names = "wdog", "fatal", "ready",
                          "handover", "stop-ack";

        clocks = <&xo_board>,
                 <&gcc GCC_CDSP_CFG_AHB_CLK>,
                 <&gcc GCC_CDSP_TBU_CLK>,
                 <&gcc GCC_BIMC_CDSP_CLK>,
                 <&turingcc TURING_WRAPPER_AON_CLK>,
                 <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
                 <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
                 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
        clock-names = "xo",
                      "sway",
                      "tbu",
                      "bimc",
                      "ahb_aon",
                      "q6ss_slave",
                      "q6ss_master",
                      "q6_axim";

        power-domains = <&rpmhpd SDM845_CX>;

        resets = <&gcc GCC_CDSP_RESTART>;
        reset-names = "restart";

        qcom,halt-regs = <&tcsr 0x19004>;

        memory-region = <&cdsp_fw_mem>;

        qcom,smem-states = <&cdsp_smp2p_out 0>;
        qcom,smem-state-names = "stop";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-mss-pil.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC7180 MSS Peripheral Image Loader

maintainers:
  - Sibi Sankar <quic_sibis@quicinc.com>

description:
  This document describes the hardware for a component that loads and boots firmware
  on the Qualcomm Technology Inc. SC7180 Modem Hexagon Core.

properties:
  compatible:
    enum:
      - qcom,sc7180-mss-pil

  reg:
    items:
      - description: MSS QDSP6 registers
      - description: RMB registers

  reg-names:
    items:
      - const: qdsp6
      - const: rmb

  iommus:
    items:
      - description: MSA Stream 1
      - description: MSA Stream 2

  interrupts:
    items:
      - description: Watchdog interrupt
      - description: Fatal interrupt
      - description: Ready interrupt
      - description: Handover interrupt
      - description: Stop acknowledge interrupt
      - description: Shutdown acknowledge interrupt

  interrupt-names:
    items:
      - const: wdog
      - const: fatal
      - const: ready
      - const: handover
      - const: stop-ack
      - const: shutdown-ack

  clocks:
    items:
      - description: GCC MSS IFACE clock
      - description: GCC MSS BUS clock
      - description: GCC MSS NAV clock
      - description: GCC MSS SNOC_AXI clock
      - description: GCC MSS MFAB_AXIS clock
      - description: RPMH XO clock

  clock-names:
    items:
      - const: iface
      - const: bus
      - const: nav
      - const: snoc_axi
      - const: mnoc_axi
      - const: xo

  power-domains:
    items:
      - description: CX power domain
      - description: MX power domain
      - description: MSS power domain

  power-domain-names:
    items:
      - const: cx
      - const: mx
      - const: mss

  resets:
    items:
      - description: AOSS restart
      - description: PDC reset

  reset-names:
    items:
      - const: mss_restart
      - const: pdc_reset

  memory-region:
    items:
      - description: MBA reserved region
      - description: modem reserved region

  firmware-name:
    $ref: /schemas/types.yaml#/definitions/string-array
    items:
      - description: Name of MBA firmware
      - description: Name of modem firmware

  qcom,halt-regs:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description:
      Halt registers are used to halt transactions of various sub-components
      within MSS.
    items:
      - items:
          - description: phandle to TCSR_MUTEX registers
          - description: offset to the Q6 halt register
          - description: offset to the modem halt register
          - description: offset to the nc halt register

  qcom,spare-regs:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description:
      Spare registers are multipurpose registers used for errata
      handling.
    items:
      - items:
          - description: phandle to TCSR_MUTEX registers
          - description: offset to the conn_box_spare0 register

  qcom,qmp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: Reference to the AOSS side-channel message RAM.

  qcom,smem-states:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: States used by the AP to signal the Hexagon core
    items:
      - description: Stop the modem

  qcom,smem-state-names:
    description: The names of the state bits used for SMP2P output
    const: stop

  glink-edge:
    $ref: qcom,glink-edge.yaml#
    unevaluatedProperties: false
    description:
      Qualcomm G-Link subnode which represents communication edge, channels
      and devices related to the DSP.

    properties:
      interrupts:
        items:
          - description: IRQ from MSS to GLINK

      mboxes:
        items:
          - description: Mailbox for communication between APPS and MSS

      label:
        const: modem

      apr: false
      fastrpc: false

required:
  - compatible
  - reg
  - reg-names
  - iommus
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - power-domains
  - power-domain-names
  - resets
  - reset-names
  - qcom,halt-regs
  - qcom,spare-regs
  - memory-region
  - qcom,qmp
  - qcom,smem-states
  - qcom,smem-state-names
  - glink-edge

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    #include <dt-bindings/reset/qcom,sdm845-aoss.h>
    #include <dt-bindings/reset/qcom,sdm845-pdc.h>

    remoteproc_mpss: remoteproc@4080000 {
        compatible = "qcom,sc7180-mss-pil";
        reg = <0x04080000 0x10000>, <0x04180000 0x48>;
        reg-names = "qdsp6", "rmb";

        iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>;

        interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
                              <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
                              <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
                              <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
                              <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
                              <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;

        interrupt-names = "wdog", "fatal", "ready", "handover",
                          "stop-ack", "shutdown-ack";

        clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
                 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
                 <&gcc GCC_MSS_NAV_AXI_CLK>,
                 <&gcc GCC_MSS_SNOC_AXI_CLK>,
                 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
                 <&rpmhcc RPMH_CXO_CLK>;
        clock-names = "iface", "bus", "nav", "snoc_axi",
                      "mnoc_axi", "xo";

        power-domains = <&rpmhpd SC7180_CX>,
                        <&rpmhpd SC7180_MX>,
                        <&rpmhpd SC7180_MSS>;
        power-domain-names = "cx", "mx", "mss";

        memory-region = <&mba_mem>, <&mpss_mem>;

        qcom,qmp = <&aoss_qmp>;

        qcom,smem-states = <&modem_smp2p_out 0>;
        qcom,smem-state-names = "stop";

        resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
                 <&pdc_reset PDC_MODEM_SYNC_RESET>;
        reset-names = "mss_restart", "pdc_reset";

        qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
        qcom,spare-regs = <&tcsr_regs 0xb3e4>;

        glink-edge {
            interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
            mboxes = <&apss_shared 12>;
            qcom,remote-pid = <1>;
            label = "modem";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-mss-pil.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC7280 MSS Peripheral Image Loader

maintainers:
  - Sibi Sankar <quic_sibis@quicinc.com>

description:
  This document describes the hardware for a component that loads and boots firmware
  on the Qualcomm Technology Inc. SC7280 Modem Hexagon Core.

properties:
  compatible:
    enum:
      - qcom,sc7280-mss-pil

  reg:
    items:
      - description: MSS QDSP6 registers
      - description: RMB registers

  reg-names:
    items:
      - const: qdsp6
      - const: rmb

  iommus:
    items:
      - description: MSA Stream 1
      - description: MSA Stream 2

  interconnects:
    items:
      - description: Path leading to system memory

  interrupts:
    items:
      - description: Watchdog interrupt
      - description: Fatal interrupt
      - description: Ready interrupt
      - description: Handover interrupt
      - description: Stop acknowledge interrupt
      - description: Shutdown acknowledge interrupt

  interrupt-names:
    items:
      - const: wdog
      - const: fatal
      - const: ready
      - const: handover
      - const: stop-ack
      - const: shutdown-ack

  clocks:
    items:
      - description: GCC MSS IFACE clock
      - description: GCC MSS OFFLINE clock
      - description: GCC MSS SNOC_AXI clock
      - description: RPMH PKA clock
      - description: RPMH XO clock

  clock-names:
    items:
      - const: iface
      - const: offline
      - const: snoc_axi
      - const: pka
      - const: xo

  power-domains:
    items:
      - description: CX power domain
      - description: MSS power domain

  power-domain-names:
    items:
      - const: cx
      - const: mss

  resets:
    items:
      - description: AOSS restart
      - description: PDC reset

  reset-names:
    items:
      - const: mss_restart
      - const: pdc_reset

  memory-region:
    items:
      - description: MBA reserved region
      - description: modem reserved region

  firmware-name:
    $ref: /schemas/types.yaml#/definitions/string-array
    items:
      - description: Name of MBA firmware
      - description: Name of modem firmware

  qcom,halt-regs:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description:
      Halt registers are used to halt transactions of various sub-components
      within MSS.
    items:
      - items:
          - description: phandle to TCSR_MUTEX registers
          - description: offset to the Q6 halt register
          - description: offset to the modem halt register
          - description: offset to the nc halt register
          - description: offset to the vq6 halt register

  qcom,ext-regs:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: EXT registers are used for various power related functionality
    items:
      - items:
          - description: phandle to TCSR_REG registers
          - description: offset to the force_clk_en register
          - description: offset to the rscc_disable register
      - items:
          - description: phandle to TCSR_MUTEX registers
          - description: offset to the axim1_clk_off register
          - description: offset to the crypto_clk_off register

  qcom,qaccept-regs:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: QACCEPT registers are used to bring up/down Q-channels
    items:
      - items:
          - description: phandle to TCSR_MUTEX registers
          - description: offset to the mdm qaccept register
          - description: offset to the cx qaccept register
          - description: offset to the axi qaccept register

  qcom,qmp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: Reference to the AOSS side-channel message RAM.

  qcom,smem-states:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: States used by the AP to signal the Hexagon core
    items:
      - description: Stop the modem

  qcom,smem-state-names:
    description: The names of the state bits used for SMP2P output
    const: stop

  glink-edge:
    $ref: qcom,glink-edge.yaml#
    unevaluatedProperties: false
    description:
      Qualcomm G-Link subnode which represents communication edge, channels
      and devices related to the DSP.

    properties:
      interrupts:
        items:
          - description: IRQ from MSS to GLINK

      mboxes:
        items:
          - description: Mailbox for communication between APPS and MSS

      label:
        const: modem

      apr: false
      fastrpc: false

required:
  - compatible
  - reg
  - reg-names
  - iommus
  - interconnects
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - power-domains
  - power-domain-names
  - resets
  - reset-names
  - qcom,halt-regs
  - qcom,ext-regs
  - qcom,qaccept-regs
  - memory-region
  - qcom,qmp
  - qcom,smem-states
  - qcom,smem-state-names
  - glink-edge

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/interconnect/qcom,sc7280.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/mailbox/qcom-ipcc.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    #include <dt-bindings/reset/qcom,sdm845-aoss.h>
    #include <dt-bindings/reset/qcom,sdm845-pdc.h>

    remoteproc_mpss: remoteproc@4080000 {
        compatible = "qcom,sc7280-mss-pil";
        reg = <0x04080000 0x10000>, <0x04180000 0x48>;
        reg-names = "qdsp6", "rmb";

        iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;

        interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;

        interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
                              <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
                              <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
                              <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
                              <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
                              <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;

        interrupt-names = "wdog", "fatal", "ready", "handover",
                          "stop-ack", "shutdown-ack";

        clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
                 <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
                 <&gcc GCC_MSS_SNOC_AXI_CLK>,
                 <&rpmhcc RPMH_PKA_CLK>,
                 <&rpmhcc RPMH_CXO_CLK>;
        clock-names = "iface", "offline", "snoc_axi", "pka", "xo";

        power-domains = <&rpmhpd SC7280_CX>,
                        <&rpmhpd SC7280_MSS>;
        power-domain-names = "cx", "mss";

        memory-region = <&mba_mem>, <&mpss_mem>;

        qcom,qmp = <&aoss_qmp>;

        qcom,smem-states = <&modem_smp2p_out 0>;
        qcom,smem-state-names = "stop";

        resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
                 <&pdc_reset PDC_MODEM_SYNC_RESET>;
        reset-names = "mss_restart", "pdc_reset";

        qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
        qcom,ext-regs = <&tcsr 0x10000 0x10004>, <&tcsr_mutex 0x26004 0x26008>;
        qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;

        glink-edge {
            interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
                                   IPCC_MPROC_SIGNAL_GLINK_QMP
                                   IRQ_TYPE_EDGE_RISING>;
            mboxes = <&ipcc IPCC_CLIENT_MPSS
                      IPCC_MPROC_SIGNAL_GLINK_QMP>;
            label = "modem";
            qcom,remote-pid = <1>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC7280 WPSS Peripheral Image Loader

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  This document defines the binding for a component that loads and boots firmware
  on the Qualcomm Technology Inc. WPSS.

properties:
  compatible:
    enum:
      - qcom,sc7280-wpss-pil

  reg:
    maxItems: 1
    description:
      The base address and size of the qdsp6ss register

  interrupts:
    items:
      - description: Watchdog interrupt
      - description: Fatal interrupt
      - description: Ready interrupt
      - description: Handover interrupt
      - description: Stop acknowledge interrupt
      - description: Shutdown acknowledge interrupt

  interrupt-names:
    items:
      - const: wdog
      - const: fatal
      - const: ready
      - const: handover
      - const: stop-ack
      - const: shutdown-ack

  clocks:
    items:
      - description: GCC WPSS AHB BDG Master clock
      - description: GCC WPSS AHB clock
      - description: GCC WPSS RSCP clock
      - description: XO clock

  clock-names:
    items:
      - const: ahb_bdg
      - const: ahb
      - const: rscp
      - const: xo

  power-domains:
    items:
      - description: CX power domain
      - description: MX power domain

  power-domain-names:
    items:
      - const: cx
      - const: mx

  resets:
    items:
      - description: AOSS restart
      - description: PDC SYNC

  reset-names:
    items:
      - const: restart
      - const: pdc_sync

  memory-region:
    maxItems: 1
    description: Reference to the reserved-memory for the Hexagon core

  firmware-name:
    $ref: /schemas/types.yaml#/definitions/string
    description:
      The name of the firmware which should be loaded for this remote
      processor.

  qcom,halt-regs:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description:
      Phandle reference to a syscon representing TCSR followed by the
      three offsets within syscon for q6, modem and nc halt registers.

  qcom,qmp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: Reference to the AOSS side-channel message RAM.

  qcom,smem-states:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: States used by the AP to signal the Hexagon core
    items:
      - description: Stop the modem

  qcom,smem-state-names:
    description: The names of the state bits used for SMP2P output
    const: stop

  glink-edge:
    $ref: qcom,glink-edge.yaml#
    unevaluatedProperties: false
    description:
      Qualcomm G-Link subnode which represents communication edge, channels
      and devices related to the ADSP.

    properties:
      interrupts:
        items:
          - description: IRQ from WPSS to GLINK

      mboxes:
        items:
          - description: Mailbox for communication between APPS and WPSS

      label:
        items:
          - const: wpss

      apr: false
      fastrpc: false

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - power-domains
  - power-domain-names
  - resets
  - reset-names
  - qcom,halt-regs
  - memory-region
  - qcom,qmp
  - qcom,smem-states
  - qcom,smem-state-names
  - glink-edge

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    #include <dt-bindings/reset/qcom,sdm845-aoss.h>
    #include <dt-bindings/reset/qcom,sdm845-pdc.h>
    #include <dt-bindings/mailbox/qcom-ipcc.h>
    remoteproc@8a00000 {
        compatible = "qcom,sc7280-wpss-pil";
        reg = <0x08a00000 0x10000>;

        interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
                              <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
                              <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
                              <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
                              <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
                              <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
        interrupt-names = "wdog", "fatal", "ready", "handover",
                          "stop-ack", "shutdown-ack";

        clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
                 <&gcc GCC_WPSS_AHB_CLK>,
                 <&gcc GCC_WPSS_RSCP_CLK>,
                 <&rpmhcc RPMH_CXO_CLK>;
        clock-names = "ahb_bdg", "ahb",
                      "rscp", "xo";

        power-domains = <&rpmhpd SC7280_CX>,
                        <&rpmhpd SC7280_MX>;
        power-domain-names = "cx", "mx";

        memory-region = <&wpss_mem>;

        qcom,qmp = <&aoss_qmp>;

        qcom,smem-states = <&wpss_smp2p_out 0>;
        qcom,smem-state-names = "stop";

        resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
                 <&pdc_reset PDC_WPSS_SYNC_RESET>;
        reset-names = "restart", "pdc_sync";

        qcom,halt-regs = <&tcsr_mutex 0x37000>;

        glink-edge {
            interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
                                         IPCC_MPROC_SIGNAL_GLINK_QMP
                                         IRQ_TYPE_EDGE_RISING>;
            mboxes = <&ipcc IPCC_CLIENT_WPSS
                            IPCC_MPROC_SIGNAL_GLINK_QMP>;

            label = "wpss";
            qcom,remote-pid = <13>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,sdm845-adsp-pil.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SDM845 ADSP Peripheral Image Loader

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  This document defines the binding for a component that loads and boots firmware
  on the Qualcomm Technology Inc. ADSP.

properties:
  compatible:
    enum:
      - qcom,sdm845-adsp-pil

  reg:
    maxItems: 1
    description:
      The base address and size of the qdsp6ss register

  interrupts:
    items:
      - description: Watchdog interrupt
      - description: Fatal interrupt
      - description: Ready interrupt
      - description: Handover interrupt
      - description: Stop acknowledge interrupt

  interrupt-names:
    items:
      - const: wdog
      - const: fatal
      - const: ready
      - const: handover
      - const: stop-ack

  clocks:
    items:
      - description: XO clock
      - description: SWAY clock
      - description: LPASS AHBS AON clock
      - description: LPASS AHBM AON clock
      - description: QDSP XO clock
      - description: Q6SP6SS SLEEP clock
      - description: Q6SP6SS CORE clock

  clock-names:
    items:
      - const: xo
      - const: sway_cbcr
      - const: lpass_ahbs_aon_cbcr
      - const: lpass_ahbm_aon_cbcr
      - const: qdsp6ss_xo
      - const: qdsp6ss_sleep
      - const: qdsp6ss_core

  power-domains:
    items:
      - description: CX power domain

  resets:
    items:
      - description: PDC AUDIO SYNC RESET
      - description: CC LPASS restart

  reset-names:
    items:
      - const: pdc_sync
      - const: cc_lpass

  memory-region:
    maxItems: 1
    description: Reference to the reserved-memory for the Hexagon core

  qcom,halt-regs:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description:
      Phandle reference to a syscon representing TCSR followed by the
      three offsets within syscon for q6, modem and nc halt registers.

  qcom,smem-states:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: States used by the AP to signal the Hexagon core
    items:
      - description: Stop the modem

  qcom,smem-state-names:
    description: The names of the state bits used for SMP2P output
    items:
      - const: stop

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - power-domains
  - resets
  - reset-names
  - qcom,halt-regs
  - memory-region
  - qcom,smem-states
  - qcom,smem-state-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/clock/qcom,lpass-sdm845.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    #include <dt-bindings/reset/qcom,sdm845-pdc.h>
    #include <dt-bindings/reset/qcom,sdm845-aoss.h>
    remoteproc@17300000 {
        compatible = "qcom,sdm845-adsp-pil";
        reg = <0x17300000 0x40c>;

        interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
                <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
                <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
                <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
                <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
        interrupt-names = "wdog", "fatal", "ready",
                "handover", "stop-ack";

        clocks = <&rpmhcc RPMH_CXO_CLK>,
                 <&gcc GCC_LPASS_SWAY_CLK>,
                 <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
                 <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
                 <&lpasscc LPASS_QDSP6SS_XO_CLK>,
                 <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
                 <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
        clock-names = "xo", "sway_cbcr",
                "lpass_ahbs_aon_cbcr",
                "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
                "qdsp6ss_sleep", "qdsp6ss_core";

        power-domains = <&rpmhpd SDM845_CX>;

        resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
                 <&aoss_reset AOSS_CC_LPASS_RESTART>;
        reset-names = "pdc_sync", "cc_lpass";

        qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;

        memory-region = <&pil_adsp_mem>;

        qcom,smem-states = <&adsp_smp2p_out 0>;
        qcom,smem-state-names = "stop";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,smd-edge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SMD Edge communication channel nodes

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  Qualcomm SMD subnode represents a remote subsystem or a remote processor of
  some sort - or in SMD language an "edge". The name of the edges are not
  important.

  In turn, subnodes of the "edges" represent devices tied to SMD channels on
  that "edge". The names of the devices are not important. The properties of
  these nodes are defined by the individual bindings for the SMD devices.
  See also Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml

properties:
  $nodename:
    const: "smd-edge"

  apr:
    $ref: /schemas/soc/qcom/qcom,apr.yaml#
    required:
      - qcom,smd-channels
    description:
      Qualcomm APR/GPR (Asynchronous/Generic Packet Router)

  fastrpc:
    $ref: /schemas/misc/qcom,fastrpc.yaml#
    required:
      - qcom,smd-channels
    description:
      Qualcomm FastRPC

  interrupts:
    maxItems: 1

  label:
    description:
      Name of the edge, used for debugging and identification purposes. The
      node name will be used if this is not present.

  mboxes:
    maxItems: 1
    description:
      Reference to the mailbox representing the outgoing doorbell in APCS for
      this client.

  qcom,ipc:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to a syscon node representing the APCS registers
          - description: u32 representing offset to the register within the syscon
          - description: u32 representing the ipc bit within the register
    description:
      Three entries specifying the outgoing ipc bit used for signaling the
      remote processor.

  qcom,smd-edge:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The identifier of the remote processor in the smd channel allocation
      table.

  qcom,remote-pid:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The identifier for the remote processor as known by the rest of the
      system.

  rpm-requests:
    $ref: /schemas/soc/qcom/qcom,smd-rpm.yaml#
    required:
      - qcom,smd-channels
    description:
      Qualcomm Resource Power Manager (RPM) over SMD.

  wcnss:
    $ref: /schemas/soc/qcom/qcom,wcnss.yaml
    required:
      - qcom,smd-channels
    description:
      Qualcomm WCNSS for Bluetooth, WiFi and FM radio.

required:
  - interrupts
  - qcom,smd-edge

oneOf:
  - required:
      - mboxes
  - required:
      - qcom,ipc

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/mailbox/qcom-ipcc.h>

    remoteproc {
        // ...

        smd-edge {
            interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;

            qcom,ipc = <&apcs 8 8>;
            qcom,smd-edge = <1>;
        };
    };


code:
Qualcomm WCNSS Peripheral Image Loader

This document defines the binding for a component that loads and boots firmware
on the Qualcomm WCNSS core.

- compatible:
	Usage: required
	Value type: <string>
	Definition: must be one of:
		    "qcom,riva-pil",
		    "qcom,pronto-v1-pil",
		    "qcom,pronto-v2-pil"

- reg:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: must specify the base address and size of the CCU, DXE and
		    PMU register blocks

- reg-names:
	Usage: required
	Value type: <stringlist>
	Definition: must be "ccu", "dxe", "pmu"

- interrupts-extended:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: must list the watchdog and fatal IRQs and may specify the
		    ready, handover and stop-ack IRQs

- interrupt-names:
	Usage: required
	Value type: <stringlist>
	Definition: should be "wdog", "fatal", optionally followed by "ready",
		    "handover", "stop-ack"

- firmware-name:
	Usage: optional
	Value type: <string>
	Definition: must list the relative firmware image path for the
		    WCNSS core. Defaults to "wcnss.mdt".

- vddmx-supply: (deprecated for qcom,pronto-v1/2-pil)
- vddcx-supply: (deprecated for qcom,pronto-v1/2-pil)
- vddpx-supply:
	Usage: required
	Value type: <phandle>
	Definition: reference to the regulators to be held on behalf of the
		    booting of the WCNSS core

- power-domains:
	Usage: required (for qcom,pronto-v1/2-pil)
	Value type: <phandle>
	Definition: reference to the power domains to be held on behalf of the
		    booting of the WCNSS core

- power-domain-names:
	Usage: required (for qcom,pronto-v1/2-pil)
	Value type: <stringlist>
	Definition: must be "cx", "mx"

- qcom,smem-states:
	Usage: optional
	Value type: <prop-encoded-array>
	Definition: reference to the SMEM state used to indicate to WCNSS that
		    it should shut down

- qcom,smem-state-names:
	Usage: optional
	Value type: <stringlist>
	Definition: should be "stop"

- memory-region:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: reference to reserved-memory node for the remote processor
		    see ../reserved-memory/reserved-memory.txt

= SUBNODES
A required subnode of the WCNSS PIL is used to describe the attached rf module
and its resource dependencies. It is described by the following properties:

- compatible:
	Usage: required
	Value type: <string>
	Definition: must be one of:
		    "qcom,wcn3620",
		    "qcom,wcn3660",
		    "qcom,wcn3660b",
		    "qcom,wcn3680"

- clocks:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: should specify the xo clock and optionally the rf clock

- clock-names:
	Usage: required
	Value type: <stringlist>
	Definition: should be "xo", optionally followed by "rf"

- vddxo-supply:
- vddrfa-supply:
- vddpa-supply:
- vdddig-supply:
	Usage: required
	Value type: <phandle>
	Definition: reference to the regulators to be held on behalf of the
		    booting of the WCNSS core

The wcnss node can also have an subnode named "smd-edge" that describes the SMD
edge, channels and devices related to the WCNSS.
See ../soc/qcom/qcom,smd.yaml for details on how to describe the SMD edge.

= EXAMPLE
The following example describes the resources needed to boot control the WCNSS,
with attached WCN3680, as it is commonly found on MSM8974 boards.

pronto@fb204000 {
	compatible = "qcom,pronto-v2-pil";
	reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
	reg-names = "ccu", "dxe", "pmu";

	interrupts-extended = <&intc 0 149 1>,
			      <&wcnss_smp2p_slave 0 0>,
			      <&wcnss_smp2p_slave 1 0>,
			      <&wcnss_smp2p_slave 2 0>,
			      <&wcnss_smp2p_slave 3 0>;
	interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

	power-domains = <&rpmpd MSM8974_VDDCX>, <&rpmpd MSM8974_VDDMX>;
	power-domain-names = "cx", "mx";

	vddpx-supply = <&pm8941_s3>;

	qcom,smem-states = <&wcnss_smp2p_out 0>;
	qcom,smem-state-names = "stop";

	memory-region = <&wcnss_region>;

	pinctrl-names = "default";
	pinctrl-0 = <&wcnss_pin_a>;

	iris {
		compatible = "qcom,wcn3680";

		clocks = <&rpmcc RPM_CXO_CLK_SRC>, <&rpmcc RPM_CXO_A2>;
		clock-names = "xo", "rf";

		vddxo-supply = <&pm8941_l6>;
		vddrfa-supply = <&pm8941_l11>;
		vddpa-supply = <&pm8941_l19>;
		vdddig-supply = <&pm8941_s3>;
	};

	smd-edge {
		interrupts = <0 142 1>;

		qcom,ipc = <&apcs 8 17>;
		qcom,smd-edge = <6>;
		qcom,remote-pid = <4>;

		label = "pronto";

		wcnss {
			compatible = "qcom,wcnss";
			qcom,smd-channels = "WCNSS_CTRL";

			qcom,mmio = <&pronto>;

			bt {
				compatible = "qcom,wcnss-bt";
			};
		};
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/remoteproc/renesas,rcar-rproc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Renesas R-Car remote processor controller bindings

maintainers:
  - Julien Massot <julien.massot@iot.bzh>

description: |
  This document defines the bindings for the remoteproc component that loads and
  boots firmwares on the Renesas R-Car family chipset.
  R-Car gen3 family may have a realtime processor, this processor shares peripheral
  and RAM with the host processor with the same address map.

properties:
  compatible:
    const: renesas,rcar-cr7

  resets:
    maxItems: 1

  power-domains:
    maxItems: 1

  memory-region:
    description:
      List of phandles to the reserved memory regions associated with the
      remoteproc device. This is variable and describes the memories shared with
      the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
      vrings, ...).
      (see ../reserved-memory/reserved-memory.yaml)

required:
  - compatible
  - resets
  - memory-region
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/power/r8a7795-sysc.h>
    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;

        cr7_ram: cr7_ram@40040000 {
            no-map;
            reg = <0x0 0x40040000 0x0 0x1fc0000>;
        };
    };

    cr7_rproc: cr7 {
        compatible = "renesas,rcar-cr7";
        memory-region = <&cr7_ram>;
        power-domains = <&sysc R8A7795_PD_CR7>;
        resets = <&cpg 222>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: STMicroelectronics STM32 remote processor controller bindings

description:
  This document defines the binding for the remoteproc component that loads and
  boots firmwares on the ST32MP family chipset.

maintainers:
  - Fabien Dessenne <fabien.dessenne@foss.st.com>
  - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>

properties:
  compatible:
    const: st,stm32mp1-m4

  reg:
    description:
      Address ranges of the RETRAM and MCU SRAM memories used by the remote
      processor.
    maxItems: 3

  resets:
    maxItems: 1

  st,syscfg-holdboot:
    description: remote processor reset hold boot
    $ref: "/schemas/types.yaml#/definitions/phandle-array"
    items:
      - items:
          - description: Phandle of syscon block
          - description: The offset of the hold boot setting register
          - description: The field mask of the hold boot

  st,syscfg-tz:
    description:
      Reference to the system configuration which holds the RCC trust zone mode
    $ref: "/schemas/types.yaml#/definitions/phandle-array"
    items:
      - items:
          - description: Phandle of syscon block
          - description: The offset of the trust zone setting register
          - description: The field mask of the trust zone state

  interrupts:
    description: Should contain the WWDG1 watchdog reset interrupt
    maxItems: 1

  wakeup-source: true

  mboxes:
    description:
      This property is required only if the rpmsg/virtio functionality is used.
    items:
      - description: |
          A channel (a) used to communicate through virtqueues with the
          remote proc.
          Bi-directional channel:
            - from local to remote = send message
            - from remote to local = send message ack
      - description: |
          A channel (b) working the opposite direction of channel (a)
      - description: |
          A channel (c) used by the local proc to notify the remote proc that it
          is about to be shut down.
          Unidirectional channel:
            - from local to remote, where ACK from the remote means that it is
              ready for shutdown
      - description: |
          A channel (d) used by the local proc to notify the remote proc that it
          has to stop interprocessor communnication.
          Unidirectional channel:
            - from local to remote, where ACK from the remote means that communnication
              as been stopped on the remote side.
    minItems: 1

  mbox-names:
    items:
      - const: vq0
      - const: vq1
      - const: shutdown
      - const: detach
    minItems: 1

  memory-region:
    description:
      List of phandles to the reserved memory regions associated with the
      remoteproc device. This is variable and describes the memories shared with
      the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
      vrings, ...).
      (see ../reserved-memory/reserved-memory.txt)

  st,syscfg-pdds:
    $ref: "/schemas/types.yaml#/definitions/phandle-array"
    description: |
      Reference to the system configuration which holds the remote
    items:
      - items:
          - description: Phandle of syscon block
          - description: The offset of the power setting register
          - description: The field mask of the PDDS selection

  st,syscfg-m4-state:
    $ref: "/schemas/types.yaml#/definitions/phandle-array"
    description: |
      Reference to the tamp register which exposes the Cortex-M4 state.
    items:
      - items:
          - description: Phandle of syscon block with the tamp register
          - description: The offset of the tamp register
          - description: The field mask of the Cortex-M4 state

  st,syscfg-rsc-tbl:
    $ref: "/schemas/types.yaml#/definitions/phandle-array"
    description: |
      Reference to the tamp register which references the Cortex-M4
      resource table address.
    items:
      - items:
          - description: Phandle of syscon block with the tamp register
          - description: The offset of the tamp register
          - description: The field mask of the Cortex-M4 resource table address

  st,auto-boot:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      If defined, when remoteproc is probed, it loads the default firmware and
      starts the remote processor.

required:
  - compatible
  - reg
  - resets
  - st,syscfg-holdboot
  - st,syscfg-tz

additionalProperties: false

examples:
  - |
    #include <dt-bindings/reset/stm32mp1-resets.h>
    m4_rproc: m4@10000000 {
      compatible = "st,stm32mp1-m4";
      reg = <0x10000000 0x40000>,
            <0x30000000 0x40000>,
            <0x38000000 0x10000>;
      resets = <&rcc MCU_R>;
      st,syscfg-holdboot = <&rcc 0x10C 0x1>;
      st,syscfg-tz = <&rcc 0x000 0x1>;
      st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
      st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
    };

...


code:
STMicroelectronics Co-Processor Bindings
----------------------------------------

This binding provides support for adjunct processors found on ST SoCs.

Co-processors can be controlled from the bootloader or the primary OS. If
the bootloader starts a co-processor, the primary OS must detect its state
and act accordingly.

Required properties:
- compatible		Should be one of:
				"st,st231-rproc"
				"st,st40-rproc"
- memory-region		Reserved memory (See: ../reserved-memory/reserved-memory.txt)
- resets		Reset lines (See: ../reset/reset.txt)
- reset-names		Must be "sw_reset" and "pwr_reset"
- clocks		Clock for co-processor (See: ../clock/clock-bindings.txt)
- clock-frequency	Clock frequency to set co-processor at if the bootloader
			hasn't already done so
- st,syscfg		System configuration register which holds the boot vector
			for the co-processor
				1st cell: Phandle to syscon block
				2nd cell: Boot vector register offset

Example:

	audio_reserved: rproc@42000000 {
		compatible = "shared-dma-pool";
		reg = <0x42000000 0x01000000>;
		no-map;
	};

	st231-audio {
		compatible	= "st,st231-rproc";
		memory-region	= <&audio_reserved>;
		resets		= <&softreset STIH407_ST231_AUD_SOFTRESET>;
		reset-names	= "sw_reset";
		clocks		= <&clk_s_c0_flexgen CLK_ST231_AUD_0>;
		clock-frequency	= <600000000>;
		st,syscfg	= <&syscfg_core 0x228>;
	};


code:
TI Davinci DSP devices
=======================

Binding status: Unstable - Subject to changes for DT representation of clocks
			   and resets

The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
is used to offload some of the processor-intensive tasks or algorithms, for
achieving various system level goals.

The processor cores in the sub-system usually contain additional sub-modules
like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
controller, a dedicated local power/sleep controller etc. The DSP processor
core used in Davinci SoCs is usually a C674x DSP CPU.

DSP Device Node:
================
Each DSP Core sub-system is represented as a single DT node.

Required properties:
--------------------
The following are the mandatory properties:

- compatible:		Should be one of the following,
			    "ti,da850-dsp" for DSPs on OMAP-L138 SoCs

- reg:			Should contain an entry for each value in 'reg-names'.
			Each entry should have the memory region's start address
			and the size of the region, the representation matching
			the parent node's '#address-cells' and '#size-cells' values.

- reg-names:		Should contain strings with the following names, each
			representing a specific internal memory region or a
			specific register space,
			     "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig_base"

- interrupts: 		Should contain the interrupt number used to receive the
			interrupts from the DSP. The value should follow the
			interrupt-specifier format as dictated by the
			'interrupt-parent' node.

- memory-region:	phandle to the reserved memory node to be associated
			with the remoteproc device. The reserved memory node
			can be a CMA memory node, and should be defined as
			per the bindings in
			Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt

Example:
--------

	/* DSP Reserved Memory node */
	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dsp_memory_region: dsp-memory@c3000000 {
			compatible = "shared-dma-pool";
			reg = <0xc3000000 0x1000000>;
			reusable;
		};
	};

	/* DSP node */
	{
		dsp: dsp@11800000 {
			compatible = "ti,da850-dsp";
			reg = <0x11800000 0x40000>,
			      <0x11e00000 0x8000>,
			      <0x11f00000 0x8000>,
			      <0x01c14044 0x4>,
			      <0x01c14174 0x8>;
			reg-names = "l2sram", "l1pram", "l1dram", "host1cfg",
				    "chipsig";
			interrupt-parent = <&intc>;
			interrupts = <28>;
			memory-region = <&dsp_memory_region>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI K3 DSP devices

maintainers:
  - Suman Anna <s-anna@ti.com>

description: |
  The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
  that are used to offload some of the processor-intensive tasks or algorithms,
  for achieving various system level goals.

  These processor sub-systems usually contain additional sub-modules like
  L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
  controller, a dedicated local power/sleep controller etc. The DSP processor
  cores in the K3 SoCs are usually either a TMS320C66x CorePac processor or a
  TMS320C71x CorePac processor.

  Each DSP Core sub-system is represented as a single DT node. Each node has a
  number of required or optional properties that enable the OS running on the
  host processor (Arm CorePac) to perform the device management of the remote
  processor and to communicate with the remote processor.

allOf:
  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#

properties:
  compatible:
    enum:
      - ti,j721e-c66-dsp
      - ti,j721e-c71-dsp
      - ti,j721s2-c71-dsp
    description:
      Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs
      Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs
      Use "ti,j721s2-c71-dsp" for C71x DSPs on K3 J721S2 SoCs

  resets:
    description: |
      Should contain the phandle to the reset controller node managing the
      local resets for this device, and a reset specifier.
    maxItems: 1

  firmware-name:
    description: |
      Should contain the name of the default firmware image
      file located on the firmware search path

  mboxes:
    description: |
      OMAP Mailbox specifier denoting the sub-mailbox, to be used for
      communication with the remote processor. This property should match
      with the sub-mailbox node used in the firmware image.
    maxItems: 1

  memory-region:
    minItems: 2
    maxItems: 8
    description: |
      phandle to the reserved memory nodes to be associated with the remoteproc
      device. There should be at least two reserved memory nodes defined. The
      reserved memory nodes should be carveout nodes, and should be defined as
      per the bindings in
      Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
    items:
      - description: region used for dynamic DMA allocations like vrings and
                     vring buffers
      - description: region reserved for firmware image sections
    additionalItems: true

# Optional properties:
# --------------------

  sram:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 1
    maxItems: 4
    items:
      maxItems: 1
    description: |
      phandles to one or more reserved on-chip SRAM regions. The regions
      should be defined as child nodes of the respective SRAM node, and
      should be defined as per the generic bindings in,
      Documentation/devicetree/bindings/sram/sram.yaml

if:
  properties:
    compatible:
      enum:
        - ti,j721e-c66-dsp
then:
  properties:
    reg:
      items:
        - description: Address and Size of the L2 SRAM internal memory region
        - description: Address and Size of the L1 PRAM internal memory region
        - description: Address and Size of the L1 DRAM internal memory region
    reg-names:
      items:
        - const: l2sram
        - const: l1pram
        - const: l1dram
else:
  if:
    properties:
      compatible:
        enum:
          - ti,j721e-c71-dsp
          - ti,j721s2-c71-dsp
  then:
    properties:
      reg:
        items:
          - description: Address and Size of the L2 SRAM internal memory region
          - description: Address and Size of the L1 DRAM internal memory region
      reg-names:
        items:
          - const: l2sram
          - const: l1dram

required:
  - compatible
  - reg
  - reg-names
  - ti,sci
  - ti,sci-dev-id
  - ti,sci-proc-ids
  - resets
  - firmware-name
  - mboxes
  - memory-region

unevaluatedProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        mailbox0_cluster3: mailbox-0 {
            #mbox-cells = <1>;
        };

        mailbox0_cluster4: mailbox-1 {
            #mbox-cells = <1>;
        };

        bus@100000 {
            compatible = "simple-bus";
            #address-cells = <2>;
            #size-cells = <2>;
            ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
                     <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
                     <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
                     <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */

            /* J721E C66_0 DSP node */
            dsp@4d80800000 {
                compatible = "ti,j721e-c66-dsp";
                reg = <0x4d 0x80800000 0x00 0x00048000>,
                      <0x4d 0x80e00000 0x00 0x00008000>,
                      <0x4d 0x80f00000 0x00 0x00008000>;
                reg-names = "l2sram", "l1pram", "l1dram";
                ti,sci = <&dmsc>;
                ti,sci-dev-id = <142>;
                ti,sci-proc-ids = <0x03 0xFF>;
                resets = <&k3_reset 142 1>;
                firmware-name = "j7-c66_0-fw";
                memory-region = <&c66_0_dma_memory_region>,
                                <&c66_0_memory_region>;
                mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
            };

            /* J721E C71_0 DSP node */
            c71_0: dsp@64800000 {
                compatible = "ti,j721e-c71-dsp";
                reg = <0x00 0x64800000 0x00 0x00080000>,
                      <0x00 0x64e00000 0x00 0x0000c000>;
                reg-names = "l2sram", "l1dram";
                ti,sci = <&dmsc>;
                ti,sci-dev-id = <15>;
                ti,sci-proc-ids = <0x30 0xFF>;
                resets = <&k3_reset 15 1>;
                firmware-name = "j7-c71_0-fw";
                memory-region = <&c71_0_dma_memory_region>,
                                <&c71_0_memory_region>;
                mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI K3 R5F processor subsystems

maintainers:
  - Suman Anna <s-anna@ti.com>

description: |
  The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
  processor subsystems/clusters (R5FSS). The dual core cluster can be used
  either in a LockStep mode providing safety/fault tolerance features or in a
  Split mode providing two individual compute cores for doubling the compute
  capacity on most SoCs. These are used together with other processors present
  on the SoC to achieve various system level goals.

  AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
  called "Single-CPU" mode, where only Core0 is used, but with ability to use
  Core1's TCMs as well.

  Each Dual-Core R5F sub-system is represented as a single DTS node
  representing the cluster, with a pair of child DT nodes representing
  the individual R5F cores. Each node has a number of required or optional
  properties that enable the OS running on the host processor to perform
  the device management of the remote processor and to communicate with the
  remote processor.

properties:
  $nodename:
    pattern: "^r5fss(@.*)?"

  compatible:
    enum:
      - ti,am654-r5fss
      - ti,j721e-r5fss
      - ti,j7200-r5fss
      - ti,am64-r5fss
      - ti,j721s2-r5fss

  power-domains:
    description: |
      Should contain a phandle to a PM domain provider node and an args
      specifier containing the R5FSS device id value.
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  ranges:
    description: |
      Standard ranges definition providing address translations for
      local R5F TCM address spaces to bus addresses.

# Optional properties:
# --------------------

  ti,cluster-mode:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Configuration Mode for the Dual R5F cores within the R5F cluster.
      Should be either a value of 1 (LockStep mode) or 0 (Split mode) on
      most SoCs (AM65x, J721E, J7200, J721s2), default is LockStep mode if
      omitted; and should be either a value of 0 (Split mode) or 2
      (Single-CPU mode) on AM64x SoCs, default is Split mode if omitted.

# R5F Processor Child Nodes:
# ==========================

patternProperties:
  "^r5f@[a-f0-9]+$":
    type: object
    description: |
      The R5F Sub-System device node should define two R5F child nodes, each
      node representing a TI instantiation of the Arm Cortex R5F core. There
      are some specific integration differences for the IP like the usage of
      a Region Address Translator (RAT) for translating the larger SoC bus
      addresses into a 32-bit address space for the processor.

      Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM)
      internal memories split between two banks - TCMA and TCMB (further
      interleaved into two banks TCMB0 and TCMB1). These memories (also called
      ATCM and BTCM) provide read/write performance on par with the core's L1
      caches. Each of the TCMs can be enabled or disabled independently and
      either of them can be configured to appear at that R5F's address 0x0.

      The cores do not use an MMU, but has a Region Address Translater
      (RAT) module that is accessible only from the R5Fs for providing
      translations between 32-bit CPU addresses into larger system bus
      addresses. Cache and memory access settings are provided through a
      Memory Protection Unit (MPU), programmable only from the R5Fs.

    $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#

    properties:
      compatible:
        enum:
          - ti,am654-r5f
          - ti,j721e-r5f
          - ti,j7200-r5f
          - ti,am64-r5f
          - ti,j721s2-r5f

      reg:
        items:
          - description: Address and Size of the ATCM internal memory region
          - description: Address and Size of the BTCM internal memory region

      reg-names:
        items:
          - const: atcm
          - const: btcm

      resets:
        description: |
          Should contain the phandle to the reset controller node managing the
          local resets for this device, and a reset specifier.
        maxItems: 1

      firmware-name:
        description: |
          Should contain the name of the default firmware image
          file located on the firmware search path

# The following properties are mandatory for R5F Core0 in both LockStep and Split
# modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for
# R5F Core1 in LockStep mode:

      mboxes:
        description: |
          OMAP Mailbox specifier denoting the sub-mailbox, to be used for
          communication with the remote processor. This property should match
          with the sub-mailbox node used in the firmware image.
        maxItems: 1

      memory-region:
        description: |
          phandle to the reserved memory nodes to be associated with the
          remoteproc device. There should be at least two reserved memory nodes
          defined. The reserved memory nodes should be carveout nodes, and
          should be defined with a "no-map" property as per the bindings in
          Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
        minItems: 2
        maxItems: 8
        items:
          - description: region used for dynamic DMA allocations like vrings and
                         vring buffers
          - description: region reserved for firmware image sections
        additionalItems: true

# Optional properties:
# --------------------
# The following properties are optional properties for each of the R5F cores:

      ti,atcm-enable:
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [0, 1]
        description: |
          R5F core configuration mode dictating if ATCM should be enabled. The
          R5F address of ATCM is dictated by ti,loczrama property. Should be
          either a value of 1 (enabled) or 0 (disabled), default is disabled
          if omitted. Recommended to enable it for maximizing TCMs.

      ti,btcm-enable:
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [0, 1]
        description: |
          R5F core configuration mode dictating if BTCM should be enabled. The
          R5F address of BTCM is dictated by ti,loczrama property. Should be
          either a value of 1 (enabled) or 0 (disabled), default is enabled if
          omitted.

      ti,loczrama:
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [0, 1]
        description: |
          R5F core configuration mode dictating which TCM should appear at
          address 0 (from core's view). Should be either a value of 1 (ATCM
          at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.

      sram:
        $ref: /schemas/types.yaml#/definitions/phandle-array
        minItems: 1
        maxItems: 4
        items:
          maxItems: 1
        description: |
          phandles to one or more reserved on-chip SRAM regions. The regions
          should be defined as child nodes of the respective SRAM node, and
          should be defined as per the generic bindings in,
          Documentation/devicetree/bindings/sram/sram.yaml

    required:
      - compatible
      - reg
      - reg-names
      - ti,sci
      - ti,sci-dev-id
      - ti,sci-proc-ids
      - resets
      - firmware-name

    unevaluatedProperties: false

if:
  properties:
    compatible:
      enum:
        - ti,am64-r5fss
then:
  properties:
    ti,cluster-mode:
      enum: [0, 2]
else:
  properties:
    ti,cluster-mode:
      enum: [0, 1]

required:
  - compatible
  - power-domains
  - "#address-cells"
  - "#size-cells"
  - ranges

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        mailbox0: mailbox-0 {
            #mbox-cells = <1>;
        };

        mailbox1: mailbox-1 {
            #mbox-cells = <1>;
        };

        bus@100000 {
            compatible = "simple-bus";
            #address-cells = <2>;
            #size-cells = <2>;
            ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
                     <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
                     <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
                     <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;

            bus@28380000 {
                compatible = "simple-bus";
                #address-cells = <2>;
                #size-cells = <2>;
                ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
                         <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
                         <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
                         <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */

                /* AM65x MCU R5FSS node */
                mcu_r5fss0: r5fss@41000000 {
                    compatible = "ti,am654-r5fss";
                    power-domains = <&k3_pds 129>;
                    ti,cluster-mode = <1>;
                    #address-cells = <1>;
                    #size-cells = <1>;
                    ranges = <0x41000000 0x00 0x41000000 0x20000>,
                             <0x41400000 0x00 0x41400000 0x20000>;

                    mcu_r5f0: r5f@41000000 {
                        compatible = "ti,am654-r5f";
                        reg = <0x41000000 0x00008000>,
                              <0x41010000 0x00008000>;
                        reg-names = "atcm", "btcm";
                        ti,sci = <&dmsc>;
                        ti,sci-dev-id = <159>;
                        ti,sci-proc-ids = <0x01 0xFF>;
                        resets = <&k3_reset 159 1>;
                        firmware-name = "am65x-mcu-r5f0_0-fw";
                        ti,atcm-enable = <1>;
                        ti,btcm-enable = <1>;
                        ti,loczrama = <1>;
                        mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>;
                        memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
                                        <&mcu_r5fss0_core0_memory_region>;
                        sram = <&mcu_r5fss0_core0_sram>;
                    };

                    mcu_r5f1: r5f@41400000 {
                        compatible = "ti,am654-r5f";
                        reg = <0x41400000 0x00008000>,
                              <0x41410000 0x00008000>;
                        reg-names = "atcm", "btcm";
                        ti,sci = <&dmsc>;
                        ti,sci-dev-id = <245>;
                        ti,sci-proc-ids = <0x02 0xFF>;
                        resets = <&k3_reset 245 1>;
                        firmware-name = "am65x-mcu-r5f0_1-fw";
                        ti,atcm-enable = <1>;
                        ti,btcm-enable = <1>;
                        ti,loczrama = <1>;
                        mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>;
                    };
                };
            };
        };
    };


code:
TI Keystone DSP devices
=======================

The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core
sub-systems that are used to offload some of the processor-intensive tasks or
algorithms, for achieving various system level goals.

These processor sub-systems usually contain additional sub-modules like L1
and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller,
a dedicated local power/sleep controller etc. The DSP processor core in
Keystone 2 SoCs is usually a TMS320C66x CorePac processor.

DSP Device Node:
================
Each DSP Core sub-system is represented as a single DT node, and should also
have an alias with the stem 'rproc' defined. Each node has a number of required
or optional properties that enable the OS running on the host processor (ARM
CorePac) to perform the device management of the remote processor and to
communicate with the remote processor.

Required properties:
--------------------
The following are the mandatory properties:

- compatible:		Should be one of the following,
			    "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
			    "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
			    "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
			    "ti,k2g-dsp" for DSPs on Keystone 2 66AK2G SoCs

- reg:			Should contain an entry for each value in 'reg-names'.
			Each entry should have the memory region's start address
			and the size of the region, the representation matching
			the parent node's '#address-cells' and '#size-cells' values.

- reg-names:		Should contain strings with the following names, each
			representing a specific internal memory region, and
			should be defined in this order,
			     "l2sram", "l1pram", "l1dram"

- ti,syscon-dev:	Should be a pair of the phandle to the Keystone Device
			State Control node, and the register offset of the DSP
			boot address register within that node's address space.

- resets:		Should contain the phandle to the reset controller node
			managing the resets for this device, and a reset
			specifier. Please refer to either of the following reset
			bindings for the reset argument specifier as per SoC,
			Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
			    for 66AK2HK/66AK2L/66AK2E SoCs or,
			Documentation/devicetree/bindings/reset/ti,sci-reset.yaml
			    for 66AK2G SoCs

- interrupts: 		Should contain an entry for each value in 'interrupt-names'.
			Each entry should have the interrupt source number used by
			the remote processor to the host processor. The values should
			follow the interrupt-specifier format as dictated by the
			'interrupt-parent' node. The purpose of each is as per the
			description in the 'interrupt-names' property.

- interrupt-names:	Should contain strings with the following names, each
			representing a specific interrupt,
			    "vring" - interrupt for virtio based IPC
			    "exception" - interrupt for exception notification

- kick-gpios: 		Should specify the gpio device needed for the virtio IPC
			stack. This will be used to interrupt the remote processor.
			The gpio device to be used is as per the bindings in,
			Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt

SoC-specific Required properties:
---------------------------------
The following are mandatory properties for Keystone 2 66AK2HK, 66AK2L and 66AK2E
SoCs only:

- clocks: 		Should contain the device's input clock, and should be
			defined as per the bindings in,
			Documentation/devicetree/bindings/clock/keystone-gate.txt

The following are mandatory properties for Keystone 2 66AK2G SoCs only:

- power-domains:	Should contain a phandle to a PM domain provider node
			and an args specifier containing the DSP device id
			value. This property is as per the binding,
			Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml

Optional properties:
--------------------

- memory-region:	phandle to the reserved memory node to be associated
			with the remoteproc device. The reserved memory node
			can be a CMA memory node, and should be defined as
			per the bindings in
			Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt

Examples:
---------

1.
	/* 66AK2H/K DSP aliases */
	aliases {
		rproc0 = &dsp0;
		rproc1 = &dsp1;
		rproc2 = &dsp2;
		rproc3 = &dsp3;
		rproc4 = &dsp4;
		rproc5 = &dsp5;
		rproc6 = &dsp6;
		rproc7 = &dsp7;
	};

	/* 66AK2H/K DSP memory node */
	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp_common_memory: dsp-common-memory@81f800000 {
			compatible = "shared-dma-pool";
			reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
			reusable;
		};
	};

	/* 66AK2H/K DSP node */
	soc {
		dsp0: dsp@10800000 {
			compatible = "ti,k2hk-dsp";
			reg = <0x10800000 0x00100000>,
			      <0x10e00000 0x00008000>,
			      <0x10f00000 0x00008000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			clocks = <&clkgem0>;
			ti,syscon-dev = <&devctrl 0x40>;
			resets = <&pscrst 0>;
			interrupt-parent = <&kirq0>;
			interrupts = <0 8>;
			interrupt-names = "vring", "exception";
			kick-gpios = <&dspgpio0 27 0>;
			memory-region = <&dsp_common_memory>;
		};

	};

2.
	/* 66AK2G DSP alias */
	aliases {
		rproc0 = &dsp0;
	};

	/* 66AK2G DSP memory node */
	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp_common_memory: dsp-common-memory@81f800000 {
			compatible = "shared-dma-pool";
			reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
			reusable;
		};
	};

	/* 66AK2G DSP node */
	soc {
		dsp0: dsp@10800000 {
			compatible = "ti,k2g-dsp";
			reg = <0x10800000 0x00100000>,
			      <0x10e00000 0x00008000>,
			      <0x10f00000 0x00008000>;
			reg-names = "l2sram", "l1pram", "l1dram";
			power-domains = <&k2g_pds 0x0046>;
			ti,syscon-dev = <&devctrl 0x40>;
			resets = <&k2g_reset 0x0046 0x1>;
			interrupt-parent = <&kirq0>;
			interrupts = <0 8>;
			interrupt-names = "vring", "exception";
			kick-gpios = <&dspgpio0 27 0>;
			memory-region = <&dsp_common_memory>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: OMAP4+ Remoteproc Devices

maintainers:
  - Suman Anna <s-anna@ti.com>

description:
  The OMAP family of SoCs usually have one or more slave processor sub-systems
  that are used to offload some of the processor-intensive tasks, or to manage
  other hardware accelerators, for achieving various system level goals.

  The processor cores in the sub-system are usually behind an IOMMU, and may
  contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
  caches, an Interrupt Controller, a Cache Controller etc.

  The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
  sub-system. The DSP processor sub-system can contain any of the TI's C64x,
  C66x or C67x family of DSP cores as the main execution unit. The IPU processor
  sub-system usually contains either a Dual-Core Cortex-M3 or Dual-Core
  Cortex-M4 processors.

  Each remote processor sub-system is represented as a single DT node. Each node
  has a number of required or optional properties that enable the OS running on
  the host processor (MPU) to perform the device management of the remote
  processor and to communicate with the remote processor. The various properties
  can be classified as constant or variable. The constant properties are
  dictated by the SoC and does not change from one board to another having the
  same SoC. Examples of constant properties include 'iommus', 'reg'. The
  variable properties are dictated by the system integration aspects such as
  memory on the board, or configuration used within the corresponding firmware
  image. Examples of variable properties include 'mboxes', 'memory-region',
  'timers', 'watchdog-timers' etc.

properties:
  compatible:
    enum:
      - ti,omap4-dsp
      - ti,omap5-dsp
      - ti,dra7-dsp
      - ti,omap4-ipu
      - ti,omap5-ipu
      - ti,dra7-ipu

  iommus:
    minItems: 1
    maxItems: 2
    description: |
      phandles to OMAP IOMMU nodes, that need to be programmed
      for this remote processor to access any external RAM memory or
      other peripheral device address spaces. This property usually
      has only a single phandle. Multiple phandles are used only in
      cases where the sub-system has different ports for different
      sub-modules within the processor sub-system (eg: DRA7 DSPs),
      and need the same programming in both the MMUs.

  mboxes:
    minItems: 1
    maxItems: 2
    description: |
      OMAP Mailbox specifier denoting the sub-mailbox, to be used for
      communication with the remote processor. The specifier format is
      as per the bindings,
      Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml
      This property should match with the sub-mailbox node used in
      the firmware image.

  clocks:
    maxItems: 1
    description: |
      Main functional clock for the remote processor

  resets:
    minItems: 1
    maxItems: 2
    description: |
      Reset handles for the remote processor

  firmware-name:
    description: |
      Default name of the firmware to load to the remote processor.

# Optional properties:
# --------------------
# Some of these properties are mandatory on some SoCs, and some are optional
# depending on the configuration of the firmware image to be executed on the
# remote processor. The conditions are mentioned for each property.
#
# The following are the optional properties:

  memory-region:
    maxItems: 1
    description: |
      phandle to the reserved memory node to be associated
      with the remoteproc device. The reserved memory node
      can be a CMA memory node, and should be defined as
      per the bindings,
      Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt

  reg:
    description: |
      Address space for any remoteproc memories present on
      the SoC. Should contain an entry for each value in
      'reg-names'. These are mandatory for all DSP and IPU
      processors that have them (OMAP4/OMAP5 DSPs do not have
      any RAMs)

  reg-names:
    description: |
      Required names for each of the address spaces defined in
      the 'reg' property. Expects the names from the following
      list, in the specified order, each representing the corresponding
      internal RAM memory region.
    minItems: 1
    items:
      - const: l2ram
      - const: l1pram
      - const: l1dram

  ti,bootreg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to the System Control Configuration region
          - description: register offset of the boot address register
          - description: the bit shift within the register
    description:
      This property is required for all the DSP instances on OMAP4, OMAP5
      and DRA7xx SoCs.

  ti,autosuspend-delay-ms:
    description: |
      Custom autosuspend delay for the remoteproc in milliseconds.
      Recommended values is preferable to be in the order of couple
      of seconds. A negative value can also be used to disable the
      autosuspend behavior.

  ti,timers:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      maxItems: 1
    description: |
      One or more phandles to OMAP DMTimer nodes, that serve
      as System/Tick timers for the OS running on the remote
      processors. This will usually be a single timer if the
      processor sub-system is running in SMP mode, or one per
      core in the processor sub-system. This can also be used
      to reserve specific timers to be dedicated to the
      remote processors.

      This property is mandatory on remote processors requiring
      external tick wakeup, and to support Power Management
      features. The timers to be used should match with the
      timers used in the firmware image.

  ti,watchdog-timers:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      maxItems: 1
    description: |
      One or more phandles to OMAP DMTimer nodes, used to
      serve as Watchdog timers for the processor cores. This
      will usually be one per executing processor core, even
      if the processor sub-system is running a SMP OS.

      The timers to be used should match with the watchdog
      timers used in the firmware image.

if:
  properties:
    compatible:
      enum:
        - ti,dra7-dsp
then:
  properties:
    reg:
      minItems: 3
      maxItems: 3
  required:
    - reg
    - reg-names
    - ti,bootreg

else:
  if:
    properties:
      compatible:
        enum:
          - ti,omap4-ipu
          - ti,omap5-ipu
          - ti,dra7-ipu
  then:
    properties:
      reg:
        minItems: 1
        maxItems: 1
      ti,bootreg: false
    required:
      - reg
      - reg-names

  else:
    properties:
      reg: false
    required:
      - ti,bootreg

required:
  - compatible
  - iommus
  - mboxes
  - clocks
  - resets
  - firmware-name

additionalProperties: false

examples:
  - |

    //Example 1: OMAP4 DSP

    /* DSP Reserved Memory node */
    #include <dt-bindings/clock/omap4.h>
    reserved-memory {
        #address-cells = <1>;
        #size-cells = <1>;

        dsp_memory_region: dsp-memory@98000000 {
            compatible = "shared-dma-pool";
            reg = <0x98000000 0x800000>;
            reusable;
        };
    };

    /* DSP node */
    ocp {
        dsp: dsp {
            compatible = "ti,omap4-dsp";
            ti,bootreg = <&scm_conf 0x304 0>;
            iommus = <&mmu_dsp>;
            mboxes = <&mailbox &mbox_dsp>;
            memory-region = <&dsp_memory_region>;
            ti,timers = <&timer5>;
            ti,watchdog-timers = <&timer6>;
            clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
            resets = <&prm_tesla 0>, <&prm_tesla 1>;
            firmware-name = "omap4-dsp-fw.xe64T";
        };
    };

  - |+

    //Example 2: OMAP5 IPU

    /* IPU Reserved Memory node */
    #include <dt-bindings/clock/omap5.h>
    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;

        ipu_memory_region: ipu-memory@95800000 {
            compatible = "shared-dma-pool";
            reg = <0 0x95800000 0 0x3800000>;
            reusable;
        };
    };

    /* IPU node */
    ocp {
        #address-cells = <1>;
        #size-cells = <1>;

        ipu: ipu@55020000 {
            compatible = "ti,omap5-ipu";
            reg = <0x55020000 0x10000>;
            reg-names = "l2ram";
            iommus = <&mmu_ipu>;
            mboxes = <&mailbox &mbox_ipu>;
            memory-region = <&ipu_memory_region>;
            ti,timers = <&timer3>, <&timer4>;
            ti,watchdog-timers = <&timer9>, <&timer11>;
            clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
            resets = <&prm_core 2>;
            firmware-name = "omap5-ipu-fw.xem4";
        };
    };

  - |+

    //Example 3: DRA7xx/AM57xx DSP

    /* DSP1 Reserved Memory node */
    #include <dt-bindings/clock/dra7.h>
    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;

        dsp1_memory_region: dsp1-memory@99000000 {
            compatible = "shared-dma-pool";
            reg = <0x0 0x99000000 0x0 0x4000000>;
            reusable;
        };
    };

    /* DSP1 node */
    ocp {
        #address-cells = <1>;
        #size-cells = <1>;

        dsp1: dsp@40800000 {
            compatible = "ti,dra7-dsp";
            reg = <0x40800000 0x48000>,
                  <0x40e00000 0x8000>,
                  <0x40f00000 0x8000>;
            reg-names = "l2ram", "l1pram", "l1dram";
            ti,bootreg = <&scm_conf 0x55c 0>;
            iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
            mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
            memory-region = <&dsp1_memory_region>;
            ti,timers = <&timer5>;
            ti,watchdog-timers = <&timer10>;
            resets = <&prm_dsp1 0>;
            clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
            firmware-name = "dra7-dsp1-fw.xe66";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI Programmable Realtime Unit (PRU) cores

maintainers:
  - Suman Anna <s-anna@ti.com>

description: |
  Each Programmable Real-Time Unit and Industrial Communication Subsystem
  (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called
  Programmable Real-Time Units (PRUs), each represented by a node. Each PRU
  core has a dedicated Instruction RAM, Control and Debug register sets, and
  use the Data RAMs present within the PRU-ICSS for code execution.

  The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary
  PRU cores called RTUs with slightly different IP integration. The K3 SoCs
  containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
  auxiliary Transmit PRU cores called Tx_PRUs that augment the PRUs. Each RTU
  or Tx_PRU core can also be used independently like a PRU, or alongside a
  corresponding PRU core to provide/implement auxiliary functionality/support.

  Each PRU, RTU or Tx_PRU core node should be defined as a child node of the
  corresponding PRU-ICSS node. Each node can optionally be rendered inactive by
  using the standard DT string property, "status".

  Please see the overall PRU-ICSS bindings document for additional details
  including a complete example,
    Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml

properties:
  compatible:
    enum:
      - ti,am3356-pru   # for AM335x SoC family (AM3356+ SoCs only)
      - ti,am4376-pru   # for AM437x SoC family (AM4376+ SoCs only)
      - ti,am5728-pru   # for AM57xx SoC family
      - ti,am625-pru    # for PRUs in K3 AM62x SoC family
      - ti,am642-pru    # for PRUs in K3 AM64x SoC family
      - ti,am642-rtu    # for RTUs in K3 AM64x SoC family
      - ti,am642-tx-pru # for Tx_PRUs in K3 AM64x SoC family
      - ti,am654-pru    # for PRUs in K3 AM65x SoC family
      - ti,am654-rtu    # for RTUs in K3 AM65x SoC family
      - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
      - ti,j721e-pru    # for PRUs in K3 J721E SoC family
      - ti,j721e-rtu    # for RTUs in K3 J721E SoC family
      - ti,j721e-tx-pru # for Tx_PRUs in K3 J721E SoC family
      - ti,k2g-pru      # for 66AK2G SoC family

  reg:
    items:
      - description: Address and Size of the PRU Instruction RAM
      - description: Address and Size of the PRU CTRL sub-module registers
      - description: Address and Size of the PRU Debug sub-module registers

  reg-names:
    items:
      - const: iram
      - const: control
      - const: debug

  firmware-name:
    description: |
      Should contain the name of the default firmware image
      file located on the firmware search path.

if:
  properties:
    compatible:
      enum:
        - ti,am654-rtu
        - ti,j721e-rtu
        - ti,am642-rtu
then:
  properties:
    $nodename:
      pattern: "^rtu@[0-9a-f]+$"
else:
  if:
    properties:
      compatible:
        enum:
          - ti,am654-tx-pru
          - ti,j721e-tx-pru
          - ti,am642-tx-pru
  then:
    properties:
      $nodename:
        pattern: "^txpru@[0-9a-f]+"
  else:
    properties:
      $nodename:
        pattern: "^pru@[0-9a-f]+$"

required:
  - compatible
  - reg
  - reg-names
  - firmware-name

additionalProperties: false

examples:
  - |
    /* AM33xx PRU-ICSS */
    pruss_tm: target-module@300000 {  /* 0x4a300000, ap 9 04.0 */
      compatible = "ti,sysc-pruss", "ti,sysc";
      #address-cells = <1>;
      #size-cells = <1>;
      ranges = <0x0 0x300000 0x80000>;

      pruss: pruss@0 {
        compatible = "ti,am3356-pruss";
        reg = <0x0 0x80000>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        pruss_mem: memories@0 {
          reg = <0x0 0x2000>,
                <0x2000 0x2000>,
                <0x10000 0x3000>;
          reg-names = "dram0", "dram1", "shrdram2";
        };

        pru0: pru@34000 {
          compatible = "ti,am3356-pru";
          reg = <0x34000 0x2000>,
                <0x22000 0x400>,
                <0x22400 0x100>;
          reg-names = "iram", "control", "debug";
          firmware-name = "am335x-pru0-fw";
        };

        pru1: pru@38000 {
          compatible = "ti,am3356-pru";
          reg = <0x38000 0x2000>,
                <0x24000 0x400>,
                <0x24400 0x100>;
          reg-names = "iram", "control", "debug";
          firmware-name = "am335x-pru1-fw";
        };
      };
    };

  - |
    /* AM65x SR2.0 ICSSG */
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    icssg0: icssg@b000000 {
      compatible = "ti,am654-icssg";
      reg = <0xb000000 0x80000>;
      power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
      #address-cells = <1>;
      #size-cells = <1>;
      ranges = <0x0 0xb000000 0x80000>;

      icssg0_mem: memories@0 {
        reg = <0x0 0x2000>,
              <0x2000 0x2000>,
              <0x10000 0x10000>;
        reg-names = "dram0", "dram1", "shrdram2";
      };

      pru0_0: pru@34000 {
        compatible = "ti,am654-pru";
        reg = <0x34000 0x4000>,
              <0x22000 0x100>,
              <0x22400 0x100>;
        reg-names = "iram", "control", "debug";
        firmware-name = "am65x-pru0_0-fw";
      };

      rtu0_0: rtu@4000 {
        compatible = "ti,am654-rtu";
        reg = <0x4000 0x2000>,
              <0x23000 0x100>,
              <0x23400 0x100>;
        reg-names = "iram", "control", "debug";
        firmware-name = "am65x-rtu0_0-fw";
      };

      tx_pru0_0: txpru@a000 {
        compatible = "ti,am654-tx-pru";
        reg = <0xa000 0x1800>,
              <0x25000 0x100>,
              <0x25400 0x100>;
        reg-names = "iram", "control", "debug";
        firmware-name = "am65x-txpru0_0-fw";
      };

      pru0_1: pru@38000 {
        compatible = "ti,am654-pru";
        reg = <0x38000 0x4000>,
              <0x24000 0x100>,
              <0x24400 0x100>;
        reg-names = "iram", "control", "debug";
        firmware-name = "am65x-pru0_1-fw";
      };

      rtu0_1: rtu@6000 {
        compatible = "ti,am654-rtu";
        reg = <0x6000 0x2000>,
              <0x23800 0x100>,
              <0x23c00 0x100>;
        reg-names = "iram", "control", "debug";
        firmware-name = "am65x-rtu0_1-fw";
      };

      tx_pru0_1: txpru@c000 {
        compatible = "ti,am654-tx-pru";
        reg = <0xc000 0x1800>,
              <0x25800 0x100>,
              <0x25c00 0x100>;
        reg-names = "iram", "control", "debug";
        firmware-name = "am65x-txpru0_1-fw";
      };
    };


code:
TI Wakeup M3 Remoteproc Driver
==============================

The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
(commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
that cannot be controlled from the MPU. This CM3 processor requires a firmware
binary to accomplish this. The wkup_m3 remoteproc driver handles the loading of
the firmware and booting of the CM3.

Wkup M3 Device Node:
====================
A wkup_m3 device node is used to represent the Wakeup M3 processor instance
within the SoC. It is added as a child node of the parent interconnect bus
(l4_wkup) through which it is accessible to the MPU.

Required properties:
--------------------
- compatible:		Should be one of,
				"ti,am3352-wkup-m3" for AM33xx SoCs
				"ti,am4372-wkup-m3" for AM43xx SoCs
- reg:			Should contain the address ranges for the two internal
			memory regions, UMEM and DMEM. The parent node should
			provide an appropriate ranges property for properly
			translating these into bus addresses.
- reg-names:		Contains the corresponding names for the two memory
			regions. These should be named "umem" & "dmem".
- ti,hwmods:		Name of the hwmod associated with the wkupm3 device.
- ti,pm-firmware:	Name of firmware file to be used for loading and
			booting the wkup_m3 remote processor.

Example:
--------
/* AM33xx */
ocp {
	 l4_wkup: l4_wkup@44c00000 {
		compatible = "am335-l4-wkup", "simple-bus";
		ranges = <0 0x44c00000 0x400000>;
		#address-cells = <1>;
		#size-cells = <1>;

		wkup_m3: wkup_m3@100000 {
			compatible = "ti,am3352-wkup-m3";
			reg = <0x100000 0x4000>,
			      <0x180000 0x2000>;
			reg-names = "umem", "dmem";
			ti,hwmods = "wkup_m3";
			ti,pm-firmware = "am335x-pm-firmware.elf";
		};
	};

	...
};