code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP34XX/OMAP36XX clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 */
&cm_clocks {
	security_l4_ick2: security_l4_ick2 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&l4_ick>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	clock@a14 {
		compatible = "ti,clksel";
		reg = <0xa14>;
		#clock-cells = <2>;
		#address-cells = <0>;

		aes1_ick: clock-aes1-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "aes1_ick";
			clocks = <&security_l4_ick2>;
			ti,bit-shift = <3>;
		};

		rng_ick: clock-rng-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "rng_ick";
			clocks = <&security_l4_ick2>;
			ti,bit-shift = <2>;
		};

		sha11_ick: clock-sha11-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "sha11_ick";
			clocks = <&security_l4_ick2>;
			ti,bit-shift = <1>;
		};

		des1_ick: clock-des1-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "des1_ick";
			clocks = <&security_l4_ick2>;
			ti,bit-shift = <0>;
		};

		pka_ick: clock-pka-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "pka_ick";
			clocks = <&security_l3_ick>;
			ti,bit-shift = <4>;
		};
	};

	/* CM_FCLKEN_CAM */
	clock@f00 {
		compatible = "ti,clksel";
		reg = <0xf00>;
		#clock-cells = <2>;
		#address-cells = <0>;

		cam_mclk: clock-cam-mclk {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "cam_mclk";
			clocks = <&dpll4_m5x2_ck>;
			ti,bit-shift = <0>;
			ti,set-rate-parent;
		};

		csi2_96m_fck: clock-csi2-96m-fck {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "csi2_96m_fck";
			clocks = <&core_96m_fck>;
			ti,bit-shift = <1>;
		};
	};

	cam_ick: cam_ick@f10 {
		#clock-cells = <0>;
		compatible = "ti,omap3-no-wait-interface-clock";
		clocks = <&l4_ick>;
		reg = <0x0f10>;
		ti,bit-shift = <0>;
	};

	security_l3_ick: security_l3_ick {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&l3_ick>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	clock@a10 {
		compatible = "ti,clksel";
		reg = <0xa10>;
		#clock-cells = <2>;
		#address-cells = <0>;

		icr_ick: clock-icr-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "icr_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <29>;
		};

		des2_ick: clock-des2-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "des2_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <26>;
		};

		mspro_ick: clock-mspro-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mspro_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <23>;
		};

		mailboxes_ick: clock-mailboxes-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mailboxes_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <7>;
		};

		sad2d_ick: clock-sad2d-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "sad2d_ick";
			clocks = <&l3_ick>;
			ti,bit-shift = <3>;
		};
	};

	ssi_l4_ick: ssi_l4_ick {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&l4_ick>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	clock@c00 {
		compatible = "ti,clksel";
		reg = <0xc00>;
		#clock-cells = <2>;
		#address-cells = <0>;

		sr1_fck: clock-sr1-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "sr1_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <6>;
		};

		sr2_fck: clock-sr2-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "sr2_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <7>;
		};
	};

	sr_l4_ick: sr_l4_ick {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&l4_ick>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll2_fck: dpll2_fck@40 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <19>;
		ti,max-div = <7>;
		reg = <0x0040>;
		ti,index-starts-at-one;
	};

	dpll2_ck: dpll2_ck@4 {
		#clock-cells = <0>;
		compatible = "ti,omap3-dpll-clock";
		clocks = <&sys_ck>, <&dpll2_fck>;
		reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
		ti,low-power-stop;
		ti,lock;
		ti,low-power-bypass;
	};

	dpll2_m2_ck: dpll2_m2_ck@44 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll2_ck>;
		ti,max-div = <31>;
		reg = <0x0044>;
		ti,index-starts-at-one;
	};

	iva2_ck: iva2_ck@0 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&dpll2_m2_ck>;
		reg = <0x0000>;
		ti,bit-shift = <0>;
	};

	clock@a00 {
		compatible = "ti,clksel";
		reg = <0xa00>;
		#clock-cells = <2>;
		#address-cells = <0>;

		modem_fck: clock-modem-fck {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "modem_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <31>;
		};

		mspro_fck: clock-mspro-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "mspro_fck";
			clocks = <&core_96m_fck>;
			ti,bit-shift = <23>;
		};
	};

	/* CM_ICLKEN3_CORE */
	clock@a18 {
		compatible = "ti,clksel";
		reg = <0xa18>;
		#clock-cells = <2>;
		#address-cells = <0>;

		mad2d_ick: clock-mad2d-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mad2d_ick";
			clocks = <&l3_ick>;
			ti,bit-shift = <3>;
		};
	};

};

&cm_clockdomains {
	cam_clkdm: cam_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&cam_ick>, <&csi2_96m_fck>;
	};

	iva2_clkdm: iva2_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&iva2_ck>;
	};

	dpll2_clkdm: dpll2_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dpll2_ck>;
	};

	wkup_clkdm: wkup_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
			 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
			 <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
	};

	d2d_clkdm: d2d_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
	};

	core_l4_clkdm: core_l4_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
			 <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
			 <&rng_ick>, <&mspro_fck>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP34xx/OMAP35xx SoC
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/media/omap3-isp.h>

#include "omap3.dtsi"

/ {
	cpus {
		cpu: cpu@0 {
			/* OMAP343x/OMAP35xx variants OPP1-6 */
			operating-points-v2 = <&cpu0_opp_table>;

			clock-latency = <300000>; /* From legacy driver */
			#cooling-cells = <2>;
		};
	};

	cpu0_opp_table: opp-table {
		compatible = "operating-points-v2-ti-cpu";
		syscon = <&scm_conf>;

		opp1-125000000 {
			opp-hz = /bits/ 64 <125000000>;
			/*
			 * we currently only select the max voltage from table
			 * Table 3-3 of the omap3530 Data sheet (SPRS507F).
			 * Format is: <target min max>
			 */
			opp-microvolt = <975000 975000 975000>;
			/*
			 * first value is silicon revision bit mask
			 * second one 720MHz Device Identification bit mask
			 */
			opp-supported-hw = <0xffffffff 3>;
		};

		opp2-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			opp-microvolt = <1075000 1075000 1075000>;
			opp-supported-hw = <0xffffffff 3>;
			opp-suspend;
		};

		opp3-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <1200000 1200000 1200000>;
			opp-supported-hw = <0xffffffff 3>;
		};

		opp4-550000000 {
			opp-hz = /bits/ 64 <550000000>;
			opp-microvolt = <1275000 1275000 1275000>;
			opp-supported-hw = <0xffffffff 3>;
		};

		opp5-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1350000 1350000 1350000>;
			opp-supported-hw = <0xffffffff 3>;
		};

		opp6-720000000 {
			opp-hz = /bits/ 64 <720000000>;
			opp-microvolt = <1350000 1350000 1350000>;
			/* only high-speed grade omap3530 devices */
			opp-supported-hw = <0xffffffff 2>;
			turbo-mode;
		};
	};

	ocp@68000000 {
		omap3_pmx_core2: pinmux@480025d8 {
			compatible = "ti,omap3-padconf", "pinctrl-single";
			reg = <0x480025d8 0x24>;
			#address-cells = <1>;
			#size-cells = <0>;
			#pinctrl-cells = <1>;
			#interrupt-cells = <1>;
			interrupt-controller;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0xff1f>;
		};

		isp: isp@480bc000 {
			compatible = "ti,omap3-isp";
			reg = <0x480bc000 0x12fc
			       0x480bd800 0x017c>;
			interrupts = <24>;
			iommus = <&mmu_isp>;
			syscon = <&scm_conf 0x6c>;
			ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
			#clock-cells = <1>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		bandgap: bandgap@48002524 {
			reg = <0x48002524 0x4>;
			compatible = "ti,omap34xx-bandgap";
			#thermal-sensor-cells = <0>;
		};

		target-module@480cb000 {
			compatible = "ti,sysc-omap3430-sr", "ti,sysc";
			ti,hwmods = "smartreflex_core";
			reg = <0x480cb024 0x4>;
			reg-names = "sysc";
			ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
			clocks = <&sr2_fck>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x480cb000 0x001000>;

			smartreflex_core: smartreflex@0 {
				compatible = "ti,omap3-smartreflex-core";
				reg = <0 0x400>;
				interrupts = <19>;
			};
		};

		target-module@480c9000 {
			compatible = "ti,sysc-omap3430-sr", "ti,sysc";
			ti,hwmods = "smartreflex_mpu_iva";
			reg = <0x480c9024 0x4>;
			reg-names = "sysc";
			ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
			clocks = <&sr1_fck>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x480c9000 0x001000>;

			smartreflex_mpu_iva: smartreflex@480c9000 {
				compatible = "ti,omap3-smartreflex-mpu-iva";
				reg = <0 0x400>;
				interrupts = <18>;
			};
		};

		/*
		 * On omap34xx the OCP registers do not seem to be accessible
		 * at all unlike on 36xx. Maybe SGX is permanently set to
		 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
		 * write-only at 0x50000e10. We detect SGX based on the SGX
		 * revision register instead of the unreadable OCP revision
		 * register. Also note that on early 34xx es1 revision there
		 * are also different clocks, but we do not have any dts users
		 * for it.
		 */
		sgx_module: target-module@50000000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x50000014 0x4>;
			reg-names = "rev";
			clocks = <&sgx_fck>, <&sgx_ick>;
			clock-names = "fck", "ick";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x50000000 0x4000>;

			/*
			 * Closed source PowerVR driver, no child device
			 * binding or driver in mainline
			 */
		};
	};

	thermal_zones: thermal-zones {
		#include "omap3-cpu-thermal.dtsi"
	};
};

&ssi {
	status = "okay";

	clocks = <&ssi_ssr_fck>,
		 <&ssi_sst_fck>,
		 <&ssi_ick>;
	clock-names = "ssi_ssr_fck",
		      "ssi_sst_fck",
		      "ssi_ick";
};

&usb_otg_target {
	clocks = <&hsotgusb_ick_3430es2>;
};

/include/ "omap34xx-omap36xx-clocks.dtsi"
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 */
&prm_clocks {
	corex2_d3_fck: corex2_d3_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&corex2_fck>;
		clock-mult = <1>;
		clock-div = <3>;
	};

	corex2_d5_fck: corex2_d5_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&corex2_fck>;
		clock-mult = <1>;
		clock-div = <5>;
	};
};
&cm_clocks {
	dpll5_ck: dpll5_ck@d04 {
		#clock-cells = <0>;
		compatible = "ti,omap3-dpll-clock";
		clocks = <&sys_ck>, <&sys_ck>;
		reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
		ti,low-power-stop;
		ti,lock;
	};

	dpll5_m2_ck: dpll5_m2_ck@d50 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll5_ck>;
		ti,max-div = <31>;
		reg = <0x0d50>;
		ti,index-starts-at-one;
	};

	sgx_gate_fck: sgx_gate_fck@b00 {
		#clock-cells = <0>;
		compatible = "ti,composite-gate-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <1>;
		reg = <0x0b00>;
	};

	core_d3_ck: core_d3_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&core_ck>;
		clock-mult = <1>;
		clock-div = <3>;
	};

	core_d4_ck: core_d4_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&core_ck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	core_d6_ck: core_d6_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&core_ck>;
		clock-mult = <1>;
		clock-div = <6>;
	};

	omap_192m_alwon_fck: omap_192m_alwon_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll4_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	core_d2_ck: core_d2_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&core_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	sgx_mux_fck: sgx_mux_fck@b40 {
		#clock-cells = <0>;
		compatible = "ti,composite-mux-clock";
		clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
		reg = <0x0b40>;
	};

	sgx_fck: sgx_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
	};

	sgx_ick: sgx_ick@b10 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&l3_ick>;
		reg = <0x0b10>;
		ti,bit-shift = <0>;
	};

	cpefuse_fck: cpefuse_fck@a08 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&sys_ck>;
		reg = <0x0a08>;
		ti,bit-shift = <0>;
	};

	ts_fck: ts_fck@a08 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&omap_32k_fck>;
		reg = <0x0a08>;
		ti,bit-shift = <1>;
	};

	usbtll_fck: usbtll_fck@a08 {
		#clock-cells = <0>;
		compatible = "ti,wait-gate-clock";
		clocks = <&dpll5_m2_ck>;
		reg = <0x0a08>;
		ti,bit-shift = <2>;
	};

	/* CM_ICLKEN3_CORE */
	clock@a18 {
		compatible = "ti,clksel";
		reg = <0xa18>;
		#clock-cells = <2>;
		#address-cells = <0>;

		usbtll_ick: clock-usbtll-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "usbtll_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <2>;
		};
	};

	clock@a10 {
		compatible = "ti,clksel";
		reg = <0xa10>;
		#clock-cells = <2>;
		#address-cells = <0>;

		mmchs3_ick: clock-mmchs3-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mmchs3_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <30>;
		};
	};

	clock@a00 {
		compatible = "ti,clksel";
		reg = <0xa00>;
		#clock-cells = <2>;
		#address-cells = <0>;

		mmchs3_fck: clock-mmchs3-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "mmchs3_fck";
			clocks = <&core_96m_fck>;
			ti,bit-shift = <30>;
		};
	};

	clock@e00 {
		compatible = "ti,clksel";
		reg = <0xe00>;
		#clock-cells = <2>;
		#address-cells = <0>;

		dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 {
			#clock-cells = <0>;
			compatible = "ti,dss-gate-clock";
			clock-output-names = "dss1_alwon_fck_3430es2";
			clocks = <&dpll4_m4x2_ck>;
			ti,bit-shift = <0>;
			ti,set-rate-parent;
		};
	};

	dss_ick: dss_ick_3430es2@e10 {
		#clock-cells = <0>;
		compatible = "ti,omap3-dss-interface-clock";
		clocks = <&l4_ick>;
		reg = <0x0e10>;
		ti,bit-shift = <0>;
	};

	usbhost_120m_fck: usbhost_120m_fck@1400 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll5_m2_ck>;
		reg = <0x1400>;
		ti,bit-shift = <1>;
	};

	usbhost_48m_fck: usbhost_48m_fck@1400 {
		#clock-cells = <0>;
		compatible = "ti,dss-gate-clock";
		clocks = <&omap_48m_fck>;
		reg = <0x1400>;
		ti,bit-shift = <0>;
	};

	usbhost_ick: usbhost_ick@1410 {
		#clock-cells = <0>;
		compatible = "ti,omap3-dss-interface-clock";
		clocks = <&l4_ick>;
		reg = <0x1410>;
		ti,bit-shift = <0>;
	};
};

&cm_clockdomains {
	dpll5_clkdm: dpll5_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dpll5_ck>;
	};

	sgx_clkdm: sgx_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&sgx_ick>;
	};

	dss_clkdm: dss_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
			 <&dss1_alwon_fck>, <&dss_ick>;
	};

	core_l4_clkdm: core_l4_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
			 <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
			 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
	};

	usbhost_clkdm: usbhost_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
			 <&usbhost_ick>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP36xx clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 */
&cm_clocks {
	dpll4_ck: dpll4_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,omap3-dpll-per-j-type-clock";
		clocks = <&sys_ck>, <&sys_ck>;
		reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
	};

	dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,hsdiv-gate-clock";
		clocks = <&dpll4_m5x2_mul_ck>;
		ti,bit-shift = <0x1e>;
		reg = <0x0d00>;
		ti,set-rate-parent;
		ti,set-bit-to-disable;
	};

	dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,hsdiv-gate-clock";
		clocks = <&dpll4_m2x2_mul_ck>;
		ti,bit-shift = <0x1b>;
		reg = <0x0d00>;
		ti,set-bit-to-disable;
	};

	dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,hsdiv-gate-clock";
		clocks = <&dpll3_m3x2_mul_ck>;
		ti,bit-shift = <0xc>;
		reg = <0x0d00>;
		ti,set-bit-to-disable;
	};

	dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,hsdiv-gate-clock";
		clocks = <&dpll4_m3x2_mul_ck>;
		ti,bit-shift = <0x1c>;
		reg = <0x0d00>;
		ti,set-bit-to-disable;
	};

	dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,hsdiv-gate-clock";
		clocks = <&dpll4_m6x2_mul_ck>;
		ti,bit-shift = <0x1f>;
		reg = <0x0d00>;
		ti,set-bit-to-disable;
	};

	clock@1000 {
		compatible = "ti,clksel";
		reg = <0x1000>;
		#clock-cells = <2>;
		#address-cells = <0>;

		uart4_fck: clock-uart4-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "uart4_fck";
			clocks = <&per_48m_fck>;
			ti,bit-shift = <18>;
		};
	};
};

&dpll4_m2x2_mul_ck {
	clock-mult = <1>;
};

&dpll4_m3x2_mul_ck {
	clock-mult = <1>;
};

&dpll4_m4x2_mul_ck {
	ti,clock-mult = <1>;
};

&dpll4_m5x2_mul_ck {
	ti,clock-mult = <1>;
};

&dpll4_m6x2_mul_ck {
	clock-mult = <1>;
};

&cm_clockdomains {
	dpll4_clkdm: dpll4_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dpll4_ck>;
	};

	per_clkdm: per_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
			 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
			 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
			 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
			 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
			 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
			 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
			 <&mcbsp4_ick>, <&uart4_fck>;
	};
};

&dpll4_m4_ck {
	ti,max-div = <31>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP34xx/OMAP36xx clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 */
&cm_clocks {
	clock@a00 {
		compatible = "ti,clksel";
		reg = <0xa00>;
		#clock-cells = <2>;
		#address-cells = <0>;

		ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
			#clock-cells = <0>;
			compatible = "ti,composite-no-wait-gate-clock";
			clock-output-names = "ssi_ssr_gate_fck_3430es2";
			clocks = <&corex2_fck>;
			ti,bit-shift = <0>;
		};
	};

	clock@a40 {
		compatible = "ti,clksel";
		reg = <0xa40>;
		#clock-cells = <2>;
		#address-cells = <0>;

		ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
			#clock-cells = <0>;
			compatible = "ti,composite-divider-clock";
			clock-output-names = "ssi_ssr_div_fck_3430es2";
			clocks = <&corex2_fck>;
			ti,bit-shift = <8>;
			ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
		};
	};

	ssi_ssr_fck: ssi_ssr_fck_3430es2 {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
	};

	ssi_sst_fck: ssi_sst_fck_3430es2 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&ssi_ssr_fck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	clock@a10 {
		compatible = "ti,clksel";
		reg = <0xa10>;
		#clock-cells = <2>;
		#address-cells = <0>;

		hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 {
			#clock-cells = <0>;
			compatible = "ti,omap3-hsotgusb-interface-clock";
			clock-output-names = "hsotgusb_ick_3430es2";
			clocks = <&core_l3_ick>;
			ti,bit-shift = <4>;
		};

		ssi_ick: clock-ssi-ick-3430es2 {
			#clock-cells = <0>;
			compatible = "ti,omap3-ssi-interface-clock";
			clock-output-names = "ssi_ick_3430es2";
			clocks = <&ssi_l4_ick>;
			ti,bit-shift = <0>;
		};
	};

	ssi_l4_ick: ssi_l4_ick {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&l4_ick>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	clock@c00 {
		compatible = "ti,clksel";
		reg = <0xc00>;
		#clock-cells = <2>;
		#address-cells = <0>;

		usim_gate_fck: clock-usim-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "usim_gate_fck";
			clocks = <&omap_96m_fck>;
			ti,bit-shift = <9>;
		};
	};

	sys_d2_ck: sys_d2_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_ck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	omap_96m_d2_fck: omap_96m_d2_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_96m_fck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	omap_96m_d4_fck: omap_96m_d4_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_96m_fck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	omap_96m_d8_fck: omap_96m_d8_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_96m_fck>;
		clock-mult = <1>;
		clock-div = <8>;
	};

	omap_96m_d10_fck: omap_96m_d10_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_96m_fck>;
		clock-mult = <1>;
		clock-div = <10>;
	};

	dpll5_m2_d4_ck: dpll5_m2_d4_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll5_m2_ck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	dpll5_m2_d8_ck: dpll5_m2_d8_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll5_m2_ck>;
		clock-mult = <1>;
		clock-div = <8>;
	};

	dpll5_m2_d16_ck: dpll5_m2_d16_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll5_m2_ck>;
		clock-mult = <1>;
		clock-div = <16>;
	};

	dpll5_m2_d20_ck: dpll5_m2_d20_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll5_m2_ck>;
		clock-mult = <1>;
		clock-div = <20>;
	};

	clock@c40 {
		compatible = "ti,clksel";
		reg = <0xc40>;
		#clock-cells = <2>;
		#address-cells = <0>;

		usim_mux_fck: clock-usim-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "usim_mux_fck";
			clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
			ti,bit-shift = <3>;
			ti,index-starts-at-one;
		};
	};

	usim_fck: usim_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&usim_gate_fck>, <&usim_mux_fck>;
	};

	clock@c10 {
		compatible = "ti,clksel";
		reg = <0xc10>;
		#clock-cells = <2>;
		#address-cells = <0>;

		usim_ick: clock-usim-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "usim_ick";
			clocks = <&wkup_l4_ick>;
			ti,bit-shift = <9>;
		};
	};
};

&cm_clockdomains {
	core_l3_clkdm: core_l3_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
	};

	wkup_clkdm: wkup_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
			 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
			 <&gpt1_ick>, <&usim_ick>;
	};

	core_l4_clkdm: core_l4_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
			 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
			 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
			 <&ssi_ick>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP3 SoC
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/media/omap3-isp.h>

#include "omap3.dtsi"

/ {
	aliases {
		serial3 = &uart4;
	};

	cpus {
		/* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
		cpu: cpu@0 {
			operating-points-v2 = <&cpu0_opp_table>;

			vbb-supply = <&abb_mpu_iva>;
			clock-latency = <300000>; /* From omap-cpufreq driver */
			#cooling-cells = <2>;
		};
	};

	cpu0_opp_table: opp-table {
		compatible = "operating-points-v2-ti-cpu";
		syscon = <&scm_conf>;

		opp50-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			/*
			 * we currently only select the max voltage from table
			 * Table 4-19 of the DM3730 Data sheet (SPRS685B)
			 * Format is:	cpu0-supply:	<target min max>
			 *		vbb-supply:	<target min max>
			 */
			opp-microvolt = <1012500 1012500 1012500>,
					 <1012500 1012500 1012500>;
			/*
			 * first value is silicon revision bit mask
			 * second one is "speed binned" bit mask
			 */
			opp-supported-hw = <0xffffffff 3>;
			opp-suspend;
		};

		opp100-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1200000 1200000 1200000>,
					 <1200000 1200000 1200000>;
			opp-supported-hw = <0xffffffff 3>;
		};

		opp130-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <1325000 1325000 1325000>,
					 <1325000 1325000 1325000>;
			opp-supported-hw = <0xffffffff 3>;
		};

		opp1g-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <1375000 1375000 1375000>,
					 <1375000 1375000 1375000>;
			/* only on am/dm37x with speed-binned bit set */
			opp-supported-hw = <0xffffffff 2>;
		};
	};

	opp_supply_mpu_iva: opp_supply {
		compatible = "ti,omap-opp-supply";
		ti,absolute-max-voltage-uv = <1375000>;
	};

	ocp@68000000 {
		uart4: serial@49042000 {
			compatible = "ti,omap3-uart";
			reg = <0x49042000 0x400>;
			interrupts = <80>;
			dmas = <&sdma 81 &sdma 82>;
			dma-names = "tx", "rx";
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		abb_mpu_iva: regulator-abb-mpu {
			compatible = "ti,abb-v1";
			regulator-name = "abb_mpu_iva";
			#address-cells = <0>;
			#size-cells = <0>;
			reg = <0x483072f0 0x8>, <0x48306818 0x4>;
			reg-names = "base-address", "int-address";
			ti,tranxdone-status-mask = <0x4000000>;
			clocks = <&sys_ck>;
			ti,settling-time = <30>;
			ti,clock-cycles = <8>;
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
			1012500		0	0	0	0	0
			1200000		0	0	0	0	0
			1325000		0	0	0	0	0
			1375000		1	0	0	0	0
			>;
		};

		omap3_pmx_core2: pinmux@480025a0 {
			compatible = "ti,omap3-padconf", "pinctrl-single";
			reg = <0x480025a0 0x5c>;
			#address-cells = <1>;
			#size-cells = <0>;
			#pinctrl-cells = <1>;
			#interrupt-cells = <1>;
			interrupt-controller;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0xff1f>;
		};

		isp: isp@480bc000 {
			compatible = "ti,omap3-isp";
			reg = <0x480bc000 0x12fc
			       0x480bd800 0x0600>;
			interrupts = <24>;
			iommus = <&mmu_isp>;
			syscon = <&scm_conf 0x2f0>;
			ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
			#clock-cells = <1>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		bandgap: bandgap@48002524 {
			reg = <0x48002524 0x4>;
			compatible = "ti,omap36xx-bandgap";
			#thermal-sensor-cells = <0>;
		};

		target-module@480cb000 {
			compatible = "ti,sysc-omap3630-sr", "ti,sysc";
			ti,hwmods = "smartreflex_core";
			reg = <0x480cb038 0x4>;
			reg-names = "sysc";
			ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&sr2_fck>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x480cb000 0x001000>;

			smartreflex_core: smartreflex@0 {
				compatible = "ti,omap3-smartreflex-core";
				reg = <0 0x400>;
				interrupts = <19>;
			};
		};

		target-module@480c9000 {
			compatible = "ti,sysc-omap3630-sr", "ti,sysc";
			ti,hwmods = "smartreflex_mpu_iva";
			reg = <0x480c9038 0x4>;
			reg-names = "sysc";
			ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&sr1_fck>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x480c9000 0x001000>;

			smartreflex_mpu_iva: smartreflex@480c9000 {
				compatible = "ti,omap3-smartreflex-mpu-iva";
				reg = <0 0x400>;
				interrupts = <18>;
			};
		};

		/*
		 * Note that the sysconfig register layout is a subset of the
		 * "ti,sysc-omap4" type register with just sidle and midle bits
		 * available while omap34xx has "ti,sysc-omap2" type sysconfig.
		 */
		sgx_module: target-module@50000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x5000fe00 0x4>,
			      <0x5000fe10 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&sgx_fck>, <&sgx_ick>;
			clock-names = "fck", "ick";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x50000000 0x2000000>;

			/*
			 * Closed source PowerVR driver, no child device
			 * binding or driver in mainline
			 */
		};
	};

	thermal_zones: thermal-zones {
		#include "omap3-cpu-thermal.dtsi"
	};
};

&sdma {
	compatible = "ti,omap3630-sdma", "ti,omap-sdma";
};

/* OMAP3630 needs dss_96m_fck for VENC */
&venc {
	clocks = <&dss_tv_fck>, <&dss_96m_fck>;
	clock-names = "fck", "tv_dac_clk";
};

&ssi {
	status = "okay";

	clocks = <&ssi_ssr_fck>,
		 <&ssi_sst_fck>,
		 <&ssi_ick>;
	clock-names = "ssi_ssr_fck",
		      "ssi_sst_fck",
		      "ssi_ick";
};

&usb_otg_target {
	clocks = <&hsotgusb_ick_3430es2>;
};

/include/ "omap34xx-omap36xx-clocks.dtsi"
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-clocks.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP3 clock data
 *
 * Copyright (C) 2013 Texas Instruments, Inc.
 */
&prm_clocks {
	virt_16_8m_ck: virt_16_8m_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <16800000>;
	};

	osc_sys_ck: osc_sys_ck@d40 {
		#clock-cells = <0>;
		compatible = "ti,mux-clock";
		clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
		reg = <0x0d40>;
	};

	sys_ck: sys_ck@1270 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&osc_sys_ck>;
		ti,bit-shift = <6>;
		ti,max-div = <3>;
		reg = <0x1270>;
		ti,index-starts-at-one;
	};

	sys_clkout1: sys_clkout1@d70 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&osc_sys_ck>;
		reg = <0x0d70>;
		ti,bit-shift = <7>;
	};

	dpll3_x2_ck: dpll3_x2_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll3_ck>;
		clock-mult = <2>;
		clock-div = <1>;
	};

	dpll3_m2x2_ck: dpll3_m2x2_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll3_m2_ck>;
		clock-mult = <2>;
		clock-div = <1>;
	};

	dpll4_x2_ck: dpll4_x2_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll4_ck>;
		clock-mult = <2>;
		clock-div = <1>;
	};

	corex2_fck: corex2_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll3_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	wkup_l4_ick: wkup_l4_ick {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&sys_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};
};

&scm_clocks {
	/* CONTROL_DEVCONF1 */
	clock@68 {
		compatible = "ti,clksel";
		reg = <0x68>;
		#clock-cells = <2>;
		#address-cells = <0>;

		mcbsp5_mux_fck: clock-mcbsp5-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "mcbsp5_mux_fck";
			clocks = <&core_96m_fck>, <&mcbsp_clks>;
			ti,bit-shift = <4>;
		};

		mcbsp3_mux_fck: clock-mcbsp3-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "mcbsp3_mux_fck";
			clocks = <&per_96m_fck>, <&mcbsp_clks>;
		};

		mcbsp4_mux_fck: clock-mcbsp4-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "mcbsp4_mux_fck";
			clocks = <&per_96m_fck>, <&mcbsp_clks>;
			ti,bit-shift = <2>;
		};
	};

	mcbsp5_fck: mcbsp5_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
	};

	/* CONTROL_DEVCONF0 */
	clock@4 {
		compatible = "ti,clksel";
		reg = <0x4>;
		#clock-cells = <2>;
		#address-cells = <0>;

		mcbsp1_mux_fck: clock-mcbsp1-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "mcbsp1_mux_fck";
			clocks = <&core_96m_fck>, <&mcbsp_clks>;
			ti,bit-shift = <2>;
		};

		mcbsp2_mux_fck: clock-mcbsp2-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "mcbsp2_mux_fck";
			clocks = <&per_96m_fck>, <&mcbsp_clks>;
			ti,bit-shift = <6>;
		};
	};

	mcbsp1_fck: mcbsp1_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
	};

	mcbsp2_fck: mcbsp2_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
	};

	mcbsp3_fck: mcbsp3_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
	};

	mcbsp4_fck: mcbsp4_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
	};
};
&cm_clocks {
	dummy_apb_pclk: dummy_apb_pclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0x0>;
	};

	omap_32k_fck: omap_32k_fck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
	};

	virt_12m_ck: virt_12m_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <12000000>;
	};

	virt_13m_ck: virt_13m_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
	};

	virt_19200000_ck: virt_19200000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <19200000>;
	};

	virt_26000000_ck: virt_26000000_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
	};

	virt_38_4m_ck: virt_38_4m_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <38400000>;
	};

	dpll4_ck: dpll4_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,omap3-dpll-per-clock";
		clocks = <&sys_ck>, <&sys_ck>;
		reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
	};

	dpll4_m2_ck: dpll4_m2_ck@d48 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll4_ck>;
		ti,max-div = <63>;
		reg = <0x0d48>;
		ti,index-starts-at-one;
	};

	dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll4_m2_ck>;
		clock-mult = <2>;
		clock-div = <1>;
	};

	dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll4_m2x2_mul_ck>;
		ti,bit-shift = <0x1b>;
		reg = <0x0d00>;
		ti,set-bit-to-disable;
	};

	omap_96m_alwon_fck: omap_96m_alwon_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll4_m2x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll3_ck: dpll3_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,omap3-dpll-core-clock";
		clocks = <&sys_ck>, <&sys_ck>;
		reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
	};

	/* CM_CLKSEL1_EMU */
	clock@1140 {
		compatible = "ti,clksel";
		reg = <0x1140>;
		#clock-cells = <2>;
		#address-cells = <0>;

		dpll3_m3_ck: clock-dpll3-m3 {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "dpll3_m3_ck";
			clocks = <&dpll3_ck>;
			ti,bit-shift = <16>;
			ti,max-div = <31>;
			ti,index-starts-at-one;
		};

		dpll4_m6_ck: clock-dpll4-m6 {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "dpll4_m6_ck";
			clocks = <&dpll4_ck>;
			ti,bit-shift = <24>;
			ti,max-div = <63>;
			ti,index-starts-at-one;
		};

		emu_src_mux_ck: clock-emu-src-mux {
			#clock-cells = <0>;
			compatible = "ti,mux-clock";
			clock-output-names = "emu_src_mux_ck";
			clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
		};

		pclk_fck: clock-pclk-fck {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "pclk_fck";
			clocks = <&emu_src_ck>;
			ti,bit-shift = <8>;
			ti,max-div = <7>;
			ti,index-starts-at-one;
		};

		pclkx2_fck: clock-pclkx2-fck {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "pclkx2_fck";
			clocks = <&emu_src_ck>;
			ti,bit-shift = <6>;
			ti,max-div = <3>;
			ti,index-starts-at-one;
		};

		atclk_fck: clock-atclk-fck {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "atclk_fck";
			clocks = <&emu_src_ck>;
			ti,bit-shift = <4>;
			ti,max-div = <3>;
			ti,index-starts-at-one;
		};

		traceclk_src_fck: clock-traceclk-src-fck {
			#clock-cells = <0>;
			compatible = "ti,mux-clock";
			clock-output-names = "traceclk_src_fck";
			clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
			ti,bit-shift = <2>;
		};

		traceclk_fck: clock-traceclk-fck {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "traceclk_fck";
			clocks = <&traceclk_src_fck>;
			ti,bit-shift = <11>;
			ti,max-div = <7>;
			ti,index-starts-at-one;
		};
	};

	dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll3_m3_ck>;
		clock-mult = <2>;
		clock-div = <1>;
	};

	dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll3_m3x2_mul_ck>;
		ti,bit-shift = <0xc>;
		reg = <0x0d00>;
		ti,set-bit-to-disable;
	};

	emu_core_alwon_ck: emu_core_alwon_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll3_m3x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	sys_altclk: sys_altclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0x0>;
	};

	mcbsp_clks: mcbsp_clks {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0x0>;
	};

	core_ck: core_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll3_m2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	dpll1_fck: dpll1_fck@940 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&core_ck>;
		ti,bit-shift = <19>;
		ti,max-div = <7>;
		reg = <0x0940>;
		ti,index-starts-at-one;
	};

	dpll1_ck: dpll1_ck@904 {
		#clock-cells = <0>;
		compatible = "ti,omap3-dpll-clock";
		clocks = <&sys_ck>, <&dpll1_fck>;
		reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
	};

	dpll1_x2_ck: dpll1_x2_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll1_ck>;
		clock-mult = <2>;
		clock-div = <1>;
	};

	dpll1_x2m2_ck: dpll1_x2m2_ck@944 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll1_x2_ck>;
		ti,max-div = <31>;
		reg = <0x0944>;
		ti,index-starts-at-one;
	};

	cm_96m_fck: cm_96m_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_96m_alwon_fck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	/* CM_CLKSEL1_PLL */
	clock@d40 {
		compatible = "ti,clksel";
		reg = <0xd40>;
		#clock-cells = <2>;
		#address-cells = <0>;

		dpll3_m2_ck: clock-dpll3-m2 {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "dpll3_m2_ck";
			clocks = <&dpll3_ck>;
			ti,bit-shift = <27>;
			ti,max-div = <31>;
			ti,index-starts-at-one;
		};

		omap_96m_fck: clock-omap-96m-fck {
			#clock-cells = <0>;
			compatible = "ti,mux-clock";
			clock-output-names = "omap_96m_fck";
			clocks = <&cm_96m_fck>, <&sys_ck>;
			ti,bit-shift = <6>;
		};

		omap_54m_fck: clock-omap-54m-fck {
			#clock-cells = <0>;
			compatible = "ti,mux-clock";
			clock-output-names = "omap_54m_fck";
			clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
			ti,bit-shift = <5>;
		};

		omap_48m_fck: clock-omap-48m-fck {
			#clock-cells = <0>;
			compatible = "ti,mux-clock";
			clock-output-names = "omap_48m_fck";
			clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
			ti,bit-shift = <3>;
		};
	};

	/* CM_CLKSEL_DSS */
	clock@e40 {
		compatible = "ti,clksel";
		reg = <0xe40>;
		#clock-cells = <2>;
		#address-cells = <0>;

		dpll4_m3_ck: clock-dpll4-m3 {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "dpll4_m3_ck";
			clocks = <&dpll4_ck>;
			ti,bit-shift = <8>;
			ti,max-div = <32>;
			ti,index-starts-at-one;
		};

		dpll4_m4_ck: clock-dpll4-m4 {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "dpll4_m4_ck";
			clocks = <&dpll4_ck>;
			ti,max-div = <16>;
			ti,index-starts-at-one;
		};
	};

	dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll4_m3_ck>;
		clock-mult = <2>;
		clock-div = <1>;
	};

	dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll4_m3x2_mul_ck>;
		ti,bit-shift = <0x1c>;
		reg = <0x0d00>;
		ti,set-bit-to-disable;
	};

	cm_96m_d2_fck: cm_96m_d2_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&cm_96m_fck>;
		clock-mult = <1>;
		clock-div = <2>;
	};

	omap_12m_fck: omap_12m_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_48m_fck>;
		clock-mult = <1>;
		clock-div = <4>;
	};

	dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
		#clock-cells = <0>;
		compatible = "ti,fixed-factor-clock";
		clocks = <&dpll4_m4_ck>;
		ti,clock-mult = <2>;
		ti,clock-div = <1>;
		ti,set-rate-parent;
	};

	dpll4_m4x2_ck: dpll4_m4x2_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll4_m4x2_mul_ck>;
		ti,bit-shift = <0x1d>;
		reg = <0x0d00>;
		ti,set-bit-to-disable;
		ti,set-rate-parent;
	};

	dpll4_m5_ck: dpll4_m5_ck@f40 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&dpll4_ck>;
		ti,max-div = <63>;
		reg = <0x0f40>;
		ti,index-starts-at-one;
	};

	dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
		#clock-cells = <0>;
		compatible = "ti,fixed-factor-clock";
		clocks = <&dpll4_m5_ck>;
		ti,clock-mult = <2>;
		ti,clock-div = <1>;
		ti,set-rate-parent;
	};

	dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll4_m5x2_mul_ck>;
		ti,bit-shift = <0x1e>;
		reg = <0x0d00>;
		ti,set-bit-to-disable;
		ti,set-rate-parent;
	};

	dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll4_m6_ck>;
		clock-mult = <2>;
		clock-div = <1>;
	};

	dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
		#clock-cells = <0>;
		compatible = "ti,gate-clock";
		clocks = <&dpll4_m6x2_mul_ck>;
		ti,bit-shift = <0x1f>;
		reg = <0x0d00>;
		ti,set-bit-to-disable;
	};

	emu_per_alwon_ck: emu_per_alwon_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll4_m6x2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	/* CM_CLKOUT_CTRL */
	clock@d70 {
		compatible = "ti,clksel";
		reg = <0xd70>;
		#clock-cells = <2>;
		#address-cells = <0>;

		clkout2_src_gate_ck: clock-clkout2-src-gate {
			#clock-cells = <0>;
			compatible = "ti,composite-no-wait-gate-clock";
			clock-output-names = "clkout2_src_gate_ck";
			clocks = <&core_ck>;
			ti,bit-shift = <7>;
		};

		clkout2_src_mux_ck: clock-clkout2-src-mux {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "clkout2_src_mux_ck";
			clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
		};

		sys_clkout2: clock-sys-clkout2 {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "sys_clkout2";
			clocks = <&clkout2_src_ck>;
			ti,bit-shift = <3>;
			ti,max-div = <64>;
			ti,index-power-of-two;
		};
	};

	clkout2_src_ck: clkout2_src_ck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
	};

	mpu_ck: mpu_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&dpll1_x2m2_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	arm_fck: arm_fck@924 {
		#clock-cells = <0>;
		compatible = "ti,divider-clock";
		clocks = <&mpu_ck>;
		reg = <0x0924>;
		ti,max-div = <2>;
	};

	emu_mpu_alwon_ck: emu_mpu_alwon_ck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&mpu_ck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	/* CM_CLKSEL_CORE */
	clock@a40 {
		compatible = "ti,clksel";
		reg = <0xa40>;
		#clock-cells = <2>;
		#address-cells = <0>;

		l3_ick: clock-l3-ick {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "l3_ick";
			clocks = <&core_ck>;
			ti,max-div = <3>;
			ti,index-starts-at-one;
		};

		l4_ick: clock-l4-ick {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "l4_ick";
			clocks = <&l3_ick>;
			ti,bit-shift = <2>;
			ti,max-div = <3>;
			ti,index-starts-at-one;
		};

		gpt10_mux_fck: clock-gpt10-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "gpt10_mux_fck";
			clocks = <&omap_32k_fck>, <&sys_ck>;
			ti,bit-shift = <6>;
		};

		gpt11_mux_fck: clock-gpt11-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "gpt11_mux_fck";
			clocks = <&omap_32k_fck>, <&sys_ck>;
			ti,bit-shift = <7>;
		};
	};

	/* CM_CLKSEL_WKUP */
	clock@c40 {
		compatible = "ti,clksel";
		reg = <0xc40>;
		#clock-cells = <2>;
		#address-cells = <0>;

		rm_ick: clock-rm-ick {
			#clock-cells = <0>;
			compatible = "ti,divider-clock";
			clock-output-names = "rm_ick";
			clocks = <&l4_ick>;
			ti,bit-shift = <1>;
			ti,max-div = <3>;
			ti,index-starts-at-one;
		};

		gpt1_mux_fck: clock-gpt1-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "gpt1_mux_fck";
			clocks = <&omap_32k_fck>, <&sys_ck>;
		};
	};

	/* CM_FCLKEN1_CORE */
	clock@a00 {
		compatible = "ti,clksel";
		reg = <0xa00>;
		#clock-cells = <2>;
		#address-cells = <0>;

		gpt10_gate_fck: clock-gpt10-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "gpt10_gate_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <11>;
		};

		gpt11_gate_fck: clock-gpt11-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "gpt11_gate_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <12>;
		};

		mmchs2_fck: clock-mmchs2-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "mmchs2_fck";
			clocks = <&core_96m_fck>;
			ti,bit-shift = <25>;
		};

		mmchs1_fck: clock-mmchs1-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "mmchs1_fck";
			clocks = <&core_96m_fck>;
			ti,bit-shift = <24>;
		};

		i2c3_fck: clock-i2c3-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "i2c3_fck";
			clocks = <&core_96m_fck>;
			ti,bit-shift = <17>;
		};

		i2c2_fck: clock-i2c2-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "i2c2_fck";
			clocks = <&core_96m_fck>;
			ti,bit-shift = <16>;
		};

		i2c1_fck: clock-i2c1-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "i2c1_fck";
			clocks = <&core_96m_fck>;
			ti,bit-shift = <15>;
		};

		mcbsp5_gate_fck: clock-mcbsp5-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "mcbsp5_gate_fck";
			clocks = <&mcbsp_clks>;
			ti,bit-shift = <10>;
		};

		mcbsp1_gate_fck: clock-mcbsp1-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "mcbsp1_gate_fck";
			clocks = <&mcbsp_clks>;
			ti,bit-shift = <9>;
		};

		mcspi4_fck: clock-mcspi4-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "mcspi4_fck";
			clocks = <&core_48m_fck>;
			ti,bit-shift = <21>;
		};

		mcspi3_fck: clock-mcspi3-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "mcspi3_fck";
			clocks = <&core_48m_fck>;
			ti,bit-shift = <20>;
		};

		mcspi2_fck: clock-mcspi2-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "mcspi2_fck";
			clocks = <&core_48m_fck>;
			ti,bit-shift = <19>;
		};

		mcspi1_fck: clock-mcspi1-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "mcspi1_fck";
			clocks = <&core_48m_fck>;
			ti,bit-shift = <18>;
		};

		uart2_fck: clock-uart2-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "uart2_fck";
			clocks = <&core_48m_fck>;
			ti,bit-shift = <14>;
		};

		uart1_fck: clock-uart1-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "uart1_fck";
			clocks = <&core_48m_fck>;
			ti,bit-shift = <13>;
		};

		hdq_fck: clock-hdq-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "hdq_fck";
			clocks = <&core_12m_fck>;
			ti,bit-shift = <22>;
		};
	};

	gpt10_fck: gpt10_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
	};

	gpt11_fck: gpt11_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
	};

	core_96m_fck: core_96m_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_96m_fck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	core_48m_fck: core_48m_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_48m_fck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	core_12m_fck: core_12m_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_12m_fck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	core_l3_ick: core_l3_ick {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&l3_ick>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	/* CM_ICLKEN1_CORE */
	clock@a10 {
		compatible = "ti,clksel";
		reg = <0xa10>;
		#clock-cells = <2>;
		#address-cells = <0>;

		sdrc_ick: clock-sdrc-ick {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "sdrc_ick";
			clocks = <&core_l3_ick>;
			ti,bit-shift = <1>;
		};

		mmchs2_ick: clock-mmchs2-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mmchs2_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <25>;
		};

		mmchs1_ick: clock-mmchs1-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mmchs1_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <24>;
		};

		hdq_ick: clock-hdq-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "hdq_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <22>;
		};

		mcspi4_ick: clock-mcspi4-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mcspi4_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <21>;
		};

		mcspi3_ick: clock-mcspi3-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mcspi3_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <20>;
		};

		mcspi2_ick: clock-mcspi2-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mcspi2_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <19>;
		};

		mcspi1_ick: clock-mcspi1-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mcspi1_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <18>;
		};

		i2c3_ick: clock-i2c3-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "i2c3_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <17>;
		};

		i2c2_ick: clock-i2c2-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "i2c2_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <16>;
		};

		i2c1_ick: clock-i2c1-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "i2c1_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <15>;
		};

		uart2_ick: clock-uart2-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "uart2_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <14>;
		};

		uart1_ick: clock-uart1-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "uart1_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <13>;
		};

		gpt11_ick: clock-gpt11-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpt11_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <12>;
		};

		gpt10_ick: clock-gpt10-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpt10_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <11>;
		};

		mcbsp5_ick: clock-mcbsp5-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mcbsp5_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <10>;
		};

		mcbsp1_ick: clock-mcbsp1-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mcbsp1_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <9>;
		};

		omapctrl_ick: clock-omapctrl-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "omapctrl_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <6>;
		};

		aes2_ick: clock-aes2-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "aes2_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <28>;
		};

		sha12_ick: clock-sha12-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "sha12_ick";
			clocks = <&core_l4_ick>;
			ti,bit-shift = <27>;
		};
	};

	gpmc_fck: gpmc_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&core_l3_ick>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	core_l4_ick: core_l4_ick {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&l4_ick>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	/* CM_FCLKEN_DSS */
	clock@e00 {
		compatible = "ti,clksel";
		reg = <0xe00>;
		#clock-cells = <2>;
		#address-cells = <0>;

		dss_tv_fck: clock-dss-tv-fck {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "dss_tv_fck";
			clocks = <&omap_54m_fck>;
			ti,bit-shift = <2>;
		};

		dss_96m_fck: clock-dss-96m-fck {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "dss_96m_fck";
			clocks = <&omap_96m_fck>;
			ti,bit-shift = <2>;
		};

		dss2_alwon_fck: clock-dss2-alwon-fck {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "dss2_alwon_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <1>;
		};
	};

	dummy_ck: dummy_ck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	/* CM_FCLKEN_WKUP */
	clock@c00 {
		compatible = "ti,clksel";
		reg = <0xc00>;
		#clock-cells = <2>;
		#address-cells = <0>;

		gpt1_gate_fck: clock-gpt1-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "gpt1_gate_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <0>;
		};

		gpio1_dbck: clock-gpio1-dbck {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "gpio1_dbck";
			clocks = <&wkup_32k_fck>;
			ti,bit-shift = <3>;
		};

		wdt2_fck: clock-wdt2-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "wdt2_fck";
			clocks = <&wkup_32k_fck>;
			ti,bit-shift = <5>;
		};
	};

	gpt1_fck: gpt1_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
	};

	wkup_32k_fck: wkup_32k_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_32k_fck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	/* CM_ICLKEN_WKUP */
	clock@c10 {
		compatible = "ti,clksel";
		reg = <0xc10>;
		#clock-cells = <2>;
		#address-cells = <0>;

		wdt2_ick: clock-wdt2-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "wdt2_ick";
			clocks = <&wkup_l4_ick>;
			ti,bit-shift = <5>;
		};

		wdt1_ick: clock-wdt1-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "wdt1_ick";
			clocks = <&wkup_l4_ick>;
			ti,bit-shift = <4>;
		};

		gpio1_ick: clock-gpio1-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpio1_ick";
			clocks = <&wkup_l4_ick>;
			ti,bit-shift = <3>;
		};

		omap_32ksync_ick: clock-omap-32ksync-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "omap_32ksync_ick";
			clocks = <&wkup_l4_ick>;
			ti,bit-shift = <2>;
		};

		gpt12_ick: clock-gpt12-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpt12_ick";
			clocks = <&wkup_l4_ick>;
			ti,bit-shift = <1>;
		};

		gpt1_ick: clock-gpt1-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpt1_ick";
			clocks = <&wkup_l4_ick>;
			ti,bit-shift = <0>;
		};
	};

	per_96m_fck: per_96m_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_96m_alwon_fck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	per_48m_fck: per_48m_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_48m_fck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	/* CM_FCLKEN_PER */
	clock@1000 {
		compatible = "ti,clksel";
		reg = <0x1000>;
		#clock-cells = <2>;
		#address-cells = <0>;

		uart3_fck: clock-uart3-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "uart3_fck";
			clocks = <&per_48m_fck>;
			ti,bit-shift = <11>;
		};

		gpt2_gate_fck: clock-gpt2-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "gpt2_gate_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <3>;
		};

		gpt3_gate_fck: clock-gpt3-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "gpt3_gate_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <4>;
		};

		gpt4_gate_fck: clock-gpt4-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "gpt4_gate_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <5>;
		};

		gpt5_gate_fck: clock-gpt5-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "gpt5_gate_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <6>;
		};

		gpt6_gate_fck: clock-gpt6-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "gpt6_gate_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <7>;
		};

		gpt7_gate_fck: clock-gpt7-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "gpt7_gate_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <8>;
		};

		gpt8_gate_fck: clock-gpt8-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "gpt8_gate_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <9>;
		};

		gpt9_gate_fck: clock-gpt9-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "gpt9_gate_fck";
			clocks = <&sys_ck>;
			ti,bit-shift = <10>;
		};

		gpio6_dbck: clock-gpio6-dbck {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "gpio6_dbck";
			clocks = <&per_32k_alwon_fck>;
			ti,bit-shift = <17>;
		};

		gpio5_dbck: clock-gpio5-dbck {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "gpio5_dbck";
			clocks = <&per_32k_alwon_fck>;
			ti,bit-shift = <16>;
		};

		gpio4_dbck: clock-gpio4-dbck {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "gpio4_dbck";
			clocks = <&per_32k_alwon_fck>;
			ti,bit-shift = <15>;
		};

		gpio3_dbck: clock-gpio3-dbck {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "gpio3_dbck";
			clocks = <&per_32k_alwon_fck>;
			ti,bit-shift = <14>;
		};

		gpio2_dbck: clock-gpio2-dbck {
			#clock-cells = <0>;
			compatible = "ti,gate-clock";
			clock-output-names = "gpio2_dbck";
			clocks = <&per_32k_alwon_fck>;
			ti,bit-shift = <13>;
		};

		wdt3_fck: clock-wdt3-fck {
			#clock-cells = <0>;
			compatible = "ti,wait-gate-clock";
			clock-output-names = "wdt3_fck";
			clocks = <&per_32k_alwon_fck>;
			ti,bit-shift = <12>;
		};

		mcbsp2_gate_fck: clock-mcbsp2-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "mcbsp2_gate_fck";
			clocks = <&mcbsp_clks>;
			ti,bit-shift = <0>;
		};

		mcbsp3_gate_fck: clock-mcbsp3-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "mcbsp3_gate_fck";
			clocks = <&mcbsp_clks>;
			ti,bit-shift = <1>;
		};

		mcbsp4_gate_fck: clock-mcbsp4-gate-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-gate-clock";
			clock-output-names = "mcbsp4_gate_fck";
			clocks = <&mcbsp_clks>;
			ti,bit-shift = <2>;
		};
	};

	/* CM_CLKSEL_PER */
	clock@1040 {
		compatible = "ti,clksel";
		reg = <0x1040>;
		#clock-cells = <2>;
		#address-cells = <0>;

		gpt2_mux_fck: clock-gpt2-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "gpt2_mux_fck";
			clocks = <&omap_32k_fck>, <&sys_ck>;
		};

		gpt3_mux_fck: clock-gpt3-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "gpt3_mux_fck";
			clocks = <&omap_32k_fck>, <&sys_ck>;
			ti,bit-shift = <1>;
		};

		gpt4_mux_fck: clock-gpt4-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "gpt4_mux_fck";
			clocks = <&omap_32k_fck>, <&sys_ck>;
			ti,bit-shift = <2>;
		};

		gpt5_mux_fck: clock-gpt5-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "gpt5_mux_fck";
			clocks = <&omap_32k_fck>, <&sys_ck>;
			ti,bit-shift = <3>;
		};

		gpt6_mux_fck: clock-gpt6-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "gpt6_mux_fck";
			clocks = <&omap_32k_fck>, <&sys_ck>;
			ti,bit-shift = <4>;
		};

		gpt7_mux_fck: clock-gpt7-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "gpt7_mux_fck";
			clocks = <&omap_32k_fck>, <&sys_ck>;
			ti,bit-shift = <5>;
		};

		gpt8_mux_fck: clock-gpt8-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "gpt8_mux_fck";
			clocks = <&omap_32k_fck>, <&sys_ck>;
			ti,bit-shift = <6>;
		};

		gpt9_mux_fck: clock-gpt9-mux-fck {
			#clock-cells = <0>;
			compatible = "ti,composite-mux-clock";
			clock-output-names = "gpt9_mux_fck";
			clocks = <&omap_32k_fck>, <&sys_ck>;
			ti,bit-shift = <7>;
		};
	};

	gpt2_fck: gpt2_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
	};

	gpt3_fck: gpt3_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
	};

	gpt4_fck: gpt4_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
	};

	gpt5_fck: gpt5_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
	};

	gpt6_fck: gpt6_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
	};

	gpt7_fck: gpt7_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
	};

	gpt8_fck: gpt8_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
	};

	gpt9_fck: gpt9_fck {
		#clock-cells = <0>;
		compatible = "ti,composite-clock";
		clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
	};

	per_32k_alwon_fck: per_32k_alwon_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&omap_32k_fck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	per_l4_ick: per_l4_ick {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&l4_ick>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	/* CM_ICLKEN_PER */
	clock@1010 {
		compatible = "ti,clksel";
		reg = <0x1010>;
		#clock-cells = <2>;
		#address-cells = <0>;

		gpio6_ick: clock-gpio6-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpio6_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <17>;
		};

		gpio5_ick: clock-gpio5-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpio5_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <16>;
		};

		gpio4_ick: clock-gpio4-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpio4_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <15>;
		};

		gpio3_ick: clock-gpio3-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpio3_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <14>;
		};

		gpio2_ick: clock-gpio2-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpio2_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <13>;
		};

		wdt3_ick: clock-wdt3-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "wdt3_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <12>;
		};

		uart3_ick: clock-uart3-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "uart3_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <11>;
		};

		uart4_ick: clock-uart4-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "uart4_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <18>;
		};

		gpt9_ick: clock-gpt9-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpt9_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <10>;
		};

		gpt8_ick: clock-gpt8-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpt8_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <9>;
		};

		gpt7_ick: clock-gpt7-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpt7_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <8>;
		};

		gpt6_ick: clock-gpt6-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpt6_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <7>;
		};

		gpt5_ick: clock-gpt5-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpt5_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <6>;
		};

		gpt4_ick: clock-gpt4-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpt4_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <5>;
		};

		gpt3_ick: clock-gpt3-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpt3_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <4>;
		};

		gpt2_ick: clock-gpt2-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "gpt2_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <3>;
		};

		mcbsp2_ick: clock-mcbsp2-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mcbsp2_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <0>;
		};

		mcbsp3_ick: clock-mcbsp3-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mcbsp3_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <1>;
		};

		mcbsp4_ick: clock-mcbsp4-ick {
			#clock-cells = <0>;
			compatible = "ti,omap3-interface-clock";
			clock-output-names = "mcbsp4_ick";
			clocks = <&per_l4_ick>;
			ti,bit-shift = <2>;
		};
	};

	emu_src_ck: emu_src_ck {
		#clock-cells = <0>;
		compatible = "ti,clkdm-gate-clock";
		clocks = <&emu_src_mux_ck>;
	};

	secure_32k_fck: secure_32k_fck {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
	};

	gpt12_fck: gpt12_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&secure_32k_fck>;
		clock-mult = <1>;
		clock-div = <1>;
	};

	wdt1_fck: wdt1_fck {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&secure_32k_fck>;
		clock-mult = <1>;
		clock-div = <1>;
	};
};

&cm_clockdomains {
	core_l3_clkdm: core_l3_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&sdrc_ick>;
	};

	dpll3_clkdm: dpll3_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dpll3_ck>;
	};

	dpll1_clkdm: dpll1_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dpll1_ck>;
	};

	per_clkdm: per_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
			 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
			 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
			 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
			 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
			 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
			 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
			 <&mcbsp4_ick>;
	};

	emu_clkdm: emu_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&emu_src_ck>;
	};

	dpll4_clkdm: dpll4_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dpll4_ck>;
	};

	wkup_clkdm: wkup_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
			 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
			 <&gpt1_ick>;
	};

	dss_clkdm: dss_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
	};

	core_l4_clkdm: core_l4_clkdm {
		compatible = "ti,clockdomain";
		clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree Source for OMAP4/5 SoC CPU thermal
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 * Contact: Eduardo Valentin <eduardo.valentin@ti.com>
 */

#include <dt-bindings/thermal/thermal.h>

cpu_thermal: cpu_thermal {
	polling-delay-passive = <250>; /* milliseconds */
	polling-delay = <1000>; /* milliseconds */

			/* sensor       ID */
	thermal-sensors = <&bandgap     0>;

	cpu_trips: trips {
		cpu_alert0: cpu_alert {
			temperature = <100000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "passive";
		};
		cpu_crit: cpu_crit {
			temperature = <125000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "critical";
		};
	};

	cpu_cooling_maps: cooling-maps {
		map0 {
			trip = <&cpu_alert0>;
			cooling-device =
				<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;

#include "motorola-mapphone-common.dtsi"

/ {
	model = "Motorola Droid Bionic XT875";
	compatible = "motorola,droid-bionic", "ti,omap4430", "ti,omap4";
};

&keypad {
	keypad,num-rows = <8>;
	keypad,num-columns = <8>;
	linux,keymap = <
	MATRIX_KEY(5, 0, KEY_VOLUMEUP)
	MATRIX_KEY(3, 0, KEY_VOLUMEDOWN)
	>;
};

&i2c1 {
	led-controller@38 {
		compatible = "ti,lm3532";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x38>;

		enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;

		ramp-up-us = <1024>;
		ramp-down-us = <8193>;

		backlight_led: led@0 {
			reg = <0>;
			led-sources = <2>;
			ti,led-mode = <0>;
			label = ":backlight";
		};
	};
};

&i2c4 {
	kxtf9: accelerometer@f {
		compatible = "kionix,kxtf9";
		reg = <0x0f>;

		vdd-supply = <&vhvio>;

		interrupt-parent = <&gpio2>;
		interrupts = <2 IRQ_TYPE_EDGE_RISING>;

		rotation-matrix = "0", "-1", "0",
				  "1", "0", "0",
				  "0", "0", "1";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;

#include "motorola-mapphone-common.dtsi"

/ {
	gpio_keys {
		compatible = "gpio-keys";

		volume_down {
			label = "Volume Down";
			gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */
			linux,code = <KEY_VOLUMEDOWN>;
			linux,can-disable;
			/* Value above 7.95ms for no GPIO hardware debounce */
			debounce-interval = <10>;
		};

		/*
		 * We use pad 0x4a100116 abe_dmic_din3.gpio_122 as the irq instead
		 * of the gpio interrupt to avoid lost events in deeper idle states.
		*/
		slider {
			label = "Keypad Slide";
			interrupts-extended = <&omap4_pmx_core 0xd6>;
			gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */
			linux,input-type = <EV_SW>;
			linux,code = <SW_KEYPAD_SLIDE>;
			linux,can-disable;
			/* Value above 7.95ms for no GPIO hardware debounce */
			debounce-interval = <10>;
		};
	};
};

/ {
	model = "Motorola Droid 4 XT894";
	compatible = "motorola,droid4", "ti,omap4430", "ti,omap4";
};

&keypad {
	keypad,num-rows = <8>;
	keypad,num-columns = <8>;
	linux,keymap = <

	/* Row 1 */
	MATRIX_KEY(0, 2, KEY_1)
	MATRIX_KEY(0, 6, KEY_2)
	MATRIX_KEY(2, 3, KEY_3)
	MATRIX_KEY(0, 7, KEY_4)
	MATRIX_KEY(0, 4, KEY_5)
	MATRIX_KEY(5, 5, KEY_6)
	MATRIX_KEY(0, 1, KEY_7)
	MATRIX_KEY(0, 5, KEY_8)
	MATRIX_KEY(0, 0, KEY_9)
	MATRIX_KEY(1, 6, KEY_0)

	/* Row 2 */
	MATRIX_KEY(3, 4, KEY_APOSTROPHE)
	MATRIX_KEY(7, 6, KEY_Q)
	MATRIX_KEY(7, 7, KEY_W)
	MATRIX_KEY(7, 2, KEY_E)
	MATRIX_KEY(1, 0, KEY_R)
	MATRIX_KEY(4, 4, KEY_T)
	MATRIX_KEY(1, 2, KEY_Y)
	MATRIX_KEY(6, 7, KEY_U)
	MATRIX_KEY(2, 2, KEY_I)
	MATRIX_KEY(5, 6, KEY_O)
	MATRIX_KEY(3, 7, KEY_P)
	MATRIX_KEY(6, 5, KEY_BACKSPACE)

	/* Row 3 */
	MATRIX_KEY(5, 4, KEY_TAB)
	MATRIX_KEY(5, 7, KEY_A)
	MATRIX_KEY(2, 7, KEY_S)
	MATRIX_KEY(7, 0, KEY_D)
	MATRIX_KEY(2, 6, KEY_F)
	MATRIX_KEY(6, 2, KEY_G)
	MATRIX_KEY(6, 6, KEY_H)
	MATRIX_KEY(1, 4, KEY_J)
	MATRIX_KEY(3, 1, KEY_K)
	MATRIX_KEY(2, 1, KEY_L)
	MATRIX_KEY(4, 6, KEY_ENTER)

	/* Row 4 */
	MATRIX_KEY(3, 6, KEY_LEFTSHIFT)		/* KEY_CAPSLOCK */
	MATRIX_KEY(6, 1, KEY_Z)
	MATRIX_KEY(7, 4, KEY_X)
	MATRIX_KEY(5, 1, KEY_C)
	MATRIX_KEY(1, 7, KEY_V)
	MATRIX_KEY(2, 4, KEY_B)
	MATRIX_KEY(4, 1, KEY_N)
	MATRIX_KEY(1, 1, KEY_M)
	MATRIX_KEY(3, 5, KEY_COMMA)
	MATRIX_KEY(5, 2, KEY_DOT)
	MATRIX_KEY(6, 3, KEY_UP)
	MATRIX_KEY(7, 3, KEY_OK)

	/* Row 5 */
	MATRIX_KEY(2, 5, KEY_LEFTCTRL)		/* KEY_LEFTSHIFT */
	MATRIX_KEY(4, 5, KEY_LEFTALT)		/* SYM */
	MATRIX_KEY(6, 0, KEY_MINUS)
	MATRIX_KEY(4, 7, KEY_EQUAL)
	MATRIX_KEY(1, 5, KEY_SPACE)
	MATRIX_KEY(3, 2, KEY_SLASH)
	MATRIX_KEY(4, 3, KEY_LEFT)
	MATRIX_KEY(5, 3, KEY_DOWN)
	MATRIX_KEY(3, 3, KEY_RIGHT)

	/* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */
	MATRIX_KEY(5, 0, KEY_VOLUMEUP)
	>;
};

&i2c1 {
	led-controller@38 {
		compatible = "ti,lm3532";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x38>;

		enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;

		ramp-up-us = <1024>;
		ramp-down-us = <8193>;

		backlight_led: led@0 {
			reg = <0>;
			led-sources = <2>;
			ti,led-mode = <0>;
			label = ":backlight";
		};

		led@1 {
			reg = <1>;
			led-sources = <1>;
			ti,led-mode = <0>;
			label = ":kbd_backlight";
		};
	};
};

&i2c4 {
	lis3dh: accelerometer@18 {
		compatible = "st,lis3dh-accel";
		reg = <0x18>;

		vdd-supply = <&vhvio>;

		interrupt-parent = <&gpio2>;
		interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */

		rotation-matrix = "0", "-1", "0",
				  "1", "0", "0",
				  "0", "0", "1";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
 */
/dts-v1/;

#include "omap4-duovero.dtsi"

#include <dt-bindings/input/input.h>

/ {
	model = "OMAP4430 Gumstix Duovero on Parlor";
	compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";

	aliases {
		display0 = &hdmi0;
	};

	leds {
		compatible = "gpio-leds";
		led0 {
			label = "duovero:blue:led0";
			gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;	/* gpio_122 */
			linux,default-trigger = "heartbeat";
		};
	};

	gpio_keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		#size-cells = <0>;
		button0 {
			label = "button0";
			linux,code = <BTN_0>;
			gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;	/* gpio_121 */
			/* Value above 7.95ms for no GPIO hardware debounce */
			debounce-interval = <10>;
			wakeup-source;
		};
	};

	hdmi0: connector {
		compatible = "hdmi-connector";
		label = "hdmi";

		type = "d";

		hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;	/* gpio_63 */

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&hdmi_out>;
			};
		};
	};
};

&omap4_pmx_core {
	pinctrl-0 = <
			&led_pins
			&button_pins
			&smsc_pins
	>;

	led_pins: pinmux_led_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3)		/* abe_dmic_din3.gpio_122 */
		>;
	};

	button_pins: pinmux_button_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3)	/* abe_dmic_din2.gpio_121 */
		>;
	};

	i2c2_pins: pinmux_i2c2_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_scl */
			OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_sda */
		>;
	};

	i2c3_pins: pinmux_i2c3_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_scl */
			OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_sda */
		>;
	};

	smsc_pins: pinmux_smsc_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3)		/* gpmc_a20.gpio_44: IRQ */
			OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_a21.gpio_45: nReset */
			OMAP4_IOPAD(0x070, PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_a24.gpio_48: amdix enabled */
		>;
	};

	dss_hdmi_pins: pinmux_dss_hdmi_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x098, PIN_INPUT | MUX_MODE3)		/* hdmi_hpd.gpio_63 */
			OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0)		/* hdmi_cec.hdmi_cec */
			OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_ddc_scl.hdmi_ddc_scl */
			OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_ddc_sda.hdmi_ddc_sda */
		>;
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;

	clock-frequency = <400000>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;

	clock-frequency = <100000>;

	/* optional 1K EEPROM with revision information */
	eeprom@51 {
		compatible = "atmel,24c01";
		reg = <0x51>;
		pagesize = <8>;
	};
};

&mmc3 {
	status = "disabled";
};

#include "omap-gpmc-smsc911x.dtsi"

&gpmc {
	ranges = <5 0 0x2c000000 0x1000000>;			/* CS5 */

	ethernet@gpmc {
		reg = <5 0 0xff>;
		interrupt-parent = <&gpio2>;
		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;		/* gpio_44 */

		phy-mode = "mii";

		gpmc,cs-on-ns = <10>;
		gpmc,cs-rd-off-ns = <50>;
		gpmc,cs-wr-off-ns = <50>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <10>;
		gpmc,adv-wr-off-ns = <10>;
		gpmc,oe-on-ns = <15>;
		gpmc,oe-off-ns = <50>;
		gpmc,we-on-ns = <15>;
		gpmc,we-off-ns = <50>;
		gpmc,rd-cycle-ns = <50>;
		gpmc,wr-cycle-ns = <50>;
		gpmc,access-ns = <50>;
		gpmc,page-burst-access-ns = <0>;
		gpmc,bus-turnaround-ns = <35>;
		gpmc,cycle2cycle-delay-ns = <35>;
		gpmc,wr-data-mux-bus-ns = <35>;
		gpmc,wr-access-ns = <50>;

		gpmc,mux-add-data = <2>;
		gpmc,sync-read;
		gpmc,sync-write;
		gpmc,clk-activation-ns = <5>;
		gpmc,sync-clk-ps = <20000>;
	};
};

&dss {
	status = "okay";
};

&hdmi {
	status = "okay";
	vdda-supply = <&vdac>;

	pinctrl-names = "default";
	pinctrl-0 = <&dss_hdmi_pins>;

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&hdmi_connector_in>;
		};
	};
};

&uart3 {
	interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
			       &omap4_pmx_core OMAP4_UART3_RX>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
 */

#include "omap443x.dtsi"
#include "omap4-mcpdm.dtsi"

/ {
	model = "Gumstix Duovero";
	compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";

	chosen {
		stdout-path = &uart3;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>; /* 1 GB */
	};

	sound {
		compatible = "ti,abe-twl6040";
		ti,model = "DuoVero";

		ti,mclk-freq = <38400000>;

		ti,mcpdm = <&mcpdm>;

		ti,twl6040 = <&twl6040>;

		/* Audio routing */
		ti,audio-routing =
			"Headset Stereophone", "HSOL",
			"Headset Stereophone", "HSOR",
			"HSMIC", "Headset Mic",
			"Headset Mic", "Headset Mic Bias";
	};

	/* HS USB Host PHY on PORT 1 */
	hsusb1_phy: hsusb1_phy {
		compatible = "usb-nop-xceiv";
		reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;	/* gpio_62 */
		#phy-cells = <0>;

		pinctrl-names = "default";
		pinctrl-0 = <&hsusb1phy_pins>;

		clocks = <&auxclk3_ck>;
		clock-names = "main_clk";
		clock-frequency = <19200000>;
	};

	/* regulator for w2cbw0015 on sdio5 */
	w2cbw0015_vmmc: w2cbw0015_vmmc {
		pinctrl-names = "default";
		pinctrl-0 = <&w2cbw0015_pins>;
		compatible = "regulator-fixed";
		regulator-name = "w2cbw0015";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&gpio2 11 GPIO_ACTIVE_LOW>;		/* gpio_43 */
		startup-delay-us = <70000>;
		enable-active-high;
		regulator-boot-on;
	};
};

&omap4_pmx_core {
	pinctrl-names = "default";
	pinctrl-0 = <
			&twl6040_pins
			&hsusbb1_pins
	>;

	twl6040_pins: pinmux_twl6040_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE3)		/* usbb2_ulpitll_nxt.gpio_160 */
			OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0)		/* sys_nirq2.sys_nirq2 */
		>;
	};

	mcbsp1_pins: pinmux_mcbsp1_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0)		/* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
			OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp1_dr.abe_mcbsp1_dr */
			OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* abe_mcbsp1_dx.abe_mcbsp1_dx */
			OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0)		/* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
		>;
	};

	hsusbb1_pins: pinmux_hsusbb1_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
			OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4)		/* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
			OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
			OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
			OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
			OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
			OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
			OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
			OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
			OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
			OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
			OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4)	/* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
		>;
	};

	hsusb1phy_pins: pinmux_hsusb1phy_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x08c, PIN_OUTPUT | MUX_MODE3)		/* gpmc_wait1.gpio_62 */
		>;
	};

	w2cbw0015_pins: pinmux_w2cbw0015_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3)		/* gpmc_a19.gpio_43 */
			OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3)		/* gpmc_ncs3.gpio_53 */
		>;
	};

	i2c1_pins: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_scl */
			OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_sda */
		>;
	};

	i2c4_pins: pinmux_i2c4_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_scl */
			OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_sda */
		>;
	};

	mmc1_pins: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_clk */
			OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmcc1_cmd */
			OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmcc1_dat0 */
			OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat1 */
			OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat2 */
			OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_dat3 */
		>;
	};

	mmc5_pins: pinmux_mmc5_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc5_clk */
			OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmcc5_cmd */
			OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmcc5_dat0 */
			OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc5_dat1 */
			OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc5_dat2 */
			OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc5_dat3 */
		>;
	};
};

/* PMIC */
&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;

	clock-frequency = <400000>;

	twl: twl@48 {
		reg = <0x48>;
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;		/* IRQ_SYS_1N cascaded to gic */
	};

	twl6040: twl@4b {
		compatible = "ti,twl6040";
		#clock-cells = <0>;
		reg = <0x4b>;
		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;		/* IRQ_SYS_2N cascaded to gic */
		ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>;		/* gpio_160 */

		vio-supply = <&v1v8>;
		v2v1-supply = <&v2v1>;
		enable-active-high;
	};
};

#include "twl6030.dtsi"
#include "twl6030_omap4.dtsi"

/* on-board bluetooth / WiFi module */
&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins>;

	clock-frequency = <400000>;
};

&mcbsp1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcbsp1_pins>;
	status = "okay";
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins>;

	vmmc-supply = <&vmmc>;
	ti,bus-width = <4>;
	ti,non-removable;		/* FIXME: use PMIC_MMC detect */
};

&mmc2 {
	status = "disabled";
};

/* mmc3 is available to the expansion board */

&mmc4 {
	status = "disabled";
};

/* on-board WiFi module */
&mmc5 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc5_pins>;

	vmmc-supply = <&w2cbw0015_vmmc>;
	ti,bus-width = <4>;
	ti,non-removable;
	cap-power-off-card;
	keep-power-in-suspend;
};

&twl_usb_comparator {
	usb-supply = <&vusb>;
};

&usb_otg_hs {
	interface-type = <1>;
	mode = <3>;
	power = <50>;
};

&usbhshost {
	port1-mode = "ehci-phy";
};

&usbhsehci {
	phys = <&hsusb1_phy>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
 */
/dts-v1/;

#include "omap443x.dtsi"

/ {
	model = "Amazon Kindle Fire (first generation)";
	compatible = "amazon,omap4-kc1", "ti,omap4430", "ti,omap4";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>; /* 512 MB */
	};

	led-controller {
		compatible = "pwm-leds";

		led-1 {
			label = "green";
			pwms = <&twl_pwm 0 7812500>;
			max-brightness = <127>;
		};

		led-2 {
			label = "orange";
			pwms = <&twl_pwm 1 7812500>;
			max-brightness = <127>;
		};
	};
};

&omap4_pmx_core {
	pinctrl-names = "default";

	uart3_pins: pinmux_uart3_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0)		/* uart3_rx_irrx */
			OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0)		/* uart3_tx_irtx */
		>;
	};

	i2c1_pins: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_scl */
			OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c1_sda */
		>;
	};

	i2c2_pins: pinmux_i2c2_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_scl */
			OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c2_sda */
		>;
	};

	i2c3_pins: pinmux_i2c3_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_scl */
			OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c3_sda */
		>;
	};

	i2c4_pins: pinmux_i2c4_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_scl */
			OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c4_sda */
		>;
	};

	mmc2_pins: pinmux_mmc2_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat0 */
			OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat1 */
			OMAP4_IOPAD(0x044, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat2 */
			OMAP4_IOPAD(0x046, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat3 */
			OMAP4_IOPAD(0x048, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat4 */
			OMAP4_IOPAD(0x04a, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat5 */
			OMAP4_IOPAD(0x04c, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat6 */
			OMAP4_IOPAD(0x04e, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_dat7 */
			OMAP4_IOPAD(0x082, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_clk */
			OMAP4_IOPAD(0x084, PIN_INPUT_PULLUP | MUX_MODE1)	/* sdmmc2_cmd */
		>;
	};

	usb_otg_hs_pins: pinmux_usb_otg_hs_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* usba0_otg_ce */
			OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0)		/* usba0_otg_dp */
			OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0)		/* usba0_otg_dm */
		>;
	};
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_pins>;

	interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
			       &omap4_pmx_core OMAP4_UART3_RX>;
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;

	clock-frequency = <400000>;

	twl: twl@48 {
		reg = <0x48>;
		/* IRQ# = 7 */
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */

		twl_power: power {
			compatible = "ti,twl6030-power";
			ti,system-power-controller;
		};
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;

	clock-frequency = <400000>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;

	clock-frequency = <400000>;
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins>;

	clock-frequency = <400000>;
};

&mmc1 {
	status = "disabled";
};

&mmc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins>;

	vmmc-supply = <&vaux1>;
	ti,non-removable;
	bus-width = <8>;
};

&mmc3 {
	status = "disabled";
};

&mmc4 {
	status = "disabled";
};

&usb_otg_hs {
	pinctrl-names = "default";
	pinctrl-0 = <&usb_otg_hs_pins>;

	interface-type = <1>;
	mode = <3>;
	power = <50>;
};

#include "twl6030.dtsi"
#include "twl6030_omap4.dtsi"

&twl_usb_comparator {
	usb-supply = <&vusb>;
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Common omap4 mcpdm configuration
 *
 * Only include this file if your board has pdmclk wired from the
 * pmic to ABE as mcpdm uses an external clock for the module.
 */

&omap4_pmx_core {
	mcpdm_pins: pinmux_mcpdm_pins {
		pinctrl-single,pins = <
		/* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */
		OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)

		/* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */
		OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)

		/* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */
		OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP   | MUX_MODE0)

		/* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */
		OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)

		/* 0x4a10010e abe_clks.abe_clks ah26 */
		OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)
		>;
	};
};

&mcpdm_module {
	/*
	 * McPDM pads must be muxed at the interconnect target module
	 * level as the module on the SoC needs external clock from
	 * the PMIC
	 */
	pinctrl-names = "default";
	pinctrl-0 = <&mcpdm_pins>;
	status = "okay";
};

&mcpdm {
	clocks = <&twl6040>;
	clock-names = "pdmclk";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 */
/dts-v1/;

#include "omap443x.dtsi"
#include "omap4-panda-common.dtsi"

/* Pandaboard Rev A4+ have external pullups on SCL & SDA */
&dss_hdmi_pins {
	pinctrl-single,pins = <
		OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0)		/* hdmi_cec.hdmi_cec */
		OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0)		/* hdmi_scl.hdmi_scl */
		OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
		>;
};