code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/vexpress-config.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Versatile Express configuration bus bindings

maintainers:
  - Andre Przywara <andre.przywara@arm.com>

description:
  This is a system control register block, acting as a bridge to the
  platform's configuration bus via "system control" interface, addressing
  devices with site number, position in the board stack, config controller,
  function and device numbers - see motherboard's TRM for more details.

properties:
  compatible:
    const: arm,vexpress,config-bus

  arm,vexpress,config-bridge:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the sysreg node.

  muxfpga:
    type: object
    properties:
      compatible:
        const: arm,vexpress-muxfpga

      arm,vexpress-sysreg,func:
        description: FPGA specifier
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - const: 7
          - description: device number

    additionalProperties: false
    required:
      - compatible
      - arm,vexpress-sysreg,func

  shutdown:
    type: object
    properties:
      compatible:
        const: arm,vexpress-shutdown

      arm,vexpress-sysreg,func:
        description: shutdown identifier
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - const: 8
          - description: device number

    additionalProperties: false
    required:
      - compatible
      - arm,vexpress-sysreg,func

  reboot:
    type: object
    properties:
      compatible:
        const: arm,vexpress-reboot

      arm,vexpress-sysreg,func:
        description: reboot identifier
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - const: 9
          - description: device number

    additionalProperties: false
    required:
      - compatible
      - arm,vexpress-sysreg,func

  dvimode:
    type: object
    properties:
      compatible:
        const: arm,vexpress-dvimode

      arm,vexpress-sysreg,func:
        description: DVI mode identifier
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - const: 11
          - description: device number

    additionalProperties: false
    required:
      - compatible
      - arm,vexpress-sysreg,func

additionalProperties: false

required:
  - compatible
  - arm,vexpress,config-bridge

patternProperties:
  'clk[0-9]*$':
    type: object
    description:
      clocks

    properties:
      compatible:
        const: arm,vexpress-osc

      arm,vexpress-sysreg,func:
        description: clock specifier
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - const: 1
          - description: clock number

      freq-range:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - description: minimal clock frequency
          - description: maximum clock frequency

      "#clock-cells":
        const: 0

      clock-output-names:
        maxItems: 1

    additionalProperties: false
    required:
      - compatible
      - arm,vexpress-sysreg,func
      - "#clock-cells"

  "^volt-.+$":
    $ref: /schemas/regulator/regulator.yaml#
    properties:
      compatible:
        const: arm,vexpress-volt

      arm,vexpress-sysreg,func:
        description: regulator specifier
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - const: 2
          - description: device number

      label:
        maxItems: 1

    unevaluatedProperties: false
    required:
      - compatible
      - arm,vexpress-sysreg,func

  "^amp-.+$":
    type: object
    properties:
      compatible:
        const: arm,vexpress-amp

      arm,vexpress-sysreg,func:
        description: current sensor identifier
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - const: 3
          - description: device number

      label:
        maxItems: 1

    additionalProperties: false
    required:
      - compatible
      - arm,vexpress-sysreg,func

  "^temp-.+$":
    type: object
    properties:
      compatible:
        const: arm,vexpress-temp

      arm,vexpress-sysreg,func:
        description: temperature sensor identifier
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - const: 4
          - description: device number

      label:
        maxItems: 1

    additionalProperties: false
    required:
      - compatible
      - arm,vexpress-sysreg,func

  "^reset[0-9]*$":
    type: object
    properties:
      compatible:
        const: arm,vexpress-reset

      arm,vexpress-sysreg,func:
        description: reset specifier
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - const: 5
          - description: reset device number

    additionalProperties: false
    required:
      - compatible
      - arm,vexpress-sysreg,func

  "^power-.+$":
    type: object
    properties:
      compatible:
        const: arm,vexpress-power

      arm,vexpress-sysreg,func:
        description: power sensor identifier
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - const: 12
          - description: device number

      label:
        maxItems: 1

    additionalProperties: false
    required:
      - compatible
      - arm,vexpress-sysreg,func

  "^energy(-.+)?$":
    type: object
    properties:
      compatible:
        const: arm,vexpress-energy

      arm,vexpress-sysreg,func:
        description: energy sensor identifier
        $ref: /schemas/types.yaml#/definitions/uint32-array
        oneOf:
          - items:
              - const: 13
              - description: device number
          - items:
              - const: 13
              - description: device number
              - const: 13
              - description: second device number

      label:
        maxItems: 1

    additionalProperties: false
    required:
      - compatible
      - arm,vexpress-sysreg,func

examples:
  - |
    mcc {
        compatible = "arm,vexpress,config-bus";
        arm,vexpress,config-bridge = <&v2m_sysreg>;

        clk0 {
            compatible = "arm,vexpress-osc";
            arm,vexpress-sysreg,func = <1 0>;
            #clock-cells = <0>;
        };

        energy {
            compatible = "arm,vexpress-energy";
            arm,vexpress-sysreg,func = <13 0>, <13 1>;
        };
    };


code:
ARM Versatile Express Serial Configuration Controller
-----------------------------------------------------

Test chips for ARM Versatile Express platform implement SCC (Serial
Configuration Controller) interface, used to set initial conditions
for the test chip.

In some cases its registers are also mapped in normal address space
and can be used to obtain runtime information about the chip internals
(like silicon temperature sensors) and as interface to other subsystems
like platform configuration control and power management.

Required properties:

- compatible value: "arm,vexpress-scc,<model>", "arm,vexpress-scc";
		    where <model> is the full tile model name (as used
		    in the tile's Technical Reference Manual),
		    eg. for Coretile Express A15x2 A7x3 (V2P-CA15_A7):
	compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";

Optional properties:

- reg: when the SCC is memory mapped, physical address and size of the
       registers window
- interrupts: when the SCC can generate a system-level interrupt

Example:

	scc@7fff0000 {
		compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
		reg = <0 0x7fff0000 0 0x1000>;
		interrupts = <0 95 4>;
	};

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/vexpress-sysreg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Versatile Express system registers bindings

maintainers:
  - Andre Przywara <andre.przywara@arm.com>

description:
  This is a system control registers block, providing multiple low level
  platform functions like board detection and identification, software
  interrupt generation, MMC and NOR Flash control, etc.

properties:
  compatible:
    const: arm,vexpress-sysreg

  reg:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  ranges: true

  gpio-controller:
    deprecated: true

  "#gpio-cells":
    deprecated: true
    const: 2

additionalProperties: false

patternProperties:
  '^gpio@[0-9a-f]+$':
    type: object
    additionalProperties: false
    description:
      GPIO children

    properties:
      compatible:
        enum:
          - arm,vexpress-sysreg,sys_led
          - arm,vexpress-sysreg,sys_mci
          - arm,vexpress-sysreg,sys_flash

      gpio-controller: true

      "#gpio-cells":
        const: 2
        description: |
          The first cell is the function number:
          for sys_led : 0..7 = LED 0..7
          for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT
          for sys_flash : 0 = NOR FLASH WPn
          The second cell can take standard GPIO flags.

      reg:
        maxItems: 1

    required:
      - compatible
      - reg
      - gpio-controller
      - "#gpio-cells"

required:
  - compatible
  - reg

examples:
  - |
    sysreg@0 {
        compatible = "arm,vexpress-sysreg";
        reg = <0x00000 0x1000>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0 0x1000>;

        v2m_led_gpios: gpio@8 {
            compatible = "arm,vexpress-sysreg,sys_led";
            reg = <0x008 4>;
            gpio-controller;
            #gpio-cells = <2>;
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/vt8500.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: VIA/Wondermedia VT8500 Platforms

maintainers:
  - Tony Prisk <linux@prisktech.co.nz>
description: test

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - via,vt8500
          - wm,wm8505
          - wm,wm8650
          - wm,wm8750
          - wm,wm8850

additionalProperties: true


code:
VIA/Wondermedia VT8500 Power Management Controller
-----------------------------------------------------

Required properties:
- compatible : "via,vt8500-pmc"
- reg : Should contain 1 register ranges(address and length)

Example:

	pmc@d8130000 {
		compatible = "via,vt8500-pmc";
		reg = <0xd8130000 0x1000>;
	};


code:
* Xen hypervisor device tree bindings

Xen ARM virtual platforms shall have a top-level "hypervisor" node with
the following properties:

- compatible:
	compatible = "xen,xen-<version>", "xen,xen";
  where <version> is the version of the Xen ABI of the platform.

- reg: specifies the base physical address and size of the regions in memory
  where the special resources should be mapped to, using an HYPERVISOR_memory_op
  hypercall.
  Region 0 is reserved for mapping grant table, it must be always present.
  The memory region is large enough to map the whole grant table (it is larger
  or equal to gnttab_max_grant_frames()).
  Regions 1...N are extended regions (unused address space) for mapping foreign
  GFNs and grants, they might be absent if there is nothing to expose.

- interrupts: the interrupt used by Xen to inject event notifications.
  A GIC node is also required.

To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node
under /hypervisor with following parameters:

________________________________________________________________________________
Name                      | Size   | Description
================================================================================
xen,uefi-system-table     | 64-bit | Guest physical address of the UEFI System
			  |	   | Table.
--------------------------------------------------------------------------------
xen,uefi-mmap-start       | 64-bit | Guest physical address of the UEFI memory
			  |	   | map.
--------------------------------------------------------------------------------
xen,uefi-mmap-size        | 32-bit | Size in bytes of the UEFI memory map
                          |        | pointed to in previous entry.
--------------------------------------------------------------------------------
xen,uefi-mmap-desc-size   | 32-bit | Size in bytes of each entry in the UEFI
                          |        | memory map.
--------------------------------------------------------------------------------
xen,uefi-mmap-desc-ver    | 32-bit | Version of the mmap descriptor format.
--------------------------------------------------------------------------------

Example (assuming #address-cells = <2> and #size-cells = <2>):

hypervisor {
	compatible = "xen,xen-4.3", "xen,xen";
	reg = <0 0xb0000000 0 0x20000>;
	interrupts = <1 15 0xf08>;
	uefi {
		xen,uefi-system-table = <0xXXXXXXXX>;
		xen,uefi-mmap-start = <0xXXXXXXXX>;
		xen,uefi-mmap-size = <0xXXXXXXXX>;
		xen,uefi-mmap-desc-size = <0xXXXXXXXX>;
		xen,uefi-mmap-desc-ver = <0xXXXXXXXX>;
        };
};

The format and meaning of the "xen,uefi-*" parameters are similar to those in
Documentation/arm/uefi.rst, which are provided by the regular UEFI stub. However
they differ because they are provided by the Xen hypervisor, together with a set
of UEFI runtime services implemented via hypercalls, see
http://xenbits.xen.org/docs/unstable/hypercall/x86_64/include,public,platform.h.html.


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/xilinx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Zynq Platforms

maintainers:
  - Michal Simek <michal.simek@xilinx.com>

description: |
  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - items:
          - enum:
              - adapteva,parallella
              - digilent,zynq-zybo
              - digilent,zynq-zybo-z7
              - ebang,ebaz4205
              - myir,zynq-zturn-v5
              - myir,zynq-zturn
              - xlnx,zynq-cc108
              - xlnx,zynq-zc702
              - xlnx,zynq-zc706
              - xlnx,zynq-zc770-xm010
              - xlnx,zynq-zc770-xm011
              - xlnx,zynq-zc770-xm012
              - xlnx,zynq-zc770-xm013
          - const: xlnx,zynq-7000

      - items:
          - const: avnet,zynq-microzed
          - const: xlnx,zynq-microzed
          - const: xlnx,zynq-7000

      - items:
          - const: avnet,zynq-zed
          - const: xlnx,zynq-zed
          - const: xlnx,zynq-7000

      - items:
          - enum:
              - xlnx,zynqmp-zc1751
          - const: xlnx,zynqmp

      - description: Xilinx internal board zc1232
        items:
          - const: xlnx,zynqmp-zc1232-revA
          - const: xlnx,zynqmp-zc1232
          - const: xlnx,zynqmp

      - description: Xilinx internal board zc1254
        items:
          - const: xlnx,zynqmp-zc1254-revA
          - const: xlnx,zynqmp-zc1254
          - const: xlnx,zynqmp

      - description: Xilinx internal board zc1275
        items:
          - const: xlnx,zynqmp-zc1275-revA
          - const: xlnx,zynqmp-zc1275
          - const: xlnx,zynqmp

      - description: Xilinx 96boards compatible board zcu100
        items:
          - const: xlnx,zynqmp-zcu100-revC
          - const: xlnx,zynqmp-zcu100
          - const: xlnx,zynqmp

      - description: Xilinx 96boards compatible board Ultra96
        items:
          - const: avnet,ultra96-rev1
          - const: avnet,ultra96
          - const: xlnx,zynqmp-zcu100-revC
          - const: xlnx,zynqmp-zcu100
          - const: xlnx,zynqmp

      - description: Xilinx evaluation board zcu102
        items:
          - enum:
              - xlnx,zynqmp-zcu102-revA
              - xlnx,zynqmp-zcu102-revB
              - xlnx,zynqmp-zcu102-rev1.0
              - xlnx,zynqmp-zcu102-rev1.1
          - const: xlnx,zynqmp-zcu102
          - const: xlnx,zynqmp

      - description: Xilinx evaluation board zcu104
        items:
          - enum:
              - xlnx,zynqmp-zcu104-revA
              - xlnx,zynqmp-zcu104-revC
              - xlnx,zynqmp-zcu104-rev1.0
          - const: xlnx,zynqmp-zcu104
          - const: xlnx,zynqmp

      - description: Xilinx evaluation board zcu106
        items:
          - enum:
              - xlnx,zynqmp-zcu106-revA
              - xlnx,zynqmp-zcu106-rev1.0
          - const: xlnx,zynqmp-zcu106
          - const: xlnx,zynqmp

      - description: Xilinx evaluation board zcu111
        items:
          - enum:
              - xlnx,zynqmp-zcu111-revA
              - xlnx,zynqmp-zcu111-rev1.0
          - const: xlnx,zynqmp-zcu111
          - const: xlnx,zynqmp

      - description: Xilinx Kria SOMs
        items:
          - const: xlnx,zynqmp-sm-k26-rev1
          - const: xlnx,zynqmp-sm-k26-revB
          - const: xlnx,zynqmp-sm-k26-revA
          - const: xlnx,zynqmp-sm-k26
          - const: xlnx,zynqmp

      - description: Xilinx Kria SOMs (starter)
        items:
          - const: xlnx,zynqmp-smk-k26-rev1
          - const: xlnx,zynqmp-smk-k26-revB
          - const: xlnx,zynqmp-smk-k26-revA
          - const: xlnx,zynqmp-smk-k26
          - const: xlnx,zynqmp

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/ahci-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common Properties for Serial ATA AHCI controllers

maintainers:
  - Hans de Goede <hdegoede@redhat.com>
  - Damien Le Moal <damien.lemoal@opensource.wdc.com>

description:
  This document defines device tree properties for a common AHCI SATA
  controller implementation. It's hardware interface is supposed to
  conform to the technical standard defined by Intel (see Serial ATA
  Advanced Host Controller Interface specification for details). The
  document doesn't constitute a DT-node binding by itself but merely
  defines a set of common properties for the AHCI-compatible devices.

select: false

allOf:
  - $ref: sata-common.yaml#

properties:
  reg:
    description:
      Generic AHCI registers space conforming to the Serial ATA AHCI
      specification.

  reg-names:
    description: CSR space IDs
    contains:
      const: ahci

  interrupts:
    description:
      Generic AHCI state change interrupt. Can be implemented either as a
      single line attached to the controller or as a set of the signals
      indicating the particular port events.
    minItems: 1
    maxItems: 32

  ahci-supply:
    description: Power regulator for AHCI controller

  target-supply:
    description: Power regulator for SATA target device

  phy-supply:
    description: Power regulator for SATA PHY

  phys:
    description: Reference to the SATA PHY node
    maxItems: 1

  phy-names:
    const: sata-phy

  hba-cap:
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description:
      Bitfield of the HBA generic platform capabilities like Staggered
      Spin-up or Mechanical Presence Switch support. It can be used to
      appropriately initialize the HWinit fields of the HBA CAP register
      in case if the system firmware hasn't done it.

  ports-implemented:
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description:
      Mask that indicates which ports the HBA supports. Useful if PI is not
      programmed by the BIOS, which is true for some embedded SoC's.

patternProperties:
  "^sata-port@[0-9a-f]+$":
    $ref: '#/$defs/ahci-port'
    description:
      It is optionally possible to describe the ports as sub-nodes so
      to enable each port independently when dealing with multiple PHYs.

required:
  - reg
  - interrupts

additionalProperties: true

$defs:
  ahci-port:
    $ref: /schemas/ata/sata-common.yaml#/$defs/sata-port

    properties:
      reg:
        description:
          AHCI SATA port identifier. By design AHCI controller can't have
          more than 32 ports due to the CAP.NP fields and PI register size
          constraints.
        minimum: 0
        maximum: 31

      phys:
        description: Individual AHCI SATA port PHY
        maxItems: 1

      phy-names:
        description: AHCI SATA port PHY ID
        const: sata-phy

      target-supply:
        description: Power regulator for SATA port target device

      hba-port-cap:
        $ref: '/schemas/types.yaml#/definitions/uint32'
        description:
          Bitfield of the HBA port-specific platform capabilities like Hot
          plugging, eSATA, FIS-based Switching, etc (see AHCI specification
          for details). It can be used to initialize the HWinit fields of
          the PxCMD register in case if the system firmware hasn't done it.

    required:
      - reg

...


code:
Device tree binding for the TI DA850 AHCI SATA Controller
---------------------------------------------------------

Required properties:
  - compatible: must be "ti,da850-ahci"
  - reg: physical base addresses and sizes of the two register regions
         used by the controller: the register map as defined by the
         AHCI 1.1 standard and the Power Down Control Register (PWRDN)
         for enabling/disabling the SATA clock receiver
  - interrupts: interrupt specifier (refer to the interrupt binding)

Example:

	sata: sata@218000 {
		compatible = "ti,da850-ahci";
		reg = <0x218000 0x2000>, <0x22c018 0x4>;
		interrupts = <67>;
	};


code:
Device tree binding for the TI DM816 AHCI SATA Controller
---------------------------------------------------------

Required properties:
  - compatible: must be "ti,dm816-ahci"
  - reg: physical base address and size of the register region used by
         the controller (as defined by the AHCI 1.1 standard)
  - interrupts: interrupt specifier (refer to the interrupt binding)
  - clocks: list of phandle and clock specifier pairs (or only
            phandles for clock providers with '0' defined for
            #clock-cells); two clocks must be specified: the functional
            clock and an external reference clock

Example:

	sata: sata@4a140000 {
		compatible = "ti,dm816-ahci";
		reg = <0x4a140000 0x10000>;
		interrupts = <16>;
		clocks = <&sysclk5_ck>, <&sata_refclk>;
	};


code:
Binding for Freescale QorIQ AHCI SATA Controller

Required properties:
  - reg: Physical base address and size of the controller's register area.
  - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
    chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc.
  - clocks: Input clock specifier. Refer to common clock bindings.
  - interrupts: Interrupt specifier. Refer to interrupt binding.

Optional properties:
  - dma-coherent: Enable AHCI coherent DMA operation.
  - reg-names: register area names when there are more than 1 register area.

Examples:
	sata@3200000 {
		compatible = "fsl,ls1021a-ahci";
		reg = <0x0 0x3200000 0x0 0x10000>;
		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&platform_clk 1>;
		dma-coherent;
	};


code:
MediaTek Serial ATA controller

Required properties:
 - compatible	   : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
		     When using "mediatek,mtk-ahci" compatible strings, you
		     need SoC specific ones in addition, one of:
		     - "mediatek,mt7622-ahci"
 - reg		   : Physical base addresses and length of register sets.
 - interrupts	   : Interrupt associated with the SATA device.
 - interrupt-names : Associated name must be: "hostc".
 - clocks	   : A list of phandle and clock specifier pairs, one for each
		     entry in clock-names.
 - clock-names	   : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
 - phys		   : A phandle and PHY specifier pair for the PHY port.
 - phy-names	   : Associated name must be: "sata-phy".
 - ports-implemented : See ./ahci-platform.txt for details.

Optional properties:
 - power-domains   : A phandle and power domain specifier pair to the power
		     domain which is responsible for collapsing and restoring
		     power to the peripheral.
 - resets	   : Must contain an entry for each entry in reset-names.
		     See ../reset/reset.txt for details.
 - reset-names	   : Associated names must be: "axi", "sw", "reg".
 - mediatek,phy-mode : A phandle to the system controller, used to enable
		       SATA function.

Example:

	sata: sata@1a200000 {
		compatible = "mediatek,mt7622-ahci",
			     "mediatek,mtk-ahci";
		reg = <0 0x1a200000 0 0x1100>;
		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hostc";
		clocks = <&pciesys CLK_SATA_AHB_EN>,
			 <&pciesys CLK_SATA_AXI_EN>,
			 <&pciesys CLK_SATA_ASIC_EN>,
			 <&pciesys CLK_SATA_RBC_EN>,
			 <&pciesys CLK_SATA_PM_EN>;
		clock-names = "ahb", "axi", "asic", "rbc", "pm";
		phys = <&u3port1 PHY_TYPE_SATA>;
		phy-names = "sata-phy";
		ports-implemented = <0x1>;
		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
		resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
			 <&pciesys MT7622_SATA_PHY_SW_RST>,
			 <&pciesys MT7622_SATA_PHY_REG_RST>;
		reset-names = "axi", "sw", "reg";
		mediatek,phy-mode = <&pciesys>;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: AHCI SATA Controller

description: |
  SATA nodes are defined to describe on-chip Serial ATA controllers.
  Each SATA controller should have its own node.

  It is possible, but not required, to represent each port as a sub-node.
  It allows to enable each port independently when dealing with multiple
  PHYs.

maintainers:
  - Hans de Goede <hdegoede@redhat.com>
  - Jens Axboe <axboe@kernel.dk>

select:
  properties:
    compatible:
      contains:
        enum:
          - brcm,iproc-ahci
          - cavium,octeon-7130-ahci
          - hisilicon,hisi-ahci
          - ibm,476gtr-ahci
          - marvell,armada-3700-ahci
          - marvell,armada-8k-ahci
          - marvell,berlin2q-ahci
  required:
    - compatible

allOf:
  - $ref: "ahci-common.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - brcm,iproc-ahci
              - marvell,armada-8k-ahci
              - marvell,berlin2-ahci
              - marvell,berlin2q-ahci
          - const: generic-ahci
      - enum:
          - cavium,octeon-7130-ahci
          - hisilicon,hisi-ahci
          - ibm,476gtr-ahci
          - marvell,armada-3700-ahci

  reg:
    minItems: 1
    maxItems: 2

  reg-names:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 3

  clock-names:
    minItems: 1
    maxItems: 3

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

patternProperties:
  "^sata-port@[0-9a-f]+$":
    $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port

    anyOf:
      - required: [ phys ]
      - required: [ target-supply ]

    unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    sata@ffe08000 {
        compatible = "snps,spear-ahci";
        reg = <0xffe08000 0x1000>;
        interrupts = <115>;
    };
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/berlin2q.h>
    #include <dt-bindings/ata/ahci.h>

    sata@f7e90000 {
        compatible = "marvell,berlin2q-ahci", "generic-ahci";
        reg = <0xf7e90000 0x1000>;
        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&chip CLKID_SATA>;
        #address-cells = <1>;
        #size-cells = <0>;

        hba-cap = <HBA_SMPS>;

        sata0: sata-port@0 {
            reg = <0>;

            phys = <&sata_phy 0>;
            target-supply = <&reg_sata0>;

            hba-port-cap = <(HBA_PORT_FBSCP | HBA_PORT_ESP)>;
        };

        sata1: sata-port@1 {
            reg = <1>;

            phys = <&sata_phy 1>;
            target-supply = <&reg_sata1>;

            hba-port-cap = <(HBA_PORT_HPCP | HBA_PORT_MPSP | HBA_PORT_FBSCP)>;
        };
    };


code:
STMicroelectronics STi SATA controller

This binding describes a SATA device.

Required properties:
 - compatible	   : Must be "st,ahci"
 - reg		   : Physical base addresses and length of register sets
 - interrupts	   : Interrupt associated with the SATA device
 - interrupt-names :   Associated name must be; "hostc"
 - clocks	   : The phandle for the clock
 - clock-names	   :   Associated name must be; "ahci_clk"
 - phys		   : The phandle for the PHY port
 - phy-names	   :   Associated name must be; "ahci_phy"

Optional properties:
 - resets	   : The power-down, soft-reset and power-reset lines of SATA IP
 - reset-names	   :   Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"

Example:

	/* Example for stih407 family silicon */
	sata0: sata@9b20000 {
		compatible	= "st,ahci";
		reg		= <0x9b20000 0x1000>;
		interrupts	= <GIC_SPI 159 IRQ_TYPE_NONE>;
		interrupt-names	= "hostc";
		phys		= <&phy_port0 PHY_TYPE_SATA>;
		phy-names	= "ahci_phy";
		resets		= <&powerdown STIH407_SATA0_POWERDOWN>,
				  <&softreset STIH407_SATA0_SOFTRESET>,
				  <&softreset STIH407_SATA0_PWR_SOFTRESET>;
		reset-names	= "pwr-dwn", "sw-rst", "pwr-rst";
		clocks		= <&clk_s_c0_flexgen CLK_ICN_REG>;
		clock-names	= "ahci_clk";
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/allwinner,sun4i-a10-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 AHCI SATA Controller bindings

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    const: allwinner,sun4i-a10-ahci

  reg:
    maxItems: 1

  clocks:
    items:
      - description: AHCI Bus Clock
      - description: AHCI Module Clock

  interrupts:
    maxItems: 1

  target-supply:
    description: Regulator for SATA target power

required:
  - compatible
  - reg
  - clocks
  - interrupts

additionalProperties: false

examples:
  - |
    ahci: sata@1c18000 {
        compatible = "allwinner,sun4i-a10-ahci";
        reg = <0x01c18000 0x1000>;
        interrupts = <56>;
        clocks = <&pll6 0>, <&ahb_gates 25>;
        target-supply = <&reg_ahci_5v>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner R40 AHCI SATA Controller bindings

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    const: allwinner,sun8i-r40-ahci

  reg:
    maxItems: 1

  clocks:
    items:
      - description: AHCI Bus Clock
      - description: AHCI Module Clock

  interrupts:
    maxItems: 1

  resets:
    maxItems: 1

  reset-names:
    const: ahci

  ahci-supply:
    description: Regulator for the AHCI controller

  phy-supply:
    description: Regulator for the SATA PHY power

required:
  - compatible
  - reg
  - clocks
  - interrupts
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun8i-r40-ccu.h>
    #include <dt-bindings/reset/sun8i-r40-ccu.h>

    ahci: sata@1c18000 {
        compatible = "allwinner,sun8i-r40-ahci";
        reg = <0x01c18000 0x1000>;
        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
        resets = <&ccu RST_BUS_SATA>;
        reset-names = "ahci";
        ahci-supply = <&reg_dldo4>;
        phy-supply = <&reg_eldo3>;
    };

...


code:
* APM X-Gene 6.0 Gb/s SATA host controller nodes

SATA host controller nodes are defined to describe on-chip Serial ATA
controllers. Each SATA controller (pair of ports) have its own node.

Required properties:
- compatible		: Shall contain:
  * "apm,xgene-ahci"
- reg			: First memory resource shall be the AHCI memory
			  resource.
			  Second memory resource shall be the host controller
			  core memory resource.
			  Third memory resource shall be the host controller
			  diagnostic memory resource.
			  4th memory resource shall be the host controller
			  AXI memory resource.
			  5th optional memory resource shall be the host
			  controller MUX memory resource if required.
- interrupts		: Interrupt-specifier for SATA host controller IRQ.
- clocks		: Reference to the clock entry.
- phys			: A list of phandles + phy-specifiers, one for each
			  entry in phy-names.
- phy-names		: Should contain:
  * "sata-phy" for the SATA 6.0Gbps PHY

Optional properties:
- dma-coherent		: Present if dma operations are coherent
- status		: Shall be "ok" if enabled or "disabled" if disabled.
			  Default is "ok".

Example:
		sataclk: sataclk {
			compatible = "fixed-clock";
			#clock-cells = <1>;
			clock-frequency = <100000000>;
			clock-output-names = "sataclk";
		};

		phy2: phy@1f22a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f22a000 0x0 0x100>;
			#phy-cells = <1>;
		};

		phy3: phy@1f23a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f23a000 0x0 0x100>;
			#phy-cells = <1>;
		};

		sata2: sata@1a400000 {
			compatible = "apm,xgene-ahci";
			reg = <0x0 0x1a400000 0x0 0x1000>,
			      <0x0 0x1f220000 0x0 0x1000>,
			      <0x0 0x1f22d000 0x0 0x1000>,
			      <0x0 0x1f22e000 0x0 0x1000>,
			      <0x0 0x1f227000 0x0 0x1000>;
			interrupts = <0x0 0x87 0x4>;
			dma-coherent;
			clocks = <&sataclk 0>;
			phys = <&phy2 0>;
			phy-names = "sata-phy";
		};

		sata3: sata@1a800000 {
			compatible = "apm,xgene-ahci-pcie";
			reg = <0x0 0x1a800000 0x0 0x1000>,
			      <0x0 0x1f230000 0x0 0x1000>,
			      <0x0 0x1f23d000 0x0 0x1000>,
			      <0x0 0x1f23e000 0x0 0x1000>,
			      <0x0 0x1f237000 0x0 0x1000>;
			interrupts = <0x0 0x88 0x4>;
			dma-coherent;
			clocks = <&sataclk 0>;
			phys = <&phy3 0>;
			phy-names = "sata-phy";
		};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/ata-generic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic Parallel ATA Controller

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description:
  Generic Parallel ATA controllers supporting PIO modes only.

properties:
  compatible:
    items:
      - enum:
          - arm,vexpress-cf
          - fsl,mpc8349emitx-pata
      - const: ata-generic

  reg:
    items:
      - description: Command interface registers
      - description: Control interface registers

  reg-shift:
    enum: [ 1, 2 ]

  interrupts:
    maxItems: 1

  ata-generic,use16bit:
    type: boolean
    description: Use 16-bit accesses instead of 32-bit for data transfers

  pio-mode:
    description: Maximum ATA PIO transfer mode
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 6
    default: 0

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    compact-flash@1a000 {
        compatible = "arm,vexpress-cf", "ata-generic";
        reg = <0x1a000 0x100>,
              <0x1a100 0xf00>;
        reg-shift = <2>;
    };
...


code:
Atmel AT91RM9200 CompactFlash

Required properties:
- compatible : "atmel,at91rm9200-cf".
- reg : should specify localbus address and size used.
- gpios : specifies the gpio pins to control the CF device. Detect
  and reset gpio's are mandatory while irq and vcc gpio's are
  optional and may be set to 0 if not present.

Example:
compact-flash@50000000 {
	compatible = "atmel,at91rm9200-cf";
	reg = <0x50000000 0x30000000>;
	gpios = <&pioC 13 0	/* irq */
		 &pioC 15 0 	/* detect */
		 0		/* vcc */
		 &pioC  5 0	/* reset */
		>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Baikal-T1 SoC AHCI SATA controller

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description:
  AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
  DWC AHCI SATA v4.10a IP-core.

allOf:
  - $ref: snps,dwc-ahci-common.yaml#

properties:
  compatible:
    const: baikal,bt1-ahci

  clocks:
    items:
      - description: Peripheral APB bus clock
      - description: Application AXI BIU clock
      - description: SATA Ports reference clock

  clock-names:
    items:
      - const: pclk
      - const: aclk
      - const: ref

  resets:
    items:
      - description: Application AXI BIU domain reset
      - description: SATA Ports clock domain reset

  reset-names:
    items:
      - const: arst
      - const: ref

  ports-implemented:
    maximum: 0x3

patternProperties:
  "^sata-port@[0-1]$":
    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port

    properties:
      reg:
        minimum: 0
        maximum: 1

      snps,tx-ts-max:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Due to having AXI3 bus interface utilized the maximum Tx DMA
          transaction size can't exceed 16 beats (AxLEN[3:0]).
        enum: [ 1, 2, 4, 8, 16 ]

      snps,rx-ts-max:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Due to having AXI3 bus interface utilized the maximum Rx DMA
          transaction size can't exceed 16 beats (AxLEN[3:0]).
        enum: [ 1, 2, 4, 8, 16 ]

    unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets

unevaluatedProperties: false

examples:
  - |
    sata@1f050000 {
      compatible = "baikal,bt1-ahci";
      reg = <0x1f050000 0x2000>;
      #address-cells = <1>;
      #size-cells = <0>;

      interrupts = <0 64 4>;

      clocks = <&ccu_sys 1>, <&ccu_axi 2>, <&sata_ref_clk>;
      clock-names = "pclk", "aclk", "ref";

      resets = <&ccu_axi 2>, <&ccu_sys 0>;
      reset-names = "arst", "ref";

      ports-implemented = <0x3>;

      sata-port@0 {
        reg = <0>;

        snps,tx-ts-max = <4>;
        snps,rx-ts-max = <4>;
      };

      sata-port@1 {
        reg = <1>;

        snps,tx-ts-max = <4>;
        snps,rx-ts-max = <4>;
      };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom SATA3 AHCI Controller

description:
  SATA nodes are defined to describe on-chip Serial ATA controllers.
  Each SATA controller should have its own node.

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

allOf:
  - $ref: ahci-common.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - brcm,bcm7216-ahci
              - brcm,bcm7445-ahci
              - brcm,bcm7425-ahci
              - brcm,bcm63138-ahci
          - const: brcm,sata3-ahci
      - items:
          - const: brcm,bcm-nsp-ahci

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: ahci
      - const: top-ctrl

  interrupts:
    maxItems: 1

if:
  properties:
    compatible:
      contains:
        enum:
          - brcm,bcm7216-ahci
          - brcm,bcm63138-ahci
then:
  properties:
    resets:
      maxItems: 1
    reset-names:
      enum:
        - rescal
        - ahci

required:
  - compatible
  - reg
  - interrupts
  - "#address-cells"
  - "#size-cells"

unevaluatedProperties: false

examples:
  - |
    sata@f045a000 {
        compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
        reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
        reg-names = "ahci", "top-ctrl";
        interrupts = <0 30 0>;
        #address-cells = <1>;
        #size-cells = <0>;

        sata0: sata-port@0 {
            reg = <0>;
            phys = <&sata_phy 0>;
        };

        sata1: sata-port@1 {
            reg = <1>;
            phys = <&sata_phy 1>;
        };
    };


code:
* Compact Flash

The Cavium Compact Flash device is connected to the Octeon Boot Bus,
and is thus a child of the Boot Bus device.  It can read and write
industry standard compact flash devices.

Properties:
- compatible: "cavium,ebt3000-compact-flash";

  Compatibility with many Cavium evaluation boards.

- reg: The base address of the CF chip select banks.  Depending on
  the device configuration, there may be one or two banks.

- cavium,bus-width: The width of the connection to the CF devices.  Valid
  values are 8 and 16.

- cavium,true-ide: Optional, if present the CF connection is in True IDE mode.

- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
  to this device.

Example:
	compact-flash@5,0 {
		compatible = "cavium,ebt3000-compact-flash";
		reg = <5 0 0x10000>, <6 0 0x10000>;
		cavium,bus-width = <16>;
		cavium,true-ide;
		cavium,dma-engine-handle = <&dma0>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ceva AHCI SATA Controller

maintainers:
  - Piyush Mehta <piyush.mehta@xilinx.com>

description: |
  The Ceva SATA controller mostly conforms to the AHCI interface with some
  special extensions to add functionality, is a high-performance dual-port
  SATA host controller with an AHCI compliant command layer which supports
  advanced features such as native command queuing and frame information
  structure (FIS) based switching for systems employing port multipliers.

properties:
  compatible:
    const: ceva,ahci-1v84

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  dma-coherent: true

  interrupts:
    maxItems: 1

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

  ceva,p0-cominit-params:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    description: |
      OOB timing value for COMINIT parameter for port 0.
      The fields for the above parameter must be as shown below:-
      ceva,p0-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
    items:
      - description: CINMP - COMINIT Negate Minimum Period.
      - description: CIBGN - COMINIT Burst Gap Nominal.
      - description: CIBGMX - COMINIT Burst Gap Maximum.
      - description: CIBGMN - COMINIT Burst Gap Minimum.

  ceva,p0-comwake-params:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    description: |
      OOB timing value for COMWAKE parameter for port 0.
      The fields for the above parameter must be as shown below:-
      ceva,p0-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
    items:
      - description: CWBGMN - COMWAKE Burst Gap Minimum.
      - description: CWBGMX - COMWAKE Burst Gap Maximum.
      - description: CWBGN - COMWAKE Burst Gap Nominal.
      - description: CWNMP - COMWAKE Negate Minimum Period.

  ceva,p0-burst-params:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    description: |
      Burst timing value for COM parameter for port 0.
      The fields for the above parameter must be as shown below:-
      ceva,p0-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
    items:
      - description: BMX - COM Burst Maximum.
      - description: BNM - COM Burst Nominal.
      - description: SFD - Signal Failure Detection value.
      - description: PTST - Partial to Slumber timer value.

  ceva,p0-retry-params:
    $ref: /schemas/types.yaml#/definitions/uint16-array
    description: |
      Retry interval timing value for port 0.
      The fields for the above parameter must be as shown below:-
      ceva,p0-retry-params = /bits/ 16 <RIT RCT>;
    items:
      - description: RIT - Retry Interval Timer.
      - description: RCT - Rate Change Timer.

  ceva,p1-cominit-params:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    description: |
      OOB timing value for COMINIT parameter for port 1.
      The fields for the above parameter must be as shown below:-
      ceva,p1-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
    items:
      - description: CINMP - COMINIT Negate Minimum Period.
      - description: CIBGN - COMINIT Burst Gap Nominal.
      - description: CIBGMX - COMINIT Burst Gap Maximum.
      - description: CIBGMN - COMINIT Burst Gap Minimum.

  ceva,p1-comwake-params:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    description: |
      OOB timing value for COMWAKE parameter for port 1.
      The fields for the above parameter must be as shown below:-
      ceva,p1-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
    items:
      - description: CWBGMN - COMWAKE Burst Gap Minimum.
      - description: CWBGMX - COMWAKE Burst Gap Maximum.
      - description: CWBGN - COMWAKE Burst Gap Nominal.
      - description: CWNMP - COMWAKE Negate Minimum Period.

  ceva,p1-burst-params:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    description: |
      Burst timing value for COM parameter for port 1.
      The fields for the above parameter must be as shown below:-
      ceva,p1-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
    items:
      - description: BMX - COM Burst Maximum.
      - description: BNM - COM Burst Nominal.
      - description: SFD - Signal Failure Detection value.
      - description: PTST - Partial to Slumber timer value.

  ceva,p1-retry-params:
    $ref: /schemas/types.yaml#/definitions/uint16-array
    description: |
      Retry interval timing value for port 1.
      The fields for the above parameter must be as shown below:-
      ceva,pN-retry-params = /bits/ 16 <RIT RCT>;
    items:
      - description: RIT - Retry Interval Timer.
      - description: RCT - Rate Change Timer.

  ceva,broken-gen2:
    $ref: /schemas/types.yaml#/definitions/flag
    description: |
      limit to gen1 speed instead of gen2.

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: sata-phy

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - interrupts
  - ceva,p0-cominit-params
  - ceva,p0-comwake-params
  - ceva,p0-burst-params
  - ceva,p0-retry-params
  - ceva,p1-cominit-params
  - ceva,p1-comwake-params
  - ceva,p1-burst-params
  - ceva,p1-retry-params

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/xlnx-zynqmp-power.h>
    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
    #include <dt-bindings/phy/phy.h>

    sata: ahci@fd0c0000 {
        compatible = "ceva,ahci-1v84";
        reg = <0xfd0c0000 0x200>;
        interrupt-parent = <&gic>;
        interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&zynqmp_clk SATA_REF>;
        ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
        ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
        ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
        ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
        ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
        ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
        ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
        ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
        ceva,broken-gen2;
        phys = <&psgtr 1 PHY_TYPE_SATA 1 1>;
        resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cortina Systems Gemini SATA Bridge

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
    The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
    takes two Faraday Technology FTIDE010 PATA controllers and bridges
    them in different configurations to two SATA ports.

properties:
  compatible:
    const: cortina,gemini-sata-bridge

  reg:
    maxItems: 1

  resets:
    maxItems: 2
    description: phandles to the reset lines for both SATA bridges

  reset-names:
    items:
      - const: sata0
      - const: sata1

  clocks:
    maxItems: 2
    description: phandles to the compulsory peripheral clocks

  clock-names:
    items:
      - const: SATA0_PCLK
      - const: SATA1_PCLK

  syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: a phandle to the global Gemini system controller

  cortina,gemini-ata-muxmode:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum:
      - 0
      - 1
      - 2
      - 3
    description: |
      Tell the desired multiplexing mode for the ATA controller and SATA
      bridges.
      Mode 0: ata0 master <-> sata0
              ata1 master <-> sata1
              ata0 slave interface brought out on IDE pads
      Mode 1: ata0 master <-> sata0
              ata1 master <-> sata1
              ata1 slave interface brought out on IDE pads
      Mode 2: ata1 master <-> sata1
              ata1 slave  <-> sata0
              ata0 master and slave interfaces brought out on IDE pads
      Mode 3: ata0 master <-> sata0
              ata0 slave  <-> sata1
              ata1 master and slave interfaces brought out on IDE pads

  cortina,gemini-enable-ide-pins:
    type: boolean
    description: Enables the PATA to IDE connection.
      The muxmode setting decides whether ATA0 or ATA1 is brought out,
      and whether master, slave or both interfaces get brought out.

  cortina,gemini-enable-sata-bridge:
    type: boolean
    description: Enables the PATA to SATA bridge inside the Gemnini SoC.
      The Muxmode decides what PATA blocks will be muxed out and how.

required:
  - clocks
  - clock-names
  - cortina,gemini-ata-muxmode
  - resets
  - reset-names
  - compatible
  - reg
  - syscon

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/cortina,gemini-clock.h>
    sata@46000000 {
      compatible = "cortina,gemini-sata-bridge";
      reg = <0x46000000 0x100>;
      resets = <&rcon 26>, <&rcon 27>;
      reset-names = "sata0", "sata1";
      clocks = <&gcc GEMINI_CLK_GATE_SATA0>,
               <&gcc GEMINI_CLK_GATE_SATA1>;
      clock-names = "SATA0_PCLK", "SATA1_PCLK";
      syscon = <&syscon>;
      cortina,gemini-ata-muxmode = <3>;
      cortina,gemini-enable-ide-pins;
      cortina,gemini-enable-sata-bridge;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/faraday,ftide010.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Faraday Technology FTIDE010 PATA controller

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  This controller is the first Faraday IDE interface block, used in the
  StorLink SL3512 and SL3516, later known as the Cortina Systems Gemini
  platform. The controller can do PIO modes 0 through 4, Multi-word DMA
  (MWDM) modes 0 through 2 and Ultra DMA modes 0 through 6.

  On the Gemini platform, this PATA block is accompanied by a PATA to
  SATA bridge in order to support SATA. This is why a phandle to that
  controller is compulsory on that platform.

  The timing properties are unique per-SoC, not per-board.

properties:
  compatible:
    oneOf:
      - const: faraday,ftide010
      - items:
          - const: cortina,gemini-pata
          - const: faraday,ftide010

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1

  clock-names:
    const: PCLK

  sata:
    description:
      phandle to the Gemini PATA to SATA bridge, if available
    $ref: /schemas/types.yaml#/definitions/phandle

required:
  - compatible
  - reg
  - interrupts

allOf:
  - $ref: pata-common.yaml#

  - if:
      properties:
        compatible:
          contains:
            const: cortina,gemini-pata

    then:
      required:
        - sata

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/cortina,gemini-clock.h>

    ide@63000000 {
      compatible = "cortina,gemini-pata", "faraday,ftide010";
      reg = <0x63000000 0x100>;
      interrupts = <4 IRQ_TYPE_EDGE_RISING>;
      clocks = <&gcc GEMINI_CLK_GATE_IDE>;
      clock-names = "PCLK";
      sata = <&sata>;
      #address-cells = <1>;
      #size-cells = <0>;
      ide-port@0 {
        reg = <0>;
      };
      ide-port@1 {
        reg = <1>;
      };
    };

...


code:
* Freescale 8xxx/3.0 Gb/s SATA nodes

SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA port should have its own node.

Required properties:
- compatible        : compatible list, contains 2 entries, first is
		 "fsl,CHIP-sata", where CHIP is the processor
		 (mpc8315, mpc8379, etc.) and the second is
		 "fsl,pq-sata"
- interrupts        : <interrupt mapping for SATA IRQ>
- cell-index        : controller index.
                          1 for controller @ 0x18000
                          2 for controller @ 0x19000
                          3 for controller @ 0x1a000
                          4 for controller @ 0x1b000

Optional properties:
- reg               : <registers mapping>

Example:
	sata@18000 {
		compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
		reg = <0x18000 0x1000>;
		cell-index = <1>;
		interrupts = <2c 8>;
		interrupt-parent = < &ipic >;
	};


code:
* Freescale i.MX PATA Controller

Required properties:
- compatible: "fsl,imx27-pata"
- reg: Address range of the PATA Controller
- interrupts: The interrupt of the PATA Controller
- clocks: the clocks for the PATA Controller

Example:

	pata: pata@83fe0000 {
		compatible = "fsl,imx51-pata", "fsl,imx27-pata";
		reg = <0x83fe0000 0x4000>;
		interrupts = <70>;
		clocks = <&clks 161>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/imx-sata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX AHCI SATA Controller

maintainers:
  - Shawn Guo <shawn.guo@linaro.org>

description: |
  The Freescale i.MX SATA controller mostly conforms to the AHCI interface
  with some special extensions at integration level.

properties:
  compatible:
    enum:
      - fsl,imx53-ahci
      - fsl,imx6q-ahci
      - fsl,imx6qp-ahci

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: sata clock
      - description: sata reference clock
      - description: ahb clock

  clock-names:
    items:
      - const: sata
      - const: sata_ref
      - const: ahb

  fsl,transmit-level-mV:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: transmit voltage level, in millivolts.

  fsl,transmit-boost-mdB:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: transmit boost level, in milli-decibels.

  fsl,transmit-atten-16ths:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: transmit attenuation, in 16ths.

  fsl,receive-eq-mdB:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: receive equalisation, in milli-decibels.

  fsl,no-spread-spectrum:
    $ref: /schemas/types.yaml#/definitions/flag
    description: if present, disable spread-spectrum clocking on the SATA link.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx6qdl-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    sata@2200000 {
        compatible = "fsl,imx6q-ahci";
        reg = <0x02200000 0x4000>;
        interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clks IMX6QDL_CLK_SATA>,
                 <&clks IMX6QDL_CLK_SATA_REF_100M>,
                 <&clks IMX6QDL_CLK_AHB>;
        clock-names = "sata", "sata_ref", "ahb";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/intel,ixp4xx-compact-flash.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel IXP4xx CompactFlash Card Controller

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  The IXP4xx network processors have a CompactFlash interface that presents
  a CompactFlash card to the system as a true IDE (parallel ATA) device. The
  device is always connected to the expansion bus of the IXP4xx SoCs using one
  or two chip select areas and address translating logic on the board. The
  node must be placed inside a chip select node on the IXP4xx expansion bus.

properties:
  compatible:
    const: intel,ixp4xx-compact-flash

  reg:
    items:
      - description: Command interface registers
      - description: Control interface registers

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

allOf:
  - $ref: pata-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    bus@c4000000 {
      compatible = "intel,ixp43x-expansion-bus-controller", "syscon";
      reg = <0xc4000000 0x1000>;
      native-endian;
      #address-cells = <2>;
      #size-cells = <1>;
      ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
      dma-ranges = <0 0x0 0x50000000 0x01000000>, <1 0x0 0x51000000 0x01000000>;
      ide@1,0 {
        compatible = "intel,ixp4xx-compact-flash";
        reg = <1 0x00000000 0x1000>, <1 0x00040000 0x1000>;
        interrupt-parent = <&gpio0>;
        interrupts = <12 IRQ_TYPE_EDGE_RISING>;
      };
    };

...


code:
* Marvell Orion SATA

Required Properties:
- compatibility : "marvell,orion-sata" or "marvell,armada-370-sata"
- reg           : Address range of controller
- interrupts    : Interrupt controller is using
- nr-ports      : Number of SATA ports in use.

Optional Properties:
- phys		: List of phandles to sata phys
- phy-names	: Should be "0", "1", etc, one number per phandle

Example:

	sata@80000 {
		compatible = "marvell,orion-sata";
		reg = <0x80000 0x5000>;
		interrupts = <21>;
		phys = <&sata_phy0>, <&sata_phy1>;
		phy-names = "0", "1";
		nr-ports = <2>;
	}


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Tegra AHCI SATA Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jonathan Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    enum:
      - nvidia,tegra124-ahci
      - nvidia,tegra132-ahci
      - nvidia,tegra210-ahci
      - nvidia,tegra186-ahci

  reg:
    minItems: 2
    items:
      - description: AHCI registers
      - description: SATA configuration and IPFS registers
      - description: SATA AUX registers

  interrupts:
    maxItems: 1

  clock-names:
    items:
      - const: sata
      - const: sata-oob

  clocks:
    maxItems: 2

  reset-names:
    minItems: 2
    items:
      - const: sata
      - const: sata-cold
      - const: sata-oob

  resets:
    minItems: 2
    maxItems: 3

  iommus:
    maxItems: 1

  interconnect-names:
    items:
      - const: dma-mem
      - const: write

  interconnects:
    maxItems: 2

  power-domains:
    items:
      - description: SAX power-domain

  phy-names:
    items:
      - const: sata-0

  phys:
    maxItems: 1

  hvdd-supply:
    description: SATA HVDD regulator supply.

  vddio-supply:
    description: SATA VDDIO regulator supply.

  avdd-supply:
    description: SATA AVDD regulator supply.

  target-5v-supply:
    description: SATA 5V power regulator supply.

  target-12v-supply:
    description: SATA 12V power regulator supply.

required:
  - compatible
  - reg
  - interrupts
  - clock-names
  - clocks
  - reset-names
  - resets

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra124-ahci
              - nvidia,tegra132-ahci
    then:
      properties:
        reg:
          maxItems: 2
        reset-names:
          minItems: 3
        resets:
          minItems: 3
      required:
        - phys
        - phy-names
        - hvdd-supply
        - vddio-supply
        - avdd-supply

  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra210-ahci
    then:
      properties:
        reg:
          minItems: 3
        reset-names:
          minItems: 3
        resets:
          minItems: 3

  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra186-ahci
    then:
      properties:
        reg:
          minItems: 3
        reset-names:
          maxItems: 2
        resets:
          maxItems: 2
      required:
        - iommus
        - interconnect-names
        - interconnects
        - power-domains

additionalProperties: true

examples:
  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/reset/tegra210-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    sata@70020000 {
            compatible = "nvidia,tegra210-ahci";
            reg = <0x70027000 0x00002000>, /* AHCI */
                  <0x70020000 0x00007000>, /* SATA */
                  <0x70001100 0x00010000>; /* SATA AUX */
            interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&tegra_car TEGRA210_CLK_SATA>,
                     <&tegra_car TEGRA210_CLK_SATA_OOB>;
            clock-names = "sata", "sata-oob";
            resets = <&tegra_car 124>,
                     <&tegra_car 129>,
                     <&tegra_car 123>;
            reset-names = "sata", "sata-cold", "sata-oob";
    };


code:
* ARASAN PATA COMPACT FLASH CONTROLLER

Required properties:
- compatible: "arasan,cf-spear1340"
- reg: Address range of the CF registers
- interrupt: Should contain the CF interrupt number
- clock-frequency: Interface clock rate, in Hz, one of
       25000000
       33000000
       40000000
       50000000
       66000000
       75000000
      100000000
      125000000
      150000000
      166000000
      200000000

Optional properties:
- arasan,broken-udma: if present, UDMA mode is unusable
- arasan,broken-mwdma: if present, MWDMA mode is unusable
- arasan,broken-pio: if present, PIO mode is unusable
- dmas: one DMA channel, as described in bindings/dma/dma.txt
  required unless both UDMA and MWDMA mode are broken
- dma-names: the corresponding channel name, must be "data"

Example:

	cf@fc000000 {
		compatible = "arasan,cf-spear1340";
		reg = <0xfc000000 0x1000>;
		interrupt-parent = <&vic1>;
		interrupts = <12>;
		dmas = <&dma-controller 23>;
		dma-names = "data";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/pata-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common Properties for Parallel AT attachment (PATA) controllers

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  This document defines device tree properties common to most Parallel
  ATA (PATA, also known as IDE) AT attachment storage devices.
  It doesn't constitue a device tree binding specification by itself but is
  meant to be referenced by device tree bindings.

  The PATA (IDE) controller-specific device tree bindings are responsible for
  defining whether each property is required or optional.

properties:
  $nodename:
    pattern: "^ide(@.*)?$"
    description:
      Specifies the host controller node. PATA host controller nodes are named
      "ide".

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

patternProperties:
  "^ide-port@[0-1]$":
    description: |
      DT nodes for ports connected on the PATA host. The master drive will have
      ID number 0 and the slave drive will have ID number 1. The PATA port
      nodes will be named "ide-port".
    type: object

    properties:
      reg:
        minimum: 0
        maximum: 1
        description:
          The ID number of the drive port, 0 for the master port and 1 for the
          slave port.

additionalProperties: true

...


code:
* Qualcomm AHCI SATA Controller

SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.

Required properties:
- compatible		: compatible list, must contain "generic-ahci"
- interrupts		: <interrupt mapping for SATA IRQ>
- reg			: <registers mapping>
- phys			: Must contain exactly one entry as specified
			  in phy-bindings.txt
- phy-names		: Must be "sata-phy"

Required properties for "qcom,ipq806x-ahci" compatible:
- clocks		: Must contain an entry for each entry in clock-names.
- clock-names		: Shall be:
				"slave_iface" - Fabric port AHB clock for SATA
				"iface" - AHB clock
				"core" - core clock
				"rxoob" - RX out-of-band clock
				"pmalive" - Power Module Alive clock
- assigned-clocks	: Shall be:
				SATA_RXOOB_CLK
				SATA_PMALIVE_CLK
- assigned-clock-rates	: Shall be:
				100Mhz (100000000) for SATA_RXOOB_CLK
				100Mhz (100000000) for SATA_PMALIVE_CLK

Example:
	sata@29000000 {
		compatible = "qcom,ipq806x-ahci", "generic-ahci";
		reg = <0x29000000 0x180>;

		interrupts = <0 209 0x0>;

		clocks = <&gcc SFAB_SATA_S_H_CLK>,
			 <&gcc SATA_H_CLK>,
			 <&gcc SATA_A_CLK>,
			 <&gcc SATA_RXOOB_CLK>,
			 <&gcc SATA_PMALIVE_CLK>;
		clock-names = "slave_iface", "iface", "core",
				"rxoob", "pmalive";
		assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
		assigned-clock-rates = <100000000>, <100000000>;

		phys = <&sata_phy>;
		phy-names = "sata-phy";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Renesas R-Car Serial-ATA Interface

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,sata-r8a7779      # R-Car H1
      - items:
          - enum:
              - renesas,sata-r8a7742      # RZ/G1H
              - renesas,sata-r8a7790-es1  # R-Car H2 ES1
              - renesas,sata-r8a7790      # R-Car H2 other than ES1
              - renesas,sata-r8a7791      # R-Car M2-W
              - renesas,sata-r8a7793      # R-Car M2-N
          - const: renesas,rcar-gen2-sata # generic R-Car Gen2
      - items:
          - enum:
              - renesas,sata-r8a774b1     # RZ/G2N
              - renesas,sata-r8a774e1     # RZ/G2H
              - renesas,sata-r8a7795      # R-Car H3
              - renesas,sata-r8a77965     # R-Car M3-N
          - const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains

if:
  not:
    properties:
      compatible:
        contains:
          const: renesas,sata-r8a7779
then:
  required:
    - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7791-sysc.h>

    sata@ee300000 {
            compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
            reg = <0xee300000 0x200000>;
            interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 815>;
            power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
            resets = <&cpg 815>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/sata-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common Properties for Serial AT attachment (SATA) controllers

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  This document defines device tree properties common to most Serial
  AT attachment (SATA) storage devices. It doesn't constitute a device tree
  binding specification by itself but is meant to be referenced by device
  tree bindings.

  The SATA controller-specific device tree bindings are responsible for
  defining whether each property is required or optional.

properties:
  $nodename:
    pattern: "^sata(@.*)?$"
    description:
      Specifies the host controller node. SATA host controller nodes are named
      "sata"

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  dma-coherent: true

patternProperties:
  "^sata-port@[0-9a-e]$":
    $ref: '#/$defs/sata-port'
    description: |
      DT nodes for ports connected on the SATA host. The SATA port
      nodes will be named "sata-port".

additionalProperties: true

$defs:
  sata-port:
    type: object

    properties:
      reg:
        minimum: 0
        description:
          The ID number of the SATA port. Aside with being directly used,
          each port can have a Port Multiplier attached thus allowing to
          access more than one drive by means of a single SATA port.

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/sata_highbank.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Calxeda AHCI SATA Controller

description: |
  The Calxeda SATA controller mostly conforms to the AHCI interface
  with some special extensions to add functionality, to map GPIOs for
  activity LEDs and for mapping the ComboPHYs.

maintainers:
  - Andre Przywara <andre.przywara@arm.com>

properties:
  compatible:
    const: calxeda,hb-ahci

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  dma-coherent: true

  calxeda,pre-clocks:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Indicates the number of additional clock cycles to transmit before
      sending an SGPIO pattern.

  calxeda,post-clocks:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Indicates the number of additional clock cycles to transmit after
      sending an SGPIO pattern.

  calxeda,led-order:
    description: Maps port numbers to offsets within the SGPIO bitstream.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 8

  calxeda,port-phys:
    description: |
      phandle-combophy and lane assignment, which maps each SATA port to a
      combophy and a lane within that combophy
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 1
    maxItems: 8
    items:
      maxItems: 2

  calxeda,tx-atten:
    description: |
      Contains TX attenuation override codes, one per port.
      The upper 24 bits of each entry are always 0 and thus ignored.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 8

  calxeda,sgpio-gpio:
    maxItems: 3
    description: |
      phandle-gpio bank, bit offset, and default on or off, which indicates
      that the driver supports SGPIO indicator lights using the indicated
      GPIOs.

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    sata@ffe08000 {
        compatible = "calxeda,hb-ahci";
        reg = <0xffe08000 0x1000>;
        interrupts = <115>;
        dma-coherent;
        calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>,
                             <&combophy0 2>, <&combophy0 3>;
        calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>;
        calxeda,led-order = <4 0 1 2 3>;
        calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
        calxeda,pre-clocks = <10>;
        calxeda,post-clocks = <0>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DWC AHCI SATA controller properties

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description:
  This document defines device tree schema for the generic Synopsys DWC
  AHCI controller properties.

select: false

allOf:
  - $ref: ahci-common.yaml#

properties:
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    description:
      Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
      PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
      clock, etc.
    minItems: 1
    maxItems: 4

  clock-names:
    minItems: 1
    maxItems: 4
    items:
      oneOf:
        - description: Application APB/AHB/AXI BIU clock
          enum:
            - pclk
            - aclk
            - hclk
            - sata
        - description: Power Module keep-alive clock
          const: pmalive
        - description: RxOOB detection clock
          const: rxoob
        - description: SATA Ports reference clock
          const: ref

  resets:
    description:
      At least basic application and reference clock domains resets are
      normally supported by the DWC AHCI SATA controller.
    minItems: 1
    maxItems: 4

  reset-names:
    minItems: 1
    maxItems: 4
    items:
      oneOf:
        - description: Application AHB/AXI BIU clock domain reset control
          enum:
            - arst
            - hrst
        - description: Power Module keep-alive clock domain reset control
          const: pmalive
        - description: RxOOB detection clock domain reset control
          const: rxoob
        - description: Reference clock domain reset control
          const: ref

patternProperties:
  "^sata-port@[0-9a-e]$":
    $ref: '#/$defs/dwc-ahci-port'

additionalProperties: true

$defs:
  dwc-ahci-port:
    $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port

    properties:
      reg:
        minimum: 0
        maximum: 7

      snps,tx-ts-max:
        $ref: /schemas/types.yaml#/definitions/uint32
        description: Maximal size of Tx DMA transactions in FIFO words
        enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]

      snps,rx-ts-max:
        $ref: /schemas/types.yaml#/definitions/uint32
        description: Maximal size of Rx DMA transactions in FIFO words
        enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DWC AHCI SATA controller

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description:
  This document defines device tree bindings for the generic Synopsys DWC
  implementation of the AHCI SATA controller.

allOf:
  - $ref: snps,dwc-ahci-common.yaml#

properties:
  compatible:
    oneOf:
      - description: Synopsys AHCI SATA-compatible devices
        const: snps,dwc-ahci
      - description: SPEAr1340 AHCI SATA device
        const: snps,spear-ahci
      - description: Rockhip RK3568 AHCI controller
        items:
          - const: rockchip,rk3568-dwc-ahci
          - const: snps,dwc-ahci

patternProperties:
  "^sata-port@[0-9a-e]$":
    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port

    unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/ata/ahci.h>

    sata@122f0000 {
      compatible = "snps,dwc-ahci";
      reg = <0x122F0000 0x1ff>;
      #address-cells = <1>;
      #size-cells = <0>;

      interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&clock1>, <&clock2>;
      clock-names = "aclk", "ref";

      phys = <&sata_phy>;
      phy-names = "sata-phy";

      ports-implemented = <0x1>;

      sata-port@0 {
        reg = <0>;

        hba-port-cap = <HBA_PORT_FBSCP>;

        snps,tx-ts-max = <512>;
        snps,rx-ts-max = <512>;
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/auxdisplay/arm,versatile-lcd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Versatile Character LCD

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>
  - Rob Herring <robh@kernel.org>

description:
  This binding defines the character LCD interface found on ARM Versatile AB
  and PB reference platforms.

properties:
  compatible:
    const: arm,versatile-lcd

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    lcd@10008000 {
            compatible = "arm,versatile-lcd";
            reg = <0x10008000 0x1000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/auxdisplay/hit,hd44780.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Hitachi HD44780 Character LCD Controller

maintainers:
  - Geert Uytterhoeven <geert@linux-m68k.org>

description:
  The Hitachi HD44780 Character LCD Controller is commonly used on character
  LCDs that can display one or more lines of text. It exposes an M6800 bus
  interface, which can be used in either 4-bit or 8-bit mode. By using a
  GPIO expander it is possible to use the driver with one of the popular I2C
  expander boards based on the PCF8574 available for these displays. For
  an example see below.

properties:
  compatible:
    const: hit,hd44780

  data-gpios:
    description:
      GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
      DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
    oneOf:
      - maxItems: 4
      - maxItems: 8

  enable-gpios:
    description:
      GPIO pin connected to the "E" (Enable) signal line of the LCD
      Controller's bus interface.
    maxItems: 1

  rs-gpios:
    description:
      GPIO pin connected to the "RS" (Register Select) signal line of the LCD
      Controller's bus interface.
    maxItems: 1

  rw-gpios:
    description:
      GPIO pin connected to the "RW" (Read/Write) signal line of the LCD
      Controller's bus interface.
    maxItems: 1

  backlight-gpios:
    description: GPIO pin used for enabling the LCD's backlight.
    maxItems: 1

  display-height-chars:
    description: Height of the display, in character cells,
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 4

  display-width-chars:
    description: Width of the display, in character cells.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 64

  internal-buffer-width:
    description:
      Internal buffer width (default is 40 for displays with 1 or 2 lines, and
      display-width-chars for displays with more than 2 lines).
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 64

required:
  - compatible
  - data-gpios
  - enable-gpios
  - rs-gpios
  - display-height-chars
  - display-width-chars

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    auxdisplay {
            compatible = "hit,hd44780";

            data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>,
                         <&hc595 1 GPIO_ACTIVE_HIGH>,
                         <&hc595 2 GPIO_ACTIVE_HIGH>,
                         <&hc595 3 GPIO_ACTIVE_HIGH>;
            enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
            rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;

            display-height-chars = <2>;
            display-width-chars = <16>;
    };
  - |
    #include <dt-bindings/gpio/gpio.h>
    i2c {
            #address-cells = <1>;
            #size-cells = <0>;

            pcf8574: pcf8574@27 {
                    compatible = "nxp,pcf8574";
                    reg = <0x27>;
                    gpio-controller;
                    #gpio-cells = <2>;
            };
    };
    hd44780 {
            compatible = "hit,hd44780";
            display-height-chars = <2>;
            display-width-chars  = <16>;
            data-gpios = <&pcf8574 4 0>,
                         <&pcf8574 5 0>,
                         <&pcf8574 6 0>,
                         <&pcf8574 7 0>;
            enable-gpios = <&pcf8574 2 0>;
            rs-gpios = <&pcf8574 0 0>;
            rw-gpios = <&pcf8574 1 0>;
            backlight-gpios = <&pcf8574 3 0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/auxdisplay/holtek,ht16k33.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Holtek HT16K33 RAM mapping 16*8 LED controller with keyscan

maintainers:
  - Robin van der Gracht <robin@protonic.nl>

allOf:
  - $ref: "/schemas/input/matrix-keymap.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - adafruit,3108  # 0.56" 4-Digit 7-Segment FeatherWing Display (Red)
              - adafruit,3130  # 0.54" Quad Alphanumeric FeatherWing Display (Red)
          - const: holtek,ht16k33

      - const: holtek,ht16k33     # Generic 16*8 LED controller with dot-matrix display

  reg:
    maxItems: 1

  refresh-rate-hz:
    maxItems: 1
    description: Display update interval in Hertz for dot-matrix displays

  interrupts:
    maxItems: 1

  debounce-delay-ms:
    maxItems: 1
    description: Debouncing interval time in milliseconds

  linux,keymap: true

  linux,no-autorepeat:
    description: Disable keyrepeat

  default-brightness-level:
    minimum: 1
    maximum: 16
    default: 16
    description: Initial brightness level

  led:
    type: object
    $ref: /schemas/leds/common.yaml#
    unevaluatedProperties: false

required:
  - compatible
  - reg

if:
  properties:
    compatible:
      const: holtek,ht16k33
then:
  required:
    - refresh-rate-hz

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/input/input.h>
    #include <dt-bindings/leds/common.h>
    i2c1 {
            #address-cells = <1>;
            #size-cells = <0>;

            ht16k33: ht16k33@70 {
                    compatible = "holtek,ht16k33";
                    reg = <0x70>;
                    refresh-rate-hz = <20>;
                    interrupt-parent = <&gpio4>;
                    interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
                    debounce-delay-ms = <50>;
                    linux,keymap = <MATRIX_KEY(2, 0, KEY_F6)>,
                                   <MATRIX_KEY(3, 0, KEY_F8)>,
                                   <MATRIX_KEY(4, 0, KEY_F10)>,
                                   <MATRIX_KEY(5, 0, KEY_F4)>,
                                   <MATRIX_KEY(6, 0, KEY_F2)>,
                                   <MATRIX_KEY(2, 1, KEY_F5)>,
                                   <MATRIX_KEY(3, 1, KEY_F7)>,
                                   <MATRIX_KEY(4, 1, KEY_F9)>,
                                   <MATRIX_KEY(5, 1, KEY_F3)>,
                                   <MATRIX_KEY(6, 1, KEY_F1)>;

                    led {
                            color = <LED_COLOR_ID_RED>;
                            function = LED_FUNCTION_BACKLIGHT;
                            linux,default-trigger = "backlight";
                    };
            };
      };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/auxdisplay/img,ascii-lcd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASCII LCD displays on Imagination Technologies boards

maintainers:
  - Paul Burton <paulburton@kernel.org>

properties:
  compatible:
    enum:
      - img,boston-lcd
      - mti,malta-lcd
      - mti,sead3-lcd

  reg:
    maxItems: 1

  offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Offset in bytes to the LCD registers within the system controller

required:
  - compatible

oneOf:
  - required:
      - reg
  - required:
      - offset

if:
  properties:
    compatible:
      contains:
        const: img,boston-lcd
then:
  required:
    - reg
else:
  required:
    - offset

additionalProperties: false

examples:
  - |
    lcd: lcd@17fff000 {
            compatible = "img,boston-lcd";
            reg = <0x17fff000 0x8>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/auxdisplay/modtronix,lcd2s.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Modtronix engineering LCD2S Character LCD Display

maintainers:
  - Lars Poeschel <poeschel@lemonage.de>

description:
  The LCD2S is a Character LCD Display manufactured by Modtronix Engineering.
  The display supports a serial I2C and SPI interface. The driver currently
  only supports the I2C interface.

properties:
  compatible:
    const: modtronix,lcd2s

  reg:
    maxItems: 1
    description:
      I2C bus address of the display.

  display-height-chars:
    description: Height of the display, in character cells.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 4

  display-width-chars:
    description: Width of the display, in character cells.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 16
    maximum: 20

required:
  - compatible
  - reg
  - display-height-chars
  - display-width-chars

additionalProperties: false

examples:
  - |
    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      lcd2s: auxdisplay@28 {
        compatible = "modtronix,lcd2s";
        reg = <0x28>;
        display-height-chars = <4>;
        display-width-chars = <20>;
      };
    };


code:
Freescale Reference Board Bindings

This document describes device tree bindings for various devices that
exist on some Freescale reference boards.

* Board Control and Status (BCSR)

Required properties:

 - compatible : Should be "fsl,<board>-bcsr"
 - reg : Offset and length of the register set for the device

Example:

	bcsr@f8000000 {
		compatible = "fsl,mpc8360mds-bcsr";
		reg = <f8000000 8000>;
	};

* Freescale on-board FPGA

This is the memory-mapped registers for on board FPGA.

Required properties:
- compatible: should be a board-specific string followed by a string
  indicating the type of FPGA.  Example:
	"fsl,<board>-fpga", "fsl,fpga-pixis", or
	"fsl,<board>-fpga", "fsl,fpga-qixis"
- reg: should contain the address and the length of the FPGA register set.

Optional properties:
- interrupts: should specify event (wakeup) IRQ.

Example (P1022DS):

	 board-control@3,0 {
		 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
		 reg = <3 0 0x30>;
		 interrupt-parent = <&mpic>;
		 interrupts = <8 8 0 0>;
	 };

Example (LS2080A-RDB):

        cpld@3,0 {
                compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
                reg = <0x3 0 0x10000>;
        };

* Freescale on-board FPGA connected on I2C bus

Some Freescale boards like BSC9132QDS have on board FPGA connected on
the i2c bus.

Required properties:
- compatible: Should be a board-specific string followed by a string
  indicating the type of FPGA.  Example:
	"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"
- reg: Should contain the address of the FPGA

Example:
	fpga: fpga@66 {
		compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
		reg = <0x66>;
	};

* Freescale on-board CPLD

Some Freescale boards like T1040RDB have an on board CPLD connected.

Required properties:
- compatible: Should be a board-specific string like "fsl,<board>-cpld"
  Example:
	"fsl,t1040rdb-cpld", "fsl,t1042rdb-cpld", "fsl,t1042rdb_pi-cpld"
- reg: should describe CPLD registers

Example:
	cpld@3,0 {
		compatible = "fsl,t1040rdb-cpld";
		reg = <3 0 0x300>;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/allwinner,sun50i-a64-de2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A64 Display Engine Bus

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  $nodename:
    pattern: "^bus(@[0-9a-f]+)?$"

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  compatible:
    oneOf:
      - const: allwinner,sun50i-a64-de2
      - items:
          - const: allwinner,sun50i-h6-de3
          - const: allwinner,sun50i-a64-de2

  reg:
    maxItems: 1

  allwinner,sram:
    description:
      The SRAM that needs to be claimed to access the display engine
      bus.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to SRAM
          - description: register value for device

  ranges: true

patternProperties:
  # All other properties should be child nodes with unit-address and 'reg'
  "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+$":
    type: object
    properties:
      reg:
        maxItems: 1

    required:
      - reg

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - allwinner,sram

additionalProperties: false

examples:
  - |
    bus@1000000 {
        compatible = "allwinner,sun50i-a64-de2";
        reg = <0x1000000 0x400000>;
        allwinner,sram = <&de2_sram 1>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0x1000000 0x400000>;

        display_clocks: clock@0 {
            compatible = "allwinner,sun50i-a64-de2-clk";
            reg = <0x0 0x100000>;
            clocks = <&ccu 52>, <&ccu 99>;
            clock-names = "bus", "mod";
            resets = <&ccu 30>;
            #clock-cells = <1>;
            #reset-cells = <1>;
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/allwinner,sun8i-a23-rsb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A23 RSB

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  compatible:
    oneOf:
      - const: allwinner,sun8i-a23-rsb
      - items:
          - enum:
              - allwinner,sun8i-a83t-rsb
              - allwinner,sun50i-h616-rsb
          - const: allwinner,sun8i-a23-rsb

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  clock-frequency:
    minimum: 1
    maximum: 20000000

patternProperties:
  "^.*@[0-9a-fA-F]+$":
    type: object
    properties:
      reg:
        maxItems: 1

    required:
      - reg

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - resets

examples:
  - |
    rsb@1f03400 {
        compatible = "allwinner,sun8i-a23-rsb";
        reg = <0x01f03400 0x400>;
        interrupts = <0 39 4>;
        clocks = <&apb0_gates 3>;
        clock-frequency = <3000000>;
        resets = <&apb0_rst 3>;
        #address-cells = <1>;
        #size-cells = <0>;

        pmic@3e3 {
            reg = <0x3e3>;

            /* ... */
        };
    };

additionalProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/arm,integrator-ap-lm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Integrator/AP Logic Module extension bus

maintainers:
  - Linus Walleij <linusw@kernel.org>

description: The Integrator/AP is a prototyping platform and as such has a
  site for stacking up to four logic modules (LM) designed specifically for
  use with this platform. A special system controller register can be read to
  determine if a logic module is connected at index 0, 1, 2 or 3. The logic
  module connector is described in this binding. The logic modules per se
  then have their own specific per-module bindings and they will be described
  as subnodes under this logic module extension bus.

properties:
  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  compatible:
    items:
      - const: arm,integrator-ap-lm

  ranges: true
  dma-ranges: true

patternProperties:
  "^bus(@[0-9a-f]*)?$":
    description: Nodes on the Logic Module bus represent logic modules
      and are named with bus. The first module is at 0xc0000000, the second
      at 0xd0000000 and so on until the top of the memory of the system at
      0xffffffff. All information about the memory used by the module is
      in ranges and dma-ranges.
    type: object

    required:
      - compatible

required:
  - compatible

examples:
  - |
    bus@c0000000 {
      compatible = "arm,integrator-ap-lm";
      #address-cells = <1>;
      #size-cells = <1>;
      ranges = <0xc0000000 0xc0000000 0x40000000>;
      dma-ranges;

      bus@c0000000 {
        compatible = "simple-bus";
        ranges = <0x00000000 0xc0000000 0x10000000>;
        /* The Logic Modules sees the Core Module 0 RAM @80000000 */
        dma-ranges = <0x00000000 0x80000000 0x10000000>;
        #address-cells = <1>;
        #size-cells = <1>;

        serial@100000 {
          compatible = "arm,pl011", "arm,primecell";
          reg = <0x00100000 0x1000>;
          interrupts-extended = <&impd1_vic 1>;
        };

        impd1_vic: interrupt-controller@3000000 {
          compatible = "arm,pl192-vic";
          interrupt-controller;
          #interrupt-cells = <1>;
          reg = <0x03000000 0x1000>;
          valid-mask = <0x00000bff>;
          interrupts-extended = <&pic 9>;
        };
      };
    };

additionalProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Baikal-T1 APB-bus

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description: |
  Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect
  which routes them to the AXI-APB bridge. This interface is a single master
  multiple slaves bus in turn serializing IO accesses and routing them to the
  addressed APB slave devices. In case of any APB protocol collisions, slave
  device not responding on timeout an IRQ is raised with an erroneous address
  reported to the APB terminator (APB Errors Handler Block).

allOf:
  - $ref: /schemas/simple-bus.yaml#

properties:
  compatible:
    contains:
      const: baikal,bt1-apb

  reg:
    items:
      - description: APB EHB MMIO registers
      - description: APB MMIO region with no any device mapped

  reg-names:
    items:
      - const: ehb
      - const: nodev

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: APB reference clock

  clock-names:
    items:
      - const: pclk

  resets:
    items:
      - description: APB domain reset line

  reset-names:
    items:
      - const: prst

unevaluatedProperties: false

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names

examples:
  - |
    #include <dt-bindings/interrupt-controller/mips-gic.h>

    bus@1f059000 {
      compatible = "baikal,bt1-apb", "simple-bus";
      reg = <0x1f059000 0x1000>,
            <0x1d000000 0x2040000>;
      reg-names = "ehb", "nodev";
      #address-cells = <1>;
      #size-cells = <1>;

      ranges;

      interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&ccu_sys 1>;
      clock-names = "pclk";

      resets = <&ccu_sys 1>;
      reset-names = "prst";
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Baikal-T1 AXI-bus

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description: |
  AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
  high-speed peripheral IP-cores with RAM controller and with MIPS P5600
  cores. Traffic arbitration is done by means of DW AXI Interconnect (so
  called AXI Main Interconnect) routing IO requests from one block to
  another: from CPU to SoC peripherals and between some SoC peripherals
  (mostly between peripheral devices and RAM, but also between DMA and
  some peripherals). In case of any protocol error, device not responding
  an IRQ is raised and a faulty situation is reported to the AXI EHB
  (Errors Handler Block) embedded on top of the DW AXI Interconnect and
  accessible by means of the Baikal-T1 System Controller.

allOf:
  - $ref: /schemas/simple-bus.yaml#

properties:
  compatible:
    contains:
      const: baikal,bt1-axi

  reg:
    minItems: 1
    items:
      - description: Synopsys DesignWare AXI Interconnect QoS registers
      - description: AXI EHB MMIO system controller registers

  reg-names:
    minItems: 1
    items:
      - const: qos
      - const: ehb

  '#interconnect-cells':
    const: 1

  syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: Phandle to the Baikal-T1 System Controller DT node

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Main Interconnect uplink reference clock

  clock-names:
    items:
      - const: aclk

  resets:
    items:
      - description: Main Interconnect reset line

  reset-names:
    items:
      - const: arst

unevaluatedProperties: false

required:
  - compatible
  - reg
  - reg-names
  - syscon
  - interrupts
  - clocks
  - clock-names

examples:
  - |
    #include <dt-bindings/interrupt-controller/mips-gic.h>

    bus@1f05a000 {
      compatible = "baikal,bt1-axi", "simple-bus";
      reg = <0x1f05a000 0x1000>,
            <0x1f04d110 0x8>;
      reg-names = "qos", "ehb";
      #address-cells = <1>;
      #size-cells = <1>;
      #interconnect-cells = <1>;

      syscon = <&syscon>;

      ranges;

      interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&ccu_axi 0>;
      clock-names = "aclk";

      resets = <&ccu_axi 0>;
      reset-names = "arst";
    };
...


code:
Driver for ARM AXI Bus with Broadcom Plugins (bcma)

Required properties:

- compatible : brcm,bus-axi

- reg : iomem address range of chipcommon core

The cores on the AXI bus are automatically detected by bcma with the
memory ranges they are using and they get registered afterwards.
Automatic detection of the IRQ number is not working on
BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
them manually through device tree. Use an interrupt-map to specify the
IRQ used by the devices on the bus. The first address is just an index,
because we do not have any special register.

The top-level axi bus may contain children representing attached cores
(devices). This is needed since some hardware details can't be auto
detected (e.g. IRQ numbers). Also some of the cores may be responsible
for extra things, e.g. ChipCommon providing access to the GPIO chip.

Example:

	axi@18000000 {
		compatible = "brcm,bus-axi";
		reg = <0x18000000 0x1000>;
		ranges = <0x00000000 0x18000000 0x00100000>;
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0x000fffff 0xffff>;
		interrupt-map =
			/* Ethernet Controller 0 */
			<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

			/* Ethernet Controller 1 */
			<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

			/* PCIe Controller 0 */
			<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			<0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;

		chipcommon {
			reg = <0x00000000 0x1000>;

			gpio-controller;
			#gpio-cells = <2>;
		};
	};