code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2016 MediaTek Inc.
 */

#include <dt-bindings/input/input.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/regulator/dlg,da9211-regulator.h>
#include <dt-bindings/gpio/gpio.h>
#include "mt8173.dtsi"

/ {
	aliases {
		mmc0 = &mmc0;
		mmc1 = &mmc1;
		mmc2 = &mmc3;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x80000000>;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm0 0 1000000>;
		power-supply = <&bl_fixed_reg>;
		enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;

		pinctrl-names = "default";
		pinctrl-0 = <&panel_backlight_en_pins>;
		status = "okay";
	};

	bl_fixed_reg: fixedregulator2 {
		compatible = "regulator-fixed";
		regulator-name = "bl_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		startup-delay-us = <1000>;
		enable-active-high;
		gpio = <&pio 32 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&bl_fixed_pins>;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	gpio_keys: gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&gpio_keys_pins>;

		switch-lid {
			label = "Lid";
			gpios = <&pio 69 GPIO_ACTIVE_LOW>;
			linux,code = <SW_LID>;
			linux,input-type = <EV_SW>;
			gpio-key,wakeup;
		};

		switch-power {
			label = "Power";
			gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_POWER>;
			debounce-interval = <30>;
			gpio-key,wakeup;
		};

		switch-tablet-mode {
			label = "Tablet_mode";
			gpios = <&pio 121 GPIO_ACTIVE_HIGH>;
			linux,code = <SW_TABLET_MODE>;
			linux,input-type = <EV_SW>;
			gpio-key,wakeup;
		};

		switch-volume-down {
			label = "Volume_down";
			gpios = <&pio 123 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_VOLUMEDOWN>;
		};

		switch-volume-up {
			label = "Volume_up";
			gpios = <&pio 124 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_VOLUMEUP>;
		};
	};

	panel: panel {
		compatible = "lg,lp120up1";
		power-supply = <&panel_fixed_3v3>;
		backlight = <&backlight>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&ps8640_out>;
			};
		};
	};

	panel_fixed_3v3: regulator1 {
		compatible = "regulator-fixed";
		regulator-name = "PANEL_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
		gpio = <&pio 41 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&panel_fixed_pins>;
	};

	ps8640_fixed_1v2: regulator2 {
		compatible = "regulator-fixed";
		regulator-name = "PS8640_1V2";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		regulator-enable-ramp-delay = <2000>;
		enable-active-high;
		regulator-boot-on;
		gpio = <&pio 30 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&ps8640_fixed_pins>;
	};

	sdio_fixed_3v3: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pio 85 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdio_fixed_3v3_pins>;
	};

	sound: sound {
		compatible = "mediatek,mt8173-rt5650";
		mediatek,audio-codec = <&rt5650 &hdmi0>;
		mediatek,platform = <&afe>;
		pinctrl-names = "default";
		pinctrl-0 = <&aud_i2s2>;

		mediatek,mclk = <1>;
		codec-capture {
			sound-dai = <&rt5650 1>;
		};
	};

	hdmicon: connector {
		compatible = "hdmi-connector";
		label = "hdmi";
		type = "a";
		ddc-i2c-bus = <&hdmiddc0>;

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&hdmi0_out>;
			};
		};
	};
};

&mfg_async {
	domain-supply = <&da9211_vgpu_reg>;
};

&cec {
	status = "okay";
};

&cpu0 {
	proc-supply = <&mt6397_vpca15_reg>;
};

&cpu1 {
	proc-supply = <&mt6397_vpca15_reg>;
};

&cpu2 {
	proc-supply = <&da9211_vcpu_reg>;
	sram-supply = <&mt6397_vsramca7_reg>;
};

&cpu3 {
	proc-supply = <&da9211_vcpu_reg>;
	sram-supply = <&mt6397_vsramca7_reg>;
};

&cpu_thermal {
	sustainable-power = <4500>; /* milliwatts */
	trips {
		threshold: trip-point0 {
			temperature = <60000>;
		};

		target: trip-point1 {
			temperature = <65000>;
		};
	};
};

&dsi0 {
	status = "okay";
	ports {
		port {
			dsi0_out: endpoint {
				remote-endpoint = <&ps8640_in>;
			};
		};
	};
};

&dpi0 {
	status = "okay";
};

&hdmi0 {
	status = "okay";
	ports {
		port@1 {
			reg = <1>;

			hdmi0_out: endpoint {
				remote-endpoint = <&hdmi_connector_in>;
			};
		};
	};
};

&hdmi_phy {
	status = "okay";
	mediatek,ibias = <0xc>;
};

&i2c0 {
	status = "okay";

	rt5650: audio-codec@1a {
		compatible = "realtek,rt5650";
		reg = <0x1a>;
		avdd-supply = <&mt6397_vgp1_reg>;
		cpvdd-supply = <&mt6397_vcama_reg>;
		interrupt-parent = <&pio>;
		interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
		pinctrl-names = "default";
		pinctrl-0 = <&rt5650_irq>;
		#sound-dai-cells = <1>;
		realtek,dmic1-data-pin = <2>;
		realtek,jd-mode = <2>;
	};

	ps8640: edp-bridge@8 {
		compatible = "parade,ps8640";
		reg = <0x8>;
		powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>;
		reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&ps8640_pins>;
		vdd12-supply = <&ps8640_fixed_1v2>;
		vdd33-supply = <&mt6397_vgp2_reg>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				ps8640_in: endpoint {
					remote-endpoint = <&dsi0_out>;
				};
			};

			port@1 {
				reg = <1>;

				ps8640_out: endpoint {
					remote-endpoint = <&panel_in>;
				};
			};
		};
	};
};

&i2c1 {
	clock-frequency = <1500000>;
	status = "okay";

	da9211: da9211@68 {
		compatible = "dlg,da9211";
		reg = <0x68>;
		interrupt-parent = <&pio>;
		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;

		regulators {
			da9211_vcpu_reg: BUCKA {
				regulator-name = "VBUCKA";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1310000>;
				regulator-min-microamp = <2000000>;
				regulator-max-microamp = <4400000>;
				regulator-ramp-delay = <10000>;
				regulator-always-on;
				regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
							   DA9211_BUCK_MODE_AUTO>;
			};

			da9211_vgpu_reg: BUCKB {
				regulator-name = "VBUCKB";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1310000>;
				regulator-min-microamp = <2000000>;
				regulator-max-microamp = <3000000>;
				regulator-ramp-delay = <10000>;
			};
		};
	};
};

&i2c2 {
	status = "okay";

	tpm: tpm@20 {
		compatible = "infineon,slb9645tt";
		reg = <0x20>;
		powered-while-suspended;
	};
};

&i2c3 {
	clock-frequency = <400000>;
	status = "okay";

	touchscreen: touchscreen@10 {
		compatible = "elan,ekth3500";
		reg = <0x10>;
		interrupt-parent = <&pio>;
		interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
	};
};

&i2c4 {
	clock-frequency = <400000>;
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&trackpad_irq>;

	trackpad: trackpad@15 {
		compatible = "elan,ekth3000";
		interrupt-parent = <&pio>;
		interrupts = <117 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x15>;
		vcc-supply = <&mt6397_vgp6_reg>;
		wakeup-source;
	};
};

&mipi_tx0 {
	status = "okay";
};

&mmc0 {
	status = "okay";
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc0_pins_default>;
	pinctrl-1 = <&mmc0_pins_uhs>;
	bus-width = <8>;
	max-frequency = <200000000>;
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	cap-mmc-hw-reset;
	hs400-ds-delay = <0x14015>;
	mediatek,hs200-cmd-int-delay = <30>;
	mediatek,hs400-cmd-int-delay = <14>;
	mediatek,hs400-cmd-resp-sel-rising;
	vmmc-supply = <&mt6397_vemc_3v3_reg>;
	vqmmc-supply = <&mt6397_vio18_reg>;
	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
	non-removable;
};

&mmc1 {
	status = "okay";
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_uhs>;
	bus-width = <4>;
	max-frequency = <200000000>;
	cap-sd-highspeed;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&mt6397_vmch_reg>;
	vqmmc-supply = <&mt6397_vmc_reg>;
};

&mmc3 {
	status = "okay";
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc3_pins_default>;
	pinctrl-1 = <&mmc3_pins_uhs>;
	bus-width = <4>;
	max-frequency = <200000000>;
	cap-sd-highspeed;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	keep-power-in-suspend;
	wakeup-source;
	cap-sdio-irq;
	vmmc-supply = <&sdio_fixed_3v3>;
	vqmmc-supply = <&mt6397_vgp3_reg>;
	non-removable;
	cap-power-off-card;

	#address-cells = <1>;
	#size-cells = <0>;

	btmrvl: btmrvl@2 {
		compatible = "marvell,sd8897-bt";
		reg = <2>;
		interrupt-parent = <&pio>;
		interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
		marvell,wakeup-pin = /bits/ 16 <0x0d>;
		marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
	};

	mwifiex: mwifiex@1 {
		compatible = "marvell,sd8897";
		reg = <1>;
		interrupt-parent = <&pio>;
		interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
		marvell,wakeup-pin = <3>;
	};
};

&nor_flash {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&nor_gpio1_pins>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <50000000>;
	};
};

&pio {
	gpio-line-names = "EC_INT_1V8",
			  "SD_CD_L",
			  "ALC5514_IRQ",
			  "ALC5650_IRQ",
			  /*
			   * AP_FLASH_WP_L is crossystem ABI. Schematics
			   * call it SFWP_B.
			   */
			  "AP_FLASH_WP_L",
			  "SFIN",
			  "SFCS0",
			  "SFHOLD",
			  "SFOUT",
			  "SFCK",
			  "WRAP_EVENT_S_EINT10",
			  "PMU_INT",
			  "I2S2_WS_ALC5650",
			  "I2S2_BCK_ALC5650",
			  "PWR_BTN_1V8",
			  "DA9212_IRQ",
			  "IDDIG",
			  "WATCHDOG",
			  "CEC",
			  "HDMISCK",
			  "HDMISD",
			  "HTPLG",
			  "MSDC3_DAT0",
			  "MSDC3_DAT1",
			  "MSDC3_DAT2",
			  "MSDC3_DAT3",
			  "MSDC3_CLK",
			  "MSDC3_CMD",
			  "USB_C0_OC_FLAGB",
			  "USBA_OC1_L",
			  "PS8640_1V2_ENABLE",
			  "THERM_ALERT_N",
			  "PANEL_LCD_POWER_EN",
			  "ANX7688_CHIP_PD_C",
			  "EC_IN_RW_1V8",
			  "ANX7688_1V_EN_C",
			  "USB_DP_HPD_C",
			  "TPM_DAVINT_N",
			  "MARVELL8897_IRQ",
			  "EN_USB_A0_PWR",
			  "USBA_A0_OC_L",
			  "EN_PP3300_DX_EDP",
			  "",
			  "SOC_I2C2_1V8_SDA_400K",
			  "SOC_I2C2_1V8_SCL_400K",
			  "SOC_I2C0_1V8_SDA_400K",
			  "SOC_I2C0_1V8_SCL_400K",
			  "EMMC_ID1",
			  "EMMC_ID0",
			  "MEM_CONFIG3",
			  "EMMC_ID2",
			  "MEM_CONFIG1",
			  "MEM_CONFIG2",
			  "BRD_ID2",
			  "MEM_CONFIG0",
			  "BRD_ID0",
			  "BRD_ID1",
			  "EMMC_DAT0",
			  "EMMC_DAT1",
			  "EMMC_DAT2",
			  "EMMC_DAT3",
			  "EMMC_DAT4",
			  "EMMC_DAT5",
			  "EMMC_DAT6",
			  "EMMC_DAT7",
			  "EMMC_CLK",
			  "EMMC_CMD",
			  "EMMC_RCLK",
			  "PLT_RST_L",
			  "LID_OPEN_1V8_L",
			  "AUDIO_SPI_MISO_R",
			  "",
			  "AC_OK_1V8",
			  "SD_DATA0",
			  "SD_DATA1",
			  "SD_DATA2",
			  "SD_DATA3",
			  "SD_CLK",
			  "SD_CMD",
			  "PWRAP_SPI0_MI",
			  "PWRAP_SPI0_MO",
			  "PWRAP_SPI0_CK",
			  "PWRAP_SPI0_CSN",
			  "",
			  "",
			  "WIFI_PDN",
			  "RTC32K_1V8",
			  "DISP_PWM0",
			  "TOUCHSCREEN_INT_L",
			  "",
			  "SRCLKENA0",
			  "SRCLKENA1",
			  "PS8640_MODE_CONF",
			  "TOUCHSCREEN_RESET_R",
			  "PLATFORM_PROCHOT_L",
			  "PANEL_POWER_EN",
			  "REC_MODE_L",
			  "EC_FW_UPDATE_L",
			  "ACCEL2_INT_L",
			  "HDMI_DP_INT",
			  "ACCELGYRO3_INT_L",
			  "ACCELGYRO4_INT_L",
			  "SPI_EC_CLK",
			  "SPI_EC_MI",
			  "SPI_EC_MO",
			  "SPI_EC_CSN",
			  "SOC_I2C3_1V8_SDA_400K",
			  "SOC_I2C3_1V8_SCL_400K",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "PS8640_SYSRSTN_1V8",
			  "APIN_MAX98090_DOUT2",
			  "TP_INT_1V8_L_R",
			  "RST_USB_HUB_R",
			  "BT_WAKE_L",
			  "ACCEL1_INT_L",
			  "TABLET_MODE_L",
			  "",
			  "V_UP_IN_L_R",
			  "V_DOWN_IN_L_R",
			  "SOC_I2C1_1V8_SDA_1M",
			  "SOC_I2C1_1V8_SCL_1M",
			  "PS8640_PDN_1V8",
			  "MAX98090_LRCLK",
			  "MAX98090_BCLK",
			  "MAX98090_MCLK",
			  "APOUT_MAX98090_DIN",
			  "APIN_MAX98090_DOUT",
			  "SOC_I2C4_1V8_SDA_400K",
			  "SOC_I2C4_1V8_SCL_400K";

	aud_i2s2: aud_i2s2 {
		pins1 {
			pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>,
				 <MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>,
				 <MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>,
				 <MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1>,
				 <MT8173_PIN_12_EINT12__FUNC_I2S2_WS>,
				 <MT8173_PIN_13_EINT13__FUNC_I2S2_BCK>,
				 <MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2>;
			bias-pull-down;
		};
	};

	bl_fixed_pins: bl_fixed_pins {
		pins1 {
			pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>;
			output-low;
		};
	};

	bt_wake_pins: bt_wake_pins {
		pins1 {
			pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>;
			bias-pull-up;
		};
	};

	disp_pwm0_pins: disp_pwm0_pins {
		pins1 {
			pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
			output-low;
		};
	};

	gpio_keys_pins: gpio_keys_pins {
		volume_pins {
			pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>,
				 <MT8173_PIN_124_KPCOL2__FUNC_GPIO124>;
			bias-pull-up;
		};

		tablet_mode_pins {
			pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>;
			bias-pull-up;
		};
	};

	hdmi_mux_pins: hdmi_mux_pins {
		pins1 {
			pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>;
		};
	};

	i2c1_pins_a: i2c1 {
		da9211_pins {
			pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>;
			bias-pull-up;
		};
	};

	mmc0_pins_default: mmc0default {
		pins_cmd_dat {
			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
			bias-pull-up;
		};

		pins_clk {
			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
			bias-pull-down;
		};

		pins_rst {
			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
			bias-pull-up;
		};
	};

	mmc1_pins_default: mmc1default {
		pins_cmd_dat {
			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
			input-enable;
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
		};

		pins_clk {
			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
			bias-pull-down;
			drive-strength = <MTK_DRIVE_4mA>;
		};

		pins_insert {
			pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>;
			bias-pull-up;
		};
	};

	mmc3_pins_default: mmc3default {
		pins_dat {
			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
			input-enable;
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
		};

		pins_cmd {
			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
			input-enable;
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
		};

		pins_clk {
			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
			bias-pull-down;
			drive-strength = <MTK_DRIVE_8mA>;
		};
	};

	mmc0_pins_uhs: mmc0 {
		pins_cmd_dat {
			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
			input-enable;
			drive-strength = <MTK_DRIVE_6mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
		};

		pins_clk {
			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
			drive-strength = <MTK_DRIVE_6mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
		};

		pins_ds {
			pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>;
			drive-strength = <MTK_DRIVE_10mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
		};

		pins_rst {
			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
			bias-pull-up;
		};
	};

	mmc1_pins_uhs: mmc1 {
		pins_cmd_dat {
			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
			input-enable;
			drive-strength = <MTK_DRIVE_6mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
		};

		pins_clk {
			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
		};
	};

	mmc3_pins_uhs: mmc3 {
		pins_dat {
			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
			input-enable;
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
		};

		pins_cmd {
			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
			input-enable;
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
		};

		pins_clk {
			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
		};
	};

	nor_gpio1_pins: nor {
		pins1 {
			pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>,
				 <MT8173_PIN_7_EINT7__FUNC_SFHOLD>,
				 <MT8173_PIN_8_EINT8__FUNC_SFIN>;
			input-enable;
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-up;
		};

		pins2 {
			pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>;
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-up;
		};

		pins_clk {
			pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>;
			input-enable;
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-up;
		};
	};

	panel_backlight_en_pins: panel_backlight_en_pins {
		pins1 {
			pinmux = <MT8173_PIN_95_PCM_TX__FUNC_GPIO95>;
		};
	};

	panel_fixed_pins: panel_fixed_pins {
		pins1 {
			pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>;
		};
	};

	ps8640_pins: ps8640_pins {
		pins1 {
			pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>,
				 <MT8173_PIN_115_URTS0__FUNC_GPIO115>,
				 <MT8173_PIN_127_LCM_RST__FUNC_GPIO127>;
		};
	};

	ps8640_fixed_pins: ps8640_fixed_pins {
		pins1 {
			pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>;
		};
	};

	rt5650_irq: rt5650_irq {
		pins1 {
			pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>;
			bias-pull-down;
		};
	};

	sdio_fixed_3v3_pins: sdio_fixed_3v3_pins {
		pins1 {
			pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>;
			output-low;
		};
	};

	spi_pins_a: spi1 {
		pins1 {
			pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>;
			bias-pull-up;
		};

		pins_spi {
			pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>,
				 <MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>,
				 <MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>,
				 <MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_>;
			bias-disable;
		};
	};

	trackpad_irq: trackpad_irq {
		pins1 {
			pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>;
			input-enable;
			bias-pull-up;
		};
	};

	usb_pins: usb {
		pins1 {
			pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>;
			output-high;
			bias-disable;
		};
	};

	wifi_wake_pins: wifi_wake_pins {
		pins1 {
			pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>;
			bias-pull-up;
		};
	};
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&disp_pwm0_pins>;
	status = "okay";
};

&pwrap {
	pmic: mt6397 {
		compatible = "mediatek,mt6397";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&pio>;
		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;

		clock: mt6397clock {
			compatible = "mediatek,mt6397-clk";
			#clock-cells = <1>;
		};

		pio6397: pinctrl {
			compatible = "mediatek,mt6397-pinctrl";
			pins-are-numbered;
			gpio-controller;
			#gpio-cells = <2>;
		};

		regulator: mt6397regulator {
			compatible = "mediatek,mt6397-regulator";

			mt6397_vpca15_reg: buck_vpca15 {
				regulator-compatible = "buck_vpca15";
				regulator-name = "vpca15";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
				regulator-allowed-modes = <0 1>;
			};

			mt6397_vpca7_reg: buck_vpca7 {
				regulator-compatible = "buck_vpca7";
				regulator-name = "vpca7";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-enable-ramp-delay = <115>;
				regulator-always-on;
			};

			mt6397_vsramca15_reg: buck_vsramca15 {
				regulator-compatible = "buck_vsramca15";
				regulator-name = "vsramca15";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};

			mt6397_vsramca7_reg: buck_vsramca7 {
				regulator-compatible = "buck_vsramca7";
				regulator-name = "vsramca7";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};

			mt6397_vcore_reg: buck_vcore {
				regulator-compatible = "buck_vcore";
				regulator-name = "vcore";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};

			mt6397_vgpu_reg: buck_vgpu {
				regulator-compatible = "buck_vgpu";
				regulator-name = "vgpu";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-enable-ramp-delay = <115>;
			};

			mt6397_vdrm_reg: buck_vdrm {
				regulator-compatible = "buck_vdrm";
				regulator-name = "vdrm";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1400000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};

			mt6397_vio18_reg: buck_vio18 {
				regulator-compatible = "buck_vio18";
				regulator-name = "vio18";
				regulator-min-microvolt = <1620000>;
				regulator-max-microvolt = <1980000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};

			mt6397_vtcxo_reg: ldo_vtcxo {
				regulator-compatible = "ldo_vtcxo";
				regulator-name = "vtcxo";
				regulator-always-on;
			};

			mt6397_va28_reg: ldo_va28 {
				regulator-compatible = "ldo_va28";
				regulator-name = "va28";
			};

			mt6397_vcama_reg: ldo_vcama {
				regulator-compatible = "ldo_vcama";
				regulator-name = "vcama";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vio28_reg: ldo_vio28 {
				regulator-compatible = "ldo_vio28";
				regulator-name = "vio28";
				regulator-always-on;
			};

			mt6397_vusb_reg: ldo_vusb {
				regulator-compatible = "ldo_vusb";
				regulator-name = "vusb";
			};

			mt6397_vmc_reg: ldo_vmc {
				regulator-compatible = "ldo_vmc";
				regulator-name = "vmc";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vmch_reg: ldo_vmch {
				regulator-compatible = "ldo_vmch";
				regulator-name = "vmch";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
				regulator-compatible = "ldo_vemc3v3";
				regulator-name = "vemc_3v3";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vgp1_reg: ldo_vgp1 {
				regulator-compatible = "ldo_vgp1";
				regulator-name = "vcamd";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <240>;
			};

			mt6397_vgp2_reg: ldo_vgp2 {
				regulator-compatible = "ldo_vgp2";
				regulator-name = "vcamio";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vgp3_reg: ldo_vgp3 {
				regulator-compatible = "ldo_vgp3";
				regulator-name = "vcamaf";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vgp4_reg: ldo_vgp4 {
				regulator-compatible = "ldo_vgp4";
				regulator-name = "vgp4";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vgp5_reg: ldo_vgp5 {
				regulator-compatible = "ldo_vgp5";
				regulator-name = "vgp5";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vgp6_reg: ldo_vgp6 {
				regulator-compatible = "ldo_vgp6";
				regulator-name = "vgp6";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
				regulator-always-on;
			};

			mt6397_vibr_reg: ldo_vibr {
				regulator-compatible = "ldo_vibr";
				regulator-name = "vibr";
				regulator-min-microvolt = <1300000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};
		};

		rtc: mt6397rtc {
			compatible = "mediatek,mt6397-rtc";
		};

		syscfg_pctl_pmic: syscfg_pctl_pmic@c000 {
			compatible = "mediatek,mt6397-pctl-pmic-syscfg",
				     "syscon";
			reg = <0 0x0000c000 0 0x0108>;
		};
	};
};

&spi {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_pins_a>;
	mediatek,pad-select = <1>;
	status = "okay";
	/* clients */
	cros_ec: ec@0 {
		compatible = "google,cros-ec-spi";
		reg = <0x0>;
		spi-max-frequency = <12000000>;
		interrupt-parent = <&pio>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
		google,cros-ec-spi-msg-delay = <500>;

		i2c_tunnel: i2c-tunnel0 {
			compatible = "google,cros-ec-i2c-tunnel";
			google,remote-bus = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			battery: sbs-battery@b {
				compatible = "sbs,sbs-battery";
				reg = <0xb>;
				sbs,i2c-retry-count = <2>;
				sbs,poll-retry-count = <1>;
			};
		};
	};
};

&ssusb {
	dr_mode = "host";
	wakeup-source;
	vusb33-supply = <&mt6397_vusb_reg>;
	status = "okay";
};

&thermal {
	bank0-supply = <&mt6397_vpca15_reg>;
	bank1-supply = <&da9211_vcpu_reg>;
};

&uart0 {
	status = "okay";
};

&usb_host {
	pinctrl-names = "default";
	pinctrl-0 = <&usb_pins>;
	vusb33-supply = <&mt6397_vusb_reg>;
	status = "okay";
};

#include <arm/cros-ec-keyboard.dtsi>


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Eddie Huang <eddie.huang@mediatek.com>
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "mt8173.dtsi"

/ {
	model = "MediaTek MT8173 evaluation board";
	compatible = "mediatek,mt8173-evb", "mediatek,mt8173";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x80000000>;
	};

	chosen { };

	connector {
		compatible = "hdmi-connector";
		label = "hdmi";
		type = "d";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&hdmi0_out>;
			};
		};
	};

	extcon_usb: extcon_iddig {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
	};

	usb_p1_vbus: regulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "usb_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	usb_p0_vbus: regulator@1 {
		compatible = "regulator-fixed";
		regulator-name = "vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&pio 9 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&mfg_async {
	domain-supply = <&da9211_vgpu_reg>;
};

&cec {
	status = "okay";
};

&cpu0 {
	proc-supply = <&mt6397_vpca15_reg>;
};

&cpu1 {
	proc-supply = <&mt6397_vpca15_reg>;
};

&cpu2 {
	proc-supply = <&da9211_vcpu_reg>;
	sram-supply = <&mt6397_vsramca7_reg>;
};

&cpu3 {
	proc-supply = <&da9211_vcpu_reg>;
	sram-supply = <&mt6397_vsramca7_reg>;
};

&dpi0 {
	status = "okay";
};

&hdmi_phy {
	status = "okay";
};

&hdmi0 {
	status = "okay";

	ports {
		port@1 {
			reg = <1>;

			hdmi0_out: endpoint {
				remote-endpoint = <&hdmi_connector_in>;
			};
		};
	};
};

&i2c1 {
	status = "okay";

	buck: da9211@68 {
		compatible = "dlg,da9211";
		reg = <0x68>;

		regulators {
			da9211_vcpu_reg: BUCKA {
				regulator-name = "VBUCKA";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1310000>;
				regulator-min-microamp = <2000000>;
				regulator-max-microamp = <4400000>;
				regulator-ramp-delay = <10000>;
				regulator-always-on;
			};

			da9211_vgpu_reg: BUCKB {
				regulator-name = "VBUCKB";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1310000>;
				regulator-min-microamp = <2000000>;
				regulator-max-microamp = <3000000>;
				regulator-ramp-delay = <10000>;
			};
		};
	};
};

&mmc0 {
	status = "okay";
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc0_pins_default>;
	pinctrl-1 = <&mmc0_pins_uhs>;
	bus-width = <8>;
	max-frequency = <50000000>;
	cap-mmc-highspeed;
	mediatek,hs200-cmd-int-delay = <26>;
	mediatek,hs400-cmd-int-delay = <14>;
	mediatek,hs400-cmd-resp-sel-rising;
	vmmc-supply = <&mt6397_vemc_3v3_reg>;
	vqmmc-supply = <&mt6397_vio18_reg>;
	non-removable;
};

&mmc1 {
	status = "okay";
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_uhs>;
	bus-width = <4>;
	max-frequency = <50000000>;
	cap-sd-highspeed;
	sd-uhs-sdr25;
	cd-gpios = <&pio 132 0>;
	vmmc-supply = <&mt6397_vmch_reg>;
	vqmmc-supply = <&mt6397_vmc_reg>;
};

&pio {
	disp_pwm0_pins: disp_pwm0_pins {
		pins1 {
			pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
			output-low;
		};
	};

	mmc0_pins_default: mmc0default {
		pins_cmd_dat {
			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
			input-enable;
			bias-pull-up;
		};

		pins_clk {
			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
			bias-pull-down;
		};

		pins_rst {
			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
			bias-pull-up;
		};
	};

	mmc1_pins_default: mmc1default {
		pins_cmd_dat {
			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
			input-enable;
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
		};

		pins_clk {
			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
			bias-pull-down;
			drive-strength = <MTK_DRIVE_4mA>;
		};

		pins_insert {
			pinmux = <MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132>;
			bias-pull-up;
		};
	};

	mmc0_pins_uhs: mmc0 {
		pins_cmd_dat {
			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
			input-enable;
			drive-strength = <MTK_DRIVE_2mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
		};

		pins_clk {
			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
			drive-strength = <MTK_DRIVE_2mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
		};

		pins_rst {
			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
			bias-pull-up;
		};
	};

	mmc1_pins_uhs: mmc1 {
		pins_cmd_dat {
			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
			input-enable;
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
		};

		pins_clk {
			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
			drive-strength = <MTK_DRIVE_4mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
		};
	};

	usb_id_pins_float: usb_iddig_pull_up {
		pins_iddig {
			pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>;
			bias-pull-up;
		};
	};

	usb_id_pins_ground: usb_iddig_pull_down {
		pins_iddig {
			pinmux = <MT8173_PIN_16_IDDIG__FUNC_IDDIG>;
			bias-pull-down;
		};
	};
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&disp_pwm0_pins>;
	status = "okay";
};

&pwrap {
	/* Only MT8173 E1 needs USB power domain */
	power-domains = <&spm MT8173_POWER_DOMAIN_USB>;

	pmic: mt6397 {
		compatible = "mediatek,mt6397";
		interrupt-parent = <&pio>;
		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;

		mt6397regulator: mt6397regulator {
			compatible = "mediatek,mt6397-regulator";

			mt6397_vpca15_reg: buck_vpca15 {
				regulator-compatible = "buck_vpca15";
				regulator-name = "vpca15";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};

			mt6397_vpca7_reg: buck_vpca7 {
				regulator-compatible = "buck_vpca7";
				regulator-name = "vpca7";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-enable-ramp-delay = <115>;
			};

			mt6397_vsramca15_reg: buck_vsramca15 {
				regulator-compatible = "buck_vsramca15";
				regulator-name = "vsramca15";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};

			mt6397_vsramca7_reg: buck_vsramca7 {
				regulator-compatible = "buck_vsramca7";
				regulator-name = "vsramca7";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};

			mt6397_vcore_reg: buck_vcore {
				regulator-compatible = "buck_vcore";
				regulator-name = "vcore";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};

			mt6397_vgpu_reg: buck_vgpu {
				regulator-compatible = "buck_vgpu";
				regulator-name = "vgpu";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-enable-ramp-delay = <115>;
			};

			mt6397_vdrm_reg: buck_vdrm {
				regulator-compatible = "buck_vdrm";
				regulator-name = "vdrm";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1400000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};

			mt6397_vio18_reg: buck_vio18 {
				regulator-compatible = "buck_vio18";
				regulator-name = "vio18";
				regulator-min-microvolt = <1620000>;
				regulator-max-microvolt = <1980000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
			};

			mt6397_vtcxo_reg: ldo_vtcxo {
				regulator-compatible = "ldo_vtcxo";
				regulator-name = "vtcxo";
				regulator-always-on;
			};

			mt6397_va28_reg: ldo_va28 {
				regulator-compatible = "ldo_va28";
				regulator-name = "va28";
				regulator-always-on;
			};

			mt6397_vcama_reg: ldo_vcama {
				regulator-compatible = "ldo_vcama";
				regulator-name = "vcama";
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vio28_reg: ldo_vio28 {
				regulator-compatible = "ldo_vio28";
				regulator-name = "vio28";
				regulator-always-on;
			};

			mt6397_vusb_reg: ldo_vusb {
				regulator-compatible = "ldo_vusb";
				regulator-name = "vusb";
			};

			mt6397_vmc_reg: ldo_vmc {
				regulator-compatible = "ldo_vmc";
				regulator-name = "vmc";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vmch_reg: ldo_vmch {
				regulator-compatible = "ldo_vmch";
				regulator-name = "vmch";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
				regulator-compatible = "ldo_vemc3v3";
				regulator-name = "vemc_3v3";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vgp1_reg: ldo_vgp1 {
				regulator-compatible = "ldo_vgp1";
				regulator-name = "vcamd";
				regulator-min-microvolt = <1220000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <240>;
			};

			mt6397_vgp2_reg: ldo_vgp2 {
				regulator-compatible = "ldo_vgp2";
				regulator-name = "vcamio";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vgp3_reg: ldo_vgp3 {
				regulator-compatible = "ldo_vgp3";
				regulator-name = "vcamaf";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vgp4_reg: ldo_vgp4 {
				regulator-compatible = "ldo_vgp4";
				regulator-name = "vgp4";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vgp5_reg: ldo_vgp5 {
				regulator-compatible = "ldo_vgp5";
				regulator-name = "vgp5";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vgp6_reg: ldo_vgp6 {
				regulator-compatible = "ldo_vgp6";
				regulator-name = "vgp6";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};

			mt6397_vibr_reg: ldo_vibr {
				regulator-compatible = "ldo_vibr";
				regulator-name = "vibr";
				regulator-min-microvolt = <1300000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <218>;
			};
		};
	};
};

&pio {
	spi_pins_a: spi0 {
		pins_spi {
			pinmux = <MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_>,
				<MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_>,
				<MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_>,
				<MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_>;
		};
	};
};

&spi {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_pins_a>;
	mediatek,pad-select = <0>;
	status = "okay";
};

&ssusb {
	vusb33-supply = <&mt6397_vusb_reg>;
	vbus-supply = <&usb_p0_vbus>;
	extcon = <&extcon_usb>;
	dr_mode = "otg";
	wakeup-source;
	pinctrl-names = "default";
	pinctrl-0 = <&usb_id_pins_float>;
	status = "okay";
};

&uart0 {
	status = "okay";
};

&usb_host {
	vusb33-supply = <&mt6397_vusb_reg>;
	vbus-supply = <&usb_p1_vbus>;
	status = "okay";
};

repo_name: angery/linux


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
 */

#ifndef __DTS_MT8173_PINFUNC_H
#define __DTS_MT8173_PINFUNC_H

#include <dt-bindings/pinctrl/mt65xx.h>

#define MT8173_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define MT8173_PIN_0_EINT0__FUNC_IRDA_PDN (MTK_PIN_NO(0) | 1)
#define MT8173_PIN_0_EINT0__FUNC_I2S1_WS (MTK_PIN_NO(0) | 2)
#define MT8173_PIN_0_EINT0__FUNC_AUD_SPDIF (MTK_PIN_NO(0) | 3)
#define MT8173_PIN_0_EINT0__FUNC_UTXD0 (MTK_PIN_NO(0) | 4)
#define MT8173_PIN_0_EINT0__FUNC_DBG_MON_A_20_ (MTK_PIN_NO(0) | 7)

#define MT8173_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
#define MT8173_PIN_1_EINT1__FUNC_IRDA_RXD (MTK_PIN_NO(1) | 1)
#define MT8173_PIN_1_EINT1__FUNC_I2S1_BCK (MTK_PIN_NO(1) | 2)
#define MT8173_PIN_1_EINT1__FUNC_SDA5 (MTK_PIN_NO(1) | 3)
#define MT8173_PIN_1_EINT1__FUNC_URXD0 (MTK_PIN_NO(1) | 4)
#define MT8173_PIN_1_EINT1__FUNC_DBG_MON_A_21_ (MTK_PIN_NO(1) | 7)

#define MT8173_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
#define MT8173_PIN_2_EINT2__FUNC_IRDA_TXD (MTK_PIN_NO(2) | 1)
#define MT8173_PIN_2_EINT2__FUNC_I2S1_MCK (MTK_PIN_NO(2) | 2)
#define MT8173_PIN_2_EINT2__FUNC_SCL5 (MTK_PIN_NO(2) | 3)
#define MT8173_PIN_2_EINT2__FUNC_UTXD3 (MTK_PIN_NO(2) | 4)
#define MT8173_PIN_2_EINT2__FUNC_DBG_MON_A_22_ (MTK_PIN_NO(2) | 7)

#define MT8173_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
#define MT8173_PIN_3_EINT3__FUNC_DSI1_TE (MTK_PIN_NO(3) | 1)
#define MT8173_PIN_3_EINT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(3) | 2)
#define MT8173_PIN_3_EINT3__FUNC_SDA3 (MTK_PIN_NO(3) | 3)
#define MT8173_PIN_3_EINT3__FUNC_URXD3 (MTK_PIN_NO(3) | 4)
#define MT8173_PIN_3_EINT3__FUNC_DBG_MON_A_23_ (MTK_PIN_NO(3) | 7)

#define MT8173_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
#define MT8173_PIN_4_EINT4__FUNC_DISP_PWM1 (MTK_PIN_NO(4) | 1)
#define MT8173_PIN_4_EINT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(4) | 2)
#define MT8173_PIN_4_EINT4__FUNC_SCL3 (MTK_PIN_NO(4) | 3)
#define MT8173_PIN_4_EINT4__FUNC_UCTS3 (MTK_PIN_NO(4) | 4)
#define MT8173_PIN_4_EINT4__FUNC_SFWP_B (MTK_PIN_NO(4) | 6)

#define MT8173_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
#define MT8173_PIN_5_EINT5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 1)
#define MT8173_PIN_5_EINT5__FUNC_I2S2_WS (MTK_PIN_NO(5) | 2)
#define MT8173_PIN_5_EINT5__FUNC_SPI_CK_3_ (MTK_PIN_NO(5) | 3)
#define MT8173_PIN_5_EINT5__FUNC_URTS3 (MTK_PIN_NO(5) | 4)
#define MT8173_PIN_5_EINT5__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(5) | 5)
#define MT8173_PIN_5_EINT5__FUNC_SFOUT (MTK_PIN_NO(5) | 6)

#define MT8173_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
#define MT8173_PIN_6_EINT6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 1)
#define MT8173_PIN_6_EINT6__FUNC_I2S2_BCK (MTK_PIN_NO(6) | 2)
#define MT8173_PIN_6_EINT6__FUNC_SPI_MI_3_ (MTK_PIN_NO(6) | 3)
#define MT8173_PIN_6_EINT6__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(6) | 5)
#define MT8173_PIN_6_EINT6__FUNC_SFCS0 (MTK_PIN_NO(6) | 6)

#define MT8173_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
#define MT8173_PIN_7_EINT7__FUNC_PCM1_DI (MTK_PIN_NO(7) | 1)
#define MT8173_PIN_7_EINT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(7) | 2)
#define MT8173_PIN_7_EINT7__FUNC_SPI_MO_3_ (MTK_PIN_NO(7) | 3)
#define MT8173_PIN_7_EINT7__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(7) | 5)
#define MT8173_PIN_7_EINT7__FUNC_SFHOLD (MTK_PIN_NO(7) | 6)

#define MT8173_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
#define MT8173_PIN_8_EINT8__FUNC_PCM1_DO (MTK_PIN_NO(8) | 1)
#define MT8173_PIN_8_EINT8__FUNC_I2S2_DI_2 (MTK_PIN_NO(8) | 2)
#define MT8173_PIN_8_EINT8__FUNC_SPI_CS_3_ (MTK_PIN_NO(8) | 3)
#define MT8173_PIN_8_EINT8__FUNC_AUD_SPDIF (MTK_PIN_NO(8) | 4)
#define MT8173_PIN_8_EINT8__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(8) | 5)
#define MT8173_PIN_8_EINT8__FUNC_SFIN (MTK_PIN_NO(8) | 6)

#define MT8173_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(9) | 1)
#define MT8173_PIN_9_EINT9__FUNC_I2S2_MCK (MTK_PIN_NO(9) | 2)
#define MT8173_PIN_9_EINT9__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(9) | 4)
#define MT8173_PIN_9_EINT9__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(9) | 5)
#define MT8173_PIN_9_EINT9__FUNC_SFCK (MTK_PIN_NO(9) | 6)

#define MT8173_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
#define MT8173_PIN_10_EINT10__FUNC_CLKM0 (MTK_PIN_NO(10) | 1)
#define MT8173_PIN_10_EINT10__FUNC_DSI1_TE (MTK_PIN_NO(10) | 2)
#define MT8173_PIN_10_EINT10__FUNC_DISP_PWM1 (MTK_PIN_NO(10) | 3)
#define MT8173_PIN_10_EINT10__FUNC_PWM4 (MTK_PIN_NO(10) | 4)
#define MT8173_PIN_10_EINT10__FUNC_IRDA_RXD (MTK_PIN_NO(10) | 5)

#define MT8173_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
#define MT8173_PIN_11_EINT11__FUNC_CLKM1 (MTK_PIN_NO(11) | 1)
#define MT8173_PIN_11_EINT11__FUNC_I2S3_WS (MTK_PIN_NO(11) | 2)
#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(11) | 3)
#define MT8173_PIN_11_EINT11__FUNC_PWM5 (MTK_PIN_NO(11) | 4)
#define MT8173_PIN_11_EINT11__FUNC_IRDA_TXD (MTK_PIN_NO(11) | 5)
#define MT8173_PIN_11_EINT11__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(11) | 6)
#define MT8173_PIN_11_EINT11__FUNC_DBG_MON_B_30_ (MTK_PIN_NO(11) | 7)

#define MT8173_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
#define MT8173_PIN_12_EINT12__FUNC_CLKM2 (MTK_PIN_NO(12) | 1)
#define MT8173_PIN_12_EINT12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 2)
#define MT8173_PIN_12_EINT12__FUNC_SRCLKENA0 (MTK_PIN_NO(12) | 3)
#define MT8173_PIN_12_EINT12__FUNC_I2S2_WS (MTK_PIN_NO(12) | 5)
#define MT8173_PIN_12_EINT12__FUNC_DBG_MON_B_32_ (MTK_PIN_NO(12) | 7)

#define MT8173_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
#define MT8173_PIN_13_EINT13__FUNC_CLKM3 (MTK_PIN_NO(13) | 1)
#define MT8173_PIN_13_EINT13__FUNC_I2S3_MCK (MTK_PIN_NO(13) | 2)
#define MT8173_PIN_13_EINT13__FUNC_SRCLKENA0 (MTK_PIN_NO(13) | 3)
#define MT8173_PIN_13_EINT13__FUNC_I2S2_BCK (MTK_PIN_NO(13) | 5)
#define MT8173_PIN_13_EINT13__FUNC_DBG_MON_A_32_ (MTK_PIN_NO(13) | 7)

#define MT8173_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
#define MT8173_PIN_14_EINT14__FUNC_CMDAT0 (MTK_PIN_NO(14) | 1)
#define MT8173_PIN_14_EINT14__FUNC_CMCSD0 (MTK_PIN_NO(14) | 2)
#define MT8173_PIN_14_EINT14__FUNC_CLKM2 (MTK_PIN_NO(14) | 4)
#define MT8173_PIN_14_EINT14__FUNC_DBG_MON_B_6_ (MTK_PIN_NO(14) | 7)

#define MT8173_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
#define MT8173_PIN_15_EINT15__FUNC_CMDAT1 (MTK_PIN_NO(15) | 1)
#define MT8173_PIN_15_EINT15__FUNC_CMCSD1 (MTK_PIN_NO(15) | 2)
#define MT8173_PIN_15_EINT15__FUNC_CMFLASH (MTK_PIN_NO(15) | 3)
#define MT8173_PIN_15_EINT15__FUNC_CLKM3 (MTK_PIN_NO(15) | 4)
#define MT8173_PIN_15_EINT15__FUNC_DBG_MON_B_29_ (MTK_PIN_NO(15) | 7)

#define MT8173_PIN_16_IDDIG__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
#define MT8173_PIN_16_IDDIG__FUNC_IDDIG (MTK_PIN_NO(16) | 1)
#define MT8173_PIN_16_IDDIG__FUNC_CMFLASH (MTK_PIN_NO(16) | 2)
#define MT8173_PIN_16_IDDIG__FUNC_PWM5 (MTK_PIN_NO(16) | 4)

#define MT8173_PIN_17_WATCHDOG__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
#define MT8173_PIN_17_WATCHDOG__FUNC_WATCHDOG_AO (MTK_PIN_NO(17) | 1)

#define MT8173_PIN_18_CEC__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
#define MT8173_PIN_18_CEC__FUNC_CEC (MTK_PIN_NO(18) | 1)

#define MT8173_PIN_19_HDMISCK__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
#define MT8173_PIN_19_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(19) | 1)
#define MT8173_PIN_19_HDMISCK__FUNC_HDCP_SCL (MTK_PIN_NO(19) | 2)

#define MT8173_PIN_20_HDMISD__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
#define MT8173_PIN_20_HDMISD__FUNC_HDMISD (MTK_PIN_NO(20) | 1)
#define MT8173_PIN_20_HDMISD__FUNC_HDCP_SDA (MTK_PIN_NO(20) | 2)

#define MT8173_PIN_21_HTPLG__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
#define MT8173_PIN_21_HTPLG__FUNC_HTPLG (MTK_PIN_NO(21) | 1)

#define MT8173_PIN_22_MSDC3_DAT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
#define MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(22) | 1)

#define MT8173_PIN_23_MSDC3_DAT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
#define MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(23) | 1)

#define MT8173_PIN_24_MSDC3_DAT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
#define MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(24) | 1)

#define MT8173_PIN_25_MSDC3_DAT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
#define MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(25) | 1)

#define MT8173_PIN_26_MSDC3_CLK__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
#define MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(26) | 1)

#define MT8173_PIN_27_MSDC3_CMD__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
#define MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(27) | 1)

#define MT8173_PIN_28_MSDC3_DSL__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
#define MT8173_PIN_28_MSDC3_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(28) | 1)

#define MT8173_PIN_29_UCTS2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
#define MT8173_PIN_29_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(29) | 1)

#define MT8173_PIN_30_URTS2__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
#define MT8173_PIN_30_URTS2__FUNC_URTS2 (MTK_PIN_NO(30) | 1)

#define MT8173_PIN_31_URXD2__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
#define MT8173_PIN_31_URXD2__FUNC_URXD2 (MTK_PIN_NO(31) | 1)
#define MT8173_PIN_31_URXD2__FUNC_UTXD2 (MTK_PIN_NO(31) | 2)

#define MT8173_PIN_32_UTXD2__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
#define MT8173_PIN_32_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(32) | 1)
#define MT8173_PIN_32_UTXD2__FUNC_URXD2 (MTK_PIN_NO(32) | 2)

#define MT8173_PIN_33_DAICLK__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
#define MT8173_PIN_33_DAICLK__FUNC_MRG_CLK (MTK_PIN_NO(33) | 1)
#define MT8173_PIN_33_DAICLK__FUNC_PCM0_CLK (MTK_PIN_NO(33) | 2)

#define MT8173_PIN_34_DAIPCMIN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
#define MT8173_PIN_34_DAIPCMIN__FUNC_MRG_DI (MTK_PIN_NO(34) | 1)
#define MT8173_PIN_34_DAIPCMIN__FUNC_PCM0_DI (MTK_PIN_NO(34) | 2)

#define MT8173_PIN_35_DAIPCMOUT__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
#define MT8173_PIN_35_DAIPCMOUT__FUNC_MRG_DO (MTK_PIN_NO(35) | 1)
#define MT8173_PIN_35_DAIPCMOUT__FUNC_PCM0_DO (MTK_PIN_NO(35) | 2)

#define MT8173_PIN_36_DAISYNC__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
#define MT8173_PIN_36_DAISYNC__FUNC_MRG_SYNC (MTK_PIN_NO(36) | 1)
#define MT8173_PIN_36_DAISYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(36) | 2)

#define MT8173_PIN_37_EINT16__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(37) | 1)
#define MT8173_PIN_37_EINT16__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(37) | 2)
#define MT8173_PIN_37_EINT16__FUNC_PWM0 (MTK_PIN_NO(37) | 3)
#define MT8173_PIN_37_EINT16__FUNC_PWM1 (MTK_PIN_NO(37) | 4)
#define MT8173_PIN_37_EINT16__FUNC_PWM2 (MTK_PIN_NO(37) | 5)
#define MT8173_PIN_37_EINT16__FUNC_CLKM0 (MTK_PIN_NO(37) | 6)

#define MT8173_PIN_38_CONN_RST__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(38) | 1)
#define MT8173_PIN_38_CONN_RST__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(38) | 2)
#define MT8173_PIN_38_CONN_RST__FUNC_CLKM1 (MTK_PIN_NO(38) | 6)

#define MT8173_PIN_39_CM2MCLK__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
#define MT8173_PIN_39_CM2MCLK__FUNC_CM2MCLK (MTK_PIN_NO(39) | 1)
#define MT8173_PIN_39_CM2MCLK__FUNC_CMCSD0 (MTK_PIN_NO(39) | 2)
#define MT8173_PIN_39_CM2MCLK__FUNC_DBG_MON_A_17_ (MTK_PIN_NO(39) | 7)

#define MT8173_PIN_40_CMPCLK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
#define MT8173_PIN_40_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(40) | 1)
#define MT8173_PIN_40_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(40) | 2)
#define MT8173_PIN_40_CMPCLK__FUNC_CMCSD2 (MTK_PIN_NO(40) | 3)
#define MT8173_PIN_40_CMPCLK__FUNC_DBG_MON_A_18_ (MTK_PIN_NO(40) | 7)

#define MT8173_PIN_41_CMMCLK__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
#define MT8173_PIN_41_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(41) | 1)
#define MT8173_PIN_41_CMMCLK__FUNC_DBG_MON_A_19_ (MTK_PIN_NO(41) | 7)

#define MT8173_PIN_42_DSI_TE__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
#define MT8173_PIN_42_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(42) | 1)

#define MT8173_PIN_43_SDA2__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
#define MT8173_PIN_43_SDA2__FUNC_SDA2 (MTK_PIN_NO(43) | 1)

#define MT8173_PIN_44_SCL2__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
#define MT8173_PIN_44_SCL2__FUNC_SCL2 (MTK_PIN_NO(44) | 1)

#define MT8173_PIN_45_SDA0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
#define MT8173_PIN_45_SDA0__FUNC_SDA0 (MTK_PIN_NO(45) | 1)

#define MT8173_PIN_46_SCL0__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
#define MT8173_PIN_46_SCL0__FUNC_SCL0 (MTK_PIN_NO(46) | 1)

#define MT8173_PIN_47_RDN0_A__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
#define MT8173_PIN_47_RDN0_A__FUNC_CMDAT2 (MTK_PIN_NO(47) | 1)

#define MT8173_PIN_48_RDP0_A__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
#define MT8173_PIN_48_RDP0_A__FUNC_CMDAT3 (MTK_PIN_NO(48) | 1)

#define MT8173_PIN_49_RDN1_A__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
#define MT8173_PIN_49_RDN1_A__FUNC_CMDAT4 (MTK_PIN_NO(49) | 1)

#define MT8173_PIN_50_RDP1_A__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
#define MT8173_PIN_50_RDP1_A__FUNC_CMDAT5 (MTK_PIN_NO(50) | 1)

#define MT8173_PIN_51_RCN_A__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
#define MT8173_PIN_51_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(51) | 1)

#define MT8173_PIN_52_RCP_A__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
#define MT8173_PIN_52_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(52) | 1)

#define MT8173_PIN_53_RDN2_A__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
#define MT8173_PIN_53_RDN2_A__FUNC_CMDAT8 (MTK_PIN_NO(53) | 1)
#define MT8173_PIN_53_RDN2_A__FUNC_CMCSD3 (MTK_PIN_NO(53) | 2)

#define MT8173_PIN_54_RDP2_A__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
#define MT8173_PIN_54_RDP2_A__FUNC_CMDAT9 (MTK_PIN_NO(54) | 1)
#define MT8173_PIN_54_RDP2_A__FUNC_CMCSD2 (MTK_PIN_NO(54) | 2)

#define MT8173_PIN_55_RDN3_A__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
#define MT8173_PIN_55_RDN3_A__FUNC_CMHSYNC (MTK_PIN_NO(55) | 1)
#define MT8173_PIN_55_RDN3_A__FUNC_CMCSD1 (MTK_PIN_NO(55) | 2)

#define MT8173_PIN_56_RDP3_A__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
#define MT8173_PIN_56_RDP3_A__FUNC_CMVSYNC (MTK_PIN_NO(56) | 1)
#define MT8173_PIN_56_RDP3_A__FUNC_CMCSD0 (MTK_PIN_NO(56) | 2)

#define MT8173_PIN_57_MSDC0_DAT0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
#define MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(57) | 1)
#define MT8173_PIN_57_MSDC0_DAT0__FUNC_I2S1_WS (MTK_PIN_NO(57) | 2)
#define MT8173_PIN_57_MSDC0_DAT0__FUNC_DBG_MON_B_7_ (MTK_PIN_NO(57) | 7)

#define MT8173_PIN_58_MSDC0_DAT1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
#define MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(58) | 1)
#define MT8173_PIN_58_MSDC0_DAT1__FUNC_I2S1_BCK (MTK_PIN_NO(58) | 2)
#define MT8173_PIN_58_MSDC0_DAT1__FUNC_DBG_MON_B_8_ (MTK_PIN_NO(58) | 7)

#define MT8173_PIN_59_MSDC0_DAT2__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
#define MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(59) | 1)
#define MT8173_PIN_59_MSDC0_DAT2__FUNC_I2S1_MCK (MTK_PIN_NO(59) | 2)
#define MT8173_PIN_59_MSDC0_DAT2__FUNC_DBG_MON_B_9_ (MTK_PIN_NO(59) | 7)

#define MT8173_PIN_60_MSDC0_DAT3__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
#define MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(60) | 1)
#define MT8173_PIN_60_MSDC0_DAT3__FUNC_I2S1_DO_1 (MTK_PIN_NO(60) | 2)
#define MT8173_PIN_60_MSDC0_DAT3__FUNC_DBG_MON_B_10_ (MTK_PIN_NO(60) | 7)

#define MT8173_PIN_61_MSDC0_DAT4__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
#define MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(61) | 1)
#define MT8173_PIN_61_MSDC0_DAT4__FUNC_I2S1_DO_2 (MTK_PIN_NO(61) | 2)
#define MT8173_PIN_61_MSDC0_DAT4__FUNC_DBG_MON_B_11_ (MTK_PIN_NO(61) | 7)

#define MT8173_PIN_62_MSDC0_DAT5__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
#define MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(62) | 1)
#define MT8173_PIN_62_MSDC0_DAT5__FUNC_I2S2_WS (MTK_PIN_NO(62) | 2)
#define MT8173_PIN_62_MSDC0_DAT5__FUNC_DBG_MON_B_12_ (MTK_PIN_NO(62) | 7)

#define MT8173_PIN_63_MSDC0_DAT6__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
#define MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(63) | 1)
#define MT8173_PIN_63_MSDC0_DAT6__FUNC_I2S2_BCK (MTK_PIN_NO(63) | 2)
#define MT8173_PIN_63_MSDC0_DAT6__FUNC_DBG_MON_B_13_ (MTK_PIN_NO(63) | 7)

#define MT8173_PIN_64_MSDC0_DAT7__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
#define MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(64) | 1)
#define MT8173_PIN_64_MSDC0_DAT7__FUNC_I2S2_DI_1 (MTK_PIN_NO(64) | 2)
#define MT8173_PIN_64_MSDC0_DAT7__FUNC_DBG_MON_B_14_ (MTK_PIN_NO(64) | 7)

#define MT8173_PIN_65_MSDC0_CLK__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
#define MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(65) | 1)
#define MT8173_PIN_65_MSDC0_CLK__FUNC_DBG_MON_B_16_ (MTK_PIN_NO(65) | 7)

#define MT8173_PIN_66_MSDC0_CMD__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
#define MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(66) | 1)
#define MT8173_PIN_66_MSDC0_CMD__FUNC_I2S2_DI_2 (MTK_PIN_NO(66) | 2)
#define MT8173_PIN_66_MSDC0_CMD__FUNC_DBG_MON_B_15_ (MTK_PIN_NO(66) | 7)

#define MT8173_PIN_67_MSDC0_DSL__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
#define MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(67) | 1)
#define MT8173_PIN_67_MSDC0_DSL__FUNC_DBG_MON_B_17_ (MTK_PIN_NO(67) | 7)

#define MT8173_PIN_68_MSDC0_RST___FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
#define MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB (MTK_PIN_NO(68) | 1)
#define MT8173_PIN_68_MSDC0_RST___FUNC_I2S2_MCK (MTK_PIN_NO(68) | 2)
#define MT8173_PIN_68_MSDC0_RST___FUNC_DBG_MON_B_18_ (MTK_PIN_NO(68) | 7)

#define MT8173_PIN_69_SPI_CK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
#define MT8173_PIN_69_SPI_CK__FUNC_SPI_CK_0_ (MTK_PIN_NO(69) | 1)
#define MT8173_PIN_69_SPI_CK__FUNC_I2S3_DO_1 (MTK_PIN_NO(69) | 2)
#define MT8173_PIN_69_SPI_CK__FUNC_PWM0 (MTK_PIN_NO(69) | 3)
#define MT8173_PIN_69_SPI_CK__FUNC_PWM5 (MTK_PIN_NO(69) | 4)
#define MT8173_PIN_69_SPI_CK__FUNC_I2S2_MCK (MTK_PIN_NO(69) | 5)
#define MT8173_PIN_69_SPI_CK__FUNC_DBG_MON_B_19_ (MTK_PIN_NO(69) | 7)

#define MT8173_PIN_70_SPI_MI__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MI_0_ (MTK_PIN_NO(70) | 1)
#define MT8173_PIN_70_SPI_MI__FUNC_I2S3_DO_2 (MTK_PIN_NO(70) | 2)
#define MT8173_PIN_70_SPI_MI__FUNC_PWM1 (MTK_PIN_NO(70) | 3)
#define MT8173_PIN_70_SPI_MI__FUNC_SPI_MO_0_ (MTK_PIN_NO(70) | 4)
#define MT8173_PIN_70_SPI_MI__FUNC_I2S2_DI_1 (MTK_PIN_NO(70) | 5)
#define MT8173_PIN_70_SPI_MI__FUNC_DSI1_TE (MTK_PIN_NO(70) | 6)
#define MT8173_PIN_70_SPI_MI__FUNC_DBG_MON_B_20_ (MTK_PIN_NO(70) | 7)

#define MT8173_PIN_71_SPI_MO__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MO_0_ (MTK_PIN_NO(71) | 1)
#define MT8173_PIN_71_SPI_MO__FUNC_I2S3_DO_3 (MTK_PIN_NO(71) | 2)
#define MT8173_PIN_71_SPI_MO__FUNC_PWM2 (MTK_PIN_NO(71) | 3)
#define MT8173_PIN_71_SPI_MO__FUNC_SPI_MI_0_ (MTK_PIN_NO(71) | 4)
#define MT8173_PIN_71_SPI_MO__FUNC_I2S2_DI_2 (MTK_PIN_NO(71) | 5)
#define MT8173_PIN_71_SPI_MO__FUNC_DBG_MON_B_21_ (MTK_PIN_NO(71) | 7)

#define MT8173_PIN_72_SPI_CS__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
#define MT8173_PIN_72_SPI_CS__FUNC_SPI_CS_0_ (MTK_PIN_NO(72) | 1)
#define MT8173_PIN_72_SPI_CS__FUNC_I2S3_DO_4 (MTK_PIN_NO(72) | 2)
#define MT8173_PIN_72_SPI_CS__FUNC_PWM3 (MTK_PIN_NO(72) | 3)
#define MT8173_PIN_72_SPI_CS__FUNC_PWM6 (MTK_PIN_NO(72) | 4)
#define MT8173_PIN_72_SPI_CS__FUNC_DISP_PWM1 (MTK_PIN_NO(72) | 5)
#define MT8173_PIN_72_SPI_CS__FUNC_DBG_MON_B_22_ (MTK_PIN_NO(72) | 7)

#define MT8173_PIN_73_MSDC1_DAT0__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
#define MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(73) | 1)
#define MT8173_PIN_73_MSDC1_DAT0__FUNC_DBG_MON_B_24_ (MTK_PIN_NO(73) | 7)

#define MT8173_PIN_74_MSDC1_DAT1__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
#define MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(74) | 1)
#define MT8173_PIN_74_MSDC1_DAT1__FUNC_DBG_MON_B_25_ (MTK_PIN_NO(74) | 7)

#define MT8173_PIN_75_MSDC1_DAT2__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
#define MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(75) | 1)
#define MT8173_PIN_75_MSDC1_DAT2__FUNC_DBG_MON_B_26_ (MTK_PIN_NO(75) | 7)

#define MT8173_PIN_76_MSDC1_DAT3__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
#define MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(76) | 1)
#define MT8173_PIN_76_MSDC1_DAT3__FUNC_DBG_MON_B_27_ (MTK_PIN_NO(76) | 7)

#define MT8173_PIN_77_MSDC1_CLK__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
#define MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(77) | 1)
#define MT8173_PIN_77_MSDC1_CLK__FUNC_DBG_MON_B_28_ (MTK_PIN_NO(77) | 7)

#define MT8173_PIN_78_MSDC1_CMD__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
#define MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(78) | 1)
#define MT8173_PIN_78_MSDC1_CMD__FUNC_DBG_MON_B_23_ (MTK_PIN_NO(78) | 7)

#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMI (MTK_PIN_NO(79) | 1)
#define MT8173_PIN_79_PWRAP_SPI0_MI__FUNC_PWRAP_SPIMO (MTK_PIN_NO(79) | 2)

#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMO (MTK_PIN_NO(80) | 1)
#define MT8173_PIN_80_PWRAP_SPI0_MO__FUNC_PWRAP_SPIMI (MTK_PIN_NO(80) | 2)

#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
#define MT8173_PIN_81_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK (MTK_PIN_NO(81) | 1)

#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
#define MT8173_PIN_82_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS (MTK_PIN_NO(82) | 1)

#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
#define MT8173_PIN_83_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(83) | 1)

#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MISO (MTK_PIN_NO(84) | 1)
#define MT8173_PIN_84_AUD_DAT_MISO__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(84) | 2)

#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(85) | 1)
#define MT8173_PIN_85_AUD_DAT_MOSI__FUNC_AUD_DAT_MISO (MTK_PIN_NO(85) | 2)

#define MT8173_PIN_86_RTC32K_CK__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
#define MT8173_PIN_86_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(86) | 1)

#define MT8173_PIN_87_DISP_PWM0__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0 (MTK_PIN_NO(87) | 1)
#define MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM1 (MTK_PIN_NO(87) | 2)
#define MT8173_PIN_87_DISP_PWM0__FUNC_DBG_MON_B_31_ (MTK_PIN_NO(87) | 7)

#define MT8173_PIN_88_SRCLKENAI__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
#define MT8173_PIN_88_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(88) | 1)

#define MT8173_PIN_89_SRCLKENAI2__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
#define MT8173_PIN_89_SRCLKENAI2__FUNC_SRCLKENAI2 (MTK_PIN_NO(89) | 1)

#define MT8173_PIN_90_SRCLKENA0__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
#define MT8173_PIN_90_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(90) | 1)

#define MT8173_PIN_91_SRCLKENA1__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
#define MT8173_PIN_91_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(91) | 1)

#define MT8173_PIN_92_PCM_CLK__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
#define MT8173_PIN_92_PCM_CLK__FUNC_PCM1_CLK (MTK_PIN_NO(92) | 1)
#define MT8173_PIN_92_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(92) | 2)
#define MT8173_PIN_92_PCM_CLK__FUNC_DBG_MON_A_24_ (MTK_PIN_NO(92) | 7)

#define MT8173_PIN_93_PCM_SYNC__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
#define MT8173_PIN_93_PCM_SYNC__FUNC_PCM1_SYNC (MTK_PIN_NO(93) | 1)
#define MT8173_PIN_93_PCM_SYNC__FUNC_I2S0_WS (MTK_PIN_NO(93) | 2)
#define MT8173_PIN_93_PCM_SYNC__FUNC_DBG_MON_A_25_ (MTK_PIN_NO(93) | 7)

#define MT8173_PIN_94_PCM_RX__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
#define MT8173_PIN_94_PCM_RX__FUNC_PCM1_DI (MTK_PIN_NO(94) | 1)
#define MT8173_PIN_94_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(94) | 2)
#define MT8173_PIN_94_PCM_RX__FUNC_DBG_MON_A_26_ (MTK_PIN_NO(94) | 7)

#define MT8173_PIN_95_PCM_TX__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
#define MT8173_PIN_95_PCM_TX__FUNC_PCM1_DO (MTK_PIN_NO(95) | 1)
#define MT8173_PIN_95_PCM_TX__FUNC_I2S0_DO (MTK_PIN_NO(95) | 2)
#define MT8173_PIN_95_PCM_TX__FUNC_DBG_MON_A_27_ (MTK_PIN_NO(95) | 7)

#define MT8173_PIN_96_URXD1__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
#define MT8173_PIN_96_URXD1__FUNC_URXD1 (MTK_PIN_NO(96) | 1)
#define MT8173_PIN_96_URXD1__FUNC_UTXD1 (MTK_PIN_NO(96) | 2)
#define MT8173_PIN_96_URXD1__FUNC_DBG_MON_A_28_ (MTK_PIN_NO(96) | 7)

#define MT8173_PIN_97_UTXD1__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
#define MT8173_PIN_97_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(97) | 1)
#define MT8173_PIN_97_UTXD1__FUNC_URXD1 (MTK_PIN_NO(97) | 2)
#define MT8173_PIN_97_UTXD1__FUNC_DBG_MON_A_29_ (MTK_PIN_NO(97) | 7)

#define MT8173_PIN_98_URTS1__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
#define MT8173_PIN_98_URTS1__FUNC_URTS1 (MTK_PIN_NO(98) | 1)
#define MT8173_PIN_98_URTS1__FUNC_UCTS1 (MTK_PIN_NO(98) | 2)
#define MT8173_PIN_98_URTS1__FUNC_DBG_MON_A_30_ (MTK_PIN_NO(98) | 7)

#define MT8173_PIN_99_UCTS1__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
#define MT8173_PIN_99_UCTS1__FUNC_UCTS1 (MTK_PIN_NO(99) | 1)
#define MT8173_PIN_99_UCTS1__FUNC_URTS1 (MTK_PIN_NO(99) | 2)
#define MT8173_PIN_99_UCTS1__FUNC_DBG_MON_A_31_ (MTK_PIN_NO(99) | 7)

#define MT8173_PIN_100_MSDC2_DAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
#define MT8173_PIN_100_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(100) | 1)
#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(100) | 3)
#define MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5 (MTK_PIN_NO(100) | 4)
#define MT8173_PIN_100_MSDC2_DAT0__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(100) | 5)
#define MT8173_PIN_100_MSDC2_DAT0__FUNC_DBG_MON_B_0_ (MTK_PIN_NO(100) | 7)

#define MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
#define MT8173_PIN_101_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(101) | 1)
#define MT8173_PIN_101_MSDC2_DAT1__FUNC_AUD_SPDIF (MTK_PIN_NO(101) | 3)
#define MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5 (MTK_PIN_NO(101) | 4)
#define MT8173_PIN_101_MSDC2_DAT1__FUNC_DBG_MON_B_1_ (MTK_PIN_NO(101) | 7)

#define MT8173_PIN_102_MSDC2_DAT2__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
#define MT8173_PIN_102_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(102) | 1)
#define MT8173_PIN_102_MSDC2_DAT2__FUNC_UTXD0 (MTK_PIN_NO(102) | 3)
#define MT8173_PIN_102_MSDC2_DAT2__FUNC_PWM0 (MTK_PIN_NO(102) | 5)
#define MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_ (MTK_PIN_NO(102) | 6)
#define MT8173_PIN_102_MSDC2_DAT2__FUNC_DBG_MON_B_2_ (MTK_PIN_NO(102) | 7)

#define MT8173_PIN_103_MSDC2_DAT3__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
#define MT8173_PIN_103_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(103) | 1)
#define MT8173_PIN_103_MSDC2_DAT3__FUNC_URXD0 (MTK_PIN_NO(103) | 3)
#define MT8173_PIN_103_MSDC2_DAT3__FUNC_PWM1 (MTK_PIN_NO(103) | 5)
#define MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_ (MTK_PIN_NO(103) | 6)
#define MT8173_PIN_103_MSDC2_DAT3__FUNC_DBG_MON_B_3_ (MTK_PIN_NO(103) | 7)

#define MT8173_PIN_104_MSDC2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(104) | 1)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_UTXD3 (MTK_PIN_NO(104) | 3)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 4)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_PWM2 (MTK_PIN_NO(104) | 5)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_ (MTK_PIN_NO(104) | 6)
#define MT8173_PIN_104_MSDC2_CLK__FUNC_DBG_MON_B_4_ (MTK_PIN_NO(104) | 7)

#define MT8173_PIN_105_MSDC2_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(105) | 1)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_URXD3 (MTK_PIN_NO(105) | 3)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_SCL3 (MTK_PIN_NO(105) | 4)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_PWM3 (MTK_PIN_NO(105) | 5)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_ (MTK_PIN_NO(105) | 6)
#define MT8173_PIN_105_MSDC2_CMD__FUNC_DBG_MON_B_5_ (MTK_PIN_NO(105) | 7)

#define MT8173_PIN_106_SDA3__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
#define MT8173_PIN_106_SDA3__FUNC_SDA3 (MTK_PIN_NO(106) | 1)

#define MT8173_PIN_107_SCL3__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
#define MT8173_PIN_107_SCL3__FUNC_SCL3 (MTK_PIN_NO(107) | 1)

#define MT8173_PIN_108_JTMS__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
#define MT8173_PIN_108_JTMS__FUNC_JTMS (MTK_PIN_NO(108) | 1)
#define MT8173_PIN_108_JTMS__FUNC_MFG_JTAG_TMS (MTK_PIN_NO(108) | 2)
#define MT8173_PIN_108_JTMS__FUNC_AP_MD32_JTAG_TMS (MTK_PIN_NO(108) | 5)
#define MT8173_PIN_108_JTMS__FUNC_DFD_TMS (MTK_PIN_NO(108) | 6)

#define MT8173_PIN_109_JTCK__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
#define MT8173_PIN_109_JTCK__FUNC_JTCK (MTK_PIN_NO(109) | 1)
#define MT8173_PIN_109_JTCK__FUNC_MFG_JTAG_TCK (MTK_PIN_NO(109) | 2)
#define MT8173_PIN_109_JTCK__FUNC_AP_MD32_JTAG_TCK (MTK_PIN_NO(109) | 5)
#define MT8173_PIN_109_JTCK__FUNC_DFD_TCK (MTK_PIN_NO(109) | 6)

#define MT8173_PIN_110_JTDI__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
#define MT8173_PIN_110_JTDI__FUNC_JTDI (MTK_PIN_NO(110) | 1)
#define MT8173_PIN_110_JTDI__FUNC_MFG_JTAG_TDI (MTK_PIN_NO(110) | 2)
#define MT8173_PIN_110_JTDI__FUNC_AP_MD32_JTAG_TDI (MTK_PIN_NO(110) | 5)
#define MT8173_PIN_110_JTDI__FUNC_DFD_TDI (MTK_PIN_NO(110) | 6)

#define MT8173_PIN_111_JTDO__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
#define MT8173_PIN_111_JTDO__FUNC_JTDO (MTK_PIN_NO(111) | 1)
#define MT8173_PIN_111_JTDO__FUNC_MFG_JTAG_TDO (MTK_PIN_NO(111) | 2)
#define MT8173_PIN_111_JTDO__FUNC_AP_MD32_JTAG_TDO (MTK_PIN_NO(111) | 5)
#define MT8173_PIN_111_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(111) | 6)

#define MT8173_PIN_112_JTRST_B__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
#define MT8173_PIN_112_JTRST_B__FUNC_JTRST_B (MTK_PIN_NO(112) | 1)
#define MT8173_PIN_112_JTRST_B__FUNC_MFG_JTAG_TRSTN (MTK_PIN_NO(112) | 2)
#define MT8173_PIN_112_JTRST_B__FUNC_AP_MD32_JTAG_TRST (MTK_PIN_NO(112) | 5)
#define MT8173_PIN_112_JTRST_B__FUNC_DFD_NTRST (MTK_PIN_NO(112) | 6)

#define MT8173_PIN_113_URXD0__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
#define MT8173_PIN_113_URXD0__FUNC_URXD0 (MTK_PIN_NO(113) | 1)
#define MT8173_PIN_113_URXD0__FUNC_UTXD0 (MTK_PIN_NO(113) | 2)
#define MT8173_PIN_113_URXD0__FUNC_I2S2_WS (MTK_PIN_NO(113) | 6)
#define MT8173_PIN_113_URXD0__FUNC_DBG_MON_A_0_ (MTK_PIN_NO(113) | 7)

#define MT8173_PIN_114_UTXD0__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
#define MT8173_PIN_114_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(114) | 1)
#define MT8173_PIN_114_UTXD0__FUNC_URXD0 (MTK_PIN_NO(114) | 2)
#define MT8173_PIN_114_UTXD0__FUNC_I2S2_BCK (MTK_PIN_NO(114) | 6)
#define MT8173_PIN_114_UTXD0__FUNC_DBG_MON_A_1_ (MTK_PIN_NO(114) | 7)

#define MT8173_PIN_115_URTS0__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
#define MT8173_PIN_115_URTS0__FUNC_URTS0 (MTK_PIN_NO(115) | 1)
#define MT8173_PIN_115_URTS0__FUNC_UCTS0 (MTK_PIN_NO(115) | 2)
#define MT8173_PIN_115_URTS0__FUNC_I2S2_MCK (MTK_PIN_NO(115) | 6)
#define MT8173_PIN_115_URTS0__FUNC_DBG_MON_A_2_ (MTK_PIN_NO(115) | 7)

#define MT8173_PIN_116_UCTS0__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
#define MT8173_PIN_116_UCTS0__FUNC_UCTS0 (MTK_PIN_NO(116) | 1)
#define MT8173_PIN_116_UCTS0__FUNC_URTS0 (MTK_PIN_NO(116) | 2)
#define MT8173_PIN_116_UCTS0__FUNC_I2S2_DI_1 (MTK_PIN_NO(116) | 6)
#define MT8173_PIN_116_UCTS0__FUNC_DBG_MON_A_3_ (MTK_PIN_NO(116) | 7)

#define MT8173_PIN_117_URXD3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
#define MT8173_PIN_117_URXD3__FUNC_URXD3 (MTK_PIN_NO(117) | 1)
#define MT8173_PIN_117_URXD3__FUNC_UTXD3 (MTK_PIN_NO(117) | 2)
#define MT8173_PIN_117_URXD3__FUNC_DBG_MON_A_9_ (MTK_PIN_NO(117) | 7)

#define MT8173_PIN_118_UTXD3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
#define MT8173_PIN_118_UTXD3__FUNC_UTXD3 (MTK_PIN_NO(118) | 1)
#define MT8173_PIN_118_UTXD3__FUNC_URXD3 (MTK_PIN_NO(118) | 2)
#define MT8173_PIN_118_UTXD3__FUNC_DBG_MON_A_10_ (MTK_PIN_NO(118) | 7)

#define MT8173_PIN_119_KPROW0__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
#define MT8173_PIN_119_KPROW0__FUNC_KROW0 (MTK_PIN_NO(119) | 1)
#define MT8173_PIN_119_KPROW0__FUNC_DBG_MON_A_11_ (MTK_PIN_NO(119) | 7)

#define MT8173_PIN_120_KPROW1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
#define MT8173_PIN_120_KPROW1__FUNC_KROW1 (MTK_PIN_NO(120) | 1)
#define MT8173_PIN_120_KPROW1__FUNC_PWM6 (MTK_PIN_NO(120) | 3)
#define MT8173_PIN_120_KPROW1__FUNC_DBG_MON_A_12_ (MTK_PIN_NO(120) | 7)

#define MT8173_PIN_121_KPROW2__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
#define MT8173_PIN_121_KPROW2__FUNC_KROW2 (MTK_PIN_NO(121) | 1)
#define MT8173_PIN_121_KPROW2__FUNC_IRDA_PDN (MTK_PIN_NO(121) | 2)
#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(121) | 3)
#define MT8173_PIN_121_KPROW2__FUNC_PWM4 (MTK_PIN_NO(121) | 4)
#define MT8173_PIN_121_KPROW2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(121) | 5)
#define MT8173_PIN_121_KPROW2__FUNC_DBG_MON_A_13_ (MTK_PIN_NO(121) | 7)

#define MT8173_PIN_122_KPCOL0__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
#define MT8173_PIN_122_KPCOL0__FUNC_KCOL0 (MTK_PIN_NO(122) | 1)
#define MT8173_PIN_122_KPCOL0__FUNC_DBG_MON_A_14_ (MTK_PIN_NO(122) | 7)

#define MT8173_PIN_123_KPCOL1__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
#define MT8173_PIN_123_KPCOL1__FUNC_KCOL1 (MTK_PIN_NO(123) | 1)
#define MT8173_PIN_123_KPCOL1__FUNC_IRDA_RXD (MTK_PIN_NO(123) | 2)
#define MT8173_PIN_123_KPCOL1__FUNC_PWM5 (MTK_PIN_NO(123) | 3)
#define MT8173_PIN_123_KPCOL1__FUNC_DBG_MON_A_15_ (MTK_PIN_NO(123) | 7)

#define MT8173_PIN_124_KPCOL2__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define MT8173_PIN_124_KPCOL2__FUNC_KCOL2 (MTK_PIN_NO(124) | 1)
#define MT8173_PIN_124_KPCOL2__FUNC_IRDA_TXD (MTK_PIN_NO(124) | 2)
#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(124) | 3)
#define MT8173_PIN_124_KPCOL2__FUNC_PWM3 (MTK_PIN_NO(124) | 4)
#define MT8173_PIN_124_KPCOL2__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(124) | 5)
#define MT8173_PIN_124_KPCOL2__FUNC_DBG_MON_A_16_ (MTK_PIN_NO(124) | 7)

#define MT8173_PIN_125_SDA1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
#define MT8173_PIN_125_SDA1__FUNC_SDA1 (MTK_PIN_NO(125) | 1)

#define MT8173_PIN_126_SCL1__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
#define MT8173_PIN_126_SCL1__FUNC_SCL1 (MTK_PIN_NO(126) | 1)

#define MT8173_PIN_127_LCM_RST__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
#define MT8173_PIN_127_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(127) | 1)

#define MT8173_PIN_128_I2S0_LRCK__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S0_WS (MTK_PIN_NO(128) | 1)
#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS (MTK_PIN_NO(128) | 2)
#define MT8173_PIN_128_I2S0_LRCK__FUNC_I2S2_WS (MTK_PIN_NO(128) | 3)
#define MT8173_PIN_128_I2S0_LRCK__FUNC_SPI_CK_2_ (MTK_PIN_NO(128) | 5)
#define MT8173_PIN_128_I2S0_LRCK__FUNC_DBG_MON_A_4_ (MTK_PIN_NO(128) | 7)

#define MT8173_PIN_129_I2S0_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(129) | 1)
#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(129) | 2)
#define MT8173_PIN_129_I2S0_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(129) | 3)
#define MT8173_PIN_129_I2S0_BCK__FUNC_SPI_MI_2_ (MTK_PIN_NO(129) | 5)
#define MT8173_PIN_129_I2S0_BCK__FUNC_DBG_MON_A_5_ (MTK_PIN_NO(129) | 7)

#define MT8173_PIN_130_I2S0_MCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S0_MCK (MTK_PIN_NO(130) | 1)
#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK (MTK_PIN_NO(130) | 2)
#define MT8173_PIN_130_I2S0_MCK__FUNC_I2S2_MCK (MTK_PIN_NO(130) | 3)
#define MT8173_PIN_130_I2S0_MCK__FUNC_SPI_MO_2_ (MTK_PIN_NO(130) | 5)
#define MT8173_PIN_130_I2S0_MCK__FUNC_DBG_MON_A_6_ (MTK_PIN_NO(130) | 7)

#define MT8173_PIN_131_I2S0_DATA0__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S0_DO (MTK_PIN_NO(131) | 1)
#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1 (MTK_PIN_NO(131) | 2)
#define MT8173_PIN_131_I2S0_DATA0__FUNC_I2S2_DI_1 (MTK_PIN_NO(131) | 3)
#define MT8173_PIN_131_I2S0_DATA0__FUNC_SPI_CS_2_ (MTK_PIN_NO(131) | 5)
#define MT8173_PIN_131_I2S0_DATA0__FUNC_DBG_MON_A_7_ (MTK_PIN_NO(131) | 7)

#define MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S0_DI (MTK_PIN_NO(132) | 1)
#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S1_DO_2 (MTK_PIN_NO(132) | 2)
#define MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2 (MTK_PIN_NO(132) | 3)
#define MT8173_PIN_132_I2S0_DATA1__FUNC_DBG_MON_A_8_ (MTK_PIN_NO(132) | 7)

#define MT8173_PIN_133_SDA4__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
#define MT8173_PIN_133_SDA4__FUNC_SDA4 (MTK_PIN_NO(133) | 1)

#define MT8173_PIN_134_SCL4__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
#define MT8173_PIN_134_SCL4__FUNC_SCL4 (MTK_PIN_NO(134) | 1)

#endif /* __DTS_MT8173_PINFUNC_H */