code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra186 xHCI controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
  exposed by the Tegra XUSB pad controller.

properties:
  compatible:
    const: nvidia,tegra186-xusb

  reg:
    items:
      - description: base and length of the xHCI host registers
      - description: base and length of the XUSB FPCI registers

  reg-names:
    items:
      - const: hcd
      - const: fpci

  interrupts:
    items:
      - description: xHCI host interrupt
      - description: mailbox interrupt

  clocks:
    items:
      - description: XUSB host clock
      - description: XUSB Falcon source clock
      - description: XUSB SuperSpeed clock
      - description: XUSB SuperSpeed source clock
      - description: XUSB HighSpeed clock source
      - description: XUSB FullSpeed clock source
      - description: USB PLL
      - description: reference clock
      - description: I/O PLL

  clock-names:
    items:
      - const: xusb_host
      - const: xusb_falcon_src
      - const: xusb_ss
      - const: xusb_ss_src
      - const: xusb_hs_src
      - const: xusb_fs_src
      - const: pll_u_480m
      - const: clk_m
      - const: pll_e

  interconnects:
    items:
      - description: read client
      - description: write client

  interconnect-names:
    items:
      - const: dma-mem # read
      - const: write

  iommus:
    maxItems: 1

  nvidia,xusb-padctl:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle to the XUSB pad controller that is used to configure
      the USB pads used by the XHCI controller

  phys:
    minItems: 1
    maxItems: 7

  phy-names:
    minItems: 1
    maxItems: 7
    items:
      enum:
        - usb2-0
        - usb2-1
        - usb2-2
        - hsic-0
        - usb3-0
        - usb3-1
        - usb3-2

  power-domains:
    items:
      - description: XUSBC power domain (for Host and USB 2.0)
      - description: XUSBA power domain (for SuperSpeed)

  power-domain-names:
    items:
      - const: xusb_host
      - const: xusb_ss

  dvddio-pex-supply:
    description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.

  hvddio-pex-supply:
    description: High-voltage PCIe/USB3 power supply. Must supply 1.8 V.

  avdd-usb-supply:
    description: USB controller power supply. Must supply 3.3 V.

  avdd-pll-utmip-supply:
    description: UTMI PLL power supply. Must supply 1.8 V.

  avdd-pll-uerefe-supply:
    description: PLLE reference PLL power supply. Must supply 1.05 V.

  dvdd-usb-ss-pll-supply:
    description: PCIe/USB3 PLL power supply. Must supply 1.05 V.

  hvdd-usb-ss-pll-e-supply:
    description: High-voltage PLLE power supply. Must supply 1.8 V.

allOf:
  - $ref: usb-xhci.yaml

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra186-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/tegra186-mc.h>
    #include <dt-bindings/power/tegra186-powergate.h>
    #include <dt-bindings/reset/tegra186-reset.h>

    usb@3530000 {
        compatible = "nvidia,tegra186-xusb";
        reg = <0x03530000 0x8000>,
              <0x03538000 0x1000>;
        reg-names = "hcd", "fpci";
        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
                 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
                 <&bpmp TEGRA186_CLK_XUSB_SS>,
                 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
                 <&bpmp TEGRA186_CLK_CLK_M>,
                 <&bpmp TEGRA186_CLK_XUSB_FS>,
                 <&bpmp TEGRA186_CLK_PLLU>,
                 <&bpmp TEGRA186_CLK_CLK_M>,
                 <&bpmp TEGRA186_CLK_PLLE>;
        clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
                      "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
                      "pll_u_480m", "clk_m", "pll_e";
        power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
                        <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
        power-domain-names = "xusb_host", "xusb_ss";
        interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
                        <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
        interconnect-names = "dma-mem", "write";
        iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
        nvidia,xusb-padctl = <&padctl>;

        #address-cells = <1>;
        #size-cells = <0>;

        phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
               <&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
               <&{/padctl@3520000/pads/usb3/lanes/usb3-0}>;
        phy-names = "usb2-0", "usb2-1", "usb3-0";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra194 xHCI controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
  exposed by the Tegra XUSB pad controller.

properties:
  compatible:
    const: nvidia,tegra194-xusb

  reg:
    items:
      - description: base and length of the xHCI host registers
      - description: base and length of the XUSB FPCI registers

  reg-names:
    items:
      - const: hcd
      - const: fpci

  interrupts:
    items:
      - description: xHCI host interrupt
      - description: mailbox interrupt

  clocks:
    items:
      - description: XUSB host clock
      - description: XUSB Falcon source clock
      - description: XUSB SuperSpeed clock
      - description: XUSB SuperSpeed source clock
      - description: XUSB HighSpeed clock source
      - description: XUSB FullSpeed clock source
      - description: USB PLL
      - description: reference clock
      - description: I/O PLL

  clock-names:
    items:
      - const: xusb_host
      - const: xusb_falcon_src
      - const: xusb_ss
      - const: xusb_ss_src
      - const: xusb_hs_src
      - const: xusb_fs_src
      - const: pll_u_480m
      - const: clk_m
      - const: pll_e

  interconnects:
    items:
      - description: read client
      - description: write client

  interconnect-names:
    items:
      - const: dma-mem # read
      - const: write

  iommus:
    maxItems: 1

  nvidia,xusb-padctl:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle to the XUSB pad controller that is used to configure
      the USB pads used by the XHCI controller

  phys:
    minItems: 1
    maxItems: 8

  phy-names:
    minItems: 1
    maxItems: 8
    items:
      enum:
        - usb2-0
        - usb2-1
        - usb2-2
        - usb2-3
        - usb3-0
        - usb3-1
        - usb3-2
        - usb3-3

  power-domains:
    items:
      - description: XUSBC power domain (for Host and USB 2.0)
      - description: XUSBA power domain (for SuperSpeed)

  power-domain-names:
    items:
      - const: xusb_host
      - const: xusb_ss

  dvddio-pex-supply:
    description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.

  hvddio-pex-supply:
    description: High-voltage PCIe/USB3 power supply. Must supply 1.8 V.

  avdd-usb-supply:
    description: USB controller power supply. Must supply 3.3 V.

  avdd-pll-utmip-supply:
    description: UTMI PLL power supply. Must supply 1.8 V.

  avdd-pll-uerefe-supply:
    description: PLLE reference PLL power supply. Must supply 1.05 V.

  dvdd-usb-ss-pll-supply:
    description: PCIe/USB3 PLL power supply. Must supply 1.05 V.

  hvdd-usb-ss-pll-e-supply:
    description: High-voltage PLLE power supply. Must supply 1.8 V.

allOf:
  - $ref: usb-xhci.yaml

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra194-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/tegra194-mc.h>
    #include <dt-bindings/power/tegra194-powergate.h>
    #include <dt-bindings/reset/tegra194-reset.h>

    usb@3610000 {
        compatible = "nvidia,tegra194-xusb";
        reg = <0x03610000 0x40000>,
              <0x03600000 0x10000>;
        reg-names = "hcd", "fpci";

        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
                 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
                 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
                 <&bpmp TEGRA194_CLK_XUSB_SS>,
                 <&bpmp TEGRA194_CLK_CLK_M>,
                 <&bpmp TEGRA194_CLK_XUSB_FS>,
                 <&bpmp TEGRA194_CLK_UTMIPLL>,
                 <&bpmp TEGRA194_CLK_CLK_M>,
                 <&bpmp TEGRA194_CLK_PLLE>;
        clock-names = "xusb_host", "xusb_falcon_src",
                      "xusb_ss", "xusb_ss_src", "xusb_hs_src",
                      "xusb_fs_src", "pll_u_480m", "clk_m",
                      "pll_e";
        interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
                        <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
        interconnect-names = "dma-mem", "write";
        iommus = <&smmu TEGRA194_SID_XUSB_HOST>;

        power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
                        <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
        power-domain-names = "xusb_host", "xusb_ss";

        nvidia,xusb-padctl = <&xusb_padctl>;

        phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
               <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
               <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
               <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
               <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>,
               <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-3}>;
        phy-names = "usb2-0", "usb2-1", "usb2-3", "usb3-0", "usb3-2", "usb3-3";
    };

repo_name: angery/linux


code:
Tegra SOC USB controllers

The device node for a USB controller that is part of a Tegra
SOC is as described in the document "Open Firmware Recommended
Practice : Universal Serial Bus" with the following modifications
and additions :

Required properties :
 - compatible : For Tegra20, must contain "nvidia,tegra20-ehci".
   For Tegra30, must contain "nvidia,tegra30-ehci".  Otherwise, must contain
   "nvidia,<chip>-ehci" plus at least one of the above, where <chip> is
   tegra114, tegra124, tegra132, or tegra210.
 - nvidia,phy : phandle of the PHY that the controller is connected to.
 - clocks : Must contain one entry, for the module clock.
   See ../clocks/clock-bindings.txt for details.
 - resets : Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
 - reset-names : Must include the following entries:
   - usb

Optional properties:
 - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
   USB ports, which need reset twice due to hardware issues.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra210 xHCI controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
  exposed by the Tegra XUSB pad controller.

properties:
  compatible:
    const: nvidia,tegra210-xusb

  reg:
    items:
      - description: base and length of the xHCI host registers
      - description: base and length of the XUSB FPCI registers
      - description: base and length of the XUSB IPFS registers

  reg-names:
    items:
      - const: hcd
      - const: fpci
      - const: ipfs

  interrupts:
    items:
      - description: xHCI host interrupt
      - description: mailbox interrupt

  clocks:
    items:
      - description: XUSB host clock
      - description: XUSB host source clock
      - description: XUSB Falcon source clock
      - description: XUSB SuperSpeed clock
      - description: XUSB SuperSpeed clock divider
      - description: XUSB SuperSpeed source clock
      - description: XUSB HighSpeed clock source
      - description: XUSB FullSpeed clock source
      - description: USB PLL
      - description: reference clock
      - description: I/O PLL

  clock-names:
    items:
      - const: xusb_host
      - const: xusb_host_src
      - const: xusb_falcon_src
      - const: xusb_ss
      - const: xusb_ss_div2
      - const: xusb_ss_src
      - const: xusb_hs_src
      - const: xusb_fs_src
      - const: pll_u_480m
      - const: clk_m
      - const: pll_e

  resets:
    items:
      - description: reset for the XUSB host controller
      - description: reset for the SuperSpeed logic
      - description: shared reset for xusb_{ss,hs,fs,falcon,host}_src.

  reset-names:
    items:
      - const: xusb_host
      - const: xusb_ss
      - const: xusb_src

  nvidia,xusb-padctl:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle to the XUSB pad controller that is used to configure
      the USB pads used by the XHCI controller

  phys:
    minItems: 1
    maxItems: 9

  phy-names:
    minItems: 1
    maxItems: 9
    items:
      enum:
        - usb2-0
        - usb2-1
        - usb2-2
        - usb2-3
        - hsic-0
        - usb3-0
        - usb3-1
        - usb3-2
        - usb3-3

  power-domains:
    items:
      - description: XUSBC power domain (for Host and USB 2.0)
      - description: XUSBA power domain (for SuperSpeed)

  power-domain-names:
    items:
      - const: xusb_host
      - const: xusb_ss

  dvddio-pex-supply:
    description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.

  hvddio-pex-supply:
    description: High-voltage PCIe/USB3 power supply. Must supply 1.8 V.

  avdd-usb-supply:
    description: USB controller power supply. Must supply 3.3 V.

  avdd-pll-utmip-supply:
    description: UTMI PLL power supply. Must supply 1.8 V.

  avdd-pll-uerefe-supply:
    description: PLLE reference PLL power supply. Must supply 1.05 V.

  dvdd-usb-ss-pll-supply:
    description: PCIe/USB3 PLL power supply. Must supply 1.05 V.

  hvdd-usb-ss-pll-e-supply:
    description: High-voltage PLLE power supply. Must supply 1.8 V.

allOf:
  - $ref: usb-xhci.yaml

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    usb@70090000 {
        compatible = "nvidia,tegra210-xusb";
        reg = <0x70090000 0x8000>,
              <0x70098000 0x1000>,
              <0x70099000 0x1000>;
        reg-names = "hcd", "fpci", "ipfs";

        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
                 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
                 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
                 <&tegra_car TEGRA210_CLK_XUSB_SS>,
                 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
                 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
                 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
                 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
                 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
                 <&tegra_car TEGRA210_CLK_CLK_M>,
                 <&tegra_car TEGRA210_CLK_PLL_E>;
        clock-names = "xusb_host", "xusb_host_src",
                      "xusb_falcon_src", "xusb_ss",
                      "xusb_ss_div2", "xusb_ss_src",
                      "xusb_hs_src", "xusb_fs_src",
                      "pll_u_480m", "clk_m", "pll_e";
        resets = <&tegra_car 89>, <&tegra_car 156>,
                 <&tegra_car 143>;
        reset-names = "xusb_host", "xusb_ss", "xusb_src";
        power-domains = <&pd_xusbhost>, <&pd_xusbss>;
        power-domain-names = "xusb_host", "xusb_ss";

        nvidia,xusb-padctl = <&padctl>;

        phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
               <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
               <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
               <&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>,
               <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>,
               <&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
        phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0",
                    "usb3-1";
        dvddio-pex-supply = <&vdd_pex_1v05>;
        hvddio-pex-supply = <&vdd_1v8>;
        avdd-usb-supply = <&vdd_3v3_sys>;
        avdd-pll-utmip-supply = <&vdd_1v8>;
        avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
        dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
        hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;

        #address-cells = <1>;
        #size-cells = <0>;

        ethernet@1 {
                compatible = "usb955,9ff";
                reg = <1>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/nxp,isp1760.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP ISP1760 family controller bindings

maintainers:
  - Sebastian Siewior <bigeasy@linutronix.de>
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description: |
  NXP ISP1760 family, which includes ISP1760/1761/1763 devicetree controller
  bindings

properties:
  compatible:
    enum:
      - nxp,usb-isp1760
      - nxp,usb-isp1761
      - nxp,usb-isp1763
  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    items:
      - description: Host controller interrupt
      - description: Device controller interrupt in isp1761

  interrupt-names:
    minItems: 1
    items:
      - const: host
      - const: peripheral

  bus-width:
    description:
      Number of data lines.
    enum: [8, 16, 32]
    default: 32

  dr_mode:
    enum:
      - host
      - peripheral

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    usb@40200000 {
        compatible = "nxp,usb-isp1763";
        reg = <0x40200000 0x100000>;
        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
        bus-width = <16>;
        dr_mode = "host";
    };

...


code:
OCTEON/OCTEON+ USB BLOCK

1) Main node

   Required properties:

   - compatible: must be "cavium,octeon-5750-usbn"

   - reg: specifies the physical base address of the USBN block and
     the length of the memory mapped region.

   - #address-cells: specifies the number of cells needed to encode an
     address. The value must be 2.

   - #size-cells: specifies the number of cells used to represent the size
     of an address. The value must be 2.

   - ranges: specifies the translation between child address space and parent
     address space.

   - clock-frequency: speed of the USB reference clock. Allowed values are
     12000000, 24000000 or 48000000.

   - cavium,refclk-type: type of the USB reference clock. Allowed values are
     "crystal" or "external".

   - refclk-frequency: deprecated, use "clock-frequency".

   - refclk-type: deprecated, use "cavium,refclk-type".

2) Child node

   The main node must have one child node which describes the built-in
   USB controller.

   Required properties:

   - compatible: must be "cavium,octeon-5750-usbc"

   - reg: specifies the physical base address of the USBC block and
     the length of the memory mapped region.

   - interrupts: specifies the interrupt number for the USB controller.

3) Example:

	usbn: usbn@1180068000000 {
		compatible = "cavium,octeon-5750-usbn";
		reg = <0x11800 0x68000000 0x0 0x1000>;
		ranges; /* Direct mapping */
		#address-cells = <2>;
		#size-cells = <2>;
		clock-frequency = <12000000>;
		cavium,refclk-type = "crystal";

		usbc@16f0010000000 {
			compatible = "cavium,octeon-5750-usbc";
			reg = <0x16f00 0x10000000 0x0 0x80000>;
			interrupts = <0 56>;
		};
	};


code:
DA8XX USB OHCI controller

Required properties:

 - compatible: Should be "ti,da830-ohci"
 - reg:        Should contain one register range i.e. start and length
 - interrupts: Description of the interrupt line
 - phys:       Phandle for the PHY device
 - phy-names:  Should be "usb-phy"

Optional properties:
 - vbus-supply: phandle of regulator that controls vbus power / over-current

Example:

ohci: usb@225000 {
        compatible = "ti,da830-ohci";
        reg = <0x225000 0x1000>;
        interrupts = <59>;
        phys = <&usb_phy 1>;
        phy-names = "usb-phy";
        vbus-supply = <&reg_usb_ohci>;
};


code:
* OHCI controller, NXP ohci-nxp variant

Required properties:
- compatible: must be "nxp,ohci-nxp"
- reg: physical base address of the controller and length of memory mapped
  region.
- interrupts: The OHCI interrupt
- transceiver: phandle of the associated ISP1301 device - this is necessary for
               the UDC controller for connecting to the USB physical layer

Example (LPC32xx):

	isp1301: usb-transceiver@2c {
		compatible = "nxp,isp1301";
		reg = <0x2c>;
	};

	ohci@31020000 {
		compatible = "nxp,ohci-nxp";
		reg = <0x31020000 0x300>;
		interrupt-parent = <&mic>;
		interrupts = <0x3b 0>;
		transceiver = <&isp1301>;
	};


code:
OMAP HS USB OHCI controller (OMAP3 and later)

Required properties:

- compatible: should be "ti,ohci-omap3"
- reg: should contain one register range i.e. start and length
- interrupts: description of the interrupt line

Example for OMAP4:

usbhsohci: ohci@4a064800 {
	compatible = "ti,ohci-omap3";
	reg = <0x4a064800 0x400>;
	interrupts = <0 76 0x4>;
};


code:
ST USB OHCI controller

Required properties:

 - compatible		: must be "st,st-ohci-300x"
 - reg			: physical base addresses of the controller and length of memory mapped
			  region
 - interrupts		: one OHCI controller interrupt should be described here
 - clocks		: phandle list of usb clocks
 - clock-names		: should be "ic" for interconnect clock and "clk48"
See: Documentation/devicetree/bindings/clock/clock-bindings.txt

 - phys			: phandle for the PHY device
 - phy-names		: should be "usb"

 - resets		: phandle to the powerdown and reset controller for the USB IP
 - reset-names		: should be "power" and "softreset".
See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
See: Documentation/devicetree/bindings/reset/reset.txt

Example:

	ohci0: usb@fe1ffc00 {
		compatible = "st,st-ohci-300x";
		reg = <0xfe1ffc00 0x100>;
		interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
		clocks = <&clk_s_a1_ls 0>,
			 <&clockgen_b0 0>;
		clock-names = "ic", "clk48";
		phys = <&usb2_phy>;
		phy-names = "usb";

		resets = <&powerdown STIH416_USB0_POWERDOWN>,
			 <&softreset STIH416_USB0_SOFTRESET>;
		reset-names = "power", "softreset";
	};


code:
OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS

OMAP MUSB GLUE
 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
 - ti,hwmods : must be "usb_otg_hs"
 - multipoint : Should be "1" indicating the musb controller supports
   multipoint. This is a MUSB configuration-specific setting.
 - num-eps : Specifies the number of endpoints. This is also a
   MUSB configuration-specific setting. Should be set to "16"
 - ram-bits : Specifies the ram address size. Should be set to "12"
 - interface-type : This is a board specific setting to describe the type of
   interface between the controller and the phy. It should be "0" or "1"
   specifying ULPI and UTMI respectively.
 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
   represents PERIPHERAL.
 - power : Should be "50". This signifies the controller can supply up to
   100mA when operating in host mode.
 - usb-phy : the phandle for the PHY device
 - phys : the phandle for the PHY device (used by generic PHY framework)
 - phy-names : the names of the PHY corresponding to the PHYs present in the
   *phy* phandle.

Optional properties:
 - ctrl-module : phandle of the control module this glue uses to write to
   mailbox

SOC specific device node entry
usb_otg_hs: usb_otg_hs@4a0ab000 {
	compatible = "ti,omap4-musb";
	ti,hwmods = "usb_otg_hs";
	multipoint = <1>;
	num-eps = <16>;
	ram-bits = <12>;
	ctrl-module = <&omap_control_usb>;
	phys = <&usb2_phy>;
	phy-names = "usb2-phy";
};

Board specific device node entry
&usb_otg_hs {
	interface-type = <1>;
	mode = <3>;
	power = <50>;
};

OMAP DWC3 GLUE
 - compatible : Should be
	* "ti,dwc3" for OMAP5 and DRA7
	* "ti,am437x-dwc3" for AM437x
 - ti,hwmods : Should be "usb_otg_ss"
 - reg : Address and length of the register set for the device.
 - interrupts : The irq number of this device that is used to interrupt the
   MPU
 - #address-cells, #size-cells : Must be present if the device has sub-nodes
 - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
   It should be set to "1" for HW mode and "2" for SW mode.
 - ranges: the child address space are mapped 1:1 onto the parent address space

Optional Properties:
 - extcon : phandle for the extcon device omap dwc3 uses to detect
   connect/disconnect events.
 - vbus-supply : phandle to the regulator device tree node if needed.

Sub-nodes:
The dwc3 core should be added as subnode to omap dwc3 glue.
- dwc3 :
   The binding details of dwc3 can be found in:
   Documentation/devicetree/bindings/usb/snps,dwc3.yaml

omap_dwc3 {
	compatible = "ti,dwc3";
	ti,hwmods = "usb_otg_ss";
	reg = <0x4a020000 0x1ff>;
	interrupts = <0 93 4>;
	#address-cells = <1>;
	#size-cells = <1>;
	utmi-mode = <2>;
	ranges;
};


code:
PXA USB controllers

OHCI

Required properties:
 - compatible: Should be "marvell,pxa-ohci" for USB controllers
   used in host mode.

Optional properties:
 - "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3"
   If present, enables the appropriate USB port of the controller.
 - "marvell,port-mode" selects the mode of the ports:
	1 = PMM_NPS_MODE
	2 = PMM_GLOBAL_MODE
	3 = PMM_PERPORT_MODE
 - "marvell,power-sense-low" - power sense pin is low-active.
 - "marvell,power-control-low" - power control pin is low-active.
 - "marvell,no-oc-protection" - disable over-current protection.
 - "marvell,oc-mode-perport" - enable per-port over-current protection.
 - "marvell,power_on_delay" Power On to Power Good time - in ms.

Example:

	usb0: ohci@4c000000 {
		compatible = "marvell,pxa-ohci", "usb-ohci";
		reg = <0x4c000000 0x100000>;
		interrupts = <18>;
		marvell,enable-port1;
		marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */
	};

UDC

Required properties:
 - compatible: Should be "marvell,pxa270-udc" for USB controllers
   used in device mode.
 - reg: usb device MMIO address space
 - interrupts: single interrupt generated by the UDC IP
 - clocks: input clock of the UDC IP (see clock-bindings.txt)

Optional properties:
 - gpios:
   - gpio activated to control the USB D+ pullup (see gpio.txt)

Example:

		pxa27x_udc: udc@40600000 {
			compatible = "marvell,pxa270-udc";
			reg = <0x40600000 0x10000>;
			interrupts = <11>;
			clocks = <&pxa2xx_clks 11>;
			gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
		};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SuperSpeed DWC3 USB SoC controller

maintainers:
  - Wesley Cheng <quic_wcheng@quicinc.com>

properties:
  compatible:
    items:
      - enum:
          - qcom,ipq4019-dwc3
          - qcom,ipq6018-dwc3
          - qcom,ipq8064-dwc3
          - qcom,ipq8074-dwc3
          - qcom,msm8953-dwc3
          - qcom,msm8994-dwc3
          - qcom,msm8996-dwc3
          - qcom,msm8998-dwc3
          - qcom,qcs404-dwc3
          - qcom,sc7180-dwc3
          - qcom,sc7280-dwc3
          - qcom,sc8280xp-dwc3
          - qcom,sdm660-dwc3
          - qcom,sdm670-dwc3
          - qcom,sdm845-dwc3
          - qcom,sdx55-dwc3
          - qcom,sdx65-dwc3
          - qcom,sm4250-dwc3
          - qcom,sm6115-dwc3
          - qcom,sm6125-dwc3
          - qcom,sm6350-dwc3
          - qcom,sm6375-dwc3
          - qcom,sm8150-dwc3
          - qcom,sm8250-dwc3
          - qcom,sm8350-dwc3
          - qcom,sm8450-dwc3
          - qcom,sm8550-dwc3
      - const: qcom,dwc3

  reg:
    description: Offset and length of register set for QSCRATCH wrapper
    maxItems: 1

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

  ranges: true

  power-domains:
    description: specifies a phandle to PM domain provider node
    maxItems: 1

  clocks:
    description: |
      Several clocks are used, depending on the variant. Typical ones are::
       - cfg_noc:: System Config NOC clock.
       - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
                60MHz for HS operation.
       - iface:: System bus AXI clock.
       - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
                 power mode (U3).
       - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
                     mode. Its frequency should be 19.2MHz.
    minItems: 1
    maxItems: 9

  clock-names:
    minItems: 1
    maxItems: 9

  assigned-clocks:
    items:
      - description: Phandle and clock specifier of MOCK_UTMI_CLK.
      - description: Phandle and clock specifoer of MASTER_CLK.

  assigned-clock-rates:
    items:
      - description: Must be 19.2MHz (19200000).
      - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
  resets:
    maxItems: 1

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: usb-ddr
      - const: apps-usb

  interrupts:
    minItems: 1
    maxItems: 4

  interrupt-names:
    minItems: 1
    maxItems: 4

  qcom,select-utmi-as-pipe-clk:
    description:
      If present, disable USB3 pipe_clk requirement.
      Used when dwc3 operates without SSPHY and only
      HS/FS/LS modes are supported.
    type: boolean

  wakeup-source: true

# Required child node:

patternProperties:
  "^usb@[0-9a-f]+$":
    $ref: snps,dwc3.yaml#

    properties:
      wakeup-source: false

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - power-domains
  - clocks
  - clock-names
  - interrupts
  - interrupt-names

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq4019-dwc3
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          items:
            - const: core
            - const: sleep
            - const: mock_utmi

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq8064-dwc3
    then:
      properties:
        clocks:
          items:
            - description: Master/Core clock, has to be >= 125 MHz
                for SS operation and >= 60MHz for HS operation.
        clock-names:
          items:
            - const: core

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8953-dwc3
              - qcom,msm8996-dwc3
              - qcom,msm8998-dwc3
              - qcom,sc7180-dwc3
              - qcom,sc7280-dwc3
              - qcom,sdm670-dwc3
              - qcom,sdm845-dwc3
              - qcom,sdx55-dwc3
              - qcom,sm6350-dwc3
    then:
      properties:
        clocks:
          maxItems: 5
        clock-names:
          items:
            - const: cfg_noc
            - const: core
            - const: iface
            - const: sleep
            - const: mock_utmi

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq6018-dwc3
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 4
        clock-names:
          oneOf:
            - items:
                - const: core
                - const: sleep
                - const: mock_utmi
            - items:
                - const: cfg_noc
                - const: core
                - const: sleep
                - const: mock_utmi

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq8074-dwc3
    then:
      properties:
        clocks:
          maxItems: 4
        clock-names:
          items:
            - const: cfg_noc
            - const: core
            - const: sleep
            - const: mock_utmi

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8994-dwc3
              - qcom,qcs404-dwc3
    then:
      properties:
        clocks:
          maxItems: 4
        clock-names:
          items:
            - const: core
            - const: iface
            - const: sleep
            - const: mock_utmi

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc8280xp-dwc3
    then:
      properties:
        clocks:
          maxItems: 9
        clock-names:
          items:
            - const: cfg_noc
            - const: core
            - const: iface
            - const: sleep
            - const: mock_utmi
            - const: noc_aggr
            - const: noc_aggr_north
            - const: noc_aggr_south
            - const: noc_sys

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdm660-dwc3
    then:
      properties:
        clocks:
          minItems: 6
        clock-names:
          items:
            - const: cfg_noc
            - const: core
            - const: iface
            - const: sleep
            - const: mock_utmi
            - const: bus

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sm6115-dwc3
              - qcom,sm6125-dwc3
              - qcom,sm8150-dwc3
              - qcom,sm8250-dwc3
              - qcom,sm8450-dwc3
              - qcom,sm8550-dwc3
    then:
      properties:
        clocks:
          minItems: 6
        clock-names:
          items:
            - const: cfg_noc
            - const: core
            - const: iface
            - const: sleep
            - const: mock_utmi
            - const: xo

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sm8350-dwc3
    then:
      properties:
        clocks:
          minItems: 5
          maxItems: 6
        clock-names:
          minItems: 5
          items:
            - const: cfg_noc
            - const: core
            - const: iface
            - const: sleep
            - const: mock_utmi
            - const: xo

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq4019-dwc3
              - qcom,ipq6018-dwc3
              - qcom,ipq8064-dwc3
              - qcom,ipq8074-dwc3
              - qcom,msm8994-dwc3
              - qcom,qcs404-dwc3
              - qcom,sc7180-dwc3
              - qcom,sdm670-dwc3
              - qcom,sdm845-dwc3
              - qcom,sdx55-dwc3
              - qcom,sdx65-dwc3
              - qcom,sm4250-dwc3
              - qcom,sm6125-dwc3
              - qcom,sm6350-dwc3
              - qcom,sm8150-dwc3
              - qcom,sm8250-dwc3
              - qcom,sm8350-dwc3
              - qcom,sm8450-dwc3
              - qcom,sm8550-dwc3
    then:
      properties:
        interrupts:
          items:
            - description: The interrupt that is asserted
                when a wakeup event is received on USB2 bus.
            - description: The interrupt that is asserted
                when a wakeup event is received on USB3 bus.
            - description: Wakeup event on DM line.
            - description: Wakeup event on DP line.
        interrupt-names:
          items:
            - const: hs_phy_irq
            - const: ss_phy_irq
            - const: dm_hs_phy_irq
            - const: dp_hs_phy_irq

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8953-dwc3
              - qcom,msm8996-dwc3
              - qcom,msm8998-dwc3
              - qcom,sm6115-dwc3
    then:
      properties:
        interrupts:
          maxItems: 2
        interrupt-names:
          items:
            - const: hs_phy_irq
            - const: ss_phy_irq

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdm660-dwc3
    then:
      properties:
        interrupts:
          minItems: 1
          maxItems: 2
        interrupt-names:
          minItems: 1
          items:
            - const: hs_phy_irq
            - const: ss_phy_irq

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc7280-dwc3
    then:
      properties:
        interrupts:
          minItems: 3
          maxItems: 4
        interrupt-names:
          minItems: 3
          items:
            - const: hs_phy_irq
            - const: dp_hs_phy_irq
            - const: dm_hs_phy_irq
            - const: ss_phy_irq

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc8280xp-dwc3
    then:
      properties:
        interrupts:
          maxItems: 4
        interrupt-names:
          items:
            - const: pwr_event
            - const: dp_hs_phy_irq
            - const: dm_hs_phy_irq
            - const: ss_phy_irq

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        usb@a6f8800 {
            compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
            reg = <0 0x0a6f8800 0 0x400>;

            #address-cells = <2>;
            #size-cells = <2>;
            ranges;
            clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
                     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
                     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
                     <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
                     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
            clock-names = "cfg_noc",
                          "core",
                          "iface",
                          "sleep",
                          "mock_utmi";

            assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
            assigned-clock-rates = <19200000>, <150000000>;

            interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "hs_phy_irq", "ss_phy_irq",
                          "dm_hs_phy_irq", "dp_hs_phy_irq";

            power-domains = <&gcc USB30_PRIM_GDSC>;

            resets = <&gcc GCC_USB30_PRIM_BCR>;

            usb@a600000 {
                compatible = "snps,dwc3";
                reg = <0 0x0a600000 0 0xcd00>;
                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
                iommus = <&apps_smmu 0x740 0>;
                snps,dis_u2_susphy_quirk;
                snps,dis_enblslpm_quirk;
                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
                phy-names = "usb2-phy", "usb3-phy";
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/realtek,rts5411.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Binding for the Realtek RTS5411 USB 3.0 hub controller

maintainers:
  - Matthias Kaehlcke <mka@chromium.org>

allOf:
  - $ref: usb-device.yaml#

properties:
  compatible:
    items:
      - enum:
          - usbbda,5411
          - usbbda,411

  reg: true

  vdd-supply:
    description:
      phandle to the regulator that provides power to the hub.

  peer-hub:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description:
      phandle to the peer hub on the controller.

required:
  - peer-hub
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    usb {
        dr_mode = "host";
        #address-cells = <1>;
        #size-cells = <0>;

        /* 2.0 hub on port 1 */
        hub_2_0: hub@1 {
            compatible = "usbbda,5411";
            reg = <1>;
            vdd-supply = <&pp3300_hub>;
            peer-hub = <&hub_3_0>;
        };

        /* 3.0 hub on port 2 */
        hub_3_0: hub@2 {
            compatible = "usbbda,411";
            reg = <2>;
            vdd-supply = <&pp3300_hub>;
            peer-hub = <&hub_2_0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/renesas,usb-xhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas USB xHCI controllers

maintainers:
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

allOf:
  - $ref: "usb-xhci.yaml"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,xhci-r8a7742 # RZ/G1H
              - renesas,xhci-r8a7743 # RZ/G1M
              - renesas,xhci-r8a7744 # RZ/G1N
              - renesas,xhci-r8a7790 # R-Car H2
              - renesas,xhci-r8a7791 # R-Car M2-W
              - renesas,xhci-r8a7793 # R-Car M2-N
          - const: renesas,rcar-gen2-xhci # R-Car Gen2 and RZ/G1
      - items:
          - enum:
              - renesas,xhci-r8a774a1 # RZ/G2M
              - renesas,xhci-r8a774b1 # RZ/G2N
              - renesas,xhci-r8a774c0 # RZ/G2E
              - renesas,xhci-r8a774e1 # RZ/G2H
              - renesas,xhci-r8a7795  # R-Car H3
              - renesas,xhci-r8a7796  # R-Car M3-W
              - renesas,xhci-r8a77961 # R-Car M3-W+
              - renesas,xhci-r8a77965 # R-Car M3-N
              - renesas,xhci-r8a77990 # R-Car E3
          - const: renesas,rcar-gen3-xhci # R-Car Gen3 and RZ/G2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: usb

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains
  - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    xhci0: usb@ee000000 {
        compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
        reg = <0xee000000 0xc00>;
        interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD 328>;
        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
        resets = <&cpg 328>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/renesas,usb3-peri.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas USB 3.0 Peripheral controller

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,r8a774a1-usb3-peri # RZ/G2M
              - renesas,r8a774b1-usb3-peri # RZ/G2N
              - renesas,r8a774c0-usb3-peri # RZ/G2E
              - renesas,r8a774e1-usb3-peri # RZ/G2H
              - renesas,r8a7795-usb3-peri  # R-Car H3
              - renesas,r8a7796-usb3-peri  # R-Car M3-W
              - renesas,r8a77961-usb3-peri # R-Car M3-W+
              - renesas,r8a77965-usb3-peri # R-Car M3-N
              - renesas,r8a77990-usb3-peri # R-Car E3
          - const: renesas,rcar-gen3-usb3-peri

      - items:
          - enum:
              - renesas,r9a09g011-usb3-peri # RZ/V2M
          - const: renesas,rzv2m-usb3-peri

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    items:
      - description: Combined interrupt for DMA, SYS and ERR
      - description: Dual Role Device (DRD)
      - description: Battery Charging
      - description: Global Purpose Input

  interrupt-names:
    minItems: 1
    items:
      - const: all_p
      - const: drd
      - const: bc
      - const: gpi

  clocks:
    minItems: 1
    items:
      - description: Main clock
      - description: Register access clock

  clock-names:
    minItems: 1
    items:
      - const: aclk
      - const: reg

  phys:
    maxItems: 1

  phy-names:
    const: usb

  power-domains:
    maxItems: 1

  resets:
    minItems: 1
    items:
      - description: Peripheral reset
      - description: DRD reset

  reset-names:
    items:
      - const: aresetn_p
      - const: drd_reset

  usb-role-switch:
    $ref: /schemas/types.yaml#/definitions/flag
    description: Support role switch.

  companion:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle of a companion.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description: |
      any connector to the data bus of this controller should be modelled
      using the OF graph bindings specified, if the "usb-role-switch"
      property is used.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: High Speed (HS) data bus.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Super Speed (SS) data bus.

    required:
      - port@0
      - port@1

required:
  - compatible
  - interrupts
  - clocks

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,rzv2m-usb3-peri
    then:
      properties:
        clocks:
          minItems: 2
        clock-names:
          minItems: 2
        interrupts:
          minItems: 4
        interrupt-names:
          minItems: 4
        resets:
          minItems: 2
      required:
        - clock-names
        - interrupt-names
        - resets
        - reset-names
    else:
      properties:
        clocks:
          maxItems: 1
        interrupts:
          maxItems: 1
        resets:
          maxItems: 1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a774c0-sysc.h>

    usb3_peri0: usb@ee020000 {
        compatible = "renesas,r8a774c0-usb3-peri", "renesas,rcar-gen3-usb3-peri";
        reg = <0xee020000 0x400>;
        interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD 328>;
        companion = <&xhci0>;
        usb-role-switch;

        ports {
                #address-cells = <1>;
                #size-cells = <0>;
                port@0 {
                        reg = <0>;
                        usb3_hs_ep: endpoint {
                                remote-endpoint = <&hs_ep>;
                        };
                };
                port@1 {
                        reg = <1>;
                        usb3_role_switch: endpoint {
                                remote-endpoint = <&hd3ss3220_out_ep>;
                        };
                };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/renesas,usbhs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas USBHS (HS-USB) controller

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

properties:
  compatible:
    oneOf:
      - items:
          - const: renesas,usbhs-r7s72100 # RZ/A1
          - const: renesas,rza1-usbhs

      - items:
          - enum:
              - renesas,usbhs-r7s9210   # RZ/A2
              - renesas,usbhs-r9a07g043 # RZ/G2UL
              - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
              - renesas,usbhs-r9a07g054 # RZ/V2L
          - const: renesas,rza2-usbhs

      - items:
          - enum:
              - renesas,usbhs-r8a7742  # RZ/G1H
              - renesas,usbhs-r8a7743  # RZ/G1M
              - renesas,usbhs-r8a7744  # RZ/G1N
              - renesas,usbhs-r8a7745  # RZ/G1E
              - renesas,usbhs-r8a77470 # RZ/G1C
              - renesas,usbhs-r8a7790  # R-Car H2
              - renesas,usbhs-r8a7791  # R-Car M2-W
              - renesas,usbhs-r8a7792  # R-Car V2H
              - renesas,usbhs-r8a7793  # R-Car M2-N
              - renesas,usbhs-r8a7794  # R-Car E2
          - const: renesas,rcar-gen2-usbhs

      - items:
          - enum:
              - renesas,usbhs-r8a774a1 # RZ/G2M
              - renesas,usbhs-r8a774b1 # RZ/G2N
              - renesas,usbhs-r8a774c0 # RZ/G2E
              - renesas,usbhs-r8a774e1 # RZ/G2H
              - renesas,usbhs-r8a7795  # R-Car H3
              - renesas,usbhs-r8a7796  # R-Car M3-W
              - renesas,usbhs-r8a77961 # R-Car M3-W+
              - renesas,usbhs-r8a77965 # R-Car M3-N
              - renesas,usbhs-r8a77990 # R-Car E3
              - renesas,usbhs-r8a77995 # R-Car D3
          - const: renesas,rcar-gen3-usbhs

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: USB 2.0 host
      - description: USB 2.0 peripheral
      - description: USB 2.0 clock selector

  interrupts:
    minItems: 1
    maxItems: 4

  renesas,buswait:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Integer to use BUSWAIT register.

  renesas,enable-gpio:
    maxItems: 1
    description: |
      gpio specifier to check GPIO determining if USB function should be
      enabled.

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: usb

  dmas:
    minItems: 2
    maxItems: 4

  dma-names:
    minItems: 2
    items:
      - const: ch0
      - const: ch1
      - const: ch2
      - const: ch3

  dr_mode: true

  power-domains:
    maxItems: 1

  resets:
    minItems: 1
    items:
      - description: USB 2.0 host
      - description: USB 2.0 peripheral

required:
  - compatible
  - reg
  - clocks
  - interrupts

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,usbhs-r9a07g043
              - renesas,usbhs-r9a07g044
              - renesas,usbhs-r9a07g054
    then:
      properties:
        interrupts:
          items:
            - description: U2P_IXL_INT
            - description: U2P_INT_DMA[0]
            - description: U2P_INT_DMA[1]
            - description: U2P_INT_DMAERR
      required:
        - resets
    else:
      properties:
        interrupts:
          maxItems: 1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>

    usbhs: usb@e6590000 {
        compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
        reg = <0xe6590000 0x100>;
        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD 704>;
    };


code:
Richtek RT1711H TypeC PD Controller.

Required properties:
 - compatible : Must be "richtek,rt1711h".
 - reg : Must be 0x4e, it's slave address of RT1711H.
 - interrupts : <a b> where a is the interrupt number and b represents an
   encoding of the sense and level information for the interrupt.

Required sub-node:
- connector: The "usb-c-connector" attached to the tcpci chip, the bindings
  of connector node are specified in
  Documentation/devicetree/bindings/connector/usb-connector.yaml

Example :
rt1711h@4e {
	compatible = "richtek,rt1711h";
	reg = <0x4e>;
	interrupt-parent = <&gpio26>;
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;

	usb_con: connector {
		compatible = "usb-c-connector";
		label = "USB-C";
		data-role = "dual";
		power-role = "dual";
		try-power-role = "sink";
		source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
		sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
			     PDO_VAR(5000, 12000, 2000)>;
		op-sink-microwatt = <10000000>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <1>;
				usb_con_ss: endpoint {
					remote-endpoint = <&usb3_data_ss>;
				};
			};
		};
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/usb/richtek,rt1711h.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Richtek RT1711H Type-C Port Switch and Power Delivery controller

maintainers:
  - Gene Chen <gene_chen@richtek.com>

description: |
  The RT1711H is a USB Type-C controller that complies with the latest
  USB Type-C and PD standards. It does the USB Type-C detection including attach
  and orientation. It integrates the physical layer of the USB BMC power
  delivery protocol to allow up to 100W of power. The BMC PD block enables full
  support for alternative interfaces of the Type-C specification.

properties:
  compatible:
    enum:
      - richtek,rt1711h
      - richtek,rt1715
    description:
      RT1711H support PD20, RT1715 support PD30 except Fast Role Swap.

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  wakeup-source:
    type: boolean

  connector:
    type: object
    $ref: /schemas/connector/usb-connector.yaml#
    description:
      Properties for usb c connector.

additionalProperties: false

required:
  - compatible
  - reg
  - connector
  - interrupts

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/usb/pd.h>
    i2c0 {
      #address-cells = <1>;
      #size-cells = <0>;

      rt1711h@4e {
        compatible = "richtek,rt1711h";
        reg = <0x4e>;
        interrupts-extended = <&gpio26 3 IRQ_TYPE_LEVEL_LOW>;
        wakeup-source;

        connector {
          compatible = "usb-c-connector";
          label = "USB-C";
          data-role = "dual";
          power-role = "dual";
          try-power-role = "sink";
          source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
          sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
          op-sink-microwatt = <10000000>;

          ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
              reg = <0>;
              endpoint {
                remote-endpoint = <&usb_hs>;
              };
            };
            port@1 {
              reg = <1>;
              endpoint {
                remote-endpoint = <&usb_ss>;
              };
            };
            port@2 {
              reg = <2>;
              endpoint {
                remote-endpoint = <&dp_aux>;
              };
            };
          };
        };
      };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: "http://devicetree.org/schemas/usb/richtek,rt1719.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Richtek RT1719 sink-only Type-C PD controller bindings

maintainers:
  - ChiYuan Huang <cy_huang@richtek.com>

description: |
  The RT1719 is a sink-only USB Type-C contoller that complies with the latest
  USB Type-C and PD standards. It does the USB Type-C detection including attach
  and orientation. It integrates the physical layer of the USB BMC power
  delivery protocol to allow up to 100W of power. The BMC PD block enables full
  support for alternative interfaces of the Type-C specification.

properties:
  compatible:
    enum:
      - richtek,rt1719

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  wakeup-source:
    description: enable IRQ remote wakeup, see power/wakeup-source.txt
    type: boolean

  connector:
    type: object
    $ref: ../connector/usb-connector.yaml#
    description:
      Properties for usb c connector.

additionalProperties: false

required:
  - compatible
  - reg
  - connector
  - interrupts

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c0 {
      #address-cells = <1>;
      #size-cells = <0>;

      rt1719@43 {
        compatible = "richtek,rt1719";
        reg = <0x43>;
        interrupts-extended = <&gpio26 2 IRQ_TYPE_LEVEL_LOW>;
        wakeup-source;

        connector {
          compatible = "usb-c-connector";
          label = "USB-C";

          ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
              reg = <0>;
              endpoint {
                remote-endpoint = <&usb_hs>;
              };
            };
            port@1 {
              reg = <1>;
              endpoint {
                remote-endpoint = <&usb_ss>;
              };
            };
          };
        };
      };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip SuperSpeed DWC3 USB SoC controller

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

description:
  The common content of the node is defined in snps,dwc3.yaml.

  Phy documentation is provided in the following places.

  USB2.0 PHY
  Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml

  Type-C PHY
  Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt

allOf:
  - $ref: snps,dwc3.yaml#

select:
  properties:
    compatible:
      contains:
        enum:
          - rockchip,rk3328-dwc3
          - rockchip,rk3399-dwc3
          - rockchip,rk3568-dwc3
  required:
    - compatible

properties:
  compatible:
    items:
      - enum:
          - rockchip,rk3328-dwc3
          - rockchip,rk3399-dwc3
          - rockchip,rk3568-dwc3
      - const: snps,dwc3

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    items:
      - description:
          Controller reference clock, must to be 24 MHz
      - description:
          Controller suspend clock, must to be 24 MHz or 32 KHz
      - description:
          Master/Core clock, must to be >= 62.5 MHz for SS
          operation and >= 30MHz for HS operation
      - description:
          Controller grf clock

  clock-names:
    minItems: 3
    items:
      - const: ref_clk
      - const: suspend_clk
      - const: bus_clk
      - const: grf_clk

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  reset-names:
    const: usb3-otg

unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

examples:
  - |
    #include <dt-bindings/clock/rk3399-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    bus {
      #address-cells = <2>;
      #size-cells = <2>;

      usbdrd3_0: usb@fe800000 {
        compatible = "rockchip,rk3399-dwc3", "snps,dwc3";
        reg = <0x0 0xfe800000 0x0 0x100000>;
        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
                 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
        clock-names = "ref_clk", "suspend_clk",
                      "bus_clk", "grf_clk";
        dr_mode = "otg";
      };
    };


code:
Samsung S3C2410 and compatible SoC USB controller

OHCI

Required properties:
 - compatible: should be "samsung,s3c2410-ohci" for USB host controller
 - reg: address and length of the controller memory mapped region
 - interrupts: interrupt number for the USB OHCI controller
 - clocks: Should reference the bus and host clocks
 - clock-names: Should contain two strings
		"usb-bus-host" for the USB bus clock
		"usb-host" for the USB host clock

Example:

usb0: ohci@49000000 {
	compatible = "samsung,s3c2410-ohci";
	reg = <0x49000000 0x100>;
	interrupts = <0 0 26 3>;
	clocks = <&clocks UCLK>, <&clocks HCLK_USBH>;
	clock-names = "usb-bus-host", "usb-host";
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/samsung,exynos-dwc3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC USB 3.0 DWC3 Controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - samsung,exynos5250-dwusb3
      - samsung,exynos5433-dwusb3
      - samsung,exynos7-dwusb3

  '#address-cells':
    const: 1

  clocks:
    minItems: 1
    maxItems: 4

  clock-names:
    minItems: 1
    maxItems: 4

  ranges: true

  '#size-cells':
    const: 1

  vdd10-supply:
    description: 1.0V power supply

  vdd33-supply:
    description: 3.0V/3.3V power supply

patternProperties:
  "^usb@[0-9a-f]+$":
    $ref: snps,dwc3.yaml#
    description: Required child node

required:
  - compatible
  - '#address-cells'
  - clocks
  - clock-names
  - ranges
  - '#size-cells'
  - vdd10-supply
  - vdd33-supply

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5250-dwusb3
    then:
      properties:
        clocks:
          minItems: 1
          maxItems: 1
        clock-names:
          items:
            - const: usbdrd30

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos54333-dwusb3
    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4
        clock-names:
          items:
            - const: aclk
            - const: susp_clk
            - const: pipe_pclk
            - const: phyclk

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7-dwusb3
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: usbdrd30
            - const: usbdrd30_susp_clk
            - const: usbdrd30_axius_clk

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5420.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    usb {
        compatible = "samsung,exynos5250-dwusb3";
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;
        clocks = <&clock CLK_USBD300>;
        clock-names = "usbdrd30";
        vdd33-supply = <&ldo9_reg>;
        vdd10-supply = <&ldo11_reg>;

        usb@12000000 {
            compatible = "snps,dwc3";
            reg = <0x12000000 0x10000>;
            interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
            phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
            phy-names = "usb2-phy", "usb3-phy";
            snps,dis_u3_susphy_quirk;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/samsung,exynos-usb2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC USB 2.0 EHCI/OHCI Controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - samsung,exynos4210-ehci
      - samsung,exynos4210-ohci

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: usbhost

  interrupts:
    maxItems: 1

  phys:
    minItems: 1
    maxItems: 3

  phy-names:
    items:
      enum: [host, hsic0, hsic1]
    minItems: 1
    maxItems: 3

  reg:
    maxItems: 1

  samsung,vbus-gpio:
    description:
      Only for controller in EHCI mode, if present, specifies the GPIO that
      needs to be pulled up for the bus to be powered.

required:
  - compatible
  - clocks
  - clock-names
  - interrupts
  - phys
  - phy-names
  - reg

allOf:
  - $ref: usb-hcd.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos4210-ohci
    then:
      properties:
        samsung,vbus-gpio: false

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5420.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    usb@12110000 {
        compatible = "samsung,exynos4210-ehci";
        reg = <0x12110000 0x100>;
        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clock CLK_USBH20>;
        clock-names = "usbhost";
        phys = <&usb2_phy 0>;
        phy-names = "host";

        #address-cells = <1>;
        #size-cells = <0>;

        hub@1 {
            compatible = "usb0424,9514";
            reg = <1>;
            #address-cells = <1>;
            #size-cells = <0>;

            usbether@1 {
                compatible = "usb0424,ec00";
                reg = <1>;
                local-mac-address = [00 00 00 00 00 00];
            };
        };
    };

    usb@12120000 {
        compatible = "samsung,exynos4210-ohci";
        reg = <0x12120000 0x100>;
        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clock CLK_USBH20>;
        clock-names = "usbhost";
        phys = <&usb2_phy 0>;
        phy-names = "host";
    };


code:
Samsung High Speed USB OTG controller
-----------------------------

The Samsung HSOTG IP can be found on Samsung SoCs, from S3C6400 onwards.
It gives functionality of OTG-compliant USB 2.0 host and device with
support for USB 2.0 high-speed (480Mbps) and full-speed (12 Mbps)
operation.

Currently only device mode is supported.

Binding details
-----

Required properties:
- compatible: "samsung,s3c6400-hsotg" should be used for all currently
    supported SoC,
- interrupts: specifier of interrupt signal of interrupt controller,
    according to bindings of interrupt controller,
- clocks: contains an array of clock specifiers:
    - first entry: OTG clock
- clock-names: contains array of clock names:
    - first entry: must be "otg"
- vusb_d-supply: phandle to voltage regulator of digital section,
- vusb_a-supply: phandle to voltage regulator of analog section.

Example
-----

	hsotg@12480000 {
		compatible = "samsung,s3c6400-hsotg";
		reg = <0x12480000 0x20000>;
		interrupts = <0 71 0>;
		clocks = <&clock 305>;
		clock-names = "otg";
		vusb_d-supply = <&vusb_reg>;
		vusb_a-supply = <&vusbdac_reg>;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/smsc,usb3503.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SMSC USB3503 High-Speed Hub Controller

maintainers:
  - Dongjin Kim <tobetter@gmail.com>

properties:
  compatible:
    enum:
      - smsc,usb3503
      - smsc,usb3503a

  reg:
    maxItems: 1

  connect-gpios:
    maxItems: 1
    description: >
      GPIO for connect

  intn-gpios:
    maxItems: 1
    description: >
      GPIO for interrupt

  reset-gpios:
    maxItems: 1
    description: >
      GPIO for reset

  disabled-ports:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 3
    items:
      minimum: 1
      maximum: 3
    description: >
      Specifies the ports unused using their port number. Do not describe this
      property if all ports have to be enabled.

  initial-mode:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2]
    description: >
      Specifies initial mode. 1 for Hub mode, 2 for standby mode.

  clocks:
    maxItems: 1
    description: >
      Clock used for driving REFCLK signal. If not provided the driver assumes
      that clock signal is always available, its rate is specified by REF_SEL
      pins and a value from the primary reference clock frequencies table is
      used.

  clock-names:
    const: refclk

  refclk-frequency:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: >
      Frequency of the REFCLK signal as defined by REF_SEL pins. If not
      provided, driver will not set rate of the REFCLK signal and assume that a
      value from the primary reference clock frequencies table is used.

required:
  - compatible

additionalProperties: false

examples:
  - |
      i2c {
          #address-cells = <1>;
          #size-cells = <0>;

          usb-hub@8 {
              compatible = "smsc,usb3503";
              reg = <0x08>;
              connect-gpios = <&gpx3 0 1>;
              disabled-ports = <2 3>;
              intn-gpios = <&gpx3 4 1>;
              reset-gpios = <&gpx3 5 1>;
              initial-mode = <1>;
              clocks = <&clks 80>;
              clock-names = "refclk";
          };
      };

  - |
      #include <dt-bindings/gpio/gpio.h>

      usb-hub {
          /* I2C is not connected */
          compatible = "smsc,usb3503";
          initial-mode = <1>; /* initialize in HUB mode */
          disabled-ports = <1>;
          intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
          reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
          connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
          refclk-frequency = <19200000>;
      };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare USB3 Controller

maintainers:
  - Felipe Balbi <balbi@kernel.org>

description:
  This is usually a subnode to DWC3 glue to which it is connected, but can also
  be presented as a standalone DT node with an optional vendor-specific
  compatible string.

allOf:
  - $ref: usb-drd.yaml#
  - if:
      properties:
        dr_mode:
          const: peripheral

      required:
        - dr_mode
    then:
      $ref: usb.yaml#
    else:
      $ref: usb-xhci.yaml#

properties:
  compatible:
    contains:
      oneOf:
        - const: snps,dwc3
        - const: synopsys,dwc3
          deprecated: true

  reg:
    maxItems: 1

  interrupts:
    description:
      It's either a single common DWC3 interrupt (dwc_usb3) or individual
      interrupts for the host, gadget and DRD modes.
    minItems: 1
    maxItems: 3

  interrupt-names:
    minItems: 1
    maxItems: 3
    oneOf:
      - const: dwc_usb3
      - items:
          enum: [host, peripheral, otg]

  clocks:
    description:
      In general the core supports three types of clocks. bus_early is a
      SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
      PHY is suspended. suspend clocks a small part of the USB3 core when
      SS PHY in P3. But particular cases may differ from that having less
      or more clock sources with another names.

  clock-names:
    contains:
      anyOf:
        - enum: [bus_early, ref, suspend]
        - true

  dma-coherent: true

  iommus:
    maxItems: 1

  usb-phy:
    minItems: 1
    items:
      - description: USB2/HS PHY
      - description: USB3/SS PHY

  phys:
    minItems: 1
    maxItems: 2

  phy-names:
    minItems: 1
    maxItems: 2
    items:
      enum:
        - usb2-phy
        - usb3-phy

  resets:
    minItems: 1

  snps,usb2-lpm-disable:
    description: Indicate if we don't want to enable USB2 HW LPM for host
      mode.
    type: boolean

  snps,usb3_lpm_capable:
    description: Determines if platform is USB3 LPM capable
    type: boolean

  snps,usb2-gadget-lpm-disable:
    description: Indicate if we don't want to enable USB2 HW LPM for gadget
      mode.
    type: boolean

  snps,dis-start-transfer-quirk:
    description:
      When set, disable isoc START TRANSFER command failure SW work-around
      for DWC_usb31 version 1.70a-ea06 and prior.
    type: boolean

  snps,disable_scramble_quirk:
    description:
      True when SW should disable data scrambling. Only really useful for FPGA
      builds.
    type: boolean

  snps,has-lpm-erratum:
    description: True when DWC3 was configured with LPM Erratum enabled
    type: boolean

  snps,lpm-nyet-threshold:
    description: LPM NYET threshold
    $ref: /schemas/types.yaml#/definitions/uint8

  snps,u2exit_lfps_quirk:
    description: Set if we want to enable u2exit lfps quirk
    type: boolean

  snps,u2ss_inp3_quirk:
    description: Set if we enable P3 OK for U2/SS Inactive quirk
    type: boolean

  snps,req_p1p2p3_quirk:
    description:
      When set, the core will always request for P1/P2/P3 transition sequence.
    type: boolean

  snps,del_p1p2p3_quirk:
    description:
      When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
      occur.
    type: boolean

  snps,del_phy_power_chg_quirk:
    description: When set core will delay PHY power change from P0 to P1/P2/P3.
    type: boolean

  snps,lfps_filter_quirk:
    description: When set core will filter LFPS reception.
    type: boolean

  snps,rx_detect_poll_quirk:
    description:
      when set core will disable a 400us delay to start Polling LFPS after
      RX.Detect.
    type: boolean

  snps,tx_de_emphasis_quirk:
    description: When set core will set Tx de-emphasis value
    type: boolean

  snps,tx_de_emphasis:
    description:
      The value driven to the PHY is controlled by the LTSSM during USB3
      Compliance mode.
    $ref: /schemas/types.yaml#/definitions/uint8
    enum:
      - 0 # -6dB de-emphasis
      - 1 # -3.5dB de-emphasis
      - 2 # No de-emphasis

  snps,dis_u3_susphy_quirk:
    description: When set core will disable USB3 suspend phy
    type: boolean

  snps,dis_u2_susphy_quirk:
    description: When set core will disable USB2 suspend phy
    type: boolean

  snps,dis_enblslpm_quirk:
    description:
      When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
      to the PHY.
    type: boolean

  snps,dis-u1-entry-quirk:
    description: Set if link entering into U1 needs to be disabled
    type: boolean

  snps,dis-u2-entry-quirk:
    description: Set if link entering into U2 needs to be disabled
    type: boolean

  snps,dis_rxdet_inp3_quirk:
    description:
      When set core will disable receiver detection in PHY P3 power state.
    type: boolean

  snps,dis-u2-freeclk-exists-quirk:
    description:
      When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
      PHY doesn't provide a free-running PHY clock.
    type: boolean

  snps,dis-del-phy-power-chg-quirk:
    description:
      When set core will change PHY power from P0 to P1/P2/P3 without delay.
    type: boolean

  snps,dis-tx-ipgap-linecheck-quirk:
    description: When set, disable u2mac linestate check during HS transmit
    type: boolean

  snps,parkmode-disable-ss-quirk:
    description:
      When set, all SuperSpeed bus instances in park mode are disabled.
    type: boolean

  snps,dis_metastability_quirk:
    description:
      When set, disable metastability workaround. CAUTION! Use only if you are
      absolutely sure of it.
    type: boolean

  snps,dis-split-quirk:
    description:
      When set, change the way URBs are handled by the driver. Needed to
      avoid -EPROTO errors with usbhid on some devices (Hikey 970).
    type: boolean

  snps,gfladj-refclk-lpm-sel-quirk:
    description:
      When set, run the SOF/ITP counter based on ref_clk.
    type: boolean

  snps,resume-hs-terminations:
    description:
      Fix the issue of HS terminations CRC error on resume by enabling this
      quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
      of resume. This option is to support certain legacy ULPI PHYs.
    type: boolean

  snps,is-utmi-l1-suspend:
    description:
      True when DWC3 asserts output signal utmi_l1_suspend_n, false when
      asserts utmi_sleep_n.
    type: boolean

  snps,hird-threshold:
    description: HIRD threshold
    $ref: /schemas/types.yaml#/definitions/uint8

  snps,hsphy_interface:
    description:
      High-Speed PHY interface selection between UTMI+ and ULPI when the
      DWC_USB3_HSPHY_INTERFACE has value 3.
    $ref: /schemas/types.yaml#/definitions/uint8
    enum: [utmi, ulpi]

  snps,quirk-frame-length-adjustment:
    description:
      Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
      length adjustment when the fladj_30mhz_sdbnd signal is invalid or
      incorrect.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x3f

  snps,ref-clock-period-ns:
    description:
      Value for REFCLKPER field of GUCTL register for reference clock period in
      nanoseconds, when the hardware set default does not match the actual
      clock.

      This binding is deprecated. Instead, provide an appropriate reference clock.
    minimum: 8
    maximum: 62
    deprecated: true

  snps,rx-thr-num-pkt-prd:
    description:
      Periodic ESS RX packet threshold count (host mode only). Set this and
      snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
      programming guide section 1.2.4) to enable periodic ESS RX threshold.
    $ref: /schemas/types.yaml#/definitions/uint8
    minimum: 1
    maximum: 16

  snps,rx-max-burst-prd:
    description:
      Max periodic ESS RX burst size (host mode only). Set this and
      snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
      programming guide section 1.2.4) to enable periodic ESS RX threshold.
    $ref: /schemas/types.yaml#/definitions/uint8
    minimum: 1
    maximum: 16

  snps,tx-thr-num-pkt-prd:
    description:
      Periodic ESS TX packet threshold count (host mode only). Set this and
      snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
      programming guide section 1.2.3) to enable periodic ESS TX threshold.
    $ref: /schemas/types.yaml#/definitions/uint8
    minimum: 1
    maximum: 16

  snps,tx-max-burst-prd:
    description:
      Max periodic ESS TX burst size (host mode only). Set this and
      snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
      programming guide section 1.2.3) to enable periodic ESS TX threshold.
    $ref: /schemas/types.yaml#/definitions/uint8
    minimum: 1
    maximum: 16

  tx-fifo-resize:
    description: Determines if the TX fifos can be dynamically resized depending
      on the number of IN endpoints used and if bursting is supported.  This
      may help improve bandwidth on platforms with higher system latencies, as
      increased fifo space allows for the controller to prefetch data into its
      internal memory.
    type: boolean

  tx-fifo-max-num:
    description: Specifies the max number of packets the txfifo resizing logic
      can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
      higher the number, the more fifo space the txfifo resizing logic will
      allocate for that endpoint.
    $ref: /schemas/types.yaml#/definitions/uint8
    minimum: 3

  snps,incr-burst-type-adjustment:
    description:
      Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
      burst type enable and INCRx type. A single value means INCRX burst mode
      enabled. If more than one value specified, undefined length INCR burst
      type will be enabled with burst lengths utilized up to the maximum
      of the values passed in this property.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 8
    uniqueItems: true
    items:
      enum: [1, 4, 8, 16, 32, 64, 128, 256]

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      This port is used with the 'usb-role-switch' property  to connect the
      dwc3 to type C connector.

  wakeup-source:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Enable USB remote wakeup.

unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts

examples:
  - |
    usb@4a030000 {
      compatible = "snps,dwc3";
      reg = <0x4a030000 0xcfff>;
      interrupts = <0 92 4>;
      usb-phy = <&usb2_phy>, <&usb3_phy>;
      snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
    };
  - |
    usb@4a000000 {
      compatible = "snps,dwc3";
      reg = <0x4a000000 0xcfff>;
      interrupts = <0 92 4>;
      clocks = <&clk 1>, <&clk 2>, <&clk 3>;
      clock-names = "bus_early", "ref", "suspend";
      phys = <&usb2_phy>, <&usb3_phy>;
      phy-names = "usb2-phy", "usb3-phy";
      snps,dis_u2_susphy_quirk;
      snps,dis_enblslpm_quirk;
    };
...


code:
ST SPEAr SoC USB controllers:
-----------------------------

EHCI:
-----

Required properties:
- compatible: "st,spear600-ehci"
- interrupts: Should contain the EHCI interrupt

Example:

	ehci@e1800000 {
		compatible = "st,spear600-ehci", "usb-ehci";
		reg = <0xe1800000 0x1000>;
		interrupt-parent = <&vic1>;
		interrupts = <27>;
	};

OHCI:
-----

Required properties:
- compatible: "st,spear600-ohci"
- interrupts: Should contain the OHCI interrupt

Example:

	ohci@e1900000 {
		compatible = "st,spear600-ohci", "usb-ohci";
		reg = <0xe1800000 0x1000>;
		interrupt-parent = <&vic1>;
		interrupts = <26>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: "http://devicetree.org/schemas/usb/st,stusb160x.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: STMicroelectronics STUSB160x Type-C controller bindings

maintainers:
  - Amelie Delaunay <amelie.delaunay@foss.st.com>

properties:
  compatible:
    enum:
      - st,stusb1600

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  vdd-supply:
    description: main power supply (4.1V-22V)

  vsys-supply:
    description: low power supply (3.0V-5.5V)

  vconn-supply:
    description: power supply (2.7V-5.5V) used to supply VConn on CC pin in
      source or dual power role

  connector:
    type: object
    $ref: /schemas/connector/usb-connector.yaml#
    unevaluatedProperties: false

    properties:
      compatible:
        const: usb-c-connector

      power-role: true

      typec-power-opmode: true

    required:
      - compatible

required:
  - compatible
  - reg
  - connector

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c4 {
        #address-cells = <1>;
        #size-cells = <0>;

        typec: stusb1600@28 {
            compatible = "st,stusb1600";
            reg = <0x28>;
            vdd-supply = <&vbus_drd>;
            vsys-supply = <&vdd_usb>;
            interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
            interrupt-parent = <&gpioi>;

            typec_con: connector {
                compatible = "usb-c-connector";
                label = "USB-C";
                power-role = "dual";
                data-role = "dual";
                typec-power-opmode = "default";

                ports {
                    #address-cells = <1>;
                    #size-cells = <0>;
                    port@0 {
                        reg = <0>;
                        typec_con_ep: endpoint {
                            remote-endpoint = <&usbotg_hs_ep>;
                        };
                    };
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/st,typec-stm32g0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32G0 USB Type-C PD controller

description: |
  The STM32G0 MCU can be programmed to control Type-C connector(s) through I2C
  typically using the UCSI protocol over I2C, with a dedicated alert
  (interrupt) pin.

maintainers:
  - Fabrice Gasnier <fabrice.gasnier@foss.st.com>

properties:
  compatible:
    const: st,stm32g0-typec

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  connector:
    type: object
    $ref: /schemas/connector/usb-connector.yaml#
    unevaluatedProperties: false

  firmware-name:
    description: |
      Should contain the name of the default firmware image
      file located on the firmware search path

  wakeup-source: true

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - connector

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      typec@53 {
        compatible = "st,stm32g0-typec";
        reg = <0x53>;
        /* Alert pin on GPIO PE12 */
        interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
        interrupt-parent = <&gpioe>;

        /* Example with one type-C connector */
        connector {
          compatible = "usb-c-connector";
          label = "USB-C";

          ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@0 {
              reg = <0>;
              con_usb_c_ep: endpoint {
                remote-endpoint = <&usb_ep>;
              };
            };
          };
        };
      };
    };

    usb {
      usb-role-switch;
      port {
        usb_ep: endpoint {
          remote-endpoint = <&con_usb_c_ep>;
        };
      };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/ti,am62-usb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI's AM62 wrapper module for the Synopsys USBSS-DRD controller

maintainers:
  - Aswath Govindraju <a-govindraju@ti.com>

properties:
  compatible:
    const: ti,am62-usb

  reg:
    maxItems: 1

  ranges: true

  power-domains:
    description:
      PM domain provider node and an args specifier containing
      the USB ISO device id value. See,
      Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
    maxItems: 1

  clocks:
    description: Clock phandle to usb2_refclk
    maxItems: 1

  clock-names:
    items:
      - const: ref

  ti,vbus-divider:
    description:
      Should be present if USB VBUS line is connected to the
      VBUS pin of the SoC via a 1/3 voltage divider.
    type: boolean

  ti,syscon-phy-pll-refclk:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to the SYSCON entry
          - description: USB phy control register offset within SYSCON
    description:
      Specifier for conveying frequency of ref clock input, for the
      operation of USB2PHY.

  '#address-cells':
    const: 2

  '#size-cells':
    const: 2

patternProperties:
  "^usb@[0-9a-f]+$":
    $ref: snps,dwc3.yaml#
    description: Required child node

required:
  - compatible
  - reg
  - power-domains
  - clocks
  - clock-names
  - ti,syscon-phy-pll-refclk

additionalProperties: false

examples:
  - |
    #include <dt-bindings/soc/ti,sci_pm_domain.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/gpio/gpio.h>

    bus {
      #address-cells = <2>;
      #size-cells = <2>;

      usbss1: usb@f910000 {
        compatible = "ti,am62-usb";
        reg = <0x00 0x0f910000 0x00 0x800>;
        clocks = <&k3_clks 162 3>;
        clock-names = "ref";
        ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
        power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
        #address-cells = <2>;
        #size-cells = <2>;

        usb@31100000 {
          compatible = "snps,dwc3";
          reg =<0x00 0x31100000 0x00 0x50000>;
          interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
                       <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
          interrupt-names = "host", "peripheral";
          maximum-speed = "high-speed";
          dr_mode = "otg";
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/ti,hd3ss3220.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI HD3SS3220 TypeC DRP Port Controller

maintainers:
  - Biju Das <biju.das.jz@bp.renesas.com>

description: |-
  HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port controller. The device provides Channel
  Configuration (CC) logic and 5V VCONN sourcing for ecosystems implementing USB Type-C. The
  HD3SS3220 can be configured as a Downstream Facing Port (DFP), Upstream Facing Port (UFP) or a
  Dual Role Port (DRP) making it ideal for any application.

properties:
  compatible:
    const: ti,hd3ss3220

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description: OF graph bindings (specified in bindings/graph.txt) that model
      SS data bus to the SS capable connector.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: Super Speed (SS) MUX inputs connected to SS capable connector.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Output of 2:1 MUX connected to Super Speed (SS) data bus.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        hd3ss3220@47 {
                compatible = "ti,hd3ss3220";
                reg = <0x47>;
                interrupt-parent = <&gpio6>;
                interrupts = <3>;

                ports {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        port@0 {
                                reg = <0>;
                                hd3ss3220_in_ep: endpoint {
                                        remote-endpoint = <&ss_ep>;
                                };
                        };
                        port@1 {
                                reg = <1>;
                                hd3ss3220_out_ep: endpoint {
                                        remote-endpoint = <&usb3_role_switch>;
                                };
                        };
                };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller

maintainers:
  - Roger Quadros <rogerq@kernel.org>

properties:
  compatible:
    oneOf:
      - const: ti,j721e-usb
      - const: ti,am64-usb
      - items:
          - const: ti,j721e-usb
          - const: ti,am64-usb

  reg:
    maxItems: 1

  ranges: true

  power-domains:
    description:
      PM domain provider node and an args specifier containing
      the USB device id value. See,
      Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
    maxItems: 1

  clocks:
    description: Clock phandles to usb2_refclk and lpm_clk
    minItems: 2
    maxItems: 2

  clock-names:
    items:
      - const: ref
      - const: lpm

  ti,usb2-only:
    description:
      If present, it restricts the controller to USB2.0 mode of
      operation. Must be present if USB3 PHY is not available
      for USB.
    type: boolean

  ti,vbus-divider:
    description:
      Should be present if USB VBUS line is connected to the
      VBUS pin of the SoC via a 1/3 voltage divider.
    type: boolean

  assigned-clocks:
    maxItems: 1

  assigned-clock-parents:
    maxItems: 1

  '#address-cells':
    const: 2

  '#size-cells':
    const: 2

  dma-coherent: true

patternProperties:
  "^usb@":
    type: object

required:
  - compatible
  - reg
  - power-domains
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/soc/ti,sci_pm_domain.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        cdns_usb@4104000 {
            compatible = "ti,j721e-usb";
            reg = <0x00 0x4104000 0x00 0x100>;
            power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
            clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
            clock-names = "ref", "lpm";
            assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
            assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
            #address-cells = <2>;
            #size-cells = <2>;

            usb@6000000 {
                  compatible = "cdns,usb3";
                  reg = <0x00 0x6000000 0x00 0x10000>,
                        <0x00 0x6010000 0x00 0x10000>,
                        <0x00 0x6020000 0x00 0x10000>;
                  reg-names = "otg", "xhci", "dev";
                  interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
                               <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
                               <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
                  interrupt-names = "host",
                                    "peripheral",
                                    "otg";
                  maximum-speed = "super-speed";
                  dr_mode = "otg";
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI Keystone Soc USB Controller

maintainers:
  - Roger Quadros <rogerq@kernel.org>

properties:
  compatible:
    items:
      - enum:
          - ti,keystone-dwc3
          - ti,am654-dwc3

  reg:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  ranges: true

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  assigned-clocks:
    minItems: 1
    maxItems: 2

  assigned-clock-parents:
    minItems: 1
    maxItems: 2

  power-domains:
    maxItems: 1
    description: Should contain a phandle to a PM domain provider node
      and an args specifier containing the USB device id
      value. This property is as per the binding,
      Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml

  phys:
    maxItems: 1
    description:
      PHY specifier for the USB3.0 PHY. Some SoCs need the USB3.0 PHY
      to be turned on before the controller.
      Documentation/devicetree/bindings/phy/phy-bindings.txt

  phy-names:
    items:
      - const: usb3-phy

  dma-coherent: true

  dma-ranges: true

patternProperties:
  "usb@[a-f0-9]+$":
    $ref: snps,dwc3.yaml#

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    dwc3@2680000 {
      compatible = "ti,keystone-dwc3";
      #address-cells = <1>;
      #size-cells = <1>;
      reg = <0x2680000 0x10000>;
      clocks = <&clkusb>;
      interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
      ranges;

      usb@2690000 {
        compatible = "snps,dwc3";
        reg = <0x2690000 0x70000>;
        interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
        usb-phy = <&usb_phy>, <&usb_phy>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/usb/ti,tps6598x.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Texas Instruments 6598x Type-C Port Switch and Power Delivery controller DT bindings

maintainers:
  - Bryan O'Donoghue <bryan.odonoghue@linaro.org>

description: |
  Texas Instruments 6598x Type-C Port Switch and Power Delivery controller

  A variant of this controller known as Apple CD321x or Apple ACE is also
  present on hardware with Apple SoCs such as the M1.

properties:
  compatible:
    enum:
      - ti,tps6598x
      - apple,cd321x
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-names:
    items:
      - const: irq

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names

additionalProperties: true

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        tps6598x: tps6598x@38 {
            compatible = "ti,tps6598x";
            reg = <0x38>;

            interrupt-parent = <&msmgpio>;
            interrupts = <107 IRQ_TYPE_LEVEL_LOW>;
            interrupt-names = "irq";

            pinctrl-names = "default";
            pinctrl-0 = <&typec_pins>;

            typec_con: connector {
                compatible = "usb-c-connector";
                label = "USB-C";
                port {
                    typec_ep: endpoint {
                        remote-endpoint = <&otg_ep>;
                    };
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/ti,usb8041.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Binding for the TI USB8041 USB 3.0 hub controller

maintainers:
  - Alexander Stein <alexander.stein@ew.tq-group.com>

allOf:
  - $ref: usb-device.yaml#

properties:
  compatible:
    enum:
      - usb451,8140
      - usb451,8142

  reg: true

  reset-gpios:
    items:
      - description: GPIO specifier for GRST# pin.

  vdd-supply:
    description:
      VDD power supply to the hub

  peer-hub:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle to the peer hub on the controller.

required:
  - compatible
  - reg
  - peer-hub

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    usb {
        dr_mode = "host";
        #address-cells = <1>;
        #size-cells = <0>;

        /* 2.0 hub on port 1 */
        hub_2_0: hub@1 {
          compatible = "usb451,8142";
          reg = <1>;
          peer-hub = <&hub_3_0>;
          reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
        };

        /* 3.0 hub on port 2 */
        hub_3_0: hub@2 {
          compatible = "usb451,8140";
          reg = <2>;
          peer-hub = <&hub_2_0>;
          reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
        };
    };


code:
USB COMPARATOR OF TWL CHIPS

TWL6030 USB COMPARATOR
 - compatible : Should be "ti,twl6030-usb"
 - interrupts : Two interrupt numbers to the cpu should be specified. First
   interrupt number is the otg interrupt number that raises ID interrupts when
   the controller has to act as host and the second interrupt number is the
   usb interrupt number that raises VBUS interrupts when the controller has to
   act as device
 - usb-supply : phandle to the regulator device tree node. It should be vusb
   if it is twl6030 or ldousb if it is twl6032 subclass.

twl6030-usb {
	compatible = "ti,twl6030-usb";
	interrupts = < 4 10 >;
};

Board specific device node entry
&twl6030-usb {
	usb-supply = <&vusb>;
};

TWL4030 USB PHY AND COMPARATOR
 - compatible : Should be "ti,twl4030-usb"
 - interrupts : The interrupt numbers to the cpu should be specified. First
   interrupt number is the otg interrupt number that raises ID interrupts
   and VBUS interrupts. The second interrupt number is optional.
 - <supply-name>-supply : phandle to the regulator device tree node.
   <supply-name> should be vusb1v5, vusb1v8 and vusb3v1
 - usb_mode : The mode used by the phy to connect to the controller. "1"
   specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode.

If a sibling node is compatible "ti,twl4030-bci", then it will find
this device and query it for USB power status.

twl4030-usb {
	compatible = "ti,twl4030-usb";
	interrupts = < 10 4 >;
	usb1v5-supply = <&vusb1v5>;
	usb1v8-supply = <&vusb1v8>;
	usb3v1-supply = <&vusb3v1>;
	usb_mode = <1>;
};