code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm APQ8064";
	compatible = "qcom,apq8064";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		smem_region: smem@80000000 {
			reg = <0x80000000 0x200000>;
			no-map;
		};

		wcnss_mem: wcnss@8f000000 {
			reg = <0x8f000000 0x700000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		CPU1: cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		CPU2: cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		CPU3: cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <400>;
				exit-latency-us = <900>;
				min-residency-us = <3000>;
			};
		};
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	thermal-zones {
		cpu0-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 7>;
			coefficients = <1199 0>;

			trips {
				cpu_alert0: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu1-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 8>;
			coefficients = <1132 0>;

			trips {
				cpu_alert1: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit1: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu2-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 9>;
			coefficients = <1199 0>;

			trips {
				cpu_alert2: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit2: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu3-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 10>;
			coefficients = <1132 0>;

			trips {
				cpu_alert3: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit3: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 10 0x304>;
	};

	clocks {
		cxo_board: cxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		pxo_board: pxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	sfpb_mutex: hwmutex {
		compatible = "qcom,sfpb-mutex";
		syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
		#hwlock-cells = <1>;
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_region>;

		hwlocks = <&sfpb_mutex 3>;
	};

	smd {
		compatible = "qcom,smd";

		modem-edge {
			interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;

			qcom,ipc = <&l2cc 8 3>;
			qcom,smd-edge = <0>;

			status = "disabled";
		};

		q6-edge {
			interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;

			qcom,ipc = <&l2cc 8 15>;
			qcom,smd-edge = <1>;

			status = "disabled";
		};

		dsps-edge {
			interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;

			qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
			qcom,smd-edge = <3>;

			status = "disabled";
		};

		riva-edge {
			interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;

			qcom,ipc = <&l2cc 8 25>;
			qcom,smd-edge = <6>;

			status = "disabled";
		};
	};

	smsm {
		compatible = "qcom,smsm";

		#address-cells = <1>;
		#size-cells = <0>;

		qcom,ipc-1 = <&l2cc 8 4>;
		qcom,ipc-2 = <&l2cc 8 14>;
		qcom,ipc-3 = <&l2cc 8 23>;
		qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;

		apps_smsm: apps@0 {
			reg = <0>;
			#qcom,smem-state-cells = <1>;
		};

		modem_smsm: modem@1 {
			reg = <1>;
			interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		q6_smsm: q6@2 {
			reg = <2>;
			interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		wcnss_smsm: wcnss@3 {
			reg = <3>;
			interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		dsps_smsm: dsps@4 {
			reg = <4>;
			interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-apq8064", "qcom,scm";

			clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
			clock-names = "core";
		};
	};

	/*
	 * These channels from the ADC are simply hardware monitors.
	 * That is why the ADC is referred to as "HKADC" - HouseKeeping
	 * ADC.
	 */
	iio-hwmon {
		compatible = "iio-hwmon";
		io-channels = <&xoadc 0x00 0x01>, /* Battery */
			    <&xoadc 0x00 0x02>, /* DC in (charger) */
			    <&xoadc 0x00 0x04>, /* VPH the main system voltage */
			    <&xoadc 0x00 0x0b>, /* Die temperature */
			    <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
			    <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
			    <&xoadc 0x00 0x0e>; /* Charger temperature */
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		tlmm_pinmux: pinctrl@800000 {
			compatible = "qcom,apq8064-pinctrl";
			reg = <0x800000 0x4000>;

			gpio-controller;
			gpio-ranges = <&tlmm_pinmux 0 0 90>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;

			pinctrl-names = "default";
			pinctrl-0 = <&ps_hold>;
		};

		sfpb_wrapper_mutex: syscon@1200000 {
			compatible = "syscon";
			reg = <0x01200000 0x8000>;
		};

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-timer",
				     "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
			interrupts = <1 1 0x301>,
				     <1 2 0x301>,
				     <1 3 0x301>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x80000>;
		};

		acc0: clock-controller@2088000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
		};

		acc1: clock-controller@2098000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
		};

		acc2: clock-controller@20a8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
		};

		acc3: clock-controller@20b8000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
		};

		saw0: power-controller@2089000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw1: power-controller@2099000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw2: power-controller@20a9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw3: power-controller@20b9000 {
			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
			reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		sps_sic_non_secure: sps-sic-non-secure@12100000 {
			compatible = "syscon";
			reg = <0x12100000 0x10000>;
		};

		gsbi1: gsbi@12440000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <1>;
			reg = <0x12440000 0x100>;
			clocks = <&gcc GSBI1_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi1_serial: serial@12450000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x12450000 0x100>,
				      <0x12400000 0x03>;
				interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi1_i2c: i2c@12460000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				pinctrl-0 = <&i2c1_pins>;
				pinctrl-1 = <&i2c1_pins_sleep>;
				pinctrl-names = "default", "sleep";
				reg = <0x12460000 0x1000>;
				interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

		};

		gsbi2: gsbi@12480000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <2>;
			reg = <0x12480000 0x100>;
			clocks = <&gcc GSBI2_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi2_i2c: i2c@124a0000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				reg = <0x124a0000 0x1000>;
				pinctrl-0 = <&i2c2_pins>;
				pinctrl-1 = <&i2c2_pins_sleep>;
				pinctrl-names = "default", "sleep";
				interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		gsbi3: gsbi@16200000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <3>;
			reg = <0x16200000 0x100>;
			clocks = <&gcc GSBI3_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			gsbi3_i2c: i2c@16280000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				pinctrl-0 = <&i2c3_pins>;
				pinctrl-1 = <&i2c3_pins_sleep>;
				pinctrl-names = "default", "sleep";
				reg = <0x16280000 0x1000>;
				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI3_QUP_CLK>,
					 <&gcc GSBI3_H_CLK>;
				clock-names = "core", "iface";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		gsbi4: gsbi@16300000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <4>;
			reg = <0x16300000 0x03>;
			clocks = <&gcc GSBI4_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gsbi4_i2c: i2c@16380000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				pinctrl-0 = <&i2c4_pins>;
				pinctrl-1 = <&i2c4_pins_sleep>;
				pinctrl-names = "default", "sleep";
				reg = <0x16380000 0x1000>;
				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI4_QUP_CLK>,
					 <&gcc GSBI4_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi5: gsbi@1a200000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <5>;
			reg = <0x1a200000 0x03>;
			clocks = <&gcc GSBI5_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gsbi5_serial: serial@1a240000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x1a240000 0x100>,
				      <0x1a200000 0x03>;
				interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi5_spi: spi@1a280000 {
				compatible = "qcom,spi-qup-v1.1.1";
				reg = <0x1a280000 0x1000>;
				interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-0 = <&spi5_default>;
				pinctrl-1 = <&spi5_sleep>;
				pinctrl-names = "default", "sleep";
				clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gsbi6: gsbi@16500000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <6>;
			reg = <0x16500000 0x03>;
			clocks = <&gcc GSBI6_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gsbi6_serial: serial@16540000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16540000 0x100>,
				      <0x16500000 0x03>;
				interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi6_i2c: i2c@16580000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				pinctrl-0 = <&i2c6_pins>;
				pinctrl-1 = <&i2c6_pins_sleep>;
				pinctrl-names = "default", "sleep";
				reg = <0x16580000 0x1000>;
				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI6_QUP_CLK>,
					 <&gcc GSBI6_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		gsbi7: gsbi@16600000 {
			status = "disabled";
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <7>;
			reg = <0x16600000 0x100>;
			clocks = <&gcc GSBI7_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			syscon-tcsr = <&tcsr>;

			gsbi7_serial: serial@16640000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16640000 0x1000>,
				      <0x16600000 0x1000>;
				interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};

			gsbi7_i2c: i2c@16680000 {
				compatible = "qcom,i2c-qup-v1.1.1";
				pinctrl-0 = <&i2c7_pins>;
				pinctrl-1 = <&i2c7_pins_sleep>;
				pinctrl-names = "default", "sleep";
				reg = <0x16680000 0x1000>;
				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gcc GSBI7_QUP_CLK>,
					 <&gcc GSBI7_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		rng@1a500000 {
			compatible = "qcom,prng";
			reg = <0x1a500000 0x200>;
			clocks = <&gcc PRNG_CLK>;
			clock-names = "core";
		};

		ssbi@c00000 {
			compatible = "qcom,ssbi";
			reg = <0x00c00000 0x1000>;
			qcom,controller-type = "pmic-arbiter";

			pm8821: pmic {
				compatible = "qcom,pm8821";
				interrupt-parent = <&tlmm_pinmux>;
				interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
				#interrupt-cells = <2>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;

				pm8821_mpps: mpps@50 {
					compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
					reg = <0x50>;
					interrupt-controller;
					#interrupt-cells = <2>;
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&pm8821_mpps 0 0 4>;
				};
			};
		};

		ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x00500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";

			pmicintc: pmic {
				compatible = "qcom,pm8921";
				interrupt-parent = <&tlmm_pinmux>;
				interrupts = <74 8>;
				#interrupt-cells = <2>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;

				pm8921_gpio: gpio@150 {

					compatible = "qcom,pm8921-gpio",
						     "qcom,ssbi-gpio";
					reg = <0x150>;
					interrupt-controller;
					#interrupt-cells = <2>;
					gpio-controller;
					gpio-ranges = <&pm8921_gpio 0 0 44>;
					#gpio-cells = <2>;

				};

				pm8921_mpps: mpps@50 {
					compatible = "qcom,pm8921-mpp",
						     "qcom,ssbi-mpp";
					reg = <0x50>;
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&pm8921_mpps 0 0 12>;
					interrupt-controller;
					#interrupt-cells = <2>;
				};

				rtc@11d {
					compatible = "qcom,pm8921-rtc";
					interrupt-parent = <&pmicintc>;
					interrupts = <39 1>;
					reg = <0x11d>;
					allow-set-time;
				};

				pwrkey@1c {
					compatible = "qcom,pm8921-pwrkey";
					reg = <0x1c>;
					interrupt-parent = <&pmicintc>;
					interrupts = <50 1>, <51 1>;
					debounce = <15625>;
					pull-up;
				};

				xoadc: xoadc@197 {
					compatible = "qcom,pm8921-adc";
					reg = <197>;
					interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
					#address-cells = <2>;
					#size-cells = <0>;
					#io-channel-cells = <2>;

					vcoin: adc-channel@0 {
						reg = <0x00 0x00>;
					};
					vbat: adc-channel@1 {
						reg = <0x00 0x01>;
					};
					dcin: adc-channel@2 {
						reg = <0x00 0x02>;
					};
					vph_pwr: adc-channel@4 {
						reg = <0x00 0x04>;
					};
					batt_therm: adc-channel@8 {
						reg = <0x00 0x08>;
					};
					batt_id: adc-channel@9 {
						reg = <0x00 0x09>;
					};
					usb_vbus: adc-channel@a {
						reg = <0x00 0x0a>;
					};
					die_temp: adc-channel@b {
						reg = <0x00 0x0b>;
					};
					ref_625mv: adc-channel@c {
						reg = <0x00 0x0c>;
					};
					ref_1250mv: adc-channel@d {
						reg = <0x00 0x0d>;
					};
					chg_temp: adc-channel@e {
						reg = <0x00 0x0e>;
					};
					ref_muxoff: adc-channel@f {
						reg = <0x00 0x0f>;
					};
				};
			};
		};

		qfprom: qfprom@700000 {
			compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
			reg = <0x00700000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			tsens_calib: calib@404 {
				reg = <0x404 0x10>;
			};
			tsens_backup: backup_calib@414 {
				reg = <0x414 0x10>;
			};
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-apq8064", "syscon";
			reg = <0x00900000 0x4000>;
			#clock-cells = <1>;
			#power-domain-cells = <1>;
			#reset-cells = <1>;
			clocks = <&cxo_board>,
				 <&pxo_board>,
				 <&lcc PLL4>;
			clock-names = "cxo", "pxo", "pll4";

			tsens: thermal-sensor {
				compatible = "qcom,msm8960-tsens";

				nvmem-cells = <&tsens_calib>, <&tsens_backup>;
				nvmem-cell-names = "calib", "calib_backup";
				interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "uplow";

				#qcom,sensors = <11>;
				#thermal-sensor-cells = <1>;
			};
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-apq8064";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			clocks = <&pxo_board>,
				 <&gcc PLL4_VOTE>,
				 <0>,
				 <0>, <0>,
				 <0>, <0>,
				 <0>;
			clock-names = "pxo",
				      "pll4_vote",
				      "mi2s_codec_clk",
				      "codec_i2s_mic_codec_clk",
				      "spare_i2s_mic_codec_clk",
				      "codec_i2s_spkr_codec_clk",
				      "spare_i2s_spkr_codec_clk",
				      "pcm_codec_clk";
		};

		mmcc: clock-controller@4000000 {
			compatible = "qcom,mmcc-apq8064";
			reg = <0x4000000 0x1000>;
			#clock-cells = <1>;
			#power-domain-cells = <1>;
			#reset-cells = <1>;
			clocks = <&pxo_board>,
				 <&gcc PLL3>,
				 <&gcc PLL8_VOTE>,
				 <&dsi0_phy 1>,
				 <&dsi0_phy 0>,
				 <0>,
				 <0>,
				 <0>;
			clock-names = "pxo",
				      "pll3",
				      "pll8_vote",
				      "dsi1pll",
				      "dsi1pllbyte",
				      "dsi2pll",
				      "dsi2pllbyte",
				      "hdmipll";
		};

		l2cc: clock-controller@2011000 {
			compatible = "qcom,kpss-gcc", "syscon";
			reg = <0x2011000 0x1000>;
		};

		rpm: rpm@108000 {
			compatible = "qcom,rpm-apq8064";
			reg = <0x108000 0x1000>;
			qcom,ipc = <&l2cc 0x8 2>;

			interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "ack", "err", "wakeup";

			rpmcc: clock-controller {
				compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
				#clock-cells = <1>;
				clocks = <&pxo_board>, <&cxo_board>;
				clock-names = "pxo", "cxo";
			};

			regulators {
				compatible = "qcom,rpm-pm8921-regulators";

				pm8921_s1: s1 {};
				pm8921_s2: s2 {};
				pm8921_s3: s3 {};
				pm8921_s4: s4 {};
				pm8921_s7: s7 {};
				pm8921_s8: s8 {};

				pm8921_l1: l1 {};
				pm8921_l2: l2 {};
				pm8921_l3: l3 {};
				pm8921_l4: l4 {};
				pm8921_l5: l5 {};
				pm8921_l6: l6 {};
				pm8921_l7: l7 {};
				pm8921_l8: l8 {};
				pm8921_l9: l9 {};
				pm8921_l10: l10 {};
				pm8921_l11: l11 {};
				pm8921_l12: l12 {};
				pm8921_l14: l14 {};
				pm8921_l15: l15 {};
				pm8921_l16: l16 {};
				pm8921_l17: l17 {};
				pm8921_l18: l18 {};
				pm8921_l21: l21 {};
				pm8921_l22: l22 {};
				pm8921_l23: l23 {};
				pm8921_l24: l24 {};
				pm8921_l25: l25 {};
				pm8921_l26: l26 {};
				pm8921_l27: l27 {};
				pm8921_l28: l28 {};
				pm8921_l29: l29 {};

				pm8921_lvs1: lvs1 {};
				pm8921_lvs2: lvs2 {};
				pm8921_lvs3: lvs3 {};
				pm8921_lvs4: lvs4 {};
				pm8921_lvs5: lvs5 {};
				pm8921_lvs6: lvs6 {};
				pm8921_lvs7: lvs7 {};

				pm8921_usb_switch: usb-switch {};

				pm8921_hdmi_switch: hdmi-switch {
					bias-pull-down;
				};

				pm8921_ncp: ncp {};
			};
		};

		usb1: usb@12500000 {
			compatible = "qcom,ci-hdrc";
			reg = <0x12500000 0x200>,
			      <0x12500200 0x200>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
			clock-names = "core", "iface";
			assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
			assigned-clock-rates = <60000000>;
			resets = <&gcc USB_HS1_RESET>;
			reset-names = "core";
			phy_type = "ulpi";
			ahb-burst-config = <0>;
			phys = <&usb_hs1_phy>;
			phy-names = "usb-phy";
			status = "disabled";
			#reset-cells = <1>;

			ulpi {
				usb_hs1_phy: phy {
					compatible = "qcom,usb-hs-phy-apq8064",
						     "qcom,usb-hs-phy";
					clocks = <&sleep_clk>, <&cxo_board>;
					clock-names = "sleep", "ref";
					resets = <&usb1 0>;
					reset-names = "por";
					#phy-cells = <0>;
				};
			};
		};

		usb3: usb@12520000 {
			compatible = "qcom,ci-hdrc";
			reg = <0x12520000 0x200>,
			      <0x12520200 0x200>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
			clock-names = "core", "iface";
			assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
			assigned-clock-rates = <60000000>;
			resets = <&gcc USB_HS3_RESET>;
			reset-names = "core";
			phy_type = "ulpi";
			ahb-burst-config = <0>;
			phys = <&usb_hs3_phy>;
			phy-names = "usb-phy";
			status = "disabled";
			#reset-cells = <1>;

			ulpi {
				usb_hs3_phy: phy {
					compatible = "qcom,usb-hs-phy-apq8064",
						     "qcom,usb-hs-phy";
					#phy-cells = <0>;
					clocks = <&sleep_clk>, <&cxo_board>;
					clock-names = "sleep", "ref";
					resets = <&usb3 0>;
					reset-names = "por";
				};
			};
		};

		usb4: usb@12530000 {
			compatible = "qcom,ci-hdrc";
			reg = <0x12530000 0x200>,
			      <0x12530200 0x200>;
			interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
			clock-names = "core", "iface";
			assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
			assigned-clock-rates = <60000000>;
			resets = <&gcc USB_HS4_RESET>;
			reset-names = "core";
			phy_type = "ulpi";
			ahb-burst-config = <0>;
			phys = <&usb_hs4_phy>;
			phy-names = "usb-phy";
			status = "disabled";
			#reset-cells = <1>;

			ulpi {
				usb_hs4_phy: phy {
					compatible = "qcom,usb-hs-phy-apq8064",
						     "qcom,usb-hs-phy";
					#phy-cells = <0>;
					clocks = <&sleep_clk>, <&cxo_board>;
					clock-names = "sleep", "ref";
					resets = <&usb4 0>;
					reset-names = "por";
				};
			};
		};

		sata_phy0: phy@1b400000 {
			compatible = "qcom,apq8064-sata-phy";
			status = "disabled";
			reg = <0x1b400000 0x200>;
			reg-names = "phy_mem";
			clocks = <&gcc SATA_PHY_CFG_CLK>;
			clock-names = "cfg";
			#phy-cells = <0>;
		};

		sata0: sata@29000000 {
			compatible = "qcom,apq8064-ahci", "generic-ahci";
			status	 = "disabled";
			reg	 = <0x29000000 0x180>;
			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc SFAB_SATA_S_H_CLK>,
				 <&gcc SATA_H_CLK>,
				 <&gcc SATA_A_CLK>,
				 <&gcc SATA_RXOOB_CLK>,
				 <&gcc SATA_PMALIVE_CLK>;
			clock-names = "slave_iface",
				      "iface",
				      "bus",
				      "rxoob",
				      "core_pmalive";

			assigned-clocks = <&gcc SATA_RXOOB_CLK>,
					  <&gcc SATA_PMALIVE_CLK>;
			assigned-clock-rates = <100000000>, <100000000>;

			phys = <&sata_phy0>;
			phy-names = "sata-phy";
			ports-implemented = <0x1>;
		};

		sdcc3: mmc@12180000 {
			compatible = "arm,pl18x", "arm,primecell";
			arm,primecell-periphid = <0x00051180>;
			status = "disabled";
			reg = <0x12180000 0x2000>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
			clock-names = "mclk", "apb_pclk";
			bus-width = <4>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			max-frequency = <192000000>;
			no-1-8-v;
			dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
			dma-names = "tx", "rx";
		};

		sdcc3bam: dma-controller@12182000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12182000 0x8000>;
			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC3_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc4: mmc@121c0000 {
			compatible = "arm,pl18x", "arm,primecell";
			arm,primecell-periphid = <0x00051180>;
			status = "disabled";
			reg = <0x121c0000 0x2000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
			clock-names = "mclk", "apb_pclk";
			bus-width = <4>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			max-frequency = <48000000>;
			dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
			dma-names = "tx", "rx";
			pinctrl-names = "default";
			pinctrl-0 = <&sdc4_gpios>;
		};

		sdcc4bam: dma-controller@121c2000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x121c2000 0x8000>;
			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC4_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		sdcc1: mmc@12400000 {
			status = "disabled";
			compatible = "arm,pl18x", "arm,primecell";
			pinctrl-names = "default";
			pinctrl-0 = <&sdcc1_pins>;
			arm,primecell-periphid = <0x00051180>;
			reg = <0x12400000 0x2000>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
			clock-names = "mclk", "apb_pclk";
			bus-width = <8>;
			max-frequency = <96000000>;
			non-removable;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
			dma-names = "tx", "rx";
		};

		sdcc1bam: dma-controller@12402000{
			compatible = "qcom,bam-v1.3.0";
			reg = <0x12402000 0x8000>;
			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc SDC1_H_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-apq8064", "syscon";
			reg = <0x1a400000 0x100>;
		};

		gpu: adreno-3xx@4300000 {
			compatible = "qcom,adreno-320.2", "qcom,adreno";
			reg = <0x04300000 0x20000>;
			reg-names = "kgsl_3d0_reg_memory";
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "kgsl_3d0_irq";
			clock-names =
			    "core",
			    "iface",
			    "mem",
			    "mem_iface";
			clocks =
			    <&mmcc GFX3D_CLK>,
			    <&mmcc GFX3D_AHB_CLK>,
			    <&mmcc GFX3D_AXI_CLK>,
			    <&mmcc MMSS_IMEM_AHB_CLK>;

			iommus = <&gfx3d 0
				  &gfx3d 1
				  &gfx3d 2
				  &gfx3d 3
				  &gfx3d 4
				  &gfx3d 5
				  &gfx3d 6
				  &gfx3d 7
				  &gfx3d 8
				  &gfx3d 9
				  &gfx3d 10
				  &gfx3d 11
				  &gfx3d 12
				  &gfx3d 13
				  &gfx3d 14
				  &gfx3d 15
				  &gfx3d 16
				  &gfx3d 17
				  &gfx3d 18
				  &gfx3d 19
				  &gfx3d 20
				  &gfx3d 21
				  &gfx3d 22
				  &gfx3d 23
				  &gfx3d 24
				  &gfx3d 25
				  &gfx3d 26
				  &gfx3d 27
				  &gfx3d 28
				  &gfx3d 29
				  &gfx3d 30
				  &gfx3d 31
				  &gfx3d1 0
				  &gfx3d1 1
				  &gfx3d1 2
				  &gfx3d1 3
				  &gfx3d1 4
				  &gfx3d1 5
				  &gfx3d1 6
				  &gfx3d1 7
				  &gfx3d1 8
				  &gfx3d1 9
				  &gfx3d1 10
				  &gfx3d1 11
				  &gfx3d1 12
				  &gfx3d1 13
				  &gfx3d1 14
				  &gfx3d1 15
				  &gfx3d1 16
				  &gfx3d1 17
				  &gfx3d1 18
				  &gfx3d1 19
				  &gfx3d1 20
				  &gfx3d1 21
				  &gfx3d1 22
				  &gfx3d1 23
				  &gfx3d1 24
				  &gfx3d1 25
				  &gfx3d1 26
				  &gfx3d1 27
				  &gfx3d1 28
				  &gfx3d1 29
				  &gfx3d1 30
				  &gfx3d1 31>;

			operating-points-v2 = <&gpu_opp_table>;

			gpu_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-320000000 {
					opp-hz = /bits/ 64 <450000000>;
				};

				opp-27000000 {
					opp-hz = /bits/ 64 <27000000>;
				};
			};
		};

		mmss_sfpb: syscon@5700000 {
			compatible = "syscon";
			reg = <0x5700000 0x70>;
		};

		dsi0: dsi@4700000 {
			compatible = "qcom,mdss-dsi-ctrl";
			label = "MDSS DSI CTRL->0";
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x04700000 0x200>;
			reg-names = "dsi_ctrl";

			clocks = <&mmcc DSI_M_AHB_CLK>,
				<&mmcc DSI_S_AHB_CLK>,
				<&mmcc AMP_AHB_CLK>,
				<&mmcc DSI_CLK>,
				<&mmcc DSI1_BYTE_CLK>,
				<&mmcc DSI_PIXEL_CLK>,
				<&mmcc DSI1_ESC_CLK>;
			clock-names = "iface", "bus", "core_mmss",
					"src", "byte", "pixel",
					"core";

			assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
					<&mmcc DSI1_ESC_SRC>,
					<&mmcc DSI_SRC>,
					<&mmcc DSI_PIXEL_SRC>;
			assigned-clock-parents = <&dsi0_phy 0>,
						<&dsi0_phy 0>,
						<&dsi0_phy 1>,
						<&dsi0_phy 1>;
			syscon-sfpb = <&mmss_sfpb>;
			phys = <&dsi0_phy>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					dsi0_in: endpoint {
					};
				};

				port@1 {
					reg = <1>;
					dsi0_out: endpoint {
					};
				};
			};
		};

		dsi0_phy: phy@4700200 {
			compatible = "qcom,dsi-phy-28nm-8960";
			#clock-cells = <1>;
			#phy-cells = <0>;

			reg = <0x04700200 0x100>,
				<0x04700300 0x200>,
				<0x04700500 0x5c>;
			reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
			clock-names = "iface", "ref";
			clocks = <&mmcc DSI_M_AHB_CLK>,
				 <&pxo_board>;
			status = "disabled";
		};

		mdp_port0: iommu@7500000 {
			compatible = "qcom,apq8064-iommu";
			#iommu-cells = <1>;
			clock-names =
			    "smmu_pclk",
			    "iommu_clk";
			clocks =
			    <&mmcc SMMU_AHB_CLK>,
			    <&mmcc MDP_AXI_CLK>;
			reg = <0x07500000 0x100000>;
			interrupts =
			    <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
			    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ncb = <2>;
		};

		mdp_port1: iommu@7600000 {
			compatible = "qcom,apq8064-iommu";
			#iommu-cells = <1>;
			clock-names =
			    "smmu_pclk",
			    "iommu_clk";
			clocks =
			    <&mmcc SMMU_AHB_CLK>,
			    <&mmcc MDP_AXI_CLK>;
			reg = <0x07600000 0x100000>;
			interrupts =
			    <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
			    <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ncb = <2>;
		};

		gfx3d: iommu@7c00000 {
			compatible = "qcom,apq8064-iommu";
			#iommu-cells = <1>;
			clock-names =
			    "smmu_pclk",
			    "iommu_clk";
			clocks =
			    <&mmcc SMMU_AHB_CLK>,
			    <&mmcc GFX3D_AXI_CLK>;
			reg = <0x07c00000 0x100000>;
			interrupts =
			    <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
			    <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ncb = <3>;
		};

		gfx3d1: iommu@7d00000 {
			compatible = "qcom,apq8064-iommu";
			#iommu-cells = <1>;
			clock-names =
			    "smmu_pclk",
			    "iommu_clk";
			clocks =
			    <&mmcc SMMU_AHB_CLK>,
			    <&mmcc GFX3D_AXI_CLK>;
			reg = <0x07d00000 0x100000>;
			interrupts =
			    <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
			    <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ncb = <3>;
		};

		pcie: pci@1b500000 {
			compatible = "qcom,pcie-apq8064";
			reg = <0x1b500000 0x1000>,
			      <0x1b502000 0x80>,
			      <0x1b600000 0x100>,
			      <0x0ff00000 0x100000>;
			reg-names = "dbi", "elbi", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x81000000 0 0          0x0fe00000 0 0x00100000>, /* I/O */
				 <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
			clocks = <&gcc PCIE_A_CLK>,
				 <&gcc PCIE_H_CLK>,
				 <&gcc PCIE_PHY_REF_CLK>;
			clock-names = "core", "iface", "phy";
			resets = <&gcc PCIE_ACLK_RESET>,
				 <&gcc PCIE_HCLK_RESET>,
				 <&gcc PCIE_POR_RESET>,
				 <&gcc PCIE_PCI_RESET>,
				 <&gcc PCIE_PHY_RESET>;
			reset-names = "axi", "ahb", "por", "pci", "phy";
			status = "disabled";
		};

		hdmi: hdmi-tx@4a00000 {
			compatible = "qcom,hdmi-tx-8960";
			pinctrl-names = "default";
			pinctrl-0 = <&hdmi_pinctrl>;
			reg = <0x04a00000 0x2f0>;
			reg-names = "core_physical";
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mmcc HDMI_APP_CLK>,
				 <&mmcc HDMI_M_AHB_CLK>,
				 <&mmcc HDMI_S_AHB_CLK>;
			clock-names = "core",
				      "master_iface",
				      "slave_iface";

			phys = <&hdmi_phy>;

			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					hdmi_in: endpoint {
					};
				};

				port@1 {
					reg = <1>;
					hdmi_out: endpoint {
					};
				};
			};
		};

		hdmi_phy: phy@4a00400 {
			compatible = "qcom,hdmi-phy-8960";
			reg = <0x4a00400 0x60>,
			      <0x4a00500 0x100>;
			reg-names = "hdmi_phy",
				    "hdmi_pll";

			clocks = <&mmcc HDMI_S_AHB_CLK>;
			clock-names = "slave_iface";
			#phy-cells = <0>;

			status = "disabled";
		};

		mdp: mdp@5100000 {
			compatible = "qcom,mdp4";
			reg = <0x05100000 0xf0000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mmcc MDP_CLK>,
				 <&mmcc MDP_AHB_CLK>,
				 <&mmcc MDP_AXI_CLK>,
				 <&mmcc MDP_LUT_CLK>,
				 <&mmcc HDMI_TV_CLK>,
				 <&mmcc MDP_TV_CLK>;
			clock-names = "core_clk",
				      "iface_clk",
				      "bus_clk",
				      "lut_clk",
				      "hdmi_clk",
				      "tv_clk";

			iommus = <&mdp_port0 0
				  &mdp_port0 2
				  &mdp_port1 0
				  &mdp_port1 2>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					mdp_lvds_out: endpoint {
					};
				};

				port@1 {
					reg = <1>;
					mdp_dsi1_out: endpoint {
					};
				};

				port@2 {
					reg = <2>;
					mdp_dsi2_out: endpoint {
					};
				};

				port@3 {
					reg = <3>;
					mdp_dtv_out: endpoint {
					};
				};
			};
		};

		riva: riva-pil@3200800 {
			compatible = "qcom,riva-pil";

			reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
			reg-names = "ccu", "dxe", "pmu";

			interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal";

			memory-region = <&wcnss_mem>;

			vddcx-supply = <&pm8921_s3>;
			vddmx-supply = <&pm8921_l24>;
			vddpx-supply = <&pm8921_s4>;

			status = "disabled";

			iris {
				compatible = "qcom,wcn3660";

				clocks = <&cxo_board>;
				clock-names = "xo";

				vddxo-supply = <&pm8921_l4>;
				vddrfa-supply = <&pm8921_s2>;
				vddpa-supply = <&pm8921_l10>;
				vdddig-supply = <&pm8921_lvs2>;
			};

			smd-edge {
				interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;

				qcom,ipc = <&l2cc 8 25>;
				qcom,smd-edge = <6>;

				label = "riva";

				wcnss {
					compatible = "qcom,wcnss";
					qcom,smd-channels = "WCNSS_CTRL";

					qcom,mmio = <&riva>;

					bluetooth {
						compatible = "qcom,wcnss-bt";
					};

					wifi {
						compatible = "qcom,wcnss-wlan";

						interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
							     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
						interrupt-names = "tx", "rx";

						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
					};
				};
			};
		};

		etb@1a01000 {
			compatible = "arm,coresight-etb10", "arm,primecell";
			reg = <0x1a01000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					etb_in: endpoint {
						remote-endpoint = <&replicator_out0>;
					};
				};
			};
		};

		tpiu@1a03000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0x1a03000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					tpiu_in: endpoint {
						remote-endpoint = <&replicator_out1>;
					};
				};
			};
		};

		replicator {
			compatible = "arm,coresight-static-replicator";

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			out-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					replicator_out0: endpoint {
						remote-endpoint = <&etb_in>;
					};
				};
				port@1 {
					reg = <1>;
					replicator_out1: endpoint {
						remote-endpoint = <&tpiu_in>;
					};
				};
			};

			in-ports {
				port {
					replicator_in: endpoint {
						remote-endpoint = <&funnel_out>;
					};
				};
			};
		};

		funnel@1a04000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x1a04000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				/*
				 * Not described input ports:
				 * 2 - connected to STM component
				 * 3 - not-connected
				 * 6 - not-connected
				 * 7 - not-connected
				 */
				port@0 {
					reg = <0>;
					funnel_in0: endpoint {
						remote-endpoint = <&etm0_out>;
					};
				};
				port@1 {
					reg = <1>;
					funnel_in1: endpoint {
						remote-endpoint = <&etm1_out>;
					};
				};
				port@4 {
					reg = <4>;
					funnel_in4: endpoint {
						remote-endpoint = <&etm2_out>;
					};
				};
				port@5 {
					reg = <5>;
					funnel_in5: endpoint {
						remote-endpoint = <&etm3_out>;
					};
				};
			};

			out-ports {
				port {
					funnel_out: endpoint {
						remote-endpoint = <&replicator_in>;
					};
				};
			};
		};

		etm@1a1c000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x1a1c000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			cpu = <&CPU0>;

			out-ports {
				port {
					etm0_out: endpoint {
						remote-endpoint = <&funnel_in0>;
					};
				};
			};
		};

		etm@1a1d000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x1a1d000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			cpu = <&CPU1>;

			out-ports {
				port {
					etm1_out: endpoint {
						remote-endpoint = <&funnel_in1>;
					};
				};
			};
		};

		etm@1a1e000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x1a1e000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			cpu = <&CPU2>;

			out-ports {
				port {
					etm2_out: endpoint {
						remote-endpoint = <&funnel_in4>;
					};
				};
			};
		};

		etm@1a1f000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x1a1f000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			cpu = <&CPU3>;

			out-ports {
				port {
					etm3_out: endpoint {
						remote-endpoint = <&funnel_in5>;
					};
				};
			};
		};
	};
};
#include "qcom-apq8064-pins.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/gpio/gpio.h>
#include "qcom-msm8974.dtsi"
#include "qcom-pm8841.dtsi"
#include "qcom-pm8941.dtsi"

/ {
	model = "Qualcomm APQ8074 Dragonboard";
	compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";

	aliases {
		serial0 = &blsp1_uart2;
		usid0 = &pm8941_0;
		usid4 = &pm8841_0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&blsp1_uart2 {
	status = "okay";
};

&blsp2_i2c5 {
	status = "okay";
	clock-frequency = <200000>;

	eeprom: eeprom@52 {
		compatible = "atmel,24c128";
		reg = <0x52>;
		pagesize = <32>;
		read-only;
	};
};

&rpm_requests {
	regulators-0 {
		compatible = "qcom,rpm-pm8841-regulators";

		pm8841_s1: s1 {
			regulator-min-microvolt = <675000>;
			regulator-max-microvolt = <1050000>;
		};

		pm8841_s2: s2 {
			regulator-min-microvolt = <500000>;
			regulator-max-microvolt = <1050000>;
		};

		pm8841_s3: s3 {
			regulator-min-microvolt = <500000>;
			regulator-max-microvolt = <1050000>;
		};

		pm8841_s4: s4 {
			regulator-min-microvolt = <500000>;
			regulator-max-microvolt = <1050000>;
		};
	};

	regulators-1 {
		compatible = "qcom,rpm-pm8941-regulators";

		vdd_l1_l3-supply = <&pm8941_s1>;
		vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
		vdd_l4_l11-supply = <&pm8941_s1>;
		vdd_l5_l7-supply = <&pm8941_s2>;
		vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
		vin_5vs-supply = <&pm8941_5v>;

		pm8941_s1: s1 {
			regulator-min-microvolt = <1300000>;
			regulator-max-microvolt = <1300000>;
			regulator-always-on;
			regulator-boot-on;
		};

		pm8941_s2: s2 {
			regulator-min-microvolt = <2150000>;
			regulator-max-microvolt = <2150000>;
			regulator-boot-on;
		};

		pm8941_s3: s3 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
			regulator-boot-on;
		};

		pm8941_l1: l1 {
			regulator-min-microvolt = <1225000>;
			regulator-max-microvolt = <1225000>;
			regulator-always-on;
			regulator-boot-on;
		};

		pm8941_l2: l2 {
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
		};

		pm8941_l3: l3 {
			regulator-min-microvolt = <1225000>;
			regulator-max-microvolt = <1225000>;
		};

		pm8941_l4: l4 {
			regulator-min-microvolt = <1225000>;
			regulator-max-microvolt = <1225000>;
		};

		pm8941_l5: l5 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};

		pm8941_l6: l6 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-boot-on;
		};

		pm8941_l7: l7 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-boot-on;
		};

		pm8941_l8: l8 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};

		pm8941_l9: l9 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <2950000>;
		};

		pm8941_l10: l10 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
		};

		pm8941_l11: l11 {
			regulator-min-microvolt = <1300000>;
			regulator-max-microvolt = <1300000>;
		};

		pm8941_l12: l12 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
			regulator-boot-on;
		};

		pm8941_l13: l13 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <2950000>;
			regulator-boot-on;
		};

		pm8941_l14: l14 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};

		pm8941_l15: l15 {
			regulator-min-microvolt = <2050000>;
			regulator-max-microvolt = <2050000>;
		};

		pm8941_l16: l16 {
			regulator-min-microvolt = <2700000>;
			regulator-max-microvolt = <2700000>;
		};

		pm8941_l17: l17 {
			regulator-min-microvolt = <2700000>;
			regulator-max-microvolt = <2700000>;
		};

		pm8941_l18: l18 {
			regulator-min-microvolt = <2850000>;
			regulator-max-microvolt = <2850000>;
		};

		pm8941_l19: l19 {
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		pm8941_l20: l20 {
			regulator-min-microvolt = <2950000>;
			regulator-max-microvolt = <2950000>;
			regulator-system-load = <200000>;
			regulator-allow-set-load;
			regulator-boot-on;
		};

		pm8941_l21: l21 {
			regulator-min-microvolt = <2950000>;
			regulator-max-microvolt = <2950000>;
			regulator-boot-on;
		};

		pm8941_l22: l22 {
			regulator-min-microvolt = <3000000>;
			regulator-max-microvolt = <3000000>;
		};

		pm8941_l23: l23 {
			regulator-min-microvolt = <3000000>;
			regulator-max-microvolt = <3000000>;
		};

		pm8941_l24: l24 {
			regulator-min-microvolt = <3075000>;
			regulator-max-microvolt = <3075000>;
			regulator-boot-on;
		};
	};
};

&sdhc_1 {
	status = "okay";

	vmmc-supply = <&pm8941_l20>;
	vqmmc-supply = <&pm8941_s3>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc1_on>;
	pinctrl-1 = <&sdc1_off>;
};

&sdhc_2 {
	status = "okay";

	cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&pm8941_l21>;
	vqmmc-supply = <&pm8941_l13>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc2_on>;
	pinctrl-1 = <&sdc2_off>;
};

&tlmm {
	sdc1_on: sdc1-on-state {
		clk-pins {
			pins = "sdc1_clk";
			drive-strength = <16>;
			bias-disable;
		};

		cmd-data-pins {
			pins = "sdc1_cmd", "sdc1_data";
			drive-strength = <10>;
			bias-pull-up;
		};
	};

	sdc2_on: sdc2-on-state {
		clk-pins {
			pins = "sdc2_clk";
			drive-strength = <10>;
			bias-disable;
		};

		cmd-data-pins {
			pins = "sdc2_cmd", "sdc2_data";
			drive-strength = <6>;
			bias-pull-up;
		};

		cd-pins {
			pins = "gpio62";
			function = "gpio";
			drive-strength = <2>;
			bias-disable;
		};
	};
};

&usb {
	status = "okay";

	phys = <&usb_hs2_phy>;
	phy-select = <&tcsr 0xb000 1>;
	extcon = <&smbb>, <&usb_id>;
	vbus-supply = <&chg_otg>;
	hnp-disable;
	srp-disable;
	adp-disable;
};

&usb_hs2_phy {
	status = "okay";
	v3p3-supply = <&pm8941_l24>;
	v1p8-supply = <&pm8941_l6>;
	extcon = <&smbb>;
	qcom,init-seq = /bits/ 8 <0x1 0x63>;
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
#include "qcom-apq8084.dtsi"
#include "qcom-pma8084.dtsi"

/ {
	model = "Qualcomm APQ8084/IFC6540";
	compatible = "qcom,apq8084-sbc", "qcom,apq8084";

	aliases {
		serial0 = &blsp2_uart2;
		usid0 = &pma8084_0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	soc {
		serial@f995e000 {
			status = "okay";
		};

		sdhci@f9824900 {
			bus-width = <8>;
			non-removable;
			status = "okay";
		};

		sdhci@f98a4900 {
			cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
			bus-width = <4>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
#include "qcom-apq8084.dtsi"
#include "qcom-pma8084.dtsi"

/ {
	model = "Qualcomm APQ 8084-MTP";
	compatible = "qcom,apq8084-mtp", "qcom,apq8084";

	aliases {
		serial0 = &blsp2_uart2;
		usid0 = &pma8084_0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	soc {
		serial@f995e000 {
			status = "okay";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-apq8084.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm APQ 8084";
	compatible = "qcom,apq8084";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		smem_mem: smem_region@fa00000 {
			reg = <0xfa00000 0x200000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "qcom,krait";
			reg = <0>;
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "qcom,krait";
			reg = <1>;
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "qcom,krait";
			reg = <2>;
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "qcom,krait";
			reg = <3>;
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			qcom,saw = <&saw_l2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <150>;
				exit-latency-us = <200>;
				min-residency-us = <2000>;
			};
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	firmware {
		scm {
			compatible = "qcom,scm-apq8084", "qcom,scm";
			clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
			clock-names = "core", "bus", "iface";
		};
	};

	thermal-zones {
		cpu0-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 5>;

			trips {
				cpu_alert0: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu1-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 6>;

			trips {
				cpu_alert1: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit1: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu2-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 7>;

			trips {
				cpu_alert2: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit2: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu3-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 8>;

			trips {
				cpu_alert3: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit3: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <GIC_PPI 7 0xf04>;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 2 0xf08>,
			     <GIC_PPI 3 0xf08>,
			     <GIC_PPI 4 0xf08>,
			     <GIC_PPI 1 0xf08>;
		clock-frequency = <19200000>;
	};

	smem {
		compatible = "qcom,smem";

		qcom,rpm-msg-ram = <&rpm_msg_ram>;
		memory-region = <&smem_mem>;

		hwlocks = <&tcsr_mutex 3>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
		};

		apcs: syscon@f9011000 {
			compatible = "syscon";
			reg = <0xf9011000 0x1000>;
		};

		sram@fc190000 {
			compatible = "qcom,apq8084-rpm-stats";
			reg = <0xfc190000 0x10000>;
		};

		qfprom: qfprom@fc4bc000 {
			compatible = "qcom,apq8084-qfprom", "qcom,qfprom";
			reg = <0xfc4bc000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			tsens_calib: calib@d0 {
				reg = <0xd0 0x18>;
			};
			tsens_backup: backup@440 {
				reg = <0x440 0x10>;
			};
		};

		tsens: thermal-sensor@fc4a8000 {
			compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
			reg = <0xfc4a9000 0x1000>, /* TM */
			      <0xfc4a8000 0x1000>; /* SROT */
			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
			nvmem-cell-names = "calib", "calib_backup";
			#qcom,sensors = <11>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow";
			#thermal-sensor-cells = <1>;
		};
		timer@f9020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;
			clock-frequency = <19200000>;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		saw0: power-controller@f9089000 {
			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
		};

		saw1: power-controller@f9099000 {
			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
		};

		saw2: power-controller@f90a9000 {
			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw3: power-controller@f90b9000 {
			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw_l2: power-controller@f9012000 {
			compatible = "qcom,saw2";
			reg = <0xf9012000 0x1000>;
			regulator;
		};

		acc0: clock-controller@f9088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9088000 0x1000>,
			      <0xf9008000 0x1000>;
		};

		acc1: clock-controller@f9098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9098000 0x1000>,
			      <0xf9008000 0x1000>;
		};

		acc2: clock-controller@f90a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90a8000 0x1000>,
			      <0xf9008000 0x1000>;
		};

		acc3: clock-controller@f90b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90b8000 0x1000>,
			      <0xf9008000 0x1000>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-apq8084";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfc400000 0x4000>;
		};

		tcsr_mutex: hwlock@fd484000 {
			compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex";
			reg = <0xfd484000 0x1000>;
			#hwlock-cells = <1>;
		};

		rpm_msg_ram: sram@fc428000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0xfc428000 0x4000>;
		};

		tlmm: pinctrl@fd510000 {
			compatible = "qcom,apq8084-pinctrl";
			reg = <0xfd510000 0x4000>;
			gpio-controller;
			gpio-ranges = <&tlmm 0 0 147>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		};

		blsp2_uart2: serial@f995e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf995e000 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		mmc@f9824900 {
			compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc", "core";
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
				 <&gcc GCC_SDCC1_APPS_CLK>,
				 <&xo_board>;
			clock-names = "iface", "core", "xo";
			status = "disabled";
		};

		mmc@f98a4900 {
			compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc", "core";
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				 <&gcc GCC_SDCC2_APPS_CLK>,
				 <&xo_board>;
			clock-names = "iface", "core", "xo";
			status = "disabled";
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};
	};

	smd {
		compatible = "qcom,smd";

		rpm {
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			rpm-requests {
				compatible = "qcom,rpm-apq8084";
				qcom,smd-channels = "rpm_requests";

				regulators-0 {
					compatible = "qcom,rpm-pma8084-regulators";

					pma8084_s1: s1 {};
					pma8084_s2: s2 {};
					pma8084_s3: s3 {};
					pma8084_s4: s4 {};
					pma8084_s5: s5 {};
					pma8084_s6: s6 {};
					pma8084_s7: s7 {};
					pma8084_s8: s8 {};
					pma8084_s9: s9 {};
					pma8084_s10: s10 {};
					pma8084_s11: s11 {};
					pma8084_s12: s12 {};

					pma8084_l1: l1 {};
					pma8084_l2: l2 {};
					pma8084_l3: l3 {};
					pma8084_l4: l4 {};
					pma8084_l5: l5 {};
					pma8084_l6: l6 {};
					pma8084_l7: l7 {};
					pma8084_l8: l8 {};
					pma8084_l9: l9 {};
					pma8084_l10: l10 {};
					pma8084_l11: l11 {};
					pma8084_l12: l12 {};
					pma8084_l13: l13 {};
					pma8084_l14: l14 {};
					pma8084_l15: l15 {};
					pma8084_l16: l16 {};
					pma8084_l17: l17 {};
					pma8084_l18: l18 {};
					pma8084_l19: l19 {};
					pma8084_l20: l20 {};
					pma8084_l21: l21 {};
					pma8084_l22: l22 {};
					pma8084_l23: l23 {};
					pma8084_l24: l24 {};
					pma8084_l25: l25 {};
					pma8084_l26: l26 {};
					pma8084_l27: l27 {};

					pma8084_lvs1: lvs1 {};
					pma8084_lvs2: lvs2 {};
					pma8084_lvs3: lvs3 {};
					pma8084_lvs4: lvs4 {};

					pma8084_5vs1: 5vs1 {};
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include <dt-bindings/leds/common.h>
#include "qcom-ipq4018-ap120c-ac.dtsi"

/ {
	model = "ALFA Network AP120C-AC Bit";

	leds {
		compatible = "gpio-leds";

		led-power {
			label = "ap120c-ac:green:power";
			function = LED_FUNCTION_POWER;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};

		led-wlan {
			label = "ap120c-ac:green:wlan";
			function = LED_FUNCTION_WLAN;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
		};

		led-support {
			label = "ap120c-ac:green:support";
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
			panic-indicator;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include <dt-bindings/leds/common.h>
#include "qcom-ipq4018-ap120c-ac.dtsi"

/ {
	leds {
		compatible = "gpio-leds";

		status: led-status {
			label = "ap120c-ac:blue:status";
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_BLUE>;
			gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
			default-state = "keep";
		};

		led-wlan2g {
			label = "ap120c-ac:green:wlan2g";
			function = LED_FUNCTION_WLAN;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "phy0tpt";
		};

		led-wlan5g {
			label = "ap120c-ac:red:wlan5g";
			function = LED_FUNCTION_WLAN;
			color = <LED_COLOR_ID_RED>;
			gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "phy1tpt";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "ALFA Network AP120C-AC";
	compatible = "alfa-network,ap120c-ac", "qcom,ipq4018";

	keys {
		compatible = "gpio-keys";

		key-reset {
			label = "reset";
			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	};
};

&tlmm {
	i2c0_pins: i2c0_pinmux {
		mux_i2c {
			function = "blsp_i2c0";
			pins = "gpio58", "gpio59";
			drive-strength = <16>;
			bias-disable;
		};
	};

	mdio_pins: mdio_pinmux {
		mux_mdio {
			pins = "gpio53";
			function = "mdio";
			bias-pull-up;
		};

		mux_mdc {
			pins = "gpio52";
			function = "mdc";
			bias-pull-up;
		};
	};

	serial0_pins: serial0_pinmux {
		mux_uart {
			pins = "gpio60", "gpio61";
			function = "blsp_uart0";
			bias-disable;
		};
	};

	spi0_pins: spi0_pinmux {
		mux_spi {
			function = "blsp_spi0";
			pins = "gpio55", "gpio56", "gpio57";
			drive-strength = <12>;
			bias-disable;
		};

		mux_cs {
			function = "gpio";
			pins = "gpio54", "gpio4";
			drive-strength = <2>;
			bias-disable;
			output-high;
		};
	};

	usb-power {
		line-name = "USB-power";
		gpios = <1 GPIO_ACTIVE_HIGH>;
		gpio-hog;
		output-high;
	};
};

&watchdog {
	status = "okay";
};

&prng {
	status = "okay";
};

&blsp_dma {
	status = "okay";
};

&blsp1_i2c3 {
	status = "okay";

	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";

	tpm@29 {
		compatible = "atmel,at97sc3204t";
		reg = <0x29>;
	};
};

&blsp1_spi1 {
	status = "okay";

	pinctrl-0 = <&spi0_pins>;
	pinctrl-names = "default";
	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <24000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "SBL1";
				reg = <0x00000000 0x00040000>;
				read-only;
			};

			partition@40000 {
				label = "MIBIB";
				reg = <0x00040000 0x00020000>;
				read-only;
			};

			partition@60000 {
				label = "QSEE";
				reg = <0x00060000 0x00060000>;
				read-only;
			};

			partition@c0000 {
				label = "CDT";
				reg = <0x000c0000 0x00010000>;
				read-only;
			};

			partition@d0000 {
				label = "DDRPARAMS";
				reg = <0x000d0000 0x00010000>;
				read-only;
			};

			partition@e0000 {
				label = "u-boot-env";
				reg = <0x000e0000 0x00010000>;
			};

			partition@f0000 {
				label = "u-boot";
				reg = <0x000f0000 0x00080000>;
				read-only;
			};

			partition@170000 {
				label = "ART";
				reg = <0x00170000 0x00010000>;
				read-only;
			};

			partition@180000 {
				label = "priv_data1";
				reg = <0x00180000 0x00010000>;
				read-only;
			};

			partition@190000 {
				label = "priv_data2";
				reg = <0x00190000 0x00010000>;
				read-only;
			};
		};
	};

	nand@1 {
		compatible = "spi-nand";
		reg = <1>;
		spi-max-frequency = <40000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "ubi1";
				reg = <0x00000000 0x04000000>;
			};

			partition@4000000 {
				label = "ubi2";
				reg = <0x04000000 0x04000000>;
			};
		};
	};
};

&blsp1_uart1 {
	status = "okay";

	pinctrl-0 = <&serial0_pins>;
	pinctrl-names = "default";
};

&cryptobam {
	status = "okay";
};

&crypto {
	status = "okay";
};

&mdio {
	status = "okay";

	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";
};

&wifi0 {
	status = "okay";
};

&wifi1 {
	status = "okay";
	qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
};

&usb3_hs_phy {
	status = "okay";
};

&usb3 {
	status = "okay";

	dwc3@8a00000 {
		phys = <&usb3_hs_phy>;
		phy-names = "usb2-phy";
	};
};

&usb2_hs_phy {
	status = "okay";
};

&usb2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>

#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "8devices Jalapeno";
	compatible = "8dev,jalapeno", "qcom,ipq4018";
};

&tlmm {
	mdio_pins: mdio_pinmux {
		pinmux_1 {
			pins = "gpio53";
			function = "mdio";
		};

		pinmux_2 {
			pins = "gpio52";
			function = "mdc";
		};

		pinconf {
			pins = "gpio52", "gpio53";
			bias-pull-up;
		};
	};

	serial_pins: serial_pinmux {
		mux {
			pins = "gpio60", "gpio61";
			function = "blsp_uart0";
			bias-disable;
		};
	};

	spi_0_pins: spi_0_pinmux {
		pin {
			function = "blsp_spi0";
			pins = "gpio55", "gpio56", "gpio57";
			drive-strength = <2>;
			bias-disable;
		};

		pin_cs {
			function = "gpio";
			pins = "gpio54", "gpio59";
			drive-strength = <2>;
			bias-disable;
			output-high;
		};
	};
};

&watchdog {
	status = "okay";
};

&prng {
	status = "okay";
};

&blsp_dma {
	status = "okay";
};

&blsp1_spi1 {
	status = "okay";

	pinctrl-0 = <&spi_0_pins>;
	pinctrl-names = "default";
	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;

	flash@0 {
		status = "okay";

		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <24000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "SBL1";
				reg = <0x00000000 0x00040000>;
				read-only;
			};

			partition@40000 {
				label = "MIBIB";
				reg = <0x00040000 0x00020000>;
				read-only;
			};

			partition@60000 {
				label = "QSEE";
				reg = <0x00060000 0x00060000>;
				read-only;
			};

			partition@c0000 {
				label = "CDT";
				reg = <0x000c0000 0x00010000>;
				read-only;
			};

			partition@d0000 {
				label = "DDRPARAMS";
				reg = <0x000d0000 0x00010000>;
				read-only;
			};

			partition@e0000 {
				label = "u-boot-env";
				reg = <0x000e0000 0x00010000>;
			};

			partition@f0000 {
				label = "u-boot";
				reg = <0x000f0000 0x00080000>;
				read-only;
			};

			partition@170000 {
				label = "ART";
				reg = <0x00170000 0x00010000>;
				read-only;
			};
		};
	};

	spi-nand@1 {
		status = "okay";

		compatible = "spi-nand";
		reg = <1>;
		spi-max-frequency = <24000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "ubi1";
				reg = <0x00000000 0x04000000>;
			};

			partition@4000000 {
				label = "ubi2";
				reg = <0x04000000 0x04000000>;
			};
		};
	};
};

&blsp1_uart1 {
	status = "okay";

	pinctrl-0 = <&serial_pins>;
	pinctrl-names = "default";
};

&cryptobam {
	status = "okay";
};

&crypto {
	status = "okay";
};

&mdio {
	status = "okay";

	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";
};

&wifi0 {
	status = "okay";

	qcom,ath10k-calibration-variant = "8devices-Jalapeno";
};

&wifi1 {
	status = "okay";

	qcom,ath10k-calibration-variant = "8devices-Jalapeno";
};

&usb3_ss_phy {
	status = "okay";
};

&usb3_hs_phy {
	status = "okay";
};

&usb3 {
	status = "okay";
};

&usb2_hs_phy {
	status = "okay";
};

&usb2 {
	status = "okay";
};


code:
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "qcom-ipq4019-ap.dk01.1.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
	compatible = "qcom,ipq4019-ap-dk01.1-c1", "qcom,ipq4019";
};


code:
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include <dt-bindings/gpio/gpio.h>
#include "qcom-ipq4019.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";

	aliases {
		serial0 = &blsp1_uart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	soc {
		rng@22000 {
			status = "okay";
		};

		pinctrl@1000000 {
			serial_pins: serial_pinmux {
				mux {
					pins = "gpio60", "gpio61";
					function = "blsp_uart0";
					bias-disable;
				};
			};

			spi_0_pins: spi_0_pinmux {
				pinmux {
					function = "blsp_spi0";
					pins = "gpio55", "gpio56", "gpio57";
				};
				pinmux_cs {
					function = "gpio";
					pins = "gpio54";
				};
				pinconf {
					pins = "gpio55", "gpio56", "gpio57";
					drive-strength = <12>;
					bias-disable;
				};
				pinconf_cs {
					pins = "gpio54";
					drive-strength = <2>;
					bias-disable;
					output-high;
				};
			};
		};

		blsp_dma: dma-controller@7884000 {
			status = "okay";
		};

		spi@78b5000 {
			pinctrl-0 = <&spi_0_pins>;
			pinctrl-names = "default";
			status = "okay";
			cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;

			mx25l25635e@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0>;
				compatible = "mx25l25635e";
				spi-max-frequency = <24000000>;
			};
		};

		serial@78af000 {
			pinctrl-0 = <&serial_pins>;
			pinctrl-names = "default";
			status = "okay";
		};

		cryptobam: dma-controller@8e04000 {
			status = "okay";
		};

		crypto@8e3a000 {
			status = "okay";
		};

		watchdog@b017000 {
			status = "okay";
		};

		wifi@a000000 {
			status = "okay";
		};

		wifi@a800000 {
			status = "okay";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.

#include "qcom-ipq4019-ap.dk04.1.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
	compatible = "qcom,ipq4019-dk04.1-c1", "qcom,ipq4019";

	soc {
		dma-controller@7984000 {
			status = "okay";
		};

		qpic-nand@79b0000 {
			status = "okay";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.

#include "qcom-ipq4019-ap.dk04.1.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
	compatible = "qcom,ipq4019-ap-dk04.1-c3", "qcom,ipq4019";
};


code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.

#include "qcom-ipq4019.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";

	aliases {
		serial0 = &blsp1_uart1;
		serial1 = &blsp1_uart2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x10000000>; /* 256MB */
	};

	soc {
		pinctrl@1000000 {
			serial_0_pins: serial0-pinmux {
				pins = "gpio16", "gpio17";
				function = "blsp_uart0";
				bias-disable;
			};

			serial_1_pins: serial1-pinmux {
				pins = "gpio8", "gpio9",
					"gpio10", "gpio11";
				function = "blsp_uart1";
				bias-disable;
			};

			spi_0_pins: spi-0-pinmux {
				pinmux {
					function = "blsp_spi0";
					pins = "gpio13", "gpio14", "gpio15";
					bias-disable;
				};
				pinmux_cs {
					function = "gpio";
					pins = "gpio12";
					bias-disable;
					output-high;
				};
			};

			i2c_0_pins: i2c-0-pinmux {
				pins = "gpio20", "gpio21";
				function = "blsp_i2c0";
				bias-disable;
			};

			nand_pins: nand-pins {
				pins = "gpio53", "gpio55", "gpio56",
					"gpio57", "gpio58", "gpio59",
					"gpio60", "gpio62", "gpio63",
					"gpio64", "gpio65", "gpio66",
					"gpio67", "gpio68", "gpio69";
				function = "qpic";
			};
		};

		serial@78af000 {
			pinctrl-0 = <&serial_0_pins>;
			pinctrl-names = "default";
			status = "okay";
		};

		serial@78b0000 {
			pinctrl-0 = <&serial_1_pins>;
			pinctrl-names = "default";
			status = "okay";
		};

		dma-controller@7884000 {
			status = "okay";
		};

		spi@78b5000 { /* BLSP1 QUP1 */
			pinctrl-0 = <&spi_0_pins>;
			pinctrl-names = "default";
			status = "okay";
			cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;

			flash@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0>;
				compatible = "micron,n25q128a11", "jedec,spi-nor";
				spi-max-frequency = <24000000>;
			};
		};

		pci@40000000 {
			status = "okay";
			perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
		};

		qpic-nand@79b0000 {
			pinctrl-0 = <&nand_pins>;
			pinctrl-names = "default";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.

#include <dt-bindings/gpio/gpio.h>
#include "qcom-ipq4019-ap.dk07.1.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C1";
	compatible = "qcom,ipq4019-ap-dk07.1-c1", "qcom,ipq4019";

	soc {
		pci@40000000 {
			status = "okay";
			perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
		};

		spi@78b6000 {
			status = "okay";
		};

		pinctrl@1000000 {
			serial_1_pins: serial1-pinmux {
				pins = "gpio8", "gpio9",
					"gpio10", "gpio11";
				function = "blsp_uart1";
				bias-disable;
			};

			spi_0_pins: spi-0-pinmux {
				pinmux {
					function = "blsp_spi0";
					pins = "gpio13", "gpio14", "gpio15";
					bias-disable;
				};
				pinmux_cs {
					function = "gpio";
					pins = "gpio12";
					bias-disable;
					output-high;
				};
			};
		};

		serial@78b0000 {
			pinctrl-0 = <&serial_1_pins>;
			pinctrl-names = "default";
			status = "okay";
		};

		spi@78b5000 {
			pinctrl-0 = <&spi_0_pins>;
			pinctrl-names = "default";
			status = "okay";
			cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;

			flash@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0>;
				compatible = "micron,n25q128a11", "jedec,spi-nor";
				spi-max-frequency = <24000000>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.

#include "qcom-ipq4019-ap.dk07.1.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
	compatible = "qcom,ipq4019-ap-dk07.1-c2", "qcom,ipq4019";

	soc {
		pinctrl@1000000 {
			serial_1_pins: serial1-pinmux {
				pins = "gpio8", "gpio9";
				function = "blsp_uart1";
				bias-disable;
			};
		};

		serial@78b0000 {
			pinctrl-0 = <&serial_1_pins>;
			pinctrl-names = "default";
			status = "okay";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, The Linux Foundation. All rights reserved.

#include "qcom-ipq4019.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";

	memory {
		device_type = "memory";
		reg = <0x80000000 0x20000000>; /* 512MB */
	};

	aliases {
		serial0 = &blsp1_uart1;
		serial1 = &blsp1_uart2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	soc {
		pinctrl@1000000 {
			serial_0_pins: serial0-pinmux {
				pins = "gpio16", "gpio17";
				function = "blsp_uart0";
				bias-disable;
			};

			i2c_0_pins: i2c-0-pinmux {
				pins = "gpio20", "gpio21";
				function = "blsp_i2c0";
				bias-disable;
			};

			nand_pins: nand-pins {
				pins = "gpio53", "gpio55", "gpio56",
				       "gpio57", "gpio58", "gpio59",
				       "gpio60", "gpio62", "gpio63",
				       "gpio64", "gpio65", "gpio66",
				       "gpio67", "gpio68", "gpio69";
				function = "qpic";
                        };
		};

		serial@78af000 {
			pinctrl-0 = <&serial_0_pins>;
			pinctrl-names = "default";
			status = "okay";
		};

		dma-controller@7884000 {
			status = "okay";
		};

		i2c@78b7000 { /* BLSP1 QUP2 */
			pinctrl-0 = <&i2c_0_pins>;
			pinctrl-names = "default";
			status = "okay";
		};

		dma-controller@7984000 {
			status = "okay";
		};

		qpic-nand@79b0000 {
			pinctrl-0 = <&nand_pins>;
			pinctrl-names = "default";
			status = "okay";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 */

/dts-v1/;

#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	model = "Qualcomm Technologies, Inc. IPQ4019";
	compatible = "qcom,ipq4019";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges;

		smem_region: smem@87e00000 {
			reg = <0x87e00000 0x080000>;
			no-map;
		};

		tz@87e80000 {
			reg = <0x87e80000 0x180000>;
			no-map;
		};
	};

	aliases {
		spi0 = &blsp1_spi1;
		spi1 = &blsp1_spi2;
		i2c0 = &blsp1_i2c3;
		i2c1 = &blsp1_i2c4;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			reg = <0x0>;
			clocks = <&gcc GCC_APPS_CLK_SRC>;
			clock-frequency = <0>;
			clock-latency = <256000>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			reg = <0x1>;
			clocks = <&gcc GCC_APPS_CLK_SRC>;
			clock-frequency = <0>;
			clock-latency = <256000>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			reg = <0x2>;
			clocks = <&gcc GCC_APPS_CLK_SRC>;
			clock-frequency = <0>;
			clock-latency = <256000>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			reg = <0x3>;
			clocks = <&gcc GCC_APPS_CLK_SRC>;
			clock-frequency = <0>;
			clock-latency = <256000>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			qcom,saw = <&saw_l2>;
		};
	};

	cpu0_opp_table: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-48000000 {
			opp-hz = /bits/ 64 <48000000>;
			clock-latency-ns = <256000>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			clock-latency-ns = <256000>;
		};
		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <256000>;
		};
		opp-716000000 {
			opp-hz = /bits/ 64 <716000000>;
			clock-latency-ns = <256000>;
 		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
					 IRQ_TYPE_LEVEL_HIGH)>;
	};

	clocks {
		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "gcc_sleep_clk_src";
			#clock-cells = <0>;
		};

		xo: xo {
			compatible = "fixed-clock";
			clock-frequency = <48000000>;
			#clock-cells = <0>;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-ipq4019", "qcom,scm";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 4 0xf08>,
			     <1 1 0xf08>;
		clock-frequency = <48000000>;
		always-on;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x0b000000 0x1000>,
			<0x0b002000 0x1000>;
		};

		gcc: clock-controller@1800000 {
			compatible = "qcom,gcc-ipq4019";
			#clock-cells = <1>;
			#power-domain-cells = <1>;
			#reset-cells = <1>;
			reg = <0x1800000 0x60000>;
		};

		prng: rng@22000 {
			compatible = "qcom,prng";
			reg = <0x22000 0x140>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
			status = "disabled";
		};

		tlmm: pinctrl@1000000 {
			compatible = "qcom,ipq4019-pinctrl";
			reg = <0x01000000 0x300000>;
			gpio-controller;
			gpio-ranges = <&tlmm 0 0 100>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		};

		vqmmc: regulator@1948000 {
			compatible = "qcom,vqmmc-ipq4019-regulator";
			reg = <0x01948000 0x4>;
			regulator-name = "vqmmc";
			regulator-min-microvolt = <1500000>;
			regulator-max-microvolt = <3000000>;
			regulator-always-on;
			status = "disabled";
		};

		sdhci: mmc@7824900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x7824900 0x11c>, <0x7824000 0x800>;
			reg-names = "hc", "core";
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			bus-width = <8>;
			clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>,
				 <&gcc GCC_DCD_XO_CLK>;
			clock-names = "iface", "core", "xo";
			status = "disabled";
		};

		blsp_dma: dma-controller@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x23000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x78b5000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x78b6000 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp_dma 6>, <&blsp_dma 7>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b7000 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp_dma 8>, <&blsp_dma 9>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b8000 0x600>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp_dma 10>, <&blsp_dma 11>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		cryptobam: dma-controller@8e04000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x08e04000 0x20000>;
			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <1>;
			qcom,controlled-remotely;
			status = "disabled";
		};

		crypto: crypto@8e3a000 {
			compatible = "qcom,crypto-v5.1";
			reg = <0x08e3a000 0x6000>;
			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
				 <&gcc GCC_CRYPTO_AXI_CLK>,
				 <&gcc GCC_CRYPTO_CLK>;
			clock-names = "iface", "bus", "core";
			dmas = <&cryptobam 2>, <&cryptobam 3>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		acc0: clock-controller@b088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
		};

		acc1: clock-controller@b098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
		};

		acc2: clock-controller@b0a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
		};

		acc3: clock-controller@b0b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
		};

		saw0: regulator@b089000 {
			compatible = "qcom,saw2";
			reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
			regulator;
		};

		saw1: regulator@b099000 {
			compatible = "qcom,saw2";
			reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
			regulator;
		};

		saw2: regulator@b0a9000 {
			compatible = "qcom,saw2";
			reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
			regulator;
		};

		saw3: regulator@b0b9000 {
			compatible = "qcom,saw2";
			reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
			regulator;
		};

		saw_l2: regulator@b012000 {
			compatible = "qcom,saw2";
			reg = <0xb012000 0x1000>;
			regulator;
		};

		blsp1_uart1: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 0>, <&blsp_dma 1>;
			dma-names = "tx", "rx";
		};

		blsp1_uart2: serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78b0000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 2>, <&blsp_dma 3>;
			dma-names = "tx", "rx";
		};

		watchdog: watchdog@b017000 {
			compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
			reg = <0xb017000 0x40>;
			clocks = <&sleep_clk>;
			timeout-sec = <10>;
			status = "disabled";
		};

		restart@4ab000 {
			compatible = "qcom,pshold";
			reg = <0x4ab000 0x4>;
		};

		pcie0: pci@40000000 {
			compatible = "qcom,pcie-ipq4019";
			reg =  <0x40000000 0xf1d
				0x40000f20 0xa8
				0x80000 0x2000
				0x40100000 0x1000>;
			reg-names = "dbi", "elbi", "parf", "config";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
				 <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;

			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
			clocks = <&gcc GCC_PCIE_AHB_CLK>,
				 <&gcc GCC_PCIE_AXI_M_CLK>,
				 <&gcc GCC_PCIE_AXI_S_CLK>;
			clock-names = "aux",
				      "master_bus",
				      "slave_bus";

			resets = <&gcc PCIE_AXI_M_ARES>,
				 <&gcc PCIE_AXI_S_ARES>,
				 <&gcc PCIE_PIPE_ARES>,
				 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
				 <&gcc PCIE_AXI_S_XPU_ARES>,
				 <&gcc PCIE_PARF_XPU_ARES>,
				 <&gcc PCIE_PHY_ARES>,
				 <&gcc PCIE_AXI_M_STICKY_ARES>,
				 <&gcc PCIE_PIPE_STICKY_ARES>,
				 <&gcc PCIE_PWR_ARES>,
				 <&gcc PCIE_AHB_ARES>,
				 <&gcc PCIE_PHY_AHB_ARES>;
			reset-names = "axi_m",
				      "axi_s",
				      "pipe",
				      "axi_m_vmid",
				      "axi_s_xpu",
				      "parf",
				      "phy",
				      "axi_m_sticky",
				      "pipe_sticky",
				      "pwr",
				      "ahb",
				      "phy_ahb";

			status = "disabled";
		};

		qpic_bam: dma-controller@7984000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x7984000 0x1a000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_QPIC_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		nand: nand-controller@79b0000 {
			compatible = "qcom,ipq4019-nand";
			reg = <0x79b0000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&gcc GCC_QPIC_CLK>,
				 <&gcc GCC_QPIC_AHB_CLK>;
			clock-names = "core", "aon";

			dmas = <&qpic_bam 0>,
			       <&qpic_bam 1>,
			       <&qpic_bam 2>;
			dma-names = "tx", "rx", "cmd";
			status = "disabled";

			nand@0 {
				reg = <0>;

				nand-ecc-strength = <4>;
				nand-ecc-step-size = <512>;
				nand-bus-width = <8>;
			};
		};

		wifi0: wifi@a000000 {
			compatible = "qcom,ipq4019-wifi";
			reg = <0xa000000 0x200000>;
			resets = <&gcc WIFI0_CPU_INIT_RESET>,
				 <&gcc WIFI0_RADIO_SRIF_RESET>,
				 <&gcc WIFI0_RADIO_WARM_RESET>,
				 <&gcc WIFI0_RADIO_COLD_RESET>,
				 <&gcc WIFI0_CORE_WARM_RESET>,
				 <&gcc WIFI0_CORE_COLD_RESET>;
			reset-names = "wifi_cpu_init", "wifi_radio_srif",
				      "wifi_radio_warm", "wifi_radio_cold",
				      "wifi_core_warm", "wifi_core_cold";
			clocks = <&gcc GCC_WCSS2G_CLK>,
				 <&gcc GCC_WCSS2G_REF_CLK>,
				 <&gcc GCC_WCSS2G_RTC_CLK>;
			clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
				      "wifi_wcss_rtc";
			interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
					   "msi4",  "msi5",  "msi6",  "msi7",
					   "msi8",  "msi9", "msi10", "msi11",
					  "msi12", "msi13", "msi14", "msi15",
					  "legacy";
			status = "disabled";
		};

		wifi1: wifi@a800000 {
			compatible = "qcom,ipq4019-wifi";
			reg = <0xa800000 0x200000>;
			resets = <&gcc WIFI1_CPU_INIT_RESET>,
				 <&gcc WIFI1_RADIO_SRIF_RESET>,
				 <&gcc WIFI1_RADIO_WARM_RESET>,
				 <&gcc WIFI1_RADIO_COLD_RESET>,
				 <&gcc WIFI1_CORE_WARM_RESET>,
				 <&gcc WIFI1_CORE_COLD_RESET>;
			reset-names = "wifi_cpu_init", "wifi_radio_srif",
				      "wifi_radio_warm", "wifi_radio_cold",
				      "wifi_core_warm", "wifi_core_cold";
			clocks = <&gcc GCC_WCSS5G_CLK>,
				 <&gcc GCC_WCSS5G_REF_CLK>,
				 <&gcc GCC_WCSS5G_RTC_CLK>;
			clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
				      "wifi_wcss_rtc";
			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names =  "msi0",  "msi1",  "msi2",  "msi3",
					   "msi4",  "msi5",  "msi6",  "msi7",
					   "msi8",  "msi9", "msi10", "msi11",
					  "msi12", "msi13", "msi14", "msi15",
					  "legacy";
			status = "disabled";
		};

		mdio: mdio@90000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "qcom,ipq4019-mdio";
			reg = <0x90000 0x64>;
			status = "disabled";

			ethphy0: ethernet-phy@0 {
				reg = <0>;
			};

			ethphy1: ethernet-phy@1 {
				reg = <1>;
			};

			ethphy2: ethernet-phy@2 {
				reg = <2>;
			};

			ethphy3: ethernet-phy@3 {
				reg = <3>;
			};

			ethphy4: ethernet-phy@4 {
				reg = <4>;
			};
		};

		usb3_ss_phy: ssphy@9a000 {
			compatible = "qcom,usb-ss-ipq4019-phy";
			#phy-cells = <0>;
			reg = <0x9a000 0x800>;
			reg-names = "phy_base";
			resets = <&gcc USB3_UNIPHY_PHY_ARES>;
			reset-names = "por_rst";
			status = "disabled";
		};

		usb3_hs_phy: hsphy@a6000 {
			compatible = "qcom,usb-hs-ipq4019-phy";
			#phy-cells = <0>;
			reg = <0xa6000 0x40>;
			reg-names = "phy_base";
			resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
			reset-names = "por_rst", "srif_rst";
			status = "disabled";
		};

		usb3: usb3@8af8800 {
			compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
			reg = <0x8af8800 0x100>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&gcc GCC_USB3_MASTER_CLK>,
				 <&gcc GCC_USB3_SLEEP_CLK>,
				 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
			clock-names = "core", "sleep", "mock_utmi";
			ranges;
			status = "disabled";

			dwc3@8a00000 {
				compatible = "snps,dwc3";
				reg = <0x8a00000 0xf8000>;
				interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
				phy-names = "usb2-phy", "usb3-phy";
				dr_mode = "host";
			};
		};

		usb2_hs_phy: hsphy@a8000 {
			compatible = "qcom,usb-hs-ipq4019-phy";
			#phy-cells = <0>;
			reg = <0xa8000 0x40>;
			reg-names = "phy_base";
			resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
			reset-names = "por_rst", "srif_rst";
			status = "disabled";
		};

		usb2: usb2@60f8800 {
			compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
			reg = <0x60f8800 0x100>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&gcc GCC_USB2_MASTER_CLK>,
				 <&gcc GCC_USB2_SLEEP_CLK>,
				 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
			clock-names = "master", "sleep", "mock_utmi";
			ranges;
			status = "disabled";

			dwc3@6000000 {
				compatible = "snps,dwc3";
				reg = <0x6000000 0xf8000>;
				interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usb2_hs_phy>;
				phy-names = "usb2-phy";
				dr_mode = "host";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only

#include "qcom-ipq8062.dtsi"

&rpm {
	smb208_regulators: regulators {
		compatible = "qcom,rpm-smb208-regulators";

		smb208_s1a: s1a {
			regulator-min-microvolt = <1050000>;
			regulator-max-microvolt = <1150000>;

			qcom,switch-mode-frequency = <1200000>;
		};

		smb208_s1b: s1b {
			regulator-min-microvolt = <1050000>;
			regulator-max-microvolt = <1150000>;

			qcom,switch-mode-frequency = <1200000>;
		};

		smb208_s2a: s2a {
			regulator-min-microvolt = < 800000>;
			regulator-max-microvolt = <1150000>;

			qcom,switch-mode-frequency = <1200000>;
		};

		smb208_s2b: s2b {
			regulator-min-microvolt = < 800000>;
			regulator-max-microvolt = <1150000>;

			qcom,switch-mode-frequency = <1200000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only

#include "qcom-ipq8064-v2.0.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. IPQ8062";
	compatible = "qcom,ipq8062", "qcom,ipq8064";
};


code:
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064-v1.0.dtsi"

/ {
	model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
	compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";

	soc {
		pinmux@800000 {
			buttons_pins: buttons_pins {
				mux {
					pins = "gpio54", "gpio65";
					drive-strength = <2>;
					bias-pull-up;
				};
			};
		};

		gsbi@16300000 {
			i2c@16380000 {
				status = "okay";
				clock-frequency = <200000>;
				pinctrl-0 = <&i2c4_pins>;
				pinctrl-names = "default";
			};
		};
	};
};