code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm PMIC Multi-Purpose Pin (MPP) block

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  This binding describes the MPP block(s) found in the 8xxx series of
  PMIC's from Qualcomm.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - qcom,pm8019-mpp
              - qcom,pm8226-mpp
              - qcom,pm8841-mpp
              - qcom,pm8916-mpp
              - qcom,pm8941-mpp
              - qcom,pm8950-mpp
              - qcom,pmi8950-mpp
              - qcom,pm8994-mpp
              - qcom,pma8084-mpp
              - qcom,pmi8994-mpp
          - const: qcom,spmi-mpp
      - items:
          - enum:
              - qcom,pm8018-mpp
              - qcom,pm8038-mpp
              - qcom,pm8058-mpp
              - qcom,pm8821-mpp
              - qcom,pm8917-mpp
              - qcom,pm8921-mpp
          - const: qcom,ssbi-mpp

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  gpio-controller: true
  gpio-line-names: true

  gpio-ranges:
    maxItems: 1

  '#gpio-cells':
    const: 2
    description:
      The first cell will be used to define gpio number and the
      second denotes the flags for this gpio

additionalProperties: false

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges
  - interrupt-controller

patternProperties:
  '-state$':
    oneOf:
      - $ref: "#/$defs/qcom-pmic-mpp-state"
      - patternProperties:
          "mpp":
            $ref: "#/$defs/qcom-pmic-mpp-state"
        additionalProperties: false

$defs:
  qcom-pmic-mpp-state:
    type: object
    allOf:
      - $ref: "pinmux-node.yaml"
      - $ref: "pincfg-node.yaml"
    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in
          this subnode.  Valid pins are
                 - mpp1-mpp4 for pm8841
                 - mpp1-mpp4 for pm8916
                 - mpp1-mpp8 for pm8941
                 - mpp1-mpp4 for pm8950
                 - mpp1-mpp4 for pmi8950
                 - mpp1-mpp4 for pma8084

        items:
          pattern: "^mpp([0-9]+)$"

      function:
        items:
          - enum:
              - digital
              - analog
              - sink

      bias-disable: true
      bias-pull-up: true
      bias-high-impedance: true
      input-enable: true
      output-high: true
      output-low: true
      power-source: true

      qcom,analog-level:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Selects the source for analog output. Valued values are defined in
          <dt-binding/pinctrl/qcom,pmic-mpp.h> PMIC_MPP_AOUT_LVL_*
        enum: [0, 1, 2, 3, 4, 5, 6, 7]

      qcom,atest:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Selects ATEST rail to route to GPIO when it's
          configured in analog-pass-through mode.
        enum: [1, 2, 3, 4]

      qcom,dtest:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Selects DTEST rail to route to GPIO when it's
          configured as digital input.
        enum: [1, 2, 3, 4]

      qcom,amux-route:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Selects the source for analog input. Valid values are defined in
          <dt-bindings/pinctrl/qcom,pmic-mpp.h> PMIC_MPP_AMUX_ROUTE_CH5,
          PMIC_MPP_AMUX_ROUTE_CH6...
        enum: [0, 1, 2, 3, 4, 5, 6, 7]

      qcom,paired:
        - description:
            Indicates that the pin should be operating in paired mode.

    required:
      - pins
      - function

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>

    pm8841_mpp: mpps@a000 {
      compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp";
      reg = <0xa000 0>;
      gpio-controller;
      #gpio-cells = <2>;
      gpio-ranges = <&pm8841_mpp 0 0 4>;
      gpio-line-names = "VDD_PX_BIAS", "WLAN_LED_CTRL",
              "BT_LED_CTRL", "GPIO-F";
      interrupt-controller;
      #interrupt-cells = <2>;

      pinctrl-names = "default";
      pinctrl-0 = <&pm8841_default>;

      mpp1-state {
        pins = "mpp1";
        function = "digital";
        input-enable;
        power-source = <PM8841_MPP_S3>;
      };

      default-state {
        gpio-mpp {
          pins = "mpp1", "mpp2", "mpp3", "mpp4";
          function = "digital";
          input-enable;
          power-source = <PM8841_MPP_S3>;
        };
      };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,qcm2290-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. QCM2290 TLMM block

maintainers:
  - Shawn Guo <shawn.guo@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm QCM2290 SoC.

properties:
  compatible:
    const: qcom,qcm2290-tlmm

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-qcm2290-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-qcm2290-tlmm-state"
        additionalProperties: false

$defs:
  qcom-qcm2290-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-6])$"
            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
                      sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
                cci_timer0, cci_timer1, cci_timer2, cci_timer3, char_exec,
                cri_trng, cri_trng0, cri_trng1, dac_calib, dbg_out, ddr_bist,
                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2,
                gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx,
                jitter_bist, mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1,
                mpm_pwr, mss_lte, m_voc, nav_gpio, pa_indicator, pbs0, pbs1,
                pbs2, pbs3, pbs4, pbs5, pbs6, pbs7, pbs8, pbs9, pbs10, pbs11,
                pbs12, pbs13, pbs14, pbs15, pbs_out, phase_flag, pll_bist,
                pll_bypassnl, pll_reset, prng_rosc, pwm_0, pwm_1, pwm_2, pwm_3,
                pwm_4, pwm_5, pwm_6, pwm_7, pwm_8, pwm_9, qdss_cti, qdss_gpio,
                qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb, sdc2_tb, sd_write,
                ssbi_wtr1, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm,
                uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
                uim2_data, uim2_present, uim2_reset, usb_phy, vfr_1,
                vsense_trigger, wlan1_adc0, wlan1_adc1 ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@500000 {
        compatible = "qcom,qcm2290-tlmm";
        reg = <0x500000 0x300000>;
        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 127>;

        sdc2_on_state: sdc2-on-state {
            clk-pins {
                pins = "sdc2_clk";
                bias-disable;
                drive-strength = <16>;
            };

            cmd-pins {
                pins = "sdc2_cmd";
                bias-pull-up;
                drive-strength = <10>;
            };

            data-pins {
                pins = "sdc2_data";
                bias-pull-up;
                drive-strength = <10>;
            };
        };
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,qcs404-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm QCS404 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm QCS404 SoC.

properties:
  compatible:
    const: qcom,qcs404-pinctrl

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: south
      - const: north
      - const: east

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 60

  gpio-line-names:
    maxItems: 120

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-qcs404-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-qcs404-tlmm-state"
        additionalProperties: false

$defs:
  qcom-qcs404-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9])$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
                      sdc2_cmd, sdc2_data, ufs_reset ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ gpio, adsp_ext, atest_char, atest_char0, atest_char1,
                atest_char2, atest_char3, aud_cdc, audio_ts, bimc_dte0,
                bimc_dte1, blsp_i2c0, blsp_i2c1, blsp_i2c3, blsp_i2c4,
                blsp_i2c5, blsp_i2c_scl_a2, blsp_i2c_scl_b2, blsp_i2c_sda_a2,
                blsp_i2c_sda_b2, blsp_spi0, blsp_spi2, blsp_spi3, blsp_spi4,
                blsp_spi5, blsp_spi_clk_a1, blsp_spi_clk_b1, blsp_spi_cs_n_a1,
                blsp_spi_cs_n_b1, blsp_spi_miso_a1, blsp_spi_miso_b1,
                blsp_spi_mosi_a1, blsp_spi_mosi_b1, blsp_uart0, blsp_uart1,
                blsp_uart2, blsp_uart3, blsp_uart5, blsp_uart_rx_a2,
                blsp_uart_rx_b2, blsp_uart_tx_a2, blsp_uart_tx_b2, cri_trng,
                cri_trng0, cri_trng1, dbg_out, dsd_clk_a, dsd_clk_b, ebi2_a,
                ebi2_lcd, ebi_cdc, ebi_ch0, ext_lpass, ext_mclk0, ext_mclk1_a,
                ext_mclk1_b, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a,
                gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest,
                gcc_tlmm, hdmi_ddc, hdmi_dtest, hdmi_lbk0, hdmi_lbk1,
                hdmi_lbk2, hdmi_lbk3, hdmi_lbk4, hdmi_lbk5, hdmi_lbk6,
                hdmi_lbk7, hdmi_lbk8, hdmi_lbk9, hdmi_pixel, hdmi_rcv, hdmi_tx,
                i2s_1, i2s_2, i2s_3_data0_a, i2s_3_data0_b, i2s_3_data1_a,
                i2s_3_data1_b, i2s_3_data2_a, i2s_3_data2_b, i2s_3_data3_a,
                i2s_3_data3_b, i2s_3_sck_a, i2s_3_sck_b, i2s_3_ws_a,
                i2s_3_ws_b, i2s_4, ir_in, ldo_en, ldo_update, mclk_in1,
                mclk_in2, m_voc, nfc_dwl, nfc_irq, pcie_clk, pll_bist,
                prng_rosc, pwm_led1, pwm_led10, pwm_led11, pwm_led12,
                pwm_led13, pwm_led14, pwm_led15, pwm_led16, pwm_led17,
                pwm_led18, pwm_led19, pwm_led2, pwm_led20, pwm_led21,
                pwm_led22, pwm_led23, pwm_led24, pwm_led3, pwm_led4, pwm_led5,
                pwm_led6, pwm_led7, pwm_led8, pwm_led9, qdss_cti_trig_in_a0,
                qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
                qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
                qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
                qdss_tracedata_a, qdss_tracedata_b, rgb_clk, rgb_data0,
                rgb_data1, rgb_data2, rgb_data3, rgb_data4, rgb_data5,
                rgb_data6, rgb_data7, rgb_data_b0, rgb_data_b1, rgb_data_b2,
                rgb_data_b3, rgb_data_b4, rgb_data_b5, rgb_data_b6,
                rgb_data_b7, rgb_de, rgb_hsync, rgb_mdp, rgb_vsync, rgmi_dll1,
                rgmi_dll2, rgmii_ck, rgmii_ctl, rgmii_int, rgmii_mdc,
                rgmii_mdio, rgmii_rx, rgmii_tx, rgmii_wol, sd_write,
                spdifrx_opt, spi_lcd, spkr_dac0, wlan1_adc0, wlan1_adc1,
                wlan2_adc0, wlan2_adc1, wsa_en ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@1000000 {
        compatible = "qcom,qcs404-pinctrl";
        reg = <0x01000000 0x200000>,
              <0x01300000 0x200000>,
              <0x07b00000 0x200000>;
        reg-names = "south", "north", "east";
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-ranges = <&tlmm 0 0 120>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;

        blsp1-i2c1-default-state {
            pins = "gpio24", "gpio25";
            function = "blsp_i2c1";
        };

        blsp1-i2c2-default-state {
            sda-pins {
                pins = "gpio19";
                function = "blsp_i2c_sda_a2";
            };

            scl-pins {
                pins = "gpio20";
                function = "blsp_i2c_scl_a2";
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC7180 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC.

properties:
  compatible:
    const: qcom,sc7180-pinctrl

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: west
      - const: north
      - const: south

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 60

  gpio-line-names:
    maxItems: 119

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sc7180-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sc7180-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sc7180-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
                      sdc2_cmd, sdc2_data, ufs_reset ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
                atest_char1, atest_char2, atest_char3, atest_tsens,
                atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
                atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
                atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
                cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
                cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0,
                ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1,
                gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
                jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
                mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1,
                mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST,
                pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti,
                qlink_enable, qlink_request, qspi_clk, qspi_cs, qspi_data,
                qup00, qup01, qup02_i2c, qup02_uart, qup03, qup04_i2c,
                qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, qup12,
                qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb,
                sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
                tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1,
                _V_GPIO, _V_PPS_IN, _V_PPS_OUT, vsense_trigger, wlan1_adc0,
                wlan1_adc1, wlan2_adc0, wlan2_adc1 ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg
  - reg-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@3500000 {
        compatible = "qcom,sc7180-pinctrl";
        reg = <0x03500000 0x300000>,
              <0x03900000 0x300000>,
              <0x03d00000 0x300000>;
        reg-names = "west", "north", "south";
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 120>;
        wakeup-parent = <&pdc>;

        dp_hot_plug_det: dp-hot-plug-det-state {
            pins = "gpio117";
            function = "dp_hot";
        };

        qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
            spi-pins {
                pins = "gpio53", "gpio54", "gpio55";
                function = "qup15";
            };

            cs-pins {
                pins = "gpio56";
                function = "gpio";
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC7280 SoC LPASS LPI TLMM

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
  (LPASS) Low Power Island (LPI) of Qualcomm SC7280 SoC.

properties:
  compatible:
    const: qcom,sc7280-lpass-lpi-pinctrl

  qcom,adsp-bypass-mode:
    description:
      Tells ADSP is in bypass mode.
    type: boolean

  reg:
    maxItems: 2

  gpio-controller: true

  "#gpio-cells":
    description: Specifying the pin number and flags, as defined in
      include/dt-bindings/gpio/gpio.h
    const: 2

  gpio-ranges:
    maxItems: 1

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sc7280-lpass-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sc7280-lpass-state"
        additionalProperties: false

$defs:
  qcom-sc7280-lpass-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: "/schemas/pinctrl/pincfg-node.yaml"

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9])$"
        minItems: 1
        maxItems: 15

      function:
        enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
                qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
                dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
                i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
                dmic3_data, i2s2_data ]
        description:
          Specify the alternative function to be configured for the specified
          pins.

      drive-strength:
        enum: [2, 4, 6, 8, 10, 12, 14, 16]
        default: 2
        description:
          Selects the drive strength for the specified pins, in mA.

      slew-rate:
        enum: [0, 1, 2, 3]
        default: 0
        description: |
            0: No adjustments
            1: Higher Slew rate (faster edges)
            2: Lower Slew rate (slower edges)
            3: Reserved (No adjustments)

      bias-pull-down: true
      bias-pull-up: true
      bias-bus-hold: true
      bias-disable: true
      output-high: true
      output-low: true

    required:
      - pins
      - function

    additionalProperties: false

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"
  - gpio-ranges

additionalProperties: false

examples:
  - |
    lpass_tlmm: pinctrl@33c0000 {
        compatible = "qcom,sc7280-lpass-lpi-pinctrl";
        reg = <0x33c0000 0x20000>,
              <0x3550000 0x10000>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&lpass_tlmm 0 0 15>;

        dmic01-state {
            dmic01-clk-pins {
                pins = "gpio6";
                function = "dmic1_clk";
            };

            dmic01-clk-sleep-pins {
                pins = "gpio6";
                function = "dmic1_clk";
            };
        };

        tx-swr-data-sleep-state {
            pins = "gpio1", "gpio2", "gpio14";
            function = "swr_tx_data";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SC7280 TLMM block

maintainers:
  - Bjorn Andersson <andersson@kernel.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SC7280 SoC.

properties:
  compatible:
    const: qcom,sc7280-pinctrl

  reg:
    maxItems: 1

  interrupts:
    description: Specifies the TLMM summary IRQ
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    description:
      Specifies the PIN numbers and Flags, as defined in defined in
      include/dt-bindings/interrupt-controller/irq.h
    const: 2

  gpio-controller: true

  '#gpio-cells':
    description: Specifying the pin number and flags, as defined in
      include/dt-bindings/gpio/gpio.h
    const: 2

  gpio-ranges:
    maxItems: 1

  gpio-line-names:
    maxItems: 175

  wakeup-parent: true

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sc7280-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sc7280-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sc7280-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
                      sdc2_cmd, sdc2_data, ufs_reset ]
        minItems: 1
        maxItems: 16

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ atest_char, atest_char0, atest_char1, atest_char2,
                atest_char3, atest_usb0, atest_usb00, atest_usb01,
                atest_usb02, atest_usb03, atest_usb1, atest_usb10,
                atest_usb11, atest_usb12, atest_usb13, audio_ref,
                cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
                cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1,
                cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0,
                cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot,
                dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
                gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus,
                mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
                mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck,
                mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
                mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0,
                mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2,
                mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7,
                mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2,
                pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag,
                pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
                qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss,
                qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs,
                qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07,
                qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
                sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write,
                sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1,
                tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset,
                uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
                usb_phy, vfr_0, vfr_1, vsense_trigger ]

      bias-pull-down: true
      bias-pull-up: true
      bias-bus-hold: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@f000000 {
        compatible = "qcom,sc7280-pinctrl";
        reg = <0xf000000 0x1000000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 175>;
        wakeup-parent = <&pdc>;

        qup_uart5_default: qup-uart5-state {
            pins = "gpio46", "gpio47";
            function = "qup13";
            drive-strength = <2>;
            bias-disable;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SC8180X TLMM block

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SC8180X SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sc8180x-tlmm

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: west
      - const: east
      - const: south

  interrupts: true
  interrupt-controller: true
  '#interrupt-cells': true
  gpio-controller: true
  gpio-reserved-ranges: true
  '#gpio-cells': true
  gpio-ranges: true
  wakeup-parent: true

required:
  - compatible
  - reg
  - reg-names

additionalProperties: false

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sc8180x-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sc8180x-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sc8180x-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
        minItems: 1
        maxItems: 16

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
                atest_tsens2, atest_usb0, atest_usb1, atest_usb2, atest_usb3,
                atest_usb4, audio_ref, btfm_slimbus, cam_mclk, cci_async,
                cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
                cci_timer4, cci_timer5, cci_timer6, cci_timer7, cci_timer8,
                cci_timer9, cri_trng, dbg_out, ddr_bist, ddr_pxi, debug_hot,
                dp_hot, edp_hot, edp_lcd, emac_phy, emac_pps, gcc_gp1, gcc_gp2,
                gcc_gp3, gcc_gp4, gcc_gp5, gpio, gps, grfc, hs1_mi2s, hs2_mi2s,
                hs3_mi2s, jitter_bist, lpass_slimbus, m_voc, mdp_vsync,
                mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4,
                mdp_vsync5, mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1,
                pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset,
                pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss_gpio, qlink,
                qspi0, qspi0_clk, qspi0_cs, qspi1, qspi1_clk, qspi1_cs,
                qua_mi2s, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
                qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
                qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, sd_write, sdc4,
                sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu,
                tsense_pwm1, tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
                usb0_phy, usb1_phy, usb2phy_ac, vfr_1, vsense_trigger,
                wlan1_adc, wlan2_adc, wmss_reset ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl@3100000 {
        compatible = "qcom,sc8180x-tlmm";
        reg = <0x03100000 0x300000>,
              <0x03500000 0x700000>,
              <0x03d00000 0x300000>;
        reg-names = "west", "east", "south";
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 190>;

        gpio-wo-subnode-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-subnodes-state {
            rx-pins {
                pins = "gpio4";
                function = "qup6";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio5";
                function = "qup6";
                bias-disable;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC8280XP SoC LPASS LPI TLMM

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
  (LPASS) Low Power Island (LPI) of Qualcomm SC8280XP SoC.

properties:
  compatible:
    const: qcom,sc8280xp-lpass-lpi-pinctrl

  reg:
    items:
      - description: LPASS LPI TLMM Control and Status registers
      - description: LPASS LPI pins SLEW registers

  clocks:
    items:
      - description: LPASS Core voting clock
      - description: LPASS Audio voting clock

  clock-names:
    items:
      - const: core
      - const: audio

  gpio-controller: true

  "#gpio-cells":
    description: Specifying the pin number and flags, as defined in
      include/dt-bindings/gpio/gpio.h
    const: 2

  gpio-ranges:
    maxItems: 1

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sc8280xp-lpass-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sc8280xp-lpass-state"
        additionalProperties: false

$defs:
  qcom-sc8280xp-lpass-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: /schemas/pinctrl/pincfg-node.yaml

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          pattern: "^gpio([0-1]|1[0-8])$"

      function:
        enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
                dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
                dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
                qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
                i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
                wsa2_swr_data, i2s2_data, i2s3_clk, i2s3_ws, i2s3_data,
                ext_mclk1_c, ext_mclk1_b, ext_mclk1_a ]
        description:
          Specify the alternative function to be configured for the specified
          pins.

      drive-strength:
        enum: [2, 4, 6, 8, 10, 12, 14, 16]
        default: 2
        description:
          Selects the drive strength for the specified pins, in mA.

      slew-rate:
        enum: [0, 1, 2, 3]
        default: 0
        description: |
          0: No adjustments
          1: Higher Slew rate (faster edges)
          2: Lower Slew rate (slower edges)
          3: Reserved (No adjustments)

      bias-pull-down: true

      bias-pull-up: true

      bias-disable: true

      output-high: true

      output-low: true

    required:
      - pins
      - function

    additionalProperties: false

allOf:
  - $ref: pinctrl.yaml#

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - gpio-controller
  - "#gpio-cells"
  - gpio-ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/sound/qcom,q6afe.h>
    pinctrl@33c0000 {
        compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
        reg = <0x33c0000 0x20000>,
              <0x3550000 0x10000>;
        clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
        clock-names = "core", "audio";
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&lpi_tlmm 0 0 18>;

        dmic01-state {
            dmic01-clk-pins {
                pins = "gpio16";
                function = "dmic1_clk";
            };

            dmic01-clk-sleep-pins {
                pins = "gpio16";
                function = "dmic1_clk";
            };
        };

        tx-swr-data-sleep-state {
            pins = "gpio0", "gpio1";
            function = "swr_tx_data";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SC8280XP TLMM block

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |
  Top Level Mode Multiplexer pin controller in Qualcomm SC8280XP SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sc8280xp-tlmm

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  gpio-reserved-ranges: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

required:
  - compatible
  - reg

additionalProperties: false

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sc8280xp-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ]
        minItems: 1
        maxItems: 16

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c,
                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
                cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
                cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5,
                ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd,
                edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1,
                emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0,
                emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3,
                emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4,
                gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c,
                jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1,
                mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5,
                mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0,
                mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
                mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
                mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0,
                mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1,
                mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq,
                pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq,
                phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1,
                prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk,
                qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
                qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
                qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1,
                sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig,
                tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
                usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp,
                usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac,
                vsense_trigger ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl@f100000 {
        compatible = "qcom,sc8280xp-tlmm";
        reg = <0x0f100000 0x300000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 230>;

        gpio-wo-subnode-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-subnodes-state {
            rx-pins {
                pins = "gpio4";
                function = "qup14";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio5";
                function = "qup14";
                bias-disable;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sdm630-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SDM630 and SDM660 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SDM630 and SDM660 SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    enum:
      - qcom,sdm630-pinctrl
      - qcom,sdm660-pinctrl

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: south
      - const: center
      - const: north

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 57

  gpio-line-names:
    maxItems: 114

  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sdm630-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sdm630-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sdm630-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
                      sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.
        enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
                atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1,
                atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
                atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20,
                atest_usb21, atest_usb22, atest_usb23, audio_ref, bimc_dte0,
                bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4,
                blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8_a, blsp_i2c8_b,
                blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2,
                blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8_a,
                blsp_spi8_b, blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1,
                blsp_uart2, blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1,
                blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async, cci_i2c,
                cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, gcc_gp1,
                gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c,
                isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync,
                mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte,
                nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0,
                phase_flag1, phase_flag10, phase_flag11, phase_flag12,
                phase_flag13, phase_flag14, phase_flag15, phase_flag16,
                phase_flag17, phase_flag18, phase_flag19, phase_flag2,
                phase_flag20, phase_flag21, phase_flag22, phase_flag23,
                phase_flag24, phase_flag25, phase_flag26, phase_flag27,
                phase_flag28, phase_flag29, phase_flag3, phase_flag30,
                phase_flag31, phase_flag4, phase_flag5, phase_flag6,
                phase_flag7, phase_flag8, phase_flag9, pll_bypassnl, pll_reset,
                pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, pwr_modem,
                pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, qdss_cti1_b,
                qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
                qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, qdss_gpio2,
                qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7,
                qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request, qspi_clk,
                qspi_cs, qspi_data0, qspi_data1, qspi_data2, qspi_data3,
                qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data, sp_cmu,
                ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, uim1_clk,
                uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
                uim2_present, uim2_reset, uim_batt, vfr_1, vsense_clkout,
                vsense_data0, vsense_data1, vsense_mode, wlan1_adc0,
                wlan1_adc1, wlan2_adc0, wlan2_adc1 ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@3100000 {
        compatible = "qcom,sdm630-pinctrl";
        reg = <0x03100000 0x400000>,
              <0x03500000 0x400000>,
              <0x03900000 0x400000>;
        reg-names = "south", "center", "north";
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        gpio-ranges = <&tlmm 0 0 114>;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;

        blsp1-uart1-default-state {
            pins = "gpio0", "gpio1", "gpio2", "gpio3";
            function = "gpio";
            drive-strength = <2>;
            bias-disable;
        };

        blsp2_uart1_default: blsp2-uart1-active-state {
            tx-rts-pins {
                pins = "gpio16", "gpio19";
                function = "blsp_uart5";
                drive-strength = <2>;
                bias-disable;
            };

            rx-pins {
                pins = "gpio17";
                function = "blsp_uart5";
                drive-strength = <2>;
                bias-pull-up;
            };

            cts-pins {
                pins = "gpio18";
                function = "blsp_uart5";
                drive-strength = <2>;
                bias-pull-down;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SDM670 TLMM block

maintainers:
  - Richard Acayan <mailingradian@gmail.com>

description: |
  The Top Level Mode Multiplexer (TLMM) block found in the SDM670 platform.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sdm670-tlmm

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  gpio-reserved-ranges:
    minItems: 1
    maxItems: 75

  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

required:
  - compatible
  - reg

additionalProperties: false

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sdm670-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sdm670-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sdm670-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
            - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
                      sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, atest_usb1, atest_usb10,
                atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
                atest_usb22, atest_usb23, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
                cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, dbg_out, ddr_bist,
                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
                gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, ldo_update,
                lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
                mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl,
                pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss, qlink_enable,
                qlink_request, qua_mi2s, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2,
                qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sdc4_clk,
                sdc4_cmd, sdc4_data, sd_write, sec_mi2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2,
                tgu_ch3, tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, tsif2_clk,
                tsif2_data, tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
                uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1,
                vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data, ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl@3400000 {
        compatible = "qcom,sdm670-tlmm";
        reg = <0x03400000 0x300000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 151>;

        qup-i2c9-state {
            pins = "gpio6", "gpio7";
            function = "qup9";
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SDM845 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SDM845 SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sdm845-pinctrl

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 75

  gpio-line-names:
    maxItems: 150

  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sdm845-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sdm845-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sdm845-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.
        enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2,
                atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13,
                atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_usb23,
                audio_ref, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
                cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
                ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
                gcc_gp2, gcc_gp3, gpio, jitter_bist, ldo_en, ldo_update,
                lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
                mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, pci_e0,
                pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset,
                pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
                qlink_request, qspi_clk, qspi_cs, qspi_data, qua_mi2s, qup0,
                qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3,
                qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
                sdc4_clk, sdc4_cmd, sdc4_data, sd_write, sec_mi2s, sp_cmu,
                spkr_i2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
                tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
                tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
                tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
                uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
                uim_batt, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
                wlan1_adc1, wlan2_adc0, wlan2_adc1]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pinctrl@3400000 {
        compatible = "qcom,sdm845-pinctrl";
        reg = <0x03400000 0xc00000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 151>;
        wakeup-parent = <&pdc_intc>;

        cci0-default-state {
            pins = "gpio17", "gpio18";
            function = "cci_i2c";

            bias-pull-up;
            drive-strength = <2>;
        };

        cam0-default-state {
            rst-pins {
                pins = "gpio9";
                function = "gpio";

                drive-strength = <16>;
                bias-disable;
            };

            mclk0-pins {
                pins = "gpio13";
                function = "cam_mclk";

                drive-strength = <16>;
                bias-disable;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SDX55 TLMM block

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SDX55 SoC.

properties:
  compatible:
    const: qcom,sdx55-pinctrl

  reg:
    description: Specifies the base address and size of the TLMM register space
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true

  gpio-reserved-ranges:
    maxItems: 1

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sdx55-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sdx55-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sdx55-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins. Functions are only valid for gpio pins.
        enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1,
                blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2,
                blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3,
                blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng,
                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
                ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1,
                emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3,
                gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update,
                mgpi_clk, m_voc, native_char, native_char0, native_char1,
                native_char2, native_char3, native_tsens, native_tsense,
                nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref,
                pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
                qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4,
                qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
                qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
                qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2,
                qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7,
                qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12,
                qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17,
                qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22,
                qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27,
                qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en,
                qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss,
                spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data,
                uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
                uim2_reset, usb2phy_ac, vsense_trigger ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@1f00000 {
        compatible = "qcom,sdx55-pinctrl";
        reg = <0x0f100000 0x300000>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&tlmm 0 0 108>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;

        serial-state {
            pins = "gpio8", "gpio9";
            function = "blsp_uart3";
            drive-strength = <8>;
            bias-disable;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SDX65 TLMM block

maintainers:
  - Vamsi krishna Lanka <quic_vamslank@quicinc.com>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SDX65 SoC.

properties:
  compatible:
    const: qcom,sdx65-tlmm

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true

  gpio-reserved-ranges:
    maxItems: 1

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sdx65-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sdx65-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sdx65-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
            - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ]
        minItems: 1
        maxItems: 150

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins. Functions are only valid for gpio pins.
        enum: [ blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
                bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
                qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
                dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
                blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
                mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
                atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
                cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
                pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
                qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
                qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
                atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
                atest_usb20, atest_char0, dac_calib10, qdss_stm10,
                qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
                blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
                qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
                qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
                dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
                qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
                dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
                dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
                dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
                dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
                sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
                qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
                uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
                blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
                qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
                blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
                cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
                blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
                qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
                isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
                qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
                sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
                gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
                qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
                tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
                qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
                sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
                sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
                ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
                blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
                pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
                qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
                qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
                gpio ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@f100000 {
        compatible = "qcom,sdx65-tlmm";
        reg = <0x03000000 0xdc2000>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&tlmm 0 0 109>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;

        gpio-wo-subnode-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-subnodes-state {
            rx-pins {
                pins = "gpio4";
                function = "blsp_uart1";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio5";
                function = "blsp_uart1";
                bias-disable;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block

maintainers:
  - Iskren Chernev <iskren.chernev@gmail.com>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SM4250 and SM6115
  SoCs.

properties:
  compatible:
    const: qcom,sm6115-tlmm

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: west
      - const: south
      - const: east

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  gpio-reserved-ranges: true
  wakeup-parent: true

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm6115-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm6115-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sm6115-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
                      sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
                cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0,
                ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
                gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist,
                mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte,
                m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag,
                pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
                qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb,
                sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk,
                uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
                uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
                wlan1_adc0, elan1_adc1 ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg
  - reg-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@500000 {
        compatible = "qcom,sm6115-tlmm";
        reg = <0x500000 0x400000>,
              <0x900000 0x400000>,
              <0xd00000 0x400000>;
        reg-names = "west", "south", "east";
        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 114>;

        sdc2_on_state: sdc2-on-state {
            clk-pins {
                pins = "sdc2_clk";
                bias-disable;
                drive-strength = <16>;
            };

            cmd-pins {
                pins = "sdc2_cmd";
                bias-pull-up;
                drive-strength = <10>;
            };

            data-pins {
                pins = "sdc2_data";
                bias-pull-up;
                drive-strength = <10>;
            };

            sd-cd-pins {
                pins = "gpio88";
                function = "gpio";
                bias-pull-up;
                drive-strength = <2>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. SM6125 TLMM block

maintainers:
  - Martin Botka <martin.botka@somainline.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SM6125 SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sm6125-tlmm

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: west
      - const: south
      - const: east

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  gpio-reserved-ranges: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

required:
  - compatible
  - reg
  - reg-names

additionalProperties: false

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm6125-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm6125-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sm6125-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
                atest_char2, atest_char3, atest_tsens, atest_tsens2, atest_usb1,
                atest_usb10, atest_usb11, atest_usb12, atest_usb13, atest_usb2,
                atest_usb20, atest_usb21, atest_usb22, atest_usb23, aud_sb,
                audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
                cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, cri_trng,
                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
                ddr_pxi2, ddr_pxi3, debug_hot, dmic0_clk, dmic0_data, dmic1_clk,
                dmic1_data, dp_hot, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
                gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en,
                ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0, mdp_vsync1,
                mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, mpm_pwr, mss_lte,
                nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset,
                pri_mi2s, pri_mi2s_ws, prng_rosc, qca_sb, qdss_cti, qdss, qlink_enable,
                qlink_request, qua_mi2s, qui_mi2s, qup00, qup01, qup02, qup03, qup04,
                qup10, qup11, qup12, qup13, qup14, sd_write, sec_mi2s, sp_cmu, swr_rx,
                swr_tx, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm,
                uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
                uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger,
                wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl@500000 {
        compatible = "qcom,sm6125-tlmm";
        reg = <0x00500000 0x400000>,
              <0x00900000 0x400000>,
              <0x00d00000 0x400000>;
        reg-names = "west", "south", "east";
        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        gpio-ranges = <&tlmm 0 0 134>;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;

        sdc2-off-state {
            clk-pins {
                pins = "sdc2_clk";
                drive-strength = <2>;
                bias-disable;
            };

            cmd-pins {
                pins = "sdc2_cmd";
                drive-strength = <2>;
                bias-pull-up;
            };

            data-pins {
                pins = "sdc2_data";
                drive-strength = <2>;
                bias-pull-up;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SM6350 TLMM block

maintainers:
  - Konrad Dybcio <konrad.dybcio@somainline.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SM6350 SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sm6350-tlmm

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  gpio-reserved-ranges: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

required:
  - compatible
  - reg

additionalProperties: false

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm6350-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm6350-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sm6350-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-7])$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, atest_char2,
                atest_char3, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
                atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, atest_usb22,
                atest_usb23, audio_ref, btfm_slimbus, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3,
                cam_mclk4, cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
                cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3,
                dp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,
                gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext, m_voc, mclk,
                mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1, mi2s_2,
                mss_lte, nav_gpio, nav_pps, pa_indicator, pcie0_clk, phase_flag0, phase_flag1,
                phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15,
                phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20,
                phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26,
                phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31,
                phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9,
                pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, qdss_gpio, qdss_gpio0,
                qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
                qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
                qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss,
                qlink1_enable, qlink1_request, qlink1_wmss, qup00, qup01, qup02, qup10, qup11,
                qup12, qup13_f1, qup13_f2, qup14, rffe0_clk, rffe0_data, rffe1_clk, rffe1_data,
                rffe2_clk, rffe2_data, rffe3_clk, rffe3_data, rffe4_clk, rffe4_data, sd_write,
                sdc1_tb, sdc2_tb, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
                tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
                uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
                wlan2_adc0, wlan2_adc1, ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl@f100000 {
        compatible = "qcom,sm6350-tlmm";
        reg = <0x0f100000 0x300000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 157>;

        gpio-wo-subnode-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-subnodes-state {
            rx-pins {
                pins = "gpio25";
                function = "qup13_f2";
                bias-disable;
            };

            tx-pins {
                pins = "gpio26";
                function = "qup13_f2";
                bias-disable;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SM6375 TLMM block

maintainers:
  - Konrad Dybcio <konrad.dybcio@somainline.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SM6375 SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sm6375-tlmm

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  gpio-reserved-ranges: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

required:
  - compatible
  - reg

additionalProperties: false

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm6375-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm6375-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sm6375-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$"
            - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
                      sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
                atest_char2, atest_char3, atest_tsens, atest_tsens2,
                atest_usb1, atest_usb10, atest_usb11, atest_usb12,
                atest_usb13, atest_usb2, atest_usb20, atest_usb21,
                atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
                cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
                cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist,
                ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd,
                gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio,
                gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext,
                m_voc, mclk, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
                mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, mss_lte, nav_gpio,
                nav_pps, pa_indicator, phase_flag0, phase_flag1, phase_flag10,
                phase_flag11, phase_flag12, phase_flag13, phase_flag14,
                phase_flag15, phase_flag16, phase_flag17, phase_flag18,
                phase_flag19, phase_flag2, phase_flag20, phase_flag21,
                phase_flag22, phase_flag23, phase_flag24, phase_flag25,
                phase_flag26, phase_flag27, phase_flag28, phase_flag29,
                phase_flag3, phase_flag30, phase_flag31, phase_flag4,
                phase_flag5, phase_flag6, phase_flag7, phase_flag8,
                phase_flag9, pll_bist, pll_bypassnl, pll_clk, pll_reset,
                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
                qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11,
                qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15,
                qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6,
                qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
                qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
                qlink1_wmss, qup00, qup01, qup02, qup10, qup11_f1, qup11_f2,
                qup12, qup13_f1, qup13_f2, qup14, sd_write, sdc1_tb, sdc2_tb,
                sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
                tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset,
                uim2_clk, uim2_data, uim2_present, uim2_reset, usb2phy_ac,
                usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
                wlan2_adc0, wlan2_adc1 ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl@500000 {
        compatible = "qcom,sm6375-tlmm";
        reg = <0x00500000 0x800000>;
        interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 157>;

        gpio-wo-subnode-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-subnodes-state {
            rx-pins {
                pins = "gpio18";
                function = "qup13_f2";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio19";
                function = "qup13_f2";
                bias-disable;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8150-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8150 TLMM pin controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC.

properties:
  compatible:
    const: qcom,sm8150-pinctrl

  reg:
    maxItems: 4

  reg-names:
    items:
      - const: west
      - const: east
      - const: north
      - const: south

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 88

  gpio-line-names:
    maxItems: 175

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm8150-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm8150-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sm8150-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
                atest_char0, atest_char1, atest_char2, atest_char3, audio_ref,
                atest_usb1, atest_usb2, atest_usb10, atest_usb11, atest_usb12,
                atest_usb13, atest_usb20, atest_usb21, atest_usb22, atest_usb2,
                atest_usb23, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
                cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
                ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, emac_phy, emac_pps,
                gcc_gp1, gcc_gp2, gcc_gp3, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s,
                jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
                mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator,
                pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset,
                pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti,
                qlink_request, qlink_enable, qspi0, qspi1, qspi2, qspi3,
                qspi_clk, qspi_cs, qua_mi2s, qup0, qup1, qup2, qup3, qup4,
                qup5, qup6, qup7, qup8, qup9, qup10, qup11, qup12, qup13,
                qup14, qup15, qup16, qup17, qup18, qup19, qup_l4, qup_l5,
                qup_l6, rgmii, sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu,
                ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
                tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, usb2phy_ac,
                usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
                wlan2_adc0, wlan2_adc1, wmss_reset ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg
  - reg-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@3100000 {
        compatible = "qcom,sm8150-pinctrl";
        reg = <0x03100000 0x300000>,
              <0x03500000 0x300000>,
              <0x03900000 0x300000>,
              <0x03d00000 0x300000>;
        reg-names = "west", "east", "north", "south";
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-ranges = <&tlmm 0 0 176>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        wakeup-parent = <&pdc>;

        qup-spi0-default-state {
            pins = "gpio0", "gpio1", "gpio2", "gpio3";
            function = "qup0";
            drive-strength = <6>;
            bias-disable;
        };

        pcie1-default-state {
            perst-pins {
                pins = "gpio102";
                function = "gpio";
                drive-strength = <2>;
                bias-pull-down;
            };

            clkreq-pins {
                pins = "gpio103";
                function = "pci_e1";
                drive-strength = <2>;
                bias-pull-up;
            };

            wake-pins {
                pins = "gpio104";
                function = "gpio";
                drive-strength = <2>;
                bias-pull-up;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8250 SoC LPASS LPI TLMM

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
  (LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC.

properties:
  compatible:
    const: qcom,sm8250-lpass-lpi-pinctrl

  reg:
    maxItems: 2

  clocks:
    items:
      - description: LPASS Core voting clock
      - description: LPASS Audio voting clock

  clock-names:
    items:
      - const: core
      - const: audio

  gpio-controller: true

  "#gpio-cells":
    description: Specifying the pin number and flags, as defined in
      include/dt-bindings/gpio/gpio.h
    const: 2

  gpio-ranges:
    maxItems: 1

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm8250-lpass-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm8250-lpass-state"
        additionalProperties: false

$defs:
  qcom-sm8250-lpass-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: "/schemas/pinctrl/pincfg-node.yaml"

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9])$"
        minItems: 1
        maxItems: 14

      function:
        enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws,
                qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk,
                dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data,
                i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk,
                dmic3_data, i2s2_data ]
        description:
          Specify the alternative function to be configured for the specified
          pins.

      drive-strength:
        enum: [2, 4, 6, 8, 10, 12, 14, 16]
        default: 2
        description:
          Selects the drive strength for the specified pins, in mA.

      slew-rate:
        enum: [0, 1, 2, 3]
        default: 0
        description: |
            0: No adjustments
            1: Higher Slew rate (faster edges)
            2: Lower Slew rate (slower edges)
            3: Reserved (No adjustments)

      bias-pull-down: true
      bias-pull-up: true
      bias-bus-hold: true
      bias-disable: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins
      - function

    additionalProperties: false

allOf:
  - $ref: pinctrl.yaml#

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - gpio-controller
  - "#gpio-cells"
  - gpio-ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/sound/qcom,q6afe.h>
    lpi_tlmm: pinctrl@33c0000 {
        compatible = "qcom,sm8250-lpass-lpi-pinctrl";
        reg = <0x33c0000 0x20000>,
              <0x3550000 0x10000>;
        clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
        clock-names = "core", "audio";
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&lpi_tlmm 0 0 14>;

        wsa-swr-active-state {
            clk-pins {
                pins = "gpio10";
                function = "wsa_swr_clk";
                drive-strength = <2>;
                slew-rate = <1>;
                bias-disable;
            };

            data-pins {
                pins = "gpio11";
                function = "wsa_swr_data";
                drive-strength = <2>;
                slew-rate = <1>;
            };
        };

        tx-swr-sleep-clk-state {
            pins = "gpio0";
            function = "swr_tx_clk";
            drive-strength = <2>;
            bias-pull-down;
        };
    };