code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright Altera Corporation (C) 2014. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/altr,rst-mgr-a10.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "altr,socfpga-a10-smp";

		cpu0: cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
		};
		cpu1: cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};
	};

	pmu: pmu@ff111000 {
		compatible = "arm,cortex-a9-pmu";
		interrupt-parent = <&intc>;
		interrupts = <0 124 4>, <0 125 4>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
		reg = <0xff111000 0x1000>,
		      <0xff113000 0x1000>;
	};

	intc: interrupt-controller@ffffd000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xffffd000 0x1000>,
		      <0xffffc100 0x100>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges;

		amba {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pdma: pdma@ffda1000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0xffda1000 0x1000>;
				interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
					     <0 84 IRQ_TYPE_LEVEL_HIGH>,
					     <0 85 IRQ_TYPE_LEVEL_HIGH>,
					     <0 86 IRQ_TYPE_LEVEL_HIGH>,
					     <0 87 IRQ_TYPE_LEVEL_HIGH>,
					     <0 88 IRQ_TYPE_LEVEL_HIGH>,
					     <0 89 IRQ_TYPE_LEVEL_HIGH>,
					     <0 90 IRQ_TYPE_LEVEL_HIGH>,
					     <0 91 IRQ_TYPE_LEVEL_HIGH>;
				#dma-cells = <1>;
				clocks = <&l4_main_clk>;
				clock-names = "apb_pclk";
				resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
				reset-names = "dma", "dma-ocp";
			};
		};

		base_fpga_region {
			#address-cells = <0x1>;
			#size-cells = <0x1>;

			compatible = "fpga-region";
			fpga-mgr = <&fpga_mgr>;
		};

		clkmgr@ffd04000 {
				compatible = "altr,clk-mgr";
				reg = <0xffd04000 0x1000>;

				clocks {
					#address-cells = <1>;
					#size-cells = <0>;

					cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					cb_intosc_ls_clk: cb_intosc_ls_clk {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					f2s_free_clk: f2s_free_clk {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					osc1: osc1 {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					main_pll: main_pll@40 {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-pll-clock";
						clocks = <&osc1>, <&cb_intosc_ls_clk>,
							 <&f2s_free_clk>;
						reg = <0x40>;

						main_mpu_base_clk: main_mpu_base_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							div-reg = <0x140 0 11>;
						};

						main_noc_base_clk: main_noc_base_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							div-reg = <0x144 0 11>;
						};

						main_emaca_clk: main_emaca_clk@68 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x68>;
						};

						main_emacb_clk: main_emacb_clk@6c {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x6C>;
						};

						main_emac_ptp_clk: main_emac_ptp_clk@70 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x70>;
						};

						main_gpio_db_clk: main_gpio_db_clk@74 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x74>;
						};

						main_sdmmc_clk: main_sdmmc_clk@78 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk"
;
							clocks = <&main_pll>;
							reg = <0x78>;
						};

						main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x7C>;
						};

						main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x80>;
						};

						main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x84>;
						};

						main_periph_ref_clk: main_periph_ref_clk@9c {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&main_pll>;
							reg = <0x9C>;
						};
					};

					periph_pll: periph_pll@c0 {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-pll-clock";
						clocks = <&osc1>, <&cb_intosc_ls_clk>,
							 <&f2s_free_clk>, <&main_periph_ref_clk>;
						reg = <0xC0>;

						peri_mpu_base_clk: peri_mpu_base_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							div-reg = <0x140 16 11>;
						};

						peri_noc_base_clk: peri_noc_base_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							div-reg = <0x144 16 11>;
						};

						peri_emaca_clk: peri_emaca_clk@e8 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0xE8>;
						};

						peri_emacb_clk: peri_emacb_clk@ec {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0xEC>;
						};

						peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0xF0>;
						};

						peri_gpio_db_clk: peri_gpio_db_clk@f4 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0xF4>;
						};

						peri_sdmmc_clk: peri_sdmmc_clk@f8 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0xF8>;
						};

						peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0xFC>;
						};

						peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x100>;
						};

						peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-a10-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x104>;
						};
					};

					mpu_free_clk: mpu_free_clk@60 {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
							 <&osc1>, <&cb_intosc_hs_div2_clk>,
							 <&f2s_free_clk>;
						reg = <0x60>;
					};

					noc_free_clk: noc_free_clk@64 {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
							 <&osc1>, <&cb_intosc_hs_div2_clk>,
							 <&f2s_free_clk>;
						reg = <0x64>;
					};

					s2f_user1_free_clk: s2f_user1_free_clk@104 {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
							 <&osc1>, <&cb_intosc_hs_div2_clk>,
							 <&f2s_free_clk>;
						reg = <0x104>;
					};

					sdmmc_free_clk: sdmmc_free_clk@f8 {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
							 <&osc1>, <&cb_intosc_hs_div2_clk>,
							 <&f2s_free_clk>;
						fixed-divider = <4>;
						reg = <0xF8>;
					};

					l4_sys_free_clk: l4_sys_free_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-perip-clk";
						clocks = <&noc_free_clk>;
						fixed-divider = <4>;
					};

					l4_main_clk: l4_main_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&noc_free_clk>;
						div-reg = <0xA8 0 2>;
						clk-gate = <0x48 1>;
					};

					l4_mp_clk: l4_mp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&noc_free_clk>;
						div-reg = <0xA8 8 2>;
						clk-gate = <0x48 2>;
					};

					l4_sp_clk: l4_sp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&noc_free_clk>;
						div-reg = <0xA8 16 2>;
						clk-gate = <0x48 3>;
					};

					mpu_periph_clk: mpu_periph_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&mpu_free_clk>;
						fixed-divider = <4>;
						clk-gate = <0x48 0>;
					};

					sdmmc_clk: sdmmc_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&sdmmc_free_clk>;
						clk-gate = <0xC8 5>;
					};

					qspi_clk: qspi_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&l4_main_clk>;
						clk-gate = <0xC8 11>;
					};

					nand_x_clk: nand_x_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&l4_mp_clk>;
						clk-gate = <0xC8 10>;
					};

					nand_ecc_clk: nand_ecc_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&nand_x_clk>;
						clk-gate = <0xC8 10>;
					};

					nand_clk: nand_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&nand_x_clk>;
						fixed-divider = <4>;
						clk-gate = <0xC8 10>;
					};

					spi_m_clk: spi_m_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&l4_main_clk>;
						clk-gate = <0xC8 9>;
					};

					usb_clk: usb_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&l4_mp_clk>;
						clk-gate = <0xC8 8>;
					};

					s2f_usr1_clk: s2f_usr1_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-a10-gate-clk";
						clocks = <&peri_s2f_usr1_clk>;
						clk-gate = <0xC8 6>;
					};
				};
		};

		socfpga_axi_setup: stmmac-axi-config {
			snps,wr_osr_lmt = <0xf>;
			snps,rd_osr_lmt = <0xf>;
			snps,blen = <0 0 0 0 16 0 0>;
		};

		gmac0: ethernet@ff800000 {
			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
			reg = <0xff800000 0x2000>;
			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			/* Filled in by bootloader */
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <4096>;
			rx-fifo-depth = <16384>;
			clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
			clock-names = "stmmaceth", "ptp_ref";
			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			snps,axi-config = <&socfpga_axi_setup>;
			status = "disabled";
		};

		gmac1: ethernet@ff802000 {
			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
			altr,sysmgr-syscon = <&sysmgr 0x48 8>;
		        reg = <0xff802000 0x2000>;
			interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			/* Filled in by bootloader */
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <4096>;
			rx-fifo-depth = <16384>;
			clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
			clock-names = "stmmaceth", "ptp_ref";
			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			snps,axi-config = <&socfpga_axi_setup>;
			status = "disabled";
		};

		gmac2: ethernet@ff804000 {
			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
			altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
			reg = <0xff804000 0x2000>;
			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq";
			/* Filled in by bootloader */
			mac-address = [00 00 00 00 00 00];
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <4096>;
			rx-fifo-depth = <16384>;
			clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
			clock-names = "stmmaceth", "ptp_ref";
			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
			reset-names = "stmmaceth", "stmmaceth-ocp";
			snps,axi-config = <&socfpga_axi_setup>;
			status = "disabled";
		};

		gpio0: gpio@ffc02900 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02900 0x100>;
			resets = <&rst GPIO0_RESET>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <29>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio1: gpio@ffc02a00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02a00 0x100>;
			resets = <&rst GPIO1_RESET>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <29>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio2: gpio@ffc02b00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc02b00 0x100>;
			resets = <&rst GPIO2_RESET>;
			status = "disabled";

			portc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <27>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		fpga_mgr: fpga-mgr@ffd03000 {
			compatible = "altr,socfpga-a10-fpga-mgr";
			reg = <0xffd03000 0x100
			       0xffcfe400 0x20>;
			clocks = <&l4_mp_clk>;
			resets = <&rst FPGAMGR_RESET>;
			reset-names = "fpgamgr";
		};

		i2c0: i2c@ffc02200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02200 0x100>;
			interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sp_clk>;
			resets = <&rst I2C0_RESET>;
			status = "disabled";
		};

		i2c1: i2c@ffc02300 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02300 0x100>;
			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sp_clk>;
			resets = <&rst I2C1_RESET>;
			status = "disabled";
		};

		i2c2: i2c@ffc02400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02400 0x100>;
			interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sp_clk>;
			resets = <&rst I2C2_RESET>;
			status = "disabled";
		};

		i2c3: i2c@ffc02500 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02500 0x100>;
			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sp_clk>;
			resets = <&rst I2C3_RESET>;
			status = "disabled";
		};

		i2c4: i2c@ffc02600 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02600 0x100>;
			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sp_clk>;
			resets = <&rst I2C4_RESET>;
			status = "disabled";
		};

		spi0: spi@ffda4000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xffda4000 0x100>;
			interrupts = <0 101 4>;
			num-cs = <4>;
			/*32bit_access;*/
			clocks = <&spi_m_clk>;
			resets = <&rst SPIM0_RESET>;
			reset-names = "spi";
			status = "disabled";
		};

		spi1: spi@ffda5000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xffda5000 0x100>;
			interrupts = <0 102 4>;
			num-cs = <4>;
			/*32bit_access;*/
			tx-dma-channel = <&pdma 16>;
			rx-dma-channel = <&pdma 17>;
			clocks = <&spi_m_clk>;
			resets = <&rst SPIM1_RESET>;
			reset-names = "spi";
			status = "disabled";
		};

		sdr: sdr@ffcfb100 {
			compatible = "altr,sdr-ctl", "syscon";
			reg = <0xffcfb100 0x80>;
		};

		L2: cache-controller@fffff000 {
			compatible = "arm,pl310-cache";
			reg = <0xfffff000 0x1000>;
			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-level = <2>;
			prefetch-data = <1>;
			prefetch-instr = <1>;
			arm,shared-override;
		};

		mmc: mmc@ff808000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff808000 0x1000>;
			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
			fifo-depth = <0x400>;
			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
			clock-names = "biu", "ciu";
			resets = <&rst SDMMC_RESET>;
			altr,sysmgr-syscon = <&sysmgr 0x28 4>;
			status = "disabled";
		};

		nand: nand@ffb90000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-denali-nand";
			reg = <0xffb90000 0x72000>,
			      <0xffb80000 0x10000>;
			reg-names = "nand_data", "denali_reg";
			interrupts = <0 99 4>;
			clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
			clock-names = "nand", "nand_x", "ecc";
			resets = <&rst NAND_RESET>;
			status = "disabled";
		};

		ocram: sram@ffe00000 {
			compatible = "mmio-sram";
			reg = <0xffe00000 0x40000>;
		};

		eccmgr: eccmgr {
			compatible = "altr,socfpga-a10-ecc-manager";
			altr,sysmgr-syscon = <&sysmgr>;
			#address-cells = <1>;
			#size-cells = <1>;
			interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
				     <0 0 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ranges;

			sdramedac {
				compatible = "altr,sdram-edac-a10";
				altr,sdr-syscon = <&sdr>;
				interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
					     <49 IRQ_TYPE_LEVEL_HIGH>;
			};

			l2-ecc@ffd06010 {
				compatible = "altr,socfpga-a10-l2-ecc";
				reg = <0xffd06010 0x4>;
				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
					     <32 IRQ_TYPE_LEVEL_HIGH>;
			};

			ocram-ecc@ff8c3000 {
				compatible = "altr,socfpga-a10-ocram-ecc";
				reg = <0xff8c3000 0x400>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
					     <33 IRQ_TYPE_LEVEL_HIGH>;
			};

			emac0-rx-ecc@ff8c0800 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0800 0x400>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
					     <36 IRQ_TYPE_LEVEL_HIGH>;
			};

			emac0-tx-ecc@ff8c0c00 {
				compatible = "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0c00 0x400>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
					     <37 IRQ_TYPE_LEVEL_HIGH>;
			};

			sdmmca-ecc@ff8c2c00 {
				compatible = "altr,socfpga-sdmmc-ecc";
				reg = <0xff8c2c00 0x400>;
				altr,ecc-parent = <&mmc>;
				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
					     <47 IRQ_TYPE_LEVEL_HIGH>,
					     <16 IRQ_TYPE_LEVEL_HIGH>,
					     <48 IRQ_TYPE_LEVEL_HIGH>;
			};

			dma-ecc@ff8c8000 {
				compatible = "altr,socfpga-dma-ecc";
				reg = <0xff8c8000 0x400>;
				altr,ecc-parent = <&pdma>;
				interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
					     <42 IRQ_TYPE_LEVEL_HIGH>;
			};

			usb0-ecc@ff8c8800 {
				compatible = "altr,socfpga-usb-ecc";
				reg = <0xff8c8800 0x400>;
				altr,ecc-parent = <&usb0>;
				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
					     <34 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		qspi: spi@ff809000 {
			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xff809000 0x100>,
			      <0xffa00000 0x100000>;
			interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
			cdns,fifo-depth = <128>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x00000000>;
			clocks = <&qspi_clk>;
			resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
			reset-names = "qspi", "qspi-ocp";
			status = "disabled";
		};

		rst: rstmgr@ffd05000 {
			#reset-cells = <1>;
			compatible = "altr,rst-mgr";
			reg = <0xffd05000 0x100>;
			altr,modrst-offset = <0x20>;
		};

		scu: snoop-control-unit@ffffc000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xffffc000 0x100>;
		};

		sysmgr: sysmgr@ffd06000 {
			compatible = "altr,sys-mgr", "syscon";
			reg = <0xffd06000 0x300>;
			cpu1-start-addr = <0xffd06230>;
		};

		/* Local timer */
		timer@ffffc600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xffffc600 0x100>;
			interrupts = <1 13 0xf01>;
			clocks = <&mpu_periph_clk>;
		};

		timer0: timer0@ffc02700 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0xffc02700 0x100>;
			clocks = <&l4_sp_clk>;
			clock-names = "timer";
			resets = <&rst SPTIMER0_RESET>;
			reset-names = "timer";
		};

		timer1: timer1@ffc02800 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0xffc02800 0x100>;
			clocks = <&l4_sp_clk>;
			clock-names = "timer";
			resets = <&rst SPTIMER1_RESET>;
			reset-names = "timer";
		};

		timer2: timer2@ffd00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0xffd00000 0x100>;
			clocks = <&l4_sys_free_clk>;
			clock-names = "timer";
			resets = <&rst L4SYSTIMER0_RESET>;
			reset-names = "timer";
		};

		timer3: timer3@ffd00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0xffd00100 0x100>;
			clocks = <&l4_sys_free_clk>;
			clock-names = "timer";
			resets = <&rst L4SYSTIMER1_RESET>;
			reset-names = "timer";
		};

		uart0: serial0@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x100>;
			interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&l4_sp_clk>;
			resets = <&rst UART0_RESET>;
			status = "disabled";
		};

		uart1: serial1@ffc02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02100 0x100>;
			interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&l4_sp_clk>;
			resets = <&rst UART1_RESET>;
			status = "disabled";
		};

		usbphy0: usbphy {
			#phy-cells = <0>;
			compatible = "usb-nop-xceiv";
			status = "okay";
		};

		usb0: usb@ffb00000 {
			compatible = "snps,dwc2";
			reg = <0xffb00000 0xffff>;
			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&usb_clk>;
			clock-names = "otg";
			resets = <&rst USB0_RESET>;
			reset-names = "dwc2";
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		usb1: usb@ffb40000 {
			compatible = "snps,dwc2";
			reg = <0xffb40000 0xffff>;
			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&usb_clk>;
			clock-names = "otg";
			resets = <&rst USB1_RESET>;
			reset-names = "dwc2";
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		watchdog0: watchdog@ffd00200 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00200 0x100>;
			interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sys_free_clk>;
			resets = <&rst L4WD0_RESET>;
			status = "disabled";
		};

		watchdog1: watchdog@ffd00300 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00300 0x100>;
			interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&l4_sys_free_clk>;
			resets = <&rst L4WD1_RESET>;
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2022 Google LLC
 */
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"

/ {
	model = "Google Chameleon V3";
	compatible = "google,chameleon-v3", "enclustra,mercury-aa1",
		     "altr,socfpga-arria10", "altr,socfpga";

	aliases {
		serial0 = &uart0;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
	};
};

&gmac0 {
	status = "okay";
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	ssm2603: audio-codec@1a {
		compatible = "adi,ssm2603";
		reg = <0x1a>;
	};
};

&i2c1 {
	status = "okay";

	u80: gpio@21 {
		compatible = "nxp,pca9535";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;

		gpio-line-names =
			"SOM_AUD_MUTE",
			"DP1_OUT_CEC_EN",
			"DP2_OUT_CEC_EN",
			"DP1_SOM_PS8469_CAD",
			"DPD_SOM_PS8469_CAD",
			"DP_OUT_PWR_EN",
			"STM32_RST_L",
			"STM32_BOOT0",

			"FPGA_PROT",
			"STM32_FPGA_COMM0",
			"TP119",
			"TP120",
			"TP121",
			"TP122",
			"TP123",
			"TP124";
	};
};

&mmc {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&usb0 {
	status = "okay";
	dr_mode = "host";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2022 Google LLC
 */

#include "socfpga_arria10.dtsi"

/ {

	model = "Enclustra Mercury AA1";
	compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga";

	aliases {
		ethernet0 = &gmac0;
		serial1 = &uart1;
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x80000000>; /* 2GB */
	};

	chosen {
		stdout-path = "serial1:115200n8";
	};
};

&gmac0 {
	phy-mode = "rgmii";
	phy-addr = <0xffffffff>; /* probe for phy addr */

	max-frame-size = <3800>;

	phy-handle = <&phy3>;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy3: ethernet-phy@3 {
			txd0-skew-ps = <0>; /* -420ps */
			txd1-skew-ps = <0>; /* -420ps */
			txd2-skew-ps = <0>; /* -420ps */
			txd3-skew-ps = <0>; /* -420ps */
			rxd0-skew-ps = <420>; /* 0ps */
			rxd1-skew-ps = <420>; /* 0ps */
			rxd2-skew-ps = <420>; /* 0ps */
			rxd3-skew-ps = <420>; /* 0ps */
			txen-skew-ps = <0>; /* -420ps */
			txc-skew-ps = <1860>; /* 960ps */
			rxdv-skew-ps = <420>; /* 0ps */
			rxc-skew-ps = <1680>; /* 780ps */
			reg = <3>;
		};
	};
};

&i2c1 {
	atsha204a: crypto@64 {
		compatible = "atmel,atsha204a";
		reg = <0x64>;
	};

	isl12022: isl12022@6f {
		compatible = "isil,isl12022";
		reg = <0x6f>;
	};
};

/* Following mappings are taken from arria10 socdk dts */
&mmc {
	cap-sd-highspeed;
	broken-cd;
	bus-width = <4>;
	clk-phase-sd-hs = <0>, <135>;
};

&osc1 {
	clock-frequency = <33330000>;
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015 Altera Corporation <www.altera.com>
 */
#include "socfpga_arria10.dtsi"

/ {
	model = "Altera SOCFPGA Arria 10";
	compatible = "altr,socfpga-arria10-socdk", "altr,socfpga-arria10", "altr,socfpga";

	aliases {
		ethernet0 = &gmac0;
		serial0 = &uart1;
	};

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1GB */
	};

	a10leds {
		compatible = "gpio-leds";

		a10sr_led0 {
			label = "a10sr-led0";
			gpios = <&a10sr_gpio 0 1>;
		};

		a10sr_led1 {
			label = "a10sr-led1";
			gpios = <&a10sr_gpio 1 1>;
		};

		a10sr_led2 {
			label = "a10sr-led2";
			gpios = <&a10sr_gpio 2 1>;
		};

		a10sr_led3 {
			label = "a10sr-led3";
			gpios = <&a10sr_gpio 3 1>;
		};
	};

	ref_033v: 033-v-ref {
		compatible = "regulator-fixed";
		regulator-name = "0.33V";
		regulator-min-microvolt = <330000>;
		regulator-max-microvolt = <330000>;
	};

	soc {
		clkmgr@ffd04000 {
			clocks {
				osc1 {
					clock-frequency = <25000000>;
				};
			};
		};
	};
};

&gmac0 {
	phy-mode = "rgmii";
	phy-addr = <0xffffffff>; /* probe for phy addr */

	/*
	 * These skews assume the user's FPGA design is adding 600ps of delay
	 * for TX_CLK on Arria 10.
	 *
	 * All skews are offset since hardware skew values for the ksz9031
	 * range from a negative skew to a positive skew.
	 * See the micrel-ksz90x1.txt Documentation file for details.
	 */
	txd0-skew-ps = <0>; /* -420ps */
	txd1-skew-ps = <0>; /* -420ps */
	txd2-skew-ps = <0>; /* -420ps */
	txd3-skew-ps = <0>; /* -420ps */
	rxd0-skew-ps = <420>; /* 0ps */
	rxd1-skew-ps = <420>; /* 0ps */
	rxd2-skew-ps = <420>; /* 0ps */
	rxd3-skew-ps = <420>; /* 0ps */
	txen-skew-ps = <0>; /* -420ps */
	txc-skew-ps = <1860>; /* 960ps */
	rxdv-skew-ps = <420>; /* 0ps */
	rxc-skew-ps = <1680>; /* 780ps */
	max-frame-size = <3800>;
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&spi1 {
	status = "okay";

	resource-manager@0 {
		compatible = "altr,a10sr";
		reg = <0>;
		spi-max-frequency = <100000>;
		/* low-level active IRQ at GPIO1_5 */
		interrupt-parent = <&portb>;
		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <2>;

		a10sr_gpio: gpio-controller {
			compatible = "altr,a10sr-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		a10sr_rst: reset-controller {
			compatible = "altr,a10sr-reset";
			#reset-cells = <1>;
		};
	};
};

&i2c1 {
	status = "okay";

	/*
	 * adjust the falling times to decrease the i2c frequency to 50Khz
	 * because the LCD module does not work at the standard 100Khz
	 */
	clock-frequency = <100000>;
	i2c-sda-falling-time-ns = <6000>;
	i2c-scl-falling-time-ns = <6000>;

	adc@14 {
		compatible = "lltc,ltc2497";
		reg = <0x14>;
		vref-supply = <&ref_033v>;
	};

	adc@16 {
		compatible = "lltc,ltc2497";
		reg = <0x16>;
		vref-supply = <&ref_033v>;
	};

	eeprom@51 {
		compatible = "atmel,24c32";
		reg = <0x51>;
		pagesize = <32>;
	};

	rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
	};

	ltc@5c {
		compatible = "ltc2977";
		reg = <0x5c>;
	};

	temp@4c {
		compatible = "maxim,max1619";
		reg = <0x4c>;
	};
};

&uart1 {
	status = "okay";
};

&usb0 {
	status = "okay";
	disable-over-current;
};

&watchdog1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2015 Altera Corporation. All rights reserved.
 */

/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"

&nand {
	status = "okay";

	nand@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "Boot and fpga data";
			reg = <0x0 0x02500000>;
		};
		partition@1c00000 {
			label = "Root Filesystem - JFFS2";
			reg = <0x02500000 0x05500000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2016 Intel. All rights reserved.
 */

/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"

&qspi {
	status = "okay";

	flash0: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,mt25qu02g", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <100000000>;

		m25p,fast-read;
		cdns,page-size = <256>;
		cdns,block-size = <16>;
		cdns,read-delay = <3>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;

		partition@qspi-boot {
			label = "Boot and fpga data";
			reg = <0x0 0x2720000>;
		};

		partition@qspi-rootfs {
			label = "Root Filesystem - JFFS2";
			reg = <0x2720000 0x58E0000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
 */

/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"

&mmc {
	status = "okay";
	cap-sd-highspeed;
	cap-mmc-highspeed;
	broken-cd;
	bus-width = <4>;
	clk-phase-sd-hs = <0>, <135>;
};

&eccmgr {
	sdmmca-ecc@ff8c2c00 {
		compatible = "altr,socfpga-sdmmc-ecc";
		reg = <0xff8c2c00 0x400>;
		altr,ecc-parent = <&mmc>;
		interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
			     <47 IRQ_TYPE_LEVEL_HIGH>,
			     <16 IRQ_TYPE_LEVEL_HIGH>,
			     <48 IRQ_TYPE_LEVEL_HIGH>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2013 Altera Corporation <www.altera.com>
 */

/dts-v1/;
/* First 4KB has trampoline code for secondary cores. */
/memreserve/ 0x00000000 0x0001000;
#include "socfpga.dtsi"

/ {
	soc {
		clkmgr@ffd04000 {
			clocks {
				osc1 {
					clock-frequency = <25000000>;
				};
			};
		};

		mmc0: mmc@ff704000 {
			broken-cd;
			bus-width = <4>;
			cap-mmc-highspeed;
			cap-sd-highspeed;
			clk-phase-sd-hs = <0>, <135>;
		};

		sysmgr@ffd08000 {
			cpu1-start-addr = <0xffd080c4>;
		};
	};
};

&watchdog0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2013 Altera Corporation <www.altera.com>
 */

#include "socfpga_arria5.dtsi"

/ {
	model = "Altera SOCFPGA Arria V SoC Development Kit";
	compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga";

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1GB */
	};

	aliases {
		/* this allow the ethaddr uboot environmnet variable contents
		* to be added to the gmac1 device tree blob.
		*/
		ethernet0 = &gmac1;
	};

	leds {
		compatible = "gpio-leds";
		led-hps0 {
			label = "hps_led0";
			gpios = <&porta 0 1>;
		};

		led-hps1 {
			label = "hps_led1";
			gpios = <&portb 11 1>;
		};

		led-hps2 {
			label = "hps_led2";
			gpios = <&porta 17 1>;
		};

		led-hps3 {
			label = "hps_led3";
			gpios = <&porta 18 1>;
		};
	};

	regulator_3_3v: regulator {
		compatible = "regulator-fixed";
		regulator-name = "3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&gmac1 {
	status = "okay";
	phy-mode = "rgmii";

	rxd0-skew-ps = <0>;
	rxd1-skew-ps = <0>;
	rxd2-skew-ps = <0>;
	rxd3-skew-ps = <0>;
	txen-skew-ps = <0>;
	txc-skew-ps = <2600>;
	rxdv-skew-ps = <0>;
	rxc-skew-ps = <2000>;
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&i2c0 {
	status = "okay";
	clock-frequency = <100000>;

	/*
	 * adjust the falling times to decrease the i2c frequency to 50Khz
	 * because the LCD module does not work at the standard 100Khz
	 */
	i2c-sda-falling-time-ns = <5000>;
	i2c-scl-falling-time-ns = <5000>;

	eeprom@51 {
		compatible = "atmel,24c32";
		reg = <0x51>;
		pagesize = <32>;
	};

	rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
	};
};

&mmc0 {
	vmmc-supply = <&regulator_3_3v>;
	vqmmc-supply = <&regulator_3_3v>;
	status = "okay";
};

&qspi {
	status = "okay";

	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q256a", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <100000000>;

		m25p,fast-read;
		cdns,page-size = <256>;
		cdns,block-size = <16>;
		cdns,read-delay = <4>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;

		partition@qspi-boot {
			/* 8MB for raw data. */
			label = "Flash 0 Raw Data";
			reg = <0x0 0x800000>;
		};

		partition@qspi-rootfs {
			/* 120MB for jffs2 data. */
			label = "Flash 0 jffs2 Filesystem";
			reg = <0x800000 0x7800000>;
		};
	};
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2012 Altera Corporation <www.altera.com>
 */

/dts-v1/;
/* First 4KB has trampoline code for secondary cores. */
/memreserve/ 0x00000000 0x0001000;
#include "socfpga.dtsi"

/ {
	soc {
		clkmgr@ffd04000 {
			clocks {
				osc1 {
					clock-frequency = <25000000>;
				};
			};
		};

		mmc0: mmc@ff704000 {
			broken-cd;
			bus-width = <4>;
			cap-mmc-highspeed;
			cap-sd-highspeed;
			clk-phase-sd-hs = <0>, <135>;
		};

		sysmgr@ffd08000 {
			cpu1-start-addr = <0xffd080c4>;
		};
	};
};

&watchdog0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for the Chameleon96
 *
 * Copyright (c) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 */

#include <dt-bindings/gpio/gpio.h>

#include "socfpga_cyclone5.dtsi"

/ {
	model = "Novetech Chameleon96";
	compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga";

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x20000000>; /* 512MB */
	};

	regulator_3_3v: regulator {
		compatible = "regulator-fixed";
		regulator-name = "3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	leds {
		compatible = "gpio-leds";

		user_led1 {
			label = "green:user1";
			gpios = <&porta 14 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
		};

		user_led2 {
			label = "green:user2";
			gpios = <&porta 22 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "mmc0";
		};

		user_led3 {
			label = "green:user3";
			gpios = <&porta 25 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "none";
		};

		user_led4 {
			label = "green:user4";
			gpios = <&portb 3 GPIO_ACTIVE_LOW>;
			panic-indicator;
			linux,default-trigger = "none";
		};
	};
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&i2c0 {
	/* On Low speed expansion */
	label = "LS-I2C0";
	status = "okay";
};

&i2c1 {
	/* On Low speed expansion */
	label = "LS-I2C1";
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&i2c3 {
	/* On High speed expansion */
	label = "HS-I2C2";
	status = "okay";
};

&mmc0 {
	vmmc-supply = <&regulator_3_3v>;
	vqmmc-supply = <&regulator_3_3v>;
	status = "okay";
};

&spi0 {
	/* On High speed expansion */
	label = "HS-SPI1";
	status = "okay";
};

&spi1 {
	/* On Low speed expansion */
	label = "LS-SPI0";
	status = "okay";
};

&uart0 {
	/* On Low speed expansion */
	label = "LS-UART1";
	status = "okay";
};

&uart1 {
	/* On Low speed expansion */
	label = "LS-UART0";
	status = "okay";
};

&usbphy0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright Altera Corporation (C) 2015. All rights reserved.
 */

#include "socfpga_cyclone5.dtsi"

/ {
	model = "Terasic DE-0(Atlas)";
	compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1GB */
	};

	aliases {
		ethernet0 = &gmac1;
	};

	regulator_3_3v: regulator {
		compatible = "regulator-fixed";
		regulator-name = "3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	leds {
		compatible = "gpio-leds";
		led-hps0 {
			label = "hps_led0";
			gpios = <&portb 24 0>;
			linux,default-trigger = "heartbeat";
		};
	};
};

&gmac1 {
	status = "okay";
	phy-mode = "rgmii";

	txd0-skew-ps = <0>; /* -420ps */
	txd1-skew-ps = <0>; /* -420ps */
	txd2-skew-ps = <0>; /* -420ps */
	txd3-skew-ps = <0>; /* -420ps */
	rxd0-skew-ps = <420>; /* 0ps */
	rxd1-skew-ps = <420>; /* 0ps */
	rxd2-skew-ps = <420>; /* 0ps */
	rxd3-skew-ps = <420>; /* 0ps */
	txen-skew-ps = <0>; /* -420ps */
	txc-skew-ps = <1860>; /* 960ps */
	rxdv-skew-ps = <420>; /* 0ps */
	rxc-skew-ps = <1680>; /* 780ps */

	max-frame-size = <3800>;
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&i2c0 {
	status = "okay";
	clock-frequency = <100000>;

	adxl345: adxl345@53 {
		compatible = "adi,adxl345";
		reg = <0x53>;

		interrupt-parent = <&portc>;
		interrupts = <3 2>;
	};
};

&mmc0 {
	vmmc-supply = <&regulator_3_3v>;
	vqmmc-supply = <&regulator_3_3v>;
	status = "okay";
};

&uart0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
 */

#include "socfpga_cyclone5.dtsi"

/ {
	model = "Aries/DENX MCV";
	compatible = "altr,socfpga-cyclone5", "altr,socfpga";

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1 GiB */
	};
};

&mmc0 {	/* On-SoM eMMC */
	bus-width = <8>;
	clk-phase-sd-hs = <0>, <135>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
 */

#include "socfpga_cyclone5_mcv.dtsi"

/ {
	model = "Aries/DENX MCV EVK";
	compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga";

	aliases {
		ethernet0 = &gmac0;
		stmpe-i2c0 = &stmpe1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&can0 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&gmac0 {
	phy-mode = "rgmii";
	status = "okay";
};

&gpio0 {	/* GPIO  0 ... 28 */
	status = "okay";
};

&gpio1 {	/* GPIO 29 ... 57 */
	status = "okay";
};

&gpio2 {	/* GPIO 58..66 (HLGPI 0..13 at offset 13) */
	status = "okay";
};

&i2c0 {
	status = "okay";
	clock-frequency = <100000>;

	stmpe1: stmpe811@41 {
		compatible = "st,stmpe811";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x41>;
		id = <0>;
		blocks = <0x5>;
		irq-gpio = <&portb 28 0x4>;     /* GPIO 57, trig. level HI */

		stmpe_touchscreen {
			compatible = "st,stmpe-ts";
			ts,sample-time = <4>;
			ts,mod-12b = <1>;
			ts,ref-sel = <0>;
			ts,adc-freq = <1>;
			ts,ave-ctrl = <1>;
			ts,touch-det-delay = <3>;
			ts,settling = <4>;
			ts,fraction-z = <7>;
			ts,i-drive = <1>;
		};
	};
};

&uart0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2012 Altera Corporation <www.altera.com>
 */

#include "socfpga_cyclone5.dtsi"

/ {
	model = "Altera SOCFPGA Cyclone V SoC Development Kit";
	compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1GB */
	};

	aliases {
		/* this allow the ethaddr uboot environmnet variable contents
		 * to be added to the gmac1 device tree blob.
		 */
		ethernet0 = &gmac1;
	};

	leds {
		compatible = "gpio-leds";
		led-hps0 {
			label = "hps_led0";
			gpios = <&portb 15 1>;
		};

		led-hps1 {
			label = "hps_led1";
			gpios = <&portb 14 1>;
		};

		led-hps2 {
			label = "hps_led2";
			gpios = <&portb 13 1>;
		};

		led-hps3 {
			label = "hps_led3";
			gpios = <&portb 12 1>;
		};
	};

	regulator_3_3v: regulator {
		compatible = "regulator-fixed";
		regulator-name = "3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&can0 {
	status = "okay";
};

&gmac1 {
	status = "okay";
	phy-mode = "rgmii";

	rxd0-skew-ps = <0>;
	rxd1-skew-ps = <0>;
	rxd2-skew-ps = <0>;
	rxd3-skew-ps = <0>;
	txen-skew-ps = <0>;
	txc-skew-ps = <2600>;
	rxdv-skew-ps = <0>;
	rxc-skew-ps = <2000>;
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&i2c0 {
	status = "okay";
	clock-frequency = <100000>;

	/*
	 * adjust the falling times to decrease the i2c frequency to 50Khz
	 * because the LCD module does not work at the standard 100Khz
	 */
	i2c-sda-falling-time-ns = <5000>;
	i2c-scl-falling-time-ns = <5000>;

	eeprom@51 {
		compatible = "atmel,24c32";
		reg = <0x51>;
		pagesize = <32>;
	};

	rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
	};
};

&mmc0 {
	cd-gpios = <&portb 18 0>;
	vmmc-supply = <&regulator_3_3v>;
	vqmmc-supply = <&regulator_3_3v>;
	status = "okay";
};

&qspi {
	status = "okay";

	flash0: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,mt25qu02g", "jedec,spi-nor";
		reg = <0>;	/* chip select */
		spi-max-frequency = <100000000>;

		m25p,fast-read;
		cdns,page-size = <256>;
		cdns,block-size = <16>;
		cdns,read-delay = <4>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;

		partition@qspi-boot {
			/* 8MB for raw data. */
			label = "Flash 0 Raw Data";
			reg = <0x0 0x800000>;
		};

		partition@qspi-rootfs {
			/* 120MB for jffs2 data. */
			label = "Flash 0 jffs2 Filesystem";
			reg = <0x800000 0x7800000>;
		};
	};
};

&spi0 {
	status = "okay";

	spidev@0 {
		compatible = "rohm,dh2228fv";
		reg = <0>;
		spi-max-frequency = <1000000>;
	};
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
 */

#include "socfpga_cyclone5.dtsi"

/ {
	model = "Terasic SoCkit";
	compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1GB */
	};

	aliases {
		/* this allow the ethaddr uboot environmnet variable contents
		 * to be added to the gmac1 device tree blob.
		 */
		ethernet0 = &gmac1;
	};

	leds {
		compatible = "gpio-leds";

		hps_led0 {
			label = "hps:blue:led0";
			gpios = <&portb 24 0>;	/* HPS_GPIO53 */
			linux,default-trigger = "heartbeat";
		};

		hps_led1 {
			label = "hps:blue:led1";
			gpios = <&portb 25 0>;	/* HPS_GPIO54 */
			linux,default-trigger = "heartbeat";
		};

		hps_led2 {
			label = "hps:blue:led2";
			gpios = <&portb 26 0>;	/* HPS_GPIO55 */
			linux,default-trigger = "heartbeat";
		};

		hps_led3 {
			label = "hps:blue:led3";
			gpios = <&portb 27 0>;	/* HPS_GPIO56 */
			linux,default-trigger = "heartbeat";
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		hps_sw0 {
			label = "hps_sw0";
			gpios = <&portc 20 0>;	/* HPS_GPI7 */
			linux,input-type = <5>;	/* EV_SW */
			linux,code = <0x0>;	/* SW_LID */
		};

		hps_sw1 {
			label = "hps_sw1";
			gpios = <&portc 19 0>;	/* HPS_GPI6 */
			linux,input-type = <5>;	/* EV_SW */
			linux,code = <0x5>;	/* SW_DOCK */
		};

		hps_sw2 {
			label = "hps_sw2";
			gpios = <&portc 18 0>;	/* HPS_GPI5 */
			linux,input-type = <5>;	/* EV_SW */
			linux,code = <0xa>;	/* SW_KEYPAD_SLIDE */
		};

		hps_sw3 {
			label = "hps_sw3";
			gpios = <&portc 17 0>;	/* HPS_GPI4 */
			linux,input-type = <5>;	/* EV_SW */
			linux,code = <0xc>;	/* SW_ROTATE_LOCK */
		};

		hps_hkey0 {
			label = "hps_hkey0";
			gpios = <&portc 21 1>;	/* HPS_GPI8 */
			linux,code = <187>;	/* KEY_F17 */
		};

		hps_hkey1 {
			label = "hps_hkey1";
			gpios = <&portc 22 1>;	/* HPS_GPI9 */
			linux,code = <188>;	/* KEY_F18 */
		};

		hps_hkey2 {
			label = "hps_hkey2";
			gpios = <&portc 23 1>;	/* HPS_GPI10 */
			linux,code = <189>;	/* KEY_F19 */
		};

		hps_hkey3 {
			label = "hps_hkey3";
			gpios = <&portc 24 1>;	/* HPS_GPI11 */
			linux,code = <190>;	/* KEY_F20 */
		};
	};

	regulator_3_3v: regulator {
		compatible = "regulator-fixed";
		regulator-name = "VCC3P3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&gmac1 {
	status = "okay";
	phy-mode = "rgmii";

	rxd0-skew-ps = <0>;
	rxd1-skew-ps = <0>;
	rxd2-skew-ps = <0>;
	rxd3-skew-ps = <0>;
	txen-skew-ps = <0>;
	txc-skew-ps = <2600>;
	rxdv-skew-ps = <0>;
	rxc-skew-ps = <2000>;
};

&gpio0 {	/* GPIO 0..29 */
	status = "okay";
};

&gpio1 {	/* GPIO 30..57 */
	status = "okay";
};

&gpio2 {	/* GPIO 58..66 (HLGPI 0..13 at offset 13) */
	status = "okay";
};

&i2c1 {
	status = "okay";

	accel1: accelerometer@53 {
		compatible = "adi,adxl345";
		reg = <0x53>;

		interrupt-parent = <&portc>;
		interrupts = <3 2>;
	};
};

&mmc0 {
	vmmc-supply = <&regulator_3_3v>;
	vqmmc-supply = <&regulator_3_3v>;
	status = "okay";
};

&qspi {
	status = "okay";

	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,mt25qu02g", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <100000000>;

		m25p,fast-read;
		cdns,page-size = <256>;
		cdns,block-size = <16>;
		cdns,read-delay = <4>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;
	};
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
 */

#include "socfpga_cyclone5.dtsi"

/ {
	model = "EBV SOCrates";
	compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";

	aliases {
		ethernet0 = &gmac1;
	};

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1GB */
	};

	leds: gpio-leds {
	};
};

&gmac1 {
	phy-mode = "rgmii";
	status = "okay";
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	rtc: rtc@68 {
		compatible = "st,m41t82";
		reg = <0x68>;
	};
};

&leds {
	compatible = "gpio-leds";

	led0 {
		label = "led:green:heartbeat";
		gpios = <&porta 28 1>;
		linux,default-trigger = "heartbeat";
	};

	led1 {
		label = "led:green:D7";
		gpios = <&portb 19 1>;
	};

	led2 {
		label = "led:green:D8";
		gpios = <&portb 25 1>;
	};
};

&mmc {
	status = "okay";
};

&qspi {
	status = "okay";

	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q256a", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <100000000>;
		m25p,fast-read;
		cdns,read-delay = <4>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;
		status = "okay";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 */

#include "socfpga_cyclone5.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board";
	compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga";

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};

	aliases {
		ethernet0 = &gmac1;
	};

	regulator_3_3v: regulator {
		compatible = "regulator-fixed";
		regulator-name = "3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	leds: gpio-leds {
		compatible = "gpio-leds";

		hps_led0 {
			label = "hps:green:led0";
			gpios = <&portb 12 GPIO_ACTIVE_LOW>;
		};

		hps_led1 {
			label = "hps:green:led1";
			gpios = <&portb 13 GPIO_ACTIVE_LOW>;
		};

		hps_led2 {
			label = "hps:green:led2";
			gpios = <&portb 14 GPIO_ACTIVE_LOW>;
		};

		hps_led3 {
			label = "hps:green:led3";
			gpios = <&portb 15 GPIO_ACTIVE_LOW>;
		};
	};
};

&gmac1 {
	status = "okay";
	phy-mode = "rgmii";
	phy = <&phy0>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		phy0: ethernet-phy@0 {
			reg = <0>;
			rxd0-skew-ps = <0>;
			rxd1-skew-ps = <0>;
			rxd2-skew-ps = <0>;
			rxd3-skew-ps = <0>;
			rxdv-skew-ps = <0>;
			rxc-skew-ps = <3000>;
			txen-skew-ps = <0>;
			txc-skew-ps = <3000>;
		};
	};
};

&gpio1 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	eeprom@51 {
		compatible = "atmel,24c32";
		reg = <0x51>;
		pagesize = <32>;
	};

	rtc@68 {
		compatible = "dallas,ds1339";
		reg = <0x68>;
	};
};

&mmc0 {
	cd-gpios = <&portb 18 0>;
	vmmc-supply = <&regulator_3_3v>;
	vqmmc-supply = <&regulator_3_3v>;
	status = "okay";
};

&usb1 {
	status = "okay";
};

&qspi {
	status = "okay";

	flash0: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q512a", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <100000000>;

		m25p,fast-read;
		cdns,page-size = <256>;
		cdns,block-size = <16>;
		cdns,read-delay = <4>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
 */

#include "socfpga_cyclone5.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "samtec VIN|ING FPGA";
	compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1GB */
	};

	aliases {
		/*
		 * This allow the ethaddr uboot environment variable contents
		 * to be added to the gmac1 device tree blob.
		 */
		ethernet0 = &gmac1;
		ethernet1 = &gmac0;
	};

	gpio-keys {
		compatible = "gpio-keys";

		hps_temp0 {
			label = "BTN_0";			/* TEMP_OS */
			gpios = <&portc 18 GPIO_ACTIVE_LOW>;	/* HPS_GPI5 */
			linux,code = <BTN_0>;
		};

		hps_hkey0 {
			label = "GP_SWITCH";			/* GP_SWITCH */
			gpios = <&portc 19 GPIO_ACTIVE_LOW>;	/* HPS_GPI6 */
			linux,code = <BTN_1>;
		};

		hps_hkey1 {
			label = "RESET_SWITCH";			/* RESET_SWITCH */
			gpios = <&portc 20 GPIO_ACTIVE_LOW>;	/* HPS_GPI7 */
			linux,code = <BTN_2>;
		};

		hps_hkey2 {
			label = "POWER_DOWN";			/* POWER_DOWN */
			gpios = <&portc 4 GPIO_ACTIVE_LOW>;	/* HPS_GPIO62 */
			linux,code = <KEY_POWER>;
		};

		hps_hkey3 {
			label = "SENSE";			/* SENSE */
			gpios = <&porta 9 GPIO_ACTIVE_LOW>;	/* HPS_GPIO9 */
			linux,code = <BTN_3>;
		};
	};

	regulator-usb-nrst {
		compatible = "regulator-fixed";
		regulator-name = "usb_nrst";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&portb 5 GPIO_ACTIVE_HIGH>;
		startup-delay-us = <70000>;
		enable-active-high;
		regulator-always-on;
	};
};

&gmac1 {
	status = "okay";
	phy-mode = "rgmii";
	phy-handle = <&phy1>;

	snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	snps,reset-delays-us = <10000 10000 10000>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy1: ethernet-phy@1 {
			reg = <1>;
			rxd0-skew-ps = <0>;
			rxd1-skew-ps = <0>;
			rxd2-skew-ps = <0>;
			rxd3-skew-ps = <0>;
			txd0-skew-ps = <0>;
			txd1-skew-ps = <0>;
			txd2-skew-ps = <0>;
			txd3-skew-ps = <0>;
			txen-skew-ps = <0>;
			txc-skew-ps = <1860>;
			rxdv-skew-ps = <0>;
			rxc-skew-ps = <1860>;
		};
	};
};

&gpio0 {	/* GPIO 0..29 */
	status = "okay";
};

&gpio1 {	/* GPIO 30..57 */
	status = "okay";
};

&gpio2 {	/* GPIO 58..66 (HLGPI 0..13 at offset 13) */
	status = "okay";
};

&i2c0 {
	status = "okay";

	gpio: pca9557@1f {
		compatible = "nxp,pca9557";
		reg = <0x1f>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	temp: lm75@48 {
		compatible = "lm75";
		reg = <0x48>;
	};

	at24@50 {
		compatible = "atmel,24c01";
		pagesize = <8>;
		reg = <0x50>;
	};

	i2c-mux@70 {
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
		};

		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
		};

		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
		};

		i2c@6 {	/* Backplane EEPROM */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
			eeprom@51 {
				compatible = "atmel,24c01";
				pagesize = <8>;
				reg = <0x51>;
			};
		};

		i2c@7 {	/* Power board EEPROM */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <7>;
			eeprom@51 {
				compatible = "atmel,24c01";
				pagesize = <8>;
				reg = <0x51>;
			};
		};
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <100000>;

	at24@50 {
		compatible = "atmel,24c02";
		pagesize = <8>;
		reg = <0x50>;
	};
};

&qspi {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q128", "jedec,spi-nor";
		reg = <0>;		/* chip select */
		spi-max-frequency = <100000000>;
		m25p,fast-read;

		cdns,page-size = <256>;
		cdns,block-size = <16>;
		cdns,read-delay = <4>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;
	};

	flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,mt25qu02g", "jedec,spi-nor";
		reg = <1>;		/* chip select */
		spi-max-frequency = <100000000>;
		m25p,fast-read;

		cdns,page-size = <256>;
		cdns,block-size = <16>;
		cdns,read-delay = <4>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;
	};
};

&usb0 {
	dr_mode = "host";
	status = "okay";
};

&usb1 {
	dr_mode = "peripheral";
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2013 Altera Corporation <www.altera.com>
 */

/dts-v1/;
#include "socfpga.dtsi"

/ {
	model = "Altera SOCFPGA VT";
	compatible = "altr,socfpga-vt", "altr,socfpga";

	chosen {
		bootargs = "console=ttyS0,57600";
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1 GB */
	};

	soc {
		clkmgr@ffd04000 {
			clocks {
				osc1 {
					clock-frequency = <10000000>;
				};
			};
		};

		mmc@ff704000 {
			broken-cd;
			bus-width = <4>;
			cap-mmc-highspeed;
			cap-sd-highspeed;
		};

		ethernet@ff700000 {
			phy-mode = "gmii";
			status = "okay";
		};

		timer0@ffc08000 {
			clock-frequency = <7000000>;
		};

		timer1@ffc09000 {
			clock-frequency = <7000000>;
		};

		timer2@ffd00000 {
			clock-frequency = <7000000>;
		};

		timer3@ffd01000 {
			clock-frequency = <7000000>;
		};

		serial0@ffc02000 {
			clock-frequency = <7372800>;
		};

		serial1@ffc03000 {
			clock-frequency = <7372800>;
		};

		sysmgr@ffd08000 {
			cpu1-start-addr = <0xffd08010>;
		};
	};
};

&gmac0 {
	status = "okay";
	phy-mode = "gmii";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for SPEAr1310 Evaluation Baord
 *
 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
 */

/dts-v1/;
/include/ "spear1310.dtsi"

/ {
	model = "ST SPEAr1310 Evaluation Board";
	compatible = "st,spear1310-evb", "st,spear1310";
	#address-cells = <1>;
	#size-cells = <1>;

	memory {
		reg = <0 0x40000000>;
	};

	ahb {
		pinmux@e0700000 {
			pinctrl-names = "default";
			pinctrl-0 = <&state_default>;

			state_default: pinmux {
				i2c0 {
					st,pins = "i2c0_grp";
					st,function = "i2c0";
				};
				i2s0 {
					st,pins = "i2s0_grp";
					st,function = "i2s0";
				};
				i2s1 {
					st,pins = "i2s1_grp";
					st,function = "i2s1";
				};
				gpio {
					st,pins = "arm_gpio_grp";
					st,function = "arm_gpio";
				};
				clcd {
					st,pins = "clcd_grp" , "clcd_high_res";
					st,function = "clcd";
				};
				eth {
					st,pins = "gmii_grp";
					st,function = "gmii";
				};
				ssp0 {
					st,pins = "ssp0_grp";
					st,function = "ssp0";
				};
				kbd {
					st,pins = "keyboard_6x6_grp";
					st,function = "keyboard";
				};
				sdhci {
					st,pins = "sdhci_grp";
					st,function = "sdhci";
				};
				smi-pmx {
					st,pins = "smi_2_chips_grp";
					st,function = "smi";
				};
				uart0 {
					st,pins = "uart0_grp";
					st,function = "uart0";
				};
				rs485 {
					st,pins = "rs485_0_1_tdm_0_1_grp";
					st,function = "rs485_0_1_tdm_0_1";
				};
				i2c1_2 {
					st,pins = "i2c_1_2_grp";
					st,function = "i2c_1_2";
				};
				smii {
					st,pins = "smii_0_1_2_grp";
					st,function = "smii_0_1_2";
				};
				nand {
					st,pins = "nand_8bit_grp",
						"nand_16bit_grp";
					st,function = "nand";
				};
				sata {
					st,pins = "sata0_grp";
					st,function = "sata";
				};
				pcie {
					st,pins = "pcie1_grp", "pcie2_grp";
					st,function = "pci_express";
				};
			};
		};

		ahci@b1000000 {
			status = "okay";
		};

		miphy@eb800000 {
			status = "okay";
		};

		cf@b2800000 {
			status = "okay";
		};

		dma@ea800000 {
			status = "okay";
		};

		dma@eb000000 {
			status = "okay";
		};

		fsmc: flash@b0000000 {
			status = "okay";

			partition@0 {
				label = "xloader";
				reg = <0x0 0x80000>;
			};
			partition@80000 {
				label = "u-boot";
				reg = <0x80000 0x140000>;
			};
			partition@1C0000 {
				label = "environment";
				reg = <0x1C0000 0x40000>;
			};
			partition@200000 {
				label = "dtb";
				reg = <0x200000 0x40000>;
			};
			partition@240000 {
				label = "linux";
				reg = <0x240000 0xC00000>;
			};
			partition@E40000 {
				label = "rootfs";
				reg = <0xE40000 0x0>;
			};
		};

		gpio_keys {
			compatible = "gpio-keys";
			#address-cells = <1>;
			#size-cells = <0>;

			button@1 {
				label = "wakeup";
				linux,code = <0x100>;
				gpios = <&gpio0 7 0x4>;
				debounce-interval = <20>;
				wakeup-source;
			};
		};

		gmac0: eth@e2000000 {
			phy-mode = "gmii";
			status = "okay";
		};

		sdhci@b3000000 {
			status = "okay";
		};

		smi: flash@ea000000 {
			status = "okay";
			clock-rate = <50000000>;

			flash@e6000000 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xe6000000 0x800000>;
				st,smi-fast-mode;

				partition@0 {
					label = "xloader";
					reg = <0x0 0x10000>;
				};
				partition@10000 {
					label = "u-boot";
					reg = <0x10000 0x50000>;
				};
				partition@60000 {
					label = "environment";
					reg = <0x60000 0x10000>;
				};
				partition@70000 {
					label = "dtb";
					reg = <0x70000 0x10000>;
				};
				partition@80000 {
					label = "linux";
					reg = <0x80000 0x310000>;
				};
				partition@390000 {
					label = "rootfs";
					reg = <0x390000 0x0>;
				};
			};
		};

		ehci@e4800000 {
			status = "okay";
		};

		ehci@e5800000 {
			status = "okay";
		};

		ohci@e4000000 {
			status = "okay";
		};

		ohci@e5000000 {
			status = "okay";
		};

		apb {
			adc@e0080000 {
				status = "okay";
			};

			gpio0: gpio@e0600000 {
			       status = "okay";
			};

			gpio1: gpio@e0680000 {
			       status = "okay";
			};

			gpio@d8400000 {
			       status = "okay";
			};

			i2c0: i2c@e0280000 {
			       status = "okay";
			};

			kbd@e0300000 {
				linux,keymap = < 0x00000001
						 0x00010002
						 0x00020003
						 0x00030004
						 0x00040005
						 0x00050006
						 0x00060007
						 0x00070008
						 0x00080009
						 0x0100000a
						 0x0101000c
						 0x0102000d
						 0x0103000e
						 0x0104000f
						 0x01050010
						 0x01060011
						 0x01070012
						 0x01080013
						 0x02000014
						 0x02010015
						 0x02020016
						 0x02030017
						 0x02040018
						 0x02050019
						 0x0206001a
						 0x0207001b
						 0x0208001c
						 0x0300001d
						 0x0301001e
						 0x0302001f
						 0x03030020
						 0x03040021
						 0x03050022
						 0x03060023
						 0x03070024
						 0x03080025
						 0x04000026
						 0x04010027
						 0x04020028
						 0x04030029
						 0x0404002a
						 0x0405002b
						 0x0406002c
						 0x0407002d
						 0x0408002e
						 0x0500002f
						 0x05010030
						 0x05020031
						 0x05030032
						 0x05040033
						 0x05050034
						 0x05060035
						 0x05070036
						 0x05080037
						 0x06000038
						 0x06010039
						 0x0602003a
						 0x0603003b
						 0x0604003c
						 0x0605003d
						 0x0606003e
						 0x0607003f
						 0x06080040
						 0x07000041
						 0x07010042
						 0x07020043
						 0x07030044
						 0x07040045
						 0x07050046
						 0x07060047
						 0x07070048
						 0x07080049
						 0x0800004a
						 0x0801004b
						 0x0802004c
						 0x0803004d
						 0x0804004e
						 0x0805004f
						 0x08060050
						 0x08070051
						 0x08080052 >;
			       autorepeat;
			       st,mode = <0>;
			       suspended_rate = <2000000>;
			       status = "okay";
			};

			rtc@e0580000 {
			       status = "okay";
			};

			serial@e0000000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			spi0: spi@e0100000 {
				status = "okay";
				num-cs = <3>;
				cs-gpios = <&gpio1 7 0>, <&spics 0 0>, <&spics 1 0>;

				stmpe610@0 {
					compatible = "st,stmpe610";
					reg = <0>;
					#address-cells = <1>;
					#size-cells = <0>;
					spi-max-frequency = <1000000>;
					spi-cpha;
					pl022,hierarchy = <0>;
					pl022,interface = <0>;
					pl022,slave-tx-disable;
					pl022,com-mode = <0>;
					pl022,rx-level-trig = <0>;
					pl022,tx-level-trig = <0>;
					pl022,ctrl-len = <0x7>;
					pl022,wait-state = <0>;
					pl022,duplex = <0>;
					interrupts = <6 0x4>;
					interrupt-parent = <&gpio1>;
					irq-trigger = <0x2>;

					stmpe_touchscreen {
						compatible = "st,stmpe-ts";
						ts,sample-time = <4>;
						ts,mod-12b = <1>;
						ts,ref-sel = <0>;
						ts,adc-freq = <1>;
						ts,ave-ctrl = <1>;
						ts,touch-det-delay = <2>;
						ts,settling = <2>;
						ts,fraction-z = <7>;
						ts,i-drive = <1>;
					};
				};

				flash@1 {
					compatible = "st,m25p80";
					reg = <1>;
					spi-max-frequency = <12000000>;
					spi-cpol;
					spi-cpha;
					pl022,hierarchy = <0>;
					pl022,interface = <0>;
					pl022,slave-tx-disable;
					pl022,com-mode = <0x2>;
					pl022,rx-level-trig = <0>;
					pl022,tx-level-trig = <0>;
					pl022,ctrl-len = <0x11>;
					pl022,wait-state = <0>;
					pl022,duplex = <0>;
				};
			};

			wdt@ec800620 {
			       status = "okay";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for all SPEAr1310 SoCs
 *
 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
 */

/include/ "spear13xx.dtsi"

/ {
	compatible = "st,spear1310";

	ahb {
		spics: spics@e0700000{
			compatible = "st,spear-spics-gpio";
			reg = <0xe0700000 0x1000>;
			st-spics,peripcfg-reg = <0x3b0>;
			st-spics,sw-enable-bit = <12>;
			st-spics,cs-value-bit = <11>;
			st-spics,cs-enable-mask = <3>;
			st-spics,cs-enable-shift = <8>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		miphy0: miphy@eb800000 {
			compatible = "st,spear1310-miphy";
			reg = <0xeb800000 0x4000>;
			misc = <&misc>;
			phy-id = <0>;
			#phy-cells = <1>;
			status = "disabled";
		};

		miphy1: miphy@eb804000 {
			compatible = "st,spear1310-miphy";
			reg = <0xeb804000 0x4000>;
			misc = <&misc>;
			phy-id = <1>;
			#phy-cells = <1>;
			status = "disabled";
		};

		miphy2: miphy@eb808000 {
			compatible = "st,spear1310-miphy";
			reg = <0xeb808000 0x4000>;
			misc = <&misc>;
			phy-id = <2>;
			#phy-cells = <1>;
			status = "disabled";
		};

		ahci0: ahci@b1000000 {
			compatible = "snps,spear-ahci";
			reg = <0xb1000000 0x10000>;
			interrupts = <0 68 0x4>;
			phys = <&miphy0 0>;
			phy-names = "sata-phy";
			status = "disabled";
		};

		ahci1: ahci@b1800000 {
			compatible = "snps,spear-ahci";
			reg = <0xb1800000 0x10000>;
			interrupts = <0 69 0x4>;
			phys = <&miphy1 0>;
			phy-names = "sata-phy";
			status = "disabled";
		};

		ahci2: ahci@b4000000 {
			compatible = "snps,spear-ahci";
			reg = <0xb4000000 0x10000>;
			interrupts = <0 70 0x4>;
			phys = <&miphy2 0>;
			phy-names = "sata-phy";
			status = "disabled";
		};

		pcie0: pcie@b1000000 {
			compatible = "st,spear1340-pcie", "snps,dw-pcie";
			reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
			reg-names = "dbi", "config";
			interrupts = <0 68 0x4>;
			num-lanes = <1>;
			phys = <&miphy0 1>;
			phy-names = "pcie-phy";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */
				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
			bus-range = <0x00 0xff>;
			status = "disabled";
		};

		pcie1: pcie@b1800000 {
			compatible = "st,spear1340-pcie", "snps,dw-pcie";
			reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
			reg-names = "dbi", "config";
			interrupts = <0 69 0x4>;
			num-lanes = <1>;
			phys = <&miphy1 1>;
			phy-names = "pcie-phy";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x81000000 0 0  0x90020000 0 0x00010000   /* downstream I/O */
				0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
			bus-range = <0x00 0xff>;
			status = "disabled";
		};

		pcie2: pcie@b4000000 {
			compatible = "st,spear1340-pcie", "snps,dw-pcie";
			reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
			reg-names = "dbi", "config";
			interrupts = <0 70 0x4>;
			num-lanes = <1>;
			phys = <&miphy2 1>;
			phy-names = "pcie-phy";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x81000000 0 0	 0xc0020000 0 0x00010000   /* downstream I/O */
				0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
			bus-range = <0x00 0xff>;
			status = "disabled";
		};

		gmac1: eth@5c400000 {
			compatible = "st,spear600-gmac";
			reg = <0x5c400000 0x8000>;
			interrupts = <0 95 0x4>;
			interrupt-names = "macirq";
			phy-mode = "mii";
			status = "disabled";
		};

		gmac2: eth@5c500000 {
			compatible = "st,spear600-gmac";
			reg = <0x5c500000 0x8000>;
			interrupts = <0 96 0x4>;
			interrupt-names = "macirq";
			phy-mode = "mii";
			status = "disabled";
		};

		gmac3: eth@5c600000 {
			compatible = "st,spear600-gmac";
			reg = <0x5c600000 0x8000>;
			interrupts = <0 97 0x4>;
			interrupt-names = "macirq";
			phy-mode = "rmii";
			status = "disabled";
		};

		gmac4: eth@5c700000 {
			compatible = "st,spear600-gmac";
			reg = <0x5c700000 0x8000>;
			interrupts = <0 98 0x4>;
			interrupt-names = "macirq";
			phy-mode = "rgmii";
			status = "disabled";
		};

		pinmux: pinmux@e0700000 {
			compatible = "st,spear1310-pinmux";
			reg = <0xe0700000 0x1000>;
			#gpio-range-cells = <3>;
		};

		apb {
			i2c1: i2c@5cd00000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,designware-i2c";
				reg = <0x5cd00000 0x1000>;
				interrupts = <0 87 0x4>;
				status = "disabled";
			};

			i2c2: i2c@5ce00000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,designware-i2c";
				reg = <0x5ce00000 0x1000>;
				interrupts = <0 88 0x4>;
				status = "disabled";
			};

			i2c3: i2c@5cf00000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,designware-i2c";
				reg = <0x5cf00000 0x1000>;
				interrupts = <0 89 0x4>;
				status = "disabled";
			};

			i2c4: i2c@5d000000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,designware-i2c";
				reg = <0x5d000000 0x1000>;
				interrupts = <0 90 0x4>;
				status = "disabled";
			};

			i2c5: i2c@5d100000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,designware-i2c";
				reg = <0x5d100000 0x1000>;
				interrupts = <0 91 0x4>;
				status = "disabled";
			};

			i2c6: i2c@5d200000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,designware-i2c";
				reg = <0x5d200000 0x1000>;
				interrupts = <0 92 0x4>;
				status = "disabled";
			};

			i2c7: i2c@5d300000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,designware-i2c";
				reg = <0x5d300000 0x1000>;
				interrupts = <0 93 0x4>;
				status = "disabled";
			};

			spi1: spi@5d400000 {
				compatible = "arm,pl022", "arm,primecell";
				reg = <0x5d400000 0x1000>;
				interrupts = <0 99 0x4>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			serial@5c800000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x5c800000 0x1000>;
				interrupts = <0 82 0x4>;
				status = "disabled";
			};

			serial@5c900000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x5c900000 0x1000>;
				interrupts = <0 83 0x4>;
				status = "disabled";
			};

			serial@5ca00000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x5ca00000 0x1000>;
				interrupts = <0 84 0x4>;
				status = "disabled";
			};

			serial@5cb00000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x5cb00000 0x1000>;
				interrupts = <0 85 0x4>;
				status = "disabled";
			};

			serial@5cc00000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x5cc00000 0x1000>;
				interrupts = <0 86 0x4>;
				status = "disabled";
			};

			thermal@e07008c4 {
				st,thermal-flags = <0x7000>;
			};

			gpiopinctrl: gpio@d8400000 {
				compatible = "st,spear-plgpio";
				reg = <0xd8400000 0x1000>;
				interrupts = <0 100 0x4>;
				#interrupt-cells = <1>;
				interrupt-controller;
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinmux 0 0 246>;
				status = "disabled";

				st-plgpio,ngpio = <246>;
				st-plgpio,enb-reg = <0xd0>;
				st-plgpio,wdata-reg = <0x90>;
				st-plgpio,dir-reg = <0xb0>;
				st-plgpio,ie-reg = <0x30>;
				st-plgpio,rdata-reg = <0x70>;
				st-plgpio,mis-reg = <0x10>;
				st-plgpio,eit-reg = <0x50>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for SPEAr1340 Evaluation Baord
 *
 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
 */

/dts-v1/;
/include/ "spear1340.dtsi"

/ {
	model = "ST SPEAr1340 Evaluation Board";
	compatible = "st,spear1340-evb", "st,spear1340";
	#address-cells = <1>;
	#size-cells = <1>;

	memory {
		reg = <0 0x40000000>;
	};

	ahb {
		pinmux@e0700000 {
			pinctrl-names = "default";
			pinctrl-0 = <&state_default>;

			state_default: pinmux {
				pads_as_gpio {
					st,pins = "pads_as_gpio_grp";
					st,function = "pads_as_gpio";
				};
				fsmc {
					st,pins = "fsmc_8bit_grp";
					st,function = "fsmc";
				};
				uart0 {
					st,pins = "uart0_grp";
					st,function = "uart0";
				};
				i2c0 {
					st,pins = "i2c0_grp";
					st,function = "i2c0";
				};
				i2c1 {
					st,pins = "i2c1_grp";
					st,function = "i2c1";
				};
				spdif-in {
					st,pins = "spdif_in_grp";
					st,function = "spdif_in";
				};
				spdif-out {
					st,pins = "spdif_out_grp";
					st,function = "spdif_out";
				};
				ssp0 {
					st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp";
					st,function = "ssp0";
				};
				smi-pmx {
					st,pins = "smi_grp";
					st,function = "smi";
				};
				i2s {
					st,pins = "i2s_in_grp", "i2s_out_grp";
					st,function = "i2s";
				};
				gmac {
					st,pins = "gmii_grp", "rgmii_grp";
					st,function = "gmac";
				};
				cam0 {
					st,pins = "cam0_grp";
					st,function = "cam0";
				};
				cam1 {
					st,pins = "cam1_grp";
					st,function = "cam1";
				};
				cam2 {
					st,pins = "cam2_grp";
					st,function = "cam2";
				};
				cam3 {
					st,pins = "cam3_grp";
					st,function = "cam3";
				};
				cec0 {
					st,pins = "cec0_grp";
					st,function = "cec0";
				};
				cec1 {
					st,pins = "cec1_grp";
					st,function = "cec1";
				};
				sdhci {
					st,pins = "sdhci_grp";
					st,function = "sdhci";
				};
				clcd {
					st,pins = "clcd_grp";
					st,function = "clcd";
				};
				sata {
					st,pins = "sata_grp";
					st,function = "sata";
				};
				pcie {
					st,pins = "pcie_grp";
					st,function = "pcie";
				};

			};
		};

		ahci@b1000000 {
			status = "okay";
		};

		miphy@eb800000 {
			status = "okay";
		};

		dma@ea800000 {
			status = "okay";
		};

		dma@eb000000 {
			status = "okay";
		};

		fsmc: flash@b0000000 {
			status = "okay";

			partition@0 {
				label = "xloader";
				reg = <0x0 0x200000>;
			};
			partition@200000 {
				label = "u-boot";
				reg = <0x200000 0x200000>;
			};
			partition@400000 {
				label = "environment";
				reg = <0x400000 0x100000>;
			};
			partition@500000 {
				label = "dtb";
				reg = <0x500000 0x100000>;
			};
			partition@600000 {
				label = "linux";
				reg = <0x600000 0xC00000>;
			};
			partition@1200000 {
				label = "rootfs";
				reg = <0x1200000 0x0>;
			};
		};

		gmac0: eth@e2000000 {
			phy-mode = "rgmii";
			status = "okay";
		};

		sdhci@b3000000 {
			status = "okay";
		};

		smi: flash@ea000000 {
			status = "okay";
			clock-rate = <50000000>;

			flash@e6000000 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xe6000000 0x800000>;
				st,smi-fast-mode;

				partition@0 {
					label = "xloader";
					reg = <0x0 0x10000>;
				};
				partition@10000 {
					label = "u-boot";
					reg = <0x10000 0x50000>;
				};
				partition@60000 {
					label = "environment";
					reg = <0x60000 0x10000>;
				};
				partition@70000 {
					label = "dtb";
					reg = <0x70000 0x10000>;
				};
				partition@80000 {
					label = "linux";
					reg = <0x80000 0x310000>;
				};
				partition@390000 {
					label = "rootfs";
					reg = <0x390000 0x0>;
				};
			};
		};

		ehci@e4800000 {
			status = "okay";
		};

		gpio_keys {
			compatible = "gpio-keys";
			#address-cells = <1>;
			#size-cells = <0>;

			button@1 {
				label = "wakeup";
				linux,code = <0x100>;
				gpios = <&gpio1 1 0x4>;
				debounce-interval = <20>;
				wakeup-source;
			};
		};

		ehci@e5800000 {
			status = "okay";
		};

		i2s0: i2s-play@b2400000 {
			status = "okay";
		};

		i2s1: i2s-rec@b2000000 {
			status = "okay";
		};

		incodec: dir-hifi {
			compatible = "dummy,dir-hifi";
			status = "okay";
		};

		ohci@e4000000 {
			status = "okay";
		};

		ohci@e5000000 {
			status = "okay";
		};

		outcodec: dit-hifi {
			compatible = "dummy,dit-hifi";
			status = "okay";
		};

		sound {
			compatible = "spear,spear-evb";
			audio-controllers = <&spdif0 &spdif1 &i2s0 &i2s1>;
			audio-codecs = <&incodec &outcodec &sta529 &sta529>;
			codec_dai_name = "dir-hifi", "dit-hifi", "sta529-audio", "sta529-audio";
			stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap";
			dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm";
			nr_controllers = <4>;
		        status = "okay";
		};

		spdif0: spdif-in@d0100000 {
			status = "okay";
		};

		spdif1: spdif-out@d0000000 {
			status = "okay";
		};

		apb {
			adc@e0080000 {
				status = "okay";
			};

			i2s-play@b2400000 {
				status = "okay";
			};

			i2s-rec@b2000000 {
				status = "okay";
			};

			gpio0: gpio@e0600000 {
			       status = "okay";
			};

			gpio1: gpio@e0680000 {
			       status = "okay";
			};

			gpio@e2800000 {
			       status = "okay";
			};

			i2c0: i2c@e0280000 {
			       status = "okay";

				sta529: sta529@1a {
					compatible = "st,sta529";
					reg = <0x1a>;
				};
			};

			i2c1: i2c@b4000000 {
			       status = "okay";

				eeprom0@56 {
					compatible = "st,eeprom";
					reg = <0x56>;
				};

				stmpe801@41 {
					compatible = "st,stmpe801";
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0x41>;
					interrupts = <4 0x4>;
					interrupt-parent = <&gpio0>;
					irq-trigger = <0x2>;

					stmpegpio: stmpe_gpio {
						compatible = "st,stmpe-gpio";
						gpio-controller;
						#gpio-cells = <2>;
					};
				};
			};

			kbd@e0300000 {
				linux,keymap = < 0x00000001
						 0x00010002
						 0x00020003
						 0x00030004
						 0x00040005
						 0x00050006
						 0x00060007
						 0x00070008
						 0x00080009
						 0x0100000a
						 0x0101000c
						 0x0102000d
						 0x0103000e
						 0x0104000f
						 0x01050010
						 0x01060011
						 0x01070012
						 0x01080013
						 0x02000014
						 0x02010015
						 0x02020016
						 0x02030017
						 0x02040018
						 0x02050019
						 0x0206001a
						 0x0207001b
						 0x0208001c
						 0x0300001d
						 0x0301001e
						 0x0302001f
						 0x03030020
						 0x03040021
						 0x03050022
						 0x03060023
						 0x03070024
						 0x03080025
						 0x04000026
						 0x04010027
						 0x04020028
						 0x04030029
						 0x0404002a
						 0x0405002b
						 0x0406002c
						 0x0407002d
						 0x0408002e
						 0x0500002f
						 0x05010030
						 0x05020031
						 0x05030032
						 0x05040033
						 0x05050034
						 0x05060035
						 0x05070036
						 0x05080037
						 0x06000038
						 0x06010039
						 0x0602003a
						 0x0603003b
						 0x0604003c
						 0x0605003d
						 0x0606003e
						 0x0607003f
						 0x06080040
						 0x07000041
						 0x07010042
						 0x07020043
						 0x07030044
						 0x07040045
						 0x07050046
						 0x07060047
						 0x07070048
						 0x07080049
						 0x0800004a
						 0x0801004b
						 0x0802004c
						 0x0803004d
						 0x0804004e
						 0x0805004f
						 0x08060050
						 0x08070051
						 0x08080052 >;
			       autorepeat;
			       st,mode = <0>;
			       suspended_rate = <2000000>;
			       status = "okay";
			};

			rtc@e0580000 {
			       status = "okay";
			};

			serial@e0000000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			serial@b4100000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			spi0: spi@e0100000 {
				status = "okay";
				num-cs = <3>;
				cs-gpios = <&gpiopinctrl 80 0>, <&gpiopinctrl 24 0>,
					   <&gpiopinctrl 85 0>;

				flash@0 {
					compatible = "m25p80";
					reg = <0>;
					spi-max-frequency = <12000000>;
					spi-cpol;
					spi-cpha;
					pl022,hierarchy = <0>;
					pl022,interface = <0>;
					pl022,slave-tx-disable;
					pl022,com-mode = <0x2>;
					pl022,rx-level-trig = <0>;
					pl022,tx-level-trig = <0>;
					pl022,ctrl-len = <0x11>;
					pl022,wait-state = <0>;
					pl022,duplex = <0>;
				};

				stmpe610@1 {
					compatible = "st,stmpe610";
					spi-max-frequency = <1000000>;
					spi-cpha;
					reg = <1>;
					pl022,hierarchy = <0>;
					pl022,interface = <0>;
					pl022,slave-tx-disable;
					pl022,com-mode = <0>;
					pl022,rx-level-trig = <0>;
					pl022,tx-level-trig = <0>;
					pl022,ctrl-len = <0x7>;
					pl022,wait-state = <0>;
					pl022,duplex = <0>;
					interrupts = <100 0>;
					interrupt-parent = <&gpiopinctrl>;
					irq-trigger = <0x2>;
					#address-cells = <1>;
					#size-cells = <0>;

					stmpe_touchscreen {
						compatible = "st,stmpe-ts";
						ts,sample-time = <4>;
						ts,mod-12b = <1>;
						ts,ref-sel = <0>;
						ts,adc-freq = <1>;
						ts,ave-ctrl = <1>;
						ts,touch-det-delay = <2>;
						ts,settling = <2>;
						ts,fraction-z = <7>;
						ts,i-drive = <1>;
					};
				};
			};

			timer@ec800600 {
				status = "okay";
			};

			wdt@ec800620 {
			       status = "okay";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for all SPEAr1340 SoCs
 *
 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
 */

/include/ "spear13xx.dtsi"

/ {
	compatible = "st,spear1340";

	ahb {

		spics: spics@e0700000{
			compatible = "st,spear-spics-gpio";
			reg = <0xe0700000 0x1000>;
			st-spics,peripcfg-reg = <0x42c>;
			st-spics,sw-enable-bit = <21>;
			st-spics,cs-value-bit = <20>;
			st-spics,cs-enable-mask = <3>;
			st-spics,cs-enable-shift = <18>;
			gpio-controller;
			#gpio-cells = <2>;
			status = "disabled";
		};

		miphy0: miphy@eb800000 {
			compatible = "st,spear1340-miphy";
			reg = <0xeb800000 0x4000>;
			misc = <&misc>;
			#phy-cells = <1>;
			status = "disabled";
		};

		ahci0: ahci@b1000000 {
			compatible = "snps,spear-ahci";
			reg = <0xb1000000 0x10000>;
			interrupts = <0 72 0x4>;
			phys = <&miphy0 0>;
			phy-names = "sata-phy";
			status = "disabled";
		};

		pcie0: pcie@b1000000 {
			compatible = "st,spear1340-pcie", "snps,dw-pcie";
			reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
			reg-names = "dbi", "config";
			interrupts = <0 68 0x4>;
			num-lanes = <1>;
			phys = <&miphy0 1>;
			phy-names = "pcie-phy";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */
				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
			bus-range = <0x00 0xff>;
			status = "disabled";
		};

		i2s-play@b2400000 {
			compatible = "snps,designware-i2s";
			reg = <0xb2400000 0x10000>;
			interrupt-names = "play_irq";
			interrupts = <0 98 0x4
				      0 99 0x4>;
			play;
			channel = <8>;
			status = "disabled";
		};

		i2s-rec@b2000000 {
			compatible = "snps,designware-i2s";
			reg = <0xb2000000 0x10000>;
			interrupt-names = "record_irq";
			interrupts = <0 100  0x4
				      0 101 0x4>;
			record;
			channel = <8>;
			status = "disabled";
		};

		pinmux: pinmux@e0700000 {
			compatible = "st,spear1340-pinmux";
			reg = <0xe0700000 0x1000>;
			#gpio-range-cells = <3>;
		};

		pwm: pwm@e0180000 {
			compatible = "st,spear13xx-pwm";
			reg = <0xe0180000 0x1000>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		spdif-in@d0100000 {
			compatible = "st,spdif-in";
			reg = < 0xd0100000 0x20000
				0xd0110000 0x10000 >;
			interrupts = <0 84 0x4>;
			status = "disabled";
		};

		spdif-out@d0000000 {
			compatible = "st,spdif-out";
			reg = <0xd0000000 0x20000>;
			interrupts = <0 85 0x4>;
			status = "disabled";
		};

		spi1: spi@5d400000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x5d400000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 99 0x4>;
			status = "disabled";
		};

		apb {
			i2c1: i2c@b4000000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,designware-i2c";
				reg = <0xb4000000 0x1000>;
				interrupts = <0 104 0x4>;
				write-16bit;
				status = "disabled";
			};

			serial@b4100000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0xb4100000 0x1000>;
				interrupts = <0 105 0x4>;
				status = "disabled";
				dmas = <&dwdma0 13 0 1>,
					<&dwdma0 12 1 0>;
				dma-names = "rx", "tx";
			};

			thermal@e07008c4 {
				st,thermal-flags = <0x2a00>;
			};

			gpiopinctrl: gpio@e2800000 {
				compatible = "st,spear-plgpio";
				reg = <0xe2800000 0x1000>;
				interrupts = <0 107 0x4>;
				#interrupt-cells = <1>;
				interrupt-controller;
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinmux 0 0 252>;
				status = "disabled";

				st-plgpio,ngpio = <250>;
				st-plgpio,wdata-reg = <0x40>;
				st-plgpio,dir-reg = <0x00>;
				st-plgpio,ie-reg = <0x80>;
				st-plgpio,rdata-reg = <0x20>;
				st-plgpio,mis-reg = <0xa0>;
				st-plgpio,eit-reg = <0x60>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for all SPEAr13xx SoCs
 *
 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};
	};

	gic: interrupt-controller@ec801000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = < 0xec801000 0x1000 >,
		      < 0xec800100 0x0100 >;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 6 0x04
			      0 7 0x04>;
	};

	L2: cache-controller {
		    compatible = "arm,pl310-cache";
		    reg = <0xed000000 0x1000>;
		    cache-unified;
		    cache-level = <2>;
	};

	memory {
		name = "memory";
		device_type = "memory";
		reg = <0 0x40000000>;
	};

	chosen {
		bootargs = "console=ttyAMA0,115200";
	};

	cpufreq {
		compatible = "st,cpufreq-spear";
		cpufreq_tbl = < 166000
				200000
				250000
				300000
				400000
				500000
				600000 >;
		status = "disabled";
	};

	ahb {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0x50000000 0x50000000 0x10000000
			  0x80000000 0x80000000 0x20000000
			  0xb0000000 0xb0000000 0x22000000
			  0xd8000000 0xd8000000 0x01000000
			  0xe0000000 0xe0000000 0x10000000>;

		sdhci@b3000000 {
			compatible = "st,sdhci-spear";
			reg = <0xb3000000 0x100>;
			interrupts = <0 28 0x4>;
			status = "disabled";
		};

		cf@b2800000 {
			compatible = "arasan,cf-spear1340";
			reg = <0xb2800000 0x1000>;
			interrupts = <0 29 0x4>;
			status = "disabled";
			dmas = <&dwdma0 0 0 0>;
			dma-names = "data";
		};

		dwdma0: dma@ea800000 {
			compatible = "snps,dma-spear1340";
			reg = <0xea800000 0x1000>;
			interrupts = <0 19 0x4>;
			status = "disabled";

			dma-channels = <8>;
			#dma-cells = <3>;
			dma-requests = <32>;
			chan_allocation_order = <1>;
			chan_priority = <1>;
			block_size = <0xfff>;
			dma-masters = <2>;
			data-width = <8 8>;
			multi-block = <1 1 1 1 1 1 1 1>;
		};

		dma@eb000000 {
			compatible = "snps,dma-spear1340";
			reg = <0xeb000000 0x1000>;
			interrupts = <0 59 0x4>;
			status = "disabled";

			dma-requests = <32>;
			dma-channels = <8>;
			dma-masters = <2>;
			#dma-cells = <3>;
			chan_allocation_order = <1>;
			chan_priority = <1>;
			block_size = <0xfff>;
			data-width = <8 8>;
			multi-block = <1 1 1 1 1 1 1 1>;
		};

		fsmc: flash@b0000000 {
			compatible = "st,spear600-fsmc-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0xb0000000 0x1000	/* FSMC Register*/
			       0xb0800000 0x0010	/* NAND Base DATA */
			       0xb0820000 0x0010	/* NAND Base ADDR */
			       0xb0810000 0x0010>;	/* NAND Base CMD */
			reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
			interrupts = <0 20 0x4
				      0 21 0x4
				      0 22 0x4
				      0 23 0x4>;
			st,mode = <2>;
			status = "disabled";
		};

		gmac0: eth@e2000000 {
			compatible = "st,spear600-gmac";
			reg = <0xe2000000 0x8000>;
			interrupts = <0 33 0x4
				      0 34 0x4>;
			interrupt-names = "macirq", "eth_wake_irq";
			status = "disabled";
		};

		pcm {
			compatible = "st,pcm-audio";
			#address-cells = <0>;
			#size-cells = <0>;
			status = "disabled";
		};

		smi: flash@ea000000 {
			compatible = "st,spear600-smi";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0xea000000 0x1000>;
			interrupts = <0 30 0x4>;
			status = "disabled";
		};

		ehci@e4800000 {
			compatible = "st,spear600-ehci", "usb-ehci";
			reg = <0xe4800000 0x1000>;
			interrupts = <0 64 0x4>;
			usbh0_id = <0>;
			status = "disabled";
		};

		ehci@e5800000 {
			compatible = "st,spear600-ehci", "usb-ehci";
			reg = <0xe5800000 0x1000>;
			interrupts = <0 66 0x4>;
			usbh1_id = <1>;
			status = "disabled";
		};

		ohci@e4000000 {
			compatible = "st,spear600-ohci", "usb-ohci";
			reg = <0xe4000000 0x1000>;
			interrupts = <0 65 0x4>;
			usbh0_id = <0>;
			status = "disabled";
		};

		ohci@e5000000 {
			compatible = "st,spear600-ohci", "usb-ohci";
			reg = <0xe5000000 0x1000>;
			interrupts = <0 67 0x4>;
			usbh1_id = <1>;
			status = "disabled";
		};

		apb {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0x50000000 0x50000000 0x10000000
				  0xb0000000 0xb0000000 0x10000000
				  0xd0000000 0xd0000000 0x02000000
				  0xd8000000 0xd8000000 0x01000000
				  0xe0000000 0xe0000000 0x10000000>;

			misc: syscon@e0700000 {
				compatible = "st,spear1340-misc", "syscon";
				reg = <0xe0700000 0x1000>;
			};

			gpio0: gpio@e0600000 {
				compatible = "arm,pl061", "arm,primecell";
				reg = <0xe0600000 0x1000>;
				interrupts = <0 24 0x4>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				status = "disabled";
			};

			gpio1: gpio@e0680000 {
				compatible = "arm,pl061", "arm,primecell";
				reg = <0xe0680000 0x1000>;
				interrupts = <0 25 0x4>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				status = "disabled";
			};

			kbd@e0300000 {
				compatible = "st,spear300-kbd";
				reg = <0xe0300000 0x1000>;
				interrupts = <0 52 0x4>;
				status = "disabled";
			};

			i2c0: i2c@e0280000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "snps,designware-i2c";
				reg = <0xe0280000 0x1000>;
				interrupts = <0 41 0x4>;
				status = "disabled";
			};

			i2s@e0180000 {
				compatible = "st,designware-i2s";
				reg = <0xe0180000 0x1000>;
				interrupt-names = "play_irq", "record_irq";
				interrupts = <0 10 0x4
					      0 11 0x4 >;
				status = "disabled";
			};

			i2s@e0200000 {
				compatible = "st,designware-i2s";
				reg = <0xe0200000 0x1000>;
				interrupt-names = "play_irq", "record_irq";
				interrupts = <0 26 0x4
					      0 53 0x4>;
				status = "disabled";
			};

			spi0: spi@e0100000 {
				compatible = "arm,pl022", "arm,primecell";
				reg = <0xe0100000 0x1000>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <0 31 0x4>;
				status = "disabled";
				dmas = <&dwdma0 5 0 0>,
					<&dwdma0 4 0 0>;
				dma-names = "rx", "tx";
			};

			rtc@e0580000 {
				compatible = "st,spear600-rtc";
				reg = <0xe0580000 0x1000>;
				interrupts = <0 36 0x4>;
				status = "disabled";
			};

			serial@e0000000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0xe0000000 0x1000>;
				interrupts = <0 35 0x4>;
				status = "disabled";
			};

			adc@e0080000 {
				compatible = "st,spear600-adc";
				reg = <0xe0080000 0x1000>;
				interrupts = <0 12 0x4>;
				status = "disabled";
			};

			timer@e0380000 {
				compatible = "st,spear-timer";
				reg = <0xe0380000 0x400>;
				interrupts = <0 37 0x4>;
			};

			timer@ec800600 {
				compatible = "arm,cortex-a9-twd-timer";
				reg = <0xec800600 0x20>;
				interrupts = <1 13 0x4>;
				status = "disabled";
			};

			wdt@ec800620 {
				compatible = "arm,cortex-a9-twd-wdt";
				reg = <0xec800620 0x20>;
				status = "disabled";
			};

			thermal@e07008c4 {
				compatible = "st,thermal-spear1340";
				reg = <0xe07008c4 0x4>;
				thermal_flags = <0x7000>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for SPEAr300 Evaluation Baord
 *
 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
 */

/dts-v1/;
/include/ "spear300.dtsi"

/ {
	model = "ST SPEAr300 Evaluation Board";
	compatible = "st,spear300-evb", "st,spear300";
	#address-cells = <1>;
	#size-cells = <1>;

	memory {
		reg = <0 0x40000000>;
	};

	ahb {
		pinmux@99000000 {
			st,pinmux-mode = <2>;
			pinctrl-names = "default";
			pinctrl-0 = <&state_default>;

			state_default: pinmux {
				i2c0 {
					st,pins = "i2c0_grp";
					st,function = "i2c0";
				};
				ssp0 {
					st,pins = "ssp0_grp";
					st,function = "ssp0";
				};
				mii0 {
					st,pins = "mii0_grp";
					st,function = "mii0";
				};
				uart0 {
					st,pins = "uart0_grp";
					st,function = "uart0";
				};
				clcd {
					st,pins = "clcd_pfmode_grp";
					st,function = "clcd";
				};
				sdhci {
					st,pins = "sdhci_4bit_grp";
					st,function = "sdhci";
				};
				gpio1 {
					st,pins = "gpio1_4_to_7_grp",
						"gpio1_0_to_3_grp";
					st,function = "gpio1";
				};
			};
		};

		clcd@60000000 {
			status = "okay";
		};

		dma@fc400000 {
			status = "okay";
		};

		fsmc: flash@94000000 {
			status = "okay";
		};

		gmac: eth@e0800000 {
			status = "okay";
		};

		sdhci@70000000 {
			cd-gpios = <&gpio1 0 0>;
			status = "okay";
		};

		smi: flash@fc000000 {
			status = "okay";
			clock-rate = <50000000>;

			flash@f8000000 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0xf8000000 0x800000>;
				st,smi-fast-mode;

				partition@0 {
					label = "xloader";
					reg = <0x0 0x10000>;
				};
				partition@10000 {
					label = "u-boot";
					reg = <0x10000 0x50000>;
				};
				partition@60000 {
					label = "environment";
					reg = <0x60000 0x10000>;
				};
				partition@70000 {
					label = "dtb";
					reg = <0x70000 0x10000>;
				};
				partition@80000 {
					label = "linux";
					reg = <0x80000 0x310000>;
				};
				partition@390000 {
					label = "rootfs";
					reg = <0x390000 0x0>;
				};
			};
		};

		spi0: spi@d0100000 {
			status = "okay";
		};

		ehci@e1800000 {
			status = "okay";
		};

		ohci@e1900000 {
			status = "okay";
		};

		ohci@e2100000 {
			status = "okay";
		};

		apb {
			gpio0: gpio@fc980000 {
			       status = "okay";
			};

			gpio1: gpio@a9000000 {
			       status = "okay";
			};

			i2c0: i2c@d0180000 {
			       status = "okay";
			};

			kbd@a0000000 {
				linux,keymap = < 0x00000001
						 0x00010002
						 0x00020003
						 0x00030004
						 0x00040005
						 0x00050006
						 0x00060007
						 0x00070008
						 0x00080009
						 0x0100000a
						 0x0101000c
						 0x0102000d
						 0x0103000e
						 0x0104000f
						 0x01050010
						 0x01060011
						 0x01070012
						 0x01080013
						 0x02000014
						 0x02010015
						 0x02020016
						 0x02030017
						 0x02040018
						 0x02050019
						 0x0206001a
						 0x0207001b
						 0x0208001c
						 0x0300001d
						 0x0301001e
						 0x0302001f
						 0x03030020
						 0x03040021
						 0x03050022
						 0x03060023
						 0x03070024
						 0x03080025
						 0x04000026
						 0x04010027
						 0x04020028
						 0x04030029
						 0x0404002a
						 0x0405002b
						 0x0406002c
						 0x0407002d
						 0x0408002e
						 0x0500002f
						 0x05010030
						 0x05020031
						 0x05030032
						 0x05040033
						 0x05050034
						 0x05060035
						 0x05070036
						 0x05080037
						 0x06000038
						 0x06010039
						 0x0602003a
						 0x0603003b
						 0x0604003c
						 0x0605003d
						 0x0606003e
						 0x0607003f
						 0x06080040
						 0x07000041
						 0x07010042
						 0x07020043
						 0x07030044
						 0x07040045
						 0x07050046
						 0x07060047
						 0x07070048
						 0x07080049
						 0x0800004a
						 0x0801004b
						 0x0802004c
						 0x0803004d
						 0x0804004e
						 0x0805004f
						 0x08060050
						 0x08070051
						 0x08080052 >;
			       autorepeat;
			       st,mode = <0>;
			       status = "okay";
			};

			rtc@fc900000 {
			       status = "okay";
			};

			serial@d0000000 {
			       status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <>;
			};

			wdt@fc880000 {
			       status = "okay";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * DTS file for SPEAr300 SoC
 *
 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
 */

/include/ "spear3xx.dtsi"

/ {
	ahb {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0x60000000 0x60000000 0x50000000
			  0xd0000000 0xd0000000 0x30000000>;

		pinmux@99000000 {
			compatible = "st,spear300-pinmux";
			reg = <0x99000000 0x1000>;
		};

		clcd@60000000 {
			compatible = "arm,pl110", "arm,primecell";
			reg = <0x60000000 0x1000>;
			interrupts = <30>;
			status = "disabled";
		};

		fsmc: flash@94000000 {
			compatible = "st,spear600-fsmc-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x94000000 0x1000	/* FSMC Register */
			       0x80000000 0x0010	/* NAND Base DATA */
			       0x80020000 0x0010	/* NAND Base ADDR */
			       0x80010000 0x0010>;	/* NAND Base CMD */
			reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
			status = "disabled";
		};

		sdhci@70000000 {
			compatible = "st,sdhci-spear";
			reg = <0x70000000 0x100>;
			interrupts = <1>;
			status = "disabled";
		};

		shirq: interrupt-controller@0x50000000 {
			compatible = "st,spear300-shirq";
			reg = <0x50000000 0x1000>;
			interrupts = <28>;
			#interrupt-cells = <1>;
			interrupt-controller;
		};

		apb {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0xa0000000 0xa0000000 0x10000000
				  0xd0000000 0xd0000000 0x30000000>;

			gpio1: gpio@a9000000 {
				#gpio-cells = <2>;
				compatible = "arm,pl061", "arm,primecell";
				gpio-controller;
				reg = <0xa9000000 0x1000>;
				interrupts = <8>;
				interrupt-parent = <&shirq>;
				status = "disabled";
			};

			kbd@a0000000 {
				compatible = "st,spear300-kbd";
				reg = <0xa0000000 0x1000>;
				interrupts = <7>;
				interrupt-parent = <&shirq>;
				status = "disabled";
			};
		};
	};
};