code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC
 *
 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
 *
 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
 */

#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/mfd/atmel-flexcom.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Microchip SAM9X60 SoC";
	compatible = "microchip,sam9x60";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &dbgu;
		gpio0 = &pioA;
		gpio1 = &pioB;
		gpio2 = &pioC;
		gpio3 = &pioD;
		tcb0 = &tcb0;
		tcb1 = &tcb1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,arm926ej-s";
			device_type = "cpu";
			reg = <0>;
		};
	};

	memory@20000000 {
		device_type = "memory";
		reg = <0x20000000 0x10000000>;
	};

	clocks {
		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};

		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};
	};

	sram: sram@300000 {
		compatible = "mmio-sram";
		reg = <0x00300000 0x100000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x00300000 0x100000>;
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		usb0: gadget@500000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "microchip,sam9x60-udc";
			reg = <0x00500000 0x100000
				0xf803c000 0x400>;
			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
			clock-names = "pclk", "hclk";
			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
			assigned-clock-rates = <480000000>;
			status = "disabled";
		};

		usb1: ohci@600000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00600000 0x100000>;
			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
			clock-names = "ohci_clk", "hclk", "uhpck";
			status = "disabled";
		};

		usb2: ehci@700000 {
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00700000 0x100000>;
			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
			clock-names = "usb_clk", "ehci_clk";
			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
			assigned-clock-rates = <480000000>;
			status = "disabled";
		};

		ebi: ebi@10000000 {
			compatible = "microchip,sam9x60-ebi";
			#address-cells = <2>;
			#size-cells = <1>;
			atmel,smc = <&smc>;
			microchip,sfr = <&sfr>;
			reg = <0x10000000 0x60000000>;
			ranges = <0x0 0x0 0x10000000 0x10000000
				  0x1 0x0 0x20000000 0x10000000
				  0x2 0x0 0x30000000 0x10000000
				  0x3 0x0 0x40000000 0x10000000
				  0x4 0x0 0x50000000 0x10000000
				  0x5 0x0 0x60000000 0x10000000>;
			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
			status = "disabled";

			nand_controller: nand-controller {
				compatible = "microchip,sam9x60-nand-controller";
				ecc-engine = <&pmecc>;
				#address-cells = <2>;
				#size-cells = <1>;
				ranges;
				status = "disabled";
			};
		};

		sdmmc0: sdio-host@80000000 {
			compatible = "microchip,sam9x60-sdhci";
			reg = <0x80000000 0x300>;
			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
			clock-names = "hclock", "multclk";
			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
			assigned-clock-rates = <100000000>;
			status = "disabled";
		};

		sdmmc1: sdio-host@90000000 {
			compatible = "microchip,sam9x60-sdhci";
			reg = <0x90000000 0x300>;
			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
			clock-names = "hclock", "multclk";
			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
			assigned-clock-rates = <100000000>;
			status = "disabled";
		};

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			flx4: flexcom@f0000000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf0000000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf0000000 0x800>;
				status = "disabled";
			};

			flx5: flexcom@f0004000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf0004000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf0004000 0x800>;
				status = "disabled";
			};

			dma0: dma-controller@f0008000 {
				compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
				reg = <0xf0008000 0x1000>;
				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
				#dma-cells = <1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
				clock-names = "dma_clk";
			};

			ssc: ssc@f0010000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xf0010000 0x4000>;
				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(38))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(39))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
				clock-names = "pclk";
				status = "disabled";
			};

			qspi: spi@f0014000 {
				compatible = "microchip,sam9x60-qspi";
				reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
				reg-names = "qspi_base", "qspi_mmap";
				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(26))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(27))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>;
				clock-names = "pclk", "qspick";
				atmel,pmc = <&pmc>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2s: i2s@f001c000 {
				compatible = "microchip,sam9x60-i2smcc";
				reg = <0xf001c000 0x100>;
				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(36))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(37))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
				clock-names = "pclk", "gclk";
				status = "disabled";
			};

			flx11: flexcom@f0020000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf0020000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf0020000 0x800>;
				status = "disabled";
			};

			flx12: flexcom@f0024000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf0024000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf0024000 0x800>;
				status = "disabled";
			};

			pit64b: timer@f0028000 {
				compatible = "microchip,sam9x60-pit64b";
				reg = <0xf0028000 0x100>;
				interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
				clock-names = "pclk", "gclk";
			};

			sha: crypto@f002c000 {
				compatible = "atmel,at91sam9g46-sha";
				reg = <0xf002c000 0x100>;
				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(34))>;
				dma-names = "tx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
				clock-names = "sha_clk";
			};

			trng: trng@f0030000 {
				compatible = "microchip,sam9x60-trng";
				reg = <0xf0030000 0x100>;
				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
			};

			aes: crypto@f0034000 {
				compatible = "atmel,at91sam9g46-aes";
				reg = <0xf0034000 0x100>;
				interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(32))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(33))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
				clock-names = "aes_clk";
			};

			tdes: crypto@f0038000 {
				compatible = "atmel,at91sam9g46-tdes";
				reg = <0xf0038000 0x100>;
				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(31))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(30))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
				clock-names = "tdes_clk";
			};

			classd: classd@f003c000 {
				compatible = "atmel,sama5d2-classd";
				reg = <0xf003c000 0x100>;
				interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(35))>;
				dma-names = "tx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
				clock-names = "pclk", "gclk";
				status = "disabled";
			};

			can0: can@f8000000 {
				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
				reg = <0xf8000000 0x300>;
				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
				clock-names = "can_clk";
				status = "disabled";
			};

			can1: can@f8004000 {
				compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can";
				reg = <0xf8004000 0x300>;
				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
				clock-names = "can_clk";
				status = "disabled";
			};

			tcb0: timer@f8008000 {
				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0xf8008000 0x100>;
				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
				clock-names = "t0_clk", "slow_clk";
			};

			tcb1: timer@f800c000 {
				compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0xf800c000 0x100>;
				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>;
				clock-names = "t0_clk", "slow_clk";
			};

			flx6: flexcom@f8010000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf8010000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf8010000 0x800>;
				status = "disabled";
			};

			flx7: flexcom@f8014000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf8014000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf8014000 0x800>;
				status = "disabled";
			};

			flx8: flexcom@f8018000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf8018000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf8018000 0x800>;
				status = "disabled";
			};

			flx0: flexcom@f801c000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf801c000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf801c000 0x800>;
				status = "disabled";
			};

			flx1: flexcom@f8020000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf8020000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf8020000 0x800>;
				status = "disabled";
			};

			flx2: flexcom@f8024000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf8024000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf8024000 0x800>;
				status = "disabled";
			};

			flx3: flexcom@f8028000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf8028000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf8028000 0x800>;
				status = "disabled";
			};

			macb0: ethernet@f802c000 {
				compatible = "cdns,sam9x60-macb", "cdns,macb";
				reg = <0xf802c000 0x1000>;
				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};

			macb1: ethernet@f8030000 {
				compatible = "cdns,sam9x60-macb", "cdns,macb";
				reg = <0xf8030000 0x1000>;
				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};

			pwm0: pwm@f8034000 {
				compatible = "microchip,sam9x60-pwm";
				reg = <0xf8034000 0x300>;
				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
				#pwm-cells = <3>;
				status = "disabled";
			};

			hlcdc: hlcdc@f8038000 {
				compatible = "microchip,sam9x60-hlcdc";
				reg = <0xf8038000 0x4000>;
				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>;
				clock-names = "periph_clk","sys_clk", "slow_clk";
				assigned-clocks = <&pmc PMC_TYPE_GCK 25>;
				assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>;
				status = "disabled";

				hlcdc-display-controller {
					compatible = "atmel,hlcdc-display-controller";
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						#address-cells = <1>;
						#size-cells = <0>;
						reg = <0>;
					};
				};

				hlcdc_pwm: hlcdc-pwm {
					compatible = "atmel,hlcdc-pwm";
					#pwm-cells = <3>;
				};
			};

			flx9: flexcom@f8040000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf8040000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf8040000 0x800>;
				status = "disabled";
			};

			flx10: flexcom@f8044000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf8044000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf8044000 0x800>;
				status = "disabled";
			};

			isi: isi@f8048000 {
				compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi";
				reg = <0xf8048000 0x100>;
				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
				clock-names = "isi_clk";
				status = "disabled";
				port {
					#address-cells = <1>;
					#size-cells = <0>;
				};
			};

			adc: adc@f804c000 {
				compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc";
				reg = <0xf804c000 0x100>;
				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
				clock-names = "adc_clk";
				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>;
				dma-names = "rx";
				atmel,min-sample-rate-hz = <200000>;
				atmel,max-sample-rate-hz = <20000000>;
				atmel,startup-time-ms = <4>;
				atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
				#io-channel-cells = <1>;
				status = "disabled";
			};

			sfr: sfr@f8050000 {
				compatible = "microchip,sam9x60-sfr", "syscon";
				reg = <0xf8050000 0x100>;
			};

			matrix: matrix@ffffde00 {
				compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
				reg = <0xffffde00 0x200>;
			};

			pmecc: ecc-engine@ffffe000 {
				compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
				reg = <0xffffe000 0x300>,
				      <0xffffe600 0x100>;
			};

			mpddrc: mpddrc@ffffe800 {
				compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
				reg = <0xffffe800 0x200>;
				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
				clock-names = "ddrck", "mpddr";
			};

			smc: smc@ffffea00 {
				compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
				reg = <0xffffea00 0x100>;
			};

			aic: interrupt-controller@fffff100 {
				compatible = "microchip,sam9x60-aic";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0xfffff100 0x100>;
				atmel,external-irqs = <31>;
			};

			dbgu: serial@fffff200 {
				compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
				reg = <0xfffff200 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(28))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(29))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
				clock-names = "usart";
				status = "disabled";
			};

			pinctrl: pinctrl@fffff400 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
				ranges = <0xfffff400 0xfffff400 0x800>;

				/* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */
				atmel,mux-mask = <
						 /*	A	B	C	*/
						 0xffffffff 0xffe03fff 0xef00019d	/* pioA */
						 0x03ffffff 0x02fc7e7f 0x00780000	/* pioB */
						 0xffffffff 0xffffffff 0xf83fffff	/* pioC */
						 0x003fffff 0x003f8000 0x00000000	/* pioD */
						 >;

				pioA: gpio@fffff400 {
					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff400 0x200>;
					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
				};

				pioB: gpio@fffff600 {
					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff600 0x200>;
					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					#gpio-lines = <26>;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
				};

				pioC: gpio@fffff800 {
					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff800 0x200>;
					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
				};

				pioD: gpio@fffffa00 {
					compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffffa00 0x200>;
					interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					#gpio-lines = <22>;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
				};
			};

			pmc: pmc@fffffc00 {
				compatible = "microchip,sam9x60-pmc", "syscon";
				reg = <0xfffffc00 0x200>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				#clock-cells = <2>;
				clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
				clock-names = "td_slck", "md_slck", "main_xtal";
			};

			reset_controller: reset-controller@fffffe00 {
				compatible = "microchip,sam9x60-rstc";
				reg = <0xfffffe00 0x10>;
				clocks = <&clk32k 0>;
			};

			shutdown_controller: shdwc@fffffe10 {
				compatible = "microchip,sam9x60-shdwc";
				reg = <0xfffffe10 0x10>;
				clocks = <&clk32k 0>;
				#address-cells = <1>;
				#size-cells = <0>;
				atmel,wakeup-rtc-timer;
				atmel,wakeup-rtt-timer;
				status = "disabled";
			};

			rtt: rtc@fffffe20 {
				compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
				reg = <0xfffffe20 0x20>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k 0>;
			};

			pit: timer@fffffe40 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xfffffe40 0x10>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
			};

			clk32k: sckc@fffffe50 {
				compatible = "microchip,sam9x60-sckc";
				reg = <0xfffffe50 0x4>;
				clocks = <&slow_xtal>;
				#clock-cells = <1>;
			};

			gpbr: syscon@fffffe60 {
				compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
				reg = <0xfffffe60 0x10>;
			};

			rtc: rtc@fffffea8 {
				compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc";
				reg = <0xfffffea8 0x100>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k 0>;
			};

			watchdog: watchdog@ffffff80 {
				compatible = "microchip,sam9x60-wdt";
				reg = <0xffffff80 0x24>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k 0>;
				status = "disabled";
			};
		};
	};
};


code:
/* SPDX-License-Identifier: GPL-2.0 */
#define PINMUX_PIN(no, func, ioset) \
(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20))

#define PIN_PA0				0
#define PIN_PA0__GPIO			PINMUX_PIN(PIN_PA0, 0, 0)
#define PIN_PA0__SDMMC0_CK		PINMUX_PIN(PIN_PA0, 1, 1)
#define PIN_PA0__QSPI0_SCK		PINMUX_PIN(PIN_PA0, 2, 1)
#define PIN_PA0__D0			PINMUX_PIN(PIN_PA0, 6, 2)
#define PIN_PA1				1
#define PIN_PA1__GPIO			PINMUX_PIN(PIN_PA1, 0, 0)
#define PIN_PA1__SDMMC0_CMD		PINMUX_PIN(PIN_PA1, 1, 1)
#define PIN_PA1__QSPI0_CS		PINMUX_PIN(PIN_PA1, 2, 1)
#define PIN_PA1__D1			PINMUX_PIN(PIN_PA1, 6, 2)
#define PIN_PA2				2
#define PIN_PA2__GPIO			PINMUX_PIN(PIN_PA2, 0, 0)
#define PIN_PA2__SDMMC0_DAT0		PINMUX_PIN(PIN_PA2, 1, 1)
#define PIN_PA2__QSPI0_IO0		PINMUX_PIN(PIN_PA2, 2, 1)
#define PIN_PA2__D2			PINMUX_PIN(PIN_PA2, 6, 2)
#define PIN_PA3				3
#define PIN_PA3__GPIO			PINMUX_PIN(PIN_PA3, 0, 0)
#define PIN_PA3__SDMMC0_DAT1		PINMUX_PIN(PIN_PA3, 1, 1)
#define PIN_PA3__QSPI0_IO1		PINMUX_PIN(PIN_PA3, 2, 1)
#define PIN_PA3__D3			PINMUX_PIN(PIN_PA3, 6, 2)
#define PIN_PA4				4
#define PIN_PA4__GPIO			PINMUX_PIN(PIN_PA4, 0, 0)
#define PIN_PA4__SDMMC0_DAT2		PINMUX_PIN(PIN_PA4, 1, 1)
#define PIN_PA4__QSPI0_IO2		PINMUX_PIN(PIN_PA4, 2, 1)
#define PIN_PA4__D4			PINMUX_PIN(PIN_PA4, 6, 2)
#define PIN_PA5				5
#define PIN_PA5__GPIO			PINMUX_PIN(PIN_PA5, 0, 0)
#define PIN_PA5__SDMMC0_DAT3		PINMUX_PIN(PIN_PA5, 1, 1)
#define PIN_PA5__QSPI0_IO3		PINMUX_PIN(PIN_PA5, 2, 1)
#define PIN_PA5__D5			PINMUX_PIN(PIN_PA5, 6, 2)
#define PIN_PA6				6
#define PIN_PA6__GPIO			PINMUX_PIN(PIN_PA6, 0, 0)
#define PIN_PA6__SDMMC0_DAT4		PINMUX_PIN(PIN_PA6, 1, 1)
#define PIN_PA6__QSPI1_SCK		PINMUX_PIN(PIN_PA6, 2, 1)
#define PIN_PA6__TIOA5			PINMUX_PIN(PIN_PA6, 4, 1)
#define PIN_PA6__FLEXCOM2_IO0		PINMUX_PIN(PIN_PA6, 5, 1)
#define PIN_PA6__D6			PINMUX_PIN(PIN_PA6, 6, 2)
#define PIN_PA7				7
#define PIN_PA7__GPIO			PINMUX_PIN(PIN_PA7, 0, 0)
#define PIN_PA7__SDMMC0_DAT5		PINMUX_PIN(PIN_PA7, 1, 1)
#define PIN_PA7__QSPI1_IO0		PINMUX_PIN(PIN_PA7, 2, 1)
#define PIN_PA7__TIOB5			PINMUX_PIN(PIN_PA7, 4, 1)
#define PIN_PA7__FLEXCOM2_IO1		PINMUX_PIN(PIN_PA7, 5, 1)
#define PIN_PA7__D7			PINMUX_PIN(PIN_PA7, 6, 2)
#define PIN_PA8				8
#define PIN_PA8__GPIO			PINMUX_PIN(PIN_PA8, 0, 0)
#define PIN_PA8__SDMMC0_DAT6		PINMUX_PIN(PIN_PA8, 1, 1)
#define PIN_PA8__QSPI1_IO1		PINMUX_PIN(PIN_PA8, 2, 1)
#define PIN_PA8__TCLK5			PINMUX_PIN(PIN_PA8, 4, 1)
#define PIN_PA8__FLEXCOM2_IO2		PINMUX_PIN(PIN_PA8, 5, 1)
#define PIN_PA8__NWE_NANDWE		PINMUX_PIN(PIN_PA8, 6, 2)
#define PIN_PA9				9
#define PIN_PA9__GPIO			PINMUX_PIN(PIN_PA9, 0, 0)
#define PIN_PA9__SDMMC0_DAT7		PINMUX_PIN(PIN_PA9, 1, 1)
#define PIN_PA9__QSPI1_IO2		PINMUX_PIN(PIN_PA9, 2, 1)
#define PIN_PA9__TIOA4			PINMUX_PIN(PIN_PA9, 4, 1)
#define PIN_PA9__FLEXCOM2_IO3		PINMUX_PIN(PIN_PA9, 5, 1)
#define PIN_PA9__NCS3			PINMUX_PIN(PIN_PA9, 6, 2)
#define PIN_PA10			10
#define PIN_PA10__GPIO			PINMUX_PIN(PIN_PA10, 0, 0)
#define PIN_PA10__SDMMC0_RSTN		PINMUX_PIN(PIN_PA10, 1, 1)
#define PIN_PA10__QSPI1_IO3		PINMUX_PIN(PIN_PA10, 2, 1)
#define PIN_PA10__TIOB4			PINMUX_PIN(PIN_PA10, 4, 1)
#define PIN_PA10__FLEXCOM2_IO4		PINMUX_PIN(PIN_PA10, 5, 1)
#define PIN_PA10__A21_NANDALE		PINMUX_PIN(PIN_PA10, 6, 2)
#define PIN_PA11			11
#define PIN_PA11__GPIO			PINMUX_PIN(PIN_PA11, 0, 0)
#define PIN_PA11__SDMMC0_VDDSEL		PINMUX_PIN(PIN_PA11, 1, 1)
#define PIN_PA11__QSPI1_CS		PINMUX_PIN(PIN_PA11, 2, 1)
#define PIN_PA11__TCLK4			PINMUX_PIN(PIN_PA11, 4, 1)
#define PIN_PA11__A22_NANDCLE		PINMUX_PIN(PIN_PA11, 6, 2)
#define PIN_PA12			12
#define PIN_PA12__GPIO			PINMUX_PIN(PIN_PA12, 0, 0)
#define PIN_PA12__SDMMC0_WP		PINMUX_PIN(PIN_PA12, 1, 1)
#define PIN_PA12__IRQ			PINMUX_PIN(PIN_PA12, 2, 1)
#define PIN_PA12__NRD_NANDOE		PINMUX_PIN(PIN_PA12, 6, 2)
#define PIN_PA13			13
#define PIN_PA13__GPIO			PINMUX_PIN(PIN_PA13, 0, 0)
#define PIN_PA13__SDMMC0_CD		PINMUX_PIN(PIN_PA13, 1, 1)
#define PIN_PA13__FLEXCOM3_IO1		PINMUX_PIN(PIN_PA13, 5, 1)
#define PIN_PA13__D8			PINMUX_PIN(PIN_PA13, 6, 2)
#define PIN_PA14			14
#define PIN_PA14__GPIO			PINMUX_PIN(PIN_PA14, 0, 0)
#define PIN_PA14__SPI0_SPCK		PINMUX_PIN(PIN_PA14, 1, 1)
#define PIN_PA14__TK1			PINMUX_PIN(PIN_PA14, 2, 1)
#define PIN_PA14__QSPI0_SCK		PINMUX_PIN(PIN_PA14, 3, 2)
#define PIN_PA14__I2SC1_MCK		PINMUX_PIN(PIN_PA14, 4, 2)
#define PIN_PA14__FLEXCOM3_IO2		PINMUX_PIN(PIN_PA14, 5, 1)
#define PIN_PA14__D9			PINMUX_PIN(PIN_PA14, 6, 2)
#define PIN_PA15			15
#define PIN_PA15__GPIO			PINMUX_PIN(PIN_PA15, 0, 0)
#define PIN_PA15__SPI0_MOSI		PINMUX_PIN(PIN_PA15, 1, 1)
#define PIN_PA15__TF1			PINMUX_PIN(PIN_PA15, 2, 1)
#define PIN_PA15__QSPI0_CS		PINMUX_PIN(PIN_PA15, 3, 2)
#define PIN_PA15__I2SC1_CK		PINMUX_PIN(PIN_PA15, 4, 2)
#define PIN_PA15__FLEXCOM3_IO0		PINMUX_PIN(PIN_PA15, 5, 1)
#define PIN_PA15__D10			PINMUX_PIN(PIN_PA15, 6, 2)
#define PIN_PA16			16
#define PIN_PA16__GPIO			PINMUX_PIN(PIN_PA16, 0, 0)
#define PIN_PA16__SPI0_MISO		PINMUX_PIN(PIN_PA16, 1, 1)
#define PIN_PA16__TD1			PINMUX_PIN(PIN_PA16, 2, 1)
#define PIN_PA16__QSPI0_IO0		PINMUX_PIN(PIN_PA16, 3, 2)
#define PIN_PA16__I2SC1_WS		PINMUX_PIN(PIN_PA16, 4, 2)
#define PIN_PA16__FLEXCOM3_IO3		PINMUX_PIN(PIN_PA16, 5, 1)
#define PIN_PA16__D11			PINMUX_PIN(PIN_PA16, 6, 2)
#define PIN_PA17			17
#define PIN_PA17__GPIO			PINMUX_PIN(PIN_PA17, 0, 0)
#define PIN_PA17__SPI0_NPCS0		PINMUX_PIN(PIN_PA17, 1, 1)
#define PIN_PA17__RD1			PINMUX_PIN(PIN_PA17, 2, 1)
#define PIN_PA17__QSPI0_IO1		PINMUX_PIN(PIN_PA17, 3, 2)
#define PIN_PA17__I2SC1_DI0		PINMUX_PIN(PIN_PA17, 4, 2)
#define PIN_PA17__FLEXCOM3_IO4		PINMUX_PIN(PIN_PA17, 5, 1)
#define PIN_PA17__D12			PINMUX_PIN(PIN_PA17, 6, 2)
#define PIN_PA18			18
#define PIN_PA18__GPIO			PINMUX_PIN(PIN_PA18, 0, 0)
#define PIN_PA18__SPI0_NPCS1		PINMUX_PIN(PIN_PA18, 1, 1)
#define PIN_PA18__RK1			PINMUX_PIN(PIN_PA18, 2, 1)
#define PIN_PA18__QSPI0_IO2		PINMUX_PIN(PIN_PA18, 3, 2)
#define PIN_PA18__I2SC1_DO0		PINMUX_PIN(PIN_PA18, 4, 2)
#define PIN_PA18__SDMMC1_DAT0		PINMUX_PIN(PIN_PA18, 5, 1)
#define PIN_PA18__D13			PINMUX_PIN(PIN_PA18, 6, 2)
#define PIN_PA19			19
#define PIN_PA19__GPIO			PINMUX_PIN(PIN_PA19, 0, 0)
#define PIN_PA19__SPI0_NPCS2		PINMUX_PIN(PIN_PA19, 1, 1)
#define PIN_PA19__RF1			PINMUX_PIN(PIN_PA19, 2, 1)
#define PIN_PA19__QSPI0_IO3		PINMUX_PIN(PIN_PA19, 3, 2)
#define PIN_PA19__TIOA0			PINMUX_PIN(PIN_PA19, 4, 1)
#define PIN_PA19__SDMMC1_DAT1		PINMUX_PIN(PIN_PA19, 5, 1)
#define PIN_PA19__D14			PINMUX_PIN(PIN_PA19, 6, 2)
#define PIN_PA20			20
#define PIN_PA20__GPIO			PINMUX_PIN(PIN_PA20, 0, 0)
#define PIN_PA20__SPI0_NPCS3		PINMUX_PIN(PIN_PA20, 1, 1)
#define PIN_PA20__TIOB0			PINMUX_PIN(PIN_PA20, 4, 1)
#define PIN_PA20__SDMMC1_DAT2		PINMUX_PIN(PIN_PA20, 5, 1)
#define PIN_PA20__D15			PINMUX_PIN(PIN_PA20, 6, 2)
#define PIN_PA21			21
#define PIN_PA21__GPIO			PINMUX_PIN(PIN_PA21, 0, 0)
#define PIN_PA21__IRQ			PINMUX_PIN(PIN_PA21, 1, 2)
#define PIN_PA21__PCK2			PINMUX_PIN(PIN_PA21, 2, 3)
#define PIN_PA21__TCLK0			PINMUX_PIN(PIN_PA21, 4, 1)
#define PIN_PA21__SDMMC1_DAT3		PINMUX_PIN(PIN_PA21, 5, 1)
#define PIN_PA21__NANDRDY		PINMUX_PIN(PIN_PA21, 6, 2)
#define PIN_PA22			22
#define PIN_PA22__GPIO			PINMUX_PIN(PIN_PA22, 0, 0)
#define PIN_PA22__FLEXCOM1_IO2		PINMUX_PIN(PIN_PA22, 1, 1)
#define PIN_PA22__D0			PINMUX_PIN(PIN_PA22, 2, 1)
#define PIN_PA22__TCK			PINMUX_PIN(PIN_PA22, 3, 4)
#define PIN_PA22__SPI1_SPCK		PINMUX_PIN(PIN_PA22, 4, 2)
#define PIN_PA22__SDMMC1_CK		PINMUX_PIN(PIN_PA22, 5, 1)
#define PIN_PA22__QSPI0_SCK		PINMUX_PIN(PIN_PA22, 6, 3)
#define PIN_PA23			23
#define PIN_PA23__GPIO			PINMUX_PIN(PIN_PA23, 0, 0)
#define PIN_PA23__FLEXCOM1_IO1		PINMUX_PIN(PIN_PA23, 1, 1)
#define PIN_PA23__D1			PINMUX_PIN(PIN_PA23, 2, 1)
#define PIN_PA23__TDI			PINMUX_PIN(PIN_PA23, 3, 4)
#define PIN_PA23__SPI1_MOSI		PINMUX_PIN(PIN_PA23, 4, 2)
#define PIN_PA23__QSPI0_CS		PINMUX_PIN(PIN_PA23, 6, 3)
#define PIN_PA24			24
#define PIN_PA24__GPIO			PINMUX_PIN(PIN_PA24, 0, 0)
#define PIN_PA24__FLEXCOM1_IO0		PINMUX_PIN(PIN_PA24, 1, 1)
#define PIN_PA24__D2			PINMUX_PIN(PIN_PA24, 2, 1)
#define PIN_PA24__TDO			PINMUX_PIN(PIN_PA24, 3, 4)
#define PIN_PA24__SPI1_MISO		PINMUX_PIN(PIN_PA24, 4, 2)
#define PIN_PA24__QSPI0_IO0		PINMUX_PIN(PIN_PA24, 6, 3)
#define PIN_PA25			25
#define PIN_PA25__GPIO			PINMUX_PIN(PIN_PA25, 0, 0)
#define PIN_PA25__FLEXCOM1_IO3		PINMUX_PIN(PIN_PA25, 1, 1)
#define PIN_PA25__D3			PINMUX_PIN(PIN_PA25, 2, 1)
#define PIN_PA25__TMS			PINMUX_PIN(PIN_PA25, 3, 4)
#define PIN_PA25__SPI1_NPCS0		PINMUX_PIN(PIN_PA25, 4, 2)
#define PIN_PA25__QSPI0_IO1		PINMUX_PIN(PIN_PA25, 6, 3)
#define PIN_PA26			26
#define PIN_PA26__GPIO			PINMUX_PIN(PIN_PA26, 0, 0)
#define PIN_PA26__FLEXCOM1_IO4		PINMUX_PIN(PIN_PA26, 1, 1)
#define PIN_PA26__D4			PINMUX_PIN(PIN_PA26, 2, 1)
#define PIN_PA26__NTRST			PINMUX_PIN(PIN_PA26, 3, 4)
#define PIN_PA26__SPI1_NPCS1		PINMUX_PIN(PIN_PA26, 4, 2)
#define PIN_PA26__QSPI0_IO2		PINMUX_PIN(PIN_PA26, 6, 3)
#define PIN_PA27			27
#define PIN_PA27__GPIO			PINMUX_PIN(PIN_PA27, 0, 0)
#define PIN_PA27__TIOA1			PINMUX_PIN(PIN_PA27, 1, 2)
#define PIN_PA27__D5			PINMUX_PIN(PIN_PA27, 2, 1)
#define PIN_PA27__SPI0_NPCS2		PINMUX_PIN(PIN_PA27, 3, 2)
#define PIN_PA27__SPI1_NPCS2		PINMUX_PIN(PIN_PA27, 4, 2)
#define PIN_PA27__SDMMC1_RSTN		PINMUX_PIN(PIN_PA27, 5, 1)
#define PIN_PA27__QSPI0_IO3		PINMUX_PIN(PIN_PA27, 6, 3)
#define PIN_PA28			28
#define PIN_PA28__GPIO			PINMUX_PIN(PIN_PA28, 0, 0)
#define PIN_PA28__TIOB1			PINMUX_PIN(PIN_PA28, 1, 2)
#define PIN_PA28__D6			PINMUX_PIN(PIN_PA28, 2, 1)
#define PIN_PA28__SPI0_NPCS3		PINMUX_PIN(PIN_PA28, 3, 2)
#define PIN_PA28__SPI1_NPCS3		PINMUX_PIN(PIN_PA28, 4, 2)
#define PIN_PA28__SDMMC1_CMD		PINMUX_PIN(PIN_PA28, 5, 1)
#define PIN_PA28__CLASSD_L0		PINMUX_PIN(PIN_PA28, 6, 1)
#define PIN_PA29			29
#define PIN_PA29__GPIO			PINMUX_PIN(PIN_PA29, 0, 0)
#define PIN_PA29__TCLK1			PINMUX_PIN(PIN_PA29, 1, 2)
#define PIN_PA29__D7			PINMUX_PIN(PIN_PA29, 2, 1)
#define PIN_PA29__SPI0_NPCS1		PINMUX_PIN(PIN_PA29, 3, 2)
#define PIN_PA29__SDMMC1_WP		PINMUX_PIN(PIN_PA29, 5, 1)
#define PIN_PA29__CLASSD_L1		PINMUX_PIN(PIN_PA29, 6, 1)
#define PIN_PA30			30
#define PIN_PA30__GPIO			PINMUX_PIN(PIN_PA30, 0, 0)
#define PIN_PA30__NWE_NANDWE		PINMUX_PIN(PIN_PA30, 2, 1)
#define PIN_PA30__SPI0_NPCS0		PINMUX_PIN(PIN_PA30, 3, 2)
#define PIN_PA30__PWMH0			PINMUX_PIN(PIN_PA30, 4, 1)
#define PIN_PA30__SDMMC1_CD		PINMUX_PIN(PIN_PA30, 5, 1)
#define PIN_PA30__CLASSD_L2		PINMUX_PIN(PIN_PA30, 6, 1)
#define PIN_PA31			31
#define PIN_PA31__GPIO			PINMUX_PIN(PIN_PA31, 0, 0)
#define PIN_PA31__NCS3			PINMUX_PIN(PIN_PA31, 2, 1)
#define PIN_PA31__SPI0_MISO		PINMUX_PIN(PIN_PA31, 3, 2)
#define PIN_PA31__PWML0			PINMUX_PIN(PIN_PA31, 4, 1)
#define PIN_PA31__CLASSD_L3		PINMUX_PIN(PIN_PA31, 6, 1)
#define PIN_PB0				32
#define PIN_PB0__GPIO			PINMUX_PIN(PIN_PB0, 0, 0)
#define PIN_PB0__A21_NANDALE		PINMUX_PIN(PIN_PB0, 2, 1)
#define PIN_PB0__SPI0_MOSI		PINMUX_PIN(PIN_PB0, 3, 2)
#define PIN_PB0__PWMH1			PINMUX_PIN(PIN_PB0, 4, 1)
#define PIN_PB1				33
#define PIN_PB1__GPIO			PINMUX_PIN(PIN_PB1, 0, 0)
#define PIN_PB1__A22_NANDCLE		PINMUX_PIN(PIN_PB1, 2, 1)
#define PIN_PB1__SPI0_SPCK		PINMUX_PIN(PIN_PB1, 3, 2)
#define PIN_PB1__PWML1			PINMUX_PIN(PIN_PB1, 4, 1)
#define PIN_PB1__CLASSD_R0		PINMUX_PIN(PIN_PB1, 6, 1)
#define PIN_PB2				34
#define PIN_PB2__GPIO			PINMUX_PIN(PIN_PB2, 0, 0)
#define PIN_PB2__NRD_NANDOE		PINMUX_PIN(PIN_PB2, 2, 1)
#define PIN_PB2__PWMFI0			PINMUX_PIN(PIN_PB2, 4, 1)
#define PIN_PB2__CLASSD_R1		PINMUX_PIN(PIN_PB2, 6, 1)
#define PIN_PB3				35
#define PIN_PB3__GPIO			PINMUX_PIN(PIN_PB3, 0, 0)
#define PIN_PB3__URXD4			PINMUX_PIN(PIN_PB3, 1, 1)
#define PIN_PB3__D8			PINMUX_PIN(PIN_PB3, 2, 1)
#define PIN_PB3__IRQ			PINMUX_PIN(PIN_PB3, 3, 3)
#define PIN_PB3__PWMEXTRG0		PINMUX_PIN(PIN_PB3, 4, 1)
#define PIN_PB3__CLASSD_R2		PINMUX_PIN(PIN_PB3, 6, 1)
#define PIN_PB4				36
#define PIN_PB4__GPIO			PINMUX_PIN(PIN_PB4, 0, 0)
#define PIN_PB4__UTXD4			PINMUX_PIN(PIN_PB4, 1, 1)
#define PIN_PB4__D9			PINMUX_PIN(PIN_PB4, 2, 1)
#define PIN_PB4__FIQ			PINMUX_PIN(PIN_PB4, 3, 4)
#define PIN_PB4__CLASSD_R3		PINMUX_PIN(PIN_PB4, 6, 1)
#define PIN_PB5				37
#define PIN_PB5__GPIO			PINMUX_PIN(PIN_PB5, 0, 0)
#define PIN_PB5__TCLK2			PINMUX_PIN(PIN_PB5, 1, 1)
#define PIN_PB5__D10			PINMUX_PIN(PIN_PB5, 2, 1)
#define PIN_PB5__PWMH2			PINMUX_PIN(PIN_PB5, 3, 1)
#define PIN_PB5__QSPI1_SCK		PINMUX_PIN(PIN_PB5, 4, 2)
#define PIN_PB5__GTSUCOMP		PINMUX_PIN(PIN_PB5, 6, 3)
#define PIN_PB6				38
#define PIN_PB6__GPIO			PINMUX_PIN(PIN_PB6, 0, 0)
#define PIN_PB6__TIOA2			PINMUX_PIN(PIN_PB6, 1, 1)
#define PIN_PB6__D11			PINMUX_PIN(PIN_PB6, 2, 1)
#define PIN_PB6__PWML2			PINMUX_PIN(PIN_PB6, 3, 1)
#define PIN_PB6__QSPI1_CS		PINMUX_PIN(PIN_PB6, 4, 2)
#define PIN_PB6__GTXER			PINMUX_PIN(PIN_PB6, 6, 3)
#define PIN_PB7				39
#define PIN_PB7__GPIO			PINMUX_PIN(PIN_PB7, 0, 0)
#define PIN_PB7__TIOB2			PINMUX_PIN(PIN_PB7, 1, 1)
#define PIN_PB7__D12			PINMUX_PIN(PIN_PB7, 2, 1)
#define PIN_PB7__PWMH3			PINMUX_PIN(PIN_PB7, 3, 1)
#define PIN_PB7__QSPI1_IO0		PINMUX_PIN(PIN_PB7, 4, 2)
#define PIN_PB7__GRXCK			PINMUX_PIN(PIN_PB7, 6, 3)
#define PIN_PB8				40
#define PIN_PB8__GPIO			PINMUX_PIN(PIN_PB8, 0, 0)
#define PIN_PB8__TCLK3			PINMUX_PIN(PIN_PB8, 1, 1)
#define PIN_PB8__D13			PINMUX_PIN(PIN_PB8, 2, 1)
#define PIN_PB8__PWML3			PINMUX_PIN(PIN_PB8, 3, 1)
#define PIN_PB8__QSPI1_IO1		PINMUX_PIN(PIN_PB8, 4, 2)
#define PIN_PB8__GCRS			PINMUX_PIN(PIN_PB8, 6, 3)
#define PIN_PB9				41
#define PIN_PB9__GPIO			PINMUX_PIN(PIN_PB9, 0, 0)
#define PIN_PB9__TIOA3			PINMUX_PIN(PIN_PB9, 1, 1)
#define PIN_PB9__D14			PINMUX_PIN(PIN_PB9, 2, 1)
#define PIN_PB9__PWMFI1			PINMUX_PIN(PIN_PB9, 3, 1)
#define PIN_PB9__QSPI1_IO2		PINMUX_PIN(PIN_PB9, 4, 2)
#define PIN_PB9__GCOL			PINMUX_PIN(PIN_PB9, 6, 3)
#define PIN_PB10			42
#define PIN_PB10__GPIO			PINMUX_PIN(PIN_PB10, 0, 0)
#define PIN_PB10__TIOB3			PINMUX_PIN(PIN_PB10, 1, 1)
#define PIN_PB10__D15			PINMUX_PIN(PIN_PB10, 2, 1)
#define PIN_PB10__PWMEXTRG1		PINMUX_PIN(PIN_PB10, 3, 1)
#define PIN_PB10__QSPI1_IO3		PINMUX_PIN(PIN_PB10, 4, 2)
#define PIN_PB10__GRX2			PINMUX_PIN(PIN_PB10, 6, 3)
#define PIN_PB11			43
#define PIN_PB11__GPIO			PINMUX_PIN(PIN_PB11, 0, 0)
#define PIN_PB11__LCDDAT0		PINMUX_PIN(PIN_PB11, 1, 1)
#define PIN_PB11__A0_NBS0		PINMUX_PIN(PIN_PB11, 2, 1)
#define PIN_PB11__URXD3			PINMUX_PIN(PIN_PB11, 3, 3)
#define PIN_PB11__PDMIC_DAT		PINMUX_PIN(PIN_PB11, 4, 2)
#define PIN_PB11__GRX3			PINMUX_PIN(PIN_PB11, 6, 3)
#define PIN_PB12			44
#define PIN_PB12__GPIO			PINMUX_PIN(PIN_PB12, 0, 0)
#define PIN_PB12__LCDDAT1		PINMUX_PIN(PIN_PB12, 1, 1)
#define PIN_PB12__A1			PINMUX_PIN(PIN_PB12, 2, 1)
#define PIN_PB12__UTXD3			PINMUX_PIN(PIN_PB12, 3, 3)
#define PIN_PB12__PDMIC_CLK		PINMUX_PIN(PIN_PB12, 4, 2)
#define PIN_PB12__GTX2			PINMUX_PIN(PIN_PB12, 6, 3)
#define PIN_PB13			45
#define PIN_PB13__GPIO			PINMUX_PIN(PIN_PB13, 0, 0)
#define PIN_PB13__LCDDAT2		PINMUX_PIN(PIN_PB13, 1, 1)
#define PIN_PB13__A2			PINMUX_PIN(PIN_PB13, 2, 1)
#define PIN_PB13__PCK1			PINMUX_PIN(PIN_PB13, 3, 3)
#define PIN_PB13__GTX3			PINMUX_PIN(PIN_PB13, 6, 3)
#define PIN_PB14			46
#define PIN_PB14__GPIO			PINMUX_PIN(PIN_PB14, 0, 0)
#define PIN_PB14__LCDDAT3		PINMUX_PIN(PIN_PB14, 1, 1)
#define PIN_PB14__A3			PINMUX_PIN(PIN_PB14, 2, 1)
#define PIN_PB14__TK1			PINMUX_PIN(PIN_PB14, 3, 2)
#define PIN_PB14__I2SC1_MCK		PINMUX_PIN(PIN_PB14, 4, 1)
#define PIN_PB14__QSPI1_SCK		PINMUX_PIN(PIN_PB14, 5, 3)
#define PIN_PB14__GTXCK			PINMUX_PIN(PIN_PB14, 6, 3)
#define PIN_PB15			47
#define PIN_PB15__GPIO			PINMUX_PIN(PIN_PB15, 0, 0)
#define PIN_PB15__LCDDAT4		PINMUX_PIN(PIN_PB15, 1, 1)
#define PIN_PB15__A4			PINMUX_PIN(PIN_PB15, 2, 1)
#define PIN_PB15__TF1			PINMUX_PIN(PIN_PB15, 3, 2)
#define PIN_PB15__I2SC1_CK		PINMUX_PIN(PIN_PB15, 4, 1)
#define PIN_PB15__QSPI1_CS		PINMUX_PIN(PIN_PB15, 5, 3)
#define PIN_PB15__GTXEN			PINMUX_PIN(PIN_PB15, 6, 3)
#define PIN_PB16			48
#define PIN_PB16__GPIO			PINMUX_PIN(PIN_PB16, 0, 0)
#define PIN_PB16__LCDDAT5		PINMUX_PIN(PIN_PB16, 1, 1)
#define PIN_PB16__A5			PINMUX_PIN(PIN_PB16, 2, 1)
#define PIN_PB16__TD1			PINMUX_PIN(PIN_PB16, 3, 2)
#define PIN_PB16__I2SC1_WS		PINMUX_PIN(PIN_PB16, 4, 1)
#define PIN_PB16__QSPI1_IO0		PINMUX_PIN(PIN_PB16, 5, 3)
#define PIN_PB16__GRXDV			PINMUX_PIN(PIN_PB16, 6, 3)
#define PIN_PB17			49
#define PIN_PB17__GPIO			PINMUX_PIN(PIN_PB17, 0, 0)
#define PIN_PB17__LCDDAT6		PINMUX_PIN(PIN_PB17, 1, 1)
#define PIN_PB17__A6			PINMUX_PIN(PIN_PB17, 2, 1)
#define PIN_PB17__RD1			PINMUX_PIN(PIN_PB17, 3, 2)
#define PIN_PB17__I2SC1_DI0		PINMUX_PIN(PIN_PB17, 4, 1)
#define PIN_PB17__QSPI1_IO1		PINMUX_PIN(PIN_PB17, 5, 3)
#define PIN_PB17__GRXER			PINMUX_PIN(PIN_PB17, 6, 3)
#define PIN_PB18			50
#define PIN_PB18__GPIO			PINMUX_PIN(PIN_PB18, 0, 0)
#define PIN_PB18__LCDDAT7		PINMUX_PIN(PIN_PB18, 1, 1)
#define PIN_PB18__A7			PINMUX_PIN(PIN_PB18, 2, 1)
#define PIN_PB18__RK1			PINMUX_PIN(PIN_PB18, 3, 2)
#define PIN_PB18__I2SC1_DO0		PINMUX_PIN(PIN_PB18, 4, 1)
#define PIN_PB18__QSPI1_IO2		PINMUX_PIN(PIN_PB18, 5, 3)
#define PIN_PB18__GRX0			PINMUX_PIN(PIN_PB18, 6, 3)
#define PIN_PB19			51
#define PIN_PB19__GPIO			PINMUX_PIN(PIN_PB19, 0, 0)
#define PIN_PB19__LCDDAT8		PINMUX_PIN(PIN_PB19, 1, 1)
#define PIN_PB19__A8			PINMUX_PIN(PIN_PB19, 2, 1)
#define PIN_PB19__RF1			PINMUX_PIN(PIN_PB19, 3, 2)
#define PIN_PB19__TIOA3			PINMUX_PIN(PIN_PB19, 4, 2)
#define PIN_PB19__QSPI1_IO3		PINMUX_PIN(PIN_PB19, 5, 3)
#define PIN_PB19__GRX1			PINMUX_PIN(PIN_PB19, 6, 3)
#define PIN_PB20			52
#define PIN_PB20__GPIO			PINMUX_PIN(PIN_PB20, 0, 0)
#define PIN_PB20__LCDDAT9		PINMUX_PIN(PIN_PB20, 1, 1)
#define PIN_PB20__A9			PINMUX_PIN(PIN_PB20, 2, 1)
#define PIN_PB20__TK0			PINMUX_PIN(PIN_PB20, 3, 1)
#define PIN_PB20__TIOB3			PINMUX_PIN(PIN_PB20, 4, 2)
#define PIN_PB20__PCK1			PINMUX_PIN(PIN_PB20, 5, 4)
#define PIN_PB20__GTX0			PINMUX_PIN(PIN_PB20, 6, 3)
#define PIN_PB21			53
#define PIN_PB21__GPIO			PINMUX_PIN(PIN_PB21, 0, 0)
#define PIN_PB21__LCDDAT10		PINMUX_PIN(PIN_PB21, 1, 1)
#define PIN_PB21__A10			PINMUX_PIN(PIN_PB21, 2, 1)
#define PIN_PB21__TF0			PINMUX_PIN(PIN_PB21, 3, 1)
#define PIN_PB21__TCLK3			PINMUX_PIN(PIN_PB21, 4, 2)
#define PIN_PB21__FLEXCOM3_IO2		PINMUX_PIN(PIN_PB21, 5, 3)
#define PIN_PB21__GTX1			PINMUX_PIN(PIN_PB21, 6, 3)
#define PIN_PB22			54
#define PIN_PB22__GPIO			PINMUX_PIN(PIN_PB22, 0, 0)
#define PIN_PB22__LCDDAT11		PINMUX_PIN(PIN_PB22, 1, 1)
#define PIN_PB22__A11			PINMUX_PIN(PIN_PB22, 2, 1)
#define PIN_PB22__TD0			PINMUX_PIN(PIN_PB22, 3, 1)
#define PIN_PB22__TIOA2			PINMUX_PIN(PIN_PB22, 4, 2)
#define PIN_PB22__FLEXCOM3_IO1		PINMUX_PIN(PIN_PB22, 5, 3)
#define PIN_PB22__GMDC			PINMUX_PIN(PIN_PB22, 6, 3)
#define PIN_PB23			55
#define PIN_PB23__GPIO			PINMUX_PIN(PIN_PB23, 0, 0)
#define PIN_PB23__LCDDAT12		PINMUX_PIN(PIN_PB23, 1, 1)
#define PIN_PB23__A12			PINMUX_PIN(PIN_PB23, 2, 1)
#define PIN_PB23__RD0			PINMUX_PIN(PIN_PB23, 3, 1)
#define PIN_PB23__TIOB2			PINMUX_PIN(PIN_PB23, 4, 2)
#define PIN_PB23__FLEXCOM3_IO0		PINMUX_PIN(PIN_PB23, 5, 3)
#define PIN_PB23__GMDIO			PINMUX_PIN(PIN_PB23, 6, 3)
#define PIN_PB24			56
#define PIN_PB24__GPIO			PINMUX_PIN(PIN_PB24, 0, 0)
#define PIN_PB24__LCDDAT13		PINMUX_PIN(PIN_PB24, 1, 1)
#define PIN_PB24__A13			PINMUX_PIN(PIN_PB24, 2, 1)
#define PIN_PB24__RK0			PINMUX_PIN(PIN_PB24, 3, 1)
#define PIN_PB24__TCLK2			PINMUX_PIN(PIN_PB24, 4, 2)
#define PIN_PB24__FLEXCOM3_IO3		PINMUX_PIN(PIN_PB24, 5, 3)
#define PIN_PB24__ISC_D10		PINMUX_PIN(PIN_PB24, 6, 3)
#define PIN_PB25			57
#define PIN_PB25__GPIO			PINMUX_PIN(PIN_PB25, 0, 0)
#define PIN_PB25__LCDDAT14		PINMUX_PIN(PIN_PB25, 1, 1)
#define PIN_PB25__A14			PINMUX_PIN(PIN_PB25, 2, 1)
#define PIN_PB25__RF0			PINMUX_PIN(PIN_PB25, 3, 1)
#define PIN_PB25__FLEXCOM3_IO4		PINMUX_PIN(PIN_PB25, 5, 3)
#define PIN_PB25__ISC_D11		PINMUX_PIN(PIN_PB25, 6, 3)
#define PIN_PB26			58
#define PIN_PB26__GPIO			PINMUX_PIN(PIN_PB26, 0, 0)
#define PIN_PB26__LCDDAT15		PINMUX_PIN(PIN_PB26, 1, 1)
#define PIN_PB26__A15			PINMUX_PIN(PIN_PB26, 2, 1)
#define PIN_PB26__URXD0			PINMUX_PIN(PIN_PB26, 3, 1)
#define PIN_PB26__PDMIC_DAT		PINMUX_PIN(PIN_PB26, 4, 1)
#define PIN_PB26__ISC_D0		PINMUX_PIN(PIN_PB26, 6, 3)
#define PIN_PB27			59
#define PIN_PB27__GPIO			PINMUX_PIN(PIN_PB27, 0, 0)
#define PIN_PB27__LCDDAT16		PINMUX_PIN(PIN_PB27, 1, 1)
#define PIN_PB27__A16			PINMUX_PIN(PIN_PB27, 2, 1)
#define PIN_PB27__UTXD0			PINMUX_PIN(PIN_PB27, 3, 1)
#define PIN_PB27__PDMIC_CLK		PINMUX_PIN(PIN_PB27, 4, 1)
#define PIN_PB27__ISC_D1		PINMUX_PIN(PIN_PB27, 6, 3)
#define PIN_PB28			60
#define PIN_PB28__GPIO			PINMUX_PIN(PIN_PB28, 0, 0)
#define PIN_PB28__LCDDAT17		PINMUX_PIN(PIN_PB28, 1, 1)
#define PIN_PB28__A17			PINMUX_PIN(PIN_PB28, 2, 1)
#define PIN_PB28__FLEXCOM0_IO0		PINMUX_PIN(PIN_PB28, 3, 1)
#define PIN_PB28__TIOA5			PINMUX_PIN(PIN_PB28, 4, 2)
#define PIN_PB28__ISC_D2		PINMUX_PIN(PIN_PB28, 6, 3)
#define PIN_PB29			61
#define PIN_PB29__GPIO			PINMUX_PIN(PIN_PB29, 0, 0)
#define PIN_PB29__LCDDAT18		PINMUX_PIN(PIN_PB29, 1, 1)
#define PIN_PB29__A18			PINMUX_PIN(PIN_PB29, 2, 1)
#define PIN_PB29__FLEXCOM0_IO1		PINMUX_PIN(PIN_PB29, 3, 1)
#define PIN_PB29__TIOB5			PINMUX_PIN(PIN_PB29, 4, 2)
#define PIN_PB29__ISC_D3		PINMUX_PIN(PIN_PB29, 7, 3)
#define PIN_PB30			62
#define PIN_PB30__GPIO			PINMUX_PIN(PIN_PB30, 0, 0)
#define PIN_PB30__LCDDAT19		PINMUX_PIN(PIN_PB30, 1, 1)
#define PIN_PB30__A19			PINMUX_PIN(PIN_PB30, 2, 1)
#define PIN_PB30__FLEXCOM0_IO2		PINMUX_PIN(PIN_PB30, 3, 1)
#define PIN_PB30__TCLK5			PINMUX_PIN(PIN_PB30, 4, 2)
#define PIN_PB30__ISC_D4		PINMUX_PIN(PIN_PB30, 6, 3)
#define PIN_PB31			63
#define PIN_PB31__GPIO			PINMUX_PIN(PIN_PB31, 0, 0)
#define PIN_PB31__LCDDAT20		PINMUX_PIN(PIN_PB31, 1, 1)
#define PIN_PB31__A20			PINMUX_PIN(PIN_PB31, 2, 1)
#define PIN_PB31__FLEXCOM0_IO3		PINMUX_PIN(PIN_PB31, 3, 1)
#define PIN_PB31__TWD0			PINMUX_PIN(PIN_PB31, 4, 1)
#define PIN_PB31__ISC_D5		PINMUX_PIN(PIN_PB31, 6, 3)
#define PIN_PC0				64
#define PIN_PC0__GPIO			PINMUX_PIN(PIN_PC0, 0, 0)
#define PIN_PC0__LCDDAT21		PINMUX_PIN(PIN_PC0, 1, 1)
#define PIN_PC0__A23			PINMUX_PIN(PIN_PC0, 2, 1)
#define PIN_PC0__FLEXCOM0_IO4		PINMUX_PIN(PIN_PC0, 3, 1)
#define PIN_PC0__TWCK0			PINMUX_PIN(PIN_PC0, 4, 1)
#define PIN_PC0__ISC_D6			PINMUX_PIN(PIN_PC0, 6, 3)
#define PIN_PC1				65
#define PIN_PC1__GPIO			PINMUX_PIN(PIN_PC1, 0, 0)
#define PIN_PC1__LCDDAT22		PINMUX_PIN(PIN_PC1, 1, 1)
#define PIN_PC1__A24			PINMUX_PIN(PIN_PC1, 2, 1)
#define PIN_PC1__CANTX0			PINMUX_PIN(PIN_PC1, 3, 1)
#define PIN_PC1__SPI1_SPCK		PINMUX_PIN(PIN_PC1, 4, 1)
#define PIN_PC1__I2SC0_CK		PINMUX_PIN(PIN_PC1, 5, 1)
#define PIN_PC1__ISC_D7			PINMUX_PIN(PIN_PC1, 6, 3)
#define PIN_PC2				66
#define PIN_PC2__GPIO			PINMUX_PIN(PIN_PC2, 0, 0)
#define PIN_PC2__LCDDAT23		PINMUX_PIN(PIN_PC2, 1, 1)
#define PIN_PC2__A25			PINMUX_PIN(PIN_PC2, 2, 1)
#define PIN_PC2__CANRX0			PINMUX_PIN(PIN_PC2, 3, 1)
#define PIN_PC2__SPI1_MOSI		PINMUX_PIN(PIN_PC2, 4, 1)
#define PIN_PC2__I2SC0_MCK		PINMUX_PIN(PIN_PC2, 5, 1)
#define PIN_PC2__ISC_D8			PINMUX_PIN(PIN_PC2, 6, 3)
#define PIN_PC3				67
#define PIN_PC3__GPIO			PINMUX_PIN(PIN_PC3, 0, 0)
#define PIN_PC3__LCDPWM			PINMUX_PIN(PIN_PC3, 1, 1)
#define PIN_PC3__NWAIT			PINMUX_PIN(PIN_PC3, 2, 1)
#define PIN_PC3__TIOA1			PINMUX_PIN(PIN_PC3, 3, 1)
#define PIN_PC3__SPI1_MISO		PINMUX_PIN(PIN_PC3, 4, 1)
#define PIN_PC3__I2SC0_WS		PINMUX_PIN(PIN_PC3, 5, 1)
#define PIN_PC3__ISC_D9			PINMUX_PIN(PIN_PC3, 6, 3)
#define PIN_PC4				68
#define PIN_PC4__GPIO			PINMUX_PIN(PIN_PC4, 0, 0)
#define PIN_PC4__LCDDISP		PINMUX_PIN(PIN_PC4, 1, 1)
#define PIN_PC4__NWR1_NBS1		PINMUX_PIN(PIN_PC4, 2, 1)
#define PIN_PC4__TIOB1			PINMUX_PIN(PIN_PC4, 3, 1)
#define PIN_PC4__SPI1_NPCS0		PINMUX_PIN(PIN_PC4, 4, 1)
#define PIN_PC4__I2SC0_DI0		PINMUX_PIN(PIN_PC4, 5, 1)
#define PIN_PC4__ISC_PCK		PINMUX_PIN(PIN_PC4, 6, 3)
#define PIN_PC5				69
#define PIN_PC5__GPIO			PINMUX_PIN(PIN_PC5, 0, 0)
#define PIN_PC5__LCDVSYNC		PINMUX_PIN(PIN_PC5, 1, 1)
#define PIN_PC5__NCS0			PINMUX_PIN(PIN_PC5, 2, 1)
#define PIN_PC5__TCLK1			PINMUX_PIN(PIN_PC5, 3, 1)
#define PIN_PC5__SPI1_NPCS1		PINMUX_PIN(PIN_PC5, 4, 1)
#define PIN_PC5__I2SC0_DO0		PINMUX_PIN(PIN_PC5, 5, 1)
#define PIN_PC5__ISC_VSYNC		PINMUX_PIN(PIN_PC5, 6, 3)
#define PIN_PC6				70
#define PIN_PC6__GPIO			PINMUX_PIN(PIN_PC6, 0, 0)
#define PIN_PC6__LCDHSYNC		PINMUX_PIN(PIN_PC6, 1, 1)
#define PIN_PC6__NCS1			PINMUX_PIN(PIN_PC6, 2, 1)
#define PIN_PC6__TWD1			PINMUX_PIN(PIN_PC6, 3, 1)
#define PIN_PC6__SPI1_NPCS2		PINMUX_PIN(PIN_PC6, 4, 1)
#define PIN_PC6__ISC_HSYNC		PINMUX_PIN(PIN_PC6, 6, 3)
#define PIN_PC7				71
#define PIN_PC7__GPIO			PINMUX_PIN(PIN_PC7, 0, 0)
#define PIN_PC7__LCDPCK			PINMUX_PIN(PIN_PC7, 1, 1)
#define PIN_PC7__NCS2			PINMUX_PIN(PIN_PC7, 2, 1)
#define PIN_PC7__TWCK1			PINMUX_PIN(PIN_PC7, 3, 1)
#define PIN_PC7__SPI1_NPCS3		PINMUX_PIN(PIN_PC7, 4, 1)
#define PIN_PC7__URXD1			PINMUX_PIN(PIN_PC7, 5, 2)
#define PIN_PC7__ISC_MCK		PINMUX_PIN(PIN_PC7, 6, 3)
#define PIN_PC8				72
#define PIN_PC8__GPIO			PINMUX_PIN(PIN_PC8, 0, 0)
#define PIN_PC8__LCDDEN			PINMUX_PIN(PIN_PC8, 1, 1)
#define PIN_PC8__NANDRDY		PINMUX_PIN(PIN_PC8, 2, 1)
#define PIN_PC8__FIQ			PINMUX_PIN(PIN_PC8, 3, 1)
#define PIN_PC8__PCK0			PINMUX_PIN(PIN_PC8, 4, 3)
#define PIN_PC8__UTXD1			PINMUX_PIN(PIN_PC8, 5, 2)
#define PIN_PC8__ISC_FIELD		PINMUX_PIN(PIN_PC8, 6, 3)
#define PIN_PC9				73
#define PIN_PC9__GPIO			PINMUX_PIN(PIN_PC9, 0, 0)
#define PIN_PC9__FIQ			PINMUX_PIN(PIN_PC9, 1, 3)
#define PIN_PC9__GTSUCOMP		PINMUX_PIN(PIN_PC9, 2, 1)
#define PIN_PC9__ISC_D0			PINMUX_PIN(PIN_PC9, 3, 1)
#define PIN_PC9__TIOA4			PINMUX_PIN(PIN_PC9, 4, 2)
#define PIN_PC10			74
#define PIN_PC10__GPIO			PINMUX_PIN(PIN_PC10, 0, 0)
#define PIN_PC10__LCDDAT2		PINMUX_PIN(PIN_PC10, 1, 2)
#define PIN_PC10__GTXCK			PINMUX_PIN(PIN_PC10, 2, 1)
#define PIN_PC10__ISC_D1		PINMUX_PIN(PIN_PC10, 3, 1)
#define PIN_PC10__TIOB4			PINMUX_PIN(PIN_PC10, 4, 2)
#define PIN_PC10__CANTX0		PINMUX_PIN(PIN_PC10, 5, 2)
#define PIN_PC11			75
#define PIN_PC11__GPIO			PINMUX_PIN(PIN_PC11, 0, 0)
#define PIN_PC11__LCDDAT3		PINMUX_PIN(PIN_PC11, 1, 2)
#define PIN_PC11__GTXEN			PINMUX_PIN(PIN_PC11, 2, 1)
#define PIN_PC11__ISC_D2		PINMUX_PIN(PIN_PC11, 3, 1)
#define PIN_PC11__TCLK4			PINMUX_PIN(PIN_PC11, 4, 2)
#define PIN_PC11__CANRX0		PINMUX_PIN(PIN_PC11, 5, 2)
#define PIN_PC11__A0_NBS0		PINMUX_PIN(PIN_PC11, 6, 2)
#define PIN_PC12			76
#define PIN_PC12__GPIO			PINMUX_PIN(PIN_PC12, 0, 0)
#define PIN_PC12__LCDDAT4		PINMUX_PIN(PIN_PC12, 1, 2)
#define PIN_PC12__GRXDV			PINMUX_PIN(PIN_PC12, 2, 1)
#define PIN_PC12__ISC_D3		PINMUX_PIN(PIN_PC12, 3, 1)
#define PIN_PC12__URXD3			PINMUX_PIN(PIN_PC12, 4, 1)
#define PIN_PC12__TK0			PINMUX_PIN(PIN_PC12, 5, 2)
#define PIN_PC12__A1			PINMUX_PIN(PIN_PC12, 6, 2)
#define PIN_PC13			77
#define PIN_PC13__GPIO			PINMUX_PIN(PIN_PC13, 0, 0)
#define PIN_PC13__LCDDAT5		PINMUX_PIN(PIN_PC13, 1, 2)
#define PIN_PC13__GRXER			PINMUX_PIN(PIN_PC13, 2, 1)
#define PIN_PC13__ISC_D4		PINMUX_PIN(PIN_PC13, 3, 1)
#define PIN_PC13__UTXD3			PINMUX_PIN(PIN_PC13, 4, 1)
#define PIN_PC13__TF0			PINMUX_PIN(PIN_PC13, 5, 2)
#define PIN_PC13__A2			PINMUX_PIN(PIN_PC13, 6, 2)
#define PIN_PC14			78
#define PIN_PC14__GPIO			PINMUX_PIN(PIN_PC14, 0, 0)
#define PIN_PC14__LCDDAT6		PINMUX_PIN(PIN_PC14, 1, 2)
#define PIN_PC14__GRX0			PINMUX_PIN(PIN_PC14, 2, 1)
#define PIN_PC14__ISC_D5		PINMUX_PIN(PIN_PC14, 3, 1)
#define PIN_PC14__TD0			PINMUX_PIN(PIN_PC14, 5, 2)
#define PIN_PC14__A3			PINMUX_PIN(PIN_PC14, 6, 2)
#define PIN_PC15			79
#define PIN_PC15__GPIO			PINMUX_PIN(PIN_PC15, 0, 0)
#define PIN_PC15__LCDDAT7		PINMUX_PIN(PIN_PC15, 1, 2)
#define PIN_PC15__GRX1			PINMUX_PIN(PIN_PC15, 2, 1)
#define PIN_PC15__ISC_D6		PINMUX_PIN(PIN_PC15, 3, 1)
#define PIN_PC15__RD0			PINMUX_PIN(PIN_PC15, 5, 2)
#define PIN_PC15__A4			PINMUX_PIN(PIN_PC15, 6, 2)
#define PIN_PC16			80
#define PIN_PC16__GPIO			PINMUX_PIN(PIN_PC16, 0, 0)
#define PIN_PC16__LCDDAT10		PINMUX_PIN(PIN_PC16, 1, 2)
#define PIN_PC16__GTX0			PINMUX_PIN(PIN_PC16, 2, 1)
#define PIN_PC16__ISC_D7		PINMUX_PIN(PIN_PC16, 3, 1)
#define PIN_PC16__RK0			PINMUX_PIN(PIN_PC16, 5, 2)
#define PIN_PC16__A5			PINMUX_PIN(PIN_PC16, 6, 2)
#define PIN_PC17			81
#define PIN_PC17__GPIO			PINMUX_PIN(PIN_PC17, 0, 0)
#define PIN_PC17__LCDDAT11		PINMUX_PIN(PIN_PC17, 1, 2)
#define PIN_PC17__GTX1			PINMUX_PIN(PIN_PC17, 2, 1)
#define PIN_PC17__ISC_D8		PINMUX_PIN(PIN_PC17, 3, 1)
#define PIN_PC17__RF0			PINMUX_PIN(PIN_PC17, 5, 2)
#define PIN_PC17__A6			PINMUX_PIN(PIN_PC17, 6, 2)
#define PIN_PC18			82
#define PIN_PC18__GPIO			PINMUX_PIN(PIN_PC18, 0, 0)
#define PIN_PC18__LCDDAT12		PINMUX_PIN(PIN_PC18, 1, 2)
#define PIN_PC18__GMDC			PINMUX_PIN(PIN_PC18, 2, 1)
#define PIN_PC18__ISC_D9		PINMUX_PIN(PIN_PC18, 3, 1)
#define PIN_PC18__FLEXCOM3_IO2		PINMUX_PIN(PIN_PC18, 5, 2)
#define PIN_PC18__A7			PINMUX_PIN(PIN_PC18, 6, 2)
#define PIN_PC19			83
#define PIN_PC19__GPIO			PINMUX_PIN(PIN_PC19, 0, 0)
#define PIN_PC19__LCDDAT13		PINMUX_PIN(PIN_PC19, 1, 2)
#define PIN_PC19__GMDIO			PINMUX_PIN(PIN_PC19, 2, 1)
#define PIN_PC19__ISC_D10		PINMUX_PIN(PIN_PC19, 3, 1)
#define PIN_PC19__FLEXCOM3_IO1		PINMUX_PIN(PIN_PC19, 5, 2)
#define PIN_PC19__A8			PINMUX_PIN(PIN_PC19, 6, 2)
#define PIN_PC20			84
#define PIN_PC20__GPIO			PINMUX_PIN(PIN_PC20, 0, 0)
#define PIN_PC20__LCDDAT14		PINMUX_PIN(PIN_PC20, 1, 2)
#define PIN_PC20__GRXCK			PINMUX_PIN(PIN_PC20, 2, 1)
#define PIN_PC20__ISC_D11		PINMUX_PIN(PIN_PC20, 3, 1)
#define PIN_PC20__FLEXCOM3_IO0		PINMUX_PIN(PIN_PC20, 5, 2)
#define PIN_PC20__A9			PINMUX_PIN(PIN_PC20, 6, 2)
#define PIN_PC21			85
#define PIN_PC21__GPIO			PINMUX_PIN(PIN_PC21, 0, 0)
#define PIN_PC21__LCDDAT15		PINMUX_PIN(PIN_PC21, 1, 2)
#define PIN_PC21__GTXER			PINMUX_PIN(PIN_PC21, 2, 1)
#define PIN_PC21__ISC_PCK		PINMUX_PIN(PIN_PC21, 3, 1)
#define PIN_PC21__FLEXCOM3_IO3		PINMUX_PIN(PIN_PC21, 5, 2)
#define PIN_PC21__A10			PINMUX_PIN(PIN_PC21, 6, 2)
#define PIN_PC22			86
#define PIN_PC22__GPIO			PINMUX_PIN(PIN_PC22, 0, 0)
#define PIN_PC22__LCDDAT18		PINMUX_PIN(PIN_PC22, 1, 2)
#define PIN_PC22__GCRS			PINMUX_PIN(PIN_PC22, 2, 1)
#define PIN_PC22__ISC_VSYNC		PINMUX_PIN(PIN_PC22, 3, 1)
#define PIN_PC22__FLEXCOM3_IO4		PINMUX_PIN(PIN_PC22, 5, 2)
#define PIN_PC22__A11			PINMUX_PIN(PIN_PC22, 6, 2)
#define PIN_PC23			87
#define PIN_PC23__GPIO			PINMUX_PIN(PIN_PC23, 0, 0)
#define PIN_PC23__LCDDAT19		PINMUX_PIN(PIN_PC23, 1, 2)
#define PIN_PC23__GCOL			PINMUX_PIN(PIN_PC23, 2, 1)
#define PIN_PC23__ISC_HSYNC		PINMUX_PIN(PIN_PC23, 3, 1)
#define PIN_PC23__A12			PINMUX_PIN(PIN_PC23, 6, 2)
#define PIN_PC24			88
#define PIN_PC24__GPIO			PINMUX_PIN(PIN_PC24, 0, 0)
#define PIN_PC24__LCDDAT20		PINMUX_PIN(PIN_PC24, 1, 2)
#define PIN_PC24__GRX2			PINMUX_PIN(PIN_PC24, 2, 1)
#define PIN_PC24__ISC_MCK		PINMUX_PIN(PIN_PC24, 3, 1)
#define PIN_PC24__A13			PINMUX_PIN(PIN_PC24, 6, 2)
#define PIN_PC25			89
#define PIN_PC25__GPIO			PINMUX_PIN(PIN_PC25, 0, 0)
#define PIN_PC25__LCDDAT21		PINMUX_PIN(PIN_PC25, 1, 2)
#define PIN_PC25__GRX3			PINMUX_PIN(PIN_PC25, 2, 1)
#define PIN_PC25__ISC_FIELD		PINMUX_PIN(PIN_PC25, 3, 1)
#define PIN_PC25__A14			PINMUX_PIN(PIN_PC25, 6, 2)
#define PIN_PC26			90
#define PIN_PC26__GPIO			PINMUX_PIN(PIN_PC26, 0, 0)
#define PIN_PC26__LCDDAT22		PINMUX_PIN(PIN_PC26, 1, 2)
#define PIN_PC26__GTX2			PINMUX_PIN(PIN_PC26, 2, 1)
#define PIN_PC26__CANTX1		PINMUX_PIN(PIN_PC26, 4, 1)
#define PIN_PC26__A15			PINMUX_PIN(PIN_PC26, 6, 2)
#define PIN_PC27			91
#define PIN_PC27__GPIO			PINMUX_PIN(PIN_PC27, 0, 0)
#define PIN_PC27__LCDDAT23		PINMUX_PIN(PIN_PC27, 1, 2)
#define PIN_PC27__GTX3			PINMUX_PIN(PIN_PC27, 2, 1)
#define PIN_PC27__PCK1			PINMUX_PIN(PIN_PC27, 3, 2)
#define PIN_PC27__CANRX1		PINMUX_PIN(PIN_PC27, 4, 1)
#define PIN_PC27__TWD0			PINMUX_PIN(PIN_PC27, 5, 2)
#define PIN_PC27__A16			PINMUX_PIN(PIN_PC27, 6, 2)
#define PIN_PC28			92
#define PIN_PC28__GPIO			PINMUX_PIN(PIN_PC28, 0, 0)
#define PIN_PC28__LCDPWM		PINMUX_PIN(PIN_PC28, 1, 2)
#define PIN_PC28__FLEXCOM4_IO0		PINMUX_PIN(PIN_PC28, 2, 1)
#define PIN_PC28__PCK2			PINMUX_PIN(PIN_PC28, 3, 2)
#define PIN_PC28__TWCK0			PINMUX_PIN(PIN_PC28, 5, 2)
#define PIN_PC28__A17			PINMUX_PIN(PIN_PC28, 6, 2)
#define PIN_PC29			93
#define PIN_PC29__GPIO			PINMUX_PIN(PIN_PC29, 0, 0)
#define PIN_PC29__LCDDISP		PINMUX_PIN(PIN_PC29, 1, 2)
#define PIN_PC29__FLEXCOM4_IO1		PINMUX_PIN(PIN_PC29, 2, 1)
#define PIN_PC29__A18			PINMUX_PIN(PIN_PC29, 6, 2)
#define PIN_PC30			94
#define PIN_PC30__GPIO			PINMUX_PIN(PIN_PC30, 0, 0)
#define PIN_PC30__LCDVSYNC		PINMUX_PIN(PIN_PC30, 1, 2)
#define PIN_PC30__FLEXCOM4_IO2		PINMUX_PIN(PIN_PC30, 2, 1)
#define PIN_PC30__A19			PINMUX_PIN(PIN_PC30, 6, 2)
#define PIN_PC31			95
#define PIN_PC31__GPIO			PINMUX_PIN(PIN_PC31, 0, 0)
#define PIN_PC31__LCDHSYNC		PINMUX_PIN(PIN_PC31, 1, 2)
#define PIN_PC31__FLEXCOM4_IO3		PINMUX_PIN(PIN_PC31, 2, 1)
#define PIN_PC31__URXD3			PINMUX_PIN(PIN_PC31, 3, 2)
#define PIN_PC31__A20			PINMUX_PIN(PIN_PC31, 6, 2)
#define PIN_PD0				96
#define PIN_PD0__GPIO			PINMUX_PIN(PIN_PD0, 0, 0)
#define PIN_PD0__LCDPCK			PINMUX_PIN(PIN_PD0, 1, 2)
#define PIN_PD0__FLEXCOM4_IO4		PINMUX_PIN(PIN_PD0, 2, 1)
#define PIN_PD0__UTXD3			PINMUX_PIN(PIN_PD0, 3, 2)
#define PIN_PD0__GTSUCOMP		PINMUX_PIN(PIN_PD0, 4, 2)
#define PIN_PD0__A23			PINMUX_PIN(PIN_PD0, 6, 2)
#define PIN_PD1				97
#define PIN_PD1__GPIO			PINMUX_PIN(PIN_PD1, 0, 0)
#define PIN_PD1__LCDDEN			PINMUX_PIN(PIN_PD1, 1, 2)
#define PIN_PD1__GRXCK			PINMUX_PIN(PIN_PD1, 4, 2)
#define PIN_PD1__A24			PINMUX_PIN(PIN_PD1, 6, 2)
#define PIN_PD2				98
#define PIN_PD2__GPIO			PINMUX_PIN(PIN_PD2, 0, 0)
#define PIN_PD2__URXD1			PINMUX_PIN(PIN_PD2, 1, 1)
#define PIN_PD2__GTXER			PINMUX_PIN(PIN_PD2, 4, 2)
#define PIN_PD2__ISC_MCK		PINMUX_PIN(PIN_PD2, 5, 2)
#define PIN_PD2__A25			PINMUX_PIN(PIN_PD2, 6, 2)
#define PIN_PD3				99
#define PIN_PD3__GPIO			PINMUX_PIN(PIN_PD3, 0, 0)
#define PIN_PD3__UTXD1			PINMUX_PIN(PIN_PD3, 1, 1)
#define PIN_PD3__FIQ			PINMUX_PIN(PIN_PD3, 2, 2)
#define PIN_PD3__GCRS			PINMUX_PIN(PIN_PD3, 4, 2)
#define PIN_PD3__ISC_D11		PINMUX_PIN(PIN_PD3, 5, 2)
#define PIN_PD3__NWAIT			PINMUX_PIN(PIN_PD3, 6, 2)
#define PIN_PD4				100
#define PIN_PD4__GPIO			PINMUX_PIN(PIN_PD4, 0, 0)
#define PIN_PD4__TWD1			PINMUX_PIN(PIN_PD4, 1, 2)
#define PIN_PD4__URXD2			PINMUX_PIN(PIN_PD4, 2, 1)
#define PIN_PD4__GCOL			PINMUX_PIN(PIN_PD4, 4, 2)
#define PIN_PD4__ISC_D10		PINMUX_PIN(PIN_PD4, 5, 2)
#define PIN_PD4__NCS0			PINMUX_PIN(PIN_PD4, 6, 2)
#define PIN_PD5				101
#define PIN_PD5__GPIO			PINMUX_PIN(PIN_PD5, 0, 0)
#define PIN_PD5__TWCK1			PINMUX_PIN(PIN_PD5, 1, 2)
#define PIN_PD5__UTXD2			PINMUX_PIN(PIN_PD5, 2, 1)
#define PIN_PD5__GRX2			PINMUX_PIN(PIN_PD5, 4, 2)
#define PIN_PD5__ISC_D9			PINMUX_PIN(PIN_PD5, 5, 2)
#define PIN_PD5__NCS1			PINMUX_PIN(PIN_PD5, 6, 2)
#define PIN_PD6				102
#define PIN_PD6__GPIO			PINMUX_PIN(PIN_PD6, 0, 0)
#define PIN_PD6__TCK			PINMUX_PIN(PIN_PD6, 1, 2)
#define PIN_PD6__PCK1			PINMUX_PIN(PIN_PD6, 2, 1)
#define PIN_PD6__GRX3			PINMUX_PIN(PIN_PD6, 4, 2)
#define PIN_PD6__ISC_D8			PINMUX_PIN(PIN_PD6, 5, 2)
#define PIN_PD6__NCS2			PINMUX_PIN(PIN_PD6, 6, 2)
#define PIN_PD7				103
#define PIN_PD7__GPIO			PINMUX_PIN(PIN_PD7, 0, 0)
#define PIN_PD7__TDI			PINMUX_PIN(PIN_PD7, 1, 2)
#define PIN_PD7__UTMI_RXVAL		PINMUX_PIN(PIN_PD7, 3, 1)
#define PIN_PD7__GTX2			PINMUX_PIN(PIN_PD7, 4, 2)
#define PIN_PD7__ISC_D0			PINMUX_PIN(PIN_PD7, 5, 2)
#define PIN_PD7__NWR1_NBS1		PINMUX_PIN(PIN_PD7, 6, 2)
#define PIN_PD8				104
#define PIN_PD8__GPIO			PINMUX_PIN(PIN_PD8, 0, 0)
#define PIN_PD8__TDO			PINMUX_PIN(PIN_PD8, 1, 2)
#define PIN_PD8__UTMI_RXERR		PINMUX_PIN(PIN_PD8, 3, 1)
#define PIN_PD8__GTX3			PINMUX_PIN(PIN_PD8, 4, 2)
#define PIN_PD8__ISC_D1			PINMUX_PIN(PIN_PD8, 5, 2)
#define PIN_PD8__NANDRDY		PINMUX_PIN(PIN_PD8, 6, 2)
#define PIN_PD9				105
#define PIN_PD9__GPIO			PINMUX_PIN(PIN_PD9, 0, 0)
#define PIN_PD9__TMS			PINMUX_PIN(PIN_PD9, 1, 2)
#define PIN_PD9__UTMI_RXACT		PINMUX_PIN(PIN_PD9, 3, 1)
#define PIN_PD9__GTXCK			PINMUX_PIN(PIN_PD9, 4, 2)
#define PIN_PD9__ISC_D2			PINMUX_PIN(PIN_PD9, 5, 2)
#define PIN_PD10			106
#define PIN_PD10__GPIO			PINMUX_PIN(PIN_PD10, 0, 0)
#define PIN_PD10__NTRST			PINMUX_PIN(PIN_PD10, 1, 2)
#define PIN_PD10__UTMI_HDIS		PINMUX_PIN(PIN_PD10, 3, 1)
#define PIN_PD10__GTXEN			PINMUX_PIN(PIN_PD10, 4, 2)
#define PIN_PD10__ISC_D3		PINMUX_PIN(PIN_PD10, 5, 2)
#define PIN_PD11			107
#define PIN_PD11__GPIO			PINMUX_PIN(PIN_PD11, 0, 0)
#define PIN_PD11__TIOA1			PINMUX_PIN(PIN_PD11, 1, 3)
#define PIN_PD11__PCK2			PINMUX_PIN(PIN_PD11, 2, 2)
#define PIN_PD11__UTMI_LS0		PINMUX_PIN(PIN_PD11, 3, 1)
#define PIN_PD11__GRXDV			PINMUX_PIN(PIN_PD11, 4, 2)
#define PIN_PD11__ISC_D4		PINMUX_PIN(PIN_PD11, 5, 2)
#define PIN_PD11__ISC_MCK		PINMUX_PIN(PIN_PD11, 7, 4)
#define PIN_PD12			108
#define PIN_PD12__GPIO			PINMUX_PIN(PIN_PD12, 0, 0)
#define PIN_PD12__TIOB1			PINMUX_PIN(PIN_PD12, 1, 3)
#define PIN_PD12__FLEXCOM4_IO0		PINMUX_PIN(PIN_PD12, 2, 2)
#define PIN_PD12__UTMI_LS1		PINMUX_PIN(PIN_PD12, 3, 1)
#define PIN_PD12__GRXER			PINMUX_PIN(PIN_PD12, 4, 2)
#define PIN_PD12__ISC_D5		PINMUX_PIN(PIN_PD12, 5, 2)
#define PIN_PD12__ISC_D4		PINMUX_PIN(PIN_PD12, 6, 4)
#define PIN_PD13			109
#define PIN_PD13__GPIO			PINMUX_PIN(PIN_PD13, 0, 0)
#define PIN_PD13__TCLK1			PINMUX_PIN(PIN_PD13, 1, 3)
#define PIN_PD13__FLEXCOM4_IO1		PINMUX_PIN(PIN_PD13, 2, 2)
#define PIN_PD13__UTMI_CDRPCSEL0	PINMUX_PIN(PIN_PD13, 3, 1)
#define PIN_PD13__GRX0			PINMUX_PIN(PIN_PD13, 4, 2)
#define PIN_PD13__ISC_D6		PINMUX_PIN(PIN_PD13, 5, 2)
#define PIN_PD13__ISC_D5		PINMUX_PIN(PIN_PD13, 6, 4)
#define PIN_PD14			110
#define PIN_PD14__GPIO			PINMUX_PIN(PIN_PD14, 0, 0)
#define PIN_PD14__TCK			PINMUX_PIN(PIN_PD14, 1, 1)
#define PIN_PD14__FLEXCOM4_IO2		PINMUX_PIN(PIN_PD14, 2, 2)
#define PIN_PD14__UTMI_CDRPCSEL1	PINMUX_PIN(PIN_PD14, 3, 1)
#define PIN_PD14__GRX1			PINMUX_PIN(PIN_PD14, 4, 2)
#define PIN_PD14__ISC_D7		PINMUX_PIN(PIN_PD14, 5, 2)
#define PIN_PD14__ISC_D6		PINMUX_PIN(PIN_PD14, 6, 4)
#define PIN_PD15			111
#define PIN_PD15__GPIO			PINMUX_PIN(PIN_PD15, 0, 0)
#define PIN_PD15__TDI			PINMUX_PIN(PIN_PD15, 1, 1)
#define PIN_PD15__FLEXCOM4_IO3		PINMUX_PIN(PIN_PD15, 2, 2)
#define PIN_PD15__UTMI_CDRCPDIVEN	PINMUX_PIN(PIN_PD15, 3, 1)
#define PIN_PD15__GTX0			PINMUX_PIN(PIN_PD15, 4, 2)
#define PIN_PD15__ISC_PCK		PINMUX_PIN(PIN_PD15, 5, 2)
#define PIN_PD15__ISC_D7		PINMUX_PIN(PIN_PD15, 6, 4)
#define PIN_PD16			112
#define PIN_PD16__GPIO			PINMUX_PIN(PIN_PD16, 0, 0)
#define PIN_PD16__TDO			PINMUX_PIN(PIN_PD16, 1, 1)
#define PIN_PD16__FLEXCOM4_IO4		PINMUX_PIN(PIN_PD16, 2, 2)
#define PIN_PD16__UTMI_CDRBISTEN	PINMUX_PIN(PIN_PD16, 3, 1)
#define PIN_PD16__GTX1			PINMUX_PIN(PIN_PD16, 4, 2)
#define PIN_PD16__ISC_VSYNC		PINMUX_PIN(PIN_PD16, 5, 2)
#define PIN_PD16__ISC_D8		PINMUX_PIN(PIN_PD16, 6, 4)
#define PIN_PD17			113
#define PIN_PD17__GPIO			PINMUX_PIN(PIN_PD17, 0, 0)
#define PIN_PD17__TMS			PINMUX_PIN(PIN_PD17, 1, 1)
#define PIN_PD17__UTMI_CDRCPSELDIV	PINMUX_PIN(PIN_PD17, 3, 1)
#define PIN_PD17__GMDC			PINMUX_PIN(PIN_PD17, 4, 2)
#define PIN_PD17__ISC_HSYNC		PINMUX_PIN(PIN_PD17, 5, 2)
#define PIN_PD17__ISC_D9		PINMUX_PIN(PIN_PD17, 6, 4)
#define PIN_PD18			114
#define PIN_PD18__GPIO			PINMUX_PIN(PIN_PD18, 0, 0)
#define PIN_PD18__NTRST			PINMUX_PIN(PIN_PD18, 1, 1)
#define PIN_PD18__GMDIO			PINMUX_PIN(PIN_PD18, 4, 2)
#define PIN_PD18__ISC_FIELD		PINMUX_PIN(PIN_PD18, 5, 2)
#define PIN_PD18__ISC_D10		PINMUX_PIN(PIN_PD18, 6, 4)
#define PIN_PD19			115
#define PIN_PD19__GPIO			PINMUX_PIN(PIN_PD19, 0, 0)
#define PIN_PD19__PCK0			PINMUX_PIN(PIN_PD19, 1, 1)
#define PIN_PD19__TWD1			PINMUX_PIN(PIN_PD19, 2, 3)
#define PIN_PD19__URXD2			PINMUX_PIN(PIN_PD19, 3, 3)
#define PIN_PD19__I2SC0_CK		PINMUX_PIN(PIN_PD19, 5, 2)
#define PIN_PD19__ISC_D11		PINMUX_PIN(PIN_PD19, 6, 4)
#define PIN_PD20			116
#define PIN_PD20__GPIO			PINMUX_PIN(PIN_PD20, 0, 0)
#define PIN_PD20__TIOA2			PINMUX_PIN(PIN_PD20, 1, 3)
#define PIN_PD20__TWCK1			PINMUX_PIN(PIN_PD20, 2, 3)
#define PIN_PD20__UTXD2			PINMUX_PIN(PIN_PD20, 3, 3)
#define PIN_PD20__I2SC0_MCK		PINMUX_PIN(PIN_PD20, 5, 2)
#define PIN_PD20__ISC_PCK		PINMUX_PIN(PIN_PD20, 6, 4)
#define PIN_PD21			117
#define PIN_PD21__GPIO			PINMUX_PIN(PIN_PD21, 0, 0)
#define PIN_PD21__TIOB2			PINMUX_PIN(PIN_PD21, 1, 3)
#define PIN_PD21__TWD0			PINMUX_PIN(PIN_PD21, 2, 4)
#define PIN_PD21__FLEXCOM4_IO0		PINMUX_PIN(PIN_PD21, 3, 3)
#define PIN_PD21__I2SC0_WS		PINMUX_PIN(PIN_PD21, 5, 2)
#define PIN_PD21__ISC_VSYNC		PINMUX_PIN(PIN_PD21, 6, 4)
#define PIN_PD22			118
#define PIN_PD22__GPIO			PINMUX_PIN(PIN_PD22, 0, 0)
#define PIN_PD22__TCLK2			PINMUX_PIN(PIN_PD22, 1, 3)
#define PIN_PD22__TWCK0			PINMUX_PIN(PIN_PD22, 2, 4)
#define PIN_PD22__FLEXCOM4_IO1		PINMUX_PIN(PIN_PD22, 3, 3)
#define PIN_PD22__I2SC0_DI0		PINMUX_PIN(PIN_PD22, 5, 2)
#define PIN_PD22__ISC_HSYNC		PINMUX_PIN(PIN_PD22, 6, 4)
#define PIN_PD23			119
#define PIN_PD23__GPIO			PINMUX_PIN(PIN_PD23, 0, 0)
#define PIN_PD23__URXD2			PINMUX_PIN(PIN_PD23, 1, 2)
#define PIN_PD23__FLEXCOM4_IO2		PINMUX_PIN(PIN_PD23, 3, 3)
#define PIN_PD23__I2SC0_DO0		PINMUX_PIN(PIN_PD23, 5, 2)
#define PIN_PD23__ISC_FIELD		PINMUX_PIN(PIN_PD23, 6, 4)
#define PIN_PD24			120
#define PIN_PD24__GPIO			PINMUX_PIN(PIN_PD24, 0, 0)
#define PIN_PD24__UTXD2			PINMUX_PIN(PIN_PD24, 1, 2)
#define PIN_PD24__FLEXCOM4_IO3		PINMUX_PIN(PIN_PD24, 3, 3)
#define PIN_PD25			121
#define PIN_PD25__GPIO			PINMUX_PIN(PIN_PD25, 0, 0)
#define PIN_PD25__SPI1_SPCK		PINMUX_PIN(PIN_PD25, 1, 3)
#define PIN_PD25__FLEXCOM4_IO4		PINMUX_PIN(PIN_PD25, 3, 3)
#define PIN_PD26			122
#define PIN_PD26__GPIO			PINMUX_PIN(PIN_PD26, 0, 0)
#define PIN_PD26__SPI1_MOSI		PINMUX_PIN(PIN_PD26, 1, 3)
#define PIN_PD26__FLEXCOM2_IO0		PINMUX_PIN(PIN_PD26, 3, 2)
#define PIN_PD27			123
#define PIN_PD27__GPIO			PINMUX_PIN(PIN_PD27, 0, 0)
#define PIN_PD27__SPI1_MISO		PINMUX_PIN(PIN_PD27, 1, 3)
#define PIN_PD27__TCK			PINMUX_PIN(PIN_PD27, 2, 3)
#define PIN_PD27__FLEXCOM2_IO1		PINMUX_PIN(PIN_PD27, 3, 2)
#define PIN_PD28			124
#define PIN_PD28__GPIO			PINMUX_PIN(PIN_PD28, 0, 0)
#define PIN_PD28__SPI1_NPCS0		PINMUX_PIN(PIN_PD28, 1, 3)
#define PIN_PD28__TCI			PINMUX_PIN(PIN_PD28, 2, 3)
#define PIN_PD28__FLEXCOM2_IO2		PINMUX_PIN(PIN_PD28, 3, 2)
#define PIN_PD29			125
#define PIN_PD29__GPIO			PINMUX_PIN(PIN_PD29, 0, 0)
#define PIN_PD29__SPI1_NPCS1		PINMUX_PIN(PIN_PD29, 1, 3)
#define PIN_PD29__TDO			PINMUX_PIN(PIN_PD29, 2, 3)
#define PIN_PD29__FLEXCOM2_IO3		PINMUX_PIN(PIN_PD29, 3, 2)
#define PIN_PD29__TIOA3			PINMUX_PIN(PIN_PD29, 4, 3)
#define PIN_PD29__TWD0			PINMUX_PIN(PIN_PD29, 5, 3)
#define PIN_PD30			126
#define PIN_PD30__GPIO			PINMUX_PIN(PIN_PD30, 0, 0)
#define PIN_PD30__SPI1_NPCS2		PINMUX_PIN(PIN_PD30, 1, 3)
#define PIN_PD30__TMS			PINMUX_PIN(PIN_PD30, 2, 3)
#define PIN_PD30__FLEXCOM2_IO4		PINMUX_PIN(PIN_PD30, 3, 2)
#define PIN_PD30__TIOB3			PINMUX_PIN(PIN_PD30, 4, 3)
#define PIN_PD30__TWCK0			PINMUX_PIN(PIN_PD30, 5, 3)
#define PIN_PD31			127
#define PIN_PD31__GPIO			PINMUX_PIN(PIN_PD31, 0, 0)
#define PIN_PD31__ADTRG			PINMUX_PIN(PIN_PD31, 1, 1)
#define PIN_PD31__NTRST			PINMUX_PIN(PIN_PD31, 2, 3)
#define PIN_PD31__IRQ			PINMUX_PIN(PIN_PD31, 3, 4)
#define PIN_PD31__TCLK3			PINMUX_PIN(PIN_PD31, 4, 3)
#define PIN_PD31__PCK0			PINMUX_PIN(PIN_PD31, 5, 2)

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
 *
 *  Copyright (C) 2015 Atmel,
 *                2015 Ludovic Desroches <ludovic.desroches@atmel.com>
 */

#include <dt-bindings/dma/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Atmel SAMA5D2 family SoC";
	compatible = "atmel,sama5d2";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a5";
			reg = <0>;
			next-level-cache = <&L2>;
		};
	};

	pmu {
		compatible = "arm,cortex-a5-pmu";
		interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	etb@740000 {
		compatible = "arm,coresight-etb10", "arm,primecell";
		reg = <0x740000 0x1000>;

		clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
		clock-names = "apb_pclk";

		in-ports {
			port {
				etb_in: endpoint {
					remote-endpoint = <&etm_out>;
				};
			};
		};
	};

	etm@73c000 {
		compatible = "arm,coresight-etm3x", "arm,primecell";
		reg = <0x73c000 0x1000>;

		clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
		clock-names = "apb_pclk";

		out-ports {
			port {
				etm_out: endpoint {
					remote-endpoint = <&etb_in>;
				};
			};
		};
	};

	memory@20000000 {
		device_type = "memory";
		reg = <0x20000000 0x20000000>;
	};

	clocks {
		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};
	};

	ns_sram: sram@200000 {
		compatible = "mmio-sram";
		reg = <0x00200000 0x20000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x00200000 0x20000>;
	};

	resistive_touch: resistive-touch {
		compatible = "resistive-adc-touch";
		io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
			      <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
			      <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
		io-channel-names = "x", "y", "pressure";
		touchscreen-min-pressure = <50000>;
		status = "disabled";
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		nfc_sram: sram@100000 {
			compatible = "mmio-sram";
			no-memory-wc;
			reg = <0x00100000 0x2400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x00100000 0x2400>;

		};

		usb0: gadget@300000 {
			compatible = "atmel,sama5d3-udc";
			reg = <0x00300000 0x100000
			       0xfc02c000 0x400>;
			interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
			clock-names = "pclk", "hclk";
			status = "disabled";
		};

		usb1: ohci@400000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00400000 0x100000>;
			interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>;
			clock-names = "ohci_clk", "hclk", "uhpck";
			status = "disabled";
		};

		usb2: ehci@500000 {
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00500000 0x100000>;
			interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
			clock-names = "usb_clk", "ehci_clk";
			status = "disabled";
		};

		L2: cache-controller@a00000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a00000 0x1000>;
			interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
			cache-unified;
			cache-level = <2>;
		};

		ebi: ebi@10000000 {
			compatible = "atmel,sama5d3-ebi";
			#address-cells = <2>;
			#size-cells = <1>;
			atmel,smc = <&hsmc>;
			reg = <0x10000000 0x10000000
			       0x60000000 0x30000000>;
			ranges = <0x0 0x0 0x10000000 0x10000000
				  0x1 0x0 0x60000000 0x10000000
				  0x2 0x0 0x70000000 0x10000000
				  0x3 0x0 0x80000000 0x10000000>;
			clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
			status = "disabled";

			nand_controller: nand-controller {
				compatible = "atmel,sama5d3-nand-controller";
				atmel,nfc-sram = <&nfc_sram>;
				atmel,nfc-io = <&nfc_io>;
				ecc-engine = <&pmecc>;
				#address-cells = <2>;
				#size-cells = <1>;
				ranges;
				status = "disabled";
			};
		};

		sdmmc0: sdio-host@a0000000 {
			compatible = "atmel,sama5d2-sdhci";
			reg = <0xa0000000 0x300>;
			interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
			clock-names = "hclock", "multclk", "baseclk";
			assigned-clocks = <&pmc PMC_TYPE_GCK 31>;
			assigned-clock-rates = <480000000>;
			status = "disabled";
		};

		sdmmc1: sdio-host@b0000000 {
			compatible = "atmel,sama5d2-sdhci";
			reg = <0xb0000000 0x300>;
			interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
			clock-names = "hclock", "multclk", "baseclk";
			assigned-clocks = <&pmc PMC_TYPE_GCK 32>;
			assigned-clock-rates = <480000000>;
			status = "disabled";
		};

		nfc_io: nfc-io@c0000000 {
			compatible = "atmel,sama5d3-nfc-io", "syscon";
			reg = <0xc0000000 0x8000000>;
		};

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			hlcdc: hlcdc@f0000000 {
				compatible = "atmel,sama5d2-hlcdc";
				reg = <0xf0000000 0x2000>;
				interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
				clock-names = "periph_clk","sys_clk", "slow_clk";
				status = "disabled";

				hlcdc-display-controller {
					compatible = "atmel,hlcdc-display-controller";
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						#address-cells = <1>;
						#size-cells = <0>;
						reg = <0>;
					};
				};

				hlcdc_pwm: hlcdc-pwm {
					compatible = "atmel,hlcdc-pwm";
					#pwm-cells = <3>;
				};
			};

			isc: isc@f0008000 {
				compatible = "atmel,sama5d2-isc";
				reg = <0xf0008000 0x4000>;
				interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>;
				clock-names = "hclock", "iscck", "gck";
				#clock-cells = <0>;
				clock-output-names = "isc-mck";
				status = "disabled";
			};

			ramc0: ramc@f000c000 {
				compatible = "atmel,sama5d3-ddramc";
				reg = <0xf000c000 0x200>;
				clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>;
				clock-names = "ddrck", "mpddr";
			};

			dma0: dma-controller@f0010000 {
				compatible = "atmel,sama5d4-dma";
				reg = <0xf0010000 0x1000>;
				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
				#dma-cells = <1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
				clock-names = "dma_clk";
			};

			/* Place dma1 here despite its address */
			dma1: dma-controller@f0004000 {
				compatible = "atmel,sama5d4-dma";
				reg = <0xf0004000 0x1000>;
				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
				#dma-cells = <1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
				clock-names = "dma_clk";
			};

			pmc: pmc@f0014000 {
				compatible = "atmel,sama5d2-pmc", "syscon";
				reg = <0xf0014000 0x160>;
				interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
				#clock-cells = <2>;
				clocks = <&clk32k>, <&main_xtal>;
				clock-names = "slow_clk", "main_xtal";
			};

			qspi0: spi@f0020000 {
				compatible = "atmel,sama5d2-qspi";
				reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
				reg-names = "qspi_base", "qspi_mmap";
				interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
				clock-names = "pclk";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			qspi1: spi@f0024000 {
				compatible = "atmel,sama5d2-qspi";
				reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
				reg-names = "qspi_base", "qspi_mmap";
				interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
				clock-names = "pclk";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			sha: crypto@f0028000 {
				compatible = "atmel,at91sam9g46-sha";
				reg = <0xf0028000 0x100>;
				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(30))>;
				dma-names = "tx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
				clock-names = "sha_clk";
			};

			aes: crypto@f002c000 {
				compatible = "atmel,at91sam9g46-aes";
				reg = <0xf002c000 0x100>;
				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(26))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(27))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
				clock-names = "aes_clk";
			};

			spi0: spi@f8000000 {
				compatible = "atmel,at91rm9200-spi";
				reg = <0xf8000000 0x100>;
				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(6))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(7))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
				clock-names = "spi_clk";
				atmel,fifo-size = <16>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			ssc0: ssc@f8004000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xf8004000 0x4000>;
				interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					AT91_XDMAC_DT_PERID(21))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					AT91_XDMAC_DT_PERID(22))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
				clock-names = "pclk";
				status = "disabled";
			};

			macb0: ethernet@f8008000 {
				compatible = "atmel,sama5d2-gem";
				reg = <0xf8008000 0x1000>;
				interrupts = <5  IRQ_TYPE_LEVEL_HIGH 3		/* Queue 0 */
					      66 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 1 */
					      67 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 2 */
				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};

			tcb0: timer@f800c000 {
				compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0xf800c000 0x100>;
				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>;
				clock-names = "t0_clk", "gclk", "slow_clk";
			};

			tcb1: timer@f8010000 {
				compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0xf8010000 0x100>;
				interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>;
				clock-names = "t0_clk", "gclk", "slow_clk";
			};

			hsmc: hsmc@f8014000 {
				compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
				reg = <0xf8014000 0x1000>;
				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;

				pmecc: ecc-engine@f8014070 {
					compatible = "atmel,sama5d2-pmecc";
					reg = <0xf8014070 0x490>,
					      <0xf8014500 0x200>;
				};
			};

			pdmic: pdmic@f8018000 {
				compatible = "atmel,sama5d2-pdmic";
				reg = <0xf8018000 0x124>;
				interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
					| AT91_XDMAC_DT_PERID(50))>;
				dma-names = "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>;
				clock-names = "pclk", "gclk";
				status = "disabled";
			};

			uart0: serial@f801c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf801c000 0x100>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(35))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(36))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
				clock-names = "usart";
				status = "disabled";
			};

			uart1: serial@f8020000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8020000 0x100>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(37))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(38))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
				clock-names = "usart";
				status = "disabled";
			};

			uart2: serial@f8024000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8024000 0x100>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(39))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(40))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
				clock-names = "usart";
				status = "disabled";
			};

			i2c0: i2c@f8028000 {
				compatible = "atmel,sama5d2-i2c";
				reg = <0xf8028000 0x100>;
				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(0))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(1))>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
				atmel,fifo-size = <16>;
				status = "disabled";
			};

			pwm0: pwm@f802c000 {
				compatible = "atmel,sama5d2-pwm";
				reg = <0xf802c000 0x4000>;
				interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
				#pwm-cells = <3>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
				status = "disabled";
			};

			sfr: sfr@f8030000 {
				compatible = "atmel,sama5d2-sfr", "syscon";
				reg = <0xf8030000 0x98>;
			};

			flx0: flexcom@f8034000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf8034000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf8034000 0x800>;
				status = "disabled";

				uart5: serial@200 {
					compatible = "atmel,at91sam9260-usart";
					reg = <0x200 0x200>;
					atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
					interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
					clock-names = "usart";
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(11))>,
					       <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(12))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <32>;
					status = "disabled";
				};

				spi2: spi@400 {
					compatible = "atmel,at91rm9200-spi";
					reg = <0x400 0x200>;
					interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
					clock-names = "spi_clk";
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(11))>,
					       <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(12))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <16>;
					status = "disabled";
				};

				i2c2: i2c@600 {
					compatible = "atmel,sama5d2-i2c";
					reg = <0x600 0x200>;
					interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(11))>,
					       <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(12))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <16>;
					status = "disabled";
				};
			};

			flx1: flexcom@f8038000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xf8038000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xf8038000 0x800>;
				status = "disabled";

				uart6: serial@200 {
					compatible = "atmel,at91sam9260-usart";
					reg = <0x200 0x200>;
					atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
					interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
					clock-names = "usart";
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(13))>,
					       <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(14))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <32>;
					status = "disabled";
				};

				spi3: spi@400 {
					compatible = "atmel,at91rm9200-spi";
					reg = <0x400 0x200>;
					interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
					clock-names = "spi_clk";
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(13))>,
					       <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(14))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <16>;
					status = "disabled";
				};

				i2c3: i2c@600 {
					compatible = "atmel,sama5d2-i2c";
					reg = <0x600 0x200>;
					interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(13))>,
					       <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(14))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <16>;
					status = "disabled";
				};
			};

			securam: sram@f8044000 {
				compatible = "atmel,sama5d2-securam", "mmio-sram";
				reg = <0xf8044000 0x1420>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
				#address-cells = <1>;
				#size-cells = <1>;
				no-memory-wc;
				ranges = <0 0xf8044000 0x1420>;
			};

			reset_controller: reset-controller@f8048000 {
				compatible = "atmel,sama5d3-rstc";
				reg = <0xf8048000 0x10>;
				clocks = <&clk32k>;
			};

			shutdown_controller: shdwc@f8048010 {
				compatible = "atmel,sama5d2-shdwc";
				reg = <0xf8048010 0x10>;
				clocks = <&clk32k>;
				#address-cells = <1>;
				#size-cells = <0>;
				atmel,wakeup-rtc-timer;
			};

			pit: timer@f8048030 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xf8048030 0x10>;
				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
				clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
			};

			watchdog: watchdog@f8048040 {
				compatible = "atmel,sama5d4-wdt";
				reg = <0xf8048040 0x10>;
				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k>;
				status = "disabled";
			};

			clk32k: sckc@f8048050 {
				compatible = "atmel,sama5d4-sckc";
				reg = <0xf8048050 0x4>;

				clocks = <&slow_xtal>;
				#clock-cells = <0>;
			};

			rtc: rtc@f80480b0 {
				compatible = "atmel,sama5d2-rtc";
				reg = <0xf80480b0 0x30>;
				interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k>;
			};

			i2s0: i2s@f8050000 {
				compatible = "atmel,sama5d2-i2s";
				reg = <0xf8050000 0x100>;
				interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(31))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(32))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>;
				clock-names = "pclk", "gclk";
				assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>;
				assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>;
				status = "disabled";
			};

			can0: can@f8054000 {
				compatible = "bosch,m_can";
				reg = <0xf8054000 0x4000>, <0x210000 0x1c00>;
				reg-names = "m_can", "message_ram";
				interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
					     <64 IRQ_TYPE_LEVEL_HIGH 7>;
				interrupt-names = "int0", "int1";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
				clock-names = "hclk", "cclk";
				assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
				assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
				assigned-clock-rates = <40000000>;
				bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
				status = "disabled";
			};

			spi1: spi@fc000000 {
				compatible = "atmel,at91rm9200-spi";
				reg = <0xfc000000 0x100>;
				interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(8))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(9))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
				clock-names = "spi_clk";
				atmel,fifo-size = <16>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			uart3: serial@fc008000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc008000 0x100>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(41))>,
				       <&dma1
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(42))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
				clock-names = "usart";
				status = "disabled";
			};

			uart4: serial@fc00c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfc00c000 0x100>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(43))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(44))>;
				dma-names = "tx", "rx";
				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
				clock-names = "usart";
				status = "disabled";
			};

			flx2: flexcom@fc010000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xfc010000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xfc010000 0x800>;
				status = "disabled";

				uart7: serial@200 {
					compatible = "atmel,at91sam9260-usart";
					reg = <0x200 0x200>;
					atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
					interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
					clock-names = "usart";
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(15))>,
						<&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(16))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <32>;
					status = "disabled";
				};

				spi4: spi@400 {
					compatible = "atmel,at91rm9200-spi";
					reg = <0x400 0x200>;
					interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
					clock-names = "spi_clk";
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(15))>,
						<&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(16))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <16>;
					status = "disabled";
				};

				i2c4: i2c@600 {
					compatible = "atmel,sama5d2-i2c";
					reg = <0x600 0x200>;
					interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(15))>,
						<&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(16))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <16>;
					status = "disabled";
				};
			};

			flx3: flexcom@fc014000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xfc014000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xfc014000 0x800>;
				status = "disabled";

				uart8: serial@200 {
					compatible = "atmel,at91sam9260-usart";
					reg = <0x200 0x200>;
					atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
					interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
					clock-names = "usart";
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(17))>,
					       <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(18))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <32>;
					status = "disabled";
				};

				spi5: spi@400 {
					compatible = "atmel,at91rm9200-spi";
					reg = <0x400 0x200>;
					interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
					clock-names = "spi_clk";
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(17))>,
					       <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(18))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <16>;
					status = "disabled";
				};

				i2c5: i2c@600 {
					compatible = "atmel,sama5d2-i2c";
					reg = <0x600 0x200>;
					interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(17))>,
					       <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(18))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <16>;
					status = "disabled";
				};

			};

			flx4: flexcom@fc018000 {
				compatible = "atmel,sama5d2-flexcom";
				reg = <0xfc018000 0x200>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0xfc018000 0x800>;
				status = "disabled";

				uart9: serial@200 {
					compatible = "atmel,at91sam9260-usart";
					reg = <0x200 0x200>;
					atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
					interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
					clock-names = "usart";
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(19))>,
					       <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(20))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <32>;
					status = "disabled";
				};

				spi6: spi@400 {
					compatible = "atmel,at91rm9200-spi";
					reg = <0x400 0x200>;
					interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
					clock-names = "spi_clk";
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(19))>,
					       <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(20))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <16>;
					status = "disabled";
				};

				i2c6: i2c@600 {
					compatible = "atmel,sama5d2-i2c";
					reg = <0x600 0x200>;
					interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
					dmas = <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(19))>,
					       <&dma0
						(AT91_XDMAC_DT_MEM_IF(0) |
						 AT91_XDMAC_DT_PER_IF(1) |
						 AT91_XDMAC_DT_PERID(20))>;
					dma-names = "tx", "rx";
					atmel,fifo-size = <16>;
					status = "disabled";
				};
			};

			trng@fc01c000 {
				compatible = "atmel,at91sam9g45-trng";
				reg = <0xfc01c000 0x100>;
				interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
			};

			aic: interrupt-controller@fc020000 {
				#interrupt-cells = <3>;
				compatible = "atmel,sama5d2-aic";
				interrupt-controller;
				reg = <0xfc020000 0x200>;
				atmel,external-irqs = <49>;
			};

			i2c1: i2c@fc028000 {
				compatible = "atmel,sama5d2-i2c";
				reg = <0xfc028000 0x100>;
				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(2))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(3))>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
				atmel,fifo-size = <16>;
				status = "disabled";
			};

			adc: adc@fc030000 {
				compatible = "atmel,sama5d2-adc";
				reg = <0xfc030000 0x100>;
				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
				clock-names = "adc_clk";
				dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
				dma-names = "rx";
				atmel,min-sample-rate-hz = <200000>;
				atmel,max-sample-rate-hz = <20000000>;
				atmel,startup-time-ms = <4>;
				atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
				#io-channel-cells = <1>;
				status = "disabled";
			};

			pioA: pinctrl@fc038000 {
				compatible = "atmel,sama5d2-pinctrl";
				reg = <0xfc038000 0x600>;
				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
					     <68 IRQ_TYPE_LEVEL_HIGH 7>,
					     <69 IRQ_TYPE_LEVEL_HIGH 7>,
					     <70 IRQ_TYPE_LEVEL_HIGH 7>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-controller;
				#gpio-cells = <2>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
			};

			pioBU: secumod@fc040000 {
				compatible = "atmel,sama5d2-secumod", "syscon";
				reg = <0xfc040000 0x100>;

				gpio-controller;
				#gpio-cells = <2>;
			};

			tdes: crypto@fc044000 {
				compatible = "atmel,at91sam9g46-tdes";
				reg = <0xfc044000 0x100>;
				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(28))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(29))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
				clock-names = "tdes_clk";
			};

			classd: classd@fc048000 {
				compatible = "atmel,sama5d2-classd";
				reg = <0xfc048000 0x100>;
				interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(47))>;
				dma-names = "tx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
				clock-names = "pclk", "gclk";
				status = "disabled";
			};

			i2s1: i2s@fc04c000 {
				compatible = "atmel,sama5d2-i2s";
				reg = <0xfc04c000 0x100>;
				interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
				dmas = <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(33))>,
				       <&dma0
					(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
					 AT91_XDMAC_DT_PERID(34))>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
				clock-names = "pclk", "gclk";
				assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
				assigned-clock-parents = <&pmc PMC_TYPE_GCK 55>;
				status = "disabled";
			};

			can1: can@fc050000 {
				compatible = "bosch,m_can";
				reg = <0xfc050000 0x4000>, <0x210000 0x3800>;
				reg-names = "m_can", "message_ram";
				interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
					     <65 IRQ_TYPE_LEVEL_HIGH 7>;
				interrupt-names = "int0", "int1";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
				clock-names = "hclk", "cclk";
				assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
				assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
				assigned-clock-rates = <40000000>;
				bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>;
				status = "disabled";
			};

			sfrbu: sfr@fc05c000 {
				compatible = "atmel,sama5d2-sfrbu", "syscon";
				reg = <0xfc05c000 0x20>;
			};

			chipid@fc069000 {
				compatible = "atmel,sama5d2-chipid";
				reg = <0xfc069000 0x8>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * sama5d29.dtsi - Device Tree Include file for SAMA5D29 SoC of the SAMA5D2
 * family.
 *
 *  Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
 *
 *  Author: Hari Prasath <Hari.PrasathGE@microchip.com>
 *
 */

#include "sama5d2.dtsi"

&macb0 {
	compatible = "atmel,sama5d29-gem";
};