code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Eddie Huang <eddie.huang@mediatek.com>
 */

#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt8173-larb-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8173-power.h>
#include <dt-bindings/reset/mt8173-resets.h>
#include <dt-bindings/gce/mt8173-gce.h>
#include <dt-bindings/thermal/thermal.h>
#include "mt8173-pinfunc.h"

/ {
	compatible = "mediatek,mt8173";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ovl0 = &ovl0;
		ovl1 = &ovl1;
		rdma0 = &rdma0;
		rdma1 = &rdma1;
		rdma2 = &rdma2;
		wdma0 = &wdma0;
		wdma1 = &wdma1;
		color0 = &color0;
		color1 = &color1;
		split0 = &split0;
		split1 = &split1;
		dpi0 = &dpi0;
		dsi0 = &dsi0;
		dsi1 = &dsi1;
		mdp-rdma0 = &mdp_rdma0;
		mdp-rdma1 = &mdp_rdma1;
		mdp-rsz0 = &mdp_rsz0;
		mdp-rsz1 = &mdp_rsz1;
		mdp-rsz2 = &mdp_rsz2;
		mdp-wdma0 = &mdp_wdma0;
		mdp-wrot0 = &mdp_wrot0;
		mdp-wrot1 = &mdp_wrot1;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
	};

	cluster0_opp: opp-table-0 {
		compatible = "operating-points-v2";
		opp-shared;
		opp-507000000 {
			opp-hz = /bits/ 64 <507000000>;
			opp-microvolt = <859000>;
		};
		opp-702000000 {
			opp-hz = /bits/ 64 <702000000>;
			opp-microvolt = <908000>;
		};
		opp-1001000000 {
			opp-hz = /bits/ 64 <1001000000>;
			opp-microvolt = <983000>;
		};
		opp-1105000000 {
			opp-hz = /bits/ 64 <1105000000>;
			opp-microvolt = <1009000>;
		};
		opp-1209000000 {
			opp-hz = /bits/ 64 <1209000000>;
			opp-microvolt = <1034000>;
		};
		opp-1300000000 {
			opp-hz = /bits/ 64 <1300000000>;
			opp-microvolt = <1057000>;
		};
		opp-1508000000 {
			opp-hz = /bits/ 64 <1508000000>;
			opp-microvolt = <1109000>;
		};
		opp-1703000000 {
			opp-hz = /bits/ 64 <1703000000>;
			opp-microvolt = <1125000>;
		};
	};

	cluster1_opp: opp-table-1 {
		compatible = "operating-points-v2";
		opp-shared;
		opp-507000000 {
			opp-hz = /bits/ 64 <507000000>;
			opp-microvolt = <828000>;
		};
		opp-702000000 {
			opp-hz = /bits/ 64 <702000000>;
			opp-microvolt = <867000>;
		};
		opp-1001000000 {
			opp-hz = /bits/ 64 <1001000000>;
			opp-microvolt = <927000>;
		};
		opp-1209000000 {
			opp-hz = /bits/ 64 <1209000000>;
			opp-microvolt = <968000>;
		};
		opp-1404000000 {
			opp-hz = /bits/ 64 <1404000000>;
			opp-microvolt = <1007000>;
		};
		opp-1612000000 {
			opp-hz = /bits/ 64 <1612000000>;
			opp-microvolt = <1049000>;
		};
		opp-1807000000 {
			opp-hz = /bits/ 64 <1807000000>;
			opp-microvolt = <1089000>;
		};
		opp-2106000000 {
			opp-hz = /bits/ 64 <2106000000>;
			opp-microvolt = <1125000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu2>;
				};
				core1 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x000>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			#cooling-cells = <2>;
			dynamic-power-coefficient = <263>;
			clocks = <&infracfg CLK_INFRA_CA53SEL>,
				 <&apmixedsys CLK_APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
			capacity-dmips-mhz = <740>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x001>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			#cooling-cells = <2>;
			dynamic-power-coefficient = <263>;
			clocks = <&infracfg CLK_INFRA_CA53SEL>,
				 <&apmixedsys CLK_APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
			capacity-dmips-mhz = <740>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x100>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			#cooling-cells = <2>;
			dynamic-power-coefficient = <530>;
			clocks = <&infracfg CLK_INFRA_CA72SEL>,
				 <&apmixedsys CLK_APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster1_opp>;
			capacity-dmips-mhz = <1024>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x101>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			#cooling-cells = <2>;
			dynamic-power-coefficient = <530>;
			clocks = <&infracfg CLK_INFRA_CA72SEL>,
				 <&apmixedsys CLK_APMIXED_MAINPLL>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster1_opp>;
			capacity-dmips-mhz = <1024>;
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				entry-latency-us = <639>;
				exit-latency-us = <680>;
				min-residency-us = <1088>;
				arm,psci-suspend-param = <0x0010000>;
			};
		};
	};

	pmu_a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	pmu_a72 {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
		interrupt-affinity = <&cpu2>, <&cpu3>;
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
		method = "smc";
		cpu_suspend = <0x84000001>;
		cpu_off	 = <0x84000002>;
		cpu_on	 = <0x84000003>;
	};

	clk26m: oscillator0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	clk32k: oscillator1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32000>;
		clock-output-names = "clk32k";
	};

	cpum_ck: oscillator2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "cpum_ck";
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <1000>; /* milliseconds */
			polling-delay = <1000>; /* milliseconds */

			thermal-sensors = <&thermal>;
			sustainable-power = <1500>; /* milliwatts */

			trips {
				threshold: trip-point0 {
					temperature = <68000>;
					hysteresis = <2000>;
					type = "passive";
				};

				target: trip-point1 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit0 {
					temperature = <115000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&target>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT
							  THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT
							  THERMAL_NO_LIMIT>;
					contribution = <3072>;
				};
				map1 {
					trip = <&target>;
					cooling-device = <&cpu2 THERMAL_NO_LIMIT
							  THERMAL_NO_LIMIT>,
							 <&cpu3 THERMAL_NO_LIMIT
							  THERMAL_NO_LIMIT>;
					contribution = <1024>;
				};
			};
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		vpu_dma_reserved: vpu_dma_mem_region@b7000000 {
			compatible = "shared-dma-pool";
			reg = <0 0xb7000000 0 0x500000>;
			alignment = <0x1000>;
			no-map;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13
			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		arm,no-tick-in-suspend;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		topckgen: clock-controller@10000000 {
			compatible = "mediatek,mt8173-topckgen";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg: power-controller@10001000 {
			compatible = "mediatek,mt8173-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pericfg: power-controller@10003000 {
			compatible = "mediatek,mt8173-pericfg", "syscon";
			reg = <0 0x10003000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		syscfg_pctl_a: syscfg_pctl_a@10005000 {
			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
			reg = <0 0x10005000 0 0x1000>;
		};

		pio: pinctrl@1000b000 {
			compatible = "mediatek,mt8173-pinctrl";
			reg = <0 0x1000b000 0 0x1000>;
			mediatek,pctl-regmap = <&syscfg_pctl_a>;
			pins-are-numbered;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;

			hdmi_pin: xxx {

				/*hdmi htplg pin*/
				pins1 {
					pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
					input-enable;
					bias-pull-down;
				};
			};

			i2c0_pins_a: i2c0 {
				pins1 {
					pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
						 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
					bias-disable;
				};
			};

			i2c1_pins_a: i2c1 {
				pins1 {
					pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
						 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
					bias-disable;
				};
			};

			i2c2_pins_a: i2c2 {
				pins1 {
					pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
						 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
					bias-disable;
				};
			};

			i2c3_pins_a: i2c3 {
				pins1 {
					pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
						 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
					bias-disable;
				};
			};

			i2c4_pins_a: i2c4 {
				pins1 {
					pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
						 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
					bias-disable;
				};
			};

			i2c6_pins_a: i2c6 {
				pins1 {
					pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
						 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
					bias-disable;
				};
			};
		};

		scpsys: syscon@10006000 {
			compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
			reg = <0 0x10006000 0 0x1000>;

			/* System Power Manager */
			spm: power-controller {
				compatible = "mediatek,mt8173-power-controller";
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <1>;

				/* power domains of the SoC */
				power-domain@MT8173_POWER_DOMAIN_VDEC {
					reg = <MT8173_POWER_DOMAIN_VDEC>;
					clocks = <&topckgen CLK_TOP_MM_SEL>;
					clock-names = "mm";
					#power-domain-cells = <0>;
				};
				power-domain@MT8173_POWER_DOMAIN_VENC {
					reg = <MT8173_POWER_DOMAIN_VENC>;
					clocks = <&topckgen CLK_TOP_MM_SEL>,
						 <&topckgen CLK_TOP_VENC_SEL>;
					clock-names = "mm", "venc";
					#power-domain-cells = <0>;
				};
				power-domain@MT8173_POWER_DOMAIN_ISP {
					reg = <MT8173_POWER_DOMAIN_ISP>;
					clocks = <&topckgen CLK_TOP_MM_SEL>;
					clock-names = "mm";
					#power-domain-cells = <0>;
				};
				power-domain@MT8173_POWER_DOMAIN_MM {
					reg = <MT8173_POWER_DOMAIN_MM>;
					clocks = <&topckgen CLK_TOP_MM_SEL>;
					clock-names = "mm";
					#power-domain-cells = <0>;
					mediatek,infracfg = <&infracfg>;
				};
				power-domain@MT8173_POWER_DOMAIN_VENC_LT {
					reg = <MT8173_POWER_DOMAIN_VENC_LT>;
					clocks = <&topckgen CLK_TOP_MM_SEL>,
						 <&topckgen CLK_TOP_VENC_LT_SEL>;
					clock-names = "mm", "venclt";
					#power-domain-cells = <0>;
				};
				power-domain@MT8173_POWER_DOMAIN_AUDIO {
					reg = <MT8173_POWER_DOMAIN_AUDIO>;
					#power-domain-cells = <0>;
				};
				power-domain@MT8173_POWER_DOMAIN_USB {
					reg = <MT8173_POWER_DOMAIN_USB>;
					#power-domain-cells = <0>;
				};
				mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
					reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
					clocks = <&clk26m>;
					clock-names = "mfg";
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <1>;

					power-domain@MT8173_POWER_DOMAIN_MFG_2D {
						reg = <MT8173_POWER_DOMAIN_MFG_2D>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <1>;

						power-domain@MT8173_POWER_DOMAIN_MFG {
							reg = <MT8173_POWER_DOMAIN_MFG>;
							#power-domain-cells = <0>;
							mediatek,infracfg = <&infracfg>;
						};
					};
				};
			};
		};

		watchdog: watchdog@10007000 {
			compatible = "mediatek,mt8173-wdt",
				     "mediatek,mt6589-wdt";
			reg = <0 0x10007000 0 0x100>;
		};

		timer: timer@10008000 {
			compatible = "mediatek,mt8173-timer",
				     "mediatek,mt6577-timer";
			reg = <0 0x10008000 0 0x1000>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_CLK_13M>,
				 <&topckgen CLK_TOP_RTC_SEL>;
		};

		pwrap: pwrap@1000d000 {
			compatible = "mediatek,mt8173-pwrap";
			reg = <0 0x1000d000 0 0x1000>;
			reg-names = "pwrap";
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
			reset-names = "pwrap";
			clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
			clock-names = "spi", "wrap";
		};

		cec: cec@10013000 {
			compatible = "mediatek,mt8173-cec";
			reg = <0 0x10013000 0 0xbc>;
			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_CEC>;
			status = "disabled";
		};

		vpu: vpu@10020000 {
			compatible = "mediatek,mt8173-vpu";
			reg = <0 0x10020000 0 0x30000>,
			      <0 0x10050000 0 0x100>;
			reg-names = "tcm", "cfg_reg";
			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&topckgen CLK_TOP_SCP_SEL>;
			clock-names = "main";
			memory-region = <&vpu_dma_reserved>;
		};

		sysirq: intpol-controller@10200620 {
			compatible = "mediatek,mt8173-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10200620 0 0x20>;
		};

		iommu: iommu@10205000 {
			compatible = "mediatek,mt8173-m4u";
			reg = <0 0x10205000 0 0x1000>;
			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_M4U>;
			clock-names = "bclk";
			mediatek,infracfg = <&infracfg>;
			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
					 <&larb3>, <&larb4>, <&larb5>;
			#iommu-cells = <1>;
		};

		efuse: efuse@10206000 {
			compatible = "mediatek,mt8173-efuse";
			reg = <0 0x10206000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			thermal_calibration: calib@528 {
				reg = <0x528 0xc>;
			};
		};

		apmixedsys: clock-controller@10209000 {
			compatible = "mediatek,mt8173-apmixedsys";
			reg = <0 0x10209000 0 0x1000>;
			#clock-cells = <1>;
		};

		hdmi_phy: hdmi-phy@10209100 {
			compatible = "mediatek,mt8173-hdmi-phy";
			reg = <0 0x10209100 0 0x24>;
			clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
			clock-names = "pll_ref";
			clock-output-names = "hdmitx_dig_cts";
			mediatek,ibias = <0xa>;
			mediatek,ibias_up = <0x1c>;
			#clock-cells = <0>;
			#phy-cells = <0>;
			status = "disabled";
		};

		gce: mailbox@10212000 {
			compatible = "mediatek,mt8173-gce";
			reg = <0 0x10212000 0 0x1000>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_GCE>;
			clock-names = "gce";
			#mbox-cells = <2>;
		};

		mipi_tx0: dsi-phy@10215000 {
			compatible = "mediatek,mt8173-mipi-tx";
			reg = <0 0x10215000 0 0x1000>;
			clocks = <&clk26m>;
			clock-output-names = "mipi_tx0_pll";
			#clock-cells = <0>;
			#phy-cells = <0>;
			status = "disabled";
		};

		mipi_tx1: dsi-phy@10216000 {
			compatible = "mediatek,mt8173-mipi-tx";
			reg = <0 0x10216000 0 0x1000>;
			clocks = <&clk26m>;
			clock-output-names = "mipi_tx1_pll";
			#clock-cells = <0>;
			#phy-cells = <0>;
			status = "disabled";
		};

		gic: interrupt-controller@10221000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			reg = <0 0x10221000 0 0x1000>,
			      <0 0x10222000 0 0x2000>,
			      <0 0x10224000 0 0x2000>,
			      <0 0x10226000 0 0x2000>;
			interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		auxadc: auxadc@11001000 {
			compatible = "mediatek,mt8173-auxadc";
			reg = <0 0x11001000 0 0x1000>;
			clocks = <&pericfg CLK_PERI_AUXADC>;
			clock-names = "main";
			#io-channel-cells = <1>;
		};

		uart0: serial@11002000 {
			compatible = "mediatek,mt8173-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11002000 0 0x400>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart1: serial@11003000 {
			compatible = "mediatek,mt8173-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11003000 0 0x400>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart2: serial@11004000 {
			compatible = "mediatek,mt8173-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11004000 0 0x400>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart3: serial@11005000 {
			compatible = "mediatek,mt8173-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11005000 0 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		i2c0: i2c@11007000 {
			compatible = "mediatek,mt8173-i2c";
			reg = <0 0x11007000 0 0x70>,
			      <0 0x11000100 0 0x80>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
			clock-div = <16>;
			clocks = <&pericfg CLK_PERI_I2C0>,
				 <&pericfg CLK_PERI_AP_DMA>;
			clock-names = "main", "dma";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_pins_a>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@11008000 {
			compatible = "mediatek,mt8173-i2c";
			reg = <0 0x11008000 0 0x70>,
			      <0 0x11000180 0 0x80>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
			clock-div = <16>;
			clocks = <&pericfg CLK_PERI_I2C1>,
				 <&pericfg CLK_PERI_AP_DMA>;
			clock-names = "main", "dma";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_pins_a>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@11009000 {
			compatible = "mediatek,mt8173-i2c";
			reg = <0 0x11009000 0 0x70>,
			      <0 0x11000200 0 0x80>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
			clock-div = <16>;
			clocks = <&pericfg CLK_PERI_I2C2>,
				 <&pericfg CLK_PERI_AP_DMA>;
			clock-names = "main", "dma";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_pins_a>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi: spi@1100a000 {
			compatible = "mediatek,mt8173-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x1100a000 0 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&pericfg CLK_PERI_SPI0>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		thermal: thermal@1100b000 {
			#thermal-sensor-cells = <0>;
			compatible = "mediatek,mt8173-thermal";
			reg = <0 0x1100b000 0 0x1000>;
			interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
			clock-names = "therm", "auxadc";
			resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
			mediatek,auxadc = <&auxadc>;
			mediatek,apmixedsys = <&apmixedsys>;
			nvmem-cells = <&thermal_calibration>;
			nvmem-cell-names = "calibration-data";
		};

		nor_flash: spi@1100d000 {
			compatible = "mediatek,mt8173-nor";
			reg = <0 0x1100d000 0 0xe0>;
			assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
			assigned-clock-parents = <&clk26m>;
			clocks = <&pericfg CLK_PERI_SPI>,
				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
				 <&pericfg CLK_PERI_NFI>;
			clock-names = "spi", "sf", "axi";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c3: i2c@11010000 {
			compatible = "mediatek,mt8173-i2c";
			reg = <0 0x11010000 0 0x70>,
			      <0 0x11000280 0 0x80>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
			clock-div = <16>;
			clocks = <&pericfg CLK_PERI_I2C3>,
				 <&pericfg CLK_PERI_AP_DMA>;
			clock-names = "main", "dma";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_pins_a>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c4: i2c@11011000 {
			compatible = "mediatek,mt8173-i2c";
			reg = <0 0x11011000 0 0x70>,
			      <0 0x11000300 0 0x80>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
			clock-div = <16>;
			clocks = <&pericfg CLK_PERI_I2C4>,
				 <&pericfg CLK_PERI_AP_DMA>;
			clock-names = "main", "dma";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4_pins_a>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		hdmiddc0: i2c@11012000 {
			compatible = "mediatek,mt8173-hdmi-ddc";
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
			reg = <0 0x11012000 0 0x1C>;
			clocks = <&pericfg CLK_PERI_I2C5>;
			clock-names = "ddc-i2c";
		};

		i2c6: i2c@11013000 {
			compatible = "mediatek,mt8173-i2c";
			reg = <0 0x11013000 0 0x70>,
			      <0 0x11000080 0 0x80>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
			clock-div = <16>;
			clocks = <&pericfg CLK_PERI_I2C6>,
				 <&pericfg CLK_PERI_AP_DMA>;
			clock-names = "main", "dma";
			pinctrl-names = "default";
			pinctrl-0 = <&i2c6_pins_a>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		afe: audio-controller@11220000  {
			compatible = "mediatek,mt8173-afe-pcm";
			reg = <0 0x11220000 0 0x1000>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
			power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
			clocks = <&infracfg CLK_INFRA_AUDIO>,
				 <&topckgen CLK_TOP_AUDIO_SEL>,
				 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
				 <&topckgen CLK_TOP_APLL1_DIV0>,
				 <&topckgen CLK_TOP_APLL2_DIV0>,
				 <&topckgen CLK_TOP_I2S0_M_SEL>,
				 <&topckgen CLK_TOP_I2S1_M_SEL>,
				 <&topckgen CLK_TOP_I2S2_M_SEL>,
				 <&topckgen CLK_TOP_I2S3_M_SEL>,
				 <&topckgen CLK_TOP_I2S3_B_SEL>;
			clock-names = "infra_sys_audio_clk",
				      "top_pdn_audio",
				      "top_pdn_aud_intbus",
				      "bck0",
				      "bck1",
				      "i2s0_m",
				      "i2s1_m",
				      "i2s2_m",
				      "i2s3_m",
				      "i2s3_b";
			assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
					  <&topckgen CLK_TOP_AUD_2_SEL>;
			assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
						 <&topckgen CLK_TOP_APLL2>;
		};

		mmc0: mmc@11230000 {
			compatible = "mediatek,mt8173-mmc";
			reg = <0 0x11230000 0 0x1000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_MSDC30_0>,
				 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
			clock-names = "source", "hclk";
			status = "disabled";
		};

		mmc1: mmc@11240000 {
			compatible = "mediatek,mt8173-mmc";
			reg = <0 0x11240000 0 0x1000>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_MSDC30_1>,
				 <&topckgen CLK_TOP_AXI_SEL>;
			clock-names = "source", "hclk";
			status = "disabled";
		};

		mmc2: mmc@11250000 {
			compatible = "mediatek,mt8173-mmc";
			reg = <0 0x11250000 0 0x1000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_MSDC30_2>,
				 <&topckgen CLK_TOP_AXI_SEL>;
			clock-names = "source", "hclk";
			status = "disabled";
		};

		mmc3: mmc@11260000 {
			compatible = "mediatek,mt8173-mmc";
			reg = <0 0x11260000 0 0x1000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&pericfg CLK_PERI_MSDC30_3>,
				 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
			clock-names = "source", "hclk";
			status = "disabled";
		};

		ssusb: usb@11271000 {
			compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
			reg = <0 0x11271000 0 0x3000>,
			      <0 0x11280700 0 0x0100>;
			reg-names = "mac", "ippc";
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
			phys = <&u2port0 PHY_TYPE_USB2>,
			       <&u3port0 PHY_TYPE_USB3>,
			       <&u2port1 PHY_TYPE_USB2>;
			power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
			clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
			clock-names = "sys_ck", "ref_ck";
			mediatek,syscon-wakeup = <&pericfg 0x400 1>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			status = "disabled";

			usb_host: usb@11270000 {
				compatible = "mediatek,mt8173-xhci",
					     "mediatek,mtk-xhci";
				reg = <0 0x11270000 0 0x1000>;
				reg-names = "mac";
				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
				power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
				clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
				clock-names = "sys_ck", "ref_ck";
				status = "disabled";
			};
		};

		u3phy: t-phy@11290000 {
			compatible = "mediatek,mt8173-u3phy";
			reg = <0 0x11290000 0 0x800>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			status = "okay";

			u2port0: usb-phy@11290800 {
				reg = <0 0x11290800 0 0x100>;
				clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
				clock-names = "ref";
				#phy-cells = <1>;
				status = "okay";
			};

			u3port0: usb-phy@11290900 {
				reg = <0 0x11290900 0 0x700>;
				clocks = <&clk26m>;
				clock-names = "ref";
				#phy-cells = <1>;
				status = "okay";
			};

			u2port1: usb-phy@11291000 {
				reg = <0 0x11291000 0 0x100>;
				clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
				clock-names = "ref";
				#phy-cells = <1>;
				status = "okay";
			};
		};

		mmsys: syscon@14000000 {
			compatible = "mediatek,mt8173-mmsys", "syscon";
			reg = <0 0x14000000 0 0x1000>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
			assigned-clock-rates = <400000000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
		};

		mdp_rdma0: rdma@14001000 {
			compatible = "mediatek,mt8173-mdp-rdma",
				     "mediatek,mt8173-mdp";
			reg = <0 0x14001000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
				 <&mmsys CLK_MM_MUTEX_32K>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
			mediatek,vpu = <&vpu>;
		};

		mdp_rdma1: rdma@14002000 {
			compatible = "mediatek,mt8173-mdp-rdma";
			reg = <0 0x14002000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_RDMA1>,
				 <&mmsys CLK_MM_MUTEX_32K>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			iommus = <&iommu M4U_PORT_MDP_RDMA1>;
		};

		mdp_rsz0: rsz@14003000 {
			compatible = "mediatek,mt8173-mdp-rsz";
			reg = <0 0x14003000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
		};

		mdp_rsz1: rsz@14004000 {
			compatible = "mediatek,mt8173-mdp-rsz";
			reg = <0 0x14004000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
		};

		mdp_rsz2: rsz@14005000 {
			compatible = "mediatek,mt8173-mdp-rsz";
			reg = <0 0x14005000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_RSZ2>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
		};

		mdp_wdma0: wdma@14006000 {
			compatible = "mediatek,mt8173-mdp-wdma";
			reg = <0 0x14006000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_WDMA>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			iommus = <&iommu M4U_PORT_MDP_WDMA>;
		};

		mdp_wrot0: wrot@14007000 {
			compatible = "mediatek,mt8173-mdp-wrot";
			reg = <0 0x14007000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_WROT0>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			iommus = <&iommu M4U_PORT_MDP_WROT0>;
		};

		mdp_wrot1: wrot@14008000 {
			compatible = "mediatek,mt8173-mdp-wrot";
			reg = <0 0x14008000 0 0x1000>;
			clocks = <&mmsys CLK_MM_MDP_WROT1>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			iommus = <&iommu M4U_PORT_MDP_WROT1>;
		};

		ovl0: ovl@1400c000 {
			compatible = "mediatek,mt8173-disp-ovl";
			reg = <0 0x1400c000 0 0x1000>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_OVL0>;
			iommus = <&iommu M4U_PORT_DISP_OVL0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
		};

		ovl1: ovl@1400d000 {
			compatible = "mediatek,mt8173-disp-ovl";
			reg = <0 0x1400d000 0 0x1000>;
			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_OVL1>;
			iommus = <&iommu M4U_PORT_DISP_OVL1>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
		};

		rdma0: rdma@1400e000 {
			compatible = "mediatek,mt8173-disp-rdma";
			reg = <0 0x1400e000 0 0x1000>;
			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
			iommus = <&iommu M4U_PORT_DISP_RDMA0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
		};

		rdma1: rdma@1400f000 {
			compatible = "mediatek,mt8173-disp-rdma";
			reg = <0 0x1400f000 0 0x1000>;
			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
			iommus = <&iommu M4U_PORT_DISP_RDMA1>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
		};

		rdma2: rdma@14010000 {
			compatible = "mediatek,mt8173-disp-rdma";
			reg = <0 0x14010000 0 0x1000>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_RDMA2>;
			iommus = <&iommu M4U_PORT_DISP_RDMA2>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
		};

		wdma0: wdma@14011000 {
			compatible = "mediatek,mt8173-disp-wdma";
			reg = <0 0x14011000 0 0x1000>;
			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_WDMA0>;
			iommus = <&iommu M4U_PORT_DISP_WDMA0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
		};

		wdma1: wdma@14012000 {
			compatible = "mediatek,mt8173-disp-wdma";
			reg = <0 0x14012000 0 0x1000>;
			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_WDMA1>;
			iommus = <&iommu M4U_PORT_DISP_WDMA1>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
		};

		color0: color@14013000 {
			compatible = "mediatek,mt8173-disp-color";
			reg = <0 0x14013000 0 0x1000>;
			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
		};

		color1: color@14014000 {
			compatible = "mediatek,mt8173-disp-color";
			reg = <0 0x14014000 0 0x1000>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_COLOR1>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
		};

		aal@14015000 {
			compatible = "mediatek,mt8173-disp-aal";
			reg = <0 0x14015000 0 0x1000>;
			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_AAL>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
		};

		gamma@14016000 {
			compatible = "mediatek,mt8173-disp-gamma";
			reg = <0 0x14016000 0 0x1000>;
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_GAMMA>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
		};

		merge@14017000 {
			compatible = "mediatek,mt8173-disp-merge";
			reg = <0 0x14017000 0 0x1000>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_MERGE>;
		};

		split0: split@14018000 {
			compatible = "mediatek,mt8173-disp-split";
			reg = <0 0x14018000 0 0x1000>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
		};

		split1: split@14019000 {
			compatible = "mediatek,mt8173-disp-split";
			reg = <0 0x14019000 0 0x1000>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
		};

		ufoe@1401a000 {
			compatible = "mediatek,mt8173-disp-ufoe";
			reg = <0 0x1401a000 0 0x1000>;
			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DISP_UFOE>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
		};

		dsi0: dsi@1401b000 {
			compatible = "mediatek,mt8173-dsi";
			reg = <0 0x1401b000 0 0x1000>;
			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
				 <&mmsys CLK_MM_DSI0_DIGITAL>,
				 <&mipi_tx0>;
			clock-names = "engine", "digital", "hs";
			resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
			phys = <&mipi_tx0>;
			phy-names = "dphy";
			status = "disabled";
		};

		dsi1: dsi@1401c000 {
			compatible = "mediatek,mt8173-dsi";
			reg = <0 0x1401c000 0 0x1000>;
			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
				 <&mmsys CLK_MM_DSI1_DIGITAL>,
				 <&mipi_tx1>;
			clock-names = "engine", "digital", "hs";
			phys = <&mipi_tx1>;
			phy-names = "dphy";
			status = "disabled";
		};

		dpi0: dpi@1401d000 {
			compatible = "mediatek,mt8173-dpi";
			reg = <0 0x1401d000 0 0x1000>;
			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_DPI_PIXEL>,
				 <&mmsys CLK_MM_DPI_ENGINE>,
				 <&apmixedsys CLK_APMIXED_TVDPLL>;
			clock-names = "pixel", "engine", "pll";
			status = "disabled";

			port {
				dpi0_out: endpoint {
					remote-endpoint = <&hdmi0_in>;
				};
			};
		};

		pwm0: pwm@1401e000 {
			compatible = "mediatek,mt8173-disp-pwm",
				     "mediatek,mt6595-disp-pwm";
			reg = <0 0x1401e000 0 0x1000>;
			#pwm-cells = <2>;
			clocks = <&mmsys CLK_MM_DISP_PWM026M>,
				 <&mmsys CLK_MM_DISP_PWM0MM>;
			clock-names = "main", "mm";
			status = "disabled";
		};

		pwm1: pwm@1401f000 {
			compatible = "mediatek,mt8173-disp-pwm",
				     "mediatek,mt6595-disp-pwm";
			reg = <0 0x1401f000 0 0x1000>;
			#pwm-cells = <2>;
			clocks = <&mmsys CLK_MM_DISP_PWM126M>,
				 <&mmsys CLK_MM_DISP_PWM1MM>;
			clock-names = "main", "mm";
			status = "disabled";
		};

		mutex: mutex@14020000 {
			compatible = "mediatek,mt8173-disp-mutex";
			reg = <0 0x14020000 0 0x1000>;
			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_MUTEX_32K>;
			mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
			mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
                                              <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
		};

		larb0: larb@14021000 {
			compatible = "mediatek,mt8173-smi-larb";
			reg = <0 0x14021000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_SMI_LARB0>,
				 <&mmsys CLK_MM_SMI_LARB0>;
			clock-names = "apb", "smi";
		};

		smi_common: smi@14022000 {
			compatible = "mediatek,mt8173-smi-common";
			reg = <0 0x14022000 0 0x1000>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_SMI_COMMON>,
				 <&mmsys CLK_MM_SMI_COMMON>;
			clock-names = "apb", "smi";
		};

		od@14023000 {
			compatible = "mediatek,mt8173-disp-od";
			reg = <0 0x14023000 0 0x1000>;
			clocks = <&mmsys CLK_MM_DISP_OD>;
			mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
		};

		hdmi0: hdmi@14025000 {
			compatible = "mediatek,mt8173-hdmi";
			reg = <0 0x14025000 0 0x400>;
			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
				 <&mmsys CLK_MM_HDMI_PLLCK>,
				 <&mmsys CLK_MM_HDMI_AUDIO>,
				 <&mmsys CLK_MM_HDMI_SPDIF>;
			clock-names = "pixel", "pll", "bclk", "spdif";
			pinctrl-names = "default";
			pinctrl-0 = <&hdmi_pin>;
			phys = <&hdmi_phy>;
			phy-names = "hdmi";
			mediatek,syscon-hdmi = <&mmsys 0x900>;
			assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
			assigned-clock-parents = <&hdmi_phy>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					hdmi0_in: endpoint {
						remote-endpoint = <&dpi0_out>;
					};
				};
			};
		};

		larb4: larb@14027000 {
			compatible = "mediatek,mt8173-smi-larb";
			reg = <0 0x14027000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
			clocks = <&mmsys CLK_MM_SMI_LARB4>,
				 <&mmsys CLK_MM_SMI_LARB4>;
			clock-names = "apb", "smi";
		};

		imgsys: clock-controller@15000000 {
			compatible = "mediatek,mt8173-imgsys", "syscon";
			reg = <0 0x15000000 0 0x1000>;
			#clock-cells = <1>;
		};

		larb2: larb@15001000 {
			compatible = "mediatek,mt8173-smi-larb";
			reg = <0 0x15001000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			power-domains = <&spm MT8173_POWER_DOMAIN_ISP>;
			clocks = <&imgsys CLK_IMG_LARB2_SMI>,
				 <&imgsys CLK_IMG_LARB2_SMI>;
			clock-names = "apb", "smi";
		};

		vdecsys: clock-controller@16000000 {
			compatible = "mediatek,mt8173-vdecsys", "syscon";
			reg = <0 0x16000000 0 0x1000>;
			#clock-cells = <1>;
		};

		vcodec_dec: vcodec@16000000 {
			compatible = "mediatek,mt8173-vcodec-dec";
			reg = <0 0x16000000 0 0x100>,	/* VDEC_SYS */
			      <0 0x16020000 0 0x1000>,	/* VDEC_MISC */
			      <0 0x16021000 0 0x800>,	/* VDEC_LD */
			      <0 0x16021800 0 0x800>,	/* VDEC_TOP */
			      <0 0x16022000 0 0x1000>,	/* VDEC_CM */
			      <0 0x16023000 0 0x1000>,	/* VDEC_AD */
			      <0 0x16024000 0 0x1000>,	/* VDEC_AV */
			      <0 0x16025000 0 0x1000>,	/* VDEC_PP */
			      <0 0x16026800 0 0x800>,	/* VDEC_HWD */
			      <0 0x16027000 0 0x800>,	/* VDEC_HWQ */
			      <0 0x16027800 0 0x800>,	/* VDEC_HWB */
			      <0 0x16028400 0 0x400>;	/* VDEC_HWG */
			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
			iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
			mediatek,vpu = <&vpu>;
			power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
			clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
				 <&topckgen CLK_TOP_UNIVPLL_D2>,
				 <&topckgen CLK_TOP_CCI400_SEL>,
				 <&topckgen CLK_TOP_VDEC_SEL>,
				 <&topckgen CLK_TOP_VCODECPLL>,
				 <&apmixedsys CLK_APMIXED_VENCPLL>,
				 <&topckgen CLK_TOP_VENC_LT_SEL>,
				 <&topckgen CLK_TOP_VCODECPLL_370P5>;
			clock-names = "vcodecpll",
				      "univpll_d2",
				      "clk_cci400_sel",
				      "vdec_sel",
				      "vdecpll",
				      "vencpll",
				      "venc_lt_sel",
				      "vdec_bus_clk_src";
			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
					  <&topckgen CLK_TOP_CCI400_SEL>,
					  <&topckgen CLK_TOP_VDEC_SEL>,
					  <&apmixedsys CLK_APMIXED_VCODECPLL>,
					  <&apmixedsys CLK_APMIXED_VENCPLL>;
			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
						 <&topckgen CLK_TOP_UNIVPLL_D2>,
						 <&topckgen CLK_TOP_VCODECPLL>;
			assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
		};

		larb1: larb@16010000 {
			compatible = "mediatek,mt8173-smi-larb";
			reg = <0 0x16010000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
			clocks = <&vdecsys CLK_VDEC_CKEN>,
				 <&vdecsys CLK_VDEC_LARB_CKEN>;
			clock-names = "apb", "smi";
		};

		vencsys: clock-controller@18000000 {
			compatible = "mediatek,mt8173-vencsys", "syscon";
			reg = <0 0x18000000 0 0x1000>;
			#clock-cells = <1>;
		};

		larb3: larb@18001000 {
			compatible = "mediatek,mt8173-smi-larb";
			reg = <0 0x18001000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
			clocks = <&vencsys CLK_VENC_CKE1>,
				 <&vencsys CLK_VENC_CKE0>;
			clock-names = "apb", "smi";
		};

		vcodec_enc_avc: vcodec@18002000 {
			compatible = "mediatek,mt8173-vcodec-enc";
			reg = <0 0x18002000 0 0x1000>;	/* VENC_SYS */
			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
			iommus = <&iommu M4U_PORT_VENC_RCPU>,
				 <&iommu M4U_PORT_VENC_REC>,
				 <&iommu M4U_PORT_VENC_BSDMA>,
				 <&iommu M4U_PORT_VENC_SV_COMV>,
				 <&iommu M4U_PORT_VENC_RD_COMV>,
				 <&iommu M4U_PORT_VENC_CUR_LUMA>,
				 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
				 <&iommu M4U_PORT_VENC_REF_LUMA>,
				 <&iommu M4U_PORT_VENC_REF_CHROMA>,
				 <&iommu M4U_PORT_VENC_NBM_RDMA>,
				 <&iommu M4U_PORT_VENC_NBM_WDMA>;
			mediatek,vpu = <&vpu>;
			clocks = <&topckgen CLK_TOP_VENC_SEL>;
			clock-names = "venc_sel";
			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
			power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
		};

		jpegdec: jpegdec@18004000 {
			compatible = "mediatek,mt8173-jpgdec";
			reg = <0 0x18004000 0 0x1000>;
			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&vencsys CLK_VENC_CKE0>,
				 <&vencsys CLK_VENC_CKE3>;
			clock-names = "jpgdec-smi",
				      "jpgdec";
			power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
			iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
				 <&iommu M4U_PORT_JPGDEC_BSDMA>;
		};

		vencltsys: clock-controller@19000000 {
			compatible = "mediatek,mt8173-vencltsys", "syscon";
			reg = <0 0x19000000 0 0x1000>;
			#clock-cells = <1>;
		};

		larb5: larb@19001000 {
			compatible = "mediatek,mt8173-smi-larb";
			reg = <0 0x19001000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
			clocks = <&vencltsys CLK_VENCLT_CKE1>,
				 <&vencltsys CLK_VENCLT_CKE0>;
			clock-names = "apb", "smi";
		};

		vcodec_enc_vp8: vcodec@19002000 {
			compatible = "mediatek,mt8173-vcodec-enc-vp8";
			reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
			iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
				 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
				 <&iommu M4U_PORT_VENC_BSDMA_SET2>,
				 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
				 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
				 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
				 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
				 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
				 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
			mediatek,vpu = <&vpu>;
			clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
			clock-names = "venc_lt_sel";
			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
			assigned-clock-parents =
				 <&topckgen CLK_TOP_VCODECPLL_370P5>;
			power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Ben Ho <ben.ho@mediatek.com>
 *	   Erin Lo <erin.lo@mediatek.com>
 */

/dts-v1/;
#include "mt8183.dtsi"
#include "mt6358.dtsi"

/ {
	model = "MediaTek MT8183 evaluation board";
	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";

	aliases {
		serial0 = &uart0;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x80000000>;
	};

	chosen {
		stdout-path = "serial0:921600n8";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		scp_mem_reserved: scp_mem_region {
			compatible = "shared-dma-pool";
			reg = <0 0x50000000 0 0x2900000>;
			no-map;
		};
	};

	ntc@0 {
		compatible = "murata,ncp03wf104";
		pullup-uv = <1800000>;
		pullup-ohm = <390000>;
		pulldown-ohm = <0>;
		io-channels = <&auxadc 0>;
	};
};

&auxadc {
	status = "okay";
};

&gpu {
	mali-supply = <&mt6358_vgpu_reg>;
	sram-supply = <&mt6358_vsram_gpu_reg>;
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c_pins_0>;
	status = "okay";
	clock-frequency = <100000>;
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c_pins_1>;
	status = "okay";
	clock-frequency = <100000>;
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c_pins_2>;
	status = "okay";
	clock-frequency = <100000>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c_pins_3>;
	status = "okay";
	clock-frequency = <100000>;
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c_pins_4>;
	status = "okay";
	clock-frequency = <1000000>;
};

&i2c5 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c_pins_5>;
	status = "okay";
	clock-frequency = <1000000>;
};

&mmc0 {
	status = "okay";
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc0_pins_default>;
	pinctrl-1 = <&mmc0_pins_uhs>;
	bus-width = <8>;
	max-frequency = <200000000>;
	cap-mmc-highspeed;
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	cap-mmc-hw-reset;
	no-sdio;
	no-sd;
	hs400-ds-delay = <0x12814>;
	vmmc-supply = <&mt6358_vemc_reg>;
	vqmmc-supply = <&mt6358_vio18_reg>;
	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
	non-removable;
};

&mmc1 {
	status = "okay";
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_uhs>;
	bus-width = <4>;
	max-frequency = <200000000>;
	cap-sd-highspeed;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	cap-sdio-irq;
	no-mmc;
	no-sd;
	vmmc-supply = <&mt6358_vmch_reg>;
	vqmmc-supply = <&mt6358_vmc_reg>;
	keep-power-in-suspend;
	wakeup-source;
	non-removable;
};

&pio {
	i2c_pins_0: i2c0{
		pins_i2c{
			pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
				 <PINMUX_GPIO83__FUNC_SCL0>;
			mediatek,pull-up-adv = <3>;
			mediatek,drive-strength-adv = <00>;
		};
	};

	i2c_pins_1: i2c1{
		pins_i2c{
			pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
				 <PINMUX_GPIO84__FUNC_SCL1>;
			mediatek,pull-up-adv = <3>;
			mediatek,drive-strength-adv = <00>;
		};
	};

	i2c_pins_2: i2c2{
		pins_i2c{
			pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
				 <PINMUX_GPIO104__FUNC_SDA2>;
			mediatek,pull-up-adv = <3>;
			mediatek,drive-strength-adv = <00>;
		};
	};

	i2c_pins_3: i2c3{
		pins_i2c{
			pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
				 <PINMUX_GPIO51__FUNC_SDA3>;
			mediatek,pull-up-adv = <3>;
			mediatek,drive-strength-adv = <00>;
		};
	};

	i2c_pins_4: i2c4{
		pins_i2c{
			pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
				 <PINMUX_GPIO106__FUNC_SDA4>;
			mediatek,pull-up-adv = <3>;
			mediatek,drive-strength-adv = <00>;
		};
	};

	i2c_pins_5: i2c5{
		pins_i2c{
			pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
				 <PINMUX_GPIO49__FUNC_SDA5>;
			mediatek,pull-up-adv = <3>;
			mediatek,drive-strength-adv = <00>;
		};
	};

	spi_pins_0: spi0{
		pins_spi{
			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
				 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
				 <PINMUX_GPIO87__FUNC_SPI0_MO>,
				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
			bias-disable;
		};
	};

	mmc0_pins_default: mmc0default {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
			input-enable;
			bias-pull-up;
		};

		pins_clk {
			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
			bias-pull-down;
		};

		pins_rst {
			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
			bias-pull-up;
		};
	};

	mmc0_pins_uhs: mmc0 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
			input-enable;
			drive-strength = <MTK_DRIVE_10mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
		};

		pins_clk {
			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
			drive-strength = <MTK_DRIVE_10mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
		};

		pins_ds {
			pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
			drive-strength = <MTK_DRIVE_10mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
		};

		pins_rst {
			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
			drive-strength = <MTK_DRIVE_10mA>;
			bias-pull-up;
		};
	};

	mmc1_pins_default: mmc1default {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
			input-enable;
			bias-pull-up;
		};

		pins_clk {
			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
			input-enable;
			bias-pull-down;
		};

		pins_pmu {
			pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
				   <PINMUX_GPIO166__FUNC_GPIO166>;
			output-high;
		};
	};

	mmc1_pins_uhs: mmc1 {
		pins_cmd_dat {
			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
			drive-strength = <MTK_DRIVE_6mA>;
			input-enable;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
		};

		pins_clk {
			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
			drive-strength = <MTK_DRIVE_6mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
			input-enable;
		};
	};

	spi_pins_1: spi1{
		pins_spi{
			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
			bias-disable;
		};
	};

	spi_pins_2: spi2{
		pins_spi{
			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
				 <PINMUX_GPIO1__FUNC_SPI2_MO>,
				 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
				 <PINMUX_GPIO94__FUNC_SPI2_MI>;
			bias-disable;
		};
	};

	spi_pins_3: spi3{
		pins_spi{
			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
				 <PINMUX_GPIO23__FUNC_SPI3_MO>,
				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
			bias-disable;
		};
	};

	spi_pins_4: spi4{
		pins_spi{
			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
				 <PINMUX_GPIO19__FUNC_SPI4_MO>,
				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
			bias-disable;
		};
	};

	spi_pins_5: spi5{
		pins_spi{
			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
				 <PINMUX_GPIO15__FUNC_SPI5_MO>,
				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
			bias-disable;
		};
	};

	pwm_pins_1: pwm1 {
		pins_pwm {
			pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
		};
	};
};

&mfg {
	domain-supply = <&mt6358_vgpu_reg>;
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_pins_0>;
	mediatek,pad-select = <0>;
	status = "okay";
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_pins_1>;
	mediatek,pad-select = <0>;
	status = "okay";
};

&spi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_pins_2>;
	mediatek,pad-select = <0>;
	status = "okay";
};

&spi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_pins_3>;
	mediatek,pad-select = <0>;
	status = "okay";
};

&spi4 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_pins_4>;
	mediatek,pad-select = <0>;
	status = "okay";
};

&spi5 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_pins_5>;
	mediatek,pad-select = <0>;
	status = "okay";

};

&cci {
	proc-supply = <&mt6358_vproc12_reg>;
};

&cpu0 {
	proc-supply = <&mt6358_vproc12_reg>;
};

&cpu1 {
	proc-supply = <&mt6358_vproc12_reg>;
};

&cpu2 {
	proc-supply = <&mt6358_vproc12_reg>;
};

&cpu3 {
	proc-supply = <&mt6358_vproc12_reg>;
};

&cpu4 {
	proc-supply = <&mt6358_vproc11_reg>;
};

&cpu5 {
	proc-supply = <&mt6358_vproc11_reg>;
};

&cpu6 {
	proc-supply = <&mt6358_vproc11_reg>;
};

&cpu7 {
	proc-supply = <&mt6358_vproc11_reg>;
};

&uart0 {
	status = "okay";
};

&pwm1 {
	status = "okay";
	pinctrl-0 = <&pwm_pins_1>;
	pinctrl-names = "default";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Google Kukui (and derivatives) da7219-max98357a sound card.
 *
 * Copyright 2019 Google LLC.
 */

#include "mt8183-kukui-audio-da7219.dtsi"
#include "mt8183-kukui-audio-max98357a.dtsi"

&sound {
	compatible = "mediatek,mt8183_da7219_max98357";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Google Kukui (and derivatives) da7219-rt1015p sound card.
 *
 * Copyright 2020 Google LLC.
 */

#include "mt8183-kukui-audio-da7219.dtsi"
#include "mt8183-kukui-audio-rt1015p.dtsi"

&sound {
	compatible = "mediatek,mt8183_da7219_rt1015p";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Google Kukui (and derivatives) audio fragment for da7219.
 *
 * Copyright 2020 Google LLC.
 */

&i2c5 {
	da7219: da7219@1a {
		pinctrl-names = "default";
		pinctrl-0 = <&da7219_pins>;
		compatible = "dlg,da7219";
		reg = <0x1a>;
		interrupt-parent = <&pio>;
		interrupts = <165 IRQ_TYPE_LEVEL_LOW 165 0>;

		dlg,micbias-lvl = <2600>;
		dlg,mic-amp-in-sel = "diff";
		VDD-supply = <&pp1800_alw>;
		VDDMIC-supply = <&pp3300_alw>;
		VDDIO-supply = <&pp1800_alw>;

		status = "okay";

		da7219_aad {
			dlg,adc-1bit-rpt = <1>;
			dlg,btn-avg = <4>;
			dlg,btn-cfg = <50>;
			dlg,mic-det-thr = <500>;
			dlg,jack-ins-deb = <20>;
			dlg,jack-det-rate = "32ms_64ms";
			dlg,jack-rem-deb = <1>;

			dlg,a-d-btn-thr = <0xa>;
			dlg,d-b-btn-thr = <0x16>;
			dlg,b-c-btn-thr = <0x21>;
			dlg,c-mic-btn-thr = <0x3E>;
		};
	};
};

&pio {
	da7219_pins: da7219_pins {
		pins1 {
			pinmux = <PINMUX_GPIO165__FUNC_GPIO165>;
			input-enable;
			bias-pull-up;
		};
	};
};

&sound {
	mediatek,headset-codec = <&da7219>;
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Google Kukui (and derivatives) audio fragment for max98357a.
 *
 * Copyright 2020 Google LLC.
 */

/ {
	max98357a: max98357a {
		compatible = "maxim,max98357a";
		sdmode-gpios = <&pio 175 0>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Google Kukui (and derivatives) audio fragment for rt1015p.
 *
 * Copyright 2020 Google LLC.
 */

/ {
	rt1015p: rt1015p {
		compatible = "realtek,rt1015p";
		sdb-gpios = <&pio 175 0>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Google Kukui (and derivatives) ts3a227e-max98357a sound card.
 *
 * Copyright 2020 Google LLC.
 */

#include "mt8183-kukui-audio-max98357a.dtsi"
#include "mt8183-kukui-audio-ts3a227e.dtsi"

&sound {
	compatible = "mediatek,mt8183_mt6358_ts3a227_max98357";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Google Kukui (and derivatives) mt6358-ts3a227-rt1015p sound card.
 *
 * Copyright 2021 Google LLC.
 */

#include "mt8183-kukui-audio-ts3a227e.dtsi"
#include "mt8183-kukui-audio-rt1015p.dtsi"

&sound {
	compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Google Kukui (and derivatives) audio fragment for ts3a227e.
 *
 * Copyright 2019 Google LLC.
 */

&i2c5 {
	ts3a227e: ts3a227e@3b {
		pinctrl-names = "default";
		pinctrl-0 = <&ts3a227e_pins>;
		compatible = "ti,ts3a227e";
		reg = <0x3b>;
		interrupt-parent = <&pio>;
		interrupts = <157 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";
	};
};

&pio {
	ts3a227e_pins: ts3a227e_pins {
		pins1 {
			pinmux = <PINMUX_GPIO157__FUNC_GPIO157>;
			input-enable;
			bias-pull-up;
		};
	};
};

&sound {
	mediatek,headset-codec = <&ts3a227e>;
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"

/ {
	model = "Google burnet board";
	compatible = "google,burnet", "mediatek,mt8183";
};

&mt6358codec {
	mediatek,dmic-mode = <1>; /* one-wire */
};

&i2c0 {
	touchscreen@2c {
		compatible = "hid-over-i2c";
		reg = <0x2c>;
		pinctrl-names = "default";
		pinctrl-0 = <&touchscreen_pins>;
		interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;

		post-power-on-delay-ms = <200>;
		hid-descr-addr = <0x0020>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"

/ {
	model = "Google cozmo board";
	compatible = "google,cozmo", "mediatek,mt8183";
};

&i2c_tunnel {
	google,remote-bus = <0>;
};

&i2c2 {
	trackpad@2c {
		compatible = "hid-over-i2c";
		reg = <0x2c>;
		hid-descr-addr = <0x20>;

		pinctrl-names = "default";
		pinctrl-0 = <&trackpad_pins>;

		interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;

		wakeup-source;
	};
};

&qca_wifi {
	qcom,ath10k-calibration-variant = "GO_COZMO";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-da7219-max98357a.dtsi"

/ {
	model = "Google damu board";
	compatible = "google,damu", "mediatek,mt8183";
};

&touchscreen {
	status = "okay";

	compatible = "hid-over-i2c";
	reg = <0x10>;
	interrupt-parent = <&pio>;
	interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&touchscreen_pins>;

	post-power-on-delay-ms = <10>;
	hid-descr-addr = <0x0001>;
};

&qca_wifi {
	qcom,ath10k-calibration-variant = "GO_DAMU";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"

/ {
	model = "Google fennel sku1 board";
	compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183";

	pwmleds {
		compatible = "pwm-leds";
		keyboard_backlight: keyboard-backlight {
			label = "cros_ec::kbd_backlight";
			pwms = <&cros_ec_pwm 0>;
			max-brightness = <1023>;
		};
	};
};

&cros_ec_pwm {
	status = "okay";
};

&touchscreen {
	status = "okay";

	compatible = "hid-over-i2c";
	reg = <0x10>;
	interrupt-parent = <&pio>;
	interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&touchscreen_pins>;

	post-power-on-delay-ms = <10>;
	hid-descr-addr = <0x0001>;
};

&qca_wifi {
	qcom,ath10k-calibration-variant = "GO_FENNEL";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"

/ {
	model = "Google fennel sku6 board";
	compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183";
};

&touchscreen {
	status = "okay";

	compatible = "hid-over-i2c";
	reg = <0x10>;
	interrupt-parent = <&pio>;
	interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&touchscreen_pins>;

	post-power-on-delay-ms = <10>;
	hid-descr-addr = <0x0001>;
};

&qca_wifi {
	qcom,ath10k-calibration-variant = "GO_FENNEL";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"

/ {
	model = "Google fennel sku7 board";
	compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183";
};

&touchscreen {
	status = "okay";

	compatible = "hid-over-i2c";
	reg = <0x10>;
	interrupt-parent = <&pio>;
	interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&touchscreen_pins>;

	post-power-on-delay-ms = <10>;
	hid-descr-addr = <0x0001>;
};

&qca_wifi {
	qcom,ath10k-calibration-variant = "GO_FENNEL";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"

&mt6358codec {
	mediatek,dmic-mode = <1>; /* one-wire */
};

&i2c2 {
	trackpad@2c {
		compatible = "hid-over-i2c";
		reg = <0x2c>;
		hid-descr-addr = <0x20>;

		pinctrl-names = "default";
		pinctrl-0 = <&trackpad_pins>;

		interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;

		wakeup-source;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-ts3a227e-rt1015p.dtsi"

/ {
	model = "Google fennel14 sku2 board";
	compatible = "google,fennel-sku2", "google,fennel", "mediatek,mt8183";
};

&qca_wifi {
	qcom,ath10k-calibration-variant = "GO_FENNEL14";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"

/ {
	model = "Google fennel14 sku0 board";
	compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183";
};

&qca_wifi {
	qcom,ath10k-calibration-variant = "GO_FENNEL14";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi-juniper.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"

/ {
	model = "Google juniper sku16 board";
	compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"

&i2c2 {
	trackpad@2c {
		compatible = "hid-over-i2c";
		reg = <0x2c>;
		hid-descr-addr = <0x20>;

		pinctrl-names = "default";
		pinctrl-0 = <&trackpad_pins>;

		interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;

		wakeup-source;
	};
};

&qca_wifi {
	qcom,ath10k-calibration-variant = "GO_JUNIPER";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"

/ {
	model = "Google kappa board";
	compatible = "google,kappa", "mediatek,mt8183";
};

&mt6358codec {
	mediatek,dmic-mode = <1>; /* one-wire */
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi-juniper.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"

/ {
	model = "Google kenzo sku17 board";
	compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi-willow.dtsi"
#include "mt8183-kukui-audio-da7219-max98357a.dtsi"

/ {
	model = "Google willow board sku0";
	compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-jacuzzi-willow.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"

/ {
	model = "Google willow board sku1";
	compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

#include "mt8183-kukui.dtsi"

/ {
	panel: panel {
		compatible = "auo,b116xw03";
		power-supply = <&pp3300_panel>;
		backlight = <&backlight_lcd0>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&anx7625_out>;
			};
		};
	};

	pp1200_mipibrdg: pp1200-mipibrdg {
		compatible = "regulator-fixed";
		regulator-name = "pp1200_mipibrdg";
		pinctrl-names = "default";
		pinctrl-0 = <&pp1200_mipibrdg_en>;

		enable-active-high;
		regulator-boot-on;

		gpio = <&pio 54 GPIO_ACTIVE_HIGH>;
	};

	pp1800_mipibrdg: pp1800-mipibrdg {
		compatible = "regulator-fixed";
		regulator-name = "pp1800_mipibrdg";
		pinctrl-names = "default";
		pinctrl-0 = <&pp1800_lcd_en>;

		enable-active-high;
		regulator-boot-on;

		gpio = <&pio 36 GPIO_ACTIVE_HIGH>;
	};

	pp3300_panel: pp3300-panel {
		compatible = "regulator-fixed";
		regulator-name = "pp3300_panel";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pp3300_panel_pins>;

		enable-active-high;
		regulator-boot-on;

		gpio = <&pio 35 GPIO_ACTIVE_HIGH>;
	};

	vddio_mipibrdg: vddio-mipibrdg {
		compatible = "regulator-fixed";
		regulator-name = "vddio_mipibrdg";
		pinctrl-names = "default";
		pinctrl-0 = <&vddio_mipibrdg_en>;

		enable-active-high;
		regulator-boot-on;

		gpio = <&pio 37 GPIO_ACTIVE_HIGH>;
	};

	volume_buttons: volume-buttons {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&volume_button_pins>;

		button-volume-down {
			label = "Volume Down";
			linux,code = <KEY_VOLUMEDOWN>;
			debounce-interval = <100>;

			gpios = <&pio 6 GPIO_ACTIVE_LOW>;
		};

		button-volume-up {
			label = "Volume Up";
			linux,code = <KEY_VOLUMEUP>;
			debounce-interval = <100>;

			gpios = <&pio 5 GPIO_ACTIVE_LOW>;
		};
	};
};

&cros_ec {
	cros_ec_pwm: pwm {
		compatible = "google,cros-ec-pwm";
		#pwm-cells = <1>;
		status = "disabled";
	};
};

&dsi0 {
	status = "okay";
	/delete-node/panel@0;
	ports {
		port {
			dsi_out: endpoint {
				remote-endpoint = <&anx7625_in>;
			};
		};
	};
};

&i2c0 {
	status = "okay";

	touchscreen: touchscreen@10 {
		compatible = "elan,ekth3500";
		reg = <0x10>;

		pinctrl-names = "default";
		pinctrl-0 = <&touchscreen_pins>;

		interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;

		reset-gpios = <&pio 156 GPIO_ACTIVE_LOW>;
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "okay";
	clock-frequency = <400000>;

	trackpad@15 {
		compatible = "elan,ekth3000";
		reg = <0x15>;

		pinctrl-names = "default";
		pinctrl-0 = <&trackpad_pins>;

		interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;

		wakeup-source;
	};
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins>;
	status = "okay";
	clock-frequency = <100000>;

	anx_bridge: anx7625@58 {
		compatible = "analogix,anx7625";
		reg = <0x58>;
		pinctrl-names = "default";
		pinctrl-0 = <&anx7625_pins>;
		panel_flags = <1>;
		enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
		vdd10-supply = <&pp1200_mipibrdg>;
		vdd18-supply = <&pp1800_mipibrdg>;
		vdd33-supply = <&vddio_mipibrdg>;

		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;

			anx7625_in: endpoint {
				remote-endpoint = <&dsi_out>;
			};
		};

		port@1 {
			reg = <1>;

			anx7625_out: endpoint {
				remote-endpoint = <&panel_in>;
			};
		};
	};
};

&i2c_tunnel {
	google,remote-bus = <2>;
};

&pio {
	/* 192 lines */
	gpio-line-names =
		"SPI_AP_EC_CS_L",
		"SPI_AP_EC_MOSI",
		"SPI_AP_EC_CLK",
		"I2S3_DO",
		"USB_PD_INT_ODL",
		"",
		"",
		"",
		"",
		"IT6505_HPD_L",
		"I2S3_TDM_D3",
		"SOC_I2C6_1V8_SCL",
		"SOC_I2C6_1V8_SDA",
		"DPI_D0",
		"DPI_D1",
		"DPI_D2",
		"DPI_D3",
		"DPI_D4",
		"DPI_D5",
		"DPI_D6",
		"DPI_D7",
		"DPI_D8",
		"DPI_D9",
		"DPI_D10",
		"DPI_D11",
		"DPI_HSYNC",
		"DPI_VSYNC",
		"DPI_DE",
		"DPI_CK",
		"AP_MSDC1_CLK",
		"AP_MSDC1_DAT3",
		"AP_MSDC1_CMD",
		"AP_MSDC1_DAT0",
		"AP_MSDC1_DAT2",
		"AP_MSDC1_DAT1",
		"",
		"",
		"",
		"",
		"",
		"",
		"OTG_EN",
		"DRVBUS",
		"DISP_PWM",
		"DSI_TE",
		"LCM_RST_1V8",
		"AP_CTS_WIFI_RTS",
		"AP_RTS_WIFI_CTS",
		"SOC_I2C5_1V8_SCL",
		"SOC_I2C5_1V8_SDA",
		"SOC_I2C3_1V8_SCL",
		"SOC_I2C3_1V8_SDA",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"SOC_I2C1_1V8_SDA",
		"SOC_I2C0_1V8_SDA",
		"SOC_I2C0_1V8_SCL",
		"SOC_I2C1_1V8_SCL",
		"AP_SPI_H1_MISO",
		"AP_SPI_H1_CS_L",
		"AP_SPI_H1_MOSI",
		"AP_SPI_H1_CLK",
		"I2S5_BCK",
		"I2S5_LRCK",
		"I2S5_DO",
		"BOOTBLOCK_EN_L",
		"MT8183_KPCOL0",
		"SPI_AP_EC_MISO",
		"UART_DBG_TX_AP_RX",
		"UART_AP_TX_DBG_RX",
		"I2S2_MCK",
		"I2S2_BCK",
		"CLK_5M_WCAM",
		"CLK_2M_UCAM",
		"I2S2_LRCK",
		"I2S2_DI",
		"SOC_I2C2_1V8_SCL",
		"SOC_I2C2_1V8_SDA",
		"SOC_I2C4_1V8_SCL",
		"SOC_I2C4_1V8_SDA",
		"",
		"SCL8",
		"SDA8",
		"FCAM_PWDN_L",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"",
		"",
		"",
		"",
		"",
		"",
		/*
		 * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics
		 * call it BIOS_FLASH_WP_R_L.
		 */
		"AP_FLASH_WP_L",
		"EC_AP_INT_ODL",
		"IT6505_INT_ODL",
		"H1_INT_OD_L",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"AP_SPI_FLASH_MISO",
		"AP_SPI_FLASH_CS_L",
		"AP_SPI_FLASH_MOSI",
		"AP_SPI_FLASH_CLK",
		"DA7219_IRQ",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"";

	pp1200_mipibrdg_en: pp1200-mipibrdg-en {
		pins1 {
			pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
			output-low;
		};
	};

	pp1800_lcd_en: pp1800-lcd-en {
		pins1 {
			pinmux = <PINMUX_GPIO36__FUNC_GPIO36>;
			output-low;
		};
	};

	pp3300_panel_pins: pp3300-panel-pins {
		panel_3v3_enable: panel-3v3-enable {
			pinmux = <PINMUX_GPIO35__FUNC_GPIO35>;
			output-low;
		};
	};

	ppvarp_lcd_en: ppvarp-lcd-en {
		pins1 {
			pinmux = <PINMUX_GPIO66__FUNC_GPIO66>;
			output-low;
		};
	};

	ppvarn_lcd_en: ppvarn-lcd-en {
		pins1 {
			pinmux = <PINMUX_GPIO166__FUNC_GPIO166>;
			output-low;
		};
	};

	anx7625_pins: anx7625-pins {
		pins1 {
			pinmux = <PINMUX_GPIO45__FUNC_GPIO45>,
				 <PINMUX_GPIO73__FUNC_GPIO73>;
			output-low;
		};
		pins2 {
			pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
			input-enable;
			bias-pull-up;
		};
	};

	touchscreen_pins: touchscreen-pins {
		touch_int_odl {
			pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
			input-enable;
			bias-pull-up;
		};

		touch_rst_l {
			pinmux = <PINMUX_GPIO156__FUNC_GPIO156>;
			output-high;
		};
	};

	trackpad_pins: trackpad-pins {
		trackpad_int {
			pinmux = <PINMUX_GPIO7__FUNC_GPIO7>;
			input-enable;
			bias-disable; /* pulled externally */
		};
	};

	vddio_mipibrdg_en: vddio-mipibrdg-en {
		pins1 {
			pinmux = <PINMUX_GPIO37__FUNC_GPIO37>;
			output-low;
		};
	};

	volume_button_pins: volume-button-pins {
		voldn-btn-odl {
			pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
			input-enable;
			bias-pull-up;
		};

		volup-btn-odl {
			pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
			input-enable;
			bias-pull-up;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-kakadu.dtsi"
#include "mt8183-kukui-audio-rt1015p.dtsi"

/ {
	model = "MediaTek kakadu board sku22";
	compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22",
		     "google,kakadu", "mediatek,mt8183";
};

&sound {
	compatible = "mediatek,mt8183_mt6358_ts3a227_rt1015p";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui-kakadu.dtsi"
#include "mt8183-kukui-audio-da7219-rt1015p.dtsi"

/ {
	model = "MediaTek kakadu board";
	compatible = "google,kakadu-rev3", "google,kakadu-rev2",
			"google,kakadu", "mediatek,mt8183";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Google LLC
 */

#include "mt8183-kukui.dtsi"
#include <dt-bindings/input/gpio-keys.h>

/ {
	ppvarn_lcd: ppvarn-lcd {
		compatible = "regulator-fixed";
		regulator-name = "ppvarn_lcd";
		pinctrl-names = "default";
		pinctrl-0 = <&ppvarn_lcd_en>;

		enable-active-high;

		gpio = <&pio 66 GPIO_ACTIVE_HIGH>;
	};

	ppvarp_lcd: ppvarp-lcd {
		compatible = "regulator-fixed";
		regulator-name = "ppvarp_lcd";
		pinctrl-names = "default";
		pinctrl-0 = <&ppvarp_lcd_en>;

		enable-active-high;

		gpio = <&pio 166 GPIO_ACTIVE_HIGH>;
	};

	pp1800_lcd: pp1800-lcd {
		compatible = "regulator-fixed";
		regulator-name = "pp1800_lcd";
		pinctrl-names = "default";
		pinctrl-0 = <&pp1800_lcd_en>;

		enable-active-high;

		gpio = <&pio 36 GPIO_ACTIVE_HIGH>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pen_eject>;

		switch-pen-insert {
			label = "Pen Insert";
			/* Insert = low, eject = high */
			gpios = <&pio 6 GPIO_ACTIVE_LOW>;
			linux,code = <SW_PEN_INSERTED>;
			linux,input-type = <EV_SW>;
			wakeup-event-action = <EV_ACT_DEASSERTED>;
			wakeup-source;
		};
	};
};

&bluetooth {
	firmware-name = "nvm_00440302_i2s_eu.bin";
};

&i2c0 {
	status = "okay";

	touchscreen: touchscreen@10 {
		compatible = "hid-over-i2c";
		reg = <0x10>;
		pinctrl-names = "default";
		pinctrl-0 = <&open_touch>;

		interrupt-parent = <&pio>;
		interrupts = <155 IRQ_TYPE_EDGE_FALLING>;

		post-power-on-delay-ms = <10>;
		hid-descr-addr = <0x0001>;
	};
};

&mt6358_vcama2_reg {
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "okay";
	clock-frequency = <400000>;
	vbus-supply = <&mt6358_vcamio_reg>;

	eeprom@58 {
		compatible = "atmel,24c32";
		reg = <0x58>;
		pagesize = <32>;
		vcc-supply = <&mt6358_vcama2_reg>;
	};
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins>;
	status = "okay";
	clock-frequency = <400000>;
	vbus-supply = <&mt6358_vcn18_reg>;

	eeprom@54 {
		compatible = "atmel,24c32";
		reg = <0x54>;
		pagesize = <32>;
		vcc-supply = <&mt6358_vcn18_reg>;
	};
};

&mipi_tx0 {
	drive-strength-microamp = <5800>;
};

&pio {
	/* 192 lines */
	gpio-line-names =
		"SPI_AP_EC_CS_L",
		"SPI_AP_EC_MOSI",
		"SPI_AP_EC_CLK",
		"I2S3_DO",
		"USB_PD_INT_ODL",
		"",
		"",
		"",
		"",
		"IT6505_HPD_L",
		"I2S3_TDM_D3",
		"SOC_I2C6_1V8_SCL",
		"SOC_I2C6_1V8_SDA",
		"DPI_D0",
		"DPI_D1",
		"DPI_D2",
		"DPI_D3",
		"DPI_D4",
		"DPI_D5",
		"DPI_D6",
		"DPI_D7",
		"DPI_D8",
		"DPI_D9",
		"DPI_D10",
		"DPI_D11",
		"DPI_HSYNC",
		"DPI_VSYNC",
		"DPI_DE",
		"DPI_CK",
		"AP_MSDC1_CLK",
		"AP_MSDC1_DAT3",
		"AP_MSDC1_CMD",
		"AP_MSDC1_DAT0",
		"AP_MSDC1_DAT2",
		"AP_MSDC1_DAT1",
		"",
		"",
		"",
		"",
		"",
		"",
		"OTG_EN",
		"DRVBUS",
		"DISP_PWM",
		"DSI_TE",
		"LCM_RST_1V8",
		"AP_CTS_WIFI_RTS",
		"AP_RTS_WIFI_CTS",
		"SOC_I2C5_1V8_SCL",
		"SOC_I2C5_1V8_SDA",
		"SOC_I2C3_1V8_SCL",
		"SOC_I2C3_1V8_SDA",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"SOC_I2C1_1V8_SDA",
		"SOC_I2C0_1V8_SDA",
		"SOC_I2C0_1V8_SCL",
		"SOC_I2C1_1V8_SCL",
		"AP_SPI_H1_MISO",
		"AP_SPI_H1_CS_L",
		"AP_SPI_H1_MOSI",
		"AP_SPI_H1_CLK",
		"I2S5_BCK",
		"I2S5_LRCK",
		"I2S5_DO",
		"BOOTBLOCK_EN_L",
		"MT8183_KPCOL0",
		"SPI_AP_EC_MISO",
		"UART_DBG_TX_AP_RX",
		"UART_AP_TX_DBG_RX",
		"I2S2_MCK",
		"I2S2_BCK",
		"CLK_5M_WCAM",
		"CLK_2M_UCAM",
		"I2S2_LRCK",
		"I2S2_DI",
		"SOC_I2C2_1V8_SCL",
		"SOC_I2C2_1V8_SDA",
		"SOC_I2C4_1V8_SCL",
		"SOC_I2C4_1V8_SDA",
		"",
		"SCL8",
		"SDA8",
		"FCAM_PWDN_L",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"",
		"",
		"",
		"",
		"",
		"",
		/*
		 * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics
		 * call it BIOS_FLASH_WP_R_L.
		 */
		"AP_FLASH_WP_L",
		"EC_AP_INT_ODL",
		"IT6505_INT_ODL",
		"H1_INT_OD_L",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"AP_SPI_FLASH_MISO",
		"AP_SPI_FLASH_CS_L",
		"AP_SPI_FLASH_MOSI",
		"AP_SPI_FLASH_CLK",
		"DA7219_IRQ",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"";

	ppvarp_lcd_en: ppvarp-lcd-en {
		pins1 {
			pinmux = <PINMUX_GPIO66__FUNC_GPIO66>;
			output-low;
		};
	};

	ppvarn_lcd_en: ppvarn-lcd-en {
		pins1 {
			pinmux = <PINMUX_GPIO166__FUNC_GPIO166>;
			output-low;
		};
	};

	pp1800_lcd_en: pp1800-lcd-en {
		pins1 {
			pinmux = <PINMUX_GPIO36__FUNC_GPIO36>;
			output-low;
		};
	};

	open_touch: open_touch {
		irq_pin {
			pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
			input-enable;
			bias-pull-up;
		};

		rst_pin {
			pinmux = <PINMUX_GPIO156__FUNC_GPIO156>;

			/*
			 * The pen driver doesn't currently support  driving
			 * this reset line.  By specifying output-high here
			 * we're relying on the fact that this pin has a default
			 * pulldown at boot (which makes sure the pen was in
			 * reset if it was powered) and then we set it high here
			 * to take it out of reset.  Better would be if the pen
			 * driver could control this and we could remove
			 * "output-high" here.
			 */
			output-high;
		};
	};

	pen_eject: peneject {
		pen_eject {
			pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
			input-enable;
			/* External pull-up. */
			bias-disable;
		};
	};
};

&qca_wifi {
	qcom,ath10k-calibration-variant = "GO_KAKADU";
};

&panel {
	status = "okay";
	compatible = "boe,tv105wum-nw0";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 *
 * SKU: 0x10 => 16
 *  - bit 8: Camera: 0 (OV5695)
 *  - bits 7..4: Panel ID: 0x1 (AUO)
 */

/dts-v1/;
#include "mt8183-kukui-kodama.dtsi"

/ {
	model = "MediaTek kodama sku16 board";
	compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183";
};

&panel {
	status = "okay";
	compatible = "auo,b101uan08.3";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Google LLC
 *
 * SKU: 0x110 => 272
 *  - bit 8: Camera: 1 (GC5035)
 *  - bits 7..4: Panel ID: 0x1 (AUO)
 */

/dts-v1/;
#include "mt8183-kukui-kodama.dtsi"

/ {
	model = "MediaTek kodama sku272 board";
	compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183";
};

&panel {
	status = "okay";
	compatible = "auo,b101uan08.3";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Google LLC
 *
 * SKU: 0x120 => 288
 *  - bit 8: Camera: 1 (GC5035)
 *  - bits 7..4: Panel ID: 0x2 (BOE)
 */

/dts-v1/;
#include "mt8183-kukui-kodama.dtsi"

/ {
	model = "MediaTek kodama sku288 board";
	compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183";
};

&panel {
	status = "okay";
	compatible = "boe,tv101wum-n53";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 *
 * SKU: 0x20 => 32
 *  - bit 8: Camera: 0 (OV5695)
 *  - bits 7..4: Panel ID: 0x2 (BOE)
 */

/dts-v1/;
#include "mt8183-kukui-kodama.dtsi"

/ {
	model = "MediaTek kodama sku32 board";
	compatible = "google,kodama-sku32", "google,kodama", "mediatek,mt8183";
};

&panel {
	status = "okay";
	compatible = "boe,tv101wum-n53";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2021 Google LLC
 */

/dts-v1/;
#include "mt8183-kukui.dtsi"
#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"

/ {
	ppvarn_lcd: ppvarn-lcd {
		compatible = "regulator-fixed";
		regulator-name = "ppvarn_lcd";
		pinctrl-names = "default";
		pinctrl-0 = <&ppvarn_lcd_en>;

		enable-active-high;

		gpio = <&pio 66 GPIO_ACTIVE_HIGH>;
	};

	ppvarp_lcd: ppvarp-lcd {
		compatible = "regulator-fixed";
		regulator-name = "ppvarp_lcd";
		pinctrl-names = "default";
		pinctrl-0 = <&ppvarp_lcd_en>;

		enable-active-high;

		gpio = <&pio 166 GPIO_ACTIVE_HIGH>;
	};

	pp1800_lcd: pp1800-lcd {
		compatible = "regulator-fixed";
		regulator-name = "pp1800_lcd";
		pinctrl-names = "default";
		pinctrl-0 = <&pp1800_lcd_en>;

		enable-active-high;

		gpio = <&pio 36 GPIO_ACTIVE_HIGH>;
	};
};

&i2c0 {
	status = "okay";

	touchscreen: touchscreen@10 {
		compatible = "hid-over-i2c";
		reg = <0x10>;
		interrupt-parent = <&pio>;
		interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&touch_default>;

		post-power-on-delay-ms = <10>;
		hid-descr-addr = <0x0001>;
	};
};

&i2c2 {
        pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "okay";
	clock-frequency = <400000>;
	vbus-supply = <&mt6358_vcamio_reg>;

	eeprom@58 {
		compatible = "atmel,24c64";
		reg = <0x58>;
		pagesize = <32>;
		vcc-supply = <&mt6358_vcamio_reg>;
	};
};

&i2c4 {
        pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins>;
	status = "okay";
	clock-frequency = <400000>;
	vbus-supply = <&mt6358_vcn18_reg>;

	eeprom@54 {
		compatible = "atmel,24c64";
		reg = <0x54>;
		pagesize = <32>;
		vcc-supply = <&mt6358_vcn18_reg>;
	};
};

&mt6358_vcama2_reg {
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
};

&pio {
	/* 192 lines */
	gpio-line-names =
		"SPI_AP_EC_CS_L",
		"SPI_AP_EC_MOSI",
		"SPI_AP_EC_CLK",
		"I2S3_DO",
		"USB_PD_INT_ODL",
		"",
		"",
		"",
		"",
		"IT6505_HPD_L",
		"I2S3_TDM_D3",
		"SOC_I2C6_1V8_SCL",
		"SOC_I2C6_1V8_SDA",
		"DPI_D0",
		"DPI_D1",
		"DPI_D2",
		"DPI_D3",
		"DPI_D4",
		"DPI_D5",
		"DPI_D6",
		"DPI_D7",
		"DPI_D8",
		"DPI_D9",
		"DPI_D10",
		"DPI_D11",
		"DPI_HSYNC",
		"DPI_VSYNC",
		"DPI_DE",
		"DPI_CK",
		"AP_MSDC1_CLK",
		"AP_MSDC1_DAT3",
		"AP_MSDC1_CMD",
		"AP_MSDC1_DAT0",
		"AP_MSDC1_DAT2",
		"AP_MSDC1_DAT1",
		"",
		"",
		"",
		"",
		"",
		"",
		"OTG_EN",
		"DRVBUS",
		"DISP_PWM",
		"DSI_TE",
		"LCM_RST_1V8",
		"AP_CTS_WIFI_RTS",
		"AP_RTS_WIFI_CTS",
		"SOC_I2C5_1V8_SCL",
		"SOC_I2C5_1V8_SDA",
		"SOC_I2C3_1V8_SCL",
		"SOC_I2C3_1V8_SDA",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"SOC_I2C1_1V8_SDA",
		"SOC_I2C0_1V8_SDA",
		"SOC_I2C0_1V8_SCL",
		"SOC_I2C1_1V8_SCL",
		"AP_SPI_H1_MISO",
		"AP_SPI_H1_CS_L",
		"AP_SPI_H1_MOSI",
		"AP_SPI_H1_CLK",
		"I2S5_BCK",
		"I2S5_LRCK",
		"I2S5_DO",
		"BOOTBLOCK_EN_L",
		"MT8183_KPCOL0",
		"SPI_AP_EC_MISO",
		"UART_DBG_TX_AP_RX",
		"UART_AP_TX_DBG_RX",
		"I2S2_MCK",
		"I2S2_BCK",
		"CLK_5M_WCAM",
		"CLK_2M_UCAM",
		"I2S2_LRCK",
		"I2S2_DI",
		"SOC_I2C2_1V8_SCL",
		"SOC_I2C2_1V8_SDA",
		"SOC_I2C4_1V8_SCL",
		"SOC_I2C4_1V8_SDA",
		"",
		"SCL8",
		"SDA8",
		"FCAM_PWDN_L",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"",
		"",
		"",
		"",
		"",
		"",
		/*
		 * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics
		 * call it BIOS_FLASH_WP_R_L.
		 */
		"AP_FLASH_WP_L",
		"EC_AP_INT_ODL",
		"IT6505_INT_ODL",
		"H1_INT_OD_L",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"AP_SPI_FLASH_MISO",
		"AP_SPI_FLASH_CS_L",
		"AP_SPI_FLASH_MOSI",
		"AP_SPI_FLASH_CLK",
		"DA7219_IRQ",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"";

	ppvarp_lcd_en: ppvarp-lcd-en {
		pins1 {
			pinmux = <PINMUX_GPIO66__FUNC_GPIO66>;
			output-low;
		};
	};

	ppvarn_lcd_en: ppvarn-lcd-en {
		pins1 {
			pinmux = <PINMUX_GPIO166__FUNC_GPIO166>;
			output-low;
		};
	};

	pp1800_lcd_en: pp1800-lcd-en {
		pins1 {
			pinmux = <PINMUX_GPIO36__FUNC_GPIO36>;
			output-low;
		};
	};

	touch_default: touchdefault {
		pin_irq {
			pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
			input-enable;
			bias-pull-up;
		};

		touch_pin_reset: pin_reset {
			pinmux = <PINMUX_GPIO156__FUNC_GPIO156>;

			/*
			 * The touchscreen driver doesn't currently support driving
			 * this reset line.  By specifying output-high here
			 * we're relying on the fact that this pin has a default
			 * pulldown at boot (which makes sure the controller was in
			 * reset if it was powered) and then we set it high here
			 * to take it out of reset.  Better would be if the touchscreen
			 * driver could control this and we could remove
			 * "output-high" here.
			 */
			output-high;
		};
	};
};

&qca_wifi {
	qcom,ath10k-calibration-variant = "GO_KODAMA";
};

&i2c_tunnel {
        google,remote-bus = <2>;
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2019 Google LLC
 *
 * Device-tree for Krane sku0.
 *
 * SKU is a 8-bit value (0x00 == 0):
 *  - Bits 7..4: Panel ID: 0x0 (AUO)
 *  - Bits 3..0: SKU ID:   0x0 (default)
 */

/dts-v1/;
#include "mt8183-kukui-krane.dtsi"

/ {
	model = "MediaTek krane sku0 board";
	compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183";
};

&panel {
	status = "okay";
	compatible = "auo,kd101n80-45na";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2019 Google LLC
 *
 * Device-tree for Krane sku176.
 *
 * SKU is a 8-bit value (0xb0 == 176):
 *  - Bits 7..4: Panel ID: 0xb (BOE)
 *  - Bits 3..0: SKU ID:   0x0 (default)
 */

/dts-v1/;
#include "mt8183-kukui-krane.dtsi"

/ {
	model = "MediaTek krane sku176 board";
	compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183";
};

&panel {
        status = "okay";
        compatible = "boe,tv101wum-nl6";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2019 Google LLC
 */

#include "mt8183-kukui.dtsi"
#include "mt8183-kukui-audio-max98357a.dtsi"

/ {
	ppvarn_lcd: ppvarn-lcd {
		compatible = "regulator-fixed";
		regulator-name = "ppvarn_lcd";
		pinctrl-names = "default";
		pinctrl-0 = <&ppvarn_lcd_en>;

		enable-active-high;

		gpio = <&pio 66 GPIO_ACTIVE_HIGH>;
	};

	ppvarp_lcd: ppvarp-lcd {
		compatible = "regulator-fixed";
		regulator-name = "ppvarp_lcd";
		pinctrl-names = "default";
		pinctrl-0 = <&ppvarp_lcd_en>;

		enable-active-high;

		gpio = <&pio 166 GPIO_ACTIVE_HIGH>;
	};

	pp1800_lcd: pp1800-lcd {
		compatible = "regulator-fixed";
		regulator-name = "pp1800_lcd";
		pinctrl-names = "default";
		pinctrl-0 = <&pp1800_lcd_en>;

		enable-active-high;

		gpio = <&pio 36 GPIO_ACTIVE_HIGH>;
	};
};

&bluetooth {
	firmware-name = "nvm_00440302_i2s_eu.bin";
};

&i2c0 {
	status = "okay";

	touchscreen4: touchscreen@5d {
		compatible = "hid-over-i2c";
		reg = <0x5d>;
		pinctrl-names = "default";
		pinctrl-0 = <&open_touch>;

		interrupt-parent = <&pio>;
		interrupts = <155 IRQ_TYPE_EDGE_FALLING>;

		post-power-on-delay-ms = <10>;
		hid-descr-addr = <0x0001>;
	};
};

&mt6358_vcama2_reg {
	regulator-min-microvolt = <2800000>;
	regulator-max-microvolt = <2800000>;
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;
	status = "okay";
	clock-frequency = <400000>;
	vbus-supply = <&mt6358_vcamio_reg>;

	eeprom@58 {
		compatible = "atmel,24c32";
		reg = <0x58>;
		pagesize = <32>;
		vcc-supply = <&mt6358_vcama2_reg>;
	};
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_pins>;
	status = "okay";
	clock-frequency = <400000>;
	vbus-supply = <&mt6358_vcn18_reg>;

	eeprom@54 {
		compatible = "atmel,24c32";
		reg = <0x54>;
		pagesize = <32>;
		vcc-supply = <&mt6358_vcn18_reg>;
	};
};

&pio {
	/* 192 lines */
	gpio-line-names =
		"SPI_AP_EC_CS_L",
		"SPI_AP_EC_MOSI",
		"SPI_AP_EC_CLK",
		"I2S3_DO",
		"USB_PD_INT_ODL",
		"",
		"",
		"",
		"",
		"IT6505_HPD_L",
		"I2S3_TDM_D3",
		"SOC_I2C6_1V8_SCL",
		"SOC_I2C6_1V8_SDA",
		"DPI_D0",
		"DPI_D1",
		"DPI_D2",
		"DPI_D3",
		"DPI_D4",
		"DPI_D5",
		"DPI_D6",
		"DPI_D7",
		"DPI_D8",
		"DPI_D9",
		"DPI_D10",
		"DPI_D11",
		"DPI_HSYNC",
		"DPI_VSYNC",
		"DPI_DE",
		"DPI_CK",
		"AP_MSDC1_CLK",
		"AP_MSDC1_DAT3",
		"AP_MSDC1_CMD",
		"AP_MSDC1_DAT0",
		"AP_MSDC1_DAT2",
		"AP_MSDC1_DAT1",
		"",
		"",
		"",
		"",
		"",
		"",
		"OTG_EN",
		"DRVBUS",
		"DISP_PWM",
		"DSI_TE",
		"LCM_RST_1V8",
		"AP_CTS_WIFI_RTS",
		"AP_RTS_WIFI_CTS",
		"SOC_I2C5_1V8_SCL",
		"SOC_I2C5_1V8_SDA",
		"SOC_I2C3_1V8_SCL",
		"SOC_I2C3_1V8_SDA",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"SOC_I2C1_1V8_SDA",
		"SOC_I2C0_1V8_SDA",
		"SOC_I2C0_1V8_SCL",
		"SOC_I2C1_1V8_SCL",
		"AP_SPI_H1_MISO",
		"AP_SPI_H1_CS_L",
		"AP_SPI_H1_MOSI",
		"AP_SPI_H1_CLK",
		"I2S5_BCK",
		"I2S5_LRCK",
		"I2S5_DO",
		"BOOTBLOCK_EN_L",
		"MT8183_KPCOL0",
		"SPI_AP_EC_MISO",
		"UART_DBG_TX_AP_RX",
		"UART_AP_TX_DBG_RX",
		"I2S2_MCK",
		"I2S2_BCK",
		"CLK_5M_WCAM",
		"CLK_2M_UCAM",
		"I2S2_LRCK",
		"I2S2_DI",
		"SOC_I2C2_1V8_SCL",
		"SOC_I2C2_1V8_SDA",
		"SOC_I2C4_1V8_SCL",
		"SOC_I2C4_1V8_SDA",
		"",
		"SCL8",
		"SDA8",
		"FCAM_PWDN_L",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"I2S_PMIC",
		"",
		"",
		"",
		"",
		"",
		"",
		/*
		 * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics
		 * call it BIOS_FLASH_WP_R_L.
		 */
		"AP_FLASH_WP_L",
		"EC_AP_INT_ODL",
		"IT6505_INT_ODL",
		"H1_INT_OD_L",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"AP_SPI_FLASH_MISO",
		"AP_SPI_FLASH_CS_L",
		"AP_SPI_FLASH_MOSI",
		"AP_SPI_FLASH_CLK",
		"DA7219_IRQ",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"",
		"";

	ppvarp_lcd_en: ppvarp-lcd-en {
		pins1 {
			pinmux = <PINMUX_GPIO66__FUNC_GPIO66>;
			output-low;
		};
	};

	ppvarn_lcd_en: ppvarn-lcd-en {
		pins1 {
			pinmux = <PINMUX_GPIO166__FUNC_GPIO166>;
			output-low;
		};
	};

	pp1800_lcd_en: pp1800-lcd-en {
		pins1 {
			pinmux = <PINMUX_GPIO36__FUNC_GPIO36>;
			output-low;
		};
	};

	open_touch: open_touch {
		irq_pin {
			pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
			input-enable;
			bias-pull-up;
		};

		rst_pin {
			pinmux = <PINMUX_GPIO156__FUNC_GPIO156>;

			/*
			 * The pen driver doesn't currently support  driving
			 * this reset line.  By specifying output-high here
			 * we're relying on the fact that this pin has a default
			 * pulldown at boot (which makes sure the pen was in
			 * reset if it was powered) and then we set it high here
			 * to take it out of reset.  Better would be if the pen
			 * driver could control this and we could remove
			 * "output-high" here.
			 */
			output-high;
		};
	};
};

&qca_wifi {
	qcom,ath10k-calibration-variant = "LE_Krane";
};

&sound {
	compatible = "mediatek,mt8183_mt6358_ts3a227_max98357";
};