code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT8183 Pin Controller

maintainers:
  - Sean Wang <sean.wang@kernel.org>

description: |+
  The MediaTek's MT8183 Pin controller is used to control SoC pins.

properties:
  compatible:
    const: mediatek,mt8183-pinctrl

  reg:
    minItems: 10
    maxItems: 10

  reg-names:
    items:
      - const: iocfg0
      - const: iocfg1
      - const: iocfg2
      - const: iocfg3
      - const: iocfg4
      - const: iocfg5
      - const: iocfg6
      - const: iocfg7
      - const: iocfg8
      - const: eint

  gpio-controller: true

  "#gpio-cells":
    const: 2
    description: |
      Number of cells in GPIO specifier. Since the generic GPIO
      binding is used, the amount of cells must be specified as 2. See the below
      mentioned gpio binding representation for description of particular cells.

  gpio-ranges:
    minItems: 1
    maxItems: 5
    description: |
      GPIO valid number range.

  interrupt-controller: true

  interrupts:
    maxItems: 1

  "#interrupt-cells":
    const: 2

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"
  - gpio-ranges

patternProperties:
  '-[0-9]+$':
    type: object
    additionalProperties: false
    patternProperties:
      'pins':
        type: object
        additionalProperties: false
        description: |
          A pinctrl node should contain at least one subnodes representing the
          pinctrl groups available on the machine. Each subnode will list the
          pins it needs, and how they should be configured, with regard to muxer
          configuration, pullups, drive strength, input enable/disable and input
          schmitt.
        $ref: "/schemas/pinctrl/pincfg-node.yaml"

        properties:
          pinmux:
            description:
              integer array, represents gpio pin number and mux setting.
              Supported pin number and mux varies for different SoCs, and are
              defined as macros in <soc>-pinfunc.h directly.

          bias-disable: true

          bias-pull-up: true

          bias-pull-down: true

          input-enable: true

          input-disable: true

          output-low: true

          output-high: true

          input-schmitt-enable: true

          input-schmitt-disable: true

          drive-strength:
            enum: [2, 4, 6, 8, 10, 12, 14, 16]

          mediatek,drive-strength-adv:
            description: |
              Describe the specific driving setup property.
              For I2C pins, the existing generic driving setup can only support
              2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
              can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
              driving setup, the existing generic setup will be disabled.
              The specific driving setup is controlled by E1E0EN.
              When E1=0/E0=0, the strength is 0.125mA.
              When E1=0/E0=1, the strength is 0.25mA.
              When E1=1/E0=0, the strength is 0.5mA.
              When E1=1/E0=1, the strength is 1mA.
              EN is used to enable or disable the specific driving setup.
              Valid arguments are described as below:
              0: (E1, E0, EN) = (0, 0, 0)
              1: (E1, E0, EN) = (0, 0, 1)
              2: (E1, E0, EN) = (0, 1, 0)
              3: (E1, E0, EN) = (0, 1, 1)
              4: (E1, E0, EN) = (1, 0, 0)
              5: (E1, E0, EN) = (1, 0, 1)
              6: (E1, E0, EN) = (1, 1, 0)
              7: (E1, E0, EN) = (1, 1, 1)
              So the valid arguments are from 0 to 7.
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [0, 1, 2, 3, 4, 5, 6, 7]

          mediatek,pull-up-adv:
            description: |
              Pull up setings for 2 pull resistors, R0 and R1. User can
              configure those special pins. Valid arguments are described as below:
              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [0, 1, 2, 3]

          mediatek,pull-down-adv:
            description: |
              Pull down settings for 2 pull resistors, R0 and R1. User can
              configure those special pins. Valid arguments are described as below:
              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [0, 1, 2, 3]

          mediatek,tdsel:
            description: |
              An integer describing the steps for output level shifter duty
              cycle when asserted (high pulse width adjustment). Valid arguments
              are from 0 to 15.
            $ref: /schemas/types.yaml#/definitions/uint32

          mediatek,rdsel:
            description: |
              An integer describing the steps for input level shifter duty cycle
              when asserted (high pulse width adjustment). Valid arguments are
              from 0 to 63.
            $ref: /schemas/types.yaml#/definitions/uint32

        required:
          - pinmux

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/pinctrl/mt8183-pinfunc.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pio: pinctrl@10005000 {
          compatible = "mediatek,mt8183-pinctrl";
          reg = <0 0x10005000 0 0x1000>,
                <0 0x11f20000 0 0x1000>,
                <0 0x11e80000 0 0x1000>,
                <0 0x11e70000 0 0x1000>,
                <0 0x11e90000 0 0x1000>,
                <0 0x11d30000 0 0x1000>,
                <0 0x11d20000 0 0x1000>,
                <0 0x11c50000 0 0x1000>,
                <0 0x11f30000 0 0x1000>,
                <0 0x1000b000 0 0x1000>;
          reg-names = "iocfg0", "iocfg1", "iocfg2",
                "iocfg3", "iocfg4", "iocfg5",
                "iocfg6", "iocfg7", "iocfg8",
                "eint";
          gpio-controller;
          #gpio-cells = <2>;
          gpio-ranges = <&pio 0 0 192>;
          interrupt-controller;
          interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
          #interrupt-cells = <2>;

          i2c0_pins_a: i2c-0 {
            pins1 {
              pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
                <PINMUX_GPIO49__FUNC_SDA5>;
              mediatek,pull-up-adv = <3>;
              mediatek,drive-strength-adv = <7>;
            };
          };

          i2c1_pins_a: i2c-1 {
            pins {
              pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
                <PINMUX_GPIO51__FUNC_SDA3>;
              mediatek,pull-down-adv = <2>;
              mediatek,drive-strength-adv = <4>;
            };
          };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek MT8188 Pin Controller

maintainers:
  - Hui Liu <hui.liu@mediatek.com>

description: |
  The MediaTek's MT8188 Pin controller is used to control SoC pins.

properties:
  compatible:
    const: mediatek,mt8188-pinctrl

  gpio-controller: true

  '#gpio-cells':
    description: |
      Number of cells in GPIO specifier, should be two. The first cell
      is the pin number, the second cell is used to specify optional
      parameters which are defined in <dt-bindings/gpio/gpio.h>.
    const: 2

  gpio-ranges:
    maxItems: 1

  gpio-line-names: true

  reg:
    items:
      - description: gpio registers base address
      - description: rm group io configuration registers base address
      - description: lt group io configuration registers base address
      - description: lm group io configuration registers base address
      - description: rt group io configuration registers base address
      - description: eint registers base address

  reg-names:
    items:
      - const: iocfg0
      - const: iocfg_rm
      - const: iocfg_lt
      - const: iocfg_lm
      - const: iocfg_rt
      - const: eint

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  interrupts:
    description: The interrupt outputs to sysirq.
    maxItems: 1

  mediatek,rsel-resistance-in-si-unit:
    type: boolean
    description: |
      We provide two methods to select the resistance for I2C when pull up or pull down.
      The first is by RSEL definition value, another one is by resistance value(ohm).
      This flag is used to identify if the method is resistance(si unit) value.

# PIN CONFIGURATION NODES
patternProperties:
  '-pins$':
    type: object
    additionalProperties: false

    patternProperties:
      '^pins':
        type: object
        $ref: "/schemas/pinctrl/pincfg-node.yaml"
        additionalProperties: false
        description: |
          A pinctrl node should contain at least one subnode representing the
          pinctrl groups available on the machine. Each subnode will list the
          pins it needs, and how they should be configured, with regard to muxer
          configuration, pullups, drive strength, input enable/disable and
          input schmitt.

        properties:
          pinmux:
            description: |
              Integer array, represents gpio pin number and mux setting.
              Supported pin number and mux varies for different SoCs, and are
              defined as macros in dt-bindings/pinctrl/mediatek,<soc>-pinfunc.h
              directly.

          drive-strength:
            enum: [2, 4, 6, 8, 10, 12, 14, 16]

          drive-strength-microamp:
            enum: [125, 250, 500, 1000]

          bias-pull-down:
            oneOf:
              - type: boolean
              - enum: [100, 101, 102, 103]
                description: mt8188 pull down PUPD/R0/R1 type define value.
              - enum: [200, 201, 202, 203, 204, 205, 206, 207]
                description: mt8188 pull down RSEL type define value.
              - enum: [75000, 5000]
                description: mt8188 pull down RSEL type si unit value(ohm).
            description: |
              For pull down type is normal, it doesn't need add RSEL & R1R0 define
              and resistance value.
              For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
              set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
              "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11"
              define in mt8188.
              For pull down type is RSEL, it can add RSEL define & resistance value(ohm)
              to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit".
              It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
              & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100"
              & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
              define in mt8188. It can also support resistance value(ohm) "75000" & "5000" in mt8188.

          bias-pull-up:
            oneOf:
              - type: boolean
              - enum: [100, 101, 102, 103]
                description: mt8188 pull up PUPD/R0/R1 type define value.
              - enum: [200, 201, 202, 203, 204, 205, 206, 207]
                description: mt8188 pull up RSEL type define value.
              - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
                description: mt8188 pull up RSEL type si unit value(ohm).
            description: |
              For pull up type is normal, it don't need add RSEL & R1R0 define
              and resistance value.
              For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
              set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
              "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11"
              define in mt8188.
              For pull up type is RSEL, it can add RSEL define & resistance value(ohm)
              to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit".
              It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
              & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100"
              & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
              define in mt8188. It can also support resistance value(ohm)
              "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8188.

          bias-disable: true

          output-high: true

          output-low: true

          input-enable: true

          input-disable: true

          input-schmitt-enable: true

          input-schmitt-disable: true

        required:
          - pinmux

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pio: pinctrl@10005000 {
        compatible = "mediatek,mt8188-pinctrl";
        reg = <0x10005000 0x1000>,
              <0x11c00000 0x1000>,
              <0x11e10000 0x1000>,
              <0x11e20000 0x1000>,
              <0x11ea0000 0x1000>,
              <0x1000b000 0x1000>;
        reg-names = "iocfg0", "iocfg_rm",
                    "iocfg_lt", "iocfg_lm", "iocfg_rt",
                    "eint";
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&pio 0 0 176>;
        interrupt-controller;
        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
        #interrupt-cells = <2>;

        pio-pins {
            pins {
                pinmux = <PINMUX_GPIO0__FUNC_B_GPIO0>;
                output-low;
            };
        };

        spi0-pins {
            pins-spi {
                pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>,
                         <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>,
                         <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>;
                drive-strength = <6>;
            };
            pins-spi-mi {
                pinmux = <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>;
                bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
            };
        };

        i2c0-pins {
            pins {
                pinmux = <PINMUX_GPIO55__FUNC_B1_SCL0>,
                         <PINMUX_GPIO56__FUNC_B1_SDA0>;
                bias-disable;
                drive-strength-microamp = <1000>;
            };
        };
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT6795 Pin Controller

maintainers:
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  - Sean Wang <sean.wang@kernel.org>

description: |
  The Mediatek's Pin controller is used to control SoC pins.

properties:
  compatible:
    const: mediatek,mt6795-pinctrl

  gpio-controller: true

  '#gpio-cells':
    description: |
      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
      the amount of cells must be specified as 2. See the below
      mentioned gpio binding representation for description of particular cells.
    const: 2

  gpio-ranges:
    description: GPIO valid number range.
    maxItems: 1

  reg:
    description:
      Physical address base for gpio base and eint registers.
    minItems: 2

  reg-names:
    items:
      - const: base
      - const: eint

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  interrupts:
    description: Interrupt outputs to the system interrupt controller (sysirq).
    minItems: 1
    items:
      - description: EINT interrupt
      - description: EINT event_b interrupt

# PIN CONFIGURATION NODES
patternProperties:
  '-pins$':
    type: object
    additionalProperties: false
    patternProperties:
      '^pins':
        type: object
        additionalProperties: false
        description: |
          A pinctrl node should contain at least one subnodes representing the
          pinctrl groups available on the machine. Each subnode will list the
          pins it needs, and how they should be configured, with regard to muxer
          configuration, pullups, drive strength, input enable/disable and
          input schmitt.
          An example of using macro:
          pincontroller {
            /* GPIO0 set as multifunction GPIO0 */
            gpio-pins {
              pins {
                pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
              }
            };
            /* GPIO45 set as multifunction SDA0 */
            i2c0-pins {
              pins {
                pinmux = <PINMUX_GPIO45__FUNC_SDA0>;
              }
            };
          };
        $ref: "pinmux-node.yaml"

        properties:
          pinmux:
            description: |
              Integer array, represents gpio pin number and mux setting.
              Supported pin number and mux varies for different SoCs, and are
              defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
              directly.

          drive-strength:
            enum: [2, 4, 6, 8, 10, 12, 14, 16]

          bias-pull-down:
            oneOf:
              - type: boolean
              - enum: [100, 101, 102, 103]
                description: mt6795 pull down PUPD/R0/R1 type define value.
            description: |
               For normal pull down type, it is not necessary to specify R1R0
               values; When pull down type is PUPD/R0/R1, adding R1R0 defines
               will set different resistance values.

          bias-pull-up:
            oneOf:
              - type: boolean
              - enum: [100, 101, 102, 103]
                description: mt6795 pull up PUPD/R0/R1 type define value.
            description: |
               For normal pull up type, it is not necessary to specify R1R0
               values; When pull up type is PUPD/R0/R1, adding R1R0 defines
               will set different resistance values.

          bias-disable: true

          output-high: true

          output-low: true

          input-enable: true

          input-disable: true

          input-schmitt-enable: true

          input-schmitt-disable: true

          mediatek,pull-up-adv:
            description: |
              Pull up setings for 2 pull resistors, R0 and R1. User can
              configure those special pins. Valid arguments are described as below:
              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [0, 1, 2, 3]

          mediatek,pull-down-adv:
            description: |
              Pull down settings for 2 pull resistors, R0 and R1. User can
              configure those special pins. Valid arguments are described as below:
              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
            $ref: /schemas/types.yaml#/definitions/uint32
            enum: [0, 1, 2, 3]

        required:
          - pinmux

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/pinctrl/mt6795-pinfunc.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pio: pinctrl@10005000 {
            compatible = "mediatek,mt6795-pinctrl";
            reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
            reg-names = "base", "eint";
            gpio-controller;
            #gpio-cells = <2>;
            gpio-ranges = <&pio 0 0 196>;
            interrupt-controller;
            interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
            #interrupt-cells = <2>;

            i2c0-pins {
                pins-sda-scl {
                    pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
                             <PINMUX_GPIO46__FUNC_SCL0>;
                };
            };

            mmc0-pins {
                pins-cmd-dat {
                    pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
                             <PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
                             <PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
                             <PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
                             <PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
                             <PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
                             <PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
                             <PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
                             <PINMUX_GPIO162__FUNC_MSDC0_CMD>;
                    input-enable;
                    bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
                };

                pins-clk {
                    pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
                    bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
                };

                pins-rst {
                    pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
                    bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
                };
            };
        };
    };


code:
== Amlogic Meson pinmux controller ==

Required properties for the root node:
 - compatible: one of "amlogic,meson8-cbus-pinctrl"
		      "amlogic,meson8b-cbus-pinctrl"
		      "amlogic,meson8m2-cbus-pinctrl"
		      "amlogic,meson8-aobus-pinctrl"
		      "amlogic,meson8b-aobus-pinctrl"
		      "amlogic,meson8m2-aobus-pinctrl"
		      "amlogic,meson-gxbb-periphs-pinctrl"
		      "amlogic,meson-gxbb-aobus-pinctrl"
		      "amlogic,meson-gxl-periphs-pinctrl"
		      "amlogic,meson-gxl-aobus-pinctrl"
		      "amlogic,meson-axg-periphs-pinctrl"
		      "amlogic,meson-axg-aobus-pinctrl"
		      "amlogic,meson-g12a-periphs-pinctrl"
		      "amlogic,meson-g12a-aobus-pinctrl"
		      "amlogic,meson-a1-periphs-pinctrl"
		      "amlogic,meson-s4-periphs-pinctrl"
 - reg: address and size of registers controlling irq functionality

=== GPIO sub-nodes ===

The GPIO bank for the controller is represented as a sub-node and it acts as a
GPIO controller.

Required properties for sub-nodes are:
 - reg: should contain a list of address and size, one tuple for each entry
   in reg-names.
 - reg-names: an array of strings describing the "reg" entries.
   Must contain "mux" and "gpio".
   May contain "pull", "pull-enable" and "ds" when appropriate.
 - gpio-controller: identifies the node as a gpio controller
 - #gpio-cells: must be 2

=== Other sub-nodes ===

Child nodes without the "gpio-controller" represent some desired
configuration for a pin or a group. Those nodes can be pinmux nodes or
configuration nodes.

Required properties for pinmux nodes are:
 - groups: a list of pinmux groups. The list of all available groups
   depends on the SoC and can be found in driver sources.
 - function: the name of a function to activate for the specified set
   of groups. The list of all available functions depends on the SoC
   and can be found in driver sources.

Required properties for configuration nodes:
 - pins: a list of pin names

Configuration nodes support the following generic properties, as
described in file pinctrl-bindings.txt:
 - "bias-disable"
 - "bias-pull-up"
 - "bias-pull-down"
 - "output-enable"
 - "output-disable"
 - "output-low"
 - "output-high"

Optional properties :
 - drive-strength-microamp: Drive strength for the specified pins in uA.
			    This property is only valid for G12A and newer.

=== Example ===

	pinctrl: pinctrl@c1109880 {
		compatible = "amlogic,meson8-cbus-pinctrl";
		reg = <0xc1109880 0x10>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio: banks@c11080b0 {
			reg = <0xc11080b0 0x28>,
			      <0xc11080e8 0x18>,
			      <0xc1108120 0x18>,
			      <0xc1108030 0x30>;
			reg-names = "mux", "pull", "pull-enable", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
               };

		nand {
			mux {
				groups = "nand_io", "nand_io_ce0", "nand_io_ce1",
					 "nand_io_rb0", "nand_ale", "nand_cle",
					 "nand_wen_clk", "nand_ren_clk", "nand_dqs",
					 "nand_ce2", "nand_ce3";
				function = "nand";
			};
		};
	};


code:
* Microchip PIC32 Pin Controller

Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
../interrupt-controller/interrupts.txt for generic information regarding
pin controller, GPIO, and interrupt bindings.

PIC32 'pin configuration node' is a node of a group of pins which can be
used for a specific device or function. This node represents configurations of
pins, optional function, and optional mux related configuration.

Required properties for pin controller node:
 - compatible: "microchip,pic32mada-pinctrl"
 - reg: Address range of the pinctrl registers.
 - clocks: Clock specifier (see clock bindings for details)

Required properties for pin configuration sub-nodes:
 - pins: List of pins to which the configuration applies.

Optional properties for pin configuration sub-nodes:
----------------------------------------------------
 - function: Mux function for the specified pins.
 - bias-pull-up: Enable weak pull-up.
 - bias-pull-down: Enable weak pull-down.
 - input-enable: Set the pin as an input.
 - output-low: Set the pin as an output level low.
 - output-high: Set the pin as an output level high.
 - microchip,digital: Enable digital I/O.
 - microchip,analog: Enable analog I/O.

Example:

pic32_pinctrl: pinctrl@1f801400{
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "microchip,pic32mzda-pinctrl";
	reg = <0x1f801400 0x400>;
	clocks = <&rootclk PB1CLK>;

	pinctrl_uart2: pinctrl_uart2 {
		uart2-tx {
			pins = "G9";
			function = "U2TX";
			microchip,digital;
			output-low;
		};
		uart2-rx {
			pins = "B0";
			function = "U2RX";
			microchip,digital;
			input-enable;
		};
	};
};

uart2: serial@1f822200 {
	compatible = "microchip,pic32mzda-uart";
	reg = <0x1f822200 0x50>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microsemi/Microchip Serial GPIO controller

maintainers:
  - Lars Povlsen <lars.povlsen@microchip.com>

description: |
  By using a serial interface, the SIO controller significantly extend
  the number of available GPIOs with a minimum number of additional
  pins on the device. The primary purpose of the SIO controllers is to
  connect control signals from SFP modules and to act as an LED
  controller.

properties:
  $nodename:
    pattern: "^gpio@[0-9a-f]+$"

  compatible:
    enum:
      - microchip,sparx5-sgpio
      - mscc,ocelot-sgpio
      - mscc,luton-sgpio

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  microchip,sgpio-port-ranges:
    description: This is a sequence of tuples, defining intervals of
      enabled ports in the serial input stream. The enabled ports must
      match the hardware configuration in order for signals to be
      properly written/read to/from the controller holding
      registers. Being tuples, then number of arguments must be
      even. The tuples mast be ordered (low, high) and are
      inclusive.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    items:
      items:
        - description: |
            "low" indicates start bit number of range
          minimum: 0
          maximum: 31
        - description: |
            "high" indicates end bit number of range
          minimum: 0
          maximum: 31
    minItems: 1
    maxItems: 32

  bus-frequency:
    description: The sgpio controller frequency (Hz). This dictates
      the serial bitstream speed, which again affects the latency in
      getting control signals back and forth between external shift
      registers. The speed must be no larger than half the system
      clock, and larger than zero.
    default: 12500000

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: switch

patternProperties:
  "^gpio@[0-1]$":
    type: object
    properties:
      compatible:
        const: microchip,sparx5-sgpio-bank

      reg:
        description: |
          The GPIO bank number. "0" is designates the input pin bank,
          "1" the output bank.
        maxItems: 1

      gpio-controller: true

      '#gpio-cells':
        description: |
         Specifies the pin (port and bit) and flags. Note that the
         SGIO pin is defined by *2* numbers, a port number between 0
         and 31, and a bit index, 0 to 3. The maximum bit number is
         controlled indirectly by the "ngpios" property: (ngpios/32).
        const: 3

      interrupts:
        description: Specifies the sgpio IRQ (in parent controller)
        maxItems: 1

      interrupt-controller: true

      '#interrupt-cells':
        description:
          Specifies the pin (port and bit) and flags, as defined in
          defined in include/dt-bindings/interrupt-controller/irq.h
        const: 3

      ngpios:
        description: The numbers of GPIO's exposed. This must be a
          multiple of 32.
        minimum: 32
        maximum: 128

    required:
      - compatible
      - reg
      - gpio-controller
      - '#gpio-cells'
      - ngpios

    additionalProperties: false

additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - microchip,sgpio-port-ranges
  - "#address-cells"
  - "#size-cells"

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    sgpio2: gpio@1101059c {
      #address-cells = <1>;
      #size-cells = <0>;
      compatible = "microchip,sparx5-sgpio";
      clocks = <&sys_clk>;
      pinctrl-0 = <&sgpio2_pins>;
      pinctrl-names = "default";
      reg = <0x1101059c 0x118>;
      microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
      bus-frequency = <25000000>;
      sgpio_in2: gpio@0 {
        reg = <0>;
        compatible = "microchip,sparx5-sgpio-bank";
        gpio-controller;
        #gpio-cells = <3>;
        ngpios = <96>;
        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <3>;
      };
      sgpio_out2: gpio@1 {
        compatible = "microchip,sparx5-sgpio-bank";
        reg = <1>;
        gpio-controller;
        #gpio-cells = <3>;
        ngpios = <96>;
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microsemi Ocelot pin controller

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>
  - Lars Povlsen <lars.povlsen@microchip.com>

properties:
  compatible:
    enum:
      - microchip,lan966x-pinctrl
      - microchip,sparx5-pinctrl
      - mscc,jaguar2-pinctrl
      - mscc,luton-pinctrl
      - mscc,ocelot-pinctrl
      - mscc,serval-pinctrl
      - mscc,servalt-pinctrl

  reg:
    items:
      - description: Base address
      - description: Extended pin configuration registers
    minItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2

  gpio-ranges: true

  interrupts:
    maxItems: 1

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  resets:
    maxItems: 1

  reset-names:
    description: Optional shared switch reset.
    items:
      - const: switch

patternProperties:
  '-pins$':
    type: object
    allOf:
      - $ref: "pinmux-node.yaml"
      - $ref: "pincfg-node.yaml"

    properties:
      function: true
      pins: true
      output-high: true
      output-low: true
      drive-strength: true

    required:
      - function
      - pins

    additionalProperties: false

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges

allOf:
  - $ref: "pinctrl.yaml#"
  - if:
      properties:
        compatible:
          contains:
            enum:
              - microchip,lan966x-pinctrl
              - microchip,sparx5-pinctrl
    then:
      properties:
        reg:
          minItems: 2

additionalProperties: false

examples:
  - |
    gpio: pinctrl@71070034 {
        compatible = "mscc,ocelot-pinctrl";
        reg = <0x71070034 0x28>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&gpio 0 0 22>;

        uart_pins: uart-pins {
            pins = "GPIO_6", "GPIO_7";
            function = "uart";
        };

        uart2_pins: uart2-pins {
            pins = "GPIO_12", "GPIO_13";
            function = "uart2";
        };
    };

...


code:
Nuvoton NPCM7XX Pin Controllers

The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
the multiplexing block, Each pin supports GPIO functionality (GPIOx)
and multiple functions that directly connect the pin to different
hardware blocks.

Required properties:
- #address-cells : should be 1.
- #size-cells	 : should be 1.
- compatible	 : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
- ranges	 : defines mapping ranges between pin controller node (parent)
			to GPIO bank node (children).

=== GPIO Bank Subnode ===

The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.

Required GPIO Bank subnode-properties:
- reg 			: specifies physical base address and size of the GPIO
				bank registers.
- gpio-controller	: Marks the device node as a GPIO controller.
- #gpio-cells		: Must be <2>. The first cell is the gpio pin number
				and the second cell is used for optional parameters.
- interrupts		: contain the GPIO bank interrupt with flags for falling edge.
- gpio-ranges		: defines the range of pins managed by the GPIO bank controller.

For example, GPIO bank subnodes like the following:
	gpio0: gpio@f0010000 {
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x0 0x80>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		gpio-ranges = <&pinctrl 0 0 32>;
	};

=== Pin Mux Subnode ===

- pin: A string containing the name of the pin
	An array of strings, each string containing the name of a pin.
	These pin are used for selecting pin configuration.

The following are the list of pins available:
	"GPIO0/IOX1DI", "GPIO1/IOX1LD",	"GPIO2/IOX1CK", "GPIO3/IOX1D0",
	"GPIO4/IOX2DI/SMB1DSDA", "GPIO5/IOX2LD/SMB1DSCL", "GPIO6/IOX2CK/SMB2DSDA",
	"GPIO7/IOX2D0/SMB2DSCL", "GPIO8/LKGPO1", "GPIO9/LKGPO2", "GPIO10/IOXHLD",
	"GPIO11/IOXHCK", "GPIO12/GSPICK/SMB5BSCL", "GPIO13/GSPIDO/SMB5BSDA",
	"GPIO14/GSPIDI/SMB5CSCL", "GPIO15/GSPICS/SMB5CSDA", "GPIO16/LKGPO0",
	"GPIO17/PSPI2DI/SMB4DEN","GPIO18/PSPI2D0/SMB4BSDA", "GPIO19/PSPI2CK/SMB4BSCL",
	"GPIO20/SMB4CSDA/SMB15SDA", "GPIO21/SMB4CSCL/SMB15SCL", "GPIO22/SMB4DSDA/SMB14SDA",
	"GPIO23/SMB4DSCL/SMB14SCL", "GPIO24/IOXHDO", "GPIO25/IOXHDI", "GPIO26/SMB5SDA",
	"GPIO27/SMB5SCL", "GPIO28/SMB4SDA", "GPIO29/SMB4SCL", "GPIO30/SMB3SDA",
	"GPIO31/SMB3SCL", "GPIO32/nSPI0CS1","SPI0D2", "SPI0D3", "GPIO37/SMB3CSDA",
	"GPIO38/SMB3CSCL", "GPIO39/SMB3BSDA", "GPIO40/SMB3BSCL", "GPIO41/BSPRXD",
	"GPO42/BSPTXD/STRAP11", "GPIO43/RXD1/JTMS2/BU1RXD", "GPIO44/nCTS1/JTDI2/BU1CTS",
	"GPIO45/nDCD1/JTDO2", "GPIO46/nDSR1/JTCK2", "GPIO47/nRI1/JCP_RDY2",
	"GPIO48/TXD2/BSPTXD", "GPIO49/RXD2/BSPRXD", "GPIO50/nCTS2", "GPO51/nRTS2/STRAP2",
	"GPIO52/nDCD2", "GPO53/nDTR2_BOUT2/STRAP1", "GPIO54/nDSR2", "GPIO55/nRI2",
	"GPIO56/R1RXERR", "GPIO57/R1MDC", "GPIO58/R1MDIO", "GPIO59/SMB3DSDA",
	"GPIO60/SMB3DSCL", "GPO61/nDTR1_BOUT1/STRAP6", "GPO62/nRTST1/STRAP5",
	"GPO63/TXD1/STRAP4", "GPIO64/FANIN0", "GPIO65/FANIN1", "GPIO66/FANIN2",
	"GPIO67/FANIN3", "GPIO68/FANIN4", "GPIO69/FANIN5", "GPIO70/FANIN6", "GPIO71/FANIN7",
	"GPIO72/FANIN8", "GPIO73/FANIN9", "GPIO74/FANIN10", "GPIO75/FANIN11",
	"GPIO76/FANIN12", "GPIO77/FANIN13","GPIO78/FANIN14", "GPIO79/FANIN15",
	"GPIO80/PWM0", "GPIO81/PWM1", "GPIO82/PWM2", "GPIO83/PWM3", "GPIO84/R2TXD0",
	"GPIO85/R2TXD1", "GPIO86/R2TXEN", "GPIO87/R2RXD0", "GPIO88/R2RXD1", "GPIO89/R2CRSDV",
	"GPIO90/R2RXERR", "GPIO91/R2MDC", "GPIO92/R2MDIO", "GPIO93/GA20/SMB5DSCL",
	"GPIO94/nKBRST/SMB5DSDA", "GPIO95/nLRESET/nESPIRST", "GPIO96/RG1TXD0",
	"GPIO97/RG1TXD1", "GPIO98/RG1TXD2", "GPIO99/RG1TXD3","GPIO100/RG1TXC",
	"GPIO101/RG1TXCTL", "GPIO102/RG1RXD0", "GPIO103/RG1RXD1", "GPIO104/RG1RXD2",
	"GPIO105/RG1RXD3", "GPIO106/RG1RXC", "GPIO107/RG1RXCTL", "GPIO108/RG1MDC",
	"GPIO109/RG1MDIO", "GPIO110/RG2TXD0/DDRV0", "GPIO111/RG2TXD1/DDRV1",
	"GPIO112/RG2TXD2/DDRV2", "GPIO113/RG2TXD3/DDRV3", "GPIO114/SMB0SCL",
	"GPIO115/SMB0SDA", "GPIO116/SMB1SCL", "GPIO117/SMB1SDA", "GPIO118/SMB2SCL",
	"GPIO119/SMB2SDA", "GPIO120/SMB2CSDA", "GPIO121/SMB2CSCL", "GPIO122/SMB2BSDA",
	"GPIO123/SMB2BSCL", "GPIO124/SMB1CSDA", "GPIO125/SMB1CSCL","GPIO126/SMB1BSDA",
	"GPIO127/SMB1BSCL", "GPIO128/SMB8SCL", "GPIO129/SMB8SDA", "GPIO130/SMB9SCL",
	"GPIO131/SMB9SDA", "GPIO132/SMB10SCL", "GPIO133/SMB10SDA","GPIO134/SMB11SCL",
	"GPIO135/SMB11SDA", "GPIO136/SD1DT0", "GPIO137/SD1DT1", "GPIO138/SD1DT2",
	"GPIO139/SD1DT3", "GPIO140/SD1CLK", "GPIO141/SD1WP", "GPIO142/SD1CMD",
	"GPIO143/SD1CD/SD1PWR", "GPIO144/PWM4",	"GPIO145/PWM5",	"GPIO146/PWM6",
	"GPIO147/PWM7",	"GPIO148/MMCDT4", "GPIO149/MMCDT5", "GPIO150/MMCDT6",
	"GPIO151/MMCDT7", "GPIO152/MMCCLK", "GPIO153/MMCWP", "GPIO154/MMCCMD",
	"GPIO155/nMMCCD/nMMCRST", "GPIO156/MMCDT0", "GPIO157/MMCDT1", "GPIO158/MMCDT2",
	"GPIO159/MMCDT3", "GPIO160/CLKOUT/RNGOSCOUT", "GPIO161/nLFRAME/nESPICS",
	"GPIO162/SERIRQ", "GPIO163/LCLK/ESPICLK", "GPIO164/LAD0/ESPI_IO0",
	"GPIO165/LAD1/ESPI_IO1", "GPIO166/LAD2/ESPI_IO2", "GPIO167/LAD3/ESPI_IO3",
	"GPIO168/nCLKRUN/nESPIALERT", "GPIO169/nSCIPME", "GPIO170/nSMI", "GPIO171/SMB6SCL",
	"GPIO172/SMB6SDA", "GPIO173/SMB7SCL", "GPIO174/SMB7SDA", "GPIO175/PSPI1CK/FANIN19",
	"GPIO176/PSPI1DO/FANIN18", "GPIO177/PSPI1DI/FANIN17", "GPIO178/R1TXD0",
	"GPIO179/R1TXD1", "GPIO180/R1TXEN", "GPIO181/R1RXD0", "GPIO182/R1RXD1",
	"GPIO183/SPI3CK", "GPO184/SPI3D0/STRAP9", "GPO185/SPI3D1/STRAP10",
	"GPIO186/nSPI3CS0", "GPIO187/nSPI3CS1",	"GPIO188/SPI3D2/nSPI3CS2",
	"GPIO189/SPI3D3/nSPI3CS3", "GPIO190/nPRD_SMI", "GPIO191", "GPIO192", "GPIO193/R1CRSDV",
	"GPIO194/SMB0BSCL", "GPIO195/SMB0BSDA", "GPIO196/SMB0CSCL", "GPIO197/SMB0DEN",
	"GPIO198/SMB0DSDA", "GPIO199/SMB0DSCL", "GPIO200/R2CK", "GPIO201/R1CK",
	"GPIO202/SMB0CSDA", "GPIO203/FANIN16", "GPIO204/DDC2SCL", "GPIO205/DDC2SDA",
	"GPIO206/HSYNC2", "GPIO207/VSYNC2", "GPIO208/RG2TXC/DVCK", "GPIO209/RG2TXCTL/DDRV4",
	"GPIO210/RG2RXD0/DDRV5", "GPIO211/RG2RXD1/DDRV6", "GPIO212/RG2RXD2/DDRV7",
	"GPIO213/RG2RXD3/DDRV8", "GPIO214/RG2RXC/DDRV9", "GPIO215/RG2RXCTL/DDRV10",
	"GPIO216/RG2MDC/DDRV11", "GPIO217/RG2MDIO/DVHSYNC", "GPIO218/nWDO1",
	"GPIO219/nWDO2", "GPIO220/SMB12SCL", "GPIO221/SMB12SDA", "GPIO222/SMB13SCL",
	"GPIO223/SMB13SDA", "GPIO224/SPIXCK", "GPO225/SPIXD0/STRAP12", "GPO226/SPIXD1/STRAP13",
	"GPIO227/nSPIXCS0", "GPIO228/nSPIXCS1",	"GPO229/SPIXD2/STRAP3", "GPIO230/SPIXD3",
	"GPIO231/nCLKREQ", "GPI255/DACOSEL"

Optional Properties:
 bias-disable, bias-pull-down, bias-pull-up, input-enable,
 input-disable, output-high, output-low, drive-push-pull,
 drive-open-drain, input-debounce, slew-rate, drive-strength

 slew-rate valid arguments are:
				<0> - slow
				<1> - fast
 drive-strength valid arguments are:
				<2> - 2mA
				<4> - 4mA
				<8> - 8mA
				<12> - 12mA
				<16> - 16mA
				<24> - 24mA

For example, pinctrl might have pinmux subnodes like the following:

	gpio0_iox1d1_pin: gpio0-iox1d1-pin {
		pins = "GPIO0/IOX1DI";
		output-high;
	};
	gpio0_iox1ck_pin: gpio0-iox1ck-pin {
		pins = "GPIO2/IOX1CK";
		output_high;
	};

=== Pin Group Subnode ===

Required pin group subnode-properties:
- groups : A string containing the name of the group to mux.
- function: A string containing the name of the function to mux to the
  group.

The following are the list of the available groups and functions :
	smb0, smb0b, smb0c, smb0d, smb0den, smb1, smb1b, smb1c, smb1d,
	smb2, smb2b, smb2c, smb2d, smb3, smb3b, smb3c, smb3d, smb4, smb4b,
	smb4c, smb4d, smb4den, smb5, smb5b, smb5c, smb5d, ga20kbc, smb6,
	smb7, smb8, smb9, smb10, smb11, smb12, smb13, smb14, smb15, fanin0,
	fanin1, fanin2, fanin3, fanin4, fanin5, fanin6, fanin7, fanin8,
	fanin9, fanin10, fanin11 fanin12 fanin13, fanin14, fanin15, faninx,
	pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, rg1, rg1mdio, rg2,
	rg2mdio, ddr, uart1, uart2, bmcuart0a, bmcuart0b, bmcuart1, iox1,
	iox2, ioxh, gspi, mmc, mmcwp, mmccd, mmcrst, mmc8, r1, r1err, r1md,
	r2, r2err, r2md, sd1, sd1pwr, wdog1, wdog2, scipme, sci, serirq,
	jtag2, spix, spixcs1, pspi1, pspi2, ddc, clkreq, clkout, spi3, spi3cs1,
	spi3quad, spi3cs2, spi3cs3, spi0cs1, lpc, lpcclk, espi, lkgpo0, lkgpo1,
	lkgpo2, nprd_smi

For example, pinctrl might have group subnodes like the following:
	r1err_pins: r1err-pins {
		groups = "r1err";
		function = "r1err";
	};
	r1md_pins: r1md-pins {
		groups = "r1md";
		function = "r1md";
	};
	r1_pins: r1-pins {
		groups = "r1";
		function = "r1";
	};

Examples
========
pinctrl: pinctrl@f0800000 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "nuvoton,npcm750-pinctrl";
	ranges = <0 0xf0010000 0x8000>;

	gpio0: gpio@f0010000 {
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x0 0x80>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		gpio-ranges = <&pinctrl 0 0 32>;
	};

	....

	gpio7: gpio@f0017000 {
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x7000 0x80>;
		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
		gpio-ranges = <&pinctrl 0 224 32>;
	};

	gpio0_iox1d1_pin: gpio0-iox1d1-pin {
		pins = "GPIO0/IOX1DI";
		output-high;
	};

	iox1_pins: iox1-pins {
		groups = "iox1";
		function = "iox1";
	};
	iox2_pins: iox2-pins {
		groups = "iox2";
		function = "iox2";
	};

	....

	clkreq_pins: clkreq-pins {
		groups = "clkreq";
		function = "clkreq";
	};
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Nuvoton WPCM450 pin control and GPIO

maintainers:
  - Jonathan Neuschäfer <j.neuschaefer@gmx.net>

properties:
  compatible:
    const: nuvoton,wpcm450-pinctrl

  reg:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

patternProperties:
  # There are three kinds of subnodes:
  # 1. a GPIO controller node for each GPIO bank
  # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2)
  # 3. a pinconf node configures properties of a single pin

  "^gpio@[0-7]$":
    type: object
    additionalProperties: false

    description:
      Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18
      GPIOs. Some GPIOs support interrupts.

    properties:
      reg:
        minimum: 0
        maximum: 7

      gpio-controller: true

      "#gpio-cells":
        const: 2

      interrupt-controller: true

      "#interrupt-cells":
        const: 2

      interrupts:
        maxItems: 3
        description:
          The interrupts associated with this GPIO bank

    required:
      - reg
      - gpio-controller
      - '#gpio-cells'

  "^mux-":
    $ref: pinmux-node.yaml#

    properties:
      groups:
        description:
          One or more groups of pins to mux to a certain function
        items:
          enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
                  hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo,
                  clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0,
                  fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11,
                  fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
                  pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ]
      function:
        description:
          The function that a group of pins is muxed to
        enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
                hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0,
                dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc,
                gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4,
                fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15,
                pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1,
                hg2, hg3, hg4, hg5, hg6, hg7, gpio ]

    dependencies:
      groups: [ function ]
      function: [ groups ]

    additionalProperties: false

  "^cfg-":
    $ref: pincfg-node.yaml#

    properties:
      pins:
        description:
          A list of pins to configure in certain ways, such as enabling
          debouncing
        items:
          pattern: "^gpio1?[0-9]{1,2}$"

      input-debounce: true

    additionalProperties: false

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>
    pinctrl: pinctrl@b8003000 {
      compatible = "nuvoton,wpcm450-pinctrl";
      reg = <0xb8003000 0x1000>;
      #address-cells = <1>;
      #size-cells = <0>;

      gpio0: gpio@0 {
        reg = <0>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
                     <3 IRQ_TYPE_LEVEL_HIGH>,
                     <4 IRQ_TYPE_LEVEL_HIGH>;
      };

      mux-rmii2 {
        groups = "rmii2";
        function = "rmii2";
      };

      pinmux_uid: mux-uid {
        groups = "gspi", "sspi";
        function = "gpio";
      };

      pinctrl_uid: cfg-uid {
        pins = "gpio14";
        input-debounce = <1>;
      };
    };

    gpio-keys {
      compatible = "gpio-keys";
      pinctrl-names = "default";
      pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;

      button-uid {
        label = "UID";
        linux,code = <102>;
        gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Pinmux Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jonathan Hunter <jonathanh@nvidia.com>

description: |
  Please refer to pinctrl-bindings.txt in this directory for details of the
  common pinctrl bindings used by client devices, including the meaning of
  the phrase "pin configuration node".

  Tegra's pin configuration nodes act as a container for an arbitrary number
  of subnodes. Each of these subnodes represents some desired configuration
  for a pin, a group, or a list of pins or groups. This configuration can
  include the mux function to select on those pin(s)/ group(s), and various
  pin configuration parameters, such as pull-up, tristate, drive strength,
  etc.

  The name of each subnode is not important; all subnodes should be
  enumerated and processed purely based on their content.

  Each subnode only affects those parameters that are explicitly listed. In
  other words, a subnode that lists a mux function but no pin configuration
  parameters implies no information about any pin configuration parameters.

  Similarly, a pin subnode that describes a pullup parameter implies no
  information about e.g.  the mux function or tristate parameter. For this
  reason, even seemingly boolean values are actually tristates in this
  binding: unspecified, off, or on. Unspecified is represented as an absent
  property, and off/on are represented as integer values 0 and 1.

  Note that many of these properties are only valid for certain specific pins
  or groups. See the Tegra TRM and various pinmux spreadsheets for complete
  details regarding which groups support which functionality. The Linux
  pinctrl driver may also be a useful reference, since it consolidates,
  disambiguates, and corrects data from all those sources.

properties:
  nvidia,pins:
    $ref: /schemas/types.yaml#/definitions/string-array
    description: An array of strings. Each string contains the name of a pin
      or group.  Valid values for these names are listed below.

  nvidia,function:
    $ref: /schemas/types.yaml#/definitions/string
    description: A string containing the name of the function to mux to the
      pin or group. Valid values for function names are listed below. See the
      Tegra TRM to determine which are valid for each pin or group.

  nvidia,pull:
    description: Pull-down/up setting to apply to the pin.
    $ref: /schemas/types.yaml#/definitions/uint32
    oneOf:
      - description: none
        const: 0
      - description: down
        const: 1
      - description: up
        const: 2

  nvidia,tristate:
    description: Tristate setting to apply to the pin.
    $ref: /schemas/types.yaml#/definitions/uint32
    oneOf:
      - description: drive
        const: 0
      - description: tristate
        const: 1

  nvidia,schmitt:
    description: Enable Schmitt trigger on the input.
    $ref: /schemas/types.yaml#/definitions/uint32
    oneOf:
      - description: disable Schmitt trigger on the input
        const: 0
      - description: enable Schmitt trigger on the input
        const: 1

  nvidia,pull-down-strength:
    description: Controls drive strength. 0 is weakest. The range of valid
      values depends on the pingroup. See "CAL_DRVDN" in the Tegra TRM.
    $ref: /schemas/types.yaml#/definitions/uint32

  nvidia,pull-up-strength:
    description: Controls drive strength. 0 is weakest. The range of valid
      values depends on the pingroup. See "CAL_DRVUP" in the Tegra TRM.
    $ref: /schemas/types.yaml#/definitions/uint32

  nvidia,high-speed-mode:
    description: Enable high speed mode the pins.
    $ref: /schemas/types.yaml#/definitions/uint32
    oneOf:
      - description: normal speed mode
        const: 0
      - description: high speed mode
        const: 1

  nvidia,low-power-mode:
    description: Controls the drive power or current. Valid values are from 0
      through 3, where 0 specifies the least power and 3 specifies the most
      power. See "Low Power Mode" or "LPMD1" and "LPMD0" in the Tegra TRM.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 0, 1, 2, 3 ]

  nvidia,enable-input:
    description: Enable the pin's input path.
    $ref: /schemas/types.yaml#/definitions/uint32
    oneOf:
      - description: disable input (i.e. output only)
        const: 0
      - description: enable input
        const: 1

  nvidia,open-drain:
    description: Open-drain configuration for the pin.
    $ref: /schemas/types.yaml#/definitions/uint32
    oneOf:
      - description: disable open-drain
        const: 0
      - description: enable open-drain
        const: 1

  nvidia,lock:
    description: Lock the pin configuration against further changes until
      reset.
    $ref: /schemas/types.yaml#/definitions/uint32
    oneOf:
      - description: disable pin configuration lock
        const: 0
      - description: enable pin configuration lock
        const: 1

  nvidia,io-reset:
    description: reset the I/O path
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 0, 1 ]

  nvidia,rcv-sel:
    description: select VIL/VIH receivers
    $ref: /schemas/types.yaml#/definitions/uint32
    oneOf:
      - description: normal receivers
        const: 0
      - description: high-voltage receivers
        const: 1

  nvidia,drive-type:
    description: Drive type to configure for the pin.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 0, 1, 2, 3 ]

  nvidia,io-hv:
    description: Select high-voltage receivers.
    $ref: /schemas/types.yaml#/definitions/uint32
    oneOf:
      - description: Use normal receivers.
        const: 0
      - description: Use high-voltage receivers.
        const: 1

  nvidia,slew-rate-rising:
    description: Controls rising signal slew rate. 0 is fastest. The range of
      valid values depends on the pingroup. See "DRVDN_SLWR" in the Tegra TRM.
    $ref: /schemas/types.yaml#/definitions/uint32

  nvidia,slew-rate-falling:
    description: Controls falling signal slew rate. 0 is fastest. The range of
      valid values depends on the pingroup. See "DRVUP_SLWF" in the Tegra TRM.
    $ref: /schemas/types.yaml#/definitions/uint32

additionalProperties: true
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra114 pinmux Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    const: nvidia,tegra114-pinmux

  reg:
    items:
      - description: pad control registers
      - description: mux registers

patternProperties:
  "^pinmux(-[a-z0-9-_]+)?$":
    type: object
    properties:
      phandle: true

    # pin groups
    additionalProperties:
      $ref: nvidia,tegra-pinmux-common.yaml
      additionalProperties: false
      properties:
        nvidia,pins:
          items:
            enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3,
                    ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
                    ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1,
                    ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1,
                    dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
                    sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5,
                    sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5,
                    clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5,
                    uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
                    uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7,
                    uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4,
                    pu5, pu6, gen1_i2c_sda_pc5, gen1_i2c_scl_pc4, dap4_fs_pp4,
                    dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0,
                    clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,
                    gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2,
                    gmi_cs2_n_pk3, gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3,
                    gmi_cs7_n_pi6, gmi_ad0_pg0, gmi_ad1_pg1, gmi_ad2_pg2,
                    gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, gmi_ad6_pg6,
                    gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
                    gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6,
                    gmi_ad15_ph7, gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1,
                    gmi_a19_pk7, gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_p_pj3,
                    gmi_rst_n_pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
                    sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
                    sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3,
                    sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
                    sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0,
                    cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
                    pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0,
                    kb_row1_pr1, kb_row2_pr2, kb_row3_pr3, kb_row4_pr4,
                    kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, kb_row8_ps0,
                    kb_row9_ps1, kb_row10_ps2, kb_col0_pq0, kb_col1_pq1,
                    kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
                    kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5,
                    core_pwr_req, cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0,
                    dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, clk1_req_pee2,
                    clk1_out_pw4, spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2,
                    dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
                    gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
                    gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6,
                    gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7,
                    sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
                    sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3,
                    sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3,
                    usb_vbus_en0_pn4, usb_vbus_en1_pn5, sdmmc3_clk_lb_in_pee5,
                    sdmmc3_clk_lb_out_pee4, reset_out_n,
                    # drive groups
                    drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
                    drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1,
                    drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3,
                    drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
                    drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf,
                    drive_gmg, drive_gmh, drive_owr, drive_uda ]

        nvidia,function:
          enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3,
                  displaya, displaya_alt, displayb, dtv, emc_dll, extperiph1,
                  extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2,
                  i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc,
                  nand, nand_alt, owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron,
                  reset_out_n, rsvd1, rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2,
                  sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5,
                  spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi, usb,
                  vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3 ]

        nvidia,pull: true
        nvidia,tristate: true
        nvidia,schmitt: true
        nvidia,pull-down-strength: true
        nvidia,pull-up-strength: true
        nvidia,high-speed-mode: true
        nvidia,low-power-mode: true
        nvidia,enable-input: true
        nvidia,open-drain: true
        nvidia,lock: true
        nvidia,io-reset: true
        nvidia,rcv-sel: true
        nvidia,drive-type: true
        nvidia,slew-rate-rising: true
        nvidia,slew-rate-falling: true

      required:
        - nvidia,pins

additionalProperties: false

required:
  - compatible
  - reg

examples:
  - |
    pinmux@70000868 {
        compatible = "nvidia,tegra114-pinmux";
        reg = <0x70000868 0x148>, /* Pad control registers */
              <0x70003000 0x40c>; /* PinMux registers */

        pinmux {
            sdmmc4_clk_pcc4 {
                nvidia,pins = "sdmmc4_clk_pcc4";
                nvidia,function = "sdmmc4";
                nvidia,pull = <0>;
                nvidia,tristate = <0>;
            };

            sdmmc4_dat0_paa0 {
                nvidia,pins = "sdmmc4_dat0_paa0",
                              "sdmmc4_dat1_paa1",
                              "sdmmc4_dat2_paa2",
                              "sdmmc4_dat3_paa3",
                              "sdmmc4_dat4_paa4",
                              "sdmmc4_dat5_paa5",
                              "sdmmc4_dat6_paa6",
                              "sdmmc4_dat7_paa7";
                nvidia,function = "sdmmc4";
                nvidia,pull = <2>;
                nvidia,tristate = <0>;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra124 Pinmux Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: The Tegra124 pinctrl binding is very similar to the Tegra20 and
  Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and
  nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a
  baseline, and only documents the differences between the two bindings.

properties:
  compatible:
    oneOf:
      - const: nvidia,tegra124-pinmux
      - items:
          - const: nvidia,tegra132-pinmux
          - const: nvidia,tegra124-pinmux

  reg:
    items:
      - description: driver strength and pad control registers
      - description: pinmux registers
      - description: MIPI_PAD_CTRL registers

patternProperties:
  "^pinmux(-[a-z0-9-_]+)?$":
    type: object
    properties:
      phandle: true

    # pin groups
    additionalProperties:
      $ref: nvidia,tegra-pinmux-common.yaml
      additionalProperties: false
      properties:
        nvidia,pins:
          $ref: /schemas/types.yaml#/definitions/string-array
          items:
            enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3,
                    ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
                    ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1,
                    ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1,
                    dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
                    sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5,
                    sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5,
                    clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5,
                    uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
                    uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7,
                    uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4,
                    pu5, pu6, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, dap4_fs_pp4,
                    dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0,
                    clk3_req_pee1, pc7, pi5, pi7, pk0, pk1, pj0, pj2, pk3, pk4,
                    pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6, pg7, ph0,
                    ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0,
                    pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
                    sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
                    sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3,
                    sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
                    sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0,
                    cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
                    pbb7, pcc2, jtag_rtck, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7,
                    kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, kb_row3_pr3,
                    kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
                    kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3,
                    kb_row12_ps4, kb_row13_ps5, kb_row14_ps6, kb_row15_ps7,
                    kb_col0_pq0, kb_col1_pq1, kb_col2_pq2, kb_col3_pq3,
                    kb_col4_pq4, kb_col5_pq5, kb_col6_pq6, kb_col7_pq7,
                    clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n,
                    clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
                    dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4,
                    spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4,
                    dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
                    gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
                    gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6,
                    gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7,
                    sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
                    sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
                    pex_wake_n_pdd3, pex_l1_rst_n_pdd5, pex_l1_clkreq_n_pdd6,
                    hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2,
                    gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4,
                    usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4,
                    sdmmc3_clk_lb_in_pee5, gmi_clk_lb, reset_out_n,
                    kb_row16_pt0, kb_row17_pt1, usb_vbus_en2_pff1, pff2,
                    dp_hpd_pff0,
                    # drive groups
                    drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
                    drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1,
                    drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3,
                    drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
                    drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf,
                    drive_gmg, drive_gmh, drive_owr, drive_uda, drive_gpv,
                    drive_dev3, drive_cec, drive_usb_vbus_en, drive_ao3,
                    drive_ao0, drive_hv0, drive_sdio4, drive_ao4,
                    # MIPI pad control groups
                    mipi_pad_ctrl_dsi_b ]

        nvidia,function:
          enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3,
                  displaya, displaya_alt, displayb, dtv, extperiph1,
                  extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2,
                  i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc,
                  owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1,
                  rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc,
                  spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
                  uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5,
                  vgp6, vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla,
                  pe0, pe, pe1, dp, rtck, sys, clk, tmds, csi, dsi_b ]

        nvidia,pull: true
        nvidia,tristate: true
        nvidia,schmitt: true
        nvidia,pull-down-strength: true
        nvidia,pull-up-strength: true
        nvidia,high-speed-mode: true
        nvidia,low-power-mode: true
        nvidia,enable-input: true
        nvidia,open-drain: true
        nvidia,lock: true
        nvidia,io-reset: true
        nvidia,rcv-sel: true
        nvidia,drive-type: true
        nvidia,slew-rate-rising: true
        nvidia,slew-rate-falling: true

      required:
        - nvidia,pins

additionalProperties: false

required:
  - compatible
  - reg

examples:
  - |
    #include <dt-bindings/clock/tegra124-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/pinctrl/pinctrl-tegra.h>

    pinmux@70000868 {
        compatible = "nvidia,tegra124-pinmux";
        reg = <0x70000868 0x164>, /* Pad control registers */
              <0x70003000 0x434>, /* Mux registers */
              <0x70000820 0x8>;   /* MIPI pad control */

        sdmmc4_default: pinmux {
            sdmmc4_clk_pcc4 {
                nvidia,pins = "sdmmc4_clk_pcc4";
                nvidia,function = "sdmmc4";
                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                nvidia,tristate = <TEGRA_PIN_DISABLE>;
            };

            sdmmc4_dat0_paa0 {
                nvidia,pins = "sdmmc4_dat0_paa0",
                              "sdmmc4_dat1_paa1",
                              "sdmmc4_dat2_paa2",
                              "sdmmc4_dat3_paa3",
                              "sdmmc4_dat4_paa4",
                              "sdmmc4_dat5_paa5",
                              "sdmmc4_dat6_paa6",
                              "sdmmc4_dat7_paa7";
                nvidia,function = "sdmmc4";
                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                nvidia,tristate = <TEGRA_PIN_DISABLE>;
            };
        };
    };
...


code:
Device tree binding for NVIDIA Tegra XUSB pad controller
========================================================

NOTE: It turns out that this binding isn't an accurate description of the XUSB
pad controller. While the description is good enough for the functional subset
required for PCIe and SATA, it lacks the flexibility to represent the features
needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
The binding described in this file is deprecated and should not be used.

The Tegra XUSB pad controller manages a set of lanes, each of which can be
assigned to one out of a set of different pads. Some of these pads have an
associated PHY that must be powered up before the pad can be used.

This document defines the device-specific binding for the XUSB pad controller.

Refer to pinctrl-bindings.txt in this directory for generic information about
pin controller device tree bindings and ../phy/phy-bindings.txt for details on
how to describe and reference PHYs in device trees.

Required properties:
--------------------
- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
  Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
  "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
- reg: Physical base address and length of the controller's registers.
- resets: Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
  - padctl
- #phy-cells: Should be 1. The specifier is the index of the PHY to reference.
  See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values.

Lane muxing:
------------

Child nodes contain the pinmux configurations following the conventions from
the pinctrl-bindings.txt document. Typically a single, static configuration is
given and applied at boot time.

Each subnode describes groups of lanes along with parameters and pads that
they should be assigned to. The name of these subnodes is not important. All
subnodes should be parsed solely based on their content.

Each subnode only applies the parameters that are explicitly listed. In other
words, if a subnode that lists a function but no pin configuration parameters
implies no information about any pin configuration parameters. Similarly, a
subnode that describes only an IDDQ parameter implies no information about
what function the pins are assigned to. For this reason even seemingly boolean
values are actually tristates in this binding: unspecified, off or on.
Unspecified is represented as an absent property, and off/on are represented
as integer values 0 and 1.

Required properties:
- nvidia,lanes: An array of strings. Each string is the name of a lane.

Optional properties:
- nvidia,function: A string that is the name of the function (pad) that the
  pin or group should be assigned to. Valid values for function names are
  listed below.
- nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)

Note that not all of these properties are valid for all lanes. Lanes can be
divided into three groups:

  - otg-0, otg-1, otg-2:

    Valid functions for this group are: "snps", "xusb", "uart", "rsvd".

    The nvidia,iddq property does not apply to this group.

  - ulpi-0, hsic-0, hsic-1:

    Valid functions for this group are: "snps", "xusb".

    The nvidia,iddq property does not apply to this group.

  - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0:

    Valid functions for this group are: "pcie", "usb3", "sata", "rsvd".

Example:
========

SoC file extract:
-----------------

	padctl@7009f000 {
		compatible = "nvidia,tegra124-xusb-padctl";
		reg = <0x0 0x7009f000 0x0 0x1000>;
		resets = <&tegra_car 142>;
		reset-names = "padctl";

		#phy-cells = <1>;
	};

Board file extract:
-------------------

	pcie-controller@1003000 {
		...

		phys = <&padctl 0>;
		phy-names = "pcie";

		...
	};

	...

	padctl: padctl@7009f000 {
		pinctrl-0 = <&padctl_default>;
		pinctrl-names = "default";

		padctl_default: pinmux {
			usb3 {
				nvidia,lanes = "pcie-0", "pcie-1";
				nvidia,function = "usb3";
				nvidia,iddq = <0>;
			};

			pcie {
				nvidia,lanes = "pcie-2", "pcie-3",
					       "pcie-4";
				nvidia,function = "pcie";
				nvidia,iddq = <0>;
			};

			sata {
				nvidia,lanes = "sata-0";
				nvidia,function = "sata";
				nvidia,iddq = <0>;
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra194-pinmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra194 Pinmux Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    enum:
      - nvidia,tegra194-pinmux
      - nvidia,tegra194-pinmux-aon

  reg:
    items:
      - description: pinmux registers

patternProperties:
  "^pinmux(-[a-z0-9-_]+)?$":
    type: object
    properties:
      phandle: true

    # pin groups
    additionalProperties:
      $ref: nvidia,tegra-pinmux-common.yaml
      unevaluatedProperties: false
      properties:
        nvidia,function:
          enum: [ aud, can0, can1, ccla, dca, dcb, dgpu, directdc, directdc1,
                  displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp,
                  dspk0, dspk1, eqos, extperiph1, extperiph2, extperiph3,
                  extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c8,
                  i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, igpu, iqc1, iqc2, mipi,
                  nv, pe0, pe1, pe2, pe3, pe4, pe5, qspi, qspi0, qspi1, rsvd0,
                  rsvd1, rsvd2, rsvd3, sata, sce, sdmmc1, sdmmc3, sdmmc4, slvs,
                  soc, spdif, spi1, spi2, spi3, touch, uarta, uartb, uartc,
                  uartd, uarte, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5,
                  vgp6, wdt ]

        nvidia,pull: true
        nvidia,tristate: true
        nvidia,schmitt: true
        nvidia,enable-input: true
        nvidia,open-drain: true
        nvidia,lock: true
        nvidia,drive-type: true
        nvidia,io-hv: true

      required:
        - nvidia,pins

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          const: nvidia,tegra194-pinmux
    then:
      patternProperties:
        "^pinmux(-[a-z0-9-_]+)?$":
          type: object
          additionalProperties:
            properties:
              nvidia,pins:
                description: An array of strings. Each string contains the name
                  of a pin or group. Valid values for these names are listed
                  below.

                  Note that the pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 pins
                  are part of PCIE C5 power partition. Client devices must
                  enable this partition before accessing the configuration for
                  these pins.
                items:
                  enum: [ dap6_sclk_pa0, dap6_dout_pa1, dap6_din_pa2,
                          dap6_fs_pa3, dap4_sclk_pa4, dap4_dout_pa5,
                          dap4_din_pa6, dap4_fs_pa7, cpu_pwr_req_0_pb0,
                          cpu_pwr_req_1_pb1, qspi0_sck_pc0, qspi0_cs_n_pc1,
                          qspi0_io0_pc2, qspi0_io1_pc3, qspi0_io2_pc4,
                          qspi0_io3_pc5, qspi1_sck_pc6, qspi1_cs_n_pc7,
                          qspi1_io0_pd0, qspi1_io1_pd1, qspi1_io2_pd2,
                          qspi1_io3_pd3, eqos_txc_pe0, eqos_td0_pe1,
                          eqos_td1_pe2, eqos_td2_pe3, eqos_td3_pe4,
                          eqos_tx_ctl_pe5, eqos_rd0_pe6, eqos_rd1_pe7,
                          eqos_rd2_pf0, eqos_rd3_pf1, eqos_rx_ctl_pf2,
                          eqos_rxc_pf3, eqos_sma_mdio_pf4, eqos_sma_mdc_pf5,
                          soc_gpio00_pg0, soc_gpio01_pg1, soc_gpio02_pg2,
                          soc_gpio03_pg3, soc_gpio08_pg4, soc_gpio09_pg5,
                          soc_gpio10_pg6, soc_gpio11_pg7, soc_gpio12_ph0,
                          soc_gpio13_ph1, soc_gpio14_ph2, uart4_tx_ph3,
                          uart4_rx_ph4, uart4_rts_ph5, uart4_cts_ph6,
                          dap2_sclk_ph7, dap2_dout_pi0, dap2_din_pi1,
                          dap2_fs_pi2, gen1_i2c_scl_pi3, gen1_i2c_sda_pi4,
                          sdmmc1_clk_pj0, sdmmc1_cmd_pj1, sdmmc1_dat0_pj2,
                          sdmmc1_dat1_pj3, sdmmc1_dat2_pj4, sdmmc1_dat3_pj5,
                          pex_l0_clkreq_n_pk0, pex_l0_rst_n_pk1,
                          pex_l1_clkreq_n_pk2, pex_l1_rst_n_pk3,
                          pex_l2_clkreq_n_pk4, pex_l2_rst_n_pk5,
                          pex_l3_clkreq_n_pk6, pex_l3_rst_n_pk7,
                          pex_l4_clkreq_n_pl0, pex_l4_rst_n_pl1,
                          pex_wake_n_pl2, sata_dev_slp_pl3, dp_aux_ch0_hpd_pm0,
                          dp_aux_ch1_hpd_pm1, dp_aux_ch2_hpd_pm2,
                          dp_aux_ch3_hpd_pm3, hdmi_cec_pm4, soc_gpio50_pm5,
                          soc_gpio51_pm6, soc_gpio52_pm7, soc_gpio53_pn0,
                          soc_gpio54_pn1, soc_gpio55_pn2, sdmmc3_clk_po0,
                          sdmmc3_cmd_po1, sdmmc3_dat0_po2, sdmmc3_dat1_po3,
                          sdmmc3_dat2_po4, sdmmc3_dat3_po5, extperiph1_clk_pp0,
                          extperiph2_clk_pp1, cam_i2c_scl_pp2, cam_i2c_sda_pp3,
                          soc_gpio04_pp4, soc_gpio05_pp5, soc_gpio06_pp6,
                          soc_gpio07_pp7, soc_gpio20_pq0, soc_gpio21_pq1,
                          soc_gpio22_pq2, soc_gpio23_pq3, soc_gpio40_pq4,
                          soc_gpio41_pq5, soc_gpio42_pq6, soc_gpio43_pq7,
                          soc_gpio44_pr0, soc_gpio45_pr1, uart1_tx_pr2,
                          uart1_rx_pr3, uart1_rts_pr4, uart1_cts_pr5,
                          dap1_sclk_ps0, dap1_dout_ps1, dap1_din_ps2,
                          dap1_fs_ps3, aud_mclk_ps4, soc_gpio30_ps5,
                          soc_gpio31_ps6, soc_gpio32_ps7, soc_gpio33_pt0,
                          dap3_sclk_pt1, dap3_dout_pt2, dap3_din_pt3,
                          dap3_fs_pt4, dap5_sclk_pt5, dap5_dout_pt6,
                          dap5_din_pt7, dap5_fs_pu0, directdc1_clk_pv0,
                          directdc1_in_pv1, directdc1_out0_pv2,
                          directdc1_out1_pv3, directdc1_out2_pv4,
                          directdc1_out3_pv5, directdc1_out4_pv6,
                          directdc1_out5_pv7, directdc1_out6_pw0,
                          directdc1_out7_pw1, gpu_pwr_req_px0, cv_pwr_req_px1,
                          gp_pwm2_px2, gp_pwm3_px3, uart2_tx_px4, uart2_rx_px5,
                          uart2_rts_px6, uart2_cts_px7, spi3_sck_py0,
                          spi3_miso_py1, spi3_mosi_py2, spi3_cs0_py3,
                          spi3_cs1_py4, uart5_tx_py5, uart5_rx_py6,
                          uart5_rts_py7, uart5_cts_pz0, usb_vbus_en0_pz1,
                          usb_vbus_en1_pz2, spi1_sck_pz3, spi1_miso_pz4,
                          spi1_mosi_pz5, spi1_cs0_pz6, spi1_cs1_pz7,
                          ufs0_ref_clk_pff0, ufs0_rst_pff1,
                          pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1,
                          directdc_comp, sdmmc4_clk, sdmmc4_cmd, sdmmc4_dqs,
                          sdmmc4_dat7, sdmmc4_dat6, sdmmc4_dat5, sdmmc4_dat4,
                          sdmmc4_dat3, sdmmc4_dat2, sdmmc4_dat1, sdmmc4_dat0,
                          sdmmc1_comp, sdmmc1_hv_trim, sdmmc3_comp,
                          sdmmc3_hv_trim, eqos_comp, qspi_comp,
                          # drive groups
                          drive_soc_gpio33_pt0, drive_soc_gpio32_ps7,
                          drive_soc_gpio31_ps6, drive_soc_gpio30_ps5,
                          drive_aud_mclk_ps4, drive_dap1_fs_ps3,
                          drive_dap1_din_ps2, drive_dap1_dout_ps1,
                          drive_dap1_sclk_ps0, drive_dap3_fs_pt4,
                          drive_dap3_din_pt3, drive_dap3_dout_pt2,
                          drive_dap3_sclk_pt1, drive_dap5_fs_pu0,
                          drive_dap5_din_pt7, drive_dap5_dout_pt6,
                          drive_dap5_sclk_pt5, drive_dap6_fs_pa3,
                          drive_dap6_din_pa2, drive_dap6_dout_pa1,
                          drive_dap6_sclk_pa0, drive_dap4_fs_pa7,
                          drive_dap4_din_pa6, drive_dap4_dout_pa5,
                          drive_dap4_sclk_pa4, drive_extperiph2_clk_pp1,
                          drive_extperiph1_clk_pp0, drive_cam_i2c_sda_pp3,
                          drive_cam_i2c_scl_pp2, drive_soc_gpio40_pq4,
                          drive_soc_gpio41_pq5, drive_soc_gpio42_pq6,
                          drive_soc_gpio43_pq7, drive_soc_gpio44_pr0,
                          drive_soc_gpio45_pr1, drive_soc_gpio20_pq0,
                          drive_soc_gpio21_pq1, drive_soc_gpio22_pq2,
                          drive_soc_gpio23_pq3, drive_soc_gpio04_pp4,
                          drive_soc_gpio05_pp5, drive_soc_gpio06_pp6,
                          drive_soc_gpio07_pp7, drive_uart1_cts_pr5,
                          drive_uart1_rts_pr4, drive_uart1_rx_pr3,
                          drive_uart1_tx_pr2, drive_dap2_din_pi1,
                          drive_dap2_dout_pi0, drive_dap2_fs_pi2,
                          drive_dap2_sclk_ph7, drive_uart4_cts_ph6,
                          drive_uart4_rts_ph5, drive_uart4_rx_ph4,
                          drive_uart4_tx_ph3, drive_soc_gpio03_pg3,
                          drive_soc_gpio02_pg2, drive_soc_gpio01_pg1,
                          drive_soc_gpio00_pg0, drive_gen1_i2c_scl_pi3,
                          drive_gen1_i2c_sda_pi4, drive_soc_gpio08_pg4,
                          drive_soc_gpio09_pg5, drive_soc_gpio10_pg6,
                          drive_soc_gpio11_pg7, drive_soc_gpio12_ph0,
                          drive_soc_gpio13_ph1, drive_soc_gpio14_ph2,
                          drive_soc_gpio50_pm5, drive_soc_gpio51_pm6,
                          drive_soc_gpio52_pm7, drive_soc_gpio53_pn0,
                          drive_soc_gpio54_pn1, drive_soc_gpio55_pn2,
                          drive_dp_aux_ch0_hpd_pm0, drive_dp_aux_ch1_hpd_pm1,
                          drive_dp_aux_ch2_hpd_pm2, drive_dp_aux_ch3_hpd_pm3,
                          drive_hdmi_cec_pm4, drive_pex_l2_clkreq_n_pk4,
                          drive_pex_wake_n_pl2, drive_pex_l1_clkreq_n_pk2,
                          drive_pex_l1_rst_n_pk3, drive_pex_l0_clkreq_n_pk0,
                          drive_pex_l0_rst_n_pk1, drive_pex_l2_rst_n_pk5,
                          drive_pex_l3_clkreq_n_pk6, drive_pex_l3_rst_n_pk7,
                          drive_pex_l4_clkreq_n_pl0, drive_pex_l4_rst_n_pl1,
                          drive_sata_dev_slp_pl3, drive_pex_l5_clkreq_n_pgg0,
                          drive_pex_l5_rst_n_pgg1, drive_cpu_pwr_req_1_pb1,
                          drive_cpu_pwr_req_0_pb0, drive_sdmmc1_clk_pj0,
                          drive_sdmmc1_cmd_pj1, drive_sdmmc1_dat3_pj5,
                          drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3,
                          drive_sdmmc1_dat0_pj2, drive_sdmmc3_dat3_po5,
                          drive_sdmmc3_dat2_po4, drive_sdmmc3_dat1_po3,
                          drive_sdmmc3_dat0_po2, drive_sdmmc3_cmd_po1,
                          drive_sdmmc3_clk_po0, drive_gpu_pwr_req_px0,
                          drive_spi3_miso_py1, drive_spi1_cs0_pz6,
                          drive_spi3_cs0_py3, drive_spi1_miso_pz4,
                          drive_spi3_cs1_py4, drive_gp_pwm3_px3,
                          drive_gp_pwm2_px2, drive_spi1_sck_pz3,
                          drive_spi3_sck_py0, drive_spi1_cs1_pz7,
                          drive_spi1_mosi_pz5, drive_spi3_mosi_py2,
                          drive_cv_pwr_req_px1, drive_uart2_tx_px4,
                          drive_uart2_rx_px5, drive_uart2_rts_px6,
                          drive_uart2_cts_px7, drive_uart5_rx_py6,
                          drive_uart5_tx_py5, drive_uart5_rts_py7,
                          drive_uart5_cts_pz0, drive_usb_vbus_en0_pz1,
                          drive_usb_vbus_en1_pz2, drive_ufs0_rst_pff1,
                          drive_ufs0_ref_clk_pff0 ]

  - if:
      properties:
        compatible:
          const: nvidia,tegra194-pinmux-aon
    then:
      patternProperties:
        "^pinmux(-[a-z0-9-_]+)?$":
          type: object
          additionalProperties:
            properties:
              nvidia,pins:
                items:
                  enum: [ can1_dout_paa0, can1_din_paa1, can0_dout_paa2,
                          can0_din_paa3, can0_stb_paa4, can0_en_paa5,
                          can0_wake_paa6, can0_err_paa7, can1_stb_pbb0,
                          can1_en_pbb1, can1_wake_pbb2, can1_err_pbb3,
                          spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
                          spi2_cs0_pcc3, touch_clk_pcc4, uart3_tx_pcc5,
                          uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0,
                          gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2,
                          safe_state_pee0, vcomp_alert_pee1,
                          ao_retention_n_pee2, batt_oc_pee3, power_on_pee4,
                          pwr_i2c_scl_pee5, pwr_i2c_sda_pee6, sys_reset_n,
                          shutdown_n, pmu_int_n, soc_pwr_req, clk_32k_in,
                          # drive groups
                          drive_shutdown_n, drive_pmu_int_n,
                          drive_safe_state_pee0, drive_vcomp_alert_pee1,
                          drive_soc_pwr_req, drive_batt_oc_pee3,
                          drive_clk_32k_in, drive_power_on_pee4,
                          drive_pwr_i2c_scl_pee5, drive_pwr_i2c_sda_pee6,
                          drive_ao_retention_n_pee2, drive_touch_clk_pcc4,
                          drive_uart3_rx_pcc6, drive_uart3_tx_pcc5,
                          drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1,
                          drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7,
                          drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0,
                          drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
                          drive_can1_dout_paa0, drive_can1_din_paa1,
                          drive_can0_dout_paa2, drive_can0_din_paa3,
                          drive_can0_stb_paa4, drive_can0_en_paa5,
                          drive_can0_wake_paa6, drive_can0_err_paa7,
                          drive_can1_stb_pbb0, drive_can1_en_pbb1,
                          drive_can1_wake_pbb2, drive_can1_err_pbb3 ]

required:
  - compatible
  - reg

examples:
  - |
    #include <dt-bindings/pinctrl/pinctrl-tegra.h>

    pinmux@2430000 {
        compatible = "nvidia,tegra194-pinmux";
        reg = <0x2430000 0x17000>;

        pinctrl-names = "pex_rst";
        pinctrl-0 = <&pex_rst_c5_out_state>;

        pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
            pex_rst {
                nvidia,pins = "pex_l5_rst_n_pgg1";
                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                nvidia,io-hv = <TEGRA_PIN_ENABLE>;
                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra20 Pinmux Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    const: nvidia,tegra20-pinmux

  reg:
    items:
      - description: tri-state registers
      - description: mux register
      - description: pull-up/down registers
      - description: pad control registers

patternProperties:
  "^pinmux(-[a-z0-9-_]+)?$":
    type: object
    properties:
      phandle: true

    # pin groups
    additionalProperties:
      $ref: nvidia,tegra-pinmux-common.yaml
      additionalProperties: false
      properties:
        nvidia,pins:
          items:
            enum: [ ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1,
                    dap2, dap3, dap4, ddc, dta, dtb, dtc, dtd, dte, dtf, gma,
                    gmb, gmc, gmd, gme, gpu, gpu7, gpv, hdint, i2cp, irrx,
                    irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn, ld0, ld1,
                    ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12,
                    ld13, ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2,
                    lhs, lm0, lm1, lpp, lpw0, lpw1, lpw2, lsc0, lsc1, lsck,
                    lsda, lsdi, lspi, lvp0, lvp1, lvs, owc, pmc, pta, rm, sdb,
                    sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi, spdo, spia,
                    spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac,
                    uad, uca, ucb, uda,
                    # tristate groups
                    ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls,
                    lc, ld17_0, ld19_18, ld21_20, ld23_22,
                    # drive groups
                    drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1,
                    drive_cdev2, drive_csus, drive_dap1, drive_dap2,
                    drive_dap3, drive_dap4, drive_dbg, drive_lcd1, drive_lcd2,
                    drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
                    drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2,
                    drive_xm2a, drive_xm2c, drive_xm2d, drive_xm2clk,
                    drive_sdio1, drive_crt, drive_ddc, drive_gma, drive_gmb,
                    drive_gmc, drive_gmd, drive_gme, drive_owr, drive_uda ]

        nvidia,function:
          enum: [ ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4,
                  dap5, displaya, displayb, emc_test0_dll, emc_test1_dll, gmi,
                  gmi_int, hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio,
                  mipi_hs, nand, osc, owr, pcie, plla_out, pllc_out1,
                  pllm_out1, pllp_out2, pllp_out3, pllp_out4, pwm, pwr_intr,
                  pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck, sdio1, sdio2,
                  sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt, spi3,
                  spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
                  vi, vi_sensor_clk, xio ]

        nvidia,pull: true
        nvidia,tristate: true
        nvidia,schmitt: true
        nvidia,pull-down-strength: true
        nvidia,pull-up-strength: true
        nvidia,high-speed-mode: true
        nvidia,low-power-mode: true
        nvidia,slew-rate-rising: true
        nvidia,slew-rate-falling: true

      required:
        - nvidia,pins

additionalProperties: false

required:
  - compatible
  - reg

examples:
  - |
    #include <dt-bindings/clock/tegra20-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pinctrl@70000000 {
        compatible = "nvidia,tegra20-pinmux";
        reg = <0x70000014 0x10>, /* Tri-state registers */
              <0x70000080 0x20>, /* Mux registers */
              <0x700000a0 0x14>, /* Pull-up/down registers */
              <0x70000868 0xa8>; /* Pad control registers */

        pinmux {
            atb {
                nvidia,pins = "atb", "gma", "gme";
                nvidia,function = "sdio4";
                nvidia,pull = <0>;
                nvidia,tristate = <0>;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra210-pinmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra210 Pinmux Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    const: nvidia,tegra210-pinmux

  reg:
    items:
      - description: APB_MISC_GP_*_PADCTRL register (pad control)
      - description: PINMUX_AUX_* registers (pinmux)

patternProperties:
  "^pinmux(-[a-z0-9-_]+)?$":
    type: object
    properties:
      phandle: true

    # pin groups
    additionalProperties:
      $ref: nvidia,tegra-pinmux-common.yaml
      additionalProperties: false
      properties:
        nvidia,pins:
          items:
            enum: [ als_prox_int_px3, ap_ready_pv5, ap_wake_bt_ph3,
                    ap_wake_nfc_ph7, aud_mclk_pbb0, batt_bcl, bt_rst_ph4,
                    bt_wake_ap_ph5, button_home_py1, button_power_on_px5,
                    button_slide_sw_py0, button_vol_down_px7,
                    button_vol_up_px6, cam1_mclk_ps0, cam1_pwdn_ps7,
                    cam1_strobe_pt1, cam2_mclk_ps1, cam2_pwdn_pt0,
                    cam_af_en_ps5, cam_flash_en_ps6, cam_i2c_scl_ps2,
                    cam_i2c_sda_ps3, cam_rst_ps4, clk_32k_in, clk_32k_out_py5,
                    clk_req, core_pwr_req, cpu_pwr_req, dap1_din_pb1,
                    dap1_dout_pb2, dap1_fs_pb0, dap1_sclk_pb3, dap2_din_paa2,
                    dap2_dout_paa3, dap2_fs_paa0, dap2_sclk_paa1, dap4_din_pj5,
                    dap4_dout_pj6, dap4_fs_pj4, dap4_sclk_pj7, dmic1_clk_pe0,
                    dmic1_dat_pe1, dmic2_clk_pe2, dmic2_dat_pe3, dmic3_clk_pe4,
                    dmic3_dat_pe5, dp_hpd0_pcc6, dvfs_clk_pbb2, dvfs_pwm_pbb1,
                    gen1_i2c_scl_pj1, gen1_i2c_sda_pj0, gen2_i2c_scl_pj2,
                    gen2_i2c_sda_pj3, gen3_i2c_scl_pf0, gen3_i2c_sda_pf1,
                    gpio_x1_aud_pbb3, gpio_x3_aud_pbb4, gps_en_pi2,
                    gps_rst_pi3, hdmi_cec_pcc0, hdmi_int_dp_hpd_pcc1,
                    jtag_rtck, lcd_bl_en_pv1, lcd_bl_pwm_pv0, lcd_gpio1_pv3,
                    lcd_gpio2_pv4, lcd_rst_pv2, lcd_te_py2, modem_wake_ap_px0,
                    motion_int_px2, nfc_en_pi0, nfc_int_pi1, pa6, pcc7, pe6,
                    pe7, pex_l0_clkreq_n_pa1, pex_l0_rst_n_pa0,
                    pex_l1_clkreq_n_pa4, pex_l1_rst_n_pa3, pex_wake_n_pa2, ph6,
                    pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
                    pwr_i2c_scl_py3, pwr_i2c_sda_py4, pwr_int_n, pz0, pz1, pz2,
                    pz3, pz4, pz5, qspi_cs_n_pee1, qspi_io0_pee2,
                    qspi_io1_pee3, qspi_io2_pee4, qspi_io3_pee5, qspi_sck_pee0,
                    sata_led_active_pa5, sdmmc1_clk_pm0, sdmmc1_cmd_pm1,
                    sdmmc1_dat0_pm5, sdmmc1_dat1_pm4, sdmmc1_dat2_pm3,
                    sdmmc1_dat3_pm2, sdmmc3_clk_pp0, sdmmc3_cmd_pp1,
                    sdmmc3_dat0_pp5, sdmmc3_dat1_pp4, sdmmc3_dat2_pp3,
                    sdmmc3_dat3_pp2, shutdown, spdif_in_pcc3, spdif_out_pcc2,
                    spi1_cs0_pc3, spi1_cs1_pc4, spi1_miso_pc1, spi1_mosi_pc0,
                    spi1_sck_pc2, spi2_cs0_pb7, spi2_cs1_pdd0, spi2_miso_pb5,
                    spi2_mosi_pb4, spi2_sck_pb6, spi4_cs0_pc6, spi4_miso_pd0,
                    spi4_mosi_pc7, spi4_sck_pc5, temp_alert_px4, touch_clk_pv7,
                    touch_int_px1, touch_rst_pv6, uart1_cts_pu3, uart1_rts_pu2,
                    uart1_rx_pu1, uart1_tx_pu0, uart2_cts_pg3, uart2_rts_pg2,
                    uart2_rx_pg1, uart2_tx_pg0, uart3_cts_pd4, uart3_rts_pd3,
                    uart3_rx_pd2, uart3_tx_pd1, uart4_cts_pi7, uart4_rts_pi6,
                    uart4_rx_pi5, uart4_tx_pi4, usb_vbus_en0_pcc4,
                    usb_vbus_en1_pcc5, wifi_en_ph0, wifi_rst_ph1,
                    wifi_wake_ap_ph2,
                    # drive groups
                    drive_pa6, drive_pcc7, drive_pe6, drive_pe7, drive_ph6,
                    drive_pk0, drive_pk1, drive_pk2, drive_pk3, drive_pk4,
                    drive_pk5, drive_pk6, drive_pk7, drive_pl0, drive_pl1,
                    drive_pz0, drive_pz1, drive_pz2, drive_pz3, drive_pz4,
                    drive_pz5, drive_sdmmc1, drive_sdmmc2, drive_sdmmc3,
                    drive_sdmmc4 ]

        nvidia,function:
          enum: [ aud, bcl, blink, ccla, cec, cldvfs, clk, core, cpu, displaya,
                  displayb, dmic1, dmic2, dmic3, dp, dtv, extperiph3, i2c1,
                  i2c2, i2c3, i2cpmu, i2cvi, i2s1, i2s2, i2s3, i2s4a, i2s4b,
                  i2s5a, i2s5b, iqc0, iqc1, jtag, pe, pe0, pe1, pmi, pwm0,
                  pwm1, pwm2, pwm3, qspi, rsvd0, rsvd1, rsvd2, rsvd3, sata,
                  sdmmc1, sdmmc3, shutdown, soc, sor0, sor1, spdif, spi1, spi2,
                  spi3, spi4, sys, touch, uart, uarta, uartb, uartc, uartd,
                  usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vimclk, vimclk2 ]

        nvidia,pull: true
        nvidia,tristate: true
        nvidia,pull-down-strength: true
        nvidia,pull-up-strength: true
        nvidia,high-speed-mode: true
        nvidia,enable-input: true
        nvidia,open-drain: true
        nvidia,lock: true
        nvidia,drive-type: true
        nvidia,io-hv: true
        nvidia,slew-rate-rising: true
        nvidia,slew-rate-falling: true

      required:
        - nvidia,pins

additionalProperties: false

required:
  - compatible
  - reg

examples:
  - |
    #include <dt-bindings/pinctrl/pinctrl-tegra.h>

    pinmux: pinmux@70000800 {
        compatible = "nvidia,tegra210-pinmux";
        reg = <0x700008d4 0x02a8>, /* Pad control registers */
              <0x70003000 0x1000>; /* Mux registers */

        pinctrl-names = "boot";
        pinctrl-0 = <&state_boot>;

        state_boot: pinmux {
            gen1_i2c_scl_pj1 {
                nvidia,pins = "gen1_i2c_scl_pj1";
                nvidia,function = "i2c1";
                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                nvidia,io-hv = <TEGRA_PIN_ENABLE>;
            };
        };
    };
...