code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,mipi-video-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S5P/Exynos SoC MIPI CSIS/DSIM DPHY

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Marek Szyprowski <m.szyprowski@samsung.com>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>

description: |
  For samsung,s5pv210-mipi-video-phy compatible PHYs the second cell in the
  PHY specifier identifies the PHY and its meaning is as follows::
    0 - MIPI CSIS 0,
    1 - MIPI DSIM 0,
    2 - MIPI CSIS 1,
    3 - MIPI DSIM 1.

  samsung,exynos5420-mipi-video-phy and samsung,exynos5433-mipi-video-phy
  support additional fifth PHY::
    4 - MIPI CSIS 2.

properties:
  compatible:
    enum:
      - samsung,s5pv210-mipi-video-phy
      - samsung,exynos5420-mipi-video-phy
      - samsung,exynos5433-mipi-video-phy

  "#phy-cells":
    const: 1

  syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to PMU system controller interface, valid only for
      samsung,s5pv210-mipi-video-phy and samsung,exynos5420-mipi-video-phy.

  samsung,pmu-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to PMU system controller interface, valid for
      samsung,exynos5433-mipi-video-phy.

  samsung,disp-sysreg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to DISP system controller interface, valid for
      samsung,exynos5433-mipi-video-phy.

  samsung,cam0-sysreg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to CAM0 system controller interface, valid for
      samsung,exynos5433-mipi-video-phy.

  samsung,cam1-sysreg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to CAM1 system controller interface, valid for
      samsung,exynos5433-mipi-video-phy.

required:
  - compatible
  - "#phy-cells"

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,s5pv210-mipi-video-phy
              - samsung,exynos5420-mipi-video-phy
    then:
      properties:
        samsung,pmu-syscon: false
        samsung,disp-sysreg: false
        samsung,cam0-sysreg: false
        samsung,cam1-sysreg: false
      required:
        - syscon
    else:
      properties:
        syscon: false
      required:
        - samsung,pmu-syscon
        - samsung,disp-sysreg
        - samsung,cam0-sysreg
        - samsung,cam1-sysreg

additionalProperties: false

examples:
  - |
    phy {
        compatible = "samsung,exynos5433-mipi-video-phy";
        #phy-cells = <1>;
        samsung,pmu-syscon = <&pmu_system_controller>;
        samsung,cam0-sysreg = <&syscon_cam0>;
        samsung,cam1-sysreg = <&syscon_cam1>;
        samsung,disp-sysreg = <&syscon_disp>;
    };

  - |
    phy {
        compatible = "samsung,s5pv210-mipi-video-phy";
        syscon = <&pmu_system_controller>;
        #phy-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung SoC series UFS PHY

maintainers:
  - Alim Akhtar <alim.akhtar@samsung.com>

properties:
  "#phy-cells":
    const: 0

  compatible:
    enum:
      - samsung,exynos7-ufs-phy
      - samsung,exynosautov9-ufs-phy
      - tesla,fsd-ufs-phy

  reg:
    maxItems: 1

  reg-names:
    items:
      - const: phy-pma

  clocks:
    minItems: 1
    maxItems: 4

  clock-names:
    minItems: 1
    maxItems: 4

  samsung,pmu-syscon:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    maxItems: 1
    items:
      minItems: 1
      items:
        - description: phandle for PMU system controller interface, used to
                       control pmu registers bits for ufs m-phy
        - description: offset of the pmu control register
    description:
      It can be phandle/offset pair. The second cell which can represent an
      offset is optional.

required:
  - "#phy-cells"
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - samsung,pmu-syscon

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos7-ufs-phy

    then:
      properties:
        clocks:
          items:
            - description: PLL reference clock
            - description: symbol clock for input symbol (rx0-ch0 symbol clock)
            - description: symbol clock for input symbol (rx1-ch1 symbol clock)
            - description: symbol clock for output symbol (tx0 symbol clock)

        clock-names:
          items:
            - const: ref_clk
            - const: rx1_symbol_clk
            - const: rx0_symbol_clk
            - const: tx0_symbol_clk

    else:
      properties:
        clocks:
          items:
            - description: PLL reference clock

        clock-names:
          items:
            - const: ref_clk

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos7-clk.h>

    ufs_phy: ufs-phy@15571800 {
        compatible = "samsung,exynos7-ufs-phy";
        reg = <0x15571800 0x240>;
        reg-names = "phy-pma";
        samsung,pmu-syscon = <&pmu_system_controller>;
        #phy-cells = <0>;
        clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
                 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
                 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
                 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
        clock-names = "ref_clk", "rx1_symbol_clk",
                      "rx0_symbol_clk", "tx0_symbol_clk";

    };
...

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S5P/Exynos SoC USB 2.0 PHY

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Marek Szyprowski <m.szyprowski@samsung.com>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>

description: |
  The first phandle argument in the PHY specifier identifies the PHY, its
  meaning is compatible dependent. For the currently supported SoCs (Exynos4210
  and Exynos4212) it is as follows::
    0 - USB device ("device"),
    1 - USB host ("host"),
    2 - HSIC0 ("hsic0"),
    3 - HSIC1 ("hsic1"),
  Exynos3250 has only USB device phy available as phy 0.

  Exynos4210 and Exynos4212 use mode switching and require that mode switch
  register is supplied.

properties:
  compatible:
    enum:
      - samsung,exynos3250-usb2-phy
      - samsung,exynos4210-usb2-phy
      - samsung,exynos4x12-usb2-phy
      - samsung,exynos5250-usb2-phy
      - samsung,exynos5420-usb2-phy
      - samsung,s5pv210-usb2-phy

  clocks:
    items:
      - description: PHY module gate clock.
      - description: Reference rate clock of PHY module.

  clock-names:
    items:
      - const: phy
      - const: ref

  "#phy-cells":
    const: 1

  reg:
    maxItems: 1

  samsung,pmureg-phandle:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to PMU system controller interface.

  samsung,sysreg-phandle:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to system registers interface.

  vbus-supply:
    description:
      VBUS power source.

required:
  - compatible
  - clocks
  - clock-names
  - "#phy-cells"
  - reg
  - samsung,pmureg-phandle

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos4x12-usb2-phy
              - samsung,exynos5250-usb2-phy
              - samsung,exynos5420-usb2-phy
    then:
      required:
        - samsung,sysreg-phandle

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5420.h>

    phy@12130000 {
        compatible = "samsung,exynos5420-usb2-phy";
        reg = <0x12130000 0x100>;
        #phy-cells = <1>;
        clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
        clock-names = "phy", "ref";
        samsung,sysreg-phandle = <&sysreg_system_controller>;
        samsung,pmureg-phandle = <&pmu_system_controller>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Marek Szyprowski <m.szyprowski@samsung.com>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>

description: |
  For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
  compatible PHYs, the second cell in the PHY specifier identifies the
  PHY id, which is interpreted as follows::
    0 - UTMI+ type phy,
    1 - PIPE3 type phy.

  For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
  'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
  form of usbdrdphyN, N = 0, 1... (depending on number of controllers).

properties:
  compatible:
    enum:
      - samsung,exynos5250-usbdrd-phy
      - samsung,exynos5420-usbdrd-phy
      - samsung,exynos5433-usbdrd-phy
      - samsung,exynos7-usbdrd-phy

  clocks:
    minItems: 2
    maxItems: 5

  clock-names:
    minItems: 2
    maxItems: 5
    description: |
      At least two clocks::
        - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
          for register access.
        - PHY reference clock (usually crystal clock), used for PHY operations,
          associated by phy name. It is used to determine bit values for clock
          settings register.  For Exynos5420 this is given as 'sclk_usbphy30'
          in the CMU.

  "#phy-cells":
    const: 1

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      Any connector to the data bus of this controller should be modelled using
      the OF graph bindings specified.

  reg:
    maxItems: 1

  samsung,pmu-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to PMU system controller interface.

  vbus-supply:
    description:
      VBUS power source.

  vbus-boost-supply:
    description:
      VBUS Boost 5V power source.

required:
  - compatible
  - clocks
  - clock-names
  - "#phy-cells"
  - reg
  - samsung,pmu-syscon

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos5433-usbdrd-phy
              - samsung,exynos7-usbdrd-phy
    then:
      properties:
        clocks:
          minItems: 5
          maxItems: 5
        clock-names:
          items:
            - const: phy
            - const: ref
            - const: phy_utmi
            - const: phy_pipe
            - const: itp
    else:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: phy
            - const: ref

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5420.h>

    phy@12100000 {
        compatible = "samsung,exynos5420-usbdrd-phy";
        reg = <0x12100000 0x100>;
        #phy-cells = <1>;
        clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
        clock-names = "phy", "ref";
        samsung,pmu-syscon = <&pmu_system_controller>;
        vbus-supply = <&usb300_vbus_reg>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/socionext,uniphier-ahci-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier AHCI PHY

description: |
  This describes the deivcetree bindings for PHY interfaces built into
  AHCI controller implemented on Socionext UniPhier SoCs.

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

properties:
  compatible:
    enum:
      - socionext,uniphier-pro4-ahci-phy
      - socionext,uniphier-pxs2-ahci-phy
      - socionext,uniphier-pxs3-ahci-phy

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  clocks:
    minItems: 1
    maxItems: 2

  clock-names: true

  resets:
    minItems: 2
    maxItems: 6

  reset-names: true

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: socionext,uniphier-pro4-ahci-phy
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: link
            - const: gio
        resets:
          minItems: 6
          maxItems: 6
        reset-names:
          items:
            - const: link
            - const: gio
            - const: phy
            - const: pm
            - const: tx
            - const: rx
  - if:
      properties:
        compatible:
          contains:
            const: socionext,uniphier-pxs2-ahci-phy
    then:
      properties:
        clocks:
          maxItems: 1
        clock-names:
          const: link
        resets:
          minItems: 2
          maxItems: 2
        reset-names:
          items:
            - const: link
            - const: phy
  - if:
      properties:
        compatible:
          contains:
            const: socionext,uniphier-pxs3-ahci-phy
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: link
            - const: phy
        resets:
          minItems: 2
          maxItems: 2
        reset-names:
          items:
            - const: link
            - const: phy

required:
  - compatible
  - reg
  - "#phy-cells"
  - clocks
  - clock-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    ahci-glue@65700000 {
        compatible = "socionext,uniphier-pxs3-ahci-glue",
                     "simple-mfd";
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0x65700000 0x100>;

        ahci_phy: phy@10 {
            compatible = "socionext,uniphier-pxs3-ahci-phy";
            reg = <0x10 0x10>;
            #phy-cells = <0>;
            clock-names = "link", "phy";
            clocks = <&sys_clk 28>, <&sys_clk 30>;
            reset-names = "link", "phy";
            resets = <&sys_rst 28>, <&sys_rst 30>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier PCIe PHY

description: |
  This describes the devicetree bindings for PHY interface built into
  PCIe controller implemented on Socionext UniPhier SoCs.

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

properties:
  compatible:
    enum:
      - socionext,uniphier-pro5-pcie-phy
      - socionext,uniphier-ld20-pcie-phy
      - socionext,uniphier-pxs3-pcie-phy
      - socionext,uniphier-nx1-pcie-phy

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  clocks:
    minItems: 1
    maxItems: 2

  clock-names: true

  resets:
    minItems: 1
    maxItems: 2

  reset-names: true

  socionext,syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: A phandle to system control to set configurations for phy

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: socionext,uniphier-pro5-pcie-phy
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: gio
            - const: link
        resets:
          minItems: 2
          maxItems: 2
        reset-names:
          items:
            - const: gio
            - const: link
    else:
      properties:
        clocks:
          maxItems: 1
        clock-names:
          const: link
        resets:
          maxItems: 1
        reset-names:
          const: link

required:
  - compatible
  - reg
  - "#phy-cells"
  - clocks
  - clock-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    pcie_phy: phy@66038000 {
        compatible = "socionext,uniphier-ld20-pcie-phy";
        reg = <0x66038000 0x4000>;
        #phy-cells = <0>;
        clock-names = "link";
        clocks = <&sys_clk 24>;
        reset-names = "link";
        resets = <&sys_rst 24>;
        socionext,syscon = <&soc_glue>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier USB2 PHY

description: |
  This describes the devicetree bindings for PHY interface built into
  USB2 controller implemented on Socionext UniPhier SoCs.
  Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3
  controller doesn't include its own High-Speed PHY. This needs to specify
  USB2 PHY instead of USB3 HS-PHY.

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

properties:
  compatible:
    enum:
      - socionext,uniphier-pro4-usb2-phy
      - socionext,uniphier-ld11-usb2-phy

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

patternProperties:
  "^phy@[0-9]+$":
    type: object
    additionalProperties: false

    properties:
      reg:
        minimum: 0
        maximum: 3
        description:
          The ID number for the PHY

      "#phy-cells":
        const: 0

      vbus-supply:
        description: A phandle to the regulator for USB VBUS, only for USB host

    required:
      - reg
      - "#phy-cells"

required:
  - compatible
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:
  - |
    // The UniPhier usb2-phy should be a subnode of a "syscon" compatible node.

    soc-glue@5f800000 {
        compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon";
        reg = <0x5f800000 0x2000>;

        usb-controller {
            compatible = "socionext,uniphier-ld11-usb2-phy";
            #address-cells = <1>;
            #size-cells = <0>;

            usb_phy0: phy@0 {
                reg = <0>;
                #phy-cells = <0>;
            };

            usb_phy1: phy@1 {
                reg = <1>;
                #phy-cells = <0>;
            };

            usb_phy2: phy@2 {
                reg = <2>;
                #phy-cells = <0>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier USB3 High-Speed (HS) PHY

description: |
  This describes the devicetree bindings for PHY interfaces built into
  USB3 controller implemented on Socionext UniPhier SoCs.
  Although the controller includes High-Speed PHY and Super-Speed PHY,
  this describes about High-Speed PHY.

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

properties:
  compatible:
    enum:
      - socionext,uniphier-pro5-usb3-hsphy
      - socionext,uniphier-pxs2-usb3-hsphy
      - socionext,uniphier-ld20-usb3-hsphy
      - socionext,uniphier-pxs3-usb3-hsphy
      - socionext,uniphier-nx1-usb3-hsphy

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  clocks:
    minItems: 2
    maxItems: 3

  clock-names: true

  resets:
    maxItems: 2

  reset-names: true

  vbus-supply:
    description: A phandle to the regulator for USB VBUS

  nvmem-cells:
    maxItems: 3
    description:
      Phandles to nvmem cell that contains the trimming data.
      Available only for HS-PHY implemented on LD20 and PXs3, and
      if unspecified, default value is used.

  nvmem-cell-names:
    items:
      - const: rterm
      - const: sel_t
      - const: hs_i
    description:
      Should be the following names, which correspond to each nvmem-cells.
      All of the 3 parameters associated with the above names are
      required for each port, if any one is omitted, the trimming data
      of the port will not be set at all.

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: socionext,uniphier-pro5-usb3-hsphy
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: gio
            - const: link
        resets:
          minItems: 2
          maxItems: 2
        reset-names:
          items:
            - const: gio
            - const: link
  - if:
      properties:
        compatible:
          contains:
            enum:
              - socionext,uniphier-pxs2-usb3-hsphy
              - socionext,uniphier-ld20-usb3-hsphy
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: link
            - const: phy
        resets:
          minItems: 2
          maxItems: 2
        reset-names:
          items:
            - const: link
            - const: phy
  - if:
      properties:
        compatible:
          contains:
            enum:
              - socionext,uniphier-pxs3-usb3-hsphy
              - socionext,uniphier-nx1-usb3-hsphy
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 3
        clock-names:
          minItems: 2
          items:
            - const: link
            - const: phy
            - const: phy-ext
        resets:
          minItems: 2
          maxItems: 2
        reset-names:
          items:
            - const: link
            - const: phy

required:
  - compatible
  - reg
  - "#phy-cells"
  - clocks
  - clock-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    usb-glue@65b00000 {
        compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0x65b00000 0x400>;

        usb_hsphy0: hs-phy@200 {
            compatible = "socionext,uniphier-ld20-usb3-hsphy";
            reg = <0x200 0x10>;
            #phy-cells = <0>;
            clock-names = "link", "phy";
            clocks = <&sys_clk 14>, <&sys_clk 16>;
            reset-names = "link", "phy";
            resets = <&sys_rst 14>, <&sys_rst 16>;
            vbus-supply = <&usb_vbus0>;
            nvmem-cell-names = "rterm", "sel_t", "hs_i";
            nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier USB3 Super-Speed (SS) PHY

description: |
  This describes the devicetree bindings for PHY interfaces built into
  USB3 controller implemented on Socionext UniPhier SoCs.
  Although the controller includes High-Speed PHY and Super-Speed PHY,
  this describes about Super-Speed PHY.

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

properties:
  compatible:
    enum:
      - socionext,uniphier-pro4-usb3-ssphy
      - socionext,uniphier-pro5-usb3-ssphy
      - socionext,uniphier-pxs2-usb3-ssphy
      - socionext,uniphier-ld20-usb3-ssphy
      - socionext,uniphier-pxs3-usb3-ssphy
      - socionext,uniphier-nx1-usb3-ssphy

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  clocks:
    minItems: 2
    maxItems: 3

  clock-names: true

  resets:
    maxItems: 2

  reset-names: true

  vbus-supply:
    description: A phandle to the regulator for USB VBUS, only for USB host

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - socionext,uniphier-pro4-usb3-ssphy
              - socionext,uniphier-pro5-usb3-ssphy
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: gio
            - const: link
        resets:
          minItems: 2
          maxItems: 2
        reset-names:
          items:
            - const: gio
            - const: link
  - if:
      properties:
        compatible:
          contains:
            enum:
              - socionext,uniphier-pxs2-usb3-ssphy
              - socionext,uniphier-ld20-usb3-ssphy
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: link
            - const: phy
        resets:
          minItems: 2
          maxItems: 2
        reset-names:
          items:
            - const: link
            - const: phy
  - if:
      properties:
        compatible:
          contains:
            enum:
              - socionext,uniphier-pxs3-usb3-ssphy
              - socionext,uniphier-nx1-usb3-ssphy
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 3
        clock-names:
          minItems: 2
          items:
            - const: link
            - const: phy
            - const: phy-ext
        resets:
          minItems: 2
          maxItems: 2
        reset-names:
          items:
            - const: link
            - const: phy

required:
  - compatible
  - reg
  - "#phy-cells"
  - clocks
  - clock-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    usb-glue@65b00000 {
        compatible = "socionext,uniphier-ld20-dwc3-glue",
                     "simple-mfd";
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0x65b00000 0x400>;

        usb_ssphy0: ss-phy@300 {
            compatible = "socionext,uniphier-ld20-usb3-ssphy";
            reg = <0x300 0x10>;
            #phy-cells = <0>;
            clock-names = "link", "phy";
            clocks = <&sys_clk 14>, <&sys_clk 16>;
            reset-names = "link", "phy";
            resets = <&sys_rst 14>, <&sys_rst 16>;
            vbus-supply = <&usb_vbus0>;
        };
    };


code:
ST SPEAr miphy DT details
=========================

ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA.

Required properties:
- compatible : should be "st,spear1310-miphy" or "st,spear1340-miphy"
- reg : offset and length of the PHY register set.
- misc: phandle for the syscon node to access misc registers
- #phy-cells : from the generic PHY bindings, must be 1.
	- cell[1]: 0 if phy used for SATA, 1 for PCIe.

Optional properties:
- phy-id: Instance id of the phy. Only required when there are multiple phys
  present on a implementation.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/sunplus,sp7021-usb2-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Sunplus SP7021 USB 2.0 PHY Controller

maintainers:
  - Vincent Shih <vincent.sunplus@gmail.com>

properties:
  compatible:
    const: sunplus,sp7021-usb2-phy

  reg:
    items:
      - description: UPHY register region
      - description: MOON4 register region

  reg-names:
    items:
      - const: phy
      - const: moon4

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  "#phy-cells":
    const: 0

  nvmem-cell-names:
    description: names corresponding to the nvmem cells of disconnect voltage
    const: disc_vol

  nvmem-cells:
    description: nvmem cell address of disconnect voltage
    maxItems: 1

  sunplus,disc-vol-addr-off:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: the otp address offset of disconnect voltage

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - resets
  - "#phy-cells"
  - nvmem-cell-names
  - nvmem-cells
  - sunplus,disc-vol-addr-off

additionalProperties: false

examples:
  - |
    sp_uphy0: usb-phy@9c004a80 {
      compatible = "sunplus,sp7021-usb2-phy";
      reg = <0x9c004a80 0x80>, <0x9c000248 0x10>;
      reg-names = "phy", "moon4";
      clocks = <&clkc 0x3d>;
      resets = <&rstc 0x2d>;
      #phy-cells = <0>;
      nvmem-cell-names = "disc_vol";
      nvmem-cells = <&disc_vol>;
      sunplus,disc-vol-addr-off = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/ti,omap-usb2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: OMAP USB2 PHY

maintainers:
  - Kishon Vijay Abraham I <kishon@ti.com>
  - Roger Quadros <rogerq@kernel.org>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - ti,dra7x-usb2
              - ti,dra7x-usb2-phy2
              - ti,am654-usb2
          - enum:
              - ti,omap-usb2
      - items:
          - const: ti,am437x-usb2
      - items:
          - const: ti,omap-usb2

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  clocks:
    minItems: 1
    items:
      - description: wakeup clock
      - description: reference clock

  clock-names:
    minItems: 1
    items:
      - const: wkupclk
      - const: refclk

  syscon-phy-power:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to the system control module
          - description: register offset to power on/off the PHY
    description:
      phandle/offset pair. Phandle to the system control module and
      register offset to power on/off the PHY.

  ctrl-module:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      (deprecated) phandle of the control module used by PHY driver
      to power on the PHY. Use syscon-phy-power instead.

required:
  - compatible
  - reg
  - "#phy-cells"
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    usb0_phy: phy@4100000 {
      compatible = "ti,am654-usb2", "ti,omap-usb2";
      reg = <0x4100000 0x54>;
      syscon-phy-power = <&scm_conf 0x4000>;
      clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
      clock-names = "wkupclk", "refclk";
      #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI AM654 SERDES binding

description:
  This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
  to be used with either PCIe or USB or SGMII.

maintainers:
  - Kishon Vijay Abraham I <kishon@ti.com>

properties:
  compatible:
    enum:
      - ti,phy-am654-serdes

  reg:
    maxItems: 1

  reg-names:
    items:
      - const: serdes

  power-domains:
    maxItems: 1

  clocks:
    maxItems: 3
    description:
      Three input clocks referring to left input reference clock, refclk and right input reference
      clock.

  assigned-clocks:
    $ref: "/schemas/types.yaml#/definitions/phandle-array"
  assigned-clock-parents:
    $ref: "/schemas/types.yaml#/definitions/phandle-array"

  '#phy-cells':
    const: 2
    description:
      The 1st cell corresponds to the phy type (should be one of the types specified in
      include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes lane function.

  ti,serdes-clk:
    description: Phandle to the SYSCON entry required for configuring SERDES clock selection.
    $ref: /schemas/types.yaml#/definitions/phandle

  '#clock-cells':
    const: 1

  mux-controls:
    maxItems: 1
    description: Phandle to the SYSCON entry required for configuring SERDES lane function.

  clock-output-names:
    oneOf:
      - description: Clock output names for SERDES 0
        items:
          - const: serdes0_cmu_refclk
          - const: serdes0_lo_refclk
          - const: serdes0_ro_refclk
      - description: Clock output names for SERDES 1
        items:
          - const: serdes1_cmu_refclk
          - const: serdes1_lo_refclk
          - const: serdes1_ro_refclk

required:
  - compatible
  - reg
  - power-domains
  - clocks
  - assigned-clocks
  - assigned-clock-parents
  - ti,serdes-clk
  - mux-controls
  - clock-output-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/phy/phy-am654-serdes.h>

    serdes0: serdes@900000 {
      compatible = "ti,phy-am654-serdes";
      reg = <0x900000 0x2000>;
      reg-names = "serdes";
      #phy-cells = <2>;
      power-domains = <&k3_pds 153>;
      clocks = <&k3_clks 153 4>, <&k3_clks 153 1>,
               <&serdes1 AM654_SERDES_LO_REFCLK>;
      clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
      assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
      assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
      ti,serdes-clk = <&serdes0_clk>;
      mux-controls = <&serdes_mux 0>;
      #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: CPSW Port's Interface Mode Selection PHY Tree Bindings

maintainers:
  - Kishon Vijay Abraham I <kishon@ti.com>

description: |
  TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
  two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
  The interface mode is selected by configuring the MII mode selection register(s)
  (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
  bit fields placement in SCM are different between SoCs while fields meaning
  is the same.
                                               +--------------+
        +-------------------------------+      |SCM           |
        |                     CPSW      |      |  +---------+ |
        |        +--------------------------------+gmii_sel | |
        |        |                      |      |  +---------+ |
        |   +----v---+     +--------+   |      +--------------+
        |   |Port 1..<--+-->GMII/MII<------->
        |   |        |  |  |        |   |
        |   +--------+  |  +--------+   |
        |               |               |
        |               |  +--------+   |
        |               |  | RMII   <------->
        |               +-->        |   |
        |               |  +--------+   |
        |               |               |
        |               |  +--------+   |
        |               |  | RGMII  <------->
        |               +-->        |   |
        |                  +--------+   |
        +-------------------------------+

  CPSW Port's Interface Mode Selection PHY describes MII interface mode between
  CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
  |
  CPSW Port's Interface Mode Selection PHY device should defined as child device
  of SCM node (scm_conf) and can be attached to each CPSW port node using standard
  PHY bindings.

properties:
  compatible:
    enum:
      - ti,am3352-phy-gmii-sel
      - ti,dra7xx-phy-gmii-sel
      - ti,am43xx-phy-gmii-sel
      - ti,dm814-phy-gmii-sel
      - ti,am654-phy-gmii-sel
      - ti,j7200-cpsw5g-phy-gmii-sel

  reg:
    maxItems: 1

  '#phy-cells': true

  ti,qsgmii-main-ports:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: |
      Required only for QSGMII mode. Array to select the port for
      QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
      ports automatically. Any one of the 4 CPSW5G ports can act as the
      main port with the rest of them being the QSGMII_SUB ports.
    maxItems: 1
    items:
      minimum: 1
      maximum: 4

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - ti,dra7xx-phy-gmii-sel
              - ti,dm814-phy-gmii-sel
              - ti,am654-phy-gmii-sel
    then:
      properties:
        '#phy-cells':
          const: 1
          description: CPSW port number (starting from 1)

  - if:
      not:
        properties:
          compatible:
            contains:
              enum:
                - ti,j7200-cpsw5g-phy-gmii-sel
    then:
      properties:
        ti,qsgmii-main-ports: false

  - if:
      properties:
        compatible:
          contains:
            enum:
              - ti,am3352-phy-gmii-sel
              - ti,am43xx-phy-gmii-sel
    then:
      properties:
        '#phy-cells':
          const: 2
          description: |
            - CPSW port number (starting from 1)
            - RMII refclk mode

required:
  - compatible
  - reg
  - '#phy-cells'

additionalProperties: false

examples:
  - |
    phy_gmii_sel: phy@650 {
        compatible = "ti,am3352-phy-gmii-sel";
        reg = <0x650 0x4>;
        #phy-cells = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: TI J721E WIZ (SERDES Wrapper)

maintainers:
  - Kishon Vijay Abraham I <kishon@ti.com>

properties:
  compatible:
    enum:
      - ti,j721e-wiz-16g
      - ti,j721e-wiz-10g
      - ti,am64-wiz-10g
      - ti,j7200-wiz-10g

  power-domains:
    maxItems: 1

  clocks:
    minItems: 3
    maxItems: 4
    description: clock-specifier to represent input to the WIZ

  clock-names:
    minItems: 3
    items:
      - const: fck
      - const: core_ref_clk
      - const: ext_ref_clk
      - const: core_ref1_clk

  num-lanes:
    minimum: 1
    maximum: 4

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  "#reset-cells":
    const: 1

  "#clock-cells":
    const: 1

  ranges: true

  assigned-clocks:
    minItems: 1
    maxItems: 2

  assigned-clock-parents:
    minItems: 1
    maxItems: 2

  assigned-clock-rates:
    minItems: 1
    maxItems: 2

  typec-dir-gpios:
    maxItems: 1
    description:
      GPIO to signal Type-C cable orientation for lane swap.
      If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
      achieve the funtionality of an external type-C plug flip mux.

  typec-dir-debounce-ms:
    minimum: 100
    maximum: 1000
    default: 100
    description:
      Number of milliseconds to wait before sampling typec-dir-gpio.
      If not specified, the default debounce of 100ms will be used.
      Type-C spec states minimum CC pin debounce of 100 ms and maximum
      of 200 ms. However, some solutions might need more than 200 ms.

  refclk-dig:
    type: object
    additionalProperties: false
    description: |
      WIZ node should have subnode for refclk_dig to select the reference
      clock source for the reference clock used in the PHY and PMA digital
      logic.
    deprecated: true
    properties:
      clocks:
        minItems: 2
        maxItems: 4
        description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
          the inputs to refclk_dig

      "#clock-cells":
        const: 0

      assigned-clocks:
        maxItems: 1

      assigned-clock-parents:
        maxItems: 1

    required:
      - clocks
      - "#clock-cells"
      - assigned-clocks
      - assigned-clock-parents

  ti,scm:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      phandle to System Control Module for syscon regmap access.

patternProperties:
  "^pll[0|1]-refclk$":
    type: object
    additionalProperties: false
    description: |
      WIZ node should have subnodes for each of the PLLs present in
      the SERDES.
    deprecated: true
    properties:
      clocks:
        maxItems: 2
        description: Phandle to clock nodes representing the two inputs to PLL.

      "#clock-cells":
        const: 0

      assigned-clocks:
        maxItems: 1

      assigned-clock-parents:
        maxItems: 1

    required:
      - clocks
      - "#clock-cells"
      - assigned-clocks
      - assigned-clock-parents

  "^cmn-refclk1?-dig-div$":
    type: object
    additionalProperties: false
    description:
      WIZ node should have subnodes for each of the PMA common refclock
      provided by the SERDES.
    deprecated: true
    properties:
      clocks:
        maxItems: 1
        description: Phandle to the clock node representing the input to the
          divider clock.

      "#clock-cells":
        const: 0

    required:
      - clocks
      - "#clock-cells"

  "^serdes@[0-9a-f]+$":
    type: object
    description: |
      WIZ node should have '1' subnode for the SERDES. It could be either
      Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
      bindings specified in
      Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
      Torrent SERDES should follow the bindings specified in
      Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml

required:
  - compatible
  - power-domains
  - clocks
  - clock-names
  - num-lanes
  - "#address-cells"
  - "#size-cells"
  - "#reset-cells"
  - ranges

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: ti,j7200-wiz-10g
    then:
      required:
        - ti,scm

additionalProperties: false

examples:
  - |
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    wiz@5000000 {
           compatible = "ti,j721e-wiz-16g";
           #address-cells = <1>;
           #size-cells = <1>;
           power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
           clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
           clock-names = "fck", "core_ref_clk", "ext_ref_clk";
           assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
           assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
           num-lanes = <2>;
           #reset-cells = <1>;
           ranges = <0x5000000 0x5000000 0x10000>;

           pll0-refclk {
                  clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
                  #clock-cells = <0>;
                  assigned-clocks = <&wiz1_pll0_refclk>;
                  assigned-clock-parents = <&k3_clks 293 13>;
           };

           pll1-refclk {
                  clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
                  #clock-cells = <0>;
                  assigned-clocks = <&wiz1_pll1_refclk>;
                  assigned-clock-parents = <&k3_clks 293 0>;
           };

           cmn-refclk-dig-div {
                  clocks = <&wiz1_refclk_dig>;
                  #clock-cells = <0>;
           };

           cmn-refclk1-dig-div {
                  clocks = <&wiz1_pll1_refclk>;
                  #clock-cells = <0>;
           };

           refclk-dig {
                  clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
                          <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
                  #clock-cells = <0>;
                  assigned-clocks = <&wiz0_refclk_dig>;
                  assigned-clock-parents = <&k3_clks 292 11>;
           };

           serdes@5000000 {
                  compatible = "ti,sierra-phy-t0";
                  reg-names = "serdes";
                  reg = <0x5000000 0x10000>;
                  #address-cells = <1>;
                  #size-cells = <0>;
                  resets = <&serdes_wiz0 0>;
                  reset-names = "sierra_reset";
                  clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
                  clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
           };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/ti,tcan104x-can.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: TCAN104x CAN TRANSCEIVER PHY

maintainers:
  - Aswath Govindraju <a-govindraju@ti.com>

properties:
  $nodename:
    pattern: "^can-phy"

  compatible:
    enum:
      - ti,tcan1042
      - ti,tcan1043

  '#phy-cells':
    const: 0

  standby-gpios:
    description:
      gpio node to toggle standby signal on transceiver
    maxItems: 1

  enable-gpios:
    description:
      gpio node to toggle enable signal on transceiver
    maxItems: 1

  max-bitrate:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      max bit rate supported in bps
    minimum: 1

  mux-states:
    description:
      mux controller node to route the signals from controller to
      transceiver.
    maxItems: 1

required:
  - compatible
  - '#phy-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    transceiver1: can-phy {
      compatible = "ti,tcan1043";
      #phy-cells = <0>;
      max-bitrate = <5000000>;
      standby-gpios = <&wakeup_gpio1 16 GPIO_ACTIVE_LOW>;
      enable-gpios = <&main_gpio1 67 GPIO_ACTIVE_HIGH>;
      mux-states = <&mux0 1>;
    };


code:
TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs

OMAP CONTROL PHY

Required properties:
 - compatible: Should be one of
 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
                        e.g. USB2_PHY on OMAP5.
 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
                        e.g. USB3 PHY and SATA PHY on OMAP5.
 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
			set PCS delay value.
			e.g. PCIE PHY in DRA7x
 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
                        DRA7 platform.
 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
                        AM437 platform.
 - reg : register ranges as listed in the reg-names property
 - reg-names: "otghs_control" for control-phy-otghs
	      "power", "pcie_pcs" and "control_sma" for control-phy-pcie
	      "power" for all other types

omap_control_usb: omap-control-usb@4a002300 {
        compatible = "ti,control-phy-otghs";
        reg = <0x4a00233c 0x4>;
        reg-names = "otghs_control";
};

TI PIPE3 PHY

Required properties:
 - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
   "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
 - reg : Address and length of the register set for the device.
 - reg-names: The names of the register addresses corresponding to the registers
   filled in "reg".
 - #phy-cells: determine the number of cells that should be given in the
   phandle while referencing this phy.
 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
   clock-names.
 - clock-names: should include:
   * "wkupclk" - wakeup clock.
   * "sysclk" - system clock.
   * "refclk" - reference clock.
   * "dpll_ref" - external dpll ref clk
   * "dpll_ref_m2" - external dpll ref clk
   * "phy-div" - divider for apll
   * "div-clk" - apll clock

Optional properties:
 - id: If there are multiple instance of the same type, in order to
   differentiate between each instance "id" can be used (e.g., multi-lane PCIe
   PHY). If "id" is not provided, it is set to default value of '1'.
 - syscon-pllreset: Handle to system control region that contains the
   CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
   register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
 - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
   register offset to write the PCS delay value.

Deprecated properties:
 - ctrl-module : phandle of the control module used by PHY driver to power on
   the PHY.

Recommended properies:
 - syscon-phy-power : phandle/offset pair. Phandle to the system control
   module and the register offset to power on/off the PHY.

This is usually a subnode of ocp2scp to which it is connected.

usb3phy@4a084400 {
	compatible = "ti,phy-usb3";
	reg = <0x4a084400 0x80>,
	      <0x4a084800 0x64>,
	      <0x4a084c00 0x40>;
	reg-names = "phy_rx", "phy_tx", "pll_ctrl";
	ctrl-module = <&omap_control_usb>;
	#phy-cells = <0>;
	clocks = <&usb_phy_cm_clk32k>,
		 <&sys_clkin>,
		 <&usb_otg_ss_refclk960m>;
	clock-names =	"wkupclk",
			"sysclk",
			"refclk";
};

sata_phy: phy@4a096000 {
	compatible = "ti,phy-pipe3-sata";
	reg = <0x4A096000 0x80>, /* phy_rx */
	      <0x4A096400 0x64>, /* phy_tx */
	      <0x4A096800 0x40>; /* pll_ctrl */
	reg-names = "phy_rx", "phy_tx", "pll_ctrl";
	ctrl-module = <&omap_control_sata>;
	clocks = <&sys_clkin1>, <&sata_ref_clk>;
	clock-names = "sysclk", "refclk";
	syscon-pllreset = <&scm_conf 0x3fc>;
	#phy-cells = <0>;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common PHY and network PCS transmit amplitude property binding

description:
  Binding describing the peak-to-peak transmit amplitude for common PHYs
  and network PCSes.

maintainers:
  - Marek Behún <kabel@kernel.org>

properties:
  tx-p2p-microvolt:
    description:
      Transmit amplitude voltages in microvolts, peak-to-peak. If this property
      contains multiple values for various PHY modes, the
      'tx-p2p-microvolt-names' property must be provided and contain
      corresponding mode names.

  tx-p2p-microvolt-names:
    description: |
      Names of the modes corresponding to voltages in the 'tx-p2p-microvolt'
      property. Required only if multiple voltages are provided.

      If a value of 'default' is provided, the system should use it for any PHY
      mode that is otherwise not defined here. If 'default' is not provided, the
      system should use manufacturer default value.
    minItems: 1
    maxItems: 16
    items:
      enum:
        - default

        # ethernet modes
        - sgmii
        - qsgmii
        - xgmii
        - 1000base-x
        - 2500base-x
        - 5gbase-r
        - rxaui
        - xaui
        - 10gbase-kr
        - usxgmii
        - 10gbase-r
        - 25gbase-r

        # PCIe modes
        - pcie
        - pcie1
        - pcie2
        - pcie3
        - pcie4
        - pcie5
        - pcie6

        # USB modes
        - usb
        - usb-ls
        - usb-fs
        - usb-hs
        - usb-ss
        - usb-ss+
        - usb-4

        # storage modes
        - sata
        - ufs-hs
        - ufs-hs-a
        - ufs-hs-b

        # display modes
        - lvds
        - dp
        - dp-rbr
        - dp-hbr
        - dp-hbr2
        - dp-hbr3
        - dp-uhbr-10
        - dp-uhbr-13.5
        - dp-uhbr-20

        # camera modes
        - mipi-dphy
        - mipi-dphy-univ
        - mipi-dphy-v2.5-univ

dependencies:
  tx-p2p-microvolt-names: [ tx-p2p-microvolt ]

additionalProperties: true

examples:
  - |
    phy: phy {
      #phy-cells = <1>;
      tx-p2p-microvolt = <915000>, <1100000>, <1200000>;
      tx-p2p-microvolt-names = "2500base-x", "usb-hs", "usb-ss";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx ZynqMP Gigabit Transceiver PHY

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description: |
  This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
  GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
  Ethernet SGMII controllers.

properties:
  "#phy-cells":
    const: 4
    description: |
      The cells contain the following arguments.

      - description: The GTR lane
        minimum: 0
        maximum: 3
      - description: The PHY type
        enum:
          - PHY_TYPE_DP
          - PHY_TYPE_PCIE
          - PHY_TYPE_SATA
          - PHY_TYPE_SGMII
          - PHY_TYPE_USB3
      - description: The PHY instance
        minimum: 0
        maximum: 1 # for DP, SATA or USB
        maximum: 3 # for PCIE or SGMII
      - description: The reference clock number
        minimum: 0
        maximum: 3

  compatible:
    enum:
      - xlnx,zynqmp-psgtr-v1.1
      - xlnx,zynqmp-psgtr

  clocks:
    minItems: 1
    maxItems: 4
    description: |
      Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
      inputs shall not have an entry.

  clock-names:
    minItems: 1
    maxItems: 4
    items:
      pattern: "^ref[0-3]$"

  reg:
    items:
      - description: SERDES registers block
      - description: SIOU registers block

  reg-names:
    items:
      - const: serdes
      - const: siou

  xlnx,tx-termination-fix:
    description: |
      Include this for fixing functional issue with the TX termination
      resistance in GT, which can be out of spec for the XCZU9EG silicon
      version.
    type: boolean

required:
  - "#phy-cells"
  - compatible
  - reg
  - reg-names

if:
  properties:
    compatible:
      const: xlnx,zynqmp-psgtr-v1.1

then:
  properties:
    xlnx,tx-termination-fix: false

additionalProperties: false

examples:
  - |
    phy: phy@fd400000 {
        compatible = "xlnx,zynqmp-psgtr-v1.1";
        reg = <0xfd400000 0x40000>,
              <0xfd3d0000 0x1000>;
        reg-names = "serdes", "siou";
        clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
        clock-names = "ref1", "ref2", "ref3";
        #phy-cells = <4>;
    };

...


code:
Abilis Systems TB10x pin controller
===================================

Required properties
-------------------

- compatible: should be "abilis,tb10x-iomux";
- reg: should contain the physical address and size of the pin controller's
  register range.

Function definitions
--------------------

Functions are defined (and referenced) by sub-nodes of the pin controller.
Every sub-node defines exactly one function (implying a set of pins).
Every function is associated to one named pin group inside the pin controller
driver and these names are used to associate pin group predefinitions to pin
controller sub-nodes.

Required function definition subnode properties:
  - abilis,function: should be set to the name of the function's pin group.

The following pin groups are available:
  - GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog,
                gpioh, gpioi, gpioj, gpiok, gpiol, gpiom, gpion
  - Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7
  - Parallel TS input ports: mip1, mip3, mip5, mip7
  - Serial TS output ports: mos0, mos1, mos2, mos3
  - Parallel TS output port: mop
  - CI+ port: ciplus
  - CableCard (Mcard) port: mcard
  - Smart card ports: stc0, stc1
  - UART ports: uart0, uart1
  - SPI ports: spi1, spi3
  - JTAG: jtag

All other ports of the chip are not multiplexed and thus not managed by this
driver.

GPIO ranges definition
----------------------

The named pin groups of GPIO ports can be used to define GPIO ranges as
explained in Documentation/devicetree/bindings/gpio/gpio.txt.

Example
-------

iomux: iomux@ff10601c {
	compatible = "abilis,tb10x-iomux";
	reg = <0xFF10601c 0x4>;
	pctl_gpio_a: pctl-gpio-a {
		abilis,function = "gpioa";
	};
	pctl_uart0: pctl-uart0 {
		abilis,function = "uart0";
	};
};
uart@ff100000 {
	compatible = "snps,dw-apb-uart";
	reg = <0xFF100000 0x100>;
	clock-frequency = <166666666>;
	interrupts = <25 1>;
	reg-shift = <2>;
	reg-io-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&pctl_uart0>;
};
gpioa: gpio@ff140000 {
	compatible = "abilis,tb10x-gpio";
	reg = <0xFF140000 0x1000>;
	gpio-controller;
	#gpio-cells = <2>;
	ngpio = <3>;
	gpio-ranges = <&iomux 0 0>;
	gpio-ranges-group-names = "gpioa";
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Actions Semi S500 SoC pinmux & GPIO controller

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

description: |
  Pinmux & GPIO controller manages pin multiplexing & configuration including
  GPIO function selection & GPIO attributes configuration. Please refer to
  pinctrl-bindings.txt in this directory for common binding part and usage.

properties:
  compatible:
    const: actions,s500-pinctrl

  reg:
    items:
      - description: GPIO Output + GPIO Input + GPIO Data
      - description: Multiplexing Control
      - description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control
      - description: PAD Drive Capacity Select
    minItems: 1

  clocks:
    maxItems: 1

  gpio-controller: true

  gpio-ranges:
    maxItems: 1

  '#gpio-cells':
    description:
      Specifies the pin number and flags, as defined in
      include/dt-bindings/gpio/gpio.h
    const: 2

  interrupt-controller: true

  '#interrupt-cells':
    description:
      Specifies the pin number and flags, as defined in
      include/dt-bindings/interrupt-controller/irq.h
    const: 2

  interrupts:
    description:
      One interrupt per each of the 5 GPIO ports supported by the controller,
      sorted by port number ascending order.
    minItems: 5
    maxItems: 5

patternProperties:
  '-pins$':
    type: object
    patternProperties:
      '^(.*-)?pinmux$':
        type: object
        description:
          Pinctrl node's client devices specify pin muxes using subnodes,
          which in turn use the standard properties below.
        $ref: pinmux-node.yaml#

        properties:
          groups:
            description:
              List of gpio pin groups affected by the functions specified in
              this subnode.
            items:
              oneOf:
                - enum: [lcd0_d18_mfp, rmii_crs_dv_mfp, rmii_txd0_mfp,
                         rmii_txd1_mfp, rmii_txen_mfp, rmii_rxen_mfp, rmii_rxd1_mfp,
                         rmii_rxd0_mfp, rmii_ref_clk_mfp, i2s_d0_mfp, i2s_pcm1_mfp,
                         i2s0_pcm0_mfp, i2s1_pcm0_mfp, i2s_d1_mfp, ks_in2_mfp,
                         ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, ks_out0_mfp,
                         ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
                         dsi_dp2_mfp, lcd0_d17_mfp, dsi_dp3_mfp, dsi_dn3_mfp,
                         dsi_dp0_mfp, lvds_ee_pn_mfp, spi0_i2c_pcm_mfp,
                         spi0_i2s_pcm_mfp, dsi_dnp1_cp_mfp, lvds_e_pn_mfp,
                         dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
                         uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
                         sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
                         uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp,
                         uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp,
                         pcm1_in_mfp, pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp,
                         dnand_data_wr_mfp, dnand_acle_ce0_mfp, nand_ceb2_mfp,
                         nand_ceb3_mfp]
            minItems: 1
            maxItems: 32

          function:
            description:
              Specify the alternative function to be configured for the
              given gpio pin groups.
            enum: [nor, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
                   sens1, uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0,
                   i2s1, pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
                   p0, sd0, sd1, sd2, i2c0, i2c1, i2c3, dsi, lvds, usb30, clko_25m,
                   mipi_csi, nand, spdif, ts, lcd0]

        required:
          - groups
          - function

        additionalProperties: false

      '^(.*-)?pinconf$':
        type: object
        description:
          Pinctrl node's client devices specify pin configurations using
          subnodes, which in turn use the standard properties below.
        $ref: pincfg-node.yaml#

        properties:
          groups:
            description:
              List of gpio pin groups affected by the drive-strength property
              specified in this subnode.
            items:
              oneOf:
                - enum: [sirq_drv, rmii_txd01_txen_drv, rmii_rxer_drv,
                         rmii_crs_drv, rmii_rxd10_drv, rmii_ref_clk_drv,
                         smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv,
                         i2s13_drv, pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv,
                         lcd_dsi_drv, dsi_drv, sd0_d0_d3_drv, sd1_d0_d3_drv,
                         sd0_cmd_drv, sd0_clk_drv, sd1_cmd_drv, sd1_clk_drv,
                         spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv,
                         i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv,
                         sens0_ckout_drv, uart3_all_drv]
            minItems: 1
            maxItems: 32

          pins:
            description:
              List of gpio pins affected by the bias-pull-* and
              input-schmitt-* properties specified in this subnode.
            items:
              oneOf:
                - enum: [dnand_dqs, dnand_dqsn, eth_txd0, eth_txd1, eth_txen,
                         eth_rxer, eth_crs_dv, eth_rxd1, eth_rxd0, eth_ref_clk,
                         eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
                         i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1,
                         i2s_mclk1, ks_in0, ks_in1, ks_in2, ks_in3, ks_out0, ks_out1,
                         ks_out2, lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
                         lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep,
                         lvds_een, lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp,
                         lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, lcd0_d17, dsi_dp3,
                         dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, dsi_dp0, dsi_dn0,
                         dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0,
                         sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
                         spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
                         uart0_tx, i2c0_sclk, i2c0_sdata, sensor0_pclk,
                         sensor0_ckout, dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1,
                         dnand_ceb2, dnand_ceb3, uart2_rx, uart2_tx, uart2_rtsb,
                         uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb,
                         pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, i2c1_sclk,
                         i2c1_sdata, i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0,
                         csi_dn1, csi_dp1, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
                         csi_cn, csi_cp, dnand_d0, dnand_d1, dnand_d2, dnand_d3,
                         dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_rb, dnand_rdb,
                         dnand_rdbn, dnand_wrb, porb, clko_25m, bsel, pkg0, pkg1,
                         pkg2, pkg3]
            minItems: 1
            maxItems: 64

          bias-pull-up: true
          bias-pull-down: true

          drive-strength:
            description:
              Selects the drive strength for the specified pins, in mA.
            enum: [2, 4, 8, 12]

          input-schmitt-enable: true
          input-schmitt-disable: true

        additionalProperties: false

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - clocks
  - gpio-controller
  - gpio-ranges
  - '#gpio-cells'
  - interrupt-controller
  - '#interrupt-cells'
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl: pinctrl@b01b0000 {
        compatible = "actions,s500-pinctrl";
        reg = <0xb01b0000 0x40>, <0xb01b0040 0x10>,
              <0xb01b0060 0x18>, <0xb01b0080 0xc>;
        clocks = <&cmu 55>;
        gpio-controller;
        gpio-ranges = <&pinctrl 0 0 132>;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

        mmc0_pins: mmc0-pins {
            pinmux {
                groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
                         "sd0_cmd_mfp", "sd0_clk_mfp";
                function = "sd0";
            };

            drv-pinconf {
                groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
                drive-strength = <8>;
            };

            bias-pinconf {
                pins = "sd0_d0", "sd0_d1", "sd0_d2",
                       "sd0_d3", "sd0_cmd";
                bias-pull-up;
            };
        };
    };

...


code:
Actions Semi S700 Pin Controller

This binding describes the pin controller found in the S700 SoC.

Required Properties:

- compatible:   Should be "actions,s700-pinctrl"
- reg:          Should contain the register base address and size of
		the pin controller.
- clocks:       phandle of the clock feeding the pin controller
- gpio-controller: Marks the device node as a GPIO controller.
- gpio-ranges: Specifies the mapping between gpio controller and
               pin-controller pins.
- #gpio-cells: Should be two. The first cell is the gpio pin number
		and the second cell is used for optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
		interrupt.  Shall be set to 2.  The first cell
		defines the interrupt number, the second encodes
		the trigger flags described in
		bindings/interrupt-controller/interrupts.txt
- interrupts: The interrupt outputs from the controller. There is one GPIO
              interrupt per GPIO bank. The number of interrupts listed depends
              on the number of GPIO banks on the SoC. The interrupts must be
              ordered by bank, starting with bank 0.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.

PIN CONFIGURATION NODES:

The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.

Pinmux functions are available only for the pin groups while pinconf
parameters are available for both pin groups and individual pins.

The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:

Required Properties:

- pins:		An array of strings, each string containing the name of a pin.
		These pins are used for selecting the pull control and schmitt
		trigger parameters. The following are the list of pins
		available:

		eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer,
		eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk,
		eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
		i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
		pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2,
		ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp,
		lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap,
		lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
		lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18,
		lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn,
		dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2,
		sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk,
		sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx,
		uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx,
		uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk,
		i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1,
		csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
		sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2,
		dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb,
		dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0,
		dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2,
		dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3

- groups:       An array of strings, each string containing the name of a pin
                group. These pin groups are used for selecting the pinmux
                functions.
		rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp,
		rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp,
		rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp,
		i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp,
		i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp,
		ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
		dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp,
		lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp,
		dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp,
		uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp,
		sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
		uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp,
		i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp,
		pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp,
		nand_ceb2_mfp, nand_ceb3_mfp

		These pin groups are used for selecting the drive strength
		parameters.

		sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv,
		rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv,
		smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv,
		pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv,
		dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv,
		uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv,
		sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv

- function:	An array of strings, each string containing the name of the
		pinmux functions. These functions can only be selected by
		the corresponding pin groups. The following are the list of
		pinmux functions available:

		nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1,
		uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
		pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0,
		sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30,
		clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0

Optional Properties:

- bias-pull-down: No arguments. The specified pins should be configured as
		pull down.
- bias-pull-up:   No arguments. The specified pins should be configured as
		pull up.
- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
		pins
- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
		pins
- drive-strength: Integer. Selects the drive strength for the specified
		pins in mA.
		Valid values are:
		<2>
		<4>
		<8>
		<12>

Example:

	pinctrl: pinctrl@e01b0000 {
		compatible = "actions,s700-pinctrl";
		reg = <0x0 0xe01b0000 0x0 0x1000>;
		clocks = <&cmu CLK_GPIO>;
		gpio-controller;
		gpio-ranges = <&pinctrl 0 0 136>;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

		uart3-default: uart3-default {
			pinmux {
				groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp";
				function = "uart3";
			};
			pinconf {
				groups = "uart3_all_drv";
				drive-strength = <2>;
			};
		};
	};


code:
Actions Semi S900 Pin Controller

This binding describes the pin controller found in the S900 SoC.

Required Properties:

- compatible:   Should be "actions,s900-pinctrl"
- reg:          Should contain the register base address and size of
                the pin controller.
- clocks:       phandle of the clock feeding the pin controller
- gpio-controller: Marks the device node as a GPIO controller.
- gpio-ranges: Specifies the mapping between gpio controller and
               pin-controller pins.
- #gpio-cells: Should be two. The first cell is the gpio pin number
               and the second cell is used for optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
                    interrupt.  Shall be set to 2.  The first cell
                    defines the interrupt number, the second encodes
                    the trigger flags described in
                    bindings/interrupt-controller/interrupts.txt
- interrupts: The interrupt outputs from the controller. There is one GPIO
              interrupt per GPIO bank. The number of interrupts listed depends
              on the number of GPIO banks on the SoC. The interrupts must be
              ordered by bank, starting with bank 0.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.

PIN CONFIGURATION NODES:

The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.

Pinmux functions are available only for the pin groups while pinconf
parameters are available for both pin groups and individual pins.

The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:

Required Properties:

- pins:           An array of strings, each string containing the name of a pin.
                  These pins are used for selecting the pull control and schmitt
                  trigger parameters. The following are the list of pins
                  available:

                  eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv,
                  eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio,
                  sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0,
                  i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
                  pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5,
                  eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11,
                  lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
                  lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan,
                  lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
                  lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean,
                  sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1,
                  sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
                  spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
                  uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb,
                  uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx,
                  uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata,
                  i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1,
                  csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3,
                  csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp,
                  dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk,
                  csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp,
                  sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3,
                  nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs,
                  nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1,
                  nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2,
                  nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs,
                  nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1,
                  nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3

- groups:         An array of strings, each string containing the name of a pin
                  group. These pin groups are used for selecting the pinmux
                  functions.

                  lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp,
                  sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp,
                  rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp,
                  rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp,
                  i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp,
                  pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp,
                  eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp,
                  eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp,
                  lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp,
                  spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
                  uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
                  sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp,
                  uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp,
                  csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp,
                  dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp,
                  nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp,
                  csi1_dn0_dp0_mfp, uart4_rx_tx_mfp

                  These pin groups are used for selecting the drive strength
                  parameters.

                  sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv,
                  rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv,
                  rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv,
                  sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv,
                  i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv,
                  lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv,
                  sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv,
                  spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv,
                  uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv

                  These pin groups are used for selecting the slew rate
                  parameters.

                  sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr,
                  rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr,
                  rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr,
                  i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr,
                  pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr,
                  spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr,
                  uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr,
                  sensor0_sr

- function:       An array of strings, each string containing the name of the
                  pinmux functions. These functions can only be selected by
                  the corresponding pin groups. The following are the list of
                  pinmux functions available:

                  eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
                  uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
                  pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0,
                  sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds,
                  usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0,
                  nand1, spdif, sirq0, sirq1, sirq2

Optional Properties:

- bias-bus-hold:  No arguments. The specified pins should retain the previous
                  state value.
- bias-high-impedance: No arguments. The specified pins should be configured
                  as high impedance.
- bias-pull-down: No arguments. The specified pins should be configured as
                  pull down.
- bias-pull-up:   No arguments. The specified pins should be configured as
                  pull up.
- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
                  pins
- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
                  pins
- slew-rate:      Integer. Sets slew rate for the specified pins.
                  Valid values are:
                  <0>  - Slow
                  <1>  - Fast
- drive-strength: Integer. Selects the drive strength for the specified
                  pins in mA.
                  Valid values are:
                  <2>
                  <4>
                  <8>
                  <12>

Example:

          pinctrl: pinctrl@e01b0000 {
                  compatible = "actions,s900-pinctrl";
                  reg = <0x0 0xe01b0000 0x0 0x1000>;
                  clocks = <&cmu CLK_GPIO>;
                  gpio-controller;
                  gpio-ranges = <&pinctrl 0 0 146>;
                  #gpio-cells = <2>;
                  interrupt-controller;
                  #interrupt-cells = <2>;
                  interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
                               <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

                  uart2-default: uart2-default {
                          pinmux {
                                  groups = "lvds_oep_odn_mfp";
                                  function = "uart2";
                          };
                          pinconf {
                                  groups = "lvds_oep_odn_drv";
                                  drive-strength = <12>;
                          };
                  };
          };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 Pin Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#gpio-cells":
    const: 3
    description:
      GPIO consumers must use three arguments, first the number of the
      bank, then the pin number inside that bank, and finally the GPIO
      flags.

  "#interrupt-cells":
    const: 3
    description:
      Interrupts consumers must use three arguments, first the number
      of the bank, then the pin number inside that bank, and finally
      the interrupts flags.

  compatible:
    enum:
      - allwinner,sun4i-a10-pinctrl
      - allwinner,sun5i-a10s-pinctrl
      - allwinner,sun5i-a13-pinctrl
      - allwinner,sun6i-a31-pinctrl
      - allwinner,sun6i-a31-r-pinctrl
      - allwinner,sun6i-a31s-pinctrl
      - allwinner,sun7i-a20-pinctrl
      - allwinner,sun8i-a23-pinctrl
      - allwinner,sun8i-a23-r-pinctrl
      - allwinner,sun8i-a33-pinctrl
      - allwinner,sun8i-a83t-pinctrl
      - allwinner,sun8i-a83t-r-pinctrl
      - allwinner,sun8i-h3-pinctrl
      - allwinner,sun8i-h3-r-pinctrl
      - allwinner,sun8i-r40-pinctrl
      - allwinner,sun8i-v3-pinctrl
      - allwinner,sun8i-v3s-pinctrl
      - allwinner,sun9i-a80-pinctrl
      - allwinner,sun9i-a80-r-pinctrl
      - allwinner,sun20i-d1-pinctrl
      - allwinner,sun50i-a64-pinctrl
      - allwinner,sun50i-a64-r-pinctrl
      - allwinner,sun50i-a100-pinctrl
      - allwinner,sun50i-a100-r-pinctrl
      - allwinner,sun50i-h5-pinctrl
      - allwinner,sun50i-h6-pinctrl
      - allwinner,sun50i-h6-r-pinctrl
      - allwinner,sun50i-h616-pinctrl
      - allwinner,sun50i-h616-r-pinctrl
      - allwinner,suniv-f1c100s-pinctrl
      - nextthing,gr8-pinctrl

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 8
    description:
      One interrupt per external interrupt bank supported on the
      controller, sorted by bank number ascending order.

  clocks:
    items:
      - description: Bus Clock
      - description: High Frequency Oscillator
      - description: Low Frequency Oscillator

  clock-names:
    items:
      - const: apb
      - const: hosc
      - const: losc

  gpio-controller: true
  interrupt-controller: true
  gpio-line-names: true

  input-debounce:
    description:
      Debouncing periods in microseconds, one period per interrupt
      bank found in the controller
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 8

patternProperties:
  # It's pretty scary, but the basic idea is that:
  #   - One node name can start with either s- or r- for PRCM nodes,
  #   - Then, the name itself can be any repetition of <string>- (to
  #     accomodate with nodes like uart4-rts-cts-pins), where each
  #     string can be either starting with 'p' but in a string longer
  #     than 3, or something that doesn't start with 'p',
  #   - Then, the bank name is optional and will be between pa and pg,
  #     pl or pm. Some pins groups that have several options will have
  #     the pin numbers then,
  #   - Finally, the name will end with either -pin or pins.

  "^([rs]-)?(([a-z0-9]{3,}|[a-oq-z][a-z0-9]*?)?-)+?(p[a-ilm][0-9]*?-)??pins?$":
    type: object

    properties:
      pins: true
      function: true
      bias-disable: true
      bias-pull-up: true
      bias-pull-down: true

      drive-strength:
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [10, 20, 30, 40]

    required:
      - pins
      - function

    additionalProperties: false

  "^vcc-p[a-ilm]-supply$":
    description:
      Power supplies for pin banks.

required:
  - "#gpio-cells"
  - compatible
  - reg
  - clocks
  - clock-names
  - gpio-controller

allOf:
  # FIXME: We should have the pin bank supplies here, but not a lot of
  # boards are defining it at the moment so it would generate a lot of
  # warnings.

  - $ref: "pinctrl.yaml#"
  - if:
      not:
        properties:
          compatible:
            enum:
              - allwinner,sun50i-h616-r-pinctrl

    then:
      required:
        - "#interrupt-cells"
        - interrupts
        - interrupt-controller

  - if:
      properties:
        compatible:
          enum:
            - allwinner,sun50i-h616-pinctrl

    then:
      properties:
        interrupts:
          minItems: 8

  - if:
      properties:
        compatible:
          enum:
            - allwinner,sun50i-a100-pinctrl

    then:
      properties:
        interrupts:
          minItems: 7
          maxItems: 7

  - if:
      properties:
        compatible:
          enum:
            - allwinner,sun20i-d1-pinctrl

    then:
      properties:
        interrupts:
          minItems: 6
          maxItems: 6

  - if:
      properties:
        compatible:
          enum:
            - allwinner,sun9i-a80-pinctrl

    then:
      properties:
        interrupts:
          minItems: 5
          maxItems: 5

  - if:
      properties:
        compatible:
          enum:
            - allwinner,sun6i-a31-pinctrl
            - allwinner,sun6i-a31s-pinctrl
            - allwinner,sun50i-h6-pinctrl

    then:
      properties:
        interrupts:
          minItems: 4
          maxItems: 4

  - if:
      properties:
        compatible:
          enum:
            - allwinner,sun8i-a23-pinctrl
            - allwinner,sun8i-a83t-pinctrl
            - allwinner,sun50i-a64-pinctrl
            - allwinner,sun50i-h5-pinctrl
            - allwinner,suniv-f1c100s-pinctrl

    then:
      properties:
        interrupts:
          minItems: 3
          maxItems: 3

  - if:
      properties:
        compatible:
          enum:
            - allwinner,sun6i-a31-r-pinctrl
            - allwinner,sun8i-a33-pinctrl
            - allwinner,sun8i-h3-pinctrl
            - allwinner,sun8i-v3-pinctrl
            - allwinner,sun8i-v3s-pinctrl
            - allwinner,sun9i-a80-r-pinctrl
            - allwinner,sun50i-h6-r-pinctrl

    then:
      properties:
        interrupts:
          minItems: 2
          maxItems: 2

  - if:
      properties:
        compatible:
          enum:
            - allwinner,sun4i-a10-pinctrl
            - allwinner,sun5i-a10s-pinctrl
            - allwinner,sun5i-a13-pinctrl
            - allwinner,sun7i-a20-pinctrl
            - allwinner,sun8i-a23-r-pinctrl
            - allwinner,sun8i-a83t-r-pinctrl
            - allwinner,sun8i-h3-r-pinctrl
            - allwinner,sun8i-r40-pinctrl
            - allwinner,sun50i-a64-r-pinctrl
            - allwinner,sun50i-a100-r-pinctrl
            - nextthing,gr8-pinctrl

    then:
      properties:
        interrupts:
          minItems: 1
          maxItems: 1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/sun5i-ccu.h>

    pio: pinctrl@1c20800 {
        compatible = "allwinner,sun5i-a13-pinctrl";
        reg = <0x01c20800 0x400>;
        interrupts = <28>;
        clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
        clock-names = "apb", "hosc", "losc";
        gpio-controller;
        interrupt-controller;
        #interrupt-cells = <3>;
        #gpio-cells = <3>;

        uart1_pe_pins: uart1-pe-pins {
            pins = "PE10", "PE11";
            function = "uart1";
        };

        uart1_pg_pins: uart1-pg-pins {
            pins = "PG3", "PG4";
            function = "uart1";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/apple,pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple GPIO controller

maintainers:
  - Mark Kettenis <kettenis@openbsd.org>

description: |
  The Apple GPIO controller is a simple combined pin and GPIO
  controller present on Apple ARM SoC platforms, including various
  iPhone and iPad devices and the "Apple Silicon" Macs.

properties:
  compatible:
    items:
      - enum:
          - apple,t8103-pinctrl
          - apple,t6000-pinctrl
      - const: apple,pinctrl

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2

  gpio-ranges:
    maxItems: 1

  apple,npins:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The number of pins in this GPIO controller.

  interrupts:
    description: One interrupt for each of the (up to 7) interrupt
      groups supported by the controller sorted by interrupt group
      number in ascending order.
    minItems: 1
    maxItems: 7

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  power-domains:
    maxItems: 1

patternProperties:
  '-pins$':
    type: object
    $ref: pinmux-node.yaml#

    properties:
      pinmux:
        description:
          Values are constructed from pin number and alternate function
          configuration number using the APPLE_PINMUX() helper macro
          defined in include/dt-bindings/pinctrl/apple.h.

    required:
      - pinmux

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges
  - apple,npins

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/apple-aic.h>
    #include <dt-bindings/pinctrl/apple.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      pinctrl: pinctrl@23c100000 {
        compatible = "apple,t8103-pinctrl", "apple,pinctrl";
        reg = <0x2 0x3c100000 0x0 0x100000>;
        clocks = <&gpio_clk>;

        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&pinctrl 0 0 212>;
        apple,npins = <212>;

        interrupt-controller;
        #interrupt-cells = <2>;
        interrupt-parent = <&aic>;
        interrupts = <AIC_IRQ 16 IRQ_TYPE_LEVEL_HIGH>,
                     <AIC_IRQ 17 IRQ_TYPE_LEVEL_HIGH>,
                     <AIC_IRQ 18 IRQ_TYPE_LEVEL_HIGH>,
                     <AIC_IRQ 19 IRQ_TYPE_LEVEL_HIGH>,
                     <AIC_IRQ 20 IRQ_TYPE_LEVEL_HIGH>,
                     <AIC_IRQ 21 IRQ_TYPE_LEVEL_HIGH>,
                     <AIC_IRQ 22 IRQ_TYPE_LEVEL_HIGH>;

        pcie_pins: pcie-pins {
          pinmux = <APPLE_PINMUX(150, 1)>,
                   <APPLE_PINMUX(151, 1)>,
                   <APPLE_PINMUX(32, 1)>;
        };
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-or-later
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2400-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED AST2400 Pin Controller

maintainers:
  - Andrew Jeffery <andrew@aj.id.au>

description: |+
  The pin controller node should be the child of a syscon node with the
  required property:

  - compatible:     Should be one of the following:
                    "aspeed,ast2400-scu", "syscon", "simple-mfd"

  Refer to the bindings described in
  Documentation/devicetree/bindings/mfd/syscon.yaml

properties:
  compatible:
    const: aspeed,ast2400-pinctrl
  reg:
    maxItems: 2

patternProperties:
  '^.*$':
    if:
      type: object
    then:
      patternProperties:
        "^function|groups$":
          $ref: "/schemas/types.yaml#/definitions/string"
          enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
                  ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
                  EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0,
                  GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4,
                  I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK,
                  MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2,
                  NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4,
                  NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0,
                  PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
                  RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3,
                  RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD,
                  SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO,
                  SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU,
                  SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2,
                  TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM,
                  VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2]

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible

additionalProperties: false

examples:
  - |
    syscon: scu@1e6e2000 {
        compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
        reg = <0x1e6e2000 0x1a8>;
        #clock-cells = <1>;
        #reset-cells = <1>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x1e6e2000 0x1000>;

        pinctrl: pinctrl {
            compatible = "aspeed,ast2400-pinctrl";

            pinctrl_i2c3_default: i2c3_default {
                function = "I2C3";
                groups = "I2C3";
            };

            pinctrl_gpioh0_unbiased_default: gpioh0 {
                pins = "A8";
                bias-disable;
            };
        };
    };