code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for NXP Layerscape-1012A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2019-2020 NXP
 *
 */

#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "fsl,ls1012a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		crypto = &crypto;
		rtc1 = &ftm_alarm0;
		rtic-a = &rtic_a;
		rtic-b = &rtic_b;
		rtic-c = &rtic_c;
		rtic-d = &rtic_d;
		sec-mon = &sec_mon;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			#cooling-cells = <2>;
			cpu-idle-states = <&CPU_PH20>;
		};
	};

	idle-states {
		/*
		 * PSCI node is not added default, U-boot will add missing
		 * parts if it determines to use PSCI.
		 */
		entry-method = "psci";

		CPU_PH20: cpu-ph20 {
			compatible = "arm,idle-state";
			idle-state-name = "PH20";
			arm,psci-suspend-param = <0x0>;
			entry-latency-us = <1000>;
			exit-latency-us = <1000>;
			min-residency-us = <3000>;
		};
	};

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
		clock-output-names = "sysclk";
	};

	coreclk: coreclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "coreclk";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
			     <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
			     <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
			     <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
	};

	gic: interrupt-controller@1400000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
		      <0x0 0x1402000 0 0x2000>, /* GICC */
		      <0x0 0x1404000 0 0x2000>, /* GICH */
		      <0x0 0x1406000 0 0x2000>; /* GICV */
		interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
	};

	reboot {
		compatible = "syscon-reboot";
		regmap = <&dcfg>;
		offset = <0xb0>;
		mask = <0x02>;
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 0>;

			trips {
				cpu_alert: cpu-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		qspi: spi@1550000 {
			compatible = "fsl,ls1021a-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x1550000 0x0 0x10000>,
				<0x0 0x40000000 0x0 0x10000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "qspi_en", "qspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			status = "disabled";
		};

		esdhc0: esdhc@1560000 {
			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
			reg = <0x0 0x1560000 0x0 0x10000>;
			interrupts = <0 62 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			big-endian;
			bus-width = <4>;
			status = "disabled";
		};

		scfg: scfg@1570000 {
			compatible = "fsl,ls1012a-scfg", "syscon";
			reg = <0x0 0x1570000 0x0 0x10000>;
			big-endian;
		};

		esdhc1: esdhc@1580000 {
			compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
			reg = <0x0 0x1580000 0x0 0x10000>;
			interrupts = <0 65 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			big-endian;
			broken-cd;
			bus-width = <4>;
			status = "disabled";
		};

		crypto: crypto@1700000 {
			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
				     "fsl,sec-v4.0";
			fsl,sec-era = <8>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x00 0x1700000 0x100000>;
			reg = <0x00 0x1700000 0x0 0x100000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			dma-coherent;

			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x10000 0x10000>;
				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x20000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x30000 0x10000>;
				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x40000 0x10000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			};

			rtic@60000 {
				compatible = "fsl,sec-v5.4-rtic",
					     "fsl,sec-v5.0-rtic",
					     "fsl,sec-v4.0-rtic";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x60000 0x100>, <0x60e00 0x18>;
				ranges = <0x0 0x60100 0x500>;

				rtic_a: rtic-a@0 {
					compatible = "fsl,sec-v5.4-rtic-memory",
						     "fsl,sec-v5.0-rtic-memory",
						     "fsl,sec-v4.0-rtic-memory";
					reg = <0x00 0x20>, <0x100 0x100>;
				};

				rtic_b: rtic-b@20 {
					compatible = "fsl,sec-v5.4-rtic-memory",
						     "fsl,sec-v5.0-rtic-memory",
						     "fsl,sec-v4.0-rtic-memory";
					reg = <0x20 0x20>, <0x200 0x100>;
				};

				rtic_c: rtic-c@40 {
					compatible = "fsl,sec-v5.4-rtic-memory",
						     "fsl,sec-v5.0-rtic-memory",
						     "fsl,sec-v4.0-rtic-memory";
					reg = <0x40 0x20>, <0x300 0x100>;
				};

				rtic_d: rtic-d@60 {
					compatible = "fsl,sec-v5.4-rtic-memory",
						     "fsl,sec-v5.0-rtic-memory",
						     "fsl,sec-v4.0-rtic-memory";
					reg = <0x60 0x20>, <0x400 0x100>;
				};
			};
		};

		sfp: efuse@1e80000 {
			compatible = "fsl,ls1021a-sfp";
			reg = <0x0 0x1e80000 0x0 0x10000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "sfp";
		};

		sec_mon: sec_mon@1e90000 {
			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
				     "fsl,sec-v4.0-mon";
			reg = <0x0 0x1e90000 0x0 0x10000>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		};

		dcfg: dcfg@1ee0000 {
			compatible = "fsl,ls1012a-dcfg",
				     "syscon";
			reg = <0x0 0x1ee0000 0x0 0x10000>;
			big-endian;
		};

		clockgen: clocking@1ee1000 {
			compatible = "fsl,ls1012a-clockgen";
			reg = <0x0 0x1ee1000 0x0 0x1000>;
			#clock-cells = <2>;
			clocks = <&sysclk &coreclk>;
			clock-names = "sysclk", "coreclk";
		};

		tmu: tmu@1f00000 {
			compatible = "fsl,qoriq-tmu";
			reg = <0x0 0x1f00000 0x0 0x10000>;
			interrupts = <0 33 0x4>;
			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>;
			fsl,tmu-calibration = <0x00000000 0x00000025
					       0x00000001 0x0000002c
					       0x00000002 0x00000032
					       0x00000003 0x00000039
					       0x00000004 0x0000003f
					       0x00000005 0x00000046
					       0x00000006 0x0000004c
					       0x00000007 0x00000053
					       0x00000008 0x00000059
					       0x00000009 0x0000005f
					       0x0000000a 0x00000066
					       0x0000000b 0x0000006c

					       0x00010000 0x00000026
					       0x00010001 0x0000002d
					       0x00010002 0x00000035
					       0x00010003 0x0000003d
					       0x00010004 0x00000045
					       0x00010005 0x0000004d
					       0x00010006 0x00000055
					       0x00010007 0x0000005d
					       0x00010008 0x00000065
					       0x00010009 0x0000006d

					       0x00020000 0x00000026
					       0x00020001 0x00000030
					       0x00020002 0x0000003a
					       0x00020003 0x00000044
					       0x00020004 0x0000004e
					       0x00020005 0x00000059
					       0x00020006 0x00000063

					       0x00030000 0x00000014
					       0x00030001 0x00000021
					       0x00030002 0x0000002e
					       0x00030003 0x0000003a
					       0x00030004 0x00000047
					       0x00030005 0x00000053
					       0x00030006 0x00000060>;
			big-endian;
			#thermal-sensor-cells = <1>;
		};

		i2c0: i2c@2180000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			status = "disabled";
		};

		i2c1: i2c@2190000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			status = "disabled";
		};

		dspi: spi@2100000 {
			compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0500 0x0 0x100>;
			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			status = "disabled";
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0600 0x0 0x100>;
			interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			status = "disabled";
		};

		gpio0: gpio@2300000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@2310000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		wdog0: watchdog@2ad0000 {
			compatible = "fsl,ls1012a-wdt",
				     "fsl,imx21-wdt";
			reg = <0x0 0x2ad0000 0x0 0x10000>;
			interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>;
			big-endian;
		};

		sai1: sai@2b50000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0x2b50000 0x0 0x10000>;
			interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 47>,
			       <&edma0 1 46>;
			status = "disabled";
		};

		sai2: sai@2b60000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0x2b60000 0x0 0x10000>;
			interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 45>,
			       <&edma0 1 44>;
			status = "disabled";
		};

		edma0: dma-controller@2c00000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x2c00000 0x0 0x10000>,
			      <0x0 0x2c10000 0x0 0x10000>,
			      <0x0 0x2c20000 0x0 0x10000>;
			interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
				     <0 103 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			big-endian;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
		};

		usb0: usb@2f00000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x2f00000 0x0 0x10000>;
			interrupts = <0 60 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
			snps,dis_rxdet_inp3_quirk;
			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
		};

		sata: sata@3200000 {
			compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
			reg = <0x0 0x3200000 0x0 0x10000>,
				<0x0 0x20140520 0x0 0x4>;
			reg-names = "ahci", "sata-ecc";
			interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			dma-coherent;
			status = "disabled";
		};

		usb1: usb@8600000 {
			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
			reg = <0x0 0x8600000 0x0 0x1000>;
			interrupts = <0 139 0x4>;
			dr_mode = "host";
			phy_type = "ulpi";
		};

		msi: msi-controller1@1572000 {
			compatible = "fsl,ls1012a-msi";
			reg = <0x0 0x1572000 0x0 0x8>;
			msi-controller;
			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
		};

		pcie1: pcie@3400000 {
			compatible = "fsl,ls1012a-pcie";
			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
			      <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 118 0x4>, /* controller interrupt */
				     <0 117 0x4>; /* PME interrupt */
			interrupt-names = "aer", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-viewport = <2>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		rcpm: power-controller@1ee2140 {
			compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
			reg = <0x0 0x1ee2140 0x0 0x4>;
			#fsl,rcpm-wakeup-cells = <1>;
		};

		ftm_alarm0: timer@29d0000 {
			compatible = "fsl,ls1012a-ftm-alarm";
			reg = <0x0 0x29d0000 0x0 0x10000>;
			fsl,rcpm-wakeup = <&rcpm 0x20000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
		};
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Device Tree File for the Kontron KBox A-230-LS.
 *
 * This consists of a Kontron SMARC-sAL28 (Dual PHY) and a special
 * carrier (s1914).
 *
 * Copyright (C) 2019 Michael Walle <michael@walle.cc>
 *
 */

/dts-v1/;
#include "fsl-ls1028a-kontron-sl28-var4.dts"
#include <dt-bindings/leds/common.h>

/ {
	model = "Kontron KBox A-230-LS";
	compatible = "kontron,kbox-a-230-ls", "kontron,sl28-var4",
		     "kontron,sl28", "fsl,ls1028a";

	leds {
		compatible = "gpio-leds";

		alarm-led {
			function = LED_FUNCTION_ALARM;
			color = <LED_COLOR_ID_YELLOW>;
			gpios = <&sl28cpld_gpio0 0 GPIO_ACTIVE_HIGH>;
		};

		power-led {
			linux,default-trigger = "default-on";
			function = LED_FUNCTION_POWER;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&sl28cpld_gpio1 3 GPIO_ACTIVE_HIGH>;
		};
	};
};

&enetc_mdio_pf3 {
	/* BCM54140 QSGMII quad PHY */
	qsgmii_phy0: ethernet-phy@7 {
		reg = <7>;
	};

	qsgmii_phy1: ethernet-phy@8 {
		reg = <8>;
	};

	qsgmii_phy2: ethernet-phy@9 {
		reg = <9>;
	};

	qsgmii_phy3: ethernet-phy@10 {
		reg = <10>;
	};
};

&enetc_port2 {
	status = "okay";
};

&enetc_port3 {
	status = "okay";
};

&i2c3 {
	eeprom@57 {
		compatible = "atmel,24c32";
		reg = <0x57>;
		pagesize = <32>;
	};
};

&mscc_felix {
	status = "okay";
};

&mscc_felix_port0 {
	label = "swp0";
	managed = "in-band-status";
	phy-handle = <&qsgmii_phy0>;
	phy-mode = "qsgmii";
	status = "okay";
};

&mscc_felix_port1 {
	label = "swp1";
	managed = "in-band-status";
	phy-handle = <&qsgmii_phy1>;
	phy-mode = "qsgmii";
	status = "okay";
};

&mscc_felix_port2 {
	label = "swp2";
	managed = "in-band-status";
	phy-handle = <&qsgmii_phy2>;
	phy-mode = "qsgmii";
	status = "okay";
};

&mscc_felix_port3 {
	label = "swp3";
	managed = "in-band-status";
	phy-handle = <&qsgmii_phy3>;
	phy-mode = "qsgmii";
	status = "okay";
};

&mscc_felix_port4 {
	status = "okay";
};

&mscc_felix_port5 {
	status = "okay";
};

&sata {
	status = "okay";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Device Tree file for the Kontron SMARC-sAL28 board.
 *
 * This is for the network variant 1 which has one ethernet port. It is
 * different than the base variant, which also has one port, but here the
 * port is connected via RGMII. This port is not TSN aware.
 * None of the  four SerDes lanes are used by the module, instead they are
 * all led out to the carrier for customer use.
 *
 * Copyright (C) 2021 Michael Walle <michael@walle.cc>
 *
 */

/dts-v1/;
#include "fsl-ls1028a-kontron-sl28.dts"
#include <dt-bindings/net/qca-ar803x.h>

/ {
	model = "Kontron SMARC-sAL28 (4 Lanes)";
	compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
};

&enetc_mdio_pf3 {
	/* Delete unused phy node */
	/delete-node/ ethernet-phy@5;

	phy0: ethernet-phy@4 {
		reg = <0x4>;
		eee-broken-1000t;
		eee-broken-100tx;
		qca,clk-out-frequency = <125000000>;
		qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
		qca,keep-pll-enabled;
		vddio-supply = <&vddio>;

		vddio: vddio-regulator {
			regulator-name = "VDDIO";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};

		vddh: vddh-regulator {
			regulator-name = "VDDH";
		};
	};
};

&enetc_port0 {
	status = "disabled";
	/* Delete the phy-handle to the old phy0 label */
	/delete-property/ phy-handle;
};

&enetc_port1 {
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Device Tree file for the Kontron SMARC-sAL28 board.
 *
 * This is for the network variant 2 which has two ethernet ports. These
 * ports are connected to the internal switch.
 *
 * Copyright (C) 2021 Michael Walle <michael@walle.cc>
 *
 */

/dts-v1/;
#include "fsl-ls1028a-kontron-sl28.dts"

/ {
	model = "Kontron SMARC-sAL28 (TSN-on-module)";
	compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a";
};

&enetc_mdio_pf3 {
	phy1: ethernet-phy@4 {
		reg = <0x4>;
		eee-broken-1000t;
		eee-broken-100tx;
	};
};

&enetc_port0 {
	status = "disabled";
	/*
	 * In the base device tree the PHY at address 5 was assigned for
	 * this port. On this module this PHY is connected to a switch
	 * port instead. Therefore, delete the phy-handle property here.
	 */
	/delete-property/ phy-handle;
};

&enetc_port2 {
	status = "okay";
};

&enetc_port3 {
	status = "okay";
};

&mscc_felix {
	status = "okay";
};

&mscc_felix_port0 {
	label = "swp0";
	managed = "in-band-status";
	phy-handle = <&phy0>;
	phy-mode = "sgmii";
	status = "okay";
};

&mscc_felix_port1 {
	label = "swp1";
	managed = "in-band-status";
	phy-handle = <&phy1>;
	phy-mode = "sgmii";
	status = "okay";
};

&mscc_felix_port4 {
	status = "okay";
};

&mscc_felix_port5 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Device Tree file for the Kontron SMARC-sAL28 board on a SMARC Eval 2.0
 * carrier (ADS2).
 *
 * Copyright (C) 2019 Michael Walle <michael@walle.cc>
 *
 */

/dts-v1/;

#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include "fsl-ls1028a-kontron-sl28.dts"

/ {
	model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier";
	compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3",
		     "kontron,sl28", "fsl,ls1028a";

	pwm-fan {
		compatible = "pwm-fan";
		cooling-min-state = <0>;
		cooling-max-state = <3>;
		#cooling-cells = <2>;
		pwms = <&sl28cpld_pwm0 0 4000000>;
		cooling-levels = <1 128 192 255>;
	};

	sound {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "simple-audio-card";
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Line", "Line Out Jack",
			"Microphone", "Microphone Jack",
			"Line", "Line In Jack";
		simple-audio-card,routing =
			"Line Out Jack", "LINEOUTR",
			"Line Out Jack", "LINEOUTL",
			"Headphone Jack", "HPOUTR",
			"Headphone Jack", "HPOUTL",
			"IN1L", "Line In Jack",
			"IN1R", "Line In Jack",
			"Microphone Jack", "MICBIAS",
			"IN2L", "Microphone Jack",
			"IN2R", "Microphone Jack";
		simple-audio-card,mclk-fs = <256>;

		simple-audio-card,dai-link@0 {
			reg = <0>;
			bitclock-master = <&dailink0_master>;
			frame-master = <&dailink0_master>;
			format = "i2s";

			cpu {
				sound-dai = <&sai6>;
			};

			dailink0_master: codec {
				sound-dai = <&wm8904>;
			};
		};

		simple-audio-card,dai-link@1 {
			reg = <1>;
			bitclock-master = <&dailink1_master>;
			frame-master = <&dailink1_master>;
			format = "i2s";

			cpu {
				sound-dai = <&sai5>;
			};

			dailink1_master: codec {
				sound-dai = <&wm8904>;
			};
		};
	};
};

&dspi2 {
	flash@0 {
		compatible = "jedec,spi-nor";
		m25p,fast-read;
		spi-max-frequency = <100000000>;
		reg = <0>;
	};
};

&i2c3 {
	eeprom@57 {
		compatible = "atmel,24c64";
		reg = <0x57>;
		pagesize = <32>;
	};
};

&i2c4 {
	status = "okay";

	wm8904: audio-codec@1a {
		#sound-dai-cells = <0>;
		compatible = "wlf,wm8904";
		reg = <0x1a>;
		clocks = <&mclk>;
		clock-names = "mclk";
		assigned-clocks = <&mclk>;
		assigned-clock-rates = <1250000>;
	};
};

&sai5 {
	status = "okay";
};

&sai6 {
	status = "okay";
};

&soc {
	mclk: clock-mclk@f130080 {
		compatible = "fsl,vf610-sai-clock";
		reg = <0x0 0xf130080 0x0 0x80>;
		clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
				    QORIQ_CLK_PLL_DIV(2)>;
		#clock-cells = <0>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Device Tree file for the Kontron SMARC-sAL28 board.
 *
 * This is for the network variant 4 which has two ethernet ports. It
 * extends the base and provides one more port connected via RGMII.
 *
 * Copyright (C) 2021 Michael Walle <michael@walle.cc>
 *
 */

/dts-v1/;
#include "fsl-ls1028a-kontron-sl28.dts"
#include <dt-bindings/net/qca-ar803x.h>

/ {
	model = "Kontron SMARC-sAL28 (Dual PHY)";
	compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
};

&enetc_mdio_pf3 {
	phy1: ethernet-phy@4 {
		reg = <0x4>;
		eee-broken-1000t;
		eee-broken-100tx;
		qca,clk-out-frequency = <125000000>;
		qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
		qca,keep-pll-enabled;
		vddio-supply = <&vddio>;

		vddio: vddio-regulator {
			regulator-name = "VDDIO";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};

		vddh: vddh-regulator {
			regulator-name = "VDDH";
		};
	};
};

&enetc_port1 {
	phy-handle = <&phy1>;
	phy-mode = "rgmii-id";
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Device Tree file for the Kontron SMARC-sAL28 board.
 *
 * Copyright (C) 2021 Michael Walle <michael@walle.cc>
 *
 */

/dts-v1/;
#include "fsl-ls1028a.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "Kontron SMARC-sAL28";
	compatible = "kontron,sl28", "fsl,ls1028a";

	aliases {
		crypto = &crypto;
		serial0 = &duart0;
		serial1 = &duart1;
		serial2 = &lpuart1;
		spi0 = &fspi;
		spi1 = &dspi2;
		mmc0 = &esdhc1;
		mmc1 = &esdhc;
		rtc0 = &rtc;
		rtc1 = &ftm_alarm0;
	};

	buttons0 {
		compatible = "gpio-keys";

		power-button {
			interrupts-extended = <&sl28cpld_intc
					       4 IRQ_TYPE_EDGE_BOTH>;
			linux,code = <KEY_POWER>;
			label = "Power";
		};

		sleep-button {
			interrupts-extended = <&sl28cpld_intc
					       5 IRQ_TYPE_EDGE_BOTH>;
			linux,code = <KEY_SLEEP>;
			label = "Sleep";
		};
	};

	buttons1 {
		compatible = "gpio-keys-polled";
		poll-interval = <200>;

		lid-switch {
			linux,input-type = <EV_SW>;
			linux,code = <SW_LID>;
			gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>;
			label = "Lid";
		};
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&can0 {
	status = "okay";
};

&dspi2 {
	status = "okay";
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&enetc_mdio_pf3 {
	phy0: ethernet-phy@5 {
		reg = <0x5>;
		eee-broken-1000t;
		eee-broken-100tx;
	};
};

&enetc_port0 {
	phy-handle = <&phy0>;
	phy-mode = "sgmii";
	managed = "in-band-status";
	status = "okay";
};

&esdhc {
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
	status = "okay";
};

&esdhc1 {
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
	status = "okay";
};

&fspi {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		m25p,fast-read;
		spi-max-frequency = <133000000>;
		reg = <0>;
		/* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
		spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
		spi-tx-bus-width = <1>; /* 1 SPI Tx line */

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				reg = <0x000000 0x010000>;
				label = "rcw";
				read-only;
			};

			partition@10000 {
				reg = <0x010000 0x1d0000>;
				label = "failsafe bootloader";
				read-only;
			};

			partition@200000 {
				reg = <0x200000 0x010000>;
				label = "configuration store";
			};

			partition@210000 {
				reg = <0x210000 0x1d0000>;
				label = "bootloader";
			};

			partition@3e0000 {
				reg = <0x3e0000 0x020000>;
				label = "bootloader environment";
			};
		};
	};
};

&ftm_alarm0 {
	status = "okay";
};

&gpio1 {
	gpio-line-names =
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "TDO", "TCK",
		"", "", "", "", "", "", "", "";
};

&gpio2 {
	gpio-line-names =
		"", "", "", "", "", "", "TMS", "TDI",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&i2c0 {
	status = "okay";

	rtc: rtc@32 {
		compatible = "microcrystal,rv8803";
		reg = <0x32>;
	};

	sl28cpld@4a {
		compatible = "kontron,sl28cpld";
		reg = <0x4a>;
		#address-cells = <1>;
		#size-cells = <0>;

		watchdog@4 {
			compatible = "kontron,sl28cpld-wdt";
			reg = <0x4>;
			kontron,assert-wdt-timeout-pin;
		};

		hwmon@b {
			compatible = "kontron,sl28cpld-fan";
			reg = <0xb>;
		};

		sl28cpld_pwm0: pwm@c {
			compatible = "kontron,sl28cpld-pwm";
			reg = <0xc>;
			#pwm-cells = <2>;
		};

		sl28cpld_pwm1: pwm@e {
			compatible = "kontron,sl28cpld-pwm";
			reg = <0xe>;
			#pwm-cells = <2>;
		};

		sl28cpld_gpio0: gpio@10 {
			compatible = "kontron,sl28cpld-gpio";
			reg = <0x10>;
			interrupts-extended = <&gpio2 6
					       IRQ_TYPE_EDGE_FALLING>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-line-names =
				"GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N",
				"GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N",
				"GPIO4_HDA_RST_N", "GPIO5_PWM_OUT",
				"GPIO6_TACHIN", "GPIO7";

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sl28cpld_gpio1: gpio@15 {
			compatible = "kontron,sl28cpld-gpio";
			reg = <0x15>;
			interrupts-extended = <&gpio2 6
					       IRQ_TYPE_EDGE_FALLING>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-line-names =
				"GPIO8", "GPIO9", "GPIO10", "GPIO11",
				"", "", "", "";

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sl28cpld_gpio2: gpio@1a {
			compatible = "kontron,sl28cpld-gpo";
			reg = <0x1a>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-line-names =
				"LCD0 voltage enable",
				"LCD0 backlight enable",
				"eMMC reset", "LVDS bridge reset",
				"LVDS bridge power-down",
				"SDIO power enable",
				"", "";
		};

		sl28cpld_gpio3: gpio@1b {
			compatible = "kontron,sl28cpld-gpi";
			reg = <0x1b>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-line-names =
				"Power button", "Force recovery", "Sleep",
				"Battery low", "Lid state", "Charging",
				"Charger present", "";
		};

		sl28cpld_intc: interrupt-controller@1c {
			compatible = "kontron,sl28cpld-intc";
			reg = <0x1c>;
			interrupts-extended = <&gpio2 6
					       IRQ_TYPE_EDGE_FALLING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	eeprom@50 {
		compatible = "atmel,24c32";
		reg = <0x50>;
		pagesize = <32>;
	};
};

&i2c3 {
	status = "okay";
};

&i2c4 {
	status = "okay";

	eeprom@50 {
		compatible = "atmel,24c32";
		reg = <0x50>;
		pagesize = <32>;
	};
};

&lpuart1 {
	status = "okay";
};

&mscc_felix_port4 {
	dsa-tag-protocol = "ocelot-8021q";
};

&mscc_felix_port5 {
	dsa-tag-protocol = "ocelot-8021q";
};

&usb0 {
	status = "okay";
};

&usb1 {
	dr_mode = "host";
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree fragment for LS1028A QDS board, serdes 13bb
 *
 * Copyright 2019-2021 NXP
 *
 * Requires a LS1028A QDS board with lane B rework.
 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
 * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
 */

/dts-v1/;
/plugin/;

&mdio_slot1 {
	#address-cells = <1>;
	#size-cells = <0>;

	slot1_sgmii: ethernet-phy@2 {
		/* AQR112 */
		reg = <0x2>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};
};

&enetc_port0 {
	phy-handle = <&slot1_sgmii>;
	phy-mode = "usxgmii";
	managed = "in-band-status";
	status = "okay";
};

&mdio_slot2 {
	#address-cells = <1>;
	#size-cells = <0>;

	/* 4 ports on AQR412 */
	slot2_qxgmii0: ethernet-phy@0 {
		reg = <0x0>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};

	slot2_qxgmii1: ethernet-phy@1 {
		reg = <0x1>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};

	slot2_qxgmii2: ethernet-phy@2 {
		reg = <0x2>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};

	slot2_qxgmii3: ethernet-phy@3 {
		reg = <0x3>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};
};

&mscc_felix_ports {
	port@0 {
		status = "okay";
		phy-handle = <&slot2_qxgmii0>;
		phy-mode = "usxgmii";
		managed = "in-band-status";
	};

	port@1 {
		status = "okay";
		phy-handle = <&slot2_qxgmii1>;
		phy-mode = "usxgmii";
		managed = "in-band-status";
	};

	port@2 {
		status = "okay";
		phy-handle = <&slot2_qxgmii2>;
		phy-mode = "usxgmii";
		managed = "in-band-status";
	};

	port@3 {
		status = "okay";
		phy-handle = <&slot2_qxgmii3>;
		phy-mode = "usxgmii";
		managed = "in-band-status";
	};
};

&mscc_felix {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree fragment for LS1028A QDS board, serdes 69xx
 *
 * Copyright 2019-2021 NXP
 *
 * Requires a LS1028A QDS board with lane B rework.
 * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2.
 */

/dts-v1/;
/plugin/;

&mdio_slot1 {
	#address-cells = <1>;
	#size-cells = <0>;

	slot1_sgmii: ethernet-phy@2 {
		/* AQR112 */
		reg = <0x2>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};
};

&enetc_port0 {
	phy-handle = <&slot1_sgmii>;
	phy-mode = "2500base-x";
	status = "okay";
};

&mdio_slot2 {
	#address-cells = <1>;
	#size-cells = <0>;

	/* 4 ports on VSC8514 */
	slot2_qsgmii0: ethernet-phy@8 {
		reg = <0x8>;
	};

	slot2_qsgmii1: ethernet-phy@9 {
		reg = <0x9>;
	};

	slot2_qsgmii2: ethernet-phy@a {
		reg = <0xa>;
	};

	slot2_qsgmii3: ethernet-phy@b {
		reg = <0xb>;
	};
};

&mscc_felix_ports {
	port@0 {
		status = "okay";
		phy-handle = <&slot2_qsgmii0>;
		phy-mode = "qsgmii";
		managed = "in-band-status";
	};

	port@1 {
		status = "okay";
		phy-handle = <&slot2_qsgmii1>;
		phy-mode = "qsgmii";
		managed = "in-band-status";
	};

	port@2 {
		status = "okay";
		phy-handle = <&slot2_qsgmii2>;
		phy-mode = "qsgmii";
		managed = "in-band-status";
	};

	port@3 {
		status = "okay";
		phy-handle = <&slot2_qsgmii3>;
		phy-mode = "qsgmii";
		managed = "in-band-status";
	};
};

&mscc_felix {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree fragment for LS1028A QDS board, serdes 7777
 *
 * Copyright 2019-2021 NXP
 *
 * Requires a LS1028A QDS board without lane B rework.
 * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
 * disabled, plugged in slot 1.
 */

/dts-v1/;
/plugin/;

&mdio_slot1 {
	#address-cells = <1>;
	#size-cells = <0>;

	/* 4 ports on AQR412 */
	slot1_sxgmii0: ethernet-phy@0 {
		reg = <0x0>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};

	slot1_sxgmii1: ethernet-phy@1 {
		reg = <0x1>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};

	slot1_sxgmii2: ethernet-phy@2 {
		reg = <0x2>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};

	slot1_sxgmii3: ethernet-phy@3 {
		reg = <0x3>;
		compatible = "ethernet-phy-ieee802.3-c45";
	};
};

&mscc_felix_ports {
	port@0 {
		status = "okay";
		phy-handle = <&slot1_sxgmii0>;
		phy-mode = "2500base-x";
	};

	port@1 {
		status = "okay";
		phy-handle = <&slot1_sxgmii1>;
		phy-mode = "2500base-x";
	};

	port@2 {
		status = "okay";
		phy-handle = <&slot1_sxgmii2>;
		phy-mode = "2500base-x";
	};

	port@3 {
		status = "okay";
		phy-handle = <&slot1_sxgmii3>;
		phy-mode = "2500base-x";
	};
};

&mscc_felix {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree fragment for LS1028A QDS board, serdes 85bb
 *
 * Copyright 2019-2021 NXP
 *
 * Requires a LS1028A QDS board with lane B rework.
 * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2.
 */

/dts-v1/;
/plugin/;

&mdio_slot1 {
	#address-cells = <1>;
	#size-cells = <0>;

	slot1_sgmii: ethernet-phy@1c {
		/* 1st port on VSC8234 */
		reg = <0x1c>;
	};
};

&enetc_port0 {
	phy-handle = <&slot1_sgmii>;
	phy-mode = "sgmii";
	managed = "in-band-status";
	status = "okay";
};

&mdio_slot2 {
	#address-cells = <1>;
	#size-cells = <0>;

	/* 4 ports on VSC8514 */
	slot2_qsgmii0: ethernet-phy@8 {
		reg = <0x8>;
	};

	slot2_qsgmii1: ethernet-phy@9 {
		reg = <0x9>;
	};

	slot2_qsgmii2: ethernet-phy@a {
		reg = <0xa>;
	};

	slot2_qsgmii3: ethernet-phy@b {
		reg = <0xb>;
	};
};

&mscc_felix_ports {
	port@0 {
		status = "okay";
		phy-handle = <&slot2_qsgmii0>;
		phy-mode = "qsgmii";
		managed = "in-band-status";
	};

	port@1 {
		status = "okay";
		phy-handle = <&slot2_qsgmii1>;
		phy-mode = "qsgmii";
		managed = "in-band-status";
	};

	port@2 {
		status = "okay";
		phy-handle = <&slot2_qsgmii2>;
		phy-mode = "qsgmii";
		managed = "in-band-status";
	};

	port@3 {
		status = "okay";
		phy-handle = <&slot2_qsgmii3>;
		phy-mode = "qsgmii";
		managed = "in-band-status";
	};
};

&mscc_felix {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree fragment for LS1028A QDS board, serdes 85xx
 *
 * Copyright 2019-2021 NXP
 *
 * Requires a LS1028A QDS board without lane B rework.
 * Requires a SCH-24801 card in slot 1.
 */

/dts-v1/;
/plugin/;

&mdio_slot1 {
	#address-cells = <1>;
	#size-cells = <0>;

	/* VSC8234 */
	slot1_sgmii0: ethernet-phy@1c {
		reg = <0x1c>;
	};

	slot1_sgmii1: ethernet-phy@1d {
		reg = <0x1d>;
	};

	slot1_sgmii2: ethernet-phy@1e {
		reg = <0x1e>;
	};

	slot1_sgmii3: ethernet-phy@1f {
		reg = <0x1f>;
	};
};

&enetc_port0 {
	phy-handle = <&slot1_sgmii0>;
	phy-mode = "sgmii";
	managed = "in-band-status";
	status = "okay";
};

&mscc_felix_ports {
	port@1 {
		status = "okay";
		phy-handle = <&slot1_sgmii1>;
		phy-mode = "sgmii";
		managed = "in-band-status";
	};

	port@2 {
		status = "okay";
		phy-handle = <&slot1_sgmii2>;
		phy-mode = "sgmii";
		managed = "in-band-status";
	};
};

&mscc_felix {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree fragment for LS1028A QDS board, serdes 85xx
 *
 * Copyright 2019-2021 NXP
 *
 * Requires a LS1028A QDS board without lane B rework.
 * Requires a SCH-24801 card in slot 1.
 */

/dts-v1/;
/plugin/;

&mdio_slot1 {
	#address-cells = <1>;
	#size-cells = <0>;

	/* VSC8234 */
	slot1_sgmii0: ethernet-phy@1c {
		reg = <0x1c>;
	};

	slot1_sgmii1: ethernet-phy@1d {
		reg = <0x1d>;
	};

	slot1_sgmii2: ethernet-phy@1e {
		reg = <0x1e>;
	};

	slot1_sgmii3: ethernet-phy@1f {
		reg = <0x1f>;
	};
};

&mscc_felix_ports {
	port@0 {
		status = "okay";
		phy-handle = <&slot1_sgmii0>;
		phy-mode = "sgmii";
		managed = "in-band-status";
	};

	port@1 {
		status = "okay";
		phy-handle = <&slot1_sgmii1>;
		phy-mode = "sgmii";
		managed = "in-band-status";
	};

	port@2 {
		status = "okay";
		phy-handle = <&slot1_sgmii2>;
		phy-mode = "sgmii";
		managed = "in-band-status";
	};

	port@3 {
		status = "okay";
		phy-handle = <&slot1_sgmii3>;
		phy-mode = "sgmii";
		managed = "in-band-status";
	};
};

&mscc_felix {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for NXP LS1028A QDS Board.
 *
 * Copyright 2018 NXP
 *
 * Harninder Rai <harninder.rai@nxp.com>
 *
 */

/dts-v1/;

#include "fsl-ls1028a.dtsi"

/ {
	model = "LS1028A QDS Board";
	compatible = "fsl,ls1028a-qds", "fsl,ls1028a";

	aliases {
		crypto = &crypto;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		serial0 = &duart0;
		serial1 = &duart1;
		mmc0 = &esdhc;
		mmc1 = &esdhc1;
		rtc1 = &ftm_alarm1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x1 0x00000000>;
	};

	sys_mclk: clock-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	sb_3v3: regulator-sb3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3v3_vbus";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack",
			"Speaker", "Speaker Ext",
			"Line", "Line In Jack";
		simple-audio-card,routing =
			"MIC_IN", "Microphone Jack",
			"Microphone Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Speaker Ext", "LINE_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai1>;
			frame-master;
			bitclock-master;
		};

		simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
			frame-master;
			bitclock-master;
			system-clock-frequency = <25000000>;
		};
	};

	mdio-mux {
		compatible = "mdio-mux-multiplexer";
		mux-controls = <&mux 0>;
		mdio-parent-bus = <&enetc_mdio_pf3>;
		#address-cells = <1>;
		#size-cells = <0>;

		/* on-board RGMII PHY */
		mdio@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			qds_phy1: ethernet-phy@5 {
				/* Atheros 8035 */
				reg = <5>;
			};
		};

		mdio_slot1: mdio@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
		};

		mdio_slot2: mdio@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
		};

		mdio_slot3: mdio@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
		};

		mdio_slot4: mdio@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <7>;
		};
	};
};

&can0 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&dspi0 {
	bus-num = <0>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <0>;
		spi-max-frequency = <10000000>;
	};

	flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <1>;
		spi-max-frequency = <10000000>;
	};

	flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <2>;
		spi-max-frequency = <10000000>;
	};
};

&dspi1 {
	bus-num = <1>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <0>;
		spi-max-frequency = <10000000>;
	};

	flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <1>;
		spi-max-frequency = <10000000>;
	};

	flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <2>;
		spi-max-frequency = <10000000>;
	};
};

&dspi2 {
	bus-num = <2>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <0>;
		spi-max-frequency = <10000000>;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&enetc_port1 {
	phy-handle = <&qds_phy1>;
	phy-mode = "rgmii-id";
	status = "okay";
};

&enetc_port2 {
	status = "okay";
};

&esdhc {
	status = "okay";
};

&esdhc1 {
	status = "okay";
};

&fspi {
	status = "okay";

	mt35xu02g0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
		spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
		spi-tx-bus-width = <1>; /* 1 SPI Tx line */
		reg = <0>;
	};
};

&ftm_alarm1 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	i2c-mux@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			current-monitor@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};

			current-monitor@41 {
				compatible = "ti,ina220";
				reg = <0x41>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			temperature-sensor@4c {
				compatible = "nxp,sa56004";
				reg = <0x4c>;
				vcc-supply = <&sb_3v3>;
			};

			eeprom@56 {
				compatible = "atmel,24c512";
				reg = <0x56>;
			};

			eeprom@57 {
				compatible = "atmel,24c512";
				reg = <0x57>;
			};
		};

		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x5>;

			sgtl5000: audio-codec@a {
				#sound-dai-cells = <0>;
				compatible = "fsl,sgtl5000";
				reg = <0xa>;
				VDDA-supply = <&reg_1p8v>;
				VDDIO-supply = <&reg_1p8v>;
				clocks = <&sys_mclk>;
			};
		};
	};

	fpga@66 {
		compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
			     "simple-mfd";
		reg = <0x66>;

		mux: mux-controller {
			compatible = "reg-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */
		};
	};

};

&i2c1 {
	status = "okay";

	rtc@51 {
		compatible = "nxp,pcf2129";
		reg = <0x51>;
	};
};

&lpuart0 {
	status = "okay";
};

&lpuart1 {
	status = "okay";
};

&mscc_felix_port4 {
	ethernet = <&enetc_port2>;
	status = "okay";
};

&sai1 {
	status = "okay";
};

&sata {
	status = "okay";
};

&usb0 {
	dr_mode = "host";
	status = "okay";
};

&usb1 {
	dr_mode = "host";
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for NXP LS1028A RDB Board.
 *
 * Copyright 2018-2021 NXP
 *
 * Harninder Rai <harninder.rai@nxp.com>
 *
 */

/dts-v1/;
#include "fsl-ls1028a.dtsi"

/ {
	model = "LS1028A RDB Board";
	compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";

	aliases {
		crypto = &crypto;
		serial0 = &duart0;
		serial1 = &duart1;
		mmc0 = &esdhc;
		mmc1 = &esdhc1;
		rtc1 = &ftm_alarm1;
		spi0 = &fspi;
		ethernet0 = &enetc_port0;
		ethernet1 = &enetc_port2;
		ethernet2 = &mscc_felix_port0;
		ethernet3 = &mscc_felix_port1;
		ethernet4 = &mscc_felix_port2;
		ethernet5 = &mscc_felix_port3;
		ethernet6 = &mscc_felix_port4;
		ethernet7 = &mscc_felix_port5;
		ethernet8 = &enetc_port3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x1 0x0000000>;
	};

	sys_mclk: clock-mclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	sb_3v3: regulator-sb3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3v3_vbus";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack",
			"Speaker", "Speaker Ext",
			"Line", "Line In Jack";
		simple-audio-card,routing =
			"MIC_IN", "Microphone Jack",
			"Microphone Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Speaker Ext", "LINE_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai4>;
			frame-master;
			bitclock-master;
		};

		simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
			frame-master;
			bitclock-master;
			system-clock-frequency = <25000000>;
		};
	};
};

&can0 {
	status = "okay";

	can-transceiver {
		max-bitrate = <5000000>;
	};
};

&can1 {
	status = "okay";

	can-transceiver {
		max-bitrate = <5000000>;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&enetc_mdio_pf3 {
	sgmii_phy0: ethernet-phy@2 {
		reg = <0x2>;
	};

	/* VSC8514 QSGMII quad PHY */
	qsgmii_phy0: ethernet-phy@10 {
		reg = <0x10>;
	};

	qsgmii_phy1: ethernet-phy@11 {
		reg = <0x11>;
	};

	qsgmii_phy2: ethernet-phy@12 {
		reg = <0x12>;
	};

	qsgmii_phy3: ethernet-phy@13 {
		reg = <0x13>;
	};
};

&enetc_port0 {
	phy-handle = <&sgmii_phy0>;
	phy-mode = "sgmii";
	managed = "in-band-status";
	status = "okay";
};

&enetc_port2 {
	status = "okay";
};

&enetc_port3 {
	status = "okay";
};

&esdhc {
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
	status = "okay";
};

&esdhc1 {
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
	status = "okay";
};

&fspi {
	status = "okay";

	mt35xu02g0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
		spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
		spi-tx-bus-width = <1>; /* 1 SPI Tx line */
		reg = <0>;
	};
};

&ftm_alarm1 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	i2c-mux@77 {
		compatible = "nxp,pca9847";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x1>;

			sgtl5000: audio-codec@a {
				#sound-dai-cells = <0>;
				compatible = "fsl,sgtl5000";
				reg = <0xa>;
				VDDA-supply = <&reg_1p8v>;
				VDDIO-supply = <&reg_1p8v>;
				clocks = <&sys_mclk>;
				sclk-strength = <3>;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x02>;

			current-monitor@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <500>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			temperature-sensor@4c {
				compatible = "nxp,sa56004";
				reg = <0x4c>;
				vcc-supply = <&sb_3v3>;
			};

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
			};
		};
	};
};

&mscc_felix {
	status = "okay";
};

&mscc_felix_port0 {
	label = "swp0";
	managed = "in-band-status";
	phy-handle = <&qsgmii_phy0>;
	phy-mode = "qsgmii";
	status = "okay";
};

&mscc_felix_port1 {
	label = "swp1";
	managed = "in-band-status";
	phy-handle = <&qsgmii_phy1>;
	phy-mode = "qsgmii";
	status = "okay";
};

&mscc_felix_port2 {
	label = "swp2";
	managed = "in-band-status";
	phy-handle = <&qsgmii_phy2>;
	phy-mode = "qsgmii";
	status = "okay";
};

&mscc_felix_port3 {
	label = "swp3";
	managed = "in-band-status";
	phy-handle = <&qsgmii_phy3>;
	phy-mode = "qsgmii";
	status = "okay";
};

&mscc_felix_port4 {
	status = "okay";
};

&mscc_felix_port5 {
	status = "okay";
};

&optee {
	status = "okay";
};

&pwm0 {
	status = "okay";
};

&sai4 {
	status = "okay";
};

&sata {
	status = "okay";
};

&usb0 {
	dr_mode = "host";
	status = "okay";
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for NXP Layerscape-1028A family SoC.
 *
 * Copyright 2018-2020 NXP
 *
 * Harninder Rai <harninder.rai@nxp.com>
 *
 */

#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "fsl,ls1028a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0>;
			enable-method = "psci";
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PW20>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x1>;
			enable-method = "psci";
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PW20>;
			#cooling-cells = <2>;
		};

		l2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	idle-states {
		/*
		 * PSCI node is not added default, U-boot will add missing
		 * parts if it determines to use PSCI.
		 */
		entry-method = "psci";

		CPU_PW20: cpu-pw20 {
			  compatible = "arm,idle-state";
			  idle-state-name = "PW20";
			  arm,psci-suspend-param = <0x0>;
			  entry-latency-us = <2000>;
			  exit-latency-us = <2000>;
			  min-residency-us = <6000>;
		};
	};

	rtc_clk: rtc-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "rtc_clk";
	};

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	osc_27m: clock-osc-27m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
		clock-output-names = "phy_27m";
	};

	firmware {
		optee: optee  {
			compatible = "linaro,optee-tz";
			method = "smc";
			status = "disabled";
		};
	};

	reboot {
		compatible = "syscon-reboot";
		regmap = <&rst>;
		offset = <0>;
		mask = <0x02>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	gic: interrupt-controller@6000000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
			<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
					 IRQ_TYPE_LEVEL_LOW)>;
		its: gic-its@6020000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
		};
	};

	thermal-zones {
		ddr-controller {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 0>;

			trips {
				ddr-ctrler-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				ddr-ctrler-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		core-cluster {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 1>;

			trips {
				core_cluster_alert: core-cluster-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				core_cluster_crit: core-cluster-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&core_cluster_alert>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ddr: memory-controller@1080000 {
			compatible = "fsl,qoriq-memory-controller";
			reg = <0x0 0x1080000 0x0 0x1000>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			little-endian;
		};

		dcfg: syscon@1e00000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd";
			reg = <0x0 0x1e00000 0x0 0x10000>;
			ranges = <0x0 0x0 0x1e00000 0x10000>;
			little-endian;

			fspi_clk: clock-controller@900 {
				compatible = "fsl,ls1028a-flexspi-clk";
				reg = <0x900 0x4>;
				#clock-cells = <0>;
				clocks = <&clockgen QORIQ_CLK_HWACCEL 0>;
				clock-output-names = "fspi_clk";
			};
		};

		rst: syscon@1e60000 {
			compatible = "syscon";
			reg = <0x0 0x1e60000 0x0 0x10000>;
			little-endian;
		};

		sfp: efuse@1e80000 {
			compatible = "fsl,ls1028a-sfp";
			reg = <0x0 0x1e80000 0x0 0x10000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "sfp";
			#address-cells = <1>;
			#size-cells = <1>;

			ls1028a_uid: unique-id@1c {
				reg = <0x1c 0x8>;
			};
		};

		scfg: syscon@1fc0000 {
			compatible = "fsl,ls1028a-scfg", "syscon";
			reg = <0x0 0x1fc0000 0x0 0x10000>;
			big-endian;
		};

		clockgen: clock-controller@1300000 {
			compatible = "fsl,ls1028a-clockgen";
			reg = <0x0 0x1300000 0x0 0xa0000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		i2c0: i2c@2000000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2000000 0x0 0x10000>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			status = "disabled";
		};

		i2c1: i2c@2010000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2010000 0x0 0x10000>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			status = "disabled";
		};

		i2c2: i2c@2020000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2020000 0x0 0x10000>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			status = "disabled";
		};

		i2c3: i2c@2030000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2030000 0x0 0x10000>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			status = "disabled";
		};

		i2c4: i2c@2040000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2040000 0x0 0x10000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			status = "disabled";
		};

		i2c5: i2c@2050000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2050000 0x0 0x10000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			status = "disabled";
		};

		i2c6: i2c@2060000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2060000 0x0 0x10000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			status = "disabled";
		};

		i2c7: i2c@2070000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2070000 0x0 0x10000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			status = "disabled";
		};

		fspi: spi@20c0000 {
			compatible = "nxp,lx2160a-fspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x20c0000 0x0 0x10000>,
			      <0x0 0x20000000 0x0 0x10000000>;
			reg-names = "fspi_base", "fspi_mmap";
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&fspi_clk>, <&fspi_clk>;
			clock-names = "fspi_en", "fspi";
			status = "disabled";
		};

		dspi0: spi@2100000 {
			compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			dmas = <&edma0 0 62>, <&edma0 0 60>;
			dma-names = "tx", "rx";
			spi-num-chipselects = <4>;
			little-endian;
			status = "disabled";
		};

		dspi1: spi@2110000 {
			compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2110000 0x0 0x10000>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			dmas = <&edma0 0 58>, <&edma0 0 56>;
			dma-names = "tx", "rx";
			spi-num-chipselects = <4>;
			little-endian;
			status = "disabled";
		};

		dspi2: spi@2120000 {
			compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2120000 0x0 0x10000>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			dmas = <&edma0 0 54>, <&edma0 0 2>;
			dma-names = "tx", "rx";
			spi-num-chipselects = <3>;
			little-endian;
			status = "disabled";
		};

		esdhc: mmc@2140000 {
			compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
			reg = <0x0 0x2140000 0x0 0x10000>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>; /* fixed up by bootloader */
			clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			little-endian;
			bus-width = <4>;
			status = "disabled";
		};

		esdhc1: mmc@2150000 {
			compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
			reg = <0x0 0x2150000 0x0 0x10000>;
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <0>; /* fixed up by bootloader */
			clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
			voltage-ranges = <1800 1800>;
			sdhci,auto-cmd12;
			non-removable;
			little-endian;
			bus-width = <4>;
			status = "disabled";
		};

		can0: can@2180000 {
			compatible = "fsl,lx2160ar1-flexcan";
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg", "per";
			status = "disabled";
		};

		can1: can@2190000 {
			compatible = "fsl,lx2160ar1-flexcan";
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg", "per";
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0500 0x0 0x100>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0600 0x0 0x100>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		lpuart0: serial@2260000 {
			compatible = "fsl,ls1028a-lpuart";
			reg = <0x0 0x2260000 0x0 0x1000>;
			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			dma-names = "rx","tx";
			dmas = <&edma0 1 32>,
			       <&edma0 1 33>;
			status = "disabled";
		};

		lpuart1: serial@2270000 {
			compatible = "fsl,ls1028a-lpuart";
			reg = <0x0 0x2270000 0x0 0x1000>;
			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			dma-names = "rx","tx";
			dmas = <&edma0 1 30>,
			       <&edma0 1 31>;
			status = "disabled";
		};

		lpuart2: serial@2280000 {
			compatible = "fsl,ls1028a-lpuart";
			reg = <0x0 0x2280000 0x0 0x1000>;
			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			dma-names = "rx","tx";
			dmas = <&edma0 1 28>,
			       <&edma0 1 29>;
			status = "disabled";
		};

		lpuart3: serial@2290000 {
			compatible = "fsl,ls1028a-lpuart";
			reg = <0x0 0x2290000 0x0 0x1000>;
			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			dma-names = "rx","tx";
			dmas = <&edma0 1 26>,
			       <&edma0 1 27>;
			status = "disabled";
		};

		lpuart4: serial@22a0000 {
			compatible = "fsl,ls1028a-lpuart";
			reg = <0x0 0x22a0000 0x0 0x1000>;
			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			dma-names = "rx","tx";
			dmas = <&edma0 1 24>,
			       <&edma0 1 25>;
			status = "disabled";
		};

		lpuart5: serial@22b0000 {
			compatible = "fsl,ls1028a-lpuart";
			reg = <0x0 0x22b0000 0x0 0x1000>;
			interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			dma-names = "rx","tx";
			dmas = <&edma0 1 22>,
			       <&edma0 1 23>;
			status = "disabled";
		};

		edma0: dma-controller@22c0000 {
			#dma-cells = <2>;
			compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
			reg = <0x0 0x22c0000 0x0 0x10000>,
			      <0x0 0x22d0000 0x0 0x10000>,
			      <0x0 0x22e0000 0x0 0x10000>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
		};

		gpio1: gpio@2300000 {
			compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			little-endian;
		};

		gpio2: gpio@2310000 {
			compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			little-endian;
		};

		gpio3: gpio@2320000 {
			compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			little-endian;
		};

		usb0: usb@3100000 {
			compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
			reg = <0x0 0x3100000 0x0 0x10000>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			snps,dis_rxdet_inp3_quirk;
			snps,quirk-frame-length-adjustment = <0x20>;
			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
			status = "disabled";
		};

		usb1: usb@3110000 {
			compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
			reg = <0x0 0x3110000 0x0 0x10000>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			snps,dis_rxdet_inp3_quirk;
			snps,quirk-frame-length-adjustment = <0x20>;
			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
			status = "disabled";
		};

		sata: sata@3200000 {
			compatible = "fsl,ls1028a-ahci";
			reg = <0x0 0x3200000 0x0 0x10000>,
				<0x7 0x100520 0x0 0x4>;
			reg-names = "ahci", "sata-ecc";
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		pcie1: pcie@3400000 {
			compatible = "fsl,ls1028a-pcie";
			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
			      <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
			interrupt-names = "pme", "aer";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			num-viewport = <8>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
			status = "disabled";
		};

		pcie_ep1: pcie-ep@3400000 {
			compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
			reg = <0x00 0x03400000 0x0 0x00100000
			       0x80 0x00000000 0x8 0x00000000>;
			reg-names = "regs", "addr_space";
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
			interrupt-names = "pme";
			num-ib-windows = <6>;
			num-ob-windows = <8>;
			status = "disabled";
		};

		pcie2: pcie@3500000 {
			compatible = "fsl,ls1028a-pcie";
			reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
			      <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pme", "aer";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			num-viewport = <8>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
			status = "disabled";
		};

		pcie_ep2: pcie-ep@3500000 {
			compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
			reg = <0x00 0x03500000 0x0 0x00100000
			       0x88 0x00000000 0x8 0x00000000>;
			reg-names = "regs", "addr_space";
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
			interrupt-names = "pme";
			num-ib-windows = <6>;
			num-ob-windows = <8>;
			status = "disabled";
		};

		smmu: iommu@5000000 {
			compatible = "arm,mmu-500";
			reg = <0 0x5000000 0 0x800000>;
			#global-interrupts = <8>;
			#iommu-cells = <1>;
			stream-match-mask = <0x7c00>;
			/* global secure fault */
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
			/* combined secure interrupt */
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
			/* global non-secure fault */
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
			/* combined non-secure interrupt */
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
			/* performance counter interrupts 0-7 */
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
			/* per context interrupt, 64 interrupts */
				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
		};

		crypto: crypto@8000000 {
			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
			fsl,sec-era = <10>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x00 0x8000000 0x100000>;
			reg = <0x00 0x8000000 0x0 0x100000>;
			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
			dma-coherent;

			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x10000 0x10000>;
				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x20000 0x10000>;
				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x30000 0x10000>;
				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x40000 0x10000>;
				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		qdma: dma-controller@8380000 {
			compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "qdma-error", "qdma-queue0",
				"qdma-queue1", "qdma-queue2", "qdma-queue3";
			dma-channels = <8>;
			block-number = <1>;
			block-offset = <0x10000>;
			fsl,dma-queues = <2>;
			status-sizes = <64>;
			queue-sizes = <64 64>;
		};

		cluster1_core0_watchdog: watchdog@c000000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc000000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster1_core1_watchdog: watchdog@c010000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc010000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		malidp0: display@f080000 {
			compatible = "arm,mali-dp500";
			reg = <0x0 0xf080000 0x0 0x10000>;
			interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
				     <0 223 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "DE", "SE";
			clocks = <&dpclk>,
				 <&clockgen QORIQ_CLK_HWACCEL 2>,
				 <&clockgen QORIQ_CLK_HWACCEL 2>,
				 <&clockgen QORIQ_CLK_HWACCEL 2>;
			clock-names = "pxlclk", "mclk", "aclk", "pclk";
			arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
			arm,malidp-arqos-value = <0xd000d000>;

			port {
				dpi0_out: endpoint {

				};
			};
		};

		gpu: gpu@f0c0000 {
			compatible = "vivante,gc";
			reg = <0x0 0xf0c0000 0x0 0x10000>;
			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_HWACCEL 2>,
				 <&clockgen QORIQ_CLK_HWACCEL 2>,
				 <&clockgen QORIQ_CLK_HWACCEL 2>;
			clock-names = "core", "shader", "bus";
			#cooling-cells = <2>;
		};

		sai1: audio-controller@f100000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0xf100000 0x0 0x10000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 4>,
			       <&edma0 1 3>;
			fsl,sai-asynchronous;
			status = "disabled";
		};

		sai2: audio-controller@f110000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0xf110000 0x0 0x10000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 6>,
			       <&edma0 1 5>;
			fsl,sai-asynchronous;
			status = "disabled";
		};

		sai3: audio-controller@f120000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0xf120000 0x0 0x10000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 8>,
			       <&edma0 1 7>;
			fsl,sai-asynchronous;
			status = "disabled";
		};

		sai4: audio-controller@f130000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0xf130000 0x0 0x10000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 10>,
			       <&edma0 1 9>;
			fsl,sai-asynchronous;
			status = "disabled";
		};

		sai5: audio-controller@f140000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0xf140000 0x0 0x10000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 12>,
			       <&edma0 1 11>;
			fsl,sai-asynchronous;
			status = "disabled";
		};

		sai6: audio-controller@f150000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0xf150000 0x0 0x10000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 14>,
			       <&edma0 1 13>;
			fsl,sai-asynchronous;
			status = "disabled";
		};

		dpclk: clock-controller@f1f0000 {
			compatible = "fsl,ls1028a-plldig";
			reg = <0x0 0xf1f0000 0x0 0x10000>;
			#clock-cells = <0>;
			clocks = <&osc_27m>;
		};

		tmu: tmu@1f80000 {
			compatible = "fsl,qoriq-tmu";
			reg = <0x0 0x1f80000 0x0 0x10000>;
			interrupts = <0 23 0x4>;
			fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
			fsl,tmu-calibration = <0x00000000 0x00000024
					       0x00000001 0x0000002b
					       0x00000002 0x00000031
					       0x00000003 0x00000038
					       0x00000004 0x0000003f
					       0x00000005 0x00000045
					       0x00000006 0x0000004c
					       0x00000007 0x00000053
					       0x00000008 0x00000059
					       0x00000009 0x00000060
					       0x0000000a 0x00000066
					       0x0000000b 0x0000006d

					       0x00010000 0x0000001c
					       0x00010001 0x00000024
					       0x00010002 0x0000002c
					       0x00010003 0x00000035
					       0x00010004 0x0000003d
					       0x00010005 0x00000045
					       0x00010006 0x0000004d
					       0x00010007 0x00000055
					       0x00010008 0x0000005e
					       0x00010009 0x00000066
					       0x0001000a 0x0000006e

					       0x00020000 0x00000018
					       0x00020001 0x00000022
					       0x00020002 0x0000002d
					       0x00020003 0x00000038
					       0x00020004 0x00000043
					       0x00020005 0x0000004d
					       0x00020006 0x00000058
					       0x00020007 0x00000063
					       0x00020008 0x0000006e

					       0x00030000 0x00000010
					       0x00030001 0x0000001c
					       0x00030002 0x00000029
					       0x00030003 0x00000036
					       0x00030004 0x00000042
					       0x00030005 0x0000004f
					       0x00030006 0x0000005b
					       0x00030007 0x00000068>;
			little-endian;
			#thermal-sensor-cells = <1>;
		};

		pcie@1f0000000 { /* Integrated Endpoint Root Complex */
			compatible = "pci-host-ecam-generic";
			reg = <0x01 0xf0000000 0x0 0x100000>;
			#address-cells = <3>;
			#size-cells = <2>;
			msi-parent = <&its>;
			device_type = "pci";
			bus-range = <0x0 0x0>;
			dma-coherent;
			msi-map = <0 &its 0x17 0xe>;
			iommu-map = <0 &smmu 0x17 0xe>;
				  /* PF0-6 BAR0 - non-prefetchable memory */
			ranges = <0x82000000 0x1 0xf8000000  0x1 0xf8000000  0x0 0x160000
				  /* PF0-6 BAR2 - prefetchable memory */
				  0xc2000000 0x1 0xf8160000  0x1 0xf8160000  0x0 0x070000
				  /* PF0: VF0-1 BAR0 - non-prefetchable memory */
				  0x82000000 0x1 0xf81d0000  0x1 0xf81d0000  0x0 0x020000
				  /* PF0: VF0-1 BAR2 - prefetchable memory */
				  0xc2000000 0x1 0xf81f0000  0x1 0xf81f0000  0x0 0x020000
				  /* PF1: VF0-1 BAR0 - non-prefetchable memory */
				  0x82000000 0x1 0xf8210000  0x1 0xf8210000  0x0 0x020000
				  /* PF1: VF0-1 BAR2 - prefetchable memory */
				  0xc2000000 0x1 0xf8230000  0x1 0xf8230000  0x0 0x020000
				  /* BAR4 (PF5) - non-prefetchable memory */
				  0x82000000 0x1 0xfc000000  0x1 0xfc000000  0x0 0x400000>;

			enetc_port0: ethernet@0,0 {
				compatible = "fsl,enetc";
				reg = <0x000000 0 0 0 0>;
				status = "disabled";
			};

			enetc_port1: ethernet@0,1 {
				compatible = "fsl,enetc";
				reg = <0x000100 0 0 0 0>;
				status = "disabled";
			};

			enetc_port2: ethernet@0,2 {
				compatible = "fsl,enetc";
				reg = <0x000200 0 0 0 0>;
				phy-mode = "internal";
				status = "disabled";

				fixed-link {
					speed = <2500>;
					full-duplex;
					pause;
				};
			};

			enetc_mdio_pf3: mdio@0,3 {
				compatible = "fsl,enetc-mdio";
				reg = <0x000300 0 0 0 0>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			ethernet@0,4 {
				compatible = "fsl,enetc-ptp";
				reg = <0x000400 0 0 0 0>;
				clocks = <&clockgen QORIQ_CLK_HWACCEL 3>;
				little-endian;
				fsl,extts-fifo;
			};

			mscc_felix: ethernet-switch@0,5 {
				reg = <0x000500 0 0 0 0>;
				/* IEP INT_B */
				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";

				mscc_felix_ports: ports {
					#address-cells = <1>;
					#size-cells = <0>;

					/* External ports */
					mscc_felix_port0: port@0 {
						reg = <0>;
						status = "disabled";
					};

					mscc_felix_port1: port@1 {
						reg = <1>;
						status = "disabled";
					};

					mscc_felix_port2: port@2 {
						reg = <2>;
						status = "disabled";
					};

					mscc_felix_port3: port@3 {
						reg = <3>;
						status = "disabled";
					};

					/* Internal ports */
					mscc_felix_port4: port@4 {
						reg = <4>;
						phy-mode = "internal";
						ethernet = <&enetc_port2>;
						status = "disabled";

						fixed-link {
							speed = <2500>;
							full-duplex;
							pause;
						};
					};

					mscc_felix_port5: port@5 {
						reg = <5>;
						phy-mode = "internal";
						ethernet = <&enetc_port3>;
						status = "disabled";

						fixed-link {
							speed = <1000>;
							full-duplex;
							pause;
						};
					};
				};
			};

			enetc_port3: ethernet@0,6 {
				compatible = "fsl,enetc";
				reg = <0x000600 0 0 0 0>;
				phy-mode = "internal";
				status = "disabled";

				fixed-link {
					speed = <1000>;
					full-duplex;
					pause;
				};
			};

			rcec@1f,0 {
				reg = <0x00f800 0 0 0 0>;
				/* IEP INT_A */
				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		/* Integrated Endpoint Register Block */
		ierb@1f0800000 {
			compatible = "fsl,ls1028a-enetc-ierb";
			reg = <0x01 0xf0800000 0x0 0x10000>;
		};

		pwm0: pwm@2800000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2800000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				      "ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&rtc_clk>, <&clockgen 4 1>;
			status = "disabled";
		};

		pwm1: pwm@2810000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2810000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				      "ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&rtc_clk>, <&clockgen 4 1>;
			status = "disabled";
		};

		pwm2: pwm@2820000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2820000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				      "ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&rtc_clk>, <&clockgen 4 1>;
			status = "disabled";
		};

		pwm3: pwm@2830000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2830000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				      "ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&rtc_clk>, <&clockgen 4 1>;
			status = "disabled";
		};

		pwm4: pwm@2840000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2840000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				      "ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&rtc_clk>, <&clockgen 4 1>;
			status = "disabled";
		};

		pwm5: pwm@2850000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2850000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				      "ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&rtc_clk>, <&clockgen 4 1>;
			status = "disabled";
		};

		pwm6: pwm@2860000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2860000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				      "ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&rtc_clk>, <&clockgen 4 1>;
			status = "disabled";
		};

		pwm7: pwm@2870000 {
			compatible = "fsl,vf610-ftm-pwm";
			#pwm-cells = <3>;
			reg = <0x0 0x2870000 0x0 0x10000>;
			clock-names = "ftm_sys", "ftm_ext",
				      "ftm_fix", "ftm_cnt_clk_en";
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&rtc_clk>, <&clockgen 4 1>;
			status = "disabled";
		};

		rcpm: power-controller@1e34040 {
			compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
			reg = <0x0 0x1e34040 0x0 0x1c>;
			#fsl,rcpm-wakeup-cells = <7>;
			little-endian;
		};

		ftm_alarm0: timer@2800000 {
			compatible = "fsl,ls1028a-ftm-alarm";
			reg = <0x0 0x2800000 0x0 0x10000>;
			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		ftm_alarm1: timer@2810000 {
			compatible = "fsl,ls1028a-ftm-alarm";
			reg = <0x0 0x2810000 0x0 0x10000>;
			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};
	};

};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * QorIQ FMan v3 device tree nodes for ls1043
 *
 * Copyright 2015-2016 Freescale Semiconductor Inc.
 */

&soc {

/* include used FMan blocks */
#include "qoriq-fman3-0.dtsi"
#include "qoriq-fman3-0-1g-0.dtsi"
#include "qoriq-fman3-0-1g-1.dtsi"
#include "qoriq-fman3-0-1g-2.dtsi"
#include "qoriq-fman3-0-1g-3.dtsi"
#include "qoriq-fman3-0-1g-4.dtsi"
#include "qoriq-fman3-0-1g-5.dtsi"
#include "qoriq-fman3-0-10g-0.dtsi"

};

&fman0 {
	fsl,erratum-a050385;

	/* these aliases provide the FMan ports mapping */
	enet0: ethernet@e0000 {
		pcs-handle-names = "qsgmii";
	};

	enet1: ethernet@e2000 {
		pcsphy-handle = <&pcsphy1>, <&qsgmiib_pcs1>;
		pcs-handle-names = "sgmii", "qsgmii";
	};

	enet2: ethernet@e4000 {
	};

	enet3: ethernet@e6000 {
	};

	enet4: ethernet@e8000 {
		pcsphy-handle = <&pcsphy4>, <&qsgmiib_pcs2>;
		pcs-handle-names = "sgmii", "qsgmii";
	};

	enet5: ethernet@ea000 {
		pcsphy-handle = <&pcsphy5>, <&qsgmiib_pcs3>;
		pcs-handle-names = "sgmii", "qsgmii";
	};

	enet6: ethernet@f0000 {
	};

	mdio@e1000 {
		qsgmiib_pcs1: ethernet-pcs@1 {
			compatible = "fsl,lynx-pcs";
			reg = <0x1>;
		};

		qsgmiib_pcs2: ethernet-pcs@2 {
			compatible = "fsl,lynx-pcs";
			reg = <0x2>;
		};

		qsgmiib_pcs3: ethernet-pcs@3 {
			compatible = "fsl,lynx-pcs";
			reg = <0x3>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
 *
 * Copyright 2014-2015 Freescale Semiconductor, Inc.
 * Copyright 2018-2021 NXP
 *
 * Mingkai Hu <Mingkai.hu@freescale.com>
 */

/dts-v1/;
#include "fsl-ls1043a.dtsi"

/ {
	model = "LS1043A QDS Board";
	compatible = "fsl,ls1043a-qds", "fsl,ls1043a";

	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		serial0 = &duart0;
		serial1 = &duart1;
		serial2 = &duart2;
		serial3 = &duart3;
		sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
		sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
		sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
		sgmii-riser-s4-p1 = &sgmii_phy_s4_p1;
		qsgmii-s1-p1 = &qsgmii_phy_s1_p1;
		qsgmii-s1-p2 = &qsgmii_phy_s1_p2;
		qsgmii-s1-p3 = &qsgmii_phy_s1_p3;
		qsgmii-s1-p4 = &qsgmii_phy_s1_p4;
		qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
		qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
		qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
		qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
		emi1-slot1 = &ls1043mdio_s1;
		emi1-slot2 = &ls1043mdio_s2;
		emi1-slot3 = &ls1043mdio_s3;
		emi1-slot4 = &ls1043mdio_s4;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	/* NOR, NAND Flashes and FPGA on board */
	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
		  0x1 0x0 0x0 0x7e800000 0x00010000
		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
	status = "okay";

	nor@0,0 {
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x8000000>;
		big-endian;
		bank-width = <2>;
		device-width = <1>;
	};

	nand@1,0 {
		compatible = "fsl,ifc-nand";
		reg = <0x1 0x0 0x10000>;
	};

	fpga: board-control@2,0 {
		compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
		reg = <0x2 0x0 0x0000100>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 2 0 0x100>;
	};
};

&i2c0 {
	status = "okay";

	pca9547@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0>;

			rtc@68 {
				compatible = "dallas,ds3232";
				reg = <0x68>;
				/* IRQ10_B */
				interrupts = <0 150 0x4>;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			ina220@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};

			ina220@41 {
				compatible = "ti,ina220";
				reg = <0x41>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			eeprom@56 {
				compatible = "atmel,24c512";
				reg = <0x56>;
			};

			eeprom@57 {
				compatible = "atmel,24c512";
				reg = <0x57>;
			};

			temp-sensor@4c {
				compatible = "adi,adt7461a";
				reg = <0x4c>;
			};
		};
	};
};

&lpuart0 {
	status = "okay";
};

&qspi {
	status = "okay";

	qflash0: flash@0 {
		compatible = "spansion,m25p80";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <20000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		reg = <0>;
	};
};

&usb0 {
	status = "okay";
};

#include "fsl-ls1043-post.dtsi"

&fman0 {
	ethernet@e0000 {
		phy-handle = <&qsgmii_phy_s2_p1>;
		phy-connection-type = "sgmii";
	};

	ethernet@e2000 {
		phy-handle = <&qsgmii_phy_s2_p2>;
		phy-connection-type = "sgmii";
	};

	ethernet@e4000 {
		phy-handle = <&rgmii_phy1>;
		phy-connection-type = "rgmii";
	};

	ethernet@e6000 {
		phy-handle = <&rgmii_phy2>;
		phy-connection-type = "rgmii";
	};

	ethernet@e8000 {
		phy-handle = <&qsgmii_phy_s2_p3>;
		phy-connection-type = "sgmii";
	};

	ethernet@ea000 {
		phy-handle = <&qsgmii_phy_s2_p4>;
		phy-connection-type = "sgmii";
	};

	ethernet@f0000 { /* DTSEC9/10GEC1 */
		fixed-link = <1 1 10000 0 0>;
		phy-connection-type = "xgmii";
	};
};

&fpga {
	mdio-mux-emi1@54 {
		compatible = "mdio-mux-mmioreg", "mdio-mux";
		mdio-parent-bus = <&mdio0>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x54 1>;    /* BRDCFG4 */
		mux-mask = <0xe0>; /* EMI1 */

		/* On-board RGMII1 PHY */
		ls1043mdio0: mdio@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			rgmii_phy1: ethernet-phy@1 { /* MAC3 */
				reg = <0x1>;
			};
		};

		/* On-board RGMII2 PHY */
		ls1043mdio1: mdio@20 {
			reg = <0x20>;
			#address-cells = <1>;
			#size-cells = <0>;

			rgmii_phy2: ethernet-phy@2 { /* MAC4 */
				reg = <0x2>;
			};
		};

		/* Slot 1 */
		ls1043mdio_s1: mdio@40 {
			reg = <0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			qsgmii_phy_s1_p1: ethernet-phy@4 {
				reg = <0x4>;
			};

			qsgmii_phy_s1_p2: ethernet-phy@5 {
				reg = <0x5>;
			};

			qsgmii_phy_s1_p3: ethernet-phy@6 {
				reg = <0x6>;
			};

			qsgmii_phy_s1_p4: ethernet-phy@7 {
				reg = <0x7>;
			};

			sgmii_phy_s1_p1: ethernet-phy@1c {
				reg = <0x1c>;
			};
		};

		/* Slot 2 */
		ls1043mdio_s2: mdio@60 {
			reg = <0x60>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			qsgmii_phy_s2_p1: ethernet-phy@8 {
				reg = <0x8>;
			};

			qsgmii_phy_s2_p2: ethernet-phy@9 {
				reg = <0x9>;
			};

			qsgmii_phy_s2_p3: ethernet-phy@a {
				reg = <0xa>;
			};

			qsgmii_phy_s2_p4: ethernet-phy@b {
				reg = <0xb>;
			};

			sgmii_phy_s2_p1: ethernet-phy@1c {
				reg = <0x1c>;
			};
		};

		/* Slot 3 */
		ls1043mdio_s3: mdio@80 {
			reg = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sgmii_phy_s3_p1: ethernet-phy@1c {
				reg = <0x1c>;
			};
		};

		/* Slot 4 */
		ls1043mdio_s4: mdio@a0 {
			reg = <0xa0>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sgmii_phy_s4_p1: ethernet-phy@1c {
				reg = <0x1c>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
 *
 * Copyright 2014-2015 Freescale Semiconductor, Inc.
 * Copyright 2018 NXP
 *
 * Mingkai Hu <Mingkai.hu@freescale.com>
 */

/dts-v1/;
#include "fsl-ls1043a.dtsi"

/ {
	model = "LS1043A RDB Board";
	compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";

	aliases {
		serial0 = &duart0;
		serial1 = &duart1;
		serial2 = &duart2;
		serial3 = &duart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&i2c0 {
	status = "okay";

	ina220@40 {
		compatible = "ti,ina220";
		reg = <0x40>;
		shunt-resistor = <1000>;
	};

	adt7461a@4c {
		compatible = "adi,adt7461";
		reg = <0x4c>;
	};

	rtc@51 {
		compatible = "nxp,pcf85263";
		reg = <0x51>;
	};

	eeprom@52 {
		compatible = "atmel,24c512";
		reg = <0x52>;
	};

	eeprom@53 {
		compatible = "atmel,24c512";
		reg = <0x53>;
	};

	rtc@68 {
		compatible = "pericom,pt7c4338";
		reg = <0x68>;
	};
};

&ifc {
	status = "okay";
	#address-cells = <2>;
	#size-cells = <1>;
	/* NOR, NAND Flashes and FPGA on board */
	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
		  0x1 0x0 0x0 0x7e800000 0x00010000
		  0x2 0x0 0x0 0x7fb00000 0x00000100>;

		nor@0,0 {
			compatible = "cfi-flash";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x0 0x0 0x8000000>;
			big-endian;
			bank-width = <2>;
			device-width = <1>;
		};

		nand@1,0 {
			compatible = "fsl,ifc-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x1 0x0 0x10000>;
		};

		cpld: board-control@2,0 {
			compatible = "fsl,ls1043ardb-cpld";
			reg = <0x2 0x0 0x0000100>;
		};
};

&dspi0 {
	bus-num = <0>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
		reg = <0>;
		spi-max-frequency = <1000000>; /* input clock */
		fsl,spi-cs-sck-delay = <100>;
		fsl,spi-sck-cs-delay = <100>;
	};

	slic@2 {
		compatible = "maxim,ds26522";
		reg = <2>;
		spi-max-frequency = <2000000>;
		fsl,spi-cs-sck-delay = <100>;
		fsl,spi-sck-cs-delay = <50>;
	};

	slic@3 {
		compatible = "maxim,ds26522";
		reg = <3>;
		spi-max-frequency = <2000000>;
		fsl,spi-cs-sck-delay = <100>;
		fsl,spi-sck-cs-delay = <50>;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

#include "fsl-ls1043-post.dtsi"

&fman0 {
	ethernet@e0000 {
		phy-handle = <&qsgmii_phy1>;
		phy-connection-type = "qsgmii";
	};

	ethernet@e2000 {
		phy-handle = <&qsgmii_phy2>;
		phy-connection-type = "qsgmii";
	};

	ethernet@e4000 {
		phy-handle = <&rgmii_phy1>;
		phy-connection-type = "rgmii-id";
	};

	ethernet@e6000 {
		phy-handle = <&rgmii_phy2>;
		phy-connection-type = "rgmii-id";
	};

	ethernet@e8000 {
		phy-handle = <&qsgmii_phy3>;
		phy-connection-type = "qsgmii";
	};

	ethernet@ea000 {
		phy-handle = <&qsgmii_phy4>;
		phy-connection-type = "qsgmii";
	};

	ethernet@f0000 { /* 10GEC1 */
		phy-handle = <&aqr105_phy>;
		phy-connection-type = "xgmii";
	};

	mdio@fc000 {
		rgmii_phy1: ethernet-phy@1 {
			reg = <0x1>;
		};

		rgmii_phy2: ethernet-phy@2 {
			reg = <0x2>;
		};

		qsgmii_phy1: ethernet-phy@4 {
			reg = <0x4>;
		};

		qsgmii_phy2: ethernet-phy@5 {
			reg = <0x5>;
		};

		qsgmii_phy3: ethernet-phy@6 {
			reg = <0x6>;
		};

		qsgmii_phy4: ethernet-phy@7 {
			reg = <0x7>;
		};
	};

	mdio@fd000 {
		aqr105_phy: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c45";
			interrupts = <0 132 4>;
			reg = <0x1>;
		};
	};
};

&uqe {
	ucc_hdlc: ucc@2000 {
		compatible = "fsl,ucc-hdlc";
		rx-clock-name = "clk8";
		tx-clock-name = "clk9";
		fsl,rx-sync-clock = "rsync_pin";
		fsl,tx-sync-clock = "tsync_pin";
		fsl,tx-timeslot-mask = <0xfffffffe>;
		fsl,rx-timeslot-mask = <0xfffffffe>;
		fsl,tdm-framer-type = "e1";
		fsl,tdm-id = <0>;
		fsl,siram-entry-id = <0>;
		fsl,tdm-interface;
	};
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};