code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the armadillo 800 eva board
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 */

/dts-v1/;
#include "r8a7740.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>

/ {
	model = "armadillo 800 eva";
	compatible = "renesas,armadillo800eva", "renesas,r8a7740";

	aliases {
		serial0 = &scifa1;
	};

	chosen {
		bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=on rw";
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0x20000000>;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_sdhi0: regulator-vcc-sdhi0 {
		compatible = "regulator-fixed";

		regulator-name = "SDHI0 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&pfc 75 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vccq_sdhi0: regulator-vccq-sdhi0 {
		compatible = "regulator-gpio";

		regulator-name = "SDHI0 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc_sdhi0>;

		enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>;
		gpios = <&pfc 17 GPIO_ACTIVE_HIGH>;
		states = <3300000 0>, <1800000 1>;

		enable-active-high;
	};

	reg_5p0v: regulator-5p0v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-5.0V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	keyboard {
		compatible = "gpio-keys";

		power-key {
			gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_POWER>;
			label = "SW3";
			wakeup-source;
		};

		back-key {
			gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_BACK>;
			label = "SW4";
		};

		menu-key {
			gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_MENU>;
			label = "SW5";
		};

		home-key {
			gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_HOME>;
			label = "SW6";
		};
	};

	leds {
		compatible = "gpio-leds";
		led3 {
			gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
			label = "LED3";
		};
		led4 {
			gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
			label = "LED4";
		};
		led5 {
			gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
			label = "LED5";
		};
		led6 {
			gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
			label = "LED6";
		};
	};

	i2c2: i2c-2 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "i2c-gpio";
		sda-gpios = <&pfc 208 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		scl-gpios = <&pfc 91 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
		i2c-gpio,delay-us = <5>;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>;
		brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
		default-brightness-level = <9>;
		pinctrl-0 = <&backlight_pins>;
		pinctrl-names = "default";
		power-supply = <&reg_5p0v>;
		enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>;
	};

	sound {
		compatible = "simple-audio-card";

		simple-audio-card,format = "i2s";

		simple-audio-card,cpu {
			sound-dai = <&sh_fsi2 0>;
			bitclock-inversion;
		};

		simple-audio-card,codec {
			sound-dai = <&wm8978>;
			bitclock-master;
			frame-master;
			system-clock-frequency = <12288000>;
		};
	};
};

&ether {
	pinctrl-0 = <&ether_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy0>;
	status = "okay";

	phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-id0007.c0f1",
			     "ethernet-phy-ieee802.3-c22";
		reg = <0>;
		reset-gpios = <&pfc 18 GPIO_ACTIVE_LOW>;
	};
};

&extal1_clk {
	clock-frequency = <24000000>;
};
&extal2_clk {
	clock-frequency = <48000000>;
};
&fsibck_clk {
	clock-frequency = <12288000>;
};
&cpg_clocks {
	renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */
};

&cmt1 {
	status = "okay";
};

&i2c0 {
	status = "okay";
	touchscreen@55 {
		compatible = "sitronix,st1232";
		reg = <0x55>;
		interrupt-parent = <&irqpin1>;
		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-0 = <&st1232_pins>;
		pinctrl-names = "default";
		gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
	};

	wm8978: codec@1a {
		#sound-dai-cells = <0>;
		compatible = "wlf,wm8978";
		reg = <0x1a>;
	};
};

&i2c2 {
	status = "okay";
	rtc@30 {
		compatible = "sii,s35390a";
		reg = <0x30>;
	};
};

&pfc {
	pinctrl-0 = <&lcd0_pins>;
	pinctrl-names = "default";

	ether_pins: ether {
		groups = "gether_mii", "gether_int";
		function = "gether";
	};

	scifa1_pins: scifa1 {
		groups = "scifa1_data";
		function = "scifa1";
	};

	st1232_pins: touchscreen {
		groups = "intc_irq10";
		function = "intc";
	};

	backlight_pins: backlight {
		groups = "tpu0_to2_1";
		function = "tpu0";
	};

	mmc0_pins: mmc0 {
		groups = "mmc0_data8_1", "mmc0_ctrl_1";
		function = "mmc0";
	};

	sdhi0_pins: sd0 {
		groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
		function = "sdhi0";
	};

	fsia_pins: sounda {
		groups = "fsia_sclk_in", "fsia_mclk_out",
			 "fsia_data_in_1", "fsia_data_out_0";
		function = "fsia";
	};

	lcd0_pins: lcd0 {
		groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";
		function = "lcd0";
	};

	lcd0-mux-hog {
		/* DBGMD/LCDC0/FSIA MUX */
		gpio-hog;
		gpios = <176 0>;
		output-high;
	};
};

&tpu {
	status = "okay";
};

&mmcif0 {
	pinctrl-0 = <&mmc0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&reg_3p3v>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&scifa1 {
	pinctrl-0 = <&scifa1_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vcc_sdhi0>;
	vqmmc-supply = <&vccq_sdhi0>;
	bus-width = <4>;
	cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&sh_fsi2 {
	pinctrl-0 = <&fsia_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&tmu0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 */

#include <dt-bindings/clock/r8a7740-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a7740";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x0>;
			clock-frequency = <800000000>;
			power-domains = <&pd_a3sm>;
			next-level-cache = <&L2>;
		};
	};

	gic: interrupt-controller@c2800000 {
		compatible = "arm,pl390";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xc2800000 0x1000>,
		      <0xc2000000 0x1000>;
	};

	L2: cache-controller@f0100000 {
		compatible = "arm,pl310-cache";
		reg = <0xf0100000 0x1000>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&pd_a3sm>;
		arm,data-latency = <3 3 3>;
		arm,tag-latency = <2 2 2>;
		arm,shared-override;
		cache-unified;
		cache-level = <2>;
	};

	dbsc3: memory-controller@fe400000 {
		compatible = "renesas,dbsc3-r8a7740";
		reg = <0xfe400000 0x400>;
		power-domains = <&pd_a4s>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	};

	ptm {
		compatible = "arm,coresight-etm3x";
		power-domains = <&pd_d4>;
	};

	ceu0: ceu@fe910000 {
		reg = <0xfe910000 0x3000>;
		compatible = "renesas,r8a7740-ceu";
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7740_CLK_CEU20>;
		power-domains = <&pd_a4r>;
		status = "disabled";
	};

	ceu1: ceu@fe914000 {
		reg = <0xfe914000 0x3000>;
		compatible = "renesas,r8a7740-ceu";
		interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7740_CLK_CEU21>;
		power-domains = <&pd_a4r>;
		status = "disabled";
	};

	cmt1: timer@e6138000 {
		compatible = "renesas,r8a7740-cmt1";
		reg = <0xe6138000 0x170>;
		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
		clock-names = "fck";
		power-domains = <&pd_c5>;
		status = "disabled";
	};

	/* irqpin0: IRQ0 - IRQ7 */
	irqpin0: interrupt-controller@e6900000 {
		compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe6900000 4>,
			<0xe6900010 4>,
			<0xe6900020 1>,
			<0xe6900040 1>,
			<0xe6900060 1>;
		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
		power-domains = <&pd_a4s>;
	};

	/* irqpin1: IRQ8 - IRQ15 */
	irqpin1: interrupt-controller@e6900004 {
		compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe6900004 4>,
			<0xe6900014 4>,
			<0xe6900024 1>,
			<0xe6900044 1>,
			<0xe6900064 1>;
		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
		power-domains = <&pd_a4s>;
	};

	/* irqpin2: IRQ16 - IRQ23 */
	irqpin2: interrupt-controller@e6900008 {
		compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe6900008 4>,
			<0xe6900018 4>,
			<0xe6900028 1>,
			<0xe6900048 1>,
			<0xe6900068 1>;
		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
		power-domains = <&pd_a4s>;
	};

	/* irqpin3: IRQ24 - IRQ31 */
	irqpin3: interrupt-controller@e690000c {
		compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe690000c 4>,
			<0xe690001c 4>,
			<0xe690002c 1>,
			<0xe690004c 1>,
			<0xe690006c 1>;
		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
		power-domains = <&pd_a4s>;
	};

	ether: ethernet@e9a00000 {
		compatible = "renesas,gether-r8a7740";
		reg = <0xe9a00000 0x800>,
		      <0xe9a01800 0x800>;
		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
		power-domains = <&pd_a4s>;
		phy-mode = "mii";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c0: i2c@fff20000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
		reg = <0xfff20000 0x425>;
		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
		power-domains = <&pd_a4r>;
		status = "disabled";
	};

	i2c1: i2c@e6c20000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
		reg = <0xe6c20000 0x425>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa0: serial@e6c40000 {
		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
		reg = <0xe6c40000 0x100>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa1: serial@e6c50000 {
		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
		reg = <0xe6c50000 0x100>;
		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa2: serial@e6c60000 {
		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
		reg = <0xe6c60000 0x100>;
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa3: serial@e6c70000 {
		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
		reg = <0xe6c70000 0x100>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa4: serial@e6c80000 {
		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
		reg = <0xe6c80000 0x100>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa5: serial@e6cb0000 {
		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
		reg = <0xe6cb0000 0x100>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa6: serial@e6cc0000 {
		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
		reg = <0xe6cc0000 0x100>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa7: serial@e6cd0000 {
		compatible = "renesas,scifa-r8a7740", "renesas,scifa";
		reg = <0xe6cd0000 0x100>;
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifb: serial@e6c30000 {
		compatible = "renesas,scifb-r8a7740", "renesas,scifb";
		reg = <0xe6c30000 0x100>;
		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	pfc: pinctrl@e6050000 {
		compatible = "renesas,pfc-r8a7740";
		reg = <0xe6050000 0x8000>,
		      <0xe605800c 0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&pfc 0 0 212>;
		interrupts-extended =
			<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
			<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
			<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
			<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
			<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
			<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
			<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
			<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
		power-domains = <&pd_c5>;
	};

	tpu: pwm@e6600000 {
		compatible = "renesas,tpu-r8a7740", "renesas,tpu";
		reg = <0xe6600000 0x148>;
		clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
		#pwm-cells = <3>;
	};

	mmcif0: mmc@e6bd0000 {
		compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
		reg = <0xe6bd0000 0x100>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7740_CLK_MMC>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	sdhi0: mmc@e6850000 {
		compatible = "renesas,sdhi-r8a7740";
		reg = <0xe6850000 0x100>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
		power-domains = <&pd_a3sp>;
		cap-sd-highspeed;
		cap-sdio-irq;
		status = "disabled";
	};

	sdhi1: mmc@e6860000 {
		compatible = "renesas,sdhi-r8a7740";
		reg = <0xe6860000 0x100>;
		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
		power-domains = <&pd_a3sp>;
		cap-sd-highspeed;
		cap-sdio-irq;
		status = "disabled";
	};

	sdhi2: mmc@e6870000 {
		compatible = "renesas,sdhi-r8a7740";
		reg = <0xe6870000 0x100>;
		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
		power-domains = <&pd_a3sp>;
		cap-sd-highspeed;
		cap-sdio-irq;
		status = "disabled";
	};

	sh_fsi2: sound@fe1f0000 {
		#sound-dai-cells = <1>;
		compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
		reg = <0xfe1f0000 0x400>;
		interrupts = <GIC_SPI 9 0x4>;
		clocks = <&mstp3_clks R8A7740_CLK_FSI>;
		power-domains = <&pd_a4mp>;
		status = "disabled";
	};

	tmu0: timer@fff80000 {
		compatible = "renesas,tmu-r8a7740", "renesas,tmu";
		reg = <0xfff80000 0x2c>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
		clock-names = "fck";
		power-domains = <&pd_a4r>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu1: timer@fff90000 {
		compatible = "renesas,tmu-r8a7740", "renesas,tmu";
		reg = <0xfff90000 0x2c>;
		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
		clock-names = "fck";
		power-domains = <&pd_a4r>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* External root clock */
		extalr_clk: extalr {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
		extal1_clk: extal1 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};
		extal2_clk: extal2 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};
		dv_clk: dv {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
		};
		fmsick_clk: fmsick {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};
		fmsock_clk: fmsock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};
		fsiack_clk: fsiack {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};
		fsibck_clk: fsibck {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@e6150000 {
			compatible = "renesas,r8a7740-cpg-clocks";
			reg = <0xe6150000 0x10000>;
			clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
			#clock-cells = <1>;
			clock-output-names = "system", "pllc0", "pllc1",
					     "pllc2", "r",
					     "usb24s",
					     "i", "zg", "b", "m1", "hp",
					     "hpp", "usbp", "s", "zb", "m3",
					     "cp";
		};

		/* Variable factor clocks (DIV6) */
		vclk1_clk: vclk1@e6150008 {
			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150008 4>;
			clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
				 <&cpg_clocks R8A7740_CLK_USB24S>,
				 <&extal1_div2_clk>, <&extalr_clk>, <0>,
				 <0>;
			#clock-cells = <0>;
		};
		vclk2_clk: vclk2@e615000c {
			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615000c 4>;
			clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
				 <&cpg_clocks R8A7740_CLK_USB24S>,
				 <&extal1_div2_clk>, <&extalr_clk>, <0>,
				 <0>;
			#clock-cells = <0>;
		};
		fmsi_clk: fmsi@e6150010 {
			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150010 4>;
			clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
			#clock-cells = <0>;
		};
		fmso_clk: fmso@e6150014 {
			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150014 4>;
			clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
			#clock-cells = <0>;
		};
		fsia_clk: fsia@e6150018 {
			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150018 4>;
			clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
			#clock-cells = <0>;
		};
		sub_clk: sub@e6150080 {
			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150080 4>;
			clocks = <&pllc1_div2_clk>,
				 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
			#clock-cells = <0>;
		};
		spu_clk: spu@e6150084 {
			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150084 4>;
			clocks = <&pllc1_div2_clk>,
				 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
			#clock-cells = <0>;
		};
		vou_clk: vou@e6150088 {
			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150088 4>;
			clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
				 <0>;
			#clock-cells = <0>;
		};
		stpro_clk: stpro@e615009c {
			compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615009c 4>;
			clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
			#clock-cells = <0>;
		};

		/* Fixed factor clocks */
		pllc1_div2_clk: pllc1_div2 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};
		extal1_div2_clk: extal1_div2 {
			compatible = "fixed-factor-clock";
			clocks = <&extal1_clk>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		/* Gate clocks */
		subck_clks: subck_clks@e6150080 {
			compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150080 4>;
			clocks = <&sub_clk>, <&sub_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
			>;
			clock-output-names =
				"subck", "subck2";
		};
		mstp1_clks: mstp1_clks@e6150134 {
			compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150134 4>, <0xe6150038 4>;
			clocks = <&cpg_clocks R8A7740_CLK_S>,
				 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
				 <&cpg_clocks R8A7740_CLK_B>,
				 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
				 <&cpg_clocks R8A7740_CLK_B>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
				R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
				R8A7740_CLK_LCDC0
			>;
			clock-output-names =
				"ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
				"tmu1", "lcdc0";
		};
		mstp2_clks: mstp2_clks@e6150138 {
			compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150138 4>, <0xe6150040 4>;
			clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
				 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
				 <&cpg_clocks R8A7740_CLK_HP>,
				 <&cpg_clocks R8A7740_CLK_HP>,
				 <&cpg_clocks R8A7740_CLK_HP>,
				 <&sub_clk>, <&sub_clk>, <&sub_clk>,
				 <&sub_clk>, <&sub_clk>, <&sub_clk>,
				 <&sub_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
				R8A7740_CLK_SCIFA7
				R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
				R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
				R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
				R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
				R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
				R8A7740_CLK_SCIFA4
			>;
			clock-output-names =
				"scifa6", "intca",
				"scifa7", "dmac1", "dmac2", "dmac3",
				"usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
				"scifa2", "scifa3", "scifa4";
		};
		mstp3_clks: mstp3_clks@e615013c {
			compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe615013c 4>, <0xe6150048 4>;
			clocks = <&cpg_clocks R8A7740_CLK_R>,
				 <&cpg_clocks R8A7740_CLK_HP>,
				 <&sub_clk>,
				 <&cpg_clocks R8A7740_CLK_HP>,
				 <&cpg_clocks R8A7740_CLK_HP>,
				 <&cpg_clocks R8A7740_CLK_HP>,
				 <&cpg_clocks R8A7740_CLK_HP>,
				 <&cpg_clocks R8A7740_CLK_HP>,
				 <&cpg_clocks R8A7740_CLK_HP>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
				R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
				R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
			>;
			clock-output-names =
				"cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
				"mmc", "gether", "tpu0";
		};
		mstp4_clks: mstp4_clks@e6150140 {
			compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150140 4>, <0xe615004c 4>;
			clocks = <&cpg_clocks R8A7740_CLK_HP>,
				 <&cpg_clocks R8A7740_CLK_HP>,
				 <&cpg_clocks R8A7740_CLK_HP>,
				 <&cpg_clocks R8A7740_CLK_HP>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7740_CLK_USBH R8A7740_CLK_SDHI2
				R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
			>;
			clock-output-names =
				"usbhost", "sdhi2", "usbfunc", "usphy";
		};
	};

	sysc: system-controller@e6180000 {
		compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
		reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;

		pm-domains {
			pd_c5: c5 {
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <0>;

				pd_a4lc: a4lc@1 {
					reg = <1>;
					#power-domain-cells = <0>;
				};

				pd_a4mp: a4mp@2 {
					reg = <2>;
					#power-domain-cells = <0>;
				};

				pd_d4: d4@3 {
					reg = <3>;
					#power-domain-cells = <0>;
				};

				pd_a4r: a4r@5 {
					reg = <5>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					pd_a3rv: a3rv@6 {
						reg = <6>;
						#power-domain-cells = <0>;
					};
				};

				pd_a4s: a4s@10 {
					reg = <10>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					pd_a3sp: a3sp@11 {
						reg = <11>;
						#power-domain-cells = <0>;
					};

					pd_a3sm: a3sm@12 {
						reg = <12>;
						#power-domain-cells = <0>;
					};

					pd_a3sg: a3sg@13 {
						reg = <13>;
						#power-domain-cells = <0>;
					};
				};

				pd_a4su: a4su@20 {
					reg = <20>;
					#power-domain-cells = <0>;
				};
			};
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the iWave-RZ/G1H Qseven board development
 * platform with camera daughter board
 *
 * Copyright (C) 2020 Renesas Electronics Corp.
 */

/dts-v1/;
#include "r8a7742-iwg21d-q7.dts"

/ {
	model = "iWave Systems RZ/G1H Qseven development platform with camera add-on";
	compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";

	aliases {
		serial0 = &scif0;
		serial1 = &scif1;
		serial3 = &scifb1;
		serial5 = &hscif0;
		ethernet1 = &ether;
	};

	mclk_cam1: mclk-cam1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};

	mclk_cam2: mclk-cam2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};

	mclk_cam3: mclk-cam3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};

	mclk_cam4: mclk-cam4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};

	reg_1p8v: 1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	reg_2p8v: 2p8v {
		compatible = "regulator-fixed";
		regulator-name = "2P8V";
		regulator-min-microvolt = <2800000>;
		regulator-max-microvolt = <2800000>;
		regulator-always-on;
	};
};

&avb {
	/* Pins shared with VIN0, keep status disabled */
	status = "disabled";
};

&can0 {
	pinctrl-0 = <&can0_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&ether {
	pinctrl-0 = <&ether_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy1>;
	renesas,ether-link-active-low;
	status = "okay";

	phy1: ethernet-phy@1 {
		compatible = "ethernet-phy-id0022.1560",
			     "ethernet-phy-ieee802.3-c22";
		reg = <1>;
		micrel,led-mode = <1>;
	};
};

&gpio0 {
	/* Disable hogging GP0_18 to output LOW */
	/delete-node/ qspi-en-hog;

	/* Hog GP0_18 to output HIGH to enable VIN2 */
	vin2-en-hog {
		gpio-hog;
		gpios = <18 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "VIN2_EN";
	};
};

&hscif0 {
	pinctrl-0 = <&hscif0_pins>;
	pinctrl-names = "default";
	uart-has-rtscts;
	status = "okay";
};

&i2c1 {
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "default";

	/* status set to "okay" when needed by camera configuration below */
	clock-frequency = <400000>;
};

&i2c3 {
	pinctrl-0 = <&i2c3_pins>;
	pinctrl-names = "default";

	/* status set to "okay" when needed by camera configuration below */
	clock-frequency = <400000>;
};

&pfc {
	can0_pins: can0 {
		groups = "can0_data_d";
		function = "can0";
	};

	ether_pins: ether {
		groups = "eth_mdio", "eth_rmii";
		function = "eth";
	};

	hscif0_pins: hscif0 {
		groups = "hscif0_data", "hscif0_ctrl";
		function = "hscif0";
	};

	i2c1_pins: i2c1 {
		groups = "i2c1_c";
		function = "i2c1";
	};

	i2c3_pins: i2c3 {
		groups = "i2c3";
		function = "i2c3";
	};

	scif0_pins: scif0 {
		groups = "scif0_data";
		function = "scif0";
	};

	scif1_pins: scif1 {
		groups = "scif1_data";
		function = "scif1";
	};

	scifb1_pins: scifb1 {
		groups = "scifb1_data";
		function = "scifb1";
	};

	vin0_8bit_pins: vin0 {
		groups = "vin0_data8", "vin0_clk", "vin0_sync";
		function = "vin0";
	};

	vin1_8bit_pins: vin1 {
		groups = "vin1_data8_b", "vin1_clk_b", "vin1_sync_b";
		function = "vin1";
	};

	vin2_pins: vin2 {
		groups = "vin2_g8", "vin2_clk";
		function = "vin2";
	};

	vin3_pins: vin3 {
		groups = "vin3_data8", "vin3_clk", "vin3_sync";
		function = "vin3";
	};
};

&qspi {
	/* Pins shared with VIN2, keep status disabled */
	status = "disabled";
};

&scif0 {
	pinctrl-0 = <&scif0_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&scif1 {
	pinctrl-0 = <&scif1_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&scifb1 {
	pinctrl-0 = <&scifb1_pins>;
	pinctrl-names = "default";
	status = "okay";

	rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
	cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
};

/*
 * Below configuration ties VINx endpoints to ov5640/ov7725 camera endpoints
 *
 * (un)comment the #include statements to change configuration
 */

/* 8bit CMOS Camera 1 (J13) */
#define CAM_PARENT_I2C		i2c0
#define MCLK_CAM		mclk_cam1
#define CAM_EP			cam0ep
#define VIN_EP			vin0ep
#undef CAM_ENABLED
#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"

#ifdef CAM_ENABLED
&vin0 {
	/*
	 * Set SW2 switch on the SOM to 'ON'
	 * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode
	 */
	status = "okay";
	pinctrl-0 = <&vin0_8bit_pins>;
	pinctrl-names = "default";

	port {
		vin0ep: endpoint {
			remote-endpoint = <&cam0ep>;
			bus-width = <8>;
			bus-type = <6>;
		};
	};
};
#endif /* CAM_ENABLED */

#undef CAM_PARENT_I2C
#undef MCLK_CAM
#undef CAM_EP
#undef VIN_EP

/* 8bit CMOS Camera 2 (J14) */
#define CAM_PARENT_I2C		i2c1
#define MCLK_CAM		mclk_cam2
#define CAM_EP			cam1ep
#define VIN_EP			vin1ep
#undef CAM_ENABLED
#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"

#ifdef CAM_ENABLED
&vin1 {
	/* Set SW1 switch on the SOM to 'ON' */
	status = "okay";
	pinctrl-0 = <&vin1_8bit_pins>;
	pinctrl-names = "default";

	port {
		vin1ep: endpoint {
			remote-endpoint = <&cam1ep>;
			bus-width = <8>;
			bus-type = <6>;
		};
	};
};

#endif /* CAM_ENABLED */

#undef CAM_PARENT_I2C
#undef MCLK_CAM
#undef CAM_EP
#undef VIN_EP

/* 8bit CMOS Camera 3 (J12) */
#define CAM_PARENT_I2C		i2c2
#define MCLK_CAM		mclk_cam3
#define CAM_EP			cam2ep
#define VIN_EP			vin2ep
#undef CAM_ENABLED
#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"

#ifdef CAM_ENABLED
&vin2 {
	status = "okay";
	pinctrl-0 = <&vin2_pins>;
	pinctrl-names = "default";

	port {
		vin2ep: endpoint {
			remote-endpoint = <&cam2ep>;
			bus-width = <8>;
			data-shift = <8>;
			bus-type = <6>;
		};
	};
};
#endif /* CAM_ENABLED */

#undef CAM_PARENT_I2C
#undef MCLK_CAM
#undef CAM_EP
#undef VIN_EP

/* 8bit CMOS Camera 4 (J11) */
#define CAM_PARENT_I2C		i2c3
#define MCLK_CAM		mclk_cam4
#define CAM_EP			cam3ep
#define VIN_EP			vin3ep
#undef CAM_ENABLED
#include "r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi"
//#include "r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi"

#ifdef CAM_ENABLED
&vin3 {
	status = "okay";
	pinctrl-0 = <&vin3_pins>;
	pinctrl-names = "default";

	port {
		vin3ep: endpoint {
			remote-endpoint = <&cam3ep>;
			bus-width = <8>;
			bus-type = <6>;
		};
	};
};
#endif /* CAM_ENABLED */

#undef CAM_PARENT_I2C
#undef MCLK_CAM
#undef CAM_EP
#undef VIN_EP


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * This include file ties a VIN interface with a single ov5640 sensor on
 * the iWave-RZ/G1H Qseven board development platform connected with the
 * camera daughter board.
 *
 * Copyright (C) 2020 Renesas Electronics Corp.
 */

#define CAM_ENABLED	1

&CAM_PARENT_I2C {
	status = "okay";

	ov5640@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;
		clocks = <&MCLK_CAM>;
		clock-names = "xclk";
		AVDD-supply = <&reg_2p8v>;
		DOVDD-supply = <&reg_2p8v>;
		DVDD-supply = <&reg_1p8v>;
		status = "okay";

		port {
			CAM_EP: endpoint {
				bus-width = <8>;
				data-shift = <2>;
				bus-type = <6>;
				pclk-sample = <1>;
				remote-endpoint = <&VIN_EP>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * This include file ties a VIN interface with a single ov7725 sensor on
 * the iWave-RZ/G1H Qseven board development platform connected with the
 * camera daughter board.
 *
 * Copyright (C) 2020 Renesas Electronics Corp.
 */

#define CAM_ENABLED	1

&CAM_PARENT_I2C {
	status = "okay";

	ov7725@21 {
		compatible = "ovti,ov7725";
		reg = <0x21>;
		clocks = <&MCLK_CAM>;
		status = "okay";

		port {
			CAM_EP: endpoint {
				bus-width = <8>;
				bus-type = <6>;
				remote-endpoint = <&VIN_EP>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the iWave-RZ/G1H Qseven board
 *
 * Copyright (C) 2020 Renesas Electronics Corp.
 */

/*
 * SSI-SGTL5000
 *
 * This command is required when Playback/Capture
 *
 *      amixer set "DVC Out" 100%
 *      amixer set "DVC In" 100%
 *
 * You can use Mute
 *
 *      amixer set "DVC Out Mute" on
 *      amixer set "DVC In Mute" on
 *
 * You can use Volume Ramp
 *
 *      amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
 *      amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
 *      amixer set "DVC Out Ramp" on
 *      aplay xxx.wav &
 *      amixer set "DVC Out"  80%  // Volume Down
 *      amixer set "DVC Out" 100%  // Volume Up
 */

/dts-v1/;
#include "r8a7742-iwg21m.dtsi"
#include <dt-bindings/pwm/pwm.h>

/ {
	model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H";
	compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";

	aliases {
		serial2 = &scifa2;
		serial4 = &scifb2;
		ethernet0 = &avb;
	};

	chosen {
		bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait";
		stdout-path = "serial2:115200n8";
	};

	audio_clock: audio_clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};

	lcd_backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&tpu 2 5000000 0>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		pinctrl-0 = <&backlight_pins>;
		pinctrl-names = "default";
		default-brightness-level = <7>;
		enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
	};

	leds {
		compatible = "gpio-leds";

		sdhi2_led {
			label = "sdio-led";
			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "mmc1";
		};
	};

	lvds-receiver {
		compatible = "ti,ds90cf384a", "lvds-decoder";
		power-supply = <&vcc_3v3_tft1>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				lvds_receiver_in: endpoint {
					remote-endpoint = <&lvds0_out>;
				};
			};
			port@1 {
				reg = <1>;
				lvds_receiver_out: endpoint {
					remote-endpoint = <&panel_in>;
				};
			};
		};
	};

	panel {
		compatible = "edt,etm0700g0dh6";
		backlight = <&lcd_backlight>;
		power-supply = <&vcc_3v3_tft1>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&lvds_receiver_out>;
			};
		};
	};

	reg_1p5v: 1p5v {
		compatible = "regulator-fixed";
		regulator-name = "1P5V";
		regulator-min-microvolt = <1500000>;
		regulator-max-microvolt = <1500000>;
		regulator-always-on;
	};

	rsnd_sgtl5000: sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&sndcodec>;
		simple-audio-card,frame-master = <&sndcodec>;

		sndcpu: simple-audio-card,cpu {
			sound-dai = <&rcar_sound>;
		};

		sndcodec: simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
		};
	};

	vcc_3v3_tft1: regulator-panel {
		compatible = "regulator-fixed";

		regulator-name = "vcc-3v3-tft1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
		startup-delay-us = <500>;
		gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>;
	};

	vcc_sdhi2: regulator-vcc-sdhi2 {
		compatible = "regulator-fixed";

		regulator-name = "SDHI2 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&gpio1 27 GPIO_ACTIVE_LOW>;
	};

	vccq_sdhi2: regulator-vccq-sdhi2 {
		compatible = "regulator-gpio";

		regulator-name = "SDHI2 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;

		gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
		gpios-states = <1>;
		states = <3300000 1>, <1800000 0>;
	};
};

&avb {
	pinctrl-0 = <&avb_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy3>;
	phy-mode = "gmii";
	renesas,no-ether-link;
	status = "okay";

	phy3: ethernet-phy@3 {
		compatible = "ethernet-phy-id0022.1622",
			     "ethernet-phy-ieee802.3-c22";
		reg = <3>;
		micrel,led-mode = <1>;
	};
};

&i2c2 {
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	sgtl5000: codec@a {
		compatible = "fsl,sgtl5000";
		#sound-dai-cells = <0>;
		reg = <0x0a>;
		clocks = <&audio_clock>;
		VDDA-supply = <&reg_3p3v>;
		VDDIO-supply = <&reg_3p3v>;
		VDDD-supply = <&reg_1p5v>;
	};

	touch: touchpanel@38 {
		compatible = "edt,edt-ft5406";
		reg = <0x38>;
		interrupt-parent = <&gpio0>;
		interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
		/* GP1_29 is also shared with audio codec reset pin */
		reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
		vcc-supply = <&vcc_3v3_tft1>;
	};
};

&can1 {
	pinctrl-0 = <&can1_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&cmt0 {
	status = "okay";
};

&du {
	status = "okay";
};

&gpio0 {
	touch-interrupt-hog {
		gpio-hog;
		gpios = <24 GPIO_ACTIVE_LOW>;
		input;
	};
};

&gpio1 {
	can-trx-en-hog {
		gpio-hog;
		gpios = <28 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "can-trx-en-gpio";
	};
};

&hsusb {
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&lvds0 {
	status = "okay";
	ports {
		port@1 {
			lvds0_out: endpoint {
				remote-endpoint = <&lvds_receiver_in>;
			};
		};
	};
};

&msiof0 {
	pinctrl-0 = <&msiof0_pins>;
	pinctrl-names = "default";
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;

	status = "okay";

	flash1: flash@0 {
		compatible = "sst,sst25vf016b", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <50000000>;
		m25p,fast-read;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "user";
				reg = <0x00000000 0x00200000>;
			};
		};
	};
};

&pci0 {
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
	/* Disable hsusb to enable USB2.0 host mode support on J2 */
	/* status = "okay"; */
};

&pci1 {
	pinctrl-0 = <&usb1_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&pci2 {
	/* Disable xhci to enable USB2.0 host mode support on J23 bottom port */
	/* status = "okay"; */
};

&pcie_bus_clk {
	clock-frequency = <100000000>;
};

&pciec {
	/* SW2[6] determines which connector is activated
	 * ON = PCIe X4 (connector-J7)
	 * OFF = mini-PCIe (connector-J26)
	 */
	status = "okay";
};

&pfc {
	avb_pins: avb {
		groups = "avb_mdio", "avb_gmii";
		function = "avb";
	};

	backlight_pins: backlight {
		groups = "tpu0_to2";
		function = "tpu0";
	};

	can1_pins: can1 {
		groups = "can1_data_b";
		function = "can1";
	};

	i2c2_pins: i2c2 {
		groups = "i2c2_b";
		function = "i2c2";
	};

	msiof0_pins: msiof0 {
		groups = "msiof0_clk", "msiof0_sync", "msiof0_tx", "msiof0_rx";
		function = "msiof0";
	};

	scifa2_pins: scifa2 {
		groups = "scifa2_data_c";
		function = "scifa2";
	};

	scifb2_pins: scifb2 {
		groups = "scifb2_data", "scifb2_ctrl";
		function = "scifb2";
	};

	sdhi2_pins: sd2 {
		groups = "sdhi2_data4", "sdhi2_ctrl";
		function = "sdhi2";
		power-source = <3300>;
	};

	sdhi2_pins_uhs: sd2_uhs {
		groups = "sdhi2_data4", "sdhi2_ctrl";
		function = "sdhi2";
		power-source = <1800>;
	};

	sound_pins: sound {
		groups = "ssi34_ctrl", "ssi3_data", "ssi4_data";
		function = "ssi";
	};

	usb0_pins: usb0 {
		groups = "usb0";
		function = "usb0";
	};

	usb1_pins: usb1 {
		groups = "usb1_pwen";
		function = "usb1";
	};
};

&rcar_sound {
	pinctrl-0 = <&sound_pins>;
	pinctrl-names = "default";
	status = "okay";

	/* Single DAI */
	#sound-dai-cells = <0>;

	rcar_sound,dai {
		dai0 {
			playback = <&ssi4>, <&src4>, <&dvc1>;
			capture = <&ssi3>, <&src3>, <&dvc0>;
		};
	};
};

&rwdt {
	timeout-sec = <60>;
	status = "okay";
};

&scifa2 {
	pinctrl-0 = <&scifa2_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&scifb2 {
	pinctrl-0 = <&scifb2_pins>;
	pinctrl-names = "default";

	uart-has-rtscts;
	status = "okay";
};

&sdhi2 {
	pinctrl-0 = <&sdhi2_pins>;
	pinctrl-1 = <&sdhi2_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi2>;
	vqmmc-supply = <&vccq_sdhi2>;
	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
	sd-uhs-sdr50;
	status = "okay";
};

&ssi4 {
	shared-pin;
};

&tpu {
	status = "okay";
};

&usbphy {
	status = "okay";
};

&xhci {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the iWave RZ/G1H Qseven SOM
 *
 * Copyright (C) 2020 Renesas Electronics Corp.
 */

#include "r8a7742.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "iwave,g21m", "renesas,r8a7742";

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x40000000>;
	};

	memory@200000000 {
		device_type = "memory";
		reg = <2 0x00000000 0 0x40000000>;
	};

	reg_3p3v: 3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&extal_clk {
	clock-frequency = <20000000>;
};

&gpio0 {
	/* GP0_18 set low to select QSPI. Doing so will disable VIN2 */
	qspi-en-hog {
		gpio-hog;
		gpios = <18 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "QSPI_EN";
	};
};

&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	rtc@68 {
		compatible = "ti,bq32000";
		reg = <0x68>;
		interrupt-parent = <&gpio1>;
		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
	};
};

&mmcif1 {
	pinctrl-0 = <&mmc1_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&reg_3p3v>;
	bus-width = <4>;
	non-removable;
	status = "okay";
};

&pfc {
	i2c0_pins: i2c0 {
		groups = "i2c0";
		function = "i2c0";
	};

	mmc1_pins: mmc1 {
		groups = "mmc1_data4", "mmc1_ctrl";
		function = "mmc1";
	};

	qspi_pins: qspi {
		groups = "qspi_ctrl", "qspi_data2";
		function = "qspi";
	};
};

&qspi {
	pinctrl-0 = <&qspi_pins>;
	pinctrl-names = "default";

	status = "okay";

	flash: flash@0 {
		compatible = "sst,sst25vf016b", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <50000000>;
		m25p,fast-read;
		spi-cpol;
		spi-cpha;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "bootloader";
				reg = <0x00000000 0x000c0000>;
				read-only;
			};
			partition@c0000 {
				label = "env";
				reg = <0x000c0000 0x00002000>;
			};
			partition@c2000 {
				label = "user";
				reg = <0x000c2000 0x0013e000>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the r8a7742 SoC
 *
 * Copyright (C) 2020 Renesas Electronics Corp.
 */

#include <dt-bindings/clock/r8a7742-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/r8a7742-sysc.h>

/ {
	compatible = "renesas,r8a7742";
	#address-cells = <2>;
	#size-cells = <2>;

	/*
	 * The external audio clocks are configured as 0 Hz fixed frequency
	 * clocks by default.
	 * Boards that provide audio clocks should override them.
	 */
	audio_clk_a: audio_clk_a {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};
	audio_clk_b: audio_clk_b {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};
	audio_clk_c: audio_clk_c {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	/* External CAN clock */
	can_clk: can {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			clock-frequency = <1400000000>;
			clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
			power-domains = <&sysc R8A7742_PD_CA15_CPU0>;
			enable-method = "renesas,apmu";
			next-level-cache = <&L2_CA15>;
			capacity-dmips-mhz = <1024>;
			voltage-tolerance = <1>; /* 1% */
			clock-latency = <300000>; /* 300 us */

			/* kHz - uV - OPPs unknown yet */
			operating-points = <1400000 1000000>,
					   <1225000 1000000>,
					   <1050000 1000000>,
					   < 875000 1000000>,
					   < 700000 1000000>,
					   < 350000 1000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
			clock-frequency = <1400000000>;
			clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
			power-domains = <&sysc R8A7742_PD_CA15_CPU1>;
			enable-method = "renesas,apmu";
			next-level-cache = <&L2_CA15>;
			capacity-dmips-mhz = <1024>;
			voltage-tolerance = <1>; /* 1% */
			clock-latency = <300000>; /* 300 us */

			/* kHz - uV - OPPs unknown yet */
			operating-points = <1400000 1000000>,
					   <1225000 1000000>,
					   <1050000 1000000>,
					   < 875000 1000000>,
					   < 700000 1000000>,
					   < 350000 1000000>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
			clock-frequency = <1400000000>;
			clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
			power-domains = <&sysc R8A7742_PD_CA15_CPU2>;
			enable-method = "renesas,apmu";
			next-level-cache = <&L2_CA15>;
			capacity-dmips-mhz = <1024>;
			voltage-tolerance = <1>; /* 1% */
			clock-latency = <300000>; /* 300 us */

			/* kHz - uV - OPPs unknown yet */
			operating-points = <1400000 1000000>,
					   <1225000 1000000>,
					   <1050000 1000000>,
					   < 875000 1000000>,
					   < 700000 1000000>,
					   < 350000 1000000>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
			clock-frequency = <1400000000>;
			clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
			power-domains = <&sysc R8A7742_PD_CA15_CPU3>;
			enable-method = "renesas,apmu";
			next-level-cache = <&L2_CA15>;
			capacity-dmips-mhz = <1024>;
			voltage-tolerance = <1>; /* 1% */
			clock-latency = <300000>; /* 300 us */

			/* kHz - uV - OPPs unknown yet */
			operating-points = <1400000 1000000>,
					   <1225000 1000000>,
					   <1050000 1000000>,
					   < 875000 1000000>,
					   < 700000 1000000>,
					   < 350000 1000000>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x100>;
			clock-frequency = <780000000>;
			clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
			power-domains = <&sysc R8A7742_PD_CA7_CPU0>;
			next-level-cache = <&L2_CA7>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x101>;
			clock-frequency = <780000000>;
			clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
			power-domains = <&sysc R8A7742_PD_CA7_CPU1>;
			next-level-cache = <&L2_CA7>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x102>;
			clock-frequency = <780000000>;
			clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
			power-domains = <&sysc R8A7742_PD_CA7_CPU2>;
			next-level-cache = <&L2_CA7>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x103>;
			clock-frequency = <780000000>;
			clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
			power-domains = <&sysc R8A7742_PD_CA7_CPU3>;
			next-level-cache = <&L2_CA7>;
		};

		L2_CA15: cache-controller-0 {
			compatible = "cache";
			power-domains = <&sysc R8A7742_PD_CA15_SCU>;
			cache-unified;
			cache-level = <2>;
		};

		L2_CA7: cache-controller-1 {
			compatible = "cache";
			power-domains = <&sysc R8A7742_PD_CA7_SCU>;
			cache-unified;
			cache-level = <2>;
		};
	};

	/* External root clock */
	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	pmu-0 {
		compatible = "arm,cortex-a15-pmu";
		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	pmu-1 {
		compatible = "arm,cortex-a7-pmu";
		interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
	};

	/* External SCIF clock */
	scif_clk: scif {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board. */
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;

		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rwdt: watchdog@e6020000 {
			compatible = "renesas,r8a7742-wdt",
				     "renesas,rcar-gen2-wdt";
			reg = <0 0xe6020000 0 0x0c>;
			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 402>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 402>;
			status = "disabled";
		};

		gpio0: gpio@e6050000 {
			compatible = "renesas,gpio-r8a7742",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6050000 0 0x50>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 0 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 912>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 912>;
		};

		gpio1: gpio@e6051000 {
			compatible = "renesas,gpio-r8a7742",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6051000 0 0x50>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 32 30>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 911>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 911>;
		};

		gpio2: gpio@e6052000 {
			compatible = "renesas,gpio-r8a7742",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6052000 0 0x50>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 64 30>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 910>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 910>;
		};

		gpio3: gpio@e6053000 {
			compatible = "renesas,gpio-r8a7742",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6053000 0 0x50>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 96 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 909>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 909>;
		};

		gpio4: gpio@e6054000 {
			compatible = "renesas,gpio-r8a7742",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6054000 0 0x50>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 128 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 908>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 908>;
		};

		gpio5: gpio@e6055000 {
			compatible = "renesas,gpio-r8a7742",
				     "renesas,rcar-gen2-gpio";
			reg = <0 0xe6055000 0 0x50>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 160 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 907>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 907>;
		};

		pfc: pinctrl@e6060000 {
			compatible = "renesas,pfc-r8a7742";
			reg = <0 0xe6060000 0 0x250>;
		};

		tpu: pwm@e60f0000 {
			compatible = "renesas,tpu-r8a7742", "renesas,tpu";
			reg = <0 0xe60f0000 0 0x148>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 304>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 304>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		cpg: clock-controller@e6150000 {
			compatible = "renesas,r8a7742-cpg-mssr";
			reg = <0 0xe6150000 0 0x1000>;
			clocks = <&extal_clk>, <&usb_extal_clk>;
			clock-names = "extal", "usb_extal";
			#clock-cells = <2>;
			#power-domain-cells = <0>;
			#reset-cells = <1>;
		};

		apmu@e6151000 {
			compatible = "renesas,r8a7742-apmu", "renesas,apmu";
			reg = <0 0xe6151000 0 0x188>;
			cpus = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
		};

		apmu@e6152000 {
			compatible = "renesas,r8a7742-apmu", "renesas,apmu";
			reg = <0 0xe6152000 0 0x188>;
			cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
		};

		rst: reset-controller@e6160000 {
			compatible = "renesas,r8a7742-rst";
			reg = <0 0xe6160000 0 0x0100>;
		};

		sysc: system-controller@e6180000 {
			compatible = "renesas,r8a7742-sysc";
			reg = <0 0xe6180000 0 0x0200>;
			#power-domain-cells = <1>;
		};

		irqc: interrupt-controller@e61c0000 {
			compatible = "renesas,irqc-r8a7742", "renesas,irqc";
			#interrupt-cells = <2>;
			interrupt-controller;
			reg = <0 0xe61c0000 0 0x200>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 407>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 407>;
		};

		thermal: thermal@e61f0000 {
			compatible = "renesas,thermal-r8a7742",
				     "renesas,rcar-gen2-thermal";
			reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 522>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 522>;
			#thermal-sensor-cells = <0>;
		};

		ipmmu_sy0: iommu@e6280000 {
			compatible = "renesas,ipmmu-r8a7742",
				     "renesas,ipmmu-vmsa";
			reg = <0 0xe6280000 0 0x1000>;
			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
			status = "disabled";
		};

		ipmmu_sy1: iommu@e6290000 {
			compatible = "renesas,ipmmu-r8a7742",
				     "renesas,ipmmu-vmsa";
			reg = <0 0xe6290000 0 0x1000>;
			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
			status = "disabled";
		};

		ipmmu_ds: iommu@e6740000 {
			compatible = "renesas,ipmmu-r8a7742",
				     "renesas,ipmmu-vmsa";
			reg = <0 0xe6740000 0 0x1000>;
			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
			status = "disabled";
		};

		ipmmu_mp: iommu@ec680000 {
			compatible = "renesas,ipmmu-r8a7742",
				     "renesas,ipmmu-vmsa";
			reg = <0 0xec680000 0 0x1000>;
			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
			status = "disabled";
		};

		ipmmu_mx: iommu@fe951000 {
			compatible = "renesas,ipmmu-r8a7742",
				     "renesas,ipmmu-vmsa";
			reg = <0 0xfe951000 0 0x1000>;
			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
			status = "disabled";
		};

		icram0: sram@e63a0000 {
			compatible = "mmio-sram";
			reg = <0 0xe63a0000 0 0x12000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0xe63a0000 0x12000>;
		};

		icram1: sram@e63c0000 {
			compatible = "mmio-sram";
			reg = <0 0xe63c0000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0xe63c0000 0x1000>;

			smp-sram@0 {
				compatible = "renesas,smp-sram";
				reg = <0 0x100>;
			};
		};

		icram2: sram@e6300000 {
			compatible = "mmio-sram";
			reg = <0 0xe6300000 0 0x40000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0xe6300000 0x40000>;
		};

		i2c0: i2c@e6508000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7742",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6508000 0 0x40>;
			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 931>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 931>;
			i2c-scl-internal-delay-ns = <110>;
			status = "disabled";
		};

		i2c1: i2c@e6518000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7742",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6518000 0 0x40>;
			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 930>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 930>;
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c2: i2c@e6530000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7742",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6530000 0 0x40>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 929>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 929>;
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c3: i2c@e6540000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7742",
				     "renesas,rcar-gen2-i2c";
			reg = <0 0xe6540000 0 0x40>;
			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 928>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 928>;
			i2c-scl-internal-delay-ns = <110>;
			status = "disabled";
		};

		iic0: i2c@e6500000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,iic-r8a7742",
				     "renesas,rcar-gen2-iic",
				     "renesas,rmobile-iic";
			reg = <0 0xe6500000 0 0x425>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 318>;
			dmas = <&dmac0 0x61>, <&dmac0 0x62>,
			       <&dmac1 0x61>, <&dmac1 0x62>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 318>;
			status = "disabled";
		};

		iic1: i2c@e6510000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,iic-r8a7742",
				     "renesas,rcar-gen2-iic",
				     "renesas,rmobile-iic";
			reg = <0 0xe6510000 0 0x425>;
			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 323>;
			dmas = <&dmac0 0x65>, <&dmac0 0x66>,
			       <&dmac1 0x65>, <&dmac1 0x66>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 323>;
			status = "disabled";
		};

		iic2: i2c@e6520000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,iic-r8a7742",
				     "renesas,rcar-gen2-iic",
				     "renesas,rmobile-iic";
			reg = <0 0xe6520000 0 0x425>;
			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 300>;
			dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
			       <&dmac1 0x69>, <&dmac1 0x6a>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 300>;
			status = "disabled";
		};

		iic3: i2c@e60b0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,iic-r8a7742",
				     "renesas,rcar-gen2-iic",
				     "renesas,rmobile-iic";
			reg = <0 0xe60b0000 0 0x425>;
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 926>;
			dmas = <&dmac0 0x77>, <&dmac0 0x78>,
			       <&dmac1 0x77>, <&dmac1 0x78>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 926>;
			status = "disabled";
		};

		hsusb: usb@e6590000 {
			compatible = "renesas,usbhs-r8a7742",
				     "renesas,rcar-gen2-usbhs";
			reg = <0 0xe6590000 0 0x100>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 704>;
			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
			       <&usb_dmac1 0>, <&usb_dmac1 1>;
			dma-names = "ch0", "ch1", "ch2", "ch3";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 704>;
			renesas,buswait = <4>;
			phys = <&usb0 1>;
			phy-names = "usb";
			status = "disabled";
		};

		usbphy: usb-phy-controller@e6590100 {
			compatible = "renesas,usb-phy-r8a7742",
				     "renesas,rcar-gen2-usb-phy";
			reg = <0 0xe6590100 0 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&cpg CPG_MOD 704>;
			clock-names = "usbhs";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 704>;
			status = "disabled";

			usb0: usb-phy@0 {
				reg = <0>;
				#phy-cells = <1>;
			};
			usb2: usb-phy@2 {
				reg = <2>;
				#phy-cells = <1>;
			};
		};

		usb_dmac0: dma-controller@e65a0000 {
			compatible = "renesas,r8a7742-usb-dmac",
				     "renesas,usb-dmac";
			reg = <0 0xe65a0000 0 0x100>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ch0", "ch1";
			clocks = <&cpg CPG_MOD 330>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 330>;
			#dma-cells = <1>;
			dma-channels = <2>;
		};

		usb_dmac1: dma-controller@e65b0000 {
			compatible = "renesas,r8a7742-usb-dmac",
				     "renesas,usb-dmac";
			reg = <0 0xe65b0000 0 0x100>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ch0", "ch1";
			clocks = <&cpg CPG_MOD 331>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 331>;
			#dma-cells = <1>;
			dma-channels = <2>;
		};

		dmac0: dma-controller@e6700000 {
			compatible = "renesas,dmac-r8a7742",
				     "renesas,rcar-dmac";
			reg = <0 0xe6700000 0 0x20000>;
			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					  "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12", "ch13", "ch14";
			clocks = <&cpg CPG_MOD 219>;
			clock-names = "fck";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 219>;
			#dma-cells = <1>;
			dma-channels = <15>;
		};

		dmac1: dma-controller@e6720000 {
			compatible = "renesas,dmac-r8a7742",
				     "renesas,rcar-dmac";
			reg = <0 0xe6720000 0 0x20000>;
			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					  "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12", "ch13", "ch14";
			clocks = <&cpg CPG_MOD 218>;
			clock-names = "fck";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 218>;
			#dma-cells = <1>;
			dma-channels = <15>;
		};

		avb: ethernet@e6800000 {
			compatible = "renesas,etheravb-r8a7742",
				     "renesas,etheravb-rcar-gen2";
			reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 812>;
			clock-names = "fck";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 812>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		qspi: spi@e6b10000 {
			compatible = "renesas,qspi-r8a7742", "renesas,qspi";
			reg = <0 0xe6b10000 0 0x2c>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 917>;
			dmas = <&dmac0 0x17>, <&dmac0 0x18>,
			       <&dmac1 0x17>, <&dmac1 0x18>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 917>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		scifa0: serial@e6c40000 {
			compatible = "renesas,scifa-r8a7742",
				     "renesas,rcar-gen2-scifa", "renesas,scifa";
			reg = <0 0xe6c40000 0 0x40>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 204>;
			clock-names = "fck";
			dmas = <&dmac0 0x21>, <&dmac0 0x22>,
			       <&dmac1 0x21>, <&dmac1 0x22>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 204>;
			status = "disabled";
		};

		scifa1: serial@e6c50000 {
			compatible = "renesas,scifa-r8a7742",
				     "renesas,rcar-gen2-scifa", "renesas,scifa";
			reg = <0 0xe6c50000 0 0x40>;
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 203>;
			clock-names = "fck";
			dmas = <&dmac0 0x25>, <&dmac0 0x26>,
			       <&dmac1 0x25>, <&dmac1 0x26>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 203>;
			status = "disabled";
		};

		scifa2: serial@e6c60000 {
			compatible = "renesas,scifa-r8a7742",
				     "renesas,rcar-gen2-scifa", "renesas,scifa";
			reg = <0 0xe6c60000 0 0x40>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 202>;
			clock-names = "fck";
			dmas = <&dmac0 0x27>, <&dmac0 0x28>,
			       <&dmac1 0x27>, <&dmac1 0x28>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 202>;
			status = "disabled";
		};

		scifb0: serial@e6c20000 {
			compatible = "renesas,scifb-r8a7742",
				     "renesas,rcar-gen2-scifb", "renesas,scifb";
			reg = <0 0xe6c20000 0 0x100>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 206>;
			clock-names = "fck";
			dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
			       <&dmac1 0x3d>, <&dmac1 0x3e>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 206>;
			status = "disabled";
		};

		scifb1: serial@e6c30000 {
			compatible = "renesas,scifb-r8a7742",
				     "renesas,rcar-gen2-scifb", "renesas,scifb";
			reg = <0 0xe6c30000 0 0x100>;
			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 207>;
			clock-names = "fck";
			dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
			       <&dmac1 0x19>, <&dmac1 0x1a>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 207>;
			status = "disabled";
		};

		scifb2: serial@e6ce0000 {
			compatible = "renesas,scifb-r8a7742",
				     "renesas,rcar-gen2-scifb", "renesas,scifb";
			reg = <0 0xe6ce0000 0 0x100>;
			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 216>;
			clock-names = "fck";
			dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
			       <&dmac1 0x1d>, <&dmac1 0x1e>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 216>;
			status = "disabled";
		};

		scif0: serial@e6e60000 {
			compatible = "renesas,scif-r8a7742",
				     "renesas,rcar-gen2-scif", "renesas,scif";
			reg = <0 0xe6e60000 0 0x40>;
			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 721>,
				 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
			       <&dmac1 0x29>, <&dmac1 0x2a>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 721>;
			status = "disabled";
		};

		scif1: serial@e6e68000 {
			compatible = "renesas,scif-r8a7742",
				     "renesas,rcar-gen2-scif", "renesas,scif";
			reg = <0 0xe6e68000 0 0x40>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 720>,
				 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
			       <&dmac1 0x2d>, <&dmac1 0x2e>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 720>;
			status = "disabled";
		};

		scif2: serial@e6e56000 {
			compatible = "renesas,scif-r8a7742",
				     "renesas,rcar-gen2-scif", "renesas,scif";
			reg = <0 0xe6e56000 0 0x40>;
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 310>,
				 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
			       <&dmac1 0x2b>, <&dmac1 0x2c>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 310>;
			status = "disabled";
		};

		hscif0: serial@e62c0000 {
			compatible = "renesas,hscif-r8a7742",
				     "renesas,rcar-gen2-hscif", "renesas,hscif";
			reg = <0 0xe62c0000 0 0x60>;
			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 717>,
				 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
			       <&dmac1 0x39>, <&dmac1 0x3a>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 717>;
			status = "disabled";
		};

		hscif1: serial@e62c8000 {
			compatible = "renesas,hscif-r8a7742",
				     "renesas,rcar-gen2-hscif", "renesas,hscif";
			reg = <0 0xe62c8000 0 0x60>;
			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 716>,
				 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
			       <&dmac1 0x4d>, <&dmac1 0x4e>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 716>;
			status = "disabled";
		};

		msiof0: spi@e6e20000 {
			compatible = "renesas,msiof-r8a7742",
				     "renesas,rcar-gen2-msiof";
			reg = <0 0xe6e20000 0 0x0064>;
			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 0>;
			dmas = <&dmac0 0x51>, <&dmac0 0x52>,
			       <&dmac1 0x51>, <&dmac1 0x52>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 0>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		msiof1: spi@e6e10000 {
			compatible = "renesas,msiof-r8a7742",
				     "renesas,rcar-gen2-msiof";
			reg = <0 0xe6e10000 0 0x0064>;
			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 208>;
			dmas = <&dmac0 0x55>, <&dmac0 0x56>,
			       <&dmac1 0x55>, <&dmac1 0x56>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 208>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		msiof2: spi@e6e00000 {
			compatible = "renesas,msiof-r8a7742",
				     "renesas,rcar-gen2-msiof";
			reg = <0 0xe6e00000 0 0x0064>;
			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 205>;
			dmas = <&dmac0 0x41>, <&dmac0 0x42>,
			       <&dmac1 0x41>, <&dmac1 0x42>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 205>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		msiof3: spi@e6c90000 {
			compatible = "renesas,msiof-r8a7742",
				     "renesas,rcar-gen2-msiof";
			reg = <0 0xe6c90000 0 0x0064>;
			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 215>;
			dmas = <&dmac0 0x45>, <&dmac0 0x46>,
			       <&dmac1 0x45>, <&dmac1 0x46>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 215>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		can0: can@e6e80000 {
			compatible = "renesas,can-r8a7742",
				     "renesas,rcar-gen2-can";
			reg = <0 0xe6e80000 0 0x1000>;
			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 916>,
				 <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;
			clock-names = "clkp1", "clkp2", "can_clk";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 916>;
			status = "disabled";
		};

		can1: can@e6e88000 {
			compatible = "renesas,can-r8a7742",
				     "renesas,rcar-gen2-can";
			reg = <0 0xe6e88000 0 0x1000>;
			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 915>,
				 <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>;
			clock-names = "clkp1", "clkp2", "can_clk";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 915>;
			status = "disabled";
		};

		pwm0: pwm@e6e30000 {
			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
			reg = <0 0xe6e30000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		pwm1: pwm@e6e31000 {
			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
			reg = <0 0xe6e31000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		pwm2: pwm@e6e32000 {
			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
			reg = <0 0xe6e32000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		pwm3: pwm@e6e33000 {
			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
			reg = <0 0xe6e33000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		pwm4: pwm@e6e34000 {
			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
			reg = <0 0xe6e34000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		pwm5: pwm@e6e35000 {
			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
			reg = <0 0xe6e35000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		pwm6: pwm@e6e36000 {
			compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar";
			reg = <0 0xe6e36000 0 0x8>;
			clocks = <&cpg CPG_MOD 523>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 523>;
			#pwm-cells = <2>;
			status = "disabled";
		};

		vin0: video@e6ef0000 {
			compatible = "renesas,vin-r8a7742",
				     "renesas,rcar-gen2-vin";
			reg = <0 0xe6ef0000 0 0x1000>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 811>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 811>;
			status = "disabled";
		};

		vin1: video@e6ef1000 {
			compatible = "renesas,vin-r8a7742",
				     "renesas,rcar-gen2-vin";
			reg = <0 0xe6ef1000 0 0x1000>;
			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 810>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 810>;
			status = "disabled";
		};

		vin2: video@e6ef2000 {
			compatible = "renesas,vin-r8a7742",
				     "renesas,rcar-gen2-vin";
			reg = <0 0xe6ef2000 0 0x1000>;
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 809>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 809>;
			status = "disabled";
		};

		vin3: video@e6ef3000 {
			compatible = "renesas,vin-r8a7742",
				     "renesas,rcar-gen2-vin";
			reg = <0 0xe6ef3000 0 0x1000>;
			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 808>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 808>;
			status = "disabled";
		};

		rcar_sound: sound@ec500000 {
			/*
			 * #sound-dai-cells is required
			 *
			 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
			 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
			 */
			compatible = "renesas,rcar_sound-r8a7742",
				     "renesas,rcar_sound-gen2";
			reg = <0 0xec500000 0 0x1000>, /* SCU */
			      <0 0xec5a0000 0 0x100>,  /* ADG */
			      <0 0xec540000 0 0x1000>, /* SSIU */
			      <0 0xec541000 0 0x280>,  /* SSI */
			      <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

			clocks = <&cpg CPG_MOD 1005>,
				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
				 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
				 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
				 <&cpg CPG_CORE R8A7742_CLK_M2>;
			clock-names = "ssi-all",
				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
				      "ssi.1", "ssi.0",
				      "src.9", "src.8", "src.7", "src.6",
				      "src.5", "src.4", "src.3", "src.2",
				      "src.1", "src.0",
				      "ctu.0", "ctu.1",
				      "mix.0", "mix.1",
				      "dvc.0", "dvc.1",
				      "clk_a", "clk_b", "clk_c", "clk_i";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 1005>,
				 <&cpg 1006>, <&cpg 1007>,
				 <&cpg 1008>, <&cpg 1009>,
				 <&cpg 1010>, <&cpg 1011>,
				 <&cpg 1012>, <&cpg 1013>,
				 <&cpg 1014>, <&cpg 1015>;
			reset-names = "ssi-all",
				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
				      "ssi.1", "ssi.0";

			status = "disabled";

			rcar_sound,dvc {
				dvc0: dvc-0 {
					dmas = <&audma1 0xbc>;
					dma-names = "tx";
				};
				dvc1: dvc-1 {
					dmas = <&audma1 0xbe>;
					dma-names = "tx";
				};
			};

			rcar_sound,mix {
				mix0: mix-0 { };
				mix1: mix-1 { };
			};

			rcar_sound,ctu {
				ctu00: ctu-0 { };
				ctu01: ctu-1 { };
				ctu02: ctu-2 { };
				ctu03: ctu-3 { };
				ctu10: ctu-4 { };
				ctu11: ctu-5 { };
				ctu12: ctu-6 { };
				ctu13: ctu-7 { };
			};

			rcar_sound,src {
				src0: src-0 {
					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x85>, <&audma1 0x9a>;
					dma-names = "rx", "tx";
				};
				src1: src-1 {
					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x87>, <&audma1 0x9c>;
					dma-names = "rx", "tx";
				};
				src2: src-2 {
					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x89>, <&audma1 0x9e>;
					dma-names = "rx", "tx";
				};
				src3: src-3 {
					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
					dma-names = "rx", "tx";
				};
				src4: src-4 {
					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
					dma-names = "rx", "tx";
				};
				src5: src-5 {
					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
					dma-names = "rx", "tx";
				};
				src6: src-6 {
					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x91>, <&audma1 0xb4>;
					dma-names = "rx", "tx";
				};
				src7: src-7 {
					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x93>, <&audma1 0xb6>;
					dma-names = "rx", "tx";
				};
				src8: src-8 {
					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x95>, <&audma1 0xb8>;
					dma-names = "rx", "tx";
				};
				src9: src-9 {
					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x97>, <&audma1 0xba>;
					dma-names = "rx", "tx";
				};
			};

			rcar_sound,ssi {
				ssi0: ssi-0 {
					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x01>, <&audma1 0x02>,
					       <&audma0 0x15>, <&audma1 0x16>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi1: ssi-1 {
					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x03>, <&audma1 0x04>,
					       <&audma0 0x49>, <&audma1 0x4a>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi2: ssi-2 {
					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x05>, <&audma1 0x06>,
					       <&audma0 0x63>, <&audma1 0x64>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi3: ssi-3 {
					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x07>, <&audma1 0x08>,
					       <&audma0 0x6f>, <&audma1 0x70>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi4: ssi-4 {
					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x09>, <&audma1 0x0a>,
					       <&audma0 0x71>, <&audma1 0x72>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi5: ssi-5 {
					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x0b>, <&audma1 0x0c>,
					       <&audma0 0x73>, <&audma1 0x74>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi6: ssi-6 {
					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x0d>, <&audma1 0x0e>,
					       <&audma0 0x75>, <&audma1 0x76>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi7: ssi-7 {
					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x0f>, <&audma1 0x10>,
					       <&audma0 0x79>, <&audma1 0x7a>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi8: ssi-8 {
					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x11>, <&audma1 0x12>,
					       <&audma0 0x7b>, <&audma1 0x7c>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
				ssi9: ssi-9 {
					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x13>, <&audma1 0x14>,
					       <&audma0 0x7d>, <&audma1 0x7e>;
					dma-names = "rx", "tx", "rxu", "txu";
				};
			};
		};

		audma0: dma-controller@ec700000 {
			compatible = "renesas,dmac-r8a7742",
				     "renesas,rcar-dmac";
			reg = <0 0xec700000 0 0x10000>;
			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					  "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12";
			clocks = <&cpg CPG_MOD 502>;
			clock-names = "fck";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 502>;
			#dma-cells = <1>;
			dma-channels = <13>;
		};

		audma1: dma-controller@ec720000 {
			compatible = "renesas,dmac-r8a7742",
				     "renesas,rcar-dmac";
			reg = <0 0xec720000 0 0x10000>;
			interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					  "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12";
			clocks = <&cpg CPG_MOD 501>;
			clock-names = "fck";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 501>;
			#dma-cells = <1>;
			dma-channels = <13>;
		};

		xhci: usb@ee000000 {
			compatible = "renesas,xhci-r8a7742",
				     "renesas,rcar-gen2-xhci";
			reg = <0 0xee000000 0 0xc00>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 328>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 328>;
			phys = <&usb2 1>;
			phy-names = "usb";
			status = "disabled";
		};

		pci0: pci@ee090000 {
			compatible = "renesas,pci-r8a7742",
				     "renesas,pci-rcar-gen2";
			device_type = "pci";
			reg = <0 0xee090000 0 0xc00>,
			      <0 0xee080000 0 0x1100>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 703>;
			status = "disabled";

			bus-range = <0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
			interrupt-map-mask = <0xf800 0 0 0x7>;
			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
					<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
					<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

			usb@1,0 {
				reg = <0x800 0 0 0 0>;
				phys = <&usb0 0>;
				phy-names = "usb";
			};

			usb@2,0 {
				reg = <0x1000 0 0 0 0>;
				phys = <&usb0 0>;
				phy-names = "usb";
			};
		};

		pci1: pci@ee0b0000 {
			compatible = "renesas,pci-r8a7742",
				     "renesas,pci-rcar-gen2";
			device_type = "pci";
			reg = <0 0xee0b0000 0 0xc00>,
			      <0 0xee0a0000 0 0x1100>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 703>;
			status = "disabled";

			bus-range = <1 1>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
			interrupt-map-mask = <0xf800 0 0 0x7>;
			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
					<0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
					<0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
		};

		pci2: pci@ee0d0000 {
			compatible = "renesas,pci-r8a7742",
				     "renesas,pci-rcar-gen2";
			device_type = "pci";
			clocks = <&cpg CPG_MOD 703>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 703>;
			reg = <0 0xee0d0000 0 0xc00>,
			      <0 0xee0c0000 0 0x1100>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";

			bus-range = <2 2>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
			interrupt-map-mask = <0xf800 0 0 0x7>;
			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
					<0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
					<0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

			usb@1,0 {
				reg = <0x20800 0 0 0 0>;
				phys = <&usb2 0>;
				phy-names = "usb";
			};

			usb@2,0 {
				reg = <0x21000 0 0 0 0>;
				phys = <&usb2 0>;
				phy-names = "usb";
			};
		};

		sdhi0: mmc@ee100000 {
			compatible = "renesas,sdhi-r8a7742",
				     "renesas,rcar-gen2-sdhi";
			reg = <0 0xee100000 0 0x328>;
			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 314>;
			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
			       <&dmac1 0xcd>, <&dmac1 0xce>;
			dma-names = "tx", "rx", "tx", "rx";
			max-frequency = <195000000>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 314>;
			status = "disabled";
		};

		sdhi1: mmc@ee120000 {
			compatible = "renesas,sdhi-r8a7742",
				     "renesas,rcar-gen2-sdhi";
			reg = <0 0xee120000 0 0x328>;
			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 313>;
			dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
			       <&dmac1 0xc9>, <&dmac1 0xca>;
			dma-names = "tx", "rx", "tx", "rx";
			max-frequency = <195000000>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 313>;
			status = "disabled";
		};

		sdhi2: mmc@ee140000 {
			compatible = "renesas,sdhi-r8a7742",
				     "renesas,rcar-gen2-sdhi";
			reg = <0 0xee140000 0 0x100>;
			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 312>;
			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
			       <&dmac1 0xc1>, <&dmac1 0xc2>;
			dma-names = "tx", "rx", "tx", "rx";
			max-frequency = <97500000>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 312>;
			status = "disabled";
		};

		sdhi3: mmc@ee160000 {
			compatible = "renesas,sdhi-r8a7742",
				     "renesas,rcar-gen2-sdhi";
			reg = <0 0xee160000 0 0x100>;
			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 311>;
			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
			       <&dmac1 0xd3>, <&dmac1 0xd4>;
			dma-names = "tx", "rx", "tx", "rx";
			max-frequency = <97500000>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 311>;
			status = "disabled";
		};

		mmcif0: mmc@ee200000 {
			compatible = "renesas,mmcif-r8a7742",
				     "renesas,sh-mmcif";
			reg = <0 0xee200000 0 0x80>;
			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 315>;
			dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
			       <&dmac1 0xd1>, <&dmac1 0xd2>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 315>;
			reg-io-width = <4>;
			status = "disabled";
			max-frequency = <97500000>;
		};

		mmcif1: mmc@ee220000 {
			compatible = "renesas,mmcif-r8a7742",
				     "renesas,sh-mmcif";
			reg = <0 0xee220000 0 0x80>;
			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 305>;
			dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
			       <&dmac1 0xe1>, <&dmac1 0xe2>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 305>;
			reg-io-width = <4>;
			status = "disabled";
			max-frequency = <97500000>;
		};

		sata0: sata@ee300000 {
			compatible = "renesas,sata-r8a7742",
				     "renesas,rcar-gen2-sata";
			reg = <0 0xee300000 0 0x200000>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 815>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 815>;
			status = "disabled";
		};

		sata1: sata@ee500000 {
			compatible = "renesas,sata-r8a7742",
				     "renesas,rcar-gen2-sata";
			reg = <0 0xee500000 0 0x200000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 814>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 814>;
			status = "disabled";
		};

		ether: ethernet@ee700000 {
			compatible = "renesas,ether-r8a7742",
				     "renesas,rcar-gen2-ether";
			reg = <0 0xee700000 0 0x400>;
			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 813>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 813>;
			phy-mode = "rmii";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		gic: interrupt-controller@f1001000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
			      <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&cpg CPG_MOD 408>;
			clock-names = "clk";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 408>;
		};

		pciec: pcie@fe000000 {
			compatible = "renesas,pcie-r8a7742",
				     "renesas,pcie-rcar-gen2";
			reg = <0 0xfe000000 0 0x80000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0x00 0xff>;
			device_type = "pci";
			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
			/* Map all possible DDR as inbound ranges */
			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>,
				     <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
			clock-names = "pcie", "pcie_bus";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 319>;
			status = "disabled";
		};

		vsp@fe920000 {
			compatible = "renesas,vsp1";
			reg = <0 0xfe920000 0 0x8000>;
			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 130>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 130>;
		};

		vsp@fe928000 {
			compatible = "renesas,vsp1";
			reg = <0 0xfe928000 0 0x8000>;
			interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 131>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 131>;
		};

		vsp@fe930000 {
			compatible = "renesas,vsp1";
			reg = <0 0xfe930000 0 0x8000>;
			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 128>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 128>;
		};

		vsp@fe938000 {
			compatible = "renesas,vsp1";
			reg = <0 0xfe938000 0 0x8000>;
			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 127>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 127>;
		};

		du: display@feb00000 {
			compatible = "renesas,du-r8a7742";
			reg = <0 0xfeb00000 0 0x70000>;
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
				 <&cpg CPG_MOD 722>;
			clock-names = "du.0", "du.1", "du.2";
			resets = <&cpg 724>;
			reset-names = "du.0";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					du_out_rgb: endpoint {
					};
				};
				port@1 {
					reg = <1>;
					du_out_lvds0: endpoint {
						remote-endpoint = <&lvds0_in>;
					};
				};
				port@2 {
					reg = <2>;
					du_out_lvds1: endpoint {
						remote-endpoint = <&lvds1_in>;
					};
				};
			};
		};

		lvds0: lvds@feb90000 {
			compatible = "renesas,r8a7742-lvds";
			reg = <0 0xfeb90000 0 0x14>;
			clocks = <&cpg CPG_MOD 726>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 726>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					lvds0_in: endpoint {
						remote-endpoint = <&du_out_lvds0>;
					};
				};
				port@1 {
					reg = <1>;
					lvds0_out: endpoint {
					};
				};
			};
		};

		lvds1: lvds@feb94000 {
			compatible = "renesas,r8a7742-lvds";
			reg = <0 0xfeb94000 0 0x14>;
			clocks = <&cpg CPG_MOD 725>;
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 725>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					lvds1_in: endpoint {
						remote-endpoint = <&du_out_lvds1>;
					};
				};
				port@1 {
					reg = <1>;
					lvds1_out: endpoint {
					};
				};
			};
		};

		prr: chipid@ff000044 {
			compatible = "renesas,prr";
			reg = <0 0xff000044 0 4>;
		};

		cmt0: timer@ffca0000 {
			compatible = "renesas,r8a7742-cmt0",
				     "renesas,rcar-gen2-cmt0";
			reg = <0 0xffca0000 0 0x1004>;
			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 124>;
			clock-names = "fck";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 124>;
			status = "disabled";
		};

		cmt1: timer@e6130000 {
			compatible = "renesas,r8a7742-cmt1",
				     "renesas,rcar-gen2-cmt1";
			reg = <0 0xe6130000 0 0x1004>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 329>;
			clock-names = "fck";
			power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
			resets = <&cpg 329>;
			status = "disabled";
		};
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;

			thermal-sensors = <&thermal>;

			trips {
				cpu-crit {
					temperature = <95000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
			cooling-maps {
			};
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clock - can be overridden by the board */
	usb_extal_clk: usb_extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <48000000>;
	};
};