code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Hardware Synchronization Primitives (HSP)

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: |
  The HSP modules are used for the processors to share resources and
  communicate together. It provides a set of hardware synchronization
  primitives for interprocessor communication. So the interprocessor
  communication (IPC) protocols can use hardware synchronization
  primitives, when operating between two processors not in an SMP
  relationship.

  The features that HSP supported are shared mailboxes, shared
  semaphores, arbitrated semaphores and doorbells.

  The mbox specifier of the "mboxes" property in the client node should
  contain two cells. The first cell determines the HSP type and the
  second cell is used to identify the mailbox that the client is going
  to use.

  For shared mailboxes, the first cell composed of two fields:
    - bits 15..8:
        A bit mask of flags that further specifies the type of shared
        mailbox to be used (based on the data size). If no flag is
        specified then, 32-bit shared mailbox is used.
    - bits 7..0:
        Defines the type of the mailbox to be used. This field should be
        TEGRA_HSP_MBOX_TYPE_SM for shared mailboxes.

  For doorbells, the second cell specifies the index of the doorbell to
  use.

  For shared mailboxes, the second cell is composed of two fields:
    - bits 31..24:
        A bit mask of flags that further specify how the shared mailbox
        will be used. Valid flags are:
          - bit 31:
              Defines the direction of the mailbox. If set, the mailbox
              will be used as a producer (i.e. used to send data). If
              cleared, the mailbox is the consumer of data sent by a
              producer.

    - bits 23..0:
        The index of the shared mailbox to use. The number of available
        mailboxes may vary by instance of the HSP block and SoC
        generation.

    The following file contains definitions that can be used to
    construct mailbox specifiers:

        <dt-bindings/mailbox/tegra186-hsp.h>

properties:
  $nodename:
    pattern: "^hsp@[0-9a-f]+$"

  compatible:
    oneOf:
      - const: nvidia,tegra186-hsp
      - const: nvidia,tegra194-hsp
      - items:
          - const: nvidia,tegra234-hsp
          - const: nvidia,tegra194-hsp

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 9

  interrupt-names:
    oneOf:
      # shared interrupts are optional
      - items:
          - const: doorbell

      - items:
          - const: doorbell
          - pattern: "^shared[0-7]$"
          - pattern: "^shared[0-7]$"
          - pattern: "^shared[0-7]$"
          - pattern: "^shared[0-7]$"
          - pattern: "^shared[0-7]$"
          - pattern: "^shared[0-7]$"
          - pattern: "^shared[0-7]$"
          - pattern: "^shared[0-7]$"

      - items:
          - pattern: "^shared[0-7]$"
          - pattern: "^shared[0-7]$"
          - pattern: "^shared[0-7]$"
          - pattern: "^shared[0-7]$"

  "#mbox-cells":
    const: 2

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/mailbox/tegra186-hsp.h>

    hsp_top0: hsp@3c00000 {
        compatible = "nvidia,tegra186-hsp";
        reg = <0x03c00000 0xa0000>;
        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "doorbell";
        #mbox-cells = <2>;
    };

    client {
        mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm APCS global block bindings

description:
  This binding describes the APCS "global" block found in various Qualcomm
  platforms.

maintainers:
  - Jassi Brar <jassisinghbrar@gmail.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - qcom,ipq6018-apcs-apps-global
              - qcom,ipq8074-apcs-apps-global
              - qcom,msm8976-apcs-kpss-global
              - qcom,msm8996-apcs-hmss-global
              - qcom,msm8998-apcs-hmss-global
              - qcom,qcm2290-apcs-hmss-global
              - qcom,sc7180-apss-shared
              - qcom,sc8180x-apss-shared
              - qcom,sdm660-apcs-hmss-global
              - qcom,sdm845-apss-shared
              - qcom,sm6125-apcs-hmss-global
              - qcom,sm6115-apcs-hmss-global
              - qcom,sm8150-apss-shared
      - items:
          - enum:
              - qcom,msm8916-apcs-kpss-global
              - qcom,msm8939-apcs-kpss-global
              - qcom,msm8953-apcs-kpss-global
              - qcom,msm8994-apcs-kpss-global
              - qcom,qcs404-apcs-apps-global
          - const: syscon
  reg:
    maxItems: 1

  clocks:
    description: phandles to the parent clocks of the clock driver
    minItems: 2
    maxItems: 3

  '#mbox-cells':
    const: 1

  '#clock-cells':
    enum: [0, 1]

  clock-names:
    minItems: 2
    maxItems: 3

required:
  - compatible
  - reg
  - '#mbox-cells'

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          enum:
            - qcom,msm8916-apcs-kpss-global
            - qcom,msm8994-apcs-kpss-global
            - qcom,msm8996-apcs-hmss-global
            - qcom,msm8998-apcs-hmss-global
            - qcom,qcs404-apcs-apps-global
            - qcom,sc7180-apss-shared
            - qcom,sdm660-apcs-hmss-global
            - qcom,sdm845-apss-shared
            - qcom,sm6125-apcs-hmss-global
            - qcom,sm8150-apss-shared
    then:
      properties:
        clocks:
          items:
            - description: primary pll parent of the clock driver
            - description: auxiliary parent
        clock-names:
          items:
            - const: pll
            - const: aux
  - if:
      properties:
        compatible:
          enum:
            - qcom,sdx55-apcs-gcc
    then:
      properties:
        clocks:
          items:
            - description: primary pll parent of the clock driver
            - description: auxiliary parent
            - description: reference clock
        clock-names:
          items:
            - const: pll
            - const: aux
            - const: ref
  - if:
      properties:
        compatible:
          enum:
            - qcom,ipq6018-apcs-apps-global
            - qcom,ipq8074-apcs-apps-global
    then:
      properties:
        clocks:
          items:
            - description: primary pll parent of the clock driver
            - description: XO clock
        clock-names:
          items:
            - const: pll
            - const: xo
  - if:
      properties:
        compatible:
          enum:
            - qcom,ipq6018-apcs-apps-global
            - qcom,ipq8074-apcs-apps-global
    then:
      properties:
        '#clock-cells':
          const: 1
    else:
      properties:
        '#clock-cells':
          const: 0

examples:

  # Example apcs with msm8996
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    apcs_glb: mailbox@9820000 {
        compatible = "qcom,msm8996-apcs-hmss-global";
        reg = <0x9820000 0x1000>;

        #mbox-cells = <1>;
    };

    rpm-glink {
        compatible = "qcom,glink-rpm";
        interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
        qcom,rpm-msg-ram = <&rpm_msg_ram>;
        mboxes = <&apcs_glb 0>;
        mbox-names = "rpm_hlos";
    };

  # Example apcs with qcs404
  - |
    #define GCC_APSS_AHB_CLK_SRC  1
    #define GCC_GPLL0_AO_OUT_MAIN 123
    apcs: mailbox@b011000 {
        compatible = "qcom,qcs404-apcs-apps-global", "syscon";
        reg = <0x0b011000 0x1000>;
        #mbox-cells = <1>;
        clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
        clock-names = "pll", "aux";
        #clock-cells = <0>;
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

description:
  The Inter-Processor Communication Controller (IPCC) is a centralized hardware
  to route interrupts across various subsystems. It involves a three-level
  addressing scheme called protocol, client and signal. For example, consider an
  entity on the Application Processor Subsystem (APSS) that wants to listen to
  Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
  a case, the client would be Modem (client-id is 2) and the signal would be
  SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
  protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
  for the list of such IDs.

properties:
  compatible:
    items:
      - enum:
          - qcom,sm6350-ipcc
          - qcom,sm6375-ipcc
          - qcom,sm8250-ipcc
          - qcom,sm8350-ipcc
          - qcom,sm8450-ipcc
          - qcom,sc7280-ipcc
      - const: qcom,ipcc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-controller: true

  "#interrupt-cells":
    const: 3
    description:
      The first cell is the client-id, the second cell is the signal-id and the
      third cell is the interrupt type.

  "#mbox-cells":
    const: 2
    description:
      The first cell is the client-id, and the second cell is the signal-id.

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - "#interrupt-cells"
  - "#mbox-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/mailbox/qcom-ipcc.h>

    mailbox@408000 {
        compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
        reg = <0x408000 0x1000>;
        interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <3>;
        #mbox-cells = <2>;
    };


code:
Rockchip mailbox

The Rockchip mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processor.

Refer to ./mailbox.txt for generic information about mailbox device-tree
bindings.

Required properties:

 - compatible: should be one of the following.
   - "rockchip,rk3368-mbox" for rk3368
 - reg: physical base address of the controller and length of memory mapped
	region.
 - interrupts: The interrupt number to the cpu. The interrupt specifier format
	depends on the interrupt controller.
 - #mbox-cells: Common mailbox binding property to identify the number
	of cells required for the mailbox specifier. Should be 1

Example:
--------

/* RK3368 */
mbox: mbox@ff6b0000 {
	compatible = "rockchip,rk3368-mailbox";
	reg = <0x0 0xff6b0000 0x0 0x1000>,
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
	#mbox-cells = <1>;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/sprd-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Spreadtrum mailbox controller bindings

maintainers:
  - Orson Zhai <orsonzhai@gmail.com>
  - Baolin Wang <baolin.wang7@gmail.com>
  - Chunyan Zhang <zhang.lyra@gmail.com>

properties:
  compatible:
    enum:
      - sprd,sc9860-mailbox
      - sprd,sc9863a-mailbox

  reg:
    items:
      - description: inbox registers' base address
      - description: outbox registers' base address

  interrupts:
    minItems: 2
    maxItems: 3

  interrupt-names:
    minItems: 2
    items:
      - const: inbox
      - const: outbox
      - const: supp-outbox

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: enable

  "#mbox-cells":
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - "#mbox-cells"
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    mailbox: mailbox@400a0000 {
      compatible = "sprd,sc9860-mailbox";
      reg = <0x400a0000 0x8000>, <0x400a8000 0x8000>;
      #mbox-cells = <1>;
      clock-names = "enable";
      clocks = <&aon_gate 53>;
      interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "inbox", "outbox";
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: STMicroelectronics STM32 IPC controller bindings

description:
  The IPCC block provides a non blocking signaling mechanism to post and
  retrieve messages in an atomic way between two processors.
  It provides the signaling for N bidirectionnal channels. The number of
  channels (N) can be read from a dedicated register.

maintainers:
  - Fabien Dessenne <fabien.dessenne@foss.st.com>
  - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>

properties:
  compatible:
    const: st,stm32mp1-ipcc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    items:
      - description: rx channel occupied
      - description: tx channel free

  interrupt-names:
    items:
      - const: rx
      - const: tx

  wakeup-source: true

  "#mbox-cells":
    const: 1

  st,proc-id:
    description: Processor id using the mailbox (0 or 1)
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]

required:
  - compatible
  - reg
  - st,proc-id
  - clocks
  - interrupt-names
  - "#mbox-cells"
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    ipcc: mailbox@4c001000 {
      compatible = "st,stm32mp1-ipcc";
      #mbox-cells = <1>;
      reg = <0x4c001000 0x400>;
      st,proc-id = <0>;
      interrupts-extended = <&exti 61 1>,
                            <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "rx", "tx";
      clocks = <&rcc_clk IPCC>;
      wakeup-source;
    };

...


code:
ST Microelectronics Mailbox Driver

Each ST Mailbox IP currently consists of 4 instances of 32 channels.  Messages
are passed between Application and Remote processors using shared memory.

Controller
----------

Required properties:
- compatible		: Should be "st,stih407-mailbox"
- reg			: Offset and length of the device's register set
- mbox-name		: Name of the mailbox
- #mbox-cells:		: Must be 2
			  <&phandle instance channel direction>
			    phandle   : Label name of controller
			    instance  : Instance number
			    channel   : Channel number

Optional properties
- interrupts		: Contains the IRQ line for a Rx mailbox

Example:

mailbox0: mailbox@0  {
	compatible	= "st,stih407-mailbox";
	reg		= <0x08f00000 0x1000>;
	interrupts	= <GIC_SPI 1 IRQ_TYPE_NONE>;
	#mbox-cells	= <2>;
	mbox-name	= "a9";
};

Client
------

Required properties:
- compatible		: Many (See the client docs)
- reg			: Shared (between Application and Remote) memory address
- mboxes		: Standard property to specify a Mailbox (See ./mailbox.txt)
			  Cells must match 'mbox-cells' (See Controller docs above)

Optional properties
- mbox-names		: Name given to channels seen in the 'mboxes' property.

Example:

mailbox_test {
	compatible	= "mailbox-test";
	reg		= <0x[shared_memory_address], [shared_memory_size]>;
	mboxes		= <&mailbox2 0 1>, <&mailbox0 2 1>;
	mbox-names	= "tx",	"rx";
};


code:
Texas Instruments' Message Manager Driver
========================================

The Texas Instruments' Message Manager is a mailbox controller that has
configurable queues selectable at SoC(System on Chip) integration. The Message
manager is broken up into queues in different address regions that are called
"proxies" - each instance is unidirectional and is instantiated at SoC
integration level to indicate receive or transmit path.

Message Manager Device Node:
===========================
Required properties:
--------------------
- compatible:		Shall be: "ti,k2g-message-manager"
- reg-names 		queue_proxy_region - Map the queue proxy region.
			queue_state_debug_region - Map the queue state debug
			region.
- reg:			Contains the register map per reg-names.
- #mbox-cells		Shall be 2. Contains the queue ID and proxy ID in that
		        order referring to the transfer path.
- interrupt-names:	Contains interrupt names matching the rx transfer path
			for a given SoC. Receive interrupts shall be of the
			format: "rx_<QID>".
			For ti,k2g-message-manager, this shall contain:
				"rx_005", "rx_057"
- interrupts:		Contains the interrupt information corresponding to
			interrupt-names property.

Example(K2G):
------------

	msgmgr: msgmgr@2a00000 {
		compatible = "ti,k2g-message-manager";
		#mbox-cells = <2>;
		reg-names = "queue_proxy_region", "queue_state_debug_region";
		reg = <0x02a00000 0x400000>, <0x028c3400 0x400>;
		interrupt-names = "rx_005", "rx_057";
		interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
	};

	pmmc: pmmc {
		[...]
		mbox-names = "rx", "tx";
		# RX queue ID is 5, proxy ID is 2
		# TX queue ID is 0, proxy ID is 0
		mboxes= <&msgmgr 5 2>,
			<&msgmgr 0 0>;
		[...]
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI OMAP2+ and K3 Mailbox devices

maintainers:
  - Suman Anna <s-anna@ti.com>

description: |
  The OMAP Mailbox hardware facilitates communication between different
  processors using a queued mailbox interrupt mechanism. The IP block is
  external to the various processor subsystems and is connected on an
  interconnect bus. The communication is achieved through a set of registers
  for message storage and interrupt configuration registers.

  Each mailbox IP block/cluster has a certain number of h/w fifo queues and
  output interrupt lines. An output interrupt line is routed to an interrupt
  controller within a processor subsystem, and there can be more than one line
  going to a specific processor's interrupt controller. The interrupt line
  connections are fixed for an instance and are dictated by the IP integration
  into the SoC (excluding the SoCs that have an Interrupt Crossbar or an
  Interrupt Router IP). Each interrupt line is programmable through a set of
  interrupt configuration registers, and have a rx and tx interrupt source per
  h/w fifo. Communication between different processors is achieved through the
  appropriate programming of the rx and tx interrupt sources on the appropriate
  interrupt lines.

  The number of h/w fifo queues and interrupt lines dictate the usable
  registers. All the current OMAP SoCs except for the newest DRA7xx SoC has a
  single IP instance. DRA7xx has multiple instances with different number of
  h/w fifo queues and interrupt lines between different instances. The interrupt
  lines can also be routed to different processor sub-systems on DRA7xx as they
  are routed through the Crossbar, a kind of interrupt router/multiplexer. The
  K3 AM65x, J721E and J7200 SoCs has each of these instances form a cluster and
  combine multiple clusters into a single IP block present within the Main
  NavSS. The interrupt lines from all these clusters are multiplexed and routed
  to different processor subsystems over a limited number of common interrupt
  output lines of an Interrupt Router. The AM64x SoCS also uses a single IP
  block comprising of multiple clusters, but the number of clusters are
  smaller, and the interrupt output lines are connected directly to various
  processors.

  Mailbox Controller Nodes
  =========================
  A Mailbox device node is used to represent a Mailbox IP instance/cluster
  within a SoC. The sub-mailboxes (actual communication channels) are
  represented as child nodes of this parent node.

  Mailbox Users
  ==============
  A device needing to communicate with a target processor device should specify
  them using the common mailbox binding properties, "mboxes" and the optional
  "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
  for details). Each value of the mboxes property should contain a phandle to
  the mailbox controller device node and an args specifier that will be the
  phandle to the intended sub-mailbox child node to be used for communication.
  The equivalent "mbox-names" property value can be used to give a name to the
  communication channel to be used by the client user.

$defs:
  omap-mbox-descriptor:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description:
      The omap-mbox-descriptor is made of up of 3 cells and represents a single
      uni-directional communication channel. A typical sub-mailbox device uses
      two such channels - one for transmitting (Tx) and one for receiving (Rx).
    items:
      - description:
          mailbox fifo id used either for transmitting on ti,mbox-tx channel or
          for receiving on ti,mbox-rx channel (fifo_id). This is the hardware
          fifo number within a mailbox cluster.
      - description:
          irq identifier index number to use from the parent's interrupts data.
          Should be 0 for most of the cases, a positive index value is seen only
          on mailboxes that have multiple interrupt lines connected to the MPU
          processor (irq_id). This is an index number in the listed interrupts
          property in the DT nodes.
      - description:
          mailbox user id for identifying the interrupt line associated with
          generating a tx/rx fifo interrupt (usr_id). This is the hardware
          user id number within a mailbox cluster.

  omap-sub-mailbox:
    type: object
    description:
      The omap-sub-mailbox is a child node within a Mailbox controller device
      node and represents the actual communication channel used to send and
      receive messages between the host processor and a remote processor. Each
      child node should have a unique node name across all the different mailbox
      device nodes.

    properties:
      ti,mbox-tx:
        $ref: "#/$defs/omap-mbox-descriptor"
        description: sub-mailbox descriptor property defining a Tx fifo.

      ti,mbox-rx:
        $ref: "#/$defs/omap-mbox-descriptor"
        description: sub-mailbox descriptor property defining a Rx fifo.

      ti,mbox-send-noirq:
        type: boolean
        description:
          Quirk flag to allow the client user of this sub-mailbox to send
          messages without triggering a Tx ready interrupt, and to control
          the Tx ticker. Should be used only on sub-mailboxes used to
          communicate with WkupM3 remote processor on AM33xx/AM43xx SoCs.

    required:
      - ti,mbox-tx
      - ti,mbox-rx

properties:
  compatible:
    enum:
      - ti,omap2-mailbox # for OMAP2420, OMAP2430 SoCs
      - ti,omap3-mailbox # for OMAP3430, OMAP3630 SoCs
      - ti,omap4-mailbox # for OMAP44xx, OMAP54xx, AM33xx, AM43xx and DRA7xx SoCs
      - ti,am654-mailbox # for K3 AM65x, J721E and J7200 SoCs
      - ti,am64-mailbox  # for K3 AM64x SoCs

  reg:
    maxItems: 1

  interrupts:
    description:
      Contains the interrupt information for the mailbox device. The format is
      dependent on which interrupt controller the Mailbox device uses. The
      number of interrupts listed will at most be the value specified in
      ti,mbox-num-users property, but is usually limited by the number of
      interrupts reaching the main processor. An interrupt-parent property
      is required on SoCs where the interrupt lines are connected through a
      Interrupt Router before reaching the main processor's GIC.

  "#mbox-cells":
    const: 1
    description:
      The specifier is a phandle to an omap-sub-mailbox device.

  ti,mbox-num-users:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Number of targets (processor devices) that the mailbox device can
      interrupt.

  ti,mbox-num-fifos:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Number of h/w fifo queues within the mailbox IP block.

  ti,hwmods:
    $ref: /schemas/types.yaml#/definitions/string
    deprecated: true
    description:
      Name of the hwmod associated with the mailbox. This should be defined
      in the mailbox node only if the node is not defined as a child node of
      a corresponding sysc interconnect node.

      This property is only needed on some legacy OMAP SoCs which have not
      yet been converted to the ti,sysc interconnect hierarachy, but is
      otherwise considered obsolete.

patternProperties:
  "^mbox-[a-z0-9-]+$":
    $ref: "#/$defs/omap-sub-mailbox"

required:
  - compatible
  - reg
  - interrupts
  - "#mbox-cells"
  - ti,mbox-num-users
  - ti,mbox-num-fifos

allOf:
  - if:
      properties:
        compatible:
          enum:
            - ti,am654-mailbox
            - ti,am64-mailbox
    then:
      properties:
        ti,mbox-num-users:
          const: 4
        ti,mbox-num-fifos:
          const: 16
        interrupts:
          minItems: 1
          maxItems: 4

  - if:
      properties:
        compatible:
          enum:
            - ti,omap4-mailbox
    then:
      properties:
        ti,mbox-num-users:
          enum: [3, 4]
        ti,mbox-num-fifos:
          enum: [8, 12]
        interrupts:
          minItems: 1
          maxItems: 4

  - if:
      properties:
        compatible:
          enum:
            - ti,omap3-mailbox
    then:
      properties:
        ti,mbox-num-users:
          const: 2
        ti,mbox-num-fifos:
          const: 2
        interrupts:
          minItems: 1
          maxItems: 1

  - if:
      properties:
        compatible:
          enum:
            - ti,omap2-mailbox
    then:
      properties:
        ti,mbox-num-users:
          const: 4
        ti,mbox-num-fifos:
          const: 6
        interrupts:
          minItems: 1
          maxItems: 2

additionalProperties: false

examples:
  - |
    /* OMAP4 */
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    mailbox: mailbox@4a0f4000 {
        compatible = "ti,omap4-mailbox";
        reg = <0x4a0f4000 0x200>;
        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
        #mbox-cells = <1>;
        ti,mbox-num-users = <3>;
        ti,mbox-num-fifos = <8>;

        mbox_ipu: mbox-ipu {
            ti,mbox-tx = <0 0 0>;
            ti,mbox-rx = <1 0 0>;
        };
        mbox_dsp: mbox-dsp {
            ti,mbox-tx = <3 0 0>;
            ti,mbox-rx = <2 0 0>;
        };
    };

    dsp {
        mboxes = <&mailbox &mbox_dsp>;
    };

  - |
    /* AM33xx */
    mailbox1: mailbox@480c8000 {
        compatible = "ti,omap4-mailbox";
        reg = <0x480c8000 0x200>;
        interrupts = <77>;
        #mbox-cells = <1>;
        ti,mbox-num-users = <4>;
        ti,mbox-num-fifos = <8>;

        mbox_wkupm3: mbox-wkup-m3 {
            ti,mbox-tx = <0 0 0>;
            ti,mbox-rx = <0 0 3>;
            ti,mbox-send-noirq;
        };
    };

  - |
    /* AM65x */
    mailbox0_cluster0: mailbox@31f80000 {
        compatible = "ti,am654-mailbox";
        reg = <0x31f80000 0x200>;
        #mbox-cells = <1>;
        ti,mbox-num-users = <4>;
        ti,mbox-num-fifos = <16>;
        interrupt-parent = <&intr_main_navss>;
        interrupts = <436>;

        mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
            ti,mbox-tx = <1 0 0>;
            ti,mbox-rx = <0 0 0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/ti,secure-proxy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments' Secure Proxy

maintainers:
  - Nishanth Menon <nm@ti.com>

description: |
  The Texas Instruments' secure proxy is a mailbox controller that has
  configurable queues selectable at SoC(System on Chip) integration. The
  Message manager is broken up into different address regions that are
  called "threads" or "proxies" - each instance is unidirectional and is
  instantiated at SoC integration level by system controller to indicate
  receive or transmit path.

properties:
  $nodename:
    pattern: "^mailbox@[0-9a-f]+$"

  compatible:
    const: ti,am654-secure-proxy

  "#mbox-cells":
    const: 1
    description:
      Contains the secure proxy thread ID used for the specific transfer path.

  reg-names:
    items:
      - const: target_data
      - const: rt
      - const: scfg

  reg:
    minItems: 3

  interrupt-names:
    minItems: 1
    maxItems: 100
    items:
      pattern: "^rx_[0-9]{3}$"
    description:
      Contains the interrupt name information for the Rx interrupt path for
      secure proxy thread in the form 'rx_<PID>'.

  interrupts:
    minItems: 1
    maxItems: 100
    description:
      Contains the interrupt information for the Rx interrupt path for secure
      proxy.

required:
  - compatible
  - reg-names
  - reg
  - interrupt-names
  - interrupts
  - "#mbox-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    secure_proxy: mailbox@32c00000 {
          compatible = "ti,am654-secure-proxy";
          #mbox-cells = <1>;
          reg-names = "target_data", "rt", "scfg";
          reg = <0x32c00000 0x100000>,
                <0x32400000 0x100000>,
                <0x32800000 0x100000>;
          interrupt-names = "rx_011";
          interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
    };


code:
The APM X-Gene SLIMpro mailbox is used to communicate messages between
the ARM64 processors and the Cortex M3 (dubbed SLIMpro). It uses a simple
interrupt based door bell mechanism and can exchange simple messages using the
internal registers.

There are total of 8 interrupts in this mailbox. Each used for an individual
door bell (or mailbox channel).

Required properties:
- compatible:	Should be as "apm,xgene-slimpro-mbox".

- reg:		Contains the mailbox register address range.

- interrupts:	8 interrupts must be from 0 to 7, interrupt 0 define the
		the interrupt for mailbox channel 0 and interrupt 1 for
		mailbox channel 1 and so likewise for the reminder.

- #mbox-cells:	only one to specify the mailbox channel number.

Example:

Mailbox Node:
		mailbox: mailbox@10540000 {
			compatible = "apm,xgene-slimpro-mbox";
			reg = <0x0 0x10540000 0x0 0xa000>;
			#mbox-cells = <1>;
			interrupts =  	<0x0 0x0 0x4>,
					<0x0 0x1 0x4>,
					<0x0 0x2 0x4>,
					<0x0 0x3 0x4>,
					<0x0 0x4 0x4>,
					<0x0 0x5 0x4>,
					<0x0 0x6 0x4>,
					<0x0 0x7 0x4>,
		};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Xilinx IPI(Inter Processor Interrupt) mailbox controller

description: |
  The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
  messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
  agent owns registers used for notification and buffers for message.

               +-------------------------------------+
               | Xilinx ZynqMP IPI Controller        |
               +-------------------------------------+
    +--------------------------------------------------+
  TF-A                   |                     |
                         |                     |
                         |                     |
    +--------------------------+               |
                         |                     |
                         |                     |
    +--------------------------------------------------+
              +------------------------------------------+
              |  +----------------+   +----------------+ |
  Hardware    |  |  IPI Agent     |   |  IPI Buffers   | |
              |  |  Registers     |   |                | |
              |  |                |   |                | |
              |  +----------------+   +----------------+ |
              |                                          |
              | Xilinx IPI Agent Block                   |
              +------------------------------------------+

maintainers:
  - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>

properties:
  compatible:
    const: xlnx,zynqmp-ipi-mailbox

  method:
    description: |
      The method of calling the PM-API firmware layer.
      Permitted values are.
      - "smc" : SMC #0, following the SMCCC
      - "hvc" : HVC #0, following the SMCCC

    $ref: /schemas/types.yaml#/definitions/string
    enum:
      - smc
      - hvc
    default: smc

  '#address-cells':
    const: 2

  '#size-cells':
    const: 2

  xlnx,ipi-id:
    description: |
      Remote Xilinx IPI agent ID of which the mailbox is connected to.
    $ref: /schemas/types.yaml#/definitions/uint32

  interrupts:
    maxItems: 1

  ranges: true

patternProperties:
  '^mailbox@[0-9a-f]+$':
    description: Internal ipi mailbox node
    type: object  # DT nodes are json objects
    properties:
      xlnx,ipi-id:
        description:
          Remote Xilinx IPI agent ID of which the mailbox is connected to.
        $ref: /schemas/types.yaml#/definitions/uint32

      '#mbox-cells':
        const: 1
        description:
          It contains tx(0) or rx(1) channel IPI id number.

      reg:
        maxItems: 4

      reg-names:
        items:
          - const: local_request_region
          - const: local_response_region
          - const: remote_request_region
          - const: remote_response_region

    required:
      - reg
      - reg-names
      - "#mbox-cells"

additionalProperties: false

required:
  - compatible
  - interrupts
  - '#address-cells'
  - '#size-cells'
  - xlnx,ipi-id

examples:
  - |
    #include<dt-bindings/interrupt-controller/arm-gic.h>

    amba {
      #address-cells = <0x2>;
      #size-cells = <0x2>;
      zynqmp-mailbox {
        compatible = "xlnx,zynqmp-ipi-mailbox";
        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
        xlnx,ipi-id = <0>;
        #address-cells = <2>;
        #size-cells = <2>;
        ranges;

        mailbox: mailbox@ff9905c0 {
          reg = <0x0 0xff9905c0 0x0 0x20>,
                <0x0 0xff9905e0 0x0 0x20>,
                <0x0 0xff990e80 0x0 0x20>,
                <0x0 0xff990ea0 0x0 0x20>;
          reg-names = "local_request_region",
                      "local_response_region",
                      "remote_request_region",
                      "remote_response_region";
          #mbox-cells = <1>;
          xlnx,ipi-id = <4>;
        };
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allegro,al5e.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allegro DVT Video IP Codecs

maintainers:
  - Michael Tretter <m.tretter@pengutronix.de>

description: |-
  Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may
  either be a H.264/H.265 encoder or H.264/H.265 decoder ip core.

  Each actual codec engine is controlled by a microcontroller (MCU). Host
  software uses a provided mailbox interface to communicate with the MCU. The
  MCUs share an interrupt.

properties:
  compatible:
    oneOf:
      - items:
          - const: allegro,al5e-1.1
          - const: allegro,al5e
      - items:
          - const: allegro,al5d-1.1
          - const: allegro,al5d

  reg:
    items:
      - description: The registers
      - description: The SRAM

  reg-names:
    items:
      - const: regs
      - const: sram

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Core clock
      - description: MCU clock
      - description: Core AXI master port clock
      - description: MCU AXI master port clock
      - description: AXI4-Lite slave port clock

  clock-names:
    items:
      - const: core_clk
      - const: mcu_clk
      - const: m_axi_core_aclk
      - const: m_axi_mcu_aclk
      - const: s_axi_lite_aclk

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names

additionalProperties: False

examples:
  - |
    fpga {
        #address-cells = <2>;
        #size-cells = <2>;

        al5e: video-codec@a0009000 {
            compatible = "allegro,al5e-1.1", "allegro,al5e";
            reg = <0 0xa0009000 0 0x1000>,
            <0 0xa0000000 0 0x8000>;
            reg-names = "regs", "sram";
            interrupts = <0 96 4>;
            clocks = <&xlnx_vcu 0>, <&xlnx_vcu 1>,
            <&clkc 71>, <&clkc 71>, <&clkc 71>;
            clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
            "m_axi_mcu_aclk", "s_axi_lite_aclk";
        };
    };
  - |
    fpga {
        #address-cells = <2>;
        #size-cells = <2>;

        al5d: video-codec@a0029000 {
            compatible = "allegro,al5d-1.1", "allegro,al5d";
            reg = <0 0xa0029000 0 0x1000>,
                  <0 0xa0020000 0 0x8000>;
            reg-names = "regs", "sram";
            interrupts = <0 96 4>;
            clocks = <&xlnx_vcu 2>, <&xlnx_vcu 3>,
                     <&clkc 71>, <&clkc 71>, <&clkc 71>;
            clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",
            "m_axi_mcu_aclk", "s_axi_lite_aclk";
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 CMOS Sensor Interface (CSI)

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |-
  The Allwinner A10 and later has a CMOS Sensor Interface to retrieve
  frames from a parallel or BT656 sensor.

properties:
  compatible:
    oneOf:
      - const: allwinner,sun4i-a10-csi1
      - const: allwinner,sun7i-a20-csi0
      - items:
          - const: allwinner,sun7i-a20-csi1
          - const: allwinner,sun4i-a10-csi1
      - items:
          - const: allwinner,sun8i-r40-csi0
          - const: allwinner,sun7i-a20-csi0

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    oneOf:
      - items:
          - description: The CSI interface clock
          - description: The CSI DRAM clock

      - items:
          - description: The CSI interface clock
          - description: The CSI ISP clock
          - description: The CSI DRAM clock

  clock-names:
    oneOf:
      - items:
          - const: bus
          - const: ram

      - items:
          - const: bus
          - const: isp
          - const: ram

  resets:
    maxItems: 1

  # FIXME: This should be made required eventually once every SoC will
  # have the MBUS declared.
  interconnects:
    maxItems: 1

  # FIXME: This should be made required eventually once every SoC will
  # have the MBUS declared.
  interconnect-names:
    const: dma-mem

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    additionalProperties: false

    properties:
      endpoint:
        $ref: video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          bus-width:
            enum: [8, 16]

          data-active: true
          hsync-active: true
          pclk-sample: true
          vsync-active: true

        required:
          - bus-width
          - data-active
          - hsync-active
          - pclk-sample
          - vsync-active

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun7i-a20-ccu.h>
    #include <dt-bindings/reset/sun4i-a10-ccu.h>

    csi0: csi@1c09000 {
        compatible = "allwinner,sun7i-a20-csi0";
        reg = <0x01c09000 0x1000>;
        interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
        clock-names = "bus", "isp", "ram";
        resets = <&ccu RST_CSI0>;

        port {
            csi_from_ov5640: endpoint {
                remote-endpoint = <&ov5640_to_csi>;
                bus-width = <8>;
                hsync-active = <1>; /* Active high */
                vsync-active = <0>; /* Active low */
                data-active = <1>;  /* Active high */
                pclk-sample = <1>;  /* Rising */
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-ir.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 Infrared Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

allOf:
  - $ref: "rc.yaml#"

properties:
  compatible:
    oneOf:
      - const: allwinner,sun4i-a10-ir
      - const: allwinner,sun5i-a13-ir
      - const: allwinner,sun6i-a31-ir
      - items:
          - enum:
              - allwinner,suniv-f1c100s-ir
              - allwinner,sun8i-a83t-ir
              - allwinner,sun8i-r40-ir
              - allwinner,sun50i-a64-ir
              - allwinner,sun50i-h6-ir
              - allwinner,sun50i-h616-ir
          - const: allwinner,sun6i-a31-ir

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Bus Clock
      - description: Module Clock

  clock-names:
    items:
      - const: apb
      - const: ir

  resets:
    maxItems: 1

  clock-frequency:
    default: 8000000
    description:
      IR Receiver clock frequency, in Hertz.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
      ir0: ir@1c21800 {
          compatible = "allwinner,sun4i-a10-ir";
          clocks = <&apb0_gates 6>, <&ir0_clk>;
          clock-names = "apb", "ir";
          clock-frequency = <3000000>;
          resets = <&apb0_rst 1>;
          interrupts = <0 5 1>;
          reg = <0x01C21800 0x40>;
          linux,rc-map-name = "rc-rc6-mce";
      };

...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 Video Engine

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    enum:
      - allwinner,sun4i-a10-video-engine
      - allwinner,sun5i-a13-video-engine
      - allwinner,sun7i-a20-video-engine
      - allwinner,sun8i-a33-video-engine
      - allwinner,sun8i-h3-video-engine
      - allwinner,sun8i-v3s-video-engine
      - allwinner,sun8i-r40-video-engine
      - allwinner,sun20i-d1-video-engine
      - allwinner,sun50i-a64-video-engine
      - allwinner,sun50i-h5-video-engine
      - allwinner,sun50i-h6-video-engine

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Bus Clock
      - description: Module Clock
      - description: RAM Clock

  clock-names:
    items:
      - const: ahb
      - const: mod
      - const: ram

  resets:
    maxItems: 1

  allwinner,sram:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to SRAM
          - description: register value for device
    description: Phandle to the device SRAM

  iommus:
    maxItems: 1

  memory-region:
    maxItems: 1
    description:
      CMA pool to use for buffers allocation instead of the default
      CMA pool.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - allwinner,sram

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun7i-a20-ccu.h>
    #include <dt-bindings/reset/sun4i-a10-ccu.h>

    video-codec@1c0e000 {
        compatible = "allwinner,sun7i-a20-video-engine";
        reg = <0x01c0e000 0x1000>;
        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
                 <&ccu CLK_DRAM_VE>;
        clock-names = "ahb", "mod", "ram";
        resets = <&ccu RST_VE>;
        allwinner,sram = <&ve_sram 1>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/allwinner,sun50i-h6-vpu-g2.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Hantro G2 VPU codec implemented on Allwinner H6 SoC

maintainers:
  - Jernej Skrabec <jernej.skrabec@gmail.com>

description:
  Hantro G2 video decode accelerator present on Allwinner H6 SoC.

properties:
  compatible:
    const: allwinner,sun50i-h6-vpu-g2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Bus Clock
      - description: Module Clock

  clock-names:
    items:
      - const: bus
      - const: mod

  resets:
    maxItems: 1

  iommus:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - iommus

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun50i-h6-ccu.h>
    #include <dt-bindings/reset/sun50i-h6-ccu.h>

    video-codec-g2@1c00000 {
        compatible = "allwinner,sun50i-h6-vpu-g2";
        reg = <0x01c00000 0x1000>;
        interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
        clock-names = "bus", "mod";
        resets = <&ccu RST_BUS_VP9>;
        iommus = <&iommu 5>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 CMOS Sensor Interface (CSI)

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    enum:
      - allwinner,sun6i-a31-csi
      - allwinner,sun8i-a83t-csi
      - allwinner,sun8i-h3-csi
      - allwinner,sun8i-v3s-csi
      - allwinner,sun50i-a64-csi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Bus Clock
      - description: Module Clock
      - description: DRAM Clock

  clock-names:
    items:
      - const: bus
      - const: mod
      - const: ram

  resets:
    maxItems: 1

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    description: Parallel input port, connect to a parallel sensor

    properties:
      endpoint:
        $ref: video-interfaces.yaml#
        unevaluatedProperties: false

        properties:
          bus-width:
            enum: [ 8, 10, 12, 16 ]

          pclk-sample: true
          hsync-active: true
          vsync-active: true

        required:
          - bus-width

    unevaluatedProperties: false

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: "#/properties/port"

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: MIPI CSI-2 bridge input port

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: Internal output port to the ISP

    anyOf:
      - required:
          - port@0
      - required:
          - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets

oneOf:
  - required:
      - ports
  - required:
      - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun8i-v3s-ccu.h>
    #include <dt-bindings/reset/sun8i-v3s-ccu.h>

    csi1: csi@1cb4000 {
        compatible = "allwinner,sun8i-v3s-csi";
        reg = <0x01cb4000 0x1000>;
        interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_CSI>,
                 <&ccu CLK_CSI1_SCLK>,
                 <&ccu CLK_DRAM_CSI>;
        clock-names = "bus",
                      "mod",
                      "ram";
        resets = <&ccu RST_BUS_CSI>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                /* Parallel bus endpoint */
                csi1_ep: endpoint {
                    remote-endpoint = <&adv7611_ep>;
                    bus-width = <16>;

                    /*
                     * If hsync-active/vsync-active are missing,
                     * embedded BT.656 sync is used.
                     */
                    hsync-active = <0>; /* Active low */
                    vsync-active = <0>; /* Active low */
                    pclk-sample = <1>;  /* Rising */
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-isp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 Image Signal Processor Driver (ISP) Device Tree Bindings

maintainers:
  - Paul Kocialkowski <paul.kocialkowski@bootlin.com>

properties:
  compatible:
    enum:
      - allwinner,sun6i-a31-isp
      - allwinner,sun8i-v3s-isp

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Bus Clock
      - description: Module Clock
      - description: DRAM Clock

  clock-names:
    items:
      - const: bus
      - const: mod
      - const: ram

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: CSI0 input port

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: CSI1 input port

    if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun8i-v3s-isp
    then:
      required:
        - port@0

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun8i-v3s-ccu.h>
    #include <dt-bindings/reset/sun8i-v3s-ccu.h>

    isp: isp@1cb8000 {
        compatible = "allwinner,sun8i-v3s-isp";
        reg = <0x01cb8000 0x1000>;
        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_CSI>,
             <&ccu CLK_CSI1_SCLK>,
             <&ccu CLK_DRAM_CSI>;
        clock-names = "bus", "mod", "ram";
        resets = <&ccu RST_BUS_CSI>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                isp_in_csi0: endpoint {
                    remote-endpoint = <&csi0_out_isp>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 MIPI CSI-2

maintainers:
  - Paul Kocialkowski <paul.kocialkowski@bootlin.com>

properties:
  compatible:
    oneOf:
      - const: allwinner,sun6i-a31-mipi-csi2
      - items:
          - const: allwinner,sun8i-v3s-mipi-csi2
          - const: allwinner,sun6i-a31-mipi-csi2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Bus Clock
      - description: Module Clock

  clock-names:
    items:
      - const: bus
      - const: mod

  phys:
    maxItems: 1
    description: MIPI D-PHY

  phy-names:
    items:
      - const: dphy

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        description: Input port, connect to a MIPI CSI-2 sensor

        properties:
          reg:
            const: 0

          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

        unevaluatedProperties: false

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Output port, connect to a CSI controller

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - phys
  - phy-names
  - resets
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun8i-v3s-ccu.h>
    #include <dt-bindings/reset/sun8i-v3s-ccu.h>

    mipi_csi2: csi@1cb1000 {
        compatible = "allwinner,sun8i-v3s-mipi-csi2",
                     "allwinner,sun6i-a31-mipi-csi2";
        reg = <0x01cb1000 0x1000>;
        interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_CSI>,
                 <&ccu CLK_CSI1_SCLK>;
        clock-names = "bus", "mod";
        resets = <&ccu RST_BUS_CSI>;

        phys = <&dphy>;
        phy-names = "dphy";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            mipi_csi2_in: port@0 {
                reg = <0>;

                mipi_csi2_in_ov5648: endpoint {
                    data-lanes = <1 2 3 4>;

                    remote-endpoint = <&ov5648_out_mipi_csi2>;
                };
            };

            mipi_csi2_out: port@1 {
                reg = <1>;

                mipi_csi2_out_csi0: endpoint {
                    remote-endpoint = <&csi0_in_mipi_csi2>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-de2-rotate.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A83T DE2 Rotate

maintainers:
  - Jernej Skrabec <jernej.skrabec@siol.net>
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |-
  The Allwinner A83T and A64 have a rotation core used for
  rotating and flipping images.

properties:
  compatible:
    oneOf:
      - const: allwinner,sun8i-a83t-de2-rotate
      - items:
          - const: allwinner,sun50i-a64-de2-rotate
          - const: allwinner,sun8i-a83t-de2-rotate

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Rotate interface clock
      - description: Rotate module clock

  clock-names:
    items:
      - const: bus
      - const: mod

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun8i-de2.h>
    #include <dt-bindings/reset/sun8i-de2.h>

    rotate: rotate@1020000 {
        compatible = "allwinner,sun8i-a83t-de2-rotate";
        reg = <0x1020000 0x10000>;
        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&display_clocks CLK_BUS_ROT>,
                 <&display_clocks CLK_ROT>;
        clock-names = "bus",
                      "mod";
        resets = <&display_clocks RST_ROT>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A83T MIPI CSI-2

maintainers:
  - Paul Kocialkowski <paul.kocialkowski@bootlin.com>

properties:
  compatible:
    const: allwinner,sun8i-a83t-mipi-csi2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Bus Clock
      - description: Module Clock
      - description: MIPI-specific Clock
      - description: Misc CSI Clock

  clock-names:
    items:
      - const: bus
      - const: mod
      - const: mipi
      - const: misc

  resets:
    maxItems: 1

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        description: Input port, connect to a MIPI CSI-2 sensor

        properties:
          reg:
            const: 0

          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

        unevaluatedProperties: false

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Output port, connect to a CSI controller

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun8i-a83t-ccu.h>
    #include <dt-bindings/reset/sun8i-a83t-ccu.h>

    mipi_csi2: csi@1cb1000 {
        compatible = "allwinner,sun8i-a83t-mipi-csi2";
        reg = <0x01cb1000 0x1000>;
        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ccu CLK_BUS_CSI>,
                 <&ccu CLK_CSI_SCLK>,
                 <&ccu CLK_MIPI_CSI>,
                 <&ccu CLK_CSI_MISC>;
        clock-names = "bus", "mod", "mipi", "misc";
        resets = <&ccu RST_BUS_CSI>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            mipi_csi2_in: port@0 {
                reg = <0>;

                mipi_csi2_in_ov8865: endpoint {
                    data-lanes = <1 2 3 4>;

                    remote-endpoint = <&ov8865_out_mipi_csi2>;
                };
            };

            mipi_csi2_out: port@1 {
                reg = <1>;

                mipi_csi2_out_csi: endpoint {
                    remote-endpoint = <&csi_in_mipi_csi2>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun8i-h3-deinterlace.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner H3 Deinterlace

maintainers:
  - Jernej Skrabec <jernej.skrabec@siol.net>
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |-
  The Allwinner H3 and later has a deinterlace core used for
  deinterlacing interlaced video content.

properties:
  compatible:
    oneOf:
      - const: allwinner,sun8i-h3-deinterlace
      - items:
          - const: allwinner,sun8i-r40-deinterlace
          - const: allwinner,sun8i-h3-deinterlace
      - items:
          - const: allwinner,sun50i-a64-deinterlace
          - const: allwinner,sun8i-h3-deinterlace

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Deinterlace interface clock
      - description: Deinterlace module clock
      - description: Deinterlace DRAM clock

  clock-names:
    items:
      - const: bus
      - const: mod
      - const: ram

  resets:
    maxItems: 1

  interconnects:
    maxItems: 1

  interconnect-names:
    const: dma-mem

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/sun8i-h3-ccu.h>
    #include <dt-bindings/reset/sun8i-h3-ccu.h>

    deinterlace: deinterlace@1400000 {
        compatible = "allwinner,sun8i-h3-deinterlace";
        reg = <0x01400000 0x20000>;
        clocks = <&ccu CLK_BUS_DEINTERLACE>,
                 <&ccu CLK_DEINTERLACE>,
                 <&ccu CLK_DRAM_DEINTERLACE>;
        clock-names = "bus", "mod", "ram";
        resets = <&ccu RST_BUS_DEINTERLACE>;
        interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
        interconnects = <&mbus 9>;
        interconnect-names = "dma-mem";
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/amlogic,axg-ge2d.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic GE2D Acceleration Unit

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

properties:
  compatible:
    enum:
      - amlogic,axg-ge2d

  interrupts:
    minItems: 1

  reg:
    minItems: 1

  resets:
    maxItems: 1

  clocks:
    minItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - resets

additionalProperties: false

examples:
  - |
    ge2d: ge2d@ff940000 {
          compatible = "amlogic,axg-ge2d";
          reg = <0xff940000 0x10000>;
          interrupts = <150>;
          clocks = <&clk_ge2d>;
          resets = <&reset_ge2d>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/amlogic,gx-vdec.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Video Decoder

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>
  - Maxime Jourdan <mjourdan@baylibre.com>

description: |
  The video decoding IP lies within the DOS memory region,
  except for the hardware bitstream parser that makes use of an undocumented
  region.

  It makes use of the following blocks:
  - ESPARSER is a bitstream parser that outputs to a VIFIFO. Further VDEC blocks
    then feed from this VIFIFO.
  - VDEC_1 can decode MPEG-1, MPEG-2, MPEG-4 part 2, MJPEG, H.263, H.264, VC-1.
  - VDEC_HEVC can decode HEVC and VP9.

  Both VDEC_1 and VDEC_HEVC share the "vdec" IRQ and as such cannot run
  concurrently.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - amlogic,gxbb-vdec # GXBB (S905)
              - amlogic,gxl-vdec # GXL (S905X, S905D)
              - amlogic,gxm-vdec # GXM (S912)
          - const: amlogic,gx-vdec
      - enum:
          - amlogic,g12a-vdec # G12A (S905X2, S905D2)
          - amlogic,sm1-vdec # SM1 (S905X3, S905D3)

  interrupts:
    minItems: 2

  interrupt-names:
    items:
      - const: vdec
      - const: esparser

  reg:
    minItems: 2

  reg-names:
    items:
      - const: dos
      - const: esparser

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: esparser

  clocks:
    minItems: 4
    maxItems: 5

  clock-names:
    minItems: 4
    items:
      - const: dos_parser
      - const: dos
      - const: vdec_1
      - const: vdec_hevc
      - const: vdec_hevcf

  amlogic,ao-sysctrl:
    description: should point to the AOBUS sysctrl node
    $ref: /schemas/types.yaml#/definitions/phandle

  amlogic,canvas:
    description: should point to a canvas provider node
    $ref: /schemas/types.yaml#/definitions/phandle

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - amlogic,gx-vdec

    then:
      properties:
        clock-names:
          maxItems: 4

  - if:
      properties:
        compatible:
          contains:
            enum:
              - amlogic,g12a-vdec
              - amlogic,sm1-vdec

    then:
      properties:
        clock-names:
          minItems: 5

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - resets
  - reset-names
  - amlogic,ao-sysctrl
  - amlogic,canvas

additionalProperties: false

examples:
  - |
    vdec: video-decoder@c8820000 {
          compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
          reg = <0xc8820000 0x10000>, <0xc110a580 0xe4>;
          reg-names = "dos", "esparser";
          interrupts = <44>, <32>;
          interrupt-names = "vdec", "esparser";
          clocks = <&clk_dos_parser> ,<&clk_dos>, <&clk_vdec_1>, <&clk_vdec_hevc>;
          clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
          resets = <&reset_parser>;
          reset-names = "esparser";
          amlogic,ao-sysctrl = <&sysctrl_AO>;
          amlogic,canvas = <&canvas>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/amlogic,meson-gx-ao-cec.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Meson AO-CEC Controller

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

description: |
  The Amlogic Meson AO-CEC module is present is Amlogic SoCs and its purpose is
  to handle communication between HDMI connected devices over the CEC bus.

properties:
  compatible:
    enum:
      - amlogic,meson-gx-ao-cec # GXBB, GXL, GXM, G12A and SM1 AO_CEC_A module
      - amlogic,meson-g12a-ao-cec # G12A AO_CEC_B module
      - amlogic,meson-sm1-ao-cec # SM1 AO_CEC_B module

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    maxItems: 1

  interrupts:
    maxItems: 1

  hdmi-phandle:
    description: phandle to the HDMI controller
    $ref: /schemas/types.yaml#/definitions/phandle

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - amlogic,meson-gx-ao-cec

    then:
      properties:
        clocks:
          items:
            - description: AO-CEC clock

        clock-names:
          items:
            - const: core

  - if:
      properties:
        compatible:
          contains:
            enum:
              - amlogic,meson-g12a-ao-cec
              - amlogic,meson-sm1-ao-cec

    then:
      properties:
        clocks:
          items:
            - description: AO-CEC clock generator source

        clock-names:
          items:
            - const: oscin

required:
  - compatible
  - reg
  - interrupts
  - hdmi-phandle
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    cec_AO: cec@100 {
        compatible = "amlogic,meson-gx-ao-cec";
        reg = <0x00100 0x14>;
        interrupts = <199>;
        clocks = <&clkc_cec>;
        clock-names = "core";
        hdmi-phandle = <&hdmi_tx>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/amlogic,meson-ir-tx.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Meson IR transmitter

maintainers:
  - Viktor Prutyanov <viktor.prutyanov@phystech.edu>

description: |
  Some Amlogic SoCs such as A311D and T950D4 have IR transmitter
  (also called blaster) controller onboard. It is capable of
  sending IR signals with arbitrary carrier frequency and duty cycle.

properties:
  compatible:
    oneOf:
      - const: amlogic,meson-ir-tx
      - items:
          - const: amlogic,meson-g12a-ir-tx
          - const: amlogic,meson-ir-tx

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: sysclk
      - const: xtal

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/g12a-clkc.h>

    ir@ff80014c {
      compatible = "amlogic,meson-g12a-ir-tx", "amlogic,meson-ir-tx";
      reg = <0xff80014c 0x10>;
      interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
      clocks = <&clkc CLKID_CLK81>, <&xtal>;
      clock-names = "sysclk", "xtal";
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amphion VPU codec IP

maintainers:
  - Ming Qian <ming.qian@nxp.com>
  - Shijie Qin <shijie.qin@nxp.com>

description: |-
  The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present
  on NXP i.MX8Q SoCs.

properties:
  $nodename:
    pattern: "^vpu@[0-9a-f]+$"

  compatible:
    items:
      - enum:
          - nxp,imx8qm-vpu
          - nxp,imx8qxp-vpu

  reg:
    maxItems: 1

  power-domains:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  ranges: true

patternProperties:
  "^mailbox@[0-9a-f]+$":
    description:
      Each vpu encoder or decoder correspond a MU, which used for communication
      between driver and firmware. Implement via mailbox on driver.
    $ref: ../mailbox/fsl,mu.yaml#

  "^vpu_core@[0-9a-f]+$":
    description:
      Each core correspond a decoder or encoder, need to configure them
      separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
      has one decoder and one encoder.
    type: object

    properties:
      compatible:
        items:
          - enum:
              - nxp,imx8q-vpu-decoder
              - nxp,imx8q-vpu-encoder

      reg:
        maxItems: 1

      power-domains:
        maxItems: 1

      mbox-names:
        items:
          - const: tx0
          - const: tx1
          - const: rx

      mboxes:
        description:
          List of phandle of 2 MU channels for tx, 1 MU channel for rx.
        maxItems: 3

      memory-region:
        description:
          Phandle to the reserved memory nodes to be associated with the
          remoteproc device. The reserved memory nodes should be carveout nodes,
          and should be defined as per the bindings in
          Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
        items:
          - description: region reserved for firmware image sections.
          - description: region used for RPC shared memory between firmware and
                         driver.

    required:
      - compatible
      - reg
      - power-domains
      - mbox-names
      - mboxes
      - memory-region

    additionalProperties: false

required:
  - compatible
  - reg
  - power-domains

additionalProperties: false

examples:
  # Device node example for i.MX8QM platform:
  - |
    #include <dt-bindings/firmware/imx/rsrc.h>

    vpu: vpu@2c000000 {
      compatible = "nxp,imx8qm-vpu";
      ranges = <0x2c000000 0x2c000000 0x2000000>;
      reg = <0x2c000000 0x1000000>;
      #address-cells = <1>;
      #size-cells = <1>;
      power-domains = <&pd IMX_SC_R_VPU>;

      mu_m0: mailbox@2d000000 {
        compatible = "fsl,imx6sx-mu";
        reg = <0x2d000000 0x20000>;
        interrupts = <0 472 4>;
        #mbox-cells = <2>;
        power-domains = <&pd IMX_SC_R_VPU_MU_0>;
      };

      mu1_m0: mailbox@2d020000 {
        compatible = "fsl,imx6sx-mu";
        reg = <0x2d020000 0x20000>;
        interrupts = <0 473 4>;
        #mbox-cells = <2>;
        power-domains = <&pd IMX_SC_R_VPU_MU_1>;
      };

      mu2_m0: mailbox@2d040000 {
        compatible = "fsl,imx6sx-mu";
        reg = <0x2d040000 0x20000>;
        interrupts = <0 474 4>;
        #mbox-cells = <2>;
        power-domains = <&pd IMX_SC_R_VPU_MU_2>;
      };

      vpu_core0: vpu_core@2d080000 {
        compatible = "nxp,imx8q-vpu-decoder";
        reg = <0x2d080000 0x10000>;
        power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
        mbox-names = "tx0", "tx1", "rx";
        mboxes = <&mu_m0 0 0>,
                 <&mu_m0 0 1>,
                 <&mu_m0 1 0>;
        memory-region = <&decoder_boot>, <&decoder_rpc>;
      };

      vpu_core1: vpu_core@2d090000 {
        compatible = "nxp,imx8q-vpu-encoder";
        reg = <0x2d090000 0x10000>;
        power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
        mbox-names = "tx0", "tx1", "rx";
        mboxes = <&mu1_m0 0 0>,
                 <&mu1_m0 0 1>,
                 <&mu1_m0 1 0>;
        memory-region = <&encoder1_boot>, <&encoder1_rpc>;
      };

      vpu_core2: vpu_core@2d0a0000 {
        reg = <0x2d0a0000 0x10000>;
        compatible = "nxp,imx8q-vpu-encoder";
        power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
        mbox-names = "tx0", "tx1", "rx";
        mboxes = <&mu2_m0 0 0>,
                 <&mu2_m0 0 1>,
                 <&mu2_m0 1 0>;
        memory-region = <&encoder2_boot>, <&encoder2_rpc>;
      };
    };

...


code:
* Device tree bindings for Aspeed Video Engine

The Video Engine (VE) embedded in the Aspeed AST2400/2500/2600 SOCs can
capture and compress video data from digital or analog sources.

Required properties:
 - compatible:		"aspeed,ast2400-video-engine" or
			"aspeed,ast2500-video-engine" or
			"aspeed,ast2600-video-engine"
 - reg:			contains the offset and length of the VE memory region
 - clocks:		clock specifiers for the syscon clocks associated with
			the VE (ordering must match the clock-names property)
 - clock-names:		"vclk" and "eclk"
 - resets:		reset specifier for the syscon reset associated with
			the VE
 - interrupts:		the interrupt associated with the VE on this platform

Optional properties:
 - memory-region:
	phandle to a memory region to allocate from, as defined in
	Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt

Example:

video-engine@1e700000 {
    compatible = "aspeed,ast2500-video-engine";
    reg = <0x1e700000 0x20000>;
    clocks = <&syscon ASPEED_CLK_GATE_VCLK>, <&syscon ASPEED_CLK_GATE_ECLK>;
    clock-names = "vclk", "eclk";
    resets = <&syscon ASPEED_RESET_VIDEO>;
    interrupts = <7>;
    memory-region = <&video_engine_memory>;
};


code:
# SPDX-License-Identifier: GPL-2.0-only
# Copyright (C) 2016-2021 Microchip Technology, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/atmel,isc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Atmel Image Sensor Controller (ISC)

maintainers:
  - Eugen Hristev <eugen.hristev@microchip.com>

description: |
  The Image Sensor Controller (ISC) device provides the video input capabilities for the
  Atmel/Microchip AT91 SAMA family of devices.

  The ISC has a single parallel input that supports RAW Bayer, RGB or YUV video,
  with both external synchronization and BT.656 synchronization for the latter.

properties:
  compatible:
    const: atmel,sama5d2-isc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    maxItems: 3

  clock-names:
    items:
      - const: hclock
      - const: iscck
      - const: gck

  '#clock-cells':
    const: 0

  clock-output-names:
    const: isc-mck

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    additionalProperties: false
    description:
      Input port node, single endpoint describing the input pad.

    properties:
      endpoint:
        $ref: video-interfaces.yaml#

        properties:
          remote-endpoint: true

          bus-width:
            enum: [8, 9, 10, 11, 12]
            default: 12

          hsync-active:
            enum: [0, 1]
            default: 1

          vsync-active:
            enum: [0, 1]
            default: 1

          pclk-sample:
            enum: [0, 1]
            default: 1

        required:
          - remote-endpoint

        additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - clock-output-names
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    isc: isc@f0008000 {
        compatible = "atmel,sama5d2-isc";
        reg = <0xf0008000 0x4000>;
        interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
        clocks = <&isc_clk>, <&iscck>, <&isc_gclk>;
        clock-names = "hclock", "iscck", "gck";
        #clock-cells = <0>;
        clock-output-names = "isc-mck";

        port {
                isc_0: endpoint {
                       remote-endpoint = <&ov7740_0>;
                       hsync-active = <1>;
                       vsync-active = <0>;
                       pclk-sample = <1>;
                       bus-width = <8>;
                };
        };
    };


code:
Atmel Image Sensor Interface (ISI)
----------------------------------

Required properties for ISI:
- compatible: must be "atmel,at91sam9g45-isi" or "microchip,sam9x60-isi".
- reg: physical base address and length of the registers set for the device.
- interrupts: should contain IRQ line for the ISI.
- clocks: list of clock specifiers, corresponding to entries in the clock-names
	property; please refer to clock-bindings.txt.
- clock-names: required elements: "isi_clk".
- pinctrl-names, pinctrl-0: please refer to pinctrl-bindings.txt.

ISI supports a single port node with parallel bus. It shall contain one
'port' child node with child 'endpoint' node. Please refer to the bindings
defined in Documentation/devicetree/bindings/media/video-interfaces.txt.

Endpoint node properties
------------------------

- bus-width: <8> or <10> (mandatory)
- hsync-active (default: active high)
- vsync-active (default: active high)
- pclk-sample (default: sample on falling edge)
- remote-endpoint: A phandle to the bus receiver's endpoint node (mandatory).

Example:

isi: isi@f0034000 {
	compatible = "atmel,at91sam9g45-isi";
	reg = <0xf0034000 0x4000>;
	interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_isi_data_0_7>;
	clocks = <&isi_clk>;
	clock-names = "isi_clk";
	port {
		isi_0: endpoint {
			remote-endpoint = <&ov2640_0>;
			bus-width = <8>;
			vsync-active = <1>;
			hsync-active = <1>;
		};
	};
};

i2c1: i2c@f0018000 {
	ov2640: camera@30 {
		compatible = "ovti,ov2640";
		reg = <0x30>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
		resetb-gpios = <&pioE 11 GPIO_ACTIVE_LOW>;
		pwdn-gpios = <&pioE 13 GPIO_ACTIVE_HIGH>;
		clocks = <&pck0>;
		clock-names = "xvclk";
		assigned-clocks = <&pck0>;
		assigned-clock-rates = <25000000>;

		port {
			ov2640_0: endpoint {
				remote-endpoint = <&isi_0>;
				bus-width = <8>;
			};
		};
	};
};


code:
Cadence MIPI-CSI2 RX controller
===============================

The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
lanes in input, and 4 different pixel streams in output.

Required properties:
  - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
  - reg: base address and size of the memory mapped region
  - clocks: phandles to the clocks driving the controller
  - clock-names: must contain:
    * sys_clk: main clock
    * p_clk: register bank clock
    * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
                         implemented in hardware, between 0 and 3

Optional properties:
  - phys: phandle to the external D-PHY, phy-names must be provided
  - phy-names: must contain "dphy", if the implementation uses an
               external D-PHY

Required subnodes:
  - ports: A ports node with one port child node per device input and output
           port, in accordance with the video interface bindings defined in
           Documentation/devicetree/bindings/media/video-interfaces.txt. The
           port nodes are numbered as follows:

           Port Description
           -----------------------------
           0    CSI-2 input
           1    Stream 0 output
           2    Stream 1 output
           3    Stream 2 output
           4    Stream 3 output

           The stream output port nodes are optional if they are not
           connected to anything at the hardware level or implemented
           in the design.Since there is only one endpoint per port,
           the endpoints are not numbered.

Example:

csi2rx: csi-bridge@0d060000 {
	compatible = "cdns,csi2rx";
	reg = <0x0d060000 0x1000>;
	clocks = <&byteclock>, <&byteclock>
		 <&coreclock>, <&coreclock>,
		 <&coreclock>, <&coreclock>;
	clock-names = "sys_clk", "p_clk",
		      "pixel_if0_clk", "pixel_if1_clk",
		      "pixel_if2_clk", "pixel_if3_clk";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;

			csi2rx_in_sensor: endpoint {
				remote-endpoint = <&sensor_out_csi2rx>;
				clock-lanes = <0>;
				data-lanes = <1 2>;
			};
		};

		port@1 {
			reg = <1>;

			csi2rx_out_grabber0: endpoint {
				remote-endpoint = <&grabber0_in_csi2rx>;
			};
		};

		port@2 {
			reg = <2>;

			csi2rx_out_grabber1: endpoint {
				remote-endpoint = <&grabber1_in_csi2rx>;
			};
		};

		port@3 {
			reg = <3>;

			csi2rx_out_grabber2: endpoint {
				remote-endpoint = <&grabber2_in_csi2rx>;
			};
		};

		port@4 {
			reg = <4>;

			csi2rx_out_grabber3: endpoint {
				remote-endpoint = <&grabber3_in_csi2rx>;
			};
		};
	};
};


code:
Cadence MIPI-CSI2 TX controller
===============================

The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
4 CSI lanes in output, and up to 4 different pixel streams in input.

Required properties:
  - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
    for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
  - reg: base address and size of the memory mapped region
  - clocks: phandles to the clocks driving the controller
  - clock-names: must contain:
    * esc_clk: escape mode clock
    * p_clk: register bank clock
    * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
                         implemented in hardware, between 0 and 3

Optional properties
  - phys: phandle to the D-PHY. If it is set, phy-names need to be set
  - phy-names: must contain "dphy"

Required subnodes:
  - ports: A ports node with one port child node per device input and output
           port, in accordance with the video interface bindings defined in
           Documentation/devicetree/bindings/media/video-interfaces.txt. The
           port nodes are numbered as follows.

           Port Description
           -----------------------------
           0    CSI-2 output
           1    Stream 0 input
           2    Stream 1 input
           3    Stream 2 input
           4    Stream 3 input

           The stream input port nodes are optional if they are not
           connected to anything at the hardware level or implemented
           in the design. Since there is only one endpoint per port,
           the endpoints are not numbered.

Example:

csi2tx: csi-bridge@0d0e1000 {
	compatible = "cdns,csi2tx";
	reg = <0x0d0e1000 0x1000>;
	clocks = <&byteclock>, <&byteclock>,
		 <&coreclock>, <&coreclock>,
		 <&coreclock>, <&coreclock>;
	clock-names = "p_clk", "esc_clk",
		      "pixel_if0_clk", "pixel_if1_clk",
		      "pixel_if2_clk", "pixel_if3_clk";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;

			csi2tx_out: endpoint {
				remote-endpoint = <&remote_in>;
				clock-lanes = <0>;
				data-lanes = <1 2>;
			};
		};

		port@1 {
			reg = <1>;

			csi2tx_in_stream0: endpoint {
				remote-endpoint = <&stream0_out>;
			};
		};

		port@2 {
			reg = <2>;

			csi2tx_in_stream1: endpoint {
				remote-endpoint = <&stream1_out>;
			};
		};

		port@3 {
			reg = <3>;

			csi2tx_in_stream2: endpoint {
				remote-endpoint = <&stream2_out>;
			};
		};

		port@4 {
			reg = <4>;

			csi2tx_in_stream3: endpoint {
				remote-endpoint = <&stream3_out>;
			};
		};
	};
};


code:
* HDMI CEC GPIO driver

The HDMI CEC GPIO module supports CEC implementations where the CEC line
is hooked up to a pull-up GPIO line and - optionally - the HPD line is
hooked up to another GPIO line.

Please note: the maximum voltage for the CEC line is 3.63V, for the HPD and
5V lines it is 5.3V. So you may need some sort of level conversion circuitry
when connecting them to a GPIO line.

Required properties:
  - compatible: value must be "cec-gpio".
  - cec-gpios: gpio that the CEC line is connected to. The line should be
    tagged as open drain.

If the CEC line is associated with an HDMI receiver/transmitter, then the
following property is also required:

  - hdmi-phandle - phandle to the HDMI controller, see also cec.txt.

If the CEC line is not associated with an HDMI receiver/transmitter, then
the following property is optional and can be used for debugging HPD changes:

  - hpd-gpios: gpio that the HPD line is connected to.

This property is optional and can be used for debugging changes on the 5V line:

  - v5-gpios: gpio that the 5V line is connected to.

Example for the Raspberry Pi 3 where the CEC line is connected to
pin 26 aka BCM7 aka CE1 on the GPIO pin header, the HPD line is
connected to pin 11 aka BCM17 and the 5V line is connected to pin
15 aka BCM22 (some level shifter is needed for the HPD and 5V lines!):

#include <dt-bindings/gpio/gpio.h>

cec-gpio {
	compatible = "cec-gpio";
	cec-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
	hpd-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
	v5-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
};


code:
Common bindings for HDMI CEC adapters

- hdmi-phandle: phandle to the HDMI controller.

- needs-hpd: if present the CEC support is only available when the HPD
  is high. Some boards only let the CEC pin through if the HPD is high,
  for example if there is a level converter that uses the HPD to power
  up or down.


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/coda.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Chips&Media Coda multi-standard codec IP

maintainers:
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |-
  Coda codec IPs are present in i.MX SoCs in various versions,
  called VPU (Video Processing Unit).

properties:
  compatible:
    oneOf:
      - items:
          - const: fsl,imx27-vpu
          - const: cnm,codadx6
      - items:
          - const: fsl,imx51-vpu
          - const: cnm,codahx4
      - items:
          - const: fsl,imx53-vpu
          - const: cnm,coda7541
      - items:
          - enum:
              - fsl,imx6dl-vpu
              - fsl,imx6q-vpu
          - const: cnm,coda960

  reg:
    maxItems: 1

  clocks:
    items:
      - description: PER clock
      - description: AHB interface clock

  clock-names:
    items:
      - const: per
      - const: ahb

  interrupts:
    minItems: 1
    items:
      - description: BIT processor interrupt
      - description: JPEG unit interrupt

  interrupt-names:
    minItems: 1
    items:
      - const: bit
      - const: jpeg

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  iram:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle pointing to the SRAM device node

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: cnm,coda960
    then:
      properties:
        interrupts:
          minItems: 2

        interrupt-names:
          minItems: 2
    else:
      properties:
        interrupts:
          maxItems: 1

        power-domains: false

examples:
  - |
    vpu: video-codec@63ff4000 {
        compatible = "fsl,imx53-vpu", "cnm,coda7541";
        reg = <0x63ff4000 0x1000>;
        interrupts = <9>;
        clocks = <&clks 63>, <&clks 63>;
        clock-names = "per", "ahb";
        iram = <&ocram>;
    };


code:
Exynos4x12/Exynos5 SoC series camera host interface (FIMC-LITE)

Required properties:

- compatible	: should be one of:
		  "samsung,exynos4212-fimc-lite" for Exynos4212/4412 SoCs,
		  "samsung,exynos5250-fimc-lite" for Exynos5250 compatible
		   devices;
- reg		: physical base address and size of the device memory mapped
		  registers;
- interrupts	: should contain FIMC-LITE interrupt;
- clocks	: FIMC LITE gate clock should be specified in this property.
- clock-names	: should contain "flite" entry.

Each FIMC device should have an alias in the aliases node, in the form of
fimc-lite<n>, where <n> is an integer specifying the IP block instance.


code:
Exynos4x12 SoC series Imaging Subsystem (FIMC-IS)

The FIMC-IS is a subsystem for processing image signal from an image sensor.
The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5
processor, ISP, DRC and FD IP blocks and peripheral devices such as UART, I2C
and SPI bus controllers, PWM and ADC.

fimc-is node
------------

Required properties:
- compatible	: should be "samsung,exynos4212-fimc-is" for Exynos4212 and
		  Exynos4412 SoCs;
- reg		: physical base address and length of the registers set;
- interrupts	: must contain two FIMC-IS interrupts, in order: ISP0, ISP1;
- clocks	: list of clock specifiers, corresponding to entries in
		  clock-names property;
- clock-names	: must contain "ppmuispx", "ppmuispx", "lite0", "lite1"
		  "mpll", "sysreg", "isp", "drc", "fd", "mcuisp", "gicisp",
		  "pwm_isp", "mcuctl_isp", "uart", "ispdiv0", "ispdiv1",
		  "mcuispdiv0", "mcuispdiv1", "aclk200", "div_aclk200",
		  "aclk400mcuisp", "div_aclk400mcuisp" entries,
		  matching entries in the clocks property.
pmu subnode
-----------

Required properties:
 - reg : must contain PMU physical base address and size of the register set.

The following are the FIMC-IS peripheral device nodes and can be specified
either standalone or as the fimc-is node child nodes.

i2c-isp (ISP I2C bus controller) nodes
------------------------------------------

Required properties:

- compatible	: should be "samsung,exynos4212-i2c-isp" for Exynos4212 and
		  Exynos4412 SoCs;
- reg		: physical base address and length of the registers set;
- clocks	: must contain gate clock specifier for this controller;
- clock-names	: must contain "i2c_isp" entry.

For the above nodes it is required to specify a pinctrl state named "default",
according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt.

Device tree nodes of the image sensors' controlled directly by the FIMC-IS
firmware must be child nodes of their corresponding ISP I2C bus controller node.
The data link of these image sensors must be specified using the common video
interfaces bindings, defined in video-interfaces.txt.


code:
Freescale Pixel Pipeline
========================

The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
that supports scaling, colorspace conversion, alpha blending, rotation, and
pixel conversion via lookup table. Different versions are present on various
i.MX SoCs from i.MX23 to i.MX7.

Required properties:
- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
  imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d.
- reg: the register base and size for the device registers
- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
- clock-names: should be "axi"
- clocks: the PXP AXI clock

Example:

pxp@21cc000 {
	compatible = "fsl,imx6ull-pxp";
	reg = <0x021cc000 0x4000>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "axi";
	clocks = <&clks IMX6UL_CLK_PXP>;
};


code:
Freescale Video Data Order Adapter
==================================

The Video Data Order Adapter (VDOA) is present on the i.MX6q. Its sole purpose
is to reorder video data from the macroblock tiled order produced by the CODA
960 VPU to the conventional raster-scan order for scanout.

Required properties:
- compatible: must be "fsl,imx6q-vdoa"
- reg: the register base and size for the device registers
- interrupts: the VDOA interrupt
- clocks: the vdoa clock

Example:

vdoa@21e4000 {
        compatible = "fsl,imx6q-vdoa";
        reg = <0x021e4000 0x4000>;
        interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clks IMX6QDL_CLK_VDOA>;
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/gpio-ir-receiver.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: GPIO Based IR receiver

maintainers:
  - Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

allOf:
  - $ref: rc.yaml#

properties:
  compatible:
    const: gpio-ir-receiver

  gpios:
    maxItems: 1

  linux,autosuspend-period:
    description: autosuspend delay time in milliseconds
    $ref: /schemas/types.yaml#/definitions/uint32

required:
  - compatible
  - gpios

unevaluatedProperties: false

examples:
  - |
    ir-receiver {
        compatible = "gpio-ir-receiver";
        gpios = <&gpio0 19 1>;
        linux,rc-map-name = "rc-rc6-mce";
        linux,autosuspend-period = <125>;
    };
...


code:
Device-Tree bindings for hix5hd2 ir IP

Required properties:
	- compatible: Should contain "hisilicon,hix5hd2-ir", or:
		- "hisilicon,hi3796cv300-ir" for Hi3796CV300 IR device.
	- reg: Base physical address of the controller and length of memory
	  mapped region.
	- interrupts: interrupt-specifier for the sole interrupt generated by
	  the device. The interrupt specifier format depends on the interrupt
	  controller parent.
	- clocks: clock phandle and specifier pair.

Optional properties:
	- linux,rc-map-name: see rc.txt file in the same directory.
	- hisilicon,power-syscon: DEPRECATED. Don't use this in new dts files.
		Provide correct clocks instead.

Example node:

	ir: ir@f8001000 {
		compatible = "hisilicon,hix5hd2-ir";
		reg = <0xf8001000 0x1000>;
		interrupts = <0 47 4>;
		clocks = <&clock HIX5HD2_IR_CLOCK>;
		linux,rc-map-name = "rc-tivo";
	};


code:
* Analog Devices AD5820 autofocus coil

Required Properties:

  - compatible: Must contain one of:
		- "adi,ad5820"
		- "adi,ad5821"
		- "adi,ad5823"

  - reg: I2C slave address

  - VANA-supply: supply of voltage for VANA pin

Optional properties:

   - enable-gpios : GPIO spec for the XSHUTDOWN pin. The XSHUTDOWN signal is
active low, a high level on the pin enables the device.

Example:

       ad5820: coil@c {
               compatible = "adi,ad5820";
               reg = <0x0c>;

               VANA-supply = <&vaux4>;
               enable-gpios = <&msmgpio 26 GPIO_ACTIVE_HIGH>;
       };


code:
* Analog Devices ADP1653 flash LED driver

Required Properties:

  - compatible: Must contain "adi,adp1653"

  - reg: I2C slave address

  - enable-gpios: Specifier of the GPIO connected to EN pin

There are two LED outputs available - flash and indicator. One LED is
represented by one child node, nodes need to be named "flash" and "indicator".

Required properties of the LED child node:
- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt

Required properties of the flash LED child node:

- flash-max-microamp : see Documentation/devicetree/bindings/leds/common.txt
- flash-timeout-us : see Documentation/devicetree/bindings/leds/common.txt
- led-max-microamp : see Documentation/devicetree/bindings/leds/common.txt

Example:

	adp1653: led-controller@30 {
		compatible = "adi,adp1653";
		reg = <0x30>;
		enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */

		flash {
			flash-timeout-us = <500000>;
			flash-max-microamp = <320000>;
			led-max-microamp = <50000>;
		};
		indicator {
			led-max-microamp = <17500>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/adv7180.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices ADV7180 analog video decoder family

maintainers:
  - Lars-Peter Clausen <lars@metafoo.de>

description:
  The adv7180 family devices are used to capture analog video to different
  digital interfaces like MIPI CSI-2 or parallel video.

properties:
  compatible:
    items:
      - enum:
          - adi,adv7180
          - adi,adv7180cp
          - adi,adv7180st
          - adi,adv7182
          - adi,adv7280
          - adi,adv7280-m
          - adi,adv7281
          - adi,adv7281-m
          - adi,adv7281-ma
          - adi,adv7282
          - adi,adv7282-m

  reg:
    maxItems: 1

  powerdown-gpios:
    maxItems: 1

  reset-gpios:
    maxItems: 1

  adv,force-bt656-4:
    description:
      Indicates that the output is a BT.656-4 compatible stream.
    type: boolean

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    unevaluatedProperties: false

    properties:
      endpoint:
        $ref: /schemas/media/video-interfaces.yaml#
        unevaluatedProperties: false

  ports: true

additionalProperties: false

required:
  - compatible
  - reg

allOf:
  - if:
      properties:
        compatible:
          enum:
            - adi,adv7180
            - adi,adv7182
            - adi,adv7280
            - adi,adv7280-m
            - adi,adv7281
            - adi,adv7281-m
            - adi,adv7281-ma
            - adi,adv7282
            - adi,adv7282-m
    then:
      required:
        - port

  - if:
      properties:
        compatible:
          contains:
            const: adi,adv7180cp
    then:
      properties:
        ports:
          $ref: /schemas/graph.yaml#/properties/ports
          properties:
            port@3:
              $ref: /schemas/graph.yaml#/properties/port
              description: Output port

          patternProperties:
            "^port@[0-2]$":
              $ref: /schemas/graph.yaml#/properties/port
              description: Input port

          required:
            - port@3

      required:
        - ports

  - if:
      properties:
        compatible:
          contains:
            const: adi,adv7180st
    then:
      properties:
        ports:
          $ref: /schemas/graph.yaml#/properties/ports
          properties:
            port@6:
              $ref: /schemas/graph.yaml#/properties/port
              description: Output port

          patternProperties:
            "^port@[0-5]$":
              $ref: /schemas/graph.yaml#/properties/port
              description: Input port

          required:
            - port@6

      required:
        - ports

examples:
  - |
    i2c {
            #address-cells = <1>;
            #size-cells = <0>;

            composite-in@20 {
                    compatible = "adi,adv7180";
                    reg = <0x20>;

                    port {
                            adv7180: endpoint {
                                    bus-width = <8>;
                                    remote-endpoint = <&vin1ep>;
                            };
                    };
            };

    };

  - |
    i2c {
            #address-cells = <1>;
            #size-cells = <0>;

            composite-in@20 {
                    compatible = "adi,adv7180cp";
                    reg = <0x20>;

                    ports {
                            #address-cells = <1>;
                            #size-cells = <0>;

                            port@0 {
                                    reg = <0>;
                                    adv7180_in: endpoint {
                                            remote-endpoint = <&composite_con_in>;
                                    };
                            };

                            port@3 {
                                    reg = <3>;
                                    adv7180_out: endpoint {
                                            remote-endpoint = <&vin4_in>;
                                    };
                            };
                    };
            };
    };