code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Mali Utgard GPU

maintainers:
  - Rob Herring <robh@kernel.org>
  - Maxime Ripard <mripard@kernel.org>
  - Heiko Stuebner <heiko@sntech.de>

properties:
  $nodename:
    pattern: '^gpu@[a-f0-9]+$'
  compatible:
    oneOf:
      - items:
          - const: allwinner,sun8i-a23-mali
          - const: allwinner,sun7i-a20-mali
          - const: arm,mali-400
      - items:
          - enum:
              - allwinner,sun4i-a10-mali
              - allwinner,sun7i-a20-mali
              - allwinner,sun8i-h3-mali
              - allwinner,sun8i-r40-mali
              - allwinner,sun50i-a64-mali
              - rockchip,rk3036-mali
              - rockchip,rk3066-mali
              - rockchip,rk3188-mali
              - rockchip,rk3228-mali
              - samsung,exynos4210-mali
              - stericsson,db8500-mali
          - const: arm,mali-400
      - items:
          - enum:
              - allwinner,sun50i-h5-mali
              - amlogic,meson8-mali
              - amlogic,meson8b-mali
              - amlogic,meson-gxbb-mali
              - amlogic,meson-gxl-mali
              - hisilicon,hi6220-mali
              - mediatek,mt7623-mali
              - rockchip,rk3328-mali
          - const: arm,mali-450

      # "arm,mali-300"

  reg:
    maxItems: 1

  interrupts:
    minItems: 4
    maxItems: 20

  interrupt-names:
    allOf:
      - additionalItems: true
        minItems: 4
        maxItems: 20
        items:
          # At least enforce the first 2 interrupts
          - const: gp
          - const: gpmmu
      - items:
          # Not ideal as any order and combination are allowed
          enum:
            - gp        # Geometry Processor interrupt
            - gpmmu     # Geometry Processor MMU interrupt
            - pp        # Pixel Processor broadcast interrupt (mali-450 only)
            - pp0       # Pixel Processor X interrupt (X from 0 to 7)
            - ppmmu0    # Pixel Processor X MMU interrupt (X from 0 to 7)
            - pp1
            - ppmmu1
            - pp2
            - ppmmu2
            - pp3
            - ppmmu3
            - pp4
            - ppmmu4
            - pp5
            - ppmmu5
            - pp6
            - ppmmu6
            - pp7
            - ppmmu7
            - pmu       # Power Management Unit interrupt (optional)
            - combined  # stericsson,db8500-mali only

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: bus
      - const: core

  memory-region: true

  mali-supply: true

  opp-table:
    type: object

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  operating-points-v2: true

  "#cooling-cells":
    const: 2

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun4i-a10-mali
              - allwinner,sun7i-a20-mali
              - allwinner,sun8i-r40-mali
              - allwinner,sun50i-a64-mali
              - allwinner,sun50i-h5-mali
              - amlogic,meson8-mali
              - amlogic,meson8b-mali
              - hisilicon,hi6220-mali
              - mediatek,mt7623-mali
              - rockchip,rk3036-mali
              - rockchip,rk3066-mali
              - rockchip,rk3188-mali
              - rockchip,rk3228-mali
              - rockchip,rk3328-mali
    then:
      required:
        - resets

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mali: gpu@1c40000 {
      compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
      reg = <0x01c40000 0x10000>;
      interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "gp",
            "gpmmu",
            "pp0",
            "ppmmu0",
            "pp1",
            "ppmmu1",
            "pmu";
      clocks = <&ccu 1>, <&ccu 2>;
      clock-names = "bus", "core";
      resets = <&ccu 1>;
      #cooling-cells = <2>;
    };

...


code:
Device tree configuration for the GFX display device on the ASPEED SoCs

Required properties:
  - compatible
    * Must be one of the following:
      + aspeed,ast2500-gfx
      + aspeed,ast2400-gfx
    * In addition, the ASPEED pinctrl bindings require the 'syscon' property to
      be present

  - reg: Physical base address and length of the GFX registers

  - interrupts: interrupt number for the GFX device

  - clocks: clock number used to generate the pixel clock

  - resets: reset line that must be released to use the GFX device

  - memory-region:
    Phandle to a memory region to allocate from, as defined in
    Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt

Example:

gfx: display@1e6e6000 {
	compatible = "aspeed,ast2500-gfx", "syscon";
	reg = <0x1e6e6000 0x1000>;
	reg-io-width = <4>;
	clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
	resets = <&syscon ASPEED_RESET_CRT1>;
	interrupts = <0x19>;
	memory-region = <&gfx_memory>;
};

gfx_memory: framebuffer {
	size = <0x01000000>;
	alignment = <0x01000000>;
	compatible = "shared-dma-pool";
	reusable;
};

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/brcm,bcm-v3d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom V3D GPU Bindings

maintainers:
  - Eric Anholt <eric@anholt.net>
  - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>

properties:
  $nodename:
    pattern: '^gpu@[a-f0-9]+$'

  compatible:
    enum:
      - brcm,2711-v3d
      - brcm,7268-v3d
      - brcm,7278-v3d

  reg:
    items:
      - description: hub register (required)
      - description: core0 register (required)
      - description: GCA cache controller register (if GCA controller present)
      - description: bridge register (if no external reset controller)
    minItems: 2

  reg-names:
    items:
      - const: hub
      - const: core0
      - enum: [ bridge, gca ]
      - enum: [ bridge, gca ]
    minItems: 2

  interrupts:
    items:
      - description: hub interrupt (required)
      - description: core interrupts (if it doesn't share the hub's interrupt)
    minItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - interrupts

additionalProperties: false

examples:
  - |
    gpu@f1200000 {
      compatible = "brcm,7268-v3d";
      reg = <0xf1200000 0x4000>,
            <0xf1208000 0x4000>,
            <0xf1204000 0x100>,
            <0xf1204100 0x100>;
      reg-names = "hub", "core0", "bridge", "gca";
      interrupts = <0 78 4>,
                   <0 77 4>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Device tree binding for NVIDIA Tegra NVDEC

description: |
  NVDEC is the hardware video decoder present on NVIDIA Tegra210
  and newer chips. It is located on the Host1x bus and typically
  programmed through Host1x channels.

maintainers:
  - Thierry Reding <treding@gmail.com>
  - Mikko Perttunen <mperttunen@nvidia.com>

properties:
  $nodename:
    pattern: "^nvdec@[0-9a-f]*$"

  compatible:
    enum:
      - nvidia,tegra210-nvdec
      - nvidia,tegra186-nvdec
      - nvidia,tegra194-nvdec

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: nvdec

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: nvdec

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

  dma-coherent: true

  interconnects:
    items:
      - description: DMA read memory client
      - description: DMA read 2 memory client
      - description: DMA write memory client

  interconnect-names:
    items:
      - const: dma-mem
      - const: read-1
      - const: write

  nvidia,host1x-class:
    description: |
      Host1x class of the engine, used to specify the targeted engine
      when programming the engine through Host1x channels or when
      configuring engine-specific behavior in Host1x.
    default: 0xf0
    $ref: /schemas/types.yaml#/definitions/uint32

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra186-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/tegra186-mc.h>
    #include <dt-bindings/power/tegra186-powergate.h>
    #include <dt-bindings/reset/tegra186-reset.h>

    nvdec@15480000 {
            compatible = "nvidia,tegra186-nvdec";
            reg = <0x15480000 0x40000>;
            clocks = <&bpmp TEGRA186_CLK_NVDEC>;
            clock-names = "nvdec";
            resets = <&bpmp TEGRA186_RESET_NVDEC>;
            reset-names = "nvdec";

            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
                            <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
                            <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
            interconnect-names = "dma-mem", "read-1", "write";
            iommus = <&smmu TEGRA186_SID_NVDEC>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Device tree binding for NVIDIA Tegra NVENC

description: |
  NVENC is the hardware video encoder present on NVIDIA Tegra210
  and newer chips. It is located on the Host1x bus and typically
  programmed through Host1x channels.

maintainers:
  - Thierry Reding <treding@gmail.com>
  - Mikko Perttunen <mperttunen@nvidia.com>

properties:
  $nodename:
    pattern: "^nvenc@[0-9a-f]*$"

  compatible:
    enum:
      - nvidia,tegra210-nvenc
      - nvidia,tegra186-nvenc
      - nvidia,tegra194-nvenc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: nvenc

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: nvenc

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

  dma-coherent: true

  interconnects:
    minItems: 2
    maxItems: 3

  interconnect-names:
    minItems: 2
    maxItems: 3

  nvidia,host1x-class:
    description: |
      Host1x class of the engine, used to specify the targeted engine
      when programming the engine through Host1x channels or when
      configuring engine-specific behavior in Host1x.
    default: 0x21
    $ref: /schemas/types.yaml#/definitions/uint32

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - power-domains

allOf:
  - if:
      properties:
        compatible:
          enum:
            - nvidia,tegra210-nvenc
            - nvidia,tegra186-nvenc
    then:
      properties:
        interconnects:
          items:
            - description: DMA read memory client
            - description: DMA write memory client
        interconnect-names:
          items:
            - const: dma-mem
            - const: write
  - if:
      properties:
        compatible:
          enum:
            - nvidia,tegra194-nvenc
    then:
      properties:
        interconnects:
          items:
            - description: DMA read memory client
            - description: DMA read 2 memory client
            - description: DMA write memory client
        interconnect-names:
          items:
            - const: dma-mem
            - const: read-1
            - const: write

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra186-clock.h>
    #include <dt-bindings/memory/tegra186-mc.h>
    #include <dt-bindings/power/tegra186-powergate.h>
    #include <dt-bindings/reset/tegra186-reset.h>

    nvenc@154c0000 {
            compatible = "nvidia,tegra186-nvenc";
            reg = <0x154c0000 0x40000>;
            clocks = <&bpmp TEGRA186_CLK_NVENC>;
            clock-names = "nvenc";
            resets = <&bpmp TEGRA186_RESET_NVENC>;
            reset-names = "nvenc";

            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
                            <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
            interconnect-names = "dma-mem", "write";
            iommus = <&smmu TEGRA186_SID_NVENC>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Device tree binding for NVIDIA Tegra NVJPG

description: |
  NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210
  and newer chips. It is located on the Host1x bus and typically programmed
  through Host1x channels.

maintainers:
  - Thierry Reding <treding@gmail.com>
  - Mikko Perttunen <mperttunen@nvidia.com>

properties:
  $nodename:
    pattern: "^nvjpg@[0-9a-f]*$"

  compatible:
    enum:
      - nvidia,tegra210-nvjpg
      - nvidia,tegra186-nvjpg
      - nvidia,tegra194-nvjpg

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: nvjpg

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: nvjpg

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

  dma-coherent: true

  interconnects:
    items:
      - description: DMA read memory client
      - description: DMA write memory client

  interconnect-names:
    items:
      - const: dma-mem
      - const: write

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra186-clock.h>
    #include <dt-bindings/memory/tegra186-mc.h>
    #include <dt-bindings/power/tegra186-powergate.h>
    #include <dt-bindings/reset/tegra186-reset.h>

    nvjpg@15380000 {
            compatible = "nvidia,tegra186-nvjpg";
            reg = <0x15380000 0x40000>;
            clocks = <&bpmp TEGRA186_CLK_NVJPG>;
            clock-names = "nvjpg";
            resets = <&bpmp TEGRA186_RESET_NVJPG>;
            reset-names = "nvjpg";

            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
                            <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
            interconnect-names = "dma-mem", "write";
            iommus = <&smmu TEGRA186_SID_NVJPG>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Device tree binding for NVIDIA Tegra234 NVDEC

description: |
  NVDEC is the hardware video decoder present on NVIDIA Tegra210
  and newer chips. It is located on the Host1x bus and typically
  programmed through Host1x channels.

maintainers:
  - Thierry Reding <treding@gmail.com>
  - Mikko Perttunen <mperttunen@nvidia.com>

properties:
  $nodename:
    pattern: "^nvdec@[0-9a-f]*$"

  compatible:
    enum:
      - nvidia,tegra234-nvdec

  reg:
    maxItems: 1

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: nvdec
      - const: fuse
      - const: tsec_pka

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: nvdec

  power-domains:
    maxItems: 1

  iommus:
    maxItems: 1

  dma-coherent: true

  interconnects:
    items:
      - description: DMA read memory client
      - description: DMA write memory client

  interconnect-names:
    items:
      - const: dma-mem
      - const: write

  nvidia,memory-controller:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle to the memory controller for determining information for the NVDEC
      firmware secure carveout. This carveout is configured by the bootloader and
      not accessible to CPU.

  nvidia,bl-manifest-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Offset to bootloader manifest from beginning of firmware that was configured by
      the bootloader.

  nvidia,bl-code-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Offset to bootloader code section from beginning of firmware that was configured by
      the bootloader.

  nvidia,bl-data-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Offset to bootloader data section from beginning of firmware that was configured by
      the bootloader.

  nvidia,os-manifest-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Offset to operating system manifest from beginning of firmware that was configured by
      the bootloader.

  nvidia,os-code-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Offset to operating system code section from beginning of firmware that was configured by
      the bootloader.

  nvidia,os-data-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Offset to operating system data section from beginning of firmware that was configured
      by the bootloader.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - power-domains
  - nvidia,memory-controller
  - nvidia,bl-manifest-offset
  - nvidia,bl-code-offset
  - nvidia,bl-data-offset
  - nvidia,os-manifest-offset
  - nvidia,os-code-offset
  - nvidia,os-data-offset

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra234-clock.h>
    #include <dt-bindings/memory/tegra234-mc.h>
    #include <dt-bindings/power/tegra234-powergate.h>
    #include <dt-bindings/reset/tegra234-reset.h>

    nvdec@15480000 {
            compatible = "nvidia,tegra234-nvdec";
            reg = <0x15480000 0x00040000>;
            clocks = <&bpmp TEGRA234_CLK_NVDEC>,
                     <&bpmp TEGRA234_CLK_FUSE>,
                     <&bpmp TEGRA234_CLK_TSEC_PKA>;
            clock-names = "nvdec", "fuse", "tsec_pka";
            resets = <&bpmp TEGRA234_RESET_NVDEC>;
            reset-names = "nvdec";
            power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
            interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
                            <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
            interconnect-names = "dma-mem", "write";
            iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
            dma-coherent;

            nvidia,memory-controller = <&mc>;

            /* Placeholder values, to be replaced with values from overlay */
            nvidia,bl-manifest-offset = <0>;
            nvidia,bl-data-offset = <0>;
            nvidia,bl-code-offset = <0>;
            nvidia,os-manifest-offset = <0>;
            nvidia,os-data-offset = <0>;
            nvidia,os-code-offset = <0>;
    };


code:
NVIDIA Tegra Graphics Processing Units

Required properties:
- compatible: "nvidia,<gpu>"
  Currently recognized values:
  - nvidia,gk20a
  - nvidia,gm20b
  - nvidia,gp10b
  - nvidia,gv11b
- reg: Physical base address and length of the controller's registers.
  Must contain two entries:
  - first entry for bar0
  - second entry for bar1
- interrupts: Must contain an entry for each entry in interrupt-names.
  See ../interrupt-controller/interrupts.txt for details.
- interrupt-names: Must include the following entries:
  - stall
  - nonstall
- vdd-supply: regulator for supply voltage. Only required for GPUs not using
  power domains.
- clocks: Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
  - gpu
  - pwr
If the compatible string is "nvidia,gm20b", then the following clock
is also required:
  - ref
If the compatible string is "nvidia,gv11b", then the following clock is also
required:
  - fuse
- resets: Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
  - gpu
- power-domains: GPUs that make use of power domains can define this property
  instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.

Optional properties:
- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.

Example for GK20A:

	gpu@57000000 {
		compatible = "nvidia,gk20a";
		reg = <0x0 0x57000000 0x0 0x01000000>,
		      <0x0 0x58000000 0x0 0x01000000>;
		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "stall", "nonstall";
		vdd-supply = <&vdd_gpu>;
		clocks = <&tegra_car TEGRA124_CLK_GPU>,
			 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
		clock-names = "gpu", "pwr";
		resets = <&tegra_car 184>;
		reset-names = "gpu";
		iommus = <&mc TEGRA_SWGROUP_GPU>;
	};

Example for GM20B:

	gpu@57000000 {
		compatible = "nvidia,gm20b";
		reg = <0x0 0x57000000 0x0 0x01000000>,
		      <0x0 0x58000000 0x0 0x01000000>;
		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "stall", "nonstall";
		clocks = <&tegra_car TEGRA210_CLK_GPU>,
			 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
			 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
		clock-names = "gpu", "pwr", "ref";
		resets = <&tegra_car 184>;
		reset-names = "gpu";
		iommus = <&mc TEGRA_SWGROUP_GPU>;
	};

Example for GP10B:

	gpu@17000000 {
		compatible = "nvidia,gp10b";
		reg = <0x0 0x17000000 0x0 0x1000000>,
		      <0x0 0x18000000 0x0 0x1000000>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "stall", "nonstall";
		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
			 <&bpmp TEGRA186_CLK_GPU>;
		clock-names = "gpu", "pwr";
		resets = <&bpmp TEGRA186_RESET_GPU>;
		reset-names = "gpu";
		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
		iommus = <&smmu TEGRA186_SID_GPU>;
	};

Example for GV11B:

	gpu@17000000 {
		compatible = "nvidia,gv11b";
		reg = <0x17000000 0x1000000>,
		      <0x18000000 0x1000000>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "stall", "nonstall";
		clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
			 <&bpmp TEGRA194_CLK_GPU_PWR>,
			 <&bpmp TEGRA194_CLK_FUSE>;
		clock-names = "gpu", "pwr", "fuse";
		resets = <&bpmp TEGRA194_RESET_GPU>;
		reset-names = "gpu";
		dma-coherent;

		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
		iommus = <&smmu TEGRA194_SID_GPU>;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/samsung-g2d.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung SoC 2D Graphics Accelerator

maintainers:
  - Inki Dae <inki.dae@samsung.com>

properties:
  compatible:
    enum:
      - samsung,s5pv210-g2d    # in S5PV210 & Exynos4210 SoC
      - samsung,exynos4212-g2d # in Exynos4x12 SoCs
      - samsung,exynos5250-g2d

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks: {}
  clock-names: {}
  iommus: {}
  power-domains: {}

if:
  properties:
    compatible:
      contains:
        const: samsung,exynos5250-g2d

then:
  properties:
    clocks:
      items:
        - description: fimg2d clock
    clock-names:
      items:
        - const: fimg2d

else:
  properties:
    clocks:
      items:
        - description: sclk_fimg2d clock
        - description: fimg2d clock
    clock-names:
      items:
        - const: sclk_fimg2d
        - const: fimg2d

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    g2d@12800000 {
        compatible = "samsung,s5pv210-g2d";
        reg = <0x12800000 0x1000>;
        interrupts = <0 89 0>;
        clocks = <&clock 177>, <&clock 277>;
        clock-names = "sclk_fimg2d", "fimg2d";
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/samsung-rotator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung SoC Image Rotator

maintainers:
  - Inki Dae <inki.dae@samsung.com>

properties:
  compatible:
    enum:
      - "samsung,s5pv210-rotator"
      - "samsung,exynos4210-rotator"
      - "samsung,exynos4212-rotator"
      - "samsung,exynos5250-rotator"
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: rotator

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    rotator@12810000 {
        compatible = "samsung,exynos4210-rotator";
        reg = <0x12810000 0x1000>;
        interrupts = <0 83 0>;
        clocks = <&clock 278>;
        clock-names = "rotator";
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/samsung-scaler.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC Image Scaler

maintainers:
  - Inki Dae <inki.dae@samsung.com>

properties:
  compatible:
    enum:
      - samsung,exynos5420-scaler
      - samsung,exynos5433-scaler

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks: {}
  clock-names: {}
  iommus: {}
  power-domains: {}

if:
  properties:
    compatible:
      contains:
        const: samsung,exynos5420-scaler

then:
  properties:
    clocks:
      items:
        - description: mscl clock

    clock-names:
      items:
        - const: mscl

else:
  properties:
    clocks:
      items:
        - description: pclk clock
        - description: aclk clock
        - description: aclk_xiu clock

    clock-names:
      items:
        - const: pclk
        - const: aclk
        - const: aclk_xiu

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5420.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    scaler@12800000 {
        compatible = "samsung,exynos5420-scaler";
        reg = <0x12800000 0x1294>;
        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clock CLK_MSCL0>;
        clock-names = "mscl";
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Vivante GPU Bindings

description: Vivante GPU core devices

maintainers:
  - Lucas Stach <l.stach@pengutronix.de>

properties:
  compatible:
    const: vivante,gc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  '#cooling-cells':
    const: 2

  assigned-clock-parents: true
  assigned-clock-rates: true
  assigned-clocks: true

  clocks:
    items:
      - description: AXI/master interface clock
      - description: GPU core clock
      - description: Shader clock (only required if GPU has feature PIPE_3D)
      - description: AHB/slave interface clock (only required if GPU can gate
          slave interface independently)
    minItems: 1

  clock-names:
    items:
      enum: [ bus, core, shader, reg ]
    minItems: 1
    maxItems: 4

  resets:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx6qdl-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    gpu@130000 {
      compatible = "vivante,gc";
      reg = <0x00130000 0x4000>;
      interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
               <&clks IMX6QDL_CLK_GPU3D_CORE>,
               <&clks IMX6QDL_CLK_GPU3D_SHADER>;
      clock-names = "bus", "core", "shader";
      power-domains = <&gpc 1>;
    };

...


code: This file has moved to graph.yaml in dt-schema repo


code:
Each HSI port is supposed to have one child node, which
symbols the remote device connected to the HSI port. The
following properties are standardized for HSI clients:

Required HSI configuration properties:

- hsi-channel-ids:	A list of channel ids

- hsi-rx-mode:		Receiver Bit transmission mode ("stream" or "frame")
- hsi-tx-mode:		Transmitter Bit transmission mode ("stream" or "frame")
- hsi-mode:		May be used instead hsi-rx-mode and hsi-tx-mode if
			the transmission mode is the same for receiver and
			transmitter
- hsi-speed-kbps:	Max bit transmission speed in kbit/s
- hsi-flow:		RX flow type ("synchronized" or "pipeline")
- hsi-arb-mode:		Arbitration mode for TX frame ("round-robin", "priority")

Optional HSI configuration properties:

- hsi-channel-names:	A list with one name per channel specified in the
			hsi-channel-ids property

Device Tree node example for an HSI client:

hsi-controller {
	hsi-port {
		modem: hsi-client {
			compatible = "nokia,n900-modem";

			hsi-channel-ids = <0>, <1>, <2>, <3>;
			hsi-channel-names = "mcsaab-control",
					    "speech-control",
					    "speech-data",
					    "mcsaab-data";
			hsi-speed-kbps = <55000>;
			hsi-mode = "frame";
			hsi-flow = "synchronized";
			hsi-arb-mode = "round-robin";

			/* more client specific properties */
		};
	};
};


code:
Nokia modem client bindings

The Nokia modem HSI client follows the common HSI client binding
and inherits all required properties. The following additional
properties are needed by the Nokia modem HSI client:

Required properties:
- compatible:		Should be one of
      "nokia,n900-modem"
      "nokia,n950-modem"
      "nokia,n9-modem"
- hsi-channel-names:	Should contain the following strings
      "mcsaab-control"
      "speech-control"
      "speech-data"
      "mcsaab-data"
- gpios:		Should provide a GPIO handler for each GPIO listed in
                        gpio-names
- gpio-names:		Should contain the following strings
      "cmt_apeslpx" (for n900, n950, n9)
      "cmt_rst_rq"  (for n900, n950, n9)
      "cmt_en"      (for n900, n950, n9)
      "cmt_rst"     (for n900)
      "cmt_bsi"     (for n900)
- interrupts:		Should be IRQ handle for modem's reset indication

Example:

&ssi_port {
	modem: hsi-client {
		compatible = "nokia,n900-modem";

		pinctrl-names = "default";
		pinctrl-0 = <&modem_pins>;

		hsi-channel-ids = <0>, <1>, <2>, <3>;
		hsi-channel-names = "mcsaab-control",
				    "speech-control",
				    "speech-data",
				    "mcsaab-data";
		hsi-speed-kbps = <55000>;
		hsi-mode = "frame";
		hsi-flow = "synchronized";
		hsi-arb-mode = "round-robin";

		interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */

		gpios = <&gpio3  6 GPIO_ACTIVE_HIGH>, /* 70 */
			<&gpio3  9 GPIO_ACTIVE_HIGH>, /* 73 */
			<&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
			<&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
			<&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
		gpio-names = "cmt_apeslpx",
			     "cmt_rst_rq",
			     "cmt_en",
			     "cmt_rst",
			     "cmt_bsi";
	};
};


code:
OMAP SSI controller bindings

OMAP3's Synchronous Serial Interface (SSI) controller implements a
legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI),
while the controller found inside OMAP4 is supposed to be fully compliant
with the HSI standard.

Required properties:
- compatible:		Should include "ti,omap3-ssi" or "ti,omap4-hsi"
- reg-names:		Contains the values "sys" and "gdd" (in this order).
- reg:			Contains a matching register specifier for each entry
			in reg-names.
- interrupt-names:	Contains the value "gdd_mpu".
- interrupts: 		Contains matching interrupt information for each entry
			in interrupt-names.
- ranges:		Represents the bus address mapping between the main
			controller node and the child nodes below.
- clock-names:		Must include the following entries:
  "ssi_ssr_fck": The OMAP clock of that name
  "ssi_sst_fck": The OMAP clock of that name
  "ssi_ick": The OMAP clock of that name
- clocks:		Contains a matching clock specifier for each entry in
			clock-names.
- #address-cells:	Should be set to <1>
- #size-cells:		Should be set to <1>

Each port is represented as a sub-node of the ti,omap3-ssi device.

Required Port sub-node properties:
- compatible:		Should be set to the following value
			ti,omap3-ssi-port (applicable to OMAP34xx devices)
			ti,omap4-hsi-port (applicable to OMAP44xx devices)
- reg-names:		Contains the values "tx" and "rx" (in this order).
- reg:			Contains a matching register specifier for each entry
			in reg-names.
- interrupts:		Should contain interrupt specifiers for mpu interrupts
			0 and 1 (in this order).
- ti,ssi-cawake-gpio:	Defines which GPIO pin is used to signify CAWAKE
			events for the port. This is an optional board-specific
			property. If it's missing the port will not be
			enabled.

Optional properties:
- ti,hwmods:		Shall contain TI interconnect module name if needed
			by the SoC

Example for Nokia N900:

ssi-controller@48058000 {
	compatible = "ti,omap3-ssi";

	/* needed until hwmod is updated to use the compatible string */
	ti,hwmods = "ssi";

	reg = <0x48058000 0x1000>,
	      <0x48059000 0x1000>;
	reg-names = "sys",
		    "gdd";

	interrupts = <55>;
	interrupt-names = "gdd_mpu";

	clocks = <&ssi_ssr_fck>,
		 <&ssi_sst_fck>,
		 <&ssi_ick>;
	clock-names = "ssi_ssr_fck",
		      "ssi_sst_fck",
		      "ssi_ick";

	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	ssi-port@4805a000 {
		compatible = "ti,omap3-ssi-port";

		reg = <0x4805a000 0x800>,
		      <0x4805a800 0x800>;
		reg-names = "tx",
			    "rx";

		interrupt-parent = <&intc>;
		interrupts = <67>,
			     <68>;

		ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
	}

	ssi-port@4805a000 {
		compatible = "ti,omap3-ssi-port";

		reg = <0x4805b000 0x800>,
		      <0x4805b800 0x800>;
		reg-names = "tx",
			    "rx";

		interrupt-parent = <&intc>;
		interrupts = <69>,
			     <70>;

	}
}


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwinfo/loongson,ls2k-chipid.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Loongson-2 SoC ChipID

maintainers:
  - Yinbo Zhu <zhuyinbo@loongson.cn>

description: |
  Loongson-2 SoC contains many groups of global utilities register
  blocks, of which the ChipID group registers record SoC version,
  feature, vendor and id information.

properties:
  compatible:
    const: loongson,ls2k-chipid

  reg:
    maxItems: 1

  little-endian: true

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    chipid: chipid@1fe00000 {
        compatible = "loongson,ls2k-chipid";
        reg = <0x1fe00000 0x3ffc>;
        little-endian;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwinfo/renesas,prr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Product Register

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>
  - Magnus Damm <magnus.damm@gmail.com>

description: |
  Most Renesas ARM SoCs have a Product Register or Boundary Scan ID
  Register that allows to retrieve SoC product and revision information.
  If present, a device node for this register should be added.

properties:
  compatible:
    enum:
      - renesas,prr
      - renesas,bsid
  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    prr: chipid@ff000044 {
        compatible = "renesas,prr";
        reg = <0xff000044 4>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwinfo/samsung,exynos-chipid.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC series Chipid driver

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - samsung,exynos4210-chipid
      - samsung,exynos850-chipid

  reg:
    maxItems: 1

  samsung,asv-bin:
    description:
      Adaptive Supply Voltage bin selection. This can be used
      to determine the ASV bin of an SoC if respective information
      is missing in the CHIPID registers or in the OTP memory.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2, 3]

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    chipid@10000000 {
        compatible = "samsung,exynos4210-chipid";
        reg = <0x10000000 0x100>;
        samsung,asv-bin = <2>;
    };


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwinfo/samsung,s5pv210-chipid.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S5PV210 SoC ChipID

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    const: samsung,s5pv210-chipid

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    chipid@e0000000 {
        compatible = "samsung,s5pv210-chipid";
        reg = <0xe0000000 0x1000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwinfo/ti,k3-socinfo.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments K3 Multicore SoC platforms chipid module

maintainers:
  - Tero Kristo <t-kristo@ti.com>
  - Nishanth Menon <nm@ti.com>

description: |
  Texas Instruments (ARM64) K3 Multicore SoC platforms chipid module is
  represented by CTRLMMR_xxx_JTAGID register which contains information about
  SoC id and revision.

properties:
  $nodename:
    pattern: "^chipid@[0-9a-f]+$"

  compatible:
    items:
      - const: ti,am654-chipid

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    chipid@43000014 {
        compatible = "ti,am654-chipid";
        reg = <0x43000014 0x4>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwlock/allwinner,sun6i-a31-hwspinlock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SUN6I hardware spinlock driver for Allwinner sun6i compatible SoCs

maintainers:
  - Wilken Gottwalt <wilken.gottwalt@posteo.net>

description:
  The hardware unit provides semaphores between the ARM cores and the embedded
  companion core on the SoC.

properties:
  compatible:
    const: allwinner,sun6i-a31-hwspinlock

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
    #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>

    hwlock@1c18000 {
        compatible = "allwinner,sun6i-a31-hwspinlock";
        reg = <0x01c18000 0x1000>;
        clocks = <&ccu CLK_BUS_SPINLOCK>;
        resets = <&ccu RST_BUS_SPINLOCK>;
    };
...


code:
Generic hwlock bindings
=======================

Generic bindings that are common to all the hwlock platform specific driver
implementations.

Please also look through the individual platform specific hwlock binding
documentations for identifying any additional properties specific to that
platform.

hwlock providers:
=================

Required properties:
- #hwlock-cells:        Specifies the number of cells needed to represent a
                        specific lock.

hwlock users:
=============

Consumers that require specific hwlock(s) should specify them using the
property "hwlocks", and an optional "hwlock-names" property.

Required properties:
- hwlocks:              List of phandle to a hwlock provider node and an
                        associated hwlock args specifier as indicated by
                        #hwlock-cells. The list can have just a single hwlock
                        or multiple hwlocks, with each hwlock represented by
                        a phandle and a corresponding args specifier.

Optional properties:
- hwlock-names:         List of hwlock name strings defined in the same order
                        as the hwlocks, with one name per hwlock. Consumers can
                        use the hwlock-names to match and get a specific hwlock.

1. Example of a node using a single specific hwlock:

The following example has a node requesting a hwlock in the bank defined by
the node hwlock1. hwlock1 is a hwlock provider with an argument specifier
of length 1.

	node {
		...
		hwlocks = <&hwlock1 2>;
		...
	};

2. Example of a node using multiple specific hwlocks:

The following example has a node requesting two hwlocks, a hwlock within
the hwlock device node 'hwlock1' with #hwlock-cells value of 1, and another
hwlock within the hwlock device node 'hwlock2' with #hwlock-cells value of 2.

	node {
		...
		hwlocks = <&hwlock1 2>, <&hwlock2 0 3>;
		...
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwlock/qcom-hwspinlock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Hardware Mutex Block

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  The hardware block provides mutexes utilized between different processors on
  the SoC as part of the communication protocol used by these processors.

properties:
  compatible:
    oneOf:
      - enum:
          - qcom,sfpb-mutex
          - qcom,tcsr-mutex
      - items:
          - enum:
              - qcom,apq8084-tcsr-mutex
              - qcom,ipq6018-tcsr-mutex
              - qcom,msm8226-tcsr-mutex
              - qcom,msm8994-tcsr-mutex
          - const: qcom,tcsr-mutex
      - items:
          - enum:
              - qcom,msm8974-tcsr-mutex
          - const: qcom,tcsr-mutex
          - const: syscon

  reg:
    maxItems: 1

  '#hwlock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#hwlock-cells'

additionalProperties: false

examples:
  - |
    hwlock@1f40000 {
        compatible = "qcom,tcsr-mutex";
        reg = <0x01f40000 0x40000>;
        #hwlock-cells = <1>;
    };
...


code:
SPRD Hardware Spinlock Device Binding
-------------------------------------

Required properties :
- compatible : should be "sprd,hwspinlock-r3p0".
- reg : the register address of hwspinlock.
- #hwlock-cells : hwlock users only use the hwlock id to represent a specific
	hwlock, so the number of cells should be <1> here.
- clock-names : Must contain "enable".
- clocks : Must contain a phandle entry for the clock in clock-names, see the
	common clock bindings.

Please look at the generic hwlock binding for usage information for consumers,
"Documentation/devicetree/bindings/hwlock/hwlock.txt"

Example of hwlock provider:
	hwspinlock@40500000 {
		compatible  = "sprd,hwspinlock-r3p0";
		reg = <0 0x40500000 0 0x1000>;
		#hwlock-cells = <1>;
		clock-names = "enable";
		clocks = <&clk_aon_apb_gates0 22>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwlock/st,stm32-hwspinlock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 Hardware Spinlock bindings

maintainers:
  - Fabien Dessenne <fabien.dessenne@foss.st.com>

properties:
  "#hwlock-cells":
    const: 1

  compatible:
    const: st,stm32-hwspinlock

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: hsem

required:
  - "#hwlock-cells"
  - compatible
  - reg
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/stm32mp1-clks.h>
    hwspinlock@4c000000 {
        compatible = "st,stm32-hwspinlock";
        #hwlock-cells = <1>;
        reg = <0x4c000000 0x400>;
        clocks = <&rcc HSEM>;
        clock-names = "hsem";
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwlock/ti,omap-hwspinlock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI HwSpinlock for OMAP and K3 based SoCs

maintainers:
  - Suman Anna <s-anna@ti.com>

properties:
  compatible:
    enum:
      - ti,omap4-hwspinlock  # for OMAP44xx, OMAP54xx, AM33xx, AM43xx, DRA7xx SoCs
      - ti,am64-hwspinlock   # for K3 AM64x SoCs
      - ti,am654-hwspinlock  # for K3 AM65x, J721E and J7200 SoCs

  reg:
    maxItems: 1

  "#hwlock-cells":
    const: 1
    description: |
      The OMAP hwspinlock users will use a 0-indexed relative hwlock number as
      the argument specifier value for requesting a specific hwspinlock within
      a hwspinlock bank.

      Please look at the generic hwlock binding for usage information for
      consumers, "Documentation/devicetree/bindings/hwlock/hwlock.txt"

required:
  - compatible
  - reg
  - "#hwlock-cells"

additionalProperties: false

examples:

  - |
    spinlock@4a0f6000 {
        compatible = "ti,omap4-hwspinlock";
        reg = <0x4a0f6000 0x1000>;
        #hwlock-cells = <1>;
    };


code:
TI ADC128D818 ADC System Monitor With Temperature Sensor
--------------------------------------------------------

Operation modes:

 - Mode 0:  7 single-ended voltage readings (IN0-IN6),
            1 temperature reading (internal)
 - Mode 1:  8 single-ended voltage readings (IN0-IN7),
            no temperature
 - Mode 2:  4 pseudo-differential voltage readings
              (IN0-IN1, IN3-IN2, IN4-IN5, IN7-IN6),
            1 temperature reading (internal)
 - Mode 3:  4 single-ended voltage readings (IN0-IN3),
            2 pseudo-differential voltage readings
              (IN4-IN5, IN7-IN6),
            1 temperature reading (internal)

If no operation mode is configured via device tree, the driver keeps the
currently active chip operation mode (default is mode 0).

Required node properties:

 - compatible:  must be set to "ti,adc128d818"
 - reg:         I2C address of the device

Optional node properties:

 - ti,mode:     Operation mode (u8) (see above).

Example (operation mode 2):

	adc128d818@1d {
		compatible = "ti,adc128d818";
		reg = <0x1d>;
		ti,mode = /bits/ 8 <2>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---

$id: http://devicetree.org/schemas/hwmon/adi,ad741x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices AD7416/AD7417/AD7418 temperature sensors

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - adi,ad7416
      - adi,ad7417
      - adi,ad7418

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        temperature-sensor@28 {
            compatible = "adi,ad7418";
            reg = <0x28>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/adi,adm1177.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor

maintainers:
  - Michael Hennerich <michael.hennerich@analog.com>

description: |
  Analog Devices ADM1177 Hot Swap Controller and Digital Power Monitor
  https://www.analog.com/media/en/technical-documentation/data-sheets/ADM1177.pdf

properties:
  compatible:
    enum:
      - adi,adm1177

  reg:
    maxItems: 1

  avcc-supply:
    description:
      Phandle to the Avcc power supply

  shunt-resistor-micro-ohms:
    description:
      The value of curent sense resistor in microohms. If not provided,
      the current reading and overcurrent alert is disabled.

  adi,shutdown-threshold-microamp:
    description:
      Specifies the current level at which an over current alert occurs.
      If not provided, the overcurrent alert is configured to max ADC range
      based on shunt-resistor-micro-ohms.

  adi,vrange-high-enable:
    description:
      Specifies which internal voltage divider to be used. A 1 selects
      a 7:2 voltage divider while a 0 selects a 14:1 voltage divider.
    type: boolean

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        pwmon@5a {
                compatible = "adi,adm1177";
                reg = <0x5a>;
                shunt-resistor-micro-ohms = <50000>; /* 50 mOhm */
                adi,shutdown-threshold-microamp = <1059000>; /* 1.059 A */
                adi,vrange-high-enable;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/adi,adm1266.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices ADM1266 Cascadable Super Sequencer with Margin
  Control and Fault Recording

maintainers:
  - Alexandru Tachici <alexandru.tachici@analog.com>

description: |
  Analog Devices ADM1266 Cascadable Super Sequencer with Margin
  Control and Fault Recording.
  https://www.analog.com/media/en/technical-documentation/data-sheets/ADM1266.pdf

properties:
  compatible:
    enum:
      - adi,adm1266

  reg:
    description: |
      I2C address of slave device.
    items:
      minimum: 0x40
      maximum: 0x4F

  avcc-supply:
    description: |
      Phandle to the Avcc power supply.

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        adm1266@40 {
                compatible = "adi,adm1266";
                reg = <0x40>;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---

$id: http://devicetree.org/schemas/hwmon/adi,adm1275.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices ADM1075/ADM127x/ADM129x digital power monitors

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  The ADM1293 and ADM1294 are high accuracy integrated digital power monitors
  that offer digital current, voltage, and power monitoring using an on-chip,
  12-bit analog-to-digital converter (ADC), communicated through a PMBus
  compliant I2C interface.

  Datasheets:
    https://www.analog.com/en/products/adm1294.html

properties:
  compatible:
    enum:
      - adi,adm1075
      - adi,adm1272
      - adi,adm1275
      - adi,adm1276
      - adi,adm1278
      - adi,adm1293
      - adi,adm1294

  reg:
    maxItems: 1

  shunt-resistor-micro-ohms:
    description:
      Shunt resistor value in micro-Ohm.

  adi,volt-curr-sample-average:
    description: |
      Number of samples to be used to report voltage and current values.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2, 4, 8, 16, 32, 64, 128]

  adi,power-sample-average:
    description: |
      Number of samples to be used to report power values.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2, 4, 8, 16, 32, 64, 128]

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - adi,adm1075
              - adi,adm1276
    then:
      properties:
        adi,volt-curr-sample-average:
          default: 128
        adi,power-sample-average: false

  - if:
      properties:
        compatible:
          contains:
            enum:
              - adi,adm1275
    then:
      properties:
        adi,volt-curr-sample-average:
          default: 16
        adi,power-sample-average: false

  - if:
      properties:
        compatible:
          contains:
            enum:
              - adi,adm1272
    then:
      properties:
        adi,volt-curr-sample-average:
          default: 128
        adi,power-sample-average:
          default: 128

  - if:
      properties:
        compatible:
          contains:
            enum:
              - adi,adm1278
              - adi,adm1293
              - adi,adm1294
    then:
      properties:
        adi,volt-curr-sample-average:
          default: 128
        adi,power-sample-average:
          default: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        power-sensor@10 {
            compatible = "adi,adm1272";
            reg = <0x10>;
            shunt-resistor-micro-ohms = <500>;
            adi,volt-curr-sample-average = <128>;
            adi,power-sample-average = <128>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2019 Analog Devices Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/adi,axi-fan-control.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices AXI FAN Control

maintainers:
  - Nuno Sá <nuno.sa@analog.com>

description: |+
  Bindings for the Analog Devices AXI FAN Control driver. Spefications of the
  core can be found in:

  https://wiki.analog.com/resources/fpga/docs/axi_fan_control

properties:
  compatible:
    enum:
      - adi,axi-fan-control-1.00.a

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  pulses-per-revolution:
    description:
      Value specifying the number of pulses per revolution of the controlled
      FAN.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2, 4]

required:
  - compatible
  - reg
  - clocks
  - interrupts
  - pulses-per-revolution

additionalProperties: false

examples:
  - |
    fpga_axi: fpga-axi {
            #address-cells = <0x2>;
            #size-cells = <0x1>;

            axi_fan_control: axi-fan-control@80000000 {
                    compatible = "adi,axi-fan-control-1.00.a";
                    reg = <0x0 0x80000000 0x10000>;
                    clocks = <&clk 71>;
                    interrupts = <0 110 0>;
                    pulses-per-revolution = <2>;
            };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/adi,ltc2947.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices LTC2947 high precision power and energy monitor

maintainers:
  - Nuno Sá <nuno.sa@analog.com>

description: |
  Analog Devices LTC2947 high precision power and energy monitor over SPI or I2C.

  https://www.analog.com/media/en/technical-documentation/data-sheets/LTC2947.pdf

properties:
  compatible:
    enum:
      - adi,ltc2947

  reg:
    maxItems: 1

  clocks:
    description:
      The LTC2947 uses either a trimmed internal oscillator or an external clock
      as the time base for determining the integration period to represent time,
      charge and energy. When an external clock is used, this property must be
      set accordingly.
    maxItems: 1

  adi,accumulator-ctl-pol:
    description:
      This property controls the polarity of current that is accumulated to
      calculate charge and energy so that, they can be only accumulated for
      positive current for example. Since there are two sets of registers for
      the accumulated values, this entry can also have two items which sets
      energy1/charge1 and energy2/charger2 respectively. Check table 12 of the
      datasheet for more information on the supported options.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 2
    maxItems: 2
    items:
      enum: [0, 1, 2, 3]
      default: 0

  adi,accumulation-deadband-microamp:
    description:
      This property controls the Accumulation Dead band which allows to set the
      level of current below which no accumulation takes place.
    maximum: 255
    default: 0

  adi,gpio-out-pol:
    description:
      This property controls the GPIO polarity. Setting it to one makes the GPIO
      active high, setting it to zero makets it active low. When this property
      is present, the GPIO is automatically configured as output and set to
      control a fan as a function of measured temperature.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]
    default: 0

  adi,gpio-in-accum:
    description:
      When set, this property sets the GPIO as input. It is then used to control
      the accumulation of charge, energy and time. This function can be
      enabled/configured separately for each of the two sets of accumulation
      registers. Check table 13 of the datasheet for more information on the
      supported options. This property cannot be used together with
      adi,gpio-out-pol.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 2
    maxItems: 2
    items:
      enum: [0, 1, 2]
      default: 0

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    spi {
           #address-cells = <1>;
           #size-cells = <0>;

           ltc2947_spi: ltc2947@0 {
                   compatible = "adi,ltc2947";
                   reg = <0>;
                   /* accumulation takes place always for energ1/charge1. */
                   /* accumulation only on positive current for energy2/charge2. */
                   adi,accumulator-ctl-pol = <0 1>;
           };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/adi,ltc2992.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Linear Technology 2992 Power Monitor

maintainers:
  - Alexandru Tachici <alexandru.tachici@analog.com>

description: |
  Linear Technology 2992 Dual Wide Range Power Monitor
  https://www.analog.com/media/en/technical-documentation/data-sheets/ltc2992.pdf

properties:
  compatible:
    enum:
      - adi,ltc2992

  reg:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  avcc-supply: true

patternProperties:
  "^channel@([0-1])$":
    type: object
    description: |
      Represents the two supplies to be monitored.

    properties:
      reg:
        description: |
          The channel number. LTC2992 can monitor two supplies.
        items:
          minimum: 0
          maximum: 1

      shunt-resistor-micro-ohms:
        description:
          The value of curent sense resistor in microohms.

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c1 {
        #address-cells = <1>;
        #size-cells = <0>;

        ltc2992@6F {
                #address-cells = <1>;
                #size-cells = <0>;

                compatible = "adi,ltc2992";
                reg = <0x6F>;

                channel@0 {
                        reg = <0x0>;
                        shunt-resistor-micro-ohms = <10000>;
                };

                channel@1 {
                        reg = <0x1>;
                        shunt-resistor-micro-ohms = <10000>;
                };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/adi,max31760.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices MAX31760 Fan-Speed Controller

maintainers:
  - Ibrahim Tilki <Ibrahim.Tilki@analog.com>

description: |
  Analog Devices MAX31760 Fan-Speed Controller
  https://datasheets.maximintegrated.com/en/ds/MAX31760.pdf

properties:
  compatible:
    enum:
      - adi,max31760

  reg:
    description: I2C address of slave device.
    minimum: 0x50
    maximum: 0x57

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        fan-controller@50 {
            reg = <0x50>;
            compatible = "adi,max31760";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/adt7475.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ADT7475 hwmon sensor

maintainers:
  - Jean Delvare <jdelvare@suse.com>

description: |
  The ADT7473, ADT7475, ADT7476, and ADT7490 are thermal monitors and multiple
  PWN fan controllers.

  They support monitoring and controlling up to four fans (the ADT7490 can only
  control up to three). They support reading a single on chip temperature
  sensor and two off chip temperature sensors (the ADT7490 additionally
  supports measuring up to three current external temperature sensors with
  series resistance cancellation (SRC)).

  Datasheets:
  https://www.onsemi.com/pub/Collateral/ADT7473-D.PDF
  https://www.onsemi.com/pub/Collateral/ADT7475-D.PDF
  https://www.onsemi.com/pub/Collateral/ADT7476-D.PDF
  https://www.onsemi.com/pub/Collateral/ADT7490-D.PDF

  Description taken from onsemiconductors specification sheets, with minor
  rephrasing.

properties:
  compatible:
    enum:
      - adi,adt7473
      - adi,adt7475
      - adi,adt7476
      - adi,adt7490

  reg:
    maxItems: 1

  adi,pwm-active-state:
    description: |
      Integer array, represents the active state of the pwm outputs If set to 0
      the pwm uses a logic low output for 100% duty cycle. If set to 1 the pwm
      uses a logic high output for 100% duty cycle.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 3
    maxItems: 3
    items:
      enum: [0, 1]
      default: 1

patternProperties:
  "^adi,bypass-attenuator-in[0-4]$":
    description: |
      Configures bypassing the individual voltage input attenuator. If
      set to 1 the attenuator is bypassed if set to 0 the attenuator is
      not bypassed. If the property is absent then the attenuator
      retains its configuration from the bios/bootloader.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]

  "^adi,pin(5|10)-function$":
    description: |
      Configures the function for pin 5 on the adi,adt7473 and adi,adt7475. Or
      pin 10 on the adi,adt7476 and adi,adt7490.
    $ref: /schemas/types.yaml#/definitions/string
    enum:
      - pwm2
      - smbalert#

  "^adi,pin(9|14)-function$":
    description: |
      Configures the function for pin 9 on the adi,adt7473 and adi,adt7475. Or
      pin 14 on the adi,adt7476 and adi,adt7490
    $ref: /schemas/types.yaml#/definitions/string
    enum:
      - tach4
      - therm#
      - smbalert#
      - gpio

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      hwmon@2e {
        compatible = "adi,adt7476";
        reg = <0x2e>;
        adi,bypass-attenuator-in0 = <1>;
        adi,bypass-attenuator-in1 = <0>;
        adi,pwm-active-state = <1 0 1>;
        adi,pin10-function = "smbalert#";
        adi,pin14-function = "tach4";
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/amd,sbrmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: >
  Sideband Remote Management Interface (SB-RMI) compliant
  AMD SoC power device.

maintainers:
  - Akshay Gupta <Akshay.Gupta@amd.com>

description: |
  SB Remote Management Interface (SB-RMI) is an SMBus compatible
  interface that reports AMD SoC's Power (normalized Power) using,
  Mailbox Service Request and resembles a typical 8-pin remote power
  sensor's I2C interface to BMC. The power attributes in hwmon
  reports power in microwatts.

properties:
  compatible:
    enum:
      - amd,sbrmi

  reg:
    maxItems: 1
    description: |
      I2C bus address of the device as specified in Section SBI SMBus Address
      of the SoC register reference. The SB-RMI address is normally 78h for
      socket 0 and 70h for socket 1, but it could vary based on hardware
      address select pins.
      \[open source SoC register reference\]
        https://www.amd.com/en/support/tech-docs?keyword=55898

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        sbrmi@3c {
                compatible = "amd,sbrmi";
                reg = <0x3c>;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/amd,sbtsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: >
  Sideband interface Temperature Sensor Interface (SB-TSI) compliant
  AMD SoC temperature device

maintainers:
  - Kun Yi <kunyi@google.com>
  - Supreeth Venkatesh <supreeth.venkatesh@amd.com>

description: |
  SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
  interface that reports AMD SoC's Ttcl (normalized temperature),
  and resembles a typical 8-pin remote temperature sensor's I2C interface
  to BMC. The emulated thermal sensor can report temperatures in increments
  of 0.125 degrees, ranging from 0 to 255.875.

properties:
  compatible:
    enum:
      - amd,sbtsi

  reg:
    maxItems: 1
    description: |
      I2C bus address of the device as specified in Section 6.3.1 of the
      SoC register reference. The SB-TSI address is normally 98h for socket
      0 and 90h for socket 1, but it could vary based on hardware address
      select pins.
      \[open source SoC register reference\]
        https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        sbtsi@4c {
                compatible = "amd,sbtsi";
                reg = <0x4c>;
        };
    };
...


code:
APM X-Gene hwmon driver

APM X-Gene SOC sensors are accessed over the "SLIMpro" mailbox.

Required properties :
 - compatible : should be "apm,xgene-slimpro-hwmon"
 - mboxes : use the label reference for the mailbox as the first parameter.
	    The second parameter is the channel number.

Example :
	hwmonslimpro {
		compatible = "apm,xgene-slimpro-hwmon";
		mboxes = <&mailbox 7>;
	};


code:
Bindings for Synaptics AS370 PVT sensors

Required properties:
- compatible : "syna,as370-hwmon"
- reg        : address and length of the register set.

Example:
	hwmon@ea0810 {
		compatible = "syna,as370-hwmon";
		reg = <0xea0810 0xc>;
	};


code:
ASPEED AST2400/AST2500 PWM and Fan Tacho controller device driver

The ASPEED PWM controller can support upto 8 PWM outputs. The ASPEED Fan Tacho
controller can support upto 16 Fan tachometer inputs.

There can be upto 8 fans supported. Each fan can have one PWM output and
one/two Fan tach inputs.

Required properties for pwm-tacho node:
- #address-cells : should be 1.

- #size-cells : should be 1.

- #cooling-cells: should be 2.

- reg : address and length of the register set for the device.

- pinctrl-names : a pinctrl state named "default" must be defined.

- pinctrl-0 : phandle referencing pin configuration of the PWM ports.

- compatible : should be "aspeed,ast2400-pwm-tacho" for AST2400 and
	       "aspeed,ast2500-pwm-tacho" for AST2500.

- clocks : phandle to clock provider with the clock number in the second cell

- resets : phandle to reset controller with the reset number in the second cell

fan subnode format:
===================
Under fan subnode there can upto 8 child nodes, with each child node
representing a fan. If there are 8 fans each fan can have one PWM port and
one/two Fan tach inputs.
For PWM port can be configured cooling-levels to create cooling device.
Cooling device could be bound to a thermal zone for the thermal control.

Required properties for each child node:
- reg : should specify PWM source port.
	integer value in the range 0 to 7 with 0 indicating PWM port A and
	7 indicating PWM port H.

- cooling-levels: PWM duty cycle values in a range from 0 to 255
                  which correspond to thermal cooling states.

- aspeed,fan-tach-ch : should specify the Fan tach input channel.
                integer value in the range 0 through 15, with 0 indicating
		Fan tach channel 0 and 15 indicating Fan tach channel 15.
		Atleast one Fan tach input channel is required.

Examples:

pwm_tacho: pwmtachocontroller@1e786000 {
	#address-cells = <1>;
	#size-cells = <1>;
	#cooling-cells = <2>;
	reg = <0x1E786000 0x1000>;
	compatible = "aspeed,ast2500-pwm-tacho";
	clocks = <&syscon ASPEED_CLK_APB>;
	resets = <&syscon ASPEED_RESET_PWM>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;

	fan@0 {
		reg = <0x00>;
		cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
		aspeed,fan-tach-ch = /bits/ 8 <0x00>;
	};

	fan@1 {
		reg = <0x01>;
		aspeed,fan-tach-ch = /bits/ 8 <0x01 0x02>;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/baikal,bt1-pvt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Baikal-T1 PVT Sensor

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description: |
  Baikal-T1 SoC provides an embedded process, voltage and temperature
  sensor to monitor an internal SoC environment (chip temperature, supply
  voltage and process monitor) and on time detect critical situations,
  which may cause the system instability and even damages. The IP-block
  is based on the Analog Bits PVT sensor, but is equipped with a dedicated
  control wrapper, which provides a MMIO registers-based access to the
  sensor core functionality (APB3-bus based) and exposes an additional
  functions like thresholds/data ready interrupts, its status and masks,
  measurements timeout. Its internal structure is depicted on the next
  diagram:

     Analog Bits core                     Bakal-T1 PVT control block
  +--------------------+                  +------------------------+
  | Temperature sensor |-+         +------| Sensors control        |
  |--------------------| |<---En---|      |------------------------|
  | Voltage sensor     |-|<--Mode--| +--->| Sampled data           |
  |--------------------| |<--Trim--+ |    |------------------------|
  | Low-Vt sensor      |-|           | +--| Thresholds comparator  |
  |--------------------| |---Data----| |  |------------------------|
  | High-Vt sensor     |-|           | +->| Interrupts status      |
  |--------------------| |--Valid--+-+ |  |------------------------|
  | Standard-Vt sensor |-+         +---+--| Interrupts mask        |
  +--------------------+                  |------------------------|
           ^                              | Interrupts timeout     |
           |                              +------------------------+
           |                                        ^  ^
  Rclk-----+----------------------------------------+  |
  APB3-------------------------------------------------+

  This bindings describes the external Baikal-T1 PVT control interfaces
  like MMIO registers space, interrupt request number and clocks source.
  These are then used by the corresponding hwmon device driver to
  implement the sysfs files-based access to the sensors functionality.

properties:
  compatible:
    const: baikal,bt1-pvt

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: PVT reference clock
      - description: APB3 interface clock

  clock-names:
    items:
      - const: ref
      - const: pclk

  "#thermal-sensor-cells":
    description: Baikal-T1 can be referenced as the CPU thermal-sensor
    const: 0

  baikal,pvt-temp-offset-millicelsius:
    description: |
      Temperature sensor trimming factor. It can be used to manually adjust the
      temperature measurements within 7.130 degrees Celsius.
    default: 0
    minimum: 0
    maximum: 7130

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

examples:
  - |
    #include <dt-bindings/interrupt-controller/mips-gic.h>

    pvt@1f200000 {
      compatible = "baikal,bt1-pvt";
      reg = <0x1f200000 0x1000>;
      #thermal-sensor-cells = <0>;

      interrupts = <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>;

      baikal,pvt-temp-offset-millicelsius = <1000>;

      clocks = <&ccu_sys>, <&ccu_sys>;
      clock-names = "ref", "pclk";
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/cirrus,lochnagar.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cirrus Logic Lochnagar Audio Development Board

maintainers:
  - patches@opensource.cirrus.com

description: |
  Lochnagar is an evaluation and development board for Cirrus Logic
  Smart CODEC and Amp devices. It allows the connection of most Cirrus
  Logic devices on mini-cards, as well as allowing connection of various
  application processor systems to provide a full evaluation platform.
  Audio system topology, clocking and power can all be controlled through
  the Lochnagar, allowing the device under test to be used in a variety of
  possible use cases.

  This binding document describes the binding for the hardware monitor
  portion of the driver.

  This binding must be part of the Lochnagar MFD binding:
    [1] ../mfd/cirrus,lochnagar.yaml

properties:
  compatible:
    enum:
      - cirrus,lochnagar2-hwmon

required:
  - compatible

additionalProperties: false


code:
GMT G762/G763 PWM Fan controller

Required node properties:

 - "compatible": must be either "gmt,g762" or "gmt,g763"
 - "reg": I2C bus address of the device
 - "clocks": a fixed clock providing input clock frequency
	     on CLK pin of the chip.

Optional properties:

 - "fan_startv": fan startup voltage. Accepted values are 0, 1, 2 and 3.
	       The higher the more.

 - "pwm_polarity": pwm polarity. Accepted values are 0 (positive duty)
	       and 1 (negative duty).

 - "fan_gear_mode": fan gear mode. Supported values are 0, 1 and 2.

If an optional property is not set in .dts file, then current value is kept
unmodified (e.g. u-boot installed value).

Additional information on operational parameters for the device is available
in Documentation/hwmon/g762.rst. A detailed datasheet for the device is available
at http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf.

Example g762 node:

   clocks {
	#address-cells = <1>;
	#size-cells = <0>;

	g762_clk: fixedclk {
		 compatible = "fixed-clock";
		 #clock-cells = <0>;
		 clock-frequency = <8192>;
	}
   }

   g762: g762@3e {
	compatible = "gmt,g762";
	reg = <0x3e>;
	clocks = <&g762_clk>
	fan_gear_mode = <0>; /* chip default */
	fan_startv = <1>;    /* chip default */
	pwm_polarity = <0>;  /* chip default */
   };


code:
Bindings for fan connected to GPIO lines

Required properties:
- compatible : "gpio-fan"

Optional properties:
- gpios: Specifies the pins that map to bits in the control value,
  ordered MSB-->LSB.
- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the
  control value that should be set to achieve them. This array
  must have the RPM values in ascending order.
- alarm-gpios: This pin going active indicates something is wrong with
  the fan, and a udev event will be fired.
- #cooling-cells: If used as a cooling device, must be <2>
  Also see:
  Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
  min and max states are derived from the speed-map of the fan.

Note: At least one the "gpios" or "alarm-gpios" properties must be set.

Examples:

	gpio_fan {
		compatible = "gpio-fan";
		gpios = <&gpio1 14 1
			 &gpio1 13 1>;
		gpio-fan,speed-map = <0    0
				      3000 1
				      6000 2>;
		alarm-gpios = <&gpio1 15 1>;
	};
	gpio_fan_cool: gpio_fan {
		compatible = "gpio-fan";
		gpios = <&gpio2 14 1
			 &gpio2 13 1>;
		gpio-fan,speed-map =	<0    0>,
					<3000 1>,
					<6000 2>;
		alarm-gpios = <&gpio2 15 1>;
		#cooling-cells = <2>; /* min followed by max */
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/ibm,occ-hwmon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: IBM On-Chip Controller (OCC) accessed from a service processor

maintainers:
  - Eddie James <eajames@linux.ibm.com>

description: |
  The POWER processor On-Chip Controller (OCC) helps manage power and
  thermals for the system. A service processor or baseboard management
  controller can query the OCC for it's power and thermal data to report
  through hwmon.

properties:
  compatible:
    enum:
      - ibm,p9-occ-hwmon
      - ibm,p10-occ-hwmon

  ibm,no-poll-on-init:
    description: This property describes whether or not the OCC should
      be polled during driver initialization.
    type: boolean

required:
  - compatible

additionalProperties: false

examples:
  - |
    hwmon {
        compatible = "ibm,p10-occ-hwmon";
        ibm,no-poll-on-init;
    };


code:
Device-tree bindings for I2C-based On-Chip Controller hwmon device
------------------------------------------------------------------

Required properties:
 - compatible = "ibm,p8-occ-hwmon";
 - reg = <I2C address>;			: I2C bus address

Examples:

    i2c-bus@100 {
        #address-cells = <1>;
        #size-cells = <0>;
        clock-frequency = <100000>;
        < more properties >

        occ-hwmon@1 {
            compatible = "ibm,p8-occ-hwmon";
            reg = <0x50>;
        };

        occ-hwmon@2 {
            compatible = "ibm,p8-occ-hwmon";
            reg = <0x51>;
        };
    };


code:
IBM POWERNV platform sensors
----------------------------

Required node properties:
- compatible: must be one of
		"ibm,opal-sensor-cooling-fan"
		"ibm,opal-sensor-amb-temp"
		"ibm,opal-sensor-power-supply"
		"ibm,opal-sensor-power"
- sensor-id: an opaque id provided by the firmware to the kernel, identifies a
	     given sensor and its attribute data

Example sensors node:

cooling-fan#8-data {
	sensor-id = <0x7052107>;
	compatible = "ibm,opal-sensor-cooling-fan";
};

amb-temp#1-thrs {
	sensor-id = <0x5096000>;
	compatible = "ibm,opal-sensor-amb-temp";
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/hwmon/iio-hwmon.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: ADC-attached Hardware Sensor

maintainers:
  - Jonathan Cameron <jic23@kernel.org>

description: >
  Bindings for hardware monitoring devices connected to ADC controllers
  supporting the Industrial I/O bindings.

properties:
  compatible:
    const: iio-hwmon

  io-channels:
    minItems: 1
    maxItems: 8 # Should be enough
    description: >
      List of phandles to ADC channels to read the monitoring values

required:
  - compatible
  - io-channels

additionalProperties: false

examples:
  - |
      iio-hwmon {
          compatible = "iio-hwmon";
          io-channels = <&adc 1>, <&adc 2>;
      };


code:
Texas Instruments INA3221 Device Tree Bindings

1) ina3221 node
  Required properties:
  - compatible: Must be "ti,ina3221"
  - reg: I2C address

  Optional properties:
  - ti,single-shot: This chip has two power modes: single-shot (chip takes one
                    measurement and then shuts itself down) and continuous (
                    chip takes continuous measurements). The continuous mode is
                    more reliable and suitable for hardware monitor type device,
                    but the single-shot mode is more power-friendly and useful
                    for battery-powered device which cares power consumptions
                    while still needs some measurements occasionally.
                    If this property is present, the single-shot mode will be
                    used, instead of the default continuous one for monitoring.

  = The node contains optional child nodes for three channels =
  = Each child node describes the information of input source =

  - #address-cells: Required only if a child node is present. Must be 1.
  - #size-cells: Required only if a child node is present. Must be 0.

2) child nodes
  Required properties:
  - reg: Must be 0, 1 or 2, corresponding to IN1, IN2 or IN3 port of INA3221

  Optional properties:
  - label: Name of the input source
  - shunt-resistor-micro-ohms: Shunt resistor value in micro-Ohm

Example:

ina3221@40 {
	compatible = "ti,ina3221";
	reg = <0x40>;
	#address-cells = <1>;
	#size-cells = <0>;

	input@0 {
		reg = <0x0>;
		status = "disabled";
	};
	input@1 {
		reg = <0x1>;
		shunt-resistor-micro-ohms = <5000>;
	};
	input@2 {
		reg = <0x2>;
		label = "VDD_5V";
		shunt-resistor-micro-ohms = <5000>;
	};
};


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/jedec,jc42.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Jedec JC-42.4 compatible temperature sensors

maintainers:
  - Jean Delvare <jdelvare@suse.com>
  - Guenter Roeck <linux@roeck-us.net>

select:
  properties:
    compatible:
      const: jedec,jc-42.4-temp

  required:
    - compatible

properties:
  compatible:
    oneOf:
      - const: jedec,jc-42.4-temp
      - items:
          - enum:
              - adi,adt7408
              - atmel,at30ts00
              - atmel,at30tse004
              - idt,tse2002
              - idt,tse2004
              - idt,ts3000
              - idt,ts3001
              - maxim,max6604
              - microchip,mcp9804
              - microchip,mcp9805
              - microchip,mcp9808
              - microchip,mcp98243
              - microchip,mcp98244
              - microchip,mcp9843
              - nxp,se97
              - nxp,se97b
              - nxp,se98
              - onnn,cat6095
              - onnn,cat34ts02
              - st,stts2002
              - st,stts2004
              - st,stts3000
              - st,stts424
              - st,stts424e
          - const: jedec,jc-42.4-temp

  reg:
    maxItems: 1

  smbus-timeout-disable:
    description: |
      When set, the smbus timeout function will be disabled. This is not
      supported on all chips.
    type: boolean

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        temp-sensor@1a {
            compatible = "jedec,jc-42.4-temp";
            reg = <0x1a>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/kontron,sl28cpld-hwmon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Hardware monitoring driver for the sl28cpld board management controller

maintainers:
  - Michael Walle <michael@walle.cc>

description: |
  This module is part of the sl28cpld multi-function device. For more
  details see ../mfd/kontron,sl28cpld.yaml.

properties:
  compatible:
    enum:
      - kontron,sl28cpld-fan

  reg:
    maxItems: 1

required:
  - compatible

additionalProperties: false


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/lltc,ltc4151.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LTC4151 High Voltage I2C Current and Voltage Monitor

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    const: lltc,ltc4151

  reg:
    maxItems: 1

  shunt-resistor-micro-ohms:
    description:
      Shunt resistor value in micro-Ohms
    default: 1000

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        sensor@6e {
            compatible = "lltc,ltc4151";
            reg = <0x6e>;
            shunt-resistor-micro-ohms = <1500>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/lm75.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LM75 hwmon sensor

maintainers:
  - Jean Delvare <jdelvare@suse.com>
  - Guenter Roeck <linux@roeck-us.net>

properties:
  compatible:
    enum:
      - adi,adt75
      - atmel,at30ts74
      - dallas,ds1775
      - dallas,ds75
      - dallas,ds7505
      - gmt,g751
      - national,lm75
      - national,lm75a
      - national,lm75b
      - maxim,max6625
      - maxim,max6626
      - maxim,max31725
      - maxim,max31726
      - maxim,mcp980x
      - nxp,pct2075
      - st,stds75
      - st,stlm75
      - microchip,tcn75
      - ti,tmp1075
      - ti,tmp100
      - ti,tmp101
      - ti,tmp105
      - ti,tmp112
      - ti,tmp175
      - ti,tmp275
      - ti,tmp75
      - ti,tmp75b
      - ti,tmp75c

  reg:
    maxItems: 1

  vs-supply:
    description: phandle to the regulator that provides the +VS supply

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      sensor@48 {
        compatible = "st,stlm75";
        reg = <0x48>;
        vs-supply = <&vs>;
      };
    };


code:
*LM87 hwmon sensor.

Required properties:
- compatible: Should be
	"ti,lm87"

- reg: I2C address

optional properties:
- has-temp3: This configures pins 18 and 19 to be used as a second
             remote temperature sensing channel. By default the pins
             are configured as voltage input pins in0 and in5.

- has-in6: When set, pin 5 is configured to be used as voltage input
           in6. Otherwise the pin is set as FAN1 input.

- has-in7: When set, pin 6 is configured to be used as voltage input
           in7. Otherwise the pin is set as FAN2 input.

- vcc-supply: a Phandle for the regulator supplying power, can be
              cofigured to measure 5.0V power supply. Default is 3.3V.

Example:

lm87@2e {
	compatible = "ti,lm87";
	reg = <0x2e>;
	has-temp3;
	vcc-supply = <&reg_5v0>;
};


code:
ltc2978

Required properties:
- compatible: should contain one of:
  * "lltc,ltc2972"
  * "lltc,ltc2974"
  * "lltc,ltc2975"
  * "lltc,ltc2977"
  * "lltc,ltc2978"
  * "lltc,ltc2979"
  * "lltc,ltc2980"
  * "lltc,ltc3880"
  * "lltc,ltc3882"
  * "lltc,ltc3883"
  * "lltc,ltc3884"
  * "lltc,ltc3886"
  * "lltc,ltc3887"
  * "lltc,ltc3889"
  * "lltc,ltc7880"
  * "lltc,ltm2987"
  * "lltc,ltm4664"
  * "lltc,ltm4675"
  * "lltc,ltm4676"
  * "lltc,ltm4677"
  * "lltc,ltm4678"
  * "lltc,ltm4680"
  * "lltc,ltm4686"
  * "lltc,ltm4700"
- reg: I2C slave address

Optional properties:
- regulators: A node that houses a sub-node for each regulator controlled by
  the device. Each sub-node is identified using the node's name, with valid
  values listed below. The content of each sub-node is defined by the
  standard binding for regulators; see regulator.txt.

Valid names of regulators depend on number of supplies supported per device:
  * ltc2972 vout0 - vout1
  * ltc2974, ltc2975 : vout0 - vout3
  * ltc2977, ltc2979, ltc2980, ltm2987 : vout0 - vout7
  * ltc2978 : vout0 - vout7
  * ltc3880, ltc3882, ltc3884, ltc3886, ltc3887, ltc3889 : vout0 - vout1
  * ltc7880 : vout0 - vout1
  * ltc3883 : vout0
  * ltm4664 : vout0 - vout1
  * ltm4675, ltm4676, ltm4677, ltm4678 : vout0 - vout1
  * ltm4680, ltm4686 : vout0 - vout1
  * ltm4700 : vout0 - vout1

Example:
ltc2978@5e {
	compatible = "lltc,ltc2978";
	reg = <0x5e>;
	regulators {
		vout0 {
			regulator-name = "FPGA-2.5V";
		};
		vout2 {
			regulator-name = "FPGA-1.5V";
		};
	};
};


code:
ltc2990: Linear Technology LTC2990 power monitor

Required properties:
- compatible: Must be "lltc,ltc2990"
- reg: I2C slave address
- lltc,meas-mode:
	An array of two integers for configuring the chip measurement mode.

	The first integer defines the bits 2..0 in the control register. In all
	cases the internal temperature and supply voltage are measured. In
	addition the following input measurements are enabled per mode:

		0: V1, V2, TR2
		1: V1-V2, TR2
		2: V1-V2, V3, V4
		3: TR1, V3, V4
		4: TR1, V3-V4
		5: TR1, TR2
		6: V1-V2, V3-V4
		7: V1, V2, V3, V4

	The second integer defines the bits 4..3 in the control register. This
	allows a subset of the measurements to be enabled:

		0: Internal temperature and supply voltage only
		1: TR1, V1 or V1-V2 only per mode
		2: TR2, V3 or V3-V4 only per mode
		3: All measurements per mode

Example:

ltc2990@4c {
	compatible = "lltc,ltc2990";
	reg = <0x4c>;
	lltc,meas-mode = <7 3>;	/* V1, V2, V3, V4 */
};


code:
Lantiq cpu temperatur sensor

Requires node properties:
- compatible value :
	"lantiq,cputemp"

Example:
	cputemp@0 {
		compatible = "lantiq,cputemp";
	};


code:
Bindings for the Maxim MAX31785 Intelligent Fan Controller
==========================================================

Reference:

https://datasheets.maximintegrated.com/en/ds/MAX31785.pdf

The Maxim MAX31785 is a PMBus device providing closed-loop, multi-channel fan
management with temperature and remote voltage sensing. Various fan control
features are provided, including PWM frequency control, temperature hysteresis,
dual tachometer measurements, and fan health monitoring.

Required properties:
- compatible     : One of "maxim,max31785" or "maxim,max31785a"
- reg            : I2C address, one of 0x52, 0x53, 0x54, 0x55.

Example:

        fans@52 {
                compatible = "maxim,max31785";
                reg = <0x52>;
        };


code:
Bindings for MAX6651 and MAX6650 I2C fan controllers

Reference:
[1]	https://datasheets.maximintegrated.com/en/ds/MAX6650-MAX6651.pdf

Required properties:
- compatible : One of "maxim,max6650" or "maxim,max6651"
- reg        : I2C address, one of 0x1b, 0x1f, 0x4b, 0x48.

Optional properties, default is to retain the chip's current setting:
- maxim,fan-microvolt : The supply voltage of the fan, either 5000000 uV or
			12000000 uV.
- maxim,fan-prescale  : Pre-scaling value, as per datasheet [1]. Lower values
			allow more fine-grained control of slower fans.
			Valid: 1, 2, 4, 8, 16.
- maxim,fan-target-rpm: Initial requested fan rotation speed. If specified, the
			driver selects closed-loop mode and the requested speed.
			This ensures the fan is already running before userspace
			takes over.

Example:
	fan-max6650: max6650@1b {
		reg = <0x1b>;
		compatible = "maxim,max6650";
		maxim,fan-microvolt = <12000000>;
		maxim,fan-prescale = <4>;
		maxim,fan-target-rpm = <1200>;
	};


code:
max6697 properties

Required properties:
- compatible:
	Should be one of
		maxim,max6581
		maxim,max6602
		maxim,max6622
		maxim,max6636
		maxim,max6689
		maxim,max6693
		maxim,max6694
		maxim,max6697
		maxim,max6698
		maxim,max6699
- reg: I2C address

Optional properties:

- smbus-timeout-disable
	Set to disable SMBus timeout. If not specified, SMBus timeout will be
	enabled.
- extended-range-enable
	Only valid for MAX6581. Set to enable extended temperature range.
	Extended temperature will be disabled if not specified.
- beta-compensation-enable
	Only valid for MAX6693 and MX6694. Set to enable beta compensation on
	remote temperature channel 1.
	Beta compensation will be disabled if not specified.
- alert-mask
	Alert bit mask. Alert disabled for bits set.
	Select bit 0 for local temperature, bit 1..7 for remote temperatures.
	If not specified, alert will be enabled for all channels.
- over-temperature-mask
	Over-temperature bit mask. Over-temperature reporting disabled for
	bits set.
	Select bit 0 for local temperature, bit 1..7 for remote temperatures.
	If not specified, over-temperature reporting will be enabled for all
	channels.
- resistance-cancellation
	Boolean for all chips other than MAX6581. Set to enable resistance
	cancellation on remote temperature channel 1.
	For MAX6581, resistance cancellation enabled for all channels if
	specified as boolean, otherwise as per bit mask specified.
	Only supported for remote temperatures (bit 1..7).
	If not specified, resistance cancellation will be disabled for all
	channels.
- transistor-ideality
	For MAX6581 only. Two values; first is bit mask, second is ideality
	select value as per MAX6581 data sheet. Select bit 1..7 for remote
	channels.
	Transistor ideality will be initialized to default (1.008) if not
	specified.

Example:

temp-sensor@1a {
	compatible = "maxim,max6697";
	reg = <0x1a>;
	smbus-timeout-disable;
	resistance-cancellation;
	alert-mask = <0x72>;
	over-temperature-mask = <0x7f>;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---

$id: http://devicetree.org/schemas/hwmon/maxim,max20730.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Maxim max20730

maintainers:
  - Jean Delvare <jdelvare@suse.com>
  - Guenter Roeck <linux@roeck-us.net>

description: |
  The MAX20730 is a fully integrated, highly efficient switching regulator
  with PMBus for applications operating from 4.5V to 16V and requiring
  up to 25A (max) load. This single-chip regulator provides extremely
  compact, high efficiency power-delivery solutions with high-precision
  output voltages and excellent transient response.

  Datasheets:
    https://datasheets.maximintegrated.com/en/ds/MAX20730.pdf
    https://datasheets.maximintegrated.com/en/ds/MAX20734.pdf
    https://datasheets.maximintegrated.com/en/ds/MAX20743.pdf

properties:
  compatible:
    enum:
      - maxim,max20730
      - maxim,max20734
      - maxim,max20743

  reg:
    maxItems: 1

  vout-voltage-divider:
    description: |
      If voltage divider present at vout, the voltage at voltage sensor pin
      will be scaled. The properties will convert the raw reading to a more
      meaningful number if voltage divider present. It has two numbers,
      the first number is the output resistor, the second number is the total
      resistance. Therefore, the adjusted vout is equal to
      Vout = Vout * output_resistance / total resistance.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 2
    maxItems: 2

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      max20730@10 {
        compatible = "maxim,max20730";
        reg = <0x10>;
        vout-voltage-divider = <1000 2000>; // vout would be scaled to 0.5
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/microchip,lan966x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip LAN966x Hardware Monitor

maintainers:
  - Michael Walle <michael@walle.cc>

description: |
  Microchip LAN966x temperature monitor and fan controller

properties:
  compatible:
    enum:
      - microchip,lan9668-hwmon

  reg:
    items:
      - description: PVT registers
      - description: FAN registers

  reg-names:
    items:
      - const: pvt
      - const: fan

  clocks:
    maxItems: 1

  '#thermal-sensor-cells':
    const: 0

required:
  - compatible
  - reg
  - reg-names
  - clocks

additionalProperties: false

examples:
  - |
    hwmon: hwmon@e2010180 {
        compatible = "microchip,lan9668-hwmon";
        reg = <0xe2010180 0xc>,
              <0xe20042a8 0xc>;
        reg-names = "pvt", "fan";
        clocks = <&sys_clk>;
        #thermal-sensor-cells = <0>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/microchip,mcp3021.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip MCP3021 A/D converter

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - microchip,mcp3021
      - microchip,mcp3221

  reg:
    maxItems: 1

  reference-voltage-microvolt:
    description:
      VDD supply power and reference voltage

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        adc@4d {
            compatible = "microchip,mcp3021";
            reg = <0x4d>;

            reference-voltage-microvolt = <4500000>; /* 4.5 V */
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/microchip,sparx5-temp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip Sparx5 Temperature Monitor

maintainers:
  - Lars Povlsen <lars.povlsen@microchip.com>

description: |
  Microchip Sparx5 embedded temperature monitor

properties:
  compatible:
    enum:
      - microchip,sparx5-temp

  reg:
    maxItems: 1

  clocks:
    items:
      - description: System reference clock

  '#thermal-sensor-cells':
    const: 0

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    tmon0: tmon@610508110 {
        compatible = "microchip,sparx5-temp";
        reg = <0x10508110 0xc>;
        #thermal-sensor-cells = <0>;
        clocks = <&sys_clk>;
    };