code:
/*
 * ARM Ltd. Juno Platform
 *
 * Copyright (c) 2013-2014 ARM Ltd.
 *
 * This file is licensed under a dual GPLv2 or BSD license.
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/arm/coresight-cti-dt.h>
#include "juno-base.dtsi"

/ {
	model = "ARM Juno development board (r0)";
	compatible = "arm,juno", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &soc_uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&A57_0>;
				};
				core1 {
					cpu = <&A57_1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&A53_0>;
				};
				core1 {
					cpu = <&A53_1>;
				};
				core2 {
					cpu = <&A53_2>;
				};
				core3 {
					cpu = <&A53_3>;
				};
			};
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				local-timer-stop;
				entry-latency-us = <300>;
				exit-latency-us = <1200>;
				min-residency-us = <2000>;
			};

			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x1010000>;
				local-timer-stop;
				entry-latency-us = <400>;
				exit-latency-us = <1200>;
				min-residency-us = <2500>;
			};
		};

		A57_0: cpu@0 {
			compatible = "arm,cortex-a57";
			reg = <0x0 0x0>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&A57_L2>;
			clocks = <&scpi_dvfs 0>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <530>;
		};

		A57_1: cpu@1 {
			compatible = "arm,cortex-a57";
			reg = <0x0 0x1>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&A57_L2>;
			clocks = <&scpi_dvfs 0>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <530>;
		};

		A53_0: cpu@100 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <578>;
			dynamic-power-coefficient = <140>;
		};

		A53_1: cpu@101 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x101>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <578>;
			dynamic-power-coefficient = <140>;
		};

		A53_2: cpu@102 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x102>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <578>;
			dynamic-power-coefficient = <140>;
		};

		A53_3: cpu@103 {
			compatible = "arm,cortex-a53";
			reg = <0x0 0x103>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <578>;
			dynamic-power-coefficient = <140>;
		};

		A57_L2: l2-cache0 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>;
			cache-level = <2>;
		};

		A53_L2: l2-cache1 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x100000>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-level = <2>;
		};
	};

	pmu-a57 {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A57_0>,
				     <&A57_1>;
	};

	pmu-a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A53_0>,
				     <&A53_1>,
				     <&A53_2>,
				     <&A53_3>;
	};
};

&etm0 {
	cpu = <&A57_0>;
};

&etm1 {
	cpu = <&A57_1>;
};

&etm2 {
	cpu = <&A53_0>;
};

&etm3 {
	cpu = <&A53_1>;
};

&etm4 {
	cpu = <&A53_2>;
};

&etm5 {
	cpu = <&A53_3>;
};

&etf0_out_port {
	remote-endpoint = <&replicator_in_port0>;
};

&replicator_in_port0 {
	remote-endpoint = <&etf0_out_port>;
};

&stm_out_port {
	remote-endpoint = <&main_funnel_in_port2>;
};

&main_funnel_in_ports {
	port@2 {
		reg = <2>;
		main_funnel_in_port2: endpoint {
			remote-endpoint = <&stm_out_port>;
		};
	};
};

&cpu_debug0 {
	cpu = <&A57_0>;
};

&cpu_debug1 {
	cpu = <&A57_1>;
};

&cpu_debug2 {
	cpu = <&A53_0>;
};

&cpu_debug3 {
	cpu = <&A53_1>;
};

&cpu_debug4 {
	cpu = <&A53_2>;
};

&cpu_debug5 {
	cpu = <&A53_3>;
};

&cti0 {
	cpu = <&A57_0>;
};

&cti1 {
	cpu = <&A57_1>;
};

&cti2 {
	cpu = <&A53_0>;
};

&cti3 {
	cpu = <&A53_1>;
};

&cti4 {
	cpu = <&A53_2>;
};

&cti5 {
	cpu = <&A53_3>;
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Fast Models
 *
 * Architecture Envelope Model (AEM) ARMv8-A
 * ARMAEMv8AMPCT
 *
 * RTSM_VE_AEMv8A.lisa
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>

/memreserve/ 0x80000000 0x00010000;

#include "rtsm_ve-motherboard.dtsi"

/ {
	model = "RTSM_VE_AEMv8A";
	compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x8000fff8>;
			next-level-cache = <&L2_0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x8000fff8>;
			next-level-cache = <&L2_0>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x2>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x8000fff8>;
			next-level-cache = <&L2_0>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x3>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x8000fff8>;
			next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x80000000>,
		      <0x00000008 0x80000000 0 0x80000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* Chipselect 2,00000000 is physically at 0x18000000 */
		vram: vram@18000000 {
			/* 8 MB of designated video RAM */
			compatible = "shared-dma-pool";
			reg = <0x00000000 0x18000000 0 0x00800000>;
			no-map;
		};
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x0 0x2c001000 0 0x1000>,
		      <0x0 0x2c002000 0 0x2000>,
		      <0x0 0x2c004000 0 0x2000>,
		      <0x0 0x2c006000 0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <100000000>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	};

	panel {
		compatible = "arm,rtsm-display";
		port {
			panel_in: endpoint {
				remote-endpoint = <&clcd_pads>;
			};
		};
	};

	bus@8000000 {
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 63>;
		interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
				<0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Fast Models
 *
 * "rs2" extension for the v2m motherboard
 */
/ {
	bus@8000000 {
		motherboard-bus@8000000 {
			arm,v2m-memory-map = "rs2";

			iofpga-bus@300000000 {
				virtio@140000 {
					compatible = "virtio,mmio";
					reg = <0x140000 0x200>;
					interrupts = <43>;
				};

				virtio@150000 {
					compatible = "virtio,mmio";
					reg = <0x150000 0x200>;
					interrupts = <44>;
				};

				virtio@200000 {
					compatible = "virtio,mmio";
					reg = <0x200000 0x200>;
					interrupts = <46>;
					status = "disabled";
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Fast Models
 *
 * Versatile Express (VE) system model
 * Motherboard component
 *
 * VEMotherBoard.lisa
 */
/ {
	v2m_clk24mhz: clk24mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "v2m:clk24mhz";
	};

	v2m_refclk1mhz: refclk1mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <1000000>;
		clock-output-names = "v2m:refclk1mhz";
	};

	v2m_refclk32khz: refclk32khz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "v2m:refclk32khz";
	};

	v2m_fixed_3v3: v2m-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	mcc {
		compatible = "arm,vexpress,config-bus";
		arm,vexpress,config-bridge = <&v2m_sysreg>;

		v2m_oscclk1: oscclk1 {
			/* CLCD clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 1>;
			freq-range = <23750000 63500000>;
			#clock-cells = <0>;
			clock-output-names = "v2m:oscclk1";
		};

		reset {
			compatible = "arm,vexpress-reset";
			arm,vexpress-sysreg,func = <5 0>;
		};

		muxfpga {
			compatible = "arm,vexpress-muxfpga";
			arm,vexpress-sysreg,func = <7 0>;
		};

		shutdown {
			compatible = "arm,vexpress-shutdown";
			arm,vexpress-sysreg,func = <8 0>;
		};

		reboot {
			compatible = "arm,vexpress-reboot";
			arm,vexpress-sysreg,func = <9 0>;
		};

		dvimode {
			compatible = "arm,vexpress-dvimode";
			arm,vexpress-sysreg,func = <11 0>;
		};
	};

	bus@8000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0x8000000 0 0x8000000 0x18000000>;

		motherboard-bus@8000000 {
			compatible = "arm,vexpress,v2m-p1", "simple-bus";
			#address-cells = <2>; /* SMB chipselect number and offset */
			#size-cells = <1>;
			ranges = <0 0 0 0x08000000 0x04000000>,
				 <1 0 0 0x14000000 0x04000000>,
				 <2 0 0 0x18000000 0x04000000>,
				 <3 0 0 0x1c000000 0x04000000>,
				 <4 0 0 0x0c000000 0x04000000>,
				 <5 0 0 0x10000000 0x04000000>;

			flash@0 {
				compatible = "arm,vexpress-flash", "cfi-flash";
				reg = <0 0x00000000 0x04000000>,
				      <4 0x00000000 0x04000000>;
				bank-width = <4>;
			};

			ethernet@202000000 {
				compatible = "smsc,lan91c111";
				reg = <2 0x02000000 0x10000>;
				interrupts = <15>;
			};

			iofpga-bus@300000000 {
				compatible = "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 3 0 0x210000>;

				v2m_sysreg: sysreg@10000 {
					compatible = "arm,vexpress-sysreg";
					reg = <0x010000 0x1000>;
					gpio-controller;
					#gpio-cells = <2>;
				};

				v2m_sysctl: sysctl@20000 {
					compatible = "arm,sp810", "arm,primecell";
					reg = <0x020000 0x1000>;
					clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
					clock-names = "refclk", "timclk", "apb_pclk";
					#clock-cells = <1>;
					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
					assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
					assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
				};

				aaci@40000 {
					compatible = "arm,pl041", "arm,primecell";
					reg = <0x040000 0x1000>;
					interrupts = <11>;
					clocks = <&v2m_clk24mhz>;
					clock-names = "apb_pclk";
				};

				mmc@50000 {
					compatible = "arm,pl180", "arm,primecell";
					reg = <0x050000 0x1000>;
					interrupts = <9>, <10>;
					cd-gpios = <&v2m_sysreg 0 0>;
					wp-gpios = <&v2m_sysreg 1 0>;
					max-frequency = <12000000>;
					vmmc-supply = <&v2m_fixed_3v3>;
					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
					clock-names = "mclk", "apb_pclk";
				};

				kmi@60000 {
					compatible = "arm,pl050", "arm,primecell";
					reg = <0x060000 0x1000>;
					interrupts = <12>;
					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
					clock-names = "KMIREFCLK", "apb_pclk";
				};

				kmi@70000 {
					compatible = "arm,pl050", "arm,primecell";
					reg = <0x070000 0x1000>;
					interrupts = <13>;
					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
					clock-names = "KMIREFCLK", "apb_pclk";
				};

				v2m_serial0: serial@90000 {
					compatible = "arm,pl011", "arm,primecell";
					reg = <0x090000 0x1000>;
					interrupts = <5>;
					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
					clock-names = "uartclk", "apb_pclk";
				};

				v2m_serial1: serial@a0000 {
					compatible = "arm,pl011", "arm,primecell";
					reg = <0x0a0000 0x1000>;
					interrupts = <6>;
					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
					clock-names = "uartclk", "apb_pclk";
				};

				v2m_serial2: serial@b0000 {
					compatible = "arm,pl011", "arm,primecell";
					reg = <0x0b0000 0x1000>;
					interrupts = <7>;
					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
					clock-names = "uartclk", "apb_pclk";
				};

				v2m_serial3: serial@c0000 {
					compatible = "arm,pl011", "arm,primecell";
					reg = <0x0c0000 0x1000>;
					interrupts = <8>;
					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
					clock-names = "uartclk", "apb_pclk";
				};

				watchdog@f0000 {
					compatible = "arm,sp805", "arm,primecell";
					reg = <0x0f0000 0x1000>;
					interrupts = <0>;
					clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
					clock-names = "wdog_clk", "apb_pclk";
				};

				v2m_timer01: timer@110000 {
					compatible = "arm,sp804", "arm,primecell";
					reg = <0x110000 0x1000>;
					interrupts = <2>;
					clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
					clock-names = "timclken1", "timclken2", "apb_pclk";
				};

				v2m_timer23: timer@120000 {
					compatible = "arm,sp804", "arm,primecell";
					reg = <0x120000 0x1000>;
					interrupts = <3>;
					clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
					clock-names = "timclken1", "timclken2", "apb_pclk";
				};

				virtio@130000 {
					compatible = "virtio,mmio";
					reg = <0x130000 0x200>;
					interrupts = <42>;
				};

				rtc@170000 {
					compatible = "arm,pl031", "arm,primecell";
					reg = <0x170000 0x1000>;
					interrupts = <4>;
					clocks = <&v2m_clk24mhz>;
					clock-names = "apb_pclk";
				};

				clcd@1f0000 {
					compatible = "arm,pl111", "arm,primecell";
					reg = <0x1f0000 0x1000>;
					interrupt-names = "combined";
					interrupts = <14>;
					clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
					clock-names = "clcdclk", "apb_pclk";
					memory-region = <&vram>;

					port {
						clcd_pads: endpoint {
							remote-endpoint = <&panel_in>;
							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
						};
					};
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Versatile Express
 *
 * LogicTile Express 20MG
 * V2F-1XV7
 *
 * Cortex-A53 (2 cores) Soft Macrocell Model
 *
 * HBI-0247C
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "vexpress-v2m-rs1.dtsi"

/ {
	model = "V2F-1XV7 Cortex-A53x2 SMM";
	arm,hbi = <0x247>;
	arm,vexpress,site = <0xf>;
	compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		stdout-path = "serial0:38400n8";
	};

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
		i2c0 = &v2m_i2c_dvi;
		i2c1 = &v2m_i2c_pcie;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0 0>;
			next-level-cache = <&L2_0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0 1>;
			next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* Chipselect 2 is physically at 0x18000000 */
		vram: vram@18000000 {
			/* 8 MB of designated video RAM */
			compatible = "shared-dma-pool";
			reg = <0 0x18000000 0 0x00800000>;
			no-map;
		};
	};

	gic: interrupt-controller@2c001000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0x2c001000 0 0x1000>,
		      <0 0x2c002000 0 0x2000>,
		      <0 0x2c004000 0 0x2000>,
		      <0 0x2c006000 0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
	};

	dcc {
		compatible = "arm,vexpress,config-bus";
		arm,vexpress,config-bridge = <&v2m_sysreg>;

		smbclk: smclk {
			/* SMC clock */
			compatible = "arm,vexpress-osc";
			arm,vexpress-sysreg,func = <1 4>;
			freq-range = <40000000 40000000>;
			#clock-cells = <0>;
			clock-output-names = "smclk";
		};

		volt-vio {
			/* VIO to expansion board above */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 0>;
			regulator-name = "VIO_UP";
			regulator-min-microvolt = <800000>;
			regulator-max-microvolt = <1800000>;
			regulator-always-on;
		};

		volt-12v {
			/* 12V from power connector J6 */
			compatible = "arm,vexpress-volt";
			arm,vexpress-sysreg,func = <2 1>;
			regulator-name = "12";
			regulator-always-on;
		};

		temp-fpga {
			/* FPGA temperature */
			compatible = "arm,vexpress-temp";
			arm,vexpress-sysreg,func = <4 0>;
			label = "FPGA";
		};
	};

	smb: bus@8000000 {
		ranges = <0x8000000 0 0x8000000 0x18000000>;
	};
};


code:
# SPDX-License-Identifier: GPL-2.0+

dtb-$(CONFIG_ARCH_BITMAIN) += bm1880-sophon-edge.dtb


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Linaro Ltd.
 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 */

/dts-v1/;

#include "bm1880.dtsi"

/*
 * GPIO name legend: proper name = the GPIO line is used as GPIO
 *         NC = not connected (pin out but not routed from the chip to
 *              anything the board)
 *         "[PER]" = pin is muxed for [peripheral] (not GPIO)
 *         LSEC = Low Speed External Connector
 *         HSEC = High Speed External Connector
 *
 * Line names are taken from the schematic "sophon-edge-schematics"
 * version, 1.0210.
 *
 * For the lines routed to the external connectors the
 * lines are named after the 96Boards CE Specification 1.0,
 * Appendix "Expansion Connector Signal Description".
 *
 * When the 96Board naming of a line and the schematic name of
 * the same line are in conflict, the 96Board specification
 * takes precedence. This is only for the informational
 * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
 * are the only ones actually used for GPIO.
 */

/ {
	compatible = "bitmain,sophon-edge", "bitmain,bm1880";
	model = "Sophon Edge";

	aliases {
		serial0 = &uart0;
		serial1 = &uart2;
		serial2 = &uart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
	};

	soc {
		gpio0: gpio@50027000 {
			porta: gpio-controller@0 {
				gpio-line-names =
					"GPIO-A", /* GPIO0, LSEC pin 23 */
					"GPIO-C", /* GPIO1, LSEC pin 25 */
					"[GPIO2_PHY0_RST]", /* GPIO2 */
					"GPIO-E", /* GPIO3, LSEC pin 27 */
					"[USB_DET]", /* GPIO4 */
					"[EN_P5V]", /* GPIO5 */
					"[VDDIO_MS1_SEL]", /* GPIO6 */
					"GPIO-G", /* GPIO7, LSEC pin 29 */
					"[BM_TUSB_RST_L]", /* GPIO8 */
					"[EN_P5V_USBHUB]", /* GPIO9 */
					"NC",
					"LED_WIFI", /* GPIO11 */
					"LED_BT", /* GPIO12 */
					"[BM_BLM8221_EN_L]", /* GPIO13 */
					"NC", /* GPIO14 */
					"NC", /* GPIO15 */
					"NC", /* GPIO16 */
					"NC", /* GPIO17 */
					"NC", /* GPIO18 */
					"NC", /* GPIO19 */
					"NC", /* GPIO20 */
					"NC", /* GPIO21 */
					"NC", /* GPIO22 */
					"NC", /* GPIO23 */
					"NC", /* GPIO24 */
					"NC", /* GPIO25 */
					"NC", /* GPIO26 */
					"NC", /* GPIO27 */
					"NC", /* GPIO28 */
					"NC", /* GPIO29 */
					"NC", /* GPIO30 */
					"NC"; /* GPIO31 */
			};
		};

		gpio1: gpio@50027400 {
			portb: gpio-controller@0 {
				gpio-line-names =
					"NC", /* GPIO32 */
					"NC", /* GPIO33 */
					"[I2C0_SDA]", /* GPIO34, LSEC pin 17 */
					"[I2C0_SCL]", /* GPIO35, LSEC pin 15 */
					"[JTAG0_TDO]", /* GPIO36 */
					"[JTAG0_TCK]", /* GPIO37 */
					"[JTAG0_TDI]", /* GPIO38 */
					"[JTAG0_TMS]", /* GPIO39 */
					"[JTAG0_TRST_X]", /* GPIO40 */
					"[JTAG1_TDO]", /* GPIO41 */
					"[JTAG1_TCK]", /* GPIO42 */
					"[JTAG1_TDI]", /* GPIO43 */
					"[CPU_TX]", /* GPIO44 */
					"[CPU_RX]", /* GPIO45 */
					"[UART1_TXD]", /* GPIO46 */
					"[UART1_RXD]", /* GPIO47 */
					"[UART0_TXD]", /* GPIO48 */
					"[UART0_RXD]", /* GPIO49 */
					"GPIO-I", /* GPIO50, LSEC pin 31 */
					"GPIO-K", /* GPIO51, LSEC pin 33 */
					"USER_LED2", /* GPIO52 */
					"USER_LED1", /* GPIO53 */
					"[UART0_RTS]", /* GPIO54 */
					"[UART0_CTS]", /* GPIO55 */
					"USER_LED4", /* GPIO56, JTAG1_TRST_X */
					"USER_LED3", /* GPIO57, JTAG1_TMS */
					"[I2S0_SCLK]", /* GPIO58 */
					"[I2S0_FS]", /* GPIO59 */
					"[I2S0_SDI]", /* GPIO60 */
					"[I2S0_SDO]", /* GPIO61 */
					"GPIO-B", /* GPIO62, LSEC pin 24 */
					"GPIO-F"; /* GPIO63, I2S1_SCLK, LSEC pin 28 */
			};
		};

		gpio2: gpio@50027800 {
			portc: gpio-controller@0 {
				gpio-line-names =
					"GPIO-D", /* GPIO64, I2S1_FS, LSEC pin 26 */
					"GPIO-J", /* GPIO65, I2S1_SDI, LSEC pin 32 */
					"GPIO-H", /* GPIO66, I2S1_SDO, LSEC pin 30 */
					"GPIO-L", /* GPIO67, LSEC pin 34 */
					"[SPI0_CS]", /* GPIO68, SPI1_CS, LSEC pin 12 */
					"[SPI0_DIN]", /* GPIO69, SPI1_SDI, LSEC pin 10 */
					"[SPI0_DOUT]", /* GPIO70, SPI1_SDO, LSEC pin 14 */
					"[SPI0_SCLK]"; /* GPIO71, SPI1_SCK, LSEC pin 8 */
			};
		};
	};
};

&pinctrl {
	pinctrl_uart0_default: pinctrl-uart0-default {
		pinmux {
			groups = "uart0_grp";
			function = "uart0";
		};
	};

	pinctrl_uart1_default: pinctrl-uart1-default {
		pinmux {
			groups = "uart1_grp";
			function = "uart1";
		};
	};

	pinctrl_uart2_default: pinctrl-uart2-default {
		pinmux {
			groups = "uart2_grp";
			function = "uart2";
		};
	};
};

&uart0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0_default>;
};

&uart1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1_default>;
};

&uart2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2_default>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Linaro Ltd.
 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 */

#include <dt-bindings/clock/bm1880-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/bitmain,bm1880-reset.h>

/ {
	compatible = "bitmain,bm1880";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secmon@100000000 {
			reg = <0x1 0x00000000 0x0 0x20000>;
			no-map;
		};

		jpu@130000000 {
			reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
			no-map;
		};

		vpu@138000000 {
			reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
			no-map;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	osc: osc {
		compatible = "fixed-clock";
		clock-frequency = <25000000>;
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@50001000 {
			compatible = "arm,gic-400";
			reg = <0x0 0x50001000 0x0 0x1000>,
			      <0x0 0x50002000 0x0 0x2000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		sctrl: system-controller@50010000 {
			compatible = "bitmain,bm1880-sctrl", "syscon",
				     "simple-mfd";
			reg = <0x0 0x50010000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x50010000 0x1000>;

			pinctrl: pinctrl@400 {
				compatible = "bitmain,bm1880-pinctrl";
				reg = <0x400 0x120>;
			};

			clk: clock-controller@e8 {
				compatible = "bitmain,bm1880-clk";
				reg = <0xe8 0x0c>, <0x800 0xb0>;
				reg-names = "pll", "sys";
				clocks = <&osc>;
				clock-names = "osc";
				#clock-cells = <1>;
			};

			rst: reset-controller@c00 {
				compatible = "bitmain,bm1880-reset";
				reg = <0xc00 0x8>;
				#reset-cells = <1>;
			};
		};

		gpio0: gpio@50027000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x0 0x50027000 0x0 0x400>;

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio1: gpio@50027400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x0 0x50027400 0x0 0x400>;

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio2: gpio@50027800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x0 0x50027800 0x0 0x400>;

			portc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <8>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		uart0: serial@58018000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x58018000 0x0 0x2000>;
			clocks = <&clk BM1880_CLK_UART_500M>,
				 <&clk BM1880_CLK_APB_UART>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst BM1880_RST_UART0_1_CLK>;
			status = "disabled";
		};

		uart1: serial@5801A000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x5801a000 0x0 0x2000>;
			clocks = <&clk BM1880_CLK_UART_500M>,
				 <&clk BM1880_CLK_APB_UART>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst BM1880_RST_UART0_1_ACLK>;
			status = "disabled";
		};

		uart2: serial@5801C000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x5801c000 0x0 0x2000>;
			clocks = <&clk BM1880_CLK_UART_500M>,
				 <&clk BM1880_CLK_APB_UART>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst BM1880_RST_UART2_3_CLK>;
			status = "disabled";
		};

		uart3: serial@5801E000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x5801e000 0x0 0x2000>;
			clocks = <&clk BM1880_CLK_UART_500M>,
				 <&clk BM1880_CLK_APB_UART>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst BM1880_RST_UART2_3_ACLK>;
			status = "disabled";
		};
	};
};


code:
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
			      bcm2711-rpi-4-b.dtb \
			      bcm2711-rpi-cm4-io.dtb \
			      bcm2837-rpi-3-a-plus.dtb \
			      bcm2837-rpi-3-b.dtb \
			      bcm2837-rpi-3-b-plus.dtb \
			      bcm2837-rpi-cm3-io3.dtb \
			      bcm2837-rpi-zero-2-w.dtb

subdir-y	+= bcmbca
subdir-y	+= northstar2
subdir-y	+= stingray


code:
// SPDX-License-Identifier: GPL-2.0
#include "arm/bcm2711-rpi-4-b.dts"


code:
// SPDX-License-Identifier: GPL-2.0
#include "arm/bcm2711-rpi-400.dts"


code:
// SPDX-License-Identifier: GPL-2.0
#include "arm/bcm2711-rpi-cm4-io.dts"


code:
// SPDX-License-Identifier: GPL-2.0
#include "arm/bcm2837-rpi-3-a-plus.dts"


code:
// SPDX-License-Identifier: GPL-2.0
#include "arm/bcm2837-rpi-3-b-plus.dts"


code:
// SPDX-License-Identifier: GPL-2.0
#include "arm/bcm2837-rpi-3-b.dts"


code:
// SPDX-License-Identifier: GPL-2.0
#include "arm/bcm2837-rpi-cm3-io3.dts"


code:
// SPDX-License-Identifier: GPL-2.0
#include "arm/bcm2837-rpi-zero-2-w.dts"


code:
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_BCMBCA) += \
				bcm4906-netgear-r8000p.dtb \
				bcm4906-tplink-archer-c2300-v1.dtb \
				bcm4908-asus-gt-ac5300.dtb \
				bcm4908-netgear-raxe500.dtb \
				bcm94908.dtb \
				bcm4912-asus-gt-ax6000.dtb \
				bcm94912.dtb \
				bcm963158.dtb \
				bcm96858.dtb \
				bcm963146.dtb \
				bcm96856.dtb \
				bcm96813.dtb


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

#include "bcm4906.dtsi"

/ {
	compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
	model = "Netgear R8000P";

	memory@0 {
		device_type = "memory";
		reg = <0x00 0x00 0x00 0x20000000>;
	};

	leds {
		compatible = "gpio-leds";

		led-power-white {
			function = LED_FUNCTION_POWER;
			color = <LED_COLOR_ID_WHITE>;
			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
		};

		led-power-amber {
			function = LED_FUNCTION_POWER;
			color = <LED_COLOR_ID_AMBER>;
			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
		};

		led-wps {
			function = LED_FUNCTION_WPS;
			color = <LED_COLOR_ID_WHITE>;
			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
		};

		led-2ghz {
			function = "2ghz";
			color = <LED_COLOR_ID_WHITE>;
			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
		};

		led-5ghz-1 {
			function = "5ghz-1";
			color = <LED_COLOR_ID_WHITE>;
			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
		};

		led-5ghz-2 {
			function = "5ghz-2";
			color = <LED_COLOR_ID_WHITE>;
			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
		};

		led-usb2 {
			function = "usb2";
			color = <LED_COLOR_ID_WHITE>;
			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
		};

		led-usb3 {
			function = "usb3";
			color = <LED_COLOR_ID_WHITE>;
			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
		};

		led-wifi {
			function = "wifi";
			color = <LED_COLOR_ID_WHITE>;
			gpios = <&gpio0 56 GPIO_ACTIVE_LOW>;
		};
	};
};

&enet {
	nvmem-cells = <&base_mac_addr>;
	nvmem-cell-names = "mac-address";
};

&usb_phy {
	brcm,ioc = <1>;
	status = "okay";
};

&ehci {
	status = "okay";
};

&ohci {
	status = "okay";
};

&xhci {
	status = "okay";
};

&ports {
	port@0 {
		label = "lan4";
	};

	port@1 {
		label = "lan3";
	};

	port@2 {
		label = "lan2";
	};

	port@3 {
		label = "lan1";
	};

	port@7 {
		reg = <7>;
		phy-mode = "internal";
		phy-handle = <&phy12>;
		label = "wan";
	};
};

&nandcs {
	nand-ecc-strength = <4>;
	nand-ecc-step-size = <512>;
	nand-on-flash-bbt;

	#address-cells = <1>;
	#size-cells = <0>;

	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			compatible = "nvmem-cells";
			label = "cferom";
			reg = <0x0 0x100000>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x0 0x100000>;

			base_mac_addr: mac@106a0 {
				reg = <0x106a0 0x6>;
			};
		};

		partition@100000 {
			compatible = "brcm,bcm4908-firmware";
			label = "firmware";
			reg = <0x100000 0x4400000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

#include "bcm4906.dtsi"

/ {
	compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
	model = "TP-Link Archer C2300 V1";

	memory@0 {
		device_type = "memory";
		reg = <0x00 0x00 0x00 0x20000000>;
	};

	leds {
		compatible = "gpio-leds";

		led-power {
			function = LED_FUNCTION_POWER;
			color = <LED_COLOR_ID_BLUE>;
			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
		};

		led-2ghz {
			function = "2ghz";
			color = <LED_COLOR_ID_BLUE>;
			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
		};

		led-5ghz {
			function = "5ghz";
			color = <LED_COLOR_ID_BLUE>;
			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
		};

		led-wan-amber {
			function = LED_FUNCTION_WAN;
			color = <LED_COLOR_ID_AMBER>;
			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
		};

		led-wan-blue {
			function = LED_FUNCTION_WAN;
			color = <LED_COLOR_ID_BLUE>;
			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
		};

		led-lan {
			function = LED_FUNCTION_LAN;
			color = <LED_COLOR_ID_BLUE>;
			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
		};

		led-wps {
			function = LED_FUNCTION_WPS;
			color = <LED_COLOR_ID_BLUE>;
			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
		};

		led-usb2 {
			function = "usb2";
			color = <LED_COLOR_ID_BLUE>;
			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
		};

		led-usb3 {
			function = "usbd3";
			color = <LED_COLOR_ID_BLUE>;
			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
		};

		led-brightness {
			function = LED_FUNCTION_BACKLIGHT;
			color = <LED_COLOR_ID_WHITE>;
			gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-keys-polled {
		compatible = "gpio-keys-polled";
		poll-interval = <100>;

		key-brightness {
			label = "LEDs";
			linux,code = <KEY_BRIGHTNESS_ZERO>;
			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
		};

		key-wps {
			label = "WPS";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
		};

		key-wifi {
			label = "WiFi";
			linux,code = <KEY_RFKILL>;
			gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
		};

		key-restart {
			label = "Reset";
			linux,code = <KEY_RESTART>;
			gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
		};
	};
};

&usb_phy {
	brcm,ioc = <1>;
	status = "okay";
};

&ehci {
	status = "okay";
};

&ohci {
	status = "okay";
};

&xhci {
	status = "okay";
};

&ports {
	port@0 {
		label = "lan4";
	};

	port@1 {
		label = "lan3";
	};

	port@2 {
		label = "lan2";
	};

	port@3 {
		label = "lan1";
	};

	port@7 {
		reg = <7>;
		phy-mode = "internal";
		phy-handle = <&phy12>;
		label = "wan";
	};
};

&nandcs {
	nand-ecc-strength = <4>;
	nand-ecc-step-size = <512>;
	nand-on-flash-bbt;

	#address-cells = <1>;
	#size-cells = <0>;

	partitions {
		compatible = "brcm,bcm4908-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "cferom";
			reg = <0x0 0x100000>;
		};

		partition@100000 {
			compatible = "brcm,bcm4908-firmware";
			reg = <0x100000 0x3900000>;
		};

		partition@5800000 {
			compatible = "brcm,bcm4908-firmware";
			reg = <0x3a00000 0x3900000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include "bcm4908.dtsi"

/ {
	cpus {
		/delete-node/ cpu@2;

		/delete-node/ cpu@3;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

#include "bcm4908.dtsi"

/ {
	compatible = "asus,gt-ac5300", "brcm,bcm4908", "brcm,bcmbca";
	model = "Asus GT-AC5300";

	memory@0 {
		device_type = "memory";
		reg = <0x00 0x00 0x00 0x40000000>;
	};

	gpio-keys-polled {
		compatible = "gpio-keys-polled";
		poll-interval = <100>;

		key-wifi {
			label = "WiFi";
			linux,code = <KEY_RFKILL>;
			gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
		};

		key-wps {
			label = "WPS";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
		};

		key-restart {
			label = "Reset";
			linux,code = <KEY_RESTART>;
			gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
		};

		key-brightness {
			label = "LEDs";
			linux,code = <KEY_BRIGHTNESS_ZERO>;
			gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
		};
	};
};

&enet {
	nvmem-cells = <&base_mac_addr>;
	nvmem-cell-names = "mac-address";
};

&usb_phy {
	brcm,ioc = <1>;
	status = "okay";
};

&ehci {
	status = "okay";
};

&ohci {
	status = "okay";
};

&xhci {
	status = "okay";
};

&ports {
	port@0 {
		label = "lan2";
	};

	port@1 {
		label = "lan1";
	};

	port@2 {
		label = "lan6";
	};

	port@3 {
		label = "lan5";
	};

	/* External BCM53134S switch */
	port@7 {
		label = "sw";
		reg = <7>;
		phy-mode = "rgmii";

		fixed-link {
			speed = <1000>;
			full-duplex;
		};
	};
};

&mdio {
	/* lan8 */
	ethernet-phy@0 {
		reg = <0>;
	};

	/* lan7 */
	ethernet-phy@1 {
		reg = <1>;
	};

	/* lan4 */
	ethernet-phy@2 {
		reg = <2>;
	};

	/* lan3 */
	ethernet-phy@3 {
		reg = <3>;
	};
};

&leds {
	led-power@11 {
		reg = <0x11>;
		function = LED_FUNCTION_POWER;
		color = <LED_COLOR_ID_WHITE>;
		default-state = "on";
		active-low;
		pinctrl-names = "default";
		pinctrl-0 = <&pins_led_17_a>;
	};

	led-wan-red@12 {
		reg = <0x12>;
		function = LED_FUNCTION_WAN;
		color = <LED_COLOR_ID_RED>;
		active-low;
		pinctrl-names = "default";
		pinctrl-0 = <&pins_led_18_a>;
	};

	led-wps@14 {
		reg = <0x14>;
		function = LED_FUNCTION_WPS;
		color = <LED_COLOR_ID_WHITE>;
		active-low;
		pinctrl-names = "default";
		pinctrl-0 = <&pins_led_20_a>;
	};

	led-wan-white@15 {
		reg = <0x15>;
		function = LED_FUNCTION_WAN;
		color = <LED_COLOR_ID_WHITE>;
		active-low;
		pinctrl-names = "default";
		pinctrl-0 = <&pins_led_21_a>;
	};

	led-lan@19 {
		reg = <0x19>;
		function = LED_FUNCTION_LAN;
		color = <LED_COLOR_ID_WHITE>;
		pinctrl-names = "default";
		pinctrl-0 = <&pins_led_25_a>;
	};
};

&nandcs {
	nand-ecc-strength = <4>;
	nand-ecc-step-size = <512>;
	nand-on-flash-bbt;
	brcm,nand-has-wp;

	#address-cells = <1>;
	#size-cells = <0>;

	partitions {
		compatible = "brcm,bcm4908-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			compatible = "nvmem-cells";
			label = "cferom";
			reg = <0x0 0x100000>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x0 0x100000>;

			base_mac_addr: mac@106a0 {
				reg = <0x106a0 0x6>;
			};
		};

		partition@100000 {
			compatible = "brcm,bcm4908-firmware";
			reg = <0x100000 0x5700000>;
		};

		partition@5800000 {
			compatible = "brcm,bcm4908-firmware";
			reg = <0x5800000 0x5700000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include "bcm4908.dtsi"

/ {
	compatible = "netgear,raxe500", "brcm,bcm4908", "brcm,bcmbca";
	model = "Netgear RAXE500";

	memory@0 {
		device_type = "memory";
		reg = <0x00 0x00 0x00 0x40000000>;
	};
};

&ehci {
	status = "okay";
};

&ohci {
	status = "okay";
};

&xhci {
	status = "okay";
};

&ports {
	port@0 {
		label = "lan4";
	};

	port@1 {
		label = "lan3";
	};

	port@2 {
		label = "lan2";
	};

	port@3 {
		label = "lan1";
	};

	port@7 {
		reg = <7>;
		phy-mode = "internal";
		phy-handle = <&phy12>;
		label = "wan";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/soc/bcm-pmb.h>

/dts-v1/;

/ {
	interrupt-parent = <&gic>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "brcm,brahma-b53";
			reg = <0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0xfff8>;
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "brcm,brahma-b53";
			reg = <0x1>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0xfff8>;
			next-level-cache = <&l2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "brcm,brahma-b53";
			reg = <0x2>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0xfff8>;
			next-level-cache = <&l2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "brcm,brahma-b53";
			reg = <0x3>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0xfff8>;
			next-level-cache = <&l2>;
		};

		l2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00 0x00 0x81000000 0x4000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x1000 0x1000>,
			      <0x2000 0x2000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	clocks {
		periph_clk: periph_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <50000000>;
			clock-output-names = "periph";
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00 0x00 0x80000000 0x281000>;

		enet: ethernet@2000 {
			compatible = "brcm,bcm4908-enet";
			reg = <0x2000 0x1000>;

			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "rx", "tx";
		};

		usb_phy: usb-phy@c200 {
			compatible = "brcm,bcm4908-usb-phy";
			reg = <0xc200 0x100>;
			reg-names = "ctrl";
			power-domains = <&pmb BCM_PMB_HOST_USB>;
			dr_mode = "host";
			brcm,has-xhci;
			brcm,has-eohci;
			#phy-cells = <1>;
			status = "disabled";
		};

		ehci: usb@c300 {
			compatible = "generic-ehci";
			reg = <0xc300 0x100>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&usb_phy PHY_TYPE_USB2>;
			status = "disabled";
		};

		ohci: usb@c400 {
			compatible = "generic-ohci";
			reg = <0xc400 0x100>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&usb_phy PHY_TYPE_USB2>;
			status = "disabled";
		};

		xhci: usb@d000 {
			compatible = "generic-xhci";
			reg = <0xd000 0x8c8>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&usb_phy PHY_TYPE_USB3>;
			status = "disabled";
		};

		bus@80000 {
			compatible = "simple-bus";
			#size-cells = <1>;
			#address-cells = <1>;
			ranges = <0 0x80000 0x50000>;

			ethernet-switch@0 {
				compatible = "brcm,bcm4908-switch";
				reg = <0x0 0x40000>,
				      <0x40000 0x110>,
				      <0x40340 0x30>,
				      <0x40380 0x30>,
				      <0x40600 0x34>,
				      <0x40800 0x208>;
				reg-names = "core", "reg", "intrl2_0",
					    "intrl2_1", "fcb", "acb";
				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
				brcm,num-gphy = <5>;
				brcm,num-rgmii-ports = <2>;

				#address-cells = <1>;
				#size-cells = <0>;

				ports: ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						phy-mode = "internal";
						phy-handle = <&phy8>;
					};

					port@1 {
						reg = <1>;
						phy-mode = "internal";
						phy-handle = <&phy9>;
					};

					port@2 {
						reg = <2>;
						phy-mode = "internal";
						phy-handle = <&phy10>;
					};

					port@3 {
						reg = <3>;
						phy-mode = "internal";
						phy-handle = <&phy11>;
					};

					port@8 {
						reg = <8>;
						phy-mode = "internal";
						ethernet = <&enet>;

						fixed-link {
							speed = <1000>;
							full-duplex;
						};
					};
				};
			};

			mdio: mdio@405c0 {
				compatible = "brcm,unimac-mdio";
				reg = <0x405c0 0x8>;
				reg-names = "mdio";
				#size-cells = <0>;
				#address-cells = <1>;

				phy8: ethernet-phy@8 {
					reg = <8>;
				};

				phy9: ethernet-phy@9 {
					reg = <9>;
				};

				phy10: ethernet-phy@a {
					reg = <10>;
				};

				phy11: ethernet-phy@b {
					reg = <11>;
				};

				phy12: ethernet-phy@c {
					reg = <12>;
				};
			};
		};

		procmon: syscon@280000 {
			compatible = "simple-bus";
			reg = <0x280000 0x1000>;
			ranges;

			#address-cells = <1>;
			#size-cells = <1>;

			pmb: power-controller@2800c0 {
				compatible = "brcm,bcm4908-pmb";
				reg = <0x2800c0 0x40>;
				#power-domain-cells = <1>;
			};
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00 0x00 0xff800000 0x3000>;

		twd: timer-mfd@400 {
			compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
			reg = <0x400 0x4c>;
			ranges = <0x0 0x400 0x4c>;

			#address-cells = <1>;
			#size-cells = <1>;

			timer@0 {
				compatible = "brcm,bcm63138-timer";
				reg = <0x0 0x28>;
			};

			watchdog@28 {
				compatible = "brcm,bcm6345-wdt";
				reg = <0x28 0x8>;
			};
		};

		gpio0: gpio-controller@500 {
			compatible = "brcm,bcm6345-gpio";
			reg-names = "dirout", "dat";
			reg = <0x500 0x28>, <0x528 0x28>;

			#gpio-cells = <2>;
			gpio-controller;
		};

		pinctrl@560 {
			compatible = "brcm,bcm4908-pinctrl";
			reg = <0x560 0x10>;

			pins_led_0_a: led_0-a-pins {
				function = "led_0";
				groups = "led_0_grp_a";
			};

			pins_led_1_a: led_1-a-pins {
				function = "led_1";
				groups = "led_1_grp_a";
			};

			pins_led_2_a: led_2-a-pins {
				function = "led_2";
				groups = "led_2_grp_a";
			};

			pins_led_3_a: led_3-a-pins {
				function = "led_3";
				groups = "led_3_grp_a";
			};

			pins_led_4_a: led_4-a-pins {
				function = "led_4";
				groups = "led_4_grp_a";
			};

			pins_led_5_a: led_5-a-pins {
				function = "led_5";
				groups = "led_5_grp_a";
			};

			pins_led_6_a: led_6-a-pins {
				function = "led_6";
				groups = "led_6_grp_a";
			};

			pins_led_7_a: led_7-a-pins {
				function = "led_7";
				groups = "led_7_grp_a";
			};

			pins_led_8_a: led_8-a-pins {
				function = "led_8";
				groups = "led_8_grp_a";
			};

			pins_led_9_a: led_9-a-pins {
				function = "led_9";
				groups = "led_9_grp_a";
			};

			pins_led_10_a: led_10-a-pins {
				function = "led_10";
				groups = "led_10_grp_a";
			};

			pins_led_11_a: led_11-a-pins {
				function = "led_11";
				groups = "led_11_grp_a";
			};

			pins_led_12_a: led_12-a-pins {
				function = "led_12";
				groups = "led_12_grp_a";
			};

			pins_led_13_a: led_13-a-pins {
				function = "led_13";
				groups = "led_13_grp_a";
			};

			pins_led_14_a: led_14-a-pins {
				function = "led_14";
				groups = "led_14_grp_a";
			};

			pins_led_15_a: led_15-a-pins {
				function = "led_15";
				groups = "led_15_grp_a";
			};

			pins_led_16_a: led_16-a-pins {
				function = "led_16";
				groups = "led_16_grp_a";
			};

			pins_led_17_a: led_17-a-pins {
				function = "led_17";
				groups = "led_17_grp_a";
			};

			pins_led_18_a: led_18-a-pins {
				function = "led_18";
				groups = "led_18_grp_a";
			};

			pins_led_19_a: led_19-a-pins {
				function = "led_19";
				groups = "led_19_grp_a";
			};

			pins_led_20_a: led_20-a-pins {
				function = "led_20";
				groups = "led_20_grp_a";
			};

			pins_led_21_a: led_21-a-pins {
				function = "led_21";
				groups = "led_21_grp_a";
			};

			pins_led_22_a: led_22-a-pins {
				function = "led_22";
				groups = "led_22_grp_a";
			};

			pins_led_23_a: led_23-a-pins {
				function = "led_23";
				groups = "led_23_grp_a";
			};

			pins_led_24_a: led_24-a-pins {
				function = "led_24";
				groups = "led_24_grp_a";
			};

			pins_led_25_a: led_25-a-pins {
				function = "led_25";
				groups = "led_25_grp_a";
			};

			pins_led_26_a: led_26-a-pins {
				function = "led_26";
				groups = "led_26_grp_a";
			};

			pins_led_27_a: led_27-a-pins {
				function = "led_27";
				groups = "led_27_grp_a";
			};

			pins_led_28_a: led_28-a-pins {
				function = "led_28";
				groups = "led_28_grp_a";
			};

			pins_led_29_a: led_29-a-pins {
				function = "led_29";
				groups = "led_29_grp_a";
			};

			pins_led_30_a: led_30-a-pins {
				function = "led_30";
				groups = "led_30_grp_a";
			};

			pins_led_31_a: led_31-a-pins {
				function = "led_31";
				groups = "led_31_grp_a";
			};

			pins_hs_uart: hs_uart-pins {
				function = "hs_uart";
				groups = "hs_uart_grp";
			};

			pins_i2c_a: i2c-a-pins {
				function = "i2c";
				groups = "i2c_grp_a";
			};

			pins_i2c_b: i2c-b-pins {
				function = "i2c";
				groups = "i2c_grp_b";
			};

			pins_i2s: i2s-pins {
				function = "i2s";
				groups = "i2s_grp";
			};

			pins_nand_ctrl: nand_ctrl-pins {
				function = "nand_ctrl";
				groups = "nand_ctrl_grp";
			};

			pins_nand_data: nand_data-pins {
				function = "nand_data";
				groups = "nand_data_grp";
			};

			pins_emmc_ctrl: emmc_ctrl-pins {
				function = "emmc_ctrl";
				groups = "emmc_ctrl_grp";
			};

			pins_usb0_pwr: usb0_pwr-pins {
				function = "usb0_pwr";
				groups = "usb0_pwr_grp";
			};

			pins_usb1_pwr: usb1_pwr-pins {
				function = "usb1_pwr";
				groups = "usb1_pwr_grp";
			};
		};

		uart0: serial@640 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x640 0x18>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
			clock-names = "refclk";
			status = "okay";
		};

		leds: leds@800 {
			compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds";
			reg = <0x800 0xdc>;

			#address-cells = <1>;
			#size-cells = <0>;
		};

		nand-controller@1800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
			reg = <0x1800 0x600>, <0x2000 0x10>;
			reg-names = "nand", "nand-int-base";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "nand";
			status = "okay";

			nandcs: nand@0 {
				compatible = "brcm,nandcs";
				reg = <0>;
			};
		};

		i2c@2100 {
			compatible = "brcm,brcmper-i2c";
			reg = <0x2100 0x58>;
			clock-frequency = <97500>;
			pinctrl-names = "default";
			pinctrl-0 = <&pins_i2c_a>;
			status = "disabled";
		};

		misc@2600 {
			compatible = "brcm,misc", "simple-mfd";
			reg = <0x2600 0xe4>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x00 0x2600 0xe4>;

			reset-controller@2644 {
				compatible = "brcm,bcm4908-misc-pcie-reset";
				reg = <0x44 0x04>;
				#reset-cells = <1>;
			};
		};
	};

	reboot {
		compatible = "syscon-reboot";
		regmap = <&twd>;
		offset = <0x34>;
		mask = <1>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

/dts-v1/;

#include "bcm4912.dtsi"

/ {
	compatible = "asus,gt-ax6000", "brcm,bcm4912", "brcm,bcmbca";
	model = "Asus GT-AX6000";

	memory@0 {
		device_type = "memory";
		reg = <0x00 0x00 0x00 0x40000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "brcm,bcm4912", "brcm,bcmbca";
	#address-cells = <2>;
	#size-cells = <2>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		B53_0: cpu@0 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_1: cpu@1 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_2: cpu@2 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x2>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_3: cpu@3 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x3>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu: pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&B53_0>, <&B53_1>,
			<&B53_2>, <&B53_3>;
	};

	clocks: clocks {
		periph_clk: periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};
		uart_clk: uart-clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&periph_clk>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x81000000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
			reg = <0x1000 0x1000>,
				<0x2000 0x2000>,
				<0x4000 0x2000>,
				<0x6000 0x2000>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0xff800000 0x800000>;

		uart0: serial@12000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x12000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_clk>, <&uart_clk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "brcm,bcm63146", "brcm,bcmbca";
	#address-cells = <2>;
	#size-cells = <2>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		B53_0: cpu@0 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_1: cpu@1 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu: pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&B53_0>, <&B53_1>;
	};

	clocks: clocks {
		periph_clk: periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};
		uart_clk: uart-clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&periph_clk>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x81000000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x1000 0x1000>,
				<0x2000 0x2000>,
				<0x4000 0x2000>,
				<0x6000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
					IRQ_TYPE_LEVEL_HIGH)>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0xff800000 0x800000>;

		uart0: serial@12000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x12000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_clk>, <&uart_clk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "brcm,bcm63158", "brcm,bcmbca";
	#address-cells = <2>;
	#size-cells = <2>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		B53_0: cpu@0 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_1: cpu@1 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_2: cpu@2 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x2>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_3: cpu@3 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x3>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu: pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&B53_0>, <&B53_1>,
			<&B53_2>, <&B53_3>;
	};

	clocks: clocks {
		periph_clk: periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};
		uart_clk: uart-clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&periph_clk>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x81000000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
			reg = <0x1000 0x1000>,
				<0x2000 0x2000>,
				<0x4000 0x2000>,
				<0x6000 0x2000>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0xff800000 0x800000>;

		uart0: serial@12000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x12000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_clk>, <&uart_clk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "brcm,bcm6813", "brcm,bcmbca";
	#address-cells = <2>;
	#size-cells = <2>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		B53_0: cpu@0 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_1: cpu@1 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_2: cpu@2 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x2>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_3: cpu@3 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x3>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu: pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&B53_0>, <&B53_1>,
			<&B53_2>, <&B53_3>;
	};

	clocks: clocks {
		periph_clk: periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};
		uart_clk: uart-clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&periph_clk>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x81000000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
			reg = <0x1000 0x1000>,
				<0x2000 0x2000>,
				<0x4000 0x2000>,
				<0x6000 0x2000>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0xff800000 0x800000>;

		uart0: serial@12000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x12000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_clk>, <&uart_clk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "brcm,bcm6856", "brcm,bcmbca";
	#address-cells = <2>;
	#size-cells = <2>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		B53_0: cpu@0 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_1: cpu@1 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu: pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&B53_0>, <&B53_1>;
	};

	clocks: clocks {
		periph_clk:periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x81000000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x1000 0x1000>, /* GICD */
				<0x2000 0x2000>, /* GICC */
				<0x4000 0x2000>, /* GICH */
				<0x6000 0x2000>; /* GICV */
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
					IRQ_TYPE_LEVEL_HIGH)>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0xff800000 0x800000>;

		uart0: serial@640 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x640 0x18>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
			clock-names = "refclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "brcm,bcm6858", "brcm,bcmbca";
	#address-cells = <2>;
	#size-cells = <2>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		B53_0: cpu@0 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_1: cpu@1 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_2: cpu@2 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x2>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_3: cpu@3 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x3>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};
		L2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu: pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&B53_0>, <&B53_1>,
			<&B53_2>, <&B53_3>;
	};

	clocks: clocks {
		periph_clk:periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x81000000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x1000 0x1000>, /* GICD */
				<0x2000 0x2000>, /* GICC */
				<0x4000 0x2000>, /* GICH */
				<0x6000 0x2000>; /* GICV */
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
					IRQ_TYPE_LEVEL_HIGH)>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0xff800000 0x62000>;

		twd: timer-mfd@400 {
			compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
			reg = <0x400 0x4c>;
			ranges = <0x0 0x400 0x4c>;

			#address-cells = <1>;
			#size-cells = <1>;

			timer@0 {
				compatible = "brcm,bcm63138-timer";
				reg = <0x0 0x28>;
			};

			watchdog@28 {
				compatible = "brcm,bcm6345-wdt";
				reg = <0x28 0x8>;
			};
		};

		uart0: serial@640 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x640 0x18>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
			clock-names = "refclk";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm4908.dtsi"

/ {
	model = "Broadcom BCM94908 Reference Board";
	compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm4912.dtsi"

/ {
	model = "Broadcom BCM94912 Reference Board";
	compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm63146.dtsi"

/ {
	model = "Broadcom BCM963146 Reference Board";
	compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm63158.dtsi"

/ {
	model = "Broadcom BCM963158 Reference Board";
	compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm6813.dtsi"

/ {
	model = "Broadcom BCM96813 Reference Board";
	compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm6856.dtsi"

/ {
	model = "Broadcom BCM96856 Reference Board";
	compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm6858.dtsi"

/ {
	model = "Broadcom BCM96858 Reference Board";
	compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-xmc.dtb


code:
/*
 *  BSD LICENSE
 *
 *  Copyright (c) 2016 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/clock/bcm-ns2.h>

	osc: oscillator {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <25000000>;
	};

	lcpll_ddr: lcpll_ddr@6501d058 {
		#clock-cells = <1>;
		compatible = "brcm,ns2-lcpll-ddr";
		reg = <0x6501d058 0x20>,
		      <0x6501c020 0x4>,
		      <0x6501d04c 0x4>;
		clocks = <&osc>;
		clock-output-names = "lcpll_ddr", "pcie_sata_usb",
				     "ddr", "ddr_ch2_unused",
				     "ddr_ch3_unused", "ddr_ch4_unused",
				     "ddr_ch5_unused";
	};

	lcpll_ports: lcpll_ports@6501d078 {
		#clock-cells = <1>;
		compatible = "brcm,ns2-lcpll-ports";
		reg = <0x6501d078 0x20>,
		      <0x6501c020 0x4>,
		      <0x6501d054 0x4>;
		clocks = <&osc>;
		clock-output-names = "lcpll_ports", "wan", "rgmii",
				     "ports_ch2_unused",
				     "ports_ch3_unused",
				     "ports_ch4_unused",
				     "ports_ch5_unused";
	};

	genpll_scr: genpll_scr@6501d098 {
		#clock-cells = <1>;
		compatible = "brcm,ns2-genpll-scr";
		reg = <0x6501d098 0x32>,
		      <0x6501c020 0x4>,
		      <0x6501d044 0x4>;
		clocks = <&osc>;
		clock-output-names = "genpll_scr", "scr", "fs",
				     "audio_ref", "scr_ch3_unused",
				     "scr_ch4_unused", "scr_ch5_unused";
	};

	iprocmed: iprocmed {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
		clock-div = <2>;
		clock-mult = <1>;
	};

	iprocslow: iprocslow {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>;
		clock-div = <4>;
		clock-mult = <1>;
	};

	genpll_sw: genpll_sw@6501d0c4 {
		#clock-cells = <1>;
		compatible = "brcm,ns2-genpll-sw";
		reg = <0x6501d0c4 0x32>,
		      <0x6501c020 0x4>,
		      <0x6501d044 0x4>;
		clocks = <&osc>;
		clock-output-names = "genpll_sw", "rpe", "250", "nic",
				     "chimp", "port", "sdio";
	};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "ns2.dtsi"

/ {
	model = "Broadcom NS2 SVK";
	compatible = "brcm,ns2-svk", "brcm,ns2";

	aliases {
		serial0 = &uart3;
		serial1 = &uart0;
		serial2 = &uart1;
		serial3 = &uart2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs = "earlycon=uart8250,mmio32,0x66130000";
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
	};
};

&enet {
	status = "okay";
};

&pci_phy0 {
	status = "okay";
};

&pci_phy1 {
	status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie4 {
	status = "okay";
};

&pcie8 {
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&ssp0 {
	status = "okay";

	slic@0 {
		compatible = "silabs,si3226x";
		reg = <0>;
		spi-max-frequency = <5000000>;
		spi-cpha;
		spi-cpol;
		pl022,hierarchy = <0>;
		pl022,interface = <0>;
		pl022,slave-tx-disable = <0>;
		pl022,com-mode = <0>;
		pl022,rx-level-trig = <1>;
		pl022,tx-level-trig = <1>;
		pl022,ctrl-len = <11>;
		pl022,wait-state = <0>;
		pl022,duplex = <0>;
	};
};

&ssp1 {
	status = "okay";

	at25@0 {
		compatible = "atmel,at25";
		reg = <0>;
		spi-max-frequency = <5000000>;
		at25,byte-len = <0x8000>;
		at25,addr-mode = <2>;
		at25,page-size = <64>;
		spi-cpha;
		spi-cpol;
		pl022,hierarchy = <0>;
		pl022,interface = <0>;
		pl022,slave-tx-disable = <0>;
		pl022,com-mode = <0>;
		pl022,rx-level-trig = <1>;
		pl022,tx-level-trig = <1>;
		pl022,ctrl-len = <11>;
		pl022,wait-state = <0>;
		pl022,duplex = <0>;
	};
};

&sata_phy0 {
	status = "okay";
};

&sata_phy1 {
	status = "okay";
};

&sata {
	status = "okay";
};

&sdio0 {
	status = "okay";
};

&sdio1 {
	status = "okay";
};

&nand {
	nandcs@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-ecc-mode = "hw";
		nand-ecc-strength = <8>;
		nand-ecc-step-size = <512>;
		nand-bus-width = <16>;
		brcm,nand-oob-sector-size = <16>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

&mdio_mux_iproc {
	mdio@10 {
		gphy0: eth-phy@10 {
			enet-phy-lane-swap;
			reg = <0x10>;
		};
	};
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <&nand_sel>;
	nand_sel: nand_sel {
		function = "nand";
		groups = "nand_grp";
	};
};

&qspi {
	bspi-sel = <0>;
	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p80";
		reg = <0x0>;
		spi-max-frequency = <12500000>;
		m25p,fast-read;
		spi-cpol;
		spi-cpha;

		partition@0 {
			label = "boot";
			reg = <0x00000000 0x000a0000>;
		};

		partition@a0000 {
			label = "env";
			reg = <0x000a0000 0x00060000>;
		};

		partition@100000 {
			label = "system";
			reg = <0x00100000 0x00600000>;
		};

		partition@700000 {
			label = "rootfs";
			reg = <0x00700000 0x01900000>;
		};
	};
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2016 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "ns2.dtsi"

/ {
	model = "Broadcom NS2 XMC";
	compatible = "brcm,ns2-xmc", "brcm,ns2";

	aliases {
		serial0 = &uart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs = "earlycon=uart8250,mmio32,0x66130000";
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0x00000001 0x00000000>;
	};
};

&enet {
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";
};

&mdio_mux_iproc {
	mdio@10 {
		gphy0: eth-phy@10 {
			reg = <0x10>;
		};
	};
};

&nand {
	nandcs@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-ecc-mode = "hw";
		nand-ecc-strength = <8>;
		nand-ecc-step-size = <512>;
		nand-bus-width = <16>;
		brcm,nand-oob-sector-size = <16>;
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "nboot";
			reg = <0x00000000 0x00280000>; /*  2.5MB */
			read-only;
		};

		partition@280000 {
			label = "nenv";
			reg = <0x00280000 0x00040000>; /* 0.25MB */
			read-only;
		};

		partition@2c0000 {
			label = "ndtb";
			reg = <0x002c0000 0x00040000>; /* 0.25MB */
			read-only;
		};

		partition@300000 {
			label = "nsystem";
			reg = <0x00300000 0x03d00000>; /*   61MB */
			read-only;
		};

		partition@4000000 {
			label = "nrootfs";
			reg = <0x04000000 0x06400000>; /*  100MB */
		};

		partition@a400000{
			label = "ncustfs";
			reg = <0x0a400000 0x35c00000>; /*  860MB */
		};
	};
};

&pci_phy0 {
	status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie8 {
	status = "okay";
};

&sata_phy0 {
	status = "okay";
};

&sata_phy1 {
	status = "okay";
};

&sata {
	status = "okay";
};

&qspi {
	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p80";
		spi-max-frequency = <62500000>;
		m25p,default-addr-width = <3>;
		reg = <0x0 0x0>;

		partition@0 {
			label = "bl0";
			reg = <0x00000000 0x00080000>; /*  512KB */
		};

		partition@80000 {
			label = "fip";
			reg = <0x00080000 0x00150000>; /* 1344KB */
		};

		partition@1e0000 {
			label = "env";
			reg = <0x001e0000 0x00010000>;/*    64KB */
		};

		partition@1f0000 {
			label = "dtb";
			reg = <0x001f0000 0x00010000>; /*   64KB */
		};

		partition@200000 {
			label = "kernel";
			reg = <0x00200000 0x00e00000>; /*   14MB */
		};

		partition@1000000 {
			label = "rootfs";
			reg = <0x01000000 0x01000000>; /*   16MB */
		};
	};
};

&uart3 {
	status = "okay";
};