code:
SMSC LAN87xx Ethernet PHY

Some boards require special tuning values. Configure them
through an Ethernet OF device node.

Optional properties:

- clocks:
  The clock used as phy reference clock and is connected to phy
  pin XTAL1/CLKIN.

- smsc,disable-energy-detect:
  If set, do not enable energy detect mode for the SMSC phy.
  default: enable energy detect mode

Examples:
smsc phy with disabled energy detect mode on an am335x based board.
&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;

	ethernetphy0: ethernet-phy@0 {
		reg = <0>;
		smsc,disable-energy-detect;
	};
};


code:
* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)

This binding is deprecated, but it continues to be supported, but new
features should be preferably added to the stmmac binding document.

This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
IP block. The IP supports multiple options for bus type, clocking and reset
structure, and feature list. Consequently, a number of properties and list
entries in properties are marked as optional, or only required in specific HW
configurations.

Required properties:
- compatible: One of:
  - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
    Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
  - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
    Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
  - "snps,dwc-qos-ethernet-4.10"
    This combination is deprecated. It should be treated as equivalent to
    "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
    compatible with earlier revisions of this binding.
- reg: Address and length of the register set for the device
- clocks: Phandle and clock specifiers for each entry in clock-names, in the
  same order. See ../clock/clock-bindings.txt.
- clock-names: May contain any/all of the following depending on the IP
  configuration, in any order:
  - "tx"
    The EQOS transmit path clock. The HW signal name is clk_tx_i.
    In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
    path. In other configurations, other clocks (such as tx_125, rmii) may
    drive the PHY TX path.
  - "rx"
    The EQOS receive path clock. The HW signal name is clk_rx_i.
    In some configurations (e.g. GMII/RGMII), this clock is derived from the
    PHY's RX clock output. In other configurations, other clocks (such as
    rx_125, rmii) may drive the EQOS RX path.
    In cases where the PHY clock is directly fed into the EQOS receive path
    without intervening logic, the DT need not represent this clock, since it
    is assumed to be fully under the control of the PHY device/driver. In
    cases where SoC integration adds additional logic to this path, such as a
    SW-controlled clock gate, this clock should be represented in DT.
  - "slave_bus"
    The CPU/slave-bus (CSR) interface clock. This applies to any bus type;
    APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
    buses).
  - "master_bus"
    The master bus interface clock. Only required in configurations that use a
    separate clock for the master and slave bus interfaces. The HW signal name
    is hclk_i (AHB) or aclk_i (AXI).
  - "ptp_ref"
    The PTP reference clock. The HW signal name is clk_ptp_ref_i.
  - "phy_ref_clk"
    This clock is deprecated and should not be used by new compatible values.
    It is equivalent to "tx".
  - "apb_pclk"
    This clock is deprecated and should not be used by new compatible values.
    It is equivalent to "slave_bus".

  Note: Support for additional IP configurations may require adding the
  following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i,
  clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i.
  Configurations exist where multiple similar clocks are used at once, e.g. all
  of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to
  extend the binding with a separate clock-names entry for each of those RX
  clocks, rather than repurposing the existing "rx" clock-names entry as a
  generic/logical clock in a similar fashion to "master_bus" and "slave_bus".
  This will allow easy support for configurations that support multiple PHY
  interfaces using a mux, and hence need to have explicit control over
  specific RX clocks.

  The following compatible values require the following set of clocks:
  - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
    - "slave_bus"
    - "master_bus"
    - "rx"
    - "tx"
    - "ptp_ref"
  - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
    - "slave_bus"
    - "master_bus"
    - "tx"
    - "ptp_ref"
  - "snps,dwc-qos-ethernet-4.10" (deprecated):
    - "phy_ref_clk"
    - "apb_clk"
- interrupts: Should contain the core's combined interrupt signal
- phy-mode: See ethernet.txt file in the same directory
- resets: Phandle and reset specifiers for each entry in reset-names, in the
  same order. See ../reset/reset.txt.
- reset-names: May contain any/all of the following depending on the IP
  configuration, in any order:
  - "eqos". The reset to the entire module. The HW signal name is hreset_n
    (AHB) or aresetn_i (AXI).

  The following compatible values require the following set of resets:
  (the reset properties may be omitted if empty)
  - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
    - "eqos".
  - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
    - None.
  - "snps,dwc-qos-ethernet-4.10" (deprecated):
    - None.

Optional properties:
- dma-coherent: Present if dma operations are coherent
- phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY.
  See ../gpio/gpio.txt.
- snps,en-lpi: If present it enables use of the AXI low-power interface
- snps,write-requests: Number of write requests that the AXI port can issue.
  It depends on the SoC configuration.
- snps,read-requests: Number of read requests that the AXI port can issue.
  It depends on the SoC configuration.
- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB
  representing 4, then 8 etc.
- snps,txpbl: DMA Programmable burst length for the TX DMA
- snps,rxpbl: DMA Programmable burst length for the RX DMA
- snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
  TX low-power mode.
- phy-handle: See ethernet.txt file in the same directory
- mdio device tree subnode: When the GMAC has a phy connected to its local
    mdio, there must be device tree subnode with the following
    required properties:
    - compatible: Must be "snps,dwc-qos-ethernet-mdio".
    - #address-cells: Must be <1>.
    - #size-cells: Must be <0>.

    For each phy on the mdio bus, there must be a node with the following
    fields:

    - reg: phy id used to communicate to phy.
    - device_type: Must be "ethernet-phy".
    - fixed-mode device tree subnode: see fixed-link.txt in the same directory

The MAC address will be determined using the optional properties
defined in ethernet.txt.

Examples:
ethernet2@40010000 {
	clock-names = "phy_ref_clk", "apb_pclk";
	clocks = <&clkc 17>, <&clkc 15>;
	compatible = "snps,dwc-qos-ethernet-4.10";
	interrupt-parent = <&intc>;
	interrupts = <0x0 0x1e 0x4>;
	reg = <0x40010000 0x4000>;
	phy-handle = <&phy2>;
	phy-mode = "gmii";
	phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>;

	snps,en-tx-lpi-clockgating;
	snps,en-lpi;
	snps,write-requests = <2>;
	snps,read-requests = <16>;
	snps,burst-map = <0x7>;
	snps,txpbl = <8>;
	snps,rxpbl = <2>;

	dma-coherent;

	mdio {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		phy2: phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			device_type = "ethernet-phy";
			reg = <0x1>;
		};
	};
};

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare MAC

maintainers:
  - Alexandre Torgue <alexandre.torgue@foss.st.com>
  - Giuseppe Cavallaro <peppe.cavallaro@st.com>
  - Jose Abreu <joabreu@synopsys.com>

# Select every compatible, including the deprecated ones. This way, we
# will be able to report a warning when we have that compatible, since
# we will validate the node thanks to the select, but won't report it
# as a valid value in the compatible property description
select:
  properties:
    compatible:
      contains:
        enum:
          - snps,dwmac
          - snps,dwmac-3.40a
          - snps,dwmac-3.50a
          - snps,dwmac-3.610
          - snps,dwmac-3.70a
          - snps,dwmac-3.710
          - snps,dwmac-4.00
          - snps,dwmac-4.10a
          - snps,dwmac-4.20a
          - snps,dwmac-5.10a
          - snps,dwxgmac
          - snps,dwxgmac-2.10

          # Deprecated
          - st,spear600-gmac

  required:
    - compatible

properties:

  # We need to include all the compatibles from schemas that will
  # include that schemas, otherwise compatible won't validate for
  # those.
  compatible:
    contains:
      enum:
        - allwinner,sun7i-a20-gmac
        - allwinner,sun8i-a83t-emac
        - allwinner,sun8i-h3-emac
        - allwinner,sun8i-r40-gmac
        - allwinner,sun8i-v3s-emac
        - allwinner,sun50i-a64-emac
        - amlogic,meson6-dwmac
        - amlogic,meson8b-dwmac
        - amlogic,meson8m2-dwmac
        - amlogic,meson-gxbb-dwmac
        - amlogic,meson-axg-dwmac
        - ingenic,jz4775-mac
        - ingenic,x1000-mac
        - ingenic,x1600-mac
        - ingenic,x1830-mac
        - ingenic,x2000-mac
        - loongson,ls2k-dwmac
        - loongson,ls7a-dwmac
        - renesas,r9a06g032-gmac
        - renesas,rzn1-gmac
        - rockchip,px30-gmac
        - rockchip,rk3128-gmac
        - rockchip,rk3228-gmac
        - rockchip,rk3288-gmac
        - rockchip,rk3328-gmac
        - rockchip,rk3366-gmac
        - rockchip,rk3368-gmac
        - rockchip,rk3588-gmac
        - rockchip,rk3399-gmac
        - rockchip,rv1108-gmac
        - snps,dwmac
        - snps,dwmac-3.40a
        - snps,dwmac-3.50a
        - snps,dwmac-3.610
        - snps,dwmac-3.70a
        - snps,dwmac-3.710
        - snps,dwmac-4.00
        - snps,dwmac-4.10a
        - snps,dwmac-4.20a
        - snps,dwmac-5.10a
        - snps,dwxgmac
        - snps,dwxgmac-2.10

  reg:
    minItems: 1
    maxItems: 2

  interrupts:
    minItems: 1
    items:
      - description: Combined signal for various interrupt events
      - description: The interrupt to manage the remote wake-up packet detection
      - description: The interrupt that occurs when Rx exits the LPI state

  interrupt-names:
    minItems: 1
    items:
      - const: macirq
      - const: eth_wake_irq
      - const: eth_lpi

  clocks:
    minItems: 1
    maxItems: 8
    additionalItems: true
    items:
      - description: GMAC main clock
      - description: Peripheral registers interface clock
      - description:
          PTP reference clock. This clock is used for programming the
          Timestamp Addend Register. If not passed then the system
          clock will be used and this is fine on some platforms.

  clock-names:
    minItems: 1
    maxItems: 8
    additionalItems: true
    contains:
      enum:
        - stmmaceth
        - pclk
        - ptp_ref

  resets:
    maxItems: 1
    description:
      MAC Reset signal.

  reset-names:
    const: stmmaceth

  power-domains:
    maxItems: 1

  mac-mode:
    $ref: ethernet-controller.yaml#/properties/phy-connection-type
    description:
      The property is identical to 'phy-mode', and assumes that there is mode
      converter in-between the MAC & PHY (e.g. GMII-to-RGMII). This converter
      can be passive (no SW requirement), and requires that the MAC operate
      in a different mode than the PHY in order to function.

  snps,axi-config:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      AXI BUS Mode parameters. Phandle to a node that can contain the
      following properties
        * snps,lpi_en, enable Low Power Interface
        * snps,xit_frm, unlock on WoL
        * snps,wr_osr_lmt, max write outstanding req. limit
        * snps,rd_osr_lmt, max read outstanding req. limit
        * snps,kbbe, do not cross 1KiB boundary.
        * snps,blen, this is a vector of supported burst length.
        * snps,fb, fixed-burst
        * snps,mb, mixed-burst
        * snps,rb, rebuild INCRx Burst

  snps,mtl-rx-config:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Multiple RX Queues parameters. Phandle to a node that
      implements the 'rx-queues-config' object described in
      this binding.

  rx-queues-config:
    type: object
    properties:
      snps,rx-queues-to-use:
        $ref: /schemas/types.yaml#/definitions/uint32
        description: number of RX queues to be used in the driver
      snps,rx-sched-sp:
        type: boolean
        description: Strict priority
      snps,rx-sched-wsp:
        type: boolean
        description: Weighted Strict priority
    allOf:
      - if:
          required:
            - snps,rx-sched-sp
        then:
          properties:
            snps,rx-sched-wsp: false
      - if:
          required:
            - snps,rx-sched-wsp
        then:
          properties:
            snps,rx-sched-sp: false
    patternProperties:
      "^queue[0-9]$":
        description: Each subnode represents a queue.
        type: object
        properties:
          snps,dcb-algorithm:
            type: boolean
            description: Queue to be enabled as DCB
          snps,avb-algorithm:
            type: boolean
            description: Queue to be enabled as AVB
          snps,map-to-dma-channel:
            $ref: /schemas/types.yaml#/definitions/uint32
            description: DMA channel id to map
          snps,route-avcp:
            type: boolean
            description: AV Untagged Control packets
          snps,route-ptp:
            type: boolean
            description: PTP Packets
          snps,route-dcbcp:
            type: boolean
            description: DCB Control Packets
          snps,route-up:
            type: boolean
            description: Untagged Packets
          snps,route-multi-broad:
            type: boolean
            description: Multicast & Broadcast Packets
          snps,priority:
            $ref: /schemas/types.yaml#/definitions/uint32
            description: Bitmask of the tagged frames priorities assigned to the queue
        allOf:
          - if:
              required:
                - snps,dcb-algorithm
            then:
              properties:
                snps,avb-algorithm: false
          - if:
              required:
                - snps,avb-algorithm
            then:
              properties:
                snps,dcb-algorithm: false
          - if:
              required:
                - snps,route-avcp
            then:
              properties:
                snps,route-ptp: false
                snps,route-dcbcp: false
                snps,route-up: false
                snps,route-multi-broad: false
          - if:
              required:
                - snps,route-ptp
            then:
              properties:
                snps,route-avcp: false
                snps,route-dcbcp: false
                snps,route-up: false
                snps,route-multi-broad: false
          - if:
              required:
                - snps,route-dcbcp
            then:
              properties:
                snps,route-avcp: false
                snps,route-ptp: false
                snps,route-up: false
                snps,route-multi-broad: false
          - if:
              required:
                - snps,route-up
            then:
              properties:
                snps,route-avcp: false
                snps,route-ptp: false
                snps,route-dcbcp: false
                snps,route-multi-broad: false
          - if:
              required:
                - snps,route-multi-broad
            then:
              properties:
                snps,route-avcp: false
                snps,route-ptp: false
                snps,route-dcbcp: false
                snps,route-up: false
        additionalProperties: false
    additionalProperties: false

  snps,mtl-tx-config:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Multiple TX Queues parameters. Phandle to a node that
      implements the 'tx-queues-config' object described in
      this binding.

  tx-queues-config:
    type: object
    properties:
      snps,tx-queues-to-use:
        $ref: /schemas/types.yaml#/definitions/uint32
        description: number of TX queues to be used in the driver
      snps,tx-sched-wrr:
        type: boolean
        description: Weighted Round Robin
      snps,tx-sched-wfq:
        type: boolean
        description: Weighted Fair Queuing
      snps,tx-sched-dwrr:
        type: boolean
        description: Deficit Weighted Round Robin
      snps,tx-sched-sp:
        type: boolean
        description: Strict priority
    allOf:
      - if:
          required:
            - snps,tx-sched-wrr
        then:
          properties:
            snps,tx-sched-wfq: false
            snps,tx-sched-dwrr: false
            snps,tx-sched-sp: false
      - if:
          required:
            - snps,tx-sched-wfq
        then:
          properties:
            snps,tx-sched-wrr: false
            snps,tx-sched-dwrr: false
            snps,tx-sched-sp: false
      - if:
          required:
            - snps,tx-sched-dwrr
        then:
          properties:
            snps,tx-sched-wrr: false
            snps,tx-sched-wfq: false
            snps,tx-sched-sp: false
      - if:
          required:
            - snps,tx-sched-sp
        then:
          properties:
            snps,tx-sched-wrr: false
            snps,tx-sched-wfq: false
            snps,tx-sched-dwrr: false
    patternProperties:
      "^queue[0-9]$":
        description: Each subnode represents a queue.
        type: object
        properties:
          snps,weight:
            $ref: /schemas/types.yaml#/definitions/uint32
            description: TX queue weight (if using a DCB weight algorithm)
          snps,dcb-algorithm:
            type: boolean
            description: TX queue will be working in DCB
          snps,avb-algorithm:
            type: boolean
            description:
              TX queue will be working in AVB.
              Queue 0 is reserved for legacy traffic and so no AVB is
              available in this queue.
          snps,send_slope:
            $ref: /schemas/types.yaml#/definitions/uint32
            description: enable Low Power Interface
          snps,idle_slope:
            $ref: /schemas/types.yaml#/definitions/uint32
            description: unlock on WoL
          snps,high_credit:
            $ref: /schemas/types.yaml#/definitions/uint32
            description: max write outstanding req. limit
          snps,low_credit:
            $ref: /schemas/types.yaml#/definitions/uint32
            description: max read outstanding req. limit
          snps,priority:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              Bitmask of the tagged frames priorities assigned to the queue.
              When a PFC frame is received with priorities matching the bitmask,
              the queue is blocked from transmitting for the pause time specified
              in the PFC frame.
        allOf:
          - if:
              required:
                - snps,dcb-algorithm
            then:
              properties:
                snps,avb-algorithm: false
          - if:
              required:
                - snps,avb-algorithm
            then:
              properties:
                snps,dcb-algorithm: false
                snps,weight: false
        additionalProperties: false
    additionalProperties: false

  snps,reset-gpio:
    deprecated: true
    maxItems: 1
    description:
      PHY Reset GPIO

  snps,reset-active-low:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Indicates that the PHY Reset is active low

  snps,reset-delays-us:
    deprecated: true
    description:
      Triplet of delays. The 1st cell is reset pre-delay in micro
      seconds. The 2nd cell is reset pulse in micro seconds. The 3rd
      cell is reset post-delay in micro seconds.
    minItems: 3
    maxItems: 3

  snps,aal:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Use Address-Aligned Beats

  snps,fixed-burst:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Program the DMA to use the fixed burst mode

  snps,mixed-burst:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Program the DMA to use the mixed burst mode

  snps,force_thresh_dma_mode:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Force DMA to use the threshold mode for both tx and rx

  snps,force_sf_dma_mode:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Force DMA to use the Store and Forward mode for both tx and
      rx. This flag is ignored if force_thresh_dma_mode is set.

  snps,en-tx-lpi-clockgating:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Enable gating of the MAC TX clock during TX low-power mode

  snps,multicast-filter-bins:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Number of multicast filter hash bins supported by this device
      instance

  snps,perfect-filter-entries:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Number of perfect filter entries supported by this device
      instance

  snps,ps-speed:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Port selection speed that can be passed to the core when PCS
      is supported. For example, this is used in case of SGMII and
      MAC2MAC connection.

  snps,clk-csr:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Frequency division factor for MDC clock.

  mdio:
    $ref: mdio.yaml#
    unevaluatedProperties: false
    description:
      Creates and registers an MDIO bus.

    properties:
      compatible:
        const: snps,dwmac-mdio

    required:
      - compatible

  stmmac-axi-config:
    type: object
    unevaluatedProperties: false
    description:
      AXI BUS Mode parameters.

    properties:
      snps,lpi_en:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          enable Low Power Interface

      snps,xit_frm:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          unlock on WoL

      snps,wr_osr_lmt:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          max write outstanding req. limit

      snps,rd_osr_lmt:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          max read outstanding req. limit

      snps,kbbe:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          do not cross 1KiB boundary.

      snps,blen:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        description:
          this is a vector of supported burst length.
        minItems: 7
        maxItems: 7

      snps,fb:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          fixed-burst

      snps,mb:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          mixed-burst

      snps,rb:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          rebuild INCRx Burst

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - phy-mode

dependencies:
  snps,reset-active-low: ["snps,reset-gpio"]
  snps,reset-delay-us: ["snps,reset-gpio"]

allOf:
  - $ref: "ethernet-controller.yaml#"
  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun7i-a20-gmac
              - allwinner,sun8i-a83t-emac
              - allwinner,sun8i-h3-emac
              - allwinner,sun8i-r40-gmac
              - allwinner,sun8i-v3s-emac
              - allwinner,sun50i-a64-emac
              - ingenic,jz4775-mac
              - ingenic,x1000-mac
              - ingenic,x1600-mac
              - ingenic,x1830-mac
              - ingenic,x2000-mac
              - snps,dwmac-3.50a
              - snps,dwmac-4.10a
              - snps,dwmac-4.20a
              - snps,dwxgmac
              - snps,dwxgmac-2.10
              - st,spear600-gmac

    then:
      properties:
        snps,pbl:
          description:
            Programmable Burst Length (tx and rx)
          $ref: /schemas/types.yaml#/definitions/uint32
          enum: [1, 2, 4, 8, 16, 32]

        snps,txpbl:
          description:
            Tx Programmable Burst Length. If set, DMA tx will use this
            value rather than snps,pbl.
          $ref: /schemas/types.yaml#/definitions/uint32
          enum: [1, 2, 4, 8, 16, 32]

        snps,rxpbl:
          description:
            Rx Programmable Burst Length. If set, DMA rx will use this
            value rather than snps,pbl.
          $ref: /schemas/types.yaml#/definitions/uint32
          enum: [1, 2, 4, 8, 16, 32]

        snps,no-pbl-x8:
          $ref: /schemas/types.yaml#/definitions/flag
          description:
            Don\'t multiply the pbl/txpbl/rxpbl values by 8. For core
            rev < 3.50, don\'t multiply the values by 4.

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun7i-a20-gmac
              - allwinner,sun8i-a83t-emac
              - allwinner,sun8i-h3-emac
              - allwinner,sun8i-r40-gmac
              - allwinner,sun8i-v3s-emac
              - allwinner,sun50i-a64-emac
              - loongson,ls2k-dwmac
              - loongson,ls7a-dwmac
              - ingenic,jz4775-mac
              - ingenic,x1000-mac
              - ingenic,x1600-mac
              - ingenic,x1830-mac
              - ingenic,x2000-mac
              - snps,dwmac-4.00
              - snps,dwmac-4.10a
              - snps,dwmac-4.20a
              - snps,dwmac-5.10a
              - snps,dwxgmac
              - snps,dwxgmac-2.10
              - st,spear600-gmac

    then:
      properties:
        snps,tso:
          $ref: /schemas/types.yaml#/definitions/flag
          description:
            Enables the TSO feature otherwise it will be managed by
            MAC HW capability register.

additionalProperties: true

examples:
  - |
    gmac0: ethernet@e0800000 {
        compatible = "snps,dwxgmac-2.10", "snps,dwxgmac";
        reg = <0xe0800000 0x8000>;
        interrupt-parent = <&vic1>;
        interrupts = <24 23 22>;
        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
        mac-address = [000000000000]; /* Filled in by U-Boot */
        max-frame-size = <3800>;
        phy-mode = "gmii";
        snps,multicast-filter-bins = <256>;
        snps,perfect-filter-entries = <128>;
        rx-fifo-depth = <16384>;
        tx-fifo-depth = <16384>;
        clocks = <&clock>;
        clock-names = "stmmaceth";
        snps,axi-config = <&stmmac_axi_setup>;
        snps,mtl-rx-config = <&mtl_rx_setup>;
        snps,mtl-tx-config = <&mtl_tx_setup>;

        stmmac_axi_setup: stmmac-axi-config {
            snps,wr_osr_lmt = <0xf>;
            snps,rd_osr_lmt = <0xf>;
            snps,blen = <256 128 64 32 0 0 0>;
        };

        mtl_rx_setup: rx-queues-config {
            snps,rx-queues-to-use = <1>;
            snps,rx-sched-sp;
            queue0 {
                snps,dcb-algorithm;
                snps,map-to-dma-channel = <0x0>;
                snps,priority = <0x0>;
            };
        };

        mtl_tx_setup: tx-queues-config {
            snps,tx-queues-to-use = <2>;
            snps,tx-sched-wrr;
            queue0 {
                snps,weight = <0x10>;
                snps,dcb-algorithm;
                snps,priority = <0x0>;
            };

            queue1 {
                snps,avb-algorithm;
                snps,send_slope = <0x1000>;
                snps,idle_slope = <0x1000>;
                snps,high_credit = <0x3E800>;
                snps,low_credit = <0xFFC18000>;
                snps,priority = <0x1>;
            };
        };

        mdio0 {
            #address-cells = <1>;
            #size-cells = <0>;
            compatible = "snps,dwmac-mdio";
            phy1: ethernet-phy@0 {
                reg = <0>;
            };
        };
    };

# FIXME: We should set it, but it would report all the generic
# properties as additional properties.
# additionalProperties: false

...


code:
Altera SOCFPGA SoC DWMAC controller

This is a variant of the dwmac/stmmac driver an inherits all descriptions
present in Documentation/devicetree/bindings/net/stmmac.txt.

The device node has additional properties:

Required properties:
 - compatible	: For Cyclone5/Arria5 SoCs it should contain
		  "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
		  "altr,socfpga-stmmac-a10-s10".
		  Along with "snps,dwmac" and any applicable more detailed
		  designware version numbers documented in stmmac.txt
 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
   encompasses the glue register, the register offset, and the register shift.
   On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
   on the Arria10/Stratix10/Agilex platforms, the register shift represents
   bit for each emac to enable/disable signals from the FPGA fabric to the
   EMAC modules.
 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
   for ptp ref clk. This affects all emacs as the clock is common.

Optional properties:
altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
		DWMAC controller is connected emac splitter.
phy-mode: The phy mode the ethernet operates in
altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter

This device node has additional phandle dependency, the sgmii converter:

Required properties:
 - compatible	: Should be altr,gmii-to-sgmii-2.0
 - reg-names	: Should be "eth_tse_control_port"

Example:

gmii_to_sgmii_converter: phy@100000240 {
	compatible = "altr,gmii-to-sgmii-2.0";
	reg = <0x00000001 0x00000240 0x00000008>,
		<0x00000001 0x00000200 0x00000040>;
	reg-names = "eth_tse_control_port";
	clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;
	clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
};

gmac0: ethernet@ff700000 {
	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
	altr,sysmgr-syscon = <&sysmgr 0x60 0>;
	reg = <0xff700000 0x2000>;
	interrupts = <0 115 4>;
	interrupt-names = "macirq";
	mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
	clocks = <&emac_0_clk>;
	clock-names = "stmmaceth";
	phy-mode = "sgmii";
	altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/socionext,synquacer-netsec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext NetSec Ethernet Controller IP

maintainers:
  - Jassi Brar <jaswinder.singh@linaro.org>
  - Ilias Apalodimas <ilias.apalodimas@linaro.org>

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    const: socionext,synquacer-netsec

  reg:
    items:
      - description: control register area
      - description: EEPROM holding the MAC address and microengine firmware

  clocks:
    maxItems: 1

  clock-names:
    const: phy_ref_clk

  dma-coherent: true

  interrupts:
    maxItems: 1

  mdio:
    $ref: mdio.yaml#

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts
  - mdio

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    ethernet@522d0000 {
        compatible = "socionext,synquacer-netsec";
        reg = <0x522d0000 0x10000>, <0x10000000 0x10000>;
        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk_netsec>;
        clock-names = "phy_ref_clk";
        phy-mode = "rgmii";
        max-speed = <1000>;
        max-frame-size = <9000>;
        phy-handle = <&phy1>;

        mdio {
            #address-cells = <1>;
            #size-cells = <0>;
            phy1: ethernet-phy@1 {
                compatible = "ethernet-phy-ieee802.3-c22";
                reg = <1>;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/socionext,uniphier-ave4.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext AVE ethernet controller

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

description: |
  This describes the devicetree bindings for AVE ethernet controller
  implemented on Socionext UniPhier SoCs.

properties:
  compatible:
    enum:
      - socionext,uniphier-pro4-ave4
      - socionext,uniphier-pxs2-ave4
      - socionext,uniphier-ld11-ave4
      - socionext,uniphier-ld20-ave4
      - socionext,uniphier-pxs3-ave4
      - socionext,uniphier-nx1-ave4

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  phy-mode: true

  phy-handle: true

  mac-address: true

  local-mac-address: true

  clocks:
    minItems: 1
    maxItems: 4

  clock-names: true

  resets:
    minItems: 1
    maxItems: 2

  reset-names: true

  socionext,syscon-phy-mode:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to syscon that configures phy mode
          - description: ID of MAC instance
    description:
      A phandle to syscon with one argument that configures phy mode.
      The argument is the ID of MAC instance.

  mdio:
    $ref: mdio.yaml#
    unevaluatedProperties: false

allOf:
  - $ref: ethernet-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: socionext,uniphier-pro4-ave4
    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4
        clock-names:
          items:
            - const: gio
            - const: ether
            - const: ether-gb
            - const: ether-phy
        resets:
          minItems: 2
          maxItems: 2
        reset-names:
          items:
            - const: gio
            - const: ether
    else:
      properties:
        clocks:
          maxItems: 1
        clock-names:
          const: ether
        resets:
          maxItems: 1
        reset-names:
          const: ether

required:
  - compatible
  - reg
  - interrupts
  - phy-mode
  - phy-handle
  - clocks
  - clock-names
  - resets
  - reset-names
  - mdio

unevaluatedProperties: false

examples:
  - |
    ether: ethernet@65000000 {
        compatible = "socionext,uniphier-ld20-ave4";
                reg = <0x65000000 0x8500>;
                interrupts = <0 66 4>;
                phy-mode = "rgmii";
                phy-handle = <&ethphy>;
                clock-names = "ether";
                clocks = <&sys_clk 6>;
                reset-names = "ether";
                resets = <&sys_rst 6>;
                socionext,syscon-phy-mode = <&soc_glue 0>;

                mdio {
                        #address-cells = <1>;
                        #size-cells = <0>;

                        ethphy: ethernet-phy@1 {
                                reg = <1>;
                        };
                };
        };


code:
STMicroelectronics SoC DWMAC glue layer controller

This file documents differences between the core properties in
Documentation/devicetree/bindings/net/stmmac.txt
and what is needed on STi platforms to program the stmmac glue logic.

The device node has following properties.

Required properties:
 - compatible	: Can be "st,stih415-dwmac", "st,stih416-dwmac",
   "st,stih407-dwmac", "st,stid127-dwmac".
 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
   encompases the glue register, and the offset of the control register.
 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
   register available on STiH407 SoC.
 - pinctrl-0: pin-control for all the MII mode supported.

Optional properties:
 - resets : phandle pointing to the system reset controller with correct
   reset line index for ethernet reset.
 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
   MAC can generate it.
 - st,tx-retime-src: This specifies which clk is wired up to the mac for
   retimeing tx lines. This is totally board dependent and can take one of the
   posssible values from "txclk", "clk_125" or "clkgen".
   If not passed, the internal clock will be used by default.
 - sti-ethclk: this is the phy clock.
 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
   to program the clk retiming.
 - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g.
   STiH407.

Example:

ethernet0: dwmac@9630000 {
	device_type = "network";
	compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
	reg = <0x9630000 0x8000>;
	reg-names = "stmmaceth";

	st,syscon = <&syscfg_sbc_reg 0x80>;
	st,gmac_en;
	resets = <&softreset STIH407_ETH1_SOFTRESET>;
	reset-names = "stmmaceth";

	interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
		     <GIC_SPI 99 IRQ_TYPE_NONE>,
		     <GIC_SPI 100 IRQ_TYPE_NONE>;
	interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";

	snps,pbl = <32>;
	snps,mixed-burst;

	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rgmii1>;

	clock-names = "stmmaceth", "sti-ethclk";
	clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>,
		 <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/stm32-dwmac.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: STMicroelectronics STM32 / MCU DWMAC glue layer controller

maintainers:
  - Alexandre Torgue <alexandre.torgue@foss.st.com>
  - Christophe Roullier <christophe.roullier@foss.st.com>

description:
  This file documents platform glue layer for stmmac.

# We need a select here so we don't match all nodes with 'snps,dwmac'
select:
  properties:
    compatible:
      contains:
        enum:
          - st,stm32-dwmac
          - st,stm32mp1-dwmac
  required:
    - compatible

allOf:
  - $ref: "snps,dwmac.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - st,stm32mp1-dwmac
          - const: snps,dwmac-4.20a
      - items:
          - enum:
              - st,stm32-dwmac
          - const: snps,dwmac-4.10a
      - items:
          - enum:
              - st,stm32-dwmac
          - const: snps,dwmac-3.50a

  reg: true

  reg-names:
    items:
      - const: stmmaceth

  clocks:
    minItems: 3
    items:
      - description: GMAC main clock
      - description: MAC TX clock
      - description: MAC RX clock
      - description: For MPU family, used for power mode
      - description: For MPU family, used for PHY without quartz
      - description: PTP clock

  clock-names:
    minItems: 3
    maxItems: 6
    contains:
      enum:
        - stmmaceth
        - mac-clk-tx
        - mac-clk-rx
        - ethstp
        - eth-ck
        - ptp_ref

  st,syscon:
    $ref: "/schemas/types.yaml#/definitions/phandle-array"
    items:
      - items:
          - description: phandle to the syscon node which encompases the glue register
          - description: offset of the control register
    description:
      Should be phandle/offset pair. The phandle to the syscon node which
      encompases the glue register, and the offset of the control register

  st,eth-clk-sel:
    description:
      set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
    type: boolean

  st,eth-ref-clk-sel:
    description:
      set this property in RMII mode when you have PHY without crystal 50MHz and want to
      select RCC clock instead of ETH_REF_CLK.
    type: boolean

required:
  - compatible
  - clocks
  - clock-names
  - st,syscon

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    #include <dt-bindings/mfd/stm32h7-rcc.h>
    //Example 1
     ethernet0: ethernet@5800a000 {
           compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
           reg = <0x5800a000 0x2000>;
           reg-names = "stmmaceth";
           interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
           interrupt-names = "macirq";
           clock-names = "stmmaceth",
                     "mac-clk-tx",
                     "mac-clk-rx",
                     "ethstp",
                     "eth-ck";
           clocks = <&rcc ETHMAC>,
                <&rcc ETHTX>,
                <&rcc ETHRX>,
                <&rcc ETHSTP>,
                <&rcc ETHCK_K>;
           st,syscon = <&syscfg 0x4>;
           snps,pbl = <2>;
           snps,axi-config = <&stmmac_axi_config_0>;
           snps,tso;
           phy-mode = "rgmii";
       };

  - |
    //Example 2 (MCU example)
     ethernet1: ethernet@40028000 {
           compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
           reg = <0x40028000 0x8000>;
           reg-names = "stmmaceth";
           interrupts = <0 61 0>, <0 62 0>;
           interrupt-names = "macirq", "eth_wake_irq";
           clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
           clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
           st,syscon = <&syscfg 0x4>;
           snps,pbl = <8>;
           snps,mixed-burst;
           phy-mode = "mii";
       };

  - |
    //Example 3
     ethernet2: ethernet@40027000 {
           compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
           reg = <0x40028000 0x8000>;
           reg-names = "stmmaceth";
           interrupts = <61>;
           interrupt-names = "macirq";
           clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
           clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
           st,syscon = <&syscfg 0x4>;
           snps,pbl = <8>;
           phy-mode = "mii";
       };


code: This file has moved to snps,dwmac.yaml.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/sunplus,sp7021-emac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sunplus SP7021 Dual Ethernet MAC

maintainers:
  - Wells Lu <wellslutw@gmail.com>

description: |
  Sunplus SP7021 dual 10M/100M Ethernet MAC controller.
  Device node of the controller has following properties.

properties:
  compatible:
    const: sunplus,sp7021-emac

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  ethernet-ports:
    type: object
    additionalProperties: false
    description: Ethernet ports to PHY

    properties:
      "#address-cells":
        const: 1

      "#size-cells":
        const: 0

    patternProperties:
      "^port@[0-1]$":
        type: object
        additionalProperties: false
        description: Port to PHY

        properties:
          reg:
            minimum: 0
            maximum: 1

          phy-handle:
            maxItems: 1

          phy-mode:
            maxItems: 1

          nvmem-cells:
            items:
              - description: nvmem cell address of MAC address

          nvmem-cell-names:
            description: names corresponding to the nvmem cells
            items:
              - const: mac-address

        required:
          - reg
          - phy-handle
          - phy-mode
          - nvmem-cells
          - nvmem-cell-names

  mdio:
    $ref: mdio.yaml#
    unevaluatedProperties: false

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - resets
  - pinctrl-0
  - pinctrl-names
  - ethernet-ports
  - mdio

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    ethernet@9c108000 {
        compatible = "sunplus,sp7021-emac";
        reg = <0x9c108000 0x400>;
        interrupt-parent = <&intc>;
        interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clkc 0xa7>;
        resets = <&rstc 0x97>;
        pinctrl-0 = <&emac_demo_board_v3_pins>;
        pinctrl-names = "default";

        ethernet-ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                phy-handle = <&eth_phy0>;
                phy-mode = "rmii";
                nvmem-cells = <&mac_addr0>;
                nvmem-cell-names = "mac-address";
            };

            port@1 {
                reg = <1>;
                phy-handle = <&eth_phy1>;
                phy-mode = "rmii";
                nvmem-cells = <&mac_addr1>;
                nvmem-cell-names = "mac-address";
            };
        };

        mdio {
            #address-cells = <1>;
            #size-cells = <0>;

            eth_phy0: ethernet-phy@0 {
                reg = <0>;
            };

            eth_phy1: ethernet-phy@1 {
                reg = <1>;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ti,bluetooth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments Bluetooth Chips

maintainers:
  - David Lechner <david@lechnology.com>

description: |
  This documents the binding structure and common properties for serial
  attached TI Bluetooth devices. The following chips are included in this
  binding:

  * TI CC256x Bluetooth devices
  * TI WiLink 7/8 (wl12xx/wl18xx) Shared Transport BT/FM/GPS devices

  TI WiLink devices have a UART interface for providing Bluetooth, FM radio,
  and GPS over what's called "shared transport". The shared transport is
  standard BT HCI protocol with additional channels for the other functions.

  TI WiLink devices also have a separate WiFi interface as described in
  wireless/ti,wlcore.yaml.

  This bindings follows the UART slave device binding in ../serial/serial.yaml.

properties:
  compatible:
    enum:
      - ti,cc2560
      - ti,wl1271-st
      - ti,wl1273-st
      - ti,wl1281-st
      - ti,wl1283-st
      - ti,wl1285-st
      - ti,wl1801-st
      - ti,wl1805-st
      - ti,wl1807-st
      - ti,wl1831-st
      - ti,wl1835-st
      - ti,wl1837-st

  enable-gpios:
    maxItems: 1

  vio-supply:
    description: Vio input supply (1.8V)

  vbat-supply:
    description: Vbat input supply (2.9-4.8V)

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: ext_clock

  max-speed:
    default: 3000000

  nvmem-cells:
    maxItems: 1
    description:
      Nvmem data cell that contains a 6 byte BD address with the most
      significant byte first (big-endian).

  nvmem-cell-names:
    items:
      - const: bd-address

required:
  - compatible

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    serial {
            bluetooth {
                    compatible = "ti,wl1835-st";
                    enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                    clocks = <&clk32k_wl18xx>;
                    clock-names = "ext_clock";
                    nvmem-cells = <&bd_address>;
                    nvmem-cell-names = "bd-address";
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI SoC Ethernet Switch Controller (CPSW)

maintainers:
  - Grygorii Strashko <grygorii.strashko@ti.com>
  - Sekhar Nori <nsekhar@ti.com>

description:
  The 3-port switch gigabit ethernet subsystem provides ethernet packet
  communication and can be configured as an ethernet switch. It provides the
  gigabit media independent interface (GMII),reduced gigabit media
  independent interface (RGMII), reduced media independent interface (RMII),
  the management data input output (MDIO) for physical layer device (PHY)
  management.

properties:
  compatible:
    oneOf:
      - const: ti,cpsw-switch
      - items:
          - const: ti,am335x-cpsw-switch
          - const: ti,cpsw-switch
      - items:
          - const: ti,am4372-cpsw-switch
          - const: ti,cpsw-switch
      - items:
          - const: ti,dra7-cpsw-switch
          - const: ti,cpsw-switch

  reg:
    maxItems: 1
    description:
      The physical base address and size of full the CPSW module IO range

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  ranges: true

  clocks:
    maxItems: 1
    description: CPSW functional clock

  clock-names:
    items:
      - const: fck

  interrupts:
    items:
      - description: RX_THRESH interrupt
      - description: RX interrupt
      - description: TX interrupt
      - description: MISC interrupt

  interrupt-names:
    items:
      - const: "rx_thresh"
      - const: "rx"
      - const: "tx"
      - const: "misc"

  pinctrl-names: true

  syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the system control device node which provides access to
      efuse IO range with MAC addresses

  ethernet-ports:
    type: object
    additionalProperties: false

    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    patternProperties:
      "^port@[0-9]+$":
        type: object
        description: CPSW external ports

        $ref: ethernet-controller.yaml#
        unevaluatedProperties: false

        properties:
          reg:
            items:
              - enum: [1, 2]
            description: CPSW port number

          phys:
            maxItems: 1
            description: phandle on phy-gmii-sel PHY

          label:
            description: label associated with this port

          ti,dual-emac-pvid:
            $ref: /schemas/types.yaml#/definitions/uint32
            minimum: 1
            maximum: 1024
            description:
              Specifies default PORT VID to be used to segregate
              ports. Default value - CPSW port number.

        required:
          - reg
          - phys

  cpts:
    type: object
    unevaluatedProperties: false
    description:
      The Common Platform Time Sync (CPTS) module

    properties:
      clocks:
        maxItems: 1
        description: CPTS reference clock

      clock-names:
        items:
          - const: cpts

      cpts_clock_mult:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Numerator to convert input clock ticks into ns

      cpts_clock_shift:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Denominator to convert input clock ticks into ns.
          Mult and shift will be calculated basing on CPTS rftclk frequency if
          both cpts_clock_shift and cpts_clock_mult properties are not provided.

    required:
      - clocks
      - clock-names

patternProperties:
  "^mdio@":
    type: object
    description:
      CPSW MDIO bus.
    $ref: "ti,davinci-mdio.yaml#"

required:
  - compatible
  - reg
  - ranges
  - clocks
  - clock-names
  - interrupts
  - interrupt-names
  - '#address-cells'
  - '#size-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/dra7.h>

    mac_sw: switch@0 {
        compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
        reg = <0x0 0x4000>;
        ranges = <0 0 0x4000>;
        clocks = <&gmac_main_clk>;
        clock-names = "fck";
        #address-cells = <1>;
        #size-cells = <1>;
        syscon = <&scm_conf>;

        interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "rx_thresh", "rx", "tx", "misc";

        ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                cpsw_port1: port@1 {
                        reg = <1>;
                        label = "port1";
                        mac-address = [ 00 00 00 00 00 00 ];
                        phys = <&phy_gmii_sel 1>;
                        phy-handle = <&ethphy0_sw>;
                        phy-mode = "rgmii";
                        ti,dual-emac-pvid = <1>;
                };

                cpsw_port2: port@2 {
                        reg = <2>;
                        label = "wan";
                        mac-address = [ 00 00 00 00 00 00 ];
                        phys = <&phy_gmii_sel 2>;
                        phy-handle = <&ethphy1_sw>;
                        phy-mode = "rgmii";
                        ti,dual-emac-pvid = <2>;
                };
        };

        davinci_mdio_sw: mdio@1000 {
                compatible = "ti,cpsw-mdio","ti,davinci_mdio";
                reg = <0x1000 0x100>;
                clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
                clock-names = "fck";
                #address-cells = <1>;
                #size-cells = <0>;
                bus_freq = <1000000>;

                ethphy0_sw: ethernet-phy@0 {
                        reg = <0>;
                };

                ethphy1_sw: ethernet-phy@1 {
                        reg = <1>;
                };
        };

        cpts {
                clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
                clock-names = "cpts";
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ti,davinci-mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI SoC Davinci/Keystone2 MDIO Controller

maintainers:
  - Grygorii Strashko <grygorii.strashko@ti.com>

description:
  TI SoC Davinci/Keystone2 MDIO Controller

allOf:
  - $ref: "mdio.yaml#"

properties:
  compatible:
    oneOf:
      - const: ti,davinci_mdio
      - items:
          - const: ti,keystone_mdio
          - const: ti,davinci_mdio
      - items:
          - const: ti,cpsw-mdio
          - const: ti,davinci_mdio
      - items:
          - const: ti,am4372-mdio
          - const: ti,cpsw-mdio
          - const: ti,davinci_mdio

  reg:
    maxItems: 1

  bus_freq:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 2500000
    description: MDIO Bus frequency

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: fck

  ti,hwmods:
    description: TI hwmod name
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/string-array
    items:
      const: davinci_mdio

if:
  properties:
    compatible:
      contains:
        const: ti,davinci_mdio
then:
  required:
    - bus_freq

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"

unevaluatedProperties: false

examples:
  - |
    davinci_mdio: mdio@4a101000 {
         compatible = "ti,davinci_mdio";
         #address-cells = <1>;
         #size-cells = <0>;
         reg = <0x4a101000 0x1000>;
         bus_freq = <1000000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
# Copyright (C) 2020 Texas Instruments Incorporated
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/ti,dp83822.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: TI DP83822 ethernet PHY

maintainers:
  - Andrew Davis <afd@ti.com>

description: |
  The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
  provides all of the physical layer functions needed to transmit and receive
  data over standard, twisted-pair cables or to connect to an external,
  fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
  connect to a MAC through a standard MII, RMII, or RGMII interface

  Specifications about the Ethernet PHY can be found at:
    http://www.ti.com/lit/ds/symlink/dp83822i.pdf

allOf:
  - $ref: "ethernet-phy.yaml#"

properties:
  reg:
    maxItems: 1

  ti,link-loss-low:
    type: boolean
    description: |
       DP83822 PHY in Fiber mode only.
       Sets the DP83822 to detect a link drop condition when the signal goes
       high.  If not set then link drop will occur when the signal goes low.
       This property is only applicable if the fiber mode support is strapped
       to on.

  ti,fiber-mode:
    type: boolean
    description: |
       DP83822 PHY only.
       If present the DP83822 PHY is configured to operate in fiber mode
       Fiber mode support can also be strapped. If the strap pin is not set
       correctly or not set at all then this boolean can be used to enable it.
       If the fiber mode is not strapped then signal detection for the PHY
       is disabled.
       In fiber mode, auto-negotiation is disabled and the PHY can only work in
       100base-fx (full and half duplex) modes.

  rx-internal-delay-ps:
    description: |
       DP83822 PHY only.
       Setting this property to a non-zero number sets the RX internal delay
       for the PHY.  The internal delay for the PHY is fixed to 3.5ns relative
       to receive data.

  tx-internal-delay-ps:
    description: |
       DP83822 PHY only.
       Setting this property to a non-zero number sets the TX internal delay
       for the PHY.  The internal delay for the PHY is fixed to 3.5ns relative
       to transmit data.

required:
  - reg

unevaluatedProperties: false

examples:
  - |
    mdio0 {
      #address-cells = <1>;
      #size-cells = <0>;
      ethphy0: ethernet-phy@0 {
        reg = <0>;
        rx-internal-delay-ps = <1>;
        tx-internal-delay-ps = <1>;
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
# Copyright (C) 2019 Texas Instruments Incorporated
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/ti,dp83867.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: TI DP83867 ethernet PHY

allOf:
  - $ref: "ethernet-controller.yaml#"

maintainers:
  - Andrew Davis <afd@ti.com>

description: |
  The DP83867 device is a robust, low power, fully featured Physical Layer
  transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
  and 1000BASE-T Ethernet protocols.

  The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet
  LANs. It interfaces directly to twisted pair media via an external
  transformer. This device interfaces directly to the MAC layer through the
  IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit
  Media Independent Interface (GMII) or Reduced GMII (RGMII).

  Specifications about the Ethernet PHY can be found at:
    https://www.ti.com/lit/gpn/dp83867ir

properties:
  reg:
    maxItems: 1

  nvmem-cells:
    maxItems: 1
    description:
      Nvmem data cell containing the value to write to the
      IO_IMPEDANCE_CTRL field of the IO_MUX_CFG register.

  nvmem-cell-names:
    items:
      - const: io_impedance_ctrl

  ti,min-output-impedance:
    type: boolean
    description: |
       MAC Interface Impedance control to set the programmable output impedance
       to a minimum value (35 ohms).

  ti,max-output-impedance:
    type: boolean
    description: |
      MAC Interface Impedance control to set the programmable output impedance
      to a maximum value (70 ohms).
      Note: Specifying an io_impedance_ctrl nvmem cell or one of the
        ti,min-output-impedance, ti,max-output-impedance properties
        are mutually exclusive. If more than one is present, an nvmem
        cell takes precedence over ti,max-output-impedance, which in
        turn takes precedence over ti,min-output-impedance.

  tx-fifo-depth:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
       Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values

  rx-fifo-depth:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
       Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values

  ti,clk-output-sel:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Muxing option for CLK_OUT pin.  See dt-bindings/net/ti-dp83867.h
      for applicable values. The CLK_OUT pin can also be disabled by this
      property.  When omitted, the PHY's default will be left as is.

  ti,rx-internal-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
      for applicable values. Required only if interface type is
      PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID.

  ti,tx-internal-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
      for applicable values. Required only if interface type is
      PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID.

        Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock
          delays will be left at their default values, as set by the PHY's pin
          strapping. The default strapping will use a delay of 2.00 ns.  Thus
          PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
          internal delay, but as PHY_INTERFACE_MODE_RGMII_ID.  The device tree
          should use "rgmii-id" if internal delays are desired as this may be
          changed in future to cause "rgmii" mode to disable delays.

  ti,dp83867-rxctrl-strap-quirk:
    type: boolean
    description: |
      This denotes the fact that the board has RX_DV/RX_CTRL pin strapped in
      mode 1 or 2. To ensure PHY operation, there are specific actions that
      software needs to take when this pin is strapped in these modes.
      See data manual for details.

  ti,sgmii-ref-clock-output-enable:
    type: boolean
    description: |
      This denotes which SGMII configuration is used (4 or 6-wire modes).
      Some MACs work with differential SGMII clock. See data manual for details.

  ti,fifo-depth:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable
      values.

required:
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/net/ti-dp83867.h>
    mdio0 {
      #address-cells = <1>;
      #size-cells = <0>;
      ethphy0: ethernet-phy@0 {
        reg = <0>;
        tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
        rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
        ti,max-output-impedance;
        ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>;
        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
# Copyright (C) 2019 Texas Instruments Incorporated
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/ti,dp83869.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: TI DP83869 ethernet PHY

allOf:
  - $ref: "ethernet-phy.yaml#"

maintainers:
  - Andrew Davis <afd@ti.com>

description: |
  The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
  with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
  1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
  100BASE-FX Fiber protocols.
  This device interfaces to the MAC layer through Reduced GMII (RGMII) and
  SGMII The DP83869HM supports Media Conversion in Managed mode. In this mode,
  the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
  conversions.  The DP83869HM can also support Bridge Conversion from RGMII to
  SGMII and SGMII to RGMII.

  Specifications about the Ethernet PHY can be found at:
    http://www.ti.com/lit/ds/symlink/dp83869hm.pdf

properties:
  reg:
    maxItems: 1

  ti,min-output-impedance:
    type: boolean
    description: |
       MAC Interface Impedance control to set the programmable output impedance
       to a minimum value (35 ohms).

  ti,max-output-impedance:
    type: boolean
    description: |
       MAC Interface Impedance control to set the programmable output impedance
       to a maximum value (70 ohms).

  tx-fifo-depth:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
       Transmitt FIFO depth see dt-bindings/net/ti-dp83869.h for values

  rx-fifo-depth:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
       Receive FIFO depth see dt-bindings/net/ti-dp83869.h for values

  ti,clk-output-sel:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
       Muxing option for CLK_OUT pin see dt-bindings/net/ti-dp83869.h for values.

  ti,op-mode:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
       Operational mode for the PHY.  If this is not set then the operational
       mode is set by the straps. see dt-bindings/net/ti-dp83869.h for values

  rx-internal-delay-ps:
    description: Delay is in pico seconds
    enum: [ 250, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000,
            3250, 3500, 3750, 4000 ]
    default: 2000

  tx-internal-delay-ps:
    description: Delay is in pico seconds
    enum: [ 250, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000,
            3250, 3500, 3750, 4000 ]
    default: 2000

required:
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/net/ti-dp83869.h>
    mdio0 {
      #address-cells = <1>;
      #size-cells = <0>;
      ethphy0: ethernet-phy@0 {
        reg = <0>;
        tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
        rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
        ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
        ti,max-output-impedance;
        ti,clk-output-sel = <DP83869_CLK_O_SEL_CHN_A_RCLK>;
        rx-internal-delay-ps = <2000>;
        tx-internal-delay-ps = <2000>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller)

maintainers:
  - Grygorii Strashko <grygorii.strashko@ti.com>
  - Sekhar Nori <nsekhar@ti.com>

description:
  The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
  (one external) and provides Ethernet packet communication for the device.
  The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
  (two external) and provides Ethernet packet communication and switching.

  The internal Communications Port Programming Interface (CPPI5) (Host port 0).
  Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
  and one RX channels and operating by NAVSS Unified DMA  Peripheral Root
  Complex (UDMA-P) controller.

  CPSWxG features
  updated Address Lookup Engine (ALE).
  priority level Quality Of Service (QOS) support (802.1p)
  Support for Audio/Video Bridging (P802.1Qav/D6.0)
  Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
  Flow Control (802.3x) Support
  Time Sensitive Network Support
  IEEE P902.3br/D2.0 Interspersing Express Traffic
  IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
  Configurable number of addresses plus VLANs
  Configurable number of classifier/policers
  VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
  ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
  RX/TX csum offload
  Management Data Input/Output (MDIO) interface for PHYs management
  RMII/RGMII Interfaces support
  new version of Common Platform Time Sync (CPTS)

  The CPSWxG NUSS is integrated into
    device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.
    device MAIN domain named CPSW0 on AM642x SoC.

  Specifications can be found at
    https://www.ti.com/lit/pdf/spruid7
    https://www.ti.com/lit/zip/spruil1
    https://www.ti.com/lit/pdf/spruim2

properties:
  "#address-cells": true
  "#size-cells": true

  compatible:
    enum:
      - ti,am654-cpsw-nuss
      - ti,j7200-cpswxg-nuss
      - ti,j721e-cpsw-nuss
      - ti,am642-cpsw-nuss

  reg:
    maxItems: 1
    description:
      The physical base address and size of full the CPSWxG NUSS IO range

  reg-names:
    items:
      - const: cpsw_nuss

  ranges: true

  dma-coherent: true

  clocks:
    maxItems: 1
    description: CPSWxG NUSS functional clock

  clock-names:
    items:
      - const: fck

  assigned-clock-parents: true

  assigned-clocks: true

  power-domains:
    maxItems: 1

  dmas:
    maxItems: 9

  dma-names:
    items:
      - const: tx0
      - const: tx1
      - const: tx2
      - const: tx3
      - const: tx4
      - const: tx5
      - const: tx6
      - const: tx7
      - const: rx

  ethernet-ports:
    type: object
    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    patternProperties:
      "^port@[1-4]$":
        type: object
        description: CPSWxG NUSS external ports

        $ref: ethernet-controller.yaml#
        unevaluatedProperties: false

        properties:
          reg:
            minimum: 1
            maximum: 4
            description: CPSW port number

          phys:
            maxItems: 1
            description: phandle on phy-gmii-sel PHY

          label:
            description: label associated with this port

          ti,mac-only:
            $ref: /schemas/types.yaml#/definitions/flag
            description:
              Specifies the port works in mac-only mode.

          ti,syscon-efuse:
            $ref: /schemas/types.yaml#/definitions/phandle-array
            items:
              - items:
                  - description: Phandle to the system control device node which
                      provides access to efuse
                  - description: offset to efuse registers???
            description:
              Phandle to the system control device node which provides access
              to efuse IO range with MAC addresses

        required:
          - reg
          - phys

    additionalProperties: false

patternProperties:
  "^mdio@[0-9a-f]+$":
    type: object
    $ref: "ti,davinci-mdio.yaml#"

    description:
      CPSW MDIO bus.

  "^cpts@[0-9a-f]+":
    type: object
    $ref: "ti,k3-am654-cpts.yaml#"
    description:
      CPSW Common Platform Time Sync (CPTS) module.

required:
  - compatible
  - reg
  - reg-names
  - ranges
  - clocks
  - clock-names
  - power-domains
  - dmas
  - dma-names
  - '#address-cells'
  - '#size-cells'

allOf:
  - if:
      not:
        properties:
          compatible:
            contains:
              const: ti,j7200-cpswxg-nuss
    then:
      properties:
        ethernet-ports:
          patternProperties:
            "^port@[3-4]$": false

additionalProperties: false

examples:
  - |
    #include <dt-bindings/pinctrl/k3.h>
    #include <dt-bindings/soc/ti,sci_pm_domain.h>
    #include <dt-bindings/net/ti-dp83867.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        mcu_cpsw: ethernet@46000000 {
            compatible = "ti,am654-cpsw-nuss";
            #address-cells = <2>;
            #size-cells = <2>;
            reg = <0x0 0x46000000 0x0 0x200000>;
            reg-names = "cpsw_nuss";
            ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
            dma-coherent;
            clocks = <&k3_clks 5 10>;
            clock-names = "fck";
            power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
            pinctrl-names = "default";
            pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;

            dmas = <&mcu_udmap 0xf000>,
                   <&mcu_udmap 0xf001>,
                   <&mcu_udmap 0xf002>,
                   <&mcu_udmap 0xf003>,
                   <&mcu_udmap 0xf004>,
                   <&mcu_udmap 0xf005>,
                   <&mcu_udmap 0xf006>,
                   <&mcu_udmap 0xf007>,
                   <&mcu_udmap 0x7000>;
            dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
                        "rx";

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                cpsw_port1: port@1 {
                    reg = <1>;
                    ti,mac-only;
                    label = "port1";
                    ti,syscon-efuse = <&mcu_conf 0x200>;
                    phys = <&phy_gmii_sel 1>;

                    phy-mode = "rgmii-rxid";
                    phy-handle = <&phy0>;
                };
            };

            davinci_mdio: mdio@f00 {
                compatible = "ti,cpsw-mdio","ti,davinci_mdio";
                reg = <0x0 0xf00 0x0 0x100>;
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&k3_clks 5 10>;
                clock-names = "fck";
                bus_freq = <1000000>;

                phy0: ethernet-phy@0 {
                    reg = <0>;
                    ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                    ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
                };
            };
        };

        cpts@3d000 {
             compatible = "ti,am65-cpts";
             reg = <0x0 0x3d000 0x0 0x400>;
             clocks = <&k3_clks 18 2>;
             clock-names = "cpts";
             interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
             interrupt-names = "cpts";
             ti,cpts-ext-ts-inputs = <4>;
             ti,cpts-periodic-outputs = <2>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ti,k3-am654-cpts.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module

maintainers:
  - Grygorii Strashko <grygorii.strashko@ti.com>
  - Sekhar Nori <nsekhar@ti.com>

description: |+
  The TI AM654x/J721E CPTS module is used to facilitate host control of time
  sync operations.
  Main features of CPTS module are
  - selection of multiple external clock sources
  - Software control of time sync events via interrupt or polling
  - 64-bit timestamp mode in ns with PPM and nudge adjustment.
  - hardware timestamp push inputs (HWx_TS_PUSH)
  - timestamp counter compare output (TS_COMP)
  - timestamp counter bit output (TS_SYNC)
  - periodic Generator function outputs (TS_GENFx)
  - Ethernet Enhanced Scheduled Traffic Operations (CPTS_ESTFn) (TSN)
  - external hardware timestamp push inputs (HWx_TS_PUSH) timestamping

   Depending on integration it enables compliance with the IEEE 1588-2008
   standard for a precision clock synchronization protocol, Ethernet Enhanced
   Scheduled Traffic Operations (CPTS_ESTFn) and PCIe Subsystem Precision Time
   Measurement (PTM).

  TI AM654x/J721E SoCs has several similar CPTS modules integrated into the
  different parts of the system which could be synchronized with each other
  - Main CPTS
  - MCU CPSW CPTS with IEEE 1588-2008 support
  - PCIe subsystem CPTS for PTM support

  Depending on CPTS module integration and when CPTS is integral part of
  another module (MCU CPSW for example) "compatible" and "reg" can
  be omitted - parent module is fully responsible for CPTS enabling and
  configuration.

properties:
  $nodename:
    pattern: "^cpts@[0-9a-f]+$"

  compatible:
    enum:
      - ti,am65-cpts
      - ti,j721e-cpts

  reg:
    maxItems: 1
    description:
      The physical base address and size of CPTS IO range

  reg-names:
    items:
      - const: cpts

  clocks:
    maxItems: 1
    description: CPTS reference clock

  clock-names:
    items:
      - const: cpts

  interrupts:
    items:
      - description: CPTS events interrupt

  interrupt-names:
    items:
      - const: cpts

  assigned-clock-parents: true

  assigned-clocks: true

  power-domains:
    maxItems: 1

  ti,cpts-ext-ts-inputs:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 8
    description:
      Number of hardware timestamp push inputs (HWx_TS_PUSH)

  ti,cpts-periodic-outputs:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 8
    description:
      Number of timestamp Generator function outputs (TS_GENFx)

  refclk-mux:
    type: object
    additionalProperties: false
    description: CPTS reference clock multiplexer clock
    properties:
      '#clock-cells':
        const: 0

      clocks:
        maxItems: 8

    required:
      - clocks

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    cpts@310d0000 {
         compatible = "ti,am65-cpts";
         reg = <0x310d0000 0x400>;
         reg-names = "cpts";
         clocks = <&main_cpts_mux>;
         clock-names = "cpts";
         interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>;
         interrupt-names = "cpts";
         ti,cpts-periodic-outputs = <6>;
         ti,cpts-ext-ts-inputs = <8>;

         main_cpts_mux: refclk-mux {
               #clock-cells = <0>;
               clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
                        <&k3_clks 157 91>, <&k3_clks 157 77>,
                        <&k3_clks 157 102>, <&k3_clks 157 80>,
                        <&k3_clks 120 3>, <&k3_clks 121 3>;
               assigned-clocks = <&main_cpts_mux>;
               assigned-clock-parents = <&k3_clks 118 11>;
         };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/toshiba,visconti-dwmac.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Toshiba Visconti DWMAC Ethernet controller

maintainers:
  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

select:
  properties:
    compatible:
      contains:
        enum:
          - toshiba,visconti-dwmac
  required:
    - compatible

allOf:
  - $ref: "snps,dwmac.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - toshiba,visconti-dwmac
          - const: snps,dwmac-4.20a

  reg:
    maxItems: 1

  clocks:
    items:
      - description: main clock
      - description: PHY reference clock

  clock-names:
    items:
      - const: stmmaceth
      - const: phy_ref_clk

required:
  - compatible
  - reg
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/toshiba,tmpv770x.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        piether: ethernet@28000000 {
            compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a";
            reg = <0 0x28000000 0 0x10000>;
            interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "macirq";
            clocks = <&pismu TMPV770X_CLK_PIETHER_BUS>, <&pismu TMPV770X_CLK_PIETHER_125M>;
            clock-names = "stmmaceth", "phy_ref_clk";
            snps,txpbl = <4>;
            snps,rxpbl = <4>;
            snps,tso;
            phy-mode = "rgmii-id";
            phy-handle = <&phy0>;

            mdio {
                #address-cells = <0x1>;
                #size-cells = <0x0>;
                compatible = "snps,dwmac-mdio";

                phy0: ethernet-phy@1 {
                    device_type = "ethernet-phy";
                    reg = <0x1>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/vertexcom-mse102x.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: The Vertexcom MSE102x (SPI)

maintainers:
  - Stefan Wahren <stefan.wahren@chargebyte.com>

description:
  Vertexcom's MSE102x are a family of HomePlug GreenPHY chips.
  They can be connected either via RGMII, RMII or SPI to a host CPU.

  In order to use a MSE102x chip as SPI device, it must be defined as
  a child of an SPI master device in the device tree.

  More information can be found at
    http://www.vertexcom.com/doc/MSE1022%20Product%20Brief.pdf

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    enum:
      - vertexcom,mse1021
      - vertexcom,mse1022

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  spi-cpha: true

  spi-cpol: true

  spi-max-frequency:
    minimum: 6000000
    maximum: 7142857

required:
  - compatible
  - reg
  - interrupts
  - spi-cpha
  - spi-cpol
  - spi-max-frequency

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    spi0 {
        #address-cells = <1>;
        #size-cells = <0>;

        ethernet@0 {
            compatible = "vertexcom,mse1021";
            reg = <0>;
            interrupt-parent = <&gpio>;
            interrupts = <23 IRQ_TYPE_EDGE_RISING>;
            spi-cpha;
            spi-cpol;
            spi-max-frequency = <7142857>;
        };
    };


code:
* VIA Rhine 10/100 Network Controller

Required properties:
- compatible : Should be "via,vt8500-rhine" for integrated
	Rhine controllers found in VIA VT8500, WonderMedia WM8950
	and similar. These are listed as 1106:3106 rev. 0x84 on the
	virtual PCI bus under vendor-provided kernels
- reg : Address and length of the io space
- interrupts : Should contain the controller interrupt line

Examples:

ethernet@d8004000 {
	compatible = "via,vt8500-rhine";
	reg = <0xd8004000 0x100>;
	interrupts = <10>;
};


code:
* VIA Velocity 10/100/1000 Network Controller

Required properties:
- compatible : Should be "via,velocity-vt6110"
- reg : Address and length of the io space
- interrupts : Should contain the controller interrupt line

Optional properties:
- no-eeprom : PCI network cards use an external EEPROM to store data. Embedded
	devices quite often set this data in uboot and do not provide an eeprom.
	Specify this option if you have no external eeprom.

Examples:

eth0@d8004000 {
	compatible = "via,velocity-vt6110";
	reg = <0xd8004000 0x400>;
	interrupts = <10>;
	no-eeprom;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/wireless/brcm,bcm4329-fmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM4329 family fullmac wireless SDIO/PCIE devices

maintainers:
  - Arend van Spriel <arend@broadcom.com>

description:
  The Broadcom Single chip MAC part for the BCM4329 family and
  later Cypress chips in the same family named CYW4373 and similar.
  These chips also have a Bluetooth portion described in a separate
  binding.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - brcm,bcm43143-fmac
              - brcm,bcm4341b0-fmac
              - brcm,bcm4341b4-fmac
              - brcm,bcm4341b5-fmac
              - brcm,bcm4329-fmac
              - brcm,bcm4330-fmac
              - brcm,bcm4334-fmac
              - brcm,bcm43340-fmac
              - brcm,bcm4335-fmac
              - brcm,bcm43362-fmac
              - brcm,bcm4339-fmac
              - brcm,bcm43430a0-fmac
              - brcm,bcm43430a1-fmac
              - brcm,bcm43455-fmac
              - brcm,bcm43456-fmac
              - brcm,bcm4354-fmac
              - brcm,bcm4356-fmac
              - brcm,bcm4359-fmac
              - cypress,cyw4373-fmac
              - cypress,cyw43012-fmac
          - const: brcm,bcm4329-fmac
      - enum:
          - brcm,bcm4329-fmac
          - pci14e4,43dc  # BCM4355
          - pci14e4,4464  # BCM4364
          - pci14e4,4488  # BCM4377
          - pci14e4,4425  # BCM4378
          - pci14e4,4433  # BCM4387

  reg:
    description: SDIO function number for the device (for most cases
      this will be 1) or PCI device identifier.

  interrupts:
    maxItems: 1
    description: Out-of-band (OOB) IRQ line for waking up the host
      in response to WLAN activity. This corresponds to the HOST_WAKE
      line into the chip.

  interrupt-names:
    description: Name for the OOB IRQ, this must be set to "host-wake".
    const: host-wake

  brcm,drive-strength:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Drive strength used for the SDIO pins on the device in mA.
    minimum: 0
    maximum: 32

  reset-gpios:
    maxItems: 1
    description: A GPIO line connected to the WL_RST line, if present
      this shall be flagged as active low.

  brcm,ccode-map:
    $ref: /schemas/types.yaml#/definitions/string-array
    description: Multiple strings for translating ISO3166 country code to
      brcmfmac firmware country code and revision.
    items:
      pattern: '^[A-Z][A-Z]-[A-Z][0-9A-Z]-[0-9]+$'

  brcm,ccode-map-trivial:
    description: |
      Use a trivial mapping of ISO3166 country codes to brcmfmac firmware
      country code and revision: cc -> { cc, 0 }. In other words, assume that
      the CLM blob firmware uses ISO3166 country codes as well, and that all
      revisions are zero. This property is mutually exclusive with
      brcm,ccode-map. If both properties are specified, then brcm,ccode-map
      takes precedence.
    type: boolean

  brcm,cal-blob:
    $ref: /schemas/types.yaml#/definitions/uint8-array
    description: A per-device calibration blob for the Wi-Fi radio. This
      should be filled in by the bootloader from platform configuration
      data, if necessary, and will be uploaded to the device if present.

  brcm,board-type:
    $ref: /schemas/types.yaml#/definitions/string
    description: Overrides the board type, which is normally the compatible of
      the root node. This can be used to decouple the overall system board or
      device name from the board type for WiFi purposes, which is used to
      construct firmware and NVRAM configuration filenames, allowing for
      multiple devices that share the same module or characteristics for the
      WiFi subsystem to share the same firmware/NVRAM files. On Apple platforms,
      this should be the Apple module-instance codename prefixed by "apple,",
      e.g. "apple,honshu".

  apple,antenna-sku:
    $ref: /schemas/types.yaml#/definitions/string
    description: Antenna SKU used to identify a specific antenna configuration
      on Apple platforms. This is use to build firmware filenames, to allow
      platforms with different antenna configs to have different firmware and/or
      NVRAM. This would normally be filled in by the bootloader from platform
      configuration data.

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>
    mmc@80118000 {
      compatible = "arm,pl18x", "arm,primecell";
      reg = <0x80118000 0x1000>;
      clocks = <&clk 0>, <&clk 1>;
      clock-names = "mclk", "apb_pclk";
      interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
      bus-width = <4>;
      non-removable;
      vmmc-supply = <&wl_bt_reg>;
      #address-cells = <1>;
      #size-cells = <0>;

      wifi@1 {
        compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac";
        reg = <1>;
        interrupt-parent = <&gpio>;
        interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
        interrupt-names = "host-wake";
        reset-gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
        brcm,ccode-map = "JP-JP-78", "US-Q2-86";
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/wireless/esp,esp8089.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Espressif ESP8089 Device Tree Bindings

maintainers:
  - Hans de Goede <hdegoede@redhat.com>

properties:
  compatible:
    const: esp,esp8089

  reg:
    maxItems: 1

  esp,crystal-26M-en:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: >
      Value for the crystal_26M_en firmware parameter

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
      mmc {
          #address-cells = <1>;
          #size-cells = <0>;

          wifi@1 {
              compatible = "esp,esp8089";
              reg = <1>;
              esp,crystal-26M-en = <2>;
          };
      };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.

%YAML 1.2
---
$id: http://devicetree.org/schemas/net/wireless/ieee80211.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common IEEE 802.11 Binding

maintainers:
  - Lorenzo Bianconi <lorenzo@kernel.org>

description: |
  This provides documentation of common properties that are valid for
  all wireless devices

properties:
  ieee80211-freq-limit:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    items:
      minItems: 2
      maxItems: 2
    description:
      List of supported frequency ranges in KHz. This can be used for devices
      that in a given config support less channels than normally. It may happen
      chipset supports a wide wireless band but it is limited to some part of
      it due to used antennas or power amplifier. An example case for this
      can be tri-band wireless router with two identical chipsets used for two
      different 5 GHz subbands. Using them incorrectly could not work or
      decrease performance noticeably

additionalProperties: true

examples:
  - |
    pcie0 {
      #address-cells = <3>;
      #size-cells = <2>;
      wifi@0,0 {
        reg = <0x0000 0 0 0 0>;
        ieee80211-freq-limit = <2402000 2482000>,
                               <5170000 5250000>;
      };
    };


code:
Marvell 8787/8897/8997 (sd8787/sd8897/sd8997/pcie8997) SDIO/PCIE devices
------

This node provides properties for controlling the Marvell SDIO/PCIE wireless device.
The node is expected to be specified as a child node to the SDIO/PCIE controller that
connects the device to the system.

Required properties:

  - compatible : should be one of the following:
	* "marvell,sd8787"
	* "marvell,sd8897"
	* "marvell,sd8997"
	* "pci11ab,2b42"
	* "pci1b4b,2b42"

Optional properties:

  - marvell,caldata* : A series of properties with marvell,caldata prefix,
		      represent calibration data downloaded to the device during
		      initialization. This is an array of unsigned 8-bit values.
		      the properties should follow below property name and
		      corresponding array length:
	"marvell,caldata-txpwrlimit-2g" (length = 566).
	"marvell,caldata-txpwrlimit-5g-sub0" (length = 502).
	"marvell,caldata-txpwrlimit-5g-sub1" (length = 688).
	"marvell,caldata-txpwrlimit-5g-sub2" (length = 750).
	"marvell,caldata-txpwrlimit-5g-sub3" (length = 502).
  - marvell,wakeup-pin : a wakeup pin number of wifi chip which will be configured
		      to firmware. Firmware will wakeup the host using this pin
		      during suspend/resume.
  - interrupts : interrupt pin number to the cpu. driver will request an irq based on
		 this interrupt number. during system suspend, the irq will be enabled
		 so that the wifi chip can wakeup host platform under certain condition.
		 during system resume, the irq will be disabled to make sure
		 unnecessary interrupt is not received.
  - vmmc-supply: a phandle of a regulator, supplying VCC to the card
  - mmc-pwrseq:  phandle to the MMC power sequence node. See "mmc-pwrseq-*"
		 for documentation of MMC power sequence bindings.

Example:

Tx power limit calibration data is configured in below example.
The calibration data is an array of unsigned values, the length
can vary between hw versions.
IRQ pin 38 is used as system wakeup source interrupt. wakeup pin 3 is configured
so that firmware can wakeup host using this device side pin.

&mmc3 {
	vmmc-supply = <&wlan_en_reg>;
	mmc-pwrseq = <&wifi_pwrseq>;
	bus-width = <4>;
	cap-power-off-card;
	keep-power-in-suspend;

	#address-cells = <1>;
	#size-cells = <0>;
	mwifiex: wifi@1 {
		compatible = "marvell,sd8897";
		reg = <1>;
		interrupt-parent = <&pio>;
		interrupts = <38 IRQ_TYPE_LEVEL_LOW>;

		marvell,caldata_00_txpwrlimit_2g_cfg_set = /bits/ 8 <
	0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01>;
		marvell,wakeup-pin = <3>;
	};
};