code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: General Purpose I2C Bus Mux

maintainers:
  - Peter Rosin <peda@axentia.se>

description: |+
  This binding describes an I2C bus multiplexer that uses a mux controller
  from the mux subsystem to route the I2C signals.

                                    .-----.  .-----.
                                    | dev |  | dev |
      .------------.                '-----'  '-----'
      | SoC        |                   |        |
      |            |          .--------+--------'
      |   .------. |  .------+    child bus A, on MUX value set to 0
      |   | I2C  |-|--| Mux  |
      |   '------' |  '--+---+    child bus B, on MUX value set to 1
      |   .------. |     |    '----------+--------+--------.
      |   | MUX- | |     |               |        |        |
      |   | Ctrl |-|-----+            .-----.  .-----.  .-----.
      |   '------' |                  | dev |  | dev |  | dev |
      '------------'                  '-----'  '-----'  '-----'

allOf:
  - $ref: /schemas/i2c/i2c-mux.yaml#

properties:
  compatible:
    const: i2c-mux

  i2c-parent:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      The phandle of the I2C bus that this multiplexer's master-side port is
      connected to.

  mux-controls:
    maxItems: 1
    description:
      The mux-controller states are the I2C sub-bus numbers.

  mux-locked:
    type: boolean
    description: |
      Explicitly allow unrelated I2C transactions on the parent I2C adapter at
      these times:
       - during setup of the multiplexer
       - between setup of the multiplexer and the child bus I2C transaction
       - between the child bus I2C transaction and releasing of the multiplexer
       - during releasing of the multiplexer

      However, I2C transactions to devices behind all I2C multiplexers connected
      to the same parent adapter that this multiplexer is connected to are blocked
      for the full duration of the complete multiplexed I2C transaction (i.e.
      including the times covered by the above list).
      If mux-locked is not present, the multiplexer is assumed to be parent-locked.
      This means that no unrelated I2C transactions are allowed on the parent I2C
      adapter for the complete multiplexed I2C transaction.
      The properties of mux-locked and parent-locked multiplexers are discussed
      in more detail in Documentation/i2c/i2c-topology.rst.

required:
  - compatible
  - i2c-parent
  - mux-controls

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    mux: mux-controller {
        compatible = "gpio-mux";
        #mux-control-cells = <0>;

        mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
                    <&pioA 1 GPIO_ACTIVE_HIGH>;
    };

    i2c-mux {
        compatible = "i2c-mux";
        mux-locked;
        i2c-parent = <&i2c1>;

        mux-controls = <&mux>;

        #address-cells = <1>;
        #size-cells = <0>;

        i2c@1 {
            reg = <1>;
            #address-cells = <1>;
            #size-cells = <0>;

            gpio@20 {
                compatible = "nxp,pca9555";
                gpio-controller;
                #gpio-cells = <2>;
                reg = <0x20>;
            };
        };

        i2c@3 {
            reg = <3>;
            #address-cells = <1>;
            #size-cells = <0>;

            gpio@20 {
                compatible = "nxp,pca9555";
                gpio-controller;
                #gpio-cells = <2>;
                reg = <0x20>;
            };
        };
    };
...


code:
* Linear Technology / Analog Devices I2C bus switch

Required Properties:

  - compatible: Must contain one of the following.
    "lltc,ltc4305", "lltc,ltc4306"
  - reg: The I2C address of the device.

  The following required properties are defined externally:

  - Standard I2C mux properties. See i2c-mux.yaml in this directory.
  - I2C child bus nodes. See i2c-mux.yaml in this directory.

Optional Properties:

  - enable-gpios: Reference to the GPIO connected to the enable input.
  - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all
    children in idle state. This is necessary for example, if there are several
    multiplexers on the bus and the devices behind them use same I2C addresses.
  - gpio-controller: Marks the device node as a GPIO Controller.
  - #gpio-cells: Should be two.  The first cell is the pin number and
	the second cell is used to specify flags.
	See ../gpio/gpio.txt for more information.
  - ltc,downstream-accelerators-enable: Enables the rise time accelerators
	on the downstream port.
  - ltc,upstream-accelerators-enable: Enables the rise time accelerators
	on the upstream port.

Example:

	ltc4306: i2c-mux@4a {
		compatible = "lltc,ltc4306";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x4a>;

		gpio-controller;
		#gpio-cells = <2>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			eeprom@50 {
				compatible = "atmel,24c02";
				reg = <0x50>;
			};
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			eeprom@50 {
				compatible = "atmel,24c02";
				reg = <0x50>;
			};
		};
	};

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-mux-pca954x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP PCA954x I2C bus switch

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description:
  The binding supports NXP PCA954x and PCA984x I2C mux/switch devices.

allOf:
  - $ref: /schemas/i2c/i2c-mux.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - nxp,pca9540
          - nxp,pca9542
          - nxp,pca9543
          - nxp,pca9544
          - nxp,pca9545
          - nxp,pca9546
          - nxp,pca9547
          - nxp,pca9548
          - nxp,pca9846
          - nxp,pca9847
          - nxp,pca9848
          - nxp,pca9849
      - items:
          - const: nxp,pca9646
          - const: nxp,pca9546

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#interrupt-cells":
    const: 2

  interrupt-controller: true

  reset-gpios:
    maxItems: 1

  i2c-mux-idle-disconnect:
    type: boolean
    description: Forces mux to disconnect all children in idle state. This is
      necessary for example, if there are several multiplexers on the bus and
      the devices behind them use same I2C addresses.

  idle-state:
    description: if present, overrides i2c-mux-idle-disconnect
    $ref: /schemas/mux/mux-controller.yaml#/properties/idle-state

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        i2c-mux@74 {
            compatible = "nxp,pca9548";
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0x74>;

            interrupt-parent = <&ipic>;
            interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
            interrupt-controller;
            #interrupt-cells = <2>;

            i2c@2 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <2>;

                eeprom@54 {
                    compatible = "atmel,24c08";
                    reg = <0x54>;
                };
            };

            i2c@4 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <4>;

                rtc@51 {
                    compatible = "nxp,pcf8563";
                    reg = <0x51>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-mux-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Pinctrl-based I2C Bus Mux

maintainers:
  - Wolfram Sang <wsa@kernel.org>

description: |
  This binding describes an I2C bus multiplexer that uses pin multiplexing to route the I2C
  signals, and represents the pin multiplexing configuration using the pinctrl device tree
  bindings.

                                 +-----+  +-----+
                                 | dev |  | dev |
    +------------------------+   +-----+  +-----+
    | SoC                    |      |        |
    |                   /----|------+--------+
    |   +---+   +------+     | child bus A, on first set of pins
    |   |I2C|---|Pinmux|     |
    |   +---+   +------+     | child bus B, on second set of pins
    |                   \----|------+--------+--------+
    |                        |      |        |        |
    +------------------------+  +-----+  +-----+  +-----+
                                | dev |  | dev |  | dev |
                                +-----+  +-----+  +-----+

  For each named state defined in the pinctrl-names property, an I2C child bus will be created.
  I2C child bus numbers are assigned based on the index into the pinctrl-names property.

  The only exception is that no bus will be created for a state named "idle". If such a state is
  defined, it must be the last entry in pinctrl-names. For example:

    pinctrl-names = "ddc", "pta", "idle"  ->  ddc = bus 0, pta = bus 1
    pinctrl-names = "ddc", "idle", "pta"  ->  Invalid ("idle" not last)
    pinctrl-names = "idle", "ddc", "pta"  ->  Invalid ("idle" not last)

  Whenever an access is made to a device on a child bus, the relevant pinctrl state will be
  programmed into hardware.

  If an idle state is defined, whenever an access is not being made to a device on a child bus,
  the idle pinctrl state will be programmed into hardware.

  If an idle state is not defined, the most recently used pinctrl state will be left programmed
  into hardware whenever no access is being made of a device on a child bus.

properties:
  compatible:
    const: i2c-mux-pinctrl

  i2c-parent:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: The phandle of the I2C bus that this multiplexer's master-side port is connected
      to.

allOf:
  - $ref: i2c-mux.yaml

unevaluatedProperties: false

required:
  - compatible
  - i2c-parent

examples:
  - |
    i2cmux {
      compatible = "i2c-mux-pinctrl";
      #address-cells = <1>;
      #size-cells = <0>;

      i2c-parent = <&i2c1>;

      pinctrl-names = "ddc", "pta", "idle";
      pinctrl-0 = <&state_i2cmux_ddc>;
      pinctrl-1 = <&state_i2cmux_pta>;
      pinctrl-2 = <&state_i2cmux_idle>;

      i2c@0 {
        reg = <0>;
        #address-cells = <1>;
        #size-cells = <0>;

        eeprom@50 {
          compatible = "atmel,24c02";
          reg = <0x50>;
        };
      };

      i2c@1 {
        reg = <1>;
        #address-cells = <1>;
        #size-cells = <0>;

        eeprom@50 {
          compatible = "atmel,24c02";
          reg = <0x50>;
        };
      };
    };


code:
Register-based I2C Bus Mux

This binding describes an I2C bus multiplexer that uses a single register
to route the I2C signals.

Required properties:
- compatible: i2c-mux-reg
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
  port is connected to.
* Standard I2C mux properties. See i2c-mux.yaml in this directory.
* I2C child bus nodes. See i2c-mux.yaml in this directory.

Optional properties:
- reg: this pair of <offset size> specifies the register to control the mux.
  The <offset size> depends on its parent node. It can be any memory-mapped
  address. The size must be either 1, 2, or 4 bytes. If reg is omitted, the
  resource of this device will be used.
- little-endian: The existence indicates the register is in little endian.
- big-endian: The existence indicates the register is in big endian.
  If both little-endian and big-endian are omitted, the endianness of the
  CPU will be used.
- write-only: The existence indicates the register is write-only.
- idle-state: value to set the muxer to when idle. When no value is
  given, it defaults to the last value used.

Whenever an access is made to a device on a child bus, the value set
in the relevant node's reg property will be output to the register.

If an idle state is defined, using the idle-state (optional) property,
whenever an access is not being made to a device on a child bus, the
register will be set according to the idle value.

If an idle state is not defined, the most recently used value will be
left programmed into the register.

Example of a mux on PCIe card, the host is a powerpc SoC (big endian):

	i2c-mux {
		/* the <offset size> depends on the address translation
		 * of the parent device. If omitted, device resource
		 * will be used instead. The size is to determine
		 * whether iowrite32, iowrite16, or iowrite8 will be used.
		 */
		reg = <0x6028 0x4>;
		little-endian;		/* little endian register on PCIe */
		compatible = "i2c-mux-reg";
		#address-cells = <1>;
		#size-cells = <0>;
		i2c-parent = <&i2c1>;
		i2c@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			si5338: clock-generator@70 {
				compatible = "silabs,si5338";
				reg = <0x70>;
				/* other stuff */
			};
		};

		i2c@1 {
			/* data is written using iowrite32 */
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			si5338: clock-generator@70 {
				compatible = "silabs,si5338";
				reg = <0x70>;
				/* other stuff */
			};
		};
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-mux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common i2c bus multiplexer/switch properties.

maintainers:
  - Peter Rosin <peda@axentia.se>

description: |+
  An i2c bus multiplexer/switch will have several child busses that are numbered
  uniquely in a device dependent manner.  The nodes for an i2c bus
  multiplexer/switch will have one child node for each child bus.

  For i2c multiplexers/switches that have child nodes that are a mixture of both
  i2c child busses and other child nodes, the 'i2c-mux' subnode can be used for
  populating the i2c child busses.  If an 'i2c-mux' subnode is present, only
  subnodes of this will be considered as i2c child busses.

properties:
  $nodename:
    pattern: '^(i2c-?)?mux'

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

patternProperties:
  '^i2c@[0-9a-f]+$':
    $ref: /schemas/i2c/i2c-controller.yaml
    unevaluatedProperties: false

    properties:
      reg:
        description: The mux selector sub-bus number for the child I2C bus.
        maxItems: 1

additionalProperties: true

examples:
  - |
    /*
     * An NXP pca9548 8 channel I2C multiplexer at address 0x70
     * with two NXP pca8574 GPIO expanders attached, one each to
     * ports 3 and 4.
     */
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        i2c-mux@70 {
            compatible = "nxp,pca9548";
            reg = <0x70>;
            #address-cells = <1>;
            #size-cells = <0>;

            i2c@3 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <3>;

                gpio@20 {
                    compatible = "nxp,pca9555";
                    gpio-controller;
                    #gpio-cells = <2>;
                    reg = <0x20>;
                };
            };
            i2c@4 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <4>;

                gpio@20 {
                    compatible = "nxp,pca9555";
                    gpio-controller;
                    #gpio-cells = <2>;
                    reg = <0x20>;
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-mxs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale MXS Inter IC (I2C) Controller

maintainers:
  - Shawn Guo <shawnguo@kernel.org>

properties:
  compatible:
    enum:
      - fsl,imx23-i2c
      - fsl,imx28-i2c

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clock-frequency:
    enum: [ 100000, 400000 ]

  dmas:
    maxItems: 1

  dma-names:
    const: rx-tx

required:
  - compatible
  - reg
  - interrupts
  - dmas
  - dma-names

additionalProperties: false

examples:
  - |
    i2c@80058000 {
        compatible = "fsl,imx28-i2c";
        reg = <0x80058000 2000>;
        interrupts = <111>;
        clock-frequency = <100000>;
        dmas = <&dma_apbx 6>;
        dma-names = "rx-tx";
    };


code:
* Two Wire Serial Interface (TWSI) / I2C

- compatible: "cavium,octeon-3860-twsi"

  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.

  or

  compatible: "cavium,octeon-7890-twsi"

  Compatibility with cn78XX SOCs.

- reg: The base address of the TWSI/I2C bus controller register bank.

- #address-cells: Must be <1>.

- #size-cells: Must be <0>.  I2C addresses have no size component.

- interrupts: A single interrupt specifier.

- clock-frequency: The I2C bus clock rate in Hz.

Example:
	twsi0: i2c@1180000001000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "cavium,octeon-3860-twsi";
		reg = <0x11800 0x00001000 0x0 0x200>;
		interrupts = <0 45>;
		clock-frequency = <100000>;

		rtc@68 {
			compatible = "dallas,ds1337";
			reg = <0x68>;
		};
		tmp@4c {
			compatible = "ti,tmp421";
			reg = <0x4c>;
		};
	};


code:
Device-tree bindings for I2C OPAL driver
----------------------------------------

Most of the device node and properties layout is specific to the firmware and
used by the firmware itself for configuring the port. From the linux
perspective, the properties of use are "ibm,port-name" and "ibm,opal-id".

Required properties:

- reg: Port-id within a given master
- compatible: must be "ibm,opal-i2c"
- ibm,opal-id: Refers to a specific bus and used to identify it when calling
	       the relevant OPAL functions.
- bus-frequency: Operating frequency of the i2c bus (in HZ). Informational for
		 linux, used by the FW though.

Optional properties:
- ibm,port-name: Firmware provides this name that uniquely identifies the i2c
		 port.

The node contains a number of other properties that are used by the FW itself
and depend on the specific hardware implementation. The example below depicts
a P8 on-chip bus.

Example:

i2c-bus@0 {
	reg = <0x0>;
	bus-frequency = <0x61a80>;
	compatible = "ibm,power8-i2c-port", "ibm,opal-i2c";
	ibm,opal-id = <0x1>;
	ibm,port-name = "p8_00000000_e1p0";
	#address-cells = <0x1>;
	phandle = <0x10000006>;
	#size-cells = <0x0>;
	linux,phandle = <0x10000006>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-owl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Actions Semi Owl I2C Controller

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

description: |
  This I2C controller is found in the Actions Semi Owl SoCs:
  S500, S700 and S900.

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

properties:
  compatible:
    enum:
      - actions,s500-i2c # Actions Semi S500 compatible SoCs
      - actions,s700-i2c # Actions Semi S700 compatible SoCs
      - actions,s900-i2c # Actions Semi S900 compatible SoCs

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    description: Phandle of the clock feeding the I2C controller.
    minItems: 1

  clock-frequency:
    description: |
      Desired I2C bus clock frequency in Hz. As only Standard and Fast
      modes are supported, possible values are 100000 and 400000.
    enum: [100000, 400000]

required:
  - compatible
  - reg
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/actions,s900-cmu.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    i2c@e0170000 {
        compatible = "actions,s900-i2c";
        reg = <0xe0170000 0x1000>;
        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cmu CLK_I2C0>;
        clock-frequency = <100000>;
    };

...


code:
* NXP PCA PCA9564/PCA9665 I2C controller

The PCA9564/PCA9665 serves as an interface between most standard
parallel-bus microcontrollers/microprocessors and the serial I2C-bus
and allows the parallel bus system to communicate bi-directionally
with the I2C-bus.

Required properties :

 - reg : Offset and length of the register set for the device
 - compatible : one of "nxp,pca9564" or "nxp,pca9665"

Optional properties
 - interrupts : the interrupt number
 - reset-gpios : gpio specifier for gpio connected to RESET_N pin. As the line
   is active low, it should be marked GPIO_ACTIVE_LOW.
 - clock-frequency : I2C bus frequency.

Example:
	i2c0: i2c@80000 {
		compatible = "nxp,pca9564";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x80000 0x4>;
		reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
		clock-frequency = <100000>;
	};


code:
* NXP PNX I2C Controller

Required properties:

 - reg: Offset and length of the register set for the device
 - compatible: should be "nxp,pnx-i2c"
 - interrupts: configure one interrupt line
 - #address-cells: always 1 (for i2c addresses)
 - #size-cells: always 0

Optional properties:

 - clock-frequency: desired I2C bus clock frequency in Hz, Default: 100000 Hz

Examples:

	i2c1: i2c@400a0000 {
		compatible = "nxp,pnx-i2c";
		reg = <0x400a0000 0x100>;
		interrupt-parent = <&mic>;
		interrupts = <51 0>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	i2c2: i2c@400a8000 {
		compatible = "nxp,pnx-i2c";
		reg = <0x400a8000 0x100>;
		interrupt-parent = <&mic>;
		interrupts = <50 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <100000>;
	};


code:
CE4100 I2C
----------

CE4100 has one PCI device which is described as the I2C-Controller. This
PCI device has three PCI-bars, each bar contains a complete I2C
controller. So we have a total of three independent I2C-Controllers
which share only an interrupt line.
The driver is probed via the PCI-ID and is gathering the information of
attached devices from the devices tree.
Grant Likely recommended to use the ranges property to map the PCI-Bar
number to its physical address and to use this to find the child nodes
of the specific I2C controller. This were his exact words:

       Here's where the magic happens.  Each entry in
       ranges describes how the parent pci address space
       (middle group of 3) is translated to the local
       address space (first group of 2) and the size of
       each range (last cell).  In this particular case,
       the first cell of the local address is chosen to be
       1:1 mapped to the BARs, and the second is the
       offset from be base of the BAR (which would be
       non-zero if you had 2 or more devices mapped off
       the same BAR)

       ranges allows the address mapping to be described
       in a way that the OS can interpret without
       requiring custom device driver code.

This is an example which is used on FalconFalls:
------------------------------------------------
	i2c-controller@b,2 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "pci8086,2e68.2",
				"pci8086,2e68",
				"pciclass,ff0000",
				"pciclass,ff00";

		reg = <0x15a00 0x0 0x0 0x0 0x0>;
		interrupts = <16 1>;

		/* as described by Grant, the first number in the group of
		* three is the bar number followed by the 64bit bar address
		* followed by size of the mapping. The bar address
		* requires also a valid translation in parents ranges
		* property.
		*/
		ranges = <0 0   0x02000000 0 0xdffe0500 0x100
			  1 0   0x02000000 0 0xdffe0600 0x100
			  2 0   0x02000000 0 0xdffe0700 0x100>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "intel,ce4100-i2c-controller";

			/* The first number in the reg property is the
			* number of the bar
			*/
			reg = <0 0 0x100>;

			/* This I2C controller has no devices */
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "intel,ce4100-i2c-controller";
			reg = <1 0 0x100>;

			/* This I2C controller has one gpio controller */
			gpio@26 {
				#gpio-cells = <2>;
				compatible = "nxp,pcf8575";
				reg = <0x26>;
				gpio-controller;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "intel,ce4100-i2c-controller";
			reg = <2 0 0x100>;

			gpio@26 {
				#gpio-cells = <2>;
				compatible = "nxp,pcf8575";
				reg = <0x26>;
				gpio-controller;
			};
		};
	};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-pxa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell MMP I2C controller bindings

maintainers:
  - Rob Herring <robh+dt@kernel.org>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#
  - if:
      not:
        required:
          - mrvl,i2c-polling
    then:
      required:
        - interrupts

properties:
  compatible:
    enum:
      - mrvl,mmp-twsi
      - mrvl,pxa-i2c
      - marvell,armada-3700-i2c

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1

  resets:
    minItems: 1

  mrvl,i2c-polling:
    $ref: /schemas/types.yaml#/definitions/flag
    description: |
      Disable interrupt of i2c controller. Polling status register of i2c
      controller instead.

  mrvl,i2c-fast-mode:
    $ref: /schemas/types.yaml#/definitions/flag
    description: Enable fast mode of i2c controller.

unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - '#address-cells'
  - '#size-cells'

examples:
  - |
    #include <dt-bindings/clock/marvell,mmp2.h>
    i2c@d4011000 {
        compatible = "mrvl,mmp-twsi";
        reg = <0xd4011000 0x1000>;
        interrupts = <7>;
        clocks = <&soc_clocks MMP2_CLK_TWSI1>;
        mrvl,i2c-fast-mode;
        #address-cells = <1>;
        #size-cells = <0>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3xxx I2C controller

description:
  This driver interfaces with the native I2C controller present in Rockchip
  RK3xxx SoCs.

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

# Everything else is described in the common file
properties:
  compatible:
    oneOf:
      - const: rockchip,rv1108-i2c
      - const: rockchip,rk3066-i2c
      - const: rockchip,rk3188-i2c
      - const: rockchip,rk3228-i2c
      - const: rockchip,rk3288-i2c
      - const: rockchip,rk3399-i2c
      - items:
          - enum:
              - rockchip,rk3036-i2c
              - rockchip,rk3128-i2c
              - rockchip,rk3368-i2c
          - const: rockchip,rk3288-i2c
      - items:
          - enum:
              - rockchip,px30-i2c
              - rockchip,rk3308-i2c
              - rockchip,rk3328-i2c
              - rockchip,rk3568-i2c
              - rockchip,rk3588-i2c
              - rockchip,rv1126-i2c
          - const: rockchip,rk3399-i2c

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description:
          For older hardware (rk3066, rk3188, rk3228, rk3288)
          there is one clock that is used both to derive the functional clock
          for the device and as the bus clock.
          For newer hardware (rk3399) this clock is used to derive
          the functional clock
      - description:
          For newer hardware (rk3399) this is the bus clock

  clock-names:
    minItems: 1
    items:
      - const: i2c
      - const: pclk

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Required on RK3066, RK3188 the phandle of the syscon node for
      the general register file (GRF)
      On those SoCs an alias with the correct I2C bus ID
      (bit offset in the GRF) is also required.

  clock-frequency:
    default: 100000
    description:
      SCL frequency to use (in Hz). If omitted, 100kHz is used.

  i2c-scl-rising-time-ns:
    default: 1000
    description:
      Number of nanoseconds the SCL signal takes to rise
      (t(r) in I2C specification). If not specified this is assumed to be
      the maximum the specification allows(1000 ns for Standard-mode,
      300 ns for Fast-mode) which might cause slightly slower communication.

  i2c-scl-falling-time-ns:
    default: 300
    description:
      Number of nanoseconds the SCL signal takes to fall
      (t(f) in the I2C specification). If not specified this is assumed to
      be the maximum the specification allows (300 ns) which might cause
      slightly slower communication.

  i2c-sda-falling-time-ns:
    default: 300
    description:
      Number of nanoseconds the SDA signal takes to fall
      (t(f) in the I2C specification). If not specified we will use the SCL
      value since they are the same in nearly all cases.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

if:
  properties:
    compatible:
      contains:
        enum:
          - rockchip,rk3066-i2c
          - rockchip,rk3188-i2c

then:
  required:
    - rockchip,grf

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3188-cru-common.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c0: i2c@2002d000 {
      compatible = "rockchip,rk3188-i2c";
      reg = <0x2002d000 0x1000>;
      interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&cru PCLK_I2C0>;
      clock-names = "i2c";
      rockchip,grf = <&grf>;
      i2c-scl-falling-time-ns = <100>;
      i2c-scl-rising-time-ns = <800>;
      #address-cells = <1>;
      #size-cells = <0>;
    };


code:
I2C for Spreadtrum platforms

Required properties:
- compatible: Should be "sprd,sc9860-i2c".
- reg: Specify the physical base address of the controller and length
  of memory mapped region.
- interrupts: Should contain I2C interrupt.
- clock-names: Should contain following entries:
  "i2c" for I2C clock,
  "source" for I2C source (parent) clock,
  "enable" for I2C module enable clock.
- clocks: Should contain a clock specifier for each entry in clock-names.
- clock-frequency: Constains desired I2C bus clock frequency in Hz.
- #address-cells: Should be 1 to describe address cells for I2C device address.
- #size-cells: Should be 0 means no size cell for I2C device address.

Optional properties:
- Child nodes conforming to I2C bus binding

Examples:
i2c0: i2c@70500000 {
	compatible = "sprd,sc9860-i2c";
	reg = <0 0x70500000 0 0x1000>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "i2c", "source", "enable";
	clocks = <&clk_i2c3>, <&ext_26m>, <&clk_ap_apb_gates 11>;
	clock-frequency = <400000>;
	#address-cells = <1>;
	#size-cells = <0>;
};


code:
ST SSC binding, for I2C mode operation

Required properties :
- compatible : Must be "st,comms-ssc-i2c" or "st,comms-ssc4-i2c"
- reg : Offset and length of the register set for the device
- interrupts : the interrupt specifier
- clock-names: Must contain "ssc".
- clocks: Must contain an entry for each name in clock-names. See the common
  clock bindings.
- A pinctrl state named "default" must be defined to set pins in mode of
  operation for I2C transfer.

Optional properties :
- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
  the default 100 kHz frequency will be used. As only Normal and Fast modes
  are supported, possible values are 100000 and 400000.
- st,i2c-min-scl-pulse-width-us : The minimum valid SCL pulse width that is
  allowed through the deglitch circuit. In units of us.
- st,i2c-min-sda-pulse-width-us : The minimum valid SDA pulse width that is
  allowed through the deglitch circuit. In units of us.
- A pinctrl state named "idle" could be defined to set pins in idle state
  when I2C instance is not performing a transfer.
- A pinctrl state named "sleep" could be defined to set pins in sleep state
  when driver enters in suspend.

Example :

i2c0: i2c@fed40000 {
	compatible	= "st,comms-ssc4-i2c";
	reg		= <0xfed40000 0x110>;
	interrupts	=  <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	clocks		= <&clk_s_a0_ls CLK_ICN_REG>;
	clock-names	= "ssc";
	clock-frequency = <400000>;
	pinctrl-names	= "default";
	pinctrl-0	= <&pinctrl_i2c0_default>;
	st,i2c-min-scl-pulse-width-us = <0>;
	st,i2c-min-sda-pulse-width-us = <5>;
};


code:
Socionext SynQuacer I2C

Required properties:
- compatible      : Must be "socionext,synquacer-i2c"
- reg             : Offset and length of the register set for the device
- interrupts      : A single interrupt specifier
- #address-cells  : Must be <1>;
- #size-cells     : Must be <0>;
- clock-names     : Must contain "pclk".
- clocks          : Must contain an entry for each name in clock-names.
                    (See the common clock bindings.)

Optional properties:
- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and
                    Fast modes are supported, possible values are 100000 and
                    400000.

Example :

    i2c@51210000 {
        compatible = "socionext,synquacer-i2c";
        reg = <0x51210000 0x1000>;
        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <0>;
        clock-names = "pclk";
        clocks = <&clk_i2c>;
        clock-frequency = <400000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-virtio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Virtio I2C Adapter

maintainers:
  - Viresh Kumar <viresh.kumar@linaro.org>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#
  - $ref: /schemas/virtio/virtio-device.yaml#

description:
  Virtio I2C device, see /schemas/virtio/virtio-device.yaml for more details.

properties:
  $nodename:
    const: i2c

  compatible:
    const: virtio,device22

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    virtio@3000 {
        compatible = "virtio,mmio";
        reg = <0x3000 0x100>;
        interrupts = <41>;

        i2c {
            compatible = "virtio,device22";

            #address-cells = <1>;
            #size-cells = <0>;

            light-sensor@20 {
                compatible = "dynaimage,al3320a";
                reg = <0x20>;
            };
        };
    };

...


code:
* Wondermedia I2C Controller

Required properties :

 - compatible : should be "wm,wm8505-i2c"
 - reg : Offset and length of the register set for the device
 - interrupts : <IRQ> where IRQ is the interrupt number
 - clocks : phandle to the I2C clock source

Optional properties :

 - clock-frequency : desired I2C bus clock frequency in Hz.
	Valid values are 100000 and 400000.
	Default to 100000 if not specified, or invalid value.

Example :

	i2c_0: i2c@d8280000 {
		compatible = "wm,wm8505-i2c";
		reg = <0xd8280000 0x1000>;
		interrupts = <19>;
		clocks = <&clki2c0>;
		clock-frequency = <400000>;
	};


code:
APM X-Gene SLIMpro Mailbox I2C Driver

An I2C controller accessed over the "SLIMpro" mailbox.

Required properties :

 - compatible : should be "apm,xgene-slimpro-i2c"
 - mboxes : use the label reference for the mailbox as the first parameter.
	    The second parameter is the channel number.

Example :
	i2cslimpro {
		compatible = "apm,xgene-slimpro-i2c";
		mboxes = <&mailbox 0>;
	};


code:
Generic device tree bindings for I2C busses
===========================================

This document describes generic bindings which can be used to describe I2C
busses and their child devices in a device tree.

Required properties (per bus)
-----------------------------

- #address-cells  - should be <1>. Read more about addresses below.
- #size-cells     - should be <0>.
- compatible      - name of I2C bus controller

For other required properties e.g. to describe register sets,
clocks, etc. check the binding documentation of the specific driver.

The cells properties above define that an address of children of an I2C bus
are described by a single value.

Optional properties (per bus)
-----------------------------

These properties may not be supported by all drivers. However, if a driver
wants to support one of the below features, it should adapt these bindings.

- clock-frequency
	frequency of bus clock in Hz.

- i2c-bus
	For I2C adapters that have child nodes that are a mixture of both I2C
	devices and non-I2C devices, the 'i2c-bus' subnode can be used for
	populating I2C devices. If the 'i2c-bus' subnode is present, only
	subnodes of this will be considered as I2C slaves. The properties,
	'#address-cells' and '#size-cells' must be defined under this subnode
	if present.

- i2c-scl-falling-time-ns
	Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C
	specification.

- i2c-scl-internal-delay-ns
	Number of nanoseconds the IP core additionally needs to setup SCL.

- i2c-scl-rising-time-ns
	Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C
	specification.

- i2c-sda-falling-time-ns
	Number of nanoseconds the SDA signal takes to fall; t(f) in the I2C
	specification.

- i2c-analog-filter
	Enable analog filter for i2c lines.

- i2c-digital-filter
	Enable digital filter for i2c lines.

- i2c-digital-filter-width-ns
	Width of spikes which can be filtered by digital filter
	(i2c-digital-filter). This width is specified in nanoseconds.

- i2c-analog-filter-cutoff-frequency
	Frequency that the analog filter (i2c-analog-filter) uses to distinguish
	which signal to filter. Signal with higher frequency than specified will
	be filtered out. Only lower frequency will pass (this is applicable to
	a low-pass analog filter). Typical value should be above the normal
	i2c bus clock frequency (clock-frequency).
	Specified in Hz.

- multi-master
	states that there is another master active on this bus. The OS can use
	this information to adapt power management to keep the arbitration awake
	all the time, for example. Can not be combined with 'single-master'.

- pinctrl
	add extra pinctrl to configure SCL/SDA pins to GPIO function for bus
	recovery, call it "gpio" or "recovery" (deprecated) state

- scl-gpios
	specify the gpio related to SCL pin. Used for GPIO bus recovery.

- sda-gpios
	specify the gpio related to SDA pin. Optional for GPIO bus recovery.

- single-master
	states that there is no other master active on this bus. The OS can use
	this information to detect a stalled bus more reliably, for example.
	Can not be combined with 'multi-master'.

- smbus
	states that additional SMBus restrictions and features apply to this bus.
	An example of feature is SMBusHostNotify. Examples of restrictions are
	more reserved addresses and timeout definitions.

- smbus-alert
	states that the optional SMBus-Alert feature apply to this bus.

- mctp-controller
	indicates that the system is accessible via this bus as an endpoint for
	MCTP over I2C transport.

Required properties (per child device)
--------------------------------------

- compatible
	name of I2C slave device

- reg
	One or many I2C slave addresses. These are usually a 7 bit addresses.
	However, flags can be attached to an address. I2C_TEN_BIT_ADDRESS is
	used to mark a 10 bit address. It is needed to avoid the ambiguity
	between e.g. a 7 bit address of 0x50 and a 10 bit address of 0x050
	which, in theory, can be on the same bus.
	Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we
	listen to be devices ourselves.

Optional properties (per child device)
--------------------------------------

These properties may not be supported by all drivers. However, if a driver
wants to support one of the below features, it should adapt these bindings.

- host-notify
	device uses SMBus host notify protocol instead of interrupt line.

- interrupts
	interrupts used by the device.

- interrupt-names
	"irq", "wakeup" and "smbus_alert" names are recognized by I2C core,
	other names are	left to individual drivers.

- reg-names
	Names of map programmable addresses.
	It can contain any map needing another address than default one.

- wakeup-source
	device can be used as a wakeup source.

Binding may contain optional "interrupts" property, describing interrupts
used by the device. I2C core will assign "irq" interrupt (or the very first
interrupt if not using interrupt names) as primary interrupt for the slave.

Alternatively, devices supporting SMBus Host Notify, and connected to
adapters that support this feature, may use "host-notify" property. I2C
core will create a virtual interrupt for Host Notify and assign it as
primary interrupt for the slave.

Also, if device is marked as a wakeup source, I2C core will set up "wakeup"
interrupt for the device. If "wakeup" interrupt name is not present in the
binding, then primary interrupt will be used as wakeup interrupt.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/ingenic,i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs I2C controller devicetree bindings

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

properties:
  $nodename:
    pattern: "^i2c@[0-9a-f]+$"

  compatible:
    oneOf:
      - enum:
          - ingenic,jz4770-i2c
          - ingenic,x1000-i2c
      - items:
          - const: ingenic,jz4780-i2c
          - const: ingenic,jz4770-i2c

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-frequency:
    enum: [ 100000, 400000 ]

  dmas:
    items:
      - description: DMA controller phandle and request line for RX
      - description: DMA controller phandle and request line for TX

  dma-names:
    items:
      - const: rx
      - const: tx

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-frequency
  - dmas
  - dma-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
    #include <dt-bindings/dma/jz4780-dma.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c@10054000 {
      compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
      #address-cells = <1>;
      #size-cells = <0>;
      reg = <0x10054000 0x1000>;

      interrupts = <56 IRQ_TYPE_LEVEL_LOW>;

      clocks = <&cgu JZ4780_CLK_SMB4>;
      pinctrl-names = "default";
      pinctrl-0 = <&pins_i2c4_data>;

      dmas = <&dma JZ4780_DMA_SMB4_RX 0xffffffff>,
             <&dma JZ4780_DMA_SMB4_TX 0xffffffff>;
      dma-names = "rx", "tx";

      clock-frequency = <400000>;

      rtc@51 {
        compatible = "nxp,pcf8563";
        reg = <0x51>;

        interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/marvell,mv64xxx-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell MV64XXX I2C Controller

maintainers:
  - Gregory CLEMENT <gregory.clement@bootlin.com>

properties:
  compatible:
    oneOf:
      - const: allwinner,sun4i-a10-i2c
      - items:
          - const: allwinner,sun7i-a20-i2c
          - const: allwinner,sun4i-a10-i2c
      - const: allwinner,sun6i-a31-i2c
      - items:
          - enum:
              - allwinner,suniv-f1c100s-i2c
              - allwinner,sun8i-a23-i2c
              - allwinner,sun8i-a83t-i2c
              - allwinner,sun8i-v536-i2c
              - allwinner,sun50i-a64-i2c
              - allwinner,sun50i-h6-i2c
          - const: allwinner,sun6i-a31-i2c
      - description: Allwinner SoCs with offload support
        items:
          - enum:
              - allwinner,sun20i-d1-i2c
              - allwinner,sun50i-a100-i2c
              - allwinner,sun50i-h616-i2c
              - allwinner,sun50i-r329-i2c
          - const: allwinner,sun8i-v536-i2c
          - const: allwinner,sun6i-a31-i2c
      - const: marvell,mv64xxx-i2c
      - const: marvell,mv78230-i2c
      - const: marvell,mv78230-a0-i2c

    description:
      Only use "marvell,mv78230-a0-i2c" for a very rare, initial
      version of the SoC which had broken offload support. Linux
      auto-detects this and sets it appropriately.

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: Reference clock for the I2C bus
      - description: Bus clock (Only for Armada 7K/8K)

  clock-names:
    minItems: 1
    items:
      - const: core
      - const: reg
    description:
      Mandatory if two clocks are used (only for Armada 7k and 8k).

  resets:
    maxItems: 1

  dmas:
    items:
      - description: RX DMA Channel
      - description: TX DMA Channel

  dma-names:
    items:
      - const: rx
      - const: tx

dependencies:
  dmas: [ dma-names ]

required:
  - compatible
  - reg
  - interrupts

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun4i-a10-i2c
              - allwinner,sun6i-a31-i2c

    then:
      required:
        - clocks

  - if:
      properties:
        compatible:
          contains:
            const: allwinner,sun6i-a31-i2c

    then:
      required:
        - resets

unevaluatedProperties: false

examples:
  - |
    i2c@11000 {
        compatible = "marvell,mv64xxx-i2c";
        reg = <0x11000 0x20>;
        interrupts = <29>;
        clock-frequency = <100000>;
    };

  - |
    i2c@11000 {
        compatible = "marvell,mv78230-i2c";
        reg = <0x11000 0x100>;
        interrupts = <29>;
        clock-frequency = <100000>;
    };

  - |
    i2c@701000 {
        compatible = "marvell,mv78230-i2c";
        reg = <0x701000 0x20>;
        interrupts = <29>;
        clock-frequency = <100000>;
        clock-names = "core", "reg";
        clocks = <&core_clock>, <&reg_clock>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/mediatek,mt7621-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

maintainers:
  - Stefan Roese <sr@denx.de>

title: Mediatek MT7621/MT7628 I2C master controller

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

properties:
  compatible:
    const: mediatek,mt7621-i2c

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: i2c

  resets:
    maxItems: 1

  reset-names:
    const: i2c

required:
  - compatible
  - reg
  - resets
  - "#address-cells"
  - "#size-cells"

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt7621-clk.h>
    #include <dt-bindings/reset/mt7621-reset.h>

    i2c: i2c@900 {
      compatible = "mediatek,mt7621-i2c";
      reg = <0x900 0x100>;
      clocks = <&sysc MT7621_CLK_I2C>;
      clock-names = "i2c";
      resets = <&sysc MT7621_RST_I2C>;
      reset-names = "i2c";

      #address-cells = <1>;
      #size-cells = <0>;

      pinctrl-names = "default";
      pinctrl-0 = <&i2c_pins>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/microchip,corei2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip MPFS I2C Controller

maintainers:
  - Daire McNamara <daire.mcnamara@microchip.com>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
          - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
      - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-frequency:
    description: |
      Desired I2C bus clock frequency in Hz. As only Standard and Fast
      modes are supported, possible values are 100000 and 400000.
    enum: [100000, 400000]

required:
  - compatible
  - reg
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    i2c@2010a000 {
      compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
      reg = <0x2010a000 0x1000>;
      clocks = <&clkcfg 15>;
      interrupt-parent = <&plic>;
      interrupts = <58>;
      clock-frequency = <100000>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: nuvoton NPCM7XX I2C Controller

description: |
  I2C bus controllers of the NPCM series support both master and
  slave mode. Each controller can switch between master and slave at run time
  (i.e. IPMB mode). HW FIFO for TX and RX are supported.

maintainers:
  - Tali Perry <tali.perry1@gmail.com>

properties:
  compatible:
    enum:
      - nuvoton,npcm750-i2c
      - nuvoton,npcm845-i2c

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1
    description: Reference clock for the I2C bus

  clock-frequency:
    description: Desired I2C bus clock frequency in Hz. If not specified,
                 the default 100 kHz frequency will be used.
                 possible values are 100000, 400000 and 1000000.
    default: 100000
    enum: [100000, 400000, 1000000]

  nuvoton,sys-mgr:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: The phandle of system manager register node.

required:
  - compatible
  - reg
  - interrupts
  - clocks

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: nuvoton,npcm845-i2c

    then:
      required:
        - nuvoton,sys-mgr

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    i2c0: i2c@80000 {
        reg = <0x80000 0x1000>;
        clocks = <&clk NPCM7XX_CLK_APB2>;
        clock-frequency = <100000>;
        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
        compatible = "nuvoton,npcm750-i2c";
        nuvoton,sys-mgr = <&gcr>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra186 (and later) BPMP I2C controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: |
  In Tegra186 and later, the BPMP (Boot and Power Management Processor)
  owns certain HW devices, such as the I2C controller for the power
  management I2C bus. Software running on other CPUs must perform IPC to
  the BPMP in order to execute transactions on that I2C bus. This
  binding describes an I2C bus that is accessed in such a fashion.

  The BPMP I2C node must be located directly inside the main BPMP node.
  See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
  binding.

  This node represents an I2C controller. See ../i2c/i2c.txt for details
  of the core I2C binding.

properties:
  compatible:
    const: nvidia,tegra186-bpmp-i2c

  nvidia,bpmp-bus-id:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Indicates the I2C bus number this DT node represents,
      as defined by the BPMP firmware.

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml

unevaluatedProperties: false

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - nvidia,bpmp-bus-id


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

title: NVIDIA Tegra I2C controller driver

properties:
  compatible:
    oneOf:
      - description: Tegra20 has 4 generic I2C controller. This can support
          master and slave mode of I2C communication. The i2c-tegra driver
          only support master mode of I2C communication. Driver of I2C
          controller is only compatible with "nvidia,tegra20-i2c".
        const: nvidia,tegra20-i2c
      - description: Tegra20 has specific I2C controller called as DVC I2C
          controller. This only support master mode of I2C communication.
          Register interface/offset and interrupts handling are different than
          generic I2C controller. Driver of DVC I2C controller is only
          compatible with "nvidia,tegra20-i2c-dvc".
        const: nvidia,tegra20-i2c-dvc
      - description: |
          Tegra30 has 5 generic I2C controller. This controller is very much
          similar to Tegra20 I2C controller with additional feature: Continue
          Transfer Support. This feature helps to implement M_NO_START as per
          I2C core API transfer flags. Driver of I2C controller is compatible
          with "nvidia,tegra30-i2c" to enable the continue transfer support.
          This is also compatible with "nvidia,tegra20-i2c" without continue
          transfer support.
        items:
          - const: nvidia,tegra30-i2c
          - const: nvidia,tegra20-i2c
      - description: |
          Tegra114 has 5 generic I2C controllers. This controller is very much
          similar to Tegra30 I2C controller with some hardware modification:
            - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk
              and fast-clk. Tegra114 has only one clock source called as
              div-clk and hence clock mechanism is changed in I2C controller.
            - Tegra30/Tegra20 I2C controller has enabled per packet transfer
              by default and there is no way to disable it. Tegra114 has this
              interrupt disable by default and SW need to enable explicitly.
          Due to above changes, Tegra114 I2C driver makes incompatible with
          previous hardware driver. Hence, Tegra114 I2C controller is
          compatible with "nvidia,tegra114-i2c".
        const: nvidia,tegra114-i2c
      - description: |
          Tegra124 has 6 generic I2C controllers. These controllers are very
          similar to those found on Tegra114 but also contain several hardware
          improvements and new registers.
        const: nvidia,tegra124-i2c
      - description: |
          Tegra210 has 6 generic I2C controllers. These controllers are very
          similar to those found on Tegra124.
        items:
          - const: nvidia,tegra210-i2c
          - const: nvidia,tegra124-i2c
      - description: |
          Tegra210 has one I2C controller that is on host1x bus and is part of
          the VE power domain and typically used for camera use-cases. This VI
          I2C controller is mostly compatible with the programming model of
          the regular I2C controllers with a few exceptions. The I2C registers
          start at an offset of 0xc00 (instead of 0), registers are 16 bytes
          apart (rather than 4) and the controller does not support slave
          mode.
        const: nvidia,tegra210-i2c-vi
      - description: |
          Tegra186 has 9 generic I2C controllers, two of which are in the AON
          (always-on) partition of the SoC. All of these controllers are very
          similar to those found on Tegra210.
        const: nvidia,tegra186-i2c
      - description: |
          Tegra194 has 8 generic I2C controllers, two of which are in the AON
          (always-on) partition of the SoC. All of these controllers are very
          similar to those found on Tegra186. However, these controllers have
          support for 64 KiB transactions whereas earlier chips supported no
          more than 4 KiB per transactions.
        const: nvidia,tegra194-i2c

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    maxItems: 2

  resets:
    items:
      - description: module reset

  reset-names:
    items:
      - const: i2c

  dmas:
    items:
      - description: DMA channel for the reception FIFO
      - description: DMA channel for the transmission FIFO

  dma-names:
    items:
      - const: rx
      - const: tx

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra20-i2c
              - nvidia,tegra30-i2c
    then:
      properties:
        clock-names:
          items:
            - const: div-clk
            - const: fast-clk

  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra114-i2c
    then:
      properties:
        clock-names:
          items:
            - const: div-clk

  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra210-i2c
    then:
      properties:
        clock-names:
          items:
            - const: div-clk

  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra210-i2c-vi
    then:
      properties:
        clock-names:
          items:
            - const: div-clk
            - const: slow
        power-domains:
          items:
            - description: phandle to the VENC power domain

unevaluatedProperties: false

examples:
  - |
    i2c@7000c000 {
        compatible = "nvidia,tegra20-i2c";
        reg = <0x7000c000 0x100>;
        interrupts = <0 38 0x04>;
        clocks = <&tegra_car 12>, <&tegra_car 124>;
        clock-names = "div-clk", "fast-clk";
        resets = <&tegra_car 12>;
        reset-names = "i2c";
        dmas = <&apbdma 16>, <&apbdma 16>;
        dma-names = "rx", "tx";

        #address-cells = <1>;
        #size-cells = <0>;
    };


code:
* NXP PCA9541 I2C bus master selector

Required Properties:

  - compatible: Must be "nxp,pca9541"

  - reg: The I2C address of the device.

  The following required properties are defined externally:

  - I2C arbitration bus node. See i2c-arb.txt in this directory.

Example:

	i2c-arbitrator@74 {
		compatible = "nxp,pca9541";
		reg = <0x74>;

		i2c-arb {
			#address-cells = <1>;
			#size-cells = <0>;

			eeprom@54 {
				compatible = "atmel,24c08";
				reg = <0x54>;
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: OpenCores I2C controller

maintainers:
  - Peter Korsgaard <peter@korsgaard.com>
  - Andrew Lunn <andrew@lunn.ch>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
              - sifive,fu540-c000-i2c # Opencore based IP block FU540-C000 SoC
          - const: sifive,i2c0
      - enum:
          - opencores,i2c-ocores
          - aeroflexgaisler,i2cmst

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-frequency:
    description: |
      clock-frequency property is meant to control the bus frequency for i2c bus
      drivers, but it was incorrectly used to specify i2c controller input clock
      frequency. So the following rules are set to fix this situation:
      - if clock-frequency is present and neither opencores,ip-clock-frequency nor
        clocks are, then clock-frequency specifies i2c controller clock frequency.
        This is to keep backwards compatibility with setups using old DTB. i2c bus
        frequency is fixed at 100 KHz.
      - if clocks is present it specifies i2c controller clock. clock-frequency
        property specifies i2c bus frequency.
      - if opencores,ip-clock-frequency is present it specifies i2c controller
        clock frequency. clock-frequency property specifies i2c bus frequency.
    default: 100000

  reg-io-width:
    description: |
      io register width in bytes
    enum: [1, 2, 4]

  reg-shift:
    description: |
      device register offsets are shifted by this value
    default: 0

  regstep:
    description: |
      deprecated, use reg-shift above
    deprecated: true

  opencores,ip-clock-frequency:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Frequency of the controller clock in Hz. Mutually exclusive with clocks.
      See the note above.

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"

oneOf:
  - required:
      - opencores,ip-clock-frequency
  - required:
      - clocks

unevaluatedProperties: false

examples:
  - |
    i2c@a0000000 {
      compatible = "opencores,i2c-ocores";
      reg = <0xa0000000 0x8>;
      #address-cells = <1>;
      #size-cells = <0>;
      interrupts = <10>;
      opencores,ip-clock-frequency = <20000000>;

      reg-shift = <0>;	/* 8 bit registers */
      reg-io-width = <1>;	/* 8 bit read/write */
    };

    i2c@b0000000 {
      compatible = "opencores,i2c-ocores";
      reg = <0xa0000000 0x8>;
      #address-cells = <1>;
      #size-cells = <0>;
      interrupts = <10>;
      clocks = <&osc>;
      clock-frequency = <400000>; /* i2c bus frequency 400 KHz */

      reg-shift = <0>;	/* 8 bit registers */
      reg-io-width = <1>;	/* 8 bit read/write */
    };
...


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Camera Control Interface (CCI) I2C controller

maintainers:
  - Loic Poulain <loic.poulain@linaro.org>
  - Robert Foss <robert.foss@linaro.org>

properties:
  compatible:
    enum:
      - qcom,msm8226-cci
      - qcom,msm8916-cci
      - qcom,msm8974-cci
      - qcom,msm8996-cci
      - qcom,sdm845-cci
      - qcom,sm8250-cci
      - qcom,sm8450-cci

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  clocks:
    minItems: 3
    maxItems: 6

  clock-names:
    minItems: 3
    maxItems: 6

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

patternProperties:
  "^i2c-bus@[01]$":
    $ref: /schemas/i2c/i2c-controller.yaml#
    unevaluatedProperties: false

    properties:
      reg:
        maxItems: 1

      clock-frequency:
        default: 100000

required:
  - compatible
  - clock-names
  - clocks
  - interrupts
  - reg

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8996-cci
    then:
      required:
        - power-domains

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8226-cci
              - qcom,msm8916-cci
    then:
      properties:
        i2c-bus@1: false

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8226-cci
              - qcom,msm8974-cci
    then:
      properties:
        clocks:
          maxItems: 3
        clock-names:
          items:
            - const: camss_top_ahb
            - const: cci_ahb
            - const: cci

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8916-cci
              - qcom,msm8996-cci
    then:
      properties:
        clocks:
          maxItems: 4
        clock-names:
          items:
            - const: camss_top_ahb
            - const: cci_ahb
            - const: cci
            - const: camss_ahb

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdm845-cci
    then:
      properties:
        clocks:
          minItems: 6
        clock-names:
          items:
            - const: camnoc_axi
            - const: soc_ahb
            - const: slow_ahb_src
            - const: cpas_ahb
            - const: cci
            - const: cci_src

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sm8250-cci
              - qcom,sm8450-cci
    then:
      properties:
        clocks:
          minItems: 5
          maxItems: 5
        clock-names:
          items:
            - const: camnoc_axi
            - const: slow_ahb_src
            - const: cpas_ahb
            - const: cci
            - const: cci_src

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,camcc-sdm845.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    cci@ac4a000 {
        reg = <0x0ac4a000 0x4000>;
        compatible = "qcom,sdm845-cci";
        #address-cells = <1>;
        #size-cells = <0>;

        interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
        power-domains = <&clock_camcc TITAN_TOP_GDSC>;

        clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
                 <&clock_camcc CAM_CC_CCI_CLK>,
                 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
        clock-names = "camnoc_axi",
                      "soc_ahb",
                      "slow_ahb_src",
                      "cpas_ahb",
                      "cci",
                      "cci_src";

        assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
                          <&clock_camcc CAM_CC_CCI_CLK>;
        assigned-clock-rates = <80000000>,
                               <37500000>;

        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&cci0_default &cci1_default>;
        pinctrl-1 = <&cci0_sleep &cci1_sleep>;

        i2c-bus@0 {
            reg = <0>;
            clock-frequency = <1000000>;
            #address-cells = <1>;
            #size-cells = <0>;

            camera@10 {
                compatible = "ovti,ov8856";
                reg = <0x10>;

                reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
                pinctrl-names = "default";
                pinctrl-0 = <&cam0_default>;

                clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
                clock-names = "xvclk";
                clock-frequency = <19200000>;

                dovdd-supply = <&vreg_lvs1a_1p8>;
                avdd-supply = <&cam0_avdd_2v8>;
                dvdd-supply = <&cam0_dvdd_1v2>;

                port {
                    ov8856_ep: endpoint {
                        link-frequencies = /bits/ 64 <360000000 180000000>;
                        data-lanes = <1 2 3 4>;
                        remote-endpoint = <&csiphy0_ep>;
                    };
                };
            };
        };

        cci_i2c1: i2c-bus@1 {
            reg = <1>;
            clock-frequency = <1000000>;
            #address-cells = <1>;
            #size-cells = <0>;

            camera@60 {
                compatible = "ovti,ov7251";
                reg = <0x60>;

                enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
                pinctrl-names = "default";
                pinctrl-0 = <&cam3_default>;

                clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
                clock-names = "xclk";
                clock-frequency = <24000000>;

                vdddo-supply = <&vreg_lvs1a_1p8>;
                vdda-supply = <&cam3_avdd_2v8>;

                port {
                    ov7251_ep: endpoint {
                        data-lanes = <0 1>;
                        remote-endpoint = <&csiphy3_ep>;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/i2c/qcom,i2c-geni-qcom.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Geni based QUP I2C Controller

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>

properties:
  compatible:
    enum:
      - qcom,geni-i2c
      - qcom,geni-i2c-master-hub

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    maxItems: 2

  clock-frequency:
    default: 100000

  dmas:
    maxItems: 2

  dma-names:
    items:
      - const: tx
      - const: rx

  interconnects:
    minItems: 2
    maxItems: 3

  interconnect-names:
    minItems: 2
    maxItems: 3

  interrupts:
    maxItems: 1

  pinctrl-0: true
  pinctrl-1: true

  pinctrl-names:
    minItems: 1
    items:
      - const: default
      - const: sleep

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

  required-opps:
    maxItems: 1

required:
  - compatible
  - interrupts
  - clocks
  - clock-names
  - reg

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: qcom,geni-i2c-master-hub
    then:
      properties:
        clocks:
          minItems: 2

        clock-names:
          items:
            - const: se
            - const: core

        dmas: false
        dma-names: false

        interconnects:
          maxItems: 2

        interconnect-names:
          items:
            - const: qup-core
            - const: qup-config
    else:
      properties:
        clocks:
          maxItems: 1

        clock-names:
          const: se

        interconnects:
          minItems: 3

        interconnect-names:
          items:
            - const: qup-core
            - const: qup-config
            - const: qup-memory

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
    #include <dt-bindings/interconnect/qcom,sc7180.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    i2c@88000 {
        compatible = "qcom,geni-i2c";
        reg = <0x00880000 0x4000>;
        clock-names = "se";
        clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
        pinctrl-names = "default";
        pinctrl-0 = <&qup_i2c0_default>;
        interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <0>;
        interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
                        <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
        interconnect-names = "qup-core", "qup-config", "qup-memory";
        power-domains = <&rpmhpd SC7180_CX>;
        required-opps = <&rpmhpd_opp_low_svs>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/qcom,i2c-qup.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Universal Peripheral (QUP) I2C controller

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

properties:
  compatible:
    enum:
      - qcom,i2c-qup-v1.1.1     # for 8660, 8960 and 8064
      - qcom,i2c-qup-v2.1.1     # for 8974 v1
      - qcom,i2c-qup-v2.2.1     # for 8974 v2 and later

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: core
      - const: iface

  clock-frequency:
    default: 100000

  dmas:
    maxItems: 2

  dma-names:
    items:
      - const: tx
      - const: rx

  interrupts:
    maxItems: 1

  pinctrl-0: true
  pinctrl-1: true

  pinctrl-names:
    minItems: 1
    items:
      - const: default
      - const: sleep

  reg:
    maxItems: 1

required:
  - compatible
  - clock-names
  - clocks
  - interrupts
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8998.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    i2c@c175000 {
        compatible = "qcom,i2c-qup-v2.2.1";
        reg = <0x0c175000 0x600>;
        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
                 <&gcc GCC_BLSP1_AHB_CLK>;
        clock-names = "core", "iface";
        dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
        dma-names = "tx", "rx";
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&blsp1_i2c1_default>;
        pinctrl-1 = <&blsp1_i2c1_sleep>;
        clock-frequency = <400000>;

        #address-cells = <1>;
        #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/renesas,iic-emev2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas EMMA Mobile EV2 IIC Interface

maintainers:
  - Wolfram Sang <wsa+renesas@sang-engineering.com>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

properties:
  compatible:
    const: renesas,iic-emev2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: sclk

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - '#address-cells'
  - '#size-cells'

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    iic0: i2c@e0070000 {
            #address-cells = <1>;
            #size-cells = <0>;
            compatible = "renesas,iic-emev2";
            reg = <0xe0070000 0x28>;
            interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
            clocks = <&iic0_sclk>;
            clock-names = "sclk";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/renesas,rcar-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car I2C Controller

maintainers:
  - Wolfram Sang <wsa+renesas@sang-engineering.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,i2c-r8a7778      # R-Car M1A
              - renesas,i2c-r8a7779      # R-Car H1
          - const: renesas,rcar-gen1-i2c # R-Car Gen1

      - items:
          - enum:
              - renesas,i2c-r8a7742      # RZ/G1H
              - renesas,i2c-r8a7743      # RZ/G1M
              - renesas,i2c-r8a7744      # RZ/G1N
              - renesas,i2c-r8a7745      # RZ/G1E
              - renesas,i2c-r8a77470     # RZ/G1C
              - renesas,i2c-r8a7790      # R-Car H2
              - renesas,i2c-r8a7791      # R-Car M2-W
              - renesas,i2c-r8a7792      # R-Car V2H
              - renesas,i2c-r8a7793      # R-Car M2-N
              - renesas,i2c-r8a7794      # R-Car E2
          - const: renesas,rcar-gen2-i2c # R-Car Gen2 and RZ/G1

      - items:
          - enum:
              - renesas,i2c-r8a774a1     # RZ/G2M
              - renesas,i2c-r8a774b1     # RZ/G2N
              - renesas,i2c-r8a774c0     # RZ/G2E
              - renesas,i2c-r8a774e1     # RZ/G2H
              - renesas,i2c-r8a7795      # R-Car H3
              - renesas,i2c-r8a7796      # R-Car M3-W
              - renesas,i2c-r8a77961     # R-Car M3-W+
              - renesas,i2c-r8a77965     # R-Car M3-N
              - renesas,i2c-r8a77970     # R-Car V3M
              - renesas,i2c-r8a77980     # R-Car V3H
              - renesas,i2c-r8a77990     # R-Car E3
              - renesas,i2c-r8a77995     # R-Car D3
          - const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G2

      - items:
          - enum:
              - renesas,i2c-r8a779a0     # R-Car V3U
              - renesas,i2c-r8a779f0     # R-Car S4-8
              - renesas,i2c-r8a779g0     # R-Car V4H
          - const: renesas,rcar-gen4-i2c # R-Car Gen4

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clock-frequency:
    description:
      Desired I2C bus clock frequency in Hz. The absence of this property
      indicates the default frequency 100 kHz.

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  dmas:
    minItems: 2
    maxItems: 4
    description:
      Must contain a list of pairs of references to DMA specifiers, one for
      transmission, and one for reception.

  dma-names:
    minItems: 2
    maxItems: 4
    items:
      enum:
        - tx
        - rx

  i2c-scl-falling-time-ns:
    default: 35
    description:
      Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C
      specification.

  i2c-scl-internal-delay-ns:
    default: 50
    description:
      Number of nanoseconds the IP core additionally needs to setup SCL.

  i2c-scl-rising-time-ns:
    default: 200
    description:
      Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C
      specification.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains
  - '#address-cells'
  - '#size-cells'

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,rcar-gen1-i2c
              - renesas,rcar-gen2-i2c
    then:
      properties:
        dmas: false
        dma-names: false

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,rcar-gen2-i2c
              - renesas,rcar-gen3-i2c
              - renesas,rcar-gen4-i2c
    then:
      required:
        - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7791-sysc.h>

    i2c0: i2c@e6508000 {
            #address-cells = <1>;
            #size-cells = <0>;
            compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
            reg = <0xe6508000 0x40>;
            interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
            clock-frequency = <400000>;
            clocks = <&cpg CPG_MOD 931>;
            power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
            resets = <&cpg 931>;
            i2c-scl-internal-delay-ns = <6>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/renesas,riic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/A and RZ/G2L I2C Bus Interface (RIIC)

maintainers:
  - Chris Brandt <chris.brandt@renesas.com>
  - Wolfram Sang <wsa+renesas@sang-engineering.com>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - renesas,riic-r7s72100   # RZ/A1H
          - renesas,riic-r7s9210    # RZ/A2M
          - renesas,riic-r9a07g043  # RZ/G2UL and RZ/Five
          - renesas,riic-r9a07g044  # RZ/G2{L,LC}
          - renesas,riic-r9a07g054  # RZ/V2L
      - const: renesas,riic-rz      # RZ/A or RZ/G2L

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: Transmit End Interrupt
      - description: Receive Data Full Interrupt
      - description: Transmit Data Empty Interrupt
      - description: Stop Condition Detection Interrupt
      - description: Start Condition Detection Interrupt
      - description: NACK Reception Interrupt
      - description: Arbitration-Lost Interrupt
      - description: Timeout Interrupt

  interrupt-names:
    items:
      - const: tei
      - const: ri
      - const: ti
      - const: spi
      - const: sti
      - const: naki
      - const: ali
      - const: tmoi

  clock-frequency:
    description:
      Desired I2C bus clock frequency in Hz. The absence of this property
      indicates the default frequency 100 kHz.

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-frequency
  - power-domains
  - '#address-cells'
  - '#size-cells'

if:
  properties:
    compatible:
      contains:
        enum:
          - renesas,riic-r9a07g043
          - renesas,riic-r9a07g044
          - renesas,riic-r9a07g054
then:
  required:
    - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r7s72100-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    i2c0: i2c@fcfee000 {
            compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
            reg = <0xfcfee000 0x44>;
            interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali",
                              "tmoi";
            clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
            clock-frequency = <100000>;
            power-domains = <&cpg_clocks>;
            #address-cells = <1>;
            #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/renesas,rmobile-iic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Mobile I2C Bus Interface (IIC)

maintainers:
  - Wolfram Sang <wsa+renesas@sang-engineering.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,iic-r8a73a4      # R-Mobile APE6
              - renesas,iic-r8a7740      # R-Mobile A1
              - renesas,iic-sh73a0       # SH-Mobile AG5
          - const: renesas,rmobile-iic   # Generic

      - items:
          - enum:
              - renesas,iic-r8a7742      # RZ/G1H
              - renesas,iic-r8a7743      # RZ/G1M
              - renesas,iic-r8a7744      # RZ/G1N
              - renesas,iic-r8a7745      # RZ/G1E
              - renesas,iic-r8a7790      # R-Car H2
              - renesas,iic-r8a7791      # R-Car M2-W
              - renesas,iic-r8a7792      # R-Car V2H
              - renesas,iic-r8a7793      # R-Car M2-N
              - renesas,iic-r8a7794      # R-Car E2
          - const: renesas,rcar-gen2-iic # R-Car Gen2 and RZ/G1
          - const: renesas,rmobile-iic   # Generic

      - items:
          - enum:
              - renesas,iic-r8a774a1     # RZ/G2M
              - renesas,iic-r8a774b1     # RZ/G2N
              - renesas,iic-r8a774c0     # RZ/G2E
              - renesas,iic-r8a774e1     # RZ/G2H
              - renesas,iic-r8a7795      # R-Car H3
              - renesas,iic-r8a7796      # R-Car M3-W
              - renesas,iic-r8a77961     # R-Car M3-W+
              - renesas,iic-r8a77965     # R-Car M3-N
              - renesas,iic-r8a77990     # R-Car E3
          - const: renesas,rcar-gen3-iic # R-Car Gen3 and RZ/G2
          - const: renesas,rmobile-iic   # Generic

  reg:
    maxItems: 1

  interrupts: true

  clock-frequency:
    description:
      Desired I2C bus clock frequency in Hz. The absence of this property
      indicates the default frequency 100 kHz.

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  dmas:
    minItems: 2
    maxItems: 4
    description:
      Must contain a list of pairs of references to DMA specifiers, one for
      transmission, and one for reception.

  dma-names:
    minItems: 2
    maxItems: 4
    items:
      enum:
        - tx
        - rx

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains
  - '#address-cells'
  - '#size-cells'

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,iic-r8a7740
              - renesas,iic-sh73a0
    then:
      properties:
        interrupts:
          items:
            - description: Arbitration Lost Interrupt (ALI)
            - description: Non-acknowledge Detection Interrupt (TACKI)
            - description: Wait Interrupt (WAITI)
            - description: Data Transmit Enable interrupt (DTEI)
    else:
      properties:
        interrupts:
          items:
            - description: Single combined interrupt

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,rcar-gen2-iic
              - renesas,rcar-gen3-iic
    then:
      required:
        - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>

    iic0: i2c@e6500000 {
            compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
                         "renesas,rmobile-iic";
            reg = <0xe6500000 0x425>;
            interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 318>;
            clock-frequency = <400000>;
            dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>;
            dma-names = "tx", "rx", "tx", "rx";
            power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
            resets = <&cpg 318>;
            #address-cells = <1>;
            #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/renesas,rzv2m.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/V2M I2C Bus Interface

maintainers:
  - Phil Edworthy <phil.edworthy@renesas.com>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - renesas,i2c-r9a09g011  # RZ/V2M
      - const: renesas,rzv2m-i2c

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: Data transmission/reception interrupt
      - description: Status interrupt

  interrupt-names:
    items:
      - const: tia
      - const: tis

  clock-frequency:
    default: 100000
    enum: [ 100000, 400000 ]
    description:
      Desired I2C bus clock frequency in Hz.

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - power-domains
  - resets
  - '#address-cells'
  - '#size-cells'

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r9a09g011-cpg.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    i2c0: i2c@a4030000 {
        compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c";
        reg = <0xa4030000 0x80>;
        interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
        interrupt-names = "tia", "tis";
        clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>;
        resets = <&cpg R9A09G011_IIC_GPA_PRESETN>;
        power-domains = <&cpg>;
        clock-frequency = <100000>;
        #address-cells = <1>;
        #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/samsung,s3c2410-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S3C/S5P/Exynos SoC I2C Controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - samsung,s3c2410-i2c
      - samsung,s3c2440-i2c
        # For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
      - samsung,s3c2440-hdmiphy-i2c
        # For s3c2440-like I2C used as a host to SATA PHY controller on an
        # internal bus:
      - samsung,exynos5-sata-phy-i2c

  '#address-cells':
    const: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: i2c

  gpios:
    description: |
      The order of the GPIOs should be the following:: <SDA, SCL>.  The GPIO
      specifier depends on the gpio controller. Required in all cases except
      for "samsung,s3c2440-hdmiphy-i2c" whose input/output lines are
      permanently wired to the respective client.
      This property is deprecated. Use "pinctrl-0" and "pinctrl-names" instead.
    deprecated: yes

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

  samsung,i2c-max-bus-freq:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Desired frequency in Hz of the bus.
    default: 100000

  samsung,i2c-sda-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Delay (in ns) applied to data line (SDA) edges.
    default: 0

  samsung,i2c-slave-addr:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Slave address in multi-master environment.
    default: 0

  samsung,sysreg-phandle:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: Pandle to syscon used to control the system registers.

  '#size-cells':
    const: 0

required:
  - compatible
  - reg

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,s3c2440-hdmiphy-i2c
              - samsung,exynos5-sata-phy-i2c
    then:
      properties:
        gpios: false

  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,s3c2410-i2c
              - samsung,s3c2440-i2c
              - samsung,s3c2440-hdmiphy-i2c
    then:
      required:
        - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5250.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    i2c@12c60000 {
        compatible = "samsung,s3c2440-i2c";
        reg = <0x12C60000 0x100>;
        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&clock CLK_I2C0>;
        clock-names = "i2c";
        pinctrl-names = "default";
        pinctrl-0 = <&i2c0_bus>;

        samsung,sysreg-phandle = <&sysreg_system_controller>;
        samsung,i2c-sda-delay = <100>;
        samsung,i2c-max-bus-freq = <20000>;
        samsung,i2c-slave-addr = <0x66>;

        eeprom@50 {
            compatible = "samsung,s524ad0xd1", "atmel,24c128";
            reg = <0x50>;
        };
    };

    i2c@12ce0000 {
        compatible = "samsung,s3c2440-hdmiphy-i2c";
        reg = <0x12CE0000 0x1000>;
        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&clock CLK_I2C_HDMI>;
        clock-names = "i2c";

        samsung,i2c-sda-delay = <100>;
        samsung,i2c-max-bus-freq = <66000>;

        phy-i2c@38 {
            compatible = "samsung,exynos4212-hdmiphy";
            reg = <0x38>;
        };
    };

    i2c@121d0000 {
        compatible = "samsung,exynos5-sata-phy-i2c";
        reg = <0x121D0000 0x100>;
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&clock CLK_SATA_PHYI2C>;
        clock-names = "i2c";

        samsung,i2c-sda-delay = <100>;
        samsung,i2c-max-bus-freq = <40000>;

        phy-i2c@38 {
            compatible = "samsung,exynos-sataphy-i2c";
            reg = <0x38>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare APB I2C Controller

maintainers:
  - Jarkko Nikula <jarkko.nikula@linux.intel.com>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#
  - if:
      properties:
        compatible:
          not:
            contains:
              const: mscc,ocelot-i2c
    then:
      properties:
        reg:
          maxItems: 1

properties:
  compatible:
    oneOf:
      - description: Generic Synopsys DesignWare I2C controller
        const: snps,designware-i2c
      - description: Microsemi Ocelot SoCs I2C controller
        items:
          - const: mscc,ocelot-i2c
          - const: snps,designware-i2c
      - description: Baikal-T1 SoC System I2C controller
        const: baikal,bt1-sys-i2c

  reg:
    minItems: 1
    items:
      - description: DW APB I2C controller memory mapped registers
      - description: |
          ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.
          This registers are specific to the Ocelot I2C-controller.

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: I2C controller reference clock source
      - description: APB interface clock source

  clock-names:
    minItems: 1
    items:
      - const: ref
      - const: pclk

  resets:
    maxItems: 1

  clock-frequency:
    description: Desired I2C bus clock frequency in Hz
    enum: [100000, 400000, 1000000, 3400000]
    default: 400000

  i2c-sda-hold-time-ns:
    description: |
      The property should contain the SDA hold time in nanoseconds. This option
      is only supported in hardware blocks version 1.11a or newer or on
      Microsemi SoCs.

  i2c-scl-falling-time-ns:
    description: |
      The property should contain the SCL falling time in nanoseconds.
      This value is used to compute the tLOW period.
    default: 300

  i2c-sda-falling-time-ns:
    description: |
      The property should contain the SDA falling time in nanoseconds.
      This value is used to compute the tHIGH period.
    default: 300

  dmas:
    items:
      - description: TX DMA Channel
      - description: RX DMA Channel

  dma-names:
    items:
      - const: tx
      - const: rx

unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts

examples:
  - |
    i2c@f0000 {
      compatible = "snps,designware-i2c";
      reg = <0xf0000 0x1000>;
      interrupts = <11>;
      clock-frequency = <400000>;
    };
  - |
    i2c@1120000 {
      compatible = "snps,designware-i2c";
      reg = <0x1120000 0x1000>;
      interrupts = <12 1>;
      clock-frequency = <400000>;
      i2c-sda-hold-time-ns = <300>;
      i2c-sda-falling-time-ns = <300>;
      i2c-scl-falling-time-ns = <300>;
    };
  - |
    i2c@2000 {
      compatible = "snps,designware-i2c";
      reg = <0x2000 0x100>;
      #address-cells = <1>;
      #size-cells = <0>;
      clock-frequency = <400000>;
      clocks = <&i2cclk>;
      interrupts = <0>;

      eeprom@64 {
        compatible = "atmel,24c02";
        reg = <0x64>;
      };
    };
  - |
    i2c@100400 {
      compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
      reg = <0x100400 0x100>, <0x198 0x8>;
      pinctrl-0 = <&i2c_pins>;
      pinctrl-names = "default";
      interrupts = <8>;
      clocks = <&ahb_clk>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/socionext,uniphier-fi2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UniPhier I2C controller (FIFO-builtin)

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

properties:
  compatible:
    const: socionext,uniphier-fi2c

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-frequency:
    minimum: 100000
    maximum: 400000

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    i2c0: i2c@58780000 {
        compatible = "socionext,uniphier-fi2c";
        reg = <0x58780000 0x80>;
        #address-cells = <1>;
        #size-cells = <0>;
        interrupts = <0 41 4>;
        clocks = <&i2c_clk>;
        clock-frequency = <100000>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/socionext,uniphier-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UniPhier I2C controller (FIFO-less)

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

properties:
  compatible:
    const: socionext,uniphier-i2c

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-frequency:
    minimum: 100000
    maximum: 400000

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    i2c0: i2c@58400000 {
        compatible = "socionext,uniphier-i2c";
        reg = <0x58400000 0x40>;
        #address-cells = <1>;
        #size-cells = <0>;
        interrupts = <0 41 1>;
        clocks = <&i2c_clk>;
        clock-frequency = <100000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/st,nomadik-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ST Microelectronics Nomadik I2C Bindings

description: The Nomadik I2C host controller began its life in the ST
  Microelectronics STn8800 SoC, and was then inherited into STn8810 and
  STn8815. It was part of the prototype STn8500 which then became ST-Ericsson
  DB8500 after the merge of these two companies wireless divisions.

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
  properties:
    compatible:
      contains:
        enum:
          - st,nomadik-i2c
  required:
    - compatible

properties:
  compatible:
    oneOf:
      # The variant found in STn8815
      - items:
          - const: st,nomadik-i2c
          - const: arm,primecell
      # The variant found in DB8500
      - items:
          - const: stericsson,db8500-i2c
          - const: st,nomadik-i2c
          - const: arm,primecell

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    oneOf:
      # Clock name in STn8815
      - items:
          - const: mclk
          - const: apb_pclk
      # Clock name in DB8500
      - items:
          - const: i2cclk
          - const: apb_pclk

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  clock-frequency:
    minimum: 1
    maximum: 400000

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
    #include <dt-bindings/arm/ux500_pm_domains.h>
    i2c@80004000 {
      compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
      reg = <0x80004000 0x1000>;
      interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

      #address-cells = <1>;
      #size-cells = <0>;

      clock-frequency = <400000>;
      clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
      clock-names = "i2cclk", "apb_pclk";
      power-domains = <&pm_domains DOMAIN_VAPE>;
      resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>;
    };

    i2c@101f8000 {
      compatible = "st,nomadik-i2c", "arm,primecell";
      reg = <0x101f8000 0x1000>;
      interrupt-parent = <&vica>;
      interrupts = <20>;
      clock-frequency = <100000>;
      #address-cells = <1>;
      #size-cells = <0>;
      clocks = <&i2c0clk>, <&pclki2c0>;
      clock-names = "mclk", "apb_pclk";
    };

...