code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 * Copyright 2019-2020 Variscite Ltd.
 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
 */

#include "imx8mn.dtsi"

/ {
	model = "Variscite VAR-SOM-MX8MN module";
	compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";

	chosen {
		stdout-path = &uart4;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x40000000>;
	};

	reg_eth_phy: regulator-eth-phy {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_eth_phy>;
		regulator-name = "eth_phy_pwr";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&A53_1 {
	cpu-supply = <&buck2_reg>;
};

&A53_2 {
	cpu-supply = <&buck2_reg>;
};

&A53_3 {
	cpu-supply = <&buck2_reg>;
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
		   <&gpio1  0 GPIO_ACTIVE_LOW>;
	/delete-property/ dmas;
	/delete-property/ dma-names;
	status = "okay";

	/* Resistive touch controller */
	touchscreen@0 {
		reg = <0>;
		compatible = "ti,ads7846";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_restouch>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;

		spi-max-frequency = <1500000>;
		pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;

		ti,x-min = /bits/ 16 <125>;
		touchscreen-size-x = <4008>;
		ti,y-min = /bits/ 16 <282>;
		touchscreen-size-y = <3864>;
		ti,x-plate-ohms = /bits/ 16 <180>;
		touchscreen-max-pressure = <255>;
		touchscreen-average-samples = <10>;
		ti,debounce-tol = /bits/ 16 <3>;
		ti,debounce-rep = /bits/ 16 <1>;
		ti,settle-delay-usec = /bits/ 16 <150>;
		ti,keep-vref-on;
		wakeup-source;
	};
};

&fec1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_fec1>;
	pinctrl-1 = <&pinctrl_fec1_sleep>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy>;
	phy-supply = <&reg_eth_phy>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy: ethernet-phy@4 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <4>;
			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
		};
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio2>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		rohm,reset-snvs-powered;

		regulators {
			buck1_reg: BUCK1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			buck2_reg: BUCK2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <900000>;
			};

			buck3_reg: BUCK3 {
				regulator-name = "buck3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck4_reg: BUCK4 {
				regulator-name = "buck4";
				regulator-min-microvolt = <2600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5_reg: BUCK5 {
				regulator-name = "buck5";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6_reg: BUCK6 {
				regulator-name = "buck6";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: LDO1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <1900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2_reg: LDO2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_reg: LDO3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4_reg: LDO4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			ldo5_reg: LDO5 {
				regulator-compatible = "ldo5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			ldo6_reg: LDO6 {
				regulator-name = "ldo6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	/* TODO: configure audio, as of now just put a placeholder */
	wm8904: codec@1a {
		compatible = "wlf,wm8904";
		reg = <0x1a>;
		status = "disabled";
	};
};

&snvs_pwrkey {
	status = "okay";
};

/* Bluetooth */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	assigned-clocks = <&clk IMX8MN_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
	uart-has-rtscts;
	status = "okay";
};

/* Console */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	usb-role-switch;
	status = "okay";
};

/* WIFI */
&usdhc1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <4>;
	non-removable;
	keep-power-in-suspend;
	status = "okay";

	brcmf: bcrmf@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
	};
};

/* SD */
&usdhc2 {
	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

/* eMMC */
&usdhc3 {
	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13
			MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13
			MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13
			MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x13
			MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x13
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
		>;
	};

	pinctrl_fec1_sleep: fec1sleepgrp {
		fsl,pins = <
			MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16		0x120
			MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17		0x120
			MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x120
			MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19		0x120
			MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20		0x120
			MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21		0x120
			MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x120
			MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x120
			MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27		0x120
			MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26		0x120
			MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23		0x120
			MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25		0x120
			MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24		0x120
			MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x120
			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x120
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_pmic: pmicirqgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x141
		>;
	};

	pinctrl_reg_eth_phy: regethphygrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9	0x41
		>;
	};

	pinctrl_restouch: restouchgrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x1c0
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x140
			MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x140
			MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x140
			MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x41
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2021 Gateworks Corporation
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>

#include "imx8mn.dtsi"

/ {
	model = "Gateworks Venice GW7902 i.MX8MN board";
	compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";

	aliases {
		usb0 = &usbotg1;
	};

	chosen {
		stdout-path = &uart2;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	can20m: can20m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <20000000>;
		clock-output-names = "can20m";
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-user-pb {
			label = "user_pb";
			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_0>;
		};

		key-user-pb1x {
			label = "user_pb1x";
			linux,code = <BTN_1>;
			interrupt-parent = <&gsc>;
			interrupts = <0>;
		};

		key-erased {
			label = "key_erased";
			linux,code = <BTN_2>;
			interrupt-parent = <&gsc>;
			interrupts = <1>;
		};

		key-eeprom-wp {
			label = "eeprom_wp";
			linux,code = <BTN_3>;
			interrupt-parent = <&gsc>;
			interrupts = <2>;
		};

		key-tamper {
			label = "tamper";
			linux,code = <BTN_4>;
			interrupt-parent = <&gsc>;
			interrupts = <5>;
		};

		switch-hold {
			label = "switch_hold";
			linux,code = <BTN_5>;
			interrupt-parent = <&gsc>;
			interrupts = <7>;
		};
	};

	led-controller {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led-0 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "panel1";
			gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-1 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "panel2";
			gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-2 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "panel3";
			gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-3 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "panel4";
			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-4 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "panel5";
			gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};

	pps {
		compatible = "pps-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pps>;
		gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_usb1_vbus: regulator-usb1 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb1>;
		regulator-name = "usb_usb1_vbus";
		gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_wifi: regulator-wifi {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_wl>;
		regulator-name = "wifi";
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&A53_0 {
	cpu-supply = <&buck2>;
};

&A53_1 {
	cpu-supply = <&buck2>;
};

&A53_2 {
	cpu-supply = <&buck2>;
};

&A53_3 {
	cpu-supply = <&buck2>;
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	status = "okay";

	can@0 {
		compatible = "microchip,mcp2515";
		reg = <0>;
		clocks = <&can20m>;
		interrupt-parent = <&gpio2>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
		spi-max-frequency = <10000000>;
	};
};

&disp_blk_ctrl {
	status = "disabled";
};

/* off-board header */
&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi2>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	local-mac-address = [00 00 00 00 00 00];
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		};
	};
};

&gpio1 {
	gpio-line-names = "", "", "", "", "", "", "", "",
		"m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio2 {
	gpio-line-names = "", "", "", "", "", "", "", "",
		"uart2_en#", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio3 {
	gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio4 {
	gpio-line-names = "", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
		"", "uart1_term", "uart1_half", "app_gpio2",
		"mipi_gpio1", "", "", "";
};

&gpio5 {
	gpio-line-names = "", "", "", "mipi_gpio4",
		"mipi_gpio3", "mipi_gpio2", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpu {
	status = "disabled";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	gsc: gsc@20 {
		compatible = "gw,gsc";
		reg = <0x20>;
		pinctrl-0 = <&pinctrl_gsc>;
		interrupt-parent = <&gpio2>;
		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <1>;

		adc {
			compatible = "gw,gsc-adc";
			#address-cells = <1>;
			#size-cells = <0>;

			channel@6 {
				gw,mode = <0>;
				reg = <0x06>;
				label = "temp";
			};

			channel@8 {
				gw,mode = <1>;
				reg = <0x08>;
				label = "vdd_bat";
			};

			channel@82 {
				gw,mode = <2>;
				reg = <0x82>;
				label = "vin";
				gw,voltage-divider-ohms = <22100 1000>;
				gw,voltage-offset-microvolt = <700000>;
			};

			channel@84 {
				gw,mode = <2>;
				reg = <0x84>;
				label = "vin_4p0";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@86 {
				gw,mode = <2>;
				reg = <0x86>;
				label = "vdd_3p3";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@88 {
				gw,mode = <2>;
				reg = <0x88>;
				label = "vdd_0p9";
			};

			channel@8c {
				gw,mode = <2>;
				reg = <0x8c>;
				label = "vdd_soc";
			};

			channel@8e {
				gw,mode = <2>;
				reg = <0x8e>;
				label = "vdd_arm";
			};

			channel@90 {
				gw,mode = <2>;
				reg = <0x90>;
				label = "vdd_1p8";
			};

			channel@92 {
				gw,mode = <2>;
				reg = <0x92>;
				label = "vdd_dram";
			};

			channel@98 {
				gw,mode = <2>;
				reg = <0x98>;
				label = "vdd_1p0";
			};

			channel@9a {
				gw,mode = <2>;
				reg = <0x9a>;
				label = "vdd_2p5";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@9c {
				gw,mode = <2>;
				reg = <0x9c>;
				label = "vdd_5p0";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@a2 {
				gw,mode = <2>;
				reg = <0xa2>;
				label = "vdd_gsc";
				gw,voltage-divider-ohms = <10000 10000>;
			};
		};
	};

	gpio: gpio@23 {
		compatible = "nxp,pca9555";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gsc>;
		interrupts = <4>;
	};

	pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio3>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		rohm,reset-snvs-powered;
		#clock-cells = <0>;
		clocks = <&osc_32k 0>;
		clock-output-names = "clk-32k-out";

		regulators {
			/* vdd_soc: 0.805-0.900V (typ=0.8V) */
			BUCK1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			/* vdd_arm: 0.805-1.0V (typ=0.9V) */
			buck2: BUCK2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <900000>;
			};

			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
			BUCK3 {
				regulator-name = "buck3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_3p3 */
			BUCK4 {
				regulator-name = "buck4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_1p8 */
			BUCK5 {
				regulator-name = "buck5";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_dram */
			BUCK6 {
				regulator-name = "buck6";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* nvcc_snvs_1p8 */
			LDO1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <1900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_snvs_0p8 */
			LDO2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdda_1p8 */
			LDO3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO6 {
				regulator-name = "ldo6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};

	eeprom@50 {
		compatible = "atmel,24c02";
		reg = <0x50>;
		pagesize = <16>;
	};

	eeprom@51 {
		compatible = "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
	};

	eeprom@52 {
		compatible = "atmel,24c02";
		reg = <0x52>;
		pagesize = <16>;
	};

	eeprom@53 {
		compatible = "atmel,24c02";
		reg = <0x53>;
		pagesize = <16>;
	};

	rtc@68 {
		compatible = "dallas,ds1672";
		reg = <0x68>;
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	accelerometer@19 {
		compatible = "st,lis2de12";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_accel>;
		reg = <0x19>;
		st,drdy-int-pin = <1>;
		interrupt-parent = <&gpio1>;
		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "INT1";
	};
};

/* off-board header */
&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

/* off-board header */
&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&pgc_gpumix {
	status = "disabled";
};

/* off-board header */
&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

/* RS232/RS485/RS422 selectable */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
	status = "okay";
};

/* RS232 console */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

/* bluetooth HCI */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
	rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
	cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
		compatible = "brcm,bcm4330-bt";
		shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
	};
};

/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "host";
	vbus-supply = <&reg_usb1_vbus>;
	disable-over-current;
	status = "okay";
};

/* SDIO WiFi */
&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	non-removable;
	vmmc-supply = <&reg_wifi>;
	status = "okay";
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x40000159 /* M2_GDIS# */
			MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x40000041 /* M2_PWR_EN */
			MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041 /* M2_RESET */
			MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7	0x40000119 /* M2_OFF# */
			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x40000159 /* M2_WDIS# */
			MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041 /* APP GPIO1 */
			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x40000041 /* VDD_4P0_EN */
			MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* APP GPIO2 */
			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* UART2_EN# */
			MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x40000041 /* MIPI_GPIO1 */
			MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* MIPI_GPIO2 */
			MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* MIPI_GPIO3/PWM2 */
			MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* MIPI_GPIO4/PWM3 */
		>;
	};

	pinctrl_accel: accelgrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x159
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19 /* RST# */
			MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19 /* IRQ# */
		>;
	};

	pinctrl_gsc: gscgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6	0x40
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
			MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
			MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3
			MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
			MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
		>;
	};

	pinctrl_i2c4_gpio: i2c4gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20	0x400001c3
			MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21	0x400001c3
		>;
	};

	pinctrl_gpio_leds: gpioledgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21	0x19
			MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23	0x19
			MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x19
			MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20	0x19
			MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x19
		>;
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41
		>;
	};

	pinctrl_pps: ppsgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x141 /* PPS */
		>;
	};

	pinctrl_reg_wl: regwlgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41 /* WLAN_WLON */
		>;
	};

	pinctrl_reg_usb1: regusb1grp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7	0x41
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK	0xd6
			MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK	0xd6
			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0	0xd6
			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC	0xd6
		>;
	};

	pinctrl_spi1: spi1grp {
		fsl,pins = <
			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82
			MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82
			MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82
			MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x40
			MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3	0x140 /* CAN_IRQ# */
		>;
	};

	pinctrl_spi2: spi2grp {
		fsl,pins = <
			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x82
			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x82
			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x82
			MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40 /* SS0 */
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
		>;
	};

	pinctrl_uart1_gpio: uart1gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x40000110 /* HALF */
			MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25	0x40000110 /* TERM */
			MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23	0x40000110 /* RS485 */
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_uart3_gpio: uart3_gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41 /* BT_EN# */
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
			MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0		0x140 /* CTS */
			MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1		0x140 /* RTS */
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
			MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x141 /* GNSS_GASP */
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
		>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

#include <dt-bindings/clock/imx8mn-clock.h>
#include <dt-bindings/power/imx8mn-power.h>
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

#include "imx8mn-pinfunc.h"

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec1;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &ecspi3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		idle-states {
			entry-method = "psci";

			cpu_pd_wait: cpu-pd-wait {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010033>;
				local-timer-stop;
				entry-latency-us = <1000>;
				exit-latency-us = <700>;
				min-residency-us = <2700>;
			};
		};

		A53_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clock-latency = <61036>;
			clocks = <&clk IMX8MN_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			nvmem-cells = <&cpu_speed_grade>;
			nvmem-cell-names = "speed_grade";
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clock-latency = <61036>;
			clocks = <&clk IMX8MN_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			clock-latency = <61036>;
			clocks = <&clk IMX8MN_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			clock-latency = <61036>;
			clocks = <&clk IMX8MN_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_L2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
		};
	};

	a53_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <850000>;
			opp-supported-hw = <0xb00>, <0x7>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};

		opp-1400000000 {
			opp-hz = /bits/ 64 <1400000000>;
			opp-microvolt = <950000>;
			opp-supported-hw = <0x300>, <0x7>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};

		opp-1500000000 {
			opp-hz = /bits/ 64 <1500000000>;
			opp-microvolt = <1000000>;
			opp-supported-hw = <0x100>, <0x3>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};
	};

	osc_32k: clock-osc-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "osc_32k";
	};

	osc_24m: clock-osc-24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc_24m";
	};

	clk_ext1: clock-ext1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext1";
	};

	clk_ext2: clock-ext2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext2";
	};

	clk_ext3: clock-ext3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext3";
	};

	clk_ext4: clock-ext4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext4";
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7
			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tmu>;
			trips {
				cpu_alert0: trip0 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit0: trip1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <8000000>;
		arm,no-tick-in-suspend;
	};

	soc: soc@0 {
		compatible = "fsl,imx8mn-soc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x3e000000>;
		dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
		nvmem-cells = <&imx8mn_uid>;
		nvmem-cell-names = "soc_unique_id";

		aips1: bus@30000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x30000000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			spba2: spba-bus@30000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x30000000 0x100000>;
				ranges;

				sai2: sai@30020000 {
					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
					reg = <0x30020000 0x10000>;
					interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
						<&clk IMX8MN_CLK_DUMMY>,
						<&clk IMX8MN_CLK_SAI2_ROOT>,
						<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				sai3: sai@30030000 {
					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
					reg = <0x30030000 0x10000>;
					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
						 <&clk IMX8MN_CLK_DUMMY>,
						 <&clk IMX8MN_CLK_SAI3_ROOT>,
						 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				sai5: sai@30050000 {
					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
					reg = <0x30050000 0x10000>;
					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
						 <&clk IMX8MN_CLK_DUMMY>,
						 <&clk IMX8MN_CLK_SAI5_ROOT>,
						 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
					dma-names = "rx", "tx";
					fsl,shared-interrupt;
					fsl,dataline = <0 0xf 0xf>;
					status = "disabled";
				};

				sai6: sai@30060000 {
					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
					reg = <0x30060000  0x10000>;
					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
						 <&clk IMX8MN_CLK_DUMMY>,
						 <&clk IMX8MN_CLK_SAI6_ROOT>,
						 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				micfil: audio-controller@30080000 {
					compatible = "fsl,imx8mm-micfil";
					reg = <0x30080000 0x10000>;
					interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_PDM_IPG>,
						 <&clk IMX8MN_CLK_PDM_ROOT>,
						 <&clk IMX8MN_AUDIO_PLL1_OUT>,
						 <&clk IMX8MN_AUDIO_PLL2_OUT>,
						 <&clk IMX8MN_CLK_EXT3>;
					clock-names = "ipg_clk", "ipg_clk_app",
						      "pll8k", "pll11k", "clkext3";
					dmas = <&sdma2 24 25 0x80000000>;
					dma-names = "rx";
					status = "disabled";
				};

				spdif1: spdif@30090000 {
					compatible = "fsl,imx35-spdif";
					reg = <0x30090000 0x10000>;
					interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
						 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
						 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
						 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
						 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
						 <&clk IMX8MN_CLK_DUMMY>; /* spba */
					clock-names = "core", "rxtx0",
						      "rxtx1", "rxtx2",
						      "rxtx3", "rxtx4",
						      "rxtx5", "rxtx6",
						      "rxtx7", "spba";
					dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				sai7: sai@300b0000 {
					compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
					reg = <0x300b0000 0x10000>;
					interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
						 <&clk IMX8MN_CLK_DUMMY>,
						 <&clk IMX8MN_CLK_SAI7_ROOT>,
						 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
					clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				easrc: easrc@300c0000 {
					compatible = "fsl,imx8mn-easrc";
					reg = <0x300c0000 0x10000>;
					interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
					clock-names = "mem";
					dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
					       <&sdma2 18 23 0> , <&sdma2 19 23 0>,
					       <&sdma2 20 23 0> , <&sdma2 21 23 0>,
					       <&sdma2 22 23 0> , <&sdma2 23 23 0>;
					dma-names = "ctx0_rx", "ctx0_tx",
						    "ctx1_rx", "ctx1_tx",
						    "ctx2_rx", "ctx2_tx",
						    "ctx3_rx", "ctx3_tx";
					firmware-name = "imx/easrc/easrc-imx8mn.bin";
					fsl,asrc-rate = <8000>;
					fsl,asrc-format = <2>;
					status = "disabled";
				};
			};

			gpio1: gpio@30200000 {
				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
				reg = <0x30200000 0x10000>;
				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 10 30>;
			};

			gpio2: gpio@30210000 {
				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
				reg = <0x30210000 0x10000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 40 21>;
			};

			gpio3: gpio@30220000 {
				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
				reg = <0x30220000 0x10000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 61 26>;
			};

			gpio4: gpio@30230000 {
				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
				reg = <0x30230000 0x10000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 21 108 11>;
			};

			gpio5: gpio@30240000 {
				compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
				reg = <0x30240000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 119 30>;
			};

			tmu: tmu@30260000 {
				compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
				reg = <0x30260000 0x10000>;
				clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
				#thermal-sensor-cells = <0>;
			};

			wdog1: watchdog@30280000 {
				compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
				reg = <0x30280000 0x10000>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
				status = "disabled";
			};

			wdog2: watchdog@30290000 {
				compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
				reg = <0x30290000 0x10000>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
				status = "disabled";
			};

			wdog3: watchdog@302a0000 {
				compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
				reg = <0x302a0000 0x10000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
				status = "disabled";
			};

			sdma3: dma-controller@302b0000 {
				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
				reg = <0x302b0000 0x10000>;
				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
				 <&clk IMX8MN_CLK_SDMA3_ROOT>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			sdma2: dma-controller@302c0000 {
				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
				reg = <0x302c0000 0x10000>;
				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
					 <&clk IMX8MN_CLK_SDMA2_ROOT>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			iomuxc: pinctrl@30330000 {
				compatible = "fsl,imx8mn-iomuxc";
				reg = <0x30330000 0x10000>;
			};

			gpr: iomuxc-gpr@30340000 {
				compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
				reg = <0x30340000 0x10000>;
			};

			ocotp: efuse@30350000 {
				compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
				reg = <0x30350000 0x10000>;
				clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
				#address-cells = <1>;
				#size-cells = <1>;

				imx8mn_uid: unique-id@410 {
					reg = <0x4 0x8>;
				};

				cpu_speed_grade: speed-grade@10 {
					reg = <0x10 4>;
				};

				fec_mac_address: mac-address@90 {
					reg = <0x90 6>;
				};
			};

			anatop: clock-controller@30360000 {
				compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
				reg = <0x30360000 0x10000>;
				#clock-cells = <1>;
			};

			snvs: snvs@30370000 {
				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
				reg = <0x30370000 0x10000>;

				snvs_rtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap = <&snvs>;
					offset = <0x34>;
					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
					clock-names = "snvs-rtc";
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
					clock-names = "snvs-pwrkey";
					linux,keycode = <KEY_POWER>;
					wakeup-source;
					status = "disabled";
				};
			};

			clk: clock-controller@30380000 {
				compatible = "fsl,imx8mn-ccm";
				reg = <0x30380000 0x10000>;
				#clock-cells = <1>;
				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
					 <&clk_ext3>, <&clk_ext4>;
				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
					      "clk_ext3", "clk_ext4";
				assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
						<&clk IMX8MN_CLK_A53_CORE>,
						<&clk IMX8MN_CLK_NOC>,
						<&clk IMX8MN_CLK_AUDIO_AHB>,
						<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
						<&clk IMX8MN_SYS_PLL3>,
						<&clk IMX8MN_AUDIO_PLL1>,
						<&clk IMX8MN_AUDIO_PLL2>;
				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
							 <&clk IMX8MN_ARM_PLL_OUT>,
							 <&clk IMX8MN_SYS_PLL3_OUT>,
							 <&clk IMX8MN_SYS_PLL1_800M>;
				assigned-clock-rates = <0>, <0>, <0>,
							<400000000>,
							<400000000>,
							<600000000>,
							<393216000>,
							<361267200>;
			};

			src: reset-controller@30390000 {
				compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
				reg = <0x30390000 0x10000>;
				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};

			gpc: gpc@303a0000 {
				compatible = "fsl,imx8mn-gpc";
				reg = <0x303a0000 0x10000>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;

				pgc {
					#address-cells = <1>;
					#size-cells = <0>;

					pgc_hsiomix: power-domain@0 {
						#power-domain-cells = <0>;
						reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
						clocks = <&clk IMX8MN_CLK_USB_BUS>;
					};

					pgc_otg1: power-domain@1 {
						#power-domain-cells = <0>;
						reg = <IMX8MN_POWER_DOMAIN_OTG1>;
					};

					pgc_gpumix: power-domain@2 {
						#power-domain-cells = <0>;
						reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
						clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
							 <&clk IMX8MN_CLK_GPU_SHADER>,
							 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
							 <&clk IMX8MN_CLK_GPU_AHB>;
					};

					pgc_dispmix: power-domain@3 {
						#power-domain-cells = <0>;
						reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
						clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
							 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
					};

					pgc_mipi: power-domain@4 {
						#power-domain-cells = <0>;
						reg = <IMX8MN_POWER_DOMAIN_MIPI>;
						power-domains = <&pgc_dispmix>;
					};
				};
			};
		};

		aips2: bus@30400000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x30400000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pwm1: pwm@30660000 {
				compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
				reg = <0x30660000 0x10000>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
					<&clk IMX8MN_CLK_PWM1_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm2: pwm@30670000 {
				compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
				reg = <0x30670000 0x10000>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
					 <&clk IMX8MN_CLK_PWM2_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm3: pwm@30680000 {
				compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
				reg = <0x30680000 0x10000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
					 <&clk IMX8MN_CLK_PWM3_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm4: pwm@30690000 {
				compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
				reg = <0x30690000 0x10000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
					 <&clk IMX8MN_CLK_PWM4_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			system_counter: timer@306a0000 {
				compatible = "nxp,sysctr-timer";
				reg = <0x306a0000 0x20000>;
				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&osc_24m>;
				clock-names = "per";
			};
		};

		aips3: bus@30800000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x30800000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			spba1: spba-bus@30800000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x30800000 0x100000>;
				ranges;

				ecspi1: spi@30820000 {
					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0x30820000 0x10000>;
					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
						 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
					clock-names = "ipg", "per";
					dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi2: spi@30830000 {
					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0x30830000 0x10000>;
					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
						 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
					clock-names = "ipg", "per";
					dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi3: spi@30840000 {
					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0x30840000 0x10000>;
					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
						 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
					clock-names = "ipg", "per";
					dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart1: serial@30860000 {
					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
					reg = <0x30860000 0x10000>;
					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
						 <&clk IMX8MN_CLK_UART1_ROOT>;
					clock-names = "ipg", "per";
					dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart3: serial@30880000 {
					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
					reg = <0x30880000 0x10000>;
					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
						 <&clk IMX8MN_CLK_UART3_ROOT>;
					clock-names = "ipg", "per";
					dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart2: serial@30890000 {
					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
					reg = <0x30890000 0x10000>;
					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
						 <&clk IMX8MN_CLK_UART2_ROOT>;
					clock-names = "ipg", "per";
					status = "disabled";
				};
			};

			crypto: crypto@30900000 {
				compatible = "fsl,sec-v4.0";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x30900000 0x40000>;
				ranges = <0 0x30900000 0x40000>;
				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_AHB>,
					 <&clk IMX8MN_CLK_IPG_ROOT>;
				clock-names = "aclk", "ipg";

				sec_jr0: jr@1000 {
					 compatible = "fsl,sec-v4.0-job-ring";
					 reg = <0x1000 0x1000>;
					 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
					 status = "disabled";
				};

				sec_jr1: jr@2000 {
					 compatible = "fsl,sec-v4.0-job-ring";
					 reg = <0x2000 0x1000>;
					 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr2: jr@3000 {
					 compatible = "fsl,sec-v4.0-job-ring";
					 reg = <0x3000 0x1000>;
					 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			i2c1: i2c@30a20000 {
				compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a20000 0x10000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
				status = "disabled";
			};

			i2c2: i2c@30a30000 {
				compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a30000 0x10000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
				status = "disabled";
			};

			i2c3: i2c@30a40000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
				reg = <0x30a40000 0x10000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
				status = "disabled";
			};

			i2c4: i2c@30a50000 {
				compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a50000 0x10000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
				status = "disabled";
			};

			uart4: serial@30a60000 {
				compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
				reg = <0x30a60000 0x10000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
					 <&clk IMX8MN_CLK_UART4_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			mu: mailbox@30aa0000 {
				compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
				reg = <0x30aa0000 0x10000>;
				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_MU_ROOT>;
				#mbox-cells = <2>;
			};

			usdhc1: mmc@30b40000 {
				compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b40000 0x10000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
					 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MN_CLK_USDHC1_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@30b50000 {
				compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b50000 0x10000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
					 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MN_CLK_USDHC2_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc3: mmc@30b60000 {
				compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b60000 0x10000>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
					 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MN_CLK_USDHC3_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			flexspi: spi@30bb0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "nxp,imx8mm-fspi";
				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
				reg-names = "fspi_base", "fspi_mmap";
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
					 <&clk IMX8MN_CLK_QSPI_ROOT>;
				clock-names = "fspi_en", "fspi";
				status = "disabled";
			};

			sdma1: dma-controller@30bd0000 {
				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
				reg = <0x30bd0000 0x10000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
					 <&clk IMX8MN_CLK_AHB>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			fec1: ethernet@30be0000 {
				compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
				reg = <0x30be0000 0x10000>;
				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
					 <&clk IMX8MN_CLK_ENET1_ROOT>,
					 <&clk IMX8MN_CLK_ENET_TIMER>,
					 <&clk IMX8MN_CLK_ENET_REF>,
					 <&clk IMX8MN_CLK_ENET_PHY_REF>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
						  <&clk IMX8MN_CLK_ENET_TIMER>,
						  <&clk IMX8MN_CLK_ENET_REF>,
						  <&clk IMX8MN_CLK_ENET_PHY_REF>;
				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
							 <&clk IMX8MN_SYS_PLL2_100M>,
							 <&clk IMX8MN_SYS_PLL2_125M>,
							 <&clk IMX8MN_SYS_PLL2_50M>;
				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				nvmem-cells = <&fec_mac_address>;
				nvmem-cell-names = "mac-address";
				fsl,stop-mode = <&gpr 0x10 3>;
				status = "disabled";
			};

		};

		aips4: bus@32c00000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x32c00000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			disp_blk_ctrl: blk-ctrl@32e28000 {
				compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
				reg = <0x32e28000 0x100>;
				power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
						<&pgc_dispmix>, <&pgc_mipi>,
						<&pgc_mipi>;
				power-domain-names = "bus", "isi",
						     "lcdif", "mipi-dsi",
						     "mipi-csi";
				clocks = <&clk IMX8MN_CLK_DISP_AXI>,
					 <&clk IMX8MN_CLK_DISP_APB>,
					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
					 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
					 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
					 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
					 <&clk IMX8MN_CLK_DSI_CORE>,
					 <&clk IMX8MN_CLK_DSI_PHY_REF>,
					 <&clk IMX8MN_CLK_CSI1_PHY_REF>,
					 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
				clock-names = "disp_axi", "disp_apb",
					      "disp_axi_root", "disp_apb_root",
					      "lcdif-axi", "lcdif-apb", "lcdif-pix",
					      "dsi-pclk", "dsi-ref",
					      "csi-aclk", "csi-pclk";
				#power-domain-cells = <1>;
			};

			usbotg1: usb@32e40000 {
				compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
				reg = <0x32e40000 0x200>;
				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
				clock-names = "usb1_ctrl_root_clk";
				assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
				phys = <&usbphynop1>;
				fsl,usbmisc = <&usbmisc1 0>;
				power-domains = <&pgc_hsiomix>;
				status = "disabled";
			};

			usbmisc1: usbmisc@32e40200 {
				compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
				#index-cells = <1>;
				reg = <0x32e40200 0x200>;
			};
		};

		dma_apbh: dma-controller@33000000 {
			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
			reg = <0x33000000 0x2000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
			#dma-cells = <1>;
			dma-channels = <4>;
			clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
		};

		gpmi: nand-controller@33002000 {
			compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
			reg-names = "gpmi-nand", "bch";
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "bch";
			clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
				 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
			clock-names = "gpmi_io", "gpmi_bch_apb";
			dmas = <&dma_apbh 0>;
			dma-names = "rx-tx";
			status = "disabled";
		};

		gpu: gpu@38000000 {
			compatible = "vivante,gc";
			reg = <0x38000000 0x8000>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MN_CLK_GPU_AHB>,
				<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
				<&clk IMX8MN_CLK_GPU_CORE_ROOT>,
				<&clk IMX8MN_CLK_GPU_SHADER>;
			clock-names = "reg", "bus", "core", "shader";
			assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
					  <&clk IMX8MN_CLK_GPU_SHADER>,
					  <&clk IMX8MN_CLK_GPU_AXI>,
					  <&clk IMX8MN_CLK_GPU_AHB>,
					  <&clk IMX8MN_GPU_PLL>;
			assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
						  <&clk IMX8MN_GPU_PLL_OUT>,
						  <&clk IMX8MN_SYS_PLL1_800M>,
						  <&clk IMX8MN_SYS_PLL1_800M>;
			assigned-clock-rates = <400000000>,
					       <400000000>,
					       <800000000>,
					       <400000000>,
					       <1200000000>;
			power-domains = <&pgc_gpumix>;
		};

		gic: interrupt-controller@38800000 {
			compatible = "arm,gic-v3";
			reg = <0x38800000 0x10000>,
			      <0x38880000 0xc0000>;
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		ddrc: memory-controller@3d400000 {
			compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
			reg = <0x3d400000 0x400000>;
			clock-names = "core", "pll", "alt", "apb";
			clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
				 <&clk IMX8MN_DRAM_PLL>,
				 <&clk IMX8MN_CLK_DRAM_ALT>,
				 <&clk IMX8MN_CLK_DRAM_APB>;
		};

		ddr-pmu@3d800000 {
			compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
			reg = <0x3d800000 0x400000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	usbphynop1: usbphynop1 {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
		clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
		assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
		assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
		clock-names = "main_clk";
		power-domains = <&pgc_otg1>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
 *
 * DHCOM iMX8MP variant:
 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
 * DHCOM PCB number: 660-100 or newer
 * PDK2 PCB number: 516-400 or newer
 */

/dts-v1/;

#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp-dhcom-som.dtsi"

/ {
	model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (2)";
	compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som",
		     "fsl,imx8mp";

	chosen {
		stdout-path = &uart1;
	};

	gpio-keys {
		compatible = "gpio-keys";

		button-0 {
			gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */
			label = "TA1-GPIO-A";
			linux,code = <KEY_A>;
			pinctrl-0 = <&pinctrl_dhcom_a>;
			pinctrl-names = "default";
			wakeup-source;
		};

		button-1 {
			gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */
			label = "TA2-GPIO-B";
			linux,code = <KEY_B>;
			pinctrl-0 = <&pinctrl_dhcom_b>;
			pinctrl-names = "default";
			wakeup-source;
		};

		button-2 {
			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
			label = "TA3-GPIO-C";
			linux,code = <KEY_C>;
			pinctrl-0 = <&pinctrl_dhcom_c>;
			pinctrl-names = "default";
			wakeup-source;
		};

		button-3 {
			gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* GPIO D */
			label = "TA4-GPIO-D";
			linux,code = <KEY_D>;
			pinctrl-0 = <&pinctrl_dhcom_d>;
			pinctrl-names = "default";
			wakeup-source;
		};
	};

	led {
		compatible = "gpio-leds";

		led-0 {
			color = <LED_COLOR_ID_GREEN>;
			default-state = "off";
			function = LED_FUNCTION_INDICATOR;
			gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* GPIO E */
			pinctrl-0 = <&pinctrl_dhcom_e>;
			pinctrl-names = "default";
		};

		led-1 {
			color = <LED_COLOR_ID_GREEN>;
			default-state = "off";
			function = LED_FUNCTION_INDICATOR;
			gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */
			pinctrl-0 = <&pinctrl_dhcom_f>;
			pinctrl-names = "default";
		};

		led-2 {
			color = <LED_COLOR_ID_GREEN>;
			default-state = "off";
			function = LED_FUNCTION_INDICATOR;
			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; /* GPIO H */
			pinctrl-0 = <&pinctrl_dhcom_h>;
			pinctrl-names = "default";
		};

		led-3 {
			color = <LED_COLOR_ID_GREEN>;
			default-state = "off";
			function = LED_FUNCTION_INDICATOR;
			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
			pinctrl-0 = <&pinctrl_dhcom_i>;
			pinctrl-names = "default";
		};
	};
};

/*
 * PDK2 carrier board uses SoM with KSZ9131 populated and connected to
 * SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node.
 */
/delete-node/ &ethphy0f;

/*
 * PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC
 * ethernet RGMII interface. The SoM is not populated with second FEC PHY.
 */
/delete-node/ &ethphy1f;

&fec {	/* Second ethernet */
	phy-handle = <&ethphypdk>;

	mdio {
		ethphypdk: ethernet-phy@7 { /* KSZ 9021 */
			compatible = "ethernet-phy-ieee802.3-c22";
			pinctrl-0 = <&pinctrl_ethphy1>;
			pinctrl-names = "default";
			interrupt-parent = <&gpio4>;
			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
			max-speed = <100>;
			reg = <7>;
			reset-assert-us = <1000>;
			reset-deassert-us = <1000>;
			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
			rxc-skew-ps = <3000>;
			rxd0-skew-ps = <0>;
			rxd1-skew-ps = <0>;
			rxd2-skew-ps = <0>;
			rxd3-skew-ps = <0>;
			rxdv-skew-ps = <0>;
			txc-skew-ps = <3000>;
			txd0-skew-ps = <0>;
			txd1-skew-ps = <0>;
			txd2-skew-ps = <0>;
			txd3-skew-ps = <0>;
			txen-skew-ps = <0>;
		};
	};
};

&flexcan1 {
	status = "okay";
};

&usb3_1 {
	fsl,over-current-active-low;
};

&iomuxc {
	/*
	 * GPIO_A,B,C,D are connected to buttons.
	 * GPIO_E,F,H,I are connected to LEDs.
	 * GPIO_M is connected to CLKOUT2.
	 */
	pinctrl-0 = <&pinctrl_hog_base
		     &pinctrl_dhcom_g &pinctrl_dhcom_j
		     &pinctrl_dhcom_k &pinctrl_dhcom_l
		     &pinctrl_dhcom_int>;
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
 */

#include "imx8mp.dtsi"

/ {
	model = "DH electronics i.MX8M Plus DHCOM SoM";
	compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";

	aliases {
		ethernet0 = &eqos;
		ethernet1 = &fec;
		rtc0 = &rv3032;
		rtc1 = &snvs_rtc;
		spi0 = &flexspi;
	};

	memory@40000000 {
		device_type = "memory";
		/* Memory size 512 MiB..8 GiB will be filled by U-Boot */
		reg = <0x0 0x40000000 0 0x08000000>;
	};

	reg_eth_vio: regulator-eth-vio {
		compatible = "regulator-fixed";
		gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
		pinctrl-0 = <&pinctrl_enet_vio>;
		pinctrl-names = "default";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-name = "eth_vio";
		vin-supply = <&buck4>;
	};

	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio2 19 0>; /* SD2_RESET */
		off-on-delay-us = <12000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "VDD_3V3_SD";
		startup-delay-us = <100>;
		vin-supply = <&buck4>;
	};
};

&A53_0 {
	cpu-supply = <&buck2>;
};

&A53_1 {
	cpu-supply = <&buck2>;
};

&A53_2 {
	cpu-supply = <&buck2>;
};

&A53_3 {
	cpu-supply = <&buck2>;
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
	status = "disabled";
};

&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "disabled";
};

&eqos {	/* First ethernet */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-handle = <&ethphy0g>;
	phy-mode = "rgmii-id";
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		/* Up to one of these two PHYs may be populated. */
		ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
			compatible = "ethernet-phy-id0007.c110",
				     "ethernet-phy-ieee802.3-c22";
			interrupt-parent = <&gpio3>;
			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
			pinctrl-0 = <&pinctrl_ethphy0>;
			pinctrl-names = "default";
			reg = <1>;
			reset-assert-us = <1000>;
			reset-deassert-us = <1000>;
			reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
			/* Non-default PHY population option. */
			status = "disabled";
		};

		ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
			compatible = "ethernet-phy-id0022.1642",
				     "ethernet-phy-ieee802.3-c22";
			interrupt-parent = <&gpio3>;
			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
			micrel,led-mode = <0>;
			pinctrl-0 = <&pinctrl_ethphy0>;
			pinctrl-names = "default";
			reg = <5>;
			reset-assert-us = <1000>;
			reset-deassert-us = <1000>;
			reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
			/* Default PHY population option. */
			status = "okay";
		};
	};
};

&fec {	/* Second ethernet */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-handle = <&ethphy1f>;
	phy-mode = "rgmii";
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		/* Up to one PHY may be populated. */
		ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
			compatible = "ethernet-phy-id0007.c110",
				     "ethernet-phy-ieee802.3-c22";
			interrupt-parent = <&gpio4>;
			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
			pinctrl-0 = <&pinctrl_ethphy1>;
			pinctrl-names = "default";
			reg = <1>;
			reset-assert-us = <1000>;
			reset-deassert-us = <1000>;
			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
			/* Non-default PHY population option. */
			status = "disabled";
		};
	};
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "disabled";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "disabled";
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi>;
	status = "okay";

	flash@0 {	/* W25Q128JWPIM */
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <80000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&gpio1 {
	gpio-line-names =
		"DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
		"DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio2 {
	gpio-line-names =
		"", "", "", "", "", "", "", "",
		"", "", "", "DHCOM-K", "", "", "", "",
		"", "", "", "", "DHCOM-INT", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio3 {
	gpio-line-names =
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "SOM-HW0", "",
		"", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
		"SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
};

&gpio4 {
	gpio-line-names =
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "SOM-HW1", "", "", "", "",
		"", "", "", "DHCOM-D", "", "", "", "";
};

&gpio5 {
	gpio-line-names =
		"", "", "DHCOM-C", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
		"", "", "", "", "", "", "", "";
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	pmic: pmic@25 {
		compatible = "nxp,pca9450c";
		reg = <0x25>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;

		/*
		 * i.MX 8M Plus Data Sheet for Consumer Products
		 * 3.1.4 Operating ranges
		 * MIMX8ML8CVNKZAB
		 */
		regulators {
			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */
				regulator-compatible = "BUCK1";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1000000>;
				regulator-ramp-delay = <3125>;
				regulator-always-on;
				regulator-boot-on;
			};

			buck2: BUCK2 {	/* VDD_ARM */
				regulator-compatible = "BUCK2";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1000000>;
				regulator-ramp-delay = <3125>;
				regulator-always-on;
				regulator-boot-on;
			};

			buck4: BUCK4 {	/* VDD_3V3 */
				regulator-compatible = "BUCK4";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				regulator-boot-on;
			};

			buck5: BUCK5 {	/* VDD_1V8 */
				regulator-compatible = "BUCK5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */
				regulator-compatible = "BUCK6";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
				regulator-boot-on;
			};

			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */
				regulator-compatible = "LDO1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			ldo3: LDO3 {	/* VDDA_1V8 */
				regulator-compatible = "LDO3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			ldo4: LDO4 {	/* PMIC_LDO4 */
				regulator-compatible = "LDO4";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
			};

			ldo5: LDO5 {	/* NVCC_SD2 */
				regulator-compatible = "LDO5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};

	adc@48 {
		compatible = "ti,tla2024";
		reg = <0x48>;
		#address-cells = <1>;
		#size-cells = <0>;

		channel@0 {	/* Voltage over AIN0 and AIN1. */
			reg = <0>;
		};

		channel@1 {	/* Voltage over AIN0 and AIN3. */
			reg = <1>;
		};

		channel@2 {	/* Voltage over AIN1 and AIN3. */
			reg = <2>;
		};

		channel@3 {	/* Voltage over AIN2 and AIN3. */
			reg = <3>;
		};

		channel@4 {	/* Voltage over AIN0 and GND. */
			reg = <4>;
		};

		channel@5 {	/* Voltage over AIN1 and GND. */
			reg = <5>;
		};

		channel@6 {	/* Voltage over AIN2 and GND. */
			reg = <6>;
		};

		channel@7 {	/* Voltage over AIN3 and GND. */
			reg = <7>;
		};
	};

	touchscreen@49 {
		compatible = "ti,tsc2004";
		reg = <0x49>;
		interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_touch>;
		vio-supply = <&buck4>;
	};

	eeprom0: eeprom@50 {	/* EEPROM with EQoS MAC address */
		compatible = "atmel,24c02";
		pagesize = <16>;
		reg = <0x50>;
	};

	rv3032: rtc@51 {
		compatible = "microcrystal,rv3032";
		reg = <0x51>;
		interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_rtc>;
	};

	eeprom1: eeprom@53 {	/* EEPROM with FEC MAC address */
		compatible = "atmel,24c02";
		pagesize = <16>;
		reg = <0x53>;
	};
};

&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&i2c5 {	/* HDMI EDID bus */
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c5>;
	pinctrl-1 = <&pinctrl_i2c5_gpio>;
	scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&pwm1 {
	pinctrl-0 = <&pinctrl_pwm1>;
	pinctrl-names = "default";
	status = "disabled";
};

&uart1 {
	/* CA53 console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	/* Bluetooth */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	uart-has-rtscts;
	status = "okay";

	/*
	 * PLL3 at 320 MHz supplies UART2 root with 64 MHz clock,
	 * which with 16x oversampling yields 4 Mbdps baud base,
	 * which is exactly the maximum rate supported by muRata
	 * 2AE bluetooth UART.
	 */
	assigned-clocks = <&clk IMX8MP_SYS_PLL3>, <&clk IMX8MP_CLK_UART2>;
	assigned-clock-parents = <0>, <&clk IMX8MP_SYS_PLL3_OUT>;
	assigned-clock-rates = <320000000>, <64000000>;

	bluetooth {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart2_bt>;
		compatible = "cypress,cyw4373a0-bt";
		shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		max-speed = <4000000>;
	};
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usb3_phy0 {
	status = "okay";
};

&usb3_0 {
	status = "okay";
};

&usb_dwc3_0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0_vbus>;
	dr_mode = "otg";
	status = "okay";
};

&usb3_phy1 {
	status = "okay";
};

&usb3_1 {
	status = "okay";
};

&usb_dwc3_1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb1_vbus>;
	dr_mode = "host";
	status = "okay";
};

/* SDIO WiFi */
&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	vmmc-supply = <&buck4>;
	bus-width = <4>;
	non-removable;
	cap-power-off-card;
	keep-power-in-suspend;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;

	brcmf: bcrmf@1 {	/* muRata 2AE */
		reg = <1>;
		compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
		/*
		 * The "host-wake" interrupt output is by default not
		 * connected to the SoC, but can be connected on to
		 * SoC pin on the carrier board.
		 */
		reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
	};
};

/* SD slot */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	bus-width = <4>;
	status = "okay";
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	vmmc-supply = <&buck4>;
	vqmmc-supply = <&buck5>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-0 = <&pinctrl_hog_base
		     &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
		     &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
		     &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
		     &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
		     /* GPIO_M is connected to CLKOUT2 */
		     &pinctrl_dhcom_int>;
	pinctrl-names = "default";

	pinctrl_dhcom_a: dhcom-a-grp {
		fsl,pins = <
			/* ENET_QOS_EVENT0-OUT */
			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x2
		>;
	};

	pinctrl_dhcom_b: dhcom-b-grp {
		fsl,pins = <
			/* ENET_QOS_EVENT0-IN */
			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x2
		>;
	};

	pinctrl_dhcom_c: dhcom-c-grp {
		fsl,pins = <
			/* GPIO_C */
			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02		0x2
		>;
	};

	pinctrl_dhcom_d: dhcom-d-grp {
		fsl,pins = <
			/* GPIO_D */
			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x2
		>;
	};

	pinctrl_dhcom_e: dhcom-e-grp {
		fsl,pins = <
			/* GPIO_E */
			MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22		0x2
		>;
	};

	pinctrl_dhcom_f: dhcom-f-grp {
		fsl,pins = <
			/* GPIO_F */
			MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23		0x2
		>;
	};

	pinctrl_dhcom_g: dhcom-g-grp {
		fsl,pins = <
			/* GPIO_G */
			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x2
		>;
	};

	pinctrl_dhcom_h: dhcom-h-grp {
		fsl,pins = <
			/* GPIO_H */
			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x2
		>;
	};

	pinctrl_dhcom_i: dhcom-i-grp {
		fsl,pins = <
			/* CSI1_SYNC */
			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x2
		>;
	};

	pinctrl_dhcom_j: dhcom-j-grp {
		fsl,pins = <
			/* CSIx_#RST */
			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x2
		>;
	};

	pinctrl_dhcom_k: dhcom-k-grp {
		fsl,pins = <
			/* CSIx_PWDN */
			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x2
		>;
	};

	pinctrl_dhcom_l: dhcom-l-grp {
		fsl,pins = <
			/* CSI2_SYNC */
			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x2
		>;
	};

	pinctrl_dhcom_int: dhcom-int-grp {
		fsl,pins = <
			/* INT_HIGHEST_PRIO */
			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20			0x2
		>;
	};

	pinctrl_hog_base: dhcom-hog-base-grp {
		fsl,pins = <
			/* GPIOs for memory coding */
			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22		0x40000080
			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x40000080
			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x40000080
			/* GPIOs for hardware coding */
			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x40000080
			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x40000080
			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25		0x40000080
		>;
	};

	pinctrl_ecspi1: dhcom-ecspi1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK		0x44
			MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI		0x44
			MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO		0x44
			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x40
		>;
	};

	pinctrl_ecspi2: dhcom-ecspi2-grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x44
			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x44
			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x44
			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40
		>;
	};

	pinctrl_eqos: dhcom-eqos-grp {	/* RGMII */
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
		>;
	};

	pinctrl_enet_vio: dhcom-enet-vio-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x22
		>;
	};

	pinctrl_ethphy0: dhcom-ethphy0-grp {
		fsl,pins = <
			/* ENET1_#RST Reset */
			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x22
			/* ENET1_#INT Interrupt */
			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x22
		>;
	};

	pinctrl_ethphy1: dhcom-ethphy1-grp {
		fsl,pins = <
			/* ENET1_#RST Reset */
			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x11
			/* ENET1_#INT Interrupt */
			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x11
		>;
	};

	pinctrl_fec: dhcom-fec-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x1f
			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
			MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER		0x1f
		>;
	};

	pinctrl_flexcan1: dhcom-flexcan1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154
			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154
		>;
	};

	pinctrl_flexcan2: dhcom-flexcan2-grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART3_RXD__CAN2_TX			0x154
			MX8MP_IOMUXC_UART3_TXD__CAN2_RX			0x154
		>;
	};

	pinctrl_flexspi: dhcom-flexspi-grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
		>;
	};

	pinctrl_hdmi: dhcom-hdmi-grp {
		fsl,pins = <
			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154
			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154
		>;
	};

	pinctrl_i2c3: dhcom-i2c3-grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x40000084
			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x40000084
		>;
	};

	pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x84
			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x84
		>;
	};

	pinctrl_i2c4: dhcom-i2c4-grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x40000084
			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x40000084
		>;
	};

	pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x84
			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x84
		>;
	};

	pinctrl_i2c5: dhcom-i2c5-grp {
		fsl,pins = <
			MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL		0x40000084
			MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA		0x40000084
		>;
	};

	pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
		fsl,pins = <
			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0x84
			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x84
		>;
	};

	pinctrl_pmic: dhcom-pmic-grp {
		fsl,pins = <
			/* PMIC_nINT */
			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x40000090
		>;
	};

	pinctrl_pwm1: dhcom-pwm1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT		0x6
		>;
	};

	pinctrl_rtc: dhcom-rtc-grp {
		fsl,pins = <
			/* RTC_#INT Interrupt */
			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x40000080
		>;
	};

	pinctrl_touch: dhcom-touch-grp {
		fsl,pins = <
			/* #TOUCH_INT */
			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x40000080
		>;
	};

	pinctrl_uart1: dhcom-uart1-grp {
		fsl,pins = <
			/* Console UART */
			MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX		0x49
			MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX		0x49
			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x49
			MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS		0x49
		>;
	};

	pinctrl_uart2: dhcom-uart2-grp {
		fsl,pins = <
			/* Bluetooth UART */
			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49
			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49
			MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS		0x49
			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS		0x49
		>;
	};

	pinctrl_uart2_bt: dhcom-uart2-bt-grp {
		fsl,pins = <
			/* BT_REG_EN */
			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x144
		>;
	};

	pinctrl_uart3: dhcom-uart3-grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x49
			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x49
			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x49
			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x49
		>;
	};

	pinctrl_uart4: dhcom-uart4-grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49
			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49
		>;
	};

	pinctrl_usb0_vbus: dhcom-usb0-grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID		0x0
		>;
	};

	pinctrl_usb1_vbus: dhcom-usb1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR		0x6
			MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC		0x80
		>;
	};

	pinctrl_usdhc1: dhcom-usdhc1-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0
			/* WL_REG_EN */
			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
		>;
	};

	pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4
			/* WL_REG_EN */
			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
		>;
	};

	pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196
			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6
			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6
			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6
			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6
			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6
			/* WL_REG_EN */
			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
		>;
	};

	pinctrl_usdhc2: dhcom-usdhc2-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x20
		>;
	};

	pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x40000080
		>;
	};

	pinctrl_usdhc3: dhcom-usdhc3-grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
		>;
	};

	pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
		>;
	};

	pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
		>;
	};

	pinctrl_wdog: dhcom-wdog-grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6
		>;
	};
};