code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/atmel-at91.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Atmel AT91.

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>
  - Claudiu Beznea <claudiu.beznea@microchip.com>
  - Nicolas Ferre <nicolas.ferre@microchip.com>

description: |
  Boards with a SoC of the Atmel AT91 or SMART family shall have the following

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - items:
          - const: atmel,at91rm9200
      - items:
          - enum:
              - olimex,sam9-l9260
          - enum:
              - atmel,at91sam9260
              - atmel,at91sam9261
              - atmel,at91sam9263
              - atmel,at91sam9g20
              - atmel,at91sam9g45
              - atmel,at91sam9n12
              - atmel,at91sam9rl
              - atmel,at91sam9xe
              - atmel,at91sam9x60
          - const: atmel,at91sam9

      - items:
          - enum:
              - overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board
              - overkiz,kizboxmini-mb   # Overkiz kizbox Mini Mother Board
              - overkiz,kizboxmini-rd   # Overkiz kizbox Mini RailDIN
              - overkiz,smartkiz        # Overkiz SmartKiz Board
              - gardena,smart-gateway-at91sam # GARDENA smart Gateway (Article No. 19000)
          - const: atmel,at91sam9g25
          - const: atmel,at91sam9x5
          - const: atmel,at91sam9

      - items:
          - enum:
              - atmel,at91sam9g15
              - atmel,at91sam9g25
              - atmel,at91sam9g35
              - atmel,at91sam9x25
              - atmel,at91sam9x35
          - const: atmel,at91sam9x5
          - const: atmel,at91sam9

      - description: Overkiz kizbox3 board
        items:
          - const: overkiz,kizbox3-hs
          - const: atmel,sama5d27
          - const: atmel,sama5d2
          - const: atmel,sama5

      - description: Microchip SAMA5D27 WLSOM1
        items:
          - const: microchip,sama5d27-wlsom1
          - const: atmel,sama5d27
          - const: atmel,sama5d2
          - const: atmel,sama5

      - description: Microchip SAMA5D27 WLSOM1 Evaluation Kit
        items:
          - const: microchip,sama5d27-wlsom1-ek
          - const: microchip,sama5d27-wlsom1
          - const: atmel,sama5d27
          - const: atmel,sama5d2
          - const: atmel,sama5

      - items:
          - const: atmel,sama5d27
          - const: atmel,sama5d2
          - const: atmel,sama5

      - description: Microchip SAMA5D2 Industrial Connectivity Platform
        items:
          - const: microchip,sama5d2-icp
          - const: atmel,sama5d27
          - const: atmel,sama5d2
          - const: atmel,sama5

      - description: SAM9X60-EK board
        items:
          - const: microchip,sam9x60ek
          - const: microchip,sam9x60
          - const: atmel,at91sam9

      - description: Nattis v2 board with Natte v2 power board
        items:
          - const: axentia,nattis-2
          - const: axentia,natte-2
          - const: axentia,linea
          - const: atmel,sama5d31
          - const: atmel,sama5d3
          - const: atmel,sama5

      - description: TSE-850 v3 board
        items:
          - const: axentia,tse850v3
          - const: axentia,linea
          - const: atmel,sama5d31
          - const: atmel,sama5d3
          - const: atmel,sama5

      - items:
          - const: axentia,linea
          - const: atmel,sama5d31
          - const: atmel,sama5d3
          - const: atmel,sama5

      - description: Overkiz kizbox2 board with two heads
        items:
          - const: overkiz,kizbox2-2
          - const: atmel,sama5d31
          - const: atmel,sama5d3
          - const: atmel,sama5

      - description: Microchip SAMA5D3 Ethernet Development System Board
        items:
          - const: microchip,sama5d3-eds
          - const: atmel,sama5d36
          - const: atmel,sama5d3
          - const: atmel,sama5

      - description: CalAmp LMU5000 board
        items:
          - const: calamp,lmu5000
          - const: atmel,at91sam9g20
          - const: atmel,at91sam9

      - description: Exegin Q5xR5 board
        items:
          - const: exegin,q5xr5
          - const: atmel,at91sam9g20
          - const: atmel,at91sam9

      - items:
          - enum:
              - atmel,sama5d31
              - atmel,sama5d33
              - atmel,sama5d34
              - atmel,sama5d35
              - atmel,sama5d36
          - const: atmel,sama5d3
          - const: atmel,sama5

      - items:
          - enum:
              - atmel,sama5d41
              - atmel,sama5d42
              - atmel,sama5d43
              - atmel,sama5d44
          - const: atmel,sama5d4
          - const: atmel,sama5

      - items:
          - const: microchip,sama7g5ek # SAMA7G5 Evaluation Kit
          - const: microchip,sama7g5
          - const: microchip,sama7

      - description: Microchip LAN9662 Evaluation Boards.
        items:
          - enum:
              - microchip,lan9662-pcb8291
              - microchip,lan9662-pcb8309
          - const: microchip,lan9662
          - const: microchip,lan966

      - description: Microchip LAN9668 PCB8290 Evaluation Board.
        items:
          - const: microchip,lan9668-pcb8290
          - const: microchip,lan9668
          - const: microchip,lan966

      - description: Kontron KSwitch D10 MMT series
        items:
          - enum:
              - kontron,kswitch-d10-mmt-8g
              - kontron,kswitch-d10-mmt-6g-2gs
          - const: kontron,s1921
          - const: microchip,lan9668
          - const: microchip,lan966

      - items:
          - enum:
              - atmel,sams70j19
              - atmel,sams70j20
              - atmel,sams70j21
              - atmel,sams70n19
              - atmel,sams70n20
              - atmel,sams70n21
              - atmel,sams70q19
              - atmel,sams70q20
              - atmel,sams70q21
          - const: atmel,sams70
          - const: atmel,samv7

      - items:
          - enum:
              - atmel,samv70j19
              - atmel,samv70j20
              - atmel,samv70n19
              - atmel,samv70n20
              - atmel,samv70q19
              - atmel,samv70q20
          - const: atmel,samv70
          - const: atmel,samv7

      - items:
          - enum:
              - atmel,samv71j19
              - atmel,samv71j20
              - atmel,samv71j21
              - atmel,samv71n19
              - atmel,samv71n20
              - atmel,samv71n21
              - atmel,samv71q19
              - atmel,samv71q20
              - atmel,samv71q21
          - const: atmel,samv71
          - const: atmel,samv7

additionalProperties: true

...


code:
Atmel system registers

Chipid required properties:
- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
- reg : Should contain registers location and length

PIT Timer required properties:
- compatible: Should be "atmel,at91sam9260-pit"
- reg: Should contain registers location and length
- interrupts: Should contain interrupt for the PIT which is the IRQ line
  shared across all System Controller members.

PIT64B Timer required properties:
- compatible: Should be "microchip,sam9x60-pit64b"
- reg: Should contain registers location and length
- interrupts: Should contain interrupt for PIT64B timer
- clocks: Should contain the available clock sources for PIT64B timer.

System Timer (ST) required properties:
- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
- reg: Should contain registers location and length
- interrupts: Should contain interrupt for the ST which is the IRQ line
  shared across all System Controller members.
- clocks: phandle to input clock.
Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt"

RAMC SDRAM/DDR Controller required properties:
- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
			"atmel,at91sam9260-sdramc",
			"atmel,at91sam9g45-ddramc",
			"atmel,sama5d3-ddramc",
			"microchip,sam9x60-ddramc",
			"microchip,sama7g5-uddrc"
- reg: Should contain registers location and length

Examples:

	ramc0: ramc@ffffe800 {
		compatible = "atmel,at91sam9g45-ddramc";
		reg = <0xffffe800 0x200>;
	};

RAMC PHY Controller required properties:
- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon"
- reg: Should contain registers location and length

Example:

	ddr3phy: ddr3phy@e3804000 {
		compatible = "microchip,sama7g5-ddr3phy", "syscon";
		reg = <0xe3804000 0x1000>;
};

SHDWC Shutdown Controller

required properties:
- compatible: Should be "atmel,<chip>-shdwc".
  <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
- reg: Should contain registers location and length
- clocks: phandle to input clock.

optional properties:
- atmel,wakeup-mode: String, operation mode of the wakeup mode.
  Supported values are: "none", "high", "low", "any".
- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).

optional at91sam9260 properties:
- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.

optional at91sam9rl properties:
- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.

optional at91sam9x5 properties:
- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.

Example:

	shdwc@fffffd10 {
		compatible = "atmel,at91sam9260-shdwc";
		reg = <0xfffffd10 0x10>;
		clocks = <&clk32k>;
	};

SHDWC SAMA5D2-Compatible Shutdown Controller

1) shdwc node

required properties:
- compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or
  "microchip,sama7g5-shdwc"
- reg: should contain registers location and length
- clocks: phandle to input clock.
- #address-cells: should be one. The cell is the wake-up input index.
- #size-cells: should be zero.

optional properties:

- debounce-delay-us: minimum wake-up inputs debouncer period in
  microseconds. It's usually a board-related property.
- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.

optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties:
- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.

The node contains child nodes for each wake-up input that the platform uses.

2) input nodes

Wake-up input nodes are usually described in the "board" part of the Device
Tree. Note also that input 0 is linked to the wake-up pin and is frequently
used.

Required properties:
- reg: should contain the wake-up input index [0 - 15].

Optional properties:
- atmel,wakeup-active-high: boolean, the corresponding wake-up input described
  by the child, forces the wake-up of the core power supply on a high level.
  The default is to be active low.

Example:

On the SoC side:
	shdwc@f8048010 {
		compatible = "atmel,sama5d2-shdwc";
		reg = <0xf8048010 0x10>;
		clocks = <&clk32k>;
		#address-cells = <1>;
		#size-cells = <0>;
		atmel,wakeup-rtc-timer;
	};

On the board side:
	shdwc@f8048010 {
		debounce-delay-us = <976>;

		input@0 {
			reg = <0>;
		};

		input@1 {
			reg = <1>;
			atmel,wakeup-active-high;
		};
	};

Special Function Registers (SFR)

Special Function Registers (SFR) manage specific aspects of the integrated
memory, bridge implementations, processor and other functionality not controlled
elsewhere.

required properties:
- compatible: Should be "atmel,<chip>-sfr", "syscon" or
	"atmel,<chip>-sfrbu", "syscon"
  <chip> can be "sama5d3", "sama5d4" or "sama5d2".
  It also can be "microchip,sam9x60-sfr", "syscon".
- reg: Should contain registers location and length

	sfr@f0038000 {
		compatible = "atmel,sama5d3-sfr", "syscon";
		reg = <0xf0038000 0x60>;
	};

Security Module (SECUMOD)

The Security Module macrocell provides all necessary secure functions to avoid
voltage, temperature, frequency and mechanical attacks on the chip. It also
embeds secure memories that can be scrambled.

The Security Module also offers the PIOBU pins which can be used as GPIO pins.
Note that they maintain their voltage during Backup/Self-refresh.

required properties:
- compatible: Should be "atmel,<chip>-secumod", "syscon".
  <chip> can be "sama5d2".
- reg: Should contain registers location and length
- gpio-controller:	Marks the port as GPIO controller.
- #gpio-cells:		There are 2. The pin number is the
			first, the second represents additional
			parameters such as GPIO_ACTIVE_HIGH/LOW.

	secumod@fc040000 {
		compatible = "atmel,sama5d2-secumod", "syscon";
		reg = <0xfc040000 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
	};

repo_name: angery/linux


code:
Axis Communications AB
ARTPEC series SoC Device Tree Bindings

ARTPEC-6 ARM SoC
================

Required root node properties:
- compatible = "axis,artpec6";

ARTPEC-6 System Controller
--------------------------

The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe
and resets.

Required properties:
- compatible: "axis,artpec6-syscon", "syscon"
- reg: Address and length of the register bank.

Example:
	syscon {
		compatible = "axis,artpec6-syscon", "syscon";
		reg = <0xf8000000 0x48>;
	};

ARTPEC-6 Development board:
---------------------------
Required root node properties:
- compatible = "axis,artpec6-dev-board", "axis,artpec6";


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/axxia.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Axxia AXM55xx

maintainers:
  - Anders Berg <anders.berg@lsi.com>

properties:
  $nodename:
    const: "/"
  compatible:
    description: LSI AXM5516 Validation board (Amarillo)
    items:
      - const: lsi,axm5516-amarillo
      - const: lsi,axm5516

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/bcm2835.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM2711/BCM2835 Platforms Device Tree Bindings

maintainers:
  - Eric Anholt <eric@anholt.net>
  - Stefan Wahren <wahrenst@gmx.net>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: BCM2711 based Boards
        items:
          - enum:
              - raspberrypi,400
              - raspberrypi,4-compute-module
              - raspberrypi,4-model-b
          - const: brcm,bcm2711

      - description: BCM2835 based Boards
        items:
          - enum:
              - raspberrypi,model-a
              - raspberrypi,model-a-plus
              - raspberrypi,model-b
              - raspberrypi,model-b-i2c0  # Raspberry Pi Model B (no P5)
              - raspberrypi,model-b-rev2
              - raspberrypi,model-b-plus
              - raspberrypi,compute-module
              - raspberrypi,model-zero
              - raspberrypi,model-zero-w
          - const: brcm,bcm2835

      - description: BCM2836 based Boards
        items:
          - enum:
              - raspberrypi,2-model-b
          - const: brcm,bcm2836

      - description: BCM2837 based Boards
        items:
          - enum:
              - raspberrypi,3-model-a-plus
              - raspberrypi,3-model-b
              - raspberrypi,3-model-b-plus
              - raspberrypi,3-compute-module
              - raspberrypi,3-compute-module-lite
              - raspberrypi,model-zero-2-w
          - const: brcm,bcm2837

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm11351.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM11351 device tree bindings

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - brcm,bcm28155-ap
      - const: brcm,bcm11351

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm21664.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM21664 device tree bindings

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - brcm,bcm21664-garnet
      - const: brcm,bcm21664

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm23550.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM23550 device tree bindings

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - brcm,bcm23550-sparrow
      - const: brcm,bcm23550

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4708.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM4708 device tree bindings

description:
  Broadcom BCM4708/47081/4709/47094/53012 Wi-Fi/network SoCs based
  on the iProc architecture (Northstar).

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>
  - Hauke Mehrtens <hauke@hauke-m.de>
  - Rafal Milecki <zajec5@gmail.com>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: BCM4708 based boards
        items:
          - enum:
              - asus,rt-ac56u
              - asus,rt-ac68u
              - buffalo,wzr-1750dhp
              - linksys,ea6300-v1
              - linksys,ea6500-v2
              - luxul,xap-1510v1
              - luxul,xwc-1000
              - netgear,r6250v1
              - netgear,r6300v2
              - smartrg,sr400ac
              - brcm,bcm94708
          - const: brcm,bcm4708

      - description: BCM47081 based boards
        items:
          - enum:
              - asus,rt-n18u
              - buffalo,wzr-600dhp2
              - buffalo,wzr-900dhp
              - luxul,xap-1410v1
              - luxul,xwr-1200v1
              - tplink,archer-c5-v2
          - const: brcm,bcm47081
          - const: brcm,bcm4708

      - description: BCM4709 based boards
        items:
          - enum:
              - asus,rt-ac87u
              - buffalo,wxr-1900dhp
              - linksys,ea9200
              - netgear,r7000
              - netgear,r8000
              - tplink,archer-c9-v1
              - brcm,bcm94709
          - const: brcm,bcm4709
          - const: brcm,bcm4708

      - description: BCM47094 based boards
        items:
          - enum:
              - asus,rt-ac88u
              - dlink,dir-885l
              - dlink,dir-890l
              - linksys,panamera
              - luxul,abr-4500-v1
              - luxul,xap-1610-v1
              - luxul,xbr-4500-v1
              - luxul,xwc-2000-v1
              - luxul,xwr-3100v1
              - luxul,xwr-3150-v1
              - netgear,r8500
              - phicomm,k3
          - const: brcm,bcm47094
          - const: brcm,bcm4708

      - description: BCM53012 based boards
        items:
          - enum:
              - brcm,bcm953012er
              - brcm,bcm953012hr
              - brcm,bcm953012k
          - const: brcm,bcm53012
          - const: brcm,bcm4708

      - description: BCM53015 based boards
        items:
          - enum:
              - meraki,mr26
          - const: brcm,bcm53015
          - const: brcm,bcm4708

      - description: BCM53016 based boards
        items:
          - enum:
              - dlink,dwl-8610ap
              - meraki,mr32
          - const: brcm,bcm53016
          - const: brcm,bcm4708

additionalProperties: true

...


code:
Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
-----------------------------------------------------------

Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
following properties:

Required root node property:

compatible: should be "brcm,bcm63138"

An optional Boot lookup table Device Tree node is required for secondary CPU
initialization as well as a 'resets' phandle to the correct PMB controller as
defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
'enable-method' property.

Required properties for the Boot lookup table node:
- compatible: should be "brcm,bcm63138-bootlut"
- reg: register base address and length for the Boot Lookup table

Optional properties for the primary CPU node:
- enable-method: should be "brcm,bcm63138"

Optional properties for the secondary CPU node:
- enable-method: should be "brcm,bcm63138"
- resets: phandle to the relevant PMB controller, one integer indicating the internal
  bus number, and a second integer indicating the address of the CPU in the PMB
  internal bus number.

Example:

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a9";
			reg = <0>;
			...
			enable-method = "brcm,bcm63138";
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			reg = <1>;
			...
			enable-method = "brcm,bcm63138";
			resets = <&pmb0 4 1>;
		};
	};

	bootlut: bootlut@8000 {
		compatible = "brcm,bcm63138-bootlut";
		reg = <0x8000 0x50>;
	};

=======
reboot
------
Two nodes are required for software reboot: a timer node and a syscon-reboot node.

Timer node:

- compatible: Must be "brcm,bcm6328-timer", "syscon"
- reg: Register base address and length

Syscon reboot node:

See Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml for the
detailed list of properties, the two values defined below are specific to the
BCM6328-style timer:

- offset: Should be 0x34 to denote the offset of the TIMER_WD_TIMER_RESET register
  from the beginning of the TIMER block
- mask: Should be 1 for the SoftRst bit.

Example:

	timer: timer@80 {
		compatible = "brcm,bcm6328-timer", "syscon";
		reg = <0x80 0x3c>;
	};

	reboot {
		compatible = "syscon-reboot";
		regmap = <&timer>;
		offset = <0x34>;
		mask = <0x1>;
	};


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcmbca.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Broadband SoC device tree bindings

description:
  Broadcom Broadband SoCs include family of high performance DSL/PON/Wireless
  chips that can be used as home gateway, router and WLAN AP for residential,
  enterprise and carrier applications.

maintainers:
  - William Zhang <william.zhang@broadcom.com>
  - Anand Gore <anand.gore@broadcom.com>
  - Kursad Oney <kursad.oney@broadcom.com>
  - Rafał Miłecki <rafal@milecki.pl>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: BCM47622 based boards
        items:
          - enum:
              - brcm,bcm947622
          - const: brcm,bcm47622
          - const: brcm,bcmbca

      - description: BCM4906 based boards
        items:
          - enum:
              - netgear,r8000p
              - tplink,archer-c2300-v1
          - const: brcm,bcm4906
          - const: brcm,bcm4908
          - const: brcm,bcmbca

      - description: BCM4908 based boards
        items:
          - enum:
              - asus,gt-ac5300
              - brcm,bcm94908
              - netgear,raxe500
          - const: brcm,bcm4908
          - const: brcm,bcmbca

      - description: BCM49408 based boards
        items:
          - const: brcm,bcm49408
          - const: brcm,bcm4908
          - const: brcm,bcmbca

      - description: BCM4912 based boards
        items:
          - enum:
              - asus,gt-ax6000
              - brcm,bcm94912
          - const: brcm,bcm4912
          - const: brcm,bcmbca

      - description: BCM63138 based boards
        items:
          - enum:
              - brcm,bcm963138
              - brcm,BCM963138DVT
          - const: brcm,bcm63138
          - const: brcm,bcmbca

      - description: BCM63146 based boards
        items:
          - enum:
              - brcm,bcm963146
          - const: brcm,bcm63146
          - const: brcm,bcmbca

      - description: BCM63148 based boards
        items:
          - enum:
              - brcm,bcm963148
          - const: brcm,bcm63148
          - const: brcm,bcmbca

      - description: BCM63158 based boards
        items:
          - enum:
              - brcm,bcm963158
          - const: brcm,bcm63158
          - const: brcm,bcmbca

      - description: BCM63178 based boards
        items:
          - enum:
              - brcm,bcm963178
          - const: brcm,bcm63178
          - const: brcm,bcmbca

      - description: BCM6756 based boards
        items:
          - enum:
              - brcm,bcm96756
          - const: brcm,bcm6756
          - const: brcm,bcmbca

      - description: BCM6813 based boards
        items:
          - enum:
              - brcm,bcm96813
          - const: brcm,bcm6813
          - const: brcm,bcmbca

      - description: BCM6846 based boards
        items:
          - enum:
              - brcm,bcm96846
          - const: brcm,bcm6846
          - const: brcm,bcmbca

      - description: BCM6855 based boards
        items:
          - enum:
              - brcm,bcm96855
          - const: brcm,bcm6855
          - const: brcm,bcmbca

      - description: BCM6856 based boards
        items:
          - enum:
              - brcm,bcm96856
          - const: brcm,bcm6856
          - const: brcm,bcmbca

      - description: BCM6858 based boards
        items:
          - enum:
              - brcm,bcm96858
          - const: brcm,bcm6858
          - const: brcm,bcmbca

      - description: BCM6878 based boards
        items:
          - enum:
              - brcm,bcm96878
          - const: brcm,bcm6878
          - const: brcm,bcmbca

additionalProperties: true

...


code:
ARM Broadcom STB platforms Device Tree Bindings
-----------------------------------------------
Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
SoC shall have the following DT organization:

Required root node properties:
    - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"

example:
/ {
    #address-cells = <2>;
    #size-cells = <2>;
    model = "Broadcom STB (bcm7445)";
    compatible = "brcm,bcm7445", "brcm,brcmstb";

Further, syscon nodes that map platform-specific registers used for general
system control is required:

    - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
    - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
		  "brcm,brcmstb-cpu-biu-ctrl",
		  "syscon"
    - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"

cpu-biu-ctrl node
-------------------
SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
complex to the different Memory Controller Ports (MCP), one per memory
controller (MEMC). This BIU block offers a feature called Write Pairing which
consists in collapsing two adjacent cache lines into a single (bursted) write
transaction towards the memory controller (MEMC) to maximize write bandwidth.

Required properties:

    - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"

Optional properties:

    - brcm,write-pairing:
	Boolean property, which when present indicates that the chip
	supports write-pairing.

example:
    rdb {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "simple-bus";
        ranges = <0 0x00 0xf0000000 0x1000000>;

        sun_top_ctrl: syscon@404000 {
            compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
            reg = <0x404000 0x51c>;
        };

        hif_cpubiuctrl: syscon@3e2400 {
            compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
            reg = <0x3e2400 0x5b4>;
            brcm,write-pairing;
        };

        hif_continuation: syscon@452000 {
            compatible = "brcm,bcm7445-hif-continuation", "syscon";
            reg = <0x452000 0x100>;
        };
    };

Nodes that allow for support of SMP initialization and reboot are required:

smpboot
-------
Required properties:

    - compatible
        The string "brcm,brcmstb-smpboot".

    - syscon-cpu
        A phandle / integer array property which lets the BSP know the location
        of certain CPU power-on registers.

        The layout of the property is as follows:
            o a phandle to the "hif_cpubiuctrl" syscon node
            o offset to the base CPU power zone register
            o offset to the base CPU reset register

    - syscon-cont
        A phandle pointing to the syscon node which describes the CPU boot
        continuation registers.
            o a phandle to the "hif_continuation" syscon node

example:
    smpboot {
        compatible = "brcm,brcmstb-smpboot";
        syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
        syscon-cont = <&hif_continuation>;
    };

reboot
-------
Required properties

    - compatible
        The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with
        the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm
        chips with the old SUN_TOP_CTRL interface.

    - syscon
        A phandle / integer array that points to the syscon node which describes
        the general system reset registers.
            o a phandle to "sun_top_ctrl"
            o offset to the "reset source enable" register
            o offset to the "software master reset" register

example:
    reboot {
        compatible = "brcm,brcmstb-reboot";
        syscon = <&sun_top_ctrl 0x304 0x308>;
    };

Power management
----------------

For power management (particularly, S2/S3/S5 system suspend), the following SoC
components are needed:

= Always-On control block (AON CTRL)

This hardware provides control registers for the "always-on" (even in low-power
modes) hardware, such as the Power Management State Machine (PMSM).

Required properties:
- compatible     : should contain "brcm,brcmstb-aon-ctrl"
- reg            : the register start and length for the AON CTRL block

Example:

aon-ctrl@410000 {
	compatible = "brcm,brcmstb-aon-ctrl";
	reg = <0x410000 0x400>;
};

= Memory controllers

A Broadcom STB SoC typically has a number of independent memory controllers,
each of which may have several associated hardware blocks, which are versioned
independently (control registers, DDR PHYs, etc.). One might consider
describing these controllers as a parent "memory controllers" block, which
contains N sub-nodes (one for each controller in the system), each of which is
associated with a number of hardware register resources (e.g., its PHY). See
the example device tree snippet below.

== MEMC (MEMory Controller)

Represents a single memory controller instance.

Required properties:
- compatible     : should contain "brcm,brcmstb-memc" and "simple-bus"

Should contain subnodes for any of the following relevant hardware resources:

== DDR PHY control

Control registers for this memory controller's DDR PHY.

Required properties:
- compatible     : should contain one of these
	"brcm,brcmstb-ddr-phy-v71.1"
	"brcm,brcmstb-ddr-phy-v72.0"
	"brcm,brcmstb-ddr-phy-v225.1"
	"brcm,brcmstb-ddr-phy-v240.1"
	"brcm,brcmstb-ddr-phy-v240.2"

- reg            : the DDR PHY register range

== DDR SHIMPHY

Control registers for this memory controller's DDR SHIMPHY.

Required properties:
- compatible     : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
- reg            : the DDR SHIMPHY register range

== MEMC DDR control

Sequencer DRAM parameters and control registers. Used for Self-Refresh
Power-Down (SRPD), among other things.

See Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml for a
full list of supported compatible strings and properties.

Example:

memory_controllers {
	ranges;
	compatible = "simple-bus";

	memc@0 {
		compatible = "brcm,brcmstb-memc", "simple-bus";
		ranges;

		ddr-phy@f1106000 {
			compatible = "brcm,brcmstb-ddr-phy-v240.1";
			reg = <0xf1106000 0x21c>;
		};

		shimphy@f1108000 {
			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
			reg = <0xf1108000 0xe4>;
		};

		memc-ddr@f1102000 {
			reg = <0xf1102000 0x800>;
			compatible = "brcm,brcmstb-memc-ddr";
		};
	};

	memc@1 {
		compatible = "brcm,brcmstb-memc", "simple-bus";
		ranges;

		ddr-phy@f1186000 {
			compatible = "brcm,brcmstb-ddr-phy-v240.1";
			reg = <0xf1186000 0x21c>;
		};

		shimphy@f1188000 {
			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
			reg = <0xf1188000 0xe4>;
		};

		memc-ddr@f1182000 {
			reg = <0xf1182000 0x800>;
			compatible = "brcm,brcmstb-memc-ddr";
		};
	};

	memc@2 {
		compatible = "brcm,brcmstb-memc", "simple-bus";
		ranges;

		ddr-phy@f1206000 {
			compatible = "brcm,brcmstb-ddr-phy-v240.1";
			reg = <0xf1206000 0x21c>;
		};

		shimphy@f1208000 {
			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
			reg = <0xf1208000 0xe4>;
		};

		memc-ddr@f1202000 {
			reg = <0xf1202000 0x800>;
			compatible = "brcm,brcmstb-memc-ddr";
		};
	};
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,cygnus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Cygnus device tree bindings

maintainers:
  - Ray Jui <rjui@broadcom.com>
  - Scott Branden <sbranden@broadcom.com>

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - brcm,bcm11300
          - brcm,bcm11320
          - brcm,bcm11350
          - brcm,bcm11360
          - brcm,bcm58300
          - brcm,bcm58302
          - brcm,bcm58303
          - brcm,bcm58305
      - const: brcm,cygnus

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,hr2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Hurricane 2 device tree bindings

description:
  Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
  are based on Broadcom's iProc SoC architecture and feature a single core Cortex
  A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
  flash and a PCIe attached integrated switching engine.

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - ubnt,unifi-switch8
      - const: brcm,bcm53342
      - const: brcm,hr2

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,ns2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom North Star 2 (NS2) device tree bindings

maintainers:
  - Ray Jui <rjui@broadcom.com>
  - Scott Branden <sbranden@broadcom.com>

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - brcm,ns2-svk
          - brcm,ns2-xmc
      - const: brcm,ns2

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,nsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Northstar Plus device tree bindings

description:
  Broadcom Northstar Plus family of SoCs are used for switching control
  and management applications as well as residential router/gateway
  applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
  several peripheral interfaces including multiple Gigabit Ethernet PHYs,
  DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
  SATA and several other IO controllers.

maintainers:
  - Ray Jui <rjui@broadcom.com>
  - Scott Branden <sbranden@broadcom.com>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: BCM58522 based boards
        items:
          - enum:
              - brcm,bcm958522er
          - const: brcm,bcm58522
          - const: brcm,nsp

      - description: BCM58525 based boards
        items:
          - enum:
              - brcm,bcm958525er
              - brcm,bcm958525xmc
          - const: brcm,bcm58525
          - const: brcm,nsp

      - description: BCM58535 based boards
        items:
          - const: brcm,bcm58535
          - const: brcm,nsp

      - description: BCM58622 based boards
        items:
          - enum:
              - brcm,bcm958622hr
          - const: brcm,bcm58622
          - const: brcm,nsp

      - description: BCM58623 based boards
        items:
          - enum:
              - brcm,bcm958623hr
          - const: brcm,bcm58623
          - const: brcm,nsp

      - description: BCM58625 based boards
        items:
          - enum:
              - brcm,bcm958625hr
              - brcm,bcm958625k
              - meraki,mx64
              - meraki,mx64-a0
              - meraki,mx64w
              - meraki,mx64w-a0
              - meraki,mx65
              - meraki,mx65w
          - const: brcm,bcm58625
          - const: brcm,nsp

      - description: BCM88312 based boards
        items:
          - enum:
              - brcm,bcm988312hr
          - const: brcm,bcm88312
          - const: brcm,nsp

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,stingray.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Stingray device tree bindings

maintainers:
  - Ray Jui <rjui@broadcom.com>
  - Scott Branden <sbranden@broadcom.com>

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - brcm,bcm958742k
          - brcm,bcm958742t
          - brcm,bcm958802a802x
      - const: brcm,stingray

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,vulcan-soc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Vulcan device tree bindings

maintainers:
  - Robert Richter <rrichter@marvell.com>

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - brcm,vulcan-eval
          - cavium,thunderx2-cn9900
      - const: brcm,vulcan-soc

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/raspberrypi,bcm2835-firmware.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Raspberry Pi VideoCore firmware driver

maintainers:
  - Eric Anholt <eric@anholt.net>
  - Stefan Wahren <wahrenst@gmx.net>

select:
  properties:
    compatible:
      contains:
        const: raspberrypi,bcm2835-firmware

  required:
    - compatible

properties:
  compatible:
    items:
      - const: raspberrypi,bcm2835-firmware
      - const: simple-mfd

  mboxes:
    maxItems: 1

  clocks:
    type: object

    properties:
      compatible:
        const: raspberrypi,firmware-clocks

      "#clock-cells":
        const: 1
        description: >
          The argument is the ID of the clocks contained by the
          firmware messages.

    required:
      - compatible
      - "#clock-cells"

  reset:
    type: object

    properties:
      compatible:
        const: raspberrypi,firmware-reset

      "#reset-cells":
        const: 1
        description: >
          The argument is the ID of the firmware reset line to affect.

    required:
      - compatible
      - "#reset-cells"

  pwm:
    type: object

    properties:
      compatible:
        const: raspberrypi,firmware-poe-pwm

      "#pwm-cells":
        # See pwm.yaml in this directory for a description of the cells format.
        const: 2

    required:
      - compatible
      - "#pwm-cells"

    additionalProperties: false

required:
  - compatible
  - mboxes

additionalProperties: false

examples:
  - |
    firmware {
        compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
        mboxes = <&mailbox>;

        firmware_clocks: clocks {
            compatible = "raspberrypi,firmware-clocks";
            #clock-cells = <1>;
        };

        reset: reset {
            compatible = "raspberrypi,firmware-reset";
            #reset-cells = <1>;
        };

        pwm: pwm {
            compatible = "raspberrypi,firmware-poe-pwm";
            #pwm-cells = <2>;
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bitmain.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Bitmain platform

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

properties:
  $nodename:
    const: "/"
  compatible:
    items:
      - enum:
          - bitmain,sophon-edge
      - const: bitmain,bm1880

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/calxeda.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Calxeda Platforms

maintainers:
  - Rob Herring <robh@kernel.org>
description: |+
  Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC
  or Cortex-A15 based ECX-2000 SOCs

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - calxeda,highbank
          - calxeda,ecx-2000

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Calxeda Highbank system registers

description: |
  The Calxeda Highbank system has a block of MMIO registers controlling
  several generic system aspects. Those can be used to control some power
  management, they also contain some gate and PLL clocks.

maintainers:
  - Andre Przywara <andre.przywara@arm.com>

properties:
  compatible:
    const: calxeda,hb-sregs

  reg:
    maxItems: 1

  clocks:
    type: object

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    sregs@fff3c000 {
        compatible = "calxeda,hb-sregs";
        reg = <0xfff3c000 0x1000>;

        clocks {
            #address-cells = <1>;
            #size-cells = <0>;

            osc: oscillator {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                clock-frequency = <33333000>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Calxeda Highbank L2 cache ECC

description: |
  Binding for the Calxeda Highbank L2 cache controller ECC device.
  This does not cover the actual L2 cache controller control registers,
  but just the error reporting functionality.

maintainers:
  - Andre Przywara <andre.przywara@arm.com>

properties:
  compatible:
    const: "calxeda,hb-sregs-l2-ecc"

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: single bit error interrupt
      - description: double bit error interrupt

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    sregs@fff3c200 {
        compatible = "calxeda,hb-sregs-l2-ecc";
        reg = <0xfff3c200 0x100>;
        interrupts = <0 71 4>, <0 72 4>;
    };


code:
Cavium Thunder platform device tree bindings
--------------------------------------------

Boards with Cavium's Thunder SoC shall have following properties.

Root Node
---------
Required root node properties:

  - compatible = "cavium,thunder-88xx";


code:
Cavium ThunderX2 CN99XX platform tree bindings
----------------------------------------------

Boards with Cavium ThunderX2 CN99XX SoC shall have the root property:
  compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";

These SoC uses the "cavium,thunder2" core which will be compatible
with "brcm,vulcan".


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: CCI Interconnect Bus Masters binding

maintainers:
  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

description: |
  Masters in the device tree connected to a CCI port (inclusive of CPUs
  and their cpu nodes).

select: true

properties:
  cci-control-port:
    $ref: /schemas/types.yaml#/definitions/phandle

additionalProperties: true

examples:
  - |
    cpus {
        #address-cells = <1>;
        #size-cells = <0>;

        cpu@0 {
            compatible = "arm,cortex-a15";
            device_type = "cpu";
            cci-control-port = <&cci_control1>;
            reg = <0>;
        };
    };

...


code:
==========================================
ARM CPUs capacity bindings
==========================================

==========================================
1 - Introduction
==========================================

ARM systems may be configured to have cpus with different power/performance
characteristics within the same chip. In this case, additional information has
to be made available to the kernel for it to be aware of such differences and
take decisions accordingly.

==========================================
2 - CPU capacity definition
==========================================

CPU capacity is a number that provides the scheduler information about CPUs
heterogeneity. Such heterogeneity can come from micro-architectural differences
(e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run
(e.g., SMP systems with multiple frequency domains). Heterogeneity in this
context is about differing performance characteristics; this binding tries to
capture a first-order approximation of the relative performance of CPUs.

CPU capacities are obtained by running a suitable benchmark. This binding makes
no guarantees on the validity or suitability of any particular benchmark, the
final capacity should, however, be:

* A "single-threaded" or CPU affine benchmark
* Divided by the running frequency of the CPU executing the benchmark
* Not subject to dynamic frequency scaling of the CPU

For the time being we however advise usage of the Dhrystone benchmark. What
above thus becomes:

CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
max frequency (with caches enabled). The obtained DMIPS score is then divided
by the frequency (in MHz) at which the benchmark has been run, so that
DMIPS/MHz are obtained.  Such values are then normalized w.r.t. the highest
score obtained in the system.

==========================================
3 - capacity-dmips-mhz
==========================================

capacity-dmips-mhz is an optional cpu node [1] property: u32 value
representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
maximum frequency available to the cpu is then used to calculate the capacity
value internally used by the kernel.

capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
node, it has to be specified for every other cpu nodes, or the system will
fall back to the default capacity value for every CPU. If cpufreq is not
available, final capacities are calculated by directly using capacity-dmips-
mhz values (normalized w.r.t. the highest value found while parsing the DT).

===========================================
4 - Examples
===========================================

Example 1 (ARM 64-bit, 6-cpu system, two clusters):
The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
are 1024 and 578 for cluster0 and cluster1. Further normalization
is done by the operating system based on cluster0@max-freq=1100 and
cluster1@max-freq=850, final capacities are 1024 for cluster0 and
446 for cluster1 (578*850/1100).

cpus {
	#address-cells = <2>;
	#size-cells = <0>;

	cpu-map {
		cluster0 {
			core0 {
				cpu = <&A57_0>;
			};
			core1 {
				cpu = <&A57_1>;
			};
		};

		cluster1 {
			core0 {
				cpu = <&A53_0>;
			};
			core1 {
				cpu = <&A53_1>;
			};
			core2 {
				cpu = <&A53_2>;
			};
			core3 {
				cpu = <&A53_3>;
			};
		};
	};

	idle-states {
		entry-method = "psci";

		CPU_SLEEP_0: cpu-sleep-0 {
			compatible = "arm,idle-state";
			arm,psci-suspend-param = <0x0010000>;
			local-timer-stop;
			entry-latency-us = <100>;
			exit-latency-us = <250>;
			min-residency-us = <150>;
		};

		CLUSTER_SLEEP_0: cluster-sleep-0 {
			compatible = "arm,idle-state";
			arm,psci-suspend-param = <0x1010000>;
			local-timer-stop;
			entry-latency-us = <800>;
			exit-latency-us = <700>;
			min-residency-us = <2500>;
		};
	};

	A57_0: cpu@0 {
		compatible = "arm,cortex-a57";
		reg = <0x0 0x0>;
		device_type = "cpu";
		enable-method = "psci";
		next-level-cache = <&A57_L2>;
		clocks = <&scpi_dvfs 0>;
		cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		capacity-dmips-mhz = <1024>;
	};

	A57_1: cpu@1 {
		compatible = "arm,cortex-a57";
		reg = <0x0 0x1>;
		device_type = "cpu";
		enable-method = "psci";
		next-level-cache = <&A57_L2>;
		clocks = <&scpi_dvfs 0>;
		cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		capacity-dmips-mhz = <1024>;
	};

	A53_0: cpu@100 {
		compatible = "arm,cortex-a53";
		reg = <0x0 0x100>;
		device_type = "cpu";
		enable-method = "psci";
		next-level-cache = <&A53_L2>;
		clocks = <&scpi_dvfs 1>;
		cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		capacity-dmips-mhz = <578>;
	};

	A53_1: cpu@101 {
		compatible = "arm,cortex-a53";
		reg = <0x0 0x101>;
		device_type = "cpu";
		enable-method = "psci";
		next-level-cache = <&A53_L2>;
		clocks = <&scpi_dvfs 1>;
		cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		capacity-dmips-mhz = <578>;
	};

	A53_2: cpu@102 {
		compatible = "arm,cortex-a53";
		reg = <0x0 0x102>;
		device_type = "cpu";
		enable-method = "psci";
		next-level-cache = <&A53_L2>;
		clocks = <&scpi_dvfs 1>;
		cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		capacity-dmips-mhz = <578>;
	};

	A53_3: cpu@103 {
		compatible = "arm,cortex-a53";
		reg = <0x0 0x103>;
		device_type = "cpu";
		enable-method = "psci";
		next-level-cache = <&A53_L2>;
		clocks = <&scpi_dvfs 1>;
		cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
		capacity-dmips-mhz = <578>;
	};

	A57_L2: l2-cache0 {
		compatible = "cache";
	};

	A53_L2: l2-cache1 {
		compatible = "cache";
	};
};

Example 2 (ARM 32-bit, 4-cpu system, two clusters,
	   cpus 0,1@1GHz, cpus 2,3@500MHz):
capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that first
cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency)

cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a15";
		reg = <0>;
		capacity-dmips-mhz = <2>;
	};

	cpu1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a15";
		reg = <1>;
		capacity-dmips-mhz = <2>;
	};

	cpu2: cpu@2 {
		device_type = "cpu";
		compatible = "arm,cortex-a15";
		reg = <0x100>;
		capacity-dmips-mhz = <1>;
	};

	cpu3: cpu@3 {
		device_type = "cpu";
		compatible = "arm,cortex-a15";
		reg = <0x101>;
		capacity-dmips-mhz = <1>;
	};
};

===========================================
5 - References
===========================================

[1] ARM Linux Kernel documentation - CPUs bindings
    Documentation/devicetree/bindings/arm/cpus.yaml


code:
========================================================
Secondary CPU enable-method "al,alpine-smp" binding
========================================================

This document describes the "al,alpine-smp" method for
enabling secondary CPUs. To apply to all CPUs, a single
"al,alpine-smp" enable method should be defined in the
"cpus" node.

Enable method name:	"al,alpine-smp"
Compatible machines:	"al,alpine"
Compatible CPUs:	"arm,cortex-a15"
Related properties:	(none)

Note:
This enable method requires valid nodes compatible with
"al,alpine-cpu-resume" and "al,alpine-nb-service".

* Alpine CPU resume registers

The CPU resume register are used to define required resume address after
reset.

Properties:
- compatible : Should contain "al,alpine-cpu-resume".
- reg : Offset and length of the register set for the device

* Alpine System-Fabric Service Registers

The System-Fabric Service Registers allow various operation on CPU and
system fabric, like powering CPUs off.

Properties:
- compatible : Should contain "al,alpine-sysfabric-service" and "syscon".
- reg : Offset and length of the register set for the device

Example:

cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "al,alpine-smp";

	cpu@0 {
		compatible = "arm,cortex-a15";
		device_type = "cpu";
		reg = <0>;
	};

	cpu@1 {
		compatible = "arm,cortex-a15";
		device_type = "cpu";
		reg = <1>;
	};

	cpu@2 {
		compatible = "arm,cortex-a15";
		device_type = "cpu";
		reg = <2>;
	};

	cpu@3 {
		compatible = "arm,cortex-a15";
		device_type = "cpu";
		reg = <3>;
	};
};

cpu_resume {
	compatible = "al,alpine-cpu-resume";
	reg = <0xfbff5ed0 0x30>;
};

nb_service {
        compatible = "al,alpine-sysfabric-service", "syscon";
        reg = <0xfb070000 0x10000>;
};


code:
========================================================
Secondary CPU enable-method "marvell,berlin-smp" binding
========================================================

This document describes the "marvell,berlin-smp" method for enabling secondary
CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
be defined in the "cpus" node.

Enable method name:	"marvell,berlin-smp"
Compatible machines:	"marvell,berlin2" and "marvell,berlin2q"
Compatible CPUs:	"marvell,pj4b" and "arm,cortex-a9"
Related properties:	(none)

Note:
This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
"marvell,berlin-cpu-ctrl"[1].

Example:

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,berlin-smp";

		cpu@0 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;
		};

		cpu@1 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <1>;
		};
	};

--
[1] arm/marvell,berlin.txt


code:
=========================================================
Secondary CPU enable-method "nuvoton,npcm750-smp" binding
=========================================================

To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
defined in the "cpus" node.

Enable method name:	"nuvoton,npcm750-smp"
Compatible machines:	"nuvoton,npcm750"
Compatible CPUs:	"arm,cortex-a9"
Related properties:	(none)

Note:
This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
"nuvoton,npcm750-gcr".

Example:

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "nuvoton,npcm750-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			clocks = <&clk NPCM7XX_CLK_CPU>;
			clock-names = "clk_cpu";
			reg = <0>;
			next-level-cache = <&L2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			clocks = <&clk NPCM7XX_CLK_CPU>;
			clock-names = "clk_cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/cpus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM CPUs bindings

maintainers:
  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

description: |+
  The device tree allows to describe the layout of CPUs in a system through
  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
  defining properties for every cpu.

  Bindings for CPU nodes follow the Devicetree Specification, available from:

  https://www.devicetree.org/specifications/

  with updates for 32-bit and 64-bit ARM systems provided in this document.

  ================================
  Convention used in this document
  ================================

  This document follows the conventions described in the Devicetree
  Specification, with the addition:

  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
    the reg property contained in bits 7 down to 0

  =====================================
  cpus and cpu node bindings definition
  =====================================

  The ARM architecture, in accordance with the Devicetree Specification,
  requires the cpus and cpu nodes to be present and contain the properties
  described below.

properties:
  reg:
    maxItems: 1
    description: |
      Usage and definition depend on ARM architecture version and
      configuration:

      On uniprocessor ARM architectures previous to v7
      this property is required and must be set to 0.

      On ARM 11 MPcore based systems this property is
        required and matches the CPUID[11:0] register bits.

        Bits [11:0] in the reg cell must be set to
        bits [11:0] in CPU ID register.

        All other bits in the reg cell must be set to 0.

      On 32-bit ARM v7 or later systems this property is
        required and matches the CPU MPIDR[23:0] register
        bits.

        Bits [23:0] in the reg cell must be set to
        bits [23:0] in MPIDR.

        All other bits in the reg cell must be set to 0.

      On ARM v8 64-bit systems this property is required
        and matches the MPIDR_EL1 register affinity bits.

        * If cpus node's #address-cells property is set to 2

          The first reg cell bits [7:0] must be set to
          bits [39:32] of MPIDR_EL1.

          The second reg cell bits [23:0] must be set to
          bits [23:0] of MPIDR_EL1.

        * If cpus node's #address-cells property is set to 1

          The reg cell bits [23:0] must be set to bits [23:0]
          of MPIDR_EL1.

      All other bits in the reg cells must be set to 0.

  compatible:
    enum:
      - apple,icestorm
      - apple,firestorm
      - arm,arm710t
      - arm,arm720t
      - arm,arm740t
      - arm,arm7ej-s
      - arm,arm7tdmi
      - arm,arm7tdmi-s
      - arm,arm9es
      - arm,arm9ej-s
      - arm,arm920t
      - arm,arm922t
      - arm,arm925
      - arm,arm926e-s
      - arm,arm926ej-s
      - arm,arm940t
      - arm,arm946e-s
      - arm,arm966e-s
      - arm,arm968e-s
      - arm,arm9tdmi
      - arm,arm1020e
      - arm,arm1020t
      - arm,arm1022e
      - arm,arm1026ej-s
      - arm,arm1136j-s
      - arm,arm1136jf-s
      - arm,arm1156t2-s
      - arm,arm1156t2f-s
      - arm,arm1176jzf
      - arm,arm1176jz-s
      - arm,arm1176jzf-s
      - arm,arm11mpcore
      - arm,armv8 # Only for s/w models
      - arm,cortex-a5
      - arm,cortex-a7
      - arm,cortex-a8
      - arm,cortex-a9
      - arm,cortex-a12
      - arm,cortex-a15
      - arm,cortex-a17
      - arm,cortex-a32
      - arm,cortex-a34
      - arm,cortex-a35
      - arm,cortex-a53
      - arm,cortex-a55
      - arm,cortex-a57
      - arm,cortex-a65
      - arm,cortex-a72
      - arm,cortex-a73
      - arm,cortex-a75
      - arm,cortex-a76
      - arm,cortex-a77
      - arm,cortex-a78
      - arm,cortex-a78ae
      - arm,cortex-a510
      - arm,cortex-a710
      - arm,cortex-m0
      - arm,cortex-m0+
      - arm,cortex-m1
      - arm,cortex-m3
      - arm,cortex-m4
      - arm,cortex-r4
      - arm,cortex-r5
      - arm,cortex-r7
      - arm,cortex-x1
      - arm,cortex-x2
      - arm,neoverse-e1
      - arm,neoverse-n1
      - arm,neoverse-n2
      - arm,neoverse-v1
      - brcm,brahma-b15
      - brcm,brahma-b53
      - brcm,vulcan
      - cavium,thunder
      - cavium,thunder2
      - faraday,fa526
      - intel,sa110
      - intel,sa1100
      - marvell,feroceon
      - marvell,mohawk
      - marvell,pj4a
      - marvell,pj4b
      - marvell,sheeva-v5
      - marvell,sheeva-v7
      - nvidia,tegra132-denver
      - nvidia,tegra186-denver
      - nvidia,tegra194-carmel
      - qcom,krait
      - qcom,kryo
      - qcom,kryo240
      - qcom,kryo250
      - qcom,kryo260
      - qcom,kryo280
      - qcom,kryo360
      - qcom,kryo385
      - qcom,kryo468
      - qcom,kryo485
      - qcom,kryo560
      - qcom,kryo570
      - qcom,kryo660
      - qcom,kryo685
      - qcom,kryo780
      - qcom,scorpion

  enable-method:
    $ref: '/schemas/types.yaml#/definitions/string'
    oneOf:
      # On ARM v8 64-bit this property is required
      - enum:
          - psci
          - spin-table
      # On ARM 32-bit systems this property is optional
      - enum:
          - actions,s500-smp
          - allwinner,sun6i-a31
          - allwinner,sun8i-a23
          - allwinner,sun9i-a80-smp
          - allwinner,sun8i-a83t-smp
          - amlogic,meson8-smp
          - amlogic,meson8b-smp
          - arm,realview-smp
          - aspeed,ast2600-smp
          - brcm,bcm11351-cpu-method
          - brcm,bcm23550
          - brcm,bcm2836-smp
          - brcm,bcm63138
          - brcm,bcm-nsp-smp
          - brcm,brahma-b15
          - marvell,armada-375-smp
          - marvell,armada-380-smp
          - marvell,armada-390-smp
          - marvell,armada-xp-smp
          - marvell,98dx3236-smp
          - marvell,mmp3-smp
          - mediatek,mt6589-smp
          - mediatek,mt81xx-tz-smp
          - qcom,gcc-msm8660
          - qcom,kpss-acc-v1
          - qcom,kpss-acc-v2
          - qcom,msm8226-smp
          - qcom,msm8909-smp
          # Only valid on ARM 32-bit, see above for ARM v8 64-bit
          - qcom,msm8916-smp
          - renesas,apmu
          - renesas,r9a06g032-smp
          - rockchip,rk3036-smp
          - rockchip,rk3066-smp
          - socionext,milbeaut-m10v-smp
          - ste,dbx500-smp
          - ti,am3352
          - ti,am4372

  cpu-release-addr:
    oneOf:
      - $ref: '/schemas/types.yaml#/definitions/uint32'
      - $ref: '/schemas/types.yaml#/definitions/uint64'
    description:
      The DT specification defines this as 64-bit always, but some 32-bit Arm
      systems have used a 32-bit value which must be supported.
      Required for systems that have an "enable-method"
        property value of "spin-table".

  cpu-idle-states:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    items:
      maxItems: 1
    description: |
      List of phandles to idle state nodes supported
      by this cpu (see ./idle-states.yaml).

  capacity-dmips-mhz:
    description:
      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
      DMIPS/MHz, relative to highest capacity-dmips-mhz
      in the system.

  cci-control-port: true

  dynamic-power-coefficient:
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description:
      A u32 value that represents the running time dynamic
      power coefficient in units of uW/MHz/V^2. The
      coefficient can either be calculated from power
      measurements or derived by analysis.

      The dynamic power consumption of the CPU  is
      proportional to the square of the Voltage (V) and
      the clock frequency (f). The coefficient is used to
      calculate the dynamic power as below -

      Pdyn = dynamic-power-coefficient * V^2 * f

      where voltage is in V, frequency is in MHz.

  performance-domains:
    maxItems: 1
    description:
      List of phandles and performance domain specifiers, as defined by
      bindings of the performance domain provider. See also
      dvfs/performance-domain.yaml.

  power-domains:
    description:
      List of phandles and PM domain specifiers, as defined by bindings of the
      PM domain provider (see also ../power_domain.txt).

  power-domain-names:
    description:
      A list of power domain name strings sorted in the same order as the
      power-domains property.

      For PSCI based platforms, the name corresponding to the index of the PSCI
      PM domain provider, must be "psci".

  qcom,saw:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: |
      Specifies the SAW* node associated with this CPU.

      Required for systems that have an "enable-method" property
      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"

      * arm/msm/qcom,saw2.txt

  qcom,acc:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: |
      Specifies the ACC* node associated with this CPU.

      Required for systems that have an "enable-method" property
      value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
      "qcom,msm8916-smp".

      * arm/msm/qcom,kpss-acc.txt

  rockchip,pmu:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: |
      Specifies the syscon node controlling the cpu core power domains.

      Optional for systems that have an "enable-method"
      property value of "rockchip,rk3066-smp"
      While optional, it is the preferred way to get access to
      the cpu-core power-domains.

  secondary-boot-reg:
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description: |
      Required for systems that have an "enable-method" property value of
      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".

      This includes the following SoCs: |
      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312

      The secondary-boot-reg property is a u32 value that specifies the
      physical address of the register used to request the ROM holding pen
      code release a secondary CPU. The value written to the register is
      formed by encoding the target CPU id into the low bits of the
      physical start address it should jump to.

if:
  # If the enable-method property contains one of those values
  properties:
    enable-method:
      contains:
        enum:
          - brcm,bcm11351-cpu-method
          - brcm,bcm23550
          - brcm,bcm-nsp-smp
  # and if enable-method is present
  required:
    - enable-method

then:
  required:
    - secondary-boot-reg

required:
  - device_type
  - reg
  - compatible

dependencies:
  rockchip,pmu: [enable-method]

additionalProperties: true

examples:
  - |
    cpus {
      #size-cells = <0>;
      #address-cells = <1>;

      cpu@0 {
        device_type = "cpu";
        compatible = "arm,cortex-a15";
        reg = <0x0>;
      };

      cpu@1 {
        device_type = "cpu";
        compatible = "arm,cortex-a15";
        reg = <0x1>;
      };

      cpu@100 {
        device_type = "cpu";
        compatible = "arm,cortex-a7";
        reg = <0x100>;
      };

      cpu@101 {
        device_type = "cpu";
        compatible = "arm,cortex-a7";
        reg = <0x101>;
      };
    };

  - |
    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
    cpus {
      #size-cells = <0>;
      #address-cells = <1>;

      cpu@0 {
        device_type = "cpu";
        compatible = "arm,cortex-a8";
        reg = <0x0>;
      };
    };

  - |
    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
    cpus {
      #size-cells = <0>;
      #address-cells = <1>;

      cpu@0 {
        device_type = "cpu";
        compatible = "arm,arm926ej-s";
        reg = <0x0>;
      };
    };

  - |
    //  Example 4 (ARM Cortex-A57 64-bit system):
    cpus {
      #size-cells = <0>;
      #address-cells = <2>;

      cpu@0 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x0>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@1 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x1>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x100>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@101 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x101>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@10000 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x10000>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@10001 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x10001>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@10100 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x10100>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@10101 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x0 0x10101>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100000000 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x0>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100000001 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x1>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100000100 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x100>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100000101 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x101>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100010000 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x10000>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100010001 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x10001>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100010100 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x10100>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };

      cpu@100010101 {
        device_type = "cpu";
        compatible = "arm,cortex-a57";
        reg = <0x1 0x10101>;
        enable-method = "spin-table";
        cpu-release-addr = <0 0x20000000>;
      };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/digicolor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Conexant Digicolor Platforms

maintainers:
  - Baruch Siach <baruch@tkos.co.il>

properties:
  $nodename:
    const: "/"
  compatible:
    const: cnxt,cx92755

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/firmware/linaro,optee-tz.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: OP-TEE Device Tree Bindings

maintainers:
  - Jens Wiklander <jens.wiklander@linaro.org>

description: |
  OP-TEE is a piece of software using hardware features to provide a Trusted
  Execution Environment. The security can be provided with ARM TrustZone, but
  also by virtualization or a separate chip.

  We're using "linaro" as the first part of the compatible property for
  the reference implementation maintained by Linaro.

properties:
  $nodename:
    const: optee

  compatible:
    const: linaro,optee-tz

  interrupts:
    maxItems: 1
    description: |
      This interrupt which is used to signal an event by the secure world
      software is expected to be edge-triggered.

  method:
    enum: [smc, hvc]
    description: |
      The method of calling the OP-TEE Trusted OS depending on smc or hvc
      instruction usage.
      SMC #0, register assignments
      or
      HVC #0, register assignments
      register assignments are specified in drivers/tee/optee/optee_smc.h

required:
  - compatible
  - method

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    firmware  {
        optee  {
            compatible = "linaro,optee-tz";
            method = "smc";
            interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>;
        };
    };

  - |
    firmware  {
        optee  {
            compatible = "linaro,optee-tz";
            method = "hvc";
        };
    };


code:
* Software Delegated Exception Interface (SDEI)

Firmware implementing the SDEI functions described in ARM document number
ARM DEN 0054A ("Software Delegated Exception Interface") can be used by
Linux to receive notification of events such as those generated by
firmware-first error handling, or from an IRQ that has been promoted to
a firmware-assisted NMI.

The interface provides a number of API functions for registering callbacks
and enabling/disabling events. Functions are invoked by trapping to the
privilege level of the SDEI firmware (specified as part of the binding
below) and passing arguments in a manner specified by the "SMC Calling
Convention (ARM DEN 0028B):

	 r0		=> 32-bit Function ID / return value
	{r1 - r3}	=> Parameters

Note that the immediate field of the trapping instruction must be set
to #0.

The SDEI_EVENT_REGISTER function registers a callback in the kernel
text to handle the specified event number.

The sdei node should be a child node of '/firmware' and have required
properties:

 - compatible    : should contain:
	* "arm,sdei-1.0" : For implementations complying to SDEI version 1.x.

 - method        : The method of calling the SDEI firmware. Permitted
                   values are:
	* "smc" : SMC #0, with the register assignments specified in this
	          binding.
	* "hvc" : HVC #0, with the register assignments specified in this
	          binding.
Example:
	firmware {
		sdei {
			compatible	= "arm,sdei-1.0";
			method		= "smc";
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/firmware/tlm,trusted-foundations.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Trusted Foundations

description: |
  Boards that use the Trusted Foundations secure monitor can signal its
  presence by declaring a node compatible under the /firmware/ node

maintainers:
  - Stephen Warren <swarren@nvidia.com>

properties:
  $nodename:
    const: trusted-foundations

  compatible:
    const: tlm,trusted-foundations

  tlm,version-major:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: major version number of Trusted Foundations firmware

  tlm,version-minor:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: minor version number of Trusted Foundations firmware

required:
  - compatible
  - tlm,version-major
  - tlm,version-minor

additionalProperties: false

examples:
  - |
    firmware {
      trusted-foundations {
        compatible = "tlm,trusted-foundations";
        tlm,version-major = <2>;
        tlm,version-minor = <8>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-pm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX7ULP Power Management Components

maintainers:
  - A.s. Dong <aisheng.dong@nxp.com>

description: |
  The Multi-System Mode Controller (MSMC) is responsible for sequencing
  the MCU into and out of all stop and run power modes. Specifically, it
  monitors events to trigger transitions between power modes while
  controlling the power, clocks, and memories of the MCU to achieve the
  power consumption and functionality of that mode.

  The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
  Standby modes for either Cortex family. Run, Wait, and Stop are the
  common terms used for the primary operating modes of Kinetis
  microcontrollers.

properties:
  compatible:
    const: fsl,imx7ulp-smc1

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    smc1@40410000 {
        compatible = "fsl,imx7ulp-smc1";
        reg = <0x40410000 0x1000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-sim.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX7ULP System Integration Module

maintainers:
  - Anson Huang <anson.huang@nxp.com>

description: |
  The system integration module (SIM) provides system control and chip configuration
  registers. In this module, chip revision information is located in JTAG ID register,
  and a set of registers have been made available in DGO domain for SW use, with the
  objective to maintain its value between system resets.

properties:
  compatible:
    items:
      - const: fsl,imx7ulp-sim
      - const: syscon

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    sim@410a3000 {
        compatible = "fsl,imx7ulp-sim", "syscon";
        reg = <0x410a3000 0x1000>;
    };


code:
Freescale Vybrid Miscellaneous System Control - CPU Configuration

The MSCM IP contains multiple sub modules, this binding describes the first
block of registers which contains CPU configuration information.

Required properties:
- compatible:	"fsl,vf610-mscm-cpucfg", "syscon"
- reg:		the register range of the MSCM CPU configuration registers

Example:
	mscm_cpucfg: cpucfg@40001000 {
		compatible = "fsl,vf610-mscm-cpucfg", "syscon";
		reg = <0x40001000 0x800>;
	}


code:
Freescale Vybrid Miscellaneous System Control - Interrupt Router

The MSCM IP contains multiple sub modules, this binding describes the second
block of registers which control the interrupt router. The interrupt router
allows to configure the recipient of each peripheral interrupt. Furthermore
it controls the directed processor interrupts. The module is available in all
Vybrid SoC's but is only really useful in dual core configurations (VF6xx
which comes with a Cortex-A5/Cortex-M4 combination).

Required properties:
- compatible:		"fsl,vf610-mscm-ir"
- reg:			the register range of the MSCM Interrupt Router
- fsl,cpucfg:		The handle to the MSCM CPU configuration node, required
			to get the current CPU ID
- interrupt-controller:	Identifies the node as an interrupt controller
- #interrupt-cells:	Two cells, interrupt number and cells.
			The hardware interrupt number according to interrupt
			assignment of the interrupt router is required.
			Flags get passed only when using GIC as parent. Flags
			encoding as documented by the GIC bindings.

Example:
	mscm_ir: interrupt-controller@40001800 {
		compatible = "fsl,vf610-mscm-ir";
		reg = <0x40001800 0x400>;
		fsl,cpucfg = <&mscm_cpucfg>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
	}


code:
* Freescale Multi Master Multi Memory Interface (M4IF) module

Required properties:
- compatible : Should be "fsl,imx51-m4if"
- reg : Address and length of the register set for the device

Example:

m4if: m4if@83fd8000 {
	compatible = "fsl,imx51-m4if";
	reg = <0x83fd8000 0x1000>;
};


code:
* Freescale Tigerp platform module

Required properties:
- compatible : Should be "fsl,imx51-tigerp"
- reg : Address and length of the register set for the device

Example:

tigerp: tigerp@83fa0000 {
	compatible = "fsl,imx51-tigerp";
	reg = <0x83fa0000 0x28>;
};