code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 *  sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
 *
 *  Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries
 *
 *  Author: Eugen Hristev <eugen.hristev@microchip.com>
 *  Author: Claudiu Beznea <claudiu.beznea@microchip.com>
 *
 */

#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/at91-usart.h>
#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	model = "Microchip SAMA7G5 family SoC";
	compatible = "microchip,sama7g5";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>; /* min followed by max */
		};
	};

	cpu_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-90000000 {
			opp-hz = /bits/ 64 <90000000>;
			opp-microvolt = <1050000 1050000 1225000>;
			clock-latency-ns = <320000>;
		};

		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			opp-microvolt = <1050000 1050000 1225000>;
			clock-latency-ns = <320000>;
		};

		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1050000 1050000 1225000>;
			clock-latency-ns = <320000>;
			opp-suspend;
		};

		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <1150000 1125000 1225000>;
			clock-latency-ns = <320000>;
		};

		opp-1000000002 {
			opp-hz = /bits/ 64 <1000000002>;
			opp-microvolt = <1250000 1225000 1300000>;
			clock-latency-ns = <320000>;
		};
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&thermal_sensor>;

			trips {
				cpu_normal: cpu-alert0 {
					temperature = <90000>;
					hysteresis = <0>;
					type = "passive";
				};

				cpu_hot: cpu-alert1 {
					temperature = <95000>;
					hysteresis = <0>;
					type = "passive";
				};

				cpu_critical: cpu-critical {
					temperature = <100000>;
					hysteresis = <0>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_normal>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};

				map1 {
					trip = <&cpu_hot>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	clocks {
		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};

		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
		};

		usb_clk: usb_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <48000000>;
		};
	};

	vddout25: fixed-regulator-vddout25 {
		compatible = "regulator-fixed";

		regulator-name = "VDDOUT25";
		regulator-min-microvolt = <2500000>;
		regulator-max-microvolt = <2500000>;
		regulator-boot-on;
		status = "disabled";
	};

	ns_sram: sram@100000 {
		compatible = "mmio-sram";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x100000 0x20000>;
		ranges;
	};

	thermal_sensor: thermal-sensor {
		compatible = "generic-adc-thermal";
		#thermal-sensor-cells = <0>;
		io-channels = <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>;
		io-channel-names = "sensor-channel";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		nfc_sram: sram@600000 {
			compatible = "mmio-sram";
			no-memory-wc;
			reg = <0x00600000 0x2400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x00600000 0x2400>;
		};

		nfc_io: nfc-io@10000000 {
			compatible = "atmel,sama5d3-nfc-io", "syscon";
			reg = <0x10000000 0x8000000>;
		};

		ebi: ebi@40000000 {
			compatible = "atmel,sama5d3-ebi";
			#address-cells = <2>;
			#size-cells = <1>;
			atmel,smc = <&hsmc>;
			reg = <0x40000000 0x20000000>;
			ranges = <0x0 0x0 0x40000000 0x8000000
				  0x1 0x0 0x48000000 0x8000000
				  0x2 0x0 0x50000000 0x8000000
				  0x3 0x0 0x58000000 0x8000000>;
			clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>;
			status = "disabled";

			nand_controller: nand-controller {
				compatible = "atmel,sama5d3-nand-controller";
				atmel,nfc-sram = <&nfc_sram>;
				atmel,nfc-io = <&nfc_io>;
				ecc-engine = <&pmecc>;
				#address-cells = <2>;
				#size-cells = <1>;
				ranges;
				status = "disabled";
			};
		};

		securam: sram@e0000000 {
			compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram";
			reg = <0xe0000000 0x4000>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0xe0000000 0x4000>;
			no-memory-wc;
		};

		secumod: secumod@e0004000 {
			compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon";
			reg = <0xe0004000 0x4000>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		sfrbu: sfr@e0008000 {
			compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
			reg = <0xe0008000 0x20>;
		};

		pioA: pinctrl@e0014000 {
			compatible = "microchip,sama7g5-pinctrl";
			reg = <0xe0014000 0x800>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
		};

		pmc: pmc@e0018000 {
			compatible = "microchip,sama7g5-pmc", "syscon";
			reg = <0xe0018000 0x200>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			#clock-cells = <2>;
			clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
			clock-names = "td_slck", "md_slck", "main_xtal";
		};

		reset_controller: reset-controller@e001d000 {
			compatible = "microchip,sama7g5-rstc";
			reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
			#reset-cells = <1>;
			clocks = <&clk32k 0>;
		};

		shdwc: shdwc@e001d010 {
			compatible = "microchip,sama7g5-shdwc", "syscon";
			reg = <0xe001d010 0x10>;
			clocks = <&clk32k 0>;
			#address-cells = <1>;
			#size-cells = <0>;
			atmel,wakeup-rtc-timer;
			atmel,wakeup-rtt-timer;
			status = "disabled";
		};

		rtt: rtc@e001d020 {
			compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
			reg = <0xe001d020 0x30>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk32k 0>;
		};

		clk32k: clock-controller@e001d050 {
			compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
			reg = <0xe001d050 0x4>;
			clocks = <&slow_xtal>;
			#clock-cells = <1>;
		};

		gpbr: gpbr@e001d060 {
			compatible = "microchip,sama7g5-gpbr", "syscon";
			reg = <0xe001d060 0x48>;
		};

		rtc: rtc@e001d0a8 {
			compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
			reg = <0xe001d0a8 0x30>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk32k 1>;
		};

		ps_wdt: watchdog@e001d180 {
			compatible = "microchip,sama7g5-wdt";
			reg = <0xe001d180 0x24>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk32k 0>;
		};

		chipid@e0020000 {
			compatible = "microchip,sama7g5-chipid";
			reg = <0xe0020000 0x8>;
		};

		tcb1: timer@e0800000 {
			compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xe0800000 0x100>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>;
			clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
		};

		hsmc: hsmc@e0808000 {
			compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
			reg = <0xe0808000 0x1000>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pmecc: ecc-engine@e0808070 {
				compatible = "atmel,sama5d2-pmecc";
				reg = <0xe0808070 0x490>,
				      <0xe0808500 0x200>;
			};
		};

		qspi0: spi@e080c000 {
			compatible = "microchip,sama7g5-ospi";
			reg = <0xe080c000 0x400>, <0x20000000 0x10000000>;
			reg-names = "qspi_base", "qspi_mmap";
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>,
			       <&dma0 AT91_XDMAC_DT_PERID(40)>;
			dma-names = "tx", "rx";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>;
			clock-names = "pclk", "gclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		qspi1: spi@e0810000 {
			compatible = "microchip,sama7g5-qspi";
			reg = <0xe0810000 0x400>, <0x30000000 0x10000000>;
			reg-names = "qspi_base", "qspi_mmap";
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>,
			       <&dma0 AT91_XDMAC_DT_PERID(42)>;
			dma-names = "tx", "rx";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>;
			clock-names = "pclk", "gclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		can0: can@e0828000 {
			compatible = "bosch,m_can";
			reg = <0xe0828000 0x100>, <0x100000 0x7800>;
			reg-names = "m_can", "message_ram";
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "int0", "int1";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
			clock-names = "hclk", "cclk";
			assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
			assigned-clock-rates = <40000000>;
			bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
			status = "disabled";
		};

		can1: can@e082c000 {
			compatible = "bosch,m_can";
			reg = <0xe082c000 0x100>, <0x100000 0xbc00>;
			reg-names = "m_can", "message_ram";
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "int0", "int1";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
			clock-names = "hclk", "cclk";
			assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
			assigned-clock-rates = <40000000>;
			bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
			status = "disabled";
		};

		can2: can@e0830000 {
			compatible = "bosch,m_can";
			reg = <0xe0830000 0x100>, <0x100000 0x10000>;
			reg-names = "m_can", "message_ram";
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "int0", "int1";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>;
			clock-names = "hclk", "cclk";
			assigned-clocks = <&pmc PMC_TYPE_GCK 63>;
			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
			assigned-clock-rates = <40000000>;
			bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
			status = "disabled";
		};

		can3: can@e0834000 {
			compatible = "bosch,m_can";
			reg = <0xe0834000 0x100>, <0x110000 0x4400>;
			reg-names = "m_can", "message_ram";
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "int0", "int1";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>;
			clock-names = "hclk", "cclk";
			assigned-clocks = <&pmc PMC_TYPE_GCK 64>;
			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
			assigned-clock-rates = <40000000>;
			bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
			status = "disabled";
		};

		can4: can@e0838000 {
			compatible = "bosch,m_can";
			reg = <0xe0838000 0x100>, <0x110000 0x8800>;
			reg-names = "m_can", "message_ram";
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "int0", "int1";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>;
			clock-names = "hclk", "cclk";
			assigned-clocks = <&pmc PMC_TYPE_GCK 65>;
			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
			assigned-clock-rates = <40000000>;
			bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
			status = "disabled";
		};

		can5: can@e083c000 {
			compatible = "bosch,m_can";
			reg = <0xe083c000 0x100>, <0x110000 0xcc00>;
			reg-names = "m_can", "message_ram";
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "int0", "int1";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
			clock-names = "hclk", "cclk";
			assigned-clocks = <&pmc PMC_TYPE_GCK 66>;
			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
			assigned-clock-rates = <40000000>;
			bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>;
			status = "disabled";
		};

		adc: adc@e1000000 {
			compatible = "microchip,sama7g5-adc";
			reg = <0xe1000000 0x200>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_GCK 26>;
			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
			assigned-clock-rates = <100000000>;
			clock-names = "adc_clk";
			dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>;
			dma-names = "rx";
			atmel,min-sample-rate-hz = <200000>;
			atmel,max-sample-rate-hz = <20000000>;
			atmel,startup-time-ms = <4>;
			#io-channel-cells = <1>;
			nvmem-cells = <&temperature_calib>;
			nvmem-cell-names = "temperature_calib";
			status = "disabled";
		};

		sdmmc0: mmc@e1204000 {
			compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
			reg = <0xe1204000 0x4000>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
			clock-names = "hclock", "multclk";
			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
			assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
			assigned-clock-rates = <200000000>;
			microchip,sdcal-inverted;
			status = "disabled";
		};

		sdmmc1: mmc@e1208000 {
			compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
			reg = <0xe1208000 0x4000>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
			clock-names = "hclock", "multclk";
			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
			assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
			assigned-clock-rates = <200000000>;
			microchip,sdcal-inverted;
			status = "disabled";
		};

		sdmmc2: mmc@e120c000 {
			compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
			reg = <0xe120c000 0x4000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>;
			clock-names = "hclock", "multclk";
			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
			assigned-clocks = <&pmc PMC_TYPE_GCK 82>;
			assigned-clock-rates = <200000000>;
			microchip,sdcal-inverted;
			status = "disabled";
		};

		pwm: pwm@e1604000 {
			compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm";
			reg = <0xe1604000 0x4000>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			#pwm-cells = <3>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 77>;
			status = "disabled";
		};

		pdmc0: sound@e1608000 {
			compatible = "microchip,sama7g5-pdmc";
			reg = <0xe1608000 0x1000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			#sound-dai-cells = <0>;
			dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>;
			dma-names = "rx";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>;
			clock-names = "pclk", "gclk";
			status = "disabled";
		};

		pdmc1: sound@e160c000 {
			compatible = "microchip,sama7g5-pdmc";
			reg = <0xe160c000 0x1000>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			#sound-dai-cells = <0>;
			dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>;
			dma-names = "rx";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>;
			clock-names = "pclk", "gclk";
			status = "disabled";
		};

		spdifrx: spdifrx@e1614000 {
			#sound-dai-cells = <0>;
			compatible = "microchip,sama7g5-spdifrx";
			reg = <0xe1614000 0x4000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>;
			dma-names = "rx";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>;
			clock-names = "pclk", "gclk";
			status = "disabled";
		};

		spdiftx: spdiftx@e1618000 {
			#sound-dai-cells = <0>;
			compatible = "microchip,sama7g5-spdiftx";
			reg = <0xe1618000 0x4000>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>;
			dma-names = "tx";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>;
			clock-names = "pclk", "gclk";
		};

		i2s0: i2s@e161c000 {
			compatible = "microchip,sama7g5-i2smcc";
			#sound-dai-cells = <0>;
			reg = <0xe161c000 0x4000>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>;
			dma-names = "tx", "rx";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
			clock-names = "pclk", "gclk";
			status = "disabled";
		};

		i2s1: i2s@e1620000 {
			compatible = "microchip,sama7g5-i2smcc";
			#sound-dai-cells = <0>;
			reg = <0xe1620000 0x4000>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>;
			dma-names = "tx", "rx";
			clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
			clock-names = "pclk", "gclk";
			status = "disabled";
		};

		eic: interrupt-controller@e1628000 {
			compatible = "microchip,sama7g5-eic";
			reg = <0xe1628000 0xec>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
			clock-names = "pclk";
			status = "disabled";
		};

		pit64b0: timer@e1800000 {
			compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
			reg = <0xe1800000 0x4000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
			clock-names = "pclk", "gclk";
		};

		pit64b1: timer@e1804000 {
			compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
			reg = <0xe1804000 0x4000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>;
			clock-names = "pclk", "gclk";
		};

		aes: crypto@e1810000 {
			compatible = "atmel,at91sam9g46-aes";
			reg = <0xe1810000 0x100>;
			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
			clock-names = "aes_clk";
			dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
			       <&dma0 AT91_XDMAC_DT_PERID(2)>;
			dma-names = "tx", "rx";
		};

		sha: crypto@e1814000 {
			compatible = "atmel,at91sam9g46-sha";
			reg = <0xe1814000 0x100>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
			clock-names = "sha_clk";
			dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
			dma-names = "tx";
		};

		flx0: flexcom@e1818000 {
			compatible = "atmel,sama5d2-flexcom";
			reg = <0xe1818000 0x200>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xe1818000 0x800>;
			status = "disabled";

			uart0: serial@200 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0x200 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
				clock-names = "usart";
				dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>,
					<&dma1 AT91_XDMAC_DT_PERID(5)>;
				dma-names = "tx", "rx";
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				status = "disabled";
			};
		};

		flx1: flexcom@e181c000 {
			compatible = "atmel,sama5d2-flexcom";
			reg = <0xe181c000 0x200>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xe181c000 0x800>;
			status = "disabled";

			i2c1: i2c@600 {
				compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
				reg = <0x600 0x200>;
				interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
				atmel,fifo-size = <32>;
				dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>,
					<&dma0 AT91_XDMAC_DT_PERID(7)>;
				dma-names = "tx", "rx";
				status = "disabled";
			};
		};

		flx3: flexcom@e1824000 {
			compatible = "atmel,sama5d2-flexcom";
			reg = <0xe1824000 0x200>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xe1824000 0x800>;
			status = "disabled";

			uart3: serial@200 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0x200 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
				clock-names = "usart";
				dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>,
					<&dma1 AT91_XDMAC_DT_PERID(11)>;
				dma-names = "tx", "rx";
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				status = "disabled";
			};
		};

		trng: rng@e2010000 {
			compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng";
			reg = <0xe2010000 0x100>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 97>;
			status = "disabled";
		};

		tdes: crypto@e2014000 {
			compatible = "atmel,at91sam9g46-tdes";
			reg = <0xe2014000 0x100>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 96>;
			clock-names = "tdes_clk";
			dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
			       <&dma0 AT91_XDMAC_DT_PERID(53)>;
			dma-names = "tx", "rx";
		};

		flx4: flexcom@e2018000 {
			compatible = "atmel,sama5d2-flexcom";
			reg = <0xe2018000 0x200>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xe2018000 0x800>;
			status = "disabled";

			uart4: serial@200 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0x200 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
				clock-names = "usart";
				dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>,
					<&dma1 AT91_XDMAC_DT_PERID(13)>;
				dma-names = "tx", "rx";
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				atmel,fifo-size = <16>;
				status = "disabled";
			};
		};

		flx7: flexcom@e2024000 {
			compatible = "atmel,sama5d2-flexcom";
			reg = <0xe2024000 0x200>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xe2024000 0x800>;
			status = "disabled";

			uart7: serial@200 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0x200 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
				clock-names = "usart";
				dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,
					<&dma1 AT91_XDMAC_DT_PERID(19)>;
				dma-names = "tx", "rx";
				atmel,use-dma-rx;
				atmel,use-dma-tx;
				atmel,fifo-size = <16>;
				status = "disabled";
			};
		};

		gmac0: ethernet@e2800000 {
			compatible = "microchip,sama7g5-gem";
			reg = <0xe2800000 0x1000>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>;
			clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
			assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
			assigned-clock-rates = <125000000>;
			status = "disabled";
		};

		gmac1: ethernet@e2804000 {
			compatible = "microchip,sama7g5-emac";
			reg = <0xe2804000 0x1000>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
			clock-names = "pclk", "hclk";
			status = "disabled";
		};

		dma0: dma-controller@e2808000 {
			compatible = "microchip,sama7g5-dma";
			reg = <0xe2808000 0x1000>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
			clock-names = "dma_clk";
			status = "disabled";
		};

		dma1: dma-controller@e280c000 {
			compatible = "microchip,sama7g5-dma";
			reg = <0xe280c000 0x1000>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
			clock-names = "dma_clk";
			status = "disabled";
		};

		/* Place dma2 here despite it's address */
		dma2: dma-controller@e1200000 {
			compatible = "microchip,sama7g5-dma";
			reg = <0xe1200000 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
			clock-names = "dma_clk";
			dma-requests = <0>;
			status = "disabled";
		};

		tcb0: timer@e2814000 {
			compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xe2814000 0x100>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>;
			clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
		};

		flx8: flexcom@e2818000 {
			compatible = "atmel,sama5d2-flexcom";
			reg = <0xe2818000 0x200>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xe2818000 0x800>;
			status = "disabled";

			i2c8: i2c@600 {
				compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
				reg = <0x600 0x200>;
				interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
				atmel,fifo-size = <32>;
				dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>,
					<&dma0 AT91_XDMAC_DT_PERID(21)>;
				dma-names = "tx", "rx";
				status = "disabled";
			};
		};

		flx9: flexcom@e281c000 {
			compatible = "atmel,sama5d2-flexcom";
			reg = <0xe281c000 0x200>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xe281c000 0x800>;
			status = "disabled";

			i2c9: i2c@600 {
				compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
				reg = <0x600 0x200>;
				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
				atmel,fifo-size = <32>;
				dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>,
					<&dma0 AT91_XDMAC_DT_PERID(23)>;
				dma-names = "tx", "rx";
				status = "disabled";
			};
		};

		flx11: flexcom@e2824000 {
			compatible = "atmel,sama5d2-flexcom";
			reg = <0xe2824000 0x200>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0xe2824000 0x800>;
			status = "disabled";

			spi11: spi@400 {
				compatible = "atmel,at91rm9200-spi";
				reg = <0x400 0x200>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
				clock-names = "spi_clk";
				#address-cells = <1>;
				#size-cells = <0>;
				atmel,fifo-size = <32>;
				dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>,
					    <&dma0 AT91_XDMAC_DT_PERID(27)>;
				dma-names = "tx", "rx";
				status = "disabled";
			};
		};

		uddrc: uddrc@e3800000 {
			compatible = "microchip,sama7g5-uddrc";
			reg = <0xe3800000 0x4000>;
		};

		ddr3phy: ddr3phy@e3804000 {
			compatible = "microchip,sama7g5-ddr3phy";
			reg = <0xe3804000 0x1000>;
		};

		otpc: efuse@e8c00000 {
			compatible = "microchip,sama7g5-otpc", "syscon";
			reg = <0xe8c00000 0x100>;
			#address-cells = <1>;
			#size-cells = <1>;

			temperature_calib: calib@1 {
				reg = <OTP_PKT(1) 76>;
			};
		};

		gic: interrupt-controller@e8c11000 {
			compatible = "arm,cortex-a7-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0xe8c11000 0x1000>,
				<0xe8c12000 0x2000>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2020 HiSilicon Limited.
 *
 * DTS file for Hisilicon SD5203 Board
 */

/dts-v1/;

/ {
	model = "Hisilicon SD5203";
	compatible = "H836ASDJ", "hisilicon,sd5203";
	interrupt-parent = <&vic>;
	#address-cells = <1>;
	#size-cells = <1>;

	chosen {
		bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
	};

	aliases {
		serial0 = &uart0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0 {
			device_type = "cpu";
			compatible = "arm,arm926ej-s";
			reg = <0x0>;
		};
	};

	memory@30000000 {
		device_type = "memory";
		reg = <0x30000000 0x8000000>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		vic: interrupt-controller@10130000 {
			compatible = "snps,dw-apb-ictl";
			reg = <0x10130000 0x1000>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		refclk125mhz: refclk125mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <125000000>;
		};

		timer0: timer@16002000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x16002000 0x1000>;
			interrupts = <4>;
			clocks = <&refclk125mhz>;
			clock-names = "apb_pclk";
		};

		timer1: timer@16003000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x16003000 0x1000>;
			interrupts = <5>;
			clocks = <&refclk125mhz>;
			clock-names = "apb_pclk";
		};

		uart0: serial@1600d000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x1600d000 0x1000>;
			bus_id = "uart0";
			clocks = <&refclk125mhz>;
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			interrupts = <17>;
		};

		uart1: serial@1600c000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x1600c000 0x1000>;
			clocks = <&refclk125mhz>;
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			interrupts = <16>;
			status = "disabled";
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the KZM-A9-GT board
 *
 * Copyright (C) 2012 Horms Solutions Ltd.
 *
 * Based on sh73a0-kzm9g.dts
 * Copyright (C) 2012 Renesas Solutions Corp.
 */

/dts-v1/;
#include "sh73a0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "KZM-A9-GT";
	compatible = "renesas,kzm9g", "renesas,sh73a0";

	aliases {
		serial0 = &scifa4;
	};

	cpus {
		cpu@0 {
			cpu0-supply = <&vdd_dvfs>;
			operating-points = <1196000 1315000>,	/* kHz  uV */
					   < 598000 1175000>,
					   < 398667 1065000>;
			voltage-tolerance = <1>; /* 1% */
		};
	};

	chosen {
		bootargs = "root=/dev/nfs ip=on ignore_loglevel rw";
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0x20000000>;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-1.8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vmmc_sdhi0: regulator-vmmc-sdhi0 {
		compatible = "regulator-fixed";
		regulator-name = "SDHI0 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pfc 15 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vmmc_sdhi2: regulator-vmmc-sdhi2 {
		compatible = "regulator-fixed";
		regulator-name = "SDHI2 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pfc 14 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	leds {
		compatible = "gpio-leds";
		led1 {
			gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
			label = "LED1";
		};
		led2 {
			gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
			label = "LED2";
		};
		led3 {
			gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
			label = "LED3";
		};
		led4 {
			gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
			label = "LED4";
		};
	};

	keyboard {
		compatible = "gpio-keys";

		back-key {
			gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_BACK>;
			label = "SW3";
		};

		right-key {
			gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RIGHT>;
			label = "SW2-R";
		};

		left-key {
			gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_LEFT>;
			label = "SW2-L";
		};

		enter-key {
			gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_ENTER>;
			label = "SW2-P";
		};

		up-key {
			gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_UP>;
			label = "SW2-U";
		};

		down-key {
			gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_DOWN>;
			label = "SW2-D";
		};

		home-key {
			gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_HOME>;
			label = "SW1";
			wakeup-source;
		};

		wakeup-key {
			gpios = <&pfc 159 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_WAKEUP>;
			label = "NMI";
			wakeup-source;
		};
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "left_j";
		simple-audio-card,cpu {
			sound-dai = <&sh_fsi2 0>;
		};
		simple-audio-card,codec {
			sound-dai = <&ak4648>;
			bitclock-master;
			frame-master;
			system-clock-frequency = <11289600>;
		};
	};
};

&bsc {
	ethernet@10000000 {
		compatible = "smsc,lan9221", "smsc,lan9115";
		reg = <0x10000000 0x100>;
		phy-mode = "mii";
		interrupt-parent = <&irqpin0>;
		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
		reg-io-width = <4>;
		smsc,irq-push-pull;
		smsc,save-mac-address;
		vddvario-supply = <&reg_1p8v>;
		vdd33a-supply = <&reg_3p3v>;
	};
};

&cmt1 {
	status = "okay";
};

&extal2_clk {
	clock-frequency = <48000000>;
};

&i2c0 {
	status = "okay";

	compass@c {
		compatible = "asahi-kasei,ak8975";
		reg = <0x0c>;
		interrupt-parent = <&irqpin3>;
		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
	};

	ak4648: codec@12 {
		compatible = "asahi-kasei,ak4648";
		reg = <0x12>;
		#sound-dai-cells = <0>;
	};

	accelerometer@1d {
		compatible = "adi,adxl345";
		reg = <0x1d>;
		interrupt-parent = <&irqpin3>;
		interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
			     <3 IRQ_TYPE_LEVEL_HIGH>;
	};

	rtc@32 {
		compatible = "ricoh,r2025sd";
		reg = <0x32>;
	};

	as3711@40 {
		compatible = "ams,as3711";
		reg = <0x40>;

		regulators {
			vdd_dvfs: sd1 {
				regulator-name = "1.315V CPU";
				regulator-min-microvolt = <1050000>;
				regulator-max-microvolt = <1350000>;
				regulator-always-on;
				regulator-boot-on;
			};
			sd2 {
				regulator-name = "1.8V";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};
			sd4 {
				regulator-name = "1.215V";
				regulator-min-microvolt = <1215000>;
				regulator-max-microvolt = <1235000>;
				regulator-always-on;
				regulator-boot-on;
			};
			ldo2 {
				regulator-name = "2.8V CPU";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-always-on;
				regulator-boot-on;
			};
			ldo3 {
				regulator-name = "3.0V CPU";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
				regulator-boot-on;
			};
			ldo4 {
				regulator-name = "2.8V";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-always-on;
				regulator-boot-on;
			};
			ldo5 {
				regulator-name = "2.8V #2";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-always-on;
				regulator-boot-on;
			};
			ldo7 {
				regulator-name = "1.15V CPU";
				regulator-min-microvolt = <1150000>;
				regulator-max-microvolt = <1150000>;
				regulator-always-on;
				regulator-boot-on;
			};
			ldo8 {
				regulator-name = "1.15V CPU #2";
				regulator-min-microvolt = <1150000>;
				regulator-max-microvolt = <1150000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};
};

&i2c1 {
	status = "okay";

	touchscreen@55 {
		compatible = "sitronix,st1232";
		reg = <0x55>;
		interrupt-parent = <&irqpin1>;
		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
	};
};

&i2c3 {
	pinctrl-0 = <&i2c3_pins>;
	pinctrl-names = "default";
	status = "okay";

	pcf8575: gpio@20 {
		compatible = "nxp,pcf8575";
		reg = <0x20>;
		interrupt-parent = <&irqpin2>;
		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
};

&mmcif {
	pinctrl-0 = <&mmcif_pins>;
	pinctrl-names = "default";

	bus-width = <8>;
	vmmc-supply = <&reg_1p8v>;
	status = "okay";
};

&pfc {
	i2c3_pins: i2c3 {
		groups = "i2c3_1";
		function = "i2c3";
	};

	mmcif_pins: mmc {
		mux {
			groups = "mmc0_data8_0", "mmc0_ctrl_0";
			function = "mmc0";
		};
		cfg {
			groups = "mmc0_data8_0";
			pins = "PORT279";
			bias-pull-up;
		};
	};

	scifa4_pins: scifa4 {
		groups = "scifa4_data", "scifa4_ctrl";
		function = "scifa4";
	};

	sdhi0_pins: sd0 {
		groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
		function = "sdhi0";
	};

	sdhi2_pins: sd2 {
		groups = "sdhi2_data4", "sdhi2_ctrl";
		function = "sdhi2";
	};

	fsia_pins: sounda {
		groups = "fsia_mclk_in", "fsia_sclk_in",
			 "fsia_data_in", "fsia_data_out";
		function = "fsia";
	};
};

&scifa4 {
	pinctrl-0 = <&scifa4_pins>;
	pinctrl-names = "default";

	uart-has-rtscts;
	status = "okay";
};

&sdhi0 {
	pinctrl-0 = <&sdhi0_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vmmc_sdhi0>;
	bus-width = <4>;
	status = "okay";
};

&sdhi2 {
	pinctrl-0 = <&sdhi2_pins>;
	pinctrl-names = "default";

	vmmc-supply = <&vmmc_sdhi2>;
	bus-width = <4>;
	broken-cd;
	status = "okay";
};

&sh_fsi2 {
	pinctrl-0 = <&fsia_pins>;
	pinctrl-names = "default";

	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 */

#include <dt-bindings/clock/sh73a0-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,sh73a0";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <1196000000>;
			clocks = <&cpg_clocks SH73A0_CLK_Z>;
			power-domains = <&pd_a2sl>;
			next-level-cache = <&L2>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clock-frequency = <1196000000>;
			clocks = <&cpg_clocks SH73A0_CLK_Z>;
			power-domains = <&pd_a2sl>;
			next-level-cache = <&L2>;
		};
	};

	timer@f0000200 {
		compatible = "arm,cortex-a9-global-timer";
		reg = <0xf0000200 0x100>;
		interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&periph_clk>;
	};

	timer@f0000600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0xf0000600 0x20>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&periph_clk>;
	};

	gic: interrupt-controller@f0001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xf0001000 0x1000>,
		      <0xf0000100 0x100>;
	};

	L2: cache-controller@f0100000 {
		compatible = "arm,pl310-cache";
		reg = <0xf0100000 0x1000>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&pd_a3sm>;
		arm,data-latency = <3 3 3>;
		arm,tag-latency = <2 2 2>;
		arm,shared-override;
		cache-unified;
		cache-level = <2>;
	};

	sbsc2: memory-controller@fb400000 {
		compatible = "renesas,sbsc-sh73a0";
		reg = <0xfb400000 0x400>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "sec", "temp";
		power-domains = <&pd_a4bc1>;
	};

	sbsc1: memory-controller@fe400000 {
		compatible = "renesas,sbsc-sh73a0";
		reg = <0xfe400000 0x400>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "sec", "temp";
		power-domains = <&pd_a4bc0>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	cmt1: timer@e6138000 {
		compatible = "renesas,sh73a0-cmt1";
		reg = <0xe6138000 0x200>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
		clock-names = "fck";
		power-domains = <&pd_c5>;
		status = "disabled";
	};

	irqpin0: interrupt-controller@e6900000 {
		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe6900000 4>,
			<0xe6900010 4>,
			<0xe6900020 1>,
			<0xe6900040 1>,
			<0xe6900060 1>;
		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
		power-domains = <&pd_a4s>;
		control-parent;
	};

	irqpin1: interrupt-controller@e6900004 {
		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe6900004 4>,
			<0xe6900014 4>,
			<0xe6900024 1>,
			<0xe6900044 1>,
			<0xe6900064 1>;
		interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
		power-domains = <&pd_a4s>;
		control-parent;
	};

	irqpin2: interrupt-controller@e6900008 {
		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe6900008 4>,
			<0xe6900018 4>,
			<0xe6900028 1>,
			<0xe6900048 1>,
			<0xe6900068 1>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
		power-domains = <&pd_a4s>;
		control-parent;
	};

	irqpin3: interrupt-controller@e690000c {
		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0xe690000c 4>,
			<0xe690001c 4>,
			<0xe690002c 1>,
			<0xe690004c 1>,
			<0xe690006c 1>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
		power-domains = <&pd_a4s>;
		control-parent;
	};

	i2c0: i2c@e6820000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6820000 0x425>;
		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c1: i2c@e6822000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6822000 0x425>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c2: i2c@e6824000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6824000 0x425>;
		interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c3: i2c@e6826000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6826000 0x425>;
		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c4: i2c@e6828000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
		reg = <0xe6828000 0x425>;
		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
		power-domains = <&pd_c5>;
		status = "disabled";
	};

	mmcif: mmc@e6bd0000 {
		compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
		reg = <0xe6bd0000 0x100>;
		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
		power-domains = <&pd_a3sp>;
		reg-io-width = <4>;
		status = "disabled";
	};

	msiof0: spi@e6e20000 {
		compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
		reg = <0xe6e20000 0x0064>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
		power-domains = <&pd_a3sp>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	msiof1: spi@e6e10000 {
		compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
		reg = <0xe6e10000 0x0064>;
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
		power-domains = <&pd_a3sp>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	msiof2: spi@e6e00000 {
		compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
		reg = <0xe6e00000 0x0064>;
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
		power-domains = <&pd_a3sp>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	msiof3: spi@e6c90000 {
		compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
		reg = <0xe6c90000 0x0064>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
		power-domains = <&pd_a3sp>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	sdhi0: mmc@ee100000 {
		compatible = "renesas,sdhi-sh73a0";
		reg = <0xee100000 0x100>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
		power-domains = <&pd_a3sp>;
		cap-sd-highspeed;
		status = "disabled";
	};

	/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
	sdhi1: mmc@ee120000 {
		compatible = "renesas,sdhi-sh73a0";
		reg = <0xee120000 0x100>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
		power-domains = <&pd_a3sp>;
		disable-wp;
		cap-sd-highspeed;
		status = "disabled";
	};

	sdhi2: mmc@ee140000 {
		compatible = "renesas,sdhi-sh73a0";
		reg = <0xee140000 0x100>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
		power-domains = <&pd_a3sp>;
		disable-wp;
		cap-sd-highspeed;
		status = "disabled";
	};

	scifa0: serial@e6c40000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c40000 0x100>;
		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa1: serial@e6c50000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c50000 0x100>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa2: serial@e6c60000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c60000 0x100>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa3: serial@e6c70000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c70000 0x100>;
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa4: serial@e6c80000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6c80000 0x100>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa5: serial@e6cb0000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6cb0000 0x100>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa6: serial@e6cc0000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6cc0000 0x100>;
		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa7: serial@e6cd0000 {
		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
		reg = <0xe6cd0000 0x100>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifb: serial@e6c30000 {
		compatible = "renesas,scifb-sh73a0", "renesas,scifb";
		reg = <0xe6c30000 0x100>;
		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	pfc: pinctrl@e6050000 {
		compatible = "renesas,pfc-sh73a0";
		reg = <0xe6050000 0x8000>,
		      <0xe605801c 0x1c>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges =
			<&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
			<&pfc 288 288 22>;
		interrupts-extended =
			<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
			<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
			<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
			<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
			<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
			<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
			<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
			<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
		power-domains = <&pd_c5>;
	};

	sysc: system-controller@e6180000 {
		compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
		reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;

		pm-domains {
			pd_c5: c5 {
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <0>;

				pd_c4: c4@0 {
					reg = <0>;
					#power-domain-cells = <0>;
				};

				pd_d4: d4@1 {
					reg = <1>;
					#power-domain-cells = <0>;
				};

				pd_a4bc0: a4bc0@4 {
					reg = <4>;
					#power-domain-cells = <0>;
				};

				pd_a4bc1: a4bc1@5 {
					reg = <5>;
					#power-domain-cells = <0>;
				};

				pd_a4lc0: a4lc0@6 {
					reg = <6>;
					#power-domain-cells = <0>;
				};

				pd_a4lc1: a4lc1@7 {
					reg = <7>;
					#power-domain-cells = <0>;
				};

				pd_a4mp: a4mp@8 {
					reg = <8>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					pd_a3mp: a3mp@9 {
						reg = <9>;
						#power-domain-cells = <0>;
					};

					pd_a3vc: a3vc@10 {
						reg = <10>;
						#power-domain-cells = <0>;
					};
				};

				pd_a4rm: a4rm@12 {
					reg = <12>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					pd_a3r: a3r@13 {
						reg = <13>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <0>;

						pd_a2rv: a2rv@14 {
							reg = <14>;
							#address-cells = <1>;
							#size-cells = <0>;
							#power-domain-cells = <0>;
						};
					};
				};

				pd_a4s: a4s@16 {
					reg = <16>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					pd_a3sp: a3sp@17 {
						reg = <17>;
						#power-domain-cells = <0>;
					};

					pd_a3sg: a3sg@18 {
						reg = <18>;
						#power-domain-cells = <0>;
					};

					pd_a3sm: a3sm@19 {
						reg = <19>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <0>;

						pd_a2sl: a2sl@20 {
							reg = <20>;
							#power-domain-cells = <0>;
						};
					};
				};
			};
		};
	};

	sh_fsi2: sound@ec230000 {
		#sound-dai-cells = <1>;
		compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
		reg = <0xec230000 0x400>;
		interrupts = <GIC_SPI 146 0x4>;
		clocks = <&mstp3_clks SH73A0_CLK_FSI>;
		power-domains = <&pd_a4mp>;
		status = "disabled";
	};

	bsc: bus@fec10000 {
		compatible = "renesas,bsc-sh73a0", "renesas,bsc",
			     "simple-pm-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x20000000>;
		reg = <0xfec10000 0x400>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&zb_clk>;
		power-domains = <&pd_a4s>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* External root clocks */
		extalr_clk: extalr {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
		extal1_clk: extal1 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
		};
		extal2_clk: extal2 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overridden by the board. */
			clock-frequency = <0>;
		};
		extcki_clk: extcki {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value can be overridden by the board. */
			clock-frequency = <0>;
		};
		fsiack_clk: fsiack {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value can be overridden by the board. */
			clock-frequency = <0>;
		};
		fsibck_clk: fsibck {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value can be overridden by the board. */
			clock-frequency = <0>;
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@e6150000 {
			compatible = "renesas,sh73a0-cpg-clocks";
			reg = <0xe6150000 0x10000>;
			clocks = <&extal1_clk>, <&extal2_clk>;
			#clock-cells = <1>;
			clock-output-names = "main", "pll0", "pll1", "pll2",
					     "pll3", "dsi0phy", "dsi1phy",
					     "zg", "m3", "b", "m1", "m2",
					     "z", "zx", "hp";
		};

		/* Variable factor clocks (DIV6) */
		vclk1_clk: vclk1@e6150008 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150008 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
				 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
				 <0>;
			#clock-cells = <0>;
		};
		vclk2_clk: vclk2@e615000c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615000c 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
				 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
				 <0>;
			#clock-cells = <0>;
		};
		vclk3_clk: vclk3@e615001c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615001c 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
				 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
				 <0>;
			#clock-cells = <0>;
		};
		zb_clk: zb_clk@e6150010 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150010 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
			#clock-cells = <0>;
			clock-output-names = "zb";
		};
		flctl_clk: flctlck@e6150014 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150014 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
			#clock-cells = <0>;
		};
		sdhi0_clk: sdhi0ck@e6150074 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150074 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&pll1_div13_clk>, <0>;
			#clock-cells = <0>;
		};
		sdhi1_clk: sdhi1ck@e6150078 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150078 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&pll1_div13_clk>, <0>;
			#clock-cells = <0>;
		};
		sdhi2_clk: sdhi2ck@e615007c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615007c 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&pll1_div13_clk>, <0>;
			#clock-cells = <0>;
		};
		fsia_clk: fsia@e6150018 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150018 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&fsiack_clk>, <&fsiack_clk>;
			#clock-cells = <0>;
		};
		fsib_clk: fsib@e6150090 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150090 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&fsibck_clk>, <&fsibck_clk>;
			#clock-cells = <0>;
		};
		sub_clk: sub@e6150080 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150080 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&extal2_clk>, <&extal2_clk>;
			#clock-cells = <0>;
		};
		spua_clk: spua@e6150084 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150084 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&extal2_clk>, <&extal2_clk>;
			#clock-cells = <0>;
		};
		spuv_clk: spuv@e6150094 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150094 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&extal2_clk>, <&extal2_clk>;
			#clock-cells = <0>;
		};
		msu_clk: msu@e6150088 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150088 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
			#clock-cells = <0>;
		};
		hsi_clk: hsi@e615008c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615008c 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&pll1_div7_clk>, <0>;
			#clock-cells = <0>;
		};
		mfg1_clk: mfg1@e6150098 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150098 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
			#clock-cells = <0>;
		};
		mfg2_clk: mfg2@e615009c {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe615009c 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
			#clock-cells = <0>;
		};
		dsit_clk: dsit@e6150060 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150060 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
			#clock-cells = <0>;
		};
		dsi0p_clk: dsi0pck@e6150064 {
			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
			reg = <0xe6150064 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
				 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
				 <&extcki_clk>, <0>, <0>, <0>;
			#clock-cells = <0>;
		};

		/* Fixed factor clocks */
		main_div2_clk: main_div2 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};
		pll1_div2_clk: pll1_div2 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};
		pll1_div7_clk: pll1_div7 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <7>;
			clock-mult = <1>;
		};
		pll1_div13_clk: pll1_div13 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <13>;
			clock-mult = <1>;
		};
		periph_clk: periph {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks SH73A0_CLK_Z>;
			#clock-cells = <0>;
			clock-div = <4>;
			clock-mult = <1>;
		};

		/* Gate clocks */
		mstp0_clks: mstp0_clks@e6150130 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150130 4>, <0xe6150030 4>;
			clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
			>;
			clock-output-names =
				"iic2", "msiof0";
		};
		mstp1_clks: mstp1_clks@e6150134 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150134 4>, <0xe6150038 4>;
			clocks = <&cpg_clocks SH73A0_CLK_B>,
				 <&cpg_clocks SH73A0_CLK_B>,
				 <&cpg_clocks SH73A0_CLK_B>,
				 <&cpg_clocks SH73A0_CLK_B>,
				 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
				 <&cpg_clocks SH73A0_CLK_HP>,
				 <&cpg_clocks SH73A0_CLK_ZG>,
				 <&cpg_clocks SH73A0_CLK_B>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
				SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
				SH73A0_CLK_TMU0	SH73A0_CLK_DSITX0
				SH73A0_CLK_IIC0 SH73A0_CLK_SGX
				SH73A0_CLK_LCDC0
			>;
			clock-output-names =
				"ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
				"tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
		};
		mstp2_clks: mstp2_clks@e6150138 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150138 4>, <0xe6150040 4>;
			clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
				 <&sub_clk>, <&sub_clk>, <&sub_clk>,
				 <&sub_clk>, <&sub_clk>, <&sub_clk>,
				 <&sub_clk>, <&sub_clk>, <&sub_clk>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
				SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
				SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
				SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
				SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
				SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
				SH73A0_CLK_SCIFA4
			>;
			clock-output-names =
				"scifa7", "sy_dmac", "mp_dmac", "msiof3",
				"msiof1", "scifa5", "scifb", "msiof2",
				"scifa0", "scifa1", "scifa2", "scifa3",
				"scifa4";
		};
		mstp3_clks: mstp3_clks@e615013c {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe615013c 4>, <0xe6150048 4>;
			clocks = <&sub_clk>, <&extalr_clk>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
				 <&cpg_clocks SH73A0_CLK_HP>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
				 <&sdhi0_clk>, <&sdhi1_clk>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
				 <&main_div2_clk>, <&main_div2_clk>,
				 <&main_div2_clk>, <&main_div2_clk>,
				 <&main_div2_clk>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
				SH73A0_CLK_FSI SH73A0_CLK_IRDA
				SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
				SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
				SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
				SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
				SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
				SH73A0_CLK_TPU4
			>;
			clock-output-names =
				"scifa6", "cmt1", "fsi", "irda", "iic1",
				"usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
				"tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
		};
		mstp4_clks: mstp4_clks@e6150140 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150140 4>, <0xe615004c 4>;
			clocks = <&cpg_clocks SH73A0_CLK_HP>,
				 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
				SH73A0_CLK_KEYSC
			>;
			clock-output-names =
				"iic3", "iic4", "keysc";
		};
		mstp5_clks: mstp5_clks@e6150144 {
			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xe6150144 4>, <0xe615003c 4>;
			clocks = <&cpg_clocks SH73A0_CLK_HP>;
			#clock-cells = <1>;
			clock-indices = <
				SH73A0_CLK_INTCA0
			>;
			clock-output-names =
				"intca0";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2012 Altera <www.altera.com>
 */

#include <dt-bindings/reset/altr,rst-mgr.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		timer0 = &timer0;
		timer1 = &timer1;
		timer2 = &timer2;
		timer3 = &timer3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "altr,socfpga-smp";

		cpu0: cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
		};
		cpu1: cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};
	};

	pmu: pmu@ff111000 {
		compatible = "arm,cortex-a9-pmu";
		interrupt-parent = <&intc>;
		interrupts = <0 176 4>, <0 177 4>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
		reg = <0xff111000 0x1000>,
		      <0xff113000 0x1000>;
	};

	intc: interrupt-controller@fffed000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xfffed000 0x1000>,
		      <0xfffec100 0x100>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges;

		amba {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pdma: pdma@ffe01000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0xffe01000 0x1000>;
				interrupts = <0 104 4>,
					     <0 105 4>,
					     <0 106 4>,
					     <0 107 4>,
					     <0 108 4>,
					     <0 109 4>,
					     <0 110 4>,
					     <0 111 4>;
				#dma-cells = <1>;
				clocks = <&l4_main_clk>;
				clock-names = "apb_pclk";
				resets = <&rst DMA_RESET>;
				reset-names = "dma";
			};
		};

		base_fpga_region {
			compatible = "fpga-region";
			fpga-mgr = <&fpgamgr0>;

			#address-cells = <0x1>;
			#size-cells = <0x1>;
		};

		can0: can@ffc00000 {
			compatible = "bosch,d_can";
			reg = <0xffc00000 0x1000>;
			interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
			clocks = <&can0_clk>;
			resets = <&rst CAN0_RESET>;
			status = "disabled";
		};

		can1: can@ffc01000 {
			compatible = "bosch,d_can";
			reg = <0xffc01000 0x1000>;
			interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
			clocks = <&can1_clk>;
			resets = <&rst CAN1_RESET>;
			status = "disabled";
		};

		clkmgr@ffd04000 {
				compatible = "altr,clk-mgr";
				reg = <0xffd04000 0x1000>;

				clocks {
					#address-cells = <1>;
					#size-cells = <0>;

					osc1: osc1 {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					osc2: osc2 {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					f2s_periph_ref_clk: f2s_periph_ref_clk {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					f2s_sdram_ref_clk: f2s_sdram_ref_clk {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					main_pll: main_pll@40 {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-pll-clock";
						clocks = <&osc1>;
						reg = <0x40>;

						mpuclk: mpuclk@48 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							div-reg = <0xe0 0 9>;
							reg = <0x48>;
						};

						mainclk: mainclk@4c {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							div-reg = <0xe4 0 9>;
							reg = <0x4C>;
						};

						dbg_base_clk: dbg_base_clk@50 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>, <&osc1>;
							div-reg = <0xe8 0 9>;
							reg = <0x50>;
						};

						main_qspi_clk: main_qspi_clk@54 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							reg = <0x54>;
						};

						main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							reg = <0x58>;
						};

						cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							reg = <0x5C>;
						};
					};

					periph_pll: periph_pll@80 {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-pll-clock";
						clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
						reg = <0x80>;

						emac0_clk: emac0_clk@88 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x88>;
						};

						emac1_clk: emac1_clk@8c {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x8C>;
						};

						per_qspi_clk: per_qsi_clk@90 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x90>;
						};

						per_nand_mmc_clk: per_nand_mmc_clk@94 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x94>;
						};

						per_base_clk: per_base_clk@98 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x98>;
						};

						h2f_usr1_clk: h2f_usr1_clk@9c {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x9C>;
						};
					};

					sdram_pll: sdram_pll@c0 {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-pll-clock";
						clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
						reg = <0xC0>;

						ddr_dqs_clk: ddr_dqs_clk@c8 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&sdram_pll>;
							reg = <0xC8>;
						};

						ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&sdram_pll>;
							reg = <0xCC>;
						};

						ddr_dq_clk: ddr_dq_clk@d0 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&sdram_pll>;
							reg = <0xD0>;
						};

						h2f_usr2_clk: h2f_usr2_clk@d4 {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&sdram_pll>;
							reg = <0xD4>;
						};
					};

					mpu_periph_clk: mpu_periph_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-perip-clk";
						clocks = <&mpuclk>;
						fixed-divider = <4>;
					};

					mpu_l2_ram_clk: mpu_l2_ram_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-perip-clk";
						clocks = <&mpuclk>;
						fixed-divider = <2>;
					};

					l4_main_clk: l4_main_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&mainclk>;
						clk-gate = <0x60 0>;
					};

					l3_main_clk: l3_main_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-perip-clk";
						clocks = <&mainclk>;
						fixed-divider = <1>;
					};

					l3_mp_clk: l3_mp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&mainclk>;
						div-reg = <0x64 0 2>;
						clk-gate = <0x60 1>;
					};

					l3_sp_clk: l3_sp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&l3_mp_clk>;
						div-reg = <0x64 2 2>;
					};

					l4_mp_clk: l4_mp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&mainclk>, <&per_base_clk>;
						div-reg = <0x64 4 3>;
						clk-gate = <0x60 2>;
					};

					l4_sp_clk: l4_sp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&mainclk>, <&per_base_clk>;
						div-reg = <0x64 7 3>;
						clk-gate = <0x60 3>;
					};

					dbg_at_clk: dbg_at_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&dbg_base_clk>;
						div-reg = <0x68 0 2>;
						clk-gate = <0x60 4>;
					};

					dbg_clk: dbg_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&dbg_at_clk>;
						div-reg = <0x68 2 2>;
						clk-gate = <0x60 5>;
					};

					dbg_trace_clk: dbg_trace_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&dbg_base_clk>;
						div-reg = <0x6C 0 3>;
						clk-gate = <0x60 6>;
					};

					dbg_timer_clk: dbg_timer_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&dbg_base_clk>;
						clk-gate = <0x60 7>;
					};

					cfg_clk: cfg_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&cfg_h2f_usr0_clk>;
						clk-gate = <0x60 8>;
					};

					h2f_user0_clk: h2f_user0_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&cfg_h2f_usr0_clk>;
						clk-gate = <0x60 9>;
					};

					emac_0_clk: emac_0_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&emac0_clk>;
						clk-gate = <0xa0 0>;
					};

					emac_1_clk: emac_1_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&emac1_clk>;
						clk-gate = <0xa0 1>;
					};

					usb_mp_clk: usb_mp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&per_base_clk>;
						clk-gate = <0xa0 2>;
						div-reg = <0xa4 0 3>;
					};

					spi_m_clk: spi_m_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&per_base_clk>;
						clk-gate = <0xa0 3>;
						div-reg = <0xa4 3 3>;
					};

					can0_clk: can0_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&per_base_clk>;
						clk-gate = <0xa0 4>;
						div-reg = <0xa4 6 3>;
					};

					can1_clk: can1_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&per_base_clk>;
						clk-gate = <0xa0 5>;
						div-reg = <0xa4 9 3>;
					};

					gpio_db_clk: gpio_db_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&per_base_clk>;
						clk-gate = <0xa0 6>;
						div-reg = <0xa8 0 24>;
					};

					h2f_user1_clk: h2f_user1_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&h2f_usr1_clk>;
						clk-gate = <0xa0 7>;
					};

					sdmmc_clk: sdmmc_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
						clk-gate = <0xa0 8>;
					};

					sdmmc_clk_divided: sdmmc_clk_divided {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&sdmmc_clk>;
						clk-gate = <0xa0 8>;
						fixed-divider = <4>;
					};

					nand_x_clk: nand_x_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
						clk-gate = <0xa0 9>;
					};

					nand_ecc_clk: nand_ecc_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&nand_x_clk>;
						clk-gate = <0xa0 9>;
					};

					nand_clk: nand_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&nand_x_clk>;
						clk-gate = <0xa0 10>;
						fixed-divider = <4>;
					};

					qspi_clk: qspi_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
						clk-gate = <0xa0 11>;
					};

					ddr_dqs_clk_gate: ddr_dqs_clk_gate {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&ddr_dqs_clk>;
						clk-gate = <0xd8 0>;
					};

					ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&ddr_2x_dqs_clk>;
						clk-gate = <0xd8 1>;
					};

					ddr_dq_clk_gate: ddr_dq_clk_gate {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&ddr_dq_clk>;
						clk-gate = <0xd8 2>;
					};

					h2f_user2_clk: h2f_user2_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&h2f_usr2_clk>;
						clk-gate = <0xd8 3>;
					};

				};
		};

		fpga_bridge0: fpga_bridge@ff400000 {
			compatible = "altr,socfpga-lwhps2fpga-bridge";
			reg = <0xff400000 0x100000>;
			resets = <&rst LWHPS2FPGA_RESET>;
			clocks = <&l4_main_clk>;
			status = "disabled";
		};

		fpga_bridge1: fpga_bridge@ff500000 {
			compatible = "altr,socfpga-hps2fpga-bridge";
			reg = <0xff500000 0x10000>;
			resets = <&rst HPS2FPGA_RESET>;
			clocks = <&l4_main_clk>;
			status = "disabled";
		};

		fpga_bridge2: fpga-bridge@ff600000 {
			compatible = "altr,socfpga-fpga2hps-bridge";
			reg = <0xff600000 0x100000>;
			resets = <&rst FPGA2HPS_RESET>;
			clocks = <&l4_main_clk>;
			status = "disabled";
		};

		fpga_bridge3: fpga-bridge@ffc25080 {
			compatible = "altr,socfpga-fpga2sdram-bridge";
			reg = <0xffc25080 0x4>;
			status = "disabled";
		};

		fpgamgr0: fpgamgr@ff706000 {
			compatible = "altr,socfpga-fpga-mgr";
			reg = <0xff706000 0x1000
			       0xffb90000 0x4>;
			interrupts = <0 175 4>;
		};

		socfpga_axi_setup: stmmac-axi-config {
			snps,wr_osr_lmt = <0xf>;
			snps,rd_osr_lmt = <0xf>;
			snps,blen = <0 0 0 0 16 0 0>;
		};

		gmac0: ethernet@ff700000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
			altr,sysmgr-syscon = <&sysmgr 0x60 0>;
			reg = <0xff700000 0x2000>;
			interrupts = <0 115 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
			clocks = <&emac_0_clk>;
			clock-names = "stmmaceth";
			resets = <&rst EMAC0_RESET>;
			reset-names = "stmmaceth";
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <4096>;
			rx-fifo-depth = <4096>;
			snps,axi-config = <&socfpga_axi_setup>;
			status = "disabled";
		};

		gmac1: ethernet@ff702000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
			altr,sysmgr-syscon = <&sysmgr 0x60 2>;
			reg = <0xff702000 0x2000>;
			interrupts = <0 120 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
			clocks = <&emac_1_clk>;
			clock-names = "stmmaceth";
			resets = <&rst EMAC1_RESET>;
			reset-names = "stmmaceth";
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <4096>;
			rx-fifo-depth = <4096>;
			snps,axi-config = <&socfpga_axi_setup>;
			status = "disabled";
		};

		gpio0: gpio@ff708000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xff708000 0x1000>;
			clocks = <&l4_mp_clk>;
			resets = <&rst GPIO0_RESET>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <29>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 164 4>;
			};
		};

		gpio1: gpio@ff709000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xff709000 0x1000>;
			clocks = <&l4_mp_clk>;
			resets = <&rst GPIO1_RESET>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <29>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 165 4>;
			};
		};

		gpio2: gpio@ff70a000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xff70a000 0x1000>;
			clocks = <&l4_mp_clk>;
			resets = <&rst GPIO2_RESET>;
			status = "disabled";

			portc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <27>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 166 4>;
			};
		};

		i2c0: i2c@ffc04000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc04000 0x1000>;
			resets = <&rst I2C0_RESET>;
			clocks = <&l4_sp_clk>;
			interrupts = <0 158 0x4>;
			status = "disabled";
		};

		i2c1: i2c@ffc05000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc05000 0x1000>;
			resets = <&rst I2C1_RESET>;
			clocks = <&l4_sp_clk>;
			interrupts = <0 159 0x4>;
			status = "disabled";
		};

		i2c2: i2c@ffc06000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc06000 0x1000>;
			resets = <&rst I2C2_RESET>;
			clocks = <&l4_sp_clk>;
			interrupts = <0 160 0x4>;
			status = "disabled";
		};

		i2c3: i2c@ffc07000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc07000 0x1000>;
			resets = <&rst I2C3_RESET>;
			clocks = <&l4_sp_clk>;
			interrupts = <0 161 0x4>;
			status = "disabled";
		};

		eccmgr: eccmgr {
			compatible = "altr,socfpga-ecc-manager";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			l2-ecc@ffd08140 {
				compatible = "altr,socfpga-l2-ecc";
				reg = <0xffd08140 0x4>;
				interrupts = <0 36 1>, <0 37 1>;
			};

			ocram-ecc@ffd08144 {
				compatible = "altr,socfpga-ocram-ecc";
				reg = <0xffd08144 0x4>;
				iram = <&ocram>;
				interrupts = <0 178 1>, <0 179 1>;
			};
		};

		L2: cache-controller@fffef000 {
			compatible = "arm,pl310-cache";
			reg = <0xfffef000 0x1000>;
			interrupts = <0 38 0x04>;
			cache-unified;
			cache-level = <2>;
			arm,tag-latency = <1 1 1>;
			arm,data-latency = <2 1 1>;
			prefetch-data = <1>;
			prefetch-instr = <1>;
			arm,shared-override;
			arm,double-linefill = <1>;
			arm,double-linefill-incr = <0>;
			arm,double-linefill-wrap = <1>;
			arm,prefetch-drop = <0>;
			arm,prefetch-offset = <7>;
		};

		l3regs@0xff800000 {
			compatible = "altr,l3regs", "syscon";
			reg = <0xff800000 0x1000>;
		};

		mmc: mmc@ff704000 {
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff704000 0x1000>;
			interrupts = <0 139 4>;
			fifo-depth = <0x400>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
			clock-names = "biu", "ciu";
			resets = <&rst SDMMC_RESET>;
			altr,sysmgr-syscon = <&sysmgr 0x108 3>;
			status = "disabled";
		};

		nand0: nand@ff900000 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "altr,socfpga-denali-nand";
			reg = <0xff900000 0x100000>,
			      <0xffb80000 0x10000>;
			reg-names = "nand_data", "denali_reg";
			interrupts = <0x0 0x90 0x4>;
			clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
			clock-names = "nand", "nand_x", "ecc";
			resets = <&rst NAND_RESET>;
			status = "disabled";
		};

		ocram: sram@ffff0000 {
			compatible = "mmio-sram";
			reg = <0xffff0000 0x10000>;
		};

		qspi: spi@ff705000 {
			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xff705000 0x1000>,
			      <0xffa00000 0x1000>;
			interrupts = <0 151 4>;
			cdns,fifo-depth = <128>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x00000000>;
			clocks = <&qspi_clk>;
			resets = <&rst QSPI_RESET>;
			status = "disabled";
		};

		rst: rstmgr@ffd05000 {
			#reset-cells = <1>;
			compatible = "altr,rst-mgr";
			reg = <0xffd05000 0x1000>;
			altr,modrst-offset = <0x10>;
		};

		scu: snoop-control-unit@fffec000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xfffec000 0x100>;
		};

		sdr: sdr@ffc25000 {
			compatible = "altr,sdr-ctl", "syscon";
			reg = <0xffc25000 0x1000>;
			resets = <&rst SDR_RESET>;
		};

		sdramedac {
			compatible = "altr,sdram-edac";
			altr,sdr-syscon = <&sdr>;
			interrupts = <0 39 4>;
		};

		spi0: spi@fff00000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xfff00000 0x1000>;
			interrupts = <0 154 4>;
			num-cs = <4>;
			clocks = <&spi_m_clk>;
			resets = <&rst SPIM0_RESET>;
			reset-names = "spi";
			status = "disabled";
		};

		spi1: spi@fff01000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xfff01000 0x1000>;
			interrupts = <0 155 4>;
			num-cs = <4>;
			clocks = <&spi_m_clk>;
			resets = <&rst SPIM1_RESET>;
			reset-names = "spi";
			status = "disabled";
		};

		sysmgr: sysmgr@ffd08000 {
			compatible = "altr,sys-mgr", "syscon";
			reg = <0xffd08000 0x4000>;
		};

		/* Local timer */
		timer@fffec600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xfffec600 0x100>;
			interrupts = <1 13 0xf01>;
			clocks = <&mpu_periph_clk>;
		};

		timer0: timer0@ffc08000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 167 4>;
			reg = <0xffc08000 0x1000>;
			clocks = <&l4_sp_clk>;
			clock-names = "timer";
			resets = <&rst SPTIMER0_RESET>;
			reset-names = "timer";
		};

		timer1: timer1@ffc09000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 168 4>;
			reg = <0xffc09000 0x1000>;
			clocks = <&l4_sp_clk>;
			clock-names = "timer";
			resets = <&rst SPTIMER1_RESET>;
			reset-names = "timer";
		};

		timer2: timer2@ffd00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 169 4>;
			reg = <0xffd00000 0x1000>;
			clocks = <&osc1>;
			clock-names = "timer";
			resets = <&rst OSC1TIMER0_RESET>;
			reset-names = "timer";
		};

		timer3: timer3@ffd01000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 170 4>;
			reg = <0xffd01000 0x1000>;
			clocks = <&osc1>;
			clock-names = "timer";
			resets = <&rst OSC1TIMER1_RESET>;
			reset-names = "timer";
		};

		uart0: serial0@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x1000>;
			interrupts = <0 162 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&l4_sp_clk>;
			dmas = <&pdma 28>,
			       <&pdma 29>;
			dma-names = "tx", "rx";
			resets = <&rst UART0_RESET>;
		};

		uart1: serial1@ffc03000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc03000 0x1000>;
			interrupts = <0 163 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&l4_sp_clk>;
			dmas = <&pdma 30>,
			       <&pdma 31>;
			dma-names = "tx", "rx";
			resets = <&rst UART1_RESET>;
		};

		usbphy0: usbphy {
			#phy-cells = <0>;
			compatible = "usb-nop-xceiv";
			status = "okay";
		};

		usb0: usb@ffb00000 {
			compatible = "snps,dwc2";
			reg = <0xffb00000 0xffff>;
			interrupts = <0 125 4>;
			clocks = <&usb_mp_clk>;
			clock-names = "otg";
			resets = <&rst USB0_RESET>;
			reset-names = "dwc2";
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		usb1: usb@ffb40000 {
			compatible = "snps,dwc2";
			reg = <0xffb40000 0xffff>;
			interrupts = <0 128 4>;
			clocks = <&usb_mp_clk>;
			clock-names = "otg";
			resets = <&rst USB1_RESET>;
			reset-names = "dwc2";
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			status = "disabled";
		};

		watchdog0: watchdog@ffd02000 {
			compatible = "snps,dw-wdt";
			reg = <0xffd02000 0x1000>;
			interrupts = <0 171 4>;
			clocks = <&osc1>;
			resets = <&rst L4WD0_RESET>;
			status = "disabled";
		};

		watchdog1: watchdog@ffd03000 {
			compatible = "snps,dw-wdt";
			reg = <0xffd03000 0x1000>;
			interrupts = <0 172 4>;
			clocks = <&osc1>;
			resets = <&rst L4WD1_RESET>;
			status = "disabled";
		};
	};
};