code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra20 SoC External Memory Controller

maintainers:
  - Dmitry Osipenko <digetx@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
  service the request stream sent from Memory Controller. The EMC also has
  various performance-affecting settings beyond the obvious SDRAM configuration
  parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
  standard protocols: DDR1, LPDDR2 and DDR2.

properties:
  compatible:
    const: nvidia,tegra20-emc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  "#interconnect-cells":
    const: 0

  nvidia,memory-controller:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle of the Memory Controller node.

  power-domains:
    maxItems: 1
    description:
      Phandle of the SoC "core" power domain.

  operating-points-v2:
    description:
      Should contain freqs and voltages and opp-supported-hw property, which
      is a bitfield indicating SoC process ID mask.

  nvidia,use-ram-code:
    type: boolean
    description:
      If present, the emc-tables@ sub-nodes will be addressed.

$defs:
  emc-table:
    type: object
    properties:
      compatible:
        const: nvidia,tegra20-emc-table

      clock-frequency:
        description:
          Memory clock rate in kHz.
        minimum: 1000
        maximum: 900000

      reg:
        maxItems: 1
        description:
          Either an opaque enumerator to tell different tables apart, or
          the valid frequency for which the table should be used (in kHz).

      nvidia,emc-registers:
        description:
          EMC timing characterization data. These are the registers
          (see section "15.4.1 EMC Registers" in the TRM) whose values
          need to be specified, according to the board documentation.
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - description: EMC_RC
          - description: EMC_RFC
          - description: EMC_RAS
          - description: EMC_RP
          - description: EMC_R2W
          - description: EMC_W2R
          - description: EMC_R2P
          - description: EMC_W2P
          - description: EMC_RD_RCD
          - description: EMC_WR_RCD
          - description: EMC_RRD
          - description: EMC_REXT
          - description: EMC_WDV
          - description: EMC_QUSE
          - description: EMC_QRST
          - description: EMC_QSAFE
          - description: EMC_RDV
          - description: EMC_REFRESH
          - description: EMC_BURST_REFRESH_NUM
          - description: EMC_PDEX2WR
          - description: EMC_PDEX2RD
          - description: EMC_PCHG2PDEN
          - description: EMC_ACT2PDEN
          - description: EMC_AR2PDEN
          - description: EMC_RW2PDEN
          - description: EMC_TXSR
          - description: EMC_TCKE
          - description: EMC_TFAW
          - description: EMC_TRPAB
          - description: EMC_TCLKSTABLE
          - description: EMC_TCLKSTOP
          - description: EMC_TREFBW
          - description: EMC_QUSE_EXTRA
          - description: EMC_FBIO_CFG6
          - description: EMC_ODT_WRITE
          - description: EMC_ODT_READ
          - description: EMC_FBIO_CFG5
          - description: EMC_CFG_DIG_DLL
          - description: EMC_DLL_XFORM_DQS
          - description: EMC_DLL_XFORM_QUSE
          - description: EMC_ZCAL_REF_CNT
          - description: EMC_ZCAL_WAIT_CNT
          - description: EMC_AUTO_CAL_INTERVAL
          - description: EMC_CFG_CLKTRIM_0
          - description: EMC_CFG_CLKTRIM_1
          - description: EMC_CFG_CLKTRIM_2

    required:
      - clock-frequency
      - compatible
      - reg
      - nvidia,emc-registers

    additionalProperties: false

patternProperties:
  "^emc-table@[0-9]+$":
    $ref: "#/$defs/emc-table"

  "^emc-tables@[a-z0-9-]+$":
    type: object
    properties:
      reg:
        maxItems: 1
        description:
          An opaque enumerator to tell different tables apart.

      nvidia,ram-code:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Value of RAM_CODE this timing set is used for.

      "#address-cells":
        const: 1

      "#size-cells":
        const: 0

      lpddr2:
        $ref: "ddr/jedec,lpddr2.yaml#"
        type: object

    patternProperties:
      "^emc-table@[0-9]+$":
        $ref: "#/$defs/emc-table"

    oneOf:
      - required:
          - nvidia,ram-code

      - required:
          - lpddr2

    additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - nvidia,memory-controller
  - "#interconnect-cells"
  - operating-points-v2

additionalProperties: false

examples:
  - |
    external-memory-controller@7000f400 {
        compatible = "nvidia,tegra20-emc";
        reg = <0x7000f400 0x400>;
        interrupts = <0 78 4>;
        clocks = <&clock_controller 57>;

        nvidia,memory-controller = <&mc>;
        operating-points-v2 = <&dvfs_opp_table>;
        power-domains = <&domain>;

        #interconnect-cells = <0>;
        #address-cells = <1>;
        #size-cells = <0>;

        nvidia,use-ram-code;

        emc-tables@0 {
            nvidia,ram-code = <0>;
            reg = <0>;

            #address-cells = <1>;
            #size-cells = <0>;

            emc-table@333000 {
                reg = <333000>;
                compatible = "nvidia,tegra20-emc-table";
                clock-frequency = <333000>;
                nvidia,emc-registers = <0x00000018 0x00000033
                        0x00000012 0x00000004 0x00000004 0x00000005
                        0x00000003 0x0000000c 0x00000006 0x00000006
                        0x00000003 0x00000001 0x00000004 0x00000005
                        0x00000004 0x00000009 0x0000000d 0x00000bff
                        0x00000000 0x00000003 0x00000003 0x00000006
                        0x00000006 0x00000001 0x00000011 0x000000c8
                        0x00000003 0x0000000e 0x00000007 0x00000008
                        0x00000002 0x00000000 0x00000000 0x00000002
                        0x00000000 0x00000000 0x00000083 0xf0440303
                        0x007fe010 0x00001414 0x00000000 0x00000000
                        0x00000000 0x00000000 0x00000000 0x00000000>;
            };
        };

        emc-tables@1 {
            reg = <1>;

            lpddr2 {
                compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
                revision-id1 = <1>;
                density = <2048>;
                io-width = <16>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra20 SoC Memory Controller

maintainers:
  - Dmitry Osipenko <digetx@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  The Tegra20 Memory Controller merges request streams from various client
  interfaces into request stream(s) for the various memory target devices,
  and returns response data to the various clients. The Memory Controller
  has a configurable arbitration algorithm to allow the user to fine-tune
  performance among the various clients.

  Tegra20 Memory Controller includes the GART (Graphics Address Relocation
  Table) which allows Memory Controller to provide a linear view of a
  fragmented memory pages.

properties:
  compatible:
    const: nvidia,tegra20-mc-gart

  reg:
    items:
      - description: controller registers
      - description: GART registers

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: mc

  interrupts:
    maxItems: 1

  "#reset-cells":
    const: 1

  "#iommu-cells":
    const: 0

  "#interconnect-cells":
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - "#reset-cells"
  - "#iommu-cells"
  - "#interconnect-cells"

additionalProperties: false

examples:
  - |
    memory-controller@7000f000 {
        compatible = "nvidia,tegra20-mc-gart";
        reg = <0x7000f000 0x400>,	/* Controller registers */
              <0x58000000 0x02000000>;	/* GART aperture */
        clocks = <&clock_controller 32>;
        clock-names = "mc";

        interrupts = <0 77 4>;

        #iommu-cells = <0>;
        #reset-cells = <1>;
        #interconnect-cells = <1>;
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra210 SoC External Memory Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: |
  The EMC interfaces with the off-chip SDRAM to service the request stream
  sent from the memory controller.

properties:
  compatible:
    const: nvidia,tegra210-emc

  reg:
    maxItems: 3

  clocks:
    items:
      - description: external memory clock

  clock-names:
    items:
      - const: emc

  interrupts:
    items:
      - description: EMC general interrupt

  memory-region:
    maxItems: 1
    description:
      phandle to a reserved memory region describing the table of EMC
      frequencies trained by the firmware

  nvidia,memory-controller:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle of the memory controller node

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - nvidia,memory-controller

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    reserved-memory {
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        emc_table: emc-table@83400000 {
            compatible = "nvidia,tegra210-emc-table";
            reg = <0x83400000 0x10000>;
        };
    };

    external-memory-controller@7001b000 {
        compatible = "nvidia,tegra210-emc";
        reg = <0x7001b000 0x1000>,
              <0x7001e000 0x1000>,
              <0x7001f000 0x1000>;
        clocks = <&tegra_car TEGRA210_CLK_EMC>;
        clock-names = "emc";
        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
        memory-region = <&emc_table>;
        nvidia,memory-controller = <&mc>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra30 SoC External Memory Controller

maintainers:
  - Dmitry Osipenko <digetx@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  The EMC interfaces with the off-chip SDRAM to service the request stream
  sent from Memory Controller. The EMC also has various performance-affecting
  settings beyond the obvious SDRAM configuration parameters and initialization
  settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
  LPDDR3, and DDR3.

properties:
  compatible:
    const: nvidia,tegra30-emc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#interconnect-cells":
    const: 0

  nvidia,memory-controller:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle of the Memory Controller node.

  power-domains:
    maxItems: 1
    description:
      Phandle of the SoC "core" power domain.

  operating-points-v2:
    description:
      Should contain freqs and voltages and opp-supported-hw property, which
      is a bitfield indicating SoC speedo ID mask.

patternProperties:
  "^emc-timings-[0-9]+$":
    type: object
    properties:
      nvidia,ram-code:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Value of RAM_CODE this timing set is used for.

    patternProperties:
      "^timing-[0-9]+$":
        type: object
        properties:
          clock-frequency:
            description:
              Memory clock rate in Hz.
            minimum: 1000000
            maximum: 900000000

          nvidia,emc-auto-cal-interval:
            description:
              Pad calibration interval in microseconds.
            $ref: /schemas/types.yaml#/definitions/uint32
            minimum: 0
            maximum: 2097151

          nvidia,emc-mode-1:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              Mode Register 1.

          nvidia,emc-mode-2:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              Mode Register 2.

          nvidia,emc-mode-reset:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              Mode Register 0.

          nvidia,emc-zcal-cnt-long:
            description:
              Number of EMC clocks to wait before issuing any commands after
              sending ZCAL_MRW_CMD.
            $ref: /schemas/types.yaml#/definitions/uint32
            minimum: 0
            maximum: 1023

          nvidia,emc-cfg-dyn-self-ref:
            type: boolean
            description:
              Dynamic self-refresh enabled.

          nvidia,emc-cfg-periodic-qrst:
            type: boolean
            description:
              FBIO "read" FIFO periodic resetting enabled.

          nvidia,emc-configuration:
            description:
              EMC timing characterization data. These are the registers
              (see section "18.13.2 EMC Registers" in the TRM) whose values
              need to be specified, according to the board documentation.
            $ref: /schemas/types.yaml#/definitions/uint32-array
            items:
              - description: EMC_RC
              - description: EMC_RFC
              - description: EMC_RAS
              - description: EMC_RP
              - description: EMC_R2W
              - description: EMC_W2R
              - description: EMC_R2P
              - description: EMC_W2P
              - description: EMC_RD_RCD
              - description: EMC_WR_RCD
              - description: EMC_RRD
              - description: EMC_REXT
              - description: EMC_WEXT
              - description: EMC_WDV
              - description: EMC_QUSE
              - description: EMC_QRST
              - description: EMC_QSAFE
              - description: EMC_RDV
              - description: EMC_REFRESH
              - description: EMC_BURST_REFRESH_NUM
              - description: EMC_PRE_REFRESH_REQ_CNT
              - description: EMC_PDEX2WR
              - description: EMC_PDEX2RD
              - description: EMC_PCHG2PDEN
              - description: EMC_ACT2PDEN
              - description: EMC_AR2PDEN
              - description: EMC_RW2PDEN
              - description: EMC_TXSR
              - description: EMC_TXSRDLL
              - description: EMC_TCKE
              - description: EMC_TFAW
              - description: EMC_TRPAB
              - description: EMC_TCLKSTABLE
              - description: EMC_TCLKSTOP
              - description: EMC_TREFBW
              - description: EMC_QUSE_EXTRA
              - description: EMC_FBIO_CFG6
              - description: EMC_ODT_WRITE
              - description: EMC_ODT_READ
              - description: EMC_FBIO_CFG5
              - description: EMC_CFG_DIG_DLL
              - description: EMC_CFG_DIG_DLL_PERIOD
              - description: EMC_DLL_XFORM_DQS0
              - description: EMC_DLL_XFORM_DQS1
              - description: EMC_DLL_XFORM_DQS2
              - description: EMC_DLL_XFORM_DQS3
              - description: EMC_DLL_XFORM_DQS4
              - description: EMC_DLL_XFORM_DQS5
              - description: EMC_DLL_XFORM_DQS6
              - description: EMC_DLL_XFORM_DQS7
              - description: EMC_DLL_XFORM_QUSE0
              - description: EMC_DLL_XFORM_QUSE1
              - description: EMC_DLL_XFORM_QUSE2
              - description: EMC_DLL_XFORM_QUSE3
              - description: EMC_DLL_XFORM_QUSE4
              - description: EMC_DLL_XFORM_QUSE5
              - description: EMC_DLL_XFORM_QUSE6
              - description: EMC_DLL_XFORM_QUSE7
              - description: EMC_DLI_TRIM_TXDQS0
              - description: EMC_DLI_TRIM_TXDQS1
              - description: EMC_DLI_TRIM_TXDQS2
              - description: EMC_DLI_TRIM_TXDQS3
              - description: EMC_DLI_TRIM_TXDQS4
              - description: EMC_DLI_TRIM_TXDQS5
              - description: EMC_DLI_TRIM_TXDQS6
              - description: EMC_DLI_TRIM_TXDQS7
              - description: EMC_DLL_XFORM_DQ0
              - description: EMC_DLL_XFORM_DQ1
              - description: EMC_DLL_XFORM_DQ2
              - description: EMC_DLL_XFORM_DQ3
              - description: EMC_XM2CMDPADCTRL
              - description: EMC_XM2DQSPADCTRL2
              - description: EMC_XM2DQPADCTRL2
              - description: EMC_XM2CLKPADCTRL
              - description: EMC_XM2COMPPADCTRL
              - description: EMC_XM2VTTGENPADCTRL
              - description: EMC_XM2VTTGENPADCTRL2
              - description: EMC_XM2QUSEPADCTRL
              - description: EMC_XM2DQSPADCTRL3
              - description: EMC_CTT_TERM_CTRL
              - description: EMC_ZCAL_INTERVAL
              - description: EMC_ZCAL_WAIT_CNT
              - description: EMC_MRS_WAIT_CNT
              - description: EMC_AUTO_CAL_CONFIG
              - description: EMC_CTT
              - description: EMC_CTT_DURATION
              - description: EMC_DYN_SELF_REF_CONTROL
              - description: EMC_FBIO_SPARE
              - description: EMC_CFG_RSV

        required:
          - clock-frequency
          - nvidia,emc-auto-cal-interval
          - nvidia,emc-mode-1
          - nvidia,emc-mode-2
          - nvidia,emc-mode-reset
          - nvidia,emc-zcal-cnt-long
          - nvidia,emc-configuration

        additionalProperties: false

    required:
      - nvidia,ram-code

    additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - nvidia,memory-controller
  - "#interconnect-cells"
  - operating-points-v2

additionalProperties: false

examples:
  - |
    external-memory-controller@7000f400 {
        compatible = "nvidia,tegra30-emc";
        reg = <0x7000f400 0x400>;
        interrupts = <0 78 4>;
        clocks = <&tegra_car 57>;

        nvidia,memory-controller = <&mc>;
        operating-points-v2 = <&dvfs_opp_table>;
        power-domains = <&domain>;

        #interconnect-cells = <0>;

        emc-timings-1 {
            nvidia,ram-code = <1>;

            timing-667000000 {
                clock-frequency = <667000000>;

                nvidia,emc-auto-cal-interval = <0x001fffff>;
                nvidia,emc-mode-1 = <0x80100002>;
                nvidia,emc-mode-2 = <0x80200018>;
                nvidia,emc-mode-reset = <0x80000b71>;
                nvidia,emc-zcal-cnt-long = <0x00000040>;
                nvidia,emc-cfg-periodic-qrst;

                nvidia,emc-configuration = <
                    0x00000020 /* EMC_RC */
                    0x0000006a /* EMC_RFC */
                    0x00000017 /* EMC_RAS */
                    0x00000007 /* EMC_RP */
                    0x00000005 /* EMC_R2W */
                    0x0000000c /* EMC_W2R */
                    0x00000003 /* EMC_R2P */
                    0x00000011 /* EMC_W2P */
                    0x00000007 /* EMC_RD_RCD */
                    0x00000007 /* EMC_WR_RCD */
                    0x00000002 /* EMC_RRD */
                    0x00000001 /* EMC_REXT */
                    0x00000000 /* EMC_WEXT */
                    0x00000007 /* EMC_WDV */
                    0x0000000a /* EMC_QUSE */
                    0x00000009 /* EMC_QRST */
                    0x0000000b /* EMC_QSAFE */
                    0x00000011 /* EMC_RDV */
                    0x00001412 /* EMC_REFRESH */
                    0x00000000 /* EMC_BURST_REFRESH_NUM */
                    0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
                    0x00000002 /* EMC_PDEX2WR */
                    0x0000000e /* EMC_PDEX2RD */
                    0x00000001 /* EMC_PCHG2PDEN */
                    0x00000000 /* EMC_ACT2PDEN */
                    0x0000000c /* EMC_AR2PDEN */
                    0x00000016 /* EMC_RW2PDEN */
                    0x00000072 /* EMC_TXSR */
                    0x00000200 /* EMC_TXSRDLL */
                    0x00000005 /* EMC_TCKE */
                    0x00000015 /* EMC_TFAW */
                    0x00000000 /* EMC_TRPAB */
                    0x00000006 /* EMC_TCLKSTABLE */
                    0x00000007 /* EMC_TCLKSTOP */
                    0x00001453 /* EMC_TREFBW */
                    0x0000000b /* EMC_QUSE_EXTRA */
                    0x00000006 /* EMC_FBIO_CFG6 */
                    0x00000000 /* EMC_ODT_WRITE */
                    0x00000000 /* EMC_ODT_READ */
                    0x00005088 /* EMC_FBIO_CFG5 */
                    0xf00b0191 /* EMC_CFG_DIG_DLL */
                    0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
                    0x00000008 /* EMC_DLL_XFORM_DQS0 */
                    0x00000008 /* EMC_DLL_XFORM_DQS1 */
                    0x00000008 /* EMC_DLL_XFORM_DQS2 */
                    0x00000008 /* EMC_DLL_XFORM_DQS3 */
                    0x0000000a /* EMC_DLL_XFORM_DQS4 */
                    0x0000000a /* EMC_DLL_XFORM_DQS5 */
                    0x0000000a /* EMC_DLL_XFORM_DQS6 */
                    0x0000000a /* EMC_DLL_XFORM_DQS7 */
                    0x00018000 /* EMC_DLL_XFORM_QUSE0 */
                    0x00018000 /* EMC_DLL_XFORM_QUSE1 */
                    0x00018000 /* EMC_DLL_XFORM_QUSE2 */
                    0x00018000 /* EMC_DLL_XFORM_QUSE3 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE4 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE5 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE6 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE7 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
                    0x0000000a /* EMC_DLL_XFORM_DQ0 */
                    0x0000000a /* EMC_DLL_XFORM_DQ1 */
                    0x0000000a /* EMC_DLL_XFORM_DQ2 */
                    0x0000000a /* EMC_DLL_XFORM_DQ3 */
                    0x000002a0 /* EMC_XM2CMDPADCTRL */
                    0x0800013d /* EMC_XM2DQSPADCTRL2 */
                    0x22220000 /* EMC_XM2DQPADCTRL2 */
                    0x77fff884 /* EMC_XM2CLKPADCTRL */
                    0x01f1f501 /* EMC_XM2COMPPADCTRL */
                    0x07077404 /* EMC_XM2VTTGENPADCTRL */
                    0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
                    0x080001e8 /* EMC_XM2QUSEPADCTRL */
                    0x0c000021 /* EMC_XM2DQSPADCTRL3 */
                    0x00000802 /* EMC_CTT_TERM_CTRL */
                    0x00020000 /* EMC_ZCAL_INTERVAL */
                    0x00000100 /* EMC_ZCAL_WAIT_CNT */
                    0x0155000c /* EMC_MRS_WAIT_CNT */
                    0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
                    0x00000000 /* EMC_CTT */
                    0x00000000 /* EMC_CTT_DURATION */
                    0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
                    0xe8000000 /* EMC_FBIO_SPARE */
                    0xff00ff49 /* EMC_CFG_RSV */
                >;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra30 SoC Memory Controller

maintainers:
  - Dmitry Osipenko <digetx@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  Tegra30 Memory Controller architecturally consists of the following parts:

    Arbitration Domains, which can handle a single request or response per
    clock from a group of clients. Typically, a system has a single Arbitration
    Domain, but an implementation may divide the client space into multiple
    Arbitration Domains to increase the effective system bandwidth.

    Protocol Arbiter, which manage a related pool of memory devices. A system
    may have a single Protocol Arbiter or multiple Protocol Arbiters.

    Memory Crossbar, which routes request and responses between Arbitration
    Domains and Protocol Arbiters. In the simplest version of the system, the
    Memory Crossbar is just a pass through between a single Arbitration Domain
    and a single Protocol Arbiter.

    Global Resources, which include things like configuration registers which
    are shared across the Memory Subsystem.

  The Tegra30 Memory Controller handles memory requests from internal clients
  and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
  SDRAMs.

properties:
  compatible:
    const: nvidia,tegra30-mc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: mc

  interrupts:
    maxItems: 1

  "#reset-cells":
    const: 1

  "#iommu-cells":
    const: 1

  "#interconnect-cells":
    const: 1

patternProperties:
  "^emc-timings-[0-9]+$":
    type: object
    properties:
      nvidia,ram-code:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Value of RAM_CODE this timing set is used for.

    patternProperties:
      "^timing-[0-9]+$":
        type: object
        properties:
          clock-frequency:
            description:
              Memory clock rate in Hz.
            minimum: 1000000
            maximum: 900000000

          nvidia,emem-configuration:
            $ref: /schemas/types.yaml#/definitions/uint32-array
            description: |
              Values to be written to the EMEM register block. See section
              "18.13.1 MC Registers" in the TRM.
            items:
              - description: MC_EMEM_ARB_CFG
              - description: MC_EMEM_ARB_OUTSTANDING_REQ
              - description: MC_EMEM_ARB_TIMING_RCD
              - description: MC_EMEM_ARB_TIMING_RP
              - description: MC_EMEM_ARB_TIMING_RC
              - description: MC_EMEM_ARB_TIMING_RAS
              - description: MC_EMEM_ARB_TIMING_FAW
              - description: MC_EMEM_ARB_TIMING_RRD
              - description: MC_EMEM_ARB_TIMING_RAP2PRE
              - description: MC_EMEM_ARB_TIMING_WAP2PRE
              - description: MC_EMEM_ARB_TIMING_R2R
              - description: MC_EMEM_ARB_TIMING_W2W
              - description: MC_EMEM_ARB_TIMING_R2W
              - description: MC_EMEM_ARB_TIMING_W2R
              - description: MC_EMEM_ARB_DA_TURNS
              - description: MC_EMEM_ARB_DA_COVERS
              - description: MC_EMEM_ARB_MISC0
              - description: MC_EMEM_ARB_RING1_THROTTLE

        required:
          - clock-frequency
          - nvidia,emem-configuration

        additionalProperties: false

    required:
      - nvidia,ram-code

    additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - "#reset-cells"
  - "#iommu-cells"
  - "#interconnect-cells"

additionalProperties: false

examples:
  - |
    memory-controller@7000f000 {
        compatible = "nvidia,tegra30-mc";
        reg = <0x7000f000 0x400>;
        clocks = <&tegra_car 32>;
        clock-names = "mc";

        interrupts = <0 77 4>;

        #iommu-cells = <1>;
        #reset-cells = <1>;
        #interconnect-cells = <1>;

        emc-timings-1 {
            nvidia,ram-code = <1>;

            timing-667000000 {
                clock-frequency = <667000000>;

                nvidia,emem-configuration = <
                    0x0000000a /* MC_EMEM_ARB_CFG */
                    0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
                    0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
                    0x00000004 /* MC_EMEM_ARB_TIMING_RP */
                    0x00000010 /* MC_EMEM_ARB_TIMING_RC */
                    0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
                    0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
                    0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
                    0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
                    0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
                    0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
                    0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
                    0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
                    0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
                    0x08040202 /* MC_EMEM_ARB_DA_TURNS */
                    0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
                    0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
                    0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
                >;
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  The DDR controller of the AR7xxx and AR9xxx families provides an interface to
  flush the FIFO between various devices and the DDR. This is mainly used by
  the IRQ controller to flush the FIFO before running the interrupt handler of
  such devices.

properties:
  compatible:
    oneOf:
      - items:
          - const: qca,ar9132-ddr-controller
          - const: qca,ar7240-ddr-controller
      - items:
          - enum:
              - qca,ar7100-ddr-controller
              - qca,ar7240-ddr-controller

  "#qca,ddr-wb-channel-cells":
    description: |
      Specifies the number of cells needed to encode the write buffer channel
      index.
    $ref: /schemas/types.yaml#/definitions/uint32
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - "#qca,ddr-wb-channel-cells"
  - reg

additionalProperties: false

examples:
  - |
    ddr_ctrl: memory-controller@18000000 {
        compatible = "qca,ar9132-ddr-controller",
                     "qca,ar7240-ddr-controller";
        reg = <0x18000000 0x100>;

        #qca,ddr-wb-channel-cells = <1>;
    };

    interrupt-controller {
        // ...
        qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
        qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
                              <&ddr_ctrl 0>, <&ddr_ctrl 1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Renesas DDR Bus Controllers

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

description: |
  Renesas SoCs contain one or more memory controllers.  These memory
  controllers differ from one SoC variant to another, and are called by
  different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
  (DBSC3)", or "SDRAM Bus State Controller (SBSC)").

properties:
  compatible:
    enum:
      - renesas,dbsc-r8a73a4  # R-Mobile APE6
      - renesas,dbsc3-r8a7740 # R-Mobile A1
      - renesas,sbsc-sh73a0   # SH-Mobile AG5

  reg:
    maxItems: 1

  interrupts:
    maxItems: 2

  interrupt-names:
    items:
      - const: sec  # secure interrupt
      - const: temp # normal (temperature) interrupt

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    sbsc1: memory-controller@fe400000 {
            compatible = "renesas,sbsc-sh73a0";
            reg = <0xfe400000 0x400>;
            interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "sec", "temp";
            power-domains = <&pd_a4bc0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Reduced Pin Count Interface (RPC-IF)

maintainers:
  - Sergei Shtylyov <sergei.shtylyov@gmail.com>

description: |
  Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
  be accessed via the external address space read mode or the manual mode.

  The flash chip itself should be represented by a subnode of the RPC-IF node.
  The flash interface is selected based on the "compatible" property of this
  subnode:
  - if it contains "jedec,spi-nor", then SPI is used;
  - if it contains "cfi-flash", then HyperFlash is used.

allOf:
  - $ref: "/schemas/spi/spi-controller.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,r8a774a1-rpc-if       # RZ/G2M
              - renesas,r8a774b1-rpc-if       # RZ/G2N
              - renesas,r8a774c0-rpc-if       # RZ/G2E
              - renesas,r8a774e1-rpc-if       # RZ/G2H
              - renesas,r8a7795-rpc-if        # R-Car H3
              - renesas,r8a7796-rpc-if        # R-Car M3-W
              - renesas,r8a77961-rpc-if       # R-Car M3-W+
              - renesas,r8a77965-rpc-if       # R-Car M3-N
              - renesas,r8a77970-rpc-if       # R-Car V3M
              - renesas,r8a77980-rpc-if       # R-Car V3H
              - renesas,r8a77990-rpc-if       # R-Car E3
              - renesas,r8a77995-rpc-if       # R-Car D3
              - renesas,r8a779a0-rpc-if       # R-Car V3U
          - const: renesas,rcar-gen3-rpc-if   # a generic R-Car gen3 or RZ/G2{E,H,M,N} device

      - items:
          - enum:
              - renesas,r8a779g0-rpc-if       # R-Car V4H
          - const: renesas,rcar-gen4-rpc-if   # a generic R-Car gen4 device

      - items:
          - enum:
              - renesas,r9a07g043-rpc-if      # RZ/G2UL
              - renesas,r9a07g044-rpc-if      # RZ/G2{L,LC}
              - renesas,r9a07g054-rpc-if      # RZ/V2L
          - const: renesas,rzg2l-rpc-if

  reg:
    items:
      - description: RPC-IF registers
      - description: direct mapping read mode area
      - description: write buffer area

  reg-names:
    items:
      - const: regs
      - const: dirmap
      - const: wbuf

  clocks: true

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

patternProperties:
  "flash@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        contains:
          enum:
            - cfi-flash
            - jedec,spi-nor

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - power-domains
  - resets
  - '#address-cells'
  - '#size-cells'

if:
  properties:
    compatible:
      contains:
        enum:
          - renesas,rzg2l-rpc-if
then:
  properties:
    clocks:
      items:
        - description: SPI Multi IO Register access clock (SPI_CLK2)
        - description: SPI Multi IO Main clock (SPI_CLK).

else:
  properties:
    clocks:
      maxItems: 1

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/renesas-cpg-mssr.h>
    #include <dt-bindings/power/r8a77995-sysc.h>

    spi@ee200000 {
      compatible = "renesas,r8a77995-rpc-if", "renesas,rcar-gen3-rpc-if";
      reg = <0xee200000 0x200>,
            <0x08000000 0x4000000>,
            <0xee208000 0x100>;
      reg-names = "regs", "dirmap", "wbuf";
      clocks = <&cpg CPG_MOD 917>;
      power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
      resets = <&cpg 917>;
      #address-cells = <1>;
      #size-cells = <0>;

      flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0>;
        spi-max-frequency = <40000000>;
        spi-tx-bus-width = <1>;
        spi-rx-bus-width = <1>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# %YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip rk3399 DMC (Dynamic Memory Controller) device

maintainers:
  - Brian Norris <briannorris@chromium.org>

properties:
  compatible:
    enum:
      - rockchip,rk3399-dmc

  devfreq-events:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Node to get DDR loading. Refer to
      Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: dmc_clk

  operating-points-v2: true

  center-supply:
    description:
      DMC regulator supply.

  rockchip,pmu:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "PMU general register files".

  interrupts:
    maxItems: 1
    description:
      The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
      finishes, a DCF interrupt is triggered.

  rockchip,ddr3_speed_bin:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
      DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
      datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
      being used.

  rockchip,pd_idle:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Configure the PD_IDLE value. Defines the power-down idle period in which
      memories are placed into power-down mode if bus is idle for PD_IDLE DFI
      clock cycles.
      See also rockchip,pd-idle-ns.

  rockchip,sr_idle:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Configure the SR_IDLE value. Defines the self-refresh idle period in
      which memories are placed into self-refresh mode if bus is idle for
      SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
      See also rockchip,sr-idle-ns.
    default: 0

  rockchip,sr_mc_gate_idle:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Defines the memory self-refresh and controller clock gating idle period.
      Memories are placed into self-refresh mode and memory controller clock
      arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
      cycles.
      See also rockchip,sr-mc-gate-idle-ns.

  rockchip,srpd_lite_idle:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Defines the self-refresh power down idle period in which memories are
      placed into self-refresh power down mode if bus is idle for
      srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
      only.
      See also rockchip,srpd-lite-idle-ns.

  rockchip,standby_idle:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Defines the standby idle period in which memories are placed into
      self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
      if bus is idle for standby_idle * DFI clock cycles.
      See also rockchip,standby-idle-ns.

  rockchip,dram_dll_dis_freq:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
      than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
      Note: if DLL was bypassed, the odt will also stop working.

  rockchip,phy_dll_dis_freq:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
      is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
      Note: PHY DLL and PHY ODT are independent.

  rockchip,auto_pd_dis_freq:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Defines the auto PD disable frequency in MHz.

  rockchip,ddr3_odt_dis_freq:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1000000  # In case anyone thought this was MHz.
    description:
      When the DRAM type is DDR3, this parameter defines the ODT disable
      frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
      the ODT on the DRAM side and controller side are both disabled.

  rockchip,ddr3_drv:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is DDR3, this parameter defines the DRAM side drive
      strength in ohms.
    default: 40

  rockchip,ddr3_odt:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is DDR3, this parameter defines the DRAM side ODT
      strength in ohms.
    default: 120

  rockchip,phy_ddr3_ca_drv:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is DDR3, this parameter defines the phy side CA line
      (incluing command line, address line and clock line) drive strength.
    default: 40

  rockchip,phy_ddr3_dq_drv:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is DDR3, this parameter defines the PHY side DQ line
      (including DQS/DQ/DM line) drive strength.
    default: 40

  rockchip,phy_ddr3_odt:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is DDR3, this parameter defines the PHY side ODT
      strength.
    default: 240

  rockchip,lpddr3_odt_dis_freq:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1000000  # In case anyone thought this was MHz.
    description:
      When the DRAM type is LPDDR3, this parameter defines then ODT disable
      frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
      ODT on the DRAM side and controller side are both disabled.

  rockchip,lpddr3_drv:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
      strength in ohms.
    default: 34

  rockchip,lpddr3_odt:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
      strength in ohms.
    default: 240

  rockchip,phy_lpddr3_ca_drv:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
      (including command line, address line and clock line) drive strength.
    default: 40

  rockchip,phy_lpddr3_dq_drv:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
      (including DQS/DQ/DM line) drive strength.
    default: 40

  rockchip,phy_lpddr3_odt:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When dram type is LPDDR3, this parameter define the phy side odt
      strength, default value is 240.

  rockchip,lpddr4_odt_dis_freq:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1000000  # In case anyone thought this was MHz.
    description:
      When the DRAM type is LPDDR4, this parameter defines the ODT disable
      frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
      the ODT on the DRAM side and controller side are both disabled.

  rockchip,lpddr4_drv:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
      strength in ohms.
    default: 60

  rockchip,lpddr4_dq_odt:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
      DQS/DQ line strength in ohms.
    default: 40

  rockchip,lpddr4_ca_odt:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
      CA line strength in ohms.
    default: 40

  rockchip,phy_lpddr4_ca_drv:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
      (including command address line) drive strength.
    default: 40

  rockchip,phy_lpddr4_ck_cs_drv:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is LPDDR4, this parameter defines the PHY side clock
      line and CS line drive strength.
    default: 80

  rockchip,phy_lpddr4_dq_drv:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
      (including DQS/DQ/DM line) drive strength.
    default: 80

  rockchip,phy_lpddr4_odt:
    deprecated: true
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
      strength.
    default: 60

  rockchip,pd-idle-ns:
    description:
      Configure the PD_IDLE value in nanoseconds. Defines the power-down idle
      period in which memories are placed into power-down mode if bus is idle
      for PD_IDLE nanoseconds.

  rockchip,sr-idle-ns:
    description:
      Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
      period in which memories are placed into self-refresh mode if bus is idle
      for SR_IDLE nanoseconds.
    default: 0

  rockchip,sr-mc-gate-idle-ns:
    description:
      Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
      Memories are placed into self-refresh mode and memory controller clock
      arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.

  rockchip,srpd-lite-idle-ns:
    description:
      Defines the self-refresh power down idle period in which memories are
      placed into self-refresh power down mode if bus is idle for
      srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only.

  rockchip,standby-idle-ns:
    description:
      Defines the standby idle period in which memories are placed into
      self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
      if bus is idle for standby_idle nanoseconds.

  rockchip,pd-idle-dis-freq-hz:
    description:
      Defines the power-down idle disable frequency in Hz. When the DDR
      frequency is greater than pd-idle-dis-freq, power-down idle is disabled.
      See also rockchip,pd-idle-ns.

  rockchip,sr-idle-dis-freq-hz:
    description:
      Defines the self-refresh idle disable frequency in Hz. When the DDR
      frequency is greater than sr-idle-dis-freq, self-refresh idle is
      disabled. See also rockchip,sr-idle-ns.

  rockchip,sr-mc-gate-idle-dis-freq-hz:
    description:
      Defines the self-refresh and memory-controller clock gating disable
      frequency in Hz. When the DDR frequency is greater than
      sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also
      rockchip,sr-mc-gate-idle-ns.

  rockchip,srpd-lite-idle-dis-freq-hz:
    description:
      Defines the self-refresh power down idle disable frequency in Hz. When
      the DDR frequency is greater than srpd-lite-idle-dis-freq, memory will
      not be placed into self-refresh power down mode when idle. See also
      rockchip,srpd-lite-idle-ns.

  rockchip,standby-idle-dis-freq-hz:
    description:
      Defines the standby idle disable frequency in Hz. When the DDR frequency
      is greater than standby-idle-dis-freq, standby idle is disabled. See also
      rockchip,standby-idle-ns.

required:
  - compatible
  - devfreq-events
  - clocks
  - clock-names
  - operating-points-v2
  - center-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3399-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    memory-controller {
      compatible = "rockchip,rk3399-dmc";
      devfreq-events = <&dfi>;
      rockchip,pmu = <&pmu>;
      interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&cru SCLK_DDRC>;
      clock-names = "dmc_clk";
      operating-points-v2 = <&dmc_opp_table>;
      center-supply = <&ppvar_centerlogic>;
      rockchip,pd-idle-ns = <160>;
      rockchip,sr-idle-ns = <10240>;
      rockchip,sr-mc-gate-idle-ns = <40960>;
      rockchip,srpd-lite-idle-ns = <61440>;
      rockchip,standby-idle-ns = <81920>;
      rockchip,ddr3_odt_dis_freq = <333000000>;
      rockchip,lpddr3_odt_dis_freq = <333000000>;
      rockchip,lpddr4_odt_dis_freq = <333000000>;
      rockchip,pd-idle-dis-freq-hz = <1000000000>;
      rockchip,sr-idle-dis-freq-hz = <1000000000>;
      rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
      rockchip,srpd-lite-idle-dis-freq-hz = <0>;
      rockchip,standby-idle-dis-freq-hz = <928000000>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: |
  Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
  Controller device

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Lukasz Luba <lukasz.luba@arm.com>

description: |
  The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
  DRAM memory chips are connected. The driver is to monitor the controller in
  runtime and switch frequency and voltage. To monitor the usage of the
  controller in runtime, the driver uses the PPMU (Platform Performance
  Monitoring Unit), which is able to measure the current load of the memory.
  When 'userspace' governor is used for the driver, an application is able to
  switch the DMC and memory frequency.

properties:
  compatible:
    items:
      - const: samsung,exynos5422-dmc

  clock-names:
    items:
      - const: fout_spll
      - const: mout_sclk_spll
      - const: ff_dout_spll2
      - const: fout_bpll
      - const: mout_bpll
      - const: sclk_bpll
      - const: mout_mx_mspll_ccore
      - const: mout_mclk_cdrex

  clocks:
    minItems: 8
    maxItems: 8

  devfreq-events:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    minItems: 1
    maxItems: 16
    items:
      maxItems: 1
    description: phandles of the PPMU events used by the controller.

  device-handle:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: |
      phandle of the connected DRAM memory device. For more information please
      refer to jedec,lpddr3.yaml.

  operating-points-v2: true

  interrupts:
    items:
      - description: DMC internal performance event counters in DREX0
      - description: DMC internal performance event counters in DREX1

  interrupt-names:
    items:
      - const: drex_0
      - const: drex_1

  reg:
    items:
      - description: registers of DREX0
      - description: registers of DREX1

  samsung,syscon-clk:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: |
      Phandle of the clock register set used by the controller, these registers
      are used for enabling a 'pause' feature and are not exposed by clock
      framework but they must be used in a safe way.  The register offsets are
      in the driver code and specyfic for this SoC type.

  vdd-supply: true

required:
  - compatible
  - clock-names
  - clocks
  - devfreq-events
  - device-handle
  - reg
  - samsung,syscon-clk

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5420.h>
    ppmu_dmc0_0: ppmu@10d00000 {
        compatible = "samsung,exynos-ppmu";
        reg = <0x10d00000 0x2000>;
        clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
        clock-names = "ppmu";
        events {
            ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
                event-name = "ppmu-event3-dmc0_0";
            };
        };
    };

    memory-controller@10c20000 {
        compatible = "samsung,exynos5422-dmc";
        reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
        clocks = <&clock CLK_FOUT_SPLL>,
                 <&clock CLK_MOUT_SCLK_SPLL>,
                 <&clock CLK_FF_DOUT_SPLL2>,
                 <&clock CLK_FOUT_BPLL>,
                 <&clock CLK_MOUT_BPLL>,
                 <&clock CLK_SCLK_BPLL>,
                 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
                 <&clock CLK_MOUT_MCLK_CDREX>;
        clock-names = "fout_spll",
                      "mout_sclk_spll",
                      "ff_dout_spll2",
                      "fout_bpll",
                      "mout_bpll",
                      "sclk_bpll",
                      "mout_mx_mspll_ccore",
                      "mout_mclk_cdrex";
        operating-points-v2 = <&dmc_opp_table>;
        devfreq-events = <&ppmu_event3_dmc0_0>,	<&ppmu_event3_dmc0_1>,
                         <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
        device-handle = <&samsung_K3QF2F20DB>;
        vdd-supply = <&buck1_reg>;
        samsung,syscon-clk = <&clock>;
        interrupt-parent = <&combiner>;
        interrupts = <16 0>, <16 1>;
        interrupt-names = "drex_0", "drex_1";
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare Universal Multi-Protocol Memory Controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Manish Narani <manish.narani@xilinx.com>
  - Michal Simek <michal.simek@xilinx.com>

description: |
  Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
  working with the memory devices supporting up to (LP)DDR4 protocol. It can
  be equipped with SEC/DEC ECC feature if DRAM data bus width is either
  16-bits or 32-bits or 64-bits wide.

  For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
  controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
  bus width configurations.

properties:
  compatible:
    oneOf:
      - deprecated: true
        description: Synopsys DW uMCTL2 DDR controller v3.80a
        const: snps,ddrc-3.80a
      - description: Synopsys DW uMCTL2 DDR controller
        const: snps,dw-umctl2-ddrc
      - description: Xilinx ZynqMP DDR controller v2.40a
        const: xlnx,zynqmp-ddrc-2.40a

  interrupts:
    description:
      DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
      ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,
      Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the
      signals merged before they reach the IRQ controller or have some of them
      absent in case if the corresponding feature is unavailable/disabled.
    minItems: 1
    maxItems: 5

  interrupt-names:
    minItems: 1
    maxItems: 5
    oneOf:
      - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ
        items:
          - const: ecc
      - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs
        items:
          enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ]

  reg:
    maxItems: 1

  clocks:
    description:
      A standard set of the clock sources contains CSRs bus clock, AXI-ports
      reference clock, DDRC core clock, Scrubber standalone clock
      (synchronous to the DDRC clock).
    minItems: 1
    maxItems: 4

  clock-names:
    minItems: 1
    maxItems: 4
    items:
      enum: [ pclk, aclk, core, sbr ]

  resets:
    description:
      Each clock domain can have separate reset signal.
    minItems: 1
    maxItems: 4

  reset-names:
    minItems: 1
    maxItems: 4
    items:
      enum: [ prst, arst, core, sbr ]

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    memory-controller@fd070000 {
      compatible = "xlnx,zynqmp-ddrc-2.40a";
      reg = <0xfd070000 0x30000>;

      interrupt-parent = <&gic>;
      interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "ecc";
    };
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    memory-controller@3d400000 {
      compatible = "snps,dw-umctl2-ddrc";
      reg = <0x3d400000 0x400000>;

      interrupts = <147 IRQ_TYPE_LEVEL_HIGH>, <148 IRQ_TYPE_LEVEL_HIGH>,
                   <149 IRQ_TYPE_LEVEL_HIGH>, <150 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e";

      clocks = <&pclk>, <&aclk>, <&core_clk>, <&sbr_clk>;
      clock-names = "pclk", "aclk", "core", "sbr";
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Peripheral properties for ST FMC2 Controller

maintainers:
  - Christophe Kerello <christophe.kerello@foss.st.com>
  - Marek Vasut <marex@denx.de>

properties:
  st,fmc2-ebi-cs-transaction-type:
    description: |
      Select one of the transactions type supported
      0: Asynchronous mode 1 SRAM/FRAM.
      1: Asynchronous mode 1 PSRAM.
      2: Asynchronous mode A SRAM/FRAM.
      3: Asynchronous mode A PSRAM.
      4: Asynchronous mode 2 NOR.
      5: Asynchronous mode B NOR.
      6: Asynchronous mode C NOR.
      7: Asynchronous mode D NOR.
      8: Synchronous read synchronous write PSRAM.
      9: Synchronous read asynchronous write PSRAM.
      10: Synchronous read synchronous write NOR.
      11: Synchronous read asynchronous write NOR.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 11

  st,fmc2-ebi-cs-cclk-enable:
    description: Continuous clock enable (first bank must be configured
      in synchronous mode). The FMC_CLK is generated continuously
      during asynchronous and synchronous access. By default, the
      FMC_CLK is only generated during synchronous access.
    $ref: /schemas/types.yaml#/definitions/flag

  st,fmc2-ebi-cs-mux-enable:
    description: Address/Data multiplexed on databus (valid only with
      NOR and PSRAM transactions type). By default, Address/Data
      are not multiplexed.
    $ref: /schemas/types.yaml#/definitions/flag

  st,fmc2-ebi-cs-buswidth:
    description: Data bus width
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 8, 16 ]
    default: 16

  st,fmc2-ebi-cs-waitpol-high:
    description: Wait signal polarity (NWAIT signal active high).
      By default, NWAIT is active low.
    $ref: /schemas/types.yaml#/definitions/flag

  st,fmc2-ebi-cs-waitcfg-enable:
    description: The NWAIT signal indicates wheither the data from the
      device are valid or if a wait state must be inserted when accessing
      the device in synchronous mode. By default, the NWAIT signal is
      active one data cycle before wait state.
    $ref: /schemas/types.yaml#/definitions/flag

  st,fmc2-ebi-cs-wait-enable:
    description: The NWAIT signal is enabled (its level is taken into
      account after the programmed latency period to insert wait states
      if asserted). By default, the NWAIT signal is disabled.
    $ref: /schemas/types.yaml#/definitions/flag

  st,fmc2-ebi-cs-asyncwait-enable:
    description: The NWAIT signal is taken into account during asynchronous
      transactions. By default, the NWAIT signal is not taken into account
      during asynchronous transactions.
    $ref: /schemas/types.yaml#/definitions/flag

  st,fmc2-ebi-cs-cpsize:
    description: CRAM page size. The controller splits the burst access
      when the memory page is reached. By default, no burst split when
      crossing page boundary.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 0, 128, 256, 512, 1024 ]
    default: 0

  st,fmc2-ebi-cs-byte-lane-setup-ns:
    description: This property configures the byte lane setup timing
      defined in nanoseconds from NBLx low to Chip Select NEx low.

  st,fmc2-ebi-cs-address-setup-ns:
    description: This property defines the duration of the address setup
      phase in nanoseconds used for asynchronous read/write transactions.

  st,fmc2-ebi-cs-address-hold-ns:
    description: This property defines the duration of the address hold
      phase in nanoseconds used for asynchronous multiplexed read/write
      transactions.

  st,fmc2-ebi-cs-data-setup-ns:
    description: This property defines the duration of the data setup phase
      in nanoseconds used for asynchronous read/write transactions.

  st,fmc2-ebi-cs-bus-turnaround-ns:
    description: This property defines the delay in nanoseconds between the
      end of current read/write transaction and the next transaction.

  st,fmc2-ebi-cs-data-hold-ns:
    description: This property defines the duration of the data hold phase
      in nanoseconds used for asynchronous read/write transactions.

  st,fmc2-ebi-cs-clk-period-ns:
    description: This property defines the FMC_CLK output signal period in
      nanoseconds.

  st,fmc2-ebi-cs-data-latency-ns:
    description: This property defines the data latency before reading or
      writing the first data in nanoseconds.

  st,fmc2-ebi-cs-write-address-setup-ns:
    description: This property defines the duration of the address setup
      phase in nanoseconds used for asynchronous write transactions.

  st,fmc2-ebi-cs-write-address-hold-ns:
    description: This property defines the duration of the address hold
      phase in nanoseconds used for asynchronous multiplexed write
      transactions.

  st,fmc2-ebi-cs-write-data-setup-ns:
    description: This property defines the duration of the data setup
      phase in nanoseconds used for asynchronous write transactions.

  st,fmc2-ebi-cs-write-bus-turnaround-ns:
    description: This property defines the delay between the end of current
      write transaction and the next transaction in nanoseconds.

  st,fmc2-ebi-cs-write-data-hold-ns:
    description: This property defines the duration of the data hold phase
      in nanoseconds used for asynchronous write transactions.

  st,fmc2-ebi-cs-max-low-pulse-ns:
    description: This property defines the maximum chip select low pulse
      duration in nanoseconds for synchronous transactions. When this timing
      reaches 0, the controller splits the current access, toggles NE to
      allow device refresh and restarts a new access.

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings

description: |
  The FMC2 functional block makes the interface with: synchronous and
  asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
  peripherals) and NAND flash memories.
  Its main purposes are:
    - to translate AXI transactions into the appropriate external device
      protocol
    - to meet the access time requirements of the external devices
  All external devices share the addresses, data and control signals with the
  controller. Each external device is accessed by means of a unique Chip
  Select. The FMC2 performs only one access at a time to an external device.

maintainers:
  - Christophe Kerello <christophe.kerello@foss.st.com>

properties:
  compatible:
    const: st,stm32mp1-fmc2-ebi

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  "#address-cells":
    const: 2

  "#size-cells":
    const: 1

  ranges:
    description: |
      Reflects the memory layout with four integer values per bank. Format:
      <bank-number> 0 <address of the bank> <size>

patternProperties:
  "^.*@[0-4],[a-f0-9]+$":
    type: object
    $ref: mc-peripheral-props.yaml#

required:
  - "#address-cells"
  - "#size-cells"
  - compatible
  - reg
  - clocks
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    memory-controller@58002000 {
      #address-cells = <2>;
      #size-cells = <1>;
      compatible = "st,stm32mp1-fmc2-ebi";
      reg = <0x58002000 0x1000>;
      clocks = <&rcc FMC_K>;
      resets = <&rcc FMC_R>;

      ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
               <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
               <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
               <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
               <4 0 0x80000000 0x10000000>; /* NAND */

      psram@0,0 {
        compatible = "mtd-ram";
        reg = <0 0x00000000 0x100000>;
        bank-width = <2>;

        st,fmc2-ebi-cs-transaction-type = <1>;
        st,fmc2-ebi-cs-address-setup-ns = <60>;
        st,fmc2-ebi-cs-data-setup-ns = <30>;
        st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
      };

      nand-controller@4,0 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "st,stm32mp1-fmc2-nfc";
        reg = <4 0x00000000 0x1000>,
              <4 0x08010000 0x1000>,
              <4 0x08020000 0x1000>,
              <4 0x01000000 0x1000>,
              <4 0x09010000 0x1000>,
              <4 0x09020000 0x1000>;
        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
        dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
               <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
               <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
        dma-names = "tx", "rx", "ecc";

        nand@0 {
          reg = <0>;
          nand-on-flash-bbt;
          #address-cells = <1>;
          #size-cells = <1>;
        };
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ti,da8xx-ddrctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments da8xx DDR2/mDDR memory controller

maintainers:
  - Bartosz Golaszewski <bgolaszewski@baylibre.com>
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  Documentation:
    OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf

properties:
  compatible:
    const: ti,da850-ddr-controller

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    memory-controller@b0000000 {
        compatible = "ti,da850-ddr-controller";
        reg = <0xb0000000 0xe8>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: device tree bindings for children of the Texas Instruments GPMC

maintainers:
  - Tony Lindgren <tony@atomide.com>
  - Roger Quadros <rogerq@kernel.org>

description:
  This binding is meant for the child nodes of the GPMC node. The node
  represents any device connected to the GPMC bus. It may be a Flash chip,
  RAM chip or Ethernet controller, etc. These properties are meant for
  configuring the GPMC settings/timings and will accompany the bindings
  supported by the respective device.

properties:
  reg: true

# GPMC Timing properties for child nodes. All are optional and default to 0.
  gpmc,sync-clk-ps:
    description: Minimum clock period for synchronous mode
    default: 0

# Chip-select signal timings corresponding to GPMC_CONFIG2:
  gpmc,cs-on-ns:
    description: Assertion time
    default: 0

  gpmc,cs-rd-off-ns:
    description: Read deassertion time
    default: 0

  gpmc,cs-wr-off-ns:
    description: Write deassertion time
    default: 0

# ADV signal timings corresponding to GPMC_CONFIG3:
  gpmc,adv-on-ns:
    description: Assertion time
    default: 0

  gpmc,adv-rd-off-ns:
    description: Read deassertion time
    default: 0

  gpmc,adv-wr-off-ns:
    description: Write deassertion time
    default: 0

  gpmc,adv-aad-mux-on-ns:
    description: Assertion time for AAD
    default: 0

  gpmc,adv-aad-mux-rd-off-ns:
    description: Read deassertion time for AAD
    default: 0

  gpmc,adv-aad-mux-wr-off-ns:
    description: Write deassertion time for AAD
    default: 0

# WE signals timings corresponding to GPMC_CONFIG4:
  gpmc,we-on-ns:
    description: Assertion time
    default: 0

  gpmc,we-off-ns:
    description: Deassertion time
    default: 0

# OE signals timings corresponding to GPMC_CONFIG4:
  gpmc,oe-on-ns:
    description: Assertion time
    default: 0

  gpmc,oe-off-ns:
    description: Deassertion time
    default: 0

  gpmc,oe-aad-mux-on-ns:
    description: Assertion time for AAD
    default: 0

  gpmc,oe-aad-mux-off-ns:
    description: Deassertion time for AAD
    default: 0

# Access time and cycle time timings (in nanoseconds) corresponding to
# GPMC_CONFIG5:
  gpmc,page-burst-access-ns:
    description: Multiple access word delay
    default: 0

  gpmc,access-ns:
    description: Start-cycle to first data valid delay
    default: 0

  gpmc,rd-cycle-ns:
    description: Total read cycle time
    default: 0

  gpmc,wr-cycle-ns:
    description: Total write cycle time
    default: 0

  gpmc,bus-turnaround-ns:
    description: Turn-around time between successive accesses
    default: 0

  gpmc,cycle2cycle-delay-ns:
    description: Delay between chip-select pulses
    default: 0

  gpmc,clk-activation-ns:
    description: GPMC clock activation time
    default: 0

  gpmc,wait-monitoring-ns:
    description: Start of wait monitoring with regard to valid data
    default: 0

# Boolean timing parameters. If property is present, parameter is enabled
# otherwise disabled.
  gpmc,adv-extra-delay:
    description: ADV signal is delayed by half GPMC clock
    type: boolean

  gpmc,cs-extra-delay:
    description: CS signal is delayed by half GPMC clock
    type: boolean

  gpmc,cycle2cycle-diffcsen:
    description: |
      Add "cycle2cycle-delay" between successive accesses
      to a different CS
    type: boolean

  gpmc,cycle2cycle-samecsen:
    description: |
      Add "cycle2cycle-delay" between successive accesses
      to the same CS
    type: boolean

  gpmc,oe-extra-delay:
    description: OE signal is delayed by half GPMC clock
    type: boolean

  gpmc,we-extra-delay:
    description: WE signal is delayed by half GPMC clock
    type: boolean

  gpmc,time-para-granularity:
    description: Multiply all access times by 2
    type: boolean

# The following two properties are applicable only to OMAP3+ and AM335x:
  gpmc,wr-access-ns:
    description: |
      In synchronous write mode, for single or
      burst accesses, defines the number of
      GPMC_FCLK cycles from start access time
      to the GPMC_CLK rising edge used by the
      memory device for the first data capture.
    default: 0

  gpmc,wr-data-mux-bus-ns:
    description: |
      In address-data multiplex mode, specifies
      the time when the first data is driven on
      the address-data bus.
    default: 0

# GPMC chip-select settings properties for child nodes. All are optional.
  gpmc,burst-length:
    description: Page/burst length.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 4, 8, 16]
    default: 0

  gpmc,burst-wrap:
    description: Enables wrap bursting
    type: boolean

  gpmc,burst-read:
    description: Enables read page/burst mode
    type: boolean

  gpmc,burst-write:
    description: Enables write page/burst mode
    type: boolean

  gpmc,device-width:
    description: |
      Total width of device(s) connected to a GPMC
      chip-select in bytes. The GPMC supports 8-bit
      and 16-bit devices and so this property must be
      1 or 2.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2]
    default: 1

  gpmc,mux-add-data:
    description: |
      Address and data multiplexing configuration.
      Valid values are
      0 for Non multiplexed mode
      1 for address-address-data multiplexing mode and
      2 for address-data multiplexing mode.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2]

  gpmc,sync-read:
    description: |
      Enables synchronous read. Defaults to asynchronous
      is this is not set.
    type: boolean

  gpmc,sync-write:
    description: |
      Enables synchronous writes. Defaults to asynchronous
      is this is not set.
    type: boolean

  gpmc,wait-pin:
    description: |
      Wait-pin used by client. Must be less than "gpmc,num-waitpins".
    $ref: /schemas/types.yaml#/definitions/uint32

  ti,wait-pin-polarity:
    description: |
      Set the desired polarity for the selected wait pin.
      0 for active low, 1 for active high.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]

  gpmc,wait-on-read:
    description: Enables wait monitoring on reads.
    type: boolean

  gpmc,wait-on-write:
    description: Enables wait monitoring on writes.
    type: boolean

required:
  - reg

# the GPMC child will have its own native properties
additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments GPMC Memory Controller device-tree bindings

maintainers:
  - Tony Lindgren <tony@atomide.com>
  - Roger Quadros <rogerq@kernel.org>

description:
  The GPMC is a unified memory controller dedicated for interfacing
  with external memory devices like
  - Asynchronous SRAM-like memories and ASICs
  - Asynchronous, synchronous, and page mode burst NOR flash
  - NAND flash
  - Pseudo-SRAM devices

properties:
  compatible:
    items:
      - enum:
          - ti,am3352-gpmc
          - ti,am64-gpmc
          - ti,omap2420-gpmc
          - ti,omap2430-gpmc
          - ti,omap3430-gpmc
          - ti,omap4430-gpmc

  reg:
    minItems: 1
    maxItems: 2

  reg-names:
    items:
      - const: cfg
      - const: data

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1
    description: |
      Functional clock. Used for bus timing calculations and
      GPMC configuration.

  clock-names:
    items:
      - const: fck

  power-domains:
    maxItems: 1

  dmas:
    items:
      - description: DMA channel for GPMC NAND prefetch

  dma-names:
    items:
      - const: rxtx

  "#address-cells": true

  "#size-cells": true

  gpmc,num-cs:
    description: maximum number of supported chip-select lines.
    $ref: /schemas/types.yaml#/definitions/uint32

  gpmc,num-waitpins:
    description: maximum number of supported wait pins.
    $ref: /schemas/types.yaml#/definitions/uint32

  ranges:
    minItems: 1
    description: |
      Must be set up to reflect the memory layout with four
      integer values for each chip-select line in use,
      <cs-number> 0 <physical address of mapping> <size>
    items:
      - description: NAND bank 0
      - description: NOR/SRAM bank 0
      - description: NOR/SRAM bank 1

  '#interrupt-cells':
    const: 2

  interrupt-controller:
    description: |
      The GPMC driver implements and interrupt controller for
      the NAND events "fifoevent" and "termcount" plus the
      rising/falling edges on the GPMC_WAIT pins.
      The interrupt number mapping is as follows
      0 - NAND_fifoevent
      1 - NAND_termcount
      2 - GPMC_WAIT0 pin edge
      3 - GPMC_WAIT1 pin edge, and so on.

  '#gpio-cells':
    const: 2

  gpio-controller:
    description: |
      The GPMC driver implements a GPIO controller for the
      GPMC WAIT pins that can be used as general purpose inputs.
      0 maps to GPMC_WAIT0 pin.

  ti,hwmods:
    description:
      Name of the HWMOD associated with GPMC. This is for legacy
      omap2/3 platforms only.
    $ref: /schemas/types.yaml#/definitions/string
    deprecated: true

  ti,no-idle-on-init:
    description:
      Prevent idling the module at init. This is for legacy omap2/3
      platforms only.
    type: boolean
    deprecated: true

patternProperties:
  "@[0-7],[a-f0-9]+$":
    type: object
    description: |
      The child device node represents the device connected to the GPMC
      bus. The device can be a NAND chip, SRAM device, NOR device
      or an ASIC.
    $ref: "ti,gpmc-child.yaml"

required:
  - compatible
  - reg
  - gpmc,num-cs
  - gpmc,num-waitpins
  - "#address-cells"
  - "#size-cells"

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: ti,am64-gpmc
    then:
      required:
        - reg-names
        - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/gpio/gpio.h>

    gpmc: memory-controller@50000000 {
      compatible = "ti,am3352-gpmc";
      reg = <0x50000000 0x2000>;
      interrupts = <100>;
      clocks = <&l3s_clkctrl>;
      clock-names = "fck";
      dmas = <&edma 52 0>;
      dma-names = "rxtx";
      gpmc,num-cs = <8>;
      gpmc,num-waitpins = <2>;
      #address-cells = <2>;
      #size-cells = <1>;
      ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
      interrupt-controller;
      #interrupt-cells = <2>;
      gpio-controller;
      #gpio-cells = <2>;

      nand@0,0 {
        compatible = "ti,omap2-nand";
        reg = <0 0 4>;
        interrupt-parent = <&gpmc>;
        interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                     <1 IRQ_TYPE_NONE>; /* termcount */
        ti,nand-xfer-type = "prefetch-dma";
        ti,nand-ecc-opt = "bch16";
        ti,elm-id = <&elm>;
        rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
      };
    };


code:
* Device tree bindings for Texas instruments AEMIF controller

The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
provide a glue-less interface to a variety of asynchronous memory devices like
ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
can be accessed at any given time via four chip selects with 64M byte access
per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
and Mobile SDR are not supported.

Documentation:
Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf

Required properties:

- compatible:		"ti,davinci-aemif"
			"ti,keystone-aemif"
			"ti,da850-aemif"

- reg:			contains offset/length value for AEMIF control registers
			space.

- #address-cells:	Must be 2. The partition number has to be encoded in the
			first address cell and it may accept values 0..N-1
			(N - total number of partitions). It's recommended to
			assign N-1 number for the control partition. The second
			cell is the offset into the partition.

- #size-cells:		Must be set to 1.

- ranges:		Contains memory regions. There are two types of
			ranges/partitions:
			- CS-specific partition/range. If continuous, must be
			set up to reflect the memory layout for 4 chipselects,
			if not then additional range/partition can be added and
			child device can select the proper one.
			- control partition which is common for all CS
			interfaces.

- clocks:		the clock feeding the controller clock. Required only
			if clock tree data present in device tree.
			See clock-bindings.txt

- clock-names:		clock name. It has to be "aemif". Required only if clock
			tree data present in device tree, in another case don't
			use it.
			See clock-bindings.txt

- clock-ranges:		Empty property indicating that child nodes can inherit
			named clocks. Required only if clock tree data present
			in device tree.
			See clock-bindings.txt

Child chip-select (cs) nodes contain the memory devices nodes connected to
such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt).
There might be board specific devices like FPGAs.

Required child cs node properties:

- #address-cells:	Must be 2.

- #size-cells:		Must be 1.

- ranges:		Empty property indicating that child nodes can inherit
			memory layout.

- clock-ranges:		Empty property indicating that child nodes can inherit
			named clocks. Required only if clock tree data present
			in device tree.

- ti,cs-chipselect:	number of chipselect. Indicates on the aemif driver
			which chipselect is used for accessing the memory. For
			compatibles "ti,davinci-aemif" and "ti,keystone-aemif"
			it can be in range [0-3]. For compatible
			"ti,da850-aemif" range is [2-5].

Optional child cs node properties:

- ti,cs-bus-width:		width of the asynchronous device's data bus
				8 or 16 if not preset 8

- ti,cs-select-strobe-mode:	enable/disable select strobe mode
				In select strobe mode chip select behaves as
				the strobe and is active only during the strobe
				period. If present then enable.

- ti,cs-extended-wait-mode:	enable/disable extended wait mode
				if set, the controller monitors the EMIFWAIT pin
				mapped to that chip select to determine if the
				device wants to extend the strobe period. If
				present then enable.

- ti,cs-min-turnaround-ns:	minimum turn around time, ns
				Time between the end of one asynchronous memory
				access and the start of another asynchronous
				memory access. This delay is not incurred
				between a read followed by read or a write
				followed by a write to same chip select.

- ti,cs-read-setup-ns:		read setup width, ns
				Time between the beginning of a memory cycle
				and the activation of read strobe.
				Minimum value is 1 (0 treated as 1).

- ti,cs-read-strobe-ns:		read strobe width, ns
				Time between the activation and deactivation of
				the read strobe.
				Minimum value is 1 (0 treated as 1).

- ti,cs-read-hold-ns:		read hold width, ns
				Time between the deactivation of the read
				strobe and the end of the cycle (which may be
				either an address change or the deactivation of
				the chip select signal.
				Minimum value is 1 (0 treated as 1).

- ti,cs-write-setup-ns:		write setup width, ns
				Time between the beginning of a memory cycle
				and the activation of write strobe.
				Minimum value is 1 (0 treated as 1).

- ti,cs-write-strobe-ns:	write strobe width, ns
				Time between the activation and deactivation of
				the write strobe.
				Minimum value is 1 (0 treated as 1).

- ti,cs-write-hold-ns:		write hold width, ns
				Time between the deactivation of the write
				strobe and the end of the cycle (which may be
				either an address change or the deactivation of
				the chip select signal.
				Minimum value is 1 (0 treated as 1).

If any of the above parameters are absent, current parameter value will be taken
from the corresponding HW reg.

Example for aemif, davinci nand and nor flash chip select shown below.

memory-controller@21000a00 {
	compatible = "ti,davinci-aemif";
	#address-cells = <2>;
	#size-cells = <1>;
	clocks = <&clkaemif 0>;
	clock-names = "aemif";
	clock-ranges;
	reg = <0x21000A00 0x00000100>;
	ranges = <0 0 0x70000000 0x10000000
		  1 0 0x21000A00 0x00000100>;
		  /*
		   * Partition0: CS-specific memory range which is
		   * implemented as continuous physical memory region
		   * Partition1: control memory range
		   */

	nand:cs2 {
		#address-cells = <2>;
		#size-cells = <1>;
		clock-ranges;
		ranges;

		ti,cs-chipselect = <2>;
		/* all timings in nanoseconds */
		ti,cs-min-turnaround-ns = <0>;
		ti,cs-read-hold-ns = <7>;
		ti,cs-read-strobe-ns = <42>;
		ti,cs-read-setup-ns = <14>;
		ti,cs-write-hold-ns = <7>;
		ti,cs-write-strobe-ns = <42>;
		ti,cs-write-setup-ns = <14>;

		nand@0,0x8000000 {
			compatible = "ti,davinci-nand";
			reg = <0 0x8000000 0x4000000
			       1 0x0000000 0x0000100>;
			/*
			 * Partition0, offset 0x8000000, size 0x4000000
			 * Partition1, offset 0x0000000, size 0x0000100
			 */

			.. see davinci-nand.txt
		};
	};

	nor:cs0 {
		#address-cells = <2>;
		#size-cells = <1>;
		clock-ranges;
		ranges;

		ti,cs-chipselect = <0>;
		/* all timings in nanoseconds */
		ti,cs-min-turnaround-ns = <0>;
		ti,cs-read-hold-ns = <8>;
		ti,cs-read-strobe-ns = <40>;
		ti,cs-read-setup-ns = <14>;
		ti,cs-write-hold-ns = <7>;
		ti,cs-write-strobe-ns = <40>;
		ti,cs-write-setup-ns = <14>;
		ti,cs-bus-width = <16>;

		flash@0,0x0000000 {
			compatible = "cfi-flash";
			reg = <0 0x0000000 0x4000000>;

			...
		};
	};
};


code:
* EMIF family of TI SDRAM controllers

EMIF - External Memory Interface - is an SDRAM controller used in
TI SoCs. EMIF supports, based on the IP revision, one or more of
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
of the EMIF IP and memory parts attached to it. Certain revisions
of the EMIF controller also contain optional ECC support, which
corrects one bit errors and detects two bit errors.

Required properties:
- compatible	: Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
  is the IP revision of the specific EMIF instance. For newer controllers,
  compatible should be one of the following:
  	     "ti,emif-am3352"
	     "ti,emif-am4372"
	     "ti,emif-dra7xx"
	     "ti,emif-keystone"

- phy-type	: <u32> indicating the DDR phy type. Following are the
  allowed values
  <1>	: Attila PHY
  <2>	: Intelli PHY

- device-handle	: phandle to a "lpddr2" node representing the memory part

- ti,hwmods	: For TI hwmods processing and omap device creation
  the value shall be "emif<n>" where <n> is the number of the EMIF
  instance with base 1.
- interrupts	: interrupt used by the controller

Required only for "ti,emif-am3352" and "ti,emif-am4372":
- sram			: Phandles for generic sram driver nodes,
  first should be type 'protect-exec' for the driver to use to copy
  and run PM functions, second should be regular pool to be used for
  data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
  for more details.

Optional properties:
- cs1-used		: Have this property if CS1 of this EMIF
  instance has a memory part attached to it. If there is a memory
  part attached to CS1, it should be the same type as the one on CS0,
  so there is no need to give the details of this memory part.

- cal-resistor-per-cs	: Have this property if the board has one
  calibration resistor per chip-select.

- hw-caps-read-idle-ctrl: Have this property if the controller
  supports read idle window programming

- hw-caps-dll-calib-ctrl: Have this property if the controller
  supports dll calibration control

- hw-caps-ll-interface	: Have this property if the controller
  has a low latency interface and corresponding interrupt events

- hw-caps-temp-alert	: Have this property if the controller
  has capability for generating SDRAM temperature alerts

-Examples:

emif1: emif@4c000000 {
	compatible	= "ti,emif-4d";
	ti,hwmods	= "emif2";
	phy-type	= <1>;
	device-handle	= <&elpida_ECB240ABACN>;
	cs1-used;
	hw-caps-read-idle-ctrl;
	hw-caps-ll-interface;
	hw-caps-temp-alert;
};

/* From am33xx.dtsi */
emif: emif@4c000000 {
        compatible = "ti,emif-am3352";
        reg =   <0x4C000000 0x1000>;
        sram = <&pm_sram_code
                &pm_sram_data>;
};

emif1: emif@4c000000 {
	compatible = "ti,emif-dra7xx";
	reg = <0x4c000000 0x200>;
	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Zynq A05 DDR Memory Controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Manish Narani <manish.narani@xilinx.com>
  - Michal Simek <michal.simek@xilinx.com>

description:
  The Zynq DDR ECC controller has an optional ECC support in half-bus width
  (16-bit) configuration. It is cappable of correcting single bit ECC errors
  and detecting double bit ECC errors.

properties:
  compatible:
    const: xlnx,zynq-ddrc-a05

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    memory-controller@f8006000 {
      compatible = "xlnx,zynq-ddrc-a05";
      reg = <0xf8006000 0x1000>;
    };
...


code:
* Marvell 88PM860x Power Management IC

Required parent device properties:
- compatible : "marvell,88pm860x"
- reg : the I2C slave address for the 88pm860x chip
- interrupts : IRQ line for the 88pm860x chip
- interrupt-controller: describes the 88pm860x as an interrupt controller (has its own domain)
- #interrupt-cells : should be 1.
		- The cell is the 88pm860x local IRQ number

Optional parent device properties:
- marvell,88pm860x-irq-read-clr: inicates whether interrupt status is cleared by read
- marvell,88pm860x-slave-addr: 88pm860x are two chips solution. <reg> stores the I2C address
				of one chip, and this property stores the I2C address of
				another chip.

88pm860x consists of a large and varied group of sub-devices:

Device			 Supply Names	 Description
------			 ------------	 -----------
88pm860x-onkey		:		: On key
88pm860x-rtc		:		: RTC
88pm8607		:		: Regulators
88pm860x-backlight	:		: Backlight
88pm860x-led		:		: Led
88pm860x-touch		:		: Touchscreen

Example:

	pmic: 88pm860x@34 {
		compatible = "marvell,88pm860x";
		reg = <0x34>;
		interrupts = <4>;
		interrupt-parent = <&intc>;
		interrupt-controller;
		#interrupt-cells = <1>;

		marvell,88pm860x-irq-read-clr;
		marvell,88pm860x-slave-addr = <0x11>;

		regulators {
			BUCK1 {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1500000>;
				regulator-boot-on;
				regulator-always-on;
			};
			LDO1 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <2800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
		rtc {
			marvell,88pm860x-vrtc = <1>;
		};
		touch {
			marvell,88pm860x-gpadc-prebias = <1>;
			marvell,88pm860x-gpadc-slot-cycle = <1>;
			marvell,88pm860x-tsi-prebias = <6>;
			marvell,88pm860x-pen-prebias = <16>;
			marvell,88pm860x-pen-prechg = <2>;
			marvell,88pm860x-resistor-X = <300>;
		};
		backlights {
			backlight-0 {
				marvell,88pm860x-iset = <4>;
				marvell,88pm860x-pwm = <3>;
			};
			backlight-2 {
			};
		};
		leds {
			led0-red {
				marvell,88pm860x-iset = <12>;
			};
			led0-green {
				marvell,88pm860x-iset = <12>;
			};
			led0-blue {
				marvell,88pm860x-iset = <12>;
			};
		};
	};


code:
Device-Tree bindings for Active-semi ACT8945A MFD driver

Required properties:
 - compatible: "active-semi,act8945a".
 - reg: the I2C slave address for the ACT8945A chip

The chip exposes two subdevices:
 - a regulators: see ../regulator/act8945a-regulator.txt
 - a charger: see ../power/act8945a-charger.txt

Example:
	pmic@5b {
		compatible = "active-semi,act8945a";
		reg = <0x5b>;

		active-semi,vsel-high;

		regulators {
			vdd_1v35_reg: REG_DCDC1 {
				regulator-name = "VDD_1V35";
				regulator-min-microvolt = <1350000>;
				regulator-max-microvolt = <1350000>;
				regulator-always-on;
			};

			vdd_1v2_reg: REG_DCDC2 {
				regulator-name = "VDD_1V2";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1300000>;
				regulator-always-on;
			};

			vdd_3v3_reg: REG_DCDC3 {
				regulator-name = "VDD_3V3";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vdd_fuse_reg: REG_LDO1 {
				regulator-name = "VDD_FUSE";
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <2500000>;
				regulator-always-on;
			};

			vdd_3v3_lp_reg: REG_LDO2 {
				regulator-name = "VDD_3V3_LP";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vdd_led_reg: REG_LDO3 {
				regulator-name = "VDD_LED";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vdd_sdhc_1v8_reg: REG_LDO4 {
				regulator-name = "VDD_SDHC_1V8";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};
		};

		charger {
			compatible = "active-semi,act8945a-charger";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>;
			interrupt-parent = <&pioA>;
			interrupts = <45 IRQ_TYPE_LEVEL_LOW>;

			active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>;
			active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>;
			active-semi,input-voltage-threshold-microvolt = <6600>;
			active-semi,precondition-timeout = <40>;
			active-semi,total-timeout = <3>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/actions,atc260x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Actions Semi ATC260x Power Management IC bindings

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

description: |
  ATC260x series PMICs integrates Audio Codec, Power Management, RTC, IR
  and GPIO controller blocks. Currently only the PM related functionalities
  (i.e. regulators and system power-off/reboot) for the ATC2603C and ATC2609A
  chip variants are supported.
  ATC2603C includes 3 programmable DC-DC converters, 9 programmable LDO
  regulators and 1 fixed LDO regulator.
  ATC2609A includes 5 programmable DC-DC converters and 10 programmable LDO
  regulators.

allOf:
  - $ref: ../input/input.yaml

properties:
  compatible:
    enum:
      - actions,atc2603c
      - actions,atc2609a

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  reset-time-sec:
    description: |
      Duration in seconds which the key should be kept pressed for device
      to reset automatically. The hardware default is 8. Use 0 to disable
      this functionality.
    enum: [0, 6, 8, 10, 12]

  regulators:
    type: object
    description: |
      List of child nodes specifying the regulators, depending on chip variant:
      * ATC2603C: dcdc[1-3], ldo[1-3,5-8,11,12], switchldo1
      * ATC2609A: dcdc[0-4], ldo[0-9]

    properties:
      compatible:
        enum:
          - actions,atc2603c-regulator
          - actions,atc2609a-regulator

      switchldo1:
        type: object
        $ref: ../regulator/regulator.yaml

        properties:
          regulator-name: true
          regulator-boot-on: true
          regulator-always-on: true
          regulator-min-microvolt: true
          regulator-max-microvolt: true
          regulator-allow-bypass: true
          regulator-active-discharge: true

        additionalProperties: false

    patternProperties:
      "^(dcdc[0-4]|ldo[0-9]|ldo1[1-2]|switchldo1)-supply$":
        description: ATC260x voltage regulators supplies

      "^(dcdc[0-4]|ldo[0-9]|ldo1[1-2])$":
        type: object
        $ref: ../regulator/regulator.yaml

        properties:
          regulator-name: true
          regulator-boot-on: true
          regulator-always-on: true
          regulator-min-microvolt: true
          regulator-max-microvolt: true
          regulator-allow-bypass: true

        additionalProperties: false

    allOf:
      - if:
          properties:
            compatible:
              contains:
                const: actions,atc2603c-regulator
        then:
          patternProperties:
            "^(dcdc[0,4]|ldo[0,4,9])(-supply)?$": false

            "^(ldo|dcdc)":
              properties:
                regulator-allow-bypass: false
      - if:
          properties:
            compatible:
              contains:
                const: actions,atc2609a-regulator
        then:
          patternProperties:
            "^(ldo1[1-2]|switchldo1)(-supply)?$": false

            "^(dcdc|ldo[3-9])":
              properties:
                regulator-allow-bypass: false

    required:
      - compatible

    additionalProperties: false

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        pmic@65 {
            compatible = "actions,atc2603c";
            reg = <0x65>;
            interrupt-parent = <&sirq>;
            interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;

            reset-time-sec = <6>;

            regulators {
                compatible = "actions,atc2603c-regulator";

                dcdc1-supply = <&reg_5v0>;
                dcdc3-supply = <&reg_5v0>;
                ldo5-supply = <&reg_5v0>;
                switchldo1-supply = <&vcc>;

                vdd_cpu: dcdc1 {
                    regulator-name = "VDD_CPU";
                    regulator-min-microvolt = <700000>;
                    regulator-max-microvolt = <1400000>;
                    regulator-always-on;
                };

                vcc: dcdc3 {
                    regulator-name = "VCC";
                    regulator-min-microvolt = <2600000>;
                    regulator-max-microvolt = <3300000>;
                    regulator-always-on;
                };

                vcc_3v1: ldo5 {
                    regulator-name = "VCC_3V1";
                    regulator-min-microvolt = <2600000>;
                    regulator-max-microvolt = <3300000>;
                };

                sd_vcc: switchldo1 {
                    regulator-name = "SD_VCC";
                    regulator-min-microvolt = <3000000>;
                    regulator-max-microvolt = <3300000>;
                    regulator-always-on;
                    regulator-boot-on;
                };
            };
        };
    };

...