code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 STMicroelectronics Limited.
 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 */
#include "st-pincfg.h"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {

	aliases {
		/* 0-5: PIO_SBC */
		gpio0 = &pio0;
		gpio1 = &pio1;
		gpio2 = &pio2;
		gpio3 = &pio3;
		gpio4 = &pio4;
		gpio5 = &pio5;
		/* 10-19: PIO_FRONT0 */
		gpio6 = &pio10;
		gpio7 = &pio11;
		gpio8 = &pio12;
		gpio9 = &pio13;
		gpio10 = &pio14;
		gpio11 = &pio15;
		gpio12 = &pio16;
		gpio13 = &pio17;
		gpio14 = &pio18;
		gpio15 = &pio19;
		/* 20: PIO_FRONT1 */
		gpio16 = &pio20;
		/* 30-35: PIO_REAR */
		gpio17 = &pio30;
		gpio18 = &pio31;
		gpio19 = &pio32;
		gpio20 = &pio33;
		gpio21 = &pio34;
		gpio22 = &pio35;
		/* 40-42: PIO_FLASH */
		gpio23 = &pio40;
		gpio24 = &pio41;
		gpio25 = &pio42;
	};

	soc {
		pin-controller-sbc@961f080 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stih407-sbc-pinctrl";
			st,syscfg = <&syscfg_sbc>;
			reg = <0x0961f080 0x4>;
			reg-names = "irqmux";
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "irqmux";
			ranges = <0 0x09610000 0x6000>;

			pio0: gpio@9610000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x0 0x100>;
				st,bank-name = "PIO0";
			};
			pio1: gpio@9611000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1000 0x100>;
				st,bank-name = "PIO1";
			};
			pio2: gpio@9612000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2000 0x100>;
				st,bank-name = "PIO2";
			};
			pio3: gpio@9613000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x3000 0x100>;
				st,bank-name = "PIO3";
			};
			pio4: gpio@9614000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x4000 0x100>;
				st,bank-name = "PIO4";
			};

			pio5: gpio@9615000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x5000 0x100>;
				st,bank-name = "PIO5";
				st,retime-pin-mask = <0x3f>;
			};

			cec0 {
				pinctrl_cec0_default: cec0-default {
					st,pins {
						hdmi_cec = <&pio2 4 ALT1 BIDIR>;
					};
				};
			};

			rc {
				pinctrl_ir: ir0 {
					st,pins {
						ir = <&pio4 0 ALT2 IN>;
					};
				};

				pinctrl_uhf: uhf0 {
					st,pins {
						ir = <&pio4 1 ALT2 IN>;
					};
				};

				pinctrl_tx: tx0 {
					st,pins {
						tx = <&pio4 2 ALT2 OUT>;
					};
				};

				pinctrl_tx_od: tx_od0 {
					st,pins {
						tx_od = <&pio4 3 ALT2 OUT>;
					};
				};
			};

			/* SBC_ASC0 - UART10 */
			sbc_serial0 {
				pinctrl_sbc_serial0: sbc_serial0-0 {
					st,pins {
						tx = <&pio3 4 ALT1 OUT>;
						rx = <&pio3 5 ALT1 IN>;
					};
				};
			};
			/* SBC_ASC1 - UART11 */
			sbc_serial1 {
				pinctrl_sbc_serial1: sbc_serial1-0 {
					st,pins {
						tx = <&pio2 6 ALT3 OUT>;
						rx = <&pio2 7 ALT3 IN>;
					};
				};
			};

			i2c10 {
				pinctrl_i2c10_default: i2c10-default {
					st,pins {
						sda = <&pio4 6 ALT1 BIDIR>;
						scl = <&pio4 5 ALT1 BIDIR>;
					};
				};
			};

			i2c11 {
				pinctrl_i2c11_default: i2c11-default {
					st,pins {
						sda = <&pio5 1 ALT1 BIDIR>;
						scl = <&pio5 0 ALT1 BIDIR>;
					};
				};
			};

			keyscan {
				pinctrl_keyscan: keyscan {
					st,pins {
						keyin0 = <&pio4 0 ALT6 IN>;
						keyin1 = <&pio4 5 ALT4 IN>;
						keyin2 = <&pio0 4 ALT2 IN>;
						keyin3 = <&pio2 6 ALT2 IN>;

						keyout0 = <&pio4 6 ALT4 OUT>;
						keyout1 = <&pio1 7 ALT2 OUT>;
						keyout2 = <&pio0 6 ALT2 OUT>;
						keyout3 = <&pio2 7 ALT2 OUT>;
					};
				};
			};

			gmac1 {
				/*
				 * Almost all the boards based on STiH407 SoC have an embedded
				 * switch where the mdio/mdc have been used for managing the SMI
				 * iface via I2C. For this reason these lines can be allocated
				 * by using dedicated configuration (in case of there will be a
				 * standard PHY transceiver on-board).
				 */
				pinctrl_rgmii1: rgmii1-0 {
					st,pins {

						txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
						txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
						txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
						txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
						txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
						txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
						rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
						rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
						rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
						rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
						rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
						rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
						clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
						phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
					};
				};

				pinctrl_rgmii1_mdio: rgmii1-mdio {
					st,pins {
						mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
						mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
						mdint = <&pio1 3 ALT1 IN BYPASS 0>;
					};
				};

				pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 {
					st,pins {
						mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
						mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
					};
				};

				pinctrl_mii1: mii1 {
					st,pins {
						txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
						col = <&pio0 7 ALT1 IN BYPASS 1000>;

						mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
						mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
						crs = <&pio1 2 ALT1 IN BYPASS 1000>;
						mdint = <&pio1 3 ALT1 IN BYPASS 0>;
						rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
						phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
					};
				};

				pinctrl_rmii1: rmii1-0 {
					st,pins {
						txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
						mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
						mdint = <&pio1 3 ALT1 IN BYPASS 0>;
						rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>;
						rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>;
						rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>;
						rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
					};
				};

				pinctrl_rmii1_phyclk: rmii1_phyclk {
					st,pins {
						phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
					};
				};

				pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext {
					st,pins {
						phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
					};
				};
			};

			pwm1 {
				pinctrl_pwm1_chan0_default: pwm1-0-default {
					st,pins {
						pwm-out = <&pio3 0 ALT1 OUT>;
						pwm-capturein = <&pio3 2 ALT1 IN>;
					};
				};
				pinctrl_pwm1_chan1_default: pwm1-1-default {
					st,pins {
						pwm-capturein = <&pio4 3 ALT1 IN>;
						pwm-out = <&pio4 4 ALT1 OUT>;
					};
				};
				pinctrl_pwm1_chan2_default: pwm1-2-default {
					st,pins {
						pwm-out = <&pio4 6 ALT3 OUT>;
					};
				};
				pinctrl_pwm1_chan3_default: pwm1-3-default {
					st,pins {
						pwm-out = <&pio4 7 ALT3 OUT>;
					};
				};
			};

			spi10 {
				pinctrl_spi10_default: spi10-4w-alt1-0 {
					st,pins {
						mtsr = <&pio4 6 ALT1 OUT>;
						mrst = <&pio4 7 ALT1 IN>;
						scl = <&pio4 5 ALT1 OUT>;
					};
				};

				pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 {
					st,pins {
						mtsr = <&pio4 6 ALT1 BIDIR_PU>;
						scl = <&pio4 5 ALT1 OUT>;
					};
				};
			};

			spi11 {
				pinctrl_spi11_default: spi11-4w-alt2-0 {
					st,pins {
						mtsr = <&pio3 1 ALT2 OUT>;
						mrst = <&pio3 0 ALT2 IN>;
						scl = <&pio3 2 ALT2 OUT>;
					};
				};

				pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
					st,pins {
						mtsr = <&pio3 1 ALT2 BIDIR_PU>;
						scl = <&pio3 2 ALT2 OUT>;
					};
				};
			};

			spi12 {
				pinctrl_spi12_default: spi12-4w-alt2-0 {
					st,pins {
						mtsr = <&pio3 6 ALT2 OUT>;
						mrst = <&pio3 4 ALT2 IN>;
						scl = <&pio3 7 ALT2 OUT>;
					};
				};

				pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
					st,pins {
						mtsr = <&pio3 6 ALT2 BIDIR_PU>;
						scl = <&pio3 7 ALT2 OUT>;
					};
				};
			};
		};

		pin-controller-front0@920f080 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stih407-front-pinctrl";
			st,syscfg = <&syscfg_front>;
			reg = <0x0920f080 0x4>;
			reg-names = "irqmux";
			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "irqmux";
			ranges = <0 0x09200000 0x10000>;

			pio10: pio@9200000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x0 0x100>;
				st,bank-name = "PIO10";
			};
			pio11: pio@9201000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1000 0x100>;
				st,bank-name = "PIO11";
			};
			pio12: pio@9202000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2000 0x100>;
				st,bank-name = "PIO12";
			};
			pio13: pio@9203000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x3000 0x100>;
				st,bank-name = "PIO13";
			};
			pio14: pio@9204000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x4000 0x100>;
				st,bank-name = "PIO14";
			};
			pio15: pio@9205000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x5000 0x100>;
				st,bank-name = "PIO15";
			};
			pio16: pio@9206000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x6000 0x100>;
				st,bank-name = "PIO16";
			};
			pio17: pio@9207000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x7000 0x100>;
				st,bank-name = "PIO17";
			};
			pio18: pio@9208000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x8000 0x100>;
				st,bank-name = "PIO18";
			};
			pio19: pio@9209000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x9000 0x100>;
				st,bank-name = "PIO19";
			};

			/* Comms */
			serial0 {
				pinctrl_serial0: serial0-0 {
					st,pins {
						tx =  <&pio17 0 ALT1 OUT>;
						rx =  <&pio17 1 ALT1 IN>;
					};
				};
				pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl {
					st,pins {
						tx =  <&pio17 0 ALT1 OUT>;
						rx =  <&pio17 1 ALT1 IN>;
						cts = <&pio17 2 ALT1 IN>;
						rts = <&pio17 3 ALT1 OUT>;
					};
				};
			};

			serial1 {
				pinctrl_serial1: serial1-0 {
					st,pins {
						tx = <&pio16 0 ALT1 OUT>;
						rx = <&pio16 1 ALT1 IN>;
					};
				};
			};

			serial2 {
				pinctrl_serial2: serial2-0 {
					st,pins {
						tx = <&pio15 0 ALT1 OUT>;
						rx = <&pio15 1 ALT1 IN>;
					};
				};
			};

			mmc1 {
				pinctrl_sd1: sd1-0 {
					st,pins {
						sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
						sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
						sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
						sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
						sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
						sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
						sd_led = <&pio16 6 ALT6 OUT>;
						sd_pwren = <&pio16 7 ALT6 OUT>;
						sd_cd = <&pio19 0 ALT6 IN>;
						sd_wp = <&pio19 1 ALT6 IN>;
					};
				};
			};

			i2c0 {
				pinctrl_i2c0_default: i2c0-default {
					st,pins {
						sda = <&pio10 6 ALT2 BIDIR>;
						scl = <&pio10 5 ALT2 BIDIR>;
					};
				};
			};

			i2c1 {
				pinctrl_i2c1_default: i2c1-default {
					st,pins {
						sda = <&pio11 1 ALT2 BIDIR>;
						scl = <&pio11 0 ALT2 BIDIR>;
					};
				};
			};

			i2c2 {
				pinctrl_i2c2_default: i2c2-default {
					st,pins {
						sda = <&pio15 6 ALT2 BIDIR>;
						scl = <&pio15 5 ALT2 BIDIR>;
					};
				};

				pinctrl_i2c2_alt2_1: i2c2-alt2-1 {
					st,pins {
						sda = <&pio12 6 ALT2 BIDIR>;
						scl = <&pio12 5 ALT2 BIDIR>;
					};
				};
			};

			i2c3 {
				pinctrl_i2c3_default: i2c3-alt1-0 {
					st,pins {
						sda = <&pio18 6 ALT1 BIDIR>;
						scl = <&pio18 5 ALT1 BIDIR>;
					};
				};
				pinctrl_i2c3_alt1_1: i2c3-alt1-1 {
					st,pins {
						sda = <&pio17 7 ALT1 BIDIR>;
						scl = <&pio17 6 ALT1 BIDIR>;
					};
				};
				pinctrl_i2c3_alt3_0: i2c3-alt3-0 {
					st,pins {
						sda = <&pio13 6 ALT3 BIDIR>;
						scl = <&pio13 5 ALT3 BIDIR>;
					};
				};
			};

			spi0 {
				pinctrl_spi0_default: spi0-4w-alt2-0 {
					st,pins {
						mtsr = <&pio10 6 ALT2 OUT>;
						mrst = <&pio10 7 ALT2 IN>;
						scl = <&pio10 5 ALT2 OUT>;
					};
				};

				pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
					st,pins {
						mtsr = <&pio10 6 ALT2 BIDIR_PU>;
						scl = <&pio10 5 ALT2 OUT>;
					};
				};

				pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 {
					st,pins {
						mtsr = <&pio19 7 ALT1 OUT>;
						mrst = <&pio19 5 ALT1 IN>;
						scl = <&pio19 6 ALT1 OUT>;
					};
				};

				pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 {
					st,pins {
						mtsr = <&pio19 7 ALT1 BIDIR_PU>;
						scl = <&pio19 6 ALT1 OUT>;
					};
				};
			};

			spi1 {
				pinctrl_spi1_default: spi1-4w-alt2-0 {
					st,pins {
						mtsr = <&pio11 1 ALT2 OUT>;
						mrst = <&pio11 2 ALT2 IN>;
						scl = <&pio11 0 ALT2 OUT>;
					};
				};

				pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
					st,pins {
						mtsr = <&pio11 1 ALT2 BIDIR_PU>;
						scl = <&pio11 0 ALT2 OUT>;
					};
				};

				pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 {
					st,pins {
						mtsr = <&pio14 3 ALT1 OUT>;
						mrst = <&pio14 4 ALT1 IN>;
						scl = <&pio14 2 ALT1 OUT>;
					};
				};

				pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 {
					st,pins {
						mtsr = <&pio14 3 ALT1 BIDIR_PU>;
						scl = <&pio14 2 ALT1 OUT>;
					};
				};
			};

			spi2 {
				pinctrl_spi2_default: spi2-4w-alt2-0 {
					st,pins {
						mtsr = <&pio12 6 ALT2 OUT>;
						mrst = <&pio12 7 ALT2 IN>;
						scl = <&pio12 5 ALT2 OUT>;
					};
				};

				pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
					st,pins {
						mtsr = <&pio12 6 ALT2 BIDIR_PU>;
						scl = <&pio12 5 ALT2 OUT>;
					};
				};

				pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 {
					st,pins {
						mtsr = <&pio14 6 ALT1 OUT>;
						mrst = <&pio14 7 ALT1 IN>;
						scl = <&pio14 5 ALT1 OUT>;
					};
				};

				pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 {
					st,pins {
						mtsr = <&pio14 6 ALT1 BIDIR_PU>;
						scl = <&pio14 5 ALT1 OUT>;
					};
				};

				pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
					st,pins {
						mtsr = <&pio15 6 ALT2 OUT>;
						mrst = <&pio15 7 ALT2 IN>;
						scl = <&pio15 5 ALT2 OUT>;
					};
				};

				pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
					st,pins {
						mtsr = <&pio15 6 ALT2 BIDIR_PU>;
						scl = <&pio15 5 ALT2 OUT>;
					};
				};
			};

			spi3 {
				pinctrl_spi3_default: spi3-4w-alt3-0 {
					st,pins {
						mtsr = <&pio13 6 ALT3 OUT>;
						mrst = <&pio13 7 ALT3 IN>;
						scl = <&pio13 5 ALT3 OUT>;
					};
				};

				pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 {
					st,pins {
						mtsr = <&pio13 6 ALT3 BIDIR_PU>;
						scl = <&pio13 5 ALT3 OUT>;
					};
				};

				pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 {
					st,pins {
						mtsr = <&pio17 7 ALT1 OUT>;
						mrst = <&pio17 5 ALT1 IN>;
						scl = <&pio17 6 ALT1 OUT>;
					};
				};

				pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 {
					st,pins {
						mtsr = <&pio17 7 ALT1 BIDIR_PU>;
						scl = <&pio17 6 ALT1 OUT>;
					};
				};

				pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 {
					st,pins {
						mtsr = <&pio18 6 ALT1 OUT>;
						mrst = <&pio18 7 ALT1 IN>;
						scl = <&pio18 5 ALT1 OUT>;
					};
				};

				pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 {
					st,pins {
						mtsr = <&pio18 6 ALT1 BIDIR_PU>;
						scl = <&pio18 5 ALT1 OUT>;
					};
				};
			};

			tsin0 {
				pinctrl_tsin0_parallel: tsin0_parallel {
					st,pins {
						DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
						VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
					};
				};
				pinctrl_tsin0_serial: tsin0_serial {
					st,pins {
						DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
						VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
					};
				};
			};

			tsin1 {
				pinctrl_tsin1_parallel: tsin1_parallel {
					st,pins {
						DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
						VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
					};
				};
				pinctrl_tsin1_serial: tsin1_serial {
					st,pins {
						DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
						VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
					};
				};
			};

			tsin2 {
				pinctrl_tsin2_parallel: tsin2_parallel {
					st,pins {
						DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;
						DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;
						DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;
						DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
						DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;
						DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
						DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
						VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
					};
				};
				pinctrl_tsin2_serial: tsin2_serial {
					st,pins {
						DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
						VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
					};
				};
			};

			tsin3 {
				pinctrl_tsin3_serial: tsin3_serial {
					st,pins {
						DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>;
						VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
					};
				};
			};

			tsin4 {
				pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 {
					st,pins {
						DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>;
						VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>;
						ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>;
						PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
					};
				};
			};

			tsin5 {
				pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 {
					st,pins {
						DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
						VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
					};
				};
				pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 {
					st,pins {
						DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;
						VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
					};
				};
			};

			tsout0 {
				pinctrl_tsout0_parallel: tsout0_parallel {
					st,pins {
						DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
						VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
					};
				};
				pinctrl_tsout0_serial: tsout0_serial {
					st,pins {
						DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
						VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
					};
				};
			};

			tsout1 {
				pinctrl_tsout1_serial: tsout1_serial {
					st,pins {
						DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>;
						VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
					};
				};
			};

			mtsin0 {
				pinctrl_mtsin0_parallel: mtsin0_parallel {
					st,pins {
						DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
						DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>;
						DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
						DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>;
						DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
						DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
						DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
						DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>;
						VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
					};
				};
			};

			systrace {
				pinctrl_systrace_default: systrace-default {
					st,pins {
						trc_data0 = <&pio11 3 ALT5 OUT>;
						trc_data1 = <&pio11 4 ALT5 OUT>;
						trc_data2 = <&pio11 5 ALT5 OUT>;
						trc_data3 = <&pio11 6 ALT5 OUT>;
						trc_clk   = <&pio11 7 ALT5 OUT>;
					};
				};
			};
		};

		pin-controller-front1@921f080 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stih407-front-pinctrl";
			st,syscfg = <&syscfg_front>;
			reg = <0x0921f080 0x4>;
			reg-names = "irqmux";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "irqmux";
			ranges = <0 0x09210000 0x10000>;

			pio20: pio@9210000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x0 0x100>;
				st,bank-name = "PIO20";
			};

			tsin4 {
				pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 {
					st,pins {
						DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
						VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
					};
				};
			};
		};

		pin-controller-rear@922f080 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stih407-rear-pinctrl";
			st,syscfg = <&syscfg_rear>;
			reg = <0x0922f080 0x4>;
			reg-names = "irqmux";
			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "irqmux";
			ranges = <0 0x09220000 0x6000>;

			pio30: gpio@9220000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x0 0x100>;
				st,bank-name = "PIO30";
			};
			pio31: gpio@9221000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1000 0x100>;
				st,bank-name = "PIO31";
			};
			pio32: gpio@9222000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2000 0x100>;
				st,bank-name = "PIO32";
			};
			pio33: gpio@9223000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x3000 0x100>;
				st,bank-name = "PIO33";
			};
			pio34: gpio@9224000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x4000 0x100>;
				st,bank-name = "PIO34";
			};
			pio35: gpio@9225000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x5000 0x100>;
				st,bank-name = "PIO35";
				st,retime-pin-mask = <0x7f>;
			};

			i2c4 {
				pinctrl_i2c4_default: i2c4-default {
					st,pins {
						sda = <&pio30 1 ALT1 BIDIR>;
						scl = <&pio30 0 ALT1 BIDIR>;
					};
				};
			};

			i2c5 {
				pinctrl_i2c5_default: i2c5-default {
					st,pins {
						sda = <&pio34 4 ALT1 BIDIR>;
						scl = <&pio34 3 ALT1 BIDIR>;
					};
				};
			};

			usb3 {
				pinctrl_usb3: usb3-2 {
					st,pins {
						usb-oc-detect = <&pio35 4 ALT1 IN>;
						usb-pwr-enable = <&pio35 5 ALT1 OUT>;
						usb-vbus-valid = <&pio35 6 ALT1 IN>;
					};
				};
			};

			pwm0 {
				pinctrl_pwm0_chan0_default: pwm0-0-default {
					st,pins {
						pwm-capturein = <&pio31 0 ALT1 IN>;
						pwm-out = <&pio31 1 ALT1 OUT>;
					};
				};
			};

			spi4 {
				pinctrl_spi4_default: spi4-4w-alt1-0 {
					st,pins {
						mtsr = <&pio30 1 ALT1 OUT>;
						mrst = <&pio30 2 ALT1 IN>;
						scl = <&pio30 0 ALT1 OUT>;
					};
				};

				pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 {
					st,pins {
						mtsr = <&pio30 1 ALT1 BIDIR_PU>;
						scl = <&pio30 0 ALT1 OUT>;
					};
				};

				pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 {
					st,pins {
						mtsr = <&pio34 1 ALT3 OUT>;
						mrst = <&pio34 2 ALT3 IN>;
						scl = <&pio34 0 ALT3 OUT>;
					};
				};

				pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 {
					st,pins {
						mtsr = <&pio34 1 ALT3 BIDIR_PU>;
						scl = <&pio34 0 ALT3 OUT>;
					};
				};
			};

			i2s_out {
				pinctrl_i2s_8ch_out: i2s_8ch_out{
					st,pins {
						mclk = <&pio33 5 ALT1 OUT>;
						lrclk = <&pio33 7 ALT1 OUT>;
						sclk = <&pio33 6 ALT1 OUT>;
						data0 = <&pio33 4 ALT1 OUT>;
						data1 = <&pio34 0 ALT1 OUT>;
						data2 = <&pio34 1 ALT1 OUT>;
						data3 = <&pio34 2 ALT1 OUT>;
					};
				};

				pinctrl_i2s_2ch_out: i2s_2ch_out{
					st,pins {
						mclk = <&pio33 5 ALT1 OUT>;
						lrclk = <&pio33 7 ALT1 OUT>;
						sclk = <&pio33 6 ALT1 OUT>;
						data0 = <&pio33 4 ALT1 OUT>;
					};
				};
			};

			i2s_in {
				pinctrl_i2s_8ch_in: i2s_8ch_in{
					st,pins {
						mclk = <&pio32 5 ALT1 IN>;
						lrclk = <&pio32 7 ALT1 IN>;
						sclk = <&pio32 6 ALT1 IN>;
						data0 = <&pio32 4 ALT1 IN>;
						data1 = <&pio33 0 ALT1 IN>;
						data2 = <&pio33 1 ALT1 IN>;
						data3 = <&pio33 2 ALT1 IN>;
						data4 = <&pio33 3 ALT1 IN>;
					};
				};

				pinctrl_i2s_2ch_in: i2s_2ch_in{
					st,pins {
						mclk = <&pio32 5 ALT1 IN>;
						lrclk = <&pio32 7 ALT1 IN>;
						sclk = <&pio32 6 ALT1 IN>;
						data0 = <&pio32 4 ALT1 IN>;
					};
				};
			};

			spdif_out {
				pinctrl_spdif_out: spdif_out{
					st,pins {
						spdif_out = <&pio34 7 ALT1 OUT>;
					};
				};
			};

			serial3 {
				pinctrl_serial3: serial3-0 {
					st,pins {
						tx = <&pio31 3 ALT1 OUT>;
						rx = <&pio31 4 ALT1 IN>;
					};
				};
			};
		};

		pin-controller-flash@923f080 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stih407-flash-pinctrl";
			st,syscfg = <&syscfg_flash>;
			reg = <0x0923f080 0x4>;
			reg-names = "irqmux";
			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "irqmux";
			ranges = <0 0x09230000 0x3000>;

			pio40: gpio@9230000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0 0x100>;
				st,bank-name = "PIO40";
			};
			pio41: gpio@9231000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1000 0x100>;
				st,bank-name = "PIO41";
			};
			pio42: gpio@9232000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2000 0x100>;
				st,bank-name = "PIO42";
			};

			mmc0 {
				pinctrl_mmc0: mmc0-0 {
					st,pins {
						emmc_clk = <&pio40 6 ALT1 BIDIR>;
						emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
						emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
						emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
						emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
						emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
						emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
						emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
						emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
						emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
					};
				};
				pinctrl_sd0: sd0-0 {
					st,pins {
						sd_clk = <&pio40 6 ALT1 BIDIR>;
						sd_cmd = <&pio40 7 ALT1 BIDIR_PU>;
						sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>;
						sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>;
						sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>;
						sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>;
						sd_led = <&pio42 0 ALT2 OUT>;
						sd_pwren = <&pio42 2 ALT2 OUT>;
						sd_vsel = <&pio42 3 ALT2 OUT>;
						sd_cd = <&pio42 4 ALT2 IN>;
						sd_wp = <&pio42 5 ALT2 IN>;
					};
				};
			};

			fsm {
				pinctrl_fsm: fsm {
					st,pins {
						spi-fsm-clk = <&pio40 1 ALT1 OUT>;
						spi-fsm-cs = <&pio40 0 ALT1 OUT>;
						spi-fsm-mosi = <&pio40 2 ALT1 OUT>;
						spi-fsm-miso = <&pio40 3 ALT1 IN>;
						spi-fsm-hol = <&pio40 5 ALT1 OUT>;
						spi-fsm-wp = <&pio40 4 ALT1 OUT>;
					};
				};
			};

			nand {
				pinctrl_nand: nand {
					st,pins {
						nand_cs1 = <&pio40 6 ALT3 OUT>;
						nand_cs0 = <&pio40 7 ALT3 OUT>;
						nand_d0 = <&pio41 0 ALT3 BIDIR>;
						nand_d1 = <&pio41 1 ALT3 BIDIR>;
						nand_d2 = <&pio41 2 ALT3 BIDIR>;
						nand_d3 = <&pio41 3 ALT3 BIDIR>;
						nand_d4 = <&pio41 4 ALT3 BIDIR>;
						nand_d5 = <&pio41 5 ALT3 BIDIR>;
						nand_d6 = <&pio41 6 ALT3 BIDIR>;
						nand_d7 = <&pio41 7 ALT3 BIDIR>;
						nand_we = <&pio42 0 ALT3 OUT>;
						nand_dqs = <&pio42 1 ALT3 OUT>;
						nand_ale = <&pio42 2 ALT3 OUT>;
						nand_cle = <&pio42 3 ALT3 OUT>;
						nand_rnb = <&pio42 4 ALT3 IN>;
						nand_oe = <&pio42 5 ALT3 OUT>;
					};
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 STMicroelectronics Limited.
 * Author: Gabriel Fernandez <gabriel.fernandez@linaro.org>
 */
#include "stih407-clock.dtsi"
#include "stih407-family.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
	soc {
		sti-display-subsystem@0 {
			compatible = "st,sti-display-subsystem";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0 0>;
			assigned-clocks = <&clk_s_d2_quadfs 0>,
					  <&clk_s_d2_quadfs 1>,
					  <&clk_s_c0_pll1 0>,
					  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					  <&clk_s_c0_flexgen CLK_MAIN_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP1>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP2>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP3>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP4>;

			assigned-clock-parents = <0>,
						 <0>,
						 <0>,
						 <&clk_s_c0_pll1 0>,
						 <&clk_s_c0_pll1 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 1>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>;

			assigned-clock-rates = <297000000>,
					       <108000000>,
					       <0>,
					       <400000000>,
					       <400000000>;

			ranges;

			sti-compositor@9d11000 {
				compatible = "st,stih407-compositor";
				reg = <0x9d11000 0x1000>;

				clock-names = "compo_main",
					      "compo_aux",
					      "pix_main",
					      "pix_aux",
					      "pix_gdp1",
					      "pix_gdp2",
					      "pix_gdp3",
					      "pix_gdp4",
					      "main_parent",
					      "aux_parent";

				clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;

				reset-names = "compo-main", "compo-aux";
				resets = <&softreset STIH407_COMPO_SOFTRESET>,
					 <&softreset STIH407_COMPO_SOFTRESET>;
				st,vtg = <&vtg_main>, <&vtg_aux>;
			};

			sti-tvout@8d08000 {
				compatible = "st,stih407-tvout";
				reg = <0x8d08000 0x1000>;
				reg-names = "tvout-reg";
				reset-names = "tvout";
				resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
				#address-cells = <1>;
				#size-cells = <1>;
				assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
						  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
						  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
						  <&clk_s_d0_flexgen CLK_PCM_0>,
						  <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
						  <&clk_s_d2_flexgen CLK_HDDAC>;

				assigned-clock-parents = <&clk_s_d2_quadfs 0>,
							 <&clk_tmdsout_hdmi>,
							 <&clk_s_d2_quadfs 0>,
							 <&clk_s_d0_quadfs 0>,
							 <&clk_s_d2_quadfs 0>,
							 <&clk_s_d2_quadfs 0>;
			};

			sti_hdmi: sti-hdmi@8d04000 {
				compatible = "st,stih407-hdmi";
				reg = <0x8d04000 0x1000>;
				reg-names = "hdmi-reg";
				#sound-dai-cells = <0>;
				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "irq";
				clock-names = "pix",
					      "tmds",
					      "phy",
					      "audio",
					      "main_parent",
					      "aux_parent";

				clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
					 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
					 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
					 <&clk_s_d0_flexgen CLK_PCM_0>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;

				hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
				reset-names = "hdmi";
				resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
				ddc = <&hdmiddc>;
			};

			sti-hda@8d02000 {
				compatible = "st,stih407-hda";
				reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
				reg-names = "hda-reg", "video-dacs-ctrl";
				clock-names = "pix",
					      "hddac",
					      "main_parent",
					      "aux_parent";
				clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
					 <&clk_s_d2_flexgen CLK_HDDAC>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;
			};
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
 * Author: Peter Griffin <peter.griffin@linaro.org>
 */
/dts-v1/;
#include "stih410.dtsi"
#include "stihxxx-b2120.dtsi"
/ {
	model = "STiH410 B2120";
	compatible = "st,stih410-b2120", "st,stih410";

	chosen {
		stdout-path = &sbc_serial0;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0x80000000>;
	};

	aliases {
		serial0 = &sbc_serial0;
		ethernet0 = &ethernet0;
	};

	usb2_picophy1: phy2 {
		status = "okay";
	};

	usb2_picophy2: phy3 {
		status = "okay";
	};

	soc {

		mmc0: sdhci@9060000 {
			max-frequency = <200000000>;
			sd-uhs-sdr50;
			sd-uhs-sdr104;
			sd-uhs-ddr50;
		};

		ohci0: usb@9a03c00 {
			status = "okay";
		};

		ehci0: usb@9a03e00 {
			status = "okay";
		};

		ohci1: usb@9a83c00 {
			status = "okay";
		};

		ehci1: usb@9a83e00 {
			status = "okay";
		};

		sti-display-subsystem@0 {
			sti-hda@8d02000 {
				status = "okay";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2016 STMicroelectronics (R&D) Limited.
 * Author: Patrice Chotard <patrice.chotard@st.com>
 */
/dts-v1/;
#include "stih410.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "STiH410 B2260";
	compatible = "st,stih410-b2260", "st,stih410";

	chosen {
		stdout-path = &uart1;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0x40000000>;
	};

	aliases {
		serial1 = &uart1;
		ethernet0 = &ethernet0;
	};

	leds {
		compatible = "gpio-leds";
		led-user-green-1 {
			label = "User_green_1";
			gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
			default-state = "off";
		};

		led-user-green-2 {
			label = "User_green_2";
			gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-user-green-3 {
			label = "User_green_3";
			gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-user-green-4 {
			label = "User_green_4";
			gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};

	sound: sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "STI-B2260";
		status = "okay";
		#address-cells = <1>;
		#size-cells = <0>;

		simple-audio-card,dai-link@0 {
			reg = <0>;
			/* DAC */
			format = "i2s";
			mclk-fs = <128>;
			cpu {
				sound-dai = <&sti_uni_player0>;
			};

			codec {
				sound-dai = <&sti_hdmi>;
			};
		};
	};

	miphy28lp_phy: miphy28lp {

		phy_port1: port@9b2a000 {
			st,osc-force-ext;
		};
	};

	usb2_picophy1: phy2 {
		status = "okay";
	};

	usb2_picophy2: phy3 {
		status = "okay";
	};

	soc {
		/* Low speed expansion connector */
		uart0: serial@9830000 {
			label = "LS-UART0";
			pinctrl-names = "default", "no-hw-flowctrl";
			pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>;
			pinctrl-1 = <&pinctrl_serial0>;
			rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>;
			uart-has-rtscts;
			status = "okay";
		};

		/* Low speed expansion connector */
		uart1: serial@9831000 {
			label = "LS-UART1";
			status = "okay";
		};

		/* Low speed expansion connector */
		spi0: spi@9844000 {
			label = "LS-SPI0";
			cs-gpios = <&pio30 3 0>;
			status = "okay";
		};

		/* Low speed expansion connector */
		i2c0: i2c@9840000 {
			label = "LS-I2C0";
			status = "okay";
		};

		/* Low speed expansion connector */
		i2c1: i2c@9841000 {
			label = "LS-I2C1";
			status = "okay";
		};

		/* high speed expansion connector */
		i2c2: i2c@9842000 {
			label = "HS-I2C2";
			pinctrl-0 = <&pinctrl_i2c2_alt2_1>;
			status = "okay";
		};

		/* high speed expansion connector */
		i2c3: i2c@9843000 {
			label = "HS-I2C3";
			pinctrl-0 = <&pinctrl_i2c3_alt3_0>;
			status = "okay";
		};

		mmc0: sdhci@9060000 {
			pinctrl-0 = <&pinctrl_sd0>;
			bus-width = <4>;
			status = "okay";
		};

		/* high speed expansion connector */
		mmc1: sdhci@9080000 {
			status = "okay";
		};

		pwm0: pwm@9810000 {
			status = "okay";
		};

		pwm1: pwm@9510000 {
			status = "okay";
		};

		ohci0: usb@9a03c00 {
			status = "okay";
		};

		ehci0: usb@9a03e00 {
			status = "okay";
		};

		ohci1: usb@9a83c00 {
			status = "okay";
		};

		ehci1: usb@9a83e00 {
			status = "okay";
		};

		st_dwc3: dwc3@8f94000 {
			status = "okay";
		};

		ethernet0: dwmac@9630000 {
			phy-mode = "rgmii";
			pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>;

			snps,reset-gpio = <&pio0 7 0>;
			snps,reset-active-low;
			snps,reset-delays-us = <0 10000 1000000>;

			status = "okay";
		};

		sti_uni_player0: sti-uni-player@8d80000 {
			status = "okay";
		};
		/* SSC11 to HDMI */
		hdmiddc: i2c@9541000 {
			/* HDMI V1.3a supports Standard mode only */
			clock-frequency = <100000>;
			st,i2c-min-scl-pulse-width-us = <0>;
			st,i2c-min-sda-pulse-width-us = <5>;
			status = "okay";
		};

		sata1: sata@9b28000 {
			status = "okay";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 STMicroelectronics R&D Limited
 */
#include <dt-bindings/clock/stih410-clks.h>
/ {
	/*
	 * Fixed 30MHz oscillator inputs to SoC
	 */
	clk_sysin: clk-sysin {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <30000000>;
		clock-output-names = "CLK_SYSIN";
	};

	clk_tmdsout_hdmi: clk-tmdsout-hdmi {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		compatible = "st,stih410-clk", "simple-bus";

		/*
		 * A9 PLL.
		 */
		clockgen-a9@92b0000 {
			compatible = "st,clkgen-c32";
			reg = <0x92b0000 0x10000>;

			clockgen_a9_pll: clockgen-a9-pll {
				#clock-cells = <1>;
				compatible = "st,stih407-clkgen-plla9";

				clocks = <&clk_sysin>;
			};

			/*
			 * ARM CPU related clocks.
			 */
			clk_m_a9: clk-m-a9 {
				#clock-cells = <0>;
				compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";

				clocks = <&clockgen_a9_pll 0>,
					 <&clockgen_a9_pll 0>,
					 <&clk_s_c0_flexgen 13>,
					 <&clk_m_a9_ext2f_div2>;

				/*
				 * ARM Peripheral clock for timers
				 */
				arm_periph_clk: clk-m-a9-periphs {
					#clock-cells = <0>;
					compatible = "fixed-factor-clock";
					clocks = <&clk_m_a9>;
					clock-div = <2>;
					clock-mult = <1>;
				};
			};
		};

		clockgen-a@90ff000 {
			compatible = "st,clkgen-c32";
			reg = <0x90ff000 0x1000>;

			clk_s_a0_pll: clk-s-a0-pll {
				#clock-cells = <1>;
				compatible = "st,clkgen-pll0-a0";

				clocks = <&clk_sysin>;
			};

			clk_s_a0_flexgen: clk-s-a0-flexgen {
				compatible = "st,flexgen", "st,flexgen-stih410-a0";

				#clock-cells = <1>;

				clocks = <&clk_s_a0_pll 0>,
					 <&clk_sysin>;
			};
		};

		clk_s_c0: clockgen-c@9103000 {
			compatible = "st,clkgen-c32";
			reg = <0x9103000 0x1000>;

			clk_s_c0_pll0: clk-s-c0-pll0 {
				#clock-cells = <1>;
				compatible = "st,clkgen-pll0-c0";

				clocks = <&clk_sysin>;
			};

			clk_s_c0_pll1: clk-s-c0-pll1 {
				#clock-cells = <1>;
				compatible = "st,clkgen-pll1-c0";

				clocks = <&clk_sysin>;
			};

			clk_s_c0_quadfs: clk-s-c0-quadfs {
				#clock-cells = <1>;
				compatible = "st,quadfs-pll";

				clocks = <&clk_sysin>;
			};

			clk_s_c0_flexgen: clk-s-c0-flexgen {
				#clock-cells = <1>;
				compatible = "st,flexgen", "st,flexgen-stih410-c0";

				clocks = <&clk_s_c0_pll0 0>,
					 <&clk_s_c0_pll1 0>,
					 <&clk_s_c0_quadfs 0>,
					 <&clk_s_c0_quadfs 1>,
					 <&clk_s_c0_quadfs 2>,
					 <&clk_s_c0_quadfs 3>,
					 <&clk_sysin>;

				/*
				 * ARM Peripheral clock for timers
				 */
				clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
					#clock-cells = <0>;
					compatible = "fixed-factor-clock";

					clocks = <&clk_s_c0_flexgen 13>;

					clock-output-names = "clk-m-a9-ext2f-div2";

					clock-div = <2>;
					clock-mult = <1>;
				};
			};
		};

		clockgen-d0@9104000 {
			compatible = "st,clkgen-c32";
			reg = <0x9104000 0x1000>;

			clk_s_d0_quadfs: clk-s-d0-quadfs {
				#clock-cells = <1>;
				compatible = "st,quadfs-d0";

				clocks = <&clk_sysin>;
			};

			clk_s_d0_flexgen: clk-s-d0-flexgen {
				#clock-cells = <1>;
				compatible = "st,flexgen", "st,flexgen-stih410-d0";

				clocks = <&clk_s_d0_quadfs 0>,
					 <&clk_s_d0_quadfs 1>,
					 <&clk_s_d0_quadfs 2>,
					 <&clk_s_d0_quadfs 3>,
					 <&clk_sysin>;
			};
		};

		clockgen-d2@9106000 {
			compatible = "st,clkgen-c32";
			reg = <0x9106000 0x1000>;

			clk_s_d2_quadfs: clk-s-d2-quadfs {
				#clock-cells = <1>;
				compatible = "st,quadfs-d2";

				clocks = <&clk_sysin>;
			};

			clk_s_d2_flexgen: clk-s-d2-flexgen {
				#clock-cells = <1>;
				compatible = "st,flexgen", "st,flexgen-stih407-d2";

				clocks = <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>,
					 <&clk_s_d2_quadfs 2>,
					 <&clk_s_d2_quadfs 3>,
					 <&clk_sysin>,
					 <&clk_sysin>,
					 <&clk_tmdsout_hdmi>;
			};
		};

		clockgen-d3@9107000 {
			compatible = "st,clkgen-c32";
			reg = <0x9107000 0x1000>;

			clk_s_d3_quadfs: clk-s-d3-quadfs {
				#clock-cells = <1>;
				compatible = "st,quadfs-d3";

				clocks = <&clk_sysin>;
			};

			clk_s_d3_flexgen: clk-s-d3-flexgen {
				#clock-cells = <1>;
				compatible = "st,flexgen", "st,flexgen-stih407-d3";

				clocks = <&clk_s_d3_quadfs 0>,
					 <&clk_s_d3_quadfs 1>,
					 <&clk_s_d3_quadfs 2>,
					 <&clk_s_d3_quadfs 3>,
					 <&clk_sysin>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 STMicroelectronics Limited.
 * Author: Peter Griffin <peter.griffin@linaro.org>
 */
#include "st-pincfg.h"
/ {

	soc {
		pin-controller-rear@922f080 {

			usb0 {
				pinctrl_usb0: usb2-0 {
					st,pins {
						usb-oc-detect = <&pio35 0 ALT1 IN>;
						usb-pwr-enable = <&pio35 1 ALT1 OUT>;
					};
				};
			};

			usb1 {
				pinctrl_usb1: usb2-1 {
					st,pins {
						usb-oc-detect = <&pio35 2 ALT1 IN>;
						usb-pwr-enable = <&pio35 3 ALT1 OUT>;
					};
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 STMicroelectronics Limited.
 * Author: Peter Griffin <peter.griffin@linaro.org>
 */
#include "stih410-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
	aliases {
		bdisp0 = &bdisp0;
	};

	usb2_picophy1: phy2 {
		compatible = "st,stih407-usb2-phy";
		#phy-cells = <0>;
		st,syscfg = <&syscfg_core 0xf8 0xf4>;
		resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
			 <&picophyreset STIH407_PICOPHY0_RESET>;
		reset-names = "global", "port";

		status = "disabled";
	};

	usb2_picophy2: phy3 {
		compatible = "st,stih407-usb2-phy";
		#phy-cells = <0>;
		st,syscfg = <&syscfg_core 0xfc 0xf4>;
		resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
			 <&picophyreset STIH407_PICOPHY1_RESET>;
		reset-names = "global", "port";

		status = "disabled";
	};

	soc {
		ohci0: usb@9a03c00 {
			compatible = "st,st-ohci-300x";
			reg = <0x9a03c00 0x100>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy1>;
			phy-names = "usb";

			status = "disabled";
		};

		ehci0: usb@9a03e00 {
			compatible = "st,st-ehci-300x";
			reg = <0x9a03e00 0x100>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy1>;
			phy-names = "usb";

			status = "disabled";
		};

		ohci1: usb@9a83c00 {
			compatible = "st,st-ohci-300x";
			reg = <0x9a83c00 0x100>;
			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy2>;
			phy-names = "usb";

			status = "disabled";
		};

		ehci1: usb@9a83e00 {
			compatible = "st,st-ehci-300x";
			reg = <0x9a83e00 0x100>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy2>;
			phy-names = "usb";

			status = "disabled";
		};

		sti-display-subsystem@0 {
			compatible = "st,sti-display-subsystem";
			#address-cells = <1>;
			#size-cells = <1>;

			reg = <0 0>;
			assigned-clocks = <&clk_s_d2_quadfs 0>,
					  <&clk_s_d2_quadfs 1>,
					  <&clk_s_c0_pll1 0>,
					  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					  <&clk_s_c0_flexgen CLK_MAIN_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP1>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP2>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP3>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP4>;

			assigned-clock-parents = <0>,
						 <0>,
						 <0>,
						 <&clk_s_c0_pll1 0>,
						 <&clk_s_c0_pll1 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 1>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>;

			assigned-clock-rates = <297000000>,
					       <297000000>,
					       <0>,
					       <400000000>,
					       <400000000>;

			ranges;

			sti-compositor@9d11000 {
				compatible = "st,stih407-compositor";
				reg = <0x9d11000 0x1000>;

				clock-names = "compo_main",
					      "compo_aux",
					      "pix_main",
					      "pix_aux",
					      "pix_gdp1",
					      "pix_gdp2",
					      "pix_gdp3",
					      "pix_gdp4",
					      "main_parent",
					      "aux_parent";

				clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;

				reset-names = "compo-main", "compo-aux";
				resets = <&softreset STIH407_COMPO_SOFTRESET>,
					 <&softreset STIH407_COMPO_SOFTRESET>;
				st,vtg = <&vtg_main>, <&vtg_aux>;
			};

			sti-tvout@8d08000 {
				compatible = "st,stih407-tvout";
				reg = <0x8d08000 0x1000>;
				reg-names = "tvout-reg";
				reset-names = "tvout";
				resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
				#address-cells = <1>;
				#size-cells = <1>;
				assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
						  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
						  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
						  <&clk_s_d0_flexgen CLK_PCM_0>,
						  <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
						  <&clk_s_d2_flexgen CLK_HDDAC>;

				assigned-clock-parents = <&clk_s_d2_quadfs 0>,
							 <&clk_tmdsout_hdmi>,
							 <&clk_s_d2_quadfs 0>,
							 <&clk_s_d0_quadfs 0>,
							 <&clk_s_d2_quadfs 0>,
							 <&clk_s_d2_quadfs 0>;
			};

			sti_hdmi: sti-hdmi@8d04000 {
				compatible = "st,stih407-hdmi";
				reg = <0x8d04000 0x1000>;
				reg-names = "hdmi-reg";
				#sound-dai-cells = <0>;
				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "irq";
				clock-names = "pix",
					      "tmds",
					      "phy",
					      "audio",
					      "main_parent",
					      "aux_parent";

				clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
					 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
					 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
					 <&clk_s_d0_flexgen CLK_PCM_0>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;

				hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
				reset-names = "hdmi";
				resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
				ddc = <&hdmiddc>;
			};

			sti-hda@8d02000 {
				compatible = "st,stih407-hda";
				status = "disabled";
				reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
				reg-names = "hda-reg", "video-dacs-ctrl";
				clock-names = "pix",
					      "hddac",
					      "main_parent",
					      "aux_parent";
				clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
					 <&clk_s_d2_flexgen CLK_HDDAC>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;
			};

			sti-hqvdp@9c00000 {
				compatible = "st,stih407-hqvdp";
				reg = <0x9C00000 0x100000>;
				clock-names = "hqvdp", "pix_main";
				clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
				reset-names = "hqvdp";
				resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
				st,vtg = <&vtg_main>;
			};
		};

		bdisp0:bdisp@9f10000 {
			compatible = "st,stih407-bdisp";
			reg = <0x9f10000 0x1000>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "bdisp";
			clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
		};

		hva@8c85000 {
			compatible = "st,st-hva";
			reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
			reg-names = "hva_registers", "hva_esram";
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "clk_hva";
			clocks = <&clk_s_c0_flexgen CLK_HVA>;
		};

		thermal@91a0000 {
			compatible = "st,stih407-thermal";
			reg = <0x91a0000 0x28>;
			clock-names = "thermal";
			clocks = <&clk_sysin>;
			interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
		};

		sti-cec@94a087c {
			compatible = "st,stih-cec";
			reg = <0x94a087c 0x64>;
			clocks = <&clk_sysin>;
			clock-names = "cec-clk";
			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "cec-irq";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_cec0_default>;
			resets = <&softreset STIH407_LPM_SOFTRESET>;
			hdmi-phandle = <&sti_hdmi>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 STMicroelectronics (R&D) Limited.
 * Author: Maxime Coquelin <maxime.coquelin@st.com>
 */
/dts-v1/;
#include "stih418.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
	model = "STiH418 B2199";
	compatible = "st,stih418-b2199", "st,stih418";

	chosen {
		stdout-path = &sbc_serial0;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0xc0000000>;
	};

	aliases {
		serial0 = &sbc_serial0;
		ethernet0 = &ethernet0;
	};

	leds {
		compatible = "gpio-leds";
		led-red {
			label = "Front Panel LED";
			gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
		led-green {
			gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	miphy28lp_phy: miphy28lp {

		phy_port0: port@9b22000 {
			st,osc-rdy;
		};

		phy_port1: port@9b2a000 {
			st,osc-force-ext;
		};
	};

	soc {
		sbc_serial0: serial@9530000 {
			status = "okay";
		};

		i2c@9842000 {
			status = "okay";
		};

		i2c@9843000 {
			status = "okay";
		};

		i2c@9844000 {
			status = "okay";
		};

		i2c@9845000 {
			status = "okay";
		};

		i2c@9540000 {
			status = "okay";
		};

		/* SSC11 to HDMI */
		i2c@9541000 {
			status = "okay";
			/* HDMI V1.3a supports Standard mode only */
			clock-frequency = <100000>;
			st,i2c-min-scl-pulse-width-us = <0>;
			st,i2c-min-sda-pulse-width-us = <5>;
		};

		mmc1: sdhci@9080000 {
			status = "okay";
		};

		mmc0: sdhci@9060000 {
			status = "okay";
			max-frequency = <200000000>;
			sd-uhs-sdr50;
			sd-uhs-sdr104;
			sd-uhs-ddr50;
			non-removable;
		};

		st_dwc3: dwc3@8f94000 {
			status = "okay";
		};

		ethernet0: dwmac@9630000 {
			st,tx-retime-src = "clkgen";
			status = "okay";
			phy-mode = "rgmii";
			fixed-link = <0 1 1000 0 0>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2021 STMicroelectronics
 * Author: Alain Volmat <avolmat@me.com>
 */
/dts-v1/;
#include "stih418.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
	model = "STiH418 B2264";
	compatible = "st,stih418-b2264", "st,stih418";

	chosen {
		stdout-path = &sbc_serial0;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x40000000 0xc0000000>;
	};

	cpus {
		cpu@0 {
			operating-points-v2 = <&cpu_opp_table>;
			/* u-boot puts hpen in SBC dmem at 0xb8 offset */
			cpu-release-addr = <0x94100b8>;
		};
		cpu@1 {
			operating-points-v2 = <&cpu_opp_table>;
			/* u-boot puts hpen in SBC dmem at 0xb8 offset */
			cpu-release-addr = <0x94100b8>;
		};
		cpu@2 {
			operating-points-v2 = <&cpu_opp_table>;
			/* u-boot puts hpen in SBC dmem at 0xb8 offset */
			cpu-release-addr = <0x94100b8>;
		};
		cpu@3 {
			operating-points-v2 = <&cpu_opp_table>;
			/* u-boot puts hpen in SBC dmem at 0xb8 offset */
			cpu-release-addr = <0x94100b8>;
		};
	};

	cpu_opp_table: opp_table {
		compatible = "operating-points-v2";
		opp-shared;

		opp00 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <784000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <784000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <784000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <784000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1500000000>;
			opp-microvolt = <784000>;
		};
	};

	aliases {
		ttyAS0 = &sbc_serial0;
		ethernet0 = &ethernet0;
	};

	soc {
		leds {
			compatible = "gpio-leds";
			led-green {
				gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
				default-state = "off";
			};
		};

		pin-controller-sbc@961f080 {
			gmac1 {
				rgmii1-0 {
					st,pins {
						rxd0 = <&pio1 4 ALT1 IN DE_IO 300 CLK_A>;
						rxd1 = <&pio1 5 ALT1 IN DE_IO 300 CLK_A>;
						rxd2 = <&pio1 6 ALT1 IN DE_IO 300 CLK_A>;
						rxd3 = <&pio1 7 ALT1 IN DE_IO 300 CLK_A>;
						rxdv = <&pio2 0 ALT1 IN DE_IO 300 CLK_A>;
					};
				};
			};
		};

	};
};

&ehci0 {
	status = "okay";
};

&ethernet0 {
	phy-mode = "rgmii";
	pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>;
	st,tx-retime-src = "clkgen";

	snps,reset-gpio = <&pio0 7 0>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 1000000>;

	status = "okay";
};

&miphy28lp_phy {
	phy_port0: port@9b22000 {
		st,sata-gen = <2>; /* SATA GEN3 */
		st,osc-rdy;
	};
};

&mmc0 {
	status = "okay";
};

&ohci1 {
	status = "okay";
};

&pwm1 {
	status = "okay";
};

&sata0 {
	status = "okay";
};

&sbc_serial0 {
	status = "okay";
};

&spifsm {
	status = "okay";
};

&st_dwc3 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 STMicroelectronics R&D Limited
 */
#include <dt-bindings/clock/stih418-clks.h>
/ {
	/*
	 * Fixed 30MHz oscillator inputs to SoC
	 */
	clk_sysin: clk-sysin {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <30000000>;
		clock-output-names = "CLK_SYSIN";
	};

	clk_tmdsout_hdmi: clk-tmdsout-hdmi {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		compatible = "st,stih418-clk", "simple-bus";

		/*
		 * A9 PLL.
		 */
		clockgen-a9@92b0000 {
			compatible = "st,clkgen-c32";
			reg = <0x92b0000 0x10000>;

			clockgen_a9_pll: clockgen-a9-pll {
				#clock-cells = <1>;
				compatible = "st,stih418-clkgen-plla9";

				clocks = <&clk_sysin>;
			};

			/*
			 * ARM CPU related clocks.
			 */
			clk_m_a9: clk-m-a9 {
				#clock-cells = <0>;
				compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";

				clocks = <&clockgen_a9_pll 0>,
					 <&clockgen_a9_pll 0>,
					 <&clk_s_c0_flexgen 13>,
					 <&clk_m_a9_ext2f_div2>;

				/*
				 * ARM Peripheral clock for timers
				 */
				arm_periph_clk: clk-m-a9-periphs {
					#clock-cells = <0>;
					compatible = "fixed-factor-clock";
					clocks = <&clk_m_a9>;
					clock-div = <2>;
					clock-mult = <1>;
				};
			};
		};

		clockgen-a@90ff000 {
			compatible = "st,clkgen-c32";
			reg = <0x90ff000 0x1000>;

			clk_s_a0_pll: clk-s-a0-pll {
				#clock-cells = <1>;
				compatible = "st,clkgen-pll0-a0";

				clocks = <&clk_sysin>;
			};

			clk_s_a0_flexgen: clk-s-a0-flexgen {
				compatible = "st,flexgen", "st,flexgen-stih410-a0";

				#clock-cells = <1>;

				clocks = <&clk_s_a0_pll 0>,
					 <&clk_sysin>;
			};
		};

		clk_s_c0: clockgen-c@9103000 {
			compatible = "st,clkgen-c32";
			reg = <0x9103000 0x1000>;

			clk_s_c0_pll0: clk-s-c0-pll0 {
				#clock-cells = <1>;
				compatible = "st,clkgen-pll0-c0";

				clocks = <&clk_sysin>;
			};

			clk_s_c0_pll1: clk-s-c0-pll1 {
				#clock-cells = <1>;
				compatible = "st,clkgen-pll1-c0";

				clocks = <&clk_sysin>;
			};

			clk_s_c0_quadfs: clk-s-c0-quadfs {
				#clock-cells = <1>;
				compatible = "st,quadfs-pll";

				clocks = <&clk_sysin>;
			};

			clk_s_c0_flexgen: clk-s-c0-flexgen {
				#clock-cells = <1>;
				compatible = "st,flexgen", "st,flexgen-stih418-c0";

				clocks = <&clk_s_c0_pll0 0>,
					 <&clk_s_c0_pll1 0>,
					 <&clk_s_c0_quadfs 0>,
					 <&clk_s_c0_quadfs 1>,
					 <&clk_s_c0_quadfs 2>,
					 <&clk_s_c0_quadfs 3>,
					 <&clk_sysin>;

				/*
				 * ARM Peripheral clock for timers
				 */
				clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
					#clock-cells = <0>;
					compatible = "fixed-factor-clock";

					clocks = <&clk_s_c0_flexgen 13>;

					clock-output-names = "clk-m-a9-ext2f-div2";

					clock-div = <2>;
					clock-mult = <1>;
				};
			};
		};

		clockgen-d0@9104000 {
			compatible = "st,clkgen-c32";
			reg = <0x9104000 0x1000>;

			clk_s_d0_quadfs: clk-s-d0-quadfs {
				#clock-cells = <1>;
				compatible = "st,quadfs-d0";

				clocks = <&clk_sysin>;
			};

			clk_s_d0_flexgen: clk-s-d0-flexgen {
				#clock-cells = <1>;
				compatible = "st,flexgen", "st,flexgen-stih410-d0";

				clocks = <&clk_s_d0_quadfs 0>,
					 <&clk_s_d0_quadfs 1>,
					 <&clk_s_d0_quadfs 2>,
					 <&clk_s_d0_quadfs 3>,
					 <&clk_sysin>;
			};
		};

		clockgen-d2@9106000 {
			compatible = "st,clkgen-c32";
			reg = <0x9106000 0x1000>;

			clk_s_d2_quadfs: clk-s-d2-quadfs {
				#clock-cells = <1>;
				compatible = "st,quadfs-d2";

				clocks = <&clk_sysin>;
			};

			clk_s_d2_flexgen: clk-s-d2-flexgen {
				#clock-cells = <1>;
				compatible = "st,flexgen", "st,flexgen-stih418-d2";

				clocks = <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>,
					 <&clk_s_d2_quadfs 2>,
					 <&clk_s_d2_quadfs 3>,
					 <&clk_sysin>,
					 <&clk_sysin>,
					 <&clk_tmdsout_hdmi>;
			};
		};

		clockgen-d3@9107000 {
			compatible = "st,clkgen-c32";
			reg = <0x9107000 0x1000>;

			clk_s_d3_quadfs: clk-s-d3-quadfs {
				#clock-cells = <1>;
				compatible = "st,quadfs-d3";

				clocks = <&clk_sysin>;
			};

			clk_s_d3_flexgen: clk-s-d3-flexgen {
				#clock-cells = <1>;
				compatible = "st,flexgen", "st,flexgen-stih407-d3";

				clocks = <&clk_s_d3_quadfs 0>,
					 <&clk_s_d3_quadfs 1>,
					 <&clk_s_d3_quadfs 2>,
					 <&clk_s_d3_quadfs 3>,
					 <&clk_sysin>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 STMicroelectronics Limited.
 * Author: Peter Griffin <peter.griffin@linaro.org>
 */
#include "stih418-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
			cpu-release-addr = <0x94100A4>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			/* u-boot puts hpen in SBC dmem at 0xa4 offset */
			cpu-release-addr = <0x94100A4>;
		};
	};

	usb2_picophy1: phy2 {
		compatible = "st,stih407-usb2-phy";
		#phy-cells = <0>;
		st,syscfg = <&syscfg_core 0xf8 0xf4>;
		resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
			 <&picophyreset STIH407_PICOPHY0_RESET>;
		reset-names = "global", "port";
	};

	usb2_picophy2: phy3 {
		compatible = "st,stih407-usb2-phy";
		#phy-cells = <0>;
		st,syscfg = <&syscfg_core 0xfc 0xf4>;
		resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
			 <&picophyreset STIH407_PICOPHY1_RESET>;
		reset-names = "global", "port";
	};

	soc {
		rng11: rng@8a8a000 {
			status = "disabled";
		};

		ohci0: usb@9a03c00 {
			compatible = "st,st-ohci-300x";
			reg = <0x9a03c00 0x100>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy1>;
			phy-names = "usb";
		};

		ehci0: usb@9a03e00 {
			compatible = "st,st-ehci-300x";
			reg = <0x9a03e00 0x100>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy1>;
			phy-names = "usb";
		};

		ohci1: usb@9a83c00 {
			compatible = "st,st-ohci-300x";
			reg = <0x9a83c00 0x100>;
			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy2>;
			phy-names = "usb";
		};

		ehci1: usb@9a83e00 {
			compatible = "st,st-ehci-300x";
			reg = <0x9a83e00 0x100>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy2>;
			phy-names = "usb";
		};

		mmc0: sdhci@9060000 {
			assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
			assigned-clock-parents = <&clk_s_c0_pll1 0>;
			assigned-clock-rates = <200000000>;
		};

		thermal@91a0000 {
			compatible = "st,stih407-thermal";
			reg = <0x91a0000 0x28>;
			clock-names = "thermal";
			clocks = <&clk_sysin>;
			interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 */
#include <dt-bindings/clock/stih407-clks.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/c8sectpfe.h>
/ {
	leds {
		compatible = "gpio-leds";
		led-red {
			label = "Front Panel LED";
			gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
		led-green {
			gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	sound: sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "STI-B2120";
		status = "okay";
		#address-cells = <1>;
		#size-cells = <0>;

		simple-audio-card,dai-link@0 {
			reg = <0>;
			/* HDMI */
			format = "i2s";
			mclk-fs = <128>;
			cpu {
				sound-dai = <&sti_uni_player0>;
			};

			codec {
				sound-dai = <&sti_hdmi>;
			};
		};

		simple-audio-card,dai-link@1 {
			reg = <1>;
			/* DAC */
			format = "i2s";
			mclk-fs = <256>;
			frame-inversion;
			cpu {
				sound-dai = <&sti_uni_player2>;
			};

			codec {
				sound-dai = <&sti_sasg_codec 1>;
			};
		};

		simple-audio-card,dai-link@2 {
			reg = <2>;
			/* SPDIF */
			format = "left_j";
			mclk-fs = <128>;
			cpu {
				sound-dai = <&sti_uni_player3>;
			};

			codec {
				sound-dai = <&sti_sasg_codec 0>;
			};
		};
	};

	miphy28lp_phy: miphy28lp {

		phy_port0: port@9b22000 {
			st,osc-rdy;
		};

		phy_port1: port@9b2a000 {
			st,osc-force-ext;
		};
	};

	soc {
		sbc_serial0: serial@9530000 {
			status = "okay";
		};

		pwm0: pwm@9810000 {
			status = "okay";
		};

		pwm1: pwm@9510000 {
			status = "okay";
		};

		ssc2: i2c@9842000 {
			status = "okay";
			clock-frequency = <100000>;
			st,i2c-min-scl-pulse-width-us = <0>;
			st,i2c-min-sda-pulse-width-us = <5>;
		};

		ssc3: i2c@9843000 {
			status = "okay";
			clock-frequency = <100000>;
			st,i2c-min-scl-pulse-width-us = <0>;
			st,i2c-min-sda-pulse-width-us = <5>;
		};

		i2c@9844000 {
			status = "okay";
		};

		i2c@9845000 {
			status = "okay";
		};

		i2c@9540000 {
			status = "okay";
		};

		mmc0: sdhci@9060000 {
			non-removable;
			status = "okay";
		};

		mmc1: sdhci@9080000 {
			status = "okay";
		};

		/* SSC11 to HDMI */
		hdmiddc: i2c@9541000 {
			status = "okay";
			/* HDMI V1.3a supports Standard mode only */
			clock-frequency = <100000>;
			st,i2c-min-scl-pulse-width-us = <0>;
			st,i2c-min-sda-pulse-width-us = <5>;
		};

		st_dwc3: dwc3@8f94000 {
			status = "okay";
		};

		ethernet0: dwmac@9630000 {
			st,tx-retime-src = "clkgen";
			status = "okay";
			phy-mode = "rgmii";
			fixed-link = <0 1 1000 0 0>;
		};

		demux@8a20000 {
			compatible	= "st,stih407-c8sectpfe";
			status		= "okay";
			reg		= <0x08a20000 0x10000>,
					  <0x08a00000 0x4000>;
			reg-names	= "c8sectpfe", "c8sectpfe-ram";
			interrupts	= <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
					  <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names	= "c8sectpfe-error-irq",
					  "c8sectpfe-idle-irq";
			pinctrl-0	= <&pinctrl_tsin0_serial>;
			pinctrl-1	= <&pinctrl_tsin0_parallel>;
			pinctrl-2	= <&pinctrl_tsin3_serial>;
			pinctrl-3	= <&pinctrl_tsin4_serial_alt3>;
			pinctrl-4	= <&pinctrl_tsin5_serial_alt1>;
			pinctrl-names	= "tsin0-serial",
					  "tsin0-parallel",
					  "tsin3-serial",
					  "tsin4-serial",
					  "tsin5-serial";
			clocks		= <&clk_s_c0_flexgen CLK_PROC_STFE>;
			clock-names	= "c8sectpfe";

			/* tsin0 is TSA on NIMA */
			tsin0: port {
				tsin-num = <0>;
				serial-not-parallel;
				i2c-bus = <&ssc2>;
				reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>;
				dvb-card = <STV0367_TDA18212_NIMA_1>;
			};
		};

		sti_uni_player0: sti-uni-player@8d80000 {
			status = "okay";
		};

		sti_uni_player2: sti-uni-player@8d82000 {
			status = "okay";
		};

		sti_uni_player3: sti-uni-player@8d85000 {
			status = "okay";
		};

		syscfg_core: core-syscfg@92b0000 {
			sti_sasg_codec: sti-sasg-codec {
				status = "okay";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spdif_out>;
			};
		};
	};
};


code:
/*
 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 *     You should have received a copy of the GNU General Public
 *     License along with this file; if not, write to the Free
 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
 *     MA 02110-1301 USA
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "stm32f429.dtsi"
#include "stm32f429-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "STMicroelectronics STM32429i-EVAL board";
	compatible = "st,stm32429i-eval", "st,stm32f429";

	chosen {
		bootargs = "root=/dev/ram";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x2000000>;
	};

	aliases {
		serial0 = &usart1;
	};

	clocks {
		clk_ext_camera: clk-ext-camera {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};
	};

	soc {
		dma-ranges = <0xc0000000 0x0 0x10000000>;
	};

	vdda: regulator-vdda {
		compatible = "regulator-fixed";
		regulator-name = "vdda";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	vref: regulator-vref {
		compatible = "regulator-fixed";
		regulator-name = "vref";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	vdd_panel: vdd-panel {
		compatible = "regulator-fixed";
		regulator-name = "vdd_panel";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	leds {
		compatible = "gpio-leds";
		led-green {
			gpios = <&gpiog 6 1>;
			linux,default-trigger = "heartbeat";
		};
		led-orange {
			gpios = <&gpiog 7 1>;
		};
		led-red {
			gpios = <&gpiog 10 1>;
		};
		led-blue {
			gpios = <&gpiog 12 1>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		button-0 {
			label = "Wake up";
			linux,code = <KEY_WAKEUP>;
			gpios = <&gpioa 0 0>;
		};
		button-1 {
			label = "Tamper";
			linux,code = <KEY_RESTART>;
			gpios = <&gpioc 13 0>;
		};
	};

	usbotg_hs_phy: usbphy {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
		clock-names = "main_clk";
	};

	panel_rgb: panel-rgb {
		compatible = "ampire,am-480272h3tmqw-t01h";
		power-supply = <&vdd_panel>;
		status = "okay";
		port {
			panel_in_rgb: endpoint {
				remote-endpoint = <&ltdc_out_rgb>;
			};
		};
	};

	mmc_vcard: mmc_vcard {
		compatible = "regulator-fixed";
		regulator-name = "mmc_vcard";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&adc {
	pinctrl-names = "default";
	pinctrl-0 = <&adc3_in8_pin>;
	vdda-supply = <&vdda>;
	vref-supply = <&vref>;
	status = "okay";
	adc3: adc@200 {
		st,adc-channels = <8>;
		status = "okay";
	};
};

&clk_hse {
	clock-frequency = <25000000>;
};

&crc {
	status = "okay";
};

&dcmi {
	status = "okay";

	port {
		dcmi_0: endpoint {
			remote-endpoint = <&ov2640_0>;
			bus-type = <5>;
			bus-width = <8>;
			hsync-active = <0>;
			vsync-active = <0>;
			pclk-sample = <1>;
		};
	};
};

&i2c1 {
	pinctrl-0 = <&i2c1_pins>;
	pinctrl-names = "default";
	status = "okay";

	ov2640: camera@30 {
		compatible = "ovti,ov2640";
		reg = <0x30>;
		resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>;
		pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>;
		clocks = <&clk_ext_camera>;
		clock-names = "xvclk";
		status = "okay";

		port {
			ov2640_0: endpoint {
				remote-endpoint = <&dcmi_0>;
			};
		};
	};

	stmpe1600: stmpe1600@42 {
		compatible = "st,stmpe1600";
		reg = <0x42>;
		interrupts = <8 3>;
		interrupt-parent = <&gpioi>;
		interrupt-controller;
		wakeup-source;

		stmpegpio: stmpe_gpio {
			compatible = "st,stmpe-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};
	};
};

&iwdg {
	status = "okay";
	timeout-sec = <32>;
};

&ltdc {
	status = "okay";
	pinctrl-0 = <&ltdc_pins_a>;
	pinctrl-names = "default";

	port {
		ltdc_out_rgb: endpoint {
			remote-endpoint = <&panel_in_rgb>;
		};
	};
};

&mac {
	status = "okay";
	pinctrl-0 = <&ethernet_mii>;
	pinctrl-names = "default";
	phy-mode = "mii";
	phy-handle = <&phy1>;
	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy1: ethernet-phy@1 {
			reg = <1>;
		};
	};
};

&rtc {
	status = "okay";
};

&sdio {
	status = "okay";
	vmmc-supply = <&mmc_vcard>;
	cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default", "opendrain";
	pinctrl-0 = <&sdio_pins>;
	pinctrl-1 = <&sdio_pins_od>;
	bus-width = <4>;
	max-frequency = <12500000>;
};

&timers1 {
	status = "okay";

	pwm {
		pinctrl-0 = <&pwm1_pins>;
		pinctrl-names = "default";
		status = "okay";
	};

	timer@0 {
		status = "okay";
	};
};

&timers3 {
	status = "okay";

	pwm {
		pinctrl-0 = <&pwm3_pins>;
		pinctrl-names = "default";
		status = "okay";
	};

	timer@2 {
		status = "okay";
	};
};

&timers5 {
	/* Override timer5 to act as clockevent */
	compatible = "st,stm32-timer";
	interrupts = <50>;
	status = "okay";
	/delete-property/#address-cells;
	/delete-property/#size-cells;
	/delete-property/clock-names;
	/delete-node/pwm;
	/delete-node/timer@4;
};

&usart1 {
	pinctrl-0 = <&usart1_pins_a>;
	pinctrl-names = "default";
	status = "okay";
};

&usbotg_hs {
	dr_mode = "host";
	phys = <&usbotg_hs_phy>;
	phy-names = "usb2-phy";
	pinctrl-0 = <&usbotg_hs_pins_a>;
	pinctrl-names = "default";
	status = "okay";
};


code:
/*
 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;
#include "stm32f746.dtsi"
#include "stm32f746-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "STMicroelectronics STM32746g-EVAL board";
	compatible = "st,stm32746g-eval", "st,stm32f746";

	chosen {
		bootargs = "root=/dev/ram";
		stdout-path = "serial0:115200n8";
	};

	memory@c0000000 {
		device_type = "memory";
		reg = <0xc0000000 0x2000000>;
	};

	aliases {
		serial0 = &usart1;
	};

	leds {
		compatible = "gpio-leds";
		led-green {
			gpios = <&gpiof 10 1>;
			linux,default-trigger = "heartbeat";
		};
		led-orange {
			gpios = <&stmfx_pinctrl 17 1>;
		};
		led-red {
			gpios = <&gpiob 7 1>;
		};
		led-blue {
			gpios = <&stmfx_pinctrl 19 1>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		button-0 {
			label = "Wake up";
			linux,code = <KEY_WAKEUP>;
			gpios = <&gpioc 13 0>;
		};
	};

	joystick {
		compatible = "gpio-keys";
		pinctrl-0 = <&joystick_pins>;
		pinctrl-names = "default";
		button-0 {
			label = "JoySel";
			linux,code = <KEY_ENTER>;
			interrupt-parent = <&stmfx_pinctrl>;
			interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
		};
		button-1 {
			label = "JoyDown";
			linux,code = <KEY_DOWN>;
			interrupt-parent = <&stmfx_pinctrl>;
			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
		};
		button-2 {
			label = "JoyLeft";
			linux,code = <KEY_LEFT>;
			interrupt-parent = <&stmfx_pinctrl>;
			interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
		};
		button-3 {
			label = "JoyRight";
			linux,code = <KEY_RIGHT>;
			interrupt-parent = <&stmfx_pinctrl>;
			interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
		};
		button-4 {
			label = "JoyUp";
			linux,code = <KEY_UP>;
			interrupt-parent = <&stmfx_pinctrl>;
			interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
		};
	};

	usbotg_hs_phy: usb-phy {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
		clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
		clock-names = "main_clk";
	};

	mmc_vcard: mmc_vcard {
		compatible = "regulator-fixed";
		regulator-name = "mmc_vcard";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&clk_hse {
	clock-frequency = <25000000>;
};

&crc {
	status = "okay";
};

&i2c1 {
	pinctrl-0 = <&i2c1_pins_b>;
	pinctrl-names = "default";
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	status = "okay";

	stmfx: stmfx@42 {
		compatible = "st,stmfx-0300";
		reg = <0x42>;
		interrupts = <8 IRQ_TYPE_EDGE_RISING>;
		interrupt-parent = <&gpioi>;

		stmfx_pinctrl: pinctrl {
			compatible = "st,stmfx-0300-pinctrl";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&stmfx_pinctrl 0 0 24>;

			joystick_pins: joystick {
				pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
				drive-push-pull;
				bias-pull-up;
			};
		};
	};
};

&rtc {
	status = "okay";
};

&sdio1 {
	status = "okay";
	vmmc-supply = <&mmc_vcard>;
	broken-cd;
	pinctrl-names = "default", "opendrain";
	pinctrl-0 = <&sdio_pins_a>;
	pinctrl-1 = <&sdio_pins_od_a>;
	bus-width = <4>;
};

&timers5 {
	/* Override timer5 to act as clockevent */
	compatible = "st,stm32-timer";
	interrupts = <50>;
	status = "okay";
	/delete-property/#address-cells;
	/delete-property/#size-cells;
	/delete-property/clock-names;
	/delete-node/pwm;
	/delete-node/timer@4;
};

&usart1 {
	pinctrl-0 = <&usart1_pins_a>;
	pinctrl-names = "default";
	status = "okay";
};

&usbotg_hs {
	dr_mode = "otg";
	phys = <&usbotg_hs_phy>;
	phy-names = "usb2-phy";
	pinctrl-0 = <&usbotg_hs_pins_a>;
	pinctrl-names = "default";
	status = "okay";
};


code:
/*
 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/mfd/stm32f4-rcc.h>

/ {
	soc {
		pinctrl: pinctrl@40020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x40020000 0x3000>;
			interrupt-parent = <&exti>;
			st,syscfg = <&syscfg 0x8>;
			pins-are-numbered;

			gpioa: gpio@40020000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x0 0x400>;
				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
				st,bank-name = "GPIOA";
			};

			gpiob: gpio@40020400 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x400 0x400>;
				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
				st,bank-name = "GPIOB";
			};

			gpioc: gpio@40020800 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x800 0x400>;
				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
				st,bank-name = "GPIOC";
			};

			gpiod: gpio@40020c00 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0xc00 0x400>;
				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
				st,bank-name = "GPIOD";
			};

			gpioe: gpio@40021000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1000 0x400>;
				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
				st,bank-name = "GPIOE";
			};

			gpiof: gpio@40021400 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1400 0x400>;
				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
				st,bank-name = "GPIOF";
			};

			gpiog: gpio@40021800 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1800 0x400>;
				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
				st,bank-name = "GPIOG";
			};

			gpioh: gpio@40021c00 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1c00 0x400>;
				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
				st,bank-name = "GPIOH";
			};

			gpioi: gpio@40022000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2000 0x400>;
				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
				st,bank-name = "GPIOI";
			};

			gpioj: gpio@40022400 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2400 0x400>;
				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
				st,bank-name = "GPIOJ";
			};

			gpiok: gpio@40022800 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2800 0x400>;
				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
				st,bank-name = "GPIOK";
			};

			usart1_pins_a: usart1-0 {
				pins1 {
					pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
					bias-disable;
					drive-push-pull;
					slew-rate = <0>;
				};
				pins2 {
					pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
					bias-disable;
				};
			};

			usart3_pins_a: usart3-0 {
				pins1 {
					pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
					bias-disable;
					drive-push-pull;
					slew-rate = <0>;
				};
				pins2 {
					pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
					bias-disable;
				};
			};

			usbotg_fs_pins_a: usbotg-fs-0 {
				pins {
					pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
						 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
						 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
					bias-disable;
					drive-push-pull;
					slew-rate = <2>;
				};
			};

			usbotg_fs_pins_b: usbotg-fs-1 {
				pins {
					pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
						 <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
						 <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
					bias-disable;
					drive-push-pull;
					slew-rate = <2>;
				};
			};

			usbotg_hs_pins_a: usbotg-hs-0 {
				pins {
					pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
						 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
						 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
						 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
						 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
						 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
						 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
						 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
						 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
						 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
						 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
						 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
					bias-disable;
					drive-push-pull;
					slew-rate = <2>;
				};
			};

			ethernet_mii: mii-0 {
				pins {
					pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
						 <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
						 <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
						 <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
						 <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
						 <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
						 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
						 <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
						 <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
						 <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
						 <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
						 <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
						 <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
						 <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
					slew-rate = <2>;
				};
			};

			adc3_in8_pin: adc-200 {
				pins {
					pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
				};
			};

			pwm1_pins: pwm1-0 {
				pins {
					pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
						 <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
						 <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
				};
			};

			pwm3_pins: pwm3-0 {
				pins {
					pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
						 <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
				};
			};

			i2c1_pins: i2c1-0 {
				pins {
					pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
						 <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
					bias-disable;
					drive-open-drain;
					slew-rate = <3>;
				};
			};

			ltdc_pins_a: ltdc-0 {
				pins {
					pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
						 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
						 <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
						 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
						 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
						 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
						 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
						 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
						 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
						 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
						 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
						 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
						 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
						 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
						 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
						 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
						 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
						 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
						 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
						 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
						 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
						 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
						 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
						 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
						 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
						 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
						 <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
						 <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
					slew-rate = <2>;
				};
			};

			ltdc_pins_b: ltdc-1 {
				pins {
					pinmux = <STM32_PINMUX('C', 6,  AF14)>,
						/* LCD_HSYNC */
						 <STM32_PINMUX('A', 4,  AF14)>,
						 /* LCD_VSYNC */
						 <STM32_PINMUX('G', 7,  AF14)>,
						 /* LCD_CLK */
						 <STM32_PINMUX('C', 10, AF14)>,
						 /* LCD_R2 */
						 <STM32_PINMUX('B', 0,  AF9)>,
						 /* LCD_R3 */
						 <STM32_PINMUX('A', 11, AF14)>,
						 /* LCD_R4 */
						 <STM32_PINMUX('A', 12, AF14)>,
						 /* LCD_R5 */
						 <STM32_PINMUX('B', 1,  AF9)>,
						 /* LCD_R6*/
						 <STM32_PINMUX('G', 6,  AF14)>,
						 /* LCD_R7 */
						 <STM32_PINMUX('A', 6,  AF14)>,
						 /* LCD_G2 */
						 <STM32_PINMUX('G', 10, AF9)>,
						 /* LCD_G3 */
						 <STM32_PINMUX('B', 10, AF14)>,
						 /* LCD_G4 */
						 <STM32_PINMUX('D', 6,  AF14)>,
						 /* LCD_B2 */
						 <STM32_PINMUX('G', 11, AF14)>,
						 /* LCD_B3*/
						 <STM32_PINMUX('B', 11, AF14)>,
						 /* LCD_G5 */
						 <STM32_PINMUX('C', 7,  AF14)>,
						 /* LCD_G6 */
						 <STM32_PINMUX('D', 3,  AF14)>,
						 /* LCD_G7 */
						 <STM32_PINMUX('G', 12, AF9)>,
						 /* LCD_B4 */
						 <STM32_PINMUX('A', 3,  AF14)>,
						 /* LCD_B5 */
						 <STM32_PINMUX('B', 8,  AF14)>,
						 /* LCD_B6 */
						 <STM32_PINMUX('B', 9,  AF14)>,
						 /* LCD_B7 */
						 <STM32_PINMUX('F', 10, AF14)>;
						 /* LCD_DE */
					slew-rate = <2>;
				};
			};

			spi5_pins: spi5-0 {
				pins1 {
					pinmux = <STM32_PINMUX('F', 7, AF5)>,
						/* SPI5_CLK */
						 <STM32_PINMUX('F', 9, AF5)>;
						/* SPI5_MOSI */
					bias-disable;
					drive-push-pull;
					slew-rate = <0>;
				};
				pins2 {
					pinmux = <STM32_PINMUX('F', 8, AF5)>;
						/* SPI5_MISO */
					bias-disable;
				};
			};

			i2c3_pins: i2c3-0 {
				pins {
					pinmux = <STM32_PINMUX('C', 9, AF4)>,
						/* I2C3_SDA */
						 <STM32_PINMUX('A', 8, AF4)>;
						/* I2C3_SCL */
					bias-disable;
					drive-open-drain;
					slew-rate = <3>;
				};
			};

			dcmi_pins: dcmi-0 {
				pins {
					pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
						 <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
						 <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
						 <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
						 <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
						 <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
						 <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
						 <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
						 <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
						 <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
						 <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
						 <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
						 <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
						 <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
						 <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
					bias-disable;
					drive-push-pull;
					slew-rate = <3>;
				};
			};

			sdio_pins: sdio-pins-0 {
				pins {
					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
						 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
						 <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
						 <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
						 <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
						 <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
					drive-push-pull;
					slew-rate = <2>;
				};
			};

			sdio_pins_od: sdio-pins-od-0 {
				pins1 {
					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
						 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
						 <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
						 <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
						 <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
					drive-push-pull;
					slew-rate = <2>;
				};

				pins2 {
					pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
					drive-open-drain;
					slew-rate = <2>;
				};
			};
		};
	};
};