code:
/*
 * Copyright 2014 Linaro Ltd
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "ARM RealView PB1176";
	compatible = "arm,realview-pb1176";

	chosen { };

	aliases {
		serial0 = &pb1176_serial0;
		serial1 = &pb1176_serial1;
		serial2 = &pb1176_serial2;
		serial3 = &pb1176_serial3;
		serial4 = &fpga_serial;
	};

	memory {
		device_type = "memory";
		/* 128 MiB memory @ 0x0 */
		reg = <0x00000000 0x08000000>;
	};

	/* The voltage to the MMC card is hardwired at 3.3V */
	vmmc: regulator-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "vmmc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
        };

	veth: regulator-veth {
		compatible = "regulator-fixed";
		regulator-name = "veth";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
	};

	xtal24mhz: xtal24mhz@24M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
	};

	timclk: timclk@1M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <24>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	mclk: mclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	kmiclk: kmiclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	sspclk: sspclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	uartclk: uartclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	/* FIXME: this actually hangs off the PLL clocks */
	pclk: pclk@0 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	flash@30000000 {
		compatible = "arm,versatile-flash", "cfi-flash";
		reg = <0x30000000 0x4000000>;
		bank-width = <4>;
		partitions {
			compatible = "arm,arm-firmware-suite";
		};
	};

	fpga_flash@38000000 {
		compatible = "arm,versatile-flash", "cfi-flash";
		reg = <0x38000000 0x800000>;
		bank-width = <4>;
		partitions {
			compatible = "arm,arm-firmware-suite";
		};
	};

	/*
	 * The "secure flash" contains things like the boot
	 * monitor so we don't want people to accidentally
	 * screw this up. Mark the device tree node disabled
	 * by default.
	 */
	secflash@3c000000 {
		compatible = "arm,versatile-flash", "cfi-flash";
		reg = <0x3c000000 0x4000000>;
		bank-width = <4>;
		status = "disabled";
	};

	/* SMSC 9118 ethernet with PHY and EEPROM */
	ethernet@3a000000 {
		compatible = "smsc,lan9118", "smsc,lan9115";
		reg = <0x3a000000 0x10000>;
		interrupt-parent = <&intc_fpga1176>;
		interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
		phy-mode = "mii";
		reg-io-width = <4>;
		smsc,irq-active-high;
		smsc,irq-push-pull;
		vdd33a-supply = <&veth>;
		vddvario-supply = <&veth>;
	};

	usb@3b000000 {
		compatible = "nxp,usb-isp1761";
		reg = <0x3b000000 0x20000>;
		interrupt-parent = <&intc_fpga1176>;
		interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
		dr_mode = "peripheral";
	};

	bridge {
		compatible = "ti,ths8134a", "ti,ths8134";
		#address-cells = <1>;
		#size-cells = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				vga_bridge_in: endpoint {
					remote-endpoint = <&clcd_pads>;
				};
			};

			port@1 {
				reg = <1>;

				vga_bridge_out: endpoint {
					remote-endpoint = <&vga_con_in>;
				};
			};
		};
	};

	vga {
		compatible = "vga-connector";

		port {
			vga_con_in: endpoint {
				remote-endpoint = <&vga_bridge_out>;
			};
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,realview-pb1176-soc", "simple-bus";
		regmap = <&syscon>;
		ranges;

		syscon: syscon@10000000 {
			compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
			reg = <0x10000000 0x1000>;
			ranges = <0x0 0x10000000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			led@8,0 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x01>;
				label = "versatile:0";
				linux,default-trigger = "heartbeat";
				default-state = "on";
			};
			led@8,1 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x02>;
				label = "versatile:1";
				linux,default-trigger = "mmc0";
				default-state = "off";
			};
			led@8,2 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x04>;
				label = "versatile:2";
				linux,default-trigger = "cpu0";
				default-state = "off";
			};
			led@8,3 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x08>;
				label = "versatile:3";
				default-state = "off";
			};
			led@8,4 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x10>;
				label = "versatile:4";
				default-state = "off";
			};
			led@8,5 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x20>;
				label = "versatile:5";
				default-state = "off";
			};
			led@8,6 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x40>;
				label = "versatile:6";
				default-state = "off";
			};
			led@8,7 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x80>;
				label = "versatile:7";
				default-state = "off";
			};
			oscclk0: clock-controller@c {
				compatible = "arm,syscon-icst307";
				reg = <0x0c 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x0C>;
				clocks = <&xtal24mhz>;
			};
			oscclk1: clock-controller@10 {
				compatible = "arm,syscon-icst307";
				reg = <0x10 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x10>;
				clocks = <&xtal24mhz>;
			};
			oscclk2: clock-controller@14 {
				compatible = "arm,syscon-icst307";
				reg = <0x14 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x14>;
				clocks = <&xtal24mhz>;
			};
			oscclk3: clock-controller@18 {
				compatible = "arm,syscon-icst307";
				reg = <0x18 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x18>;
				clocks = <&xtal24mhz>;
			};
			oscclk4: clock-controller@1c {
				compatible = "arm,syscon-icst307";
				reg = <0x1c 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x1c>;
				clocks = <&xtal24mhz>;
			};
		};

		/* Primary DevChip GIC synthesized with the CPU */
		intc_dc1176: interrupt-controller@10120000 {
			compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			interrupt-controller;
			reg = <0x10121000 0x1000>,
			      <0x10120000 0x100>;
		};

		L2: cache-controller {
			compatible = "arm,l220-cache";
			reg = <0x10110000 0x1000>;
			interrupt-parent = <&intc_dc1176>;
			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-level = <2>;
			/*
			 * Override default cache size, sets and
			 * associativity as these may be erroneously set
			 * up by boot loader(s).
			 */
			arm,override-auxreg;
			cache-size = <131072>; // 128kB
			cache-sets = <512>;
			cache-line-size = <32>;
		};

		pmu {
			compatible = "arm,arm1176-pmu";
			interrupt-parent = <&intc_dc1176>;
			interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
		};

		timer01: timer@10104000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x10104000 0x1000>;
			interrupt-parent = <&intc_dc1176>;
			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&timclk>, <&timclk>, <&pclk>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		timer23: timer@10105000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x10105000 0x1000>;
			interrupt-parent = <&intc_dc1176>;
			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
			arm,sp804-has-irq = <1>;
			clocks = <&timclk>, <&timclk>, <&pclk>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		pb1176_rtc: rtc@10108000 {
			compatible = "arm,pl031", "arm,primecell";
			reg = <0x10108000 0x1000>;
			interrupt-parent = <&intc_dc1176>;
			interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		pb1176_gpio0: gpio@1010a000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x1010a000 0x1000>;
			gpio-controller;
			interrupt-parent = <&intc_dc1176>;
			interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		pb1176_ssp: spi@1010b000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x1010b000 0x1000>;
			interrupt-parent = <&intc_dc1176>;
			interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sspclk>, <&pclk>;
			clock-names = "sspclk", "apb_pclk";
		};

		pb1176_serial0: serial@1010c000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x1010c000 0x1000>;
			interrupt-parent = <&intc_dc1176>;
			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		pb1176_serial1: serial@1010d000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x1010d000 0x1000>;
			interrupt-parent = <&intc_dc1176>;
			interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		pb1176_serial2: serial@1010e000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x1010e000 0x1000>;
			interrupt-parent = <&intc_dc1176>;
			interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		pb1176_serial3: serial@1010f000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x1010f000 0x1000>;
			interrupt-parent = <&intc_dc1176>;
			interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		/* Direct-mapped development chip ROM */
		pb1176_rom@10200000 {
			compatible = "direct-mapped";
			reg = <0x10200000 0x4000>;
			bank-width = <1>;
		};

		clcd@10112000 {
			compatible = "arm,pl111", "arm,primecell";
			reg = <0x10112000 0x1000>;
			interrupt-parent = <&intc_dc1176>;
			interrupt-names = "combined";
			interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&oscclk0>, <&pclk>;
			clock-names = "clcdclk", "apb_pclk";
			/* 1024x768 16bpp @65MHz works fine */
			max-memory-bandwidth = <95000000>;

			port {
				clcd_pads: endpoint {
					remote-endpoint = <&vga_bridge_in>;
					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
				};
			};
		};
	};

	/* These peripherals are inside the FPGA rather than the DevChip */
	fpga {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		i2c0: i2c@10002000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "arm,versatile-i2c";
			reg = <0x10002000 0x1000>;

			rtc@68 {
				compatible = "dallas,ds1338";
				reg = <0x68>;
			};
		};

		fpga_aaci: aaci@10004000 {
			compatible = "arm,pl041", "arm,primecell";
			reg = <0x10004000 0x1000>;
			interrupt-parent = <&intc_fpga1176>;
			interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		fpga_mci: mmcsd@10005000 {
			compatible = "arm,pl18x", "arm,primecell";
			reg = <0x10005000 0x1000>;
			interrupt-parent = <&intc_fpga1176>;
			interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
					<0 2 IRQ_TYPE_LEVEL_HIGH>;
			/* Due to frequent FIFO overruns, use just 500 kHz */
			max-frequency = <500000>;
			bus-width = <4>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			clocks = <&mclk>, <&pclk>;
			clock-names = "mclk", "apb_pclk";
			vmmc-supply = <&vmmc>;
			cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
			wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
		};

		fpga_kmi0: kmi@10006000 {
			compatible = "arm,pl050", "arm,primecell";
			reg = <0x10006000 0x1000>;
			interrupt-parent = <&intc_fpga1176>;
			interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&kmiclk>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};

		fpga_kmi1: kmi@10007000 {
			compatible = "arm,pl050", "arm,primecell";
			reg = <0x10007000 0x1000>;
			interrupt-parent = <&intc_fpga1176>;
			interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&kmiclk>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};

		fpga_charlcd: charlcd@10008000 {
			compatible = "arm,versatile-lcd";
			reg = <0x10008000 0x1000>;
			interrupt-parent = <&intc_fpga1176>;
			interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		fpga_serial: serial@10009000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x10009000 0x1000>;
			interrupt-parent = <&intc_fpga1176>;
			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		/* This GIC on the board is cascaded off the DevChip GIC */
		intc_fpga1176: interrupt-controller@10040000 {
			compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			interrupt-controller;
			reg = <0x10041000 0x1000>,
			      <0x10040000 0x100>;
			interrupt-parent = <&intc_dc1176>;
			interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
		};

		fpga_gpio0: gpio@10014000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x10014000 0x1000>;
			gpio-controller;
			interrupt-parent = <&intc_fpga1176>;
			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		fpga_gpio1: gpio@10015000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x10015000 0x1000>;
			gpio-controller;
			interrupt-parent = <&intc_fpga1176>;
			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		fpga_rtc: rtc@10017000 {
			compatible = "arm,pl031", "arm,primecell";
			reg = <0x10017000 0x1000>;
			interrupt-parent = <&intc_fpga1176>;
			interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};
	};
};


code:
/*
 * Copyright 2015 Linaro Ltd
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "ARM RealView PB11MPcore";
	compatible = "arm,realview-pb11mp";

	chosen { };

	aliases {
		serial0 = &pb11mp_serial0;
		serial1 = &pb11mp_serial1;
		serial2 = &pb11mp_serial2;
		serial3 = &pb11mp_serial3;
	};

	memory {
		device_type = "memory";
		/*
		 * The PB11MPCore has 512 MiB memory @ 0x70000000
		 * and the first 256 are also remapped @ 0x00000000
		 */
		reg = <0x70000000 0x20000000>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "arm,realview-smp";

		MP11_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,arm11mpcore";
			reg = <0>;
			next-level-cache = <&L2>;
		};

		MP11_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,arm11mpcore";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		MP11_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,arm11mpcore";
			reg = <2>;
			next-level-cache = <&L2>;
		};

		MP11_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,arm11mpcore";
			reg = <3>;
			next-level-cache = <&L2>;
		};
	};

	/* Primary TestChip GIC synthesized with the CPU */
	intc_tc11mp: interrupt-controller@1f000100 {
		compatible = "arm,tc11mp-gic";
		#interrupt-cells = <3>;
		#address-cells = <1>;
		interrupt-controller;
		reg = <0x1f001000 0x1000>,
		      <0x1f000100 0x100>;
	};

	L2: cache-controller {
		compatible = "arm,l220-cache";
		reg = <0x1f002000 0x1000>;
		interrupt-parent = <&intc_tc11mp>;
		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
			     <0 30 IRQ_TYPE_LEVEL_HIGH>,
			     <0 31 IRQ_TYPE_LEVEL_HIGH>;
		cache-unified;
		cache-level = <2>;
		/*
		 * Override default cache size, sets and
		 * associativity as these may be erroneously set
		 * up by boot loader(s), probably for safety
		 * since th outer sync operation can cause the
		 * cache to hang unless disabled.
		 */
		cache-size = <1048576>; // 1MB
		cache-sets = <4096>;
		cache-line-size = <32>;
		arm,shared-override;
		arm,parity-enable;
		arm,outer-sync-disable;
	};

	scu@1f000000 {
		compatible = "arm,arm11mp-scu";
		reg = <0x1f000000 0x100>;
	};

	timer@1f000600 {
		compatible = "arm,arm11mp-twd-timer";
		reg = <0x1f000600 0x20>;
		interrupt-parent = <&intc_tc11mp>;
		interrupts = <1 13 0xf04>;
	};

	watchdog@1f000620 {
		compatible = "arm,arm11mp-twd-wdt";
		reg = <0x1f000620 0x20>;
		interrupt-parent = <&intc_tc11mp>;
		interrupts = <1 14 0xf04>;
	};

	/* PMU with one IRQ line per core */
	pmu {
		compatible = "arm,arm11mpcore-pmu";
		interrupt-parent = <&intc_tc11mp>;
		interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
			     <0 18 IRQ_TYPE_LEVEL_HIGH>,
			     <0 19 IRQ_TYPE_LEVEL_HIGH>,
			     <0 20 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
	};

	/* The voltage to the MMC card is hardwired at 3.3V */
	vmmc: regulator-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "vmmc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
        };

	veth: regulator-veth {
		compatible = "regulator-fixed";
		regulator-name = "veth";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
	};

	xtal24mhz: xtal24mhz@24M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
	};

	refclk32khz: refclk32khz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
	};

	timclk: timclk@1M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <24>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	mclk: mclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	kmiclk: kmiclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	sspclk: sspclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	uartclk: uartclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	wdogclk: wdogclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	/* FIXME: this actually hangs off the PLL clocks */
	pclk: pclk@0 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	flash0@40000000 {
		/* 2 * 32MiB NOR Flash memory */
		compatible = "arm,versatile-flash", "cfi-flash";
		reg = <0x40000000 0x04000000>;
		bank-width = <4>;
		partitions {
			compatible = "arm,arm-firmware-suite";
		};
	};

	flash1@44000000 {
		// 2 * 32MiB NOR Flash memory
		compatible = "arm,versatile-flash", "cfi-flash";
		reg = <0x44000000 0x04000000>;
		bank-width = <4>;
		partitions {
			compatible = "arm,arm-firmware-suite";
		};
	};

	bridge {
		compatible = "ti,ths8134a", "ti,ths8134";
		#address-cells = <1>;
		#size-cells = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				vga_bridge_in: endpoint {
					remote-endpoint = <&clcd_pads>;
				};
			};

			port@1 {
				reg = <1>;

				vga_bridge_out: endpoint {
					remote-endpoint = <&vga_con_in>;
				};
			};
		};
	};

	vga {
		/*
		 * This DDC I2C is connected directly to the DVI portions
		 * of the connector, so it's not really working when the
		 * monitor is connected to the VGA connector.
		 */
		compatible = "vga-connector";
		ddc-i2c-bus = <&i2c1>;

		port {
			vga_con_in: endpoint {
				remote-endpoint = <&vga_bridge_out>;
			};
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,realview-pb11mp-soc", "simple-bus";
		regmap = <&pb11mp_syscon>;
		ranges;

		pb11mp_syscon: syscon@10000000 {
			compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
			reg = <0x10000000 0x1000>;
			ranges = <0x0 0x10000000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			led@8,0 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x01>;
				label = "versatile:0";
				linux,default-trigger = "heartbeat";
				default-state = "on";
			};
			led@8,1 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x02>;
				label = "versatile:1";
				linux,default-trigger = "mmc0";
				default-state = "off";
			};
			led@8,2 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x04>;
				label = "versatile:2";
				linux,default-trigger = "cpu0";
				default-state = "off";
			};
			led@8,3 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x08>;
				label = "versatile:3";
				linux,default-trigger = "cpu1";
				default-state = "off";
			};
			led@8,4 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x10>;
				label = "versatile:4";
				linux,default-trigger = "cpu2";
				default-state = "off";
			};
			led@8,5 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x20>;
				label = "versatile:5";
				linux,default-trigger = "cpu3";
				default-state = "off";
			};
			led@8,6 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x40>;
				label = "versatile:6";
				default-state = "off";
			};
			led@8,7 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x80>;
				label = "versatile:7";
				default-state = "off";
			};

			oscclk0: clock-controller@c {
				compatible = "arm,syscon-icst307";
				reg = <0x0c 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x0C>;
				clocks = <&xtal24mhz>;
			};
			oscclk1: clock-controller@10 {
				compatible = "arm,syscon-icst307";
				reg = <0x10 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x10>;
				clocks = <&xtal24mhz>;
			};
			oscclk2: clock-controller@14 {
				compatible = "arm,syscon-icst307";
				reg = <0x14 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x14>;
				clocks = <&xtal24mhz>;
			};
			oscclk3: clock-controller@18 {
				compatible = "arm,syscon-icst307";
				reg = <0x18 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x18>;
				clocks = <&xtal24mhz>;
			};
			oscclk4: clock-controller@1c {
				compatible = "arm,syscon-icst307";
				reg = <0x1c 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x1c>;
				clocks = <&xtal24mhz>;
			};
			oscclk5: clock-controller@d4 {
				compatible = "arm,syscon-icst307";
				reg = <0xd4 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0xd4>;
				clocks = <&xtal24mhz>;
			};
			oscclk6: clock-controller@d8 {
				compatible = "arm,syscon-icst307";
				reg = <0xd8 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0xd8>;
				clocks = <&xtal24mhz>;
			};
		};

		sp810_syscon: sysctl@10001000 {
			compatible = "arm,sp810", "arm,primecell";
			reg = <0x10001000 0x1000>;
			clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
			clock-names = "refclk", "timclk", "apb_pclk";
			#clock-cells = <1>;
			clock-output-names = "timerclk0",
					     "timerclk1",
					     "timerclk2",
					     "timerclk3";
			assigned-clocks = <&sp810_syscon 0>,
					  <&sp810_syscon 1>,
					  <&sp810_syscon 2>,
					  <&sp810_syscon 3>;
			assigned-clock-parents = <&timclk>,
					       <&timclk>,
					       <&timclk>,
					       <&timclk>;
		};

		i2c0: i2c@10002000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "arm,versatile-i2c";
			reg = <0x10002000 0x1000>;

			rtc@68 {
				compatible = "dallas,ds1338";
				reg = <0x68>;
			};
		};

		aaci: aaci@10004000 {
			compatible = "arm,pl041", "arm,primecell";
			reg = <0x10004000 0x1000>;
			interrupt-parent = <&intc_tc11mp>;
			interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		mci: mmcsd@10005000 {
			compatible = "arm,pl18x", "arm,primecell";
			reg = <0x10005000 0x1000>;
			interrupt-parent = <&intc_tc11mp>;
			interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
					<0 15 IRQ_TYPE_LEVEL_HIGH>;
			/* Due to frequent FIFO overruns, use just 500 kHz */
			max-frequency = <500000>;
			bus-width = <4>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			clocks = <&mclk>, <&pclk>;
			clock-names = "mclk", "apb_pclk";
			vmmc-supply = <&vmmc>;
			cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
			wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
		};

		kmi0: kmi@10006000 {
			compatible = "arm,pl050", "arm,primecell";
			reg = <0x10006000 0x1000>;
			interrupt-parent = <&intc_tc11mp>;
			interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&kmiclk>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};

		kmi1: kmi@10007000 {
			compatible = "arm,pl050", "arm,primecell";
			reg = <0x10007000 0x1000>;
			interrupt-parent = <&intc_tc11mp>;
			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&kmiclk>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};

		pb11mp_serial0: serial@10009000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x10009000 0x1000>;
			interrupt-parent = <&intc_tc11mp>;
			interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		pb11mp_serial1: serial@1000a000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x1000a000 0x1000>;
			interrupt-parent = <&intc_tc11mp>;
			interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		pb11mp_serial2: serial@1000b000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x1000b000 0x1000>;
			interrupt-parent = <&intc_pb11mp>;
			interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		pb11mp_serial3: serial@1000c000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x1000c000 0x1000>;
			interrupt-parent = <&intc_pb11mp>;
			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		spi@1000d000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x1000d000 0x1000>;
			interrupt-parent = <&intc_pb11mp>;
			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sspclk>, <&pclk>;
			clock-names = "sspclk", "apb_pclk";
		};

		watchdog@1000f000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x1000f000 0x1000>;
			interrupt-parent = <&intc_pb11mp>;
			interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&wdogclk>, <&pclk>;
			clock-names = "wdog_clk", "apb_pclk";
			status = "disabled";
		};

		watchdog@10010000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x10010000 0x1000>;
			interrupt-parent = <&intc_pb11mp>;
			interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&wdogclk>, <&pclk>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		timer01: timer@10011000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x10011000 0x1000>;
			interrupt-parent = <&intc_tc11mp>;
			interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
			arm,sp804-has-irq = <1>;
			clocks = <&sp810_syscon 0>,
			         <&sp810_syscon 1>,
				 <&pclk>;
			clock-names = "timer0clk",
				    "timer1clk",
				    "apb_pclk";
		};

		timer23: timer@10012000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x10012000 0x1000>;
			interrupt-parent = <&intc_tc11mp>;
			interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
			arm,sp804-has-irq = <1>;
			clocks = <&sp810_syscon 2>,
			         <&sp810_syscon 3>,
				 <&pclk>;
			clock-names = "timer0clk",
				    "timer1clk",
				    "apb_pclk";
		};

		gpio0: gpio@10013000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x10013000 0x1000>;
			gpio-controller;
			interrupt-parent = <&intc_pb11mp>;
			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		gpio1: gpio@10014000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x10014000 0x1000>;
			gpio-controller;
			interrupt-parent = <&intc_pb11mp>;
			interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		gpio2: gpio@10015000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x10015000 0x1000>;
			gpio-controller;
			interrupt-parent = <&intc_pb11mp>;
			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		i2c1: i2c@10016000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "arm,versatile-i2c";
			reg = <0x10016000 0x1000>;
		};

		rtc: rtc@10017000 {
			compatible = "arm,pl031", "arm,primecell";
			reg = <0x10017000 0x1000>;
			interrupt-parent = <&intc_tc11mp>;
			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		timer45: timer@10018000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x10018000 0x1000>;
			clocks = <&timclk>, <&timclk>, <&pclk>;
			clock-names = "timer0clk", "timer1clk", "apb_pclk";
			status = "disabled";
		};

		timer67: timer@10019000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x10019000 0x1000>;
			clocks = <&timclk>, <&timclk>, <&pclk>;
			clock-names = "timer0clk", "timer1clk", "apb_pclk";
			status = "disabled";
		};

		clcd@10020000 {
			compatible = "arm,pl111", "arm,primecell";
			reg = <0x10020000 0x1000>;
			interrupt-parent = <&intc_pb11mp>;
			interrupt-names = "combined";
			interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&oscclk4>, <&pclk>;
			clock-names = "clcdclk", "apb_pclk";
			/* 1024x768 16bpp @65MHz works fine */
			max-memory-bandwidth = <95000000>;

			port {
				clcd_pads: endpoint {
					remote-endpoint = <&vga_bridge_in>;
					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
				};
			};
		};

		/*
		 * This GIC on the Platform Baseboard is cascaded off the
		 * TestChip GIC
		 */
		intc_pb11mp: interrupt-controller@1e000000 {
			compatible = "arm,arm11mp-gic";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			interrupt-controller;
			reg = <0x1e001000 0x1000>,
			      <0x1e000000 0x100>;
			interrupt-parent = <&intc_tc11mp>;
			interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
		};

		/* SMSC 9118 ethernet with PHY and EEPROM */
		ethernet@4e000000 {
			compatible = "smsc,lan9118", "smsc,lan9115";
			reg = <0x4e000000 0x10000>;
			interrupt-parent = <&intc_tc11mp>;
			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
			phy-mode = "mii";
			reg-io-width = <4>;
			smsc,irq-active-high;
			smsc,irq-push-pull;
			vdd33a-supply = <&veth>;
			vddvario-supply = <&veth>;
		};

		usb@4f000000 {
			compatible = "nxp,usb-isp1761";
			reg = <0x4f000000 0x20000>;
			interrupt-parent = <&intc_tc11mp>;
			interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "peripheral";
		};
	};
};

repo_name: angery/linux


code:
/*
 * Copyright 2016 Linaro Ltd
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/dts-v1/;
#include "arm-realview-pbx.dtsi"

/ {
	model = "ARM RealView Platform Baseboard for Cortex-A8";
	compatible = "arm,realview-pba8";
	arm,hbi = <0x178>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "arm,realview-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0>;
		};
	};

	pmu: pmu@0 {
		compatible = "arm,cortex-a8-pmu";
		interrupt-parent = <&intc>;
		interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>;
	};

	/* Primary GIC PL390 interrupt controller in the test chip */
	intc: interrupt-controller@1e000000 {
		compatible = "arm,pl390";
		#interrupt-cells = <3>;
		#address-cells = <1>;
		interrupt-controller;
		reg = <0x1e001000 0x1000>,
		      <0x1e000000 0x100>;
	};
};

&ethernet {
	interrupt-parent = <&intc>;
	interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
};

&usb {
	interrupt-parent = <&intc>;
	interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
};

&soc {
	compatible = "arm,realview-pba8-soc", "simple-bus";
};

&syscon {
	compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd";
};

&serial0 {
	interrupt-parent = <&intc>;
	interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
};

&serial1 {
	interrupt-parent = <&intc>;
	interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
};

&serial2 {
	interrupt-parent = <&intc>;
	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
};

&serial3 {
	interrupt-parent = <&intc>;
	interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
};

&ssp {
	interrupt-parent = <&intc>;
	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
};

&wdog0 {
	interrupt-parent = <&intc>;
	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
};

&wdog1 {
	interrupt-parent = <&intc>;
	interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
};

&timer01 {
	interrupt-parent = <&intc>;
	interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
};

&timer23 {
	interrupt-parent = <&intc>;
	interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
};

&gpio0 {
	interrupt-parent = <&intc>;
	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
};

&gpio1 {
	interrupt-parent = <&intc>;
	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
};

&gpio2 {
	interrupt-parent = <&intc>;
	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
};

&rtc {
	interrupt-parent = <&intc>;
	interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
};

&timer45 {
	interrupt-parent = <&intc>;
	interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
};

&timer67 {
	interrupt-parent = <&intc>;
	interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
};

&aaci {
	interrupt-parent = <&intc>;
	interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
};

&mmc {
	interrupt-parent = <&intc>;
	interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
		     <0 18 IRQ_TYPE_LEVEL_HIGH>;
};

&kmi0 {
	interrupt-parent = <&intc>;
	interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
};

&kmi1 {
	interrupt-parent = <&intc>;
	interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
};

&clcd {
	interrupt-parent = <&intc>;
	interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
};


code:
/*
 * Copyright 2016 Linaro Ltd
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/dts-v1/;
#include "arm-realview-pbx.dtsi"

/ {
	/*
	 * This is the RealView Platform Baseboard Explore for Cortex-A9
	 * (HBI0182 + HBI0183) as described in ARM DUI 0440B
	 */
	model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
	arm,hbi = <0x182>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "arm,realview-smp";

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
				core1 {
					cpu = <&CPU1>;
				};
			};
		};
		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x0>;
			next-level-cache = <&L2>;
		};
		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0x1>;
			next-level-cache = <&L2>;
		};
	};

	L2: cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0x1f002000 0x1000>;
		cache-unified;
		cache-level = <2>;
		/*
		 * Override default cache size, sets and
		 * associativity as these may be erroneously set
		 * up by boot loader(s).
		 */
		cache-size = <131072>; // 128KB
		cache-sets = <512>;
		cache-line-size = <32>;
		arm,parity-disable;
		arm,tag-latency = <1 1 1>;
		arm,data-latency = <1 1 1>;
	};

	scu: scu@1f000000 {
		compatible = "arm,cortex-a9-scu";
		reg = <0x1f000000 0x100>;
	};

	twd_timer: timer@1f000600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x1f000600 0x20>;
		interrupt-parent = <&intc>;
		interrupts = <1 13 0xf04>;
	};

	twd_wdog: watchdog@1f000620 {
		compatible = "arm,cortex-a9-twd-wdt";
		reg = <0x1f000620 0x20>;
		interrupt-parent = <&intc>;
		interrupts = <1 14 0xf04>;
	};

	pmu: pmu@0 {
		compatible = "arm,cortex-a9-pmu";
		interrupt-parent = <&intc>;
		interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>,
			     <0 45 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&CPU0>, <&CPU1>;
	};

	/* Primary GIC PL390 interrupt controller in the test chip */
	intc: interrupt-controller@1f000000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <1>;
		interrupt-controller;
		reg = <0x1f001000 0x1000>,
		      <0x1f000100 0x100>;
	};
};

&ethernet {
	interrupt-parent = <&intc>;
	interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
};

&usb {
	interrupt-parent = <&intc>;
	interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
};

&serial0 {
	interrupt-parent = <&intc>;
	interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
};

&serial1 {
	interrupt-parent = <&intc>;
	interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
};

&serial2 {
	interrupt-parent = <&intc>;
	interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
};

&serial3 {
	interrupt-parent = <&intc>;
	interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
};

&ssp {
	interrupt-parent = <&intc>;
	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
};

&wdog0 {
	interrupt-parent = <&intc>;
	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
};

&wdog1 {
	interrupt-parent = <&intc>;
	interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
};

&timer01 {
	interrupt-parent = <&intc>;
	interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
};

&timer23 {
	interrupt-parent = <&intc>;
	interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
};

&gpio0 {
	interrupt-parent = <&intc>;
	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
};

&gpio1 {
	interrupt-parent = <&intc>;
	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
};

&gpio2 {
	interrupt-parent = <&intc>;
	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
};

&rtc {
	interrupt-parent = <&intc>;
	interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
};

&timer45 {
	interrupt-parent = <&intc>;
	interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
};

&timer67 {
	interrupt-parent = <&intc>;
	interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
};

&aaci {
	interrupt-parent = <&intc>;
	interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
};

&mmc {
	interrupt-parent = <&intc>;
	interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
		     <0 18 IRQ_TYPE_LEVEL_HIGH>;
};

&kmi0 {
	interrupt-parent = <&intc>;
	interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
};

&kmi1 {
	interrupt-parent = <&intc>;
	interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
};

&clcd {
	interrupt-parent = <&intc>;
	interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
};


code:
/*
 * Copyright 2016 Linaro Ltd
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "arm,realview-pbx";

	chosen { };

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serial3;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
	};

	memory {
		device_type = "memory";
		/* 128 MiB memory @ 0x0 */
		reg = <0x00000000 0x08000000>;
	};

	/* The voltage to the MMC card is hardwired at 3.3V */
	vmmc: regulator-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "vmmc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
        };

	veth: regulator-veth {
		compatible = "regulator-fixed";
		regulator-name = "veth";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
	};

	xtal24mhz: xtal24mhz@24M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
	};

	refclk32khz: refclk32khz {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
	};

	timclk: timclk@1M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <24>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	mclk: mclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	kmiclk: kmiclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	sspclk: sspclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	uartclk: uartclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	wdogclk: wdogclk@24M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	/* FIXME: this actually hangs off the PLL clocks */
	pclk: pclk@0 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	flash0@40000000 {
		/* 2 * 32MiB NOR Flash memory */
		compatible = "arm,versatile-flash", "cfi-flash";
		reg = <0x40000000 0x04000000>;
		bank-width = <4>;
		partitions {
			compatible = "arm,arm-firmware-suite";
		};
	};

	flash1@44000000 {
		/* 2 * 32MiB NOR Flash memory */
		compatible = "arm,versatile-flash", "cfi-flash";
		reg = <0x44000000 0x04000000>;
		bank-width = <4>;
		partitions {
			compatible = "arm,arm-firmware-suite";
		};
	};

	/* SMSC 9118 ethernet with PHY and EEPROM */
	ethernet: ethernet@4e000000 {
		compatible = "smsc,lan9118", "smsc,lan9115";
		reg = <0x4e000000 0x10000>;
		phy-mode = "mii";
		reg-io-width = <4>;
		smsc,irq-active-high;
		smsc,irq-push-pull;
		vdd33a-supply = <&veth>;
		vddvario-supply = <&veth>;
	};

	usb: usb@4f000000 {
		compatible = "nxp,usb-isp1761";
		reg = <0x4f000000 0x20000>;
		dr_mode = "peripheral";
	};

	bridge {
		compatible = "ti,ths8134a", "ti,ths8134";
		#address-cells = <1>;
		#size-cells = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				vga_bridge_in: endpoint {
					remote-endpoint = <&clcd_pads>;
				};
			};

			port@1 {
				reg = <1>;

				vga_bridge_out: endpoint {
					remote-endpoint = <&vga_con_in>;
				};
			};
		};
	};

	vga {
		/*
		 * This DDC I2C is connected directly to the DVI portions
		 * of the connector, so it's not really working when the
		 * monitor is connected to the VGA connector.
		 */
		compatible = "vga-connector";
		ddc-i2c-bus = <&i2c1>;

		port {
			vga_con_in: endpoint {
				remote-endpoint = <&vga_bridge_out>;
			};
		};
	};

	soc: soc {
		compatible = "arm,realview-pbx-soc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		regmap = <&syscon>;
		ranges;

		syscon: syscon@10000000 {
			compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
			reg = <0x10000000 0x1000>;
			ranges = <0x0 0x10000000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			led@8,0 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x01>;
				label = "versatile:0";
				linux,default-trigger = "heartbeat";
				default-state = "on";
			};
			led@8,1 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x02>;
				label = "versatile:1";
				linux,default-trigger = "mmc0";
				default-state = "off";
			};
			led@8,2 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x04>;
				label = "versatile:2";
				linux,default-trigger = "cpu0";
				default-state = "off";
			};
			led@8,3 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x08>;
				label = "versatile:3";
				default-state = "off";
			};
			led@8,4 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x10>;
				label = "versatile:4";
				default-state = "off";
			};
			led@8,5 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x20>;
				label = "versatile:5";
				default-state = "off";
			};
			led@8,6 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x40>;
				label = "versatile:6";
				default-state = "off";
			};
			led@8,7 {
				compatible = "register-bit-led";
				reg = <0x08 0x04>;
				offset = <0x08>;
				mask = <0x80>;
				label = "versatile:7";
				default-state = "off";
			};
			oscclk0: clock-controller@c {
				compatible = "arm,syscon-icst307";
				reg = <0x0c 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x0C>;
				clocks = <&xtal24mhz>;
			};
			oscclk1: clock-controller@10 {
				compatible = "arm,syscon-icst307";
				reg = <0x10 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x10>;
				clocks = <&xtal24mhz>;
			};
			oscclk2: clock-controller@14 {
				compatible = "arm,syscon-icst307";
				reg = <0x14 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x14>;
				clocks = <&xtal24mhz>;
			};
			oscclk3: clock-controller@18 {
				compatible = "arm,syscon-icst307";
				reg = <0x18 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x18>;
				clocks = <&xtal24mhz>;
			};
			oscclk4: clock-controller@1c {
				compatible = "arm,syscon-icst307";
				reg = <0x1c 0x04>;
				#clock-cells = <0>;
				lock-offset = <0x20>;
				vco-offset = <0x1c>;
				clocks = <&xtal24mhz>;
			};
		};

		sp810_syscon0: sysctl@10001000 {
			compatible = "arm,sp810", "arm,primecell";
			reg = <0x10001000 0x1000>;
			clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
			clock-names = "refclk", "timclk", "apb_pclk";
			#clock-cells = <1>;
			clock-output-names = "timerclk0",
					     "timerclk1",
					     "timerclk2",
					     "timerclk3";
			assigned-clocks = <&sp810_syscon0 0>,
					  <&sp810_syscon0 1>,
					  <&sp810_syscon0 2>,
					  <&sp810_syscon0 3>;
			assigned-clock-parents = <&timclk>,
					       <&timclk>,
					       <&timclk>,
					       <&timclk>;
		};

		i2c0: i2c@10002000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "arm,versatile-i2c";
			reg = <0x10002000 0x1000>;

			rtc@68 {
				compatible = "dallas,ds1338";
				reg = <0x68>;
			};
		};

		serial0: serial@10009000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x10009000 0x1000>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		serial1: serial@1000a000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x1000a000 0x1000>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		serial2: serial@1000b000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x1000b000 0x1000>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		ssp: spi@1000d000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x1000d000 0x1000>;
			clocks = <&sspclk>, <&pclk>;
			clock-names = "sspclk", "apb_pclk";
		};

		wdog0: watchdog@1000f000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x1000f000 0x1000>;
			clocks = <&wdogclk>, <&pclk>;
			clock-names = "wdog_clk", "apb_pclk";
			status = "disabled";
		};

		wdog1: watchdog@10010000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x10010000 0x1000>;
			clocks = <&wdogclk>, <&pclk>;
			clock-names = "wdog_clk", "apb_pclk";
			status = "disabled";
		};

		timer01: timer@10011000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x10011000 0x1000>;
			clocks = <&sp810_syscon0 0>,
			         <&sp810_syscon0 1>,
				 <&pclk>;
			clock-names = "timerclk0",
				    "timerclk1",
				    "apb_pclk";
		};

		timer23: timer@10012000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x10012000 0x1000>;
			clocks = <&sp810_syscon0 2>,
			         <&sp810_syscon0 3>,
				 <&pclk>;
			clock-names = "timerclk2",
				    "timerclk3",
				    "apb_pclk";
		};

		gpio0: gpio@10013000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x10013000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		gpio1: gpio@10014000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x10014000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		gpio2: gpio@10015000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x10015000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		i2c1: i2c@10016000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "arm,versatile-i2c";
			reg = <0x10016000 0x1000>;
		};

		rtc: rtc@10017000 {
			compatible = "arm,pl031", "arm,primecell";
			reg = <0x10017000 0x1000>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		timer45: timer@10018000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x10018000 0x1000>;
			clocks = <&timclk>, <&timclk>, <&pclk>;
			clock-names = "timerclk4", "timerclk5", "apb_pclk";
		};

		timer67: timer@10019000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x10019000 0x1000>;
			clocks = <&timclk>, <&timclk>, <&pclk>;
			clock-names = "timerclk6", "timerclk7", "apb_pclk";
		};

		sp810_syscon1: sysctl@1001a000 {
			compatible = "arm,sp810", "arm,primecell";
			reg = <0x1001a000 0x1000>;
			clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
			clock-names = "refclk", "timclk", "apb_pclk";
			#clock-cells = <1>;
			clock-output-names = "timerclk4",
					     "timerclk5",
					     "timerclk6",
					     "timerclk7";
			assigned-clocks = <&sp810_syscon1 0>,
					  <&sp810_syscon1 1>,
					  <&sp810_syscon1 2>,
					  <&sp810_syscon1 3>;
			assigned-clock-parents = <&timclk>,
					       <&timclk>,
					       <&timclk>,
					       <&timclk>;
		};
	};

	/* These peripherals are inside the FPGA */
	fpga {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		aaci: aaci@10004000 {
			compatible = "arm,pl041", "arm,primecell";
			reg = <0x10004000 0x1000>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		mmc: mmcsd@10005000 {
			compatible = "arm,pl18x", "arm,primecell";
			reg = <0x10005000 0x1000>;

			/* Due to frequent FIFO overruns, use just 500 kHz */
			max-frequency = <500000>;
			bus-width = <4>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			clocks = <&mclk>, <&pclk>;
			clock-names = "mclk", "apb_pclk";
			vmmc-supply = <&vmmc>;
			cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
			wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
		};

		kmi0: kmi@10006000 {
			compatible = "arm,pl050", "arm,primecell";
			reg = <0x10006000 0x1000>;
			clocks = <&kmiclk>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};

		kmi1: kmi@10007000 {
			compatible = "arm,pl050", "arm,primecell";
			reg = <0x10007000 0x1000>;
			clocks = <&kmiclk>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};

		serial3: serial@1000c000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x1000c000 0x1000>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};
	};

	/* These peripherals are inside the NEC ISSP */
	issp {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		clcd: clcd@10020000 {
			compatible = "arm,pl111", "arm,primecell";
			reg = <0x10020000 0x1000>;
			interrupt-names = "combined";
			clocks = <&oscclk4>, <&pclk>;
			clock-names = "clcdclk", "apb_pclk";
			/* 1024x768 16bpp @65MHz works fine */
			max-memory-bandwidth = <95000000>;

			port {
				clcd_pads: endpoint {
					remote-endpoint = <&vga_bridge_in>;
					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Device Tree file for Ctera C200-V2
 *
 * Copyright (C) 2022 Pawel Dembicki <paweldembicki@gmail.com>
 */

/dts-v1/;

#include "armada-370.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/leds/common.h>

/ {
	model = "Ctera C200 V2";
	compatible = "ctera,c200-v2", "marvell,armada370", "marvell,armada-370-xp";

	chosen {
		bootargs = "console=ttyS0,115200";
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>; /* 1024 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
	};

	thermal-zones {
		ethphy-thermal {
			polling-delay = <20000>;
			polling-delay-passive = <2000>;

			thermal-sensors = <&ethphy0>;

			trips {
				ethphy_alert1: trip1 {
					temperature = <65000>;
					hysteresis = <4000>;
					type = "passive";
				};

				ethphy_crit: trip2 {
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	beeper {
		compatible = "pwm-beeper";
		pinctrl-0 = <&pmx_beeper>;
		pinctrl-names = "default";
		pwms = <&gpio1 31 4000>;
	};

	gpio-poweroff {
		compatible = "gpio-poweroff";
		pinctrl-0 = <&pmx_poweroff>;
		pinctrl-names = "default";
		gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
	};

	keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&pmx_buttons>;
		pinctrl-names = "default";

		button-power {
			label = "Power Button";
			linux,code = <KEY_POWER>;
			gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
		};

		button-reset {
			label = "Reset Button";
			linux,code = <KEY_RESTART>;
			gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
		};

		button-usb1 {
			label = "USB1 Button";
			linux,code = <BTN_0>;
			gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
		};

		button-usb2 {
			label = "USB2 Button";
			linux,code = <BTN_1>;
			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
		};
	};

	leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&pmx_leds1 &pmx_leds2>;
		pinctrl-names = "default";

		led-0 {
			function = LED_FUNCTION_USB;
			function-enumerator = <2>;
			color = <LED_COLOR_ID_RED>;
			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
		};

		led-1 {
			function = LED_FUNCTION_USB;
			function-enumerator = <2>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
		};

		led-2 {
			function = LED_FUNCTION_USB;
			function-enumerator = <1>;
			color = <LED_COLOR_ID_RED>;
			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
		};

		led-3 {
			function = LED_FUNCTION_USB;
			function-enumerator = <1>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
		};

		led-4 {
			function = LED_FUNCTION_DISK;
			function-enumerator = <2>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
		};

		led-5 {
			function = LED_FUNCTION_DISK;
			function-enumerator = <1>;
			color = <LED_COLOR_ID_RED>;
			gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
		};

		led-6 {
			function = LED_FUNCTION_DISK;
			function-enumerator = <2>;
			color = <LED_COLOR_ID_RED>;
			gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
		};

		led-7 {
			function = LED_FUNCTION_INDICATOR;
			color = <LED_COLOR_ID_BLUE>;
			gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
		};

		led-8 {
			function = LED_FUNCTION_DISK_ERR;
			color = <LED_COLOR_ID_RED>;
			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
		};

		led-9 {
			function = LED_FUNCTION_DISK_ERR;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
		};

		led-10 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
		};

		led-11 {
			function = LED_FUNCTION_DISK;
			function-enumerator = <1>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
		};

		led-12 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
		};
	};
};

&coherencyfab {
	broken-idle;
};

&eth1 {
	pinctrl-0 = <&ge1_rgmii_pins>;
	pinctrl-names = "default";
	status = "okay";
	phy-handle = <&ethphy0>;
	phy-connection-type = "rgmii-id";
};

&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";
	clock-frequency = <100000>;
	status = "okay";

	hwmon@2a {
		compatible = "nuvoton,nct7802";
		reg = <0x2a>;
	};

	rtc@30 {
		compatible = "sii,s35390a";
		reg = <0x30>;
	};
};

&mdio {
	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";

	ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */
		reg = <0>;
		#thermal-sensor-cells = <0>;
	};
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		marvell,nand-keep-config;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "uboot";
				reg = <0x0000000 0x200000>;
				read-only;
			};

			partition@200000 {
				label = "certificate";
				reg = <0x0200000 0x100000>;
				read-only;
			};

			partition@300000 {
				label = "preset_cfg";
				reg = <0x0300000 0x100000>;
				read-only;
			};

			partition@400000 {
				label = "dev_params";
				reg = <0x0400000 0x100000>;
				read-only;
			};
			partition@500000 {
				label = "active_bank";
				reg = <0x0500000 0x0100000>;
			};

			partition@600000 {
				label = "magic";
				reg = <0x0600000 0x0100000>;
				read-only;
			};

			partition@700000 {
				label = "bank1";
				reg = <0x0700000 0x2800000>;
			};

			partition@2f00000 {
				label = "bank2";
				reg = <0x2f00000 0x2800000>;
			};

			/* 0x5700000-0x5a00000 undefined in vendor firmware */

			partition@5a00000 {
				label = "reserved";
				reg = <0x5a00000 0x2000000>;
			};

			partition@7a00000 {
				label = "rootfs";
				reg = <0x7a00000 0x8600000>;
			};
		};
	};
};

&pciec {
	status = "okay";

	pcie@1,0 { /* Renesas uPD720202 USB 3.0 controller */
		pinctrl-0 = <&pmx_pcie>;
		pinctrl-names = "default";
		status = "okay";
		reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
	};
};

&pinctrl {
	pmx_poweroff: pmx-poweroff {
		marvell,pins = "mpp7";
		marvell,function = "gpo";
	};

	pmx_power_cpu: pmx-power-cpu {
		marvell,pins = "mpp4";
		marvell,function = "vdd";
	};

	pmx_buttons: pmx-buttons {
		marvell,pins = "mpp6", "mpp10", "mpp14", "mpp32";
		marvell,function = "gpio";
	};

	pmx_leds1: pmx-leds1 {
		marvell,pins = "mpp47";
		marvell,function = "gpo";
	};

	pmx_leds2: pmx-leds2 {
		marvell,pins = "mpp12", "mpp13", "mpp15", "mpp16", "mpp50", "mpp51",
			       "mpp52", "mpp53", "mpp55", "mpp56", "mpp57", "mpp58";
		marvell,function = "gpio";
	};

	pmx_pcie: pmx-pcie {
		marvell,pins = "mpp59";
		marvell,function = "gpio";
	};

	pmx_beeper: pmx-beeper {
		marvell,pins = "mpp63";
		marvell,function = "gpio";
	};
};

&pmsu {
	pinctrl-0 = <&pmx_power_cpu>;
	pinctrl-names = "default";
};

&rtc {
	status = "disabled";
};

&sata {
	nr-ports = <2>;
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	hdd0_temp: sata-port@0 {
		reg = <0>;
		#thermal-sensor-cells = <0>;
	};

	hdd1_temp: sata-port@1 {
		reg = <1>;
		#thermal-sensor-cells = <0>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell Armada 370 evaluation board
 * (DB-88F6710-BP-DDR3)
 *
 *  Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the default
 * 0xd0000000). The 0xf1000000 is the default used by the recent,
 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
 * boards were delivered with an older version of the bootloader that
 * left internal registers mapped at 0xd0000000. If you are in this
 * situation, you should either update your bootloader (preferred
 * solution) or the below Device Tree should be adjusted.
 */

/dts-v1/;
#include "armada-370.dtsi"

/ {
	model = "Marvell Armada 370 Evaluation Board";
	compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x40000000>; /* 1 GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;

		internal-regs {
			serial@12000 {
				status = "okay";
			};
			sata@a0000 {
				nr-ports = <2>;
				status = "okay";
			};

			ethernet@70000 {
				pinctrl-0 = <&ge0_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};
			ethernet@74000 {
				pinctrl-0 = <&ge1_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
			};

			i2c@11000 {
				pinctrl-0 = <&i2c0_pins>;
				pinctrl-names = "default";
				clock-frequency = <100000>;
				status = "okay";
				audio_codec: audio-codec@4a {
					#sound-dai-cells = <0>;
					compatible = "cirrus,cs42l51";
					reg = <0x4a>;
				};
			};

			audio-controller@30000 {
				pinctrl-0 = <&i2s_pins2>;
				pinctrl-names = "default";
				status = "okay";
			};

			mvsdio@d4000 {
				pinctrl-0 = <&sdio_pins1>;
				pinctrl-names = "default";
				/*
				 * This device is disabled by default, because
				 * using the SD card connector requires
				 * changing the default CON40 connector
				 * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
				 * different connector
				 * "DB-88F6710_MPP_RGMII_SD_Jumper".
				 */
				status = "disabled";
				/* No CD or WP GPIOs */
				broken-cd;
			};

			usb@50000 {
				status = "okay";
			};

			usb@51000 {
				status = "okay";
			};
		};
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "Armada 370 DB Audio";
		simple-audio-card,mclk-fs = <256>;
		simple-audio-card,widgets =
			"Headphone", "Out Jack",
			"Line", "In Jack";
		simple-audio-card,routing =
			"Out Jack", "HPL",
			"Out Jack", "HPR",
			"AIN1L", "In Jack",
			"AIN1L", "In Jack";
		status = "okay";

		simple-audio-card,dai-link@0 {
			format = "i2s";
			cpu {
				sound-dai = <&audio_controller 0>;
			};

			codec {
				sound-dai = <&audio_codec>;
			};
		};

		simple-audio-card,dai-link@1 {
			format = "i2s";
			cpu {
				sound-dai = <&audio_controller 1>;
			};

			codec {
				sound-dai = <&spdif_out>;
			};
		};

		simple-audio-card,dai-link@2 {
			format = "i2s";
			cpu {
				sound-dai = <&audio_controller 1>;
			};

			codec {
				sound-dai = <&spdif_in>;
			};
		};
	};

	spdif_out: spdif-out {
		#sound-dai-cells = <0>;
		compatible = "linux,spdif-dit";
	};

	spdif_in: spdif-in {
		#sound-dai-cells = <0>;
		compatible = "linux,spdif-dir";
	};
};

&pciec {
	status = "okay";
	/*
	 * The two PCIe units are accessible through
	 * both standard PCIe slots and mini-PCIe
	 * slots on the board.
	 */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};

	pcie@2,0 {
		/* Port 1, Lane 0 */
		status = "okay";
	};
};

&mdio {
	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";
	phy0: ethernet-phy@0 {
		reg = <0>;
	};

	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&spi0 {
	pinctrl-0 = <&spi0_pins2>;
	pinctrl-names = "default";
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "mx25l25635e", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <50000000>;
	};
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		marvell,nand-keep-config;
		nand-on-flash-bbt;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0 0x800000>;
			};
			partition@800000 {
				label = "Linux";
				reg = <0x800000 0x800000>;
			};
			partition@1000000 {
				label = "Filesystem";
				reg = <0x1000000 0x3f000000>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for D-Link DNS-327L
 *
 * Copyright (C) 2015, Andrew Andrianov <andrew@ncrmnt.org>
 */

/* Remaining unsolved:
 * There's still some unknown device on i2c address 0x13
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi"

/ {
	model = "D-Link DNS-327L";
	compatible = "dlink,dns327l",
		"marvell,armada370",
		"marvell,armada-370-xp";

	chosen {
		stdout-path = &uart0;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x20000000>; /* 512 MiB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
			MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
			MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;

		internal-regs {
			sata@a0000 {
				nr-ports = <2>;
				status = "okay";
			};

			usb@50000 {
				status = "okay";
			};
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <
			&backup_button_pin
			&power_button_pin
			&reset_button_pin>;
		pinctrl-names = "default";

		power-button {
			label = "Power Button";
			linux,code = <KEY_POWER>;
			gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
		};

		backup-button {
			label = "Backup Button";
			linux,code = <KEY_COPY>;
			gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
		};

		reset-button {
			label = "Reset Button";
			linux,code = <KEY_RESTART>;
			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <
			&sata_l_amber_pin
			&sata_r_amber_pin
			&backup_led_pin
			/* Ensure these are managed by hardware */
			&sata_l_white_pin
			&sata_r_white_pin>;

		pinctrl-names = "default";

		led-sata-r-amber {
			label = "dns327l:amber:sata-r";
			gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
			default-state = "keep";
		};

		led-sata-l-amber {
			label = "dns327l:amber:sata-l";
			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
			default-state = "keep";
		};

		led-backup {
			label = "dns327l:white:usb";
			gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
			default-state = "keep";
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		usb_power: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			pinctrl-0 = <&xhci_pwr_pin>;
			pinctrl-names = "default";
			regulator-name = "USB3.0 Port Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-boot-on;
			regulator-always-on;
			gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
		};

		sata_r_power: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			pinctrl-0 = <&sata_r_pwr_pin>;
			pinctrl-names = "default";
			regulator-name = "SATA-R Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			startup-delay-us = <2000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
		};

		sata_l_power: regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			pinctrl-0 = <&sata_l_pwr_pin>;
			pinctrl-names = "default";
			regulator-name = "SATA-L Power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			startup-delay-us = <4000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
		};
	};
};

&pciec {
	status = "okay";

	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};

	pcie@2,0 {
		/* Port 1, Lane 0 */
		status = "okay";
	};
};

&pinctrl {
	sata_l_white_pin: sata-l-white-pin {
		marvell,pins = "mpp57";
		marvell,function = "sata0";
	};

	sata_r_white_pin: sata-r-white-pin {
		marvell,pins = "mpp55";
		marvell,function = "sata1";
	};

	sata_r_amber_pin: sata-r-amber-pin {
		marvell,pins = "mpp52";
		marvell,function = "gpio";
	};

	sata_l_amber_pin: sata-l-amber-pin {
		marvell,pins = "mpp53";
		marvell,function = "gpio";
	};

	backup_led_pin: backup-led-pin {
		marvell,pins = "mpp61";
		marvell,function = "gpo";
	};

	xhci_pwr_pin: xhci-pwr-pin {
		marvell,pins = "mpp13";
		marvell,function = "gpio";
	};

	sata_r_pwr_pin: sata-r-pwr-pin {
		marvell,pins = "mpp54";
		marvell,function = "gpio";
	};

	sata_l_pwr_pin: sata-l-pwr-pin {
		marvell,pins = "mpp56";
		marvell,function = "gpio";
	};

	uart1_pins: uart1-pins {
		marvell,pins = "mpp60", "mpp61";
		marvell,function = "uart1";
	};

	power_button_pin: power-button-pin {
		marvell,pins = "mpp65";
		marvell,function = "gpio";
	};

	backup_button_pin: backup-button-pin {
		marvell,pins = "mpp63";
		marvell,function = "gpio";
	};

	reset_button_pin: reset-button-pin {
		marvell,pins = "mpp64";
		marvell,function = "gpio";
	};
};

/* Serial console */
&uart0 {
	status = "okay";
};

/* Connected to Weltrend MCU */
&uart1 {
	pinctrl-0 = <&uart1_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&mdio {
	phy0: ethernet-phy@0 { /* Marvell 88E1318 */
		reg = <0>;
		marvell,reg-init = <0x2 0x19 0x0 0x0077>,
				   <0x2 0x18 0x0 0x5747>;
	};
};

&eth1 {
	phy = <&phy0>;
	phy-mode = "rgmii-id";
	status = "okay";
};

&i2c0 {
	compatible = "marvell,mv64xxx-i2c";
	clock-frequency = <100000>;
	status = "okay";
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		marvell,nand-keep-config;
		nand-on-flash-bbt;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				/* 1.0 MiB */
				reg = <0x0000000 0x100000>;
				read-only;
			};

			partition@100000 {
				label = "u-boot-env";
				/* 128 KiB */
				reg = <0x100000 0x20000>;
				read-only;
			};

			partition@120000 {
				label = "uImage";
				/* 7 MiB */
				reg = <0x120000 0x700000>;
			};

			partition@820000 {
				label = "ubifs";
				/* ~ 84 MiB */
				reg = <0x820000 0x54e0000>;
			};

			/* Hardcoded into stock bootloader */
			partition@5d00000 {
				label = "failsafe-uImage";
				/* 5 MiB */
				reg = <0x5d00000 0x500000>;
			};

			partition@6200000 {
				label = "failsafe-fs";
				/* 29 MiB */
				reg = <0x6200000 0x1d00000>;
			};

			partition@7f00000 {
				label = "bbt";
				/* 1 MiB for BBT */
				reg = <0x7f00000 0x100000>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Globalscale Mirabox
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi"

/ {
	model = "Globalscale Mirabox";
	compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x20000000>; /* 512 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;

		internal-regs {
			serial@12000 {
				status = "okay";
			};
			timer@20300 {
				clock-frequency = <600000000>;
				status = "okay";
			};

			gpio_leds {
				compatible = "gpio-leds";
				pinctrl-names = "default";
				pinctrl-0 = <&pwr_led_pin &stat_led_pins>;

				green_pwr_led {
					label = "mirabox:green:pwr";
					gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
					default-state = "keep";
				};

				blue_stat_led {
					label = "mirabox:blue:stat";
					gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
					default-state = "off";
				};

				green_stat_led {
					label = "mirabox:green:stat";
					gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
					default-state = "off";
				};
			};

			ethernet@70000 {
				pinctrl-0 = <&ge0_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};
			ethernet@74000 {
				pinctrl-0 = <&ge1_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
			};

			crypto@90000 {
				status = "okay";
			};

			mvsdio@d4000 {
				pinctrl-0 = <&sdio_pins3>;
				pinctrl-names = "default";
				status = "okay";
				/*
				 * No CD or WP GPIOs: SDIO interface used for
				 * Wifi/Bluetooth chip
				 */
				 broken-cd;
			};

			usb@50000 {
				status = "okay";
			};

			usb@51000 {
				status = "okay";
			};

			i2c@11000 {
				status = "okay";
				clock-frequency = <100000>;
				pca9505: pca9505@25 {
					compatible = "nxp,pca9505";
					gpio-controller;
					#gpio-cells = <2>;
					reg = <0x25>;
				};
			};
		};
	};
};

&pciec {
	status = "okay";

	/* Internal mini-PCIe connector */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};

	/* Connected on the PCB to a USB 3.0 XHCI controller */
	pcie@2,0 {
		/* Port 1, Lane 0 */
		status = "okay";
	};
};

&mdio {
	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";
	phy0: ethernet-phy@0 {
		reg = <0>;
	};

	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&pinctrl {
	pwr_led_pin: pwr-led-pin {
		marvell,pins = "mpp63";
		marvell,function = "gpio";
	};

	stat_led_pins: stat-led-pins {
		marvell,pins = "mpp64", "mpp65";
		marvell,function = "gpio";
	};
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		marvell,nand-keep-config;
		nand-on-flash-bbt;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0 0x400000>;
			};
			partition@400000 {
				label = "Linux";
				reg = <0x400000 0x400000>;
			};
			partition@800000 {
				label = "Filesystem";
				reg = <0x800000 0x3f800000>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for NETGEAR ReadyNAS 102
 *
 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi"

/ {
	model = "NETGEAR ReadyNAS 102";
	compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x20000000>; /* 512 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;

		internal-regs {

			/* RTC is provided by Intersil ISL12057 I2C RTC chip */
			rtc@10300 {
				status = "disabled";
			};

			serial@12000 {
				status = "okay";
			};

			/* eSATA interface */
			sata@a0000 {
				nr-ports = <1>;
				status = "okay";
			};

			ethernet@74000 {
				pinctrl-0 = <&ge1_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};

			usb@50000 {
				status = "okay";
			};

			i2c@11000 {
				clock-frequency = <100000>;

				pinctrl-0 = <&i2c0_pins>;
				pinctrl-names = "default";

				status = "okay";

				isl12057: rtc@68 {
					compatible = "isil,isl12057";
					reg = <0x68>;
					wakeup-source;
				};

				g762: g762@3e {
					compatible = "gmt,g762";
					reg = <0x3e>;
					clocks = <&g762_clk>; /* input clock */
					fan_gear_mode = <0>;
					fan_startv = <1>;
					pwm_polarity = <0>;
				};
			};
		};
	};

	clocks {
		g762_clk: g762-oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <8192>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&power_led_pin
			     &sata1_led_pin
			     &sata2_led_pin
			     &backup_led_pin>;
		pinctrl-names = "default";

		blue-power-led {
			label = "rn102:blue:pwr";
			gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
			default-state = "keep";
		};

		blue-sata1-led {
			label = "rn102:blue:sata1";
			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};

		blue-sata2-led {
			label = "rn102:blue:sata2";
			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};

		blue-backup-led {
			label = "rn102:blue:backup";
			gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&power_button_pin
			     &reset_button_pin
			     &backup_button_pin>;
		pinctrl-names = "default";

		power-button {
			label = "Power Button";
			linux,code = <KEY_POWER>;
			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
		};

		reset-button {
			label = "Reset Button";
			linux,code = <KEY_RESTART>;
			gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
		};

		backup-button {
			label = "Backup Button";
			linux,code = <KEY_COPY>;
			gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-poweroff {
		compatible = "gpio-poweroff";
		pinctrl-0 = <&poweroff>;
		pinctrl-names = "default";
		gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
	};
};

&pciec {
	status = "okay";

	/* Connected to Marvell 88SE9170 SATA controller */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};

	/* Connected to FL1009 USB 3.0 controller */
	pcie@2,0 {
		/* Port 1, Lane 0 */
		status = "okay";
	};
};

&mdio {
	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";
	phy0: ethernet-phy@0 { /* Marvell 88E1318 */
		reg = <0>;
	};
};

&pinctrl {
	power_led_pin: power-led-pin {
		marvell,pins = "mpp57";
		marvell,function = "gpio";
	};

	sata1_led_pin: sata1-led-pin {
		marvell,pins = "mpp15";
		marvell,function = "gpio";
	};

	sata2_led_pin: sata2-led-pin {
		marvell,pins = "mpp14";
		marvell,function = "gpio";
	};

	backup_led_pin: backup-led-pin {
		marvell,pins = "mpp56";
		marvell,function = "gpio";
	};

	backup_button_pin: backup-button-pin {
		marvell,pins = "mpp58";
		marvell,function = "gpio";
	};

	power_button_pin: power-button-pin {
		marvell,pins = "mpp62";
		marvell,function = "gpio";
	};

	reset_button_pin: reset-button-pin {
		marvell,pins = "mpp6";
		marvell,function = "gpio";
	};

	poweroff: poweroff {
		marvell,pins = "mpp8";
		marvell,function = "gpio";
	};
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		marvell,nand-keep-config;
		nand-on-flash-bbt;

		/* Use Hardware BCH ECC */
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0000000 0x180000>;  /* 1.5MB */
				read-only;
			};

			partition@180000 {
				label = "u-boot-env";
				reg = <0x180000 0x20000>;    /* 128KB */
				read-only;
			};

			partition@200000 {
				label = "uImage";
				reg = <0x0200000 0x600000>;    /* 6MB */
			};

			partition@800000 {
				label = "minirootfs";
				reg = <0x0800000 0x400000>;    /* 4MB */
			};

			/* Last MB is for the BBT, i.e. not writable */
			partition@c00000 {
				label = "ubifs";
				reg = <0x0c00000 0x7400000>; /* 116MB */
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for NETGEAR ReadyNAS 104
 *
 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
 */

/dts-v1/;

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi"

/ {
	model = "NETGEAR ReadyNAS 104";
	compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x20000000>; /* 512 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;

		internal-regs {

			/* RTC is provided by Intersil ISL12057 I2C RTC chip */
			rtc@10300 {
				status = "disabled";
			};

			serial@12000 {
				status = "okay";
			};

			ethernet@70000 {
				pinctrl-0 = <&ge0_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};

			ethernet@74000 {
				pinctrl-0 = <&ge1_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
			};

			usb@50000 {
				status = "okay";
			};

			i2c@11000 {
				clock-frequency = <100000>;

				pinctrl-0 = <&i2c0_pins>;
				pinctrl-names = "default";

				status = "okay";

				isl12057: rtc@68 {
					compatible = "isil,isl12057";
					reg = <0x68>;
					wakeup-source;
				};

				g762: g762@3e {
					compatible = "gmt,g762";
					reg = <0x3e>;
					clocks = <&g762_clk>; /* input clock */
					fan_gear_mode = <0>;
					fan_startv = <1>;
					pwm_polarity = <0>;
				};

				pca9554: pca9554@23 {
					compatible = "nxp,pca9554";
					gpio-controller;
					#gpio-cells = <2>;
					reg = <0x23>;
				};
			};
		};
	};

	clocks {
		g762_clk: g762-oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <8192>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";
		pinctrl-0 = <&backup_led_pin &power_led_pin>;
		pinctrl-names = "default";

		blue-backup-led {
			label = "rn104:blue:backup";
			gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		blue-power-led {
			label = "rn104:blue:pwr";
			gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "keep";
		};

		blue-sata1-led {
			label = "rn104:blue:sata1";
			gpios = <&pca9554 0 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		blue-sata2-led {
			label = "rn104:blue:sata2";
			gpios = <&pca9554 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		blue-sata3-led {
			label = "rn104:blue:sata3";
			gpios = <&pca9554 2 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		blue-sata4-led {
			label = "rn104:blue:sata4";
			gpios = <&pca9554 3 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};

	auxdisplay {
		compatible = "hit,hd44780";
		data-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
				<&gpio1 26 GPIO_ACTIVE_HIGH>,
				<&gpio1 27 GPIO_ACTIVE_HIGH>,
				<&gpio1 29 GPIO_ACTIVE_HIGH>;
		enable-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
		rs-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
		rw-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
		backlight-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
		display-height-chars = <2>;
		display-width-chars = <16>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&backup_button_pin
			     &power_button_pin
			     &reset_button_pin>;
		pinctrl-names = "default";

		backup-button {
			label = "Backup Button";
			linux,code = <KEY_COPY>;
			gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
		};

		power-button {
			label = "Power Button";
			linux,code = <KEY_POWER>;
			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
		};

		reset-button {
			label = "Reset Button";
			linux,code = <KEY_RESTART>;
			gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-poweroff {
		compatible = "gpio-poweroff";
		pinctrl-0 = <&poweroff>;
		pinctrl-names = "default";
		gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
	};
};

&pciec {
	status = "okay";

	/* Connected to FL1009 USB 3.0 controller */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};

	/* Connected to Marvell 88SE9215 SATA controller */
	pcie@2,0 {
		/* Port 1, Lane 0 */
		status = "okay";
	};
};

&mdio {
	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";
	phy0: ethernet-phy@0 { /* Marvell 88E1318 */
		reg = <0>;
	};

	phy1: ethernet-phy@1 { /* Marvell 88E1318 */
		reg = <1>;
	};
};

&pinctrl {
	poweroff: poweroff {
		marvell,pins = "mpp60";
		marvell,function = "gpio";
	};

	backup_button_pin: backup-button-pin {
		marvell,pins = "mpp52";
		marvell,function = "gpio";
	};

	power_button_pin: power-button-pin {
		marvell,pins = "mpp62";
		marvell,function = "gpio";
	};

	backup_led_pin: backup-led-pin {
		marvell,pins = "mpp63";
		marvell,function = "gpio";
	};

	power_led_pin: power-led-pin {
		marvell,pins = "mpp64";
		marvell,function = "gpio";
	};

	reset_button_pin: reset-button-pin {
		marvell,pins = "mpp65";
		marvell,function = "gpio";
	};
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		marvell,nand-keep-config;
		nand-on-flash-bbt;

		/* Use Hardware BCH ECC */
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0000000 0x180000>;  /* 1.5MB */
				read-only;
			};

			partition@180000 {
				label = "u-boot-env";
				reg = <0x180000 0x20000>;    /* 128KB */
				read-only;
			};

			partition@200000 {
				label = "uImage";
				reg = <0x0200000 0x600000>;    /* 6MB */
			};

			partition@800000 {
				label = "minirootfs";
				reg = <0x0800000 0x400000>;    /* 4MB */
			};

			/* Last MB is for the BBT, i.e. not writable */
			partition@c00000 {
				label = "ubifs";
				reg = <0x0c00000 0x7400000>; /* 116MB */
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell Armada 370 Reference Design board
 * (RD-88F6710-A1)
 *
 *  Copied from arch/arm/boot/dts/armada-370-db.dts
 *
 *  Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
 *
 * Note: this Device Tree assumes that the bootloader has remapped the
 * internal registers to 0xf1000000 (instead of the default
 * 0xd0000000). The 0xf1000000 is the default used by the recent,
 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
 * boards were delivered with an older version of the bootloader that
 * left internal registers mapped at 0xd0000000. If you are in this
 * situation, you should either update your bootloader (preferred
 * solution) or the below Device Tree should be adjusted.
 */

/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi"

/ {
	model = "Marvell Armada 370 Reference Design";
	compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x20000000>; /* 512 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;

		internal-regs {
			serial@12000 {
				status = "okay";
			};
			sata@a0000 {
				nr-ports = <2>;
				status = "okay";
			};

			ethernet@70000 {
				status = "okay";
				phy = <&phy0>;
				phy-mode = "sgmii";
			};
			ethernet@74000 {
				pinctrl-0 = <&ge1_rgmii_pins>;
				pinctrl-names = "default";
				status = "okay";
				phy-mode = "rgmii-id";
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			mvsdio@d4000 {
				pinctrl-0 = <&sdio_pins1>;
				pinctrl-names = "default";
				status = "okay";
				/* No CD or WP GPIOs */
				broken-cd;
			};

			usb@50000 {
				status = "okay";
			};

			usb@51000 {
				status = "okay";
			};

			gpio-keys {
				compatible = "gpio-keys";
				button {
					label = "Software Button";
					linux,code = <KEY_POWER>;
					gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
				};
			};

			gpio-fan {
				compatible = "gpio-fan";
				gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
				gpio-fan,speed-map = <0 0 3000 1>;
				pinctrl-0 = <&fan_pins>;
				pinctrl-names = "default";
			};

			gpio_leds {
				compatible = "gpio-leds";
				pinctrl-names = "default";
				pinctrl-0 = <&led_pins>;

				sw_led {
					label = "370rd:green:sw";
					gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
					default-state = "keep";
				};
			};
		};
	};
};

&pciec {
	status = "okay";

	/* Internal mini-PCIe connector */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};

	/* Internal mini-PCIe connector */
	pcie@2,0 {
		/* Port 1, Lane 0 */
		status = "okay";
	};
};

&mdio {
	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";
	phy0: ethernet-phy@0 {
		reg = <0>;
	};

	switch: switch@10 {
		compatible = "marvell,mv88e6085";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x10>;
		interrupt-controller;
		#interrupt-cells = <2>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				label = "lan0";
			};

			port@1 {
				reg = <1>;
				label = "lan1";
			};

			port@2 {
				reg = <2>;
				label = "lan2";
			};

			port@3 {
				reg = <3>;
				label = "lan3";
			};

			port@5 {
				reg = <5>;
				label = "cpu";
				ethernet = <&eth1>;
				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
		};

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switchphy0: switchphy@0 {
				reg = <0>;
				interrupt-parent = <&switch>;
				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
			};

			switchphy1: switchphy@1 {
				reg = <1>;
				interrupt-parent = <&switch>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
			};

			switchphy2: switchphy@2 {
				reg = <2>;
				interrupt-parent = <&switch>;
				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
			};

			switchphy3: switchphy@3 {
				reg = <3>;
				interrupt-parent = <&switch>;
				interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};

&pinctrl {
	fan_pins: fan-pins {
		marvell,pins = "mpp8";
		marvell,function = "gpio";
	};

	led_pins: led-pins {
		marvell,pins = "mpp32";
		marvell,function = "gpio";
	};
};

&nand_controller {
	status = "okay";

	nand@0 {
		reg = <0>;
		label = "pxa3xx_nand-0";
		nand-rb = <0>;
		marvell,nand-keep-config;
		nand-on-flash-bbt;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0 0x800000>;
			};
			partition@800000 {
				label = "Linux";
				reg = <0x800000 0x800000>;
			};
			partition@1000000 {
				label = "Filesystem";
				reg = <0x1000000 0x3f000000>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree file for Seagate NAS 2-Bay (Armada 370 SoC).
 *
 * Copyright (C) 2015 Seagate
 *
 * Author: Vincent Donnefort <vdonnefort@gmail.com>
 */

/*
 * Here are some information allowing to identify the device:
 *
 * Product name                 : Seagate NAS 2-Bay
 * Code name (board/PCB)        : Dart 2-Bay
 * Model name (case sticker)    : SRPD20
 * Material desc (product spec) : STCTxxxxxxx
 */

/dts-v1/;
#include "armada-370-seagate-nas-xbay.dtsi"

/ {
	model = "Seagate NAS 2-Bay (Dart, SRPD20)";
	compatible = "seagate,dart-2", "marvell,armada370", "marvell,armada-370-xp";

	gpio-fan {
		gpio-fan,speed-map =
			<   0 3
			  950 2
			 1400 1
			 1800 0>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC).
 *
 * Copyright (C) 2015 Seagate
 *
 * Author: Vincent Donnefort <vdonnefort@gmail.com>
 */

/*
 * Here are some information allowing to identify the device:
 *
 * Product name                 : Seagate NAS 4-Bay
 * Code name (board/PCB)        : Dart 4-Bay
 * Model name (case sticker)    : SRPD40
 * Material desc (product spec) : STCUxxxxxxx
 */

/dts-v1/;
#include "armada-370-seagate-nas-xbay.dtsi"
#include <dt-bindings/leds/leds-ns2.h>

/ {
	model = "Seagate NAS 4-Bay (Dart, SRPD40)";
	compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp";

	soc {
		internal-regs {
			ethernet@74000 {
				status = "okay";
				pinctrl-0 = <&ge1_rgmii_pins>;
				pinctrl-names = "default";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
			};

			i2c@11000 {
				/* I2C GPIO expander (PCA9554A) */
				pca9554: pca9554@21 {
					compatible = "nxp,pca9554";
					reg = <0x21>;
					#gpio-cells = <2>;
					gpio-controller;
				};
			};
		};
	};

	regulators {
		regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			regulator-name = "SATA2 power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&pca9554 6 GPIO_ACTIVE_HIGH>;
		};
		regulator@4 {
			compatible = "regulator-fixed";
			reg = <4>;
			regulator-name = "SATA3 power";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-always-on;
			regulator-boot-on;
			gpio = <&pca9554 7 GPIO_ACTIVE_HIGH>;
		};
	};

	gpio-leds {
		led-red-sata2 {
			label = "dart:red:sata2";
			gpios = <&pca9554 0 GPIO_ACTIVE_LOW>;
		};
		led-red-sata3 {
			label = "dart:red:sata3";
			gpios = <&pca9554 3 GPIO_ACTIVE_LOW>;
		};
	};

	leds-ns2 {
		compatible = "lacie,ns2-leds";

		white-sata2 {
			label = "dart:white:sata2";
			cmd-gpio = <&pca9554 1 GPIO_ACTIVE_HIGH>;
			slow-gpio = <&pca9554 2 GPIO_ACTIVE_HIGH>;
			num-modes = <4>;
			modes-map = <NS_V2_LED_SATA 0 0
				     NS_V2_LED_OFF  0 1
				     NS_V2_LED_ON   1 0
				     NS_V2_LED_ON   1 1>;
		};
		white-sata3 {
			label = "dart:white:sata3";
			cmd-gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
			slow-gpio = <&pca9554 5 GPIO_ACTIVE_HIGH>;
			num-modes = <4>;
			modes-map = <NS_V2_LED_SATA 0 0
				     NS_V2_LED_OFF  0 1
				     NS_V2_LED_ON   1 0
				     NS_V2_LED_ON   1 1>;
		};
	};

	gpio-fan {
		gpio-fan,speed-map =
			<   0 3
			  800 2
			  1050 1
			  1300 0>;
	};
};

&pciec {
	/* SATA AHCI controller 88SE9170 */
	pcie@1,0 {
		status = "okay";
	};
};

&mdio {
	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};