code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SM8250 TLMM block

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in the Qualcomm SM8250 SoC.

properties:
  compatible:
    const: qcom,sm8250-pinctrl

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: west
      - const: south
      - const: north

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 90

  gpio-line-names:
    maxItems: 180

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm8250-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm8250-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sm8250-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
            - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
                ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
                ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
                mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
                mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
                mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
                pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
                pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
                qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
                qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
                qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
                sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
                tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
                tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
                tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

required:
  - compatible
  - reg
  - reg-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl@1f00000 {
        compatible = "qcom,sm8250-pinctrl";
        reg = <0x0f100000 0x300000>,
              <0x0f500000 0x300000>,
              <0x0f900000 0x300000>;
        reg-names = "west", "south", "north";
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 180>;
        wakeup-parent = <&pdc>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SM8350 TLMM block

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SM8350 SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sm8350-tlmm

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true
  gpio-reserved-ranges: true
  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

required:
  - compatible
  - reg

additionalProperties: false

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm8350-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm8350-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sm8350-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$"
            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.

        enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
                cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
                ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
                gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
                mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
                mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck,
                mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
                mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
                mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
                mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator,
                pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk,
                pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
                qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
                qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0,
                qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10,
                qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19,
                qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5,
                qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
                sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
                tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
                uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present,
                uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl@f100000 {
        compatible = "qcom,sm8350-tlmm";
        reg = <0x0f100000 0x300000>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&tlmm 0 0 203>;

        gpio-wo-subnode-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-subnodes-state {
            rx-pins {
                pins = "gpio18";
                function = "qup3";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio19";
                function = "qup3";
                bias-disable;
            };
        };
    };
...

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8450 SoC LPASS LPI TLMM

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description:
  Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
  (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.

properties:
  compatible:
    const: qcom,sm8450-lpass-lpi-pinctrl

  reg:
    items:
      - description: LPASS LPI TLMM Control and Status registers
      - description: LPASS LPI pins SLEW registers

  clocks:
    items:
      - description: LPASS Core voting clock
      - description: LPASS Audio voting clock

  clock-names:
    items:
      - const: core
      - const: audio

  gpio-controller: true

  "#gpio-cells":
    description: Specifying the pin number and flags, as defined in
      include/dt-bindings/gpio/gpio.h
    const: 2

  gpio-ranges:
    maxItems: 1

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm8450-lpass-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm8450-lpass-state"
        additionalProperties: false

$defs:
  qcom-sm8450-lpass-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: /schemas/pinctrl/pincfg-node.yaml

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          pattern: "^gpio([0-9]|[1-2][0-9])$"

      function:
        enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
                dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
                dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
                qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
                i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
                wsa2_swr_data, i2s2_data, i2s4_ws, i2s4_clk, i2s4_data,
                slimbus_clk, i2s3_clk, i2s3_ws, i2s3_data, slimbus_data,
                ext_mclk1_c, ext_mclk1_b, ext_mclk1_a, ext_mclk1_d,
                ext_mclk1_e ]
        description:
          Specify the alternative function to be configured for the specified
          pins.

      drive-strength:
        enum: [2, 4, 6, 8, 10, 12, 14, 16]
        default: 2
        description:
          Selects the drive strength for the specified pins, in mA.

      slew-rate:
        enum: [0, 1, 2, 3]
        default: 0
        description: |
          0: No adjustments
          1: Higher Slew rate (faster edges)
          2: Lower Slew rate (slower edges)
          3: Reserved (No adjustments)

      bias-pull-down: true

      bias-pull-up: true

      bias-disable: true

      output-high: true

      output-low: true

    required:
      - pins
      - function

    additionalProperties: false

allOf:
  - $ref: pinctrl.yaml#

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - gpio-controller
  - "#gpio-cells"
  - gpio-ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/sound/qcom,q6afe.h>
    pinctrl@3440000 {
        compatible = "qcom,sm8450-lpass-lpi-pinctrl";
        reg = <0x3440000 0x20000>,
              <0x34d0000 0x10000>;
        clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
        clock-names = "core", "audio";
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&lpi_tlmm 0 0 23>;

        wsa-swr-active-state {
            clk-pins {
                pins = "gpio10";
                function = "wsa_swr_clk";
                drive-strength = <2>;
                slew-rate = <1>;
                bias-disable;
            };

            data-pins {
                pins = "gpio11";
                function = "wsa_swr_data";
                drive-strength = <2>;
                slew-rate = <1>;
            };
        };

        tx-swr-sleep-clk-state {
            pins = "gpio0";
            function = "swr_tx_clk";
            drive-strength = <2>;
            bias-pull-down;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SM8450 TLMM block

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm SM8450 SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,sm8450-tlmm

  reg:
    maxItems: 1

  interrupts: true
  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 105

  gpio-line-names:
    maxItems: 209

  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

required:
  - compatible
  - reg

additionalProperties: false

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-sm8450-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-sm8450-tlmm-state"
        additionalProperties: false

$defs:
  qcom-sm8450-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.
        enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
                cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
                ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3,
                gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1,
                mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck,
                mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
                mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
                mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
                mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn,
                pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s,
                prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request,
                qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss,
                qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
                qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11,
                qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2,
                qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4,
                qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
                sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
                tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
                tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
                uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,
                usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]

      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl@f100000 {
        compatible = "qcom,sm8450-tlmm";
        reg = <0x0f100000 0x300000>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&tlmm 0 0 211>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

        gpio-wo-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-state {
            rx-pins {
                pins = "gpio26";
                function = "qup7";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio27";
                function = "qup7";
                bias-disable;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,tlmm-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. Top Level Mode Multiplexer (TLMM) definitions

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  This defines the common properties used to describe all Qualcomm Top Level
  Mode Multiplexer bindings and pinconf/pinmux states for these.

properties:
  interrupts:
    description:
      Specifies the TLMM summary IRQ
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    description:
      Specifies the PIN numbers and Flags, as defined in defined in
      include/dt-bindings/interrupt-controller/irq.h
    const: 2

  gpio-controller: true

  '#gpio-cells':
    description:
      Specifying the pin number and flags, as defined in
      include/dt-bindings/gpio/gpio.h
    const: 2

  gpio-ranges:
    maxItems: 1

  wakeup-parent:
    description:
      Specifying the interrupt-controller used to wake up the system when the
      TLMM block has been powered down.

  gpio-reserved-ranges:
    description:
      Pins can be reserved for trusted applications and thereby unaccessible
      from the OS.  This property can be used to mark the pins which resources
      should not be accessed by the OS. Please see the ../gpio/gpio.txt for more
      information.

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges

additionalProperties: true

$defs:
  qcom-tlmm-state:
    properties:
      drive-strength:
        enum: [2, 4, 6, 8, 10, 12, 14, 16]
        description:
          Selects the drive strength for the specified pins, in mA.

      bias-pull-down: true
      bias-pull-up: true
      bias-disable: true
      input-enable: true
      output-high: true
      output-low: true

    allOf:
      - $ref: pincfg-node.yaml#
      - $ref: pinmux-node.yaml#

      - if:
          properties:
            pins:
              items:
                pattern: "^gpio"
        then:
          required:
            - function
        else:
          properties:
            function: false

    additionalProperties: true
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ralink,mt7620-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ralink MT7620 Pin Controller

maintainers:
  - Arınç ÜNAL <arinc.unal@arinc9.com>
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

description:
  Ralink MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs.
  The pin controller can only set the muxing of pin groups. Muxing individual
  pins is not supported. There is no pinconf support.

properties:
  compatible:
    const: ralink,mt7620-pinctrl

patternProperties:
  '-pins$':
    type: object
    patternProperties:
      '^(.*-)?pinmux$':
        type: object
        description: node for pinctrl.
        $ref: pinmux-node.yaml#

        properties:
          groups:
            description: The pin group to select.
            enum: [
              # common
              i2c, spi, wdt,

              # For MT7620 SoC
              ephy, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi refclk,
              uartf, uartlite, wled,

              # For MT7628 and MT7688 SoCs
              gpio, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an,
              p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, perst, pwm0,
              pwm1, refclk, sdmode, spi cs1, spis, uart0, uart1, uart2,
              wled_an, wled_kn,
            ]

          function:
            description: The mux function to select.
            enum: [
              # common
              gpio, i2c, refclk, spi,

              # For MT7620 SoC
              ephy, gpio i2s, gpio uartf, i2s uartf, mdio, nand, pa,
              pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf,
              rgmii1, rgmii2, sd, spi refclk, uartf, uartlite, wdt refclk,
              wdt rst, wled,

              # For MT7628 and MT7688 SoCs
              antenna, debug, i2s, jtag, p0led_an, p0led_kn,
              p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn,
              p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2,
              rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi cs1,
              spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -,
            ]

        required:
          - groups
          - function

        additionalProperties: false

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    pinctrl {
      compatible = "ralink,mt7620-pinctrl";

      i2c_pins: i2c0-pins {
        pinmux {
          groups = "i2c";
          function = "i2c";
        };
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ralink,mt7621-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ralink MT7621 Pin Controller

maintainers:
  - Arınç ÜNAL <arinc.unal@arinc9.com>
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

description:
  Ralink MT7621 pin controller for MT7621 SoC.
  The pin controller can only set the muxing of pin groups. Muxing individual
  pins is not supported. There is no pinconf support.

properties:
  compatible:
    const: ralink,mt7621-pinctrl

patternProperties:
  '-pins$':
    type: object
    patternProperties:
      '^(.*-)?pinmux$':
        type: object
        description: node for pinctrl.
        $ref: pinmux-node.yaml#

        properties:
          groups:
            description: The pin group to select.
            enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, uart1,
                   uart2, uart3, wdt]

          function:
            description: The mux function to select.
            enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk,
                   pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, spi,
                   uart1, uart2, uart3, wdt refclk, wdt rst]

        required:
          - groups
          - function

        additionalProperties: false

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    pinctrl {
      compatible = "ralink,mt7621-pinctrl";

      i2c_pins: i2c0-pins {
        pinmux {
          groups = "i2c";
          function = "i2c";
        };
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ralink RT2880 Pin Controller

maintainers:
  - Arınç ÜNAL <arinc.unal@arinc9.com>
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

description:
  Ralink RT2880 pin controller for RT2880 SoC.
  The pin controller can only set the muxing of pin groups. Muxing individual
  pins is not supported. There is no pinconf support.

properties:
  compatible:
    const: ralink,rt2880-pinctrl

patternProperties:
  '-pins$':
    type: object
    patternProperties:
      '^(.*-)?pinmux$':
        type: object
        description: node for pinctrl.
        $ref: pinmux-node.yaml#

        properties:
          groups:
            description: The pin group to select.
            enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci]

          function:
            description: The mux function to select.
            enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci]

        required:
          - groups
          - function

        additionalProperties: false

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    pinctrl {
      compatible = "ralink,rt2880-pinctrl";

      i2c_pins: i2c0-pins {
        pinmux {
          groups = "i2c";
          function = "i2c";
        };
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ralink RT305X Pin Controller

maintainers:
  - Arınç ÜNAL <arinc.unal@arinc9.com>
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

description:
  Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350
  SoCs.
  The pin controller can only set the muxing of pin groups. Muxing individual
  pins is not supported. There is no pinconf support.

properties:
  compatible:
    const: ralink,rt305x-pinctrl

patternProperties:
  '-pins$':
    type: object
    patternProperties:
      '^(.*-)?pinmux$':
        type: object
        description: node for pinctrl.
        $ref: pinmux-node.yaml#

        properties:
          groups:
            description: The pin group to select.
            enum: [
              # common
              i2c, jtag, led, mdio, rgmii, spi, spi_cs1, uartf, uartlite,

              # For RT3050, RT3052 and RT3350 SoCs
              sdram,

              # For RT3352 SoC
              lna, pa
            ]

          function:
            description: The mux function to select.
            enum: [
              # common
              gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, mdio,
              pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, uartf,
              uartlite, wdg_cs1,

              # For RT3050, RT3052 and RT3350 SoCs
              sdram,

              # For RT3352 SoC
              lna, pa
            ]

        required:
          - groups
          - function

        additionalProperties: false

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    pinctrl {
      compatible = "ralink,rt305x-pinctrl";

      i2c_pins: i2c0-pins {
        pinmux {
          groups = "i2c";
          function = "i2c";
        };
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ralink,rt3883-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ralink RT3883 Pin Controller

maintainers:
  - Arınç ÜNAL <arinc.unal@arinc9.com>
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

description:
  Ralink RT3883 pin controller for RT3883 SoC.
  The pin controller can only set the muxing of pin groups. Muxing individual
  pins is not supported. There is no pinconf support.

properties:
  compatible:
    const: ralink,rt3883-pinctrl

patternProperties:
  '-pins$':
    type: object
    patternProperties:
      '^(.*-)?pinmux$':
        type: object
        description: node for pinctrl.
        $ref: pinmux-node.yaml#

        properties:
          groups:
            description: The pin group to select.
            enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi, uartf,
                   uartlite]

          function:
            description: The mux function to select.
            enum: [ge1, ge2, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag,
                   lna a, lna g, mdio, pci-dev, pci-fnc, pci-host1, pci-host2,
                   pcm gpio, pcm i2s, pcm uartf, spi, uartf, uartlite]

        required:
          - groups
          - function

        additionalProperties: false

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    pinctrl {
      compatible = "ralink,rt3883-pinctrl";

      i2c_pins: i2c0-pins {
        pinmux {
          groups = "i2c";
          function = "i2c";
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,pfc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Pin Function Controller (GPIO and Pin Mux/Config)

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

description:
  The Pin Function Controller (PFC) is a Pin Mux/Config controller.
  On SH/R-Mobile SoCs it also acts as a GPIO controller.

properties:
  compatible:
    enum:
      - renesas,pfc-emev2       # EMMA Mobile EV2
      - renesas,pfc-r8a73a4     # R-Mobile APE6
      - renesas,pfc-r8a7740     # R-Mobile A1
      - renesas,pfc-r8a7742     # RZ/G1H
      - renesas,pfc-r8a7743     # RZ/G1M
      - renesas,pfc-r8a7744     # RZ/G1N
      - renesas,pfc-r8a7745     # RZ/G1E
      - renesas,pfc-r8a77470    # RZ/G1C
      - renesas,pfc-r8a774a1    # RZ/G2M
      - renesas,pfc-r8a774b1    # RZ/G2N
      - renesas,pfc-r8a774c0    # RZ/G2E
      - renesas,pfc-r8a774e1    # RZ/G2H
      - renesas,pfc-r8a7778     # R-Car M1
      - renesas,pfc-r8a7779     # R-Car H1
      - renesas,pfc-r8a7790     # R-Car H2
      - renesas,pfc-r8a7791     # R-Car M2-W
      - renesas,pfc-r8a7792     # R-Car V2H
      - renesas,pfc-r8a7793     # R-Car M2-N
      - renesas,pfc-r8a7794     # R-Car E2
      - renesas,pfc-r8a7795     # R-Car H3
      - renesas,pfc-r8a7796     # R-Car M3-W
      - renesas,pfc-r8a77961    # R-Car M3-W+
      - renesas,pfc-r8a77965    # R-Car M3-N
      - renesas,pfc-r8a77970    # R-Car V3M
      - renesas,pfc-r8a77980    # R-Car V3H
      - renesas,pfc-r8a77990    # R-Car E3
      - renesas,pfc-r8a77995    # R-Car D3
      - renesas,pfc-r8a779a0    # R-Car V3U
      - renesas,pfc-r8a779f0    # R-Car S4-8
      - renesas,pfc-r8a779g0    # R-Car V4H
      - renesas,pfc-sh73a0      # SH-Mobile AG5

  reg:
    minItems: 1
    maxItems: 10

  gpio-controller: true

  '#gpio-cells':
    const: 2

  gpio-ranges:
    minItems: 1
    maxItems: 16

  interrupts-extended:
    minItems: 32
    maxItems: 64
    description:
      Specify the interrupts associated with external IRQ pins on SoCs where
      the PFC acts as a GPIO controller.  It must contain one interrupt per
      external IRQ, sorted by external IRQ number.

  power-domains:
    maxItems: 1

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

if:
  properties:
    compatible:
      enum:
        - renesas,pfc-r8a73a4
        - renesas,pfc-r8a7740
        - renesas,pfc-sh73a0
then:
  required:
    - interrupts-extended
    - gpio-controller
    - '#gpio-cells'
    - gpio-ranges
    - power-domains

additionalProperties:
  anyOf:
    - type: object
      allOf:
        - $ref: pincfg-node.yaml#
        - $ref: pinmux-node.yaml#

      description:
        Pin controller client devices use pin configuration subnodes (children
        and grandchildren) for desired pin configuration.
        Client device subnodes use below standard properties.

      properties:
        phandle: true
        function: true
        groups: true
        pins: true
        bias-disable: true
        bias-pull-down: true
        bias-pull-up: true
        drive-strength:
          enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset of supported values
        power-source:
          enum: [ 1800, 3300 ]
        gpio-hog: true
        gpios: true
        input: true
        output-high: true
        output-low: true

      additionalProperties: false

    - type: object
      properties:
        phandle: true

      additionalProperties:
        $ref: "#/additionalProperties/anyOf/0"

examples:
  - |
    pfc: pinctrl@e6050000 {
            compatible = "renesas,pfc-r8a7740";
            reg = <0xe6050000 0x8000>,
                  <0xe605800c 0x20>;
            gpio-controller;
            #gpio-cells = <2>;
            gpio-ranges = <&pfc 0 0 212>;
            interrupts-extended =
                <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
                <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
                <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
                <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
                <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
                <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
                <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
                <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
            power-domains = <&pd_c5>;

            lcd0-mux-hog {
                    /* DBGMD/LCDC0/FSIA MUX */
                    gpio-hog;
                    gpios = <176 0>;
                    output-high;
            };
    };

  - |
    pinctrl@e6060000 {
            compatible = "renesas,pfc-r8a7795";
            reg = <0xe6060000 0x50c>;

            avb_pins: avb {
                    mux {
                            groups = "avb_link", "avb_mdio", "avb_mii";
                            function = "avb";
                    };

                    pins_mdio {
                            groups = "avb_mdio";
                            drive-strength = <24>;
                    };

                    pins_mii_tx {
                            pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC",
                                   "PIN_AVB_TD0", "PIN_AVB_TD1", "PIN_AVB_TD2",
                                   "PIN_AVB_TD3";
                            drive-strength = <12>;
                    };
            };

            keys_pins: keys {
                    pins = "GP_5_17", "GP_5_20", "GP_5_22", "GP_2_1";
                    bias-pull-up;
            };

            sdhi0_pins: sd0 {
                    groups = "sdhi0_data4", "sdhi0_ctrl";
                    function = "sdhi0";
                    power-source = <3300>;
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/A1 combined Pin and GPIO controller

maintainers:
  - Jacopo Mondi <jacopo+renesas@jmondi.org>
  - Geert Uytterhoeven <geert+renesas@glider.be>

description:
  The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
  controller, named "Ports" in the hardware reference manual.
  Pin multiplexing and GPIO configuration is performed on a per-pin basis
  writing configuration values to per-port register sets.
  Each "port" features up to 16 pins, each of them configurable for GPIO
  function (port mode) or in alternate function mode.
  Up to 8 different alternate function modes exist for each single pin.

properties:
  compatible:
    oneOf:
      - const: renesas,r7s72100-ports     # RZ/A1H
      - items:
          - const: renesas,r7s72101-ports # RZ/A1M
          - const: renesas,r7s72100-ports # fallback
      - const: renesas,r7s72102-ports     # RZ/A1L

  reg:
    maxItems: 1

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

patternProperties:
  "^gpio-[0-9]*$":
    type: object
    additionalProperties: false

    description:
      Each port of the r7s72100 pin controller hardware is itself a GPIO
      controller.
      Different SoCs have different numbers of available pins per port, but
      generally speaking, each of them can be configured in GPIO ("port") mode
      on this hardware.
      Describe GPIO controllers using sub-nodes with the following properties.

    properties:
      gpio-controller: true

      '#gpio-cells':
        const: 2

      gpio-ranges:
        maxItems: 1

    required:
      - gpio-controller
      - '#gpio-cells'
      - gpio-ranges

additionalProperties:
  anyOf:
    - type: object
      allOf:
        - $ref: pincfg-node.yaml#
        - $ref: pinmux-node.yaml#

      description:
        A pin multiplexing sub-node describes how to configure a set of (or a
        single) pin in some desired alternate function mode.
        A single sub-node may define several pin configurations.
        A few alternate function require special pin configuration flags to be
        supplied along with the alternate function configuration number.
        The hardware reference manual specifies when a pin function requires
        "software IO driven" mode to be specified. To do so use the generic
        properties from the <include/linux/pinctrl/pinconf_generic.h> header
        file to instruct the pin controller to perform the desired pin
        configuration operation.
        The hardware reference manual specifies when a pin has to be configured
        to work in bi-directional mode and when the IO direction has to be
        specified by software. Bi-directional pins must be managed by the pin
        controller driver internally, while software driven IO direction has to
        be explicitly selected when multiple options are available.

      properties:
        pinmux:
          description: |
            Integer array representing pin number and pin multiplexing
            configuration.
            When a pin has to be configured in alternate function mode, use
            this property to identify the pin by its global index, and provide
            its alternate function configuration number along with it.
            When multiple pins are required to be configured as part of the
            same alternate function they shall be specified as members of the
            same argument list of a single "pinmux" property.
            Helper macros to ease assembling the pin index from its position
            (port where it sits on and pin number) and alternate function
            identifier are provided by the pin controller header file at:
            <include/dt-bindings/pinctrl/r7s72100-pinctrl.h>
            Integers values in "pinmux" argument list are assembled as:
            ((PORT * 16 + PIN) | MUX_FUNC << 16)

        phandle: true
        input-enable: true
        output-enable: true

      required:
        - pinmux

      additionalProperties: false

    - type: object
      properties:
        phandle: true

      additionalProperties:
        $ref: "#/additionalProperties/anyOf/0"

examples:
  - |
    #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
    pinctrl: pinctrl@fcfe3000 {
            compatible = "renesas,r7s72100-ports";

            reg = <0xfcfe3000 0x4230>;

            /*
             * A GPIO controller node, controlling 16 pins indexed from 0.
             * The GPIO controller base in the global pin indexing space is pin
             * 48, thus pins [0 - 15] on this controller map to pins [48 - 63]
             * in the global pin indexing space.
             */
            port3: gpio-3 {
                    gpio-controller;
                    #gpio-cells = <2>;
                    gpio-ranges = <&pinctrl 0 48 16>;
            };

            /*
             * A serial communication interface with a TX output pin and an RX
             * input pin.
             * Pin #0 on port #3 is configured as alternate function #6.
             * Pin #2 on port #3 is configured as alternate function #4.
             */
            scif2_pins: serial2 {
                    pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
            };

            /*
             * I2c master: both SDA and SCL pins need bi-directional operations
             * Pin #4 on port #1 is configured as alternate function #1.
             * Pin #5 on port #1 is configured as alternate function #1.
             * Both need to work in bi-directional mode, the driver must manage
             * this internally.
             */
            i2c2_pins: i2c2 {
                    pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
            };

            /*
             * Multi-function timer input and output compare pins.
             */
            tioc0_pins: tioc0 {
                    /*
                     * Configure TIOC0A as software driven input
                     * Pin #0 on port #4 is configured as alternate function #2
                     * with IO direction specified by software as input.
                     */
                    tioc0_input_pins {
                            pinmux = <RZA1_PINMUX(4, 0, 2)>;
                            input-enable;
                    };

                    /*
                     * Configure TIOC0B as software driven output
                     * Pin #1 on port #4 is configured as alternate function #1
                     * with IO direction specified by software as output.
                     */
                    tioc0_output_pins {
                            pinmux = <RZA1_PINMUX(4, 1, 1)>;
                            output-enable;
                    };
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/A2 combined Pin and GPIO controller

maintainers:
  - Chris Brandt <chris.brandt@renesas.com>
  - Geert Uytterhoeven <geert+renesas@glider.be>

description:
  The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
  controller.
  Pin multiplexing and GPIO configuration is performed on a per-pin basis.
  Each port features up to 8 pins, each of them configurable for GPIO function
  (port mode) or in alternate function mode.
  Up to 8 different alternate function modes exist for each single pin.

properties:
  compatible:
    const: "renesas,r7s9210-pinctrl" # RZ/A2M

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2
    description:
      The first cell contains the global GPIO port index, constructed using the
      RZA2_PIN() helper macro in r7s9210-pinctrl.h.
      E.g. "RZA2_PIN(PORT6, 0)" for P6_0.

  gpio-ranges:
    maxItems: 1

patternProperties:
  "^.*$":
    if:
      type: object
    then:
      allOf:
        - $ref: pincfg-node.yaml#
        - $ref: pinmux-node.yaml#
      description:
        The child nodes of the pin controller designate pins to be used for
        specific peripheral functions or as GPIO.

        A pin multiplexing sub-node describes how to configure a set of
        (or a single) pin in some desired alternate function mode.
        The values for the pinmux properties are a combination of port name,
        pin number and the desired function index. Use the RZA2_PINMUX macro
        located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily
        define these.
        For assigning GPIO pins, use the macro RZA2_PIN also in
        to express the desired port pin.

      properties:
        phandle: true

        pinmux:
          description:
            Values are constructed from GPIO port number, pin number, and
            alternate function configuration number using the RZA2_PINMUX()
            helper macro in r7s9210-pinctrl.h.

      required:
        - pinmux

      additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
    pinctrl: pinctrl@fcffe000 {
            compatible = "renesas,r7s9210-pinctrl";
            reg = <0xfcffe000 0x1000>;

            gpio-controller;
            #gpio-cells = <2>;
            gpio-ranges = <&pinctrl 0 0 176>;

            /* Serial Console */
            scif4_pins: serial4 {
                    pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
                             <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

description:
  The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
  GPIO controller.
  Pin multiplexing and GPIO configuration is performed on a per-pin basis.
  Each port features up to 8 pins, each of them configurable for GPIO function
  (port mode) or in alternate function mode.
  Up to 8 different alternate function modes exist for each single pin.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}

      - items:
          - enum:
              - renesas,r9a07g054-pinctrl     # RZ/V2L
          - const: renesas,r9a07g044-pinctrl  # RZ/G2{L,LC} fallback for RZ/V2L

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2
    description:
      The first cell contains the global GPIO port index, constructed using the
      RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
      second cell represents consumer flag as mentioned in ../gpio/gpio.txt
      E.g. "RZG2L_GPIO(39, 1)" for P39_1.

  gpio-ranges:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2
    description:
      The first cell contains the global GPIO port index, constructed using the
      RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
      second cell is used to specify the flag.
      E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is
      being used as an interrupt.

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    items:
      - description: GPIO_RSTN signal
      - description: GPIO_PORT_RESETN signal
      - description: GPIO_SPARE_RESETN signal

additionalProperties:
  anyOf:
    - type: object
      allOf:
        - $ref: pincfg-node.yaml#
        - $ref: pinmux-node.yaml#

      description:
        Pin controller client devices use pin configuration subnodes (children
        and grandchildren) for desired pin configuration.
        Client device subnodes use below standard properties.

      properties:
        phandle: true
        pinmux:
          description:
            Values are constructed from GPIO port number, pin number, and
            alternate function configuration number using the RZG2L_PORT_PINMUX()
            helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
        pins: true
        drive-strength:
          enum: [ 2, 4, 8, 12 ]
        output-impedance-ohms:
          enum: [ 33, 50, 66, 100 ]
        power-source:
          description: I/O voltage in millivolt.
          enum: [ 1800, 2500, 3300 ]
        slew-rate: true
        gpio-hog: true
        gpios: true
        input-enable: true
        output-high: true
        output-low: true
        line-name: true

    - type: object
      properties:
        phandle: true

      additionalProperties:
        $ref: "#/additionalProperties/anyOf/0"

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges
  - interrupt-controller
  - '#interrupt-cells'
  - clocks
  - power-domains
  - resets

examples:
  - |
    #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
    #include <dt-bindings/clock/r9a07g044-cpg.h>

    pinctrl: pinctrl@11030000 {
            compatible = "renesas,r9a07g044-pinctrl";
            reg = <0x11030000 0x10000>;

            gpio-controller;
            #gpio-cells = <2>;
            gpio-ranges = <&pinctrl 0 0 392>;
            interrupt-controller;
            #interrupt-cells = <2>;
            clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
            resets = <&cpg R9A07G044_GPIO_RSTN>,
                     <&cpg R9A07G044_GPIO_PORT_RESETN>,
                     <&cpg R9A07G044_GPIO_SPARE_RESETN>;
            power-domains = <&cpg>;

            scif0_pins: serial0 {
                    pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
                             <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
            };

            i2c1_pins: i2c1 {
                    pins = "RIIC1_SDA", "RIIC1_SCL";
                    input-enable;
            };

            sd1-pwr-en-hog {
                    gpio-hog;
                    gpios = <RZG2L_GPIO(39, 2) 0>;
                    output-high;
                    line-name = "sd1_pwr_en";
            };

            sdhi1_pins: sd1 {
                    sd1_mux {
                            pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
                                     <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
                            power-source  = <3300>;
                    };

                    sd1_data {
                            pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
                            power-source  = <3300>;
                    };

                    sd1_ctrl {
                            pins = "SD1_CLK", "SD1_CMD";
                            power-source  = <3300>;
                    };
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/N1 Pin Controller

maintainers:
  - Gareth Williams <gareth.williams.jx@renesas.com>
  - Geert Uytterhoeven <geert+renesas@glider.be>

properties:
  compatible:
    items:
      - enum:
          - renesas,r9a06g032-pinctrl # RZ/N1D
          - renesas,r9a06g033-pinctrl # RZ/N1S
      - const: renesas,rzn1-pinctrl   # Generic RZ/N1

  reg:
    items:
      - description: GPIO Multiplexing Level1 Register Block
      - description: GPIO Multiplexing Level2 Register Block

  clocks:
    maxItems: 1

  clock-names:
    const: bus
    description:
      The bus clock, sometimes described as pclk, for register accesses.

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - clocks
  - clock-names

additionalProperties:
  anyOf:
    - type: object
      allOf:
        - $ref: pincfg-node.yaml#
        - $ref: pinmux-node.yaml#

      description:
        A pin multiplexing sub-node describes how to configure a set of (or a
        single) pin in some desired alternate function mode.
        A single sub-node may define several pin configurations.

      properties:
        pinmux:
          description: |
            Integer array representing pin number and pin multiplexing
            configuration.
            When a pin has to be configured in alternate function mode, use
            this property to identify the pin by its global index, and provide
            its alternate function configuration number along with it.
            When multiple pins are required to be configured as part of the
            same alternate function they shall be specified as members of the
            same argument list of a single "pinmux" property.
            Integers values in the "pinmux" argument list are assembled as:
            (PIN | MUX_FUNC << 8)
            where PIN directly corresponds to the pl_gpio pin number and
            MUX_FUNC is one of the alternate function identifiers defined in:
            <include/dt-bindings/pinctrl/rzn1-pinctrl.h>
            These identifiers collapse the IO Multiplex Configuration Level 1
            and Level 2 numbers that are detailed in the hardware reference
            manual into a single number. The identifiers for Level 2 are simply
            offset by 10.  Additional identifiers are provided to specify the
            MDIO source peripheral.

        phandle: true
        bias-disable: true
        bias-pull-up:
          description: Pull up the pin with 50 kOhm
        bias-pull-down:
          description: Pull down the pin with 50 kOhm
        bias-high-impedance: true
        drive-strength:
          enum: [ 4, 6, 8, 12 ]

      required:
        - pinmux

      additionalProperties:
        $ref: "#/additionalProperties/anyOf/0"

    - type: object
      properties:
        phandle: true

      additionalProperties:
        $ref: "#/additionalProperties/anyOf/0"

examples:
  - |
    #include <dt-bindings/clock/r9a06g032-sysctrl.h>
    #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
    pinctrl: pinctrl@40067000 {
            compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
            reg = <0x40067000 0x1000>, <0x51000000 0x480>;
            clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
            clock-names = "bus";

            /*
             * A serial communication interface with a TX output pin and an RX
             * input pin.
             */
            pins_uart0: pins_uart0 {
                    pinmux = <
                            RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
                            RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
                    >;
            };

            /*
             * Set the pull-up on the RXD pin of the UART.
             */
            pins_uart0_alt: pins_uart0_alt {
                    pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>;

                    pins_uart6_rx {
                            pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;
                            bias-pull-up;
                    };
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/V2M combined Pin and GPIO controller

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>
  - Phil Edworthy <phil.edworthy@renesas.com>

description:
  The Renesas RZ/V2M SoC features a combined Pin and GPIO controller.
  Pin multiplexing and GPIO configuration is performed on a per-pin basis.
  Each port features up to 16 pins, each of them configurable for GPIO function
  (port mode) or in alternate function mode.
  Up to 8 different alternate function modes exist for each single pin.

properties:
  compatible:
    const: renesas,r9a09g011-pinctrl # RZ/V2M

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2
    description:
      The first cell contains the global GPIO port index, constructed using the
      RZV2M_GPIO() helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h> and the
      second cell represents consumer flag as mentioned in ../gpio/gpio.txt
      E.g. "RZV2M_GPIO(8, 1)" for P8_1.

  gpio-ranges:
    maxItems: 1

  interrupts:
    description: INEXINT[0..38] corresponding to individual pin inputs.
    maxItems: 39

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

additionalProperties:
  anyOf:
    - type: object
      allOf:
        - $ref: pincfg-node.yaml#
        - $ref: pinmux-node.yaml#

      description:
        Pin controller client devices use pin configuration subnodes (children
        and grandchildren) for desired pin configuration.
        Client device subnodes use below standard properties.

      properties:
        phandle: true
        pinmux:
          description:
            Values are constructed from GPIO port number, pin number, and
            alternate function configuration number using the RZV2M_PORT_PINMUX()
            helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h>.
        pins: true
        bias-disable: true
        bias-pull-down: true
        bias-pull-up: true
        drive-strength-microamp:
          # Superset of supported values
          enum: [ 1600, 1800, 2000, 3200, 3800, 4000, 6400, 7800, 8000,
                  9000, 9600, 11000, 12000, 13000, 18000 ]
        slew-rate:
          description: 0 is slow slew rate, 1 is fast slew rate
          enum: [ 0, 1 ]
        gpio-hog: true
        gpios: true
        output-high: true
        output-low: true
        line-name: true

    - type: object
      properties:
        phandle: true

      additionalProperties:
        $ref: "#/additionalProperties/anyOf/0"

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges
  - interrupts
  - clocks
  - power-domains
  - resets

examples:
  - |
    #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
    #include <dt-bindings/clock/r9a09g011-cpg.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pinctrl: pinctrl@b6250000 {
            compatible = "renesas,r9a09g011-pinctrl";
            reg = <0xb6250000 0x800>;

            gpio-controller;
            #gpio-cells = <2>;
            gpio-ranges = <&pinctrl 0 0 352>;
            interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
            resets = <&cpg R9A09G011_PFC_PRESETN>;
            power-domains = <&cpg>;

            i2c2_pins: i2c2 {
                    pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */
                             <RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */
            };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip Pinmux Controller

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The Rockchip Pinmux Controller enables the IC to share one PAD
  to several functional blocks. The sharing is done by multiplexing
  the PAD input/output signals. For each PAD there are several muxing
  options with option 0 being used as a GPIO.

  Please refer to pinctrl-bindings.txt in this directory for details of the
  common pinctrl bindings used by client devices, including the meaning of the
  phrase "pin configuration node".

  The Rockchip pin configuration node is a node of a group of pins which can be
  used for a specific device or function. This node represents both mux and
  config of the pins in that group. The 'pins' selects the function mode
  (also named pin mode) this pin can work on and the 'config' configures
  various pad settings such as pull-up, etc.

  The pins are grouped into up to 9 individual pin banks which need to be
  defined as gpio sub-nodes of the pinmux controller.

properties:
  compatible:
    enum:
      - rockchip,px30-pinctrl
      - rockchip,rk2928-pinctrl
      - rockchip,rk3036-pinctrl
      - rockchip,rk3066a-pinctrl
      - rockchip,rk3066b-pinctrl
      - rockchip,rk3128-pinctrl
      - rockchip,rk3188-pinctrl
      - rockchip,rk3228-pinctrl
      - rockchip,rk3288-pinctrl
      - rockchip,rk3308-pinctrl
      - rockchip,rk3328-pinctrl
      - rockchip,rk3368-pinctrl
      - rockchip,rk3399-pinctrl
      - rockchip,rk3568-pinctrl
      - rockchip,rk3588-pinctrl
      - rockchip,rv1108-pinctrl
      - rockchip,rv1126-pinctrl

  rockchip,grf:
    $ref: "/schemas/types.yaml#/definitions/phandle"
    description:
      The phandle of the syscon node for the GRF registers.

  rockchip,pmu:
    $ref: "/schemas/types.yaml#/definitions/phandle"
    description:
      The phandle of the syscon node for the PMU registers,
      as some SoCs carry parts of the iomux controller registers there.
      Required for at least rk3188 and rk3288. On the rk3368 this should
      point to the PMUGRF syscon.

  "#address-cells":
    enum: [1, 2]

  "#size-cells":
    enum: [1, 2]

  ranges: true

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - rockchip,grf
  - "#address-cells"
  - "#size-cells"
  - ranges

patternProperties:
  "gpio@[0-9a-f]+$":
    type: object

    $ref: "/schemas/gpio/rockchip,gpio-bank.yaml#"

    unevaluatedProperties: false

  "pcfg-[a-z0-9-]+$":
    type: object
    properties:
      bias-disable: true

      bias-pull-down: true

      bias-pull-pin-default: true

      bias-pull-up: true

      drive-strength:
        minimum: 0
        maximum: 20

      input-enable: true

      input-schmitt-enable: true

      output-high: true

      output-low: true

    additionalProperties: false

additionalProperties:
  type: object
  additionalProperties:
    type: object
    properties:
      rockchip,pins:
        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
        minItems: 1
        items:
          items:
            - minimum: 0
              maximum: 8
              description:
                Pin bank.
            - minimum: 0
              maximum: 31
              description:
                Pin bank index.
            - minimum: 0
              maximum: 13
              description:
                Mux 0 means GPIO and mux 1 to N means
                the specific device function.
            - description:
                The phandle of a node contains the generic pinconfig options
                to use as described in pinctrl-bindings.txt.

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/pinctrl/rockchip.h>

    pinctrl: pinctrl {
      compatible = "rockchip,rk3066a-pinctrl";
      rockchip,grf = <&grf>;

      #address-cells = <1>;
      #size-cells = <1>;
      ranges;

      gpio0: gpio@20034000 {
        compatible = "rockchip,gpio-bank";
        reg = <0x20034000 0x100>;
        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk_gates8 9>;

        gpio-controller;
        #gpio-cells = <2>;

        interrupt-controller;
        #interrupt-cells = <2>;
      };

      pcfg_pull_default: pcfg-pull-default {
        bias-pull-pin-default;
      };

      uart2 {
        uart2_xfer: uart2-xfer {
          rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
                          <1 RK_PB1 1 &pcfg_pull_default>;
        };
      };
    };

    uart2: serial@20064000 {
      compatible = "snps,dw-apb-uart";
      reg = <0x20064000 0x400>;
      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&mux_uart2>;
      pinctrl-0 = <&uart2_xfer>;
      pinctrl-names = "default";
      reg-io-width = <1>;
      reg-shift = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-gpio-bank.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
  controller.

  GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller.

  See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for
  additional information and example.

properties:
  '#gpio-cells':
    const: 2

  gpio-controller: true

  '#interrupt-cells':
    description:
      For GPIO banks supporting external GPIO interrupts or external wake-up
      interrupts.
    const: 2

  interrupt-controller:
    description:
      For GPIO banks supporting external GPIO interrupts or external wake-up
      interrupts.

  interrupts:
    description:
      For GPIO banks supporting direct external wake-up interrupts (without
      multiplexing).  Number of interrupts must match number of wake-up capable
      pins of this bank.
    minItems: 1
    maxItems: 8

required:
  - '#gpio-cells'
  - gpio-controller

additionalProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-pins-cfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
  controller.

  Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller.

  The values used for config properties should be derived from the hardware
  manual and these values are programmed as-is into the pin pull up/down and
  driver strength register of the pin-controller.

  See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for
  additional information and example.

properties:
  samsung,pins:
    description: |
      List of pins to configure. For initial and sleep states, the maximum
      number is one pin. In other cases there is no upper limit.

      The pins should use lowercase names matching hardware manual, e.g. for
      GPA0 bank: gpa0-0, gpa0-1, gpa0-2.
    $ref: /schemas/types.yaml#/definitions/string-array

  samsung,pin-function:
    description: |
      The pin function selection that should be applied on the pins listed in the
      child node is specified using the "samsung,pin-function" property. The value
      of this property that should be applied to each of the pins listed in the
      "samsung,pins" property should be picked from the hardware manual of the SoC
      for the specified pin group. This property is optional in the child node if
      no specific function selection is desired for the pins listed in the child
      node. The value of this property is used as-is to program the pin-controller
      function selector register of the pin-bank.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 15

  samsung,pin-drv:
    description: Drive strength configuration.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 15

  samsung,pin-pud:
    description: Pull up/down configuration.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2, 3]

  samsung,pin-val:
    description: Initial value of pin output buffer.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]

  samsung,pin-con-pdn:
    description: Function in power down mode.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2, 3]

  samsung,pin-pud-pdn:
    description: Pull up/down configuration in power down mode.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2, 3]

required:
  - samsung,pins

additionalProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S3C/S5P/Exynos SoC pin controller - wake-up interrupt controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
  controller.

  External wake-up interrupts for Samsung S3C/S5P/Exynos SoC pin controller.
  For S3C24xx, S3C64xx, S5PV210 and Exynos4210 compatible wake-up interrupt
  controllers, only one pin-controller device node can include external wake-up
  interrupts child node (in other words, only one External wake-up interrupts
  pin-controller is supported).
  For newer controllers, multiple pin-controller device node can include
  external wake-up interrupts child node.

  See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for
  additional information and example.

properties:
  compatible:
    enum:
      - samsung,s3c2410-wakeup-eint
      - samsung,s3c2412-wakeup-eint
      - samsung,s3c64xx-wakeup-eint
      - samsung,s5pv210-wakeup-eint
      - samsung,exynos4210-wakeup-eint
      - samsung,exynos7-wakeup-eint
      - samsung,exynos850-wakeup-eint
      - samsung,exynosautov9-wakeup-eint

  interrupts:
    description:
      Interrupt used by multiplexed external wake-up interrupts.
    minItems: 1
    maxItems: 6

required:
  - compatible

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,s3c2410-wakeup-eint
              - samsung,s3c2412-wakeup-eint
    then:
      properties:
        interrupts:
          minItems: 6
          maxItems: 6
      required:
        - interrupts

  - if:
      properties:
        compatible:
          contains:
            const: samsung,s3c64xx-wakeup-eint
    then:
      properties:
        interrupts:
          minItems: 4
          maxItems: 4
      required:
        - interrupts

  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,s5pv210-wakeup-eint
              - samsung,exynos4210-wakeup-eint
              - samsung,exynos7-wakeup-eint
    then:
      properties:
        interrupts:
          minItems: 1
          maxItems: 1
      required:
        - interrupts

  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos850-wakeup-eint
              - samsung,exynosautov9-wakeup-eint
    then:
      properties:
        interrupts: false

additionalProperties: false


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S3C/S5P/Exynos SoC pin controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>
  - Tomasz Figa <tomasz.figa@gmail.com>

description: |
  This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
  controller.

  All the pin controller nodes should be represented in the aliases node using
  the following format 'pinctrl{n}' where n is a unique number for the alias.

  The controller supports three types of interrupts::
   - External GPIO interrupts (see interrupts property in pin controller node);

   - External wake-up interrupts - multiplexed (capable of waking up the system
     see interrupts property in external wake-up interrupt controller node -
     samsung,pinctrl-wakeup-interrupt.yaml);

   - External wake-up interrupts - direct (capable of waking up the system, see
     interrupts property in every bank of pin controller with external wake-up
     interrupt controller - samsung,pinctrl-gpio-bank.yaml).

properties:
  $nodename:
    pattern: "^pinctrl(@.*)?"

  compatible:
    enum:
      - samsung,s3c2412-pinctrl
      - samsung,s3c2416-pinctrl
      - samsung,s3c2440-pinctrl
      - samsung,s3c2450-pinctrl
      - samsung,s3c64xx-pinctrl
      - samsung,s5pv210-pinctrl
      - samsung,exynos3250-pinctrl
      - samsung,exynos4210-pinctrl
      - samsung,exynos4x12-pinctrl
      - samsung,exynos5250-pinctrl
      - samsung,exynos5260-pinctrl
      - samsung,exynos5410-pinctrl
      - samsung,exynos5420-pinctrl
      - samsung,exynos5433-pinctrl
      - samsung,exynos7-pinctrl
      - samsung,exynos7885-pinctrl
      - samsung,exynos850-pinctrl
      - samsung,exynosautov9-pinctrl
      - tesla,fsd-pinctrl

  interrupts:
    description:
      Required for GPIO banks supporting external GPIO interrupts.
    maxItems: 1

  power-domains:
    maxItems: 1

  reg:
    description:
      Second base address of the pin controller if the specific registers of
      the pin controller are separated into the different base address.
      Only certain banks of certain pin controller might need it.
    minItems: 1
    maxItems: 2

  wakeup-interrupt-controller:
    $ref: samsung,pinctrl-wakeup-interrupt.yaml

patternProperties:
  "^[a-z]+[0-9]*-gpio-bank$":
    description:
      Pin banks of the controller are represented by child nodes of the
      controller node. Bank name is taken from name of the node.
    $ref: samsung,pinctrl-gpio-bank.yaml

  "^[a-z0-9-]+-pins$":
    oneOf:
      - $ref: samsung,pinctrl-pins-cfg.yaml
        required:
          - samsung,pins
      - type: object
        patternProperties:
          "^[a-z0-9-]+-pins$":
            $ref: samsung,pinctrl-pins-cfg.yaml

        additionalProperties: false

  "^(initial|sleep)-state$":
    type: object
    additionalProperties: false

    patternProperties:
      "^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$":
        $ref: samsung,pinctrl-pins-cfg.yaml

        properties:
          samsung,pins:
            description: See samsung,pinctrl-pins-cfg.yaml
            $ref: /schemas/types.yaml#/definitions/string-array
            maxItems: 1

        required:
          - samsung,pins

        unevaluatedProperties: false

required:
  - compatible
  - reg

allOf:
  - $ref: "pinctrl.yaml#"
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5433-pinctrl
    then:
      properties:
        reg:
          minItems: 1
          maxItems: 2
    else:
      properties:
        reg:
          minItems: 1
          maxItems: 1

additionalProperties: false

examples:
  - |
    pinctrl@7f008000 {
        compatible = "samsung,s3c64xx-pinctrl";
        reg = <0x7f008000 0x1000>;
        interrupt-parent = <&vic1>;
        interrupts = <21>;

        wakeup-interrupt-controller {
            compatible = "samsung,s3c64xx-wakeup-eint";
            interrupts-extended = <&vic0 0>,
                                  <&vic0 1>,
                                  <&vic1 0>,
                                  <&vic1 1>;
        };

        /* Pin bank with external GPIO or muxed external wake-up interrupts */
        gpa-gpio-bank {
            gpio-controller;
            #gpio-cells = <2>;
            interrupt-controller;
            #interrupt-cells = <2>;
        };

        // ...

        uart0-data-pins {
            samsung,pins = "gpa-0", "gpa-1";
            samsung,pin-function = <2>;
            samsung,pin-pud = <0>;
        };

        // ...
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pinctrl@11400000 {
        compatible = "samsung,exynos4210-pinctrl";
        reg = <0x11400000 0x1000>;
        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;

        pinctrl-names = "default";
        pinctrl-0 = <&sleep0>;

        /* Pin bank with external GPIO or muxed external wake-up interrupts */
        gpa0-gpio-bank {
            gpio-controller;
            #gpio-cells = <2>;
            interrupt-controller;
            #interrupt-cells = <2>;
        };

        // ...

        uart0-data-pins {
            samsung,pins = "gpa0-0", "gpa0-1";
            samsung,pin-function = <2>;
            samsung,pin-pud = <0>;
            samsung,pin-drv = <0>;
        };

        // ...

        sleep0: sleep-state {
            gpa0-0-pin {
                samsung,pins = "gpa0-0";
                samsung,pin-con-pdn = <2>;
                samsung,pin-pud-pdn = <0>;
            };

            gpa0-1-pin {
                samsung,pins = "gpa0-1";
                samsung,pin-con-pdn = <0>;
                samsung,pin-pud-pdn = <0>;
            };

            // ...
        };
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pinctrl@11000000 {
        compatible = "samsung,exynos4210-pinctrl";
        reg = <0x11000000 0x1000>;
        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;

        wakeup-interrupt-controller {
            compatible = "samsung,exynos4210-wakeup-eint";
            interrupt-parent = <&gic>;
            interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
        };

        /* Pin bank with external GPIO or muxed external wake-up interrupts */
        gpj0-gpio-bank {
            gpio-controller;
            #gpio-cells = <2>;
            interrupt-controller;
            #interrupt-cells = <2>;
        };

        /* Pin bank without external interrupts */
        gpy0-gpio-bank {
            gpio-controller;
            #gpio-cells = <2>;
        };

        /* Pin bank with external direct wake-up interrupts */
        gpx0-gpio-bank {
            gpio-controller;
            #gpio-cells = <2>;

            interrupt-controller;
            interrupt-parent = <&gic>;
            interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
            #interrupt-cells = <2>;
        };

        // ...

        sd0-clk-pins {
            samsung,pins = "gpk0-0";
            samsung,pin-function = <2>;
            samsung,pin-pud = <0>;
            samsung,pin-drv = <3>;
        };

        sd4-bus-width8-pins {
            part-1-pins {
                samsung,pins = "gpk0-3", "gpk0-4",
                               "gpk0-5", "gpk0-6";
                samsung,pin-function = <3>;
                samsung,pin-pud = <3>;
                samsung,pin-drv = <3>;
            };

            part-2-pins {
                samsung,pins = "gpk1-3", "gpk1-4",
                               "gpk1-5", "gpk1-6";
                samsung,pin-function = <4>;
                samsung,pin-pud = <3>;
                samsung,pin-drv = <3>;
            };
        };

        // ...

        otg-gp-pins {
            samsung,pins = "gpx3-3";
            samsung,pin-function = <1>;
            samsung,pin-pud = <0>;
            samsung,pin-drv = <0>;
            samsung,pin-val = <0>;
        };
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pinctrl@10580000 {
        compatible = "samsung,exynos5433-pinctrl";
        reg = <0x10580000 0x1a20>, <0x11090000 0x100>;

        pinctrl-names = "default";
        pinctrl-0 = <&initial_alive>;

        wakeup-interrupt-controller {
            compatible = "samsung,exynos7-wakeup-eint";
            interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
        };

        /* Pin bank with external direct wake-up interrupts */
        gpa0-gpio-bank {
            gpio-controller;
            #gpio-cells = <2>;

            interrupt-controller;
            interrupt-parent = <&gic>;
            interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
            #interrupt-cells = <2>;
        };

        // ...

        te-irq-pins {
            samsung,pins = "gpf1-3";
            samsung,pin-function = <0xf>;
        };

        // ..

        initial_alive: initial-state {
            gpa0-0-pin {
                samsung,pins = "gpa0-0";
                samsung,pin-function = <0>;
                samsung,pin-pud = <1>;
                samsung,pin-drv = <0>;
            };

            // ...
        };
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pinctrl@114b0000 {
        compatible = "samsung,exynos5433-pinctrl";
        reg = <0x114b0000 0x1000>;
        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
        power-domains = <&pd_aud>;

        /* Pin bank with external GPIO or muxed external wake-up interrupts */
        gpz0-gpio-bank {
            gpio-controller;
            #gpio-cells = <2>;
            interrupt-controller;
            #interrupt-cells = <2>;
        };

        // ...

        i2s0-bus-pins {
            samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
                           "gpz0-4", "gpz0-5", "gpz0-6";
            samsung,pin-function = <2>;
            samsung,pin-pud = <0>;
            samsung,pin-drv = <0>;
        };

        // ...
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2022 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/semtech,sx1501q.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Semtech SX150x GPIO expander

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

properties:
  compatible:
    enum:
      - semtech,sx1501q
      - semtech,sx1502q
      - semtech,sx1503q
      - semtech,sx1504q
      - semtech,sx1505q
      - semtech,sx1506q
      - semtech,sx1507q
      - semtech,sx1508q
      - semtech,sx1509q

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  '#interrupt-cells':
    const: 2

  interrupt-controller: true

  '#gpio-cells':
    const: 2

  gpio-controller: true

  semtech,probe-reset:
    description: Will trigger a reset of the GPIO expander on probe
    type: boolean

patternProperties:
  '-cfg$':
    type: object
    properties:
      pins: true

      bias-disable: true
      bias-pull-up: true
      bias-pull-down: true
      bias-pull-pin-default: true
      drive-push-pull: true
      output-low: true
      output-high: true
      drive-open-drain: true

    required:
      - pins

    allOf:
      - $ref: "pincfg-node.yaml#"
      - $ref: "pinmux-node.yaml#"
      - if:
          properties:
            pins:
              contains:
                const: oscio
        then:
          properties:
            bias-disable: false
            bias-pull-up: false
            bias-pull-down: false
            bias-pull-pin-default: false
            drive-open-drain: false

    additionalProperties: false

required:
  - compatible
  - reg
  - '#gpio-cells'
  - gpio-controller

allOf:
  - $ref: "pinctrl.yaml#"
  - if:
      not:
        properties:
          compatible:
            contains:
              enum:
                - semtech,sx1507q
                - semtech,sx1508q
                - semtech,sx1509q
    then:
      properties:
        semtech,probe-reset: false
  - if:
      properties:
        compatible:
          contains:
            enum:
              - semtech,sx1501q
              - semtech,sx1504q
    then:
      patternProperties:
        '-cfg$':
          properties:
            pins:
              items:
                pattern: '^gpio[0-3]$'
  - if:
      properties:
        compatible:
          contains:
            enum:
              - semtech,sx1502q
              - semtech,sx1505q
    then:
      patternProperties:
        '-cfg$':
          properties:
            pins:
              items:
                pattern: '^gpio[0-7]$'
  - if:
      properties:
        compatible:
          contains:
            enum:
              - semtech,sx1503q
              - semtech,sx1506q
    then:
      patternProperties:
        '-cfg$':
          properties:
            pins:
              items:
                pattern: '^(gpio[0-9]|gpio1[0-5])$'
  - if:
      properties:
        compatible:
          contains:
            const: semtech,sx1507q
    then:
      patternProperties:
        '-cfg$':
          properties:
            pins:
              items:
                pattern: '^(oscio|gpio[0-3])$'
  - if:
      properties:
        compatible:
          contains:
            const: semtech,sx1508q
    then:
      patternProperties:
        '-cfg$':
          properties:
            pins:
              items:
                pattern: '^(oscio|gpio[0-7])$'
  - if:
      properties:
        compatible:
          contains:
            const: semtech,sx1509q
    then:
      patternProperties:
        '-cfg$':
          properties:
            pins:
              items:
                pattern: '^(oscio|gpio[0-9]|gpio1[0-5])$'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c@1000 {
        reg = <0x1000 0x80>;
        #address-cells = <1>;
        #size-cells = <0>;

        pinctrl@20 {
            compatible = "semtech,sx1501q";
            reg = <0x20>;

            #gpio-cells = <2>;
            #interrupt-cells = <2>;

            interrupts = <16 IRQ_TYPE_EDGE_FALLING>;

            gpio-controller;
            interrupt-controller;

            gpio1-cfg {
                  pins = "gpio1";
                  bias-pull-up;
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UniPhier SoCs pin controller

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

properties:
  compatible:
    enum:
      - socionext,uniphier-ld4-pinctrl
      - socionext,uniphier-pro4-pinctrl
      - socionext,uniphier-sld8-pinctrl
      - socionext,uniphier-pro5-pinctrl
      - socionext,uniphier-pxs2-pinctrl
      - socionext,uniphier-ld6b-pinctrl
      - socionext,uniphier-ld11-pinctrl
      - socionext,uniphier-ld20-pinctrl
      - socionext,uniphier-pxs3-pinctrl
      - socionext,uniphier-nx1-pinctrl

additionalProperties:
  type: object

  allOf:
    - $ref: pincfg-node.yaml#
    - $ref: pinmux-node.yaml#

  properties:
    phandle: true
    function: true
    groups: true
    pins: true
    bias-pull-up: true
    bias-pull-down: true
    bias-pull-pin-default: true
    drive-strength: true

  additionalProperties:
    type: object

    allOf:
      - $ref: pincfg-node.yaml#
      - $ref: pinmux-node.yaml#

    properties:
      phandle: true
      function: true
      groups: true
      pins: true
      bias-pull-up: true
      bias-pull-down: true
      bias-pull-pin-default: true
      drive-strength: true

    unevaluatedProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible

examples:
  - |
    // The UniPhier pinctrl should be a subnode of a "syscon" compatible node.

    soc-glue@5f800000 {
        compatible = "socionext,uniphier-pro4-soc-glue", "simple-mfd", "syscon";
        reg = <0x5f800000 0x2000>;

        pinctrl: pinctrl {
            compatible = "socionext,uniphier-pro4-pinctrl";
        };
    };


code:
* Spreadtrum Pin Controller

The Spreadtrum pin controller are organized in 3 blocks (types).

The first block comprises some global control registers, and each
register contains several bit fields with one bit or several bits
to configure for some global common configuration, such as domain
pad driving level, system control select and so on ("domain pad
driving level": One pin can output 3.0v or 1.8v, depending on the
related domain pad driving selection, if the related domain pad
slect 3.0v, then the pin can output 3.0v. "system control" is used
to choose one function (like: UART0) for which system, since we
have several systems (AP/CP/CM4) on one SoC.).

There are too much various configuration that we can not list all
of them, so we can not make every Spreadtrum-special configuration
as one generic configuration, and maybe it will add more strange
global configuration in future. Then we add one "sprd,control" to
set these various global control configuration, and we need use
magic number for this property.

Moreover we recognise every fields comprising one bit or several
bits in one global control register as one pin, thus we should
record every pin's bit offset, bit width and register offset to
configure this field (pin).

The second block comprises some common registers which have unified
register definition, and each register described one pin is used
to configure the pin sleep mode, function select and sleep related
configuration.

Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
PUBCP system, TGLDSP system and AGDSP system. And the pin sleep
related configuration are:
- input-enable
- input-disable
- output-high
- output-low
- bias-pull-up
- bias-pull-down

In some situation we need set the pin sleep mode and pin sleep related
configuration, to set the pin sleep related configuration automatically
by hardware when the system specified by sleep mode goes into deep
sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP
and set the pin sleep related configuration as "input-enable", which
means when PUBCP system goes into deep sleep mode, this pin will be set
input enable automatically.

Moreover we can not use the "sleep" state, since some systems (like:
PUBCP system) do not run linux kernel OS (only AP system run linux
kernel on SC9860 platform), then we can not select "sleep" state
when the PUBCP system goes into deep sleep mode. Thus we introduce
"sprd,sleep-mode" property to set pin sleep mode.

The last block comprises some misc registers which also have unified
register definition, and each register described one pin is used to
configure drive strength, pull up/down and so on. Especially for pull
up, we have two kind pull up resistor: 20K and 4.7K.

Required properties for Spreadtrum pin controller:
- compatible: "sprd,<soc>-pinctrl"
  Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported SoCs.
- reg: The register address of pin controller device.
- pins : An array of pin names.

Optional properties:
- function: Specified the function name.
- drive-strength: Drive strength in mA.
- input-schmitt-disable: Enable schmitt-trigger mode.
- input-schmitt-enable: Disable schmitt-trigger mode.
- bias-disable: Disable pin bias.
- bias-pull-down: Pull down on pin.
- bias-pull-up: Pull up on pin.
- input-enable: Enable pin input.
- input-disable: Enable pin output.
- output-high: Set the pin as an output level high.
- output-low: Set the pin as an output level low.
- sleep-hardware-state: Indicate these configs in this state are sleep related.
- sprd,control: Control values referring to databook for global control pins.
- sprd,sleep-mode: Sleep mode selection.

Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported values.


code:
* Spreadtrum SC9860 Pin Controller

Please refer to sprd,pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: Must be "sprd,sc9860-pinctrl".
- reg: The register address of pin controller device.
- pins : An array of strings, each string containing the name of a pin.

Optional properties:
- function: A string containing the name of the function, values must be
  one of: "func1", "func2", "func3" and "func4".
- drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
  12, 14, 16, 20, 21, 24, 25, 27, 29, 31 and 33.
- input-schmitt-disable: Enable schmitt-trigger mode.
- input-schmitt-enable: Disable schmitt-trigger mode.
- bias-disable: Disable pin bias.
- bias-pull-down: Pull down on pin.
- bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
  is 20K and 4700 for pull-up resistor is 4.7K.
- input-enable: Enable pin input.
- input-disable: Enable pin output.
- output-high: Set the pin as an output level high.
- output-low: Set the pin as an output level low.
- sleep-hardware-state: Indicate these configs in this state are sleep related.
- sprd,control: Control values referring to databook for global control pins.
- sprd,sleep-mode: Choose the pin sleep mode, and supported values are:
  AP_SLEEP, PUBCP_SLEEP, TGLDSP_SLEEP and AGDSP_SLEEP.

Pin sleep mode definition:
enum pin_sleep_mode {
	AP_SLEEP = BIT(0),
	PUBCP_SLEEP = BIT(1),
	TGLDSP_SLEEP = BIT(2),
	AGDSP_SLEEP = BIT(3),
};

Example:
pin_controller: pinctrl@402a0000 {
	compatible = "sprd,sc9860-pinctrl";
	reg = <0x402a0000 0x10000>;

	grp1: sd0 {
		pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE";
		sprd,control = <0x1>;
	};

	grp2: rfctl_33 {
		pins = "SC9860_RFCTL33";
		function = "func2";
		sprd,sleep-mode = <AP_SLEEP | PUBCP_SLEEP>;
		grp2_sleep_mode: rfctl_33_sleep {
			pins = "SC9860_RFCTL33";
			sleep-hardware-state;
			output-low;
		}
	};

	grp3: rfctl_misc_20 {
		pins = "SC9860_RFCTL20_MISC";
		drive-strength = <10>;
		bias-pull-up = <4700>;
		grp3_sleep_mode: rfctl_misc_sleep {
			pins = "SC9860_RFCTL20_MISC";
			sleep-hardware-state;
			bias-pull-up;
		}
	};
};