code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/brcm,avs-ro-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom AVS ring oscillator thermal

maintainers:
  - Stefan Wahren <wahrenst@gmx.net>

description: |+
  The thermal node should be the child of a syscon node with the
  required property:

  - compatible: Should be one of the following:
                "brcm,bcm2711-avs-monitor", "syscon", "simple-mfd"

  Refer to the bindings described in
  Documentation/devicetree/bindings/mfd/syscon.yaml

properties:
  compatible:
    const: brcm,bcm2711-thermal

  # See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details
  "#thermal-sensor-cells":
    const: 0

required:
  - compatible
  - '#thermal-sensor-cells'

additionalProperties: false

examples:
  - |
        avs-monitor@7d5d2000 {
                compatible = "brcm,bcm2711-avs-monitor",
                             "syscon", "simple-mfd";
                reg = <0x7d5d2000 0xf00>;

                thermal: thermal {
                        compatible = "brcm,bcm2711-thermal";
                        #thermal-sensor-cells = <0>;
                };
        };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/brcm,avs-tmon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom STB thermal management

description: Thermal management core, provided by the AVS TMON hardware block.

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

allOf:
  - $ref: thermal-sensor.yaml#

properties:
  compatible:
    items:
      - enum:
          - brcm,avs-tmon-bcm7216
          - brcm,avs-tmon-bcm7445
      - const: brcm,avs-tmon

  reg:
    maxItems: 1
    description: >
      Address range for the AVS TMON registers

  interrupts:
    maxItems: 1

  interrupt-names:
    items:
      - const: tmon

  "#thermal-sensor-cells":
    const: 0

additionalProperties: false

required:
  - compatible
  - reg
  - "#thermal-sensor-cells"

examples:
  - |
     thermal@f04d1500 {
          compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon";
          reg = <0xf04d1500 0x28>;
          interrupts = <0x6>;
          interrupt-names = "tmon";
          interrupt-parent = <&avs_host_l2_intc>;
          #thermal-sensor-cells = <0>;
     };

repo_name: angery/linux


code:
Binding for Thermal Sensor driver for BCM2835 SoCs.

Required parameters:
-------------------

compatible: 		should be one of: "brcm,bcm2835-thermal",
			"brcm,bcm2836-thermal" or "brcm,bcm2837-thermal"
reg:			Address range of the thermal registers.
clocks: 		Phandle of the clock used by the thermal sensor.
#thermal-sensor-cells:	should be 0 (see Documentation/devicetree/bindings/thermal/thermal-sensor.yaml)

Example:

thermal-zones {
	cpu_thermal: cpu-thermal {
		polling-delay-passive = <0>;
		polling-delay = <1000>;

		thermal-sensors = <&thermal>;

		trips {
			cpu-crit {
				temperature	= <80000>;
				hysteresis	= <0>;
				type		= "critical";
			};
		};

		coefficients = <(-538)	407000>;

		cooling-maps {
		};
	};
};

thermal: thermal@7e212000 {
	compatible = "brcm,bcm2835-thermal";
	reg = <0x7e212000 0x8>;
	clocks = <&clocks BCM2835_CLOCK_TSENS>;
	#thermal-sensor-cells = <0>;
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/brcm,ns-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Northstar Thermal

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

description:
  Thermal sensor that is part of Northstar's DMU (Device Management Unit).

allOf:
  - $ref: thermal-sensor.yaml#

properties:
  compatible:
    const: brcm,ns-thermal

  reg:
    description: PVTMON registers range
    maxItems: 1

  "#thermal-sensor-cells":
    const: 0

unevaluatedProperties: false

required:
  - reg

examples:
  - |
    thermal: thermal@1800c2c0 {
        compatible = "brcm,ns-thermal";
        reg = <0x1800c2c0 0x10>;
        #thermal-sensor-cells = <0>;
    };

    thermal-zones {
        cpu-thermal {
            polling-delay-passive = <0>;
            polling-delay = <1000>;
            coefficients = <(-556) 418000>;
            thermal-sensors = <&thermal>;

            trips {
                cpu-crit {
                    temperature = <125000>;
                    hysteresis = <0>;
                    type = "critical";
                };
            };

            cooling-maps {
            };
        };
    };


code:
* Broadcom Stingray Thermal

This binding describes thermal sensors that is part of Stingray SoCs.

Required properties:
- compatible : Must be "brcm,sr-thermal"
- reg : Memory where tmon data will be available.
- brcm,tmon-mask: A one cell bit mask of valid TMON sources.
                  Each bit represents single TMON source.
- #thermal-sensor-cells : Thermal sensor phandler
- polling-delay: Max number of milliseconds to wait between polls.
- thermal-sensors: A list of thermal sensor phandles and specifier.
                   specifier value is tmon ID and it should be
                   in correspond with brcm,tmon-mask.
- temperature: trip temperature threshold in millicelsius.

Example:
	tmons {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x8f100000 0x100>;

		tmon: tmon@0 {
			compatible = "brcm,sr-thermal";
			reg = <0x0 0x40>;
			brcm,tmon-mask = <0x3f>;
			#thermal-sensor-cells = <1>;
		};
	};

	thermal-zones {
		ihost0_thermal: ihost0-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			thermal-sensors = <&tmon 0>;
			trips {
				cpu-crit {
					temperature = <105000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
		ihost1_thermal: ihost1-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			thermal-sensors = <&tmon 1>;
			trips {
				cpu-crit {
					temperature = <105000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
		ihost2_thermal: ihost2-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			thermal-sensors = <&tmon 2>;
			trips {
				cpu-crit {
					temperature = <105000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
		ihost3_thermal: ihost3-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			thermal-sensors = <&tmon 3>;
			trips {
				cpu-crit {
					temperature = <105000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
		crmu_thermal: crmu-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			thermal-sensors = <&tmon 4>;
			trips {
				cpu-crit {
					temperature = <105000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
		nitro_thermal: nitro-thermal {
			polling-delay-passive = <0>;
			polling-delay = <1000>;
			thermal-sensors = <&tmon 5>;
			trips {
				cpu-crit {
					temperature = <105000>;
					hysteresis = <0>;
					type = "critical";
				};
			};
		};
	};


code:
* Dialog DA9062/61 TJUNC Thermal Module

This module is part of the DA9061/DA9062. For more details about entire
DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt

Junction temperature thermal module uses an interrupt signal to identify
high THERMAL_TRIP_HOT temperatures for the PMIC device.

Required properties:

- compatible: should be one of the following valid compatible string lines:
        "dlg,da9061-thermal", "dlg,da9062-thermal"
        "dlg,da9062-thermal"

Optional properties:

- polling-delay-passive : Specify the polling period, measured in
    milliseconds, between thermal zone device update checks.

Example: DA9062

	pmic0: da9062@58 {
		thermal {
			compatible = "dlg,da9062-thermal";
			polling-delay-passive = <3000>;
		};
	};

Example: DA9061 using a fall-back compatible for the DA9062 onkey driver

	pmic0: da9061@58 {
		thermal {
			compatible = "dlg,da9061-thermal", "dlg,da9062-thermal";
			polling-delay-passive = <3000>;
		};
	};


code:
* ST-Ericsson DB8500 Thermal

** Thermal node properties:

- compatible : "stericsson,db8500-thermal";
- reg : address range of the thermal sensor registers;
- interrupts : interrupts generated from PRCMU;
- interrupt-names : "IRQ_HOTMON_LOW" and "IRQ_HOTMON_HIGH";
- num-trips : number of total trip points, this is required, set it 0 if none,
  if greater than 0, the following properties must be defined;
- tripN-temp : temperature of trip point N, should be in ascending order;
- tripN-type : type of trip point N, should be one of "active" "passive" "hot"
  "critical";
- tripN-cdev-num : number of the cooling devices which can be bound to trip
  point N, this is required if trip point N is defined, set it 0 if none,
  otherwise the following cooling device names must be defined;
- tripN-cdev-nameM : name of the No. M cooling device of trip point N;

Usually the num-trips and tripN-*** are separated in board related dts files.

Example:
thermal@801573c0 {
	compatible = "stericsson,db8500-thermal";
	reg = <0x801573c0 0x40>;
	interrupts = <21 0x4>, <22 0x4>;
	interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";

	num-trips = <3>;

	trip0-temp = <75000>;
	trip0-type = "active";
	trip0-cdev-num = <1>;
	trip0-cdev-name0 = "thermal-cpufreq-0";

	trip1-temp = <80000>;
	trip1-type = "active";
	trip1-cdev-num = <2>;
	trip1-cdev-name0 = "thermal-cpufreq-0";
	trip1-cdev-name1 = "thermal-fan";

	trip2-temp = <85000>;
	trip2-type = "critical";
	trip2-cdev-num = <0>;
}


code:
* Dove Thermal

This driver is for Dove SoCs which contain a thermal sensor.

Required properties:
- compatible : "marvell,dove-thermal"
- reg : Address range of the thermal registers

The reg properties should contain two ranges. The first is for the
three Thermal Manager registers, while the second range contains the
Thermal Diode Control Registers.

Example:

	thermal@10078 {
		compatible = "marvell,dove-thermal";
		reg = <0xd001c 0x0c>, <0xd005c 0x08>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/fsl,scu-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX SCU Client Device Node - Thermal bindings based on SCU Message Protocol

maintainers:
  - Dong Aisheng <aisheng.dong@nxp.com>

description: i.MX SCU Client Device Node
  Client nodes are maintained as children of the relevant IMX-SCU device node.

allOf:
  - $ref: thermal-sensor.yaml#

properties:
  compatible:
    items:
      - const: fsl,imx8qxp-sc-thermal
      - const: fsl,imx-sc-thermal

  '#thermal-sensor-cells':
    const: 1

required:
  - compatible
  - '#thermal-sensor-cells'

additionalProperties: false

examples:
  - |
    thermal-sensor {
        compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
        #thermal-sensor-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/generic-adc-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: General Purpose Analog To Digital Converter (ADC) based thermal sensor

maintainers:
  - Laxman Dewangan <ldewangan@nvidia.com>

description:
  On some of platforms, thermal sensor like thermistors are connected to
  one of ADC channel and sensor resistance is read via voltage across the
  sensor resistor. The voltage read across the sensor is mapped to
  temperature using voltage-temperature lookup table.

properties:
  compatible:
    const: generic-adc-thermal

  '#thermal-sensor-cells':
    const: 0

  io-channels:
    maxItems: 1

  io-channel-names:
    const: sensor-channel

  temperature-lookup-table:
    description: |
      Lookup table to map the relation between ADC value and temperature.
      When ADC is read, the value is looked up on the table to get the
      equivalent temperature.

      If not specified, driver assumes the ADC channel gives milliCelsius
      directly.
    $ref: /schemas/types.yaml#/definitions/int32-matrix
    items:
      items:
        - description: Temperature in milliCelsius
        - description: ADC read value

required:
  - compatible
  - '#thermal-sensor-cells'
  - io-channels
  - io-channel-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/thermal/thermal.h>

    thermal-sensor {
        compatible = "generic-adc-thermal";
        #thermal-sensor-cells = <0>;
        io-channels = <&ads1015 1>;
        io-channel-names = "sensor-channel";
        temperature-lookup-table = <
              (-40000) 2578
              (-39000) 2577
              (-38000) 2576
              (-37000) 2575
              (-36000) 2574
              (-35000) 2573
              (-34000) 2572
              (-33000) 2571
              (-32000) 2569
              (-31000) 2568
              (-30000) 2567
              /* skip */
              118000 254
              119000 247
              120000 240
              121000 233
              122000 226
              123000 220
              124000 214
              125000 208>;
    };
...


code:
* Temperature Sensor on hisilicon SoCs

** Required properties :

- compatible: "hisilicon,tsensor".
- reg: physical base address of thermal sensor and length of memory mapped
  region.
- interrupt: The interrupt number to the cpu. Defines the interrupt used
  by /SOCTHERM/tsensor.
- clock-names: Input clock name, should be 'thermal_clk'.
- clocks: phandles for clock specified in "clock-names" property.
- #thermal-sensor-cells: Should be 1. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.

Example :

for Hi6220:
	tsensor: tsensor@0,f7030700 {
		compatible = "hisilicon,tsensor";
		reg = <0x0 0xf7030700 0x0 0x1000>;
		interrupts = <0 7 0x4>;
		clocks = <&sys_ctrl HI6220_TSENSOR_CLK>;
		clock-names = "thermal_clk";
		#thermal-sensor-cells = <1>;
	}

for Hi3660:
	tsensor: tsensor@fff30000 {
		compatible = "hisilicon,hi3660-tsensor";
		reg = <0x0 0xfff30000 0x0 0x1000>;
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
		#thermal-sensor-cells = <1>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/imx-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX Thermal Binding

maintainers:
  - Shawn Guo <shawnguo@kernel.org>
  - Anson Huang <Anson.Huang@nxp.com>

properties:
  compatible:
    enum:
      - fsl,imx6q-tempmon
      - fsl,imx6sx-tempmon
      - fsl,imx7d-tempmon

  interrupts:
    description: |
      The interrupt output of the controller, i.MX6Q has IRQ_HIGH which
      will be triggered when temperature is higher than high threshold,
      i.MX6SX and i.MX7S/D have two more IRQs than i.MX6Q, one is IRQ_LOW
      and the other is IRQ_PANIC, when temperature is lower than low
      threshold, IRQ_LOW will be triggered, when temperature is higher
      than panic threshold, IRQ_PANIC will be triggered, and system can
      be configured to auto reboot by SRC module for IRQ_PANIC. IRQ_HIGH,
      IRQ_LOW and IRQ_PANIC share same interrupt output of controller.
    maxItems: 1

  nvmem-cells:
    items:
      - description: Phandle to the calibration data provided by ocotp
      - description: Phandle to the temperature grade provided by ocotp

  nvmem-cell-names:
    items:
      - const: calib
      - const: temp_grade

  fsl,tempmon:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: Phandle to anatop system controller node.

  fsl,tempmon-data:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: |
      Deprecated property, phandle pointer to fuse controller that contains
      TEMPMON calibration data, e.g. OCOTP on imx6q. The details about
      calibration data can be found in SoC Reference Manual.
    deprecated: true

  clocks:
    maxItems: 1

required:
  - compatible
  - interrupts
  - fsl,tempmon
  - nvmem-cells
  - nvmem-cell-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx6sx-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    efuse@21bc000 {
         #address-cells = <1>;
         #size-cells = <1>;
         compatible = "fsl,imx6sx-ocotp", "syscon";
         reg = <0x021bc000 0x4000>;
         clocks = <&clks IMX6SX_CLK_OCOTP>;

         tempmon_calib: calib@38 {
             reg = <0x38 4>;
         };

         tempmon_temp_grade: temp-grade@20 {
             reg = <0x20 4>;
         };
    };

    anatop@20c8000 {
        compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
        reg = <0x020c8000 0x1000>;
        interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
                     <0 54 IRQ_TYPE_LEVEL_HIGH>,
                     <0 127 IRQ_TYPE_LEVEL_HIGH>;

        tempmon {
             compatible = "fsl,imx6sx-tempmon";
             interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
             fsl,tempmon = <&anatop>;
             nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
             nvmem-cell-names = "calib", "temp_grade";
             clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/imx8mm-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8M Mini Thermal Binding

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

description: |
  i.MX8MM has TMU IP to allow temperature measurement, there are
  currently two distinct major versions of the IP that is supported
  by a single driver. The IP versions are named v1 and v2, v1 is
  for i.MX8MM which has ONLY 1 sensor, v2 is for i.MX8MP which has
  2 sensors.

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx8mm-tmu
          - fsl,imx8mp-tmu
      - items:
          - const: fsl,imx8mn-tmu
          - const: fsl,imx8mm-tmu

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  nvmem-cells:
    maxItems: 1
    description: Phandle to the calibration data provided by ocotp

  nvmem-cell-names:
    const: calib

  "#thermal-sensor-cells":
    description: |
      Number of cells required to uniquely identify the thermal
      sensors, 0 for ONLY one sensor and 1 for multiple sensors.
    enum:
      - 0
      - 1

required:
  - compatible
  - reg
  - clocks
  - '#thermal-sensor-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mm-clock.h>

    thermal-sensor@30260000 {
         compatible = "fsl,imx8mm-tmu";
         reg = <0x30260000 0x10000>;
         clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
         #thermal-sensor-cells = <0>;
    };

...


code:
* Kirkwood Thermal

This version is for Kirkwood 88F8262 & 88F6283 SoCs. Other kirkwoods
don't contain a thermal sensor.

Required properties:
- compatible : "marvell,kirkwood-thermal"
- reg : Address range of the thermal registers

Example:

	thermal@10078 {
		compatible = "marvell,kirkwood-thermal";
		reg = <0x10078 0x4>;
	};


code:
Thermal driver for MAX77620 Power management IC from Maxim Semiconductor.

Maxim Semiconductor MAX77620 supports alarm interrupts when its
die temperature crosses 120C and 140C. These threshold temperatures
are not configurable. Device does not provide the real temperature
of die other than just indicating whether temperature is above or
below threshold level.

Required properties:
-------------------
#thermal-sensor-cells:	For more details, please refer to
			<devicetree/bindings/thermal/thermal-sensor.yaml>
			The value must be 0.

For more details, please refer generic thermal DT binding document
<devicetree/bindings/thermal/thermal*.yaml>.

Please refer <devicetree/bindings/mfd/max77620.txt> for mfd DT binding
document for the MAX77620.

Example:
--------
#include <dt-bindings/mfd/max77620.h>
#include <dt-bindings/thermal/thermal.h>
...

i2c@7000d000 {
	spmic: max77620@3c {
		compatible = "maxim,max77620";
		:::::
		#thermal-sensor-cells = <0>;
		:::
	};
};

cool_dev: cool-dev {
	compatible = "cooling-dev";
	#cooling-cells = <2>;
};

thermal-zones {
	PMIC-Die {
		polling-delay = <0>;
		polling-delay-passive = <0>;
		thermal-sensors = <&spmic>;

		trips {
			pmic_die_warn_temp_thresh: hot-die {
				temperature = <120000>;
				type = "hot";
				hysteresis = <0>;
			};

			pmic_die_cirt_temp_thresh: cirtical-die {
				temperature = <140000>;
				type = "critical";
				hysteresis = <0>;
			};
		};

		cooling-maps {
			map0 {
				trip = <&pmic_die_warn_temp_thresh>;
				cooling-device = <&cool_dev THERMAL_NO_LIMIT
						  THERMAL_NO_LIMIT>;
				contribution = <100>;
			};
		};
	};
};


code:
* Mediatek Thermal

This describes the device tree binding for the Mediatek thermal controller
which measures the on-SoC temperatures. This device does not have its own ADC,
instead it directly controls the AUXADC via AHB bus accesses. For this reason
this device needs phandles to the AUXADC. Also it controls a mux in the
apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
is also needed.

Required properties:
- compatible:
  - "mediatek,mt8173-thermal" : For MT8173 family of SoCs
  - "mediatek,mt2701-thermal" : For MT2701 family of SoCs
  - "mediatek,mt2712-thermal" : For MT2712 family of SoCs
  - "mediatek,mt7622-thermal" : For MT7622 SoC
  - "mediatek,mt7981-thermal", "mediatek,mt7986-thermal" : For MT7981 SoC
  - "mediatek,mt7986-thermal" : For MT7986 SoC
  - "mediatek,mt8183-thermal" : For MT8183 family of SoCs
  - "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs
- reg: Address range of the thermal controller
- interrupts: IRQ for the thermal controller
- clocks, clock-names: Clocks needed for the thermal controller. required
                       clocks are:
		       "therm":	 Main clock needed for register access
		       "auxadc": The AUXADC clock
- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses
- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller.
- #thermal-sensor-cells : Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.

Optional properties:
- resets: Reference to the reset controller controlling the thermal controller.
- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
               unspecified default values shall be used.
- nvmem-cell-names: Should be "calibration-data"

Example:

	thermal: thermal@1100b000 {
		#thermal-sensor-cells = <1>;
		compatible = "mediatek,mt8173-thermal";
		reg = <0 0x1100b000 0 0x1000>;
		interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
		clock-names = "therm", "auxadc";
		resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
		reset-names = "therm";
		mediatek,auxadc = <&auxadc>;
		mediatek,apmixedsys = <&apmixedsys>;
		nvmem-cells = <&thermal_calibration_data>;
		nvmem-cell-names = "calibration-data";
	};


code:
Tegra124 SOCTHERM thermal management system

The SOCTHERM IP block contains thermal sensors, support for polled
or interrupt-based thermal monitoring, CPU and GPU throttling based
on temperature trip points, and handling external overcurrent
notifications. It is also used to manage emergency shutdown in an
overheating situation.

Required properties :
- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
  For Tegra132, must contain "nvidia,tegra132-soctherm".
  For Tegra210, must contain "nvidia,tegra210-soctherm".
- reg : Should contain at least 2 entries for each entry in reg-names:
  - SOCTHERM register set
  - Tegra CAR register set: Required for Tegra124 and Tegra210.
  - CCROC register set: Required for Tegra132.
- reg-names :  Should contain at least 2 entries:
  - soctherm-reg
  - car-reg
  - ccroc-reg
- interrupts : Defines the interrupt used by SOCTHERM
- clocks : Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
  - tsensor
  - soctherm
- resets : Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
  - soctherm
- #thermal-sensor-cells : Should be 1. For a description of this property, see
     Documentation/devicetree/bindings/thermal/thermal-sensor.yaml.
    See <dt-bindings/thermal/tegra124-soctherm.h> for a list of valid values
    when referring to thermal sensors.
- throttle-cfgs: A sub-node which is a container of configuration for each
    hardware throttle events. These events can be set as cooling devices.
  * throttle events: Sub-nodes must be named as "light" or "heavy".
      Properties:
      - nvidia,priority: Each throttles has its own throttle settings, so the
        SW need to set priorities for various throttle, the HW arbiter can select
        the final throttle settings.
        Bigger value indicates higher priority, In general, higher priority
        translates to lower target frequency. SW needs to ensure that critical
        thermal alarms are given higher priority, and ensure that there is
        no race if priority of two vectors is set to the same value.
        The range of this value is 1~100.
      - nvidia,cpu-throt-percent: This property is for Tegra124 and Tegra210.
        It is the throttling depth of pulse skippers, it's the percentage
        throttling.
      - nvidia,cpu-throt-level: This property is only for Tegra132, it is the
        level of pulse skippers, which used to throttle clock frequencies. It
        indicates cpu clock throttling depth, and the depth can be programmed.
        Must set as following values:
        TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED
        TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE
      - nvidia,gpu-throt-level: This property is for Tegra124 and Tegra210.
        It is the level of pulse skippers, which used to throttle clock
        frequencies. It indicates gpu clock throttling depth and can be
        programmed to any of the following values which represent a throttling
        percentage:
        TEGRA_SOCTHERM_THROT_LEVEL_NONE (0%)
        TEGRA_SOCTHERM_THROT_LEVEL_LOW (50%),
        TEGRA_SOCTHERM_THROT_LEVEL_MED (75%),
        TEGRA_SOCTHERM_THROT_LEVEL_HIGH (85%).
      - #cooling-cells: Should be 1. This cooling device only support on/off state.
        For a description of this property see:
	Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml

      Optional properties: The following properties are T210 specific and
      valid only for OCx throttle events.
      - nvidia,count-threshold: Specifies the number of OC events that are
        required for triggering an interrupt. Interrupts are not triggered if
        the property is missing. A value of 0 will interrupt on every OC alarm.
      - nvidia,polarity-active-low: Configures the polarity of the OC alaram
        signal. If present, this means assert low, otherwise assert high.
      - nvidia,alarm-filter: Number of clocks to filter event. When the filter
        expires (which means the OC event has not occurred for a long time),
        the counter is cleared and filter is rearmed. Default value is 0.
      - nvidia,throttle-period-us: Specifies the number of uSec for which
        throttling is engaged after the OC event is deasserted. Default value
        is 0.

Optional properties:
- nvidia,thermtrips : When present, this property specifies the temperature at
  which the soctherm hardware will assert the thermal trigger signal to the
  Power Management IC, which can be configured to reset or shutdown the device.
  It is an array of pairs where each pair represents a tsensor id followed by a
  temperature in milli Celcius. In the absence of this property the critical
  trip point will be used for thermtrip temperature.

Note:
- the "critical" type trip points will be used to set the temperature at which
the SOC_THERM hardware will assert a thermal trigger if the "nvidia,thermtrips"
property is missing. When the thermtrips property is present, the breach of a
critical trip point is reported back to the thermal framework to implement
software shutdown.

- the "hot" type trip points will be set to SOC_THERM hardware as the throttle
temperature. Once the temperature of this thermal zone is higher
than it, it will trigger the HW throttle event.

Example :

	soctherm@700e2000 {
		compatible = "nvidia,tegra124-soctherm";
		reg = <0x0 0x700e2000 0x0 0x600  /* SOC_THERM reg_base */
			0x0 0x60006000 0x0 0x400 /* CAR reg_base */
		reg-names = "soctherm-reg", "car-reg";
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
			<&tegra_car TEGRA124_CLK_SOC_THERM>;
		clock-names = "tsensor", "soctherm";
		resets = <&tegra_car 78>;
		reset-names = "soctherm";

		#thermal-sensor-cells = <1>;

		nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500
				     TEGRA124_SOCTHERM_SENSOR_GPU 103000>;

		throttle-cfgs {
			/*
			 * When the "heavy" cooling device triggered,
			 * the HW will skip cpu clock's pulse in 85% depth,
			 * skip gpu clock's pulse in 85% level
			 */
			throttle_heavy: heavy {
				nvidia,priority = <100>;
				nvidia,cpu-throt-percent = <85>;
				nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;

				#cooling-cells = <1>;
			};

			/*
			 * When the "light" cooling device triggered,
			 * the HW will skip cpu clock's pulse in 50% depth,
			 * skip gpu clock's pulse in 50% level
			 */
			throttle_light: light {
				nvidia,priority = <80>;
				nvidia,cpu-throt-percent = <50>;
				nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>;

				#cooling-cells = <1>;
			};

			/*
			 * If these two devices are triggered in same time, the HW throttle
			 * arbiter will select the highest priority as the final throttle
			 * settings to skip cpu pulse.
			 */

			throttle_oc1: oc1 {
				nvidia,priority = <50>;
				nvidia,polarity-active-low;
				nvidia,count-threshold = <100>;
				nvidia,alarm-filter = <5100000>;
				nvidia,throttle-period-us = <0>;
				nvidia,cpu-throt-percent = <75>;
				nvidia,gpu-throt-level =
						<TEGRA_SOCTHERM_THROT_LEVEL_MED>;
                        };
		};
	};

Example: referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" :

	soctherm@700e2000 {
		compatible = "nvidia,tegra132-soctherm";
		reg = <0x0 0x700e2000 0x0 0x600  /* SOC_THERM reg_base */
			0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
		reg-names = "soctherm-reg", "ccroc-reg";

		throttle-cfgs {
			/*
			 * When the "heavy" cooling device triggered,
			 * the HW will skip cpu clock's pulse in HIGH level
			 */
			throttle_heavy: heavy {
				nvidia,priority = <100>;
				nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;

				#cooling-cells = <1>;
			};

			/*
			 * When the "light" cooling device triggered,
			 * the HW will skip cpu clock's pulse in MED level
			 */
			throttle_light: light {
				nvidia,priority = <80>;
				nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;

				#cooling-cells = <1>;
			};

			/*
			 * If these two devices are triggered in same time, the HW throttle
			 * arbiter will select the highest priority as the final throttle
			 * settings to skip cpu pulse.
			 */

		};
	};

Example: referring to thermal sensors :

       thermal-zones {
                cpu {
                        polling-delay-passive = <1000>;
                        polling-delay = <1000>;

                        thermal-sensors =
                                <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;

			trips {
				cpu_shutdown_trip: shutdown-trip {
					temperature = <102500>;
					hysteresis = <1000>;
					type = "critical";
				};

				cpu_throttle_trip: throttle-trip {
					temperature = <100000>;
					hysteresis = <1000>;
					type = "hot";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_throttle_trip>;
					cooling-device = <&throttle_heavy 1 1>;
				};
			};
                };
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra186 (and later) BPMP thermal sensor

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: |
  In Tegra186, the BPMP (Boot and Power Management Processor) implements
  an interface that is used to read system temperatures, including CPU
  cluster and GPU temperatures. This binding describes the thermal
  sensor that is exposed by BPMP.

  The BPMP thermal node must be located directly inside the main BPMP
  node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the
  BPMP binding.

  This node represents a thermal sensor. See

    Documentation/devicetree/bindings/thermal/thermal-sensor.yaml

  for details of the core thermal binding.

properties:
  compatible:
    enum:
      - nvidia,tegra186-bpmp-thermal
      - nvidia,tegra194-bpmp-thermal

  '#thermal-sensor-cells':
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Number of cells needed in the phandle specifier to
      identify a given sensor. Must be 1 and the single cell specifies
      the sensor index.
    const: 1

additionalProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/nvidia,tegra30-tsensor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra30 Thermal Sensor

maintainers:
  - Dmitry Osipenko <digetx@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  TSENSOR provides thermal and voltage sensors which monitor temperature
  and voltage of the chip. Sensors are placed across the die to gauge the
  temperature of the whole chip. The TSENSOR module:

    Generates an interrupt to SW to lower temperature via DVFS on reaching
    a certain thermal/voltage threshold.

    Generates a signal to the CAR to reduce CPU frequency by half on reaching
    a certain thermal/voltage threshold.

    Generates a signal to the PMC when the temperature reaches dangerously high
    levels to reset the chip and sets a flag in the PMC.

  TSENSOR has two channels which monitor two different spots of the SoC.

properties:
  compatible:
    const: nvidia,tegra30-tsensor

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#thermal-sensor-cells":
    const: 1

  assigned-clock-parents: true
  assigned-clock-rates: true
  assigned-clocks: true

required:
  - compatible
  - reg
  - clocks
  - resets
  - interrupts
  - "#thermal-sensor-cells"

additionalProperties: false

examples:
  - |
    thermal-sensor@70014000 {
      compatible = "nvidia,tegra30-tsensor";
      reg = <0x70014000 0x500>;
      interrupts = <0 102 4>;
      clocks = <&clk 100>;
      resets = <&rst 100>;

      #thermal-sensor-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/qcom,spmi-temp-alarm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm QPNP PMIC Temperature Alarm

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  QPNP temperature alarm peripherals are found inside of Qualcomm PMIC chips
  that utilize the Qualcomm SPMI implementation. These peripherals provide an
  interrupt signal and status register to identify high PMIC die temperature.

allOf:
  - $ref: thermal-sensor.yaml#

properties:
  compatible:
    const: qcom,spmi-temp-alarm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  io-channels:
    items:
      - description: ADC channel, which reports chip die temperature

  io-channel-names:
    items:
      - const: thermal

  '#thermal-sensor-cells':
    const: 0

required:
  - compatible
  - reg
  - interrupts
  - '#thermal-sensor-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pmic {
        #address-cells = <1>;
        #size-cells = <0>;

        pm8350_temp_alarm: temperature-sensor@a00 {
            compatible = "qcom,spmi-temp-alarm";
            reg = <0xa00>;
            interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
            #thermal-sensor-cells = <0>;
        };
    };

    thermal-zones {
        pm8350_thermal: pm8350c-thermal {
            polling-delay-passive = <100>;
            polling-delay = <0>;
            thermal-sensors = <&pm8350_temp_alarm>;

            trips {
                pm8350_trip0: trip0 {
                    temperature = <95000>;
                    hysteresis = <0>;
                    type = "passive";
                };

                pm8350_crit: pm8350c-crit {
                    temperature = <115000>;
                    hysteresis = <0>;
                    type = "critical";
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2021 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Limits Management Hardware(LMh)

maintainers:
  - Thara Gopinath <thara.gopinath@linaro.org>

description:
  Limits Management Hardware(LMh) is a hardware infrastructure on some
  Qualcomm SoCs that can enforce temperature and current limits as
  programmed by software for certain IPs like CPU.

properties:
  compatible:
    enum:
      - qcom,sc8180x-lmh
      - qcom,sdm845-lmh
      - qcom,sm8150-lmh

  reg:
    items:
      - description: core registers

  interrupts:
    maxItems: 1

  '#interrupt-cells':
    const: 1

  interrupt-controller: true

  cpus:
    description:
      phandle of the first cpu in the LMh cluster
    maxItems: 1

  qcom,lmh-temp-arm-millicelsius:
    description:
      An integer expressing temperature threshold at which the LMh thermal
      FSM is engaged.

  qcom,lmh-temp-low-millicelsius:
    description:
      An integer expressing temperature threshold at which the state machine
      will attempt to remove frequency throttling.

  qcom,lmh-temp-high-millicelsius:
    description:
      An integer expressing temperature threshold at which the state machine
      will attempt to throttle the frequency.

required:
  - compatible
  - reg
  - interrupts
  - '#interrupt-cells'
  - interrupt-controller
  - cpus
  - qcom,lmh-temp-arm-millicelsius
  - qcom,lmh-temp-low-millicelsius
  - qcom,lmh-temp-high-millicelsius

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    lmh@17d70800 {
      compatible = "qcom,sdm845-lmh";
      reg = <0x17d70800 0x400>;
      interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
      cpus = <&CPU4>;
      qcom,lmh-temp-arm-millicelsius = <65000>;
      qcom,lmh-temp-low-millicelsius = <94500>;
      qcom,lmh-temp-high-millicelsius = <95000>;
      interrupt-controller;
      #interrupt-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm-hc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm's SPMI PMIC ADC HC Thermal Monitoring
maintainers:
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

properties:
  compatible:
    const: qcom,spmi-adc-tm-hc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#thermal-sensor-cells":
    const: 1
    description:
      Number of cells required to uniquely identify the thermal sensors. Since
      we have multiple sensors this is set to 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  qcom,avg-samples:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Number of samples to be used for measurement.
    enum:
      - 1
      - 2
      - 4
      - 8
      - 16
    default: 1

  qcom,decimation:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: This parameter is used to decrease ADC sampling rate.
            Quicker measurements can be made by reducing decimation ratio.
    enum:
      - 256
      - 512
      - 1024
    default: 1024

patternProperties:
  "^([-a-z0-9]*)@[0-7]$":
    type: object
    description:
      Represent one thermal sensor.

    properties:
      reg:
        description: Specify the sensor channel. There are 8 channels in PMIC5's ADC TM
        minimum: 0
        maximum: 7

      io-channels:
        description:
          From common IIO binding. Used to pipe PMIC ADC channel to thermal monitor

      qcom,ratiometric:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          Channel calibration type.
          If this property is specified VADC will use the VDD reference
          (1.875V) and GND for channel calibration. If property is not found,
          channel will be calibrated with 0V and 1.25V reference channels,
          also known as absolute calibration.

      qcom,hw-settle-time-us:
        description: Time between AMUX getting configured and the ADC starting conversion.
        enum: [0, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, 6000, 8000, 10000]

      qcom,pre-scaling:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        description: Used for scaling the channel input signal before the
          signal is fed to VADC. The configuration for this node is to know the
          pre-determined ratio and use it for post scaling. It is a pair of
          integers, denoting the numerator and denominator of the fraction by
          which input signal is multiplied. For example, <1 3> indicates the
          signal is scaled down to 1/3 of its value before ADC measurement.  If
          property is not found default value depending on chip will be used.
        items:
          - const: 1
          - enum: [ 1, 3, 4, 6, 20, 8, 10 ]

    required:
      - reg
      - io-channels

    additionalProperties:
      false

required:
  - compatible
  - reg
  - interrupts
  - "#address-cells"
  - "#size-cells"
  - "#thermal-sensor-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/iio/qcom,spmi-vadc.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    spmi_bus {
        #address-cells = <1>;
        #size-cells = <0>;
        pm8998_adc: adc@3100 {
            reg = <0x3100>;
            compatible = "qcom,spmi-adc-rev2";
            #address-cells = <1>;
            #size-cells = <0>;
            #io-channel-cells = <1>;

            /* Other propreties are omitted */
            adc-chan@4c {
                reg = <ADC5_XO_THERM_100K_PU>;
            };
        };

        pm8998_adc_tm: adc-tm@3400 {
            compatible = "qcom,spmi-adc-tm-hc";
            reg = <0x3400>;
            interrupts = <0x2 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
            #thermal-sensor-cells = <1>;
            #address-cells = <1>;
            #size-cells = <0>;

            thermistor@1 {
                reg = <1>;
                io-channels = <&pm8998_adc ADC5_XO_THERM_100K_PU>;
                qcom,ratiometric;
                qcom,hw-settle-time-us = <200>;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm's SPMI PMIC ADC Thermal Monitoring
maintainers:
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

properties:
  compatible:
    enum:
      - qcom,spmi-adc-tm5
      - qcom,spmi-adc-tm5-gen2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#thermal-sensor-cells":
    const: 1
    description:
      Number of cells required to uniquely identify the thermal sensors. Since
      we have multiple sensors this is set to 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  qcom,avg-samples:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Number of samples to be used for measurement.
            Not applicable for Gen2 ADC_TM peripheral.
    enum:
      - 1
      - 2
      - 4
      - 8
      - 16
    default: 1

  qcom,decimation:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: This parameter is used to decrease ADC sampling rate.
            Quicker measurements can be made by reducing decimation ratio.
            Not applicable for Gen2 ADC_TM peripheral.
    enum:
      - 250
      - 420
      - 840
    default: 840

patternProperties:
  "^([-a-z0-9]*)@[0-7]$":
    type: object
    description:
      Represent one thermal sensor.

    properties:
      reg:
        description: Specify the sensor channel. There are 8 channels in PMIC5's ADC TM
        minimum: 0
        maximum: 7

      io-channels:
        description:
          From common IIO binding. Used to pipe PMIC ADC channel to thermal monitor

      qcom,ratiometric:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          Channel calibration type.
          If this property is specified VADC will use the VDD reference
          (1.875V) and GND for channel calibration. If property is not found,
          channel will be calibrated with 0V and 1.25V reference channels,
          also known as absolute calibration.

      qcom,hw-settle-time-us:
        description: Time between AMUX getting configured and the ADC starting conversion.
        enum: [15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, 8000, 16000, 32000, 64000, 128000]

      qcom,pre-scaling:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        description: Used for scaling the channel input signal before the
          signal is fed to VADC. The configuration for this node is to know the
          pre-determined ratio and use it for post scaling. It is a pair of
          integers, denoting the numerator and denominator of the fraction by
          which input signal is multiplied. For example, <1 3> indicates the
          signal is scaled down to 1/3 of its value before ADC measurement.  If
          property is not found default value depending on chip will be used.
        items:
          - const: 1
          - enum: [ 1, 3, 4, 6, 20, 8, 10 ]

      qcom,avg-samples:
        $ref: /schemas/types.yaml#/definitions/uint32
        description: Number of samples to be used for measurement.
          This property in child node is applicable only for Gen2 ADC_TM peripheral.
        enum:
          - 1
          - 2
          - 4
          - 8
          - 16
        default: 1

      qcom,decimation:
        $ref: /schemas/types.yaml#/definitions/uint32
        description: This parameter is used to decrease ADC sampling rate.
          Quicker measurements can be made by reducing decimation ratio.
          This property in child node is applicable only for Gen2 ADC_TM peripheral.
        enum:
          - 85
          - 340
          - 1360
        default: 1360

    required:
      - reg
      - io-channels

    additionalProperties:
      false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: qcom,spmi-adc-tm5

    then:
      patternProperties:
        "^([-a-z0-9]*)@[0-7]$":
          properties:
            qcom,decimation: false
            qcom,avg-samples: false

  - if:
      properties:
        compatible:
          contains:
            const: qcom,spmi-adc-tm5-gen2

    then:
      properties:
        qcom,avg-samples: false
        qcom,decimation: false

required:
  - compatible
  - reg
  - interrupts
  - "#address-cells"
  - "#size-cells"
  - "#thermal-sensor-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/iio/qcom,spmi-vadc.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    spmi_bus {
        #address-cells = <1>;
        #size-cells = <0>;
        pm8150b_adc: adc@3100 {
            reg = <0x3100>;
            compatible = "qcom,spmi-adc5";
            #address-cells = <1>;
            #size-cells = <0>;
            #io-channel-cells = <1>;

            /* Other properties are omitted */
            conn-therm@4f {
                reg = <ADC5_AMUX_THM3_100K_PU>;
                qcom,ratiometric;
                qcom,hw-settle-time = <200>;
            };
        };

        pm8150b_adc_tm: adc-tm@3500 {
            compatible = "qcom,spmi-adc-tm5";
            reg = <0x3500>;
            interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
            #thermal-sensor-cells = <1>;
            #address-cells = <1>;
            #size-cells = <0>;

            conn-therm@0 {
                reg = <0>;
                io-channels = <&pm8150b_adc ADC5_AMUX_THM3_100K_PU>;
                qcom,ratiometric;
                qcom,hw-settle-time-us = <200>;
            };
        };
    };

  - |
    #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
    #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    spmi_bus {
        #address-cells = <1>;
        #size-cells = <0>;
        pmk8350_vadc: adc@3100 {
            reg = <0x3100>;
            compatible = "qcom,spmi-adc7";
            #address-cells = <1>;
            #size-cells = <0>;
            #io-channel-cells = <1>;

            /* Other properties are omitted */
            xo-therm@44 {
                reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
                qcom,ratiometric;
                qcom,hw-settle-time = <200>;
            };

            conn-therm@147 {
                reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
                qcom,ratiometric;
                qcom,hw-settle-time = <200>;
            };
        };

        pmk8350_adc_tm: adc-tm@3400 {
            compatible = "qcom,spmi-adc-tm5-gen2";
            reg = <0x3400>;
            interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
            #thermal-sensor-cells = <1>;
            #address-cells = <1>;
            #size-cells = <0>;

            pmk8350-xo-therm@0 {
                reg = <0>;
                io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
                qcom,decimation = <340>;
                qcom,ratiometric;
                qcom,hw-settle-time-us = <200>;
            };

            conn-therm@1 {
                reg = <1>;
                io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
                qcom,avg-samples = <2>;
                qcom,ratiometric;
                qcom,hw-settle-time-us = <200>;
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR MIT)
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: QCOM SoC Temperature Sensor (TSENS)

maintainers:
  - Amit Kucheria <amitk@kernel.org>

description: |
  QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
  three distinct major versions of the IP that is supported by a single driver.
  The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
  everything before v1 when there was no versioning information.

properties:
  compatible:
    oneOf:
      - description: msm8960 TSENS based
        items:
          - enum:
              - qcom,ipq8064-tsens
              - qcom,msm8960-tsens

      - description: v0.1 of TSENS
        items:
          - enum:
              - qcom,mdm9607-tsens
              - qcom,msm8916-tsens
              - qcom,msm8939-tsens
              - qcom,msm8974-tsens
          - const: qcom,tsens-v0_1

      - description: v1 of TSENS
        items:
          - enum:
              - qcom,msm8976-tsens
              - qcom,qcs404-tsens
          - const: qcom,tsens-v1

      - description: v2 of TSENS
        items:
          - enum:
              - qcom,msm8953-tsens
              - qcom,msm8996-tsens
              - qcom,msm8998-tsens
              - qcom,sc7180-tsens
              - qcom,sc7280-tsens
              - qcom,sc8180x-tsens
              - qcom,sc8280xp-tsens
              - qcom,sdm630-tsens
              - qcom,sdm845-tsens
              - qcom,sm6115-tsens
              - qcom,sm6350-tsens
              - qcom,sm8150-tsens
              - qcom,sm8250-tsens
              - qcom,sm8350-tsens
              - qcom,sm8450-tsens
              - qcom,sm8550-tsens
          - const: qcom,tsens-v2

      - description: v2 of TSENS with combined interrupt
        enum:
          - qcom,ipq8074-tsens

  reg:
    items:
      - description: TM registers
      - description: SROT registers

  interrupts:
    minItems: 1
    maxItems: 2

  interrupt-names:
    minItems: 1
    maxItems: 2

  nvmem-cells:
    minItems: 1
    maxItems: 2
    description:
      Reference to an nvmem node for the calibration data

  nvmem-cell-names:
    minItems: 1
    items:
      - const: calib
      - enum:
          - calib_backup
          - calib_sel

  "#qcom,sensors":
    description:
      Number of sensors enabled on this platform
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 16

  "#thermal-sensor-cells":
    const: 1
    description:
      Number of cells required to uniquely identify the thermal sensors. Since
      we have multiple sensors this is set to 1

required:
  - compatible
  - interrupts
  - interrupt-names
  - "#thermal-sensor-cells"
  - "#qcom,sensors"

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq8064-tsens
              - qcom,mdm9607-tsens
              - qcom,msm8916-tsens
              - qcom,msm8960-tsens
              - qcom,msm8974-tsens
              - qcom,msm8976-tsens
              - qcom,qcs404-tsens
              - qcom,tsens-v0_1
              - qcom,tsens-v1
    then:
      properties:
        interrupts:
          items:
            - description: Combined interrupt if upper or lower threshold crossed
        interrupt-names:
          items:
            - const: uplow

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8953-tsens
              - qcom,msm8996-tsens
              - qcom,msm8998-tsens
              - qcom,sc7180-tsens
              - qcom,sc7280-tsens
              - qcom,sc8180x-tsens
              - qcom,sc8280xp-tsens
              - qcom,sdm630-tsens
              - qcom,sdm845-tsens
              - qcom,sm6350-tsens
              - qcom,sm8150-tsens
              - qcom,sm8250-tsens
              - qcom,sm8350-tsens
              - qcom,sm8450-tsens
              - qcom,tsens-v2
    then:
      properties:
        interrupts:
          items:
            - description: Combined interrupt if upper or lower threshold crossed
            - description: Interrupt if critical threshold crossed
        interrupt-names:
          items:
            - const: uplow
            - const: critical

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq8074-tsens
    then:
      properties:
        interrupts:
          items:
            - description: Combined interrupt if upper, lower or critical thresholds crossed
        interrupt-names:
          items:
            - const: combined

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq8074-tsens
              - qcom,tsens-v0_1
              - qcom,tsens-v1
              - qcom,tsens-v2

    then:
      required:
        - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    // Example msm9860 based SoC (ipq8064):
    gcc: clock-controller {

           /* ... */

           tsens: thermal-sensor {
                compatible = "qcom,ipq8064-tsens";

                 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
                 nvmem-cell-names = "calib", "calib_backup";
                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
                 interrupt-names = "uplow";

                 #qcom,sensors = <11>;
                 #thermal-sensor-cells = <1>;
          };
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    // Example 1 (legacy: for pre v1 IP):
    tsens1: thermal-sensor@900000 {
           compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
           reg = <0x4a9000 0x1000>, /* TM */
                 <0x4a8000 0x1000>; /* SROT */

           nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
           nvmem-cell-names = "calib", "calib_sel";

           interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
           interrupt-names = "uplow";

           #qcom,sensors = <5>;
           #thermal-sensor-cells = <1>;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    // Example 2 (for any platform containing v1 of the TSENS IP):
    tsens2: thermal-sensor@4a9000 {
          compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
          reg = <0x004a9000 0x1000>, /* TM */
                <0x004a8000 0x1000>; /* SROT */

          nvmem-cells = <&tsens_caldata>;
          nvmem-cell-names = "calib";

          interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
          interrupt-names = "uplow";

          #qcom,sensors = <10>;
          #thermal-sensor-cells = <1>;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    // Example 3 (for any platform containing v2 of the TSENS IP):
    tsens3: thermal-sensor@c263000 {
           compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
           reg = <0xc263000 0x1ff>,
                 <0xc222000 0x1ff>;

           interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
                        <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
           interrupt-names = "uplow", "critical";

           #qcom,sensors = <13>;
           #thermal-sensor-cells = <1>;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    // Example 4 (for any IPQ8074 based SoC-s):
    tsens4: thermal-sensor@4a9000 {
           compatible = "qcom,ipq8074-tsens";
           reg = <0x4a9000 0x1000>,
                 <0x4a8000 0x1000>;

           interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
           interrupt-names = "combined";

           #qcom,sensors = <16>;
           #thermal-sensor-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/qoriq-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

properties:
  compatible:
    description: |
      The version of the device is determined by the TMU IP Block Revision
      Register (IPBRR0) at offset 0x0BF8.
      Table of correspondences between IPBRR0 values and example chips:
            Value           Device
            ----------      -----
            0x01900102      T1040
    enum:
      - fsl,qoriq-tmu
      - fsl,imx8mq-tmu

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  fsl,tmu-range:
    $ref: '/schemas/types.yaml#/definitions/uint32-array'
    description: |
      The values to be programmed into TTRnCR, as specified by the SoC
      reference manual. The first cell is TTR0CR, the second is TTR1CR, etc.
    maxItems: 4

  fsl,tmu-calibration:
    $ref: '/schemas/types.yaml#/definitions/uint32-matrix'
    description: |
      A list of cell pairs containing temperature calibration data, as
      specified by the SoC reference manual. The first cell of each pair
      is the value to be written to TTCFGR, and the second is the value
      to be written to TSCFGR.
    items:
      items:
        - description: value for TTCFGR
        - description: value for TSCFGR
    minItems: 1
    maxItems: 64

  little-endian:
    description: |
      boolean, if present, the TMU registers are little endian. If absent,
      the default is big endian.
    type: boolean

  clocks:
    maxItems: 1

  "#thermal-sensor-cells":
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - fsl,tmu-range
  - fsl,tmu-calibration
  - '#thermal-sensor-cells'

additionalProperties: false

examples:
  - |
    tmu@f0000 {
        compatible = "fsl,qoriq-tmu";
        reg = <0xf0000 0x1000>;
        interrupts = <18 2 0 0>;
        fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
        fsl,tmu-calibration = <0x00000000 0x00000025>,
                              <0x00000001 0x00000028>,
                              <0x00000002 0x0000002d>,
                              <0x00000003 0x00000031>,
                              <0x00000004 0x00000036>,
                              <0x00000005 0x0000003a>,
                              <0x00000006 0x00000040>,
                              <0x00000007 0x00000044>,
                              <0x00000008 0x0000004a>,
                              <0x00000009 0x0000004f>,
                              <0x0000000a 0x00000054>,
                              <0x00010000 0x0000000d>,
                              <0x00010001 0x00000013>,
                              <0x00010002 0x00000019>,
                              <0x00010003 0x0000001f>,
                              <0x00010004 0x00000025>,
                              <0x00010005 0x0000002d>,
                              <0x00010006 0x00000033>,
                              <0x00010007 0x00000043>,
                              <0x00010008 0x0000004b>,
                              <0x00010009 0x00000053>,
                              <0x00020000 0x00000010>,
                              <0x00020001 0x00000017>,
                              <0x00020002 0x0000001f>,
                              <0x00020003 0x00000029>,
                              <0x00020004 0x00000031>,
                              <0x00020005 0x0000003c>,
                              <0x00020006 0x00000042>,
                              <0x00020007 0x0000004d>,
                              <0x00020008 0x00000056>,
                              <0x00030000 0x00000012>,
                              <0x00030001 0x0000001d>;
        #thermal-sensor-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
# Copyright (C) 2020 Renesas Electronics Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/rcar-gen3-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car Gen3 Thermal Sensor

description:
  On most R-Car Gen3 and later SoCs, the thermal sensor controllers (TSC)
  control the thermal sensors (THS) which are the analog circuits for
  measuring temperature (Tj) inside the LSI.

maintainers:
  - Niklas Söderlund <niklas.soderlund@ragnatech.se>

properties:
  compatible:
    enum:
      - renesas,r8a774a1-thermal # RZ/G2M
      - renesas,r8a774b1-thermal # RZ/G2N
      - renesas,r8a774e1-thermal # RZ/G2H
      - renesas,r8a7795-thermal  # R-Car H3
      - renesas,r8a7796-thermal  # R-Car M3-W
      - renesas,r8a77961-thermal # R-Car M3-W+
      - renesas,r8a77965-thermal # R-Car M3-N
      - renesas,r8a77980-thermal # R-Car V3H
      - renesas,r8a779a0-thermal # R-Car V3U
      - renesas,r8a779f0-thermal # R-Car S4-8

  reg: true

  interrupts:
    items:
      - description: TEMP1 interrupt
      - description: TEMP2 interrupt
      - description: TEMP3 interrupt

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  "#thermal-sensor-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - power-domains
  - resets
  - "#thermal-sensor-cells"

if:
  properties:
    compatible:
      contains:
        enum:
          - renesas,r8a779a0-thermal
then:
  properties:
    reg:
      items:
        - description: TSC0 registers
        - description: TSC1 registers
        - description: TSC2 registers
        - description: TSC3 registers
        - description: TSC4 registers
else:
  properties:
    reg:
      minItems: 2
      items:
        - description: TSC1 registers
        - description: TSC2 registers
        - description: TSC3 registers
  if:
    not:
      properties:
        compatible:
          contains:
            enum:
              - renesas,r8a779f0-thermal
  then:
    required:
      - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    tsc: thermal@e6198000 {
            compatible = "renesas,r8a7795-thermal";
            reg = <0xe6198000 0x100>,
                  <0xe61a0000 0x100>,
                  <0xe61a8000 0x100>;
            interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 522>;
            power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
            resets = <&cpg 522>;
            #thermal-sensor-cells = <1>;
    };

    thermal-zones {
            sensor_thermal: sensor-thermal {
                    polling-delay-passive = <250>;
                    polling-delay = <1000>;
                    thermal-sensors = <&tsc 0>;

                    trips {
                            sensor1_crit: sensor1-crit {
                                    temperature = <90000>;
                                    hysteresis = <2000>;
                                    type = "critical";
                            };
                    };
            };
    };
  - |
    #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a779a0-sysc.h>

    tsc_r8a779a0: thermal@e6190000 {
            compatible = "renesas,r8a779a0-thermal";
            reg = <0xe6190000 0x200>,
                  <0xe6198000 0x200>,
                  <0xe61a0000 0x200>,
                  <0xe61a8000 0x200>,
                  <0xe61b0000 0x200>;
            clocks = <&cpg CPG_MOD 919>;
            power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
            resets = <&cpg 919>;
            #thermal-sensor-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
# Copyright (C) 2020 Renesas Electronics Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/rcar-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car Thermal

maintainers:
  - Niklas Söderlund <niklas.soderlund@ragnatech.se>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,thermal-r8a73a4 # R-Mobile APE6
              - renesas,thermal-r8a7779 # R-Car H1
          - const: renesas,rcar-thermal # Generic without thermal-zone
      - items:
          - enum:
              - renesas,thermal-r8a7742 # RZ/G1H
              - renesas,thermal-r8a7743 # RZ/G1M
              - renesas,thermal-r8a7744 # RZ/G1N
          - const: renesas,rcar-gen2-thermal # Generic thermal-zone
      - items:
          - enum:
              - renesas,thermal-r8a7790 # R-Car H2
              - renesas,thermal-r8a7791 # R-Car M2-W
              - renesas,thermal-r8a7792 # R-Car V2H
              - renesas,thermal-r8a7793 # R-Car M2-N
          - const: renesas,rcar-gen2-thermal # Generic thermal-zone
          - const: renesas,rcar-thermal # Generic without thermal-zone
      - items:
          - enum:
              - renesas,thermal-r8a774c0 # RZ/G2E
              - renesas,thermal-r8a77970 # R-Car V3M
              - renesas,thermal-r8a77990 # R-Car E3
              - renesas,thermal-r8a77995 # R-Car D3
  reg:
    description:
      Address ranges of the thermal registers. If more then one range is given
      the first one must be the common registers followed by each sensor
      according to the datasheet.
    minItems: 1
    maxItems: 4

  interrupts:
    minItems: 1
    maxItems: 3

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  "#thermal-sensor-cells":
    const: 0

required:
  - compatible
  - reg

allOf:
  - if:
      not:
        properties:
          compatible:
            contains:
              enum:
                - renesas,thermal-r8a73a4 # R-Mobile APE6
                - renesas,thermal-r8a7779 # R-Car H1
    then:
      required:
        - resets
        - '#thermal-sensor-cells'

  - if:
      not:
        properties:
          compatible:
            contains:
              const: renesas,thermal-r8a7779 # R-Car H1
    then:
      required:
        - interrupts
        - clocks
        - power-domains

additionalProperties: false

examples:
  # Example (non interrupt support)
  - |
    thermal@ffc48000 {
            compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
            reg = <0xffc48000 0x38>;
    };

  # Example (interrupt support)
  - |
    #include <dt-bindings/clock/r8a73a4-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    thermal@e61f0000 {
            compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
            reg = <0xe61f0000 0x14>, <0xe61f0100 0x38>,
                  <0xe61f0200 0x38>, <0xe61f0300 0x38>;
            interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
            power-domains = <&pd_c5>;
    };

  # Example (with thermal-zone)
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>

    thermal: thermal@e61f0000 {
      compatible = "renesas,thermal-r8a7790",
                   "renesas,rcar-gen2-thermal",
                   "renesas,rcar-thermal";
            reg = <0xe61f0000 0x10>, <0xe61f0100 0x38>;
            interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 522>;
            power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
            resets = <&cpg 522>;
            #thermal-sensor-cells = <0>;
    };

    thermal-zones {
            cpu_thermal: cpu-thermal {
                    polling-delay-passive = <1000>;
                    polling-delay = <5000>;

                    thermal-sensors = <&thermal>;

                    trips {
                            cpu-crit {
                                    temperature = <115000>;
                                    hysteresis = <0>;
                                    type = "critical";
                            };
                    };
                    cooling-maps {
                    };
            };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/rockchip-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Temperature Sensor ADC (TSADC) on Rockchip SoCs

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    enum:
      - rockchip,px30-tsadc
      - rockchip,rk3228-tsadc
      - rockchip,rk3288-tsadc
      - rockchip,rk3328-tsadc
      - rockchip,rk3368-tsadc
      - rockchip,rk3399-tsadc
      - rockchip,rk3568-tsadc
      - rockchip,rv1108-tsadc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 2

  clock-names:
    items:
      - const: tsadc
      - const: apb_pclk

  resets:
    minItems: 1
    maxItems: 3

  reset-names:
    minItems: 1
    items:
      - const: tsadc-apb
      - const: tsadc
      - const: tsadc-phy

  "#thermal-sensor-cells":
    const: 1

  rockchip,grf:
    description: The phandle of the syscon node for the general register file.
    $ref: /schemas/types.yaml#/definitions/phandle

  rockchip,hw-tshut-temp:
    description: The hardware-controlled shutdown temperature value.
    $ref: /schemas/types.yaml#/definitions/uint32

  rockchip,hw-tshut-mode:
    description: The hardware-controlled shutdown mode 0:CRU 1:GPIO.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]

  rockchip,hw-tshut-polarity:
    description: The hardware-controlled active polarity 0:LOW 1:HIGH.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - "#thermal-sensor-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/rk3288-cru.h>

    tsadc: tsadc@ff280000 {
        compatible = "rockchip,rk3288-tsadc";
        reg = <0xff280000 0x100>;
        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
        clock-names = "tsadc", "apb_pclk";
        resets = <&cru SRST_TSADC>;
        reset-names = "tsadc-apb";
        #thermal-sensor-cells = <1>;
        rockchip,hw-tshut-temp = <95000>;
        rockchip,hw-tshut-mode = <0>;
        rockchip,hw-tshut-polarity = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/rzg2l-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G2L Thermal Sensor Unit

description:
  On RZ/G2L SoCs, the thermal sensor unit (TSU) measures the
  temperature(Tj) inside the LSI.

maintainers:
  - Biju Das <biju.das.jz@bp.renesas.com>

properties:
  compatible:
    items:
      - enum:
          - renesas,r9a07g043-tsu # RZ/G2UL and RZ/Five
          - renesas,r9a07g044-tsu # RZ/G2{L,LC}
          - renesas,r9a07g054-tsu # RZ/V2L
      - const: renesas,rzg2l-tsu

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  "#thermal-sensor-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - power-domains
  - resets
  - "#thermal-sensor-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r9a07g044-cpg.h>

    tsu: thermal@10059400 {
            compatible = "renesas,r9a07g044-tsu",
                         "renesas,rzg2l-tsu";
            reg = <0x10059400 0x400>;
            clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
            resets = <&cpg R9A07G044_TSU_PRESETN>;
            power-domains = <&cpg>;
            #thermal-sensor-cells = <1>;
    };

    thermal-zones {
            cpu-thermal {
                    polling-delay-passive = <250>;
                    polling-delay = <1000>;
                    thermal-sensors = <&tsu 0>;

                    trips {
                            sensor_crit: sensor-crit {
                                    temperature = <125000>;
                                    hysteresis = <1000>;
                                    type = "critical";
                            };
                    };
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/samsung,exynos-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC Thermal Management Unit (TMU)

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |
  For multi-instance tmu each instance should have an alias correctly numbered
  in "aliases" node.

properties:
  compatible:
    enum:
      - samsung,exynos3250-tmu
      - samsung,exynos4412-tmu
      - samsung,exynos4210-tmu
      - samsung,exynos5250-tmu
      - samsung,exynos5260-tmu
        # For TMU channel 0, 1 on Exynos5420:
      - samsung,exynos5420-tmu
        # For TMU channels 2, 3 and 4 of Exynos5420:
      - samsung,exynos5420-tmu-ext-triminfo
      - samsung,exynos5433-tmu
      - samsung,exynos7-tmu

  clocks:
    minItems: 1
    maxItems: 3

  clock-names:
    minItems: 1
    maxItems: 3

  interrupts:
    description: |
      The Exynos TMU supports generating interrupts when reaching given
      temperature thresholds. Number of supported thermal trip points depends
      on the SoC (only first trip points defined in DT will be configured)::
       - most of SoC: 4
       - samsung,exynos5433-tmu: 8
       - samsung,exynos7-tmu: 8
    maxItems: 1

  reg:
    items:
      - description: TMU instance registers.
      - description: |
          Shared TMU registers.

          Note:: On Exynos5420, the TRIMINFO register is misplaced for TMU
          channels 2, 3 and 4 Use "samsung,exynos5420-tmu-ext-triminfo" in
          cases, there is a misplaced register, also provide clock to access
          that base.
          TRIMINFO at 0x1006c000 contains data for TMU channel 3
          TRIMINFO at 0x100a0000 contains data for TMU channel 4
          TRIMINFO at 0x10068000 contains data for TMU channel 2
    minItems: 1

  '#thermal-sensor-cells': true

  vtmu-supply:
    description: The regulator node supplying voltage to TMU.

required:
  - compatible
  - clocks
  - clock-names
  - interrupts
  - reg

allOf:
  - $ref: /schemas/thermal/thermal-sensor.yaml
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5420-tmu-ext-triminfo
    then:
      properties:
        clocks:
          items:
            - description:
                Operational clock for TMU channel.
            - description:
                Optional clock to access the shared registers (e.g. TRIMINFO) of TMU
                channel.
        clock-names:
          items:
            - const: tmu_apbif
            - const: tmu_triminfo_apbif
        reg:
          minItems: 2
          maxItems: 2
  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos5433-tmu
              - samsung,exynos7-tmu
    then:
      properties:
        clocks:
          items:
            - description:
                Operational clock for TMU channel.
            - description:
                Optional special clock for functional operation of TMU channel.
        clock-names:
          items:
            - const: tmu_apbif
            - const: tmu_sclk
        reg:
          minItems: 1
          maxItems: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos3250-tmu
              - samsung,exynos4412-tmu
              - samsung,exynos4210-tmu
              - samsung,exynos5250-tmu
              - samsung,exynos5260-tmu
              - samsung,exynos5420-tmu
    then:
      properties:
        clocks:
          minItems: 1
          maxItems: 1
        reg:
          minItems: 1
          maxItems: 1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos4.h>

    tmu@100c0000 {
        compatible = "samsung,exynos4412-tmu";
        reg = <0x100C0000 0x100>;
        interrupt-parent = <&combiner>;
        interrupts = <2 4>;
        #thermal-sensor-cells = <0>;
        clocks = <&clock CLK_TMU_APBIF>;
        clock-names = "tmu_apbif";
        vtmu-supply = <&ldo10_reg>;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tmu@10068000 {
        compatible = "samsung,exynos5420-tmu-ext-triminfo";
        reg = <0x10068000 0x100>, <0x1006c000 0x4>;
        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
        #thermal-sensor-cells = <0>;
        clocks = <&clock 318>, <&clock 318>; /* CLK_TMU */
        clock-names = "tmu_apbif", "tmu_triminfo_apbif";
        vtmu-supply = <&ldo7_reg>;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tmu@10060000 {
        compatible = "samsung,exynos5433-tmu";
        reg = <0x10060000 0x200>;
        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
        #thermal-sensor-cells = <0>;
        clocks = <&cmu_peris 3>, /* CLK_PCLK_TMU0_APBIF */
                 <&cmu_peris 35>; /* CLK_SCLK_TMU0 */
        clock-names = "tmu_apbif", "tmu_sclk";
        vtmu-supply = <&ldo3_reg>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/socionext,uniphier-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier thermal monitor

description: |
  This describes the devicetree bindings for thermal monitor supported by
  PVT(Process, Voltage and Temperature) monitoring unit implemented on
  Socionext UniPhier SoCs.

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

properties:
  compatible:
    enum:
      - socionext,uniphier-pxs2-thermal
      - socionext,uniphier-ld20-thermal
      - socionext,uniphier-pxs3-thermal
      - socionext,uniphier-nx1-thermal

  interrupts:
    maxItems: 1

  "#thermal-sensor-cells":
    const: 0

  socionext,tmod-calibration:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    maxItems: 2
    description:
      A pair of calibrated values referred from PVT, in case that the values
      aren't set on SoC, like a reference board.

required:
  - compatible
  - interrupts
  - "#thermal-sensor-cells"

additionalProperties: false

examples:
  - |
    // The UniPhier thermal should be a subnode of a "syscon" compatible node.

    sysctrl@61840000 {
        compatible = "socionext,uniphier-ld20-sysctrl",
                     "simple-mfd", "syscon";
        reg = <0x61840000 0x10000>;

        pvtctl: thermal {
            compatible = "socionext,uniphier-ld20-thermal";
            interrupts = <0 3 1>;
            #thermal-sensor-cells = <0>;
        };
    };


code:
* SPEAr Thermal

Required properties:
- compatible : "st,thermal-spear1340"
- reg : Address range of the thermal registers
- st,thermal-flags: flags used to enable thermal sensor

Example:

	thermal@fc000000 {
		compatible = "st,thermal-spear1340";
		reg = <0xfc000000 0x1000>;
		st,thermal-flags = <0x7000>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/sprd-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Spreadtrum thermal sensor controller bindings

maintainers:
  - Orson Zhai <orsonzhai@gmail.com>
  - Baolin Wang <baolin.wang7@gmail.com>
  - Chunyan Zhang <zhang.lyra@gmail.com>

properties:
  compatible:
    const: sprd,ums512-thermal

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: enable

  nvmem-cells:
    maxItems: 2
    description:
      Reference to nvmem nodes for the calibration data.

  nvmem-cell-names:
    items:
      - const: thm_sign_cal
      - const: thm_ratio_cal

  "#thermal-sensor-cells":
    const: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

patternProperties:
  "^([a-z]*-)?sensor(-section)?@[0-9]+$":
    type: object
    description:
      Represent one thermal sensor.

    properties:
      reg:
        description: Specify the sensor id.
        maxItems: 1

      nvmem-cells:
        maxItems: 1
        description:
          Reference to an nvmem node for the calibration data.

      nvmem-cell-names:
        const: sen_delta_cal

    required:
      - reg
      - nvmem-cells
      - nvmem-cell-names

    additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - nvmem-cells
  - nvmem-cell-names
  - "#thermal-sensor-cells"
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:
  - |
        ap_thm0: thermal@32200000 {
                compatible = "sprd,ums512-thermal";
                reg = <0x32200000 0x10000>;
                clock-names = "enable";
                clocks = <&aonapb_gate 32>;
                #thermal-sensor-cells = <1>;
                nvmem-cells = <&thm0_sign>, <&thm0_ratio>;
                nvmem-cell-names = "thm_sign_cal", "thm_ratio_cal";
                #address-cells = <1>;
                #size-cells = <0>;

                prometheus-sensor@0 {
                        reg = <0>;
                        nvmem-cells = <&thm0_sen0>;
                        nvmem-cell-names = "sen_delta_cal";
                };

                ank-sensor@1 {
                        reg = <1>;
                        nvmem-cells = <&thm0_sen1>;
                        nvmem-cell-names = "sen_delta_cal";
                };
        };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/st,stm32-thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 digital thermal sensor (DTS) binding

maintainers:
  - Pascal Paillet <p.paillet@foss.st.com>

properties:
  compatible:
    const: st,stm32-thermal

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: pclk

  "#thermal-sensor-cells":
    const: 0

required:
  - "#thermal-sensor-cells"
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    dts: thermal@50028000 {
        compatible = "st,stm32-thermal";
        reg = <0x50028000 0x100>;
        clocks = <&rcc TMPSENS>;
        clock-names = "pclk";
        #thermal-sensor-cells = <0>;
        interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
    };

    thermal-zones {
        cpu_thermal: cpu-thermal {
            polling-delay-passive = <0>;
            polling-delay = <0>;

            thermal-sensors = <&dts>;
            trips {
                cpu_alert1: cpu-alert1 {
                    temperature = <85000>;
                    hysteresis = <0>;
                    type = "passive";
                };

                cpu_crit: cpu-crit {
                    temperature = <120000>;
                    hysteresis = <0>;
                    type = "critical";
                };
            };

            cooling-maps {
            };
        };
    };
...


code:
Binding for Thermal Sensor driver for STMicroelectronics STi series of SoCs.

Required parameters:
-------------------

compatible : 	Should be "st,stih407-thermal"

clock-names : 	Should be "thermal".
		  See: Documentation/devicetree/bindings/resource-names.txt
clocks : 	Phandle of the clock used by the thermal sensor.
		  See: Documentation/devicetree/bindings/clock/clock-bindings.txt

Optional parameters:
-------------------

reg : 		For non-sysconf based sensors, this should be the physical base
		address and length of the sensor's registers.
interrupts :	Standard way to define interrupt number.
		  NB: For thermal sensor's for which no interrupt has been
		  defined, a polling delay of 1000ms will be used to read the
		  temperature from device.

Example:

	temp0@91a0000 {
		compatible = "st,stih407-thermal";
		reg = <0x91a0000 0x28>;
		clock-names = "thermal";
		clocks = <&CLK_SYSIN>;
		interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
		st,passive_cooling_temp = <110>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0)
# Copyright 2020 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/thermal-cooling-devices.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Thermal cooling device binding

maintainers:
  - Amit Kucheria <amitk@kernel.org>

description: |
  Thermal management is achieved in devicetree by describing the sensor hardware
  and the software abstraction of cooling devices and thermal zones required to
  take appropriate action to mitigate thermal overload.

  The following node types are used to completely describe a thermal management
  system in devicetree:
   - thermal-sensor: device that measures temperature, has SoC-specific bindings
   - cooling-device: device used to dissipate heat either passively or actively
   - thermal-zones: a container of the following node types used to describe all
     thermal data for the platform

  This binding describes the cooling devices.

  There are essentially two ways to provide control on power dissipation:
    - Passive cooling: by means of regulating device performance. A typical
      passive cooling mechanism is a CPU that has dynamic voltage and frequency
      scaling (DVFS), and uses lower frequencies as cooling states.
    - Active cooling: by means of activating devices in order to remove the
      dissipated heat, e.g. regulating fan speeds.

  Any cooling device has a range of cooling states (i.e. different levels of
  heat dissipation). They also have a way to determine the state of cooling in
  which the device is. For example, a fan's cooling states correspond to the
  different fan speeds possible. Cooling states are referred to by single
  unsigned integers, where larger numbers mean greater heat dissipation. The
  precise set of cooling states associated with a device should be defined in
  a particular device's binding.

select: true

properties:
  "#cooling-cells":
    description:
      Must be 2, in order to specify minimum and maximum cooling state used in
      the cooling-maps reference. The first cell is the minimum cooling state
      and the second cell is the maximum cooling state requested.
    const: 2

additionalProperties: true

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/thermal/thermal.h>

    // Example 1: Cpufreq cooling device on CPU0
    cpus {
            #address-cells = <2>;
            #size-cells = <0>;

            CPU0: cpu@0 {
                    device_type = "cpu";
                    compatible = "qcom,kryo385";
                    reg = <0x0 0x0>;
                    enable-method = "psci";
                    cpu-idle-states = <&LITTLE_CPU_SLEEP_0>,
                                      <&LITTLE_CPU_SLEEP_1>,
                                      <&CLUSTER_SLEEP_0>;
                    capacity-dmips-mhz = <607>;
                    dynamic-power-coefficient = <100>;
                    qcom,freq-domain = <&cpufreq_hw 0>;
                    #cooling-cells = <2>;
                    next-level-cache = <&L2_0>;
                    L2_0: l2-cache {
                            compatible = "cache";
                            cache-unified;
                            cache-level = <2>;
                            next-level-cache = <&L3_0>;
                            L3_0: l3-cache {
                                    compatible = "cache";
                                    cache-unified;
                                    cache-level = <3>;
                            };
                    };
          };

          /* ... */

    };

    /* ... */

    thermal-zones {
            cpu0-thermal {
                    polling-delay-passive = <250>;
                    polling-delay = <1000>;

                    thermal-sensors = <&tsens0 1>;

                    trips {
                            cpu0_alert0: trip-point0 {
                                    temperature = <90000>;
                                    hysteresis = <2000>;
                                    type = "passive";
                            };
                    };

                    cooling-maps {
                            map0 {
                                    trip = <&cpu0_alert0>;
                                    /* Corresponds to 1000MHz in OPP table */
                                    cooling-device = <&CPU0 5 5>;
                            };
                    };
            };

            /* ... */
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2020 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Thermal idle cooling device binding

maintainers:
  - Daniel Lezcano <daniel.lezcano@linaro.org>

description: |
  The thermal idle cooling device allows the system to passively
  mitigate the temperature on the device by injecting idle cycles,
  forcing it to cool down.

  This binding describes the thermal idle node.

properties:
  $nodename:
    const: thermal-idle
    description: |
      A thermal-idle node describes the idle cooling device properties to
      cool down efficiently the attached thermal zone.

  '#cooling-cells':
    const: 2
    description: |
      Must be 2, in order to specify minimum and maximum cooling state used in
      the cooling-maps reference. The first cell is the minimum cooling state
      and the second cell is the maximum cooling state requested.

  duration-us:
    description: |
      The idle duration in microsecond the device should cool down.

  exit-latency-us:
    description: |
      The exit latency constraint in microsecond for the injected idle state
      for the device. It is the latency constraint to apply when selecting an
      idle state from among all the present ones.

required:
  - '#cooling-cells'

additionalProperties: false

examples:
  - |
    /{
        #include <dt-bindings/thermal/thermal.h>

        compatible = "foo";
        model = "foo";
        #address-cells = <1>;
        #size-cells = <1>;

        // Example: Combining idle cooling device on big CPUs with cpufreq cooling device
        cpus {
            #address-cells = <2>;
            #size-cells = <0>;

            /* ... */

            cpu_b0: cpu@100 {
                device_type = "cpu";
                compatible = "arm,cortex-a72";
                reg = <0x0 0x100>;
                enable-method = "psci";
                capacity-dmips-mhz = <1024>;
                dynamic-power-coefficient = <436>;
                #cooling-cells = <2>; /* min followed by max */
                cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>;
                cpu_b0_therm: thermal-idle {
                    #cooling-cells = <2>;
                    duration-us = <10000>;
                    exit-latency-us = <500>;
                };
            };

            cpu_b1: cpu@101 {
                device_type = "cpu";
                compatible = "arm,cortex-a72";
                reg = <0x0 0x101>;
                enable-method = "psci";
                capacity-dmips-mhz = <1024>;
                dynamic-power-coefficient = <436>;
                #cooling-cells = <2>; /* min followed by max */
                cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>;
                cpu_b1_therm: thermal-idle {
                    #cooling-cells = <2>;
                    duration-us = <10000>;
                    exit-latency-us = <500>;
                };
            };

            /* ... */

        };

        /* ... */

        thermal_zones {
            cpu_thermal: cpu {
                polling-delay-passive = <100>;
                polling-delay = <1000>;

                /* ... */

                trips {
                    cpu_alert0: cpu_alert0 {
                        temperature = <65000>;
                        hysteresis = <2000>;
                        type = "passive";
                    };

                    cpu_alert1: cpu_alert1 {
                        temperature = <70000>;
                        hysteresis = <2000>;
                        type = "passive";
                    };

                    cpu_alert2: cpu_alert2 {
                        temperature = <75000>;
                        hysteresis = <2000>;
                        type = "passive";
                    };

                    cpu_crit: cpu_crit {
                        temperature = <95000>;
                        hysteresis = <2000>;
                        type = "critical";
                    };
                };

                cooling-maps {
                    map0 {
                        trip = <&cpu_alert1>;
                        cooling-device = <&cpu_b0_therm 0 15 >,
                                         <&cpu_b1_therm 0 15>;
                    };

                    map1 {
                        trip = <&cpu_alert2>;
                        cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
                                         <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0)
# Copyright 2020 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/thermal-sensor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Thermal sensor binding

maintainers:
  - Amit Kucheria <amitk@kernel.org>

description: |
  Thermal management is achieved in devicetree by describing the sensor hardware
  and the software abstraction of thermal zones required to take appropriate
  action to mitigate thermal overloads.

  The following node types are used to completely describe a thermal management
  system in devicetree:
   - thermal-sensor: device that measures temperature, has SoC-specific bindings
   - cooling-device: device used to dissipate heat either passively or actively
   - thermal-zones: a container of the following node types used to describe all
     thermal data for the platform

  This binding describes the thermal-sensor.

  Thermal sensor devices provide temperature sensing capabilities on thermal
  zones. Typical devices are I2C ADC converters and bandgaps. Thermal sensor
  devices may control one or more internal sensors.

properties:
  "#thermal-sensor-cells":
    description:
      Used to uniquely identify a thermal sensor instance within an IC. Will be
      0 on sensor nodes with only a single sensor and at least 1 on nodes
      containing several internal sensors.
    enum: [0, 1]

required:
  - "#thermal-sensor-cells"

additionalProperties: true

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    // Example 1: SDM845 TSENS
    soc: soc {
            #address-cells = <2>;
            #size-cells = <2>;

            /* ... */

            tsens0: thermal-sensor@c263000 {
                    compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
                    reg = <0 0x0c263000 0 0x1ff>, /* TM */
                          <0 0x0c222000 0 0x1ff>; /* SROT */
                    #qcom,sensors = <13>;
                    interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
                                 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
                    interrupt-names = "uplow", "critical";
                    #thermal-sensor-cells = <1>;
            };

            tsens1: thermal-sensor@c265000 {
                    compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
                    reg = <0 0x0c265000 0 0x1ff>, /* TM */
                          <0 0x0c223000 0 0x1ff>; /* SROT */
                    #qcom,sensors = <8>;
                    interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
                                 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
                    interrupt-names = "uplow", "critical";
                    #thermal-sensor-cells = <1>;
            };
    };
...