code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mm.dtsi"

/ {
	chosen {
		stdout-path = &uart1;
	};

	aliases {
		rtc0 = &rtc_i2c;
		rtc1 = &snvs_rtc;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		brightness-levels = <0 45 63 88 119 158 203 255>;
		default-brightness-level = <4>;
		/* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
		enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
		power-supply = <&reg_3p3v>;
		/* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
		pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
		status = "disabled";
	};

	/* Fixed clock dedicated to SPI CAN controller */
	clk40m: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <40000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;

		key-wakeup {
			debounce-interval = <10>;
			/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
			gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
			label = "Wake-Up";
			linux,code = <KEY_WAKEUP>;
			wakeup-source;
		};
	};

	hdmi_connector: hdmi-connector {
		compatible = "hdmi-connector";
		ddc-i2c-bus = <&i2c2>;
		label = "hdmi";
		type = "a";
		status = "disabled";
	};

	panel_lvds: panel-lvds {
		compatible = "panel-lvds";
		backlight = <&backlight>;
		data-mapping = "vesa-24";
		status = "disabled";
	};

	/* Carrier Board Supplies */
	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <1800000>;
		regulator-min-microvolt = <1800000>;
		regulator-name = "+V1.8_SW";
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "+V3.3_SW";
	};

	reg_5p0v: regulator-5p0v {
		compatible = "regulator-fixed";
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "+V5_SW";
	};

	/* Non PMIC On-module Supplies */
	reg_ethphy: regulator-ethphy {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
		off-on-delay = <500000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_eth>;
		regulator-boot-on;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "On-module +V3.3_ETH";
		startup-delay-us = <200000>;
	};

	reg_usb_otg1_vbus: regulator-usb-otg1 {
		compatible = "regulator-fixed";
		enable-active-high;
		/* Verdin USB_1_EN (SODIMM 155) */
		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb1_en>;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "USB_1_EN";
	};

	reg_usb_otg2_vbus: regulator-usb-otg2 {
		compatible = "regulator-fixed";
		enable-active-high;
		/* Verdin USB_2_EN (SODIMM 185) */
		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb2_en>;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "USB_2_EN";
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		enable-active-high;
		/* Verdin SD_1_PWR_EN (SODIMM 76) */
		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
		off-on-delay = <100000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "+V3.3_SD";
		startup-delay-us = <2000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* Use the kernel configuration settings instead */
		/delete-node/ linux,cma;
	};
};

&A53_0 {
	cpu-supply = <&reg_vdd_arm>;
};

&A53_1 {
	cpu-supply = <&reg_vdd_arm>;
};

&A53_2 {
	cpu-supply = <&reg_vdd_arm>;
};

&A53_3 {
	cpu-supply = <&reg_vdd_arm>;
};

&cpu_alert0 {
	temperature = <95000>;
};

&cpu_crit0 {
	temperature = <105000>;
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

/* Verdin SPI_1 */
&ecspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
};

/* Verdin CAN_1 (On-module) */
&ecspi3 {
	#address-cells = <1>;
	#size-cells = <0>;
	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3>;
	status = "okay";

	can1: can@0 {
		compatible = "microchip,mcp251xfd";
		clocks = <&clk40m>;
		interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_can1_int>;
		reg = <0>;
		spi-max-frequency = <8500000>;
	};
};

/* Verdin ETH_1 (On-module PHY) */
&fec1 {
	fsl,magic-packet;
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-id";
	phy-supply = <&reg_ethphy>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_fec1>;
	pinctrl-1 = <&pinctrl_fec1_sleep>;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@7 {
			compatible = "ethernet-phy-ieee802.3-c22";
			interrupt-parent = <&gpio1>;
			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
			micrel,led-mode = <0>;
			reg = <7>;
		};
	};
};

/* Verdin QSPI_1 */
&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
};

&gpio1 {
	gpio-line-names = "SODIMM_216",
			  "SODIMM_19",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_220",
			  "SODIMM_222",
			  "",
			  "SODIMM_218",
			  "SODIMM_155",
			  "SODIMM_157",
			  "SODIMM_185",
			  "SODIMM_187";
};

&gpio2 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_84",
			  "SODIMM_78",
			  "SODIMM_74",
			  "SODIMM_80",
			  "SODIMM_82",
			  "SODIMM_70",
			  "SODIMM_72";
};

&gpio5 {
	gpio-line-names = "SODIMM_131",
			  "",
			  "SODIMM_91",
			  "SODIMM_16",
			  "SODIMM_15",
			  "SODIMM_208",
			  "SODIMM_137",
			  "SODIMM_139",
			  "SODIMM_141",
			  "SODIMM_143",
			  "SODIMM_196",
			  "SODIMM_200",
			  "SODIMM_198",
			  "SODIMM_202",
			  "",
			  "",
			  "SODIMM_55",
			  "SODIMM_53",
			  "SODIMM_95",
			  "SODIMM_93",
			  "SODIMM_14",
			  "SODIMM_12",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_210",
			  "SODIMM_212",
			  "SODIMM_151",
			  "SODIMM_153";

	ctrl-sleep-moci-hog {
		gpio-hog;
		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
		gpios = <1 GPIO_ACTIVE_HIGH>;
		line-name = "CTRL_SLEEP_MOCI#";
		output-high;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
	};
};

/* On-module I2C */
&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	pca9450: pmic@25 {
		compatible = "nxp,pca9450a";
		interrupt-parent = <&gpio1>;
		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		reg = <0x25>;
		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;

		/*
		 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
		 * behind this PMIC.
		 */

		regulators {
			reg_vdd_soc: BUCK1 {
				nxp,dvs-run-voltage = <850000>;
				nxp,dvs-standby-voltage = <800000>;
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <850000>;
				regulator-min-microvolt = <800000>;
				regulator-name = "On-module +VDD_SOC (BUCK1)";
				regulator-ramp-delay = <3125>;
			};

			reg_vdd_arm: BUCK2 {
				nxp,dvs-run-voltage = <950000>;
				nxp,dvs-standby-voltage = <850000>;
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1050000>;
				regulator-min-microvolt = <805000>;
				regulator-name = "On-module +VDD_ARM (BUCK2)";
				regulator-ramp-delay = <3125>;
			};

			reg_vdd_dram: BUCK3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1000000>;
				regulator-min-microvolt = <805000>;
				regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
			};

			reg_vdd_3v3: BUCK4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <3300000>;
				regulator-name = "On-module +V3.3 (BUCK4)";
			};

			reg_vdd_1v8: BUCK5 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1800000>;
				regulator-min-microvolt = <1800000>;
				regulator-name = "PWR_1V8_MOCI (BUCK5)";
			};

			reg_nvcc_dram: BUCK6 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1100000>;
				regulator-min-microvolt = <1100000>;
				regulator-name = "On-module +VDD_DDR (BUCK6)";
			};

			reg_nvcc_snvs: LDO1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1800000>;
				regulator-min-microvolt = <1800000>;
				regulator-name = "On-module +V1.8_SNVS (LDO1)";
			};

			reg_vdd_snvs: LDO2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <800000>;
				regulator-min-microvolt = <800000>;
				regulator-name = "On-module +V0.8_SNVS (LDO2)";
			};

			reg_vdda: LDO3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <1800000>;
				regulator-min-microvolt = <1800000>;
				regulator-name = "On-module +V1.8A (LDO3)";
			};

			reg_vdd_phy: LDO4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-max-microvolt = <900000>;
				regulator-min-microvolt = <900000>;
				regulator-name = "On-module +V0.9_MIPI (LDO4)";
			};

			reg_nvcc_sd: LDO5 {
				regulator-max-microvolt = <3300000>;
				regulator-min-microvolt = <1800000>;
				regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
			};
		};
	};

	rtc_i2c: rtc@32 {
		compatible = "epson,rx8130";
		reg = <0x32>;
	};

	adc@49 {
		compatible = "ti,ads1015";
		reg = <0x49>;
		#address-cells = <1>;
		#size-cells = <0>;

		/* Verdin I2C_1 (ADC_4 - ADC_3) */
		channel@0 {
			reg = <0>;
			ti,datarate = <4>;
			ti,gain = <2>;
		};

		/* Verdin I2C_1 (ADC_4 - ADC_1) */
		channel@1 {
			reg = <1>;
			ti,datarate = <4>;
			ti,gain = <2>;
		};

		/* Verdin I2C_1 (ADC_3 - ADC_1) */
		channel@2 {
			reg = <2>;
			ti,datarate = <4>;
			ti,gain = <2>;
		};

		/* Verdin I2C_1 (ADC_2 - ADC_1) */
		channel@3 {
			reg = <3>;
			ti,datarate = <4>;
			ti,gain = <2>;
		};

		/* Verdin I2C_1 ADC_4 */
		channel@4 {
			reg = <4>;
			ti,datarate = <4>;
			ti,gain = <2>;
		};

		/* Verdin I2C_1 ADC_3 */
		channel@5 {
			reg = <5>;
			ti,datarate = <4>;
			ti,gain = <2>;
		};

		/* Verdin I2C_1 ADC_2 */
		channel@6 {
			reg = <6>;
			ti,datarate = <4>;
			ti,gain = <2>;
		};

		/* Verdin I2C_1 ADC_1 */
		channel@7 {
			reg = <7>;
			ti,datarate = <4>;
			ti,gain = <2>;
		};
	};

	eeprom@50 {
		compatible = "st,24c02";
		pagesize = <16>;
		reg = <0x50>;
	};
};

/* Verdin I2C_2_DSI */
&i2c2 {
	clock-frequency = <10000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "disabled";
};

/* Verdin I2C_3_HDMI N/A */

/* Verdin I2C_4_CSI */
&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};

/* Verdin I2C_1 */
&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;

	gpio_expander_21: gpio-expander@21 {
		compatible = "nxp,pcal6416";
		#gpio-cells = <2>;
		gpio-controller;
		reg = <0x21>;
		vcc-supply = <&reg_3p3v>;
		status = "disabled";
	};

	lvds_ti_sn65dsi84: bridge@2c {
		compatible = "ti,sn65dsi84";
		/* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
		/* Verdin GPIO_10_DSI (SODIMM 21) */
		enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_10_dsi>;
		reg = <0x2c>;
		status = "disabled";
	};

	/* Current measurement into module VCC */
	hwmon: hwmon@40 {
		compatible = "ti,ina219";
		reg = <0x40>;
		shunt-resistor = <10000>;
		status = "disabled";
	};

	hdmi_lontium_lt8912: hdmi@48 {
		compatible = "lontium,lt8912b";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
		reg = <0x48>;
		/* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
		/* Verdin GPIO_10_DSI (SODIMM 21) */
		reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
		status = "disabled";
	};

	atmel_mxt_ts: touch@4a {
		compatible = "atmel,maxtouch";
		/*
		 * Verdin GPIO_9_DSI
		 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
		 */
		interrupt-parent = <&gpio3>;
		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
		reg = <0x4a>;
		/* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
		reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
		status = "disabled";
	};

	/* Temperature sensor on carrier board */
	hwmon_temp: sensor@4f {
		compatible = "ti,tmp75c";
		reg = <0x4f>;
		status = "disabled";
	};

	/* EEPROM on display adapter (MIPI DSI Display Adapter) */
	eeprom_display_adapter: eeprom@50 {
		compatible = "st,24c02";
		pagesize = <16>;
		reg = <0x50>;
		status = "disabled";
	};

	/* EEPROM on carrier board */
	eeprom_carrier_board: eeprom@57 {
		compatible = "st,24c02";
		pagesize = <16>;
		reg = <0x57>;
		status = "disabled";
	};
};

/* Verdin PCIE_1 */
&pcie0 {
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_250M>;
	assigned-clock-rates = <10000000>, <250000000>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
		 <&clk IMX8MM_CLK_PCIE1_AUX>,
		 <&clk IMX8MM_CLK_PCIE1_PHY>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	/* PCIE_1_RESET# (SODIMM 244) */
	reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
};

&pcie_phy {
	clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
	clock-names = "ref";
	fsl,clkreq-unsupported;
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
	fsl,tx-deemph-gen1 = <0x2d>;
	fsl,tx-deemph-gen2 = <0xf>;
};

/* Verdin PWM_3_DSI */
&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_1>;
	#pwm-cells = <3>;
};

/* Verdin PWM_1 */
&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_2>;
	#pwm-cells = <3>;
};

/* Verdin PWM_2 */
&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_3>;
	#pwm-cells = <3>;
};

/* Verdin I2S_1 */
&sai2 {
	#sound-dai-cells = <0>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
};

&snvs_pwrkey {
	status = "okay";
};

/* Verdin UART_3, used as the Linux console */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
};

/* Verdin UART_1 */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	uart-has-rtscts;
};

/* Verdin UART_2 */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
};

/*
 * Verdin UART_4
 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
 */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
};

/* Verdin USB_1 */
&usbotg1 {
	adp-disable;
	dr_mode = "otg";
	hnp-disable;
	over-current-active-low;
	samsung,picophy-dc-vol-level-adjust = <7>;
	samsung,picophy-pre-emp-curr-control = <3>;
	srp-disable;
	vbus-supply = <&reg_usb_otg1_vbus>;
};

/* Verdin USB_2 */
&usbotg2 {
	dr_mode = "host";
	over-current-active-low;
	samsung,picophy-dc-vol-level-adjust = <7>;
	samsung,picophy-pre-emp-curr-control = <3>;
	vbus-supply = <&reg_usb_otg2_vbus>;
};

&usbphynop1 {
	vcc-supply = <&reg_vdd_3v3>;
};

&usbphynop2 {
	power-domains = <&pgc_otg2>;
	vcc-supply = <&reg_vdd_3v3>;
};

/* On-module eMMC */
&usdhc1 {
	bus-width = <8>;
	keep-power-in-suspend;
	non-removable;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	status = "okay";
};

/* Verdin SD_1 */
&usdhc2 {
	bus-width = <4>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	disable-wp;
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
};

&wdog1 {
	fsl,ext-reset-output;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
		    <&pinctrl_gpio3>, <&pinctrl_gpio4>,
		    <&pinctrl_gpio7>, <&pinctrl_gpio8>,
		    <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
		    <&pinctrl_pmic_tpm_ena>;

	pinctrl_can1_int: can1intgrp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x146>;	/* CAN_1_SPI_INT#_1.8V */
	};

	pinctrl_can2_int: can2intgrp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x106>;	/* CAN_2_SPI_INT#_1.8V, unused */
	};

	pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1		0x106>;	/* SODIMM 256 */
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins =
			<MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x6>,	/* SODIMM 198 */
			<MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x6>,	/* SODIMM 200 */
			<MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x6>,	/* SODIMM 196 */
			<MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x6>;	/* SODIMM 202 */
	};

	pinctrl_ecspi3: ecspi3grp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x146>,	/* CAN_2_SPI_CS#_1.8V */
			<MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK		0x6>,	/* CAN_SPI_SCK_1.8V */
			<MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI		0x6>,	/* CAN_SPI_MOSI_1.8V */
			<MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO		0x6>,	/* CAN_SPI_MISO_1.8V */
			<MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25		0x6>;	/* CAN_1_SPI_CS_1.8V# */
	};

	pinctrl_fec1: fec1grp {
		fsl,pins =
			<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
			<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3>,
			<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91>,
			<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91>,
			<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91>,
			<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91>,
			<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91>,
			<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
			<MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f>,
			<MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f>,
			<MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f>,
			<MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f>,
			<MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f>,
			<MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f>,
			<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x146>;
	};

	pinctrl_fec1_sleep: fec1-sleepgrp {
		fsl,pins =
			<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
			<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3>,
			<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91>,
			<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91>,
			<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91>,
			<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91>,
			<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91>,
			<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
			<MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21		0x1f>,
			<MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20		0x1f>,
			<MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19		0x1f>,
			<MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18		0x1f>,
			<MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23		0x1f>,
			<MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x1f>,
			<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x106>;
	};

	pinctrl_flexspi0: flexspi0grp {
		fsl,pins =
			<MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x106>,	/* SODIMM 52 */
			<MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x106>,	/* SODIMM 54 */
			<MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B		0x106>,	/* SODIMM 64 */
			<MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x106>,	/* SODIMM 56 */
			<MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x106>,	/* SODIMM 58 */
			<MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x106>,	/* SODIMM 60 */
			<MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x106>,	/* SODIMM 62 */
			<MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS		0x106>;	/* SODIMM 66 */
	};

	pinctrl_gpio1: gpio1grp {
		fsl,pins =
			<MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x106>;	/* SODIMM 206 */
	};

	pinctrl_gpio2: gpio2grp {
		fsl,pins =
			<MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5		0x106>;	/* SODIMM 208 */
	};

	pinctrl_gpio3: gpio3grp {
		fsl,pins =
			<MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26		0x106>;	/* SODIMM 210 */
	};

	pinctrl_gpio4: gpio4grp {
		fsl,pins =
			<MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27		0x106>;	/* SODIMM 212 */
	};

	pinctrl_gpio5: gpio5grp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x106>;	/* SODIMM 216 */
	};

	pinctrl_gpio6: gpio6grp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x106>;	/* SODIMM 218 */
	};

	pinctrl_gpio7: gpio7grp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x106>;	/* SODIMM 220 */
	};

	pinctrl_gpio8: gpio8grp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x106>;	/* SODIMM 222 */
	};

	/* Verdin GPIO_9_DSI (pulled-up as active-low) */
	pinctrl_gpio_9_dsi: gpio9dsigrp {
		fsl,pins =
			<MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15		0x146>;	/* SODIMM 17 */
	};

	/* Verdin GPIO_10_DSI (pulled-up as active-low) */
	pinctrl_gpio_10_dsi: gpio10dsigrp {
		fsl,pins =
			<MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x146>;	/* SODIMM 21 */
	};

	pinctrl_gpio_hog1: gpiohog1grp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20		0x106>,	/* SODIMM 88 */
			<MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1		0x106>,	/* SODIMM 90 */
			<MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2		0x106>,	/* SODIMM 92 */
			<MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3		0x106>,	/* SODIMM 94 */
			<MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4		0x106>,	/* SODIMM 96 */
			<MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5		0x106>,	/* SODIMM 100 */
			<MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0		0x106>,	/* SODIMM 102 */
			<MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11		0x106>,	/* SODIMM 104 */
			<MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12		0x106>,	/* SODIMM 106 */
			<MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13		0x106>,	/* SODIMM 108 */
			<MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14		0x106>,	/* SODIMM 112 */
			<MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15		0x106>,	/* SODIMM 114 */
			<MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x106>,	/* SODIMM 116 */
			<MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x106>,	/* SODIMM 118 */
			<MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x106>;	/* SODIMM 120 */
	};

	pinctrl_gpio_hog2: gpiohog2grp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x106>;	/* SODIMM 91 */
	};

	pinctrl_gpio_hog3: gpiohog3grp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x146>,	/* SODIMM 157 */
			<MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x146>;	/* SODIMM 187 */
	};

	pinctrl_gpio_keys: gpiokeysgrp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28		0x146>;	/* SODIMM 252 */
	};

	/* On-module I2C */
	pinctrl_i2c1: i2c1grp {
		fsl,pins =
			<MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x40000146>,	/* PMIC_I2C_SCL */
			<MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x40000146>;	/* PMIC_I2C_SDA */
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins =
			<MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14		0x146>,	/* PMIC_I2C_SCL */
			<MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15		0x146>;	/* PMIC_I2C_SDA */
	};

	/* Verdin I2C_4_CSI */
	pinctrl_i2c2: i2c2grp {
		fsl,pins =
			<MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x40000146>,	/* SODIMM 55 */
			<MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x40000146>;	/* SODIMM 53 */
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins =
			<MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x146>,	/* SODIMM 55 */
			<MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x146>;	/* SODIMM 53 */
	};

	/* Verdin I2C_2_DSI */
	pinctrl_i2c3: i2c3grp {
		fsl,pins =
			<MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000146>,	/* SODIMM 95 */
			<MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000146>;	/* SODIMM 93 */
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins =
			<MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x146>,	/* SODIMM 95 */
			<MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x146>;	/* SODIMM 93 */
	};

	/* Verdin I2C_1 */
	pinctrl_i2c4: i2c4grp {
		fsl,pins =
			<MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000146>,	/* SODIMM 14 */
			<MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000146>;	/* SODIMM 12 */
	};

	pinctrl_i2c4_gpio: i2c4gpiogrp {
		fsl,pins =
			<MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20		0x146>,	/* SODIMM 14 */
			<MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21		0x146>;	/* SODIMM 12 */
	};

	/* Verdin I2S_2_BCLK (TOUCH_RESET#) */
	pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x6>;	/* SODIMM 42 */
	};

	/* Verdin I2S_2_D_OUT shared with SAI5 */
	pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24		0x6>;	/* SODIMM 46 */
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x6>,	/* SODIMM 244 */
			/* PMIC_EN_PCIe_CLK, unused */
			<MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x6>;
	};

	pinctrl_pmic: pmicirqgrp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141>;	/* PMIC_INT# */
	};

	/* Verdin PWM_3_DSI shared with GPIO1_IO1 */
	pinctrl_pwm_1: pwm1grp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT		0x6>;	/* SODIMM 19 */
	};

	pinctrl_pwm_2: pwm2grp {
		fsl,pins =
			<MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT			0x6>;	/* SODIMM 15 */
	};

	pinctrl_pwm_3: pwm3grp {
		fsl,pins =
			<MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT			0x6>;	/* SODIMM 16 */
	};

	/* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
	pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x106>;	/* SODIMM 19 */
	};

	pinctrl_reg_eth: regethgrp {
		fsl,pins =
			<MX8MM_IOMUXC_SD2_WP_GPIO2_IO20			0x146>;	/* PMIC_EN_ETH */
	};

	pinctrl_reg_usb1_en: regusb1engrp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x106>;	/* SODIMM 155 */
	};

	pinctrl_reg_usb2_en: regusb2engrp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x106>;	/* SODIMM 185 */
	};

	pinctrl_sai2: sai2grp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK		0x6>,	/* SODIMM 38 */
			<MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0x6>,	/* SODIMM 30 */
			<MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0x6>,	/* SODIMM 32 */
			<MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0x6>,	/* SODIMM 36 */
			<MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0x6>;	/* SODIMM 34 */
	};

	pinctrl_sai5: sai5grp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0		0x6>,	/* SODIMM 48 */
			<MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC		0x6>,	/* SODIMM 44 */
			<MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK		0x6>,	/* SODIMM 42 */
			<MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0		0x6>;	/* SODIMM 46 */
	};

	/* control signal for optional ATTPM20P or SE050 */
	pinctrl_pmic_tpm_ena: pmictpmenagrp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x106>;	/* PMIC_TPM_ENA */
	};

	pinctrl_tsp: tspgrp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6		0x6>,	/* SODIMM 148 */
			<MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x6>,	/* SODIMM 152 */
			<MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x6>,	/* SODIMM 154 */
			<MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x146>,	/* SODIMM 174 */
			<MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17		0x6>;	/* SODIMM 150 */
	};

	pinctrl_uart1: uart1grp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX		0x146>,	/* SODIMM 147 */
			<MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX		0x146>;	/* SODIMM 149 */
	};

	pinctrl_uart2: uart2grp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B		0x146>,	/* SODIMM 133 */
			<MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B		0x146>,	/* SODIMM 135 */
			<MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX		0x146>,	/* SODIMM 131 */
			<MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX		0x146>;	/* SODIMM 129 */
	};

	pinctrl_uart3: uart3grp {
		fsl,pins =
			<MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x146>,	/* SODIMM 141 */
			<MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x146>,	/* SODIMM 139 */
			<MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x146>,	/* SODIMM 137 */
			<MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x146>;	/* SODIMM 143 */
	};

	pinctrl_uart4: uart4grp {
		fsl,pins =
			<MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x146>,	/* SODIMM 151 */
			<MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x146>;	/* SODIMM 153 */
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins =
			<MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190>,
			<MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0>,
			<MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0>,
			<MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0>,
			<MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0>,
			<MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0>,
			<MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d0>,
			<MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d0>,
			<MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d0>,
			<MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d0>,
			<MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d1>,
			<MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x190>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins =
			<MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194>,
			<MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4>,
			<MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4>,
			<MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4>,
			<MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4>,
			<MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4>,
			<MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d4>,
			<MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d4>,
			<MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d4>,
			<MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d4>,
			<MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d1>,
			<MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x194>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins =
			<MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196>,
			<MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6>,
			<MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6>,
			<MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6>,
			<MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6>,
			<MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6>,
			<MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d6>,
			<MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d6>,
			<MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d6>,
			<MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d6>,
			<MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0x1d1>,
			<MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x196>;
	};

	pinctrl_usdhc2_cd: usdhc2cdgrp {
		fsl,pins =
			<MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x6>;	/* SODIMM 84 */
	};

	pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
		fsl,pins =
			<MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x0>;	/* SODIMM 84 */
	};

	pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
		fsl,pins =
			<MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5		0x6>;	/* SODIMM 76 */
	};

	/*
	 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
	 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
	 */
	pinctrl_usdhc2: usdhc2grp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,
			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x90>,	/* SODIMM 78 */
			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x90>,	/* SODIMM 74 */
			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x90>,	/* SODIMM 80 */
			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x90>,	/* SODIMM 82 */
			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x90>,	/* SODIMM 70 */
			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x90>;	/* SODIMM 72 */
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,
			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x94>,
			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x94>,
			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x94>,
			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x94>,
			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x94>,
			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x94>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x10>,
			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x96>,
			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x96>,
			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x96>,
			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x96>,
			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x96>,
			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x96>;
	};

	/* Avoid backfeeding with removed card power */
	pinctrl_usdhc2_sleep: usdhc2slpgrp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0x0>,
			<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x0>,
			<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x0>,
			<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0>,
			<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0>,
			<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0>,
			<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0>;
	};

	/*
	 * On-module Wi-Fi/BT or type specific SDHC interface
	 * (e.g. on X52 extension slot of Verdin Development Board)
	 */
	pinctrl_usdhc3: usdhc3grp {
		fsl,pins =
			<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x150>,
			<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x150>,
			<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x150>,
			<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x150>,
			<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x150>,
			<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x150>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins =
			<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x154>,
			<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x154>,
			<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x154>,
			<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x154>,
			<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x154>,
			<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x154>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins =
			<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x156>,
			<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x156>,
			<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x156>,
			<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x156>,
			<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x156>,
			<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x156>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins =
			<MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166>;	/* PMIC_WDI */
	};

	pinctrl_wifi_ctrl: wifictrlgrp {
		fsl,pins =
			<MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16		0x46>,	/* WIFI_WKUP_BT */
			<MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9		0x146>,	/* WIFI_W_WKUP_HOST */
			<MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20		0x46>;	/* WIFI_WKUP_WLAN */
	};

	pinctrl_wifi_i2s: bti2sgrp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK		0x6>,	/* WIFI_TX_BCLK */
			<MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0		0x6>,	/* WIFI_TX_DATA0 */
			<MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC		0x6>,	/* WIFI_TX_SYNC */
			<MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0		0x6>;	/* WIFI_RX_DATA0 */
	};

	pinctrl_wifi_pwr_en: wifipwrengrp {
		fsl,pins =
			<MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x6>;	/* PMIC_EN_WIFI */
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

#include <dt-bindings/clock/imx8mm-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/imx8mm-power.h>
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/thermal/thermal.h>

#include "imx8mm-pinfunc.h"

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec1;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &ecspi3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		idle-states {
			entry-method = "psci";

			cpu_pd_wait: cpu-pd-wait {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010033>;
				local-timer-stop;
				entry-latency-us = <1000>;
				exit-latency-us = <700>;
				min-residency-us = <2700>;
			};
		};

		A53_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clk IMX8MM_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			nvmem-cells = <&cpu_speed_grade>;
			nvmem-cell-names = "speed_grade";
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clk IMX8MM_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clk IMX8MM_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clk IMX8MM_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			cpu-idle-states = <&cpu_pd_wait>;
			#cooling-cells = <2>;
		};

		A53_L2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
		};
	};

	a53_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <850000>;
			opp-supported-hw = <0xe>, <0x7>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};

		opp-1600000000 {
			opp-hz = /bits/ 64 <1600000000>;
			opp-microvolt = <950000>;
			opp-supported-hw = <0xc>, <0x7>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};

		opp-1800000000 {
			opp-hz = /bits/ 64 <1800000000>;
			opp-microvolt = <1000000>;
			opp-supported-hw = <0x8>, <0x3>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};
	};

	osc_32k: clock-osc-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "osc_32k";
	};

	osc_24m: clock-osc-24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc_24m";
	};

	clk_ext1: clock-ext1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext1";
	};

	clk_ext2: clock-ext2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext2";
	};

	clk_ext3: clock-ext3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext3";
	};

	clk_ext4: clock-ext4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext4";
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7
			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
		clock-frequency = <8000000>;
		arm,no-tick-in-suspend;
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tmu>;
			trips {
				cpu_alert0: trip0 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit0: trip1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	usbphynop1: usbphynop1 {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
		clock-names = "main_clk";
		power-domains = <&pgc_otg1>;
	};

	usbphynop2: usbphynop2 {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
		clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
		assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
		assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
		clock-names = "main_clk";
		power-domains = <&pgc_otg2>;
	};

	soc: soc@0 {
		compatible = "fsl,imx8mm-soc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x3e000000>;
		dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
		nvmem-cells = <&imx8mm_uid>;
		nvmem-cell-names = "soc_unique_id";

		aips1: bus@30000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x30000000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30000000 0x30000000 0x400000>;

			spba2: spba-bus@30000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x30000000 0x100000>;
				ranges;

				sai1: sai@30010000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
					reg = <0x30010000 0x10000>;
					interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
						 <&clk IMX8MM_CLK_SAI1_ROOT>,
						 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
					clock-names = "bus", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				sai2: sai@30020000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
					reg = <0x30020000 0x10000>;
					interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
						<&clk IMX8MM_CLK_SAI2_ROOT>,
						<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
					clock-names = "bus", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				sai3: sai@30030000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
					reg = <0x30030000 0x10000>;
					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
						 <&clk IMX8MM_CLK_SAI3_ROOT>,
						 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
					clock-names = "bus", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				sai5: sai@30050000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
					reg = <0x30050000 0x10000>;
					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
						 <&clk IMX8MM_CLK_SAI5_ROOT>,
						 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
					clock-names = "bus", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				sai6: sai@30060000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
					reg = <0x30060000 0x10000>;
					interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
						 <&clk IMX8MM_CLK_SAI6_ROOT>,
						 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
					clock-names = "bus", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				micfil: audio-controller@30080000 {
					compatible = "fsl,imx8mm-micfil";
					reg = <0x30080000 0x10000>;
					interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_PDM_IPG>,
						 <&clk IMX8MM_CLK_PDM_ROOT>,
						 <&clk IMX8MM_AUDIO_PLL1_OUT>,
						 <&clk IMX8MM_AUDIO_PLL2_OUT>,
						 <&clk IMX8MM_CLK_EXT3>;
					clock-names = "ipg_clk", "ipg_clk_app",
						      "pll8k", "pll11k", "clkext3";
					dmas = <&sdma2 24 25 0x80000000>;
					dma-names = "rx";
					status = "disabled";
				};

				spdif1: spdif@30090000 {
					compatible = "fsl,imx35-spdif";
					reg = <0x30090000 0x10000>;
					interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
						 <&clk IMX8MM_CLK_24M>, /* rxtx0 */
						 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
						 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
						 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
						 <&clk IMX8MM_CLK_DUMMY>; /* spba */
					clock-names = "core", "rxtx0",
						      "rxtx1", "rxtx2",
						      "rxtx3", "rxtx4",
						      "rxtx5", "rxtx6",
						      "rxtx7", "spba";
					dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};
			};

			gpio1: gpio@30200000 {
				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
				reg = <0x30200000 0x10000>;
				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 10 30>;
			};

			gpio2: gpio@30210000 {
				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
				reg = <0x30210000 0x10000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 40 21>;
			};

			gpio3: gpio@30220000 {
				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
				reg = <0x30220000 0x10000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 61 26>;
			};

			gpio4: gpio@30230000 {
				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
				reg = <0x30230000 0x10000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 87 32>;
			};

			gpio5: gpio@30240000 {
				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
				reg = <0x30240000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 119 30>;
			};

			tmu: tmu@30260000 {
				compatible = "fsl,imx8mm-tmu";
				reg = <0x30260000 0x10000>;
				clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
				#thermal-sensor-cells = <0>;
			};

			wdog1: watchdog@30280000 {
				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
				reg = <0x30280000 0x10000>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
				status = "disabled";
			};

			wdog2: watchdog@30290000 {
				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
				reg = <0x30290000 0x10000>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
				status = "disabled";
			};

			wdog3: watchdog@302a0000 {
				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
				reg = <0x302a0000 0x10000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
				status = "disabled";
			};

			sdma2: dma-controller@302c0000 {
				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
				reg = <0x302c0000 0x10000>;
				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
					 <&clk IMX8MM_CLK_SDMA2_ROOT>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			sdma3: dma-controller@302b0000 {
				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
				reg = <0x302b0000 0x10000>;
				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
				 <&clk IMX8MM_CLK_SDMA3_ROOT>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			iomuxc: pinctrl@30330000 {
				compatible = "fsl,imx8mm-iomuxc";
				reg = <0x30330000 0x10000>;
			};

			gpr: iomuxc-gpr@30340000 {
				compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
				reg = <0x30340000 0x10000>;
			};

			ocotp: efuse@30350000 {
				compatible = "fsl,imx8mm-ocotp", "syscon";
				reg = <0x30350000 0x10000>;
				clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
				/* For nvmem subnodes */
				#address-cells = <1>;
				#size-cells = <1>;

				imx8mm_uid: unique-id@410 {
					reg = <0x4 0x8>;
				};

				cpu_speed_grade: speed-grade@10 {
					reg = <0x10 4>;
				};

				fec_mac_address: mac-address@90 {
					reg = <0x90 6>;
				};
			};

			anatop: clock-controller@30360000 {
				compatible = "fsl,imx8mm-anatop";
				reg = <0x30360000 0x10000>;
				#clock-cells = <1>;
			};

			snvs: snvs@30370000 {
				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
				reg = <0x30370000 0x10000>;

				snvs_rtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap = <&snvs>;
					offset = <0x34>;
					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
					clock-names = "snvs-rtc";
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
					clock-names = "snvs-pwrkey";
					linux,keycode = <KEY_POWER>;
					wakeup-source;
					status = "disabled";
				};

				snvs_lpgpr: snvs-lpgpr {
					compatible = "fsl,imx8mm-snvs-lpgpr",
						     "fsl,imx7d-snvs-lpgpr";
				};
			};

			clk: clock-controller@30380000 {
				compatible = "fsl,imx8mm-ccm";
				reg = <0x30380000 0x10000>;
				#clock-cells = <1>;
				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
					 <&clk_ext3>, <&clk_ext4>;
				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
					      "clk_ext3", "clk_ext4";
				assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
						<&clk IMX8MM_CLK_A53_CORE>,
						<&clk IMX8MM_CLK_NOC>,
						<&clk IMX8MM_CLK_AUDIO_AHB>,
						<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
						<&clk IMX8MM_SYS_PLL3>,
						<&clk IMX8MM_VIDEO_PLL1>,
						<&clk IMX8MM_AUDIO_PLL1>;
				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
							 <&clk IMX8MM_ARM_PLL_OUT>,
							 <&clk IMX8MM_SYS_PLL3_OUT>,
							 <&clk IMX8MM_SYS_PLL1_800M>;
				assigned-clock-rates = <0>, <0>, <0>,
							<400000000>,
							<400000000>,
							<750000000>,
							<594000000>,
							<393216000>;
			};

			src: reset-controller@30390000 {
				compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
				reg = <0x30390000 0x10000>;
				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};

			gpc: gpc@303a0000 {
				compatible = "fsl,imx8mm-gpc";
				reg = <0x303a0000 0x10000>;
				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-parent = <&gic>;
				interrupt-controller;
				#interrupt-cells = <3>;

				pgc {
					#address-cells = <1>;
					#size-cells = <0>;

					pgc_hsiomix: power-domain@0 {
						#power-domain-cells = <0>;
						reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
						clocks = <&clk IMX8MM_CLK_USB_BUS>;
						assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
						assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
					};

					pgc_pcie: power-domain@1 {
						#power-domain-cells = <0>;
						reg = <IMX8MM_POWER_DOMAIN_PCIE>;
						power-domains = <&pgc_hsiomix>;
						clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
					};

					pgc_otg1: power-domain@2 {
						#power-domain-cells = <0>;
						reg = <IMX8MM_POWER_DOMAIN_OTG1>;
					};

					pgc_otg2: power-domain@3 {
						#power-domain-cells = <0>;
						reg = <IMX8MM_POWER_DOMAIN_OTG2>;
					};

					pgc_gpumix: power-domain@4 {
						#power-domain-cells = <0>;
						reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
						clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
							 <&clk IMX8MM_CLK_GPU_AHB>;
						assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
								  <&clk IMX8MM_CLK_GPU_AHB>;
						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
									 <&clk IMX8MM_SYS_PLL1_800M>;
						assigned-clock-rates = <800000000>, <400000000>;
					};

					pgc_gpu: power-domain@5 {
						#power-domain-cells = <0>;
						reg = <IMX8MM_POWER_DOMAIN_GPU>;
						clocks = <&clk IMX8MM_CLK_GPU_AHB>,
							 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
							 <&clk IMX8MM_CLK_GPU2D_ROOT>,
							 <&clk IMX8MM_CLK_GPU3D_ROOT>;
						resets = <&src IMX8MQ_RESET_GPU_RESET>;
						power-domains = <&pgc_gpumix>;
					};

					pgc_vpumix: power-domain@6 {
						#power-domain-cells = <0>;
						reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
						clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
						assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
						assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
					};

					pgc_vpu_g1: power-domain@7 {
						#power-domain-cells = <0>;
						reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
					};

					pgc_vpu_g2: power-domain@8 {
						#power-domain-cells = <0>;
						reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
					};

					pgc_vpu_h1: power-domain@9 {
						#power-domain-cells = <0>;
						reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
					};

					pgc_dispmix: power-domain@10 {
						#power-domain-cells = <0>;
						reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
						clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
							 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
						assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
								  <&clk IMX8MM_CLK_DISP_APB>;
						assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
									 <&clk IMX8MM_SYS_PLL1_800M>;
						assigned-clock-rates = <500000000>, <200000000>;
					};

					pgc_mipi: power-domain@11 {
						#power-domain-cells = <0>;
						reg = <IMX8MM_POWER_DOMAIN_MIPI>;
					};
				};
			};
		};

		aips2: bus@30400000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x30400000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30400000 0x30400000 0x400000>;

			pwm1: pwm@30660000 {
				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
				reg = <0x30660000 0x10000>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
					<&clk IMX8MM_CLK_PWM1_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm2: pwm@30670000 {
				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
				reg = <0x30670000 0x10000>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
					 <&clk IMX8MM_CLK_PWM2_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm3: pwm@30680000 {
				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
				reg = <0x30680000 0x10000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
					 <&clk IMX8MM_CLK_PWM3_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm4: pwm@30690000 {
				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
				reg = <0x30690000 0x10000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
					 <&clk IMX8MM_CLK_PWM4_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			system_counter: timer@306a0000 {
				compatible = "nxp,sysctr-timer";
				reg = <0x306a0000 0x20000>;
				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&osc_24m>;
				clock-names = "per";
			};
		};

		aips3: bus@30800000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x30800000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x30800000 0x30800000 0x400000>,
				 <0x8000000 0x8000000 0x10000000>;

			spba1: spba-bus@30800000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x30800000 0x100000>;
				ranges;

				ecspi1: spi@30820000 {
					compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0x30820000 0x10000>;
					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
						 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
					clock-names = "ipg", "per";
					dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi2: spi@30830000 {
					compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0x30830000 0x10000>;
					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
						 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
					clock-names = "ipg", "per";
					dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi3: spi@30840000 {
					compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0x30840000 0x10000>;
					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
						 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
					clock-names = "ipg", "per";
					dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart1: serial@30860000 {
					compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
					reg = <0x30860000 0x10000>;
					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
						 <&clk IMX8MM_CLK_UART1_ROOT>;
					clock-names = "ipg", "per";
					dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart3: serial@30880000 {
					compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
					reg = <0x30880000 0x10000>;
					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
						 <&clk IMX8MM_CLK_UART3_ROOT>;
					clock-names = "ipg", "per";
					dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart2: serial@30890000 {
					compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
					reg = <0x30890000 0x10000>;
					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
						 <&clk IMX8MM_CLK_UART2_ROOT>;
					clock-names = "ipg", "per";
					status = "disabled";
				};
			};

			crypto: crypto@30900000 {
				compatible = "fsl,sec-v4.0";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x30900000 0x40000>;
				ranges = <0 0x30900000 0x40000>;
				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_AHB>,
					 <&clk IMX8MM_CLK_IPG_ROOT>;
				clock-names = "aclk", "ipg";

				sec_jr0: jr@1000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x1000 0x1000>;
					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
					status = "disabled";
				};

				sec_jr1: jr@2000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x2000 0x1000>;
					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr2: jr@3000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x3000 0x1000>;
					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			i2c1: i2c@30a20000 {
				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a20000 0x10000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
				status = "disabled";
			};

			i2c2: i2c@30a30000 {
				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a30000 0x10000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
				status = "disabled";
			};

			i2c3: i2c@30a40000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
				reg = <0x30a40000 0x10000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
				status = "disabled";
			};

			i2c4: i2c@30a50000 {
				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a50000 0x10000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
				status = "disabled";
			};

			uart4: serial@30a60000 {
				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
				reg = <0x30a60000 0x10000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
					 <&clk IMX8MM_CLK_UART4_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			mu: mailbox@30aa0000 {
				compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
				reg = <0x30aa0000 0x10000>;
				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_MU_ROOT>;
				#mbox-cells = <2>;
			};

			usdhc1: mmc@30b40000 {
				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b40000 0x10000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MM_CLK_USDHC1_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@30b50000 {
				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b50000 0x10000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MM_CLK_USDHC2_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc3: mmc@30b60000 {
				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b60000 0x10000>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MM_CLK_USDHC3_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			flexspi: spi@30bb0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "nxp,imx8mm-fspi";
				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
				reg-names = "fspi_base", "fspi_mmap";
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
					 <&clk IMX8MM_CLK_QSPI_ROOT>;
				clock-names = "fspi_en", "fspi";
				status = "disabled";
			};

			sdma1: dma-controller@30bd0000 {
				compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
				reg = <0x30bd0000 0x10000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
					 <&clk IMX8MM_CLK_AHB>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			fec1: ethernet@30be0000 {
				compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
				reg = <0x30be0000 0x10000>;
				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
					 <&clk IMX8MM_CLK_ENET1_ROOT>,
					 <&clk IMX8MM_CLK_ENET_TIMER>,
					 <&clk IMX8MM_CLK_ENET_REF>,
					 <&clk IMX8MM_CLK_ENET_PHY_REF>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
						  <&clk IMX8MM_CLK_ENET_TIMER>,
						  <&clk IMX8MM_CLK_ENET_REF>,
						  <&clk IMX8MM_CLK_ENET_PHY_REF>;
				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
							 <&clk IMX8MM_SYS_PLL2_100M>,
							 <&clk IMX8MM_SYS_PLL2_125M>,
							 <&clk IMX8MM_SYS_PLL2_50M>;
				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				nvmem-cells = <&fec_mac_address>;
				nvmem-cell-names = "mac-address";
				fsl,stop-mode = <&gpr 0x10 3>;
				status = "disabled";
			};

		};

		aips4: bus@32c00000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x32c00000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x32c00000 0x32c00000 0x400000>;

			csi: csi@32e20000 {
				compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
				reg = <0x32e20000 0x1000>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
				clock-names = "mclk";
				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
				status = "disabled";

				port {
					csi_in: endpoint {
						remote-endpoint = <&imx8mm_mipi_csi_out>;
					};
				};
			};

			disp_blk_ctrl: blk-ctrl@32e28000 {
				compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
				reg = <0x32e28000 0x100>;
				power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
						<&pgc_dispmix>, <&pgc_mipi>,
						<&pgc_mipi>;
				power-domain-names = "bus", "csi-bridge",
						     "lcdif", "mipi-dsi",
						     "mipi-csi";
				clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
					 <&clk IMX8MM_CLK_CSI1_ROOT>,
					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
					 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
					 <&clk IMX8MM_CLK_DISP_ROOT>,
					 <&clk IMX8MM_CLK_DSI_CORE>,
					 <&clk IMX8MM_CLK_DSI_PHY_REF>,
					 <&clk IMX8MM_CLK_CSI1_CORE>,
					 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
				clock-names = "csi-bridge-axi","csi-bridge-apb",
					      "csi-bridge-core", "lcdif-axi",
					      "lcdif-apb", "lcdif-pix",
					      "dsi-pclk", "dsi-ref",
					      "csi-aclk", "csi-pclk";
				#power-domain-cells = <1>;
			};

			mipi_csi: mipi-csi@32e30000 {
				compatible = "fsl,imx8mm-mipi-csi2";
				reg = <0x32e30000 0x1000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
						  <&clk IMX8MM_CLK_CSI1_PHY_REF>;
				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
							  <&clk IMX8MM_SYS_PLL2_1000M>;
				clock-frequency = <333000000>;
				clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
					 <&clk IMX8MM_CLK_CSI1_ROOT>,
					 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
				clock-names = "pclk", "wrap", "phy", "axi";
				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
					};

					port@1 {
						reg = <1>;

						imx8mm_mipi_csi_out: endpoint {
							remote-endpoint = <&csi_in>;
						};
					};
				};
			};

			usbotg1: usb@32e40000 {
				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
				reg = <0x32e40000 0x200>;
				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
				clock-names = "usb1_ctrl_root_clk";
				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
				phys = <&usbphynop1>;
				fsl,usbmisc = <&usbmisc1 0>;
				power-domains = <&pgc_hsiomix>;
				status = "disabled";
			};

			usbmisc1: usbmisc@32e40200 {
				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
				#index-cells = <1>;
				reg = <0x32e40200 0x200>;
			};

			usbotg2: usb@32e50000 {
				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
				reg = <0x32e50000 0x200>;
				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
				clock-names = "usb1_ctrl_root_clk";
				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
				phys = <&usbphynop2>;
				fsl,usbmisc = <&usbmisc2 0>;
				power-domains = <&pgc_hsiomix>;
				status = "disabled";
			};

			usbmisc2: usbmisc@32e50200 {
				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
				#index-cells = <1>;
				reg = <0x32e50200 0x200>;
			};

			pcie_phy: pcie-phy@32f00000 {
				compatible = "fsl,imx8mm-pcie-phy";
				reg = <0x32f00000 0x10000>;
				clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
				clock-names = "ref";
				assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
				assigned-clock-rates = <100000000>;
				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
				resets = <&src IMX8MQ_RESET_PCIEPHY>;
				reset-names = "pciephy";
				#phy-cells = <0>;
				status = "disabled";
			};
		};

		dma_apbh: dma-controller@33000000 {
			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
			reg = <0x33000000 0x2000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
			#dma-cells = <1>;
			dma-channels = <4>;
			clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
		};

		gpmi: nand-controller@33002000 {
			compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
			reg-names = "gpmi-nand", "bch";
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "bch";
			clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
				 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
			clock-names = "gpmi_io", "gpmi_bch_apb";
			dmas = <&dma_apbh 0>;
			dma-names = "rx-tx";
			status = "disabled";
		};

		pcie0: pcie@33800000 {
			compatible = "fsl,imx8mm-pcie";
			reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
			reg-names = "dbi", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			bus-range = <0x00 0xff>;
			ranges =  <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
				   0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
			num-lanes = <1>;
			num-viewport = <4>;
			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
			fsl,max-link-speed = <2>;
			linux,pci-domain = <0>;
			power-domains = <&pgc_pcie>;
			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
			reset-names = "apps", "turnoff";
			phys = <&pcie_phy>;
			phy-names = "pcie-phy";
			status = "disabled";
		};

		gpu_3d: gpu@38000000 {
			compatible = "vivante,gc";
			reg = <0x38000000 0x8000>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
				 <&clk IMX8MM_CLK_GPU3D_ROOT>,
				 <&clk IMX8MM_CLK_GPU3D_ROOT>;
			clock-names = "reg", "bus", "core", "shader";
			assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
					  <&clk IMX8MM_GPU_PLL_OUT>;
			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
			assigned-clock-rates = <0>, <1000000000>;
			power-domains = <&pgc_gpu>;
		};

		gpu_2d: gpu@38008000 {
			compatible = "vivante,gc";
			reg = <0x38008000 0x8000>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MM_CLK_GPU_AHB>,
				 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
				 <&clk IMX8MM_CLK_GPU2D_ROOT>;
			clock-names = "reg", "bus", "core";
			assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
					  <&clk IMX8MM_GPU_PLL_OUT>;
			assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
			assigned-clock-rates = <0>, <1000000000>;
			power-domains = <&pgc_gpu>;
		};

		vpu_g1: video-codec@38300000 {
			compatible = "nxp,imx8mm-vpu-g1";
			reg = <0x38300000 0x10000>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
			power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
		};

		vpu_g2: video-codec@38310000 {
			compatible = "nxp,imx8mq-vpu-g2";
			reg = <0x38310000 0x10000>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
			power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
		};

		vpu_blk_ctrl: blk-ctrl@38330000 {
			compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
			reg = <0x38330000 0x100>;
			power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
					<&pgc_vpu_g2>, <&pgc_vpu_h1>;
			power-domain-names = "bus", "g1", "g2", "h1";
			clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
				 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
				 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
			clock-names = "g1", "g2", "h1";
			assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
					  <&clk IMX8MM_CLK_VPU_G2>;
			assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
						 <&clk IMX8MM_VPU_PLL_OUT>;
			assigned-clock-rates = <600000000>,
					       <600000000>;
			#power-domain-cells = <1>;
		};

		gic: interrupt-controller@38800000 {
			compatible = "arm,gic-v3";
			reg = <0x38800000 0x10000>, /* GIC Dist */
			      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		ddrc: memory-controller@3d400000 {
			compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
			reg = <0x3d400000 0x400000>;
			clock-names = "core", "pll", "alt", "apb";
			clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
				 <&clk IMX8MM_DRAM_PLL>,
				 <&clk IMX8MM_CLK_DRAM_ALT>,
				 <&clk IMX8MM_CLK_DRAM_APB>;
		};

		ddr-pmu@3d800000 {
			compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
			reg = <0x3d800000 0x400000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Compass Electronics Group, LLC
 */

/ {
	leds {
		compatible = "gpio-leds";

		led-0 {
			label = "gen_led0";
			gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-1 {
			label = "gen_led1";
			gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-2 {
			label = "gen_led2";
			gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-3 {
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_led3>;
			label = "heartbeat";
			gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	reg_audio: regulator-audio {
		compatible = "regulator-fixed";
		regulator-name = "3v3_aud";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		regulator-name = "vsd_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usb_otg_vbus: regulator-usb {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb_otg>;
		regulator-name = "usb_otg_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	sound {
		compatible = "fsl,imx-audio-wm8962";
		model = "wm8962-audio";
		audio-cpu = <&sai3>;
		audio-codec = <&wm8962>;
		audio-routing =
			"Headphone Jack", "HPOUTL",
			"Headphone Jack", "HPOUTR",
			"Ext Spk", "SPKOUTL",
			"Ext Spk", "SPKOUTR",
			"AMIC", "MICBIAS",
			"IN3R", "AMIC";
	};
};

&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_espi2>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	status = "okay";

	eeprom@0 {
		compatible = "microchip,at25160bn", "atmel,at25";
		reg = <0>;
		spi-max-frequency = <5000000>;
		spi-cpha;
		spi-cpol;
		pagesize = <32>;
		size = <2048>;
		address-width = <16>;
	};
};

&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	pca6416_0: gpio@20 {
		compatible = "nxp,pcal6416";
		reg = <0x20>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pcal6414>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio4>;
		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
	};

	pca6416_1: gpio@21 {
		compatible = "nxp,pcal6416";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gpio4>;
		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
	};

	wm8962: audio-codec@1a {
		compatible = "wlf,wm8962";
		reg = <0x1a>;
		clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
		DCVDD-supply = <&reg_audio>;
		DBVDD-supply = <&reg_audio>;
		AVDD-supply = <&reg_audio>;
		CPVDD-supply = <&reg_audio>;
		MICVDD-supply = <&reg_audio>;
		PLLVDD-supply = <&reg_audio>;
		SPKVDD1-supply = <&reg_audio>;
		SPKVDD2-supply = <&reg_audio>;
		gpio-cfg = <
			0x0000 /* 0:Default */
			0x0000 /* 1:Default */
			0x0000 /* 2:FN_DMICCLK */
			0x0000 /* 3:Default */
			0x0000 /* 4:FN_DMICCDAT */
			0x0000 /* 5:Default */
		>;
	};
};

&easrc {
	fsl,asrc-rate = <48000>;
	status = "okay";
};

&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	fsl,sai-mclk-direction-output;
	status = "okay";
};

&snvs_pwrkey {
	status = "okay";
};

&uart2 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clk IMX8MN_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
	uart-has-rtscts;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg_vbus>;
	disable-over-current;
	dr_mode = "otg";
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
	bus-width = <4>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&iomuxc {
	pinctrl_espi2: espi2grp {
		fsl,pins = <
			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
			MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x41
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
			MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
		>;
	};

	pinctrl_led3: led3grp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x41
		>;
	};

	pinctrl_pcal6414: pcal6414-gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x19
		>;
	};

	pinctrl_reg_usb_otg: reg-otggrp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29     0x19
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
			MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
			MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
			MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
			MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX	0x40
			MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX	0x40
			MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x40
			MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x40
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B	0x41
			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK	0x190
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d0
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Compass Electronics Group, LLC
 */

/dts-v1/;

#include "imx8mn.dtsi"
#include "imx8mn-beacon-som.dtsi"
#include "imx8mn-beacon-baseboard.dtsi"

/ {
	model = "Beacon EmbeddedWorks i.MX8M Nano Development Kit";
	compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn";

	chosen {
		stdout-path = &uart2;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Compass Electronics Group, LLC
 */

/ {
	aliases {
		rtc0 = &rtc;
		rtc1 = &snvs_rtc;
		spi0 = &flexspi;
	};

	usdhc1_pwrseq: usdhc1_pwrseq {
		compatible = "mmc-pwrseq-simple";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc1_gpio>;
		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
		clocks = <&osc_32k>;
		clock-names = "ext_clock";
		post-power-on-delay-ms = <80>;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&A53_1 {
	cpu-supply = <&buck2_reg>;
};

&A53_2 {
	cpu-supply = <&buck2_reg>;
};

&A53_3 {
	cpu-supply = <&buck2_reg>;
};

/* DDR controller is running LPDDR at 800MHz which requires 0.95V */
&a53_opp_table {
	opp-1200000000 {
		opp-microvolt = <950000>;
	};
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
		};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	phy-supply = <&buck6_reg>;
	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};
	};
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi>;
	status = "okay";

	flash@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <80000000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
		rohm,reset-snvs-powered;
		#clock-cells = <0>;
		clocks = <&osc_32k 0>;
		clock-output-names = "clk-32k-out";

		regulators {
			buck1_reg: BUCK1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			buck2_reg: BUCK2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <900000>;
			};

			buck3_reg: BUCK3 {
				// BUCK5 in datasheet
				regulator-name = "buck3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck4_reg: BUCK4 {
				// BUCK6 in datasheet
				regulator-name = "buck4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5_reg: BUCK5 {
				// BUCK7 in datasheet
				regulator-name = "buck5";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6_reg: BUCK6 {
				// BUCK8 in datasheet
				regulator-name = "buck6";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: LDO1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2_reg: LDO2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_reg: LDO3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4_reg: LDO4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo6_reg: LDO6 {
				regulator-name = "ldo6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	eeprom@50 {
		compatible = "microchip,24c64", "atmel,24c64";
		pagesize = <32>;
		read-only;	/* Manufacturing EEPROM programmed at factory */
		reg = <0x50>;
	};

	rtc: rtc@51 {
		compatible = "nxp,pcf85263";
		reg = <0x51>;
	};
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MN_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
		compatible = "brcm,bcm43438-bt";
		shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
		host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
		device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
		clocks = <&osc_32k>;
		max-speed = <4000000>;
		clock-names = "extclk";
	};
};

&usdhc1 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	vmmc-supply = <&buck4_reg>;
	vqmmc-supply = <&buck5_reg>;
	bus-width = <4>;
	non-removable;
	cap-power-off-card;
	keep-power-in-suspend;
	mmc-pwrseq = <&usdhc1_pwrseq>;
	status = "okay";

	brcmf: bcrmf@1 {
		reg = <1>;
		compatible = "brcm,bcm4329-fmac";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_wlan>;
		interrupt-parent = <&gpio2>;
		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "host-wake";
	};
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_flexspi: flexspigrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
			MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
			MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
			MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
			MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
			MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
		>;
	};

	pinctrl_pmic: pmicirqgrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
			MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
			MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
			MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19
			MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7	0x19
			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x19
			MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x141
		>;
	};

	pinctrl_usdhc1_gpio: usdhc1gpiogrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
		>;
	};

	pinctrl_wlan: wlangrp {
		fsl,pins = <
			MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9		0x111
		>;
	};
};