code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UniPhier outer cache controller

description: |
  UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
  controller system. All of them have a level 2 cache controller, and some
  have a level 3 cache controller as well.

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

properties:
  compatible:
    const: socionext,uniphier-system-cache

  reg:
    description: |
      should contain 3 regions: control register, revision register,
      operation register, in this order.
    maxItems: 3

  interrupts:
    description: |
      Interrupts can be used to notify the completion of cache operations.
      The number of interrupts should match to the number of CPU cores.
      The specified interrupts correspond to CPU0, CPU1, ... in this order.
    minItems: 1
    maxItems: 4

  cache-unified: true

  cache-size: true

  cache-sets: true

  cache-line-size: true

  cache-level:
    minimum: 2
    maximum: 3

  next-level-cache: true

allOf:
  - $ref: /schemas/cache-controller.yaml#

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - cache-unified
  - cache-size
  - cache-sets
  - cache-line-size
  - cache-level

examples:
  - |
    // System with L2.
    cache-controller@500c0000 {
        compatible = "socionext,uniphier-system-cache";
        reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
        interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
        cache-unified;
        cache-size = <0x140000>;
        cache-sets = <512>;
        cache-line-size = <128>;
        cache-level = <2>;
    };
  - |
    // System with L2 and L3.
    //   L2 should specify the next level cache by 'next-level-cache'.
    l2: cache-controller@500c0000 {
        compatible = "socionext,uniphier-system-cache";
        reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
        interrupts = <0 190 4>, <0 191 4>;
        cache-unified;
        cache-size = <0x200000>;
        cache-sets = <512>;
        cache-line-size = <128>;
        cache-level = <2>;
        next-level-cache = <&l3>;
    };

    l3: cache-controller@500c8000 {
        compatible = "socionext,uniphier-system-cache";
        reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
        interrupts = <0 174 4>, <0 175 4>;
        cache-unified;
        cache-size = <0x200000>;
        cache-sets = <512>;
        cache-line-size = <256>;
        cache-level = <3>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/socionext/uniphier.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier platform device tree bindings

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

properties:
  $nodename:
    const: /
  compatible:
    oneOf:
      - description: LD4 SoC boards
        items:
          - enum:
              - socionext,uniphier-ld4-ref
          - const: socionext,uniphier-ld4
      - description: Pro4 SoC boards
        items:
          - enum:
              - socionext,uniphier-pro4-ace
              - socionext,uniphier-pro4-ref
              - socionext,uniphier-pro4-sanji
          - const: socionext,uniphier-pro4
      - description: Pro5 SoC boards
        items:
          - enum:
              - socionext,uniphier-pro5-epcore
              - socionext,uniphier-pro5-proex
          - const: socionext,uniphier-pro5
      - description: sLD8 SoC boards
        items:
          - enum:
              - socionext,uniphier-sld8-ref
          - const: socionext,uniphier-sld8
      - description: PXs2 SoC boards
        items:
          - enum:
              - socionext,uniphier-pxs2-gentil
              - socionext,uniphier-pxs2-vodka
          - const: socionext,uniphier-pxs2
      - description: LD6b SoC boards
        items:
          - enum:
              - socionext,uniphier-ld6b-ref
          - const: socionext,uniphier-ld6b
      - description: LD11 SoC boards
        items:
          - enum:
              - socionext,uniphier-ld11-global
              - socionext,uniphier-ld11-ref
          - const: socionext,uniphier-ld11
      - description: LD20 SoC boards
        items:
          - enum:
              - socionext,uniphier-ld20-akebi96
              - socionext,uniphier-ld20-global
              - socionext,uniphier-ld20-ref
          - const: socionext,uniphier-ld20
      - description: PXs3 SoC boards
        items:
          - enum:
              - socionext,uniphier-pxs3-ref
          - const: socionext,uniphier-pxs3

additionalProperties: true

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sp810.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Versatile Express SP810 System Controller bindings

maintainers:
  - Andre Przywara <andre.przywara@arm.com>

description:
  The Arm SP810 system controller provides clocks, timers and a watchdog.

# We need a select here so we don't match all nodes with 'arm,primecell'
select:
  properties:
    compatible:
      contains:
        const: arm,sp810
  required:
    - compatible

properties:
  compatible:
    items:
      - const: arm,sp810
      - const: arm,primecell

  reg:
    maxItems: 1

  clock-names:
    items:
      - const: refclk
      - const: timclk
      - const: apb_pclk

  clocks:
    items:
      - description: reference clock
      - description: timer clock
      - description: APB register access clock

  "#clock-cells":
    const: 1

  clock-output-names:
    maxItems: 4

  assigned-clocks:
    maxItems: 4

  assigned-clock-parents:
    maxItems: 4

additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#clock-cells"

examples:
  - |
    sysctl@20000 {
        compatible = "arm,sp810", "arm,primecell";
        reg = <0x020000 0x1000>;
        clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
        clock-names = "refclk", "timclk", "apb_pclk";
        #clock-cells = <1>;
        clock-output-names = "timerclken0", "timerclken1",
                             "timerclken2", "timerclken3";
        assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>,
                          <&v2m_sysctl 3>, <&v2m_sysctl 3>;
        assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>,
                                 <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
    };


code:
SPEAr Misc configuration
===========================
SPEAr SOCs have some miscellaneous registers which are used to configure
few properties of different peripheral controllers.

misc node required properties:

- compatible Should be	"st,spear1340-misc", "syscon".
- reg: Address range of misc space up to 8K


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/spear.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ST SPEAr Platforms

maintainers:
  - Viresh Kumar <vireshk@kernel.org>
  - Stefan Roese <sr@denx.de>

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - st,spear600
          - st,spear300
          - st,spear310
          - st,spear320
          - st,spear1310
          - st,spear1340

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2019 Unisoc Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sprd/sprd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Unisoc platforms device tree bindings

maintainers:
  - Orson Zhai <orsonzhai@gmail.com>
  - Baolin Wang <baolin.wang7@gmail.com>
  - Chunyan Zhang <zhang.lyra@gmail.com>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - items:
          - enum:
              - sprd,sc9836-openphone
          - const: sprd,sc9836
      - items:
          - enum:
              - sprd,sp9860g-1h10
          - const: sprd,sc9860
      - items:
          - enum:
              - sprd,sp9863a-1h10
          - const: sprd,sc9863a

      - items:
          - enum:
              - sprd,ums512-1h10
          - const: sprd,ums512

additionalProperties: true

...


code:
ST-Ericsson Nomadik Device Tree Bindings

For various board the "board" node may contain specific properties
that pertain to this particular board, such as board-specific GPIOs.

Required root node property: src
- Nomadik System and reset controller used for basic chip control, clock
  and reset line control.
- compatible: must be "stericsson,nomadik,src"

Boards with the Nomadik SoC include:

Nomadik NHK-15 board manufactured by ST Microelectronics:

Required root node property:

compatible="st,nomadik-nhk-15";

S8815 "MiniKit" manufactured by Calao Systems:

Required root node property:

compatible="calaosystems,usb-s8815";

Required node: usb-s8815

Example:

usb-s8815 {
		ethernet-gpio {
			gpios = <&gpio3 19 0x1>;
			interrupts = <19 0x1>;
			interrupt-parent = <&gpio3>;
		};
		mmcsd-gpio {
			gpios = <&gpio3 16 0x1>;
		};
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ST STi Platforms

maintainers:
  - Patrice Chotard <patrice.chotard@foss.st.com>

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - st,stih415
          - st,stih416
          - st,stih407
          - st,stih410
          - st,stih418

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: STMicroelectronics STM32 ML-AHB interconnect bindings

maintainers:
  - Fabien Dessenne <fabien.dessenne@foss.st.com>
  - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>

description: |
  These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
  a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
  parts can be accessed through different addresses (see "RAM aliases" in [1])
  using different buses (see [2]): balancing the Cortex-M firmware accesses
  among those ports allows to tune the system performance.
  [1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf
  [2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping

allOf:
  - $ref: /schemas/simple-bus.yaml#

properties:
  compatible:
    contains:
      enum:
        - st,mlahb

  dma-ranges:
    description: |
      Describe memory addresses translation between the local CPU and the
      remote Cortex-M processor. Each memory region, is declared with
      3 parameters:
      - param 1: device base address (Cortex-M processor address)
      - param 2: physical base address (local CPU address)
      - param 3: size of the memory region.
    maxItems: 3

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

required:
  - compatible
  - '#address-cells'
  - '#size-cells'
  - dma-ranges

unevaluatedProperties: false

examples:
  - |
    mlahb: ahb@38000000 {
      compatible = "st,mlahb", "simple-bus";
      #address-cells = <1>;
      #size-cells = <1>;
      reg = <0x10000000 0x40000>;
      ranges;
      dma-ranges = <0x00000000 0x38000000 0x10000>,
                   <0x10000000 0x10000000 0x60000>,
                   <0x30000000 0x30000000 0x60000>;

      m4_rproc: m4@10000000 {
       reg = <0x10000000 0x40000>;
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: STMicroelectronics STM32 Platforms System Controller bindings

maintainers:
  - Alexandre Torgue <alexandre.torgue@foss.st.com>
  - Christophe Roullier <christophe.roullier@foss.st.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - st,stm32mp157-syscfg
              - st,stm32mp151-pwr-mcu
              - st,stm32-syscfg
              - st,stm32-power-config
              - st,stm32-tamp
          - const: syscon
      - items:
          - const: st,stm32-tamp
          - const: syscon
          - const: simple-mfd

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg

if:
  properties:
    compatible:
      contains:
        enum:
          - st,stm32mp157-syscfg
then:
  required:
    - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/stm32mp1-clks.h>
    syscfg: syscon@50020000 {
        compatible = "st,stm32mp157-syscfg", "syscon";
        reg = <0x50020000 0x400>;
        clocks = <&rcc SYSCFG>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/stm32/stm32.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 Platforms Device Tree Bindings

maintainers:
  - Alexandre Torgue <alexandre.torgue@foss.st.com>

properties:
  $nodename:
    const: "/"
  compatible:
    oneOf:
      - description: emtrion STM32MP1 Argon based Boards
        items:
          - const: emtrion,stm32mp157c-emsbc-argon
          - const: emtrion,stm32mp157c-emstamp-argon
          - const: st,stm32mp157
      - items:
          - enum:
              - st,stm32f429i-disco
              - st,stm32429i-eval
          - const: st,stm32f429
      - items:
          - enum:
              - st,stm32f469i-disco
          - const: st,stm32f469
      - items:
          - enum:
              - st,stm32f746-disco
              - st,stm32746g-eval
          - const: st,stm32f746
      - items:
          - enum:
              - st,stm32f769-disco
          - const: st,stm32f769
      - items:
          - enum:
              - st,stm32h743i-disco
              - st,stm32h743i-eval
          - const: st,stm32h743
      - items:
          - enum:
              - st,stm32h750i-art-pi
          - const: st,stm32h750
      - items:
          - enum:
              - st,stm32mp135f-dk
          - const: st,stm32mp135

      - description: ST STM32MP151 based Boards
        items:
          - enum:
              - prt,prtt1a   # Protonic PRTT1A
              - prt,prtt1c   # Protonic PRTT1C
              - prt,prtt1s   # Protonic PRTT1S
          - const: st,stm32mp151

      - description: DH STM32MP151 DHCOR SoM based Boards
        items:
          - const: dh,stm32mp151a-dhcor-testbench
          - const: dh,stm32mp151a-dhcor-som
          - const: st,stm32mp151

      - description: DH STM32MP153 DHCOM SoM based Boards
        items:
          - const: dh,stm32mp153c-dhcom-drc02
          - const: dh,stm32mp153c-dhcom-som
          - const: st,stm32mp153

      - description: DH STM32MP153 DHCOR SoM based Boards
        items:
          - const: dh,stm32mp153c-dhcor-drc-compact
          - const: dh,stm32mp153c-dhcor-som
          - const: st,stm32mp153

      - items:
          - enum:
              - shiratech,stm32mp157a-iot-box # IoT Box
              - shiratech,stm32mp157a-stinger96 # Stinger96
              - st,stm32mp157c-ed1
              - st,stm32mp157a-dk1
              - st,stm32mp157c-dk2
          - const: st,stm32mp157

      - items:
          - const: st,stm32mp157a-dk1-scmi
          - const: st,stm32mp157a-dk1
          - const: st,stm32mp157
      - items:
          - const: st,stm32mp157c-dk2-scmi
          - const: st,stm32mp157c-dk2
          - const: st,stm32mp157
      - items:
          - const: st,stm32mp157c-ed1-scmi
          - const: st,stm32mp157c-ed1
          - const: st,stm32mp157
      - items:
          - const: st,stm32mp157c-ev1
          - const: st,stm32mp157c-ed1
          - const: st,stm32mp157
      - items:
          - const: st,stm32mp157c-ev1-scmi
          - const: st,stm32mp157c-ev1
          - const: st,stm32mp157c-ed1
          - const: st,stm32mp157

      - description: DH STM32MP1 SoM based Boards
        items:
          - enum:
              - arrow,stm32mp157a-avenger96 # Avenger96
          - const: dh,stm32mp157a-dhcor-som
          - const: st,stm32mp157

      - description: DH STM32MP1 SoM based Boards
        items:
          - enum:
              - dh,stm32mp157c-dhcom-pdk2
              - dh,stm32mp157c-dhcom-picoitx
          - const: dh,stm32mp157c-dhcom-som
          - const: st,stm32mp157

      - description: Engicam i.Core STM32MP1 SoM based Boards
        items:
          - enum:
              - engicam,icore-stm32mp1-ctouch2       # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0
              - engicam,icore-stm32mp1-ctouch2-of10  # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
              - engicam,icore-stm32mp1-edimm2.2      # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
          - const: engicam,icore-stm32mp1            # STM32MP1 Engicam i.Core STM32MP1 SoM
          - const: st,stm32mp157

      - description: Engicam MicroGEA STM32MP1 SoM based Boards
        items:
          - enum:
              - engicam,microgea-stm32mp1-microdev2.0
              - engicam,microgea-stm32mp1-microdev2.0-of7
          - const: engicam,microgea-stm32mp1
          - const: st,stm32mp157

      - description: Octavo OSD32MP15x System-in-Package based boards
        items:
          - enum:
              - lxa,stm32mp157c-mc1 # Linux Automation MC-1
          - const: oct,stm32mp15xx-osd32
          - enum:
              - st,stm32mp157

      - description: Odyssey STM32MP1 SoM based Boards
        items:
          - enum:
              - seeed,stm32mp157c-odyssey
          - const: seeed,stm32mp157c-odyssey-som
          - const: st,stm32mp157

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sunplus SP7021 Boards

maintainers:
  - qinjian <qinjian@cqplus1.com>

description: |
  ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC.
  Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - sunplus,sp7021-achip
          - sunplus,sp7021-demo-v3
      - const: sunplus,sp7021

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0+ OR X11)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunxi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner platforms

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:

      - description: Allwinner A100 Perf1 Board
        items:
          - const: allwinner,a100-perf1
          - const: allwinner,sun50i-a100

      - description: Allwinner A23 Evaluation Board
        items:
          - const: allwinner,sun8i-a23-evb
          - const: allwinner,sun8i-a23

      - description: Allwinner A31 APP4 Evaluation Board
        items:
          - const: allwinner,app4-evb1
          - const: allwinner,sun6i-a31

      - description: Allwinner A83t Homlet Evaluation Board v2
        items:
          - const: allwinner,h8homlet-v2
          - const: allwinner,sun8i-a83t

      - description: Allwinner GA10H Quad Core Tablet v1.1
        items:
          - const: allwinner,ga10h-v1.1
          - const: allwinner,sun8i-a33

      - description: Allwinner GT90H Tablet v4
        items:
          - const: allwinner,gt90h-v4
          - const: allwinner,sun8i-a23

      - description: Allwinner R16 EVB (Parrot)
        items:
          - const: allwinner,parrot
          - const: allwinner,sun8i-a33

      - description: Amarula A64 Relic
        items:
          - const: amarula,a64-relic
          - const: allwinner,sun50i-a64

      - description: Auxtek T003 A10s HDMI TV Stick
        items:
          - const: allwinner,auxtek-t003
          - const: allwinner,sun5i-a10s

      - description: Auxtek T004 A10s HDMI TV Stick
        items:
          - const: allwinner,auxtek-t004
          - const: allwinner,sun5i-a10s

      - description: BA10 TV Box
        items:
          - const: allwinner,ba10-tvbox
          - const: allwinner,sun4i-a10

      - description: BananaPi
        items:
          - const: lemaker,bananapi
          - const: allwinner,sun7i-a20

      - description: BananaPi M1 Plus
        items:
          - const: sinovoip,bpi-m1-plus
          - const: allwinner,sun7i-a20

      - description: BananaPi M2
        items:
          - const: sinovoip,bpi-m2
          - const: allwinner,sun6i-a31s

      - description: BananaPi M2 Berry
        items:
          - const: sinovoip,bpi-m2-berry
          - const: allwinner,sun8i-r40

      - description: BananaPi M2 Plus
        items:
          - const: sinovoip,bpi-m2-plus
          - const: allwinner,sun8i-h3

      - description: BananaPi M2 Plus
        items:
          - const: sinovoip,bpi-m2-plus
          - const: allwinner,sun50i-h5

      - description: BananaPi M2 Plus v1.2
        items:
          - const: bananapi,bpi-m2-plus-v1.2
          - const: allwinner,sun8i-h3

      - description: BananaPi M2 Plus v1.2
        items:
          - const: bananapi,bpi-m2-plus-v1.2
          - const: allwinner,sun50i-h5

      - description: BananaPi M2 Magic
        items:
          - const: sinovoip,bananapi-m2m
          - const: allwinner,sun8i-a33

      - description: BananaPi M2 Ultra
        items:
          - const: sinovoip,bpi-m2-ultra
          - const: allwinner,sun8i-r40

      - description: BananaPi M2 Zero
        items:
          - const: sinovoip,bpi-m2-zero
          - const: allwinner,sun8i-h2-plus

      - description: BananaPi M3
        items:
          - const: sinovoip,bpi-m3
          - const: allwinner,sun8i-a83t

      - description: BananaPi M64
        items:
          - const: sinovoip,bananapi-m64
          - const: allwinner,sun50i-a64

      - description: BananaPro
        items:
          - const: lemaker,bananapro
          - const: allwinner,sun7i-a20

      - description: Beelink GS1
        items:
          - const: azw,beelink-gs1
          - const: allwinner,sun50i-h6

      - description: Beelink X2
        items:
          - const: roofull,beelink-x2
          - const: allwinner,sun8i-h3

      - description: Chuwi V7 CW0825
        items:
          - const: chuwi,v7-cw0825
          - const: allwinner,sun4i-a10

      - description: Colorfly E708 Q1 Tablet
        items:
          - const: colorfly,e708-q1
          - const: allwinner,sun6i-a31s

      - description: CSQ CS908 Set Top Box
        items:
          - const: csq,cs908
          - const: allwinner,sun6i-a31s

      - description: Cubietech Cubieboard
        items:
          - const: cubietech,a10-cubieboard
          - const: allwinner,sun4i-a10

      - description: Cubietech Cubieboard2
        items:
          - const: cubietech,cubieboard2
          - const: allwinner,sun7i-a20

      - description: Cubietech Cubieboard4
        items:
          - const: cubietech,a80-cubieboard4
          - const: allwinner,sun9i-a80

      - description: Cubietech Cubietruck
        items:
          - const: cubietech,cubietruck
          - const: allwinner,sun7i-a20

      - description: Cubietech Cubietruck Plus
        items:
          - const: cubietech,cubietruck-plus
          - const: allwinner,sun8i-a83t

      - description: Difrnce DIT4350
        items:
          - const: difrnce,dit4350
          - const: allwinner,sun5i-a13

      - description: Dserve DSRV9703C
        items:
          - const: dserve,dsrv9703c
          - const: allwinner,sun4i-a10

      - description: Elimo Engineering Impetus SoM
        items:
          - const: elimo,impetus
          - const: sochip,s3
          - const: allwinner,sun8i-v3

      - description: Elimo Engineering Initium
        items:
          - const: elimo,initium
          - const: elimo,impetus
          - const: sochip,s3
          - const: allwinner,sun8i-v3

      - description: Empire Electronix D709 Tablet
        items:
          - const: empire-electronix,d709
          - const: allwinner,sun5i-a13

      - description: Empire Electronix M712 Tablet
        items:
          - const: empire-electronix,m712
          - const: allwinner,sun5i-a13

      - description: Forlinx OKA40i-C Development board
        items:
          - const: forlinx,oka40i-c
          - const: forlinx,feta40i-c
          - const: allwinner,sun8i-r40

      - description: FriendlyARM NanoPi A64
        items:
          - const: friendlyarm,nanopi-a64
          - const: allwinner,sun50i-a64

      - description: FriendlyARM NanoPi Duo2
        items:
          - const: friendlyarm,nanopi-duo2
          - const: allwinner,sun8i-h3

      - description: FriendlyARM NanoPi M1
        items:
          - const: friendlyarm,nanopi-m1
          - const: allwinner,sun8i-h3

      - description: FriendlyARM NanoPi M1 Plus
        items:
          - const: friendlyarm,nanopi-m1-plus
          - const: allwinner,sun8i-h3

      - description: FriendlyARM NanoPi Neo
        items:
          - const: friendlyarm,nanopi-neo
          - const: allwinner,sun8i-h3

      - description: FriendlyARM NanoPi Neo 2
        items:
          - const: friendlyarm,nanopi-neo2
          - const: allwinner,sun50i-h5

      - description: FriendlyARM NanoPi Neo Air
        items:
          - const: friendlyarm,nanopi-neo-air
          - const: allwinner,sun8i-h3

      - description: FriendlyARM NanoPi Neo Plus2
        items:
          - const: friendlyarm,nanopi-neo-plus2
          - const: allwinner,sun50i-h5

      - description: FriendlyARM NanoPi R1
        items:
          - const: friendlyarm,nanopi-r1
          - const: allwinner,sun8i-h3

      - description: FriendlyARM NanoPi R1S H5
        items:
          - const: friendlyarm,nanopi-r1s-h5
          - const: allwinner,sun50i-h5

      - description: FriendlyARM ZeroPi
        items:
          - const: friendlyarm,zeropi
          - const: allwinner,sun8i-h3

      - description: Gemei G9 Tablet
        items:
          - const: gemei,g9
          - const: allwinner,sun4i-a10

      - description: Hyundai A7HD
        items:
          - const: hyundai,a7hd
          - const: allwinner,sun4i-a10

      - description: HSG H702
        items:
          - const: hsg,h702
          - const: allwinner,sun5i-a13

      - description: I12 TV Box
        items:
          - const: allwinner,i12-tvbox
          - const: allwinner,sun7i-a20

      - description: ICNova A20 SWAC
        items:
          - const: incircuit,icnova-a20-swac
          - const: incircuit,icnova-a20
          - const: allwinner,sun7i-a20

      - description: INet-1
        items:
          - const: inet-tek,inet1
          - const: allwinner,sun4i-a10

      - description: iNet-86DZ Rev 01
        items:
          - const: primux,inet86dz
          - const: allwinner,sun8i-a23

      - description: iNet-9F Rev 03
        items:
          - const: inet-tek,inet9f-rev03
          - const: allwinner,sun4i-a10

      - description: iNet-97F Rev 02
        items:
          - const: primux,inet97fv2
          - const: allwinner,sun4i-a10

      - description: iNet-98V Rev 02
        items:
          - const: primux,inet98v-rev2
          - const: allwinner,sun5i-a13

      - description: iNet D978 Rev 02 Tablet
        items:
          - const: primux,inet-d978-rev2
          - const: allwinner,sun8i-a33

      - description: iNet Q972 Tablet
        items:
          - const: inet-tek,inet-q972
          - const: allwinner,sun6i-a31s

      - description: Itead Ibox A20
        items:
          - const: itead,itead-ibox-a20
          - const: allwinner,sun7i-a20

      - description: Itead Iteaduino Plus A10
        items:
          - const: itead,iteaduino-plus-a10
          - const: allwinner,sun4i-a10

      - description: Jesurun Q5
        items:
          - const: jesurun,q5
          - const: allwinner,sun4i-a10

      - description: Lamobo R1
        items:
          - const: lamobo,lamobo-r1
          - const: allwinner,sun7i-a20

      - description: Libre Computer Board ALL-H3-CC H2+
        items:
          - const: libretech,all-h3-cc-h2-plus
          - const: allwinner,sun8i-h2-plus

      - description: Libre Computer Board ALL-H3-CC H3
        items:
          - const: libretech,all-h3-cc-h3
          - const: allwinner,sun8i-h3

      - description: Libre Computer Board ALL-H3-CC H5
        items:
          - const: libretech,all-h3-cc-h5
          - const: allwinner,sun50i-h5

      - description: Libre Computer Board ALL-H3-IT H5
        items:
          - const: libretech,all-h3-it-h5
          - const: allwinner,sun50i-h5

      - description: Libre Computer Board ALL-H5-CC H5
        items:
          - const: libretech,all-h5-cc-h5
          - const: allwinner,sun50i-h5

      - description: Lichee Pi Nano
        items:
          - const: licheepi,licheepi-nano
          - const: allwinner,suniv-f1c100s

      - description: Lichee Pi One
        items:
          - const: licheepi,licheepi-one
          - const: allwinner,sun5i-a13

      - description: Lichee Pi Zero
        items:
          - const: licheepi,licheepi-zero
          - const: allwinner,sun8i-v3s

      - description: Lichee Pi Zero (with Dock)
        items:
          - const: licheepi,licheepi-zero-dock
          - const: licheepi,licheepi-zero
          - const: allwinner,sun8i-v3s

      - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash)
        items:
          - const: sipeed,lichee-zero-plus
          - const: sochip,s3
          - const: allwinner,sun8i-v3

      - description: Linksprite PCDuino
        items:
          - const: linksprite,a10-pcduino
          - const: allwinner,sun4i-a10

      - description: Linksprite PCDuino2
        items:
          - const: linksprite,a10-pcduino2
          - const: allwinner,sun4i-a10

      - description: Linksprite PCDuino3
        items:
          - const: linksprite,pcduino3
          - const: allwinner,sun7i-a20

      - description: Linksprite PCDuino3 Nano
        items:
          - const: linksprite,pcduino3-nano
          - const: allwinner,sun7i-a20

      - description: Linutronix Testbox v2
        items:
          - const: linutronix,testbox-v2
          - const: lamobo,lamobo-r1
          - const: allwinner,sun7i-a20

      - description: HAOYU Electronics Marsboard A10
        items:
          - const: haoyu,a10-marsboard
          - const: allwinner,sun4i-a10

      - description: HAOYU Electronics Marsboard A20
        items:
          - const: haoyu,a20-marsboard
          - const: allwinner,sun7i-a20

      - description: MapleBoard MP130
        items:
          - const: mapleboard,mp130
          - const: allwinner,sun8i-h3

      - description: Mele A1000
        items:
          - const: mele,a1000
          - const: allwinner,sun4i-a10

      - description: Mele A1000G Quad Set Top Box
        items:
          - const: mele,a1000g-quad
          - const: allwinner,sun6i-a31

      - description: Mele I7 Quad Set Top Box
        items:
          - const: mele,i7
          - const: allwinner,sun6i-a31

      - description: Mele M3
        items:
          - const: mele,m3
          - const: allwinner,sun7i-a20

      - description: Mele M9 Set Top Box
        items:
          - const: mele,m9
          - const: allwinner,sun6i-a31

      - description: Merrii A20 Hummingboard
        items:
          - const: merrii,a20-hummingbird
          - const: allwinner,sun7i-a20

      - description: Merrii A31 Hummingboard
        items:
          - const: merrii,a31-hummingbird
          - const: allwinner,sun6i-a31

      - description: Merrii A80 Optimus
        items:
          - const: merrii,a80-optimus
          - const: allwinner,sun9i-a80

      - description: Miniand Hackberry
        items:
          - const: miniand,hackberry
          - const: allwinner,sun4i-a10

      - description: MK802
        items:
          - const: allwinner,mk802
          - const: allwinner,sun4i-a10

      - description: MK802-A10s
        items:
          - const: allwinner,a10s-mk802
          - const: allwinner,sun5i-a10s

      - description: MK802-II
        items:
          - const: allwinner,mk802ii
          - const: allwinner,sun4i-a10

      - description: MK808c
        items:
          - const: allwinner,mk808c
          - const: allwinner,sun7i-a20

      - description: MSI Primo81 Tablet
        items:
          - const: msi,primo81
          - const: allwinner,sun6i-a31s

      - description: Emlid Neutis N5 Developper Board
        items:
          - const: emlid,neutis-n5-devboard
          - const: emlid,neutis-n5
          - const: allwinner,sun50i-h5

      - description: Emlid Neutis N5H3 Developper Board
        items:
          - const: emlid,neutis-n5h3-devboard
          - const: emlid,neutis-n5h3
          - const: allwinner,sun8i-h3

      - description: NextThing Co. CHIP
        items:
          - const: nextthing,chip
          - const: allwinner,sun5i-r8
          - const: allwinner,sun5i-a13

      - description: NextThing Co. CHIP Pro
        items:
          - const: nextthing,chip-pro
          - const: nextthing,gr8

      - description: NextThing Co. GR8 Evaluation Board
        items:
          - const: nextthing,gr8-evb
          - const: nextthing,gr8

      - description: Nintendo NES Classic
        items:
          - const: nintendo,nes-classic
          - const: allwinner,sun8i-r16
          - const: allwinner,sun8i-a33

      - description: Nintendo Super NES Classic
        items:
          - const: nintendo,super-nes-classic
          - const: nintendo,nes-classic
          - const: allwinner,sun8i-r16
          - const: allwinner,sun8i-a33

      - description: Oceanic 5inMFD (5205)
        items:
          - const: oceanic,5205-5inmfd
          - const: allwinner,sun50i-a64

      - description: Olimex A10-OlinuXino LIME
        items:
          - const: olimex,a10-olinuxino-lime
          - const: allwinner,sun4i-a10

      - description: Olimex A10s-OlinuXino Micro
        items:
          - const: olimex,a10s-olinuxino-micro
          - const: allwinner,sun5i-a10s

      - description: Olimex A13-OlinuXino
        items:
          - const: olimex,a13-olinuxino
          - const: allwinner,sun5i-a13

      - description: Olimex A13-OlinuXino Micro
        items:
          - const: olimex,a13-olinuxino-micro
          - const: allwinner,sun5i-a13

      - description: Olimex A20-Olimex SOM Evaluation Board
        items:
          - const: olimex,a20-olimex-som-evb
          - const: allwinner,sun7i-a20

      - description: Olimex A20-Olimex SOM Evaluation Board (with eMMC)
        items:
          - const: olimex,a20-olimex-som-evb-emmc
          - const: allwinner,sun7i-a20

      - description: Olimex A20-OlinuXino LIME
        items:
          - const: olimex,a20-olinuxino-lime
          - const: allwinner,sun7i-a20

      - description: Olimex A20-OlinuXino LIME (with eMMC)
        items:
          - const: olimex,a20-olinuxino-lime-emmc
          - const: allwinner,sun7i-a20

      - description: Olimex A20-OlinuXino LIME2
        items:
          - const: olimex,a20-olinuxino-lime2
          - const: allwinner,sun7i-a20

      - description: Olimex A20-OlinuXino LIME2 (with eMMC)
        items:
          - const: olimex,a20-olinuxino-lime2-emmc
          - const: allwinner,sun7i-a20

      - description: Olimex A20-OlinuXino Micro
        items:
          - const: olimex,a20-olinuxino-micro
          - const: allwinner,sun7i-a20

      - description: Olimex A20-OlinuXino Micro (with eMMC)
        items:
          - const: olimex,a20-olinuxino-micro-emmc
          - const: allwinner,sun7i-a20

      - description: Olimex A20-SOM204 Evaluation Board
        items:
          - const: olimex,a20-olimex-som204-evb
          - const: allwinner,sun7i-a20

      - description: Olimex A20-SOM204 Evaluation Board (with eMMC)
        items:
          - const: olimex,a20-olimex-som204-evb-emmc
          - const: allwinner,sun7i-a20

      - description: Olimex A33-OlinuXino
        items:
          - const: olimex,a33-olinuxino
          - const: allwinner,sun8i-a33

      - description: Olimex A64-OlinuXino
        items:
          - const: olimex,a64-olinuxino
          - const: allwinner,sun50i-a64

      - description: Olimex A64-OlinuXino (with eMMC)
        items:
          - const: olimex,a64-olinuxino-emmc
          - const: allwinner,sun50i-a64

      - description: Olimex A64 Teres-I
        items:
          - const: olimex,a64-teres-i
          - const: allwinner,sun50i-a64

      - description: Pine64
        items:
          - const: pine64,pine64
          - const: allwinner,sun50i-a64

      - description: Pine64+
        items:
          - const: pine64,pine64-plus
          - const: allwinner,sun50i-a64

      - description: Pine64 PineCube
        items:
          - const: pine64,pinecube
          - const: sochip,s3
          - const: allwinner,sun8i-v3

      - description: Pine64 PineH64 model A
        items:
          - const: pine64,pine-h64
          - const: allwinner,sun50i-h6

      - description: Pine64 PineH64 model B
        items:
          - const: pine64,pine-h64-model-b
          - const: allwinner,sun50i-h6

      - description: Pine64 LTS
        items:
          - const: pine64,pine64-lts
          - const: allwinner,sun50i-r18
          - const: allwinner,sun50i-a64

      - description: Pine64 Pinebook
        items:
          - const: pine64,pinebook
          - const: allwinner,sun50i-a64

      - description: Pine64 PinePhone Developer Batch (1.0)
        items:
          - const: pine64,pinephone-1.0
          - const: pine64,pinephone
          - const: allwinner,sun50i-a64

      - description: Pine64 PinePhone Braveheart (1.1)
        items:
          - const: pine64,pinephone-1.1
          - const: pine64,pinephone
          - const: allwinner,sun50i-a64

      - description: Pine64 PinePhone (1.2)
        items:
          - const: pine64,pinephone-1.2
          - const: pine64,pinephone
          - const: allwinner,sun50i-a64

      - description: Pine64 PineTab, Development Sample
        items:
          - const: pine64,pinetab
          - const: allwinner,sun50i-a64

      - description: Pine64 PineTab, Early Adopter's batch (and maybe later ones)
        items:
          - const: pine64,pinetab-early-adopter
          - const: allwinner,sun50i-a64

      - description: Pine64 SoPine Baseboard
        items:
          - const: pine64,sopine-baseboard
          - const: pine64,sopine
          - const: allwinner,sun50i-a64

      - description: PineRiver Mini X-Plus
        items:
          - const: pineriver,mini-xplus
          - const: allwinner,sun4i-a10

      - description: PocketBook Touch Lux 3
        items:
          - const: pocketbook,touch-lux-3
          - const: allwinner,sun5i-a13

      - description: Point of View Protab2-IPS9
        items:
          - const: pov,protab2-ips9
          - const: allwinner,sun4i-a10

      - description: Polaroid MID2407PXE03 Tablet
        items:
          - const: polaroid,mid2407pxe03
          - const: allwinner,sun8i-a23

      - description: Polaroid MID2809PXE04 Tablet
        items:
          - const: polaroid,mid2809pxe04
          - const: allwinner,sun8i-a23

      - description: Q8 A13 Tablet
        items:
          - const: allwinner,q8-a13
          - const: allwinner,sun5i-a13

      - description: Q8 A23 Tablet
        items:
          - const: allwinner,q8-a23
          - const: allwinner,sun8i-a23

      - description: Q8 A33 Tablet
        items:
          - const: allwinner,q8-a33
          - const: allwinner,sun8i-a33

      - description: Qihua CQA3T BV3
        items:
          - const: qihua,t3-cqa3t-bv3
          - const: allwinner,sun8i-t3
          - const: allwinner,sun8i-r40

      - description: R7 A10s HDMI TV Stick
        items:
          - const: allwinner,r7-tv-dongle
          - const: allwinner,sun5i-a10s

      - description: RerVision H3-DVK
        items:
          - const: rervision,h3-dvk
          - const: allwinner,sun8i-h3

      - description: Sinlinx SinA31s Core Board
        items:
          - const: sinlinx,sina31s
          - const: allwinner,sun6i-a31s

      - description: Sinlinx SinA31s Development Board
        items:
          - const: sinlinx,sina31s-sdk
          - const: allwinner,sun6i-a31s

      - description: Sinlinx SinA33
        items:
          - const: sinlinx,sina33
          - const: allwinner,sun8i-a33

      - description: SL631 Action Camera with IMX179
        items:
          - const: allwinner,sl631-imx179
          - const: allwinner,sl631
          - const: allwinner,sun8i-v3

      - description: Tanix TX6
        items:
          - const: oranth,tanix-tx6
          - const: allwinner,sun50i-h6

      - description: Tanix TX6 mini
        items:
          - const: oranth,tanix-tx6-mini
          - const: allwinner,sun50i-h6

      - description: TBS A711 Tablet
        items:
          - const: tbs-biometrics,a711
          - const: allwinner,sun8i-a83t

      - description: Topwise A721 Tablet
        items:
          - const: topwise,a721
          - const: allwinner,sun4i-a10

      - description: Utoo P66
        items:
          - const: utoo,p66
          - const: allwinner,sun5i-a13

      - description: Wexler TAB7200
        items:
          - const: wexler,tab7200
          - const: allwinner,sun7i-a20

      - description: WITS A31 Colombus Evaluation Board
        items:
          - const: wits,colombus
          - const: allwinner,sun6i-a31

      - description: WITS Pro A20 DKT
        items:
          - const: wits,pro-a20-dkt
          - const: allwinner,sun7i-a20

      - description: Wobo i5
        items:
          - const: wobo,a10s-wobo-i5
          - const: allwinner,sun5i-a10s

      - description: Yones TopTech BS1078 v2 Tablet
        items:
          - const: yones-toptech,bs1078-v2
          - const: allwinner,sun6i-a31s

      - description: X96 Mate TV box
        items:
          - const: hechuang,x96-mate
          - const: allwinner,sun50i-h616

      - description: Xunlong OrangePi
        items:
          - const: xunlong,orangepi
          - const: allwinner,sun7i-a20

      - description: Xunlong OrangePi 2
        items:
          - const: xunlong,orangepi-2
          - const: allwinner,sun8i-h3

      - description: Xunlong OrangePi 3
        items:
          - const: xunlong,orangepi-3
          - const: allwinner,sun50i-h6

      - description: Xunlong OrangePi Lite
        items:
          - const: xunlong,orangepi-lite
          - const: allwinner,sun8i-h3

      - description: Xunlong OrangePi Lite2
        items:
          - const: xunlong,orangepi-lite2
          - const: allwinner,sun50i-h6

      - description: Xunlong OrangePi Mini
        items:
          - const: xunlong,orangepi-mini
          - const: allwinner,sun7i-a20

      - description: Xunlong OrangePi One
        items:
          - const: xunlong,orangepi-one
          - const: allwinner,sun8i-h3

      - description: Xunlong OrangePi One Plus
        items:
          - const: xunlong,orangepi-one-plus
          - const: allwinner,sun50i-h6

      - description: Xunlong OrangePi PC
        items:
          - const: xunlong,orangepi-pc
          - const: allwinner,sun8i-h3

      - description: Xunlong OrangePi PC 2
        items:
          - const: xunlong,orangepi-pc2
          - const: allwinner,sun50i-h5

      - description: Xunlong OrangePi PC Plus
        items:
          - const: xunlong,orangepi-pc-plus
          - const: allwinner,sun8i-h3

      - description: Xunlong OrangePi Plus
        items:
          - const: xunlong,orangepi-plus
          - const: allwinner,sun8i-h3

      - description: Xunlong OrangePi Plus 2E
        items:
          - const: xunlong,orangepi-plus2e
          - const: allwinner,sun8i-h3

      - description: Xunlong OrangePi Prime
        items:
          - const: xunlong,orangepi-prime
          - const: allwinner,sun50i-h5

      - description: Xunlong OrangePi R1
        items:
          - const: xunlong,orangepi-r1
          - const: allwinner,sun8i-h2-plus

      - description: Xunlong OrangePi Win
        items:
          - const: xunlong,orangepi-win
          - const: allwinner,sun50i-a64

      - description: Xunlong OrangePi Zero
        items:
          - const: xunlong,orangepi-zero
          - const: allwinner,sun8i-h2-plus

      - description: Xunlong OrangePi Zero Plus
        items:
          - const: xunlong,orangepi-zero-plus
          - const: allwinner,sun50i-h5

      - description: Xunlong OrangePi Zero Plus2
        items:
          - const: xunlong,orangepi-zero-plus2
          - const: allwinner,sun50i-h5

      - description: Xunlong OrangePi Zero Plus2
        items:
          - const: xunlong,orangepi-zero-plus2-h3
          - const: allwinner,sun8i-h3

      - description: Xunlong OrangePi Zero 2
        items:
          - const: xunlong,orangepi-zero2
          - const: allwinner,sun50i-h616

additionalProperties: true


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner Memory Bus (MBUS) controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |
  The MBUS controller drives the MBUS that other devices in the SoC
  will use to perform DMA. It also has a register interface that
  allows to monitor and control the bandwidth and priorities for
  masters on that bus.

  Each device having to perform their DMA through the MBUS must have
  the interconnects and interconnect-names properties set to the MBUS
  controller and with "dma-mem" as the interconnect name.

properties:
  "#interconnect-cells":
    const: 1
    description:
      The content of the cell is the MBUS ID.

  compatible:
    enum:
      - allwinner,sun5i-a13-mbus
      - allwinner,sun8i-a33-mbus
      - allwinner,sun8i-a50-mbus
      - allwinner,sun8i-a83t-mbus
      - allwinner,sun8i-h3-mbus
      - allwinner,sun8i-r40-mbus
      - allwinner,sun8i-v3s-mbus
      - allwinner,sun8i-v536-mbus
      - allwinner,sun20i-d1-mbus
      - allwinner,sun50i-a64-mbus
      - allwinner,sun50i-a100-mbus
      - allwinner,sun50i-h5-mbus
      - allwinner,sun50i-h6-mbus
      - allwinner,sun50i-h616-mbus
      - allwinner,sun50i-r329-mbus

  reg:
    minItems: 1
    items:
      - description: MBUS interconnect/bandwidth limit/PMU registers
      - description: DRAM controller/PHY registers

  reg-names:
    minItems: 1
    items:
      - const: mbus
      - const: dram

  clocks:
    minItems: 1
    items:
      - description: MBUS interconnect module clock
      - description: DRAM controller/PHY module clock
      - description: Register bus clock, shared by MBUS and DRAM

  clock-names:
    minItems: 1
    items:
      - const: mbus
      - const: dram
      - const: bus

  interrupts:
    maxItems: 1
    description:
      MBUS PMU activity interrupt.

  dma-ranges:
    description:
      See section 2.3.9 of the DeviceTree Specification.

  '#address-cells': true

  '#size-cells': true

required:
  - "#interconnect-cells"
  - compatible
  - reg
  - clocks
  - dma-ranges

if:
  not:
    properties:
      compatible:
        contains:
          enum:
            - allwinner,sun5i-a13-mbus
            - allwinner,sun8i-r40-mbus

then:
  properties:
    reg:
      minItems: 2

    reg-names:
      minItems: 2

    clocks:
      minItems: 3

    clock-names:
      minItems: 3

  required:
    - reg-names
    - clock-names

else:
  properties:
    reg:
      maxItems: 1

    reg-names:
      maxItems: 1

    clocks:
      maxItems: 1

    clock-names:
      maxItems: 1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/sun50i-a64-ccu.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    dram-controller@1c01000 {
        compatible = "allwinner,sun5i-a13-mbus";
        reg = <0x01c01000 0x1000>;
        clocks = <&ccu CLK_MBUS>;
        #address-cells = <1>;
        #size-cells = <1>;
        dma-ranges = <0x00000000 0x40000000 0x20000000>;
        #interconnect-cells = <1>;
    };

  - |
    dram-controller@1c62000 {
        compatible = "allwinner,sun50i-a64-mbus";
        reg = <0x01c62000 0x1000>,
              <0x01c63000 0x1000>;
        reg-names = "mbus", "dram";
        clocks = <&ccu CLK_MBUS>,
                 <&ccu CLK_DRAM>,
                 <&ccu CLK_BUS_DRAM>;
        clock-names = "mbus", "dram", "bus";
        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <1>;
        dma-ranges = <0x00000000 0x40000000 0xc0000000>;
        #interconnect-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun6i-a31-cpuconfig.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner CPU Configuration Controller Device Tree Bindings

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    enum:
      - allwinner,sun6i-a31-cpuconfig
      - allwinner,sun8i-a23-cpuconfig
      - allwinner,sun8i-a83t-cpucfg
      - allwinner,sun8i-a83t-r-cpucfg
      - allwinner,sun9i-a80-cpucfg

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
      cpucfg@1f01c00 {
          compatible = "allwinner,sun6i-a31-cpuconfig";
          reg = <0x01f01c00 0x300>;
      };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun9i-a80-prcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A80 PRCM Device Tree Bindings

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    const: allwinner,sun9i-a80-prcm

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
      prcm@8001400 {
          compatible = "allwinner,sun9i-a80-prcm";
          reg = <0x08001400 0x200>;
      };

...


code:
Synaptics SoC Device Tree Bindings

According to https://www.synaptics.com/company/news/conexant-marvell
Synaptics has acquired the Multimedia Solutions Business of Marvell, so
berlin SoCs are now Synaptics' SoCs now.

---------------------------------------------------------------

Work in progress statement:

Device tree files and bindings applying to Marvell Berlin SoCs and boards are
considered "unstable". Any Marvell Berlin device tree binding may change at any
time. Be sure to use a device tree binary and a kernel image generated from the
same source tree.

Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
stable binding/ABI.

---------------------------------------------------------------

Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:

* Required root node properties:
compatible: must contain "marvell,berlin"

In addition, the above compatible shall be extended with the specific
SoC and board used. Currently known SoC compatibles are:
    "marvell,berlin2"      for Marvell Armada 1500 (BG2, 88DE3100),
    "marvell,berlin2cd"    for Marvell Armada 1500-mini (BG2CD, 88DE3005)
    "marvell,berlin2ct"    for Marvell Armada ? (BG2CT, 88DE????)
    "marvell,berlin2q"     for Marvell Armada 1500-pro (BG2Q, 88DE3114)
    "marvell,berlin3"      for Marvell Armada ? (BG3, 88DE????)

* Example:

/ {
	model = "Sony NSZ-GS7";
	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";

	...
}

* Marvell Berlin CPU control bindings

CPU control register allows various operations on CPUs, like resetting them
independently.

Required properties:
- compatible: should be "marvell,berlin-cpu-ctrl"
- reg: address and length of the register set

Example:

cpu-ctrl@f7dd0000 {
	compatible = "marvell,berlin-cpu-ctrl";
	reg = <0xf7dd0000 0x10000>;
};

* Marvell Berlin2 chip control binding

Marvell Berlin SoCs have a chip control register set providing several
individual registers dealing with pinmux, padmux, clock, reset, and secondary
CPU boot address. Unfortunately, the individual registers are spread among the
chip control registers, so there should be a single DT node only providing the
different functions which are described below.

Required properties:
- compatible:
	* the first and second values must be:
		"simple-mfd", "syscon"
- reg: address and length of following register sets for
  BG2/BG2CD: chip control register set
  BG2Q: chip control register set and cpu pll registers

* Marvell Berlin2 system control binding

Marvell Berlin SoCs have a system control register set providing several
individual registers dealing with pinmux, padmux, and reset.

Required properties:
- compatible:
	* the first and second values must be:
		"simple-mfd", "syscon"
- reg: address and length of the system control register set

Example:

chip: chip-control@ea0000 {
	compatible = "simple-mfd", "syscon";
	reg = <0xea0000 0x400>;

	/* sub-device nodes */
};

sysctrl: system-controller@d000 {
	compatible = "simple-mfd", "syscon";
	reg = <0xd000 0x100>;

	/* sub-device nodes */
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/tegra.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jonathan Hunter <jonathanh@nvidia.com>

properties:
  $nodename:
    const: "/"
  compatible:
    oneOf:
      - items:
          - enum:
              - compal,paz00
              - compulab,trimslice
              - nvidia,harmony
              - nvidia,seaboard
              - nvidia,ventana
          - const: nvidia,tegra20
      - items:
          - enum:
              - ad,medcom-wide
              - ad,plutux
              - ad,tec
          - const: ad,tamonten
          - const: nvidia,tegra20
      - items:
          - enum:
              - toradex,colibri_t20-eval-v3
              - toradex,colibri_t20-iris
          - const: toradex,colibri_t20
          - const: nvidia,tegra20
      - items:
          - const: asus,tf101
          - const: nvidia,tegra20
      - items:
          - const: acer,picasso
          - const: nvidia,tegra20
      - items:
          - enum:
              - nvidia,beaver
          - const: nvidia,tegra30
      - items:
          - enum:
              - nvidia,cardhu-a02
              - nvidia,cardhu-a04
          - const: nvidia,cardhu
          - const: nvidia,tegra30
      - items:
          - const: asus,tf201
          - const: nvidia,tegra30
      - items:
          - const: asus,tf300t
          - const: nvidia,tegra30
      - items:
          - const: asus,tf300tg
          - const: nvidia,tegra30
      - items:
          - const: asus,tf700t
          - const: nvidia,tegra30
      - items:
          - const: toradex,apalis_t30-eval
          - const: toradex,apalis_t30
          - const: nvidia,tegra30
      - items:
          - const: toradex,apalis_t30-v1.1-eval
          - const: toradex,apalis_t30-eval
          - const: toradex,apalis_t30-v1.1
          - const: toradex,apalis_t30
          - const: nvidia,tegra30
      - items:
          - enum:
              - toradex,colibri_t30-eval-v3
          - const: toradex,colibri_t30
          - const: nvidia,tegra30
      - items:
          - const: asus,grouper
          - const: nvidia,tegra30
      - items:
          - const: asus,tilapia
          - const: asus,grouper
          - const: nvidia,tegra30
      - items:
          - const: ouya,ouya
          - const: nvidia,tegra30
      - items:
          - const: pegatron,chagall
          - const: nvidia,tegra30
      - items:
          - enum:
              - asus,tf701t
              - nvidia,dalmore
              - nvidia,roth
              - nvidia,tn7
          - const: nvidia,tegra114
      - items:
          - enum:
              - nvidia,jetson-tk1
              - nvidia,venice2
          - const: nvidia,tegra124
      - items:
          - const: toradex,apalis-tk1-eval
          - const: toradex,apalis-tk1
          - const: nvidia,tegra124
      - items:
          - const: toradex,apalis-tk1-v1.2-eval
          - const: toradex,apalis-tk1-eval
          - const: toradex,apalis-tk1-v1.2
          - const: toradex,apalis-tk1
          - const: nvidia,tegra124
      - items:
          - enum:
              - nvidia,norrin
          - const: nvidia,tegra132
          - const: nvidia,tegra124
      - items:
          - enum:
              - nvidia,darcy
              - nvidia,p2371-0000
              - nvidia,p2371-2180
              - nvidia,p2571
              - nvidia,p2894-0050-a08
          - const: nvidia,tegra210
      - description: Jetson TX2 Developer Kit
        items:
          - const: nvidia,p2771-0000
          - const: nvidia,tegra186
      - description: Jetson TX2 NX Developer Kit
        items:
          - const: nvidia,p3509-0000+p3636-0001
          - const: nvidia,tegra186
      - description: Jetson AGX Xavier Developer Kit
        items:
          - const: nvidia,p2972-0000
          - const: nvidia,tegra194
      - description: Jetson Xavier NX
        items:
          - const: nvidia,p3668-0000
          - const: nvidia,tegra194
      - description: Jetson Xavier NX (eMMC)
        items:
          - const: nvidia,p3668-0001
          - const: nvidia,tegra194
      - description: Jetson Xavier NX Developer Kit
        items:
          - const: nvidia,p3509-0000+p3668-0000
          - const: nvidia,tegra194
      - description: Jetson Xavier NX Developer Kit (eMMC)
        items:
          - const: nvidia,p3509-0000+p3668-0001
          - const: nvidia,tegra194
      - items:
          - const: nvidia,tegra234-vdk
          - const: nvidia,tegra234
      - description: Jetson AGX Orin
        items:
          - const: nvidia,p3701-0000
          - const: nvidia,tegra234
      - description: Jetson AGX Orin Developer Kit
        items:
          - const: nvidia,p3737-0000+p3701-0000
          - const: nvidia,p3701-0000
          - const: nvidia,tegra234

additionalProperties: true


code:
NVIDIA compliant embedded controller

Required properties:
- compatible : should be "nvidia,nvec".
- reg : the iomem of the i2c slave controller
- interrupts : the interrupt line of the i2c slave controller
- clock-frequency : the frequency of the i2c bus
- gpios : the gpio used for ec request
- slave-addr: the i2c address of the slave controller
- clocks : Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
- clock-names : Must include the following entries:
  Tegra20/Tegra30:
  - div-clk
  - fast-clk
  Tegra114:
  - div-clk
- resets : Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
  - i2c


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings

maintainers:
  - Sumit Gupta <sumitg@nvidia.com>
  - Mikko Perttunen <mperttunen@nvidia.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |+
  The Tegra CPU COMPLEX CLUSTER area contains memory-mapped
  registers that initiate CPU frequency/voltage transitions.

properties:
  $nodename:
    pattern: "ccplex@([0-9a-f]+)$"

  compatible:
    enum:
      - nvidia,tegra186-ccplex-cluster
      - nvidia,tegra234-ccplex-cluster

  reg:
    maxItems: 1

  nvidia,bpmp:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: |
      Specifies the BPMP node that needs to be queried to get
      operating point data for all CPUs.

additionalProperties: false

required:
  - compatible
  - reg
  - nvidia,bpmp

examples:
  - |
    ccplex@e000000 {
      compatible = "nvidia,tegra234-ccplex-cluster";
      reg = <0x0e000000 0x5ffff>;
      nvidia,bpmp = <&bpmp>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Power Management Controller (PMC)

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    enum:
      - nvidia,tegra186-pmc
      - nvidia,tegra194-pmc
      - nvidia,tegra234-pmc

  reg:
    minItems: 4
    maxItems: 5

  reg-names:
    minItems: 4
    items:
      - const: pmc
      - const: wake
      - const: aotag
      - const: scratch
      - const: misc

  interrupt-controller: true

  "#interrupt-cells":
    description: Specifies the number of cells needed to encode an
      interrupt source. The value must be 2.
    const: 2

  nvidia,invert-interrupt:
    description: If present, inverts the PMU interrupt signal.
    $ref: /schemas/types.yaml#/definitions/flag

if:
  properties:
    compatible:
      contains:
        const: nvidia,tegra186-pmc
then:
  properties:
    reg:
      maxItems: 4

    reg-names:
      maxItems: 4
else:
  properties:
    reg:
      minItems: 5

    reg-names:
      minItems: 5

patternProperties:
  "^[a-z0-9]+-[a-z0-9]+$":
    if:
      type: object
    then:
      description: |
        These are pad configuration nodes. On Tegra SoCs a pad is a set of
        pins which are configured as a group. The pin grouping is a fixed
        attribute of the hardware. The PMC can be used to set pad power
        state and signaling voltage. A pad can be either in active or
        power down mode. The support for power state and signaling voltage
        configuration varies depending on the pad in question. 3.3 V and
        1.8 V signaling voltages are supported on pins where software
        controllable signaling voltage switching is available.

        Pad configurations are described with pin configuration nodes
        which are placed under the pmc node and they are referred to by
        the pinctrl client properties. For more information see

          Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

        The following pads are present on Tegra186:

          csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
          pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
          hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
          dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
          sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv

        The following pads are present on Tegra194:

          csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
          pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
          pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
          soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
          hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
          pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
          spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
          audio-hv, ao-hv

      properties:
        pins:
          $ref: /schemas/types.yaml#/definitions/string
          description: Must contain the name of the pad(s) to be
            configured.

        low-power-enable:
          description: Configure the pad into power down mode.
          $ref: /schemas/types.yaml#/definitions/flag

        low-power-disable:
          description: Configure the pad into active mode.
          $ref: /schemas/types.yaml#/definitions/flag

        power-source:
          $ref: /schemas/types.yaml#/definitions/uint32
          description: |
            Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
            TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
            voltages.

            The values are defined in

              include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h

            The power state can be configured on all of the above pads
            except for ao-hv. Following pads have software configurable
            signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
            audio-hv, ao-hv.

        phandle: true

      required:
        - pins

      additionalProperties: false

required:
  - compatible
  - reg
  - reg-names

additionalProperties: false

dependencies:
  interrupt-controller: ['#interrupt-cells']
  "#interrupt-cells":
    required:
      - interrupt-controller

examples:
  - |
    #include <dt-bindings/clock/tegra186-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
    #include <dt-bindings/memory/tegra186-mc.h>
    #include <dt-bindings/reset/tegra186-reset.h>

    pmc@c3600000 {
        compatible = "nvidia,tegra186-pmc";
        reg = <0x0c360000 0x10000>,
              <0x0c370000 0x10000>,
              <0x0c380000 0x10000>,
              <0x0c390000 0x10000>;
        reg-names = "pmc", "wake", "aotag", "scratch";
        nvidia,invert-interrupt;

        sdmmc1_3v3: sdmmc1-3v3 {
            pins = "sdmmc1-hv";
            power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
        };

        sdmmc1_1v8: sdmmc1-1v8 {
            pins = "sdmmc1-hv";
            power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
        };
    };

    sdmmc1: mmc@3400000 {
        compatible = "nvidia,tegra186-sdhci";
        reg = <0x03400000 0x10000>;
        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
                 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
        clock-names = "sdhci", "tmclk";
        resets = <&bpmp TEGRA186_RESET_SDMMC1>;
        reset-names = "sdhci";
        interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
                        <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
        interconnect-names = "dma-mem", "write";
        iommus = <&smmu TEGRA186_SID_SDMMC1>;
        pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
        pinctrl-0 = <&sdmmc1_3v3>;
        pinctrl-1 = <&sdmmc1_1v8>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: NVIDIA Tegra194 AXI2APB bridge

maintainers:
  - Sumit Gupta <sumitg@nvidia.com>

properties:
  $nodename:
    pattern: "^axi2apb@([0-9a-f]+)$"

  compatible:
    enum:
      - nvidia,tegra194-axi2apb

  reg:
    maxItems: 6
    description: Physical base address and length of registers for all bridges

additionalProperties: false

required:
  - compatible
  - reg

examples:
  - |
    axi2apb: axi2apb@2390000 {
      compatible = "nvidia,tegra194-axi2apb";
      reg = <0x02390000 0x1000>,
            <0x023a0000 0x1000>,
            <0x023b0000 0x1000>,
            <0x023c0000 0x1000>,
            <0x023d0000 0x1000>,
            <0x023e0000 0x1000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: NVIDIA Tegra194 CBB 1.0 bindings

maintainers:
  - Sumit Gupta <sumitg@nvidia.com>

description: |+
  The Control Backbone (CBB) is comprised of the physical path from an
  initiator to a target's register configuration space. CBB 1.0 has
  multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
  initiators and targets using different bridges like AXIP2P, AXI2APB.

  This driver handles errors due to illegal register accesses reported
  by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs
  "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
  which is the main NOC.

  By default, the access issuing initiator is informed about the error
  using SError or Data Abort exception unless the ERD (Error Response
  Disable) is enabled/set for that initiator. If the ERD is enabled, then
  SError or Data Abort is masked and the error is reported with interrupt.

  - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
    errors due to illegal accesses from CCPLEX are reported by interrupts.
    If ERD is not set, then error is reported by SError.
  - For other initiators, the ERD is disabled. So, the access issuing
    initiator is informed about the illegal access by Data Abort exception.
    In addition, an interrupt is also generated to CCPLEX. These initiators
    include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
    engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder
    engine) etc which can initiate transactions.

  The driver prints relevant debug information like Error Code, Error
  Description, Master, Address, AXI ID, Cache, Protection, Security Group
  etc on receiving error notification.

properties:
  $nodename:
    pattern: "^[a-z]+-noc@[0-9a-f]+$"

  compatible:
    enum:
      - nvidia,tegra194-cbb-noc
      - nvidia,tegra194-aon-noc
      - nvidia,tegra194-bpmp-noc
      - nvidia,tegra194-rce-noc
      - nvidia,tegra194-sce-noc

  reg:
    maxItems: 1

  interrupts:
    description:
      CCPLEX receives secure or nonsecure interrupt depending on error type.
      A secure interrupt is received for SEC(firewall) & SLV errors and a
      non-secure interrupt is received for TMO & DEC errors.
    items:
      - description: non-secure interrupt
      - description: secure interrupt

  nvidia,axi2apb:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description:
      Specifies the node having all axi2apb bridges which need to be checked
      for any error logged in their status register.

  nvidia,apbmisc:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description:
      Specifies the apbmisc node which need to be used for reading the ERD
      register.

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - nvidia,apbmisc

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    cbb-noc@2300000 {
        compatible = "nvidia,tegra194-cbb-noc";
        reg = <0x02300000 0x1000>;
        interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
        nvidia,axi2apb = <&axi2apb>;
        nvidia,apbmisc = <&apbmisc>;
    };


code:
NVIDIA Tegra AHB

Required properties:
- compatible : For Tegra20, must contain "nvidia,tegra20-ahb".  For
  Tegra30, must contain "nvidia,tegra30-ahb".  Otherwise, must contain
  '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
  tegra132, or tegra210.
- reg : Should contain 1 register ranges(address and length).  For
  Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004
  0x10c>.  For Tegra124, Tegra132 and Tegra210 chips, the value should
  be be <0x6000c000 0x150>.

Example (for a Tegra20 chip):
	ahb: ahb@6000c004 {
		compatible = "nvidia,tegra20-ahb";
		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
	};


code:
NVIDIA Tegra Flow Controller

Required properties:
- compatible: Should contain one of the following:
  - "nvidia,tegra20-flowctrl": for Tegra20
  - "nvidia,tegra30-flowctrl": for Tegra30
  - "nvidia,tegra114-flowctrl": for Tegra114
  - "nvidia,tegra124-flowctrl": for Tegra124
  - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132
  - "nvidia,tegra210-flowctrl": for Tegra210
- reg: Should contain one register range (address and length)

Example:

	flow-controller@60007000 {
		compatible = "nvidia,tegra20-flowctrl";
		reg = <0x60007000 0x1000>;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Tegra Power Management Controller (PMC)

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jonathan Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    enum:
      - nvidia,tegra20-pmc
      - nvidia,tegra30-pmc
      - nvidia,tegra114-pmc
      - nvidia,tegra124-pmc
      - nvidia,tegra210-pmc

  reg:
    maxItems: 1
    description:
      Offset and length of the register set for the device.

  clock-names:
    items:
      - const: pclk
      - const: clk32k_in
    description:
      Must includes entries pclk and clk32k_in.
      pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
      input to Tegra.

  clocks:
    maxItems: 2
    description:
      Must contain an entry for each entry in clock-names.
      See ../clocks/clocks-bindings.txt for details.

  '#clock-cells':
    const: 1
    description:
      Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
      PMC also has blink control which allows 32Khz clock output to
      Tegra blink pad.
      Consumer of PMC clock should specify the desired clock by having
      the clock ID in its "clocks" phandle cell with pmc clock provider.
      See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
      clock IDs.

  '#interrupt-cells':
    const: 2
    description:
      Specifies number of cells needed to encode an interrupt source.
      The value must be 2.

  interrupt-controller: true

  nvidia,invert-interrupt:
    $ref: /schemas/types.yaml#/definitions/flag
    description: Inverts the PMU interrupt signal.
      The PMU is an external Power Management Unit, whose interrupt output
      signal is fed into the PMC. This signal is optionally inverted, and
      then fed into the ARM GIC. The PMC is not involved in the detection
      or handling of this interrupt signal, merely its inversion.

  nvidia,core-power-req-active-high:
    $ref: /schemas/types.yaml#/definitions/flag
    description: Core power request active-high.

  nvidia,sys-clock-req-active-high:
    $ref: /schemas/types.yaml#/definitions/flag
    description: System clock request active-high.

  nvidia,combined-power-req:
    $ref: /schemas/types.yaml#/definitions/flag
    description: combined power request for CPU and Core.

  nvidia,cpu-pwr-good-en:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      CPU power good signal from external PMIC to PMC is enabled.

  nvidia,suspend-mode:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2]
    description:
      The suspend mode that the platform should use.
      Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
      Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
      Mode 2 is for LP2, CPU voltage off

  nvidia,cpu-pwr-good-time:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: CPU power good time in uSec.

  nvidia,cpu-pwr-off-time:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: CPU power off time in uSec.

  nvidia,core-pwr-good-time:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description:
      <Oscillator-stable-time Power-stable-time>
      Core power good time in uSec.

  nvidia,core-pwr-off-time:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Core power off time in uSec.

  nvidia,lp0-vec:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description:
      <start length> Starting address and length of LP0 vector.
      The LP0 vector contains the warm boot code that is executed
      by AVP when resuming from the LP0 state.
      The AVP (Audio-Video Processor) is an ARM7 processor and
      always being the first boot processor when chip is power on
      or resume from deep sleep mode. When the system is resumed
      from the deep sleep mode, the warm boot code will restore
      some PLLs, clocks and then brings up CPU0 for resuming the
      system.

  core-supply:
    description:
      Phandle to voltage regulator connected to the SoC Core power rail.

  core-domain:
    type: object
    description: |
      The vast majority of hardware blocks of Tegra SoC belong to a
      Core power domain, which has a dedicated voltage rail that powers
      the blocks.

    properties:
      operating-points-v2:
        description:
          Should contain level, voltages and opp-supported-hw property.
          The supported-hw is a bitfield indicating SoC speedo or process
          ID mask.

      "#power-domain-cells":
        const: 0

    required:
      - operating-points-v2
      - "#power-domain-cells"

    additionalProperties: false

  i2c-thermtrip:
    type: object
    description:
      On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
      hardware-triggered thermal reset will be enabled.

    properties:
      nvidia,i2c-controller-id:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          ID of I2C controller to send poweroff command to PMU.
          Valid values are described in section 9.2.148
          "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
          Manual.

      nvidia,bus-addr:
        $ref: /schemas/types.yaml#/definitions/uint32
        description: Bus address of the PMU on the I2C bus.

      nvidia,reg-addr:
        $ref: /schemas/types.yaml#/definitions/uint32
        description: PMU I2C register address to issue poweroff command.

      nvidia,reg-data:
        $ref: /schemas/types.yaml#/definitions/uint32
        description: Poweroff command to write to PMU.

      nvidia,pinmux-id:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Pinmux used by the hardware when issuing Poweroff command.
          Defaults to 0. Valid values are described in section 12.5.2
          "Pinmux Support" of the Tegra4 Technical Reference Manual.

    required:
      - nvidia,i2c-controller-id
      - nvidia,bus-addr
      - nvidia,reg-addr
      - nvidia,reg-data

    additionalProperties: false

  powergates:
    type: object
    description: |
      This node contains a hierarchy of power domain nodes, which should
      match the powergates on the Tegra SoC. Each powergate node
      represents a power-domain on the Tegra SoC that can be power-gated
      by the Tegra PMC.
      Hardware blocks belonging to a power domain should contain
      "power-domains" property that is a phandle pointing to corresponding
      powergate node.
      The name of the powergate node should be one of the below. Note that
      not every powergate is applicable to all Tegra devices and the following
      list shows which powergates are applicable to which devices.
      Please refer to Tegra TRM for mode details on the powergate nodes to
      use for each power-gate block inside Tegra.
      Name		Description			            Devices Applicable
      3d		  3D Graphics			            Tegra20/114/124/210
      3d0		  3D Graphics 0		            Tegra30
      3d1		  3D Graphics 1		            Tegra30
      aud		  Audio				                Tegra210
      dfd		  Debug				                Tegra210
      dis		  Display A			              Tegra114/124/210
      disb		Display B			              Tegra114/124/210
      heg		  2D Graphics		            	Tegra30/114/124/210
      iram		Internal RAM		            Tegra124/210
      mpe		  MPEG Encode			            All
      nvdec		NVIDIA Video Decode Engine	Tegra210
      nvjpg		NVIDIA JPEG Engine		      Tegra210
      pcie		PCIE				                Tegra20/30/124/210
      sata		SATA				                Tegra30/124/210
      sor		  Display interfaces       		Tegra124/210
      ve2		  Video Encode Engine 2		    Tegra210
      venc		Video Encode Engine		      All
      vdec		Video Decode Engine		      Tegra20/30/114/124
      vic		  Video Imaging Compositor	  Tegra124/210
      xusba		USB Partition A			        Tegra114/124/210
      xusbb		USB Partition B 		        Tegra114/124/210
      xusbc		USB Partition C			        Tegra114/124/210

    patternProperties:
      "^[a-z0-9]+$":
        type: object

        properties:
          clocks:
            minItems: 1
            maxItems: 8
            description:
              Must contain an entry for each clock required by the PMC
              for controlling a power-gate.
              See ../clocks/clock-bindings.txt document for more details.

          resets:
            minItems: 1
            maxItems: 8
            description:
              Must contain an entry for each reset required by the PMC
              for controlling a power-gate.
              See ../reset/reset.txt for more details.

          '#power-domain-cells':
            const: 0
            description: Must be 0.

        required:
          - clocks
          - resets
          - '#power-domain-cells'

    additionalProperties: false

patternProperties:
  "^[a-f0-9]+-[a-f0-9]+$":
    type: object
    description:
      This is a Pad configuration node. On Tegra SOCs a pad is a set of
      pins which are configured as a group. The pin grouping is a fixed
      attribute of the hardware. The PMC can be used to set pad power state
      and signaling voltage. A pad can be either in active or power down mode.
      The support for power state and signaling voltage configuration varies
      depending on the pad in question. 3.3V and 1.8V signaling voltages
      are supported on pins where software controllable signaling voltage
      switching is available.

      The pad configuration state nodes are placed under the pmc node and they
      are referred to by the pinctrl client properties. For more information
      see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
      The pad name should be used as the value of the pins property in pin
      configuration nodes.

      The following pads are present on Tegra124 and Tegra132
      audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
      hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
      sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.

      The following pads are present on Tegra210
      audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
      debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
      hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
      sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.

    properties:
      pins:
        $ref: /schemas/types.yaml#/definitions/string
        description: Must contain name of the pad(s) to be configured.

      low-power-enable:
        $ref: /schemas/types.yaml#/definitions/flag
        description: Configure the pad into power down mode.

      low-power-disable:
        $ref: /schemas/types.yaml#/definitions/flag
        description: Configure the pad into active mode.

      power-source:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
          TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
          The values are defined in
          include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
          Power state can be configured on all Tegra124 and Tegra132
          pads. None of the Tegra124 or Tegra132 pads support signaling
          voltage switching.
          All of the listed Tegra210 pads except pex-cntrl support power
          state configuration. Signaling voltage switching is supported
          on below Tegra210 pads.
          audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
          sdmmc3, spi, spi-hv, and uart.

    required:
      - pins

    additionalProperties: false

required:
  - compatible
  - reg
  - clock-names
  - clocks
  - '#clock-cells'

additionalProperties: false

dependencies:
  "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
  "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
  "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]

examples:
  - |

    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
    #include <dt-bindings/soc/tegra-pmc.h>

    tegra_pmc: pmc@7000e400 {
              compatible = "nvidia,tegra210-pmc";
              reg = <0x7000e400 0x400>;
              core-supply = <&regulator>;
              clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
              clock-names = "pclk", "clk32k_in";
              #clock-cells = <1>;

              nvidia,invert-interrupt;
              nvidia,suspend-mode = <0>;
              nvidia,cpu-pwr-good-time = <0>;
              nvidia,cpu-pwr-off-time = <0>;
              nvidia,core-pwr-good-time = <4587 3876>;
              nvidia,core-pwr-off-time = <39065>;
              nvidia,core-power-req-active-high;
              nvidia,sys-clock-req-active-high;

              pd_core: core-domain {
                      operating-points-v2 = <&core_opp_table>;
                      #power-domain-cells = <0>;
              };

              powergates {
                    pd_audio: aud {
                            clocks = <&tegra_car TEGRA210_CLK_APE>,
                                     <&tegra_car TEGRA210_CLK_APB2APE>;
                            resets = <&tegra_car 198>;
                            power-domains = <&pd_core>;
                            #power-domain-cells = <0>;
                    };

                    pd_xusbss: xusba {
                            clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
                            resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
                            power-domains = <&pd_core>;
                            #power-domain-cells = <0>;
                    };
              };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: NVIDIA Tegra CBB 2.0 bindings

maintainers:
  - Sumit Gupta <sumitg@nvidia.com>

description: |+
  The Control Backbone (CBB) is comprised of the physical path from an
  initiator to a target's register configuration space. CBB 2.0 consists
  of multiple sub-blocks connected to each other to create a topology.
  The Tegra234 SoC has different fabrics based on CBB 2.0 architecture
  which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and
  "CBB central fabric".

  In CBB 2.0, each initiator which can issue transactions connects to a
  Root Master Node (MN) before it connects to any other element of the
  fabric. Each Root MN contains a Error Monitor (EM) which detects and
  logs error. Interrupts from various EM blocks are collated by Error
  Notifier (EN) which is per fabric and presents a single interrupt from
  fabric to the SoC interrupt controller.

  The driver handles errors from CBB due to illegal register accesses
  and prints debug information about failed transaction on receiving
  the interrupt from EN. Debug information includes Error Code, Error
  Description, MasterID, Fabric, SlaveID, Address, Cache, Protection,
  Security Group etc on receiving error notification.

  If the Error Response Disable (ERD) is set/enabled for an initiator,
  then SError or Data abort exception error response is masked and an
  interrupt is used for reporting errors due to illegal accesses from
  that initiator. The value returned on read failures is '0xFFFFFFFF'
  for compatibility with PCIE.

properties:
  $nodename:
    pattern: "^[a-z]+-fabric@[0-9a-f]+$"

  compatible:
    enum:
      - nvidia,tegra234-aon-fabric
      - nvidia,tegra234-bpmp-fabric
      - nvidia,tegra234-cbb-fabric
      - nvidia,tegra234-dce-fabric
      - nvidia,tegra234-rce-fabric
      - nvidia,tegra234-sce-fabric

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: secure interrupt from error notifier

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    cbb-fabric@1300000 {
      compatible = "nvidia,tegra234-cbb-fabric";
      reg = <0x13a00000 0x400000>;
      interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/tesla.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Tesla Full Self Driving(FSD) platforms

maintainers:
  - Alim Akhtar <alim.akhtar@samsung.com>
  - linux-fsd@tesla.com

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:

      - description: FSD SoC board
        items:
          - enum:
              - tesla,fsd-evb   # Tesla FSD Evaluation
          - const: tesla,fsd

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/ti/k3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments K3 Multicore SoC architecture device tree bindings

maintainers:
  - Nishanth Menon <nm@ti.com>

description: |
  Platforms based on Texas Instruments K3 Multicore SoC architecture
  shall have the following properties.

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:

      - description: K3 AM62A7 SoC
        items:
          - enum:
              - ti,am62a7-sk
          - const: ti,am62a7

      - description: K3 AM625 SoC
        items:
          - enum:
              - ti,am625-sk
          - const: ti,am625

      - description: K3 AM642 SoC
        items:
          - enum:
              - ti,am642-evm
              - ti,am642-sk
          - const: ti,am642

      - description: K3 AM654 SoC
        items:
          - enum:
              - siemens,iot2050-advanced
              - siemens,iot2050-advanced-pg2
              - siemens,iot2050-basic
              - siemens,iot2050-basic-pg2
              - ti,am654-evm
          - const: ti,am654

      - description: K3 J7200 SoC
        oneOf:
          - const: ti,j7200
          - items:
              - enum:
                  - ti,j7200-evm
              - const: ti,j7200

      - description: K3 J721E SoC
        oneOf:
          - const: ti,j721e
          - items:
              - enum:
                  - beagle,j721e-beagleboneai64
                  - ti,j721e-evm
                  - ti,j721e-sk
              - const: ti,j721e

      - description: K3 J721s2 SoC
        items:
          - enum:
              - ti,j721s2-evm
          - const: ti,j721s2

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/ti/nspire.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI-NSPIRE calculators

maintainers:
  - Daniel Tang <dt.tangr@gmail.com>

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          # CX models
          - ti,nspire-cx
          # Touchpad models
          - ti,nspire-tp
          # Clickpad models
          - ti,nspire-clp

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/ti/ti,davinci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments DaVinci Platforms Device Tree Bindings

maintainers:
  - Sekhar Nori <nsekhar@ti.com>

description:
  DA850/OMAP-L138/AM18x based boards

properties:
  $nodename:
    const: '/'
  compatible:
    items:
      - enum:
          - ti,da850-evm    # DA850/OMAP-L138/AM18x Evaluation Module (EVM) board
          - ti,da850-lcdk   # DA850/OMAP-L138/AM18x L138/C6748 Development Kit (LCDK) board
          - enbw,cmc        # EnBW AM1808 based CMC board
          - lego,ev3        # LEGO MINDSTORMS EV3 (AM1808 based)
      - const: ti,da850

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/toshiba.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Toshiba Visconti Platform

maintainers:
  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: Visconti5 TMPV7708
        items:
          - enum:
              - toshiba,tmpv7708-rm-mbrc  # TMPV7708 RM main board
              - toshiba,tmpv7708-visrobo-vrb  # TMPV7708 VisROBO VRB board
          - const: toshiba,tmpv7708

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/ux500.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ux500 platforms

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:

      - description: ST-Ericsson HREF (pre-v60)
        items:
          - const: st-ericsson,mop500
          - const: st-ericsson,u8500

      - description: ST-Ericsson HREF520
        items:
          - const: st-ericsson,href520
          - const: st-ericsson,u8500

      - description: ST-Ericsson HREF (v60+)
        items:
          - const: st-ericsson,hrefv60+
          - const: st-ericsson,u8500

      - description: Calao Systems Snowball
        items:
          - const: calaosystems,snowball-a9500
          - const: st-ericsson,u9500

      - description: Samsung Galaxy Ace 2 (GT-I8160)
        items:
          - const: samsung,codina
          - const: st-ericsson,u8500

      - description: Samsung Galaxy Exhibit (SGH-T599)
        items:
          - const: samsung,codina-tmo
          - const: st-ericsson,u8500

      - description: Samsung Galaxy Beam (GT-I8530)
        items:
          - const: samsung,gavini
          - const: st-ericsson,u8500

      - description: Samsung Galaxy S III mini (GT-I8190)
        items:
          - const: samsung,golden
          - const: st-ericsson,u8500

      - description: Samsung Galaxy S Advance (GT-I9070)
        items:
          - const: samsung,janice
          - const: st-ericsson,u8500

      - description: Samsung Galaxy Amp (SGH-I407)
        items:
          - const: samsung,kyle
          - const: st-ericsson,u8500

      - description: Samsung Galaxy XCover 2 (GT-S7710)
        items:
          - const: samsung,skomer
          - const: st-ericsson,u8500

additionalProperties: true


code:
ST-Ericsson Ux500 boards
------------------------

Required properties (in root node) one of these:
	compatible = "st-ericsson,mop500" (legacy)
	compatible = "st-ericsson,u8500"

Required node (under root node):

soc: represents the system-on-chip and contains the chip
peripherals

Required property of soc node, one of these:
	compatible = "stericsson,db8500"

Required subnodes under soc node:

backupram: (used for CPU spin tables and for storing data
during retention, system won't boot without this):
	compatible = "ste,dbx500-backupram"

scu:
	see binding for arm/arm,scu.yaml

interrupt-controller:
	see binding for interrupt-controller/arm,gic.txt

timer:
	see binding for timer/arm,twd-timer.yaml

clocks:
	see binding for clocks/ux500.txt

Example:

/dts-v1/;

/ {
        model = "ST-Ericsson HREF (pre-v60) and ST UIB";
        compatible = "st-ericsson,mop500", "st-ericsson,u8500";

        soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "stericsson,db8500";
		interrupt-parent = <&intc>;
		ranges;

		backupram@80150000 {
			compatible = "ste,dbx500-backupram";
			reg = <0x80150000 0x2000>;
		};

		intc: interrupt-controller@a0411000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			interrupt-controller;
			reg = <0xa0411000 0x1000>,
			      <0xa0410100 0x100>;
		};

		scu@a0410000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xa0410000 0x100>;
		};

		timer@a0410600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xa0410600 0x20>;
			interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
			clocks = <&smp_twd_clk>;
		};

		clocks {
			compatible = "stericsson,u8500-clks";

			smp_twd_clk: smp-twd-clock {
				#clock-cells = <0>;
			};
		};
        };
};


code:
* ST-Ericsson UX500 PM Domains

UX500 supports multiple PM domains which are used to gate power to one or
more peripherals on the SOC.

The implementation of PM domains for UX500 are based upon the generic PM domain
and use the corresponding DT bindings.

==PM domain providers==

Required properties:
 - compatible: Must be "stericsson,ux500-pm-domains".
 - #power-domain-cells : Number of cells in a power domain specifier, must be 1.

Example:
	pm_domains: pm_domains0 {
		compatible = "stericsson,ux500-pm-domains";
		#power-domain-cells = <1>;
	};

==PM domain consumers==

Required properties:
 - power-domains: A phandle and PM domain specifier. Below are the list of
		valid specifiers:

		Index	Specifier
		-----	---------
		0	DOMAIN_VAPE

Example:
	sdi0_per1@80126000 {
		compatible = "arm,pl18x", "arm,primecell";
		power-domains = <&pm_domains DOMAIN_VAPE>
	};