code:
/*
 * Copyright (c) 2017 MediaTek Inc.
 * Author: Ming Huang <ming.huang@mediatek.com>
 *	   Sean Wang <sean.wang@mediatek.com>
 *
 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7622-clk.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/reset/mt7622-reset.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "mediatek,mt7622";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpu_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;
		opp-300000000 {
			opp-hz = /bits/ 64 <30000000>;
			opp-microvolt = <950000>;
		};

		opp-437500000 {
			opp-hz = /bits/ 64 <437500000>;
			opp-microvolt = <1000000>;
		};

		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <1050000>;
		};

		opp-812500000 {
			opp-hz = /bits/ 64 <812500000>;
			opp-microvolt = <1100000>;
		};

		opp-1025000000 {
			opp-hz = /bits/ 64 <1025000000>;
			opp-microvolt = <1150000>;
		};

		opp-1137500000 {
			opp-hz = /bits/ 64 <1137500000>;
			opp-microvolt = <1200000>;
		};

		opp-1262500000 {
			opp-hz = /bits/ 64 <1262500000>;
			opp-microvolt = <1250000>;
		};

		opp-1350000000 {
			opp-hz = /bits/ 64 <1350000000>;
			opp-microvolt = <1310000>;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
				 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
			enable-method = "psci";
			clock-frequency = <1300000000>;
			cci-control-port = <&cci_control2>;
			next-level-cache = <&L2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
				 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cpu_opp_table>;
			#cooling-cells = <2>;
			enable-method = "psci";
			clock-frequency = <1300000000>;
			cci-control-port = <&cci_control2>;
			next-level-cache = <&L2>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	pwrap_clk: dummy40m {
		compatible = "fixed-clock";
		clock-frequency = <40000000>;
		#clock-cells = <0>;
	};

	clk25m: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
		clock-output-names = "clkxtal";
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
		secmon_reserved: secmon@43000000 {
			reg = <0 0x43000000 0 0x30000>;
			no-map;
		};
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <1000>;
			polling-delay = <1000>;

			thermal-sensors = <&thermal 0>;

			trips {
				cpu_passive: cpu-passive {
					temperature = <47000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_active: cpu-active {
					temperature = <67000>;
					hysteresis = <2000>;
					type = "active";
				};

				cpu_hot: cpu-hot {
					temperature = <87000>;
					hysteresis = <2000>;
					type = "hot";
				};

				cpu-crit {
					temperature = <107000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_passive>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};

				map1 {
					trip = <&cpu_active>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};

				map2 {
					trip = <&cpu_hot>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
			      IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
			      IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
			      IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
			      IRQ_TYPE_LEVEL_HIGH)>;
	};

	infracfg: infracfg@10000000 {
		compatible = "mediatek,mt7622-infracfg",
			     "syscon";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pwrap: pwrap@10001000 {
		compatible = "mediatek,mt7622-pwrap";
		reg = <0 0x10001000 0 0x250>;
		reg-names = "pwrap";
		clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
		clock-names = "spi", "wrap";
		resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
		reset-names = "pwrap";
		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	pericfg: pericfg@10002000 {
		compatible = "mediatek,mt7622-pericfg",
			     "syscon";
		reg = <0 0x10002000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	scpsys: power-controller@10006000 {
		compatible = "mediatek,mt7622-scpsys",
			     "syscon";
		#power-domain-cells = <1>;
		reg = <0 0x10006000 0 0x1000>;
		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
		infracfg = <&infracfg>;
		clocks = <&topckgen CLK_TOP_HIF_SEL>;
		clock-names = "hif_sel";
	};

	cir: cir@10009000 {
		compatible = "mediatek,mt7622-cir";
		reg = <0 0x10009000 0 0x1000>;
		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg CLK_INFRA_IRRX_PD>,
			 <&topckgen CLK_TOP_AXI_SEL>;
		clock-names = "clk", "bus";
		status = "disabled";
	};

	sysirq: interrupt-controller@10200620 {
		compatible = "mediatek,mt7622-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10200620 0 0x20>;
	};

	efuse: efuse@10206000 {
		compatible = "mediatek,mt7622-efuse",
			     "mediatek,efuse";
		reg = <0 0x10206000 0 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		thermal_calibration: calib@198 {
			reg = <0x198 0xc>;
		};
	};

	apmixedsys: apmixedsys@10209000 {
		compatible = "mediatek,mt7622-apmixedsys",
			     "syscon";
		reg = <0 0x10209000 0 0x1000>;
		#clock-cells = <1>;
	};

	topckgen: topckgen@10210000 {
		compatible = "mediatek,mt7622-topckgen",
			     "syscon";
		reg = <0 0x10210000 0 0x1000>;
		#clock-cells = <1>;
	};

	rng: rng@1020f000 {
		compatible = "mediatek,mt7622-rng",
			     "mediatek,mt7623-rng";
		reg = <0 0x1020f000 0 0x1000>;
		clocks = <&infracfg CLK_INFRA_TRNG>;
		clock-names = "rng";
	};

	pio: pinctrl@10211000 {
		compatible = "mediatek,mt7622-pinctrl";
		reg = <0 0x10211000 0 0x1000>,
		      <0 0x10005000 0 0x1000>;
		reg-names = "base", "eint";
		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&pio 0 0 103>;
		interrupt-controller;
		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		#interrupt-cells = <2>;
	};

	watchdog: watchdog@10212000 {
		compatible = "mediatek,mt7622-wdt",
			     "mediatek,mt6589-wdt";
		reg = <0 0x10212000 0 0x800>;
	};

	rtc: rtc@10212800 {
		compatible = "mediatek,mt7622-rtc",
			     "mediatek,soc-rtc";
		reg = <0 0x10212800 0 0x200>;
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_RTC>;
		clock-names = "rtc";
	};

	gic: interrupt-controller@10300000 {
		compatible = "arm,gic-400";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10310000 0 0x1000>,
		      <0 0x10320000 0 0x1000>,
		      <0 0x10340000 0 0x2000>,
		      <0 0x10360000 0 0x2000>;
	};

	cci: cci@10390000 {
		compatible = "arm,cci-400";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0 0x10390000 0 0x1000>;
		ranges = <0 0 0x10390000 0x10000>;

		cci_control0: slave-if@1000 {
			compatible = "arm,cci-400-ctrl-if";
			interface-type = "ace-lite";
			reg = <0x1000 0x1000>;
		};

		cci_control1: slave-if@4000 {
			compatible = "arm,cci-400-ctrl-if";
			interface-type = "ace";
			reg = <0x4000 0x1000>;
		};

		cci_control2: slave-if@5000 {
			compatible = "arm,cci-400-ctrl-if", "syscon";
			interface-type = "ace";
			reg = <0x5000 0x1000>;
		};

		pmu@9000 {
			compatible = "arm,cci-400-pmu,r1";
			reg = <0x9000 0x5000>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	auxadc: adc@11001000 {
		compatible = "mediatek,mt7622-auxadc";
		reg = <0 0x11001000 0 0x1000>;
		clocks = <&pericfg CLK_PERI_AUXADC_PD>;
		clock-names = "main";
		#io-channel-cells = <1>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt7622-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_UART_SEL>,
			 <&pericfg CLK_PERI_UART0_PD>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt7622-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_UART_SEL>,
			 <&pericfg CLK_PERI_UART1_PD>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt7622-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_UART_SEL>,
			 <&pericfg CLK_PERI_UART2_PD>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt7622-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11005000 0 0x400>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_UART_SEL>,
			 <&pericfg CLK_PERI_UART3_PD>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	pwm: pwm@11006000 {
		compatible = "mediatek,mt7622-pwm";
		reg = <0 0x11006000 0 0x1000>;
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_PWM_SEL>,
			 <&pericfg CLK_PERI_PWM_PD>,
			 <&pericfg CLK_PERI_PWM1_PD>,
			 <&pericfg CLK_PERI_PWM2_PD>,
			 <&pericfg CLK_PERI_PWM3_PD>,
			 <&pericfg CLK_PERI_PWM4_PD>,
			 <&pericfg CLK_PERI_PWM5_PD>,
			 <&pericfg CLK_PERI_PWM6_PD>;
		clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
			      "pwm5", "pwm6";
		status = "disabled";
	};

	i2c0: i2c@11007000 {
		compatible = "mediatek,mt7622-i2c";
		reg = <0 0x11007000 0 0x90>,
		      <0 0x11000100 0 0x80>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C0_PD>,
			 <&pericfg CLK_PERI_AP_DMA_PD>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c1: i2c@11008000 {
		compatible = "mediatek,mt7622-i2c";
		reg = <0 0x11008000 0 0x90>,
		      <0 0x11000180 0 0x80>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C1_PD>,
			 <&pericfg CLK_PERI_AP_DMA_PD>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@11009000 {
		compatible = "mediatek,mt7622-i2c";
		reg = <0 0x11009000 0 0x90>,
		      <0 0x11000200 0 0x80>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C2_PD>,
			 <&pericfg CLK_PERI_AP_DMA_PD>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi0: spi@1100a000 {
		compatible = "mediatek,mt7622-spi";
		reg = <0 0x1100a000 0 0x100>;
		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI0_SEL>,
			 <&pericfg CLK_PERI_SPI0_PD>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	thermal: thermal@1100b000 {
		#thermal-sensor-cells = <1>;
		compatible = "mediatek,mt7622-thermal";
		reg = <0 0x1100b000 0 0x1000>;
		interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_THERM_PD>,
			 <&pericfg CLK_PERI_AUXADC_PD>;
		clock-names = "therm", "auxadc";
		resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
		reset-names = "therm";
		mediatek,auxadc = <&auxadc>;
		mediatek,apmixedsys = <&apmixedsys>;
		nvmem-cells = <&thermal_calibration>;
		nvmem-cell-names = "calibration-data";
	};

	btif: serial@1100c000 {
		compatible = "mediatek,mt7622-btif",
			     "mediatek,mtk-btif";
		reg = <0 0x1100c000 0 0x1000>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_BTIF_PD>;
		clock-names = "main";
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";

		bluetooth {
			compatible = "mediatek,mt7622-bluetooth";
			power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
			clocks = <&clk25m>;
			clock-names = "ref";
		};
	};

	nandc: nfi@1100d000 {
		compatible = "mediatek,mt7622-nfc";
		reg = <0 0x1100D000 0 0x1000>;
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI_PD>,
			 <&pericfg CLK_PERI_SNFI_PD>;
		clock-names = "nfi_clk", "pad_clk";
		ecc-engine = <&bch>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	snfi: spi@1100d000 {
		compatible = "mediatek,mt7622-snand";
		reg = <0 0x1100d000 0 0x1000>;
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
		clock-names = "nfi_clk", "pad_clk";
		nand-ecc-engine = <&bch>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	bch: ecc@1100e000 {
		compatible = "mediatek,mt7622-ecc";
		reg = <0 0x1100e000 0 0x1000>;
		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFIECC_PD>;
		clock-names = "nfiecc_clk";
		status = "disabled";
	};

	nor_flash: spi@11014000 {
		compatible = "mediatek,mt7622-nor",
			     "mediatek,mt8173-nor";
		reg = <0 0x11014000 0 0xe0>;
		clocks = <&pericfg CLK_PERI_FLASH_PD>,
			 <&topckgen CLK_TOP_FLASH_SEL>;
		clock-names = "spi", "sf";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi1: spi@11016000 {
		compatible = "mediatek,mt7622-spi";
		reg = <0 0x11016000 0 0x100>;
		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI1_SEL>,
			 <&pericfg CLK_PERI_SPI1_PD>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	uart4: serial@11019000 {
		compatible = "mediatek,mt7622-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11019000 0 0x400>;
		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_UART_SEL>,
			 <&pericfg CLK_PERI_UART4_PD>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	audsys: clock-controller@11220000 {
		compatible = "mediatek,mt7622-audsys", "syscon";
		reg = <0 0x11220000 0 0x2000>;
		#clock-cells = <1>;

		afe: audio-controller {
			compatible = "mediatek,mt7622-audio";
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
				     <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
			interrupt-names = "afe", "asys";

			clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
				 <&topckgen CLK_TOP_AUD1_SEL>,
				 <&topckgen CLK_TOP_AUD2_SEL>,
				 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
				 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
				 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
				 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
				 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
				 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
				 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
				 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
				 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
				 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
				 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
				 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
				 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
				 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
				 <&audsys CLK_AUDIO_I2SO1>,
				 <&audsys CLK_AUDIO_I2SO2>,
				 <&audsys CLK_AUDIO_I2SO3>,
				 <&audsys CLK_AUDIO_I2SO4>,
				 <&audsys CLK_AUDIO_I2SIN1>,
				 <&audsys CLK_AUDIO_I2SIN2>,
				 <&audsys CLK_AUDIO_I2SIN3>,
				 <&audsys CLK_AUDIO_I2SIN4>,
				 <&audsys CLK_AUDIO_ASRCO1>,
				 <&audsys CLK_AUDIO_ASRCO2>,
				 <&audsys CLK_AUDIO_ASRCO3>,
				 <&audsys CLK_AUDIO_ASRCO4>,
				 <&audsys CLK_AUDIO_AFE>,
				 <&audsys CLK_AUDIO_AFE_CONN>,
				 <&audsys CLK_AUDIO_A1SYS>,
				 <&audsys CLK_AUDIO_A2SYS>;

			clock-names = "infra_sys_audio_clk",
				      "top_audio_mux1_sel",
				      "top_audio_mux2_sel",
				      "top_audio_a1sys_hp",
				      "top_audio_a2sys_hp",
				      "i2s0_src_sel",
				      "i2s1_src_sel",
				      "i2s2_src_sel",
				      "i2s3_src_sel",
				      "i2s0_src_div",
				      "i2s1_src_div",
				      "i2s2_src_div",
				      "i2s3_src_div",
				      "i2s0_mclk_en",
				      "i2s1_mclk_en",
				      "i2s2_mclk_en",
				      "i2s3_mclk_en",
				      "i2so0_hop_ck",
				      "i2so1_hop_ck",
				      "i2so2_hop_ck",
				      "i2so3_hop_ck",
				      "i2si0_hop_ck",
				      "i2si1_hop_ck",
				      "i2si2_hop_ck",
				      "i2si3_hop_ck",
				      "asrc0_out_ck",
				      "asrc1_out_ck",
				      "asrc2_out_ck",
				      "asrc3_out_ck",
				      "audio_afe_pd",
				      "audio_afe_conn_pd",
				      "audio_a1sys_pd",
				      "audio_a2sys_pd";

			assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
					  <&topckgen CLK_TOP_A2SYS_HP_SEL>,
					  <&topckgen CLK_TOP_A1SYS_HP_DIV>,
					  <&topckgen CLK_TOP_A2SYS_HP_DIV>;
			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
						 <&topckgen CLK_TOP_AUD2PLL>;
			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
		};
	};

	mmc0: mmc@11230000 {
		compatible = "mediatek,mt7622-mmc";
		reg = <0 0x11230000 0 0x1000>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
			 <&topckgen CLK_TOP_MSDC50_0_SEL>;
		clock-names = "source", "hclk";
		resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
		reset-names = "hrst";
		status = "disabled";
	};

	mmc1: mmc@11240000 {
		compatible = "mediatek,mt7622-mmc";
		reg = <0 0x11240000 0 0x1000>;
		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
			 <&topckgen CLK_TOP_AXI_SEL>;
		clock-names = "source", "hclk";
		resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;
		reset-names = "hrst";
		status = "disabled";
	};

	wmac: wmac@18000000 {
		compatible = "mediatek,mt7622-wmac";
		reg = <0 0x18000000 0 0x100000>;
		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;

		mediatek,infracfg = <&infracfg>;
		status = "disabled";

		power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
	};

	ssusbsys: ssusbsys@1a000000 {
		compatible = "mediatek,mt7622-ssusbsys",
			     "syscon";
		reg = <0 0x1a000000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	ssusb: usb@1a0c0000 {
		compatible = "mediatek,mt7622-xhci",
			     "mediatek,mtk-xhci";
		reg = <0 0x1a0c0000 0 0x01000>,
		      <0 0x1a0c4700 0 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
		clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
			 <&ssusbsys CLK_SSUSB_REF_EN>,
			 <&ssusbsys CLK_SSUSB_MCU_EN>,
			 <&ssusbsys CLK_SSUSB_DMA_EN>;
		clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
		phys = <&u2port0 PHY_TYPE_USB2>,
		       <&u3port0 PHY_TYPE_USB3>,
		       <&u2port1 PHY_TYPE_USB2>;

		status = "disabled";
	};

	u3phy: t-phy@1a0c4000 {
		compatible = "mediatek,mt7622-tphy",
			     "mediatek,generic-tphy-v1";
		reg = <0 0x1a0c4000 0 0x700>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		u2port0: usb-phy@1a0c4800 {
			reg = <0 0x1a0c4800 0 0x0100>;
			#phy-cells = <1>;
			clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
			clock-names = "ref";
		};

		u3port0: usb-phy@1a0c4900 {
			reg = <0 0x1a0c4900 0 0x0700>;
			#phy-cells = <1>;
			clocks = <&clk25m>;
			clock-names = "ref";
		};

		u2port1: usb-phy@1a0c5000 {
			reg = <0 0x1a0c5000 0 0x0100>;
			#phy-cells = <1>;
			clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
			clock-names = "ref";
		};
	};

	pciesys: pciesys@1a100800 {
		compatible = "mediatek,mt7622-pciesys",
			     "syscon";
		reg = <0 0x1a100800 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pciecfg: pciecfg@1a140000 {
		compatible = "mediatek,generic-pciecfg", "syscon";
		reg = <0 0x1a140000 0 0x1000>;
	};

	pcie0: pcie@1a143000 {
		compatible = "mediatek,mt7622-pcie";
		device_type = "pci";
		reg = <0 0x1a143000 0 0x1000>;
		reg-names = "port0";
		linux,pci-domain = <0>;
		#address-cells = <3>;
		#size-cells = <2>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "pcie_irq";
		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
			 <&pciesys CLK_PCIE_P0_AHB_EN>,
			 <&pciesys CLK_PCIE_P0_AUX_EN>,
			 <&pciesys CLK_PCIE_P0_AXI_EN>,
			 <&pciesys CLK_PCIE_P0_OBFF_EN>,
			 <&pciesys CLK_PCIE_P0_PIPE_EN>;
		clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
			      "axi_ck0", "obff_ck0", "pipe_ck0";

		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
		bus-range = <0x00 0xff>;
		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
		status = "disabled";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
				<0 0 0 2 &pcie_intc0 1>,
				<0 0 0 3 &pcie_intc0 2>,
				<0 0 0 4 &pcie_intc0 3>;
		pcie_intc0: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};
	};

	pcie1: pcie@1a145000 {
		compatible = "mediatek,mt7622-pcie";
		device_type = "pci";
		reg = <0 0x1a145000 0 0x1000>;
		reg-names = "port1";
		linux,pci-domain = <1>;
		#address-cells = <3>;
		#size-cells = <2>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "pcie_irq";
		clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
			 /* designer has connect RC1 with p0_ahb clock */
			 <&pciesys CLK_PCIE_P0_AHB_EN>,
			 <&pciesys CLK_PCIE_P1_AUX_EN>,
			 <&pciesys CLK_PCIE_P1_AXI_EN>,
			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
		clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
			      "axi_ck1", "obff_ck1", "pipe_ck1";

		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
		bus-range = <0x00 0xff>;
		ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
		status = "disabled";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
				<0 0 0 2 &pcie_intc1 1>,
				<0 0 0 3 &pcie_intc1 2>,
				<0 0 0 4 &pcie_intc1 3>;
		pcie_intc1: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};
	};

	sata: sata@1a200000 {
		compatible = "mediatek,mt7622-ahci",
			     "mediatek,mtk-ahci";
		reg = <0 0x1a200000 0 0x1100>;
		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hostc";
		clocks = <&pciesys CLK_SATA_AHB_EN>,
			 <&pciesys CLK_SATA_AXI_EN>,
			 <&pciesys CLK_SATA_ASIC_EN>,
			 <&pciesys CLK_SATA_RBC_EN>,
			 <&pciesys CLK_SATA_PM_EN>;
		clock-names = "ahb", "axi", "asic", "rbc", "pm";
		phys = <&sata_port PHY_TYPE_SATA>;
		phy-names = "sata-phy";
		ports-implemented = <0x1>;
		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
		resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
			 <&pciesys MT7622_SATA_PHY_SW_RST>,
			 <&pciesys MT7622_SATA_PHY_REG_RST>;
		reset-names = "axi", "sw", "reg";
		mediatek,phy-mode = <&pciesys>;
		status = "disabled";
	};

	sata_phy: t-phy@1a243000 {
		compatible = "mediatek,mt7622-tphy",
			     "mediatek,generic-tphy-v1";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		sata_port: sata-phy@1a243000 {
			reg = <0 0x1a243000 0 0x0100>;
			clocks = <&topckgen CLK_TOP_ETH_500M>;
			clock-names = "ref";
			#phy-cells = <1>;
		};
	};

	hifsys: syscon@1af00000 {
		compatible = "mediatek,mt7622-hifsys", "syscon";
		reg = <0 0x1af00000 0 0x70>;
	};

	ethsys: syscon@1b000000 {
		compatible = "mediatek,mt7622-ethsys",
			     "syscon";
		reg = <0 0x1b000000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	hsdma: dma-controller@1b007000 {
		compatible = "mediatek,mt7622-hsdma";
		reg = <0 0x1b007000 0 0x1000>;
		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&ethsys CLK_ETH_HSDMA_EN>;
		clock-names = "hsdma";
		power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
		#dma-cells = <1>;
		dma-requests = <3>;
	};

	pcie_mirror: pcie-mirror@10000400 {
		compatible = "mediatek,mt7622-pcie-mirror",
			     "syscon";
		reg = <0 0x10000400 0 0x10>;
	};

	wed0: wed@1020a000 {
		compatible = "mediatek,mt7622-wed",
			     "syscon";
		reg = <0 0x1020a000 0 0x1000>;
		interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
	};

	wed1: wed@1020b000 {
		compatible = "mediatek,mt7622-wed",
			     "syscon";
		reg = <0 0x1020b000 0 0x1000>;
		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;
	};

	eth: ethernet@1b100000 {
		compatible = "mediatek,mt7622-eth",
			     "mediatek,mt2701-eth",
			     "syscon";
		reg = <0 0x1b100000 0 0x20000>;
		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_ETH_SEL>,
			 <&ethsys CLK_ETH_ESW_EN>,
			 <&ethsys CLK_ETH_GP0_EN>,
			 <&ethsys CLK_ETH_GP1_EN>,
			 <&ethsys CLK_ETH_GP2_EN>,
			 <&sgmiisys CLK_SGMII_TX250M_EN>,
			 <&sgmiisys CLK_SGMII_RX250M_EN>,
			 <&sgmiisys CLK_SGMII_CDR_REF>,
			 <&sgmiisys CLK_SGMII_CDR_FB>,
			 <&topckgen CLK_TOP_SGMIIPLL>,
			 <&apmixedsys CLK_APMIXED_ETH2PLL>;
		clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
			      "sgmii_tx250m", "sgmii_rx250m",
			      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
			      "eth2pll";
		power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
		mediatek,ethsys = <&ethsys>;
		mediatek,sgmiisys = <&sgmiisys>;
		cci-control-port = <&cci_control2>;
		mediatek,wed = <&wed0>, <&wed1>;
		mediatek,pcie-mirror = <&pcie_mirror>;
		mediatek,hifsys = <&hifsys>;
		dma-coherent;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	sgmiisys: sgmiisys@1b128000 {
		compatible = "mediatek,mt7622-sgmiisys",
			     "syscon";
		reg = <0 0x1b128000 0 0x3000>;
		#clock-cells = <1>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2021 MediaTek Inc.
 * Author: Sam.Shih <sam.shih@mediatek.com>
 */

/dts-v1/;
#include "mt7986a.dtsi"

/ {
	model = "MediaTek MT7986a RFB";
	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x40000000>;
	};
};

&crypto {
	status = "okay";
};

&eth {
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "2500base-x";

		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
		};
	};

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;
	};
};

&mdio {
	switch: switch@0 {
		compatible = "mediatek,mt7531";
		reg = <31>;
		reset-gpios = <&pio 5 0>;
	};
};

&pio {
	spi_flash_pins: spi-flash-pins {
		mux {
			function = "spi";
			groups = "spi0", "spi0_wp_hold";
		};
	};

	spic_pins: spic-pins {
		mux {
			function = "spi";
			groups = "spi1_2";
		};
	};

	uart1_pins: uart1-pins {
		mux {
			function = "uart";
			groups = "uart1";
		};
	};

	uart2_pins: uart2-pins {
		mux {
			function = "uart";
			groups = "uart2";
		};
	};

	wf_2g_5g_pins: wf-2g-5g-pins {
		mux {
			function = "wifi";
			groups = "wf_2g", "wf_5g";
		};
		conf {
			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
			       "WF1_TOP_CLK", "WF1_TOP_DATA";
			drive-strength = <4>;
		};
	};

	wf_dbdc_pins: wf-dbdc-pins {
		mux {
			function = "wifi";
			groups = "wf_dbdc";
		};
		conf {
			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
			       "WF0_TOP_CLK", "WF0_TOP_DATA";
			drive-strength = <4>;
		};
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_flash_pins>;
	cs-gpios = <0>, <0>;
	status = "okay";
	spi_nand: spi_nand@0 {
		compatible = "spi-nand";
		reg = <0>;
		spi-max-frequency = <10000000>;
		spi-tx-buswidth = <4>;
		spi-rx-buswidth = <4>;
	};
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic_pins>;
	cs-gpios = <0>, <0>;
	status = "okay";
};

&switch {
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			label = "lan0";
		};

		port@1 {
			reg = <1>;
			label = "lan1";
		};

		port@2 {
			reg = <2>;
			label = "lan2";
		};

		port@3 {
			reg = <3>;
			label = "lan3";
		};

		port@4 {
			reg = <4>;
			label = "lan4";
		};

		port@6 {
			reg = <6>;
			label = "cpu";
			ethernet = <&gmac0>;
			phy-mode = "2500base-x";

			fixed-link {
				speed = <2500>;
				full-duplex;
				pause;
			};
		};
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
	status = "okay";
};

&wifi {
	status = "okay";
	pinctrl-names = "default", "dbdc";
	pinctrl-0 = <&wf_2g_5g_pins>;
	pinctrl-1 = <&wf_dbdc_pins>;
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2021 MediaTek Inc.
 * Author: Sam.Shih <sam.shih@mediatek.com>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7986-clk.h>
#include <dt-bindings/reset/mt7986-resets.h>

/ {
	compatible = "mediatek,mt7986a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	clk40m: oscillator-40m {
		compatible = "fixed-clock";
		clock-frequency = <40000000>;
		#clock-cells = <0>;
		clock-output-names = "clkxtal";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x0>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x1>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x2>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			enable-method = "psci";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			#cooling-cells = <2>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
		secmon_reserved: secmon@43000000 {
			reg = <0 0x43000000 0 0x30000>;
			no-map;
		};

		wmcpu_emi: wmcpu-reserved@4fc00000 {
			no-map;
			reg = <0 0x4fc00000 0 0x00100000>;
		};

		wo_emi0: wo-emi@4fd00000 {
			reg = <0 0x4fd00000 0 0x40000>;
			no-map;
		};

		wo_emi1: wo-emi@4fd40000 {
			reg = <0 0x4fd40000 0 0x40000>;
			no-map;
		};

		wo_ilm0: wo-ilm@151e0000 {
			reg = <0 0x151e0000 0 0x8000>;
			no-map;
		};

		wo_ilm1: wo-ilm@151f0000 {
			reg = <0 0x151f0000 0 0x8000>;
			no-map;
		};

		wo_data: wo-data@4fd80000 {
			reg = <0 0x4fd80000 0 0x240000>;
			no-map;
		};

		wo_dlm0: wo-dlm@151e8000 {
			reg = <0 0x151e8000 0 0x2000>;
			no-map;
		};

		wo_dlm1: wo-dlm@151f8000 {
			reg = <0 0x151f8000 0 0x2000>;
			no-map;
		};

		wo_boot: wo-boot@15194000 {
			reg = <0 0x15194000 0 0x1000>;
			no-map;
		};

	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		gic: interrupt-controller@c000000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			reg = <0 0x0c000000 0 0x10000>,  /* GICD */
			      <0 0x0c080000 0 0x80000>,  /* GICR */
			      <0 0x0c400000 0 0x2000>,   /* GICC */
			      <0 0x0c410000 0 0x1000>,   /* GICH */
			      <0 0x0c420000 0 0x2000>;   /* GICV */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		infracfg: infracfg@10001000 {
			compatible = "mediatek,mt7986-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
		};

		wed_pcie: wed-pcie@10003000 {
			compatible = "mediatek,mt7986-wed-pcie",
				     "syscon";
			reg = <0 0x10003000 0 0x10>;
		};

		topckgen: topckgen@1001b000 {
			compatible = "mediatek,mt7986-topckgen", "syscon";
			reg = <0 0x1001B000 0 0x1000>;
			#clock-cells = <1>;
		};

		watchdog: watchdog@1001c000 {
			compatible = "mediatek,mt7986-wdt",
				     "mediatek,mt6589-wdt";
			reg = <0 0x1001c000 0 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			#reset-cells = <1>;
			status = "disabled";
		};

		apmixedsys: apmixedsys@1001e000 {
			compatible = "mediatek,mt7986-apmixedsys";
			reg = <0 0x1001E000 0 0x1000>;
			#clock-cells = <1>;
		};

		pio: pinctrl@1001f000 {
			compatible = "mediatek,mt7986a-pinctrl";
			reg = <0 0x1001f000 0 0x1000>,
			      <0 0x11c30000 0 0x1000>,
			      <0 0x11c40000 0 0x1000>,
			      <0 0x11e20000 0 0x1000>,
			      <0 0x11e30000 0 0x1000>,
			      <0 0x11f00000 0 0x1000>,
			      <0 0x11f10000 0 0x1000>,
			      <0 0x1000b000 0 0x1000>;
			reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
				    "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pio 0 0 100>;
			interrupt-controller;
			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			#interrupt-cells = <2>;
		};

		sgmiisys0: syscon@10060000 {
			compatible = "mediatek,mt7986-sgmiisys_0",
				     "syscon";
			reg = <0 0x10060000 0 0x1000>;
			#clock-cells = <1>;
		};

		sgmiisys1: syscon@10070000 {
			compatible = "mediatek,mt7986-sgmiisys_1",
				     "syscon";
			reg = <0 0x10070000 0 0x1000>;
			#clock-cells = <1>;
		};

		trng: rng@1020f000 {
			compatible = "mediatek,mt7986-rng",
				     "mediatek,mt7623-rng";
			reg = <0 0x1020f000 0 0x100>;
			clocks = <&infracfg CLK_INFRA_TRNG_CK>;
			clock-names = "rng";
			status = "disabled";
		};

		crypto: crypto@10320000 {
			compatible = "inside-secure,safexcel-eip97";
			reg = <0 0x10320000 0 0x40000>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ring0", "ring1", "ring2", "ring3";
			clocks = <&infracfg CLK_INFRA_EIP97_CK>;
			clock-names = "infra_eip97_ck";
			assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
			status = "disabled";
		};

		uart0: serial@11002000 {
			compatible = "mediatek,mt7986-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11002000 0 0x400>;
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
				 <&infracfg CLK_INFRA_UART0_CK>;
			clock-names = "baud", "bus";
			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
					  <&infracfg CLK_INFRA_UART0_SEL>;
			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
						 <&topckgen CLK_TOP_UART_SEL>;
			status = "disabled";
		};

		uart1: serial@11003000 {
			compatible = "mediatek,mt7986-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11003000 0 0x400>;
			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
				 <&infracfg CLK_INFRA_UART1_CK>;
			clock-names = "baud", "bus";
			assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
			status = "disabled";
		};

		uart2: serial@11004000 {
			compatible = "mediatek,mt7986-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11004000 0 0x400>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
				 <&infracfg CLK_INFRA_UART2_CK>;
			clock-names = "baud", "bus";
			assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
			status = "disabled";
		};

		i2c0: i2c@11008000 {
			compatible = "mediatek,mt7986-i2c";
			reg = <0 0x11008000 0 0x90>,
			      <0 0x10217080 0 0x80>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clock-div = <5>;
			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
				 <&infracfg CLK_INFRA_AP_DMA_CK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi0: spi@1100a000 {
			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x1100a000 0 0x100>;
			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&topckgen CLK_TOP_MPLL_D2>,
				 <&topckgen CLK_TOP_SPI_SEL>,
				 <&infracfg CLK_INFRA_SPI0_CK>,
				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
			status = "disabled";
		};

		spi1: spi@1100b000 {
			compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x1100b000 0 0x100>;
			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&topckgen CLK_TOP_MPLL_D2>,
				 <&topckgen CLK_TOP_SPIM_MST_SEL>,
				 <&infracfg CLK_INFRA_SPI1_CK>,
				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
			status = "disabled";
		};

		ethsys: syscon@15000000 {
			 #address-cells = <1>;
			 #size-cells = <1>;
			 compatible = "mediatek,mt7986-ethsys",
				      "syscon";
			 reg = <0 0x15000000 0 0x1000>;
			 #clock-cells = <1>;
			 #reset-cells = <1>;
		};

		wed0: wed@15010000 {
			compatible = "mediatek,mt7986-wed",
				     "syscon";
			reg = <0 0x15010000 0 0x1000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
			memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
					<&wo_data>, <&wo_boot>;
			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
					      "wo-data", "wo-boot";
			mediatek,wo-ccif = <&wo_ccif0>;
		};

		wed1: wed@15011000 {
			compatible = "mediatek,mt7986-wed",
				     "syscon";
			reg = <0 0x15011000 0 0x1000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
			memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
					<&wo_data>, <&wo_boot>;
			memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
					      "wo-data", "wo-boot";
			mediatek,wo-ccif = <&wo_ccif1>;
		};

		wo_ccif0: syscon@151a5000 {
			compatible = "mediatek,mt7986-wo-ccif", "syscon";
			reg = <0 0x151a5000 0 0x1000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
		};

		wo_ccif1: syscon@151ad000 {
			compatible = "mediatek,mt7986-wo-ccif", "syscon";
			reg = <0 0x151ad000 0 0x1000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
		};

		eth: ethernet@15100000 {
			compatible = "mediatek,mt7986-eth";
			reg = <0 0x15100000 0 0x80000>;
			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ethsys CLK_ETH_FE_EN>,
				 <&ethsys CLK_ETH_GP2_EN>,
				 <&ethsys CLK_ETH_GP1_EN>,
				 <&ethsys CLK_ETH_WOCPU1_EN>,
				 <&ethsys CLK_ETH_WOCPU0_EN>,
				 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
				 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
				 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
				 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
				 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
				 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
				 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
				 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
				 <&topckgen CLK_TOP_NETSYS_SEL>,
				 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
			clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
				      "sgmii_tx250m", "sgmii_rx250m",
				      "sgmii_cdr_ref", "sgmii_cdr_fb",
				      "sgmii2_tx250m", "sgmii2_rx250m",
				      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
				      "netsys0", "netsys1";
			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
					  <&topckgen CLK_TOP_SGM_325M_SEL>;
			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
						 <&apmixedsys CLK_APMIXED_SGMPLL>;
			mediatek,ethsys = <&ethsys>;
			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
			mediatek,wed-pcie = <&wed_pcie>;
			mediatek,wed = <&wed0>, <&wed1>;
			#reset-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		wifi: wifi@18000000 {
			compatible = "mediatek,mt7986-wmac";
			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
			reset-names = "consys";
			clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
			clock-names = "mcu", "ap2conn";
			reg = <0 0x18000000 0 0x1000000>,
			      <0 0x10003000 0 0x1000>,
			      <0 0x11d10000 0 0x1000>;
			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
			memory-region = <&wmcpu_emi>;
		};
	};

};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2021 MediaTek Inc.
 * Author: Sam.Shih <sam.shih@mediatek.com>
 */

/dts-v1/;
#include "mt7986b.dtsi"

/ {
	model = "MediaTek MT7986b RFB";
	compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x40000000>;
	};
};

&crypto {
	status = "okay";
};

&eth {
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "2500base-x";

		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
		};
	};

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		switch@0 {
			compatible = "mediatek,mt7531";
			reg = <31>;
			reset-gpios = <&pio 5 0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "lan0";
				};

				port@1 {
					reg = <1>;
					label = "lan1";
				};

				port@2 {
					reg = <2>;
					label = "lan2";
				};

				port@3 {
					reg = <3>;
					label = "lan3";
				};

				port@4 {
					reg = <4>;
					label = "lan4";
				};

				port@6 {
					reg = <6>;
					label = "cpu";
					ethernet = <&gmac0>;
					phy-mode = "2500base-x";

					fixed-link {
						speed = <2500>;
						full-duplex;
						pause;
					};
				};
			};
		};
	};
};

&pio {
	spi_flash_pins: spi-flash-pins {
		mux {
			function = "spi";
			groups = "spi0", "spi0_wp_hold";
		};
	};

	spic_pins: spic-pins {
		mux {
			function = "spi";
			groups = "spi1_2";
		};
	};

	wf_2g_5g_pins: wf-2g-5g-pins {
		mux {
			function = "wifi";
			groups = "wf_2g", "wf_5g";
		};
		conf {
			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
			       "WF1_TOP_CLK", "WF1_TOP_DATA";
			drive-strength = <4>;
		};
	};

	wf_dbdc_pins: wf-dbdc-pins {
		mux {
			function = "wifi";
			groups = "wf_dbdc";
		};
		conf {
			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
			       "WF0_TOP_CLK", "WF0_TOP_DATA";
			drive-strength = <4>;
		};
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi_flash_pins>;
	cs-gpios = <0>, <0>;
	status = "okay";
	spi_nand: spi_nand@0 {
		compatible = "spi-nand";
		reg = <0>;
		spi-max-frequency = <10000000>;
		spi-tx-buswidth = <4>;
		spi-rx-buswidth = <4>;
	};
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spic_pins>;
	cs-gpios = <0>, <0>;
	status = "okay";
};

&uart0 {
	status = "okay";
};

&wifi {
	status = "okay";
	pinctrl-names = "default", "dbdc";
	pinctrl-0 = <&wf_2g_5g_pins>;
	pinctrl-1 = <&wf_dbdc_pins>;
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2021 MediaTek Inc.
 * Author: Sam.Shih <sam.shih@mediatek.com>
 */

#include "mt7986a.dtsi"
/ {
	compatible = "mediatek,mt7986b";
};

&pio {
	compatible = "mediatek,mt7986b-pinctrl";
	gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>;
};


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2020 MediaTek Inc.
 */
#ifndef __DTS_MT8167_PINFUNC_H
#define __DTS_MT8167_PINFUNC_H

#include <dt-bindings/pinctrl/mt65xx.h>

#define MT8167_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define MT8167_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1)
#define MT8167_PIN_0_EINT0__FUNC_DPI_CK (MTK_PIN_NO(0) | 2)
#define MT8167_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3)
#define MT8167_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4)
#define MT8167_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6)
#define MT8167_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7)

#define MT8167_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
#define MT8167_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1)
#define MT8167_PIN_1_EINT1__FUNC_DPI_D12 (MTK_PIN_NO(1) | 2)
#define MT8167_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3)
#define MT8167_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4)
#define MT8167_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5)
#define MT8167_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6)
#define MT8167_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7)

#define MT8167_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
#define MT8167_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1)
#define MT8167_PIN_2_EINT2__FUNC_DPI_D13 (MTK_PIN_NO(2) | 2)
#define MT8167_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3)
#define MT8167_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4)
#define MT8167_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5)
#define MT8167_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6)
#define MT8167_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7)

#define MT8167_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
#define MT8167_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1)
#define MT8167_PIN_3_EINT3__FUNC_DPI_D14 (MTK_PIN_NO(3) | 2)
#define MT8167_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3)
#define MT8167_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4)
#define MT8167_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5)
#define MT8167_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6)
#define MT8167_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7)

#define MT8167_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
#define MT8167_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1)
#define MT8167_PIN_4_EINT4__FUNC_DPI_D15 (MTK_PIN_NO(4) | 2)
#define MT8167_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3)
#define MT8167_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4)
#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5)
#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6)
#define MT8167_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7)

#define MT8167_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
#define MT8167_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1)
#define MT8167_PIN_5_EINT5__FUNC_DPI_D16 (MTK_PIN_NO(5) | 2)
#define MT8167_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3)
#define MT8167_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4)
#define MT8167_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5)
#define MT8167_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6)
#define MT8167_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7)

#define MT8167_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
#define MT8167_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1)
#define MT8167_PIN_6_EINT6__FUNC_DPI_D17 (MTK_PIN_NO(6) | 2)
#define MT8167_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3)
#define MT8167_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4)
#define MT8167_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5)
#define MT8167_PIN_6_EINT6__FUNC_MM_TEST_CK (MTK_PIN_NO(6) | 6)
#define MT8167_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7)

#define MT8167_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
#define MT8167_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1)
#define MT8167_PIN_7_EINT7__FUNC_DPI_D6 (MTK_PIN_NO(7) | 2)
#define MT8167_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3)
#define MT8167_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4)
#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5)
#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) | 6)
#define MT8167_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) | 7)

#define MT8167_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
#define MT8167_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) | 1)
#define MT8167_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) | 2)
#define MT8167_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) | 3)
#define MT8167_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4)
#define MT8167_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) | 5)
#define MT8167_PIN_8_EINT8__FUNC_DPI_D7 (MTK_PIN_NO(8) | 6)
#define MT8167_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) | 7)

#define MT8167_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
#define MT8167_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) | 1)
#define MT8167_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) | 2)
#define MT8167_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
#define MT8167_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4)
#define MT8167_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) | 5)
#define MT8167_PIN_9_EINT9__FUNC_DPI_D8 (MTK_PIN_NO(9) | 6)
#define MT8167_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) | 7)

#define MT8167_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
#define MT8167_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) | 1)
#define MT8167_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) | 2)
#define MT8167_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 3)
#define MT8167_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4)
#define MT8167_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) | 5)
#define MT8167_PIN_10_EINT10__FUNC_DPI_D9 (MTK_PIN_NO(10) | 6)
#define MT8167_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) | 7)

#define MT8167_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
#define MT8167_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) | 1)
#define MT8167_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) | 2)
#define MT8167_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) | 3)
#define MT8167_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) | 4)
#define MT8167_PIN_11_EINT11__FUNC_DPI_D10 (MTK_PIN_NO(11) | 5)
#define MT8167_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 6)
#define MT8167_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) | 7)

#define MT8167_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
#define MT8167_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) | 1)
#define MT8167_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) | 2)
#define MT8167_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) | 3)
#define MT8167_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) | 4)
#define MT8167_PIN_12_EINT12__FUNC_DPI_D11 (MTK_PIN_NO(12) | 5)
#define MT8167_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 6)
#define MT8167_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) | 7)

#define MT8167_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
#define MT8167_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) | 3)
#define MT8167_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) | 4)
#define MT8167_PIN_13_EINT13__FUNC_DPI_D0 (MTK_PIN_NO(13) | 5)
#define MT8167_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 6)
#define MT8167_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) | 7)

#define MT8167_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
#define MT8167_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) | 2)
#define MT8167_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) | 3)
#define MT8167_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 4)
#define MT8167_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) | 5)
#define MT8167_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) | 6)
#define MT8167_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) | 7)

#define MT8167_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
#define MT8167_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) | 2)
#define MT8167_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) | 3)
#define MT8167_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 4)
#define MT8167_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) | 5)
#define MT8167_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) | 6)
#define MT8167_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) | 7)

#define MT8167_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
#define MT8167_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) | 2)
#define MT8167_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) | 3)
#define MT8167_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 4)
#define MT8167_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) | 5)
#define MT8167_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) | 6)
#define MT8167_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) | 7)

#define MT8167_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
#define MT8167_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) | 2)
#define MT8167_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) | 3)
#define MT8167_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) | 4)
#define MT8167_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 5)
#define MT8167_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) | 6)
#define MT8167_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) | 7)

#define MT8167_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
#define MT8167_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 2)
#define MT8167_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) | 3)
#define MT8167_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) | 4)
#define MT8167_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) | 5)
#define MT8167_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) | 6)
#define MT8167_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) | 7)

#define MT8167_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
#define MT8167_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) | 1)
#define MT8167_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) | 2)
#define MT8167_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) | 3)
#define MT8167_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) | 4)
#define MT8167_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) | 5)
#define MT8167_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) | 6)
#define MT8167_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) | 7)

#define MT8167_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
#define MT8167_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) | 1)
#define MT8167_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 3)
#define MT8167_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) | 4)
#define MT8167_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) | 5)
#define MT8167_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) | 6)
#define MT8167_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) | 7)

#define MT8167_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
#define MT8167_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) | 1)
#define MT8167_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 2)
#define MT8167_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) | 3)
#define MT8167_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) | 7)

#define MT8167_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
#define MT8167_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) | 2)
#define MT8167_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) | 3)
#define MT8167_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) | 4)
#define MT8167_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) | 5)
#define MT8167_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) | 6)
#define MT8167_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) | 7)

#define MT8167_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
#define MT8167_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) | 2)
#define MT8167_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) | 3)
#define MT8167_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) | 4)
#define MT8167_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) | 5)
#define MT8167_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) | 6)
#define MT8167_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) | 7)

#define MT8167_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
#define MT8167_PIN_24_EINT24__FUNC_DPI_D20 (MTK_PIN_NO(24) | 1)
#define MT8167_PIN_24_EINT24__FUNC_DPI_DE (MTK_PIN_NO(24) | 2)
#define MT8167_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) | 3)
#define MT8167_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) | 4)
#define MT8167_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) | 5)
#define MT8167_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) | 6)
#define MT8167_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) | 7)

#define MT8167_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
#define MT8167_PIN_25_EINT25__FUNC_DPI_D19 (MTK_PIN_NO(25) | 1)
#define MT8167_PIN_25_EINT25__FUNC_DPI_VSYNC (MTK_PIN_NO(25) | 2)
#define MT8167_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 3)
#define MT8167_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) | 4)
#define MT8167_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) | 5)
#define MT8167_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) | 6)
#define MT8167_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) | 7)

#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) | 1)
#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) | 2)

#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) | 1)
#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) | 2)

#define MT8167_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) | 1)
#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) | 4)
#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) | 5)
#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) | 6)

#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) | 1)

#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) | 1)

#define MT8167_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
#define MT8167_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) | 1)

#define MT8167_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
#define MT8167_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) | 1)

#define MT8167_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
#define MT8167_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) | 1)

#define MT8167_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
#define MT8167_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) | 1)
#define MT8167_PIN_34_URXD2__FUNC_DPI_D5 (MTK_PIN_NO(34) | 2)
#define MT8167_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) | 3)
#define MT8167_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) | 4)
#define MT8167_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) | 6)
#define MT8167_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) | 7)

#define MT8167_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
#define MT8167_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) | 1)
#define MT8167_PIN_35_UTXD2__FUNC_DPI_HSYNC (MTK_PIN_NO(35) | 2)
#define MT8167_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) | 3)
#define MT8167_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) | 4)
#define MT8167_PIN_35_UTXD2__FUNC_DPI_D18 (MTK_PIN_NO(35) | 5)
#define MT8167_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) | 6)
#define MT8167_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) | 7)

#define MT8167_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
#define MT8167_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) | 1)
#define MT8167_PIN_36_MRG_CLK__FUNC_DPI_D4 (MTK_PIN_NO(36) | 2)
#define MT8167_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) | 3)
#define MT8167_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) | 4)
#define MT8167_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) | 5)
#define MT8167_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) | 6)
#define MT8167_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) | 7)

#define MT8167_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
#define MT8167_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) | 1)
#define MT8167_PIN_37_MRG_SYNC__FUNC_DPI_D3 (MTK_PIN_NO(37) | 2)
#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) | 3)
#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) | 4)
#define MT8167_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) | 5)
#define MT8167_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) | 6)
#define MT8167_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) | 7)

#define MT8167_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
#define MT8167_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) | 1)
#define MT8167_PIN_38_MRG_DI__FUNC_DPI_D1 (MTK_PIN_NO(38) | 2)
#define MT8167_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) | 3)
#define MT8167_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) | 4)
#define MT8167_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) | 5)
#define MT8167_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) | 6)
#define MT8167_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) | 7)

#define MT8167_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
#define MT8167_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) | 1)
#define MT8167_PIN_39_MRG_DO__FUNC_DPI_D2 (MTK_PIN_NO(39) | 2)
#define MT8167_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) | 3)
#define MT8167_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) | 4)
#define MT8167_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) | 5)
#define MT8167_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) | 6)
#define MT8167_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) | 7)

#define MT8167_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
#define MT8167_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) | 1)
#define MT8167_PIN_40_KPROW0__FUNC_IMG_TEST_CK (MTK_PIN_NO(40) | 4)
#define MT8167_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) | 7)

#define MT8167_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
#define MT8167_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) | 1)
#define MT8167_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) | 2)
#define MT8167_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 3)
#define MT8167_PIN_41_KPROW1__FUNC_MFG_TEST_CK (MTK_PIN_NO(41) | 4)
#define MT8167_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) | 7)

#define MT8167_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
#define MT8167_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) | 1)
#define MT8167_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) | 7)

#define MT8167_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
#define MT8167_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) | 1)
#define MT8167_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) | 2)
#define MT8167_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) | 3)
#define MT8167_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) | 4)
#define MT8167_PIN_43_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(43) | 5)
#define MT8167_PIN_43_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(43) | 6)
#define MT8167_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) | 7)

#define MT8167_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
#define MT8167_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) | 1)
#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) | 2)
#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) | 3)
#define MT8167_PIN_44_JTMS__FUNC_GPUDFD_TMS_XI (MTK_PIN_NO(44) | 4)
#define MT8167_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) | 5)
#define MT8167_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) | 6)

#define MT8167_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
#define MT8167_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) | 1)
#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) | 2)
#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) | 3)
#define MT8167_PIN_45_JTCK__FUNC_GPUDFD_TCK_XI (MTK_PIN_NO(45) | 4)
#define MT8167_PIN_45_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(45) | 5)
#define MT8167_PIN_45_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(45) | 6)

#define MT8167_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
#define MT8167_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) | 1)
#define MT8167_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) | 2)
#define MT8167_PIN_46_JTDI__FUNC_GPUDFD_TDI_XI (MTK_PIN_NO(46) | 4)
#define MT8167_PIN_46_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(46) | 5)
#define MT8167_PIN_46_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(46) | 6)

#define MT8167_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
#define MT8167_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) | 1)
#define MT8167_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) | 2)
#define MT8167_PIN_47_JTDO__FUNC_GPUDFD_TDO (MTK_PIN_NO(47) | 4)
#define MT8167_PIN_47_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(47) | 5)
#define MT8167_PIN_47_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(47) | 6)

#define MT8167_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
#define MT8167_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) | 1)
#define MT8167_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) | 3)
#define MT8167_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) | 4)
#define MT8167_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) | 7)

#define MT8167_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
#define MT8167_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) | 1)
#define MT8167_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) | 3)
#define MT8167_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) | 4)
#define MT8167_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) | 7)

#define MT8167_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) | 1)
#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) | 2)
#define MT8167_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) | 3)
#define MT8167_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 4)
#define MT8167_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) | 7)

#define MT8167_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) | 1)
#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) | 2)
#define MT8167_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) | 3)
#define MT8167_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) | 4)
#define MT8167_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) | 7)

#define MT8167_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
#define MT8167_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) | 1)

#define MT8167_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
#define MT8167_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) | 1)

#define MT8167_PIN_54_DISP_PWM__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
#define MT8167_PIN_54_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(54) | 1)
#define MT8167_PIN_54_DISP_PWM__FUNC_PWM_B (MTK_PIN_NO(54) | 2)
#define MT8167_PIN_54_DISP_PWM__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) | 7)

#define MT8167_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) | 1)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) | 2)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) | 3)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) | 4)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) | 5)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) | 6)
#define MT8167_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) | 7)

#define MT8167_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) | 1)
#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) | 3)
#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) | 4)
#define MT8167_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) | 5)
#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) | 6)
#define MT8167_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) | 7)

#define MT8167_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
#define MT8167_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) | 1)
#define MT8167_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) | 2)
#define MT8167_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 3)
#define MT8167_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) | 4)
#define MT8167_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) | 5)
#define MT8167_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) | 6)
#define MT8167_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) | 7)

#define MT8167_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
#define MT8167_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) | 1)

#define MT8167_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
#define MT8167_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) | 1)

#define MT8167_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
#define MT8167_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) | 1)
#define MT8167_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) | 2)

#define MT8167_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
#define MT8167_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) | 1)
#define MT8167_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) | 2)

#define MT8167_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
#define MT8167_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) | 1)
#define MT8167_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) | 2)

#define MT8167_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
#define MT8167_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) | 1)
#define MT8167_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) | 2)

#define MT8167_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
#define MT8167_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) | 1)
#define MT8167_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) | 2)
#define MT8167_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) | 7)

#define MT8167_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
#define MT8167_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) | 1)
#define MT8167_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) | 2)
#define MT8167_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) | 7)

#define MT8167_PIN_66_LCM_RST__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
#define MT8167_PIN_66_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(66) | 1)
#define MT8167_PIN_66_LCM_RST__FUNC_I2S0_MCK (MTK_PIN_NO(66) | 3)
#define MT8167_PIN_66_LCM_RST__FUNC_DBG_MON_B_3 (MTK_PIN_NO(66) | 7)

#define MT8167_PIN_67_DSI_TE__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
#define MT8167_PIN_67_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(67) | 1)
#define MT8167_PIN_67_DSI_TE__FUNC_I2S_8CH_MCK (MTK_PIN_NO(67) | 3)
#define MT8167_PIN_67_DSI_TE__FUNC_DBG_MON_B_14 (MTK_PIN_NO(67) | 7)

#define MT8167_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) | 1)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) | 2)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) | 3)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) | 5)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) | 6)
#define MT8167_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) | 7)

#define MT8167_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_DPI_D21 (MTK_PIN_NO(69) | 4)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6)
#define MT8167_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7)

#define MT8167_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) | 1)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) | 2)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DPI_D22 (MTK_PIN_NO(70) | 4)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) | 5)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) | 6)
#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) | 7)

#define MT8167_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) | 1)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) | 2)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) | 3)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 4)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) | 5)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) | 6)
#define MT8167_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) | 7)

#define MT8167_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) | 1)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) | 2)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) | 3)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(72) | 4)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) | 5)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) | 6)
#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7)

#define MT8167_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) | 1)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) | 2)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) | 3)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) | 4)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) | 5)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) | 6)
#define MT8167_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7)

#define MT8167_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) | 0)
#define MT8167_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) | 1)

#define MT8167_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) | 0)
#define MT8167_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) | 1)

#define MT8167_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) | 0)
#define MT8167_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) | 1)

#define MT8167_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) | 0)
#define MT8167_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) | 1)

#define MT8167_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) | 0)
#define MT8167_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) | 1)

#define MT8167_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) | 0)
#define MT8167_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) | 1)

#define MT8167_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) | 0)
#define MT8167_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) | 1)

#define MT8167_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) | 0)
#define MT8167_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) | 1)

#define MT8167_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) | 0)
#define MT8167_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) | 1)

#define MT8167_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) | 0)
#define MT8167_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) | 1)

#define MT8167_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) | 0)
#define MT8167_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) | 1)

#define MT8167_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) | 0)
#define MT8167_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) | 1)

#define MT8167_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) | 0)
#define MT8167_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) | 1)

#define MT8167_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) | 0)
#define MT8167_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) | 1)

#define MT8167_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) | 0)
#define MT8167_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) | 1)

#define MT8167_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) | 0)
#define MT8167_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) | 1)

#define MT8167_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) | 0)
#define MT8167_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) | 1)
#define MT8167_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) | 2)

#define MT8167_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
#define MT8167_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) | 1)
#define MT8167_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) | 2)

#define MT8167_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
#define MT8167_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) | 1)
#define MT8167_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) | 2)

#define MT8167_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
#define MT8167_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) | 1)
#define MT8167_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) | 2)

#define MT8167_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
#define MT8167_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) | 1)
#define MT8167_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) | 2)

#define MT8167_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
#define MT8167_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) | 1)
#define MT8167_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) | 2)

#define MT8167_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
#define MT8167_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) | 1)
#define MT8167_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) | 2)
#define MT8167_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) | 3)

#define MT8167_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
#define MT8167_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) | 1)
#define MT8167_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) | 2)
#define MT8167_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) | 3)

#define MT8167_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
#define MT8167_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) | 1)
#define MT8167_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) | 2)

#define MT8167_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
#define MT8167_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) | 1)
#define MT8167_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) | 2)

#define MT8167_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
#define MT8167_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) | 1)
#define MT8167_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) | 2)
#define MT8167_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) | 3)
#define MT8167_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) | 5)
#define MT8167_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) | 7)

#define MT8167_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
#define MT8167_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) | 1)
#define MT8167_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) | 2)
#define MT8167_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) | 3)
#define MT8167_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) | 4)
#define MT8167_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) | 5)
#define MT8167_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) | 7)

#define MT8167_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
#define MT8167_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) | 1)
#define MT8167_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) | 3)
#define MT8167_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) | 5)
#define MT8167_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) | 7)

#define MT8167_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
#define MT8167_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) | 1)
#define MT8167_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) | 2)
#define MT8167_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) | 3)
#define MT8167_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) | 5)
#define MT8167_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) | 7)

#define MT8167_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
#define MT8167_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) | 1)
#define MT8167_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) | 4)
#define MT8167_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) | 7)

#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) | 1)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_UDI_NTRST_XI (MTK_PIN_NO(105) | 2)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_DFD_NTRST_XI (MTK_PIN_NO(105) | 3)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) | 4)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPUEJ_NTRST_XI (MTK_PIN_NO(105) | 5)
#define MT8167_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) | 7)

#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) | 1)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_UDI_TMS_XI (MTK_PIN_NO(106) | 2)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DFD_TMS_XI (MTK_PIN_NO(106) | 3)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) | 4)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPUEJ_TMS_XI (MTK_PIN_NO(106) | 5)
#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) | 7)

#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) | 1)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_UDI_TCK_XI (MTK_PIN_NO(107) | 2)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DFD_TCK_XI (MTK_PIN_NO(107) | 3)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) | 4)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPUEJ_TCK_XI (MTK_PIN_NO(107) | 5)
#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) | 7)

#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) | 1)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_UDI_TDI_XI (MTK_PIN_NO(108) | 2)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DFD_TDI_XI (MTK_PIN_NO(108) | 3)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) | 4)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPUEJ_TDI_XI (MTK_PIN_NO(108) | 5)
#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) | 7)

#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) | 1)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_UDI_TDO (MTK_PIN_NO(109) | 2)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DFD_TDO (MTK_PIN_NO(109) | 3)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) | 4)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPUEJ_TDO (MTK_PIN_NO(109) | 5)
#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) | 7)

#define MT8167_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
#define MT8167_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) | 1)
#define MT8167_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) | 4)

#define MT8167_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
#define MT8167_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) | 1)
#define MT8167_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) | 4)

#define MT8167_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
#define MT8167_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) | 1)
#define MT8167_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) | 4)

#define MT8167_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
#define MT8167_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) | 1)
#define MT8167_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) | 4)

#define MT8167_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
#define MT8167_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) | 1)
#define MT8167_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) | 4)

#define MT8167_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
#define MT8167_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) | 1)
#define MT8167_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) | 4)

#define MT8167_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
#define MT8167_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) | 1)
#define MT8167_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) | 4)

#define MT8167_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
#define MT8167_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1)
#define MT8167_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) | 4)

#define MT8167_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
#define MT8167_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) | 1)
#define MT8167_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) | 4)

#define MT8167_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
#define MT8167_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) | 1)
#define MT8167_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) | 4)

#define MT8167_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
#define MT8167_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) | 1)
#define MT8167_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) | 4)
#define MT8167_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) | 5)

#define MT8167_PIN_121_CEC__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
#define MT8167_PIN_121_CEC__FUNC_CEC (MTK_PIN_NO(121) | 1)

#define MT8167_PIN_122_HTPLG__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
#define MT8167_PIN_122_HTPLG__FUNC_HTPLG (MTK_PIN_NO(122) | 1)

#define MT8167_PIN_123_HDMISCK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
#define MT8167_PIN_123_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(123) | 1)

#define MT8167_PIN_124_HDMISD__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define MT8167_PIN_124_HDMISD__FUNC_HDMISD (MTK_PIN_NO(124) | 1)

#endif /* __DTS_MT8167_PINFUNC_H */


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2020 BayLibre, SAS.
 * Author: Fabien Parent <fparent@baylibre.com>
 */

/dts-v1/;

#include "mt8167.dtsi"
#include "pumpkin-common.dtsi"

/ {
	model = "Pumpkin MT8167";
	compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167";

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x80000000>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2020 MediaTek Inc.
 * Copyright (c) 2020 BayLibre, SAS.
 * Author: Fabien Parent <fparent@baylibre.com>
 */

#include <dt-bindings/clock/mt8167-clk.h>
#include <dt-bindings/memory/mt8167-larb-port.h>
#include <dt-bindings/power/mt8167-power.h>

#include "mt8167-pinfunc.h"

#include "mt8516.dtsi"

/ {
	compatible = "mediatek,mt8167";

	soc {
		topckgen: topckgen@10000000 {
			compatible = "mediatek,mt8167-topckgen", "syscon";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg: infracfg@10001000 {
			compatible = "mediatek,mt8167-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
		};

		apmixedsys: apmixedsys@10018000 {
			compatible = "mediatek,mt8167-apmixedsys", "syscon";
			reg = <0 0x10018000 0 0x710>;
			#clock-cells = <1>;
		};

		scpsys: syscon@10006000 {
			compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd";
			reg = <0 0x10006000 0 0x1000>;

			spm: power-controller {
				compatible = "mediatek,mt8167-power-controller";
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <1>;

				/* power domains of the SoC */
				power-domain@MT8167_POWER_DOMAIN_MM {
					reg = <MT8167_POWER_DOMAIN_MM>;
					clocks = <&topckgen CLK_TOP_SMI_MM>;
					clock-names = "mm";
					#power-domain-cells = <0>;
					mediatek,infracfg = <&infracfg>;
				};

				power-domain@MT8167_POWER_DOMAIN_VDEC {
					reg = <MT8167_POWER_DOMAIN_VDEC>;
					clocks = <&topckgen CLK_TOP_SMI_MM>,
						 <&topckgen CLK_TOP_RG_VDEC>;
					clock-names = "mm", "vdec";
					#power-domain-cells = <0>;
				};

				power-domain@MT8167_POWER_DOMAIN_ISP {
					reg = <MT8167_POWER_DOMAIN_ISP>;
					clocks = <&topckgen CLK_TOP_SMI_MM>;
					clock-names = "mm";
					#power-domain-cells = <0>;
				};

				power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
					reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;
					clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
						 <&topckgen CLK_TOP_RG_SLOW_MFG>;
					clock-names = "axi_mfg", "mfg";
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <1>;
					mediatek,infracfg = <&infracfg>;

					power-domain@MT8167_POWER_DOMAIN_MFG_2D {
						reg = <MT8167_POWER_DOMAIN_MFG_2D>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <1>;

						power-domain@MT8167_POWER_DOMAIN_MFG {
							reg = <MT8167_POWER_DOMAIN_MFG>;
							#power-domain-cells = <0>;
							mediatek,infracfg = <&infracfg>;
						};
					};
				};

				power-domain@MT8167_POWER_DOMAIN_CONN {
					reg = <MT8167_POWER_DOMAIN_CONN>;
					#power-domain-cells = <0>;
					mediatek,infracfg = <&infracfg>;
				};
			};
		};

		imgsys: syscon@15000000 {
			compatible = "mediatek,mt8167-imgsys", "syscon";
			reg = <0 0x15000000 0 0x1000>;
			#clock-cells = <1>;
		};

		vdecsys: syscon@16000000 {
			compatible = "mediatek,mt8167-vdecsys", "syscon";
			reg = <0 0x16000000 0 0x1000>;
			#clock-cells = <1>;
		};

		pio: pinctrl@1000b000 {
			compatible = "mediatek,mt8167-pinctrl";
			reg = <0 0x1000b000 0 0x1000>;
			mediatek,pctl-regmap = <&syscfg_pctl>;
			pins-are-numbered;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
		};

		mmsys: mmsys@14000000 {
			compatible = "mediatek,mt8167-mmsys", "syscon";
			reg = <0 0x14000000 0 0x1000>;
			#clock-cells = <1>;
		};

		smi_common: smi@14017000 {
			compatible = "mediatek,mt8167-smi-common";
			reg = <0 0x14017000 0 0x1000>;
			clocks = <&mmsys CLK_MM_SMI_COMMON>,
				 <&mmsys CLK_MM_SMI_COMMON>;
			clock-names = "apb", "smi";
			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
		};

		larb0: larb@14016000 {
			compatible = "mediatek,mt8167-smi-larb";
			reg = <0 0x14016000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&mmsys CLK_MM_SMI_LARB0>,
				 <&mmsys CLK_MM_SMI_LARB0>;
			clock-names = "apb", "smi";
			power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
		};

		larb1: larb@15001000 {
			compatible = "mediatek,mt8167-smi-larb";
			reg = <0 0x15001000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&imgsys CLK_IMG_LARB1_SMI>,
				 <&imgsys CLK_IMG_LARB1_SMI>;
			clock-names = "apb", "smi";
			power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
		};

		larb2: larb@16010000 {
			compatible = "mediatek,mt8167-smi-larb";
			reg = <0 0x16010000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&vdecsys CLK_VDEC_CKEN>,
				 <&vdecsys CLK_VDEC_LARB1_CKEN>;
			clock-names = "apb", "smi";
			power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
		};

		iommu: m4u@10203000 {
			compatible = "mediatek,mt8167-m4u";
			reg = <0 0x10203000 0 0x1000>;
			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
			#iommu-cells = <1>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2019 MediaTek Inc.
 */

/dts-v1/;
#include "mt8173-elm-hana.dtsi"

/ {
	model = "Google Hanawl";
	compatible = "google,hana-rev7", "mediatek,mt8173";
};

&cpu_thermal {
	trips {
		cpu_crit: cpu_crit0 {
			temperature = <100000>;
			type = "critical";
		};
	};
};

&gpio_keys {
	/delete-node/switch-tablet-mode;
	/delete-node/switch-volume-down;
	/delete-node/switch-volume-up;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2016 MediaTek Inc.
 */

/dts-v1/;
#include "mt8173-elm-hana.dtsi"

/ {
	model = "Google Hana";
	compatible = "google,hana-rev6", "google,hana-rev5",
		     "google,hana-rev4", "google,hana-rev3",
		     "google,hana", "mediatek,mt8173";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2016 MediaTek Inc.
 */

#include "mt8173-elm.dtsi"

&i2c0 {
	clock-frequency = <200000>;
};

&i2c3 {
	touchscreen2: touchscreen@34 {
		compatible = "melfas,mip4_ts";
		reg = <0x34>;
		interrupt-parent = <&pio>;
		interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
	};

	/*
	 * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd
	 * Gen (MTK) are using synaptics touchscreen (hid-over-i2c driver) as a
	 * second source touchscreen.
	 */
	touchscreen3: touchscreen@20 {
		compatible = "hid-over-i2c";
		reg = <0x20>;
		hid-descr-addr = <0x0020>;
		interrupt-parent = <&pio>;
		interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
	};
};

&i2c4 {
	/*
	 * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd
	 * Gen (MTK) are using synaptics trackpad (hid-over-i2c driver) as a
	 * second source trackpad.
	 */
	trackpad2: trackpad@2c {
		compatible = "hid-over-i2c";
		interrupt-parent = <&pio>;
		interrupts = <117 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x2c>;
		hid-descr-addr = <0x0020>;
		wakeup-source;
	};
};

&mmc1 {
	wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
};

&pio {
	hdmi_mux_pins: hdmi_mux_pins {
		pins2 {
			pinmux = <MT8173_PIN_98_URTS1__FUNC_GPIO98>;
			bias-pull-up;
			output-high;
		};
	};

	mmc1_pins_default: mmc1default {
		pins_wp {
			pinmux = <MT8173_PIN_42_DSI_TE__FUNC_GPIO42>;
			input-enable;
			bias-pull-up;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2016 MediaTek Inc.
 */

/dts-v1/;
#include "mt8173-elm.dtsi"

/ {
	model = "Google Elm";
	compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6",
		     "google,elm-rev5", "google,elm-rev4", "google,elm-rev3",
		     "google,elm", "mediatek,mt8173";
};