code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Based on "omap4.dtsi"
 */

#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/dra7.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/dra.h>
#include <dt-bindings/clock/dra7.h>

#define MAX_SOURCES 400

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	compatible = "ti,dra7xx";
	interrupt-parent = <&crossbar_mpu>;
	chosen { };

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		i2c4 = &i2c5;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		serial6 = &uart7;
		serial7 = &uart8;
		serial8 = &uart9;
		serial9 = &uart10;
		ethernet0 = &cpsw_port1;
		ethernet1 = &cpsw_port2;
		d_can0 = &dcan1;
		d_can1 = &dcan2;
		spi0 = &qspi;
	};

	timer {
		compatible = "arm,armv7-timer";
		status = "disabled";	/* See ARM architected timer wrap erratum i940 */
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&gic>;
	};

	gic: interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x0 0x48211000 0x0 0x1000>,
		      <0x0 0x48212000 0x0 0x2000>,
		      <0x0 0x48214000 0x0 0x2000>,
		      <0x0 0x48216000 0x0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-parent = <&gic>;
	};

	wakeupgen: interrupt-controller@48281000 {
		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x0 0x48281000 0x0 0x1000>;
		interrupt-parent = <&gic>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;

			operating-points-v2 = <&cpu0_opp_table>;

			clocks = <&dpll_mpu_ck>;
			clock-names = "cpu";

			clock-latency = <300000>; /* From omap-cpufreq driver */

			/* cooling options */
			#cooling-cells = <2>; /* min followed by max */

			vbb-supply = <&abb_mpu>;
		};
	};

	cpu0_opp_table: opp-table {
		compatible = "operating-points-v2-ti-cpu";
		syscon = <&scm_wkup>;

		opp_nom-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <1060000 850000 1150000>,
					<1060000 850000 1150000>;
			opp-supported-hw = <0xFF 0x01>;
			opp-suspend;
		};

		opp_od-1176000000 {
			opp-hz = /bits/ 64 <1176000000>;
			opp-microvolt = <1160000 885000 1160000>,
					<1160000 885000 1160000>;

			opp-supported-hw = <0xFF 0x02>;
		};

		opp_high@1500000000 {
			opp-hz = /bits/ 64 <1500000000>;
			opp-microvolt = <1210000 950000 1250000>,
					<1210000 950000 1250000>;
			opp-supported-hw = <0xFF 0x04>;
		};
	};

	/*
	 * XXX: Use a flat representation of the SOC interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since it will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp: ocp {
		compatible = "simple-pm-bus";
		power-domains = <&prm_core>;
		clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>,
			 <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0xc0000000>;
		dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;

		l3-noc@44000000 {
			compatible = "ti,dra7-l3-noc";
			reg = <0x44000000 0x1000>,
			      <0x45000000 0x1000>;
			interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
					      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		};

		l4_cfg: interconnect@4a000000 {
		};
		l4_wkup: interconnect@4ae00000 {
		};
		l4_per1: interconnect@48000000 {
		};

		target-module@48210000 {
			compatible = "ti,sysc-omap4-simple", "ti,sysc";
			power-domains = <&prm_mpu>;
			clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x48210000 0x1f0000>;

			mpu {
				compatible = "ti,omap5-mpu";
			};
		};

		l4_per2: interconnect@48400000 {
		};
		l4_per3: interconnect@48800000 {
		};

		/*
		 * Register access seems to have complex dependencies and also
		 * seems to need an enabled phy. See the TRM chapter for "Table
		 * 26-678. Main Sequence PCIe Controller Global Initialization"
		 * and also dra7xx_pcie_probe().
		 */
		axi0: target-module@51000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			power-domains = <&prm_l3init>;
			resets = <&prm_l3init 0>;
			reset-names = "rstctrl";
			clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,
				 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
				 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>;
			clock-names = "fck", "phy-clk", "phy-clk-div";
			#size-cells = <1>;
			#address-cells = <1>;
			ranges = <0x51000000 0x51000000 0x3000>,
				 <0x20000000 0x20000000 0x10000000>;
			dma-ranges;
			/**
			 * To enable PCI endpoint mode, disable the pcie1_rc
			 * node and enable pcie1_ep mode.
			 */
			pcie1_rc: pcie@51000000 {
				reg = <0x51000000 0x2000>,
				      <0x51002000 0x14c>,
				      <0x20001000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0 232 0x4>, <0 233 0x4>;
				#address-cells = <3>;
				#size-cells = <2>;
				device_type = "pci";
				ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>,
					 <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>;
				bus-range = <0x00 0xff>;
				#interrupt-cells = <1>;
				num-lanes = <1>;
				linux,pci-domain = <0>;
				phys = <&pcie1_phy>;
				phy-names = "pcie-phy0";
				ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie1_intc 1>,
						<0 0 0 2 &pcie1_intc 2>,
						<0 0 0 3 &pcie1_intc 3>,
						<0 0 0 4 &pcie1_intc 4>;
				ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
				status = "disabled";
				pcie1_intc: interrupt-controller {
					interrupt-controller;
					#address-cells = <0>;
					#interrupt-cells = <1>;
				};
			};

			pcie1_ep: pcie_ep@51000000 {
				reg = <0x51000000 0x28>,
				      <0x51002000 0x14c>,
				      <0x51001000 0x28>,
				      <0x20001000 0x10000000>;
				reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
				interrupts = <0 232 0x4>;
				num-lanes = <1>;
				num-ib-windows = <4>;
				num-ob-windows = <16>;
				phys = <&pcie1_phy>;
				phy-names = "pcie-phy0";
				ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
				ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
				status = "disabled";
			};
		};

		/*
		 * Register access seems to have complex dependencies and also
		 * seems to need an enabled phy. See the TRM chapter for "Table
		 * 26-678. Main Sequence PCIe Controller Global Initialization"
		 * and also dra7xx_pcie_probe().
		 */
		axi1: target-module@51800000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,
				 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
				 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>;
			clock-names = "fck", "phy-clk", "phy-clk-div";
			power-domains = <&prm_l3init>;
			resets = <&prm_l3init 1>;
			reset-names = "rstctrl";
			#size-cells = <1>;
			#address-cells = <1>;
			ranges = <0x51800000 0x51800000 0x3000>,
				 <0x30000000 0x30000000 0x10000000>;
			dma-ranges;
			status = "disabled";
			pcie2_rc: pcie@51800000 {
				reg = <0x51800000 0x2000>,
				      <0x51802000 0x14c>,
				      <0x30001000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0 355 0x4>, <0 356 0x4>;
				#address-cells = <3>;
				#size-cells = <2>;
				device_type = "pci";
				ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
					 <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
				bus-range = <0x00 0xff>;
				#interrupt-cells = <1>;
				num-lanes = <1>;
				linux,pci-domain = <1>;
				phys = <&pcie2_phy>;
				phy-names = "pcie-phy0";
				interrupt-map-mask = <0 0 0 7>;
				interrupt-map = <0 0 0 1 &pcie2_intc 1>,
						<0 0 0 2 &pcie2_intc 2>,
						<0 0 0 3 &pcie2_intc 3>,
						<0 0 0 4 &pcie2_intc 4>;
				ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
				pcie2_intc: interrupt-controller {
					interrupt-controller;
					#address-cells = <0>;
					#interrupt-cells = <1>;
				};
			};
		};

		ocmcram1: ocmcram@40300000 {
			compatible = "mmio-sram";
			reg = <0x40300000 0x80000>;
			ranges = <0x0 0x40300000 0x80000>;
			#address-cells = <1>;
			#size-cells = <1>;
			/*
			 * This is a placeholder for an optional reserved
			 * region for use by secure software. The size
			 * of this region is not known until runtime so it
			 * is set as zero to either be updated to reserve
			 * space or left unchanged to leave all SRAM for use.
			 * On HS parts that that require the reserved region
			 * either the bootloader can update the size to
			 * the required amount or the node can be overridden
			 * from the board dts file for the secure platform.
			 */
			sram-hs@0 {
				compatible = "ti,secure-ram";
				reg = <0x0 0x0>;
			};
		};

		/*
		 * NOTE: ocmcram2 and ocmcram3 are not available on all
		 * DRA7xx and AM57xx variants. Confirm availability in
		 * the data manual for the exact part number in use
		 * before enabling these nodes in the board dts file.
		 */
		ocmcram2: ocmcram@40400000 {
			status = "disabled";
			compatible = "mmio-sram";
			reg = <0x40400000 0x100000>;
			ranges = <0x0 0x40400000 0x100000>;
			#address-cells = <1>;
			#size-cells = <1>;
		};

		ocmcram3: ocmcram@40500000 {
			status = "disabled";
			compatible = "mmio-sram";
			reg = <0x40500000 0x100000>;
			ranges = <0x0 0x40500000 0x100000>;
			#address-cells = <1>;
			#size-cells = <1>;
		};

		bandgap: bandgap@4a0021e0 {
			reg = <0x4a0021e0 0xc
				0x4a00232c 0xc
				0x4a002380 0x2c
				0x4a0023C0 0x3c
				0x4a002564 0x8
				0x4a002574 0x50>;
				compatible = "ti,dra752-bandgap";
				interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
				#thermal-sensor-cells = <1>;
		};

		dsp1_system: dsp_system@40d00000 {
			compatible = "syscon";
			reg = <0x40d00000 0x100>;
		};

		dra7_iodelay_core: padconf@4844a000 {
			compatible = "ti,dra7-iodelay";
			reg = <0x4844a000 0x0d1c>;
			#address-cells = <1>;
			#size-cells = <0>;
			#pinctrl-cells = <2>;
		};

		target-module@43300000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x43300000 0x4>,
			      <0x43300010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x43300000 0x100000>;

			edma: dma@0 {
				compatible = "ti,edma3-tpcc";
				reg = <0 0x100000>;
				reg-names = "edma3_cc";
				interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "edma3_ccint", "edma3_mperr",
						  "edma3_ccerrint";
				dma-requests = <64>;
				#dma-cells = <2>;

				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;

				/*
				* memcpy is disabled, can be enabled with:
				* ti,edma-memcpy-channels = <20 21>;
				* for example. Note that these channels need to be
				* masked in the xbar as well.
				*/
			};
		};

		target-module@43400000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x43400000 0x4>,
			      <0x43400010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x43400000 0x100000>;

			edma_tptc0: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@43500000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x43500000 0x4>,
			      <0x43500010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x43500000 0x100000>;

			edma_tptc1: dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0 0x100000>;
				interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "edma3_tcerrint";
			};
		};

		target-module@4e000000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x4e000000 0x4>,
			      <0x4e000010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ranges = <0x0 0x4e000000 0x2000000>;
			#size-cells = <1>;
			#address-cells = <1>;

			dmm@0 {
				compatible = "ti,omap5-dmm";
				reg = <0 0x800>;
				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		ipu1: ipu@58820000 {
			compatible = "ti,dra7-ipu";
			reg = <0x58820000 0x10000>;
			reg-names = "l2ram";
			iommus = <&mmu_ipu1>;
			status = "disabled";
			resets = <&prm_ipu 0>, <&prm_ipu 1>;
			clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
			firmware-name = "dra7-ipu1-fw.xem4";
		};

		ipu2: ipu@55020000 {
			compatible = "ti,dra7-ipu";
			reg = <0x55020000 0x10000>;
			reg-names = "l2ram";
			iommus = <&mmu_ipu2>;
			status = "disabled";
			resets = <&prm_core 0>, <&prm_core 1>;
			clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
			firmware-name = "dra7-ipu2-fw.xem4";
		};

		dsp1: dsp@40800000 {
			compatible = "ti,dra7-dsp";
			reg = <0x40800000 0x48000>,
			      <0x40e00000 0x8000>,
			      <0x40f00000 0x8000>;
			reg-names = "l2ram", "l1pram", "l1dram";
			ti,bootreg = <&scm_conf 0x55c 10>;
			iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
			status = "disabled";
			resets = <&prm_dsp1 0>;
			clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
			firmware-name = "dra7-dsp1-fw.xe66";
		};

		target-module@40d01000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x40d01000 0x4>,
			      <0x40d01010 0x4>,
			      <0x40d01014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
			clock-names = "fck";
			resets = <&prm_dsp1 1>;
			reset-names = "rstctrl";
			ranges = <0x0 0x40d01000 0x1000>;
			#size-cells = <1>;
			#address-cells = <1>;

			mmu0_dsp1: mmu@0 {
				compatible = "ti,dra7-dsp-iommu";
				reg = <0x0 0x100>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				#iommu-cells = <0>;
				ti,syscon-mmuconfig = <&dsp1_system 0x0>;
			};
		};

		target-module@40d02000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x40d02000 0x4>,
			      <0x40d02010 0x4>,
			      <0x40d02014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
			clock-names = "fck";
			resets = <&prm_dsp1 1>;
			reset-names = "rstctrl";
			ranges = <0x0 0x40d02000 0x1000>;
			#size-cells = <1>;
			#address-cells = <1>;

			mmu1_dsp1: mmu@0 {
				compatible = "ti,dra7-dsp-iommu";
				reg = <0x0 0x100>;
				interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
				#iommu-cells = <0>;
				ti,syscon-mmuconfig = <&dsp1_system 0x1>;
			};
		};

		target-module@58882000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x58882000 0x4>,
			      <0x58882010 0x4>,
			      <0x58882014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
			clock-names = "fck";
			resets = <&prm_ipu 2>;
			reset-names = "rstctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x58882000 0x100>;

			mmu_ipu1: mmu@0 {
				compatible = "ti,dra7-iommu";
				reg = <0x0 0x100>;
				interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
				#iommu-cells = <0>;
				ti,iommu-bus-err-back;
			};
		};

		target-module@55082000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x55082000 0x4>,
			      <0x55082010 0x4>,
			      <0x55082014 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
					 SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
			clock-names = "fck";
			resets = <&prm_core 2>;
			reset-names = "rstctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x55082000 0x100>;

			mmu_ipu2: mmu@0 {
				compatible = "ti,dra7-iommu";
				reg = <0x0 0x100>;
				interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
				#iommu-cells = <0>;
				ti,iommu-bus-err-back;
			};
		};

		abb_mpu: regulator-abb-mpu {
			compatible = "ti,abb-v3";
			regulator-name = "abb_mpu";
			#address-cells = <0>;
			#size-cells = <0>;
			clocks = <&sys_clkin1>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
			      <0x4ae06014 0x4>, <0x4a003b20 0xc>,
			      <0x4ae0c158 0x4>;
			reg-names = "setup-address", "control-address",
				    "int-address", "efuse-address",
				    "ldo-address";
			ti,tranxdone-status-mask = <0x80>;
			/* LDOVBBMPU_FBB_MUX_CTRL */
			ti,ldovbb-override-mask = <0x400>;
			/* LDOVBBMPU_FBB_VSET_OUT */
			ti,ldovbb-vset-mask = <0x1F>;

			/*
			 * NOTE: only FBB mode used but actual vset will
			 * determine final biasing
			 */
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
			1060000		0	0x0	0 0x02000000 0x01F00000
			1160000		0	0x4	0 0x02000000 0x01F00000
			1210000		0	0x8	0 0x02000000 0x01F00000
			>;
		};

		abb_ivahd: regulator-abb-ivahd {
			compatible = "ti,abb-v3";
			regulator-name = "abb_ivahd";
			#address-cells = <0>;
			#size-cells = <0>;
			clocks = <&sys_clkin1>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
			      <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
			      <0x4a002470 0x4>;
			reg-names = "setup-address", "control-address",
				    "int-address", "efuse-address",
				    "ldo-address";
			ti,tranxdone-status-mask = <0x40000000>;
			/* LDOVBBIVA_FBB_MUX_CTRL */
			ti,ldovbb-override-mask = <0x400>;
			/* LDOVBBIVA_FBB_VSET_OUT */
			ti,ldovbb-vset-mask = <0x1F>;

			/*
			 * NOTE: only FBB mode used but actual vset will
			 * determine final biasing
			 */
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
			1055000		0	0x0	0 0x02000000 0x01F00000
			1150000		0	0x4	0 0x02000000 0x01F00000
			1250000		0	0x8	0 0x02000000 0x01F00000
			>;
		};

		abb_dspeve: regulator-abb-dspeve {
			compatible = "ti,abb-v3";
			regulator-name = "abb_dspeve";
			#address-cells = <0>;
			#size-cells = <0>;
			clocks = <&sys_clkin1>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
			      <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
			      <0x4a00246c 0x4>;
			reg-names = "setup-address", "control-address",
				    "int-address", "efuse-address",
				    "ldo-address";
			ti,tranxdone-status-mask = <0x20000000>;
			/* LDOVBBDSPEVE_FBB_MUX_CTRL */
			ti,ldovbb-override-mask = <0x400>;
			/* LDOVBBDSPEVE_FBB_VSET_OUT */
			ti,ldovbb-vset-mask = <0x1F>;

			/*
			 * NOTE: only FBB mode used but actual vset will
			 * determine final biasing
			 */
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
			1055000		0	0x0	0 0x02000000 0x01F00000
			1150000		0	0x4	0 0x02000000 0x01F00000
			1250000		0	0x8	0 0x02000000 0x01F00000
			>;
		};

		abb_gpu: regulator-abb-gpu {
			compatible = "ti,abb-v3";
			regulator-name = "abb_gpu";
			#address-cells = <0>;
			#size-cells = <0>;
			clocks = <&sys_clkin1>;
			ti,settling-time = <50>;
			ti,clock-cycles = <16>;

			reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
			      <0x4ae06010 0x4>, <0x4a003b08 0xc>,
			      <0x4ae0c154 0x4>;
			reg-names = "setup-address", "control-address",
				    "int-address", "efuse-address",
				    "ldo-address";
			ti,tranxdone-status-mask = <0x10000000>;
			/* LDOVBBGPU_FBB_MUX_CTRL */
			ti,ldovbb-override-mask = <0x400>;
			/* LDOVBBGPU_FBB_VSET_OUT */
			ti,ldovbb-vset-mask = <0x1F>;

			/*
			 * NOTE: only FBB mode used but actual vset will
			 * determine final biasing
			 */
			ti,abb_info = <
			/*uV		ABB	efuse	rbb_m fbb_m	vset_m*/
			1090000		0	0x0	0 0x02000000 0x01F00000
			1210000		0	0x4	0 0x02000000 0x01F00000
			1280000		0	0x8	0 0x02000000 0x01F00000
			>;
		};

		target-module@4b300000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x4b300000 0x4>,
			      <0x4b300010 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4b300000 0x1000>,
				 <0x5c000000 0x5c000000 0x4000000>;

			qspi: spi@0 {
				compatible = "ti,dra7xxx-qspi";
				reg = <0 0x100>,
				      <0x5c000000 0x4000000>;
				reg-names = "qspi_base", "qspi_mmap";
				syscon-chipselects = <&scm_conf 0x558>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
				clock-names = "fck";
				num-cs = <4>;
				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};
		};

		/* OCP2SCP1 */
		/* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */

		target-module@50000000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x50000000 4>,
			      <0x50000010 4>,
			      <0x50000014 4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
				 <0x00000000 0x00000000 0x40000000>; /* data */

			gpmc: gpmc@50000000 {
				compatible = "ti,am3352-gpmc";
				reg = <0x50000000 0x37c>;      /* device IO registers */
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&edma_xbar 4 0>;
				dma-names = "rxtx";
				gpmc,num-cs = <8>;
				gpmc,num-waitpins = <2>;
				#address-cells = <2>;
				#size-cells = <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-controller;
				#gpio-cells = <2>;
				status = "disabled";
			};
		};

		target-module@56000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x5600fe00 0x4>,
			      <0x5600fe10 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x56000000 0x2000000>;
		};

		crossbar_mpu: crossbar@4a002a48 {
			compatible = "ti,irq-crossbar";
			reg = <0x4a002a48 0x130>;
			interrupt-controller;
			interrupt-parent = <&wakeupgen>;
			#interrupt-cells = <3>;
			ti,max-irqs = <160>;
			ti,max-crossbar-sources = <MAX_SOURCES>;
			ti,reg-size = <2>;
			ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
			ti,irqs-skip = <10 133 139 140>;
			ti,irqs-safe-map = <0>;
		};

		target-module@58000000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x58000000 4>,
			      <0x58000014 4>;
			reg-names = "rev", "syss";
			ti,syss-mask = <1>;
			clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>,
				 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
				 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>,
				 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>;
			clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x58000000 0x800000>;

			dss: dss@0 {
				compatible = "ti,dra7-dss";
				/* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
				/* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
				status = "disabled";
				/* CTRL_CORE_DSS_PLL_CONTROL */
				syscon-pll-ctrl = <&scm_conf 0x538>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0 0x800000>;

				target-module@1000 {
					compatible = "ti,sysc-omap2", "ti,sysc";
					reg = <0x1000 0x4>,
					      <0x1010 0x4>,
					      <0x1014 0x4>;
					reg-names = "rev", "sysc", "syss";
					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
							<SYSC_IDLE_NO>,
							<SYSC_IDLE_SMART>;
					ti,sysc-midle = <SYSC_IDLE_FORCE>,
							<SYSC_IDLE_NO>,
							<SYSC_IDLE_SMART>;
					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
							 SYSC_OMAP2_ENAWAKEUP |
							 SYSC_OMAP2_SOFTRESET |
							 SYSC_OMAP2_AUTOIDLE)>;
					ti,syss-mask = <1>;
					clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
					clock-names = "fck";
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0 0x1000 0x1000>;

					dispc@0 {
						compatible = "ti,dra7-dispc";
						reg = <0 0x1000>;
						interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
						clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
						clock-names = "fck";
						/* CTRL_CORE_SMA_SW_1 */
						syscon-pol = <&scm_conf 0x534>;
					};
				};

				target-module@40000 {
					compatible = "ti,sysc-omap4", "ti,sysc";
					reg = <0x40000 0x4>,
					      <0x40010 0x4>;
					reg-names = "rev", "sysc";
					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
							<SYSC_IDLE_NO>,
							<SYSC_IDLE_SMART>,
							<SYSC_IDLE_SMART_WKUP>;
					ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
					clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
						 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
					clock-names = "fck", "dss_clk";
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0 0x40000 0x40000>;

					hdmi: encoder@0 {
						compatible = "ti,dra7-hdmi";
						reg = <0 0x200>,
						      <0x200 0x80>,
						      <0x300 0x80>,
						      <0x20000 0x19000>;
						reg-names = "wp", "pll", "phy", "core";
						interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
						status = "disabled";
						clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
							 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
						clock-names = "fck", "sys_clk";
						dmas = <&sdma_xbar 76>;
						dma-names = "audio_tx";
					};
				};
			};
		};

		target-module@59000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x59000020 0x4>;
			reg-names = "rev";
			clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x59000000 0x1000>;

			bb2d: gpu@0 {
				compatible = "vivante,gc";
				reg = <0x0 0x700>;
				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
				clock-names = "core";
			};
		};

		aes1_target: target-module@4b500000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x4b500080 0x4>,
			      <0x4b500084 0x4>,
			      <0x4b500088 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4sec_clkdm */
			clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4b500000 0x1000>;

			aes1: aes@0 {
				compatible = "ti,omap4-aes";
				reg = <0 0xa0>;
				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
				dma-names = "tx", "rx";
				clocks = <&l3_iclk_div>;
				clock-names = "fck";
			};
		};

		aes2_target: target-module@4b700000 {
			compatible = "ti,sysc-omap2", "ti,sysc";
			reg = <0x4b700080 0x4>,
			      <0x4b700084 0x4>,
			      <0x4b700088 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>,
					<SYSC_IDLE_SMART_WKUP>;
			ti,syss-mask = <1>;
			/* Domains (P, C): per_pwrdm, l4sec_clkdm */
			clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4b700000 0x1000>;

			aes2: aes@0 {
				compatible = "ti,omap4-aes";
				reg = <0 0xa0>;
				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
				dma-names = "tx", "rx";
				clocks = <&l3_iclk_div>;
				clock-names = "fck";
			};
		};

		sham1_target: target-module@4b101000 {
			compatible = "ti,sysc-omap3-sham", "ti,sysc";
			reg = <0x4b101100 0x4>,
			      <0x4b101110 0x4>,
			      <0x4b101114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
			clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x4b101000 0x1000>;

			sham1: sham@0 {
				compatible = "ti,omap5-sham";
				reg = <0 0x300>;
				interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&edma_xbar 119 0>;
				dma-names = "rx";
				clocks = <&l3_iclk_div>;
				clock-names = "fck";
			};
		};

		sham2_target: target-module@42701000 {
			compatible = "ti,sysc-omap3-sham", "ti,sysc";
			reg = <0x42701100 0x4>,
			      <0x42701110 0x4>,
			      <0x42701114 0x4>;
			reg-names = "rev", "sysc", "syss";
			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
					 SYSC_OMAP2_AUTOIDLE)>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,syss-mask = <1>;
			/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
			clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x42701000 0x1000>;

			sham2: sham@0 {
				compatible = "ti,omap5-sham";
				reg = <0 0x300>;
				interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&edma_xbar 165 0>;
				dma-names = "rx";
				clocks = <&l3_iclk_div>;
				clock-names = "fck";
			};
		};

		iva_hd_target: target-module@5a000000 {
			compatible = "ti,sysc-omap4", "ti,sysc";
			reg = <0x5a05a400 0x4>,
			      <0x5a05a410 0x4>;
			reg-names = "rev", "sysc";
			ti,sysc-midle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
					<SYSC_IDLE_NO>,
					<SYSC_IDLE_SMART>;
			power-domains = <&prm_iva>;
			resets = <&prm_iva 2>;
			reset-names = "rstctrl";
			clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>;
			clock-names = "fck";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x5a000000 0x5a000000 0x1000000>,
				 <0x5b000000 0x5b000000 0x1000000>;

			iva {
				compatible = "ti,ivahd";
			};
		};

		opp_supply_mpu: opp-supply@4a003b20 {
			compatible = "ti,omap5-opp-supply";
			reg = <0x4a003b20 0xc>;
			ti,efuse-settings = <
			/* uV   offset */
			1060000 0x0
			1160000 0x4
			1210000 0x8
			>;
			ti,absolute-max-voltage-uv = <1500000>;
		};

	};

	thermal_zones: thermal-zones {
		#include "omap4-cpu-thermal.dtsi"
		#include "omap5-gpu-thermal.dtsi"
		#include "omap5-core-thermal.dtsi"
		#include "dra7-dspeve-thermal.dtsi"
		#include "dra7-iva-thermal.dtsi"
	};

};

&cpu_thermal {
	polling-delay = <500>; /* milliseconds */
	coefficients = <0 2000>;
};

&gpu_thermal {
	coefficients = <0 2000>;
};

&core_thermal {
	coefficients = <0 2000>;
};

&dspeve_thermal {
	coefficients = <0 2000>;
};

&iva_thermal {
	coefficients = <0 2000>;
};

&cpu_crit {
	temperature = <120000>; /* milli Celsius */
};

&core_crit {
	temperature = <120000>; /* milli Celsius */
};

&gpu_crit {
	temperature = <120000>; /* milli Celsius */
};

&dspeve_crit {
	temperature = <120000>; /* milli Celsius */
};

&iva_crit {
	temperature = <120000>; /* milli Celsius */
};

#include "dra7-l4.dtsi"
#include "dra7xx-clocks.dtsi"

&prm {
	prm_mpu: prm@300 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x300 0x100>;
		#power-domain-cells = <0>;
	};

	prm_dsp1: prm@400 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x400 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_ipu: prm@500 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x500 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_coreaon: prm@628 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x628 0xd8>;
		#power-domain-cells = <0>;
	};

	prm_core: prm@700 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x700 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_iva: prm@f00 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0xf00 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_cam: prm@1000 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1000 0x100>;
		#power-domain-cells = <0>;
	};

	prm_dss: prm@1100 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1100 0x100>;
		#power-domain-cells = <0>;
	};

	prm_gpu: prm@1200 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1200 0x100>;
		#power-domain-cells = <0>;
	};

	prm_l3init: prm@1300 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1300 0x100>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_l4per: prm@1400 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1400 0x100>;
		#power-domain-cells = <0>;
	};

	prm_custefuse: prm@1600 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1600 0x100>;
		#power-domain-cells = <0>;
	};

	prm_wkupaon: prm@1724 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1724 0x100>;
		#power-domain-cells = <0>;
	};

	prm_dsp2: prm@1b00 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1b00 0x40>;
		#reset-cells = <1>;
		#power-domain-cells = <0>;
	};

	prm_eve1: prm@1b40 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1b40 0x40>;
		#power-domain-cells = <0>;
	};

	prm_eve2: prm@1b80 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1b80 0x40>;
		#power-domain-cells = <0>;
	};

	prm_eve3: prm@1bc0 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1bc0 0x40>;
		#power-domain-cells = <0>;
	};

	prm_eve4: prm@1c00 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1c00 0x60>;
		#power-domain-cells = <0>;
	};

	prm_rtc: prm@1c60 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1c60 0x20>;
		#power-domain-cells = <0>;
	};

	prm_vpe: prm@1c80 {
		compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
		reg = <0x1c80 0x80>;
		#power-domain-cells = <0>;
	};
};

/* Preferred always-on timer for clockevent */
&timer1_target {
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
		assigned-clock-parents = <&sys_32k_ck>;
	};
};

/* Local timers, see ARM architected timer wrap erratum i940 */
&timer15_target {
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
		assigned-clock-parents = <&timer_sys_clk_div>;
	};
};

&timer16_target {
	ti,no-reset-on-init;
	ti,no-idle;
	timer@0 {
		assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
		assigned-clock-parents = <&timer_sys_clk_div>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "dra71x.dtsi"
#include "dra7-mmc-iodelay.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>

/ {
	compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7";
	model = "TI DRA718 EVM";

	memory {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ipu2_memory_region: ipu2-memory@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x3800000>;
			reusable;
			status = "okay";
		};

		dsp1_memory_region: dsp1-memory@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_memory_region: ipu1-memory@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};
	};

	vpo_sd_1v8_3v3: gpio-regulator-TPS74801 {
		compatible = "regulator-gpio";

		regulator-name = "vddshv8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&evm_5v0>;

		gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0
			  3300000 0x1>;
	};

	evm_1v8_sw: fixedregulator-evm_1v8 {
		compatible = "regulator-fixed";
		regulator-name = "evm_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&lp8732_buck0_reg>;
		regulator-always-on;
		regulator-boot-on;
	};

	poweroff: gpio-poweroff {
		compatible = "gpio-poweroff";
		gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>;
		input;
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	lp8733: lp8733@60 {
		compatible = "ti,lp8733";
		reg = <0x60>;

		buck0-in-supply =<&vsys_3v3>;
		buck1-in-supply =<&vsys_3v3>;
		ldo0-in-supply =<&evm_5v0>;
		ldo1-in-supply =<&evm_5v0>;

		lp8733_regulators: regulators {
			lp8733_buck0_reg: buck0 {
				/* FB_B0 -> LP8733-BUCK1 - VPO_S1_AVS - VDD_CORE_AVS (core, mpu, gpu) */
				regulator-name = "lp8733-buck0";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-always-on;
				regulator-boot-on;
			};

			lp8733_buck1_reg: buck1 {
				/* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */
				regulator-name = "lp8733-buck1";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8733_ldo0_reg: ldo0 {
				/* LDO0 -> LP8733-LDO1 - VPO_L1_3V3 - VDDSHV8 (optional) */
				regulator-name = "lp8733-ldo0";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8733_ldo1_reg: ldo1 {
				/* LDO1 -> LP8733-LDO2 - VPO_L2_3V3 - VDDA_USB3V3 */
				regulator-name = "lp8733-ldo1";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};

	lp8732: lp8732@61 {
		compatible = "ti,lp8732";
		reg = <0x61>;

		buck0-in-supply =<&vsys_3v3>;
		buck1-in-supply =<&vsys_3v3>;
		ldo0-in-supply =<&vsys_3v3>;
		ldo1-in-supply =<&vsys_3v3>;

		lp8732_regulators: regulators {
			lp8732_buck0_reg: buck0 {
				/* FB_B0 -> LP8732-BUCK1 - VPO_S3_1V8 - VDDS_1V8 */
				regulator-name = "lp8732-buck0";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			lp8732_buck1_reg: buck1 {
				/* FB_B1 -> LP8732-BUCK2 - VPO_S4_DDR - VDD_DDR_1V35 */
				regulator-name = "lp8732-buck1";
				regulator-min-microvolt = <1350000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8732_ldo0_reg: ldo0 {
				/* LDO0 -> LP8732-LDO1 - VPO_L3_1V8 - VDA_1V8_PLL */
				regulator-name = "lp8732-ldo0";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			lp8732_ldo1_reg: ldo1 {
				/* LDO1 -> LP8732-LDO2 - VPO_L4_1V8 - VDA_1V8_PHY */
				regulator-name = "lp8732-ldo1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};
};

&pcf_lcd {
	interrupt-parent = <&gpio7>;
	interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
};

&pcf_gpio_21 {
	interrupt-parent = <&gpio7>;
	interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
};

&pcf_hdmi {
	hdmi-i2c-disable-hog {
		/*
		 * PM_OEn to High: Disable routing I2C3 to PM_I2C
		 * With this PM_SEL(p3) should not matter
		 */
		gpio-hog;
		gpios = <0 GPIO_ACTIVE_LOW>;
		output-high;
		line-name = "pm_oe_n";
	};
};

&mmc1 {
	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
	pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
	pinctrl-1 = <&mmc1_pins_hs>;
	pinctrl-2 = <&mmc1_pins_sdr12>;
	pinctrl-3 = <&mmc1_pins_sdr25>;
	pinctrl-4 = <&mmc1_pins_sdr50>;
	pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
	vqmmc-supply = <&vpo_sd_1v8_3v3>;
};

&mmc2 {
	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
	pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
	vmmc-supply = <&evm_1v8_sw>;
	vqmmc-supply = <&evm_1v8_sw>;
};

&mac_sw {
	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
		     <&pcf_hdmi 9 GPIO_ACTIVE_LOW>,	/* P11 */
		     <&pcf_hdmi 10 GPIO_ACTIVE_LOW>;	/* P12 */
	status = "okay";
};

&cpsw_port1 {
	phy-handle = <&dp83867_0>;
	phy-mode = "rgmii-id";
	ti,dual-emac-pvid = <1>;
};

&cpsw_port2 {
	phy-handle = <&dp83867_1>;
	phy-mode = "rgmii-id";
	ti,dual-emac-pvid = <2>;
};

&davinci_mdio_sw {
	dp83867_0: ethernet-phy@2 {
		reg = <2>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
		ti,min-output-impedance;
		ti,dp83867-rxctrl-strap-quirk;
	};

	dp83867_1: ethernet-phy@3 {
		reg = <3>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
		ti,min-output-impedance;
		ti,dp83867-rxctrl-strap-quirk;
	};
};

/* No Sata on this device */
&sata_phy {
	status = "disabled";
};

&sata {
	status = "disabled";
};

/* No RTC on this device */
&rtc {
	status = "disabled";
};

&usb2_phy1 {
	phy-supply = <&lp8733_ldo1_reg>;
};

&usb2_phy2 {
	phy-supply = <&lp8733_ldo1_reg>;
};

&dss {
	/* Supplied by VDA_1V8_PLL */
	vdda_video-supply = <&lp8732_ldo0_reg>;
};

&hdmi {
	/* Supplied by VDA_1V8_PHY */
	vdda_video-supply = <&lp8732_ldo1_reg>;
};

&extcon_usb1 {
	vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>;
};

&extcon_usb2 {
	vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>;
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_memory_region>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_memory_region>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_memory_region>;
};

repo_name: angery/linux


code:
/*
 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "dra72-evm-common.dtsi"

&rtctarget {
	status = "disabled";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
 */
/dts-v1/;

#include "dra72x.dtsi"
#include "dra7-ipu-dsp-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/ti-dra7-atl.h>

/ {
	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";

	aliases {
		display0 = &hdmi0;
	};

	chosen {
		stdout-path = &uart1;
	};

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_5v0: fixedregulator-evm5v0 {
		/* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 1 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "evm_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_3v6: fixedregulator-evm_3v6 {
		compatible = "regulator-fixed";
		regulator-name = "evm_3v6";
		regulator-min-microvolt = <3600000>;
		regulator-max-microvolt = <3600000>;
		vin-supply = <&evm_5v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
		/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_3v3_sw: fixedregulator-evm_3v3 {
		/* TPS22965DSG */
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vsys_3v3>;
		regulator-always-on;
		regulator-boot-on;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
		/* TPS77018DBVT */
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd";
		vin-supply = <&evm_3v3_sw>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	evm_3v3_sd: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "evm_3v3_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_3v3_sw>;
		enable-active-high;
		gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
	};

	extcon_usb1: extcon_usb1 {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
	};

	extcon_usb2: extcon_usb2 {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
	};

	hdmi0: connector {
		compatible = "hdmi-connector";
		label = "hdmi";

		type = "a";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&tpd12s015_out>;
			};
		};
	};

	tpd12s015: encoder {
		compatible = "ti,tpd12s015";

		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				tpd12s015_in: endpoint {
					remote-endpoint = <&hdmi_out>;
				};
			};

			port@1 {
				reg = <1>;

				tpd12s015_out: endpoint {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};

	sound0: sound0 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-EVM";
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Line", "Line Out",
			"Microphone", "Mic Jack",
			"Line", "Line In";
		simple-audio-card,routing =
			"Headphone Jack",       "HPLOUT",
			"Headphone Jack",       "HPROUT",
			"Line Out",		"LLOUT",
			"Line Out",		"RLOUT",
			"MIC3L",		"Mic Jack",
			"MIC3R",		"Mic Jack",
			"Mic Jack",		"Mic Bias",
			"LINE1L",               "Line In",
			"LINE1R",               "Line In";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&sound0_master>;
		simple-audio-card,frame-master = <&sound0_master>;
		simple-audio-card,bitclock-inversion;

		sound0_master: simple-audio-card,cpu {
			sound-dai = <&mcasp3>;
			system-clock-frequency = <5644800>;
		};

		simple-audio-card,codec {
			sound-dai = <&tlv320aic3106>;
			clocks = <&atl_clkin2_ck>;
		};
	};

	vmmcwl_fixed: fixedregulator-mmcwl {
		compatible = "regulator-fixed";
		regulator-name = "vmmcwl_fixed";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	clk_ov5640_fixed: clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
	};
};

&dra7_pmx_core {
	dcan1_pins_default: dcan1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
			DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1)	/* wakeup0.dcan1_rx */
		>;
	};

	dcan1_pins_sleep: dcan1_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
			DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP)	/* wakeup0.off */
		>;
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	pcf_lcd: gpio@20 {
		compatible = "nxp,pcf8575";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	pcf_gpio_21: gpio@21 {
		compatible = "nxp,pcf8575";
		reg = <0x21>;
		lines-initial-states = <0x1408>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	tlv320aic3106: tlv320aic3106@19 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x19>;
		adc-settle-ms = <40>;
		ai3x-micbias-vg = <1>;		/* 2.0V */
		status = "okay";

		/* Regulators */
		AVDD-supply = <&evm_3v3_sw>;
		IOVDD-supply = <&evm_3v3_sw>;
		DRVDD-supply = <&evm_3v3_sw>;
		DVDD-supply = <&aic_dvdd>;
	};
};

&i2c5 {
	status = "okay";
	clock-frequency = <400000>;

	pcf_hdmi: pcf8575@26 {
		compatible = "nxp,pcf8575";
		reg = <0x26>;
		gpio-controller;
		#gpio-cells = <2>;
		/*
		 * initial state is used here to keep the mdio interface
		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
		 * VIN2_S0 driven high otherwise Ethernet stops working
		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
		 */
		lines-initial-states = <0x0f2b>;

		hdmi-audio-hog {
			/* vin6_sel_s0: high: VIN6, low: audio */
			gpio-hog;
			gpios = <1 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "vin6_sel_s0";
		};
	};

	ov5640@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;

		clocks = <&clk_ov5640_fixed>;
		clock-names = "xclk";

		port {
			csi2_cam0: endpoint {
				remote-endpoint = <&csi2_phy0>;
				clock-lanes = <0>;
				data-lanes = <1 2>;
			};
		};
	};

};

&uart1 {
	status = "okay";
	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
			      <&dra7_pmx_core 0x3e0>;
};

&elm {
	status = "okay";
};

&gpmc {
	/*
	 * For the existing IOdelay configuration via U-Boot we don't
	 * support NAND on dra72-evm. Keep it disabled. Enabling it
	 * requires a different configuration by U-Boot.
	 */
	status = "disabled";
	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		/* To use NAND, DIP switch SW5 must be set like so:
		 * SW5.1 (NAND_SELn) = ON (LOW)
		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
		 */
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;		/* device IO registers */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
		ti,nand-xfer-type = "prefetch-dma";
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;
		gpmc,device-width = <2>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <80>;
		gpmc,cs-wr-off-ns = <80>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <60>;
		gpmc,adv-wr-off-ns = <60>;
		gpmc,we-on-ns = <10>;
		gpmc,we-off-ns = <50>;
		gpmc,oe-on-ns = <4>;
		gpmc,oe-off-ns = <40>;
		gpmc,access-ns = <40>;
		gpmc,wr-access-ns = <80>;
		gpmc,rd-cycle-ns = <80>;
		gpmc,wr-cycle-ns = <80>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x00020000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00020000 0x00020000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00040000 0x00020000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x00060000 0x00020000>;
		};
		partition@4 {
			label = "NAND.u-boot-spl-os";
			reg = <0x00080000 0x00040000>;
		};
		partition@5 {
			label = "NAND.u-boot";
			reg = <0x000c0000 0x00100000>;
		};
		partition@6 {
			label = "NAND.u-boot-env";
			reg = <0x001c0000 0x00020000>;
		};
		partition@7 {
			label = "NAND.u-boot-env.backup1";
			reg = <0x001e0000 0x00020000>;
		};
		partition@8 {
			label = "NAND.kernel";
			reg = <0x00200000 0x00800000>;
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00a00000 0x0f600000>;
		};
	};
};

&omap_dwc3_1 {
	extcon = <&extcon_usb1>;
};

&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
};

&usb1 {
	dr_mode = "otg";
	extcon = <&extcon_usb1>;
};

&usb2 {
	dr_mode = "host";
	extcon = <&extcon_usb2>;
};

&mmc1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins_default>;
	vmmc-supply = <&evm_3v3_sd>;
	bus-width = <4>;
	/*
	 * SDCD signal is not being used here - using the fact that GPIO mode
	 * is a viable alternative
	 */
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
	max-frequency = <192000000>;
};

&mmc2 {
	/* SW5-3 in ON position */
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins_default>;
	bus-width = <8>;
	non-removable;
	max-frequency = <192000000>;
};

&mmc4 {
	status = "okay";
	vmmc-supply = <&evm_3v6>;
	vqmmc-supply = <&vmmcwl_fixed>;
	bus-width = <4>;
	cap-power-off-card;
	keep-power-in-suspend;
	non-removable;
	pinctrl-names = "default", "hs", "sdr12", "sdr25";
	pinctrl-0 = <&mmc4_pins_default>;
	pinctrl-1 = <&mmc4_pins_default>;
	pinctrl-2 = <&mmc4_pins_default>;
	pinctrl-3 = <&mmc4_pins_default>;
	#address-cells = <1>;
	#size-cells = <0>;
	wifi@2 {
		compatible = "ti,wl1835";
		reg = <2>;
		interrupt-parent = <&gpio5>;
		interrupts = <7 IRQ_TYPE_EDGE_RISING>;
	};
};

&dcan1 {
	status = "okay";
	pinctrl-names = "default", "sleep", "active";
	pinctrl-0 = <&dcan1_pins_sleep>;
	pinctrl-1 = <&dcan1_pins_sleep>;
	pinctrl-2 = <&dcan1_pins_default>;
};

&qspi {
	status = "okay";

	spi-max-frequency = <76800000>;
	flash@0 {
		compatible = "s25fl256s1";
		spi-max-frequency = <76800000>;
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */
		partition@0 {
			label = "QSPI.SPL";
			reg = <0x00000000 0x00010000>;
		};
		partition@1 {
			label = "QSPI.SPL.backup1";
			reg = <0x00010000 0x00010000>;
		};
		partition@2 {
			label = "QSPI.SPL.backup2";
			reg = <0x00020000 0x00010000>;
		};
		partition@3 {
			label = "QSPI.SPL.backup3";
			reg = <0x00030000 0x00010000>;
		};
		partition@4 {
			label = "QSPI.u-boot";
			reg = <0x00040000 0x00100000>;
		};
		partition@5 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x00140000 0x00080000>;
		};
		partition@6 {
			label = "QSPI.u-boot-env";
			reg = <0x001c0000 0x00010000>;
		};
		partition@7 {
			label = "QSPI.u-boot-env.backup1";
			reg = <0x001d0000 0x0010000>;
		};
		partition@8 {
			label = "QSPI.kernel";
			reg = <0x001e0000 0x0800000>;
		};
		partition@9 {
			label = "QSPI.file-system";
			reg = <0x009e0000 0x01620000>;
		};
	};
};

&dss {
	status = "okay";
};

&hdmi {
	status = "okay";

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&tpd12s015_in>;
		};
	};
};

&atl {
	assigned-clocks = <&abe_dpll_sys_clk_mux>,
			  <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>,
			  <&dpll_abe_ck>,
			  <&dpll_abe_m2x2_ck>,
			  <&atl_clkin2_ck>;
	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;

	status = "okay";

	atl2 {
		bws = <DRA7_ATL_WS_MCASP2_FSX>;
		aws = <DRA7_ATL_WS_MCASP3_FSX>;
	};
};

&mcasp3 {
	#sound-dai-cells = <0>;

	assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
	assigned-clock-parents = <&atl_clkin2_ck>;

	status = "okay";

	op-mode = <0>;          /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializer */
	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&pcie1_rc {
	status = "okay";
};

&csi2_0 {
	csi2_phy0: endpoint {
		remote-endpoint = <&csi2_cam0>;
		clock-lanes = <0>;
		data-lanes = <1 2>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
 */
#include "dra72-evm-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>

/ {
	model = "TI DRA722 Rev C EVM";

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ipu2_cma_pool: ipu2_cma@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x3800000>;
			reusable;
			status = "okay";
		};

		dsp1_cma_pool: dsp1_cma@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_cma_pool: ipu1_cma@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};
	};

	evm_1v8_sw: fixedregulator-evm_1v8 {
		compatible = "regulator-fixed";
		regulator-name = "evm_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&smps4_reg>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&i2c1 {
	tps65917: tps65917@58 {
		reg = <0x58>;

		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
	};
};

#include "dra72-evm-tps65917.dtsi"

&ldo2_reg {
	/* LDO2_OUT --> VDDA_1V8_PHY2 */
	regulator-always-on;
	regulator-boot-on;
};

&hdmi {
	vdda-supply = <&ldo2_reg>;
};

&pcf_gpio_21 {
	interrupt-parent = <&gpio3>;
	interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
};

&mac_sw {
	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
		     <&pcf_hdmi 9 GPIO_ACTIVE_LOW>,	/* P11 */
		     <&pcf_hdmi 10 GPIO_ACTIVE_LOW>;	/* P12 */
	status = "okay";
};

&cpsw_port1 {
	phy-handle = <&dp83867_0>;
	phy-mode = "rgmii-id";
	ti,dual-emac-pvid = <1>;
};

&cpsw_port2 {
	phy-handle = <&dp83867_1>;
	phy-mode = "rgmii-id";
	ti,dual-emac-pvid = <2>;
};

&davinci_mdio_sw {
	dp83867_0: ethernet-phy@2 {
		reg = <2>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
		ti,min-output-impedance;
		interrupt-parent = <&gpio6>;
		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
		ti,dp83867-rxctrl-strap-quirk;
	};

	dp83867_1: ethernet-phy@3 {
		reg = <3>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
		ti,min-output-impedance;
		interrupt-parent = <&gpio6>;
		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
		ti,dp83867-rxctrl-strap-quirk;
	};
};

&mmc1 {
	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	pinctrl-2 = <&mmc1_pins_sdr12>;
	pinctrl-3 = <&mmc1_pins_sdr25>;
	pinctrl-4 = <&mmc1_pins_sdr50>;
	pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
	vqmmc-supply = <&ldo1_reg>;
};

&mmc2 {
	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
	pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
	vmmc-supply = <&evm_1v8_sw>;
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_cma_pool>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_cma_pool>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_cma_pool>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
 */

/*
 * Integrated Power Management Chip
 * https://www.ti.com/lit/ds/symlink/tps65917-q1.pdf
 */

&tps65917 {
	compatible = "ti,tps65917";

	interrupt-controller;
	#interrupt-cells = <2>;

	ti,system-power-controller;

	tps65917_pmic {
		compatible = "ti,tps65917-pmic";

		smps1-in-supply = <&vsys_3v3>;
		smps2-in-supply = <&vsys_3v3>;
		smps3-in-supply = <&vsys_3v3>;
		smps4-in-supply = <&vsys_3v3>;
		smps5-in-supply = <&vsys_3v3>;
		ldo1-in-supply = <&vsys_3v3>;
		ldo2-in-supply = <&vsys_3v3>;
		ldo3-in-supply = <&vsys_3v3>;
		ldo4-in-supply = <&evm_5v0>;
		ldo5-in-supply = <&vsys_3v3>;

		tps65917_regulators: regulators {
			smps1_reg: smps1 {
				/* VDD_MPU */
				regulator-name = "smps1";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-always-on;
				regulator-boot-on;
			};

			smps2_reg: smps2 {
				/* VDD_CORE */
				regulator-name = "smps2";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1150000>;
				regulator-boot-on;
				regulator-always-on;
			};

			smps3_reg: smps3 {
				/* VDD_GPU IVA DSPEVE */
				regulator-name = "smps3";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-boot-on;
				regulator-always-on;
			};

			smps4_reg: smps4 {
				/* VDDS1V8 */
				regulator-name = "smps4";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			smps5_reg: smps5 {
				/* VDD_DDR */
				regulator-name = "smps5";
				regulator-min-microvolt = <1350000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: ldo1 {
				/* LDO1_OUT --> SDIO  */
				regulator-name = "ldo1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				regulator-boot-on;
				regulator-allow-bypass;
			};

			ldo2_reg: ldo2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-allow-bypass;
			};

			ldo3_reg: ldo3 {
				/* VDDA_1V8_PHY */
				regulator-name = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo5_reg: ldo5 {
				/* VDDA_1V8_PLL */
				regulator-name = "ldo5";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			ldo4_reg: ldo4 {
				/* VDDA_3V_USB: VDDA_USBHS33 */
				regulator-name = "ldo4";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
			};
		};
	};

	tps65917_power_button {
		compatible = "ti,palmas-pwrbutton";
		interrupt-parent = <&tps65917>;
		interrupts = <1 IRQ_TYPE_NONE>;
		wakeup-source;
		ti,palmas-long-press-seconds = <6>;
	};
};

&usb2_phy1 {
	phy-supply = <&ldo4_reg>;
};

&usb2_phy2 {
	phy-supply = <&ldo4_reg>;
};

&dss {
	vdda_video-supply = <&ldo5_reg>;
};

&mmc1 {
	vqmmc-supply = <&ldo1_reg>;
};

&cpu0 {
	vdd-supply = <&smps1_reg>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
 */
#include "dra72-evm-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
/ {
	model = "TI DRA722";

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ipu2_memory_region: ipu2-memory@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x3800000>;
			reusable;
			status = "okay";
		};

		dsp1_memory_region: dsp1-memory@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_memory_region: ipu1-memory@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};
	};

	evm_1v8_sw: fixedregulator-evm_1v8 {
		compatible = "regulator-fixed";
		regulator-name = "evm_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&smps4_reg>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&i2c1 {
	tps65917: tps65917@58 {
		reg = <0x58>;

		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
	};
};

#include "dra72-evm-tps65917.dtsi"

&hdmi {
	vdda-supply = <&ldo3_reg>;
};

&pcf_gpio_21 {
	interrupt-parent = <&gpio6>;
	interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
};

&mac_sw {
	mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&cpsw_port1 {
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii";
	ti,dual-emac-pvid = <1>;
};

&cpsw_port2 {
	status = "disabled";
};

&davinci_mdio_sw {
	ethphy0: ethernet-phy@3 {
		reg = <3>;
	};
};

&mmc1 {
	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	pinctrl-2 = <&mmc1_pins_sdr12>;
	pinctrl-3 = <&mmc1_pins_sdr25>;
	pinctrl-4 = <&mmc1_pins_sdr50>;
	pinctrl-5 = <&mmc1_pins_ddr50_rev10>;
	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;
	vqmmc-supply = <&ldo1_reg>;
};

&mmc2 {
	pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr_rev10>;
	pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
	vmmc-supply = <&evm_1v8_sw>;
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_memory_region>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_memory_region>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_memory_region>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs.
 *
 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
 */

/*
 * Rules for modifying this file:
 * a) Update of this file should typically correspond to a datamanual revision.
 *    Datamanual revision that was used should be updated in comment below.
 *    If there is no update to datamanual, do not update the values. If you
 *    need to use values different from that recommended by the datamanual
 *    for your design, then you should consider adding values to the device-
 *    -tree file for your board directly.
 * b) We keep the mode names as close to the datamanual as possible. So
 *    if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
 *    we follow that in code too.
 * c) If the values change between multiple revisions of silicon, we add
 *    a revision tag to both the new and old entry. Use 'rev10' for PG 1.0,
 *    'rev20' for PG 2.0 and so on.
 * d) The node name and node label should be the exact same string. This is
 *    to curb naming creativity and achieve consistency.
 * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and
 *    'dra72_' tag to entries. Both the new and old entries should gain a tag.
 *
 * Datamanual Revisions:
 *
 * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017
 * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017
 * DRA71x : SPRS960B, Revised February 2017
 */

&dra7_pmx_core {
	mmc1_pins_default: mmc1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_sdr12: mmc1_pins_sdr12 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_hs: mmc1_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_sdr25: mmc1_pins_sdr25 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_sdr50: mmc1_pins_sdr50 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)	/* mmc1_clk.mmc1_clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)	/* mmc1_cmd.mmc1_cmd */
			DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)	/* mmc1_dat0.mmc1_dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)	/* mmc1_dat1.mmc1_dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)	/* mmc1_dat2.mmc1_dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)	/* mmc1_dat3.mmc1_dat3 */
		>;
	};

	mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_sdr104: mmc1_pins_sdr104 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_clk.clk */
			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_cmd.cmd */
			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat0.dat0 */
			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat1.dat1 */
			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat2.dat2 */
			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc2_pins_default: mmc2_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_hs: mmc2_pins_hs {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a22.mmc2_dat7 */
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1)	/* gpmc_cs1.mmc2_cmd */
		>;
	};

	mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_hs200: mmc2_pins_hs200 {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc4_pins_default: mmc4_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
			DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
			DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
			DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
			DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
			DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
		>;
	};
};

&dra7_iodelay_core {

	/* Corresponds to MMC1_MANUAL1 in datamanual */
	mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
		pinctrl-pin-array = <
			0x618 A_DELAY_PS(588) G_DELAY_PS(0)	/* CFG_MMC1_CLK_IN */
			0x624 A_DELAY_PS(1000) G_DELAY_PS(0)	/* CFG_MMC1_CMD_IN */
			0x630 A_DELAY_PS(1375) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_IN */
			0x63C A_DELAY_PS(1000) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_IN */
			0x648 A_DELAY_PS(1000) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_IN */
			0x654 A_DELAY_PS(1000) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_IN */
			0x620 A_DELAY_PS(1230) G_DELAY_PS(0)	/* CFG_MMC1_CLK_OUT */
			0x62C A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OUT */
			0x638 A_DELAY_PS(56) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OUT */
			0x644 A_DELAY_PS(76) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OUT */
			0x650 A_DELAY_PS(91) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OUT */
			0x65C A_DELAY_PS(99) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OUT */
			0x628 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OEN */
			0x634 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OEN */
			0x640 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OEN */
			0x64C A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OEN */
			0x658 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OEN */
		>;
	};

	/* Corresponds to MMC1_MANUAL2 in datamanual */
	mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf {
		pinctrl-pin-array = <
			0x620 A_DELAY_PS(560) G_DELAY_PS(365)	/* CFG_MMC1_CLK_OUT */
			0x62c A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OUT */
			0x638 A_DELAY_PS(29) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OUT */
			0x644 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OUT */
			0x650 A_DELAY_PS(47) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OUT */
			0x65c A_DELAY_PS(30) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OUT */
			0x628 A_DELAY_PS(125) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OEN */
			0x634 A_DELAY_PS(43) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OEN */
			0x640 A_DELAY_PS(433) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OEN */
			0x64c A_DELAY_PS(287) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OEN */
			0x658 A_DELAY_PS(351) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OEN */
		>;
	};

	/* Corresponds to MMC1_MANUAL2 in datamanual */
	mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
		pinctrl-pin-array = <
			0x620 A_DELAY_PS(520) G_DELAY_PS(320)	/* CFG_MMC1_CLK_OUT */
			0x62c A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OUT */
			0x638 A_DELAY_PS(40) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OUT */
			0x644 A_DELAY_PS(83) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OUT */
			0x650 A_DELAY_PS(98) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OUT */
			0x65c A_DELAY_PS(106) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OUT */
			0x628 A_DELAY_PS(51) G_DELAY_PS(0)	/* CFG_MMC1_CMD_OEN */
			0x634 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_MMC1_DAT0_OEN */
			0x640 A_DELAY_PS(363) G_DELAY_PS(0)	/* CFG_MMC1_DAT1_OEN */
			0x64c A_DELAY_PS(199) G_DELAY_PS(0)	/* CFG_MMC1_DAT2_OEN */
			0x658 A_DELAY_PS(273) G_DELAY_PS(0)	/* CFG_MMC1_DAT3_OEN */
		>;
	};

	/* Corresponds to MMC2_MANUAL1 in datamanual */
	mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf {
		pinctrl-pin-array = <
			0x18c A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A19_IN */
			0x1a4 A_DELAY_PS(119) G_DELAY_PS(0)	/* CFG_GPMC_A20_IN */
			0x1b0 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A21_IN */
			0x1bc A_DELAY_PS(18) G_DELAY_PS(0)	/* CFG_GPMC_A22_IN */
			0x1c8 A_DELAY_PS(894) G_DELAY_PS(0)	/* CFG_GPMC_A23_IN */
			0x1d4 A_DELAY_PS(30) G_DELAY_PS(0)	/* CFG_GPMC_A24_IN */
			0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A25_IN */
			0x1ec A_DELAY_PS(23) G_DELAY_PS(0)	/* CFG_GPMC_A26_IN */
			0x1f8 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A27_IN */
			0x360 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_CS1_IN */
			0x194 A_DELAY_PS(152) G_DELAY_PS(0)	/* CFG_GPMC_A19_OUT */
			0x1ac A_DELAY_PS(206) G_DELAY_PS(0)	/* CFG_GPMC_A20_OUT */
			0x1b8 A_DELAY_PS(78) G_DELAY_PS(0)	/* CFG_GPMC_A21_OUT */
			0x1c4 A_DELAY_PS(2) G_DELAY_PS(0)	/* CFG_GPMC_A22_OUT */
			0x1d0 A_DELAY_PS(266) G_DELAY_PS(0)	/* CFG_GPMC_A23_OUT */
			0x1dc A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A24_OUT */
			0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A25_OUT */
			0x1f4 A_DELAY_PS(43) G_DELAY_PS(0)	/* CFG_GPMC_A26_OUT */
			0x200 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A27_OUT */
			0x368 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_CS1_OUT */
			0x190 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A19_OEN */
			0x1a8 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A20_OEN */
			0x1b4 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A21_OEN */
			0x1c0 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A22_OEN */
			0x1d8 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A24_OEN */
			0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A25_OEN */
			0x1f0 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A26_OEN */
			0x1fc A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A27_OEN */
			0x364 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_CS1_OEN */
		>;
	};

	/* Corresponds to MMC2_MANUAL3 in datamanual */
	mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf {
		pinctrl-pin-array = <
			0x194 A_DELAY_PS(150) G_DELAY_PS(95)	/* CFG_GPMC_A19_OUT */
			0x1ac A_DELAY_PS(250) G_DELAY_PS(0)	/* CFG_GPMC_A20_OUT */
			0x1b8 A_DELAY_PS(125) G_DELAY_PS(0)	/* CFG_GPMC_A21_OUT */
			0x1c4 A_DELAY_PS(100) G_DELAY_PS(0)	/* CFG_GPMC_A22_OUT */
			0x1d0 A_DELAY_PS(870) G_DELAY_PS(415)	/* CFG_GPMC_A23_OUT */
			0x1dc A_DELAY_PS(30) G_DELAY_PS(0)	/* CFG_GPMC_A24_OUT */
			0x1e8 A_DELAY_PS(200) G_DELAY_PS(0)	/* CFG_GPMC_A25_OUT */
			0x1f4 A_DELAY_PS(200) G_DELAY_PS(0)	/* CFG_GPMC_A26_OUT */
			0x200 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A27_OUT */
			0x368 A_DELAY_PS(240) G_DELAY_PS(0)	/* CFG_GPMC_CS1_OUT */
			0x190 A_DELAY_PS(695) G_DELAY_PS(0)	/* CFG_GPMC_A19_OEN */
			0x1a8 A_DELAY_PS(924) G_DELAY_PS(0)	/* CFG_GPMC_A20_OEN */
			0x1b4 A_DELAY_PS(719) G_DELAY_PS(0)	/* CFG_GPMC_A21_OEN */
			0x1c0 A_DELAY_PS(824) G_DELAY_PS(0)	/* CFG_GPMC_A22_OEN */
			0x1d8 A_DELAY_PS(877) G_DELAY_PS(0)	/* CFG_GPMC_A24_OEN */
			0x1e4 A_DELAY_PS(446) G_DELAY_PS(0)	/* CFG_GPMC_A25_OEN */
			0x1f0 A_DELAY_PS(847) G_DELAY_PS(0)	/* CFG_GPMC_A26_OEN */
			0x1fc A_DELAY_PS(586) G_DELAY_PS(0)	/* CFG_GPMC_A27_OEN */
			0x364 A_DELAY_PS(1039) G_DELAY_PS(0)	/* CFG_GPMC_CS1_OEN */
		>;
	};

	/* Corresponds to MMC2_MANUAL3 in datamanual */
	mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
		pinctrl-pin-array = <
			0x194 A_DELAY_PS(285) G_DELAY_PS(0)	/* CFG_GPMC_A19_OUT */
			0x1ac A_DELAY_PS(189) G_DELAY_PS(0)	/* CFG_GPMC_A20_OUT */
			0x1b8 A_DELAY_PS(0) G_DELAY_PS(120)	/* CFG_GPMC_A21_OUT */
			0x1c4 A_DELAY_PS(0) G_DELAY_PS(70)	/* CFG_GPMC_A22_OUT */
			0x1d0 A_DELAY_PS(730) G_DELAY_PS(360)	/* CFG_GPMC_A23_OUT */
			0x1dc A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A24_OUT */
			0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A25_OUT */
			0x1f4 A_DELAY_PS(70) G_DELAY_PS(0)	/* CFG_GPMC_A26_OUT */
			0x200 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A27_OUT */
			0x368 A_DELAY_PS(0) G_DELAY_PS(120)	/* CFG_GPMC_CS1_OUT */
			0x190 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A19_OEN */
			0x1a8 A_DELAY_PS(231) G_DELAY_PS(0)	/* CFG_GPMC_A20_OEN */
			0x1b4 A_DELAY_PS(39) G_DELAY_PS(0)	/* CFG_GPMC_A21_OEN */
			0x1c0 A_DELAY_PS(91) G_DELAY_PS(0)	/* CFG_GPMC_A22_OEN */
			0x1d8 A_DELAY_PS(176) G_DELAY_PS(0)	/* CFG_GPMC_A24_OEN */
			0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A25_OEN */
			0x1f0 A_DELAY_PS(101) G_DELAY_PS(0)	/* CFG_GPMC_A26_OEN */
			0x1fc A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A27_OEN */
			0x364 A_DELAY_PS(360) G_DELAY_PS(0)	/* CFG_GPMC_CS1_OEN */
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Based on "omap4.dtsi"
 */

#include "dra7.dtsi"

/ {
	compatible = "ti,dra722", "ti,dra72", "ti,dra7";

	aliases {
		rproc0 = &ipu1;
		rproc1 = &ipu2;
		rproc2 = &dsp1;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupt-parent = <&wakeupgen>;
		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
	};
};

&l4_per2 {
	target-module@5b000 {			/* 0x4845b000, ap 59 46.0 */
		compatible = "ti,sysc-omap4", "ti,sysc";
		reg = <0x5b000 0x4>,
		      <0x5b010 0x4>;
		reg-names = "rev", "sysc";
		ti,sysc-midle = <SYSC_IDLE_FORCE>,
				<SYSC_IDLE_NO>;
		ti,sysc-sidle = <SYSC_IDLE_FORCE>,
				<SYSC_IDLE_NO>;
		clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
		clock-names = "fck";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x5b000 0x1000>;

		cal: cal@0 {
			compatible = "ti,dra72-cal";
			reg = <0x0000 0x400>,
			      <0x0800 0x40>,
			      <0x0900 0x40>;
			reg-names = "cal_top",
				    "cal_rx_core0",
				    "cal_rx_core1";
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			ti,camerrx-control = <&scm_conf 0xE94>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi2_0: port@0 {
					reg = <0>;
				};
				csi2_1: port@1 {
					reg = <1>;
				};
			};
		};
	};
};

&dss {
	reg = <0 0x80>,
	      <0x4054 0x4>,
	      <0x4300 0x20>;
	reg-names = "dss", "pll1_clkctrl", "pll1";

	clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
		 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>;
	clock-names = "fck", "video1_clk";
};

&mailbox5 {
	mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
		ti,mbox-tx = <6 2 2>;
		ti,mbox-rx = <4 2 2>;
		status = "disabled";
	};
	mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
		ti,mbox-tx = <5 2 2>;
		ti,mbox-rx = <1 2 2>;
		status = "disabled";
	};
};

&mailbox6 {
	mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
		ti,mbox-tx = <6 2 2>;
		ti,mbox-rx = <4 2 2>;
		status = "disabled";
	};
};

&pcie1_rc {
	compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
};

&pcie1_ep {
	compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep";
};

&pcie2_rc {
	compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Common IPU and DSP data for TI DRA74x/DRA76x/AM572x/AM574x platforms
 */

#include "dra7-ipu-dsp-common.dtsi"

&mailbox6 {
	mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
		status = "okay";
	};
};

&dsp2 {
	mboxes = <&mailbox6 &mbox_dsp2_ipc3x>;
	ti,timers = <&timer6>;
	ti,watchdog-timers = <&timer13>;
};