code:
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/tegra30-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra30-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/tegra-pmc.h>
#include <dt-bindings/thermal/thermal.h>

#include "tegra30-peripherals-opp.dtsi"

/ {
	compatible = "nvidia,tegra30";
	interrupt-parent = <&lic>;
	#address-cells = <1>;
	#size-cells = <1>;

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x0>;
	};

	pcie@3000 {
		compatible = "nvidia,tegra30-pcie";
		device_type = "pci";
		reg = <0x00003000 0x00000800>, /* PADS registers */
		      <0x00003800 0x00000200>, /* AFI registers */
		      <0x10000000 0x10000000>; /* configuration space */
		reg-names = "pads", "afi", "cs";
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
		interrupt-names = "intr", "msi";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

		bus-range = <0x00 0xff>;
		#address-cells = <3>;
		#size-cells = <2>;

		ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
			 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
			 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
			 <0x01000000 0 0          0x02000000 0 0x00010000>, /* downstream I/O */
			 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
			 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */

		clocks = <&tegra_car TEGRA30_CLK_PCIE>,
			 <&tegra_car TEGRA30_CLK_AFI>,
			 <&tegra_car TEGRA30_CLK_PLL_E>,
			 <&tegra_car TEGRA30_CLK_CML0>;
		clock-names = "pex", "afi", "pll_e", "cml";
		resets = <&tegra_car 70>,
			 <&tegra_car 72>,
			 <&tegra_car 74>;
		reset-names = "pex", "afi", "pcie_x";
		power-domains = <&pd_core>;
		operating-points-v2 = <&pcie_dvfs_opp_table>;
		status = "disabled";

		pci@1,0 {
			device_type = "pci";
			assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
			reg = <0x000800 0 0 0 0>;
			bus-range = <0x00 0xff>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <2>;
		};

		pci@2,0 {
			device_type = "pci";
			assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
			reg = <0x001000 0 0 0 0>;
			bus-range = <0x00 0xff>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <2>;
		};

		pci@3,0 {
			device_type = "pci";
			assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
			reg = <0x001800 0 0 0 0>;
			bus-range = <0x00 0xff>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <2>;
		};
	};

	sram@40000000 {
		compatible = "mmio-sram";
		reg = <0x40000000 0x40000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x40000000 0x40000>;

		vde_pool: sram@400 {
			reg = <0x400 0x3fc00>;
			pool;
		};
	};

	host1x@50000000 {
		compatible = "nvidia,tegra30-host1x";
		reg = <0x50000000 0x00024000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
		interrupt-names = "syncpt", "host1x";
		clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
		clock-names = "host1x";
		resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>;
		reset-names = "host1x", "mc";
		iommus = <&mc TEGRA_SWGROUP_HC>;
		power-domains = <&pd_heg>;
		operating-points-v2 = <&host1x_dvfs_opp_table>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe@54040000 {
			compatible = "nvidia,tegra30-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_MPE>;
			resets = <&tegra_car 60>;
			reset-names = "mpe";
			power-domains = <&pd_mpe>;
			operating-points-v2 = <&mpe_dvfs_opp_table>;

			iommus = <&mc TEGRA_SWGROUP_MPE>;

			status = "disabled";
		};

		vi@54080000 {
			compatible = "nvidia,tegra30-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_VI>;
			resets = <&tegra_car 20>;
			reset-names = "vi";
			power-domains = <&pd_venc>;
			operating-points-v2 = <&vi_dvfs_opp_table>;

			iommus = <&mc TEGRA_SWGROUP_VI>;

			status = "disabled";
		};

		epp@540c0000 {
			compatible = "nvidia,tegra30-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_EPP>;
			resets = <&tegra_car 19>;
			reset-names = "epp";
			power-domains = <&pd_heg>;
			operating-points-v2 = <&epp_dvfs_opp_table>;

			iommus = <&mc TEGRA_SWGROUP_EPP>;

			status = "disabled";
		};

		isp@54100000 {
			compatible = "nvidia,tegra30-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_ISP>;
			resets = <&tegra_car 23>;
			reset-names = "isp";
			power-domains = <&pd_venc>;

			iommus = <&mc TEGRA_SWGROUP_ISP>;

			status = "disabled";
		};

		gr2d@54140000 {
			compatible = "nvidia,tegra30-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_GR2D>;
			resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>;
			reset-names = "2d", "mc";
			power-domains = <&pd_heg>;
			operating-points-v2 = <&gr2d_dvfs_opp_table>;

			iommus = <&mc TEGRA_SWGROUP_G2>;
		};

		gr3d@54180000 {
			compatible = "nvidia,tegra30-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car TEGRA30_CLK_GR3D>,
				 <&tegra_car TEGRA30_CLK_GR3D2>;
			clock-names = "3d", "3d2";
			resets = <&tegra_car 24>,
				 <&tegra_car 98>,
				 <&mc TEGRA30_MC_RESET_3D>,
				 <&mc TEGRA30_MC_RESET_3D2>;
			reset-names = "3d", "3d2", "mc", "mc2";
			power-domains = <&pd_3d0>, <&pd_3d1>;
			power-domain-names = "3d0", "3d1";
			operating-points-v2 = <&gr3d_dvfs_opp_table>;

			iommus = <&mc TEGRA_SWGROUP_NV>,
				 <&mc TEGRA_SWGROUP_NV2>;
		};

		dc@54200000 {
			compatible = "nvidia,tegra30-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
				 <&tegra_car TEGRA30_CLK_PLL_P>;
			clock-names = "dc", "parent";
			resets = <&tegra_car 27>;
			reset-names = "dc";
			power-domains = <&pd_core>;
			operating-points-v2 = <&disp1_dvfs_opp_table>;

			iommus = <&mc TEGRA_SWGROUP_DC>;

			nvidia,head = <0>;

			interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>,
					<&mc TEGRA30_MC_DISPLAY0B &emc>,
					<&mc TEGRA30_MC_DISPLAY1B &emc>,
					<&mc TEGRA30_MC_DISPLAY0C &emc>,
					<&mc TEGRA30_MC_DISPLAYHC &emc>;
			interconnect-names = "wina",
					     "winb",
					     "winb-vfilter",
					     "winc",
					     "cursor";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra30-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_DISP2>,
				 <&tegra_car TEGRA30_CLK_PLL_P>;
			clock-names = "dc", "parent";
			resets = <&tegra_car 26>;
			reset-names = "dc";
			power-domains = <&pd_core>;
			operating-points-v2 = <&disp2_dvfs_opp_table>;

			iommus = <&mc TEGRA_SWGROUP_DCB>;

			nvidia,head = <1>;

			interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>,
					<&mc TEGRA30_MC_DISPLAY0BB &emc>,
					<&mc TEGRA30_MC_DISPLAY1BB &emc>,
					<&mc TEGRA30_MC_DISPLAY0CB &emc>,
					<&mc TEGRA30_MC_DISPLAYHCB &emc>;
			interconnect-names = "wina",
					     "winb",
					     "winb-vfilter",
					     "winc",
					     "cursor";

			rgb {
				status = "disabled";
			};
		};

		hdmi@54280000 {
			compatible = "nvidia,tegra30-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_HDMI>,
				 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
			clock-names = "hdmi", "parent";
			resets = <&tegra_car 51>;
			reset-names = "hdmi";
			power-domains = <&pd_core>;
			operating-points-v2 = <&hdmi_dvfs_opp_table>;
			status = "disabled";
		};

		tvo@542c0000 {
			compatible = "nvidia,tegra30-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_TVO>;
			power-domains = <&pd_core>;
			operating-points-v2 = <&tvo_dvfs_opp_table>;
			status = "disabled";
		};

		dsi@54300000 {
			compatible = "nvidia,tegra30-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car TEGRA30_CLK_DSIA>,
				 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
			clock-names = "dsi", "parent";
			resets = <&tegra_car 48>;
			reset-names = "dsi";
			power-domains = <&pd_core>;
			operating-points-v2 = <&dsia_dvfs_opp_table>;
			status = "disabled";
		};

		dsi@54400000 {
			compatible = "nvidia,tegra30-dsi";
			reg = <0x54400000 0x00040000>;
			clocks = <&tegra_car TEGRA30_CLK_DSIB>,
				 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
			clock-names = "dsi", "parent";
			resets = <&tegra_car 84>;
			reset-names = "dsi";
			power-domains = <&pd_core>;
			operating-points-v2 = <&dsib_dvfs_opp_table>;
			status = "disabled";
		};
	};

	timer@50040600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x50040600 0x20>;
		interrupt-parent = <&intc>;
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&tegra_car TEGRA30_CLK_TWD>;
	};

	intc: interrupt-controller@50041000 {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000>,
		      <0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&intc>;
	};

	cache-controller@50043000 {
		compatible = "arm,pl310-cache";
		reg = <0x50043000 0x1000>;
		arm,data-latency = <6 6 2>;
		arm,tag-latency = <5 5 2>;
		cache-unified;
		cache-level = <2>;
	};

	lic: interrupt-controller@60004000 {
		compatible = "nvidia,tegra30-ictlr";
		reg = <0x60004000 0x100>,
		      <0x60004100 0x50>,
		      <0x60004200 0x50>,
		      <0x60004300 0x50>,
		      <0x60004400 0x50>;
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&intc>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
		reg = <0x60005000 0x400>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_TIMER>;
	};

	tegra_car: clock@60006000 {
		compatible = "nvidia,tegra30-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;

		sclk {
			compatible = "nvidia,tegra30-sclk";
			clocks = <&tegra_car TEGRA30_CLK_SCLK>;
			power-domains = <&pd_core>;
			operating-points-v2 = <&sclk_dvfs_opp_table>;
		};

		pll-c {
			compatible = "nvidia,tegra30-pllc";
			clocks = <&tegra_car TEGRA30_CLK_PLL_C>;
			power-domains = <&pd_core>;
			operating-points-v2 = <&pll_c_dvfs_opp_table>;
		};

		pll-e {
			compatible = "nvidia,tegra30-plle";
			clocks = <&tegra_car TEGRA30_CLK_PLL_E>;
			power-domains = <&pd_core>;
			operating-points-v2 = <&pll_e_dvfs_opp_table>;
		};

		pll-m {
			compatible = "nvidia,tegra30-pllm";
			clocks = <&tegra_car TEGRA30_CLK_PLL_M>;
			power-domains = <&pd_core>;
			operating-points-v2 = <&pll_m_dvfs_opp_table>;
		};
	};

	flow-controller@60007000 {
		compatible = "nvidia,tegra30-flowctrl";
		reg = <0x60007000 0x1000>;
	};

	apbdma: dma@6000a000 {
		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1400>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
		resets = <&tegra_car 34>;
		reset-names = "dma";
		#dma-cells = <1>;
	};

	ahb: ahb@6000c000 {
		compatible = "nvidia,tegra30-ahb";
		reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
	};

	actmon: actmon@6000c800 {
		compatible = "nvidia,tegra30-actmon";
		reg = <0x6000c800 0x400>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
			 <&tegra_car TEGRA30_CLK_EMC>;
		clock-names = "actmon", "emc";
		resets = <&tegra_car TEGRA30_CLK_ACTMON>;
		reset-names = "actmon";
		operating-points-v2 = <&emc_bw_dfs_opp_table>;
		interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
		interconnect-names = "cpu-read";
		#cooling-cells = <2>;
	};

	gpio: gpio@6000d000 {
		compatible = "nvidia,tegra30-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
		gpio-ranges = <&pinmux 0 0 248>;
	};

	vde@6001a000 {
		compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
		reg = <0x6001a000 0x1000>, /* Syntax Engine */
		      <0x6001b000 0x1000>, /* Video Bitstream Engine */
		      <0x6001c000  0x100>, /* Macroblock Engine */
		      <0x6001c200  0x100>, /* Post-processing Engine */
		      <0x6001c400  0x100>, /* Motion Compensation Engine */
		      <0x6001c600  0x100>, /* Transform Engine */
		      <0x6001c800  0x100>, /* Pixel prediction block */
		      <0x6001ca00  0x100>, /* Video DMA */
		      <0x6001d800  0x400>; /* Video frame controls */
		reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
			    "tfe", "ppb", "vdma", "frameid";
		iram = <&vde_pool>; /* IRAM region */
		interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
		interrupt-names = "sync-token", "bsev", "sxe";
		clocks = <&tegra_car TEGRA30_CLK_VDE>;
		reset-names = "vde", "mc";
		resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
		iommus = <&mc TEGRA_SWGROUP_VDE>;
		power-domains = <&pd_vde>;
		operating-points-v2 = <&vde_dvfs_opp_table>;
	};

	apbmisc@70000800 {
		compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
		reg = <0x70000800 0x64>, /* Chip revision */
		      <0x70000008 0x04>; /* Strapping options */
	};

	pinmux: pinmux@70000868 {
		compatible = "nvidia,tegra30-pinmux";
		reg = <0x70000868 0x0d4>, /* Pad control registers */
		      <0x70003000 0x3e4>; /* Mux registers */
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
	 * the APB DMA based serial driver, the compatible is
	 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
		resets = <&tegra_car 6>;
		reset-names = "serial";
		dmas = <&apbdma 8>, <&apbdma 8>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
		resets = <&tegra_car 7>;
		reset-names = "serial";
		dmas = <&apbdma 9>, <&apbdma 9>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
		resets = <&tegra_car 55>;
		reset-names = "serial";
		dmas = <&apbdma 10>, <&apbdma 10>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
		resets = <&tegra_car 65>;
		reset-names = "serial";
		dmas = <&apbdma 19>, <&apbdma 19>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uarte: serial@70006400 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
		resets = <&tegra_car 66>;
		reset-names = "serial";
		dmas = <&apbdma 20>, <&apbdma 20>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	gmi@70009000 {
		compatible = "nvidia,tegra30-gmi";
		reg = <0x70009000 0x1000>;
		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0x48000000 0x7ffffff>;
		clocks = <&tegra_car TEGRA30_CLK_NOR>;
		clock-names = "gmi";
		resets = <&tegra_car 42>;
		reset-names = "gmi";
		power-domains = <&pd_core>;
		operating-points-v2 = <&nor_dvfs_opp_table>;
		status = "disabled";
	};

	pwm: pwm@7000a000 {
		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car TEGRA30_CLK_PWM>;
		resets = <&tegra_car 17>;
		reset-names = "pwm";
		power-domains = <&pd_core>;
		operating-points-v2 = <&pwm_dvfs_opp_table>;
		status = "disabled";
	};

	rtc@7000e000 {
		compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_RTC>;
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_I2C1>,
			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		resets = <&tegra_car 12>;
		reset-names = "i2c";
		dmas = <&apbdma 21>, <&apbdma 21>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_I2C2>,
			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		resets = <&tegra_car 54>;
		reset-names = "i2c";
		dmas = <&apbdma 22>, <&apbdma 22>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_I2C3>,
			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		resets = <&tegra_car 67>;
		reset-names = "i2c";
		dmas = <&apbdma 23>, <&apbdma 23>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c700 0x100>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_I2C4>,
			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
		resets = <&tegra_car 103>;
		reset-names = "i2c";
		clock-names = "div-clk", "fast-clk";
		dmas = <&apbdma 26>, <&apbdma 26>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000d000 0x100>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_I2C5>,
			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		resets = <&tegra_car 47>;
		reset-names = "i2c";
		dmas = <&apbdma 24>, <&apbdma 24>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra30-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
		resets = <&tegra_car 41>;
		reset-names = "spi";
		dmas = <&apbdma 15>, <&apbdma 15>;
		dma-names = "rx", "tx";
		power-domains = <&pd_core>;
		operating-points-v2 = <&sbc1_dvfs_opp_table>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra30-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
		resets = <&tegra_car 44>;
		reset-names = "spi";
		dmas = <&apbdma 16>, <&apbdma 16>;
		dma-names = "rx", "tx";
		power-domains = <&pd_core>;
		operating-points-v2 = <&sbc2_dvfs_opp_table>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra30-slink";
		reg = <0x7000d800 0x200>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
		resets = <&tegra_car 46>;
		reset-names = "spi";
		dmas = <&apbdma 17>, <&apbdma 17>;
		dma-names = "rx", "tx";
		power-domains = <&pd_core>;
		operating-points-v2 = <&sbc3_dvfs_opp_table>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra30-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
		resets = <&tegra_car 68>;
		reset-names = "spi";
		dmas = <&apbdma 18>, <&apbdma 18>;
		dma-names = "rx", "tx";
		power-domains = <&pd_core>;
		operating-points-v2 = <&sbc4_dvfs_opp_table>;
		status = "disabled";
	};

	spi@7000dc00 {
		compatible = "nvidia,tegra30-slink";
		reg = <0x7000dc00 0x200>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
		resets = <&tegra_car 104>;
		reset-names = "spi";
		dmas = <&apbdma 27>, <&apbdma 27>;
		dma-names = "rx", "tx";
		power-domains = <&pd_core>;
		operating-points-v2 = <&sbc5_dvfs_opp_table>;
		status = "disabled";
	};

	spi@7000de00 {
		compatible = "nvidia,tegra30-slink";
		reg = <0x7000de00 0x200>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
		resets = <&tegra_car 106>;
		reset-names = "spi";
		dmas = <&apbdma 28>, <&apbdma 28>;
		dma-names = "rx", "tx";
		power-domains = <&pd_core>;
		operating-points-v2 = <&sbc6_dvfs_opp_table>;
		status = "disabled";
	};

	kbc@7000e200 {
		compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
		reg = <0x7000e200 0x100>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_KBC>;
		resets = <&tegra_car 36>;
		reset-names = "kbc";
		status = "disabled";
	};

	tegra_pmc: pmc@7000e400 {
		compatible = "nvidia,tegra30-pmc";
		reg = <0x7000e400 0x400>;
		clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
		#clock-cells = <1>;

		pd_core: core-domain {
			#power-domain-cells = <0>;
			operating-points-v2 = <&core_opp_table>;
		};

		powergates {
			pd_3d0: td {
				clocks = <&tegra_car TEGRA30_CLK_GR3D>;
				resets = <&mc TEGRA30_MC_RESET_3D>,
					 <&tegra_car TEGRA30_CLK_GR3D>;
				power-domains = <&pd_core>;
				#power-domain-cells = <0>;
			};

			pd_3d1: td2 {
				clocks = <&tegra_car TEGRA30_CLK_GR3D2>;
				resets = <&mc TEGRA30_MC_RESET_3D2>,
					 <&tegra_car TEGRA30_CLK_GR3D2>;
				power-domains = <&pd_core>;
				#power-domain-cells = <0>;
			};

			pd_venc: venc {
				clocks = <&tegra_car TEGRA30_CLK_ISP>,
					 <&tegra_car TEGRA30_CLK_VI>,
					 <&tegra_car TEGRA30_CLK_CSI>;
				resets = <&mc TEGRA30_MC_RESET_ISP>,
					 <&mc TEGRA30_MC_RESET_VI>,
					 <&tegra_car TEGRA30_CLK_ISP>,
					 <&tegra_car 20 /* VI */>,
					 <&tegra_car TEGRA30_CLK_CSI>;
				power-domains = <&pd_core>;
				#power-domain-cells = <0>;
			};

			pd_vde: vdec {
				clocks = <&tegra_car TEGRA30_CLK_VDE>;
				resets = <&mc TEGRA30_MC_RESET_VDE>,
					 <&tegra_car TEGRA30_CLK_VDE>;
				power-domains = <&pd_core>;
				#power-domain-cells = <0>;
			};

			pd_mpe: mpe {
				clocks = <&tegra_car TEGRA30_CLK_MPE>;
				resets = <&mc TEGRA30_MC_RESET_MPE>,
					 <&tegra_car TEGRA30_CLK_MPE>;
				power-domains = <&pd_core>;
				#power-domain-cells = <0>;
			};

			pd_heg: heg {
				clocks = <&tegra_car TEGRA30_CLK_GR2D>,
					 <&tegra_car TEGRA30_CLK_EPP>,
					 <&tegra_car TEGRA30_CLK_HOST1X>;
				resets = <&mc TEGRA30_MC_RESET_2D>,
					 <&mc TEGRA30_MC_RESET_EPP>,
					 <&mc TEGRA30_MC_RESET_HC>,
					 <&tegra_car TEGRA30_CLK_GR2D>,
					 <&tegra_car TEGRA30_CLK_EPP>,
					 <&tegra_car TEGRA30_CLK_HOST1X>;
				power-domains = <&pd_core>;
				#power-domain-cells = <0>;
			};
		};
	};

	mc: memory-controller@7000f000 {
		compatible = "nvidia,tegra30-mc";
		reg = <0x7000f000 0x400>;
		clocks = <&tegra_car TEGRA30_CLK_MC>;
		clock-names = "mc";

		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;
		#reset-cells = <1>;
		#interconnect-cells = <1>;
	};

	emc: memory-controller@7000f400 {
		compatible = "nvidia,tegra30-emc";
		reg = <0x7000f400 0x400>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_EMC>;
		power-domains = <&pd_core>;

		nvidia,memory-controller = <&mc>;
		operating-points-v2 = <&emc_icc_dvfs_opp_table>;

		#interconnect-cells = <0>;
	};

	fuse@7000f800 {
		compatible = "nvidia,tegra30-efuse";
		reg = <0x7000f800 0x400>;
		clocks = <&tegra_car TEGRA30_CLK_FUSE>;
		clock-names = "fuse";
		resets = <&tegra_car 39>;
		reset-names = "fuse";
		power-domains = <&pd_core>;
		operating-points-v2 = <&fuse_burn_dvfs_opp_table>;
	};

	tsensor: tsensor@70014000 {
		compatible = "nvidia,tegra30-tsensor";
		reg = <0x70014000 0x500>;
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
		resets = <&tegra_car TEGRA30_CLK_TSENSOR>;

		assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
		assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
		assigned-clock-rates = <500000>;

		#thermal-sensor-cells = <1>;
	};

	hda@70030000 {
		compatible = "nvidia,tegra30-hda";
		reg = <0x70030000 0x10000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_HDA>,
			 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
			 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
		resets = <&tegra_car 125>, /* hda */
			 <&tegra_car 128>, /* hda2hdmi */
			 <&tegra_car 111>; /* hda2codec_2x */
		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
		status = "disabled";
	};

	ahub@70080000 {
		compatible = "nvidia,tegra30-ahub";
		reg = <0x70080000 0x200>,
		      <0x70080200 0x100>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
			 <&tegra_car TEGRA30_CLK_APBIF>;
		clock-names = "d_audio", "apbif";
		resets = <&tegra_car 106>, /* d_audio */
			 <&tegra_car 107>, /* apbif */
			 <&tegra_car 30>,  /* i2s0 */
			 <&tegra_car 11>,  /* i2s1 */
			 <&tegra_car 18>,  /* i2s2 */
			 <&tegra_car 101>, /* i2s3 */
			 <&tegra_car 102>, /* i2s4 */
			 <&tegra_car 108>, /* dam0 */
			 <&tegra_car 109>, /* dam1 */
			 <&tegra_car 110>, /* dam2 */
			 <&tegra_car 10>;  /* spdif */
		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
			      "spdif";
		dmas = <&apbdma 1>, <&apbdma 1>,
		       <&apbdma 2>, <&apbdma 2>,
		       <&apbdma 3>, <&apbdma 3>,
		       <&apbdma 4>, <&apbdma 4>;
		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
			    "rx3", "tx3";
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;

		tegra_i2s0: i2s@70080300 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080300 0x100>;
			nvidia,ahub-cif-ids = <4 4>;
			clocks = <&tegra_car TEGRA30_CLK_I2S0>;
			resets = <&tegra_car 30>;
			reset-names = "i2s";
			status = "disabled";
		};

		tegra_i2s1: i2s@70080400 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080400 0x100>;
			nvidia,ahub-cif-ids = <5 5>;
			clocks = <&tegra_car TEGRA30_CLK_I2S1>;
			resets = <&tegra_car 11>;
			reset-names = "i2s";
			status = "disabled";
		};

		tegra_i2s2: i2s@70080500 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080500 0x100>;
			nvidia,ahub-cif-ids = <6 6>;
			clocks = <&tegra_car TEGRA30_CLK_I2S2>;
			resets = <&tegra_car 18>;
			reset-names = "i2s";
			status = "disabled";
		};

		tegra_i2s3: i2s@70080600 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080600 0x100>;
			nvidia,ahub-cif-ids = <7 7>;
			clocks = <&tegra_car TEGRA30_CLK_I2S3>;
			resets = <&tegra_car 101>;
			reset-names = "i2s";
			status = "disabled";
		};

		tegra_i2s4: i2s@70080700 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080700 0x100>;
			nvidia,ahub-cif-ids = <8 8>;
			clocks = <&tegra_car TEGRA30_CLK_I2S4>;
			resets = <&tegra_car 102>;
			reset-names = "i2s";
			status = "disabled";
		};
	};

	mmc@78000000 {
		compatible = "nvidia,tegra30-sdhci";
		reg = <0x78000000 0x200>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
		clock-names = "sdhci";
		resets = <&tegra_car 14>;
		reset-names = "sdhci";
		power-domains = <&pd_core>;
		operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
		status = "disabled";
	};

	mmc@78000200 {
		compatible = "nvidia,tegra30-sdhci";
		reg = <0x78000200 0x200>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
		clock-names = "sdhci";
		resets = <&tegra_car 9>;
		reset-names = "sdhci";
		status = "disabled";
	};

	mmc@78000400 {
		compatible = "nvidia,tegra30-sdhci";
		reg = <0x78000400 0x200>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
		clock-names = "sdhci";
		resets = <&tegra_car 69>;
		reset-names = "sdhci";
		power-domains = <&pd_core>;
		operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
		status = "disabled";
	};

	mmc@78000600 {
		compatible = "nvidia,tegra30-sdhci";
		reg = <0x78000600 0x200>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
		clock-names = "sdhci";
		resets = <&tegra_car 15>;
		reset-names = "sdhci";
		status = "disabled";
	};

	usb@7d000000 {
		compatible = "nvidia,tegra30-ehci";
		reg = <0x7d000000 0x4000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA30_CLK_USBD>;
		resets = <&tegra_car 22>;
		reset-names = "usb";
		nvidia,needs-double-reset;
		nvidia,phy = <&phy1>;
		power-domains = <&pd_core>;
		operating-points-v2 = <&usbd_dvfs_opp_table>;
		status = "disabled";
	};

	phy1: usb-phy@7d000000 {
		compatible = "nvidia,tegra30-usb-phy";
		reg = <0x7d000000 0x4000>,
		      <0x7d000000 0x4000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA30_CLK_USBD>,
			 <&tegra_car TEGRA30_CLK_PLL_U>,
			 <&tegra_car TEGRA30_CLK_USBD>;
		clock-names = "reg", "pll_u", "utmi-pads";
		resets = <&tegra_car 22>, <&tegra_car 22>;
		reset-names = "usb", "utmi-pads";
		#phy-cells = <0>;
		nvidia,hssync-start-delay = <9>;
		nvidia,idle-wait-delay = <17>;
		nvidia,elastic-limit = <16>;
		nvidia,term-range-adj = <6>;
		nvidia,xcvr-setup = <51>;
		nvidia,xcvr-setup-use-fuses;
		nvidia,xcvr-lsfslew = <1>;
		nvidia,xcvr-lsrslew = <1>;
		nvidia,xcvr-hsslew = <32>;
		nvidia,hssquelch-level = <2>;
		nvidia,hsdiscon-level = <5>;
		nvidia,has-utmi-pad-registers;
		nvidia,pmc = <&tegra_pmc 0>;
		status = "disabled";
	};

	usb@7d004000 {
		compatible = "nvidia,tegra30-ehci";
		reg = <0x7d004000 0x4000>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA30_CLK_USB2>;
		resets = <&tegra_car 58>;
		reset-names = "usb";
		nvidia,phy = <&phy2>;
		power-domains = <&pd_core>;
		operating-points-v2 = <&usb2_dvfs_opp_table>;
		status = "disabled";
	};

	phy2: usb-phy@7d004000 {
		compatible = "nvidia,tegra30-usb-phy";
		reg = <0x7d004000 0x4000>,
		      <0x7d000000 0x4000>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA30_CLK_USB2>,
			 <&tegra_car TEGRA30_CLK_PLL_U>,
			 <&tegra_car TEGRA30_CLK_USBD>;
		clock-names = "reg", "pll_u", "utmi-pads";
		resets = <&tegra_car 58>, <&tegra_car 22>;
		reset-names = "usb", "utmi-pads";
		#phy-cells = <0>;
		nvidia,hssync-start-delay = <9>;
		nvidia,idle-wait-delay = <17>;
		nvidia,elastic-limit = <16>;
		nvidia,term-range-adj = <6>;
		nvidia,xcvr-setup = <51>;
		nvidia,xcvr-setup-use-fuses;
		nvidia,xcvr-lsfslew = <2>;
		nvidia,xcvr-lsrslew = <2>;
		nvidia,xcvr-hsslew = <32>;
		nvidia,hssquelch-level = <2>;
		nvidia,hsdiscon-level = <5>;
		nvidia,pmc = <&tegra_pmc 2>;
		status = "disabled";
	};

	usb@7d008000 {
		compatible = "nvidia,tegra30-ehci";
		reg = <0x7d008000 0x4000>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA30_CLK_USB3>;
		resets = <&tegra_car 59>;
		reset-names = "usb";
		nvidia,phy = <&phy3>;
		power-domains = <&pd_core>;
		operating-points-v2 = <&usb3_dvfs_opp_table>;
		status = "disabled";
	};

	phy3: usb-phy@7d008000 {
		compatible = "nvidia,tegra30-usb-phy";
		reg = <0x7d008000 0x4000>,
		      <0x7d000000 0x4000>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA30_CLK_USB3>,
			 <&tegra_car TEGRA30_CLK_PLL_U>,
			 <&tegra_car TEGRA30_CLK_USBD>;
		clock-names = "reg", "pll_u", "utmi-pads";
		resets = <&tegra_car 59>, <&tegra_car 22>;
		reset-names = "usb", "utmi-pads";
		#phy-cells = <0>;
		nvidia,hssync-start-delay = <0>;
		nvidia,idle-wait-delay = <17>;
		nvidia,elastic-limit = <16>;
		nvidia,term-range-adj = <6>;
		nvidia,xcvr-setup = <51>;
		nvidia,xcvr-setup-use-fuses;
		nvidia,xcvr-lsfslew = <2>;
		nvidia,xcvr-lsrslew = <2>;
		nvidia,xcvr-hsslew = <32>;
		nvidia,hssquelch-level = <2>;
		nvidia,hsdiscon-level = <5>;
		nvidia,pmc = <&tegra_pmc 1>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
			#cooling-cells = <2>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&{/cpus/cpu@0}>,
				     <&{/cpus/cpu@1}>,
				     <&{/cpus/cpu@2}>,
				     <&{/cpus/cpu@3}>;
	};

	thermal-zones {
		tsensor0-thermal {
			polling-delay-passive = <1000>; /* milliseconds */
			polling-delay = <5000>; /* milliseconds */

			thermal-sensors = <&tsensor 0>;

			trips {
				level1_trip: dvfs-alert {
					/* throttle at 80C until temperature drops to 79.8C */
					temperature = <80000>;
					hysteresis = <200>;
					type = "passive";
				};

				level2_trip: cpu-div2-throttle {
					/* hardware CPU x2 freq throttle at 85C */
					temperature = <85000>;
					hysteresis = <200>;
					type = "hot";
				};

				level3_trip: soc-critical {
					/* hardware shut down at 90C */
					temperature = <90000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&level1_trip>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		tsensor1-thermal {
			status = "disabled";

			polling-delay-passive = <1000>; /* milliseconds */
			polling-delay = <0>; /* milliseconds */

			thermal-sensors = <&tsensor 1>;

			trips {
				dvfs-alert {
					temperature = <80000>;
					hysteresis = <200>;
					type = "passive";
				};
			};
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board
 *
 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */
/dts-v1/;
#include "at91sam9260.dtsi"
#include "tny_a9260_common.dtsi"

/ {
	model = "Calao TNY A9260";
	compatible = "calao,tny-a9260", "atmel,at91sam9260", "atmel,at91sam9";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board
 *
 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */

/ {
	chosen {
		bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs";
	};

	memory@20000000 {
		reg = <0x20000000 0x4000000>;
	};

	clocks {
		slow_xtal {
			clock-frequency = <32768>;
		};

		main_xtal {
			clock-frequency = <12000000>;
		};
	};

	ahb {
		apb {
			tcb0: timer@fffa0000 {
				timer@0 {
					compatible = "atmel,tcb-timer";
					reg = <0>, <1>;
				};

				timer@2 {
					compatible = "atmel,tcb-timer";
					reg = <2>;
				};
			};

			dbgu: serial@fffff200 {
				status = "okay";
			};
		};

		ebi: ebi@10000000 {
			status = "okay";

			nand_controller: nand-controller {
				status = "okay";
				pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
				pinctrl-names = "default";

				nand@3 {
					reg = <0x3 0x0 0x800000>;
					rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
					cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
					nand-bus-width = <8>;
					nand-ecc-mode = "soft";
					nand-on-flash-bbt;
					label = "atmel_nand";

					partitions {
						compatible = "fixed-partitions";
						#address-cells = <1>;
						#size-cells = <1>;

						at91bootstrap@0 {
							label = "at91bootstrap";
							reg = <0x0 0x20000>;
						};

						barebox@20000 {
							label = "barebox";
							reg = <0x20000 0x40000>;
						};

						bareboxenv@60000 {
							label = "bareboxenv";
							reg = <0x60000 0x20000>;
						};

						bareboxenv2@80000 {
							label = "bareboxenv2";
							reg = <0x80000 0x20000>;
						};

						oftree@80000 {
							label = "oftree";
							reg = <0xa0000 0x20000>;
						};

						kernel@a0000 {
							label = "kernel";
							reg = <0xc0000 0x400000>;
						};

						rootfs@4a0000 {
							label = "rootfs";
							reg = <0x4c0000 0x7800000>;
						};

						data@7ca0000 {
							label = "data";
							reg = <0x7cc0000 0x8340000>;
						};
					};
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * usb_a9263.dts - Device Tree file for Caloa USB A9293 board
 *
 *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */
/dts-v1/;
#include "at91sam9263.dtsi"

/ {
	model = "Calao TNY A9263";
	compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9";

	chosen {
		bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
	};

	memory@20000000 {
		reg = <0x20000000 0x4000000>;
	};

	clocks {
		slow_xtal {
			clock-frequency = <32768>;
		};

		main_xtal {
			clock-frequency = <12000000>;
		};
	};

	ahb {
		apb {
			dbgu: serial@ffffee00 {
				status = "okay";
			};

			tcb0: timer@fff7c000 {
				timer@0 {
					compatible = "atmel,tcb-timer";
					reg = <0>, <1>;
				};

				timer@2 {
					compatible = "atmel,tcb-timer";
					reg = <2>;
				};
			};

			usb1: gadget@fff78000 {
				atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>;
				status = "okay";
			};
		};

		ebi0: ebi@10000000 {
			status = "okay";

			nand_controller: nand-controller {
				status = "okay";
				pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
				pinctrl-names = "default";

				nand@3 {
					reg = <0x3 0x0 0x800000>;
					rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>;
					cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>;
					nand-bus-width = <8>;
					nand-ecc-mode = "soft";
					nand-on-flash-bbt;
					label = "atmel_nand";

					partitions {
						compatible = "fixed-partitions";
						#address-cells = <1>;
						#size-cells = <1>;

						at91bootstrap@0 {
							label = "at91bootstrap";
							reg = <0x0 0x20000>;
						};

						barebox@20000 {
							label = "barebox";
							reg = <0x20000 0x40000>;
						};

						bareboxenv@60000 {
							label = "bareboxenv";
							reg = <0x60000 0x20000>;
						};

						bareboxenv2@80000 {
							label = "bareboxenv2";
							reg = <0x80000 0x20000>;
						};

						oftree@80000 {
							label = "oftree";
							reg = <0xa0000 0x20000>;
						};

						kernel@a0000 {
							label = "kernel";
							reg = <0xc0000 0x400000>;
						};

						rootfs@4a0000 {
							label = "rootfs";
							reg = <0x4c0000 0x7800000>;
						};

						data@7ca0000 {
							label = "data";
							reg = <0x7cc0000 0x8340000>;
						};
					};
				};
			};
		};
	};

	i2c-gpio-0 {
		status = "okay";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board
 *
 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */
/dts-v1/;
#include "at91sam9g20.dtsi"
#include "tny_a9260_common.dtsi"

/ {
	model = "Calao TNY A9G20";
	compatible = "calao,tny-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 */

/*
 * Integrated Power Management Chip
 * http://www.ti.com/lit/ds/symlink/tps65070.pdf
 */

&tps {
	compatible = "ti,tps6507x";

	regulators {
		#address-cells = <1>;
		#size-cells = <0>;

		vdcdc1_reg: regulator@0 {
			reg = <0>;
			regulator-compatible = "VDCDC1";
		};

		vdcdc2_reg: regulator@1 {
			reg = <1>;
			regulator-compatible = "VDCDC2";
		};

		vdcdc3_reg: regulator@2 {
			reg = <2>;
			regulator-compatible = "VDCDC3";
		};

		ldo1_reg: regulator@3 {
			reg = <3>;
			regulator-compatible = "LDO1";
		};

		ldo2_reg: regulator@4 {
			reg = <4>;
			regulator-compatible = "LDO2";
		};

	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 */

/*
 * Integrated Power Management Chip
 * http://www.ti.com/lit/ds/symlink/tps65217.pdf
 */

&tps {
	compatible = "ti,tps65217";
	interrupt-controller;
	#interrupt-cells = <1>;

	charger {
		compatible = "ti,tps65217-charger";
		interrupts = <0>, <1>;
		interrupt-names = "USB", "AC";
		status = "disabled";
	};

	pwrbutton {
		compatible = "ti,tps65217-pwrbutton";
		interrupts = <2>;
		status = "disabled";
	};

	regulators {
		#address-cells = <1>;
		#size-cells = <0>;

		dcdc1_reg: regulator@0 {
			reg = <0>;
			regulator-compatible = "dcdc1";
		};

		dcdc2_reg: regulator@1 {
			reg = <1>;
			regulator-compatible = "dcdc2";
		};

		dcdc3_reg: regulator@2 {
			reg = <2>;
			regulator-compatible = "dcdc3";
		};

		ldo1_reg: regulator@3 {
			reg = <3>;
			regulator-compatible = "ldo1";
		};

		ldo2_reg: regulator@4 {
			reg = <4>;
			regulator-compatible = "ldo2";
		};

		ldo3_reg: regulator@5 {
			reg = <5>;
			regulator-compatible = "ldo3";
		};

		ldo4_reg: regulator@6 {
			reg = <6>;
			regulator-compatible = "ldo4";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 */

/*
 * Integrated Power Management Chip
 * http://www.ti.com/lit/ds/symlink/tps65910.pdf
 */

&tps {
	compatible = "ti,tps65910";

	regulators {
		#address-cells = <1>;
		#size-cells = <0>;

		vrtc_reg: regulator@0 {
			reg = <0>;
			regulator-compatible = "vrtc";
		};

		vio_reg: regulator@1 {
			reg = <1>;
			regulator-compatible = "vio";
		};

		vdd1_reg: regulator@2 {
			reg = <2>;
			regulator-compatible = "vdd1";
		};

		vdd2_reg: regulator@3 {
			reg = <3>;
			regulator-compatible = "vdd2";
		};

		vdd3_reg: regulator@4 {
			reg = <4>;
			regulator-compatible = "vdd3";
		};

		vdig1_reg: regulator@5 {
			reg = <5>;
			regulator-compatible = "vdig1";
		};

		vdig2_reg: regulator@6 {
			reg = <6>;
			regulator-compatible = "vdig2";
		};

		vpll_reg: regulator@7 {
			reg = <7>;
			regulator-compatible = "vpll";
		};

		vdac_reg: regulator@8 {
			reg = <8>;
			regulator-compatible = "vdac";
		};

		vaux1_reg: regulator@9 {
			reg = <9>;
			regulator-compatible = "vaux1";
		};

		vaux2_reg: regulator@10 {
			reg = <10>;
			regulator-compatible = "vaux2";
		};

		vaux33_reg: regulator@11 {
			reg = <11>;
			regulator-compatible = "vaux33";
		};

		vmmc_reg: regulator@12 {
			reg = <12>;
			regulator-compatible = "vmmc";
		};

		vbb_reg: regulator@13 {
			reg = <13>;
			regulator-compatible = "vbb";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 */

/*
 * Integrated Power Management Chip
 */
&twl {
	compatible = "ti,twl4030";
	interrupt-controller;
	#interrupt-cells = <1>;

	rtc {
		compatible = "ti,twl4030-rtc";
		interrupts = <11>;
	};

	charger: bci {
		compatible = "ti,twl4030-bci";
		interrupts = <9>, <2>;
		bci3v1-supply = <&vusb3v1>;
		io-channels = <&twl_madc 11>;
		io-channel-names = "vac";
	};

	watchdog {
		compatible = "ti,twl4030-wdt";
	};

	vaux1: regulator-vaux1 {
		compatible = "ti,twl4030-vaux1";
	};

	vaux2: regulator-vaux2 {
		compatible = "ti,twl4030-vaux2";
	};

	vaux3: regulator-vaux3 {
		compatible = "ti,twl4030-vaux3";
	};

	vaux4: regulator-vaux4 {
		compatible = "ti,twl4030-vaux4";
	};

	vcc: regulator-vdd1 {
		compatible = "ti,twl4030-vdd1";
		regulator-min-microvolt = <600000>;
		regulator-max-microvolt = <1450000>;
	};

	vdac: regulator-vdac {
		compatible = "ti,twl4030-vdac";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	vio: regulator-vio {
		compatible = "ti,twl4030-vio";
	};

	vintana1: regulator-vintana1 {
		compatible = "ti,twl4030-vintana1";
	};

	vintana2: regulator-vintana2 {
		compatible = "ti,twl4030-vintana2";
	};

	vintdig: regulator-vintdig {
		compatible = "ti,twl4030-vintdig";
	};

	vmmc1: regulator-vmmc1 {
		compatible = "ti,twl4030-vmmc1";
		regulator-min-microvolt = <1850000>;
		regulator-max-microvolt = <3150000>;
	};

	vmmc2: regulator-vmmc2 {
		compatible = "ti,twl4030-vmmc2";
		regulator-min-microvolt = <1850000>;
		regulator-max-microvolt = <3150000>;
	};

	vusb1v5: regulator-vusb1v5 {
		compatible = "ti,twl4030-vusb1v5";
	};

	vusb1v8: regulator-vusb1v8 {
		compatible = "ti,twl4030-vusb1v8";
	};

	vusb3v1: regulator-vusb3v1 {
		compatible = "ti,twl4030-vusb3v1";
	};

	vpll1: regulator-vpll1 {
		compatible = "ti,twl4030-vpll1";
	};

	vpll2: regulator-vpll2 {
		compatible = "ti,twl4030-vpll2";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	vsim: regulator-vsim {
		compatible = "ti,twl4030-vsim";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3000000>;
	};

	twl_gpio: gpio {
		compatible = "ti,twl4030-gpio";
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <1>;
	};

	usb2_phy: twl4030-usb {
		compatible = "ti,twl4030-usb";
		interrupts = <10>, <4>;
		usb1v5-supply = <&vusb1v5>;
		usb1v8-supply = <&vusb1v8>;
		usb3v1-supply = <&vusb3v1>;
		usb_mode = <1>;
		#phy-cells = <0>;
	};

	twl_pwm: pwm {
		compatible = "ti,twl4030-pwm";
		#pwm-cells = <2>;
	};

	twl_pwmled: pwmled {
		compatible = "ti,twl4030-pwmled";
		#pwm-cells = <2>;
	};

	twl_pwrbutton: pwrbutton {
		compatible = "ti,twl4030-pwrbutton";
		interrupts = <8>;
	};

	twl_keypad: keypad {
		compatible = "ti,twl4030-keypad";
		interrupts = <1>;
		keypad,num-rows = <8>;
		keypad,num-columns = <8>;
	};

	twl_madc: madc {
		compatible = "ti,twl4030-madc";
		interrupts = <3>;
		#io-channel-cells = <1>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013 Linaro, Ltd.
 */

&twl {
	pinctrl-names = "default";
	pinctrl-0 = <&twl4030_pins &twl4030_vpins>;
};

&omap3_pmx_core {
	/*
	 * On most OMAP3 platforms, the twl4030 IRQ line is connected
	 * to the SYS_NIRQ line on OMAP.  Therefore, configure the
	 * defaults for the SYS_NIRQ pin here.
	 */
	twl4030_pins: pinmux_twl4030_pins {
		pinctrl-single,pins = <
			OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */
		>;
	};
};

/*
 * If your board is not using the I2C4 pins with twl4030, then don't include
 * this file. For proper idle mode signaling with sys_clkreq and sys_off_mode
 * pins we need to configure I2C4, or else use the legacy sys_nvmode1 and
 * sys_nvmode2 signaling.
 */
&omap3_pmx_wkup {
	twl4030_vpins: pinmux_twl4030_vpins {
		pinctrl-single,pins = <
			OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0)		/* i2c4_scl.i2c4_scl */
			OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0)		/* i2c4_sda.i2c4_sda */
			OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0)	/* sys_clkreq.sys_clkreq */
			OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0)	/* sys_off_mode.sys_off_mode */
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 */

/*
 * Integrated Power Management Chip
 * http://www.ti.com/lit/ds/symlink/twl6030.pdf
 */
&twl {
	compatible = "ti,twl6030";
	interrupt-controller;
	#interrupt-cells = <1>;

	rtc {
		compatible = "ti,twl4030-rtc";
		interrupts = <11>;
	};

	vaux1: regulator-vaux1 {
		compatible = "ti,twl6030-vaux1";
		regulator-min-microvolt = <1000000>;
		regulator-max-microvolt = <3000000>;
	};

	vaux2: regulator-vaux2 {
		compatible = "ti,twl6030-vaux2";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <2800000>;
	};

	vaux3: regulator-vaux3 {
		compatible = "ti,twl6030-vaux3";
		regulator-min-microvolt = <1000000>;
		regulator-max-microvolt = <3000000>;
	};

	vmmc: regulator-vmmc {
		compatible = "ti,twl6030-vmmc";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <3000000>;
	};

	vpp: regulator-vpp {
		compatible = "ti,twl6030-vpp";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <2500000>;
	};

	vusim: regulator-vusim {
		compatible = "ti,twl6030-vusim";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <2900000>;
	};

	vdac: regulator-vdac {
		compatible = "ti,twl6030-vdac";
	};

	vana: regulator-vana {
		compatible = "ti,twl6030-vana";
	};

	vcxio: regulator-vcxio {
		compatible = "ti,twl6030-vcxio";
		regulator-always-on;
	};

	vusb: regulator-vusb {
		compatible = "ti,twl6030-vusb";
	};

	v1v8: regulator-v1v8 {
		compatible = "ti,twl6030-v1v8";
		regulator-always-on;
	};

	v2v1: regulator-v2v1 {
		compatible = "ti,twl6030-v2v1";
		regulator-always-on;
	};

	twl_usb_comparator: usb-comparator {
		compatible = "ti,twl6030-usb";
		interrupts = <4>, <10>;
	};

	twl_pwm: pwm {
		/* provides two PWMs (id 0, 1 for PWM1 and PWM2) */
		compatible = "ti,twl6030-pwm";
		#pwm-cells = <2>;
	};

	twl_pwmled: pwmled {
		/* provides one PWM (id 0 for Charging indicator LED) */
		compatible = "ti,twl6030-pwmled";
		#pwm-cells = <2>;
	};

	gpadc {
		compatible = "ti,twl6030-gpadc";
		interrupts = <3>;
		#io-channel-cells = <1>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 */

&twl {
	/*
	 * On most OMAP4 platforms, the twl6030 IRQ line is connected
	 * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is
	 * connected to the fref_clk0_out.sys_drm_msecure line.
	 * Therefore, configure the defaults for the SYS_NIRQ1 and
	 * fref_clk0_out.sys_drm_msecure pins here.
	 */
	pinctrl-names = "default";
	pinctrl-0 = <
		&twl6030_pins
		&twl6030_wkup_pins
	>;
};

&omap4_pmx_wkup {
	twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2)		/* fref_clk0_out.sys_drm_msecure */
		>;
	};
};

&omap4_pmx_core {
	twl6030_pins: pinmux_twl6030_pins {
		pinctrl-single,pins = <
			OMAP4_IOPAD(0x19e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0)	/* sys_nirq1.sys_nirq1 */
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD4 Reference Board
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

/dts-v1/;
#include "uniphier-ld4.dtsi"
#include "uniphier-ref-daughter.dtsi"
#include "uniphier-support-card.dtsi"

/ {
	model = "UniPhier LD4 Reference Board";
	compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &serial0;
		serial1 = &serialsc;
		serial2 = &serial2;
		serial3 = &serial3;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};
};

&ethsc {
	interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};

&serialsc {
	interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};

&serial0 {
	status = "okay";
};

&serial2 {
	status = "okay";
};

&serial3 {
	status = "okay";
};

&gpio {
	xirq1-hog {
		gpio-hog;
		gpios = <UNIPHIER_GPIO_IRQ(1) 0>;
		input;
	};
};

&i2c0 {
	status = "okay";
};

&sd {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&nand {
	status = "okay";

	nand@0 {
		reg = <0>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD4 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "socionext,uniphier-ld4";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24576000>;
		};

		arm_timer_clk: arm-timer {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		l2: cache-controller@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
			      <0x506c0000 0x400>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-size = <(512 * 1024)>;
			cache-sets = <256>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		spi: spi@54006000 {
			compatible = "socionext,uniphier-scssi";
			status = "disabled";
			reg = <0x54006000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi0>;
			clocks = <&peri_clk 11>;
			resets = <&peri_rst 11>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			resets = <&peri_rst 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			resets = <&peri_rst 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			resets = <&peri_rst 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			resets = <&peri_rst 3>;
		};

		gpio: gpio@55000000 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000000 0x200>;
			interrupt-parent = <&aidet>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 0>;
			gpio-ranges-group-names = "gpio_range";
			ngpios = <136>;
			socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
		};

		i2c0: i2c@58400000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58400000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			resets = <&peri_rst 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58480000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58480000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			resets = <&peri_rst 5>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c2: i2c@58500000 {
			compatible = "socionext,uniphier-i2c";
			reg = <0x58500000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			clocks = <&peri_clk 6>;
			resets = <&peri_rst 6>;
			clock-frequency = <400000>;
		};

		i2c3: i2c@58580000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58580000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			resets = <&peri_rst 7>;
			clock-frequency = <100000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		mioctrl@59810000 {
			compatible = "socionext,uniphier-ld4-mioctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x800>;

			mio_clk: clock {
				compatible = "socionext,uniphier-ld4-mio-clock";
				#clock-cells = <1>;
			};

			mio_rst: reset {
				compatible = "socionext,uniphier-ld4-mio-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-ld4-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-ld4-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-ld4-peri-reset";
				#reset-cells = <1>;
			};
		};

		dmac: dma-controller@5a000000 {
			compatible = "socionext,uniphier-mio-dmac";
			reg = <0x5a000000 0x1000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mio_clk 7>;
			resets = <&mio_rst 7>;
			#dma-cells = <1>;
		};

		sd: mmc@5a400000 {
			compatible = "socionext,uniphier-sd-v2.91";
			status = "disabled";
			reg = <0x5a400000 0x200>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default", "uhs";
			pinctrl-0 = <&pinctrl_sd>;
			pinctrl-1 = <&pinctrl_sd_uhs>;
			clocks = <&mio_clk 0>;
			reset-names = "host", "bridge";
			resets = <&mio_rst 0>, <&mio_rst 3>;
			dma-names = "rx-tx";
			dmas = <&dmac 4>;
			bus-width = <4>;
			cap-sd-highspeed;
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
		};

		emmc: mmc@5a500000 {
			compatible = "socionext,uniphier-sd-v2.91";
			status = "disabled";
			reg = <0x5a500000 0x200>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc>;
			clocks = <&mio_clk 1>;
			reset-names = "host", "bridge", "hw";
			resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
			dma-names = "rx-tx";
			dmas = <&dmac 6>;
			bus-width = <8>;
			cap-mmc-highspeed;
			cap-mmc-hw-reset;
			non-removable;
		};

		usb0: usb@5a800100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a800100 0x100>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
				 <&mio_clk 12>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
				 <&mio_rst 12>;
			has-transaction-translator;
		};

		usb1: usb@5a810100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a810100 0x100>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
				 <&mio_clk 13>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
				 <&mio_rst 13>;
			has-transaction-translator;
		};

		usb2: usb@5a820100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a820100 0x100>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb2>;
			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
				 <&mio_clk 14>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
				 <&mio_rst 14>;
			has-transaction-translator;
		};

		soc-glue@5f800000 {
			compatible = "socionext,uniphier-ld4-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-ld4-pinctrl";
			};
		};

		soc-glue@5f900000 {
			compatible = "socionext,uniphier-ld4-soc-glue-debug",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x5f900000 0x2000>;

			efuse@100 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x100 0x28>;
			};

			efuse@130 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x130 0x8>;
			};
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <GIC_PPI 11
				(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		aidet: interrupt-controller@61830000 {
			compatible = "socionext,uniphier-ld4-aidet";
			reg = <0x61830000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-ld4-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-ld4-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-ld4-reset";
				#reset-cells = <1>;
			};
		};

		nand: nand-controller@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5a";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			clock-names = "nand", "nand_x", "ecc";
			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
			reset-names = "nand", "reg";
			resets = <&sys_rst 2>, <&sys_rst 2>;
		};
	};
};

#include "uniphier-pinctrl.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD6b Reference Board
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

/dts-v1/;
#include "uniphier-ld6b.dtsi"
#include "uniphier-ref-daughter.dtsi"
#include "uniphier-support-card.dtsi"

/ {
	model = "UniPhier LD6b Reference Board";
	compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serialsc;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		ethernet0 = ð
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x80000000>;
	};
};

&ethsc {
	interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};

&serialsc {
	interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};

&serial0 {
	status = "okay";
};

&serial1 {
	status = "okay";
};

&serial2 {
	status = "okay";
};

&gpio {
	xirq4-hog {
		gpio-hog;
		gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
		input;
	};
};

&i2c0 {
	status = "okay";
};

&sd {
	status = "okay";
};

&eth {
	status = "okay";
	phy-handle = <&ethphy>;
};

&mdio {
	ethphy: ethernet-phy@0 {
		reg = <0>;
	};
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&nand {
	status = "okay";

	nand@0 {
		reg = <0>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier LD6b SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

/*
 * LD6b consists of two silicon dies: D-chip and A-chip.
 * The D-chip (digital chip) is the same as the PXs2 die.
 * Reuse the PXs2 device tree with some properties overridden.
 */
#include "uniphier-pxs2.dtsi"

/ {
	compatible = "socionext,uniphier-ld6b";
};

/* UART3 unavailable: the pads are not wired to the package balls */
&serial3 {
	status = "disabled";
};

/*
 * LD6b and PXs2 have completely different packages,
 * which makes the pinctrl driver unshareable.
 */
&pinctrl {
	compatible = "socionext,uniphier-ld6b-pinctrl";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier SoCs default pinctrl settings
//
// Copyright (C) 2015-2017 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

&pinctrl {
	pinctrl_aout: aout {
		groups = "aout";
		function = "aout";
	};

	pinctrl_ain1: ain1 {
		groups = "ain1";
		function = "ain1";
	};

	pinctrl_ain2: ain2 {
		groups = "ain2";
		function = "ain2";
	};

	pinctrl_ainiec1: ainiec1 {
		groups = "ainiec1";
		function = "ainiec1";
	};

	pinctrl_aout1: aout1 {
		groups = "aout1";
		function = "aout1";
	};

	pinctrl_aout2: aout2 {
		groups = "aout2";
		function = "aout2";
	};

	pinctrl_aout3: aout3 {
		groups = "aout3";
		function = "aout3";
	};

	pinctrl_aoutiec1: aoutiec1 {
		groups = "aoutiec1";
		function = "aoutiec1";
	};

	pinctrl_aoutiec2: aoutiec2 {
		groups = "aoutiec2";
		function = "aoutiec2";
	};

	pinctrl_emmc: emmc {
		groups = "emmc", "emmc_dat8";
		function = "emmc";
	};

	pinctrl_ether_mii: ether-mii {
		groups = "ether_mii";
		function = "ether_mii";
	};

	pinctrl_ether_rgmii: ether-rgmii {
		groups = "ether_rgmii";
		function = "ether_rgmii";
	};

	pinctrl_ether_rmii: ether-rmii {
		groups = "ether_rmii";
		function = "ether_rmii";
	};

	pinctrl_ether1_rgmii: ether1-rgmii {
		groups = "ether1_rgmii";
		function = "ether1_rgmii";
	};

	pinctrl_ether1_rmii: ether1-rmii {
		groups = "ether1_rmii";
		function = "ether1_rmii";
	};

	pinctrl_i2c0: i2c0 {
		groups = "i2c0";
		function = "i2c0";
	};

	pinctrl_i2c1: i2c1 {
		groups = "i2c1";
		function = "i2c1";
	};

	pinctrl_i2c2: i2c2 {
		groups = "i2c2";
		function = "i2c2";
	};

	pinctrl_i2c3: i2c3 {
		groups = "i2c3";
		function = "i2c3";
	};

	pinctrl_i2c4: i2c4 {
		groups = "i2c4";
		function = "i2c4";
	};

	pinctrl_i2c5: i2c5 {
		groups = "i2c5";
		function = "i2c5";
	};

	pinctrl_i2c6: i2c6 {
		groups = "i2c6";
		function = "i2c6";
	};

	pinctrl_nand: nand {
		groups = "nand";
		function = "nand";
	};

	pinctrl_nand2cs: nand2cs {
		groups = "nand", "nand_cs1";
		function = "nand";
	};

	pinctrl_pcie: pcie {
		groups = "pcie";
		function = "pcie";
	};

	pinctrl_sd: sd {
		groups = "sd";
		function = "sd";
	};

	pinctrl_sd_uhs: sd-uhs {
		groups = "sd";
		function = "sd";
	};

	pinctrl_sd1: sd1 {
		groups = "sd1";
		function = "sd1";
	};

	pinctrl_spi0: spi0 {
		groups = "spi0";
		function = "spi0";
	};

	pinctrl_spi1: spi1 {
		groups = "spi1";
		function = "spi1";
	};

	pinctrl_spi2: spi2 {
		groups = "spi2";
		function = "spi2";
	};

	pinctrl_spi3: spi3 {
		groups = "spi3";
		function = "spi3";
	};

	pinctrl_system_bus: system-bus {
		groups = "system_bus", "system_bus_cs1";
		function = "system_bus";
	};

	pinctrl_uart0: uart0 {
		groups = "uart0";
		function = "uart0";
	};

	pinctrl_uart1: uart1 {
		groups = "uart1";
		function = "uart1";
	};

	pinctrl_uart2: uart2 {
		groups = "uart2";
		function = "uart2";
	};

	pinctrl_uart3: uart3 {
		groups = "uart3";
		function = "uart3";
	};

	pinctrl_usb0: usb0 {
		groups = "usb0";
		function = "usb0";
	};

	pinctrl_usb0_device: usb0-device {
		groups = "usb0_device";
		function = "usb0";
	};

	pinctrl_usb1: usb1 {
		groups = "usb1";
		function = "usb1";
	};

	pinctrl_usb1_device: usb1-device {
		groups = "usb1_device";
		function = "usb1";
	};

	pinctrl_usb2: usb2 {
		groups = "usb2";
		function = "usb2";
	};

	pinctrl_usb3: usb3 {
		groups = "usb3";
		function = "usb3";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Pro4 Ace Board
//
// Copyright (C) 2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

/dts-v1/;
#include "uniphier-pro4.dtsi"

/ {
	model = "UniPhier Pro4 Ace Board";
	compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		ethernet0 = ð
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};
};

&serial0 {
	status = "okay";
};

&serial1 {
	status = "okay";
};

&serial2 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	eeprom@54 {
		compatible = "st,24c64", "atmel,24c64";
		reg = <0x54>;
		pagesize = <32>;
	};
};

&i2c1 {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&i2c3 {
	status = "okay";
};

&sd {
	status = "okay";
};

&usb2 {
	status = "okay";
};

&usb3 {
	status = "okay";
};

&eth {
	status = "okay";
	phy-handle = <&ethphy>;
};

&mdio {
	ethphy: ethernet-phy@1 {
		reg = <1>;
	};
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&ahci0 {
	status = "okay";
};

&ahci1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Pro4 Reference Board
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

/dts-v1/;
#include "uniphier-pro4.dtsi"
#include "uniphier-ref-daughter.dtsi"
#include "uniphier-support-card.dtsi"

/ {
	model = "UniPhier Pro4 Reference Board";
	compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serialsc;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		ethernet0 = ð
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};
};

&ethsc {
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
};

&serialsc {
	interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
};

&serial0 {
	status = "okay";
};

&serial1 {
	status = "okay";
};

&serial2 {
	status = "okay";
};

&gpio {
	xirq2-hog {
		gpio-hog;
		gpios = <UNIPHIER_GPIO_IRQ(2) 0>;
		input;
	};
};

&i2c0 {
	status = "okay";
};

&sd {
	status = "okay";
};

&usb2 {
	status = "okay";
};

&usb3 {
	status = "okay";
};

&eth {
	status = "okay";
	phy-handle = <&ethphy>;
};

&mdio {
	ethphy: ethernet-phy@0 {
		reg = <0>;
	};
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&nand {
	status = "okay";

	nand@0 {
		reg = <0>;
	};
};

&ahci0 {
	status = "okay";
};

&ahci1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Pro4 Sanji Board
//
// Copyright (C) 2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

/dts-v1/;
#include "uniphier-pro4.dtsi"

/ {
	model = "UniPhier Pro4 Sanji Board";
	compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		ethernet0 = ð
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x80000000>;
	};
};

&serial0 {
	status = "okay";
};

&serial1 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	eeprom@54 {
		compatible = "st,24c64", "atmel,24c64";
		reg = <0x54>;
		pagesize = <32>;
	};
};

&i2c1 {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&i2c3 {
	status = "okay";
};

&usb2 {
	status = "okay";
};

&usb3 {
	status = "okay";
};

&emmc {
	status = "okay";
};

&eth {
	status = "okay";
	phy-handle = <&ethphy>;
};

&mdio {
	ethphy: ethernet-phy@1 {
		reg = <1>;
	};
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Pro4 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "socionext,uniphier-pro4";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		arm_timer_clk: arm-timer {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		l2: cache-controller@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
			      <0x506c0000 0x400>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-size = <(768 * 1024)>;
			cache-sets = <256>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		spi0: spi@54006000 {
			compatible = "socionext,uniphier-scssi";
			status = "disabled";
			reg = <0x54006000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi0>;
			clocks = <&peri_clk 11>;
			resets = <&peri_rst 11>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			resets = <&peri_rst 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			resets = <&peri_rst 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			resets = <&peri_rst 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			resets = <&peri_rst 3>;
		};

		gpio: gpio@55000000 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000000 0x200>;
			interrupt-parent = <&aidet>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 0>;
			gpio-ranges-group-names = "gpio_range";
			ngpios = <248>;
			socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			resets = <&peri_rst 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			resets = <&peri_rst 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			clocks = <&peri_clk 6>;
			resets = <&peri_rst 6>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			resets = <&peri_rst 7>;
			clock-frequency = <100000>;
		};

		/* i2c4 does not exist */

		/* chip-internal connection for DMD */
		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&peri_clk 9>;
			resets = <&peri_rst 9>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for HDMI */
		i2c6: i2c@58786000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58786000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&peri_clk 10>;
			resets = <&peri_rst 10>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		mioctrl@59810000 {
			compatible = "socionext,uniphier-pro4-mioctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x800>;

			mio_clk: clock {
				compatible = "socionext,uniphier-pro4-mio-clock";
				#clock-cells = <1>;
			};

			mio_rst: reset {
				compatible = "socionext,uniphier-pro4-mio-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-pro4-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-pro4-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-pro4-peri-reset";
				#reset-cells = <1>;
			};
		};

		dmac: dma-controller@5a000000 {
			compatible = "socionext,uniphier-mio-dmac";
			reg = <0x5a000000 0x1000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mio_clk 7>;
			resets = <&mio_rst 7>;
			#dma-cells = <1>;
		};

		sd: mmc@5a400000 {
			compatible = "socionext,uniphier-sd-v2.91";
			status = "disabled";
			reg = <0x5a400000 0x200>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default", "uhs";
			pinctrl-0 = <&pinctrl_sd>;
			pinctrl-1 = <&pinctrl_sd_uhs>;
			clocks = <&mio_clk 0>;
			reset-names = "host", "bridge";
			resets = <&mio_rst 0>, <&mio_rst 3>;
			dma-names = "rx-tx";
			dmas = <&dmac 4>;
			bus-width = <4>;
			cap-sd-highspeed;
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
		};

		emmc: mmc@5a500000 {
			compatible = "socionext,uniphier-sd-v2.91";
			status = "disabled";
			reg = <0x5a500000 0x200>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc>;
			clocks = <&mio_clk 1>;
			reset-names = "host", "bridge", "hw";
			resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
			dma-names = "rx-tx";
			dmas = <&dmac 5>;
			bus-width = <8>;
			cap-mmc-highspeed;
			cap-mmc-hw-reset;
			non-removable;
		};

		sd1: mmc@5a600000 {
			compatible = "socionext,uniphier-sd-v2.91";
			status = "disabled";
			reg = <0x5a600000 0x200>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_sd1>;
			clocks = <&mio_clk 2>;
			reset-names = "host", "bridge";
			resets = <&mio_rst 2>, <&mio_rst 5>;
			dma-names = "rx-tx";
			dmas = <&dmac 6>;
			bus-width = <4>;
			cap-sd-highspeed;
		};

		usb2: usb@5a800100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a800100 0x100>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb2>;
			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
				 <&mio_clk 12>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
				 <&mio_rst 12>;
			phy-names = "usb";
			phys = <&usb_phy0>;
			has-transaction-translator;
		};

		usb3: usb@5a810100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a810100 0x100>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb3>;
			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
				 <&mio_clk 13>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
				 <&mio_rst 13>;
			phy-names = "usb";
			phys = <&usb_phy1>;
			has-transaction-translator;
		};

		soc_glue: soc-glue@5f800000 {
			compatible = "socionext,uniphier-pro4-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-pro4-pinctrl";
			};

			usb-controller {
				compatible = "socionext,uniphier-pro4-usb2-phy";
				#address-cells = <1>;
				#size-cells = <0>;

				usb_phy0: phy@0 {
					reg = <0>;
					#phy-cells = <0>;
				};

				usb_phy1: phy@1 {
					reg = <1>;
					#phy-cells = <0>;
				};

				usb_phy2: phy@2 {
					reg = <2>;
					#phy-cells = <0>;
					vbus-supply = <&usb0_vbus>;
				};

				usb_phy3: phy@3 {
					reg = <3>;
					#phy-cells = <0>;
					vbus-supply = <&usb1_vbus>;
				};
			};

			sg_clk: clock {
				compatible = "socionext,uniphier-pro4-sg-clock";
				#clock-cells = <1>;
			};
		};

		soc-glue@5f900000 {
			compatible = "socionext,uniphier-pro4-soc-glue-debug",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x5f900000 0x2000>;

			efuse@100 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x100 0x28>;
			};

			efuse@130 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x130 0x8>;
			};

			efuse@200 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x200 0x14>;
			};
		};

		xdmac: dma-controller@5fc10000 {
			compatible = "socionext,uniphier-xdmac";
			reg = <0x5fc10000 0x5300>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <16>;
			#dma-cells = <2>;
		};

		aidet: interrupt-controller@5fc20000 {
			compatible = "socionext,uniphier-pro4-aidet";
			reg = <0x5fc20000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <GIC_PPI 11
				(GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-pro4-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-pro4-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-pro4-reset";
				#reset-cells = <1>;
			};
		};

		eth: ethernet@65000000 {
			compatible = "socionext,uniphier-pro4-ave4";
			status = "disabled";
			reg = <0x65000000 0x8500>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_ether_rgmii>;
			clock-names = "gio", "ether", "ether-gb", "ether-phy";
			clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
				 <&sys_clk 10>;
			reset-names = "gio", "ether";
			resets = <&sys_rst 12>, <&sys_rst 6>;
			phy-mode = "rgmii";
			local-mac-address = [00 00 00 00 00 00];
			socionext,syscon-phy-mode = <&soc_glue 0>;

			mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		ahci0: sata@65600000 {
			compatible = "socionext,uniphier-pro4-ahci",
				     "generic-ahci";
			status = "disabled";
			reg = <0x65600000 0x10000>;
			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sys_clk 12>, <&sys_clk 28>;
			resets = <&sys_rst 12>, <&sys_rst 28>, <&ahci0_rst 3>;
			ports-implemented = <1>;
			phys = <&ahci0_phy>;
			assigned-clocks = <&sg_clk 0>;
			assigned-clock-rates = <25000000>;
		};

		sata-controller@65700000 {
			compatible = "socionext,uniphier-pxs2-ahci-glue",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x65700000 0x100>;

			ahci0_rst: reset-controller@0 {
				compatible = "socionext,uniphier-pro4-ahci-reset";
				reg = <0x0 0x4>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 28>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 28>;
				#reset-cells = <1>;
			};

			ahci0_phy: sata-phy@10 {
				compatible = "socionext,uniphier-pro4-ahci-phy";
				reg = <0x10 0x40>;
				clock-names = "link", "gio";
				clocks = <&sys_clk 28>, <&sys_clk 12>;
				reset-names = "link", "gio", "phy",
					      "pm", "tx", "rx";
				resets = <&sys_rst 28>, <&sys_rst 12>,
					 <&sys_rst 30>,
					 <&ahci0_rst 0>, <&ahci0_rst 1>,
					 <&ahci0_rst 2>;
				#phy-cells = <0>;
			};
		};

		ahci1: sata@65800000 {
			compatible = "socionext,uniphier-pro4-ahci",
				     "generic-ahci";
			status = "disabled";
			reg = <0x65800000 0x10000>;
			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sys_clk 12>, <&sys_clk 29>;
			resets = <&sys_rst 12>, <&sys_rst 29>, <&ahci1_rst 3>;
			ports-implemented = <1>;
			phys = <&ahci1_phy>;
			assigned-clocks = <&sg_clk 0>;
			assigned-clock-rates = <25000000>;
		};

		sata-controller@65900000 {
			compatible = "socionext,uniphier-pro4-ahci-glue",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x65900000 0x100>;

			ahci1_rst: reset-controller@0 {
				compatible = "socionext,uniphier-pro4-ahci-reset";
				reg = <0x0 0x4>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 29>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 29>;
				#reset-cells = <1>;
			};

			ahci1_phy: sata-phy@10 {
				compatible = "socionext,uniphier-pro4-ahci-phy";
				reg = <0x10 0x40>;
				clock-names = "link", "gio";
				clocks = <&sys_clk 29>, <&sys_clk 12>;
				reset-names = "link", "gio", "phy",
					      "pm", "tx", "rx";
				resets = <&sys_rst 29>, <&sys_rst 12>,
					 <&sys_rst 30>,
					 <&ahci1_rst 0>, <&ahci1_rst 1>,
					 <&ahci1_rst 2>;
				#phy-cells = <0>;
			};
		};

		usb0: usb@65a00000 {
			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
			status = "disabled";
			reg = <0x65a00000 0xcd00>;
			interrupt-names = "host", "peripheral";
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clock-names = "ref", "bus_early", "suspend";
			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
			resets = <&usb0_rst 4>;
			phys = <&usb_phy2>, <&usb0_ssphy>;
			dr_mode = "host";
		};

		usb-controller@65b00000 {
			compatible = "socionext,uniphier-pro4-dwc3-glue",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x65b00000 0x100>;

			usb0_vbus: regulator@0 {
				compatible = "socionext,uniphier-pro4-usb3-regulator";
				reg = <0 0x10>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 14>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 14>;
			};

			usb0_ssphy: ss-phy@10 {
				compatible = "socionext,uniphier-pro4-usb3-ssphy";
				reg = <0x10 0x10>;
				#phy-cells = <0>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 14>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 14>;
				vbus-supply = <&usb0_vbus>;
			};

			usb0_rst: reset@40 {
				compatible = "socionext,uniphier-pro4-usb3-reset";
				reg = <0x40 0x4>;
				#reset-cells = <1>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 14>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 14>;
			};
		};

		usb1: usb@65c00000 {
			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
			status = "disabled";
			reg = <0x65c00000 0xcd00>;
			interrupt-names = "host", "peripheral";
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clock-names = "ref", "bus_early", "suspend";
			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
			resets = <&usb1_rst 4>;
			phys = <&usb_phy3>;
			dr_mode = "host";
		};

		usb-controller@65d00000 {
			compatible = "socionext,uniphier-pro4-dwc3-glue",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x65d00000 0x100>;

			usb1_vbus: regulator@0 {
				compatible = "socionext,uniphier-pro4-usb3-regulator";
				reg = <0 0x10>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 15>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 15>;
			};

			usb1_rst: reset@40 {
				compatible = "socionext,uniphier-pro4-usb3-reset";
				reg = <0x40 0x4>;
				#reset-cells = <1>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 15>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 15>;
			};
		};

		nand: nand-controller@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5a";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			clock-names = "nand", "nand_x", "ecc";
			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
			reset-names = "nand", "reg";
			resets = <&sys_rst 2>, <&sys_rst 2>;
		};
	};
};

#include "uniphier-pinctrl.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Device Tree Source for UniPhier Pro5 EP-CORE Board (Pro5-PCIe_EP-CORE)
 *
 * Copyright (C) 2021 Socionext Inc.
 *   Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
 */

/dts-v1/;
#include "uniphier-pro5.dtsi"
#include "uniphier-support-card.dtsi"

/ {
	model = "UniPhier Pro5 EP-CORE Board";
	compatible = "socionext,uniphier-pro5-epcore", "socionext,uniphier-pro5";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		i2c0 = &i2c0;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};
};

&ethsc {
	interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};

&serialsc {
	interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};

&serial0 {
	status = "okay";
};

&serial1 {
	status = "okay";
};

&serial2 {
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&emmc {
	status = "okay";
};

&sd {
	status = "okay";
};

&pcie_ep {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Device Tree Source for UniPhier Pro5 ProEX Board
 *
 * Copyright (C) 2021 Socionext Inc.
 *   Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
 */

/dts-v1/;
#include "uniphier-pro5.dtsi"

/ {
	model = "UniPhier Pro5 ProEX Board";
	compatible = "socionext,uniphier-pro5-proex", "socionext,uniphier-pro5";

	chosen {
		stdout-path = "serial2:115200n8";
	};

	aliases {
		serial1 = &serial1;
		serial2 = &serial2;
		i2c0 = &i2c0;
		i2c1 = &i2c3;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};
};

&serial1 {
	status = "okay";
};

&serial2 {
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i2c3 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&emmc {
	status = "okay";
};

&pcie_ep {
	status = "okay";
};