code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin).
 *
 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
 */

#include "bcm958625-meraki-mx6x-common.dtsi"

/ {

	keys {
		compatible = "gpio-keys-polled";
		autorepeat;
		poll-interval = <20>;

		button-reset {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&gpioa 6 GPIO_ACTIVE_LOW>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led-0 {
			/* green:lan1-left */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <0>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 19 GPIO_ACTIVE_LOW>;
		};

		led-1 {
			/* green:lan1-right */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <1>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 18 GPIO_ACTIVE_LOW>;
		};

		led-2 {
			/* green:lan2-left */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <2>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
		};

		led-3 {
			/* green:lan2-right */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <3>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 20 GPIO_ACTIVE_LOW>;
		};

		led-4 {
			/* green:lan3-left */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <4>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
		};

		led-5 {
			/* green:lan3-right */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <5>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
		};

		led-6 {
			/* green:lan4-left */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <6>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
		};

		led-7 {
			/* green:lan4-right */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <7>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
		};

		led-8 {
			/* green:wan-left */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <8>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 30 GPIO_ACTIVE_LOW>;
		};

		led-9 {
			/* green:wan-right */
			function = LED_FUNCTION_ACTIVITY;
			function-enumerator = <9>;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpioa 29 GPIO_ACTIVE_LOW>;
		};

		led-a {
			/* amber:power */
			function = LED_FUNCTION_FAULT;
			color = <LED_COLOR_ID_AMBER>;
			gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
		};

		led-b {
			/* white:status */
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_WHITE>;
			gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
		};
	};
};

&srab {
	compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
	status = "okay";

	ports {
		port@0 {
			label = "lan1";
			reg = <0>;
		};

		port@1 {
			label = "lan2";
			reg = <1>;
		};

		port@2 {
			label = "lan3";
			reg = <2>;
		};

		port@3 {
			label = "lan4";
			reg = <3>;
		};

		port@4 {
			label = "wan";
			reg = <4>;
		};

		port@8 {
			ethernet = <&amac2>;
			reg = <8>;
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC.
 *
 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
 */

/dts-v1/;

#include "bcm958625-meraki-kingpin.dtsi"
#include "bcm-nsp-ax.dtsi"

/ {
	model = "Cisco Meraki MX64(A0)";
	compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x80000000>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC.
 *
 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
 */

/dts-v1/;

#include "bcm958625-meraki-kingpin.dtsi"

/ {
	model = "Cisco Meraki MX64";
	compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x80000000>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC.
 *
 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
 */

/dts-v1/;

#include "bcm958625-meraki-kingpin.dtsi"
#include "bcm-nsp-ax.dtsi"

/ {
	model = "Cisco Meraki MX64W(A0)";
	compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x80000000>;
	};
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC.
 *
 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
 */

/dts-v1/;

#include "bcm958625-meraki-kingpin.dtsi"

/ {
	model = "Cisco Meraki MX64W";
	compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x80000000>;
	};
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Device Tree Bindings for Cisco Meraki MX65.
 *
 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
 */

/dts-v1/;

#include "bcm958625-meraki-alamo.dtsi"

/ {
	model = "Cisco Meraki MX65";
	compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x80000000>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Device Tree Bindings for Cisco Meraki MX65W.
 *
 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
 */

/dts-v1/;

#include "bcm958625-meraki-alamo.dtsi"

/ {
	model = "Cisco Meraki MX65W";
	compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x80000000>;
	};
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices.
 *
 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
 */

#include "bcm-nsp.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

/ {
	pwm-leds {
		compatible = "pwm-leds";

		led-1 {
			function = LED_FUNCTION_INDICATOR;
			color = <LED_COLOR_ID_RED>;
			pwms = <&pwm 1 50000>;
			max-brightness = <255>;
		};

		led-2 {
			function = LED_FUNCTION_POWER;
			color = <LED_COLOR_ID_GREEN>;
			pwms = <&pwm 2 50000>;
			max-brightness = <255>;
		};

		led-3 {
			function = LED_FUNCTION_INDICATOR;
			color = <LED_COLOR_ID_BLUE>;
			pwms = <&pwm 3 50000>;
			max-brightness = <255>;
		};
	};
};

&amac2 {
	status = "okay";
	nvmem-cells = <&mac_address>;
	nvmem-cell-names = "mac-address";
};

&ehci0 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	eeprom@50 {
		compatible = "atmel,24c64";
		reg = <0x50>;
		pagesize = <32>;
		read-only;
		#address-cells = <1>;
		#size-cells = <1>;

		mac_address: mac-address@66 {
			reg = <0x66 0x6>;
		};
	};
};

&nand_controller {
	nand@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <24>;
		nand-ecc-step-size = <1024>;

		brcm,nand-oob-sector-size = <27>;

		partition@0 {
			label = "u-boot";
			reg = <0x0 0x80000>;
			read-only;
		};

		partition@80000 {
			label = "shmoo";
			reg = <0x80000 0x80000>;
			read-only;
		};

		partition@100000 {
			label = "bootkernel1";
			reg = <0x100000 0x300000>;
		};

		partition@400000 {
			label = "nvram";
			reg = <0x400000 0x100000>;
		};

		partition@500000 {
			label = "bootkernel2";
			reg = <0x500000 0x300000>;
		};

		partition@800000 {
			label = "ubi";
			reg = <0x800000 0x3f700000>;
		};
	};
};

&ohci0 {
	status = "okay";
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm_leds>;

	pwm_leds: pwm_leds {
		function = "pwm";
		groups = "pwm1_grp", "pwm2_grp", "pwm3_grp";
	};
};

&pwm {
	status = "okay";
	#pwm-cells = <2>;
};

&uart0 {
	clock-frequency = <62500000>;
	status = "okay";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2016 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm-nsp.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "NorthStar Plus SVK (BCM958625HR)";
	compatible = "brcm,bcm958625hr", "brcm,bcm58625", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x20000000>;
	};

	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
		open-source;
		priority = <200>;
	};

	sfp: sfp {
		compatible = "sff,sfp";
		i2c-bus = <&i2c0>;
		mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
		los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&gpioa 26 GPIO_ACTIVE_HIGH>;
	};
};

&i2c0 {
	status = "okay";
};

&dma {
	status = "okay";
};

&amac0 {
	status = "okay";
};

&amac1 {
	status = "okay";
};

&amac2 {
	status = "okay";
};

&ehci0 {
	status = "okay";
};

&nand_controller {
	nand@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <24>;
		nand-ecc-step-size = <1024>;

		brcm,nand-oob-sector-size = <27>;

		partition@0 {
			label = "nboot";
			reg = <0x00000000 0x00200000>;
			read-only;
		};
		partition@200000 {
			label = "nenv";
			reg = <0x00200000 0x00400000>;
		};
		partition@600000 {
			label = "nsystem";
			reg = <0x00600000 0x00a00000>;
		};
		partition@1000000 {
			label = "nrootfs";
			reg = <0x01000000 0x03000000>;
		};
		partition@4000000 {
			label = "ncustfs";
			reg = <0x04000000 0x3c000000>;
		};
	};
};

&ohci0 {
	status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <&nand_sel>;
	nand_sel: nand_sel {
		function = "nand";
		groups = "nand_grp";
	};
};

&qspi {
	status = "okay";
	bspi-sel = <0>;
	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p80";
		reg = <0x0>;
		spi-max-frequency = <12500000>;
		m25p,fast-read;
		spi-cpol;
		spi-cpha;

		partition@0 {
			label = "boot";
			reg = <0x00000000 0x000a0000>;
		};

		partition@a0000 {
			label = "env";
			reg = <0x000a0000 0x00060000>;
		};

		partition@100000 {
			label = "system";
			reg = <0x00100000 0x00600000>;
		};

		partition@700000 {
			label = "rootfs";
			reg = <0x00700000 0x01900000>;
		};
	};
};

&sata_phy0 {
	status = "okay";
};

&sata_phy1 {
	status = "okay";
};

&srab {
	compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
	status = "okay";

	ports {
		port@0 {
			label = "port0";
			reg = <0>;
		};

		port@1 {
			label = "port1";
			reg = <1>;
		};

		port@2 {
			label = "port2";
			reg = <2>;
		};

		port@3 {
			label = "port3";
			reg = <3>;
		};

		port@4 {
			label = "port4";
			reg = <4>;
		};

		port@5 {
			label = "sfp";
			phy-mode = "sgmii";
			reg = <5>;
			sfp = <&sfp>;
			managed = "in-band-status";
		};

		port@8 {
			ethernet = <&amac2>;
			label = "cpu";
			reg = <8>;
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};

&uart0 {
	status = "okay";
};

&usb3_phy {
	status = "okay";
};

&xhci {
	status = "okay";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm-nsp.dtsi"

/ {
	model = "NorthStar Plus SVK (BCM958625K)";
	compatible = "brcm,bcm958625k", "brcm,bcm58625", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x80000000>;
	};
};

&dma {
	status = "okay";
};

&amac0 {
	status = "okay";
};

&amac1 {
	status = "okay";
};

&amac2 {
	status = "okay";
};

&ehci0 {
	status = "okay";
};

&nand_controller {
	nand@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <24>;
		nand-ecc-step-size = <1024>;

		brcm,nand-oob-sector-size = <27>;

		partition@0 {
			label = "nboot";
			reg = <0x00000000 0x00200000>;
			read-only;
		};
		partition@200000 {
			label = "nenv";
			reg = <0x00200000 0x00400000>;
		};
		partition@600000 {
			label = "nsystem";
			reg = <0x00600000 0x00a00000>;
		};
		partition@1000000 {
			label = "nrootfs";
			reg = <0x01000000 0x03000000>;
		};
		partition@4000000 {
			label = "ncustfs";
			reg = <0x04000000 0x3c000000>;
		};
	};
};

&ohci0 {
	status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};

&pcie2 {
	status = "okay";
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <&nand_sel>, <&gpiobs>, <&pwmc>;

	nand_sel: nand_sel {
		function = "nand";
		groups = "nand_grp";
	};

	gpiobs: gpiobs {
		function = "gpio_b";
		groups = "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp",
			 "gpio_b_3_grp";
	};

	pwmc: pwmc {
		function = "pwm";
		groups = "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp";
	};

	emmc_sel: emmc_sel {
		function = "emmc";
		groups = "emmc_grp";
	};
};

&pwm {
	status = "okay";
};

&qspi {
	status = "okay";
	bspi-sel = <0>;
	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p80";
		reg = <0x0>;
		spi-max-frequency = <12500000>;
		m25p,fast-read;
		spi-cpol;
		spi-cpha;

		partition@0 {
			label = "boot";
			reg = <0x00000000 0x000a0000>;
		};

		partition@a0000 {
			label = "env";
			reg = <0x000a0000 0x00060000>;
		};

		partition@100000 {
			label = "system";
			reg = <0x00100000 0x00600000>;
		};

		partition@700000 {
			label = "rootfs";
			reg = <0x00700000 0x01900000>;
		};
	};
};

&sata_phy0 {
	status = "okay";
};

&sata_phy1 {
	status = "okay";
};

&sata {
	status = "okay";
};

/*
 * By default the sd slot is functional. For emmc to work add "<&emmc_sel>"
 * and delete "<&nand_sel>" in "pinctrl-0" property of pinctrl node. Remove the
 * bus-width property here and disable the nand node with status = "disabled";.
 *
 * Ex: pinctrl-0 = <&emmc_sel>, <&gpiobs>, <&pwmc>;
 */
&sdio {
	bus-width = <4>;
	no-1-8-v;
	status = "okay";
};

&srab {
	compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
	status = "okay";

	ports {
		port@0 {
			label = "port0";
			reg = <0>;
		};

		port@1 {
			label = "port1";
			reg = <1>;
		};

		port@2 {
			label = "port2";
			reg = <2>;
		};

		port@3 {
			label = "port3";
			reg = <3>;
		};

		port@4 {
			label = "port4";
			reg = <4>;
		};

		port@8 {
			ethernet = <&amac2>;
			label = "cpu";
			reg = <8>;
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&usb3_phy {
	status = "okay";
};

&xhci {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm63138.dtsi"

/ {
	model = "Broadcom BCM963138 Reference Board";
	compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca";

	chosen {
		bootargs = "console=ttyS0,115200";
		stdout-path = &serial0;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x08000000>;
	};
};

&serial0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Broadcom BCM63138 Reference Board DTS
 */

/dts-v1/;

#include "bcm63138.dtsi"

/ {
	compatible = "brcm,BCM963138DVT", "brcm,bcm63138", "brcm,bcmbca";
	model = "Broadcom BCM963138DVT";

	chosen {
		bootargs = "console=ttyS0,115200";
		stdout-path = &serial0;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x08000000>;
	};

};

&serial0 {
	status = "okay";
};

&serial1 {
	status = "okay";
};

&nand_controller {
	status = "okay";

	nand@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;
		brcm,nand-oob-sectors-size = <16>;
	};
};

&ahci {
	status = "okay";
};

&sata_phy {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm63148.dtsi"

/ {
	model = "Broadcom BCM963148 Reference Board";
	compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm63178.dtsi"

/ {
	model = "Broadcom BCM963178 Reference Board";
	compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm6756.dtsi"

/ {
	model = "Broadcom BCM96756 Reference Board";
	compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm6846.dtsi"

/ {
	model = "Broadcom BCM96846 Reference Board";
	compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm6855.dtsi"

/ {
	model = "Broadcom BCM96855 Reference Board";
	compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 Broadcom Ltd.
 */

/dts-v1/;

#include "bcm6878.dtsi"

/ {
	model = "Broadcom BCM96878 Reference Board";
	compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x08000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2016 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

#include "bcm-nsp.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "NorthStar Plus SVK (BCM988312HR)";
	compatible = "brcm,bcm988312hr", "brcm,bcm88312", "brcm,nsp";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x80000000>;
	};

	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
		open-source;
		priority = <200>;
	};
};

/* USB 3 support needed to be complete */

&dma {
	status = "okay";
};

&amac0 {
	status = "okay";
};

&amac1 {
	status = "okay";
};

&amac2 {
	status = "okay";
};

&ehci0 {
	status = "okay";
};

&nand_controller {
	nand@0 {
		compatible = "brcm,nandcs";
		reg = <0>;
		nand-on-flash-bbt;

		#address-cells = <1>;
		#size-cells = <1>;

		nand-ecc-strength = <24>;
		nand-ecc-step-size = <1024>;

		brcm,nand-oob-sector-size = <27>;

		partition@0 {
			label = "nboot";
			reg = <0x00000000 0x00200000>;
			read-only;
		};
		partition@200000 {
			label = "nenv";
			reg = <0x00200000 0x00400000>;
		};
		partition@600000 {
			label = "nsystem";
			reg = <0x00600000 0x00a00000>;
		};
		partition@1000000 {
			label = "nrootfs";
			reg = <0x01000000 0x03000000>;
		};
		partition@4000000 {
			label = "ncustfs";
			reg = <0x04000000 0x3c000000>;
		};
	};
};

&ohci0 {
	status = "okay";
};

&pcie0 {
	status = "okay";
};

&pcie1 {
	status = "okay";
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <&nand_sel>;
	nand_sel: nand_sel {
		function = "nand";
		groups = "nand_grp";
	};
};

&qspi {
	status = "okay";
	bspi-sel = <0>;
	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "m25p80";
		reg = <0x0>;
		spi-max-frequency = <12500000>;
		m25p,fast-read;
		spi-cpol;
		spi-cpha;

		partition@0 {
			label = "boot";
			reg = <0x00000000 0x000a0000>;
		};

		partition@a0000 {
			label = "env";
			reg = <0x000a0000 0x00060000>;
		};

		partition@100000 {
			label = "system";
			reg = <0x00100000 0x00600000>;
		};

		partition@700000 {
			label = "rootfs";
			reg = <0x00700000 0x01900000>;
		};
	};
};

&sata_phy0 {
	status = "okay";
};

&sata_phy1 {
	status = "okay";
};

&sata {
	status = "okay";
};

&srab {
	compatible = "brcm,bcm88312-srab", "brcm,nsp-srab";
	status = "okay";

	ports {
		port@0 {
			label = "port0";
			reg = <0>;
		};

		port@1 {
			label = "port1";
			reg = <1>;
		};

		port@2 {
			label = "port2";
			reg = <2>;
		};

		port@3 {
			label = "port3";
			reg = <3>;
		};

		port@4 {
			label = "port4";
			reg = <4>;
		};

		port@8 {
			ethernet = <&amac2>;
			label = "cpu";
			reg = <8>;
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};

&uart0 {
	status = "okay";
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Broadcom human machine interface daughter card (bcm9hmidc) installed on
 * bcm958300k/bcm958305k boards
 */

&touchscreen {
	touchscreen-inverted-x;
	touchscreen-inverted-y;
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for Sony NSZ-GS7
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 */

/dts-v1/;

#include "berlin2.dtsi"

/ {
	model = "Sony NSZ-GS7";
	compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x40000000>; /* 1 GB */
	};
};

&ahci { status = "okay"; };

&eth1 { status = "okay"; };

/* Unpopulated SATA plug on solder side */
&sata0 { status = "okay"; };

&sata_phy { status = "okay"; };

/* Samsung M8G2FA 8GB eMMC */
&sdhci2 {
	non-removable;
	bus-width = <8>;
	status = "okay";
};

&uart0 { status = "okay"; };


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * based on GPL'ed 2.6 kernel sources
 *  (c) Marvell International Ltd.
 */

#include <dt-bindings/clock/berlin2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 1500 (BG2) SoC";
	compatible = "marvell,berlin2", "marvell,berlin";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,berlin-smp";

		cpu@0 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;

			clocks = <&chip_clk CLKID_CPU>;
			clock-latency = <100000>;
			operating-points = <
				/* kHz    uV */
				1200000 1200000
				1000000 1200000
				800000  1200000
				600000  1200000
			>;
		};

		cpu@1 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <1>;

			clocks = <&chip_clk CLKID_CPU>;
			clock-latency = <100000>;
			operating-points = <
				/* kHz    uV */
				1200000 1200000
				1000000 1200000
				800000  1200000
				600000  1200000
			>;
		};
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc@f7000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;

		ranges = <0 0xf7000000 0x1000000>;

		sdhci0: mmc@ab0000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0000 0x200>;
			clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
			clock-names = "io", "core";
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci1: mmc@ab0800 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0800 0x200>;
			clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
			clock-names = "io", "core";
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci2: mmc@ab1000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab1000 0x200>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
			clock-names = "io", "core";
			pinctrl-0 = <&emmc_pmux>;
			pinctrl-names = "default";
			status = "disabled";
		};

		l2: cache-controller@ac0000 {
			compatible = "marvell,tauros3-cache", "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};

		scu: snoop-control-unit@ad0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xad0000 0x58>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
			clocks = <&chip_clk CLKID_TWD>;
		};

		eth1: ethernet@b90000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xb90000 0x10000>;
			clocks = <&chip_clk CLKID_GETH1>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy1>;
			status = "disabled";

			ethphy1: ethernet-phy@0 {
				reg = <0>;
			};
		};

		cpu-ctrl@dd0000 {
			compatible = "marvell,berlin-cpu-ctrl";
			reg = <0xdd0000 0x10000>;
		};

		eth0: ethernet@e50000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xe50000 0x10000>;
			clocks = <&chip_clk CLKID_GETH0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy0>;
			status = "disabled";

			ethphy0: ethernet-phy@0 {
				reg = <0>;
			};
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				interrupts = <8>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				interrupts = <9>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				interrupts = <10>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				interrupts = <11>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				interrupts = <12>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				interrupts = <13>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				interrupts = <14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				interrupts = <15>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3000 0xc00>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		ahci: sata@e90000 {
			compatible = "marvell,berlin2-ahci", "generic-ahci";
			reg = <0xe90000 0x1000>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_SATA>;
			#address-cells = <1>;
			#size-cells = <0>;

			sata0: sata-port@0 {
				reg = <0>;
				phys = <&sata_phy 0>;
				status = "disabled";
			};

			sata1: sata-port@1 {
				reg = <1>;
				phys = <&sata_phy 1>;
				status = "disabled";
			};
		};

		sata_phy: phy@e900a0 {
			compatible = "marvell,berlin2-sata-phy";
			reg = <0xe900a0 0x200>;
			clocks = <&chip_clk CLKID_SATA>;
			#address-cells = <1>;
			#size-cells = <0>;
			#phy-cells = <1>;
			status = "disabled";

			sata-phy@0 {
				reg = <0>;
			};

			sata-phy@1 {
				reg = <1>;
			};
		};

		chip: chip-control@ea0000 {
			compatible = "simple-mfd", "syscon";
			reg = <0xea0000 0x400>;

			chip_clk: clock {
				compatible = "marvell,berlin2-clk";
				#clock-cells = <1>;
				clocks = <&refclk>;
				clock-names = "refclk";
			};

			soc_pinctrl: pin-controller {
				compatible = "marvell,berlin2-soc-pinctrl";

				emmc_pmux: emmc-pmux {
					groups = "G26";
					function = "emmc";
				};
			};

			chip_rst: reset {
				compatible = "marvell,berlin2-reset";
				#reset-cells = <2>;
			};
		};

		pwm: pwm@f20000 {
			compatible = "marvell,berlin-pwm";
			reg = <0xf20000 0x40>;
			clocks = <&chip_clk CLKID_CFG>;
			#pwm-cells = <3>;
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			wdt0: watchdog@1000 {
				compatible = "snps,dw-wdt";
				reg = <0x1000 0x100>;
				clocks = <&refclk>;
				interrupts = <0>;
			};

			wdt1: watchdog@2000 {
				compatible = "snps,dw-wdt";
				reg = <0x2000 0x100>;
				clocks = <&refclk>;
				interrupts = <1>;
			};

			wdt2: watchdog@3000 {
				compatible = "snps,dw-wdt";
				reg = <0x3000 0x100>;
				clocks = <&refclk>;
				interrupts = <2>;
			};

			sm_gpio1: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <8>;
					reg = <0>;
				};
			};

			sm_gpio0: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <11>;
				};
			};

			uart0: serial@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <8>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: serial@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <9>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart2: serial@b000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xb000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <10>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart2_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			sysctrl: system-controller@d000 {
				compatible = "simple-mfd", "syscon";
				reg = <0xd000 0x100>;

				sys_pinctrl: pin-controller {
					compatible = "marvell,berlin2-system-pinctrl";
					uart0_pmux: uart0-pmux {
						groups = "GSM4";
						function = "uart0";
					};

					uart1_pmux: uart1-pmux {
						groups = "GSM5";
						function = "uart1";
					};
					uart2_pmux: uart2-pmux {
						groups = "GSM3";
						function = "uart2";
					};
				};
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x400>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for Google Chromecast
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 */

/dts-v1/;

#include "berlin2cd.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Google Chromecast";
	compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin";

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";

		/*
		 * We're using "linux,usable-memory" instead of "reg" here
		 * because the (signed and encrypted) bootloader that shipped
		 * with this device provides an incorrect memory range in
		 * ATAG_MEM. Linux helpfully overrides the "reg" property with
		 * data from the ATAG, so we can't specify the proper range
		 * normally. Fortunately, this alternate property is checked
		 * first by the OF driver, so we can (ab)use it instead.
		 */
		linux,usable-memory = <0x00000000 0x20000000>; /* 512 MB */
	};

	led-controller {
		compatible = "pwm-leds";
		pinctrl-0 = <&ledpwm_pmux>;
		pinctrl-names = "default";

		led-1 {
			label = "white";
			pwms = <&pwm 0 600000 0>;
			max-brightness = <255>;
			linux,default-trigger = "default-on";
		};

		led-2 {
			label = "red";
			pwms = <&pwm 1 600000 0>;
			max-brightness = <255>;
		};
	};
};

/*
 * AzureWave AW-NH387 (Marvell 88W8787)
 * 802.11b/g/n + Bluetooth 2.1
 */
&sdhci0 {
	non-removable;
	status = "okay";
};

&uart0 { status = "okay"; };

&usb_phy1 { status = "okay"; };

&usb1 { status = "okay"; };

&soc_pinctrl {
	ledpwm_pmux: ledpwm-pmux {
		groups = "G0";
		function = "pwm";
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2018 Alexander Monakov <amonakov@gmail.com>
 */
/dts-v1/;

#include "berlin2cd.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Valve Steam Link";
	compatible = "valve,steamlink", "marvell,berlin2cd", "marvell,berlin";

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x20000000>; /* 512 MB */
	};

	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
		active-delay = <100>;
		inactive-delay = <10>;
		wait-delay = <100>;
		priority = <200>;
	};
};

&cpu {
	cpu-supply = <&vcpu>;
	operating-points = <
		/* kHz    uV */
		1000000 1325000
	>;
};

&i2c0 {
	status = "okay";

	/* There are two regulators on the board. One is accessible via I2C,
	 * with buck1 providing SoC power (set up by bootloader to 1.325V or
	 * less depending on leakage value in OTP), and buck2 likely used for
	 * DRAM (providing 1.35V). The other regulator on the opposite side
	 * of the board is probably supplying SDIO and NAND fixed voltages. */
	regulator@19 {
		compatible = "marvell,88pg868";
		reg = <0x19>;

		vcpu: buck1 {
			regulator-boot-on;
			regulator-always-on;
			regulator-min-microvolt = <1000000>;
			regulator-max-microvolt = <1325000>;
		};
	};
};

/* Fixed interface to on-board Marvell 8897 Wi-Fi/Bluetooth/NFC chip. */
&sdhci0 {
	keep-power-in-suspend;
	non-removable;
	status = "okay";
};

&uart0 {
	/* RX/TX are routed to TP50/TP51 on the board. */
	status = "okay";
};

/* The SoC is connected to on-board USB hub that in turn has one downstream
 * port wired to the on-board Steam Controller wireless receiver chip. */
&usb_phy1 { status = "okay"; };

&usb1 {
	dr_mode = "host";
	status = "okay";
};

&eth1 { status = "okay"; };


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * based on GPL'ed 2.6 kernel sources
 *  (c) Marvell International Ltd.
 */

#include <dt-bindings/clock/berlin2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 1500-mini (BG2CD) SoC";
	compatible = "marvell,berlin2cd", "marvell,berlin";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu: cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;

			clocks = <&chip_clk CLKID_CPU>;
			clock-latency = <100000>;
			operating-points = <
				/* kHz    uV */
				800000  1200000
				600000  1200000
			>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc@f7000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;

		ranges = <0 0xf7000000 0x1000000>;

		sdhci0: mmc@ab0000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0000 0x200>;
			clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
			clock-names = "io", "core";
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		l2: cache-controller@ac0000 {
			compatible = "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};

		snoop-control-unit@ad0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xad0000 0x100>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		global-timer@ad0200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0xad0200 0x20>;
			interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
			clocks = <&chip_clk CLKID_TWD>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
			clocks = <&chip_clk CLKID_TWD>;
		};

		local-wdt@ad0620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0xad0620 0x20>;
			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
			clocks = <&chip_clk CLKID_TWD>;
		};

		usb_phy0: usb-phy@b74000 {
			compatible = "marvell,berlin2cd-usb-phy";
			reg = <0xb74000 0x128>;
			#phy-cells = <0>;
			resets = <&chip_rst 0x178 23>;
			status = "disabled";
		};

		usb_phy1: usb-phy@b78000 {
			compatible = "marvell,berlin2cd-usb-phy";
			reg = <0xb78000 0x128>;
			#phy-cells = <0>;
			resets = <&chip_rst 0x178 24>;
			status = "disabled";
		};

		eth1: ethernet@b90000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xb90000 0x10000>;
			clocks = <&chip_clk CLKID_GETH1>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy1>;
			status = "disabled";

			ethphy1: ethernet-phy@0 {
				reg = <0>;
			};
		};

		eth0: ethernet@e50000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xe50000 0x10000>;
			clocks = <&chip_clk CLKID_GETH0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy0>;
			status = "disabled";

			ethphy0: ethernet-phy@0 {
				reg = <0>;
			};
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			i2c0: i2c@1400 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x1400 0x100>;
				interrupts = <16>;
				clocks = <&chip_clk CLKID_CFG>;
				status = "disabled";
			};

			i2c1: i2c@1800 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x1800 0x100>;
				interrupts = <17>;
				clocks = <&chip_clk CLKID_CFG>;
				status = "disabled";
			};

			spi0: spi@1c00 {
				compatible = "snps,dw-apb-ssi";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x1c00 0x100>;
				interrupts = <4>;
				clocks = <&chip_clk CLKID_CFG>;
				status = "disabled";
			};

			wdt4: watchdog@2000 {
				compatible = "snps,dw-wdt";
				reg = <0x2000 0x100>;
				clocks = <&chip_clk CLKID_CFG>;
				interrupts = <5>;
				status = "disabled";
			};

			wdt5: watchdog@2400 {
				compatible = "snps,dw-wdt";
				reg = <0x2400 0x100>;
				clocks = <&chip_clk CLKID_CFG>;
				interrupts = <6>;
				status = "disabled";
			};

			wdt6: watchdog@2800 {
				compatible = "snps,dw-wdt";
				reg = <0x2800 0x100>;
				clocks = <&chip_clk CLKID_CFG>;
				interrupts = <7>;
				status = "disabled";
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				interrupts = <8>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				interrupts = <9>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				interrupts = <10>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				interrupts = <11>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				interrupts = <12>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				interrupts = <13>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				interrupts = <14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				interrupts = <15>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3000 0xc00>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		chip: chip-control@ea0000 {
			compatible = "simple-mfd", "syscon";
			reg = <0xea0000 0x400>;

			chip_clk: clock {
				compatible = "marvell,berlin2-clk";
				#clock-cells = <1>;
				clocks = <&refclk>;
				clock-names = "refclk";
			};

			soc_pinctrl: pin-controller {
				compatible = "marvell,berlin2cd-soc-pinctrl";

				uart0_pmux: uart0-pmux {
					groups = "G6";
					function = "uart0";
				};
			};

			chip_rst: reset {
				compatible = "marvell,berlin2-reset";
				#reset-cells = <2>;
			};
		};

		usb0: usb@ed0000 {
			compatible = "chipidea,usb2";
			reg = <0xed0000 0x200>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_USB0>;
			phys = <&usb_phy0>;
			phy-names = "usb-phy";
			status = "disabled";
		};

		usb1: usb@ee0000 {
			compatible = "chipidea,usb2";
			reg = <0xee0000 0x200>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_USB1>;
			phys = <&usb_phy1>;
			phy-names = "usb-phy";
			status = "disabled";
		};

		pwm: pwm@f20000 {
			compatible = "marvell,berlin-pwm";
			reg = <0xf20000 0x40>;
			clocks = <&chip_clk CLKID_CFG>;
			#pwm-cells = <3>;
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			wdt0: watchdog@1000 {
				compatible = "snps,dw-wdt";
				reg = <0x1000 0x100>;
				clocks = <&refclk>;
				interrupts = <0>;
			};

			wdt1: watchdog@2000 {
				compatible = "snps,dw-wdt";
				reg = <0x2000 0x100>;
				clocks = <&refclk>;
				interrupts = <1>;
				status = "disabled";
			};

			wdt2: watchdog@3000 {
				compatible = "snps,dw-wdt";
				reg = <0x3000 0x100>;
				clocks = <&refclk>;
				interrupts = <2>;
				status = "disabled";
			};

			sm_gpio1: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <8>;
					reg = <0>;
				};
			};

			spi1: spi@6000 {
				compatible = "snps,dw-apb-ssi";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x6000 0x100>;
				clocks = <&refclk>;
				interrupts = <5>;
				status = "disabled";
			};

			i2c2: i2c@7000 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x7000 0x100>;
				interrupts = <6>;
				clocks = <&refclk>;
				status = "disabled";
			};

			i2c3: i2c@8000 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x8000 0x100>;
				interrupts = <7>;
				clocks = <&refclk>;
				status = "disabled";
			};

			sm_gpio0: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <8>;
					reg = <0>;
				};
			};

			uart0: serial@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <8>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: serial@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <9>;
				clocks = <&refclk>;
				status = "disabled";
			};

			uart2: serial@b000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xb000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <10>;
				clocks = <&refclk>;
				status = "disabled";
			};

			sysctrl: system-controller@d000 {
				compatible = "simple-mfd", "syscon";
				reg = <0xd000 0x100>;

				sys_pinctrl: pin-controller {
					compatible = "marvell,berlin2cd-system-pinctrl";
				};

				adc: adc {
					compatible = "marvell,berlin2-adc";
					interrupts = <12>, <14>;
					interrupt-names = "adc", "tsen";
				};
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x400>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include "berlin2q.dtsi"

/ {
	model = "Marvell BG2-Q DMP";
	compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin";

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x80000000>;
	};

	chosen {
		bootargs = "earlyprintk";
		stdout-path = "serial0:115200n8";
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_usb0_vbus: regulator_usb0 {
			compatible = "regulator-fixed";
			regulator-name = "usb0_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&portb 8 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usb1_vbus: regulator_usb1 {
			compatible = "regulator-fixed";
			regulator-name = "usb1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&portb 10 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_usb2_vbus: regulator_usb2 {
			compatible = "regulator-fixed";
			regulator-name = "usb2_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&portb 12 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		reg_sdio1_vmmc: regulator_sdio1_vmmc {
			compatible = "regulator-fixed";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-name = "sdio1_vmmc";
			enable-active-high;
			regulator-boot-on;
			gpio = <&portb 21 GPIO_ACTIVE_HIGH>;
		};

		reg_sdio1_vqmmc: regulator_sido1_vqmmc {
			compatible = "regulator-gpio";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <3300000>;
			regulator-name = "sdio1_vqmmc";
			regulator-type = "voltage";
			enable-active-high;
			gpios = <&portb 16 GPIO_ACTIVE_HIGH>;
			states = <3300000 0x1
				  1800000 0x0>;
		};
	};
};

&soc_pinctrl {
	sd1gpio_pmux: sd1pwr-pmux {
		groups = "G23", "G32";
		function = "gpio";
	};
};

&sdhci1 {
	vmmc-supply = <&reg_sdio1_vmmc>;
	vqmmc-supply = <&reg_sdio1_vqmmc>;
	cd-gpios = <&portc 30 GPIO_ACTIVE_LOW>;
	wp-gpios = <&portd 0 GPIO_ACTIVE_HIGH>;
	pinctrl-0 = <&sd1gpio_pmux>, <&sd1_pmux>;
	pinctrl-names = "default";
	status = "okay";
};

&sdhci2 {
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&usb_phy0 {
	status = "okay";
};

&usb_phy2 {
	status = "okay";
};

&usb0 {
	vbus-supply = <&reg_usb0_vbus>;
	status = "okay";
};

&usb2 {
	vbus-supply = <&reg_usb2_vbus>;
	status = "okay";
};

&eth0 {
	status = "okay";
};

&sata0 {
	status = "okay";
};

&sata_phy {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
 */

#include <dt-bindings/clock/berlin2q.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 1500 pro (BG2-Q) SoC";
	compatible = "marvell,berlin2q", "marvell,berlin";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,berlin-smp";

		cpu0: cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;

			clocks = <&chip_clk CLKID_CPU>;
			clock-latency = <100000>;
			/* Can be modified by the bootloader */
			operating-points = <
				/* kHz    uV */
				1200000 1200000
				1000000 1200000
				800000  1200000
				600000  1200000
			>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <1>;

			clocks = <&chip_clk CLKID_CPU>;
			clock-latency = <100000>;
			/* Can be modified by the bootloader */
			operating-points = <
				/* kHz    uV */
				1200000 1200000
				1000000 1200000
				800000  1200000
				600000  1200000
			>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <2>;

			clocks = <&chip_clk CLKID_CPU>;
			clock-latency = <100000>;
			/* Can be modified by the bootloader */
			operating-points = <
				/* kHz    uV */
				1200000 1200000
				1000000 1200000
				800000  1200000
				600000  1200000
			>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <3>;

			clocks = <&chip_clk CLKID_CPU>;
			clock-latency = <100000>;
			/* Can be modified by the bootloader */
			operating-points = <
				/* kHz    uV */
				1200000 1200000
				1000000 1200000
				800000  1200000
				600000  1200000
			>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc@f7000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0 0xf7000000 0x1000000>;
		interrupt-parent = <&gic>;

		sdhci0: mmc@ab0000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0000 0x200>;
			clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
			clock-names = "io", "core";
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci1: mmc@ab0800 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0800 0x200>;
			clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
			clock-names = "io", "core";
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci2: mmc@ab1000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab1000 0x200>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>;
			clock-names = "io", "core";
			status = "disabled";
		};

		l2: cache-controller@ac0000 {
			compatible = "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-unified;
			cache-level = <2>;
			arm,data-latency = <2 2 2>;
			arm,tag-latency = <2 2 2>;
		};

		scu: snoop-control-unit@ad0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xad0000 0x58>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			clocks = <&chip_clk CLKID_TWD>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		usb_phy2: phy@a2f400 {
			compatible = "marvell,berlin2cd-usb-phy";
			reg = <0xa2f400 0x128>;
			#phy-cells = <0>;
			resets = <&chip_rst 0x104 14>;
			status = "disabled";
		};

		usb2: usb@a30000 {
			compatible = "chipidea,usb2";
			reg = <0xa30000 0x10000>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_USB2>;
			phys = <&usb_phy2>;
			phy-names = "usb-phy";
			status = "disabled";
		};

		usb_phy0: phy@b74000 {
			compatible = "marvell,berlin2cd-usb-phy";
			reg = <0xb74000 0x128>;
			#phy-cells = <0>;
			resets = <&chip_rst 0x104 12>;
			status = "disabled";
		};

		usb_phy1: phy@b78000 {
			compatible = "marvell,berlin2cd-usb-phy";
			reg = <0xb78000 0x128>;
			#phy-cells = <0>;
			resets = <&chip_rst 0x104 13>;
			status = "disabled";
		};

		eth0: ethernet@b90000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xb90000 0x10000>;
			clocks = <&chip_clk CLKID_GETH0>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy0>;
			status = "disabled";

			ethphy0: ethernet-phy@0 {
				reg = <0>;
			};
		};

		cpu-ctrl@dd0000 {
			compatible = "marvell,berlin-cpu-ctrl";
			reg = <0xdd0000 0x10000>;
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			i2c0: i2c@1400 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x1400 0x100>;
				interrupts = <4>;
				clocks = <&chip_clk CLKID_CFG>;
				pinctrl-0 = <&twsi0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			i2c1: i2c@1800 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x1800 0x100>;
				interrupts = <5>;
				clocks = <&chip_clk CLKID_CFG>;
				pinctrl-0 = <&twsi1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				interrupts = <8>;
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3800 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3800 0x30>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		chip: chip-control@ea0000 {
			compatible = "simple-mfd", "syscon";
			reg = <0xea0000 0x400>, <0xdd0170 0x10>;

			chip_clk: clock {
				compatible = "marvell,berlin2q-clk";
				#clock-cells = <1>;
				clocks = <&refclk>;
				clock-names = "refclk";
			};

			soc_pinctrl: pin-controller {
				compatible = "marvell,berlin2q-soc-pinctrl";

				sd1_pmux: sd1-pmux {
					groups = "G31";
					function = "sd1";
				};

				twsi0_pmux: twsi0-pmux {
					groups = "G6";
					function = "twsi0";
				};

				twsi1_pmux: twsi1-pmux {
					groups = "G7";
					function = "twsi1";
				};
			};

			chip_rst: reset {
				compatible = "marvell,berlin2-reset";
				#reset-cells = <2>;
			};
		};

		ahci: sata@e90000 {
			compatible = "marvell,berlin2q-ahci", "generic-ahci";
			reg = <0xe90000 0x1000>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_SATA>;
			#address-cells = <1>;
			#size-cells = <0>;

			sata0: sata-port@0 {
				reg = <0>;
				phys = <&sata_phy 0>;
				status = "disabled";
			};

			sata1: sata-port@1 {
				reg = <1>;
				phys = <&sata_phy 1>;
				status = "disabled";
			};
		};

		sata_phy: phy@e900a0 {
			compatible = "marvell,berlin2q-sata-phy";
			reg = <0xe900a0 0x200>;
			clocks = <&chip_clk CLKID_SATA>;
			#address-cells = <1>;
			#size-cells = <0>;
			#phy-cells = <1>;
			status = "disabled";

			sata-phy@0 {
				reg = <0>;
			};

			sata-phy@1 {
				reg = <1>;
			};
		};

		usb0: usb@ed0000 {
			compatible = "chipidea,usb2";
			reg = <0xed0000 0x10000>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_USB0>;
			phys = <&usb_phy0>;
			phy-names = "usb-phy";
			status = "disabled";
		};

		usb1: usb@ee0000 {
			compatible = "chipidea,usb2";
			reg = <0xee0000 0x10000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_USB1>;
			phys = <&usb_phy1>;
			phy-names = "usb-phy";
			status = "disabled";
		};

		pwm: pwm@f20000 {
			compatible = "marvell,berlin-pwm";
			reg = <0xf20000 0x40>;
			clocks = <&chip_clk CLKID_CFG>;
			#pwm-cells = <3>;
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			wdt0: watchdog@1000 {
				compatible = "snps,dw-wdt";
				reg = <0x1000 0x100>;
				clocks = <&refclk>;
				interrupts = <0>;
			};

			wdt1: watchdog@2000 {
				compatible = "snps,dw-wdt";
				reg = <0x2000 0x100>;
				clocks = <&refclk>;
				interrupts = <1>;
			};

			wdt2: watchdog@3000 {
				compatible = "snps,dw-wdt";
				reg = <0x3000 0x100>;
				clocks = <&refclk>;
				interrupts = <2>;
			};

			sm_gpio1: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <32>;
					reg = <0>;
				};
			};

			i2c2: i2c@7000 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x7000 0x100>;
				interrupts = <6>;
				clocks = <&refclk>;
				pinctrl-0 = <&twsi2_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			i2c3: i2c@8000 {
				compatible = "snps,designware-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x8000 0x100>;
				interrupts = <7>;
				clocks = <&refclk>;
				pinctrl-0 = <&twsi3_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart0: uart@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				interrupts = <8>;
				clocks = <&refclk>;
				reg-shift = <2>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: uart@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				interrupts = <9>;
				clocks = <&refclk>;
				reg-shift = <2>;
				pinctrl-0 = <&uart1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			sm_gpio0: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					ngpios = <32>;
					reg = <0>;
				};
			};

			sysctrl: pin-controller@d000 {
				compatible = "simple-mfd", "syscon";
				reg = <0xd000 0x100>;

				sys_pinctrl: pin-controller {
					compatible = "marvell,berlin2q-system-pinctrl";

					uart0_pmux: uart0-pmux {
						groups = "GSM12";
						function = "uart0";
					};

					uart1_pmux: uart1-pmux {
						groups = "GSM14";
						function = "uart1";
					};

					twsi2_pmux: twsi2-pmux {
						groups = "GSM13";
						function = "twsi2";
					};

					twsi3_pmux: twsi3-pmux {
						groups = "GSM14";
						function = "twsi3";
					};
				};

				adc: adc {
					compatible = "marvell,berlin2-adc";
					interrupts = <12>, <14>;
					interrupt-names = "adc", "tsen";
				};
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x30>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/
 */

/ {
	model = "CompuLab SB-SOM";
	compatible = "compulab,sb-som";

	vsb_3v3: fixedregulator-v3_3 {
		compatible = "regulator-fixed";
		regulator-name = "vsb_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		enable-active-high;
	};

	lcd0: display {
		compatible = "startek,startek-kd050c", "panel-dpi";
		label = "lcd";

		panel-timing {
			clock-frequency = <33000000>;
			hactive = <800>;
			vactive = <480>;
			hfront-porch = <40>;
			hback-porch = <40>;
			hsync-len = <43>;
			vback-porch = <29>;
			vfront-porch = <13>;
			vsync-len = <3>;
			hsync-active = <0>;
			vsync-active = <0>;
			de-active = <1>;
			pixelclk-active = <1>;
		};
	};

	hdmi_conn: connector {
		compatible = "hdmi-connector";
		label = "hdmi";

		type = "a";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Thermistor dts fragment for devices that use Thermistors as
 * children of the IIO based ADC.
 *
 * Currently, used by Exynos5420 based Peach PIT and
 * Exynos5800 based Peach PI.
 *
 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
*/

&adc {
	thermistor3 {
		compatible = "murata,ncp15wb473";
		pullup-uv = <1800000>;
		pullup-ohm = <47000>;
		pulldown-ohm = <0>;
		io-channels = <&adc 3>;
	};
	thermistor4 {
		compatible = "murata,ncp15wb473";
		pullup-uv = <1800000>;
		pullup-ohm = <47000>;
		pulldown-ohm = <0>;
		io-channels = <&adc 4>;
	};
	thermistor5 {
		compatible = "murata,ncp15wb473";
		pullup-uv = <1800000>;
		pullup-ohm = <47000>;
		pulldown-ohm = <0>;
		io-channels = <&adc 5>;
	};
	thermistor6 {
		compatible = "murata,ncp15wb473";
		pullup-uv = <1800000>;
		pullup-ohm = <47000>;
		pulldown-ohm = <0>;
		io-channels = <&adc 6>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Keyboard dts fragment for devices that use cros-ec-keyboard
 *
 * Copyright (c) 2014 Google, Inc
*/

#include <dt-bindings/input/input.h>
#include <dt-bindings/input/cros-ec-keyboard.h>

&cros_ec {
	keyboard_controller: keyboard-controller {
		compatible = "google,cros-ec-keyb";
		keypad,num-rows = <8>;
		keypad,num-columns = <13>;
		google,needs-ghost-filter;

		linux,keymap = <
			CROS_STD_TOP_ROW_KEYMAP
			CROS_STD_MAIN_KEYMAP
		>;
	};
};


code:
/*
 * Smart battery dts fragment for devices that use cros-ec-sbs
 *
 * Copyright (c) 2015 Google, Inc
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

&i2c_tunnel {
	battery: sbs-battery@b {
		compatible = "sbs,sbs-battery";
		reg = <0xb>;
		sbs,i2c-retry-count = <2>;
		sbs,poll-retry-count = <1>;
	};
};


code:
/*
 * Device Tree Include file for the Conexant Digicolor CX92755 SoC
 *
 * Author: Baruch Siach <baruch@tkos.co.il>
 *
 *  Copyright (C) 2014 Paradox Innovation Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "cnxt,cx92755";

	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
		};
	};

	main_clk: main_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency  = <200000000>;
	};

	intc: interrupt-controller@f0000040 {
		compatible = "cnxt,cx92755-ic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0xf0000040 0x40>;
		syscon = <&uc_regs>;
	};

	timer@f0000fc0 {
		compatible = "cnxt,cx92755-timer";
		reg = <0xf0000fc0 0x40>;
		interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>;
		clocks = <&main_clk>;
	};

	rtc@f0000c30 {
		compatible = "cnxt,cx92755-rtc";
		reg = <0xf0000c30 0x18>;
		interrupts = <25>;
	};

	watchdog@f0000fc0 {
		compatible = "cnxt,cx92755-wdt";
		reg = <0xf0000fc0 0x8>;
		clocks = <&main_clk>;
		timeout-sec = <15>;
	};

	pinctrl: pinctrl@f0000e20 {
		compatible = "cnxt,cx92755-pinctrl";
		reg = <0xf0000e20 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	uc_regs: syscon@f00003a0 {
		compatible = "cnxt,cx92755-uc", "syscon";
		reg = <0xf00003a0 0x10>;
	};

	uart0: uart@f0000740 {
		compatible = "cnxt,cx92755-usart";
		reg = <0xf0000740 0x20>;
		clocks = <&main_clk>;
		interrupts = <44>;
		status = "disabled";
	};

	uart1: uart@f0000760 {
		compatible = "cnxt,cx92755-usart";
		reg = <0xf0000760 0x20>;
		clocks = <&main_clk>;
		interrupts = <45>;
		status = "disabled";
	};

	uart2: uart@f0000780 {
		compatible = "cnxt,cx92755-usart";
		reg = <0xf0000780 0x20>;
		clocks = <&main_clk>;
		interrupts = <46>;
		status = "disabled";
	};

	i2c: i2c@f0000120 {
		compatible = "cnxt,cx92755-i2c";
		reg = <0xf0000120 0x10>;
		interrupts = <28>;
		clocks = <&main_clk>;
		clock-frequency = <100000>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};
};


code:
/*
 * Device Tree file for the Conexant Equinox CX92755 EVK
 *
 * Author: Baruch Siach <baruch@tkos.co.il>
 *
 *  Copyright (C) 2014 Paradox Innovation Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include "cx92755.dtsi"

/ {
	model = "Conexant Equinox CX92755 EVK";
	compatible = "cnxt,equinox", "cnxt,cx92755";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
	};

	memory@0 {
		reg = <0 0x8000000>;
		device_type = "memory";
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&uart0 {
	status = "okay";
	pinctrl-0 = <&uart0_default>;
	pinctrl-names = "default";
};

&i2c {
	status = "okay";
};

&pinctrl {
	uart0_default: uart0_active {
		pins = "GP_O0", "GP_O1";
		function = "client_b";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Device Tree for AM1808 EnBW CMC board
 *
 * Copyright 2012 DENX Software Engineering GmbH
 * Heiko Schocher <hs@denx.de>
 */
/dts-v1/;
#include "da850.dtsi"

/ {
	compatible = "enbw,cmc", "ti,da850";
	model = "EnBW CMC";

	soc@1c00000 {
		serial0: serial@42000 {
			status = "okay";
		};
		serial1: serial@10c000 {
			status = "okay";
		};
		serial2: serial@10d000 {
			status = "okay";
		};
		mdio: mdio@224000 {
			status = "okay";
		};
		eth0: ethernet@220000 {
			status = "okay";
		};
	};
};

&ref_clk {
	clock-frequency = <24000000>;
};

&edma0 {
	ti,edma-reserved-slot-ranges = <32 50>;
};

&edma1 {
	ti,edma-reserved-slot-ranges = <32 90>;
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Device Tree for DA850 EVM board
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 */
/dts-v1/;
#include "da850.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "ti,da850-evm", "ti,da850";
	model = "DA850/AM1808/OMAP-L138 EVM";

	chosen {
		stdout-path = &serial2;
	};

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		ethernet0 = &eth0;
		spi0 = &spi1;
	};

	backlight: backlight-pwm {
		pinctrl-names = "default";
		pinctrl-0 = <&ecap2_pins>;
		power-supply = <&backlight_lcd>;
		compatible = "pwm-backlight";
		/*
		 * The PWM here corresponds to production hardware. The
		 * schematic needs to be 1015171 (15 March 2010), Rev A
		 * or newer.
		 */
		pwms = <&ecap2 0 50000 0>;
		brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
		default-brightness-level = <7>;
	};

	panel {
		compatible = "ti,tilcdc,panel";
		pinctrl-names = "default";
		pinctrl-0 = <&lcd_pins>;
		/*
		 * The vpif and the LCD are mutually exclusive.
		 * To enable VPIF, change the status below to 'disabled' then
		 * then change the status of the vpif below to 'okay'
		 */
		status = "okay";
		enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */

		panel-info {
			ac-bias = <255>;
			ac-bias-intrpt = <0>;
			dma-burst-sz = <16>;
			bpp = <16>;
			fdd = <0x80>;
			sync-edge = <0>;
			sync-ctrl = <1>;
			raster-order = <0>;
			fifo-th = <0>;
		};

		display-timings {
			native-mode = <&timing0>;
			timing0: 480x272 {
				clock-frequency = <9000000>;
				hactive = <480>;
				vactive = <272>;
				hfront-porch = <3>;
				hback-porch = <2>;
				hsync-len = <42>;
				vback-porch = <3>;
				vfront-porch = <4>;
				vsync-len = <11>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <1>;
			};
		};
	};

	vbat: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "vbat";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
	};

	baseboard_3v3: fixedregulator-3v3 {
		/* TPS73701DCQ */
		compatible = "regulator-fixed";
		regulator-name = "baseboard_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vbat>;
		regulator-always-on;
		regulator-boot-on;
	};

	baseboard_1v8: fixedregulator-1v8 {
		/* TPS73701DCQ */
		compatible = "regulator-fixed";
		regulator-name = "baseboard_1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&vbat>;
		regulator-always-on;
		regulator-boot-on;
	};

	backlight_lcd: backlight-regulator {
		compatible = "regulator-fixed";
		regulator-name = "lcd_backlight_pwr";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */
		enable-active-high;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DA850-OMAPL138 EVM";
		simple-audio-card,widgets =
			"Line", "Line In",
			"Line", "Line Out";
		simple-audio-card,routing =
			"LINE1L", "Line In",
			"LINE1R", "Line In",
			"Line Out", "LLOUT",
			"Line Out", "RLOUT";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&link0_codec>;
		simple-audio-card,frame-master = <&link0_codec>;
		simple-audio-card,bitclock-inversion;

		simple-audio-card,cpu {
			sound-dai = <&mcasp0>;
			system-clock-frequency = <24576000>;
		};

		link0_codec: simple-audio-card,codec {
			sound-dai = <&tlv320aic3106>;
			system-clock-frequency = <24576000>;
		};
	};
};

&ecap2 {
	status = "okay";
};

&ref_clk {
	clock-frequency = <24000000>;
};

&pmx_core {
	status = "okay";

	mcasp0_pins: pinmux_mcasp0_pins {
		pinctrl-single,bits = <
			/*
			 * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR,
			 * AFSR, AMUTE
			 */
			0x00 0x11111111 0xffffffff
			/* AXR11, AXR12 */
			0x04 0x00011000 0x000ff000
		>;
	};
	nand_pins: nand_pins {
		pinctrl-single,bits = <
			/* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */
			0x1c 0x10110110  0xf0ff0ff0
			/*
			 * EMA_D[0], EMA_D[1], EMA_D[2],
			 * EMA_D[3], EMA_D[4], EMA_D[5],
			 * EMA_D[6], EMA_D[7]
			 */
			0x24 0x11111111  0xffffffff
			/* EMA_A[1], EMA_A[2] */
			0x30 0x01100000  0x0ff00000
		>;
	};
};

&cpu {
	cpu-supply = <&vdcdc3_reg>;
};

/*
 * The standard da850-evm kits and SOM's are 375MHz so enable this operating
 * point by default. Higher frequencies must be enabled for custom boards with
 * other variants of the SoC.
 */
&opp_375 {
	status = "okay";
};

&sata {
	status = "okay";
};

&serial0 {
	status = "okay";
};

&serial1 {
	status = "okay";
};

&serial2 {
	status = "okay";
};

&rtc0 {
	status = "okay";
};

&lcdc {
	status = "okay";
};

&i2c0 {
	status = "okay";
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;

	tps: tps@48 {
		reg = <0x48>;
	};
	tlv320aic3106: tlv320aic3106@18 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3106";
		reg = <0x18>;
		status = "okay";

		/* Regulators */
		IOVDD-supply = <&vdcdc2_reg>;
		AVDD-supply = <&baseboard_3v3>;
		DRVDD-supply = <&baseboard_3v3>;
		DVDD-supply = <&baseboard_1v8>;
	};
	tca6416: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
	tca6416_bb: gpio@21 {
		compatible = "ti,tca6416";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&wdt {
	status = "okay";
};

&mmc0 {
	max-frequency = <50000000>;
	bus-width = <4>;
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	cd-gpios = <&gpio 64 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio 65 GPIO_ACTIVE_HIGH>;
};

&spi1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <30000000>;
		m25p,fast-read;
		reg = <0>;
		partition@0 {
			label = "U-Boot-SPL";
			reg = <0x00000000 0x00010000>;
			read-only;
		};
		partition@1 {
			label = "U-Boot";
			reg = <0x00010000 0x00080000>;
			read-only;
		};
		partition@2 {
			label = "U-Boot-Env";
			reg = <0x00090000 0x00010000>;
			read-only;
		};
		partition@3 {
			label = "Kernel";
			reg = <0x000a0000 0x00280000>;
		};
		partition@4 {
			label = "Filesystem";
			reg = <0x00320000 0x00400000>;
		};
		partition@5 {
			label = "MAC-Address";
			reg = <0x007f0000 0x00010000>;
			read-only;
		};
	};
};

&mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	bus_freq = <2200000>;
};

&eth0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mii_pins>;
};

&gpio {
	status = "okay";
};

/include/ "tps6507x.dtsi"

&tps {
	vdcdc1_2-supply = <&vbat>;
	vdcdc3-supply = <&vbat>;
	vldo1_2-supply = <&vbat>;

	regulators {
		vdcdc1_reg: regulator@0 {
			regulator-name = "VDCDC1_3.3V";
			regulator-min-microvolt = <3150000>;
			regulator-max-microvolt = <3450000>;
			regulator-always-on;
			regulator-boot-on;
		};

		vdcdc2_reg: regulator@1 {
			regulator-name = "VDCDC2_3.3V";
			regulator-min-microvolt = <1710000>;
			regulator-max-microvolt = <3450000>;
			regulator-always-on;
			regulator-boot-on;
			ti,defdcdc_default = <1>;
		};

		vdcdc3_reg: regulator@2 {
			regulator-name = "VDCDC3_1.2V";
			regulator-min-microvolt = <950000>;
			regulator-max-microvolt = <1350000>;
			regulator-always-on;
			regulator-boot-on;
			ti,defdcdc_default = <1>;
		};

		ldo1_reg: regulator@3 {
			regulator-name = "LDO1_1.8V";
			regulator-min-microvolt = <1710000>;
			regulator-max-microvolt = <1890000>;
			regulator-always-on;
			regulator-boot-on;
		};

		ldo2_reg: regulator@4 {
			regulator-name = "LDO2_1.2V";
			regulator-min-microvolt = <1140000>;
			regulator-max-microvolt = <1320000>;
			regulator-always-on;
			regulator-boot-on;
		};
	};
};

&mcasp0 {
	#sound-dai-cells = <0>;
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcasp0_pins>;

	op-mode = <0>;          /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializer */
	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
		0 0 0 0
		0 0 0 0
		0 0 0 1
		2 0 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&edma0 {
	ti,edma-reserved-slot-ranges = <32 50>;
};

&edma1 {
	ti,edma-reserved-slot-ranges = <32 90>;
};

&aemif {
	pinctrl-names = "default";
	pinctrl-0 = <&nand_pins>;
	status = "ok";
	cs3 {
		#address-cells = <2>;
		#size-cells = <1>;
		clock-ranges;
		ranges;

		ti,cs-chipselect = <3>;

		nand@2000000,0 {
			compatible = "ti,davinci-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0 0x02000000 0x02000000
			       1 0x00000000 0x00008000>;

			ti,davinci-chipselect = <1>;
			ti,davinci-mask-ale = <0>;
			ti,davinci-mask-cle = <0>;
			ti,davinci-mask-chipsel = <0>;
			ti,davinci-ecc-mode = "hw";
			ti,davinci-ecc-bits = <4>;
			ti,davinci-nand-use-bbt;
		};
	};
};

&usb_phy {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&vpif {
	pinctrl-names = "default";
	pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
	/*
	 * The vpif and the LCD are mutually exclusive.
	 * To enable VPIF, disable the ti,tilcdc,panel then
	 * change the status below to 'okay'
	 */
	status = "disabled";
};