code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for NXP Layerscape-1043A family SoC.
 *
 * Copyright 2014-2015 Freescale Semiconductor, Inc.
 * Copyright 2018, 2020 NXP
 *
 * Mingkai Hu <Mingkai.hu@freescale.com>
 */

#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "fsl,ls1043a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		crypto = &crypto;
		fman0 = &fman0;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		ethernet4 = &enet4;
		ethernet5 = &enet5;
		ethernet6 = &enet6;
		rtc1 = &ftm_alarm0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		/*
		 * We expect the enable-method for cpu's to be "psci", but this
		 * is dependent on the SoC FW, which will fill this in.
		 *
		 * Currently supported enable-method is psci v0.2
		 */
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		l2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	idle-states {
		/*
		 * PSCI node is not added default, U-boot will add missing
		 * parts if it determines to use PSCI.
		 */
		entry-method = "psci";

		CPU_PH20: cpu-ph20 {
			compatible = "arm,idle-state";
			idle-state-name = "PH20";
			arm,psci-suspend-param = <0x0>;
			entry-latency-us = <1000>;
			exit-latency-us = <1000>;
			min-residency-us = <3000>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0 0x80000000>;
		      /* DRAM space 1, size: 2GiB DRAM */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		bman_fbpr: bman-fbpr {
			compatible = "shared-dma-pool";
			size = <0 0x1000000>;
			alignment = <0 0x1000000>;
			no-map;
		};

		qman_fqd: qman-fqd {
			compatible = "shared-dma-pool";
			size = <0 0x400000>;
			alignment = <0 0x400000>;
			no-map;
		};

		qman_pfdr: qman-pfdr {
			compatible = "shared-dma-pool";
			size = <0 0x2000000>;
			alignment = <0 0x2000000>;
			no-map;
		};
	};

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	reboot {
		compatible = "syscon-reboot";
		regmap = <&dcfg>;
		offset = <0xb0>;
		mask = <0x02>;
	};

	thermal-zones {
		ddr-controller {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 0>;

			trips {
				ddr-ctrler-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				ddr-ctrler-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		serdes {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 1>;

			trips {
				serdes-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				serdes-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		fman {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 2>;

			trips {
				fman-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				fman-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		core-cluster {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 3>;

			trips {
				core_cluster_alert: core-cluster-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				core_cluster_crit: core-cluster-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&core_cluster_alert>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		sec {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 4>;

			trips {
				sec-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				sec-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 0xf08>, /* Physical Secure PPI */
			     <1 14 0xf08>, /* Physical Non-Secure PPI */
			     <1 11 0xf08>, /* Virtual PPI */
			     <1 10 0xf08>; /* Hypervisor PPI */
		fsl,erratum-a008585;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 106 0x4>,
			     <0 107 0x4>,
			     <0 95 0x4>,
			     <0 97 0x4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
	};

	gic: interrupt-controller@1400000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
		      <0x0 0x1402000 0 0x2000>, /* GICC */
		      <0x0 0x1404000 0 0x2000>, /* GICH */
		      <0x0 0x1406000 0 0x2000>; /* GICV */
		interrupts = <1 9 0xf08>;
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
		dma-coherent;

		clockgen: clocking@1ee1000 {
			compatible = "fsl,ls1043a-clockgen";
			reg = <0x0 0x1ee1000 0x0 0x1000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		scfg: scfg@1570000 {
			compatible = "fsl,ls1043a-scfg", "syscon";
			reg = <0x0 0x1570000 0x0 0x10000>;
			big-endian;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x1570000 0x10000>;

			extirq: interrupt-controller@1ac {
				compatible = "fsl,ls1043a-extirq";
				#interrupt-cells = <2>;
				#address-cells = <0>;
				interrupt-controller;
				reg = <0x1ac 4>;
				interrupt-map =
					<0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
					<1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
					<2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
					<3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
					<4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
					<5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
					<6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
					<7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
					<8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
					<9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
					<10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
					<11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-map-mask = <0xf 0x0>;
			};
		};

		crypto: crypto@1700000 {
			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
				     "fsl,sec-v4.0";
			fsl,sec-era = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x00 0x1700000 0x100000>;
			reg = <0x00 0x1700000 0x0 0x100000>;
			interrupts = <0 75 0x4>;
			dma-coherent;

			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x10000 0x10000>;
				interrupts = <0 71 0x4>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x20000 0x10000>;
				interrupts = <0 72 0x4>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x30000 0x10000>;
				interrupts = <0 73 0x4>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x40000 0x10000>;
				interrupts = <0 74 0x4>;
			};
		};

		sfp: efuse@1e80000 {
			compatible = "fsl,ls1021a-sfp";
			reg = <0x0 0x1e80000 0x0 0x10000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "sfp";
		};

		dcfg: dcfg@1ee0000 {
			compatible = "fsl,ls1043a-dcfg", "syscon";
			reg = <0x0 0x1ee0000 0x0 0x1000>;
			big-endian;
		};

		ifc: memory-controller@1530000 {
			compatible = "fsl,ifc";
			reg = <0x0 0x1530000 0x0 0x10000>;
			interrupts = <0 43 0x4>;
		};

		qspi: spi@1550000 {
			compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x1550000 0x0 0x10000>,
				<0x0 0x40000000 0x0 0x4000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <0 99 0x4>;
			clock-names = "qspi_en", "qspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			status = "disabled";
		};

		esdhc: esdhc@1560000 {
			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
			reg = <0x0 0x1560000 0x0 0x10000>;
			interrupts = <0 62 0x4>;
			clock-frequency = <0>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			big-endian;
			bus-width = <4>;
		};

		ddr: memory-controller@1080000 {
			compatible = "fsl,qoriq-memory-controller";
			reg = <0x0 0x1080000 0x0 0x1000>;
			interrupts = <0 144 0x4>;
			big-endian;
		};

		tmu: tmu@1f00000 {
			compatible = "fsl,qoriq-tmu";
			reg = <0x0 0x1f00000 0x0 0x10000>;
			interrupts = <0 33 0x4>;
			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
			fsl,tmu-calibration = <0x00000000 0x00000023
					       0x00000001 0x0000002a
					       0x00000002 0x00000031
					       0x00000003 0x00000037
					       0x00000004 0x0000003e
					       0x00000005 0x00000044
					       0x00000006 0x0000004b
					       0x00000007 0x00000051
					       0x00000008 0x00000058
					       0x00000009 0x0000005e
					       0x0000000a 0x00000065
					       0x0000000b 0x0000006b

					       0x00010000 0x00000023
					       0x00010001 0x0000002b
					       0x00010002 0x00000033
					       0x00010003 0x0000003b
					       0x00010004 0x00000043
					       0x00010005 0x0000004b
					       0x00010006 0x00000054
					       0x00010007 0x0000005c
					       0x00010008 0x00000064
					       0x00010009 0x0000006c

					       0x00020000 0x00000021
					       0x00020001 0x0000002c
					       0x00020002 0x00000036
					       0x00020003 0x00000040
					       0x00020004 0x0000004b
					       0x00020005 0x00000055
					       0x00020006 0x0000005f

					       0x00030000 0x00000013
					       0x00030001 0x0000001d
					       0x00030002 0x00000028
					       0x00030003 0x00000032
					       0x00030004 0x0000003d
					       0x00030005 0x00000047
					       0x00030006 0x00000052
					       0x00030007 0x0000005c>;
			#thermal-sensor-cells = <1>;
		};

		qman: qman@1880000 {
			compatible = "fsl,qman";
			reg = <0x0 0x1880000 0x0 0x10000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			memory-region = <&qman_fqd &qman_pfdr>;
		};

		bman: bman@1890000 {
			compatible = "fsl,bman";
			reg = <0x0 0x1890000 0x0 0x10000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			memory-region = <&bman_fbpr>;
		};

		bportals: bman-portals@508000000 {
			ranges = <0x0 0x5 0x08000000 0x8000000>;
		};

		qportals: qman-portals@500000000 {
			ranges = <0x0 0x5 0x00000000 0x8000000>;
		};

		dspi0: spi@2100000 {
			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <0 64 0x4>;
			clock-names = "dspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		dspi1: spi@2110000 {
			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2110000 0x0 0x10000>;
			interrupts = <0 65 0x4>;
			clock-names = "dspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		i2c0: i2c@2180000 {
			compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <0 56 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			dmas = <&edma0 1 38>,
			       <&edma0 1 39>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		i2c1: i2c@2190000 {
			compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <0 57 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
			status = "disabled";
		};

		i2c2: i2c@21a0000 {
			compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21a0000 0x0 0x10000>;
			interrupts = <0 58 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
			status = "disabled";
		};

		i2c3: i2c@21b0000 {
			compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21b0000 0x0 0x10000>;
			interrupts = <0 59 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0500 0x0 0x100>;
			interrupts = <0 54 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0600 0x0 0x100>;
			interrupts = <0 54 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
		};

		duart2: serial@21d0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0500 0x0 0x100>;
			interrupts = <0 55 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
		};

		duart3: serial@21d0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0600 0x0 0x100>;
			interrupts = <0 55 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
		};

		gpio1: gpio@2300000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <0 66 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2310000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <0 67 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2320000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <0 68 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@2330000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2330000 0x0 0x10000>;
			interrupts = <0 134 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		uqe: uqe@2400000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,qe", "simple-bus";
			ranges = <0x0 0x0 0x2400000 0x40000>;
			reg = <0x0 0x2400000 0x0 0x480>;
			brg-frequency = <100000000>;
			bus-frequency = <200000000>;
			fsl,qe-num-riscs = <1>;
			fsl,qe-num-snums = <28>;

			qeic: qeic@80 {
				compatible = "fsl,qe-ic";
				reg = <0x80 0x80>;
				#address-cells = <0>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			};

			si1: si@700 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,ls1043-qe-si",
						"fsl,t1040-qe-si";
				reg = <0x700 0x80>;
			};

			siram1: siram@1000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,ls1043-qe-siram",
						"fsl,t1040-qe-siram";
				reg = <0x1000 0x800>;
			};

			ucc@2000 {
				cell-index = <1>;
				reg = <0x2000 0x200>;
				interrupts = <32>;
				interrupt-parent = <&qeic>;
			};

			ucc@2200 {
				cell-index = <3>;
				reg = <0x2200 0x200>;
				interrupts = <34>;
				interrupt-parent = <&qeic>;
			};

			muram@10000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,qe-muram", "fsl,cpm-muram";
				ranges = <0x0 0x10000 0x6000>;

				data-only@0 {
					compatible = "fsl,qe-muram-data",
					"fsl,cpm-muram-data";
					reg = <0x0 0x6000>;
				};
			};
		};

		lpuart0: serial@2950000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2950000 0x0 0x1000>;
			interrupts = <0 48 0x4>;
			clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart1: serial@2960000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2960000 0x0 0x1000>;
			interrupts = <0 49 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart2: serial@2970000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2970000 0x0 0x1000>;
			interrupts = <0 50 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart3: serial@2980000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2980000 0x0 0x1000>;
			interrupts = <0 51 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart4: serial@2990000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2990000 0x0 0x1000>;
			interrupts = <0 52 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart5: serial@29a0000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x29a0000 0x0 0x1000>;
			interrupts = <0 53 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			clock-names = "ipg";
			status = "disabled";
		};

		wdog0: watchdog@2ad0000 {
			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
			reg = <0x0 0x2ad0000 0x0 0x10000>;
			interrupts = <0 83 0x4>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			clock-names = "wdog";
			big-endian;
		};

		edma0: dma-controller@2c00000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x2c00000 0x0 0x10000>,
			      <0x0 0x2c10000 0x0 0x10000>,
			      <0x0 0x2c20000 0x0 0x10000>;
			interrupts = <0 103 0x4>,
				     <0 103 0x4>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			big-endian;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
		};

		aux_bus: aux_bus {
			#address-cells = <2>;
			#size-cells = <2>;
			compatible = "simple-bus";
			ranges;
			dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;

			usb0: usb@2f00000 {
				compatible = "snps,dwc3";
				reg = <0x0 0x2f00000 0x0 0x10000>;
				interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
				dr_mode = "host";
				snps,quirk-frame-length-adjustment = <0x20>;
				snps,dis_rxdet_inp3_quirk;
				usb3-lpm-capable;
				snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
				status = "disabled";
			};

			usb1: usb@3000000 {
				compatible = "snps,dwc3";
				reg = <0x0 0x3000000 0x0 0x10000>;
				interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
				dr_mode = "host";
				snps,quirk-frame-length-adjustment = <0x20>;
				snps,dis_rxdet_inp3_quirk;
				usb3-lpm-capable;
				snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
				status = "disabled";
			};

			usb2: usb@3100000 {
				compatible = "snps,dwc3";
				reg = <0x0 0x3100000 0x0 0x10000>;
				interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
				dr_mode = "host";
				snps,quirk-frame-length-adjustment = <0x20>;
				snps,dis_rxdet_inp3_quirk;
				usb3-lpm-capable;
				snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
				status = "disabled";
			};

			sata: sata@3200000 {
				compatible = "fsl,ls1043a-ahci";
				reg = <0x0 0x3200000 0x0 0x10000>,
					<0x0 0x20140520 0x0 0x4>;
				reg-names = "ahci", "sata-ecc";
				interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
						    QORIQ_CLK_PLL_DIV(1)>;
				dma-coherent;
			};
		};

		msi1: msi-controller1@1571000 {
			compatible = "fsl,ls1043a-msi";
			reg = <0x0 0x1571000 0x0 0x8>;
			msi-controller;
			interrupts = <0 116 0x4>;
		};

		msi2: msi-controller2@1572000 {
			compatible = "fsl,ls1043a-msi";
			reg = <0x0 0x1572000 0x0 0x8>;
			msi-controller;
			interrupts = <0 126 0x4>;
		};

		msi3: msi-controller3@1573000 {
			compatible = "fsl,ls1043a-msi";
			reg = <0x0 0x1573000 0x0 0x8>;
			msi-controller;
			interrupts = <0 160 0x4>;
		};

		pcie1: pcie@3400000 {
			compatible = "fsl,ls1043a-pcie";
			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
			      <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>,
				     <0 118 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pme", "aer";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-viewport = <6>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi1>, <&msi2>, <&msi3>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
					<0000 0 0 2 &gic 0 111 0x4>,
					<0000 0 0 3 &gic 0 112 0x4>,
					<0000 0 0 4 &gic 0 113 0x4>;
			fsl,pcie-scfg = <&scfg 0>;
			big-endian;
			status = "disabled";
		};

		pcie2: pcie@3500000 {
			compatible = "fsl,ls1043a-pcie";
			reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
			      <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>,
				     <0 128 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pme", "aer";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-viewport = <6>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi1>, <&msi2>, <&msi3>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
					<0000 0 0 2 &gic 0 121 0x4>,
					<0000 0 0 3 &gic 0 122 0x4>,
					<0000 0 0 4 &gic 0 123 0x4>;
			fsl,pcie-scfg = <&scfg 1>;
			big-endian;
			status = "disabled";
		};

		pcie3: pcie@3600000 {
			compatible = "fsl,ls1043a-pcie";
			reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
			      <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>,
				     <0 162 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pme", "aer";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-viewport = <6>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi1>, <&msi2>, <&msi3>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
					<0000 0 0 2 &gic 0 155 0x4>,
					<0000 0 0 3 &gic 0 156 0x4>,
					<0000 0 0 4 &gic 0 157 0x4>;
			fsl,pcie-scfg = <&scfg 2>;
			big-endian;
			status = "disabled";
		};

		qdma: dma-controller@8380000 {
			compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "qdma-error", "qdma-queue0",
				"qdma-queue1", "qdma-queue2", "qdma-queue3";
			dma-channels = <8>;
			block-number = <1>;
			block-offset = <0x10000>;
			fsl,dma-queues = <2>;
			status-sizes = <64>;
			queue-sizes = <64 64>;
			big-endian;
		};

		rcpm: power-controller@1ee2140 {
			compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
			reg = <0x0 0x1ee2140 0x0 0x4>;
			#fsl,rcpm-wakeup-cells = <1>;
		};

		ftm_alarm0: timer@29d0000 {
			compatible = "fsl,ls1043a-ftm-alarm";
			reg = <0x0 0x29d0000 0x0 0x10000>;
			fsl,rcpm-wakeup = <&rcpm 0x20000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
		};
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

};

#include "qoriq-qman-portals.dtsi"
#include "qoriq-bman-portals.dtsi"


code:
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * QorIQ FMan v3 device tree nodes for ls1046
 *
 * Copyright 2015-2016 Freescale Semiconductor Inc.
 *
 */

&soc {

/* include used FMan blocks */
#include "qoriq-fman3-0.dtsi"
#include "qoriq-fman3-0-1g-0.dtsi"
#include "qoriq-fman3-0-1g-1.dtsi"
#include "qoriq-fman3-0-1g-2.dtsi"
#include "qoriq-fman3-0-1g-3.dtsi"
#include "qoriq-fman3-0-1g-4.dtsi"
#include "qoriq-fman3-0-1g-5.dtsi"
#include "qoriq-fman3-0-10g-0.dtsi"
#include "qoriq-fman3-0-10g-1.dtsi"
};

&fman0 {
	/* these aliases provide the FMan ports mapping */
	enet0: ethernet@e0000 {
		pcsphy-handle = <&qsgmiib_pcs3>;
		pcs-handle-names = "qsgmii";
	};

	enet1: ethernet@e2000 {
	};

	enet2: ethernet@e4000 {
	};

	enet3: ethernet@e6000 {
	};

	enet4: ethernet@e8000 {
		pcsphy-handle = <&pcsphy4>, <&qsgmiib_pcs1>;
		pcs-handle-names = "sgmii", "qsgmii";
	};

	enet5: ethernet@ea000 {
		pcsphy-handle = <&pcsphy5>, <&pcsphy5>;
		pcs-handle-names = "sgmii", "qsgmii";
	};

	enet6: ethernet@f0000 {
	};

	enet7: ethernet@f2000 {
		pcsphy-handle = <&pcsphy7>, <&qsgmiib_pcs2>, <&pcsphy7>;
		pcs-handle-names = "sgmii", "qsgmii", "xfi";
	};

	mdio@eb000 {
		qsgmiib_pcs1: ethernet-pcs@1 {
			compatible = "fsl,lynx-pcs";
			reg = <0x1>;
		};

		qsgmiib_pcs2: ethernet-pcs@2 {
			compatible = "fsl,lynx-pcs";
			reg = <0x2>;
		};

		qsgmiib_pcs3: ethernet-pcs@3 {
			compatible = "fsl,lynx-pcs";
			reg = <0x3>;
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
 *
 * Copyright 2019 NXP.
 *
 */

/dts-v1/;

#include "fsl-ls1046a.dtsi"

/ {
	model = "LS1046A FRWY Board";
	compatible = "fsl,ls1046a-frwy", "fsl,ls1046a";

	aliases {
		serial0 = &duart0;
		serial1 = &duart1;
		serial2 = &duart2;
		serial3 = &duart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	sb_3v3: regulator-sb3v3 {
		compatible = "regulator-fixed";
		regulator-name = "LT8642SEV-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&duart2 {
	status = "okay";
};

&duart3 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	i2c-mux@77 {
		compatible = "nxp,pca9546";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			power-monitor@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};

			temperature-sensor@4c {
				compatible = "nxp,sa56004";
				reg = <0x4c>;
				vcc-supply = <&sb_3v3>;
			};

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
			};

			eeprom@52 {
				compatible = "onnn,cat24c04", "atmel,24c04";
				reg = <0x52>;
			};
		};
	};
};

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	/* NAND Flash */
	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;
	status = "okay";

	nand@0,0 {
		compatible = "fsl,ifc-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x0 0x0 0x10000>;
	};

};

&qspi {
	status = "okay";

	mt25qu512a0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
		reg = <0>;
	};
};

#include "fsl-ls1046-post.dtsi"

&fman0 {
	ethernet@e0000 {
		phy-handle = <&qsgmii_phy4>;
		phy-connection-type = "qsgmii";
	};

	ethernet@e8000 {
		phy-handle = <&qsgmii_phy2>;
		phy-connection-type = "qsgmii";
	};

	ethernet@ea000 {
		phy-handle = <&qsgmii_phy1>;
		phy-connection-type = "qsgmii";
	};

	ethernet@f2000 {
		phy-handle = <&qsgmii_phy3>;
		phy-connection-type = "qsgmii";
	};

	mdio@fd000 {
		qsgmii_phy1: ethernet-phy@1c {
			reg = <0x1c>;
		};

		qsgmii_phy2: ethernet-phy@1d {
			reg = <0x1d>;
		};

		qsgmii_phy3: ethernet-phy@1e {
			reg = <0x1e>;
		};

		qsgmii_phy4: ethernet-phy@1f {
			reg = <0x1f>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2018-2019 NXP
 *
 * Shaohui Xie <Shaohui.Xie@nxp.com>
 */

/dts-v1/;

#include "fsl-ls1046a.dtsi"

/ {
	model = "LS1046A QDS Board";
	compatible = "fsl,ls1046a-qds", "fsl,ls1046a";

	aliases {
		emi1-slot1 = &ls1046mdio_s1;
		emi1-slot2 = &ls1046mdio_s2;
		emi1-slot4 = &ls1046mdio_s4;
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
		qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
		qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
		qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
		serial0 = &duart0;
		serial1 = &duart1;
		serial2 = &duart2;
		serial3 = &duart3;
		sgmii-s1-p1 = &sgmii_phy_s1_p1;
		sgmii-s1-p2 = &sgmii_phy_s1_p2;
		sgmii-s1-p3 = &sgmii_phy_s1_p3;
		sgmii-s1-p4 = &sgmii_phy_s1_p4;
		sgmii-s4-p1 = &sgmii_phy_s4_p1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&dspi {
	bus-num = <0>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "n25q128a11", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;
	};

	flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "sst25wf040b", "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <1>;
		spi-max-frequency = <10000000>;
	};

	flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "en25s64", "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <2>;
		spi-max-frequency = <10000000>;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	pca9547@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			ina220@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};

			ina220@41 {
				compatible = "ti,ina220";
				reg = <0x41>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
				/* IRQ10_B */
				interrupts = <0 150 0x4>;
			};

			eeprom@56 {
				compatible = "atmel,24c512";
				reg = <0x56>;
			};

			eeprom@57 {
				compatible = "atmel,24c512";
				reg = <0x57>;
			};

			temp-sensor@4c {
				compatible = "adi,adt7461a";
				reg = <0x4c>;
			};
		};
	};
};

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	/* NOR, NAND Flashes and FPGA on board */
	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
		  0x1 0x0 0x0 0x7e800000 0x00010000
		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
	status = "okay";

	nor@0,0 {
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x8000000>;
		big-endian;
		bank-width = <2>;
		device-width = <1>;
	};

	nand@1,0 {
		compatible = "fsl,ifc-nand";
		reg = <0x1 0x0 0x10000>;
	};

	fpga: board-control@2,0 {
		compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
		reg = <0x2 0x0 0x0000100>;
		ranges = <0 2 0 0x100>;
	};
};

&lpuart0 {
	status = "okay";
};

&qspi {
	status = "okay";

	qflash0: flash@0 {
		compatible = "spansion,m25p80";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		reg = <0>;
	};
};

#include "fsl-ls1046-post.dtsi"

&fman0 {
	ethernet@e0000 {
		phy-handle = <&qsgmii_phy_s2_p1>;
		phy-connection-type = "sgmii";
	};

	ethernet@e2000 {
		phy-handle = <&sgmii_phy_s4_p1>;
		phy-connection-type = "sgmii";
	};

	ethernet@e4000 {
		phy-handle = <&rgmii_phy1>;
		phy-connection-type = "rgmii";
	};

	ethernet@e6000 {
		phy-handle = <&rgmii_phy2>;
		phy-connection-type = "rgmii";
	};

	ethernet@e8000 {
		phy-handle = <&sgmii_phy_s1_p3>;
		phy-connection-type = "sgmii";
	};

	ethernet@ea000 {
		phy-handle = <&sgmii_phy_s1_p4>;
		phy-connection-type = "sgmii";
	};

	ethernet@f0000 { /* DTSEC9/10GEC1 */
		phy-handle = <&sgmii_phy_s1_p1>;
		phy-connection-type = "xgmii";
	};

	ethernet@f2000 { /* DTSEC10/10GEC2 */
		phy-handle = <&sgmii_phy_s1_p2>;
		phy-connection-type = "xgmii";
	};
};

&fpga {
	#address-cells = <1>;
	#size-cells = <1>;

	mdio-mux-emi1 {
		compatible = "mdio-mux-mmioreg", "mdio-mux";
		mdio-parent-bus = <&mdio0>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x54 1>;    /* BRDCFG4 */
		mux-mask = <0xe0>; /* EMI1 */

		/* On-board RGMII1 PHY */
		ls1046mdio0: mdio@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			rgmii_phy1: ethernet-phy@1 { /* MAC3 */
				reg = <0x1>;
			};
		};

		/* On-board RGMII2 PHY */
		ls1046mdio1: mdio@1 {
			reg = <0x20>;
			#address-cells = <1>;
			#size-cells = <0>;

			rgmii_phy2: ethernet-phy@2 { /* MAC4 */
				reg = <0x2>;
			};
		};

		/* Slot 1 */
		ls1046mdio_s1: mdio@2 {
			reg = <0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sgmii_phy_s1_p1: ethernet-phy@1c {
				reg = <0x1c>;
			};

			sgmii_phy_s1_p2: ethernet-phy@1d {
				reg = <0x1d>;
			};

			sgmii_phy_s1_p3: ethernet-phy@1e {
				reg = <0x1e>;
			};

			sgmii_phy_s1_p4: ethernet-phy@1f {
				reg = <0x1f>;
			};
		};

		/* Slot 2 */
		ls1046mdio_s2: mdio@3 {
			reg = <0x60>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			qsgmii_phy_s2_p1: ethernet-phy@8 {
				reg = <0x8>;
			};

			qsgmii_phy_s2_p2: ethernet-phy@9 {
				reg = <0x9>;
			};

			qsgmii_phy_s2_p3: ethernet-phy@a {
				reg = <0xa>;
			};

			qsgmii_phy_s2_p4: ethernet-phy@b {
				reg = <0xb>;
			};
		};

		/* Slot 4 */
		ls1046mdio_s4: mdio@5 {
			reg = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sgmii_phy_s4_p1: ethernet-phy@1c {
				reg = <0x1c>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2019-2020 NXP
 *
 * Mingkai Hu <mingkai.hu@nxp.com>
 */

/dts-v1/;

#include "fsl-ls1046a.dtsi"

/ {
	model = "LS1046A RDB Board";
	compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";

	aliases {
		serial0 = &duart0;
		serial1 = &duart1;
		serial2 = &duart2;
		serial3 = &duart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&esdhc {
	mmc-hs200-1_8v;
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
};

&i2c0 {
	status = "okay";

	ina220@40 {
		compatible = "ti,ina220";
		reg = <0x40>;
		shunt-resistor = <1000>;
	};

	temp-sensor@4c {
		compatible = "adi,adt7461";
		reg = <0x4c>;
	};

	eeprom@52 {
		compatible = "onnn,cat24c05", "atmel,24c04";
		reg = <0x52>;
	};
};

&i2c3 {
	status = "okay";

	rtc@51 {
		compatible = "nxp,pcf2129";
		reg = <0x51>;
		/* IRQ_RTC_B -> IRQ05, active low */
		interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
	};
};

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	/* NAND Flashe and CPLD on board */
	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
	status = "okay";

	nand@0,0 {
		compatible = "fsl,ifc-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x0 0x0 0x10000>;
	};

	cpld: board-control@2,0 {
		compatible = "fsl,ls1046ardb-cpld";
		reg = <0x2 0x0 0x0000100>;
	};
};

&qspi {
	status = "okay";

	s25fs512s0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
		reg = <0>;
	};

	s25fs512s1: flash@1 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
		reg = <1>;
	};
};

&usb1 {
	dr_mode = "otg";
};

#include "fsl-ls1046-post.dtsi"

&fman0 {
	ethernet@e4000 {
		phy-handle = <&rgmii_phy1>;
		phy-connection-type = "rgmii-id";
	};

	ethernet@e6000 {
		phy-handle = <&rgmii_phy2>;
		phy-connection-type = "rgmii-id";
	};

	ethernet@e8000 {
		phy-handle = <&sgmii_phy1>;
		phy-connection-type = "sgmii";
	};

	ethernet@ea000 {
		phy-handle = <&sgmii_phy2>;
		phy-connection-type = "sgmii";
	};

	ethernet@f0000 { /* 10GEC1 */
		phy-handle = <&aqr106_phy>;
		phy-connection-type = "xgmii";
	};

	ethernet@f2000 { /* 10GEC2 */
		fixed-link = <0 1 1000 0 0>;
		phy-connection-type = "xgmii";
	};

	mdio@fc000 {
		rgmii_phy1: ethernet-phy@1 {
			reg = <0x1>;
		};

		rgmii_phy2: ethernet-phy@2 {
			reg = <0x2>;
		};

		sgmii_phy1: ethernet-phy@3 {
			reg = <0x3>;
		};

		sgmii_phy2: ethernet-phy@4 {
			reg = <0x4>;
		};
	};

	mdio@fd000 {
		aqr106_phy: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c45";
			interrupts = <0 131 4>;
			reg = <0x0>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for NXP Layerscape-1046A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2018, 2020 NXP
 *
 * Mingkai Hu <mingkai.hu@nxp.com>
 */

#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "fsl,ls1046a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		crypto = &crypto;
		fman0 = &fman0;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		ethernet4 = &enet4;
		ethernet5 = &enet5;
		ethernet6 = &enet6;
		ethernet7 = &enet7;
		rtc1 = &ftm_alarm0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x1>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x2>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x3>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		l2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	idle-states {
		/*
		 * PSCI node is not added default, U-boot will add missing
		 * parts if it determines to use PSCI.
		 */
		entry-method = "psci";

		CPU_PH20: cpu-ph20 {
			compatible = "arm,idle-state";
			idle-state-name = "PH20";
			arm,psci-suspend-param = <0x0>;
			entry-latency-us = <1000>;
			exit-latency-us = <1000>;
			min-residency-us = <3000>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* Real size will be filled by bootloader */
		reg = <0x0 0x80000000 0x0 0x0>;
	};

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	reboot {
		compatible = "syscon-reboot";
		regmap = <&dcfg>;
		offset = <0xb0>;
		mask = <0x02>;
	};

	thermal-zones {
		ddr-controller {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 0>;

			trips {
				ddr-ctrler-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				ddr-ctrler-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		serdes {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 1>;

			trips {
				serdes-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				serdes-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		fman {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 2>;

			trips {
				fman-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				fman-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		core-cluster {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 3>;

			trips {
				core_cluster_alert: core-cluster-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				core_cluster_crit: core-cluster-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&core_cluster_alert>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		sec {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 4>;

			trips {
				sec-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				sec-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
					  IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
	};

	gic: interrupt-controller@1400000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x1410000 0 0x10000>, /* GICD */
		      <0x0 0x1420000 0 0x20000>, /* GICC */
		      <0x0 0x1440000 0 0x20000>, /* GICH */
		      <0x0 0x1460000 0 0x20000>; /* GICV */
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
					 IRQ_TYPE_LEVEL_LOW)>;
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
		dma-coherent;

		ddr: memory-controller@1080000 {
			compatible = "fsl,qoriq-memory-controller";
			reg = <0x0 0x1080000 0x0 0x1000>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
		};

		ifc: memory-controller@1530000 {
			compatible = "fsl,ifc";
			reg = <0x0 0x1530000 0x0 0x10000>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		qspi: spi@1550000 {
			compatible = "fsl,ls1021a-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x1550000 0x0 0x10000>,
				<0x0 0x40000000 0x0 0x10000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "qspi_en", "qspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		esdhc: esdhc@1560000 {
			compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
			reg = <0x0 0x1560000 0x0 0x10000>;
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			big-endian;
			bus-width = <4>;
		};

		scfg: scfg@1570000 {
			compatible = "fsl,ls1046a-scfg", "syscon";
			reg = <0x0 0x1570000 0x0 0x10000>;
			big-endian;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x1570000 0x10000>;

			extirq: interrupt-controller@1ac {
				compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq";
				#interrupt-cells = <2>;
				#address-cells = <0>;
				interrupt-controller;
				reg = <0x1ac 4>;
				interrupt-map =
					<0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
					<1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
					<2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
					<3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
					<4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
					<5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
					<6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
					<7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
					<8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
					<9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
					<10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
					<11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-map-mask = <0xf 0x0>;
			};
		};

		crypto: crypto@1700000 {
			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
				     "fsl,sec-v4.0";
			fsl,sec-era = <8>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x00 0x1700000 0x100000>;
			reg = <0x00 0x1700000 0x0 0x100000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;

			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x10000 0x10000>;
				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x20000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x30000 0x10000>;
				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x40000 0x10000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		qman: qman@1880000 {
			compatible = "fsl,qman";
			reg = <0x0 0x1880000 0x0 0x10000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			memory-region = <&qman_fqd &qman_pfdr>;

		};

		bman: bman@1890000 {
			compatible = "fsl,bman";
			reg = <0x0 0x1890000 0x0 0x10000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			memory-region = <&bman_fbpr>;

		};

		qportals: qman-portals@500000000 {
			ranges = <0x0 0x5 0x00000000 0x8000000>;
		};

		bportals: bman-portals@508000000 {
			ranges = <0x0 0x5 0x08000000 0x8000000>;
		};

		sfp: efuse@1e80000 {
			compatible = "fsl,ls1021a-sfp";
			reg = <0x0 0x1e80000 0x0 0x10000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "sfp";
		};

		dcfg: dcfg@1ee0000 {
			compatible = "fsl,ls1046a-dcfg", "syscon";
			reg = <0x0 0x1ee0000 0x0 0x1000>;
			big-endian;
		};

		clockgen: clocking@1ee1000 {
			compatible = "fsl,ls1046a-clockgen";
			reg = <0x0 0x1ee1000 0x0 0x1000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		tmu: tmu@1f00000 {
			compatible = "fsl,qoriq-tmu";
			reg = <0x0 0x1f00000 0x0 0x10000>;
			interrupts = <0 33 0x4>;
			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
			fsl,tmu-calibration =
				/* Calibration data group 1 */
				<0x00000000 0x00000023
				0x00000001 0x00000029
				0x00000002 0x0000002f
				0x00000003 0x00000036
				0x00000004 0x0000003c
				0x00000005 0x00000042
				0x00000006 0x00000049
				0x00000007 0x0000004f
				0x00000008 0x00000055
				0x00000009 0x0000005c
				0x0000000a 0x00000062
				0x0000000b 0x00000068
				/* Calibration data group 2 */
				0x00010000 0x00000022
				0x00010001 0x0000002a
				0x00010002 0x00000032
				0x00010003 0x0000003a
				0x00010004 0x00000042
				0x00010005 0x0000004a
				0x00010006 0x00000052
				0x00010007 0x0000005a
				0x00010008 0x00000062
				0x00010009 0x0000006a
				/* Calibration data group 3 */
				0x00020000 0x00000021
				0x00020001 0x0000002b
				0x00020002 0x00000035
				0x00020003 0x0000003e
				0x00020004 0x00000048
				0x00020005 0x00000052
				0x00020006 0x0000005c
				/* Calibration data group 4 */
				0x00030000 0x00000011
				0x00030001 0x0000001a
				0x00030002 0x00000024
				0x00030003 0x0000002e
				0x00030004 0x00000038
				0x00030005 0x00000042
				0x00030006 0x0000004c
				0x00030007 0x00000056>;
			big-endian;
			#thermal-sensor-cells = <1>;
		};

		dspi: spi@2100000 {
			compatible = "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		i2c0: i2c@2180000 {
			compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			dmas = <&edma0 1 38>,
			       <&edma0 1 39>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		i2c1: i2c@2190000 {
			compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			scl-gpios = <&gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
			status = "disabled";
		};

		i2c2: i2c@21a0000 {
			compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21a0000 0x0 0x10000>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			scl-gpios = <&gpio3 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
			status = "disabled";
		};

		i2c3: i2c@21b0000 {
			compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21b0000 0x0 0x10000>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			scl-gpios = <&gpio3 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0500 0x0 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0600 0x0 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		duart2: serial@21d0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0500 0x0 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		duart3: serial@21d0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0600 0x0 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		gpio0: gpio@2300000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@2310000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2320000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2330000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2330000 0x0 0x10000>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		lpuart0: serial@2950000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2950000 0x0 0x1000>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart1: serial@2960000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2960000 0x0 0x1000>;
			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart2: serial@2970000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2970000 0x0 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart3: serial@2980000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2980000 0x0 0x1000>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart4: serial@2990000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2990000 0x0 0x1000>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart5: serial@29a0000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x29a0000 0x0 0x1000>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			clock-names = "ipg";
			status = "disabled";
		};

		wdog0: watchdog@2ad0000 {
			compatible = "fsl,imx21-wdt";
			reg = <0x0 0x2ad0000 0x0 0x10000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			big-endian;
		};

		edma0: dma-controller@2c00000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x2c00000 0x0 0x10000>,
			      <0x0 0x2c10000 0x0 0x10000>,
			      <0x0 0x2c20000 0x0 0x10000>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			big-endian;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
		};

		aux_bus: aux_bus {
			#address-cells = <2>;
			#size-cells = <2>;
			compatible = "simple-bus";
			ranges;
			dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;

			usb0: usb@2f00000 {
				compatible = "snps,dwc3";
				reg = <0x0 0x2f00000 0x0 0x10000>;
				interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
				dr_mode = "host";
				snps,quirk-frame-length-adjustment = <0x20>;
				snps,dis_rxdet_inp3_quirk;
				snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
				usb3-lpm-capable;
			};

			usb1: usb@3000000 {
				compatible = "snps,dwc3";
				reg = <0x0 0x3000000 0x0 0x10000>;
				interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
				dr_mode = "host";
				snps,quirk-frame-length-adjustment = <0x20>;
				snps,dis_rxdet_inp3_quirk;
				snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
				usb3-lpm-capable;
			};

			usb2: usb@3100000 {
				compatible = "snps,dwc3";
				reg = <0x0 0x3100000 0x0 0x10000>;
				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
				dr_mode = "host";
				snps,quirk-frame-length-adjustment = <0x20>;
				snps,dis_rxdet_inp3_quirk;
				snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
				usb3-lpm-capable;
			};

			sata: sata@3200000 {
				compatible = "fsl,ls1046a-ahci";
				reg = <0x0 0x3200000 0x0 0x10000>,
					<0x0 0x20140520 0x0 0x4>;
				reg-names = "ahci", "sata-ecc";
				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
						    QORIQ_CLK_PLL_DIV(2)>;
			};
		};

		msi1: msi-controller@1580000 {
			compatible = "fsl,ls1046a-msi";
			msi-controller;
			reg = <0x0 0x1580000 0x0 0x10000>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
		};

		msi2: msi-controller@1590000 {
			compatible = "fsl,ls1046a-msi";
			msi-controller;
			reg = <0x0 0x1590000 0x0 0x10000>;
			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
		};

		msi3: msi-controller@15a0000 {
			compatible = "fsl,ls1046a-msi";
			msi-controller;
			reg = <0x0 0x15a0000 0x0 0x10000>;
			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
		};

		pcie1: pcie@3400000 {
			compatible = "fsl,ls1046a-pcie";
			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
			      <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
			interrupt-names = "aer", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-viewport = <8>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi1>, <&msi2>, <&msi3>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
			status = "disabled";
		};

		pcie_ep1: pcie_ep@3400000 {
			compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
			reg = <0x00 0x03400000 0x0 0x00100000>,
			      <0x40 0x00000000 0x8 0x00000000>;
			reg-names = "regs", "addr_space";
			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pme";
			num-ib-windows = <6>;
			num-ob-windows = <8>;
			big-endian;
			status = "disabled";
		};

		pcie2: pcie@3500000 {
			compatible = "fsl,ls1046a-pcie";
			reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
			      <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
			interrupt-names = "aer", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-viewport = <8>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi2>, <&msi3>, <&msi1>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
			status = "disabled";
		};

		pcie_ep2: pcie_ep@3500000 {
			compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
			reg = <0x00 0x03500000 0x0 0x00100000>,
			      <0x48 0x00000000 0x8 0x00000000>;
			reg-names = "regs", "addr_space";
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pme";
			num-ib-windows = <6>;
			num-ob-windows = <8>;
			big-endian;
			status = "disabled";
		};

		pcie3: pcie@3600000 {
			compatible = "fsl,ls1046a-pcie";
			reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
			      <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
			interrupt-names = "aer", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-viewport = <8>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi3>, <&msi1>, <&msi2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
			status = "disabled";
		};

		pcie_ep3: pcie_ep@3600000 {
			compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
			reg = <0x00 0x03600000 0x0 0x00100000>,
			      <0x50 0x00000000 0x8 0x00000000>;
			reg-names = "regs", "addr_space";
			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "pme";
			num-ib-windows = <6>;
			num-ob-windows = <8>;
			big-endian;
			status = "disabled";
		};

		qdma: dma-controller@8380000 {
			compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
			reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
			      <0x0 0x8390000 0x0 0x10000>, /* Status regs */
			      <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "qdma-error", "qdma-queue0",
				"qdma-queue1", "qdma-queue2", "qdma-queue3";
			dma-channels = <8>;
			block-number = <1>;
			block-offset = <0x10000>;
			fsl,dma-queues = <2>;
			status-sizes = <64>;
			queue-sizes = <64 64>;
			big-endian;
		};

		rcpm: power-controller@1ee2140 {
			compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
			reg = <0x0 0x1ee2140 0x0 0x4>;
			#fsl,rcpm-wakeup-cells = <1>;
		};

		ftm_alarm0: timer@29d0000 {
			compatible = "fsl,ls1046a-ftm-alarm";
			reg = <0x0 0x29d0000 0x0 0x10000>;
			fsl,rcpm-wakeup = <&rcpm 0x20000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		bman_fbpr: bman-fbpr {
			compatible = "shared-dma-pool";
			size = <0 0x1000000>;
			alignment = <0 0x1000000>;
			no-map;
		};

		qman_fqd: qman-fqd {
			compatible = "shared-dma-pool";
			size = <0 0x800000>;
			alignment = <0 0x800000>;
			no-map;
		};

		qman_pfdr: qman-pfdr {
			compatible = "shared-dma-pool";
			size = <0 0x2000000>;
			alignment = <0 0x2000000>;
			no-map;
		};
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};

#include "qoriq-qman-portals.dtsi"
#include "qoriq-bman-portals.dtsi"


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for NXP LS1088A QDS Board.
 *
 * Copyright 2017 NXP
 *
 * Harninder Rai <harninder.rai@nxp.com>
 *
 */

/dts-v1/;

#include "fsl-ls1088a.dtsi"

/ {
	model = "LS1088A QDS Board";
	compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
};

&dspi {
	bus-num = <0>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <1000000>;
	};

	flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		spi-max-frequency = <3500000>;
		reg = <1>;
	};

	flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		spi-max-frequency = <3500000>;
		reg = <2>;
	};
};

&i2c0 {
	status = "okay";

	i2c-switch@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			ina220@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};

			ina220@41 {
				compatible = "ti,ina220";
				reg = <0x41>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			temp-sensor@4c {
				compatible = "adi,adt7461a";
				reg = <0x4c>;
			};

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
				/* IRQ10_B */
				interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
			};

			eeprom@56 {
				compatible = "atmel,24c512";
				reg = <0x56>;
			};

			eeprom@57 {
				compatible = "atmel,24c512";
				reg = <0x57>;
			};
		};
	};
};

&ifc {
	ranges = <0 0 0x5 0x80000000 0x08000000
		  2 0 0x5 0x30000000 0x00010000
		  3 0 0x5 0x20000000 0x00010000>;
	status = "okay";

	nor@0,0 {
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x8000000>;
		bank-width = <2>;
		device-width = <1>;
	};

	nand@2,0 {
		compatible = "fsl,ifc-nand";
		reg = <0x2 0x0 0x10000>;
	};

	fpga: board-control@3,0 {
		compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
		reg = <0x3 0x0 0x0000100>;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&esdhc {
	status = "okay";
};

&qspi {
	status = "okay";

	s25fs512s0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
		reg = <0>;
	};

	s25fs512s1: flash@1 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
		reg = <1>;
	};
};

&sata {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for NXP LS1088A RDB Board.
 *
 * Copyright 2017-2020 NXP
 *
 * Harninder Rai <harninder.rai@nxp.com>
 *
 */

/dts-v1/;

#include "fsl-ls1088a.dtsi"

/ {
	model = "LS1088A RDB Board";
	compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
};

&dpmac2 {
	phy-handle = <&mdio2_aquantia_phy>;
	phy-connection-type = "10gbase-r";
	pcs-handle = <&pcs2>;
};

&dpmac3 {
	phy-handle = <&mdio1_phy5>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs3_0>;
};

&dpmac4 {
	phy-handle = <&mdio1_phy6>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs3_1>;
};

&dpmac5 {
	phy-handle = <&mdio1_phy7>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs3_2>;
};

&dpmac6 {
	phy-handle = <&mdio1_phy8>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs3_3>;
};

&dpmac7 {
	phy-handle = <&mdio1_phy1>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs7_0>;
};

&dpmac8 {
	phy-handle = <&mdio1_phy2>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs7_1>;
};

&dpmac9 {
	phy-handle = <&mdio1_phy3>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs7_2>;
};

&dpmac10 {
	phy-handle = <&mdio1_phy4>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs7_3>;
};

&emdio1 {
	status = "okay";

	mdio1_phy5: ethernet-phy@c {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0xc>;
	};

	mdio1_phy6: ethernet-phy@d {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0xd>;
	};

	mdio1_phy7: ethernet-phy@e {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0xe>;
	};

	mdio1_phy8: ethernet-phy@f {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0xf>;
	};

	mdio1_phy1: ethernet-phy@1c {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x1c>;
	};

	mdio1_phy2: ethernet-phy@1d {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x1d>;
	};

	mdio1_phy3: ethernet-phy@1e {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x1e>;
	};

	mdio1_phy4: ethernet-phy@1f {
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x1f>;
	};
};

&emdio2 {
	status = "okay";

	mdio2_aquantia_phy: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c45";
		interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x0>;
	};
};

&i2c0 {
	status = "okay";

	i2c-switch@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			ina220@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			temp-sensor@4c {
				compatible = "adi,adt7461a";
				reg = <0x4c>;
			};

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
				/* IRQ_RTC_B -> IRQ0_B(CPLD) -> IRQ00(CPU), active low */
				interrupts-extended = <&extirq 0 IRQ_TYPE_LEVEL_LOW>;
			};
		};
	};
};

&ifc {
	ranges = <0 0 0x5 0x30000000 0x00010000
		  2 0 0x5 0x20000000 0x00010000>;
	status = "okay";

	nand@0,0 {
		compatible = "fsl,ifc-nand";
		reg = <0x0 0x0 0x10000>;
	};

	fpga: board-control@2,0 {
		compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
		reg = <0x2 0x0 0x0000100>;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&esdhc {
	mmc-hs200-1_8v;
	status = "okay";
};

&pcs_mdio2 {
	status = "okay";
};

&pcs_mdio3 {
	status = "okay";
};

&pcs_mdio7 {
	status = "okay";
};

&qspi {
	status = "okay";

	s25fs512s0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
		reg = <0>;
	};

	s25fs512s1: flash@1 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
		reg = <1>;
	};
};

&sata {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	dr_mode = "otg";
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Travese Ten64 (LS1088) board
 * Based on fsl-ls1088a-rdb.dts
 * Copyright 2017-2020 NXP
 * Copyright 2019-2021 Traverse Technologies
 *
 * Author: Mathew McBride <matt@traverse.com.au>
 */

/dts-v1/;

#include "fsl-ls1088a.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "Traverse Ten64";
	compatible = "traverse,ten64", "fsl,ls1088a";

	aliases {
		serial0 = &duart0;
		serial1 = &duart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	buttons {
		compatible = "gpio-keys";

		/* Fired by system controller when
		 * external power off (e.g ATX Power Button)
		 * asserted
		 */
		button-powerdn {
			label = "External Power Down";
			gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_POWER>;
		};

		/* Rear Panel 'ADMIN' button (GPIO_H) */
		button-admin {
			label = "ADMIN button";
			gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_WPS_BUTTON>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led-0 {
			label = "ten64:green:sfp1:down";
			gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
		};

		led-1 {
			label = "ten64:green:sfp2:up";
			gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
		};

		led-2 {
			label = "ten64:admin";
			gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
		};
	};

	sfp_xg0: dpmac2-sfp {
		compatible = "sff,sfp";
		i2c-bus = <&sfplower_i2c>;
		tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
		los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
		maximum-power-milliwatt = <2000>;
	};

	sfp_xg1: dpmac1-sfp {
		compatible = "sff,sfp";
		i2c-bus = <&sfpupper_i2c>;
		tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
		los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
		maximum-power-milliwatt = <2000>;
	};
};

/* XG1 - Upper SFP */
&dpmac1 {
	sfp = <&sfp_xg1>;
	pcs-handle = <&pcs1>;
	phy-connection-type = "10gbase-r";
	managed = "in-band-status";
};

/* XG0 - Lower SFP */
&dpmac2 {
	sfp = <&sfp_xg0>;
	pcs-handle = <&pcs2>;
	phy-connection-type = "10gbase-r";
	managed = "in-band-status";
};

/* DPMAC3..6 is GE4 to GE8 */
&dpmac3 {
	phy-handle = <&mdio1_phy5>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs3_0>;
};

&dpmac4 {
	phy-handle = <&mdio1_phy6>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs3_1>;
};

&dpmac5 {
	phy-handle = <&mdio1_phy7>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs3_2>;
};

&dpmac6 {
	phy-handle = <&mdio1_phy8>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs3_3>;
};

/* DPMAC7..10 is GE0 to GE3 */
&dpmac7 {
	phy-handle = <&mdio1_phy1>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs7_0>;
};

&dpmac8 {
	phy-handle = <&mdio1_phy2>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs7_1>;
};

&dpmac9 {
	phy-handle = <&mdio1_phy3>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs7_2>;
};

&dpmac10 {
	phy-handle = <&mdio1_phy4>;
	phy-connection-type = "qsgmii";
	managed = "in-band-status";
	pcs-handle = <&pcs7_3>;
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&emdio1 {
	status = "okay";

	mdio1_phy5: ethernet-phy@c {
		reg = <0xc>;
	};

	mdio1_phy6: ethernet-phy@d {
		reg = <0xd>;
	};

	mdio1_phy7: ethernet-phy@e {
		reg = <0xe>;
	};

	mdio1_phy8: ethernet-phy@f {
		reg = <0xf>;
	};

	mdio1_phy1: ethernet-phy@1c {
		reg = <0x1c>;
	};

	mdio1_phy2: ethernet-phy@1d {
		reg = <0x1d>;
	};

	mdio1_phy3: ethernet-phy@1e {
		reg = <0x1e>;
	};

	mdio1_phy4: ethernet-phy@1f {
		reg = <0x1f>;
	};
};

&esdhc {
	status = "okay";
};

&i2c0 {
	status = "okay";

	sfpgpio: gpio@76 {
		compatible = "ti,tca9539";
		reg = <0x76>;
		#gpio-cells = <2>;
		gpio-controller;

		admin_led_lower {
			gpio-hog;
			gpios = <13 GPIO_ACTIVE_HIGH>;
			output-low;
		};
	};

	at97sc: tpm@29 {
		compatible = "atmel,at97sc3204t";
		reg = <0x29>;
	};
};

&i2c2 {
	status = "okay";

	rx8035: rtc@32 {
		compatible = "epson,rx8035";
		reg = <0x32>;
	};
};

&i2c3 {
	status = "okay";

	i2c-switch@70 {
		compatible = "nxp,pca9540";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		sfpupper_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		sfplower_i2c: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
	};
};

&pcs_mdio1 {
	status = "okay";
};

&pcs_mdio2 {
	status = "okay";
};

&pcs_mdio3 {
	status = "okay";
};

&pcs_mdio7 {
	status = "okay";
};

&qspi {
	status = "okay";

	en25s64: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		spi-max-frequency = <20000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "bl2";
				reg = <0 0x100000>;
			};

			partition@100000 {
				label = "bl3";
				reg = <0x100000 0x200000>;
			};

			partition@300000 {
				label = "mcfirmware";
				reg = <0x300000 0x200000>;
			};

			partition@500000 {
				label = "ubootenv";
				reg = <0x500000 0x80000>;
			};

			partition@580000 {
				label = "dpl";
				reg = <0x580000 0x40000>;
			};

			partition@5C0000 {
				label = "dpc";
				reg = <0x5C0000 0x40000>;
			};

			partition@600000 {
				label = "devicetree";
				reg = <0x600000 0x40000>;
			};
		};
	};

	nand: flash@1 {
		compatible = "spi-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <1>;
		spi-max-frequency = <20000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			/* reserved for future boot direct from NAND flash
			 * (this would use the same layout as the 8MiB NOR flash)
			 */
			partition@0 {
				label = "nand-boot-reserved";
				reg = <0 0x800000>;
			};

			/* recovery / install environment */
			partition@800000 {
				label = "recovery";
				reg = <0x800000 0x2000000>;
			};

			/* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
			partition@2800000 {
				label = "ubia";
				reg = <0x2800000 0x6C00000>;
			};

			/* ubib (second OpenWrt) */
			partition@9400000 {
				label = "ubib";
				reg = <0x9400000 0x6C00000>;
			};
		};
	};
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};