code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/faraday,ftpci100.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Faraday Technology FTPCI100 PCI Host Bridge

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
    This PCI bridge is found inside that Cortina Systems Gemini SoC platform and
    is a generic IP block from Faraday Technology. It exists in two variants:
    plain and dual PCI. The plain version embeds a cascading interrupt controller
    into the host bridge. The dual version routes the interrupts to the host
    chips interrupt controller.
    The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
    Technology) and product ID 0x4321.
    I/O space considerations:
    The plain variant has 128MiB of non-prefetchable memory space, whereas the
    "dual" variant has 64MiB. Take this into account when describing the ranges.

    Interrupt map considerations:

    The "dual" variant will get INT A, B, C, D from the system interrupt controller
    and should point to respective interrupt in that controller in its interrupt-map.

    The code which is the only documentation of how the Faraday PCI (the non-dual
    variant) interrupts assigns the default interrupt mapping/swizzling has
    typically been like this, doing the swizzling on the interrupt controller side
    rather than in the interconnect:

    interrupt-map-mask = <0xf800 0 0 7>;
    interrupt-map =
        <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
        <0x4800 0 0 2 &pci_intc 1>,
        <0x4800 0 0 3 &pci_intc 2>,
        <0x4800 0 0 4 &pci_intc 3>,
        <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
        <0x5000 0 0 2 &pci_intc 2>,
        <0x5000 0 0 3 &pci_intc 3>,
        <0x5000 0 0 4 &pci_intc 0>,
        <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
        <0x5800 0 0 2 &pci_intc 3>,
        <0x5800 0 0 3 &pci_intc 0>,
        <0x5800 0 0 4 &pci_intc 1>,
        <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
        <0x6000 0 0 2 &pci_intc 0>,
        <0x6000 0 0 3 &pci_intc 1>,
        <0x6000 0 0 4 &pci_intc 2>;

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - const: cortina,gemini-pci
          - const: faraday,ftpci100
      - items:
          - const: cortina,gemini-pci-dual
          - const: faraday,ftpci100-dual
      - const: faraday,ftpci100
      - const: faraday,ftpci100-dual

  reg:
    maxItems: 1

  "#address-cells":
    const: 3

  "#interrupt-cells":
    const: 1

  ranges:
    minItems: 2

  dma-ranges:
    minItems: 3
    description: |
      three ranges for the inbound memory region. The ranges must
      be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB,
      128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
      pre-fetchable.

  clocks:
    items:
      - description: peripheral clock (PCLK)
      - description: PCI clock (PCICLK).
    description: |
      If these are not present, they are assumed to be
      hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.

  clock-names:
    items:
      - const: PCLK
      - const: PCICLK

  interrupt-controller:
    type: object

required:
  - reg
  - compatible
  - "#interrupt-cells"
  - interrupt-map-mask
  - interrupt-map
  - dma-ranges

if:
  properties:
    compatible:
      contains:
        const: faraday,ftpci100
then:
  required:
    - interrupt-controller

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    pci@50000000 {
      compatible = "cortina,gemini-pci", "faraday,ftpci100";
      reg = <0x50000000 0x100>;
      device_type = "pci";
      #address-cells = <3>;
      #size-cells = <2>;
      #interrupt-cells = <1>;

      bus-range = <0x00 0xff>;
      ranges = /* 1MiB I/O space 0x50000000-0x500fffff */
        <0x01000000 0 0          0x50000000 0 0x00100000>,
        /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
        <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;

      /* DMA ranges */
      dma-ranges =
        /* 128MiB at 0x00000000-0x07ffffff */
        <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
        /* 64MiB at 0x00000000-0x03ffffff */
        <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
        /* 64MiB at 0x00000000-0x03ffffff */
        <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;

      interrupt-map-mask = <0xf800 0 0 7>;
      interrupt-map =
        <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
        <0x4800 0 0 2 &pci_intc 1>,
        <0x4800 0 0 3 &pci_intc 2>,
        <0x4800 0 0 4 &pci_intc 3>,
        <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
        <0x5000 0 0 2 &pci_intc 2>,
        <0x5000 0 0 3 &pci_intc 3>,
        <0x5000 0 0 4 &pci_intc 0>,
        <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
        <0x5800 0 0 2 &pci_intc 3>,
        <0x5800 0 0 3 &pci_intc 0>,
        <0x5800 0 0 4 &pci_intc 1>,
        <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
        <0x6000 0 0 2 &pci_intc 0>,
        <0x6000 0 0 3 &pci_intc 0>,
        <0x6000 0 0 4 &pci_intc 0>;
      pci_intc: interrupt-controller {
        interrupt-parent = <&intcon>;
        interrupt-controller;
        interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <0>;
        #interrupt-cells = <1>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX6 PCIe host controller

maintainers:
  - Lucas Stach <l.stach@pengutronix.de>
  - Richard Zhu <hongxing.zhu@nxp.com>

description: |+
  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
  and thus inherits all the common properties defined in snps,dw-pcie.yaml.

properties:
  compatible:
    enum:
      - fsl,imx6q-pcie
      - fsl,imx6sx-pcie
      - fsl,imx6qp-pcie
      - fsl,imx7d-pcie
      - fsl,imx8mq-pcie
      - fsl,imx8mm-pcie
      - fsl,imx8mp-pcie

  reg:
    items:
      - description: Data Bus Interface (DBI) registers.
      - description: PCIe configuration space region.

  reg-names:
    items:
      - const: dbi
      - const: config

  interrupts:
    items:
      - description: builtin MSI controller.

  interrupt-names:
    items:
      - const: msi

  clocks:
    minItems: 3
    items:
      - description: PCIe bridge clock.
      - description: PCIe bus clock.
      - description: PCIe PHY clock.
      - description: Additional required clock entry for imx6sx-pcie,
          imx8mq-pcie.

  clock-names:
    minItems: 3
    items:
      - const: pcie
      - const: pcie_bus
      - const: pcie_phy
      - enum: [ pcie_inbound_axi, pcie_aux ]

  num-lanes:
    const: 1

  fsl,imx7d-pcie-phy:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: A phandle to an fsl,imx7d-pcie-phy node. Additional
      required properties for imx7d-pcie and imx8mq-pcie.

  power-domains:
    items:
      - description: The phandle pointing to the DISPLAY domain for
          imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
          imx8mq-pcie.
      - description: The phandle pointing to the PCIE_PHY power domains
          for imx6sx-pcie.

  power-domain-names:
    items:
      - const: pcie
      - const: pcie_phy

  resets:
    maxItems: 3
    description: Phandles to PCIe-related reset lines exposed by SRC
      IP block. Additional required by imx7d-pcie and imx8mq-pcie.

  reset-names:
    items:
      - const: pciephy
      - const: apps
      - const: turnoff

  fsl,tx-deemph-gen1:
    description: Gen1 De-emphasis value (optional required).
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

  fsl,tx-deemph-gen2-3p5db:
    description: Gen2 (3.5db) De-emphasis value (optional required).
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

  fsl,tx-deemph-gen2-6db:
    description: Gen2 (6db) De-emphasis value (optional required).
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 20

  fsl,tx-swing-full:
    description: Gen2 TX SWING FULL value (optional required).
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 127

  fsl,tx-swing-low:
    description: TX launch amplitude swing_low value (optional required).
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 127

  fsl,max-link-speed:
    description: Specify PCI Gen for link capability (optional required).
      Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
      requirements and thus for gen2 capability a gen2 compliant clock
      generator should be used and configured.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2, 3, 4]
    default: 1

  phys:
    maxItems: 1

  phy-names:
    const: pcie-phy

  reset-gpio:
    description: Should specify the GPIO for controlling the PCI bus device
      reset signal. It's not polarity aware and defaults to active-low reset
      sequence (L=reset state, H=operation state) (optional required).

  reset-gpio-active-high:
    description: If present then the reset sequence using the GPIO
      specified in the "reset-gpio" property is reversed (H=reset state,
      L=operation state) (optional required).
    type: boolean

  vpcie-supply:
    description: Should specify the regulator in charge of PCIe port power.
      The regulator will be enabled when initializing the PCIe host and
      disabled either as part of the init process or when shutting down
      the host (optional required).

  vph-supply:
    description: Should specify the regulator in charge of VPH one of
      the three PCIe PHY powers. This regulator can be supplied by both
      1.8v and 3.3v voltage supplies (optional required).

required:
  - compatible
  - reg
  - reg-names
  - "#address-cells"
  - "#size-cells"
  - device_type
  - bus-range
  - ranges
  - num-lanes
  - interrupts
  - interrupt-names
  - "#interrupt-cells"
  - interrupt-map-mask
  - interrupt-map
  - clocks
  - clock-names

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx6sx-pcie
    then:
      properties:
        clock-names:
          items:
            - {}
            - {}
            - {}
            - const: pcie_inbound_axi
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8mq-pcie
    then:
      properties:
        clock-names:
          items:
            - {}
            - {}
            - {}
            - const: pcie_aux
  - if:
      properties:
        compatible:
          not:
            contains:
              enum:
                - fsl,imx6sx-pcie
                - fsl,imx8mq-pcie
    then:
      properties:
        clock-names:
          maxItems: 3

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx6qdl-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pcie: pcie@1ffc000 {
        compatible = "fsl,imx6q-pcie";
        reg = <0x01ffc000 0x04000>,
              <0x01f00000 0x80000>;
        reg-names = "dbi", "config";
        #address-cells = <3>;
        #size-cells = <2>;
        device_type = "pci";
        bus-range = <0x00 0xff>;
        ranges = <0x81000000 0 0          0x01f80000 0 0x00010000>,
                 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
        num-lanes = <1>;
        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "msi";
        #interrupt-cells = <1>;
        interrupt-map-mask = <0 0 0 0x7>;
        interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
                        <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
                <&clks IMX6QDL_CLK_LVDS1_GATE>,
                <&clks IMX6QDL_CLK_PCIE_REF_125M>;
        clock-names = "pcie", "pcie_bus", "pcie_phy";
    };
...

repo_name: angery/linux


code:
* Bus Enumeration by Freescale PCI-X Agent

Typically any Freescale PCI-X bridge hardware strapped into Agent mode
is prevented from enumerating the bus. The PrPMC form-factor requires
all mezzanines to be PCI-X Agents, but one per system may still
enumerate the bus.

The property defined below will allow a PCI-X bridge to be used for bus
enumeration despite being strapped into Agent mode.

Required properties:
- fsl,pci-agent-force-enum : There is no value associated with this
  property. The property itself is treated as a boolean.

Example:

	/* PCI-X bridge known to be PrPMC Monarch */
	pci0: pci@ef008000 {
		fsl,pci-agent-force-enum;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";
		...
		...
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: HiSilicon Kirin SoCs PCIe host DT description

maintainers:
  - Xiaowei Song <songxiaowei@hisilicon.com>
  - Binghui Wang <wangbinghui@hisilicon.com>

description: |
  Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
  It shares common functions with the PCIe DesignWare core driver and
  inherits common properties defined in
  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    contains:
      enum:
        - hisilicon,kirin960-pcie
        - hisilicon,kirin970-pcie

  reg:
    description: |
      Should contain dbi, apb, config registers location and length.
      For hisilicon,kirin960-pcie, it should also contain phy.
    minItems: 3
    maxItems: 4

  reg-names:
    minItems: 3
    maxItems: 4

  clocks: true

  clock-names:
    items:
      - const: pcie_phy_ref
      - const: pcie_aux
      - const: pcie_apb_phy
      - const: pcie_apb_sys
      - const: pcie_aclk

  phys:
    maxItems: 1

  hisilicon,clken-gpios:
    description: |
      Clock input enablement GPIOs from PCI devices like Ethernet, M.2 and
      mini-PCIe slots.

required:
  - compatible
  - reg
  - reg-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/hi3660-clock.h>
    #include <dt-bindings/clock/hi3670-clock.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      pcie@f4000000 {
        compatible = "hisilicon,kirin960-pcie";
        reg = <0x0 0xf4000000 0x0 0x1000>,
              <0x0 0xff3fe000 0x0 0x1000>,
              <0x0 0xf3f20000 0x0 0x40000>,
              <0x0 0xf5000000 0x0 0x2000>;
        reg-names = "dbi", "apb", "phy", "config";
        bus-range = <0x0  0xff>;
        #address-cells = <3>;
        #size-cells = <2>;
        device_type = "pci";
        ranges = <0x02000000 0x0 0x00000000
                  0x0 0xf6000000
                  0x0 0x02000000>;
        num-lanes = <1>;
        #interrupt-cells = <1>;
        interrupts = <0 283 4>;
        interrupt-names = "msi";
        interrupt-map-mask = <0xf800 0 0 7>;
        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
                 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
                 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
                 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
                 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
        clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
                      "pcie_apb_sys", "pcie_aclk";
      };

      pcie@f5000000 {
        compatible = "hisilicon,kirin970-pcie";
        reg = <0x0 0xf4000000 0x0 0x1000000>,
              <0x0 0xfc180000 0x0 0x1000>,
              <0x0 0xf5000000 0x0 0x2000>;
        reg-names = "dbi", "apb", "config";
        bus-range = <0x0  0xff>;
        #address-cells = <3>;
        #size-cells = <2>;
        device_type = "pci";
        phys = <&pcie_phy>;
        ranges = <0x02000000 0x0 0x00000000
                  0x0 0xf6000000
                  0x0 0x02000000>;
        num-lanes = <1>;
        #interrupt-cells = <1>;
        interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "msi";
        interrupt-map-mask = <0 0 0 7>;
        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
        reset-gpios = <&gpio7 0 0>;
        hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>;
        pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
          reg = <0 0 0 0 0>;
          compatible = "pciclass,0604";
          device_type = "pci";
          #address-cells = <3>;
          #size-cells = <2>;
          ranges;

          pcie@0,0 { // Lane 0: upstream
            reg = <0 0 0 0 0>;
            compatible = "pciclass,0604";
            device_type = "pci";
            #address-cells = <3>;
            #size-cells = <2>;
            ranges;

            pcie@1,0 { // Lane 4: M.2
              reg = <0x0800 0 0 0 0>;
              compatible = "pciclass,0604";
              device_type = "pci";
              reset-gpios = <&gpio3 1 0>;
              #address-cells = <3>;
              #size-cells = <2>;
              ranges;
            };

            pcie@5,0 { // Lane 5: Mini PCIe
              reg = <0x2800 0 0 0 0>;
              compatible = "pciclass,0604";
              device_type = "pci";
              reset-gpios = <&gpio27 4 0 >;
              #address-cells = <3>;
              #size-cells = <2>;
              ranges;
            };

            pcie@7,0 { // Lane 6: Ethernet
              reg = <0x03800 0 0 0 0>;
              compatible = "pciclass,0604";
              device_type = "pci";
              reset-gpios = <&gpio25 2 0 >;
              #address-cells = <3>;
              #size-cells = <2>;
              ranges;
            };
          };
        };
      };
    };


code:
HiSilicon STB PCIe host bridge DT description

The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
It shares common functions with the DesignWare PCIe core driver and inherits
common properties defined in
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.

Additional properties are described here:

Required properties
- compatible: Should be one of the following strings:
		"hisilicon,hi3798cv200-pcie"
- reg: Should contain sysctl, rc_dbi, config registers location and length.
- reg-names: Must include the following entries:
  "control": control registers of PCIe controller;
  "rc-dbi": configuration space of PCIe controller;
  "config": configuration transaction space of PCIe controller.
- bus-range: PCI bus numbers covered.
- interrupts: MSI interrupt.
- interrupt-names: Must include "msi" entries.
- clocks: List of phandle and clock specifier pairs as listed in clock-names
  property.
- clock-name: Must include the following entries:
  "aux": auxiliary gate clock;
  "pipe": pipe gate clock;
  "sys": sys gate clock;
  "bus": bus gate clock.
- resets: List of phandle and reset specifier pairs as listed in reset-names
  property.
- reset-names: Must include the following entries:
  "soft": soft reset;
  "sys": sys reset;
  "bus": bus reset.

Optional properties:
- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
- vpcie-supply: The regulator in charge of PCIe port power.
- phys: List of phandle and phy mode specifier, should be 0.
- phy-names: Must be "phy".

Example:
	pcie@f9860000 {
		compatible = "hisilicon,hi3798cv200-pcie";
		reg = <0xf9860000 0x1000>,
		      <0xf0000000 0x2000>,
		      <0xf2000000 0x01000000>;
		reg-names = "control", "rc-dbi", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		bus-range = <0 15>;
		num-lanes = <1>;
		ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
			0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "msi";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&crg PCIE_AUX_CLK>,
			 <&crg PCIE_PIPE_CLK>,
			 <&crg PCIE_SYS_CLK>,
			 <&crg PCIE_BUS_CLK>;
		clock-names = "aux", "pipe", "sys", "bus";
		resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
		reset-names = "soft", "sys", "bus";
		phys = <&combphy1 PHY_TYPE_PCIE>;
		phy-names = "phy";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic PCI host controller

maintainers:
  - Will Deacon <will@kernel.org>

description: |
  Firmware-initialised PCI host controllers and PCI emulations, such as the
  virtio-pci implementations found in kvmtool and other para-virtualised
  systems, do not require driver support for complexities such as regulator
  and clock management. In fact, the controller may not even require the
  configuration of a control interface by the operating system, instead
  presenting a set of fixed windows describing a subset of IO, Memory and
  Configuration Spaces.

  Configuration Space is assumed to be memory-mapped (as opposed to being
  accessed via an ioport) and laid out with a direct correspondence to the
  geography of a PCI bus address by concatenating the various components to
  form an offset.

  For CAM, this 24-bit offset is:

          cfg_offset(bus, device, function, register) =
                     bus << 16 | device << 11 | function << 8 | register

  While ECAM extends this by 4 bits to accommodate 4k of function space:

          cfg_offset(bus, device, function, register) =
                     bus << 20 | device << 15 | function << 12 | register

properties:
  compatible:
    description: Depends on the layout of configuration space (CAM vs ECAM
      respectively). May also have more specific compatibles.
    oneOf:
      - description:
          PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP
        items:
          - const: arm,juno-r1-pcie
          - const: plda,xpressrich3-axi
          - const: pci-host-ecam-generic
      - description: |
          ThunderX PCI host controller for pass-1.x silicon

          Firmware-initialized PCI host controller to on-chip devices found on
          some Cavium ThunderX processors.  These devices have ECAM-based config
          access, but the BARs are all at fixed addresses.  We handle the fixed
          addresses by synthesizing Enhanced Allocation (EA) capabilities for
          these devices.
        const: cavium,pci-host-thunder-ecam
      - description:
          Cavium ThunderX PEM firmware-initialized PCIe host controller
        const: cavium,pci-host-thunder-pem
      - description:
          HiSilicon Hip06/Hip07 PCIe host bridge in almost-ECAM mode. Some
          firmware places the host controller in a mode where it is ECAM
          compliant for all devices other than the root complex.
        enum:
          - hisilicon,hip06-pcie-ecam
          - hisilicon,hip07-pcie-ecam
      - description: |
          In some cases, firmware may already have configured the Synopsys
          DesignWare PCIe controller in RC mode with static ATU window mappings
          that cover all config, MMIO and I/O spaces in a [mostly] ECAM
          compatible fashion. In this case, there is no need for the OS to
          perform any low level setup of clocks, PHYs or device registers, nor
          is there any reason for the driver to reconfigure ATU windows for
          config and/or IO space accesses at runtime.

          In cases where the IP was synthesized with a minimum ATU window size
          of 64 KB, it cannot be supported by the generic ECAM driver, because
          it requires special config space accessors that filter accesses to
          device #1 and beyond on the first bus.
        items:
          - enum:
              - marvell,armada8k-pcie-ecam
              - socionext,synquacer-pcie-ecam
          - const: snps,dw-pcie-ecam
      - description:
          CAM or ECAM compliant PCI host controllers without any quirks
        enum:
          - pci-host-cam-generic
          - pci-host-ecam-generic

  reg:
    description:
      The Configuration Space base address and size, as accessed from the parent
      bus. The base address corresponds to the first bus in the "bus-range"
      property. If no "bus-range" is specified, this will be bus 0 (the
      default). Some host controllers have a 2nd non-compliant address range,
      so 2 entries are allowed.
    minItems: 1
    maxItems: 2

  ranges:
    description:
      As described in IEEE Std 1275-1994, but must provide at least a
      definition of non-prefetchable memory. One or both of prefetchable Memory
      and IO Space may also be provided.
    minItems: 1
    maxItems: 3

  dma-coherent: true
  iommu-map: true
  iommu-map-mask: true
  msi-parent: true

required:
  - compatible
  - reg
  - ranges

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: arm,juno-r1-pcie
    then:
      required:
        - dma-coherent

  - if:
      properties:
        compatible:
          not:
            contains:
              enum:
                - cavium,pci-host-thunder-pem
                - hisilicon,hip06-pcie-ecam
                - hisilicon,hip07-pcie-ecam
    then:
      properties:
        reg:
          maxItems: 1

unevaluatedProperties: false

examples:
  - |

    bus {
        #address-cells = <2>;
        #size-cells = <2>;
        pcie@40000000 {
            compatible = "pci-host-cam-generic";
            device_type = "pci";
            #address-cells = <3>;
            #size-cells = <2>;
            bus-range = <0x0 0x1>;

            // CPU_PHYSICAL(2)  SIZE(2)
            reg = <0x0 0x40000000  0x0 0x1000000>;

            // BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
            ranges = <0x01000000 0x0 0x01000000  0x0 0x01000000  0x0 0x00010000>,
                     <0x02000000 0x0 0x41000000  0x0 0x41000000  0x0 0x3f000000>;

            #interrupt-cells = <0x1>;

            // PCI_DEVICE(3)  INT#(1)  CONTROLLER(PHANDLE)  CONTROLLER_DATA(3)
            interrupt-map = <   0x0 0x0 0x0  0x1  &gic  0x0 0x4 0x1>,
                            < 0x800 0x0 0x0  0x1  &gic  0x0 0x5 0x1>,
                            <0x1000 0x0 0x0  0x1  &gic  0x0 0x6 0x1>,
                            <0x1800 0x0 0x0  0x1  &gic  0x0 0x7 0x1>;

            // PCI_DEVICE(3)  INT#(1)
            interrupt-map-mask = <0xf800 0x0 0x0  0x7>;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel IXP4xx PCI controller

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: PCI host controller found in the Intel IXP4xx SoC series.

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

properties:
  compatible:
    items:
      - enum:
          - intel,ixp42x-pci
          - intel,ixp43x-pci
    description: The two supported variants are ixp42x and ixp43x,
      though more variants may exist.

  reg:
    items:
      - description: IXP4xx-specific registers

  interrupts:
    items:
      - description: Main PCI interrupt
      - description: PCI DMA interrupt 1
      - description: PCI DMA interrupt 2

  ranges:
    maxItems: 2
    description: Typically one memory range of 64MB and one IO
      space range of 64KB.

  dma-ranges:
    maxItems: 1
    description: The DMA range tells the PCI host which addresses
      the RAM is at. It can map only 64MB so if the RAM is bigger
      than 64MB the DMA access has to be restricted to these
      addresses.

  "#interrupt-cells": true

  interrupt-map: true

  interrupt-map-mask:
    items:
      - const: 0xf800
      - const: 0
      - const: 0
      - const: 7

required:
  - compatible
  - reg
  - dma-ranges
  - "#interrupt-cells"
  - interrupt-map
  - interrupt-map-mask

unevaluatedProperties: false

examples:
  - |
    pci@c0000000 {
      compatible = "intel,ixp43x-pci";
      reg = <0xc0000000 0x1000>;
      #address-cells = <3>;
      #size-cells = <2>;
      device_type = "pci";
      bus-range = <0x00 0xff>;

      ranges =
        <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
        <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
      dma-ranges =
        <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;

      #interrupt-cells = <1>;
      interrupt-map-mask = <0xf800 0 0 7>;
      interrupt-map =
        <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
        <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
        <0x0800 0 0 3 &gpio0 9  3>, /* INT C on slot 1 is irq 9 */
        <0x0800 0 0 4 &gpio0 8  3>, /* INT D on slot 1 is irq 8 */
        <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
        <0x1000 0 0 2 &gpio0 9  3>, /* INT B on slot 2 is irq 9 */
        <0x1000 0 0 3 &gpio0 8  3>, /* INT C on slot 2 is irq 8 */
        <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
        <0x1800 0 0 1 &gpio0 9  3>, /* INT A on slot 3 is irq 9 */
        <0x1800 0 0 2 &gpio0 8  3>, /* INT B on slot 3 is irq 8 */
        <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
        <0x1800 0 0 4 &gpio0 10 3>; /* INT D on slot 3 is irq 10 */
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel Keem Bay PCIe controller Endpoint mode

maintainers:
  - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
  - Srikanth Thokala <srikanth.thokala@intel.com>

properties:
  compatible:
    const: intel,keembay-pcie-ep

  reg:
    maxItems: 5

  reg-names:
    items:
      - const: dbi
      - const: dbi2
      - const: atu
      - const: addr_space
      - const: apb

  interrupts:
    maxItems: 4

  interrupt-names:
    items:
      - const: pcie
      - const: pcie_ev
      - const: pcie_err
      - const: pcie_mem_access

  num-lanes:
    description: Number of lanes to use.
    enum: [ 1, 2 ]

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    pcie-ep@37000000 {
          compatible = "intel,keembay-pcie-ep";
          reg = <0x37000000 0x00001000>,
                <0x37100000 0x00001000>,
                <0x37300000 0x00001000>,
                <0x36000000 0x01000000>,
                <0x37800000 0x00000200>;
          reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
          interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
                       <GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
                       <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
                       <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
          interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
          num-lanes = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel Keem Bay PCIe controller Root Complex mode

maintainers:
  - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
  - Srikanth Thokala <srikanth.thokala@intel.com>

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

properties:
  compatible:
    const: intel,keembay-pcie

  ranges:
    maxItems: 1

  reset-gpios:
    maxItems: 1

  reg:
    maxItems: 4

  reg-names:
    items:
      - const: dbi
      - const: atu
      - const: config
      - const: apb

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: master
      - const: aux

  interrupts:
    maxItems: 3

  interrupt-names:
    items:
      - const: pcie
      - const: pcie_ev
      - const: pcie_err

  num-lanes:
    description: Number of lanes to use.
    enum: [ 1, 2 ]

required:
  - compatible
  - reg
  - reg-names
  - ranges
  - clocks
  - clock-names
  - interrupts
  - interrupt-names
  - reset-gpios

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>
    #define KEEM_BAY_A53_PCIE
    #define KEEM_BAY_A53_AUX_PCIE
    pcie@37000000 {
          compatible = "intel,keembay-pcie";
          reg = <0x37000000 0x00001000>,
                <0x37300000 0x00001000>,
                <0x36e00000 0x00200000>,
                <0x37800000 0x00000200>;
          reg-names = "dbi", "atu", "config", "apb";
          #address-cells = <3>;
          #size-cells = <2>;
          device_type = "pci";
          ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
          interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
                       <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
                       <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
          interrupt-names = "pcie", "pcie_ev", "pcie_err";
          clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
                   <&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
          clock-names = "master", "aux";
          reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
          num-lanes = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PCIe RC controller on Intel Gateway SoCs

maintainers:
  - Rahul Tanwar <rtanwar@maxlinear.com>

select:
  properties:
    compatible:
      contains:
        const: intel,lgm-pcie
  required:
    - compatible

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    items:
      - const: intel,lgm-pcie
      - const: snps,dw-pcie

  reg:
    items:
      - description: Controller control and status registers.
      - description: PCIe configuration registers.
      - description: Controller application registers.

  reg-names:
    items:
      - const: dbi
      - const: config
      - const: app

  ranges:
    maxItems: 1

  resets:
    maxItems: 1

  clocks:
    maxItems: 1

  phys:
    maxItems: 1

  phy-names:
    const: pcie

  reset-gpios:
    maxItems: 1

  num-lanes:
    maximum: 2

  max-link-speed:
    enum: [1, 2, 3, 4]
    default: 1

  reset-assert-ms:
    description: |
      Delay after asserting reset to the PCIe device.
    maximum: 500
    default: 100

required:
  - compatible
  - reg
  - reg-names
  - ranges
  - resets
  - clocks
  - phys
  - phy-names
  - reset-gpios
  - '#interrupt-cells'
  - interrupt-map
  - interrupt-map-mask

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    pcie10: pcie@d0e00000 {
      compatible = "intel,lgm-pcie", "snps,dw-pcie";
      device_type = "pci";
      #address-cells = <3>;
      #size-cells = <2>;
      reg = <0xd0e00000 0x1000>,
            <0xd2000000 0x800000>,
            <0xd0a41000 0x1000>;
      reg-names = "dbi", "config", "app";
      linux,pci-domain = <0>;
      max-link-speed = <4>;
      bus-range = <0x00 0x08>;
      #interrupt-cells = <1>;
      interrupt-map-mask = <0 0 0 0x7>;
      interrupt-map = <0 0 0 1 &ioapic1 27 1>,
                      <0 0 0 2 &ioapic1 28 1>,
                      <0 0 0 3 &ioapic1 29 1>,
                      <0 0 0 4 &ioapic1 30 1>;
      ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
      resets = <&rcu0 0x50 0>;
      clocks = <&cgu0 120>;
      phys = <&cb0phy0>;
      phy-names = "pcie";
      reset-assert-ms = <500>;
      reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
      num-lanes = <2>;
    };


code:
Freescale Layerscape PCIe controller

This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in snps,dw-pcie.yaml.

This controller derives its clocks from the Reset Configuration Word (RCW)
which is used to describe the PLL settings at the time of chip-reset.

Also as per the available Reference Manuals, there is no specific 'version'
register available in the Freescale PCIe controller register set,
which can allow determining the underlying DesignWare PCIe controller version
information.

Required properties:
- compatible: should contain the platform identifier such as:
  RC mode:
        "fsl,ls1021a-pcie"
        "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
        "fsl,ls2088a-pcie"
        "fsl,ls1088a-pcie"
        "fsl,ls1046a-pcie"
        "fsl,ls1043a-pcie"
        "fsl,ls1012a-pcie"
        "fsl,ls1028a-pcie"
  EP mode:
	"fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"
	"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
	"fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
	"fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
	"fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"
- reg: base addresses and lengths of the PCIe controller register blocks.
- interrupts: A list of interrupt outputs of the controller. Must contain an
  entry for each entry in the interrupt-names property.
- interrupt-names: It could include the following entries:
  "aer": Used for interrupt line which reports AER events when
	 non MSI/MSI-X/INTx mode is used
  "pme": Used for interrupt line which reports PME events when
	 non MSI/MSI-X/INTx mode is used
  "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a)
	  which has a single interrupt line for miscellaneous controller
	  events(could include AER and PME events).
- fsl,pcie-scfg: Must include two entries.
  The first entry must be a link to the SCFG device node
  The second entry is the physical PCIe controller index starting from '0'.
  This is used to get SCFG PEXN registers
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
  of the data transferred from/to the IP block. This can avoid the software
  cache flush/invalid actions, and improve the performance significantly.

Optional properties:
- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
  this property.

Example:

        pcie@3400000 {
                compatible = "fsl,ls1088a-pcie";
                reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
                      <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
                reg-names = "regs", "config";
                interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
                interrupt-names = "aer";
                #address-cells = <3>;
                #size-cells = <2>;
                device_type = "pci";
                dma-coherent;
                num-viewport = <256>;
                bus-range = <0x0 0xff>;
                ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
                          0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
                msi-parent = <&its>;
                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 0 7>;
                interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
                                <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
                                <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
                                <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
                iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
        };


code:
NXP Layerscape PCIe Gen4 controller

This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
the common properties defined in mobiveil-pcie.txt.

Required properties:
- compatible: should contain the platform identifier such as:
  "fsl,lx2160a-pcie"
- reg: base addresses and lengths of the PCIe controller register blocks.
  "csr_axi_slave": Bridge config registers
  "config_axi_slave": PCIe controller registers
- interrupts: A list of interrupt outputs of the controller. Must contain an
  entry for each entry in the interrupt-names property.
- interrupt-names: It could include the following entries:
  "intr": The interrupt that is asserted for controller interrupts
  "aer": Asserted for aer interrupt when chip support the aer interrupt with
	 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
  "pme": Asserted for pme interrupt when chip support the pme interrupt with
	 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
- dma-coherent: Indicates that the hardware IP block can ensure the coherency
  of the data transferred from/to the IP block. This can avoid the software
  cache flush/invalid actions, and improve the performance significantly.
- msi-parent : See the generic MSI binding described in
  Documentation/devicetree/bindings/interrupt-controller/msi.txt.

Example:

	pcie@3400000 {
		compatible = "fsl,lx2160a-pcie";
		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
		       0x80 0x00000000 0x0 0x00001000>; /* configuration space */
		reg-names = "csr_axi_slave", "config_axi_slave";
		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
		interrupt-names = "aer", "pme", "intr";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		apio-wins = <8>;
		ppio-wins = <8>;
		dma-coherent;
		bus-range = <0x0 0xff>;
		msi-parent = <&its>;
		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/loongson.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Loongson PCI Host Controller

maintainers:
  - Jiaxun Yang <jiaxun.yang@flygoat.com>

description: |+
  PCI host controller found on Loongson PCHs and SoCs.

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

properties:
  compatible:
    enum:
      - loongson,ls2k-pci
      - loongson,ls7a-pci
      - loongson,rs780e-pci

  reg:
    minItems: 1
    items:
      - description: CFG0 standard config space register
      - description: CFG1 extended config space register

  ranges:
    minItems: 1
    maxItems: 3

required:
  - compatible
  - reg
  - ranges

unevaluatedProperties: false

examples:
  - |

    bus {
        #address-cells = <2>;
        #size-cells = <2>;
        pcie@1a000000 {
            compatible = "loongson,rs780e-pci";
            device_type = "pci";
            #address-cells = <3>;
            #size-cells = <2>;

            // CPU_PHYSICAL(2)  SIZE(2)
            reg = <0x0 0x1a000000  0x0 0x2000000>;

            // BUS_ADDRESS(3)  CPU_PHYSICAL(2)  SIZE(2)
            ranges = <0x01000000 0x0 0x00004000  0x0 0x00004000  0x0 0x00004000>,
                     <0x02000000 0x0 0x40000000  0x0 0x40000000  0x0 0x40000000>;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek MT7621 PCIe controller

maintainers:
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

description: |+
  MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
  with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

properties:
  compatible:
    const: mediatek,mt7621-pci

  reg:
    items:
      - description: host-pci bridge registers
      - description: pcie port 0 RC control registers
      - description: pcie port 1 RC control registers
      - description: pcie port 2 RC control registers

  ranges:
    maxItems: 2

patternProperties:
  '^pcie@[0-2],0$':
    type: object
    $ref: /schemas/pci/pci-bus.yaml#

    properties:
      resets:
        maxItems: 1

      clocks:
        maxItems: 1

      phys:
        maxItems: 1

      phy-names:
        pattern: '^pcie-phy[0-2]$'

    required:
      - "#interrupt-cells"
      - interrupt-map-mask
      - interrupt-map
      - resets
      - clocks
      - phys
      - phy-names
      - ranges

    unevaluatedProperties: false

required:
  - compatible
  - reg
  - ranges
  - "#interrupt-cells"
  - interrupt-map-mask
  - interrupt-map
  - reset-gpios

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/mips-gic.h>

    pcie: pcie@1e140000 {
        compatible = "mediatek,mt7621-pci";
        reg = <0x1e140000 0x100>,
              <0x1e142000 0x100>,
              <0x1e143000 0x100>,
              <0x1e144000 0x100>;

        #address-cells = <3>;
        #size-cells = <2>;
        pinctrl-names = "default";
        pinctrl-0 = <&pcie_pins>;
        device_type = "pci";
        ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>,  /* pci memory */
                 <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>;  /* io space */
        #interrupt-cells = <1>;
        interrupt-map-mask = <0xF800 0 0 0>;
        interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
                        <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
                        <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
        reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;

        pcie@0,0 {
            reg = <0x0000 0 0 0 0>;
            #address-cells = <3>;
            #size-cells = <2>;
            device_type = "pci";
            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0>;
            interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
            resets = <&rstctrl 24>;
            clocks = <&clkctrl 24>;
            phys = <&pcie0_phy 1>;
            phy-names = "pcie-phy0";
            ranges;
        };

        pcie@1,0 {
            reg = <0x0800 0 0 0 0>;
            #address-cells = <3>;
            #size-cells = <2>;
            device_type = "pci";
            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0>;
            interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
            resets = <&rstctrl 25>;
            clocks = <&clkctrl 25>;
            phys = <&pcie0_phy 1>;
            phy-names = "pcie-phy1";
            ranges;
        };

        pcie@2,0 {
            reg = <0x1000 0 0 0 0>;
            #address-cells = <3>;
            #size-cells = <2>;
            device_type = "pci";
            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0>;
            interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
            resets = <&rstctrl 26>;
            clocks = <&clkctrl 26>;
            phys = <&pcie2_phy 0>;
            phy-names = "pcie-phy2";
            ranges;
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek PCIECFG controller

maintainers:
  - Chuanjia Liu <chuanjia.liu@mediatek.com>
  - Jianjun Wang <jianjun.wang@mediatek.com>

description: |
  The MediaTek PCIECFG controller controls some feature about
  LTSSM, ASPM and so on.

properties:
  compatible:
    items:
      - enum:
          - mediatek,generic-pciecfg
      - const: syscon

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pciecfg: pciecfg@1a140000 {
        compatible = "mediatek,generic-pciecfg", "syscon";
        reg = <0x1a140000 0x1000>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Gen3 PCIe controller on MediaTek SoCs

maintainers:
  - Jianjun Wang <jianjun.wang@mediatek.com>

description: |+
  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
  and compatible with Gen2, Gen1 speed.

  This PCIe controller supports up to 256 MSI vectors, the MSI hardware
  block diagram is as follows:

                    +-----+
                    | GIC |
                    +-----+
                       ^
                       |
                   port->irq
                       |
               +-+-+-+-+-+-+-+-+
               |0|1|2|3|4|5|6|7| (PCIe intc)
               +-+-+-+-+-+-+-+-+
                ^ ^           ^
                | |    ...    |
        +-------+ +------+    +-----------+
        |                |                |
  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
   ^ ^      ^  ^    ^ ^      ^  ^    ^ ^      ^  ^
   | |      |  |    | |      |  |    | |      |  |  (MSI vectors)
   | |      |  |    | |      |  |    | |      |  |

    (MSI SET0)       (MSI SET1)  ...   (MSI SET7)

  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
  each set has its own address for MSI message, and supports 32 MSI vectors
  to generate interrupt.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt7986-pcie
              - mediatek,mt8188-pcie
              - mediatek,mt8195-pcie
          - const: mediatek,mt8192-pcie
      - const: mediatek,mt8192-pcie

  reg:
    maxItems: 1

  reg-names:
    items:
      - const: pcie-mac

  interrupts:
    maxItems: 1

  ranges:
    minItems: 1
    maxItems: 8

  iommu-map:
    maxItems: 1

  iommu-map-mask:
    const: 0

  resets:
    minItems: 1
    maxItems: 2

  reset-names:
    minItems: 1
    maxItems: 2
    items:
      enum: [ phy, mac ]

  clocks:
    minItems: 4
    maxItems: 6

  clock-names:
    minItems: 4
    maxItems: 6

  assigned-clocks:
    maxItems: 1

  assigned-clock-parents:
    maxItems: 1

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: pcie-phy

  power-domains:
    maxItems: 1

  '#interrupt-cells':
    const: 1

  interrupt-controller:
    description: Interrupt controller node for handling legacy PCI interrupts.
    type: object
    properties:
      '#address-cells':
        const: 0
      '#interrupt-cells':
        const: 1
      interrupt-controller: true

    required:
      - '#address-cells'
      - '#interrupt-cells'
      - interrupt-controller

    additionalProperties: false

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - ranges
  - clocks
  - clock-names
  - '#interrupt-cells'
  - interrupt-controller

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#
  - if:
      properties:
        compatible:
          const: mediatek,mt8192-pcie
    then:
      properties:
        clock-names:
          items:
            - const: pl_250m
            - const: tl_26m
            - const: tl_96m
            - const: tl_32k
            - const: peri_26m
            - const: top_133m
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8188-pcie
              - mediatek,mt8195-pcie
    then:
      properties:
        clock-names:
          items:
            - const: pl_250m
            - const: tl_26m
            - const: tl_96m
            - const: tl_32k
            - const: peri_26m
            - const: peri_mem
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt7986-pcie
    then:
      properties:
        clock-names:
          items:
            - const: pl_250m
            - const: tl_26m
            - const: peri_26m
            - const: top_133m

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie: pcie@11230000 {
            compatible = "mediatek,mt8192-pcie";
            device_type = "pci";
            #address-cells = <3>;
            #size-cells = <2>;
            reg = <0x00 0x11230000 0x00 0x4000>;
            reg-names = "pcie-mac";
            interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
            bus-range = <0x00 0xff>;
            ranges = <0x82000000 0x00 0x12000000 0x00
                      0x12000000 0x00 0x1000000>;
            clocks = <&infracfg 44>,
                     <&infracfg 40>,
                     <&infracfg 43>,
                     <&infracfg 97>,
                     <&infracfg 99>,
                     <&infracfg 111>;
            clock-names = "pl_250m", "tl_26m", "tl_96m",
                          "tl_32k", "peri_26m", "top_133m";
            assigned-clocks = <&topckgen 50>;
            assigned-clock-parents = <&topckgen 91>;

            phys = <&pciephy>;
            phy-names = "pcie-phy";

            resets = <&infracfg_rst 2>,
                     <&infracfg_rst 3>;
            reset-names = "phy", "mac";

            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0x7>;
            interrupt-map = <0 0 0 1 &pcie_intc 0>,
                            <0 0 0 2 &pcie_intc 1>,
                            <0 0 0 3 &pcie_intc 2>,
                            <0 0 0 4 &pcie_intc 3>;
            pcie_intc: interrupt-controller {
                      #address-cells = <0>;
                      #interrupt-cells = <1>;
                      interrupt-controller;
            };
        };
    };


code:
MediaTek Gen2 PCIe controller

Required properties:
- compatible: Should contain one of the following strings:
	"mediatek,mt2701-pcie"
	"mediatek,mt2712-pcie"
	"mediatek,mt7622-pcie"
	"mediatek,mt7623-pcie"
	"mediatek,mt7629-pcie"
	"airoha,en7523-pcie"
- device_type: Must be "pci"
- reg: Base addresses and lengths of the root ports.
- reg-names: Names of the above areas to use during resource lookup.
- #address-cells: Address representation for root ports (must be 3)
- #size-cells: Size representation for root ports (must be 2)
- clocks: Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
- clock-names:
  Mandatory entries:
   - sys_ckN :transaction layer and data link layer clock
  Required entries for MT2701/MT7623:
   - free_ck :for reference clock of PCIe subsys
  Required entries for MT2712/MT7622:
   - ahb_ckN :AHB slave interface operating clock for CSR access and RC
	      initiated MMIO access
  Required entries for MT7622:
   - axi_ckN :application layer MMIO channel operating clock
   - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
	      pcie_mac_ck/pcie_pipe_ck is turned off
   - obff_ckN :OBFF functional block operating clock
   - pipe_ckN :LTSSM and PHY/MAC layer operating clock
  where N starting from 0 to one less than the number of root ports.
- phys: List of PHY specifiers (used by generic PHY framework).
- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
  number of PHYs as specified in *phys* property.
- power-domains: A phandle and power domain specifier pair to the power domain
  which is responsible for collapsing and restoring power to the peripheral.
- bus-range: Range of bus numbers associated with this controller.
- ranges: Ranges for the PCI memory and I/O regions.

Required properties for MT7623/MT2701:
- #interrupt-cells: Size representation for interrupts (must be 1)
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
  Please refer to the standard PCI bus binding document for a more detailed
  explanation.
- resets: Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
  number of root ports.

Required properties for MT2712/MT7622/MT7629:
-interrupts: A list of interrupt outputs of the controller, must have one
	     entry for each PCIe port
- interrupt-names: Must include the following entries:
	- "pcie_irq": The interrupt that is asserted when an MSI/INTX is received
- linux,pci-domain: PCI domain ID. Should be unique for each host controller

In addition, the device tree node must have sub-nodes describing each
PCIe port interface, having the following mandatory properties:

Required properties:
- device_type: Must be "pci"
- reg: Only the first four bytes are used to refer to the correct bus number
  and device number.
- #address-cells: Must be 3
- #size-cells: Must be 2
- #interrupt-cells: Must be 1
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
  Please refer to the standard PCI bus binding document for a more detailed
  explanation.
- ranges: Sub-ranges distributed from the PCIe controller node. An empty
  property is sufficient.

Examples for MT7623:

	hifsys: syscon@1a000000 {
		compatible = "mediatek,mt7623-hifsys",
			     "mediatek,mt2701-hifsys",
			     "syscon";
		reg = <0 0x1a000000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pcie: pcie@1a140000 {
		compatible = "mediatek,mt7623-pcie";
		device_type = "pci";
		reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
		      <0 0x1a142000 0 0x1000>, /* Port0 registers */
		      <0 0x1a143000 0 0x1000>, /* Port1 registers */
		      <0 0x1a144000 0 0x1000>; /* Port2 registers */
		reg-names = "subsys", "port0", "port1", "port2";
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xf800 0 0 0>;
		interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
				<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
				<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
			 <&hifsys CLK_HIFSYS_PCIE0>,
			 <&hifsys CLK_HIFSYS_PCIE1>,
			 <&hifsys CLK_HIFSYS_PCIE2>;
		clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
		resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
			 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
			 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
		reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
		phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
		       <&pcie2_phy PHY_TYPE_PCIE>;
		phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
		bus-range = <0x00 0xff>;
		ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000	/* I/O space */
			  0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;	/* memory space */

		pcie@0,0 {
			reg = <0x0000 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
			ranges;
		};

		pcie@1,0 {
			reg = <0x0800 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
			ranges;
		};

		pcie@2,0 {
			reg = <0x1000 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
			ranges;
		};
	};

Examples for MT2712:

	pcie1: pcie@112ff000 {
		compatible = "mediatek,mt2712-pcie";
		device_type = "pci";
		reg = <0 0x112ff000 0 0x1000>;
		reg-names = "port1";
		linux,pci-domain = <1>;
		#address-cells = <3>;
		#size-cells = <2>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "pcie_irq";
		clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
			 <&pericfg CLK_PERI_PCIE1>;
		clock-names = "sys_ck1", "ahb_ck1";
		phys = <&u3port1 PHY_TYPE_PCIE>;
		phy-names = "pcie-phy1";
		bus-range = <0x00 0xff>;
		ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;
		status = "disabled";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
				<0 0 0 2 &pcie_intc1 1>,
				<0 0 0 3 &pcie_intc1 2>,
				<0 0 0 4 &pcie_intc1 3>;
		pcie_intc1: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};
	};

	pcie0: pcie@11700000 {
		compatible = "mediatek,mt2712-pcie";
		device_type = "pci";
		reg = <0 0x11700000 0 0x1000>;
		reg-names = "port0";
		linux,pci-domain = <0>;
		#address-cells = <3>;
		#size-cells = <2>;
		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "pcie_irq";
		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
			 <&pericfg CLK_PERI_PCIE0>;
		clock-names = "sys_ck0", "ahb_ck0";
		phys = <&u3port0 PHY_TYPE_PCIE>;
		phy-names = "pcie-phy0";
		bus-range = <0x00 0xff>;
		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
		status = "disabled";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
				<0 0 0 2 &pcie_intc0 1>,
				<0 0 0 3 &pcie_intc0 2>,
				<0 0 0 4 &pcie_intc0 3>;
		pcie_intc0: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};
	};

Examples for MT7622:

	pcie0: pcie@1a143000 {
		compatible = "mediatek,mt7622-pcie";
		device_type = "pci";
		reg = <0 0x1a143000 0 0x1000>;
		reg-names = "port0";
		linux,pci-domain = <0>;
		#address-cells = <3>;
		#size-cells = <2>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "pcie_irq";
		clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
			 <&pciesys CLK_PCIE_P0_AHB_EN>,
			 <&pciesys CLK_PCIE_P0_AUX_EN>,
			 <&pciesys CLK_PCIE_P0_AXI_EN>,
			 <&pciesys CLK_PCIE_P0_OBFF_EN>,
			 <&pciesys CLK_PCIE_P0_PIPE_EN>;
		clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
			      "axi_ck0", "obff_ck0", "pipe_ck0";

		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
		bus-range = <0x00 0xff>;
		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x8000000>;
		status = "disabled";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
				<0 0 0 2 &pcie_intc0 1>,
				<0 0 0 3 &pcie_intc0 2>,
				<0 0 0 4 &pcie_intc0 3>;
		pcie_intc0: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};
	};

	pcie1: pcie@1a145000 {
		compatible = "mediatek,mt7622-pcie";
		device_type = "pci";
		reg = <0 0x1a145000 0 0x1000>;
		reg-names = "port1";
		linux,pci-domain = <1>;
		#address-cells = <3>;
		#size-cells = <2>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "pcie_irq";
		clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
			 /* designer has connect RC1 with p0_ahb clock */
			 <&pciesys CLK_PCIE_P0_AHB_EN>,
			 <&pciesys CLK_PCIE_P1_AUX_EN>,
			 <&pciesys CLK_PCIE_P1_AXI_EN>,
			 <&pciesys CLK_PCIE_P1_OBFF_EN>,
			 <&pciesys CLK_PCIE_P1_PIPE_EN>;
		clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
			      "axi_ck1", "obff_ck1", "pipe_ck1";

		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
		bus-range = <0x00 0xff>;
		ranges = <0x82000000 0 0x28000000  0x0 0x28000000  0 0x8000000>;
		status = "disabled";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
				<0 0 0 2 &pcie_intc1 1>,
				<0 0 0 3 &pcie_intc1 2>,
				<0 0 0 4 &pcie_intc1 3>;
		pcie_intc1: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip PCIe Root Port Bridge Controller

maintainers:
  - Daire McNamara <daire.mcnamara@microchip.com>

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#
  - $ref: /schemas/interrupt-controller/msi-controller.yaml#

properties:
  compatible:
    const: microchip,pcie-host-1.0 # PolarFire

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: cfg
      - const: apb

  clocks:
    description:
      Fabric Interface Controllers, FICs, are the interface between the FPGA
      fabric and the core complex on PolarFire SoC. The FICs require two clocks,
      one from each side of the interface. The "FIC clocks" described by this
      property are on the core complex side & communication through a FIC is not
      possible unless it's corresponding clock is enabled. A clock must be
      enabled for each of the interfaces the root port is connected through.
      This could in theory be all 4 interfaces, one interface or any combination
      in between.
    minItems: 1
    items:
      - description: FIC0's clock
      - description: FIC1's clock
      - description: FIC2's clock
      - description: FIC3's clock

  clock-names:
    description:
      As any FIC connection combination is possible, the names should match the
      order in the clocks property and take the form "ficN" where N is a number
      0-3
    minItems: 1
    maxItems: 4
    items:
      pattern: '^fic[0-3]$'

  interrupts:
    minItems: 1
    items:
      - description: PCIe host controller
      - description: builtin MSI controller

  interrupt-names:
    minItems: 1
    items:
      - const: pcie
      - const: msi

  ranges:
    maxItems: 1

  dma-ranges:
    minItems: 1
    maxItems: 6

  msi-controller:
    description: Identifies the node as an MSI controller.

  msi-parent:
    description: MSI controller the device is capable of using.

  interrupt-controller:
    type: object
    properties:
      '#address-cells':
        const: 0

      '#interrupt-cells':
        const: 1

      interrupt-controller: true

    required:
      - '#address-cells'
      - '#interrupt-cells'
      - interrupt-controller

    additionalProperties: false

required:
  - reg
  - reg-names
  - "#interrupt-cells"
  - interrupts
  - interrupt-map-mask
  - interrupt-map
  - msi-controller

unevaluatedProperties: false

examples:
  - |
    soc {
            #address-cells = <2>;
            #size-cells = <2>;
            pcie0: pcie@2030000000 {
                    compatible = "microchip,pcie-host-1.0";
                    reg = <0x0 0x70000000 0x0 0x08000000>,
                          <0x0 0x43000000 0x0 0x00010000>;
                    reg-names = "cfg", "apb";
                    device_type = "pci";
                    #address-cells = <3>;
                    #size-cells = <2>;
                    #interrupt-cells = <1>;
                    interrupts = <119>;
                    interrupt-map-mask = <0x0 0x0 0x0 0x7>;
                    interrupt-map = <0 0 0 1 &pcie_intc0 0>,
                                    <0 0 0 2 &pcie_intc0 1>,
                                    <0 0 0 3 &pcie_intc0 2>,
                                    <0 0 0 4 &pcie_intc0 3>;
                    interrupt-parent = <&plic0>;
                    msi-parent = <&pcie0>;
                    msi-controller;
                    bus-range = <0x00 0x7f>;
                    ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
                    pcie_intc0: interrupt-controller {
                        #address-cells = <0>;
                        #interrupt-cells = <1>;
                        interrupt-controller;
                    };
            };
    };


code:
* Mobiveil AXI PCIe Root Port Bridge DT description

Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
has up to 8 outbound and inbound windows for the address translation.

Required properties:
- #address-cells: Address representation for root ports, set to <3>
- #size-cells: Size representation for root ports, set to <2>
- #interrupt-cells: specifies the number of cells needed to encode an
	interrupt source. The value must be 1.
- compatible: Should contain "mbvl,gpex40-pcie"
- reg: Should contain PCIe registers location and length
	Mandatory:
	"config_axi_slave": PCIe controller registers
	"csr_axi_slave"	  : Bridge config registers
	Optional:
	"gpio_slave"	  : GPIO registers to control slot power
	"apb_csr"	  : MSI registers

- device_type: must be "pci"
- apio-wins : number of requested apio outbound windows
		default 2 outbound windows are configured -
		1. Config window
		2. Memory window
- ppio-wins : number of requested ppio inbound windows
		default 1 inbound memory window is configured.
- bus-range: PCI bus numbers covered
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an
	interrupt source. The value must be 1.
- interrupts: The interrupt line of the PCIe controller
		last cell of this field is set to 4 to
		denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.
- interrupt-map-mask,
	interrupt-map: standard PCI properties to define the mapping of the
	PCI interface to interrupt numbers.
- ranges: ranges for the PCI memory regions (I/O space region is not
	supported by hardware)
	Please refer to the standard PCI bus binding document for a more
	detailed explanation

Example:
++++++++
	pcie0: pcie@a0000000 {
		#address-cells = <3>;
		#size-cells = <2>;
		compatible = "mbvl,gpex40-pcie";
		reg =	<0xa0000000 0x00001000>,
			<0xb0000000 0x00010000>,
			<0xff000000 0x00200000>,
			<0xb0010000 0x00001000>;
		reg-names =	"config_axi_slave",
				"csr_axi_slave",
				"gpio_slave",
				"apb_csr";
		device_type = "pci";
		apio-wins = <2>;
		ppio-wins = <1>;
		bus-range = <0x00000000 0x000000ff>;
		interrupt-controller;
		interrupt-parent = <&gic>;
		#interrupt-cells = <1>;
		interrupts = < 0 89 4 >;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 0 &pci_express 0>,
				<0 0 0 1 &pci_express 1>,
				<0 0 0 2 &pci_express 2>,
				<0 0 0 3 &pci_express 3>;
		ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;

	};


code:
* Marvell EBU PCIe interfaces

Mandatory properties:

- compatible: one of the following values:
    marvell,armada-370-pcie
    marvell,armada-xp-pcie
    marvell,dove-pcie
    marvell,kirkwood-pcie
- #address-cells, set to <3>
- #size-cells, set to <2>
- #interrupt-cells, set to <1>
- bus-range: PCI bus numbers covered
- device_type, set to "pci"
- ranges: ranges describing the MMIO registers to control the PCIe
  interfaces, and ranges describing the MBus windows needed to access
  the memory and I/O regions of each PCIe interface.
- msi-parent: Link to the hardware entity that serves as the Message
  Signaled Interrupt controller for this PCI controller.

The ranges describing the MMIO registers have the following layout:

    0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s

where:

  * r is a 32-bits value that gives the offset of the MMIO
  registers of this PCIe interface, from the base of the internal
  registers.

  * s is a 32-bits value that give the size of this MMIO
  registers area. This range entry translates the '0x82000000 0 r' PCI
  address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
  of the internal register window (as identified by MBUS_ID(0xf0,
  0x01)).

The ranges describing the MBus windows have the following layout:

    0x8t000000 s 0     MBUS_ID(w, a) 0 1 0

where:

   * t is the type of the MBus window (as defined by the standard PCI DT
   bindings), 1 for I/O and 2 for memory.

   * s is the PCI slot that corresponds to this PCIe interface

   * w is the 'target ID' value for the MBus window

   * a the 'attribute' value for the MBus window.

Since the location and size of the different MBus windows is not fixed in
hardware, and only determined in runtime, those ranges cover the full first
4 GB of the physical address space, and do not translate into a valid CPU
address.

In addition, the device tree node must have sub-nodes describing each
PCIe interface, having the following mandatory properties:

- reg: used only for interrupt mapping, so only the first four bytes
  are used to refer to the correct bus number and device number.
- assigned-addresses: reference to the MMIO registers used to control
  this PCIe interface.
- clocks: the clock associated to this PCIe interface
- marvell,pcie-port: the physical PCIe port number
- status: either "disabled" or "okay"
- device_type, set to "pci"
- #address-cells, set to <3>
- #size-cells, set to <2>
- #interrupt-cells, set to <1>
- ranges, translating the MBus windows ranges of the parent node into
  standard PCI addresses.
- interrupt-map-mask and interrupt-map, standard PCI properties to
  define the mapping of the PCIe interface to interrupt numbers.

and the following optional properties:
- marvell,pcie-lane: the physical PCIe lane number, for ports having
  multiple lanes. If this property is not found, we assume that the
  value is 0.
- num-lanes: number of SerDes PCIe lanes for this link (1 or 4)
- reset-gpios: optional GPIO to PERST#
- reset-delay-us: delay in us to wait after reset de-assertion, if not
  specified will default to 100ms, as required by the PCIe specification.
- interrupt-names: list of interrupt names, supported are:
   - "intx" - interrupt line triggered by one of the legacy interrupt
- interrupts or interrupts-extended: List of the interrupt sources which
  corresponding to the "interrupt-names". If non-empty then also additional
  'interrupt-controller' subnode must be defined.

Example:

pcie-controller {
	compatible = "marvell,armada-xp-pcie";
	device_type = "pci";

	#address-cells = <3>;
	#size-cells = <2>;

	bus-range = <0x00 0xff>;
	msi-parent = <&mpic>;

	ranges =
	       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000	/* Port 0.0 registers */
		0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000	/* Port 2.0 registers */
		0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000	/* Port 0.1 registers */
		0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000	/* Port 0.2 registers */
		0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000	/* Port 0.3 registers */
		0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000	/* Port 1.0 registers */
		0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000	/* Port 3.0 registers */
		0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000	/* Port 1.1 registers */
		0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000	/* Port 1.2 registers */
		0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000	/* Port 1.3 registers */
		0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
		0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
		0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
		0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
		0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
		0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
		0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
		0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */

		0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
		0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
		0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
		0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
		0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
		0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
		0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
		0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */

		0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
		0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */

		0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
		0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;

	pcie@1,0 {
		device_type = "pci";
		assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
		reg = <0x0800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
			  0x81000000 0 0 0x81000000 0x1 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 58>;
		marvell,pcie-port = <0>;
		marvell,pcie-lane = <0>;
		num-lanes = <1>;
		/* low-active PERST# reset on GPIO 25 */
		reset-gpios = <&gpio0 25 1>;
		/* wait 20ms for device settle after reset deassertion */
		reset-delay-us = <20000>;
		clocks = <&gateclk 5>;
	};

	pcie@2,0 {
		device_type = "pci";
		assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
		reg = <0x1000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
			  0x81000000 0 0 0x81000000 0x2 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 59>;
		marvell,pcie-port = <0>;
		marvell,pcie-lane = <1>;
		num-lanes = <1>;
		clocks = <&gateclk 6>;
	};

	pcie@3,0 {
		device_type = "pci";
		assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
		reg = <0x1800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
			  0x81000000 0 0 0x81000000 0x3 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 60>;
		marvell,pcie-port = <0>;
		marvell,pcie-lane = <2>;
		num-lanes = <1>;
		clocks = <&gateclk 7>;
	};

	pcie@4,0 {
		device_type = "pci";
		assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
		reg = <0x2000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
			  0x81000000 0 0 0x81000000 0x4 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 61>;
		marvell,pcie-port = <0>;
		marvell,pcie-lane = <3>;
		num-lanes = <1>;
		clocks = <&gateclk 8>;
	};

	pcie@5,0 {
		device_type = "pci";
		assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
		reg = <0x2800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
			  0x81000000 0 0 0x81000000 0x5 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 62>;
		marvell,pcie-port = <1>;
		marvell,pcie-lane = <0>;
		num-lanes = <1>;
		clocks = <&gateclk 9>;
	};

	pcie@6,0 {
		device_type = "pci";
		assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
		reg = <0x3000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
			  0x81000000 0 0 0x81000000 0x6 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 63>;
		marvell,pcie-port = <1>;
		marvell,pcie-lane = <1>;
		num-lanes = <1>;
		clocks = <&gateclk 10>;
	};

	pcie@7,0 {
		device_type = "pci";
		assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
		reg = <0x3800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
			  0x81000000 0 0 0x81000000 0x7 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 64>;
		marvell,pcie-port = <1>;
		marvell,pcie-lane = <2>;
		num-lanes = <1>;
		clocks = <&gateclk 11>;
	};

	pcie@8,0 {
		device_type = "pci";
		assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
		reg = <0x4000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
			  0x81000000 0 0 0x81000000 0x8 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 65>;
		marvell,pcie-port = <1>;
		marvell,pcie-lane = <3>;
		num-lanes = <1>;
		clocks = <&gateclk 12>;
	};

	pcie@9,0 {
		device_type = "pci";
		assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
		reg = <0x4800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
			  0x81000000 0 0 0x81000000 0x9 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 99>;
		marvell,pcie-port = <2>;
		marvell,pcie-lane = <0>;
		num-lanes = <1>;
		clocks = <&gateclk 26>;
	};

	pcie@a,0 {
		device_type = "pci";
		assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
		reg = <0x5000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
			  0x81000000 0 0 0x81000000 0xa 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 103>;
		marvell,pcie-port = <3>;
		marvell,pcie-lane = <0>;
		num-lanes = <1>;
		clocks = <&gateclk 27>;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Vidya Sagar <vidyas@nvidia.com>

description: |
  This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
  inherits all the common properties defined in snps,dw-pcie-ep.yaml.  Some
  of the controller instances are dual mode; they can work either in Root
  Port mode or Endpoint mode but one at a time.

  On Tegra194, controllers C0, C4 and C5 support Endpoint mode.
  On Tegra234, controllers C5, C6, C7 and C10 support Endpoint mode.

  Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
  operate in the Endpoint mode because of the way the platform is designed.

properties:
  compatible:
    enum:
      - nvidia,tegra194-pcie-ep
      - nvidia,tegra234-pcie-ep

  reg:
    items:
      - description: controller's application logic registers
      - description: iATU and DMA registers. This is where the iATU (internal
          Address Translation Unit) registers of the PCIe core are made
          available for software access.
      - description: aperture where the Root Port's own configuration
          registers are available.
      - description: aperture used to map the remote Root Complex address space

  reg-names:
    items:
      - const: appl
      - const: atu_dma
      - const: dbi
      - const: addr_space

  interrupts:
    items:
      - description: controller interrupt

  interrupt-names:
    items:
      - const: intr

  clocks:
    items:
      - description: module clock

  clock-names:
    items:
      - const: core

  resets:
    items:
      - description: APB bus interface reset
      - description: module reset

  reset-names:
    items:
      - const: apb
      - const: core

  reset-gpios:
    description: Must contain a phandle to a GPIO controller followed by GPIO
      that is being used as PERST input signal. Please refer to pci.txt.

  phys:
    minItems: 1
    maxItems: 8

  phy-names:
    minItems: 1
    items:
      - const: p2u-0
      - const: p2u-1
      - const: p2u-2
      - const: p2u-3
      - const: p2u-4
      - const: p2u-5
      - const: p2u-6
      - const: p2u-7

  power-domains:
    maxItems: 1
    description: |
      A phandle to the node that controls power to the respective PCIe
      controller and a specifier name for the PCIe controller.

      Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h"
      Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h"

  interconnects:
    items:
      - description: memory read client
      - description: memory write client

  interconnect-names:
    items:
      - const: dma-mem # read
      - const: write

  dma-coherent: true

  nvidia,bpmp:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: |
      Must contain a pair of phandles to BPMP controller node followed by
      controller ID. Following are the controller IDs for each controller:

      Tegra194

        0: C0
        1: C1
        2: C2
        3: C3
        4: C4
        5: C5

      Tegra234

        0 : C0
        1 : C1
        2 : C2
        3 : C3
        4 : C4
        5 : C5
        6 : C6
        7 : C7
        8 : C8
        9 : C9
        10: C10

    items:
      - items:
          - description: phandle to BPMP controller node
          - description: PCIe controller ID
            maximum: 10

  nvidia,aspm-cmrt-us:
    description: Common Mode Restore Time for proper operation of ASPM to be
      specified in microseconds

  nvidia,aspm-pwr-on-t-us:
    description: Power On time for proper operation of ASPM to be specified in
      microseconds

  nvidia,aspm-l0s-entrance-latency-us:
    description: ASPM L0s entrance latency to be specified in microseconds

  vddio-pex-ctl-supply:
    description: A phandle to the regulator supply for PCIe side band signals

  nvidia,refclk-select-gpios:
    maxItems: 1
    description: GPIO used to enable REFCLK to controller from the host

  nvidia,enable-ext-refclk:
    description: |
      This boolean property needs to be present if the controller is configured
      to receive Reference Clock from the host.
      NOTE: This is applicable only for Tegra234.

    $ref: /schemas/types.yaml#/definitions/flag

  nvidia,enable-srns:
    description: |
      This boolean property needs to be present if the controller is
      configured to operate in SRNS (Separate Reference Clocks with No
      Spread-Spectrum Clocking).  NOTE: This is applicable only for
      Tegra234.

    $ref: /schemas/types.yaml#/definitions/flag

allOf:
  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#

unevaluatedProperties: false

required:
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - resets
  - reset-names
  - power-domains
  - reset-gpios
  - vddio-pex-ctl-supply
  - num-lanes
  - phys
  - phy-names
  - nvidia,bpmp

examples:
  - |
    #include <dt-bindings/clock/tegra194-clock.h>
    #include <dt-bindings/gpio/tegra194-gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/tegra194-powergate.h>
    #include <dt-bindings/reset/tegra194-reset.h>

    bus@0 {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges = <0x0 0x0 0x0 0x8 0x0>;

        pcie-ep@141a0000 {
            compatible = "nvidia,tegra194-pcie-ep";
            reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
                  <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
                  <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
                  <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
            reg-names = "appl", "atu_dma", "dbi", "addr_space";
            interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
            interrupt-names = "intr";

            clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
            clock-names = "core";

            resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
                     <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
            reset-names = "apb", "core";

            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
            pinctrl-names = "default";
            pinctrl-0 = <&clkreq_c5_bi_dir_state>;

            nvidia,bpmp = <&bpmp 5>;

            nvidia,aspm-cmrt-us = <60>;
            nvidia,aspm-pwr-on-t-us = <20>;
            nvidia,aspm-l0s-entrance-latency-us = <3>;

            vddio-pex-ctl-supply = <&vdd_1v8ao>;

            reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;

            nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
                                          GPIO_ACTIVE_HIGH>;

            num-lanes = <8>;

            phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
                   <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
                   <&p2u_nvhs_6>, <&p2u_nvhs_7>;

            phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
                        "p2u-5", "p2u-6", "p2u-7";
        };
    };

  - |
    #include <dt-bindings/clock/tegra234-clock.h>
    #include <dt-bindings/gpio/tegra234-gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/tegra234-powergate.h>
    #include <dt-bindings/reset/tegra234-reset.h>

    bus@0 {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges = <0x0 0x0 0x0 0x8 0x0>;

        pcie-ep@141a0000 {
            compatible = "nvidia,tegra234-pcie-ep";
            power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
            reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
                  <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
                  <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
                  <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G)        */
            reg-names = "appl", "atu_dma", "dbi", "addr_space";

            interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
            interrupt-names = "intr";

            clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
            clock-names = "core";

            resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
                     <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
            reset-names = "apb", "core";

            nvidia,bpmp = <&bpmp 5>;

            nvidia,enable-ext-refclk;
            nvidia,aspm-cmrt-us = <60>;
            nvidia,aspm-pwr-on-t-us = <20>;
            nvidia,aspm-l0s-entrance-latency-us = <3>;

            vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;

            reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;

            nvidia,refclk-select-gpios = <&gpio_aon
                                          TEGRA234_AON_GPIO(AA, 4)
                                          GPIO_ACTIVE_HIGH>;

            num-lanes = <8>;

            phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
                   <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
                   <&p2u_nvhs_6>, <&p2u_nvhs_7>;

            phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
                        "p2u-5", "p2u-6", "p2u-7";
        };
    };