code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2014, 2015 Andy Yan <andy.yan@rock-chips.com>
 */

/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3288.dtsi"

/ {
	model = "PopMetal-RK3288";
	compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	ext_gmac: external-gmac-clock {
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
		clock-output-names = "ext_gmac";
		#clock-cells = <0>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;

		pinctrl-names = "default";
		pinctrl-0 = <&pwrbtn>;

		key-power {
			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_POWER>;
			label = "GPIO Key Power";
			linux,input-type = <1>;
			wakeup-source;
			debounce-interval = <100>;
		};
	};

	ir: ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&ir_int>;
	};

	vcc_flash: flash-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc_flash";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&vcc_io>;
	};

	vcc_sd: sdmmc-regulator {
		compatible = "regulator-fixed";
		gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc_pwr>;
		regulator-name = "vcc_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		startup-delay-us = <100000>;
		vin-supply = <&vcc_io>;
	};

	vcc_sys: vsys-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc_sys";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	/*
	 * A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled
	 * by the dvp_pwr pin.
	 */
	vcc18_dvp: vcc18-dvp-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc18-dvp";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&vcc28_dvp>;
	};

	vcc28_dvp: vcc28-dvp-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&dvp_pwr>;
		regulator-name = "vcc28_dvp";
		regulator-min-microvolt = <2800000>;
		regulator-max-microvolt = <2800000>;
		regulator-always-on;
		vin-supply = <&vcc_io>;
	};
};

&cpu0 {
	cpu-supply = <&vdd_cpu>;
};

&cpu1 {
	cpu-supply = <&vdd_cpu>;
};

&cpu2 {
	cpu-supply = <&vdd_cpu>;
};

&cpu3 {
	cpu-supply = <&vdd_cpu>;
};

&emmc {
	bus-width = <8>;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
	vmmc-supply = <&vcc_io>;
	vqmmc-supply = <&vcc_flash>;
	status = "okay";
};

&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	card-detect-delay = <200>;
	disable-wp;                     /* wp not hooked up */
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	vmmc-supply = <&vcc_sd>;
	vqmmc-supply = <&vccio_sd>;
	status = "okay";
};

&gmac {
	phy-supply = <&vcc_lan>;
	phy-mode = "rgmii";
	clock_in_out = "input";
	snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 1000000>;
	assigned-clocks = <&cru SCLK_MAC>;
	assigned-clock-parents = <&ext_gmac>;
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	tx_delay = <0x30>;
	rx_delay = <0x10>;
	status = "okay";
};

&hdmi {
	ddc-i2c-bus = <&i2c5>;
	status = "okay";
};

&i2c0 {
	status = "okay";
	clock-frequency = <400000>;

	rk808: pmic@1b {
		compatible = "rockchip,rk808";
		reg = <0x1b>;
		interrupt-parent = <&gpio0>;
		interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pmic_int &global_pwroff>;
		rockchip,system-power-controller;
		wakeup-source;
		#clock-cells = <1>;
		clock-output-names = "xin32k", "rk808-clkout2";

		vcc1-supply = <&vcc_sys>;
		vcc2-supply = <&vcc_sys>;
		vcc3-supply = <&vcc_sys>;
		vcc4-supply = <&vcc_sys>;
		vcc6-supply = <&vcc_sys>;
		vcc7-supply = <&vcc_sys>;
		vcc8-supply = <&vcc_18>;
		vcc9-supply = <&vcc_io>;
		vcc10-supply = <&vcc_io>;
		vcc11-supply = <&vcc_sys>;
		vcc12-supply = <&vcc_io>;
		vddio-supply = <&vcc_io>;

		regulators {
			vdd_cpu: DCDC_REG1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <1350000>;
				regulator-name = "vdd_arm";
				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdd_gpu: DCDC_REG2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-name = "vdd_gpu";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1000000>;
				};
			};

			vcc_ddr: DCDC_REG3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-name = "vcc_ddr";
				regulator-state-mem {
					regulator-on-in-suspend;
				};
			};

			vcc_io: DCDC_REG4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vcc_io";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <3300000>;
				};
			};

			vcc_lan: LDO_REG1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vcc_lan";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <3300000>;
				};
			};

			vccio_sd: LDO_REG2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vccio_sd";
				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdd_10: LDO_REG3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-name = "vdd_10";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1000000>;
				};
			};

			vcc18_lcd: LDO_REG4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcc18_lcd";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1800000>;
				};
			};

			ldo5: LDO_REG5 {
				regulator-always-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "ldo5";
			};

			vdd10_lcd: LDO_REG6 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-name = "vdd10_lcd";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1000000>;
				};
			};

			vcc_18: LDO_REG7 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcc_18";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1800000>;
				};
			};

			vcca_33: LDO_REG8 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vcca_33";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <3300000>;
				};
			};

			vccio_wl: SWITCH_REG1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-name = "vccio_wl";
				regulator-state-mem {
					regulator-on-in-suspend;
				};
			};

			vcc_lcd: SWITCH_REG2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-name = "vcc_lcd";
				regulator-state-mem {
					regulator-on-in-suspend;
				};
			};
		};
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	ak8963: ak8963@d {
		compatible = "asahi-kasei,ak8975";
		reg = <0x0d>;
		interrupt-parent = <&gpio8>;
		interrupts = <RK_PA1 IRQ_TYPE_EDGE_RISING>;
		pinctrl-names = "default";
		pinctrl-0 = <&comp_int>;
		vdd-supply = <&vcc_io>;
		vid-supply = <&vcc_io>;
	};

	l3g4200d: l3g4200d@69 {
		compatible = "st,l3g4200d-gyro";
		st,drdy-int-pin = <2>;
		reg = <0x69>;
		vdd-supply = <&vcc_io>;
		vddio-supply = <&vcc_io>;
	};

	mma8452: mma8452@1d {
		compatible = "fsl,mma8452";
		reg = <0x1d>;
		interrupt-parent = <&gpio8>;
		interrupts = <RK_PA0 IRQ_TYPE_EDGE_RISING>;
		pinctrl-names = "default";
		pinctrl-0 = <&gsensor_int>;
	};
};

&i2c2 {
	status = "okay";
};

&i2c3 {
	status = "okay";
};

&i2c4 {
	status = "okay";
};

&i2c5 {
	status = "okay";
};

&io_domains {
	status = "okay";

	audio-supply = <&vcca_33>;
	bb-supply = <&vcc_io>;
	dvp-supply = <&vcc18_dvp>;
	flash0-supply = <&vcc_flash>;
	flash1-supply = <&vcc_lan>;
	gpio30-supply = <&vcc_io>;
	gpio1830-supply = <&vcc_io>;
	lcdc-supply = <&vcc_io>;
	sdcard-supply = <&vccio_sd>;
	wifi-supply = <&vccio_wl>;
};

&pinctrl {
	ak8963 {
		comp_int: comp-int {
			rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	buttons {
		pwrbtn: pwrbtn {
			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	dvp {
		dvp_pwr: dvp-pwr {
			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	ir {
		ir_int: ir-int {
			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	mma8452 {
		gsensor_int: gsensor-int {
			rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	pmic {
		pmic_int: pmic-int {
			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	sdmmc {
		sdmmc_pwr: sdmmc-pwr {
			rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&tsadc {
	rockchip,hw-tshut-mode = <0>;
	rockchip,hw-tshut-polarity = <0>;
	status = "okay";
};

&vopb {
	status = "okay";
};

&vopb_mmu {
	status = "okay";
};

&vopl {
	status = "okay";
};

&vopl_mmu {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&uart4 {
	status = "okay";
};

&usbphy {
	status = "okay";
};

&usb_otg {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
 */

/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3288.dtsi"

/ {
	model = "Netxeon R89";
	compatible = "netxeon,r89", "rockchip,rk3288";

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	ext_gmac: external-gmac-clock {
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
		clock-output-names = "ext_gmac";
		#clock-cells = <0>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;

		pinctrl-names = "default";
		pinctrl-0 = <&pwrbtn>;

		key-power {
			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_POWER>;
			label = "GPIO Key Power";
			linux,input-type = <1>;
			wakeup-source;
			debounce-interval = <100>;
		};
	};

	ir: ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <&gpio7 RK_PA0 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&ir_int>;
	};

	vcc_host: vcc-host-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&host_vbus_drv>;
		regulator-name = "vcc_host";
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_otg: vcc-otg-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&otg_vbus_drv>;
		regulator-name = "vcc_otg";
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_sdmmc: sdmmc-regulator {
		compatible = "regulator-fixed";
		regulator-name = "sdmmc-supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
		startup-delay-us = <100000>;
		vin-supply = <&vcc_io>;
	};

	vcc_sys: sys-regulator {
		compatible = "regulator-fixed";
		regulator-name = "sys-supply";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&cpu0 {
	cpu-supply = <&vdd_cpu>;
};

&cpu1 {
	cpu-supply = <&vdd_cpu>;
};

&cpu2 {
	cpu-supply = <&vdd_cpu>;
};

&cpu3 {
	cpu-supply = <&vdd_cpu>;
};

&gmac {
	phy-supply = <&vcc_lan>;
	phy-mode = "rgmii";
	clock_in_out = "input";
	snps,reset-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 1000000>;
	assigned-clocks = <&cru SCLK_MAC>;
	assigned-clock-parents = <&ext_gmac>;
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	tx_delay = <0x30>;
	rx_delay = <0x10>;
	status = "okay";
};

&hdmi {
	status = "okay";
};

&i2c0 {
	status = "okay";

	vdd_cpu: pmic@40 {
		compatible = "silergy,syr827";
		reg = <0x40>;
		fcs,suspend-voltage-selector = <1>;
		regulator-name = "VDD_CPU";
		regulator-enable-ramp-delay = <300>;
		regulator-min-microvolt = <850000>;
		regulator-max-microvolt = <1350000>;
		regulator-ramp-delay = <8000>;
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <&vcc_sys>;
	};

	vdd_gpu: pmic@41 {
		compatible = "silergy,syr828";
		reg = <0x41>;
		fcs,suspend-voltage-selector = <1>;
		regulator-name = "VDD_GPU";
		regulator-enable-ramp-delay = <300>;
		regulator-min-microvolt = <850000>;
		regulator-max-microvolt = <1350000>;
		regulator-ramp-delay = <8000>;
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <&vcc_sys>;
	};

	rtc@51 {
		compatible = "haoyu,hym8563";
		reg = <0x51>;
		#clock-cells = <0>;
		clock-output-names = "xin32k";
		interrupt-parent = <&gpio0>;
		interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&pmic_int>;
	};

	act8846: pmic@5a {
		compatible = "active-semi,act8846";
		reg = <0x5a>;
		pinctrl-names = "default";
		pinctrl-0 = <&pmic_vsel>, <&pwr_hold>;
		system-power-controller;

		regulators {
			vcc_ddr: REG1 {
				regulator-name = "VCC_DDR";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-always-on;
			};

			vcc_io: REG2 {
				regulator-name = "VCC_IO";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vdd_log: REG3 {
				regulator-name = "VDD_LOG";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-always-on;
			};

			vcc_20: REG4 {
				regulator-name = "VCC_20";
				regulator-min-microvolt = <2000000>;
				regulator-max-microvolt = <2000000>;
				regulator-always-on;
			};

			vccio_sd: REG5 {
				regulator-name = "VCCIO_SD";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vdd10_lcd: REG6 {
				regulator-name = "VDD10_LCD";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-always-on;
			};

			vcc_wl: REG7 {
				regulator-name = "VCC_WL";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vcca_33: REG8 {
				regulator-name = "VCCA_33";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vcc_lan: REG9 {
				regulator-name = "VCC_LAN";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vdd_10: REG10 {
				regulator-name = "VDD_10";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-always-on;
			};

			vcc_18: REG11 {
				regulator-name = "VCC_18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			vcc18_lcd: REG12 {
				regulator-name = "VCC18_LCD";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};
		};
	};
};

&i2c5 {
	status = "okay";
};

&pinctrl {
	pcfg_output_high: pcfg-output-high {
		output-high;
	};

	pcfg_output_low: pcfg-output-low {
		output-low;
	};

	act8846 {
		pmic_vsel: pmic-vsel {
			rockchip,pins = <7 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>;
		};

		pwr_hold: pwr-hold {
			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>;
		};
	};

	buttons {
		pwrbtn: pwrbtn {
			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	ir {
		ir_int: ir-int {
			rockchip,pins = <7 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	pmic {
		pmic_int: pmic-int {
			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	usb {
		host_vbus_drv: host-vbus-drv {
			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		otg_vbus_drv: otg-vbus-drv {
			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&pwm0 {
	status = "okay";
};

&saradc {
	vref-supply = <&vcc_18>;
	status = "okay";
};

&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	card-detect-delay = <200>;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
	vmmc-supply = <&vcc_sdmmc>;
	vqmmc-supply = <&vccio_sd>;
	status = "okay";
};

&tsadc {
	rockchip,hw-tshut-mode = <0>;
	rockchip,hw-tshut-polarity = <0>;
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&uart4 {
	status = "okay";
};

&usb_host0_ehci {
	status = "okay";
};

&usb_host1 {
	status = "okay";
};

&usb_otg {
	status = "okay";
};

&usbphy {
	status = "okay";
};

&vopb {
	status = "okay";
};

&vopb_mmu {
	status = "okay";
};

&vopl {
	status = "okay";
};

&vopl_mmu {
	status = "okay";
};

&wdt {
	status = "okay";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
 * Copyright (c) 2019 Vamrs Limited
 * Copyright (c) 2019 Amarula Solutions(India)
 */

/dts-v1/;
#include "rk3288.dtsi"
#include <arm/rockchip-radxa-dalang-carrier.dtsi>
#include "rk3288-vmarc-som.dtsi"

/ {
	model = "Radxa ROCK Pi N8";
	compatible = "radxa,rockpi-n8", "vamrs,rk3288-vmarc-som",
		     "rockchip,rk3288";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

#include <dt-bindings/pwm/pwm.h>
#include "rk3288.dtsi"

/ {
	memory@0 {
		reg = <0x0 0x0 0x0 0x80000000>;
		device_type = "memory";
	};

	emmc_pwrseq: emmc-pwrseq {
		compatible = "mmc-pwrseq-emmc";
		pinctrl-0 = <&emmc_reset>;
		pinctrl-names = "default";
		reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
	};

	ext_gmac: external-gmac-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
		clock-output-names = "ext_gmac";
	};

	vcc_flash: flash-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc_flash";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		startup-delay-us = <150>;
		vin-supply = <&vcc_io>;
	};

	vcc_sys: vsys-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc_sys";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};
};

&cpu0 {
	cpu0-supply = <&vdd_cpu>;
};

&emmc {
	bus-width = <8>;
	cap-mmc-highspeed;
	disable-wp;
	non-removable;
	mmc-pwrseq = <&emmc_pwrseq>;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
	vmmc-supply = <&vcc_io>;
	vqmmc-supply = <&vcc_flash>;
	status = "okay";
};

&gmac {
	assigned-clocks = <&cru SCLK_MAC>;
	assigned-clock-parents = <&ext_gmac>;
	clock_in_out = "input";
	phy-mode = "rgmii";
	phy-supply = <&vccio_pmu>;
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins &phy_rst>;
	snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 30000>;
	rx_delay = <0x10>;
	tx_delay = <0x30>;
};

&gpu {
	mali-supply = <&vdd_gpu>;
	status = "okay";
};

&i2c0 {
	status = "okay";

	act8846: act8846@5a {
		compatible = "active-semi,act8846";
		reg = <0x5a>;
		system-power-controller;
		inl1-supply = <&vcc_io>;
		inl2-supply = <&vcc_sys>;
		inl3-supply = <&vcc_20>;
		vp1-supply = <&vcc_sys>;
		vp2-supply = <&vcc_sys>;
		vp3-supply = <&vcc_sys>;
		vp4-supply = <&vcc_sys>;

		regulators {
			vcc_ddr: REG1 {
				regulator-name = "VCC_DDR";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-always-on;
			};

			vcc_io: vccio_codec: REG2 {
				regulator-name = "VCC_IO";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vdd_log: REG3 {
				regulator-name = "VDD_LOG";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-always-on;
			};

			vcc_20: REG4 {
				regulator-name = "VCC_20";
				regulator-min-microvolt = <2000000>;
				regulator-max-microvolt = <2000000>;
				regulator-always-on;
			};

			vccio_sd: REG5 {
				regulator-name = "VCCIO_SD";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vdd10_lcd: REG6 {
				regulator-name = "VDD10_LCD";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-always-on;
			};

			vcca_codec: REG7 {
				regulator-name = "VCCA_CODEC";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vcca_tp: REG8 {
				regulator-name = "VCCA_TP";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vccio_pmu: REG9 {
				regulator-name = "VCCIO_PMU";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};

			vdd_10: REG10 {
				regulator-name = "VDD_10";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-always-on;
			};

			vcc_18: REG11 {
				regulator-name = "VCC_18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			vcc18_lcd: REG12 {
				regulator-name = "VCC18_LCD";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};
		};
	};

	vdd_cpu: syr827@40 {
		compatible = "silergy,syr827";
		reg = <0x40>;
		fcs,suspend-voltage-selector = <1>;
		regulator-always-on;
		regulator-boot-on;
		regulator-enable-ramp-delay = <300>;
		regulator-name = "vdd_cpu";
		regulator-min-microvolt = <850000>;
		regulator-max-microvolt = <1350000>;
		regulator-ramp-delay = <8000>;
		vin-supply = <&vcc_sys>;
	};

	vdd_gpu: syr828@41 {
		compatible = "silergy,syr828";
		reg = <0x41>;
		fcs,suspend-voltage-selector = <1>;
		regulator-always-on;
		regulator-enable-ramp-delay = <300>;
		regulator-min-microvolt = <850000>;
		regulator-max-microvolt = <1350000>;
		regulator-name = "vdd_gpu";
		regulator-ramp-delay = <8000>;
		vin-supply = <&vcc_sys>;
	};
};

&io_domains {
	status = "okay";

	audio-supply = <&vcc_io>;
	bb-supply = <&vcc_io>;
	dvp-supply = <&vcc_18>;
	flash0-supply = <&vcc_flash>;
	flash1-supply = <&vccio_pmu>;
	gpio30-supply = <&vccio_pmu>;
	gpio1830-supply = <&vcc_io>;
	lcdc-supply = <&vcc_io>;
	sdcard-supply = <&vccio_sd>;
	wifi-supply = <&vcc_18>;
};

&pinctrl {
	pcfg_output_high: pcfg-output-high {
		output-high;
	};

	emmc {
		emmc_reset: emmc-reset {
			rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	gmac {
		phy_rst: phy-rst {
			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
		};
	};
};

&saradc {
	vref-supply = <&vcc_18>;
};

&tsadc {
	rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
	rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
	status = "okay";
};

&vopb {
	status = "okay";
};

&vopb_mmu {
	status = "okay";
};

&vopl {
	status = "okay";
};

&vopl_mmu {
	status = "okay";
};

&wdt {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3288-rock2-som.dtsi"

/ {
	model = "Radxa Rock 2 Square";
	compatible = "radxa,rock2-square", "rockchip,rk3288";

	chosen {
		stdout-path = "serial2:115200n8";
	};

	adc-keys {
		compatible = "adc-keys";
		io-channels = <&saradc 1>;
		io-channel-names = "buttons";
		keyup-threshold-microvolt = <1800000>;

		button-recovery {
			label = "Recovery";
			linux,code = <KEY_VENDOR>;
			press-threshold-microvolt = <0>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-power {
			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
			label = "GPIO Power";
			linux,code = <KEY_POWER>;
			pinctrl-names = "default";
			pinctrl-0 = <&pwr_key>;
			wakeup-source;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		heartbeat_led: led-0 {
			gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_LOW>;
			label = "rock2:green:state1";
			linux,default-trigger = "heartbeat";
		};

		mmc_led: led-1 {
			gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
			label = "rock2:blue:state2";
			linux,default-trigger = "mmc0";
		};
	};

	ir: ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&ir_int>;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "SPDIF";
		simple-audio-card,dai-link@1 {  /* S/PDIF - S/PDIF */
			cpu { sound-dai = <&spdif>; };
			codec { sound-dai = <&spdif_out>; };
		};
	};

	sata_pwr: sata-prw-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&sata_pwr_en>;
		/* Always turn on the 5V sata power connector */
		regulator-always-on;
		regulator-name = "sata_pwr";
	};

	spdif_out: spdif-out {
		compatible = "linux,spdif-dit";
		#sound-dai-cells = <0>;
	};

	sound-i2s {
		compatible = "rockchip,rk3288-hdmi-analog";
		pinctrl-names = "default";
		pinctrl-0 = <&phone_ctl>, <&hp_det>;
		rockchip,audio-codec = <&es8388>;
		rockchip,hp-det-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
		rockchip,hp-en-gpios = <&gpio8 0 GPIO_ACTIVE_HIGH>;
		rockchip,i2s-controller = <&i2s>;
		rockchip,model = "I2S";
		rockchip,routing = "Analog", "LOUT2",
				   "Analog", "ROUT2";
	};

	sdio_pwrseq: sdio-pwrseq {
		compatible = "mmc-pwrseq-simple";
		clocks = <&hym8563>;
		clock-names = "ext_clock";
		pinctrl-names = "default";
		pinctrl-0 = <&wifi_enable>;
		reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
	};

	vcc_usb_host: vcc-host-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&host_vbus_drv>;
		regulator-name = "vcc_host";
	};

	vcc_sd: sdmmc-regulator {
		compatible = "regulator-fixed";
		gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc_pwr>;
		regulator-name = "vcc_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vcc_io>;
	};
};

&sdio0 {
	bus-width = <4>;
	cap-sd-highspeed;
	cap-sdio-irq;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>;
	vmmc-supply = <&vcc_io>;
	vqmmc-supply = <&vcc_18>;
	status = "okay";
};

&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	card-detect-delay = <200>;
	disable-wp;	/* wp not hooked up */
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
	vmmc-supply = <&vcc_sd>;
	vqmmc-supply = <&vccio_sd>;
	status = "okay";
};

&gmac {
	status = "okay";
};

&hdmi {
	ddc-i2c-bus = <&i2c5>;
	status = "okay";
};

&i2c0 {
	hym8563: rtc@51 {
		compatible = "haoyu,hym8563";
		reg = <0x51>;
		#clock-cells = <0>;
		clock-output-names = "xin32k";
		interrupt-parent = <&gpio0>;
		interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&pmic_int>;

	};
};

&i2c2 {
	status = "okay";

	es8388: es8388@10 {
		compatible = "everest,es8388", "everest,es8328";
		reg = <0x10>;
		AVDD-supply = <&vccio_codec>;
		DVDD-supply = <&vccio_codec>;
		HPVDD-supply = <&vccio_codec>;
		PVDD-supply = <&vccio_codec>;
		clocks = <&cru SCLK_I2S0_OUT>;
	};
};

&i2c5 {
	status = "okay";
};

&i2s {
	status = "okay";
};

&pinctrl {
	ir {
		ir_int: ir-int {
			rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	keys {
		pwr_key: pwr-key {
			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	pmic {
		pmic_int: pmic-int {
			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	headphone {
		hp_det: hp-det {
			rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		phone_ctl: phone-ctl {
			rockchip,pins = <8 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	usb {
		host_vbus_drv: host-vbus-drv {
			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	sata {
		sata_pwr_en: sata-pwr-en {
			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	sdmmc {
		sdmmc_pwr: sdmmc-pwr {
			rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	sdio {
		wifi_enable: wifi-enable {
			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&saradc {
	status = "okay";
};

&spdif {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&usbphy {
	status = "okay";
};

&usbphy1 {
	vbus-supply = <&vcc_usb_host>;
};

&usb_host0_ehci {
	status = "okay";
};

&usb_host1 {
	status = "okay";
};

&usb_otg {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
 */

/dts-v1/;

#include "rk3288-tinker.dtsi"

/ {
	model = "Rockchip RK3288 Asus Tinker Board S";
	compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
};

&emmc {
	bus-width = <8>;
	cap-mmc-highspeed;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
	max-frequency = <150000000>;
	mmc-hs200-1_8v;
	mmc-ddr-1_8v;
	status = "okay";
};

&hdmi {
	pinctrl-names = "default";
	pinctrl-0 = <&hdmi_cec_c0>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
 */

/dts-v1/;

#include "rk3288-tinker.dtsi"

/ {
	model = "Rockchip RK3288 Asus Tinker Board";
	compatible = "asus,rk3288-tinker", "rockchip,rk3288";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
 */

#include "rk3288.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/rockchip,rk808.h>

/ {
	chosen {
		stdout-path = "serial2:115200n8";
	};

	memory {
		reg = <0x0 0x0 0x0 0x80000000>;
		device_type = "memory";
	};

	ext_gmac: external-gmac-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
		clock-output-names = "ext_gmac";
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;

		pinctrl-names = "default";
		pinctrl-0 = <&pwrbtn>;

		button {
			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_POWER>;
			label = "GPIO Key Power";
			linux,input-type = <1>;
			wakeup-source;
			debounce-interval = <100>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		act_led: led-0 {
			gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "mmc0";
		};

		heartbeat_led: led-1 {
			gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};

		pwr_led: led-2 {
			gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "default-on";
		};
	};

	sdio_pwrseq: sdio-pwrseq {
		compatible = "mmc-pwrseq-simple";
		clocks = <&rk808 RK808_CLKOUT1>;
		clock-names = "ext_clock";
		pinctrl-names = "default";
		pinctrl-0 = <&wifi_enable>;
		reset-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>,
			<&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,name = "rockchip,tinker-codec";
		simple-audio-card,mclk-fs = <512>;

		simple-audio-card,codec {
			sound-dai = <&hdmi>;
		};

		simple-audio-card,cpu {
			sound-dai = <&i2s>;
		};
	};

	vcc_sys: vsys-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc_sys";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vcc_sd: sdmmc-regulator {
		compatible = "regulator-fixed";
		gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc_pwr>;
		regulator-name = "vcc_sd";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		startup-delay-us = <100000>;
		vin-supply = <&vcc_io>;
	};
};

&cpu0 {
	cpu0-supply = <&vdd_cpu>;
};

&cpu_opp_table {
	opp-1704000000 {
		opp-hz = /bits/ 64 <1704000000>;
		opp-microvolt = <1350000>;
	};
	opp-1800000000 {
		opp-hz = /bits/ 64 <1800000000>;
		opp-microvolt = <1400000>;
	};
};

&gmac {
	assigned-clocks = <&cru SCLK_MAC>;
	assigned-clock-parents = <&ext_gmac>;
	clock_in_out = "input";
	phy-mode = "rgmii";
	phy-supply = <&vcc33_lan>;
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>;
	snps,reset-gpio = <&gpio4 7 0>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 1000000>;
	tx_delay = <0x30>;
	rx_delay = <0x10>;
	status = "okay";
};

&gpu {
	mali-supply = <&vdd_gpu>;
	status = "okay";
};

&hdmi {
	ddc-i2c-bus = <&i2c5>;
	status = "okay";
};

&i2c0 {
	clock-frequency = <400000>;
	status = "okay";

	rk808: pmic@1b {
		compatible = "rockchip,rk808";
		reg = <0x1b>;
		interrupt-parent = <&gpio0>;
		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
		#clock-cells = <1>;
		clock-output-names = "xin32k", "rk808-clkout2";
		dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
				<&gpio0 12 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
		rockchip,system-power-controller;
		wakeup-source;

		vcc1-supply = <&vcc_sys>;
		vcc2-supply = <&vcc_sys>;
		vcc3-supply = <&vcc_sys>;
		vcc4-supply = <&vcc_sys>;
		vcc6-supply = <&vcc_sys>;
		vcc7-supply = <&vcc_sys>;
		vcc8-supply = <&vcc_io>;
		vcc9-supply = <&vcc_io>;
		vcc10-supply = <&vcc_io>;
		vcc11-supply = <&vcc_sys>;
		vcc12-supply = <&vcc_io>;
		vddio-supply = <&vcc_io>;

		regulators {
			vdd_cpu: DCDC_REG1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <750000>;
				regulator-max-microvolt = <1400000>;
				regulator-name = "vdd_arm";
				regulator-ramp-delay = <6000>;
				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdd_gpu: DCDC_REG2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <1250000>;
				regulator-name = "vdd_gpu";
				regulator-ramp-delay = <6000>;
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1000000>;
				};
			};

			vcc_ddr: DCDC_REG3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-name = "vcc_ddr";
				regulator-state-mem {
					regulator-on-in-suspend;
				};
			};

			vcc_io: DCDC_REG4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vcc_io";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <3300000>;
				};
			};

			vcc18_ldo1: LDO_REG1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcc18_ldo1";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1800000>;
				};
			};

			vcc33_mipi: LDO_REG2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vcc33_mipi";
				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdd_10: LDO_REG3 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-name = "vdd_10";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1000000>;
				};
			};

			vcc18_codec: LDO_REG4 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcc18_codec";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1800000>;
				};
			};

			vccio_sd: LDO_REG5 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-name = "vccio_sd";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <3300000>;
				};
			};

			vdd10_lcd: LDO_REG6 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1000000>;
				regulator-name = "vdd10_lcd";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1000000>;
				};
			};

			vcc_18: LDO_REG7 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcc_18";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1800000>;
				};
			};

			vcc18_lcd: LDO_REG8 {
				regulator-always-on;
				regulator-boot-on;
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-name = "vcc18_lcd";
				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1800000>;
				};
			};

			vcc33_sd: SWITCH_REG1 {
				regulator-always-on;
				regulator-boot-on;
				regulator-name = "vcc33_sd";
				regulator-state-mem {
					regulator-on-in-suspend;
				};
			};

			vcc33_lan: SWITCH_REG2 {
				regulator-always-on;
				regulator-boot-on;
				regulator-name = "vcc33_lan";
				regulator-state-mem {
					regulator-on-in-suspend;
				};
			};
		};
	};
};

&i2c2 {
	status = "okay";
};

&i2c5 {
	status = "okay";
};

&i2s {
	#sound-dai-cells = <0>;
	status = "okay";
};

&io_domains {
	status = "okay";

	sdcard-supply = <&vccio_sd>;
	wifi-supply = <&vcc_18>;
};

&pinctrl {
	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
		drive-strength = <8>;
	};

	pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
		bias-pull-up;
		drive-strength = <8>;
	};

	backlight {
		bl_en: bl-en {
			rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	buttons {
		pwrbtn: pwrbtn {
			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	eth_phy {
		eth_phy_pwr: eth-phy-pwr {
			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	pmic {
		pmic_int: pmic-int {
			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
		};

		dvs_1: dvs-1 {
			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
		};

		dvs_2: dvs-2 {
			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
		};
	};

	sdmmc {
		sdmmc_bus4: sdmmc-bus4 {
			rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up_drv_8ma>,
					<6 RK_PC1 1 &pcfg_pull_up_drv_8ma>,
					<6 RK_PC2 1 &pcfg_pull_up_drv_8ma>,
					<6 RK_PC3 1 &pcfg_pull_up_drv_8ma>;
		};

		sdmmc_clk: sdmmc-clk {
			rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
		};

		sdmmc_cmd: sdmmc-cmd {
			rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up_drv_8ma>;
		};

		sdmmc_pwr: sdmmc-pwr {
			rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	usb {
		host_vbus_drv: host-vbus-drv {
			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		pwr_3g: pwr-3g {
			rockchip,pins = <7 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	sdio {
		wifi_enable: wifi-enable {
			rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
					<4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&pwm0 {
	status = "okay";
};

&saradc {
	vref-supply = <&vcc18_ldo1>;
	status = "okay";
};

&sdmmc {
	bus-width = <4>;
	cap-mmc-highspeed;
	cap-sd-highspeed;
	broken-cd;
	disable-wp;			/* wp not hooked up */
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
	status = "okay";
	vmmc-supply = <&vcc33_sd>;
	vqmmc-supply = <&vccio_sd>;
};

&sdio0 {
	bus-width = <4>;
	cap-sd-highspeed;
	cap-sdio-irq;
	keep-power-in-suspend;
	max-frequency = <50000000>;
	mmc-pwrseq = <&sdio_pwrseq>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	vmmc-supply = <&vcc_io>;
	vqmmc-supply = <&vcc_18>;
	status = "okay";
};

&tsadc {
	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&uart4 {
	status = "okay";
};

&usbphy {
	status = "okay";
};

&usb_host0_ehci {
	status = "okay";
};

&usb_host1 {
	status = "okay";
};

&usb_otg {
	status = "okay";
};

&vopb {
	status = "okay";
};

&vopb_mmu {
	status = "okay";
};

&vopl {
	status = "okay";
};

&vopl_mmu {
	status = "okay";
};

&wdt {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Google Veyron (and derivatives) fragment for the  max98090 audio
 * codec and analog headphone jack.
 *
 * Copyright 2016 Google, Inc
 */

/ {
	sound {
		compatible = "rockchip,rockchip-audio-max98090";
		pinctrl-names = "default";
		pinctrl-0 = <&mic_det>, <&hp_det>;
		rockchip,model = "VEYRON-I2S";
		rockchip,i2s-controller = <&i2s>;
		rockchip,audio-codec = <&max98090>;
		rockchip,hp-det-gpios = <&gpio6 RK_PA5 GPIO_ACTIVE_HIGH>;
		rockchip,mic-det-gpios = <&gpio6 RK_PB3 GPIO_ACTIVE_LOW>;
		rockchip,headset-codec = <&headsetcodec>;
		rockchip,hdmi-codec = <&hdmi>;
	};
};

&i2c2 {
	max98090: max98090@10 {
		compatible = "maxim,max98090";
		reg = <0x10>;
		interrupt-parent = <&gpio6>;
		interrupts = <RK_PA7 IRQ_TYPE_EDGE_FALLING>;
		clock-names = "mclk";
		clocks = <&cru SCLK_I2S0_OUT>;
		pinctrl-names = "default";
		pinctrl-0 = <&int_codec>;
	};
};

&i2c4 {
	headsetcodec: ts3a227e@3b {
		compatible = "ti,ts3a227e";
		reg = <0x3b>;
		interrupt-parent = <&gpio0>;
		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&ts3a227e_int_l>;
		ti,micbias = <7>;		/* MICBIAS = 2.8V */
	};
};

&i2s {
	status = "okay";
};

&io_domains {
	audio-supply = <&vcc18_codec>;
};

&rk808 {
	vcc10-supply = <&vcc33_sys>;

	regulators {
		vcc18_codec: LDO_REG6 {
			regulator-name = "vcc18_codec";
			regulator-always-on;
			regulator-boot-on;
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};
	};
};

&pinctrl {
	codec {
		hp_det: hp-det {
			rockchip,pins = <6 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
		};

		/*
		 * HACK: We're going to _pull down_ this _active low_ interrupt
		 * so that it never fires.  We don't need this interrupt because
		 * we've got a ts3a227e chip but the driver requires it.
		 */
		int_codec: int-codec {
			rockchip,pins = <6 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
		};

		mic_det: mic-det {
			rockchip,pins = <6 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	headset {
		ts3a227e_int_l: ts3a227e-int-l {
			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Google Veyron Brain Rev 0 board device tree source
 *
 * Copyright 2014 Google, Inc
 */

/dts-v1/;
#include "rk3288-veyron.dtsi"
#include "rk3288-veyron-broadcom-bluetooth.dtsi"

/ {
	model = "Google Brain";
	compatible = "google,veyron-brain-rev0", "google,veyron-brain",
		     "google,veyron", "rockchip,rk3288";

	vcc33_sys: vcc33-sys {
		vin-supply = <&vcc_5v>;
	};

	vcc33_io: vcc33_io {
		compatible = "regulator-fixed";
		regulator-name = "vcc33_io";
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <&vcc33_sys>;
		/* This is gated by vcc_18 too */
	};

	/* This turns on vbus for host2 and otg (dwc2) */
	vcc5_host2: vcc5-host2-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&usb2_pwr_en>;
		regulator-name = "vcc5_host2";
		regulator-always-on;
		regulator-boot-on;
	};
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <
		/* Common for sleep and wake, but no owners */
		&ddr0_retention
		&ddrio_pwroff
		&global_pwroff
	>;

	hdmi {
		vcc50_hdmi_en: vcc50-hdmi-en {
			rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	pmic {
		dvs_1: dvs-1 {
			rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
		};

		dvs_2: dvs-2 {
			rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
		};
	};

	usb-host {
		usb2_pwr_en: usb2-pwr-en {
			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&rk808 {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
	dvs-gpios = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>,
		    <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;

	/delete-property/ vcc6-supply;

	regulators {
		/* vcc33_io is sourced directly from vcc33_sys */
		/delete-node/ LDO_REG1;

		/* This is not a pwren anymore, but the real power supply */
		vdd10_lcd: LDO_REG7 {
			regulator-always-on;
			regulator-boot-on;
			regulator-min-microvolt = <1000000>;
			regulator-max-microvolt = <1000000>;
			regulator-name = "vdd10_lcd";
			regulator-suspend-mem-disabled;
		};

		vcc18_hdmi: SWITCH_REG2 {
			regulator-always-on;
			regulator-boot-on;
			regulator-name = "vcc18_hdmi";
			regulator-suspend-mem-disabled;
		};
	};
};

&vcc50_hdmi {
	enable-active-high;
	gpio = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&vcc50_hdmi_en>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth
 * chip.
 *
 * Copyright 2019 Google, Inc
 */

&uart0 {
	bluetooth {
		pinctrl-names = "default";
		pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>,
			    <&bt_dev_wake>;

		compatible = "brcm,bcm43540-bt";
		host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
		shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
		device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
		max-speed = <3000000>;
		brcm,bt-pcm-int-params = [01 02 00 01 01];
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Google Veyron (and derivatives) board device tree source
 * Chromebook specific parts
 *
 * Copyright 2015 Google, Inc
 */

#include <dt-bindings/clock/rockchip,rk808.h>
#include <dt-bindings/input/input.h>
#include "rk3288-veyron.dtsi"
#include "rk3288-veyron-analog-audio.dtsi"
#include "rk3288-veyron-edp.dtsi"
#include "rk3288-veyron-sdmmc.dtsi"

/ {
	aliases {
		/* Assign 20 so we don't get confused w/ builtin ones */
		i2c20 = &i2c_tunnel;
	};

	gpio-charger {
		compatible = "gpio-charger";
		charger-type = "mains";
		gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&ac_present_ap>;
	};

	lid_switch: lid-switch {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&ap_lid_int_l>;

		switch-lid {
			label = "Lid";
			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
			wakeup-source;
			linux,code = <SW_LID>;
			linux,input-type = <EV_SW>;
			debounce-interval = <1>;
		};
	};

	/* A non-regulated voltage from power supply or battery */
	vccsys: vccsys {
		compatible = "regulator-fixed";
		regulator-name = "vccsys";
		regulator-boot-on;
		regulator-always-on;
	};

	vcc33_sys: vcc33-sys {
		vin-supply = <&vccsys>;
	};

	vcc_5v: vcc-5v {
		vin-supply = <&vccsys>;
	};

	/* This turns on vbus for host1 (dwc2) */
	vcc5_host1: vcc5-host1-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&host1_pwr_en>;
		regulator-name = "vcc5_host1";
		regulator-always-on;
		regulator-boot-on;
	};

	/* This turns on vbus for otg for host mode (dwc2) */
	vcc5v_otg: vcc5v-otg-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&usbotg_pwren_h>;
		regulator-name = "vcc5_host2";
		regulator-always-on;
		regulator-boot-on;
	};
};

&rk808 {
	vcc11-supply = <&vcc_5v>;

	regulators {
		vcc33_ccd: LDO_REG8 {
			regulator-name = "vcc33_ccd";
			regulator-always-on;
			regulator-boot-on;
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};
	};
};

&spi0 {
	status = "okay";

	cros_ec: ec@0 {
		compatible = "google,cros-ec-spi";
		reg = <0>;
		google,cros-ec-spi-pre-delay = <30>;
		interrupt-parent = <&gpio7>;
		interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&ec_int>;
		spi-max-frequency = <3000000>;

		i2c_tunnel: i2c-tunnel {
			compatible = "google,cros-ec-i2c-tunnel";
			google,remote-bus = <0>;
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};
};

&i2c4 {
	trackpad@15 {
		compatible = "elan,ekth3000";
		reg = <0x15>;
		interrupt-parent = <&gpio7>;
		interrupts = <RK_PA3 IRQ_TYPE_EDGE_FALLING>;
		pinctrl-names = "default";
		pinctrl-0 = <&trackpad_int>;
		vcc-supply = <&vcc33_io>;
		wakeup-source;
	};
};

&pinctrl {
	buttons {
		ap_lid_int_l: ap-lid-int-l {
			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	charger {
		ac_present_ap: ac-present-ap {
			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	cros-ec {
		ec_int: ec-int {
			rockchip,pins = <7 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	suspend {
		suspend_l_wake: suspend-l-wake {
			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
		};

		suspend_l_sleep: suspend-l-sleep {
			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>;
		};
	};

	trackpad {
		trackpad_int: trackpad-int {
			rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	usb-host {
		host1_pwr_en: host1-pwr-en {
			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		usbotg_pwren_h: usbotg-pwren-h {
			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

#include "cros-ec-keyboard.dtsi"


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Google Veyron (and derivatives) fragment for the edp displays
 *
 * Copyright 2019 Google LLC
 */

/ {
	backlight_regulator: backlight-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&bl_pwr_en>;
		regulator-name = "backlight_regulator";
		vin-supply = <&vcc33_sys>;
		startup-delay-us = <15000>;
	};

	panel_regulator: panel-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&lcd_enable_h>;
		regulator-name = "panel_regulator";
		vin-supply = <&vcc33_sys>;
	};

	vcc18_lcd: vcc18-lcd {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&avdd_1v8_disp_en>;
		regulator-name = "vcc18_lcd";
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <&vcc18_wl>;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		brightness-levels = <0 255>;
		num-interpolated-steps = <255>;
		default-brightness-level = <128>;
		enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&bl_en>;
		pwms = <&pwm0 0 1000000 0>;
		post-pwm-on-delay-ms = <10>;
		pwm-off-delay-ms = <10>;
		power-supply = <&backlight_regulator>;
	};

	panel: panel {
		compatible = "innolux,n116bge";
		status = "okay";
		power-supply = <&panel_regulator>;
		backlight = <&backlight>;

		panel-timing {
			clock-frequency = <74250000>;
			hactive = <1366>;
			hfront-porch = <136>;
			hback-porch = <60>;
			hsync-len = <30>;
			hsync-active = <0>;
			vactive = <768>;
			vfront-porch = <8>;
			vback-porch = <12>;
			vsync-len = <12>;
			vsync-active = <0>;
		};

		ports {
			panel_in: port {
				panel_in_edp: endpoint {
					remote-endpoint = <&edp_out_panel>;
				};
			};
		};
	};
};

&edp {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&edp_hpd>;

	ports {
		edp_out: port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			edp_out_panel: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&panel_in_edp>;
			};
		};
	};
};

&edp_phy {
	status = "okay";
};

&pwm0 {
	status = "okay";
};

&vopl {
	status = "okay";
};

&vopl_mmu {
	status = "okay";
};

&pinctrl {
	backlight {
		bl_pwr_en: bl_pwr_en {
			rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		bl_en: bl-en {
			rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	lcd {
		lcd_enable_h: lcd-en {
			rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		avdd_1v8_disp_en: avdd-1v8-disp-en {
			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Google Veyron Fievel Rev 0+ board device tree source
 *
 * Copyright 2016 Google, Inc
 */

/dts-v1/;
#include "rk3288-veyron.dtsi"
#include "rk3288-veyron-analog-audio.dtsi"

/ {
	model = "Google Fievel";
	compatible = "google,veyron-fievel-rev8", "google,veyron-fievel-rev7",
		     "google,veyron-fievel-rev6", "google,veyron-fievel-rev5",
		     "google,veyron-fievel-rev4", "google,veyron-fievel-rev3",
		     "google,veyron-fievel-rev2", "google,veyron-fievel-rev1",
		     "google,veyron-fievel-rev0", "google,veyron-fievel",
		     "google,veyron", "rockchip,rk3288";

	vccsys: vccsys {
		compatible = "regulator-fixed";
		regulator-name = "vccsys";
		regulator-boot-on;
		regulator-always-on;
	};

	/*
	 * vcc33_pmuio and vcc33_io is sourced directly from vcc33_sys,
	 * enabled by vcc_18
	 */
	vcc33_io: vcc33-io {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-boot-on;
		regulator-name = "vcc33_io";
	};

	vcc5_host1: vcc5-host1-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio5 RK_PC2 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&hub_usb1_pwr_en>;
		regulator-name = "vcc5_host1";
		regulator-always-on;
		regulator-boot-on;
	};

	vcc5_host2: vcc5-host2-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio5 RK_PB6 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&hub_usb2_pwr_en>;
		regulator-name = "vcc5_host2";
		regulator-always-on;
		regulator-boot-on;
	};

	vcc5v_otg: vcc5v-otg-regulator {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&usb_otg_pwr_en>;
		regulator-name = "vcc5_otg";
		regulator-always-on;
		regulator-boot-on;
	};

	ext_gmac: external-gmac-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
		clock-output-names = "ext_gmac";
	};
};

&gmac {
	status = "okay";

	assigned-clocks = <&cru SCLK_MAC>;
	assigned-clock-parents = <&ext_gmac>;
	clock_in_out = "input";
	phy-handle = <&ethphy>;
	phy-mode = "rgmii";
	phy-supply = <&vcc33_lan>;
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
	rx_delay = <0x10>;
	tx_delay = <0x30>;

	/*
	 * Reset for the RTL8211 PHY which requires a 10-ms reset pulse (low)
	 * with a 30ms settling time.
	 */
	snps,reset-gpio = <&gpio4 RK_PB0 0>;
	snps,reset-active-low;
	snps,reset-delays-us = <0 10000 30000>;
	wakeup-source;

	mdio0 {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy: ethernet-phy@1 {
			reg = <1>;
		};
	};
};

&rk808 {
	dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
		    <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;

	vcc6-supply = <&vcc33_sys>;
	vcc10-supply = <&vcc33_sys>;
	vcc11-supply = <&vcc_5v>;
	vcc12-supply = <&vcc33_sys>;

	regulators {
		/delete-node/ LDO_REG1;

		/*
		 * According to the schematic, vcc18_lcdt is for
		 * HDMI_AVDD_1V8
		 */
		vcc18_lcdt: LDO_REG2 {
			regulator-always-on;
			regulator-boot-on;
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-name = "vdd18_lcdt";
			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};

		/*
		 * This is not a pwren anymore, but the real power supply,
		 * vdd10_lcd for HDMI_AVDD_1V0
		 */
		vdd10_lcd: LDO_REG7 {
			regulator-always-on;
			regulator-boot-on;
			regulator-min-microvolt = <1000000>;
			regulator-max-microvolt = <1000000>;
			regulator-name = "vdd10_lcd";
			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};

		/* for usb camera */
		vcc33_ccd: LDO_REG8 {
			regulator-always-on;
			regulator-boot-on;
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-name = "vcc33_ccd";
			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};

		vcc33_lan: SWITCH_REG2 {
			regulator-name = "vcc33_lan";
		};
	};
};

&sdio0 {
	#address-cells = <1>;
	#size-cells = <0>;

	btmrvl: btmrvl@2 {
		compatible = "marvell,sd8897-bt";
		reg = <2>;
		interrupt-parent = <&gpio4>;
		interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
		marvell,wakeup-pin = /bits/ 16 <13>;
		pinctrl-names = "default";
		pinctrl-0 = <&bt_host_wake_l>;
	};
};

&vcc50_hdmi {
	enable-active-high;
	gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&vcc50_hdmi_en>;
};

&vcc_5v {
	enable-active-high;
	gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&drv_5v>;
};

&gpio0 {
	gpio-line-names = "PMIC_SLEEP_AP",
			  "DDRIO_PWROFF",
			  "DDRIO_RETEN",
			  "TS3A227E_INT_L",
			  "PMIC_INT_L",
			  "PWR_KEY_L",
			  "HUB_USB1_nFALUT",
			  "PHY_PMEB",

			  "PHY_INT",
			  /*
			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
			   * it REC_MODE_L.
			   */
			  "RECOVERY_SW_L",
			  "OTP_OUT",
			  "",
			  "USB_OTG_POWER_EN",
			  "AP_WARM_RESET_H",
			  "USB_OTG_nFALUT",
			  "I2C0_SDA_PMIC",

			  "I2C0_SCL_PMIC",
			  "DEVMODE_L",
			  "USB_INT";
};

&gpio2 {
	gpio-line-names = "CONFIG0",
			  "CONFIG1",
			  "CONFIG2",
			  "",
			  "",
			  "",
			  "",
			  "CONFIG3",

			  "",
			  "EMMC_RST_L",
			  "",
			  "",
			  "BL_PWR_EN",
			  "",
			  "TOUCH_INT",
			  "TOUCH_RST",

			  "I2C3_SCL_TP",
			  "I2C3_SDA_TP";
};

&gpio3 {
	gpio-line-names = "FLASH0_D0",
			  "FLASH0_D1",
			  "FLASH0_D2",
			  "FLASH0_D3",
			  "FLASH0_D4",
			  "FLASH0_D5",
			  "FLASH0_D6",
			  "FLASH0_D7",

			  "VCC5V_GOOD_H",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "FLASH0_CS2/EMMC_CMD",
			  "",
			  "FLASH0_DQS/EMMC_CLKO",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "PHY_TXD2",
			  "PHY_TXD3",
			  "MAC_RXD2",
			  "MAC_RXD3",
			  "PHY_TXD0",
			  "PHY_TXD1",
			  "MAC_RXD0",
			  "MAC_RXD1";
};

&gpio4 {
	gpio-line-names = "MAC_MDC",
			  "MAC_RXDV",
			  "MAC_RXER",
			  "MAC_CLK",
			  "PHY_TXEN",
			  "MAC_MDIO",
			  "MAC_RXCLK",
			  "",

			  "PHY_RST",
			  "PHY_TXCLK",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "UART0_RXD",
			  "UART0_TXD",
			  "UART0_CTS_L",
			  "UART0_RTS_L",
			  "SDIO0_D0",
			  "SDIO0_D1",
			  "SDIO0_D2",
			  "SDIO0_D3",

			  "SDIO0_CMD",
			  "SDIO0_CLK",
			  "BT_DEV_WAKE",
			  "",
			  "WIFI_ENABLE_H",
			  "BT_ENABLE_L",
			  "WIFI_HOST_WAKE",
			  "BT_HOST_WAKE";
};

&gpio5 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "",
			  "",
			  "",
			  "",
			  "USB_OTG_CTL1",
			  "HUB_USB2_CTL1",
			  "HUB_USB2_PWR_EN",
			  "HUB_USB_ILIM_SEL",

			  "USB_OTG_STATUS_L",
			  "HUB_USB1_CTL1",
			  "HUB_USB1_PWR_EN",
			  "VCC50_HDMI_EN";
};

&gpio6 {
	gpio-line-names = "I2S0_SCLK",
			  "I2S0_LRCK_RX",
			  "I2S0_LRCK_TX",
			  "I2S0_SDI",
			  "I2S0_SDO0",
			  "HP_DET_H",
			  "",
			  "INT_CODEC",

			  "I2S0_CLK",
			  "I2C2_SDA",
			  "I2C2_SCL",
			  "MICDET",
			  "",
			  "",
			  "",
			  "",

			  "HUB_USB2_nFALUT",
			  "USB_OTG_ILIM_SEL";
};

&gpio7 {
	gpio-line-names = "LCD_BL_PWM",
			  "PWM_LOG",
			  "BL_EN",
			  "PWR_LED1",
			  "TPM_INT_H",
			  "SPK_ON",
			  /*
			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
			   * it FW_WP_AP.
			   */
			  "AP_FLASH_WP_L",
			  "",

			  "CPU_NMI",
			  "DVSOK",
			  "",
			  "EDP_HPD",
			  "DVS1",
			  "",
			  "LCD_EN",
			  "DVS2",

			  "HDMI_CEC",
			  "I2C4_SDA",
			  "I2C4_SCL",
			  "I2C5_SDA_HDMI",
			  "I2C5_SCL_HDMI",
			  "5V_DRV",
			  "UART2_RXD",
			  "UART2_TXD";
};

&gpio8 {
	gpio-line-names = "RAM_ID0",
			  "RAM_ID1",
			  "RAM_ID2",
			  "RAM_ID3",
			  "I2C1_SDA_TPM",
			  "I2C1_SCL_TPM",
			  "SPI2_CLK",
			  "SPI2_CS0",

			  "SPI2_RXD",
			  "SPI2_TXD";
};

&pinctrl {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <
		/* Common for sleep and wake, but no owners */
		&ddr0_retention
		&ddrio_pwroff
		&global_pwroff

		/* For usb bc1.2 */
		&usb_otg_ilim_sel
		&usb_usb_ilim_sel

		/* Wake only */
		&bt_dev_wake_awake
		&pwr_led1_on
	>;

	pinctrl-1 = <
		/* Common for sleep and wake, but no owners */
		&ddr0_retention
		&ddrio_pwroff
		&global_pwroff

		/* For usb bc1.2 */
		&usb_otg_ilim_sel
		&usb_usb_ilim_sel

		/* Sleep only */
		&bt_dev_wake_sleep
		&pwr_led1_blink
	>;

	buck-5v {
		drv_5v: drv-5v {
			rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	gmac {
		phy_rst: phy-rst {
			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
		};

		phy_pmeb: phy-pmeb {
			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
		};

		phy_int: phy-int {
			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	hdmi {
		vcc50_hdmi_en: vcc50-hdmi-en {
			rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	leds {
		pwr_led1_on: pwr-led1-on {
			rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>;
		};

		pwr_led1_blink: pwr-led1-blink {
			rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>;
		};
	};

	pmic {
		dvs_1: dvs-1 {
			rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
		};

		dvs_2: dvs-2 {
			rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
		};
	};

	usb-bc12 {
		usb_otg_ilim_sel: usb-otg-ilim-sel {
			rockchip,pins = <6 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
		};

		usb_usb_ilim_sel: usb-usb-ilim-sel {
			rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
		};
	};

	usb-host {
		hub_usb1_pwr_en: hub_usb1_pwr_en {
			rockchip,pins = <5 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		hub_usb2_pwr_en: hub_usb2_pwr_en {
			rockchip,pins = <5 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		usb_otg_pwr_en: usb_otg_pwr_en {
			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Google Veyron Jaq Rev 1+ board device tree source
 *
 * Copyright 2015 Google, Inc
 */

/dts-v1/;

#include "rk3288-veyron-chromebook.dtsi"
#include "cros-ec-sbs.dtsi"

/ {
	model = "Google Jaq";
	compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
		     "google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
		     "google,veyron-jaq-rev1", "google,veyron-jaq",
		     "google,veyron", "rockchip,rk3288";
};

&backlight {
	/* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
	brightness-levels = <8 255>;
	num-interpolated-steps = <247>;
};

&rk808 {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
	dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
		    <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;

	regulators {
		mic_vcc: LDO_REG2 {
			regulator-name = "mic_vcc";
			regulator-always-on;
			regulator-boot-on;
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};
	};
};

&sdio0 {
	#address-cells = <1>;
	#size-cells = <0>;

	btmrvl: btmrvl@2 {
		compatible = "marvell,sd8897-bt";
		reg = <2>;
		interrupt-parent = <&gpio4>;
		interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
		marvell,wakeup-pin = /bits/ 16 <13>;
		pinctrl-names = "default";
		pinctrl-0 = <&bt_host_wake_l>;
	};
};

&sdmmc {
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
			&sdmmc_bus4>;
};

&vcc_5v {
	enable-active-high;
	gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&drv_5v>;
};

&vcc50_hdmi {
	enable-active-high;
	gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&vcc50_hdmi_en>;
};

&gpio0 {
	gpio-line-names = "PMIC_SLEEP_AP",
			  "DDRIO_PWROFF",
			  "DDRIO_RETEN",
			  "TS3A227E_INT_L",
			  "PMIC_INT_L",
			  "PWR_KEY_L",
			  "AP_LID_INT_L",
			  "EC_IN_RW",

			  "AC_PRESENT_AP",
			  /*
			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
			   * it REC_MODE_L.
			   */
			  "RECOVERY_SW_L",
			  "OTP_OUT",
			  "HOST1_PWR_EN",
			  "USBOTG_PWREN_H",
			  "AP_WARM_RESET_H",
			  "nFALUT2",
			  "I2C0_SDA_PMIC",

			  "I2C0_SCL_PMIC",
			  "SUSPEND_L",
			  "USB_INT";
};

&gpio2 {
	gpio-line-names = "CONFIG0",
			  "CONFIG1",
			  "CONFIG2",
			  "",
			  "",
			  "",
			  "",
			  "CONFIG3",

			  "",
			  "EMMC_RST_L",
			  "",
			  "",
			  "BL_PWR_EN",
			  "AVDD_1V8_DISP_EN";
};

&gpio3 {
	gpio-line-names = "FLASH0_D0",
			  "FLASH0_D1",
			  "FLASH0_D2",
			  "FLASH0_D3",
			  "FLASH0_D4",
			  "FLASH0_D5",
			  "FLASH0_D6",
			  "FLASH0_D7",

			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "FLASH0_CS2/EMMC_CMD",
			  "",
			  "FLASH0_DQS/EMMC_CLKO";
};

&gpio4 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "UART0_RXD",
			  "UART0_TXD",
			  "UART0_CTS",
			  "UART0_RTS",
			  "SDIO0_D0",
			  "SDIO0_D1",
			  "SDIO0_D2",
			  "SDIO0_D3",

			  "SDIO0_CMD",
			  "SDIO0_CLK",
			  "BT_DEV_WAKE",	/* Maybe missing from mighty? */
			  "",
			  "WIFI_ENABLE_H",
			  "BT_ENABLE_L",
			  "WIFI_HOST_WAKE",
			  "BT_HOST_WAKE";
};

&gpio5 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "",
			  "",
			  "",
			  "",
			  "SPI0_CLK",
			  "SPI0_CS0",
			  "SPI0_TXD",
			  "SPI0_RXD",

			  "",
			  "",
			  "",
			  "VCC50_HDMI_EN";
};

&gpio6 {
	gpio-line-names = "I2S0_SCLK",
			  "I2S0_LRCK_RX",
			  "I2S0_LRCK_TX",
			  "I2S0_SDI",
			  "I2S0_SDO0",
			  "HP_DET_H",
			  "ALS_INT",
			  "INT_CODEC",

			  "I2S0_CLK",
			  "I2C2_SDA",
			  "I2C2_SCL",
			  "MICDET",
			  "",
			  "",
			  "",
			  "",

			  "SDMMC_D0",
			  "SDMMC_D1",
			  "SDMMC_D2",
			  "SDMMC_D3",
			  "SDMMC_CLK",
			  "SDMMC_CMD";
};

&gpio7 {
	gpio-line-names = "LCDC_BL",
			  "PWM_LOG",
			  "BL_EN",
			  "TRACKPAD_INT",
			  "TPM_INT_H",
			  "SDMMC_DET_L",
			  /*
			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
			   * it FW_WP_AP.
			   */
			  "AP_FLASH_WP_L",
			  "EC_INT",

			  "CPU_NMI",
			  "DVSOK",
			  "SDMMC_WP",		/* mighty only */
			  "EDP_HPD",
			  "DVS1",
			  "nFALUT1",		/* nFAULT1 on jaq */
			  "LCD_EN",
			  "DVS2",

			  "VCC5V_GOOD_H",
			  "I2C4_SDA_TP",
			  "I2C4_SCL_TP",
			  "I2C5_SDA_HDMI",
			  "I2C5_SCL_HDMI",
			  "5V_DRV",
			  "UART2_RXD",
			  "UART2_TXD";
};

&gpio8 {
	gpio-line-names = "RAM_ID0",
			  "RAM_ID1",
			  "RAM_ID2",
			  "RAM_ID3",
			  "I2C1_SDA_TPM",
			  "I2C1_SCL_TPM",
			  "SPI2_CLK",
			  "SPI2_CS0",

			  "SPI2_RXD",
			  "SPI2_TXD";
};

&pinctrl {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <
		/* Common for sleep and wake, but no owners */
		&ddr0_retention
		&ddrio_pwroff
		&global_pwroff

		/* Wake only */
		&suspend_l_wake
		&bt_dev_wake_awake
	>;
	pinctrl-1 = <
		/* Common for sleep and wake, but no owners */
		&ddr0_retention
		&ddrio_pwroff
		&global_pwroff

		/* Sleep only */
		&suspend_l_sleep
		&bt_dev_wake_sleep
	>;

	buck-5v {
		drv_5v: drv-5v {
			rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	hdmi {
		vcc50_hdmi_en: vcc50-hdmi-en {
			rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	pmic {
		dvs_1: dvs-1 {
			rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
		};

		dvs_2: dvs-2 {
			rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Google Veyron Jerry Rev 3+ board device tree source
 *
 * Copyright 2015 Google, Inc
 */

/dts-v1/;
#include "rk3288-veyron-chromebook.dtsi"
#include "cros-ec-sbs.dtsi"

/ {
	model = "Google Jerry";
	compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14",
		     "google,veyron-jerry-rev13", "google,veyron-jerry-rev12",
		     "google,veyron-jerry-rev11", "google,veyron-jerry-rev10",
		     "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
		     "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
		     "google,veyron-jerry-rev3", "google,veyron-jerry",
		     "google,veyron", "rockchip,rk3288";
};

&rk808 {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
	dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
		    <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;

	regulators {
		mic_vcc: LDO_REG2 {
			regulator-name = "mic_vcc";
			regulator-always-on;
			regulator-boot-on;
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-state-mem {
				regulator-off-in-suspend;
			};
		};
	};
};

&sdio0 {
	#address-cells = <1>;
	#size-cells = <0>;

	mwifiex: wifi@1 {
		compatible = "marvell,sd8897";
		reg = <1>;

		marvell,caldata-txpwrlimit-2g = /bits/ 8 <
0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x04 0x00 0x0f
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x05 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x06 0x00 0x0f
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x07 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x08 0x00 0x0f
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x09 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0a 0x00 0x0f
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x0b 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0c 0x00 0x0f
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
0x24 0x00 0x67 0x09 0x14 0x0d 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
0x0d 0x09 0x0e 0x09 0x0f 0x09>;

		marvell,caldata-txpwrlimit-5g-sub0 = /bits/ 8 <
0x01 0x00 0x06 0x00 0xf0 0x01 0x89 0x01
0x3a 0x00 0x88 0x13 0x14 0x24 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
0x88 0x13 0x14 0x28 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09
0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05
0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
0x14 0x2c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09
0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09
0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05
0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x30
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05
0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05
0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x34 0x01 0x0c
0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09
0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05
0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05
0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x38 0x01 0x0c 0x02 0x0c
0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a
0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05
0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05
0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x3c 0x01 0x0c 0x02 0x0c 0x03 0x0c
0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a
0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05
0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05
0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x40 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a
0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05
0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>;

		marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 <
0x01 0x00 0x06 0x00 0xaa 0x02 0x89 0x01
0x3a 0x00 0x88 0x13 0x14 0x64 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
0x88 0x13 0x14 0x68 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09
0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05
0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
0x14 0x6c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09
0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09
0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05
0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x70
0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09
0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05
0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05
0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x74 0x01 0x0c
0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09
0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05
0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05
0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x78 0x01 0x0c 0x02 0x0c
0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a
0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05
0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05
0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x7c 0x01 0x0c 0x02 0x0c 0x03 0x0c
0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a
0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05
0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05
0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x80 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a
0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a
0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05
0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01
0x3a 0x00 0x88 0x13 0x14 0x84 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
0x88 0x13 0x14 0x88 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08
0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04
0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
0x14 0x8c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08
0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08
0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04
0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>;

		marvell,caldata-txpwrlimit-5g-sub2 = /bits/ 8 <
0x01 0x00 0x06 0x00 0x36 0x01 0x89 0x01
0x3a 0x00 0x88 0x13 0x14 0x95 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a
0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08
0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
0x88 0x13 0x14 0x99 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a
0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08
0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04
0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
0x14 0x9d 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08
0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08
0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04
0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa1
0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08
0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04
0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05
0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa5 0x01 0x0b
0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08
0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04
0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05
0x1a 0x05 0x1b 0x05>;
	};
};

&sdmmc {
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
			&sdmmc_bus4>;
};

&vcc_5v {
	enable-active-high;
	gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&drv_5v>;
};

&vcc50_hdmi {
	enable-active-high;
	gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&vcc50_hdmi_en>;
};

&gpio0 {
	gpio-line-names = "PMIC_SLEEP_AP",
			  "DDRIO_PWROFF",
			  "DDRIO_RETEN",
			  "TS3A227E_INT_L",
			  "PMIC_INT_L",
			  "PWR_KEY_L",
			  "AP_LID_INT_L",
			  "EC_IN_RW",

			  "AC_PRESENT_AP",
			  /*
			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
			   * it REC_MODE_L.
			   */
			  "RECOVERY_SW_L",
			  "OTP_OUT",
			  "HOST1_PWR_EN",
			  "USBOTG_PWREN_H",
			  "AP_WARM_RESET_H",
			  "nFAULT2",
			  "I2C0_SDA_PMIC",

			  "I2C0_SCL_PMIC",
			  "SUSPEND_L",
			  "USB_INT";
};

&gpio2 {
	gpio-line-names = "CONFIG0",
			  "CONFIG1",
			  "CONFIG2",
			  "",
			  "",
			  "",
			  "",
			  "CONFIG3",

			  "",
			  "EMMC_RST_L",
			  "",
			  "",
			  "BL_PWR_EN",
			  "AVDD_1V8_DISP_EN";
};

&gpio3 {
	gpio-line-names = "FLASH0_D0",
			  "FLASH0_D1",
			  "FLASH0_D2",
			  "FLASH0_D3",
			  "FLASH0_D4",
			  "FLASH0_D5",
			  "FLASH0_D6",
			  "FLASH0_D7",

			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "FLASH0_CS2/EMMC_CMD",
			  "",
			  "FLASH0_DQS/EMMC_CLKO";
};

&gpio4 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "UART0_RXD",
			  "UART0_TXD",
			  "UART0_CTS",
			  "UART0_RTS",
			  "SDIO0_D0",
			  "SDIO0_D1",
			  "SDIO0_D2",
			  "SDIO0_D3",

			  "SDIO0_CMD",
			  "SDIO0_CLK",
			  "BT_DEV_WAKE",
			  "",
			  "WIFI_ENABLE_H",
			  "BT_ENABLE_L",
			  "WIFI_HOST_WAKE",
			  "BT_HOST_WAKE";
};

&gpio5 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "",
			  "",
			  "",
			  "",
			  "SPI0_CLK",
			  "SPI0_CS0",
			  "SPI0_TXD",
			  "SPI0_RXD",

			  "",
			  "",
			  "",
			  "VCC50_HDMI_EN";
};

&gpio6 {
	gpio-line-names = "I2S0_SCLK",
			  "I2S0_LRCK_RX",
			  "I2S0_LRCK_TX",
			  "I2S0_SDI",
			  "I2S0_SDO0",
			  "HP_DET_H",
			  "",
			  "INT_CODEC",

			  "I2S0_CLK",
			  "I2C2_SDA",
			  "I2C2_SCL",
			  "MICDET",
			  "",
			  "",
			  "",
			  "",

			  "SDMMC_D0",
			  "SDMMC_D1",
			  "SDMMC_D2",
			  "SDMMC_D3",
			  "SDMMC_CLK",
			  "SDMMC_CMD";
};

&gpio7 {
	gpio-line-names = "LCDC_BL",
			  "PWM_LOG",
			  "BL_EN",
			  "TRACKPAD_INT",
			  "TPM_INT_H",
			  "SDMMC_DET_L",
			  /*
			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
			   * it FW_WP_AP.
			   */
			  "AP_FLASH_WP_L",
			  "EC_INT",

			  "CPU_NMI",
			  "DVSOK",
			  "",
			  "EDP_HPD",
			  "DVS1",
			  "nFAULT1",
			  "LCD_EN",
			  "DVS2",

			  "VCC5V_GOOD_H",
			  "I2C4_SDA_TP",
			  "I2C4_SCL_TP",
			  "I2C5_SDA_HDMI",
			  "I2C5_SCL_HDMI",
			  "5V_DRV",
			  "UART2_RXD",
			  "UART2_TXD";
};

&gpio8 {
	gpio-line-names = "RAM_ID0",
			  "RAM_ID1",
			  "RAM_ID2",
			  "RAM_ID3",
			  "I2C1_SDA_TPM",
			  "I2C1_SCL_TPM",
			  "SPI2_CLK",
			  "SPI2_CS0",

			  "SPI2_RXD",
			  "SPI2_TXD";
};

&pinctrl {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <
		/* Common for sleep and wake, but no owners */
		&ddr0_retention
		&ddrio_pwroff
		&global_pwroff

		/* Wake only */
		&suspend_l_wake
		&bt_dev_wake_awake
	>;
	pinctrl-1 = <
		/* Common for sleep and wake, but no owners */
		&ddr0_retention
		&ddrio_pwroff
		&global_pwroff

		/* Sleep only */
		&suspend_l_sleep
		&bt_dev_wake_sleep
	>;

	buck-5v {
		drv_5v: drv-5v {
			rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	hdmi {
		vcc50_hdmi_en: vcc50-hdmi-en {
			rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	pmic {
		dvs_1: dvs-1 {
			rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
		};

		dvs_2: dvs-2 {
			rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
		};
	};
};

&i2c4 {
	status = "okay";

	/*
	 * Trackpad pin control is shared between Elan and Synaptics devices
	 * so we have to pull it up to the bus level.
	 */
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer &trackpad_int>;

	trackpad@15 {
		/*
		 * Remove the inherited pinctrl settings to avoid clashing
		 * with bus-wide ones.
		 */
		/delete-property/pinctrl-names;
		/delete-property/pinctrl-0;
	};

	trackpad@2c {
		compatible = "hid-over-i2c";
		interrupt-parent = <&gpio7>;
		interrupts = <RK_PA3 IRQ_TYPE_EDGE_FALLING>;
		reg = <0x2c>;
		hid-descr-addr = <0x0020>;
		vcc-supply = <&vcc33_io>;
		wakeup-source;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Google Veyron Mickey Rev 0 board device tree source
 *
 * Copyright 2015 Google, Inc
 */

/dts-v1/;
#include "rk3288-veyron.dtsi"
#include "rk3288-veyron-broadcom-bluetooth.dtsi"

/ {
	model = "Google Mickey";
	compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
		     "google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
		     "google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
		     "google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
		     "google,veyron-mickey-rev0", "google,veyron-mickey",
		     "google,veyron", "rockchip,rk3288";

	vcc_5v: vcc-5v {
		vin-supply = <&vcc33_sys>;
	};

	vcc33_io: vcc33_io {
		compatible = "regulator-fixed";
		regulator-name = "vcc33_io";
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <&vcc33_sys>;
	};

	sound {
		compatible = "rockchip,rockchip-audio-max98090";
		rockchip,model = "VEYRON-HDMI";
		rockchip,hdmi-codec = <&hdmi>;
		rockchip,i2s-controller = <&i2s>;
	};
};

&cpu_thermal {
	/delete-node/ trips;
	/delete-node/ cooling-maps;

	trips {
		cpu_alert_almost_warm: cpu_alert_almost_warm {
			temperature = <63000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "passive";
		};
		cpu_alert_warm: cpu_alert_warm {
			temperature = <65000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "passive";
		};
		cpu_alert_almost_hot: cpu_alert_almost_hot {
			temperature = <80000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "passive";
		};
		cpu_alert_hot: cpu_alert_hot {
			temperature = <82000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "passive";
		};
		cpu_alert_hotter: cpu_alert_hotter {
			temperature = <84000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "passive";
		};
		cpu_alert_very_hot: cpu_alert_very_hot {
			temperature = <85000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "passive";
		};
		cpu_crit: cpu_crit {
			temperature = <90000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "critical";
		};
	};

	cooling-maps {
		/*
		 * After 1st level, throttle the CPU down to as low as 1.4 GHz
		 * and don't let the GPU go faster than 400 MHz.
		 */
		cpu_warm_limit_cpu {
			trip = <&cpu_alert_warm>;
			cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>,
					 <&cpu1 THERMAL_NO_LIMIT 4>,
					 <&cpu2 THERMAL_NO_LIMIT 4>,
					 <&cpu3 THERMAL_NO_LIMIT 4>;
		};
		cpu_warm_limit_gpu {
			trip = <&cpu_alert_warm>;
			cooling-device = <&gpu 1 1>;
		};

		/*
		 * Add some discrete steps to help throttling system deal
		 * with the fact that there are two passive cooling devices:
		 * the CPU and the GPU.
		 *
		 * - 1.2 GHz - 1.0 GHz (almost hot)
		 * - 800 MHz           (hot)
		 * - 800 MHz - 696 MHz (hotter)
		 * - 696 MHz - min     (very hot)
		 *
		 * Note:
		 * - 800 MHz appears to be a "sweet spot" for me.  I can run
		 *   some pretty serious workload here and be happy.
		 * - After 696 MHz we stop lowering voltage, so throttling
		 *   past there is less effective.
		 */
		cpu_almost_hot_limit_cpu {
			trip = <&cpu_alert_almost_hot>;
			cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>,
					 <&cpu3 5 6>;
		};
		cpu_hot_limit_cpu {
			trip = <&cpu_alert_hot>;
			cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>,
					 <&cpu3 7 7>;
		};
		cpu_hotter_limit_cpu {
			trip = <&cpu_alert_hotter>;
			cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>,
					 <&cpu3 7 8>;
		};
		cpu_very_hot_limit_cpu {
			trip = <&cpu_alert_very_hot>;
			cooling-device = <&cpu0 8 THERMAL_NO_LIMIT>,
					 <&cpu1 8 THERMAL_NO_LIMIT>,
					 <&cpu2 8 THERMAL_NO_LIMIT>,
					 <&cpu3 8 THERMAL_NO_LIMIT>;
		};

		/* At very hot, don't let GPU go over 300 MHz */
		cpu_very_hot_limit_gpu {
			trip = <&cpu_alert_very_hot>;
			cooling-device = <&gpu 2 2>;
		};
	};
};

&gpu_thermal {
	/delete-node/ trips;
	/delete-node/ cooling-maps;

	trips {
		gpu_alert_warmish: gpu_alert_warmish {
			temperature = <60000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "passive";
		};
		gpu_alert_warm: gpu_alert_warm {
			temperature = <65000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "passive";
		};
		gpu_alert_hotter: gpu_alert_hotter {
			temperature = <84000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "passive";
		};
		gpu_alert_very_very_hot: gpu_alert_very_very_hot {
			temperature = <86000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "passive";
		};
		gpu_crit: gpu_crit {
			temperature = <90000>; /* millicelsius */
			hysteresis = <2000>; /* millicelsius */
			type = "critical";
		};
	};

	cooling-maps {
		/* After 1st level throttle the GPU down to as low as 400 MHz */
		gpu_warmish_limit_gpu {
			trip = <&gpu_alert_warmish>;
			cooling-device = <&gpu THERMAL_NO_LIMIT 1>;
		};

		/*
		 * Slightly after we throttle the GPU, we'll also make sure that
		 * the CPU can't go faster than 1.4 GHz.  Note that we won't
		 * throttle the CPU lower than 1.4 GHz due to GPU heat--we'll
		 * let the CPU do the rest itself.
		 */
		gpu_warm_limit_cpu {
			trip = <&gpu_alert_warm>;
			cooling-device = <&cpu0 4 4>,
					 <&cpu1 4 4>,
					 <&cpu2 4 4>,
					 <&cpu3 4 4>;
		};

		/* When hot, GPU goes down to 300 MHz */
		gpu_hotter_limit_gpu {
			trip = <&gpu_alert_hotter>;
			cooling-device = <&gpu 2 2>;
		};

		/* When really hot, don't let GPU go _above_ 300 MHz */
		gpu_very_very_hot_limit_gpu {
			trip = <&gpu_alert_very_very_hot>;
			cooling-device = <&gpu 2 THERMAL_NO_LIMIT>;
		};
	};
};

&i2c2 {
	status = "disabled";
};

&i2c4 {
	status = "disabled";
};

&i2s {
	status = "okay";
};

&rk808 {
	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
	dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
		    <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;

	/delete-property/ vcc6-supply;
	/delete-property/ vcc12-supply;

	vcc11-supply = <&vcc33_sys>;

	regulators {
		/* vcc33_io is sourced directly from vcc33_sys */
		/delete-node/ LDO_REG1;
		/delete-node/ LDO_REG7;

		/* This is not a pwren anymore, but the real power supply */
		vdd10_lcd: LDO_REG7 {
			regulator-always-on;
			regulator-boot-on;
			regulator-min-microvolt = <1000000>;
			regulator-max-microvolt = <1000000>;
			regulator-name = "vdd10_lcd";
			regulator-suspend-mem-disabled;
		};

		vcc18_lcd: LDO_REG8 {
			regulator-always-on;
			regulator-boot-on;
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-name = "vcc18_lcd";
			regulator-suspend-mem-disabled;
		};
	};
};

&gpio0 {
	gpio-line-names = "PMIC_SLEEP_AP",
			  "",
			  "",
			  "",
			  "PMIC_INT_L",
			  "POWER_BUTTON_L",
			  "",
			  "",

			  "",
			  /*
			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
			   * it REC_MODE_L.
			   */
			  "RECOVERY_SW_L",
			  "OT_RESET",
			  "",
			  "",
			  "AP_WARM_RESET_H",
			  "",
			  "I2C0_SDA_PMIC",

			  "I2C0_SCL_PMIC",
			  "",
			  "nFALUT";
};

&gpio2 {
	gpio-line-names = "CONFIG0",
			  "CONFIG1",
			  "CONFIG2",
			  "",
			  "",
			  "",
			  "",
			  "CONFIG3",

			  "",
			  "EMMC_RST_L";
};

&gpio3 {
	gpio-line-names = "FLASH0_D0",
			  "FLASH0_D1",
			  "FLASH0_D2",
			  "FLASH0_D3",
			  "FLASH0_D4",
			  "FLASH0_D5",
			  "FLASH0_D6",
			  "FLASH0_D7",

			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "FLASH0_CS2/EMMC_CMD",
			  "",
			  "FLASH0_DQS/EMMC_CLKO";
};

&gpio4 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  "UART0_RXD",
			  "UART0_TXD",
			  "UART0_CTS_L",
			  "UART0_RTS_L",
			  "SDIO0_D0",
			  "SDIO0_D1",
			  "SDIO0_D2",
			  "SDIO0_D3",

			  "SDIO0_CMD",
			  "SDIO0_CLK",
			  "BT_DEV_WAKE",
			  "",
			  "WIFI_ENABLE_H",
			  "BT_ENABLE_L",
			  "WIFI_HOST_WAKE",
			  "BT_HOST_WAKE";
};

&gpio7 {
	gpio-line-names = "",
			  "PWM_LOG",
			  "",
			  "",
			  "TPM_INT_H",
			  "SDMMC_DET_L",
			  /*
			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
			   * it FW_WP_AP.
			   */
			  "AP_FLASH_WP_L",
			  "",

			  "CPU_NMI",
			  "DVSOK",
			  "HDMI_WAKE",
			  "POWER_HDMI_ON",
			  "DVS1",
			  "",
			  "",
			  "DVS2",

			  "HDMI_CEC",
			  "",
			  "",
			  "I2C5_SDA_HDMI",
			  "I2C5_SCL_HDMI",
			  "",
			  "UART2_RXD",
			  "UART2_TXD";
};

&gpio8 {
	gpio-line-names = "RAM_ID0",
			  "RAM_ID1",
			  "RAM_ID2",
			  "RAM_ID3",
			  "I2C1_SDA_TPM",
			  "I2C1_SCL_TPM",
			  "SPI2_CLK",
			  "SPI2_CS0",

			  "SPI2_RXD",
			  "SPI2_TXD";
};

&pinctrl {
	pinctrl-names = "default";
	pinctrl-0 = <
		/* Common for sleep and wake, but no owners */
		&ddr0_retention
		&ddrio_pwroff
		&global_pwroff
	>;

	hdmi {
		power_hdmi_on: power-hdmi-on {
			rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	pmic {
		dvs_1: dvs-1 {
			rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
		};

		dvs_2: dvs-2 {
			rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
		};
	};
};

&usb_host0_ehci {
	status = "disabled";
};

&usb_host1 {
	status = "disabled";
};

&vcc50_hdmi {
	enable-active-high;
	gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&power_hdmi_on>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Google Veyron Mighty Rev 1+ board device tree source
 *
 * Copyright 2015 Google, Inc
 */

/dts-v1/;

#include "rk3288-veyron-jaq.dts"

/ {
	model = "Google Mighty";
	compatible = "google,veyron-mighty-rev5", "google,veyron-mighty-rev4",
		     "google,veyron-mighty-rev3", "google,veyron-mighty-rev2",
		     "google,veyron-mighty-rev1", "google,veyron-mighty",
		     "google,veyron", "rockchip,rk3288";
};

&sdmmc {
	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
			&sdmmc_wp_pin &sdmmc_bus4>;
	wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;

	/delete-property/ disable-wp;
};

&pinctrl {
	sdmmc {
		sdmmc_wp_pin: sdmmc-wp-pin {
			rockchip,pins = <7 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};
};