code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gnss/brcm,bcm4751.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM4751 family GNSS Receiver

maintainers:
  - Johan Hovold <johan@kernel.org>
  - Linus Walleij <linus.walleij@linaro.org>

description:
  Broadcom GPS chips can be used over the UART or I2C bus. The UART
  bus requires CTS/RTS support. The number of the capsule is more
  elaborate than the compatibles BCM4751 may be printed
  BCM4751IFBG for example.

allOf:
  - $ref: gnss-common.yaml#

properties:
  compatible:
    enum:
      - brcm,bcm4751
      - brcm,bcm4752
      - brcm,bcm4753

  reg:
    description:
      The I2C Address, not required on UART buses.

  vdd-auxin-supply:
    description:
      Main voltage supply, pin name VDD_AUXIN, typically connected
      directly to a battery such as LiIon 3.8V battery or a 2.6V supply.

  vddio-supply:
    description:
      IO voltage supply, pin name VDDIO, typically 1.8V

  reset-gpios:
    maxItems: 1
    description: An optional active low reset line, should be flagged with
      GPIO_ACTIVE_LOW.

  enable-gpios:
    description: Enable GPIO line, connected to pins named REGPU or NSTANDBY.
      If the line is active low such as NSTANDBY, it should be tagged
      GPIO_ACTIVE_LOW.

required:
  - compatible
  - enable-gpios

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    serial {
        gnss {
            compatible = "brcm,bcm4751";
            vdd-auxin-supply = <&vbat>;
            reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
            enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
            current-speed = <38400>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gnss/gnss-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common Properties for Global Navigation Satellite Systems (GNSS)
  receiver devices

maintainers:
  - Johan Hovold <johan@kernel.org>

description: |
  This document defines device tree properties common to Global Navigation
  Satellite System receivers.

properties:
  $nodename:
    pattern: "^gnss(@.*)?$"

  lna-supply:
    description: A separate regulator supplying power for the Low Noise
      Amplifier (LNA). This is an amplifier connected between the GNSS
      device and the receiver antenna.

  enable-gpios:
    description: A GPIO line that will enable the GNSS receiver when
      asserted. If this line is active low, the GPIO phandle should
      consequently be tagged with the GPIO_ACTIVE_LOW flag so the operating
      system can rely on asserting the line to enable the GNSS device.
    maxItems: 1

  timepulse-gpios:
    description: When a timepulse is provided to the GNSS device using a
      GPIO line, this is used.
    maxItems: 1

  current-speed:
    description: The baudrate in bits per second of the device as it comes
      online, current active speed.
    $ref: /schemas/types.yaml#/definitions/uint32

additionalProperties: true

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    serial {
      gnss {
        compatible = "u-blox,neo-8";
        vcc-supply = <&gnss_reg>;
        timepulse-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
        current-speed = <4800>;
      };
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gnss/mediatek.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek GNSS Receiver

maintainers:
  - Johan Hovold <johan@kernel.org>

description:
  Mediatek chipsets are used in GNSS-receiver modules produced by several
  vendors and can use a UART interface.

allOf:
  - $ref: gnss-common.yaml#

properties:
  compatible:
    const: globaltop,pa6h

  vcc-supply:
    description:
      Main voltage regulator, pin name VCC.

  reset-gpios:
    maxItems: 1
    description: An optional reset line, with names such as RESET or NRESET.
      If the line is active low it should be flagged with GPIO_ACTIVE_LOW.

  timepulse-gpios:
    description: Comes with pin names such as PPS1 or 1PPS.

  gnss-fix-gpios:
    maxItems: 1
    description: GPIO used to determine device position fix state, pin names
      FIX or 3D_FIX.

  vbackup-supply:
    description:
      Regulator providing backup voltage, pin names such as VBAT or VBACKUP.

required:
  - compatible
  - vcc-supply

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    serial {
        gnss {
            compatible = "globaltop,pa6h";
            vcc-supply = <&vcc_3v3>;
            reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gnss/sirfstar.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiRFstar GNSS Receiver

maintainers:
  - Johan Hovold <johan@kernel.org>

description:
  The SiRFstar GNSS receivers have incarnated over the years in different
  chips, starting from the SiRFstarIII which was a chip that was introduced in
  2004 and used in a lot of dedicated GPS devices. In 2009 SiRF was acquired
  by CSR (Cambridge Silicon Radio) and in 2012 the CSR GPS business was
  acquired by Samsung, while some products remained with CSR. In 2014 CSR
  was acquired by Qualcomm who still sell some of the SiRF products.

  SiRF chips can be used over UART, I2C or SPI buses.

allOf:
  - $ref: gnss-common.yaml#

properties:
  compatible:
    enum:
      - csr,gsd4t
      - csr,csrg05ta03-icje-r
      - fastrax,uc430
      - linx,r4
      - wi2wi,w2sg0004
      - wi2wi,w2sg0008i
      - wi2wi,w2sg0084i

  reg:
    description:
      The I2C Address, SPI chip select address. Not required on UART buses.

  vcc-supply:
    description:
      Main voltage regulator, pin names such as 3V3_IN, VCC, VDD.

  reset-gpios:
    maxItems: 1
    description: An optional active low reset line, should be flagged with
      GPIO_ACTIVE_LOW.

  sirf,onoff-gpios:
    maxItems: 1
    description: GPIO used to power on and off device, pin name ON_OFF.

  sirf,wakeup-gpios:
    maxItems: 1
    description: GPIO used to determine device power state, pin names such
      as RFPWRUP, WAKEUP.

required:
  - compatible
  - vcc-supply

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    serial {
        gnss {
            compatible = "wi2wi,w2sg0084i";
            vcc-supply = <&gnss_vcc_reg>;
            reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
            sirf,onoff-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
            sirf,wakeup-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
            current-speed = <38400>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gnss/u-blox,neo-6m.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: U-blox GNSS Receiver

allOf:
  - $ref: gnss-common.yaml#

maintainers:
  - Johan Hovold <johan@kernel.org>

description: >
  The U-blox GNSS receivers can use UART, DDC (I2C), SPI and USB interfaces.

properties:
  compatible:
    enum:
      - u-blox,neo-6m
      - u-blox,neo-8
      - u-blox,neo-m8

  reg:
    description: >
      The DDC Slave Address, SPI chip select address, the number of the USB hub
      port or the USB host-controller port to which this device is attached,
      depending on the bus used. Required for the DDC, SPI or USB busses.

  vcc-supply:
    description: >
      Main voltage regulator

  u-blox,extint-gpios:
    maxItems: 1
    description: >
      GPIO connected to the "external interrupt" input pin

  v-bckp-supply:
    description: >
      Backup voltage regulator

required:
  - compatible
  - vcc-supply

unevaluatedProperties: false

examples:
  - |
    serial {
        gnss {
            compatible = "u-blox,neo-8";
            v-bckp-supply = <&gnss_v_bckp_reg>;
            vcc-supply = <&gnss_vcc_reg>;
        };
    };


code:
Android Goldfish Audio

Android goldfish audio device generated by android emulator.

Required properties:

- compatible : should contain "google,goldfish-audio" to match emulator
- reg        : <registers mapping>
- interrupts : <interrupt mapping>

Example:

	goldfish_audio@9030000 {
		compatible = "google,goldfish-audio";
		reg = <0x9030000 0x100>;
		interrupts = <0x4>;
	};


code:
Android Goldfish Battery

Android goldfish battery device generated by android emulator.

Required properties:

- compatible : should contain "google,goldfish-battery" to match emulator
- reg        : <registers mapping>
- interrupts : <interrupt mapping>

Example:

	goldfish_battery@9020000 {
		compatible = "google,goldfish-battery";
		reg = <0x9020000 0x1000>;
		interrupts = <0x3>;
	};


code:
Android Goldfish Events Keypad

Android goldfish events keypad device generated by android emulator.

Required properties:

- compatible : should contain "google,goldfish-events-keypad" to match emulator
- reg        : <registers mapping>
- interrupts : <interrupt mapping>

Example:

	goldfish-events@9040000 {
		compatible = "google,goldfish-events-keypad";
		reg = <0x9040000 0x1000>;
		interrupts = <0x5>;
	};


code:
Android Goldfish QEMU Pipe

Andorid pipe virtual device generated by android emulator.

Required properties:

- compatible : should contain "google,android-pipe" to match emulator
- reg        : <registers mapping>
- interrupts : <interrupt mapping>

Example:

	android_pipe@a010000 {
		compatible = "google,android-pipe";
		reg = <ff018000 0x2000>;
		interrupts = <0x12>;
	};


code:
Android Goldfish TTY

Android goldfish tty device generated by android emulator.

Required properties:

- compatible : should contain "google,goldfish-tty" to match emulator
- reg        : <registers mapping>
- interrupts : <interrupt mapping>

Example:

	goldfish_tty@1f004000 {
		compatible = "google,goldfish-tty";
		reg = <0x1f004000 0x1000>;
		interrupts = <0xc>;
	};


code:
GPIO controllers on MPC8xxx SoCs

This is for the non-QE/CPM/GUTs GPIO controllers as found on
8349, 8572, 8610 and compatible.

Every GPIO controller node must have #gpio-cells property defined,
this information will be used to translate gpio-specifiers.
See bindings/gpio/gpio.txt for details of how to specify GPIO
information for devices.

The GPIO module usually is connected to the SoC's internal interrupt
controller, see bindings/interrupt-controller/interrupts.txt (the
interrupt client nodes section) for details how to specify this GPIO
module's interrupt.

The GPIO module may serve as another interrupt controller (cascaded to
the SoC's internal interrupt controller).  See the interrupt controller
nodes section in bindings/interrupt-controller/interrupts.txt for
details.

Required properties:
- compatible:		"fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
			for 83xx, "fsl,mpc8572-gpio" for 85xx, or
			"fsl,mpc8610-gpio" for 86xx.
- #gpio-cells:		Should be two. The first cell is the pin number
			and the second cell is used to specify optional
			parameters (currently unused).
- interrupts:		Interrupt mapping for GPIO IRQ.
- gpio-controller:	Marks the port as GPIO controller.

Optional properties:
- interrupt-controller:	Empty boolean property which marks the GPIO
			module as an IRQ controller.
- #interrupt-cells:	Should be two.  Defines the number of integer
			cells required to specify an interrupt within
			this interrupt controller.  The first cell
			defines the pin number, the second cell
			defines additional flags (trigger type,
			trigger polarity).  Note that the available
			set of trigger conditions supported by the
			GPIO module depends on the actual SoC.

Example of gpio-controller nodes for a MPC8347 SoC:

	gpio1: gpio-controller@c00 {
		#gpio-cells = <2>;
		compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
		reg = <0xc00 0x100>;
		interrupt-parent = <&ipic>;
		interrupts = <74 0x8>;
		gpio-controller;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	gpio2: gpio-controller@d00 {
		#gpio-cells = <2>;
		compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
		reg = <0xd00 0x100>;
		interrupt-parent = <&ipic>;
		interrupts = <75 0x8>;
		gpio-controller;
	};

Example of a peripheral using the GPIO module as an IRQ controller:

	funkyfpga@0 {
		compatible = "funky-fpga";
		...
		interrupt-parent = <&gpio1>;
		interrupts = <4 3>;
	};


code:
* Abilis TB10x GPIO controller

Required Properties:
- compatible: Should be "abilis,tb10x-gpio"
- reg: Address and length of the register set for the device
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be <2>. The first cell is the pin number and the
  second cell is used to specify optional parameters:
   - bit 0 specifies polarity (0 for normal, 1 for inverted).
- abilis,ngpio: the number of GPIO pins this driver controls.

Optional Properties:
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be <1>. Interrupts are triggered on both edges.
- interrupts: Defines the interrupt line connecting this GPIO controller to
  its parent interrupt controller.

GPIO ranges are specified as described in
Documentation/devicetree/bindings/gpio/gpio.txt

Example:

	gpioa: gpio@ff140000 {
		compatible = "abilis,tb10x-gpio";
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&tb10x_ictl>;
		interrupts = <27 2>;
		reg = <0xFF140000 0x1000>;
		gpio-controller;
		#gpio-cells = <2>;
		abilis,ngpio = <3>;
		gpio-ranges = <&iomux 0 0 0>;
		gpio-ranges-group-names = "gpioa_pins";
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/airoha,en7523-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Airoha EN7523 GPIO controller

maintainers:
  - John Crispin <john@phrozen.org>

description: |
  Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
  GPIOs.

properties:
  $nodename:
    pattern: "^gpio@[0-9a-f]+$"

  compatible:
    items:
      - const: airoha,en7523-gpio

  reg:
    description: |
      The first tuple points to the input register.
      The second and third tuple point to the direction registers
      The fourth tuple points to the output register
    maxItems: 4

  "#gpio-cells":
    const: 2

  gpio-controller: true

required:
  - compatible
  - reg
  - "#gpio-cells"
  - gpio-controller

additionalProperties: false

examples:
  - |
    gpio0: gpio@1fbf0200 {
        compatible = "airoha,en7523-gpio";
        reg = <0x1fbf0204 0x4>,
              <0x1fbf0200 0x4>,
              <0x1fbf0220 0x4>,
              <0x1fbf0214 0x4>;
        gpio-controller;
        #gpio-cells = <2>;
    };

    gpio1: gpio@1fbf0270 {
        compatible = "airoha,en7523-gpio";
        reg = <0x1fbf0270 0x4>,
              <0x1fbf0260 0x4>,
              <0x1fbf0264 0x4>,
              <0x1fbf0278 0x4>;
        gpio-controller;
        #gpio-cells = <2>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Aspeed SGPIO controller

maintainers:
  - Andrew Jeffery <andrew@aj.id.au>

description:
  This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
  AST2600 have two sgpio master one with 128 pins another one with 80 pins,
  AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
  GPIO pins can be programmed to support the following options
  - Support interrupt option for each input port and various interrupt
    sensitivity option (level-high, level-low, edge-high, edge-low)
  - Support reset tolerance option for each output port
  - Directly connected to APB bus and its shift clock is from APB bus clock
    divided by a programmable value.
  - Co-work with external signal-chained TTL components (74LV165/74LV595)

properties:
  compatible:
    enum:
      - aspeed,ast2400-sgpio
      - aspeed,ast2500-sgpio
      - aspeed,ast2600-sgpiom

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2

  interrupts:
    maxItems: 1

  interrupt-controller: true

  clocks:
    maxItems: 1

  ngpios: true

  bus-frequency: true

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - interrupts
  - interrupt-controller
  - ngpios
  - clocks
  - bus-frequency

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/aspeed-clock.h>
    sgpio: sgpio@1e780200 {
        #gpio-cells = <2>;
        compatible = "aspeed,ast2500-sgpio";
        gpio-controller;
        interrupts = <40>;
        reg = <0x1e780200 0x0100>;
        clocks = <&syscon ASPEED_CLK_APB>;
        interrupt-controller;
        ngpios = <80>;
        bus-frequency = <12000000>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM6345 GPIO controller

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>
  - Jonas Gorski <jonas.gorski@gmail.com>

description: |+
  Bindings for Broadcom's BCM63xx memory-mapped GPIO controllers.

  These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345
  are the only ones which don't need a pinctrl driver.

  BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
  and/or written, and the direction changed from input to output.
  BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
  and/or written, and the direction changed from input to output.
  BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data
  and dirout registers, where GPIO state can be read and/or written, and the
  direction changed from input to output.

properties:
  compatible:
    enum:
      - brcm,bcm6318-gpio
      - brcm,bcm6328-gpio
      - brcm,bcm6345-gpio
      - brcm,bcm6358-gpio
      - brcm,bcm6362-gpio
      - brcm,bcm6368-gpio
      - brcm,bcm63268-gpio

  gpio-controller: true

  "#gpio-cells":
    const: 2

  gpio-ranges:
    maxItems: 1

  native-endian: true

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: dirout
      - const: dat

required:
  - compatible
  - reg
  - reg-names
  - gpio-controller
  - '#gpio-cells'

additionalProperties: false

examples:
  - |
    gpio@fffe0406 {
      compatible = "brcm,bcm6345-gpio";
      reg-names = "dirout", "dat";
      reg = <0xfffe0406 2>, <0xfffe040a 2>;
      native-endian;

      gpio-controller;
      #gpio-cells = <2>;
    };

  - |
    gpio@0 {
      compatible = "brcm,bcm63268-gpio";
      reg-names = "dirout", "dat";
      reg = <0x0 0x8>, <0x8 0x8>;

      gpio-controller;
      gpio-ranges = <&pinctrl 0 0 52>;
      #gpio-cells = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom STB "UPG GIO" GPIO controller

description: >
  The controller's registers are organized as sets of eight 32-bit
  registers with each set controlling a bank of up to 32 pins.  A single
  interrupt is shared for all of the banks handled by the controller.

maintainers:
  - Doug Berger <opendmb@gmail.com>
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  compatible:
    items:
      - enum:
          - brcm,bcm7445-gpio
      - const: brcm,brcmstb-gpio

  reg:
    maxItems: 1
    description: >
      Define the base and range of the I/O address space containing
      the brcmstb GPIO controller registers

  "#gpio-cells":
    const: 2
    description: >
      The first cell is the pin number (within the controller's
      pin space), and the second is used for the following:
      bit[0]: polarity (0 for active-high, 1 for active-low)

  gpio-controller: true

  brcm,gpio-bank-widths:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: >
      Number of GPIO lines for each bank.  Number of elements must
      correspond to number of banks suggested by the 'reg' property.

  interrupts:
    maxItems: 1
    description: >
      The interrupt shared by all GPIO lines for this controller.

  "#interrupt-cells":
    const: 2
    description: |
      The first cell is the GPIO number, the second should specify
      flags.  The following subset of flags is supported:
      - bits[3:0] trigger type and level flags
        1 = low-to-high edge triggered
        2 = high-to-low edge triggered
        4 = active high level-sensitive
        8 = active low level-sensitive
      Valid combinations are 1, 2, 3, 4, 8.

  interrupt-controller: true

  wakeup-source:
    type: boolean
    description: >
      GPIOs for this controller can be used as a wakeup source

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"
  - "brcm,gpio-bank-widths"

additionalProperties: false

examples:
  - |
    upg_gio: gpio@f040a700 {
        #gpio-cells = <2>;
        #interrupt-cells = <2>;
        compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
        gpio-controller;
        interrupt-controller;
        reg = <0xf040a700 0x80>;
        interrupt-parent = <&irq0_intc>;
        interrupts = <0x6>;
        brcm,gpio-bank-widths = <32 32 32 24>;
    };

    upg_gio_aon: gpio@f04172c0 {
        #gpio-cells = <2>;
        #interrupt-cells = <2>;
        compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
        gpio-controller;
        interrupt-controller;
        reg = <0xf04172c0 0x40>;
        interrupt-parent = <&irq0_aon_intc>;
        interrupts = <0x6>;
        wakeup-source;
        brcm,gpio-bank-widths = <18 4>;
    };


code:
Broadcom Kona Family GPIO
=========================

This GPIO driver is used in the following Broadcom SoCs:
  BCM11130, BCM11140, BCM11351, BCM28145, BCM28155

The Broadcom GPIO Controller IP can be configured prior to synthesis to
support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
GPIO controller only supports edge, not level, triggering of interrupts.

Required properties
-------------------

- compatible: "brcm,bcm11351-gpio", "brcm,kona-gpio"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller. There is one GPIO
  interrupt per GPIO bank. The number of interrupts listed depends on the
  number of GPIO banks on the SoC. The interrupts must be ordered by bank,
  starting with bank 0. There is always a 1:1 mapping between banks and
  IRQs.
- #gpio-cells: Should be <2>. The first cell is the pin number, the second
  cell is used to specify optional parameters:
  - bit 0 specifies polarity (0 for normal, 1 for inverted)
  See also "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
- #interrupt-cells: Should be <2>. The first cell is the GPIO number. The
  second cell is used to specify flags. The following subset of flags is
  supported:
  - trigger type (bits[1:0]):
      1 = low-to-high edge triggered.
      2 = high-to-low edge triggered.
      3 = low-to-high or high-to-low edge triggered
      Valid values are 1, 2, 3
  See also .../devicetree/bindings/interrupt-controller/interrupts.txt.
- gpio-controller: Marks the device node as a GPIO controller.
- interrupt-controller: Marks the device node as an interrupt controller.

Example:
	gpio: gpio@35003000 {
		compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
		reg = <0x35003000 0x800>;
		interrupts =
		       <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
			GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
			GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
			GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
			GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
			GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		#interrupt-cells = <2>;
		gpio-controller;
		interrupt-controller;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/brcm,xgs-iproc-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom XGS iProc GPIO controller

maintainers:
  - Chris Packham <chris.packham@alliedtelesis.co.nz>

description: |
  This controller is the Chip Common A GPIO present on a number of Broadcom
  switch ASICs with integrated SoCs.

properties:
  compatible:
    const: brcm,iproc-gpio-cca

  reg:
    items:
      - description: the I/O address containing the GPIO controller registers.
      - description: the I/O address containing the Chip Common A interrupt registers.

  gpio-controller: true

  '#gpio-cells':
    const: 2

  ngpios:
    minimum: 0
    maximum: 32

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - "#gpio-cells"
  - gpio-controller

additionalProperties: false

dependencies:
  interrupt-controller: [ interrupts ]

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    gpio@18000060 {
        compatible = "brcm,iproc-gpio-cca";
        #gpio-cells = <2>;
        reg = <0x18000060 0x50>,
              <0x18000000 0x50>;
        ngpios = <12>;
        gpio-controller;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
    };

...


code:
* General Purpose Input Output (GPIO) bus.

Properties:
- compatible: "cavium,octeon-3860-gpio"

  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.

- reg: The base address of the GPIO unit's register bank.

- gpio-controller: This is a GPIO controller.

- #gpio-cells: Must be <2>.  The first cell is the GPIO pin.

- interrupt-controller: The GPIO controller is also an interrupt
  controller, many of its pins may be configured as an interrupt
  source.

- #interrupt-cells: Must be <2>.  The first cell is the GPIO pin
   connected to the interrupt source.  The second cell is the interrupt
   triggering protocol and may have one of four values:
   1 - edge triggered on the rising edge.
   2 - edge triggered on the falling edge
   4 - level triggered active high.
   8 - level triggered active low.

- interrupts: Interrupt routing for each pin.

Example:

	gpio-controller@1070000000800 {
		#gpio-cells = <2>;
		compatible = "cavium,octeon-3860-gpio";
		reg = <0x10700 0x00000800 0x0 0x100>;
		gpio-controller;
		/* Interrupts are specified by two parts:
		 * 1) GPIO pin number (0..15)
		 * 2) Triggering (1 - edge rising
		 *		  2 - edge falling
		 *		  4 - level active high
		 *		  8 - level active low)
		 */
		interrupt-controller;
		#interrupt-cells = <2>;
		/* The GPIO pin connect to 16 consecutive CUI bits */
		interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
			     <0 20>, <0 21>, <0 22>, <0 23>,
			     <0 24>, <0 25>, <0 26>, <0 27>,
			     <0 28>, <0 29>, <0 30>, <0 31>;
	};


code:
Cadence GPIO controller bindings

Required properties:
- compatible: should be "cdns,gpio-r1p02".
- reg: the register base address and size.
- #gpio-cells: should be 2.
	* first cell is the GPIO number.
	* second cell specifies the GPIO flags, as defined in
		<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
		and GPIO_ACTIVE_LOW flags are supported.
- gpio-controller: marks the device as a GPIO controller.
- clocks: should contain one entry referencing the peripheral clock driving
	the GPIO controller.

Optional properties:
- ngpios: integer number of gpio lines supported by this controller, up to 32.
- interrupts: interrupt specifier for the controllers interrupt.
- interrupt-controller: marks the device as an interrupt controller. When
	defined, interrupts, interrupt-parent and #interrupt-cells
	are required.
- interrupt-cells: should be 2.
	* first cell is the GPIO number you want to use as an IRQ source.
	* second cell specifies the IRQ type, as defined in
		<dt-bindings/interrupt-controller/irq.h>.
		Currently only level sensitive IRQs are supported.

Example:
	gpio0: gpio-controller@fd060000 {
		compatible = "cdns,gpio-r1p02";
		reg =<0xfd060000 0x1000>;

		clocks = <&gpio_clk>;

		interrupt-parent = <&gic>;
		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};


code:
* ARM Cirrus Logic CLPS711X SYSFLG1 MCTRL GPIOs

Required properties:
- compatible: Should contain "cirrus,ep7209-mctrl-gpio".
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be two. The first cell is the pin number and
  the second cell is used to specify the gpio polarity:
    0 = Active high,
    1 = Active low.

Example:
	sysgpio: sysgpio {
		compatible = "cirrus,ep7312-mctrl-gpio",
			     "cirrus,ep7209-mctrl-gpio";
		gpio-controller;
		#gpio-cells = <2>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/delta,tn48m-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Delta Networks TN48M CPLD GPIO controller

maintainers:
  - Robert Marko <robert.marko@sartura.hr>

description: |
  This module is part of the Delta TN48M multi-function device. For more
  details see ../mfd/delta,tn48m-cpld.yaml.

  Delta TN48M has an onboard Lattice CPLD that is used as an GPIO expander.
  It provides 12 pins in total, they are input-only or ouput-only type.

properties:
  compatible:
    enum:
      - delta,tn48m-gpo
      - delta,tn48m-gpi

  reg:
    maxItems: 1

  "#gpio-cells":
    const: 2

  gpio-controller: true

required:
  - compatible
  - reg
  - "#gpio-cells"
  - gpio-controller

additionalProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic 8-bit shift register

maintainers:
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    enum:
      - fairchild,74hc595
      - nxp,74lvc594

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    description:
      The second cell is only used to specify the GPIO polarity.
    const: 2

  registers-number:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Number of daisy-chained shift registers

  enable-gpios:
    description: GPIO connected to the OE (Output Enable) pin.
    maxItems: 1

patternProperties:
  "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
    type: object

    properties:
      gpio-hog: true
      gpios: true
      output-high: true
      output-low: true
      line-name: true

    required:
      - gpio-hog
      - gpios

    additionalProperties: false

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - registers-number

allOf:
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

unevaluatedProperties: false

examples:
  - |
    spi {
            #address-cells = <1>;
            #size-cells = <0>;

            gpio5: gpio5@0 {
                    compatible = "fairchild,74hc595";
                    reg = <0>;
                    gpio-controller;
                    #gpio-cells = <2>;
                    registers-number = <4>;
                    spi-max-frequency = <100000>;
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/faraday,ftgpio010.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Faraday Technology FTGPIO010 GPIO Controller

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

properties:
  compatible:
    oneOf:
      - items:
          - const: cortina,gemini-gpio
          - const: faraday,ftgpio010
      - items:
          - const: moxa,moxart-gpio
          - const: faraday,ftgpio010
      - const: faraday,ftgpio010

  reg:
    maxItems: 1

  resets:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1
    description: Should contain the interrupt line for the GPIO block

  gpio-controller: true
  "#gpio-cells":
    const: 2

  interrupt-controller: true
  "#interrupt-cells":
    const: 2

required:
  - compatible
  - reg
  - interrupts
  - "#gpio-cells"
  - interrupt-controller
  - "#interrupt-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    gpio@4d000000 {
      compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
      reg = <0x4d000000 0x100>;
      interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
      gpio-controller;
      #gpio-cells = <2>;
      interrupt-controller;
      #interrupt-cells = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/fsl,imx8qxp-sc-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: GPIO driver over IMX SCU firmware API

maintainers:
  - Shenwei Wang <shenwei.wang@nxp.com>

description: |
  This module provides the standard interface to control the
  resource pins in SCU domain on i.MX8 platforms.

properties:
  compatible:
    enum:
      - fsl,imx8qxp-sc-gpio

  "#gpio-cells":
    const: 2

  gpio-controller: true

required:
  - compatible
  - "#gpio-cells"
  - gpio-controller

additionalProperties: false

examples:
  - |
    gpio0: gpio {
        compatible = "fsl,imx8qxp-sc-gpio";
        gpio-controller;
        #gpio-cells = <2>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/fsl-imx-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX/MXC GPIO controller

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx1-gpio
          - fsl,imx21-gpio
          - fsl,imx31-gpio
          - fsl,imx35-gpio
          - fsl,imx7d-gpio
      - items:
          - const: fsl,imx35-gpio
          - const: fsl,imx31-gpio
      - items:
          - enum:
              - fsl,imx50-gpio
              - fsl,imx51-gpio
              - fsl,imx53-gpio
              - fsl,imx6q-gpio
              - fsl,imx6sl-gpio
              - fsl,imx6sll-gpio
              - fsl,imx6sx-gpio
              - fsl,imx6ul-gpio
              - fsl,imx7d-gpio
              - fsl,imx8mm-gpio
              - fsl,imx8mn-gpio
              - fsl,imx8mp-gpio
              - fsl,imx8mq-gpio
              - fsl,imx8qxp-gpio
              - fsl,imxrt1050-gpio
              - fsl,imxrt1170-gpio
          - const: fsl,imx35-gpio

  reg:
    maxItems: 1

  interrupts:
    description: |
      Should be the port interrupt shared by all 32 pins, if one number.
      If two numbers, the first one is the interrupt shared by low 16 pins
      and the second one is for high 16 pins.
    minItems: 1
    maxItems: 2

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  clocks:
    maxItems: 1

  "#gpio-cells":
    const: 2

  gpio-controller: true
  gpio-line-names: true
  gpio-ranges: true

  power-domains:
    maxItems: 1

patternProperties:
  "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
    type: object
    properties:
      gpio-hog: true
      gpios: true
      input: true
      output-high: true
      output-low: true
      line-name: true

    required:
      - gpio-hog
      - gpios

    additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - "#interrupt-cells"
  - "#gpio-cells"
  - gpio-controller

additionalProperties: false

examples:
  - |
    gpio0: gpio@73f84000 {
        compatible = "fsl,imx35-gpio";
        reg = <0x73f84000 0x4000>;
        interrupts = <50 51>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };

...


code:
Fujitsu MB86S7x GPIO Controller
-------------------------------

Required properties:
- compatible: Should be "fujitsu,mb86s70-gpio"
- reg: Base address and length of register space
- clocks: Specify the clock
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be <2>. The first cell is the pin number and the
  second cell is used to specify optional parameters:
   - bit 0 specifies polarity (0 for normal, 1 for inverted).

Examples:
	gpio0: gpio@31000000 {
		compatible = "fujitsu,mb86s70-gpio";
		reg = <0 0x31000000 0x10000>;
		gpio-controller;
		#gpio-cells = <2>;
		clocks = <&clk 0 2 1>;
	};


code:
Gateworks PLD GPIO controller bindings

The GPIO controller should be a child node on an I2C bus,
see: i2c/i2c.txt for details.

Required properties:
- compatible: Should be "gateworks,pld-gpio"
- reg: I2C slave address
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be <2>. The first cell is the gpio number and
  the second cell is used to specify optional parameters.

Example:

pld@56 {
	compatible = "gateworks,pld-gpio";
	reg = <0x56>;
	gpio-controller;
	#gpio-cells = <2>;
};


code:
* 74XX MMIO GPIO driver

Required properties:
- compatible: Should contain one of the following:
   "ti,741g125": for 741G125 (1-bit Input),
   "ti,741g174": for 741G74 (1-bit Output),
   "ti,742g125": for 742G125 (2-bit Input),
   "ti,7474"   : for 7474 (2-bit Output),
   "ti,74125"  : for 74125 (4-bit Input),
   "ti,74175"  : for 74175 (4-bit Output),
   "ti,74365"  : for 74365 (6-bit Input),
   "ti,74174"  : for 74174 (6-bit Output),
   "ti,74244"  : for 74244 (8-bit Input),
   "ti,74273"  : for 74273 (8-bit Output),
   "ti,741624" : for 741624 (16-bit Input),
   "ti,7416374": for 7416374 (16-bit Output).
- reg: Physical base address and length where IC resides.
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be two. The first cell is the pin number and
   the second cell is used to specify the GPIO polarity:
    0 = Active High,
    1 = Active Low.

Example:
	ctrl: gpio@30008004 {
		compatible = "ti,74174";
		reg = <0x30008004 0x1>;
		gpio-controller;
		#gpio-cells = <2>;
	};


code:
Avionic Design N-bit GPIO expander bindings

Required properties:
- compatible: should be "ad,gpio-adnp"
- reg: The I2C slave address for this device.
- interrupts: Interrupt specifier for the controllers interrupt.
- #gpio-cells: Should be 2. The first cell is the GPIO number and the
  second cell is used to specify optional parameters:
  - bit 0: polarity (0: normal, 1: inverted)
- gpio-controller: Marks the device as a GPIO controller
- nr-gpios: The number of pins supported by the controller.

The GPIO expander can optionally be used as an interrupt controller, in
which case it uses the default two cell specifier as described in
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.

Example:

	gpioext: gpio-controller@41 {
		compatible = "ad,gpio-adnp";
		reg = <0x41>;

		interrupt-parent = <&gpio>;
		interrupts = <160 1>;

		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;

		nr-gpios = <64>;
	};


code:
Altera GPIO controller bindings

Required properties:
- compatible:
  - "altr,pio-1.0"
- reg: Physical base address and length of the controller's registers.
- #gpio-cells : Should be 2
  - The first cell is the gpio offset number.
  - The second cell is reserved and is currently unused.
- gpio-controller : Marks the device node as a GPIO controller.
- interrupt-controller: Mark the device node as an interrupt controller
- #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.
  - The first cell is the GPIO offset number within the GPIO controller.
  - The second cell is the interrupt trigger type and level flags.
- interrupts: Specify the interrupt.
- altr,interrupt-type: Specifies the interrupt trigger type the GPIO
  hardware is synthesized. This field is required if the Altera GPIO controller
  used has IRQ enabled as the interrupt type is not software controlled,
  but hardware synthesized. Required if GPIO is used as an interrupt
  controller. The value is defined in <dt-bindings/interrupt-controller/irq.h>
  Only the following flags are supported:
    IRQ_TYPE_EDGE_RISING
    IRQ_TYPE_EDGE_FALLING
    IRQ_TYPE_EDGE_BOTH
    IRQ_TYPE_LEVEL_HIGH

Optional properties:
- altr,ngpio: Width of the GPIO bank. This defines how many pins the
  GPIO device has. Ranges between 1-32. Optional and defaults to 32 if not
  specified.

Example:

gpio_altr: gpio@ff200000 {
	compatible = "altr,pio-1.0";
	reg = <0xff200000 0x10>;
	interrupts = <0 45 4>;
	altr,ngpio = <32>;
	altr,interrupt-type = <IRQ_TYPE_EDGE_RISING>;
	#gpio-cells = <2>;
	gpio-controller;
	#interrupt-cells = <2>;
	interrupt-controller;
};


code:
Aspeed GPIO controller Device Tree Bindings
-------------------------------------------

Required properties:
- compatible		: Either "aspeed,ast2400-gpio", "aspeed,ast2500-gpio",
					or "aspeed,ast2600-gpio".

- #gpio-cells 		: Should be two
			  - First cell is the GPIO line number
			  - Second cell is used to specify optional
			    parameters (unused)

- reg			: Address and length of the register set for the device
- gpio-controller	: Marks the device node as a GPIO controller.
- interrupts		: Interrupt specifier (see interrupt bindings for
			  details)
- interrupt-controller	: Mark the GPIO controller as an interrupt-controller

Optional properties:

- clocks		: A phandle to the clock to use for debounce timings
- ngpios		: Number of GPIOs controlled by this controller. Should	be set
				  when there are multiple GPIO controllers on a SoC (ast2600).

The gpio and interrupt properties are further described in their respective
bindings documentation:

- Documentation/devicetree/bindings/gpio/gpio.txt
- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt

  Example:
	gpio@1e780000 {
		#gpio-cells = <2>;
		compatible = "aspeed,ast2400-gpio";
		gpio-controller;
		interrupts = <20>;
		reg = <0x1e780000 0x1000>;
		interrupt-controller;
	};


code:
Binding for Qualcomm Atheros AR7xxx/AR9xxx GPIO controller

Required properties:
- compatible: has to be "qca,<soctype>-gpio" and one of the following
  fallbacks:
  - "qca,ar7100-gpio"
  - "qca,ar9340-gpio"
- reg: Base address and size of the controllers memory area
- gpio-controller : Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and the
  second cell is used to specify optional parameters.
- ngpios: Should be set to the number of GPIOs available on the SoC.

Optional properties:
- interrupts: Interrupt specifier for the controllers interrupt.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
		     source, should be 2

Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.

Example:

	gpio@18040000 {
		compatible = "qca,ar9132-gpio", "qca,ar7100-gpio";
		reg = <0x18040000 0x30>;
		interrupts = <2>;

		ngpios = <22>;

		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};


code:
Cirrus Logic CLPS711X GPIO controller

Required properties:
- compatible: Should be "cirrus,ep7209-gpio"
- reg: Physical base GPIO controller registers location and length.
  There should be two registers, first is DATA register, the second
  is DIRECTION.
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be two. The first cell is the pin number and
  the second cell is used to specify the gpio polarity:
    0 = active high
    1 = active low

Note: Each GPIO port should have an alias correctly numbered in "aliases"
node.

Example:

aliases {
	gpio0 = &porta;
};

porta: gpio@80000000 {
	compatible = "cirrus,ep7312-gpio","cirrus,ep7209-gpio";
	reg = <0x80000000 0x1>, <0x80000040 0x1>;
	gpio-controller;
	#gpio-cells = <2>;
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-consumer-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common GPIO lines

maintainers:
  - Bartosz Golaszewski <brgl@bgdev.pl>
  - Linus Walleij <linus.walleij@linaro.org>

description:
  Pay attention to using proper GPIO flag (e.g. GPIO_ACTIVE_LOW) for the GPIOs
  using inverted signal (e.g. RESETN).

select: true

properties:
  enable-gpios:
    maxItems: 1
    description:
      GPIO connected to the enable control pin.

  reset-gpios:
    description:
      GPIO (or GPIOs for power sequence) connected to the device reset pin
      (e.g. RESET or RESETN).

  powerdown-gpios:
    maxItems: 1
    description:
      GPIO connected to the power down pin (hardware power down or power cut,
      e.g. PD or PWDN).

  pwdn-gpios:
    maxItems: 1
    description: Use powerdown-gpios
    deprecated: true

  wakeup-gpios:
    maxItems: 1
    description:
      GPIO connected to the pin waking up the device from suspend or other
      power-saving modes.

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mmc-pwrseq-simple
    then:
      properties:
        reset-gpios:
          minItems: 1
          maxItems: 32
    else:
      properties:
        reset-gpios:
          maxItems: 1

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: GPIO controller for Davinci and keystone devices

maintainers:
  - Keerthy <j-keerthy@ti.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - ti,k2g-gpio
              - ti,am654-gpio
              - ti,j721e-gpio
              - ti,am64-gpio
          - const: ti,keystone-gpio

      - items:
          - enum:
              - ti,dm6441-gpio
              - ti,keystone-gpio

  reg:
    maxItems: 1

  gpio-controller: true

  gpio-ranges: true

  gpio-line-names:
    description: strings describing the names of each gpio line.
    minItems: 1
    maxItems: 144

  "#gpio-cells":
    const: 2
    description:
      first cell is the pin number and second cell is used to specify optional parameters (unused).

  interrupts:
    description:
      The interrupts are specified as per the interrupt parent. Only banked
      or unbanked IRQs are supported at a time. If the interrupts are
      banked then provide list of interrupts corresponding to each bank, else
      provide the list of interrupts for each gpio.
    minItems: 1
    maxItems: 100

  ti,ngpio:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The number of GPIO pins supported consecutively.
    minimum: 1

  ti,davinci-gpio-unbanked:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The number of GPIOs that have an individual interrupt line to processor.
    minimum: 0

  clocks:
    maxItems: 1

  clock-names:
    const: gpio

  interrupt-controller: true

  power-domains:
    maxItems: 1

  "#interrupt-cells":
    const: 2

patternProperties:
  "^(.+-hog(-[0-9]+)?)$":
    type: object

    required:
      - gpio-hog

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"
  - interrupts
  - ti,ngpio
  - ti,davinci-gpio-unbanked
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include<dt-bindings/interrupt-controller/arm-gic.h>

    gpio0: gpio@2603000 {
      compatible = "ti,k2g-gpio", "ti,keystone-gpio";
      reg = <0x02603000 0x100>;
      gpio-controller;
      #gpio-cells = <2>;
      interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
      interrupt-controller;
      #interrupt-cells = <2>;
      ti,ngpio = <144>;
      ti,davinci-gpio-unbanked = <0>;
      clocks = <&k2g_clks 0x001b 0x0>;
      clock-names = "gpio";
    };

  - |
    #include<dt-bindings/interrupt-controller/arm-gic.h>

    gpio1: gpio@260bf00 {
      compatible = "ti,keystone-gpio";
      reg = <0x0260bf00 0x100>;
      gpio-controller;
      #gpio-cells = <2>;
      /* HW Interrupts mapped to GPIO pins */
      interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
                   <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
      clocks = <&clkgpio>;
      clock-names = "gpio";
      ti,ngpio = <32>;
      ti,davinci-gpio-unbanked = <32>;
    };

  - |
    wkup_gpio0: gpio0@42110000 {
      compatible = "ti,am654-gpio", "ti,keystone-gpio";
      reg = <0x42110000 0x100>;
      gpio-controller;
      #gpio-cells = <2>;
      interrupt-parent = <&intr_wkup_gpio>;
      interrupts = <60>, <61>, <62>, <63>;
      interrupt-controller;
      #interrupt-cells = <2>;
      ti,ngpio = <56>;
      ti,davinci-gpio-unbanked = <0>;
      clocks = <&k3_clks 59 0>;
      clock-names = "gpio";
    };


code:
Keystone 2 DSP GPIO controller bindings

HOST OS userland running on ARM can send interrupts to DSP cores using
the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
This is one of the component used by the IPC mechanism used on Keystone SOCs.

For example TCI6638K2K SoC has 8 DSP GPIO controllers:
 - 8 for C66x CorePacx CPUs 0-7

Keystone 2 DSP GPIO controller has specific features:
- each GPIO can be configured only as output pin;
- setting GPIO value to 1 causes IRQ generation on target DSP core;
- reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
  pending.

Required Properties:
- compatible: should be "ti,keystone-dsp-gpio"
- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
  access device state control registers and the offset of device's specific
  registers within device state control registers range.
- gpio-controller: Marks the device node as a gpio controller.
- #gpio-cells: Should be 2.

Please refer to gpio.txt in this directory for details of the common GPIO
bindings used by client devices.

Example:
	dspgpio0: keystone_dsp_gpio@2620240 {
		compatible = "ti,keystone-dsp-gpio";
		ti,syscon-dev = <&devctrl 0x240>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	dsp0: dsp0 {
		compatible = "linux,rproc-user";
		...
		kick-gpio = <&dspgpio0 27>;
	};


code:
Spreadtrum EIC controller bindings

The EIC is the abbreviation of external interrupt controller, which can
be used only in input mode. The Spreadtrum platform has 2 EIC controllers,
one is in digital chip, and another one is in PMIC. The digital chip EIC
controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
module.

The EIC-debounce sub-module provides up to 8 source input signal
connections. A debounce mechanism is used to capture the input signals'
stable status (millisecond resolution) and a single-trigger mechanism
is introduced into this sub-module to enhance the input event detection
reliability. In addition, this sub-module's clock can be shut off
automatically to reduce power dissipation. Moreover the debounce range
is from 1ms to 4s with a step size of 1ms. The input signal will be
ignored if it is asserted for less than 1 ms.

The EIC-latch sub-module is used to latch some special power down signals
and generate interrupts, since the EIC-latch does not depend on the APB
clock to capture signals.

The EIC-async sub-module uses a 32kHz clock to capture the short signals
(microsecond resolution) to generate interrupts by level or edge trigger.

The EIC-sync is similar with GPIO's input function, which is a synchronized
signal input register. It can generate interrupts by level or edge trigger
when detecting input signals.

Required properties:
- compatible: Should be one of the following:
  "sprd,sc9860-eic-debounce",
  "sprd,sc9860-eic-latch",
  "sprd,sc9860-eic-async",
  "sprd,sc9860-eic-sync",
  "sprd,sc2731-eic".
- reg: Define the base and range of the I/O address space containing
  the GPIO controller registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be <2>. The first cell is the gpio number and
  the second cell is used to specify optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be <2>. Specifies the number of cells needed
  to encode interrupt source.
- interrupts: Should be the port interrupt shared by all the gpios.

Example:
	eic_debounce: gpio@40210000 {
		compatible = "sprd,sc9860-eic-debounce";
		reg = <0 0x40210000 0 0x80>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	};

	eic_latch: gpio@40210080 {
		compatible = "sprd,sc9860-eic-latch";
		reg = <0 0x40210080 0 0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	};

	eic_async: gpio@402100a0 {
		compatible = "sprd,sc9860-eic-async";
		reg = <0 0x402100a0 0 0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	};

	eic_sync: gpio@402100c0 {
		compatible = "sprd,sc9860-eic-sync";
		reg = <0 0x402100c0 0 0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	};

	pmic_eic: gpio@300 {
		compatible = "sprd,sc2731-eic";
		reg = <0x300>;
		interrupt-parent = <&sc2731_pmic>;
		interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};


code:
Exportable MPIO interface of Exar UART chips

Required properties of the device:
 - exar,first-pin: first exportable pins (0..15)
 - ngpios: number of exportable pins (1..16)


code:
Aeroflex Gaisler GRGPIO General Purpose I/O cores.

The GRGPIO GPIO core is available in the GRLIB VHDL IP core library.

Note: In the ordinary environment for the GRGPIO core, a Leon SPARC system,
these properties are built from information in the AMBA plug&play.

Required properties:

- name : Should be "GAISLER_GPIO" or "01_01a"

- reg : Address and length of the register set for the device

- interrupts : Interrupt numbers for this device

Optional properties:

- nbits : The number of gpio lines. If not present driver assumes 32 lines.

- irqmap : An array with an index for each gpio line. An index is either a valid
	index into the interrupts property array, or 0xffffffff that indicates
	no irq for that line. Driver provides no interrupt support if not
	present.

For further information look in the documentation for the GLIB IP core library:
http://www.gaisler.com/products/grlib/grip.pdf


code:
TI/National Semiconductor LP3943 GPIO controller

Required properties:
  - compatible: "ti,lp3943-gpio"
  - gpio-controller: Marks the device node as a GPIO controller.
  - #gpio-cells: Should be 2. See gpio.txt in this directory for a
                 description of the cells format.

Example:
Simple LED controls with LP3943 GPIO controller

&i2c4 {
	lp3943@60 {
		compatible = "ti,lp3943";
		reg = <0x60>;

		gpioex: gpio {
			compatible = "ti,lp3943-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};
	};
};

leds {
	compatible = "gpio-leds";
	indicator1 {
		label = "indi1";
		gpios = <&gpioex 9 GPIO_ACTIVE_LOW>;
	};

	indicator2 {
		label = "indi2";
		gpios = <&gpioex 10 GPIO_ACTIVE_LOW>;
		default-state = "off";
	};
};


code:
GPIO driver for Maxim MAX3191x industrial serializer

Required properties:
 - compatible:		Must be one of:
			"maxim,max31910"
			"maxim,max31911"
			"maxim,max31912"
			"maxim,max31913"
			"maxim,max31953"
			"maxim,max31963"
 - reg: 		Chip select number.
 - gpio-controller:	Marks the device node as a GPIO controller.
 - #gpio-cells: 	Should be two. For consumer use see gpio.txt.

Optional properties:
 - #daisy-chained-devices:
			Number of chips in the daisy-chain (default is 1).
 - maxim,modesel-gpios: GPIO pins to configure modesel of each chip.
			The number of GPIOs must equal "#daisy-chained-devices"
			(if each chip is driven by a separate pin) or 1
			(if all chips are wired to the same pin).
 - maxim,fault-gpios: 	GPIO pins to read fault of each chip.
			The number of GPIOs must equal "#daisy-chained-devices"
			or 1.
 - maxim,db0-gpios:	GPIO pins to configure debounce of each chip.
			The number of GPIOs must equal "#daisy-chained-devices"
			or 1.
 - maxim,db1-gpios:	GPIO pins to configure debounce of each chip.
			The number of GPIOs must equal "maxim,db0-gpios".
 - maxim,modesel-8bit:	Boolean whether the modesel pin of the chips is
			pulled high (8-bit mode).  Use this if the modesel pin
			is hardwired and consequently "maxim,modesel-gpios"
			cannot be specified.  By default if neither this nor
			"maxim,modesel-gpios" is given, the driver assumes
			that modesel is pulled low (16-bit mode).
 - maxim,ignore-undervoltage:
			Boolean whether to ignore undervoltage alarms signaled
			by the "maxim,fault-gpios" or by the status byte
			(in 16-bit mode).  Use this if the chips are powered
			through 5VOUT instead of VCC24V, in which case they
			will constantly signal undervoltage.

For other required and optional properties of SPI slave nodes please refer to
../spi/spi-bus.txt.

Example:
	gpio@0 {
		compatible = "maxim,max31913";
		reg = <0>;
		gpio-controller;
		#gpio-cells = <2>;

		maxim,modesel-gpios = <&gpio2 23>;
		maxim,fault-gpios   = <&gpio2 24 GPIO_ACTIVE_LOW>;
		maxim,db0-gpios     = <&gpio2 25>;
		maxim,db1-gpios     = <&gpio2 26>;

		spi-max-frequency = <25000000>;
	};


code:
GPIO driver for MAX77620 Power management IC from Maxim Semiconductor.

Device has 8 GPIO pins which can be configured as GPIO as well as the
special IO functions.

Required properties:
-------------------
- gpio-controller : 	Marks the device node as a gpio controller.
- #gpio-cells : 	Should be two.  The first cell is the pin number and
			the second cell is used to specify the gpio polarity:
				0 = active high
				1 = active low
For more details, please refer generic GPIO DT binding document
<devicetree/bindings/gpio/gpio.txt>.

Example:
--------
#include <dt-bindings/mfd/max77620.h>
...
max77620@3c {
	compatible = "maxim,max77620";

	gpio-controller;
	#gpio-cells = <2>;
};


code:
Lantiq SoC External Bus memory mapped GPIO controller

By attaching hardware latches to the EBU it is possible to create output
only gpios. This driver configures a special memory address, which when
written to outputs 16 bit to the latches.

The node describing the memory mapped GPIOs needs to be a child of the node
describing the "lantiq,localbus".

Required properties:
- compatible : Should be "lantiq,gpio-mm-lantiq"
- reg : Address and length of the register set for the device
- #gpio-cells : Should be two.  The first cell is the pin number and
  the second cell is used to specify optional parameters (currently
  unused).
- gpio-controller : Marks the device node as a gpio controller.

Optional properties:
- lantiq,shadow : The default value that we shall assume as already set on the
  shift register cascade.

Example:

localbus@0 {
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
		1 0 0x4000000 0x4000010>; /* addsel1 */
	compatible = "lantiq,localbus", "simple-bus";

	gpio_mm0: gpio@4000000 {
		compatible = "lantiq,gpio-mm";
		reg = <1 0x0 0x10>;
		gpio-controller;
		#gpio-cells = <2>;
		lantiq,shadow = <0x77f>
	};
}


code:
Turris Mox Moxtet GPIO expander via Moxtet bus

Required properties:
 - compatible		: Should be "cznic,moxtet-gpio".
 - gpio-controller	: Marks the device node as a GPIO controller.
 - #gpio-cells		: Should be two. For consumer use see gpio.txt.

Other properties are required for a Moxtet bus device, please refer to
Documentation/devicetree/bindings/bus/moxtet.txt.

Example:

	moxtet_sfp: gpio@0 {
		compatible = "cznic,moxtet-gpio";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0>;
	}


code:
* Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller

Required properties:
- compatible : Should be "fsl,<soc>-gpio"
  The following <soc>s are known to be supported:
	mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq,
	ls1021a, ls1043a, ls2080a, ls1028a, ls1088a.
- reg : Address and length of the register set for the device
- interrupts : Should be the port interrupt shared by all 32 pins.
- #gpio-cells : Should be two.  The first cell is the pin number and
  the second cell is used to specify the gpio polarity:
      0 = active high
      1 = active low

Optional properties:
- little-endian : GPIO registers are used as little endian. If not
                  present registers are used as big endian by default.

Example of gpio-controller node for a mpc5125 SoC:

gpio0: gpio@1100 {
	compatible = "fsl,mpc5125-gpio";
	#gpio-cells = <2>;
	reg = <0x1100 0x080>;
	interrupts = <78 0x8>;
};

Example of gpio-controller node for a ls2080a SoC:

gpio0: gpio@2300000 {
	compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
	reg = <0x0 0x2300000 0x0 0x10000>;
	interrupts = <0 36 0x4>; /* Level high type */
	gpio-controller;
	little-endian;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
};

Example of gpio-controller node for a ls1028a/ls1088a SoC:

gpio1: gpio@2300000 {
	compatible = "fsl,ls1028a-gpio", "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
	reg = <0x0 0x2300000 0x0 0x10000>;
	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	little-endian;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell EBU GPIO controller

maintainers:
  - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  - Andrew Lunn <andrew@lunn.ch>

properties:
  compatible:
    oneOf:
      - enum:
          - marvell,armada-8k-gpio
          - marvell,orion-gpio

      - items:
          - enum:
              - marvell,mv78200-gpio
              - marvell,armada-370-gpio
          - const: marvell,orion-gpio

      - description: Deprecated binding
        items:
          - const: marvell,armadaxp-gpio
          - const: marvell,orion-gpio
        deprecated: true

  reg:
    description: |
      Address and length of the register set for the device. Not used for
      marvell,armada-8k-gpio.

      A second entry can be provided, for the PWM function using the GPIO Blink
      Counter on/off registers.
    minItems: 1
    maxItems: 2

  reg-names:
    items:
      - const: gpio
      - const: pwm
    minItems: 1

  offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Offset in the register map for the gpio registers (in bytes)

  interrupts:
    description: |
      The list of interrupts that are used for all the pins managed by this
      GPIO bank. There can be more than one interrupt (example: 1 interrupt
      per 8 pins on Armada XP, which means 4 interrupts per bank of 32
      GPIOs).
    minItems: 1
    maxItems: 4

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  gpio-controller: true

  ngpios:
    minimum: 1
    maximum: 32

  "#gpio-cells":
    const: 2

  marvell,pwm-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Offset in the register map for the pwm registers (in bytes)

  "#pwm-cells":
    description:
      The first cell is the GPIO line number. The second cell is the period
      in nanoseconds.
    const: 2

  clocks:
    description:
      Clock(s) used for PWM function.
    items:
      - description: Core clock
      - description: AXI bus clock
    minItems: 1

  clock-names:
    items:
      - const: core
      - const: axi
    minItems: 1

required:
  - compatible
  - gpio-controller
  - ngpios
  - "#gpio-cells"

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: marvell,armada-8k-gpio
    then:
      required:
        - offset
    else:
      required:
        - reg

unevaluatedProperties: true

examples:
  - |
    gpio@d0018100 {
      compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
      reg = <0xd0018100 0x40>, <0xd0018800 0x30>;
      ngpios = <32>;
      gpio-controller;
      #gpio-cells = <2>;
      interrupt-controller;
      #interrupt-cells = <2>;
      interrupts = <16>, <17>, <18>, <19>;
    };

  - |
    gpio@18140 {
      compatible = "marvell,armada-370-gpio", "marvell,orion-gpio";
      reg = <0x18140 0x40>, <0x181c8 0x08>;
      reg-names = "gpio", "pwm";
      ngpios = <17>;
      gpio-controller;
      #gpio-cells = <2>;
      #pwm-cells = <2>;
      interrupt-controller;
      #interrupt-cells = <2>;
      interrupts = <87>, <88>, <89>;
      clocks = <&coreclk 0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-mxs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale MXS GPIO controller

maintainers:
  - Shawn Guo <shawnguo@kernel.org>
  - Anson Huang <Anson.Huang@nxp.com>

description: |
  The Freescale MXS GPIO controller is part of MXS PIN controller.
  The GPIOs are organized in port/bank, each port consists of 32 GPIOs.
  As the GPIO controller is embedded in the PIN controller and all the
  GPIO ports share the same IO space with PIN controller, the GPIO node
  will be represented as sub-nodes of MXS pinctrl node.

properties:
  compatible:
    enum:
      - fsl,imx23-pinctrl
      - fsl,imx28-pinctrl

  '#address-cells':
    const: 1
  '#size-cells':
    const: 0

  reg:
    maxItems: 1

patternProperties:
  "gpio@[0-9]+$":
    type: object
    properties:
      compatible:
        enum:
          - fsl,imx23-gpio
          - fsl,imx28-gpio

      reg:
        maxItems: 1

      interrupts:
        description: Should be the port interrupt shared by all 32 pins.
        maxItems: 1

      interrupt-controller: true

      "#interrupt-cells":
        const: 2

      "#gpio-cells":
        const: 2

      gpio-controller: true

    required:
      - compatible
      - reg
      - interrupts
      - interrupt-controller
      - "#interrupt-cells"
      - "#gpio-cells"
      - gpio-controller

    additionalProperties: false

required:
  - compatible
  - reg
  - '#address-cells'
  - '#size-cells'

additionalProperties: false

examples:
  - |
    pinctrl@80018000 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "fsl,imx28-pinctrl";
        reg = <0x80018000 0x2000>;

        gpio@0 {
                compatible = "fsl,imx28-gpio";
                reg = <0>;
                interrupts = <127>;
                gpio-controller;
                #gpio-cells = <2>;
                interrupt-controller;
                #interrupt-cells = <2>;
        };

        gpio@1 {
                compatible = "fsl,imx28-gpio";
                reg = <1>;
                interrupts = <126>;
                gpio-controller;
                #gpio-cells = <2>;
                interrupt-controller;
                #interrupt-cells = <2>;
        };

        gpio@2 {
                compatible = "fsl,imx28-gpio";
                reg = <2>;
                interrupts = <125>;
                gpio-controller;
                #gpio-cells = <2>;
                interrupt-controller;
                #interrupt-cells = <2>;
        };

        gpio@3 {
                compatible = "fsl,imx28-gpio";
                reg = <3>;
                interrupts = <124>;
                gpio-controller;
                #gpio-cells = <2>;
                interrupt-controller;
                #interrupt-cells = <2>;
        };

        gpio@4 {
                compatible = "fsl,imx28-gpio";
                reg = <4>;
                interrupts = <123>;
                gpio-controller;
                #gpio-cells = <2>;
                interrupt-controller;
                #interrupt-cells = <2>;
        };
    };


code:
Nomadik GPIO controller

Required properties:
- compatible            : Should be "st,nomadik-gpio".
- reg                   : Physical base address and length of the controller's registers.
- interrupts            : The interrupt outputs from the controller.
- #gpio-cells           : Should be two:
                            The first cell is the pin number.
                            The second cell is used to specify optional parameters:
                              - bits[3:0] trigger type and level flags:
                                  1 = low-to-high edge triggered.
                                  2 = high-to-low edge triggered.
                                  4 = active high level-sensitive.
                                  8 = active low level-sensitive.
- gpio-controller       : Marks the device node as a GPIO controller.
- interrupt-controller  : Marks the device node as an interrupt controller.
- gpio-bank             : Specifies which bank a controller owns.
- st,supports-sleepmode : Specifies whether controller can sleep or not

Example:

                gpio1: gpio@8012e080 {
                        compatible = "st,nomadik-gpio";
                        reg =  <0x8012e080 0x80>;
                        interrupts = <0 120 0x4>;
                        #gpio-cells = <2>;
                        gpio-controller;
                        interrupt-controller;
                        st,supports-sleepmode;
                        gpio-bank = <1>;
                };


code:
Palmas GPIO controller bindings

Required properties:
- compatible:
  - "ti,palams-gpio" for palma series of the GPIO controller
  - "ti,tps80036-gpio" for Palma series device TPS80036.
  - "ti,tps65913-gpio" for palma series device TPS65913.
  - "ti,tps65914-gpio" for palma series device TPS65914.
- #gpio-cells : Should be two.
  - first cell is the gpio pin number
  - second cell is used to specify the gpio polarity:
      0 = active high
      1 = active low
- gpio-controller : Marks the device node as a GPIO controller.

Note: This gpio node will be sub node of palmas node.

Example:
	palmas: tps65913@58 {
		:::::::::::
		palmas_gpio: palmas_gpio {
			compatible = "ti,palmas-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};
		:::::::::::
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-pca9570.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PCA9570 I2C GPO expander

maintainers:
  - Sungbo Eo <mans0n@gorani.run>

properties:
  compatible:
    enum:
      - dlg,slg7xl45106
      - nxp,pca9570
      - nxp,pca9571

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"

additionalProperties: false

examples:
  - |
    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        gpio@24 {
            compatible = "nxp,pca9570";
            reg = <0x24>;
            gpio-controller;
            #gpio-cells = <2>;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-pca95xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP PCA95xx I2C GPIO multiplexer

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |+
  Bindings for the family of I2C GPIO multiplexers/expanders: NXP PCA95xx,
  Maxim MAX73xx

properties:
  compatible:
    oneOf:
      - items:
          - const: diodes,pi4ioe5v6534q
          - const: nxp,pcal6534
      - items:
          - enum:
              - exar,xra1202
              - maxim,max7310
              - maxim,max7312
              - maxim,max7313
              - maxim,max7315
              - maxim,max7319
              - maxim,max7320
              - maxim,max7321
              - maxim,max7322
              - maxim,max7323
              - maxim,max7324
              - maxim,max7325
              - maxim,max7326
              - maxim,max7327
              - nxp,pca6408
              - nxp,pca6416
              - nxp,pca9505
              - nxp,pca9506
              - nxp,pca9534
              - nxp,pca9535
              - nxp,pca9536
              - nxp,pca9537
              - nxp,pca9538
              - nxp,pca9539
              - nxp,pca9554
              - nxp,pca9555
              - nxp,pca9556
              - nxp,pca9557
              - nxp,pca9574
              - nxp,pca9575
              - nxp,pca9698
              - nxp,pcal6408
              - nxp,pcal6416
              - nxp,pcal6524
              - nxp,pcal6534
              - nxp,pcal9535
              - nxp,pcal9554b
              - nxp,pcal9555a
              - onnn,cat9554
              - onnn,pca9654
              - ti,pca6107
              - ti,pca9536
              - ti,tca6408
              - ti,tca6416
              - ti,tca6424
              - ti,tca9539
              - ti,tca9554

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2

  gpio-line-names:
    minItems: 1
    maxItems: 40

  interrupts:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  reset-gpios:
    maxItems: 1
    description:
      GPIO specification for the RESET input. This is an active low signal to
      the PCA953x.  Not valid for Maxim MAX732x devices.

  vcc-supply:
    description:
      Optional power supply.  Not valid for Maxim MAX732x devices.

  wakeup-source:
    $ref: /schemas/types.yaml#/definitions/flag

patternProperties:
  "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
    type: object
    properties:
      gpio-hog: true
      gpios: true
      input: true
      output-high: true
      output-low: true
      line-name: true

    required:
      - gpio-hog
      - gpios

    additionalProperties: false

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - maxim,max7320
              - maxim,max7321
              - maxim,max7322
              - maxim,max7323
              - maxim,max7324
              - maxim,max7325
              - maxim,max7326
              - maxim,max7327
    then:
      properties:
        reset-gpios: false
        vcc-supply: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c0 {
        #address-cells = <1>;
        #size-cells = <0>;

        gpio@20 {
            compatible = "nxp,pca9505";
            reg = <0x20>;
            pinctrl-names = "default";
            pinctrl-0 = <&pinctrl_pca9505>;
            gpio-controller;
            #gpio-cells = <2>;
            interrupt-parent = <&gpio3>;
            interrupts = <23 IRQ_TYPE_LEVEL_LOW>;

            usb3-sata-sel-hog {
                gpio-hog;
                gpios = <4 GPIO_ACTIVE_HIGH>;
                output-low;
                line-name = "usb3_sata_sel";
            };
        };
    };

  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c1 {
        #address-cells = <1>;
        #size-cells = <0>;

        gpio99: gpio@22 {
            compatible = "nxp,pcal6524";
            reg = <0x22>;
            interrupt-parent = <&gpio6>;
            interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* gpio6_161 */
            interrupt-controller;
            #interrupt-cells = <2>;
            vcc-supply = <&vdds_1v8_main>;
            gpio-controller;
            #gpio-cells = <2>;
            gpio-line-names = "hdmi-ct-hpd", "hdmi.ls-oe", "p02", "p03",
                              "vibra", "fault2", "p06", "p07", "en-usb",
                              "en-host1", "en-host2", "chg-int", "p14", "p15",
                              "mic-int", "en-modem", "shdn-hs-amp",
                              "chg-status+red", "green", "blue", "en-esata",
                              "fault1", "p26", "p27";
        };
    };

  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c2 {
        #address-cells = <1>;
        #size-cells = <0>;

        /* MAX7325 with interrupt support enabled */
        gpio@6d {
            compatible = "maxim,max7325";
            reg = <0x6d>;
            gpio-controller;
            #gpio-cells = <2>;
            interrupt-controller;
            #interrupt-cells = <2>;
            interrupt-parent = <&gpio4>;
            interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
        };
    };

  - |
    i2c3 {
        #address-cells = <1>;
        #size-cells = <0>;

        /* MAX7325 with interrupt support disabled */
        gpio@6e {
            compatible = "maxim,max7325";
            reg = <0x6e>;
            gpio-controller;
            #gpio-cells = <2>;
        };
    };


code:
Generic Parallel-in/Serial-out Shift Register GPIO Driver

This binding describes generic parallel-in/serial-out shift register
devices that can be used for GPI (General Purpose Input). This includes
SN74165 serial-out shift registers and the SN65HVS88x series of
industrial serializers.

Required properties:
 - compatible		: Should be "pisosr-gpio".
 - gpio-controller	: Marks the device node as a GPIO controller.
 - #gpio-cells		: Should be two. For consumer use see gpio.txt.

Optional properties:
 - ngpios		: Number of used GPIO lines (0..n-1), default is 8.
 - load-gpios		: GPIO pin specifier attached to load enable, this
			  pin is pulsed before reading from the device to
			  load input pin values into the device.

For other required and optional properties of SPI slave
nodes please refer to ../spi/spi-bus.txt.

Example:

	gpio@0 {
		compatible = "ti,sn65hvs882", "pisosr-gpio";
		gpio-controller;
		#gpio-cells = <2>;

		load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;

		reg = <0>;
		spi-max-frequency = <1000000>;
		spi-cpol;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-rda.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RDA Micro GPIO controller

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

properties:
  compatible:
    const: rda,8810pl-gpio

  reg:
    maxItems: 1

  gpio-controller: true

  "#gpio-cells":
    const: 2

  ngpios:
    description:
      Number of available gpios in a bank.
    minimum: 1
    maximum: 32

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"
  - ngpios
  - interrupt-controller
  - "#interrupt-cells"
  - interrupts

additionalProperties: false

...


code:
Spreadtrum GPIO controller bindings

The controller's registers are organized as sets of sixteen 16-bit
registers with each set controlling a bank of up to 16 pins. A single
interrupt is shared for all of the banks handled by the controller.

Required properties:
- compatible: Should be "sprd,sc9860-gpio".
- reg: Define the base and range of the I/O address space containing
the GPIO controller registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be <2>. The first cell is the gpio number and
the second cell is used to specify optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be <2>. Specifies the number of cells needed
to encode interrupt source.
- interrupts: Should be the port interrupt shared by all the gpios.

Example:
	ap_gpio: gpio@40280000 {
		compatible = "sprd,sc9860-gpio";
		reg = <0 0x40280000 0 0x1000>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
	};


code:
STMPE gpio
----------

Required properties:
 - compatible: "st,stmpe-gpio"

Optional properties:
 - st,norequest-mask: bitmask specifying which GPIOs should _not_ be requestable
   due to different usage (e.g. touch, keypad)

Node should be child node of stmpe node to which it belongs.

Example:
	stmpe_gpio {
		compatible = "st,stmpe-gpio";
		st,norequest-mask = <0x20>;	//gpio 5 can't be used
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-stp-xway.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Lantiq SoC Serial To Parallel (STP) GPIO controller

description: |
  The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
  peripheral controller used to drive external shift register cascades. At most
  3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
  and Ethernet PHYs to drive some bytes of the cascade automatically.

maintainers:
  - John Crispin <john@phrozen.org>

properties:
  $nodename:
    pattern: "^gpio@[0-9a-f]+$"

  compatible:
    const: lantiq,gpio-stp-xway

  reg:
    maxItems: 1

  gpio-controller: true

  "#gpio-cells":
    description:
      The first cell is the pin number and the second cell is used to specify
      consumer flags.
    const: 2

  lantiq,shadow:
    description:
      The default value that we shall assume as already set on the
      shift register cascade.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0x000000
    maximum: 0xffffff

  lantiq,groups:
    description:
      Set the 3 bit mask to select which of the 3 groups are enabled
      in the shift register cascade.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0x0
    maximum: 0x7

  lantiq,dsl:
    description:
      The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
      property can enable this feature.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0x0
    maximum: 0x3

  lantiq,rising:
    description:
      Use rising instead of falling edge for the shift register.
    type: boolean

patternProperties:
  "^lantiq,phy[1-4]$":
    description:
      The gphy core can control 3 bits of the gpio cascade. In the xRX200 family
      phy[1-2] are available, in xRX330 phy[1-3] and in XRX330 phy[1-4].
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0x0
    maximum: 0x7

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"

additionalProperties: false

examples:
  - |
    gpio@e100bb0 {
        compatible = "lantiq,gpio-stp-xway";
        reg = <0xE100BB0 0x40>;
        #gpio-cells = <2>;
        gpio-controller;

        pinctrl-0 = <&stp_pins>;
        pinctrl-names = "default";

        lantiq,shadow = <0xffffff>;
        lantiq,groups = <0x7>;
        lantiq,dsl = <0x3>;
        lantiq,phy1 = <0x7>;
        lantiq,phy2 = <0x7>;
    };
...


code:
Cavium ThunderX/OCTEON-TX GPIO controller bindings

Required Properties:
- reg: The controller bus address.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Must be 2.
  - First cell is the GPIO pin number relative to the controller.
  - Second cell is a standard generic flag bitfield as described in gpio.txt.

Optional Properties:
- compatible: "cavium,thunder-8890-gpio", unused as PCI driver binding is used.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Must be present and have value of 2 if
                    "interrupt-controller" is present.
  - First cell is the GPIO pin number relative to the controller.
  - Second cell is triggering flags as defined in interrupts.txt.

Example:

gpio_6_0: gpio@6,0 {
	compatible = "cavium,thunder-8890-gpio";
	reg = <0x3000 0 0 0 0>; /*  DEVFN = 0x30 (6:0) */
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-tpic2810.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TPIC2810 GPIO controller bindings

maintainers:
  - Aswath Govindraju <a-govindraju@ti.com>

properties:
  compatible:
    enum:
      - ti,tpic2810

  reg:
    maxItems: 1

  gpio-controller: true

  "#gpio-cells":
    const: 2

  gpio-line-names:
    minItems: 1
    maxItems: 32

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;
        gpio@60 {
            compatible = "ti,tpic2810";
            reg = <0x60>;
            gpio-controller;
            #gpio-cells = <2>;
            gpio-line-names = "LED A", "LED B", "LED C";
        };
    };


code:
* TS-4800 FPGA's GPIO controller bindings

Required properties:
- compatible: Must be "technologic,ts4800-gpio".
- #gpio-cells: Should be two. The first cell is the pin number.
- reg: Physical base address of the controller and length
       of memory mapped region.

Optional property:
- ngpios: See "gpio.txt"

Example:

gpio1: gpio {
	compatible = "technologic,ts4800-gpio";
	reg = <0x10020 0x6>;
	ngpios = <8>;
	gpio-controller;
	#gpio-cells = <2>;
};


code:
* Technologic Systems I2C-FPGA's GPIO controller bindings

This bindings describes the GPIO controller for Technologic's FPGA core.
TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
uses 2 bits: it doesn't use a dedicated input bit.

Required properties:
- compatible: Should be one of the following
		"technologic,ts4900-gpio"
		"technologic,ts7970-gpio"
- reg: Physical base address of the controller and length
       of memory mapped region.
- #gpio-cells: Should be two. The first cell is the pin number.
- gpio-controller: Marks the device node as a gpio controller.

Optional property:
- ngpios: Number of GPIOs this controller is instantiated with,
  the default is 32. See gpio.txt for more details.

Example:

&i2c2 {
	gpio8: gpio@28 {
		compatible = "technologic,ts4900-gpio";
		reg = <0x28>;
		#gpio-cells = <2>;
		gpio-controller;
		ngpios = <32>;
	};
};


code:
twl4030 GPIO controller bindings

Required properties:
- compatible:
  - "ti,twl4030-gpio" for twl4030 GPIO controller
- #gpio-cells : Should be two.
  - first cell is the pin number
  - second cell is used to specify optional parameters (unused)
- gpio-controller : Marks the device node as a GPIO controller.
- #interrupt-cells : Should be 2.
- interrupt-controller: Mark the device node as an interrupt controller
  The first cell is the GPIO number.
  The second cell is not used.
- ti,use-leds : Enables LEDA and LEDB outputs if set
- ti,debounce : if n-th bit is set, debounces GPIO-n
- ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1)
- ti,pullups : if n-th bit is set, set a pullup on GPIO-n
- ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n

Example:

twl_gpio: gpio {
    compatible = "ti,twl4030-gpio";
    #gpio-cells = <2>;
    gpio-controller;
    #interrupt-cells = <2>;
    interrupt-controller;
    ti,use-leds;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale VF610 PORT/GPIO module

maintainers:
  - Stefan Agner <stefan@agner.ch>

description: |
  The Freescale PORT/GPIO modules are two adjacent modules providing GPIO
  functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of
  each, and each PORT module has its own interrupt.

  Note: Each GPIO port should have an alias correctly numbered in "aliases"
  node.

properties:
  compatible:
    oneOf:
      - const: fsl,vf610-gpio
      - items:
          - const: fsl,imx7ulp-gpio
          - const: fsl,vf610-gpio
      - items:
          - enum:
              - fsl,imx93-gpio
              - fsl,imx8ulp-gpio
          - const: fsl,imx7ulp-gpio

  reg:
    description: The first reg tuple represents the PORT module, the second tuple
      represents the GPIO module.
    maxItems: 2

  interrupts:
    maxItems: 1

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  "#gpio-cells":
    const: 2

  gpio-controller: true

  clocks:
    items:
      - description: SoC GPIO clock
      - description: SoC PORT clock

  clock-names:
    items:
      - const: gpio
      - const: port

  gpio-ranges:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - "#interrupt-cells"
  - "#gpio-cells"
  - gpio-controller

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gpio1: gpio@40049000 {
        compatible = "fsl,vf610-gpio";
        reg = <0x40049000 0x1000>, <0x400ff000 0x40>;
        interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-ranges = <&iomuxc 0 0 32>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-virtio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Virtio GPIO controller

maintainers:
  - Viresh Kumar <viresh.kumar@linaro.org>

allOf:
  - $ref: /schemas/virtio/virtio-device.yaml#

description:
  Virtio GPIO controller, see /schemas/virtio/virtio-device.yaml for more
  details.

properties:
  $nodename:
    const: gpio

  compatible:
    const: virtio,device29

  gpio-controller: true

  "#gpio-cells":
    const: 2

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

required:
  - compatible
  - gpio-controller
  - "#gpio-cells"

unevaluatedProperties: false

examples:
  - |
    virtio@3000 {
        compatible = "virtio,mmio";
        reg = <0x3000 0x100>;
        interrupts = <41>;

        gpio {
            compatible = "virtio,device29";
            gpio-controller;
            #gpio-cells = <2>;
            interrupt-controller;
            #interrupt-cells = <2>;
        };
    };

...


code:
APM X-Gene Standby GPIO controller bindings

This is a gpio controller in the standby domain. It also supports interrupt in
some particular pins which are sourced to its parent interrupt controller
as diagram below:
                            +-----------------+
                            | X-Gene standby  |
                            | GPIO controller +------ GPIO_0
+------------+              |                 | ...
| Parent IRQ | EXT_INT_0    |                 +------ GPIO_8/EXT_INT_0
| controller | (SPI40)      |                 | ...
| (GICv2)    +--------------+                 +------ GPIO_[N+8]/EXT_INT_N
|            |   ...        |                 |
|            | EXT_INT_N    |                 +------ GPIO_[N+9]
|            | (SPI[40 + N])|                 | ...
|            +--------------+                 +------ GPIO_MAX
+------------+              +-----------------+

Required properties:
- compatible: "apm,xgene-gpio-sb" for the X-Gene Standby GPIO controller
- reg: Physical base address and size of the controller's registers
- #gpio-cells: Should be two.
	- first cell is the pin number
	- second cell is used to specify the gpio polarity:
		0 = active high
		1 = active low
- gpio-controller: Marks the device node as a GPIO controller.
- interrupts: The EXT_INT_0 parent interrupt resource must be listed first.
- interrupt-cells: Should be two.
       - first cell is 0-N coresponding for EXT_INT_0 to EXT_INT_N.
       - second cell is used to specify flags.
- interrupt-controller: Marks the device node as an interrupt controller.
- apm,nr-gpios: Optional, specify number of gpios pin.
- apm,nr-irqs: Optional, specify number of interrupt pins.
- apm,irq-start: Optional, specify lowest gpio pin support interrupt.

Example:
	sbgpio: gpio@17001000{
		compatible = "apm,xgene-gpio-sb";
		reg = <0x0 0x17001000 0x0 0x400>;
		#gpio-cells = <2>;
		gpio-controller;
		interrupts = 	<0x0 0x28 0x1>,
				<0x0 0x29 0x1>,
				<0x0 0x2a 0x1>,
				<0x0 0x2b 0x1>,
				<0x0 0x2c 0x1>,
				<0x0 0x2d 0x1>;
		interrupt-parent = <&gic>;
		#interrupt-cells = <2>;
		interrupt-controller;
		apm,nr-gpios = <22>;
		apm,nr-irqs = <6>;
		apm,irq-start = <8>;
	};

	testuser {
		compatible = "example,testuser";
		/* Use the GPIO_13/EXT_INT_5 line as an active high triggered
		 * level interrupt
		 */
		interrupts = <5 4>;
		interrupt-parent = <&sbgpio>;
	};


code:
APM X-Gene SoC GPIO controller bindings

This is a gpio controller that is part of the flash controller.
This gpio controller controls a total of 48 gpios.

Required properties:
- compatible: "apm,xgene-gpio" for X-Gene GPIO controller
- reg: Physical base address and size of the controller's registers
- #gpio-cells: Should be two.
	- first cell is the pin number
	- second cell is used to specify the gpio polarity:
		0 = active high
		1 = active low
- gpio-controller: Marks the device node as a GPIO controller.

Example:
	gpio0: gpio0@1701c000 {
		compatible = "apm,xgene-gpio";
		reg = <0x0 0x1701c000 0x0 0x40>;
		gpio-controller;
		#gpio-cells = <2>;
	};


code:
GPIO Driver for XRA1403 16-BIT GPIO Expander With Reset Input from EXAR

The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features available:
	- Individually programmable inputs:
		- Internal pull-up resistors
		- Polarity inversion
		- Individual interrupt enable
		- Rising edge and/or Falling edge interrupt
		- Input filter
	- Individually programmable outputs
		- Output Level Control
		- Output Three-State Control

Properties
----------
Check documentation for SPI and GPIO controllers regarding properties needed to configure the node.

	- compatible = "exar,xra1403".
	- reg - SPI id of the device.
	- gpio-controller - marks the node as gpio.
	- #gpio-cells - should be two where the first cell is the pin number
		and the second one is used for optional parameters.

Optional properties:
-------------------
	- reset-gpios: in case available used to control the device reset line.
	- interrupt-controller - marks the node as interrupt controller.
	- #interrupt-cells - should be two and represents the number of cells
		needed to encode interrupt source.

Example
--------

	gpioxra0: gpio@2 {
		compatible = "exar,xra1403";
		reg = <2>;

		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;

		reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
		spi-max-frequency = <1000000>;
	};


code:
Zevio GPIO controller

Required properties:
- compatible: Should be "lsi,zevio-gpio"
- reg: Address and length of the register set for the device
- #gpio-cells: Should be two. The first cell is the pin number and the
  second cell is used to specify optional parameters (currently unused).
- gpio-controller: Marks the device node as a GPIO controller.

Example:
	gpio: gpio@90000000 {
		compatible = "lsi,zevio-gpio";
		reg = <0x90000000 0x1000>;
		gpio-controller;
		#gpio-cells = <2>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-zynq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Zynq GPIO controller

maintainers:
  - Michal Simek <michal.simek@xilinx.com>

properties:
  compatible:
    enum:
      - xlnx,zynq-gpio-1.0
      - xlnx,zynqmp-gpio-1.0
      - xlnx,versal-gpio-1.0
      - xlnx,pmc-gpio-1.0

  reg:
    maxItems: 1

  "#gpio-cells":
    const: 2

  interrupts:
    maxItems: 1

  gpio-controller: true

  gpio-line-names:
    description: strings describing the names of each gpio line
    minItems: 58
    maxItems: 174

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

allOf:
  - if:
      properties:
        compatible:
          enum:
            - xlnx,zynqmp-gpio-1.0
    then:
      properties:
        gpio-line-names:
          minItems: 174
          maxItems: 174

  - if:
      properties:
        compatible:
          enum:
            - xlnx,zynq-gpio-1.0
    then:
      properties:
        gpio-line-names:
          minItems: 118
          maxItems: 118

  - if:
      properties:
        compatible:
          enum:
            - xlnx,versal-gpio-1.0
    then:
      properties:
        gpio-line-names:
          minItems: 58
          maxItems: 58

  - if:
      properties:
        compatible:
          enum:
            - xlnx,pmc-gpio-1.0
    then:
      properties:
        gpio-line-names:
          minItems: 116
          maxItems: 116

required:
  - compatible
  - reg
  - "#gpio-cells"
  - interrupts
  - gpio-controller
  - interrupt-controller
  - "#interrupt-cells"
  - clocks

additionalProperties: false

examples:
  - |
    gpio@e000a000 {
      #gpio-cells = <2>;
      compatible = "xlnx,zynq-gpio-1.0";
      clocks = <&clkc 42>;
      gpio-controller;
      interrupt-parent = <&intc>;
      interrupts = <0 20 4>;
      interrupt-controller;
      #interrupt-cells = <2>;
      reg = <0xe000a000 0x1000>;
    };