code:
// SPDX-License-Identifier: BSD-3-Clause
/*
 * SDX65 SoC device tree source
 *
 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 */

#include <dt-bindings/clock/qcom,gcc-sdx65.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
	interrupt-parent = <&intc>;

	memory {
		device_type = "memory";
		reg = <0 0>;
	};

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			clock-frequency = <76800000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			clock-frequency = <32764>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};

		nand_clk_dummy: nand-clk-dummy {
			compatible = "fixed-clock";
			clock-frequency = <32764>;
			#clock-cells = <0>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			enable-method = "psci";
			clocks = <&apcs>;
			power-domains = <&rpmhpd SDX65_CX_AO>;
			power-domain-names = "rpmhpd";
			operating-points-v2 = <&cpu_opp_table>;
		};
	};

	cpu_opp_table: cpu-opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-345600000 {
			opp-hz = /bits/ 64 <345600000>;
			required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-576000000 {
			opp-hz = /bits/ 64 <576000000>;
			required-opps = <&rpmhpd_opp_svs>;
		};

		opp-1094400000 {
			opp-hz = /bits/ 64 <1094400000>;
			required-opps = <&rpmhpd_opp_nom>;
		};

		opp-1497600000 {
			opp-hz = /bits/ 64 <1497600000>;
			required-opps = <&rpmhpd_opp_turbo>;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-sdx65", "qcom,scm";
		};
	};

	mc_virt: interconnect-mc-virt {
		compatible = "qcom,sdx65-mc-virt";
		#interconnect-cells = <1>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved_memory: reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		tz_heap_mem: memory@8fcad000 {
			no-map;
			reg = <0x8fcad000 0x40000>;
		};

		secdata_mem: memory@8fcfd000 {
			no-map;
			reg = <0x8fcfd000 0x1000>;
		};

		hyp_mem: memory@8fd00000 {
			no-map;
			reg = <0x8fd00000 0x80000>;
		};

		access_control_mem: memory@8fd80000 {
			no-map;
			reg = <0x8fd80000 0x80000>;
		};

		aop_mem: memory@8fe00000 {
			no-map;
			reg = <0x8fe00000 0x20000>;
		};

		smem_mem: memory@8fe20000 {
			compatible = "qcom,smem";
			reg = <0x8fe20000 0xc0000>;
			hwlocks = <&tcsr_mutex 3>;
			no-map;
		};

		cmd_db: reserved-memory@8fee0000 {
			compatible = "qcom,cmd-db";
			reg = <0x8fee0000 0x20000>;
			no-map;
		};

		tz_mem: memory@8ff00000 {
			no-map;
			reg = <0x8ff00000 0x100000>;
		};

		tz_apps_mem: memory@90000000 {
			no-map;
			reg = <0x90000000 0x500000>;
		};

		llcc_tcm_mem: memory@15800000 {
			no-map;
			reg = <0x15800000 0x800000>;
		};
	};

	smp2p-mpss {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		ipa_smp2p_out: ipa-ap-to-modem {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		ipa_smp2p_in: ipa-modem-to-ap {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-sdx65";
			reg = <0x00100000 0x001f7400>;
			clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
			#power-domain-cells = <1>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		blsp1_uart3: serial@831000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x00831000 0x200>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		usb_hsphy: phy@ff4000 {
			compatible = "qcom,usb-snps-hs-7nm-phy";
			reg = <0xff4000 0x120>;
			#phy-cells = <0>;
			status = "disabled";
			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "ref";
			resets = <&gcc GCC_QUSB2PHY_BCR>;
		};

		usb_qmpphy: phy@ff6000 {
			compatible = "qcom,sdx65-qmp-usb3-uni-phy";
			reg = <0x00ff6000 0x1c8>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
				 <&gcc GCC_USB3_PRIM_CLKREF_EN>;
			clock-names = "aux", "cfg_ahb", "ref";

			resets = <&gcc GCC_USB3PHY_PHY_BCR>,
				 <&gcc GCC_USB3_PHY_BCR>;
			reset-names = "phy", "common";

			usb_ssphy: phy@ff6200 {
				reg = <0x00ff6e00 0x160>,
				      <0x00ff7000 0x1ec>,
				      <0x00ff6200 0x1e00>;
				#phy-cells = <0>;
				#clock-cells = <0>;
				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
				clock-names = "pipe0";
				clock-output-names = "usb3_uni_phy_pipe_clk_src";
			};
		};

		system_noc: interconnect@1620000 {
			compatible = "qcom,sdx65-system-noc";
			reg = <0x01620000 0x31200>;
			#interconnect-cells = <1>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		qpic_bam: dma-controller@1b04000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x01b04000 0x1c000>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rpmhcc RPMH_QPIC_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			qcom,controlled-remotely;
			status = "disabled";
		};

		qpic_nand: nand-controller@1b30000 {
			compatible = "qcom,sdx55-nand";
			reg = <0x01b30000 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&rpmhcc RPMH_QPIC_CLK>,
				 <&nand_clk_dummy>;
			clock-names = "core", "aon";

			dmas = <&qpic_bam 0>,
			       <&qpic_bam 1>,
			       <&qpic_bam 2>;
			dma-names = "tx", "rx", "cmd";
			status = "disabled";
		};

		tcsr_mutex: hwlock@1f40000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x01f40000 0x40000>;
			#hwlock-cells = <1>;
		};

		remoteproc_mpss: remoteproc@4080000 {
			compatible = "qcom,sdx55-mpss-pas";
			reg = <0x04080000 0x4040>;

			interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready", "handover",
					  "stop-ack", "shutdown-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd SDX65_CX>,
					<&rpmhpd SDX65_MSS>;
			power-domain-names = "cx", "mss";

			qcom,smem-states = <&modem_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
				label = "mpss";
				qcom,remote-pid = <1>;
				mboxes = <&apcs 15>;
			};
		};

		sdhc_1: mmc@8804000 {
			compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
			reg = <0x08804000 0x1000>;
			reg-names = "hc";
			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
				 <&gcc GCC_SDCC1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		mem_noc: interconnect@9680000 {
			compatible = "qcom,sdx65-mem-noc";
			reg = <0x09680000 0x27200>;
			#interconnect-cells = <1>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		usb: usb@a6f8800 {
			compatible = "qcom,sdx65-dwc3", "qcom,dwc3";
			reg = <0x0a6f8800 0x400>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
				 <&gcc GCC_USB30_MASTER_CLK>,
				 <&gcc GCC_USB30_MSTR_AXI_CLK>,
				 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB30_SLEEP_CLK>;
			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
					"sleep";

			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <200000000>;

			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 76 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 18 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 19 IRQ_TYPE_EDGE_BOTH>;
			interrupt-names = "hs_phy_irq",
					  "ss_phy_irq",
					  "dm_hs_phy_irq",
					  "dp_hs_phy_irq";

			power-domains = <&gcc USB30_GDSC>;

			resets = <&gcc GCC_USB30_BCR>;

			usb_dwc3: usb@a600000 {
				compatible = "snps,dwc3";
				reg = <0x0a600000 0xcd00>;
				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
				iommus = <&apps_smmu 0x1a0 0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				phys = <&usb_hsphy>, <&usb_ssphy>;
				phy-names = "usb2-phy", "usb3-phy";
			};
		};

		restart@c264000 {
			compatible = "qcom,pshold";
			reg = <0x0c264000 0x1000>;
		};

		spmi_bus: qcom,spmi@c440000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0xc440000 0xd00>,
				<0xc600000 0x2000000>,
				<0xe600000 0x100000>,
				<0xe700000 0xa0000>,
				<0xc40a000 0x26000>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "periph_irq";
			interrupt-controller;
			#interrupt-cells = <4>;
			#address-cells = <2>;
			#size-cells = <0>;
			cell-index = <0>;
			qcom,channel = <0>;
			qcom,ee = <0>;
		};

		tlmm: pinctrl@f100000 {
			compatible = "qcom,sdx65-tlmm";
			reg = <0xf100000 0x300000>;
			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&tlmm 0 0 109>;
			interrupt-controller;
			interrupt-parent = <&intc>;
			#interrupt-cells = <2>;
		};

		pdc: interrupt-controller@b210000 {
			compatible = "qcom,sdx65-pdc", "qcom,pdc";
			reg = <0xb210000 0x10000>;
			qcom,pdc-ranges = <0 147 52>, <52 266 32>;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupt-controller;
		};

		sram@1468f000 {
			compatible = "qcom,sdx65-imem", "syscon", "simple-mfd";
			reg = <0x1468f000 0x1000>;
			ranges = <0x0 0x1468f000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			pil-reloc@94c {
				compatible = "qcom,pil-reloc-info";
				reg = <0x94c 0xc8>;
			};
		};

		apps_smmu: iommu@15000000 {
			compatible = "qcom,sdx65-smmu-500", "arm,mmu-500";
			reg = <0x15000000 0x40000>;
			#iommu-cells = <2>;
			#global-interrupts = <1>;
			interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
		};

		intc: interrupt-controller@17800000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			interrupt-parent = <&intc>;
			#interrupt-cells = <3>;
			reg = <0x17800000 0x1000>,
			      <0x17802000 0x1000>;
		};

		a7pll: clock@17808000 {
			compatible = "qcom,sdx55-a7pll";
			reg = <0x17808000 0x1000>;
			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "bi_tcxo";
			#clock-cells = <0>;
		};

		apcs: mailbox@17810000 {
			compatible = "qcom,sdx55-apcs-gcc", "syscon";
			reg = <0x17810000 0x2000>;
			#mbox-cells = <1>;
			clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
			clock-names = "ref", "pll", "aux";
			#clock-cells = <0>;
		};

		watchdog@17817000 {
			compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt";
			reg = <0x17817000 0x1000>;
			clocks = <&sleep_clk>;
		};

		timer@17820000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x17820000 0x1000>;
			clock-frequency = <19200000>;

			frame@17821000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 7 0x4>,
					     <GIC_SPI 6 0x4>;
				reg = <0x17821000 0x1000>,
				      <0x17822000 0x1000>;
			};

			frame@17823000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 8 0x4>;
				reg = <0x17823000 0x1000>;
				status = "disabled";
			};

			frame@17824000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 9 0x4>;
				reg = <0x17824000 0x1000>;
				status = "disabled";
			};

			frame@17825000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 10 0x4>;
				reg = <0x17825000 0x1000>;
				status = "disabled";
			};

			frame@17826000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 11 0x4>;
				reg = <0x17826000 0x1000>;
				status = "disabled";
			};

			frame@17827000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 12 0x4>;
				reg = <0x17827000 0x1000>;
				status = "disabled";
			};

			frame@17828000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 13 0x4>;
				reg = <0x17828000 0x1000>;
				status = "disabled";
			};

			frame@17829000 {
				frame-number = <7>;
				interrupts = <GIC_SPI 14 0x4>;
				reg = <0x17829000 0x1000>;
				status = "disabled";
			};
		};

		apps_rsc: rsc@17830000 {
			label = "apps_rsc";
			compatible = "qcom,rpmh-rsc";
			reg = <0x17830000 0x10000>,
			    <0x17840000 0x10000>;
			reg-names = "drv-0", "drv-1";
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				   <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			qcom,tcs-offset = <0xd00>;
			qcom,drv-id = <1>;
			qcom,tcs-config = <ACTIVE_TCS  2>,
				<SLEEP_TCS   2>,
				<WAKE_TCS    2>,
				<CONTROL_TCS 1>;

			rpmhcc: clock-controller {
				compatible = "qcom,sdx65-rpmh-clk";
				#clock-cells = <1>;
				clock-names = "xo";
				clocks = <&xo_board>;
			};

			rpmhpd: power-controller {
				compatible = "qcom,sdx65-rpmhpd";
				#power-domain-cells = <1>;
				operating-points-v2 = <&rpmhpd_opp_table>;

				rpmhpd_opp_table: opp-table {
					compatible = "operating-points-v2";

					rpmhpd_opp_ret: opp1 {
						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
					};

					rpmhpd_opp_min_svs: opp2 {
						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
					};

					rpmhpd_opp_low_svs: opp3 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
					};

					rpmhpd_opp_svs: opp4 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
					};

					rpmhpd_opp_svs_l1: opp5 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					};

					rpmhpd_opp_nom: opp6 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
					};

					rpmhpd_opp_nom_l1: opp7 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
					};

					rpmhpd_opp_nom_l2: opp8 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
					};

					rpmhpd_opp_turbo: opp9 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
					};

					rpmhpd_opp_turbo_l1: opp10 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					};
				};
			};

			apps_bcm_voter: bcm-voter {
				compatible = "qcom,bcm-voter";
			};

		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			<1 12 0xf08>,
			<1 10 0xf08>,
			<1 11 0xf08>;
		clock-frequency = <19200000>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the Genmai board
 *
 * Copyright (C) 2013-14 Renesas Solutions Corp.
 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
 */

/dts-v1/;
#include "r7s72100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>

/ {
	model = "Genmai";
	compatible = "renesas,genmai", "renesas,r7s72100";

	aliases {
		serial0 = &scif2;
	};

	chosen {
		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
		stdout-path = "serial0:115200n8";
	};

	memory@8000000 {
		device_type = "memory";
		reg = <0x08000000 0x08000000>;
	};

	lbsc {
		#address-cells = <1>;
		#size-cells = <1>;
	};

	leds {
		status = "okay";
		compatible = "gpio-leds";

		led1 {
			gpios = <&port4 10 GPIO_ACTIVE_LOW>;
		};

		led2 {
			gpios = <&port4 11 GPIO_ACTIVE_LOW>;
		};
	};
};

&pinctrl {

	scif2_pins: serial2 {
		/* P3_0 as TxD2; P3_2 as RxD2 */
		pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>;
	};

	i2c2_pins: i2c2 {
		/* RIIC2: P1_4 as SCL, P1_5 as SDA */
		pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>;
	};

	ether_pins: ether {
		/* Ethernet on Ports 1,2,3,5 */
		pinmux = <RZA1_PINMUX(1, 14, 4)>,/* P1_14 = ET_COL  */
			 <RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC   */
			 <RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
			 <RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
			 <RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER  */
			 <RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV  */
			 <RZA1_PINMUX(2, 0, 2)>, /* P2_0 = ET_TXCLK */
			 <RZA1_PINMUX(2, 1, 2)>, /* P2_1 = ET_TXER  */
			 <RZA1_PINMUX(2, 2, 2)>, /* P2_2 = ET_TXEN  */
			 <RZA1_PINMUX(2, 3, 2)>, /* P2_3 = ET_CRS   */
			 <RZA1_PINMUX(2, 4, 2)>, /* P2_4 = ET_TXD0  */
			 <RZA1_PINMUX(2, 5, 2)>, /* P2_5 = ET_TXD1  */
			 <RZA1_PINMUX(2, 6, 2)>, /* P2_6 = ET_TXD2  */
			 <RZA1_PINMUX(2, 7, 2)>, /* P2_7 = ET_TXD3  */
			 <RZA1_PINMUX(2, 8, 2)>, /* P2_8 = ET_RXD0  */
			 <RZA1_PINMUX(2, 9, 2)>, /* P2_9 = ET_RXD1  */
			 <RZA1_PINMUX(2, 10, 2)>,/* P2_10 = ET_RXD2 */
			 <RZA1_PINMUX(2, 11, 2)>;/* P2_11 = ET_RXD3 */
	};
};

&extal_clk {
	clock-frequency = <13330000>;
};

&usb_x1_clk {
	clock-frequency = <48000000>;
};

&rtc_x1_clk {
	clock-frequency = <32768>;
};

&mtu2 {
	status = "okay";
};

&ether {
	pinctrl-names = "default";
	pinctrl-0 = <&ether_pins>;

	status = "okay";

	renesas,no-ether-link;
	phy-handle = <&phy0>;
	phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-idb824.2814",
			     "ethernet-phy-ieee802.3-c22";
		reg = <0>;
	};
};

&i2c2 {
	status = "okay";
	clock-frequency = <400000>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins>;

	eeprom@50 {
		compatible = "renesas,r1ex24128", "atmel,24c128";
		reg = <0x50>;
		pagesize = <64>;
	};
};

&rtc {
	status = "okay";
};

&scif2 {
	pinctrl-names = "default";
	pinctrl-0 = <&scif2_pins>;

	status = "okay";
};

&spi4 {
	status = "okay";

	codec: codec@0 {
		compatible = "wlf,wm8978";
		reg = <0>;
		spi-max-frequency = <5000000>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the GR-Peach board
 *
 * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
 * Copyright (C) 2016 Renesas Electronics
 */

/dts-v1/;
#include "r7s72100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>

/ {
	model = "GR-Peach";
	compatible = "renesas,gr-peach", "renesas,r7s72100";

	aliases {
		serial0 = &scif2;
	};

	chosen {
		bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
		stdout-path = "serial0:115200n8";
	};

	memory@20000000 {
		device_type = "memory";
		reg = <0x20000000 0x00a00000>;
	};

	lbsc {
		#address-cells = <1>;
		#size-cells = <1>;
	};

	flash@18000000 {
		compatible = "mtd-rom";
		probe-type = "map_rom";
		reg = <0x18000000 0x00800000>;
		bank-width = <4>;
		device-width = <1>;

		clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
		power-domains = <&cpg_clocks>;

		#address-cells = <1>;
		#size-cells = <1>;

		rootfs@600000 {
			label = "rootfs";
			reg = <0x00600000 0x00200000>;
		};
	};

	leds {
		status = "okay";
		compatible = "gpio-leds";

		led1 {
			gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
		};
	};
};

&pinctrl {
	scif2_pins: serial2 {
		/* P6_2 as RxD2; P6_3 as TxD2 */
		pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
	};

	ether_pins: ether {
		/* Ethernet on Ports 1,3,5,10 */
		pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL   */
			 <RZA1_PINMUX(3, 0, 2)>,  /* P3_0 = ET_TXCLK  */
			 <RZA1_PINMUX(3, 3, 2)>,  /* P3_3 = ET_MDIO   */
			 <RZA1_PINMUX(3, 4, 2)>,  /* P3_4 = ET_RXCLK  */
			 <RZA1_PINMUX(3, 5, 2)>,  /* P3_5 = ET_RXER   */
			 <RZA1_PINMUX(3, 6, 2)>,  /* P3_6 = ET_RXDV   */
			 <RZA1_PINMUX(5, 9, 2)>,  /* P5_9 = ET_MDC    */
			 <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER  */
			 <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN  */
			 <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS   */
			 <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0  */
			 <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1  */
			 <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2  */
			 <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3  */
			 <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0  */
			 <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1  */
			 <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
			 <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
	};
};

&extal_clk {
	clock-frequency = <13333000>;
};

&usb_x1_clk {
	clock-frequency = <48000000>;
};

&mtu2 {
	status = "okay";
};

&ostm0 {
	status = "okay";
};

&ostm1 {
	status = "okay";
};

&scif2 {
	pinctrl-names = "default";
	pinctrl-0 = <&scif2_pins>;

	status = "okay";
};

&ether {
	pinctrl-names = "default";
	pinctrl-0 = <&ether_pins>;

	status = "okay";

	renesas,no-ether-link;
	phy-handle = <&phy0>;

	phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-id0007.c0f0",
			     "ethernet-phy-ieee802.3-c22";
		reg = <0>;

		reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
		reset-delay-us = <5>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the RZ/A1H RSK board
 *
 * Copyright (C) 2016 Renesas Electronics
 */

/dts-v1/;
#include "r7s72100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>

/ {
	model = "RSKRZA1";
	compatible = "renesas,rskrza1", "renesas,r7s72100";

	aliases {
		serial0 = &scif2;
	};

	chosen {
		bootargs = "ignore_loglevel";
		stdout-path = "serial0:115200n8";
	};

	memory@8000000 {
		device_type = "memory";
		reg = <0x08000000 0x02000000>;
	};

	keyboard {
		compatible = "gpio-keys";

		pinctrl-names = "default";
		pinctrl-0 = <&keyboard_pins>;

		key-1 {
			interrupt-parent = <&irqc>;
			interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
			linux,code = <KEY_1>;
			label = "SW1";
			wakeup-source;
		};

		key-2 {
			interrupt-parent = <&irqc>;
			interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
			linux,code = <KEY_2>;
			label = "SW2";
			wakeup-source;
		};

		key-3 {
			interrupt-parent = <&irqc>;
			interrupts = <5 IRQ_TYPE_EDGE_BOTH>;
			linux,code = <KEY_3>;
			label = "SW3";
			wakeup-source;
		};
	};

	lbsc {
		#address-cells = <1>;
		#size-cells = <1>;
	};

	leds {
		compatible = "gpio-leds";

		led0 {
			gpios = <&port7 1 GPIO_ACTIVE_LOW>;
		};

		led1 {
			gpios = <&io_expander1 0 GPIO_ACTIVE_LOW>;
		};

		led2 {
			gpios = <&io_expander1 1 GPIO_ACTIVE_LOW>;
		};

		led3 {
			gpios = <&io_expander1 2 GPIO_ACTIVE_LOW>;
		};
	};
};

&extal_clk {
	clock-frequency = <13330000>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;
	status = "okay";

	clock-frequency = <400000>;

	io_expander1: gpio@20 {
		compatible = "onnn,cat9554";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	io_expander2: gpio@21 {
		compatible = "onnn,cat9554";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	eeprom@50 {
		compatible = "renesas,r1ex24016", "atmel,24c16";
		reg = <0x50>;
		pagesize = <16>;
	};
};

&usb_x1_clk {
	clock-frequency = <48000000>;
};

&rtc_x1_clk {
	clock-frequency = <32768>;
};

&pinctrl {
	/* RIIC ch3 (Port Expander, EEPROM (MAC Addr), Audio Codec) */
	i2c3_pins: i2c3 {
		pinmux = <RZA1_PINMUX(1, 6, 1)>,	/* RIIC3SCL */
			 <RZA1_PINMUX(1, 7, 1)>;	/* RIIC3SDA */
	};

	keyboard_pins: keyboard {
		pinmux = <RZA1_PINMUX(1, 9, 3)>,	/* IRQ3 */
			 <RZA1_PINMUX(1, 8, 3)>,	/* IRQ2 */
			 <RZA1_PINMUX(1, 11, 3)>;	/* IRQ5 */
	};

	/* Serial Console */
	scif2_pins: serial2 {
		pinmux = <RZA1_PINMUX(3, 0, 6)>,	/* TxD2 */
			 <RZA1_PINMUX(3, 2, 4)>;	/* RxD2 */
	};

	/* Ethernet */
	ether_pins: ether {
		/* Ethernet on Ports 1,2,3,5 */
		pinmux = <RZA1_PINMUX(1, 14, 4)>,	/* ET_COL   */
			 <RZA1_PINMUX(5, 9, 2)>,	/* ET_MDC   */
			 <RZA1_PINMUX(3, 3, 2)>,	/* ET_MDIO  */
			 <RZA1_PINMUX(3, 4, 2)>,	/* ET_RXCLK */
			 <RZA1_PINMUX(3, 5, 2)>,	/* ET_RXER  */
			 <RZA1_PINMUX(3, 6, 2)>,	/* ET_RXDV  */
			 <RZA1_PINMUX(2, 0, 2)>,	/* ET_TXCLK */
			 <RZA1_PINMUX(2, 1, 2)>,	/* ET_TXER  */
			 <RZA1_PINMUX(2, 2, 2)>,	/* ET_TXEN  */
			 <RZA1_PINMUX(2, 3, 2)>,	/* ET_CRS   */
			 <RZA1_PINMUX(2, 4, 2)>,	/* ET_TXD0  */
			 <RZA1_PINMUX(2, 5, 2)>,	/* ET_TXD1  */
			 <RZA1_PINMUX(2, 6, 2)>,	/* ET_TXD2  */
			 <RZA1_PINMUX(2, 7, 2)>,	/* ET_TXD3  */
			 <RZA1_PINMUX(2, 8, 2)>,	/* ET_RXD0  */
			 <RZA1_PINMUX(2, 9, 2)>,	/* ET_RXD1  */
			 <RZA1_PINMUX(2, 10, 2)>,	/* ET_RXD2  */
			 <RZA1_PINMUX(2, 11, 2)>;	/* ET_RXD3  */
	};

	/* SDHI ch1 on CN1 */
	sdhi1_pins: sdhi1 {
		pinmux = <RZA1_PINMUX(3, 8, 7)>,	/* SD_CD_1 */
			 <RZA1_PINMUX(3, 9, 7)>,	/* SD_WP_1 */
			 <RZA1_PINMUX(3, 10, 7)>,	/* SD_D1_1 */
			 <RZA1_PINMUX(3, 11, 7)>,	/* SD_D0_1 */
			 <RZA1_PINMUX(3, 12, 7)>,	/* SD_CLK_1 */
			 <RZA1_PINMUX(3, 13, 7)>,	/* SD_CMD_1 */
			 <RZA1_PINMUX(3, 14, 7)>,	/* SD_D3_1 */
			 <RZA1_PINMUX(3, 15, 7)>;	/* SD_D2_1 */
	};
};

&mtu2 {
	status = "okay";
};

&ether {
	pinctrl-names = "default";
	pinctrl-0 = <&ether_pins>;
	status = "okay";
	renesas,no-ether-link;
	phy-handle = <&phy0>;
	phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-idb824.2814",
			     "ethernet-phy-ieee802.3-c22";
		reg = <0>;
	};
};

&sdhi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&sdhi1_pins>;
	bus-width = <4>;
	status = "okay";
};

&ostm0 {
	status = "okay";
};

&ostm1 {
	status = "okay";
};

&rtc {
	status = "okay";
};

&scif2 {
	pinctrl-names = "default";
	pinctrl-0 = <&scif2_pins>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the r7s72100 SoC
 *
 * Copyright (C) 2013-14 Renesas Solutions Corp.
 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
 */

#include <dt-bindings/clock/r7s72100-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r7s72100";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
		spi4 = &spi4;
	};

	/* Fixed factor clocks */
	b_clk: b {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&cpg_clocks R7S72100_CLK_PLL>;
		clock-mult = <1>;
		clock-div = <3>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <400000000>;
			clocks = <&cpg_clocks R7S72100_CLK_I>;
			next-level-cache = <&L2>;
		};
	};

	/* External clocks */
	extal_clk: extal {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		/* If clk present, value must be set by board */
		clock-frequency = <0>;
	};

	p0_clk: p0 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&cpg_clocks R7S72100_CLK_PLL>;
		clock-mult = <1>;
		clock-div = <12>;
	};

	p1_clk: p1 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&cpg_clocks R7S72100_CLK_PLL>;
		clock-mult = <1>;
		clock-div = <6>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts-extended = <&gic GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
	};

	rtc_x1_clk: rtc_x1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		/* If clk present, value must be set by board to 32678 */
		clock-frequency = <0>;
	};

	rtc_x3_clk: rtc_x3 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		/* If clk present, value must be set by board to 4000000 */
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		L2: cache-controller@3ffff000 {
			compatible = "arm,pl310-cache";
			reg = <0x3ffff000 0x1000>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			arm,early-bresp-disable;
			arm,full-line-zero-disable;
			cache-unified;
			cache-level = <2>;
		};

		scif0: serial@e8007000 {
			compatible = "renesas,scif-r7s72100", "renesas,scif";
			reg = <0xe8007000 64>;
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
			clock-names = "fck";
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		scif1: serial@e8007800 {
			compatible = "renesas,scif-r7s72100", "renesas,scif";
			reg = <0xe8007800 64>;
			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
			clock-names = "fck";
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		scif2: serial@e8008000 {
			compatible = "renesas,scif-r7s72100", "renesas,scif";
			reg = <0xe8008000 64>;
			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
			clock-names = "fck";
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		scif3: serial@e8008800 {
			compatible = "renesas,scif-r7s72100", "renesas,scif";
			reg = <0xe8008800 64>;
			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
			clock-names = "fck";
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		scif4: serial@e8009000 {
			compatible = "renesas,scif-r7s72100", "renesas,scif";
			reg = <0xe8009000 64>;
			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
			clock-names = "fck";
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		scif5: serial@e8009800 {
			compatible = "renesas,scif-r7s72100", "renesas,scif";
			reg = <0xe8009800 64>;
			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
			clock-names = "fck";
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		scif6: serial@e800a000 {
			compatible = "renesas,scif-r7s72100", "renesas,scif";
			reg = <0xe800a000 64>;
			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
			clock-names = "fck";
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		scif7: serial@e800a800 {
			compatible = "renesas,scif-r7s72100", "renesas,scif";
			reg = <0xe800a800 64>;
			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
			clock-names = "fck";
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		spi0: spi@e800c800 {
			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
			reg = <0xe800c800 0x24>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
			power-domains = <&cpg_clocks>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi1: spi@e800d000 {
			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
			reg = <0xe800d000 0x24>;
			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
			power-domains = <&cpg_clocks>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@e800d800 {
			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
			reg = <0xe800d800 0x24>;
			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
			power-domains = <&cpg_clocks>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi3: spi@e800e000 {
			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
			reg = <0xe800e000 0x24>;
			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
			power-domains = <&cpg_clocks>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi4: spi@e800e800 {
			compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
			reg = <0xe800e800 0x24>;
			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
			power-domains = <&cpg_clocks>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		usbhs0: usb@e8010000 {
			compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
			reg = <0xe8010000 0x1a0>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp7_clks R7S72100_CLK_USB0>;
			renesas,buswait = <4>;
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		usbhs1: usb@e8207000 {
			compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
			reg = <0xe8207000 0x1a0>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp7_clks R7S72100_CLK_USB1>;
			renesas,buswait = <4>;
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		mmcif: mmc@e804c800 {
			compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
			reg = <0xe804c800 0x80>;
			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
			power-domains = <&cpg_clocks>;
			reg-io-width = <4>;
			bus-width = <8>;
			status = "disabled";
		};

		sdhi0: mmc@e804e000 {
			compatible = "renesas,sdhi-r7s72100";
			reg = <0xe804e000 0x100>;
			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
				 <&mstp12_clks R7S72100_CLK_SDHI01>;
			clock-names = "core", "cd";
			power-domains = <&cpg_clocks>;
			cap-sd-highspeed;
			cap-sdio-irq;
			status = "disabled";
		};

		sdhi1: mmc@e804e800 {
			compatible = "renesas,sdhi-r7s72100";
			reg = <0xe804e800 0x100>;
			interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
				 <&mstp12_clks R7S72100_CLK_SDHI11>;
			clock-names = "core", "cd";
			power-domains = <&cpg_clocks>;
			cap-sd-highspeed;
			cap-sdio-irq;
			status = "disabled";
		};

		gic: interrupt-controller@e8201000 {
			compatible = "arm,pl390";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0xe8201000 0x1000>,
				<0xe8202000 0x1000>;
		};

		ether: ethernet@e8203000 {
			compatible = "renesas,ether-r7s72100";
			reg = <0xe8203000 0x800>,
			      <0xe8204800 0x200>;
			interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
			power-domains = <&cpg_clocks>;
			phy-mode = "mii";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ceu: camera@e8210000 {
			reg = <0xe8210000 0x3000>;
			compatible = "renesas,r7s72100-ceu";
			interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mstp6_clks R7S72100_CLK_CEU>;
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		wdt: watchdog@fcfe0000 {
			compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
			reg = <0xfcfe0000 0x6>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&p0_clk>;
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@fcfe0000 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-cpg-clocks",
				     "renesas,rz-cpg-clocks";
			reg = <0xfcfe0000 0x18>;
			clocks = <&extal_clk>, <&usb_x1_clk>;
			clock-output-names = "pll", "i", "g";
			#power-domain-cells = <0>;
		};

		/* MSTP clocks */
		mstp3_clks: mstp3_clks@fcfe0420 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0420 4>;
			clocks = <&p0_clk>;
			clock-indices = <R7S72100_CLK_MTU2>;
			clock-output-names = "mtu2";
		};

		mstp4_clks: mstp4_clks@fcfe0424 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0424 4>;
			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
				 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
			clock-indices = <
				R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
				R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
			>;
			clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
		};

		mstp5_clks: mstp5_clks@fcfe0428 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0428 4>;
			clocks = <&p0_clk>, <&p0_clk>;
			clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
			clock-output-names = "ostm0", "ostm1";
		};

		mstp6_clks: mstp6_clks@fcfe042c {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe042c 4>;
			clocks = <&b_clk>, <&p0_clk>;
			clock-indices = <R7S72100_CLK_CEU R7S72100_CLK_RTC>;
			clock-output-names = "ceu", "rtc";
		};

		mstp7_clks: mstp7_clks@fcfe0430 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0430 4>;
			clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
			clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
			clock-output-names = "ether", "usb0", "usb1";
		};

		mstp8_clks: mstp8_clks@fcfe0434 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0434 4>;
			clocks = <&p1_clk>;
			clock-indices = <R7S72100_CLK_MMCIF>;
			clock-output-names = "mmcif";
		};

		mstp9_clks: mstp9_clks@fcfe0438 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0438 4>;
			clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>;
			clock-indices = <
				R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
				R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1
			>;
			clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";
		};

		mstp10_clks: mstp10_clks@fcfe043c {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe043c 4>;
			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
				 <&p1_clk>;
			clock-indices = <
				R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
				R7S72100_CLK_SPI4
			>;
			clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
		};
		mstp12_clks: mstp12_clks@fcfe0444 {
			#clock-cells = <1>;
			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0xfcfe0444 4>;
			clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
			clock-indices = <
				R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
				R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
			>;
			clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
		};

		pinctrl: pinctrl@fcfe3000 {
			compatible = "renesas,r7s72100-ports";

			reg = <0xfcfe3000 0x4230>;

			port0: gpio-0 {
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl 0 0 6>;
			};

			port1: gpio-1 {
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl 0 16 16>;
			};

			port2: gpio-2 {
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl 0 32 16>;
			};

			port3: gpio-3 {
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl 0 48 16>;
			};

			port4: gpio-4 {
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl 0 64 16>;
			};

			port5: gpio-5 {
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl 0 80 11>;
			};

			port6: gpio-6 {
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl 0 96 16>;
			};

			port7: gpio-7 {
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl 0 112 16>;
			};

			port8: gpio-8 {
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl 0 128 16>;
			};

			port9: gpio-9 {
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl 0 144 8>;
			};

			port10: gpio-10 {
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl 0 160 16>;
			};

			port11: gpio-11 {
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&pinctrl 0 176 16>;
			};
		};

		ostm0: timer@fcfec000 {
			compatible = "renesas,r7s72100-ostm", "renesas,ostm";
			reg = <0xfcfec000 0x30>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
			clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		ostm1: timer@fcfec400 {
			compatible = "renesas,r7s72100-ostm", "renesas,ostm";
			reg = <0xfcfec400 0x30>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
			clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		i2c0: i2c@fcfee000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
			reg = <0xfcfee000 0x44>;
			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
			clock-frequency = <100000>;
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		i2c1: i2c@fcfee400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
			reg = <0xfcfee400 0x44>;
			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
			clock-frequency = <100000>;
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		i2c2: i2c@fcfee800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
			reg = <0xfcfee800 0x44>;
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
			clock-frequency = <100000>;
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		i2c3: i2c@fcfeec00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
			reg = <0xfcfeec00 0x44>;
			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
			clock-frequency = <100000>;
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		irqc: interrupt-controller@fcfef800 {
			compatible = "renesas,r7s72100-irqc",
				     "renesas,rza1-irqc";
			#interrupt-cells = <2>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0xfcfef800 0x6>;
			interrupt-map =
				<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
				<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
				<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-map-mask = <7 0>;
		};

		mtu2: timer@fcff0000 {
			compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
			reg = <0xfcff0000 0x400>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tgi0a";
			clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
			clock-names = "fck";
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};

		rtc: rtc@fcff1000 {
			compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
			reg = <0xfcff1000 0x2e>;
			interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "alarm", "period", "carry";
			clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
				 <&rtc_x3_clk>, <&extal_clk>;
			clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
			power-domains = <&cpg_clocks>;
			status = "disabled";
		};
	};

	usb_x1_clk: usb_x1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		/* If clk present, value must be set by board */
		clock-frequency = <0>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the RZA2MEVB board
 *
 * Copyright (C) 2018 Renesas Electronics
 *
 * As upstream Linux does not support XIP, it cannot run in 8 MiB of HyperRAM.
 * Hence the 64 MiB of SDRAM on the sub-board needs to be enabled, which has
 * the following ramifications:
 *   - SCIF4 connected to the on-board USB-serial can no longer be used as the
 *     serial console,
 *   - Instead, SCIF2 is used as the serial console, by connecting a 3.3V TTL
 *     USB-to-Serial adapter to the CMOS camera connector:
 *       - RXD = CN17-9,
 *       - TXD = CN17-10,
 *       - GND = CN17-2 or CN17-17,
 *   - The first Ethernet channel can no longer be used,
 *   - USB Channel 1 loses the overcurrent input signal.
 *
 * Please make sure your sub-board matches the following switch settings:
 *
 *           SW6                SW6-1 set to SDRAM
 *  ON                          SW6-2 set to Audio
 * +---------------------+      SW6-3 set to DRP
 * | =   =   = = =       |      SW6-4 set to CEU
 * |   =   =             |      SW6-5 set to Ether2
 * | 1 2 3 4 5 6 7 8 9 0 |      SW6-6 set to VDC6
 * +---------------------+      SW6-7 set to VDC6
 */

/dts-v1/;
#include "r7s9210.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>

/ {
	model = "RZA2MEVB";
	compatible = "renesas,rza2mevb", "renesas,r7s9210";

	aliases {
		serial0 = &scif2;
		ethernet0 = &ether1;
	};

	chosen {
		bootargs = "ignore_loglevel";
		stdout-path = "serial0:115200n8";
	};

	keyboard {
		compatible = "gpio-keys";

		pinctrl-names = "default";
		pinctrl-0 = <&keyboard_pins>;

		key-3 {
			interrupt-parent = <&irqc>;
			interrupts = <0 IRQ_TYPE_EDGE_BOTH>;
			linux,code = <KEY_3>;
			label = "SW3";
			wakeup-source;
		};
	};

	lbsc {
		#address-cells = <1>;
		#size-cells = <1>;
	};

	leds {
		compatible = "gpio-leds";

		led-red {
			gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
		};
		led-green {
			gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>;
		};
	};

	memory@c000000 {
		device_type = "memory";
		reg = <0x0c000000 0x04000000>;	/* SDRAM */
	};
};

&ehci0 {
	status = "okay";
};

&ehci1 {
	status = "okay";
};

&ether1 {
	pinctrl-names = "default";
	pinctrl-0 = <&eth1_pins>;
	status = "okay";
	renesas,no-ether-link;
	phy-handle = <&phy1>;
	phy1: ethernet-phy@1 {
		compatible = "ethernet-phy-id001c.c816",
			     "ethernet-phy-ieee802.3-c22";
		reg = <0>;
	};
};

/* EXTAL */
&extal_clk {
	clock-frequency = <24000000>;	/* 24MHz */
};

&i2c3 {
	status = "okay";
	clock-frequency = <400000>;

	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_pins>;

	eeprom@50 {
		compatible = "renesas,r1ex24128", "atmel,24c128";
		reg = <0x50>;
		pagesize = <64>;
	};
};

/* High resolution System tick timers */
&ostm0 {
	status = "okay";
};

&ostm1 {
	status = "okay";
};

&pinctrl {
	eth0_pins: eth0 {
		pinmux = <RZA2_PINMUX(PORTE, 0, 7)>, /* REF50CK0 */
			 <RZA2_PINMUX(PORT6, 1, 7)>, /* RMMI0_TXDEN */
			 <RZA2_PINMUX(PORT6, 2, 7)>, /* RMII0_TXD0 */
			 <RZA2_PINMUX(PORT6, 3, 7)>, /* RMII0_TXD1 */
			 <RZA2_PINMUX(PORTE, 4, 7)>, /* RMII0_CRSDV */
			 <RZA2_PINMUX(PORTE, 1, 7)>, /* RMII0_RXD0 */
			 <RZA2_PINMUX(PORTE, 2, 7)>, /* RMII0_RXD1 */
			 <RZA2_PINMUX(PORTE, 3, 7)>, /* RMII0_RXER */
			 <RZA2_PINMUX(PORTE, 5, 1)>, /* ET0_MDC */
			 <RZA2_PINMUX(PORTE, 6, 1)>, /* ET0_MDIO */
			 <RZA2_PINMUX(PORTL, 0, 5)>; /* IRQ4 */
	};

	eth1_pins: eth1 {
		pinmux = <RZA2_PINMUX(PORTK, 3, 7)>, /* REF50CK1 */
			 <RZA2_PINMUX(PORTK, 0, 7)>, /* RMMI1_TXDEN */
			 <RZA2_PINMUX(PORTK, 1, 7)>, /* RMII1_TXD0 */
			 <RZA2_PINMUX(PORTK, 2, 7)>, /* RMII1_TXD1 */
			 <RZA2_PINMUX(PORT3, 2, 7)>, /* RMII1_CRSDV */
			 <RZA2_PINMUX(PORTK, 4, 7)>, /* RMII1_RXD0 */
			 <RZA2_PINMUX(PORT3, 5, 7)>, /* RMII1_RXD1 */
			 <RZA2_PINMUX(PORT3, 1, 7)>, /* RMII1_RXER */
			 <RZA2_PINMUX(PORT3, 3, 1)>, /* ET1_MDC */
			 <RZA2_PINMUX(PORT3, 4, 1)>, /* ET1_MDIO */
			 <RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */
	};

	i2c3_pins: i2c3 {
		pinmux = <RZA2_PINMUX(PORTD, 6, 1)>,	/* RIIC3SCL */
			 <RZA2_PINMUX(PORTD, 7, 1)>;	/* RIIC3SDA */
	};

	keyboard_pins: keyboard {
		pinmux = <RZA2_PINMUX(PORTJ, 1, 6)>;	/* IRQ0 */
	};

	/* Serial Console */
	scif2_pins: serial2 {
		pinmux = <RZA2_PINMUX(PORTE, 2, 3)>,	/* TxD2 */
			 <RZA2_PINMUX(PORTE, 1, 3)>;	/* RxD2 */
	};

	sdhi0_pins: sdhi0 {
		pinmux = <RZA2_PINMUX(PORT5, 0, 3)>,	/* SD0_CD */
			 <RZA2_PINMUX(PORT5, 1, 3)>;	/* SD0_WP */
	};

	sdhi1_pins: sdhi1 {
		pinmux = <RZA2_PINMUX(PORT5, 4, 3)>,	/* SD1_CD */
			 <RZA2_PINMUX(PORT5, 5, 3)>;	/* SD1_WP */
	};

	usb0_pins: usb0 {
		pinmux = <RZA2_PINMUX(PORT5, 2, 3)>,	/* VBUSIN0 */
			 <RZA2_PINMUX(PORTC, 6, 1)>,	/* VBUSEN0 */
			 <RZA2_PINMUX(PORTC, 7, 1)>;	/* OVRCUR0 */
	};

	usb1_pins: usb1 {
		pinmux = <RZA2_PINMUX(PORTC, 0, 1)>,	/* VBUSIN1 */
			 <RZA2_PINMUX(PORTC, 5, 1)>;	/* VBUSEN1 */
	};
};

/* RTC_X1 */
&rtc_x1_clk {
	clock-frequency = <32768>;
};

/* Serial Console */
&scif2 {
	pinctrl-names = "default";
	pinctrl-0 = <&scif2_pins>;

	status = "okay";
};

&sdhi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&sdhi0_pins>;
	bus-width = <4>;
	status = "okay";
};

&sdhi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&sdhi1_pins>;
	bus-width = <4>;
	status = "okay";
};

/* USB-0 as Host */
&usb2_phy0 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb0_pins>;
	dr_mode = "host";	/* Requires JP3 to be fitted */
	status = "okay";
};

/* USB-1 as Host */
&usb2_phy1 {
	pinctrl-names = "default";
	pinctrl-0 = <&usb1_pins>;
	dr_mode = "host";
	status = "okay";
};

/* USB_X1 */
&usb_x1_clk {
	clock-frequency = <48000000>;
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the R7S9210 SoC
 *
 * Copyright (C) 2018 Renesas Electronics Corporation
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r7s9210-cpg-mssr.h>

/ {
	compatible = "renesas,r7s9210";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	/* External clocks */
	extal_clk: extal {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		/* Value must be set by board */
		clock-frequency = <0>;
	};

	rtc_x1_clk: rtc_x1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		/* If clk present, value (32678) must be set by board */
		clock-frequency = <0>;
	};

	usb_x1_clk: usb_x1 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		/* If clk present, value (48000000) must be set by board */
		clock-frequency = <0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <528000000>;
			next-level-cache = <&L2>;
		};
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		L2: cache-controller@1f003000 {
			compatible = "arm,pl310-cache";
			reg = <0x1f003000 0x1000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			arm,early-bresp-disable;
			arm,full-line-zero-disable;
			cache-unified;
			cache-level = <2>;
		};

		scif0: serial@e8007000 {
			compatible = "renesas,scif-r7s9210";
			reg = <0xe8007000 0x18>;
			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD 47>;
			clock-names = "fck";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif1: serial@e8007800 {
			compatible = "renesas,scif-r7s9210";
			reg = <0xe8007800 0x18>;
			interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD 46>;
			clock-names = "fck";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif2: serial@e8008000 {
			compatible = "renesas,scif-r7s9210";
			reg = <0xe8008000 0x18>;
			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD 45>;
			clock-names = "fck";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif3: serial@e8008800 {
			compatible = "renesas,scif-r7s9210";
			reg = <0xe8008800 0x18>;
			interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD 44>;
			clock-names = "fck";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif4: serial@e8009000 {
			compatible = "renesas,scif-r7s9210";
			reg = <0xe8009000 0x18>;
			interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD 43>;
			clock-names = "fck";
			power-domains = <&cpg>;
			status = "disabled";
		};

		spi0: spi@e800c800 {
			compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
			reg = <0xe800c800 0x24>;
			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&cpg CPG_MOD 97>;
			power-domains = <&cpg>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi1: spi@e800d000 {
			compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
			reg = <0xe800d000 0x24>;
			interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&cpg CPG_MOD 96>;
			power-domains = <&cpg>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@e800d800 {
			compatible = "renesas,rspi-r7s9210", "renesas,rspi-rz";
			reg = <0xe800d800 0x24>;
			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&cpg CPG_MOD 95>;
			power-domains = <&cpg>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ether0: ethernet@e8204000 {
			compatible = "renesas,ether-r7s9210";
			reg = <0xe8204000 0x200>;
			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 65>;
			power-domains = <&cpg>;

			phy-mode = "rmii";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ether1: ethernet@e8204200 {
			compatible = "renesas,ether-r7s9210";
			reg = <0xe8204200 0x200>;
			interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 64>;
			power-domains = <&cpg>;
			phy-mode = "rmii";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c0: i2c@e803a000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
			reg = <0xe803a000 0x44>;
			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 87>;
			power-domains = <&cpg>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c1: i2c@e803a400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
			reg = <0xe803a400 0x44>;
			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 86>;
			power-domains = <&cpg>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c2: i2c@e803a800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
			reg = <0xe803a800 0x44>;
			interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 85>;
			power-domains = <&cpg>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		i2c3: i2c@e803ac00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r7s9210", "renesas,riic-rz";
			reg = <0xe803ac00 0x44>;
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD 84>;
			power-domains = <&cpg>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		ostm0: timer@e803b000 {
			compatible = "renesas,r7s9210-ostm", "renesas,ostm";
			reg = <0xe803b000 0x30>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 36>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm1: timer@e803c000 {
			compatible = "renesas,r7s9210-ostm", "renesas,ostm";
			reg = <0xe803c000 0x30>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 35>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm2: timer@e803d000 {
			compatible = "renesas,r7s9210-ostm", "renesas,ostm";
			reg = <0xe803d000 0x30>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD 34>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ohci0: usb@e8218000 {
			compatible = "generic-ohci";
			reg = <0xe8218000 0x100>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 61>;
			phys = <&usb2_phy0>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		ehci0: usb@e8218100 {
			compatible = "generic-ehci";
			reg = <0xe8218100 0x100>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 61>;
			phys = <&usb2_phy0>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		usb2_phy0: usb-phy@e8218200 {
			compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy";
			reg = <0xe8218200 0x700>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 61>, <&usb_x1_clk>;
			clock-names = "fck", "usb_x1";
			power-domains = <&cpg>;
			#phy-cells = <0>;
			status = "disabled";
		};

		usbhs0: usb@e8219000 {
			compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs";
			reg = <0xe8219000 0x724>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 61>;
			renesas,buswait = <7>;
			phys = <&usb2_phy0>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		ohci1: usb@e821a000 {
			compatible = "generic-ohci";
			reg = <0xe821a000 0x100>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 60>;
			phys = <&usb2_phy1>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		ehci1: usb@e821a100 {
			compatible = "generic-ehci";
			reg = <0xe821a100 0x100>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 60>;
			phys = <&usb2_phy1>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		usb2_phy1: usb-phy@e821a200 {
			compatible = "renesas,usb2-phy-r7s9210", "renesas,rcar-gen3-usb2-phy";
			reg = <0xe821a200 0x700>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 60>, <&usb_x1_clk>;
			clock-names = "fck", "usb_x1";
			power-domains = <&cpg>;
			#phy-cells = <0>;
			status = "disabled";
		};

		usbhs1: usb@e821b000 {
			compatible = "renesas,usbhs-r7s9210", "renesas,rza2-usbhs";
			reg = <0xe821b000 0x724>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 60>;
			renesas,buswait = <7>;
			phys = <&usb2_phy1>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		sdhi0: mmc@e8228000 {
			compatible = "renesas,sdhi-r7s9210";
			reg = <0xe8228000 0x8c0>;
			interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>;
			clock-names = "core", "cd";
			power-domains = <&cpg>;
			cap-sd-highspeed;
			cap-sdio-irq;
			status = "disabled";
		};

		sdhi1: mmc@e822a000 {
			compatible = "renesas,sdhi-r7s9210";
			reg = <0xe822a000 0x8c0>;
			interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>;
			clock-names = "core", "cd";
			power-domains = <&cpg>;
			cap-sd-highspeed;
			cap-sdio-irq;
			status = "disabled";
		};

		gic: interrupt-controller@e8221000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0xe8221000 0x1000>,
			      <0xe8222000 0x1000>;
		};

		cpg: clock-controller@fcfe0010 {
			compatible = "renesas,r7s9210-cpg-mssr";
			reg = <0xfcfe0010 0x455>;
			clocks = <&extal_clk>;
			clock-names = "extal";
			#clock-cells = <2>;
			#power-domain-cells = <0>;
		};

		wdt: watchdog@fcfe7000 {
			compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt";
			reg = <0xfcfe7000 0x26>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_CORE R7S9210_CLK_P0>;
		};

		bsid: chipid@fcfe8004 {
			compatible = "renesas,bsid";
			reg = <0xfcfe8004 4>;
		};

		irqc: interrupt-controller@fcfef800 {
			compatible = "renesas,r7s9210-irqc",
				     "renesas,rza1-irqc";
			#interrupt-cells = <2>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0xfcfef800 0x6>;
			interrupt-map =
				<0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				<1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
				<2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
				<3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
				<4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				<5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
				<6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				<7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-map-mask = <7 0>;
		};

		pinctrl: pinctrl@fcffe000 {
			compatible = "renesas,r7s9210-pinctrl";
			reg = <0xfcffe000 0x1000>;

			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 176>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the APE6EVM board
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 */

/dts-v1/;
#include "r8a73a4.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "APE6EVM";
	compatible = "renesas,ape6evm", "renesas,r8a73a4";

	aliases {
		serial0 = &scifa0;
	};

	chosen {
		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x40000000>;
	};

	memory@200000000 {
		device_type = "memory";
		reg = <2 0x00000000 0 0x40000000>;
	};

	vcc_mmc0: regulator-mmc0 {
		compatible = "regulator-fixed";
		regulator-name = "MMC0 Vcc";
		regulator-min-microvolt = <2800000>;
		regulator-max-microvolt = <2800000>;
		regulator-always-on;
	};

	vcc_sdhi0: regulator-sdhi0 {
		compatible = "regulator-fixed";

		regulator-name = "SDHI0 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&pfc 76 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	/* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */
	ape6evm_fixed_1v8: regulator-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	ape6evm_fixed_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	leds {
		compatible = "gpio-leds";
		led1 {
			gpios = <&pfc 28 GPIO_ACTIVE_HIGH>;
			label = "GNSS_EN";
		};
		led2 {
			gpios = <&pfc 126 GPIO_ACTIVE_HIGH>;
			label = "NFC_NRST";
		};
		led3 {
			gpios = <&pfc 132 GPIO_ACTIVE_HIGH>;
			label = "GNSS_NRST";
		};
		led4 {
			gpios = <&pfc 232 GPIO_ACTIVE_HIGH>;
			label = "BT_WAKEUP";
		};
		led5 {
			gpios = <&pfc 250 GPIO_ACTIVE_HIGH>;
			label = "STROBE";
		};
		led6 {
			gpios = <&pfc 288 GPIO_ACTIVE_HIGH>;
			label = "BBRESETOUT";
		};
	};

	keyboard {
		compatible = "gpio-keys";

		pinctrl-names = "default";
		pinctrl-0 = <&keyboard_pins>;

		zero-key {
			gpios = <&pfc 324 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_0>;
			label = "S16";
			wakeup-source;
		};

		menu-key {
			gpios = <&pfc 325 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_MENU>;
			label = "S17";
		};

		home-key {
			gpios = <&pfc 326 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_HOME>;
			label = "S18";
		};

		back-key {
			gpios = <&pfc 327 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_BACK>;
			label = "S19";
		};

		volup-key {
			gpios = <&pfc 328 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_VOLUMEUP>;
			label = "S20";
		};

		voldown-key {
			gpios = <&pfc 329 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_VOLUMEDOWN>;
			label = "S21";
		};
	};
};

&i2c5 {
	status = "okay";
	vdd_dvfs: regulator@1b {
		compatible = "maxim,max8973";
		reg = <0x1b>;

		regulator-min-microvolt = <935000>;
		regulator-max-microvolt = <1200000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&cpu0 {
	cpu0-supply = <&vdd_dvfs>;
	operating-points = <1950000 1115000>,	/* kHz  uV */
			   <1462500  995000>;
	voltage-tolerance = <1>; /* 1% */
};

&bsc {
	flash@0 {
		compatible = "cfi-flash", "mtd-rom";
		reg = <0x0 0x08000000>;
		bank-width = <2>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "uboot";
				reg = <0x00000000 0x00040000>;
				read-only;
			};
			partition@40000 {
				label = "uboot-env";
				reg = <0x00040000 0x00040000>;
				read-only;
			};
			partition@80000 {
				label = "flash";
				reg = <0x00080000 0x07f80000>;
			};
		};
	};

	ethernet@8000000 {
		compatible = "smsc,lan9220", "smsc,lan9115";
		reg = <0x08000000 0x1000>;
		interrupt-parent = <&irqc1>;
		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
		phy-mode = "mii";
		reg-io-width = <4>;
		smsc,irq-active-high;
		smsc,irq-push-pull;
		reset-gpios = <&pfc 270 GPIO_ACTIVE_LOW>;
		vdd33a-supply = <&ape6evm_fixed_3v3>;
		vddvario-supply = <&ape6evm_fixed_1v8>;
	};
};

&cmt1 {
	status = "okay";
};

&pfc {
	scifa0_pins: scifa0 {
		groups = "scifa0_data";
		function = "scifa0";
	};

	mmc0_pins: mmc0 {
		groups = "mmc0_data8", "mmc0_ctrl";
		function = "mmc0";
	};

	sdhi0_pins: sd0 {
		groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
		function = "sdhi0";
	};

	sdhi1_pins: sd1 {
		groups = "sdhi1_data4", "sdhi1_ctrl";
		function = "sdhi1";
	};

	keyboard_pins: keyboard {
		pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328",
		       "PORT329";
		bias-pull-up;
	};
};

&mmcif0 {
	vmmc-supply = <&vcc_mmc0>;
	bus-width = <8>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc0_pins>;
	status = "okay";
};

&scifa0 {
	pinctrl-0 = <&scifa0_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&sdhi0 {
	vmmc-supply = <&vcc_sdhi0>;
	bus-width = <4>;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdhi0_pins>;
	status = "okay";
};

&sdhi1 {
	vmmc-supply = <&ape6evm_fixed_3v3>;
	bus-width = <4>;
	broken-cd;
	disable-wp;
	pinctrl-names = "default";
	pinctrl-0 = <&sdhi1_pins>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the r8a73a4 SoC
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Magnus Damm
 */

#include <dt-bindings/clock/r8a73a4-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a73a4";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			clocks = <&cpg_clocks R8A73A4_CLK_Z>;
			clock-frequency = <1500000000>;
			power-domains = <&pd_a2sl>;
			next-level-cache = <&L2_CA15>;
		};

		L2_CA15: cache-controller-0 {
			compatible = "cache";
			clocks = <&cpg_clocks R8A73A4_CLK_Z>;
			power-domains = <&pd_a3sm>;
			cache-unified;
			cache-level = <2>;
		};

		L2_CA7: cache-controller-1 {
			compatible = "cache";
			clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
			power-domains = <&pd_a3km>;
			cache-unified;
			cache-level = <2>;
		};
	};

	ptm {
		compatible = "arm,coresight-etm3x";
		power-domains = <&pd_d4>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	dbsc1: memory-controller@e6790000 {
		compatible = "renesas,dbsc-r8a73a4";
		reg = <0 0xe6790000 0 0x10000>;
		power-domains = <&pd_a3bc>;
	};

	dbsc2: memory-controller@e67a0000 {
		compatible = "renesas,dbsc-r8a73a4";
		reg = <0 0xe67a0000 0 0x10000>;
		power-domains = <&pd_a3bc>;
	};

	i2c5: i2c@e60b0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
		reg = <0 0xe60b0000 0 0x428>;
		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
		power-domains = <&pd_a3sp>;

		status = "disabled";
	};

	cmt1: timer@e6130000 {
		compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
		reg = <0 0xe6130000 0 0x1004>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
		clock-names = "fck";
		power-domains = <&pd_c5>;
		status = "disabled";
	};

	irqc0: interrupt-controller@e61c0000 {
		compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0 0xe61c0000 0 0x200>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
		power-domains = <&pd_c4>;
	};

	irqc1: interrupt-controller@e61c0200 {
		compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0 0xe61c0200 0 0x200>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
		power-domains = <&pd_c4>;
	};

	pfc: pinctrl@e6050000 {
		compatible = "renesas,pfc-r8a73a4";
		reg = <0 0xe6050000 0 0x9000>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges =
			<&pfc 0 0 31>, <&pfc 32 32 9>,
			<&pfc 64 64 22>, <&pfc 96 96 31>,
			<&pfc 128 128 7>, <&pfc 160 160 19>,
			<&pfc 192 192 31>, <&pfc 224 224 27>,
			<&pfc 256 256 28>, <&pfc 288 288 21>,
			<&pfc 320 320 10>;
		interrupts-extended =
			<&irqc0  0 0>, <&irqc0  1 0>, <&irqc0  2 0>, <&irqc0  3 0>,
			<&irqc0  4 0>, <&irqc0  5 0>, <&irqc0  6 0>, <&irqc0  7 0>,
			<&irqc0  8 0>, <&irqc0  9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
			<&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
			<&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
			<&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
			<&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
			<&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
			<&irqc1  0 0>, <&irqc1  1 0>, <&irqc1  2 0>, <&irqc1  3 0>,
			<&irqc1  4 0>, <&irqc1  5 0>, <&irqc1  6 0>, <&irqc1  7 0>,
			<&irqc1  8 0>, <&irqc1  9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
			<&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
			<&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
			<&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
			<&irqc1 24 0>, <&irqc1 25 0>;
		power-domains = <&pd_c5>;
	};

	thermal@e61f0000 {
		compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
			 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
		power-domains = <&pd_c5>;
	};

	i2c0: i2c@e6500000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
		reg = <0 0xe6500000 0 0x428>;
		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c1: i2c@e6510000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
		reg = <0 0xe6510000 0 0x428>;
		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c2: i2c@e6520000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
		reg = <0 0xe6520000 0 0x428>;
		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c3: i2c@e6530000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
		reg = <0 0xe6530000 0 0x428>;
		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c4: i2c@e6540000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
		reg = <0 0xe6540000 0 0x428>;
		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c6: i2c@e6550000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
		reg = <0 0xe6550000 0 0x428>;
		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c7: i2c@e6560000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
		reg = <0 0xe6560000 0 0x428>;
		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	i2c8: i2c@e6570000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
		reg = <0 0xe6570000 0 0x428>;
		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifb0: serial@e6c20000 {
		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
		reg = <0 0xe6c20000 0 0x100>;
		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifb1: serial@e6c30000 {
		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
		reg = <0 0xe6c30000 0 0x100>;
		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa0: serial@e6c40000 {
		compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
		reg = <0 0xe6c40000 0 0x100>;
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifa1: serial@e6c50000 {
		compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
		reg = <0 0xe6c50000 0 0x100>;
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifb2: serial@e6ce0000 {
		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
		reg = <0 0xe6ce0000 0 0x100>;
		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
		clock-names = "fck";
		power-domains = <&pd_a3sp>;
		status = "disabled";
	};

	scifb3: serial@e6cf0000 {
		compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
		reg = <0 0xe6cf0000 0 0x100>;
		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
		clock-names = "fck";
		power-domains = <&pd_c4>;
		status = "disabled";
	};

	sdhi0: mmc@ee100000 {
		compatible = "renesas,sdhi-r8a73a4";
		reg = <0 0xee100000 0 0x100>;
		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
		power-domains = <&pd_a3sp>;
		cap-sd-highspeed;
		status = "disabled";
	};

	sdhi1: mmc@ee120000 {
		compatible = "renesas,sdhi-r8a73a4";
		reg = <0 0xee120000 0 0x100>;
		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
		power-domains = <&pd_a3sp>;
		cap-sd-highspeed;
		status = "disabled";
	};

	sdhi2: mmc@ee140000 {
		compatible = "renesas,sdhi-r8a73a4";
		reg = <0 0xee140000 0 0x100>;
		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
		power-domains = <&pd_a3sp>;
		cap-sd-highspeed;
		status = "disabled";
	};

	mmcif0: mmc@ee200000 {
		compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
		reg = <0 0xee200000 0 0x80>;
		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
		power-domains = <&pd_a3sp>;
		reg-io-width = <4>;
		status = "disabled";
	};

	mmcif1: mmc@ee220000 {
		compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
		reg = <0 0xee220000 0 0x80>;
		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
		power-domains = <&pd_a3sp>;
		reg-io-width = <4>;
		status = "disabled";
	};

	gic: interrupt-controller@f1001000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0xf1001000 0 0x1000>,
			<0 0xf1002000 0 0x2000>,
			<0 0xf1004000 0 0x2000>,
			<0 0xf1006000 0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
		clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
		clock-names = "clk";
		power-domains = <&pd_c4>;
	};

	bsc: bus@fec10000 {
		compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
			     "simple-pm-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0x20000000>;
		reg = <0 0xfec10000 0 0x400>;
		clocks = <&zb_clk>;
		power-domains = <&pd_c4>;
	};

	clocks {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* External root clocks */
		extalr_clk: extalr {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
		extal1_clk: extal1 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
		extal2_clk: extal2 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <48000000>;
		};
		fsiack_clk: fsiack {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overridden by the board. */
			clock-frequency = <0>;
		};
		fsibck_clk: fsibck {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overridden by the board. */
			clock-frequency = <0>;
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@e6150000 {
			compatible = "renesas,r8a73a4-cpg-clocks";
			reg = <0 0xe6150000 0 0x10000>;
			clocks = <&extal1_clk>, <&extal2_clk>;
			#clock-cells = <1>;
			clock-output-names = "main", "pll0", "pll1", "pll2",
					     "pll2s", "pll2h", "z", "z2",
					     "i", "m3", "b", "m1", "m2",
					     "zx", "zs", "hp";
		};

		/* Variable factor clocks (DIV6) */
		zb_clk: zb_clk@e6150010 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150010 0 4>;
			clocks = <&pll1_div2_clk>, <0>,
				 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
			#clock-cells = <0>;
			clock-output-names = "zb";
		};
		sdhi0_clk: sdhi0ck@e6150074 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150074 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <0>, <&extal2_clk>;
			#clock-cells = <0>;
		};
		sdhi1_clk: sdhi1ck@e6150078 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150078 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <0>, <&extal2_clk>;
			#clock-cells = <0>;
		};
		sdhi2_clk: sdhi2ck@e615007c {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe615007c 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <0>, <&extal2_clk>;
			#clock-cells = <0>;
		};
		mmc0_clk: mmc0@e6150240 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150240 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <0>, <&extal2_clk>;
			#clock-cells = <0>;
		};
		mmc1_clk: mmc1@e6150244 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150244 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <0>, <&extal2_clk>;
			#clock-cells = <0>;
		};
		vclk1_clk: vclk1@e6150008 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150008 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <0>, <&extal2_clk>, <&main_div2_clk>,
				 <&extalr_clk>, <0>, <0>;
			#clock-cells = <0>;
		};
		vclk2_clk: vclk2@e615000c {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe615000c 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <0>, <&extal2_clk>, <&main_div2_clk>,
				 <&extalr_clk>, <0>, <0>;
			#clock-cells = <0>;
		};
		vclk3_clk: vclk3@e615001c {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe615001c 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <0>, <&extal2_clk>, <&main_div2_clk>,
				 <&extalr_clk>, <0>, <0>;
			#clock-cells = <0>;
		};
		vclk4_clk: vclk4@e6150014 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150014 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <0>, <&extal2_clk>, <&main_div2_clk>,
				 <&extalr_clk>, <0>, <0>;
			#clock-cells = <0>;
		};
		vclk5_clk: vclk5@e6150034 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150034 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <0>, <&extal2_clk>, <&main_div2_clk>,
				 <&extalr_clk>, <0>, <0>;
			#clock-cells = <0>;
		};
		fsia_clk: fsia@e6150018 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150018 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <&fsiack_clk>, <0>;
			#clock-cells = <0>;
		};
		fsib_clk: fsib@e6150090 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150090 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <&fsibck_clk>, <0>;
			#clock-cells = <0>;
		};
		mp_clk: mp@e6150080 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150080 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <&extal2_clk>, <&extal2_clk>;
			#clock-cells = <0>;
		};
		m4_clk: m4@e6150098 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150098 0 4>;
			clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
			#clock-cells = <0>;
		};
		hsi_clk: hsi@e615026c {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe615026c 0 4>;
			clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
				 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
			#clock-cells = <0>;
		};
		spuv_clk: spuv@e6150094 {
			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150094 0 4>;
			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
				 <&extal2_clk>, <&extal2_clk>;
			#clock-cells = <0>;
		};

		/* Fixed factor clocks */
		main_div2_clk: main_div2 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};
		pll0_div2_clk: pll0_div2 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};
		pll1_div2_clk: pll1_div2 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};
		extal1_div2_clk: extal1_div2 {
			compatible = "fixed-factor-clock";
			clocks = <&extal1_clk>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		/* Gate clocks */
		mstp2_clks: mstp2_clks@e6150138 {
			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
				 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
			#clock-cells = <1>;
			clock-indices = <
				R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
				R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
				R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
				R8A73A4_CLK_DMAC
			>;
			clock-output-names =
				"scifa0", "scifa1", "scifb0", "scifb1",
				"scifb2", "scifb3", "dmac";
		};
		mstp3_clks: mstp3_clks@e615013c {
			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
			clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
				 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
				 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
				 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
				 R8A73A4_CLK_HP>, <&cpg_clocks
				 R8A73A4_CLK_HP>, <&extalr_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
				R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
				R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
				R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
				R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
				R8A73A4_CLK_CMT1
			>;
			clock-output-names =
				"iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
				"mmcif0", "iic6", "iic7", "iic0", "iic1",
				"cmt1";
		};
		mstp4_clks: mstp4_clks@e6150140 {
			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
			clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
				 <&main_div2_clk>,
				 <&cpg_clocks R8A73A4_CLK_HP>,
				 <&cpg_clocks R8A73A4_CLK_HP>;
			#clock-cells = <1>;
			clock-indices = <
				R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
				R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
				R8A73A4_CLK_IIC3
			>;
			clock-output-names =
				"irqc", "intc-sys", "iic5", "iic4", "iic3";
		};
		mstp5_clks: mstp5_clks@e6150144 {
			compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
			clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
			#clock-cells = <1>;
			clock-indices = <
				R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
			>;
			clock-output-names =
				"thermal", "iic8";
		};
	};

	prr: chipid@ff000044 {
		compatible = "renesas,prr";
		reg = <0 0xff000044 0 4>;
	};

	sysc: system-controller@e6180000 {
		compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
		reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;

		pm-domains {
			pd_c5: c5 {
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <0>;

				pd_c4: c4@0 {
					reg = <0>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					pd_a3sg: a3sg@16 {
						reg = <16>;
						#power-domain-cells = <0>;
					};

					pd_a3ex: a3ex@17 {
						reg = <17>;
						#power-domain-cells = <0>;
					};

					pd_a3sp: a3sp@18 {
						reg = <18>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <0>;

						pd_a2us: a2us@19 {
							reg = <19>;
							#power-domain-cells = <0>;
						};
					};

					pd_a3sm: a3sm@20 {
						reg = <20>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <0>;

						pd_a2sl: a2sl@21 {
							reg = <21>;
							#power-domain-cells = <0>;
						};
					};

					pd_a3km: a3km@22 {
						reg = <22>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <0>;

						pd_a2kl: a2kl@23 {
							reg = <23>;
							#power-domain-cells = <0>;
						};
					};
				};

				pd_c4ma: c4ma@1 {
					reg = <1>;
					#power-domain-cells = <0>;
				};

				pd_c4cl: c4cl@2 {
					reg = <2>;
					#power-domain-cells = <0>;
				};

				pd_d4: d4@3 {
					reg = <3>;
					#power-domain-cells = <0>;
				};

				pd_a4bc: a4bc@4 {
					reg = <4>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					pd_a3bc: a3bc@5 {
						reg = <5>;
						#power-domain-cells = <0>;
					};
				};

				pd_a4l: a4l@6 {
					reg = <6>;
					#power-domain-cells = <0>;
				};

				pd_a4lc: a4lc@7 {
					reg = <7>;
					#power-domain-cells = <0>;
				};

				pd_a4mp: a4mp@8 {
					reg = <8>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					pd_a3mp: a3mp@9 {
						reg = <9>;
						#power-domain-cells = <0>;
					};

					pd_a3vc: a3vc@10 {
						reg = <10>;
						#power-domain-cells = <0>;
					};
				};

				pd_a4sf: a4sf@11 {
					reg = <11>;
					#power-domain-cells = <0>;
				};

				pd_a3r: a3r@12 {
					reg = <12>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <0>;

					pd_a2rv: a2rv@13 {
						reg = <13>;
						#power-domain-cells = <0>;
					};

					pd_a2is: a2is@14 {
						reg = <14>;
						#power-domain-cells = <0>;
					};
				};
			};
		};
	};
};