code:
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * QorIQ FMan v3 10g port #1 device tree
 *
 * Copyright 2012-2015 Freescale Semiconductor Inc.
 *
 */

fman@1a00000 {
	fman0_rx_0x11: port@91000 {
		cell-index = <0x11>;
		compatible = "fsl,fman-v3-port-rx";
		reg = <0x91000 0x1000>;
		fsl,fman-10g-port;
	};

	fman0_tx_0x31: port@b1000 {
		cell-index = <0x31>;
		compatible = "fsl,fman-v3-port-tx";
		reg = <0xb1000 0x1000>;
		fsl,fman-10g-port;
	};

	ethernet@f2000 {
		cell-index = <0x9>;
		compatible = "fsl,fman-memac";
		reg = <0xf2000 0x1000>;
		fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
		pcsphy-handle = <&pcsphy7>;
	};

	mdio@f3000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
		reg = <0xf3000 0x1000>;

		pcsphy7: ethernet-phy@0 {
			reg = <0x0>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * QorIQ FMan v3 1g port #0 device tree
 *
 * Copyright 2012-2015 Freescale Semiconductor Inc.
 *
 */

fman@1a00000 {
	fman0_rx_0x08: port@88000 {
		cell-index = <0x8>;
		compatible = "fsl,fman-v3-port-rx";
		reg = <0x88000 0x1000>;
	};

	fman0_tx_0x28: port@a8000 {
		cell-index = <0x28>;
		compatible = "fsl,fman-v3-port-tx";
		reg = <0xa8000 0x1000>;
	};

	ethernet@e0000 {
		cell-index = <0>;
		compatible = "fsl,fman-memac";
		reg = <0xe0000 0x1000>;
		fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
		ptp-timer = <&ptp_timer0>;
		pcsphy-handle = <&pcsphy0>;
	};

	mdio@e1000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
		reg = <0xe1000 0x1000>;

		pcsphy0: ethernet-phy@0 {
			reg = <0x0>;
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * QorIQ FMan v3 1g port #1 device tree
 *
 * Copyright 2012-2015 Freescale Semiconductor Inc.
 *
 */

fman@1a00000 {
	fman0_rx_0x09: port@89000 {
		cell-index = <0x9>;
		compatible = "fsl,fman-v3-port-rx";
		reg = <0x89000 0x1000>;
	};

	fman0_tx_0x29: port@a9000 {
		cell-index = <0x29>;
		compatible = "fsl,fman-v3-port-tx";
		reg = <0xa9000 0x1000>;
	};

	ethernet@e2000 {
		cell-index = <1>;
		compatible = "fsl,fman-memac";
		reg = <0xe2000 0x1000>;
		fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
		ptp-timer = <&ptp_timer0>;
		pcsphy-handle = <&pcsphy1>;
	};

	mdio@e3000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
		reg = <0xe3000 0x1000>;

		pcsphy1: ethernet-phy@0 {
			reg = <0x0>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * QorIQ FMan v3 1g port #2 device tree
 *
 * Copyright 2012-2015 Freescale Semiconductor Inc.
 *
 */

fman@1a00000 {
	fman0_rx_0x0a: port@8a000 {
		cell-index = <0xa>;
		compatible = "fsl,fman-v3-port-rx";
		reg = <0x8a000 0x1000>;
	};

	fman0_tx_0x2a: port@aa000 {
		cell-index = <0x2a>;
		compatible = "fsl,fman-v3-port-tx";
		reg = <0xaa000 0x1000>;
	};

	ethernet@e4000 {
		cell-index = <2>;
		compatible = "fsl,fman-memac";
		reg = <0xe4000 0x1000>;
		fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
		ptp-timer = <&ptp_timer0>;
		pcsphy-handle = <&pcsphy2>;
	};

	mdio@e5000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
		reg = <0xe5000 0x1000>;

		pcsphy2: ethernet-phy@0 {
			reg = <0x0>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * QorIQ FMan v3 1g port #3 device tree
 *
 * Copyright 2012-2015 Freescale Semiconductor Inc.
 *
 */

fman@1a00000 {
	fman0_rx_0x0b: port@8b000 {
		cell-index = <0xb>;
		compatible = "fsl,fman-v3-port-rx";
		reg = <0x8b000 0x1000>;
	};

	fman0_tx_0x2b: port@ab000 {
		cell-index = <0x2b>;
		compatible = "fsl,fman-v3-port-tx";
		reg = <0xab000 0x1000>;
	};

	ethernet@e6000 {
		cell-index = <3>;
		compatible = "fsl,fman-memac";
		reg = <0xe6000 0x1000>;
		fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
		ptp-timer = <&ptp_timer0>;
		pcsphy-handle = <&pcsphy3>;
	};

	mdio@e7000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
		reg = <0xe7000 0x1000>;

		pcsphy3: ethernet-phy@0 {
			reg = <0x0>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * QorIQ FMan v3 1g port #4 device tree
 *
 * Copyright 2012-2015 Freescale Semiconductor Inc.
 *
 */

fman@1a00000 {
	fman0_rx_0x0c: port@8c000 {
		cell-index = <0xc>;
		compatible = "fsl,fman-v3-port-rx";
		reg = <0x8c000 0x1000>;
	};

	fman0_tx_0x2c: port@ac000 {
		cell-index = <0x2c>;
		compatible = "fsl,fman-v3-port-tx";
		reg = <0xac000 0x1000>;
	};

	ethernet@e8000 {
		cell-index = <4>;
		compatible = "fsl,fman-memac";
		reg = <0xe8000 0x1000>;
		fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
		ptp-timer = <&ptp_timer0>;
		pcsphy-handle = <&pcsphy4>;
	};

	mdio@e9000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
		reg = <0xe9000 0x1000>;

		pcsphy4: ethernet-phy@0 {
			reg = <0x0>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * QorIQ FMan v3 1g port #5 device tree
 *
 * Copyright 2012-2015 Freescale Semiconductor Inc.
 *
 */

fman@1a00000 {
	fman0_rx_0x0d: port@8d000 {
		cell-index = <0xd>;
		compatible = "fsl,fman-v3-port-rx";
		reg = <0x8d000 0x1000>;
	};

	fman0_tx_0x2d: port@ad000 {
		cell-index = <0x2d>;
		compatible = "fsl,fman-v3-port-tx";
		reg = <0xad000 0x1000>;
	};

	ethernet@ea000 {
		cell-index = <5>;
		compatible = "fsl,fman-memac";
		reg = <0xea000 0x1000>;
		fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
		ptp-timer = <&ptp_timer0>;
		pcsphy-handle = <&pcsphy5>;
	};

	mdio@eb000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
		reg = <0xeb000 0x1000>;

		pcsphy5: ethernet-phy@0 {
			reg = <0x0>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * QorIQ FMan v3 device tree
 *
 * Copyright 2012-2015 Freescale Semiconductor Inc.
 *
 */

#include <dt-bindings/clock/fsl,qoriq-clockgen.h>

fman0: fman@1a00000 {
	#address-cells = <1>;
	#size-cells = <1>;
	cell-index = <0>;
	compatible = "fsl,fman";
	ranges = <0x0 0x0 0x1a00000 0xfe000>;
	reg = <0x0 0x1a00000 0x0 0xfe000>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen QORIQ_CLK_FMAN 0>;
	clock-names = "fmanclk";
	fsl,qman-channel-range = <0x800 0x10>;
	ptimer-handle = <&ptp_timer0>;
	dma-coherent;

	muram@0 {
		compatible = "fsl,fman-muram";
		reg = <0x0 0x60000>;
	};

	fman0_oh_0x2: port@82000 {
		cell-index = <0x2>;
		compatible = "fsl,fman-v3-port-oh";
		reg = <0x82000 0x1000>;
	};

	fman0_oh_0x3: port@83000 {
		cell-index = <0x3>;
		compatible = "fsl,fman-v3-port-oh";
		reg = <0x83000 0x1000>;
	};

	fman0_oh_0x4: port@84000 {
		cell-index = <0x4>;
		compatible = "fsl,fman-v3-port-oh";
		reg = <0x84000 0x1000>;
	};

	fman0_oh_0x5: port@85000 {
		cell-index = <0x5>;
		compatible = "fsl,fman-v3-port-oh";
		reg = <0x85000 0x1000>;
	};

	fman0_oh_0x6: port@86000 {
		cell-index = <0x6>;
		compatible = "fsl,fman-v3-port-oh";
		reg = <0x86000 0x1000>;
	};

	fman0_oh_0x7: port@87000 {
		cell-index = <0x7>;
		compatible = "fsl,fman-v3-port-oh";
		reg = <0x87000 0x1000>;
	};

	mdio0: mdio@fc000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
		reg = <0xfc000 0x1000>;
	};

	xmdio0: mdio@fd000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
		reg = <0xfd000 0x1000>;
	};
};

ptp_timer0: ptp-timer@1afe000 {
	compatible = "fsl,fman-ptp-timer";
	reg = <0x0 0x1afe000 0x0 0x1000>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clockgen QORIQ_CLK_FMAN 0>;
	fsl,extts-fifo;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * QorIQ QMan Portals device tree
 *
 * Copyright 2011-2016 Freescale Semiconductor Inc.
 *
 */

&qportals {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "simple-bus";

	qportal0: qman-portal@0 {
		/*
		 * bootloader fix-ups are expected to provide the
		 * "fsl,bman-portal-<hardware revision>" compatible
		 */
		compatible = "fsl,qman-portal";
		reg = <0x0 0x4000>, <0x4000000 0x4000>;
		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
		cell-index = <0>;
	};

	qportal1: qman-portal@10000 {
		compatible = "fsl,qman-portal";
		reg = <0x10000 0x4000>, <0x4010000 0x4000>;
		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
		cell-index = <1>;
	};

	qportal2: qman-portal@20000 {
		compatible = "fsl,qman-portal";
		reg = <0x20000 0x4000>, <0x4020000 0x4000>;
		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
		cell-index = <2>;
	};

	qportal3: qman-portal@30000 {
		compatible = "fsl,qman-portal";
		reg = <0x30000 0x4000>, <0x4030000 0x4000>;
		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
		cell-index = <3>;
	};

	qportal4: qman-portal@40000 {
		compatible = "fsl,qman-portal";
		reg = <0x40000 0x4000>, <0x4040000 0x4000>;
		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
		cell-index = <4>;
	};

	qportal5: qman-portal@50000 {
		compatible = "fsl,qman-portal";
		reg = <0x50000 0x4000>, <0x4050000 0x4000>;
		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
		cell-index = <5>;
	};

	qportal6: qman-portal@60000 {
		compatible = "fsl,qman-portal";
		reg = <0x60000 0x4000>, <0x4060000 0x4000>;
		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
		cell-index = <6>;
	};

	qportal7: qman-portal@70000 {
		compatible = "fsl,qman-portal";
		reg = <0x70000 0x4000>, <0x4070000 0x4000>;
		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
		cell-index = <7>;
	};

	qportal8: qman-portal@80000 {
		compatible = "fsl,qman-portal";
		reg = <0x80000 0x4000>, <0x4080000 0x4000>;
		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
		cell-index = <8>;
	};

	qportal9: qman-portal@90000 {
		compatible = "fsl,qman-portal";
		reg = <0x90000 0x4000>, <0x4090000 0x4000>;
		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
		cell-index = <9>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * NXP S32G2 SoC family
 *
 * Copyright (c) 2021 SUSE LLC
 * Copyright (c) 2017-2021 NXP
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "nxp,s32g2";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cluster0_l2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};

		cluster1_l2: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	firmware {
		psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0x80000000>;

		uart0: serial@401c8000 {
			compatible = "nxp,s32g2-linflexuart",
				     "fsl,s32v234-linflexuart";
			reg = <0x401c8000 0x3000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
		};

		uart1: serial@401cc000 {
			compatible = "nxp,s32g2-linflexuart",
				     "fsl,s32v234-linflexuart";
			reg = <0x401cc000 0x3000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
		};

		uart2: serial@402bc000 {
			compatible = "nxp,s32g2-linflexuart",
				     "fsl,s32v234-linflexuart";
			reg = <0x402bc000 0x3000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
		};

		gic: interrupt-controller@50800000 {
			compatible = "arm,gic-v3";
			reg = <0x50800000 0x10000>,
			      <0x50880000 0x80000>,
			      <0x50400000 0x2000>,
			      <0x50410000 0x2000>,
			      <0x50420000 0x2000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright (c) 2021 SUSE LLC
 * Copyright (c) 2019-2021 NXP
 */

/dts-v1/;

#include "s32g2.dtsi"

/ {
	model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
	compatible = "nxp,s32g274a-evb", "nxp,s32g2";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	/* 4GiB RAM */
	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0 0x80000000>,
		      <0x8 0x80000000 0 0x80000000>;
	};
};

/* UART (J58) to Micro USB port */
&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright (c) 2021 SUSE LLC
 * Copyright (c) 2019-2021 NXP
 */

/dts-v1/;

#include "s32g2.dtsi"

/ {
	model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
	compatible = "nxp,s32g274a-rdb2", "nxp,s32g2";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	/* 4GiB RAM */
	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0 0x80000000>,
		      <0x8 0x80000000 0 0x80000000>;
	};
};

/* UART (J2) to Micro USB port */
&uart0 {
	status = "okay";
};

/* UART (J1) to Micro USB port */
&uart1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2015-2016 Freescale Semiconductor, Inc.
 * Copyright 2016-2017 NXP
 */

/dts-v1/;
#include "s32v234.dtsi"

/ {
	model = "NXP S32V234-EVB2 Board";
	compatible = "fsl,s32v234-evb", "fsl,s32v234";

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2015-2016 Freescale Semiconductor, Inc.
 * Copyright 2016-2018 NXP
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/memreserve/ 0x80000000 0x00010000;

/ {
	compatible = "fsl,s32v234";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster0_l2_cache>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster0_l2_cache>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster1_l2_cache>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x101>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x80000000>;
			next-level-cache = <&cluster1_l2_cache>;
		};

		cluster0_l2_cache: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};

		cluster1_l2_cache: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>;
		/* clock-frequency might be modified by u-boot, depending on the
		 * chip version.
		 */
		clock-frequency = <10000000>;
	};

	gic: interrupt-controller@7d001000 {
		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0x7d001000 0 0x1000>,
		      <0 0x7d002000 0 0x2000>,
		      <0 0x7d004000 0 0x2000>,
		      <0 0x7d006000 0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
					 IRQ_TYPE_LEVEL_HIGH)>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		aips0: bus@40000000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			reg = <0x0 0x40000000 0x0 0x7d000>;
			ranges;

			uart0: serial@40053000 {
				compatible = "fsl,s32v234-linflexuart";
				reg = <0x0 0x40053000 0x0 0x1000>;
				interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};
		};

		aips1: bus@40080000 {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			interrupt-parent = <&gic>;
			reg = <0x0 0x40080000 0x0 0x70000>;
			ranges;

			uart1: serial@400bc000 {
				compatible = "fsl,s32v234-linflexuart";
				reg = <0x0 0x400bc000 0x0 0x1000>;
				interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
				status = "disabled";
			};
		};
	};
};


code:
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
dtb-$(CONFIG_ARCH_HISI) += hi3670-hikey970.dtb
dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb


code:
// SPDX-License-Identifier: GPL-2.0

/*
 * dtsi for Hisilicon Hi3660 Coresight
 *
 * Copyright (C) 2016-2018 HiSilicon Ltd.
 *
 * Author: Wanglai Shi <shiwanglai@hisilicon.com>
 *
 */
/ {
	soc {
		/* A53 cluster internals */
		etm@ecc40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xecc40000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu0>;

			out-ports {
				port {
					etm0_out: endpoint {
						remote-endpoint =
							<&cluster0_funnel_in0>;
					};
				};
			};
		};

		etm@ecd40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xecd40000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu1>;

			out-ports {
				port {
					etm1_out: endpoint {
						remote-endpoint =
							<&cluster0_funnel_in1>;
					};
				};
			};
		};

		etm@ece40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xece40000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu2>;

			out-ports {
				port {
					etm2_out: endpoint {
						remote-endpoint =
							<&cluster0_funnel_in2>;
					};
				};
			};
		};

		etm@ecf40000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xecf40000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu3>;

			out-ports {
				port {
					etm3_out: endpoint {
						remote-endpoint =
							<&cluster0_funnel_in3>;
					};
				};
			};
		};

		funnel@ec801000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0 0xec801000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					cluster0_funnel_out: endpoint {
						remote-endpoint =
							<&cluster0_etf_in>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					cluster0_funnel_in0: endpoint {
						remote-endpoint = <&etm0_out>;
					};
				};

				port@1 {
					reg = <1>;
					cluster0_funnel_in1: endpoint {
						remote-endpoint = <&etm1_out>;
					};
				};

				port@2 {
					reg = <2>;
					cluster0_funnel_in2: endpoint {
						remote-endpoint = <&etm2_out>;
					};
				};

				port@3 {
					reg = <3>;
					cluster0_funnel_in3: endpoint {
						remote-endpoint = <&etm3_out>;
					};
				};
			};
		};

		etf@ec802000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0 0xec802000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					cluster0_etf_in: endpoint {
						remote-endpoint =
							<&cluster0_funnel_out>;
					};
				};
			};

			out-ports {
				port {
					cluster0_etf_out: endpoint {
						remote-endpoint =
							<&combo_funnel_in0>;
					};
				};
			};
		};

		/* A73 cluster internals */
		etm@ed440000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xed440000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu4>;

			out-ports {
				port {
					etm4_out: endpoint {
						remote-endpoint =
							<&cluster1_funnel_in0>;
					};
				};
			};
		};

		etm@ed540000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xed540000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu5>;

			out-ports {
				port {
					etm5_out: endpoint {
						remote-endpoint =
							<&cluster1_funnel_in1>;
					};
				};
			};
		};

		etm@ed640000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xed640000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu6>;

			out-ports {
				port {
					etm6_out: endpoint {
						remote-endpoint =
							<&cluster1_funnel_in2>;
					};
				};
			};
		};

		etm@ed740000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xed740000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu7>;

			out-ports {
				port {
					etm7_out: endpoint {
						remote-endpoint =
							<&cluster1_funnel_in3>;
					};
				};
			};
		};

		funnel@ed001000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0 0xed001000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";
			out-ports {
				port {
					cluster1_funnel_out: endpoint {
						remote-endpoint =
							<&cluster1_etf_in>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					cluster1_funnel_in0: endpoint {
						remote-endpoint = <&etm4_out>;
					};
				};

				port@1 {
					reg = <1>;
					cluster1_funnel_in1: endpoint {
						remote-endpoint = <&etm5_out>;
					};
				};

				port@2 {
					reg = <2>;
					cluster1_funnel_in2: endpoint {
						remote-endpoint = <&etm6_out>;
					};
				};

				port@3 {
					reg = <3>;
					cluster1_funnel_in3: endpoint {
						remote-endpoint = <&etm7_out>;
					};
				};
			};
		};

		etf@ed002000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0 0xed002000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					cluster1_etf_in: endpoint {
						remote-endpoint =
							<&cluster1_funnel_out>;
					};
				};
			};

			out-ports {
				port {
					cluster1_etf_out: endpoint {
						remote-endpoint =
							<&combo_funnel_in1>;
					};
				};
			};
		};

		/* An invisible combo funnel between clusters and top funnel */
		funnel {
			compatible = "arm,coresight-static-funnel";
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					combo_funnel_out: endpoint {
						remote-endpoint =
							<&top_funnel_in>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					combo_funnel_in0: endpoint {
						remote-endpoint =
							<&cluster0_etf_out>;
					};
				};

				port@1 {
					reg = <1>;
					combo_funnel_in1: endpoint {
						remote-endpoint =
							<&cluster1_etf_out>;
					};
				};
			};
		};

		/* Top internals */
		funnel@ec031000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0 0xec031000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					top_funnel_out: endpoint {
						remote-endpoint =
							<&top_etf_in>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					top_funnel_in: endpoint {
						remote-endpoint =
							<&combo_funnel_out>;
					};
				};
			};
		};

		etf@ec036000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0 0xec036000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					top_etf_in: endpoint {
						remote-endpoint =
							<&top_funnel_out>;
					};
				};
			};

			out-ports {
				port {
					top_etf_out: endpoint {
						remote-endpoint =
							<&replicator_in>;
					};
				};
			};
		};

		replicator {
			compatible = "arm,coresight-static-replicator";
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					replicator_in: endpoint {
						remote-endpoint =
							<&top_etf_out>;
					};
				};
			};

			out-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					replicator0_out0: endpoint {
						remote-endpoint = <&etr_in>;
					};
				};

				port@1 {
					reg = <1>;
					replicator0_out1: endpoint {
						remote-endpoint = <&tpiu_in>;
					};
				};
			};
		};

		etr@ec033000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0 0xec033000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					etr_in: endpoint {
						remote-endpoint =
							<&replicator0_out0>;
					};
				};
			};
		};

		tpiu@ec032000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0 0xec032000 0 0x1000>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					tpiu_in: endpoint {
						remote-endpoint =
							<&replicator0_out1>;
					};
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Hisilicon HiKey960 Development Board
 *
 * Copyright (C) 2016, HiSilicon Ltd.
 *
 */

/dts-v1/;

#include "hi3660.dtsi"
#include "hikey960-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/usb/pd.h>

/ {
	model = "HiKey960";
	compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";

	aliases {
		mshc1 = &dwmmc1;
		mshc2 = &dwmmc2;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &uart6;
	};

	chosen {
		stdout-path = "serial6:115200n8";
	};

	memory@0 {
		device_type = "memory";
		/* rewrite this at bootloader */
		reg = <0x0 0x0 0x0 0x0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ramoops@32000000 {
			compatible = "ramoops";
			reg = <0x0 0x32000000 0x0 0x00100000>;
			record-size = <0x00020000>;
			console-size = <0x00020000>;
			ftrace-size = <0x00020000>;
		};
	};

	reboot-mode-syscon@32100000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x0 0x32100000 0x0 0x00001000>;

		reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x0>;

			mode-normal = <0x77665501>;
			mode-bootloader = <0x77665500>;
			mode-recovery = <0x77665502>;
		};
	};

	keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;

		key-power {
			wakeup-source;
			gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
			label = "GPIO Power";
			linux,code = <KEY_POWER>;
		};
	};

	leds {
		compatible = "gpio-leds";

		user_led1 {
			label = "green:user1";
			/* gpio_150_user_led1 */
			gpios = <&gpio18 6 0>;
			linux,default-trigger = "heartbeat";
		};

		user_led2 {
			label = "green:user2";
			/* gpio_151_user_led2 */
			gpios = <&gpio18 7 0>;
			linux,default-trigger = "none";
		};

		user_led3 {
			label = "green:user3";
			/* gpio_189_user_led3 */
			gpios = <&gpio23 5 0>;
			linux,default-trigger = "mmc0";
		};

		user_led4 {
			label = "green:user4";
			/* gpio_190_user_led4 */
			gpios = <&gpio23 6 0>;
			panic-indicator;
			linux,default-trigger = "none";
		};

		wlan_active_led {
			label = "yellow:wlan";
			/* gpio_205_wifi_active */
			gpios = <&gpio25 5 0>;
			linux,default-trigger = "phy0tx";
			default-state = "off";
		};

		bt_active_led {
			label = "blue:bt";
			gpios = <&gpio25 7 0>;
			/* gpio_207_user_led1 */
			linux,default-trigger = "hci0-power";
			default-state = "off";
		};
	};

	pmic: pmic@fff34000 {
		compatible = "hisilicon,hi6421v530-pmic";
		reg = <0x0 0xfff34000 0x0 0x1000>;
		interrupt-controller;
		#interrupt-cells = <2>;

		regulators {
			ldo3: LDO3 { /* HDMI */
				regulator-name = "VOUT3_1V85";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <2200000>;
				regulator-enable-ramp-delay = <120>;
			};

			ldo9: LDO9 { /* SDCARD I/O */
				regulator-name = "VOUT9_1V8_2V95";
				regulator-min-microvolt = <1750000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <240>;
			};

			ldo11: LDO11 { /* Low Speed Connector */
				regulator-name = "VOUT11_1V8_2V95";
				regulator-min-microvolt = <1750000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <240>;
			};

			ldo15: LDO15 { /* UFS VCC */
				regulator-name = "VOUT15_3V0";
				regulator-min-microvolt = <1750000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-enable-ramp-delay = <120>;
			};

			ldo16: LDO16 { /* SD VDD */
				regulator-name = "VOUT16_2V95";
				regulator-min-microvolt = <1750000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <360>;
			};
		};
	};

	wlan_en: wlan-en-1-8v {
		compatible = "regulator-fixed";
		regulator-name = "wlan-en-regulator";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;

		/* GPIO_051_WIFI_EN */
		gpio = <&gpio6 3 0>;

		/* WLAN card specific delay */
		startup-delay-us = <70000>;
		enable-active-high;
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};

/*
 * Legend: proper name = the GPIO line is used as GPIO
 *         NC = not connected (pin out but not routed from the chip to
 *              anything the board)
 *         "[PER]" = pin is muxed for [peripheral] (not GPIO)
 *         "" = no idea, schematic doesn't say, could be
 *              unrouted (not connected to any external pin)
 *         LSEC = Low Speed External Connector
 *         HSEC = High Speed External Connector
 *
 * Line names are taken from "HiKey 960 Board ver A" schematics
 * from Huawei. The 40 pin low speed expansion connector is named
 * J2002 63453-140LF.
 *
 * For the lines routed to the external connectors the
 * lines are named after the 96Boards CE Specification 1.0,
 * Appendix "Expansion Connector Signal Description".
 *
 * When the 96Board naming of a line and the schematic name of
 * the same line are in conflict, the 96Board specification
 * takes precedence, which means that the external UART on the
 * LSEC is named UART0 while the schematic and SoC names this
 * UART3. This is only for the informational lines i.e. "[FOO]",
 * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
 * ones actually used for GPIO.
 */
&gpio0 {
	/* GPIO_000-GPIO_007 */
	gpio-line-names =
		"",
		"TP901", /* TEST_MODE connected to TP901 */
		"[PMU0_SSI]",
		"[PMU1_SSI]",
		"[PMU2_SSI]",
		"[PMU0_CLKOUT]",
		"[JTAG_TCK]",
		"[JTAG_TMS]";
};

&gpio1 {
	/* GPIO_008-GPIO_015 */
	gpio-line-names =
		"[JTAG_TRST_N]",
		"[JTAG_TDI]",
		"[JTAG_TDO]",
		"NC", "NC",
		"[I2C3_SCL]",
		"[I2C3_SDA]",
		"NC";
};

&gpio2 {
	/* GPIO_016-GPIO_023 */
	gpio-line-names =
		"NC", "NC", "NC",
		"GPIO-J", /* LSEC pin 32: GPIO_019 */
		"GPIO_020_HDMI_SEL",
		"GPIO-L", /* LSEC pin 34: GPIO_021 */
		"GPIO_022_UFSBUCK_INT_N",
		"GPIO-G"; /* LSEC pin 29: LCD_TE0 */
};

&gpio3 {
	/* GPIO_024-GPIO_031 */
	/* The rail from pin BK36 is named LCD_TE0, we assume to be muxed as GPIO for GPIO-G */
	gpio-line-names =
		"[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */
		"[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */
		"NC",
		"[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */
		"[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */
		"[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */
		"[I2C3_SDA]", /* HSEC pin 38: ISP_SDA1 */
		"NC";
};

&gpio4 {
	/* GPIO_032-GPIO_039 */
	gpio-line-names =
		"NC", "NC",
		"PWR_BTN_N", /* LSEC pin 4: GPIO_034_PWRON_DET */
		"GPIO_035_PMU2_EN",
		"GPIO_036_USB_HUB_RESET",
		"NC", "NC", "NC";
};

&gpio5 {
	/* GPIO_040-GPIO_047 */
	gpio-line-names =
		"GPIO-H", /* LSEC pin 30: GPIO_040_LCD_RST_N */
		"GPIO_041_HDMI_PD",
		"TP904", /* Test point */
		"TP905", /* Test point */
		"NC", "NC",
		"GPIO_046_HUB_VDD33_EN",
		"GPIO_047_PMU1_EN";
};

&gpio6 {
	/* GPIO_048-GPIO_055 */
	gpio-line-names =
		"NC", "NC", "NC",
		"GPIO_051_WIFI_EN",
		"GPIO-I", /* LSEC pin 31: GPIO_052_CAM0_RST_N */
		/*
		 * These two pins should be used for SD(IO) data according to the
		 * 96boards specification but seems to be repurposed for a IRDA UART.
		 * They are however named according to the spec.
		 */
		"[SD_DAT1]", /* HSEC pin 3: UART0_IRDA_RXD */
		"[SD_DAT2]", /* HSEC pin 5: UART0_IRDA_TXD */
		"[UART1_RXD]"; /* LSEC pin 13: DEBUG_UART6_RXD */
};

&gpio7 {
	/* GPIO_056-GPIO_063 */
	gpio-line-names =
		"[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */
		"[UART0_CTS]", /* LSEC pin 3: UART3_CTS_N */
		"[UART0_RTS]", /* LSEC pin 9: UART3_RTS_N */
		"[UART0_RXD]", /* LSEC pin 7: UART3_RXD */
		"[UART0_TXD]", /* LSEC pin 5: UART3_TXD */
		"[SOC_BT_UART4_CTS_N]",
		"[SOC_BT_UART4_RTS_N]",
		"[SOC_BT_UART4_RXD]";
};

&gpio8 {
	/* GPIO_064-GPIO_071 */
	gpio-line-names =
		"[SOC_BT_UART4_TXD]",
		"NC",
		"[PMU_HKADC_SSI]",
		"NC",
		"GPIO_068_SEL",
		"NC", "NC", "NC";

};

&gpio9 {
	/* GPIO_072-GPIO_079 */
	gpio-line-names =
		"NC", "NC", "NC",
		"GPIO-K", /* LSEC pin 33: GPIO_075_CAM1_RST_N */
		"NC", "NC", "NC", "NC";
};

&gpio10 {
	/* GPIO_080-GPIO_087 */
	gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};

&gpio11 {
	/* GPIO_088-GPIO_095 */
	gpio-line-names =
		"NC",
		"[PCIE_PERST_N]",
		"NC", "NC", "NC", "NC", "NC", "NC";
};

&gpio12 {
	/* GPIO_096-GPIO_103 */
	gpio-line-names = "NC", "NC", "NC", "", "", "", "", "NC";
};

&gpio13 {
	/* GPIO_104-GPIO_111 */
	gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};

&gpio14 {
	/* GPIO_112-GPIO_119 */
	gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};

&gpio15 {
	/* GPIO_120-GPIO_127 */
	gpio-line-names =
		"NC", "NC", "NC", "NC", "NC", "NC",
		"GPIO_126_BT_EN",
		"TP902"; /* GPIO_127_JTAG_SEL0 */
};

&gpio16 {
	/* GPIO_128-GPIO_135 */
	gpio-line-names = "", "", "", "", "", "", "", "";
};

&gpio17 {
	/* GPIO_136-GPIO_143 */
	gpio-line-names = "", "", "", "", "", "", "", "";
};

&gpio18 {
	/* GPIO_144-GPIO_151 */
	gpio-line-names =
		"[UFS_REF_CLK]",
		"[UFS_RST_N]",
		"[SPI1_SCLK]", /* HSEC pin 9: GPIO_146_SPI3_CLK */
		"[SPI1_DIN]", /* HSEC pin 11: GPIO_147_SPI3_DI */
		"[SPI1_DOUT]", /* HSEC pin 1: GPIO_148_SPI3_DO */
		"[SPI1_CS]", /* HSEC pin 7: GPIO_149_SPI3_CS0_N */
		"GPIO_150_USER_LED1",
		"GPIO_151_USER_LED2";
};

&gpio19 {
	/* GPIO_152-GPIO_159 */
	gpio-line-names = "NC", "NC", "NC", "NC", "", "", "", "";
};

&gpio20 {
	/* GPIO_160-GPIO_167 */
	gpio-line-names =
		"[SD_CLK]",
		"[SD_CMD]",
		"[SD_DATA0]",
		"[SD_DATA1]",
		"[SD_DATA2]",
		"[SD_DATA3]",
		"", "";
};

&gpio21 {
	/* GPIO_168-GPIO_175 */
	gpio-line-names =
		"[WL_SDIO_CLK]",
		"[WL_SDIO_CMD]",
		"[WL_SDIO_DATA0]",
		"[WL_SDIO_DATA1]",
		"[WL_SDIO_DATA2]",
		"[WL_SDIO_DATA3]",
		"", "";
};

&gpio22 {
	/* GPIO_176-GPIO_183 */
	gpio-line-names =
		"[GPIO_176_PMU_PWR_HOLD]",
		"NA",
		"[SYSCLK_EN]",
		"GPIO_179_WL_WAKEUP_AP",
		"GPIO_180_HDMI_INT",
		"NA",
		"GPIO-F", /* LSEC pin 28: LCD_BL_PWM */
		"[I2C0_SCL]"; /* LSEC pin 15 */
};

&gpio23 {
	/* GPIO_184-GPIO_191 */
	gpio-line-names =
		"[I2C0_SDA]", /* LSEC pin 17 */
		"[I2C1_SCL]", /* Actual SoC I2C1 */
		"[I2C1_SDA]", /* Actual SoC I2C1 */
		"[I2C1_SCL]", /* LSEC pin 19: I2C7_SCL */
		"[I2C1_SDA]", /* LSEC pin 21: I2C7_SDA */
		"GPIO_189_USER_LED3",
		"GPIO_190_USER_LED4",
		"";
};

&gpio24 {
	/* GPIO_192-GPIO_199 */
	gpio-line-names =
		"[PCM_DI]", /* LSEC pin 22: GPIO_192_I2S0_DI */
		"[PCM_DO]", /* LSEC pin 20: GPIO_193_I2S0_DO */
		"[PCM_CLK]", /* LSEC pin 18: GPIO_194_I2S0_XCLK */
		"[PCM_FS]", /* LSEC pin 16: GPIO_195_I2S0_XFS */
		"[GPIO_196_I2S2_DI]",
		"[GPIO_197_I2S2_DO]",
		"[GPIO_198_I2S2_XCLK]",
		"[GPIO_199_I2S2_XFS]";
};

&gpio25 {
	/* GPIO_200-GPIO_207 */
	gpio-line-names =
		"NC",
		"NC",
		"GPIO_202_VBUS_TYPEC",
		"GPIO_203_SD_DET",
		"GPIO_204_PMU12_IRQ_N",
		"GPIO_205_WIFI_ACTIVE",
		"GPIO_206_USBSW_SEL",
		"GPIO_207_BT_ACTIVE";
};

&gpio26 {
	/* GPIO_208-GPIO_215 */
	gpio-line-names =
		"GPIO-A", /* LSEC pin 23: GPIO_208 */
		"GPIO-B", /* LSEC pin 24: GPIO_209 */
		"GPIO-C", /* LSEC pin 25: GPIO_210 */
		"GPIO-D", /* LSEC pin 26: GPIO_211 */
		"GPIO-E", /* LSEC pin 27: GPIO_212 */
		"[PCIE_CLKREQ_N]",
		"[PCIE_WAKE_N]",
		"[SPI0_CLK]"; /* LSEC pin 8: SPI2_CLK */
};

&gpio27 {
	/* GPIO_216-GPIO_223 */
	gpio-line-names =
		"[SPI0_DIN]", /* LSEC pin 10: SPI2_DI */
		"[SPI0_DOUT]", /* LSEC pin 14: SPI2_DO */
		"[SPI0_CS]", /* LSEC pin 12: SPI2_CS0_N */
		"GPIO_219_CC_INT",
		"NC",
		"NC",
		"[PMU_INT]",
		"";
};

&gpio28 {
	/* GPIO_224-GPIO_231 */
	gpio-line-names =
		"", "", "", "", "", "", "", "";
};

&i2c0 {
	/* On Low speed expansion */
	label = "LS-I2C0";
	status = "okay";
};

&i2c1 {
	status = "okay";

	rt1711h: rt1711h@4e {
		compatible = "richtek,rt1711h";
		reg = <0x4e>;
		status = "okay";
		interrupt-parent = <&gpio27>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&usb_cfg_func>;

		usb_con: connector {
			compatible = "usb-c-connector";
			label = "USB-C";
			data-role = "dual";
			power-role = "dual";
			try-power-role = "sink";
			source-pdos = <PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)>;
			sink-pdos = <PDO_FIXED(5000, 500, PDO_FIXED_USB_COMM)
				PDO_VAR(5000, 5000, 1000)>;
			op-sink-microwatt = <10000000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;
				port@1 {
					reg = <1>;
					usb_con_ss: endpoint {
						remote-endpoint = <&dwc3_ss>;
					};
				};
			};
		};
		port {
			#address-cells = <1>;
			#size-cells = <0>;

			rt1711h_ep: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&dwc3_role_switch>;
			};
		};
	};

	adv7533: adv7533@39 {
		status = "okay";
		compatible = "adi,adv7533";
		reg = <0x39>;
		adi,dsi-lanes = <4>;
		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
			};
			port@1 {
				reg = <1>;
			};
		};
	};
};

&i2c7 {
	/* On Low speed expansion */
	label = "LS-I2C1";
	status = "okay";
};

&uart3 {
	/* On Low speed expansion */
	label = "LS-UART0";
	status = "okay";
};

&uart4 {
	status = "okay";

	bluetooth {
		compatible = "ti,wl1837-st";
		enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;
		max-speed = <3000000>;
	};
};

&uart6 {
	/* On Low speed expansion */
	label = "LS-UART1";
	status = "okay";
};

&spi2 {
	/* On Low speed expansion */
	label = "LS-SPI0";
	status = "okay";
};

&spi3 {
	/* On High speed expansion */
	label = "HS-SPI1";
	status = "okay";
};

&dwmmc1 {
	bus-width = <0x4>;
	cap-sd-highspeed;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	disable-wp;
	cd-gpios = <&gpio25 3 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&sd_pmx_func
		     &sd_clk_cfg_func
		     &sd_cfg_func>;
	vmmc-supply = <&ldo16>;
	vqmmc-supply = <&ldo9>;
	status = "okay";
};

&dwmmc2 { /* WIFI */
	bus-width = <0x4>;
	non-removable;
	broken-cd;
	cap-power-off-card;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio_pmx_func
		     &sdio_clk_cfg_func
		     &sdio_cfg_func>;
	/* WL_EN */
	vmmc-supply = <&wlan_en>;
	status = "okay";

	wlcore: wlcore@2 {
		compatible = "ti,wl1837";
		reg = <2>;      /* sdio func num */
		/* WL_IRQ, GPIO_179_WL_WAKEUP_AP */
		interrupt-parent = <&gpio22>;
		interrupts = <3 IRQ_TYPE_EDGE_RISING>;
	};
};

&dwc3 { /* USB */
	dr_mode = "otg";
	maximum-speed = "super-speed";
	phy_type = "utmi";
	snps,dis-del-phy-power-chg-quirk;
	snps,lfps_filter_quirk;
	snps,dis_u2_susphy_quirk;
	snps,dis_u3_susphy_quirk;
	snps,tx_de_emphasis_quirk;
	snps,tx_de_emphasis = <1>;
	snps,dis_enblslpm_quirk;
	snps,gctl-reset-quirk;
	usb-role-switch;
	role-switch-default-mode = "host";
	port {
		#address-cells = <1>;
		#size-cells = <0>;
		dwc3_role_switch: endpoint@0 {
			reg = <0>;
			remote-endpoint = <&rt1711h_ep>;
		};

		dwc3_ss: endpoint@1 {
			reg = <1>;
			remote-endpoint = <&usb_con_ss>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Hisilicon Hi3660 SoC
 *
 * Copyright (C) 2016, HiSilicon Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3660-clock.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "hisilicon,hi3660";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <592>;
			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
			operating-points-v2 = <&cluster0_opp>;
			#cooling-cells = <2>;
			dynamic-power-coefficient = <110>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <592>;
			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
			operating-points-v2 = <&cluster0_opp>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x2>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <592>;
			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
			operating-points-v2 = <&cluster0_opp>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x3>;
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <592>;
			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
			operating-points-v2 = <&cluster0_opp>;
			#cooling-cells = <2>;
		};

		cpu4: cpu@100 {
			compatible = "arm,cortex-a73";
			device_type = "cpu";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&A73_L2>;
			cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
			capacity-dmips-mhz = <1024>;
			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
			operating-points-v2 = <&cluster1_opp>;
			#cooling-cells = <2>;
			dynamic-power-coefficient = <550>;
		};

		cpu5: cpu@101 {
			compatible = "arm,cortex-a73";
			device_type = "cpu";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&A73_L2>;
			cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
			capacity-dmips-mhz = <1024>;
			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
			operating-points-v2 = <&cluster1_opp>;
			#cooling-cells = <2>;
		};

		cpu6: cpu@102 {
			compatible = "arm,cortex-a73";
			device_type = "cpu";
			reg = <0x0 0x102>;
			enable-method = "psci";
			next-level-cache = <&A73_L2>;
			cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
			capacity-dmips-mhz = <1024>;
			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
			operating-points-v2 = <&cluster1_opp>;
			#cooling-cells = <2>;
		};

		cpu7: cpu@103 {
			compatible = "arm,cortex-a73";
			device_type = "cpu";
			reg = <0x0 0x103>;
			enable-method = "psci";
			next-level-cache = <&A73_L2>;
			cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
			capacity-dmips-mhz = <1024>;
			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
			operating-points-v2 = <&cluster1_opp>;
			#cooling-cells = <2>;
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <400>;
				exit-latency-us = <650>;
				min-residency-us = <1500>;
			};
			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <500>;
				exit-latency-us = <1600>;
				min-residency-us = <3500>;
			};

			CPU_SLEEP_1: cpu-sleep-1 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <400>;
				exit-latency-us = <550>;
				min-residency-us = <1500>;
			};

			CLUSTER_SLEEP_1: cluster-sleep-1 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <800>;
				exit-latency-us = <2900>;
				min-residency-us = <3500>;
			};
		};

		A53_L2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};

		A73_L2: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	cluster0_opp: opp-table-0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp00 {
			opp-hz = /bits/ 64 <533000000>;
			opp-microvolt = <700000>;
			clock-latency-ns = <300000>;
		};

		opp01 {
			opp-hz = /bits/ 64 <999000000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
		};

		opp02 {
			opp-hz = /bits/ 64 <1402000000>;
			opp-microvolt = <900000>;
			clock-latency-ns = <300000>;
		};

		opp03 {
			opp-hz = /bits/ 64 <1709000000>;
			opp-microvolt = <1000000>;
			clock-latency-ns = <300000>;
		};

		opp04 {
			opp-hz = /bits/ 64 <1844000000>;
			opp-microvolt = <1100000>;
			clock-latency-ns = <300000>;
		};
	};

	cluster1_opp: opp-table-1 {
		compatible = "operating-points-v2";
		opp-shared;

		opp10 {
			opp-hz = /bits/ 64 <903000000>;
			opp-microvolt = <700000>;
			clock-latency-ns = <300000>;
		};

		opp11 {
			opp-hz = /bits/ 64 <1421000000>;
			opp-microvolt = <800000>;
			clock-latency-ns = <300000>;
		};

		opp12 {
			opp-hz = /bits/ 64 <1805000000>;
			opp-microvolt = <900000>;
			clock-latency-ns = <300000>;
		};

		opp13 {
			opp-hz = /bits/ 64 <2112000000>;
			opp-microvolt = <1000000>;
			clock-latency-ns = <300000>;
		};

		opp14 {
			opp-hz = /bits/ 64 <2362000000>;
			opp-microvolt = <1100000>;
			clock-latency-ns = <300000>;
		};
	};

	gic: interrupt-controller@e82b0000 {
		compatible = "arm,gic-400";
		reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
		      <0x0 0xe82b2000 0 0x2000>, /* GICC */
		      <0x0 0xe82b4000 0 0x2000>, /* GICH */
		      <0x0 0xe82b6000 0 0x2000>; /* GICV */
		#address-cells = <0>;
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
					 IRQ_TYPE_LEVEL_HIGH)>;
	};

	a53-pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
	};

	a73-pmu {
		compatible = "arm,cortex-a73-pmu";
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu4>,
				     <&cpu5>,
				     <&cpu6>,
				     <&cpu7>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		crg_ctrl: crg_ctrl@fff35000 {
			compatible = "hisilicon,hi3660-crgctrl", "syscon";
			reg = <0x0 0xfff35000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		crg_rst: crg_rst_controller {
			compatible = "hisilicon,hi3660-reset";
			#reset-cells = <2>;
			hisi,rst-syscon = <&crg_ctrl>;
		};

		pctrl: pctrl@e8a09000 {
			compatible = "hisilicon,hi3660-pctrl", "syscon";
			reg = <0x0 0xe8a09000 0x0 0x2000>;
			#clock-cells = <1>;
		};

		pmuctrl: crg_ctrl@fff34000 {
			compatible = "hisilicon,hi3660-pmuctrl", "syscon";
			reg = <0x0 0xfff34000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		sctrl: sctrl@fff0a000 {
			compatible = "hisilicon,hi3660-sctrl", "syscon";
			reg = <0x0 0xfff0a000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		iomcu: iomcu@ffd7e000 {
			compatible = "hisilicon,hi3660-iomcu", "syscon";
			reg = <0x0 0xffd7e000 0x0 0x1000>;
			#clock-cells = <1>;

		};

		iomcu_rst: reset {
			compatible = "hisilicon,hi3660-reset";
			hisi,rst-syscon = <&iomcu>;
			#reset-cells = <2>;
		};

		mailbox: mailbox@e896b000 {
			compatible = "hisilicon,hi3660-mbox";
			reg = <0x0 0xe896b000 0x0 0x1000>;
			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
			#mbox-cells = <3>;
		};

		stub_clock: stub_clock@e896b500 {
			compatible = "hisilicon,hi3660-stub-clk";
			reg = <0x0 0xe896b500 0x0 0x0100>;
			#clock-cells = <1>;
			mboxes = <&mailbox 13 3 0>;
		};

		dual_timer0: timer@fff14000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x0 0xfff14000 0x0 0x1000>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_OSC32K>,
				 <&crg_ctrl HI3660_OSC32K>,
				 <&crg_ctrl HI3660_OSC32K>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		i2c0: i2c@ffd71000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xffd71000 0x0 0x1000>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
			resets = <&iomcu_rst 0x20 3>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
			status = "disabled";
		};

		i2c1: i2c@ffd72000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xffd72000 0x0 0x1000>;
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
			resets = <&iomcu_rst 0x20 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
			status = "disabled";
		};

		i2c3: i2c@fdf0c000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xfdf0c000 0x0 0x1000>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
			resets = <&crg_rst 0x78 7>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
			status = "disabled";
		};

		i2c7: i2c@fdf0b000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xfdf0b000 0x0 0x1000>;
			interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
			resets = <&crg_rst 0x60 14>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
			status = "disabled";
		};

		uart0: serial@fdf02000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf02000 0x0 0x1000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
				 <&crg_ctrl HI3660_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
			status = "disabled";
		};

		uart1: serial@fdf00000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf00000 0x0 0x1000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			dma-names = "rx", "tx";
			dmas = <&dma0 2 &dma0 3>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
				 <&crg_ctrl HI3660_CLK_GATE_UART1>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
			status = "disabled";
		};

		uart2: serial@fdf03000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf03000 0x0 0x1000>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			dma-names = "rx", "tx";
			dmas = <&dma0 4 &dma0 5>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
				 <&crg_ctrl HI3660_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
			status = "disabled";
		};

		uart3: serial@ffd74000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xffd74000 0x0 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
				 <&crg_ctrl HI3660_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
			status = "disabled";
		};

		uart4: serial@fdf01000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf01000 0x0 0x1000>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			dma-names = "rx", "tx";
			dmas = <&dma0 6 &dma0 7>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
				 <&crg_ctrl HI3660_CLK_GATE_UART4>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
			status = "disabled";
		};

		uart5: serial@fdf05000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf05000 0x0 0x1000>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			dma-names = "rx", "tx";
			dmas = <&dma0 8 &dma0 9>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
				 <&crg_ctrl HI3660_CLK_GATE_UART5>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
			status = "disabled";
		};

		uart6: serial@fff32000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfff32000 0x0 0x1000>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_UART6>,
				 <&crg_ctrl HI3660_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
			status = "disabled";
		};

		dma0: dma@fdf30000 {
			compatible = "hisilicon,k3-dma-1.0";
			reg = <0x0 0xfdf30000 0x0 0x1000>;
			#dma-cells = <1>;
			dma-channels = <16>;
			dma-requests = <32>;
			dma-channel-mask = <0xfffe>;
			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
			dma-no-cci;
			dma-type = "hi3660_dma";
		};

		asp_dmac: dma-controller@e804b000 {
			compatible = "hisilicon,hisi-pcm-asp-dma-1.0";
			reg = <0x0 0xe804b000 0x0 0x1000>;
			#dma-cells = <1>;
			dma-channels = <16>;
			dma-requests = <32>;
			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "asp_dma_irq";
		};

		rtc0: rtc@fff04000 {
			compatible = "arm,pl031", "arm,primecell";
			reg = <0x0 0Xfff04000 0x0 0x1000>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";
		};

		gpio0: gpio@e8a0b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0b000 0 0x1000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 1 0 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
			clock-names = "apb_pclk";
		};

		gpio1: gpio@e8a0c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0c000 0 0x1000>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 1 7 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
			clock-names = "apb_pclk";
		};

		gpio2: gpio@e8a0d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0d000 0 0x1000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 14 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
			clock-names = "apb_pclk";
		};

		gpio3: gpio@e8a0e000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0e000 0 0x1000>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 22 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
			clock-names = "apb_pclk";
		};

		gpio4: gpio@e8a0f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0f000 0 0x1000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 30 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
			clock-names = "apb_pclk";
		};

		gpio5: gpio@e8a10000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a10000 0 0x1000>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 38 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
			clock-names = "apb_pclk";
		};

		gpio6: gpio@e8a11000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a11000 0 0x1000>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 46 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
			clock-names = "apb_pclk";
		};

		gpio7: gpio@e8a12000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a12000 0 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 54 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
			clock-names = "apb_pclk";
		};

		gpio8: gpio@e8a13000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a13000 0 0x1000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 62 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
			clock-names = "apb_pclk";
		};

		gpio9: gpio@e8a14000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a14000 0 0x1000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 70 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
			clock-names = "apb_pclk";
		};

		gpio10: gpio@e8a15000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a15000 0 0x1000>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 78 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
			clock-names = "apb_pclk";
		};

		gpio11: gpio@e8a16000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a16000 0 0x1000>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 86 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
			clock-names = "apb_pclk";
		};

		gpio12: gpio@e8a17000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a17000 0 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
			clock-names = "apb_pclk";
		};

		gpio13: gpio@e8a18000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a18000 0 0x1000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 102 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
			clock-names = "apb_pclk";
		};

		gpio14: gpio@e8a19000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a19000 0 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 110 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
			clock-names = "apb_pclk";
		};

		gpio15: gpio@e8a1a000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a1a000 0 0x1000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 118 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
			clock-names = "apb_pclk";
		};

		gpio16: gpio@e8a1b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a1b000 0 0x1000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
			clock-names = "apb_pclk";
		};

		gpio17: gpio@e8a1c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a1c000 0 0x1000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
			clock-names = "apb_pclk";
		};

		gpio18: gpio@ff3b4000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xff3b4000 0 0x1000>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx2 0 0 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
			clock-names = "apb_pclk";
		};

		gpio19: gpio@ff3b5000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xff3b5000 0 0x1000>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx2 0 8 4>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
			clock-names = "apb_pclk";
		};

		gpio20: gpio@e8a1f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a1f000 0 0x1000>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx1 0 0 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
			clock-names = "apb_pclk";
		};

		gpio21: gpio@e8a20000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a20000 0 0x1000>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx3 0 0 6>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
			clock-names = "apb_pclk";
		};

		gpio22: gpio@fff0b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0b000 0 0x1000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO176 */
			gpio-ranges = <&pmx4 2 0 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
			clock-names = "apb_pclk";
		};

		gpio23: gpio@fff0c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0c000 0 0x1000>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO184 */
			gpio-ranges = <&pmx4 0 6 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
			clock-names = "apb_pclk";
		};

		gpio24: gpio@fff0d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0d000 0 0x1000>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO192 */
			gpio-ranges = <&pmx4 0 13 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
			clock-names = "apb_pclk";
		};

		gpio25: gpio@fff0e000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0e000 0 0x1000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO200 */
			gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
			clock-names = "apb_pclk";
		};

		gpio26: gpio@fff0f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0f000 0 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO208 */
			gpio-ranges = <&pmx4 0 28 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
			clock-names = "apb_pclk";
		};

		gpio27: gpio@fff10000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff10000 0 0x1000>;
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO216 */
			gpio-ranges = <&pmx4 0 36 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
			clock-names = "apb_pclk";
		};

		gpio28: gpio@fff1d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff1d000 0 0x1000>;
			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
			clock-names = "apb_pclk";
		};

		spi2: spi@ffd68000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x0 0xffd68000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>;
			clock-names = "sspclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;
			num-cs = <1>;
			cs-gpios = <&gpio27 2 0>;
			status = "disabled";
		};

		spi3: spi@ff3b3000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x0 0xff3b3000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>;
			clock-names = "sspclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;
			num-cs = <1>;
			cs-gpios = <&gpio18 5 0>;
			status = "disabled";
		};

		pcie@f4000000 {
			compatible = "hisilicon,kirin960-pcie";
			reg = <0x0 0xf4000000 0x0 0x1000>,
			      <0x0 0xff3fe000 0x0 0x1000>,
			      <0x0 0xf3f20000 0x0 0x40000>,
			      <0x0 0xf5000000 0x0 0x2000>;
			reg-names = "dbi", "apb", "phy", "config";
			bus-range = <0x0 0xff>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0x00000000
				  0x0 0xf6000000
				  0x0 0x02000000>;
			num-lanes = <1>;
			#interrupt-cells = <1>;
			interrupts = <0 283 4>;
			interrupt-names = "msi";
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map = <0x0 0 0 1
					 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
					<0x0 0 0 2
					 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
					<0x0 0 0 3
					 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
					<0x0 0 0 4
					 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
				 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
				 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
				 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
				 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
			clock-names = "pcie_phy_ref", "pcie_aux",
				      "pcie_apb_phy", "pcie_apb_sys",
				      "pcie_aclk";
			reset-gpios = <&gpio11 1 0 >;
		};

		/* UFS */
		ufs: ufs@ff3b0000 {
			compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
			/* 0: HCI standard */
			/* 1: UFS SYS CTRL */
			reg = <0x0 0xff3b0000 0x0 0x1000>,
				<0x0 0xff3b1000 0x0 0x1000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
				<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
			clock-names = "ref_clk", "phy_clk";
			freq-table-hz = <0 0>,
					<0 0>;
			/* offset: 0x84; bit: 12 */
			resets = <&crg_rst 0x84 12>;
			reset-names = "rst";
		};

		/* SD */
		dwmmc1: dwmmc1@ff37f000 {
			compatible = "hisilicon,hi3660-dw-mshc";
			reg = <0x0 0xff37f000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
				<&crg_ctrl HI3660_HCLK_GATE_SD>;
			clock-names = "ciu", "biu";
			clock-frequency = <3200000>;
			resets = <&crg_rst 0x94 18>;
			reset-names = "reset";
			hisilicon,peripheral-syscon = <&sctrl>;
			card-detect-delay = <200>;
			status = "disabled";
		};

		/* SDIO */
		dwmmc2: dwmmc2@ff3ff000 {
			compatible = "hisilicon,hi3660-dw-mshc";
			reg = <0x0 0xff3ff000 0x0 0x1000>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
				 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
			clock-names = "ciu", "biu";
			resets = <&crg_rst 0x94 20>;
			reset-names = "reset";
			card-detect-delay = <200>;
			status = "disabled";
		};

		watchdog0: watchdog@e8a06000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xe8a06000 0x0 0x1000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_OSC32K>,
				 <&crg_ctrl HI3660_OSC32K>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		watchdog1: watchdog@e8a07000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xe8a07000 0x0 0x1000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_OSC32K>,
				 <&crg_ctrl HI3660_OSC32K>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		tsensor: tsensor@fff30000 {
			compatible = "hisilicon,hi3660-tsensor";
			reg = <0x0 0xfff30000 0x0 0x1000>;
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
			#thermal-sensor-cells = <1>;
		};

		thermal-zones {

			cls0: cls0-thermal {
				polling-delay = <1000>;
				polling-delay-passive = <100>;
				sustainable-power = <4500>;

				/* sensor ID */
				thermal-sensors = <&tsensor 1>;

				trips {
					threshold: trip-point0 {
						temperature = <65000>;
						hysteresis = <1000>;
						type = "passive";
					};

					target: trip-point1 {
						temperature = <75000>;
						hysteresis = <1000>;
						type = "passive";
					};
				};

				cooling-maps {
					map0 {
						trip = <&target>;
						contribution = <1024>;
						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
					};
					map1 {
						trip = <&target>;
						contribution = <512>;
						cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
					};
				};
			};
		};

		usb3_otg_bc: usb3_otg_bc@ff200000 {
			compatible = "syscon", "simple-mfd";
			reg = <0x0 0xff200000 0x0 0x1000>;

			usb_phy: usb-phy {
				compatible = "hisilicon,hi3660-usb-phy";
				#phy-cells = <0>;
				hisilicon,pericrg-syscon = <&crg_ctrl>;
				hisilicon,pctrl-syscon = <&pctrl>;
				hisilicon,eye-diagram-param = <0x22466e4>;
			};
		};

		dwc3: usb@ff100000 {
			compatible = "snps,dwc3";
			reg = <0x0 0xff100000 0x0 0x100000>;

			clocks = <&crg_ctrl HI3660_CLK_ABB_USB>,
				 <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
			clock-names = "ref", "bus_early";

			assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
			assigned-clock-rates = <229000000>;

			resets = <&crg_rst 0x90 8>,
				 <&crg_rst 0x90 7>,
				 <&crg_rst 0x90 6>,
				 <&crg_rst 0x90 5>;

			interrupts = <0 159 4>, <0 161 4>;
			phys = <&usb_phy>;
			phy-names = "usb3-phy";
		};
	};
};

#include "hi3660-coresight.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Hisilicon HiKey970 Development Board
 *
 * Copyright (C) 2016, HiSilicon Ltd.
 * Copyright (C) 2018, Linaro Ltd.
 *
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>

#include "hi3670.dtsi"
#include "hikey970-pinctrl.dtsi"
#include "hikey970-pmic.dtsi"

/ {
	model = "HiKey970";
	compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";

	aliases {
		mshc1 = &dwmmc1;
		mshc2 = &dwmmc2;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &uart6;       /* console UART */
	};

	chosen {
		stdout-path = "serial6:115200n8";
	};

	memory@0 {
		device_type = "memory";
		/* expect bootloader to fill in this region */
		reg = <0x0 0x0 0x0 0x0>;
	};

	wlan_en: wlan-en-1-8v {
		compatible = "regulator-fixed";
		regulator-name = "wlan-en-regulator";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;

		/* GPIO_051_WIFI_EN */
		gpio = <&gpio6 3 0>;

		/* WLAN card specific delay */
		startup-delay-us = <70000>;
		enable-active-high;
	};
};

/*
 * Legend: proper name = the GPIO line is used as GPIO
 *         NC = not connected (pin out but not routed from the chip to
 *              anything the board)
 *         "[PER]" = pin is muxed for [peripheral] (not GPIO)
 *         "" = no idea, schematic doesn't say, could be
 *              unrouted (not connected to any external pin)
 *         LSEC = Low Speed External Connector
 *         HSEC = High Speed External Connector
 *
 * Line names are taken from "hikey970-schematics.pdf" from HiSilicon.
 *
 * For the lines routed to the external connectors the
 * lines are named after the 96Boards CE Specification 1.0,
 * Appendix "Expansion Connector Signal Description".
 *
 * When the 96Board naming of a line and the schematic name of
 * the same line are in conflict, the 96Board specification
 * takes precedence, which means that the external UART on the
 * LSEC is named UART0 while the schematic and SoC names this
 * UART2. This is only for the informational lines i.e. "[FOO]",
 * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
 * ones actually used for GPIO.
 */
&gpio0 {
	/* GPIO_000-GPIO_007 */
	gpio-line-names =
		"",
		"TP901", /* TEST_MODE connected to TP901 */
		"",
		"GPIO_003_USB_HUB_RESET_N",
		"NC",
		"[AP_GPS_REF_CLK]",
		"[I2C3_SCL]",
		"[I2C3_SDA]";
};

&gpio1 {
	/* GPIO_008-GPIO_015 */
	gpio-line-names =
		"[UART0_CTS]", /* LSEC pin 3: GPIO_008_UART2_CTS_N */
		"[UART0_RTS]", /* LSEC pin 9: GPIO_009_UART2_RTS_N */
		"[UART0_TXD]", /* LSEC pin 5: GPIO_010_UART2_TXD */
		"[UART0_RXD]", /* LSEC pin 7: GPIO_011_UART2_RXD */
		"[USER_LED5]",
		"GPIO-I", /* LSEC pin 31: GPIO_013_CAM0_RST_N */
		"[USER_LED3]",
		"[USER_LED4]";
};

&gpio2 {
	/* GPIO_016-GPIO_023 */
	gpio-line-names =
		"GPIO-G", /* LSEC pin 29: GPIO_016_LCD_TE0 */
		"[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */
		"[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */
		"GPIO_019_BT_ACTIVE",
		"[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */
		"[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */
		"[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */
		"[I2C3_SDA]"; /* HSEC pin 38: ISP_SDA1 */
};

&gpio3 {
	/* GPIO_024-GPIO_031 */
	gpio-line-names =
		"GPIO_024_WIFI_ACTIVE",
		"GPIO_025_PERST_M.2",
		"[I2C4_SCL]",
		"[I2C4_SDA]",
		"NC",
		"GPIO-H", /* LSEC pin 30: GPIO_029_LCD_RST_N */
		"[USER_LED1]",
		"GPIO-L"; /* LSEC pin 34: GPIO_031 */
};

&gpio4 {
	/* GPIO_032-GPIO_039 */
	gpio-line-names =
		"GPIO-K", /* LSEC pin 33: GPIO_032_CAM1_RST_N */
		"GPIO_033_PMU1_EN",
		"GPIO_034_USBSW_SEL",
		/*
		 * These two pins should be used for SD(IO) data according
		 * to the 96boards specification but seems to be repurposed
		 * for UART 0. They are however named according to the spec.
		 */
		"[SD_DAT1]", /* HSEC pin 3: GPIO_035_UART0_RXD */
		"[SD_DAT2]", /* HSEC pin 5: GPIO_036_UART0_TXD */
		"[UART1_RXD]", /* LSEC pin 13: DEBUG_UART6_RXD */
		"[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */
		"[SOC_GPS_UART3_CTS_N]"; /* TP2304 */
};

&gpio5 {
	/* GPIO_040-GPIO_047 */
	gpio-line-names =
		"[SOC_GPS_UART3_RTS_N]", /* TP2302 */
		"[SOC_GPS_UART3_RXD]", /* TP2303 */
		"[SOC_GPS_UART3_TXD]", /* TP2305 */
		"[SOC_BT_UART4_CTS_N]",
		"[SOC_BT_UART4_RTS_N]",
		"[SOC_BT_UART4_RXD]",
		"[SOC_BT_UART4_TXD]",
		"NC";
};

&gpio6 {
	/* GPIO_048-GPIO_055 */
	gpio-line-names =
		"NC",
		"GPIO_049_USER_LED6",
		"GPIO_050_CAN_RST",
		"GPIO_051_WIFI_EN",
		"GPIO-D", /* LSEC pin 26 */
		"GPIO-J", /* LSEC pin 32 */
		"GPIO_054_BT_EN",
		"[GPIO_055_SEL]";
};

&gpio7 {
	/* GPIO_056-GPIO_063 */
	gpio-line-names =
		"[PCIE_PERST_L]", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};

&gpio8 {
	/* GPIO_064-GPIO_071 */
	gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};

&gpio9 {
	/* GPIO_072-GPIO_079 */
	gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};

&gpio10 {
	/* GPIO_080-GPIO_087 */
	gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};

&gpio11 {
	/* GPIO_088-GPIO_095 */
	gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};

&gpio12 {
	/* GPIO_096-GPIO_103 */
	gpio-line-names = "NC", "", "", "", "", "", "", "";
};

&gpio13 {
	/* GPIO_104-GPIO_111 */
	gpio-line-names = "", "", "", "", "", "", "", "";
};

&gpio14 {
	/* GPIO_112-GPIO_119 */
	gpio-line-names = "", "", "", "", "", "", "", "";
};

&gpio15 {
	/* GPIO_120-GPIO_127 */
	gpio-line-names = "", "", "", "", "", "", "", "";
};

&gpio16 {
	/* GPIO_128-GPIO_135 */
	gpio-line-names =
		"[WL_SDIO_CLK]",
		"[WL_SDIO_CMD]",
		"[WL_SDIO_DATA0]",
		"[WL_SDIO_DATA1]",
		"[WL_SDIO_DATA2]",
		"[WL_SDIO_DATA3]",
		"[ETH_ISOLATE]",
		"NC";
};

&gpio17 {
	/* GPIO_136-GPIO_143 */
	gpio-line-names =
		"[MINI1CLK_EN]", "NC", "", "", "", "", "", "";
};

&gpio18 {
	/* GPIO_144-GPIO_151 */
	gpio-line-names =
		"[SPI1_SCLK]", /* HSEC pin 9: GPIO_144_SPI3_CLK */
		"[SPI1_DIN]", /* HSEC pin 11: GPIO_145_SPI3_DI */
		"[SPI1_DOUT]", /* HSEC pin 1: GPIO_146_SPI3_DO */
		"[SPI1_CS]", /* HSEC pin 7: GPIO_147_SPI3_CS0_N */
		"[POWER_INT_N]",
		"[CDMA_GPS_SYNC]",
		"GPIO_150_PEX_INTA",
		"GPIO_151_CAN_INT";
};

&gpio19 {
	/* GPIO_152-GPIO_159 */
	gpio-line-names = "", "", "", "", "", "", "", "";
};

&gpio20 {
	/* GPIO_160-GPIO_167 */
	gpio-line-names =
		"[SD_CLK]",
		"[SD_CMD]",
		"[SD_DATA0]",
		"[SD_DATA1]",
		"[SD_DATA2]",
		"[SD_DATA3]",
		"GPIO_166_ETHCLK_EN",
		"GPIO_167_USER_LED2";
};

&gpio21 {
	/* GPIO_168-GPIO_175 */
	gpio-line-names =
		"GPIO_168_GPS_EN",
		"GPIO-C", /* LSEC pin 25: GPIO_169_USIM1_CLK */
		"GPIO-E", /* LSEC pin 27: GPIO_170_USIM1_RST */
		"GPIO-B", /* LSEC pin 24: GPIO_171_USIM1_DATA */
		"", "", "", "", "";
};

&gpio22 {
	/* GPIO_176-GPIO_183 */
	gpio-line-names =
		"[PMU_PWR_HOLD]",
		"GPIO_177_WL_WAKEUP_AP",
		"[JTAG_TCK]",
		"[JTAG_TMS]",
		"[JTAG_TDI]",
		"[JTAG_TMS]",
		"GPIO_182_FATAL_ERR",
		"NC";
};

&gpio23 {
	/* GPIO_184-GPIO_191 */
	gpio-line-names =
		"GPIO_184_JTAG_SEL",
		"GPIO-F", /* LSEC pin 28: GPIO_185_LCD_BL_PWM */
		"[I2C0_SCL]", /* LSEC pin 15: GPIO_186_I2C0_SCL */
		"[I2C0_SDA]", /* LSEC pin 17: GPIO_187_I2C0_SDA */
		"[GPIO_188_I2C1_SCL]", /* Actual SoC I2C1_SCL */
		"[GPIO_189_I2C1_SDA]", /* Actual SoC I2C1_SDA */
		"[I2C1_SCL]", /* LSEC pin 19: GPIO_190_I2C2_SCL */
		"[I2C2_SDA]"; /* LSEC pin 21: GPIO_191_I2C2_SDA */
};

&gpio24 {
	/* GPIO_192-GPIO_199 */
	gpio-line-names =
		"[SD_LED]",
		"NC",
		"[PCM_DI]", /* LSEC pin 22: GPIO_194_I2S0_DI */
		"[PCM_DO]", /* LSEC pin 20: GPIO_195_I2S0_DO */
		"[PCM_CLK]", /* LSEC pin 18: GPIO_196_I2S0_XCLK */
		"[PCM_FS]", /* LSEC pin 16: GPIO_197_I2S0_XFS */
		"",
		"[I2S2_DO]";
};

&gpio25 {
	/* GPIO_200-GPIO_207 */
	gpio-line-names =
		"[I2S2_XCLK]",
		"[I2S2_XFS]",
		"GPIO_202_PERST_ETH",
		"GPIO_203_PWRON_DET",
		"GPIO_204_PMU1_IRQ_N",
		"GPIO_205_SD_DET",
		"GPIO_206_GPS_MOTION_INT",
		"GPIO_207_HDMI_SEL";
};

&gpio26 {
	/* GPIO_208-GPIO_215 */
	gpio-line-names =
		"GPIO-A", /* LSEC pin 23: GPIO_208_WAKEUP_SOC */
		"GPIO_209_VBUS_TYPEC",
		"NC",
		"NC",
		"NC",
		"[SPI0_SCLK]", /* LSEC pin 8: GPIO_213_SPI2_CLK */
		"[SPI0_DIN]", /* LSEC pin 10: GPIO_214_SPI2_DI */
		"[SPI0_DOUT]"; /* LSEC pin 14: GPIO_215_SPI2_DO */
};

&gpio27 {
	/* GPIO_216-GPIO_223 */
	gpio-line-names =
		"[SPI0_CS]", /* LSEC pin 12: GPIO_216_SPI2_CS0_N */
		"GPIO_217_HDMI_PD",
		"GPIO_218_GPS_WAKEUP_AP",
		"GPIO_219_M.2CLK_EN",
		"GPIO_220_PERST_MINI",
		"GPIO_221_CC_INT",
		"[PCIE_CLKREQ_L]",
		"NC";
};

&gpio28 {
	/* GPIO_224-GPIO_231 */
	gpio-line-names =
		"[PMU0_INT]",
		"[SPMI_DATA]",
		"[SPMI_CLK]",
		"[CAN_SPI_CLK]",
		"[CAN_SPI_DI]",
		"[CAN_SPI_DO]",
		"[CAN_SPI_CS]",
		"GPIO_231_HDMI_INT";
};

&dwmmc1 {
	bus-width = <0x4>;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	cap-sd-highspeed;
	disable-wp;
	cd-inverted;
	cd-gpios = <&gpio25 5 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&sd_pmx_func
		     &sd_clk_cfg_func
		     &sd_cfg_func>;
	vmmc-supply = <&ldo16>;
	vqmmc-supply = <&ldo9>;
	status = "okay";
};

&dwmmc2 { /* WIFI */
	bus-width = <0x4>;
	non-removable;
	broken-cd;
	cap-power-off-card;
	pinctrl-names = "default";
	pinctrl-0 = <&sdio_pmx_func
		     &sdio_clk_cfg_func
		     &sdio_cfg_func>;
	/* WL_EN */
	vmmc-supply = <&wlan_en>;
	status = "okay";

	wlcore: wlcore@2 {
		compatible = "ti,wl1837";
		reg = <2>;      /* sdio func num */
		/* WL_IRQ, GPIO_177_WL_WAKEUP_AP */
		interrupt-parent = <&gpio22>;
		interrupts = <1 IRQ_TYPE_EDGE_RISING>;
	};
};

&uart0 {
	/* On High speed expansion header */
	label = "HS-UART0";
	status = "okay";
};

&uart2 {
	/* On Low speed expansion header */
	label = "LS-UART0";
	status = "okay";
};

&uart6 {
	/* On Low speed expansion header */
	label = "LS-UART1";
	status = "okay";
};