code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi86.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SN65DSI86 DSI to eDP bridge chip

maintainers:
  - Sandeep Panda <spanda@codeaurora.org>

description: |
  The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
  https://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf

properties:
  compatible:
    const: ti,sn65dsi86

  reg:
    enum: [ 0x2c, 0x2d ]

  enable-gpios:
    maxItems: 1
    description: GPIO specifier for bridge_en pin (active high).

  suspend-gpios:
    maxItems: 1
    description: GPIO specifier for GPIO1 pin on bridge (active low).

  no-hpd:
    type: boolean
    description:
      Set if the HPD line on the bridge isn't hooked up to anything or is
      otherwise unusable.

  vccio-supply:
    description: A 1.8V supply that powers the digital IOs.

  vpll-supply:
    description: A 1.8V supply that powers the DisplayPort PLL.

  vcca-supply:
    description: A 1.2V supply that powers the analog circuits.

  vcc-supply:
    description: A 1.2V supply that powers the digital core.

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1
    description:
      Clock specifier for input reference clock. The reference clock rate must
      be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.

  clock-names:
    const: refclk

  gpio-controller: true
  '#gpio-cells':
    const: 2
    description:
      First cell is pin number, second cell is flags.  GPIO pin numbers are
      1-based to match the datasheet.  See ../../gpio/gpio.txt for more
      information.

  '#pwm-cells':
    const: 1
    description: See ../../pwm/pwm.yaml for description of the cell formats.

  aux-bus:
    $ref: /schemas/display/dp-aux-bus.yaml#

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for MIPI DSI input

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Video port for eDP output (panel or connector).

        properties:
          endpoint:
            $ref: /schemas/graph.yaml#/$defs/endpoint-base
            unevaluatedProperties: false

            properties:
              data-lanes:
                oneOf:
                  - minItems: 1
                    maxItems: 1
                    uniqueItems: true
                    items:
                      enum:
                        - 0
                        - 1
                    description:
                      If you have 1 logical lane the bridge supports routing
                      to either port 0 or port 1.  Port 0 is suggested.
                      See ../../media/video-interface.txt for details.

                  - minItems: 2
                    maxItems: 2
                    uniqueItems: true
                    items:
                      enum:
                        - 0
                        - 1
                    description:
                      If you have 2 logical lanes the bridge supports
                      reordering but only on physical ports 0 and 1.
                      See ../../media/video-interface.txt for details.

                  - minItems: 4
                    maxItems: 4
                    uniqueItems: true
                    items:
                      enum:
                        - 0
                        - 1
                        - 2
                        - 3
                    description:
                      If you have 4 logical lanes the bridge supports
                      reordering in any way.
                      See ../../media/video-interface.txt for details.

              lane-polarities:
                minItems: 1
                maxItems: 4
                items:
                  enum:
                    - 0
                    - 1
                description: See ../../media/video-interface.txt

            dependencies:
              lane-polarities: [data-lanes]

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - vccio-supply
  - vpll-supply
  - vcca-supply
  - vcc-supply
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      bridge@2d {
        compatible = "ti,sn65dsi86";
        reg = <0x2d>;

        interrupt-parent = <&tlmm>;
        interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;

        enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;

        vpll-supply = <&src_pp1800_s4a>;
        vccio-supply = <&src_pp1800_s4a>;
        vcca-supply = <&src_pp1200_l2a>;
        vcc-supply = <&src_pp1200_l2a>;

        clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
        clock-names = "refclk";

        no-hpd;

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;
            endpoint {
              remote-endpoint = <&dsi0_out>;
            };
          };

          port@1 {
            reg = <1>;
            sn65dsi86_out: endpoint {
              remote-endpoint = <&panel_in_edp>;
            };
          };
        };

        aux-bus {
          panel {
            compatible = "boe,nv133fhm-n62";
            power-supply = <&pp3300_dx_edp>;
            backlight = <&backlight>;
            hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;

            port {
              panel_in_edp: endpoint {
                remote-endpoint = <&sn65dsi86_out>;
              };
            };
          };
        };
      };
    };
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      bridge@2d {
        compatible = "ti,sn65dsi86";
        reg = <0x2d>;

        enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>;
        suspend-gpios = <&msmgpio 34 GPIO_ACTIVE_LOW>;

        interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;

        vccio-supply = <&pm8916_l17>;
        vcca-supply = <&pm8916_l6>;
        vpll-supply = <&pm8916_l17>;
        vcc-supply = <&pm8916_l6>;

        clock-names = "refclk";
        clocks = <&input_refclk>;

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;

            edp_bridge_in: endpoint {
              remote-endpoint = <&dsi_out>;
            };
          };

          port@1 {
            reg = <1>;

            edp_bridge_out: endpoint {
              data-lanes = <2 1 3 0>;
              lane-polarities = <0 1 0 1>;
              remote-endpoint = <&edp_panel_in>;
            };
          };
        };
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/ti,tfp410.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TFP410 DPI to DVI encoder

maintainers:
  - Tomi Valkeinen <tomi.valkeinen@ti.com>
  - Jyri Sarha <jsarha@ti.com>

properties:
  compatible:
    const: ti,tfp410

  reg:
    description: I2C address of the device.
    maxItems: 1

  powerdown-gpios:
    maxItems: 1

  ti,deskew:
    description:
      Data de-skew value in 350ps increments, from 0 to 7, as configured
      through the DK[3:1] pins. The de-skew multiplier is computed as
      (DK[3:1] - 4), so it ranges from -4 to 3.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 7

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: DPI input port.

        properties:
          endpoint:
            $ref: /schemas/graph.yaml#/$defs/endpoint-base
            unevaluatedProperties: false

            properties:
              pclk-sample:
                description:
                  Endpoint sampling edge.
                enum:
                  - 0  # Falling edge
                  - 1  # Rising edge
                default: 0

              bus-width:
                description:
                  Endpoint bus width.
                enum:
                  - 12  # 12 data lines connected and dual-edge mode
                  - 24  # 24 data lines connected and single-edge mode
                default: 24

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: DVI output port.

    required:
      - port@0
      - port@1

required:
  - compatible
  - ports

if:
  required:
    - reg
then:
  properties:
    ti,deskew: false
else:
  required:
    - ti,deskew

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    tfp410: encoder {
        compatible = "ti,tfp410";
        powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
        ti,deskew = <3>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                tfp410_in: endpoint {
                    pclk-sample = <1>;
                    bus-width = <24>;
                    remote-endpoint = <&dpi_out>;
                };
            };

            port@1 {
                reg = <1>;
                tfp410_out: endpoint {
                    remote-endpoint = <&dvi_connector_in>;
                };
            };
        };
    };

...

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358762.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Toshiba TC358762 MIPI DSI to MIPI DPI bridge

maintainers:
  - Marek Vasut <marex@denx.de>

description: |
  The TC358762 is bridge device which converts MIPI DSI to MIPI DPI.

properties:
  compatible:
    enum:
      - toshiba,tc358762

  reg:
    maxItems: 1
    description: virtual channel number of a DSI peripheral

  vddc-supply:
    description: Regulator for 1.2V internal core power.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for MIPI DSI input

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Video port for MIPI DPI output (panel or connector).

    required:
      - port@1

required:
  - compatible
  - reg
  - vddc-supply
  - ports

additionalProperties: false

examples:
  - |
    i2c1 {
      #address-cells = <1>;
      #size-cells = <0>;

      bridge@0 {
        reg = <0>;
        compatible = "toshiba,tc358762";
        vddc-supply = <&vcc_1v2_reg>;

        ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;
            bridge_in: endpoint {
              remote-endpoint = <&dsi_out>;
            };
          };

          port@1 {
            reg = <1>;
            bridge_out: endpoint {
              remote-endpoint = <&panel_in>;
            };
          };
        };
      };
    };

...


code:
TC358764 MIPI-DSI to LVDS panel bridge

Required properties:
  - compatible: "toshiba,tc358764"
  - reg: the virtual channel number of a DSI peripheral
  - vddc-supply: core voltage supply, 1.2V
  - vddio-supply: I/O voltage supply, 1.8V or 3.3V
  - vddlvds-supply: LVDS1/2 voltage supply, 3.3V
  - reset-gpios: a GPIO spec for the reset pin

The device node can contain following 'port' child nodes,
according to the OF graph bindings defined in [1]:
  0: DSI Input, not required, if the bridge is DSI controlled
  1: LVDS Output, mandatory

[1]: Documentation/devicetree/bindings/media/video-interfaces.txt

Example:

	bridge@0 {
		reg = <0>;
		compatible = "toshiba,tc358764";
		vddc-supply = <&vcc_1v2_reg>;
		vddio-supply = <&vcc_1v8_reg>;
		vddlvds-supply = <&vcc_3v3_reg>;
		reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>;
		#address-cells = <1>;
		#size-cells = <0>;
		port@1 {
			reg = <1>;
			lvds_ep: endpoint {
				remote-endpoint = <&panel_ep>;
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358767.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Toshiba TC358767 eDP bridge bindings

maintainers:
  - Andrey Gusakov <andrey.gusakov@cogentembedded.com>

description: The TC358767 is bridge device which converts DSI/DPI to eDP/DP

properties:
  compatible:
    const: toshiba,tc358767

  reg:
    enum:
      - 0x68
      - 0x0f
    description: |
        i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins

  clock-names:
    const: "ref"

  clocks:
    maxItems: 1
    description: |
        OF device-tree clock specification for refclk input. The reference.
        clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.

  shutdown-gpios:
    maxItems: 1
    description: |
        OF device-tree gpio specification for SD pin(active high shutdown input)

  reset-gpios:
    maxItems: 1
    description: |
        OF device-tree gpio specification for RSTX pin(active low system reset)

  toshiba,hpd-pin:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum:
      - 0
      - 1
    description: TC358767 GPIO pin number to which HPD is connected to (0 or 1)

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: |
            DSI input port. The remote endpoint phandle should be a
            reference to a valid DSI output endpoint node

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description: array of physical DSI data lane indexes.
                minItems: 1
                items:
                  - const: 1
                  - const: 2
                  - const: 3
                  - const: 4

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
            DPI input/output port. The remote endpoint phandle should be a
            reference to a valid DPI output or input endpoint node.

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
            eDP/DP output port. The remote endpoint phandle should be a
            reference to a valid eDP panel input endpoint node. This port is
            optional, treated as DP panel if not defined

    oneOf:
      - required:
          - port@0
      - required:
          - port@1

required:
  - compatible
  - reg
  - clock-names
  - clocks
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    /* DPI input and eDP output */

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        edp-bridge@68 {
            compatible = "toshiba,tc358767";
            reg = <0x68>;
            shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
            reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
            clock-names = "ref";
            clocks = <&edp_refclk>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@1 {
                    reg = <1>;

                    bridge_in_0: endpoint {
                        remote-endpoint = <&dpi_out>;
                    };
                };

                port@2 {
                    reg = <2>;

                    bridge_out: endpoint {
                        remote-endpoint = <&panel_in>;
                    };
                };
            };
        };
    };
  - |
    /* DPI input and DP output */

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        edp-bridge@68 {
            compatible = "toshiba,tc358767";
            reg = <0x68>;
            shutdown-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
            reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
            clock-names = "ref";
            clocks = <&edp_refclk>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@1 {
                    reg = <1>;

                    bridge_in_1: endpoint {
                        remote-endpoint = <&dpi_out>;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358768.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Toschiba TC358768/TC358778 Parallel RGB to MIPI DSI bridge

maintainers:
  - Peter Ujfalusi <peter.ujfalusi@ti.com>

description: |
  The TC358768/TC358778 is bridge device which converts RGB to DSI.

properties:
  compatible:
    enum:
      - toshiba,tc358768
      - toshiba,tc358778

  reg:
    maxItems: 1
    description: base I2C address of the device

  reset-gpios:
    maxItems: 1
    description: GPIO connected to active low RESX pin

  vddc-supply:
    description: Regulator for 1.2V internal core power.

  vddmipi-supply:
    description: Regulator for 1.2V for the MIPI.

  vddio-supply:
    description: Regulator for 1.8V - 3.3V IO power.

  clocks:
    maxItems: 1

  clock-names:
    const: refclk

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description: |
          Video port for RGB input

        properties:
          endpoint:
            $ref: /schemas/graph.yaml#/$defs/endpoint-base
            unevaluatedProperties: false

            properties:
              data-lines:
                $ref: /schemas/types.yaml#/definitions/uint32
                enum: [ 16, 18, 24 ]

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Video port for DSI output (panel or connector).

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - vddc-supply
  - vddmipi-supply
  - vddio-supply
  - ports

allOf:
  - $ref: ../dsi-controller.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    i2c1 {
      #address-cells = <1>;
      #size-cells = <0>;

      dsi_bridge: dsi@e {
        compatible = "toshiba,tc358768";
        reg = <0xe>;

        clocks = <&tc358768_refclk>;
        clock-names = "refclk";

        reset-gpios = <&pcf_display_board 0 GPIO_ACTIVE_LOW>;

        vddc-supply = <&v1_2d>;
        vddmipi-supply = <&v1_2d>;
        vddio-supply = <&v3_3d>;

        dsi_bridge_ports: ports {
          #address-cells = <1>;
          #size-cells = <0>;

          port@0 {
            reg = <0>;
            rgb_in: endpoint {
              remote-endpoint = <&dpi_out>;
              data-lines = <24>;
            };
          };

          port@1 {
            reg = <1>;
            dsi_out: endpoint {
              remote-endpoint = <&lcd_in>;
            };
          };
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358775.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Toshiba TC358775 DSI to LVDS bridge bindings

maintainers:
  - Vinay Simha BN <simhavcs@gmail.com>

description: |
  This binding supports DSI to LVDS bridge TC358775

  MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
  Video frame size:
  Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
  limited by 135 MHz LVDS speed
  Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
  panel, limited by 270 MHz LVDS speed.

properties:
  compatible:
    const: toshiba,tc358775

  reg:
    maxItems: 1
    description: i2c address of the bridge, 0x0f

  vdd-supply:
    description: 1.2V LVDS Power Supply

  vddio-supply:
    description: 1.8V IO Power Supply

  stby-gpios:
    maxItems: 1
    description: Standby pin, Low active

  reset-gpios:
    maxItems: 1
    description: Hardware reset, Low active

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          DSI Input. The remote endpoint phandle should be a
          reference to a valid mipi_dsi_host device node.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Video port for LVDS output (panel or connector).

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: |
          Video port for Dual link LVDS output (panel or connector).

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - vdd-supply
  - vddio-supply
  - stby-gpios
  - reset-gpios
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    /* For single-link LVDS display panel */

    i2c@78b8000 {
        /* On High speed expansion */
        label = "HS-I2C2";
        reg = <0x078b8000 0x500>;
        clock-frequency = <400000>; /* fastmode operation */
        #address-cells = <1>;
        #size-cells = <0>;

        tc_bridge: bridge@f {
            compatible = "toshiba,tc358775";
            reg = <0x0f>;

            vdd-supply = <&pm8916_l2>;
            vddio-supply = <&pm8916_l6>;

            stby-gpios = <&msmgpio 99 GPIO_ACTIVE_LOW>;
            reset-gpios = <&msmgpio 72 GPIO_ACTIVE_LOW>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    d2l_in_test: endpoint {
                        remote-endpoint = <&dsi0_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    lvds_out: endpoint {
                        remote-endpoint = <&panel_in>;
                    };
                };
            };
        };
    };

    dsi@1a98000 {
        reg = <0x1a98000 0x25c>;
        reg-names = "dsi_ctrl";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@1 {
                reg = <1>;
                dsi0_out: endpoint {
                    remote-endpoint = <&d2l_in_test>;
                    data-lanes = <0 1 2 3>;
                };
             };
         };
     };

  - |
    /* For dual-link LVDS display panel */

    i2c@78b8000 {
        /* On High speed expansion */
        label = "HS-I2C2";
        reg = <0x078b8000 0x500>;
        clock-frequency = <400000>; /* fastmode operation */
        #address-cells = <1>;
        #size-cells = <0>;

        tc_bridge_dual: bridge@f {
            compatible = "toshiba,tc358775";
            reg = <0x0f>;

            vdd-supply = <&pm8916_l2>;
            vddio-supply = <&pm8916_l6>;

            stby-gpios = <&msmgpio 99 GPIO_ACTIVE_LOW>;
            reset-gpios = <&msmgpio 72 GPIO_ACTIVE_LOW>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    d2l_in_dual: endpoint {
                        remote-endpoint = <&dsi0_out_dual>;
                    };
                };

                port@1 {
                    reg = <1>;
                    lvds0_out: endpoint {
                        remote-endpoint = <&panel_in0>;
                    };
                };

                port@2 {
                    reg = <2>;
                    lvds1_out: endpoint {
                        remote-endpoint = <&panel_in1>;
                    };
                };
            };
        };
    };

    dsi@1a98000 {
        reg = <0x1a98000 0x25c>;
        reg-names = "dsi_ctrl";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@1 {
                reg = <1>;
                dsi0_out_dual: endpoint {
                    remote-endpoint = <&d2l_in_dual>;
                    data-lanes = <0 1 2 3>;
                };
             };
         };
     };
...


code:
* Currus Logic CLPS711X Framebuffer

Required properties:
- compatible: Shall contain "cirrus,ep7209-fb".
- reg       : Physical base address and length of the controller's registers +
              location and size of the framebuffer memory.
- clocks    : phandle + clock specifier pair of the FB reference clock.
- display   : phandle to a display node as described in
              Documentation/devicetree/bindings/display/panel/display-timing.txt.
              Additionally, the display node has to define properties:
  - bits-per-pixel: Bits per pixel.
  - ac-prescale   : LCD AC bias frequency. This frequency is the required
                    AC bias frequency for a given manufacturer's LCD plate.
  - cmap-invert   : Invert the color levels (Optional).

Optional properties:
- lcd-supply: Regulator for LCD supply voltage.

Example:
	fb: fb@800002c0 {
		compatible = "cirrus,ep7312-fb", "cirrus,ep7209-fb";
		reg = <0x800002c0 0xd44>, <0x60000000 0xc000>;
		clocks = <&clks 2>;
		lcd-supply = <&reg5v0>;
		display = <&display>;
	};

	display: display {
		model = "320x240x4";
		bits-per-pixel = <4>;
		ac-prescale = <17>;

		display-timings {
			native-mode = <&timing0>;
			timing0: 320x240 {
				hactive = <320>;
				hback-porch = <0>;
				hfront-porch = <0>;
				hsync-len = <0>;
				vactive = <240>;
				vback-porch = <0>;
				vfront-porch = <0>;
				vsync-len = <0>;
				clock-frequency = <6500000>;
			};
		};
	};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/connector/analog-tv-connector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog TV Connector

maintainers:
  - Laurent Pinchart <Laurent.pinchart@ideasonboard.com>

properties:
  compatible:
    enum:
      - composite-video-connector
      - svideo-connector

  label: true

  sdtv-standards:
    description:
      Limit the supported TV standards on a connector to the given ones. If
      not specified all TV standards are allowed. Possible TV standards are
      defined in include/dt-bindings/display/sdtv-standards.h.
    $ref: /schemas/types.yaml#/definitions/uint32

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description: Connection to controller providing analog TV signals

required:
  - compatible
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/display/sdtv-standards.h>

    connector {
        compatible = "composite-video-connector";
        label = "tv";
        sdtv-standards = <(SDTV_STD_PAL | SDTV_STD_NTSC)>;

        port {
            tv_connector_in: endpoint {
                remote-endpoint = <&venc_out>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/connector/dp-connector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DisplayPort Connector

maintainers:
  - Tomi Valkeinen <tomi.valkeinen@ti.com>

properties:
  compatible:
    const: dp-connector

  label: true

  type:
    enum:
      - full-size
      - mini

  hpd-gpios:
    description: A GPIO line connected to HPD
    maxItems: 1

  dp-pwr-supply:
    description: Power supply for the DP_PWR pin

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description: Connection to controller providing DP signals

required:
  - compatible
  - type
  - port

additionalProperties: false

examples:
  - |
    connector {
        compatible = "dp-connector";
        label = "dp0";
        type = "full-size";

        port {
            dp_connector_in: endpoint {
                remote-endpoint = <&dp_out>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/connector/dvi-connector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DVI Connector

maintainers:
  - Laurent Pinchart <Laurent.pinchart@ideasonboard.com>

properties:
  compatible:
    const: dvi-connector

  label: true

  hpd-gpios:
    description: A GPIO line connected to HPD
    maxItems: 1

  ddc-i2c-bus:
    description: phandle link to the I2C controller used for DDC EDID probing
    $ref: /schemas/types.yaml#/definitions/phandle

  analog:
    type: boolean
    description: the connector has DVI analog pins

  digital:
    type: boolean
    description: the connector has DVI digital pins

  dual-link:
    type: boolean
    description: the connector has pins for DVI dual-link

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description: Connection to controller providing DVI signals

required:
  - compatible
  - port

anyOf:
  - required:
      - analog
  - required:
      - digital

additionalProperties: false

examples:
  - |
    connector {
        compatible = "dvi-connector";
        label = "dvi";

        digital;

        ddc-i2c-bus = <&i2c3>;

        port {
            dvi_connector_in: endpoint {
                remote-endpoint = <&tfp410_out>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/connector/hdmi-connector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: HDMI Connector

maintainers:
  - Laurent Pinchart <Laurent.pinchart@ideasonboard.com>

properties:
  compatible:
    const: hdmi-connector

  type:
    description: The HDMI connector type
    enum:
      - a   # Standard full size
      - b   # Never deployed?
      - c   # Mini
      - d   # Micro
      - e   # automotive

  label: true

  hpd-gpios:
    description: A GPIO line connected to HPD
    maxItems: 1

  ddc-i2c-bus:
    description: phandle link to the I2C controller used for DDC EDID probing
    $ref: /schemas/types.yaml#/definitions/phandle

  ddc-en-gpios:
    description: GPIO signal to enable DDC bus
    maxItems: 1

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description: Connection to controller providing HDMI signals

required:
  - compatible
  - port
  - type

additionalProperties: false

examples:
  - |
    connector {
        compatible = "hdmi-connector";
        label = "hdmi";

        type = "a";

        port {
            hdmi_connector_in: endpoint {
                remote-endpoint = <&tpd12s015_out>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/connector/vga-connector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: VGA Connector

maintainers:
  - Laurent Pinchart <Laurent.pinchart@ideasonboard.com>

properties:
  compatible:
    const: vga-connector

  label: true

  ddc-i2c-bus:
    description: phandle link to the I2C controller used for DDC EDID probing
    $ref: /schemas/types.yaml#/definitions/phandle

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description: Connection to controller providing VGA signals

required:
  - compatible
  - port

additionalProperties: false

examples:
  - |
    connector {
        compatible = "vga-connector";
        label = "vga";

        ddc-i2c-bus = <&i2c3>;

        port {
            vga_connector_in: endpoint {
                remote-endpoint = <&adv7123_out>;
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/dp-aux-bus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DisplayPort AUX bus

maintainers:
  - Douglas Anderson <dianders@chromium.org>

description:
  DisplayPort controllers provide a control channel to the sinks that
  are hooked up to them. This is the DP AUX bus. Over the DP AUX bus
  we can query properties about a sink and also configure it. In
  particular, DP sinks support DDC over DP AUX which allows tunneling
  a standard I2C DDC connection over the AUX channel.

  To model this relationship, DP sinks should be placed as children
  of the DP controller under the "aux-bus" node.

  At the moment, this binding only handles the eDP case. It is
  possible it will be extended in the future to handle the DP case.
  For DP, presumably a connector would be listed under the DP AUX
  bus instead of a panel.

properties:
  $nodename:
    const: "aux-bus"

  panel:
    $ref: panel/panel-common.yaml#

additionalProperties: false

required:
  - panel


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/dsi-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common Properties for DSI Display Panels

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  This document defines device tree properties common to DSI, Display
  Serial Interface controllers and attached panels. It doesn't constitute
  a device tree binding specification by itself but is meant to be referenced
  by device tree bindings.

  When referenced from panel device tree bindings the properties defined in
  this document are defined as follows. The panel device tree bindings are
  responsible for defining whether each property is required or optional.

  Notice: this binding concerns DSI panels connected directly to a master
  without any intermediate port graph to the panel. Each DSI master
  can control one to four virtual channels to one panel. Each virtual
  channel should have a node "panel" for their virtual channel with their
  reg-property set to the virtual channel number, usually there is just
  one virtual channel, number 0.

properties:
  $nodename:
    pattern: "^dsi(@.*)?$"

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

patternProperties:
  "^panel@[0-3]$":
    description: Panels connected to the DSI link
    type: object

    properties:
      reg:
        minimum: 0
        maximum: 3
        description:
          The virtual channel number of a DSI peripheral. Must be in the range
          from 0 to 3, as DSI uses a 2-bit addressing scheme. Some DSI
          peripherals respond to more than a single virtual channel. In that
          case the reg property can take multiple entries, one for each virtual
          channel that the peripheral responds to.

      clock-master:
        type: boolean
        description:
          Should be enabled if the host is being used in conjunction with
          another DSI host to drive the same peripheral. Hardware supporting
          such a configuration generally requires the data on both the busses
          to be driven by the same clock. Only the DSI host instance
          controlling this clock should contain this property.

      enforce-video-mode:
        type: boolean
        description:
          The best option is usually to run a panel in command mode, as this
          gives better control over the panel hardware. However for different
          reasons like broken hardware, missing features or testing, it may be
          useful to be able to force a command mode-capable panel into video
          mode.

    required:
      - reg

additionalProperties: true

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    dsi@a0351000 {
        reg = <0xa0351000 0x1000>;
        #address-cells = <1>;
        #size-cells = <0>;
        panel@0 {
            compatible = "sony,acx424akp";
            reg = <0>;
            vddi-supply = <&ab8500_ldo_aux1_reg>;
            reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
        };
    };

...


code:
The Exynos display port interface should be configured based on
the type of panel connected to it.

We use two nodes:
	-dp-controller node
	-dptx-phy node(defined inside dp-controller node)

For the DP-PHY initialization, we use the dptx-phy node.
Required properties for dptx-phy: deprecated, use phys and phy-names
	-reg: deprecated
		Base address of DP PHY register.
	-samsung,enable-mask: deprecated
		The bit-mask used to enable/disable DP PHY.

For the Panel initialization, we read data from dp-controller node.
Required properties for dp-controller:
	-compatible:
		should be "samsung,exynos5-dp".
	-reg:
		physical base address of the controller and length
		of memory mapped region.
	-interrupts:
		interrupt combiner values.
	-clocks:
		from common clock binding: handle to dp clock.
	-clock-names:
		from common clock binding: Shall be "dp".
	-phys:
		from general PHY binding: the phandle for the PHY device.
	-phy-names:
		from general PHY binding: Should be "dp".

Optional properties for dp-controller:
	-interlaced:
		interlace scan mode.
			Progressive if defined, Interlaced if not defined
	-vsync-active-high:
		VSYNC polarity configuration.
			High if defined, Low if not defined
	-hsync-active-high:
		HSYNC polarity configuration.
			High if defined, Low if not defined
	-samsung,hpd-gpio:
		Hotplug detect GPIO.
			Indicates which GPIO should be used for hotplug
			detection
	-video interfaces: Device node can contain video interface port
			nodes according to [1].
	- display-timings: timings for the connected panel as described by
		Documentation/devicetree/bindings/display/panel/display-timing.txt

For the below properties, please refer to Analogix DP binding document:
 * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
	-phys (required)
	-phy-names (required)
	-hpd-gpios (optional)
	 force-hpd (optional)

Deprecated properties for DisplayPort:
-interlaced:            deprecated prop that can parsed from drm_display_mode.
-vsync-active-high:     deprecated prop that can parsed from drm_display_mode.
-hsync-active-high:     deprecated prop that can parsed from drm_display_mode.
-samsung,ycbcr-coeff:   deprecated prop that can parsed from drm_display_mode.
-samsung,dynamic-range: deprecated prop that can parsed from drm_display_mode.
-samsung,color-space:   deprecated prop that can parsed from drm_display_info.
-samsung,color-depth:   deprecated prop that can parsed from drm_display_info.
-samsung,link-rate:     deprecated prop that can reading from monitor by dpcd method.
-samsung,lane-count:    deprecated prop that can reading from monitor by dpcd method.
-samsung,hpd-gpio:      deprecated name for hpd-gpios.

-------------------------------------------------------------------------------

Example:

SOC specific portion:
	dp-controller {
		compatible = "samsung,exynos5-dp";
		reg = <0x145b0000 0x10000>;
		interrupts = <10 3>;
		interrupt-parent = <&combiner>;
		clocks = <&clock 342>;
		clock-names = "dp";

		phys = <&dp_phy>;
		phy-names = "dp";
	};

Board Specific portion:
	dp-controller {
		display-timings {
			native-mode = <&lcd_timing>;
			lcd_timing: 1366x768 {
				clock-frequency = <70589280>;
				hactive = <1366>;
				vactive = <768>;
				hfront-porch = <40>;
				hback-porch = <40>;
				hsync-len = <32>;
				vback-porch = <10>;
				vfront-porch = <12>;
				vsync-len = <6>;
			};
		};

		ports {
			port@0 {
				dp_out: endpoint {
					remote-endpoint = <&bridge_in>;
				};
			};
		};
	};


code:
Exynos MIPI DSI Master

Required properties:
  - compatible: value should be one of the following
		"samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
		"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
		"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
		"samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
		"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
  - reg: physical base address and length of the registers set for the device
  - interrupts: should contain DSI interrupt
  - clocks: list of clock specifiers, must contain an entry for each required
    entry in clock-names
  - clock-names: should include "bus_clk"and "sclk_mipi" entries
		 the use of "pll_clk" is deprecated
  - phys: list of phy specifiers, must contain an entry for each required
    entry in phy-names
  - phy-names: should include "dsim" entry
  - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
  - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
  - samsung,pll-clock-frequency: specifies frequency of the oscillator clock
  - #address-cells, #size-cells: should be set respectively to <1> and <0>
    according to DSI host bindings (see MIPI DSI bindings [1])
  - samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst
    mode
  - samsung,esc-clock-frequency: specifies DSI frequency in escape mode

Optional properties:
  - power-domains: a phandle to DSIM power domain node

Child nodes:
  Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).

Video interfaces:
  Device node can contain following video interface port nodes according to [2]:
  0: RGB input,
  1: DSI output

[1]: Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt

Example:

	dsi@11c80000 {
		compatible = "samsung,exynos4210-mipi-dsi";
		reg = <0x11C80000 0x10000>;
		interrupts = <0 79 0>;
		clocks = <&clock 286>, <&clock 143>;
		clock-names = "bus_clk", "sclk_mipi";
		phys = <&mipi_phy 1>;
		phy-names = "dsim";
		vddcore-supply = <&vusb_reg>;
		vddio-supply = <&vmipi_reg>;
		power-domains = <&pd_lcd0>;
		#address-cells = <1>;
		#size-cells = <0>;
		samsung,pll-clock-frequency = <24000000>;

		panel@1 {
			reg = <0>;
			...
			port {
				panel_ep: endpoint {
					remote-endpoint = <&dsi_ep>;
				};
			};
		};

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				decon_to_mic: endpoint {
					remote-endpoint = <&mic_to_decon>;
				};
			};

			port@1 {
				reg = <1>;
				dsi_ep: endpoint {
					reg = <0>;
					samsung,burst-clock-frequency = <500000000>;
					samsung,esc-clock-frequency = <20000000>;
					remote-endpoint = <&panel_ep>;
				};
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/faraday,tve200.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Faraday TV Encoder TVE200

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

properties:
  compatible:
    oneOf:
      - const: faraday,tve200
      - items:
          - const: cortina,gemini-tvc
          - const: faraday,tve200

  reg:
    maxItems: 1

  interrupts:
    minItems: 1

  clock-names:
    items:
      - const: PCLK
      - const: TVE

  clocks:
    minItems: 2

  resets:
    minItems: 1

  port:
    $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - interrupts
  - clock-names
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/cortina,gemini-clock.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/reset/cortina,gemini-reset.h>
    display-controller@6a000000 {
      compatible = "faraday,tve200";
      reg = <0x6a000000 0x1000>;
      interrupts = <13 IRQ_TYPE_EDGE_RISING>;
      resets = <&syscon GEMINI_RESET_TVC>;
      clocks = <&syscon GEMINI_CLK_GATE_TVC>,
               <&syscon GEMINI_CLK_TVC>;
      clock-names = "PCLK", "TVE";

      port {
        display_out: endpoint {
          remote-endpoint = <&panel_in>;
        };
      };
    };


code:
Device Tree bindings for Freescale DCU DRM Driver

Required properties:
- compatible:		Should be one of
	* "fsl,ls1021a-dcu".
	* "fsl,vf610-dcu".

- reg:			Address and length of the register set for dcu.
- clocks:		Handle to "dcu" and "pix" clock (in the order below)
			This can be the same clock (e.g. LS1021a)
			See ../clocks/clock-bindings.txt for details.
- clock-names:		Should be "dcu" and "pix"
			See ../clocks/clock-bindings.txt for details.
- big-endian		Boolean property, LS1021A DCU registers are big-endian.
- port			Video port for the panel output

Optional properties:
- fsl,tcon:		The phandle to the timing controller node.

Examples:
dcu: dcu@2ce0000 {
	compatible = "fsl,ls1021a-dcu";
	reg = <0x0 0x2ce0000 0x0 0x10000>;
	clocks = <&platform_clk 0>, <&platform_clk 0>;
	clock-names = "dcu", "pix";
	big-endian;
	fsl,tcon = <&tcon>;

	port {
		dcu_out: endpoint {
			remote-endpoint = <&panel_out>;
	     };
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/fsl,lcdif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale/NXP i.MX LCD Interface (LCDIF)

maintainers:
  - Marek Vasut <marex@denx.de>
  - Stefan Agner <stefan@agner.ch>

description: |
  (e)LCDIF display controller found in the Freescale/NXP i.MX SoCs.

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx23-lcdif
          - fsl,imx28-lcdif
          - fsl,imx6sx-lcdif
          - fsl,imx8mp-lcdif
      - items:
          - enum:
              - fsl,imx6sl-lcdif
              - fsl,imx6sll-lcdif
              - fsl,imx6ul-lcdif
              - fsl,imx7d-lcdif
              - fsl,imx8mm-lcdif
              - fsl,imx8mn-lcdif
              - fsl,imx8mq-lcdif
          - const: fsl,imx6sx-lcdif

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Pixel clock
      - description: Bus clock
      - description: Display AXI clock
    minItems: 1

  clock-names:
    items:
      - const: pix
      - const: axi
      - const: disp_axi
    minItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description: The LCDIF output port

required:
  - compatible
  - reg
  - clocks
  - interrupts
  - port

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx6sx-lcdif
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 3
        clock-names:
          minItems: 2
          maxItems: 3
      required:
        - clock-names
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8mp-lcdif
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          minItems: 3
          maxItems: 3
      required:
        - clock-names
        - power-domains
  - if:
      not:
        properties:
          compatible:
            contains:
              enum:
                - fsl,imx6sx-lcdif
                - fsl,imx8mp-lcdif
    then:
      properties:
        clocks:
          maxItems: 1
        clock-names:
          maxItems: 1

examples:
  - |
    #include <dt-bindings/clock/imx6sx-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    display-controller@2220000 {
        compatible = "fsl,imx6sx-lcdif";
        reg = <0x02220000 0x4000>;
        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
                 <&clks IMX6SX_CLK_LCDIF_APB>,
                 <&clks IMX6SX_CLK_DISPLAY_AXI>;
        clock-names = "pix", "axi", "disp_axi";

        port {
            endpoint {
                remote-endpoint = <&panel_in>;
            };
        };
    };

...


code:
Device Tree bindings for Freescale TCON Driver

Required properties:
- compatible:		Should be one of
	* "fsl,vf610-tcon".

- reg:			Address and length of the register set for tcon.
- clocks:		From common clock binding: handle to tcon ipg clock.
- clock-names:		From common clock binding: Shall be "ipg".

Examples:
timing-controller@4003d000 {
	compatible = "fsl,vf610-tcon";
	reg = <0x4003d000 0x1000>;
	clocks = <&clks VF610_CLK_TCON0>;
	clock-names = "ipg";
};


code:
Android Goldfish framebuffer

Android Goldfish framebuffer device used by Android emulator.

Required properties:

- compatible : should contain "google,goldfish-fb"
- reg        : <registers mapping>
- interrupts : <interrupt mapping>

Example:

	display-controller@1f008000 {
		compatible = "google,goldfish-fb";
		interrupts = <0x10>;
		reg = <0x1f008000 0x100>;
	};


code:
Himax HX8357D display panels

This binding is for display panels using a Himax HX8357D controller in SPI
mode, such as the Adafruit 3.5" TFT for Raspberry Pi.

Required properties:
- compatible:	"adafruit,yx350hv15", "himax,hx8357d"
- dc-gpios:	D/C pin
- reg:		address of the panel on the SPI bus

The node for this driver must be a child node of a SPI controller, hence
all mandatory properties described in ../spi/spi-bus.txt must be specified.

Optional properties:
- rotation:	panel rotation in degrees counter clockwise (0,90,180,270)
- backlight:	phandle of the backlight device attached to the panel

Example:
	display@0{
		compatible = "adafruit,yx350hv15", "himax,hx8357d";
		reg = <0>;
		spi-max-frequency = <32000000>;
		dc-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
		rotation = <90>;
		backlight = <&backlight>;
	};


code:
Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver

A DSI Host Controller resides in the middle of display controller and external
HDMI converter or panel.

Required properties:
- compatible: value should be "hisilicon,hi6220-dsi".
- reg: physical base address and length of dsi controller's registers.
- clocks: contains APB clock phandle + clock-specifier pair.
- clock-names: should be "pclk".
- ports: contains DSI controller input and output sub port.
  The input port connects to ADE output port with the reg value "0".
  The output port with the reg value "1", it could connect to panel or
  any other bridge endpoints.
  See Documentation/devicetree/bindings/graph.txt for more device graph info.

A example of HiKey board hi6220 SoC and board specific DT entry:
Example:

SoC specific:
	dsi: dsi@f4107800 {
		compatible = "hisilicon,hi6220-dsi";
		reg = <0x0 0xf4107800 0x0 0x100>;
		clocks = <&media_ctrl  HI6220_DSI_PCLK>;
		clock-names = "pclk";
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* 0 for input port */
			port@0 {
				reg = <0>;
				dsi_in: endpoint {
					remote-endpoint = <&ade_out>;
				};
			};
		};
	};

Board specific:
	&dsi {
		status = "ok";

		ports {
			/* 1 for output port */
			port@1 {
				reg = <1>;

				dsi_out0: endpoint@0 {
					remote-endpoint = <&adv7533_in>;
				};
			};
		};
	};

	&i2c2 {
		...

		adv7533: adv7533@39 {
			...

			port {
				adv7533_in: endpoint {
					remote-endpoint = <&dsi_out0>;
				};
			};
		};
	};


code:
Device-Tree bindings for hisilicon ADE display controller driver

ADE (Advanced Display Engine) is the display controller which grab image
data from memory, do composition, do post image processing, generate RGB
timing stream and transfer to DSI.

Required properties:
- compatible: value should be "hisilicon,hi6220-ade".
- reg: physical base address and length of the ADE controller's registers.
- hisilicon,noc-syscon: ADE NOC QoS syscon.
- resets: The ADE reset controller node.
- interrupt: the ldi vblank interrupt number used.
- clocks: a list of phandle + clock-specifier pairs, one for each entry
  in clock-names.
- clock-names: should contain:
  "clk_ade_core" for the ADE core clock.
  "clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
  jpeg codec.
  "clk_ade_pix" for the ADE pixel clock.
- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
  phandle + clock-specifier pairs.
- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
  The rate of "clk_ade_core" could be "360000000" or "180000000";
  The rate of "clk_codec_jpeg" could be or less than "1440000000".
  These rate values could be configured according to performance and power
  consumption.
- port: the output port. This contains one endpoint subnode, with its
  remote-endpoint set to the phandle of the connected DSI input endpoint.
  See Documentation/devicetree/bindings/graph.txt for more device graph info.

Optional properties:
- dma-coherent: Present if dma operations are coherent.

A example of HiKey board hi6220 SoC specific DT entry:
Example:

	ade: ade@f4100000 {
		compatible = "hisilicon,hi6220-ade";
		reg = <0x0 0xf4100000 0x0 0x7800>;
		reg-names = "ade_base";
		hisilicon,noc-syscon = <&medianoc_ade>;
		resets = <&media_ctrl MEDIA_ADE>;
		interrupts = <0 115 4>; /* ldi interrupt */

		clocks = <&media_ctrl HI6220_ADE_CORE>,
			 <&media_ctrl HI6220_CODEC_JPEG>,
			 <&media_ctrl HI6220_ADE_PIX_SRC>;
		/*clock name*/
		clock-names  = "clk_ade_core",
			       "clk_codec_jpeg",
			       "clk_ade_pix";

		assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
			<&media_ctrl HI6220_CODEC_JPEG>;
		assigned-clock-rates = <360000000>, <288000000>;
		dma-coherent;

		port {
			ade_out: endpoint {
				remote-endpoint = <&dsi_in>;
			};
		};
	};


code:
Ilitek ILI9225 display panels

This binding is for display panels using an Ilitek ILI9225 controller in SPI
mode.

Required properties:
- compatible:	"vot,v220hf01a-t", "ilitek,ili9225"
- rs-gpios:	Register select signal
- reset-gpios:	Reset pin

The node for this driver must be a child node of a SPI controller, hence
all mandatory properties described in ../spi/spi-bus.txt must be specified.

Optional properties:
- rotation:	panel rotation in degrees counter clockwise (0,90,180,270)

Example:
	display@0{
		compatible = "vot,v220hf01a-t", "ilitek,ili9225";
		reg = <0>;
		spi-max-frequency = <12000000>;
		rs-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
		rotation = <270>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/ilitek,ili9486.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ilitek ILI9486 display panels

maintainers:
  - Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>

description:
  This binding is for display panels using an Ilitek ILI9486 controller in SPI
  mode.

allOf:
  - $ref: panel/panel-common.yaml#

properties:
  compatible:
    items:
      - enum:
          # Waveshare 3.5" 320x480 Color TFT LCD
          - waveshare,rpi-lcd-35
          # Ozzmaker 3.5" 320x480 Color TFT LCD
          - ozzmaker,piscreen
      - const: ilitek,ili9486

  spi-max-frequency:
    maximum: 32000000

  dc-gpios:
    maxItems: 1
    description: Display data/command selection (D/CX)

  backlight: true
  reg: true
  reset-gpios: true
  rotation: true

required:
  - compatible
  - reg
  - dc-gpios
  - reset-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    backlight: backlight {
            compatible = "gpio-backlight";
            gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
    };
    spi {
            #address-cells = <1>;
            #size-cells = <0>;

            display@0{
                    compatible = "waveshare,rpi-lcd-35", "ilitek,ili9486";
                    reg = <0>;
                    spi-max-frequency = <32000000>;
                    dc-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
                    reset-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
                    rotation = <180>;
                    backlight = <&backlight>;
            };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX LCD Controller, found on i.MX1, i.MX21, i.MX25 and i.MX27

maintainers:
  - Sascha Hauer <s.hauer@pengutronix.de>
  - Pengutronix Kernel Team <kernel@pengutronix.de>

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx1-fb
          - fsl,imx21-fb
      - items:
          - enum:
              - fsl,imx25-fb
              - fsl,imx27-fb
          - const: fsl,imx21-fb

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: ipg
      - const: ahb
      - const: per

  display:
    $ref: /schemas/types.yaml#/definitions/phandle

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

  lcd-supply:
    description:
      Regulator for LCD supply voltage.

  fsl,dmacr:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Override value for DMA Control Register

  fsl,lpccr:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Contrast Control Register value.

  fsl,lscr1:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      LCDC Sharp Configuration Register value.

required:
  - compatible
  - clocks
  - clock-names
  - display
  - interrupts
  - reg

additionalProperties: false

examples:
  - |
    imxfb: fb@10021000 {
        compatible = "fsl,imx21-fb";
        interrupts = <61>;
        reg = <0x10021000 0x1000>;
        display = <&display0>;
        clocks = <&clks 103>, <&clks 49>, <&clks 66>;
        clock-names = "ipg", "ahb", "per";
    };

    display0: display0 {
        model = "Primeview-PD050VL1";
        bits-per-pixel = <16>;
        fsl,pcr = <0xf0c88080>; /* non-standard but required */

        display-timings {
            native-mode = <&timing_disp0>;
            timing_disp0: timing0 {
                hactive = <640>;
                vactive = <480>;
                hback-porch = <112>;
                hfront-porch = <36>;
                hsync-len = <32>;
                vback-porch = <33>;
                vfront-porch = <33>;
                vsync-len = <2>;
                clock-frequency = <25000000>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX6 DWC HDMI TX Encoder

maintainers:
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
  with a companion PHY IP.

allOf:
  - $ref: ../bridge/synopsys,dw-hdmi.yaml#

properties:
  compatible:
    enum:
      - fsl,imx6dl-hdmi
      - fsl,imx6q-hdmi

  reg-io-width:
    const: 1

  clocks:
    maxItems: 2

  clock-names:
    maxItems: 2

  ddc-i2c-bus:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      The HDMI DDC bus can be connected to either a system I2C master or the
      functionally-reduced I2C master contained in the DWC HDMI. When connected
      to a system I2C master this property contains a phandle to that I2C
      master controller.

  gpr:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle to the iomuxc-gpr region containing the HDMI multiplexer control
      register.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports
    description: |
      This device has four video ports, corresponding to the four inputs of the
      HDMI multiplexer. Each port shall have a single endpoint.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: First input of the HDMI multiplexer

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: Second input of the HDMI multiplexer

      port@2:
        $ref: /schemas/graph.yaml#/properties/port
        description: Third input of the HDMI multiplexer

      port@3:
        $ref: /schemas/graph.yaml#/properties/port
        description: Fourth input of the HDMI multiplexer

    anyOf:
      - required:
          - port@0
      - required:
          - port@1
      - required:
          - port@2
      - required:
          - port@3

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - gpr
  - interrupts
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx6qdl-clock.h>

    hdmi: hdmi@120000 {
        reg = <0x00120000 0x9000>;
        interrupts = <0 115 0x04>;
        gpr = <&gpr>;
        clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
                 <&clks IMX6QDL_CLK_HDMI_ISFR>;
        clock-names = "iahb", "isfr";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                hdmi_mux_0: endpoint {
                    remote-endpoint = <&ipu1_di0_hdmi>;
                };
            };

            port@1 {
                reg = <1>;

                hdmi_mux_1: endpoint {
                    remote-endpoint = <&ipu1_di1_hdmi>;
                };
            };
        };
    };

...


code:
Freescale i.MX DRM master device
================================

The freescale i.MX DRM master device is a virtual device needed to list all
IPU or other display interface nodes that comprise the graphics subsystem.

Required properties:
- compatible: Should be "fsl,imx-display-subsystem"
- ports: Should contain a list of phandles pointing to display interface ports
  of IPU devices

example:

display-subsystem {
	compatible = "fsl,imx-display-subsystem";
	ports = <&ipu_di0>;
};

Freescale i.MX IPUv3
====================

Required properties:
- compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
  - imx51
  - imx53
  - imx6q
  - imx6qp
- reg: should be register base and length as documented in the
  datasheet
- interrupts: Should contain sync interrupt and error interrupt,
  in this order.
- resets: phandle pointing to the system reset controller and
          reset line index, see reset/fsl,imx-src.txt for details
Additional required properties for fsl,imx6qp-ipu:
- fsl,prg: phandle to prg node associated with this IPU instance
Optional properties:
- port@[0-3]: Port nodes with endpoint definitions as defined in
  Documentation/devicetree/bindings/media/video-interfaces.txt.
  Ports 0 and 1 should correspond to CSI0 and CSI1,
  ports 2 and 3 should correspond to DI0 and DI1, respectively.

example:

ipu: ipu@18000000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx53-ipu";
	reg = <0x18000000 0x080000000>;
	interrupts = <11 10>;
	resets = <&src 2>;

	ipu_di0: port@2 {
		reg = <2>;

		ipu_di0_disp0: endpoint {
			remote-endpoint = <&display_in>;
		};
	};
};

Freescale i.MX PRE (Prefetch Resolve Engine)
============================================

Required properties:
- compatible: should be "fsl,imx6qp-pre"
- reg: should be register base and length as documented in the
  datasheet
- clocks : phandle to the PRE axi clock input, as described
  in Documentation/devicetree/bindings/clock/clock-bindings.txt and
  Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
- clock-names: should be "axi"
- interrupts: should contain the PRE interrupt
- fsl,iram: phandle pointing to the mmio-sram device node, that should be
  used for the PRE SRAM double buffer.

example:

pre@21c8000 {
	compatible = "fsl,imx6qp-pre";
	reg = <0x021c8000 0x1000>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clks IMX6QDL_CLK_PRE0>;
	clock-names = "axi";
	fsl,iram = <&ocram2>;
};

Freescale i.MX PRG (Prefetch Resolve Gasket)
============================================

Required properties:
- compatible: should be "fsl,imx6qp-prg"
- reg: should be register base and length as documented in the
  datasheet
- clocks : phandles to the PRG ipg and axi clock inputs, as described
  in Documentation/devicetree/bindings/clock/clock-bindings.txt and
  Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
- clock-names: should be "ipg" and "axi"
- fsl,pres: phandles to the PRE units attached to this PRG, with the fixed
  PRE as the first entry and the muxable PREs following.

example:

prg@21cc000 {
	compatible = "fsl,imx6qp-prg";
	reg = <0x021cc000 0x1000>;
	clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
		 <&clks IMX6QDL_CLK_PRG0_AXI>;
	clock-names = "ipg", "axi";
	fsl,pres = <&pre1>, <&pre2>, <&pre3>;
};

Parallel display support
========================

Required properties:
- compatible: Should be "fsl,imx-parallel-display"
Optional properties:
- interface-pix-fmt: How this display is connected to the
  display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
  and "lvds666".
- edid: verbatim EDID data block describing attached display.
- ddc: phandle describing the i2c bus handling the display data
  channel
- port@[0-1]: Port nodes with endpoint definitions as defined in
  Documentation/devicetree/bindings/media/video-interfaces.txt.
  Port 0 is the input port connected to the IPU display interface,
  port 1 is the output port connected to a panel.

example:

disp0 {
	compatible = "fsl,imx-parallel-display";
	edid = [edid-data];
	interface-pix-fmt = "rgb24";

	port@0 {
		reg = <0>;

		display_in: endpoint {
			remote-endpoint = <&ipu_di0_disp0>;
		};
	};

	port@1 {
		reg = <1>;

		display_out: endpoint {
			remote-endpoint = <&panel_in>;
		};
	};
};

panel {
	...

	port {
		panel_in: endpoint {
			remote-endpoint = <&display_out>;
		};
	};
};


code:
Device-Tree bindings for LVDS Display Bridge (ldb)

LVDS Display Bridge
===================

The LVDS Display Bridge device tree node contains up to two lvds-channel
nodes describing each of the two LVDS encoder channels of the bridge.

Required properties:
 - #address-cells : should be <1>
 - #size-cells : should be <0>
 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
                Both LDB versions are similar, but i.MX6 has an additional
                multiplexer in the front to select any of the four IPU display
                interfaces as input for each LVDS channel.
 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
         The phandle points to the iomuxc-gpr region containing the LVDS
         control register.
- clocks, clock-names : phandles to the LDB divider and selector clocks and to
                        the display interface selector clocks, as described in
                        Documentation/devicetree/bindings/clock/clock-bindings.txt
        The following clocks are expected on i.MX53:
                "di0_pll" - LDB LVDS channel 0 mux
                "di1_pll" - LDB LVDS channel 1 mux
                "di0" - LDB LVDS channel 0 gate
                "di1" - LDB LVDS channel 1 gate
                "di0_sel" - IPU1 DI0 mux
                "di1_sel" - IPU1 DI1 mux
        On i.MX6q the following additional clocks are needed:
                "di2_sel" - IPU2 DI0 mux
                "di3_sel" - IPU2 DI1 mux
        The needed clock numbers for each are documented in
        Documentation/devicetree/bindings/clock/imx5-clock.yaml, and in
        Documentation/devicetree/bindings/clock/imx6q-clock.yaml.

Optional properties:
 - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q
 - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
               not used on i.MX6q
 - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
   be configured - one input will be distributed on both outputs in dual
   channel mode

LVDS Channel
============

Each LVDS Channel has to contain either an of graph link to a panel device node
or a display-timings node that describes the video timings for the connected
LVDS display as well as the fsl,data-mapping and fsl,data-width properties.

Required properties:
 - reg : should be <0> or <1>
 - port: Input and output port nodes with endpoint definitions as defined in
   Documentation/devicetree/bindings/graph.txt.
   On i.MX5, the internal two-input-multiplexer is used. Due to hardware
   limitations, only one input port (port@[0,1]) can be used for each channel
   (lvds-channel@[0,1], respectively).
   On i.MX6, there should be four input ports (port@[0-3]) that correspond
   to the four LVDS multiplexer inputs.
   A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
   to a panel input port. Optionally, the output port can be left out if
   display-timings are used instead.

Optional properties (required if display-timings are used):
 - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
 - display-timings : A node that describes the display timings as defined in
   Documentation/devicetree/bindings/display/panel/display-timing.txt.
 - fsl,data-mapping : should be "spwg" or "jeida"
                      This describes how the color bits are laid out in the
                      serialized LVDS signal.
 - fsl,data-width : should be <18> or <24>

example:

gpr: iomuxc-gpr@53fa8000 {
	/* ... */
};

ldb: ldb@53fa8008 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx53-ldb";
	gpr = <&gpr>;
	clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
		 <&clks IMX5_CLK_LDB_DI1_SEL>,
		 <&clks IMX5_CLK_IPU_DI0_SEL>,
		 <&clks IMX5_CLK_IPU_DI1_SEL>,
		 <&clks IMX5_CLK_LDB_DI0_GATE>,
		 <&clks IMX5_CLK_LDB_DI1_GATE>;
	clock-names = "di0_pll", "di1_pll",
		      "di0_sel", "di1_sel",
		      "di0", "di1";

	/* Using an of-graph endpoint link to connect the panel */
	lvds-channel@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0>;

		port@0 {
			reg = <0>;

			lvds0_in: endpoint {
				remote-endpoint = <&ipu_di0_lvds0>;
			};
		};

		port@2 {
			reg = <2>;

			lvds0_out: endpoint {
				remote-endpoint = <&panel_in>;
			};
		};
	};

	/* Using display-timings and fsl,data-mapping/width instead */
	lvds-channel@1 {
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <1>;
		fsl,data-mapping = "spwg";
		fsl,data-width = <24>;

		display-timings {
			/* ... */
		};

		port@1 {
			reg = <1>;

			lvds1_in: endpoint {
				remote-endpoint = <&ipu_di1_lvds1>;
			};
		};
	};
};

panel: lvds-panel {
	/* ... */

	port {
		panel_in: endpoint {
			remote-endpoint = <&lvds0_out>;
		};
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 NXP
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: iMX8MQ Display Controller Subsystem (DCSS)

maintainers:
  - Laurentiu Palcu <laurentiu.palcu@nxp.com>

description:

  The DCSS (display controller sub system) is used to source up to three
  display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
  2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
  image processing capabilities are included to provide a solution capable of
  driving next generation high dynamic range displays.

properties:
  compatible:
    const: nxp,imx8mq-dcss

  reg:
    items:
      - description: DCSS base address and size, up to IRQ steer start
      - description: DCSS BLKCTL base address and size

  interrupts:
    items:
      - description: Context loader completion and error interrupt
      - description: DTG interrupt used to signal context loader trigger time
      - description: DTG interrupt for Vblank

  interrupt-names:
    items:
      - const: ctxld
      - const: ctxld_kick
      - const: vblank

  clocks:
    items:
      - description: Display APB clock for all peripheral PIO access interfaces
      - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
      - description: RTRAM clock
      - description: Pixel clock, can be driven either by HDMI phy clock or MIPI
      - description: DTRC clock, needed by video decompressor

  clock-names:
    items:
      - const: apb
      - const: axi
      - const: rtrm
      - const: pix
      - const: dtrc

  assigned-clocks:
    items:
      - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
      - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
      - description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or
                     IMX8MQ_VIDEO_PLL1_REF_SEL

  assigned-clock-parents:
    items:
      - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
      - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
      - description: Phandle and clock specifier of IMX8MQ_CLK_27M

  assigned-clock-rates:
    items:
      - description: Must be 800 MHz
      - description: Must be 400 MHz

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      A port node pointing to the input port of a HDMI/DP or MIPI display bridge.

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mq-clock.h>
    dcss: display-controller@32e00000 {
        compatible = "nxp,imx8mq-dcss";
        reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
        interrupts = <6>, <8>, <9>;
        interrupt-names = "ctxld", "ctxld_kick", "vblank";
        interrupt-parent = <&irqsteer>;
        clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
                 <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,
                 <&clk IMX8MQ_CLK_DISP_DTRC>;
        clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
        assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
                          <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
        assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
                                 <&clk IMX8MQ_CLK_27M>;
        assigned-clock-rates = <800000000>,
                               <400000000>;
        port {
            dcss_out: endpoint {
                remote-endpoint = <&hdmi_in>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/ingenic,ipu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs Image Processing Unit (IPU) devicetree bindings

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

properties:
  compatible:
    oneOf:
      - enum:
          - ingenic,jz4725b-ipu
          - ingenic,jz4760-ipu
      - items:
          - const: ingenic,jz4770-ipu
          - const: ingenic,jz4760-ipu

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: ipu

  port:
    $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
    ipu@13080000 {
      compatible = "ingenic,jz4770-ipu", "ingenic,jz4760-ipu";
      reg = <0x13080000 0x800>;

      interrupt-parent = <&intc>;
      interrupts = <29>;

      clocks = <&cgu JZ4770_CLK_IPU>;
      clock-names = "ipu";

      port {
        ipu_ep: endpoint {
          remote-endpoint = <&lcdc_ep>;
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/ingenic,lcd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs LCD controller devicetree bindings

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

properties:
  $nodename:
    pattern: "^lcd-controller@[0-9a-f]+$"

  compatible:
    enum:
      - ingenic,jz4740-lcd
      - ingenic,jz4725b-lcd
      - ingenic,jz4760-lcd
      - ingenic,jz4760b-lcd
      - ingenic,jz4770-lcd
      - ingenic,jz4780-lcd

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Pixel clock
      - description: Module clock
    minItems: 1

  clock-names:
    items:
      - const: lcd_pclk
      - const: lcd
    minItems: 1

  port:
    $ref: /schemas/graph.yaml#/properties/port

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: DPI output, to interface with TFT panels.

      port@8:
        $ref: /schemas/graph.yaml#/properties/port
        description: Link to the Image Processing Unit (IPU).
          (See ingenic,ipu.yaml).

    required:
      - port@0

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

if:
  properties:
    compatible:
      contains:
        enum:
          - ingenic,jz4740-lcd
          - ingenic,jz4780-lcd
then:
  properties:
    clocks:
      minItems: 2
    clock-names:
      minItems: 2
else:
  properties:
    clocks:
      maxItems: 1
    clock-names:
      maxItems: 1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
    lcd-controller@13050000 {
      compatible = "ingenic,jz4740-lcd";
      reg = <0x13050000 0x1000>;

      interrupt-parent = <&intc>;
      interrupts = <30>;

      clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
      clock-names = "lcd_pclk", "lcd";

      port {
        endpoint {
          remote-endpoint = <&panel_input>;
        };
      };
    };

  - |
    #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
    lcd-controller@13050000 {
      compatible = "ingenic,jz4725b-lcd";
      reg = <0x13050000 0x1000>;

      interrupt-parent = <&intc>;
      interrupts = <31>;

      clocks = <&cgu JZ4725B_CLK_LCD>;
      clock-names = "lcd_pclk";

      port {
        endpoint {
          remote-endpoint = <&panel_input>;
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/intel,keembay-display.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Devicetree bindings for Intel Keem Bay display controller

maintainers:
  - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
  - Edmond J Dea <edmund.j.dea@intel.com>

properties:
  compatible:
    const: intel,keembay-display

  reg:
    items:
      - description: LCD registers range

  reg-names:
    items:
      - const: lcd

  clocks:
    items:
      - description: LCD controller clock
      - description: pll0 clock

  clock-names:
    items:
      - const: clk_lcd
      - const: clk_pll0

  interrupts:
    maxItems: 1

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description: Display output node to DSI.

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - interrupts
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    display@20930000 {
        compatible = "intel,keembay-display";
        reg = <0x20930000 0x3000>;
        reg-names = "lcd";
        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&scmi_clk 0x83>,
                 <&scmi_clk 0x0>;
        clock-names = "clk_lcd", "clk_pll0";

        port {
            disp_out: endpoint {
                remote-endpoint = <&dsi_in>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/intel,keembay-msscam.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Devicetree bindings for Intel Keem Bay MSSCAM

maintainers:
  - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
  - Edmond J Dea <edmund.j.dea@intel.com>

description: |
   MSSCAM controls local clocks in the display subsystem namely LCD clocks and
   MIPI DSI clocks. It also configures the interconnect between LCD and
   MIPI DSI.

properties:
  compatible:
    items:
      - const: intel,keembay-msscam
      - const: syscon

  reg:
    maxItems: 1

  reg-io-width:
    const: 4

required:
  - compatible
  - reg
  - reg-io-width

additionalProperties: false

examples:
  - |
    msscam:msscam@20910000 {
        compatible = "intel,keembay-msscam", "syscon";
        reg = <0x20910000 0x30>;
        reg-io-width = <4>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/lvds.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LVDS Display Common Properties

maintainers:
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |+
  LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
  incompatible data link layers have been used over time to transmit image data
  to LVDS devices. This bindings supports devices compatible with the following
  specifications.

  [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
  1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
  [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
  Semiconductor
  [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
  Electronics Standards Association (VESA)

  Device compatible with those specifications have been marketed under the
  FPD-Link and FlatLink brands.

properties:
  data-mapping:
    enum:
      - jeida-18
      - jeida-24
      - vesa-24
    description: |
      The color signals mapping order.

      LVDS data mappings are defined as follows.

      - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
        [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><

      - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
        specifications. Data are transferred as follows on 4 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
      DATA1     ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
      DATA3     ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><

      - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
        Data are transferred as follows on 4 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
      DATA3     ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><

      Control signals are mapped as follows.

      CTL0: HSync
      CTL1: VSync
      CTL2: Data Enable
      CTL3: 0

  data-mirror:
    type: boolean
    description:
      If set, reverse the bit order described in the data mappings below on all
      data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.

additionalProperties: true

...


code:
PXA LCD Controller
------------------

Required properties:
 - compatible : one of these
	"marvell,pxa2xx-lcdc",
	"marvell,pxa270-lcdc",
	"marvell,pxa300-lcdc"
 - reg : should contain 1 register range (address and length).
 - interrupts : framebuffer controller interrupt.
 - clocks: phandle to input clocks

Optional properties:
 - lcd-supply: A phandle to a power regulator that controls the LCD voltage.

Required nodes:
 - port: connection to the LCD panel (see video-interfaces.txt)
	 This node must have its properties bus-width and remote-endpoint set.
	 If the panel is not a TFT color panel, then a "lcd-type" property in
	 the panel should specify the panel type.
	 This panel node should be in the board dts.

Example:
	lcd-controller@40500000 {
		compatible = "marvell,pxa2xx-lcdc";
		reg = <0x44000000 0x10000>;
		interrupts = <17>;
		clocks = <&clks CLK_LCD>;

		port {
			lcdc_out: endpoint {
				remote-endpoint = <&panel_in>;
				bus-width = <16>;
			};
		};
	};


code:
PXA3xx GCU Controller
---------------------

Required properties:
 - compatible : "marvell,pxa300-gcu"
 - reg : should contain the register range (address and length).
 - interrupts : Controller interrupt.
 - clocks: phandle to the PXA specific input clock.

Example for PXA300:

	display-controller@54000000 {
		compatible = "marvell,pxa300-gcu";
		reg = <0x54000000 0x1000>;
		interrupts = <39>;
		clocks = <&clks CLK_PXA300_GCU>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display adaptive ambient light processor

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display adaptive ambient light processor, namely AAL,
  is responsible for backlight power saving and sunlight visibility improving.
  AAL device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt8173-disp-aal
          - mediatek,mt8183-disp-aal
      - items:
          - enum:
              - mediatek,mt2712-disp-aal
          - const: mediatek,mt8173-disp-aal
      - items:
          - enum:
              - mediatek,mt8186-disp-aal
              - mediatek,mt8192-disp-aal
              - mediatek,mt8195-disp-aal
          - const: mediatek,mt8183-disp-aal

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: AAL Clock

  mediatek,gce-client-reg:
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property, such as phandle of gce, subsys id,
      register offset and size. Each GCE subsys id is mapping to a client
      defined in the header include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>
    #include <dt-bindings/gce/mt8173-gce.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        aal@14015000 {
           compatible = "mediatek,mt8173-disp-aal";
           reg = <0 0x14015000 0 0x1000>;
           interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
           power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
           clocks = <&mmsys CLK_MM_DISP_AAL>;
           mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
       };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display color correction

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display color correction, namely CCORR, reproduces correct color
  on panels with different color gamut.
  CCORR device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt8183-disp-ccorr
      - items:
          - const: mediatek,mt8192-disp-ccorr
      - items:
          - enum:
              - mediatek,mt8195-disp-ccorr
          - const: mediatek,mt8192-disp-ccorr
      - items:
          - enum:
              - mediatek,mt8186-disp-ccorr
          - const: mediatek,mt8183-disp-ccorr

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: CCORR Clock

  mediatek,gce-client-reg:
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property, such as phandle of gce, subsys id,
      register offset and size. Each GCE subsys id is mapping to a client
      defined in the header include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/power/mt8183-power.h>
    #include <dt-bindings/gce/mt8183-gce.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        ccorr0: ccorr@1400f000 {
            compatible = "mediatek,mt8183-disp-ccorr";
            reg = <0 0x1400f000 0 0x1000>;
            interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
            clocks = <&mmsys CLK_MM_DISP_CCORR0>;
            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek HDMI CEC Controller Device Tree Bindings

maintainers:
  - CK Hu <ck.hu@mediatek.com>
  - Jitao shi <jitao.shi@mediatek.com>

description: |
  The HDMI CEC controller handles hotplug detection and CEC communication.

properties:
  compatible:
    enum:
      - mediatek,mt7623-cec
      - mediatek,mt8167-cec
      - mediatek,mt8173-cec

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    cec: cec@10013000 {
        compatible = "mediatek,mt8173-cec";
        reg = <0x10013000 0xbc>;
        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
        clocks = <&infracfg CLK_INFRA_CEC>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display color processor

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display color processor, namely COLOR, provides hue, luma and
  saturation adjustments to get better picture quality and to have one panel
  resemble the other in their output characteristics.
  COLOR device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt2701-disp-color
      - items:
          - const: mediatek,mt8167-disp-color
      - items:
          - const: mediatek,mt8173-disp-color
      - items:
          - enum:
              - mediatek,mt7623-disp-color
              - mediatek,mt2712-disp-color
          - const: mediatek,mt2701-disp-color
      - items:
          - enum:
              - mediatek,mt8183-disp-color
              - mediatek,mt8186-disp-color
              - mediatek,mt8192-disp-color
              - mediatek,mt8195-disp-color
          - const: mediatek,mt8173-disp-color
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: COLOR Clock

  mediatek,gce-client-reg:
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property, such as phandle of gce, subsys id,
      register offset and size. Each GCE subsys id is mapping to a client
      defined in the header include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>
    #include <dt-bindings/gce/mt8173-gce.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        color0: color@14013000 {
            compatible = "mediatek,mt8173-disp-color";
            reg = <0 0x14013000 0 0x1000>;
            interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
            clocks = <&mmsys CLK_MM_DISP_COLOR0>;
            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek display dither processor

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>

description: |
  Mediatek display dither processor, namely DITHER, works by approximating
  unavailable colors with available colors and by mixing and matching available
  colors to mimic unavailable ones.
  DITHER device node must be siblings to the central MMSYS_CONFIG node.
  For a description of the MMSYS_CONFIG binding, see
  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  for details.

properties:
  compatible:
    oneOf:
      - items:
          - const: mediatek,mt8183-disp-dither
      - items:
          - enum:
              - mediatek,mt8186-disp-dither
              - mediatek,mt8192-disp-dither
              - mediatek,mt8195-disp-dither
          - const: mediatek,mt8183-disp-dither

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    description: A phandle and PM domain specifier as defined by bindings of
      the power controller specified by phandle. See
      Documentation/devicetree/bindings/power/power-domain.yaml for details.

  clocks:
    items:
      - description: DITHER Clock

  mediatek,gce-client-reg:
    description: The register of client driver can be configured by gce with
      4 arguments defined in this property, such as phandle of gce, subsys id,
      register offset and size. Each GCE subsys id is mapping to a client
      defined in the header include/dt-bindings/gce/<chip>-gce.h.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/power/mt8183-power.h>
    #include <dt-bindings/gce/mt8183-gce.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        dither0: dither@14012000 {
            compatible = "mediatek,mt8183-disp-dither";
            reg = <0 0x14012000 0 0x1000>;
            interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
            clocks = <&mmsys CLK_MM_DISP_DITHER0>;
            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
        };
    };