code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LPDDR channel with chip/rank topology description

description:
  An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
  CK, etc.) that connect one or more LPDDR chips to a host system. The main
  purpose of this node is to overall LPDDR topology of the system, including the
  amount of individual LPDDR chips and the ranks per chip.

maintainers:
  - Julius Werner <jwerner@chromium.org>

properties:
  compatible:
    enum:
      - jedec,lpddr2-channel
      - jedec,lpddr3-channel
      - jedec,lpddr4-channel
      - jedec,lpddr5-channel

  io-width:
    description:
      The number of DQ pins in the channel. If this number is different
      from (a multiple of) the io-width of the LPDDR chip, that means that
      multiple instances of that type of chip are wired in parallel on this
      channel (with the channel's DQ pins split up between the different
      chips, and the CA, CS, etc. pins of the different chips all shorted
      together).  This means that the total physical memory controlled by a
      channel is equal to the sum of the densities of each rank on the
      connected LPDDR chip, times the io-width of the channel divided by
      the io-width of the LPDDR chip.
    enum:
      - 8
      - 16
      - 32
      - 64
      - 128

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

patternProperties:
  "^rank@[0-9]+$":
    type: object
    description:
      Each physical LPDDR chip may have one or more ranks. Ranks are
      internal but fully independent sub-units of the chip. Each LPDDR bus
      transaction on the channel targets exactly one rank, based on the
      state of the CS pins. Different ranks may have different densities and
      timing requirements.
    required:
      - reg

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: jedec,lpddr2-channel
    then:
      patternProperties:
        "^rank@[0-9]+$":
          $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: jedec,lpddr3-channel
    then:
      patternProperties:
        "^rank@[0-9]+$":
          $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: jedec,lpddr4-channel
    then:
      patternProperties:
        "^rank@[0-9]+$":
          $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: jedec,lpddr5-channel
    then:
      patternProperties:
        "^rank@[0-9]+$":
          $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml#

required:
  - compatible
  - io-width
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:
  - |
    lpddr-channel0 {
      #address-cells = <1>;
      #size-cells = <0>;
      compatible = "jedec,lpddr3-channel";
      io-width = <32>;

      rank@0 {
        compatible = "lpddr3-ff,0100", "jedec,lpddr3";
        reg = <0>;
        density = <8192>;
        io-width = <16>;
        revision-id = <1 0>;
      };
    };

    lpddr-channel1 {
      #address-cells = <1>;
      #size-cells = <0>;
      compatible = "jedec,lpddr4-channel";
      io-width = <32>;

      rank@0 {
        compatible = "lpddr4-05,0301", "jedec,lpddr4";
        reg = <0>;
        density = <4096>;
        io-width = <32>;
        revision-id = <3 1>;
      };

      rank@1 {
        compatible = "lpddr4-05,0301", "jedec,lpddr4";
        reg = <1>;
        density = <2048>;
        io-width = <32>;
        revision-id = <3 1>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common properties for LPDDR types

description:
  Different LPDDR types generally use the same properties and only differ in the
  range of legal values for each. This file defines the common parts that can be
  reused for each type. Nodes using this schema should generally be nested under
  an LPDDR channel node.

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    description:
      Compatible strings can be either explicit vendor names and part numbers
      (e.g. elpida,ECB240ABACN), or generated strings of the form
      lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID
      (from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are
      formatted in lower case hexadecimal representation with leading zeroes.
      The latter form can be useful when LPDDR nodes are created at runtime by
      boot firmware that doesn't have access to static part number information.

  reg:
    description:
      The rank number of this LPDDR rank when used as a subnode to an LPDDR
      channel.
    minimum: 0
    maximum: 3

  revision-id:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description:
      Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
    maxItems: 2
    items:
      minimum: 0
      maximum: 255

  density:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Density in megabits of SDRAM chip. Decoded from Mode Register 8.
    enum:
      - 64
      - 128
      - 256
      - 512
      - 1024
      - 2048
      - 3072
      - 4096
      - 6144
      - 8192
      - 12288
      - 16384
      - 24576
      - 32768

  io-width:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      IO bus width in bits of SDRAM chip. Decoded from Mode Register 8.
    enum:
      - 8
      - 16
      - 32

additionalProperties: true

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LPDDR2 SDRAM AC timing parameters for a given speed-bin

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    const: jedec,lpddr2-timings

  max-freq:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Maximum DDR clock frequency for the speed-bin, in Hz.

  min-freq:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Minimum DDR clock frequency for the speed-bin, in Hz.

  tCKESR:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      CKE minimum pulse width during SELF REFRESH (low pulse width during
      SELF REFRESH) in pico seconds.

  tDQSCK-max:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      DQS output data access time from CK_t/CK_c in pico seconds.

  tDQSCK-max-derated:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
      seconds.

  tFAW:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Four-bank activate window in pico seconds.

  tRAS-max-ns:
    description: |
      Row active time in nano seconds.

  tRAS-min:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Row active time in pico seconds.

  tRCD:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      RAS-to-CAS delay in pico seconds.

  tRPab:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Row precharge time (all banks) in pico seconds.

  tRRD:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Active bank A to active bank B in pico seconds.

  tRTP:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Internal READ to PRECHARGE command delay in pico seconds.

  tWR:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      WRITE recovery time in pico seconds.

  tWTR:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Internal WRITE-to-READ command delay in pico seconds.

  tXP:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Exit power-down to next valid command delay in pico seconds.

  tZQCL:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Long calibration time in pico seconds.

  tZQCS:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Short calibration time in pico seconds.

  tZQinit:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Initialization calibration time in pico seconds.

required:
  - compatible
  - min-freq
  - max-freq

additionalProperties: false

examples:
  - |
    timings {
        compatible = "jedec,lpddr2-timings";
        min-freq = <10000000>;
        max-freq = <400000000>;
        tCKESR = <15000>;
        tDQSCK-max = <5500>;
        tFAW = <50000>;
        tRAS-max-ns = <70000>;
        tRAS-min = <42000>;
        tRPab = <21000>;
        tRCD = <18000>;
        tRRD = <10000>;
        tRTP = <7500>;
        tWR = <15000>;
        tWTR = <7500>;
        tXP = <7500>;
        tZQCL = <360000>;
        tZQCS = <90000>;
        tZQinit = <1000000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LPDDR2 SDRAM compliant to JEDEC JESD209-2

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

allOf:
  - $ref: jedec,lpddr-props.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - elpida,ECB240ABACN
              - elpida,B8132B2PB-6D-F
          - enum:
              - jedec,lpddr2-nvm
              - jedec,lpddr2-s2
              - jedec,lpddr2-s4
      - items:
          - pattern: "^lpddr2-[0-9a-f]{2},[0-9a-f]{4}$"
          - enum:
              - jedec,lpddr2-nvm
              - jedec,lpddr2-s2
              - jedec,lpddr2-s4

  revision-id1:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 255
    description: |
      Revision 1 value of SDRAM chip. Obtained from device datasheet.
      Property is deprecated, use revision-id instead.
    deprecated: true

  revision-id2:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 255
    description: |
      Revision 2 value of SDRAM chip. Obtained from device datasheet.
      Property is deprecated, use revision-id instead.
    deprecated: true

  tRRD-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 16
    description: |
      Active bank a to active bank b in terms of number of clock cycles.
      Obtained from device datasheet.

  tWTR-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 16
    description: |
      Internal WRITE-to-READ command delay in terms of number of clock cycles.
      Obtained from device datasheet.

  tXP-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 16
    description: |
      Exit power-down to next valid command delay in terms of number of clock
      cycles. Obtained from device datasheet.

  tRTP-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 16
    description: |
      Internal READ to PRECHARGE command delay in terms of number of clock
      cycles. Obtained from device datasheet.

  tCKE-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 16
    description: |
      CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
      of clock cycles. Obtained from device datasheet.

  tRPab-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 16
    description: |
      Row precharge time (all banks) in terms of number of clock cycles.
      Obtained from device datasheet.

  tRCD-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 16
    description: |
      RAS-to-CAS delay in terms of number of clock cycles. Obtained from
      device datasheet.

  tWR-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 16
    description: |
      WRITE recovery time in terms of number of clock cycles. Obtained from
      device datasheet.

  tRASmin-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 16
    description: |
      Row active time in terms of number of clock cycles. Obtained from device
      datasheet.

  tCKESR-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 16
    description: |
      CKE minimum pulse width during SELF REFRESH (low pulse width during
      SELF REFRESH) in terms of number of clock cycles. Obtained from device
      datasheet.

  tFAW-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 16
    description: |
      Four-bank activate window in terms of number of clock cycles. Obtained
      from device datasheet.

patternProperties:
  "^lpddr2-timings":
    $ref: jedec,lpddr2-timings.yaml
    description: |
      The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
      "lpddr2-timings" provides AC timing parameters of the device for
      a given speed-bin. The user may provide the timings for as many
      speed-bins as is required.

required:
  - compatible
  - density
  - io-width

unevaluatedProperties: false

examples:
  - |
    elpida_ECB240ABACN: lpddr2 {
        compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
        density = <2048>;
        io-width = <32>;
        revision-id = <1 0>;

        tRPab-min-tck = <3>;
        tRCD-min-tck = <3>;
        tWR-min-tck = <3>;
        tRASmin-min-tck = <3>;
        tRRD-min-tck = <2>;
        tWTR-min-tck = <2>;
        tXP-min-tck = <2>;
        tRTP-min-tck = <2>;
        tCKE-min-tck = <3>;
        tCKESR-min-tck = <3>;
        tFAW-min-tck = <8>;

        timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 {
            compatible = "jedec,lpddr2-timings";
            min-freq = <10000000>;
            max-freq = <400000000>;
            tRPab = <21000>;
            tRCD = <18000>;
            tWR = <15000>;
            tRAS-min = <42000>;
            tRRD = <10000>;
            tWTR = <7500>;
            tXP = <7500>;
            tRTP = <7500>;
            tCKESR = <15000>;
            tDQSCK-max = <5500>;
            tFAW = <50000>;
            tZQCS = <90000>;
            tZQCL = <360000>;
            tZQinit = <1000000>;
            tRAS-max-ns = <70000>;
        };

        timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 {
            compatible = "jedec,lpddr2-timings";
            min-freq = <10000000>;
            max-freq = <200000000>;
            tRPab = <21000>;
            tRCD = <18000>;
            tWR = <15000>;
            tRAS-min = <42000>;
            tRRD = <10000>;
            tWTR = <10000>;
            tXP = <7500>;
            tRTP = <7500>;
            tCKESR = <15000>;
            tDQSCK-max = <5500>;
            tFAW = <50000>;
            tZQCS = <90000>;
            tZQCL = <360000>;
            tZQinit = <1000000>;
            tRAS-max-ns = <70000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LPDDR3 SDRAM AC timing parameters for a given speed-bin

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    const: jedec,lpddr3-timings

  reg:
    maxItems: 1
    description: |
      Maximum DDR clock frequency for the speed-bin, in Hz.
      Property is deprecated, use max-freq.
    deprecated: true

  max-freq:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Maximum DDR clock frequency for the speed-bin, in Hz.

  min-freq:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Minimum DDR clock frequency for the speed-bin, in Hz.

  tCKE:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.

  tCKESR:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      CKE minimum pulse width during SELF REFRESH (low pulse width during
      SELF REFRESH) in pico seconds.

  tFAW:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Four-bank activate window in pico seconds.

  tMRD:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Mode register set command delay in pico seconds.

  tR2R-C2C:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Additional READ-to-READ delay in chip-to-chip cases in pico seconds.

  tRAS:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Row active time in pico seconds.

  tRC:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      ACTIVATE-to-ACTIVATE command period in pico seconds.

  tRCD:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      RAS-to-CAS delay in pico seconds.

  tRFC:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Refresh Cycle time in pico seconds.

  tRPab:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Row precharge time (all banks) in pico seconds.

  tRPpb:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Row precharge time (single banks) in pico seconds.

  tRRD:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Active bank A to active bank B in pico seconds.

  tRTP:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Internal READ to PRECHARGE command delay in pico seconds.

  tW2W-C2C:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.

  tWR:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      WRITE recovery time in pico seconds.

  tWTR:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Internal WRITE-to-READ command delay in pico seconds.

  tXP:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Exit power-down to next valid command delay in pico seconds.

  tXSR:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      SELF REFRESH exit to next valid command delay in pico seconds.

required:
  - compatible
  - min-freq
  - max-freq

additionalProperties: false

examples:
  - |
    lpddr3 {
        timings {
            compatible = "jedec,lpddr3-timings";
            max-freq = <800000000>;
            min-freq = <100000000>;
            tCKE = <3750>;
            tCKESR = <3750>;
            tFAW = <25000>;
            tMRD = <7000>;
            tR2R-C2C = <0>;
            tRAS = <23000>;
            tRC = <33750>;
            tRCD = <10000>;
            tRFC = <65000>;
            tRPab = <12000>;
            tRPpb = <12000>;
            tRRD = <6000>;
            tRTP = <3750>;
            tW2W-C2C = <0>;
            tWR = <7500>;
            tWTR = <3750>;
            tXP = <3750>;
            tXSR = <70000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LPDDR3 SDRAM compliant to JEDEC JESD209-3

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

allOf:
  - $ref: jedec,lpddr-props.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - samsung,K3QF2F20DB
          - const: jedec,lpddr3
      - items:
          - pattern: "^lpddr3-[0-9a-f]{2},[0-9a-f]{4}$"
          - const: jedec,lpddr3

  '#address-cells':
    const: 1
    deprecated: true

  manufacturer-id:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Manufacturer ID value read from Mode Register 5.  The property is
      deprecated, manufacturer should be derived from the compatible.
    deprecated: true

  '#size-cells':
    const: 0
    deprecated: true

  tCKE-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
      of clock cycles.

  tCKESR-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      CKE minimum pulse width during SELF REFRESH (low pulse width during
      SELF REFRESH) in terms of number of clock cycles.

  tDQSCK-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      DQS output data access time from CK_t/CK_c in terms of number of clock
      cycles.

  tFAW-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 63
    description: |
      Four-bank activate window in terms of number of clock cycles.

  tMRD-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      Mode register set command delay in terms of number of clock cycles.

  tR2R-C2C-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]
    description: |
      Additional READ-to-READ delay in chip-to-chip cases in terms of number
      of clock cycles.

  tRAS-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 63
    description: |
      Row active time in terms of number of clock cycles.

  tRC-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 63
    description: |
      ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.

  tRCD-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      RAS-to-CAS delay in terms of number of clock cycles.

  tRFC-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 255
    description: |
      Refresh Cycle time in terms of number of clock cycles.

  tRL-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
     READ data latency in terms of number of clock cycles.

  tRPab-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      Row precharge time (all banks) in terms of number of clock cycles.

  tRPpb-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      Row precharge time (single banks) in terms of number of clock cycles.

  tRRD-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      Active bank A to active bank B in terms of number of clock cycles.

  tRTP-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      Internal READ to PRECHARGE command delay in terms of number of clock
      cycles.

  tW2W-C2C-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]
    description: |
      Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
      of clock cycles.

  tWL-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      WRITE data latency in terms of number of clock cycles.

  tWR-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      WRITE recovery time in terms of number of clock cycles.

  tWTR-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 15
    description: |
      Internal WRITE-to-READ command delay in terms of number of clock cycles.

  tXP-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 255
    description: |
      Exit power-down to next valid command delay in terms of number of clock
      cycles.

  tXSR-min-tck:
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 1023
    description: |
      SELF REFRESH exit to next valid command delay in terms of number of clock
      cycles.

patternProperties:
  "^timings((-[0-9])+|(@[0-9a-f]+))?$":
    $ref: jedec,lpddr3-timings.yaml
    description: |
      The lpddr3 node may have one or more child nodes with timings.
      Each timing node provides AC timing parameters of the device for a given
      speed-bin. The user may provide the timings for as many speed-bins as is
      required.

required:
  - compatible
  - density
  - io-width

unevaluatedProperties: false

examples:
  - |
    lpddr3 {
        compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
        density = <16384>;
        io-width = <32>;

        tCKE-min-tck = <2>;
        tCKESR-min-tck = <2>;
        tDQSCK-min-tck = <5>;
        tFAW-min-tck = <5>;
        tMRD-min-tck = <5>;
        tR2R-C2C-min-tck = <0>;
        tRAS-min-tck = <5>;
        tRC-min-tck = <6>;
        tRCD-min-tck = <3>;
        tRFC-min-tck = <17>;
        tRL-min-tck = <14>;
        tRPab-min-tck = <2>;
        tRPpb-min-tck = <2>;
        tRRD-min-tck = <2>;
        tRTP-min-tck = <2>;
        tW2W-C2C-min-tck = <0>;
        tWL-min-tck = <8>;
        tWR-min-tck = <7>;
        tWTR-min-tck = <2>;
        tXP-min-tck = <2>;
        tXSR-min-tck = <12>;

        timings {
            compatible = "jedec,lpddr3-timings";
            max-freq = <800000000>;
            min-freq = <100000000>;
            tCKE = <3750>;
            tCKESR = <3750>;
            tFAW = <25000>;
            tMRD = <7000>;
            tR2R-C2C = <0>;
            tRAS = <23000>;
            tRC = <33750>;
            tRCD = <10000>;
            tRFC = <65000>;
            tRPab = <12000>;
            tRPpb = <12000>;
            tRRD = <6000>;
            tRTP = <3750>;
            tW2W-C2C = <0>;
            tWR = <7500>;
            tWTR = <3750>;
            tXP = <3750>;
            tXSR = <70000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LPDDR4 SDRAM compliant to JEDEC JESD209-4

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

allOf:
  - $ref: jedec,lpddr-props.yaml#

properties:
  compatible:
    items:
      - pattern: "^lpddr4-[0-9a-f]{2},[0-9a-f]{4}$"
      - const: jedec,lpddr4

required:
  - compatible
  - density
  - io-width

unevaluatedProperties: false

examples:
  - |
    lpddr {
        compatible = "lpddr4-ff,0100", "jedec,lpddr4";
        density = <8192>;
        io-width = <16>;
        revision-id = <1 0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LPDDR5 SDRAM compliant to JEDEC JESD209-5

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

allOf:
  - $ref: jedec,lpddr-props.yaml#

properties:
  compatible:
    items:
      - pattern: "^lpddr5-[0-9a-f]{2},[0-9a-f]{4}$"
      - const: jedec,lpddr5

  serial-id:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description:
      Serial IDs read from Mode Registers 47 through 54. One byte per uint32
      cell (i.e. <MR47 MR48 MR49 MR50 MR51 MR52 MR53 MR54>).
    maxItems: 8
    items:
      minimum: 0
      maximum: 255

required:
  - compatible
  - density
  - io-width

unevaluatedProperties: false

examples:
  - |
    lpddr {
        compatible = "lpddr5-01,0200", "jedec,lpddr5";
        density = <8192>;
        io-width = <8>;
        revision-id = <2 0>;
        serial-id = <3 1 0 0 0 0 0 0>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC SROM Controller driver

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |+
  The SROM controller can be used to attach external peripherals. In this case
  extra properties, describing the bus behind it, should be specified.

properties:
  compatible:
    items:
      - const: samsung,exynos4210-srom

  reg:
    maxItems: 1

  "#address-cells":
    const: 2

  "#size-cells":
    const: 1

  ranges:
    minItems: 1
    maxItems: 4
    description: |
      Reflects the memory layout with four integer values per bank. Format:
      <bank-number> 0 <parent address of bank> <size>
      Up to four banks are supported.

patternProperties:
  "^.*@[0-3],[a-f0-9]+$":
    type: object
    description:
      The actual device nodes should be added as subnodes to the SROMc node.
      These subnodes, in addition to regular device specification, should
      contain the following properties, describing configuration
      of the relevant SROM bank.

    properties:
      reg:
        description:
          Bank number, base address (relative to start of the bank) and size
          of the memory mapped for the device. Note that base address will be
          typically 0 as this is the start of the bank.
        maxItems: 1

      reg-io-width:
        enum: [1, 2]
        description:
          Data width in bytes (1 or 2). If omitted, default of 1 is used.

      samsung,srom-page-mode:
        description:
          If page mode is set, 4 data page mode will be configured,
          else normal (1 data) page mode will be set.
        type: boolean

      samsung,srom-timing:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          minItems: 6
          maxItems: 6
        description: |
          Array of 6 integers, specifying bank timings in the following order:
          Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
          Each value is specified in cycles and has the following meaning
          and valid range:
          Tacp: Page mode access cycle at Page mode (0 - 15)
          Tcah: Address holding time after CSn (0 - 15)
          Tcoh: Chip selection hold on OEn (0 - 15)
          Tacc: Access cycle (0 - 31, the actual time is N + 1)
          Tcos: Chip selection set-up before OEn (0 - 15)
          Tacs: Address set-up before CSn (0 - 15)

    required:
      - reg
      - samsung,srom-timing

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    // Example: basic definition, no banks are configured
    memory-controller@12560000 {
        compatible = "samsung,exynos4210-srom";
        reg = <0x12560000 0x14>;
    };

  - |
    // Example: SROMc with SMSC911x ethernet chip on bank 3
    memory-controller@12570000 {
        #address-cells = <2>;
        #size-cells = <1>;
        ranges = <0 0 0x04000000 0x20000   // Bank0
                  1 0 0x05000000 0x20000   // Bank1
                  2 0 0x06000000 0x20000   // Bank2
                  3 0 0x07000000 0x20000>; // Bank3

        compatible = "samsung,exynos4210-srom";
        reg = <0x12570000 0x14>;

        ethernet@3,0 {
            compatible = "smsc,lan9115";
            reg = <3 0 0x10000>;     // Bank 3, offset = 0
            phy-mode = "mii";
            interrupt-parent = <&gpx0>;
            interrupts = <5 8>;
            reg-io-width = <2>;
            smsc,irq-push-pull;
            smsc,force-internal-phy;

            samsung,srom-page-mode;
            samsung,srom-timing = <9 12 1 9 1 1>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale DDR memory controller

maintainers:
  - Borislav Petkov <bp@alien8.de>
  - York Sun <york.sun@nxp.com>

properties:
  $nodename:
    pattern: "^memory-controller@[0-9a-f]+$"

  compatible:
    oneOf:
      - items:
          - enum:
              - fsl,qoriq-memory-controller-v4.4
              - fsl,qoriq-memory-controller-v4.5
              - fsl,qoriq-memory-controller-v4.7
              - fsl,qoriq-memory-controller-v5.0
          - const: fsl,qoriq-memory-controller
      - enum:
          - fsl,bsc9132-memory-controller
          - fsl,mpc8536-memory-controller
          - fsl,mpc8540-memory-controller
          - fsl,mpc8541-memory-controller
          - fsl,mpc8544-memory-controller
          - fsl,mpc8548-memory-controller
          - fsl,mpc8555-memory-controller
          - fsl,mpc8560-memory-controller
          - fsl,mpc8568-memory-controller
          - fsl,mpc8569-memory-controller
          - fsl,mpc8572-memory-controller
          - fsl,mpc8349-memory-controller
          - fsl,p1020-memory-controller
          - fsl,p1021-memory-controller
          - fsl,p2020-memory-controller
          - fsl,qoriq-memory-controller

  interrupts:
    maxItems: 1

  little-endian:
    description:
      Specifies little-endian access to registers. If omitted, big-endian will
      be used.
    type: boolean

  reg:
    maxItems: 1

required:
  - compatible
  - interrupts
  - reg

additionalProperties: false

examples:
  - |
    memory-controller@2000 {
        compatible = "fsl,bsc9132-memory-controller";
        reg = <0x2000 0x1000>;
        interrupts = <16 2 1 8>;
    };

  - |
    memory-controller@8000 {
        compatible = "fsl,qoriq-memory-controller-v4.7",
                     "fsl,qoriq-memory-controller";
        reg = <0x8000 0x1000>;
        interrupts = <16 2 1 23>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: FSL/NXP Integrated Flash Controller

maintainers:
  - Li Yang <leoyang.li@nxp.com>

description: |
  NXP's integrated flash controller (IFC) is an advanced version of the
  enhanced local bus controller which includes similar programming and signal
  interfaces with an extended feature set. The IFC provides access to multiple
  external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
  SRAM and other memories where address and data are shared on a bus.

properties:
  $nodename:
    pattern: "^memory-controller@[0-9a-f]+$"

  compatible:
    const: fsl,ifc

  "#address-cells":
    enum: [2, 3]
    description: |
      Should be either two or three.  The first cell is the chipselect
      number, and the remaining cells are the offset into the chipselect.

  "#size-cells":
    enum: [1, 2]
    description: |
      Either one or two, depending on how large each chipselect can be.

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 2
    description: |
      IFC may have one or two interrupts.  If two interrupt specifiers are
      present, the first is the "common" interrupt (CM_EVTER_STAT), and the
      second is the NAND interrupt (NAND_EVTER_STAT).  If there is only one,
      that interrupt reports both types of event.

  little-endian:
    type: boolean
    description: |
      If this property is absent, the big-endian mode will be in use as default
      for registers.

  ranges:
    description: |
      Each range corresponds to a single chipselect, and covers the entire
      access window as configured.

patternProperties:
  "^.*@[a-f0-9]+(,[a-f0-9]+)+$":
    type: object
    description: |
      Child device nodes describe the devices connected to IFC such as NOR (e.g.
      cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
      like FPGAs, CPLDs, etc.

    required:
      - compatible
      - reg

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        memory-controller@ffe1e000 {
            compatible = "fsl,ifc";
            #address-cells = <2>;
            #size-cells = <1>;
            reg = <0x0 0xffe1e000 0 0x2000>;
            interrupts = <16 2 19 2>;
            little-endian;

            /* NOR, NAND Flashes and CPLD on board */
            ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,
                     <0x1 0x0 0x0 0xffa00000 0x00010000>,
                     <0x3 0x0 0x0 0xffb00000 0x00020000>;

            flash@0,0 {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "cfi-flash";
                reg = <0x0 0x0 0x2000000>;
                bank-width = <2>;
                device-width = <1>;

                partition@0 {
                    /* 32MB for user data */
                    reg = <0x0 0x02000000>;
                    label = "NOR Data";
                };
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX8M DDR Controller

maintainers:
  - Peng Fan <peng.fan@nxp.com>

description:
  The DDRC block is integrated in i.MX8M for interfacing with DDR based
  memories.

  It supports switching between different frequencies at runtime but during
  this process RAM itself becomes briefly inaccessible so actual frequency
  switching is implemented by TF-A code which runs from a SRAM area.

  The Linux driver for the DDRC doesn't even map registers (they're included
  for the sake of "describing hardware"), it mostly just exposes firmware
  capabilities through standard Linux mechanism like devfreq and OPP tables.

properties:
  compatible:
    items:
      - enum:
          - fsl,imx8mn-ddrc
          - fsl,imx8mm-ddrc
          - fsl,imx8mq-ddrc
      - const: fsl,imx8m-ddrc

  reg:
    maxItems: 1
    description:
      Base address and size of DDRC CTL area.
      This is not currently mapped by the imx8m-ddrc driver.

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: core
      - const: pll
      - const: alt
      - const: apb

  operating-points-v2: true
  opp-table:
    type: object

required:
  - reg
  - compatible
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mm-clock.h>
    ddrc: memory-controller@3d400000 {
        compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
        reg = <0x3d400000 0x400000>;
        clock-names = "core", "pll", "alt", "apb";
        clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
                 <&clk IMX8MM_DRAM_PLL>,
                 <&clk IMX8MM_CLK_DRAM_ALT>,
                 <&clk IMX8MM_CLK_DRAM_APB>;
        operating-points-v2 = <&ddrc_opp_table>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/mmdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Multi Mode DDR controller (MMDC)

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

properties:
  compatible:
    oneOf:
      - const: fsl,imx6q-mmdc
      - items:
          - enum:
              - fsl,imx6qp-mmdc
              - fsl,imx6sl-mmdc
              - fsl,imx6sll-mmdc
              - fsl,imx6sx-mmdc
              - fsl,imx6ul-mmdc
              - fsl,imx7ulp-mmdc
          - const: fsl,imx6q-mmdc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx6qdl-clock.h>

    memory-controller@21b0000 {
        compatible = "fsl,imx6q-mmdc";
        reg = <0x021b0000 0x4000>;
        clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
    };

    memory-controller@21b4000 {
        compatible = "fsl,imx6q-mmdc";
        reg = <0x021b4000 0x4000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs NAND / External Memory Controller (NEMC) devicetree bindings

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

properties:
  reg:
    minItems: 1
    maxItems: 255

  ingenic,nemc-bus-width:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [8, 16]
    description: Specifies the bus width in bits.

  ingenic,nemc-tAS:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Address setup time in nanoseconds.

  ingenic,nemc-tAH:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Address hold time in nanoseconds.

  ingenic,nemc-tBP:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Burst pitch time in nanoseconds.

  ingenic,nemc-tAW:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Address wait time in nanoseconds.

  ingenic,nemc-tSTRV:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Static memory recovery time in nanoseconds.

required:
  - reg

additionalProperties: true
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ingenic,nemc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs NAND / External Memory Controller (NEMC) devicetree bindings

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

properties:
  $nodename:
    pattern: "^memory-controller@[0-9a-f]+$"

  compatible:
    oneOf:
      - enum:
          - ingenic,jz4740-nemc
          - ingenic,jz4780-nemc
      - items:
          - const: ingenic,jz4725b-nemc
          - const: ingenic,jz4740-nemc

  "#address-cells":
    const: 2

  "#size-cells":
    const: 1

  ranges: true

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

patternProperties:
  ".*@[0-9]+$":
    type: object

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - ranges
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
    #include <dt-bindings/gpio/gpio.h>
    nemc: memory-controller@13410000 {
      compatible = "ingenic,jz4780-nemc";
      reg = <0x13410000 0x10000>;
      #address-cells = <2>;
      #size-cells = <1>;
      ranges = <1 0 0x1b000000 0x1000000>,
         <2 0 0x1a000000 0x1000000>,
         <3 0 0x19000000 0x1000000>,
         <4 0 0x18000000 0x1000000>,
         <5 0 0x17000000 0x1000000>,
         <6 0 0x16000000 0x1000000>;

      clocks = <&cgu JZ4780_CLK_NEMC>;

      ethernet@6 {
        compatible = "davicom,dm9000";
        davicom,no-eeprom;

        pinctrl-names = "default";
        pinctrl-0 = <&pins_nemc_cs6>;

        reg = <6 0 1>, /* addr */
              <6 2 1>; /* data */

        ingenic,nemc-tAS = <15>;
        ingenic,nemc-tAH = <10>;
        ingenic,nemc-tBP = <20>;
        ingenic,nemc-tAW = <50>;
        ingenic,nemc-tSTRV = <100>;

        reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
        vcc-supply = <&eth0_power>;

        interrupt-parent = <&gpe>;
        interrupts = <19 4>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/marvell,mvebu-sdram-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell MVEBU SDRAM controller

maintainers:
  - Jan Luebbe <jlu@pengutronix.de>
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    const: marvell,armada-xp-sdram-controller

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    memory-controller@1400 {
        compatible = "marvell,armada-xp-sdram-controller";
        reg = <0x1400 0x500>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Peripheral-specific properties for a Memory Controller bus.

description:
  Many Memory Controllers need to add properties to peripheral devices.
  They could be common properties like reg or they could be controller
  specific like delay in clock or data lines, etc. These properties need
  to be defined in the peripheral node because they are per-peripheral
  and there can be multiple peripherals attached to a controller. All
  those properties are listed here. The controller specific properties
  should go in their own separate schema that should be referenced
  from here.

maintainers:
  - Marek Vasut <marex@denx.de>

properties:
  reg:
    description: Bank number, base address and size of the device.

  bank-width:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Bank width of the device, in bytes.
    enum: [1, 2, 4]

required:
  - reg

# The controller specific properties go here.
allOf:
  - $ref: st,stm32-fmc2-ebi-props.yaml#

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/mediatek,mt7621-memc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MT7621 SDRAM controller

maintainers:
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

properties:
  compatible:
    items:
      - const: mediatek,mt7621-memc
      - const: syscon

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    memory-controller@5000 {
        compatible = "mediatek,mt7621-memc", "syscon";
        reg = <0x5000 0x1000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SMI (Smart Multimedia Interface) Common

maintainers:
  - Yong Wu <yong.wu@mediatek.com>

description: |
  The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml

  MediaTek SMI have two generations of HW architecture, here is the list
  which generation the SoCs use:
  generation 1: mt2701 and mt7623.
  generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.

  There's slight differences between the two SMI, for generation 2, the
  register which control the iommu port is at each larb's register base. But
  for generation 1, the register is at smi ao base(smi always on register
  base). Besides that, the smi async clock should be prepared and enabled for
  SMI generation 1 to transform the smi clock into emi clock domain, but that is
  not needed for SMI generation 2.

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt2701-smi-common
          - mediatek,mt2712-smi-common
          - mediatek,mt6779-smi-common
          - mediatek,mt6795-smi-common
          - mediatek,mt8167-smi-common
          - mediatek,mt8173-smi-common
          - mediatek,mt8183-smi-common
          - mediatek,mt8186-smi-common
          - mediatek,mt8188-smi-common-vdo
          - mediatek,mt8188-smi-common-vpp
          - mediatek,mt8192-smi-common
          - mediatek,mt8195-smi-common-vdo
          - mediatek,mt8195-smi-common-vpp
          - mediatek,mt8195-smi-sub-common

      - description: for mt7623
        items:
          - const: mediatek,mt7623-smi-common
          - const: mediatek,mt2701-smi-common

  reg:
    maxItems: 1

  power-domains:
    maxItems: 1

  clocks:
    description: |
      apb and smi are mandatory. the async is only for generation 1 smi HW.
      gals(global async local sync) also is optional, see below.
    minItems: 2
    items:
      - description: apb is Advanced Peripheral Bus clock, It's the clock for
          setting the register.
      - description: smi is the clock for transfer data and command.
      - description: Either asynchronous clock to help transform the smi clock
          into the emi clock domain on Gen1 h/w, or the path0 clock of gals.
      - description: gals1 is the path1 clock of gals.

  clock-names:
    minItems: 2
    maxItems: 4

  mediatek,smi:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: a phandle to the smi-common node above. Only for sub-common.

required:
  - compatible
  - reg
  - power-domains
  - clocks
  - clock-names

allOf:
  - if:  # only for gen1 HW
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt2701-smi-common
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: apb
            - const: smi
            - const: async

  - if:  # only for sub common
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8195-smi-sub-common
    then:
      required:
        - mediatek,smi
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: apb
            - const: smi
            - const: gals0
    else:
      properties:
        mediatek,smi: false

  - if:  # for gen2 HW that have gals
      properties:
        compatible:
          enum:
            - mediatek,mt6779-smi-common
            - mediatek,mt8183-smi-common
            - mediatek,mt8186-smi-common
            - mediatek,mt8192-smi-common
            - mediatek,mt8195-smi-common-vdo
            - mediatek,mt8195-smi-common-vpp

    then:
      properties:
        clocks:
          minItems: 4
          maxItems: 4
        clock-names:
          items:
            - const: apb
            - const: smi
            - const: gals0
            - const: gals1

  - if:  # for gen2 HW that don't have gals
      properties:
        compatible:
          enum:
            - mediatek,mt2712-smi-common
            - mediatek,mt6795-smi-common
            - mediatek,mt8167-smi-common
            - mediatek,mt8173-smi-common

    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: apb
            - const: smi

additionalProperties: false

examples:
  - |+
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>

    smi_common: smi@14022000 {
            compatible = "mediatek,mt8173-smi-common";
            reg = <0x14022000 0x1000>;
            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
            clocks = <&mmsys CLK_MM_SMI_COMMON>,
                     <&mmsys CLK_MM_SMI_COMMON>;
            clock-names = "apb", "smi";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SMI (Smart Multimedia Interface) Local Arbiter

maintainers:
  - Yong Wu <yong.wu@mediatek.com>

description: |
  The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt2701-smi-larb
          - mediatek,mt2712-smi-larb
          - mediatek,mt6779-smi-larb
          - mediatek,mt6795-smi-larb
          - mediatek,mt8167-smi-larb
          - mediatek,mt8173-smi-larb
          - mediatek,mt8183-smi-larb
          - mediatek,mt8186-smi-larb
          - mediatek,mt8188-smi-larb
          - mediatek,mt8192-smi-larb
          - mediatek,mt8195-smi-larb

      - description: for mt7623
        items:
          - const: mediatek,mt7623-smi-larb
          - const: mediatek,mt2701-smi-larb

  reg:
    maxItems: 1

  clocks:
    description: |
      apb and smi are mandatory. gals(global async local sync) is optional.
    minItems: 2
    items:
      - description: apb is Advanced Peripheral Bus clock, It's the clock for
          setting the register.
      - description: smi is the clock for transfer data and command.
      - description: the clock for gals.

  clock-names:
    minItems: 2
    maxItems: 3

  power-domains:
    maxItems: 1

  mediatek,smi:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: a phandle to the smi_common node.

  mediatek,larb-id:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 31
    description: the hardware id of this larb. It's only required when this
      hardward id is not consecutive from its M4U point of view.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains

allOf:
  - if:  # HW has gals
      properties:
        compatible:
          enum:
            - mediatek,mt8183-smi-larb
            - mediatek,mt8186-smi-larb
            - mediatek,mt8188-smi-larb
            - mediatek,mt8195-smi-larb

    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 3
        clock-names:
          minItems: 2
          items:
            - const: apb
            - const: smi
            - const: gals

    else:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: apb
            - const: smi

  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt2701-smi-larb
              - mediatek,mt2712-smi-larb
              - mediatek,mt6779-smi-larb
              - mediatek,mt8186-smi-larb
              - mediatek,mt8188-smi-larb
              - mediatek,mt8192-smi-larb
              - mediatek,mt8195-smi-larb

    then:
      required:
        - mediatek,larb-id

additionalProperties: false

examples:
  - |+
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/power/mt8173-power.h>

    larb1: larb@16010000 {
      compatible = "mediatek,mt8173-smi-larb";
      reg = <0x16010000 0x1000>;
      mediatek,smi = <&smi_common>;
      power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
      clocks = <&vdecsys CLK_VDEC_CKEN>,
               <&vdecsys CLK_VDEC_LARB_CKEN>;
      clock-names = "apb", "smi";
    };


code:
Device tree bindings for MVEBU Device Bus controllers

The Device Bus controller available in some Marvell's SoC allows to control
different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
The actual devices are instantiated from the child nodes of a Device Bus node.

Required properties:

 - compatible:          Armada 370/XP SoC are supported using the
                        "marvell,mvebu-devbus" compatible string.

                        Orion5x SoC are supported using the
                        "marvell,orion-devbus" compatible string.

 - reg:                 A resource specifier for the register space.
                        This is the base address of a chip select within
			the controller's register space.
                        (see the example below)

 - #address-cells:      Must be set to 1
 - #size-cells:         Must be set to 1
 - ranges:              Must be set up to reflect the memory layout with four
                        integer values for each chip-select line in use:
                        0 <physical address of mapping> <size>

Optional properties:

 - devbus,keep-config   This property can optionally be used to keep
                        using the timing parameters set by the
                        bootloader. It makes all the timing properties
                        described below unused.

Timing properties for child nodes:

Read parameters:

 - devbus,turn-off-ps:  Defines the time during which the controller does not
                        drive the AD bus after the completion of a device read.
                        This prevents contentions on the Device Bus after a read
                        cycle from a slow device.
                        Mandatory, except if devbus,keep-config is used.

 - devbus,bus-width:    Defines the bus width, in bits (e.g. <16>).
                        Mandatory, except if devbus,keep-config is used.

 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
                        to read data sample. This parameter is useful for
                        synchronous pipelined devices, where the address
                        precedes the read data by one or two cycles.
                        Mandatory, except if devbus,keep-config is used.

 - devbus,acc-first-ps: Defines the time delay from the negation of
                        ALE[0] to the cycle that the first read data is sampled
                        by the controller.
                        Mandatory, except if devbus,keep-config is used.

 - devbus,acc-next-ps:  Defines the time delay between the cycle that
                        samples data N and the cycle that samples data N+1
                        (in burst accesses).
                        Mandatory, except if devbus,keep-config is used.

 - devbus,rd-setup-ps:  Defines the time delay between DEV_CSn assertion to
			DEV_OEn assertion. If set to 0 (default),
                        DEV_OEn and DEV_CSn are asserted at the same cycle.
                        This parameter has no affect on <acc-first-ps> parameter
                        (no affect on first data sample). Set <rd-setup-ps>
                        to a value smaller than <acc-first-ps>.
                        Mandatory for "marvell,mvebu-devbus" compatible string,
                        except if devbus,keep-config is used.

 - devbus,rd-hold-ps:   Defines the time between the last data sample to the
			de-assertion of DEV_CSn. If set to 0 (default),
			DEV_OEn and DEV_CSn are de-asserted at the same cycle
			(the cycle of the last data sample).
                        This parameter has no affect on DEV_OEn de-assertion.
                        DEV_OEn is always de-asserted the next cycle after
                        last data sampled. Also this parameter has no
                        affect on <turn-off-ps> parameter.
                        Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
                        Mandatory for "marvell,mvebu-devbus" compatible string,
                        except if devbus,keep-config is used.

Write parameters:

 - devbus,ale-wr-ps:    Defines the time delay from the ALE[0] negation cycle
			to the DEV_WEn assertion.
                        Mandatory.

 - devbus,wr-low-ps:    Defines the time during which DEV_WEn is active.
                        A[2:0] and Data are kept valid as long as DEV_WEn
                        is active. This parameter defines the setup time of
                        address and data to DEV_WEn rise.
                        Mandatory.

 - devbus,wr-high-ps:   Defines the time during which DEV_WEn is kept
                        inactive (high) between data beats of a burst write.
                        DEV_A[2:0] and Data are kept valid (do not toggle) for
                        <wr-high-ps> - <tick> ps.
			This parameter defines the hold time of address and
			data after DEV_WEn rise.
                        Mandatory.

 - devbus,sync-enable: Synchronous device enable.
                       1: True
                       0: False
                       Mandatory for "marvell,mvebu-devbus" compatible string,
                       except if devbus,keep-config is used.

An example for an Armada XP GP board, with a 16 MiB NOR device as child
is showed below. Note that the Device Bus driver is in charge of allocating
the mbus address decoding window for each of its child devices.
The window is created using the chip select specified in the child
device node together with the base address and size specified in the ranges
property. For instance, in the example below the allocated decoding window
will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
for chip select 0 (a.k.a DEV_BOOTCS).

This address window handling is done in this mvebu-devbus only as a temporary
solution. It will be removed when the support for mbus device tree binding is
added.

The reg property implicitly specifies the chip select as this:

  0x10400: DEV_BOOTCS
  0x10408: DEV_CS0
  0x10410: DEV_CS1
  0x10418: DEV_CS2
  0x10420: DEV_CS3

Example:

	devbus-bootcs@d0010400 {
		ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
		#address-cells = <1>;
		#size-cells = <1>;

		/* Device Bus parameters are required */

		/* Read parameters */
		devbus,bus-width    = <8>;
		devbus,turn-off-ps  = <60000>;
		devbus,badr-skew-ps = <0>;
		devbus,acc-first-ps = <124000>;
		devbus,acc-next-ps  = <248000>;
		devbus,rd-setup-ps  = <0>;
		devbus,rd-hold-ps   = <0>;

		/* Write parameters */
		devbus,sync-enable = <0>;
		devbus,wr-high-ps  = <60000>;
		devbus,wr-low-ps   = <60000>;
		devbus,ale-wr-ps   = <60000>;

		flash@0 {
			compatible = "cfi-flash";

			/* 16 MiB */
			reg = <0 0x1000000>;
			bank-width = <2>;
			#address-cells = <1>;
			#size-cells = <1>;

			/*
			 * We split the 16 MiB in two partitions,
			 * just as an example.
			 */
			partition@0 {
				label = "First";
				reg = <0 0x800000>;
			};

			partition@800000 {
				label = "Second";
				reg = <0x800000 0x800000>;
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra124 SoC External Memory Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: |
  The EMC interfaces with the off-chip SDRAM to service the request stream
  sent from the memory controller.

properties:
  compatible:
    const: nvidia,tegra124-emc

  reg:
    maxItems: 1

  clocks:
    items:
      - description: external memory clock

  clock-names:
    items:
      - const: emc

  "#interconnect-cells":
    const: 0

  nvidia,memory-controller:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle of the memory controller node

  power-domains:
    maxItems: 1
    description:
      Phandle of the SoC "core" power domain.

  operating-points-v2:
    description:
      Should contain freqs and voltages and opp-supported-hw property, which
      is a bitfield indicating SoC speedo ID mask.

patternProperties:
  "^emc-timings-[0-9]+$":
    type: object
    properties:
      nvidia,ram-code:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
          this timing set is used for

    patternProperties:
      "^timing-[0-9]+$":
        type: object
        properties:
          clock-frequency:
            description:
              external memory clock rate in Hz
            minimum: 1000000
            maximum: 1000000000

          nvidia,emc-auto-cal-config:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_AUTO_CAL_CONFIG register for this set of
              timings

          nvidia,emc-auto-cal-config2:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_AUTO_CAL_CONFIG2 register for this set of
              timings

          nvidia,emc-auto-cal-config3:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_AUTO_CAL_CONFIG3 register for this set of
              timings

          nvidia,emc-auto-cal-interval:
            description:
              pad calibration interval in microseconds
            $ref: /schemas/types.yaml#/definitions/uint32
            minimum: 0
            maximum: 2097151

          nvidia,emc-bgbias-ctl0:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_BGBIAS_CTL0 register for this set of timings

          nvidia,emc-cfg:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_CFG register for this set of timings

          nvidia,emc-cfg-2:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_CFG_2 register for this set of timings

          nvidia,emc-ctt-term-ctrl:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_CTT_TERM_CTRL register for this set of timings

          nvidia,emc-mode-1:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_MRW register for this set of timings

          nvidia,emc-mode-2:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_MRW2 register for this set of timings

          nvidia,emc-mode-4:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_MRW4 register for this set of timings

          nvidia,emc-mode-reset:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              reset value of the EMC_MRS register for this set of timings

          nvidia,emc-mrs-wait-cnt:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMR_MRS_WAIT_CNT register for this set of timings

          nvidia,emc-sel-dpd-ctrl:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_SEL_DPD_CTRL register for this set of timings

          nvidia,emc-xm2dqspadctrl2:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_XM2DQSPADCTRL2 register for this set of timings

          nvidia,emc-zcal-cnt-long:
            description:
              number of EMC clocks to wait before issuing any commands after
              clock change
            $ref: /schemas/types.yaml#/definitions/uint32
            minimum: 0
            maximum: 1023

          nvidia,emc-zcal-interval:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              value of the EMC_ZCAL_INTERVAL register for this set of timings

          nvidia,emc-configuration:
            description:
              EMC timing characterization data. These are the registers (see
              section "15.6.2 EMC Registers" in the TRM) whose values need to
              be specified, according to the board documentation.
            $ref: /schemas/types.yaml#/definitions/uint32-array
            items:
              - description: EMC_RC
              - description: EMC_RFC
              - description: EMC_RFC_SLR
              - description: EMC_RAS
              - description: EMC_RP
              - description: EMC_R2W
              - description: EMC_W2R
              - description: EMC_R2P
              - description: EMC_W2P
              - description: EMC_RD_RCD
              - description: EMC_WR_RCD
              - description: EMC_RRD
              - description: EMC_REXT
              - description: EMC_WEXT
              - description: EMC_WDV
              - description: EMC_WDV_MASK
              - description: EMC_QUSE
              - description: EMC_QUSE_WIDTH
              - description: EMC_IBDLY
              - description: EMC_EINPUT
              - description: EMC_EINPUT_DURATION
              - description: EMC_PUTERM_EXTRA
              - description: EMC_PUTERM_WIDTH
              - description: EMC_PUTERM_ADJ
              - description: EMC_CDB_CNTL_1
              - description: EMC_CDB_CNTL_2
              - description: EMC_CDB_CNTL_3
              - description: EMC_QRST
              - description: EMC_QSAFE
              - description: EMC_RDV
              - description: EMC_RDV_MASK
              - description: EMC_REFRESH
              - description: EMC_BURST_REFRESH_NUM
              - description: EMC_PRE_REFRESH_REQ_CNT
              - description: EMC_PDEX2WR
              - description: EMC_PDEX2RD
              - description: EMC_PCHG2PDEN
              - description: EMC_ACT2PDEN
              - description: EMC_AR2PDEN
              - description: EMC_RW2PDEN
              - description: EMC_TXSR
              - description: EMC_TXSRDLL
              - description: EMC_TCKE
              - description: EMC_TCKESR
              - description: EMC_TPD
              - description: EMC_TFAW
              - description: EMC_TRPAB
              - description: EMC_TCLKSTABLE
              - description: EMC_TCLKSTOP
              - description: EMC_TREFBW
              - description: EMC_FBIO_CFG6
              - description: EMC_ODT_WRITE
              - description: EMC_ODT_READ
              - description: EMC_FBIO_CFG5
              - description: EMC_CFG_DIG_DLL
              - description: EMC_CFG_DIG_DLL_PERIOD
              - description: EMC_DLL_XFORM_DQS0
              - description: EMC_DLL_XFORM_DQS1
              - description: EMC_DLL_XFORM_DQS2
              - description: EMC_DLL_XFORM_DQS3
              - description: EMC_DLL_XFORM_DQS4
              - description: EMC_DLL_XFORM_DQS5
              - description: EMC_DLL_XFORM_DQS6
              - description: EMC_DLL_XFORM_DQS7
              - description: EMC_DLL_XFORM_DQS8
              - description: EMC_DLL_XFORM_DQS9
              - description: EMC_DLL_XFORM_DQS10
              - description: EMC_DLL_XFORM_DQS11
              - description: EMC_DLL_XFORM_DQS12
              - description: EMC_DLL_XFORM_DQS13
              - description: EMC_DLL_XFORM_DQS14
              - description: EMC_DLL_XFORM_DQS15
              - description: EMC_DLL_XFORM_QUSE0
              - description: EMC_DLL_XFORM_QUSE1
              - description: EMC_DLL_XFORM_QUSE2
              - description: EMC_DLL_XFORM_QUSE3
              - description: EMC_DLL_XFORM_QUSE4
              - description: EMC_DLL_XFORM_QUSE5
              - description: EMC_DLL_XFORM_QUSE6
              - description: EMC_DLL_XFORM_QUSE7
              - description: EMC_DLL_XFORM_ADDR0
              - description: EMC_DLL_XFORM_ADDR1
              - description: EMC_DLL_XFORM_ADDR2
              - description: EMC_DLL_XFORM_ADDR3
              - description: EMC_DLL_XFORM_ADDR4
              - description: EMC_DLL_XFORM_ADDR5
              - description: EMC_DLL_XFORM_QUSE8
              - description: EMC_DLL_XFORM_QUSE9
              - description: EMC_DLL_XFORM_QUSE10
              - description: EMC_DLL_XFORM_QUSE11
              - description: EMC_DLL_XFORM_QUSE12
              - description: EMC_DLL_XFORM_QUSE13
              - description: EMC_DLL_XFORM_QUSE14
              - description: EMC_DLL_XFORM_QUSE15
              - description: EMC_DLI_TRIM_TXDQS0
              - description: EMC_DLI_TRIM_TXDQS1
              - description: EMC_DLI_TRIM_TXDQS2
              - description: EMC_DLI_TRIM_TXDQS3
              - description: EMC_DLI_TRIM_TXDQS4
              - description: EMC_DLI_TRIM_TXDQS5
              - description: EMC_DLI_TRIM_TXDQS6
              - description: EMC_DLI_TRIM_TXDQS7
              - description: EMC_DLI_TRIM_TXDQS8
              - description: EMC_DLI_TRIM_TXDQS9
              - description: EMC_DLI_TRIM_TXDQS10
              - description: EMC_DLI_TRIM_TXDQS11
              - description: EMC_DLI_TRIM_TXDQS12
              - description: EMC_DLI_TRIM_TXDQS13
              - description: EMC_DLI_TRIM_TXDQS14
              - description: EMC_DLI_TRIM_TXDQS15
              - description: EMC_DLL_XFORM_DQ0
              - description: EMC_DLL_XFORM_DQ1
              - description: EMC_DLL_XFORM_DQ2
              - description: EMC_DLL_XFORM_DQ3
              - description: EMC_DLL_XFORM_DQ4
              - description: EMC_DLL_XFORM_DQ5
              - description: EMC_DLL_XFORM_DQ6
              - description: EMC_DLL_XFORM_DQ7
              - description: EMC_XM2CMDPADCTRL
              - description: EMC_XM2CMDPADCTRL4
              - description: EMC_XM2CMDPADCTRL5
              - description: EMC_XM2DQPADCTRL2
              - description: EMC_XM2DQPADCTRL3
              - description: EMC_XM2CLKPADCTRL
              - description: EMC_XM2CLKPADCTRL2
              - description: EMC_XM2COMPPADCTRL
              - description: EMC_XM2VTTGENPADCTRL
              - description: EMC_XM2VTTGENPADCTRL2
              - description: EMC_XM2VTTGENPADCTRL3
              - description: EMC_XM2DQSPADCTRL3
              - description: EMC_XM2DQSPADCTRL4
              - description: EMC_XM2DQSPADCTRL5
              - description: EMC_XM2DQSPADCTRL6
              - description: EMC_DSR_VTTGEN_DRV
              - description: EMC_TXDSRVTTGEN
              - description: EMC_FBIO_SPARE
              - description: EMC_ZCAL_WAIT_CNT
              - description: EMC_MRS_WAIT_CNT2
              - description: EMC_CTT
              - description: EMC_CTT_DURATION
              - description: EMC_CFG_PIPE
              - description: EMC_DYN_SELF_REF_CONTROL
              - description: EMC_QPOP

        required:
          - clock-frequency
          - nvidia,emc-auto-cal-config
          - nvidia,emc-auto-cal-config2
          - nvidia,emc-auto-cal-config3
          - nvidia,emc-auto-cal-interval
          - nvidia,emc-bgbias-ctl0
          - nvidia,emc-cfg
          - nvidia,emc-cfg-2
          - nvidia,emc-ctt-term-ctrl
          - nvidia,emc-mode-1
          - nvidia,emc-mode-2
          - nvidia,emc-mode-4
          - nvidia,emc-mode-reset
          - nvidia,emc-mrs-wait-cnt
          - nvidia,emc-sel-dpd-ctrl
          - nvidia,emc-xm2dqspadctrl2
          - nvidia,emc-zcal-cnt-long
          - nvidia,emc-zcal-interval
          - nvidia,emc-configuration

        additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - nvidia,memory-controller
  - "#interconnect-cells"
  - operating-points-v2

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra124-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mc: memory-controller@70019000 {
        compatible = "nvidia,tegra124-mc";
        reg = <0x70019000 0x1000>;
        clocks = <&tegra_car TEGRA124_CLK_MC>;
        clock-names = "mc";

        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

        #iommu-cells = <1>;
        #reset-cells = <1>;
        #interconnect-cells = <1>;
    };

    external-memory-controller@7001b000 {
        compatible = "nvidia,tegra124-emc";
        reg = <0x7001b000 0x1000>;
        clocks = <&car TEGRA124_CLK_EMC>;
        clock-names = "emc";

        nvidia,memory-controller = <&mc>;
        operating-points-v2 = <&dvfs_opp_table>;
        power-domains = <&domain>;

        #interconnect-cells = <0>;

        emc-timings-0 {
            nvidia,ram-code = <3>;

            timing-0 {
                clock-frequency = <12750000>;

                nvidia,emc-auto-cal-config = <0xa1430000>;
                nvidia,emc-auto-cal-config2 = <0x00000000>;
                nvidia,emc-auto-cal-config3 = <0x00000000>;
                nvidia,emc-auto-cal-interval = <0x001fffff>;
                nvidia,emc-bgbias-ctl0 = <0x00000008>;
                nvidia,emc-cfg = <0x73240000>;
                nvidia,emc-cfg-2 = <0x000008c5>;
                nvidia,emc-ctt-term-ctrl = <0x00000802>;
                nvidia,emc-mode-1 = <0x80100003>;
                nvidia,emc-mode-2 = <0x80200008>;
                nvidia,emc-mode-4 = <0x00000000>;
                nvidia,emc-mode-reset = <0x80001221>;
                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
                nvidia,emc-zcal-cnt-long = <0x00000042>;
                nvidia,emc-zcal-interval = <0x00000000>;

                nvidia,emc-configuration = <
                    0x00000000 /* EMC_RC */
                    0x00000003 /* EMC_RFC */
                    0x00000000 /* EMC_RFC_SLR */
                    0x00000000 /* EMC_RAS */
                    0x00000000 /* EMC_RP */
                    0x00000004 /* EMC_R2W */
                    0x0000000a /* EMC_W2R */
                    0x00000003 /* EMC_R2P */
                    0x0000000b /* EMC_W2P */
                    0x00000000 /* EMC_RD_RCD */
                    0x00000000 /* EMC_WR_RCD */
                    0x00000003 /* EMC_RRD */
                    0x00000003 /* EMC_REXT */
                    0x00000000 /* EMC_WEXT */
                    0x00000006 /* EMC_WDV */
                    0x00000006 /* EMC_WDV_MASK */
                    0x00000006 /* EMC_QUSE */
                    0x00000002 /* EMC_QUSE_WIDTH */
                    0x00000000 /* EMC_IBDLY */
                    0x00000005 /* EMC_EINPUT */
                    0x00000005 /* EMC_EINPUT_DURATION */
                    0x00010000 /* EMC_PUTERM_EXTRA */
                    0x00000003 /* EMC_PUTERM_WIDTH */
                    0x00000000 /* EMC_PUTERM_ADJ */
                    0x00000000 /* EMC_CDB_CNTL_1 */
                    0x00000000 /* EMC_CDB_CNTL_2 */
                    0x00000000 /* EMC_CDB_CNTL_3 */
                    0x00000004 /* EMC_QRST */
                    0x0000000c /* EMC_QSAFE */
                    0x0000000d /* EMC_RDV */
                    0x0000000f /* EMC_RDV_MASK */
                    0x00000060 /* EMC_REFRESH */
                    0x00000000 /* EMC_BURST_REFRESH_NUM */
                    0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
                    0x00000002 /* EMC_PDEX2WR */
                    0x00000002 /* EMC_PDEX2RD */
                    0x00000001 /* EMC_PCHG2PDEN */
                    0x00000000 /* EMC_ACT2PDEN */
                    0x00000007 /* EMC_AR2PDEN */
                    0x0000000f /* EMC_RW2PDEN */
                    0x00000005 /* EMC_TXSR */
                    0x00000005 /* EMC_TXSRDLL */
                    0x00000004 /* EMC_TCKE */
                    0x00000005 /* EMC_TCKESR */
                    0x00000004 /* EMC_TPD */
                    0x00000000 /* EMC_TFAW */
                    0x00000000 /* EMC_TRPAB */
                    0x00000005 /* EMC_TCLKSTABLE */
                    0x00000005 /* EMC_TCLKSTOP */
                    0x00000064 /* EMC_TREFBW */
                    0x00000000 /* EMC_FBIO_CFG6 */
                    0x00000000 /* EMC_ODT_WRITE */
                    0x00000000 /* EMC_ODT_READ */
                    0x106aa298 /* EMC_FBIO_CFG5 */
                    0x002c00a0 /* EMC_CFG_DIG_DLL */
                    0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
                    0x00064000 /* EMC_DLL_XFORM_DQS0 */
                    0x00064000 /* EMC_DLL_XFORM_DQS1 */
                    0x00064000 /* EMC_DLL_XFORM_DQS2 */
                    0x00064000 /* EMC_DLL_XFORM_DQS3 */
                    0x00064000 /* EMC_DLL_XFORM_DQS4 */
                    0x00064000 /* EMC_DLL_XFORM_DQS5 */
                    0x00064000 /* EMC_DLL_XFORM_DQS6 */
                    0x00064000 /* EMC_DLL_XFORM_DQS7 */
                    0x00064000 /* EMC_DLL_XFORM_DQS8 */
                    0x00064000 /* EMC_DLL_XFORM_DQS9 */
                    0x00064000 /* EMC_DLL_XFORM_DQS10 */
                    0x00064000 /* EMC_DLL_XFORM_DQS11 */
                    0x00064000 /* EMC_DLL_XFORM_DQS12 */
                    0x00064000 /* EMC_DLL_XFORM_DQS13 */
                    0x00064000 /* EMC_DLL_XFORM_DQS14 */
                    0x00064000 /* EMC_DLL_XFORM_DQS15 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE0 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE1 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE2 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE3 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE4 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE5 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE6 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE7 */
                    0x00000000 /* EMC_DLL_XFORM_ADDR0 */
                    0x00000000 /* EMC_DLL_XFORM_ADDR1 */
                    0x00000000 /* EMC_DLL_XFORM_ADDR2 */
                    0x00000000 /* EMC_DLL_XFORM_ADDR3 */
                    0x00000000 /* EMC_DLL_XFORM_ADDR4 */
                    0x00000000 /* EMC_DLL_XFORM_ADDR5 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE8 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE9 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE10 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE11 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE12 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE13 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE14 */
                    0x00000000 /* EMC_DLL_XFORM_QUSE15 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
                    0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
                    0x000fc000 /* EMC_DLL_XFORM_DQ0 */
                    0x000fc000 /* EMC_DLL_XFORM_DQ1 */
                    0x000fc000 /* EMC_DLL_XFORM_DQ2 */
                    0x000fc000 /* EMC_DLL_XFORM_DQ3 */
                    0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
                    0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
                    0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
                    0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
                    0x10000280 /* EMC_XM2CMDPADCTRL */
                    0x00000000 /* EMC_XM2CMDPADCTRL4 */
                    0x00111111 /* EMC_XM2CMDPADCTRL5 */
                    0x00000000 /* EMC_XM2DQPADCTRL2 */
                    0x00000000 /* EMC_XM2DQPADCTRL3 */
                    0x77ffc081 /* EMC_XM2CLKPADCTRL */
                    0x00000e0e /* EMC_XM2CLKPADCTRL2 */
                    0x81f1f108 /* EMC_XM2COMPPADCTRL */
                    0x07070004 /* EMC_XM2VTTGENPADCTRL */
                    0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
                    0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
                    0x51451400 /* EMC_XM2DQSPADCTRL3 */
                    0x00514514 /* EMC_XM2DQSPADCTRL4 */
                    0x00514514 /* EMC_XM2DQSPADCTRL5 */
                    0x51451400 /* EMC_XM2DQSPADCTRL6 */
                    0x0000003f /* EMC_DSR_VTTGEN_DRV */
                    0x00000007 /* EMC_TXDSRVTTGEN */
                    0x00000000 /* EMC_FBIO_SPARE */
                    0x00000042 /* EMC_ZCAL_WAIT_CNT */
                    0x000e000e /* EMC_MRS_WAIT_CNT2 */
                    0x00000000 /* EMC_CTT */
                    0x00000003 /* EMC_CTT_DURATION */
                    0x0000f2f3 /* EMC_CFG_PIPE */
                    0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
                    0x0000000a /* EMC_QPOP */
                >;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra124 SoC Memory Controller

maintainers:
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
  These are interleaved to provide high performance with the load shared across
  two memory channels. The Tegra124 Memory Controller handles memory requests
  from internal clients and arbitrates among them to allocate memory bandwidth
  for DDR3L and LPDDR3 SDRAMs.

properties:
  compatible:
    const: nvidia,tegra124-mc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: mc

  interrupts:
    maxItems: 1

  "#reset-cells":
    const: 1

  "#iommu-cells":
    const: 1

  "#interconnect-cells":
    const: 1

patternProperties:
  "^emc-timings-[0-9]+$":
    type: object
    properties:
      nvidia,ram-code:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Value of RAM_CODE this timing set is used for.

    patternProperties:
      "^timing-[0-9]+$":
        type: object
        properties:
          clock-frequency:
            description:
              Memory clock rate in Hz.
            minimum: 1000000
            maximum: 1066000000

          nvidia,emem-configuration:
            $ref: /schemas/types.yaml#/definitions/uint32-array
            description: |
              Values to be written to the EMEM register block. See section
              "15.6.1 MC Registers" in the TRM.
            items:
              - description: MC_EMEM_ARB_CFG
              - description: MC_EMEM_ARB_OUTSTANDING_REQ
              - description: MC_EMEM_ARB_TIMING_RCD
              - description: MC_EMEM_ARB_TIMING_RP
              - description: MC_EMEM_ARB_TIMING_RC
              - description: MC_EMEM_ARB_TIMING_RAS
              - description: MC_EMEM_ARB_TIMING_FAW
              - description: MC_EMEM_ARB_TIMING_RRD
              - description: MC_EMEM_ARB_TIMING_RAP2PRE
              - description: MC_EMEM_ARB_TIMING_WAP2PRE
              - description: MC_EMEM_ARB_TIMING_R2R
              - description: MC_EMEM_ARB_TIMING_W2W
              - description: MC_EMEM_ARB_TIMING_R2W
              - description: MC_EMEM_ARB_TIMING_W2R
              - description: MC_EMEM_ARB_DA_TURNS
              - description: MC_EMEM_ARB_DA_COVERS
              - description: MC_EMEM_ARB_MISC0
              - description: MC_EMEM_ARB_MISC1
              - description: MC_EMEM_ARB_RING1_THROTTLE

        required:
          - clock-frequency
          - nvidia,emem-configuration

        additionalProperties: false

    required:
      - nvidia,ram-code

    additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - "#reset-cells"
  - "#iommu-cells"
  - "#interconnect-cells"

additionalProperties: false

examples:
  - |
    memory-controller@70019000 {
        compatible = "nvidia,tegra124-mc";
        reg = <0x70019000 0x1000>;
        clocks = <&tegra_car 32>;
        clock-names = "mc";

        interrupts = <0 77 4>;

        #iommu-cells = <1>;
        #reset-cells = <1>;
        #interconnect-cells = <1>;

        emc-timings-3 {
            nvidia,ram-code = <3>;

            timing-12750000 {
                clock-frequency = <12750000>;

                nvidia,emem-configuration = <
                    0x40040001 /* MC_EMEM_ARB_CFG */
                    0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
                    0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
                    0x00000001 /* MC_EMEM_ARB_TIMING_RP */
                    0x00000002 /* MC_EMEM_ARB_TIMING_RC */
                    0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
                    0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
                    0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
                    0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
                    0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
                    0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
                    0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
                    0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
                    0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
                    0x06030203 /* MC_EMEM_ARB_DA_TURNS */
                    0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
                    0x77e30303 /* MC_EMEM_ARB_MISC0 */
                    0x70000f03 /* MC_EMEM_ARB_MISC1 */
                    0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
                >;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra186 (and later) SoC Memory Controller

maintainers:
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
  into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
  handles memory requests for 40-bit virtual addresses from internal clients
  and arbitrates among them to allocate memory bandwidth.

  Up to 15 GiB of physical memory can be supported. Security features such as
  encryption of traffic to and from DRAM via general security apertures are
  available for video and other secure applications, as well as DRAM ECC for
  automotive safety applications (single bit error correction and double bit
  error detection).

properties:
  $nodename:
    pattern: "^memory-controller@[0-9a-f]+$"

  compatible:
    items:
      - enum:
          - nvidia,tegra186-mc
          - nvidia,tegra194-mc
          - nvidia,tegra234-mc

  reg:
    minItems: 6
    maxItems: 18

  reg-names:
    minItems: 6
    maxItems: 18

  interrupts:
    items:
      - description: MC general interrupt

  "#address-cells":
    const: 2

  "#size-cells":
    const: 2

  ranges: true

  dma-ranges: true

  "#interconnect-cells":
    const: 1

patternProperties:
  "^external-memory-controller@[0-9a-f]+$":
    description:
      The bulk of the work involved in controlling the external memory
      controller on NVIDIA Tegra186 and later is performed on the BPMP. This
      coprocessor exposes the EMC clock that is used to set the frequency at
      which the external memory is clocked and a remote procedure call that
      can be used to obtain the set of available frequencies.
    type: object
    properties:
      compatible:
        items:
          - enum:
              - nvidia,tegra186-emc
              - nvidia,tegra194-emc
              - nvidia,tegra234-emc

      reg:
        minItems: 1
        maxItems: 2

      interrupts:
        items:
          - description: EMC general interrupt

      clocks:
        items:
          - description: external memory clock

      clock-names:
        items:
          - const: emc

      "#interconnect-cells":
        const: 0

      nvidia,bpmp:
        $ref: /schemas/types.yaml#/definitions/phandle
        description:
          phandle of the node representing the BPMP

    allOf:
      - if:
          properties:
            compatible:
              const: nvidia,tegra186-emc
        then:
          properties:
            reg:
              maxItems: 1

      - if:
          properties:
            compatible:
              const: nvidia,tegra194-emc
        then:
          properties:
            reg:
              minItems: 2

      - if:
          properties:
            compatible:
              const: nvidia,tegra234-emc
        then:
          properties:
            reg:
              minItems: 2

    additionalProperties: false

    required:
      - compatible
      - reg
      - interrupts
      - clocks
      - clock-names
      - "#interconnect-cells"
      - nvidia,bpmp

allOf:
  - if:
      properties:
        compatible:
          const: nvidia,tegra186-mc
    then:
      properties:
        reg:
          maxItems: 6
          description: 5 memory controller channels and 1 for stream-id registers

        reg-names:
          items:
            - const: sid
            - const: broadcast
            - const: ch0
            - const: ch1
            - const: ch2
            - const: ch3

  - if:
      properties:
        compatible:
          const: nvidia,tegra194-mc
    then:
      properties:
        reg:
          minItems: 18
          description: 17 memory controller channels and 1 for stream-id registers

        reg-names:
          items:
            - const: sid
            - const: broadcast
            - const: ch0
            - const: ch1
            - const: ch2
            - const: ch3
            - const: ch4
            - const: ch5
            - const: ch6
            - const: ch7
            - const: ch8
            - const: ch9
            - const: ch10
            - const: ch11
            - const: ch12
            - const: ch13
            - const: ch14
            - const: ch15

  - if:
      properties:
        compatible:
          const: nvidia,tegra234-mc
    then:
      properties:
        reg:
          minItems: 18
          description: 17 memory controller channels and 1 for stream-id registers

        reg-names:
          items:
            - const: sid
            - const: broadcast
            - const: ch0
            - const: ch1
            - const: ch2
            - const: ch3
            - const: ch4
            - const: ch5
            - const: ch6
            - const: ch7
            - const: ch8
            - const: ch9
            - const: ch10
            - const: ch11
            - const: ch12
            - const: ch13
            - const: ch14
            - const: ch15

additionalProperties: false

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - "#address-cells"
  - "#size-cells"

examples:
  - |
    #include <dt-bindings/clock/tegra186-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        memory-controller@2c00000 {
            compatible = "nvidia,tegra186-mc";
            reg = <0x0 0x02c00000 0x0 0x10000>,    /* MC-SID */
                  <0x0 0x02c10000 0x0 0x10000>,    /* Broadcast channel */
                  <0x0 0x02c20000 0x0 0x10000>,    /* MC0 */
                  <0x0 0x02c30000 0x0 0x10000>,    /* MC1 */
                  <0x0 0x02c40000 0x0 0x10000>,    /* MC2 */
                  <0x0 0x02c50000 0x0 0x10000>;    /* MC3 */
            reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
            interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;

            #address-cells = <2>;
            #size-cells = <2>;

            ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;

            /*
             * Memory clients have access to all 40 bits that the memory
             * controller can address.
             */
            dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;

            external-memory-controller@2c60000 {
                compatible = "nvidia,tegra186-emc";
                reg = <0x0 0x02c60000 0x0 0x50000>;
                interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&bpmp TEGRA186_CLK_EMC>;
                clock-names = "emc";

                #interconnect-cells = <0>;

                nvidia,bpmp = <&bpmp>;
            };
        };
    };