code:
Specifying GPIO information for devices
=======================================

1) gpios property
-----------------

GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
of this GPIO for the device. While a non-existent <name> is considered valid
for compatibility reasons (resolving to the "gpios" property), it is not allowed
for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
bindings use it, but are only supported for compatibility reasons and should not
be used for newer bindings since it has been deprecated.

GPIO properties can contain one or more GPIO phandles, but only in exceptional
cases should they contain more than one. If your device uses several GPIOs with
distinct functions, reference each of them under its own property, giving it a
meaningful name. The only case where an array of GPIOs is accepted is when
several GPIOs serve the same function (e.g. a parallel data line).

The exact purpose of each gpios property must be documented in the device tree
binding of the device.

The following example could be used to describe GPIO pins used as device enable
and bit-banged data signals:

	gpio1: gpio1 {
		gpio-controller;
		#gpio-cells = <2>;
	};
	[...]

	data-gpios = <&gpio1 12 0>,
		     <&gpio1 13 0>,
		     <&gpio1 14 0>,
		     <&gpio1 15 0>;

In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is
a local offset to the GPIO line and the second cell represent consumer flags,
such as if the consumer desire the line to be active low (inverted) or open
drain. This is the recommended practice.

The exact meaning of each specifier cell is controller specific, and must be
documented in the device tree binding for the device, but it is strongly
recommended to use the two-cell approach.

Most controllers are specifying a generic flag bitfield in the last cell, so
for these, use the macros defined in
include/dt-bindings/gpio/gpio.h whenever possible:

Example of a node using GPIOs:

	node {
		enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;
	};

GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.

Optional standard bitfield specifiers for the last cell:

- Bit 0: 0 means active high, 1 means active low
- Bit 1: 0 mean push-pull wiring, see:
           https://en.wikipedia.org/wiki/Push-pull_output
         1 means single-ended wiring, see:
           https://en.wikipedia.org/wiki/Single-ended_triode
- Bit 2: 0 means open-source, 1 means open drain, see:
           https://en.wikipedia.org/wiki/Open_collector
- Bit 3: 0 means the output should be maintained during sleep/low-power mode
         1 means the output state can be lost during sleep/low-power mode
- Bit 4: 0 means no pull-up resistor should be enabled
         1 means a pull-up resistor should be enabled
         This setting only applies to hardware with a simple on/off
         control for pull-up configuration. If the hardware has more
         elaborate pull-up configuration, it should be represented
         using a pin control binding.
- Bit 5: 0 means no pull-down resistor should be enabled
         1 means a pull-down resistor should be enabled
         This setting only applies to hardware with a simple on/off
         control for pull-down configuration. If the hardware has more
         elaborate pull-down configuration, it should be represented
         using a pin control binding.

1.1) GPIO specifier best practices
----------------------------------

A gpio-specifier should contain a flag indicating the GPIO polarity; active-
high or active-low. If it does, the following best practices should be
followed:

The gpio-specifier's polarity flag should represent the physical level at the
GPIO controller that achieves (or represents, for inputs) a logically asserted
value at the device. The exact definition of logically asserted should be
defined by the binding for the device. If the board inverts the signal between
the GPIO controller and the device, then the gpio-specifier will represent the
opposite physical level than the signal at the device's pin.

When the device's signal polarity is configurable, the binding for the
device must either:

a) Define a single static polarity for the signal, with the expectation that
any software using that binding would statically program the device to use
that signal polarity.

The static choice of polarity may be either:

a1) (Preferred) Dictated by a binding-specific DT property.

or:

a2) Defined statically by the DT binding itself.

In particular, the polarity cannot be derived from the gpio-specifier, since
that would prevent the DT from separately representing the two orthogonal
concepts of configurable signal polarity in the device, and possible board-
level signal inversion.

or:

b) Pick a single option for device signal polarity, and document this choice
in the binding. The gpio-specifier should represent the polarity of the signal
(at the GPIO controller) assuming that the device is configured for this
particular signal polarity choice. If software chooses to program the device
to generate or receive a signal of the opposite polarity, software will be
responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
controller.

2) gpio-controller nodes
------------------------

Every GPIO controller node must contain both an empty "gpio-controller"
property, and a #gpio-cells integer property, which indicates the number of
cells in a gpio-specifier.

Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
instance of a hardware IP core on a silicon die, usually exposed to the
programmer as a coherent range of I/O addresses. Usually each such bank is
exposed in the device tree as an individual gpio-controller node, reflecting
the fact that the hardware was synthesized by reusing the same IP block a
few times over.

Optionally, a GPIO controller may have a "ngpios" property. This property
indicates the number of in-use slots of available slots for GPIOs. The
typical example is something like this: the hardware register is 32 bits
wide, but only 18 of the bits have a physical counterpart. The driver is
generally written so that all 32 bits can be used, but the IP block is reused
in a lot of designs, some using all 32 bits, some using 18 and some using
12. In this case, setting "ngpios = <18>;" informs the driver that only the
first 18 GPIOs, at local offset 0 .. 17, are in use.

If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
additional set of tuples is needed to specify which GPIOs are unusable, with
the gpio-reserved-ranges binding. This property indicates the start and size
of the GPIOs that can't be used.

Optionally, a GPIO controller may have a "gpio-line-names" property. This is
an array of strings defining the names of the GPIO lines going out of the
GPIO controller. This name should be the most meaningful producer name
for the system, such as a rail name indicating the usage. Package names
such as pin name are discouraged: such lines have opaque names (since they
are by definition generic purpose) and such names are usually not very
helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are
reasonable line names as they describe what the line is used for. "GPIO0"
is not a good name to give to a GPIO line. Placeholders are discouraged:
rather use the "" (blank string) if the use of the GPIO line is undefined
in your design. The names are assigned starting from line offset 0 from
left to right from the passed array. An incomplete array (where the number
of passed named are less than ngpios) will still be used up until the last
provided valid line index.

Example:

gpio-controller@00000000 {
	compatible = "foo";
	reg = <0x00000000 0x1000>;
	gpio-controller;
	#gpio-cells = <2>;
	ngpios = <18>;
	gpio-reserved-ranges = <0 4>, <12 2>;
	gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
		"LED G", "LED B", "Col A", "Col B", "Col C", "Col D",
		"Row A", "Row B", "Row C", "Row D", "NMI button",
		"poweroff", "reset";
}

The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
providing automatic GPIO request and configuration as part of the
gpio-controller's driver probe function.

Each GPIO hog definition is represented as a child node of the GPIO controller.
Required properties:
- gpio-hog:   A property specifying that this child node represents a GPIO hog.
- gpios:      Store the GPIO information (id, flags, ...) for each GPIO to
	      affect. Shall contain an integer multiple of the number of cells
	      specified in its parent node (GPIO controller node).
Only one of the following properties scanned in the order shown below.
This means that when multiple properties are present they will be searched
in the order presented below and the first match is taken as the intended
configuration.
- input:      A property specifying to set the GPIO direction as input.
- output-low  A property specifying to set the GPIO direction as output with
	      the value low.
- output-high A property specifying to set the GPIO direction as output with
	      the value high.

Optional properties:
- line-name:  The GPIO label name. If not present the node name is used.

Example of two SOC GPIO banks defined as gpio-controller nodes:

	qe_pio_a: gpio-controller@1400 {
		compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
		reg = <0x1400 0x18>;
		gpio-controller;
		#gpio-cells = <2>;

		line_b-hog {
			gpio-hog;
			gpios = <6 0>;
			output-low;
			line-name = "foo-bar-gpio";
		};
	};

	qe_pio_e: gpio-controller@1460 {
		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
		reg = <0x1460 0x18>;
		gpio-controller;
		#gpio-cells = <2>;
	};

2.1) gpio- and pin-controller interaction
-----------------------------------------

Some or all of the GPIOs provided by a GPIO controller may be routed to pins
on the package via a pin controller. This allows muxing those pins between
GPIO and other functions. It is a fairly common practice among silicon
engineers.

2.2) Ordinary (numerical) GPIO ranges
-------------------------------------

It is useful to represent which GPIOs correspond to which pins on which pin
controllers. The gpio-ranges property described below represents this with
a discrete set of ranges mapping pins from the pin controller local number space
to pins in the GPIO controller local number space.

The format is: <[pin controller phandle], [GPIO controller offset],
                [pin controller offset], [number of pins]>;

The GPIO controller offset pertains to the GPIO controller node containing the
range definition.

The pin controller node referenced by the phandle must conform to the bindings
described in pinctrl/pinctrl-bindings.txt.

Each offset runs from 0 to N. It is perfectly fine to pile any number of
ranges with just one pin-to-GPIO line mapping if the ranges are concocted, but
in practice these ranges are often lumped in discrete sets.

Example:

    gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>;

This means:
- pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and
- pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29

Verbose example:

	qe_pio_e: gpio-controller@1460 {
		#gpio-cells = <2>;
		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
		reg = <0x1460 0x18>;
		gpio-controller;
		gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
	};

Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's
pins 50..69.

2.3) GPIO ranges from named pin groups
--------------------------------------

It is also possible to use pin groups for gpio ranges when pin groups are the
easiest and most convenient mapping.

Both both <pinctrl-base> and <count> must set to 0 when using named pin groups
names.

The property gpio-ranges-group-names must contain exactly one string for each
range.

Elements of gpio-ranges-group-names must contain the name of a pin group
defined in the respective pin controller. The number of pins/GPIO lines in the
range is the number of pins in that pin group. The number of pins of that
group is defined int the implementation and not in the device tree.

If numerical and named pin groups are mixed, the string corresponding to a
numerical pin range in gpio-ranges-group-names must be empty.

Example:

	gpio_pio_i: gpio-controller@14b0 {
		#gpio-cells = <2>;
		compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
		reg = <0x1480 0x18>;
		gpio-controller;
		gpio-ranges =			<&pinctrl1 0 20 10>,
						<&pinctrl2 10 0 0>,
						<&pinctrl1 15 0 10>,
						<&pinctrl2 25 0 0>;
		gpio-ranges-group-names =	"",
						"foo",
						"",
						"bar";
	};

Here, three GPIO ranges are defined referring to two pin controllers.

pinctrl1 GPIO ranges are defined using pin numbers whereas the GPIO ranges
in pinctrl2 are defined using the pin groups named "foo" and "bar".

Previous versions of this binding required all pin controller nodes that
were referenced by any gpio-ranges property to contain a property named
#gpio-range-cells with value <3>. This requirement is now deprecated.
However, that property may still exist in older device trees for
compatibility reasons, and would still be required even in new device
trees that need to be compatible with older software.


code:
* Atmel GPIO controller (PIO)

Required properties:
- compatible: "atmel,<chip>-gpio", where <chip> is at91rm9200 or at91sam9x5.
- reg: Should contain GPIO controller registers location and length
- interrupts: Should be the port interrupt shared by all the pins.
- #gpio-cells: Should be two.  The first cell is the pin number and
  the second cell is used to specify optional parameters to declare if the GPIO
  is active high or low. See gpio.txt.
- gpio-controller: Marks the device node as a GPIO controller.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two. The first cell is the pin number and the
  second cell is used to specify irq type flags, see the two cell description
  in interrupt-controller/interrupts.txt for details.

optional properties:
- #gpio-lines: Number of gpio if absent 32.

Example:
	pioA: gpio@fffff200 {
		compatible = "atmel,at91rm9200-gpio";
		reg = <0xfffff200 0x100>;
		interrupts = <2 4>;
		#gpio-cells = <2>;
		gpio-controller;
		#gpio-lines = <19>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

repo_name: angery/linux


code:
NXP LPC32xx SoC GPIO controller

Required properties:
- compatible: must be "nxp,lpc3220-gpio"
- reg: Physical base address and length of the controller's registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be 3:
   1) bank:
      0: GPIO P0
      1: GPIO P1
      2: GPIO P2
      3: GPIO P3
      4: GPI P3
      5: GPO P3
   2) pin number
   3) optional parameters:
      - bit 0 specifies polarity (0 for normal, 1 for inverted)
- reg: Index of the GPIO group

Example:

	gpio: gpio@40028000 {
		compatible = "nxp,lpc3220-gpio";
		reg = <0x40028000 0x1000>;
		gpio-controller;
		#gpio-cells = <3>; /* bank, pin, flags */
	};

	leds {
		compatible = "gpio-leds";

		led0 {
			gpios = <&gpio 5 1 1>; /* GPO_P3 1, active low */
			linux,default-trigger = "heartbeat";
			default-state = "off";
		};

		led1 {
			gpios = <&gpio 5 14 1>; /* GPO_P3 14, active low */
			linux,default-trigger = "timer";
			default-state = "off";
		};
	};


code:
* Oxford Semiconductor OXNAS SoC GPIO Controller

Please refer to gpio.txt for generic information regarding GPIO bindings.

Required properties:
 - compatible: "oxsemi,ox810se-gpio" or "oxsemi,ox820-gpio"
 - reg: Base address and length for the device.
 - interrupts: The port interrupt shared by all pins.
 - gpio-controller: Marks the port as GPIO controller.
 - #gpio-cells: Two. The first cell is the pin number and
   the second cell is used to specify the gpio polarity as defined in
   defined in <dt-bindings/gpio/gpio.h>:
      0 = GPIO_ACTIVE_HIGH
      1 = GPIO_ACTIVE_LOW
 - interrupt-controller: Marks the device node as an interrupt controller.
 - #interrupt-cells: Two. The first cell is the GPIO number and second cell
   is used to specify the trigger type as defined in
   <dt-bindings/interrupt-controller/irq.h>:
      IRQ_TYPE_EDGE_RISING
      IRQ_TYPE_EDGE_FALLING
      IRQ_TYPE_EDGE_BOTH
 - gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the
   gpio base and count, should be in the format of numeric-gpio-range as
   specified in the gpio.txt file.

Example:

gpio0: gpio@0 {
	compatible = "oxsemi,ox810se-gpio";
	reg = <0x000000 0x100000>;
	interrupts = <21>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&pinctrl 0 0 32>;
};

keys {
	...

	button-esc {
		label = "ESC";
		linux,code = <1>;
		gpios = <&gpio0 12 0>;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/hisilicon,ascend910-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: HiSilicon common GPIO controller

maintainers:
  - Jay Fang <f.fangjian@huawei.com>

description:
  The HiSilicon common GPIO controller can be used for many different
  types of SoC such as Huawei Ascend AI series chips.

properties:
  compatible:
    const: hisilicon,ascend910-gpio

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  gpio-controller: true

  "#gpio-cells":
    const: 2

  ngpios:
    minimum: 1
    maximum: 32

required:
  - compatible
  - reg
  - interrupts
  - gpio-controller
  - "#gpio-cells"
  - ngpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gpio@840d0000 {
      compatible = "hisilicon,ascend910-gpio";
      reg = <0x840d0000 0x1000>;
      ngpios = <32>;
      gpio-controller;
      #gpio-cells = <2>;
      interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
    };


code:
* IBM/AMCC/APM GPIO Controller for PowerPC 4XX series and compatible SoCs

All GPIOs are pin-shared with other functions. DCRs control whether a
particular pin that has GPIO capabilities acts as a GPIO or is used for
another purpose. GPIO outputs are separately programmable to emulate
an open-drain driver.

Required properties:
	- compatible: must be "ibm,ppc4xx-gpio"
	- reg: address and length of the register set for the device
	- #gpio-cells: must be set to 2. The first cell is the pin number
		and the second cell is used to specify the gpio polarity:
		0 = active high
		1 = active low
	- gpio-controller: marks the device node as a gpio controller.

Example:

GPIO0: gpio@ef600b00 {
	compatible = "ibm,ppc4xx-gpio";
	reg = <0xef600b00 0x00000048>;
	#gpio-cells = <2>;
	gpio-controller;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/idt,32434-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: IDT 79RC32434 GPIO controller

maintainers:
  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>

properties:
  compatible:
    const: idt,32434-gpio

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: gpio
      - const: pic

  gpio-controller: true

  "#gpio-cells":
    const: 2

  ngpios:
    minimum: 1
    maximum: 32

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - gpio-controller
  - "#gpio-cells"

additionalProperties: false

examples:
  - |
    gpio0: gpio@50004 {
        compatible = "idt,32434-gpio";
        reg = <0x50004 0x10>, <0x38030 0x0c>;
        reg-names = "gpio", "pic";

        interrupt-controller;
        #interrupt-cells = <2>;

        interrupt-parent = <&cpuintc>;
        interrupts = <6>;

        gpio-controller;
        #gpio-cells = <2>;

        ngpios = <14>;
    };


code:
Intel IXP4xx XScale Networking Processors GPIO

This GPIO controller is found in the Intel IXP4xx processors.
It supports 16 GPIO lines.

The interrupt portions of the GPIO controller is hierarchical:
the synchronous edge detector is part of the GPIO block, but the
actual enabling/disabling of the interrupt line is done in the
main IXP4xx interrupt controller which has a 1:1 mapping for
the first 12 GPIO lines to 12 system interrupts.

The remaining 4 GPIO lines can not be used for receiving
interrupts.

The interrupt parent of this GPIO controller must be the
IXP4xx interrupt controller.

Required properties:

- compatible : Should be
  "intel,ixp4xx-gpio"
- reg : Should contain registers location and length
- gpio-controller : marks this as a GPIO controller
- #gpio-cells : Should be 2, see gpio/gpio.txt
- interrupt-controller : marks this as an interrupt controller
- #interrupt-cells : a standard two-cell interrupt, see
  interrupt-controller/interrupts.txt

Example:

gpio0: gpio@c8004000 {
	compatible = "intel,ixp4xx-gpio";
	reg = <0xc8004000 0x1000>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/kontron,sl28cpld-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: GPIO driver for the sl28cpld board management controller

maintainers:
  - Michael Walle <michael@walle.cc>

description: |
  This module is part of the sl28cpld multi-function device. For more
  details see ../mfd/kontron,sl28cpld.yaml.

  There are three flavors of the GPIO controller, one full featured
  input/output with interrupt support (kontron,sl28cpld-gpio), one
  output-only (kontron,sl28-gpo) and one input-only (kontron,sl28-gpi).

  Each controller supports 8 GPIO lines.

properties:
  compatible:
    enum:
      - kontron,sl28cpld-gpio
      - kontron,sl28cpld-gpi
      - kontron,sl28cpld-gpo

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#interrupt-cells":
    const: 2

  interrupt-controller: true

  "#gpio-cells":
    const: 2

  gpio-controller: true

  gpio-line-names:
    minItems: 1
    maxItems: 8

required:
  - compatible
  - "#gpio-cells"
  - gpio-controller

additionalProperties: false


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/mediatek,mt7621-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT7621 SoC GPIO controller

maintainers:
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

description: |
  The IP core used inside these SoCs has 3 banks of 32 GPIOs each.
  The registers of all the banks are interwoven inside one single IO range.
  We load one GPIO controller instance per bank. Also the GPIO controller can receive
  interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU
  using GIC INT12.

properties:
  $nodename:
    pattern: "^gpio@[0-9a-f]+$"

  compatible:
    const: mediatek,mt7621-gpio

  reg:
    maxItems: 1

  "#gpio-cells":
    const: 2

  gpio-controller: true
  gpio-ranges: true

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - "#gpio-cells"
  - gpio-controller
  - gpio-ranges
  - interrupt-controller
  - "#interrupt-cells"
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/mips-gic.h>

    gpio@600 {
      compatible = "mediatek,mt7621-gpio";
      reg = <0x600 0x100>;
      #gpio-cells = <2>;
      gpio-controller;
      gpio-ranges = <&pinctrl 0 0 95>;
      interrupt-controller;
      #interrupt-cells = <2>;
      interrupt-parent = <&gic>;
      interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip MPFS GPIO Controller

maintainers:
  - Conor Dooley <conor.dooley@microchip.com>

properties:
  compatible:
    items:
      - enum:
          - microchip,mpfs-gpio

  reg:
    maxItems: 1

  interrupts:
    description:
      Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
    minItems: 1
    maxItems: 32

  interrupt-controller: true

  clocks:
    maxItems: 1

  "#gpio-cells":
    const: 2

  "#interrupt-cells":
    const: 1

  ngpios:
    description:
      The number of GPIOs available.
    minimum: 1
    maximum: 32
    default: 32

  gpio-controller: true

patternProperties:
  "^.+-hog(-[0-9]+)?$":
    type: object

    additionalProperties: false

    properties:
      gpio-hog: true
      gpios: true
      input: true
      output-high: true
      output-low: true
      line-name: true

    required:
      - gpio-hog
      - gpios

required:
  - compatible
  - reg
  - interrupts
  - "#interrupt-cells"
  - interrupt-controller
  - "#gpio-cells"
  - gpio-controller
  - clocks

additionalProperties: false

examples:
  - |
    gpio@20122000 {
        compatible = "microchip,mpfs-gpio";
        reg = <0x20122000 0x1000>;
        clocks = <&clkcfg 25>;
        interrupt-parent = <&plic>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <1>;
        interrupts = <53>, <53>, <53>, <53>,
                     <53>, <53>, <53>, <53>,
                     <53>, <53>, <53>, <53>,
                     <53>, <53>, <53>, <53>,
                     <53>, <53>, <53>, <53>,
                     <53>, <53>, <53>, <53>,
                     <53>, <53>, <53>, <53>,
                     <53>, <53>, <53>, <53>;
    };
...


code:
* Microchip PIC32 GPIO devices (PIO).

Required properties:
 - compatible: "microchip,pic32mzda-gpio"
 - reg: Base address and length for the device.
 - interrupts: The port interrupt shared by all pins.
 - gpio-controller: Marks the port as GPIO controller.
 - #gpio-cells: Two. The first cell is the pin number and
   the second cell is used to specify the gpio polarity as defined in
   defined in <dt-bindings/gpio/gpio.h>:
      0 = GPIO_ACTIVE_HIGH
      1 = GPIO_ACTIVE_LOW
      2 = GPIO_OPEN_DRAIN
 - interrupt-controller: Marks the device node as an interrupt controller.
 - #interrupt-cells: Two. The first cell is the GPIO number and second cell
   is used to specify the trigger type as defined in
   <dt-bindings/interrupt-controller/irq.h>:
      IRQ_TYPE_EDGE_RISING
      IRQ_TYPE_EDGE_FALLING
      IRQ_TYPE_EDGE_BOTH
 - clocks: Clock specifier (see clock bindings for details).
 - microchip,gpio-bank: Specifies which bank a controller owns.
 - gpio-ranges: Interaction with the PINCTRL subsystem.

Example:

/* PORTA */
gpio0: gpio0@1f860000 {
	compatible = "microchip,pic32mzda-gpio";
	reg = <0x1f860000 0x100>;
	interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	clocks = <&rootclk PB4CLK>;
	microchip,gpio-bank = <0>;
	gpio-ranges = <&pic32_pinctrl 0 0 16>;
};

keys {
	...

	button@sw1 {
		label = "ESC";
		linux,code = <1>;
		gpios = <&gpio0 12 0>;
	};
};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/mrvl-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell PXA GPIO controller

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>
  - Bartosz Golaszewski <bgolaszewski@baylibre.com>
  - Rob Herring <robh+dt@kernel.org>

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - intel,pxa25x-gpio
              - intel,pxa26x-gpio
              - intel,pxa27x-gpio
              - intel,pxa3xx-gpio
    then:
      properties:
        interrupts:
          minItems: 3
          maxItems: 3
        interrupt-names:
          items:
            - const: gpio0
            - const: gpio1
            - const: gpio_mux
  - if:
      properties:
        compatible:
          contains:
            enum:
              - marvell,mmp-gpio
              - marvell,mmp2-gpio
    then:
      properties:
        interrupts:
          maxItems: 1
        interrupt-names:
          items:
            - const: gpio_mux

properties:
  $nodename:
    pattern: '^gpio@[0-9a-f]+$'

  compatible:
    enum:
      - intel,pxa25x-gpio
      - intel,pxa26x-gpio
      - intel,pxa27x-gpio
      - intel,pxa3xx-gpio
      - marvell,mmp-gpio
      - marvell,mmp2-gpio
      - marvell,pxa93x-gpio

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  ranges: true

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2

  gpio-ranges: true

  interrupts: true

  interrupt-names: true

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

patternProperties:
  '^gpio@[0-9a-f]*$':
    type: object
    properties:
      reg:
        maxItems: 1

    required:
      - reg

    additionalProperties: false

required:
  - compatible
  - '#address-cells'
  - '#size-cells'
  - reg
  - gpio-controller
  - '#gpio-cells'
  - interrupts
  - interrupt-names
  - interrupt-controller
  - '#interrupt-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/pxa-clock.h>
    gpio@40e00000 {
        compatible = "intel,pxa3xx-gpio";
        #address-cells = <1>;
        #size-cells = <1>;
        reg = <0x40e00000 0x10000>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupts = <8>, <9>, <10>;
        interrupt-names = "gpio0", "gpio1", "gpio_mux";
        clocks = <&clks CLK_GPIO>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };
  - |
    #include <dt-bindings/clock/marvell,pxa910.h>
    gpio@d4019000 {
        compatible = "marvell,mmp-gpio";
        #address-cells = <1>;
        #size-cells = <1>;
        reg = <0xd4019000 0x1000>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupts = <49>;
        interrupt-names = "gpio_mux";
        clocks = <&soc_clocks PXA910_CLK_GPIO>;
        resets = <&soc_clocks PXA910_CLK_GPIO>;
        interrupt-controller;
        #interrupt-cells = <2>;
        ranges;

        gpio@d4019000 {
            reg = <0xd4019000 0x4>;
        };

        gpio@d4019004 {
            reg = <0xd4019004 0x4>;
        };

        gpio@d4019008 {
            reg = <0xd4019008 0x4>;
        };

        gpio@d4019100 {
            reg = <0xd4019100 0x4>;
        };
     };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/mstar,msc313-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MStar/SigmaStar GPIO controller

maintainers:
  - Daniel Palmer <daniel@thingy.jp>

properties:
  $nodename:
    pattern: "^gpio@[0-9a-f]+$"

  compatible:
    enum:
      - mstar,msc313-gpio
      - sstar,ssd20xd-gpio

  reg:
    maxItems: 1

  gpio-controller: true

  "#gpio-cells":
    const: 2

  gpio-ranges: true

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"
  - interrupt-controller
  - "#interrupt-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/msc313-gpio.h>

    gpio: gpio@207800 {
      compatible = "mstar,msc313-gpio";
      #gpio-cells = <2>;
      reg = <0x207800 0x200>;
      gpio-controller;
      gpio-ranges = <&pinctrl 0 36 22>,
                    <&pinctrl 22 63 4>,
                    <&pinctrl 26 68 6>;
      #interrupt-cells = <2>;
      interrupt-controller;
      interrupt-parent = <&intc_fiq>;
    };


code:
Binding for the GPIO extension bus found on some LaCie/Seagate boards
(Example: 2Big/5Big Network v2, 2Big NAS).

Required properties:
- compatible: "lacie,netxbig-gpio-ext".
- addr-gpios: GPIOs representing the address register (LSB -> MSB).
- data-gpios: GPIOs representing the data register (LSB -> MSB).
- enable-gpio: latches the new configuration (address, data) on raising edge.

Example:

netxbig_gpio_ext: netxbig-gpio-ext {
	compatible = "lacie,netxbig-gpio-ext";

	addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH
		      &gpio1 16 GPIO_ACTIVE_HIGH
		      &gpio1 17 GPIO_ACTIVE_HIGH>;
	data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH
		      &gpio1 13 GPIO_ACTIVE_HIGH
		      &gpio1 14 GPIO_ACTIVE_HIGH>;
	enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
};


code:
Bindings for the National Instruments 169445 GPIO NAND controller

The 169445 GPIO NAND controller has two memory mapped GPIO registers, one
for input (the ready signal) and one for output (control signals).  It is
intended to be used with the GPIO NAND driver.

Required properties:
	- compatible: should be "ni,169445-nand-gpio"
	- reg-names: must contain
		"dat" - data register
	- reg: address + size pairs describing the GPIO register sets;
		order must correspond with the order of entries in reg-names
	- #gpio-cells: must be set to 2. The first cell is the pin number and
			the second cell is used to specify the gpio polarity:
			0 = active high
			1 = active low
	- gpio-controller: Marks the device node as a gpio controller.

Optional properties:
	- no-output: disables driving output on the pins

Examples:
	gpio1: nand-gpio-out@1f300010 {
		compatible = "ni,169445-nand-gpio";
		reg = <0x1f300010 0x4>;
		reg-names = "dat";
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpio2: nand-gpio-in@1f300014 {
		compatible = "ni,169445-nand-gpio";
		reg = <0x1f300014 0x4>;
		reg-names = "dat";
		gpio-controller;
		#gpio-cells = <2>;
		no-output;
	};


code:
Nintendo Wii (Hollywood) GPIO controller

Required properties:
- compatible: "nintendo,hollywood-gpio"
- reg: Physical base address and length of the controller's registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be <2>. The first cell is the pin number and the
  second cell is used to specify optional parameters:
   - bit 0 specifies polarity (0 for normal, 1 for inverted).

Optional properties:
- ngpios: see Documentation/devicetree/bindings/gpio/gpio.txt
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- interrupts: Interrupt specifier for the controller's Broadway (PowerPC)
  interrupt.

Example:

	GPIO: gpio@d8000c0 {
		#gpio-cells = <2>;
		compatible = "nintendo,hollywood-gpio";
		reg = <0x0d8000c0 0x40>;
		gpio-controller;
		ngpios = <24>;
	}


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra GPIO Controller (Tegra186 and later)

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: |
  Tegra186 contains two GPIO controllers; a main controller and an "AON"
  controller. This binding document applies to both controllers. The register
  layouts for the controllers share many similarities, but also some
  significant differences. Hence, this document describes closely related but
  different bindings and compatible values.

  The Tegra186 GPIO controller allows software to set the IO direction of,
  and read/write the value of, numerous GPIO signals. Routing of GPIO signals
  to package balls is under the control of a separate pin controller hardware
  block. Two major sets of registers exist:

    a) Security registers, which allow configuration of allowed access to the
       GPIO register set. These registers exist in a single contiguous block
       of physical address space. The size of this block, and the security
       features available, varies between the different GPIO controllers.

       Access to this set of registers is not necessary in all circumstances.
       Code that wishes to configure access to the GPIO registers needs access
       to these registers to do so. Code which simply wishes to read or write
       GPIO data does not need access to these registers.

    b) GPIO registers, which allow manipulation of the GPIO signals. In some
       GPIO controllers, these registers are exposed via multiple "physical
       aliases" in address space, each of which access the same underlying
       state. See the hardware documentation for rationale. Any particular
       GPIO client is expected to access just one of these physical aliases.

    Tegra HW documentation describes a unified naming convention for all GPIOs
    implemented by the SoC. Each GPIO is assigned to a port, and a port may
    control a number of GPIOs. Thus, each GPIO is named according to an
    alphabetical port name and an integer GPIO name within the port. For
    example, GPIO_PA0, GPIO_PN6, or GPIO_PCC3.

    The number of ports implemented by each GPIO controller varies. The number
    of implemented GPIOs within each port varies. GPIO registers within a
    controller are grouped and laid out according to the port they affect.

    The mapping from port name to the GPIO controller that implements that
    port, and the mapping from port name to register offset within a
    controller, are both extremely non-linear. The header file
    <dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In
    that file, the naming convention for ports matches the HW documentation.
    The values chosen for the names are alphabetically sorted within a
    particular controller. Drivers need to map between the DT GPIO IDs and HW
    register offsets using a lookup table.

    Each GPIO controller can generate a number of interrupt signals. Each
    signal represents the aggregate status for all GPIOs within a set of
    ports. Thus, the number of interrupt signals generated by a controller
    varies as a rough function of the number of ports it implements. Note
    that the HW documentation refers to both the overall controller HW
    module and the sets-of-ports as "controllers".

    Each GPIO controller in fact generates multiple interrupts signals for
    each set of ports. Each GPIO may be configured to feed into a specific
    one of the interrupt signals generated by a set-of-ports. The intent is
    for each generated signal to be routed to a different CPU, thus allowing
    different CPUs to each handle subsets of the interrupts within a port.
    The status of each of these per-port-set signals is reported via a
    separate register. Thus, a driver needs to know which status register to
    observe. This binding currently defines no configuration mechanism for
    this. By default, drivers should use register
    GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
    define a property to configure this.

properties:
  compatible:
    enum:
      - nvidia,tegra186-gpio
      - nvidia,tegra186-gpio-aon
      - nvidia,tegra194-gpio
      - nvidia,tegra194-gpio-aon
      - nvidia,tegra234-gpio
      - nvidia,tegra234-gpio-aon

  reg-names:
    items:
      - const: security
      - const: gpio
    minItems: 1

  reg:
    items:
      - description: Security configuration registers.
      - description: |
          GPIO control registers. This may cover either:

            a) The single physical alias that this OS should use.
            b) All physical aliases that exist in the controller. This is
               appropriate when the OS is responsible for managing assignment
               of the physical aliases.
    minItems: 1

  interrupts:
    description: The interrupt outputs from the HW block, one per set of
      ports, in the order the HW manual describes them. The number of entries
      required varies depending on compatible value.

  gpio-controller: true

  "#gpio-cells":
    description: |
      Indicates how many cells are used in a consumer's GPIO specifier. In the
      specifier:

        - The first cell is the pin number.
          See <dt-bindings/gpio/tegra186-gpio.h>.
        - The second cell contains flags:
          - Bit 0 specifies polarity
            - 0: Active-high (normal).
            - 1: Active-low (inverted).
    const: 2

  interrupt-controller: true

  "#interrupt-cells":
    description: |
      Indicates how many cells are used in a consumer's interrupt specifier.
      In the specifier:

        - The first cell is the GPIO number.
          See <dt-bindings/gpio/tegra186-gpio.h>.
        - The second cell is contains flags:
          - Bits [3:0] indicate trigger type and level:
            - 1: Low-to-high edge triggered.
            - 2: High-to-low edge triggered.
            - 4: Active high level-sensitive.
            - 8: Active low level-sensitive.

            Valid combinations are 1, 2, 3, 4, 8.
    const: 2

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra186-gpio
              - nvidia,tegra194-gpio
              - nvidia,tegra234-gpio
    then:
      properties:
        interrupts:
          minItems: 6
          maxItems: 48

  - if:
      properties:
        compatible:
          contains:
            enum:
              - nvidia,tegra186-gpio-aon
              - nvidia,tegra194-gpio-aon
              - nvidia,tegra234-gpio-aon
    then:
      properties:
        interrupts:
          minItems: 1
          maxItems: 4

required:
  - compatible
  - reg
  - reg-names
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    gpio@2200000 {
        compatible = "nvidia,tegra186-gpio";
        reg-names = "security", "gpio";
        reg = <0x2200000 0x10000>,
              <0x2210000 0x10000>;
        interrupts = <0  47 IRQ_TYPE_LEVEL_HIGH>,
                     <0  50 IRQ_TYPE_LEVEL_HIGH>,
                     <0  53 IRQ_TYPE_LEVEL_HIGH>,
                     <0  56 IRQ_TYPE_LEVEL_HIGH>,
                     <0  59 IRQ_TYPE_LEVEL_HIGH>,
                     <0 180 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };

    gpio@c2f0000 {
        compatible = "nvidia,tegra186-gpio-aon";
        reg-names = "security", "gpio";
        reg = <0xc2f0000 0x1000>,
              <0xc2f1000 0x1000>;
        interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    oneOf:
      - enum:
          - nvidia,tegra20-gpio
          - nvidia,tegra30-gpio

      - items:
          - enum:
              - nvidia,tegra114-gpio
              - nvidia,tegra124-gpio
              - nvidia,tegra210-gpio
          - const: nvidia,tegra30-gpio

  reg:
    maxItems: 1

  interrupts:
    description: The interrupt outputs from the controller. For Tegra20,
      there should be 7 interrupts specified, and for Tegra30, there should
      be 8 interrupts specified.

  "#gpio-cells":
    description: The first cell is the pin number and the second cell is used
      to specify the GPIO polarity (0 = active high, 1 = active low).
    const: 2

  gpio-controller: true

  gpio-ranges:
    maxItems: 1

  "#interrupt-cells":
    description: |
      Should be 2. The first cell is the GPIO number. The second cell is
      used to specify flags:

        bits[3:0] trigger type and level flags:
          1 = low-to-high edge triggered.
          2 = high-to-low edge triggered.
          4 = active high level-sensitive.
          8 = active low level-sensitive.

      Valid combinations are 1, 2, 3, 4, 8.
    const: 2

  interrupt-controller: true

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra30-gpio
    then:
      properties:
        interrupts:
          minItems: 8
          maxItems: 8
    else:
      properties:
        interrupts:
          minItems: 7
          maxItems: 7

required:
  - compatible
  - reg
  - interrupts
  - "#gpio-cells"
  - gpio-controller
  - "#interrupt-cells"
  - interrupt-controller

additionalProperties:
  type: object
  required:
    - gpio-hog

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gpio: gpio@6000d000 {
        compatible = "nvidia,tegra20-gpio";
        reg = <0x6000d000 0x1000>;
        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
        #gpio-cells = <2>;
        gpio-controller;
        #interrupt-cells = <2>;
        interrupt-controller;
    };


code:
NXP LPC18xx/43xx GPIO controller Device Tree Bindings
-----------------------------------------------------

Required properties:
- compatible		: Should be "nxp,lpc1850-gpio"
- reg			: List of addresses and lengths of the GPIO controller
			  register sets
- reg-names		: Should be "gpio", "gpio-pin-ic", "gpio-group0-ic" and
			  "gpio-gpoup1-ic"
- clocks		: Phandle and clock specifier pair for GPIO controller
- resets		: Phandle and reset specifier pair for GPIO controller
- gpio-controller	: Marks the device node as a GPIO controller
- #gpio-cells 		: Should be two:
			  - The first cell is the GPIO line number
			  - The second cell is used to specify polarity
- interrupt-controller	: Marks the device node as an interrupt controller
- #interrupt-cells	: Should be two:
			  - The first cell is an interrupt number within
			    0..9 range, for GPIO pin interrupts it is equal
			    to 'nxp,gpio-pin-interrupt' property value of
			    GPIO pin configuration, 8 is for GPIO GROUP0
			    interrupt, 9 is for GPIO GROUP1 interrupt
			  - The second cell is used to specify interrupt type

Optional properties:
- gpio-ranges		: Mapping between GPIO and pinctrl

Example:
#define LPC_GPIO(port, pin)	(port * 32 + pin)
#define LPC_PIN(port, pin)	(0x##port * 32 + pin)

gpio: gpio@400f4000 {
	compatible = "nxp,lpc1850-gpio";
	reg = <0x400f4000 0x4000>, <0x40087000 0x1000>,
	      <0x40088000 0x1000>, <0x40089000 0x1000>;
	reg-names = "gpio", "gpio-pin-ic",
		    "gpio-group0-ic", "gpio-gpoup1-ic";
	clocks = <&ccu1 CLK_CPU_GPIO>;
	resets = <&rgu 28>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges =	<&pinctrl LPC_GPIO(0,0)  LPC_PIN(0,0)  2>,
			...
			<&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5)  7>;
};

gpio_joystick {
	compatible = "gpio-keys";
	...

	button0 {
		...
		interrupt-parent = <&gpio>;
		interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
		gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/nxp,pcf8575.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PCF857x-compatible I/O expanders

maintainers:
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

description:
  The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
  driven high by a pull-up current source or driven low to ground. This
  combines the direction and output level into a single bit per line, which
  can't be read back. We can't actually know at initialization time whether a
  line is configured (a) as output and driving the signal low/high, or (b) as
  input and reporting a low/high value, without knowing the last value written
  since the chip came out of reset (if any). The only reliable solution for
  setting up line direction is thus to do it explicitly.

properties:
  compatible:
    enum:
      - maxim,max7328
      - maxim,max7329
      - nxp,pca8574
      - nxp,pca8575
      - nxp,pca9670
      - nxp,pca9671
      - nxp,pca9672
      - nxp,pca9673
      - nxp,pca9674
      - nxp,pca9675
      - nxp,pcf8574
      - nxp,pcf8574a
      - nxp,pcf8575

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2
    description:
      The first cell is the GPIO number and the second cell specifies GPIO
      flags, as defined in <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
      and GPIO_ACTIVE_LOW flags are supported.

  lines-initial-states:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Bitmask that specifies the initial state of each line.
      When a bit is set to zero, the corresponding line will be initialized to
      the input (pulled-up) state.
      When the  bit is set to one, the line will be initialized to the
      low-level output state.
      If the property is not specified all lines will be initialized to the
      input state.

  interrupts:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  wakeup-source: true

patternProperties:
  "^(.+-hog(-[0-9]+)?)$":
    type: object

    required:
      - gpio-hog

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'

additionalProperties: false

examples:
  - |
    i2c {
            #address-cells = <1>;
            #size-cells = <0>;

            pcf8575: gpio@20 {
                    compatible = "nxp,pcf8575";
                    reg = <0x20>;
                    interrupt-parent = <&irqpin2>;
                    interrupts = <3 0>;
                    gpio-controller;
                    #gpio-cells = <2>;
                    interrupt-controller;
                    #interrupt-cells = <2>;
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/pl061-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM PL061 GPIO controller

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>
  - Rob Herring <robh@kernel.org>

# We need a select here so we don't match all nodes with 'arm,primecell'
select:
  properties:
    compatible:
      contains:
        const: arm,pl061
  required:
    - compatible

properties:
  $nodename:
    pattern: "^gpio@[0-9a-f]+$"

  compatible:
    items:
      - const: arm,pl061
      - const: arm,primecell

  reg:
    maxItems: 1

  interrupts:
    oneOf:
      - maxItems: 1
      - maxItems: 8

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  clocks:
    maxItems: 1

  clock-names: true

  "#gpio-cells":
    const: 2

  gpio-controller: true

  gpio-line-names: true

  gpio-ranges:
    minItems: 1
    maxItems: 8

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - "#interrupt-cells"
  - clocks
  - "#gpio-cells"
  - gpio-controller

additionalProperties: false

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/qcom,wcd934x-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: WCD9340/WCD9341 GPIO controller

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description: |
  Qualcomm Technologies Inc WCD9340/WCD9341 Audio Codec has integrated
  gpio controller to control 5 gpios on the chip.

properties:
  compatible:
    enum:
      - qcom,wcd9340-gpio
      - qcom,wcd9341-gpio

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"

additionalProperties: false

examples:
  - |
    wcdgpio: gpio@42 {
        compatible = "qcom,wcd9340-gpio";
        reg = <0x042 0x2>;
        gpio-controller;
        #gpio-cells = <2>;
    };

...


code:
Raspberry Pi GPIO expander

The Raspberry Pi 3 GPIO expander is controlled by the VC4 firmware. The
firmware exposes a mailbox interface that allows the ARM core to control the
GPIO lines on the expander.

The Raspberry Pi GPIO expander node must be a child node of the Raspberry Pi
firmware node.

Required properties:

- compatible : Should be "raspberrypi,firmware-gpio"
- gpio-controller : Marks the device node as a gpio controller
- #gpio-cells : Should be two.  The first cell is the pin number, and
  the second cell is used to specify the gpio polarity:
  0 = active high
  1 = active low

Example:

firmware: firmware-rpi {
	compatible = "raspberrypi,bcm2835-firmware";
	mboxes = <&mailbox>;

	expgpio: gpio {
		 compatible = "raspberrypi,firmware-gpio";
		 gpio-controller;
		 #gpio-cells = <2>;
	 };
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/realtek,otto-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Realtek Otto GPIO controller

maintainers:
  - Sander Vanheule <sander@svanheule.net>
  - Bert Vermeulen <bert@biot.com>

description: |
  Realtek's GPIO controller on their MIPS switch SoCs (Otto platform) consists
  of two banks of 32 GPIOs. These GPIOs can generate edge-triggered interrupts.
  Each bank's interrupts are cascased into one interrupt line on the parent
  interrupt controller, if provided.
  This binding allows defining a single bank in the devicetree. The interrupt
  controller is not supported on the fallback compatible name, which only
  allows for GPIO port use.

properties:
  $nodename:
    pattern: "^gpio@[0-9a-f]+$"

  compatible:
    items:
      - enum:
          - realtek,rtl8380-gpio
          - realtek,rtl8390-gpio
          - realtek,rtl9300-gpio
          - realtek,rtl9310-gpio
      - const: realtek,otto-gpio

  reg: true

  "#gpio-cells":
    const: 2

  gpio-controller: true

  ngpios:
    minimum: 1
    maximum: 32

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  interrupts:
    maxItems: 1

if:
  properties:
    compatible:
      contains:
        const: realtek,rtl9300-gpio
then:
  properties:
    reg:
      items:
        - description: GPIO and interrupt control
        - description: interrupt CPU map
else:
  properties:
    reg:
      items:
        - description: GPIO and interrupt control

required:
  - compatible
  - reg
  - "#gpio-cells"
  - gpio-controller

additionalProperties: false

dependencies:
  interrupt-controller: [ interrupts ]

examples:
  - |
      gpio@3500 {
        compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
        reg = <0x3500 0x1c>;
        gpio-controller;
        #gpio-cells = <2>;
        ngpios = <24>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupt-parent = <&rtlintc>;
        interrupts = <23>;
      };
  - |
      gpio@3300 {
        compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio";
        reg = <0x3300 0x1c>, <0x3338 0x8>;
        gpio-controller;
        #gpio-cells = <2>;
        ngpios = <24>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupt-parent = <&rtlintc>;
        interrupts = <13>;
      };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/renesas,em-gio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas EMMA Mobile General Purpose I/O Interface

maintainers:
  - Magnus Damm <magnus.damm@gmail.com>

properties:
  compatible:
    const: renesas,em-gio

  reg:
    items:
      - description: First set of contiguous registers
      - description: Second set of contiguous registers

  interrupts:
    items:
      - description: Interrupt for the first set of 16 GPIO ports
      - description: Interrupt for the second set of 16 GPIO ports

  gpio-controller: true

  '#gpio-cells':
    const: 2

  gpio-ranges:
    maxItems: 1

  ngpios:
    minimum: 1
    maximum: 32

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

required:
  - compatible
  - reg
  - interrupts
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges
  - ngpios
  - interrupt-controller
  - '#interrupt-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    gpio0: gpio@e0050000 {
            compatible = "renesas,em-gio";
            reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
            interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
            gpio-controller;
            #gpio-cells = <2>;
            gpio-ranges = <&pfc 0 0 32>;
            ngpios = <32>;
            interrupt-controller;
            #interrupt-cells = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/renesas,rcar-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car General-Purpose Input/Output Ports (GPIO)

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,gpio-r8a7778      # R-Car M1
              - renesas,gpio-r8a7779      # R-Car H1
          - const: renesas,rcar-gen1-gpio # R-Car Gen1

      - items:
          - enum:
              - renesas,gpio-r8a7742      # RZ/G1H
              - renesas,gpio-r8a7743      # RZ/G1M
              - renesas,gpio-r8a7744      # RZ/G1N
              - renesas,gpio-r8a7745      # RZ/G1E
              - renesas,gpio-r8a77470     # RZ/G1C
              - renesas,gpio-r8a7790      # R-Car H2
              - renesas,gpio-r8a7791      # R-Car M2-W
              - renesas,gpio-r8a7792      # R-Car V2H
              - renesas,gpio-r8a7793      # R-Car M2-N
              - renesas,gpio-r8a7794      # R-Car E2
          - const: renesas,rcar-gen2-gpio # R-Car Gen2 or RZ/G1

      - items:
          - enum:
              - renesas,gpio-r8a774a1     # RZ/G2M
              - renesas,gpio-r8a774b1     # RZ/G2N
              - renesas,gpio-r8a774c0     # RZ/G2E
              - renesas,gpio-r8a774e1     # RZ/G2H
              - renesas,gpio-r8a7795      # R-Car H3
              - renesas,gpio-r8a7796      # R-Car M3-W
              - renesas,gpio-r8a77961     # R-Car M3-W+
              - renesas,gpio-r8a77965     # R-Car M3-N
              - renesas,gpio-r8a77970     # R-Car V3M
              - renesas,gpio-r8a77980     # R-Car V3H
              - renesas,gpio-r8a77990     # R-Car E3
              - renesas,gpio-r8a77995     # R-Car D3
          - const: renesas,rcar-gen3-gpio # R-Car Gen3 or RZ/G2

      - items:
          - enum:
              - renesas,gpio-r8a779a0     # R-Car V3U
              - renesas,gpio-r8a779f0     # R-Car S4-8
              - renesas,gpio-r8a779g0     # R-Car V4H
          - const: renesas,rcar-gen4-gpio # R-Car Gen4

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  gpio-ranges:
    maxItems: 1

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 8

patternProperties:
  "^.*$":
    if:
      type: object
    then:
      properties:
        gpio-hog: true
        gpios: true
        input: true
        output-high: true
        output-low: true
        line-name: true

      required:
        - gpio-hog
        - gpios

      additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges
  - interrupt-controller
  - '#interrupt-cells'

if:
  not:
    properties:
      compatible:
        contains:
          enum:
            - renesas,rcar-gen1-gpio
then:
  required:
    - clocks
    - power-domains
    - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a77470-sysc.h>
    gpio3: gpio@e6053000 {
            compatible = "renesas,gpio-r8a77470", "renesas,rcar-gen2-gpio";
            reg = <0xe6053000 0x50>;
            interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 909>;
            power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
            resets = <&cpg 909>;
            gpio-controller;
            #gpio-cells = <2>;
            gpio-ranges = <&pfc 0 96 30>;
            gpio-reserved-ranges = <17 10>;
            interrupt-controller;
            #interrupt-cells = <2>;
     };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip GPIO bank

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    enum:
      - rockchip,gpio-bank
      - rockchip,rk3188-gpio-bank0

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: APB interface clock source
      - description: GPIO debounce reference clock source

  gpio-ranges: true

  gpio-controller: true

  gpio-line-names: true

  "#gpio-cells":
    const: 2

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - gpio-controller
  - "#gpio-cells"
  - interrupt-controller
  - "#interrupt-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl: pinctrl {
      #address-cells = <1>;
      #size-cells = <1>;
      ranges;

      gpio0: gpio@2000a000 {
        compatible = "rockchip,rk3188-gpio-bank0";
        reg = <0x2000a000 0x100>;
        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk_gates8 9>;

        gpio-controller;
        #gpio-cells = <2>;

        interrupt-controller;
        #interrupt-cells = <2>;
      };

      gpio1: gpio@2003c000 {
        compatible = "rockchip,gpio-bank";
        reg = <0x2003c000 0x100>;
        interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk_gates8 10>;

        gpio-controller;
        #gpio-cells = <2>;

        interrupt-controller;
        #interrupt-cells = <2>;
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/rockchip,rk3328-grf-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3328 General Register Files GPIO controller

description:
  The Rockchip RK3328 General Register File (GRF) outputs only the
  GPIO_MUTE pin, originally for codec mute control, but it can also be used
  for general purpose. It is manipulated by the GRF_SOC_CON10 register.
  If needed in the future support for the HDMI pins can also be added.
  The GPIO node should be declared as the child of the GRF node.

  The GPIO_MUTE pin is referred to in the format

  <&grf_gpio 0 GPIO_ACTIVE_LOW>

  The first cell is the pin number and
  the second cell is used to specify the GPIO polarity
    0 = Active high
    1 = Active low

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    const: rockchip,rk3328-grf-gpio

  gpio-controller: true

  "#gpio-cells":
    const: 2

required:
  - compatible
  - gpio-controller
  - "#gpio-cells"

additionalProperties: false

examples:
  - |
    grf_gpio: gpio {
      compatible = "rockchip,rk3328-grf-gpio";
      gpio-controller;
      #gpio-cells = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive GPIO controller

maintainers:
  - Paul Walmsley <paul.walmsley@sifive.com>

properties:
  compatible:
    items:
      - enum:
          - sifive,fu540-c000-gpio
          - sifive,fu740-c000-gpio
          - canaan,k210-gpiohs
      - const: sifive,gpio0

  reg:
    maxItems: 1

  interrupts:
    description:
      Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
    minItems: 1
    maxItems: 32

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  clocks:
    maxItems: 1

  "#gpio-cells":
    const: 2

  ngpios:
    description:
      The number of GPIOs available on the controller implementation.
      It is 16 for the SiFive SoCs and 32 for the Canaan K210.
    minimum: 1
    maximum: 32
    default: 16

  gpio-line-names:
    minItems: 1
    maxItems: 32

  gpio-controller: true

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - "#interrupt-cells"
  - "#gpio-cells"
  - gpio-controller

if:
  properties:
    compatible:
      contains:
        enum:
          - sifive,fu540-c000-gpio
          - sifive,fu740-c000-gpio
then:
  required:
    - clocks

additionalProperties: false

examples:
  - |
      #include <dt-bindings/clock/sifive-fu540-prci.h>
      gpio@10060000 {
        compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
        interrupt-parent = <&plic>;
        interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>,
                     <17>, <18>, <19>, <20>, <21>, <22>;
        reg = <0x10060000 0x1000>;
        clocks = <&tlclk FU540_PRCI_CLK_TLCLK>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
      };

...


code:
Synopsys GPIO via CREG (Control REGisters) driver

Required properties:
- compatible : "snps,creg-gpio-hsdk" or "snps,creg-gpio-axs10x".
- reg : Exactly one register range with length 0x4.
- #gpio-cells : Since the generic GPIO binding is used, the
  amount of cells must be specified as 2. The first cell is the
  pin number, the second cell is used to specify optional parameters:
  See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
- gpio-controller : Marks the device node as a GPIO controller.
- ngpios: Number of GPIO pins.

Example:

gpio: gpio@f00014b0 {
	compatible = "snps,creg-gpio-hsdk";
	reg = <0xf00014b0 0x4>;
	gpio-controller;
	#gpio-cells = <2>;
	ngpios = <2>;
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare APB GPIO controller

description: |
  Synopsys DesignWare GPIO controllers have a configurable number of ports,
  each of which are intended to be represented as child nodes with the generic
  GPIO-controller properties as desribed in this bindings file.

maintainers:
  - Hoan Tran <hoan@os.amperecomputing.com>
  - Serge Semin <fancer.lancer@gmail.com>

properties:
  $nodename:
    pattern: "^gpio@[0-9a-f]+$"

  compatible:
    const: snps,dw-apb-gpio

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: APB interface clock source
      - description: DW GPIO debounce reference clock source

  clock-names:
    minItems: 1
    items:
      - const: bus
      - const: db

  resets:
    maxItems: 1

patternProperties:
  "^gpio-(port|controller)@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: snps,dw-apb-gpio-port

      reg:
        maxItems: 1

      gpio-controller: true

      '#gpio-cells':
        const: 2

      ngpios:
        default: 32
        minimum: 1
        maximum: 32

      snps,nr-gpios:
        description: The number of GPIO pins exported by the port.
        deprecated: true
        $ref: /schemas/types.yaml#/definitions/uint32
        default: 32
        minimum: 1
        maximum: 32

      interrupts:
        description: |
          The interrupts to the parent controller raised when GPIOs generate
          the interrupts. If the controller provides one combined interrupt
          for all GPIOs, specify a single interrupt. If the controller provides
          one interrupt for each GPIO, provide a list of interrupts that
          correspond to each of the GPIO pins.
        minItems: 1
        maxItems: 32

      interrupt-controller: true

      '#interrupt-cells':
        const: 2

    required:
      - compatible
      - reg
      - gpio-controller
      - '#gpio-cells'

    dependencies:
      interrupt-controller: [ interrupts ]

    additionalProperties: false

additionalProperties: false

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"

examples:
  - |
    gpio: gpio@20000 {
      compatible = "snps,dw-apb-gpio";
      reg = <0x20000 0x1000>;
      #address-cells = <1>;
      #size-cells = <0>;

      porta: gpio-port@0 {
        compatible = "snps,dw-apb-gpio-port";
        reg = <0>;
        gpio-controller;
        #gpio-cells = <2>;
        snps,nr-gpios = <8>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupt-parent = <&vic1>;
        interrupts = <0>;
      };

      portb: gpio-port@1 {
        compatible = "snps,dw-apb-gpio-port";
        reg = <1>;
        gpio-controller;
        #gpio-cells = <2>;
        snps,nr-gpios = <8>;
      };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UniPhier GPIO controller

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

properties:
  $nodename:
    pattern: "^gpio@[0-9a-f]+$"

  compatible:
    const: socionext,uniphier-gpio

  reg:
    maxItems: 1

  gpio-controller: true

  "#gpio-cells":
    const: 2

  interrupt-controller: true

  "#interrupt-cells":
    description: |
      The first cell defines the interrupt number.
      The second cell bits[3:0] is used to specify trigger type as follows:
        1 = low-to-high edge triggered
        2 = high-to-low edge triggered
        4 = active high level-sensitive
        8 = active low level-sensitive
      Valid combinations are 1, 2, 3, 4, 8.
    const: 2

  ngpios:
    minimum: 0
    maximum: 512

  gpio-ranges: true

  gpio-ranges-group-names: true

  socionext,interrupt-ranges:
    description: |
      Specifies an interrupt number mapping between this GPIO controller and
      its interrupt parent, in the form of arbitrary number of
      <child-interrupt-base parent-interrupt-base length> triplets.
    $ref: /schemas/types.yaml#/definitions/uint32-matrix

patternProperties:
  "^.+-hog(-[0-9]+)?$":
    type: object
    properties:
      gpio-hog: true
      gpios: true
      input: true
      output-high: true
      output-low: true
      line-name: true

    required:
      - gpio-hog
      - gpios

    additionalProperties: false

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"
  - interrupt-controller
  - "#interrupt-cells"
  - ngpios
  - gpio-ranges
  - socionext,interrupt-ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/gpio/uniphier-gpio.h>

    gpio: gpio@55000000 {
        compatible = "socionext,uniphier-gpio";
        reg = <0x55000000 0x200>;
        interrupt-parent = <&aidet>;
        interrupt-controller;
        #interrupt-cells = <2>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&pinctrl 0 0 0>;
        gpio-ranges-group-names = "gpio_range";
        ngpios = <248>;
        socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>;
    };

    // Consumer:
    // Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC
    // document. Unfortunately, only the one's place is octal in the port
    // numbering. (That is, PORT 8, 9, 18, 19, 28, 29, ... do not exist.)
    // UNIPHIER_GPIO_PORT() is a helper macro to calculate 29 * 8 + 4.
    sdhci0_pwrseq {
        compatible = "mmc-pwrseq-emmc";
        reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>;
    };


code:
GPIO controller on CE4100 / Sodaville SoCs
==========================================

The bindings for CE4100's GPIO controller match the generic description
which is covered by the gpio.txt file in this folder.

The only additional property is the intel,muxctl property which holds the
value which is written into the MUXCNTL register.

There is no compatible property for now because the driver is probed via
PCI id (vendor 0x8086 device 0x2e67).

The interrupt specifier consists of two cells encoded as follows:
 - <1st cell>: The interrupt-number that identifies the interrupt source.
 - <2nd cell>: The level-sense information, encoded as follows:
		4 - active high level-sensitive
		8 - active low level-sensitive

Example of the GPIO device and one user:

	pcigpio: gpio@b,1 {
			/* two cells for GPIO and interrupt */
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			compatible = "pci8086,2e67.2",
					   "pci8086,2e67",
					   "pciclassff0000",
					   "pciclassff00";

			reg = <0x15900 0x0 0x0 0x0 0x0>;
			/* Interrupt line of the gpio device */
			interrupts = <15 1>;
			/* It is an interrupt and GPIO controller itself */
			interrupt-controller;
			gpio-controller;
			intel,muxctl = <0>;
	};

	testuser@20 {
			compatible = "example,testuser";
			/* User the 11th GPIO line as an active high triggered
			 * level interrupt
			 */
			interrupts = <11 8>;
			interrupt-parent = <&pcigpio>;
			/* Use this GPIO also with the gpio functions */
			gpios = <&pcigpio 11 0>;
	};


code:
=== ST Microelectronics SPEAr SPI CS Driver ===

SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
Cell spi controller through its system registers, which otherwise remains under
PL022 control. If chipselect remain under PL022 control then they would be
released as soon as transfer is over and TxFIFO becomes empty. This is not
desired by some of the device protocols above spi which expect (multiple)
transfers without releasing their chipselects.

Chipselects can be controlled by software by turning them as GPIOs. SPEAr
provides another interface through system registers through which software can
directly control each PL022 chipselect. Hence, it is natural for SPEAr to export
the control of this interface as gpio.

Required properties:

  * compatible: should be defined as "st,spear-spics-gpio"
  * reg: mentioning address range of spics controller
  * st-spics,peripcfg-reg: peripheral configuration register offset
  * st-spics,sw-enable-bit: bit offset to enable sw control
  * st-spics,cs-value-bit: bit offset to drive chipselect low or high
  * st-spics,cs-enable-mask: chip select number bit mask
  * st-spics,cs-enable-shift: chip select number program offset
  * gpio-controller: Marks the device node as gpio controller
  * #gpio-cells: should be 1 and will mention chip select number

All the above bit offsets are within peripcfg register.

Example:
-------
spics: spics@e0700000{
        compatible = "st,spear-spics-gpio";
        reg = <0xe0700000 0x1000>;
        st-spics,peripcfg-reg = <0x3b0>;
        st-spics,sw-enable-bit = <12>;
        st-spics,cs-value-bit = <11>;
        st-spics,cs-enable-mask = <3>;
        st-spics,cs-enable-shift = <8>;
        gpio-controller;
        #gpio-cells = <2>;
};

spi0: spi@e0100000 {
        num-cs = <3>;
        cs-gpios = <&gpio1 7 0>, <&spics 0>,
                   <&spics 1>;
	...
}


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/ti,omap-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: OMAP GPIO controller bindings

maintainers:
  - Grygorii Strashko <grygorii.strashko@ti.com>

description: |
  The general-purpose interface combines general-purpose input/output (GPIO) banks.
  Each GPIO banks provides up to 32 dedicated general-purpose pins with input
  and output capabilities; interrupt generation in active mode and wake-up
  request generation in idle mode upon the detection of external events.

properties:
  compatible:
    oneOf:
      - enum:
          - ti,omap2-gpio
          - ti,omap3-gpio
          - ti,omap4-gpio
      - items:
          - const: ti,am4372-gpio
          - const: ti,omap4-gpio

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  interrupts:
    maxItems: 1

  gpio-ranges: true

  gpio-line-names:
    minItems: 1
    maxItems: 32

  ti,gpio-always-on:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Indicates if a GPIO bank is always powered and will never lose its logic state.

  ti,hwmods:
    $ref: /schemas/types.yaml#/definitions/string
    deprecated: true
    description:
      Name of the hwmod associated with the GPIO. Needed on some legacy OMAP
      SoCs which have not been converted to the ti,sysc interconnect hierarachy.

  ti,no-reset-on-init:
    $ref: /schemas/types.yaml#/definitions/flag
    deprecated: true
    description:
      Do not reset on init. Used with ti,hwmods on some legacy OMAP SoCs which
      have not been converted to the ti,sysc interconnect hierarachy.

patternProperties:
  "^(.+-hog(-[0-9]+)?)$":
    type: object

    required:
      - gpio-hog

required:
  - compatible
  - reg
  - gpio-controller
  - "#gpio-cells"
  - interrupt-controller
  - "#interrupt-cells"
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    gpio0: gpio@0 {
        compatible = "ti,omap4-gpio";
        reg = <0x0 0x1000>;
        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <96>;
        ti,gpio-always-on;

        ls-buf-en-hog {
            gpio-hog;
            gpios = <10 GPIO_ACTIVE_HIGH>;
            output-high;
            line-name = "LS_BUF_EN";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/toshiba,gpio-visconti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Toshiba Visconti ARM SoCs GPIO controller

maintainers:
  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

properties:
  compatible:
    items:
      - const: toshiba,gpio-tmpv7708

  reg:
    maxItems: 1

  "#gpio-cells":
    const: 2

  gpio-ranges: true

  gpio-controller: true

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  interrupts:
    description:
      interrupt mapping one per GPIO.
    minItems: 16
    maxItems: 16

required:
  - compatible
  - reg
  - "#gpio-cells"
  - gpio-ranges
  - gpio-controller
  - interrupt-controller
  - "#interrupt-cells"

additionalProperties: false

examples:
  - |
      #include <dt-bindings/interrupt-controller/irq.h>
      #include <dt-bindings/interrupt-controller/arm-gic.h>

      soc {
        #address-cells = <2>;
        #size-cells = <2>;

        gpio: gpio@28020000 {
          compatible = "toshiba,gpio-tmpv7708";
          reg = <0 0x28020000 0 0x1000>;
          #gpio-cells = <0x2>;
          gpio-ranges = <&pmux 0 0 32>;
          gpio-controller;
          interrupt-controller;
          #interrupt-cells = <2>;
          interrupt-parent = <&gic>;
        };
      };
...


code:
Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers.

The Western Digital MyBook Live has two memory-mapped GPIO controllers.
Both GPIO controller only have a single 8-bit data register, where GPIO
state can be read and/or written.

Required properties:
	- compatible: should be "wd,mbl-gpio"
	- reg-names: must contain
		"dat" - data register
	- reg: address + size pairs describing the GPIO register sets;
		order must correspond with the order of entries in reg-names
	- #gpio-cells: must be set to 2. The first cell is the pin number and
			the second cell is used to specify the gpio polarity:
			0 = active high
			1 = active low
	- gpio-controller: Marks the device node as a gpio controller.

Optional properties:
	- no-output: GPIOs are read-only.

Examples:
	gpio0: gpio0@e0000000 {
		compatible = "wd,mbl-gpio";
		reg-names = "dat";
		reg = <0xe0000000 0x1>;
		#gpio-cells = <2>;
		gpio-controller;
	};

	gpio1: gpio1@e0100000 {
		compatible = "wd,mbl-gpio";
		reg-names = "dat";
		reg = <0xe0100000 0x1>;
		#gpio-cells = <2>;
		gpio-controller;
		no-output;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpio/x-powers,axp209-gpio.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: X-Powers AXP209 GPIO

maintainers:
  - Chen-Yu Tsai <wens@csie.org>

properties:
  "#gpio-cells":
    const: 2
    description: >
      The first cell is the pin number and the second is the GPIO flags.

  compatible:
    oneOf:
      - enum:
          - x-powers,axp209-gpio
          - x-powers,axp221-gpio
          - x-powers,axp813-gpio
      - items:
          - enum:
              - x-powers,axp223-gpio
              - x-powers,axp809-gpio
          - const: x-powers,axp221-gpio
      - items:
          - const: x-powers,axp803-gpio
          - const: x-powers,axp813-gpio

  gpio-controller: true

patternProperties:
  "^.*-pins?$":
    $ref: /schemas/pinctrl/pinmux-node.yaml#

    properties:
      pins:
        items:
          enum:
            - GPIO0
            - GPIO1
            - GPIO2

      function:
        enum:
          - adc
          - ldo
          - gpio_in
          - gpio_out

required:
  - compatible
  - "#gpio-cells"
  - gpio-controller

additionalProperties: false

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx AXI GPIO controller

maintainers:
  - Neeli Srinivas <srinivas.neeli@xilinx.com>

description:
  The AXI GPIO design provides a general purpose input/output interface
  to an AXI4-Lite interface. The AXI GPIO can be configured as either
  a single or a dual-channel device. The width of each channel is
  independently configurable. The channels can be configured to
  generate an interrupt when a transition on any of their inputs occurs.

properties:
  compatible:
    enum:
      - xlnx,xps-gpio-1.00.a

  reg:
    maxItems: 1

  "#gpio-cells":
    const: 2

  interrupts:
    maxItems: 1

  gpio-controller: true

  gpio-line-names:
    description: strings describing the names of each gpio line
    minItems: 1
    maxItems: 64

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  clocks:
    maxItems: 1

  interrupt-names: true

  xlnx,all-inputs:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: This option sets this GPIO channel1 bits in input mode.

  xlnx,all-inputs-2:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: This option sets this GPIO channel2 bits in input mode.

  xlnx,all-outputs:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: This option sets this GPIO channel1 bits in output mode.

  xlnx,all-outputs-2:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: This option sets this GPIO channel2 bits in output mode.

  xlnx,dout-default:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Sets the default value of all the enabled bits of
                 channel1.
    default: 0

  xlnx,dout-default-2:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Sets the default value of all the enabled bits of
                 channel2.
    default: 0

  xlnx,gpio-width:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The value defines the bit width of the GPIO channel1.
    minimum: 1
    maximum: 32
    default: 32

  xlnx,gpio2-width:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: The value defines the bit width of the GPIO channel2.
    minimum: 1
    maximum: 32
    default: 32

  xlnx,interrupt-present:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: This parameter enables interrupt control logic
                 and interrupt registers in GPIO module.
    minimum: 0
    maximum: 1
    default: 0

  xlnx,is-dual:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: This parameter enables a second GPIO channel (GPIO2).
    minimum: 0
    maximum: 1
    default: 0

  xlnx,tri-default:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: This value configures the input or output mode
                 of each bit of GPIO channel1.

  xlnx,tri-default-2:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: This value configures the input or output mode
                 of each bit of GPIO channel2.

required:
  - reg
  - compatible
  - gpio-controller
  - "#gpio-cells"

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

        gpio@e000a000 {
            compatible = "xlnx,xps-gpio-1.00.a";
            reg = <0xa0020000 0x10000>;
            #gpio-cells = <2>;
            #interrupt-cells = <0x2>;
            clocks = <&zynqmp_clk 71>;
            gpio-controller;
            interrupt-controller;
            interrupt-names = "ip2intc_irpt";
            interrupt-parent = <&gic>;
            interrupts = <0 89 4>;
            xlnx,all-inputs = <0x0>;
            xlnx,all-inputs-2 = <0x0>;
            xlnx,all-outputs = <0x0>;
            xlnx,all-outputs-2 = <0x0>;
            xlnx,dout-default = <0x0>;
            xlnx,dout-default-2 = <0x0>;
            xlnx,gpio-width = <0x20>;
            xlnx,gpio2-width = <0x20>;
            xlnx,interrupt-present = <0x1>;
            xlnx,is-dual = <0x1>;
            xlnx,tri-default = <0xFFFFFFFF>;
            xlnx,tri-default-2 = <0xFFFFFFFF>;
        };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: ZynqMP Mode Pin GPIO controller

description:
  PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
  GPIO controller with configurable from numbers of pins (from 0 to 3 per
  PS_MODE). Every pin can be configured as input/output.

maintainers:
  - Piyush Mehta <piyush.mehta@xilinx.com>

properties:
  compatible:
    const: xlnx,zynqmp-gpio-modepin

  gpio-controller: true

  "#gpio-cells":
    const: 2

required:
  - compatible
  - gpio-controller
  - "#gpio-cells"

additionalProperties: false

examples:
  - |
    zynqmp-firmware {
        gpio {
            compatible = "xlnx,zynqmp-gpio-modepin";
            gpio-controller;
            #gpio-cells = <2>;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Bootlin
%YAML 1.2
---
$id: "http://devicetree.org/schemas/gpio/xylon,logicvc-gpio.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Xylon LogiCVC GPIO controller

maintainers:
  - Paul Kocialkowski <paul.kocialkowski@bootlin.com>

description: |
  The LogiCVC GPIO describes the GPIO block included in the LogiCVC display
  controller. These are meant to be used for controlling display-related
  signals.

  The controller exposes GPIOs from the display and power control registers,
  which are mapped by the driver as follows:
  - GPIO[4:0] (display control) mapped to index 0-4
  - EN_BLIGHT (power control) mapped to index 5
  - EN_VDD (power control) mapped to index 6
  - EN_VEE (power control) mapped to index 7
  - V_EN (power control) mapped to index 8

properties:
  $nodename:
    pattern: "^gpio@[0-9a-f]+$"

  compatible:
    enum:
      - xylon,logicvc-3.02.a-gpio

  reg:
    maxItems: 1

  "#gpio-cells":
    const: 2

  gpio-controller: true

  gpio-line-names:
    minItems: 1
    maxItems: 9

required:
  - compatible
  - reg
  - "#gpio-cells"
  - gpio-controller

additionalProperties: false

examples:
  - |
    logicvc: logicvc@43c00000 {
      compatible = "xylon,logicvc-3.02.a", "syscon", "simple-mfd";
      reg = <0x43c00000 0x6000>;

      #address-cells = <1>;
      #size-cells = <1>;

      logicvc_gpio: gpio@40 {
        compatible = "xylon,logicvc-3.02.a-gpio";
        reg = <0x40 0x40>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-line-names = "GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO4",
               "EN_BLIGHT", "EN_VDD", "EN_VEE", "V_EN";
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Mali Bifrost GPU

maintainers:
  - Rob Herring <robh@kernel.org>

properties:
  $nodename:
    pattern: '^gpu@[a-f0-9]+$'

  compatible:
    oneOf:
      - items:
          - enum:
              - amlogic,meson-g12a-mali
              - mediatek,mt8183-mali
              - realtek,rtd1619-mali
              - renesas,r9a07g044-mali
              - renesas,r9a07g054-mali
              - rockchip,px30-mali
              - rockchip,rk3568-mali
          - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
      - items:
          - enum:
              - mediatek,mt8192-mali
          - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable

  reg:
    maxItems: 1

  interrupts:
    minItems: 3
    items:
      - description: Job interrupt
      - description: MMU interrupt
      - description: GPU interrupt
      - description: Event interrupt

  interrupt-names:
    minItems: 3
    items:
      - const: job
      - const: mmu
      - const: gpu
      - const: event

  clocks:
    minItems: 1
    maxItems: 3

  clock-names: true

  mali-supply: true

  sram-supply: true

  operating-points-v2: true

  power-domains:
    minItems: 1
    maxItems: 3

  resets:
    minItems: 1
    maxItems: 3

  reset-names: true

  "#cooling-cells":
    const: 2

  dynamic-power-coefficient:
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description:
      A u32 value that represents the running time dynamic
      power coefficient in units of uW/MHz/V^2. The
      coefficient can either be calculated from power
      measurements or derived by analysis.

      The dynamic power consumption of the GPU is
      proportional to the square of the Voltage (V) and
      the clock frequency (f). The coefficient is used to
      calculate the dynamic power as below -

      Pdyn = dynamic-power-coefficient * V^2 * f

      where voltage is in V, frequency is in MHz.

  dma-coherent: true

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: amlogic,meson-g12a-mali
    then:
      required:
        - resets
  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,r9a07g044-mali
              - renesas,r9a07g054-mali
    then:
      properties:
        interrupts:
          minItems: 4
        interrupt-names:
          minItems: 4
        clocks:
          minItems: 3
        clock-names:
          items:
            - const: gpu
            - const: bus
            - const: bus_ace
        resets:
          minItems: 3
        reset-names:
          items:
            - const: rst
            - const: axi_rst
            - const: ace_rst
      required:
        - clock-names
        - power-domains
        - resets
        - reset-names
  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt8183-mali
    then:
      properties:
        power-domains:
          minItems: 3
        power-domain-names:
          items:
            - const: core0
            - const: core1
            - const: core2

      required:
        - sram-supply
        - power-domains
        - power-domain-names
    else:
      properties:
        power-domains:
          maxItems: 1
        sram-supply: false
  - if:
      properties:
        compatible:
          contains:
            const: rockchip,rk3568-mali
    then:
      properties:
        clocks:
          minItems: 2
        clock-names:
          items:
            - const: gpu
            - const: bus
      required:
        - clock-names

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gpu@ffe40000 {
      compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
      reg = <0xffe40000 0x10000>;
      interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "job", "mmu", "gpu";
      clocks = <&clk 1>;
      mali-supply = <&vdd_gpu>;
      operating-points-v2 = <&gpu_opp_table>;
      resets = <&reset 0>, <&reset 1>;
    };

    gpu_opp_table: opp-table {
      compatible = "operating-points-v2";

      opp-533000000 {
        opp-hz = /bits/ 64 <533000000>;
        opp-microvolt = <1250000>;
      };
      opp-450000000 {
        opp-hz = /bits/ 64 <450000000>;
        opp-microvolt = <1150000>;
      };
      opp-400000000 {
        opp-hz = /bits/ 64 <400000000>;
        opp-microvolt = <1125000>;
      };
      opp-350000000 {
        opp-hz = /bits/ 64 <350000000>;
        opp-microvolt = <1075000>;
      };
      opp-266000000 {
        opp-hz = /bits/ 64 <266000000>;
        opp-microvolt = <1025000>;
      };
      opp-160000000 {
        opp-hz = /bits/ 64 <160000000>;
        opp-microvolt = <925000>;
      };
      opp-100000000 {
        opp-hz = /bits/ 64 <100000000>;
        opp-microvolt = <912500>;
      };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/arm,mali-midgard.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM Mali Midgard GPU

maintainers:
  - Rob Herring <robh@kernel.org>

properties:
  $nodename:
    pattern: '^gpu@[a-f0-9]+$'
  compatible:
    oneOf:
      - items:
          - enum:
              - samsung,exynos5250-mali
          - const: arm,mali-t604
      - items:
          - enum:
              - samsung,exynos5420-mali
          - const: arm,mali-t628
      - items:
          - enum:
              - allwinner,sun50i-h6-mali
          - const: arm,mali-t720
      - items:
          - enum:
              - amlogic,meson-gxm-mali
              - realtek,rtd1295-mali
          - const: arm,mali-t820
      - items:
          - enum:
              - arm,juno-mali
          - const: arm,mali-t624
      - items:
          - enum:
              - rockchip,rk3288-mali
              - samsung,exynos5433-mali
          - const: arm,mali-t760
      - items:
          - enum:
              - rockchip,rk3399-mali
          - const: arm,mali-t860

          # "arm,mali-t830"
          # "arm,mali-t880"

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: Job interrupt
      - description: MMU interrupt
      - description: GPU interrupt

  interrupt-names:
    items:
      - const: job
      - const: mmu
      - const: gpu

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: core
      - const: bus

  mali-supply: true
  opp-table:
    type: object

  power-domains:
    maxItems: 1

  resets:
    minItems: 1
    maxItems: 2

  operating-points-v2: true

  "#cooling-cells":
    const: 2

  dma-coherent: true

  dynamic-power-coefficient:
    $ref: '/schemas/types.yaml#/definitions/uint32'
    description:
      A u32 value that represents the running time dynamic
      power coefficient in units of uW/MHz/V^2. The
      coefficient can either be calculated from power
      measurements or derived by analysis.

      The dynamic power consumption of the GPU is
      proportional to the square of the Voltage (V) and
      the clock frequency (f). The coefficient is used to
      calculate the dynamic power as below -

      Pdyn = dynamic-power-coefficient * V^2 * f

      where voltage is in V, frequency is in MHz.

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: allwinner,sun50i-h6-mali
    then:
      properties:
        clocks:
          minItems: 2
      required:
        - clock-names
        - resets
  - if:
      properties:
        compatible:
          contains:
            const: amlogic,meson-gxm-mali
    then:
      properties:
        resets:
          minItems: 2
      required:
        - resets

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gpu@ffa30000 {
      compatible = "rockchip,rk3288-mali", "arm,mali-t760";
      reg = <0xffa30000 0x10000>;
      interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
             <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "job", "mmu", "gpu";
      clocks = <&cru 0>;
      mali-supply = <&vdd_gpu>;
      operating-points-v2 = <&gpu_opp_table>;
      power-domains = <&power 0>;
      #cooling-cells = <2>;
    };

    gpu_opp_table: opp-table {
      compatible = "operating-points-v2";

      opp-533000000 {
        opp-hz = /bits/ 64 <533000000>;
        opp-microvolt = <1250000>;
      };
      opp-450000000 {
        opp-hz = /bits/ 64 <450000000>;
        opp-microvolt = <1150000>;
      };
      opp-400000000 {
        opp-hz = /bits/ 64 <400000000>;
        opp-microvolt = <1125000>;
      };
      opp-350000000 {
        opp-hz = /bits/ 64 <350000000>;
        opp-microvolt = <1075000>;
      };
      opp-266000000 {
        opp-hz = /bits/ 64 <266000000>;
        opp-microvolt = <1025000>;
      };
      opp-160000000 {
        opp-hz = /bits/ 64 <160000000>;
        opp-microvolt = <925000>;
      };
      opp-100000000 {
        opp-hz = /bits/ 64 <100000000>;
        opp-microvolt = <912500>;
      };
    };

...