code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/st,st-nci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics ST NCI NFC controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - st,st21nfcb-i2c
      - st,st21nfcb-spi
      - st,st21nfcc-i2c

  reset-gpios:
    description: Output GPIO pin used for resetting the controller

  ese-present:
    type: boolean
    description: |
      Specifies that an ese is physically connected to the controller

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

  uicc-present:
    type: boolean
    description: |
      Specifies that the uicc swp signal can be physically connected to the
      controller

required:
  - compatible
  - interrupts
  - reg
  - reset-gpios

if:
  properties:
    compatible:
      contains:
        enum:
          - st,st21nfcb-i2c
          - st,st21nfcc-i2c
then:
  properties:
    spi-max-frequency: false
else:
  $ref: /schemas/spi/spi-peripheral-props.yaml#
  required:
    - spi-max-frequency

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        nfc@8 {
            compatible = "st,st21nfcb-i2c";
            reg = <0x08>;

            interrupt-parent = <&gpio5>;
            interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
            reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;

            ese-present;
            uicc-present;
        };
    };

  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        nfc@0 {
            compatible = "st,st21nfcb-spi";
            reg = <0>;

            spi-max-frequency = <4000000>;

            interrupt-parent = <&gpio5>;
            interrupts = <2 IRQ_TYPE_EDGE_RISING>;
            reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;

            ese-present;
            uicc-present;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/st,st21nfca.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics SAS ST21NFCA NFC controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    const: st,st21nfca-i2c

  enable-gpios:
    description: Output GPIO pin used for enabling/disabling the controller

  ese-present:
    type: boolean
    description: |
      Specifies that an ese is physically connected to the controller

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

  uicc-present:
    type: boolean
    description: |
      Specifies that the uicc swp signal can be physically connected to the
      controller

required:
  - compatible
  - enable-gpios
  - interrupts
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        nfc@1 {
            compatible = "st,st21nfca-i2c";
            reg = <0x1>;

            interrupt-parent = <&gpio5>;
            interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
            enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;

            ese-present;
            uicc-present;
        };
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/st,st95hf.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics ST95HF NFC controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    const: st,st95hf

  enable-gpio:
    description: Output GPIO pin used for enabling/disabling the controller

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

  st95hfvin-supply:
    description: ST95HF transceiver's Vin regulator supply

required:
  - compatible
  - enable-gpio
  - interrupts
  - reg
  - spi-max-frequency

allOf:
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        nfc@0{
            compatible = "st,st95hf";
            reg = <0>;

            spi-max-frequency = <1000000>;
            enable-gpio = <&pio4 GPIO_ACTIVE_HIGH>;
            interrupt-parent = <&pio0>;
            interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/ti,trf7970a.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments TRF7970A RFID/NFC/15693 Transceiver

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Mark Greer <mgreer@animalcreek.com>

properties:
  compatible:
    const: ti,trf7970a

  autosuspend-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Specify autosuspend delay in milliseconds.

  clock-frequency:
    description: |
      Set to specify that the input frequency to the trf7970a is 13560000Hz or
      27120000Hz

  en2-rf-quirk:
    type: boolean
    description: |
      Specify that the trf7970a being used has the "EN2 RF" erratum

  interrupts:
    maxItems: 1

  irq-status-read-quirk:
    type: boolean
    description: |
      Specify that the trf7970a being used has the "IRQ Status Read" erratum

  reg:
    maxItems: 1

  ti,enable-gpios:
    minItems: 1
    maxItems: 2
    description: |
      One or two GPIO entries used for 'EN' and 'EN2' pins on the TRF7970A. EN2
      is optional.

  vdd-io-supply:
    description: |
      Regulator specifying voltage for VDD-IO

  vin-supply:
    description: |
      Regulator for supply voltage to VIN pin

required:
  - compatible
  - interrupts
  - reg
  - spi-max-frequency
  - ti,enable-gpios
  - vin-supply

allOf:
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        nfc@0 {
            compatible = "ti,trf7970a";
            reg = <0>;

            pinctrl-names = "default";
            pinctrl-0 = <&trf7970a_default>;
            spi-max-frequency = <2000000>;
            interrupt-parent = <&gpio2>;
            interrupts = <14 0>;

            ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>,
                              <&gpio2 5 GPIO_ACTIVE_HIGH>;
            vin-supply = <&ldo3_reg>;
            vdd-io-supply = <&ldo2_reg>;
            autosuspend-delay = <30000>;
            irq-status-read-quirk;
            en2-rf-quirk;
            clock-frequency = <27120000>;
        };
    };


code:
* NI XGE Ethernet controller

Required properties:
- compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
              older device trees with DMA engines co-located in the address map,
              with the one reg entry to describe the whole device.
- reg: Address and length of the register set for the device. It contains the
       information of registers in the same order as described by reg-names.
- reg-names: Should contain the reg names
	"dma":  DMA engine control and status region
        "ctrl": MDIO and PHY control and status region
- interrupts: Should contain tx and rx interrupt
- interrupt-names: Should be "rx" and "tx"
- phy-mode: See ethernet.txt file in the same directory.
- nvmem-cells: Phandle of nvmem cell containing the MAC address
- nvmem-cell-names: Should be "address"

Optional properties:
- mdio subnode to indicate presence of MDIO controller
- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
  Use instead of phy-handle.
- phy-handle: See ethernet.txt file in the same directory.

Examples (10G generic PHY):
	nixge0: ethernet@40000000 {
		compatible = "ni,xge-enet-3.00";
		reg = <0x40000000 0x4000
		       0x41002000 0x2000>;
		reg-names = "dma", "ctrl";

		nvmem-cells = <&eth1_addr>;
		nvmem-cell-names = "address";

		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "rx", "tx";
		interrupt-parent = <&intc>;

		phy-mode = "xgmii";
		phy-handle = <&ethernet_phy1>;

		mdio {
			ethernet_phy1: ethernet-phy@4 {
				compatible = "ethernet-phy-ieee802.3-c45";
				reg = <4>;
			};
		};
	};

Examples (10G generic PHY, no MDIO):
	nixge0: ethernet@40000000 {
		compatible = "ni,xge-enet-2.00";
		reg = <0x40000000 0x6000>;

		nvmem-cells = <&eth1_addr>;
		nvmem-cell-names = "address";

		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "rx", "tx";
		interrupt-parent = <&intc>;

		phy-mode = "xgmii";
		phy-handle = <&ethernet_phy1>;
	};

Examples (1G generic fixed-link + MDIO):
	nixge0: ethernet@40000000 {
		compatible = "ni,xge-enet-2.00";
		reg = <0x40000000 0x6000>;

		nvmem-cells = <&eth1_addr>;
		nvmem-cell-names = "address";

		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "rx", "tx";
		interrupt-parent = <&intc>;

		phy-mode = "xgmii";

		fixed-link {
			speed = <1000>;
			pause;
			link-gpios = <&gpio0 63 GPIO_ACTIVE_HIGH>;
		};

		mdio {
			ethernet_phy1: ethernet-phy@4 {
				compatible = "ethernet-phy-ieee802.3-c22";
				reg = <4>;
			};
		};

	};


code:
Nokia Bluetooth Chips
---------------------

Nokia phones often come with UART connected bluetooth chips from different
vendors and modified device API. Those devices speak a protocol named H4+
(also known as h4p) by Nokia, which is similar to the H4 protocol from the
Bluetooth standard. In addition to the H4 protocol it specifies two more
UART status lines for wakeup of UART transceivers to improve power management
and a few new packet types used to negotiate uart speed.

Required properties:

 - compatible: should contain "nokia,h4p-bluetooth" as well as one of the following:
   * "brcm,bcm2048-nokia"
   * "ti,wl1271-bluetooth-nokia"
 - reset-gpios: GPIO specifier, used to reset the BT module (active low)
 - bluetooth-wakeup-gpios: GPIO specifier, used to wakeup the BT module (active high)
 - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor (active high)
 - clock-names: should be "sysclk"
 - clocks: should contain a clock specifier for every name in clock-names

Optional properties:

 - None

Example:

/ {
       /* controlled (enabled/disabled) directly by BT module */
       bluetooth_clk: vctcxo {
               compatible = "fixed-clock";
               #clock-cells = <0>;
               clock-frequency = <38400000>;
       };
};

&uart2 {
       pinctrl-names = "default";
       pinctrl-0 = <&uart2_pins>;

       bluetooth {
               compatible = "ti,wl1271-bluetooth-nokia", "nokia,h4p-bluetooth";

               reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; /* gpio26 */
               host-wakeup-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */
               bluetooth-wakeup-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* gpio37 */

               clocks = <&bluetooth_clk>;
               clock-names = "sysclk";
       };
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Tegra234 MGBE Multi-Gigabit Ethernet Controller

maintainers:
  - Thierry Reding <treding@nvidia.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    const: nvidia,tegra234-mgbe

  reg:
    maxItems: 3

  reg-names:
    items:
      - const: hypervisor
      - const: mac
      - const: xpcs

  interrupts:
    minItems: 1
    maxItems: 3

  interrupt-names:
    minItems: 1
    items:
      - const: common
      - const: macsec-ns
      - const: macsec

  clocks:
    maxItems: 12

  clock-names:
    items:
      - const: mgbe
      - const: mac
      - const: mac-divider
      - const: ptp-ref
      - const: rx-input-m
      - const: rx-input
      - const: tx
      - const: eee-pcs
      - const: rx-pcs-input
      - const: rx-pcs-m
      - const: rx-pcs
      - const: tx-pcs

  resets:
    maxItems: 2

  reset-names:
    items:
      - const: mac
      - const: pcs

  interconnects:
    items:
      - description: memory read client
      - description: memory write client

  interconnect-names:
    items:
      - const: dma-mem
      - const: write

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

  phy-handle: true

  phy-mode:
    contains:
      enum:
        - usxgmii
        - 10gbase-kr

  mdio:
    $ref: mdio.yaml#
    unevaluatedProperties: false
    description:
      Optional node for embedded MDIO controller.

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - resets
  - reset-names
  - power-domains
  - phy-handle
  - phy-mode

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra234-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/memory/tegra234-mc.h>
    #include <dt-bindings/power/tegra234-powergate.h>
    #include <dt-bindings/reset/tegra234-reset.h>

    ethernet@6800000 {
        compatible = "nvidia,tegra234-mgbe";
        reg = <0x06800000 0x10000>,
              <0x06810000 0x10000>,
              <0x068a0000 0x10000>;
        reg-names = "hypervisor", "mac", "xpcs";
        interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "common";
        clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
                 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
                 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
                 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
                 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
                 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
                 <&bpmp TEGRA234_CLK_MGBE0_TX>,
                 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
                 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
                 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
                 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
                 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
        clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
                      "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
                      "rx-pcs", "tx-pcs";
        resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
                 <&bpmp TEGRA234_RESET_MGBE0_PCS>;
        reset-names = "mac", "pcs";
        interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
                        <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
        interconnect-names = "dma-mem", "write";
        iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
        power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;

        phy-handle = <&mgbe0_phy>;
        phy-mode = "usxgmii";

        mdio {
            #address-cells = <1>;
            #size-cells = <0>;

            mgbe0_phy: phy@0 {
                compatible = "ethernet-phy-ieee802.3-c45";
                reg = <0x0>;

                #phy-cells = <0>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8 DWMAC glue layer

maintainers:
  - Clark Wang <xiaoning.wang@nxp.com>
  - Shawn Guo <shawnguo@kernel.org>
  - NXP Linux Team <linux-imx@nxp.com>

# We need a select here so we don't match all nodes with 'snps,dwmac'
select:
  properties:
    compatible:
      contains:
        enum:
          - nxp,imx8mp-dwmac-eqos
          - nxp,imx8dxl-dwmac-eqos
  required:
    - compatible

allOf:
  - $ref: "snps,dwmac.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - nxp,imx8mp-dwmac-eqos
              - nxp,imx8dxl-dwmac-eqos
          - const: snps,dwmac-5.10a

  clocks:
    minItems: 3
    items:
      - description: MAC host clock
      - description: MAC apb clock
      - description: MAC timer clock
      - description: MAC RGMII TX clock
      - description: EQOS MEM clock

  clock-names:
    minItems: 3
    maxItems: 5
    contains:
      enum:
        - stmmaceth
        - pclk
        - ptp_ref
        - tx
        - mem

  intf_mode:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to the GPR syscon
          - description: the offset of the GPR register
    description:
      Should be phandle/offset pair. The phandle to the syscon node which
      encompases the GPR register, and the offset of the GPR register.

  snps,rmii_refclk_ext:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      To select RMII reference clock from external.

required:
  - compatible
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/imx8mp-clock.h>

    eqos: ethernet@30bf0000 {
            compatible = "nxp,imx8mp-dwmac-eqos","snps,dwmac-5.10a";
            reg = <0x30bf0000 0x10000>;
            interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "macirq", "eth_wake_irq";
            clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
                     <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
                     <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
                     <&clk IMX8MP_CLK_ENET_QOS>;
            clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
            phy-mode = "rgmii";
    };


code:
* NXP LPC1850 GMAC ethernet controller

This device is a platform glue layer for stmmac.
Please see stmmac.txt for the other unchanged properties.

Required properties:
 - compatible:  Should contain "nxp,lpc1850-dwmac"

Examples:

mac: ethernet@40010000 {
	compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
	reg = <0x40010000 0x2000>;
	interrupts = <5>;
	interrupt-names = "macirq";
	clocks = <&ccu1 CLK_CPU_ETHERNET>;
	clock-names = "stmmaceth";
	resets = <&rgu 22>;
	reset-names = "stmmaceth";
}


code:
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nxp,tja11xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP TJA11xx PHY

maintainers:
  - Andrew Lunn <andrew@lunn.ch>
  - Florian Fainelli <f.fainelli@gmail.com>
  - Heiner Kallweit <hkallweit1@gmail.com>

description:
  Bindings for NXP TJA11xx automotive PHYs

allOf:
  - $ref: ethernet-phy.yaml#

patternProperties:
  "^ethernet-phy@[0-9a-f]+$":
    type: object
    description: |
      Some packages have multiple PHYs. Secondary PHY should be defines as
      subnode of the first (parent) PHY.

    properties:
      reg:
        minimum: 0
        maximum: 31
        description:
          The ID number for the child PHY. Should be +1 of parent PHY.

      nxp,rmii-refclk-in:
        type: boolean
        description: |
          The REF_CLK is provided for both transmitted and received data
          in RMII mode. This clock signal is provided by the PHY and is
          typically derived from an external 25MHz crystal. Alternatively,
          a 50MHz clock signal generated by an external oscillator can be
          connected to pin REF_CLK. A third option is to connect a 25MHz
          clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
          as input or output according to the actual circuit connection.
          If present, indicates that the REF_CLK will be configured as
          interface reference clock input when RMII mode enabled.
          If not present, the REF_CLK will be configured as interface
          reference clock output when RMII mode enabled.
          Only supported on TJA1100 and TJA1101.

    required:
      - reg

unevaluatedProperties: false

examples:
  - |
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        tja1101_phy0: ethernet-phy@4 {
            reg = <0x4>;
            nxp,rmii-refclk-in;
        };
    };
  - |
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        tja1102_phy0: ethernet-phy@4 {
            reg = <0x4>;
            #address-cells = <1>;
            #size-cells = <0>;

            tja1102_phy1: ethernet-phy@5 {
                reg = <0x5>;
            };
        };
    };


code:
* OpenCores MAC 10/100 Mbps

Required properties:
- compatible: Should be "opencores,ethoc".
- reg: two memory regions (address and length),
  first region is for the device registers and descriptor rings,
  second is for the device packet memory.
- interrupts: interrupt for the device.

Optional properties:
- clocks: phandle to refer to the clk used as per
  Documentation/devicetree/bindings/clock/clock-bindings.txt

Examples:

	enet0: ethoc@fd030000 {
		compatible = "opencores,ethoc";
		reg = <0xfd030000 0x4000 0xfd800000 0x4000>;
		interrupts = <1>;
		local-mac-address = [00 50 c2 13 6f 00];
		clocks = <&osc>;
        };


code:
* Oxford Semiconductor OXNAS DWMAC Ethernet controller

The device inherits all the properties of the dwmac/stmmac devices
described in the file stmmac.txt in the current directory with the
following changes.

Required properties on all platforms:

- compatible:	For the OX820 SoC, it should be :
		- "oxsemi,ox820-dwmac" to select glue
		- "snps,dwmac-3.512" to select IP version.
		For the OX810SE SoC, it should be :
		- "oxsemi,ox810se-dwmac" to select glue
		- "snps,dwmac-3.512" to select IP version.

- clocks: Should contain phandles to the following clocks
- clock-names:	Should contain the following:
		- "stmmaceth" for the host clock - see stmmac.txt
		- "gmac" for the peripheral gate clock

- oxsemi,sys-ctrl: a phandle to the system controller syscon node

Example :

etha: ethernet@40400000 {
	compatible = "oxsemi,ox820-dwmac", "snps,dwmac-3.512";
	reg = <0x40400000 0x2000>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq", "eth_wake_irq";
	mac-address = [000000000000]; /* Filled in by U-Boot */
	phy-mode = "rgmii";

	clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>;
	clock-names = "gmac", "stmmaceth";
	resets = <&reset RESET_MAC>;

	/* Regmap for sys registers */
	oxsemi,sys-ctrl = <&sys>;

};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/pcs/fsl,lynx-pcs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP Lynx PCS

maintainers:
  - Ioana Ciornei <ioana.ciornei@nxp.com>

description: |
  NXP Lynx 10G and 28G SerDes have Ethernet PCS devices which can be used as
  protocol controllers. They are accessible over the Ethernet interface's MDIO
  bus.

properties:
  compatible:
    const: fsl,lynx-pcs

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    mdio-bus {
      #address-cells = <1>;
      #size-cells = <0>;

      qsgmii_pcs1: ethernet-pcs@1 {
        compatible = "fsl,lynx-pcs";
        reg = <1>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/N1 MII converter

maintainers:
  - Clément Léger <clement.leger@bootlin.com>

description: |
  This MII converter is present on the Renesas RZ/N1 SoC family. It is
  responsible to do MII passthrough or convert it to RMII/RGMII.

properties:
  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  compatible:
    items:
      - enum:
          - renesas,r9a06g032-miic
      - const: renesas,rzn1-miic

  reg:
    maxItems: 1

  clocks:
    items:
      - description: MII reference clock
      - description: RGMII reference clock
      - description: RMII reference clock
      - description: AHB clock used for the MII converter register interface

  clock-names:
    items:
      - const: mii_ref
      - const: rgmii_ref
      - const: rmii_ref
      - const: hclk

  renesas,miic-switch-portin:
    description: MII Switch PORTIN configuration. This value should use one of
      the values defined in dt-bindings/net/pcs-rzn1-miic.h.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2]

  power-domains:
    maxItems: 1

patternProperties:
  "^mii-conv@[0-5]$":
    type: object
    description: MII converter port

    properties:
      reg:
        description: MII Converter port number.
        enum: [1, 2, 3, 4, 5]

      renesas,miic-input:
        description: Converter input port configuration. This value should use
          one of the values defined in dt-bindings/net/pcs-rzn1-miic.h.
        $ref: /schemas/types.yaml#/definitions/uint32

    required:
      - reg
      - renesas,miic-input

    additionalProperties: false

    allOf:
      - if:
          properties:
            reg:
              const: 1
        then:
          properties:
            renesas,miic-input:
              const: 0
      - if:
          properties:
            reg:
              const: 2
        then:
          properties:
            renesas,miic-input:
              enum: [1, 11]
      - if:
          properties:
            reg:
              const: 3
        then:
          properties:
            renesas,miic-input:
              enum: [7, 10]
      - if:
          properties:
            reg:
              const: 4
        then:
          properties:
            renesas,miic-input:
              enum: [4, 6, 9, 13]
      - if:
          properties:
            reg:
              const: 5
        then:
          properties:
            renesas,miic-input:
              enum: [3, 5, 8, 12]

required:
  - '#address-cells'
  - '#size-cells'
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/net/pcs-rzn1-miic.h>
    #include <dt-bindings/clock/r9a06g032-sysctrl.h>

    eth-miic@44030000 {
      #address-cells = <1>;
      #size-cells = <0>;
      compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
      reg = <0x44030000 0x10000>;
      clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
              <&sysctrl R9A06G032_CLK_RGMII_REF>,
              <&sysctrl R9A06G032_CLK_RMII_REF>,
              <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
      clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
      renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
      power-domains = <&sysctrl>;

      mii_conv1: mii-conv@1 {
        renesas,miic-input = <MIIC_GMAC1_PORT>;
        reg = <1>;
      };

      mii_conv2: mii-conv@2 {
        renesas,miic-input = <MIIC_SWITCH_PORTD>;
        reg = <2>;
      };

      mii_conv3: mii-conv@3 {
        renesas,miic-input = <MIIC_SWITCH_PORTC>;
        reg = <3>;
      };

      mii_conv4: mii-conv@4 {
        renesas,miic-input = <MIIC_SWITCH_PORTB>;
        reg = <4>;
      };

      mii_conv5: mii-conv@5 {
        renesas,miic-input = <MIIC_SWITCH_PORTA>;
        reg = <5>;
      };
    };


code: This file has moved to ethernet-phy.yaml.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/pse-pd/podl-pse-regulator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Regulator based Power Sourcing Equipment

maintainers:
  - Oleksij Rempel <o.rempel@pengutronix.de>

description: Regulator based PoDL PSE controller. The device must be referenced
  by the PHY node to control power injection to the Ethernet cable.

allOf:
  - $ref: "pse-controller.yaml#"

properties:
  compatible:
    const: podl-pse-regulator

  '#pse-cells':
    const: 0

  pse-supply:
    description: Power supply for the PSE controller

additionalProperties: false

required:
  - compatible
  - pse-supply

examples:
  - |
    ethernet-pse {
      compatible = "podl-pse-regulator";
      pse-supply = <&reg_t1l1>;
      #pse-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/pse-pd/pse-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Power Sourcing Equipment (PSE).

description: Binding for the Power Sourcing Equipment (PSE) as defined in the
  IEEE 802.3 specification. It is designed for hardware which is delivering
  power over twisted pair/ethernet cable. The ethernet-pse nodes should be
  used to describe PSE controller and referenced by the ethernet-phy node.

maintainers:
  - Oleksij Rempel <o.rempel@pengutronix.de>

properties:
  $nodename:
    pattern: "^ethernet-pse(@.*)?$"

  "#pse-cells":
    description:
      Used to uniquely identify a PSE instance within an IC. Will be
      0 on PSE nodes with only a single output and at least 1 on nodes
      controlling several outputs.
    enum: [0, 1]

required:
  - "#pse-cells"

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/qca,ar71xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: QCA AR71XX MAC

allOf:
  - $ref: ethernet-controller.yaml#

maintainers:
  - Oleksij Rempel <o.rempel@pengutronix.de>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - qca,ar7100-eth   # Atheros AR7100
              - qca,ar7240-eth   # Atheros AR7240
              - qca,ar7241-eth   # Atheros AR7241
              - qca,ar7242-eth   # Atheros AR7242
              - qca,ar9130-eth   # Atheros AR9130
              - qca,ar9330-eth   # Atheros AR9330
              - qca,ar9340-eth   # Atheros AR9340
              - qca,qca9530-eth  # Qualcomm Atheros QCA9530
              - qca,qca9550-eth  # Qualcomm Atheros QCA9550
              - qca,qca9560-eth  # Qualcomm Atheros QCA9560

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: MAC main clock
      - description: MDIO clock

  clock-names:
    items:
      - const: eth
      - const: mdio

  resets:
    items:
      - description: MAC reset
      - description: MDIO reset

  reset-names:
    items:
      - const: mac
      - const: mdio

  mdio:
    $ref: mdio.yaml#
    unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts
  - phy-mode
  - clocks
  - clock-names
  - resets
  - reset-names

unevaluatedProperties: false

examples:
  # Lager board
  - |
    eth0: ethernet@19000000 {
        compatible = "qca,ar9330-eth";
        reg = <0x19000000 0x200>;
        interrupts = <4>;
        resets = <&rst 9>, <&rst 22>;
        reset-names = "mac", "mdio";
        clocks = <&pll 1>, <&pll 2>;
        clock-names = "eth", "mdio";
        phy-mode = "mii";
        phy-handle = <&phy_port4>;
    };

    eth1: ethernet@1a000000 {
        compatible = "qca,ar9330-eth";
        reg = <0x1a000000 0x200>;
        interrupts = <5>;
        resets = <&rst 13>, <&rst 23>;
        reset-names = "mac", "mdio";
        clocks = <&pll 1>, <&pll 2>;
        clock-names = "eth", "mdio";

        phy-mode = "gmii";

        fixed-link {
            speed = <1000>;
            full-duplex;
        };

        mdio {
            #address-cells = <1>;
            #size-cells = <0>;

            switch10: switch@10 {
                compatible = "qca,ar9331-switch";
                reg = <0x10>;
                resets = <&rst 8>;
                reset-names = "switch";

                interrupt-parent = <&miscintc>;
                interrupts = <12>;

                interrupt-controller;
                #interrupt-cells = <1>;

                ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    switch_port0: port@0 {
                        reg = <0x0>;
                        ethernet = <&eth1>;

                        phy-mode = "gmii";

                        fixed-link {
                            speed = <1000>;
                            full-duplex;
                        };
                    };

                    switch_port1: port@1 {
                        reg = <0x1>;
                        phy-handle = <&phy_port0>;
                        phy-mode = "internal";
                    };

                    switch_port2: port@2 {
                        reg = <0x2>;
                        phy-handle = <&phy_port1>;
                        phy-mode = "internal";
                    };

                    switch_port3: port@3 {
                        reg = <0x3>;
                        phy-handle = <&phy_port2>;
                        phy-mode = "internal";
                    };

                    switch_port4: port@4 {
                        reg = <0x4>;
                        phy-handle = <&phy_port3>;
                        phy-mode = "internal";
                    };
                };

                mdio {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    interrupt-parent = <&switch10>;

                    phy_port0: ethernet-phy@0 {
                        reg = <0x0>;
                        interrupts = <0>;
                    };

                    phy_port1: ethernet-phy@1 {
                        reg = <0x1>;
                        interrupts = <0>;
                    };

                    phy_port2: ethernet-phy@2 {
                        reg = <0x2>;
                        interrupts = <0>;
                    };

                    phy_port3: ethernet-phy@3 {
                        reg = <0x3>;
                        interrupts = <0>;
                    };

                    phy_port4: ethernet-phy@4 {
                        reg = <0x4>;
                        interrupts = <0>;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Atheros AR803x PHY

maintainers:
  - Andrew Lunn <andrew@lunn.ch>
  - Florian Fainelli <f.fainelli@gmail.com>
  - Heiner Kallweit <hkallweit1@gmail.com>

description: |
  Bindings for Qualcomm Atheros AR803x PHYs

allOf:
  - $ref: ethernet-phy.yaml#

properties:
  qca,clk-out-frequency:
    description: Clock output frequency in Hertz.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [25000000, 50000000, 62500000, 125000000]

  qca,clk-out-strength:
    description: Clock output driver strength.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2]

  qca,disable-smarteee:
    description: Disable Atheros SmartEEE feature.
    type: boolean

  qca,keep-pll-enabled:
    description: |
      If set, keep the PLL enabled even if there is no link. Useful if you
      want to use the clock output without an ethernet link.

      Only supported on the AR8031.
    type: boolean

  qca,disable-hibernation-mode:
    description: |
      Disable Atheros AR803X PHYs hibernation mode. If present, indicates
      that the hardware of PHY will not enter power saving mode when the
      cable is disconnected. And the RX_CLK always keeps outputting a
      valid clock.
    type: boolean

  qca,smarteee-tw-us-100m:
    description: EEE Tw parameter for 100M links.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 255

  qca,smarteee-tw-us-1g:
    description: EEE Tw parameter for gigabit links.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 255

  vddio-supply:
    description: |
      RGMII I/O voltage regulator (see regulator/regulator.yaml).

      The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
      either connect this to the vddio-regulator (1.5V / 1.8V) or the
      vddh-regulator (2.5V).

      Only supported on the AR8031.

  vddio-regulator:
    type: object
    description:
      Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V.
    $ref: /schemas/regulator/regulator.yaml

  vddh-regulator:
    type: object
    description:
      Dummy subnode to model the external connection of the PHY VDDH
      regulator to VDDIO.
    $ref: /schemas/regulator/regulator.yaml

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/net/qca-ar803x.h>

    ethernet {
        #address-cells = <1>;
        #size-cells = <0>;

        phy-mode = "rgmii-id";

        ethernet-phy@0 {
            reg = <0>;

            qca,clk-out-frequency = <125000000>;
            qca,clk-out-strength = <AR803X_STRENGTH_FULL>;

            vddio-supply = <&vddio>;

            vddio: vddio-regulator {
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
            };
        };
    };
  - |
    #include <dt-bindings/net/qca-ar803x.h>

    ethernet {
        #address-cells = <1>;
        #size-cells = <0>;

        phy-mode = "rgmii-id";

        ethernet-phy@0 {
            reg = <0>;

            qca,clk-out-frequency = <50000000>;
            qca,keep-pll-enabled;

            vddio-supply = <&vddh>;

            vddh: vddh-regulator {
            };
        };
    };


code:
* Qualcomm QCA7000

The QCA7000 is a serial-to-powerline bridge with a host interface which could
be configured either as SPI or UART slave. This configuration is done by
the QCA7000 firmware.

(a) Ethernet over SPI

In order to use the QCA7000 as SPI device it must be defined as a child of a
SPI master in the device tree.

Required properties:
- compatible	    : Should be "qca,qca7000"
- reg		    : Should specify the SPI chip select
- interrupts	    : The first cell should specify the index of the source
		      interrupt and the second cell should specify the trigger
		      type as rising edge
- spi-cpha	    : Must be set
- spi-cpol	    : Must be set

Optional properties:
- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at.
		      Numbers smaller than 1000000 or greater than 16000000
		      are invalid. Missing the property will set the SPI
		      frequency to 8000000 Hertz.
- qca,legacy-mode   : Set the SPI data transfer of the QCA7000 to legacy mode.
		      In this mode the SPI master must toggle the chip select
		      between each data word. In burst mode these gaps aren't
		      necessary, which is faster. This setting depends on how
		      the QCA7000 is setup via GPIO pin strapping. If the
		      property is missing the driver defaults to burst mode.

The MAC address will be determined using the optional properties
defined in ethernet.txt.

SPI Example:

/* Freescale i.MX28 SPI master*/
ssp2: spi@80014000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx28-spi";
	pinctrl-names = "default";
	pinctrl-0 = <&spi2_pins_a>;

	qca7000: ethernet@0 {
		compatible = "qca,qca7000";
		reg = <0x0>;
		interrupt-parent = <&gpio3>;      /* GPIO Bank 3 */
		interrupts = <25 0x1>;            /* Index: 25, rising edge */
		spi-cpha;                         /* SPI mode: CPHA=1 */
		spi-cpol;                         /* SPI mode: CPOL=1 */
		spi-max-frequency = <8000000>;    /* freq: 8 MHz */
		local-mac-address = [ A0 B0 C0 D0 E0 F0 ];
	};
};

(b) Ethernet over UART

In order to use the QCA7000 as UART slave it must be defined as a child of a
UART master in the device tree. It is possible to preconfigure the UART
settings of the QCA7000 firmware, but it's not possible to change them during
runtime.

Required properties:
- compatible        : Should be "qca,qca7000"

Optional properties:
- local-mac-address : see ./ethernet.txt
- current-speed     : current baud rate of QCA7000 which defaults to 115200
		      if absent, see also ../serial/serial.yaml

UART Example:

/* Freescale i.MX28 UART */
auart0: serial@8006a000 {
	compatible = "fsl,imx28-auart", "fsl,imx23-auart";
	reg = <0x8006a000 0x2000>;
	pinctrl-names = "default";
	pinctrl-0 = <&auart0_2pins_a>;

	qca7000: ethernet {
		compatible = "qca,qca7000";
		local-mac-address = [ A0 B0 C0 D0 E0 F0 ];
		current-speed = <38400>;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/qcom,bam-dmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm BAM Data Multiplexer

maintainers:
  - Stephan Gerhold <stephan@gerhold.net>

description: |
  The BAM Data Multiplexer provides access to the network data channels
  of modems integrated into many older Qualcomm SoCs, e.g. Qualcomm MSM8916
  or MSM8974. It is built using a simple protocol layer on top of a DMA engine
  (Qualcomm BAM DMA) and bidirectional interrupts to coordinate power control.

  Note that this schema does not directly describe a hardware block but rather
  a firmware convention that combines several other hardware blocks (such as the
  DMA engine). As such it is specific to a firmware version, not a particular
  SoC or hardware version.

properties:
  compatible:
    const: qcom,bam-dmux

  interrupts:
    description:
      Interrupts used by the modem to signal the AP.
      Both interrupts must be declared as IRQ_TYPE_EDGE_BOTH.
    items:
      - description: Power control
      - description: Power control acknowledgment

  interrupt-names:
    items:
      - const: pc
      - const: pc-ack

  qcom,smem-states:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: State bits used by the AP to signal the modem.
    items:
      - description: Power control
      - description: Power control acknowledgment

  qcom,smem-state-names:
    description: Names for the state bits used by the AP to signal the modem.
    items:
      - const: pc
      - const: pc-ack

  dmas:
    items:
      - description: TX DMA channel phandle
      - description: RX DMA channel phandle

  dma-names:
    items:
      - const: tx
      - const: rx

required:
  - compatible
  - interrupts
  - interrupt-names
  - qcom,smem-states
  - qcom,smem-state-names
  - dmas
  - dma-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    mpss: remoteproc {
        bam-dmux {
            compatible = "qcom,bam-dmux";

            interrupt-parent = <&modem_smsm>;
            interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
            interrupt-names = "pc", "pc-ack";

            qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
            qcom,smem-state-names = "pc", "pc-ack";

            dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
            dma-names = "tx", "rx";
        };
    };


code:
Qualcomm Ethernet ETHQOS device

This documents dwmmac based ethernet device which supports Gigabit
ethernet for version v2.3.0 onwards.

This device has following properties:

Required properties:

- compatible: Should be one of:
		"qcom,qcs404-ethqos"
		"qcom,sm8150-ethqos"

- reg: Address and length of the register set for the device

- reg-names: Should contain register names "stmmaceth", "rgmii"

- clocks: Should contain phandle to clocks

- clock-names: Should contain clock names "stmmaceth", "pclk",
		"ptp_ref", "rgmii"

- interrupts: Should contain phandle to interrupts

- interrupt-names: Should contain interrupt names "macirq", "eth_lpi"

Rest of the properties are defined in stmmac.txt file in same directory

Example:

ethernet: ethernet@7a80000 {
	compatible = "qcom,qcs404-ethqos";
	reg = <0x07a80000 0x10000>,
		<0x07a96000 0x100>;
	reg-names = "stmmaceth", "rgmii";
	clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
	clocks = <&gcc GCC_ETH_AXI_CLK>,
		<&gcc GCC_ETH_SLAVE_AHB_CLK>,
		<&gcc GCC_ETH_PTP_CLK>,
		<&gcc GCC_ETH_RGMII_CLK>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "macirq", "eth_lpi";
	snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;

	snps,txpbl = <8>;
	snps,rxpbl = <2>;
	snps,aal;
	snps,tso;

	phy-handle = <&phy1>;
	phy-mode = "rgmii";

	mdio {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "snps,dwmac-mdio";
		phy1: phy@4 {
			device_type = "ethernet-phy";
			reg = <0x4>;
		};
	};

};


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/qcom,ipa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm IP Accelerator (IPA)

maintainers:
  - Alex Elder <elder@kernel.org>

description:
  This binding describes the Qualcomm IPA.  The IPA is capable of offloading
  certain network processing tasks (e.g. filtering, routing, and NAT) from
  the main processor.

  The IPA sits between multiple independent "execution environments,"
  including the Application Processor (AP) and the modem.  The IPA presents
  a Generic Software Interface (GSI) to each execution environment.
  The GSI is an integral part of the IPA, but it is logically isolated
  and has a distinct interrupt and a separately-defined address space.

  See also soc/qcom/qcom,smp2p.txt and interconnect/interconnect.txt.  See
  iommu/iommu.txt and iommu/arm,smmu.yaml for more information about SMMU
  bindings.

  - |
    --------             ---------
    |      |             |       |
    |  AP  +<---.   .----+ Modem |
    |      +--. |   | .->+       |
    |      |  | |   | |  |       |
    --------  | |   | |  ---------
              v |   v |
            --+-+---+-+--
            |    GSI    |
            |-----------|
            |           |
            |    IPA    |
            |           |
            -------------

properties:
  compatible:
    enum:
      - qcom,msm8998-ipa
      - qcom,sc7180-ipa
      - qcom,sc7280-ipa
      - qcom,sdm845-ipa
      - qcom,sdx55-ipa
      - qcom,sm6350-ipa
      - qcom,sm8350-ipa

  reg:
    items:
      - description: IPA registers
      - description: IPA shared memory
      - description: GSI registers

  reg-names:
    items:
      - const: ipa-reg
      - const: ipa-shared
      - const: gsi

  iommus:
    minItems: 1
    maxItems: 2

  clocks:
    maxItems: 1

  clock-names:
    const: core

  interrupts:
    items:
      - description: IPA interrupt (hardware IRQ)
      - description: GSI interrupt (hardware IRQ)
      - description: Modem clock query interrupt (smp2p interrupt)
      - description: Modem setup ready interrupt (smp2p interrupt)

  interrupt-names:
    items:
      - const: ipa
      - const: gsi
      - const: ipa-clock-query
      - const: ipa-setup-ready

  interconnects:
    oneOf:
      - items:
          - description: Path leading to system memory
          - description: Path between the AP and IPA config space
      - items:
          - description: Path leading to system memory
          - description: Path leading to internal memory
          - description: Path between the AP and IPA config space

  interconnect-names:
    oneOf:
      - items:
          - const: memory
          - const: config
      - items:
          - const: memory
          - const: imem
          - const: config

  qcom,qmp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle to the AOSS side-channel message RAM

  qcom,smem-states:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: State bits used in by the AP to signal the modem.
    items:
      - description: Whether the "ipa-clock-enabled" state bit is valid
      - description: Whether the IPA clock is enabled (if valid)

  qcom,smem-state-names:
    description: The names of the state bits used for SMP2P output
    items:
      - const: ipa-clock-enabled-valid
      - const: ipa-clock-enabled

  qcom,gsi-loader:
    enum:
      - self
      - modem
      - skip
    description:
      Indicates how GSI firmware should be loaded.  If the AP loads
      and validates GSI firmware, this property has value "self".
      If the modem does this, this property has value "modem".
      Otherwise, "skip" means GSI firmware loading is not required.

  modem-init:
    deprecated: true
    type: boolean
    description:
      This is the older (deprecated) way of indicating how GSI firmware
      should be loaded.  If present, the modem loads GSI firmware; if
      absent, the AP loads GSI firmware.

  memory-region:
    maxItems: 1
    description:
      If present, a phandle for a reserved memory area that holds
      the firmware passed to Trust Zone for authentication.  Required
      when the AP (not the modem) performs early initialization.

  firmware-name:
    $ref: /schemas/types.yaml#/definitions/string
    description:
      If present, name (or relative path) of the file within the
      firmware search path containing the firmware image used when
      initializing IPA hardware.  Optional, and only used when
      Trust Zone performs early initialization.

required:
  - compatible
  - iommus
  - reg
  - clocks
  - interrupts
  - interconnects
  - qcom,smem-states

allOf:
  # If qcom,gsi-loader is present, modem-init must not be present
  - if:
      required:
        - qcom,gsi-loader
    then:
      properties:
        modem-init: false

      # If qcom,gsi-loader is "self", the AP loads GSI firmware, and
      # memory-region must be specified
      if:
        properties:
          qcom,gsi-loader:
            contains:
              const: self
      then:
        required:
          - memory-region
    else:
      # If qcom,gsi-loader is not present, we use deprecated behavior.
      # If modem-init is not present, the AP loads GSI firmware, and
      # memory-region must be specified.
      if:
        not:
          required:
            - modem-init
      then:
        required:
          - memory-region

additionalProperties: false

examples:
  - |
        #include <dt-bindings/interrupt-controller/arm-gic.h>
        #include <dt-bindings/clock/qcom,rpmh.h>
        #include <dt-bindings/interconnect/qcom,sdm845.h>

        smp2p-mpss {
                compatible = "qcom,smp2p";
                interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
                mboxes = <&apss_shared 6>;
                qcom,smem = <94>, <432>;
                qcom,local-pid = <0>;
                qcom,remote-pid = <5>;

                ipa_smp2p_out: ipa-ap-to-modem {
                        qcom,entry-name = "ipa";
                        #qcom,smem-state-cells = <1>;
                };

                ipa_smp2p_in: ipa-modem-to-ap {
                        qcom,entry-name = "ipa";
                        interrupt-controller;
                        #interrupt-cells = <2>;
                };
        };

        ipa@1e40000 {
                compatible = "qcom,sc7180-ipa";

                qcom,gsi-loader = "self";
                memory-region = <&ipa_fw_mem>;
                firmware-name = "qcom/sc7180-trogdor/modem/modem.mdt";

                iommus = <&apps_smmu 0x440 0x0>,
                         <&apps_smmu 0x442 0x0>;
                reg = <0x1e40000 0x7000>,
                      <0x1e47000 0x2000>,
                      <0x1e04000 0x2c000>;
                reg-names = "ipa-reg",
                            "ipa-shared",
                            "gsi";

                interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
                                      <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
                                      <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
                                      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
                interrupt-names = "ipa",
                                  "gsi",
                                  "ipa-clock-query",
                                  "ipa-setup-ready";

                clocks = <&rpmhcc RPMH_IPA_CLK>;
                clock-names = "core";

                interconnects =
                        <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
                        <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
                interconnect-names = "memory",
                                     "imem",
                                     "config";

                qcom,qmp = <&aoss_qmp>;

                qcom,smem-states = <&ipa_smp2p_out 0>,
                                   <&ipa_smp2p_out 1>;
                qcom,smem-state-names = "ipa-clock-enabled-valid",
                                        "ipa-clock-enabled";
        };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm IPQ40xx MDIO Controller

maintainers:
  - Robert Marko <robert.marko@sartura.hr>

properties:
  compatible:
    oneOf:
      - enum:
          - qcom,ipq4019-mdio
          - qcom,ipq5018-mdio

      - items:
          - enum:
              - qcom,ipq6018-mdio
              - qcom,ipq8074-mdio
          - const: qcom,ipq4019-mdio

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  reg:
    minItems: 1
    maxItems: 2
    description:
      the first Address and length of the register set for the MDIO controller.
      the second Address and length of the register for ethernet LDO, this second
      address range is only required by the platform IPQ50xx.

  clocks:
    items:
      - description: MDIO clock source frequency fixed to 100MHZ

  clock-names:
    items:
      - const: gcc_mdio_ahb_clk

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"

allOf:
  - $ref: "mdio.yaml#"

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq5018-mdio
              - qcom,ipq6018-mdio
              - qcom,ipq8074-mdio
    then:
      required:
        - clocks
        - clock-names
    else:
      properties:
        clocks: false
        clock-names: false

unevaluatedProperties: false

examples:
  - |
    mdio@90000 {
      #address-cells = <1>;
      #size-cells = <0>;
      compatible = "qcom,ipq4019-mdio";
      reg = <0x90000 0x64>;

      ethphy0: ethernet-phy@0 {
        reg = <0>;
      };

      ethphy1: ethernet-phy@1 {
        reg = <1>;
      };

      ethphy2: ethernet-phy@2 {
        reg = <2>;
      };

      ethphy3: ethernet-phy@3 {
        reg = <3>;
      };

      ethphy4: ethernet-phy@4 {
        reg = <4>;
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/qcom,ipq8064-mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm ipq806x MDIO bus controller

maintainers:
  - Ansuel Smith <ansuelsmth@gmail.com>

description:
  The ipq806x soc have a MDIO dedicated controller that is
  used to communicate with the gmac phy connected.

allOf:
  - $ref: "mdio.yaml#"

properties:
  compatible:
    const: qcom,ipq8064-mdio

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - "#address-cells"
  - "#size-cells"

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>

    mdio0: mdio@37000000 {
        #address-cells = <1>;
        #size-cells = <0>;

        compatible = "qcom,ipq8064-mdio";
        reg = <0x37000000 0x200000>;

        clocks = <&gcc GMAC_CORE1_CLK>;

        switch@10 {
            compatible = "qca,qca8337";
            reg = <0x10>;

            ports {
              /* ... */
            };
        };
    };


code:
Qualcomm Technologies EMAC Gigabit Ethernet Controller

This network controller consists of two devices: a MAC and an SGMII
internal PHY.  Each device is represented by a device tree node.  A phandle
connects the MAC node to its corresponding internal phy node.  Another
phandle points to the external PHY node.

Required properties:

MAC node:
- compatible : Should be "qcom,fsm9900-emac".
- reg : Offset and length of the register regions for the device
- interrupts : Interrupt number used by this controller
- mac-address : The 6-byte MAC address. If present, it is the default
	MAC address.
- internal-phy : phandle to the internal PHY node
- phy-handle : phandle to the external PHY node

Internal PHY node:
- compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii".
- reg : Offset and length of the register region(s) for the device
- interrupts : Interrupt number used by this controller

The external phy child node:
- reg : The phy address

Example:

FSM9900:

soc {
	#address-cells = <1>;
	#size-cells = <1>;

	emac0: ethernet@feb20000 {
		compatible = "qcom,fsm9900-emac";
		reg = <0xfeb20000 0x10000>,
		      <0xfeb36000 0x1000>;
		interrupts = <76>;

		clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
			<&gcc 6>, <&gcc 7>;
		clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk",
			"mdio_clk", "tx_clk", "rx_clk", "sys_clk";

		internal-phy = <&emac_sgmii>;

		phy-handle = <&phy0>;

		#address-cells = <1>;
		#size-cells = <0>;
		phy0: ethernet-phy@0 {
			reg = <0>;
		};

		pinctrl-names = "default";
		pinctrl-0 = <&mdio_pins_a>;
	};

	emac_sgmii: ethernet@feb38000 {
		compatible = "qcom,fsm9900-emac-sgmii";
		reg = <0xfeb38000 0x1000>;
		interrupts = <80>;
	};

	tlmm: pinctrl@fd510000 {
		compatible = "qcom,fsm9900-pinctrl";

		mdio_pins_a: mdio {
			state {
				pins = "gpio123", "gpio124";
				function = "mdio";
			};
		};
	};

QDF2432:

soc {
	#address-cells = <2>;
	#size-cells = <2>;

	emac0: ethernet@38800000 {
		compatible = "qcom,fsm9900-emac";
		reg = <0x0 0x38800000 0x0 0x10000>,
		      <0x0 0x38816000 0x0 0x1000>;
		interrupts = <0 256 4>;

		clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
			 <&gcc 6>, <&gcc 7>;
		clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk",
			"mdio_clk", "tx_clk", "rx_clk", "sys_clk";

		internal-phy = <&emac_sgmii>;

		phy-handle = <&phy0>;

		#address-cells = <1>;
		#size-cells = <0>;
		phy0: ethernet-phy@4 {
			reg = <4>;
		};
	};

	emac_sgmii: ethernet@410400 {
		compatible = "qcom,qdf2432-emac-sgmii";
		reg = <0x0 0x00410400 0x0 0xc00>, /* Base address */
		      <0x0 0x00410000 0x0 0x400>; /* Per-lane digital */
		interrupts = <0 254 1>;
	};


code:
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Realtek RTL82xx PHY

maintainers:
  - Andrew Lunn <andrew@lunn.ch>
  - Florian Fainelli <f.fainelli@gmail.com>
  - Heiner Kallweit <hkallweit1@gmail.com>

description:
  Bindings for Realtek RTL82xx PHYs

allOf:
  - $ref: ethernet-phy.yaml#

properties:
  realtek,clkout-disable:
    type: boolean
    description:
      Disable CLKOUT clock, CLKOUT clock default is enabled after hardware reset.

  realtek,aldps-enable:
    type: boolean
    description:
      Enable ALDPS mode, ALDPS mode default is disabled after hardware reset.

unevaluatedProperties: false

examples:
  - |
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        ethphy1: ethernet-phy@1 {
                reg = <1>;
                realtek,clkout-disable;
                realtek,aldps-enable;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/realtek-bluetooth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RTL8723BS/RTL8723CS/RTL8822CS Bluetooth

maintainers:
  - Vasily Khoruzhick <anarsoul@gmail.com>
  - Alistair Francis <alistair@alistair23.me>

description:
  RTL8723CS/RTL8723CS/RTL8822CS is WiFi + BT chip. WiFi part is connected over
  SDIO, while BT is connected over serial. It speaks H5 protocol with few
  extra commands to upload firmware and change module speed.

properties:
  compatible:
    enum:
      - realtek,rtl8723bs-bt
      - realtek,rtl8723cs-bt
      - realtek,rtl8723ds-bt
      - realtek,rtl8822cs-bt

  device-wake-gpios:
    maxItems: 1
    description: GPIO specifier, used to wakeup the BT module

  enable-gpios:
    maxItems: 1
    description: GPIO specifier, used to enable the BT module

  host-wake-gpios:
    maxItems: 1
    description: GPIO specifier, used to wakeup the host processor

  max-speed: true

required:
  - compatible

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
        uart-has-rtscts;

        bluetooth {
            compatible = "realtek,rtl8723bs-bt";
            device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
            host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/renesas,ether.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Electronics SH EtherMAC

allOf:
  - $ref: ethernet-controller.yaml#

maintainers:
  - Sergei Shtylyov <sergei.shtylyov@gmail.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,gether-r8a7740   # device is a part of R8A7740 SoC
              - renesas,gether-r8a77980  # device is a part of R8A77980 SoC
              - renesas,ether-r7s72100   # device is a part of R7S72100 SoC
              - renesas,ether-r7s9210    # device is a part of R7S9210 SoC
      - items:
          - enum:
              - renesas,ether-r8a7778    # device is a part of R8A7778 SoC
              - renesas,ether-r8a7779    # device is a part of R8A7779 SoC
          - enum:
              - renesas,rcar-gen1-ether  # a generic R-Car Gen1 device
      - items:
          - enum:
              - renesas,ether-r8a7742    # device is a part of R8A7742 SoC
              - renesas,ether-r8a7743    # device is a part of R8A7743 SoC
              - renesas,ether-r8a7745    # device is a part of R8A7745 SoC
              - renesas,ether-r8a7790    # device is a part of R8A7790 SoC
              - renesas,ether-r8a7791    # device is a part of R8A7791 SoC
              - renesas,ether-r8a7793    # device is a part of R8A7793 SoC
              - renesas,ether-r8a7794    # device is a part of R8A7794 SoC
          - enum:
              - renesas,rcar-gen2-ether  # a generic R-Car Gen2 or RZ/G1 device

  reg:
    items:
      - description: E-DMAC/feLic registers
      - description: TSU registers
    minItems: 1

  interrupts:
    maxItems: 1

  '#address-cells':
    description: number of address cells for the MDIO bus
    const: 1

  '#size-cells':
    description: number of size cells on the MDIO bus
    const: 0

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  phy-mode: true

  phy-handle: true

  renesas,no-ether-link:
    type: boolean
    description:
      specify when a board does not provide a proper Ether LINK signal

  renesas,ether-link-active-low:
    type: boolean
    description:
      specify when the Ether LINK signal is active-low instead of normal
      active-high

patternProperties:
  "^ethernet-phy@[0-9a-f]$":
    type: object
    $ref: ethernet-phy.yaml#

required:
  - compatible
  - reg
  - interrupts
  - phy-mode
  - phy-handle
  - '#address-cells'
  - '#size-cells'
  - clocks

additionalProperties: false

examples:
  # Lager board
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>
    #include <dt-bindings/gpio/gpio.h>

    ethernet@ee700000 {
        compatible = "renesas,ether-r8a7790", "renesas,rcar-gen2-ether";
        reg = <0xee700000 0x400>;
        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD 813>;
        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
        resets = <&cpg 813>;
        phy-mode = "rmii";
        phy-handle = <&phy1>;
        renesas,ether-link-active-low;
        #address-cells = <1>;
        #size-cells = <0>;

        phy1: ethernet-phy@1 {
            compatible = "ethernet-phy-id0022.1537",
                         "ethernet-phy-ieee802.3-c22";
            reg = <1>;
            interrupt-parent = <&irqc0>;
            interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
            micrel,led-mode = <1>;
            reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/renesas,etheravb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Ethernet AVB

maintainers:
  - Sergei Shtylyov <sergei.shtylyov@gmail.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,etheravb-r8a7742      # RZ/G1H
              - renesas,etheravb-r8a7743      # RZ/G1M
              - renesas,etheravb-r8a7744      # RZ/G1N
              - renesas,etheravb-r8a7745      # RZ/G1E
              - renesas,etheravb-r8a77470     # RZ/G1C
              - renesas,etheravb-r8a7790      # R-Car H2
              - renesas,etheravb-r8a7791      # R-Car M2-W
              - renesas,etheravb-r8a7792      # R-Car V2H
              - renesas,etheravb-r8a7793      # R-Car M2-N
              - renesas,etheravb-r8a7794      # R-Car E2
          - const: renesas,etheravb-rcar-gen2 # R-Car Gen2 and RZ/G1

      - items:
          - enum:
              - renesas,etheravb-r8a774a1     # RZ/G2M
              - renesas,etheravb-r8a774b1     # RZ/G2N
              - renesas,etheravb-r8a774c0     # RZ/G2E
              - renesas,etheravb-r8a774e1     # RZ/G2H
              - renesas,etheravb-r8a7795      # R-Car H3
              - renesas,etheravb-r8a7796      # R-Car M3-W
              - renesas,etheravb-r8a77961     # R-Car M3-W+
              - renesas,etheravb-r8a77965     # R-Car M3-N
              - renesas,etheravb-r8a77970     # R-Car V3M
              - renesas,etheravb-r8a77980     # R-Car V3H
              - renesas,etheravb-r8a77990     # R-Car E3
              - renesas,etheravb-r8a77995     # R-Car D3
          - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2

      - items:
          - enum:
              - renesas,etheravb-r8a779a0     # R-Car V3U
              - renesas,etheravb-r8a779g0     # R-Car V4H
          - const: renesas,etheravb-rcar-gen4 # R-Car Gen4

      - items:
          - enum:
              - renesas,etheravb-r9a09g011 # RZ/V2M
          - const: renesas,etheravb-rzv2m  # RZ/V2M compatible

      - items:
          - enum:
              - renesas,r9a07g043-gbeth # RZ/G2UL
              - renesas,r9a07g044-gbeth # RZ/G2{L,LC}
              - renesas,r9a07g054-gbeth # RZ/V2L
          - const: renesas,rzg2l-gbeth  # RZ/{G2L,G2UL,V2L} family

  reg: true

  interrupts: true

  interrupt-names: true

  clocks: true

  clock-names: true

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  phy-mode: true

  phy-handle: true

  '#address-cells':
    description: Number of address cells for the MDIO bus.
    const: 1

  '#size-cells':
    description: Number of size cells on the MDIO bus.
    const: 0

  renesas,no-ether-link:
    type: boolean
    description:
      Specify when a board does not provide a proper AVB_LINK signal.

  renesas,ether-link-active-low:
    type: boolean
    description:
      Specify when the AVB_LINK signal is active-low instead of normal
      active-high.

  rx-internal-delay-ps:
    enum: [0, 1800]

  tx-internal-delay-ps:
    enum: [0, 2000]

patternProperties:
  "^ethernet-phy@[0-9a-f]$":
    type: object
    $ref: ethernet-phy.yaml#

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains
  - resets
  - phy-mode
  - phy-handle
  - '#address-cells'
  - '#size-cells'

allOf:
  - $ref: ethernet-controller.yaml#

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,etheravb-rcar-gen2
              - renesas,etheravb-r8a7795
              - renesas,etheravb-r8a7796
              - renesas,etheravb-r8a77961
              - renesas,etheravb-r8a77965
    then:
      properties:
        reg:
          items:
            - description: MAC register block
            - description: Stream buffer
    else:
      properties:
        reg:
          items:
            - description: MAC register block

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,etheravb-rcar-gen2
              - renesas,rzg2l-gbeth
    then:
      properties:
        interrupts:
          minItems: 1
          maxItems: 3
        interrupt-names:
          minItems: 1
          items:
            - const: mux
            - const: fil
            - const: arp_ns
        rx-internal-delay-ps: false
    else:
      if:
        properties:
          compatible:
            contains:
              const: renesas,etheravb-rzv2m
      then:
        properties:
          interrupts:
            minItems: 29
            maxItems: 29
          interrupt-names:
            items:
              pattern: '^(ch(1?)[0-9])|ch20|ch21|dia|dib|err_a|err_b|mgmt_a|mgmt_b|line3$'
          rx-internal-delay-ps: false
        required:
          - interrupt-names
      else:
        properties:
          interrupts:
            minItems: 25
            maxItems: 25
          interrupt-names:
            items:
              pattern: '^ch[0-9]+$'
        required:
          - interrupt-names
          - rx-internal-delay-ps

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,etheravb-r8a774a1
              - renesas,etheravb-r8a774b1
              - renesas,etheravb-r8a774e1
              - renesas,etheravb-r8a7795
              - renesas,etheravb-r8a7796
              - renesas,etheravb-r8a77961
              - renesas,etheravb-r8a77965
              - renesas,etheravb-r8a77970
              - renesas,etheravb-r8a77980
              - renesas,etheravb-rcar-gen4
    then:
      required:
        - tx-internal-delay-ps
    else:
      properties:
        tx-internal-delay-ps: false

  - if:
      properties:
        compatible:
          contains:
            const: renesas,etheravb-r8a77995
    then:
      properties:
        rx-internal-delay-ps:
          const: 1800

  - if:
      properties:
        compatible:
          contains:
            const: renesas,etheravb-r8a77980
    then:
      properties:
        tx-internal-delay-ps:
          const: 2000

  - if:
      properties:
        compatible:
          contains:
            const: renesas,rzg2l-gbeth
    then:
      properties:
        clocks:
          items:
            - description: Main clock
            - description: Register access clock
            - description: Reference clock for RGMII
        clock-names:
          items:
            - const: axi
            - const: chi
            - const: refclk
    else:
      if:
        properties:
          compatible:
            contains:
              const: renesas,etheravb-rzv2m
      then:
        properties:
          clocks:
            items:
              - description: Main clock
              - description: Coherent Hub Interface clock
              - description: gPTP reference clock
          clock-names:
            items:
              - const: axi
              - const: chi
              - const: gptp
      else:
        properties:
          clocks:
            minItems: 1
            items:
              - description: AVB functional clock
              - description: Optional TXC reference clock
          clock-names:
            minItems: 1
            items:
              - const: fck
              - const: refclk

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>
    #include <dt-bindings/gpio/gpio.h>
    aliases {
            ethernet0 = &avb;
    };

    avb: ethernet@e6800000 {
            compatible = "renesas,etheravb-r8a7795",
                         "renesas,etheravb-rcar-gen3";
            reg = <0xe6800000 0x800>, <0xe6a00000 0x10000>;
            interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6",
                              "ch7", "ch8", "ch9", "ch10", "ch11", "ch12",
                              "ch13", "ch14", "ch15", "ch16", "ch17", "ch18",
                              "ch19", "ch20", "ch21", "ch22", "ch23", "ch24";
            clocks = <&cpg CPG_MOD 812>;
            clock-names = "fck";
            iommus = <&ipmmu_ds0 16>;
            power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
            resets = <&cpg 812>;
            phy-mode = "rgmii";
            phy-handle = <&phy0>;
            rx-internal-delay-ps = <0>;
            tx-internal-delay-ps = <2000>;
            #address-cells = <1>;
            #size-cells = <0>;

            phy0: ethernet-phy@0 {
                    compatible = "ethernet-phy-id0022.1622",
                                 "ethernet-phy-ieee802.3-c22";
                    rxc-skew-ps = <1500>;
                    reg = <0>;
                    interrupt-parent = <&gpio2>;
                    interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
                    reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/renesas,r8a779f0-ether-switch.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Ethernet Switch

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

properties:
  compatible:
    const: renesas,r8a779f0-ether-switch

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: base
      - const: secure_base

  interrupts:
    maxItems: 47

  interrupt-names:
    items:
      - const: mfwd_error
      - const: race_error
      - const: coma_error
      - const: gwca0_error
      - const: gwca1_error
      - const: etha0_error
      - const: etha1_error
      - const: etha2_error
      - const: gptp0_status
      - const: gptp1_status
      - const: mfwd_status
      - const: race_status
      - const: coma_status
      - const: gwca0_status
      - const: gwca1_status
      - const: etha0_status
      - const: etha1_status
      - const: etha2_status
      - const: rmac0_status
      - const: rmac1_status
      - const: rmac2_status
      - const: gwca0_rxtx0
      - const: gwca0_rxtx1
      - const: gwca0_rxtx2
      - const: gwca0_rxtx3
      - const: gwca0_rxtx4
      - const: gwca0_rxtx5
      - const: gwca0_rxtx6
      - const: gwca0_rxtx7
      - const: gwca1_rxtx0
      - const: gwca1_rxtx1
      - const: gwca1_rxtx2
      - const: gwca1_rxtx3
      - const: gwca1_rxtx4
      - const: gwca1_rxtx5
      - const: gwca1_rxtx6
      - const: gwca1_rxtx7
      - const: gwca0_rxts0
      - const: gwca0_rxts1
      - const: gwca1_rxts0
      - const: gwca1_rxts1
      - const: rmac0_mdio
      - const: rmac1_mdio
      - const: rmac2_mdio
      - const: rmac0_phy
      - const: rmac1_phy
      - const: rmac2_phy

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  iommus:
    maxItems: 16

  power-domains:
    maxItems: 1

  ethernet-ports:
    type: object
    additionalProperties: false

    properties:
      '#address-cells':
        description: Port number of ETHA (TSNA).
        const: 1

      '#size-cells':
        const: 0

    patternProperties:
      "^port@[0-9a-f]+$":
        type: object
        $ref: /schemas/net/ethernet-controller.yaml#
        unevaluatedProperties: false

        properties:
          reg:
            maxItems: 1
            description:
              Port number of ETHA (TSNA).

          phys:
            maxItems: 1
            description:
              Phandle of an Ethernet SERDES.

          mdio:
            $ref: /schemas/net/mdio.yaml#
            unevaluatedProperties: false

        required:
          - reg
          - phy-handle
          - phy-mode
          - phys
          - mdio

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names
  - clocks
  - resets
  - power-domains
  - ethernet-ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a779f0-sysc.h>

    ethernet@e6880000 {
        compatible = "renesas,r8a779f0-ether-switch";
        reg = <0xe6880000 0x20000>, <0xe68c0000 0x20000>;
        reg-names = "base", "secure_base";
        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "mfwd_error", "race_error",
                          "coma_error", "gwca0_error",
                          "gwca1_error", "etha0_error",
                          "etha1_error", "etha2_error",
                          "gptp0_status", "gptp1_status",
                          "mfwd_status", "race_status",
                          "coma_status", "gwca0_status",
                          "gwca1_status", "etha0_status",
                          "etha1_status", "etha2_status",
                          "rmac0_status", "rmac1_status",
                          "rmac2_status",
                          "gwca0_rxtx0", "gwca0_rxtx1",
                          "gwca0_rxtx2", "gwca0_rxtx3",
                          "gwca0_rxtx4", "gwca0_rxtx5",
                          "gwca0_rxtx6", "gwca0_rxtx7",
                          "gwca1_rxtx0", "gwca1_rxtx1",
                          "gwca1_rxtx2", "gwca1_rxtx3",
                          "gwca1_rxtx4", "gwca1_rxtx5",
                          "gwca1_rxtx6", "gwca1_rxtx7",
                          "gwca0_rxts0", "gwca0_rxts1",
                          "gwca1_rxts0", "gwca1_rxts1",
                          "rmac0_mdio", "rmac1_mdio",
                          "rmac2_mdio",
                          "rmac0_phy", "rmac1_phy",
                          "rmac2_phy";
        clocks = <&cpg CPG_MOD 1505>;
        power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
        resets = <&cpg 1505>;

        ethernet-ports {
            #address-cells = <1>;
            #size-cells = <0>;
            port@0 {
                reg = <0>;
                phy-handle = <&eth_phy0>;
                phy-mode = "sgmii";
                phys = <&eth_serdes 0>;
                mdio {
                    #address-cells = <1>;
                    #size-cells = <0>;
                };
            };
            port@1 {
                reg = <1>;
                phy-handle = <&eth_phy1>;
                phy-mode = "sgmii";
                phys = <&eth_serdes 1>;
                mdio {
                    #address-cells = <1>;
                    #size-cells = <0>;
                };
            };
            port@2 {
                reg = <2>;
                phy-handle = <&eth_phy2>;
                phy-mode = "sgmii";
                phys = <&eth_serdes 2>;
                mdio {
                    #address-cells = <1>;
                    #size-cells = <0>;
                };
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/rockchip,emac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3036/RK3066/RK3188 Ethernet Media Access Controller (EMAC)

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    enum:
      - rockchip,rk3036-emac
      - rockchip,rk3066-emac
      - rockchip,rk3188-emac

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2
    items:
      - description: host clock
      - description: reference clock
      - description: mac TX/RX clock

  clock-names:
    minItems: 2
    items:
      - const: hclk
      - const: macref
      - const: macclk

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon GRF used to control speed and mode for the EMAC.

  phy-supply:
    description:
      Phandle to a regulator if the PHY needs one.

  mdio:
    $ref: mdio.yaml#
    unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - rockchip,grf
  - phy
  - phy-mode
  - mdio

allOf:
  - $ref: "ethernet-controller.yaml#"
  - if:
      properties:
        compatible:
          contains:
            const: rockchip,rk3036-emac

    then:
      properties:
        clocks:
          minItems: 3

        clock-names:
          minItems: 3

    else:
      properties:
        clocks:
          maxItems: 2

        clock-names:
          maxItems: 2

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3188-cru-common.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    ethernet@10204000 {
      compatible = "rockchip,rk3188-emac";
      reg = <0xc0fc2000 0x3c>;
      interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
      clock-names = "hclk", "macref";
      rockchip,grf = <&grf>;
      pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
      pinctrl-names = "default";
      phy = <&phy0>;
      phy-mode = "rmii";
      phy-supply = <&vcc_rmii>;

      mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        phy0: ethernet-phy@0 {
          reg = <1>;
        };
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/rockchip-dwmac.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Rockchip 10/100/1000 Ethernet driver(GMAC)

maintainers:
  - David Wu <david.wu@rock-chips.com>

# We need a select here so we don't match all nodes with 'snps,dwmac'
select:
  properties:
    compatible:
      contains:
        enum:
          - rockchip,px30-gmac
          - rockchip,rk3128-gmac
          - rockchip,rk3228-gmac
          - rockchip,rk3288-gmac
          - rockchip,rk3308-gmac
          - rockchip,rk3328-gmac
          - rockchip,rk3366-gmac
          - rockchip,rk3368-gmac
          - rockchip,rk3399-gmac
          - rockchip,rk3568-gmac
          - rockchip,rk3588-gmac
          - rockchip,rv1108-gmac
          - rockchip,rv1126-gmac
  required:
    - compatible

allOf:
  - $ref: "snps,dwmac.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - rockchip,px30-gmac
              - rockchip,rk3128-gmac
              - rockchip,rk3228-gmac
              - rockchip,rk3288-gmac
              - rockchip,rk3308-gmac
              - rockchip,rk3328-gmac
              - rockchip,rk3366-gmac
              - rockchip,rk3368-gmac
              - rockchip,rk3399-gmac
              - rockchip,rv1108-gmac
              - rockchip,rv1126-gmac
      - items:
          - enum:
              - rockchip,rk3568-gmac
              - rockchip,rk3588-gmac
          - const: snps,dwmac-4.20a

  clocks:
    minItems: 5
    maxItems: 8

  clock-names:
    contains:
      enum:
        - stmmaceth
        - mac_clk_tx
        - mac_clk_rx
        - aclk_mac
        - pclk_mac
        - clk_mac_ref
        - clk_mac_refout
        - clk_mac_speed

  clock_in_out:
    description:
      For RGMII, it must be "input", means main clock(125MHz)
      is not sourced from SoC's PLL, but input from PHY.
      For RMII, "input" means PHY provides the reference clock(50MHz),
      "output" means GMAC provides the reference clock.
    $ref: /schemas/types.yaml#/definitions/string
    enum: [input, output]

  rockchip,grf:
    description: The phandle of the syscon node for the general register file.
    $ref: /schemas/types.yaml#/definitions/phandle

  rockchip,php-grf:
    description:
      The phandle of the syscon node for the peripheral general register file.
    $ref: /schemas/types.yaml#/definitions/phandle

  tx_delay:
    description: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
    $ref: /schemas/types.yaml#/definitions/uint32

  rx_delay:
    description: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
    $ref: /schemas/types.yaml#/definitions/uint32

  phy-supply:
    description: PHY regulator

required:
  - compatible
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/rk3288-cru.h>

    gmac: ethernet@ff290000 {
        compatible = "rockchip,rk3288-gmac";
        reg = <0xff290000 0x10000>;
        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "macirq";
        clocks = <&cru SCLK_MAC>,
                 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
                 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
                 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
        clock-names = "stmmaceth",
                      "mac_clk_rx", "mac_clk_tx",
                      "clk_mac_ref", "clk_mac_refout",
                      "aclk_mac", "pclk_mac";
        assigned-clocks = <&cru SCLK_MAC>;
        assigned-clock-parents = <&ext_gmac>;

        rockchip,grf = <&grf>;
        phy-mode = "rgmii";
        clock_in_out = "input";
        tx_delay = <0x30>;
        rx_delay = <0x10>;
    };


code:
* Samsung 10G Ethernet driver (SXGBE)

Required properties:
- compatible: Should be "samsung,sxgbe-v2.0a"
- reg: Address and length of the register set for the device
- interrupts: Should contain the SXGBE interrupts
  These interrupts are ordered by fixed and follows variable
  trasmit DMA interrupts, receive DMA interrupts and lpi interrupt.
  index 0 - this is fixed common interrupt of SXGBE and it is always
  available.
  index 1 to 25 - 8 variable trasmit interrupts, variable 16 receive interrupts
  and 1 optional lpi interrupt.
- phy-mode: String, operation mode of the PHY interface.
  Supported values are: "sgmii", "xgmii".
- samsung,pbl: Integer, Programmable Burst Length.
  Supported values are 1, 2, 4, 8, 16, or 32.
- samsung,burst-map: Integer, Program the possible bursts supported by sxgbe
  This is an integer and represents allowable DMA bursts when fixed burst.
  Allowable range is 0x01-0x3F. When this field is set fixed burst is enabled.
  When fixed length is needed for burst mode, it can be set within allowable
  range.

Optional properties:
- max-frame-size: Maximum Transfer Unit (IEEE defined MTU), rather
		  than the maximum frame size.

The MAC address will be determined using the optional properties
defined in ethernet.txt.

Example:

	aliases {
		ethernet0 = <&sxgbe0>;
	};

	sxgbe0: ethernet@1a040000 {
		compatible = "samsung,sxgbe-v2.0a";
		reg = <0 0x1a040000 0 0x10000>;
		interrupt-parent = <&gic>;
		interrupts = <0 209 4>, <0 185 4>, <0 186 4>, <0 187 4>,
			     <0 188 4>, <0 189 4>, <0 190 4>, <0 191 4>,
			     <0 192 4>, <0 193 4>, <0 194 4>, <0 195 4>,
			     <0 196 4>, <0 197 4>, <0 198 4>, <0 199 4>,
			     <0 200 4>, <0 201 4>, <0 202 4>, <0 203 4>,
			     <0 204 4>, <0 205 4>, <0 206 4>, <0 207 4>,
			     <0 208 4>, <0 210 4>;
		samsung,pbl = <0x08>
		samsung,burst-map = <0x20>
		mac-address = [ 00 11 22 33 44 55 ]; /* Filled in by U-Boot */
		max-frame-size = <9000>;
		phy-mode = "xgmii";
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/sff,sfp.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
  Transceiver

maintainers:
  - Russell King <linux@armlinux.org.uk>

properties:
  compatible:
    enum:
      - sff,sfp  # for SFP modules
      - sff,sff  # for soldered down SFF modules

  i2c-bus:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      phandle of an I2C bus controller for the SFP two wire serial

  maximum-power-milliwatt:
    minimum: 1000
    default: 1000
    description:
      Maximum module power consumption Specifies the maximum power consumption
      allowable by a module in the slot, in milli-Watts. Presently, modules can
      be up to 1W, 1.5W or 2W.

  "mod-def0-gpios":
    maxItems: 1
    description:
      GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS) module
      presence input gpio signal, active (module absent) high. Must not be
      present for SFF modules

  "los-gpios":
    maxItems: 1
    description:
      GPIO phandle and a specifier of the Receiver Loss of Signal Indication
      input gpio signal, active (signal lost) high

  "tx-fault-gpios":
    maxItems: 1
    description:
      GPIO phandle and a specifier of the Module Transmitter Fault input gpio
      signal, active (fault condition) high

  "tx-disable-gpios":
    maxItems: 1
    description:
      GPIO phandle and a specifier of the Transmitter Disable output gpio
      signal, active (Tx disable) high

  "rate-select0-gpios":
    maxItems: 1
    description:
      GPIO phandle and a specifier of the Rx Signaling Rate Select (AKA RS0)
      output gpio signal, low - low Rx rate, high - high Rx rate Must not be
      present for SFF modules

  "rate-select1-gpios":
    maxItems: 1
    description:
      GPIO phandle and a specifier of the Tx Signaling Rate Select (AKA RS1)
      output gpio signal (SFP+ only), low - low Tx rate, high - high Tx rate. Must
      not be present for SFF modules

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: sff,sff
    then:
      properties:
        mod-def0-gpios: false
        rate-select0-gpios: false
        rate-select1-gpios: false

required:
  - compatible
  - i2c-bus

additionalProperties: false

examples:
  - | # Direct serdes to SFP connection
    #include <dt-bindings/gpio/gpio.h>

    sfp1: sfp {
      compatible = "sff,sfp";
      i2c-bus = <&sfp_1g_i2c>;
      los-gpios = <&cpm_gpio2 22 GPIO_ACTIVE_HIGH>;
      mod-def0-gpios = <&cpm_gpio2 21 GPIO_ACTIVE_LOW>;
      maximum-power-milliwatt = <1000>;
      pinctrl-names = "default";
      pinctrl-0 = <&cpm_sfp_1g_pins &cps_sfp_1g_pins>;
      tx-disable-gpios = <&cps_gpio1 24 GPIO_ACTIVE_HIGH>;
      tx-fault-gpios = <&cpm_gpio2 19 GPIO_ACTIVE_HIGH>;
    };

    ethernet {
      phy-names = "comphy";
      phys = <&cps_comphy5 0>;
      sfp = <&sfp1>;
    };

  - | # Serdes to PHY to SFP connection
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    sfp2: sfp {
      compatible = "sff,sfp";
      i2c-bus = <&sfp_i2c>;
      los-gpios = <&cps_gpio1 28 GPIO_ACTIVE_HIGH>;
      mod-def0-gpios = <&cps_gpio1 27 GPIO_ACTIVE_LOW>;
      pinctrl-names = "default";
      pinctrl-0 = <&cps_sfpp0_pins>;
      tx-disable-gpios = <&cps_gpio1 29 GPIO_ACTIVE_HIGH>;
      tx-fault-gpios  = <&cps_gpio1 26 GPIO_ACTIVE_HIGH>;
    };

    mdio {
      #address-cells = <1>;
      #size-cells = <0>;

      phy: ethernet-phy@0 {
        compatible = "ethernet-phy-ieee802.3-c45";
        pinctrl-names = "default";
        pinctrl-0 = <&cpm_phy0_pins &cps_phy0_pins>;
        reg = <0>;
        interrupt = <&cpm_gpio2 18 IRQ_TYPE_EDGE_FALLING>;
        sfp = <&sfp2>;
      };
    };

    ethernet {
      phy = <&phy>;
      phy-mode = "10gbase-kr";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/smsc,lan9115.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller

maintainers:
  - Shawn Guo <shawnguo@kernel.org>

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    oneOf:
      - const: smsc,lan9115
      - items:
          - enum:
              - smsc,lan89218
              - smsc,lan9117
              - smsc,lan9118
              - smsc,lan9220
              - smsc,lan9221
          - const: smsc,lan9115

  reg:
    maxItems: 1

  reg-shift: true

  reg-io-width:
    enum: [ 2, 4 ]
    default: 2

  interrupts:
    minItems: 1
    items:
      - description:
          LAN interrupt line
      - description:
          Optional PME (power management event) interrupt that is able to wake
          up the host system with a 50ms pulse on network activity

  clocks:
    maxItems: 1

  phy-mode: true

  smsc,irq-active-high:
    type: boolean
    description: Indicates the IRQ polarity is active-high

  smsc,irq-push-pull:
    type: boolean
    description: Indicates the IRQ type is push-pull

  smsc,force-internal-phy:
    type: boolean
    description: Forces SMSC LAN controller to use internal PHY

  smsc,force-external-phy:
    type: boolean
    description: Forces SMSC LAN controller to use external PHY

  smsc,save-mac-address:
    type: boolean
    description:
      Indicates that MAC address needs to be saved before resetting the
      controller

  reset-gpios:
    maxItems: 1
    description:
      A GPIO line connected to the RESET (active low) signal of the device.
      On many systems this is wired high so the device goes out of reset at
      power-on, but if it is under program control, this optional GPIO can
      wake up in response to it.

  vdd33a-supply:
    description: 3.3V analog power supply

  vddvario-supply:
    description: IO logic power supply

required:
  - compatible
  - reg
  - interrupts

# There are lots of bus-specific properties ("qcom,*", "samsung,*", "fsl,*",
# "gpmc,*", ...) to be found, that actually depend on the compatible value of
# the parent node.
additionalProperties: true

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    ethernet@f4000000 {
            compatible = "smsc,lan9220", "smsc,lan9115";
            reg = <0xf4000000 0x2000000>;
            phy-mode = "mii";
            interrupt-parent = <&gpio1>;
            interrupts = <31>, <32>;
            reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
            reg-io-width = <4>;
            smsc,irq-push-pull;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/smsc,lan91c111.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller

maintainers:
  - Nicolas Pitre <nico@fluxnic.net>

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    const: smsc,lan91c111

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  reg-shift: true

  reg-io-width:
    enum: [ 1, 2, 4 ]
    default: 4

  reset-gpios:
    description: GPIO connected to control RESET pin
    maxItems: 1

  power-gpios:
    description: GPIO connect to control PWRDWN pin
    maxItems: 1

  pxa-u16-align4:
    description: put in place the workaround the force all u16 writes to be
      32 bits aligned
    type: boolean

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    ethernet@4010000 {
          compatible = "smsc,lan91c111";
          reg = <0x40100000 0x10000>;
          phy-mode = "mii";
          interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
          reg-io-width = <2>;
    };