code:
/*
 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>

/ {
	aliases {
		can0 = &can2;
		can1 = &can1;
		display = &display;
		i2c0 = &i2c2;
		i2c1 = &i2c_gpio;
		i2c2 = &i2c1;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		lcdif-23bit-pins-a = &pinctrl_disp0_1;
		lcdif-24bit-pins-a = &pinctrl_disp0_2;
		pwm0 = &pwm5;
		reg-can-xcvr = &reg_can_xcvr;
		serial2 = &uart5;
		serial4 = &uart3;
		spi0 = &ecspi2;
		spi1 = &spi_gpio;
		stk5led = &user_led;
		usbh1 = &usbotg2;
		usbotg = &usbotg1;
	};

	chosen {
		stdout-path = &uart1;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0>; /* will be filled by U-Boot */
	};

	clocks {
		mclk: mclk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
		};
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lcd_rst>;
		enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
		pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
		power-supply = <&reg_lcd_pwr>;
		/*
		 * a poor man's way to create a 1:1 relationship between
		 * the PWM value and the actual duty cycle
		 */
		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <50>;
	};

	i2c_gpio: i2c-gpio {
		compatible = "i2c-gpio";
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c_gpio>;
		gpios = <
			&gpio5 1 GPIO_ACTIVE_HIGH /* SDA */
			&gpio5 0 GPIO_ACTIVE_HIGH /* SCL */
		>;
		clock-frequency = <400000>;
		status = "okay";

		ds1339: rtc@68 {
			compatible = "dallas,ds1339";
			reg = <0x68>;
			status = "disabled";
		};
	};

	leds {
		compatible = "gpio-leds";

		user_led: user {
			label = "Heartbeat";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_led>;
			gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	reg_3v3_etn: regulator-3v3etn {
		compatible = "regulator-fixed";
		regulator-name = "3V3_ETN";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_etnphy_power>;
		gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_2v5: regulator-2v5 {
		compatible = "regulator-fixed";
		regulator-name = "2V5";
		regulator-min-microvolt = <2500000>;
		regulator-max-microvolt = <2500000>;
		regulator-always-on;
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_can_xcvr: regulator-canxcvr {
		compatible = "regulator-fixed";
		regulator-name = "CAN XCVR";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_flexcan_xcvr>;
		gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
	};

	reg_lcd_pwr: regulator-lcdpwr {
		compatible = "regulator-fixed";
		regulator-name = "LCD POWER";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lcd_pwr>;
		gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_usbh1_vbus: regulator-usbh1vbus {
		compatible = "regulator-fixed";
		regulator-name = "usbh1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
		gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usbotg_vbus: regulator-usbotgvbus {
		compatible = "regulator-fixed";
		regulator-name = "usbotg_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	spi_gpio: spi {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "spi-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_spi_gpio>;
		gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>;
		gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>;
		gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
		num-chipselects = <2>;
		cs-gpios = <
			&gpio1 29 GPIO_ACTIVE_HIGH
			&gpio1 10 GPIO_ACTIVE_HIGH
		>;
		status = "disabled";
	};

	sound {
		compatible = "karo,imx6ul-tx6ul-sgtl5000",
			     "simple-audio-card";
		simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&codec_dai>;
		simple-audio-card,frame-master = <&codec_dai>;
		simple-audio-card,widgets =
			"Microphone", "Mic Jack",
			"Line", "Line In",
			"Line", "Line Out",
			"Headphone", "Headphone Jack";
		simple-audio-card,routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";

		cpu_dai: simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};

		codec_dai: simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
		};
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can_xcvr>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can_xcvr>;
	status = "okay";
};

&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	cs-gpios = <
		&gpio1 29 GPIO_ACTIVE_HIGH
		&gpio1 10 GPIO_ACTIVE_HIGH
	>;
	status = "disabled";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
	phy-mode = "rmii";
	phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
	phy-supply = <&reg_3v3_etn>;
	phy-handle = <&etnphy0>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		etnphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_etnphy0_int>;
			interrupt-parent = <&gpio5>;
			interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
			status = "okay";
		};

		etnphy1: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <2>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_etnphy1_int>;
			interrupt-parent = <&gpio4>;
			interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
			status = "okay";
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
	phy-mode = "rmii";
	phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
	phy-supply = <&reg_3v3_etn>;
	phy-handle = <&etnphy1>;
	status = "disabled";
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	fsl,no-blockmark-swap;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clock-frequency = <400000>;
	status = "okay";

	sgtl5000: codec@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		#sound-dai-cells = <0>;
		VDDA-supply = <&reg_2v5>;
		VDDIO-supply = <&reg_3v3>;
		clocks = <&mclk>;
	};

	polytouch: polytouch@38 {
		compatible = "edt,edt-ft5x06";
		reg = <0x38>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_edt_ft5x06>;
		interrupt-parent = <&gpio5>;
		interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
		reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
		wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
		wakeup-source;
	};

	touchscreen: touchscreen@48 {
		compatible = "ti,tsc2007";
		reg = <0x48>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tsc2007>;
		interrupt-parent = <&gpio3>;
		interrupts = <26 IRQ_TYPE_NONE>;
		gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
		ti,x-plate-ohms = <660>;
		wakeup-source;
	};
};

&kpp {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_kpp>;
	/* sample keymap */
	/* row/col 0..3 are mapped to KPP row/col 4..7 */
	linux,keymap = <
		MATRIX_KEY(4, 4, KEY_POWER)
		MATRIX_KEY(4, 5, KEY_KP0)
		MATRIX_KEY(4, 6, KEY_KP1)
		MATRIX_KEY(4, 7, KEY_KP2)
		MATRIX_KEY(5, 4, KEY_KP3)
		MATRIX_KEY(5, 5, KEY_KP4)
		MATRIX_KEY(5, 6, KEY_KP5)
		MATRIX_KEY(5, 7, KEY_KP6)
		MATRIX_KEY(6, 4, KEY_KP7)
		MATRIX_KEY(6, 5, KEY_KP8)
		MATRIX_KEY(6, 6, KEY_KP9)
	>;
	status = "okay";
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_disp0_1>;
	lcd-supply = <&reg_lcd_pwr>;
	display = <&display>;
	status = "okay";

	display: disp0 {
		bits-per-pixel = <32>;
		bus-width = <24>;
		status = "okay";

		display-timings {
			VGA {
				clock-frequency = <25200000>;
				hactive = <640>;
				vactive = <480>;
				hback-porch = <48>;
				hsync-len = <96>;
				hfront-porch = <16>;
				vback-porch = <31>;
				vsync-len = <2>;
				vfront-porch = <12>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <1>;
			};

			ETV570 {
				clock-frequency = <25200000>;
				hactive = <640>;
				vactive = <480>;
				hback-porch = <114>;
				hsync-len = <30>;
				hfront-porch = <16>;
				vback-porch = <32>;
				vsync-len = <3>;
				vfront-porch = <10>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <1>;
			};

			ET0350 {
				clock-frequency = <6413760>;
				hactive = <320>;
				vactive = <240>;
				hback-porch = <34>;
				hsync-len = <34>;
				hfront-porch = <20>;
				vback-porch = <15>;
				vsync-len = <3>;
				vfront-porch = <4>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <1>;
			};

			ET0430 {
				clock-frequency = <9009000>;
				hactive = <480>;
				vactive = <272>;
				hback-porch = <2>;
				hsync-len = <41>;
				hfront-porch = <2>;
				vback-porch = <2>;
				vsync-len = <10>;
				vfront-porch = <2>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};

			ET0500 {
				clock-frequency = <33264000>;
				hactive = <800>;
				vactive = <480>;
				hback-porch = <88>;
				hsync-len = <128>;
				hfront-porch = <40>;
				vback-porch = <33>;
				vsync-len = <2>;
				vfront-porch = <10>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <1>;
			};

			ET0700 { /* same as ET0500 */
				clock-frequency = <33264000>;
				hactive = <800>;
				vactive = <480>;
				hback-porch = <88>;
				hsync-len = <128>;
				hfront-porch = <40>;
				vback-porch = <33>;
				vsync-len = <2>;
				vfront-porch = <10>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <1>;
			};

			ETQ570 {
				clock-frequency = <6596040>;
				hactive = <320>;
				vactive = <240>;
				hback-porch = <38>;
				hsync-len = <30>;
				hfront-porch = <30>;
				vback-porch = <16>;
				vsync-len = <3>;
				vfront-porch = <4>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <1>;
			};
		};
	};
};

&pwm5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm5>;
	status = "okay";
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
	uart-has-rtscts;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
	uart-has-rtscts;
	status = "okay";
};

&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
	uart-has-rtscts;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usbotg_vbus>;
	dr_mode = "peripheral";
	disable-over-current;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usbh1_vbus>;
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
	bus-width = <4>;
	no-1-8-v;
	cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
	fsl,wp-controller;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
	};

	pinctrl_led: ledgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x0b0b0 /* LED */
		>;
	};

	pinctrl_disp0_1: disp0grp-1 {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x10 /* LSCLK */
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x10 /* OE_ACD */
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x10 /* HSYNC */
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x10 /* VSYNC */
			/* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01	0x10
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x10
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x10
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x10
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x10
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x10
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x10
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08	0x10
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09	0x10
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x10
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x10
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x10
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x10
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x10
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x10
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16	0x10
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17	0x10
			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x10
			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x10
			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x10
			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x10
			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x10
			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x10
		>;
	};

	pinctrl_disp0_2: disp0grp-2 {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x10 /* LSCLK */
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x10 /* OE_ACD */
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x10 /* HSYNC */
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x10 /* VSYNC */
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00	0x10
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01	0x10
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x10
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x10
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x10
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x10
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x10
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x10
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08	0x10
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09	0x10
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x10
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x10
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x10
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x10
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x10
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x10
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16	0x10
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17	0x10
			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18	0x10
			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19	0x10
			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20	0x10
			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21	0x10
			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22	0x10
			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23	0x10
		>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x0b0b0 /* CSPI_SS */
			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x0b0b0 /* CSPI_SS */
			MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI	0x0b0b0 /* CSPI_MOSI */
			MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO	0x0b0b0 /* CSPI_MISO */
			MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK	0x0b0b0 /* CSPI_SCLK */
		>;
	};

	pinctrl_edt_ft5x06: edt-ft5x06grp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0 /* Interrupt */
			MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x1b0b0 /* Reset */
			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x1b0b0 /* Wake */
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x000b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x000b0
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x000b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x000b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x000b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x000b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x000b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x400000b1
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x000b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x000b0
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x000b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x000b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x000b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x000b0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x000b0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x400000b1
		>;
	};

	pinctrl_enet1_mdio: enet1-mdiogrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x0b0b0
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
		>;
	};

	pinctrl_etnphy_power: etnphy-pwrgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x0b0b0 /* ETN PHY POWER */
		>;
	};

	pinctrl_etnphy0_int: etnphy-intgrp-0 {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x0b0b0 /* ETN PHY INT */
		>;
	};

	pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x0b0b0 /* ETN PHY RESET */
		>;
	};

	pinctrl_etnphy1_int: etnphy-intgrp-1 {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA06__GPIO4_IO27	0x0b0b0 /* ETN PHY INT */
		>;
	};

	pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA07__GPIO4_IO28	0x0b0b0 /* ETN PHY RESET */
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x0b0b0
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x0b0b0
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x0b0b0
			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x0b0b0
		>;
	};

	pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__GPIO3_IO05	0x0b0b0 /* Flexcan XCVR enable */
		>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x0b0b1
			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x0b0b1
			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0x0b0b1
			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x0b000
			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x0b0b1
			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x0b0b1
			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x0b0b1
			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x0b0b1
			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x0b0b1
			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x0b0b1
			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x0b0b1
			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x0b0b1
			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x0b0b1
			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x0b0b1
			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x0b0b1
		>;
	};

	pinctrl_i2c_gpio: i2c-gpiogrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x4001b8b1 /* I2C SCL */
			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x4001b8b1 /* I2C SDA */
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__I2C2_SCL		0x4001b8b1
			MX6UL_PAD_GPIO1_IO01__I2C2_SDA		0x4001b8b1
		>;
	};

	pinctrl_kpp: kppgrp {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__KPP_COL06	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__KPP_COL07	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04	0x1b0b0
			MX6UL_PAD_ENET2_RX_EN__KPP_ROW05	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07	0x1b0b0
		>;
	};

	pinctrl_lcd_pwr: lcd-pwrgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x0b0b0 /* LCD Power Enable */
		>;
	};

	pinctrl_lcd_rst: lcd-rstgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_RESET__GPIO3_IO04	0x0b0b0 /* LCD Reset */
		>;
	};

	pinctrl_pwm5: pwm5grp {
		fsl,pins = <
			MX6UL_PAD_NAND_DQS__PWM5_OUT		0x0b0b0
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x0b0b0 /* SSI1_RXD */
			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x0b0b0 /* SSI1_TXD */
			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x0b0b0 /* SSI1_CLK */
			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x0b0b0 /* SSI1_FS */
		>;
	};

	pinctrl_spi_gpio: spi-gpiogrp {
		fsl,pins = <
			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29	0x0b0b0 /* CSPI_SS */
			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x0b0b0 /* CSPI_SS */
			MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30	0x0b0b0 /* CSPI_MOSI */
			MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31	0x0b0b0 /* CSPI_MISO */
			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28	0x0b0b0 /* CSPI_SCLK */
		>;
	};

	pinctrl_tsc2007: tsc2007grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TMS__GPIO1_IO11		0x1b0b0 /* Interrupt */
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x0b0b0
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x0b0b0
		>;
	};

	pinctrl_uart1_rtscts: uart1-rtsctsgrp {
		fsl,pins = <
			MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS	0x0b0b0
			MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS	0x0b0b0
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x0b0b0
			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x0b0b0
		>;
	};

	pinctrl_uart2_rtscts: uart2-rtsctsgrp {
		fsl,pins = <
			MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x0b0b0
			MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x0b0b0
		>;
	};

	pinctrl_uart5: uart5grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX	0x0b0b0
			MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX	0x0b0b0
		>;
	};

	pinctrl_uart5_rtscts: uart5-rtsctsgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x0b0b0
			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x0b0b0
		>;
	};

	pinctrl_usbh1_oc: usbh1-ocgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x17059 /* USBH1_OC */
		>;
	};

	pinctrl_usbh1_vbus: usbh1-vbusgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0x0b0b0 /* USBH1_VBUSEN */
		>;
	};

	pinctrl_usbotg_oc: usbotg-ocgrp {
		fsl,pins = <
			MX6UL_PAD_UART3_RTS_B__GPIO1_IO27	0x17059 /* USBOTG_OC */
		>;
	};

	pinctrl_usbotg_vbus: usbotg-vbusgrp {
		fsl,pins = <
			MX6UL_PAD_UART3_CTS_B__GPIO1_IO26	0x1b0b0 /* USBOTG_VBUSEN */
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x070b1
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x07099
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x070b1
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x070b1
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x070b1
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x070b1
		>;
	};

	pinctrl_usdhc1_cd: usdhc1cdgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x170b0 /* SD1 CD */
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x070b1
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x070b1
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x070b1
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x070b1
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x070b1
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x070b1
			/* eMMC RESET */
			MX6UL_PAD_NAND_ALE__USDHC2_RESET_B	0x170b0
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2015 Freescale Semiconductor, Inc.

#include <dt-bindings/clock/imx6ul-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6ul-pinfunc.h"

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 */
	chosen {};

	aliases {
		ethernet0 = &fec1;
		ethernet1 = &fec2;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		serial6 = &uart7;
		serial7 = &uart8;
		sai1 = &sai1;
		sai2 = &sai2;
		sai3 = &sai3;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &ecspi3;
		spi3 = &ecspi4;
		usb0 = &usbotg1;
		usb1 = &usbotg2;
		usbphy0 = &usbphy1;
		usbphy1 = &usbphy2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			clock-frequency = <696000000>;
			clock-latency = <61036>; /* two CLK32 periods */
			#cooling-cells = <2>;
			operating-points =
				/* kHz	uV */
				<696000	1275000>,
				<528000	1175000>,
				<396000	1025000>,
				<198000	950000>;
			fsl,soc-operating-points =
				/* KHz	uV */
				<696000	1275000>,
				<528000	1175000>,
				<396000	1175000>,
				<198000	1175000>;
			clocks = <&clks IMX6UL_CLK_ARM>,
				 <&clks IMX6UL_CLK_PLL2_BUS>,
				 <&clks IMX6UL_CLK_PLL2_PFD2>,
				 <&clks IMX6UL_CA7_SECONDARY_SEL>,
				 <&clks IMX6UL_CLK_STEP>,
				 <&clks IMX6UL_CLK_PLL1_SW>,
				 <&clks IMX6UL_CLK_PLL1_SYS>;
			clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
				      "secondary_sel", "step", "pll1_sw",
				      "pll1_sys";
			arm-supply = <&reg_arm>;
			soc-supply = <&reg_soc>;
			nvmem-cells = <&cpu_speed_grade>;
			nvmem-cell-names = "speed_grade";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&intc>;
		status = "disabled";
	};

	ckil: clock-cli {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "ckil";
	};

	osc: clock-osc {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc";
	};

	ipp_di0: clock-di0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "ipp_di0";
	};

	ipp_di1: clock-di1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "ipp_di1";
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupt-parent = <&gpc>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gpc>;
		ranges;

		ocram: sram@900000 {
			compatible = "mmio-sram";
			reg = <0x00900000 0x20000>;
			ranges = <0 0x00900000 0x20000>;
			#address-cells = <1>;
			#size-cells = <1>;
		};

		intc: interrupt-controller@a01000 {
			compatible = "arm,gic-400", "arm,cortex-a7-gic";
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupt-parent = <&intc>;
			reg = <0x00a01000 0x1000>,
			      <0x00a02000 0x2000>,
			      <0x00a04000 0x2000>,
			      <0x00a06000 0x2000>;
		};

		dma_apbh: dma-apbh@1804000 {
			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
			reg = <0x01804000 0x2000>;
			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
				     <0 13 IRQ_TYPE_LEVEL_HIGH>,
				     <0 13 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
			#dma-cells = <1>;
			dma-channels = <4>;
			clocks = <&clks IMX6UL_CLK_APBHDMA>;
		};

		gpmi: nand-controller@1806000 {
			compatible = "fsl,imx6q-gpmi-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
			reg-names = "gpmi-nand", "bch";
			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "bch";
			clocks = <&clks IMX6UL_CLK_GPMI_IO>,
				 <&clks IMX6UL_CLK_GPMI_APB>,
				 <&clks IMX6UL_CLK_GPMI_BCH>,
				 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
				 <&clks IMX6UL_CLK_PER_BCH>;
			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
				      "gpmi_bch_apb", "per1_bch";
			dmas = <&dma_apbh 0>;
			dma-names = "rx-tx";
			status = "disabled";
		};

		aips1: bus@2000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02000000 0x100000>;
			ranges;

			spba-bus@2000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x02000000 0x40000>;
				ranges;

				ecspi1: spi@2008000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
					reg = <0x02008000 0x4000>;
					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_ECSPI1>,
						 <&clks IMX6UL_CLK_ECSPI1>;
					clock-names = "ipg", "per";
					dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi2: spi@200c000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
					reg = <0x0200c000 0x4000>;
					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_ECSPI2>,
						 <&clks IMX6UL_CLK_ECSPI2>;
					clock-names = "ipg", "per";
					dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi3: spi@2010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
					reg = <0x02010000 0x4000>;
					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_ECSPI3>,
						 <&clks IMX6UL_CLK_ECSPI3>;
					clock-names = "ipg", "per";
					dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ecspi4: spi@2014000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
					reg = <0x02014000 0x4000>;
					interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_ECSPI4>,
						 <&clks IMX6UL_CLK_ECSPI4>;
					clock-names = "ipg", "per";
					dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				uart7: serial@2018000 {
					compatible = "fsl,imx6ul-uart",
						     "fsl,imx6q-uart";
					reg = <0x02018000 0x4000>;
					interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_UART7_IPG>,
						 <&clks IMX6UL_CLK_UART7_SERIAL>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				uart1: serial@2020000 {
					compatible = "fsl,imx6ul-uart",
						     "fsl,imx6q-uart";
					reg = <0x02020000 0x4000>;
					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_UART1_IPG>,
						 <&clks IMX6UL_CLK_UART1_SERIAL>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				uart8: serial@2024000 {
					compatible = "fsl,imx6ul-uart",
						     "fsl,imx6q-uart";
					reg = <0x02024000 0x4000>;
					interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_UART8_IPG>,
						 <&clks IMX6UL_CLK_UART8_SERIAL>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				sai1: sai@2028000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
					reg = <0x02028000 0x4000>;
					interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
						 <&clks IMX6UL_CLK_SAI1>,
						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
					clock-names = "bus", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma 35 24 0>,
					       <&sdma 36 24 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				sai2: sai@202c000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
					reg = <0x0202c000 0x4000>;
					interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
						 <&clks IMX6UL_CLK_SAI2>,
						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
					clock-names = "bus", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma 37 24 0>,
					       <&sdma 38 24 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				sai3: sai@2030000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
					reg = <0x02030000 0x4000>;
					interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
						 <&clks IMX6UL_CLK_SAI3>,
						 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
					clock-names = "bus", "mclk1", "mclk2", "mclk3";
					dmas = <&sdma 39 24 0>,
					       <&sdma 40 24 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				asrc: asrc@2034000 {
					compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc";
					reg = <0x2034000 0x4000>;
					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
						<&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
						<&clks IMX6UL_CLK_SPBA>;
					clock-names = "mem", "ipg", "asrck_0",
						"asrck_1", "asrck_2", "asrck_3", "asrck_4",
						"asrck_5", "asrck_6", "asrck_7", "asrck_8",
						"asrck_9", "asrck_a", "asrck_b", "asrck_c",
						"asrck_d", "asrck_e", "asrck_f", "spba";
					dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
						<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
					dma-names = "rxa", "rxb", "rxc",
						    "txa", "txb", "txc";
					fsl,asrc-rate  = <48000>;
					fsl,asrc-width = <16>;
					status = "okay";
				};
			};

			tsc: tsc@2040000 {
				compatible = "fsl,imx6ul-tsc";
				reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_IPG>,
					 <&clks IMX6UL_CLK_ADC2>;
				clock-names = "tsc", "adc";
				status = "disabled";
			};

			pwm1: pwm@2080000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x02080000 0x4000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_PWM1>,
					 <&clks IMX6UL_CLK_PWM1>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm2: pwm@2084000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x02084000 0x4000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_PWM2>,
					 <&clks IMX6UL_CLK_PWM2>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm3: pwm@2088000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x02088000 0x4000>;
				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_PWM3>,
					 <&clks IMX6UL_CLK_PWM3>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm4: pwm@208c000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x0208c000 0x4000>;
				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_PWM4>,
					 <&clks IMX6UL_CLK_PWM4>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			can1: can@2090000 {
				compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
				reg = <0x02090000 0x4000>;
				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
					 <&clks IMX6UL_CLK_CAN1_SERIAL>;
				clock-names = "ipg", "per";
				fsl,stop-mode = <&gpr 0x10 1>;
				status = "disabled";
			};

			can2: can@2094000 {
				compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
				reg = <0x02094000 0x4000>;
				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
					 <&clks IMX6UL_CLK_CAN2_SERIAL>;
				clock-names = "ipg", "per";
				fsl,stop-mode = <&gpr 0x10 2>;
				status = "disabled";
			};

			gpt1: timer@2098000 {
				compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
				reg = <0x02098000 0x4000>;
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
					 <&clks IMX6UL_CLK_GPT1_SERIAL>;
				clock-names = "ipg", "per";
			};

			gpio1: gpio@209c000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x0209c000 0x4000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_GPIO1>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
					      <&iomuxc 16 33 16>;
			};

			gpio2: gpio@20a0000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x020a0000 0x4000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_GPIO2>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
			};

			gpio3: gpio@20a4000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x020a4000 0x4000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_GPIO3>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 65 29>;
			};

			gpio4: gpio@20a8000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x020a8000 0x4000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_GPIO4>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
			};

			gpio5: gpio@20ac000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x020ac000 0x4000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_GPIO5>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
			};

			fec2: ethernet@20b4000 {
				compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
				reg = <0x020b4000 0x4000>;
				interrupt-names = "int0", "pps";
				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_ENET>,
					 <&clks IMX6UL_CLK_ENET_AHB>,
					 <&clks IMX6UL_CLK_ENET_PTP>,
					 <&clks IMX6UL_CLK_ENET2_REF_125M>,
					 <&clks IMX6UL_CLK_ENET2_REF_125M>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				fsl,num-tx-queues = <1>;
				fsl,num-rx-queues = <1>;
				fsl,stop-mode = <&gpr 0x10 4>;
				fsl,magic-packet;
				status = "disabled";
			};

			kpp: keypad@20b8000 {
				compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp";
				reg = <0x020b8000 0x4000>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_KPP>;
				status = "disabled";
			};

			wdog1: watchdog@20bc000 {
				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
				reg = <0x020bc000 0x4000>;
				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_WDOG1>;
			};

			wdog2: watchdog@20c0000 {
				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
				reg = <0x020c0000 0x4000>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_WDOG2>;
				status = "disabled";
			};

			clks: clock-controller@20c4000 {
				compatible = "fsl,imx6ul-ccm";
				reg = <0x020c4000 0x4000>;
				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
				#clock-cells = <1>;
				clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
				clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
			};

			anatop: anatop@20c8000 {
				compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
					     "syscon", "simple-mfd";
				reg = <0x020c8000 0x1000>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

				reg_3p0: regulator-3p0 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd3p0";
					regulator-min-microvolt = <2625000>;
					regulator-max-microvolt = <3400000>;
					anatop-reg-offset = <0x120>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
					anatop-min-voltage = <2625000>;
					anatop-max-voltage = <3400000>;
					anatop-enable-bit = <0>;
				};

				reg_arm: regulator-vddcore {
					compatible = "fsl,anatop-regulator";
					regulator-name = "cpu";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <0>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <24>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				reg_soc: regulator-vddsoc {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddsoc";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <18>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <28>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				tempmon: tempmon {
					compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
					interrupt-parent = <&gpc>;
					interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
					fsl,tempmon = <&anatop>;
					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
					nvmem-cell-names = "calib", "temp_grade";
					clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
				};
			};

			usbphy1: usbphy@20c9000 {
				compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
				reg = <0x020c9000 0x1000>;
				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_USBPHY1>;
				phy-3p0-supply = <&reg_3p0>;
				fsl,anatop = <&anatop>;
			};

			usbphy2: usbphy@20ca000 {
				compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
				reg = <0x020ca000 0x1000>;
				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_USBPHY2>;
				phy-3p0-supply = <&reg_3p0>;
				fsl,anatop = <&anatop>;
			};

			snvs: snvs@20cc000 {
				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
				reg = <0x020cc000 0x4000>;

				snvs_rtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap = <&snvs>;
					offset = <0x34>;
					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				};

				snvs_poweroff: snvs-poweroff {
					compatible = "syscon-poweroff";
					regmap = <&snvs>;
					offset = <0x38>;
					value = <0x60>;
					mask = <0x60>;
					status = "disabled";
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
					linux,keycode = <KEY_POWER>;
					wakeup-source;
					status = "disabled";
				};

				snvs_lpgpr: snvs-lpgpr {
					compatible = "fsl,imx6ul-snvs-lpgpr";
				};
			};

			epit1: epit@20d0000 {
				reg = <0x020d0000 0x4000>;
				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			epit2: epit@20d4000 {
				reg = <0x020d4000 0x4000>;
				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			};

			src: reset-controller@20d8000 {
				compatible = "fsl,imx6ul-src", "fsl,imx51-src";
				reg = <0x020d8000 0x4000>;
				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};

			gpc: gpc@20dc000 {
				compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
				reg = <0x020dc000 0x4000>;
				interrupt-controller;
				#interrupt-cells = <3>;
				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-parent = <&intc>;
			};

			iomuxc: pinctrl@20e0000 {
				compatible = "fsl,imx6ul-iomuxc";
				reg = <0x020e0000 0x4000>;
			};

			gpr: iomuxc-gpr@20e4000 {
				compatible = "fsl,imx6ul-iomuxc-gpr",
					     "fsl,imx6q-iomuxc-gpr", "syscon";
				reg = <0x020e4000 0x4000>;
			};

			gpt2: timer@20e8000 {
				compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
				reg = <0x020e8000 0x4000>;
				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
					 <&clks IMX6UL_CLK_GPT2_SERIAL>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			sdma: dma-controller@20ec000 {
				compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
					     "fsl,imx35-sdma";
				reg = <0x020ec000 0x4000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_IPG>,
					 <&clks IMX6UL_CLK_SDMA>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
			};

			pwm5: pwm@20f0000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x020f0000 0x4000>;
				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_PWM5>,
					 <&clks IMX6UL_CLK_PWM5>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm6: pwm@20f4000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x020f4000 0x4000>;
				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_PWM6>,
					 <&clks IMX6UL_CLK_PWM6>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm7: pwm@20f8000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x020f8000 0x4000>;
				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_PWM7>,
					 <&clks IMX6UL_CLK_PWM7>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm8: pwm@20fc000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x020fc000 0x4000>;
				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_PWM8>,
					 <&clks IMX6UL_CLK_PWM8>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};
		};

		aips2: bus@2100000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02100000 0x100000>;
			ranges;

			crypto: crypto@2140000 {
				compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x2140000 0x3c000>;
				ranges = <0 0x2140000 0x3c000>;
				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
					 <&clks IMX6UL_CLK_CAAM_MEM>;
				clock-names = "ipg", "aclk", "mem";

				sec_jr0: jr@1000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x1000 0x1000>;
					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr1: jr@2000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x2000 0x1000>;
					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr2: jr@3000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x3000 0x1000>;
					interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			usbotg1: usb@2184000 {
				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
				reg = <0x02184000 0x200>;
				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_USBOH3>;
				fsl,usbphy = <&usbphy1>;
				fsl,usbmisc = <&usbmisc 0>;
				fsl,anatop = <&anatop>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbotg2: usb@2184200 {
				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
				reg = <0x02184200 0x200>;
				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_USBOH3>;
				fsl,usbphy = <&usbphy2>;
				fsl,usbmisc = <&usbmisc 1>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbmisc: usbmisc@2184800 {
				#index-cells = <1>;
				compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
				reg = <0x02184800 0x200>;
			};

			fec1: ethernet@2188000 {
				compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
				reg = <0x02188000 0x4000>;
				interrupt-names = "int0", "pps";
				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_ENET>,
					 <&clks IMX6UL_CLK_ENET_AHB>,
					 <&clks IMX6UL_CLK_ENET_PTP>,
					 <&clks IMX6UL_CLK_ENET_REF>,
					 <&clks IMX6UL_CLK_ENET_REF>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				fsl,num-tx-queues = <1>;
				fsl,num-rx-queues = <1>;
				fsl,stop-mode = <&gpr 0x10 3>;
				fsl,magic-packet;
				status = "disabled";
			};

			usdhc1: mmc@2190000 {
				compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
				reg = <0x02190000 0x4000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_USDHC1>,
					 <&clks IMX6UL_CLK_USDHC1>,
					 <&clks IMX6UL_CLK_USDHC1>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-step = <2>;
				fsl,tuning-start-tap = <20>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@2194000 {
				compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
				reg = <0x02194000 0x4000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_USDHC2>,
					 <&clks IMX6UL_CLK_USDHC2>,
					 <&clks IMX6UL_CLK_USDHC2>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				fsl,tuning-step = <2>;
				fsl,tuning-start-tap = <20>;
				status = "disabled";
			};

			adc1: adc@2198000 {
				compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
				reg = <0x02198000 0x4000>;
				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_ADC1>;
				clock-names = "adc";
				fsl,adck-max-frequency = <30000000>, <40000000>,
							 <20000000>;
				status = "disabled";
			};

			i2c1: i2c@21a0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
				reg = <0x021a0000 0x4000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_I2C1>;
				status = "disabled";
			};

			i2c2: i2c@21a4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
				reg = <0x021a4000 0x4000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_I2C2>;
				status = "disabled";
			};

			i2c3: i2c@21a8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
				reg = <0x021a8000 0x4000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_I2C3>;
				status = "disabled";
			};

			memory-controller@21b0000 {
				compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
				reg = <0x021b0000 0x4000>;
				clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
			};

			weim: weim@21b8000 {
				#address-cells = <2>;
				#size-cells = <1>;
				compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
				reg = <0x021b8000 0x4000>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_EIM>;
				fsl,weim-cs-gpr = <&gpr>;
				status = "disabled";
			};

			ocotp: efuse@21bc000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,imx6ul-ocotp", "syscon";
				reg = <0x021bc000 0x4000>;
				clocks = <&clks IMX6UL_CLK_OCOTP>;

				tempmon_calib: calib@38 {
					reg = <0x38 4>;
				};

				tempmon_temp_grade: temp-grade@20 {
					reg = <0x20 4>;
				};

				cpu_speed_grade: speed-grade@10 {
					reg = <0x10 4>;
				};
			};

			csi: csi@21c4000 {
				compatible = "fsl,imx6ul-csi";
				reg = <0x021c4000 0x4000>;
				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_CSI>;
				clock-names = "mclk";
				status = "disabled";
			};

			lcdif: lcdif@21c8000 {
				compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";
				reg = <0x021c8000 0x4000>;
				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
					 <&clks IMX6UL_CLK_LCDIF_APB>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "pix", "axi", "disp_axi";
				status = "disabled";
			};

			pxp: pxp@21cc000 {
				compatible = "fsl,imx6ul-pxp";
				reg = <0x021cc000 0x4000>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_PXP>;
				clock-names = "axi";
			};

			qspi: spi@21e0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-qspi";
				reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_QSPI>,
					 <&clks IMX6UL_CLK_QSPI>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			wdog3: watchdog@21e4000 {
				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
				reg = <0x021e4000 0x4000>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_WDOG3>;
				status = "disabled";
			};

			uart2: serial@21e8000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart";
				reg = <0x021e8000 0x4000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_UART2_IPG>,
					 <&clks IMX6UL_CLK_UART2_SERIAL>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart3: serial@21ec000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart";
				reg = <0x021ec000 0x4000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_UART3_IPG>,
					 <&clks IMX6UL_CLK_UART3_SERIAL>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart4: serial@21f0000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart";
				reg = <0x021f0000 0x4000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_UART4_IPG>,
					 <&clks IMX6UL_CLK_UART4_SERIAL>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart5: serial@21f4000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart";
				reg = <0x021f4000 0x4000>;
				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_UART5_IPG>,
					 <&clks IMX6UL_CLK_UART5_SERIAL>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c4: i2c@21f8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
				reg = <0x021f8000 0x4000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_I2C4>;
				status = "disabled";
			};

			uart6: serial@21fc000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart";
				reg = <0x021fc000 0x4000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_UART6_IPG>,
					 <&clks IMX6UL_CLK_UART6_SERIAL>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Copyright (C) 2016 Freescale Semiconductor, Inc.

/dts-v1/;

#include "imx6ull.dtsi"
#include "imx6ul-14x14-evk.dtsi"

/ {
	model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board";
	compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
};

&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>;
	assigned-clock-rates = <320000000>;
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2017-2022 Toradex
 */

/dts-v1/;

#include "imx6ull-colibri-nonwifi.dtsi"
#include "imx6ull-colibri-aster.dtsi"

/ {
	model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Aster";
	compatible = "toradex,colibri-imx6ull-aster",
		     "toradex,colibri-imx6ull",
		     "fsl,imx6ull";
};

&ad7879_ts {
	status = "okay";
};

&atmel_mxt_ts {
	status = "okay";
};

&backlight {
	status = "okay";
};

&i2c1 {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&lcdif {
	status = "okay";
};

&panel_dpi {
	status = "okay";
};

&pwm4 {
	status = "okay";
};

/* PWM <B> */
&pwm5 {
	/* Pin already used by atmel_mxt_ts touchscreen */
	status = "disabled";
};

/* PWM <C> */
&pwm6 {
	/* Pin already used by atmel_mxt_ts touchscreen */
	status = "disabled";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2017-2022 Toradex
 */

/ {
	chosen {
		stdout-path = "serial0:115200n8";
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_snvs_gpiokeys>;

		power {
			label = "Wake-Up";
			gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_WAKEUP>;
			debounce-interval = <10>;
			wakeup-source;
		};
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_5v0: regulator-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_usbh_vbus: regulator-usbh-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbh_reg>;
		regulator-name = "VCC_USB[1-4]";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
		vin-supply = <&reg_5v0>;
	};
};

&adc1 {
	status = "okay";
};

&ecspi1 {
	status = "okay";

	num-cs = <2>;
	cs-gpios = <
		&gpio3 26 GPIO_ACTIVE_HIGH /* SODIMM 86 LCD_DATA21 */
		&gpio4 28 GPIO_ACTIVE_HIGH /* SODIMM 65 CSI_DATA07 */
	>;
};

/*
 * Following SODIMM Pins should not be accessed as GPIO on Aster board:
 * 134 - AIN5_SCL (no connection)
 * 127 - Voltage Level Translator OE# signal (IC11 and IC12)
 *
 * To configure GPIO to LED5, please disable FEC2 and uncomment the following:
 *	&iomuxc {
 *		pinctrl-names = "default";
 *		pinctrl-0 = <
 *			&pinctrl_gpio1
 *			&pinctrl_gpio2
 *			&pinctrl_gpio3
 *			&pinctrl_gpio4
 *			&pinctrl_gpio6 - for non-WiFi modules only
 *			&pinctrl_gpio7
 *			&pinctrl_gpio_aster
 *		>;
 *
 *		pinctrl_gpio_aster: gpio-aster {
 *			fsl,pins = <
 *				MX6UL_PAD_GPIO1_IO07__GPIO1_IO07    0x1b0b0
 *			>;
 *		};
 *  };
 */

&i2c1 {
	status = "okay";

	m41t0m6: rtc@68 {
		compatible = "st,m41t0";
		reg = <0x68>;
	};
};

/* PWM <A> */
&pwm4 {
	status = "okay";
};

/* PWM <B> */
&pwm5 {
	status = "okay";
};

/* PWM <C> */
&pwm6 {
	status = "okay";
};

/* PWM <D> */
&pwm7 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&uart5 {
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usbh_vbus>;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usbh_vbus>;
	status = "okay";
};

&usdhc1 {
	vmmc-supply = <&reg_3v3>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

/dts-v1/;

#include "imx6ull-colibri-emmc-nonwifi.dtsi"
#include "imx6ull-colibri-aster.dtsi"

/ {
	model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster";
	compatible = "toradex,colibri-imx6ull-emmc-aster",
		     "toradex,colibri-imx6ull-emmc",
		     "toradex,colibri-imx6ull",
		     "fsl,imx6ull";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright 2021 Toradex
 */

/dts-v1/;

#include "imx6ull-colibri-emmc-nonwifi.dtsi"
#include "imx6ull-colibri-eval-v3.dtsi"

/ {
	model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Evaluation Board V3";
	compatible = "toradex,colibri-imx6ull-emmc-eval",
		     "toradex,colibri-imx6ull-emmc",
		     "toradex,colibri-imx6ull",
		     "fsl,imx6ull";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

/dts-v1/;

#include "imx6ull-colibri-emmc-nonwifi.dtsi"
#include "imx6ull-colibri-iris-v2.dtsi"

/ {
	model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2";
	compatible = "toradex,colibri-imx6ull-iris-v2",
		     "toradex,colibri-imx6ull-emmc",
		     "toradex,colibri-imx6ull",
		     "fsl,imx6ull";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

/dts-v1/;

#include "imx6ull-colibri-emmc-nonwifi.dtsi"
#include "imx6ull-colibri-iris.dtsi"

/ {
	model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris";
	compatible = "toradex,colibri-imx6ull-emmc-iris",
		     "toradex,colibri-imx6ull-emmc",
		     "toradex,colibri-imx6ull",
		     "fsl,imx6ull";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

#include "imx6ull-colibri.dtsi"

/ {
	aliases {
		mmc0 = &usdhc2; /* eMMC */
		mmc1 = &usdhc1; /* MMC 4-bit slot */
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;
	};
};

&gpio1 {
	gpio-line-names = "SODIMM_8",
			  "SODIMM_6",
			  "SODIMM_129",
			  "SODIMM_89",
			  "SODIMM_19",
			  "SODIMM_21",
			  "UNUSABLE_SODIMM_180",
			  "UNUSABLE_SODIMM_184",
			  "SODIMM_4",
			  "SODIMM_2",
			  "SODIMM_106",
			  "SODIMM_71",
			  "SODIMM_23",
			  "SODIMM_31",
			  "SODIMM_99",
			  "SODIMM_102",
			  "SODIMM_33",
			  "SODIMM_35",
			  "SODIMM_25",
			  "SODIMM_27",
			  "SODIMM_36",
			  "SODIMM_38",
			  "SODIMM_32",
			  "SODIMM_34",
			  "SODIMM_135",
			  "SODIMM_77",
			  "SODIMM_100",
			  "SODIMM_186",
			  "SODIMM_196",
			  "SODIMM_194";
};

&gpio2 {
	gpio-line-names = "SODIMM_55",
			  "SODIMM_63",
			  "SODIMM_178",
			  "SODIMM_188",
			  "SODIMM_73",
			  "SODIMM_30",
			  "SODIMM_67",
			  "SODIMM_104",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_190",
			  "SODIMM_47",
			  "SODIMM_192",
			  "SODIMM_49",
			  "SODIMM_51",
			  "SODIMM_53";
};

&gpio3 {
	gpio-line-names = "SODIMM_56",
			  "SODIMM_44",
			  "SODIMM_68",
			  "SODIMM_82",
			  "",
			  "SODIMM_76",
			  "SODIMM_70",
			  "SODIMM_60",
			  "SODIMM_58",
			  "SODIMM_78",
			  "SODIMM_72",
			  "SODIMM_80",
			  "SODIMM_46",
			  "SODIMM_62",
			  "SODIMM_48",
			  "SODIMM_74",
			  "SODIMM_50",
			  "SODIMM_52",
			  "SODIMM_54",
			  "SODIMM_66",
			  "SODIMM_64",
			  "SODIMM_57",
			  "SODIMM_61",
			  "SODIMM_29",
			  "SODIMM_37",
			  "SODIMM_88",
			  "SODIMM_86",
			  "SODIMM_92",
			  "SODIMM_90";
};

&gpio4 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_140",
			  "SODIMM_59",
			  "SODIMM_142",
			  "SODIMM_144",
			  "SODIMM_133",
			  "SODIMM_146",
			  "SODIMM_28",
			  "SODIMM_75",
			  "SODIMM_96",
			  "SODIMM_81",
			  "SODIMM_94",
			  "SODIMM_101",
			  "SODIMM_103",
			  "SODIMM_79",
			  "SODIMM_97",
			  "SODIMM_69",
			  "SODIMM_98",
			  "SODIMM_85",
			  "SODIMM_65";
};

&gpio5 {
	gpio-line-names = "SODIMM_43",
			  "SODIMM_45",
			  "SODIMM_137",
			  "SODIMM_95",
			  "SODIMM_107",
			  "SODIMM_131",
			  "SODIMM_93",
			  "",
			  "SODIMM_138",
			  "",
			  "SODIMM_105",
			  "SODIMM_127";
};

/* NAND */
&gpmi {
	status = "disabled";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
		&pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7
		&pinctrl_gpmi_gpio>;
};

&iomuxc_snvs {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>;
};

/* eMMC */
&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2emmc>;
	assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
	assigned-clock-rates = <0>, <198000000>;
	bus-width = <8>;
	keep-power-in-suspend;
	no-1-8-v;
	non-removable;
	vmmc-supply = <&reg_module_3v3>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2018-2022 Toradex
 */

/dts-v1/;

#include "imx6ull-colibri-nonwifi.dtsi"
#include "imx6ull-colibri-eval-v3.dtsi"

/ {
	model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3";
	compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull";
};

&ad7879_ts {
	status = "okay";
};

&backlight {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&lcdif {
	status = "okay";
};

&panel_dpi {
	status = "okay";
};

&pwm4 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2017-2022 Toradex
 */

/ {
	chosen {
		stdout-path = "serial0:115200n8";
	};

	/* fixed crystal dedicated to mcp2515 */
	clk16m: clk16m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <16000000>;
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_5v0: regulator-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_usbh_vbus: regulator-usbh-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbh_reg>;
		regulator-name = "VCC_USB[1-4]";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
		vin-supply = <&reg_5v0>;
	};
};

&adc1 {
	status = "okay";
};

&ecspi1 {
	status = "okay";

	mcp2515: can@0 {
		compatible = "microchip,mcp2515";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_can_int>;
		reg = <0>;
		clocks = <&clk16m>;
		interrupt-parent = <&gpio2>;
		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
		spi-max-frequency = <10000000>;
		vdd-supply = <&reg_3v3>;
		xceiver-supply = <&reg_5v0>;
		status = "okay";
	};
};

&i2c1 {
	status = "okay";

	/* M41T0M6 real time clock on carrier board */
	m41t0m6: rtc@68 {
		compatible = "st,m41t0";
		reg = <0x68>;
	};
};

/* PWM <A> */
&pwm4 {
	status = "okay";
};

/* PWM <B> */
&pwm5 {
	status = "okay";
};

/* PWM <C> */
&pwm6 {
	status = "okay";
};

/* PWM <D> */
&pwm7 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&uart5 {
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usbh_vbus>;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usbh_vbus>;
	status = "okay";
};

&usdhc1 {
	vmmc-supply = <&reg_3v3>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2018-2022 Toradex
 */

/dts-v1/;

#include "imx6ull-colibri-nonwifi.dtsi"
#include "imx6ull-colibri-iris-v2.dtsi"

/ {
	model = "Toradex Colibri iMX6ULL 256M/512B on Colibri Iris V2";
	compatible = "toradex,colibri-imx6ull-iris-v2",
		     "toradex,colibri-imx6ull",
		     "fsl,imx6ull";
};

&ad7879_ts {
	status = "okay";
};

&atmel_mxt_ts {
	status = "okay";
};

&backlight {
	status = "okay";
};

&gpio1 {
	/* This turns the LVDS transceiver on */
	lvds-power-on-hog {
		gpio-hog;
		gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
		line-name = "LVDS_POWER_ON";
		output-high;
	};
};

&gpio2 {
	/*
	 * This switches the LVDS transceiver to the single-channel
	 * output mode.
	 */
	lvds-ch-mode-hog {
		gpio-hog;
		gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
		line-name = "LVDS_CH_MODE";
		output-high;
	};

	/*
	 * This switches the LVDS transceiver to the 24-bit RGB mode.
	 */
	lvds-rgb-mode-hog {
		gpio-hog;
		gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
		line-name = "LVDS_RGB_MODE";
		output-low;
	};
};

&gpio5 {
	/*
	 * This switches the LVDS transceiver to VESA color mapping mode.
	 */
	lvds-color-map-hog {
		gpio-hog;
		gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
		line-name = "LVDS_COLOR_MAP";
		output-low;
	};
};

&i2c1 {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&lcdif {
	status = "okay";
};

&panel_dpi {
	status = "okay";
};

&pwm4 {
	status = "okay";
};

/* PWM <B> */
&pwm5 {
	/* Pin already used by atmel_mxt_ts touchscreen */
	status = "disabled";
};

/* PWM <C> */
&pwm6 {
	/* Pin already used by atmel_mxt_ts touchscreen */
	status = "disabled";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2018-2022 Toradex
 */

#include "imx6ull-colibri-iris.dtsi"

/ {
	reg_3v3_vmmc: regulator-3v3-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "3v3_vmmc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
		startup-delay-us = <100>;
		enable-active-high;
	};
};

&usdhc1 {
	cap-power-off-card;
	vmmc-supply = <&reg_3v3_vmmc>;
	/delete-property/ keep-power-in-suspend;
	/delete-property/ no-1-8-v;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2018-2022 Toradex
 */

/dts-v1/;

#include "imx6ull-colibri-nonwifi.dtsi"
#include "imx6ull-colibri-iris.dtsi"

/ {
	model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Iris";
	compatible = "toradex,colibri-imx6ull-iris",
		     "toradex,colibri-imx6ull",
		     "fsl,imx6ull";
};

&ad7879_ts {
	status = "okay";
};

&backlight {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&lcdif {
	status = "okay";
};

&panel_dpi {
	status = "okay";
};

&pwm4 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2018-2022 Toradex
 */

/ {
	chosen {
		stdout-path = "serial0:115200n8";
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_snvs_gpiokeys>;

		power {
			label = "Wake-Up";
			gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_WAKEUP>;
			debounce-interval = <10>;
			wakeup-source;
		};
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_5v0: regulator-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_usbh_vbus: regulator-usbh-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbh_reg>;
		regulator-name = "VCC_USB[1-4]";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
		vin-supply = <&reg_5v0>;
	};
};

&adc1 {
	status = "okay";
};

&gpio1 {
	/*
	 * uart25_tx_on turns the UART transceiver on. If one wants to turn the
	 * transceiver off, that property has to be deleted and the gpio handled
	 * in userspace.
	 * The same applies to uart1_tx_on.
	 */
	uart25_tx_on-hog {
		gpio-hog;
		gpios = <15 0>;
		output-high;
	};
};

&gpio2 {
	uart1_tx_on-hog {
		gpio-hog;
		gpios = <7 0>;
		output-high;
	};
};

&i2c1 {
	status = "okay";

	/* M41T0M6 real time clock on carrier board */
	m41t0m6: rtc@68 {
		compatible = "st,m41t0";
		reg = <0x68>;
	};
};

/* PWM <A> */
&pwm4 {
	status = "okay";
};

/* PWM <B> */
&pwm5 {
	status = "okay";
};

/* PWM <C> */
&pwm6 {
	status = "okay";
};

/* PWM <D> */
&pwm7 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&uart5 {
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usbh_vbus>;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usbh_vbus>;
	status = "okay";
};

&usdhc1 {
	vmmc-supply = <&reg_3v3>;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2017-2022 Toradex
 */

/dts-v1/;

#include "imx6ull-colibri-wifi.dtsi"
#include "imx6ull-colibri-aster.dtsi"

/ {
	model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster";
	compatible = "toradex,colibri-imx6ull-wifi-aster",
		     "toradex,colibri-imx6ull",
		     "fsl,imx6ull";
};

&ad7879_ts {
	status = "okay";
};

&atmel_mxt_ts {
	status = "okay";
};

&backlight {
	status = "okay";
};

&i2c1 {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&lcdif {
	status = "okay";
};

&panel_dpi {
	status = "okay";
};

&pwm4 {
	status = "okay";
};

/* PWM <B> */
&pwm5 {
	/* Pin already used by atmel_mxt_ts touchscreen */
	status = "disabled";
};

/* PWM <C> */
&pwm6 {
	/* Pin already used by atmel_mxt_ts touchscreen */
	status = "disabled";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2018-2022 Toradex
 */

/dts-v1/;

#include "imx6ull-colibri-wifi.dtsi"
#include "imx6ull-colibri-eval-v3.dtsi"

/ {
	model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3";
	compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull";
};

&ad7879_ts {
	status = "okay";
};

&backlight {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&lcdif {
	status = "okay";
};

&panel_dpi {
	status = "okay";
};

&pwm4 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2018-2022 Toradex
 */

/dts-v1/;

#include "imx6ull-colibri-wifi.dtsi"
#include "imx6ull-colibri-iris-v2.dtsi"

/ {
	model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2";
	compatible = "toradex,colibri-imx6ull-wifi-iris-v2",
		     "toradex,colibri-imx6ull",
		     "fsl,imx6ull";
};

&ad7879_ts {
	status = "okay";
};

&atmel_mxt_ts {
	status = "okay";
};

&backlight {
	status = "okay";
};

&gpio1 {
	/* This turns the LVDS transceiver on */
	lvds-power-on-hog {
		gpio-hog;
		gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
		line-name = "LVDS_POWER_ON";
		output-high;
	};
};

&gpio2 {
	/*
	 * This switches the LVDS transceiver to the single-channel
	 * output mode.
	 */
	lvds-ch-mode-hog {
		gpio-hog;
		gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
		line-name = "LVDS_CH_MODE";
		output-high;
	};

	/*
	 * This switches the LVDS transceiver to the 24-bit RGB mode.
	 */
	lvds-rgb-mode-hog {
		gpio-hog;
		gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
		line-name = "LVDS_RGB_MODE";
		output-low;
	};
};

&gpio5 {
	/*
	 * This switches the LVDS transceiver to VESA color mapping mode.
	 */
	lvds-color-map-hog {
		gpio-hog;
		gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
		line-name = "LVDS_COLOR_MAP";
		output-low;
	};
};

&i2c2 {
	status = "okay";
};

&lcdif {
	status = "okay";
};

&panel_dpi {
	status = "okay";
};

&pwm4 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2018-2022 Toradex
 */

/dts-v1/;

#include "imx6ull-colibri-wifi.dtsi"
#include "imx6ull-colibri-iris.dtsi"

/ {
	model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris";
	compatible = "toradex,colibri-imx6ull-wifi-iris",
		     "toradex,colibri-imx6ull",
		     "fsl,imx6ull";
};

&ad7879_ts {
	status = "okay";
};

&atmel_mxt_ts {
	status = "okay";
};

&backlight {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&lcdif {
	status = "okay";
};

&panel_dpi {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2018-2022 Toradex
 */

#include "imx6ull-colibri.dtsi"

/ {
	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	wifi_pwrseq: sdio-pwrseq {
		compatible = "mmc-pwrseq-simple";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_snvs_wifi_pdn>;
		reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
	};
};

&cpu0 {
	clock-frequency = <792000000>;
};

&gpio1 {
	gpio-line-names = "SODIMM_8",
			  "SODIMM_6",
			  "SODIMM_129",
			  "",
			  "SODIMM_19",
			  "SODIMM_21",
			  "UNUSABLE_SODIMM_180",
			  "UNUSABLE_SODIMM_184",
			  "SODIMM_4",
			  "SODIMM_2",
			  "SODIMM_106",
			  "SODIMM_71",
			  "SODIMM_23",
			  "SODIMM_31",
			  "SODIMM_99",
			  "SODIMM_102",
			  "SODIMM_33",
			  "SODIMM_35",
			  "SODIMM_25",
			  "SODIMM_27",
			  "SODIMM_36",
			  "SODIMM_38",
			  "SODIMM_32",
			  "SODIMM_34",
			  "SODIMM_135",
			  "SODIMM_77",
			  "SODIMM_100",
			  "SODIMM_186",
			  "SODIMM_196",
			  "SODIMM_194";
};

&gpio2 {
	gpio-line-names = "SODIMM_55",
			  "SODIMM_63",
			  "SODIMM_178",
			  "SODIMM_188",
			  "SODIMM_73",
			  "SODIMM_30",
			  "SODIMM_67",
			  "SODIMM_104",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_190",
			  "SODIMM_47",
			  "SODIMM_192",
			  "SODIMM_49",
			  "SODIMM_51",
			  "SODIMM_53";
};

&gpio3 {
	gpio-line-names = "SODIMM_56",
			  "SODIMM_44",
			  "SODIMM_68",
			  "SODIMM_82",
			  "",
			  "SODIMM_76",
			  "SODIMM_70",
			  "SODIMM_60",
			  "SODIMM_58",
			  "SODIMM_78",
			  "SODIMM_72",
			  "SODIMM_80",
			  "SODIMM_46",
			  "SODIMM_62",
			  "SODIMM_48",
			  "SODIMM_74",
			  "SODIMM_50",
			  "SODIMM_52",
			  "SODIMM_54",
			  "SODIMM_66",
			  "SODIMM_64",
			  "SODIMM_57",
			  "SODIMM_61",
			  "SODIMM_29",
			  "SODIMM_37",
			  "SODIMM_88",
			  "SODIMM_86",
			  "SODIMM_92",
			  "SODIMM_90";
};

&gpio4 {
	gpio-line-names = "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_59",
			  "",
			  "",
			  "SODIMM_133",
			  "",
			  "SODIMM_28",
			  "SODIMM_75",
			  "SODIMM_96",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_69",
			  "SODIMM_98",
			  "SODIMM_85",
			  "SODIMM_65";
};

&gpio5 {
	gpio-line-names = "SODIMM_43",
			  "SODIMM_45",
			  "SODIMM_137",
			  "SODIMM_95",
			  "SODIMM_107",
			  "SODIMM_131",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_105";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
		&pinctrl_gpio4 &pinctrl_gpio7>;

};

&iomuxc_snvs {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_snvs_gpio1>;
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
	assigned-clock-rates = <0>, <198000000>;
	cap-power-off-card;
	keep-power-in-suspend;
	max-frequency = <25000000>;
	mmc-pwrseq = <&wifi_pwrseq>;
	no-1-8-v;
	non-removable;
	vmmc-supply = <&reg_module_3v3>;
	wakeup-source;
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2018-2022 Toradex
 */

#include "imx6ull.dtsi"

/ {
	/* Ethernet aliases to ensure correct MAC addresses */
	aliases {
		ethernet0 = &fec2;
		ethernet1 = &fec1;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
		enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_bl_on>;
		power-supply = <&reg_3v3>;
		pwms = <&pwm4 0 5000000 1>;
		status = "disabled";
	};

	connector {
		compatible = "gpio-usb-b-connector", "usb-b-connector";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_snvs_usbc_det>;
		id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */
		label = "USBC";
		self-powered;
		type = "micro";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				usb_dr_connector: endpoint {
					remote-endpoint = <&usb1_drd_sw>;
				};
			};
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_snvs_gpiokeys>;

		wakeup {
			debounce-interval = <10>;
			gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
			label = "Wake-Up";
			linux,code = <KEY_WAKEUP>;
			wakeup-source;
		};
	};

	panel_dpi: panel-dpi {
		compatible = "edt,et057090dhu";
		backlight = <&backlight>;
		power-supply = <&reg_3v3>;
		status = "disabled";

		port {
			lcd_panel_in: endpoint {
				remote-endpoint = <&lcdif_out>;
			};
		};
	};

	reg_module_3v3: regulator-module-3v3 {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-name = "+V3.3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_module_3v3_avdd: regulator-module-3v3-avdd {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-name = "+V3.3_AVDD_AUDIO";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_sd1_vqmmc: regulator-sd1-vqmmc {
		compatible = "regulator-gpio";
		gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_snvs_reg_sd>;
		regulator-always-on;
		regulator-name = "+V3.3_1.8_SD";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		states = <1800000 0x1 3300000 0x0>;
		vin-supply = <&reg_module_3v3>;
	};

	reg_eth_phy: regulator-eth-phy {
		compatible = "regulator-fixed-clock";
		regulator-boot-on;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-name = "+V3.3_ETH";
		regulator-type = "voltage";
		vin-supply = <&reg_module_3v3>;
		clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
		startup-delay-us = <150000>;
	};
};

&adc1 {
	vref-supply = <&reg_module_3v3_avdd>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc1>;
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "disabled";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "disabled";
};

/* Colibri SPI */
&ecspi1 {
	cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
};

/* Ethernet */
&fec2 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_enet2>;
	pinctrl-1 = <&pinctrl_enet2_sleep>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_eth_phy>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			max-speed = <100>;
			reg = <2>;
		};
	};
};

/* NAND */
&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	fsl,use-minimum-ecc;
	nand-on-flash-bbt;
	nand-ecc-mode = "hw";
	nand-ecc-strength = <8>;
	nand-ecc-step-size = <512>;
	status = "okay";
};

/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */
&i2c1 {
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "disabled";

	/* Atmel maxtouch controller */
	atmel_mxt_ts: touchscreen@4a {
		compatible = "atmel,maxtouch";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>;
		reg = <0x4a>;
		interrupt-parent = <&gpio5>;
		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;       /* SODIMM 107 / INT */
		reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;    /* SODIMM 106 / RST */
		status = "disabled";
	};
};

/*
 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 * touch screen controller
 */
&i2c2 {
	/* Use low frequency to compensate for the high pull-up values. */
	clock-frequency = <40000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	ad7879_ts: touchscreen@2c {
		compatible = "adi,ad7879-1";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
		reg = <0x2c>;
		interrupt-parent = <&gpio5>;
		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
		touchscreen-max-pressure = <4096>;
		adi,resistance-plate-x = <120>;
		adi,first-conversion-delay = /bits/ 8 <3>;
		adi,acquisition-time = /bits/ 8 <1>;
		adi,median-filter-size = /bits/ 8 <2>;
		adi,averaging = /bits/ 8 <1>;
		adi,conversion-interval = /bits/ 8 <255>;
		status = "disabled";
	};
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat
		     &pinctrl_lcdif_ctrl>;
	status = "disabled";

	port {
		lcdif_out: endpoint {
			remote-endpoint = <&lcd_panel_in>;
		};
	};
};

/* PWM <A> */
&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
};

/* PWM <B> */
&pwm5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm5>;
};

/* PWM <C> */
&pwm6 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm6>;
};

/* PWM <D> */
&pwm7 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm7>;
};

&sdma {
	status = "okay";
};

&snvs_pwrkey {
	status = "disabled";
};

/* Colibri UART_A */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
	uart-has-rtscts;
	fsl,dte-mode;
};

/* Colibri UART_B */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	uart-has-rtscts;
	fsl,dte-mode;
};

/* Colibri UART_C */
&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	fsl,dte-mode;
};

/* Colibri USBC */
&usbotg1 {
	dr_mode = "otg";
	srp-disable;
	hnp-disable;
	adp-disable;
	usb-role-switch;

	port {
		usb1_drd_sw: endpoint {
			remote-endpoint = <&usb_dr_connector>;
		};
	};
};

/* Colibri USBH */
&usbotg2 {
	dr_mode = "host";
};

/* Colibri MMC/SD */
&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
	pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>;
	assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
	assigned-clock-rates = <0>, <198000000>;
	bus-width = <4>;
	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
	disable-wp;
	keep-power-in-suspend;
	no-1-8-v;
	vqmmc-supply = <&reg_sd1_vqmmc>;
	wakeup-source;
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
};

&iomuxc {
	pinctrl_adc1: adc1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00        0x3000 /* SODIMM 8 */
			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0x3000 /* SODIMM 6 */
			MX6UL_PAD_GPIO1_IO08__GPIO1_IO08        0x3000 /* SODIMM 4 */
			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x3000 /* SODIMM 2 */
		>;
	};

	pinctrl_atmel_adap: atmeladapgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_DQS__GPIO4_IO16          0xb0a0  /* SODIMM 28 */
			MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05       0xb0a0  /* SODIMM 30 */
		>;
	};

	pinctrl_atmel_conn: atmelconngrp {
		fsl,pins = <
			MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0xb0a0  /* SODIMM 106 */
		>;
	};

	pinctrl_can_int: canintgrp {
		fsl,pins = <
			MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04	0x13010	/* SODIMM 73 */
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
		>;
	};

	pinctrl_enet2_sleep: enet2-sleepgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO06__GPIO1_IO06	0x0
			MX6UL_PAD_GPIO1_IO07__GPIO1_IO07	0x0
			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x0
			MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09	0x0
			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x0
			MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15	0x0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
			MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11	0x0
			MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12	0x0
			MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13	0x0
		>;
	};

	pinctrl_ecspi1_cs: ecspi1csgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x70a0	/* SODIMM 86 */
		>;
	};

	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK	0x000a0	/* SODIMM 88 */
			MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	0x000a0 /* SODIMM 92 */
			MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	0x100a0 /* SODIMM 90 */
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX	0x1b020
			MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX	0x1b020
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX	0x1b020
			MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX	0x1b020
		>;
	};

	pinctrl_gpio_bl_on: gpioblongrp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TMS__GPIO1_IO11		0x30a0	/* SODIMM 71 */
		>;
	};

	pinctrl_gpio1: gpio1grp {
		fsl,pins = <
			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x10b0 /* SODIMM 77 */
			MX6UL_PAD_JTAG_TCK__GPIO1_IO14		0x70a0 /* SODIMM 99 */
			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x10b0 /* SODIMM 133 */
			MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x10b0 /* SODIMM 135 */
			MX6UL_PAD_UART3_CTS_B__GPIO1_IO26	0x10b0 /* SODIMM 100 */
			MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15	0x70a0 /* SODIMM 102 */
			MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07	0x10b0 /* SODIMM 104 */
			MX6UL_PAD_UART3_RTS_B__GPIO1_IO27	0x10b0 /* SODIMM 186 */
		>;
	};

	pinctrl_gpio2: gpio2grp { /* Camera */
		fsl,pins = <
			MX6UL_PAD_CSI_DATA04__GPIO4_IO25	0x10b0 /* SODIMM 69 */
			MX6UL_PAD_CSI_MCLK__GPIO4_IO17		0x10b0 /* SODIMM 75 */
			MX6UL_PAD_CSI_DATA06__GPIO4_IO27	0x10b0 /* SODIMM 85 */
			MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18	0x10b0 /* SODIMM 96 */
			MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x10b0 /* SODIMM 98 */
		>;
	};

	pinctrl_gpio3: gpio3grp { /* CAN2 */
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02	0x10b0 /* SODIMM 178 */
			MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03	0x10b0 /* SODIMM 188 */
		>;
	};

	pinctrl_gpio4: gpio4grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA07__GPIO4_IO28	0x10b0 /* SODIMM 65 */
		>;
	};

	pinctrl_gpio6: gpio6grp { /* Wifi pins */
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0x10b0 /* SODIMM 89 */
			MX6UL_PAD_CSI_DATA02__GPIO4_IO23	0x10b0 /* SODIMM 79 */
			MX6UL_PAD_CSI_VSYNC__GPIO4_IO19		0x10b0 /* SODIMM 81 */
			MX6UL_PAD_CSI_DATA03__GPIO4_IO24	0x10b0 /* SODIMM 97 */
			MX6UL_PAD_CSI_DATA00__GPIO4_IO21	0x10b0 /* SODIMM 101 */
			MX6UL_PAD_CSI_DATA01__GPIO4_IO22	0x10b0 /* SODIMM 103 */
			MX6UL_PAD_CSI_HSYNC__GPIO4_IO20		0x10b0 /* SODIMM 94 */
		>;
	};

	pinctrl_gpio7: gpio7grp { /* CAN1 */
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00	0xb0b0/* SODIMM 55 */
			MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01	0xb0b0 /* SODIMM 63 */
		>;
	};

	/*
	 * With an eMMC instead of a raw NAND device the following pins
	 * are available at SODIMM pins.
	 */
	pinctrl_gpmi_gpio: gpmigpiogrp {
		fsl,pins = <
			MX6UL_PAD_NAND_ALE__GPIO4_IO10		0x10b0 /* SODIMM 140 */
			MX6UL_PAD_NAND_CE0_B__GPIO4_IO13	0x10b0 /* SODIMM 144 */
			MX6UL_PAD_NAND_CLE__GPIO4_IO15		0x10b0 /* SODIMM 146 */
			MX6UL_PAD_NAND_READY_B__GPIO4_IO12	0x10b0 /* SODIMM 142 */
		>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0x100a9
			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0x100a9
			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0x100a9
			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0x100a9
			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0x100a9
			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0x100a9
			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0x100a9
			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0x100a9
			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0x100a9
			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0x100a9
			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0x100a9
			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0x100a9
			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0x100a9
			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0x100a9
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0	/* SODIMM 196 */
			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0	/* SODIMM 194 */
		>;
	};

	pinctrl_i2c1_gpio: i2c1-gpiogrp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0	/* SODIMM 196 */
			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0	/* SODIMM 194 */
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0
			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0
		>;
	};

	pinctrl_i2c2_gpio: i2c2-gpiogrp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0
			MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0
		>;
	};

	pinctrl_lcdif_dat: lcdifdatgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079	/* SODIMM 76 */
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079	/* SODIMM 70 */
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079	/* SODIMM 60 */
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079	/* SODIMM 58 */
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079	/* SODIMM 78 */
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079	/* SODIMM 72 */
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079	/* SODIMM 80 */
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079	/* SODIMM 46 */
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079	/* SODIMM 62 */
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079	/* SODIMM 48 */
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079	/* SODIMM 74 */
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079	/* SODIMM 50 */
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079	/* SODIMM 52 */
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079	/* SODIMM 54 */
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079	/* SODIMM 66 */
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079	/* SODIMM 64 */
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079	/* SODIMM 57 */
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079	/* SODIMM 61 */
		>;
	};

	pinctrl_lcdif_ctrl: lcdifctrlgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x00079	/* SODIMM 56 */
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x00079	/* SODIMM 44 */
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x00079	/* SODIMM 68 */
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x00079	/* SODIMM 82 */
		>;
	};

	pinctrl_pwm4: pwm4grp {
		fsl,pins = <
			MX6UL_PAD_NAND_WP_B__PWM4_OUT	0x00079		/* SODIMM 59 */
		>;
	};

	pinctrl_pwm5: pwm5grp {
		fsl,pins = <
			MX6UL_PAD_NAND_DQS__PWM5_OUT	0x00079		/* SODIMM 28 */
		>;
	};

	pinctrl_pwm6: pwm6grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_TX_EN__PWM6_OUT	0x00079		/* SODIMM 30 */
		>;
	};

	pinctrl_pwm7: pwm7grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT	0x00079	/* SODIMM 67 */
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX	0x1b0b1	/* SODIMM 33 */
			MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX	0x1b0b1	/* SODIMM 35 */
			MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS	0x1b0b1	/* SODIMM 27 */
			MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS	0x1b0b1	/* SODIMM 25 */
		>;
	};

	pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */
		fsl,pins = <
			MX6UL_PAD_JTAG_TDI__GPIO1_IO13		0x70a0 /* SODIMM 31 / DCD */
			MX6UL_PAD_LCD_DATA18__GPIO3_IO23	0x10b0 /* SODIMM 29 / DSR */
			MX6UL_PAD_JTAG_TDO__GPIO1_IO12		0x90b1 /* SODIMM 23 / DTR */
			MX6UL_PAD_LCD_DATA19__GPIO3_IO24        0x10b0 /* SODIMM 37 / RI */
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX	0x1b0b1 /* SODIMM 36 */
			MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX	0x1b0b1 /* SODIMM 38 */
			MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS	0x1b0b1 /* SODIMM 32 */
			MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS	0x1b0b1 /* SODIMM 34 */
		>;
	};
	pinctrl_uart5: uart5grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX	0x1b0b1 /* SODIMM 19 */
			MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX	0x1b0b1 /* SODIMM 21 */
		>;
	};

	pinctrl_usbh_reg: usbhreggrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0x10b0 /* SODIMM 129 / USBH_PEN */
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059 /* SODIMM 47 */
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059 /* SODIMM 190 */
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059 /* SODIMM 192 */
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059 /* SODIMM 49 */
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059 /* SODIMM 51 */
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059 /* SODIMM 53 */
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x17069
			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x17069
			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x17069
			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17069
			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17069
			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x10069

			MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT	0x10
		>;
	};

	pinctrl_usdhc2emmc: usdhc2emmcgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
		>;
	};
};

&iomuxc_snvs {
	pinctrl_atmel_snvs_conn: atmelsnvsconngrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04     0xb0a0	/* SODIMM 107 */
		>;
	};

	pinctrl_snvs_gpio1: snvsgpio1grp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x110a0	/* SODIMM 93 */
			MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03	0x110a0	/* SODIMM 95 */
			MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10	0x1b0a0	/* SODIMM 105 */
			MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x0b0a0	/* SODIMM 131 / USBH_OC */
			MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x110a0	/* SODIMM 138 */
		>;
	};

	pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */
		fsl,pins = <
			MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11	0x130a0	/* SODIMM 127 */
		>;
	};

	pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x100b0
		>;
	};

	pinctrl_snvs_reg_sd: snvsregsdgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x400100b0
		>;
	};

	pinctrl_snvs_usbc_det: snvsusbcdetgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x130b0
		>;
	};

	pinctrl_snvs_gpiokeys: snvsgpiokeysgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x130a0	/* SODIMM 45 / WAKE_UP */
		>;
	};

	pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x1b0a0 /* SODIMM 43 / MMC_CD */
		>;
	};

	pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp {
		fsl,pins = <
			MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00	0x0
		>;
	};

	pinctrl_snvs_wifi_pdn: snvswifipdngrp {
		fsl,pins = <
			MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11	0x130a0
		>;
	};
};