code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Copyright 2015 Freescale Semiconductor, Inc.
// Copyright 2016 Toradex AG

#include <dt-bindings/clock/imx7d-clock.h>
#include <dt-bindings/power/imx7-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/imx7-reset.h>
#include "imx7d-pinfunc.h"

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 */
	chosen {};

	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		gpio6 = &gpio7;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		serial6 = &uart7;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &ecspi3;
		spi3 = &ecspi4;
		usb0 = &usbotg1;
		usb1 = &usbh;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		idle-states {
			entry-method = "psci";

			cpu_sleep_wait: cpu-sleep-wait {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				local-timer-stop;
				entry-latency-us = <100>;
				exit-latency-us = <50>;
				min-residency-us = <1000>;
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			clock-frequency = <792000000>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clks IMX7D_CLK_ARM>;
			cpu-idle-states = <&cpu_sleep_wait>;
			operating-points-v2 = <&cpu0_opp_table>;
			#cooling-cells = <2>;
			nvmem-cells = <&fuse_grade>;
			nvmem-cell-names = "speed_grade";
		};
	};

	cpu0_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-792000000 {
			opp-hz = /bits/ 64 <792000000>;
			opp-microvolt = <1000000>;
			clock-latency-ns = <150000>;
			opp-supported-hw = <0xf>, <0xf>;
		};
	};

	ckil: clock-cki {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "ckil";
	};

	osc: clock-osc {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc";
	};

	usbphynop1: usbphynop1 {
		compatible = "usb-nop-xceiv";
		clocks = <&clks IMX7D_USB_PHY1_CLK>;
		clock-names = "main_clk";
		#phy-cells = <0>;
	};

	usbphynop3: usbphynop3 {
		compatible = "usb-nop-xceiv";
		clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
		clock-names = "main_clk";
		power-domains = <&pgc_hsic_phy>;
		#phy-cells = <0>;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupt-parent = <&gpc>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>;
	};

	replicator {
		/*
		 * non-configurable replicators don't show up on the
		 * AMBA bus.  As such no need to add "arm,primecell"
		 */
		compatible = "arm,coresight-static-replicator";

		out-ports {
			#address-cells = <1>;
			#size-cells = <0>;
				/* replicator output ports */
			port@0 {
				reg = <0>;
				replicator_out_port0: endpoint {
					remote-endpoint = <&tpiu_in_port>;
				};
			};

			port@1 {
				reg = <1>;
				replicator_out_port1: endpoint {
					remote-endpoint = <&etr_in_port>;
				};
			};
		};

		in-ports {
			port {
				replicator_in_port0: endpoint {
					remote-endpoint = <&etf_out_port>;
				};
			};
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		arm,cpu-registers-not-fw-configured;
		interrupt-parent = <&intc>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gpc>;
		ranges;

		funnel@30041000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x30041000 0x1000>;
			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
			clock-names = "apb_pclk";

			ca_funnel_in_ports: in-ports {
				port {
					ca_funnel_in_port0: endpoint {
						remote-endpoint = <&etm0_out_port>;
					};
				};

				/* the other input ports are not connect to anything */
			};

			out-ports {
				port {
					ca_funnel_out_port0: endpoint {
						remote-endpoint = <&hugo_funnel_in_port0>;
					};
				};

			};
		};

		etm@3007c000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x3007c000 0x1000>;
			cpu = <&cpu0>;
			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					etm0_out_port: endpoint {
						remote-endpoint = <&ca_funnel_in_port0>;
					};
				};
			};
		};

		funnel@30083000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x30083000 0x1000>;
			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
			clock-names = "apb_pclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					hugo_funnel_in_port0: endpoint {
						remote-endpoint = <&ca_funnel_out_port0>;
					};
				};

				port@1 {
					reg = <1>;
					hugo_funnel_in_port1: endpoint {
						/* M4 input */
					};
				};
				/* the other input ports are not connect to anything */
			};

			out-ports {
				port {
					hugo_funnel_out_port0: endpoint {
						remote-endpoint = <&etf_in_port>;
					};
				};
			};
		};

		etf@30084000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x30084000 0x1000>;
			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					etf_in_port: endpoint {
						remote-endpoint = <&hugo_funnel_out_port0>;
					};
				};
			};

			out-ports {
				port {
					etf_out_port: endpoint {
						remote-endpoint = <&replicator_in_port0>;
					};
				};
			};
		};

		etr@30086000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x30086000 0x1000>;
			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					etr_in_port: endpoint {
						remote-endpoint = <&replicator_out_port1>;
					};
				};
			};
		};

		tpiu@30087000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0x30087000 0x1000>;
			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					tpiu_in_port: endpoint {
						remote-endpoint = <&replicator_out_port0>;
					};
				};
			};
		};

		intc: interrupt-controller@31001000 {
			compatible = "arm,cortex-a7-gic";
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupt-parent = <&intc>;
			reg = <0x31001000 0x1000>,
			      <0x31002000 0x2000>,
			      <0x31004000 0x2000>,
			      <0x31006000 0x2000>;
		};

		aips1: bus@30000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x30000000 0x400000>;
			ranges;

			gpio1: gpio@30200000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30200000 0x10000>;
				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
			};

			gpio2: gpio@30210000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30210000 0x10000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 13 32>;
			};

			gpio3: gpio@30220000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30220000 0x10000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 45 29>;
			};

			gpio4: gpio@30230000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30230000 0x10000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 74 24>;
			};

			gpio5: gpio@30240000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30240000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 98 18>;
			};

			gpio6: gpio@30250000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30250000 0x10000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 116 23>;
			};

			gpio7: gpio@30260000 {
				compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
				reg = <0x30260000 0x10000>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 139 16>;
			};

			wdog1: watchdog@30280000 {
				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
				reg = <0x30280000 0x10000>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
			};

			wdog2: watchdog@30290000 {
				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
				reg = <0x30290000 0x10000>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
				status = "disabled";
			};

			wdog3: watchdog@302a0000 {
				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
				reg = <0x302a0000 0x10000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
				status = "disabled";
			};

			wdog4: watchdog@302b0000 {
				compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
				reg = <0x302b0000 0x10000>;
				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
				status = "disabled";
			};

			iomuxc_lpsr: pinctrl@302c0000 {
				compatible = "fsl,imx7d-iomuxc-lpsr";
				reg = <0x302c0000 0x10000>;
				fsl,input-sel = <&iomuxc>;
			};

			gpt1: timer@302d0000 {
				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
				reg = <0x302d0000 0x10000>;
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
					 <&clks IMX7D_GPT1_ROOT_CLK>;
				clock-names = "ipg", "per";
			};

			gpt2: timer@302e0000 {
				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
				reg = <0x302e0000 0x10000>;
				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
					 <&clks IMX7D_GPT2_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			gpt3: timer@302f0000 {
				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
				reg = <0x302f0000 0x10000>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
					 <&clks IMX7D_GPT3_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			gpt4: timer@30300000 {
				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
				reg = <0x30300000 0x10000>;
				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
					 <&clks IMX7D_GPT4_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			kpp: keypad@30320000 {
				compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
				reg = <0x30320000 0x10000>;
				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_KPP_ROOT_CLK>;
				status = "disabled";
			};

			iomuxc: pinctrl@30330000 {
				compatible = "fsl,imx7d-iomuxc";
				reg = <0x30330000 0x10000>;
			};

			gpr: iomuxc-gpr@30340000 {
				compatible = "fsl,imx7d-iomuxc-gpr",
					"fsl,imx6q-iomuxc-gpr", "syscon",
					"simple-mfd";
				reg = <0x30340000 0x10000>;

				mux: mux-controller {
					compatible = "mmio-mux";
					#mux-control-cells = <0>;
					mux-reg-masks = <0x14 0x00000010>;
				};

				video_mux: csi-mux {
					compatible = "video-mux";
					mux-controls = <&mux 0>;
					#address-cells = <1>;
					#size-cells = <0>;
					status = "disabled";

					port@0 {
						reg = <0>;
					};

					port@1 {
						reg = <1>;

						csi_mux_from_mipi_vc0: endpoint {
							remote-endpoint = <&mipi_vc0_to_csi_mux>;
						};
					};

					port@2 {
						reg = <2>;

						csi_mux_to_csi: endpoint {
							remote-endpoint = <&csi_from_csi_mux>;
						};
					};
				};
			};

			ocotp: efuse@30350000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,imx7d-ocotp", "syscon";
				reg = <0x30350000 0x10000>;
				clocks = <&clks IMX7D_OCOTP_CLK>;

				tempmon_calib: calib@3c {
					reg = <0x3c 0x4>;
				};

				fuse_grade: fuse-grade@10 {
					reg = <0x10 0x4>;
				};
			};

			anatop: anatop@30360000 {
				compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
					"syscon", "simple-mfd";
				reg = <0x30360000 0x10000>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

				reg_1p0d: regulator-vdd1p0d {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd1p0d";
					regulator-min-microvolt = <800000>;
					regulator-max-microvolt = <1200000>;
					anatop-reg-offset = <0x210>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <8>;
					anatop-min-voltage = <800000>;
					anatop-max-voltage = <1200000>;
					anatop-enable-bit = <0>;
				};

				reg_1p2: regulator-vdd1p2 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd1p2";
					regulator-min-microvolt = <1100000>;
					regulator-max-microvolt = <1300000>;
					anatop-reg-offset = <0x220>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0x14>;
					anatop-min-voltage = <1100000>;
					anatop-max-voltage = <1300000>;
					anatop-enable-bit = <0>;
				};

				tempmon: tempmon {
					compatible = "fsl,imx7d-tempmon";
					interrupt-parent = <&gpc>;
					interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
					fsl,tempmon = <&anatop>;
					nvmem-cells = <&tempmon_calib>,	<&fuse_grade>;
					nvmem-cell-names = "calib", "temp_grade";
					clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
				};
			};

			snvs: snvs@30370000 {
				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
				reg = <0x30370000 0x10000>;

				snvs_rtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap = <&snvs>;
					offset = <0x34>;
					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_SNVS_CLK>;
					clock-names = "snvs-rtc";
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_SNVS_CLK>;
					clock-names = "snvs-pwrkey";
					linux,keycode = <KEY_POWER>;
					wakeup-source;
					status = "disabled";
				};
			};

			clks: clock-controller@30380000 {
				compatible = "fsl,imx7d-ccm";
				reg = <0x30380000 0x10000>;
				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				#clock-cells = <1>;
				clocks = <&ckil>, <&osc>;
				clock-names = "ckil", "osc";
			};

			src: reset-controller@30390000 {
				compatible = "fsl,imx7d-src", "syscon";
				reg = <0x30390000 0x10000>;
				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};

			gpc: gpc@303a0000 {
				compatible = "fsl,imx7d-gpc";
				reg = <0x303a0000 0x10000>;
				interrupt-controller;
				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <3>;
				interrupt-parent = <&intc>;
				#power-domain-cells = <1>;

				pgc {
					#address-cells = <1>;
					#size-cells = <0>;

					pgc_mipi_phy: power-domain@0 {
						#power-domain-cells = <0>;
						reg = <0>;
						power-supply = <&reg_1p0d>;
					};

					pgc_pcie_phy: power-domain@1 {
						#power-domain-cells = <0>;
						reg = <1>;
						power-supply = <&reg_1p0d>;
					};

					pgc_hsic_phy: power-domain@2 {
						#power-domain-cells = <0>;
						reg = <2>;
						power-supply = <&reg_1p2>;
					};
				};
			};
		};

		aips2: bus@30400000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x30400000 0x400000>;
			ranges;

			adc1: adc@30610000 {
				compatible = "fsl,imx7d-adc";
				reg = <0x30610000 0x10000>;
				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_ADC_ROOT_CLK>;
				clock-names = "adc";
				#io-channel-cells = <1>;
				status = "disabled";
			};

			adc2: adc@30620000 {
				compatible = "fsl,imx7d-adc";
				reg = <0x30620000 0x10000>;
				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_ADC_ROOT_CLK>;
				clock-names = "adc";
				#io-channel-cells = <1>;
				status = "disabled";
			};

			ecspi4: spi@30630000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
				reg = <0x30630000 0x10000>;
				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
					<&clks IMX7D_ECSPI4_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			ftm1: pwm@30640000 {
				compatible = "fsl,vf610-ftm-pwm";
				reg = <0x30640000 0x10000>;
				#pwm-cells = <3>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
				clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
					<&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
					<&clks IMX7D_FLEXTIMER1_ROOT_CLK>,
					<&clks IMX7D_FLEXTIMER1_ROOT_CLK>;
				status = "disabled";
			};

			ftm2: pwm@30650000 {
				compatible = "fsl,vf610-ftm-pwm";
				reg = <0x30650000 0x10000>;
				#pwm-cells = <3>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clock-names = "ftm_sys", "ftm_ext",
				"ftm_fix", "ftm_cnt_clk_en";
				clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
					<&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
					<&clks IMX7D_FLEXTIMER2_ROOT_CLK>,
					<&clks IMX7D_FLEXTIMER2_ROOT_CLK>;
				status = "disabled";
			};

			pwm1: pwm@30660000 {
				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
				reg = <0x30660000 0x10000>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
					 <&clks IMX7D_PWM1_ROOT_CLK>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm2: pwm@30670000 {
				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
				reg = <0x30670000 0x10000>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
					 <&clks IMX7D_PWM2_ROOT_CLK>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm3: pwm@30680000 {
				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
				reg = <0x30680000 0x10000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
					 <&clks IMX7D_PWM3_ROOT_CLK>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm4: pwm@30690000 {
				compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
				reg = <0x30690000 0x10000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
					 <&clks IMX7D_PWM4_ROOT_CLK>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			csi: csi@30710000 {
				compatible = "fsl,imx7-csi";
				reg = <0x30710000 0x10000>;
				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					 <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
					 <&clks IMX7D_CLK_DUMMY>;
				clock-names = "axi", "mclk", "dcic";
				status = "disabled";

				port {
					csi_from_csi_mux: endpoint {
						remote-endpoint = <&csi_mux_to_csi>;
					};
				};
			};

			lcdif: lcdif@30730000 {
				compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
				reg = <0x30730000 0x10000>;
				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
					<&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
				clock-names = "pix", "axi";
				status = "disabled";
			};

			mipi_csi: mipi-csi@30750000 {
				compatible = "fsl,imx7-mipi-csi2";
				reg = <0x30750000 0x10000>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
					 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
					 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
				clock-names = "pclk", "wrap", "phy";
				power-domains = <&pgc_mipi_phy>;
				phy-supply = <&reg_1p0d>;
				resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
					};

					port@1 {
						reg = <1>;

						mipi_vc0_to_csi_mux: endpoint {
							remote-endpoint = <&csi_mux_from_mipi_vc0>;
						};
					};
				};
			};
		};

		aips3: bus@30800000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x30800000 0x400000>;
			ranges;

			spba-bus@30800000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x30800000 0x100000>;
				ranges;

				ecspi1: spi@30820000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
					reg = <0x30820000 0x10000>;
					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
						<&clks IMX7D_ECSPI1_ROOT_CLK>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi2: spi@30830000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
					reg = <0x30830000 0x10000>;
					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
						<&clks IMX7D_ECSPI2_ROOT_CLK>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi3: spi@30840000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
					reg = <0x30840000 0x10000>;
					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
						<&clks IMX7D_ECSPI3_ROOT_CLK>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				uart1: serial@30860000 {
					compatible = "fsl,imx7d-uart",
						     "fsl,imx6q-uart";
					reg = <0x30860000 0x10000>;
					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_UART1_ROOT_CLK>,
						<&clks IMX7D_UART1_ROOT_CLK>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				uart2: serial@30890000 {
					compatible = "fsl,imx7d-uart",
						     "fsl,imx6q-uart";
					reg = <0x30890000 0x10000>;
					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_UART2_ROOT_CLK>,
						<&clks IMX7D_UART2_ROOT_CLK>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				uart3: serial@30880000 {
					compatible = "fsl,imx7d-uart",
						     "fsl,imx6q-uart";
					reg = <0x30880000 0x10000>;
					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_UART3_ROOT_CLK>,
						<&clks IMX7D_UART3_ROOT_CLK>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				sai1: sai@308a0000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
					reg = <0x308a0000 0x10000>;
					interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_SAI1_IPG_CLK>,
						 <&clks IMX7D_SAI1_ROOT_CLK>,
						 <&clks IMX7D_CLK_DUMMY>,
						 <&clks IMX7D_CLK_DUMMY>;
					clock-names = "bus", "mclk1", "mclk2", "mclk3";
					dma-names = "rx", "tx";
					dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
					status = "disabled";
				};

				sai2: sai@308b0000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
					reg = <0x308b0000 0x10000>;
					interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_SAI2_IPG_CLK>,
						 <&clks IMX7D_SAI2_ROOT_CLK>,
						 <&clks IMX7D_CLK_DUMMY>,
						 <&clks IMX7D_CLK_DUMMY>;
					clock-names = "bus", "mclk1", "mclk2", "mclk3";
					dma-names = "rx", "tx";
					dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
					status = "disabled";
				};

				sai3: sai@308c0000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
					reg = <0x308c0000 0x10000>;
					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX7D_SAI3_IPG_CLK>,
						 <&clks IMX7D_SAI3_ROOT_CLK>,
						 <&clks IMX7D_CLK_DUMMY>,
						 <&clks IMX7D_CLK_DUMMY>;
					clock-names = "bus", "mclk1", "mclk2", "mclk3";
					dma-names = "rx", "tx";
					dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
					status = "disabled";
				};
			};

			crypto: crypto@30900000 {
				compatible = "fsl,sec-v4.0";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x30900000 0x40000>;
				ranges = <0 0x30900000 0x40000>;
				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CAAM_CLK>,
					 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
				clock-names = "ipg", "aclk";

				sec_jr0: jr@1000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x1000 0x1000>;
					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr1: jr@2000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x2000 0x1000>;
					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr2: jr@3000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x3000 0x1000>;
					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			flexcan1: can@30a00000 {
				compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
				reg = <0x30a00000 0x10000>;
				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_CAN1_ROOT_CLK>;
				clock-names = "ipg", "per";
				fsl,stop-mode = <&gpr 0x10 1>;
				status = "disabled";
			};

			flexcan2: can@30a10000 {
				compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
				reg = <0x30a10000 0x10000>;
				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_CLK_DUMMY>,
					<&clks IMX7D_CAN2_ROOT_CLK>;
				clock-names = "ipg", "per";
				fsl,stop-mode = <&gpr 0x10 2>;
				status = "disabled";
			};

			i2c1: i2c@30a20000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
				reg = <0x30a20000 0x10000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
				status = "disabled";
			};

			i2c2: i2c@30a30000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
				reg = <0x30a30000 0x10000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
				status = "disabled";
			};

			i2c3: i2c@30a40000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
				reg = <0x30a40000 0x10000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
				status = "disabled";
			};

			i2c4: i2c@30a50000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
				reg = <0x30a50000 0x10000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
				status = "disabled";
			};

			uart4: serial@30a60000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart";
				reg = <0x30a60000 0x10000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART4_ROOT_CLK>,
					<&clks IMX7D_UART4_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart5: serial@30a70000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart";
				reg = <0x30a70000 0x10000>;
				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART5_ROOT_CLK>,
					<&clks IMX7D_UART5_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart6: serial@30a80000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart";
				reg = <0x30a80000 0x10000>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART6_ROOT_CLK>,
					<&clks IMX7D_UART6_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart7: serial@30a90000 {
				compatible = "fsl,imx7d-uart",
					     "fsl,imx6q-uart";
				reg = <0x30a90000 0x10000>;
				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_UART7_ROOT_CLK>,
					<&clks IMX7D_UART7_ROOT_CLK>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			mu0a: mailbox@30aa0000 {
				compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
				reg = <0x30aa0000 0x10000>;
				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_MU_ROOT_CLK>;
				#mbox-cells = <2>;
				status = "disabled";
			};

			mu0b: mailbox@30ab0000 {
				compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
				reg = <0x30ab0000 0x10000>;
				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_MU_ROOT_CLK>;
				#mbox-cells = <2>;
				fsl,mu-side-b;
				status = "disabled";
			};

			usbotg1: usb@30b10000 {
				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
				reg = <0x30b10000 0x200>;
				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_USB_CTRL_CLK>;
				fsl,usbphy = <&usbphynop1>;
				fsl,usbmisc = <&usbmisc1 0>;
				phy-clkgate-delay-us = <400>;
				status = "disabled";
			};

			usbh: usb@30b30000 {
				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
				reg = <0x30b30000 0x200>;
				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_USB_CTRL_CLK>;
				fsl,usbphy = <&usbphynop3>;
				fsl,usbmisc = <&usbmisc3 0>;
				phy_type = "hsic";
				dr_mode = "host";
				phy-clkgate-delay-us = <400>;
				status = "disabled";
			};

			usbmisc1: usbmisc@30b10200 {
				#index-cells = <1>;
				compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
				reg = <0x30b10200 0x200>;
			};

			usbmisc3: usbmisc@30b30200 {
				#index-cells = <1>;
				compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
				reg = <0x30b30200 0x200>;
			};

			usdhc1: mmc@30b40000 {
				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x30b40000 0x10000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
					<&clks IMX7D_USDHC1_ROOT_CLK>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@30b50000 {
				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x30b50000 0x10000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
					<&clks IMX7D_USDHC2_ROOT_CLK>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc3: mmc@30b60000 {
				compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x30b60000 0x10000>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
					<&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
					<&clks IMX7D_USDHC3_ROOT_CLK>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			qspi: spi@30bb0000 {
				compatible = "fsl,imx7d-qspi";
				reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
					<&clks IMX7D_QSPI_ROOT_CLK>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			sdma: dma-controller@30bd0000 {
				compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
				reg = <0x30bd0000 0x10000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
					 <&clks IMX7D_SDMA_CORE_CLK>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			fec1: ethernet@30be0000 {
				compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
				reg = <0x30be0000 0x10000>;
				interrupt-names = "int0", "int1", "int2", "pps";
				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
					<&clks IMX7D_ENET_AXI_ROOT_CLK>,
					<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
					<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
					<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
				clock-names = "ipg", "ahb", "ptp",
					"enet_clk_ref", "enet_out";
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				fsl,stop-mode = <&gpr 0x10 3>;
				status = "disabled";
			};
		};

		dma_apbh: dma-apbh@33000000 {
			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
			reg = <0x33000000 0x2000>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
			#dma-cells = <1>;
			dma-channels = <4>;
			clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
		};

		gpmi: nand-controller@33002000{
			compatible = "fsl,imx7d-gpmi-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
			reg-names = "gpmi-nand", "bch";
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "bch";
			clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
				<&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
			clock-names = "gpmi_io", "gpmi_bch_apb";
			dmas = <&dma_apbh 0>;
			dma-names = "rx-tx";
			status = "disabled";
			assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
			assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2019 NXP

/dts-v1/;

#include "imx7ulp.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Embedded Artists i.MX7ULP COM";
	compatible = "ea,imx7ulp-com", "fsl,imx7ulp";

	chosen {
		stdout-path = &lpuart4;
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x4000000>;
	};
};

&lpuart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart4>;
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1_id>;
	srp-disable;
	hnp-disable;
	adp-disable;
	status = "okay";
};

&usdhc0 {
	assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
	assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc0>;
	non-removable;
	bus-width = <8>;
	no-1-8-v;
	status = "okay";
};

&iomuxc1 {
	pinctrl_lpuart4: lpuart4grp {
		fsl,pins = <
			IMX7ULP_PAD_PTC3__LPUART4_RX	0x3
			IMX7ULP_PAD_PTC2__LPUART4_TX	0x3
		>;
	};

	pinctrl_usbotg1_id: otg1idgrp {
		fsl,pins = <
			IMX7ULP_PAD_PTC13__USB0_ID	0x10003
		>;
	};

	pinctrl_usdhc0: usdhc0grp {
		fsl,pins = <
			IMX7ULP_PAD_PTD1__SDHC0_CMD	0x43
			IMX7ULP_PAD_PTD2__SDHC0_CLK	0x10042
			IMX7ULP_PAD_PTD3__SDHC0_D7	0x43
			IMX7ULP_PAD_PTD4__SDHC0_D6	0x43
			IMX7ULP_PAD_PTD5__SDHC0_D5	0x43
			IMX7ULP_PAD_PTD6__SDHC0_D4	0x43
			IMX7ULP_PAD_PTD7__SDHC0_D3	0x43
			IMX7ULP_PAD_PTD8__SDHC0_D2	0x43
			IMX7ULP_PAD_PTD9__SDHC0_D1	0x43
			IMX7ULP_PAD_PTD10__SDHC0_D0	0x43
			IMX7ULP_PAD_PTD11__SDHC0_DQS	0x42
		>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017-2018 NXP
 *   Dong Aisheng <aisheng.dong@nxp.com>
 */

/dts-v1/;

#include "imx7ulp.dtsi"

/ {
	model = "NXP i.MX7ULP EVK";
	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";

	chosen {
		stdout-path = &lpuart4;
	};

	memory@60000000 {
		device_type = "memory";
		reg = <0x60000000 0x40000000>;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&tpm4 1 50000 0>;
		brightness-levels = <0 20 25 30 35 40 100>;
		default-brightness-level = <6>;
		status = "okay";
	};

	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbotg1_vbus>;
		regulator-name = "usb_otg1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_vsd_3v3: regulator-vsd-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc0_rst>;
		gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&lpuart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart4>;
	status = "okay";
};

&tpm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm0>;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1_id>;
	srp-disable;
	hnp-disable;
	adp-disable;
	disable-over-current;
	status = "okay";
};

&usdhc0 {
	assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
	assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc0>;
	cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_vsd_3v3>;
	status = "okay";
};

&iomuxc1 {
	pinctrl_lpuart4: lpuart4grp {
		fsl,pins = <
			IMX7ULP_PAD_PTC3__LPUART4_RX	0x3
			IMX7ULP_PAD_PTC2__LPUART4_TX	0x3
		>;
		bias-pull-up;
	};

	pinctrl_pwm0: pwm0grp {
		fsl,pins = <
			IMX7ULP_PAD_PTF2__TPM4_CH1	0x2
		>;
	};

	pinctrl_usbotg1_vbus: otg1vbusgrp {
		fsl,pins = <
			IMX7ULP_PAD_PTC0__PTC0		0x20000
		>;
	};

	pinctrl_usbotg1_id: otg1idgrp {
		fsl,pins = <
			IMX7ULP_PAD_PTC13__USB0_ID	0x10003
		>;
	};

	pinctrl_usdhc0: usdhc0grp {
		fsl,pins = <
			IMX7ULP_PAD_PTD1__SDHC0_CMD	0x43
			IMX7ULP_PAD_PTD2__SDHC0_CLK	0x40
			IMX7ULP_PAD_PTD7__SDHC0_D3	0x43
			IMX7ULP_PAD_PTD8__SDHC0_D2	0x43
			IMX7ULP_PAD_PTD9__SDHC0_D1	0x43
			IMX7ULP_PAD_PTD10__SDHC0_D0	0x43
			IMX7ULP_PAD_PTC10__PTC10	0x3	/* CD */
		>;
	};

	pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
		fsl,pins = <
			IMX7ULP_PAD_PTD0__PTD0		0x3
		>;
	};
};


code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 */

#ifndef __DTS_IMX7ULP_PINFUNC_H
#define __DTS_IMX7ULP_PINFUNC_H

/*
 * The pin function ID is a tuple of
 * <mux_conf_reg input_reg mux_mode input_val>
 */

#define IMX7ULP_PAD_PTC0__PTC0                                       0x0000 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC0__TRACE_D15                                  0x0000 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B                              0x0000 0x0244 0x4 0x1
#define IMX7ULP_PAD_PTC0__LPI2C4_SCL                                 0x0000 0x0278 0x5 0x1
#define IMX7ULP_PAD_PTC0__TPM4_CLKIN                                 0x0000 0x0298 0x6 0x1
#define IMX7ULP_PAD_PTC0__FB_AD0                                     0x0000 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC1__PTC1                                       0x0004 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC1__TRACE_D14                                  0x0004 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B                              0x0004 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC1__LPI2C4_SDA                                 0x0004 0x027c 0x5 0x1
#define IMX7ULP_PAD_PTC1__TPM4_CH0                                   0x0004 0x0280 0x6 0x1
#define IMX7ULP_PAD_PTC1__FB_AD1                                     0x0004 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC2__PTC2                                       0x0008 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC2__TRACE_D13                                  0x0008 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC2__LPUART4_TX                                 0x0008 0x024c 0x4 0x1
#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ                                0x0008 0x0274 0x5 0x1
#define IMX7ULP_PAD_PTC2__TPM4_CH1                                   0x0008 0x0284 0x6 0x1
#define IMX7ULP_PAD_PTC2__FB_AD2                                     0x0008 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC3__PTC3                                       0x000c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC3__TRACE_D12                                  0x000c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC3__LPUART4_RX                                 0x000c 0x0248 0x4 0x1
#define IMX7ULP_PAD_PTC3__TPM4_CH2                                   0x000c 0x0288 0x6 0x1
#define IMX7ULP_PAD_PTC3__FB_AD3                                     0x000c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC4__PTC4                                       0x0010 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC4__TRACE_D11                                  0x0010 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC4__FXIO1_D0                                   0x0010 0x0204 0x2 0x1
#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1                                0x0010 0x02a0 0x3 0x1
#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B                              0x0010 0x0250 0x4 0x1
#define IMX7ULP_PAD_PTC4__LPI2C5_SCL                                 0x0010 0x02bc 0x5 0x1
#define IMX7ULP_PAD_PTC4__TPM4_CH3                                   0x0010 0x028c 0x6 0x1
#define IMX7ULP_PAD_PTC4__FB_AD4                                     0x0010 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC5__PTC5                                       0x0014 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC5__TRACE_D10                                  0x0014 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC5__FXIO1_D1                                   0x0014 0x0208 0x2 0x1
#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2                                0x0014 0x02a4 0x3 0x1
#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B                              0x0014 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC5__LPI2C5_SDA                                 0x0014 0x02c0 0x5 0x1
#define IMX7ULP_PAD_PTC5__TPM4_CH4                                   0x0014 0x0290 0x6 0x1
#define IMX7ULP_PAD_PTC5__FB_AD5                                     0x0014 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC6__PTC6                                       0x0018 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC6__TRACE_D9                                   0x0018 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC6__FXIO1_D2                                   0x0018 0x020c 0x2 0x1
#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3                                0x0018 0x02a8 0x3 0x1
#define IMX7ULP_PAD_PTC6__LPUART5_TX                                 0x0018 0x0258 0x4 0x1
#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ                                0x0018 0x02b8 0x5 0x1
#define IMX7ULP_PAD_PTC6__TPM4_CH5                                   0x0018 0x0294 0x6 0x1
#define IMX7ULP_PAD_PTC6__FB_AD6                                     0x0018 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC7__PTC7                                       0x001c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC7__TRACE_D8                                   0x001c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC7__FXIO1_D3                                   0x001c 0x0210 0x2 0x1
#define IMX7ULP_PAD_PTC7__LPUART5_RX                                 0x001c 0x0254 0x4 0x1
#define IMX7ULP_PAD_PTC7__TPM5_CH1                                   0x001c 0x02c8 0x6 0x1
#define IMX7ULP_PAD_PTC7__FB_AD7                                     0x001c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC8__PTC8                                       0x0020 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC8__TRACE_D7                                   0x0020 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC8__FXIO1_D4                                   0x0020 0x0214 0x2 0x1
#define IMX7ULP_PAD_PTC8__LPSPI2_SIN                                 0x0020 0x02b0 0x3 0x1
#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B                              0x0020 0x025c 0x4 0x1
#define IMX7ULP_PAD_PTC8__LPI2C6_SCL                                 0x0020 0x02fc 0x5 0x1
#define IMX7ULP_PAD_PTC8__TPM5_CLKIN                                 0x0020 0x02cc 0x6 0x1
#define IMX7ULP_PAD_PTC8__FB_AD8                                     0x0020 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC9__PTC9                                       0x0024 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC9__TRACE_D6                                   0x0024 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC9__FXIO1_D5                                   0x0024 0x0218 0x2 0x1
#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT                                0x0024 0x02b4 0x3 0x1
#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B                              0x0024 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC9__LPI2C6_SDA                                 0x0024 0x0300 0x5 0x1
#define IMX7ULP_PAD_PTC9__TPM5_CH0                                   0x0024 0x02c4 0x6 0x1
#define IMX7ULP_PAD_PTC9__FB_AD9                                     0x0024 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC10__PTC10                                     0x0028 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC10__TRACE_D5                                  0x0028 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC10__FXIO1_D6                                  0x0028 0x021c 0x2 0x1
#define IMX7ULP_PAD_PTC10__LPSPI2_SCK                                0x0028 0x02ac 0x3 0x1
#define IMX7ULP_PAD_PTC10__LPUART6_TX                                0x0028 0x0264 0x4 0x1
#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ                               0x0028 0x02f8 0x5 0x1
#define IMX7ULP_PAD_PTC10__TPM7_CH3                                  0x0028 0x02e8 0x6 0x1
#define IMX7ULP_PAD_PTC10__FB_AD10                                   0x0028 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC11__PTC11                                     0x002c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC11__TRACE_D4                                  0x002c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC11__FXIO1_D7                                  0x002c 0x0220 0x2 0x1
#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0                               0x002c 0x029c 0x3 0x1
#define IMX7ULP_PAD_PTC11__LPUART6_RX                                0x002c 0x0260 0x4 0x1
#define IMX7ULP_PAD_PTC11__TPM7_CH4                                  0x002c 0x02ec 0x6 0x1
#define IMX7ULP_PAD_PTC11__FB_AD11                                   0x002c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC12__PTC12                                     0x0030 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC12__TRACE_D3                                  0x0030 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC12__FXIO1_D8                                  0x0030 0x0224 0x2 0x1
#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1                               0x0030 0x0314 0x3 0x1
#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B                             0x0030 0x0268 0x4 0x1
#define IMX7ULP_PAD_PTC12__LPI2C7_SCL                                0x0030 0x0308 0x5 0x1
#define IMX7ULP_PAD_PTC12__TPM7_CH5                                  0x0030 0x02f0 0x6 0x1
#define IMX7ULP_PAD_PTC12__FB_AD12                                   0x0030 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC13__PTC13                                     0x0034 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC13__TRACE_D2                                  0x0034 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC13__FXIO1_D9                                  0x0034 0x0228 0x2 0x1
#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2                               0x0034 0x0318 0x3 0x1
#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B                             0x0034 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC13__LPI2C7_SDA                                0x0034 0x030c 0x5 0x1
#define IMX7ULP_PAD_PTC13__TPM7_CLKIN                                0x0034 0x02f4 0x6 0x1
#define IMX7ULP_PAD_PTC13__FB_AD13                                   0x0034 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC13__USB0_ID                                   0x0034 0x0338 0xb 0x1
#define IMX7ULP_PAD_PTC14__PTC14                                     0x0038 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC14__TRACE_D1                                  0x0038 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC14__FXIO1_D10                                 0x0038 0x022c 0x2 0x1
#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3                               0x0038 0x031c 0x3 0x1
#define IMX7ULP_PAD_PTC14__LPUART7_TX                                0x0038 0x0270 0x4 0x1
#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ                               0x0038 0x0304 0x5 0x1
#define IMX7ULP_PAD_PTC14__TPM7_CH0                                  0x0038 0x02dc 0x6 0x1
#define IMX7ULP_PAD_PTC14__FB_AD14                                   0x0038 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC15__PTC15                                     0x003c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC15__TRACE_D0                                  0x003c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC15__FXIO1_D11                                 0x003c 0x0230 0x2 0x1
#define IMX7ULP_PAD_PTC15__LPUART7_RX                                0x003c 0x026c 0x4 0x1
#define IMX7ULP_PAD_PTC15__TPM7_CH1                                  0x003c 0x02e0 0x6 0x1
#define IMX7ULP_PAD_PTC15__FB_AD15                                   0x003c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC16__PTC16                                     0x0040 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT                              0x0040 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC16__FXIO1_D12                                 0x0040 0x0234 0x2 0x1
#define IMX7ULP_PAD_PTC16__LPSPI3_SIN                                0x0040 0x0324 0x3 0x1
#define IMX7ULP_PAD_PTC16__TPM7_CH2                                  0x0040 0x02e4 0x6 0x1
#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B                   0x0040 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC16__USB1_OC2                                  0x0040 0x0334 0xb 0x1
#define IMX7ULP_PAD_PTC17__PTC17                                     0x0044 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC17__FXIO1_D13                                 0x0044 0x0238 0x2 0x1
#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT                               0x0044 0x0328 0x3 0x1
#define IMX7ULP_PAD_PTC17__TPM6_CLKIN                                0x0044 0x02d8 0x6 0x1
#define IMX7ULP_PAD_PTC17__FB_CS0_B                                  0x0044 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC18__PTC18                                     0x0048 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC18__FXIO1_D14                                 0x0048 0x023c 0x2 0x1
#define IMX7ULP_PAD_PTC18__LPSPI3_SCK                                0x0048 0x0320 0x3 0x1
#define IMX7ULP_PAD_PTC18__TPM6_CH0                                  0x0048 0x02d0 0x6 0x1
#define IMX7ULP_PAD_PTC18__FB_OE_B                                   0x0048 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC18__USB0_ID                                   0x0048 0x0338 0xb 0x2
#define IMX7ULP_PAD_PTC18__VIU_DE                                    0x0048 0x033c 0xc 0x1
#define IMX7ULP_PAD_PTC19__PTC19                                     0x004c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC19__FXIO1_D15                                 0x004c 0x0240 0x2 0x1
#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0                               0x004c 0x0310 0x3 0x1
#define IMX7ULP_PAD_PTC19__TPM6_CH1                                  0x004c 0x02d4 0x6 0x1
#define IMX7ULP_PAD_PTC19__FB_A16                                    0x004c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC19__USB0_ID                                   0x004c 0x0338 0xa 0x3
#define IMX7ULP_PAD_PTC19__USB1_PWR2                                 0x004c 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTC19__VIU_DE                                    0x004c 0x033c 0xc 0x3
#define IMX7ULP_PAD_PTD0__PTD0                                       0x0080 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B                              0x0080 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD1__PTD1                                       0x0084 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD1__SDHC0_CMD                                  0x0084 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD2__PTD2                                       0x0088 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD2__SDHC0_CLK                                  0x0088 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD3__PTD3                                       0x008c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD3__SDHC0_D7                                   0x008c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD4__PTD4                                       0x0090 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD4__SDHC0_D6                                   0x0090 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD5__PTD5                                       0x0094 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD5__SDHC0_D5                                   0x0094 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD6__PTD6                                       0x0098 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD6__SDHC0_D4                                   0x0098 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD7__PTD7                                       0x009c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD7__SDHC0_D3                                   0x009c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD8__PTD8                                       0x00a0 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD8__TPM4_CLKIN                                 0x00a0 0x0298 0x6 0x2
#define IMX7ULP_PAD_PTD8__SDHC0_D2                                   0x00a0 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD9__PTD9                                       0x00a4 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD9__TPM4_CH0                                   0x00a4 0x0280 0x6 0x2
#define IMX7ULP_PAD_PTD9__SDHC0_D1                                   0x00a4 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD10__PTD10                                     0x00a8 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD10__TPM4_CH1                                  0x00a8 0x0284 0x6 0x2
#define IMX7ULP_PAD_PTD10__SDHC0_D0                                  0x00a8 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD11__PTD11                                     0x00ac 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD11__TPM4_CH2                                  0x00ac 0x0288 0x6 0x2
#define IMX7ULP_PAD_PTD11__SDHC0_DQS                                 0x00ac 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE0__PTE0                                       0x0100 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE0__FXIO1_D31                                  0x0100 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1                                0x0100 0x02a0 0x3 0x2
#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B                              0x0100 0x0244 0x4 0x2
#define IMX7ULP_PAD_PTE0__LPI2C4_SCL                                 0x0100 0x0278 0x5 0x2
#define IMX7ULP_PAD_PTE0__SDHC1_D1                                   0x0100 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE0__FB_A25                                     0x0100 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE1__PTE1                                       0x0104 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE1__FXIO1_D30                                  0x0104 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2                                0x0104 0x02a4 0x3 0x2
#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B                              0x0104 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE1__LPI2C4_SDA                                 0x0104 0x027c 0x5 0x2
#define IMX7ULP_PAD_PTE1__SDHC1_D0                                   0x0104 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE1__FB_A26                                     0x0104 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE2__PTE2                                       0x0108 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE2__FXIO1_D29                                  0x0108 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3                                0x0108 0x02a8 0x3 0x2
#define IMX7ULP_PAD_PTE2__LPUART4_TX                                 0x0108 0x024c 0x4 0x2
#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ                                0x0108 0x0274 0x5 0x2
#define IMX7ULP_PAD_PTE2__SDHC1_CLK                                  0x0108 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE3__PTE3                                       0x010c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE3__FXIO1_D28                                  0x010c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE3__LPUART4_RX                                 0x010c 0x0248 0x4 0x2
#define IMX7ULP_PAD_PTE3__TPM5_CH1                                   0x010c 0x02c8 0x6 0x2
#define IMX7ULP_PAD_PTE3__SDHC1_CMD                                  0x010c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE4__PTE4                                       0x0110 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE4__FXIO1_D27                                  0x0110 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE4__LPSPI2_SIN                                 0x0110 0x02b0 0x3 0x2
#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B                              0x0110 0x0250 0x4 0x2
#define IMX7ULP_PAD_PTE4__LPI2C5_SCL                                 0x0110 0x02bc 0x5 0x2
#define IMX7ULP_PAD_PTE4__TPM5_CLKIN                                 0x0110 0x02cc 0x6 0x2
#define IMX7ULP_PAD_PTE4__SDHC1_D3                                   0x0110 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE5__PTE5                                       0x0114 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE5__FXIO1_D26                                  0x0114 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT                                0x0114 0x02b4 0x3 0x2
#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B                              0x0114 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE5__LPI2C5_SDA                                 0x0114 0x02c0 0x5 0x2
#define IMX7ULP_PAD_PTE5__TPM5_CH0                                   0x0114 0x02c4 0x6 0x2
#define IMX7ULP_PAD_PTE5__SDHC1_D2                                   0x0114 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE5__VIU_DE                                     0x0114 0x033c 0xc 0x2
#define IMX7ULP_PAD_PTE6__PTE6                                       0x0118 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE6__FXIO1_D25                                  0x0118 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE6__LPSPI2_SCK                                 0x0118 0x02ac 0x3 0x2
#define IMX7ULP_PAD_PTE6__LPUART5_TX                                 0x0118 0x0258 0x4 0x2
#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ                                0x0118 0x02b8 0x5 0x2
#define IMX7ULP_PAD_PTE6__TPM7_CH3                                   0x0118 0x02e8 0x6 0x2
#define IMX7ULP_PAD_PTE6__SDHC1_D4                                   0x0118 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE6__FB_A17                                     0x0118 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE6__USB0_OC                                    0x0118 0x0330 0xb 0x1
#define IMX7ULP_PAD_PTE7__PTE7                                       0x011c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE7__TRACE_D7                                   0x011c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE7__USB0_PWR                                   0x011c 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTE7__VIU_FID                                    0x011c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE7__FXIO1_D24                                  0x011c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0                                0x011c 0x029c 0x3 0x2
#define IMX7ULP_PAD_PTE7__LPUART5_RX                                 0x011c 0x0254 0x4 0x2
#define IMX7ULP_PAD_PTE7__TPM7_CH4                                   0x011c 0x02ec 0x6 0x2
#define IMX7ULP_PAD_PTE7__SDHC1_D5                                   0x011c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE7__FB_A18                                     0x011c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE8__PTE8                                       0x0120 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE8__TRACE_D6                                   0x0120 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE8__VIU_D16                                    0x0120 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE8__FXIO1_D23                                  0x0120 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1                                0x0120 0x0314 0x3 0x2
#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B                              0x0120 0x025c 0x4 0x2
#define IMX7ULP_PAD_PTE8__LPI2C6_SCL                                 0x0120 0x02fc 0x5 0x2
#define IMX7ULP_PAD_PTE8__TPM7_CH5                                   0x0120 0x02f0 0x6 0x2
#define IMX7ULP_PAD_PTE8__SDHC1_WP                                   0x0120 0x0200 0x7 0x1
#define IMX7ULP_PAD_PTE8__SDHC1_D6                                   0x0120 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B               0x0120 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE9__PTE9                                       0x0124 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE9__TRACE_D5                                   0x0124 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE9__VIU_D17                                    0x0124 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE9__FXIO1_D22                                  0x0124 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2                                0x0124 0x0318 0x3 0x2
#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B                              0x0124 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE9__LPI2C6_SDA                                 0x0124 0x0300 0x5 0x2
#define IMX7ULP_PAD_PTE9__TPM7_CLKIN                                 0x0124 0x02f4 0x6 0x2
#define IMX7ULP_PAD_PTE9__SDHC1_CD                                   0x0124 0x032c 0x7 0x1
#define IMX7ULP_PAD_PTE9__SDHC1_D7                                   0x0124 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B    0x0124 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE10__PTE10                                     0x0128 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE10__TRACE_D4                                  0x0128 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE10__VIU_D18                                   0x0128 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE10__FXIO1_D21                                 0x0128 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3                               0x0128 0x031c 0x3 0x2
#define IMX7ULP_PAD_PTE10__LPUART6_TX                                0x0128 0x0264 0x4 0x2
#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ                               0x0128 0x02f8 0x5 0x2
#define IMX7ULP_PAD_PTE10__TPM7_CH0                                  0x0128 0x02dc 0x6 0x2
#define IMX7ULP_PAD_PTE10__SDHC1_VS                                  0x0128 0x0000 0x7 0x0
#define IMX7ULP_PAD_PTE10__SDHC1_DQS                                 0x0128 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE10__FB_A19                                    0x0128 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE11__PTE11                                     0x012c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE11__TRACE_D3                                  0x012c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE11__VIU_D19                                   0x012c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE11__FXIO1_D20                                 0x012c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE11__LPUART6_RX                                0x012c 0x0260 0x4 0x2
#define IMX7ULP_PAD_PTE11__TPM7_CH1                                  0x012c 0x02e0 0x6 0x2
#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B                             0x012c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE11__FB_A20                                    0x012c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE12__PTE12                                     0x0130 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE12__TRACE_D2                                  0x0130 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE12__USB1_OC2                                  0x0130 0x0334 0xb 0x2
#define IMX7ULP_PAD_PTE12__VIU_D20                                   0x0130 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE12__FXIO1_D19                                 0x0130 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE12__LPSPI3_SIN                                0x0130 0x0324 0x3 0x2
#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B                             0x0130 0x0268 0x4 0x2
#define IMX7ULP_PAD_PTE12__LPI2C7_SCL                                0x0130 0x0308 0x5 0x2
#define IMX7ULP_PAD_PTE12__TPM7_CH2                                  0x0130 0x02e4 0x6 0x2
#define IMX7ULP_PAD_PTE12__SDHC1_WP                                  0x0130 0x0200 0x8 0x2
#define IMX7ULP_PAD_PTE12__FB_A21                                    0x0130 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE13__PTE13                                     0x0134 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE13__TRACE_D1                                  0x0134 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE13__USB1_PWR2                                 0x0134 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTE13__VIU_D21                                   0x0134 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE13__FXIO1_D18                                 0x0134 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT                               0x0134 0x0328 0x3 0x2
#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B                             0x0134 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE13__LPI2C7_SDA                                0x0134 0x030c 0x5 0x2
#define IMX7ULP_PAD_PTE13__TPM6_CLKIN                                0x0134 0x02d8 0x6 0x2
#define IMX7ULP_PAD_PTE13__SDHC1_CD                                  0x0134 0x032c 0x8 0x2
#define IMX7ULP_PAD_PTE13__FB_A22                                    0x0134 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE14__PTE14                                     0x0138 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE14__TRACE_D0                                  0x0138 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE14__USB0_OC                                   0x0138 0x0330 0xb 0x2
#define IMX7ULP_PAD_PTE14__VIU_D22                                   0x0138 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE14__FXIO1_D17                                 0x0138 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE14__LPSPI3_SCK                                0x0138 0x0320 0x3 0x2
#define IMX7ULP_PAD_PTE14__LPUART7_TX                                0x0138 0x0270 0x4 0x2
#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ                               0x0138 0x0304 0x5 0x2
#define IMX7ULP_PAD_PTE14__TPM6_CH0                                  0x0138 0x02d0 0x6 0x2
#define IMX7ULP_PAD_PTE14__SDHC1_VS                                  0x0138 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE14__FB_A23                                    0x0138 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE15__PTE15                                     0x013c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT                              0x013c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE15__USB0_PWR                                  0x013c 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTE15__VIU_D23                                   0x013c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE15__FXIO1_D16                                 0x013c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0                               0x013c 0x0310 0x3 0x2
#define IMX7ULP_PAD_PTE15__LPUART7_RX                                0x013c 0x026c 0x4 0x2
#define IMX7ULP_PAD_PTE15__TPM6_CH1                                  0x013c 0x02d4 0x6 0x2
#define IMX7ULP_PAD_PTE15__FB_A24                                    0x013c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF0__PTF0                                       0x0180 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF0__VIU_DE                                     0x0180 0x033c 0xc 0x0
#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B                              0x0180 0x0244 0x4 0x3
#define IMX7ULP_PAD_PTF0__LPI2C4_SCL                                 0x0180 0x0278 0x5 0x3
#define IMX7ULP_PAD_PTF0__TPM4_CLKIN                                 0x0180 0x0298 0x6 0x3
#define IMX7ULP_PAD_PTF0__FB_RW_B                                    0x0180 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF1__PTF1                                       0x0184 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF1__VIU_HSYNC                                  0x0184 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B                              0x0184 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTF1__LPI2C4_SDA                                 0x0184 0x027c 0x5 0x3
#define IMX7ULP_PAD_PTF1__TPM4_CH0                                   0x0184 0x0280 0x6 0x3
#define IMX7ULP_PAD_PTF1__CLKOUT                                     0x0184 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF2__PTF2                                       0x0188 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF2__VIU_VSYNC                                  0x0188 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF2__LPUART4_TX                                 0x0188 0x024c 0x4 0x3
#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ                                0x0188 0x0274 0x5 0x3
#define IMX7ULP_PAD_PTF2__TPM4_CH1                                   0x0188 0x0284 0x6 0x3
#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B     0x0188 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF3__PTF3                                       0x018c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF3__VIU_PCLK                                   0x018c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF3__LPUART4_RX                                 0x018c 0x0248 0x4 0x3
#define IMX7ULP_PAD_PTF3__TPM4_CH2                                   0x018c 0x0288 0x6 0x3
#define IMX7ULP_PAD_PTF3__FB_AD16                                    0x018c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF4__PTF4                                       0x0190 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF4__VIU_D0                                     0x0190 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF4__FXIO1_D0                                   0x0190 0x0204 0x2 0x2
#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1                                0x0190 0x02a0 0x3 0x3
#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B                              0x0190 0x0250 0x4 0x3
#define IMX7ULP_PAD_PTF4__LPI2C5_SCL                                 0x0190 0x02bc 0x5 0x3
#define IMX7ULP_PAD_PTF4__TPM4_CH3                                   0x0190 0x028c 0x6 0x2
#define IMX7ULP_PAD_PTF4__FB_AD17                                    0x0190 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF5__PTF5                                       0x0194 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF5__VIU_D1                                     0x0194 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF5__FXIO1_D1                                   0x0194 0x0208 0x2 0x2
#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2                                0x0194 0x02a4 0x3 0x3
#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B                              0x0194 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTF5__LPI2C5_SDA                                 0x0194 0x02c0 0x5 0x3
#define IMX7ULP_PAD_PTF5__TPM4_CH4                                   0x0194 0x0290 0x6 0x2
#define IMX7ULP_PAD_PTF5__FB_AD18                                    0x0194 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF6__PTF6                                       0x0198 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF6__VIU_D2                                     0x0198 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF6__FXIO1_D2                                   0x0198 0x020c 0x2 0x2
#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3                                0x0198 0x02a8 0x3 0x3
#define IMX7ULP_PAD_PTF6__LPUART5_TX                                 0x0198 0x0258 0x4 0x3
#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ                                0x0198 0x02b8 0x5 0x3
#define IMX7ULP_PAD_PTF6__TPM4_CH5                                   0x0198 0x0294 0x6 0x2
#define IMX7ULP_PAD_PTF6__FB_AD19                                    0x0198 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF7__PTF7                                       0x019c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF7__VIU_D3                                     0x019c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF7__FXIO1_D3                                   0x019c 0x0210 0x2 0x2
#define IMX7ULP_PAD_PTF7__LPUART5_RX                                 0x019c 0x0254 0x4 0x3
#define IMX7ULP_PAD_PTF7__TPM5_CH1                                   0x019c 0x02c8 0x6 0x3
#define IMX7ULP_PAD_PTF7__FB_AD20                                    0x019c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF8__PTF8                                       0x01a0 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK                              0x01a0 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF8__VIU_D4                                     0x01a0 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF8__FXIO1_D4                                   0x01a0 0x0214 0x2 0x2
#define IMX7ULP_PAD_PTF8__LPSPI2_SIN                                 0x01a0 0x02b0 0x3 0x3
#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B                              0x01a0 0x025c 0x4 0x3
#define IMX7ULP_PAD_PTF8__LPI2C6_SCL                                 0x01a0 0x02fc 0x5 0x3
#define IMX7ULP_PAD_PTF8__TPM5_CLKIN                                 0x01a0 0x02cc 0x6 0x3
#define IMX7ULP_PAD_PTF8__FB_AD21                                    0x01a0 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF9__PTF9                                       0x01a4 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT                              0x01a4 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF9__VIU_D5                                     0x01a4 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF9__FXIO1_D5                                   0x01a4 0x0218 0x2 0x2
#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT                                0x01a4 0x02b4 0x3 0x3
#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B                              0x01a4 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTF9__LPI2C6_SDA                                 0x01a4 0x0300 0x5 0x3
#define IMX7ULP_PAD_PTF9__TPM5_CH0                                   0x01a4 0x02c4 0x6 0x3
#define IMX7ULP_PAD_PTF9__FB_AD22                                    0x01a4 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF10__PTF10                                     0x01a8 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF10__USB1_ULPI_STP                             0x01a8 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF10__VIU_D6                                    0x01a8 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF10__FXIO1_D6                                  0x01a8 0x021c 0x2 0x2
#define IMX7ULP_PAD_PTF10__LPSPI2_SCK                                0x01a8 0x02ac 0x3 0x3
#define IMX7ULP_PAD_PTF10__LPUART6_TX                                0x01a8 0x0264 0x4 0x3
#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ                               0x01a8 0x02f8 0x5 0x3
#define IMX7ULP_PAD_PTF10__TPM7_CH3                                  0x01a8 0x02e8 0x6 0x3
#define IMX7ULP_PAD_PTF10__FB_AD23                                   0x01a8 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF11__PTF11                                     0x01ac 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR                             0x01ac 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF11__VIU_D7                                    0x01ac 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF11__FXIO1_D7                                  0x01ac 0x0220 0x2 0x2
#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0                               0x01ac 0x029c 0x3 0x3
#define IMX7ULP_PAD_PTF11__LPUART6_RX                                0x01ac 0x0260 0x4 0x3
#define IMX7ULP_PAD_PTF11__TPM7_CH4                                  0x01ac 0x02ec 0x6 0x3
#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B     0x01ac 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF12__PTF12                                     0x01b0 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0                           0x01b0 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF12__VIU_D8                                    0x01b0 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF12__FXIO1_D8                                  0x01b0 0x0224 0x2 0x2
#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1                               0x01b0 0x0314 0x3 0x3
#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B                             0x01b0 0x0268 0x4 0x3
#define IMX7ULP_PAD_PTF12__LPI2C7_SCL                                0x01b0 0x0308 0x5 0x3
#define IMX7ULP_PAD_PTF12__TPM7_CH5                                  0x01b0 0x02f0 0x6 0x3
#define IMX7ULP_PAD_PTF12__FB_AD24                                   0x01b0 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF13__PTF13                                     0x01b4 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1                           0x01b4 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF13__VIU_D9                                    0x01b4 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF13__FXIO1_D9                                  0x01b4 0x0228 0x2 0x2
#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2                               0x01b4 0x0318 0x3 0x3
#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B                             0x01b4 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTF13__LPI2C7_SDA                                0x01b4 0x030c 0x5 0x3
#define IMX7ULP_PAD_PTF13__TPM7_CLKIN                                0x01b4 0x02f4 0x6 0x3
#define IMX7ULP_PAD_PTF13__FB_AD25                                   0x01b4 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF14__PTF14                                     0x01b8 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2                           0x01b8 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF14__VIU_D10                                   0x01b8 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF14__FXIO1_D10                                 0x01b8 0x022c 0x2 0x2
#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3                               0x01b8 0x031c 0x3 0x3
#define IMX7ULP_PAD_PTF14__LPUART7_TX                                0x01b8 0x0270 0x4 0x3
#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ                               0x01b8 0x0304 0x5 0x3
#define IMX7ULP_PAD_PTF14__TPM7_CH0                                  0x01b8 0x02dc 0x6 0x3
#define IMX7ULP_PAD_PTF14__FB_AD26                                   0x01b8 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF15__PTF15                                     0x01bc 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3                           0x01bc 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF15__VIU_D11                                   0x01bc 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF15__FXIO1_D11                                 0x01bc 0x0230 0x2 0x2
#define IMX7ULP_PAD_PTF15__LPUART7_RX                                0x01bc 0x026c 0x4 0x3
#define IMX7ULP_PAD_PTF15__TPM7_CH1                                  0x01bc 0x02e0 0x6 0x3
#define IMX7ULP_PAD_PTF15__FB_AD27                                   0x01bc 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF16__PTF16                                     0x01c0 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4                           0x01c0 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF16__VIU_D12                                   0x01c0 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF16__FXIO1_D12                                 0x01c0 0x0234 0x2 0x2
#define IMX7ULP_PAD_PTF16__LPSPI3_SIN                                0x01c0 0x0324 0x3 0x3
#define IMX7ULP_PAD_PTF16__TPM7_CH2                                  0x01c0 0x02e4 0x6 0x3
#define IMX7ULP_PAD_PTF16__FB_AD28                                   0x01c0 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF17__PTF17                                     0x01c4 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5                           0x01c4 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF17__VIU_D13                                   0x01c4 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF17__FXIO1_D13                                 0x01c4 0x0238 0x2 0x2
#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT                               0x01c4 0x0328 0x3 0x3
#define IMX7ULP_PAD_PTF17__TPM6_CLKIN                                0x01c4 0x02d8 0x6 0x3
#define IMX7ULP_PAD_PTF17__FB_AD29                                   0x01c4 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF18__PTF18                                     0x01c8 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6                           0x01c8 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF18__VIU_D14                                   0x01c8 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF18__FXIO1_D14                                 0x01c8 0x023c 0x2 0x2
#define IMX7ULP_PAD_PTF18__LPSPI3_SCK                                0x01c8 0x0320 0x3 0x3
#define IMX7ULP_PAD_PTF18__TPM6_CH0                                  0x01c8 0x02d0 0x6 0x3
#define IMX7ULP_PAD_PTF18__FB_AD30                                   0x01c8 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF19__PTF19                                     0x01cc 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7                           0x01cc 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF19__VIU_D15                                   0x01cc 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF19__FXIO1_D15                                 0x01cc 0x0240 0x2 0x2
#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0                               0x01cc 0x0310 0x3 0x3
#define IMX7ULP_PAD_PTF19__TPM6_CH1                                  0x01cc 0x02d4 0x6 0x3
#define IMX7ULP_PAD_PTF19__FB_AD31                                   0x01cc 0x0000 0x9 0x0

#endif /* __DTS_IMX7ULP_PINFUNC_H */


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017-2018 NXP
 *   Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx7ulp-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "imx7ulp-pinfunc.h"

/ {
	interrupt-parent = <&intc>;

	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		gpio0 = &gpio_ptc;
		gpio1 = &gpio_ptd;
		gpio2 = &gpio_pte;
		gpio3 = &gpio_ptf;
		i2c0 = &lpi2c6;
		i2c1 = &lpi2c7;
		mmc0 = &usdhc0;
		mmc1 = &usdhc1;
		serial0 = &lpuart4;
		serial1 = &lpuart5;
		serial2 = &lpuart6;
		serial3 = &lpuart7;
		usbphy0 = &usbphy1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@f00 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0xf00>;
		};
	};

	intc: interrupt-controller@40021000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x40021000 0x1000>,
		      <0x40022000 0x1000>;
	};

	rosc: clock-rosc {
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "rosc";
		#clock-cells = <0>;
	};

	sosc: clock-sosc {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "sosc";
		#clock-cells = <0>;
	};

	sirc: clock-sirc {
		compatible = "fixed-clock";
		clock-frequency = <16000000>;
		clock-output-names = "sirc";
		#clock-cells = <0>;
	};

	firc: clock-firc {
		compatible = "fixed-clock";
		clock-frequency = <48000000>;
		clock-output-names = "firc";
		#clock-cells = <0>;
	};

	upll: clock-upll {
		compatible = "fixed-clock";
		clock-frequency = <480000000>;
		clock-output-names = "upll";
		#clock-cells = <0>;
	};

	ahbbridge0: bus@40000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x40000000 0x800000>;
		ranges;

		edma1: dma-controller@40080000 {
			#dma-cells = <2>;
			compatible = "fsl,imx7ulp-edma";
			reg = <0x40080000 0x2000>,
				<0x40210000 0x1000>;
			dma-channels = <32>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dma", "dmamux0";
			clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
				 <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
		};

		crypto: crypto@40240000 {
			compatible = "fsl,sec-v4.0";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40240000 0x10000>;
			ranges = <0 0x40240000 0x10000>;
			clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
				 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
			clock-names = "aclk", "ipg";

			sec_jr0: jr@1000 {
				compatible = "fsl,sec-v4.0-job-ring";
				reg = <0x1000 0x1000>;
				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr1: jr@2000 {
				compatible = "fsl,sec-v4.0-job-ring";
				reg = <0x2000 0x1000>;
				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		lpuart4: serial@402d0000 {
			compatible = "fsl,imx7ulp-lpuart";
			reg = <0x402d0000 0x1000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
			clock-names = "ipg";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
			assigned-clock-rates = <24000000>;
			status = "disabled";
		};

		lpuart5: serial@402e0000 {
			compatible = "fsl,imx7ulp-lpuart";
			reg = <0x402e0000 0x1000>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
			clock-names = "ipg";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		tpm4: pwm@40250000 {
			compatible = "fsl,imx7ulp-pwm";
			reg = <0x40250000 0x1000>;
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
			clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		tpm5: tpm@40260000 {
			compatible = "fsl,imx7ulp-tpm";
			reg = <0x40260000 0x1000>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
			clock-names = "ipg", "per";
		};

		usbotg1: usb@40330000 {
			compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
			reg = <0x40330000 0x200>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_USB0>;
			phys = <&usbphy1>;
			fsl,usbmisc = <&usbmisc1 0>;
			ahb-burst-config = <0x0>;
			tx-burst-size-dword = <0x8>;
			rx-burst-size-dword = <0x8>;
			status = "disabled";
		};

		usbmisc1: usbmisc@40330200 {
			compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
			#index-cells = <1>;
			reg = <0x40330200 0x200>;
		};

		usbphy1: usb-phy@40350000 {
			compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
			reg = <0x40350000 0x1000>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
			#phy-cells = <0>;
		};

		usdhc0: mmc@40370000 {
			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
			reg = <0x40370000 0x10000>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
				 <&pcc2 IMX7ULP_CLK_USDHC0>;
			clock-names = "ipg", "ahb", "per";
			bus-width = <4>;
			fsl,tuning-start-tap = <20>;
			fsl,tuning-step = <2>;
			status = "disabled";
		};

		usdhc1: mmc@40380000 {
			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
			reg = <0x40380000 0x10000>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
				 <&pcc2 IMX7ULP_CLK_USDHC1>;
			clock-names = "ipg", "ahb", "per";
			bus-width = <4>;
			fsl,tuning-start-tap = <20>;
			fsl,tuning-step = <2>;
			status = "disabled";
		};

		scg1: clock-controller@403e0000 {
			compatible = "fsl,imx7ulp-scg1";
			reg = <0x403e0000 0x10000>;
			clocks = <&rosc>, <&sosc>, <&sirc>,
				 <&firc>, <&upll>;
			clock-names = "rosc", "sosc", "sirc",
				      "firc", "upll";
			#clock-cells = <1>;
		};

		wdog1: watchdog@403d0000 {
			compatible = "fsl,imx7ulp-wdt";
			reg = <0x403d0000 0x10000>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
			assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
			timeout-sec = <40>;
		};

		pcc2: clock-controller@403f0000 {
			compatible = "fsl,imx7ulp-pcc2";
			reg = <0x403f0000 0x10000>;
			#clock-cells = <1>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
				 <&scg1 IMX7ULP_CLK_DDR_DIV>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
				 <&scg1 IMX7ULP_CLK_UPLL>,
				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
				 <&scg1 IMX7ULP_CLK_ROSC>,
				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
			clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
				      "apll_pfd2", "apll_pfd1", "apll_pfd0",
				      "upll", "sosc_bus_clk",
				      "firc_bus_clk", "rosc", "spll_bus_clk";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
		};

		smc1: clock-controller@40410000 {
			compatible = "fsl,imx7ulp-smc1";
			reg = <0x40410000 0x1000>;
			#clock-cells = <1>;
			clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
				 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
			clock-names = "divcore", "hsrun_divcore";
		};

		pcc3: clock-controller@40b30000 {
			compatible = "fsl,imx7ulp-pcc3";
			reg = <0x40b30000 0x10000>;
			#clock-cells = <1>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
				 <&scg1 IMX7ULP_CLK_DDR_DIV>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
				 <&scg1 IMX7ULP_CLK_UPLL>,
				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
				 <&scg1 IMX7ULP_CLK_ROSC>,
				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
			clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
				      "apll_pfd2", "apll_pfd1", "apll_pfd0",
				      "upll", "sosc_bus_clk",
				      "firc_bus_clk", "rosc", "spll_bus_clk";
		};
	};

	ahbbridge1: bus@40800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x40800000 0x800000>;
		ranges;

		lpi2c6: i2c@40a40000 {
			compatible = "fsl,imx7ulp-lpi2c";
			reg = <0x40a40000 0x10000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>,
				 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
			clock-names = "per", "ipg";
			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		lpi2c7: i2c@40a50000 {
			compatible = "fsl,imx7ulp-lpi2c";
			reg = <0x40a50000 0x10000>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>,
				 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
			clock-names = "per", "ipg";
			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		lpuart6: serial@40a60000 {
			compatible = "fsl,imx7ulp-lpuart";
			reg = <0x40a60000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
			clock-names = "ipg";
			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		lpuart7: serial@40a70000 {
			compatible = "fsl,imx7ulp-lpuart";
			reg = <0x40a70000 0x1000>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3  IMX7ULP_CLK_LPUART7>;
			clock-names = "ipg";
			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		memory-controller@40ab0000 {
			compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
			reg = <0x40ab0000 0x1000>;
			clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
		};

		iomuxc1: pinctrl@40ac0000 {
			compatible = "fsl,imx7ulp-iomuxc1";
			reg = <0x40ac0000 0x1000>;
		};

		gpio_ptc: gpio@40ae0000 {
			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
			reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
				 <&pcc3 IMX7ULP_CLK_PCTLC>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 0 20>;
		};

		gpio_ptd: gpio@40af0000 {
			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
			reg = <0x40af0000 0x1000 0x400f0040 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
				 <&pcc3 IMX7ULP_CLK_PCTLD>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 32 12>;
		};

		gpio_pte: gpio@40b00000 {
			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
			reg = <0x40b00000 0x1000 0x400f0080 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
				 <&pcc3 IMX7ULP_CLK_PCTLE>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 64 16>;
		};

		gpio_ptf: gpio@40b10000 {
			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
			reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
				 <&pcc3 IMX7ULP_CLK_PCTLF>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 96 20>;
		};
	};

	m4aips1: bus@41080000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x41080000 0x80000>;
		ranges;

		sim: sim@410a3000 {
			compatible = "fsl,imx7ulp-sim", "syscon";
			reg = <0x410a3000 0x1000>;
		};

		ocotp: efuse@410a6000 {
			compatible = "fsl,imx7ulp-ocotp", "syscon";
			reg = <0x410a6000 0x4000>;
			clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019
 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
 */

/dts-v1/;
#include "imxrt1050.dtsi"
#include "imxrt1050-pinfunc.h"

/ {
	model = "NXP IMXRT1050-evk board";
	compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";

	chosen {
		stdout-path = &lpuart1;
	};

	aliases {
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		mmc0 = &usdhc1;
		serial0 = &lpuart1;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x2000000>;
	};
};

&lpuart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart1>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl_lpuart1: lpuart1grp {
		fsl,pins = <
			MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD	0xf1
			MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD	0xf1
		>;
	};

	pinctrl_usdhc0: usdhc0grp {
		fsl,pins = <
			MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B		0x1B000
			MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT	0xB069
			MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD	0x17061
			MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK	0x17061
			MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3	0x17061
			MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2	0x17061
			MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1	0x17061
			MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0	0x17061
		>;
	};
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc0>;
	pinctrl-1 = <&pinctrl_usdhc0>;
	pinctrl-2 = <&pinctrl_usdhc0>;
	pinctrl-3 = <&pinctrl_usdhc0>;
	cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
	status = "okay";
};