code:
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Biao Huang <biao.huang@mediatek.com>
 */

#ifndef __DTS_MT2701_PINFUNC_H
#define __DTS_MT2701_PINFUNC_H

#include <dt-bindings/pinctrl/mt65xx.h>

#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)

#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)

#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)

#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)

#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)

#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5)

#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5)
#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7)

#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4)
#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7)

#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4)
#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7)

#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4)
#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7)

#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)

#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)

#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)

#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)

#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1)
#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5)
#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7)

#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2)
#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7)

#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2)
#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4)
#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5)
#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6)
#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7)

#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2)
#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5)
#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6)
#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7)

#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2)
#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3)
#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5)
#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6)
#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7)

#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2)
#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3)
#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5)
#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6)
#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7)

#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3)
#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4)
#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5)
#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7)
#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10)

#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1)
#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3)
#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4)
#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7)
#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10)

#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3)
#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4)
#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7)
#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10)

#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1)
#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3)
#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4)
#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7)

#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2)
#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3)
#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4)
#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5)
#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7)

#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1)
#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2)
#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3)
#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4)
#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7)

#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3)
#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4)
#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7)

#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1)
#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3)
#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4)
#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5)
#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7)
#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14)

#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2)
#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4)
#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5)
#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6)
#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7)

#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7)

#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5)
#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6)
#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7)

#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5)
#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6)
#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7)

#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5)
#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7)

#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1)
#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2)
#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3)
#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4)

#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1)
#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2)
#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3)
#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4)

#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1)
#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2)
#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4)

#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1)
#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2)
#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4)

#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1)
#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)

#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2)

#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)

#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1)

#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1)
#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2)

#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1)
#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2)

#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2)
#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6)
#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7)

#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3)
#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4)
#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5)
#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7)

#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3)
#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4)
#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7)

#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4)
#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5)
#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7)

#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3)
#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7)

#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1)

#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1)

#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7)

#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6)
#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7)

#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6)
#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7)

#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1)

#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1)

#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1)

#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1)

#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1)
#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5)

#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1)
#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2)

#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1)
#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2)

#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1)
#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2)

#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2)
#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7)

#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7)

#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1)

#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1)

#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1)

#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1)

#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1)

#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1)

#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1)

#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1)

#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1)

#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0)
#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1)

#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1)
#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3)
#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4)

#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1)
#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2)
#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3)
#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4)

#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1)
#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2)
#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3)
#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4)

#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1)
#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3)
#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4)

#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2)
#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3)
#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7)

#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2)
#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3)
#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7)

#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2)
#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7)

#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7)

#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7)

#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7)

#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4)

#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4)

#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4)

#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4)

#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4)

#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4)

#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4)

#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4)

#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4)

#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4)

#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4)
#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)

#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1)
#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4)
#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5)

#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1)
#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4)
#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5)

#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1)
#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4)
#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5)

#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1)
#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4)
#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5)

#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6)
#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7)

#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3)
#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4)
#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7)

#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1)
#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5)
#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6)
#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7)

#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1)
#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5)
#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7)

#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1)

#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1)
#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5)
#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7)
#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9)

#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1)
#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2)
#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5)
#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7)
#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9)

#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1)
#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2)
#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5)
#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7)

#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1)
#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2)
#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3)
#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5)
#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7)

#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1)
#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2)
#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3)
#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5)
#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7)

#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11)

#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5)
#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7)
#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11)

#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2)
#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7)

#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)

#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2)

#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2)

#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)

#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)

#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1)
#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3)
#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4)
#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7)

#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2)
#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4)
#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7)

#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0)
#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1)

#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0)
#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1)

#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0)

#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0)
#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1)

#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0)
#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1)

#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9)

#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9)
#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14)

#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9)
#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14)

#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9)
#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14)

#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9)
#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14)

#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9)
#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14)

#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9)
#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14)

#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9)

#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9)

#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9)

#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9)

#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9)

#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7)

#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)

#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6)

#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6)

#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6)

#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6)

#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1)

#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1)

#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)

#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)

#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)

#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)

#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)

#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1)
#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6)

#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1)
#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6)

#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)

#endif /* __DTS_MT2701_PINFUNC_H */


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Erin.Lo <erin.lo@mediatek.com>
 *
 */

#include <dt-bindings/clock/mt2701-clk.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include "mt2701-pinfunc.h"

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "mediatek,mt2701";
	interrupt-parent = <&cirq>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "mediatek,mt81xx-tz-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		trustzone-bootinfo@80002000 {
			compatible = "mediatek,trustzone-bootinfo";
			reg = <0 0x80002000 0 0x1000>;
		};
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	rtc_clk: dummy32k {
		compatible = "fixed-clock";
		clock-frequency = <32000>;
		#clock-cells = <0>;
	};

	clk26m: oscillator@0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	rtc32k: oscillator@1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32000>;
		clock-output-names = "rtc32k";
	};

	thermal-zones {
		cpu_thermal: cpu_thermal {
			polling-delay-passive = <1000>; /* milliseconds */
			polling-delay = <1000>; /* milliseconds */

			thermal-sensors = <&thermal 0>;
			sustainable-power = <1000>;

			trips {
				threshold: trip-point@0 {
					temperature = <68000>;
					hysteresis = <2000>;
					type = "passive";
				};

				target: trip-point@1 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit@0 {
					temperature = <115000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	topckgen: syscon@10000000 {
		compatible = "mediatek,mt2701-topckgen", "syscon";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
		compatible = "mediatek,mt2701-infracfg", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pericfg: syscon@10003000 {
		compatible = "mediatek,mt2701-pericfg", "syscon";
		reg = <0 0x10003000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	syscfg_pctl_a: syscfg@10005000 {
		compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
		reg = <0 0x10005000 0 0x1000>;
	};

	scpsys: power-controller@10006000 {
		compatible = "mediatek,mt2701-scpsys", "syscon";
		#power-domain-cells = <1>;
		reg = <0 0x10006000 0 0x1000>;
		infracfg = <&infracfg>;
		clocks = <&topckgen CLK_TOP_MM_SEL>,
			 <&topckgen CLK_TOP_MFG_SEL>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "mm", "mfg", "ethif";
	};

	watchdog: watchdog@10007000 {
		compatible = "mediatek,mt2701-wdt",
			     "mediatek,mt6589-wdt";
		reg = <0 0x10007000 0 0x100>;
	};

	timer: timer@10008000 {
		compatible = "mediatek,mt2701-timer",
			     "mediatek,mt6577-timer";
		reg = <0 0x10008000 0 0x80>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>, <&rtc_clk>;
		clock-names = "system-clk", "rtc-clk";
	};

	pio: pinctrl@1000b000 {
		compatible = "mediatek,mt2701-pinctrl";
		reg = <0 0x1000b000 0 0x1000>;
		mediatek,pctl-regmap = <&syscfg_pctl_a>;
		pins-are-numbered;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};

	smi_common: smi@1000c000 {
		compatible = "mediatek,mt2701-smi-common";
		reg = <0 0x1000c000 0 0x1000>;
		clocks = <&infracfg CLK_INFRA_SMI>,
			 <&mmsys CLK_MM_SMI_COMMON>,
			 <&infracfg CLK_INFRA_SMI>;
		clock-names = "apb", "smi", "async";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	sysirq: interrupt-controller@10200100 {
		compatible = "mediatek,mt2701-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10200100 0 0x1c>;
	};

	cirq: interrupt-controller@10204000 {
		compatible = "mediatek,mt2701-cirq",
			     "mediatek,mtk-cirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&sysirq>;
		reg = <0 0x10204000 0 0x400>;
		mediatek,ext-irq-range = <32 200>;
	};

	iommu: mmsys_iommu@10205000 {
		compatible = "mediatek,mt2701-m4u";
		reg = <0 0x10205000 0 0x1000>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg CLK_INFRA_M4U>;
		clock-names = "bclk";
		mediatek,larbs = <&larb0 &larb1 &larb2>;
		#iommu-cells = <1>;
	};

	apmixedsys: syscon@10209000 {
		compatible = "mediatek,mt2701-apmixedsys", "syscon";
		reg = <0 0x10209000 0 0x1000>;
		#clock-cells = <1>;
	};

	gic: interrupt-controller@10211000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10211000 0 0x1000>,
		      <0 0x10212000 0 0x2000>,
		      <0 0x10214000 0 0x2000>,
		      <0 0x10216000 0 0x2000>;
	};

	auxadc: adc@11001000 {
		compatible = "mediatek,mt2701-auxadc";
		reg = <0 0x11001000 0 0x1000>;
		clocks = <&pericfg CLK_PERI_AUXADC>;
		clock-names = "main";
		#io-channel-cells = <1>;
		status = "disabled";
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11005000 0 0x400>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	i2c0: i2c@11007000 {
		compatible = "mediatek,mt2701-i2c",
			     "mediatek,mt6577-i2c";
		reg = <0 0x11007000 0 0x70>,
		      <0 0x11000200 0 0x80>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c1: i2c@11008000 {
		compatible = "mediatek,mt2701-i2c",
			     "mediatek,mt6577-i2c";
		reg = <0 0x11008000 0 0x70>,
		      <0 0x11000280 0 0x80>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@11009000 {
		compatible = "mediatek,mt2701-i2c",
			     "mediatek,mt6577-i2c";
		reg = <0 0x11009000 0 0x70>,
		      <0 0x11000300 0 0x80>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi0: spi@1100a000 {
		compatible = "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x1100a000 0 0x100>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI0_SEL>,
			 <&pericfg CLK_PERI_SPI0>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	thermal: thermal@1100b000 {
		#thermal-sensor-cells = <0>;
		compatible = "mediatek,mt2701-thermal";
		reg = <0 0x1100b000 0 0x1000>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
		clock-names = "therm", "auxadc";
		resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
		reset-names = "therm";
		mediatek,auxadc = <&auxadc>;
		mediatek,apmixedsys = <&apmixedsys>;
	};

	nandc: nfi@1100d000 {
		compatible = "mediatek,mt2701-nfc";
		reg = <0 0x1100d000 0 0x1000>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI>,
			 <&pericfg CLK_PERI_NFI_PAD>;
		clock-names = "nfi_clk", "pad_clk";
		status = "disabled";
		ecc-engine = <&bch>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	bch: ecc@1100e000 {
		compatible = "mediatek,mt2701-ecc";
		reg = <0 0x1100e000 0 0x1000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI_ECC>;
		clock-names = "nfiecc_clk";
		status = "disabled";
	};

	nor_flash: spi@11014000 {
		compatible = "mediatek,mt2701-nor",
			     "mediatek,mt8173-nor";
		reg = <0 0x11014000 0 0xe0>;
		clocks = <&pericfg CLK_PERI_FLASH>,
			 <&topckgen CLK_TOP_FLASH_SEL>;
		clock-names = "spi", "sf";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi1: spi@11016000 {
		compatible = "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x11016000 0 0x100>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI1_SEL>,
			 <&pericfg CLK_PERI_SPI1>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	spi2: spi@11017000 {
		compatible = "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x11017000 0 0x1000>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI2_SEL>,
			 <&pericfg CLK_PERI_SPI2>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	audsys: clock-controller@11220000 {
		compatible = "mediatek,mt2701-audsys", "syscon";
		reg = <0 0x11220000 0 0x2000>;
		#clock-cells = <1>;

		afe: audio-controller {
			compatible = "mediatek,mt2701-audio";
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
			interrupt-names = "afe", "asys";
			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;

			clocks = <&infracfg CLK_INFRA_AUDIO>,
				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
				 <&topckgen CLK_TOP_AUD_48K_TIMING>,
				 <&topckgen CLK_TOP_AUD_44K_TIMING>,
				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
				 <&audsys CLK_AUD_I2SO1>,
				 <&audsys CLK_AUD_I2SO2>,
				 <&audsys CLK_AUD_I2SO3>,
				 <&audsys CLK_AUD_I2SO4>,
				 <&audsys CLK_AUD_I2SIN1>,
				 <&audsys CLK_AUD_I2SIN2>,
				 <&audsys CLK_AUD_I2SIN3>,
				 <&audsys CLK_AUD_I2SIN4>,
				 <&audsys CLK_AUD_ASRCO1>,
				 <&audsys CLK_AUD_ASRCO2>,
				 <&audsys CLK_AUD_ASRCO3>,
				 <&audsys CLK_AUD_ASRCO4>,
				 <&audsys CLK_AUD_AFE>,
				 <&audsys CLK_AUD_AFE_CONN>,
				 <&audsys CLK_AUD_A1SYS>,
				 <&audsys CLK_AUD_A2SYS>,
				 <&audsys CLK_AUD_AFE_MRGIF>;

			clock-names = "infra_sys_audio_clk",
				      "top_audio_mux1_sel",
				      "top_audio_mux2_sel",
				      "top_audio_a1sys_hp",
				      "top_audio_a2sys_hp",
				      "i2s0_src_sel",
				      "i2s1_src_sel",
				      "i2s2_src_sel",
				      "i2s3_src_sel",
				      "i2s0_src_div",
				      "i2s1_src_div",
				      "i2s2_src_div",
				      "i2s3_src_div",
				      "i2s0_mclk_en",
				      "i2s1_mclk_en",
				      "i2s2_mclk_en",
				      "i2s3_mclk_en",
				      "i2so0_hop_ck",
				      "i2so1_hop_ck",
				      "i2so2_hop_ck",
				      "i2so3_hop_ck",
				      "i2si0_hop_ck",
				      "i2si1_hop_ck",
				      "i2si2_hop_ck",
				      "i2si3_hop_ck",
				      "asrc0_out_ck",
				      "asrc1_out_ck",
				      "asrc2_out_ck",
				      "asrc3_out_ck",
				      "audio_afe_pd",
				      "audio_afe_conn_pd",
				      "audio_a1sys_pd",
				      "audio_a2sys_pd",
				      "audio_mrgif_pd";

			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
						 <&topckgen CLK_TOP_AUD2PLL_90M>;
			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
		};
	};

	mmsys: syscon@14000000 {
		compatible = "mediatek,mt2701-mmsys", "syscon";
		reg = <0 0x14000000 0 0x1000>;
		#clock-cells = <1>;
	};

	bls: pwm@1400a000 {
		compatible = "mediatek,mt2701-disp-pwm";
		reg = <0 0x1400a000 0 0x1000>;
		#pwm-cells = <2>;
		clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
		clock-names = "main", "mm";
		status = "disabled";
	};

	larb0: larb@14010000 {
		compatible = "mediatek,mt2701-smi-larb";
		reg = <0 0x14010000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		mediatek,larb-id = <0>;
		clocks = <&mmsys CLK_MM_SMI_LARB0>,
			 <&mmsys CLK_MM_SMI_LARB0>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	imgsys: syscon@15000000 {
		compatible = "mediatek,mt2701-imgsys", "syscon";
		reg = <0 0x15000000 0 0x1000>;
		#clock-cells = <1>;
	};

	larb2: larb@15001000 {
		compatible = "mediatek,mt2701-smi-larb";
		reg = <0 0x15001000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		mediatek,larb-id = <2>;
		clocks = <&imgsys CLK_IMG_SMI_COMM>,
			 <&imgsys CLK_IMG_SMI_COMM>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	};

	jpegdec: jpegdec@15004000 {
		compatible = "mediatek,mt2701-jpgdec";
		reg = <0 0x15004000 0 0x1000>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
			  <&imgsys CLK_IMG_JPGDEC>;
		clock-names = "jpgdec-smi",
			      "jpgdec";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
	};

	jpegenc: jpegenc@1500a000 {
		compatible = "mediatek,mt2701-jpgenc",
			     "mediatek,mtk-jpgenc";
		reg = <0 0x1500a000 0 0x1000>;
		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&imgsys CLK_IMG_VENC>;
		clock-names = "jpgenc";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
		iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
			 <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
	};

	vdecsys: syscon@16000000 {
		compatible = "mediatek,mt2701-vdecsys", "syscon";
		reg = <0 0x16000000 0 0x1000>;
		#clock-cells = <1>;
	};

	larb1: larb@16010000 {
		compatible = "mediatek,mt2701-smi-larb";
		reg = <0 0x16010000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		mediatek,larb-id = <1>;
		clocks = <&vdecsys CLK_VDEC_CKGEN>,
			 <&vdecsys CLK_VDEC_LARB>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
	};

	hifsys: syscon@1a000000 {
		compatible = "mediatek,mt2701-hifsys", "syscon";
		reg = <0 0x1a000000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	usb0: usb@1a1c0000 {
		compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
		reg = <0 0x1a1c0000 0 0x1000>,
		      <0 0x1a1c4700 0 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "sys_ck", "ref_ck";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
		status = "disabled";
	};

	u3phy0: t-phy@1a1c4000 {
		compatible = "mediatek,mt2701-tphy",
			     "mediatek,generic-tphy-v1";
		reg = <0 0x1a1c4000 0 0x0700>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		u2port0: usb-phy@1a1c4800 {
			reg = <0 0x1a1c4800 0 0x0100>;
			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};

		u3port0: usb-phy@1a1c4900 {
			reg = <0 0x1a1c4900 0 0x0700>;
			clocks = <&clk26m>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	usb1: usb@1a240000 {
		compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
		reg = <0 0x1a240000 0 0x1000>,
		      <0 0x1a244700 0 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "sys_ck", "ref_ck";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
		phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
		status = "disabled";
	};

	u3phy1: t-phy@1a244000 {
		compatible = "mediatek,mt2701-tphy",
			     "mediatek,generic-tphy-v1";
		reg = <0 0x1a244000 0 0x0700>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		u2port1: usb-phy@1a244800 {
			reg = <0 0x1a244800 0 0x0100>;
			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};

		u3port1: usb-phy@1a244900 {
			reg = <0 0x1a244900 0 0x0700>;
			clocks = <&clk26m>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	usb2: usb@11200000 {
		compatible = "mediatek,mt2701-musb",
			     "mediatek,mtk-musb";
		reg = <0 0x11200000 0 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "mc";
		phys = <&u2port2 PHY_TYPE_USB2>;
		dr_mode = "otg";
		clocks = <&pericfg CLK_PERI_USB0>,
			 <&pericfg CLK_PERI_USB0_MCU>,
			 <&pericfg CLK_PERI_USB_SLV>;
		clock-names = "main","mcu","univpll";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
		status = "disabled";
	};

	u2phy0: t-phy@11210000 {
		compatible = "mediatek,mt2701-tphy",
			     "mediatek,generic-tphy-v1";
		reg = <0 0x11210000 0 0x0800>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "okay";

		u2port2: usb-phy@1a1c4800 {
			reg = <0 0x11210800 0 0x0100>;
			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	ethsys: syscon@1b000000 {
		compatible = "mediatek,mt2701-ethsys", "syscon";
		reg = <0 0x1b000000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	eth: ethernet@1b100000 {
		compatible = "mediatek,mt2701-eth", "syscon";
		reg = <0 0x1b100000 0 0x20000>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
			 <&ethsys CLK_ETHSYS_ESW>,
			 <&ethsys CLK_ETHSYS_GP1>,
			 <&ethsys CLK_ETHSYS_GP2>,
			 <&apmixedsys CLK_APMIXED_TRGPLL>;
		clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
		resets = <&ethsys MT2701_ETHSYS_FE_RST>,
			 <&ethsys MT2701_ETHSYS_GMAC_RST>,
			 <&ethsys MT2701_ETHSYS_PPE_RST>;
		reset-names = "fe", "gmac", "ppe";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
		mediatek,ethsys = <&ethsys>;
		mediatek,pctl = <&syscfg_pctl_a>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	bdpsys: syscon@1c000000 {
		compatible = "mediatek,mt2701-bdpsys", "syscon";
		reg = <0 0x1c000000 0 0x1000>;
		#clock-cells = <1>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2017-2018 MediaTek Inc.
 * Author: John Crispin <john@phrozen.org>
 *	   Sean Wang <sean.wang@mediatek.com>
 *
 */

&pwrap {
	pmic: mt6323 {
		compatible = "mediatek,mt6323";
		interrupt-parent = <&pio>;
		interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;

		mt6323_leds: leds {
			compatible = "mediatek,mt6323-led";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mt6323regulator: mt6323regulator{
			compatible = "mediatek,mt6323-regulator";

			mt6323_vproc_reg: buck_vproc{
				regulator-name = "vproc";
				regulator-min-microvolt = < 700000>;
				regulator-max-microvolt = <1350000>;
				regulator-ramp-delay = <12500>;
				regulator-always-on;
				regulator-boot-on;
			};

			mt6323_vsys_reg: buck_vsys{
				regulator-name = "vsys";
				regulator-min-microvolt = <1400000>;
				regulator-max-microvolt = <2987500>;
				regulator-ramp-delay = <25000>;
				regulator-always-on;
				regulator-boot-on;
			};

			mt6323_vpa_reg: buck_vpa{
				regulator-name = "vpa";
				regulator-min-microvolt = < 500000>;
				regulator-max-microvolt = <3650000>;
			};

			mt6323_vtcxo_reg: ldo_vtcxo{
				regulator-name = "vtcxo";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <90>;
				regulator-always-on;
				regulator-boot-on;
			};

			mt6323_vcn28_reg: ldo_vcn28{
				regulator-name = "vcn28";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <185>;
			};

			mt6323_vcn33_bt_reg: ldo_vcn33_bt{
				regulator-name = "vcn33_bt";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3600000>;
				regulator-enable-ramp-delay = <185>;
			};

			mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
				regulator-name = "vcn33_wifi";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3600000>;
				regulator-enable-ramp-delay = <185>;
			};

			mt6323_va_reg: ldo_va{
				regulator-name = "va";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <216>;
				regulator-always-on;
				regulator-boot-on;
			};

			mt6323_vcama_reg: ldo_vcama{
				regulator-name = "vcama";
				regulator-min-microvolt = <1500000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <216>;
			};

			mt6323_vio28_reg: ldo_vio28{
				regulator-name = "vio28";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-enable-ramp-delay = <216>;
				regulator-always-on;
				regulator-boot-on;
			};

			mt6323_vusb_reg: ldo_vusb{
				regulator-name = "vusb";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <216>;
				regulator-boot-on;
			};

			mt6323_vmc_reg: ldo_vmc{
				regulator-name = "vmc";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <36>;
				regulator-boot-on;
			};

			mt6323_vmch_reg: ldo_vmch{
				regulator-name = "vmch";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <36>;
				regulator-boot-on;
			};

			mt6323_vemc3v3_reg: ldo_vemc3v3{
				regulator-name = "vemc3v3";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <36>;
				regulator-boot-on;
			};

			mt6323_vgp1_reg: ldo_vgp1{
				regulator-name = "vgp1";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <216>;
			};

			mt6323_vgp2_reg: ldo_vgp2{
				regulator-name = "vgp2";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <216>;
			};

			mt6323_vgp3_reg: ldo_vgp3{
				regulator-name = "vgp3";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <216>;
			};

			mt6323_vcn18_reg: ldo_vcn18{
				regulator-name = "vcn18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <216>;
			};

			mt6323_vsim1_reg: ldo_vsim1{
				regulator-name = "vsim1";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <216>;
			};

			mt6323_vsim2_reg: ldo_vsim2{
				regulator-name = "vsim2";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <216>;
			};

			mt6323_vrtc_reg: ldo_vrtc{
				regulator-name = "vrtc";
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-always-on;
				regulator-boot-on;
			};

			mt6323_vcamaf_reg: ldo_vcamaf{
				regulator-name = "vcamaf";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <216>;
			};

			mt6323_vibr_reg: ldo_vibr{
				regulator-name = "vibr";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <36>;
			};

			mt6323_vrf18_reg: ldo_vrf18{
				regulator-name = "vrf18";
				regulator-min-microvolt = <1825000>;
				regulator-max-microvolt = <1825000>;
				regulator-enable-ramp-delay = <187>;
			};

			mt6323_vm_reg: ldo_vm{
				regulator-name = "vm";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <216>;
				regulator-always-on;
				regulator-boot-on;
			};

			mt6323_vio18_reg: ldo_vio18{
				regulator-name = "vio18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <216>;
				regulator-always-on;
				regulator-boot-on;
			};

			mt6323_vcamd_reg: ldo_vcamd{
				regulator-name = "vcamd";
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <216>;
			};

			mt6323_vcamio_reg: ldo_vcamio{
				regulator-name = "vcamio";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-enable-ramp-delay = <216>;
			};
		};

		mt6323keys: mt6323keys {
			compatible = "mediatek,mt6323-keys";
			mediatek,long-press-mode = <1>;
			power-off-time-sec = <0>;

			power {
				linux,keycodes = <116>;
				wakeup-source;
			};

			home {
				linux,keycodes = <114>;
			};
		};

		codec: mt6397codec {
			compatible = "mediatek,mt6397-codec";
		};

		power-controller {
			compatible = "mediatek,mt6323-pwrc";
		};

		rtc {
			compatible = "mediatek,mt6323-rtc";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Mars.C <mars.cheng@mediatek.com>
 *
 */

/dts-v1/;
#include "mt6580.dtsi"

/ {
	model = "MediaTek MT6580 evaluation board";
	compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	chosen {
		stdout-path = "serial0:921600n8";
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};
};

&uart0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Mars.C <mars.cheng@mediatek.com>
 *
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "mediatek,mt6580";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&sysirq>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
		};

	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	rtc_clk: dummy32k {
		compatible = "fixed-clock";
		clock-frequency = <32000>;
		#clock-cells = <0>;
	};

	uart_clk: dummy26m {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	timer: timer@10008000 {
		compatible = "mediatek,mt6580-timer",
			     "mediatek,mt6577-timer";
		reg = <0x10008000 0x80>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>, <&rtc_clk>;
		clock-names = "system-clk", "rtc-clk";
	};

	sysirq: interrupt-controller@10200100 {
		compatible = "mediatek,mt6580-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0x10200100 0x1c>;
	};

	gic: interrupt-controller@10211000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0x10211000 0x1000>,
		      <0x10212000 0x2000>,
		      <0x10214000 0x2000>,
		      <0x10216000 0x2000>;
	};

	uart0: serial@11005000 {
		compatible = "mediatek,mt6580-uart",
			     "mediatek,mt6577-uart";
		reg = <0x11005000 0x400>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart1: serial@11006000 {
		compatible = "mediatek,mt6580-uart",
			     "mediatek,mt6577-uart";
		reg = <0x11006000 0x400>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2021 Maxim Kutnij <gtk3@inbox.ru>
 */

/dts-v1/;
#include "mt6582.dtsi"

/ {
	model = "Prestigio PMT5008 3G";
	compatible = "prestigio,pmt5008-3g", "mediatek,mt6582";

	aliases {
		bootargs = "console=ttyS0,921600n8 earlyprintk";
		serial0 = &uart0;
		serial3 = &uart3;
	};

	chosen {
		stdout-path = "serial0:921600n8";
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2021 Maxim Kutnij <gtk3@inbox.ru>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "mediatek,mt6582";
	interrupt-parent = <&sysirq>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
		};
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	rtc_clk: dummy32k {
		compatible = "fixed-clock";
		clock-frequency = <32000>;
		#clock-cells = <0>;
	};

	uart_clk: dummy26m {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	timer: timer@11008000 {
		compatible = "mediatek,mt6577-timer";
		reg = <0x10008000 0x80>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>, <&rtc_clk>;
		clock-names = "system-clk", "rtc-clk";
	};

	sysirq: interrupt-controller@10200100 {
		compatible = "mediatek,mt6582-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0x10200100 0x1c>;
	};

	gic: interrupt-controller@10211000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0x10211000 0x1000>,
		      <0x10212000 0x2000>,
		      <0x10214000 0x2000>,
		      <0x10216000 0x2000>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt6582-uart",
			     "mediatek,mt6577-uart";
		reg = <0x11002000 0x400>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt6582-uart",
			     "mediatek,mt6577-uart";
		reg = <0x11003000 0x400>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt6582-uart",
			     "mediatek,mt6577-uart";
		reg = <0x11004000 0x400>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt6582-uart",
			     "mediatek,mt6577-uart";
		reg = <0x11005000 0x400>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	watchdog: watchdog@10007000 {
		compatible = "mediatek,mt6582-wdt",
			     "mediatek,mt6589-wdt";
		reg = <0x10007000 0x100>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2014 MundoReader S.L.
 * Author: Matthias Brugger <matthias.bgg@gmail.com>
 *
 */

/dts-v1/;
#include "mt6589.dtsi"

/ {
	model = "bq Aquaris5";
	compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";

	chosen {
		bootargs = "console=ttyS0,921600n8 earlyprintk";
		stdout-path = &uart0;
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};

};

&uart0 {
	status = "okay";
};

&uart3 {
	status = "okay";
};


code:
// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2021, Luca Weiss <luca@z3ntu.xyz>
 */

/dts-v1/;
#include "mt6589.dtsi"

/ {
	model = "Fairphone 1";
	compatible = "fairphone,fp1", "mediatek,mt6589";

	chosen {
		stdout-path = &uart3;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};
};

&cpus {
	/* SMP is not stable on this board, makes the kernel panic */
	/delete-property/ enable-method;
};

&uart3 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2014 MundoReader S.L.
 * Author: Matthias Brugger <matthias.bgg@gmail.com>
 *
*/

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "mediatek,mt6589";
	interrupt-parent = <&sysirq>;

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "mediatek,mt6589-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
		};

	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		system_clk: dummy13m {
			compatible = "fixed-clock";
			clock-frequency = <13000000>;
			#clock-cells = <0>;
		};

		rtc_clk: dummy32k {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			#clock-cells = <0>;
		};

		uart_clk: dummy26m {
			compatible = "fixed-clock";
			clock-frequency = <26000000>;
			#clock-cells = <0>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		timer: timer@10008000 {
			compatible = "mediatek,mt6577-timer";
			reg = <0x10008000 0x80>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&system_clk>, <&rtc_clk>;
			clock-names = "system-clk", "rtc-clk";
		};

		sysirq: interrupt-controller@10200100 {
			compatible = "mediatek,mt6589-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0x10200100 0x1c>;
		};

		gic: interrupt-controller@10211000 {
			compatible = "arm,cortex-a7-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0x10211000 0x1000>,
			      <0x10212000 0x2000>,
			      <0x10214000 0x2000>,
			      <0x10216000 0x2000>;
		};

		uart0: serial@11006000 {
			compatible = "mediatek,mt6577-uart";
			reg = <0x11006000 0x400>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart1: serial@11007000 {
			compatible = "mediatek,mt6577-uart";
			reg = <0x11007000 0x400>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart2: serial@11008000 {
			compatible = "mediatek,mt6577-uart";
			reg = <0x11008000 0x400>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart3: serial@11009000 {
			compatible = "mediatek,mt6577-uart";
			reg = <0x11009000 0x400>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		wdt: watchdog@10000000 {
			compatible = "mediatek,mt6589-wdt";
			reg = <0x10000000 0x44>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Howard Chen <ibanezchen@gmail.com>
 *
 */

/dts-v1/;
#include "mt6592.dtsi"

/ {
	model = "mt6592 evb";
	compatible = "mediatek,mt6592-evb", "mediatek,mt6592";

	memory {
		device_type = "memory";
		reg = <0x80000000 0x40000000>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Howard Chen <ibanezchen@gmail.com>
 *
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "mediatek,mt6592";
	interrupt-parent = <&sysirq>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
		};
		cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x4>;
		};
		cpu@5 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x5>;
		};
		cpu@6 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x6>;
		};
		cpu@7 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x7>;
		};
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	rtc_clk: dummy32k {
		compatible = "fixed-clock";
		clock-frequency = <32000>;
		#clock-cells = <0>;
	};

	uart_clk: dummy26m {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	timer: timer@10008000 {
		compatible = "mediatek,mt6577-timer";
		reg = <0x10008000 0x80>;
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>, <&rtc_clk>;
		clock-names = "system-clk", "rtc-clk";
	};

	sysirq: interrupt-controller@10200220 {
		compatible = "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0x10200220 0x1c>;
	};

	gic: interrupt-controller@10211000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0x10211000 0x1000>,
		      <0x10212000 0x1000>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt6577-uart";
		reg = <0x11002000 0x400>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt6577-uart";
		reg = <0x11003000 0x400>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt6577-uart";
		reg = <0x11004000 0x400>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt6577-uart";
		reg = <0x11005000 0x400>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&uart_clk>;
		status = "disabled";
	};
};