code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/marvell,prestera.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell Prestera switch family

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - marvell,prestera-98dx3236
              - marvell,prestera-98dx3336
              - marvell,prestera-98dx4251
          - const: marvell,prestera
      - enum:
          - pci11ab,c804
          - pci11ab,c80c
          - pci11ab,cc1e

  reg:
    maxItems: 1

  interrupts:
    maxItems: 3

  dfx:
    description: Reference to the DFX Server bus node.
    $ref: /schemas/types.yaml#/definitions/phandle

  nvmem-cells: true

  nvmem-cell-names: true

if:
  properties:
    compatible:
      contains:
        const: marvell,prestera

# Memory mapped AlleyCat3 family
then:
  properties:
    nvmem-cells: false
    nvmem-cell-names: false
  required:
    - interrupts

# PCI Aldrin family
else:
  properties:
    interrupts: false
    dfx: false

required:
  - compatible
  - reg

# Ports can also be described
additionalProperties:
  type: object

examples:
  - |
    packet-processor@0 {
        compatible = "marvell,prestera-98dx3236", "marvell,prestera";
        reg = <0 0x4000000>;
        interrupts = <33>, <34>, <35>;
        dfx = <&dfx>;
    };

  - |
    pcie@0 {
        #address-cells = <3>;
        #size-cells = <2>;
        ranges = <0x0 0x0 0x0 0x0 0x0 0x0>;
        reg = <0x0 0x0 0x0 0x0 0x0 0x0>;
        device_type = "pci";

        switch@0,0 {
            reg = <0x0 0x0 0x0 0x0 0x0>;
            compatible = "pci11ab,c80c";
            nvmem-cells = <&mac_address 0>;
            nvmem-cell-names = "mac-address";
        };
    };


code:
* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA)

Required properties:
- compatible: could be one of the following:
	"marvell,armada-370-neta"
	"marvell,armada-xp-neta"
	"marvell,armada-3700-neta"
	"marvell,armada-ac5-neta"
- reg: address and length of the register set for the device.
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
- phy-mode: See ethernet.txt file in the same directory
- clocks: List of clocks for this device. At least one clock is
  mandatory for the core clock. If several clocks are given, then the
  clock-names property must be used to identify them.

Optional properties:
- tx-csum-limit: maximum mtu supported by port that allow TX checksum.
  Value is presented in bytes. If not used, by default 1600B is set for
  "marvell,armada-370-neta" and 9800B for others.
- clock-names: List of names corresponding to clocks property; shall be
  "core" for core clock and "bus" for the optional bus clock.
- phys: comphy for the ethernet port, see ../phy/phy-bindings.txt

Optional properties (valid only for Armada XP/38x):

- buffer-manager: a phandle to a buffer manager node. Please refer to
  Documentation/devicetree/bindings/net/marvell-neta-bm.txt
- bm,pool-long: ID of a pool, that will accept all packets of a size
  higher than 'short' pool's threshold (if set) and up to MTU value.
  Obligatory, when the port is supposed to use hardware
  buffer management.
- bm,pool-short: ID of a pool, that will be used for accepting
  packets of a size lower than given threshold. If not set, the port
  will use a single 'long' pool for all packets, as defined above.

Example:

ethernet@70000 {
	compatible = "marvell,armada-370-neta";
	reg = <0x70000 0x2500>;
	interrupts = <8>;
	clocks = <&gate_clk 4>;
	tx-csum-limit = <9800>
	phy = <&phy0>;
	phy-mode = "rgmii-id";
	buffer-manager = <&bm>;
	bm,pool-long = <0>;
	bm,pool-short = <1>;
};

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/net/marvell-bluetooth.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Marvell Bluetooth chips

description: |
  This documents the binding structure and common properties for serial
  attached Marvell Bluetooth devices.

maintainers:
  - Rob Herring <robh@kernel.org>

properties:
  compatible:
    const: mrvl,88w8897

required:
  - compatible

additionalProperties: false

examples:
  - |
    serial {
      bluetooth {
        compatible = "mrvl,88w8897";
      };
    };


code:
Marvell 8897/8997 (sd8897/sd8997) bluetooth devices (SDIO or USB based)
------
The 8997 devices supports multiple interfaces. When used on SDIO interfaces,
the btmrvl driver is used and when used on USB interface, the btusb driver is
used.

Required properties:

  - compatible : should be one of the following:
	* "marvell,sd8897-bt" (for SDIO)
	* "marvell,sd8997-bt" (for SDIO)
	* "usb1286,204e"      (for USB)

Optional properties:

  - marvell,cal-data: Calibration data downloaded to the device during
		      initialization. This is an array of 28 values(u8).
		      This is only applicable to SDIO devices.

  - marvell,wakeup-pin: It represents wakeup pin number of the bluetooth chip.
		        firmware will use the pin to wakeup host system (u16).
  - marvell,wakeup-gap-ms: wakeup gap represents wakeup latency of the host
		      platform. The value will be configured to firmware. This
		      is needed to work chip's sleep feature as expected (u16).
  - interrupt-names: Used only for USB based devices (See below)
  - interrupts : specifies the interrupt pin number to the cpu. For SDIO, the
		 driver will use the first interrupt specified in the interrupt
		 array. For USB based devices, the driver will use the interrupt
		 named "wakeup" from the interrupt-names and interrupt arrays.
		 The driver will request an irq based on this interrupt number.
		 During system suspend, the irq will be enabled so that the
		 bluetooth chip can wakeup host platform under certain
		 conditions. During system resume, the irq will be disabled
		 to make sure unnecessary interrupt is not received.

Example:

IRQ pin 119 is used as system wakeup source interrupt.
wakeup pin 13 and gap 100ms are configured so that firmware can wakeup host
using this device side pin and wakeup latency.

Example for SDIO device follows (calibration data is also available in
below example).

&mmc3 {
	vmmc-supply = <&wlan_en_reg>;
	bus-width = <4>;
	cap-power-off-card;
	keep-power-in-suspend;

	#address-cells = <1>;
	#size-cells = <0>;
	btmrvl: bluetooth@2 {
		compatible = "marvell,sd8897-bt";
		reg = <2>;
		interrupt-parent = <&pio>;
		interrupts = <119 IRQ_TYPE_LEVEL_LOW>;

		marvell,cal-data = /bits/ 8 <
			0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02
			0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00
			0x00 0x00 0xf0 0x00>;
		marvell,wakeup-pin = /bits/ 16 <0x0d>;
		marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
	};
};

Example for USB device:

&usb_host1_ohci {
    #address-cells = <1>;
    #size-cells = <0>;

    mvl_bt1: bt@1 {
	compatible = "usb1286,204e";
	reg = <1>;
	interrupt-parent = <&gpio0>;
	interrupt-names = "wakeup";
	interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
	marvell,wakeup-pin = /bits/ 16 <0x0d>;
	marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
    };
};


code:
* Marvell Armada 380/XP Buffer Manager driver (BM)

Required properties:

- compatible: should be "marvell,armada-380-neta-bm".
- reg: address and length of the register set for the device.
- clocks: a pointer to the reference clock for this device.
- internal-mem: a phandle to BM internal SRAM definition.

Optional properties (port):

- pool<0 : 3>,capacity: size of external buffer pointers' ring maintained
  in DRAM. Can be set for each pool (id 0 : 3) separately. The value has
  to be chosen between 128 and 16352 and it also has to be aligned to 32.
  Otherwise the driver would adjust a given number or choose default if
  not set.
- pool<0 : 3>,pkt-size: maximum size of a packet accepted by a given buffer
  pointers' pool (id 0 : 3). It will be taken into consideration only when pool
  type is 'short'. For 'long' ones it would be overridden by port's MTU.
  If not set a driver will choose a default value.

In order to see how to hook the BM to a given ethernet port, please
refer to Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt.

Example:

- main node:

bm: bm@c8000 {
	compatible = "marvell,armada-380-neta-bm";
	reg = <0xc8000 0xac>;
	clocks = <&gateclk 13>;
	internal-mem = <&bm_bppi>;
	pool2,capacity = <4096>;
	pool1,pkt-size = <512>;
};

- internal SRAM node:

bm_bppi: bm-bppi {
	compatible = "mmio-sram";
	reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
	ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
	#address-cells = <1>;
	#size-cells = <1>;
	clocks = <&gateclk 13>;
};


code:
Marvell Orion/Discovery ethernet controller
=============================================

The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
(Kirkwood, Dove, Orion5x, and Discovery Innovation) and as part of Marvell
Discovery system controller chips (mv64[345]60).

The Discovery ethernet controller is described with two levels of nodes. The
first level describes the ethernet controller itself and the second level
describes up to 3 ethernet port nodes within that controller. The reason for
the multiple levels is that the port registers are interleaved within a single
set of controller registers. Each port node describes port-specific properties.

Note: The above separation is only true for Discovery system controllers.
For Orion SoCs we stick to the separation, although there each controller has
only one port associated. Multiple ports are implemented as multiple single-port
controllers. As Kirkwood has some issues with proper initialization after reset,
an extra compatible string is added for it.

* Ethernet controller node

Required controller properties:
 - #address-cells: shall be 1.
 - #size-cells: shall be 0.
 - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
 - reg: address and length of the controller registers.

Optional controller properties:
 - clocks: phandle reference to the controller clock.
 - marvell,tx-checksum-limit: max tx packet size for hardware checksum.

* Ethernet port node

Required port properties:
 - compatible: shall be one of "marvell,orion-eth-port",
      "marvell,kirkwood-eth-port".
 - reg: port number relative to ethernet controller, shall be 0, 1, or 2.
 - interrupts: port interrupt.
 - local-mac-address: See ethernet.txt file in the same directory.

Optional port properties:
 - marvell,tx-queue-size: size of the transmit ring buffer.
 - marvell,tx-sram-addr: address of transmit descriptor buffer located in SRAM.
 - marvell,tx-sram-size: size of transmit descriptor buffer located in SRAM.
 - marvell,rx-queue-size: size of the receive ring buffer.
 - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
 - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.

and

 - phy-handle: See ethernet.txt file in the same directory.
 - phy-mode: See ethernet.txt file in the same directory.

or

 - speed: port speed if no PHY connected.
 - duplex: port mode if no PHY connected.

* Node example:

mdio-bus {
	...
	ethphy: ethernet-phy@8 {
		...
	};
};

eth: ethernet-controller@72000 {
	compatible = "marvell,orion-eth";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x72000 0x2000>;
	clocks = <&gate_clk 2>;
	marvell,tx-checksum-limit = <1600>;

	ethernet@0 {
		compatible = "marvell,orion-eth-port";
		reg = <0>;
		interrupts = <29>;
		phy-handle = <&ethphy>;
		local-mac-address = [00 00 00 00 00 00];
	};
};


code:
* Marvell PXA168 Ethernet Controller

Required properties:
- compatible: should be "marvell,pxa168-eth".
- reg: address and length of the register set for the device.
- interrupts: interrupt for the device.
- clocks: pointer to the clock for the device.

Optional properties:
- port-id: Ethernet port number. Should be '0','1' or '2'.
- #address-cells: must be 1 when using sub-nodes.
- #size-cells: must be 0 when using sub-nodes.
- phy-handle: see ethernet.txt file in the same directory.

The MAC address will be determined using the optional properties
defined in ethernet.txt.

Sub-nodes:
Each PHY can be represented as a sub-node. This is not mandatory.

Sub-nodes required properties:
- reg: the MDIO address of the PHY.

Example:

	eth0: ethernet@f7b90000 {
		compatible = "marvell,pxa168-eth";
		reg = <0xf7b90000 0x10000>;
		clocks = <&chip CLKID_GETH0>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		phy-handle = <&ethphy0>;

		ethphy0: ethernet-phy@0 {
			reg = <0>;
		};
	};


code:
* Maxim (Dallas) DS26522 Dual T1/E1/J1 Transceiver

Required properties:
- compatible: Should contain "maxim,ds26522".
- reg: SPI CS.
- spi-max-frequency: SPI clock.

Example:
	slic@1 {
		compatible = "maxim,ds26522";
		reg = <1>;
		spi-max-frequency = <2000000>; /* input clock */
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mctp-i2c-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MCTP I2C transport binding

maintainers:
  - Matt Johnston <matt@codeconstruct.com.au>

description: |
  An mctp-i2c-controller defines a local MCTP endpoint on an I2C controller.
  MCTP I2C is specified by DMTF DSP0237.

  An mctp-i2c-controller must be attached to an I2C adapter which supports
  slave functionality. I2C busses (either directly or as subordinate mux
  busses) are attached to the mctp-i2c-controller with a 'mctp-controller'
  property on each used bus. Each mctp-controller I2C bus will be presented
  to the host system as a separate MCTP I2C instance.

properties:
  compatible:
    const: mctp-i2c-controller

  reg:
    minimum: 0x40000000
    maximum: 0x4000007f
    description: |
      7 bit I2C address of the local endpoint.
      I2C_OWN_SLAVE_ADDRESS (1<<30) flag must be set.

additionalProperties: false

required:
  - compatible
  - reg

examples:
  - |
    // Basic case of a single I2C bus
    #include <dt-bindings/i2c/i2c.h>

    i2c {
      #address-cells = <1>;
      #size-cells = <0>;
      mctp-controller;

      mctp@30 {
        compatible = "mctp-i2c-controller";
        reg = <(0x30 | I2C_OWN_SLAVE_ADDRESS)>;
      };
    };

  - |
    // Mux topology with multiple MCTP-handling busses under
    // a single mctp-i2c-controller.
    // i2c1 and i2c6 can have MCTP devices, i2c5 does not.
    #include <dt-bindings/i2c/i2c.h>

    i2c1: i2c {
      #address-cells = <1>;
      #size-cells = <0>;
      mctp-controller;

      mctp@50 {
        compatible = "mctp-i2c-controller";
        reg = <(0x50 | I2C_OWN_SLAVE_ADDRESS)>;
      };
    };

    i2c-mux {
      #address-cells = <1>;
      #size-cells = <0>;
      i2c-parent = <&i2c1>;

      i2c5: i2c@0 {
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0>;
        eeprom@33 {
          reg = <0x33>;
        };
      };

      i2c6: i2c@1 {
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <1>;
        mctp-controller;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mdio-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MDIO on GPIOs

maintainers:
  - Andrew Lunn <andrew@lunn.ch>
  - Heiner Kallweit <hkallweit1@gmail.com>
  - Russell King <linux@armlinux.org.uk>

allOf:
  - $ref: "mdio.yaml#"

properties:
  compatible:
    enum:
      - virtual,mdio-gpio
      - microchip,mdio-smi0

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  gpios:
    minItems: 2
    items:
      - description: MDC
      - description: MDIO
      - description: MDO

#Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases"
#node.
additionalProperties:
  type: object

examples:
  - |
    aliases {
        mdio-gpio0 = &mdio0;
    };

    mdio0: mdio {
      compatible = "virtual,mdio-gpio";
      #address-cells = <1>;
      #size-cells = <0>;
      gpios = <&qe_pio_a 11>,
              <&qe_pio_c 6>;
      ethphy0: ethernet-phy@0 {
        reg = <0>;
      };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.

maintainers:
  - Andrew Lunn <andrew@lunn.ch>

description:
  This is a special case of a MDIO bus multiplexer.  One or more GPIO
  lines are used to control which child bus is connected.

allOf:
  - $ref: /schemas/net/mdio-mux.yaml#

properties:
  compatible:
    const: mdio-mux-gpio

  gpios:
    description:
      List of GPIOs used to control the multiplexer, least significant bit first.
    minItems: 1
    maxItems: 32

required:
  - compatible
  - gpios

unevaluatedProperties: false

examples:
  - |
    /*
     An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
     pair of GPIO lines.  Child busses 2 and 3 populated with 4
     PHYs each.
     */
    mdio-mux {
        compatible = "mdio-mux-gpio";
        gpios = <&gpio1 3 0>, <&gpio1 4 0>;
        mdio-parent-bus = <&smi1>;
        #address-cells = <1>;
        #size-cells = <0>;

        mdio@2 {
            reg = <2>;
            #address-cells = <1>;
            #size-cells = <0>;

            ethernet-phy@1 {
                reg = <1>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <10 8>; /* Pin 10, active low */
            };
            ethernet-phy@2 {
                reg = <2>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <10 8>; /* Pin 10, active low */
            };
            ethernet-phy@3 {
                reg = <3>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <10 8>; /* Pin 10, active low */
            };
            ethernet-phy@4 {
                reg = <4>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <10 8>; /* Pin 10, active low */
            };
        };

        mdio@3 {
            reg = <3>;
            #address-cells = <1>;
            #size-cells = <0>;

            ethernet-phy@1 {
                reg = <1>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <12 8>; /* Pin 12, active low */
            };
            ethernet-phy@2 {
                reg = <2>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <12 8>; /* Pin 12, active low */
            };
            ethernet-phy@3 {
                reg = <3>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <12 8>; /* Pin 12, active low */
            };
            ethernet-phy@4 {
                reg = <4>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <12 8>; /* Pin 12, active low */
            };
        };
    };
...


code:
Properties for the MDIO bus multiplexer/glue of Amlogic G12a SoC family.

This is a special case of a MDIO bus multiplexer. It allows to choose between
the internal mdio bus leading to the embedded 10/100 PHY or the external
MDIO bus.

Required properties in addition to the generic multiplexer properties:
- compatible : amlogic,g12a-mdio-mux
- reg: physical address and length of the multiplexer/glue registers
- clocks: list of clock phandle, one for each entry clock-names.
- clock-names: should contain the following:
  * "pclk"   : peripheral clock.
  * "clkin0" : platform crytal
  * "clkin1" : SoC 50MHz MPLL

Example :

mdio_mux: mdio-multiplexer@4c000 {
	compatible = "amlogic,g12a-mdio-mux";
	reg = <0x0 0x4c000 0x0 0xa4>;
	clocks = <&clkc CLKID_ETH_PHY>,
		 <&xtal>,
		 <&clkc CLKID_MPLL_5OM>;
	clock-names = "pclk", "clkin0", "clkin1";
	mdio-parent-bus = <&mdio0>;
	#address-cells = <1>;
	#size-cells = <0>;

	ext_mdio: mdio@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	int_mdio: mdio@1 {
		reg = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		internal_ephy: ethernet-phy@8 {
			compatible = "ethernet-phy-id0180.3301",
				     "ethernet-phy-ieee802.3-c22";
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <8>;
			max-speed = <100>;
		};
	};
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device

maintainers:
  - Andrew Lunn <andrew@lunn.ch>

description: |+
  This is a special case of a MDIO bus multiplexer.  A memory-mapped device,
  like an FPGA, is used to control which child bus is connected.  The mdio-mux
  node must be a child of the memory-mapped device.  The driver currently only
  supports devices with 8, 16 or 32-bit registers.

allOf:
  - $ref: /schemas/net/mdio-mux.yaml#

properties:
  compatible:
    items:
      - const: mdio-mux-mmioreg
      - const: mdio-mux

  reg:
    description: Contains the offset of the register that controls the bus
      multiplexer. The size field in the 'reg' property is the size of register,
      and must therefore be 1, 2, or 4.
    maxItems: 1

  mux-mask:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Contains an eight-bit mask that specifies which bits in the
      register control the actual bus multiplexer.  The 'reg' property of each
      child mdio-mux node must be constrained by this mask.

required:
  - compatible
  - reg
  - mux-mask

unevaluatedProperties: false

examples:
  - |
    mdio-mux@9 {
        compatible = "mdio-mux-mmioreg", "mdio-mux";
        mdio-parent-bus = <&xmdio0>;
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <9 1>; // BRDCFG1
        mux-mask = <0x6>; // EMI2

        mdio@0 {  // Slot 1 XAUI (FM2)
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <0>;

            phy_xgmii_slot1: ethernet-phy@4 {
                compatible = "ethernet-phy-ieee802.3-c45";
                reg = <4>;
            };
        };

        mdio@2 {  // Slot 2 XAUI (FM1)
            reg = <2>;
            #address-cells = <1>;
            #size-cells = <0>;

            ethernet-phy@4 {
                compatible = "ethernet-phy-ieee802.3-c45";
                reg = <4>;
            };
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Properties for an MDIO bus multiplexer consumer device

maintainers:
  - Andrew Lunn <andrew@lunn.ch>

description: |+
  This is a special case of MDIO mux when MDIO mux is defined as a consumer
  of a mux producer device. The mux producer can be of any type like mmio mux
  producer, gpio mux producer or generic register based mux producer.

allOf:
  - $ref: /schemas/net/mdio-mux.yaml#

properties:
  compatible:
    const: mdio-mux-multiplexer

  mux-controls:
    maxItems: 1

required:
  - compatible
  - mux-controls

unevaluatedProperties: false

examples:
  - |
    mux: mux-controller { // Mux Producer
        compatible = "reg-mux";
        #mux-control-cells = <1>;
        mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
                        <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
    };

    mdio-mux-1 { // Mux consumer
        compatible = "mdio-mux-multiplexer";
        mux-controls = <&mux 0>;
        mdio-parent-bus = <&emdio1>;
        #address-cells = <1>;
        #size-cells = <0>;

        mdio@0 {
            reg = <0x0>;
            #address-cells = <1>;
            #size-cells = <0>;
        };

        mdio@8 {
            reg = <0x8>;
            #address-cells = <1>;
            #size-cells = <0>;
        };
    };

    mdio-mux-2 { // Mux consumer
        compatible = "mdio-mux-multiplexer";
        mux-controls = <&mux 1>;
        mdio-parent-bus = <&emdio2>;
        #address-cells = <1>;
        #size-cells = <0>;

        mdio@0 {
            reg = <0x0>;
            #address-cells = <1>;
            #size-cells = <0>;
        };

        mdio@1 {
            reg = <0x1>;
            #address-cells = <1>;
            #size-cells = <0>;
        };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mdio-mux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common MDIO bus multiplexer/switch properties.

maintainers:
  - Andrew Lunn <andrew@lunn.ch>

description: |+
  An MDIO bus multiplexer/switch will have several child busses that are
  numbered uniquely in a device dependent manner.  The nodes for an MDIO
  bus multiplexer/switch will have one child node for each child bus.

properties:
  mdio-parent-bus:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      The phandle of the MDIO bus that this multiplexer's master-side port is
      connected to.

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

patternProperties:
  '^mdio@[0-9a-f]+$':
    $ref: mdio.yaml#
    unevaluatedProperties: false

    properties:
      reg:
        maxItems: 1

additionalProperties: true

...


code: This file has moved to mdio.yaml.


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MDIO Bus Generic Binding

maintainers:
  - Andrew Lunn <andrew@lunn.ch>
  - Florian Fainelli <f.fainelli@gmail.com>
  - Heiner Kallweit <hkallweit1@gmail.com>

description:
  These are generic properties that can apply to any MDIO bus. Any
  MDIO bus must have a list of child nodes, one per device on the
  bus. These should follow the generic ethernet-phy.yaml document, or
  a device specific binding document.

properties:
  $nodename:
    pattern: "^mdio(@.*)?"

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  reset-gpios:
    maxItems: 1
    description:
      The phandle and specifier for the GPIO that controls the RESET
      lines of all devices on that MDIO bus.

  reset-delay-us:
    description:
      RESET pulse width in microseconds. It applies to all MDIO devices
      and must therefore be appropriately determined based on all devices
      requirements (maximum value of all per-device RESET pulse widths).

  reset-post-delay-us:
    description:
      Delay after reset deassert in microseconds. It applies to all MDIO
      devices and it's determined by how fast all devices are ready for
      communication. This delay happens just before e.g. Ethernet PHY
      type ID auto detection.

  clock-frequency:
    description:
      Desired MDIO bus clock frequency in Hz. Values greater than IEEE 802.3
      defined 2.5MHz should only be used when all devices on the bus support
      the given clock speed.

  suppress-preamble:
    description:
      The 32 bit preamble should be suppressed. In order for this to
      work, all devices on the bus must support suppressed preamble.
    type: boolean

patternProperties:
  '@[0-9a-f]+$':
    type: object

    properties:
      reg:
        minimum: 0
        maximum: 31
        description:
          The ID number for the device.

      broken-turn-around:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          If set, indicates the MDIO device does not correctly release
          the turn around line low at end of the control phase of the
          MDIO transaction.

      reset-gpios:
        maxItems: 1
        description:
          The GPIO phandle and specifier for the MDIO reset signal.

      reset-assert-us:
        description:
          Delay after the reset was asserted in microseconds. If this
          property is missing the delay will be skipped.

      reset-deassert-us:
        description:
          Delay after the reset was deasserted in microseconds. If
          this property is missing the delay will be skipped.

    required:
      - reg

additionalProperties: true

examples:
  - |
    davinci_mdio: mdio@5c030000 {
        reg = <0x5c030000 0x1000>;
        #address-cells = <1>;
        #size-cells = <0>;

        reset-gpios = <&gpio2 5 1>;
        reset-delay-us = <2>;

        ethphy0: ethernet-phy@1 {
            reg = <1>;
        };

        ethphy1: ethernet-phy@3 {
            reg = <3>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Frame Engine Ethernet controller

maintainers:
  - Lorenzo Bianconi <lorenzo@kernel.org>
  - Felix Fietkau <nbd@nbd.name>

description:
  The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
  have dual GMAC ports.

properties:
  compatible:
    enum:
      - mediatek,mt2701-eth
      - mediatek,mt7623-eth
      - mediatek,mt7622-eth
      - mediatek,mt7629-eth
      - mediatek,mt7986-eth
      - ralink,rt5350-eth

  reg:
    maxItems: 1

  clocks: true
  clock-names: true

  interrupts:
    minItems: 3
    maxItems: 4

  power-domains:
    maxItems: 1

  resets:
    maxItems: 3

  reset-names:
    items:
      - const: fe
      - const: gmac
      - const: ppe

  mediatek,ethsys:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon node that handles the port setup.

  cci-control-port: true

  mediatek,hifsys:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the mediatek hifsys controller used to provide various clocks
      and reset to the system.

  mediatek,sgmiisys:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 1
    maxItems: 2
    items:
      maxItems: 1
    description:
      A list of phandle to the syscon node that handles the SGMII setup which is required for
      those SoCs equipped with SGMII.

  mediatek,wed:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 2
    maxItems: 2
    items:
      maxItems: 1
    description:
      List of phandles to wireless ethernet dispatch nodes.

  dma-coherent: true

  mdio-bus:
    $ref: mdio.yaml#
    unevaluatedProperties: false

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

allOf:
  - $ref: "ethernet-controller.yaml#"
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt2701-eth
              - mediatek,mt7623-eth
    then:
      properties:
        interrupts:
          maxItems: 3

        clocks:
          minItems: 4
          maxItems: 4

        clock-names:
          items:
            - const: ethif
            - const: esw
            - const: gp1
            - const: gp2

        mediatek,pctl:
          $ref: /schemas/types.yaml#/definitions/phandle
          description:
            Phandle to the syscon node that handles the ports slew rate and
            driver current.

        mediatek,wed: false

  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt7622-eth
    then:
      properties:
        interrupts:
          maxItems: 3

        clocks:
          minItems: 11
          maxItems: 11

        clock-names:
          items:
            - const: ethif
            - const: esw
            - const: gp0
            - const: gp1
            - const: gp2
            - const: sgmii_tx250m
            - const: sgmii_rx250m
            - const: sgmii_cdr_ref
            - const: sgmii_cdr_fb
            - const: sgmii_ck
            - const: eth2pll

        mediatek,sgmiisys:
          minItems: 1
          maxItems: 1

        mediatek,pcie-mirror:
          $ref: /schemas/types.yaml#/definitions/phandle
          description:
            Phandle to the mediatek pcie-mirror controller.

  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt7629-eth
    then:
      properties:
        interrupts:
          maxItems: 3

        clocks:
          minItems: 17
          maxItems: 17

        clock-names:
          items:
            - const: ethif
            - const: sgmiitop
            - const: esw
            - const: gp0
            - const: gp1
            - const: gp2
            - const: fe
            - const: sgmii_tx250m
            - const: sgmii_rx250m
            - const: sgmii_cdr_ref
            - const: sgmii_cdr_fb
            - const: sgmii2_tx250m
            - const: sgmii2_rx250m
            - const: sgmii2_cdr_ref
            - const: sgmii2_cdr_fb
            - const: sgmii_ck
            - const: eth2pll

        mediatek,infracfg:
          $ref: /schemas/types.yaml#/definitions/phandle
          description:
            Phandle to the syscon node that handles the path from GMAC to
            PHY variants.

        mediatek,sgmiisys:
          minItems: 2
          maxItems: 2

        mediatek,wed: false

  - if:
      properties:
        compatible:
          contains:
            const: mediatek,mt7986-eth
    then:
      properties:
        interrupts:
          minItems: 4

        clocks:
          minItems: 15
          maxItems: 15

        clock-names:
          items:
            - const: fe
            - const: gp2
            - const: gp1
            - const: wocpu1
            - const: wocpu0
            - const: sgmii_tx250m
            - const: sgmii_rx250m
            - const: sgmii_cdr_ref
            - const: sgmii_cdr_fb
            - const: sgmii2_tx250m
            - const: sgmii2_rx250m
            - const: sgmii2_cdr_ref
            - const: sgmii2_cdr_fb
            - const: netsys0
            - const: netsys1

        mediatek,sgmiisys:
          minItems: 2
          maxItems: 2

        mediatek,wed-pcie:
          $ref: /schemas/types.yaml#/definitions/phandle
          description:
            Phandle to the mediatek wed-pcie controller.

patternProperties:
  "^mac@[0-1]$":
    type: object
    additionalProperties: false
    allOf:
      - $ref: ethernet-controller.yaml#
    description:
      Ethernet MAC node
    properties:
      compatible:
        const: mediatek,eth-mac

      reg:
        maxItems: 1

      phy-handle: true

      phy-mode: true

    required:
      - reg
      - compatible
      - phy-handle

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - mediatek,ethsys

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/mt7622-clk.h>
    #include <dt-bindings/power/mt7622-power.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      ethernet: ethernet@1b100000 {
        compatible = "mediatek,mt7622-eth";
        reg = <0 0x1b100000 0 0x20000>;
        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
                     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
                     <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
        clocks = <&topckgen CLK_TOP_ETH_SEL>,
                 <&ethsys CLK_ETH_ESW_EN>,
                 <&ethsys CLK_ETH_GP0_EN>,
                 <&ethsys CLK_ETH_GP1_EN>,
                 <&ethsys CLK_ETH_GP2_EN>,
                 <&sgmiisys CLK_SGMII_TX250M_EN>,
                 <&sgmiisys CLK_SGMII_RX250M_EN>,
                 <&sgmiisys CLK_SGMII_CDR_REF>,
                 <&sgmiisys CLK_SGMII_CDR_FB>,
                 <&topckgen CLK_TOP_SGMIIPLL>,
                 <&apmixedsys CLK_APMIXED_ETH2PLL>;
        clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
                      "sgmii_tx250m", "sgmii_rx250m",
                      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
                      "eth2pll";
        power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
        mediatek,ethsys = <&ethsys>;
        mediatek,sgmiisys = <&sgmiisys>;
        cci-control-port = <&cci_control2>;
        mediatek,pcie-mirror = <&pcie_mirror>;
        mediatek,hifsys = <&hifsys>;
        dma-coherent;

        #address-cells = <1>;
        #size-cells = <0>;

        mdio0: mdio-bus {
          #address-cells = <1>;
          #size-cells = <0>;

          phy0: ethernet-phy@0 {
            reg = <0>;
          };

          phy1: ethernet-phy@1 {
            reg = <1>;
          };
        };

        gmac0: mac@0 {
          compatible = "mediatek,eth-mac";
          phy-mode = "rgmii";
          phy-handle = <&phy0>;
          reg = <0>;
        };

        gmac1: mac@1 {
          compatible = "mediatek,eth-mac";
          phy-mode = "rgmii";
          phy-handle = <&phy1>;
          reg = <1>;
        };
      };
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/mt7622-clk.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      eth: ethernet@15100000 {
        #define CLK_ETH_FE_EN               0
        #define CLK_ETH_WOCPU1_EN           3
        #define CLK_ETH_WOCPU0_EN           4
        #define CLK_TOP_NETSYS_SEL          43
        #define CLK_TOP_NETSYS_500M_SEL     44
        #define CLK_TOP_NETSYS_2X_SEL       46
        #define CLK_TOP_SGM_325M_SEL        47
        #define CLK_APMIXED_NET2PLL         1
        #define CLK_APMIXED_SGMPLL          3

        compatible = "mediatek,mt7986-eth";
        reg = <0 0x15100000 0 0x80000>;
        interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&ethsys CLK_ETH_FE_EN>,
                 <&ethsys CLK_ETH_GP2_EN>,
                 <&ethsys CLK_ETH_GP1_EN>,
                 <&ethsys CLK_ETH_WOCPU1_EN>,
                 <&ethsys CLK_ETH_WOCPU0_EN>,
                 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
                 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
                 <&sgmiisys0 CLK_SGMII_CDR_REF>,
                 <&sgmiisys0 CLK_SGMII_CDR_FB>,
                 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
                 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
                 <&sgmiisys1 CLK_SGMII_CDR_REF>,
                 <&sgmiisys1 CLK_SGMII_CDR_FB>,
                 <&topckgen CLK_TOP_NETSYS_SEL>,
                 <&topckgen CLK_TOP_NETSYS_SEL>;
        clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
                      "sgmii_tx250m", "sgmii_rx250m",
                      "sgmii_cdr_ref", "sgmii_cdr_fb",
                      "sgmii2_tx250m", "sgmii2_rx250m",
                      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
                      "netsys0", "netsys1";
        mediatek,ethsys = <&ethsys>;
        mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
        assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
                          <&topckgen CLK_TOP_SGM_325M_SEL>;
        assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
                                 <&apmixedsys CLK_APMIXED_SGMPLL>;

        #address-cells = <1>;
        #size-cells = <0>;

        mdio: mdio-bus {
          #address-cells = <1>;
          #size-cells = <0>;

          phy5: ethernet-phy@0 {
            compatible = "ethernet-phy-id67c9.de0a";
            phy-mode = "2500base-x";
            reset-gpios = <&pio 6 1>;
            reset-deassert-us = <20000>;
            reg = <5>;
          };

          phy6: ethernet-phy@1 {
            compatible = "ethernet-phy-id67c9.de0a";
            phy-mode = "2500base-x";
            reg = <6>;
          };
        };

        mac0: mac@0 {
          compatible = "mediatek,eth-mac";
          phy-mode = "2500base-x";
          phy-handle = <&phy5>;
          reg = <0>;
        };

        mac1: mac@1 {
          compatible = "mediatek,eth-mac";
          phy-mode = "2500base-x";
          phy-handle = <&phy6>;
          reg = <1>;
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek STAR Ethernet MAC Controller

maintainers:
  - Bartosz Golaszewski <bgolaszewski@baylibre.com>

description:
  This Ethernet MAC is used on the MT8* family of SoCs from MediaTek.
  It's compliant with 802.3 standards and supports half- and full-duplex
  modes with flow-control as well as CRC offloading and VLAN tags.

allOf:
  - $ref: "ethernet-controller.yaml#"

properties:
  compatible:
    enum:
      - mediatek,mt8516-eth
      - mediatek,mt8518-eth
      - mediatek,mt8175-eth
      - mediatek,mt8365-eth

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    maxItems: 3

  clock-names:
    additionalItems: false
    items:
      - const: core
      - const: reg
      - const: trans

  mediatek,pericfg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the device containing the PERICFG register range. This is used
      to control the MII mode.

  mediatek,rmii-rxc:
    type: boolean
    description:
      If present, indicates that the RMII reference clock, which is from external
      PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin.

  mediatek,rxc-inverse:
    type: boolean
    description:
      If present, indicates that clock on RXC pad will be inversed.

  mediatek,txc-inverse:
    type: boolean
    description:
      If present, indicates that clock on TXC pad will be inversed.

  mdio:
    $ref: mdio.yaml#
    unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - mediatek,pericfg
  - phy-handle

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8516-clk.h>

    ethernet: ethernet@11180000 {
        compatible = "mediatek,mt8516-eth";
        reg = <0x11180000 0x1000>;
        mediatek,pericfg = <&pericfg>;
        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>;
        clocks = <&topckgen CLK_TOP_RG_ETH>,
                 <&topckgen CLK_TOP_66M_ETH>,
                 <&topckgen CLK_TOP_133M_ETH>;
        clock-names = "core", "reg", "trans";
        phy-handle = <&eth_phy>;
        phy-mode = "rmii";

        mdio {
            #address-cells = <1>;
            #size-cells = <0>;

            eth_phy: ethernet-phy@0 {
                reg = <0>;
            };
        };
    };


code:
MediaTek SoC built-in Bluetooth Devices
==================================

This device is a serial attached device to BTIF device and thus it must be a
child node of the serial node with BTIF. The dt-bindings details for BTIF
device can be known via Documentation/devicetree/bindings/serial/8250.yaml.

Required properties:

- compatible:	Must be
		  "mediatek,mt7622-bluetooth": for MT7622 SoC
- clocks:	Should be the clock specifiers corresponding to the entry in
		clock-names property.
- clock-names:	Should contain "ref" entries.
- power-domains: Phandle to the power domain that the device is part of

Example:

	btif: serial@1100c000 {
		compatible = "mediatek,mt7622-btif",
			     "mediatek,mtk-btif";
		reg = <0 0x1100c000 0 0x1000>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_BTIF_PD>;
		clock-names = "main";
		reg-shift = <2>;
		reg-io-width = <4>;

		bluetooth {
			compatible = "mediatek,mt7622-bluetooth";
			power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
			clocks = <&clk25m>;
			clock-names = "ref";
		};
	};

MediaTek UART based Bluetooth Devices
==================================

This device is a serial attached device to UART device and thus it must be a
child node of the serial node with UART.

Please refer to the following documents for generic properties:

	Documentation/devicetree/bindings/serial/serial.yaml

Required properties:

- compatible:	Must be
		  "mediatek,mt7663u-bluetooth": for MT7663U device
		  "mediatek,mt7668u-bluetooth": for MT7668U device
- vcc-supply:	Main voltage regulator

If the pin controller on the platform can support both pinmux and GPIO
control such as the most of MediaTek platform. Please use below properties.

- pinctrl-names: Should be "default", "runtime"
- pinctrl-0: Should contain UART RXD low when the device is powered up to
	     enter proper bootstrap mode.
- pinctrl-1: Should contain UART mode pin ctrl

Else, the pin controller on the platform only can support pinmux control and
the GPIO control still has to rely on the dedicated GPIO controller such as
a legacy MediaTek SoC, MT7621. Please use the below properties.

- boot-gpios:	GPIO same to the pin as UART RXD and used to keep LOW when
		the device is powered up to enter proper bootstrap mode when
- pinctrl-names: Should be "default"
- pinctrl-0: Should contain UART mode pin ctrl

Optional properties:

- reset-gpios:	GPIO used to reset the device whose initial state keeps low,
		if the GPIO is missing, then board-level design should be
		guaranteed.
- clocks:	Should be the clock specifiers corresponding to the entry in
		clock-names property. If the clock is missing, then board-level
		design should be guaranteed.
- clock-names:	Should contain "osc" entry for the external oscillator.
- current-speed:  Current baud rate of the device whose defaults to 921600

Example:

	uart1_pins_boot: uart1-default {
		pins-dat {
			pinmux = <MT7623_PIN_81_URXD1_FUNC_GPIO81>;
			output-low;
		};
	};

	uart1_pins_runtime: uart1-runtime {
		pins-dat {
			pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
				 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
		};
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt7623-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART1_SEL>,
			 <&pericfg CLK_PERI_UART1>;
		clock-names = "baud", "bus";

		bluetooth {
			compatible = "mediatek,mt7663u-bluetooth";
			vcc-supply = <&reg_5v>;
			reset-gpios = <&pio 24 GPIO_ACTIVE_LOW>;
			pinctrl-names = "default", "runtime";
			pinctrl-0 = <&uart1_pins_boot>;
			pinctrl-1 = <&uart1_pins_runtime>;
			current-speed = <921600>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek DWMAC glue layer controller

maintainers:
  - Biao Huang <biao.huang@mediatek.com>

description:
  This file documents platform glue layer for stmmac.

# We need a select here so we don't match all nodes with 'snps,dwmac'
select:
  properties:
    compatible:
      contains:
        enum:
          - mediatek,mt2712-gmac
          - mediatek,mt8188-gmac
          - mediatek,mt8195-gmac
  required:
    - compatible

allOf:
  - $ref: "snps,dwmac.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt2712-gmac
          - const: snps,dwmac-4.20a
      - items:
          - enum:
              - mediatek,mt8195-gmac
          - const: snps,dwmac-5.10a
      - items:
          - enum:
              - mediatek,mt8188-gmac
          - const: mediatek,mt8195-gmac
          - const: snps,dwmac-5.10a

  clocks:
    minItems: 5
    items:
      - description: AXI clock
      - description: APB clock
      - description: MAC Main clock
      - description: PTP clock
      - description: RMII reference clock provided by MAC
      - description: MAC clock gate

  clock-names:
    minItems: 5
    items:
      - const: axi
      - const: apb
      - const: mac_main
      - const: ptp_ref
      - const: rmii_internal
      - const: mac_cg

  power-domains:
    maxItems: 1

  mediatek,pericfg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      The phandle to the syscon node that control ethernet
      interface and timing delay.

  mediatek,tx-delay-ps:
    description:
      The internal TX clock delay (provided by this driver) in nanoseconds.
      For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
      or will round down. Range 0~31*170.
      For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
      or will round down. Range 0~31*550.
      For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
      or will round down. Range 0~31*290.

  mediatek,rx-delay-ps:
    description:
      The internal RX clock delay (provided by this driver) in nanoseconds.
      For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
      or will round down. Range 0~31*170.
      For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
      or will round down. Range 0~31*550.
      For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
      of 290, or will round down. Range 0~31*290.

  mediatek,rmii-rxc:
    type: boolean
    description:
      If present, indicates that the RMII reference clock, which is from external
      PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin.

  mediatek,rmii-clk-from-mac:
    type: boolean
    description:
      If present, indicates that MAC provides the RMII reference clock, which
      outputs to TXC pin only.

  mediatek,txc-inverse:
    type: boolean
    description:
      If present, indicates that
      1. tx clock will be inversed in MII/RGMII case,
      2. tx clock inside MAC will be inversed relative to reference clock
         which is from external PHYs in RMII case, and it rarely happen.
      3. the reference clock, which outputs to TXC pin will be inversed in RMII case
         when the reference clock is from MAC.

  mediatek,rxc-inverse:
    type: boolean
    description:
      If present, indicates that
      1. rx clock will be inversed in MII/RGMII case.
      2. reference clock will be inversed when arrived at MAC in RMII case, when
         the reference clock is from external PHYs.
      3. the inside clock, which be sent to MAC, will be inversed in RMII case when
         the reference clock is from MAC.

  mediatek,mac-wol:
    type: boolean
    description:
      If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled.
      Otherwise, PHY WOL is perferred.

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - phy-mode
  - mediatek,pericfg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt2712-clk.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/mt2712-power.h>

    eth: ethernet@1101c000 {
        compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
        reg = <0x1101c000 0x1300>;
        interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
        interrupt-names = "macirq";
        phy-mode ="rgmii-rxid";
        mac-address = [00 55 7b b5 7d f7];
        clock-names = "axi",
                      "apb",
                      "mac_main",
                      "ptp_ref",
                      "rmii_internal";
        clocks = <&pericfg CLK_PERI_GMAC>,
                 <&pericfg CLK_PERI_GMAC_PCLK>,
                 <&topckgen CLK_TOP_ETHER_125M_SEL>,
                 <&topckgen CLK_TOP_ETHER_50M_SEL>,
                 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
        assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
                          <&topckgen CLK_TOP_ETHER_50M_SEL>,
                          <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
        assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
                                 <&topckgen CLK_TOP_APLL1_D3>,
                                 <&topckgen CLK_TOP_ETHERPLL_50M>;
        power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
        mediatek,pericfg = <&pericfg>;
        mediatek,tx-delay-ps = <1530>;
        snps,txpbl = <1>;
        snps,rxpbl = <1>;
        snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
        snps,reset-delays-us = <0 10000 10000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/micrel,ks8851.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Micrel KS8851 Ethernet MAC (SPI and Parallel bus options)

maintainers:
  - Marek Vasut <marex@denx.de>

properties:
  compatible:
    enum:
      - micrel,ks8851      # SPI bus option
      - micrel,ks8851-mll  # Parallel bus option

  interrupts:
    maxItems: 1

  reg:
    minItems: 1
    items:
      - description: SPI or Parallel bus hardware address
      - description: Parallel bus command mode address

  reset-gpios:
    maxItems: 1
    description:
      The reset_n input pin

  vdd-supply:
    description: |
      Analog 3.3V supply for Ethernet MAC

  vdd-io-supply:
    description: |
      Digital 1.8V IO supply for Ethernet MAC

required:
  - compatible
  - reg
  - interrupts

allOf:
  - $ref: ethernet-controller.yaml#
  - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: micrel,ks8851
    then:
      properties:
        reg:
          maxItems: 1
  - if:
      properties:
        compatible:
          contains:
            const: micrel,ks8851-mll
    then:
      properties:
        reg:
          minItems: 2

unevaluatedProperties: false

examples:
  - |
    /* SPI bus option */
    spi {
        #address-cells = <1>;
        #size-cells = <0>;
        ethernet@0 {
            compatible = "micrel,ks8851";
            reg = <0>;
            interrupt-parent = <&msmgpio>;
            interrupts = <90 8>;
            vdd-supply = <&ext_l2>;
            vdd-io-supply = <&pm8921_lvs6>;
            reset-gpios = <&msmgpio 89 0>;
        };
    };
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    /* Parallel bus option */
    memory-controller {
        #address-cells = <2>;
        #size-cells = <1>;
        ethernet@1,0 {
            compatible = "micrel,ks8851-mll";
            reg = <1 0x0 0x2>, <1 0x2 0x20000>;
            interrupt-parent = <&gpioc>;
            interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
        };
    };


code:
Micrel KS8995 SPI controlled Ethernet Switch families

Required properties (according to spi-bus.txt):
- compatible: either "micrel,ks8995", "micrel,ksz8864" or "micrel,ksz8795"

Optional properties:
- reset-gpios : phandle of gpio that will be used to reset chip during probe

Example:

spi-master {
	...
	switch@0 {
		compatible = "micrel,ksz8795";

		reg = <0>;
		spi-max-frequency = <50000000>;
		reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
	};
};


code:
Micrel KSZ9021/KSZ9031/KSZ9131 Gigabit Ethernet PHY

Some boards require special tuning values, particularly when it comes
to clock delays. You can specify clock delay values in the PHY OF
device node. Deprecated, but still supported, these properties can
also be added to an Ethernet OF device node.

Note that these settings are applied after any phy-specific fixup from
phy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c),
and therefore may overwrite them.

KSZ9021:

  All skew control options are specified in picoseconds. The minimum
  value is 0, the maximum value is 3000, and it can be specified in 200ps
  steps, *but* these values are in not fact what you get because this chip's
  skew values actually increase in 120ps steps, starting from -840ps. The
  incorrect values came from an error in the original KSZ9021 datasheet
  before it was corrected in revision 1.2 (Feb 2014), but it is too late to
  change the driver now because of the many existing device trees that have
  been created using values that go up in increments of 200.

  The following table shows the actual skew delay you will get for each of the
  possible devicetree values, and the number that will be programmed into the
  corresponding pad skew register:

  Device Tree Value	Delay	Pad Skew Register Value
  -----------------------------------------------------
	0   		-840ps		0000
	200 		-720ps		0001
	400 		-600ps		0010
	600 		-480ps		0011
	800 		-360ps		0100
	1000		-240ps		0101
	1200		-120ps		0110
	1400		   0ps		0111
	1600		 120ps		1000
	1800		 240ps		1001
	2000		 360ps		1010
	2200		 480ps		1011
	2400		 600ps		1100
	2600		 720ps		1101
	2800		 840ps		1110
	3000		 960ps		1111

  Optional properties:

    - rxc-skew-ps : Skew control of RXC pad
    - rxdv-skew-ps : Skew control of RX CTL pad
    - txc-skew-ps : Skew control of TXC pad
    - txen-skew-ps : Skew control of TX CTL pad
    - rxd0-skew-ps : Skew control of RX data 0 pad
    - rxd1-skew-ps : Skew control of RX data 1 pad
    - rxd2-skew-ps : Skew control of RX data 2 pad
    - rxd3-skew-ps : Skew control of RX data 3 pad
    - txd0-skew-ps : Skew control of TX data 0 pad
    - txd1-skew-ps : Skew control of TX data 1 pad
    - txd2-skew-ps : Skew control of TX data 2 pad
    - txd3-skew-ps : Skew control of TX data 3 pad

KSZ9031:

  All skew control options are specified in picoseconds. The minimum
  value is 0, and the maximum is property-dependent. The increment
  step is 60ps. The default value is the neutral setting, so setting
  rxc-skew-ps=<0> actually results in -900 picoseconds adjustment.

  The KSZ9031 hardware supports a range of skew values from negative to
  positive, where the specific range is property dependent. All values
  specified in the devicetree are offset by the minimum value so they
  can be represented as positive integers in the devicetree since it's
  difficult to represent a negative number in the devictree.

  The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps.

  Pad Skew Value	Delay (ps)	Devicetree Value
  ------------------------------------------------------
  0_0000		-900ps		0
  0_0001		-840ps		60
  0_0010		-780ps		120
  0_0011		-720ps		180
  0_0100		-660ps		240
  0_0101		-600ps		300
  0_0110		-540ps		360
  0_0111		-480ps		420
  0_1000		-420ps		480
  0_1001		-360ps		540
  0_1010		-300ps		600
  0_1011		-240ps		660
  0_1100		-180ps		720
  0_1101		-120ps		780
  0_1110		-60ps		840
  0_1111		0ps		900
  1_0000		60ps		960
  1_0001		120ps		1020
  1_0010		180ps		1080
  1_0011		240ps		1140
  1_0100		300ps		1200
  1_0101		360ps		1260
  1_0110		420ps		1320
  1_0111		480ps		1380
  1_1000		540ps		1440
  1_1001		600ps		1500
  1_1010		660ps		1560
  1_1011		720ps		1620
  1_1100		780ps		1680
  1_1101		840ps		1740
  1_1110		900ps		1800
  1_1111		960ps		1860

  The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps
  data pads, and the rxdv-skew-ps, txen-skew-ps control pads.

  Pad Skew Value	Delay (ps)	Devicetree Value
  ------------------------------------------------------
  0000			-420ps		0
  0001			-360ps		60
  0010			-300ps		120
  0011			-240ps		180
  0100			-180ps		240
  0101			-120ps		300
  0110			-60ps		360
  0111			0ps		420
  1000			60ps		480
  1001			120ps		540
  1010			180ps		600
  1011			240ps		660
  1100			300ps		720
  1101			360ps		780
  1110			420ps		840
  1111			480ps		900

  Optional properties:

    Maximum value of 1860, default value 900:

      - rxc-skew-ps : Skew control of RX clock pad
      - txc-skew-ps : Skew control of TX clock pad

    Maximum value of 900, default value 420:

      - rxdv-skew-ps : Skew control of RX CTL pad
      - txen-skew-ps : Skew control of TX CTL pad
      - rxd0-skew-ps : Skew control of RX data 0 pad
      - rxd1-skew-ps : Skew control of RX data 1 pad
      - rxd2-skew-ps : Skew control of RX data 2 pad
      - rxd3-skew-ps : Skew control of RX data 3 pad
      - txd0-skew-ps : Skew control of TX data 0 pad
      - txd1-skew-ps : Skew control of TX data 1 pad
      - txd2-skew-ps : Skew control of TX data 2 pad
      - txd3-skew-ps : Skew control of TX data 3 pad

    - micrel,force-master:
        Boolean, force phy to master mode. Only set this option if the phy
        reference clock provided at CLK125_NDO pin is used as MAC reference
        clock because the clock jitter in slave mode is to high (errata#2).
        Attention: The link partner must be configurable as slave otherwise
        no link will be established.

KSZ9131:

  All skew control options are specified in picoseconds. The increment
  step is 100ps. Unlike KSZ9031, the values represent picoseccond delays.
  A negative value can be assigned as rxc-skew-psec = <(-100)>;.

  Optional properties:

    Range of the value -700 to 2400, default value 0:

      - rxc-skew-psec : Skew control of RX clock pad
      - txc-skew-psec : Skew control of TX clock pad

    Range of the value -700 to 800, default value 0:

      - rxdv-skew-psec : Skew control of RX CTL pad
      - txen-skew-psec : Skew control of TX CTL pad
      - rxd0-skew-psec : Skew control of RX data 0 pad
      - rxd1-skew-psec : Skew control of RX data 1 pad
      - rxd2-skew-psec : Skew control of RX data 2 pad
      - rxd3-skew-psec : Skew control of RX data 3 pad
      - txd0-skew-psec : Skew control of TX data 0 pad
      - txd1-skew-psec : Skew control of TX data 1 pad
      - txd2-skew-psec : Skew control of TX data 2 pad
      - txd3-skew-psec : Skew control of TX data 3 pad

Examples:

	/* Attach to an Ethernet device with autodetected PHY */
	&enet {
		rxc-skew-ps = <1800>;
		rxdv-skew-ps = <0>;
		txc-skew-ps = <1800>;
		txen-skew-ps = <0>;
		status = "okay";
	};

	/* Attach to an explicitly-specified PHY */
	mdio {
		phy0: ethernet-phy@0 {
			rxc-skew-ps = <1800>;
			rxdv-skew-ps = <0>;
			txc-skew-ps = <1800>;
			txen-skew-ps = <0>;
			reg = <0>;
		};
	};
	ethernet@70000 {
		phy = <&phy0>;
		phy-mode = "rgmii-id";
	};

References

  Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014.
  http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf

  Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014.
  http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf

Notes:

  Note that a previous version of the Micrel ksz9021rl/rn Data Sheet
  was missing extended register 106 (transmit data pad skews), and
  incorrectly specified the ps per step as 200ps/step instead of
  120ps/step. The latest update to this document reflects the latest
  revision of the Micrel specification even though usage in the kernel
  still reflects that incorrect document.


code:
Micrel PHY properties.

These properties cover the base properties Micrel PHYs.

Optional properties:

 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.

	Configure the LED mode with single value. The list of PHYs and the
	bits that are currently supported:

	KSZ8001: register 0x1e, bits 15..14
	KSZ8041: register 0x1e, bits 15..14
	KSZ8021: register 0x1f, bits 5..4
	KSZ8031: register 0x1f, bits 5..4
	KSZ8051: register 0x1f, bits 5..4
	KSZ8081: register 0x1f, bits 5..4
	KSZ8091: register 0x1f, bits 5..4
	LAN8814: register EP5.0, bit 6

	See the respective PHY datasheet for the mode values.

 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
						bit selects 25 MHz mode

	Setting the RMII Reference Clock Select bit enables 25 MHz rather
	than 50 MHz clock mode.

	Note that this option in only needed for certain PHY revisions with a
	non-standard, inverted function of this configuration bit.
	Specifically, a clock reference ("rmii-ref" below) is always needed to
	actually select a mode.

 - clocks, clock-names: contains clocks according to the common clock bindings.

	supported clocks:
	- KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
	  input clock. Used to determine the XI input clock.

 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode

	Some PHYs, such as the KSZ8041FTL variant, support fiber mode, enabled
	by the FXEN boot strapping pin. It can't be determined from the PHY
	registers whether the PHY is in fiber mode, so this boolean device tree
	property can be used to describe it.

	In fiber mode, auto-negotiation is disabled and the PHY can only work in
	100base-fx (full and half duplex) modes.

 - coma-mode-gpios: If present the given gpio will be deasserted when the
		    PHY is probed.

	Some PHYs have a COMA mode input pin which puts the PHY into
	isolate and power-down mode. On some boards this input is connected
	to a GPIO of the SoC.

	Supported on the LAN8814.


code:
* Microchip ENC28J60

This is a standalone 10 MBit ethernet controller with SPI interface.

For each device connected to a SPI bus, define a child node within
the SPI master node.

Required properties:
- compatible: Should be "microchip,enc28j60"
- reg: Specify the SPI chip select the ENC28J60 is wired to
- interrupts: Specify the interrupt index within the interrupt controller (referred
              to above in interrupt-parent) and interrupt type. The ENC28J60 natively
              generates falling edge interrupts, however, additional board logic
              might invert the signal.
- pinctrl-names: List of assigned state names, see pinctrl binding documentation.
- pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
             see also generic and your platform specific pinctrl binding
             documentation.

Optional properties:
- spi-max-frequency: Maximum frequency of the SPI bus when accessing the ENC28J60.
  According to the ENC28J80 datasheet, the chip allows a maximum of 20 MHz, however,
  board designs may need to limit this value.

The MAC address will be determined using the optional properties
defined in ethernet.txt.

Example (for NXP i.MX28 with pin control stuff for GPIO irq):

        ssp2: ssp@80014000 {
                compatible = "fsl,imx28-spi";
                pinctrl-names = "default";
                pinctrl-0 = <&spi2_pins_b &spi2_sck_cfg>;

                enc28j60: ethernet@0 {
                        compatible = "microchip,enc28j60";
                        pinctrl-names = "default";
                        pinctrl-0 = <&enc28j60_pins>;
                        reg = <0>;
                        interrupt-parent = <&gpio3>;
                        interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
                        spi-max-frequency = <12000000>;
                };
        };

        pinctrl@80018000 {
                enc28j60_pins: enc28j60_pins@0 {
                        reg = <0>;
                        fsl,pinmux-ids = <
                                MX28_PAD_AUART0_RTS__GPIO_3_3    /* Interrupt */
                        >;
                        fsl,drive-strength = <MXS_DRIVE_4mA>;
                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
                        fsl,pull-up = <MXS_PULL_DISABLE>;
                };
        };


code:
Microchip LAN78xx Gigabit Ethernet controller

The LAN78XX devices are usually configured by programming their OTP or with
an external EEPROM, but some platforms (e.g. Raspberry Pi 3 B+) have neither.
The Device Tree properties, if present, override the OTP and EEPROM.

Required properties:
- compatible: Should be one of "usb424,7800", "usb424,7801" or "usb424,7850".

The MAC address will be determined using the optional properties
defined in ethernet.txt.

Optional properties of the embedded PHY:
- microchip,led-modes: a 0..4 element vector, with each element configuring
  the operating mode of an LED. Omitted LEDs are turned off. Allowed values
  are defined in "include/dt-bindings/net/microchip-lan78xx.h".

Example:

/* Based on the configuration for a Raspberry Pi 3 B+ */
&usb {
	usb-port@1 {
		compatible = "usb424,2514";
		reg = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		usb-port@1 {
			compatible = "usb424,2514";
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			ethernet: ethernet@1 {
				compatible = "usb424,7800";
				reg = <1>;
				local-mac-address = [ 00 11 22 33 44 55 ];

				mdio {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					eth_phy: ethernet-phy@1 {
						reg = <1>;
						microchip,led-modes = <
							LAN78XX_LINK_1000_ACTIVITY
							LAN78XX_LINK_10_100_ACTIVITY
						>;
					};
				};
			};
		};
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/microchip,lan95xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: The device tree bindings for the USB Ethernet controllers

maintainers:
  - Oleksij Rempel <o.rempel@pengutronix.de>

description: |
  Device tree properties for hard wired SMSC95xx compatible USB Ethernet
  controller.

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - usb424,9500   # SMSC9500 USB Ethernet Device
          - usb424,9505   # SMSC9505 USB Ethernet Device
          - usb424,9530   # SMSC LAN9530 USB Ethernet Device
          - usb424,9730   # SMSC LAN9730 USB Ethernet Device
          - usb424,9900   # SMSC9500 USB Ethernet Device (SAL10)
          - usb424,9901   # SMSC9505 USB Ethernet Device (SAL10)
          - usb424,9902   # SMSC9500A USB Ethernet Device (SAL10)
          - usb424,9903   # SMSC9505A USB Ethernet Device (SAL10)
          - usb424,9904   # SMSC9512/9514 USB Hub & Ethernet Device (SAL10)
          - usb424,9905   # SMSC9500A USB Ethernet Device (HAL)
          - usb424,9906   # SMSC9505A USB Ethernet Device (HAL)
          - usb424,9907   # SMSC9500 USB Ethernet Device (Alternate ID)
          - usb424,9908   # SMSC9500A USB Ethernet Device (Alternate ID)
          - usb424,9909   # SMSC9512/9514 USB Hub & Ethernet Devic.  ID)
          - usb424,9e00   # SMSC9500A USB Ethernet Device
          - usb424,9e01   # SMSC9505A USB Ethernet Device
          - usb424,9e08   # SMSC LAN89530 USB Ethernet Device
          - usb424,ec00   # SMSC9512/9514 USB Hub & Ethernet Device

  reg:
    maxItems: 1

  local-mac-address: true
  mac-address: true

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    usb {
        #address-cells = <1>;
        #size-cells = <0>;

        ethernet@1 {
            compatible = "usb424,9e00";
            reg = <1>;
            local-mac-address = [00 00 00 00 00 00];
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip Lan966x Ethernet switch controller

maintainers:
  - Horatiu Vultur <horatiu.vultur@microchip.com>

description: |
  The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
  two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
  it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
  2 Quad-SGMII/Quad-USGMII interfaces.

properties:
  $nodename:
    pattern: "^switch@[0-9a-f]+$"

  compatible:
    const: microchip,lan966x-switch

  reg:
    items:
      - description: cpu target
      - description: general control block target

  reg-names:
    items:
      - const: cpu
      - const: gcb

  interrupts:
    minItems: 1
    items:
      - description: register based extraction
      - description: frame dma based extraction
      - description: analyzer interrupt
      - description: ptp interrupt
      - description: ptp external interrupt

  interrupt-names:
    minItems: 1
    items:
      - const: xtr
      - const: fdma
      - const: ana
      - const: ptp
      - const: ptp-ext

  resets:
    items:
      - description: Reset controller used for switch core reset (soft reset)

  reset-names:
    items:
      - const: switch

  ethernet-ports:
    type: object

    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    additionalProperties: false

    patternProperties:
      "^port@[0-9a-f]+$":
        type: object

        $ref: "/schemas/net/ethernet-controller.yaml#"
        unevaluatedProperties: false

        properties:
          '#address-cells':
            const: 1
          '#size-cells':
            const: 0

          reg:
            description:
              Switch port number

          phys:
            description:
              Phandle of a Ethernet SerDes PHY

          phy-mode:
            description:
              This specifies the interface used by the Ethernet SerDes towards
              the PHY or SFP.
            enum:
              - gmii
              - sgmii
              - qsgmii
              - 1000base-x
              - 2500base-x

          phy-handle:
            description:
              Phandle of a Ethernet PHY.

          sfp:
            description:
              Phandle of an SFP.

          managed: true

        required:
          - reg
          - phys
          - phy-mode

        oneOf:
          - required:
              - phy-handle
          - required:
              - sfp
              - managed

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names
  - resets
  - reset-names
  - ethernet-ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    switch: switch@e0000000 {
      compatible = "microchip,lan966x-switch";
      reg =  <0xe0000000 0x0100000>,
             <0xe2000000 0x0800000>;
      reg-names = "cpu", "gcb";
      interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "xtr";
      resets = <&switch_reset 0>;
      reset-names = "switch";
      ethernet-ports {
        #address-cells = <1>;
        #size-cells = <0>;

        port0: port@0 {
          reg = <0>;
          phy-handle = <&phy0>;
          phys = <&serdes 0 0>;
          phy-mode = "gmii";
        };

        port1: port@1 {
          reg = <1>;
          sfp = <&sfp_eth1>;
          managed = "in-band-status";
          phys = <&serdes 2 4>;
          phy-mode = "sgmii";
        };
      };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip Sparx5 Ethernet switch controller

maintainers:
  - Steen Hegelund <steen.hegelund@microchip.com>
  - Lars Povlsen <lars.povlsen@microchip.com>

description: |
  The SparX-5 Enterprise Ethernet switch family provides a rich set of
  Enterprise switching features such as advanced TCAM-based VLAN and
  QoS processing enabling delivery of differentiated services, and
  security through TCAM-based frame processing using versatile content
  aware processor (VCAP).

  IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
  with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
  IPv6 (S,G) multicast groups.

  L3 security features include source guard and reverse path
  forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
  IP tunnels (IP over GRE/IP).

  The SparX-5 switch family targets managed Layer 2 and Layer 3
  equipment in SMB, SME, and Enterprise where high port count
  1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.

properties:
  $nodename:
    pattern: "^switch@[0-9a-f]+$"

  compatible:
    const: microchip,sparx5-switch

  reg:
    items:
      - description: cpu target
      - description: devices target
      - description: general control block target

  reg-names:
    items:
      - const: cpu
      - const: devices
      - const: gcb

  interrupts:
    minItems: 1
    items:
      - description: register based extraction
      - description: frame dma based extraction
      - description: ptp interrupt

  interrupt-names:
    minItems: 1
    items:
      - const: xtr
      - const: fdma
      - const: ptp

  resets:
    items:
      - description: Reset controller used for switch core reset (soft reset)

  reset-names:
    items:
      - const: switch

  mac-address: true

  ethernet-ports:
    type: object
    additionalProperties: false

    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    patternProperties:
      "^port@[0-9a-f]+$":
        $ref: /schemas/net/ethernet-controller.yaml#
        unevaluatedProperties: false

        properties:
          reg:
            description: Switch port number

          phys:
            maxItems: 1
            description:
              phandle of a Ethernet SerDes PHY.  This defines which SerDes
              instance will handle the Ethernet traffic.

          microchip,bandwidth:
            description: Specifies bandwidth in Mbit/s allocated to the port.
            $ref: "/schemas/types.yaml#/definitions/uint32"
            maximum: 25000

          microchip,sd-sgpio:
            description:
              Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs
              This is optional, and only needed if the default used index is
              is not correct.
            $ref: "/schemas/types.yaml#/definitions/uint32"
            minimum: 0
            maximum: 383

        required:
          - reg
          - phys
          - phy-mode
          - microchip,bandwidth

        oneOf:
          - required:
              - phy-handle
          - required:
              - sfp
              - managed

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names
  - ethernet-ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    switch: switch@600000000 {
      compatible = "microchip,sparx5-switch";
      reg =  <0 0x401000>,
             <0x10004000 0x7fc000>,
             <0x11010000 0xaf0000>;
      reg-names = "cpu", "devices", "gcb";
      interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "xtr";
      resets = <&reset 0>;
      reset-names = "switch";
      ethernet-ports {
        #address-cells = <1>;
        #size-cells = <0>;

        port0: port@0 {
          reg = <0>;
          microchip,bandwidth = <1000>;
          phys = <&serdes 13>;
          phy-handle = <&phy0>;
          phy-mode = "qsgmii";
        };
        /* ... */
        /* Then the 25G interfaces */
        port60: port@60 {
          reg = <60>;
          microchip,bandwidth = <25000>;
          phys = <&serdes 29>;
          phy-mode = "10gbase-r";
          sfp = <&sfp_eth60>;
          managed = "in-band-status";
          microchip,sd-sgpio = <365>;
        };
        port61: port@61 {
          reg = <61>;
          microchip,bandwidth = <25000>;
          phys = <&serdes 30>;
          phy-mode = "10gbase-r";
          sfp = <&sfp_eth61>;
          managed = "in-band-status";
          microchip,sd-sgpio = <369>;
        };
        port62: port@62 {
          reg = <62>;
          microchip,bandwidth = <25000>;
          phys = <&serdes 31>;
          phy-mode = "10gbase-r";
          sfp = <&sfp_eth62>;
          managed = "in-band-status";
          microchip,sd-sgpio = <373>;
        };
        port63: port@63 {
          reg = <63>;
          microchip,bandwidth = <25000>;
          phys = <&serdes 32>;
          phy-mode = "10gbase-r";
          sfp = <&sfp_eth63>;
          managed = "in-band-status";
          microchip,sd-sgpio = <377>;
        };
        /* Finally the Management interface */
        port64: port@64 {
          reg = <64>;
          microchip,bandwidth = <1000>;
          phys = <&serdes 0>;
          phy-handle = <&phy64>;
          phy-mode = "sgmii";
          mac-address = [ 00 00 00 01 02 03 ];
        };
      };
    };

...
#  vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mscc,miim.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microsemi MII Management Controller (MIIM)

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

allOf:
  - $ref: "mdio.yaml#"

properties:
  compatible:
    enum:
      - mscc,ocelot-miim
      - microchip,lan966x-miim

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  reg:
    items:
      - description: base address
      - description: associated reset register for internal PHYs
    minItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-frequency: true

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"

unevaluatedProperties: false

examples:
  - |
    mdio@107009c {
      compatible = "mscc,ocelot-miim";
      reg = <0x107009c 0x36>, <0x10700f0 0x8>;
      interrupts = <14>;
      #address-cells = <1>;
      #size-cells = <0>;

      phy0: ethernet-phy@0 {
        reg = <0>;
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mscc,vsc7514-switch.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip VSC7514 Ethernet switch controller

maintainers:
  - Vladimir Oltean <vladimir.oltean@nxp.com>
  - Claudiu Manoil <claudiu.manoil@nxp.com>
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

description: |
  Bindings for the Microchip VSC7514 switch driver

  The VSC7514 switch driver handles up to 11 ports and can inject/extract
  packets using CPU. Additionally, PTP is supported as well as FDMA for faster
  packet extraction/injection.

properties:
  $nodename:
    pattern: "^switch@[0-9a-f]+$"

  compatible:
    const: mscc,vsc7514-switch

  reg:
    items:
      - description: system target
      - description: rewriter target
      - description: qs target
      - description: PTP target
      - description: Port0 target
      - description: Port1 target
      - description: Port2 target
      - description: Port3 target
      - description: Port4 target
      - description: Port5 target
      - description: Port6 target
      - description: Port7 target
      - description: Port8 target
      - description: Port9 target
      - description: Port10 target
      - description: QSystem target
      - description: Analyzer target
      - description: S0 target
      - description: S1 target
      - description: S2 target
      - description: fdma target

  reg-names:
    items:
      - const: sys
      - const: rew
      - const: qs
      - const: ptp
      - const: port0
      - const: port1
      - const: port2
      - const: port3
      - const: port4
      - const: port5
      - const: port6
      - const: port7
      - const: port8
      - const: port9
      - const: port10
      - const: qsys
      - const: ana
      - const: s0
      - const: s1
      - const: s2
      - const: fdma

  interrupts:
    minItems: 1
    items:
      - description: PTP ready
      - description: register based extraction
      - description: frame dma based extraction

  interrupt-names:
    minItems: 1
    items:
      - const: ptp_rdy
      - const: xtr
      - const: fdma

  ethernet-ports:
    type: object

    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    additionalProperties: false

    patternProperties:
      "^port@[0-9a-f]+$":
        type: object
        description: Ethernet ports handled by the switch

        $ref: ethernet-controller.yaml#

        unevaluatedProperties: false

        properties:
          reg:
            description: Switch port number

          phy-handle: true

          phy-mode: true

          fixed-link: true

          mac-address: true

        required:
          - reg
          - phy-mode

        oneOf:
          - required:
              - phy-handle
          - required:
              - fixed-link

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names
  - ethernet-ports

additionalProperties: false

examples:
  - |
    switch@1010000 {
      compatible = "mscc,vsc7514-switch";
      reg = <0x1010000 0x10000>,
            <0x1030000 0x10000>,
            <0x1080000 0x100>,
            <0x10e0000 0x10000>,
            <0x11e0000 0x100>,
            <0x11f0000 0x100>,
            <0x1200000 0x100>,
            <0x1210000 0x100>,
            <0x1220000 0x100>,
            <0x1230000 0x100>,
            <0x1240000 0x100>,
            <0x1250000 0x100>,
            <0x1260000 0x100>,
            <0x1270000 0x100>,
            <0x1280000 0x100>,
            <0x1800000 0x80000>,
            <0x1880000 0x10000>,
            <0x1040000 0x10000>,
            <0x1050000 0x10000>,
            <0x1060000 0x10000>,
            <0x1a0 0x1c4>;
      reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
            "port2", "port3", "port4", "port5", "port6",
            "port7", "port8", "port9", "port10", "qsys",
            "ana", "s0", "s1", "s2", "fdma";
      interrupts = <18 21 16>;
      interrupt-names = "ptp_rdy", "xtr", "fdma";

      ethernet-ports {
        #address-cells = <1>;
        #size-cells = <0>;

        port0: port@0 {
          reg = <0>;
          phy-handle = <&phy0>;
          phy-mode = "internal";
        };
        port1: port@1 {
          reg = <1>;
          phy-handle = <&phy1>;
          phy-mode = "internal";
        };
      };
    };

...


code:
* Microsemi - vsc8531 Giga bit ethernet phy

Optional properties:
- vsc8531,vddmac	: The vddmac in mV. Allowed values is listed
			  in the first row of Table 1 (below).
			  This property is only used in combination
			  with the 'edge-slowdown' property.
			  Default value is 3300.
- vsc8531,edge-slowdown	: % the edge should be slowed down relative to
			  the fastest possible edge time.
			  Edge rate sets the drive strength of the MAC
			  interface output signals.  Changing the
			  drive strength will affect the edge rate of
			  the output signal.  The goal of this setting
			  is to help reduce electrical emission (EMI)
			  by being able to reprogram drive strength
			  and in effect slow down the edge rate if
			  desired.
			  To adjust the edge-slowdown, the 'vddmac'
			  must be specified. Table 1 lists the
			  supported edge-slowdown values for a given
			  'vddmac'.
			  Default value is 0%.
			  Ref: Table:1 - Edge rate change (below).
- vsc8531,led-[N]-mode	: LED mode. Specify how the LED[N] should behave.
			  N depends on the number of LEDs supported by a
			  PHY.
			  Allowed values are defined in
			  "include/dt-bindings/net/mscc-phy-vsc8531.h".
			  Default values are VSC8531_LINK_1000_ACTIVITY (1),
			  VSC8531_LINK_100_ACTIVITY (2),
			  VSC8531_LINK_ACTIVITY (0) and
			  VSC8531_DUPLEX_COLLISION (8).
- load-save-gpios	: GPIO used for the load/save operation of the PTP
			  hardware clock (PHC).

Table: 1 - Edge rate change
----------------------------------------------------------------|
| 		Edge Rate Change (VDDMAC)			|
|								|
| 3300 mV	2500 mV		1800 mV		1500 mV		|
|---------------------------------------------------------------|
| 0%		0%		0%		0%		|
| (Fastest)			(recommended)	(recommended)	|
|---------------------------------------------------------------|
| 2%		3%		5%		6%		|
|---------------------------------------------------------------|
| 4%		6%		9%		14%		|
|---------------------------------------------------------------|
| 7%		10%		16%		21%		|
|(recommended)	(recommended)					|
|---------------------------------------------------------------|
| 10%		14%		23%		29%		|
|---------------------------------------------------------------|
| 17%		23%		35%		42%		|
|---------------------------------------------------------------|
| 29%		37%		52%		58%		|
|---------------------------------------------------------------|
| 53%		63%		76%		77%		|
| (slowest)							|
|---------------------------------------------------------------|

Example:

        vsc8531_0: ethernet-phy@0 {
                compatible = "ethernet-phy-id0007.0570";
                vsc8531,vddmac		= <3300>;
                vsc8531,edge-slowdown	= <7>;
                vsc8531,led-0-mode	= <VSC8531_LINK_1000_ACTIVITY>;
                vsc8531,led-1-mode	= <VSC8531_LINK_100_ACTIVITY>;
		load-save-gpios		= <&gpio 10 GPIO_ACTIVE_HIGH>;
        };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/marvell,nci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell International Ltd. NCI NFC controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - marvell,nfc-i2c
      - marvell,nfc-spi
      - marvell,nfc-uart

  hci-muxed:
    type: boolean
    description: |
      Specifies that the chip is muxing NCI over HCI frames

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

  reset-n-io:
    $ref: "/schemas/types.yaml#/definitions/phandle-array"
    maxItems: 1
    description: |
      Output GPIO pin used to reset the chip (active low)

  i2c-int-falling:
    type: boolean
    description: |
      For I2C type of connection. Specifies that the chip read event shall be
      trigged on falling edge.

  i2c-int-rising:
    type: boolean
    description: |
      For I2C type of connection.  Specifies that the chip read event shall be
      trigged on rising edge.

  break-control:
    type: boolean
    description: |
      For UART type of connection. Specifies that the chip needs specific break
      management.

  flow-control:
    type: boolean
    description: |
      For UART type of connection. Specifies that the chip is using RTS/CTS.

  spi-cpha: true
  spi-cpol: true

required:
  - compatible

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: marvell,nfc-i2c
    then:
      properties:
        break-control: false
        flow-control: false
        spi-cpha: false
        spi-cpol: false
        spi-max-frequency: false
      required:
        - reg

  - if:
      properties:
        compatible:
          contains:
            const: marvell,nfc-spi
    then:
      $ref: /schemas/spi/spi-peripheral-props.yaml#
      properties:
        break-control: false
        flow-control: false
        i2c-int-falling: false
        i2c-int-rising: false
      required:
        - reg

  - if:
      properties:
        compatible:
          contains:
            const: marvell,nfc-uart
    then:
      properties:
        i2c-int-falling: false
        i2c-int-rising: false
        interrupts: false
        spi-cpha: false
        spi-cpol: false
        spi-max-frequency: false
        reg: false

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        nfc@8 {
            compatible = "marvell,nfc-i2c";
            reg = <0x8>;

            interrupt-parent = <&gpio3>;
            interrupts = <21 IRQ_TYPE_EDGE_RISING>;

            i2c-int-rising;

            reset-n-io = <&gpio3 19 GPIO_ACTIVE_LOW>;
        };
    };

  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        nfc@0 {
            compatible = "marvell,nfc-spi";
            reg = <0>;

            spi-max-frequency = <3000000>;
            spi-cpha;
            spi-cpol;

            interrupt-parent = <&gpio1>;
            interrupts = <17 IRQ_TYPE_EDGE_RISING>;

            reset-n-io = <&gpio3 19 GPIO_ACTIVE_LOW>;
        };
    };

  - |
    #include <dt-bindings/gpio/gpio.h>

    uart {
        nfc {
            compatible = "marvell,nfc-uart";

            reset-n-io = <&gpio3 16 GPIO_ACTIVE_LOW>;

            hci-muxed;
            flow-control;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/nxp,nci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP Semiconductors NCI NFC controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    oneOf:
      - const: nxp,nxp-nci-i2c
      - items:
          - enum:
              - nxp,nq310
              - nxp,pn547
          - const: nxp,nxp-nci-i2c

  enable-gpios:
    description: Output GPIO pin used for enabling/disabling the controller

  firmware-gpios:
    description: Output GPIO pin used to enter firmware download mode

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - enable-gpios
  - interrupts
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        nfc@29 {
            compatible = "nxp,nxp-nci-i2c";

            reg = <0x29>;

            interrupt-parent = <&gpio1>;
            interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;

            enable-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
            firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/nxp,pn532.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP Semiconductors PN532 NFC controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    oneOf:
      - const: nxp,pn532
      - description: Deprecated bindings
        enum:
          - nxp,pn532-i2c
          - nxp,pn533-i2c
        deprecated: true

  interrupts:
    description: Required if connected via I2C
    maxItems: 1

  reg:
    description: Required if connected via I2C
    maxItems: 1

required:
  - compatible

dependencies:
  interrupts: [ 'reg' ]

additionalProperties: false

examples:
  # PN532 on I2C bus
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        nfc@24 {
            compatible = "nxp,pn532";

            reg = <0x24>;

            interrupt-parent = <&gpio1>;
            interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
        };
    };

  # PN532 connected via UART
  - |
    serial@49042000 {
        reg = <0x49042000 0x400>;

        nfc {
            compatible = "nxp,pn532";
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/nxp,pn544.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP Semiconductors PN544 NFC Controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    const: nxp,pn544-i2c

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  enable-gpios:
    description: Output GPIO pin used for enabling/disabling the PN544
    maxItems: 1

  firmware-gpios:
    description: Output GPIO pin used to enter firmware download mode
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - enable-gpios
  - firmware-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        nfc@28 {
            compatible = "nxp,pn544-i2c";
            reg = <0x28>;

            interrupt-parent = <&gpio1>;
            interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;

            enable-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
            firmware-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nfc/samsung,s3fwrn5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S3FWRN5 NCI NFC Controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

properties:
  compatible:
    enum:
      - samsung,s3fwrn5-i2c
      - samsung,s3fwrn82

  en-gpios:
    maxItems: 1
    description:
      Output GPIO pin used for enabling/disabling the chip

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  wake-gpios:
    maxItems: 1
    description:
      Output GPIO pin used to enter firmware mode and sleep/wakeup control

  s3fwrn5,en-gpios:
    maxItems: 1
    deprecated: true
    description:
      Use en-gpios

  s3fwrn5,fw-gpios:
    maxItems: 1
    deprecated: true
    description:
      Use wake-gpios

additionalProperties: false

required:
  - compatible
  - en-gpios
  - wake-gpios

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: samsung,s3fwrn5-i2c
    then:
      required:
        - interrupts
        - reg

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c4 {
        #address-cells = <1>;
        #size-cells = <0>;

        s3fwrn5@27 {
            compatible = "samsung,s3fwrn5-i2c";
            reg = <0x27>;

            interrupt-parent = <&gpa1>;
            interrupts = <3 IRQ_TYPE_EDGE_RISING>;

            en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>;
            wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>;

            clocks = <&rpmcc 20>;
        };
    };
  # UART example on Raspberry Pi
  - |
    uart0 {
        nfc {
            compatible = "samsung,s3fwrn82";

            en-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
            wake-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;

        };
    };