code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/renesas,tpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas H8/300 Timer Pulse Unit

maintainers:
  - Yoshinori Sato <ysato@users.sourceforge.jp>

description:
  The TPU is a 16bit timer/counter with configurable clock inputs and
  programmable compare match.
  This implementation supports only cascade mode.

select:
  properties:
    compatible:
      contains:
        const: renesas,tpu
    '#pwm-cells': false
  required:
    - compatible

properties:
  compatible:
    const: renesas,tpu

  reg:
    items:
      - description: First channel
      - description: Second channel

  clocks:
    maxItems: 1

  clock-names:
    const: fck

required:
  - compatible
  - reg
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    tpu: tpu@ffffe0 {
            compatible = "renesas,tpu";
            reg = <0xffffe0 16>, <0xfffff0 12>;
            clocks = <&pclk>;
            clock-names = "fck";
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/rockchip,rk-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip Timer

maintainers:
  - Daniel Lezcano <daniel.lezcano@linaro.org>

properties:
  compatible:
    oneOf:
      - const: rockchip,rk3288-timer
      - const: rockchip,rk3399-timer
      - items:
          - enum:
              - rockchip,rv1108-timer
              - rockchip,rk3036-timer
              - rockchip,rk3128-timer
              - rockchip,rk3188-timer
              - rockchip,rk3228-timer
              - rockchip,rk3229-timer
              - rockchip,rk3288-timer
              - rockchip,rk3368-timer
              - rockchip,px30-timer
          - const: rockchip,rk3288-timer
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 2

  clock-names:
    items:
      - const: pclk
      - const: timer

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/rk3288-cru.h>

    timer: timer@ff810000 {
        compatible = "rockchip,rk3288-timer";
        reg = <0xff810000 0x20>;
        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cru PCLK_TIMER>, <&xin24m>;
        clock-names = "pclk", "timer";
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC Multi Core Timer (MCT)

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description: |+
  The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
  global timer and CPU local timers. The global timer is a 64-bit free running
  up-counter and can generate 4 interrupts when the counter reaches one of the
  four preset counter values. The CPU local timers are 32-bit free running
  down-counters and generate an interrupt when the counter expires. There is
  one CPU local timer instantiated in MCT for every CPU in the system.

properties:
  compatible:
    oneOf:
      - enum:
          - samsung,exynos4210-mct
          - samsung,exynos4412-mct
      - items:
          - enum:
              - axis,artpec8-mct
              - samsung,exynos3250-mct
              - samsung,exynos5250-mct
              - samsung,exynos5260-mct
              - samsung,exynos5420-mct
              - samsung,exynos5433-mct
              - samsung,exynos850-mct
              - tesla,fsd-mct
          - const: samsung,exynos4210-mct

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: fin_pll
      - const: mct

  reg:
    maxItems: 1

  samsung,frc-shared:
    type: boolean
    description: |
      Indicates that the hardware requires that this processor share the
      free-running counter with a different (main) processor.

  samsung,local-timers:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 16
    description: |
      List of indices of local timers usable from this processor.

  interrupts:
    description: |
      Interrupts should be put in specific order. This is, the local timer
      interrupts should be specified after the four global timer interrupts
      have been specified:
      0: Global Timer Interrupt 0
      1: Global Timer Interrupt 1
      2: Global Timer Interrupt 2
      3: Global Timer Interrupt 3
      4: Local Timer Interrupt 0
      5: Local Timer Interrupt 1
      6: ..
      7: ..
      i: Local Timer Interrupt n
      For MCT block that uses a per-processor interrupt for local timers, such
      as ones compatible with "samsung,exynos4412-mct", only one local timer
      interrupt might be specified, meaning that all local timers use the same
      per processor interrupt.
    minItems: 5               # 4 Global + 1 local
    maxItems: 20              # 4 Global + 16 local

required:
  - compatible
  - clock-names
  - clocks
  - interrupts
  - reg

allOf:
  - if:
      not:
        properties:
          compatible:
            contains:
              enum:
                - axis,artpec8-mct
    then:
      properties:
        samsung,local-timers: false
        samsung,frc-shared: false
  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos3250-mct
    then:
      properties:
        interrupts:
          minItems: 8
          maxItems: 8

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynos5250-mct
    then:
      properties:
        interrupts:
          minItems: 6
          maxItems: 6

  - if:
      properties:
        compatible:
          contains:
            enum:
              - axis,artpec8-mct
              - samsung,exynos5260-mct
              - samsung,exynos5420-mct
              - samsung,exynos5433-mct
              - samsung,exynos850-mct
    then:
      properties:
        interrupts:
          minItems: 12
          maxItems: 12

  - if:
      properties:
        compatible:
          contains:
            enum:
              - tesla,fsd-mct
    then:
      properties:
        interrupts:
          minItems: 16
          maxItems: 16

additionalProperties: false

examples:
  - |
    // In this example, the IP contains two local timers, using separate
    // interrupts, so two local timer interrupts have been specified,
    // in addition to four global timer interrupts.
    #include <dt-bindings/clock/exynos4.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    timer@10050000 {
        compatible = "samsung,exynos4210-mct";
        reg = <0x10050000 0x800>;
        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
        clock-names = "fin_pll", "mct";

        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
    };

  - |
    // In this example, the timer interrupts are connected to two separate
    // interrupt controllers. Hence, an interrupts-extended is needed.
    #include <dt-bindings/clock/exynos4.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    timer@101c0000 {
        compatible = "samsung,exynos4210-mct";
        reg = <0x101C0000 0x800>;
        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
        clock-names = "fin_pll", "mct";

        interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
                              <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
                              <&combiner 12 6>,
                              <&combiner 12 7>,
                              <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
                              <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
    };

  - |
    // In this example, the IP contains four local timers, but using
    // a per-processor interrupt to handle them. Only one first local
    // interrupt is specified.
    #include <dt-bindings/clock/exynos4.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    timer@10050000 {
        compatible = "samsung,exynos4412-mct";
        reg = <0x10050000 0x800>;
        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
        clock-names = "fin_pll", "mct";

        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
    };

  - |
    // In this example, the IP contains four local timers, but using
    // a per-processor interrupt to handle them. All the local timer
    // interrupts are specified.
    #include <dt-bindings/clock/exynos4.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    timer@10050000 {
        compatible = "samsung,exynos4412-mct";
        reg = <0x10050000 0x800>;
        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
        clock-names = "fin_pll", "mct";

        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive Core Local Interruptor

maintainers:
  - Palmer Dabbelt <palmer@dabbelt.com>
  - Anup Patel <anup.patel@wdc.com>

description:
  SiFive (and other RISC-V) SOCs include an implementation of the SiFive
  Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
  interrupts. It directly connects to the timer and inter-processor interrupt
  lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
  interrupt controller is the parent interrupt controller for CLINT device.
  The clock frequency of CLINT is specified via "timebase-frequency" DT
  property of "/cpus" DT node. The "timebase-frequency" DT property is
  described in Documentation/devicetree/bindings/riscv/cpus.yaml

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - sifive,fu540-c000-clint
              - starfive,jh7100-clint
              - canaan,k210-clint
          - const: sifive,clint0
      - items:
          - const: sifive,clint0
          - const: riscv,clint0
        deprecated: true
        description: For the QEMU virt machine only

    description:
      Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".
      Supported compatible strings are -
      "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
      onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive
      CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and
      "sifive,clint0" for the SiFive CLINT v0 IP block with no chip
      integration tweaks.
      Please refer to sifive-blocks-ip-versioning.txt for details

  reg:
    maxItems: 1

  interrupts-extended:
    minItems: 1
    maxItems: 4095

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts-extended

examples:
  - |
    timer@2000000 {
      compatible = "sifive,fu540-c000-clint", "sifive,clint0";
      interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
                            <&cpu2intc 3>, <&cpu2intc 7>,
                            <&cpu3intc 3>, <&cpu3intc 7>,
                            <&cpu4intc 3>, <&cpu4intc 7>;
       reg = <0x2000000 0x10000>;
    };
...


code:
Synopsys ARC Local Timer with Interrupt Capabilities
- Found on all ARC CPUs (ARC700/ARCHS)
- Can be optionally programmed to interrupt on Limit
- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
  TIMER0 used as clockevent provider (true for all ARC cores)
  TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS)

Required properties:

- compatible : should be "snps,arc-timer"
- interrupts : single Interrupt going into parent intc
	       (16 for ARCHS cores, 3 for ARC700 cores)
- clocks     : phandle to the source clock

Example:

	timer0 {
		compatible = "snps,arc-timer";
		interrupts = <3>;
		interrupt-parent = <&core_intc>;
		clocks = <&core_clk>;
	};

	timer1 {
		compatible = "snps,arc-timer";
		clocks = <&core_clk>;
	};


code:
Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs
- clocksource provider for SMP SoC

Required properties:

- compatible : should be "snps,archs-gfrc"
- clocks     : phandle to the source clock

Example:

	gfrc {
		compatible = "snps,archs-gfrc";
		clocks = <&core_clk>;
	};


code:
Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
- clocksource provider for UP SoC

Required properties:

- compatible : should be "snps,archs-rtc"
- clocks     : phandle to the source clock

Example:

	rtc {
		compatible = "snps,arc-rtc";
		clocks = <&core_clk>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare APB Timer

maintainers:
  - Daniel Lezcano <daniel.lezcano@linaro.org>

properties:
  compatible:
    oneOf:
      - const: snps,dw-apb-timer
      - enum:
          - snps,dw-apb-timer-sp
          - snps,dw-apb-timer-osc
        deprecated: true

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  resets:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: Timer ticks reference clock source
      - description: APB interface clock source

  clock-names:
    minItems: 1
    items:
      - const: timer
      - const: pclk

  clock-frequency: true

additionalProperties: false

required:
  - compatible
  - reg
  - interrupts

oneOf:
  - required:
      - clocks
      - clock-names
  - required:
      - clock-frequency
  - required:
      - clock-freq

examples:
  - |
    timer@ffe00000 {
      compatible = "snps,dw-apb-timer";
      interrupts = <0 170 4>;
      reg = <0xffe00000 0x1000>;
      clocks = <&timer_clk>, <&timer_pclk>;
      clock-names = "timer", "pclk";
    };
  - |
    timer@ffe00000 {
      compatible = "snps,dw-apb-timer";
      interrupts = <0 170 4>;
      reg = <0xffe00000 0x1000>;
      clocks = <&timer_clk>;
      clock-names = "timer";
    };
  - |
    timer@ffe00000 {
      compatible = "snps,dw-apb-timer";
      interrupts = <0 170 4>;
      reg = <0xffe00000 0x1000>;
      clock-frequency = <25000000>;
    };
...


code:
Milbeaut SoCs Timer Controller

Required properties:

- compatible : should be "socionext,milbeaut-timer".
- reg : Specifies base physical address and size of the registers.
- interrupts : The interrupt of the first timer.
- clocks: phandle to the input clk.

Example:

timer {
	compatible = "socionext,milbeaut-timer";
	reg = <0x1e000050 0x20>
	interrupts = <0 91 4>;
	clocks = <&clk 4>;
};


code:
Spreadtrum timers

The Spreadtrum SC9860 platform provides 3 general-purpose timers.
These timers can support 32bit or 64bit counter, as well as supporting
period mode or one-shot mode, and they are can be wakeup source
during deep sleep.

Required properties:
- compatible: should be "sprd,sc9860-timer" for SC9860 platform.
- reg: The register address of the timer device.
- interrupts: Should contain the interrupt for the timer device.
- clocks: The phandle to the source clock (usually a 32.768 KHz fixed clock).

Example:
	timer@40050000 {
		compatible = "sprd,sc9860-timer";
		reg = <0 0x40050000 0 0x20>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&ext_32k>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2022 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/timer/st,nomadik-mtu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: ST Microelectronics Nomadik Multi-Timer Unit MTU Timer

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: This timer is found in the ST Microelectronics Nomadik
  SoCs STn8800, STn8810 and STn8815 as well as in ST-Ericsson DB8500.

properties:
  compatible:
    items:
      - const: st,nomadik-mtu

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    description: The first clock named TIMCLK clocks the actual timers and
      the second clock clocks the digital interface to the interconnect.
    maxItems: 2

  clock-names:
    items:
      - const: timclk
      - const: apb_pclk

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/mfd/dbx500-prcmu.h>
    timer@a03c6000 {
      compatible = "st,nomadik-mtu";
      reg = <0xa03c6000 0x1000>;
      interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
      clock-names = "timclk", "apb_pclk";
    };


code:
* SPEAr ARM Timer

** Timer node required properties:

- compatible : Should be:
	"st,spear-timer"
- reg: Address range of the timer registers
- interrupt: Should contain the timer interrupt number

Example:

	timer@f0000000 {
		compatible = "st,spear-timer";
		reg = <0xf0000000 0x400>;
		interrupts = <2>;
	};


code:
STMicroelectronics Low Power Controller (LPC) - Clocksource
===========================================================

LPC currently supports Watchdog OR Real Time Clock OR Clocksource
functionality.

[See: ../watchdog/st_lpc_wdt.txt for Watchdog options]
[See: ../rtc/rtc-st-lpc.txt for RTC options]

Required properties

- compatible   : Must be: "st,stih407-lpc"
- reg          : LPC registers base address + size
- interrupts   : LPC interrupt line number and associated flags
- clocks       : Clock used by LPC device (See: ../clock/clock-bindings.txt)
- st,lpc-mode  : The LPC can run either one of three modes:
                  ST_LPC_MODE_RTC    [0]
                  ST_LPC_MODE_WDT    [1]
                  ST_LPC_MODE_CLKSRC [2]
		 One (and only one) mode must be selected.

Example:
       lpc@fde05000 {
               compatible      = "st,stih407-lpc";
               reg             = <0xfde05000 0x1000>;
               clocks          = <&clk_s_d3_flexgen CLK_LPC_0>;
               st,lpc-mode     = <ST_LPC_MODE_CLKSRC>;
       };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/st,stm32-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 general-purpose 16 and 32 bits timers bindings

maintainers:
  - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
  - Patrice Chotard <patrice.chotard@foss.st.com>

properties:
  compatible:
    const: st,stm32-timer

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    timer: timer@40000c00 {
        compatible = "st,stm32-timer";
        reg = <0x40000c00 0x400>;
        interrupts = <50>;
        clocks = <&clk_pmtr1>;
    };

...


code:
* Device tree bindings for Texas Instruments DaVinci timer

This document provides bindings for the 64-bit timer in the DaVinci
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or independently
(unchained mode) of each other.

The timer is a free running up-counter and can generate interrupts when the
counter reaches preset counter values.

Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
watchdog timers.

Required properties:

- compatible : should be "ti,da830-timer".
- reg : specifies base physical address and count of the registers.
- interrupts : interrupts generated by the timer.
- interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1",
		   "cmpint2", "cmpint3", "cmpint4", "cmpint5", "cmpint6",
		   "cmpint7" ("cmpintX" may be omitted if not present in the
		   hardware).
- clocks : the clock feeding the timer clock.

Example:

	clocksource: timer@20000 {
		compatible = "ti,da830-timer";
		reg = <0x20000 0x1000>;
		interrupts = <21>, <22>, <74>, <75>, <76>, <77>, <78>, <79>,
			     <80>, <81>;
		interrupt-names = "tint12", "tint34", "cmpint0", "cmpint1",
				  "cmpint2", "cmpint3", "cmpint4", "cmpint5",
				  "cmpint6", "cmpint7";
		clocks = <&pll0_auxclk>;
	};


code:
* Device tree bindings for Texas instruments Keystone timer

This document provides bindings for the 64-bit timer in the KeyStone
architecture devices. The timer can be configured as a general-purpose 64-bit
timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
timers, each half can operate in conjunction (chain mode) or independently
(unchained mode) of each other.

It is global timer is a free running up-counter and can generate interrupt
when the counter reaches preset counter values.

Documentation:
https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf

Required properties:

- compatible : should be "ti,keystone-timer".
- reg : specifies base physical address and count of the registers.
- interrupts : interrupt generated by the timer.
- clocks : the clock feeding the timer clock.

Example:

timer@22f0000 {
	compatible = "ti,keystone-timer";
	reg = <0x022f0000 0x80>;
	interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
	clocks = <&clktimer15>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI dual-mode timer

maintainers:
  - Tony Lindgren <tony@atomide.com>

description: |
  The TI dual-mode timer is a general purpose timer with PWM capabilities.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - ti,am335x-timer
              - ti,am335x-timer-1ms
              - ti,am654-timer
              - ti,dm814-timer
              - ti,dm816-timer
              - ti,omap2420-timer
              - ti,omap3430-timer
              - ti,omap4430-timer
              - ti,omap5430-timer
      - items:
          - const: ti,am4372-timer
          - const: ti,am335x-timer
      - items:
          - const: ti,am4372-timer-1ms
          - const: ti,am335x-timer-1ms

  reg:
    items:
      - description: IO address
      - description: L3 to L4 mapping for omap4/5 L4 ABE
    minItems: 1

  clocks:
    items:
      - description: Functional clock
      - description: System clock for omap4/5 and dra7
    minItems: 1

  clock-names:
    items:
      - const: fck
      - const: timer_sys_ck
    minItems: 1

  power-domains:
    description:
      Power domain if available
    maxItems: 1

  interrupts:
    description:
      Interrupt if available. The timer PWM features may be usable
      in a limited way even without interrupts.
    maxItems: 1

  ti,timer-alwon:
    description:
      Timer is always enabled when the SoC is powered. Note that some SoCs like
      am335x can suspend to PM coprocessor RTC only mode and in that case the
      SoC power is cut including timers.
    type: boolean

  ti,timer-dsp:
    description:
      Timer is routable to the DSP in addition to the operating system.
    type: boolean

  ti,timer-pwm:
    description:
      Timer has been wired for PWM capability.
    type: boolean

  ti,timer-secure:
    description:
      Timer access has been limited to secure mode only.
    type: boolean

  ti,hwmods:
    description:
      Name of the HWMOD associated with timer. This is for legacy
      omap2/3 platforms only.
    $ref: /schemas/types.yaml#/definitions/string
    deprecated: true

required:
  - compatible
  - reg

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: ti,am654-timer
    then:
      required:
        - power-domains
    else:
      required:
        - interrupts

  - if:
      not:
        properties:
          compatible:
            contains:
              enum:
                - ti,omap3430-timer
                - ti,omap4430-timer
                - ti,omap5430-timer
    then:
      properties:
        reg:
          maxItems: 1
        clocks:
          maxItems: 1
        clock-names:
          maxItems: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - ti,dm814-timer
              - ti,dm816-timer
              - ti,omap2420-timer
              - ti,omap3430-timer
    then:
      properties:
        ti,hwmods:
          items:
            - pattern: "^timer([1-9]|1[0-2])$"
    else:
      properties:
        ti,hwmods: false

examples:
  - |
    timer1: timer@0 {
      compatible = "ti,am335x-timer-1ms";
      reg = <0x0 0x400>;
      interrupts = <67>;
      ti,timer-alwon;
      clocks = <&timer1_fck>;
      clock-names = "fck";
    };
...


code:
VIA/Wondermedia VT8500 Timer
-----------------------------------------------------

Required properties:
- compatible : "via,vt8500-timer"
- reg : Should contain 1 register ranges(address and length)
- interrupts : interrupt for the timer

Example:

	timer@d8130100 {
		compatible = "via,vt8500-timer";
		reg = <0xd8130100 0x28>;
		interrupts = <36>;
	};


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx LogiCORE IP AXI Timer

maintainers:
  - Sean Anderson <sean.anderson@seco.com>

properties:
  compatible:
    contains:
      const: xlnx,xps-timer-1.00.a

  clocks:
    maxItems: 1

  clock-names:
    const: s_axi_aclk

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

  '#pwm-cells': true

  xlnx,count-width:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [8, 16, 32]
    default: 32
    description:
      The width of the counter(s), in bits.

  xlnx,one-timer-only:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 0, 1 ]
    description:
      Whether only one timer is present in this block.

required:
  - compatible
  - reg
  - xlnx,one-timer-only

allOf:
  - if:
      required:
        - '#pwm-cells'
    then:
      allOf:
        - required:
            - clocks
        - properties:
            xlnx,one-timer-only:
              const: 0
    else:
      required:
        - interrupts
  - if:
      required:
        - clocks
    then:
      required:
        - clock-names

additionalProperties: false

examples:
  - |
    timer@800e0000 {
        clock-names = "s_axi_aclk";
        clocks = <&zynqmp_clk 71>;
        compatible = "xlnx,xps-timer-1.00.a";
        reg = <0x800e0000 0x10000>;
        interrupts = <0 39 2>;
        xlnx,count-width = <16>;
        xlnx,one-timer-only = <0x0>;
    };

    timer@800f0000 {
        #pwm-cells = <0>;
        clock-names = "s_axi_aclk";
        clocks = <&zynqmp_clk 71>;
        compatible = "xlnx,xps-timer-1.00.a";
        reg = <0x800e0000 0x10000>;
        xlnx,count-width = <32>;
        xlnx,one-timer-only = <0x0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timestamp/hardware-timestamps-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Hardware timestamp providers

maintainers:
  - Dipen Patel <dipenp@nvidia.com>

description:
  Some devices/SoCs have hardware timestamp engines (HTE) which can use
  hardware means to timestamp entity in realtime. The entity could be anything
  from GPIOs, IRQs, Bus and so on. The hardware timestamp engine present
  itself as a provider with the bindings described in this document.

properties:
  $nodename:
    pattern: "^timestamp(@.*|-[0-9a-f])?$"

  "#timestamp-cells":
    description:
      Number of cells in a HTE specifier.

required:
  - "#timestamp-cells"

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timestamp/hte-consumer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: HTE Consumer

maintainers:
  - Dipen Patel <dipenp@nvidia.com>

select: true

properties:
  timestamps:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description:
      The list of HTE provider phandle. The first cell must represent the
      provider phandle followed by the line identifiers. The meaning of the
      line identifier and exact number of arguments must be specified in the
      HTE provider device tree binding document.

  timestamp-names:
    $ref: /schemas/types.yaml#/definitions/string-array
    description:
      An optional string property to label each line specifier present in the
      timestamp property.

dependencies:
  timestamp-names: [ timestamps ]

additionalProperties: true

examples:
  - |
    hte_tegra_consumer {
              timestamps = <&tegra_hte_aon 0x9>, <&tegra_hte_lic 0x19>;
              timestamp-names = "hte-gpio", "hte-i2c";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Tegra194 on chip generic hardware timestamping engine (HTE)

maintainers:
  - Dipen Patel <dipenp@nvidia.com>

description:
  Tegra SoC has two instances of generic hardware timestamping engines (GTE)
  known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip
  IRQ lines for the state change respectively, upon detection it will record
  timestamp (taken from system counter) in its internal hardware FIFO. It has
  a bitmap array arranged in 32bit slices where each bit represent signal/line
  to enable or disable for the hardware timestamping. The GTE GPIO monitors
  GPIO lines from the AON (always on) GPIO controller.

properties:
  compatible:
    enum:
      - nvidia,tegra194-gte-aon
      - nvidia,tegra194-gte-lic

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  nvidia,int-threshold:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      HTE device generates its interrupt based on this u32 FIFO threshold
      value. The recommended value is 1.
    minimum: 1
    maximum: 256

  nvidia,slices:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      HTE lines are arranged in 32 bit slice where each bit represents different
      line/signal that it can enable/configure for the timestamp. It is u32
      property and depends on the HTE instance in the chip. The value 3 is for
      GPIO GTE and 11 for IRQ GTE.
    enum: [3, 11]

  '#timestamp-cells':
    description:
      This represents number of line id arguments as specified by the
      consumers. For the GTE IRQ, this is IRQ number as mentioned in the
      SoC technical reference manual. For the GTE GPIO, its value is same as
      mentioned in the nvidia GPIO device tree binding document.
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - nvidia,slices
  - "#timestamp-cells"

additionalProperties: false

examples:
  - |
    tegra_hte_aon: timestamp@c1e0000 {
              compatible = "nvidia,tegra194-gte-aon";
              reg = <0xc1e0000 0x10000>;
              interrupts = <0 13 0x4>;
              nvidia,int-threshold = <1>;
              nvidia,slices = <3>;
              #timestamp-cells = <1>;
    };

  - |
    tegra_hte_lic: timestamp@3aa0000 {
              compatible = "nvidia,tegra194-gte-lic";
              reg = <0x3aa0000 0x10000>;
              interrupts = <0 11 0x4>;
              nvidia,int-threshold = <1>;
              nvidia,slices = <11>;
              #timestamp-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/trivial-devices.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Trivial I2C and SPI devices that have simple device tree bindings

maintainers:
  - Rob Herring <robh@kernel.org>

description: |
  This is a list of trivial I2C and SPI devices that have simple device tree
  bindings, consisting only of a compatible field, an address and possibly an
  interrupt line.

  If a device needs more specific bindings, such as properties to
  describe some aspect of it, there needs to be a specific binding
  document for it just like any other devices.

properties:
  reg:
    maxItems: 1
  interrupts:
    maxItems: 1

  spi-max-frequency: true

  compatible:
    items:
      - enum:
            # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
          - ad,ad7414
            # ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
          - ad,adm9240
            # AD5110 - Nonvolatile Digital Potentiometer
          - adi,ad5110
            # Analog Devices ADP5585 Keypad Decoder and I/O Expansion
          - adi,adp5585
            # Analog Devices ADP5585 Keypad Decoder and I/O Expansion with support for Row5
          - adi,adp5585-02
            # Analog Devices ADP5589 Keypad Decoder and I/O Expansion
          - adi,adp5589
            # Analog Devices LT7182S Dual Channel 6A, 20V PolyPhase Step-Down Silent Switcher
          - adi,lt7182s
            # AMS iAQ-Core VOC Sensor
          - ams,iaq-core
            # i2c serial eeprom (24cxx)
          - at,24c08
            # i2c trusted platform module (TPM)
          - atmel,at97sc3204t
            # ATSHA204 - i2c h/w symmetric crypto module
          - atmel,atsha204
            # ATSHA204A - i2c h/w symmetric crypto module
          - atmel,atsha204a
            # i2c h/w elliptic curve crypto module
          - atmel,atecc508a
            # BPA-RS600: Power Supply
          - blutek,bpa-rs600
            # Bosch Sensortec pressure, temperature, humididty and VOC sensor
          - bosch,bme680
            # CM32181: Ambient Light Sensor
          - capella,cm32181
            # CM3232: Ambient Light Sensor
          - capella,cm3232
            # CM3323: Ambient Light Sensor
          - capella,cm3323
            # High-Precision Digital Thermometer
          - dallas,ds1631
            # Total-Elapsed-Time Recorder with Alarm
          - dallas,ds1682
            # Tiny Digital Thermometer and Thermostat
          - dallas,ds1775
            # CPU Peripheral Monitor
          - dallas,ds1780
            # CPU Supervisor with Nonvolatile Memory and Programmable I/O
          - dallas,ds4510
            # Digital Thermometer and Thermostat
          - dallas,ds75
            # Delta AHE-50DC Open19 power shelf fan control module
          - delta,ahe50dc-fan
            # Delta Electronics DPS-650-AB power supply
          - delta,dps650ab
            # Delta Electronics DPS920AB 920W 54V Power Supply
          - delta,dps920ab
            # 1/4 Brick DC/DC Regulated Power Module
          - delta,q54sj108a2
            # Devantech SRF02 ultrasonic ranger in I2C mode
          - devantech,srf02
            # Devantech SRF08 ultrasonic ranger
          - devantech,srf08
            # Devantech SRF10 ultrasonic ranger
          - devantech,srf10
            # DH electronics GmbH on-board CPLD trivial SPI device
          - dh,dhcom-board
            # DA9053: flexible system level PMIC with multicore support
          - dlg,da9053
            # DMARD05: 3-axis I2C Accelerometer
          - domintech,dmard05
            # DMARD06: 3-axis I2C Accelerometer
          - domintech,dmard06
            # DMARD05: 3-axis I2C Accelerometer
          - domintech,dmard07
            # DMARD09: 3-axis Accelerometer
          - domintech,dmard09
            # DMARD10: 3-axis Accelerometer
          - domintech,dmard10
            # MMA7660FC: 3-Axis Orientation/Motion Detection Sensor
          - fsl,mma7660
            # MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
          - fsl,mma8450
            # MPL3115: Absolute Digital Pressure Sensor
          - fsl,mpl3115
            # MPR121: Proximity Capacitive Touch Sensor Controller
          - fsl,mpr121
            # Monolithic Power Systems Inc. multi-phase controller mp2888
          - mps,mp2888
            # Monolithic Power Systems Inc. multi-phase controller mp2975
          - mps,mp2975
            # Honeywell Humidicon HIH-6130 humidity/temperature sensor
          - honeywell,hi6130
            # IBM Common Form Factor Power Supply Versions (all versions)
          - ibm,cffps
            # IBM Common Form Factor Power Supply Versions 1
          - ibm,cffps1
            # IBM Common Form Factor Power Supply Versions 2
          - ibm,cffps2
            # Infineon IR36021 digital POL buck controller
          - infineon,ir36021
            # Infineon IR38060 Voltage Regulator
          - infineon,ir38060
            # Infineon IR38064 Voltage Regulator
          - infineon,ir38064
            # Infineon IR38164 Voltage Regulator
          - infineon,ir38164
            # Infineon IR38263 Voltage Regulator
          - infineon,ir38263
            # Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
          - infineon,slb9635tt
            # Infineon SLB9645 I2C TPM (new protocol, max 400khz)
          - infineon,slb9645tt
            # Infineon SLB9673 I2C TPM 2.0
          - infineon,slb9673
            # Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor
          - infineon,tlv493d-a1b6
            # Infineon Multi-phase Digital VR Controller xdpe11280
          - infineon,xdpe11280
            # Infineon Multi-phase Digital VR Controller xdpe12254
          - infineon,xdpe12254
            # Infineon Multi-phase Digital VR Controller xdpe12284
          - infineon,xdpe12284
            # Infineon Multi-phase Digital VR Controller xdpe15284
          - infineon,xdpe15284
            # Infineon Multi-phase Digital VR Controller xdpe152c4
          - infineon,xdpe152c4
            # Injoinic IP5108 2.0A Power Bank IC with I2C
          - injoinic,ip5108
            # Injoinic IP5109 2.1A Power Bank IC with I2C
          - injoinic,ip5109
            # Injoinic IP5207 1.2A Power Bank IC with I2C
          - injoinic,ip5207
            # Injoinic IP5209 2.4A Power Bank IC with I2C
          - injoinic,ip5209
            # Inspur Power System power supply unit version 1
          - inspur,ipsps1
            # Intersil ISL29028 Ambient Light and Proximity Sensor
          - isil,isl29028
            # Intersil ISL29030 Ambient Light and Proximity Sensor
          - isil,isl29030
            # Intersil ISL68137 Digital Output Configurable PWM Controller
          - isil,isl68137
            # 5 Bit Programmable, Pulse-Width Modulator
          - maxim,ds1050
            # 10 kOhm digital potentiometer with I2C interface
          - maxim,ds1803-010
            # 50 kOhm digital potentiometer with I2C interface
          - maxim,ds1803-050
            # 100 kOhm digital potentiometer with I2C interface
          - maxim,ds1803-100
            # 10 kOhm digital potentiometer with I2C interface
          - maxim,ds3502
            # Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
          - maxim,max1237
            # Temperature Sensor, I2C interface
          - maxim,max1619
            # 10-bit 10 kOhm linear programable voltage divider
          - maxim,max5481
            # 10-bit 50 kOhm linear programable voltage divider
          - maxim,max5482
            # 10-bit 10 kOhm linear programable variable resistor
          - maxim,max5483
            # 10-bit 50 kOhm linear programable variable resistor
          - maxim,max5484
            # PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion
          - maxim,max6621
            # 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
          - maxim,max6625
            # 3-Channel Remote Temperature Sensor
          - maxim,max31730
            # mCube 3-axis 8-bit digital accelerometer
          - mcube,mc3230
            # Measurement Specialities I2C temperature and humidity sensor
          - meas,htu21
            # Measurement Specialities I2C pressure and temperature sensor
          - meas,ms5637
            # Measurement Specialities I2C pressure and temperature sensor
          - meas,ms5803
            # Measurement Specialities I2C pressure and temperature sensor
          - meas,ms5805
            # Measurement Specialities I2C pressure and temperature sensor
          - meas,ms5837
            # Measurement Specialities temp and humidity part of ms8607 device
          - meas,ms8607-humidity
            # Measurement Specialities temp and pressure part of ms8607 device
          - meas,ms8607-temppressure
            # Measurement Specialties temperature sensor
          - meas,tsys01
            # MEMSIC magnetometer
          - memsic,mmc35240
            # MEMSIC 3-axis accelerometer
          - memsic,mx4005
            # MEMSIC 2-axis 8-bit digital accelerometer
          - memsic,mxc6225
            # MEMSIC 2-axis 8-bit digital accelerometer
          - memsic,mxc6255
            # MEMSIC 3-axis accelerometer
          - memsic,mxc6655
            # Menlo on-board CPLD trivial SPI device
          - menlo,m53cpld
            # Microchip differential I2C ADC, 1 Channel, 18 bit
          - microchip,mcp3421
            # Microchip differential I2C ADC, 2 Channel, 18 bit
          - microchip,mcp3422
            # Microchip differential I2C ADC, 2 Channel, 18 bit
          - microchip,mcp3423
            # Microchip differential I2C ADC, 4 Channel, 18 bit
          - microchip,mcp3424
            # Microchip differential I2C ADC, 1 Channel, 16 bit
          - microchip,mcp3425
            # Microchip differential I2C ADC, 2 Channel, 16 bit
          - microchip,mcp3426
            # Microchip differential I2C ADC, 2 Channel, 16 bit
          - microchip,mcp3427
            # Microchip differential I2C ADC, 4 Channel, 16 bit
          - microchip,mcp3428
            # Microchip 7-bit Single I2C Digital POT (5k)
          - microchip,mcp4017-502
            # Microchip 7-bit Single I2C Digital POT (10k)
          - microchip,mcp4017-103
            # Microchip 7-bit Single I2C Digital POT (50k)
          - microchip,mcp4017-503
            # Microchip 7-bit Single I2C Digital POT (100k)
          - microchip,mcp4017-104
            # Microchip 7-bit Single I2C Digital POT (5k)
          - microchip,mcp4018-502
            # Microchip 7-bit Single I2C Digital POT (10k)
          - microchip,mcp4018-103
            # Microchip 7-bit Single I2C Digital POT (50k)
          - microchip,mcp4018-503
            # Microchip 7-bit Single I2C Digital POT (100k)
          - microchip,mcp4018-104
            # Microchip 7-bit Single I2C Digital POT (5k)
          - microchip,mcp4019-502
            # Microchip 7-bit Single I2C Digital POT (10k)
          - microchip,mcp4019-103
            # Microchip 7-bit Single I2C Digital POT (50k)
          - microchip,mcp4019-503
            # Microchip 7-bit Single I2C Digital POT (100k)
          - microchip,mcp4019-104
            # PWM Fan Speed Controller With Fan Fault Detection
          - microchip,tc654
            # PWM Fan Speed Controller With Fan Fault Detection
          - microchip,tc655
            # MiraMEMS DA226 2-axis 14-bit digital accelerometer
          - miramems,da226
            # MiraMEMS DA280 3-axis 14-bit digital accelerometer
          - miramems,da280
            # MiraMEMS DA311 3-axis 12-bit digital accelerometer
          - miramems,da311
            # Temperature sensor with integrated fan control
          - national,lm63
            # I2C TEMP SENSOR
          - national,lm75
            # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
          - national,lm80
            # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
          - national,lm81
            # Temperature sensor with integrated fan control
          - national,lm85
            # I2C ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator
          - national,lm92
            # i2c trusted platform module (TPM)
          - nuvoton,npct501
            # i2c trusted platform module (TPM2)
          - nuvoton,npct601
            # Nuvoton Temperature Sensor
          - nuvoton,w83773g
            # OKI ML86V7667 video decoder
          - oki,ml86v7667
            # OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
          - ovti,ov5642
            # 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
          - plx,pex8648
            # Pulsedlight LIDAR range-finding sensor
          - pulsedlight,lidar-lite-v2
            # Renesas ISL29501 time-of-flight sensor
          - renesas,isl29501
            # S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
          - samsung,24ad0xd1
            # Samsung Exynos SoC SATA PHY I2C device
          - samsung,exynos-sataphy-i2c
            # Sensirion low power multi-pixel gas sensor with I2C interface
          - sensirion,sgpc3
            # Sensirion multi-pixel gas sensor with I2C interface
          - sensirion,sgp30
            # Sensirion gas sensor with I2C interface
          - sensirion,sgp40
            # Sensirion temperature & humidity sensor with I2C interface
          - sensirion,sht4x
            # Sensortek 3 axis accelerometer
          - sensortek,stk8312
            # Sensortek 3 axis accelerometer
          - sensortek,stk8ba50
            # SGX Sensortech VZ89X Sensors
          - sgx,vz89x
            # Relative Humidity and Temperature Sensors
          - silabs,si7020
            # Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply
          - skyworks,sky81452
            # Socionext SynQuacer TPM MMIO module
          - socionext,synquacer-tpm-mmio
            # SparkFun Qwiic Joystick (COM-15168) with i2c interface
          - sparkfun,qwiic-joystick
            # i2c serial eeprom (24cxx)
          - st,24c256
            # Ambient Light Sensor with SMBUS/Two Wire Serial Interface
          - taos,tsl2550
            # Temperature Monitoring and Fan Control
          - ti,amc6821
            # Temperature and humidity sensor with i2c interface
          - ti,hdc1000
            # Temperature and humidity sensor with i2c interface
          - ti,hdc1008
            # Temperature and humidity sensor with i2c interface
          - ti,hdc1010
            # Temperature and humidity sensor with i2c interface
          - ti,hdc1050
            # Temperature and humidity sensor with i2c interface
          - ti,hdc1080
            # Thermometer with SPI interface
          - ti,lm70
          - ti,lm71
            # Temperature sensor with 2-wire interface
          - ti,lm73
            # Thermometer with SPI interface
          - ti,lm74
            # Temperature sensor with integrated fan control
          - ti,lm96000
            # I2C Touch-Screen Controller
          - ti,tsc2003
            # Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
          - ti,tmp103
            # Thermometer with SPI interface
          - ti,tmp121
          - ti,tmp122
          - ti,tmp125
            # Digital Temperature Sensor
          - ti,tmp275
            # TI DC-DC converter on PMBus
          - ti,tps40400
            # TI Dual channel DCAP+ multiphase controller TPS53676 with AVSBus
          - ti,tps53676
            # TI Dual channel DCAP+ multiphase controller TPS53679
          - ti,tps53679
            # TI Dual channel DCAP+ multiphase controller TPS53688
          - ti,tps53688
            # TI DC-DC converters on PMBus
          - ti,tps544b20
          - ti,tps544b25
          - ti,tps544c20
          - ti,tps544c25
            # Winbond/Nuvoton H/W Monitor
          - winbond,w83793
            # Vicor Corporation Digital Supervisor
          - vicor,pli1209bc
            # i2c trusted platform module (TPM)
          - winbond,wpct301

required:
  - compatible
  - reg

additionalProperties: false

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence Universal Flash Storage (UFS) Controller

maintainers:
  - Jan Kotas <jank@cadence.com>

# Select only our matches, not all jedec,ufs-2.0
select:
  properties:
    compatible:
      contains:
        enum:
          - cdns,ufshc
          - cdns,ufshc-m31-16nm
  required:
    - compatible

allOf:
  - $ref: ufs-common.yaml

properties:
  compatible:
    items:
      - enum:
          - cdns,ufshc
            # CDNS UFS HC + M31 16nm PHY
          - cdns,ufshc-m31-16nm
      - const: jedec,ufs-2.0

  clocks:
    minItems: 1
    maxItems: 3

  clock-names:
    minItems: 1
    items:
      - const: core_clk
      - const: phy_clk
      - const: ref_clk

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

  dma-coherent: true

required:
  - compatible
  - clocks
  - clock-names
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    ufs@fd030000 {
        compatible = "cdns,ufshc", "jedec,ufs-2.0";
        reg = <0xfd030000 0x10000>;
        interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
        freq-table-hz = <0 0>, <0 0>;
        clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
        clock-names = "core_clk", "phy_clk";
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/hisilicon,ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: HiSilicon Universal Flash Storage (UFS) Controller

maintainers:
  - Li Wei <liwei213@huawei.com>

# Select only our matches, not all jedec,ufs
select:
  properties:
    compatible:
      contains:
        enum:
          - hisilicon,hi3660-ufs
          - hisilicon,hi3670-ufs
  required:
    - compatible

allOf:
  - $ref: ufs-common.yaml

properties:
  compatible:
    oneOf:
      - items:
          - const: hisilicon,hi3660-ufs
          - const: jedec,ufs-1.1
      - items:
          - enum:
              - hisilicon,hi3670-ufs
          - const: jedec,ufs-2.1

  clocks:
    minItems: 2
    maxItems: 2

  clock-names:
    items:
      - const: ref_clk
      - const: phy_clk

  reg:
    items:
      - description: UFS register address space
      - description: UFS SYS CTRL register address space

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: rst

required:
  - compatible
  - reg
  - resets
  - reset-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/hi3670-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        ufs@ff3c0000 {
            compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
            reg = <0x0 0xff3c0000 0x0 0x1000>,
                  <0x0 0xff3e0000 0x0 0x1000>;
            interrupt-parent = <&gic>;
            interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
                     <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
            clock-names = "ref_clk", "phy_clk";
            freq-table-hz = <0 0>,
                            <0 0>;

            resets = <&crg_rst 0x84 12>;
            reset-names = "rst";
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/mediatek,ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek Universal Flash Storage (UFS) Controller

maintainers:
  - Stanley Chu <stanley.chu@mediatek.com>

allOf:
  - $ref: ufs-common.yaml

properties:
  compatible:
    enum:
      - mediatek,mt8183-ufshci
      - mediatek,mt8192-ufshci

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: ufs

  phys:
    maxItems: 1

  reg:
    maxItems: 1

  vcc-supply: true

required:
  - compatible
  - clocks
  - clock-names
  - phys
  - reg
  - vcc-supply

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        ufs@ff3c0000 {
            compatible = "mediatek,mt8183-ufshci";
            reg = <0 0x11270000 0 0x2300>;
            interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
            phys = <&ufsphy>;

            clocks = <&infracfg_ao CLK_INFRA_UFS>;
            clock-names = "ufs";
            freq-table-hz = <0 0>;

            vcc-supply = <&mt_pmic_vemc_ldo_reg>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Universal Flash Storage (UFS) Controller

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>
  - Andy Gross <agross@kernel.org>

# Select only our matches, not all jedec,ufs-2.0
select:
  properties:
    compatible:
      contains:
        const: qcom,ufshc
  required:
    - compatible

properties:
  compatible:
    items:
      - enum:
          - qcom,msm8994-ufshc
          - qcom,msm8996-ufshc
          - qcom,msm8998-ufshc
          - qcom,sc8280xp-ufshc
          - qcom,sdm845-ufshc
          - qcom,sm6350-ufshc
          - qcom,sm8150-ufshc
          - qcom,sm8250-ufshc
          - qcom,sm8350-ufshc
          - qcom,sm8450-ufshc
      - const: qcom,ufshc
      - const: jedec,ufs-2.0

  clocks:
    minItems: 8
    maxItems: 11

  clock-names:
    minItems: 8
    maxItems: 11

  interconnects:
    minItems: 2
    maxItems: 2

  interconnect-names:
    items:
      - const: ufs-ddr
      - const: cpu-ufs

  iommus:
    minItems: 1
    maxItems: 2

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: ufsphy

  power-domains:
    maxItems: 1

  reg:
    minItems: 1
    maxItems: 2

  resets:
    maxItems: 1

  '#reset-cells':
    const: 1

  reset-names:
    items:
      - const: rst

  reset-gpios:
    maxItems: 1
    description:
      GPIO connected to the RESET pin of the UFS memory device.

required:
  - compatible
  - reg

allOf:
  - $ref: ufs-common.yaml

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8998-ufshc
              - qcom,sc8280xp-ufshc
              - qcom,sm8250-ufshc
              - qcom,sm8350-ufshc
              - qcom,sm8450-ufshc
    then:
      properties:
        clocks:
          minItems: 8
          maxItems: 8
        clock-names:
          items:
            - const: core_clk
            - const: bus_aggr_clk
            - const: iface_clk
            - const: core_clk_unipro
            - const: ref_clk
            - const: tx_lane0_sync_clk
            - const: rx_lane0_sync_clk
            - const: rx_lane1_sync_clk
        reg:
          minItems: 1
          maxItems: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdm845-ufshc
              - qcom,sm6350-ufshc
              - qcom,sm8150-ufshc
    then:
      properties:
        clocks:
          minItems: 9
          maxItems: 9
        clock-names:
          items:
            - const: core_clk
            - const: bus_aggr_clk
            - const: iface_clk
            - const: core_clk_unipro
            - const: ref_clk
            - const: tx_lane0_sync_clk
            - const: rx_lane0_sync_clk
            - const: rx_lane1_sync_clk
            - const: ice_core_clk
        reg:
          minItems: 2
          maxItems: 2

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,msm8996-ufshc
    then:
      properties:
        clocks:
          minItems: 11
          maxItems: 11
        clock-names:
          items:
            - const: core_clk_src
            - const: core_clk
            - const: bus_clk
            - const: bus_aggr_clk
            - const: iface_clk
            - const: core_clk_unipro_src
            - const: core_clk_unipro
            - const: core_clk_ice
            - const: ref_clk
            - const: tx_lane0_sync_clk
            - const: rx_lane0_sync_clk
        reg:
          minItems: 1
          maxItems: 1

    # TODO: define clock bindings for qcom,msm8994-ufshc

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interconnect/qcom,sm8450.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        ufs@1d84000 {
            compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
                         "jedec,ufs-2.0";
            reg = <0 0x01d84000 0 0x3000>;
            interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
            phys = <&ufs_mem_phy_lanes>;
            phy-names = "ufsphy";
            lanes-per-direction = <2>;
            #reset-cells = <1>;
            resets = <&gcc GCC_UFS_PHY_BCR>;
            reset-names = "rst";
            reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;

            vcc-supply = <&vreg_l7b_2p5>;
            vcc-max-microamp = <1100000>;
            vccq-supply = <&vreg_l9b_1p2>;
            vccq-max-microamp = <1200000>;

            power-domains = <&gcc UFS_PHY_GDSC>;
            iommus = <&apps_smmu 0xe0 0x0>;
            interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
                            <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
            interconnect-names = "ufs-ddr", "cpu-ufs";

            clock-names = "core_clk",
                          "bus_aggr_clk",
                          "iface_clk",
                          "core_clk_unipro",
                          "ref_clk",
                          "tx_lane0_sync_clk",
                          "rx_lane0_sync_clk",
                          "rx_lane1_sync_clk";
            clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
                     <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
                     <&gcc GCC_UFS_PHY_AHB_CLK>,
                     <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
                     <&rpmhcc RPMH_CXO_CLK>,
                     <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
                     <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
                     <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
            freq-table-hz = <75000000 300000000>,
                            <0 0>,
                            <0 0>,
                            <75000000 300000000>,
                            <75000000 300000000>,
                            <0 0>,
                            <0 0>,
                            <0 0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/renesas,ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car UFS Host Controller

maintainers:
  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

allOf:
  - $ref: ufs-common.yaml

properties:
  compatible:
    const: renesas,r8a779f0-ufs

  reg:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: fck
      - const: ref_clk

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains
  - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a779f0-sysc.h>

    ufs: ufs@e686000 {
            compatible = "renesas,r8a779f0-ufs";
            reg = <0xe6860000 0x100>;
            interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
            clock-names = "fck", "ref_clk";
            freq-table-hz = <200000000 200000000>, <38400000 38400000>;
            power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
            resets = <&cpg 1514>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung SoC series UFS host controller

maintainers:
  - Alim Akhtar <alim.akhtar@samsung.com>

description: |
  Each Samsung UFS host controller instance should have its own node.

allOf:
  - $ref: ufs-common.yaml

properties:
  compatible:
    enum:
      - samsung,exynos7-ufs
      - samsung,exynosautov9-ufs
      - samsung,exynosautov9-ufs-vh
      - tesla,fsd-ufs

  reg:
    items:
      - description: HCI register
      - description: vendor specific register
      - description: unipro register
      - description: UFS protector register

  reg-names:
    items:
      - const: hci
      - const: vs_hci
      - const: unipro
      - const: ufsp

  clocks:
    items:
      - description: ufs link core clock
      - description: unipro main clock

  clock-names:
    items:
      - const: core_clk
      - const: sclk_unipro_main

  phys:
    maxItems: 1

  phy-names:
    const: ufs-phy

  samsung,sysreg:
    $ref: '/schemas/types.yaml#/definitions/phandle-array'
    description: Should be phandle/offset pair. The phandle to the syscon node
                 which indicates the FSYSx sysreg interface and the offset of
                 the control register for UFS io coherency setting.

  dma-coherent: true

required:
  - compatible
  - reg
  - phys
  - phy-names
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/exynos7-clk.h>

    ufs: ufs@15570000 {
       compatible = "samsung,exynos7-ufs";
       reg = <0x15570000 0x100>,
             <0x15570100 0x100>,
             <0x15571000 0x200>,
             <0x15572000 0x300>;
       reg-names = "hci", "vs_hci", "unipro", "ufsp";
       interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
       clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
                <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
       clock-names = "core_clk", "sclk_unipro_main";
       pinctrl-names = "default";
       pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
       phys = <&ufs_phy>;
       phy-names = "ufs-phy";
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/snps,tc-dwc-g210.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare Universal Flash Storage (UFS) Controller

maintainers:
  - Li Wei <liwei213@huawei.com>

# Select only our matches, not all jedec,ufs
select:
  properties:
    compatible:
      contains:
        enum:
          - snps,dwc-ufshcd-1.40a
  required:
    - compatible

allOf:
  - $ref: ufs-common.yaml

properties:
  compatible:
    items:
      - enum:
          - snps,g210-tc-6.00-20bit
          - snps,g210-tc-6.00-40bit
      - const: snps,dwc-ufshcd-1.40a
      - const: jedec,ufs-2.0

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    ufs@d0000000 {
        compatible = "snps,g210-tc-6.00-40bit",
                     "snps,dwc-ufshcd-1.40a",
                     "jedec,ufs-2.0";
        reg = <0xd0000000 0x10000>;
        interrupts = <24>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI J721e UFS Host Controller Glue Driver

maintainers:
  - Vignesh Raghavendra <vigneshr@ti.com>

properties:
  compatible:
    items:
      - const: ti,j721e-ufs

  reg:
    maxItems: 1
    description: address of TI UFS glue registers

  clocks:
    maxItems: 1
    description: phandle to the M-PHY clock

  power-domains:
    maxItems: 1

  assigned-clocks:
    maxItems: 1

  assigned-clock-parents:
    maxItems: 1

  "#address-cells":
    const: 2

  "#size-cells":
    const: 2

  ranges: true

required:
  - compatible
  - reg
  - clocks
  - power-domains

patternProperties:
  "^ufs@[0-9a-f]+$":
    $ref: cdns,ufshc.yaml
    description: |
      Cadence UFS controller node must be the child node.
    unevaluatedProperties: false

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        ufs-wrapper@4e80000 {
            compatible = "ti,j721e-ufs";
            reg = <0x0 0x4e80000 0x0 0x100>;
            power-domains = <&k3_pds 277>;
            clocks = <&k3_clks 277 1>;
            assigned-clocks = <&k3_clks 277 1>;
            assigned-clock-parents = <&k3_clks 277 4>;

            ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
            #address-cells = <2>;
            #size-cells = <2>;

            ufs@4000 {
                compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
                reg = <0x0 0x4000 0x0 0x10000>;
                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                freq-table-hz = <19200000 19200000>;
                power-domains = <&k3_pds 277>;
                clocks = <&k3_clks 277 1>;
                assigned-clocks = <&k3_clks 277 1>;
                assigned-clock-parents = <&k3_clks 277 4>;
                clock-names = "core_clk";
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/ufs/ufs-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Common properties for Universal Flash Storage (UFS) Host Controllers

maintainers:
  - Alim Akhtar <alim.akhtar@samsung.com>
  - Avri Altman <avri.altman@wdc.com>

properties:
  clocks: true

  clock-names: true

  freq-table-hz:
    items:
      items:
        - description: Minimum frequency for given clock in Hz
        - description: Maximum frequency for given clock in Hz
    description: |
      Array of <min max> operating frequencies in Hz stored in the same order
      as the clocks property. If this property is not defined or a value in the
      array is "0" then it is assumed that the frequency is set by the parent
      clock or a fixed rate clock source.

  interrupts:
    maxItems: 1

  lanes-per-direction:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 2]
    default: 2
    description:
      Number of lanes available per direction.  Note that it is assume same
      number of lanes is used both directions at once.

  vdd-hba-supply:
    description:
      Phandle to UFS host controller supply regulator node.

  vcc-supply:
    description:
      Phandle to VCC supply regulator node.

  vccq-supply:
    description:
      Phandle to VCCQ supply regulator node.

  vccq2-supply:
    description:
      Phandle to VCCQ2 supply regulator node.

  vcc-supply-1p8:
    type: boolean
    description:
      For embedded UFS devices, valid VCC range is 1.7-1.95V or 2.7-3.6V. This
      boolean property when set, specifies to use low voltage range of
      1.7-1.95V. Note for external UFS cards this property is invalid and valid
      VCC range is always 2.7-3.6V.

  vcc-max-microamp:
    description:
      Specifies max. load that can be drawn from VCC supply.

  vccq-max-microamp:
    description:
      Specifies max. load that can be drawn from VCCQ supply.

  vccq2-max-microamp:
    description:
      Specifies max. load that can be drawn from VCCQ2 supply.

dependencies:
  freq-table-hz: [ 'clocks' ]

required:
  - interrupts

additionalProperties: true


code:
1) OF unittest platform device

** unittest

Required properties:
- compatible: must be "unittest"

All other properties are optional.

Example:
	unittest {
		compatible = "unittest";
	};

2) OF unittest i2c adapter platform device

** platform device unittest adapter

Required properties:
- compatible: must be unittest-i2c-bus

Children nodes contain unittest i2c devices.

Example:
	unittest-i2c-bus {
		compatible = "unittest-i2c-bus";
	};

3) OF unittest i2c device

** I2C unittest device

Required properties:
- compatible: must be unittest-i2c-dev

All other properties are optional

Example:
	unittest-i2c-dev {
		compatible = "unittest-i2c-dev";
	};

4) OF unittest i2c mux device

** I2C unittest mux

Required properties:
- compatible: must be unittest-i2c-mux

Children nodes contain unittest i2c bus nodes per channel.

Example:
	unittest-i2c-mux {
		compatible = "unittest-i2c-mux";
		#address-cells = <1>;
		#size-cells = <0>;
		channel-0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;
			i2c-dev {
				reg = <8>;
				compatible = "unittest-i2c-dev";
			};
		};
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/allwinner,sun4i-a10-musb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 mUSB OTG Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  compatible:
    oneOf:
      - const: allwinner,sun4i-a10-musb
      - const: allwinner,sun6i-a31-musb
      - const: allwinner,sun8i-a33-musb
      - const: allwinner,sun8i-h3-musb
      - items:
          - enum:
              - allwinner,sun8i-a83t-musb
              - allwinner,sun20i-d1-musb
              - allwinner,sun50i-h6-musb
          - const: allwinner,sun8i-a33-musb
      - items:
          - const: allwinner,sun50i-h616-musb
          - const: allwinner,sun8i-h3-musb

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-names:
    const: mc

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  phys:
    maxItems: 1

  phy-names:
    const: usb

  extcon:
    description: Extcon specifier for the OTG PHY

  dr_mode:
    enum:
      - host
      - otg
      - peripheral

  allwinner,sram:
    description: Phandle to the device SRAM
    $ref: /schemas/types.yaml#/definitions/phandle-array

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - phys
  - phy-names
  - dr_mode
  - extcon

if:
  properties:
    compatible:
      contains:
        enum:
          - allwinner,sun6i-a31-musb
          - allwinner,sun8i-a33-musb
          - allwinner,sun8i-h3-musb

then:
  required:
    - resets

additionalProperties: false

examples:
  - |
    usb_otg: usb@1c13000 {
      compatible = "allwinner,sun4i-a10-musb";
      reg = <0x01c13000 0x0400>;
      clocks = <&ahb_gates 0>;
      interrupts = <38>;
      interrupt-names = "mc";
      phys = <&usbphy 0>;
      phy-names = "usb";
      extcon = <&usbphy 0>;
      dr_mode = "peripheral";
    };

...


code:
  AM33xx MUSB
~~~~~~~~~~~~~~~
- compatible: ti,am33xx-usb
- reg: offset and length of the usbss register sets
- ti,hwmods : must be "usb_otg_hs"

The glue layer contains multiple child nodes. It is required to have
at least a control module node, USB node and a PHY node. The second USB
node and its PHY node are optional. The DMA node is also optional.

Reset module
~~~~~~~~~~~~
- compatible: ti,am335x-usb-ctrl-module
- reg: offset and length of the "USB control registers" in the "Control
  Module" block. A second offset and length for the USB wake up control
  in the same memory block.
- reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
  the USB wake up control register.

USB PHY
~~~~~~~
compatible: ti,am335x-usb-phy
reg: offset and length of the "USB PHY" register space
ti,ctrl_mod: reference to the "reset module" node
reg-names: phy
The PHY should have a "phy" alias numbered properly in the alias
node.

USB
~~~
- compatible: ti,musb-am33xx
- reg: offset and length of "USB Controller Registers", and offset and
  length of "USB Core" register space.
- reg-names: control for the ""USB Controller Registers" and "mc" for
  "USB Core" register space
- interrupts: USB interrupt number
- interrupt-names: mc
- dr_mode: Should be one of "host", "peripheral" or "otg".
- mentor,multipoint: Should be "1" indicating the musb controller supports
  multipoint. This is a MUSB configuration-specific setting.
- mentor,num-eps: Specifies the number of endpoints. This is also a
  MUSB configuration-specific setting. Should be set to "16"
- mentor,ram-bits: Specifies the ram address size. Should be set to "12"
- mentor,power: Should be "500". This signifies the controller can supply up to
  500mA when operating in host mode.
- phys: reference to the USB phy
- dmas: specifies the dma channels
- dma-names: specifies the names of the channels. Use "rxN" for receive
  and "txN" for transmit endpoints. N specifies the endpoint number.

The controller should have an "usb" alias numbered properly in the alias
node.

DMA
~~~
- compatible: ti,am3359-cppi41
- reg: offset and length of the following register spaces: USBSS, USB
  CPPI DMA Controller, USB CPPI DMA Scheduler, USB Queue Manager
- reg-names: glue, controller, scheduler, queuemgr
- #dma-cells: should be set to 2. The first number represents the
  endpoint number (0 … 14 for endpoints 1 … 15 on instance 0 and 15 … 29
  for endpoints 1 … 15 on instance 1). The second number is 0 for RX and
  1 for TX transfers.
- dma-channels: should be set to 30 representing the 15 endpoints for
  each USB instance.
- #dma-channels: deprecated

Example:
~~~~~~~~
The following example contains all the nodes as used on am335x-evm:

aliases {
	usb0 = &usb0;
	usb1 = &usb1;
	phy0 = &usb0_phy;
	phy1 = &usb1_phy;
};

usb: usb@47400000 {
	compatible = "ti,am33xx-usb";
	reg = <0x47400000 0x1000>;
	ranges;
	#address-cells = <1>;
	#size-cells = <1>;
	ti,hwmods = "usb_otg_hs";

	ctrl_mod: control@44e10000 {
		compatible = "ti,am335x-usb-ctrl-module";
		reg = <0x44e10620 0x10
			0x44e10648 0x4>;
		reg-names = "phy_ctrl", "wakeup";
	};

	usb0_phy: usb-phy@47401300 {
		compatible = "ti,am335x-usb-phy";
		reg = <0x47401300 0x100>;
		reg-names = "phy";
		ti,ctrl_mod = <&ctrl_mod>;
		#phy-cells = <0>;
	};

	usb0: usb@47401000 {
		compatible = "ti,musb-am33xx";
		reg = <0x47401400 0x400
			0x47401000 0x200>;
		reg-names = "mc", "control";

		interrupts = <18>;
		interrupt-names = "mc";
		dr_mode = "otg"
		mentor,multipoint = <1>;
		mentor,num-eps = <16>;
		mentor,ram-bits = <12>;
		mentor,power = <500>;
		phys = <&usb0_phy>;

		dmas = <&cppi41dma  0 0 &cppi41dma  1 0
			&cppi41dma  2 0 &cppi41dma  3 0
			&cppi41dma  4 0 &cppi41dma  5 0
			&cppi41dma  6 0 &cppi41dma  7 0
			&cppi41dma  8 0 &cppi41dma  9 0
			&cppi41dma 10 0 &cppi41dma 11 0
			&cppi41dma 12 0 &cppi41dma 13 0
			&cppi41dma 14 0 &cppi41dma  0 1
			&cppi41dma  1 1 &cppi41dma  2 1
			&cppi41dma  3 1 &cppi41dma  4 1
			&cppi41dma  5 1 &cppi41dma  6 1
			&cppi41dma  7 1 &cppi41dma  8 1
			&cppi41dma  9 1 &cppi41dma 10 1
			&cppi41dma 11 1 &cppi41dma 12 1
			&cppi41dma 13 1 &cppi41dma 14 1>;
		dma-names =
			"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
			"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
			"rx14", "rx15",
			"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
			"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
			"tx14", "tx15";
	};

	usb1_phy: usb-phy@47401b00 {
		compatible = "ti,am335x-usb-phy";
		reg = <0x47401b00 0x100>;
		reg-names = "phy";
		ti,ctrl_mod = <&ctrl_mod>;
		#phy-cells = <0>;
	};

	usb1: usb@47401800 {
		compatible = "ti,musb-am33xx";
		reg = <0x47401c00 0x400
			0x47401800 0x200>;
		reg-names = "mc", "control";
		interrupts = <19>;
		interrupt-names = "mc";
		dr_mode = "host"
		mentor,multipoint = <1>;
		mentor,num-eps = <16>;
		mentor,ram-bits = <12>;
		mentor,power = <500>;
		phys = <&usb1_phy>;

		dmas = <&cppi41dma 15 0 &cppi41dma 16 0
			&cppi41dma 17 0 &cppi41dma 18 0
			&cppi41dma 19 0 &cppi41dma 20 0
			&cppi41dma 21 0 &cppi41dma 22 0
			&cppi41dma 23 0 &cppi41dma 24 0
			&cppi41dma 25 0 &cppi41dma 26 0
			&cppi41dma 27 0 &cppi41dma 28 0
			&cppi41dma 29 0 &cppi41dma 15 1
			&cppi41dma 16 1 &cppi41dma 17 1
			&cppi41dma 18 1 &cppi41dma 19 1
			&cppi41dma 20 1 &cppi41dma 21 1
			&cppi41dma 22 1 &cppi41dma 23 1
			&cppi41dma 24 1 &cppi41dma 25 1
			&cppi41dma 26 1 &cppi41dma 27 1
			&cppi41dma 28 1 &cppi41dma 29 1>;
		dma-names =
			"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
			"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
			"rx14", "rx15",
			"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
			"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
			"tx14", "tx15";
	};

	cppi41dma: dma-controller@7402000 {
		compatible = "ti,am3359-cppi41";
		reg =  <0x47400000 0x1000
			0x47402000 0x1000
			0x47403000 0x1000
			0x47404000 0x4000>;
		reg-names = "glue", "controller", "scheduler", "queuemgr";
		interrupts = <17>;
		interrupt-names = "glue";
		#dma-cells = <2>;
		dma-channels = <30>;
		dma-requests = <256>;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Meson G12A DWC3 USB SoC Controller Glue

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

description: |
  The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
  in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
  only.

  A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.

  One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.

  The DWC3 Glue controls the PHY routing and power, an interrupt line is
  connected to the Glue to serve as OTG ID change detection.

  The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
  host-only mode.

  The Amlogic GXL, GXM & AXG SoCs doesn't embed an USB3 PHY.

properties:
  compatible:
    enum:
      - amlogic,meson-gxl-usb-ctrl
      - amlogic,meson-gxm-usb-ctrl
      - amlogic,meson-axg-usb-ctrl
      - amlogic,meson-g12a-usb-ctrl
      - amlogic,meson-a1-usb-ctrl

  ranges: true

  "#address-cells":
    enum: [ 1, 2 ]

  "#size-cells":
    enum: [ 1, 2 ]

  clocks:
    minItems: 1
    maxItems: 3

  clock-names:
    minItems: 1
    maxItems: 3

  resets:
    minItems: 1

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  phy-names:
    minItems: 1
    maxItems: 3

  phys:
    minItems: 1
    maxItems: 3

  dr_mode: true

  power-domains:
    maxItems: 1

  vbus-supply:
    description: VBUS power supply when used in OTG switchable mode

patternProperties:
  "^usb@[0-9a-f]+$":
    oneOf:
      - $ref: dwc2.yaml#
      - $ref: snps,dwc3.yaml#

additionalProperties: false

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - ranges
  - clocks
  - resets
  - reg
  - interrupts
  - phy-names
  - phys
  - dr_mode

allOf:
  - if:
      properties:
        compatible:
          enum:
            - amlogic,meson-g12a-usb-ctrl

    then:
      properties:
        phy-names:
          items:
            - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
            - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
            - const: usb3-phy0 # USB3 PHY if USB3_0 is used
  - if:
      properties:
        compatible:
          enum:
            - amlogic,meson-gxl-usb-ctrl

    then:
      properties:
        clocks:
          minItems: 2
        clock-names:
          items:
            - const: usb_ctrl
            - const: ddr
        phy-names:
          items:
            - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
            - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
      required:
        - clock-names
  - if:
      properties:
        compatible:
          enum:
            - amlogic,meson-gxm-usb-ctrl

    then:
      properties:
        clocks:
          minItems: 2
        clock-names:
          items:
            - const: usb_ctrl
            - const: ddr
        phy-names:
          items:
            - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used
            - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
            - const: usb2-phy2 # USB2 PHY2 if USBOTG_C port is used

      required:
        - clock-names
  - if:
      properties:
        compatible:
          enum:
            - amlogic,meson-axg-usb-ctrl

    then:
      properties:
        phy-names:
          items:
            - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
        clocks:
          minItems: 2
        clock-names:
          items:
            - const: usb_ctrl
            - const: ddr
      required:
        - clock-names
  - if:
      properties:
        compatible:
          enum:
            - amlogic,meson-a1-usb-ctrl

    then:
      properties:
        phy-names:
          items:
            - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
        clocks:
          minItems: 3
        clock-names:
          items:
            - const: usb_ctrl
            - const: usb_bus
            - const: xtal_usb_ctrl
      required:
        - clock-names

examples:
  - |
    usb: usb@ffe09000 {
          compatible = "amlogic,meson-g12a-usb-ctrl";
          reg = <0xffe09000 0xa0>;
          interrupts = <16>;
          #address-cells = <1>;
          #size-cells = <1>;
          ranges;

          clocks = <&clkc_usb>;
          resets = <&reset_usb>;

          dr_mode = "otg";

          phys = <&usb2_phy0>, <&usb2_phy1>, <&usb3_phy0>;
          phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";

          dwc2: usb@ff400000 {
              compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
              reg = <0xff400000 0x40000>;
              interrupts = <31>;
              clocks = <&clkc_usb1>;
              clock-names = "otg";
              phys = <&usb2_phy1>;
              dr_mode = "peripheral";
              g-rx-fifo-size = <192>;
              g-np-tx-fifo-size = <128>;
              g-tx-fifo-size = <128 128 16 16 16>;
          };

          dwc3: usb@ff500000 {
              compatible = "snps,dwc3";
              reg = <0xff500000 0x100000>;
              interrupts = <30>;
              dr_mode = "host";
              snps,dis_u2_susphy_quirk;
              snps,quirk-frame-length-adjustment = <0x20>;
          };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/analogix,anx7411.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analogix ANX7411 Type-C controller bindings

maintainers:
  - Xin Ji <xji@analogixsemi.com>

properties:
  compatible:
    enum:
      - analogix,anx7411

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  connector:
    type: object
    $ref: ../connector/usb-connector.yaml
    unevaluatedProperties: false

    description:
      Properties for usb c connector.

    properties:
      compatible:
        const: usb-c-connector

      power-role: true

      data-role: true

      try-power-role: true

    required:
      - compatible

required:
  - compatible
  - reg
  - connector

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        typec@2c {
            compatible = "analogix,anx7411";
            reg = <0x2c>;
            interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
            interrupt-parent = <&gpio0>;

            typec_con: connector {
                compatible = "usb-c-connector";
                power-role = "dual";
                data-role = "dual";
                try-power-role = "source";

                ports {
                    #address-cells = <1>;
                    #size-cells = <0>;
                    port@0 {
                        reg = <0>;
                        typec_con_ep: endpoint {
                            remote-endpoint = <&usbotg_hs_ep>;
                        };
                    };
                };
            };
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 Facebook Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/aspeed,ast2600-udc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED USB 2.0 Device Controller

maintainers:
  - Neal Liu <neal_liu@aspeedtech.com>

description: |+
  The ASPEED USB 2.0 Device Controller implements 1 control endpoint and
  4 generic endpoints for AST260x.

  Supports independent DMA channel for each generic endpoint.
  Supports 32/256 stages descriptor mode for all generic endpoints.

properties:
  compatible:
    enum:
      - aspeed,ast2600-udc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/aspeed-clock.h>
    udc: usb@1e6a2000 {
        compatible = "aspeed,ast2600-udc";
        reg = <0x1e6a2000 0x300>;
        interrupts = <9>;
        clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usb2bd_default>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 Facebook Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/aspeed,usb-vhub.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED USB 2.0 Virtual Hub Controller

maintainers:
  - Benjamin Herrenschmidt <benh@kernel.crashing.org>

description: |+
  The ASPEED USB 2.0 Virtual Hub Controller implements 1 set of USB Hub
  register and several sets of Device and Endpoint registers to support
  the Virtual Hub's downstream USB devices.

  Supported number of devices and endpoints vary depending on hardware
  revisions. AST2400 and AST2500 Virtual Hub supports 5 downstream devices
  and 15 generic endpoints, while AST2600 Virtual Hub supports 7 downstream
  devices and 21 generic endpoints.

properties:
  compatible:
    enum:
      - aspeed,ast2400-usb-vhub
      - aspeed,ast2500-usb-vhub
      - aspeed,ast2600-usb-vhub

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  aspeed,vhub-downstream-ports:
    description: Number of downstream ports supported by the Virtual Hub
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 5
    minimum: 1
    maximum: 7

  aspeed,vhub-generic-endpoints:
    description: Number of generic endpoints supported by the Virtual Hub
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 15
    minimum: 1
    maximum: 21

  vhub-vendor-id:
    description: vhub Vendor ID
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 65535

  vhub-product-id:
    description: vhub Product ID
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 65535

  vhub-device-revision:
    description: vhub Device Revision in binary-coded decimal
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 65535

  vhub-strings:
    type: object
    additionalProperties: false

    properties:
      '#address-cells':
        const: 1

      '#size-cells':
        const: 0

    patternProperties:
      '^string@[0-9a-f]+$':
        type: object
        additionalProperties: false
        description: string descriptors of the specific language

        properties:
          reg:
            maxItems: 1
            description: 16-bit Language Identifier defined by USB-IF

          manufacturer:
            description: vhub manufacturer
            $ref: /schemas/types.yaml#/definitions/string

          product:
            description: vhub product name
            $ref: /schemas/types.yaml#/definitions/string

          serial-number:
            description: vhub device serial number
            $ref: /schemas/types.yaml#/definitions/string

required:
  - compatible
  - reg
  - clocks
  - interrupts
  - aspeed,vhub-downstream-ports
  - aspeed,vhub-generic-endpoints

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/aspeed-clock.h>
    vhub: usb-vhub@1e6a0000 {
            compatible = "aspeed,ast2500-usb-vhub";
            reg = <0x1e6a0000 0x300>;
            interrupts = <5>;
            clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
            aspeed,vhub-downstream-ports = <5>;
            aspeed,vhub-generic-endpoints = <15>;
            pinctrl-names = "default";
            pinctrl-0 = <&pinctrl_usb2ad_default>;

            vhub-vendor-id = <0x1d6b>;
            vhub-product-id = <0x0107>;
            vhub-device-revision = <0x0100>;
            vhub-strings {
                #address-cells = <1>;
                #size-cells = <0>;

                string@409 {
                        reg = <0x409>;
                        manufacturer = "ASPEED";
                        product = "USB Virtual Hub";
                        serial-number = "0000";
                };
            };
    };


code:
Atmel SOC USB controllers

OHCI

Required properties:
 - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
   used in host mode.
 - reg: Address and length of the register set for the device
 - interrupts: Should contain ohci interrupt
 - clocks: Should reference the peripheral, host and system clocks
 - clock-names: Should contain three strings
		"ohci_clk" for the peripheral clock
		"hclk" for the host clock
		"uhpck" for the system clock
 - num-ports: Number of ports.
 - atmel,vbus-gpio: If present, specifies a gpio that needs to be
   activated for the bus to be powered.
 - atmel,oc-gpio: If present, specifies a gpio that needs to be
   activated for the overcurrent detection.

usb0: ohci@500000 {
	compatible = "atmel,at91rm9200-ohci", "usb-ohci";
	reg = <0x00500000 0x100000>;
	clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
	clock-names = "ohci_clk", "hclk", "uhpck";
	interrupts = <20 4>;
	num-ports = <2>;
};

EHCI

Required properties:
 - compatible: Should be "atmel,at91sam9g45-ehci" for USB controllers
   used in host mode.
 - reg: Address and length of the register set for the device
 - interrupts: Should contain ehci interrupt
 - clocks: Should reference the peripheral and the UTMI clocks
 - clock-names: Should contain two strings
		"ehci_clk" for the peripheral clock
		"usb_clk" for the UTMI clock

Optional properties:
 - phy_type : For multi port host USB controllers, should be one of
   "utmi", or "hsic".

usb1: ehci@800000 {
	compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
	reg = <0x00800000 0x100000>;
	interrupts = <22 4>;
	clocks = <&utmi>, <&uhphs_clk>;
	clock-names = "usb_clk", "ehci_clk";
};

AT91 USB device controller

Required properties:
 - compatible: Should be one of the following
	       "atmel,at91rm9200-udc"
	       "atmel,at91sam9260-udc"
	       "atmel,at91sam9261-udc"
	       "atmel,at91sam9263-udc"
 - reg: Address and length of the register set for the device
 - interrupts: Should contain macb interrupt
 - clocks: Should reference the peripheral and the AHB clocks
 - clock-names: Should contain two strings
		"pclk" for the peripheral clock
		"hclk" for the AHB clock

Optional properties:
 - atmel,vbus-gpio: If present, specifies a gpio that needs to be
   activated for the bus to be powered.

usb1: gadget@fffa4000 {
	compatible = "atmel,at91rm9200-udc";
	reg = <0xfffa4000 0x4000>;
	interrupts = <10 4>;
	clocks = <&udc_clk>, <&udpck>;
	clock-names = "pclk", "hclk";
	atmel,vbus-gpio = <&pioC 5 0>;
};

Atmel High-Speed USB device controller

Required properties:
 - compatible: Should be one of the following
	       "atmel,at91sam9rl-udc"
	       "atmel,at91sam9g45-udc"
	       "atmel,sama5d3-udc"
	       "microchip,sam9x60-udc"
	       "microchip,lan9662-udc"
	       For "microchip,lan9662-udc" the fallback "atmel,sama5d3-udc"
	       is required.
 - reg: Address and length of the register set for the device
 - interrupts: Should contain usba interrupt
 - clocks: Should reference the peripheral and host clocks
 - clock-names: Should contain two strings
		"pclk" for the peripheral clock
		"hclk" for the host clock

Deprecated property:
 - ep childnode: To specify the number of endpoints and their properties.

Optional properties:
 - atmel,vbus-gpio: If present, specifies a gpio that allows to detect whether
   vbus is present (USB is connected).

Deprecated child node properties:
 - name: Name of the endpoint.
 - reg: Num of the endpoint.
 - atmel,fifo-size: Size of the fifo.
 - atmel,nb-banks: Number of banks.
 - atmel,can-dma: Boolean to specify if the endpoint support DMA.
 - atmel,can-isoc: Boolean to specify if the endpoint support ISOC.

usb2: gadget@fff78000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "atmel,at91sam9rl-udc";
	reg = <0x00600000 0x80000
	       0xfff78000 0x400>;
	interrupts = <27 4 0>;
	clocks = <&utmi>, <&udphs_clk>;
	clock-names = "hclk", "pclk";
	atmel,vbus-gpio = <&pioB 19 0>;
};


code:
* Broadcom USB controllers

Required properties:
- compatible: "brcm,bcm3384-ohci", "brcm,bcm3384-ehci"

  These currently use the generic-ohci and generic-ehci drivers.  On some
  systems, special handling may be needed in the following cases:

  - Restoring state after systemwide power save modes
  - Sharing PHYs with the USBD (UDC) hardware
  - Figuring out which controllers are disabled on ASIC bondout variants


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/brcm,bcm7445-ehci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom STB USB EHCI Controller

allOf:
  - $ref: "usb-hcd.yaml"

maintainers:
  - Al Cooper <alcooperx@gmail.com>

properties:
  compatible:
    const: brcm,bcm7445-ehci

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1
    description: Clock specifier for the EHCI clock

  clock-names:
    const: sw_usb

  phys:
    maxItems: 1

  phy-names:
    const: usbphy

required:
  - compatible
  - reg
  - interrupts
  - phys
  - clocks

additionalProperties: false

examples:
  - |
    usb@f0b00300 {
        compatible = "brcm,bcm7445-ehci";
        reg = <0xf0b00300 0xa8>;
        interrupts = <0x0 0x5a 0x0>;
        phys = <&usbphy_0 0x0>;
        phy-names = "usbphy";
        clocks = <&usb20>;
        clock-names = "sw_usb";
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/brcm,bdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom USB Device Controller (BDC)

maintainers:
  - Al Cooper <alcooperx@gmail.com>
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  compatible:
    items:
      - enum:
          - brcm,bdc-udc-v2
          - brcm,bdc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  phys:
    minItems: 1
    items:
      - description: USB 2.0 or 3.0 PHY
      - description: USB 3.0 PHY if there is a dedicated 2.0 PHY

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
        usb@f0b02000 {
                compatible = "brcm,bdc-udc-v2";
                reg = <0xf0b02000 0xfc4>;
                interrupts = <0x0 0x60 0x0>;
                phys = <&usbphy_0 0x0>;
                clocks = <&sw_usbd>;
        };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/brcm,usb-pinmap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom USB pin map Controller

maintainers:
  - Al Cooper <alcooperx@gmail.com>

properties:
  compatible:
    items:
      - const: brcm,usb-pinmap

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1
    description: Interrupt for signals mirrored to out-gpios.

  in-gpios:
    minItems: 1
    maxItems: 2
    description: Array of one or two GPIO pins used for input signals.

  brcm,in-functions:
    $ref: /schemas/types.yaml#/definitions/string-array
    description: Array of input signal names, one per gpio in in-gpios.

  brcm,in-masks:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: Array of enable and mask pairs, one per gpio in-gpios.

  out-gpios:
    maxItems: 1
    description: Array of one GPIO pin used for output signals.

  brcm,out-functions:
    $ref: /schemas/types.yaml#/definitions/string-array
    description: Array of output signal names, one per gpio in out-gpios.

  brcm,out-masks:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: Array of enable, value, changed and clear masks, one
      per gpio in out-gpios.

required:
  - compatible
  - reg

additionalProperties: false

dependencies:
  in-gpios: [ interrupts ]

examples:
  - |
    usb_pinmap: usb-pinmap@22000d0 {
        compatible = "brcm,usb-pinmap";
        reg = <0x22000d0 0x4>;
        in-gpios = <&gpio 18 0>, <&gpio 19 0>;
        brcm,in-functions = "VBUS", "PWRFLT";
        brcm,in-masks = <0x8000 0x40000 0x10000 0x80000>;
        out-gpios = <&gpio 20 0>;
        brcm,out-functions = "PWRON";
        brcm,out-masks = <0x20000 0x800000 0x400000 0x200000>;
        interrupts = <0x0 0xb2 0x4>;
    };

...