code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/socionext,uniphier-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext UniPhier SPI controller

description: |
  UniPhier SoCs have SCSSI which supports SPI single channel.

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
  - Keiji Hayashibara <hayashibara.keiji@socionext.com>

allOf:
  - $ref: spi-controller.yaml#

properties:
  "#address-cells": true
  "#size-cells": true

  compatible:
    const: socionext,uniphier-scssi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - resets
  - "#address-cells"
  - "#size-cells"

unevaluatedProperties: false

examples:
  - |
    spi0: spi@54006000 {
        compatible = "socionext,uniphier-scssi";
        reg = <0x54006000 0x100>;
        #address-cells = <1>;
        #size-cells = <0>;
        interrupts = <0 39 4>;
        clocks = <&peri_clk 11>;
        resets = <&peri_rst 11>;
    };


code:
* Marvell Armada 3700 SPI Controller

Required Properties:

- compatible: should be "marvell,armada-3700-spi"
- reg: physical base address of the controller and length of memory mapped
       region.
- interrupts: The interrupt number. The interrupt specifier format depends on
	      the interrupt controller and of its driver.
- clocks: Must contain the clock source, usually from the North Bridge clocks.
- num-cs: The number of chip selects that is supported by this SPI Controller
- #address-cells: should be 1.
- #size-cells: should be 0.

Example:

	spi0: spi@10600 {
		compatible = "marvell,armada-3700-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x10600 0x5d>;
		clocks = <&nb_perih_clk 7>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
		num-cs = <4>;
	};

repo_name: angery/linux


code:
Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller

Required properties:
- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
- reg: Base address and size of the controllers memory area
- clocks: phandle of the AHB clock.
- clock-names: has to be "ahb".
- #address-cells: <1>, as required by generic SPI binding.
- #size-cells: <0>, also as required by generic SPI binding.

Child nodes as per the generic SPI binding.

Example:

	spi@1f000000 {
		compatible = "qca,ar9132-spi", "qca,ar7100-spi";
		reg = <0x1f000000 0x10>;

		clocks = <&pll 2>;
		clock-names = "ahb";

		#address-cells = <1>;
		#size-cells = <0>;
	};


code:
Binding for Broadcom BCM6328 High Speed SPI controller

Required properties:
- compatible: must contain of "brcm,bcm6328-hsspi".
- reg: Base address and size of the controllers memory area.
- interrupts: Interrupt for the SPI block.
- clocks: phandles of the SPI clock and the PLL clock.
- clock-names: must be "hsspi", "pll".
- #address-cells: <1>, as required by generic SPI binding.
- #size-cells: <0>, also as required by generic SPI binding.

Optional properties:
- num-cs: some controllers have less than 8 cs signals. Defaults to 8
  if absent.

Child nodes as per the generic SPI binding.

Example:

	spi@10001000 {
		compatible = "brcm,bcm6328-hsspi";
		reg = <0x10001000 0x600>;

		interrupts = <29>;

		clocks = <&clkctl 9>, <&hsspi_pll>;
		clock-names = "hsspi", "pll";

		num-cs = <2>;

		#address-cells = <1>;
		#size-cells = <0>;
	};


code:
Binding for Broadcom BCM6348/BCM6358 SPI controller

Required properties:
- compatible: must contain one of "brcm,bcm6348-spi", "brcm,bcm6358-spi".
- reg: Base address and size of the controllers memory area.
- interrupts: Interrupt for the SPI block.
- clocks: phandle of the SPI clock.
- clock-names: has to be "spi".
- #address-cells: <1>, as required by generic SPI binding.
- #size-cells: <0>, also as required by generic SPI binding.

Optional properties:
- num-cs: some controllers have less than 8 cs signals. Defaults to 8
  if absent.

Child nodes as per the generic SPI binding.

Example:

	spi@10000800 {
		compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi";
		reg = <0x10000800 0x70c>;

		interrupts = <1>;

		clocks = <&clkctl 9>;
		clock-names = "spi";

		num-cs = <5>;

		#address-cells = <1>;
		#size-cells = <0>;
	};


code: This file has moved to spi-controller.yaml.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence SPI controller

maintainers:
  - Michal Simek <michal.simek@xilinx.com>

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    enum:
      - cdns,spi-r1p6
      - xlnx,zynq-spi-r1p6

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clock-names:
    items:
      - const: ref_clk
      - const: pclk

  clocks:
    maxItems: 2

  num-cs:
    description: |
      Number of chip selects used. If a decoder is used,
      this will be the number of chip selects after the
      decoder.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 4
    default: 4

  is-decoded-cs:
    description: |
      Flag to indicate whether decoder is used or not.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 0, 1 ]
    default: 0

required:
  - compatible
  - reg
  - interrupts
  - clock-names
  - clocks

unevaluatedProperties: false

examples:
  - |
    spi@e0007000 {
      compatible = "xlnx,zynq-spi-r1p6";
      clock-names = "ref_clk", "pclk";
      clocks = <&clkc 26>, <&clkc 35>;
      interrupt-parent = <&intc>;
      interrupts = <0 49 4>;
      num-cs = <4>;
      is-decoded-cs = <0>;
      reg = <0xe0007000 0x1000>;
    };
...


code:
Serial Peripheral Interface on Cirrus Logic CL-PS71xx, EP72xx, EP73xx

Required properties
- #address-cells: must be <1>
- #size-cells: must be <0>
- compatible: should include "cirrus,ep7209-spi"
- reg: Address and length of one register range
- interrupts: one interrupt line
- clocks: One entry, refers to the SPI bus clock
- cs-gpios: Specifies the gpio pins to be used for chipselects.
	    See: Documentation/devicetree/bindings/spi/spi-bus.txt

An additional register is present in the system controller,
which is assumed to be in the same device tree, with and marked
as compatible with "cirrus,ep7209-syscon3".

Example:

spi@80000500 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "cirrus,ep7209-spi";
	reg = <0x80000500 0x4>;
	interrupts = <15>;
	clocks = <&clks CLPS711X_CLK_SPI>;
};

syscon3: syscon@80002200 {
	compatible = "cirrus,ep7209-syscon3", "syscon";
	reg = <0x80002200 0x40>;
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SPI Controller Generic Binding

maintainers:
  - Mark Brown <broonie@kernel.org>

description: |
  SPI busses can be described with a node for the SPI controller device
  and a set of child nodes for each SPI slave on the bus. The system SPI
  controller may be described for use in SPI master mode or in SPI slave mode,
  but not for both at the same time.

properties:
  $nodename:
    pattern: "^spi(@.*|-[0-9a-f])*$"

  "#address-cells":
    enum: [0, 1]

  "#size-cells":
    const: 0

  cs-gpios:
    description: |
      GPIOs used as chip selects.
      If that property is used, the number of chip selects will be
      increased automatically with max(cs-gpios, hardware chip selects).

      So if, for example, the controller has 4 CS lines, and the
      cs-gpios looks like this
        cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;

      Then it should be configured so that num_chipselect = 4, with
      the following mapping
        cs0 : &gpio1 0 0
        cs1 : native
        cs2 : &gpio1 1 0
        cs3 : &gpio1 2 0

      The second flag of a gpio descriptor can be GPIO_ACTIVE_HIGH (0)
      or GPIO_ACTIVE_LOW(1). Legacy device trees often use 0.

      There is a special rule set for combining the second flag of an
      cs-gpio with the optional spi-cs-high flag for SPI slaves.

      Each table entry defines how the CS pin is to be physically
      driven (not considering potential gpio inversions by pinmux):

      device node     | cs-gpio       | CS pin state active | Note
      ================+===============+=====================+=====
      spi-cs-high     | -             | H                   |
      -               | -             | L                   |
      spi-cs-high     | ACTIVE_HIGH   | H                   |
      -               | ACTIVE_HIGH   | L                   | 1
      spi-cs-high     | ACTIVE_LOW    | H                   | 2
      -               | ACTIVE_LOW    | L                   |

      Notes:
      1) Should print a warning about polarity inversion.
         Here it would be wise to avoid and define the gpio as
         ACTIVE_LOW.
      2) Should print a warning about polarity inversion
         because ACTIVE_LOW is overridden by spi-cs-high.
         Should be generally avoided and be replaced by
         spi-cs-high + ACTIVE_HIGH.

  num-cs:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Total number of chip selects.

  spi-slave:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      The SPI controller acts as a slave, instead of a master.

  slave:
    type: object

    properties:
      compatible:
        description:
          Compatible of the SPI device.

    required:
      - compatible

patternProperties:
  "^.*@[0-9a-f]+$":
    type: object
    $ref: spi-peripheral-props.yaml

    properties:
      spi-3wire:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          The device requires 3-wire mode.

      spi-cpha:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          The device requires shifted clock phase (CPHA) mode.

      spi-cpol:
        $ref: /schemas/types.yaml#/definitions/flag
        description:
          The device requires inverse clock polarity (CPOL) mode.

    required:
      - compatible
      - reg

allOf:
  - if:
      not:
        required:
          - spi-slave
    then:
      properties:
        "#address-cells":
          const: 1
    else:
      properties:
        "#address-cells":
          const: 0

additionalProperties: true

examples:
  - |
    spi@80010000 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "fsl,imx28-spi";
        reg = <0x80010000 0x2000>;
        interrupts = <96>;
        dmas = <&dma_apbh 0>;
        dma-names = "rx-tx";

        display@0 {
            compatible = "lg,lg4573";
            spi-max-frequency = <1000000>;
            reg = <0>;
        };

        sensor@1 {
            compatible = "bosch,bme680";
            spi-max-frequency = <100000>;
            reg = <1>;
        };

        flash@2 {
            compatible = "jedec,spi-nor";
            spi-max-frequency = <50000000>;
            reg = <2>, <3>;
            stacked-memories = /bits/ 64 <0x10000000 0x10000000>;
        };
    };


code:
Davinci SPI controller device bindings

Links on DM:
Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

Required properties:
- #address-cells: number of cells required to define a chip select
	address on the SPI bus. Should be set to 1.
- #size-cells: should be zero.
- compatible:
	- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
	- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
	- "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
		family
- reg: Offset and length of SPI controller register space
- num-cs: Number of chip selects. This includes internal as well as
	GPIO chip selects.
- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
	IP to the interrupt controller within the SoC. Possible values
	are 0 and 1. Manual says one of the two possible interrupt
	lines can be tied to the interrupt controller. Set this
	based on a specific SoC configuration.
- interrupts: interrupt number mapped to CPU.
- clocks: spi clk phandle
          For 66AK2G this property should be set per binding,
          Documentation/devicetree/bindings/clock/ti,sci-clk.yaml

SoC-specific Required Properties:

The following are mandatory properties for Keystone 2 66AK2G SoCs only:

- power-domains:	Should contain a phandle to a PM domain provider node
			and an args specifier containing the SPI device id
			value. This property is as per the binding,

Optional:
- cs-gpios: gpio chip selects
	For example to have 3 internal CS and 2 GPIO CS, user could define
	cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
	where first three are internal CS and last two are GPIO CS.

Optional properties for slave devices:
SPI slave nodes can contain the following properties.
Not all SPI Peripherals from Texas Instruments support this.
Please check SPI peripheral documentation for a device before using these.

- ti,spi-wdelay : delay between transmission of words
	(SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module
	clock periods.

	delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period

Below is timing diagram which shows functional meaning of
"ti,spi-wdelay" parameter.

             +-+ +-+ +-+ +-+ +-+                           +-+ +-+ +-+
SPI_CLK      | | | | | | | | | |                           | | | | | |
  +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +-

SPI_SOMI/SIMO+-----------------+                           +-----------
  +----------+ word1           +---------------------------+word2
             +-----------------+                           +-----------
                                          WDELAY
                                <-------------------------->

Example of a NOR flash slave device (n25q032) connected to DaVinci
SPI controller device over the SPI bus.

spi0:spi@20bf0000 {
	#address-cells			= <1>;
	#size-cells			= <0>;
	compatible			= "ti,dm6446-spi";
	reg				= <0x20BF0000 0x1000>;
	num-cs				= <4>;
	ti,davinci-spi-intr-line	= <0>;
	interrupts			= <338>;
	clocks				= <&clkspi>;

	flash: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p32";
		spi-max-frequency = <25000000>;
		reg = <0>;
		ti,spi-wdelay = <8>;

		partition@0 {
			label = "u-boot-spl";
			reg = <0x0 0x80000>;
			read-only;
		};

		partition@1 {
			label = "test";
			reg = <0x80000 0x380000>;
		};
	};
};


code:
ARM Freescale DSPI controller

Required properties:
- compatible : must be one of:
	"fsl,vf610-dspi",
	"fsl,ls1021a-v1.0-dspi",
	"fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
	"fsl,ls1028a-dspi",
	"fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
	"fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
	"fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
	"fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"),
	"fsl,ls2085a-dspi",
	"fsl,lx2160a-dspi",
- reg : Offset and length of the register set for the device
- interrupts : Should contain SPI controller interrupt
- clocks: from common clock binding: handle to dspi clock.
- clock-names: from common clock binding: Shall be "dspi".
- pinctrl-0: pin control group to be used for this controller.
- pinctrl-names: must contain a "default" entry.
- spi-num-chipselects : the number of the chipselect signals.

Optional property:
- big-endian: If present the dspi device's registers are implemented
  in big endian mode.
- bus-num : the slave chip chipselect signal number.

Optional SPI slave node properties:
- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
  select and the start of clock signal, at the start of a transfer.
- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
  signal and deactivating chip select, at the end of a transfer.

Example:

dspi0@4002c000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,vf610-dspi";
	reg = <0x4002c000 0x1000>;
	interrupts = <0 67 0x04>;
	clocks = <&clks VF610_CLK_DSPI0>;
	clock-names = "dspi";
	spi-num-chipselects = <5>;
	bus-num = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi0_1>;
	big-endian;

	sflash: at26df081a@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "atmel,at26df081a";
		spi-max-frequency = <16000000>;
		spi-cpol;
		spi-cpha;
		reg = <0>;
		linux,modalias = "m25p80";
		modal = "at26df081a";
		fsl,spi-cs-sck-delay = <100>;
		fsl,spi-sck-cs-delay = <50>;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Low Power SPI (LPSPI) for i.MX

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

allOf:
  - $ref: "/schemas/spi/spi-controller.yaml#"

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx7ulp-spi
          - fsl,imx8qxp-spi
      - items:
          - enum:
              - fsl,imx8ulp-spi
              - fsl,imx93-spi
          - const: fsl,imx7ulp-spi
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: SoC SPI per clock
      - description: SoC SPI ipg clock

  clock-names:
    items:
      - const: per
      - const: ipg

  dmas:
    items:
      - description: TX DMA Channel
      - description: RX DMA Channel

  dma-names:
    items:
      - const: tx
      - const: rx

  fsl,spi-only-use-cs1-sel:
    description:
      spi common code does not support use of CS signals discontinuously.
      i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add
      this property to re-config the chipselect value in the LPSPI driver.
    type: boolean

  num-cs:
    description:
      number of chip selects.
    minimum: 1
    maximum: 2
    default: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx7ulp-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    spi@40290000 {
        compatible = "fsl,imx7ulp-spi";
        reg = <0x40290000 0x10000>;
        interrupt-parent = <&intc>;
        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clks IMX7ULP_CLK_LPSPI2>,
                 <&clks IMX7ULP_CLK_DUMMY>;
        clock-names = "per", "ipg";
        spi-slave;
        fsl,spi-only-use-cs1-sel;
        num-cs = <2>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SPI-GPIO devicetree bindings

maintainers:
  - Rob Herring <robh@kernel.org>

description:
  This represents a group of 3-n GPIO lines used for bit-banged SPI on
  dedicated GPIO lines.

allOf:
  - $ref: "/schemas/spi/spi-controller.yaml#"

properties:
  compatible:
    const: spi-gpio

  sck-gpios:
    description: GPIO spec for the SCK line to use
    maxItems: 1

  miso-gpios:
    description: GPIO spec for the MISO line to use
    maxItems: 1

  mosi-gpios:
    description: GPIO spec for the MOSI line to use
    maxItems: 1

  cs-gpios:
    description: GPIOs to use for chipselect lines.
      Not needed if num-chipselects = <0>.
    minItems: 1
    maxItems: 1024

  num-chipselects:
    description: Number of chipselect lines. Should be <0> if a single device
      with no chip select is connected.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  # Deprecated properties
  gpio-sck: false
  gpio-miso: false
  gpio-mosi: false

required:
  - compatible
  - num-chipselects
  - sck-gpios

unevaluatedProperties: false

examples:
  - |
    spi {
      compatible = "spi-gpio";
      #address-cells = <0x1>;
      #size-cells = <0x0>;

      sck-gpios = <&gpio 95 0>;
      miso-gpios = <&gpio 98 0>;
      mosi-gpios = <&gpio 97 0>;
      cs-gpios = <&gpio 125 0>;
      num-chipselects = <1>;

      /* clients */
    };

...


code:
IMG Synchronous Peripheral Flash Interface (SPFI) controller

Required properties:
- compatible: Must be "img,spfi".
- reg: Must contain the base address and length of the SPFI registers.
- interrupts: Must contain the SPFI interrupt.
- clocks: Must contain an entry for each entry in clock-names.
  See ../clock/clock-bindings.txt for details.
- clock-names: Must include the following entries:
  - spfi: SPI operating clock
  - sys: SPI system interface clock
- dmas: Must contain an entry for each entry in dma-names.
  See ../dma/dma.txt for details.
- dma-names: Must include the following entries:
  - rx
  - tx
- cs-gpios: Must specify the GPIOs used for chipselect lines.
- #address-cells: Must be 1.
- #size-cells: Must be 0.

Optional properties:
- img,supports-quad-mode: Should be set if the interface supports quad mode
  SPI transfers.
- spfi-max-frequency: Maximum speed supported by the spfi block.

Example:

spi@18100f00 {
	compatible = "img,spfi";
	reg = <0x18100f00 0x100>;
	interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&spi_clk>, <&system_clk>;
	clock-names = "spfi", "sys";
	dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
	dma-names = "rx", "tx";

	#address-cells = <1>;
	#size-cells = <0>;
};


code:
Lantiq Synchronous Serial Controller (SSC) SPI master driver

Required properties:
- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
  "intel,lgm-spi"
- #address-cells: see spi-bus.txt
- #size-cells: see spi-bus.txt
- reg: address and length of the spi master registers
- interrupts:
  For compatible "intel,lgm-ssc" - the common interrupt number for
  all of tx rx & err interrupts.
       or
  For rest of the compatibles, should contain the "spi_rx", "spi_tx" and
  "spi_err" interrupt.

Optional properties:
- clocks: spi clock phandle
- num-cs: see spi-bus.txt, set to 8 if unset
- base-cs: the number of the first chip select, set to 1 if unset.

Example:

spi: spi@e100800 {
	compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
	reg = <0xE100800 0x100>;
	interrupt-parent = <&icu0>;
	interrupts = <22 23 24>;
	interrupt-names = "spi_rx", "spi_tx", "spi_err";
	#address-cells = <1>;
	#size-cells = <1>;
	num-cs = <6>;
	base-cs = <1>;
};

ssc0: spi@e0800000 {
	compatible = "intel,lgm-spi";
	reg = <0xe0800000 0x400>;
	interrupt-parent = <&ioapic1>;
	interrupts = <35 1>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cgu0 LGM_CLK_NGI>, <&cgu0 LGM_GCLK_SSC0>;
	clock-names = "freq", "gate";
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-mux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic SPI Multiplexer

description: |
  This binding describes a SPI bus multiplexer to route the SPI chip select
  signals. This can be used when you need more devices than the SPI controller
  has chip selects available. An example setup is shown in ASCII art; the actual
  setting of the multiplexer to a channel needs to be done by a specific SPI mux
  driver.

        MOSI /--------------------------------+--------+--------+--------\
        MISO |/------------------------------+|-------+|-------+|-------\|
         SCL ||/----------------------------+||------+||------+||------\||
             |||                            |||      |||      |||      |||
      +------------+                        |||      |||      |||      |||
      | SoC  |||   |                      +-+++-+  +-+++-+  +-+++-+  +-+++-+
      |      |||   |                      | dev |  | dev |  | dev |  | dev |
      |   +--+++-+ | CS-X  +------+\      +--+--+  +--+--+  +--+--+  +--+--+
      |   | SPI  +-|-------+ Mux  |\\   CS-0 |        |        |        |
      |   +------+ |       +--+---+\\\-------/   CS-1 |        |        |
      |            |          |    \\\----------------/   CS-2 |        |
      |   +------+ |          |     \\-------------------------/   CS-3 |
      |   | ?    +-|----------/      \----------------------------------/
      |   +------+ |
      +------------+

allOf:
  - $ref: "/schemas/spi/spi-controller.yaml#"
  - $ref: "/schemas/spi/spi-peripheral-props.yaml#"

maintainers:
  - Chris Packham <chris.packham@alliedtelesis.co.nz>

properties:
  compatible:
    const: spi-mux

  mux-controls:
    maxItems: 1

required:
  - compatible
  - reg
  - spi-max-frequency
  - mux-controls

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    mux: mux-controller {
        compatible = "gpio-mux";
        #mux-control-cells = <0>;

        mux-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
    };

    spi {
        #address-cells = <1>;
        #size-cells = <0>;
        spi@0 {
            compatible = "spi-mux";
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <0>;
            spi-max-frequency = <100000000>;

            mux-controls = <&mux>;

            flash@0 {
                compatible = "jedec,spi-nor";
                reg = <0>;
                spi-max-frequency = <40000000>;
            };

            sensor@1 {
                compatible = "bosch,bme680";
                reg = <1>;
                spi-max-frequency = <10000000>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-nxp-fspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP Flex Serial Peripheral Interface (FSPI)

maintainers:
  - Han Xu <han.xu@nxp.com>
  - Kuldeep Singh <singh.kuldeep87k@gmail.com>

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    enum:
      - nxp,imx8dxl-fspi
      - nxp,imx8mm-fspi
      - nxp,imx8mp-fspi
      - nxp,imx8qxp-fspi
      - nxp,lx2160a-fspi

  reg:
    items:
      - description: registers address space
      - description: memory mapped address space

  reg-names:
    items:
      - const: fspi_base
      - const: fspi_mmap

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: SPI bus clock
      - description: SPI serial clock

  clock-names:
    items:
      - const: fspi_en
      - const: fspi

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/fsl,qoriq-clockgen.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        spi@20c0000 {
            compatible = "nxp,lx2160a-fspi";
            reg = <0x0 0x20c0000 0x0 0x100000>,
                  <0x0 0x20000000 0x0 0x10000000>;
            reg-names = "fspi_base", "fspi_mmap";
            interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>,
                     <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>;
            clock-names = "fspi_en", "fspi";
            #address-cells = <1>;
            #size-cells = <0>;

            flash@0 {
                compatible = "jedec,spi-nor";
                spi-max-frequency = <50000000>;
                reg = <0>;
                spi-rx-bus-width = <8>;
                spi-tx-bus-width = <8>;
            };
        };
    };


code:
Cavium, Inc. OCTEON SOC SPI master controller.

Required properties:
- compatible : "cavium,octeon-3010-spi"
- reg : The register base for the controller.
- interrupts : One interrupt, used by the controller.
- #address-cells : <1>, as required by generic SPI binding.
- #size-cells : <0>, also as required by generic SPI binding.

Child nodes as per the generic SPI binding.

Example:

	spi@1070000001000 {
		compatible = "cavium,octeon-3010-spi";
		reg = <0x10700 0x00001000 0x0 0x100>;
		interrupts = <0 58>;
		#address-cells = <1>;
		#size-cells = <0>;

		eeprom@0 {
			compatible = "st,m95256", "atmel,at25";
			reg = <0>;
			spi-max-frequency = <5000000>;
			spi-cpha;
			spi-cpol;

			pagesize = <64>;
			size = <32768>;
			address-width = <16>;
		};
	};


code:
Marvell Orion SPI device

Required properties:
- compatible : should be on of the following:
    - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
    - "marvell,armada-370-spi", for the Armada 370 SoCs
    - "marvell,armada-375-spi", for the Armada 375 SoCs
    - "marvell,armada-380-spi", for the Armada 38x SoCs
    - "marvell,armada-390-spi", for the Armada 39x SoCs
    - "marvell,armada-xp-spi", for the Armada XP SoCs
- reg : offset and length of the register set for the device.
	This property can optionally have additional entries to configure
	the SPI direct access mode that some of the Marvell SoCs support
	additionally to the normal indirect access (PIO) mode. The values
	for the MBus "target" and "attribute" are defined in the Marvell
	SoC "Functional Specifications" Manual in the chapter "Marvell
	Core Processor Address Decoding".
	The eight register sets following the control registers refer to
	chip-select lines 0 through 7 respectively.
- cell-index : Which of multiple SPI controllers is this.
- clocks : pointers to the reference clocks for this device, the first
	   one is the one used for the clock on the spi bus, the
	   second one is optional and is the clock used for the
	   functional part of the controller

Optional properties:
- interrupts : Is currently not used.
- clock-names : names of used clocks, mandatory if the second clock is
		used, the name must be "core", and "axi" (the latter
		is only for Armada 7K/8K).

Example:
       spi@10600 {
	       compatible = "marvell,orion-spi";
	       #address-cells = <1>;
	       #size-cells = <0>;
	       cell-index = <0>;
	       reg = <0x10600 0x28>;
	       interrupts = <23>;
       };

Example with SPI direct mode support (optionally):
	spi0: spi@10600 {
		compatible = "marvell,orion-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		cell-index = <0>;
		reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
		      <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
		      <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
		      <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
		      <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
		      <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
		      <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
		      <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
		      <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
		interrupts = <23>;
	};

To enable the direct mode, the board specific 'ranges' property in the
'soc' node needs to add the entries for the desired SPI controllers
and its chip-selects that are used in the direct mode instead of PIO
mode. Here an example for this (SPI controller 0, device 1 and SPI
controller 1, device 2 are used in direct mode. All other SPI device
are used in the default indirect (PIO) mode):
	soc {
		/*
		 * Enable the SPI direct access by configuring an entry
		 * here in the board-specific ranges property
		 */
		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000>,	/* internal regs */
			 <MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>,	/* BootROM       */
			 <MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000>,	/* SPI0-DEV1 */
			 <MBUS_ID(0x01, 0x9a) 0 0 0xf1110000 0x10000>;	/* SPI1-DEV2 */

For further information on the MBus bindings, please see the MBus
DT documentation:
Documentation/devicetree/bindings/bus/mvebu-mbus.txt


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Peripheral-specific properties for a SPI bus.

description:
  Many SPI controllers need to add properties to peripheral devices. They could
  be common properties like spi-max-frequency, spi-cpha, etc. or they could be
  controller specific like delay in clock or data lines, etc. These properties
  need to be defined in the peripheral node because they are per-peripheral and
  there can be multiple peripherals attached to a controller. All those
  properties are listed here. The controller specific properties should go in
  their own separate schema that should be referenced from here.

maintainers:
  - Mark Brown <broonie@kernel.org>

properties:
  reg:
    minItems: 1
    maxItems: 256
    items:
      items:
        - minimum: 0
          maximum: 256
    description:
      Chip select used by the device.

  spi-cs-high:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      The device requires the chip select active high.

  spi-lsb-first:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      The device requires the LSB first mode.

  spi-max-frequency:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Maximum SPI clocking speed of the device in Hz.

  spi-cs-setup-ns:
    description:
      Delay in nanosecods to be introduced by the controller after CS is
      asserted.

  spi-rx-bus-width:
    description:
      Bus width to the SPI bus used for read transfers.
      If 0 is provided, then no RX will be possible on this device.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2, 4, 8]
    default: 1

  spi-rx-delay-us:
    description:
      Delay, in microseconds, after a read transfer.

  rx-sample-delay-ns:
    description: SPI Rx sample delay offset, unit is nanoseconds.
      The delay from the default sample time before the actual
      sample of the rxd input signal occurs.

  spi-tx-bus-width:
    description:
      Bus width to the SPI bus used for write transfers.
      If 0 is provided, then no TX will be possible on this device.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2, 4, 8]
    default: 1

  spi-tx-delay-us:
    description:
      Delay, in microseconds, after a write transfer.

  stacked-memories:
    description: Several SPI memories can be wired in stacked mode.
      This basically means that either a device features several chip
      selects, or that different devices must be seen as a single
      bigger chip. This basically doubles (or more) the total address
      space with only a single additional wire, while still needing
      to repeat the commands when crossing a chip boundary. The size of
      each chip should be provided as members of the array.
    $ref: /schemas/types.yaml#/definitions/uint64-array
    minItems: 2
    maxItems: 4

  parallel-memories:
    description: Several SPI memories can be wired in parallel mode.
      The devices are physically on a different buses but will always
      act synchronously as each data word is spread across the
      different memories (eg. even bits are stored in one memory, odd
      bits in the other). This basically doubles the address space and
      the throughput while greatly complexifying the wiring because as
      many busses as devices must be wired. The size of each chip should
      be provided as members of the array.
    $ref: /schemas/types.yaml#/definitions/uint64-array
    minItems: 2
    maxItems: 4

# The controller specific properties go here.
allOf:
  - $ref: cdns,qspi-nor-peripheral-props.yaml#
  - $ref: samsung,spi-peripheral-props.yaml#
  - $ref: nvidia,tegra210-quad-peripheral-props.yaml#

additionalProperties: true


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-pl022.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM PL022 SPI controller

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

allOf:
  - $ref: "spi-controller.yaml#"

# We need a select here so we don't match all nodes with 'arm,primecell'
select:
  properties:
    compatible:
      contains:
        const: arm,pl022
  required:
    - compatible

properties:
  compatible:
    items:
      - const: arm,pl022
      - const: arm,primecell

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: sspclk
      - const: apb_pclk

  pl022,autosuspend-delay:
    description: delay in ms following transfer completion before the
      runtime power management system suspends the device. A setting of 0
      indicates no delay and the device will be suspended immediately.
    $ref: "/schemas/types.yaml#/definitions/uint32"

  pl022,rt:
    description: indicates the controller should run the message pump with realtime
      priority to minimise the transfer latency on the bus (boolean)
    type: boolean

  dmas:
    description:
      Two or more DMA channel specifiers following the convention outlined
      in bindings/dma/dma.txt
    minItems: 2
    maxItems: 32

  dma-names:
    description:
      There must be at least one channel named "tx" for transmit and named "rx"
      for receive.
    minItems: 2
    maxItems: 32
    additionalItems: true
    items:
      - const: rx
      - const: tx

  resets:
    maxItems: 1

patternProperties:
  "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
    type: object
    # SPI slave nodes must be children of the SPI master node and can
    # contain the following properties.
    properties:
      pl022,interface:
        description: SPI interface type
        $ref: "/schemas/types.yaml#/definitions/uint32"
        enum:
          - 0      # SPI
          - 1      # Texas Instruments Synchronous Serial Frame Format
          - 2      # Microwire (Half Duplex)

      pl022,com-mode:
        description: Specifies the transfer mode
        $ref: "/schemas/types.yaml#/definitions/uint32"
        enum:
          - 0      # interrupt mode
          - 1      # polling mode
          - 2      # DMA mode
        default: 1

      pl022,rx-level-trig:
        description: Rx FIFO watermark level
        $ref: "/schemas/types.yaml#/definitions/uint32"
        minimum: 0
        maximum: 4

      pl022,tx-level-trig:
        description: Tx FIFO watermark level
        $ref: "/schemas/types.yaml#/definitions/uint32"
        minimum: 0
        maximum: 4

      pl022,ctrl-len:
        description: Microwire interface - Control length
        $ref: "/schemas/types.yaml#/definitions/uint32"
        minimum: 0x03
        maximum: 0x1f

      pl022,wait-state:
        description: Microwire interface - Wait state
        $ref: "/schemas/types.yaml#/definitions/uint32"
        enum: [0, 1]

      pl022,duplex:
        description: Microwire interface - Full/Half duplex
        $ref: "/schemas/types.yaml#/definitions/uint32"
        enum: [0, 1]

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    spi@e0100000 {
      compatible = "arm,pl022", "arm,primecell";
      reg = <0xe0100000 0x1000>;
      #address-cells = <1>;
      #size-cells = <0>;
      interrupts = <0 31 0x4>;
      dmas = <&dma_controller 23 1>,
        <&dma_controller 24 0>;
      dma-names = "rx", "tx";

      flash@1 {
        compatible = "st,m25p80";
        reg = <1>;
        spi-max-frequency = <12000000>;
        spi-cpol;
        spi-cpha;
        pl022,interface = <0>;
        pl022,com-mode = <0x2>;
        pl022,rx-level-trig = <0>;
        pl022,tx-level-trig = <0>;
        pl022,ctrl-len = <0x11>;
        pl022,wait-state = <0>;
        pl022,duplex = <0>;
      };
    };
...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip SPI Controller

description:
  The Rockchip SPI controller is used to interface with various devices such
  as flash and display controllers using the SPI communication interface.

allOf:
  - $ref: "spi-controller.yaml#"

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

# Everything else is described in the common file
properties:
  compatible:
    oneOf:
      - const: rockchip,rk3036-spi
      - const: rockchip,rk3066-spi
      - const: rockchip,rk3228-spi
      - const: rockchip,rv1108-spi
      - items:
          - enum:
              - rockchip,px30-spi
              - rockchip,rk3128-spi
              - rockchip,rk3188-spi
              - rockchip,rk3288-spi
              - rockchip,rk3308-spi
              - rockchip,rk3328-spi
              - rockchip,rk3368-spi
              - rockchip,rk3399-spi
              - rockchip,rk3568-spi
              - rockchip,rk3588-spi
              - rockchip,rv1126-spi
          - const: rockchip,rk3066-spi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: transfer-clock
      - description: peripheral clock

  clock-names:
    items:
      - const: spiclk
      - const: apb_pclk

  dmas:
    items:
      - description: TX DMA Channel
      - description: RX DMA Channel

  dma-names:
    items:
      - const: tx
      - const: rx

  rx-sample-delay-ns:
    default: 0
    description:
      Nano seconds to delay after the SCLK edge before sampling Rx data
      (may need to be fine tuned for high capacitance lines).
      If not specified 0 will be used.

  pinctrl-names:
    minItems: 1
    items:
      - const: default
      - const: sleep
    description:
      Names for the pin configuration(s); may be "default" or "sleep",
      where the "sleep" configuration may describe the state
      the pins should be in during system suspend.

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3188-cru-common.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    spi0: spi@ff110000 {
      compatible = "rockchip,rk3066-spi";
      reg = <0xff110000 0x1000>;
      interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
      clock-names = "spiclk", "apb_pclk";
      dmas = <&pdma1 11>, <&pdma1 12>;
      dma-names = "tx", "rx";
      pinctrl-0 = <&spi1_pins>;
      pinctrl-1 = <&spi1_sleep>;
      pinctrl-names = "default", "sleep";
      rx-sample-delay-ns = <10>;
      #address-cells = <1>;
      #size-cells = <0>;
    };


code:
NXP SC18IS602/SCIS603

Required properties:
	- compatible : Should be one of
		"nxp,sc18is602"
		"nxp,sc18is602b"
		"nxp,sc18is603"
	- reg: I2C bus address

Optional properties:
	- clock-frequency : external oscillator clock frequency. If not
	  specified, the SC18IS602 default frequency (7372000) will be used.

The clock-frequency property is relevant and needed only if the chip has an
external oscillator (SC18IS603).

Example:

	sc18is603@28 {
		compatible = "nxp,sc18is603";
		reg = <0x28>;
		clock-frequency = <14744000>;
	}


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive SPI controller

maintainers:
  - Pragnesh Patel <pragnesh.patel@sifive.com>
  - Paul Walmsley  <paul.walmsley@sifive.com>
  - Palmer Dabbelt <palmer@sifive.com>

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    items:
      - enum:
          - sifive,fu540-c000-spi
          - sifive,fu740-c000-spi
      - const: sifive,spi0

    description:
      Should be "sifive,<chip>-spi" and "sifive,spi<version>".
      Supported compatible strings are -
      "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
      as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0"
      for the SiFive SPI v0 IP block with no chip integration tweaks.
      Please refer to sifive-blocks-ip-versioning.txt for details

      SPI RTL that corresponds to the IP block version numbers can be found here -
      https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi

  reg:
    minItems: 1
    items:
      - description: SPI registers region
      - description: Memory mapped flash region

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

    description:
      Must reference the frequency given to the controller

  sifive,fifo-depth:
    description:
      Depth of hardware queues; defaults to 8
    $ref: "/schemas/types.yaml#/definitions/uint32"
    enum: [8]
    default: 8

  sifive,max-bits-per-word:
    description:
      Maximum bits per word; defaults to 8
    $ref: "/schemas/types.yaml#/definitions/uint32"
    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
    default: 8

required:
  - compatible
  - reg
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    spi: spi@10040000 {
      compatible = "sifive,fu540-c000-spi", "sifive,spi0";
      reg = <0x10040000 0x1000>, <0x20000000 0x10000000>;
      interrupt-parent = <&plic>;
      interrupts = <51>;
      clocks = <&tlclk>;
      #address-cells = <1>;
      #size-cells = <0>;
      sifive,fifo-depth = <8>;
      sifive,max-bits-per-word = <8>;
    };

...


code:
Spreadtrum SPI Controller

Required properties:
- compatible: Should be "sprd,sc9860-spi".
- reg: Offset and length of SPI controller register space.
- interrupts: Should contain SPI interrupt.
- clock-names: Should contain following entries:
	"spi" for SPI clock,
	"source" for SPI source (parent) clock,
	"enable" for SPI module enable clock.
- clocks: List of clock input name strings sorted in the same order
	as the clock-names property.
- #address-cells: The number of cells required to define a chip select
	address on the SPI bus. Should be set to 1.
- #size-cells: Should be set to 0.

Optional properties:
dma-names: Should contain names of the SPI used DMA channel.
dmas: Should contain DMA channels and DMA slave ids which the SPI used
	sorted in the same order as the dma-names property.

Example:
spi0: spi@70a00000{
	compatible = "sprd,sc9860-spi";
	reg = <0 0x70a00000 0 0x1000>;
	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	clock-names = "spi", "source","enable";
	clocks = <&clk_spi0>, <&ext_26m>, <&clk_ap_apb_gates 5>;
	dma-names = "rx_chn", "tx_chn";
	dmas = <&apdma 11 11>, <&apdma 12 12>;
	#address-cells = <1>;
	#size-cells = <0>;
};


code:
STMicroelectronics SSC (SPI) Controller
---------------------------------------

Required properties:
- compatible	: "st,comms-ssc4-spi"
- reg		: Offset and length of the device's register set
- interrupts	: The interrupt specifier
- clock-names	: Must contain "ssc"
- clocks	: Must contain an entry for each name in clock-names
		    See ../clk/*
- pinctrl-names	: Uses "default", can use "sleep" if provided
		    See ../pinctrl/pinctrl-bindings.txt

Optional properties:
- cs-gpios	: List of GPIO chip selects
		    See ../spi/spi-bus.txt

Child nodes represent devices on the SPI bus
  See ../spi/spi-bus.txt

Example:
	spi@9840000 {
		compatible	= "st,comms-ssc4-spi";
		reg		= <0x9840000 0x110>;
		interrupts	= <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
		clocks		= <&clk_s_c0_flexgen CLK_EXT2F_A9>;
		clock-names	= "ssc";
		pinctrl-0	= <&pinctrl_spi0_default>;
		pinctrl-names	= "default";
		cs-gpios	= <&pio17 5 0>;
		#address-cells	= <1>;
		#size-cells	= <0>;

		st95hf@0{
			compatible		= "st,st95hf";
			reg			= <0>;
			spi-max-frequency	= <1000000>;
			interrupts		= <2 IRQ_TYPE_EDGE_FALLING>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd. 2021
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-sunplus-sp7021.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sunplus sp7021 SPI controller

allOf:
  - $ref: "spi-controller.yaml"

maintainers:
  - Li-hao Kuo <lhjeff911@gmail.com>

properties:
  compatible:
    enum:
      - sunplus,sp7021-spi

  reg:
    items:
      - description: the SPI master registers
      - description: the SPI slave registers

  reg-names:
    items:
      - const: master
      - const: slave

  interrupt-names:
    items:
      - const: dma_w
      - const: master_risc
      - const: slave_risc

  interrupts:
    minItems: 3

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names
  - clocks
  - resets
  - pinctrl-names
  - pinctrl-0

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    spi@9C002D80 {
        compatible = "sunplus,sp7021-spi";
        reg = <0x9C002D80 0x80>, <0x9C002E00 0x80>;
        reg-names = "master", "slave";
        interrupt-parent = <&intc>;
        interrupt-names = "dma_w",
                          "master_risc",
                          "slave_risc";
        interrupts = <144 IRQ_TYPE_LEVEL_HIGH>,
                     <146 IRQ_TYPE_LEVEL_HIGH>,
                     <145 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clkc 0x32>;
        resets = <&rstc 0x22>;
        pinctrl-names = "default";
        pinctrl-0 = <&pins_spi0>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-xilinx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx SPI controller

maintainers:
  - Michal Simek <michal.simek@xilinx.com>

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    enum:
      - xlnx,xps-spi-2.00.a
      - xlnx,xps-spi-2.00.b
      - xlnx,axi-quad-spi-1.00.a

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  xlnx,num-ss-bits:
    description: Number of chip selects used.
    minimum: 1
    maximum: 32

  xlnx,num-transfer-bits:
    description: Number of bits per transfer. This will be 8 if not specified.
    enum: [8, 16, 32]
    default: 8

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    spi0: spi@41e00000 {
      compatible = "xlnx,xps-spi-2.00.a";
      interrupt-parent = <&intc>;
      interrupts = <0 31 1>;
      reg = <0x41e00000 0x10000>;
      xlnx,num-ss-bits = <0x1>;
      xlnx,num-transfer-bits = <32>;
    };
...


code:
Cadence Xtensa XTFPGA platform SPI controller.

This simple SPI master controller is built into xtfpga bitstreams and is used
to control daughterboard audio codec.

Required properties:
- compatible: should be "cdns,xtfpga-spi".
- reg: physical base address of the controller and length of memory mapped
  region.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller

maintainers:
  - Michal Simek <michal.simek@xilinx.com>

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    enum:
      - xlnx,versal-qspi-1.0
      - xlnx,zynqmp-qspi-1.0

  reg:
    maxItems: 2

  interrupts:
    maxItems: 1

  clock-names:
    items:
      - const: ref_clk
      - const: pclk

  clocks:
    maxItems: 2

required:
  - compatible
  - reg
  - interrupts
  - clock-names
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      qspi: spi@ff0f0000 {
        compatible = "xlnx,zynqmp-qspi-1.0";
        clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
        clock-names = "ref_clk", "pclk";
        interrupts = <0 15 4>;
        interrupt-parent = <&gic>;
        reg = <0x0 0xff0f0000 0x0 0x1000>,
              <0x0 0xc0000000 0x0 0x8000000>;
      };
    };


code:
Altera SPI

Required properties:
- compatible : should be "ALTR,spi-1.0". <DEPRECATED>
- compatible : should be "altr,spi-1.0".


code:
OpenCores tiny SPI

Required properties:
- compatible : should be "opencores,tiny-spi-rtlsvn2".
- gpios : should specify GPIOs used for chipselect.
Optional properties:
- clock-frequency : input clock frequency to the core.
- baud-width: width, in bits, of the programmable divider used to scale
	the input clock to SCLK.

The clock-frequency and baud-width properties are needed only if the divider
is programmable. They are not needed if the divider is fixed.


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Spreadtrum ADI controller

maintainers:
  - Orson Zhai <orsonzhai@gmail.com>
  - Baolin Wang <baolin.wang7@gmail.com>
  - Chunyan Zhang <zhang.lyra@gmail.com>

description: |
  ADI is the abbreviation of Anolog-Digital interface, which is used to access
  analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
  framework for its hardware implementation is alike to SPI bus and its timing
  is compatile to SPI timing.

  ADI controller has 50 channels including 2 software read/write channels and
  48 hardware channels to access analog chip. For 2 software read/write channels,
  users should set ADI registers to access analog chip. For hardware channels,
  we can configure them to allow other hardware components to use it independently,
  which means we can just link one analog chip address to one hardware channel,
  then users can access the mapped analog chip address by this hardware channel
  triggered by hardware components instead of ADI software channels.

  Thus we introduce one property named "sprd,hw-channels" to configure hardware
  channels, the first value specifies the hardware channel id which is used to
  transfer data triggered by hardware automatically, and the second value specifies
  the analog chip address where user want to access by hardware components.

  Since we have multi-subsystems will use unique ADI to access analog chip, when
  one system is reading/writing data by ADI software channels, that should be under
  one hardware spinlock protection to prevent other systems from reading/writing
  data by ADI software channels at the same time, or two parallel routine of setting
  ADI registers will make ADI controller registers chaos to lead incorrect results.
  Then we need one hardware spinlock to synchronize between the multiple subsystems.

  The new version ADI controller supplies multiple master channels for different
  subsystem accessing, that means no need to add hardware spinlock to synchronize,
  thus change the hardware spinlock support to be optional to keep backward
  compatibility.

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

properties:
  compatible:
    enum:
      - sprd,sc9860-adi
      - sprd,sc9863-adi
      - sprd,ums512-adi

  reg:
    maxItems: 1

  hwlocks:
    maxItems: 1

  hwlock-names:
    const: adi

  sprd,hw-channels:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    description: A list of hardware channels
    minItems: 1
    maxItems: 48
    items:
      items:
        - description: The hardware channel id which is used to transfer data
            triggered by hardware automatically, channel id 0-1 are for software
            use, 2-49 are hardware channels.
          minimum: 2
          maximum: 49
        - description: The analog chip address where user want to access by
            hardware components.

required:
  - compatible
  - reg
  - '#address-cells'
  - '#size-cells'

unevaluatedProperties: false

examples:
  - |
    aon {
        #address-cells = <2>;
        #size-cells = <2>;

        adi_bus: spi@40030000 {
            compatible = "sprd,sc9860-adi";
            reg = <0 0x40030000 0 0x10000>;
            hwlocks = <&hwlock1 0>;
            hwlock-names = "adi";
            #address-cells = <1>;
            #size-cells = <0>;
            sprd,hw-channels = <30 0x8c20>;
        };
    };
...


code:
Microchip PIC32 Quad SPI controller
-----------------------------------
Required properties:
- compatible: Should be "microchip,pic32mzda-sqi".
- reg: Address and length of SQI controller register space.
- interrupts: Should contain SQI interrupt.
- clocks: Should contain phandle of two clocks in sequence, one that drives
          clock on SPI bus and other that drives SQI controller.
- clock-names: Should be "spi_ck" and "reg_ck" in order.

Example:
	sqi1: spi@1f8e2000 {
		compatible = "microchip,pic32mzda-sqi";
		reg = <0x1f8e2000 0x200>;
		clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>;
		clock-names = "spi_ck", "reg_ck";
		interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings

maintainers:
  - Christophe Kerello <christophe.kerello@foss.st.com>
  - Patrice Chotard <patrice.chotard@foss.st.com>

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    const: st,stm32f469-qspi

  reg:
    items:
      - description: registers
      - description: memory mapping

  reg-names:
    items:
      - const: qspi
      - const: qspi_mm

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  resets:
    maxItems: 1

  dmas:
    items:
      - description: tx DMA channel
      - description: rx DMA channel

  dma-names:
    items:
      - const: tx
      - const: rx

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    spi@58003000 {
      compatible = "st,stm32f469-qspi";
      reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
      reg-names = "qspi", "qspi_mm";
      interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
      dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
             <&mdma1 22 0x10 0x100008 0x0 0x0>;
      dma-names = "tx", "rx";
      clocks = <&rcc QSPI_K>;
      resets = <&rcc QSPI_R>;

      #address-cells = <1>;
      #size-cells = <0>;

      flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0>;
        spi-rx-bus-width = <4>;
        spi-max-frequency = <108000000>;
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/st,stm32-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 SPI Controller bindings

description: |
  The STM32 SPI controller is used to communicate with external devices using
  the Serial Peripheral Interface. It supports full-duplex, half-duplex and
  simplex synchronous serial communication with external devices. It supports
  from 4 to 32-bit data size.

maintainers:
  - Erwan Leray <erwan.leray@foss.st.com>
  - Fabrice Gasnier <fabrice.gasnier@foss.st.com>

allOf:
  - $ref: "spi-controller.yaml#"
  - if:
      properties:
        compatible:
          contains:
            const: st,stm32f4-spi

    then:
      properties:
        st,spi-midi-ns: false

properties:
  compatible:
    enum:
      - st,stm32f4-spi
      - st,stm32h7-spi

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  resets:
    maxItems: 1

  dmas:
    description: |
      DMA specifiers for tx and rx dma. DMA fifo mode must be used. See
      the STM32 DMA bindings Documentation/devicetree/bindings/dma/st,stm32-dma.yaml.
    items:
      - description: rx DMA channel
      - description: tx DMA channel

  dma-names:
    items:
      - const: rx
      - const: tx

patternProperties:
  "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
    type: object
    # SPI slave nodes must be children of the SPI master node and can
    # contain the following properties.
    properties:
      st,spi-midi-ns:
        description: |
          Only for STM32H7, (Master Inter-Data Idleness) minimum time
          delay in nanoseconds inserted between two consecutive data frames.

required:
  - compatible
  - reg
  - clocks
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    spi@4000b000 {
      #address-cells = <1>;
      #size-cells = <0>;
      compatible = "st,stm32h7-spi";
      reg = <0x4000b000 0x400>;
      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&rcc SPI2_K>;
      resets = <&rcc SPI2_R>;
      dmas = <&dmamux1 0 39 0x400 0x05>,
             <&dmamux1 1 40 0x400 0x05>;
      dma-names = "rx", "tx";
      cs-gpios = <&gpioa 11 0>;

    };

...


code:
TI QSPI controller.

Required properties:
- compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
- reg: Should contain QSPI registers location and length.
- reg-names: Should contain the resource reg names.
	- qspi_base: Qspi configuration register Address space
	- qspi_mmap: Memory mapped Address space
	- (optional) qspi_ctrlmod: Control module Address space
- interrupts: should contain the qspi interrupt number.
- #address-cells, #size-cells : Must be present if the device has sub-nodes
- ti,hwmods: Name of the hwmod associated to the QSPI

Recommended properties:
- spi-max-frequency: Definition as per
                     Documentation/devicetree/bindings/spi/spi-bus.txt

Optional properties:
- syscon-chipselects: Handle to system control region contains QSPI
		      chipselect register and offset of that register.

NOTE: TI QSPI controller requires different pinmux and IODelay
parameters for Mode-0 and Mode-3 operations, which needs to be set up by
the bootloader (U-Boot). Default configuration only supports Mode-0
operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be
specified in the slave nodes of TI QSPI controller without appropriate
modification to bootloader.

Example:

For am4372:
qspi: qspi@47900000 {
	compatible = "ti,am4372-qspi";
	reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
	reg-names = "qspi_base", "qspi_mmap";
	#address-cells = <1>;
	#size-cells = <0>;
	spi-max-frequency = <25000000>;
	ti,hwmods = "qspi";
};

For dra7xx:
qspi: qspi@4b300000 {
	compatible = "ti,dra7xxx-qspi";
	reg = <0x4b300000 0x100>,
	      <0x5c000000 0x4000000>,
	reg-names = "qspi_base", "qspi_mmap";
	syscon-chipselects = <&scm_conf 0x558>;
	#address-cells = <1>;
	#size-cells = <0>;
	spi-max-frequency = <48000000>;
	ti,hwmods = "qspi";
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Zynq QSPI controller

description:
  The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
  memory devices.

allOf:
  - $ref: "spi-controller.yaml#"

maintainers:
  - Michal Simek <michal.simek@xilinx.com>

# Everything else is described in the common file
properties:
  compatible:
    const: xlnx,zynq-qspi-1.0

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: reference clock
      - description: peripheral clock

  clock-names:
    items:
      - const: ref_clk
      - const: pclk

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    spi@e000d000 {
        compatible = "xlnx,zynq-qspi-1.0";
        reg = <0xe000d000 0x1000>;
        interrupt-parent = <&intc>;
        interrupts = <0 19 4>;
        clock-names = "ref_clk", "pclk";
        clocks = <&clkc 10>, <&clkc 43>;
        num-cs = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spmi/hisilicon,hisi-spmi-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: HiSilicon SPMI controller

maintainers:
  - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

description: |
  The HiSilicon SPMI BUS controller is found on some Kirin-based designs.
  It is a MIPI System Power Management (SPMI) controller.

  The PMIC part is provided by
  ./Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml.

allOf:
  - $ref: spmi.yaml#

properties:

  $nodename:
    pattern: "spmi@[0-9a-f]"

  compatible:
    const: hisilicon,kirin970-spmi-controller

  reg:
    maxItems: 1

  hisilicon,spmi-channel:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      number of the Kirin 970 SPMI channel where the SPMI devices are connected.

required:
  - compatible
  - reg
  - hisilicon,spmi-channel

patternProperties:
  "@[0-9a-f]$":
    type: object

    description: |
      PMIC properties, which are specific to the used SPMI PMIC device(s).
      When used in combination with HiSilicon 6421v600, the properties
      are documented at
      drivers/staging/hikey9xx/hisilicon,hi6421-spmi-pmic.yaml.

unevaluatedProperties: false

examples:
  - |
    bus {
      #address-cells = <2>;
      #size-cells = <2>;

      spmi: spmi@fff24000 {
        compatible = "hisilicon,kirin970-spmi-controller";
        #address-cells = <2>;
        #size-cells = <0>;
        reg = <0x0 0xfff24000 0x0 0x1000>;
        hisilicon,spmi-channel = <2>;

        pmic@0 {
          reg = <0 0>;
          /* pmic properties */
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spmi/mtk,spmi-mtk-pmif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek SPMI Controller

maintainers:
  - Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>

description: |+
  On MediaTek SoCs the PMIC is connected via SPMI and the controller allows
  for multiple SoCs to control a single SPMI master.

allOf:
  - $ref: "spmi.yaml"

properties:
  compatible:
    enum:
      - mediatek,mt6873-spmi
      - mediatek,mt8195-spmi

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: pmif
      - const: spmimst

  clocks:
    minItems: 3
    maxItems: 3

  clock-names:
    items:
      - const: pmif_sys_ck
      - const: pmif_tmr_ck
      - const: spmimst_clk_mux

  assigned-clocks:
    maxItems: 1

  assigned-clock-parents:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8192-clk.h>

    spmi: spmi@10027000 {
        compatible = "mediatek,mt6873-spmi";
        reg = <0x10027000 0xe00>,
              <0x10029000 0x100>;
        reg-names = "pmif", "spmimst";
        clocks = <&infracfg CLK_INFRA_PMIC_AP>,
                 <&infracfg CLK_INFRA_PMIC_TMR>,
                 <&topckgen CLK_TOP_SPMI_MST_SEL>;
        clock-names = "pmif_sys_ck",
                      "pmif_tmr_ck",
                      "spmimst_clk_mux";
        assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
        assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SPMI Controller (PMIC Arbiter)

maintainers:
  - Stephen Boyd <sboyd@kernel.org>

description: |
  The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
  controller with wrapping arbitration logic to allow for multiple on-chip
  devices to control a single SPMI master.

  The PMIC Arbiter can also act as an interrupt controller, providing interrupts
  to slave devices.

allOf:
  - $ref: spmi.yaml

properties:
  compatible:
    const: qcom,spmi-pmic-arb

  reg:
    oneOf:
      - items: # V1
          - description: core registers
          - description: interrupt controller registers
          - description: configuration registers
      - items: # V2
          - description: core registers
          - description: tx-channel per virtual slave regosters
          - description: rx-channel (called observer) per virtual slave registers
          - description: interrupt controller registers
          - description: configuration registers

  reg-names:
    oneOf:
      - items:
          - const: core
          - const: intr
          - const: cnfg
      - items:
          - const: core
          - const: chnls
          - const: obsrvr
          - const: intr
          - const: cnfg

  interrupts:
    maxItems: 1

  interrupt-names:
    const: periph_irq

  interrupt-controller: true

  '#address-cells': true

  '#interrupt-cells':
    const: 4
    description: |
      cell 1: slave ID for the requested interrupt (0-15)
      cell 2: peripheral ID for requested interrupt (0-255)
      cell 3: the requested peripheral interrupt (0-7)
      cell 4: interrupt flags indicating level-sense information,
              as defined in dt-bindings/interrupt-controller/irq.h

  '#size-cells': true

  qcom,ee:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 5
    description: >
      indicates the active Execution Environment identifier

  qcom,channel:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 5
    description: >
      which of the PMIC Arb provided channels to use for accesses

  qcom,bus-id:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 1
    description: >
      SPMI bus instance. only applicable to PMIC arbiter version 7 and beyond.
      Supported values, 0 = primary bus, 1 = secondary bus

required:
  - compatible
  - reg-names
  - qcom,ee
  - qcom,channel

unevaluatedProperties: false

examples:
  - |
    spmi@fc4cf000 {
        compatible = "qcom,spmi-pmic-arb";
        reg-names = "core", "intr", "cnfg";
        reg = <0xfc4cf000 0x1000>,
              <0xfc4cb000 0x1000>,
              <0xfc4ca000 0x1000>;

        interrupt-names = "periph_irq";
        interrupts = <0 190 0>;

        qcom,ee = <0>;
        qcom,channel = <0>;

        #address-cells = <2>;
        #size-cells = <0>;

        interrupt-controller;
        #interrupt-cells = <4>;

        qcom,bus-id = <0>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spmi/spmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: System Power Management Interface (SPMI) Controller

maintainers:
  - Stephen Boyd <sboyd@kernel.org>

description: |
  The System Power Management (SPMI) controller is a 2-wire bus defined
  by the MIPI Alliance for power management control to be used on SoC designs.

  SPMI controllers are modelled in device tree using a generic set of
  bindings defined here, plus any bus controller specific properties, if
  needed.

  Each SPMI controller has zero or more child nodes (up to 16 ones), each
  one representing an unique slave at the bus.

properties:
  $nodename:
    pattern: "^spmi@.*"

  "#address-cells":
    const: 2

  "#size-cells":
    const: 0

patternProperties:
  "@[0-9a-f]$":
    description: up to 16 child PMIC nodes
    type: object

    properties:
      reg:
        items:
          - minItems: 1
            items:
              - minimum: 0
                maximum: 0xf
              - enum: [ 0 ]
                description:
                  0 means user ID address. 1 is reserved for group ID
                  address.

    required:
      - reg

required:
  - reg

additionalProperties: true

examples:
  - |
    #include <dt-bindings/spmi/spmi.h>

    spmi@0 {
      reg = <0 0>;

      #address-cells = <2>;
      #size-cells = <0>;

      child@0 {
        reg = <0 SPMI_USID>;
      };

      child@7 {
        reg = <7 SPMI_USID>;
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 System Control

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description:
  The SRAM controller found on most Allwinner devices is represented
  by a regular node for the SRAM controller itself, with sub-nodes
  representing the SRAM handled by the SRAM controller.

properties:
  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  compatible:
    oneOf:
      - enum:
          - allwinner,sun4i-a10-sram-controller
          - allwinner,sun50i-a64-sram-controller
        deprecated: true
      - enum:
          - allwinner,sun4i-a10-system-control
          - allwinner,sun5i-a13-system-control
          - allwinner,sun8i-a23-system-control
          - allwinner,sun8i-h3-system-control
          - allwinner,sun20i-d1-system-control
          - allwinner,sun50i-a64-system-control
          - allwinner,sun50i-h5-system-control
          - allwinner,sun50i-h616-system-control
      - items:
          - enum:
              - allwinner,suniv-f1c100s-system-control
              - allwinner,sun7i-a20-system-control
              - allwinner,sun8i-r40-system-control
          - const: allwinner,sun4i-a10-system-control
      - items:
          - const: allwinner,sun8i-v3s-system-control
          - const: allwinner,sun8i-h3-system-control
      - items:
          - const: allwinner,sun50i-h6-system-control
          - const: allwinner,sun50i-a64-system-control

  reg:
    maxItems: 1

  ranges: true

patternProperties:
  "^sram@[a-z0-9]+":
    type: object

    properties:
      compatible:
        const: mmio-sram

    patternProperties:
      "^sram-section?@[a-f0-9]+$":
        type: object

        properties:
          compatible:
            oneOf:
              - const: allwinner,sun4i-a10-sram-a3-a4
              - const: allwinner,sun4i-a10-sram-c1
              - const: allwinner,sun4i-a10-sram-d
              - const: allwinner,sun50i-a64-sram-c
              - items:
                  - enum:
                      - allwinner,sun5i-a13-sram-a3-a4
                      - allwinner,sun7i-a20-sram-a3-a4
                  - const: allwinner,sun4i-a10-sram-a3-a4
              - items:
                  - enum:
                      - allwinner,sun5i-a13-sram-c1
                      - allwinner,sun7i-a20-sram-c1
                      - allwinner,sun8i-a23-sram-c1
                      - allwinner,sun8i-h3-sram-c1
                      - allwinner,sun8i-r40-sram-c1
                      - allwinner,sun50i-a64-sram-c1
                      - allwinner,sun50i-h5-sram-c1
                      - allwinner,sun50i-h6-sram-c1
                  - const: allwinner,sun4i-a10-sram-c1
              - items:
                  - enum:
                      - allwinner,suniv-f1c100s-sram-d
                      - allwinner,sun5i-a13-sram-d
                      - allwinner,sun7i-a20-sram-d
                  - const: allwinner,sun4i-a10-sram-d
              - items:
                  - const: allwinner,sun50i-h6-sram-c
                  - const: allwinner,sun50i-a64-sram-c

required:
  - "#address-cells"
  - "#size-cells"
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    system-control@1c00000 {
      compatible = "allwinner,sun4i-a10-system-control";
      reg = <0x01c00000 0x30>;
      #address-cells = <1>;
      #size-cells = <1>;
      ranges;

      sram_a: sram@0 {
        compatible = "mmio-sram";
        reg = <0x00000000 0xc000>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0x00000000 0xc000>;

        emac_sram: sram-section@8000 {
          compatible = "allwinner,sun4i-a10-sram-a3-a4";
          reg = <0x8000 0x4000>;
        };
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/sram/qcom,imem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm IMEM memory region

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description:
  Qualcomm IMEM is dedicated memory region for various debug features and DMA
  transactions.

properties:
  compatible:
    items:
      - enum:
          - qcom,apq8064-imem
          - qcom,msm8974-imem
          - qcom,qcs404-imem
          - qcom,sc7180-imem
          - qcom,sc7280-imem
          - qcom,sdm630-imem
          - qcom,sdm845-imem
          - qcom,sdx55-imem
          - qcom,sdx65-imem
      - const: syscon
      - const: simple-mfd

  reg:
    maxItems: 1

  ranges: true

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  reboot-mode:
    $ref: /schemas/power/reset/syscon-reboot-mode.yaml#

patternProperties:
  "^pil-reloc@[0-9a-f]+$":
    $ref: /schemas/remoteproc/qcom,pil-info.yaml#
    description: Peripheral image loader relocation region

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        sram@146bf000 {
            compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
            reg = <0 0x146bf000 0 0x1000>;
            ranges = <0 0 0x146bf000 0x1000>;

            #address-cells = <1>;
            #size-cells = <1>;

            pil-reloc@94c {
                compatible = "qcom,pil-reloc-info";
                reg = <0x94c 0xc8>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sram/qcom,ocmem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: On Chip Memory (OCMEM) that is present on some Qualcomm Snapdragon SoCs.

maintainers:
  - Brian Masney <masneyb@onstation.org>

description: |
  The On Chip Memory (OCMEM) is typically used by the GPU, camera/video, and
  audio components on some Snapdragon SoCs.

properties:
  compatible:
    const: qcom,msm8974-ocmem

  reg:
    items:
      - description: Control registers
      - description: OCMEM address range

  reg-names:
    items:
      - const: ctrl
      - const: mem

  clocks:
    items:
      - description: Core clock
      - description: Interface clock

  clock-names:
    items:
      - const: core
      - const: iface

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  ranges:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - '#address-cells'
  - '#size-cells'
  - ranges

additionalProperties: false

patternProperties:
  "-sram@[0-9a-f]+$":
    type: object
    description: A region of reserved memory.

    properties:
      reg:
        maxItems: 1

    required:
      - reg

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmcc.h>
    #include <dt-bindings/clock/qcom,mmcc-msm8974.h>

    sram@fdd00000 {
        compatible = "qcom,msm8974-ocmem";

        reg = <0xfdd00000 0x2000>,
              <0xfec00000 0x180000>;
        reg-names = "ctrl",
                    "mem";

        clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
                 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
        clock-names = "core",
                      "iface";

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0xfec00000 0x100000>;

        gmu-sram@0 {
            reg = <0x0 0x100000>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/sram/sram.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic on-chip SRAM

maintainers:
  - Rob Herring <robh@kernel.org>

description: |+
  Simple IO memory regions to be managed by the genalloc API.

  Each child of the sram node specifies a region of reserved memory. Each
  child node should use a 'reg' property to specify a specific range of
  reserved memory.

  Following the generic-names recommended practice, node names should
  reflect the purpose of the node. Unit address (@<address>) should be
  appended to the name.

properties:
  $nodename:
    pattern: "^sram(@.*)?"

  compatible:
    contains:
      enum:
        - mmio-sram
        - amlogic,meson-gxbb-sram
        - arm,juno-sram-ns
        - atmel,sama5d2-securam
        - nvidia,tegra186-sysram
        - nvidia,tegra194-sysram
        - nvidia,tegra234-sysram
        - qcom,rpm-msg-ram
        - rockchip,rk3288-pmu-sram

  reg:
    maxItems: 1

  clocks:
    maxItems: 1
    description:
      A list of phandle and clock specifier pair that controls the single
      SRAM clock.

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  ranges:
    maxItems: 1
    description:
      Should translate from local addresses within the sram to bus addresses.

  no-memory-wc:
    description:
      The flag indicating, that SRAM memory region has not to be remapped
      as write combining. WC is used by default.
    type: boolean

patternProperties:
  "^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$":
    type: object
    description:
      Each child of the sram node specifies a region of reserved memory.
    properties:
      compatible:
        description:
          Should contain a vendor specific string in the form
          <vendor>,[<device>-]<usage>
        contains:
          enum:
            - allwinner,sun4i-a10-sram-a3-a4
            - allwinner,sun4i-a10-sram-c1
            - allwinner,sun4i-a10-sram-d
            - allwinner,sun9i-a80-smp-sram
            - allwinner,sun50i-a64-sram-c
            - amlogic,meson8-ao-arc-sram
            - amlogic,meson8b-ao-arc-sram
            - amlogic,meson8-smp-sram
            - amlogic,meson8b-smp-sram
            - amlogic,meson-gxbb-scp-shmem
            - amlogic,meson-axg-scp-shmem
            - arm,juno-scp-shmem
            - arm,scmi-shmem
            - arm,scp-shmem
            - renesas,smp-sram
            - rockchip,rk3066-smp-sram
            - samsung,exynos4210-sysram
            - samsung,exynos4210-sysram-ns
            - socionext,milbeaut-smp-sram

      reg:
        description:
          IO mem address range, relative to the SRAM range.
        maxItems: 1

      pool:
        description:
          Indicates that the particular reserved SRAM area is addressable
          and in use by another device or devices.
        type: boolean

      export:
        description:
          Indicates that the reserved SRAM area may be accessed outside
          of the kernel, e.g. by bootloader or userspace.
        type: boolean

      protect-exec:
        description: |
          Same as 'pool' above but with the additional constraint that code
          will be run from the region and that the memory is maintained as
          read-only, executable during code execution. NOTE: This region must
          be page aligned on start and end in order to properly allow
          manipulation of the page attributes.
        type: boolean

      label:
        description:
          The name for the reserved partition, if omitted, the label is taken
          from the node name excluding the unit address.

    required:
      - reg

    additionalProperties: false

required:
  - compatible
  - reg

if:
  not:
    properties:
      compatible:
        contains:
          enum:
            - qcom,rpm-msg-ram
            - rockchip,rk3288-pmu-sram
then:
  required:
    - "#address-cells"
    - "#size-cells"
    - ranges

additionalProperties: false

examples:
  - |
    sram@5c000000 {
        compatible = "mmio-sram";
        reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0x5c000000 0x40000>;

        smp-sram@100 {
            reg = <0x100 0x50>;
        };

        device-sram@1000 {
            reg = <0x1000 0x1000>;
            pool;
        };

        exported-sram@20000 {
            reg = <0x20000 0x20000>;
            export;
        };
    };

  - |
    // Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
    // of the secondary cores. Once the core gets powered up it executes the
    // code that is residing at some specific location of the SYSRAM.
    //
    // Therefore reserved section sub-nodes have to be added to the mmio-sram
    // declaration. These nodes are of two types depending upon secure or
    // non-secure execution environment.
    sram@2020000 {
        compatible = "mmio-sram";
        reg = <0x02020000 0x54000>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0x02020000 0x54000>;

        smp-sram@0 {
            compatible = "samsung,exynos4210-sysram";
            reg = <0x0 0x1000>;
        };

        smp-sram@53000 {
            compatible = "samsung,exynos4210-sysram-ns";
            reg = <0x53000 0x1000>;
        };
    };

  - |
    // Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
    // Once the core gets powered up it executes the code that is residing at a
    // specific location.
    //
    // Therefore a reserved section sub-node has to be added to the mmio-sram
    // declaration.
    sram@d9000000 {
        compatible = "mmio-sram";
        reg = <0xd9000000 0x20000>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0xd9000000 0x20000>;

        smp-sram@1ff80 {
            compatible = "amlogic,meson8b-smp-sram";
            reg = <0x1ff80 0x8>;
        };
    };

  - |
    sram@e63c0000 {
        compatible = "mmio-sram";
        reg = <0xe63c0000 0x1000>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0xe63c0000 0x1000>;

        smp-sram@0 {
            compatible = "renesas,smp-sram";
            reg = <0 0x10>;
        };
    };

  - |
    sram@10080000 {
        compatible = "mmio-sram";
        reg = <0x10080000 0x10000>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        smp-sram@10080000 {
            compatible = "rockchip,rk3066-smp-sram";
            reg = <0x10080000 0x50>;
        };
    };

  - |
    // Rockchip's rk3288 SoC uses the sram of pmu to store the function of
    // resume from maskrom(the 1st level loader). This is a common use of
    // the "pmu-sram" because it keeps power even in low power states
    // in the system.
    sram@ff720000 {
      compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
      reg = <0xff720000 0x1000>;
    };

  - |
    // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
    // primary core (cpu0). Once the core gets powered up it checks if a magic
    // value is set at a specific location. If it is then the BROM will jump
    // to the software entry address, instead of executing a standard boot.
    //
    // Also there are no "secure-only" properties. The implementation should
    // check if this SRAM is usable first.
    sram@20000 {
        // 256 KiB secure SRAM at 0x20000
        compatible = "mmio-sram";
        reg = <0x00020000 0x40000>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0x00020000 0x40000>;

        smp-sram@1000 {
            // This is checked by BROM to determine if
            // cpu0 should jump to SMP entry vector
            compatible = "allwinner,sun9i-a80-smp-sram";
            reg = <0x1000 0x8>;
        };
    };

  - |
    sram@0 {
        compatible = "mmio-sram";
        reg = <0x0 0x10000>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0x0 0x10000>;

        smp-sram@f100 {
            compatible = "socionext,milbeaut-smp-sram";
            reg = <0xf100 0x20>;
        };
    };


code:
* ST SPEAr ADC device driver

Required properties:
- compatible: Should be "st,spear600-adc"
- reg: Address and length of the register set for the device
- interrupts: Should contain the ADC interrupt
- sampling-frequency: Default sampling frequency

Optional properties:
- vref-external: External voltage reference in milli-volts. If omitted
  the internal voltage reference will be used.
- average-samples: Number of samples to generate an average value. If
  omitted, single data conversion will be used.

Examples:

	adc: adc@d8200000 {
		compatible = "st,spear600-adc";
		reg = <0xd8200000 0x1000>;
		interrupt-parent = <&vic1>;
		interrupts = <6>;
		sampling-frequency = <5000000>;
		vref-external = <2500>;	/* 2.5V VRef */
	};


code:
.. SPDX-License-Identifier: GPL-2.0

==========================================
Submitting Devicetree (DT) binding patches
==========================================

I. For patch submitters
=======================

  0) Normal patch submission rules from
     Documentation/process/submitting-patches.rst applies.

  1) The Documentation/ and include/dt-bindings/ portion of the patch should
     be a separate patch. The preferred subject prefix for binding patches is::

       "dt-bindings: <binding dir>: ..."

     The 80 characters of the subject are precious. It is recommended to not
     use "Documentation" or "doc" because that is implied. All bindings are
     docs. Repeating "binding" again should also be avoided.

  2) DT binding files are written in DT schema format using json-schema
     vocabulary and YAML file format. The DT binding files must pass validation
     by running::

       make dt_binding_check

     See Documentation/devicetree/bindings/writing-schema.rst for more details
     about schema and tools setup.

  3) DT binding files should be dual licensed. The preferred license tag is
     (GPL-2.0-only OR BSD-2-Clause).

  4) Submit the entire series to the devicetree mailinglist at

       devicetree@vger.kernel.org

     and Cc: the DT maintainers. Use scripts/get_maintainer.pl to identify
     all of the DT maintainers.

  5) The Documentation/ portion of the patch should come in the series before
     the code implementing the binding.

  6) Any compatible strings used in a chip or board DTS file must be
     previously documented in the corresponding DT binding text file
     in Documentation/devicetree/bindings.  This rule applies even if
     the Linux device driver does not yet match on the compatible
     string.  [ checkpatch will emit warnings if this step is not
     followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864
     ("checkpatch: add DT compatible string documentation checks"). ]

  7) The wildcard "<chip>" may be used in compatible strings, as in
     the following example:

         - compatible: Must contain '"nvidia,<chip>-pcie",
           "nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ...

     As in the above example, the known values of "<chip>" should be
     documented if it is used.

  8) If a documented compatible string is not yet matched by the
     driver, the documentation should also include a compatible
     string that is matched by the driver (as in the "nvidia,tegra20-pcie"
     example above).

  9) Bindings are actively used by multiple projects other than the Linux
     Kernel, extra care and consideration may need to be taken when making changes
     to existing bindings.

II. For kernel maintainers
==========================

  1) If you aren't comfortable reviewing a given binding, reply to it and ask
     the devicetree maintainers for guidance.  This will help them prioritize
     which ones to review and which ones are ok to let go.

  2) For driver (not subsystem) bindings: If you are comfortable with the
     binding, and it hasn't received an Acked-by from the devicetree
     maintainers after a few weeks, go ahead and take it.

     For subsystem bindings (anything affecting more than a single device),
     getting a devicetree maintainer to review it is required.

  3) For a series going though multiple trees, the binding patch should be
     kept with the driver using the binding.

III. Notes
==========

  0) Please see Documentation/devicetree/bindings/ABI.rst for details
     regarding devicetree ABI.

  1) This document is intended as a general familiarization with the process as
     decided at the 2013 Kernel Summit.  When in doubt, the current word of the
     devicetree maintainers overrules this document.  In that situation, a patch
     updating this document would be appreciated.


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/allwinner,sun8i-a83t-ths.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner SUN8I Thermal Controller

maintainers:
  - Vasily Khoruzhick <anarsoul@gmail.com>
  - Yangtao Li <tiny.windzz@gmail.com>

properties:
  compatible:
    enum:
      - allwinner,sun8i-a83t-ths
      - allwinner,sun8i-h3-ths
      - allwinner,sun8i-r40-ths
      - allwinner,sun50i-a64-ths
      - allwinner,sun50i-a100-ths
      - allwinner,sun50i-h5-ths
      - allwinner,sun50i-h6-ths

  clocks:
    minItems: 1
    items:
      - description: Bus Clock
      - description: Module Clock

  clock-names:
    minItems: 1
    items:
      - const: bus
      - const: mod

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  resets:
    maxItems: 1

  nvmem-cells:
    maxItems: 1
    description: Calibration data for thermal sensors

  nvmem-cell-names:
    const: calibration

  # See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details
  "#thermal-sensor-cells":
    enum:
      - 0
      - 1

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun50i-a100-ths
              - allwinner,sun50i-h6-ths

    then:
      properties:
        clocks:
          maxItems: 1

        clock-names:
          maxItems: 1

    else:
      properties:
        clocks:
          minItems: 2

        clock-names:
          minItems: 2

  - if:
      properties:
        compatible:
          contains:
            const: allwinner,sun8i-h3-ths

    then:
      properties:
        "#thermal-sensor-cells":
          const: 0

    else:
      properties:
        "#thermal-sensor-cells":
          const: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - allwinner,sun8i-h3-ths
              - allwinner,sun8i-r40-ths
              - allwinner,sun50i-a64-ths
              - allwinner,sun50i-a100-ths
              - allwinner,sun50i-h5-ths
              - allwinner,sun50i-h6-ths

    then:
      required:
        - clocks
        - clock-names
        - resets

required:
  - compatible
  - reg
  - interrupts
  - '#thermal-sensor-cells'

additionalProperties: false

examples:
  - |
    thermal-sensor@1f04000 {
         compatible = "allwinner,sun8i-a83t-ths";
         reg = <0x01f04000 0x100>;
         interrupts = <0 31 0>;
         nvmem-cells = <&ths_calibration>;
         nvmem-cell-names = "calibration";
         #thermal-sensor-cells = <1>;
    };

  - |
    thermal-sensor@1c25000 {
         compatible = "allwinner,sun8i-h3-ths";
         reg = <0x01c25000 0x400>;
         clocks = <&ccu 0>, <&ccu 1>;
         clock-names = "bus", "mod";
         resets = <&ccu 2>;
         interrupts = <0 31 0>;
         nvmem-cells = <&ths_calibration>;
         nvmem-cell-names = "calibration";
         #thermal-sensor-cells = <0>;
    };

  - |
    thermal-sensor@5070400 {
         compatible = "allwinner,sun50i-h6-ths";
         reg = <0x05070400 0x100>;
         clocks = <&ccu 0>;
         clock-names = "bus";
         resets = <&ccu 2>;
         interrupts = <0 15 0>;
         nvmem-cells = <&ths_calibration>;
         nvmem-cell-names = "calibration";
         #thermal-sensor-cells = <1>;
    };

...


code:
Amazon's Annapurna Labs Thermal Sensor

Simple thermal device that allows temperature reading by a single MMIO
transaction.

Required properties:
- compatible: "amazon,al-thermal".
- reg: The physical base address and length of the sensor's registers.
- #thermal-sensor-cells: Must be 1. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.

Example:
	thermal: thermal {
		compatible = "amazon,al-thermal";
		reg = <0x0 0x05002860 0x0 0x1>;
		#thermal-sensor-cells = <0x1>;
	};

	thermal-zones {
		thermal-z0 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&thermal 0>;
			trips {
				critical {
					temperature = <105000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/amlogic,thermal.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic Thermal

maintainers:
  - Guillaume La Roque <glaroque@baylibre.com>

description: Binding for Amlogic Thermal

properties:
  compatible:
    items:
      - enum:
          - amlogic,g12a-cpu-thermal
          - amlogic,g12a-ddr-thermal
      - const: amlogic,g12a-thermal

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  amlogic,ao-secure:
    description: phandle to the ao-secure syscon
    $ref: '/schemas/types.yaml#/definitions/phandle'

  '#thermal-sensor-cells':
    const: 0

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - amlogic,ao-secure

additionalProperties: false

examples:
  - |
        cpu_temp: temperature-sensor@ff634800 {
                compatible = "amlogic,g12a-cpu-thermal",
                             "amlogic,g12a-thermal";
                reg = <0xff634800 0x50>;
                interrupts = <0x0 0x24 0x0>;
                clocks = <&clk 164>;
                #thermal-sensor-cells = <0>;
                amlogic,ao-secure = <&sec_AO>;
        };
...


code:
* Marvell Armada 370/375/380/XP thermal management

Required properties:

- compatible: Should be set to one of the following:
    * marvell,armada370-thermal
    * marvell,armada375-thermal
    * marvell,armada380-thermal
    * marvell,armadaxp-thermal
    * marvell,armada-ap806-thermal
    * marvell,armada-cp110-thermal

Note: these bindings are deprecated for AP806/CP110 and should instead
follow the rules described in:
Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt

- reg: Device's register space.
  Two entries are expected, see the examples below. The first one points
  to the status register (4B). The second one points to the control
  registers (8B).
  Note: The compatibles marvell,armada370-thermal,
  marvell,armada380-thermal, and marvell,armadaxp-thermal must point to
  "control MSB/control 1", with size of 4 (deprecated binding), or point
  to "control LSB/control 0" with size of 8 (current binding). All other
  compatibles must point to "control LSB/control 0" with size of 8.

Examples:

	/* Legacy bindings */
	thermal@d0018300 {
		compatible = "marvell,armada370-thermal";
		reg = <0xd0018300 0x4
		       0xd0018304 0x4>;
	};

	ap_thermal: thermal@6f8084 {
		compatible = "marvell,armada-ap806-thermal";
		reg = <0x6f808C 0x4>,
		      <0x6f8084 0x8>;
	};