code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for MACCHIATOBin Armada 8040 community board platform
 */

#include "armada-8040.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Marvell 8040 MACCHIATOBin";
	compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
			"marvell,armada-ap806-quad", "marvell,armada-ap806";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	aliases {
		ethernet0 = &cp0_eth0;
		ethernet1 = &cp1_eth0;
		ethernet2 = &cp1_eth1;
		ethernet3 = &cp1_eth2;
	};

	/* Regulator labels correspond with schematics */
	v_3_3: regulator-3-3v {
		compatible = "regulator-fixed";
		regulator-name = "v_3_3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		status = "okay";
	};

	v_vddo_h: regulator-1-8v {
		compatible = "regulator-fixed";
		regulator-name = "v_vddo_h";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		status = "okay";
	};

	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp0_xhci_vbus_pins>;
		regulator-name = "v_5v0_usb3_hst_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		status = "okay";
	};

	sfp_eth0: sfp-eth0 {
		/* CON15,16 - CPM lane 4 */
		compatible = "sff,sfp";
		i2c-bus = <&sfpp0_i2c>;
		los-gpios = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp1_sfpp0_pins>;
		maximum-power-milliwatt = <2000>;
	};

	sfp_eth1: sfp-eth1 {
		/* CON17,18 - CPS lane 4 */
		compatible = "sff,sfp";
		i2c-bus = <&sfpp1_i2c>;
		los-gpios = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
		maximum-power-milliwatt = <2000>;
	};

	sfp_eth3: sfp-eth3 {
		/* CON13,14 - CPS lane 5 */
		compatible = "sff,sfp";
		i2c-bus = <&sfp_1g_i2c>;
		los-gpios = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
		maximum-power-milliwatt = <2000>;
	};
};

&uart0 {
	status = "okay";
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
};

&ap_sdhci0 {
	bus-width = <8>;
	/*
	 * Not stable in HS modes - phy needs "more calibration", so add
	 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
	 */
	marvell,xenon-phy-slow-mode;
	no-1-8-v;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
	vqmmc-supply = <&v_vddo_h>;
};

&cp0_i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c0_pins>;
	status = "okay";
};

&cp0_i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c1_pins>;
	status = "okay";

	i2c-switch@70 {
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		sfpp0_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};
		sfpp1_i2c: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
		sfp_1g_i2c: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};
	};
};

/* J25 UART header */
&cp0_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_uart1_pins>;
	status = "okay";
};

&cp0_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_ge_mdio_pins>;
	status = "okay";

	ge_phy: ethernet-phy@0 {
		reg = <0>;
	};
};

&cp0_pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_pcie_pins>;
	num-lanes = <4>;
	num-viewport = <8>;
	reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
	ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
	phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
	       <&cp0_comphy2 0>, <&cp0_comphy3 0>;
	phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
		    "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
	status = "okay";
};

&cp0_pinctrl {
	cp0_ge_mdio_pins: ge-mdio-pins {
		marvell,pins = "mpp32", "mpp34";
		marvell,function = "ge";
	};
	cp0_i2c1_pins: i2c1-pins {
		marvell,pins = "mpp35", "mpp36";
		marvell,function = "i2c1";
	};
	cp0_i2c0_pins: i2c0-pins {
		marvell,pins = "mpp37", "mpp38";
		marvell,function = "i2c0";
	};
	cp0_uart1_pins: uart1-pins {
		marvell,pins = "mpp40", "mpp41";
		marvell,function = "uart1";
	};
	cp0_xhci_vbus_pins: xhci0-vbus-pins {
		marvell,pins = "mpp47";
		marvell,function = "gpio";
	};
	cp0_sfp_1g_pins: sfp-1g-pins {
		marvell,pins = "mpp51", "mpp53", "mpp54";
		marvell,function = "gpio";
	};
	cp0_pcie_pins: pcie-pins {
		marvell,pins = "mpp52";
		marvell,function = "gpio";
	};
	cp0_sdhci_pins: sdhci-pins {
		marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
			       "mpp60", "mpp61";
		marvell,function = "sdio";
	};
	cp0_sfpp1_pins: sfpp1-pins {
		marvell,pins = "mpp62";
		marvell,function = "gpio";
	};
};

&cp0_ethernet {
	status = "okay";
};

&cp0_eth0 {
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy4 0>;
};

&cp0_sata0 {
	status = "okay";

	/* CPM Lane 5 - U29 */
	sata-port@1 {
		phys = <&cp0_comphy5 1>;
		phy-names = "cp0-sata0-1-phy";
	};
};

&cp0_sdhci0 {
	/* U6 */
	broken-cd;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_sdhci_pins>;
	status = "okay";
	vqmmc-supply = <&v_3_3>;
};

&cp0_utmi {
	status = "okay";
};

&cp0_usb3_0 {
	/* J38? - USB2.0 only */
	phys = <&cp0_utmi0>;
	phy-names = "utmi";
	dr_mode = "host";
	status = "okay";
};

&cp0_usb3_1 {
	/* J38? - USB2.0 only */
	phys = <&cp0_utmi1>;
	phy-names = "utmi";
	dr_mode = "host";
	status = "okay";
};

&cp1_ethernet {
	status = "okay";
};

&cp1_eth0 {
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy4 0>;
};

&cp1_eth1 {
	/* CPS Lane 0 - J5 (Gigabit RJ45) */
	status = "okay";
	/* Network PHY */
	phy = <&ge_phy>;
	phy-mode = "sgmii";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy0 1>;
};

&cp1_eth2 {
	/* CPS Lane 5 */
	status = "okay";
	/* Network PHY */
	phy-mode = "2500base-x";
	managed = "in-band-status";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy5 2>;
	sfp = <&sfp_eth3>;
};

&cp1_pinctrl {
	cp1_sfpp1_pins: sfpp1-pins {
		marvell,pins = "mpp8", "mpp10", "mpp11";
		marvell,function = "gpio";
	};
	cp1_spi1_pins: spi1-pins {
		marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
		marvell,function = "spi1";
	};
	cp1_uart0_pins: uart0-pins {
		marvell,pins = "mpp6", "mpp7";
		marvell,function = "uart0";
	};
	cp1_sfp_1g_pins: sfp-1g-pins {
		marvell,pins = "mpp24";
		marvell,function = "gpio";
	};
	cp1_sfpp0_pins: sfpp0-pins {
		marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
		marvell,function = "gpio";
	};
};

/* J27 UART header */
&cp1_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_uart0_pins>;
	status = "okay";
};

&cp1_sata0 {
	status = "okay";

	/* CPS Lane 1 - U32 */
	sata-port@0 {
		phys = <&cp1_comphy1 0>;
		phy-names = "cp1-sata0-0-phy";
	};

	/* CPS Lane 3 - U31 */
	sata-port@1 {
		phys = <&cp1_comphy3 1>;
		phy-names = "cp1-sata0-1-phy";
	};
};

&cp1_spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_spi1_pins>;
	status = "okay";

	flash@0 {
		compatible = "st,w25q32";
		spi-max-frequency = <50000000>;
		reg = <0>;
	};
};

&cp1_comphy2 {
	cp1_usbh0_con: connector {
		compatible = "usb-a-connector";
		phy-supply = <&v_5v0_usb3_hst_vbus>;
	};
};

&cp1_utmi {
	status = "okay";
};

&cp1_usb3_0 {
	/* CPS Lane 2 - CON7 */
	phys = <&cp1_comphy2 0>, <&cp1_utmi0>;
	phy-names = "cp1-usb3h0-comphy", "utmi";
	dr_mode = "host";
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 * Copyright (C) 2020 Sartura Ltd.
 *
 * Device Tree file for IEI Puzzle-M801
 */

#include "armada-8040.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>

/ {
	model = "IEI-Puzzle-M801";
	compatible = "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806";

	aliases {
		ethernet0 = &cp0_eth0;
		ethernet1 = &cp1_eth0;
		ethernet2 = &cp0_eth1;
		ethernet3 = &cp0_eth2;
		ethernet4 = &cp1_eth1;
		ethernet5 = &cp1_eth2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	/* Regulator labels correspond with schematics */
	v_3_3: regulator-3-3v {
		compatible = "regulator-fixed";
		regulator-name = "v_3_3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		status = "okay";
	};

	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp0_xhci_vbus_pins>;
		regulator-name = "v_5v0_usb3_hst_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		status = "okay";
	};

	v_vddo_h: regulator-1-8v {
		compatible = "regulator-fixed";
		regulator-name = "v_vddo_h";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		status = "okay";
	};

	sfp_cp0_eth0: sfp-cp0-eth0 {
		compatible = "sff,sfp";
		i2c-bus = <&sfpplus0_i2c>;
		los-gpios = <&sfpplus_gpio 11 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&sfpplus_gpio 10 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&sfpplus_gpio 9 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&sfpplus_gpio 8 GPIO_ACTIVE_HIGH>;
		maximum-power-milliwatt = <3000>;
	};

	sfp_cp1_eth0: sfp-cp1-eth0 {
		compatible = "sff,sfp";
		i2c-bus = <&sfpplus1_i2c>;
		los-gpios = <&sfpplus_gpio 3 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&sfpplus_gpio 2 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&sfpplus_gpio 1 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&sfpplus_gpio 0 GPIO_ACTIVE_HIGH>;
		maximum-power-milliwatt = <3000>;
	};

	leds {
		compatible = "gpio-leds";
		status = "okay";
		pinctrl-0 = <&cp0_sfpplus_led_pins &cp1_sfpplus_led_pins>;
		pinctrl-names = "default";

		led-0 {
			/* SFP+ port 2: Activity */
			function = LED_FUNCTION_LAN;
			function-enumerator = <0>;
			gpios = <&cp1_gpio1 6 GPIO_ACTIVE_LOW>;
		};

		led-1 {
			/* SFP+ port 1: Activity */
			function = LED_FUNCTION_LAN;
			function-enumerator = <1>;
			gpios = <&cp1_gpio1 14 GPIO_ACTIVE_LOW>;
		};

		led-2 {
			/* SFP+ port 2: 10 Gbps indicator */
			function = LED_FUNCTION_LAN;
			function-enumerator = <2>;
			gpios = <&cp1_gpio1 7 GPIO_ACTIVE_LOW>;
		};

		led-3 {
			/* SFP+ port 2: 1 Gbps indicator */
			function = LED_FUNCTION_LAN;
			function-enumerator = <3>;
			gpios = <&cp1_gpio1 8 GPIO_ACTIVE_LOW>;
		};

		led-4 {
			/* SFP+ port 1: 10 Gbps indicator */
			function = LED_FUNCTION_LAN;
			function-enumerator = <4>;
			gpios = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
		};

		led-5 {
			/* SFP+ port 1: 1 Gbps indicator */
			function = LED_FUNCTION_LAN;
			function-enumerator = <5>;
			gpios = <&cp1_gpio1 31 GPIO_ACTIVE_LOW>;
		};

		led-6 {
			function = LED_FUNCTION_DISK;
			linux,default-trigger = "disk-activity";
			gpios = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
		};

	};
};

&ap_sdhci0 {
	bus-width = <8>;
	/*
	 * Not stable in HS modes - phy needs "more calibration", so add
	 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
	 */
	marvell,xenon-phy-slow-mode;
	no-1-8-v;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
	vqmmc-supply = <&v_vddo_h>;
};

&ap_thermal_cpu1 {
	trips {
		cpu_active: cpu-active {
			temperature = <44000>;
			hysteresis = <2000>;
			type = "active";
		};
	};
	cooling-maps {
		fan-map {
			trip = <&cpu_active>;
			cooling-device = <&chassis_fan_group0 64 THERMAL_NO_LIMIT>,
					<&chassis_fan_group1 64 THERMAL_NO_LIMIT>;
		};
	};
};

&i2c0 {
	clock-frequency = <100000>;
	status = "okay";

	rtc@32 {
		compatible = "epson,rx8010";
		reg = <0x32>;
	};
};

&spi0 {
	status = "okay";
	flash@0 {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-max-frequency = <20000000>;
		partition@u-boot {
			label = "u-boot";
			reg = <0x00000000 0x001f0000>;
		};
		partition@u-boot-env {
			label = "u-boot-env";
			reg = <0x001f0000 0x00010000>;
		};
		partition@ubi1 {
			label = "ubi1";
			reg = <0x00200000 0x03f00000>;
		};
		partition@ubi2 {
			label = "ubi2";
			reg = <0x04100000 0x03f00000>;
		};
	};
};

&uart0 {
	status = "okay";
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
};

&uart1 {
	status = "okay";
	/* IEI WT61P803 PUZZLE MCU Controller */
	mcu {
		compatible = "iei,wt61p803-puzzle";
		current-speed = <115200>;
		enable-beep;

		leds {
			compatible = "iei,wt61p803-puzzle-leds";
			#address-cells = <1>;
			#size-cells = <0>;

			led@0 {
				reg = <0>;
				function = LED_FUNCTION_POWER;
				color = <LED_COLOR_ID_BLUE>;
			};
		};

		hwmon {
			compatible = "iei,wt61p803-puzzle-hwmon";
			#address-cells = <1>;
			#size-cells = <0>;

			chassis_fan_group0:fan-group@0 {
				#cooling-cells = <2>;
				reg = <0x00>;
				cooling-levels = <64 102 170 230 250>;
			};

			chassis_fan_group1:fan-group@1 {
				#cooling-cells = <2>;
				reg = <0x01>;
				cooling-levels = <64 102 170 230 250>;
			};
		};
	};
};

&cp0_rtc {
	status = "disabled";
};

&cp0_i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c0_pins>;
	status = "okay";

	sfpplus_gpio: gpio@21 {
		compatible = "nxp,pca9555";
		reg = <0x21>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	eeprom@54 {
		compatible = "atmel,24c04";
		reg = <0x54>;
	};
};

&cp0_i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c1_pins>;
	status = "okay";

	i2c-switch@70 {
		compatible = "nxp,pca9544";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		sfpplus0_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		sfpplus1_i2c: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
	};
};

&cp0_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_uart1_pins>;
	status = "okay";
};

&cp0_mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	status = "okay";

	ge_phy2: ethernet-phy@0 {
		reg = <0>;
	};

	ge_phy3: ethernet-phy@1 {
		reg = <1>;
	};
};

&cp0_pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_pcie_pins>;
	num-lanes = <1>;
	num-viewport = <8>;
	reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
	ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
	phys = <&cp0_comphy0 0>;
	phy-names = "cp0-pcie0-x1-phy";
	status = "okay";
};

&cp0_pinctrl {
	cp0_ge_mdio_pins: ge-mdio-pins {
		marvell,pins = "mpp32", "mpp34";
		marvell,function = "ge";
	};
	cp0_i2c1_pins: i2c1-pins {
		marvell,pins = "mpp35", "mpp36";
		marvell,function = "i2c1";
	};
	cp0_i2c0_pins: i2c0-pins {
		marvell,pins = "mpp37", "mpp38";
		marvell,function = "i2c0";
	};
	cp0_uart1_pins: uart1-pins {
		marvell,pins = "mpp40", "mpp41";
		marvell,function = "uart1";
	};
	cp0_xhci_vbus_pins: xhci0-vbus-pins {
		marvell,pins = "mpp47";
		marvell,function = "gpio";
	};
	cp0_pcie_pins: pcie-pins {
		marvell,pins = "mpp52";
		marvell,function = "gpio";
	};
	cp0_sdhci_pins: sdhci-pins {
		marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
			       "mpp60", "mpp61";
		marvell,function = "sdio";
	};
	cp0_sfpplus_led_pins: sfpplus-led-pins {
		marvell,pins = "mpp54";
		marvell,function = "gpio";
	};
};

&cp0_ethernet {
	status = "okay";
};

&cp0_eth0 {
	status = "okay";
	phy-mode = "10gbase-r";
	phys = <&cp0_comphy4 0>;
	local-mac-address = [ae 00 00 00 ff 00];
	sfp = <&sfp_cp0_eth0>;
	managed = "in-band-status";
};

&cp0_eth1 {
	status = "okay";
	phy = <&ge_phy2>;
	phy-mode = "sgmii";
	local-mac-address = [ae 00 00 00 ff 01];
	phys = <&cp0_comphy3 1>;
};

&cp0_eth2 {
	status = "okay";
	phy-mode = "sgmii";
	phys = <&cp0_comphy1 2>;
	local-mac-address = [ae 00 00 00 ff 02];
	phy = <&ge_phy3>;
};

&cp0_sata0 {
	status = "okay";

	sata-port@0 {
		phys = <&cp0_comphy2 0>;
		phy-names = "cp0-sata0-0-phy";
	};

	sata-port@1 {
		phys = <&cp0_comphy5 1>;
		phy-names = "cp0-sata0-1-phy";
	};
};

&cp0_sdhci0 {
	broken-cd;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_sdhci_pins>;
	status = "okay";
	vqmmc-supply = <&v_3_3>;
};

&cp0_usb3_0 {
	status = "okay";
};

&cp0_usb3_1 {
	status = "okay";
};

&cp1_i2c0 {
	clock-frequency = <100000>;
	status = "disabled";
};

&cp1_i2c1 {
	clock-frequency = <100000>;
	status = "disabled";
};

&cp1_rtc {
	status = "disabled";
};

&cp1_ethernet {
	status = "okay";
};

&cp1_eth0 {
	status = "okay";
	phy-mode = "10gbase-r";
	phys = <&cp1_comphy4 0>;
	local-mac-address = [ae 00 00 00 ff 03];
	sfp = <&sfp_cp1_eth0>;
	managed = "in-band-status";
};

&cp1_eth1 {
	status = "okay";
	phy = <&ge_phy4>;
	phy-mode = "sgmii";
	local-mac-address = [ae 00 00 00 ff 04];
	phys = <&cp1_comphy3 1>;
};

&cp1_eth2 {
	status = "okay";
	phy-mode = "sgmii";
	local-mac-address = [ae 00 00 00 ff 05];
	phys = <&cp1_comphy5 2>;
	phy = <&ge_phy5>;
};

&cp1_pinctrl {
	cp1_sfpplus_led_pins: sfpplus-led-pins {
		marvell,pins = "mpp6", "mpp7", "mpp8", "mpp10", "mpp14", "mpp31";
		marvell,function = "gpio";
	};
};

&cp1_uart0 {
	status = "disabled";
};

&cp1_comphy2 {
	cp1_usbh0_con: connector {
		compatible = "usb-a-connector";
		phy-supply = <&v_5v0_usb3_hst_vbus>;
	};
};

&cp1_usb3_0 {
	phys = <&cp1_comphy2 0>;
	phy-names = "cp1-usb3h0-comphy";
	status = "okay";
};

&cp1_mdio {
	#address-cells = <1>;
	#size-cells = <0>;

	status = "okay";

	ge_phy4: ethernet-phy@1 {
		reg = <1>;
	};
	ge_phy5: ethernet-phy@0 {
		reg = <0>;
	};
};

&cp1_pcie0 {
	num-lanes = <2>;
	phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
	phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
	status = "okay";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and
 * two CP110.
 */

#include "armada-ap806-quad.dtsi"
#include "armada-80x0.dtsi"

/ {
	model = "Marvell Armada 8040";
	compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
		     "marvell,armada-ap806";
};

&cp0_pcie0 {
	iommu-map =
		<0x0   &smmu 0x480 0x20>,
		<0x100 &smmu 0x4a0 0x20>,
		<0x200 &smmu 0x4c0 0x20>;
	iommu-map-mask = <0x031f>;
};

/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
 * in CP master is not connected (by package) to the oscillator. So
 * disable it. However, the RTC clock in CP slave is connected to the
 * oscillator so this one is let enabled.
 */
&cp0_rtc {
	status = "disabled";
};

&cp0_sata0 {
	iommus = <&smmu 0x444>;
};

&cp0_sdhci0 {
	iommus = <&smmu 0x445>;
};

&cp0_usb3_0 {
	iommus = <&smmu 0x440>;
};

&cp0_usb3_1 {
	iommus = <&smmu 0x441>;
};

&cp1_sata0 {
	iommus = <&smmu 0x454>;
};

&cp1_usb3_0 {
	iommus = <&smmu 0x450>;
};

&cp1_usb3_1 {
	iommus = <&smmu 0x451>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2017 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada-8080 Development board platform
 */

#include "armada-8080.dtsi"

/ {
	model = "Marvell 8080 board";
	compatible = "marvell,armada-8080-db", "marvell,armada-8080",
		     "marvell,armada-ap810-octa", "marvell,armada-ap810";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};
};

&uart0_ap0 {
	clock-frequency = <384000>;
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2017 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada-8080 SoC, made of an AP810 OCTA.
 */

#include "armada-ap810-ap0-octa-core.dtsi"

/ {
	model = "Marvell 8080 board";
	compatible = "marvell,armada-8080", "marvell,armada-ap810-octa",
				"marvell,armada-ap810";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2017 Marvell Technology Group Ltd.
 *
 * Device Tree file for the Armada 80x0 SoC family
 */

/ {
	aliases {
		gpio1 = &cp1_gpio1;
		gpio2 = &cp0_gpio2;
		spi1 = &cp0_spi0;
		spi2 = &cp0_spi1;
		spi3 = &cp1_spi0;
		spi4 = &cp1_spi1;
	};
};

/*
 * Instantiate the master CP110
 */
#define CP11X_NAME		cp0
#define CP11X_BASE		f2000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE	f2600000
#define CP11X_PCIE1_BASE	f2620000
#define CP11X_PCIE2_BASE	f2640000

#include "armada-cp110.dtsi"

#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE

/*
 * Instantiate the slave CP110
 */
#define CP11X_NAME		cp1
#define CP11X_BASE		f4000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE	f4600000
#define CP11X_PCIE1_BASE	f4620000
#define CP11X_PCIE2_BASE	f4640000

#include "armada-cp110.dtsi"

#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE

/* The 80x0 has two CP blocks, but uses only one block from each. */
&cp1_gpio1 {
	status = "okay";
};

&cp0_gpio2 {
	status = "okay";
};

&cp0_syscon0 {
	cp0_pinctrl: pinctrl {
		compatible = "marvell,armada-8k-cpm-pinctrl";
	};
};

&cp1_syscon0 {
	cp1_pinctrl: pinctrl {
		compatible = "marvell,armada-8k-cps-pinctrl";

		nand_pins: nand-pins {
			marvell,pins =
			"mpp0", "mpp1", "mpp2", "mpp3",
			"mpp4", "mpp5", "mpp6", "mpp7",
			"mpp8", "mpp9", "mpp10", "mpp11",
			"mpp15", "mpp16", "mpp17", "mpp18",
			"mpp19", "mpp20", "mpp21", "mpp22",
			"mpp23", "mpp24", "mpp25", "mpp26",
			"mpp27";
			marvell,function = "dev";
		};

		nand_rb: nand-rb {
			marvell,pins = "mpp13", "mpp12";
			marvell,function = "nf";
		};
	};
};

&cp1_crypto {
	/*
	 * The cryptographic engine found on the cp110
	 * master is enabled by default at the SoC
	 * level. Because it is not possible as of now
	 * to enable two cryptographic engines in
	 * parallel, disable this one by default.
	 */
	status = "disabled";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada AP806.
 */

#include "armada-ap806.dtsi"

/ {
	model = "Marvell Armada AP806 Dual";
	compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x000>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 0>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x001>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 0>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2>;
		};

		l2: l2-cache {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-level = <2>;
		};
	};

	thermal-zones {
		/delete-node/ ap-thermal-cpu2;
		/delete-node/ ap-thermal-cpu3;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada AP806.
 */

#include "armada-ap806.dtsi"

/ {
	model = "Marvell Armada AP806 Quad";
	compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x000>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 0>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_0>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x001>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 0>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_0>;
		};
		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x100>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 1>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
		};
		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x101>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 1>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
		};

		l2_0: l2-cache0 {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-level = <2>;
		};

		l2_1: l2-cache1 {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-level = <2>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada AP806.
 */

#define AP_NAME		ap806
#include "armada-ap80x.dtsi"

/ {
	model = "Marvell Armada AP806";
	compatible = "marvell,armada-ap806";
};

&ap_syscon0 {
	ap_clk: clock {
		compatible = "marvell,ap806-clock";
		#clock-cells = <1>;
	};
};

&ap_syscon1 {
	cpu_clk: clock-cpu@278 {
		compatible = "marvell,ap806-cpu-clock";
		clocks = <&ap_clk 0>, <&ap_clk 1>;
		#clock-cells = <1>;
		reg = <0x278 0xa30>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell Armada AP807 Quad
 *
 * Copyright (C) 2019 Marvell Technology Group Ltd.
 */

#include "armada-ap807.dtsi"

/ {
	model = "Marvell Armada AP807 Quad";
	compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x000>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 0>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_0>;
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x001>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 0>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_0>;
		};
		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x100>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 1>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
		};
		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x101>;
			enable-method = "psci";
			#cooling-cells = <2>;
			clocks = <&cpu_clk 1>;
			i-cache-size = <0xc000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
		};

		l2_0: l2-cache0 {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-level = <2>;
		};

		l2_1: l2-cache1 {
			compatible = "cache";
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-level = <2>;
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Marvell Armada AP807
 *
 * Copyright (C) 2019 Marvell Technology Group Ltd.
 */

#define AP_NAME		ap807
#include "armada-ap80x.dtsi"

/ {
	model = "Marvell Armada AP807";
	compatible = "marvell,armada-ap807";
};

&ap_syscon0 {
	ap_clk: clock {
		compatible = "marvell,ap807-clock";
		#clock-cells = <1>;
	};
};

&ap_syscon1 {
	cpu_clk: clock-cpu {
		compatible = "marvell,ap807-cpu-clock";
		clocks = <&ap_clk 0>, <&ap_clk 1>;
		#clock-cells = <1>;
	};
};

&ap_sdhci0 {
	compatible = "marvell,armada-ap807-sdhci",
		     "marvell,armada-ap806-sdhci"; /* Backward compatibility */
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada AP80x.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

/dts-v1/;

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		gpio0 = &ap_gpio;
		spi0 = &spi0;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * This area matches the mapping done with a
		 * mainline U-Boot, and should be updated by the
		 * bootloader.
		 */

		psci-area@4000000 {
			reg = <0x0 0x4000000 0x0 0x200000>;
			no-map;
		};

		tee@4400000 {
			reg = <0 0x4400000 0 0x1000000>;
			no-map;
		};
	};

	AP_NAME {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		config-space@f0000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0x0 0x0 0xf0000000 0x1000000>;

			smmu: iommu@5000000 {
				compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
				reg = <0x100000 0x100000>;
				dma-coherent;
				#iommu-cells = <1>;
				#global-interrupts = <1>;
				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			gic: interrupt-controller@210000 {
				compatible = "arm,gic-400";
				#interrupt-cells = <3>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;
				interrupt-controller;
				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
				reg = <0x210000 0x10000>,
				      <0x220000 0x20000>,
				      <0x240000 0x20000>,
				      <0x260000 0x20000>;

				gic_v2m0: v2m@280000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x280000 0x1000>;
					arm,msi-base-spi = <160>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m1: v2m@290000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x290000 0x1000>;
					arm,msi-base-spi = <192>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m2: v2m@2a0000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x2a0000 0x1000>;
					arm,msi-base-spi = <224>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m3: v2m@2b0000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x2b0000 0x1000>;
					arm,msi-base-spi = <256>;
					arm,msi-num-spis = <32>;
				};
			};

			timer {
				compatible = "arm,armv8-timer";
				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
			};

			pmu {
				compatible = "arm,cortex-a72-pmu";
				interrupt-parent = <&pic>;
				interrupts = <17>;
			};

			odmi: odmi@300000 {
				compatible = "marvell,odmi-controller";
				interrupt-controller;
				msi-controller;
				marvell,odmi-frames = <4>;
				reg = <0x300000 0x4000>,
				      <0x304000 0x4000>,
				      <0x308000 0x4000>,
				      <0x30C000 0x4000>;
				marvell,spi-base = <128>, <136>, <144>, <152>;
			};

			gicp: gicp@3f0040 {
				compatible = "marvell,ap806-gicp";
				reg = <0x3f0040 0x10>;
				marvell,spi-ranges = <64 64>, <288 64>;
				msi-controller;
			};

			pic: interrupt-controller@3f0100 {
				compatible = "marvell,armada-8k-pic";
				reg = <0x3f0100 0x10>;
				#interrupt-cells = <1>;
				interrupt-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			sei: interrupt-controller@3f0200 {
				compatible = "marvell,ap806-sei";
				reg = <0x3f0200 0x40>;
				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <1>;
				interrupt-controller;
				msi-controller;
			};

			xor@400000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x400000 0x1000>,
				      <0x410000 0x1000>;
				msi-parent = <&gic_v2m0>;
				clocks = <&ap_clk 3>;
				dma-coherent;
			};

			xor@420000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x420000 0x1000>,
				      <0x430000 0x1000>;
				msi-parent = <&gic_v2m0>;
				clocks = <&ap_clk 3>;
				dma-coherent;
			};

			xor@440000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x440000 0x1000>,
				      <0x450000 0x1000>;
				msi-parent = <&gic_v2m0>;
				clocks = <&ap_clk 3>;
				dma-coherent;
			};

			xor@460000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x460000 0x1000>,
				      <0x470000 0x1000>;
				msi-parent = <&gic_v2m0>;
				clocks = <&ap_clk 3>;
				dma-coherent;
			};

			spi0: spi@510600 {
				compatible = "marvell,armada-380-spi";
				reg = <0x510600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ap_clk 3>;
				status = "disabled";
			};

			i2c0: i2c@511000 {
				compatible = "marvell,mv78230-i2c";
				reg = <0x511000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ap_clk 3>;
				status = "disabled";
			};

			uart0: serial@512000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x512000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&ap_clk 3>;
				status = "disabled";
			};

			uart1: serial@512100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x512100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&ap_clk 3>;
				status = "disabled";

			};

			watchdog: watchdog@610000 {
				compatible = "arm,sbsa-gwdt";
				reg = <0x610000 0x1000>, <0x600000 0x1000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			};

			ap_sdhci0: mmc@6e0000 {
				compatible = "marvell,armada-ap806-sdhci";
				reg = <0x6e0000 0x300>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clock-names = "core";
				clocks = <&ap_clk 4>;
				dma-coherent;
				marvell,xenon-phy-slow-mode;
				status = "disabled";
			};

			ap_syscon0: system-controller@6f4000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x6f4000 0x2000>;

				ap_pinctrl: pinctrl {
					compatible = "marvell,ap806-pinctrl";

					uart0_pins: uart0-pins {
						marvell,pins = "mpp11", "mpp19";
						marvell,function = "uart0";
					};
				};

				ap_gpio: gpio@1040 {
					compatible = "marvell,armada-8k-gpio";
					offset = <0x1040>;
					ngpios = <20>;
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&ap_pinctrl 0 0 20>;
					marvell,pwm-offset = <0x10c0>;
					#pwm-cells = <2>;
					clocks = <&ap_clk 3>;
				};
			};

			ap_syscon1: system-controller@6f8000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x6f8000 0x1000>;
				#address-cells = <1>;
				#size-cells = <1>;

				ap_thermal: thermal-sensor@80 {
					compatible = "marvell,armada-ap806-thermal";
					reg = <0x80 0x10>;
					interrupt-parent = <&sei>;
					interrupts = <18>;
					#thermal-sensor-cells = <1>;
				};
			};
		};
	};

	/*
	 * The thermal IP features one internal sensor plus, if applicable, one
	 * remote channel wired to one sensor per CPU.
	 *
	 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
	 * first one that will have a critical trip point will be chosen.
	 */
	thermal-zones {
		ap_thermal_ic: ap-thermal-ic {
			polling-delay-passive = <0>; /* Interrupt driven */
			polling-delay = <0>; /* Interrupt driven */

			thermal-sensors = <&ap_thermal 0>;

			trips {
				ap_crit: ap-crit {
					temperature = <100000>; /* mC degrees */
					hysteresis = <2000>; /* mC degrees */
					type = "critical";
				};
			};

			cooling-maps { };
		};

		ap_thermal_cpu0: ap-thermal-cpu0 {
			polling-delay-passive = <1000>;
			polling-delay = <1000>;

			thermal-sensors = <&ap_thermal 1>;

			trips {
				cpu0_hot: cpu0-hot {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu0_emerg: cpu0-emerg {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};
			};

			cooling-maps {
				map0_hot: map0-hot {
					trip = <&cpu0_hot>;
					cooling-device = <&cpu0 1 2>,
						<&cpu1 1 2>;
				};
				map0_emerg: map0-ermerg {
					trip = <&cpu0_emerg>;
					cooling-device = <&cpu0 3 3>,
						<&cpu1 3 3>;
				};
			};
		};

		ap_thermal_cpu1: ap-thermal-cpu1 {
			polling-delay-passive = <1000>;
			polling-delay = <1000>;

			thermal-sensors = <&ap_thermal 2>;

			trips {
				cpu1_hot: cpu1-hot {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu1_emerg: cpu1-emerg {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};
			};

			cooling-maps {
				map1_hot: map1-hot {
					trip = <&cpu1_hot>;
					cooling-device = <&cpu0 1 2>,
						<&cpu1 1 2>;
				};
				map1_emerg: map1-emerg {
					trip = <&cpu1_emerg>;
					cooling-device = <&cpu0 3 3>,
						<&cpu1 3 3>;
				};
			};
		};

		ap_thermal_cpu2: ap-thermal-cpu2 {
			polling-delay-passive = <1000>;
			polling-delay = <1000>;

			thermal-sensors = <&ap_thermal 3>;

			trips {
				cpu2_hot: cpu2-hot {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu2_emerg: cpu2-emerg {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};
			};

			cooling-maps {
				map2_hot: map2-hot {
					trip = <&cpu2_hot>;
					cooling-device = <&cpu2 1 2>,
						<&cpu3 1 2>;
				};
				map2_emerg: map2-emerg {
					trip = <&cpu2_emerg>;
					cooling-device = <&cpu2 3 3>,
						<&cpu3 3 3>;
				};
			};
		};

		ap_thermal_cpu3: ap-thermal-cpu3 {
			polling-delay-passive = <1000>;
			polling-delay = <1000>;

			thermal-sensors = <&ap_thermal 4>;

			trips {
				cpu3_hot: cpu3-hot {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu3_emerg: cpu3-emerg {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};
			};

			cooling-maps {
				map3_hot: map3-bhot {
					trip = <&cpu3_hot>;
					cooling-device = <&cpu2 1 2>,
						<&cpu3 1 2>;
				};
				map3_emerg: map3-emerg {
					trip = <&cpu3_emerg>;
					cooling-device = <&cpu2 3 3>,
						<&cpu3 3 3>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2017 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada AP810 OCTA cores.
 */

#include "armada-ap810-ap0.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "marvell,armada-ap810-octa";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x000>;
			enable-method = "psci";
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x001>;
			enable-method = "psci";
		};
		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x100>;
			enable-method = "psci";
		};
		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x101>;
			enable-method = "psci";
		};
		cpu4: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x200>;
			enable-method = "psci";
		};
		cpu5: cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x201>;
			enable-method = "psci";
		};
		cpu6: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x300>;
			enable-method = "psci";
		};
		cpu7: cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x301>;
			enable-method = "psci";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2017 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada AP810.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/dts-v1/;

/ {
	model = "Marvell Armada AP810";
	compatible = "marvell,armada-ap810";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0_ap0;
		serial1 = &uart1_ap0;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	ap810-ap0 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		config-space@e8000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0x0 0x0 0xe8000000 0x4000000>;
			interrupt-parent = <&gic>;

			gic: interrupt-controller@3000000 {
				compatible = "arm,gic-v3";
				#interrupt-cells = <3>;
				#address-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
				ranges;

				reg = <0x3000000 0x10000>,	/* GICD */
				      <0x3060000 0x100000>,	/* GICR */
				      <0x00c0000 0x2000>,	/* GICC */
				      <0x00d0000 0x1000>,	/* GICH */
				      <0x00e0000 0x2000>;	/* GICV */

				gic_its_ap0: interrupt-controller@3040000 {
					compatible = "arm,gic-v3-its";
					msi-controller;
					#msi-cells = <1>;
					reg = <0x3040000 0x20000>;
				};
			};

			timer {
				compatible = "arm,armv8-timer";
				interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
					     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
					     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
					     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
			};

			xor@400000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x400000 0x1000>,
				      <0x410000 0x1000>;
				msi-parent = <&gic_its_ap0 0xa0>;
				dma-coherent;
			};

			xor@420000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x420000 0x1000>,
				      <0x430000 0x1000>;
				msi-parent = <&gic_its_ap0 0xa1>;
				dma-coherent;
			};

			xor@440000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x440000 0x1000>,
				      <0x450000 0x1000>;
				msi-parent = <&gic_its_ap0 0xa2>;
				dma-coherent;
			};

			xor@460000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x460000 0x1000>,
				      <0x470000 0x1000>;
				msi-parent = <&gic_its_ap0 0xa3>;
				dma-coherent;
			};

			uart0_ap0: serial@512000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x512000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				status = "disabled";
			};

			uart1_ap0: serial@512100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x512100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				status = "disabled";
			};
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 */

/* Common definitions used by Armada 7K/8K DTs */
#define PASTER(x, y) x ## y
#define EVALUATOR(x, y) PASTER(x, y)
#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))
#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))
#define ADDRESSIFY(addr) EVALUATOR(0x, addr)


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada CP110.
 */

#define CP11X_TYPE cp110

#include "armada-cp11x.dtsi"

#undef CP11X_TYPE


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada CP115.
 */

#define CP11X_TYPE cp115

#include "armada-cp11x.dtsi"

#undef CP11X_TYPE


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada CP11x.
 */

#include <dt-bindings/interrupt-controller/mvebu-icu.h>
#include <dt-bindings/thermal/thermal.h>

#include "armada-common.dtsi"

#define CP11X_PCIEx_CONF_BASE(iface)	(CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))

/ {
	/*
	 * The contents of the node are defined below, in order to
	 * save one indentation level
	 */
	CP11X_NAME: CP11X_NAME { };

	/*
	 * CPs only have one sensor in the thermal IC.
	 *
	 * The cooling maps are empty as there are no cooling devices.
	 */
	thermal-zones {
		CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
			polling-delay-passive = <0>; /* Interrupt driven */
			polling-delay = <0>; /* Interrupt driven */

			thermal-sensors = <&CP11X_LABEL(thermal) 0>;

			trips {
				CP11X_LABEL(crit): crit {
					temperature = <100000>; /* mC degrees */
					hysteresis = <2000>; /* mC degrees */
					type = "critical";
				};
			};

			cooling-maps { };
		};
	};
};

&CP11X_NAME {
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "simple-bus";
	interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
	ranges;

	config-space@CP11X_BASE {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;

		CP11X_LABEL(ethernet): ethernet@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "marvell,armada-7k-pp22";
			reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
			clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
				 <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
				 <&CP11X_LABEL(clk) 1 18>;
			clock-names = "pp_clk", "gop_clk",
				      "mg_clk", "mg_core_clk", "axi_clk";
			marvell,system-controller = <&CP11X_LABEL(syscon0)>;
			status = "disabled";
			dma-coherent;

			CP11X_LABEL(eth0): ethernet-port@0 {
				interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
					<43 IRQ_TYPE_LEVEL_HIGH>,
					<47 IRQ_TYPE_LEVEL_HIGH>,
					<51 IRQ_TYPE_LEVEL_HIGH>,
					<55 IRQ_TYPE_LEVEL_HIGH>,
					<59 IRQ_TYPE_LEVEL_HIGH>,
					<63 IRQ_TYPE_LEVEL_HIGH>,
					<67 IRQ_TYPE_LEVEL_HIGH>,
					<71 IRQ_TYPE_LEVEL_HIGH>,
					<129 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "hif0", "hif1", "hif2",
					"hif3", "hif4", "hif5", "hif6", "hif7",
					"hif8", "link";
				reg = <0>;
				port-id = <0>; /* For backward compatibility. */
				gop-port-id = <0>;
				status = "disabled";
			};

			CP11X_LABEL(eth1): ethernet-port@1 {
				interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
					<44 IRQ_TYPE_LEVEL_HIGH>,
					<48 IRQ_TYPE_LEVEL_HIGH>,
					<52 IRQ_TYPE_LEVEL_HIGH>,
					<56 IRQ_TYPE_LEVEL_HIGH>,
					<60 IRQ_TYPE_LEVEL_HIGH>,
					<64 IRQ_TYPE_LEVEL_HIGH>,
					<68 IRQ_TYPE_LEVEL_HIGH>,
					<72 IRQ_TYPE_LEVEL_HIGH>,
					<128 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "hif0", "hif1", "hif2",
					"hif3", "hif4", "hif5", "hif6", "hif7",
					"hif8", "link";
				reg = <1>;
				port-id = <1>; /* For backward compatibility. */
				gop-port-id = <2>;
				status = "disabled";
			};

			CP11X_LABEL(eth2): ethernet-port@2 {
				interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
					<45 IRQ_TYPE_LEVEL_HIGH>,
					<49 IRQ_TYPE_LEVEL_HIGH>,
					<53 IRQ_TYPE_LEVEL_HIGH>,
					<57 IRQ_TYPE_LEVEL_HIGH>,
					<61 IRQ_TYPE_LEVEL_HIGH>,
					<65 IRQ_TYPE_LEVEL_HIGH>,
					<69 IRQ_TYPE_LEVEL_HIGH>,
					<73 IRQ_TYPE_LEVEL_HIGH>,
					<127 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "hif0", "hif1", "hif2",
					"hif3", "hif4", "hif5", "hif6", "hif7",
					"hif8", "link";
				reg = <2>;
				port-id = <2>; /* For backward compatibility. */
				gop-port-id = <3>;
				status = "disabled";
			};
		};

		CP11X_LABEL(comphy): phy@120000 {
			compatible = "marvell,comphy-cp110";
			reg = <0x120000 0x6000>;
			marvell,system-controller = <&CP11X_LABEL(syscon0)>;
			clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
				 <&CP11X_LABEL(clk) 1 18>;
			clock-names = "mg_clk", "mg_core_clk", "axi_clk";
			#address-cells = <1>;
			#size-cells = <0>;

			CP11X_LABEL(comphy0): phy@0 {
				reg = <0>;
				#phy-cells = <1>;
			};

			CP11X_LABEL(comphy1): phy@1 {
				reg = <1>;
				#phy-cells = <1>;
			};

			CP11X_LABEL(comphy2): phy@2 {
				reg = <2>;
				#phy-cells = <1>;
			};

			CP11X_LABEL(comphy3): phy@3 {
				reg = <3>;
				#phy-cells = <1>;
			};

			CP11X_LABEL(comphy4): phy@4 {
				reg = <4>;
				#phy-cells = <1>;
			};

			CP11X_LABEL(comphy5): phy@5 {
				reg = <5>;
				#phy-cells = <1>;
			};
		};

		CP11X_LABEL(mdio): mdio@12a200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "marvell,orion-mdio";
			reg = <0x12a200 0x10>;
			clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
				 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
			status = "disabled";
		};

		CP11X_LABEL(xmdio): mdio@12a600 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "marvell,xmdio";
			reg = <0x12a600 0x10>;
			clocks = <&CP11X_LABEL(clk) 1 5>,
				 <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
			status = "disabled";
		};

		CP11X_LABEL(icu): interrupt-controller@1e0000 {
			compatible = "marvell,cp110-icu";
			reg = <0x1e0000 0x440>;
			#address-cells = <1>;
			#size-cells = <1>;

			CP11X_LABEL(icu_nsr): interrupt-controller@10 {
				compatible = "marvell,cp110-icu-nsr";
				reg = <0x10 0x20>;
				#interrupt-cells = <2>;
				interrupt-controller;
				msi-parent = <&gicp>;
			};

			CP11X_LABEL(icu_sei): interrupt-controller@50 {
				compatible = "marvell,cp110-icu-sei";
				reg = <0x50 0x10>;
				#interrupt-cells = <2>;
				interrupt-controller;
				msi-parent = <&sei>;
			};
		};

		CP11X_LABEL(rtc): rtc@284000 {
			compatible = "marvell,armada-8k-rtc";
			reg = <0x284000 0x20>, <0x284080 0x24>;
			reg-names = "rtc", "rtc-soc";
			interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
		};

		CP11X_LABEL(syscon0): system-controller@440000 {
			compatible = "syscon", "simple-mfd";
			reg = <0x440000 0x2000>;

			CP11X_LABEL(clk): clock {
				compatible = "marvell,cp110-clock";
				#clock-cells = <2>;
			};

			CP11X_LABEL(gpio1): gpio@100 {
				compatible = "marvell,armada-8k-gpio";
				offset = <0x100>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
				marvell,pwm-offset = <0x1f0>;
				#pwm-cells = <2>;
				interrupt-controller;
				interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
					<85 IRQ_TYPE_LEVEL_HIGH>,
					<84 IRQ_TYPE_LEVEL_HIGH>,
					<83 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <2>;
				clock-names = "core", "axi";
				clocks = <&CP11X_LABEL(clk) 1 21>,
					 <&CP11X_LABEL(clk) 1 17>;
				status = "disabled";
			};

			CP11X_LABEL(gpio2): gpio@140 {
				compatible = "marvell,armada-8k-gpio";
				offset = <0x140>;
				ngpios = <31>;
				gpio-controller;
				#gpio-cells = <2>;
				gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
				marvell,pwm-offset = <0x1f0>;
				#pwm-cells = <2>;
				interrupt-controller;
				interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
					<81 IRQ_TYPE_LEVEL_HIGH>,
					<80 IRQ_TYPE_LEVEL_HIGH>,
					<79 IRQ_TYPE_LEVEL_HIGH>;
				#interrupt-cells = <2>;
				clock-names = "core", "axi";
				clocks = <&CP11X_LABEL(clk) 1 21>,
					 <&CP11X_LABEL(clk) 1 17>;
				status = "disabled";
			};
		};

		CP11X_LABEL(syscon1): system-controller@400000 {
			compatible = "syscon", "simple-mfd";
			reg = <0x400000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			CP11X_LABEL(thermal): thermal-sensor@70 {
				compatible = "marvell,armada-cp110-thermal";
				reg = <0x70 0x10>;
				interrupts-extended =
					<&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
				#thermal-sensor-cells = <1>;
			};
		};

		CP11X_LABEL(utmi): utmi@580000 {
			compatible = "marvell,cp110-utmi-phy";
			reg = <0x580000 0x2000>;
			marvell,system-controller = <&CP11X_LABEL(syscon0)>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			CP11X_LABEL(utmi0): usb-phy@0 {
				reg = <0>;
				#phy-cells = <0>;
			};

			CP11X_LABEL(utmi1): usb-phy@1 {
				reg = <1>;
				#phy-cells = <0>;
			};
		};

		CP11X_LABEL(usb3_0): usb@500000 {
			compatible = "marvell,armada-8k-xhci",
			"generic-xhci";
			reg = <0x500000 0x4000>;
			dma-coherent;
			interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "core", "reg";
			clocks = <&CP11X_LABEL(clk) 1 22>,
				 <&CP11X_LABEL(clk) 1 16>;
			status = "disabled";
		};

		CP11X_LABEL(usb3_1): usb@510000 {
			compatible = "marvell,armada-8k-xhci",
			"generic-xhci";
			reg = <0x510000 0x4000>;
			dma-coherent;
			interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "core", "reg";
			clocks = <&CP11X_LABEL(clk) 1 23>,
				 <&CP11X_LABEL(clk) 1 16>;
			status = "disabled";
		};

		CP11X_LABEL(sata0): sata@540000 {
			compatible = "marvell,armada-8k-ahci",
			"generic-ahci";
			reg = <0x540000 0x30000>;
			dma-coherent;
			interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&CP11X_LABEL(clk) 1 15>,
				 <&CP11X_LABEL(clk) 1 16>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sata-port@0 {
				reg = <0>;
			};

			sata-port@1 {
				reg = <1>;
			};
		};

		CP11X_LABEL(xor0): xor@6a0000 {
			compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
			reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
			dma-coherent;
			msi-parent = <&gic_v2m0>;
			clock-names = "core", "reg";
			clocks = <&CP11X_LABEL(clk) 1 8>,
				 <&CP11X_LABEL(clk) 1 14>;
		};

		CP11X_LABEL(xor1): xor@6c0000 {
			compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
			reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
			dma-coherent;
			msi-parent = <&gic_v2m0>;
			clock-names = "core", "reg";
			clocks = <&CP11X_LABEL(clk) 1 7>,
				 <&CP11X_LABEL(clk) 1 14>;
		};

		CP11X_LABEL(spi0): spi@700600 {
			compatible = "marvell,armada-380-spi";
			reg = <0x700600 0x50>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "core", "axi";
			clocks = <&CP11X_LABEL(clk) 1 21>,
				 <&CP11X_LABEL(clk) 1 17>;
			status = "disabled";
		};

		CP11X_LABEL(spi1): spi@700680 {
			compatible = "marvell,armada-380-spi";
			reg = <0x700680 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-names = "core", "axi";
			clocks = <&CP11X_LABEL(clk) 1 21>,
				 <&CP11X_LABEL(clk) 1 17>;
			status = "disabled";
		};

		CP11X_LABEL(i2c0): i2c@701000 {
			compatible = "marvell,mv78230-i2c";
			reg = <0x701000 0x20>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "core", "reg";
			clocks = <&CP11X_LABEL(clk) 1 21>,
				 <&CP11X_LABEL(clk) 1 17>;
			status = "disabled";
		};

		CP11X_LABEL(i2c1): i2c@701100 {
			compatible = "marvell,mv78230-i2c";
			reg = <0x701100 0x20>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "core", "reg";
			clocks = <&CP11X_LABEL(clk) 1 21>,
				 <&CP11X_LABEL(clk) 1 17>;
			status = "disabled";
		};

		CP11X_LABEL(uart0): serial@702000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x702000 0x100>;
			reg-shift = <2>;
			interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <1>;
			clock-names = "baudclk", "apb_pclk";
			clocks = <&CP11X_LABEL(clk) 1 21>,
				 <&CP11X_LABEL(clk) 1 17>;
			status = "disabled";
		};

		CP11X_LABEL(uart1): serial@702100 {
			compatible = "snps,dw-apb-uart";
			reg = <0x702100 0x100>;
			reg-shift = <2>;
			interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <1>;
			clock-names = "baudclk", "apb_pclk";
			clocks = <&CP11X_LABEL(clk) 1 21>,
				 <&CP11X_LABEL(clk) 1 17>;
			status = "disabled";
		};

		CP11X_LABEL(uart2): serial@702200 {
			compatible = "snps,dw-apb-uart";
			reg = <0x702200 0x100>;
			reg-shift = <2>;
			interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <1>;
			clock-names = "baudclk", "apb_pclk";
			clocks = <&CP11X_LABEL(clk) 1 21>,
				 <&CP11X_LABEL(clk) 1 17>;
			status = "disabled";
		};

		CP11X_LABEL(uart3): serial@702300 {
			compatible = "snps,dw-apb-uart";
			reg = <0x702300 0x100>;
			reg-shift = <2>;
			interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
			reg-io-width = <1>;
			clock-names = "baudclk", "apb_pclk";
			clocks = <&CP11X_LABEL(clk) 1 21>,
				 <&CP11X_LABEL(clk) 1 17>;
			status = "disabled";
		};

		CP11X_LABEL(nand_controller): nand@720000 {
			/*
			 * Due to the limitation of the pins available
			 * this controller is only usable on the CPM
			 * for A7K and on the CPS for A8K.
			 */
			compatible = "marvell,armada-8k-nand-controller",
				"marvell,armada370-nand-controller";
			reg = <0x720000 0x54>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "core", "reg";
			clocks = <&CP11X_LABEL(clk) 1 2>,
				 <&CP11X_LABEL(clk) 1 17>;
			marvell,system-controller = <&CP11X_LABEL(syscon0)>;
			status = "disabled";
		};

		CP11X_LABEL(trng): trng@760000 {
			compatible = "marvell,armada-8k-rng",
			"inside-secure,safexcel-eip76";
			reg = <0x760000 0x7d>;
			interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "core", "reg";
			clocks = <&CP11X_LABEL(clk) 1 25>,
				 <&CP11X_LABEL(clk) 1 17>;
			status = "okay";
		};

		CP11X_LABEL(sdhci0): mmc@780000 {
			compatible = "marvell,armada-cp110-sdhci";
			reg = <0x780000 0x300>;
			interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "core", "axi";
			clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
			dma-coherent;
			status = "disabled";
		};

		CP11X_LABEL(crypto): crypto@800000 {
			compatible = "inside-secure,safexcel-eip197b";
			reg = <0x800000 0x200000>;
			interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
				<88 IRQ_TYPE_LEVEL_HIGH>,
				<89 IRQ_TYPE_LEVEL_HIGH>,
				<90 IRQ_TYPE_LEVEL_HIGH>,
				<91 IRQ_TYPE_LEVEL_HIGH>,
				<92 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mem", "ring0", "ring1",
				"ring2", "ring3", "eip";
			clock-names = "core", "reg";
			clocks = <&CP11X_LABEL(clk) 1 26>,
				 <&CP11X_LABEL(clk) 1 17>;
			dma-coherent;
		};
	};

	CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
		reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
		      <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
		reg-names = "ctrl", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		dma-coherent;
		msi-parent = <&gic_v2m0>;

		bus-range = <0 0xff>;
		/* non-prefetchable memory */
		ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0  CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
		interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
		num-lanes = <1>;
		clock-names = "core", "reg";
		clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
		status = "disabled";
	};

	CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
		reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
		      <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
		reg-names = "ctrl", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		dma-coherent;
		msi-parent = <&gic_v2m0>;

		bus-range = <0 0xff>;
		/* non-prefetchable memory */
		ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0  CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
		interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <1>;
		clock-names = "core", "reg";
		clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
		status = "disabled";
	};

	CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
		reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
		      <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
		reg-names = "ctrl", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		dma-coherent;
		msi-parent = <&gic_v2m0>;

		bus-range = <0 0xff>;
		/* non-prefetchable memory */
		ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0  CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
		interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <1>;
		clock-names = "core", "reg";
		clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
		status = "disabled";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2020 Marvell International Ltd.
 */

#include "cn9130-crb.dtsi"

/ {
	model = "Marvell Armada CN9130-CRB-A";
};

&cp0_pcie0 {
	status = "okay";
	num-lanes = <4>;
	num-viewport = <8>;
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy0 0
		&cp0_comphy1 0
		&cp0_comphy2 0
		&cp0_comphy3 0>;
	iommu-map =
		<0x0   &smmu 0x480 0x20>,
		<0x100 &smmu 0x4a0 0x20>,
		<0x200 &smmu 0x4c0 0x20>;
	iommu-map-mask = <0x031f>;
};

&cp0_usb3_0 {
	status = "okay";
	usb-phy = <&cp0_usb3_0_phy0>;
	phy-names = "usb";
};

&cp0_usb3_1 {
	status = "okay";
	usb-phy = <&cp0_usb3_0_phy1>;
	phy-names = "usb";
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2020 Marvell International Ltd.
 */

#include "cn9130-crb.dtsi"

/ {
	model = "Marvell Armada CN9130-CRB-B";
};

&cp0_pcie0 {
	status = "okay";
	num-lanes = <1>;
	num-viewport = <8>;
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy0 0>;
	iommu-map =
		<0x0   &smmu 0x480 0x20>,
		<0x100 &smmu 0x4a0 0x20>,
		<0x200 &smmu 0x4c0 0x20>;
	iommu-map-mask = <0x031f>;
};

&cp0_sata0 {
	status = "okay";
	sata-port@0 {
		status = "okay";
		/* Generic PHY, providing serdes lanes */
		phys = <&cp0_comphy2 0>;
	};
};

&cp0_usb3_0 {
	status = "okay";
	usb-phy = <&cp0_usb3_0_phy0>;
	phy-names = "usb";
	phys = <&cp0_comphy1 0>;
};

&cp0_usb3_1 {
	status = "okay";
	usb-phy = <&cp0_usb3_0_phy1>;
	phy-names = "usb";
	phys = <&cp0_comphy3 1>;
};


code:
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2020 Marvell International Ltd.
 */

#include "cn9130.dtsi" /* include SoC device tree */

#include <dt-bindings/gpio/gpio.h>

/ {
	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		i2c0 = &cp0_i2c0;
		ethernet0 = &cp0_eth0;
		ethernet1 = &cp0_eth1;
		ethernet2 = &cp0_eth2;
		gpio1 = &cp0_gpio1;
		gpio2 = &cp0_gpio2;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	ap0_reg_mmc_vccq: ap0_mmc_vccq@0 {
		compatible = "regulator-gpio";
		regulator-name = "ap0_mmc_vccq";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x1
			  3300000 0x0>;
	};

	cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
		compatible = "regulator-fixed";
		regulator-name = "cp0-xhci1-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
	};

	cp0_usb3_0_phy0: cp0_usb3_phy0 {
		compatible = "usb-nop-xceiv";
	};

	cp0_usb3_0_phy1: cp0_usb3_phy1 {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&cp0_reg_usb3_vbus1>;
	};

	cp0_reg_sd_vccq: cp0_sd_vccq@0 {
		compatible = "regulator-gpio";
		regulator-name = "cp0_sd_vccq";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x1
			  3300000 0x0>;
	};

	cp0_reg_sd_vcc: cp0_sd_vcc@0 {
		compatible = "regulator-fixed";
		regulator-name = "cp0_sd_vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};

	sfp: sfp {
		compatible = "sff,sfp";
		i2c-bus = <&cp0_i2c1>;
		mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>;
		los-gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
		tx-disable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>;
		maximum-power-milliwatt = <3000>;
		status = "okay";
	};
};

&uart0 {
	status = "okay";
};

/* on-board eMMC U6 */
&ap_sdhci0 {
	pinctrl-names = "default";
	bus-width = <8>;
	status = "okay";
	mmc-ddr-1_8v;
	vqmmc-supply = <&ap0_reg_mmc_vccq>;
};

&cp0_syscon0 {
	cp0_pinctrl: pinctrl {
		compatible = "marvell,cp115-standalone-pinctrl";

		cp0_i2c0_pins: cp0-i2c-pins-0 {
			marvell,pins = "mpp37", "mpp38";
			marvell,function = "i2c0";
		};
		cp0_i2c1_pins: cp0-i2c-pins-1 {
			marvell,pins = "mpp35", "mpp36";
			marvell,function = "i2c1";
		};
		cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
			marvell,pins = "mpp55";
			marvell,function = "gpio";
		};
		cp0_sdhci_pins: cp0-sdhi-pins-0 {
			marvell,pins = "mpp56", "mpp57", "mpp58",
				       "mpp59", "mpp60", "mpp61";
			marvell,function = "sdio";
		};
		cp0_spi0_pins: cp0-spi-pins-0 {
			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
			marvell,function = "spi1";
		};
	};
};

&cp0_gpio1 {
	status = "okay";
};

&cp0_gpio2 {
	status = "okay";
};

&cp0_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c0_pins>;
	status = "okay";
	clock-frequency = <100000>;
	expander0: mcp23x17@20 {
		compatible = "microchip,mcp23017";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x20>;
		status = "okay";
	};
};

&cp0_i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c1_pins>;
	clock-frequency = <100000>;
	status = "okay";
};

&cp0_sdhci0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_sdhci_pins
		     &cp0_sdhci_cd_pins_crb>;
	bus-width = <4>;
	cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
	vqmmc-supply = <&cp0_reg_sd_vccq>;
	vmmc-supply = <&cp0_reg_sd_vcc>;
	status = "okay";
};

&cp0_spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_spi0_pins>;
	reg = <0x700680 0x50>,		/* control */
	      <0x2000000 0x1000000>;	/* CS0 */
	status = "okay";

	flash@0 {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		/* On-board MUX does not allow higher frequencies */
		spi-max-frequency = <40000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0x0 0x200000>;
			};

			partition@400000 {
				label = "Filesystem";
				reg = <0x200000 0xe00000>;
			};
		};
	};
};

&cp0_mdio {
	status = "okay";
	phy0: ethernet-phy@0 {
		reg = <0>;
	};

	switch6: switch0@6 {
		/* Actual device is MV88E6393X */
		compatible = "marvell,mv88e6190";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <6>;
		interrupt-parent = <&cp0_gpio1>;
		interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <2>;

		dsa,member = <0 0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@1 {
				reg = <1>;
				label = "p1";
				phy-handle = <&switch0phy1>;
			};

			port@2 {
				reg = <2>;
				label = "p2";
				phy-handle = <&switch0phy2>;
			};

			port@3 {
				reg = <3>;
				label = "p3";
				phy-handle = <&switch0phy3>;
			};

			port@4 {
				reg = <4>;
				label = "p4";
				phy-handle = <&switch0phy4>;
			};

			port@5 {
				reg = <5>;
				label = "p5";
				phy-handle = <&switch0phy5>;
			};

			port@6 {
				reg = <6>;
				label = "p6";
				phy-handle = <&switch0phy6>;
			};

			port@7 {
				reg = <7>;
				label = "p7";
				phy-handle = <&switch0phy7>;
			};

			port@8 {
				reg = <8>;
				label = "p8";
				phy-handle = <&switch0phy8>;
			};

			port@9 {
				reg = <9>;
				label = "p9";
				phy-mode = "10gbase-r";
				sfp = <&sfp>;
				managed = "in-band-status";
			};

			port@a {
				reg = <10>;
				label = "cpu";
				ethernet = <&cp0_eth0>;
			};

		};

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch0phy1: switch0phy1@1 {
				reg = <0x1>;
			};

			switch0phy2: switch0phy2@2 {
				reg = <0x2>;
			};

			switch0phy3: switch0phy3@3 {
				reg = <0x3>;
			};

			switch0phy4: switch0phy4@4 {
				reg = <0x4>;
			};

			switch0phy5: switch0phy5@5 {
				reg = <0x5>;
			};

			switch0phy6: switch0phy6@6 {
				reg = <0x6>;
			};

			switch0phy7: switch0phy7@7 {
				reg = <0x7>;
			};

			switch0phy8: switch0phy8@8 {
				reg = <0x8>;
			};
		};
	};
};

&cp0_xmdio {
	status = "okay";
	nbaset_phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <0>;
	};
};

&cp0_ethernet {
	status = "okay";
};

&cp0_eth0 {
	/* This port is connected to 88E6393X switch */
	status = "okay";
	phy-mode = "10gbase-r";
	managed = "in-band-status";
	phys = <&cp0_comphy4 0>;
};

&cp0_eth1 {
	status = "okay";
	phy = <&phy0>;
	phy-mode = "rgmii-id";
};

&cp0_eth2 {
	/* This port uses "2500base-t" phy-mode */
	status = "disabled";
	phy = <&nbaset_phy0>;
	phys = <&cp0_comphy5 2>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2020 Marvell International Ltd.
 *
 * Device tree for the CN9130-DB board (setup "B").
 */

#include "cn9130-db.dtsi"

/ {
	model = "Marvell Armada CN9130-DB setup B";
};

/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
 */

&cp0_nand_controller {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 Marvell International Ltd.
 *
 * Device tree for the CN9130-DB board.
 */

#include "cn9130-db.dtsi"

/ {
	model = "Marvell Armada CN9130-DB setup A";
};

/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
 * simultaneously. When SPI controller is enabled, NAND should be disabled.
 */

&cp0_spi1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 Marvell International Ltd.
 *
 * Device tree for the CN9130-DB board.
 */

#include "cn9130.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		gpio1 = &cp0_gpio1;
		gpio2 = &cp0_gpio2;
		i2c0 = &cp0_i2c0;
		ethernet0 = &cp0_eth0;
		ethernet1 = &cp0_eth1;
		ethernet2 = &cp0_eth2;
		spi1 = &cp0_spi0;
		spi2 = &cp0_spi1;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	ap0_reg_sd_vccq: ap0_sd_vccq@0 {
		compatible = "regulator-gpio";
		regulator-name = "ap0_sd_vccq";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x1 3300000 0x0>;
	};

	cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
		compatible = "regulator-fixed";
		regulator-name = "cp0-xhci0-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
	};

	cp0_usb3_0_phy0: cp0_usb3_phy@0 {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&cp0_reg_usb3_vbus0>;
	};

	cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
		compatible = "regulator-fixed";
		regulator-name = "cp0-xhci1-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
	};

	cp0_usb3_0_phy1: cp0_usb3_phy@1 {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&cp0_reg_usb3_vbus1>;
	};

	cp0_reg_sd_vccq: cp0_sd_vccq@0 {
		compatible = "regulator-gpio";
		regulator-name = "cp0_sd_vccq";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x1
			  3300000 0x0>;
	};

	cp0_reg_sd_vcc: cp0_sd_vcc@0 {
		compatible = "regulator-fixed";
		regulator-name = "cp0_sd_vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};

	cp0_sfp_eth0: sfp-eth@0 {
		compatible = "sff,sfp";
		i2c-bus = <&cp0_sfpp0_i2c>;
		los-gpios = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
		/*
		 * SFP cages are unconnected on early PCBs because of an the I2C
		 * lanes not being connected. Prevent the port for being
		 * unusable by disabling the SFP node.
		 */
		status = "disabled";
	};
};

&uart0 {
	status = "okay";
};

/* on-board eMMC - U9 */
&ap_sdhci0 {
	pinctrl-names = "default";
	bus-width = <8>;
	vqmmc-supply = <&ap0_reg_sd_vccq>;
	status = "okay";
};

&cp0_crypto {
	status = "disabled";
};

&cp0_ethernet {
	status = "okay";
};

/* SLM-1521-V2, CON9 */
&cp0_eth0 {
	status = "okay";
	phy-mode = "10gbase-r";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy4 0>;
	managed = "in-band-status";
	sfp = <&cp0_sfp_eth0>;
};

/* CON56 */
&cp0_eth1 {
	status = "okay";
	phy = <&phy0>;
	phy-mode = "rgmii-id";
};

/* CON57 */
&cp0_eth2 {
	status = "okay";
	phy = <&phy1>;
	phy-mode = "rgmii-id";
};

&cp0_gpio1 {
	status = "okay";
};

&cp0_gpio2 {
	status = "okay";
};

&cp0_i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c0_pins>;
	clock-frequency = <100000>;

	/* U36 */
	expander0: pca953x@21 {
		compatible = "nxp,pca9555";
		pinctrl-names = "default";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x21>;
		status = "okay";
	};

	/* U42 */
	eeprom0: eeprom@50 {
		compatible = "atmel,24c64";
		reg = <0x50>;
		pagesize = <0x20>;
	};

	/* U38 */
	eeprom1: eeprom@57 {
		compatible = "atmel,24c64";
		reg = <0x57>;
		pagesize = <0x20>;
	};
};

&cp0_i2c1 {
	status = "okay";
	clock-frequency = <100000>;

	/* SLM-1521-V2 - U3 */
	i2c-mux@72 { /* verify address - depends on dpr */
		compatible = "nxp,pca9544";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x72>;
		cp0_sfpp0_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			/* U12 */
			cp0_module_expander1: pca9555@21 {
				compatible = "nxp,pca9555";
				pinctrl-names = "default";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x21>;
			};

		};
	};
};

&cp0_mdio {
	status = "okay";

	phy0: ethernet-phy@0 {
		reg = <0>;
	};

	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

/* U54 */
&cp0_nand_controller {
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&nand_pins &nand_rb>;

	nand@0 {
		reg = <0>;
		label = "main-storage";
		nand-rb = <0>;
		nand-ecc-mode = "hw";
		nand-on-flash-bbt;
		nand-ecc-strength = <8>;
		nand-ecc-step-size = <512>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0 0x200000>;
			};
			partition@200000 {
				label = "Linux";
				reg = <0x200000 0xe00000>;
			};
			partition@1000000 {
				label = "Filesystem";
				reg = <0x1000000 0x3f000000>;
			};
		};
	};
};

/* SLM-1521-V2, CON6 */
&cp0_pcie0 {
	status = "okay";
	num-lanes = <4>;
	num-viewport = <8>;
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy0 0
		&cp0_comphy1 0
		&cp0_comphy2 0
		&cp0_comphy3 0>;
};

&cp0_sata0 {
	status = "okay";

	/* SLM-1521-V2, CON2 */
	sata-port@1 {
		status = "okay";
		/* Generic PHY, providing serdes lanes */
		phys = <&cp0_comphy5 1>;
	};
};

/* CON 28 */
&cp0_sdhci0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_sdhci_pins
		     &cp0_sdhci_cd_pins>;
	bus-width = <4>;
	cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	vqmmc-supply = <&cp0_reg_sd_vccq>;
	vmmc-supply = <&cp0_reg_sd_vcc>;
};

/* U55 */
&cp0_spi1 {
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_spi0_pins>;
	reg = <0x700680 0x50>;

	flash@0 {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		/* On-board MUX does not allow higher frequencies */
		spi-max-frequency = <40000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot-0";
				reg = <0x0 0x200000>;
			};

			partition@400000 {
				label = "Filesystem-0";
				reg = <0x200000 0xe00000>;
			};
		};
	};
};

&cp0_syscon0 {
	cp0_pinctrl: pinctrl {
		compatible = "marvell,cp115-standalone-pinctrl";

		cp0_i2c0_pins: cp0-i2c-pins-0 {
			marvell,pins = "mpp37", "mpp38";
			marvell,function = "i2c0";
		};
		cp0_i2c1_pins: cp0-i2c-pins-1 {
			marvell,pins = "mpp35", "mpp36";
			marvell,function = "i2c1";
		};
		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
			marvell,pins = "mpp0", "mpp1", "mpp2",
				       "mpp3", "mpp4", "mpp5",
				       "mpp6", "mpp7", "mpp8",
				       "mpp9", "mpp10", "mpp11";
			marvell,function = "ge0";
		};
		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
			marvell,pins = "mpp44", "mpp45", "mpp46",
				       "mpp47", "mpp48", "mpp49",
				       "mpp50", "mpp51", "mpp52",
				       "mpp53", "mpp54", "mpp55";
			marvell,function = "ge1";
		};
		cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
			marvell,pins = "mpp43";
			marvell,function = "gpio";
		};
		cp0_sdhci_pins: cp0-sdhi-pins-0 {
			marvell,pins = "mpp56", "mpp57", "mpp58",
				       "mpp59", "mpp60", "mpp61";
			marvell,function = "sdio";
		};
		cp0_spi0_pins: cp0-spi-pins-0 {
			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
			marvell,function = "spi1";
		};
		nand_pins: nand-pins {
			marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
				       "mpp19", "mpp20", "mpp21", "mpp22",
				       "mpp23", "mpp24", "mpp25", "mpp26",
				       "mpp27";
			marvell,function = "dev";
		};
		nand_rb: nand-rb {
			marvell,pins = "mpp13";
			marvell,function = "nf";
		};
	};
};

&cp0_utmi {
	status = "okay";
};

&cp0_usb3_0 {
	status = "okay";
	usb-phy = <&cp0_usb3_0_phy0>;
	phys = <&cp0_utmi0>;
	phy-names = "utmi";
	dr_mode = "host";
};

&cp0_usb3_1 {
	status = "okay";
	usb-phy = <&cp0_usb3_0_phy1>;
	phys = <&cp0_utmi1>;
	phy-names = "utmi";
	dr_mode = "host";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 Marvell International Ltd.
 *
 * Device tree for the CN9130 SoC.
 */

#include "armada-ap807-quad.dtsi"

/ {
	model = "Marvell Armada CN9130 SoC";
	compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
		     "marvell,armada-ap807";

	aliases {
		gpio1 = &cp0_gpio1;
		gpio2 = &cp0_gpio2;
		spi1 = &cp0_spi0;
		spi2 = &cp0_spi1;
	};
};

/*
 * Instantiate the internal CP115
 */

#define CP11X_NAME		cp0
#define CP11X_BASE		f2000000
#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
						    0xe0000000 + ((iface - 1) * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
#define CP11X_PCIE0_BASE	f2600000
#define CP11X_PCIE1_BASE	f2620000
#define CP11X_PCIE2_BASE	f2640000

#include "armada-cp115.dtsi"

#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE

&cp0_gpio1 {
	status = "okay";
};

&cp0_gpio2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2020 Marvell International Ltd.
 *
 * Device tree for the CN9131-DB board (setup "B").
 */

#include "cn9131-db.dtsi"

/ {
	model = "Marvell Armada CN9131-DB setup B";
};

/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
 */

&cp0_nand_controller {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 Marvell International Ltd.
 *
 * Device tree for the CN9131-DB board.
 */

#include "cn9131-db.dtsi"

/ {
	model = "Marvell Armada CN9131-DB setup A";
};

/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
 * simultaneously. When SPI controller is enabled, NAND should be disabled.
 */

&cp0_spi1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2020 Marvell International Ltd.
 *
 * Device tree for the CN9131-DB board.
 */

#include "cn9130-db.dtsi"

/ {
	compatible = "marvell,cn9131", "marvell,cn9130",
		     "marvell,armada-ap807-quad", "marvell,armada-ap807";

	aliases {
		gpio3 = &cp1_gpio1;
		gpio4 = &cp1_gpio2;
		ethernet3 = &cp1_eth0;
		ethernet4 = &cp1_eth1;
	};

	cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&cp1_xhci0_vbus_pins>;
		regulator-name = "cp1-xhci0-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
	};

	cp1_usb3_0_phy0: cp1_usb3_phy0 {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&cp1_reg_usb3_vbus0>;
	};

	cp1_sfp_eth1: sfp-eth1 {
		compatible = "sff,sfp";
		i2c-bus = <&cp1_i2c0>;
		los-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp1_sfp_pins>;
		/*
		 * SFP cages are unconnected on early PCBs because of an the I2C
		 * lanes not being connected. Prevent the port for being
		 * unusable by disabling the SFP node.
		 */
		status = "disabled";
	};
};

/*
 * Instantiate the first slave CP115
 */

#define CP11X_NAME		cp1
#define CP11X_BASE		f4000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE	f4600000
#define CP11X_PCIE1_BASE	f4620000
#define CP11X_PCIE2_BASE	f4640000

#include "armada-cp115.dtsi"

#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE

&cp1_crypto {
	status = "disabled";
};

&cp1_ethernet {
	status = "okay";
};

/* CON50 */
&cp1_eth0 {
	status = "okay";
	phy-mode = "10gbase-r";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy4 0>;
	managed = "in-band-status";
	sfp = <&cp1_sfp_eth1>;
};

&cp1_gpio1 {
	status = "okay";
};

&cp1_gpio2 {
	status = "okay";
};

&cp1_i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_i2c0_pins>;
	clock-frequency = <100000>;
};

/* CON40 */
&cp1_pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_pcie_reset_pins>;
	num-lanes = <2>;
	num-viewport = <8>;
	marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
	status = "okay";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy0 0
		&cp1_comphy1 0>;
};

&cp1_sata0 {
	status = "okay";

	/* CON32 */
	sata-port@1 {
		/* Generic PHY, providing serdes lanes */
		phys = <&cp1_comphy5 1>;
	};
};

/* U24 */
&cp1_spi1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_spi0_pins>;
	reg = <0x700680 0x50>;

	flash@0 {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		/* On-board MUX does not allow higher frequencies */
		spi-max-frequency = <40000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot-1";
				reg = <0x0 0x200000>;
			};

			partition@400000 {
				label = "Filesystem-1";
				reg = <0x200000 0xe00000>;
			};
		};
	};

};

&cp1_syscon0 {
	cp1_pinctrl: pinctrl {
		compatible = "marvell,cp115-standalone-pinctrl";

		cp1_i2c0_pins: cp1-i2c-pins-0 {
			marvell,pins = "mpp37", "mpp38";
			marvell,function = "i2c0";
		};
		cp1_spi0_pins: cp1-spi-pins-0 {
			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
			marvell,function = "spi1";
		};
		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
			marvell,pins = "mpp3";
			marvell,function = "gpio";
		};
		cp1_sfp_pins: sfp-pins {
			marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
			marvell,function = "gpio";
		};
		cp1_pcie_reset_pins: cp1-pcie-reset-pins {
			marvell,pins = "mpp0";
			marvell,function = "gpio";
		};
	};
};

/* CON58 */
&cp1_utmi {
	status = "okay";
};

&cp1_usb3_1 {
	status = "okay";
	usb-phy = <&cp1_usb3_0_phy0>;
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy3 1>, <&cp1_utmi1>;
	phy-names = "usb", "utmi";
	dr_mode = "host";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 Marvell International Ltd.
 *
 * Device tree for the CN9132-DB board.
 */

#include "cn9132-db.dtsi"

/ {
	model = "Marvell Armada CN9132-DB setup B";
};

/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
 */

&cp0_nand_controller {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2019 Marvell International Ltd.
 *
 * Device tree for the CN9132-DB board.
 */

#include "cn9132-db.dtsi"

/ {
	model = "Marvell Armada CN9132-DB setup A";
};

/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
 * simultaneously. When SPI controller is enabled, NAND should be disabled.
 */

&cp0_spi1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2020 Marvell International Ltd.
 *
 * Device tree for the CN9132-DB board.
 */

#include "cn9131-db.dtsi"

/ {
	compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
		     "marvell,armada-ap807-quad", "marvell,armada-ap807";

	aliases {
		gpio5 = &cp2_gpio1;
		gpio6 = &cp2_gpio2;
		ethernet5 = &cp2_eth0;
	};

	cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
		compatible = "regulator-fixed";
		regulator-name = "cp2-xhci0-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
	};

	cp2_usb3_0_phy0: cp2_usb3_phy0 {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&cp2_reg_usb3_vbus0>;
	};

	cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
		compatible = "regulator-fixed";
		regulator-name = "cp2-xhci1-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
	};

	cp2_usb3_0_phy1: cp2_usb3_phy1 {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&cp2_reg_usb3_vbus1>;
	};

	cp2_reg_sd_vccq: cp2_sd_vccq@0 {
		compatible = "regulator-gpio";
		regulator-name = "cp2_sd_vcc";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x1 3300000 0x0>;
	};

	cp2_sfp_eth0: sfp-eth0 {
		compatible = "sff,sfp";
		i2c-bus = <&cp2_sfpp0_i2c>;
		los-gpios = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
		tx-fault-gpios = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
		/*
		 * SFP cages are unconnected on early PCBs because of an the I2C
		 * lanes not being connected. Prevent the port for being
		 * unusable by disabling the SFP node.
		 */
		status = "disabled";
	};
};

/*
 * Instantiate the second slave CP115
 */

#define CP11X_NAME		cp2
#define CP11X_BASE		f6000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE	f6600000
#define CP11X_PCIE1_BASE	f6620000
#define CP11X_PCIE2_BASE	f6640000

#include "armada-cp115.dtsi"

#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE

&cp2_crypto {
	status = "disabled";
};

&cp2_ethernet {
	status = "okay";
};

/* SLM-1521-V2, CON9 */
&cp2_eth0 {
	status = "disabled";
	phy-mode = "10gbase-r";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp2_comphy4 0>;
	managed = "in-band-status";
	sfp = <&cp2_sfp_eth0>;
};

&cp2_gpio1 {
	status = "okay";
};

&cp2_gpio2 {
	status = "okay";
};

&cp2_i2c0 {
	clock-frequency = <100000>;

	/* SLM-1521-V2 - U3 */
	i2c-mux@72 {
		compatible = "nxp,pca9544";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x72>;
		cp2_sfpp0_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			/* U12 */
			cp2_module_expander1: pca9555@21 {
				compatible = "nxp,pca9555";
				pinctrl-names = "default";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x21>;
			};
		};
	};
};

/* SLM-1521-V2, CON6 */
&cp2_pcie0 {
	status = "okay";
	num-lanes = <2>;
	num-viewport = <8>;
	/* Generic PHY, providing serdes lanes */
	phys = <&cp2_comphy0 0
		&cp2_comphy1 0>;
};

/* SLM-1521-V2, CON8 */
&cp2_pcie2 {
	status = "okay";
	num-lanes = <1>;
	num-viewport = <8>;
	/* Generic PHY, providing serdes lanes */
	phys = <&cp2_comphy5 2>;
};

&cp2_sata0 {
	status = "okay";

	/* SLM-1521-V2, CON4 */
	sata-port@0 {
		/* Generic PHY, providing serdes lanes */
		phys = <&cp2_comphy2 0>;
	};
};

/* CON 2 on SLM-1683 - microSD */
&cp2_sdhci0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&cp2_sdhci_pins>;
	bus-width = <4>;
	cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
	vqmmc-supply = <&cp2_reg_sd_vccq>;
};

&cp2_syscon0 {
	cp2_pinctrl: pinctrl {
		compatible = "marvell,cp115-standalone-pinctrl";

		cp2_i2c0_pins: cp2-i2c-pins-0 {
			marvell,pins = "mpp37", "mpp38";
			marvell,function = "i2c0";
		};
		cp2_sdhci_pins: cp2-sdhi-pins-0 {
			marvell,pins = "mpp56", "mpp57", "mpp58",
				       "mpp59", "mpp60", "mpp61";
			marvell,function = "sdio";
		};
	};
};

&cp2_utmi {
	status = "okay";
};

&cp2_usb3_0 {
	status = "okay";
	usb-phy = <&cp2_usb3_0_phy0>;
	phys = <&cp2_utmi0>;
	phy-names = "usb";
	dr_mode = "host";
};

/* SLM-1521-V2, CON11 */
&cp2_usb3_1 {
	status = "okay";
	usb-phy = <&cp2_usb3_0_phy1>;
	/* Generic PHY, providing serdes lanes */
	phys = <&cp2_comphy3 1>, <&cp2_utmi1>;
	phy-names = "usb", "utmi";
	dr_mode = "host";
};


code:
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb


code:
/*
 * Copyright (c) 2017 MediaTek Inc.
 * Author: YT Shen <yt.shen@mediatek.com>
 *
 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
 */

/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "mt2712e.dtsi"

/ {
	model = "MediaTek MT2712 evaluation board";
	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";

	aliases {
		serial0 = &uart0;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x80000000>;
	};

	chosen {
		stdout-path = "serial0:921600n8";
	};

	cpus_fixed_vproc0: regulator-vproc-buck0 {
		compatible = "regulator-fixed";
		regulator-name = "vproc_buck0";
		regulator-min-microvolt = <1000000>;
		regulator-max-microvolt = <1000000>;
	};

	cpus_fixed_vproc1: regulator-vproc-buck1 {
		compatible = "regulator-fixed";
		regulator-name = "vproc_buck1";
		regulator-min-microvolt = <1000000>;
		regulator-max-microvolt = <1000000>;
	};

	extcon_usb: extcon_iddig {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&pio 12 GPIO_ACTIVE_HIGH>;
	};

	extcon_usb1: extcon_iddig1 {
		compatible = "linux,extcon-usb-gpio";
		id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>;
	};

	usb_p0_vbus: regulator-usb-p0-vbus {
		compatible = "regulator-fixed";
		regulator-name = "p0_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&pio 13 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	usb_p1_vbus: regulator-usb-p1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "p1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&pio 15 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	usb_p2_vbus: regulator-usb-p2-vbus {
		compatible = "regulator-fixed";
		regulator-name = "p2_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	usb_p3_vbus: regulator-usb-p3-vbus {
		compatible = "regulator-fixed";
		regulator-name = "p3_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&pio 17 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};

};

&auxadc {
	status = "okay";
};

&cpu0 {
	proc-supply = <&cpus_fixed_vproc0>;
};

&cpu1 {
	proc-supply = <&cpus_fixed_vproc0>;
};

&cpu2 {
	proc-supply = <&cpus_fixed_vproc1>;
};

&eth {
	phy-mode = "rgmii-rxid";
	phy-handle = <&ethernet_phy0>;
	mediatek,tx-delay-ps = <1530>;
	snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
	snps,reset-delays-us = <0 10000 10000>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&eth_default>;
	pinctrl-1 = <&eth_sleep>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		ethernet_phy0: ethernet-phy@5 {
			compatible = "ethernet-phy-id0243.0d90";
			reg = <0x5>;
		};
	};
};

&pio {
	eth_default: eth_default {
		tx_pins {
			pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
				 <MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
				 <MT2712_PIN_73_GBE_TXD1__FUNC_GBE_TXD1>,
				 <MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0>,
				 <MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC>,
				 <MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN>;
			drive-strength = <MTK_DRIVE_8mA>;
		};
		rx_pins {
			pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3>,
				 <MT2712_PIN_79_GBE_RXD2__FUNC_GBE_RXD2>,
				 <MT2712_PIN_80_GBE_RXD1__FUNC_GBE_RXD1>,
				 <MT2712_PIN_81_GBE_RXD0__FUNC_GBE_RXD0>,
				 <MT2712_PIN_82_GBE_RXDV__FUNC_GBE_RXDV>,
				 <MT2712_PIN_84_GBE_RXC__FUNC_GBE_RXC>;
			input-enable;
		};
		mdio_pins {
			pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC>,
				 <MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO>;
			drive-strength = <MTK_DRIVE_8mA>;
			input-enable;
		};
	};

	eth_sleep: eth_sleep {
		tx_pins {
			pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
				 <MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
				 <MT2712_PIN_73_GBE_TXD1__FUNC_GPIO73>,
				 <MT2712_PIN_74_GBE_TXD0__FUNC_GPIO74>,
				 <MT2712_PIN_75_GBE_TXC__FUNC_GPIO75>,
				 <MT2712_PIN_76_GBE_TXEN__FUNC_GPIO76>;
		};
		rx_pins {
			pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GPIO78>,
				 <MT2712_PIN_79_GBE_RXD2__FUNC_GPIO79>,
				 <MT2712_PIN_80_GBE_RXD1__FUNC_GPIO80>,
				 <MT2712_PIN_81_GBE_RXD0__FUNC_GPIO81>,
				 <MT2712_PIN_82_GBE_RXDV__FUNC_GPIO82>,
				 <MT2712_PIN_84_GBE_RXC__FUNC_GPIO84>;
			input-disable;
		};
		mdio_pins {
			pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GPIO85>,
				 <MT2712_PIN_86_GBE_MDIO__FUNC_GPIO86>;
			input-disable;
			bias-disable;
		};
	};

	usb0_id_pins_float: usb0_iddig {
		pins_iddig {
			pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
			bias-pull-up;
		};
	};

	usb1_id_pins_float: usb1_iddig {
		pins_iddig {
			pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
			bias-pull-up;
		};
	};
};

&ssusb {
	vbus-supply = <&usb_p0_vbus>;
	extcon = <&extcon_usb>;
	dr_mode = "otg";
	wakeup-source;
	mediatek,u3p-dis-msk = <0x1>;
	//enable-manual-drd;
	//maximum-speed = "full-speed";
	pinctrl-names = "default";
	pinctrl-0 = <&usb0_id_pins_float>;
	status = "okay";
};

&ssusb1 {
	vbus-supply = <&usb_p1_vbus>;
	extcon = <&extcon_usb1>;
	dr_mode = "otg";
	//mediatek,u3p-dis-msk = <0x1>;
	enable-manual-drd;
	wakeup-source;
	//maximum-speed = "full-speed";
	pinctrl-names = "default";
	pinctrl-0 = <&usb1_id_pins_float>;
	status = "okay";
};

&uart0 {
	status = "okay";
};

&usb_host0 {
	vbus-supply = <&usb_p2_vbus>;
	status = "okay";
};

&usb_host1 {
	status = "okay";
};