code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/bosch,m_can.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Bosch MCAN controller Bindings

description: Bosch MCAN controller for CAN bus

maintainers:
  - Chandrasekar Ramakrishnan <rcsekar@samsung.com>

allOf:
  - $ref: can-controller.yaml#

properties:
  compatible:
    const: bosch,m_can

  reg:
    items:
      - description: M_CAN registers map
      - description: message RAM

  reg-names:
    items:
      - const: m_can
      - const: message_ram

  interrupts:
    items:
      - description: interrupt line0
      - description: interrupt line1
    minItems: 1

  interrupt-names:
    items:
      - const: int0
      - const: int1
    minItems: 1

  clocks:
    items:
      - description: peripheral clock
      - description: bus clock

  clock-names:
    items:
      - const: hclk
      - const: cclk

  bosch,mram-cfg:
    description: |
      Message RAM configuration data.
      Multiple M_CAN instances can share the same Message RAM
      and each element(e.g Rx FIFO or Tx Buffer and etc) number
      in Message RAM is also configurable, so this property is
      telling driver how the shared or private Message RAM are
      used by this M_CAN controller.

      The format should be as follows:
      <offset sidf_elems xidf_elems rxf0_elems rxf1_elems rxb_elems txe_elems txb_elems>
      The 'offset' is an address offset of the Message RAM where
      the following elements start from. This is usually set to
      0x0 if you're using a private Message RAM. The remain cells
      are used to specify how many elements are used for each FIFO/Buffer.

      M_CAN includes the following elements according to user manual:
      11-bit Filter	0-128 elements / 0-128 words
      29-bit Filter	0-64 elements / 0-128 words
      Rx FIFO 0		0-64 elements / 0-1152 words
      Rx FIFO 1		0-64 elements / 0-1152 words
      Rx Buffers	0-64 elements / 0-1152 words
      Tx Event FIFO	0-32 elements / 0-64 words
      Tx Buffers	0-32 elements / 0-576 words

      Please refer to 2.4.1 Message RAM Configuration in Bosch
      M_CAN user manual for details.
    $ref: /schemas/types.yaml#/definitions/int32-array
    items:
      - description: The 'offset' is an address offset of the Message RAM where
          the following elements start from. This is usually set to 0x0 if
          you're using a private Message RAM.
        default: 0
      - description: 11-bit Filter 0-128 elements / 0-128 words
        minimum: 0
        maximum: 128
      - description: 29-bit Filter 0-64 elements / 0-128 words
        minimum: 0
        maximum: 64
      - description: Rx FIFO 0 0-64 elements / 0-1152 words
        minimum: 0
        maximum: 64
      - description: Rx FIFO 1 0-64 elements / 0-1152 words
        minimum: 0
        maximum: 64
      - description: Rx Buffers 0-64 elements / 0-1152 words
        minimum: 0
        maximum: 64
      - description: Tx Event FIFO 0-32 elements / 0-64 words
        minimum: 0
        maximum: 32
      - description: Tx Buffers 0-32 elements / 0-576 words
        minimum: 0
        maximum: 32
    minItems: 1

  power-domains:
    description:
      Power domain provider node and an args specifier containing
      the can device id value.
    maxItems: 1

  can-transceiver:
    $ref: can-transceiver.yaml#

  phys:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - bosch,mram-cfg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx6sx-clock.h>
    can@20e8000 {
      compatible = "bosch,m_can";
      reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
      reg-names = "m_can", "message_ram";
      interrupts = <0 114 0x04>, <0 114 0x04>;
      interrupt-names = "int0", "int1";
      clocks = <&clks IMX6SX_CLK_CANFD>,
               <&clks IMX6SX_CLK_CANFD>;
      clock-names = "hclk", "cclk";
      bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;

      can-transceiver {
        max-bitrate = <5000000>;
      };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/can-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: CAN Controller Generic Binding

maintainers:
  - Marc Kleine-Budde <mkl@pengutronix.de>

properties:
  $nodename:
    pattern: "^can(@.*)?$"

  termination-gpios:
    description: GPIO pin to enable CAN bus termination.
    maxItems: 1

  termination-ohms:
    description: The resistance value of the CAN bus termination resistor.
    minimum: 1
    maximum: 65535

additionalProperties: true

...

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/can-transceiver.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: CAN transceiver Bindings

description: CAN transceiver generic properties bindings

maintainers:
  - Rob Herring <robh@kernel.org>

properties:
  max-bitrate:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: a positive non 0 value that determines the max speed that CAN/CAN-FD can run.
    minimum: 1

additionalProperties: true


code:
Memory mapped Bosch CC770 and Intel AN82527 CAN controller

Note: The CC770 is a CAN controller from Bosch, which is 100%
compatible with the old AN82527 from Intel, but with "bugs" being fixed.

Required properties:

- compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
	for the AN82527.

- reg : should specify the chip select, address offset and size required
	to map the registers of the controller. The size is usually 0x80.

- interrupts : property with a value describing the interrupt source
	(number and sensitivity) required for the controller.

Optional properties:

- bosch,external-clock-frequency : frequency of the external oscillator
	clock in Hz. Note that the internal clock frequency used by the
	controller is half of that value. If not specified, a default
	value of 16000000 (16 MHz) is used.

- bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
	If not specified or if the specified value is 0, the CLKOUT pin
	will be disabled.

- bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
	a resonable value will be calculated.

- bosch,disconnect-rx0-input : see data sheet.

- bosch,disconnect-rx1-input : see data sheet.

- bosch,disconnect-tx1-output : see data sheet.

- bosch,polarity-dominant : see data sheet.

- bosch,divide-memory-clock : see data sheet.

- bosch,iso-low-speed-mux : see data sheet.

For further information, please have a look to the CC770 or AN82527.

Examples:

can@3,100 {
	compatible = "bosch,cc770";
	reg = <3 0x100 0x80>;
	interrupts = <2 0>;
	interrupt-parent = <&mpic>;
	bosch,external-clock-frequency = <16000000>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/ctu,ctucanfd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: CTU CAN FD Open-source IP Core Device Tree Bindings

description: |
  Open-source CAN FD IP core developed at the Czech Technical University in Prague

  The core sources and documentation on project page
    [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
    [2] datasheet : https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf

  Integration in Xilinx Zynq SoC based system together with
  OpenCores SJA1000 compatible controllers
    [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
  Martin Jerabek dimploma thesis with integration and testing
  framework description
    [4] PDF : https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-canfd.pdf

maintainers:
  - Pavel Pisa <pisa@cmp.felk.cvut.cz>
  - Ondrej Ille <ondrej.ille@gmail.com>
  - Martin Jerabek <martin.jerabek01@gmail.com>

allOf:
  - $ref: can-controller.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - const: ctu,ctucanfd-2
          - const: ctu,ctucanfd
      - const: ctu,ctucanfd

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    description: |
      phandle of reference clock (100 MHz is appropriate
      for FPGA implementation on Zynq-7000 system).
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    ctu_can_fd_0: can@43c30000 {
      compatible = "ctu,ctucanfd";
      interrupts = <0 30 4>;
      clocks = <&clkc 15>;
      reg = <0x43c30000 0x10000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/fsl,flexcan.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title:
  Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).

maintainers:
  - Marc Kleine-Budde <mkl@pengutronix.de>

allOf:
  - $ref: can-controller.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx93-flexcan
          - fsl,imx8qm-flexcan
          - fsl,imx8mp-flexcan
          - fsl,imx6q-flexcan
          - fsl,imx28-flexcan
          - fsl,imx25-flexcan
          - fsl,p1010-flexcan
          - fsl,vf610-flexcan
          - fsl,ls1021ar2-flexcan
          - fsl,lx2160ar1-flexcan
      - items:
          - enum:
              - fsl,imx53-flexcan
              - fsl,imx35-flexcan
          - const: fsl,imx25-flexcan
      - items:
          - enum:
              - fsl,imx7d-flexcan
              - fsl,imx6ul-flexcan
              - fsl,imx6sx-flexcan
          - const: fsl,imx6q-flexcan
      - items:
          - enum:
              - fsl,ls1028ar1-flexcan
          - const: fsl,lx2160ar1-flexcan

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: ipg
      - const: per

  clock-frequency:
    description: |
      The oscillator frequency driving the flexcan device, filled in by the
      boot loader. This property should only be used the used operating system
      doesn't support the clocks and clock-names property.

  xceiver-supply:
    description: Regulator that powers the CAN transceiver.

  big-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description: |
      This means the registers of FlexCAN controller are big endian. This is
      optional property.i.e. if this property is not present in device tree
      node then controller is assumed to be little endian. If this property is
      present then controller is assumed to be big endian.

  fsl,stop-mode:
    description: |
      Register bits of stop mode control.

      The format should be as follows:
      <gpr req_gpr req_bit>
      gpr is the phandle to general purpose register node.
      req_gpr is the gpr register offset of CAN stop request.
      req_bit is the bit offset of CAN stop request.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: The 'gpr' is the phandle to general purpose register node.
          - description: The 'req_gpr' is the gpr register offset of CAN stop request.
            maximum: 0xff
          - description: The 'req_bit' is the bit offset of CAN stop request.
            maximum: 0x1f

  fsl,clk-source:
    description: |
      Select the clock source to the CAN Protocol Engine (PE). It's SoC
      implementation dependent. Refer to RM for detailed definition. If this
      property is not set in device tree node then driver selects clock source 1
      by default.
      0: clock source 0 (oscillator clock)
      1: clock source 1 (peripheral clock)
    $ref: /schemas/types.yaml#/definitions/uint8
    default: 1
    minimum: 0
    maximum: 1

  wakeup-source:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Enable CAN remote wakeup.

  fsl,scu-index:
    description: |
      The scu index of CAN instance.
      For SoCs with SCU support, need setup stop mode via SCU firmware, so this
      property can help indicate a resource. It supports up to 3 CAN instances
      now.
    $ref: /schemas/types.yaml#/definitions/uint8
    minimum: 0
    maximum: 2

  termination-gpios: true
  termination-ohms: true

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    can@1c000 {
        compatible = "fsl,p1010-flexcan";
        reg = <0x1c000 0x1000>;
        interrupts = <48 0x2>;
        interrupt-parent = <&mpic>;
        clock-frequency = <200000000>;
        fsl,clk-source = /bits/ 8 <0>;
    };
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    can@2090000 {
        compatible = "fsl,imx6q-flexcan";
        reg = <0x02090000 0x4000>;
        interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clks 1>, <&clks 2>;
        clock-names = "ipg", "per";
        fsl,stop-mode = <&gpr 0x34 28>;
        fsl,scu-index = /bits/ 8 <1>;
    };
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>

    can@2090000 {
        compatible = "fsl,imx6q-flexcan";
        reg = <0x02090000 0x4000>;
        interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clks 1>, <&clks 2>;
        clock-names = "ipg", "per";
        fsl,stop-mode = <&gpr 0x34 28>;
        termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
        termination-ohms = <120>;
    };


code:
Aeroflex Gaisler GRCAN and GRHCAN CAN controllers.

The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core
library.

Note: These properties are built from the AMBA plug&play in a Leon SPARC system
(the ordinary environment for GRCAN and GRHCAN). There are no dts files for
sparc.

Required properties:

- name : Should be "GAISLER_GRCAN", "01_03d", "GAISLER_GRHCAN" or "01_034"

- reg : Address and length of the register set for the device

- freq : Frequency of the external oscillator clock in Hz (the frequency of
	the amba bus in the ordinary case)

- interrupts : Interrupt number for this device

Optional properties:

- systemid : If not present or if the value of the least significant 16 bits
	of this 32-bit property is smaller than GRCAN_TXBUG_SAFE_GRLIB_VERSION
	a bug workaround is activated.

For further information look in the documentation for the GLIB IP core library:
http://www.gaisler.com/products/grlib/grip.pdf


code:
* Holt HI-311X stand-alone CAN controller device tree bindings

Required properties:
 - compatible: Should be one of the following:
   - "holt,hi3110" for HI-3110
 - reg: SPI chip select.
 - clocks: The clock feeding the CAN controller.
 - interrupts: Should contain IRQ line for the CAN controller.

Optional properties:
 - vdd-supply: Regulator that powers the CAN controller.
 - xceiver-supply: Regulator that powers the CAN transceiver.

Example:
	can0: can@1 {
		compatible = "holt,hi3110";
		reg = <1>;
		clocks = <&clk32m>;
		interrupt-parent = <&gpio4>;
		interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
		vdd-supply = <&reg5v0>;
		xceiver-supply = <&reg5v0>;
	};


code:
IFI CANFD controller
--------------------

Required properties:
  - compatible: Should be "ifi,canfd-1.0"
  - reg: Should contain CAN controller registers location and length
  - interrupts: Should contain IRQ line for the CAN controller

Example:

	canfd0: canfd@ff220000 {
		compatible = "ifi,canfd-1.0";
		reg = <0xff220000 0x00001000>;
		interrupts = <0 43 0>;
	};


code:
* Microchip MCP251X stand-alone CAN controller device tree bindings

Required properties:
 - compatible: Should be one of the following:
   - "microchip,mcp2510" for MCP2510.
   - "microchip,mcp2515" for MCP2515.
   - "microchip,mcp25625" for MCP25625.
 - reg: SPI chip select.
 - clocks: The clock feeding the CAN controller.
 - interrupts: Should contain IRQ line for the CAN controller.

Optional properties:
 - vdd-supply: Regulator that powers the CAN controller.
 - xceiver-supply: Regulator that powers the CAN transceiver.
 - gpio-controller: Indicates this device is a GPIO controller.
 - #gpio-cells: Should be two. The first cell is the pin number and
                the second cell is used to specify the gpio polarity.

Example:
	can0: can@1 {
		compatible = "microchip,mcp2515";
		reg = <1>;
		clocks = <&clk24m>;
		interrupt-parent = <&gpio4>;
		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
		vdd-supply = <&reg5v0>;
		xceiver-supply = <&reg5v0>;
		gpio-controller;
		#gpio-cells = <2>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/microchip,mcp251xfd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title:
  Microchip MCP2517FD, MCP2518FD and MCP251863 stand-alone CAN
  controller device tree bindings

maintainers:
  - Marc Kleine-Budde <mkl@pengutronix.de>

allOf:
  - $ref: can-controller.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - microchip,mcp2517fd
          - microchip,mcp2518fd
          - microchip,mcp251xfd
      - items:
          - enum:
              - microchip,mcp251863
          - const: microchip,mcp2518fd
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  vdd-supply:
    description: Regulator that powers the CAN controller.

  xceiver-supply:
    description: Regulator that powers the CAN transceiver.

  microchip,rx-int-gpios:
    description:
      GPIO phandle of GPIO connected to to INT1 pin of the MCP251XFD, which
      signals a pending RX interrupt.
    maxItems: 1

  spi-max-frequency:
    description:
      Must be half or less of "clocks" frequency.
    maximum: 20000000

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    spi0 {
        #address-cells = <1>;
        #size-cells = <0>;

        can@0 {
            compatible = "microchip,mcp251xfd";
            reg = <0>;
            clocks = <&can0_osc>;
            pinctrl-names = "default";
            pinctrl-0 = <&can0_pins>;
            spi-max-frequency = <20000000>;
            interrupts-extended = <&gpio 13 IRQ_TYPE_LEVEL_LOW>;
            microchip,rx-int-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
            vdd-supply = <&reg5v0>;
            xceiver-supply = <&reg5v0>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/microchip,mpfs-can.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title:
  Microchip PolarFire SoC (MPFS) can controller

maintainers:
  - Conor Dooley <conor.dooley@microchip.com>

allOf:
  - $ref: can-controller.yaml#

properties:
  compatible:
    const: microchip,mpfs-can

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    can@2010c000 {
        compatible = "microchip,mpfs-can";
        reg = <0x2010c000 0x1000>;
        clocks = <&clkcfg 17>;
        interrupt-parent = <&plic>;
        interrupts = <56>;
    };


code:
CAN Device Tree Bindings
------------------------

(c) 2006-2009 Secret Lab Technologies Ltd
Grant Likely <grant.likely@secretlab.ca>

fsl,mpc5200-mscan nodes
-----------------------
In addition to the required compatible-, reg- and interrupt-properties, you can
also specify which clock source shall be used for the controller:

- fsl,mscan-clock-source : a string describing the clock source. Valid values
			   are:	"ip" for ip bus clock
				 "ref" for reference clock (XTAL)
			   "ref" is default in case this property is not
			   present.

fsl,mpc5121-mscan nodes
-----------------------
In addition to the required compatible-, reg- and interrupt-properties, you can
also specify which clock source and divider shall be used for the controller:

- fsl,mscan-clock-source : a string describing the clock source. Valid values
			   are:	"ip" for ip bus clock
				"ref" for reference clock
				"sys" for system clock
			   If this property is not present, an optimal CAN
			   clock source and frequency based on the system
			   clock will be selected. If this is not possible,
			   the reference clock will be used.

- fsl,mscan-clock-divider: for the reference and system clock, an additional
			   clock divider can be specified. By default, a
			   value of 1 is used.

Note that the MPC5121 Rev. 1 processor is not supported.

Examples:
	can@1300 {
		compatible = "fsl,mpc5121-mscan";
		interrupts = <12 0x8>;
		interrupt-parent = <&ipic>;
		reg = <0x1300 0x80>;
	};

	can@1380 {
		compatible = "fsl,mpc5121-mscan";
		interrupts = <13 0x8>;
		interrupt-parent = <&ipic>;
		reg = <0x1380 0x80>;
		fsl,mscan-clock-source = "ref";
		fsl,mscan-clock-divider = <3>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/nxp,sja1000.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Memory mapped SJA1000 CAN controller from NXP (formerly Philips)

maintainers:
  - Wolfgang Grandegger <wg@grandegger.com>

properties:
  compatible:
    oneOf:
      - enum:
          - nxp,sja1000
          - technologic,sja1000
      - items:
          - enum:
              - renesas,r9a06g032-sja1000 # RZ/N1D
              - renesas,r9a06g033-sja1000 # RZ/N1S
          - const: renesas,rzn1-sja1000 # RZ/N1

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  reg-io-width:
    description: I/O register width (in bytes) implemented by this device
    default: 1
    enum: [ 1, 2, 4 ]

  nxp,external-clock-frequency:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 16000000
    description: |
      Frequency of the external oscillator clock in Hz.
      The internal clock frequency used by the SJA1000 is half of that value.

  nxp,tx-output-mode:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 0, 1, 2, 3 ]
    default: 1
    description: |
      operation mode of the TX output control logic. Valid values are:
        <0> : bi-phase output mode
        <1> : normal output mode (default)
        <2> : test output mode
        <3> : clock output mode

  nxp,tx-output-config:
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0x02
    description: |
      TX output pin configuration. Valid values are any one of the below
      or combination of TX0 and TX1:
        <0x01> : TX0 invert
        <0x02> : TX0 pull-down (default)
        <0x04> : TX0 pull-up
        <0x06> : TX0 push-pull
        <0x08> : TX1 invert
        <0x10> : TX1 pull-down
        <0x20> : TX1 pull-up
        <0x30> : TX1 push-pull

  nxp,clock-out-frequency:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      clock frequency in Hz on the CLKOUT pin.
      If not specified or if the specified value is 0, the CLKOUT pin
      will be disabled.

  nxp,no-comparator-bypass:
    type: boolean
    description: Allows to disable the CAN input comparator.

required:
  - compatible
  - reg
  - interrupts

allOf:
  - $ref: can-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - technologic,sja1000
              - renesas,rzn1-sja1000
    then:
      required:
        - reg-io-width
  - if:
      properties:
        compatible:
          contains:
            const: renesas,rzn1-sja1000
    then:
      required:
        - clocks
        - power-domains

unevaluatedProperties: false

examples:
  - |
    can@1a000 {
        compatible = "technologic,sja1000";
        reg = <0x1a000 0x100>;
        interrupts = <1>;
        reg-io-width = <2>;
        nxp,tx-output-config = <0x06>;
        nxp,external-clock-frequency = <24000000>;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/r9a06g032-sysctrl.h>

    can@52104000 {
        compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
        reg = <0x52104000 0x800>;
        reg-io-width = <4>;
        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
        power-domains = <&sysctrl>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car CAN Controller

maintainers:
  - Sergei Shtylyov <sergei.shtylyov@gmail.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,can-r8a7778      # R-Car M1-A
              - renesas,can-r8a7779      # R-Car H1
          - const: renesas,rcar-gen1-can # R-Car Gen1

      - items:
          - enum:
              - renesas,can-r8a7742      # RZ/G1H
              - renesas,can-r8a7743      # RZ/G1M
              - renesas,can-r8a7744      # RZ/G1N
              - renesas,can-r8a7745      # RZ/G1E
              - renesas,can-r8a77470     # RZ/G1C
              - renesas,can-r8a7790      # R-Car H2
              - renesas,can-r8a7791      # R-Car M2-W
              - renesas,can-r8a7792      # R-Car V2H
              - renesas,can-r8a7793      # R-Car M2-N
              - renesas,can-r8a7794      # R-Car E2
          - const: renesas,rcar-gen2-can # R-Car Gen2 and RZ/G1

      - items:
          - enum:
              - renesas,can-r8a774a1     # RZ/G2M
              - renesas,can-r8a774b1     # RZ/G2N
              - renesas,can-r8a774c0     # RZ/G2E
              - renesas,can-r8a774e1     # RZ/G2H
              - renesas,can-r8a7795      # R-Car H3
              - renesas,can-r8a7796      # R-Car M3-W
              - renesas,can-r8a77961     # R-Car M3-W+
              - renesas,can-r8a77965     # R-Car M3-N
              - renesas,can-r8a77990     # R-Car E3
              - renesas,can-r8a77995     # R-Car D3
          - const: renesas,rcar-gen3-can # R-Car Gen3 and RZ/G2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: clkp1
      - const: clkp2
      - const: can_clk

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  renesas,can-clock-select:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 0, 1, 3 ]
    default: 0
    description: |
      R-Car CAN Clock Source Select.  Valid values are:
        <0x0> (default) : Peripheral clock (clkp1)
        <0x1> : Peripheral clock (clkp2)
        <0x3> : External input clock

  assigned-clocks:
    description:
      Reference to the clkp2 (CANFD) clock.
      On R-Car Gen3 and RZ/G2 SoCs, "clkp2" is the CANFD clock.  This is a div6
      clock and can be used by both CAN and CAN FD controllers at the same
      time.  It needs to be scaled to maximum frequency if any of these
      controllers use it.

  assigned-clock-rates:
    description: Maximum frequency of the CANFD clock.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains

allOf:
  - $ref: can-controller.yaml#

  - if:
      not:
        properties:
          compatible:
            contains:
              const: renesas,rcar-gen1-can
    then:
      required:
        - resets

  - if:
      properties:
        compatible:
          contains:
            const: renesas,rcar-gen3-can
    then:
      required:
        - assigned-clocks
        - assigned-clock-rates

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7791-sysc.h>

    can0: can@e6e80000 {
            compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
            reg = <0xe6e80000 0x1000>;
            interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 916>,
                     <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
            clock-names = "clkp1", "clkp2", "can_clk";
            power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
            resets = <&cpg 916>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas R-Car CAN FD Controller

maintainers:
  - Fabrizio Castro <fabrizio.castro.jz@renesas.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,r8a774a1-canfd     # RZ/G2M
              - renesas,r8a774b1-canfd     # RZ/G2N
              - renesas,r8a774c0-canfd     # RZ/G2E
              - renesas,r8a774e1-canfd     # RZ/G2H
              - renesas,r8a7795-canfd      # R-Car H3
              - renesas,r8a7796-canfd      # R-Car M3-W
              - renesas,r8a77961-canfd     # R-Car M3-W+
              - renesas,r8a77965-canfd     # R-Car M3-N
              - renesas,r8a77970-canfd     # R-Car V3M
              - renesas,r8a77980-canfd     # R-Car V3H
              - renesas,r8a77990-canfd     # R-Car E3
              - renesas,r8a77995-canfd     # R-Car D3
          - const: renesas,rcar-gen3-canfd # R-Car Gen3 and RZ/G2

      - items:
          - enum:
              - renesas,r9a07g043-canfd    # RZ/G2UL and RZ/Five
              - renesas,r9a07g044-canfd    # RZ/G2{L,LC}
              - renesas,r9a07g054-canfd    # RZ/V2L
          - const: renesas,rzg2l-canfd     # RZ/G2L family

      - const: renesas,r8a779a0-canfd      # R-Car V3U

  reg:
    maxItems: 1

  interrupts: true

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: fck
      - const: canfd
      - const: can_clk

  power-domains:
    maxItems: 1

  resets: true

  renesas,no-can-fd:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      The controller can operate in either CAN FD only mode (default) or
      Classical CAN only mode.  The mode is global to both the channels.
      Specify this property to put the controller in Classical CAN only mode.

  assigned-clocks:
    description:
      Reference to the CANFD clock.  The CANFD clock is a div6 clock and can be
      used by both CAN (if present) and CAN FD controllers at the same time.
      It needs to be scaled to maximum frequency if any of these controllers
      use it.

  assigned-clock-rates:
    description: Maximum frequency of the CANFD clock.

patternProperties:
  "^channel[0-7]$":
    type: object
    description:
      The controller supports multiple channels and each is represented as a
      child node.  Each channel can be enabled/disabled individually.

    additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - interrupt-names
  - clocks
  - clock-names
  - power-domains
  - resets
  - assigned-clocks
  - assigned-clock-rates
  - channel0
  - channel1

allOf:
  - $ref: can-controller.yaml#

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,rzg2l-canfd
    then:
      properties:
        interrupts:
          items:
            - description: CAN global error interrupt
            - description: CAN receive FIFO interrupt
            - description: CAN0 error interrupt
            - description: CAN0 transmit interrupt
            - description: CAN0 transmit/receive FIFO receive completion interrupt
            - description: CAN1 error interrupt
            - description: CAN1 transmit interrupt
            - description: CAN1 transmit/receive FIFO receive completion interrupt

        interrupt-names:
          items:
            - const: g_err
            - const: g_recc
            - const: ch0_err
            - const: ch0_rec
            - const: ch0_trx
            - const: ch1_err
            - const: ch1_rec
            - const: ch1_trx

        resets:
          maxItems: 2

        reset-names:
          items:
            - const: rstp_n
            - const: rstc_n

      required:
        - reset-names
    else:
      properties:
        interrupts:
          items:
            - description: Channel interrupt
            - description: Global interrupt

        interrupt-names:
          items:
            - const: ch_int
            - const: g_int

        resets:
          maxItems: 1

  - if:
      not:
        properties:
          compatible:
            contains:
              const: renesas,r8a779a0-canfd
    then:
      patternProperties:
        "^channel[2-7]$": false

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7795-sysc.h>

    canfd: can@e66c0000 {
            compatible = "renesas,r8a7795-canfd",
                         "renesas,rcar-gen3-canfd";
            reg = <0xe66c0000 0x8000>;
            interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "ch_int", "g_int";
            clocks = <&cpg CPG_MOD 914>,
                     <&cpg CPG_CORE R8A7795_CLK_CANFD>,
                     <&can_clk>;
            clock-names = "fck", "canfd", "can_clk";
            assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
            assigned-clock-rates = <40000000>;
            power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
            resets = <&cpg 914>;

            channel0 {
            };

            channel1 {
            };
    };


code:
Texas Instruments TCAN4x5x CAN Controller
================================================

This file provides device node information for the TCAN4x5x interface contains.

Required properties:
	- compatible: "ti,tcan4x5x"
	- reg: 0
	- #address-cells: 1
	- #size-cells: 0
	- spi-max-frequency: Maximum frequency of the SPI bus the chip can
			     operate at should be less than or equal to 18 MHz.
	- interrupt-parent: the phandle to the interrupt controller which provides
                    the interrupt.
	- interrupts: interrupt specification for data-ready.

See Documentation/devicetree/bindings/net/can/bosch,m_can.yaml for additional
required property details.

Optional properties:
	- reset-gpios: Hardwired output GPIO. If not defined then software
		       reset.
	- device-state-gpios: Input GPIO that indicates if the device is in
			      a sleep state or if the device is active.
	- device-wake-gpios: Wake up GPIO to wake up the TCAN device.

Example:
tcan4x5x: tcan4x5x@0 {
		compatible = "ti,tcan4x5x";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <10000000>;
		bosch,mram-cfg = <0x0 0 0 16 0 0 1 1>;
		interrupt-parent = <&gpio1>;
		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
		device-state-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
		device-wake-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
};


code:
Texas Instruments High End CAN Controller (HECC)
================================================

This file provides information, what the device node
for the hecc interface contains.

Required properties:
- compatible: "ti,am3517-hecc"
- reg: addresses and lengths of the register spaces for 'hecc', 'hecc-ram'
       and 'mbx'
- reg-names :"hecc", "hecc-ram", "mbx"
- interrupts: interrupt mapping for the hecc interrupts sources
- clocks: clock phandles (see clock bindings for details)

Optional properties:
- ti,use-hecc1int: if provided configures HECC to produce all interrupts
		   on HECC1INT interrupt line. By default HECC0INT interrupt
		   line will be used.
- xceiver-supply: regulator that powers the CAN transceiver

Example:

For am3517evm board:
	hecc: can@5c050000 {
		compatible = "ti,am3517-hecc";
		reg = <0x5c050000 0x80>,
		      <0x5c053000 0x180>,
		      <0x5c052000 0x200>;
		reg-names = "hecc", "hecc-ram", "mbx";
		interrupts = <24>;
		clocks = <&hecc_ck>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/can/xilinx,can.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title:
  Xilinx Axi CAN/Zynq CANPS controller

maintainers:
  - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>

properties:
  compatible:
    enum:
      - xlnx,zynq-can-1.0
      - xlnx,axi-can-1.00.a
      - xlnx,canfd-1.0
      - xlnx,canfd-2.0

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    maxItems: 2

  power-domains:
    maxItems: 1

  tx-fifo-depth:
    $ref: "/schemas/types.yaml#/definitions/uint32"
    description: CAN Tx fifo depth (Zynq, Axi CAN).

  rx-fifo-depth:
    $ref: "/schemas/types.yaml#/definitions/uint32"
    description: CAN Rx fifo depth (Zynq, Axi CAN, CAN FD in sequential Rx mode)

  tx-mailbox-count:
    $ref: "/schemas/types.yaml#/definitions/uint32"
    description: CAN Tx mailbox buffer count (CAN FD)

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

allOf:
  - $ref: can-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - xlnx,zynq-can-1.0

    then:
      properties:
        clock-names:
          items:
            - const: can_clk
            - const: pclk
      required:
        - tx-fifo-depth
        - rx-fifo-depth

  - if:
      properties:
        compatible:
          contains:
            enum:
              - xlnx,axi-can-1.00.a

    then:
      properties:
        clock-names:
          items:
            - const: can_clk
            - const: s_axi_aclk
      required:
        - tx-fifo-depth
        - rx-fifo-depth

  - if:
      properties:
        compatible:
          contains:
            enum:
              - xlnx,canfd-1.0
              - xlnx,canfd-2.0

    then:
      properties:
        clock-names:
          items:
            - const: can_clk
            - const: s_axi_aclk
      required:
        - tx-mailbox-count
        - rx-fifo-depth

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    can@e0008000 {
        compatible = "xlnx,zynq-can-1.0";
        reg = <0xe0008000 0x1000>;
        clocks = <&clkc 19>, <&clkc 36>;
        clock-names = "can_clk", "pclk";
        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-parent = <&intc>;
        tx-fifo-depth = <0x40>;
        rx-fifo-depth = <0x40>;
    };

  - |
    can@40000000 {
        compatible = "xlnx,axi-can-1.00.a";
        reg = <0x40000000 0x10000>;
        clocks = <&clkc 0>, <&clkc 1>;
        clock-names = "can_clk", "s_axi_aclk";
        interrupt-parent = <&intc>;
        interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
        tx-fifo-depth = <0x40>;
        rx-fifo-depth = <0x40>;
    };

  - |
    can@40000000 {
        compatible = "xlnx,canfd-1.0";
        reg = <0x40000000 0x2000>;
        clocks = <&clkc 0>, <&clkc 1>;
        clock-names = "can_clk", "s_axi_aclk";
        interrupt-parent = <&intc>;
        interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
        tx-mailbox-count = <0x20>;
        rx-fifo-depth = <0x20>;
    };

  - |
    can@ff060000 {
        compatible = "xlnx,canfd-2.0";
        reg = <0xff060000 0x6000>;
        clocks = <&clkc 0>, <&clkc 1>;
        clock-names = "can_clk", "s_axi_aclk";
        interrupt-parent = <&intc>;
        interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
        tx-mailbox-count = <0x20>;
        rx-fifo-depth = <0x40>;
    };


code:
* System Management Interface (SMI) / MDIO

Properties:
- compatible: One of:

   "cavium,octeon-3860-mdio": Compatibility with all cn3XXX, cn5XXX
                       and cn6XXX SOCs.

   "cavium,thunder-8890-mdio": Compatibility with all cn8XXX SOCs.

- reg: The base address of the MDIO bus controller register bank.

- #address-cells: Must be <1>.

- #size-cells: Must be <0>.  MDIO addresses have no size component.

Typically an MDIO bus might have several children.

Example:
	mdio@1180000001800 {
		compatible = "cavium,octeon-3860-mdio";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x11800 0x00001800 0x0 0x40>;

		ethernet-phy@0 {
			...
			reg = <0>;
		};
	};

* System Management Interface (SMI) / MDIO Nexus

  Several mdio buses may be gathered as children of a single PCI
  device, this PCI device is the nexus of the buses.

Properties:

- compatible: "cavium,thunder-8890-mdio-nexus";

- reg: The PCI device and function numbers of the nexus device.

- #address-cells: Must be <2>.

- #size-cells: Must be <2>.

- ranges: As needed for mapping of the MDIO bus device registers.

- assigned-addresses: As needed for mapping of the MDIO bus device registers.

Example:

        mdio-nexus@1,3 {
                compatible = "cavium,thunder-8890-mdio-nexus";
                #address-cells = <2>;
                #size-cells = <2>;
                reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
                assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
                ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;

                mdio0@87e0,05003800 {
                        compatible = "cavium,thunder-8890-mdio";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0x87e0 0x05003800 0x0 0x30>;

                        ethernet-phy@0 {
                                ...
                                reg = <0>;
                        };
                };
                mdio0@87e0,05003880 {
                        compatible = "cavium,thunder-8890-mdio";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0x87e0 0x05003880 0x0 0x30>;

                        ethernet-phy@0 {
                                ...
                                reg = <0>;
                        };
                };
        };


code:
* MIX Ethernet controller.

Properties:
- compatible: "cavium,octeon-5750-mix"

  Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX
  devices.

- reg: The base addresses of four separate register banks.  The first
  bank contains the MIX registers.  The second bank the corresponding
  AGL registers.  The third bank are the AGL registers shared by all
  MIX devices present.  The fourth bank is the AGL_PRT_CTL shared by
  all MIX devices present.

- cell-index: A single cell specifying which portion of the shared
  register banks corresponds to this MIX device.

- interrupts: Two interrupt specifiers.  The first is the MIX
  interrupt routing and the second the routing for the AGL interrupts.

- phy-handle: Optional, see ethernet.txt file in the same directory.

Example:
	ethernet@1070000100800 {
		compatible = "cavium,octeon-5750-mix";
		reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
		      <0x11800 0xE0000800 0x0 0x300>, /* AGL */
		      <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
		      <0x11800 0xE0002008 0x0 0x8>;   /* AGL_PRT_CTL */
		cell-index = <1>;
		interrupts = <1 18>, < 1 46>;
		local-mac-address = [ 00 0f b7 10 63 54 ];
		phy-handle = <&phy1>;
	};


code:
* PIP Ethernet nexus.

The PIP Ethernet nexus can control several data packet input/output
devices.  The devices have a two level grouping scheme.  There may be
several interfaces, and each interface may have several ports.  These
ports might be an individual Ethernet PHY.

Properties for the PIP nexus:
- compatible: "cavium,octeon-3860-pip"

  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.

- reg: The base address of the PIP's register bank.

- #address-cells: Must be <1>.

- #size-cells: Must be <0>.

Properties for PIP interfaces which is a child the PIP nexus:
- compatible: "cavium,octeon-3860-pip-interface"

  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.

- reg: The interface number.

- #address-cells: Must be <1>.

- #size-cells: Must be <0>.

Properties for PIP port which is a child the PIP interface:
- compatible: "cavium,octeon-3860-pip-port"

  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.

- reg: The port number within the interface group.

- phy-handle: Optional, see ethernet.txt file in the same directory.

- rx-delay: Delay value for RGMII receive clock. Optional. Disabled if 0.
  Value range is 1-31, and mapping to the actual delay varies depending on HW.

- tx-delay: Delay value for RGMII transmit clock. Optional. Disabled if 0.
  Value range is 1-31, and mapping to the actual delay varies depending on HW.

Example:

	pip@11800a0000000 {
		compatible = "cavium,octeon-3860-pip";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x11800 0xa0000000 0x0 0x2000>;

		interface@0 {
			compatible = "cavium,octeon-3860-pip-interface";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>; /* interface */

			ethernet@0 {
				compatible = "cavium,octeon-3860-pip-port";
				reg = <0x0>; /* Port */
				local-mac-address = [ 00 0f b7 10 63 60 ];
				phy-handle = <&phy2>;
			};
			ethernet@1 {
				compatible = "cavium,octeon-3860-pip-port";
				reg = <0x1>; /* Port */
				local-mac-address = [ 00 0f b7 10 63 61 ];
				phy-handle = <&phy3>;
			};
			ethernet@2 {
				compatible = "cavium,octeon-3860-pip-port";
				reg = <0x2>; /* Port */
				local-mac-address = [ 00 0f b7 10 63 62 ];
				phy-handle = <&phy4>;
			};
			ethernet@3 {
				compatible = "cavium,octeon-3860-pip-port";
				reg = <0x3>; /* Port */
				local-mac-address = [ 00 0f b7 10 63 63 ];
				phy-handle = <&phy5>;
			};
		};

		interface@1 {
			compatible = "cavium,octeon-3860-pip-interface";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>; /* interface */

			ethernet@0 {
				compatible = "cavium,octeon-3860-pip-port";
				reg = <0x0>; /* Port */
				local-mac-address = [ 00 0f b7 10 63 64 ];
				phy-handle = <&phy6>;
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/cdns,macb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence MACB/GEM Ethernet controller

maintainers:
  - Nicolas Ferre <nicolas.ferre@microchip.com>
  - Claudiu Beznea <claudiu.beznea@microchip.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - cdns,at91rm9200-emac  # Atmel at91rm9200 SoC
          - const: cdns,emac          # Generic

      - items:
          - enum:
              - cdns,zynq-gem         # Xilinx Zynq-7xxx SoC
              - cdns,zynqmp-gem       # Xilinx Zynq Ultrascale+ MPSoC
          - const: cdns,gem           # Generic
        deprecated: true

      - items:
          - enum:
              - xlnx,versal-gem       # Xilinx Versal
              - xlnx,zynq-gem         # Xilinx Zynq-7xxx SoC
              - xlnx,zynqmp-gem       # Xilinx Zynq Ultrascale+ MPSoC
          - const: cdns,gem           # Generic

      - items:
          - enum:
              - cdns,at91sam9260-macb # Atmel at91sam9 SoCs
              - cdns,sam9x60-macb     # Microchip sam9x60 SoC
              - microchip,mpfs-macb   # Microchip PolarFire SoC
          - const: cdns,macb          # Generic

      - items:
          - enum:
              - atmel,sama5d3-macb    # 10/100Mbit IP on Atmel sama5d3 SoCs
          - enum:
              - cdns,at91sam9260-macb # Atmel at91sam9 SoCs.
          - const: cdns,macb          # Generic

      - enum:
          - atmel,sama5d29-gem        # GEM XL IP (10/100) on Atmel sama5d29 SoCs
          - atmel,sama5d2-gem         # GEM IP (10/100) on Atmel sama5d2 SoCs
          - atmel,sama5d3-gem         # Gigabit IP on Atmel sama5d3 SoCs
          - atmel,sama5d4-gem         # GEM IP (10/100) on Atmel sama5d4 SoCs
          - cdns,np4-macb             # NP4 SoC devices
          - microchip,sama7g5-emac    # Microchip SAMA7G5 ethernet interface
          - microchip,sama7g5-gem     # Microchip SAMA7G5 gigabit ethernet interface
          - sifive,fu540-c000-gem     # SiFive FU540-C000 SoC
          - cdns,emac                 # Generic
          - cdns,gem                  # Generic
          - cdns,macb                 # Generic

  reg:
    minItems: 1
    items:
      - description: Basic register set
      - description: GEMGXL Management block registers on SiFive FU540-C000 SoC

  interrupts:
    minItems: 1
    maxItems: 8
    description: One interrupt per available hardware queue

  clocks:
    minItems: 1
    maxItems: 5

  clock-names:
    minItems: 1
    items:
      - enum: [ ether_clk, hclk, pclk ]
      - enum: [ hclk, pclk ]
      - const: tx_clk
      - enum: [ rx_clk, tsu_clk ]
      - const: tsu_clk

  local-mac-address: true

  phy-mode: true

  phy-handle: true

  phys:
    maxItems: 1

  resets:
    maxItems: 1
    description:
      Recommended with ZynqMP, specify reset control for this
      controller instance with zynqmp-reset driver.

  reset-names:
    maxItems: 1

  fixed-link: true

  iommus:
    maxItems: 1

  power-domains:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  mdio:
    type: object
    description:
      Node containing PHY children. If this node is not present, then PHYs will
      be direct children.

patternProperties:
  "^ethernet-phy@[0-9a-f]$":
    type: object
    $ref: ethernet-phy.yaml#

    properties:
      reset-gpios: true

      magic-packet:
        type: boolean
        description:
          Indicates that the hardware supports waking up via magic packet.

    unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - phy-mode

allOf:
  - $ref: ethernet-controller.yaml#

  - if:
      not:
        properties:
          compatible:
            contains:
              const: sifive,fu540-c000-gem
    then:
      properties:
        reg:
          maxItems: 1

unevaluatedProperties: false

examples:
  - |
    macb0: ethernet@fffc4000 {
            compatible = "cdns,macb";
            reg = <0xfffc4000 0x4000>;
            interrupts = <21>;
            phy-mode = "rmii";
            local-mac-address = [3a 0e 03 04 05 06];
            clock-names = "pclk", "hclk", "tx_clk";
            clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
            #address-cells = <1>;
            #size-cells = <0>;

            ethernet-phy@1 {
                    reg = <0x1>;
                    reset-gpios = <&pioE 6 1>;
            };
    };

  - |
    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
    #include <dt-bindings/power/xlnx-zynqmp-power.h>
    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
    #include <dt-bindings/phy/phy.h>

    bus {
            #address-cells = <2>;
            #size-cells = <2>;
            gem1: ethernet@ff0c0000 {
                    compatible = "xlnx,zynqmp-gem", "cdns,gem";
                    interrupt-parent = <&gic>;
                    interrupts = <0 59 4>, <0 59 4>;
                    reg = <0x0 0xff0c0000 0x0 0x1000>;
                    clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
                             <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
                             <&zynqmp_clk GEM_TSU>;
                    clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
                    #address-cells = <1>;
                    #size-cells = <0>;
                    iommus = <&smmu 0x875>;
                    power-domains = <&zynqmp_firmware PD_ETH_1>;
                    resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
                    reset-names = "gem1_rst";
                    phy-mode = "sgmii";
                    phys = <&psgtr 1 PHY_TYPE_SGMII 1 1>;
                    fixed-link {
                            speed = <1000>;
                            full-duplex;
                            pause;
                    };
            };
    };


code:
* Cirrus Logic CS8900/CS8920 Network Controller

Required properties:
- compatible	: Should be "cirrus,cs8900" or "cirrus,cs8920".
- reg		: Address and length of the IO space.
- interrupts	: Should contain the controller interrupt line.

Examples:
	eth0: eth@10000000 {
		compatible = "cirrus,cs8900";
		reg = <0x10000000 0x400>;
		interrupts = <10>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cortina Systems Gemini Ethernet Controller

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  This ethernet controller is found in the Gemini SoC family:
  StorLink SL3512 and SL3516, also known as Cortina Systems
  CS3512 and CS3516.

properties:
  compatible:
    const: cortina,gemini-ethernet

  reg:
    minItems: 3
    description: must contain the global registers and the V-bit and A-bit
      memory areas, in total three register sets.

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  ranges: true

#The subnodes represents the two ethernet ports in this device.
#They are not independent of each other since they share resources
#in the parent node, and are thus children.
patternProperties:
  "^ethernet-port@[0-9]+$":
    type: object
    unevaluatedProperties: false
    description: contains the resources for ethernet port
    allOf:
      - $ref: ethernet-controller.yaml#
    properties:
      compatible:
        const: cortina,gemini-ethernet-port

      reg:
        items:
          - description: DMA/TOE memory
          - description: GMAC memory area of the port

      interrupts:
        maxItems: 1
        description: should contain the interrupt line of the port.
                     this is nominally a level interrupt active high.

      resets:
        maxItems: 1
        description: this must provide an SoC-integrated reset line for the port.

      clocks:
        maxItems: 1
        description: this should contain a handle to the PCLK clock for
                     clocking the silicon in this port

      clock-names:
        const: PCLK

    required:
      - reg
      - compatible
      - interrupts
      - resets
      - clocks
      - clock-names

required:
  - compatible
  - reg
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/cortina,gemini-clock.h>
    #include <dt-bindings/reset/cortina,gemini-reset.h>
    mdio0: mdio {
      #address-cells = <1>;
      #size-cells = <0>;
      phy0: ethernet-phy@1 {
        reg = <1>;
        device_type = "ethernet-phy";
      };
      phy1: ethernet-phy@3 {
        reg = <3>;
        device_type = "ethernet-phy";
      };
    };

    ethernet@60000000 {
        compatible = "cortina,gemini-ethernet";
        reg = <0x60000000 0x4000>, /* Global registers, queue */
              <0x60004000 0x2000>, /* V-bit */
              <0x60006000 0x2000>; /* A-bit */
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        gmac0: ethernet-port@0 {
                compatible = "cortina,gemini-ethernet-port";
                reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
                      <0x6000a000 0x2000>; /* Port 0 GMAC */
                interrupt-parent = <&intcon>;
                interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
                resets = <&syscon GEMINI_RESET_GMAC0>;
                clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
                clock-names = "PCLK";
                phy-mode = "rgmii";
                phy-handle = <&phy0>;
        };

        gmac1: ethernet-port@1 {
                compatible = "cortina,gemini-ethernet-port";
                reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
                      <0x6000e000 0x2000>; /* Port 1 GMAC */
                interrupt-parent = <&intcon>;
                interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
                resets = <&syscon GEMINI_RESET_GMAC1>;
                clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
                clock-names = "PCLK";
                phy-mode = "rgmii";
                phy-handle = <&phy1>;
        };
    };


code:
Cortina Phy Driver Device Tree Bindings
---------------------------------------

CORTINA is a registered trademark of Cortina Systems, Inc.

The driver supports the Cortina Electronic Dispersion Compensation (EDC)
devices, equipped with clock and data recovery (CDR) circuits. These
devices make use of registers that are not compatible with Clause 45 or
Clause 22, therefore they need to be described using the
"ethernet-phy-id" compatible.

Since the driver only implements  polling mode support, interrupts info
can be skipped.

Example (CS4340 phy):
	mdio {
		cs4340_phy@10 {
			compatible = "ethernet-phy-id13e5.1002";
			reg = <0x10>;
		};
	};


code:
TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED)
-----------------------------------------------

Required properties:
- compatible		: Should be "ti,am3352-cpsw-phy-sel" for am335x platform and
			  "ti,dra7xx-cpsw-phy-sel" for dra7xx platform
			  "ti,am43xx-cpsw-phy-sel" for am43xx platform
- reg			: physical base address and size of the cpsw
			  registers map
- reg-names		: names of the register map given in "reg" node

Optional properties:
-rmii-clock-ext		: If present, the driver will configure the RMII
			  interface to external clock usage

Examples:

	phy_sel: cpsw-phy-sel@44e10650 {
		compatible = "ti,am3352-cpsw-phy-sel";
		reg= <0x44e10650 0x4>;
		reg-names = "gmii-sel";
	};

(or)
	phy_sel: cpsw-phy-sel@44e10650 {
		compatible = "ti,am3352-cpsw-phy-sel";
		reg= <0x44e10650 0x4>;
		reg-names = "gmii-sel";
		rmii-clock-ext;
	};


code:
TI SoC Ethernet Switch Controller Device Tree Bindings
------------------------------------------------------

Required properties:
- compatible		: Should be one of the below:-
			  "ti,cpsw" for backward compatible
			  "ti,am335x-cpsw" for AM335x controllers
			  "ti,am4372-cpsw" for AM437x controllers
			  "ti,dra7-cpsw" for DRA7x controllers
- reg			: physical base address and size of the cpsw
			  registers map
- interrupts		: property with a value describing the interrupt
			  number
- cpdma_channels 	: Specifies number of channels in CPDMA
- ale_entries		: Specifies No of entries ALE can hold
- bd_ram_size		: Specifies internal descriptor RAM size
- mac_control		: Specifies Default MAC control register content
			  for the specific platform
- slaves		: Specifies number for slaves
- active_slave		: Specifies the slave to use for time stamping,
			  ethtool and SIOCGMIIPHY
- cpsw-phy-sel		: Specifies the phandle to the CPSW phy mode selection
			  device. See also cpsw-phy-sel.txt for its binding.
			  Note that in legacy cases cpsw-phy-sel may be
			  a child device instead of a phandle
			  (DEPRECATED, use phys property instead).

Optional properties:
- ti,hwmods		: Must be "cpgmac0"
- dual_emac		: Specifies Switch to act as Dual EMAC
- syscon		: Phandle to the system control device node, which is
			  the control module device of the am33x
- mode-gpios		: Should be added if one/multiple gpio lines are
			  required to be driven so that cpsw data lines
			  can be connected to the phy via selective mux.
			  For example in dra72x-evm, pcf gpio has to be
			  driven low so that cpsw slave 0 and phy data
			  lines are connected via mux.
- cpts_clock_mult	: Numerator to convert input clock ticks into nanoseconds
- cpts_clock_shift	: Denominator to convert input clock ticks into nanoseconds
			  Mult and shift will be calculated basing on CPTS
			  rftclk frequency if both cpts_clock_shift and
			  cpts_clock_mult properties are not provided.

Slave Properties:
Required properties:
- phy-mode		: See ethernet.txt file in the same directory
- phys			: phandle on phy-gmii-sel PHY (see phy/ti-phy-gmii-sel.txt)

Optional properties:
- dual_emac_res_vlan	: Specifies VID to be used to segregate the ports
- phy_id		: Specifies slave phy id (deprecated, use phy-handle)
- phy-handle		: See ethernet.txt file in the same directory

The MAC address will be determined using the optional properties
defined in ethernet.txt.

Slave sub-nodes:
- fixed-link		: See fixed-link.txt file in the same directory

Note: Exactly one of phy_id, phy-handle, or fixed-link must be specified.

Note: "ti,hwmods" field is used to fetch the base address and irq
resources from TI, omap hwmod data base during device registration.
Future plan is to migrate hwmod data base contents into device tree
blob so that, all the required data will be used from device tree dts
file.

Examples:

	mac: ethernet@4a100000 {
		compatible = "ti,cpsw";
		reg = <0x4A100000 0x1000>;
		interrupts = <55 0x4>;
		interrupt-parent = <&intc>;
		cpdma_channels = <8>;
		ale_entries = <1024>;
		bd_ram_size = <0x2000>;
		rx_descs = <64>;
		mac_control = <0x20>;
		slaves = <2>;
		active_slave = <0>;
		cpts_clock_mult = <0x80000000>;
		cpts_clock_shift = <29>;
		syscon = <&cm>;
		cpsw-phy-sel = <&phy_sel>;
		cpsw_emac0: slave@0 {
			phy_id = <&davinci_mdio>, <0>;
			phy-mode = "rgmii-txid";
			/* Filled in by U-Boot */
			mac-address = [ 00 00 00 00 00 00 ];
			phys = <&phy_gmii_sel 1 0>;
		};
		cpsw_emac1: slave@1 {
			phy_id = <&davinci_mdio>, <1>;
			phy-mode = "rgmii-txid";
			/* Filled in by U-Boot */
			mac-address = [ 00 00 00 00 00 00 ];
			phys = <&phy_gmii_sel 2 0>;
		};
	};

(or)
	mac: ethernet@4a100000 {
		compatible = "ti,cpsw";
		ti,hwmods = "cpgmac0";
		cpdma_channels = <8>;
		ale_entries = <1024>;
		bd_ram_size = <0x2000>;
		rx_descs = <64>;
		mac_control = <0x20>;
		slaves = <2>;
		active_slave = <0>;
		cpts_clock_mult = <0x80000000>;
		cpts_clock_shift = <29>;
		syscon = <&cm>;
		cpsw-phy-sel = <&phy_sel>;
		cpsw_emac0: slave@0 {
			phy_id = <&davinci_mdio>, <0>;
			phy-mode = "rgmii-txid";
			/* Filled in by U-Boot */
			mac-address = [ 00 00 00 00 00 00 ];
			phys = <&phy_gmii_sel 1 0>;
		};
		cpsw_emac1: slave@1 {
			phy_id = <&davinci_mdio>, <1>;
			phy-mode = "rgmii-txid";
			/* Filled in by U-Boot */
			mac-address = [ 00 00 00 00 00 00 ];
			phys = <&phy_gmii_sel 2 0>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/davicom,dm9051.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Davicom DM9051 SPI Ethernet Controller

maintainers:
  - Joseph CHANG <josright123@gmail.com>

description: |
  The DM9051 is a fully integrated and cost-effective low pin count single
  chip Fast Ethernet controller with a Serial Peripheral Interface (SPI).

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    const: davicom,dm9051

  reg:
    maxItems: 1

  spi-max-frequency:
    maximum: 45000000

  interrupts:
    maxItems: 1

  local-mac-address: true

  mac-address: true

required:
  - compatible
  - reg
  - spi-max-frequency
  - interrupts

additionalProperties: false

examples:
  # Raspberry Pi platform
  - |
    /* for Raspberry Pi with pin control stuff for GPIO irq */
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>
    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        ethernet@0 {
            compatible = "davicom,dm9051";
            reg = <0>; /* spi chip select */
            local-mac-address = [00 00 00 00 00 00];
            interrupt-parent = <&gpio>;
            interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
            spi-max-frequency = <31200000>;
        };
    };


code:
Davicom DM9000 Fast Ethernet controller

Required properties:
- compatible = "davicom,dm9000";
- reg : physical addresses and sizes of registers, must contain 2 entries:
    first entry : address register,
    second entry : data register.
- interrupts : interrupt specifier specific to interrupt controller

Optional properties:
- davicom,no-eeprom : Configuration EEPROM is not available
- davicom,ext-phy : Use external PHY
- reset-gpios : phandle of gpio that will be used to reset chip during probe
- vcc-supply : phandle of regulator that will be used to enable power to chip

Example:

	ethernet@18000000 {
		compatible = "davicom,dm9000";
		reg = <0x18000000 0x2 0x18000004 0x2>;
		interrupt-parent = <&gpn>;
		interrupts = <7 4>;
		local-mac-address = [00 00 de ad be ef];
		davicom,no-eeprom;
		reset-gpios = <&gpf 12 GPIO_ACTIVE_LOW>;
		vcc-supply = <&eth0_power>;
	};


code:
* Texas Instruments Davinci EMAC

This file provides information, what the device node
for the davinci_emac interface contains.

Required properties:
- compatible: "ti,davinci-dm6467-emac", "ti,am3517-emac" or
  "ti,dm816-emac"
- reg: Offset and length of the register set for the device
- ti,davinci-ctrl-reg-offset: offset to control register
- ti,davinci-ctrl-mod-reg-offset: offset to control module register
- ti,davinci-ctrl-ram-offset: offset to control module ram
- ti,davinci-ctrl-ram-size: size of control module ram
- interrupts: interrupt mapping for the davinci emac interrupts sources:
              4 sources: <Receive Threshold Interrupt
			  Receive Interrupt
			  Transmit Interrupt
			  Miscellaneous Interrupt>

Optional properties:
- phy-handle: See ethernet.txt file in the same directory.
              If absent, davinci_emac driver defaults to 100/FULL.
- ti,davinci-rmii-en: 1 byte, 1 means use RMII
- ti,davinci-no-bd-ram: boolean, does EMAC have BD RAM?

The MAC address will be determined using the optional properties
defined in ethernet.txt.

Example (enbw_cmc board):
	eth0: emac@1e20000 {
		compatible = "ti,davinci-dm6467-emac";
		reg = <0x220000 0x4000>;
		ti,davinci-ctrl-reg-offset = <0x3000>;
		ti,davinci-ctrl-mod-reg-offset = <0x2000>;
		ti,davinci-ctrl-ram-offset = <0>;
		ti,davinci-ctrl-ram-size = <0x2000>;
		local-mac-address = [ 00 00 00 00 00 00 ];
		interrupts = <33
				34
				35
				36
				>;
		interrupt-parent = <&intc>;
	};


code:
Atheros AR9331 built-in switch
=============================

It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal
MDIO bus. All PHYs are built-in as well.

Required properties:

 - compatible: should be: "qca,ar9331-switch"
 - reg: Address on the MII bus for the switch.
 - resets : Must contain an entry for each entry in reset-names.
 - reset-names : Must include the following entries: "switch"
 - interrupt-parent: Phandle to the parent interrupt controller
 - interrupts: IRQ line for the switch
 - interrupt-controller: Indicates the switch is itself an interrupt
   controller. This is used for the PHY interrupts.
 - #interrupt-cells: must be 1
 - mdio: Container of PHY and devices on the switches MDIO bus.

See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required and optional properties.
Examples:

eth0: ethernet@19000000 {
	compatible = "qca,ar9330-eth";
	reg = <0x19000000 0x200>;
	interrupts = <4>;

	resets = <&rst 9>, <&rst 22>;
	reset-names = "mac", "mdio";
	clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
	clock-names = "eth", "mdio";

	phy-mode = "mii";
	phy-handle = <&phy_port4>;
};

eth1: ethernet@1a000000 {
	compatible = "qca,ar9330-eth";
	reg = <0x1a000000 0x200>;
	interrupts = <5>;
	resets = <&rst 13>, <&rst 23>;
	reset-names = "mac", "mdio";
	clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
	clock-names = "eth", "mdio";

	phy-mode = "gmii";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		switch10: switch@10 {
			#address-cells = <1>;
			#size-cells = <0>;

			compatible = "qca,ar9331-switch";
			reg = <0x10>;
			resets = <&rst 8>;
			reset-names = "switch";

			interrupt-parent = <&miscintc>;
			interrupts = <12>;

			interrupt-controller;
			#interrupt-cells = <1>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				switch_port0: port@0 {
					reg = <0x0>;
					ethernet = <&eth1>;

					phy-mode = "gmii";

					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};

				switch_port1: port@1 {
					reg = <0x1>;
					phy-handle = <&phy_port0>;
					phy-mode = "internal";
				};

				switch_port2: port@2 {
					reg = <0x2>;
					phy-handle = <&phy_port1>;
					phy-mode = "internal";
				};

				switch_port3: port@3 {
					reg = <0x3>;
					phy-handle = <&phy_port2>;
					phy-mode = "internal";
				};

				switch_port4: port@4 {
					reg = <0x4>;
					phy-handle = <&phy_port3>;
					phy-mode = "internal";
				};
			};

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				interrupt-parent = <&switch10>;

				phy_port0: phy@0 {
					reg = <0x0>;
					interrupts = <0>;
				};

				phy_port1: phy@1 {
					reg = <0x1>;
					interrupts = <0>;
				};

				phy_port2: phy@2 {
					reg = <0x2>;
					interrupts = <0>;
				};

				phy_port3: phy@3 {
					reg = <0x3>;
					interrupts = <0>;
				};

				phy_port4: phy@4 {
					reg = <0x4>;
					interrupts = <0>;
				};
			};
		};
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/arrow,xrs700x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arrow SpeedChips XRS7000 Series Switch Device Tree Bindings

allOf:
  - $ref: dsa.yaml#

maintainers:
  - George McCollister <george.mccollister@gmail.com>

description:
  The Arrow SpeedChips XRS7000 Series of single chip gigabit Ethernet switches
  are designed for critical networking applications. They have up to three
  RGMII ports and one RMII port and are managed via i2c or mdio.

properties:
  compatible:
    oneOf:
      - enum:
          - arrow,xrs7003e
          - arrow,xrs7003f
          - arrow,xrs7004e
          - arrow,xrs7004f

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;
        switch@8 {
            compatible = "arrow,xrs7004e";
            reg = <0x8>;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;
                ethernet-port@1 {
                    reg = <1>;
                    label = "lan0";
                    phy-handle = <&swphy0>;
                    phy-mode = "rgmii-id";
                };
                ethernet-port@2 {
                    reg = <2>;
                    label = "lan1";
                    phy-handle = <&swphy1>;
                    phy-mode = "rgmii-id";
                };
                ethernet-port@3 {
                    reg = <3>;
                    ethernet = <&fec1>;
                    phy-mode = "rgmii-id";

                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/brcm,b53.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM53xx Ethernet switches

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

description:
  Broadcom BCM53xx Ethernet switches

properties:
  compatible:
    oneOf:
      - const: brcm,bcm5325
      - const: brcm,bcm53115
      - const: brcm,bcm53125
      - const: brcm,bcm53128
      - const: brcm,bcm5365
      - const: brcm,bcm5395
      - const: brcm,bcm5389
      - const: brcm,bcm5397
      - const: brcm,bcm5398
      - items:
          - const: brcm,bcm11360-srab
          - const: brcm,cygnus-srab
      - items:
          - enum:
              - brcm,bcm53010-srab
              - brcm,bcm53011-srab
              - brcm,bcm53012-srab
              - brcm,bcm53018-srab
              - brcm,bcm53019-srab
          - const: brcm,bcm5301x-srab
      - items:
          - enum:
              - brcm,bcm11404-srab
              - brcm,bcm11407-srab
              - brcm,bcm11409-srab
              - brcm,bcm58310-srab
              - brcm,bcm58311-srab
              - brcm,bcm58313-srab
          - const: brcm,omega-srab
      - items:
          - enum:
              - brcm,bcm58522-srab
              - brcm,bcm58523-srab
              - brcm,bcm58525-srab
              - brcm,bcm58622-srab
              - brcm,bcm58623-srab
              - brcm,bcm58625-srab
              - brcm,bcm88312-srab
          - const: brcm,nsp-srab
      - items:
          - enum:
              - brcm,bcm3384-switch
              - brcm,bcm6328-switch
              - brcm,bcm6368-switch
          - const: brcm,bcm63xx-switch

required:
  - compatible
  - reg

allOf:
  - $ref: dsa.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - brcm,bcm5325
              - brcm,bcm53115
              - brcm,bcm53125
              - brcm,bcm53128
              - brcm,bcm5365
              - brcm,bcm5395
              - brcm,bcm5397
              - brcm,bcm5398
    then:
      $ref: /schemas/spi/spi-peripheral-props.yaml

    # BCM585xx/586xx/88312 SoCs
  - if:
      properties:
        compatible:
          contains:
            enum:
              - brcm,bcm58522-srab
              - brcm,bcm58523-srab
              - brcm,bcm58525-srab
              - brcm,bcm58622-srab
              - brcm,bcm58623-srab
              - brcm,bcm58625-srab
              - brcm,bcm88312-srab
    then:
      properties:
        reg:
          minItems: 3
          maxItems: 3
        reg-names:
          items:
            - const: srab
            - const: mux_config
            - const: sgmii_config
        interrupts:
          minItems: 13
          maxItems: 13
        interrupt-names:
          items:
            - const: link_state_p0
            - const: link_state_p1
            - const: link_state_p2
            - const: link_state_p3
            - const: link_state_p4
            - const: link_state_p5
            - const: link_state_p7
            - const: link_state_p8
            - const: phy
            - const: ts
            - const: imp_sleep_timer_p5
            - const: imp_sleep_timer_p7
            - const: imp_sleep_timer_p8
      required:
        - interrupts
    else:
      properties:
        reg:
          maxItems: 1

unevaluatedProperties: false

examples:
  - |
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        ethernet-switch@1e {
            compatible = "brcm,bcm53125";
            reg = <30>;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    label = "lan1";
                };

                port@1 {
                    reg = <1>;
                    label = "lan2";
                };

                port@5 {
                    reg = <5>;
                    label = "cable-modem";
                    phy-mode = "rgmii-txid";
                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                    };
                };

                port@8 {
                    reg = <8>;
                    phy-mode = "rgmii-txid";
                    ethernet = <&eth0>;
                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                    };
                };
            };
        };
    };
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    axi {
        #address-cells = <1>;
        #size-cells = <1>;

        switch@36000 {
            compatible = "brcm,bcm58623-srab", "brcm,nsp-srab";
            reg = <0x36000 0x1000>,
                  <0x3f308 0x8>,
                  <0x3f410 0xc>;
            reg-names = "srab", "mux_config", "sgmii_config";
            interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "link_state_p0",
                              "link_state_p1",
                              "link_state_p2",
                              "link_state_p3",
                              "link_state_p4",
                              "link_state_p5",
                              "link_state_p7",
                              "link_state_p8",
                              "phy",
                              "ts",
                              "imp_sleep_timer_p5",
                              "imp_sleep_timer_p7",
                              "imp_sleep_timer_p8";

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    label = "port0";
                    reg = <0>;
                };

                port@1 {
                    label = "port1";
                    reg = <1>;
                };

                port@2 {
                    label = "port2";
                    reg = <2>;
                };

                port@3 {
                    label = "port3";
                    reg = <3>;
                };

                port@4 {
                    label = "port4";
                    reg = <4>;
                };

                port@8 {
                    ethernet = <&amac2>;
                    reg = <8>;
                    phy-mode = "internal";

                    fixed-link {
                        speed = <1000>;
                        full-duplex;
                    };
                };
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/brcm,sf2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Starfighter 2 integrated swich

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  compatible:
    items:
      - enum:
          - brcm,bcm4908-switch
          - brcm,bcm7278-switch-v4.0
          - brcm,bcm7278-switch-v4.8
          - brcm,bcm7445-switch-v4.0

  reg:
    minItems: 6
    maxItems: 6

  reg-names:
    items:
      - const: core
      - const: reg
      - const: intrl2_0
      - const: intrl2_1
      - const: fcb
      - const: acb

  interrupts:
    minItems: 2
    maxItems: 2

  interrupt-names:
    items:
      - const: switch_0
      - const: switch_1

  resets:
    maxItems: 1

  reset-names:
    const: switch

  clocks:
    minItems: 1
    items:
      - description: switch's main clock
      - description: dividing of the switch core clock

  clock-names:
    minItems: 1
    items:
      - const: sw_switch
      - const: sw_switch_mdiv

  brcm,num-gphy:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: maximum number of integrated gigabit PHYs in the switch

  brcm,num-rgmii-ports:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: maximum number of RGMII interfaces supported by the switch

  brcm,fcb-pause-override:
    description: if present indicates that the switch supports Failover Control
      Block pause override capability
    type: boolean

  brcm,acb-packets-inflight:
    description: if present indicates that the switch Admission Control Block
      supports reporting the number of packets in-flight in a switch queue
    type: boolean

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  ports:
    type: object

    properties:
      brcm,use-bcm-hdr:
        description: if present, indicates that the switch port has Broadcom
          tags enabled (per-packet metadata)
        type: boolean

required:
  - reg
  - interrupts
  - "#address-cells"
  - "#size-cells"

allOf:
  - $ref: "dsa.yaml#"
  - if:
      properties:
        compatible:
          contains:
            enum:
              - brcm,bcm7278-switch-v4.0
              - brcm,bcm7278-switch-v4.8
    then:
      properties:
        clocks:
          minItems: 1
          maxItems: 1
        clock-names:
          minItems: 1
          maxItems: 1
      required:
        - clocks
        - clock-names
  - if:
      properties:
        compatible:
          contains:
            const: brcm,bcm7445-switch-v4.0
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          minItems: 2
          maxItems: 2
      required:
        - clocks
        - clock-names

additionalProperties: false

examples:
  - |
    switch@f0b00000 {
            compatible = "brcm,bcm7445-switch-v4.0";
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0xf0b00000 0x40000>,
                  <0xf0b40000 0x110>,
                  <0xf0b40340 0x30>,
                  <0xf0b40380 0x30>,
                  <0xf0b40400 0x34>,
                  <0xf0b40600 0x208>;
            reg-names = "core", "reg", "intrl2_0", "intrl2_1",
                        "fcb", "acb";
            interrupts = <0 0x18 0>,
                         <0 0x19 0>;
            clocks = <&sw_switch>, <&sw_switch_mdiv>;
            clock-names = "sw_switch", "sw_switch_mdiv";
            brcm,num-gphy = <1>;
            brcm,num-rgmii-ports = <2>;
            brcm,fcb-pause-override;
            brcm,acb-packets-inflight;

            ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@0 {
                            label = "gphy";
                            reg = <0>;
                    };
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/dsa-port.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ethernet Switch port Device Tree Bindings

maintainers:
  - Andrew Lunn <andrew@lunn.ch>
  - Florian Fainelli <f.fainelli@gmail.com>
  - Vivien Didelot <vivien.didelot@gmail.com>

description:
  Ethernet switch port Description

allOf:
  - $ref: /schemas/net/ethernet-controller.yaml#

properties:
  reg:
    items:
      - description: Port number

  label:
    description:
      Describes the label associated with this port, which will become
      the netdev name
    $ref: /schemas/types.yaml#/definitions/string

  link:
    description:
      Should be a list of phandles to other switch's DSA port. This
      port is used as the outgoing port towards the phandle ports. The
      full routing information must be given, not just the one hop
      routes to neighbouring switches
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      maxItems: 1

  ethernet:
    description:
      Should be a phandle to a valid Ethernet device node.  This host
      device is what the switch port is connected to
    $ref: /schemas/types.yaml#/definitions/phandle

  dsa-tag-protocol:
    description:
      Instead of the default, the switch will use this tag protocol if
      possible. Useful when a device supports multiple protocols and
      the default is incompatible with the Ethernet device.
    enum:
      - dsa
      - edsa
      - ocelot
      - ocelot-8021q
      - rtl8_4
      - rtl8_4t
      - seville

  phy-handle: true

  phy-mode: true

  fixed-link: true

  mac-address: true

  sfp: true

  managed: true

  rx-internal-delay-ps: true

  tx-internal-delay-ps: true

required:
  - reg

# CPU and DSA ports must have phylink-compatible link descriptions
if:
  oneOf:
    - required: [ ethernet ]
    - required: [ link ]
then:
  allOf:
    - required:
        - phy-mode
    - oneOf:
        - required:
            - fixed-link
        - required:
            - phy-handle
        - required:
            - managed

additionalProperties: true

...


code:
Distributed Switch Architecture Device Tree Bindings
----------------------------------------------------

See Documentation/devicetree/bindings/net/dsa/dsa.yaml for the documentation.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/dsa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ethernet Switch Device Tree Bindings

maintainers:
  - Andrew Lunn <andrew@lunn.ch>
  - Florian Fainelli <f.fainelli@gmail.com>
  - Vivien Didelot <vivien.didelot@gmail.com>

description:
  This binding represents Ethernet Switches which have a dedicated CPU
  port. That port is usually connected to an Ethernet Controller of the
  SoC. Such setups are typical for embedded devices.

select: false

properties:
  $nodename:
    pattern: "^(ethernet-)?switch(@.*)?$"

  dsa,member:
    minItems: 2
    maxItems: 2
    description:
      A two element list indicates which DSA cluster, and position within the
      cluster a switch takes. <0 0> is cluster 0, switch 0. <0 1> is cluster 0,
      switch 1. <1 0> is cluster 1, switch 0. A switch not part of any cluster
      (single device hanging off a CPU port) must not specify this property
    $ref: /schemas/types.yaml#/definitions/uint32-array

patternProperties:
  "^(ethernet-)?ports$":
    type: object
    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    patternProperties:
      "^(ethernet-)?port@[0-9]+$":
        type: object
        description: Ethernet switch ports

        $ref: dsa-port.yaml#

        unevaluatedProperties: false

oneOf:
  - required:
      - ports
  - required:
      - ethernet-ports

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/hirschmann,hellcreek.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Hirschmann Hellcreek TSN Switch Device Tree Bindings

allOf:
  - $ref: dsa.yaml#

maintainers:
  - Andrew Lunn <andrew@lunn.ch>
  - Florian Fainelli <f.fainelli@gmail.com>
  - Vladimir Oltean <olteanv@gmail.com>
  - Kurt Kanzenbach <kurt@linutronix.de>

description:
  The Hellcreek TSN Switch IP is a 802.1Q Ethernet compliant switch. It supports
  the Precision Time Protocol, Hardware Timestamping as well the Time Aware
  Shaper.

properties:
  compatible:
    items:
      - const: hirschmann,hellcreek-de1soc-r1

  reg:
    description:
      The physical base address and size of TSN and PTP memory base
    minItems: 2
    maxItems: 2

  reg-names:
    items:
      - const: tsn
      - const: ptp

  leds:
    type: object
    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    patternProperties:
      "^led@[01]$":
        type: object
        description: Hellcreek leds
        $ref: /schemas/leds/common.yaml#

        properties:
          reg:
            items:
              - enum: [0, 1]
            description: Led number

          label: true

          default-state: true

        required:
          - reg

        additionalProperties: false

    additionalProperties: false

required:
  - compatible
  - reg
  - reg-names
  - ethernet-ports
  - leds

unevaluatedProperties: false

examples:
  - |
        switch0: switch@ff240000 {
            compatible = "hirschmann,hellcreek-de1soc-r1";
            reg = <0xff240000 0x1000>,
                  <0xff250000 0x1000>;
            reg-names = "tsn", "ptp";
            dsa,member = <0 0>;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    ethernet = <&gmac0>;
                    phy-mode = "mii";

                    fixed-link {
                        speed = <100>;
                        full-duplex;
                    };
                };

                port@2 {
                    reg = <2>;
                    label = "lan0";
                    phy-handle = <&phy1>;
                };

                port@3 {
                    reg = <3>;
                    label = "lan1";
                    phy-handle = <&phy2>;
                };
            };

            leds {
                #address-cells = <1>;
                #size-cells = <0>;

                led@0 {
                    reg = <0>;
                    label = "sync_good";
                    default-state = "on";
                };

                led@1 {
                    reg = <1>;
                    label = "is_gm";
                    default-state = "off";
                };
            };
        };


code:
SMSC/MicroChip LAN9303 three port ethernet switch
-------------------------------------------------

Required properties:

- compatible: should be
  - "smsc,lan9303-i2c" for I2C managed mode
    or
  - "smsc,lan9303-mdio" for mdio managed mode

Optional properties:

- reset-gpios: GPIO to be used to reset the whole device
- reset-duration: reset duration in milliseconds, defaults to 200 ms

Subnodes:

The integrated switch subnode should be specified according to the binding
described in dsa/dsa.txt. The CPU port of this switch is always port 0.

Note: always use 'reg = <0/1/2>;' for the three DSA ports, even if the device is
configured to use 1/2/3 instead. This hardware configuration will be
auto-detected and mapped accordingly.

Example:

I2C managed mode:

	master: masterdevice@X {

		fixed-link { /* RMII fixed link to LAN9303 */
			speed = <100>;
			full-duplex;
		};
	};

	switch: switch@a {
		compatible = "smsc,lan9303-i2c";
		reg = <0xa>;
		reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
		reset-duration = <200>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 { /* RMII fixed link to master */
				reg = <0>;
				ethernet = <&master>;
			};

			port@1 { /* external port 1 */
				reg = <1>;
				label = "lan1";
			};

			port@2 { /* external port 2 */
				reg = <2>;
				label = "lan2";
			};
		};
	};

MDIO managed mode:

	master: masterdevice@X {
		phy-handle = <&switch>;

		mdio {
			#address-cells = <1>;
			#size-cells = <0>;

			switch: switch-phy@0 {
				compatible = "smsc,lan9303-mdio";
				reg = <0>;
				reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
				reset-duration = <100>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						ethernet = <&master>;
					};

					port@1 { /* external port 1 */
						reg = <1>;
						label = "lan1";
					};

					port@2 { /* external port 2 */
						reg = <2>;
						label = "lan2";
					};
				};
			};
		};
	};


code:
Lantiq GSWIP Ethernet switches
==================================

Required properties for GSWIP core:

- compatible	: "lantiq,xrx200-gswip" for the embedded GSWIP in the
		  xRX200 SoC
		  "lantiq,xrx300-gswip" for the embedded GSWIP in the
		  xRX300 SoC
		  "lantiq,xrx330-gswip" for the embedded GSWIP in the
		  xRX330 SoC
- reg		: memory range of the GSWIP core registers
		: memory range of the GSWIP MDIO registers
		: memory range of the GSWIP MII registers

See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of
additional required and optional properties.

Required properties for MDIO bus:
- compatible	: "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP
		  core of the xRX200 SoC and the PHYs connected to it.

See Documentation/devicetree/bindings/net/mdio.txt for a list of additional
required and optional properties.

Required properties for GPHY firmware loading:
- compatible	: "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw"
		  "lantiq,xrx300-gphy-fw", "lantiq,gphy-fw"
		  "lantiq,xrx330-gphy-fw", "lantiq,gphy-fw"
		  for the loading of the firmware into the embedded
		  GPHY core of the SoC.
- lantiq,rcu	: reference to the rcu syscon

The GPHY firmware loader has a list of GPHY entries, one for each
embedded GPHY

- reg		: Offset of the GPHY firmware register in the RCU
		  register range
- resets	: list of resets of the embedded GPHY
- reset-names	: list of names of the resets

Example:

Ethernet switch on the VRX200 SoC:

switch@e108000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "lantiq,xrx200-gswip";
	reg = <	0xe108000 0x3100	/* switch */
		0xe10b100 0xd8		/* mdio */
		0xe10b1d8 0x130		/* mii */
		>;
	dsa,member = <0 0>;

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			label = "lan3";
			phy-mode = "rgmii";
			phy-handle = <&phy0>;
		};

		port@1 {
			reg = <1>;
			label = "lan4";
			phy-mode = "rgmii";
			phy-handle = <&phy1>;
		};

		port@2 {
			reg = <2>;
			label = "lan2";
			phy-mode = "internal";
			phy-handle = <&phy11>;
		};

		port@4 {
			reg = <4>;
			label = "lan1";
			phy-mode = "internal";
			phy-handle = <&phy13>;
		};

		port@5 {
			reg = <5>;
			label = "wan";
			phy-mode = "rgmii";
			phy-handle = <&phy5>;
		};

		port@6 {
			reg = <0x6>;
			ethernet = <&eth0>;
		};
	};

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "lantiq,xrx200-mdio";
		reg = <0>;

		phy0: ethernet-phy@0 {
			reg = <0x0>;
		};
		phy1: ethernet-phy@1 {
			reg = <0x1>;
		};
		phy5: ethernet-phy@5 {
			reg = <0x5>;
		};
		phy11: ethernet-phy@11 {
			reg = <0x11>;
		};
		phy13: ethernet-phy@13 {
			reg = <0x13>;
		};
	};

	gphy-fw {
		compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
		lantiq,rcu = <&rcu0>;
		#address-cells = <1>;
		#size-cells = <0>;

		gphy@20 {
			reg = <0x20>;

			resets = <&reset0 31 30>;
			reset-names = "gphy";
		};

		gphy@68 {
			reg = <0x68>;

			resets = <&reset0 29 28>;
			reset-names = "gphy";
		};
	};
};


code:
Marvell DSA Switch Device Tree Bindings
---------------------------------------

WARNING: This binding is currently unstable. Do not program it into a
FLASH never to be changed again. Once this binding is stable, this
warning will be removed.

If you need a stable binding, use the old dsa.txt binding.

Marvell Switches are MDIO devices. The following properties should be
placed as a child node of an mdio device.

The properties described here are those specific to Marvell devices.
Additional required and optional properties can be found in dsa.txt.

The compatibility string is used only to find an identification register,
which is at a different MDIO base address in different switch families.
- "marvell,mv88e6085"	: Switch has base address 0x10. Use with models:
			  6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165,
			  6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321,
			  6341, 6350, 6351, 6352
- "marvell,mv88e6190"	: Switch has base address 0x00. Use with models:
			  6190, 6190X, 6191, 6290, 6390, 6390X
- "marvell,mv88e6250"	: Switch has base address 0x08 or 0x18. Use with model:
			  6220, 6250

Required properties:
- compatible		: Should be one of "marvell,mv88e6085",
			  "marvell,mv88e6190" or "marvell,mv88e6250" as
			  indicated above
- reg			: Address on the MII bus for the switch.

Optional properties:

- reset-gpios		: Should be a gpio specifier for a reset line
- interrupts		: Interrupt from the switch
- interrupt-controller	: Indicates the switch is itself an interrupt
			  controller. This is used for the PHY interrupts.
#interrupt-cells = <2>	: Controller uses two cells, number and flag
- eeprom-length		: Set to the length of an EEPROM connected to the
			  switch. Must be set if the switch can not detect
			  the presence and/or size of a connected EEPROM,
			  otherwise optional.
- mdio			: Container of PHY and devices on the switches MDIO
			  bus.
- mdio?		: Container of PHYs and devices on the external MDIO
			  bus. The node must contains a compatible string of
			  "marvell,mv88e6xxx-mdio-external"

Example:

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		interrupt-parent = <&gpio0>;
		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <2>;

		switch0: switch@0 {
			compatible = "marvell,mv88e6085";
			reg = <0>;
			reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				switch1phy0: switch1phy0@0 {
					reg = <0>;
					interrupt-parent = <&switch0>;
					interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
				};
			};
		};
	};

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		interrupt-parent = <&gpio0>;
		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
		interrupt-controller;
		#interrupt-cells = <2>;

		switch0: switch@0 {
			compatible = "marvell,mv88e6190";
			reg = <0>;
			reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;
				switch1phy0: switch1phy0@0 {
					reg = <0>;
					interrupt-parent = <&switch0>;
					interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			mdio1 {
				compatible = "marvell,mv88e6xxx-mdio-external";
				#address-cells = <1>;
				#size-cells = <0>;
				switch1phy9: switch1phy0@9 {
					reg = <9>;
				};
			};
		};
	};