code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra30-pinmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra30 pinmux Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    const: nvidia,tegra30-pinmux

  reg:
    items:
      - description: pad control registers
      - description: mux registers

patternProperties:
  "^pinmux(-[a-z0-9-_]+)?$":
    type: object
    properties:
      phandle: true

    # pin groups
    additionalProperties:
      $ref: nvidia,tegra-pinmux-common.yaml
      additionalProperties: false
      properties:
        nvidia,pins:
          items:
            enum: [ clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2,
                    dap2_sclk_pa3, dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6,
                    sdmmc3_cmd_pa7, gmi_a17_pb0, gmi_a18_pb1, lcd_pwr0_pb2,
                    lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
                    sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0,
                    lcd_pwr1_pc1, uart2_txd_pc2, uart2_rxd_pc3,
                    gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, lcd_pwr2_pc6,
                    gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1,
                    lcd_dc1_pd2, sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5,
                    vi_vsync_pd6, vi_hsync_pd7, lcd_d0_pe0, lcd_d1_pe1,
                    lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5, lcd_d6_pe6,
                    lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2,
                    lcd_d11_pf3, lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6,
                    lcd_d15_pf7, gmi_ad0_pg0, gmi_ad1_pg1, gmi_ad2_pg2,
                    gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, gmi_ad6_pg6,
                    gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
                    gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6,
                    gmi_ad15_ph7, gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2,
                    gmi_cs6_n_pi3, gmi_rst_n_pi4, gmi_iordy_pi5, gmi_cs7_n_pi6,
                    gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1, gmi_cs1_n_pj2,
                    lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
                    uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1,
                    gmi_cs4_n_pk2, gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5,
                    spdif_in_pk6, gmi_a19_pk7, vi_d2_pl0, vi_d3_pl1, vi_d4_pl2,
                    vi_d5_pl3, vi_d6_pl4, vi_d7_pl5, vi_d8_pl6, vi_d9_pl7,
                    lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
                    lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7,
                    dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3,
                    lcd_cs0_n_pn4, lcd_sdout_pn5, lcd_dc0_pn6, hdmi_int_pn7,
                    ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
                    ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5,
                    ulpi_data5_po6, ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1,
                    dap3_dout_pp2, dap3_sclk_pp3, dap4_fs_pp4, dap4_din_pp5,
                    dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0, kb_col1_pq1,
                    kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
                    kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1,
                    kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5,
                    kb_row6_pr6, kb_row7_pr7, kb_row8_ps0, kb_row9_ps1,
                    kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, kb_row13_ps5,
                    kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
                    vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5,
                    gen2_i2c_sda_pt6, sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4,
                    pu5, pu6, jtag_rtck_pu7, pv0, pv1, pv2, pv3, ddc_scl_pv4,
                    ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7, lcd_cs1_n_pw0,
                    lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
                    clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0,
                    spi2_miso_px1, spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4,
                    spi1_sck_px5, spi1_cs0_n_px6, spi1_miso_px7, ulpi_clk_py0,
                    ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, sdmmc1_dat3_py4,
                    sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
                    sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3,
                    lcd_sck_pz4, sys_clk_req_pz5, pwr_i2c_scl_pz6,
                    pwr_i2c_sda_pz7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1,
                    sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
                    sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
                    cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
                    pbb7, cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3,
                    sdmmc4_clk_pcc4, clk2_req_pcc5, pex_l2_rst_n_pcc6,
                    pex_l2_clkreq_n_pcc7, pex_l0_prsnt_n_pdd0,
                    pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2, pex_wake_n_pdd3,
                    pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
                    pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0,
                    clk3_req_pee1, clk1_req_pee2, hdmi_cec_pee3, clk_32k_in,
                    core_pwr_req, cpu_pwr_req, owr, pwr_int_n,
                    # drive groups
                    drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
                    drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_cec,
                    drive_crt, drive_csus, drive_dap1, drive_dap2, drive_dap3,
                    drive_dap4, drive_dbg, drive_ddc, drive_dev3, drive_gma,
                    drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_gmf,
                    drive_gmg, drive_gmh, drive_gpv, drive_lcd1, drive_lcd2,
                    drive_owr, drive_sdio1, drive_sdio2, drive_sdio3,
                    drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
                    drive_uda, drive_vi1 ]

        nvidia,function:
          enum: [ blink, cec, clk_12m_out, clk_32k_in, core_pwr_req,
                  cpu_pwr_req, crt, dap, ddr, dev3, displaya, displayb, dtv,
                  extperiph1, extperiph2, extperiph3, gmi, gmi_alt, hda, hdcp,
                  hdmi, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2,
                  i2s3, i2s4, invalid, kbc, mio, nand, nand_alt, owr, pcie,
                  pwm0, pwm1, pwm2, pwm3, pwr_int_n, rsvd1, rsvd2, rsvd3,
                  rsvd4, rtck, sata, sdmmc1, sdmmc2, sdmmc3, sdmmc4, spdif,
                  spi1, spi2, spi2_alt, spi3, spi4, spi5, spi6, sysclk, test,
                  trace, uarta, uartb, uartc, uartd, uarte, ulpi, vgp1, vgp2,
                  vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt2, vi_alt3 ]

        nvidia,pull: true
        nvidia,tristate: true
        nvidia,schmitt: true
        nvidia,pull-down-strength: true
        nvidia,pull-up-strength: true
        nvidia,high-speed-mode: true
        nvidia,low-power-mode: true
        nvidia,enable-input: true
        nvidia,open-drain: true
        nvidia,lock: true
        nvidia,io-reset: true
        nvidia,slew-rate-rising: true
        nvidia,slew-rate-falling: true

      required:
        - nvidia,pins

additionalProperties: false

required:
  - compatible
  - reg

examples:
  - |
    pinctrl@70000000 {
        compatible = "nvidia,tegra30-pinmux";
        reg = <0x70000868 0x0d0>, /* Pad control registers */
              <0x70003000 0x3e0>; /* Mux registers */

        pinmux {
            sdmmc4_clk_pcc4 {
                nvidia,pins = "sdmmc4_clk_pcc4",
                              "sdmmc4_rst_n_pcc3";
                nvidia,function = "sdmmc4";
                nvidia,pull = <0>;
                nvidia,tristate = <0>;
            };

            sdmmc4_dat0_paa0 {
                nvidia,pins = "sdmmc4_dat0_paa0",
                              "sdmmc4_dat1_paa1",
                              "sdmmc4_dat2_paa2",
                              "sdmmc4_dat3_paa3",
                              "sdmmc4_dat4_paa4",
                              "sdmmc4_dat5_paa5",
                              "sdmmc4_dat6_paa6",
                              "sdmmc4_dat7_paa7";
                nvidia,function = "sdmmc4";
                nvidia,pull = <2>;
                nvidia,tristate = <0>;
            };
        };
    };
...


code:
NXP LPC18xx/43xx SCU pin controller Device Tree Bindings
--------------------------------------------------------

Required properties:
- compatible		: Should be "nxp,lpc1850-scu"
- reg			: Address and length of the register set for the device
- clocks		: Clock specifier (see clock bindings for details)

The lpc1850-scu driver uses the generic pin multiplexing and generic pin
configuration documented in pinctrl-bindings.txt.

The following generic nodes are supported:
 - function
 - pins
 - bias-disable
 - bias-pull-up
 - bias-pull-down
 - drive-strength
 - input-enable
 - input-disable
 - input-schmitt-enable
 - input-schmitt-disable
 - slew-rate

NXP specific properties:
 - nxp,gpio-pin-interrupt : Assign pin to gpio pin interrupt controller
			    irq number 0 to 7. See example below.

Not all pins support all properties so either refer to the NXP 1850/4350
user manual or the pin table in the pinctrl-lpc18xx driver for supported
pin properties.

Example:
pinctrl: pinctrl@40086000 {
	compatible = "nxp,lpc1850-scu";
	reg = <0x40086000 0x1000>;
	clocks = <&ccu1 CLK_CPU_SCU>;

	i2c0_pins: i2c0-pins {
		i2c0_pins_cfg {
			pins = "i2c0_scl", "i2c0_sda";
			function = "i2c0";
			input-enable;
		};
	};

	uart0_pins: uart0-pins {
		uart0_rx_cfg {
			pins = "pf_11";
			function = "uart0";
			bias-disable;
			input-enable;
		};

		uart0_tx_cfg {
			pins = "pf_10";
			function = "uart0";
			bias-disable;
		};
	};

	gpio_joystick_pins: gpio-joystick-pins {
		gpio_joystick_1_cfg {
			pins =  "p9_0";
			function = "gpio";
			nxp,gpio-pin-interrupt = <0>;
			input-enable;
			bias-disable;
		};
	};
};

repo_name: angery/linux


code:
* Oxford Semiconductor OXNAS SoC Family Pin Controller

Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
../interrupt-controller/interrupts.txt for generic information regarding
pin controller, GPIO, and interrupt bindings.

OXNAS 'pin configuration node' is a node of a group of pins which can be
used for a specific device or function. This node represents configurations of
pins, optional function, and optional mux related configuration.

Required properties for pin controller node:
 - compatible: "oxsemi,ox810se-pinctrl" or "oxsemi,ox820-pinctrl"
 - oxsemi,sys-ctrl: a phandle to the system controller syscon node

Required properties for pin configuration sub-nodes:
 - pins: List of pins to which the configuration applies.

Optional properties for pin configuration sub-nodes:
----------------------------------------------------
 - function: Mux function for the specified pins.
 - bias-pull-up: Enable weak pull-up.

Example:

pinctrl: pinctrl {
	compatible = "oxsemi,ox810se-pinctrl";

	/* Regmap for sys registers */
	oxsemi,sys-ctrl = <&sys>;

	pinctrl_uart2: pinctrl_uart2 {
		uart2a {
			pins = "gpio31";
			function = "fct3";
		};
		uart2b {
			pins = "gpio32";
			function = "fct3";
		};
	};
};

uart2: serial@900000 {
	compatible = "ns16550a";
	reg = <0x900000 0x100000>;
	clocks = <&sysclk>;
	interrupts = <29>;
	reg-shift = <0>;
	fifo-size = <16>;
	reg-io-width = <1>;
	current-speed = <115200>;
	no-loopback-test;
	resets = <&reset 22>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic pin configuration node schema

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description:
  Many data items that are represented in a pin configuration node are common
  and generic. Pin control bindings should use the properties defined below
  where they are applicable; not all of these properties are relevant or useful
  for all hardware or binding structures. Each individual binding document
  should state which of these generic properties, if any, are used, and the
  structure of the DT nodes that contain these properties.

properties:
  bias-disable:
    type: boolean
    description: disable any pin bias

  bias-high-impedance:
    type: boolean
    description: high impedance mode ("third-state", "floating")

  bias-bus-hold:
    type: boolean
    description: latch weakly

  bias-pull-up:
    oneOf:
      - type: boolean
      - $ref: /schemas/types.yaml#/definitions/uint32
    description: pull up the pin. Takes as optional argument on hardware
      supporting it the pull strength in Ohm.

  bias-pull-down:
    oneOf:
      - type: boolean
      - $ref: /schemas/types.yaml#/definitions/uint32
    description: pull down the pin. Takes as optional argument on hardware
      supporting it the pull strength in Ohm.

  bias-pull-pin-default:
    oneOf:
      - type: boolean
      - $ref: /schemas/types.yaml#/definitions/uint32
    description: use pin-default pull state. Takes as optional argument on
      hardware supporting it the pull strength in Ohm.

  drive-push-pull:
    oneOf:
      - type: boolean
      - $ref: /schemas/types.yaml#/definitions/uint32
        enum: [ 0, 1 ]
        deprecated: true
    description: drive actively high and low

  drive-open-drain:
    oneOf:
      - type: boolean
      - $ref: /schemas/types.yaml#/definitions/uint32
        const: 1    # No known cases of 0
        deprecated: true
    description: drive with open drain

  drive-open-source:
    type: boolean
    description: drive with open source

  drive-strength:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: sink or source at most X mA

  drive-strength-microamp:
    description: sink or source at most X uA

  input-enable:
    type: boolean
    description: enable input on pin (no effect on output, such as
      enabling an input buffer)

  input-disable:
    type: boolean
    description: disable input on pin (no effect on output, such as
      disabling an input buffer)

  input-schmitt-enable:
    type: boolean
    description: enable schmitt-trigger mode

  input-schmitt-disable:
    type: boolean
    description: disable schmitt-trigger mode

  input-debounce:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Takes the debounce time in usec as argument or 0 to disable
      debouncing

  power-source:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: select between different power supplies

  low-power-enable:
    type: boolean
    description: enable low power mode

  low-power-disable:
    type: boolean
    description: disable low power mode

  output-disable:
    type: boolean
    description: disable output on a pin (such as disable an output buffer)

  output-enable:
    type: boolean
    description: enable output on a pin without actively driving it
      (such as enabling an output buffer)

  output-impedance-ohms:
    description: set the output impedance of a pin to at most X ohms

  output-low:
    type: boolean
    description: set the pin to output mode with low level

  output-high:
    type: boolean
    description: set the pin to output mode with high level

  sleep-hardware-state:
    type: boolean
    description: indicate this is sleep related state which will be
      programmed into the registers for the sleep state.

  slew-rate:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: set the slew rate

  skew-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      this affects the expected clock skew on input pins
      and the delay before latching a value to an output
      pin. Typically indicates how many double-inverters are
      used to delay the signal.

additionalProperties: true


code:
== Introduction ==

Hardware modules that control pin multiplexing or configuration parameters
such as pull-up/down, tri-state, drive-strength etc are designated as pin
controllers. Each pin controller must be represented as a node in device tree,
just like any other hardware module.

Hardware modules whose signals are affected by pin configuration are
designated client devices. Again, each client device must be represented as a
node in device tree, just like any other hardware module.

For a client device to operate correctly, certain pin controllers must
set up certain specific pin configurations. Some client devices need a
single static pin configuration, e.g. set up during initialization. Others
need to reconfigure pins at run-time, for example to tri-state pins when the
device is inactive. Hence, each client device can define a set of named
states. The number and names of those states is defined by the client device's
own binding.

The common pinctrl bindings defined in this file provide an infrastructure
for client device device tree nodes to map those state names to the pin
configuration used by those states.

Note that pin controllers themselves may also be client devices of themselves.
For example, a pin controller may set up its own "active" state when the
driver loads. This would allow representing a board's static pin configuration
in a single place, rather than splitting it across multiple client device
nodes. The decision to do this or not somewhat rests with the author of
individual board device tree files, and any requirements imposed by the
bindings for the individual client devices in use by that board, i.e. whether
they require certain specific named states for dynamic pin configuration.

== Pinctrl client devices ==

For each client device individually, every pin state is assigned an integer
ID. These numbers start at 0, and are contiguous. For each state ID, a unique
property exists to define the pin configuration. Each state may also be
assigned a name. When names are used, another property exists to map from
those names to the integer IDs.

Each client device's own binding determines the set of states that must be
defined in its device tree node, and whether to define the set of state
IDs that must be provided, or whether to define the set of state names that
must be provided.

Required properties:
pinctrl-0:	List of phandles, each pointing at a pin configuration
		node. These referenced pin configuration nodes must be child
		nodes of the pin controller that they configure. Multiple
		entries may exist in this list so that multiple pin
		controllers may be configured, or so that a state may be built
		from multiple nodes for a single pin controller, each
		contributing part of the overall configuration. See the next
		section of this document for details of the format of these
		pin configuration nodes.

		In some cases, it may be useful to define a state, but for it
		to be empty. This may be required when a common IP block is
		used in an SoC either without a pin controller, or where the
		pin controller does not affect the HW module in question. If
		the binding for that IP block requires certain pin states to
		exist, they must still be defined, but may be left empty.

Optional properties:
pinctrl-1:	List of phandles, each pointing at a pin configuration
		node within a pin controller.
...
pinctrl-n:	List of phandles, each pointing at a pin configuration
		node within a pin controller.
pinctrl-names:	The list of names to assign states. List entry 0 defines the
		name for integer state ID 0, list entry 1 for state ID 1, and
		so on.

For example:

	/* For a client device requiring named states */
	device {
		pinctrl-names = "active", "idle";
		pinctrl-0 = <&state_0_node_a>;
		pinctrl-1 = <&state_1_node_a>, <&state_1_node_b>;
	};

	/* For the same device if using state IDs */
	device {
		pinctrl-0 = <&state_0_node_a>;
		pinctrl-1 = <&state_1_node_a>, <&state_1_node_b>;
	};

	/*
	 * For an IP block whose binding supports pin configuration,
	 * but in use on an SoC that doesn't have any pin control hardware
	 */
	device {
		pinctrl-names = "active", "idle";
		pinctrl-0 = <>;
		pinctrl-1 = <>;
	};

== Pin controller devices ==

See pinctrl.yaml

== Generic pin multiplexing node content ==

See pinmux-node.yaml

== Generic pin configuration node content ==

See pincfg-node.yaml


code:
Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor.

Device has 8 GPIO pins which can be configured as GPIO as well as the
special IO functions.

Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
for details of the common pinctrl bindings used by client devices,
including the meaning of the phrase "pin configuration node".

Optional Pinmux properties:
--------------------------
Following properties are required if default setting of pins are required
at boot.
- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
		<pinctrl-bindings.txt>.

The pin configurations are defined as child of the pinctrl states node. Each
sub-node have following properties:

Required properties:
------------------
- pins: List of pins. Valid values of pins properties are:
		      gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7.

Optional properties:
-------------------
Following are optional properties defined as pinmux DT binding document
<pinctrl-bindings.txt>. Absence of properties will leave the configuration
on default.
	function,
	drive-push-pull,
	drive-open-drain,
	bias-pull-up,
	bias-pull-down.

Valid values for function properties are:
	gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in,
	reference-out

Theres is also customised properties for the GPIO1, GPIO2 and GPIO3. These
customised properties are required to configure FPS configuration parameters
of these GPIOs. Please refer <devicetree/bindings/mfd/max77620.txt> for more
detail of Flexible Power Sequence (FPS).

- maxim,active-fps-source:		FPS source for the GPIOs to get
					enabled/disabled when system is in
					active state.  Valid values are:
					- MAX77620_FPS_SRC_0,
						FPS source is FPS0.
					- MAX77620_FPS_SRC_1,
						FPS source is FPS1
					- MAX77620_FPS_SRC_2 and
						FPS source is FPS2
					- MAX77620_FPS_SRC_NONE.
						GPIO is not controlled
						by FPS events and it gets
						enabled/disabled by register
						access.
					Absence of this property will leave
					the FPS configuration register for that
					GPIO to default configuration.

- maxim,active-fps-power-up-slot:	Sequencing event slot number on which
					the GPIO get enabled when
					master FPS input event set to HIGH.
					Valid values are 0 to 7.
					This is applicable if FPS source is
					selected as FPS0, FPS1 or FPS2.

- maxim,active-fps-power-down-slot:	Sequencing event slot number on which
					the GPIO get disabled when master
					FPS input event set to LOW.
					Valid values are 0 to 7.
					This is applicable if FPS source is
					selected as FPS0, FPS1 or FPS2.

- maxim,suspend-fps-source:		This is same as property
					"maxim,active-fps-source" but value
					get configured when system enters in
					to suspend state.

- maxim,suspend-fps-power-up-slot:	This is same as property
					"maxim,active-fps-power-up-slot" but
					this value get configured into FPS
					configuration register when system
					enters into suspend.
					This is applicable if suspend state
					FPS source is selected as FPS0, FPS1 or

- maxim,suspend-fps-power-down-slot:	This is same as property
					"maxim,active-fps-power-down-slot" but
					this value get configured into FPS
					configuration register when system
					enters into suspend.
					This is applicable if suspend state
					FPS source is selected as FPS0, FPS1 or
					FPS2.

Example:
--------
#include <dt-bindings/mfd/max77620.h>
...
max77620@3c {

	pinctrl-names = "default";
	pinctrl-0 = <&spmic_default>;

	spmic_default: pinmux@0 {
		pin_gpio0 {
			pins = "gpio0";
			function = "gpio";
		};

		pin_gpio1 {
			pins = "gpio1";
			function = "fps-out";
			maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
		};

		pin_gpio2 {
			pins = "gpio2";
			function = "fps-out";
			maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
		};
	};
};


code:
Microchip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for
8-/16-bit I/O expander with serial interface (I2C/SPI)

Required properties:
- compatible : Should be
    - "mcp,mcp23s08" (DEPRECATED) for  8 GPIO SPI version
    - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
    - "mcp,mcp23008" (DEPRECATED) for  8 GPIO I2C version or
    - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip

    - "microchip,mcp23s08" for  8 GPIO SPI version
    - "microchip,mcp23s17" for 16 GPIO SPI version
    - "microchip,mcp23s18" for 16 GPIO SPI version
    - "microchip,mcp23008" for  8 GPIO I2C version or
    - "microchip,mcp23017" for 16 GPIO I2C version of the chip
    - "microchip,mcp23018" for 16 GPIO I2C version
    NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
    removed.
- #gpio-cells : Should be two.
  - first cell is the pin number
  - second cell is used to specify flags as described in
    'Documentation/devicetree/bindings/gpio/gpio.txt'. Allowed values defined by
    'include/dt-bindings/gpio/gpio.h' (e.g. GPIO_ACTIVE_LOW).
- gpio-controller : Marks the device node as a GPIO controller.
- reg : For an address on its bus. I2C uses this a the I2C address of the chip.
        SPI uses this to specify the chipselect line which the chip is
        connected to. The driver and the SPI variant of the chip support
        multiple chips on the same chipselect. Have a look at
        microchip,spi-present-mask below.

Required device specific properties (only for SPI chips):
- mcp,spi-present-mask (DEPRECATED)
- microchip,spi-present-mask : This is a present flag, that makes only sense for SPI
        chips - as the name suggests. Multiple SPI chips can share the same
        SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a
        chip connected with the corresponding spi address set. For example if
        you have a chip with address 3 connected, you have to set bit3 to 1,
        which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not
        possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at
        least one bit to 1 for SPI chips.
    NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
    removed.
- spi-max-frequency = The maximum frequency this chip is able to handle

Optional properties:
- #interrupt-cells : Should be two.
  - first cell is the pin number
  - second cell is used to specify flags.
- interrupt-controller: Marks the device node as a interrupt controller.
- drive-open-drain: Sets the ODR flag in the IOCON register. This configures
        the IRQ output as open drain active low.
- reset-gpios: Corresponds to the active-low RESET# pin for the chip

Optional device specific properties:
- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices
        with two interrupt outputs (these are the devices ending with 17 and
        those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and
        IO 8-15 are bank 2. These chips have two different interrupt outputs:
        One for bank 1 and another for bank 2. If irq-mirror is set, both
        interrupts are generated regardless of the bank that an input change
        occurred on. If it is not set, the interrupt are only generated for the
        bank they belong to.
        On devices with only one interrupt output this property is useless.
- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This
        configures the IRQ output polarity as active high.

Example I2C (with interrupt):
gpiom1: gpio@20 {
        compatible = "microchip,mcp23017";
        gpio-controller;
        #gpio-cells = <2>;
        reg = <0x20>;

        interrupt-parent = <&gpio1>;
        interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
        interrupt-controller;
        #interrupt-cells=<2>;
        microchip,irq-mirror;
};

Example SPI:
gpiom1: gpio@0 {
        compatible = "microchip,mcp23s17";
        gpio-controller;
        #gpio-cells = <2>;
        microchip,spi-present-mask = <0x01>;
        reg = <0>;
        spi-max-frequency = <1000000>;
};

Pull-up configuration
=====================

If pins are used as output, they can also be configured with pull-ups. This is
done with pinctrl.

Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
for details of the common pinctrl bindings used by client devices,
including the meaning of the phrase "pin configuration node".

Optional Pinmux properties:
--------------------------
Following properties are required if default setting of pins are required
at boot.
- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
		<pinctrl-bindings.txt>.

The pin configurations are defined as child of the pinctrl states node. Each
sub-node have following properties:

Required properties:
------------------
- pins: List of pins. Valid values of pins properties are:
		      gpio0 ... gpio7 for the devices with 8 GPIO pins and
		      gpio0 ... gpio15 for the devices with 16 GPIO pins.

Optional properties:
-------------------
The following optional property is defined in the pinmux DT binding document
<pinctrl-bindings.txt>. Absence of this property will leave the configuration
in its default state.
	bias-pull-up

Example with pinctrl to pull-up output pins:
gpio21: gpio@21 {
	compatible = "microchip,mcp23017";
	gpio-controller;
	#gpio-cells = <0x2>;
	reg = <0x21>;
	interrupt-parent = <&socgpio>;
	interrupts = <0x17 0x8>;
	interrupt-names = "mcp23017@21 irq";
	interrupt-controller;
	#interrupt-cells = <0x2>;
	microchip,irq-mirror;
	pinctrl-names = "default";
	pinctrl-0 = <&i2cgpio0irq>, <&gpio21pullups>;
	reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;

	gpio21pullups: pinmux {
		pins =	"gpio0", "gpio1", "gpio2", "gpio3",
			"gpio4", "gpio5", "gpio6", "gpio7",
			"gpio8", "gpio9", "gpio10", "gpio11",
			"gpio12", "gpio13", "gpio14", "gpio15";
		bias-pull-up;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT8186 Pin Controller

maintainers:
  - Sean Wang <sean.wang@mediatek.com>

description: |
  The Mediatek's Pin controller is used to control SoC pins.

properties:
  compatible:
    const: mediatek,mt8186-pinctrl

  gpio-controller: true

  '#gpio-cells':
    description: |
      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
      the amount of cells must be specified as 2. See the below
      mentioned gpio binding representation for description of particular cells.
    const: 2

  gpio-ranges:
    maxItems: 1

  gpio-line-names: true

  reg:
    description: |
      Physical address base for gpio base registers. There are 8 different GPIO
      physical address base in mt8186.
    maxItems: 8

  reg-names:
    description: |
      Gpio base register names.
    items:
      - const: iocfg0
      - const: iocfg_lt
      - const: iocfg_lm
      - const: iocfg_lb
      - const: iocfg_bl
      - const: iocfg_rb
      - const: iocfg_rt
      - const: eint

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  interrupts:
    description: The interrupt outputs to sysirq
    maxItems: 1

  mediatek,rsel-resistance-in-si-unit:
    type: boolean
    description: |
      Identifying i2c pins pull up/down type which is RSEL. It can support
      RSEL define or si unit value(ohm) to set different resistance.

# PIN CONFIGURATION NODES
patternProperties:
  '-pins$':
    type: object
    additionalProperties: false
    patternProperties:
      '^pins':
        type: object
        additionalProperties: false
        description: |
          A pinctrl node should contain at least one subnodes representing the
          pinctrl groups available on the machine. Each subnode will list the
          pins it needs, and how they should be configured, with regard to muxer
          configuration, pullups, drive strength, input enable/disable and
          input schmitt.
          An example of using macro:
          pincontroller {
            /* GPIO0 set as multifunction GPIO0 */
            gpio-pins {
              pins {
                pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
              }
            };
            /* GPIO128 set as multifunction SDA0 */
            i2c0-pins {
              pins {
                pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
              }
            };
          };
        $ref: "pinmux-node.yaml"

        properties:
          pinmux:
            description: |
              Integer array, represents gpio pin number and mux setting.
              Supported pin number and mux varies for different SoCs, and are
              defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
              directly.

          drive-strength:
            enum: [2, 4, 6, 8, 10, 12, 14, 16]

          drive-strength-microamp:
            enum: [125, 250, 500, 1000]

          bias-pull-down:
            oneOf:
              - type: boolean
              - enum: [100, 101, 102, 103]
                description: mt8186 pull down PUPD/R0/R1 type define value.
              - enum: [200, 201, 202, 203]
                description: mt8186 pull down RSEL type define value.
              - enum: [75000, 5000]
                description: mt8186 pull down RSEL type si unit value(ohm).
            description: |
              For pull down type is normal, it don't need add RSEL & R1R0 define
              and resistance value.
              For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
              set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
              "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
              "MTK_PUPD_SET_R1R0_11" define in mt8186.
              For pull down type is RSEL, it can add RSEL define & resistance
              value(ohm) to set different resistance by identifying property
              "mediatek,rsel-resistance-in-si-unit".
              It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
              & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
              define in mt8186. It can also support resistance value(ohm)
              "75000" & "5000" in mt8186.
              An example of using RSEL define:
              pincontroller {
                i2c0_pin {
                  pins {
                    pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
                    bias-pull-down = <MTK_PULL_SET_RSEL_001>;
                  }
                };
              };
              An example of using si unit resistance value(ohm):
              &pio {
                mediatek,rsel-resistance-in-si-unit;
              }
              pincontroller {
                i2c0_pin {
                  pins {
                    pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
                    bias-pull-down = <75000>;
                  }
                };
              };

          bias-pull-up:
            oneOf:
              - type: boolean
              - enum: [100, 101, 102, 103]
                description: mt8186 pull up PUPD/R0/R1 type define value.
              - enum: [200, 201, 202, 203]
                description: mt8186 pull up RSEL type define value.
              - enum: [1000, 5000, 10000, 75000]
                description: mt8186 pull up RSEL type si unit value(ohm).
            description: |
              For pull up type is normal, it don't need add RSEL & R1R0 define
              and resistance value.
              For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
              set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
              "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
              "MTK_PUPD_SET_R1R0_11" define in mt8186.
              For pull up type is RSEL, it can add RSEL define & resistance
              value(ohm) to set different resistance by identifying property
              "mediatek,rsel-resistance-in-si-unit".
              It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
              & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
              define in mt8186. It can also support resistance value(ohm)
              "1000" & "5000" & "10000" & "75000" in mt8186.
              An example of using si unit resistance value(ohm):
              &pio {
                mediatek,rsel-resistance-in-si-unit;
              }
              pincontroller {
                i2c0-pins {
                  pins {
                    pinmux = <PINMUX_GPIO128__FUNC_SDA0>;
                    bias-pull-up = <1000>;
                  }
                };
              };

          bias-disable: true

          output-high: true

          output-low: true

          input-enable: true

          input-disable: true

          input-schmitt-enable: true

          input-schmitt-disable: true

        required:
          - pinmux

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pio: pinctrl@10005000 {
      compatible = "mediatek,mt8186-pinctrl";
      reg = <0x10005000 0x1000>,
            <0x10002000 0x0200>,
            <0x10002200 0x0200>,
            <0x10002400 0x0200>,
            <0x10002600 0x0200>,
            <0x10002A00 0x0200>,
            <0x10002c00 0x0200>,
            <0x1000b000 0x1000>;
      reg-names = "iocfg0", "iocfg_lt", "iocfg_lm",
                  "iocfg_lb", "iocfg_bl", "iocfg_rb",
                  "iocfg_rt", "eint";
      gpio-controller;
      #gpio-cells = <2>;
      gpio-ranges = <&pio 0 0 185>;
      interrupt-controller;
      interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
      #interrupt-cells = <2>;

      pio-pins {
        pins {
          pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
          output-low;
        };
      };

      spi0-pins {
        pins-spi {
          pinmux = <PINMUX_GPIO0__FUNC_SPI0_CLK_B>,
                   <PINMUX_GPIO1__FUNC_SPI0_CSB_B>,
                   <PINMUX_GPIO2__FUNC_SPI0_MO_B>;
          bias-disable;
        };
        pins-spi-mi {
          pinmux = <PINMUX_GPIO3__FUNC_SPI0_MI_B>;
          bias-pull-down;
        };
      };

      i2c0-pins {
        pins {
          pinmux = <PINMUX_GPIO127__FUNC_SCL0>,
                   <PINMUX_GPIO128__FUNC_SDA0>;
          bias-pull-up = <MTK_PULL_SET_RSEL_001>;
          drive-strength-microamp = <1000>;
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT8192 Pin Controller

maintainers:
  - Sean Wang <sean.wang@mediatek.com>

description: |
  The Mediatek's Pin controller is used to control SoC pins.

properties:
  compatible:
    const: mediatek,mt8192-pinctrl

  gpio-controller: true

  '#gpio-cells':
    description: |
      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
      the amount of cells must be specified as 2. See the below
      mentioned gpio binding representation for description of particular cells.
    const: 2

  gpio-ranges:
    description: gpio valid number range.
    maxItems: 1

  gpio-line-names: true

  reg:
    description: |
      Physical address base for gpio base registers. There are 11 GPIO
      physical address base in mt8192.
    maxItems: 11

  reg-names:
    description: |
      Gpio base register names.
    maxItems: 11

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  interrupts:
    description: The interrupt outputs to sysirq.
    maxItems: 1

#PIN CONFIGURATION NODES
patternProperties:
  '-pins$':
    type: object
    additionalProperties: false
    patternProperties:
      '^pins':
        type: object
        description: |
          A pinctrl node should contain at least one subnodes representing the
          pinctrl groups available on the machine. Each subnode will list the
          pins it needs, and how they should be configured, with regard to muxer
          configuration, pullups, drive strength, input enable/disable and
          input schmitt.
        $ref: "pinmux-node.yaml"

        properties:
          pinmux:
            description: |
              Integer array, represents gpio pin number and mux setting.
              Supported pin number and mux varies for different SoCs, and are defined
              as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.

          drive-strength:
            description: |
              It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
              dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
            enum: [2, 4, 6, 8, 10, 12, 14, 16]

          drive-strength-microamp:
            enum: [125, 250, 500, 1000]

          bias-pull-down:
            oneOf:
              - type: boolean
                description: normal pull down.
              - enum: [100, 101, 102, 103]
                description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_
                  defines in dt-bindings/pinctrl/mt65xx.h.
              - enum: [200, 201, 202, 203]
                description: RSEL pull down type. See MTK_PULL_SET_RSEL_
                  defines in dt-bindings/pinctrl/mt65xx.h.

          bias-pull-up:
            oneOf:
              - type: boolean
                description: normal pull up.
              - enum: [100, 101, 102, 103]
                description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_
                  defines in dt-bindings/pinctrl/mt65xx.h.
              - enum: [200, 201, 202, 203]
                description: RSEL pull up type. See MTK_PULL_SET_RSEL_
                  defines in dt-bindings/pinctrl/mt65xx.h.

          bias-disable: true

          output-high: true

          output-low: true

          input-enable: true

          input-disable: true

          input-schmitt-enable: true

          input-schmitt-disable: true

        required:
          - pinmux

        additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges

additionalProperties: false

examples:
  - |
            #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
            #include <dt-bindings/interrupt-controller/arm-gic.h>
            pio: pinctrl@10005000 {
                    compatible = "mediatek,mt8192-pinctrl";
                    reg = <0x10005000 0x1000>,
                          <0x11c20000 0x1000>,
                          <0x11d10000 0x1000>,
                          <0x11d30000 0x1000>,
                          <0x11d40000 0x1000>,
                          <0x11e20000 0x1000>,
                          <0x11e70000 0x1000>,
                          <0x11ea0000 0x1000>,
                          <0x11f20000 0x1000>,
                          <0x11f30000 0x1000>,
                          <0x1000b000 0x1000>;
                    reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
                          "iocfg_bl", "iocfg_br", "iocfg_lm",
                          "iocfg_lb", "iocfg_rt", "iocfg_lt",
                          "iocfg_tl", "eint";
                    gpio-controller;
                    #gpio-cells = <2>;
                    gpio-ranges = <&pio 0 0 220>;
                    interrupt-controller;
                    interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
                    #interrupt-cells = <2>;

                    spi1-default-pins {
                            pins-cs-mosi-clk {
                                    pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
                                             <PINMUX_GPIO159__FUNC_SPI1_A_MO>,
                                             <PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
                                    bias-disable;
                            };

                            pins-miso {
                                    pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
                                    bias-pull-down;
                            };
                    };
            };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT8195 Pin Controller

maintainers:
  - Sean Wang <sean.wang@mediatek.com>

description: |
  The Mediatek's Pin controller is used to control SoC pins.

properties:
  compatible:
    const: mediatek,mt8195-pinctrl

  gpio-controller: true

  '#gpio-cells':
    description: |
      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
      the amount of cells must be specified as 2. See the below
      mentioned gpio binding representation for description of particular cells.
    const: 2

  gpio-ranges:
    description: gpio valid number range.
    maxItems: 1

  gpio-line-names: true

  reg:
    description: |
      Physical address base for gpio base registers. There are 8 GPIO
      physical address base in mt8195.
    maxItems: 8

  reg-names:
    description: |
      Gpio base register names.
    maxItems: 8

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  interrupts:
    description: The interrupt outputs to sysirq.
    maxItems: 1

  mediatek,rsel-resistance-in-si-unit:
    type: boolean
    description: |
      Identifying i2c pins pull up/down type which is RSEL. It can support
      RSEL define or si unit value(ohm) to set different resistance.

# PIN CONFIGURATION NODES
patternProperties:
  '-pins$':
    type: object
    additionalProperties: false
    patternProperties:
      '^pins':
        type: object
        additionalProperties: false
        description: |
          A pinctrl node should contain at least one subnodes representing the
          pinctrl groups available on the machine. Each subnode will list the
          pins it needs, and how they should be configured, with regard to muxer
          configuration, pullups, drive strength, input enable/disable and
          input schmitt.
          An example of using macro:
          pincontroller {
            /* GPIO0 set as multifunction GPIO0 */
            gpio-pins {
              pins {
                pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
              }
            };
            /* GPIO8 set as multifunction SDA0 */
            i2c0-pins {
              pins {
                pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
              }
            };
          };
        $ref: "pinmux-node.yaml"

        properties:
          pinmux:
            description: |
              Integer array, represents gpio pin number and mux setting.
              Supported pin number and mux varies for different SoCs, and are
              defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
              directly.

          drive-strength:
            enum: [2, 4, 6, 8, 10, 12, 14, 16]

          drive-strength-microamp:
            enum: [125, 250, 500, 1000]

          bias-pull-down:
            oneOf:
              - type: boolean
              - enum: [100, 101, 102, 103]
                description: mt8195 pull down PUPD/R0/R1 type define value.
              - enum: [200, 201, 202, 203, 204, 205, 206, 207]
                description: mt8195 pull down RSEL type define value.
              - enum: [75000, 5000]
                description: mt8195 pull down RSEL type si unit value(ohm).
            description: |
              For pull down type is normal, it don't need add RSEL & R1R0 define
              and resistance value.
              For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
              set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
              "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
              "MTK_PUPD_SET_R1R0_11" define in mt8195.
              For pull down type is RSEL, it can add RSEL define & resistance
              value(ohm) to set different resistance by identifying property
              "mediatek,rsel-resistance-in-si-unit".
              It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
              & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
              & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
              & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
              define in mt8195. It can also support resistance value(ohm)
              "75000" & "5000" in mt8195.

              An example of using RSEL define:
              pincontroller {
                i2c0_pin {
                  pins {
                    pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
                    bias-pull-down = <MTK_PULL_SET_RSEL_001>;
                  }
                };
              };
              An example of using si unit resistance value(ohm):
              &pio {
                mediatek,rsel-resistance-in-si-unit;
              }
              pincontroller {
                i2c0_pin {
                  pins {
                    pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
                    bias-pull-down = <75000>;
                  }
                };
              };

          bias-pull-up:
            oneOf:
              - type: boolean
              - enum: [100, 101, 102, 103]
                description: mt8195 pull up PUPD/R0/R1 type define value.
              - enum: [200, 201, 202, 203, 204, 205, 206, 207]
                description: mt8195 pull up RSEL type define value.
              - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
                description: mt8195 pull up RSEL type si unit value(ohm).
            description: |
              For pull up type is normal, it don't need add RSEL & R1R0 define
              and resistance value.
              For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
              set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
              "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
              "MTK_PUPD_SET_R1R0_11" define in mt8195.
              For pull up type is RSEL, it can add RSEL define & resistance
              value(ohm) to set different resistance by identifying property
              "mediatek,rsel-resistance-in-si-unit".
              It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
              & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011"
              & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101"
              & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
              define in mt8195. It can also support resistance value(ohm)
              "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" &
              "75000" in mt8195.
              An example of using RSEL define:
              pincontroller {
                i2c0-pins {
                  pins {
                    pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
                    bias-pull-up = <MTK_PULL_SET_RSEL_001>;
                  }
                };
              };
              An example of using si unit resistance value(ohm):
              &pio {
                mediatek,rsel-resistance-in-si-unit;
              }
              pincontroller {
                i2c0-pins {
                  pins {
                    pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
                    bias-pull-up = <1000>;
                  }
                };
              };

          bias-disable: true

          output-high: true

          output-low: true

          input-enable: true

          input-disable: true

          input-schmitt-enable: true

          input-schmitt-disable: true

        required:
          - pinmux

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #
    pio: pinctrl@10005000 {
      compatible = "mediatek,mt8195-pinctrl";
      reg = <0x10005000 0x1000>,
            <0x11d10000 0x1000>,
            <0x11d30000 0x1000>,
            <0x11d40000 0x1000>,
            <0x11e20000 0x1000>,
            <0x11eb0000 0x1000>,
            <0x11f40000 0x1000>,
            <0x1000b000 0x1000>;
      reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
                  "iocfg_br", "iocfg_lm", "iocfg_rb",
                  "iocfg_tl", "eint";
      gpio-controller;
      #gpio-cells = <2>;
      gpio-ranges = <&pio 0 0 144>;
      interrupt-controller;
      interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
      #interrupt-cells = <2>;

      pio-pins {
        pins {
          pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
          output-low;
        };
      };

      spi0-pins {
        pins-spi {
          pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
                   <PINMUX_GPIO134__FUNC_SPIM0_MO>,
                   <PINMUX_GPIO133__FUNC_SPIM0_CLK>;
          bias-disable;
        };
        pins-spi-mi {
          pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
          bias-pull-down;
        };
      };

      i2c0-pins {
        pins {
          pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
                   <PINMUX_GPIO9__FUNC_SCL0>;
          bias-disable;
          drive-strength-microamp = <1000>;
        };
      };
    };


code:
Palmas Pincontrol bindings

The pins of Palmas device can be set on different option and provides
the configuration for Pull UP/DOWN, open drain etc.

Required properties:
- compatible: It must be one of following:
  - "ti,palmas-pinctrl" for Palma series of the pincontrol.
  - "ti,tps65913-pinctrl" for Palma series device TPS65913.
  - "ti,tps80036-pinctrl" for Palma series device TPS80036.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

Palmas's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
list of pins. This configuration can include the mux function to select on
those pin(s), and various pin configuration parameters, such as pull-up,
open drain.

The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.

Optional properties:
- ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode.
	Selection primary or secondary function associated to I2C2_SCL_SCE,
	I2C2_SDA_SDO pin/pad for DVFS1 interface
- ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode.
	Selection primary or secondary function associated to GPADC_START
	and SYSEN2 pin/pad for DVFS2 interface
- ti,palmas-override-powerhold: This is applicable for PMICs for which
	GPIO7 is configured in POWERHOLD mode which has higher priority
	over DEV_ON bit and keeps the PMIC supplies on even after the DEV_ON
	bit is turned off. This property enables driver to over ride the
	POWERHOLD value to GPIO7 so as to turn off the PMIC in power off
	scenarios. So for GPIO7 if ti,palmas-override-powerhold is set
	then the GPIO_7 field should never be muxed to anything else.
	It should be set to POWERHOLD by default and only in case of
	power off scenarios the driver will over ride the mux value.

This binding uses the following generic properties as defined in
pinctrl-bindings.txt:

Required: pins
Options: function, bias-disable, bias-pull-up, bias-pull-down,
	 drive-open-drain.

Note that many of these properties are only valid for certain specific pins.
See the Palmas device datasheet for complete details regarding which pins
support which functionality.

Valid values for pin names are:
	gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9,
	gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, vac, powergood,
	nreswarm, pwrdown, gpadc_start, reset_in, nsleep, enable1, enable2,
	int.

Valid value of function names are:
	gpio, led, pwm, regen, sysen, clk32kgaudio, id, vbus_det, chrg_det,
	vac, vacok, powergood, usb_psel, msecure, pwrhold, int, nreswarm,
	simrsto, simrsti, low_vbat, wireless_chrg1, rcm, pwrdown, gpadc_start,
	reset_in, nsleep, enable.

There are 4 special functions: opt0, opt1, opt2 and opt3. If any of these
functions is selected then directly pins register will be written with 0, 1, 2
or 3 respectively if it is valid for that pins or list of pins.

Example:
	palmas: tps65913 {
		....
		pinctrl {
			compatible = "ti,tps65913-pinctrl";
			ti,palmas-enable-dvfs1;
			pinctrl-names = "default";
			pinctrl-0 = <&palmas_pins_state>;

			palmas_pins_state: pinmux {
				gpio0 {
					pins = "gpio0";
					function = "id";
					bias-pull-up;
				};

				vac {
					pins = "vac";
					function = "vacok";
					bias-pull-down;
				};

				gpio5 {
					pins = "gpio5";
					function = "opt0";
					drive-open-drain = <1>;
				};
			};
		};
		....
	};


code:
Pincontrol driver for RK805 Power management IC.

RK805 has 2 pins which can be configured as GPIO output only.

Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
for details of the common pinctrl bindings used by client devices,
including the meaning of the phrase "pin configuration node".

Optional Pinmux properties:
--------------------------
Following properties are required if default setting of pins are required
at boot.
- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
		<pinctrl-bindings.txt>.

The pin configurations are defined as child of the pinctrl states node. Each
sub-node have following properties:

Required properties:
------------------
- #gpio-cells: Should be two. The first cell is the pin number and the
  second is the GPIO flags.

- gpio-controller: Marks the device node as a GPIO controller.

- pins: List of pins. Valid values of pins properties are: gpio0, gpio1.

First 2 properties must be added in the RK805 PMIC node, documented in
Documentation/devicetree/bindings/mfd/rockchip,rk808.yaml

Optional properties:
-------------------
Following are optional properties defined as pinmux DT binding document
<pinctrl-bindings.txt>. Absence of properties will leave the configuration
on default.
	function,
	output-low,
	output-high.

Valid values for function properties are: gpio.

Theres is also not customised properties for any GPIO.

Example:
--------
rk805: rk805@18 {
	compatible = "rockchip,rk805";
	...
	gpio-controller;
	#gpio-cells = <2>;

	pinctrl-names = "default";
	pinctrl-0 = <&pmic_int_l>, <&rk805_default>;

	rk805_default: pinmux {
		gpio01 {
			pins = "gpio0", "gpio1";
			function = "gpio";
			output-high;
		};
	};
};


code:
One-register-per-pin type device tree based pinctrl driver

Required properties:
- compatible : "pinctrl-single" or "pinconf-single".
  "pinctrl-single" means that pinconf isn't supported.
  "pinconf-single" means that generic pinconf is supported.

- reg : offset and length of the register set for the mux registers

- #pinctrl-cells : number of cells in addition to the index, set to 1
  or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits

- pinctrl-single,register-width : pinmux register access width in bits

- pinctrl-single,function-mask : mask of allowed pinmux function bits
  in the pinmux register

Optional properties:
- pinctrl-single,function-off : function off mode for disabled state if
  available and same for all registers; if not specified, disabling of
  pin functions is ignored

- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
  more than one pin, for which "pinctrl-single,function-mask" property specifies
 position mask of pin.

- pinctrl-single,drive-strength : array of value that are used to configure
  drive strength in the pinmux register. They're value of drive strength
  current and drive strength mask.

		/* drive strength current, mask */
		pinctrl-single,power-source = <0x30 0xf0>;

- pinctrl-single,bias-pullup : array of value that are used to configure the
  input bias pullup in the pinmux register.

		/* input, enabled pullup bits, disabled pullup bits, mask */
		pinctrl-single,bias-pullup = <0 1 0 1>;

- pinctrl-single,bias-pulldown : array of value that are used to configure the
  input bias pulldown in the pinmux register.

		/* input, enabled pulldown bits, disabled pulldown bits, mask */
		pinctrl-single,bias-pulldown = <2 2 0 2>;

  * Two bits to control input bias pullup and pulldown: User should use
    pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
    pullup, and the other one bit means pulldown.
  * Three bits to control input bias enable, pullup and pulldown. User should
    use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
    enable bit should be included in pullup or pulldown bits.
  * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
    pinctrl-single,bias-disable. Because pinctrl single driver could implement
    it by calling pulldown, pullup disabled.

- pinctrl-single,input-schmitt : array of value that are used to configure
  input schmitt in the pinmux register. In some silicons, there're two input
  schmitt value (rising-edge & falling-edge) in the pinmux register.

		/* input schmitt value, mask */
		pinctrl-single,input-schmitt = <0x30 0x70>;

- pinctrl-single,input-schmitt-enable : array of value that are used to
  configure input schmitt enable or disable in the pinmux register.

		/* input, enable bits, disable bits, mask */
		pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;

- pinctrl-single,low-power-mode : array of value that are used to configure
  low power mode of this pin. For some silicons, the low power mode will
  control the output of the pin when the pad including the pin enter low
  power mode.
		/* low power mode value, mask */
		pinctrl-single,low-power-mode = <0x288 0x388>;

- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
  range. They're value of subnode phandle, pin base in pinctrl device, pin
  number in this range, GPIO function value of this GPIO range.
  The number of parameters is depend on #pinctrl-single,gpio-range-cells
  property.

		/* pin base, nr pins & gpio function */
		pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>;

- interrupt-controller : standard interrupt controller binding if using
  interrupts for wake-up events for example. In this case pinctrl-single
  is set up as a chained interrupt controller and the wake-up interrupts
  can be requested by the drivers using request_irq().

- #interrupt-cells : standard interrupt binding if using interrupts

This driver assumes that there is only one register for each pin (unless the
pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
specified in the pinctrl-bindings.txt document in this directory.

The pin configuration nodes for pinctrl-single are specified as pinctrl
register offset and values using pinctrl-single,pins. Only the bits specified
in pinctrl-single,function-mask are updated.

When #pinctrl-cells = 1, then setting a pin for a device could be done with:

	pinctrl-single,pins = <0xdc 0x118>;

Where 0xdc is the offset from the pinctrl register base address for the device
pinctrl register, and 0x118 contains the desired value of the pinctrl register.

When #pinctrl-cells = 2, then setting a pin for a device could be done with:

	pinctrl-single,pins = <0xdc 0x30 0x07>;

Where 0x30 is the pin configuration value and 0x07 is the pin mux mode value.
These two values are OR'd together to produce the value stored at offset 0xdc.
See the device example and static board pins example below for more information.

In case when one register changes more than one pin's mux the
pinctrl-single,bits need to be used which takes three parameters:

	pinctrl-single,bits = <0xdc 0x18 0xff>;

Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
be used when applying this change to the register.

Optional sub-node: In case some pins could be configured as GPIO in the pinmux
register, those pins could be defined as a GPIO range. This sub-node is required
by pinctrl-single,gpio-range property.

Required properties in sub-node:
- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
  pinctrl-single,gpio-range property.

	range: gpio-range {
		#pinctrl-single,gpio-range-cells = <3>;
	};

Example:

/* SoC common file */

/* first controller instance for pins in core domain */
pmx_core: pinmux@4a100040 {
	compatible = "pinctrl-single";
	reg = <0x4a100040 0x0196>;
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	interrupt-controller;
	pinctrl-single,register-width = <16>;
	pinctrl-single,function-mask = <0xffff>;
};

/* second controller instance for pins in wkup domain */
pmx_wkup: pinmux@4a31e040 {
	compatible = "pinctrl-single";
	reg = <0x4a31e040 0x0038>;
	#address-cells = <1>;
	#size-cells = <0>;
	#interrupt-cells = <1>;
	interrupt-controller;
	pinctrl-single,register-width = <16>;
	pinctrl-single,function-mask = <0xffff>;
};

control_devconf0: pinmux@48002274 {
	compatible = "pinctrl-single";
	reg = <0x48002274 4>;	/* Single register */
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-single,bit-per-mux;
	pinctrl-single,register-width = <32>;
	pinctrl-single,function-mask = <0x5F>;
};

/* third controller instance for pins in gpio domain */
pmx_gpio: pinmux@d401e000 {
	compatible = "pinconf-single";
	reg = <0xd401e000 0x0330>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	pinctrl-single,register-width = <32>;
	pinctrl-single,function-mask = <7>;

	/* sparse GPIO range could be supported */
	pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>,
				    <&range 12 1 0>, <&range 13 29 1>,
				    <&range 43 1 0>, <&range 44 49 1>,
				    <&range 94 1 1>, <&range 96 2 1>;

	range: gpio-range {
		#pinctrl-single,gpio-range-cells = <3>;
	};
};

/* board specific .dts file */

&pmx_core {

	/*
	 * map all board specific static pins enabled by the pinctrl driver
	 * itself during the boot (or just set them up in the bootloader)
	 */
	pinctrl-names = "default";
	pinctrl-0 = <&board_pins>;

	board_pins: pinmux_board_pins {
		pinctrl-single,pins = <
			0x6c 0xf
			0x6e 0xf
			0x70 0xf
			0x72 0xf
		>;
	};

	uart0_pins: pinmux_uart0_pins {
		pinctrl-single,pins = <
			0x208 0		/* UART0_RXD (IOCFG138) */
			0x20c 0		/* UART0_TXD (IOCFG139) */
		>;
		pinctrl-single,bias-pulldown = <0 2 2>;
		pinctrl-single,bias-pullup = <0 1 1>;
	};

	/* map uart2 pins */
	uart2_pins: pinmux_uart2_pins {
		pinctrl-single,pins = <
			0xd8 0x118
			0xda 0
			0xdc 0x118
			0xde 0
		>;
	};
};

&control_devconf0 {
	mcbsp1_pins: pinmux_mcbsp1_pins {
		pinctrl-single,bits = <
			0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
		>;
	};

	mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
		pinctrl-single,bits = <
			0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
		>;
	};

};

&uart1 {
       pinctrl-names = "default";
       pinctrl-0 = <&uart0_pins>;
};

&uart2 {
       pinctrl-names = "default";
       pinctrl-0 = <&uart2_pins>;
};


code:
CSR SiRFprimaII pinmux controller

Required properties:
- compatible	: "sirf,prima2-pinctrl"
- reg		: Address range of the pinctrl registers
- interrupts    : Interrupts used by every GPIO group
- gpio-controller : Indicates this device is a GPIO controller
- interrupt-controller  : Marks the device node as an interrupt controller
Optional properties:
- sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
- sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m

Please refer to pinctrl-bindings.txt in this directory for details of the common
pinctrl bindings used by client devices.

SiRFprimaII's pinmux nodes act as a container for an arbitrary number of subnodes.
Each of these subnodes represents some desired configuration for a group of pins.

Required subnode-properties:
- sirf,pins : An array of strings. Each string contains the name of a group.
- sirf,function: A string containing the name of the function to mux to the
  group.

  Valid values for group and function names can be found from looking at the
  group and function arrays in driver files:
  drivers/pinctrl/pinctrl-sirf.c

For example, pinctrl might have subnodes like the following:
 uart2_pins_a: uart2@0 {
         uart {
                 sirf,pins = "uart2grp";
                 sirf,function = "uart2";
         };
 };
 uart2_noflow_pins_a: uart2@1 {
         uart {
                 sirf,pins = "uart2_nostreamctrlgrp";
                 sirf,function = "uart2_nostreamctrl";
         };
 };

For a specific board, if it wants to use uart2 without hardware flow control,
it can add the following to its board-specific .dts file.
uart2: uart@b0070000 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_noflow_pins_a>;
}


code:
*ST pin controller.

Each multi-function pin is controlled, driven and routed through the
PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
and multiple alternate functions(ALT1 - ALTx) that directly connect
the pin to different hardware blocks.

When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
Pull Up (PU) are driven by the related PIO block.

ST pinctrl driver controls PIO multiplexing block and also interacts with
gpio driver to configure a pin.

GPIO bank can have one of the two possible types of interrupt-wirings.

First type is via irqmux, single interrupt is used by multiple gpio banks. This
reduces number of overall interrupts numbers required. All these banks belong to
a single pincontroller.
		  _________
		 |	   |----> [gpio-bank (n)    ]
		 |	   |----> [gpio-bank (n + 1)]
	[irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
		 |	   |----> [gpio-bank (...  )]
		 |_________|----> [gpio-bank (n + 7)]

Second type has a dedicated interrupt per gpio bank.

	[irqN]----> [gpio-bank (n)]

Pin controller node:
Required properties:
- compatible	: should be "st,stih407-<pio-block>-pinctrl"
- st,syscfg		: Should be a phandle of the syscfg node.
- st,retime-pin-mask	: Should be mask to specify which pins can be retimed.
	If the property is not present, it is assumed that all the pins in the
	bank are capable of retiming. Retiming is mainly used to improve the
	IO timing margins of external synchronous interfaces.
- ranges : defines mapping between pin controller node (parent) to gpio-bank
  node (children).

Optional properties:
- interrupts	: Interrupt number of the irqmux. If the interrupt is shared
  with other gpio banks via irqmux.
  a irqline and gpio banks.
- reg		: irqmux memory resource. If irqmux is present.
- reg-names	: irqmux resource should be named as "irqmux".

GPIO controller/bank node.
Required properties:
- gpio-controller : Indicates this device is a GPIO controller
- #gpio-cells	  : Must be two.
     - First cell: specifies the pin number inside the controller
     - Second cell: specifies whether the pin is logically inverted.
       - 0 = active high
       - 1 = active low
- st,bank-name	  : Should be a name string for this bank as specified in
  datasheet.

Optional properties:
- interrupts	: Interrupt number for this gpio bank. If there is a dedicated
  interrupt wired up for this gpio bank.

- interrupt-controller : Indicates this device is a interrupt controller. GPIO
  bank can be an interrupt controller iff one of the interrupt type either via
irqmux or a dedicated interrupt per bank is specified.

- #interrupt-cells: the value of this property should be 2.
     - First Cell: represents the external gpio interrupt number local to the
       gpio interrupt space of the controller.
     - Second Cell: flags to identify the type of the interrupt
       - 1 = rising edge triggered
       - 2 = falling edge triggered
       - 3 = rising and falling edge triggered
       - 4 = high level triggered
       - 8 = low level triggered
for related macros look in:
include/dt-bindings/interrupt-controller/irq.h

Example:
	pin-controller-sbc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,stih407-sbc-pinctrl";
		st,syscfg = <&syscfg_sbc>;
		reg = <0x0961f080 0x4>;
		reg-names = "irqmux";
		interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
		interrupt-names = "irqmux";
		ranges = <0 0x09610000 0x6000>;

		pio0: gpio@9610000 {
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x0 0x100>;
			st,bank-name = "PIO0";
		};
		...
		pin-functions nodes follow...
	};

Contents of function subnode node:
----------------------
Required properties for pin configuration node:
- st,pins	: Child node with list of pins with configuration.

Below is the format of how each pin conf should look like.

<bank offset mux mode rt_type rt_delay rt_clk>

Every PIO is represented with 4-7 parameters depending on retime configuration.
Each parameter is explained as below.

-bank		: Should be bank phandle to which this PIO belongs.
-offset		: Offset in the PIO bank.
-mux		: Should be alternate function number associated this pin.
		Use same numbers from datasheet.
-mode		:pin configuration is selected from one of the below values.
		IN
		IN_PU
		OUT
		BIDIR
		BIDIR_PU

-rt_type	Retiming Configuration for the pin.
		Possible retime configuration are:

		-------		-------------
		value		args
		-------		-------------
		NICLK		<delay> <clk>
		ICLK_IO		<delay> <clk>
		BYPASS		<delay>
		DE_IO		<delay> <clk>
		SE_ICLK_IO	<delay> <clk>
		SE_NICLK_IO	<delay> <clk>

- delay	is retime delay in pico seconds as mentioned in data sheet.

- rt_clk	:clk to be use for retime.
		Possible values are:
		CLK_A
		CLK_B
		CLK_C
		CLK_D

Example of mmcclk pin which is a bi-direction pull pu with retime config
as non inverted clock retimed with CLK_B and delay of 0 pico seconds:

pin-controller {
	...
	mmc0 {
		pinctrl_mmc: mmc {
			st,pins {
				mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
				...
			};
		};
	...
	};
};

sdhci0:sdhci@fe810000{
	...
	interrupt-parent = <&pio3>;
	#interrupt-cells = <2>;
	interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
	interrupt-names = "card-detect";
	pinctrl-names = "default";
	pinctrl-0	= <&pinctrl_mmc>;
};


code:
VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller

These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc).

Required properties:
- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
	"wm8750-pinctrl" or "wm,wm8850-pinctrl"
- reg: Should contain the physical address of the module's registers.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and the
  second cell is used to specify optional parameters.
	bit 0 - active low

Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

Each pin configuration node lists the pin(s) to which it applies, and one or
more of the mux functions to select on those pin(s), and pull-up/down
configuration. Each subnode only affects those parameters that are explicitly
listed. In other words, a subnode that lists only a mux function implies no
information about any pull configuration. Similarly, a subnode that lists only
a pull parameter implies no information about the mux function.

Required subnode-properties:
- wm,pins: An array of cells. Each cell contains the ID of a pin.

Optional subnode-properties:
- wm,function: Integer, containing the function to mux to the pin(s):
  0: GPIO in
  1: GPIO out
  2: alternate

- wm,pull: Integer, representing the pull-down/up to apply to the pin(s):
  0: none
  1: down
  2: up

Each of wm,function and wm,pull may contain either a single value which
will be applied to all pins in wm,pins, or one value for each entry in
wm,pins.

Example:

	pinctrl: pinctrl {
		compatible = "wm,wm8505-pinctrl";
		reg = <0xD8110000 0x10000>;
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-controller;
		#gpio-cells = <2>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Pin controller device

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>
  - Rafał Miłecki <rafal@milecki.pl>

description: |
  Pin controller devices should contain the pin configuration nodes that client
  devices reference.

  The contents of each of those pin configuration child nodes is defined
  entirely by the binding for the individual pin controller device. There
  exists no common standard for this content. The pinctrl framework only
  provides generic helper bindings that the pin controller driver can use.

  The pin configuration nodes need not be direct children of the pin controller
  device; they may be grandchildren, for example. Whether this is legal, and
  whether there is any interaction between the child and intermediate parent
  nodes, is again defined entirely by the binding for the individual pin
  controller device.

properties:
  $nodename:
    pattern: "^(pinctrl|pinmux)(@[0-9a-f]+)?$"

  "#pinctrl-cells":
    description: >
      Number of pin control cells in addition to the index within the pin
      controller device instance.

  pinctrl-use-default:
    type: boolean
    description: >
      Indicates that the OS can use the boot default pin configuration. This
      allows using an OS that does not have a driver for the pin controller.
      This property can be set either globally for the pin controller or in
      child nodes for individual pin group control.

additionalProperties: true


code:
ST Microelectronics, SPEAr pinmux controller

Required properties:
- compatible	: "st,spear300-pinmux"
		: "st,spear310-pinmux"
		: "st,spear320-pinmux"
		: "st,spear1310-pinmux"
		: "st,spear1340-pinmux"
- reg		: Address range of the pinctrl registers
- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
	- Its values for SPEAr300:
		- NAND_MODE		: <0>
		- NOR_MODE		: <1>
		- PHOTO_FRAME_MODE	: <2>
		- LEND_IP_PHONE_MODE	: <3>
		- HEND_IP_PHONE_MODE	: <4>
		- LEND_WIFI_PHONE_MODE	: <5>
		- HEND_WIFI_PHONE_MODE	: <6>
		- ATA_PABX_WI2S_MODE	: <7>
		- ATA_PABX_I2S_MODE	: <8>
		- CAML_LCDW_MODE	: <9>
		- CAMU_LCD_MODE		: <10>
		- CAMU_WLCD_MODE	: <11>
		- CAML_LCD_MODE		: <12>
	- Its values for SPEAr320:
		- AUTO_NET_SMII_MODE	: <0>
		- AUTO_NET_MII_MODE	: <1>
		- AUTO_EXP_MODE		: <2>
		- SMALL_PRINTERS_MODE	: <3>
		- EXTENDED_MODE		: <4>

Please refer to pinctrl-bindings.txt in this directory for details of the common
pinctrl bindings used by client devices.

SPEAr's pinmux nodes act as a container for an arbitrary number of subnodes. Each
of these subnodes represents muxing for a pin, a group, or a list of pins or
groups.

The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.

Required subnode-properties:
- st,pins : An array of strings. Each string contains the name of a pin or
  group.
- st,function: A string containing the name of the function to mux to the pin or
  group. See the SPEAr's TRM to determine which are valid for each pin or group.

  Valid values for group and function names can be found from looking at the
  group and function arrays in driver files:
  drivers/pinctrl/spear/pinctrl-spear3*0.c

Valid values for group names are:
For All SPEAr3xx machines:
	"firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp",
	"gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp",
	"gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp",
	"timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp"

For SPEAr300 machines:
	"fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp",
	"clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp",
	"dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp",
	"gpio1_0_to_3_grp", "gpio1_4_to_7_grp"

For SPEAr310 machines:
	"emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp",
	"uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp"

For SPEAr320 machines:
	"clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp",
	"sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp",
	"uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp",
	"uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp",
	"uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp",
	"uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp",
	"uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp",
	"uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
	"uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp",
	"uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp",
	"uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp",
	"can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp",
	"pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp",
	"pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp",
	"pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp",
	"pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp",
	"pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp",
	"pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp",
	"ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp",
	"ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp",
	"ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp",
	"rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp",
	"i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp"

For SPEAr1310 machines:
	"i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp",
	"i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp",
	"smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp",
	"smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp",
	"nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp",
	"keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp",
	"gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp",
	"sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp",
	"uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp",
	"uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp",
	"i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp",
	"i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp",
	"i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp",
	"can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp",
	"pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp",
	"ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp"

For SPEAr1340 machines:
	"pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp",
	"keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp",
	"spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp",
	"pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp",
	"vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp",
	"cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp",
	"ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp",
	"uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp",
	"rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp",
	"sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp",
	"miphy_dbg_grp", "pcie_grp", "sata_grp"

Valid values for function names are:
For All SPEAr3xx machines:
	"firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext",
	"uart0", "timer_0_1", "timer_2_3"

For SPEAr300 machines:
	"fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1"

For SPEAr310 machines:
	"emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0",
	"rs485_1", "tdm"

For SPEAr320 machines:
	"clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem",
	"uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen",
	"can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
	"mii0_1", "i2c1", "i2c2"

For SPEAr1310 machines:
	"i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii",
	"rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0",
	"gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3",
	"uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1",
	"i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64"

For SPEAr1340 machines:
	"pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1",
	"pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0",
	"uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf",
	"xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata"


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Generic pin multiplexing node schema

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  The contents of the pin configuration child nodes are defined by the binding
  for the individual pin controller device. The pin configuration nodes need not
  be direct children of the pin controller device; they may be grandchildren,
  for example. Whether this is legal, and whether there is any interaction
  between the child and intermediate parent nodes, is again defined entirely by
  the binding for the individual pin controller device.

  While not required to be used, there are 3 generic forms of pin muxing nodes
  which pin controller devices can use.

  pin multiplexing nodes:

  Example:

  state_0_node_a {
    uart0 {
      function = "uart0";
      groups = "u0rxtx", "u0rtscts";
    };
  };
  state_1_node_a {
    spi0 {
      function = "spi0";
      groups = "spi0pins";
    };
  };
  state_2_node_a {
    function = "i2c0";
    pins = "mfio29", "mfio30";
  };

  Optionally an alternative binding can be used if more suitable depending on the
  pin controller hardware. For hardware where there is a large number of identical
  pin controller instances, naming each pin and function can easily become
  unmaintainable. This is especially the case if the same controller is used for
  different pins and functions depending on the SoC revision and packaging.

  For cases like this, the pin controller driver may use pinctrl-pin-array helper
  binding with a hardware based index and a number of pin configuration values:

  pincontroller {
    ... /* Standard DT properties for the device itself elided */
    #pinctrl-cells = <2>;

    state_0_node_a {
      pinctrl-pin-array = <
        0 A_DELAY_PS(0) G_DELAY_PS(120)
        4 A_DELAY_PS(0) G_DELAY_PS(360)
        ...
        >;
    };
    ...
  };

  Above #pinctrl-cells specifies the number of value cells in addition to the
  index of the registers. This is similar to the interrupts-extended binding with
  one exception. There is no need to specify the phandle for each entry as that
  is already known as the defined pins are always children of the pin controller
  node. Further having the phandle pointing to another pin controller would not
  currently work as the pinctrl framework uses named modes to group pins for each
  pin control device.

  The index for pinctrl-pin-array must relate to the hardware for the pinctrl
  registers, and must not be a virtual index of pin instances. The reason for
  this is to avoid mapping of the index in the dts files and the pin controller
  driver as it can change.

  For hardware where pin multiplexing configurations have to be specified for
  each single pin the number of required sub-nodes containing "pin" and
  "function" properties can quickly escalate and become hard to write and
  maintain.

  For cases like this, the pin controller driver may use the pinmux helper
  property, where the pin identifier is provided with mux configuration settings
  in a pinmux group. A pinmux group consists of the pin identifier and mux
  settings represented as a single integer or an array of integers.

  The pinmux property accepts an array of pinmux groups, each of them describing
  a single pin multiplexing configuration.

  pincontroller {
    state_0_node_a {
      pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
    };
  };

  Each individual pin controller driver bindings documentation shall specify
  how pin IDs and pin multiplexing configuration are defined and assembled
  together in a pinmux group.

properties:
  function:
    $ref: /schemas/types.yaml#/definitions/string
    description: The mux function to select

  pins:
    oneOf:
      - $ref: /schemas/types.yaml#/definitions/uint32-array
      - $ref: /schemas/types.yaml#/definitions/string-array
    description:
      The list of pin identifiers that properties in the node apply to. The
      specific binding for the hardware defines whether the entries are integers
      or strings, and their meaning.

  groups:
    $ref: /schemas/types.yaml#/definitions/string-array
    description:
      the group to apply the properties to, if the driver supports
      configuration of whole groups rather than individual pins (either
      this, "pins" or "pinmux" has to be specified)

  pinmux:
    description:
      The list of numeric pin ids and their mux settings that properties in the
      node apply to (either this, "pins" or "groups" have to be specified)
    $ref: /schemas/types.yaml#/definitions/uint32-array

  pinctrl-pin-array:
    $ref: /schemas/types.yaml#/definitions/uint32-array

additionalProperties: true


code:
Qualcomm APQ8064 TLMM block

Required properties:
- compatible: "qcom,apq8064-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
                The first cell is the gpio pin number and the
                second cell is used for optional parameters.
- gpio-ranges: see ../gpio/gpio.txt

Optional properties:

- gpio-reserved-ranges: see ../gpio/gpio.txt

Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

Qualcomm's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.

The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.

The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:

 pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength,
 output-low, output-high.

Non-empty subnodes must specify the 'pins' property.

Valid values for pins are:
  gpio0-gpio89

Valid values for function are:
  cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a,
  gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
  gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
  gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
  gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
  riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold

Example:

	msmgpio: pinctrl@800000 {
		compatible = "qcom,apq8064-pinctrl";
		reg = <0x800000 0x4000>;

		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <0 16 0x4>;

		pinctrl-names = "default";
		pinctrl-0 = <&gsbi5_uart_default>;
		gpio-ranges = <&msmgpio 0 0 90>;

		gsbi5_uart_default: gsbi5_uart_default {
			mux {
				pins = "gpio51", "gpio52";
				function = "gsbi5";
			};

			tx {
				pins = "gpio51";
				drive-strength = <4>;
				bias-disable;
			};

			rx {
				pins = "gpio52";
				drive-strength = <2>;
				bias-pull-up;
			};
		};
	};