code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.

%YAML 1.2
---
$id: http://devicetree.org/schemas/net/wireless/mediatek,mt76.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek mt76 wireless devices Generic Binding

maintainers:
  - Felix Fietkau <nbd@nbd.name>
  - Lorenzo Bianconi <lorenzo@kernel.org>
  - Ryder Lee <ryder.lee@mediatek.com>

description: |
  This node provides properties for configuring the MediaTek mt76xx
  wireless device. The node is expected to be specified as a child
  node of the PCI controller to which the wireless chip is connected.
  Alternatively, it can specify the wireless part of the MT7628/MT7688
  or MT7622/MT7986 SoC.

allOf:
  - $ref: ieee80211.yaml#

properties:
  compatible:
    enum:
      - mediatek,mt76
      - mediatek,mt7628-wmac
      - mediatek,mt7622-wmac
      - mediatek,mt7986-wmac

  reg:
    minItems: 1
    maxItems: 3
    description:
      MT7986 should contain 3 regions consys, dcm, and sku, in this order.

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  memory-region:
    maxItems: 1

  resets:
    maxItems: 1
    description:
      Specify the consys reset for mt7986.

  reset-names:
    const: consys

  clocks:
    maxItems: 2
    description:
      Specify the consys clocks for mt7986.

  clock-names:
    items:
      - const: mcu
      - const: ap2conn

  mediatek,infracfg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the infrastructure bus fabric syscon node.
      This property is MT7622 specific

  ieee80211-freq-limit: true

  mediatek,eeprom-data:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description:
      EEPROM data embedded as array.

  mediatek,mtd-eeprom:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to MTD partition
          - description: offset containing EEPROM data
    description:
      Phandle to a MTD partition + offset containing EEPROM data

  big-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Specify if the radio eeprom partition is written in big-endian

  mediatek,eeprom-merge-otp:
    type: boolean
    description:
      Merge EEPROM data with OTP data. Can be used on boards where the flash
      calibration data is generic and specific calibration data should be
      pulled from the OTP ROM

  mediatek,disable-radar-background:
    type: boolean
    description:
      Disable/enable radar/CAC detection running on a dedicated offchannel
      chain available on some hw.
      Background radar/CAC detection allows to avoid the CAC downtime
      switching on a different channel during CAC detection on the selected
      radar channel.

  led:
    type: object
    $ref: /schemas/leds/common.yaml#
    additionalProperties: false
    properties:
      led-sources:
        maxItems: 1

  power-limits:
    type: object
    additionalProperties: false
    patternProperties:
      "^r[0-9]+":
        type: object
        additionalProperties: false
        properties:
          regdomain:
            $ref: /schemas/types.yaml#/definitions/string
            description:
              Regdomain refers to a legal regulatory region. Different
              countries define different levels of allowable transmitter
              power, time that a channel can be occupied, and different
              available channels
            enum:
              - FCC
              - ETSI
              - JP

        patternProperties:
          "^txpower-[256]g$":
            type: object
            additionalProperties: false
            patternProperties:
              "^b[0-9]+$":
                type: object
                additionalProperties: false
                properties:
                  channels:
                    $ref: /schemas/types.yaml#/definitions/uint32-array
                    minItems: 2
                    maxItems: 2
                    description:
                      Pairs of first and last channel number of the selected
                      band

                  rates-cck:
                    $ref: /schemas/types.yaml#/definitions/uint8-array
                    minItems: 4
                    maxItems: 4
                    description:
                      4 half-dBm per-rate power limit values

                  rates-ofdm:
                    $ref: /schemas/types.yaml#/definitions/uint8-array
                    minItems: 8
                    maxItems: 8
                    description:
                      8 half-dBm per-rate power limit values

                  rates-mcs:
                    $ref: /schemas/types.yaml#/definitions/uint8-matrix
                    description:
                      Sets of per-rate power limit values for 802.11n/802.11ac
                      rates for multiple channel bandwidth settings.
                      Each set starts with the number of channel bandwidth
                      settings for which the rate set applies, followed by
                      either 8 or 10 power limit values. The order of the
                      channel bandwidth settings is 20, 40, 80 and 160 MHz.
                    maxItems: 4
                    items:
                      minItems: 9
                      maxItems: 11

                  rates-ru:
                    $ref: /schemas/types.yaml#/definitions/uint8-matrix
                    description:
                      Sets of per-rate power limit values for 802.11ax rates
                      for multiple channel bandwidth or resource unit settings.
                      Each set starts with the number of channel bandwidth or
                      resource unit settings for which the rate set applies,
                      followed by 12 power limit values. The order of the
                      channel resource unit settings is RU26, RU52, RU106,
                      RU242/SU20, RU484/SU40, RU996/SU80 and RU2x996/SU160.
                    items:
                      minItems: 13
                      maxItems: 13

                  txs-delta:
                    $ref: /schemas/types.yaml#/definitions/uint32-array
                    description:
                      Half-dBm power delta for different numbers of antennas

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    pcie0 {
      #address-cells = <3>;
      #size-cells = <2>;
      wifi@0,0 {
        compatible = "mediatek,mt76";
        reg = <0x0000 0 0 0 0>;
        ieee80211-freq-limit = <5000000 6000000>;
        mediatek,mtd-eeprom = <&factory 0x8000>;
        big-endian;

        led {
          led-sources = <2>;
        };

        power-limits {
          r0 {
            regdomain = "FCC";
            txpower-5g {
               b0 {
                   channels = <36 48>;
                   rates-ofdm = /bits/ 8 <23 23 23 23 23 23 23 23>;
                   rates-mcs = /bits/ 8 <1 23 23 23 23 23 23 23 23 23 23>,
                               /bits/ 8 <3 22 22 22 22 22 22 22 22 22 22>;
                   rates-ru = /bits/ 8 <3 22 22 22 22 22 22 22 22 22 22 22 22>,
                              /bits/ 8 <4 20 20 20 20 20 20 20 20 20 20 20 20>;
               };
               b1 {
                   channels = <100 181>;
                   rates-ofdm = /bits/ 8 <14 14 14 14 14 14 14 14>;
                   rates-mcs = /bits/ 8  <4 14 14 14 14 14 14 14 14 14 14>;
                   txs-delta = <12 9 6>;
                   rates-ru = /bits/ 8  <7 14 14 14 14 14 14 14 14 14 14 14 14>;
               };
             };
          };
        };
      };
    };

  - |
    wifi@10300000 {
      compatible = "mediatek,mt7628-wmac";
      reg = <0x10300000 0x100000>;

      interrupt-parent = <&cpuintc>;
      interrupts = <6>;

      mediatek,mtd-eeprom = <&factory 0x0>;
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    wifi@18000000 {
      compatible = "mediatek,mt7622-wmac";
      reg = <0x10300000 0x100000>;
      interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;

      mediatek,infracfg = <&infracfg>;

      power-domains = <&scpsys 3>;
    };

  - |
    wifi@18000000 {
        compatible = "mediatek,mt7986-wmac";
        resets = <&watchdog 23>;
        reset-names = "consys";
        reg = <0x18000000 0x1000000>,
              <0x10003000 0x1000>,
              <0x11d10000 0x1000>;
        interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&topckgen 50>,
                 <&topckgen 62>;
        clock-names = "mcu", "ap2conn";
        memory-region = <&wmcpu_emi>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/wireless/microchip,wilc1000.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip WILC wireless devicetree bindings

maintainers:
  - Adham Abozaeid <adham.abozaeid@microchip.com>
  - Ajay Singh <ajay.kathat@microchip.com>

description:
  The wilc1000 chips can be connected via SPI or SDIO. This document
  describes the binding to connect wilc devices.

properties:
  compatible:
    const: microchip,wilc1000

  reg: true

  interrupts:
    maxItems: 1

  clocks:
    description: phandle to the clock connected on rtc clock line.
    maxItems: 1

  clock-names:
    const: rtc

  enable-gpios:
    maxItems: 1
    description: Used by wilc1000-spi to determine the GPIO line
      connected to the ENABLE line.  If specified, reset-gpios
      must be specified as well as otherwise the driver cannot
      ensure the timing required between asserting ENABLE
      and deasserting RESET.  This should be declared as an
      active-high signal.

  reset-gpios:
    maxItems: 1
    description: Used by wilc1000-spi to determine the GPIO line
      connected to the RESET line.  This should be declared as an
      active-low signal.

required:
  - compatible
  - interrupts

allOf:
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    spi {
      #address-cells = <1>;
      #size-cells = <0>;
      wifi@0 {
        compatible = "microchip,wilc1000";
        spi-max-frequency = <48000000>;
        reg = <0>;
        interrupt-parent = <&pioC>;
        interrupts = <27 0>;
        clocks = <&pck1>;
        clock-names = "rtc";
        enable-gpios = <&pioA 5 GPIO_ACTIVE_HIGH>;
        reset-gpios = <&pioA 6 GPIO_ACTIVE_LOW>;
      };
    };

  - |
    mmc {
      #address-cells = <1>;
      #size-cells = <0>;
      pinctrl-names = "default";
      pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
      non-removable;
      vmmc-supply = <&vcc_mmc1_reg>;
      vqmmc-supply = <&vcc_3v3_reg>;
      bus-width = <4>;
      wifi@0 {
        compatible = "microchip,wilc1000";
        reg = <0>;
        interrupt-parent = <&pioC>;
        interrupts = <27 0>;
        clocks = <&pck1>;
        clock-names = "rtc";
      };
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/wireless/qca,ath9k.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Atheros ath9k wireless devices Generic Binding

maintainers:
  - Toke Høiland-Jørgensen <toke@toke.dk>

description: |
  This node provides properties for configuring the ath9k wireless device.
  The node is expected to be specified as a child node of the PCI controller
  to which the wireless chip is connected.

allOf:
  - $ref: ieee80211.yaml#

properties:
  compatible:
    enum:
      - pci168c,0023  # AR5416
      - pci168c,0024  # AR5418
      - pci168c,0027  # AR9160
      - pci168c,0029  # AR9220 and AR9223
      - pci168c,002a  # AR9280 and AR9283
      - pci168c,002b  # AR9285
      - pci168c,002c  # AR2427 - 802.11n bonded out
      - pci168c,002d  # AR9227
      - pci168c,002e  # AR9287
      - pci168c,0030  # AR9380, AR9381 and AR9382
      - pci168c,0032  # AR9485
      - pci168c,0033  # AR9580 and AR9590
      - pci168c,0034  # AR9462
      - pci168c,0036  # AR9565
      - pci168c,0037  # AR1111 and AR9485

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  ieee80211-freq-limit: true

  qca,no-eeprom:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Indicates that there is no physical EEPROM connected

  nvmem-cells:
    items:
      - description: Reference to an nvmem node for the MAC address
      - description: Reference to an nvmem node for calibration data

  nvmem-cell-names:
    items:
      - const: mac-address
      - const: calibration

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pcie0 {
      #address-cells = <3>;
      #size-cells = <2>;
      wifi@0,0 {
        compatible = "pci168c,002d";
        reg = <0 0 0 0 0>;
        interrupts = <3>;
        qca,no-eeprom;
      };
    };
  - |
    pci0 {
      #address-cells = <3>;
      #size-cells = <2>;
      wifi@0,11 {
        compatible = "pci168c,0029";
        reg = <0x8800 0 0 0 0>;
        nvmem-cells = <&macaddr_art_c>, <&cal_art_1000>;
        nvmem-cell-names = "mac-address", "calibration";
      };
    };


code:
* Qualcomm Atheros ath10k wireless devices

Required properties:
- compatible: Should be one of the following:
	* "qcom,ath10k"
	* "qcom,ipq4019-wifi"
	* "qcom,wcn3990-wifi"

PCI based devices uses compatible string "qcom,ath10k" and takes calibration
data along with board specific data via "qcom,ath10k-calibration-data".
Rest of the properties are not applicable for PCI based devices.

AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"
and also uses most of the properties defined in this doc (except
"qcom,ath10k-calibration-data"). It uses "qcom,ath10k-pre-calibration-data"
to carry pre calibration data.

In general, entry "qcom,ath10k-pre-calibration-data" and
"qcom,ath10k-calibration-data" conflict with each other and only one
can be provided per device.

SNOC based devices (i.e. wcn3990) uses compatible string "qcom,wcn3990-wifi".

- reg: Address and length of the register set for the device.
- reg-names: Must include the list of following reg names,
	     "membase"
- interrupts: reference to the list of 17 interrupt numbers for "qcom,ipq4019-wifi"
	      compatible target.
	      reference to the list of 12 interrupt numbers for "qcom,wcn3990-wifi"
	      compatible target.
	      Must contain interrupt-names property per entry for
	      "qcom,ath10k", "qcom,ipq4019-wifi" compatible targets.

- interrupt-names: Must include the entries for MSI interrupt
		   names ("msi0" to "msi15") and legacy interrupt
		   name ("legacy") for "qcom,ath10k", "qcom,ipq4019-wifi"
		   compatible targets.

Optional properties:
- resets: Must contain an entry for each entry in reset-names.
          See ../reset/reseti.txt for details.
- reset-names: Must include the list of following reset names,
	       "wifi_cpu_init"
	       "wifi_radio_srif"
	       "wifi_radio_warm"
	       "wifi_radio_cold"
	       "wifi_core_warm"
	       "wifi_core_cold"
- clocks: List of clock specifiers, must contain an entry for each required
          entry in clock-names.
- clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref",
	       "wifi_wcss_rtc" for "qcom,ipq4019-wifi" compatible target and
	       "cxo_ref_clk_pin" and optionally "qdss" for "qcom,wcn3990-wifi"
	       compatible target.
- qcom,msi_addr: MSI interrupt address.
- qcom,msi_base: Base value to add before writing MSI data into
		MSI address register.
- qcom,ath10k-calibration-variant: string to search for in the board-2.bin
				   variant list with the same bus and device
				   specific ids
- qcom,ath10k-calibration-data : calibration data + board specific data
				 as an array, the length can vary between
				 hw versions.
- qcom,ath10k-pre-calibration-data : pre calibration data as an array,
				     the length can vary between hw versions.
- <supply-name>-supply: handle to the regulator device tree node
			   optional "supply-name" are "vdd-0.8-cx-mx",
			   "vdd-1.8-xo", "vdd-1.3-rfa", "vdd-3.3-ch0",
			   and "vdd-3.3-ch1".
- memory-region:
	Usage: optional
	Value type: <phandle>
	Definition: reference to the reserved-memory for the msa region
		    used by the wifi firmware running in Q6.
- iommus:
	Usage: optional
	Value type: <prop-encoded-array>
	Definition: A list of phandle and IOMMU specifier pairs.
- ext-fem-name:
	Usage: Optional
	Value type: string
	Definition: Name of external front end module used. Some valid FEM names
		    for example: "microsemi-lx5586", "sky85703-11"
		    and "sky85803" etc.
- qcom,snoc-host-cap-8bit-quirk:
	Usage: Optional
	Value type: <empty>
	Definition: Quirk specifying that the firmware expects the 8bit version
		    of the host capability QMI request
- qcom,xo-cal-data: xo cal offset to be configured in xo trim register.

- qcom,msa-fixed-perm: Boolean context flag to disable SCM call for statically
		       mapped msa region.

- qcom,coexist-support : should contain eithr "0" or "1" to indicate coex
			 support by the hardware.
- qcom,coexist-gpio-pin : gpio pin number  information to support coex
			  which will be used by wifi firmware.

* Subnodes
The ath10k wifi node can contain one optional firmware subnode.
Firmware subnode is needed when the platform does not have TustZone.
The firmware subnode must have:

- iommus:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: A list of phandle and IOMMU specifier pairs.

Example (to supply PCI based wifi block details):

In this example, the node is defined as child node of the PCI controller.

pci {
	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";

		wifi@0,0 {
			reg = <0 0 0 0 0>;
			qcom,ath10k-calibration-data = [ 01 02 03 ... ];
			ext-fem-name = "microsemi-lx5586";
		};
	};
};

Example (to supply ipq4019 SoC wifi block details):

wifi0: wifi@a000000 {
	compatible = "qcom,ipq4019-wifi";
	reg = <0xa000000 0x200000>;
	resets = <&gcc WIFI0_CPU_INIT_RESET>,
		 <&gcc WIFI0_RADIO_SRIF_RESET>,
		 <&gcc WIFI0_RADIO_WARM_RESET>,
		 <&gcc WIFI0_RADIO_COLD_RESET>,
		 <&gcc WIFI0_CORE_WARM_RESET>,
		 <&gcc WIFI0_CORE_COLD_RESET>;
	reset-names = "wifi_cpu_init",
		      "wifi_radio_srif",
		      "wifi_radio_warm",
		      "wifi_radio_cold",
		      "wifi_core_warm",
		      "wifi_core_cold";
	clocks = <&gcc GCC_WCSS2G_CLK>,
		 <&gcc GCC_WCSS2G_REF_CLK>,
		 <&gcc GCC_WCSS2G_RTC_CLK>;
	clock-names = "wifi_wcss_cmd",
		      "wifi_wcss_ref",
		      "wifi_wcss_rtc";
	interrupts = <0 0x20 0x1>,
		     <0 0x21 0x1>,
		     <0 0x22 0x1>,
		     <0 0x23 0x1>,
		     <0 0x24 0x1>,
		     <0 0x25 0x1>,
		     <0 0x26 0x1>,
		     <0 0x27 0x1>,
		     <0 0x28 0x1>,
		     <0 0x29 0x1>,
		     <0 0x2a 0x1>,
		     <0 0x2b 0x1>,
		     <0 0x2c 0x1>,
		     <0 0x2d 0x1>,
		     <0 0x2e 0x1>,
		     <0 0x2f 0x1>,
		     <0 0xa8 0x0>;
	interrupt-names = "msi0",  "msi1",  "msi2",  "msi3",
			  "msi4",  "msi5",  "msi6",  "msi7",
			  "msi8",  "msi9",  "msi10", "msi11",
			  "msi12", "msi13", "msi14", "msi15",
			  "legacy";
	qcom,msi_addr = <0x0b006040>;
	qcom,msi_base = <0x40>;
	qcom,ath10k-pre-calibration-data = [ 01 02 03 ... ];
	qcom,coexist-support = <1>;
	qcom,coexist-gpio-pin = <0x33>;
};

Example (to supply wcn3990 SoC wifi block details):

wifi@18000000 {
		compatible = "qcom,wcn3990-wifi";
		reg = <0x18800000 0x800000>;
		reg-names = "membase";
		clocks = <&clock_gcc clk_rf_clk2_pin>;
		clock-names = "cxo_ref_clk_pin";
		interrupts =
			<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
		vdd-0.8-cx-mx-supply = <&pm8998_l5>;
		vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
		vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
		vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
		vdd-3.3-ch1-supply = <&vreg_l26a_3p3>;
		memory-region = <&wifi_msa_mem>;
		iommus = <&apps_smmu 0x0040 0x1>;
		qcom,msa-fixed-perm;
		wifi-firmware {
			iommus = <&apps_iommu 0xc22 0x1>;
		};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.

%YAML 1.2
---
$id: http://devicetree.org/schemas/net/wireless/qcom,ath11k.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies ath11k wireless devices Generic Binding

maintainers:
  - Kalle Valo <kvalo@kernel.org>

description: |
  These are dt entries for Qualcomm Technologies, Inc. IEEE 802.11ax
  devices, for example like AHB based IPQ8074.

properties:
  compatible:
    enum:
      - qcom,ipq8074-wifi
      - qcom,ipq6018-wifi
      - qcom,wcn6750-wifi

  reg:
    maxItems: 1

  interrupts:
    minItems: 32
    maxItems: 52

  interrupt-names:
    maxItems: 52

  qcom,rproc:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      DT entry of q6v5-wcss remoteproc driver.
      Phandle to a node that can contain the following properties
        * compatible
        * reg
        * reg-names

  qcom,ath11k-calibration-variant:
    $ref: /schemas/types.yaml#/definitions/string
    description:
      string to uniquely identify variant of the calibration data in the
      board-2.bin for designs with colliding bus and device specific ids

  memory-region:
    minItems: 1
    maxItems: 2
    description:
      phandle to a node describing reserved memory (System RAM memory)
      used by ath11k firmware (see bindings/reserved-memory/reserved-memory.txt)

  iommus:
    minItems: 1
    maxItems: 2

  wifi-firmware:
    type: object
    description: |
      WCN6750 wifi node can contain one optional firmware subnode.
      Firmware subnode is needed when the platform does not have Trustzone.
    required:
      - iommus

  qcom,smem-states:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: State bits used by the AP to signal the WLAN Q6.
    items:
      - description: Signal bits used to enable/disable low power mode
                     on WCN6750 in the case of WoW (Wake on Wireless).

  qcom,smem-state-names:
    description: The names of the state bits used for SMP2P output.
    items:
      - const: wlan-smp2p-out

required:
  - compatible
  - reg
  - interrupts
  - qcom,rproc

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq8074-wifi
              - qcom,ipq6018-wifi
    then:
      properties:
        interrupts:
          items:
            - description: misc-pulse1 interrupt events
            - description: misc-latch interrupt events
            - description: sw exception interrupt events
            - description: watchdog interrupt events
            - description: interrupt event for ring CE0
            - description: interrupt event for ring CE1
            - description: interrupt event for ring CE2
            - description: interrupt event for ring CE3
            - description: interrupt event for ring CE4
            - description: interrupt event for ring CE5
            - description: interrupt event for ring CE6
            - description: interrupt event for ring CE7
            - description: interrupt event for ring CE8
            - description: interrupt event for ring CE9
            - description: interrupt event for ring CE10
            - description: interrupt event for ring CE11
            - description: interrupt event for ring host2wbm-desc-feed
            - description: interrupt event for ring host2reo-re-injection
            - description: interrupt event for ring host2reo-command
            - description: interrupt event for ring host2rxdma-monitor-ring3
            - description: interrupt event for ring host2rxdma-monitor-ring2
            - description: interrupt event for ring host2rxdma-monitor-ring1
            - description: interrupt event for ring reo2ost-exception
            - description: interrupt event for ring wbm2host-rx-release
            - description: interrupt event for ring reo2host-status
            - description: interrupt event for ring reo2host-destination-ring4
            - description: interrupt event for ring reo2host-destination-ring3
            - description: interrupt event for ring reo2host-destination-ring2
            - description: interrupt event for ring reo2host-destination-ring1
            - description: interrupt event for ring rxdma2host-monitor-destination-mac3
            - description: interrupt event for ring rxdma2host-monitor-destination-mac2
            - description: interrupt event for ring rxdma2host-monitor-destination-mac1
            - description: interrupt event for ring ppdu-end-interrupts-mac3
            - description: interrupt event for ring ppdu-end-interrupts-mac2
            - description: interrupt event for ring ppdu-end-interrupts-mac1
            - description: interrupt event for ring rxdma2host-monitor-status-ring-mac3
            - description: interrupt event for ring rxdma2host-monitor-status-ring-mac2
            - description: interrupt event for ring rxdma2host-monitor-status-ring-mac1
            - description: interrupt event for ring host2rxdma-host-buf-ring-mac3
            - description: interrupt event for ring host2rxdma-host-buf-ring-mac2
            - description: interrupt event for ring host2rxdma-host-buf-ring-mac1
            - description: interrupt event for ring rxdma2host-destination-ring-mac3
            - description: interrupt event for ring rxdma2host-destination-ring-mac2
            - description: interrupt event for ring rxdma2host-destination-ring-mac1
            - description: interrupt event for ring host2tcl-input-ring4
            - description: interrupt event for ring host2tcl-input-ring3
            - description: interrupt event for ring host2tcl-input-ring2
            - description: interrupt event for ring host2tcl-input-ring1
            - description: interrupt event for ring wbm2host-tx-completions-ring3
            - description: interrupt event for ring wbm2host-tx-completions-ring2
            - description: interrupt event for ring wbm2host-tx-completions-ring1
            - description: interrupt event for ring tcl2host-status-ring
        interrupt-names:
          items:
            - const: misc-pulse1
            - const: misc-latch
            - const: sw-exception
            - const: watchdog
            - const: ce0
            - const: ce1
            - const: ce2
            - const: ce3
            - const: ce4
            - const: ce5
            - const: ce6
            - const: ce7
            - const: ce8
            - const: ce9
            - const: ce10
            - const: ce11
            - const: host2wbm-desc-feed
            - const: host2reo-re-injection
            - const: host2reo-command
            - const: host2rxdma-monitor-ring3
            - const: host2rxdma-monitor-ring2
            - const: host2rxdma-monitor-ring1
            - const: reo2ost-exception
            - const: wbm2host-rx-release
            - const: reo2host-status
            - const: reo2host-destination-ring4
            - const: reo2host-destination-ring3
            - const: reo2host-destination-ring2
            - const: reo2host-destination-ring1
            - const: rxdma2host-monitor-destination-mac3
            - const: rxdma2host-monitor-destination-mac2
            - const: rxdma2host-monitor-destination-mac1
            - const: ppdu-end-interrupts-mac3
            - const: ppdu-end-interrupts-mac2
            - const: ppdu-end-interrupts-mac1
            - const: rxdma2host-monitor-status-ring-mac3
            - const: rxdma2host-monitor-status-ring-mac2
            - const: rxdma2host-monitor-status-ring-mac1
            - const: host2rxdma-host-buf-ring-mac3
            - const: host2rxdma-host-buf-ring-mac2
            - const: host2rxdma-host-buf-ring-mac1
            - const: rxdma2host-destination-ring-mac3
            - const: rxdma2host-destination-ring-mac2
            - const: rxdma2host-destination-ring-mac1
            - const: host2tcl-input-ring4
            - const: host2tcl-input-ring3
            - const: host2tcl-input-ring2
            - const: host2tcl-input-ring1
            - const: wbm2host-tx-completions-ring3
            - const: wbm2host-tx-completions-ring2
            - const: wbm2host-tx-completions-ring1
            - const: tcl2host-status-ring

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq8074-wifi
              - qcom,ipq6018-wifi
    then:
      required:
        - interrupt-names

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,wcn6750-wifi
    then:
      properties:
        interrupts:
          items:
            - description: interrupt event for ring CE1
            - description: interrupt event for ring CE2
            - description: interrupt event for ring CE3
            - description: interrupt event for ring CE4
            - description: interrupt event for ring CE5
            - description: interrupt event for ring CE6
            - description: interrupt event for ring CE7
            - description: interrupt event for ring CE8
            - description: interrupt event for ring CE9
            - description: interrupt event for ring CE10
            - description: interrupt event for ring DP1
            - description: interrupt event for ring DP2
            - description: interrupt event for ring DP3
            - description: interrupt event for ring DP4
            - description: interrupt event for ring DP5
            - description: interrupt event for ring DP6
            - description: interrupt event for ring DP7
            - description: interrupt event for ring DP8
            - description: interrupt event for ring DP9
            - description: interrupt event for ring DP10
            - description: interrupt event for ring DP11
            - description: interrupt event for ring DP12
            - description: interrupt event for ring DP13
            - description: interrupt event for ring DP14
            - description: interrupt event for ring DP15
            - description: interrupt event for ring DP16
            - description: interrupt event for ring DP17
            - description: interrupt event for ring DP18
            - description: interrupt event for ring DP19
            - description: interrupt event for ring DP20
            - description: interrupt event for ring DP21
            - description: interrupt event for ring DP22

examples:
  - |

    q6v5_wcss: q6v5_wcss@CD00000 {
        compatible = "qcom,ipq8074-wcss-pil";
        reg = <0xCD00000 0x4040>,
              <0x4AB000 0x20>;
        reg-names = "qdsp6",
                    "rmb";
    };

    wifi0: wifi@c000000 {
        compatible = "qcom,ipq8074-wifi";
        reg = <0xc000000 0x2000000>;
        interrupts = <0 320 1>,
                     <0 319 1>,
                     <0 318 1>,
                     <0 317 1>,
                     <0 316 1>,
                     <0 315 1>,
                     <0 314 1>,
                     <0 311 1>,
                     <0 310 1>,
                     <0 411 1>,
                     <0 410 1>,
                     <0 40 1>,
                     <0 39 1>,
                     <0 302 1>,
                     <0 301 1>,
                     <0 37 1>,
                     <0 36 1>,
                     <0 296 1>,
                     <0 295 1>,
                     <0 294 1>,
                     <0 293 1>,
                     <0 292 1>,
                     <0 291 1>,
                     <0 290 1>,
                     <0 289 1>,
                     <0 288 1>,
                     <0 239 1>,
                     <0 236 1>,
                     <0 235 1>,
                     <0 234 1>,
                     <0 233 1>,
                     <0 232 1>,
                     <0 231 1>,
                     <0 230 1>,
                     <0 229 1>,
                     <0 228 1>,
                     <0 224 1>,
                     <0 223 1>,
                     <0 203 1>,
                     <0 183 1>,
                     <0 180 1>,
                     <0 179 1>,
                     <0 178 1>,
                     <0 177 1>,
                     <0 176 1>,
                     <0 163 1>,
                     <0 162 1>,
                     <0 160 1>,
                     <0 159 1>,
                     <0 158 1>,
                     <0 157 1>,
                     <0 156 1>;
        interrupt-names = "misc-pulse1",
                          "misc-latch",
                          "sw-exception",
                          "watchdog",
                          "ce0",
                          "ce1",
                          "ce2",
                          "ce3",
                          "ce4",
                          "ce5",
                          "ce6",
                          "ce7",
                          "ce8",
                          "ce9",
                          "ce10",
                          "ce11",
                          "host2wbm-desc-feed",
                          "host2reo-re-injection",
                          "host2reo-command",
                          "host2rxdma-monitor-ring3",
                          "host2rxdma-monitor-ring2",
                          "host2rxdma-monitor-ring1",
                          "reo2ost-exception",
                          "wbm2host-rx-release",
                          "reo2host-status",
                          "reo2host-destination-ring4",
                          "reo2host-destination-ring3",
                          "reo2host-destination-ring2",
                          "reo2host-destination-ring1",
                          "rxdma2host-monitor-destination-mac3",
                          "rxdma2host-monitor-destination-mac2",
                          "rxdma2host-monitor-destination-mac1",
                          "ppdu-end-interrupts-mac3",
                          "ppdu-end-interrupts-mac2",
                          "ppdu-end-interrupts-mac1",
                          "rxdma2host-monitor-status-ring-mac3",
                          "rxdma2host-monitor-status-ring-mac2",
                          "rxdma2host-monitor-status-ring-mac1",
                          "host2rxdma-host-buf-ring-mac3",
                          "host2rxdma-host-buf-ring-mac2",
                          "host2rxdma-host-buf-ring-mac1",
                          "rxdma2host-destination-ring-mac3",
                          "rxdma2host-destination-ring-mac2",
                          "rxdma2host-destination-ring-mac1",
                          "host2tcl-input-ring4",
                          "host2tcl-input-ring3",
                          "host2tcl-input-ring2",
                          "host2tcl-input-ring1",
                          "wbm2host-tx-completions-ring3",
                          "wbm2host-tx-completions-ring2",
                          "wbm2host-tx-completions-ring1",
                          "tcl2host-status-ring";
        qcom,rproc = <&q6v5_wcss>;
    };

  - |

    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;

        qcn9074_0: qcn9074_0@51100000 {
            no-map;
            reg = <0x0 0x51100000 0x0 0x03500000>;
        };
    };

    pci {
        pcie0 {
            #size-cells = <2>;
            #address-cells = <3>;

            wifi_0: wifi@0 {
                reg = <0 0 0 0 0>;
                memory-region = <&qcn9074_0>;
            };
        };
    };

  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;

        wlan_ce_mem: memory@4cd000 {
            no-map;
            reg = <0x0 0x004cd000 0x0 0x1000>;
        };

        wlan_fw_mem: memory@80c00000 {
            no-map;
            reg = <0x0 0x80c00000 0x0 0xc00000>;
        };
    };

    wifi: wifi@17a10040 {
        compatible = "qcom,wcn6750-wifi";
        reg = <0x17a10040 0x0>;
        iommus = <&apps_smmu 0x1c00 0x1>;
        interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
        qcom,rproc = <&remoteproc_wpss>;
        memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
        qcom,smem-states = <&wlan_smp2p_out 0>;
        qcom,smem-state-names = "wlan-smp2p-out";
        wifi-firmware {
                iommus = <&apps_smmu 0x1c02 0x1>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020, Silicon Laboratories, Inc.
%YAML 1.2
---

$id: http://devicetree.org/schemas/net/wireless/silabs,wfx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Silicon Labs WFxxx devicetree bindings

maintainers:
  - Jérôme Pouiller <jerome.pouiller@silabs.com>

description: >
  Support for the Wifi chip WFxxx from Silicon Labs. Currently, the only device
  from the WFxxx series is the WF200 described here:
     https://www.silabs.com/documents/public/data-sheets/wf200-datasheet.pdf

  The WF200 can be connected via SPI or via SDIO.

  For SDIO:

    Declaring the WFxxx chip in device tree is mandatory (usually, the VID/PID is
    sufficient for the SDIO devices).

    It is recommended to declare a mmc-pwrseq on SDIO host above WFx. Without
    it, you may encounter issues during reboot. The mmc-pwrseq should be
    compatible with mmc-pwrseq-simple. Please consult
    Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml for more
    information.

properties:
  compatible:
    items:
      - enum:
          - prt,prtt1c-wfm200 # Protonic PRTT1C Board
          - silabs,brd4001a # WGM160P Evaluation Board
          - silabs,brd8022a # WF200 Evaluation Board
          - silabs,brd8023a # WFM200 Evaluation Board
      - const: silabs,wf200 # Chip alone without antenna

  reg:
    description:
      When used on SDIO bus, <reg> must be set to 1. When used on SPI bus, it is
      the chip select address of the device as defined in the SPI devices
      bindings.
    maxItems: 1

  interrupts:
    description: The interrupt line. Should be IRQ_TYPE_EDGE_RISING. When SPI is
      used, this property is required. When SDIO is used, the "in-band"
      interrupt provided by the SDIO bus is used unless an interrupt is defined
      in the Device Tree.
    maxItems: 1

  reset-gpios:
    description: (SPI only) Phandle of gpio that will be used to reset chip
      during probe. Without this property, you may encounter issues with warm
      boot.

      For SDIO, the reset gpio should declared using a mmc-pwrseq.
    maxItems: 1

  wakeup-gpios:
    description: Phandle of gpio that will be used to wake-up chip. Without this
      property, driver will disable most of power saving features.
    maxItems: 1

  silabs,antenna-config-file:
    $ref: /schemas/types.yaml#/definitions/string
    description: Use an alternative file for antenna configuration (aka
      "Platform Data Set" in Silabs jargon). Default depends of "compatible"
      string. For "silabs,wf200", the default is 'wf200.pds'.

  local-mac-address: true

  mac-address: true

required:
  - compatible
  - reg

allOf:
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        wifi@0 {
            compatible = "silabs,brd8022a", "silabs,wf200";
            pinctrl-names = "default";
            pinctrl-0 = <&wfx_irq &wfx_gpios>;
            reg = <0>;
            interrupts-extended = <&gpio 16 IRQ_TYPE_EDGE_RISING>;
            wakeup-gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
            reset-gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
            spi-max-frequency = <42000000>;
        };
    };

  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    wfx_pwrseq: wfx_pwrseq {
        compatible = "mmc-pwrseq-simple";
        pinctrl-names = "default";
        pinctrl-0 = <&wfx_reset>;
        reset-gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
    };

    mmc {
        mmc-pwrseq = <&wfx_pwrseq>;
        #address-cells = <1>;
        #size-cells = <0>;

        wifi@1 {
            compatible = "silabs,brd8022a", "silabs,wf200";
            pinctrl-names = "default";
            pinctrl-0 = <&wfx_wakeup>;
            reg = <1>;
            wakeup-gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
        };
    };
...


code:
* Texas Instruments wl1251 wireless lan controller

The wl1251 chip can be connected via SPI or via SDIO. This
document describes the binding for the SPI connected chip.

Required properties:
- compatible :        Should be "ti,wl1251"
- reg :               Chip select address of device
- spi-max-frequency : Maximum SPI clocking speed of device in Hz
- interrupts :        Should contain interrupt line
- vio-supply :        phandle to regulator providing VIO

Optional properties:
- ti,wl1251-has-eeprom : boolean, the wl1251 has an eeprom connected, which
                         provides configuration data (calibration, MAC, ...)
- ti,power-gpio :	 GPIO connected to chip's PMEN pin if operated in
			 SPI mode
- Please consult Documentation/devicetree/bindings/spi/spi-bus.txt
  for optional SPI connection related properties,

Examples:

&spi1 {
	wl1251@0 {
		compatible = "ti,wl1251";

		reg = <0>;
		spi-max-frequency = <48000000>;
		spi-cpol;
		spi-cpha;

		interrupt-parent = <&gpio2>;
		interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */

		vio-supply = <&vio>;
		ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */
	};
};

&mmc3 {
	vmmc-supply = <&wlan_en>;

	bus-width = <4>;
	non-removable;
	ti,non-removable;
	cap-power-off-card;

	pinctrl-names = "default";
	pinctrl-0 = <&mmc3_pins>;

	#address-cells = <1>;
	#size-cells = <0>;

	wlan: wifi@1 {
		compatible = "ti,wl1251";

		reg = <1>;

		interrupt-parent = <&gpio1>;
		interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;	/* GPIO_21 */

		ti,wl1251-has-eeprom;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/wireless/ti,wlcore.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments Wilink 6/7/8 (wl12xx/wl18xx) Wireless LAN Controller

maintainers:
  - Tony Lindgren <tony@atomide.com>

description:
  The wl12xx/wl18xx chips can be connected via SPI or via SDIO.
  Note that the *-clock-frequency properties assume internal clocks.  In case
  of external clocks, new bindings (for parsing the clock nodes) have to be
  added.

properties:
  compatible:
    enum:
      - ti,wl1271
      - ti,wl1273
      - ti,wl1281
      - ti,wl1283
      - ti,wl1285
      - ti,wl1801
      - ti,wl1805
      - ti,wl1807
      - ti,wl1831
      - ti,wl1835
      - ti,wl1837

  reg:
    maxItems: 1
    description:
      This is required when connected via SPI, and optional when connected via
      SDIO.

  interrupts:
    minItems: 1
    maxItems: 2

  interrupt-names:
    items:
      - const: irq
      - const: wakeup

  vwlan-supply:
    description:
      Points to the node of the regulator that powers/enable the wl12xx/wl18xx
      chip.  This is required when connected via SPI.

  ref-clock-frequency:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Reference clock frequency.

  tcxo-clock-frequency:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: TCXO clock frequency.

  clock-xtal:
    $ref: /schemas/types.yaml#/definitions/flag
    description: Indicates that the clock is generated from XTAL.

required:
  - compatible
  - interrupts

allOf:
  - $ref: /schemas/spi/spi-peripheral-props.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - ti,wl1271
              - ti,wl1273
              - ti,wl1281
              - ti,wl1283
    then:
      required:
        - ref-clock-frequency

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    // For wl12xx family:
    spi1 {
            #address-cells = <1>;
            #size-cells = <0>;

            wlcore1: wlcore@1 {
                    compatible = "ti,wl1271";
                    reg = <1>;
                    spi-max-frequency = <48000000>;
                    interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
                    vwlan-supply = <&vwlan_fixed>;
                    clock-xtal;
                    ref-clock-frequency = <38400000>;
            };
    };

    // For wl18xx family:
    spi2 {
            #address-cells = <1>;
            #size-cells = <0>;

            wlcore2: wlcore@0 {
                    compatible = "ti,wl1835";
                    reg = <0>;
                    spi-max-frequency = <48000000>;
                    interrupts = <27 IRQ_TYPE_EDGE_RISING>;
                    vwlan-supply = <&vwlan_fixed>;
            };
    };

    // SDIO example:
    mmc3 {
            vmmc-supply = <&wlan_en_reg>;
            bus-width = <4>;
            cap-power-off-card;
            keep-power-in-suspend;

            #address-cells = <1>;
            #size-cells = <0>;

            wlcore3: wlcore@2 {
                    compatible = "ti,wl1835";
                    reg = <2>;
                    interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
            };
    };


code:
* Wiznet w5x00

This is a standalone 10/100 MBit Ethernet controller with SPI interface.

For each device connected to a SPI bus, define a child node within
the SPI master node.

Required properties:
- compatible: Should be one of the following strings:
	      "wiznet,w5100"
	      "wiznet,w5200"
	      "wiznet,w5500"
- reg: Specify the SPI chip select the chip is wired to.
- interrupts: Specify the interrupt index within the interrupt controller (referred
              to above in interrupt-parent) and interrupt type. w5x00 natively
              generates falling edge interrupts, however, additional board logic
              might invert the signal.
- pinctrl-names: List of assigned state names, see pinctrl binding documentation.
- pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
             see also generic and your platform specific pinctrl binding
             documentation.

Optional properties:
- spi-max-frequency: Maximum frequency of the SPI bus when accessing the w5500.
  According to the w5500 datasheet, the chip allows a maximum of 80 MHz, however,
  board designs may need to limit this value.
- local-mac-address: See ethernet.txt in the same directory.

Example (for Raspberry Pi with pin control stuff for GPIO irq):

&spi {
	ethernet@0: w5500@0 {
		compatible = "wiznet,w5500";
		reg = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&eth1_pins>;
		interrupt-parent = <&gpio>;
		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
		spi-max-frequency = <30000000>;
	};
};

&gpio {
	eth1_pins: eth1_pins {
		brcm,pins = <25>;
		brcm,function = <0>; /* in */
		brcm,pull = <0>; /* none */
	};
};


code:
XILINX AXI ETHERNET Device Tree Bindings
--------------------------------------------------------

Also called  AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
provides connectivity to an external ethernet PHY supporting different
interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
segments of memory for buffering TX and RX, as well as the capability of
offloading TX/RX checksum calculation off the processor.

Management configuration is done through the AXI interface, while payload is
sent and received through means of an AXI DMA controller. This driver
includes the DMA driver code, so this driver is incompatible with AXI DMA
driver.

For more details about mdio please refer phy.txt file in the same directory.

Required properties:
- compatible	: Must be one of "xlnx,axi-ethernet-1.00.a",
		  "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
- reg		: Address and length of the IO space, as well as the address
                  and length of the AXI DMA controller IO space, unless
                  axistream-connected is specified, in which case the reg
                  attribute of the node referenced by it is used.
- interrupts	: Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
		  and optionally Ethernet core. If axistream-connected is
		  specified, the TX/RX DMA interrupts should be on that node
		  instead, and only the Ethernet core interrupt is optionally
		  specified here.
- phy-handle	: Should point to the external phy device if exists. Pointing
		  this to the PCS/PMA PHY is deprecated and should be avoided.
		  See ethernet.txt file in the same directory.
- xlnx,rxmem	: Set to allocated memory buffer for Rx/Tx in the hardware

Optional properties:
- phy-mode	: See ethernet.txt
- xlnx,phy-type	: Deprecated, do not use, but still accepted in preference
		  to phy-mode.
- xlnx,txcsum	: 0 or empty for disabling TX checksum offload,
		  1 to enable partial TX checksum offload,
		  2 to enable full TX checksum offload
- xlnx,rxcsum	: Same values as xlnx,txcsum but for RX checksum offload
- xlnx,switch-x-sgmii : Boolean to indicate the Ethernet core is configured to
		  support both 1000BaseX and SGMII modes. If set, the phy-mode
		  should be set to match the mode selected on core reset (i.e.
		  by the basex_or_sgmii core input line).
- clock-names: 	  Tuple listing input clock names. Possible clocks:
		  s_axi_lite_clk: Clock for AXI register slave interface
		  axis_clk: AXI4-Stream clock for TXD RXD TXC and RXS interfaces
		  ref_clk: Ethernet reference clock, used by signal delay
			   primitives and transceivers
		  mgt_clk: MGT reference clock (used by optional internal
			   PCS/PMA PHY)

		  Note that if s_axi_lite_clk is not specified by name, the
		  first clock of any name is used for this. If that is also not
		  specified, the clock rate is auto-detected from the CPU clock
		  (but only on platforms where this is possible). New device
		  trees should specify all applicable clocks by name - the
		  fallbacks to an unnamed clock or to CPU clock are only for
		  backward compatibility.
- clocks: 	  Phandles to input clocks matching clock-names. Refer to common
		  clock bindings.
- axistream-connected: Reference to another node which contains the resources
		       for the AXI DMA controller used by this device.
		       If this is specified, the DMA-related resources from that
		       device (DMA registers and DMA TX/RX interrupts) rather
		       than this one will be used.
 - mdio		: Child node for MDIO bus. Must be defined if PHY access is
		  required through the core's MDIO interface (i.e. always,
		  unless the PHY is accessed through a different bus).
		  Non-standard MDIO bus frequency is supported via
		  "clock-frequency", see mdio.yaml.

 - pcs-handle: 	  Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
		  modes, where "pcs-handle" should be used to point
		  to the PCS/PMA PHY, and "phy-handle" should point to an
		  external PHY if exists.

Example:
	axi_ethernet_eth: ethernet@40c00000 {
		compatible = "xlnx,axi-ethernet-1.00.a";
		device_type = "network";
		interrupt-parent = <&microblaze_0_axi_intc>;
		interrupts = <2 0 1>;
		clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
		clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
		phy-mode = "mii";
		reg = <0x40c00000 0x40000 0x50c00000 0x40000>;
		xlnx,rxcsum = <0x2>;
		xlnx,rxmem = <0x800>;
		xlnx,txcsum = <0x2>;
		phy-handle = <&phy0>;
		axi_ethernetlite_0_mdio: mdio {
			#address-cells = <1>;
			#size-cells = <0>;
			phy0: phy@0 {
				device_type = "ethernet-phy";
				reg = <1>;
			};
		};
	};


code:
XILINX GMIITORGMII Converter Driver Device Tree Bindings
--------------------------------------------------------

The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media
Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
Ethernet physical media devices (PHY) and the Gigabit Ethernet controller.
This core can be used in all three modes of operation(10/100/1000 Mb/s).
The Management Data Input/Output (MDIO) interface is used to configure the
Speed of operation. This core can switch dynamically between the three
Different speed modes by configuring the conveter register through mdio write.

This converter sits between the ethernet MAC and the external phy.
MAC <==> GMII2RGMII <==> RGMII_PHY

For more details about mdio please refer phy.txt file in the same directory.

Required properties:
- compatible	: Should be "xlnx,gmii-to-rgmii-1.0"
- reg		: The ID number for the phy, usually a small integer
- phy-handle	: Should point to the external phy device.
		  See ethernet.txt file in the same directory.

Example:
	mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		phy: ethernet-phy@0 {
			......
		};
		gmiitorgmii: gmiitorgmii@8 {
			compatible = "xlnx,gmii-to-rgmii-1.0";
			reg = <8>;
			phy-handle = <&phy>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/xlnx,emaclite.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Emaclite Ethernet controller

maintainers:
  - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
  - Harini Katakam <harini.katakam@amd.com>

allOf:
  - $ref: ethernet-controller.yaml#

properties:
  compatible:
    enum:
      - xlnx,opb-ethernetlite-1.01.a
      - xlnx,opb-ethernetlite-1.01.b
      - xlnx,xps-ethernetlite-1.00.a
      - xlnx,xps-ethernetlite-2.00.a
      - xlnx,xps-ethernetlite-2.01.a
      - xlnx,xps-ethernetlite-3.00.a

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  phy-handle: true

  local-mac-address: true

  xlnx,tx-ping-pong:
    type: boolean
    description: hardware supports tx ping pong buffer.

  xlnx,rx-ping-pong:
    type: boolean
    description: hardware supports rx ping pong buffer.

required:
  - compatible
  - reg
  - interrupts
  - phy-handle

additionalProperties: false

examples:
  - |
    axi_ethernetlite_1: ethernet@40e00000 {
        compatible = "xlnx,xps-ethernetlite-3.00.a";
        reg = <0x40e00000 0x10000>;
        interrupt-parent = <&axi_intc_1>;
        interrupts = <1>;
        local-mac-address = [00 00 00 00 00 00];
        phy-handle = <&phy0>;
        xlnx,rx-ping-pong;
        xlnx,tx-ping-pong;
    };


code:
* Nios II Processor Binding

This binding specifies what properties available in the device tree
representation of a Nios II Processor Core.

Users can use sopc2dts tool for generating device tree sources (dts) from a
Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts

Required properties:

- compatible: Compatible property value should be "altr,nios2-1.0".
- reg: Contains CPU index.
- interrupt-controller: Specifies that the node is an interrupt controller
- #interrupt-cells: Specifies the number of cells needed to encode an
		interrupt source, should be 1.
- clock-frequency: Contains the clock frequency for CPU, in Hz.
- dcache-line-size: Contains data cache line size.
- icache-line-size: Contains instruction line size.
- dcache-size: Contains data cache size.
- icache-size: Contains instruction cache size.
- altr,pid-num-bits: Specifies the number of bits to use to represent the process
		identifier (PID).
- altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB.
- altr,tlb-num-entries: Specifies the number of entries in the TLB.
- altr,tlb-ptr-sz: Specifies size of TLB pointer.
- altr,has-mul: Specifies CPU hardware multipy support, should be 1.
- altr,has-mmu: Specifies CPU support MMU support, should be 1.
- altr,has-initda: Specifies CPU support initda instruction, should be 1.
- altr,reset-addr: Specifies CPU reset address
- altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address
- altr,exception-addr: Specifies CPU exception address

Optional properties:
- altr,has-div: Specifies CPU hardware divide support
- altr,implementation: Nios II core implementation, this should be "fast";

Example:

cpu@0 {
	device_type = "cpu";
	compatible = "altr,nios2-1.0";
	reg = <0>;
	interrupt-controller;
	#interrupt-cells = <1>;
	clock-frequency = <125000000>;
	dcache-line-size = <32>;
	icache-line-size = <32>;
	dcache-size = <32768>;
	icache-size = <32768>;
	altr,implementation = "fast";
	altr,pid-num-bits = <8>;
	altr,tlb-num-ways = <16>;
	altr,tlb-num-entries = <128>;
	altr,tlb-ptr-sz = <7>;
	altr,has-div = <1>;
	altr,has-mul = <1>;
	altr,reset-addr = <0xc2800000>;
	altr,fast-tlb-miss-addr = <0xc7fff400>;
	altr,exception-addr = <0xd0000020>;
	altr,has-initda = <1>;
	altr,has-mmu = <1>;
};


code:
==============================================================================
NUMA binding description.
==============================================================================

==============================================================================
1 - Introduction
==============================================================================

Systems employing a Non Uniform Memory Access (NUMA) architecture contain
collections of hardware resources including processors, memory, and I/O buses,
that comprise what is commonly known as a NUMA node.
Processor accesses to memory within the local NUMA node is generally faster
than processor accesses to memory outside of the local NUMA node.
DT defines interfaces that allow the platform to convey NUMA node
topology information to OS.

==============================================================================
2 - numa-node-id
==============================================================================

For the purpose of identification, each NUMA node is associated with a unique
token known as a node id. For the purpose of this binding
a node id is a 32-bit integer.

A device node is associated with a NUMA node by the presence of a
numa-node-id property which contains the node id of the device.

Example:
	/* numa node 0 */
	numa-node-id = <0>;

	/* numa node 1 */
	numa-node-id = <1>;

==============================================================================
3 - distance-map
==============================================================================

The optional device tree node distance-map describes the relative
distance (memory latency) between all numa nodes.

- compatible : Should at least contain "numa-distance-map-v1".

- distance-matrix
  This property defines a matrix to describe the relative distances
  between all numa nodes.
  It is represented as a list of node pairs and their relative distance.

  Note:
	1. Each entry represents distance from first node to second node.
	The distances are equal in either direction.
	2. The distance from a node to self (local distance) is represented
	with value 10 and all internode distance should be represented with
	a value greater than 10.
	3. distance-matrix should have entries in lexicographical ascending
	order of nodes.
	4. There must be only one device node distance-map which must
	reside in the root node.
	5. If the distance-map node is not present, a default
	distance-matrix is used.

Example:
	4 nodes connected in mesh/ring topology as below,

		0_______20______1
		|               |
		|               |
		20             20
		|               |
		|               |
		|_______________|
		3       20      2

	if relative distance for each hop is 20,
	then internode distance would be,
	      0 -> 1 = 20
	      1 -> 2 = 20
	      2 -> 3 = 20
	      3 -> 0 = 20
	      0 -> 2 = 40
	      1 -> 3 = 40

     and dt presentation for this distance matrix is,

		distance-map {
			 compatible = "numa-distance-map-v1";
			 distance-matrix = <0 0  10>,
					   <0 1  20>,
					   <0 2  40>,
					   <0 3  20>,
					   <1 0  20>,
					   <1 1  10>,
					   <1 2  20>,
					   <1 3  40>,
					   <2 0  40>,
					   <2 1  20>,
					   <2 2  10>,
					   <2 3  20>,
					   <3 0  20>,
					   <3 1  40>,
					   <3 2  20>,
					   <3 3  10>;
		};

==============================================================================
4 - Empty memory nodes
==============================================================================

Empty memory nodes, which no memory resides in, are allowed. There are no
device nodes for these empty memory nodes. However, the NUMA node IDs and
distance maps are still valid and memory may be added into them through
hotplug afterwards.

Example:

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
		numa-node-id = <0>;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x80000000>;
		numa-node-id = <1>;
	};

	/* Empty memory node 2 and 3 */
	distance-map {
		compatible = "numa-distance-map-v1";
		distance-matrix = <0 0  10>,
				  <0 1  20>,
				  <0 2  40>,
				  <0 3  20>,
				  <1 0  20>,
				  <1 1  10>,
				  <1 2  20>,
				  <1 3  40>,
				  <2 0  40>,
				  <2 1  20>,
				  <2 2  10>,
				  <2 3  20>,
				  <3 0  20>,
				  <3 1  40>,
				  <3 2  20>,
				  <3 3  10>;
	};

==============================================================================
5 - Example dts
==============================================================================

Dual socket system consists of 2 boards connected through ccn bus and
each board having one socket/soc of 8 cpus, memory and pci bus.

	memory@c00000 {
		device_type = "memory";
		reg = <0x0 0xc00000 0x0 0x80000000>;
		/* node 0 */
		numa-node-id = <0>;
	};

	memory@10000000000 {
		device_type = "memory";
		reg = <0x100 0x0 0x0 0x80000000>;
		/* node 1 */
		numa-node-id = <1>;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			/* node 0 */
			numa-node-id = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
			numa-node-id = <0>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0x2>;
			enable-method = "psci";
			numa-node-id = <0>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0x3>;
			enable-method = "psci";
			numa-node-id = <0>;
		};
		cpu@4 {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0x4>;
			enable-method = "psci";
			numa-node-id = <0>;
		};
		cpu@5 {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0x5>;
			enable-method = "psci";
			numa-node-id = <0>;
		};
		cpu@6 {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0x6>;
			enable-method = "psci";
			numa-node-id = <0>;
		};
		cpu@7 {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0x7>;
			enable-method = "psci";
			numa-node-id = <0>;
		};
		cpu@8 {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0x8>;
			enable-method = "psci";
			/* node 1 */
			numa-node-id = <1>;
		};
		cpu@9 {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0x9>;
			enable-method = "psci";
			numa-node-id = <1>;
		};
		cpu@a {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0xa>;
			enable-method = "psci";
			numa-node-id = <1>;
		};
		cpu@b {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0xb>;
			enable-method = "psci";
			numa-node-id = <1>;
		};
		cpu@c {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0xc>;
			enable-method = "psci";
			numa-node-id = <1>;
		};
		cpu@d {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0xd>;
			enable-method = "psci";
			numa-node-id = <1>;
		};
		cpu@e {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0xe>;
			enable-method = "psci";
			numa-node-id = <1>;
		};
		cpu@f {
			device_type = "cpu";
			compatible =  "arm,armv8";
			reg = <0x0 0xf>;
			enable-method = "psci";
			numa-node-id = <1>;
		};
	};

	pcie0: pcie0@848000000000 {
		compatible = "arm,armv8";
		device_type = "pci";
		bus-range = <0 255>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0x8480 0x00000000 0 0x10000000>;  /* Configuration space */
		ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>;
		/* node 0 */
		numa-node-id = <0>;
        };

	pcie1: pcie1@948000000000 {
		compatible = "arm,armv8";
		device_type = "pci";
		bus-range = <0 255>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0x9480 0x00000000 0 0x10000000>;  /* Configuration space */
		ranges = <0x03000000 0x9010 0x00000000 0x9010 0x00000000 0x70 0x00000000>;
		/* node 1 */
		numa-node-id = <1>;
        };

	distance-map {
		compatible = "numa-distance-map-v1";
		distance-matrix = <0 0 10>,
				  <0 1 20>,
				  <1 1 10>;
	};


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvme/apple,nvme-ans.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple ANS NVM Express host controller

maintainers:
  - Sven Peter <sven@svenpeter.dev>

properties:
  compatible:
    items:
      - enum:
          - apple,t8103-nvme-ans2
          - apple,t6000-nvme-ans2
      - const: apple,nvme-ans2

  reg:
    items:
      - description: NVMe and NVMMU registers
      - description: ANS2 co-processor control registers

  reg-names:
    items:
      - const: nvme
      - const: ans

  resets:
    maxItems: 1

  power-domains:
    # two domains for t8103, three for t6000
    minItems: 2
    items:
      - description: power domain for the NVMe controller.
      - description: power domain for the first PCIe bus connecting the NVMe
          controller to the storage modules.
      - description: optional power domain for the second PCIe bus
          connecting the NVMe controller to the storage modules.

  power-domain-names:
    minItems: 2
    items:
      - const: ans
      - const: apcie0
      - const: apcie1

  mboxes:
    maxItems: 1
    description: Mailbox of the ANS2 co-processor

  interrupts:
    maxItems: 1

  apple,sart:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      Reference to the SART address filter.

      The SART address filter is documented in iommu/apple,sart.yaml.

if:
  properties:
    compatible:
      contains:
        const: apple,t8103-nvme-ans2
then:
  properties:
    power-domains:
      maxItems: 2
    power-domain-names:
      maxItems: 2
else:
  properties:
    power-domains:
      minItems: 3
    power-domain-names:
      minItems: 3

required:
  - compatible
  - reg
  - reg-names
  - resets
  - power-domains
  - power-domain-names
  - mboxes
  - interrupts
  - apple,sart

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/apple-aic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    nvme@7bcc0000 {
      compatible = "apple,t8103-nvme-ans2", "apple,nvme-ans2";
      reg = <0x7bcc0000 0x40000>, <0x77400000 0x4000>;
      reg-names = "nvme", "ans";
      interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>;
      mboxes = <&ans>;
      apple,sart = <&sart>;
      power-domains = <&ps_ans2>, <&ps_apcie_st>;
      power-domain-names = "ans", "apcie0";
      resets = <&ps_ans2>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/allwinner,sun4i-a10-sid.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 Security ID

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    oneOf:
      - const: allwinner,sun4i-a10-sid
      - const: allwinner,sun7i-a20-sid
      - const: allwinner,sun8i-a83t-sid
      - const: allwinner,sun8i-h3-sid
      - const: allwinner,sun20i-d1-sid
      - const: allwinner,sun50i-a64-sid
      - items:
          - const: allwinner,sun50i-a100-sid
          - const: allwinner,sun50i-a64-sid
      - const: allwinner,sun50i-h5-sid
      - const: allwinner,sun50i-h6-sid

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    efuse@1c23800 {
        compatible = "allwinner,sun4i-a10-sid";
        reg = <0x01c23800 0x10>;
    };

  - |
    efuse@1c23800 {
        compatible = "allwinner,sun7i-a20-sid";
        reg = <0x01c23800 0x200>;
    };

...


code:
= Amlogic Meson GX eFuse device tree bindings =

Required properties:
- compatible: should be "amlogic,meson-gxbb-efuse"
- clocks: phandle to the efuse peripheral clock provided by the
	  clock controller.
- secure-monitor: phandle to the secure-monitor node

= Data cells =
Are child nodes of eFuse, bindings of which as described in
bindings/nvmem/nvmem.txt

Example:

	efuse: efuse {
		compatible = "amlogic,meson-gxbb-efuse";
		clocks = <&clkc CLKID_EFUSE>;
		#address-cells = <1>;
		#size-cells = <1>;
		secure-monitor = <&sm>;

		sn: sn@14 {
			reg = <0x14 0x10>;
		};

		eth_mac: eth_mac@34 {
			reg = <0x34 0x10>;
		};

		bid: bid@46 {
			reg = <0x46 0x30>;
		};
	};

	sm: secure-monitor {
		compatible = "amlogic,meson-gxbb-sm";
	};

= Data consumers =
Are device nodes which consume nvmem data cells.

For example:

	eth_mac {
		...
		nvmem-cells = <&eth_mac>;
		nvmem-cell-names = "eth_mac";
	};


code:
Amlogic Meson6/Meson8/Meson8b efuse

Required Properties:
- compatible: depending on the SoC this should be one of:
	- "amlogic,meson6-efuse"
	- "amlogic,meson8-efuse"
	- "amlogic,meson8b-efuse"
- reg: base address and size of the efuse registers
- clocks: a reference to the efuse core gate clock
- clock-names: must be "core"

All properties and sub-nodes as well as the consumer bindings
defined in nvmem.txt in this directory are also supported.

Example:
	efuse: nvmem@0 {
		compatible = "amlogic,meson8-efuse";
		reg = <0x0 0x2000>;
		clocks = <&clkc CLKID_EFUSE>;
		clock-names = "core";
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/apple,efuses.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple SoC eFuse-based NVMEM

description: |
  Apple SoCs such as the M1 contain factory-programmed eFuses used to e.g. store
  calibration data for the PCIe and the Type-C PHY or unique chip identifiers
  such as the ECID.

maintainers:
  - Sven Peter <sven@svenpeter.dev>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    items:
      - enum:
          - apple,t8103-efuses
          - apple,t6000-efuses
      - const: apple,efuses

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    efuse@3d2bc000 {
        compatible = "apple,t8103-efuses", "apple,efuses";
        reg = <0x3d2bc000 0x1000>;
        #address-cells = <1>;
        #size-cells = <1>;

        ecid: efuse@500 {
            reg = <0x500 0x8>;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/brcm,nvram.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom's NVRAM

description: |
  Broadcom's NVRAM is a structure containing device specific environment
  variables. It is used for storing device configuration, booting parameters
  and calibration data.

  NVRAM can be accessed on Broadcom BCM47xx MIPS and Northstar ARM Cortex-A9
  devices usiong I/O mapped memory.

  NVRAM variables can be defined as NVMEM device subnodes.

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    const: brcm,nvram

  reg:
    maxItems: 1

  board_id:
    type: object
    description: Board identification name

  et0macaddr:
    type: object
    description: First Ethernet interface's MAC address

  et1macaddr:
    type: object
    description: Second Ethernet interface's MAC address

  et2macaddr:
    type: object
    description: Third Ethernet interface's MAC address

unevaluatedProperties: false

examples:
  - |
    nvram@1eff0000 {
        compatible = "brcm,nvram";
        reg = <0x1eff0000 0x10000>;

        mac: et0macaddr {
        };
    };


code:
Broadcom OTP memory controller

Required Properties:
- compatible: "brcm,ocotp" for the first generation Broadcom OTPC which is used
  in Cygnus and supports 32 bit read/write. Use "brcm,ocotp-v2" for the second
  generation Broadcom OTPC which is used in SoC's such as Stingray and supports
  64-bit read/write.
- reg: Base address of the OTP controller.
- brcm,ocotp-size: Amount of memory available, in 32 bit words

Example:

otp: otp@301c800 {
	compatible = "brcm,ocotp";
	reg = <0x0301c800 0x2c>;
	brcm,ocotp-size = <2048>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/fsl,layerscape-sfp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Layerscape Security Fuse Processor

maintainers:
  - Michael Walle <michael@walle.cc>

description: |
  SFP is the security fuse processor which among other things provides a
  unique identifier per part.

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    oneOf:
      - description: Trust architecture 2.1 SFP
        items:
          - const: fsl,ls1021a-sfp
      - description: Trust architecture 3.0 SFP
        items:
          - const: fsl,ls1028a-sfp

  reg:
    maxItems: 1

  clocks:
    maxItems: 1
    description:
      The SFP clock. Typically, this is the platform clock divided by 4.

  clock-names:
    const: sfp

  ta-prog-sfp-supply:
    description:
      The regulator for the TA_PROG_SFP pin. It will be enabled for programming
      and disabled for reading.

required:
  - compatible
  - reg
  - clock-names
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
    efuse@1e80000 {
        compatible = "fsl,ls1028a-sfp";
        reg = <0x1e80000 0x8000>;
        clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
                            QORIQ_CLK_PLL_DIV(4)>;
        clock-names = "sfp";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/fsl,scu-ocotp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX SCU Client Device Node - OCOTP bindings based on SCU Message Protocol

maintainers:
  - Dong Aisheng <aisheng.dong@nxp.com>

description: i.MX SCU Client Device Node
  Client nodes are maintained as children of the relevant IMX-SCU device node.

allOf:
  - $ref: nvmem.yaml#

properties:
  compatible:
    enum:
      - fsl,imx8qm-scu-ocotp
      - fsl,imx8qxp-scu-ocotp

patternProperties:
  '^mac@[0-9a-f]*$':
    type: object
    description:
      MAC address.

    properties:
      reg:
        description:
          Byte offset within OCOTP where the MAC address is stored
        maxItems: 1

    required:
      - reg

    additionalProperties: false

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    ocotp {
        compatible = "fsl,imx8qxp-scu-ocotp";
        #address-cells = <1>;
        #size-cells = <1>;

        fec_mac0: mac@2c4 {
            reg = <0x2c4 6>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/imx-iim.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX IC Identification Module (IIM)

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

description: |
  This binding represents the IC Identification Module (IIM) found on
  i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 and i.MX53 SoCs.

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    enum:
      - fsl,imx25-iim
      - fsl,imx27-iim
      - fsl,imx31-iim
      - fsl,imx35-iim
      - fsl,imx51-iim
      - fsl,imx53-iim

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx5-clock.h>

    iim: efuse@63f98000 {
        compatible = "fsl,imx53-iim";
        reg = <0x63f98000 0x4000>;
        interrupts = <69>;
        clocks = <&clks IMX5_CLK_IIM_GATE>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX6 On-Chip OTP Controller (OCOTP)

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

description: |
  This binding represents the on-chip eFuse OTP controller found on
  i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL,
  i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN and i.MX8MP SoCs.

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - fsl,imx6q-ocotp
              - fsl,imx6sl-ocotp
              - fsl,imx6sx-ocotp
              - fsl,imx6ul-ocotp
              - fsl,imx6ull-ocotp
              - fsl,imx7d-ocotp
              - fsl,imx6sll-ocotp
              - fsl,imx7ulp-ocotp
              - fsl,imx8mq-ocotp
              - fsl,imx8mm-ocotp
          - const: syscon
      - items:
          - enum:
              - fsl,imx8mn-ocotp
              # i.MX8MP not really compatible with fsl,imx8mm-ocotp, however
              # the code for getting SoC revision depends on fsl,imx8mm-ocotp
              # compatible.
              - fsl,imx8mp-ocotp
          - const: fsl,imx8mm-ocotp
          - const: syscon

  reg:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  clocks:
    maxItems: 1

required:
  - "#address-cells"
  - "#size-cells"
  - compatible
  - reg

patternProperties:
  "^.*@[0-9a-f]+$":
    type: object

    properties:
      reg:
        maxItems: 1
        description:
          Offset and size in bytes within the storage device.

    required:
      - reg

    additionalProperties: false

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx6sx-clock.h>

    ocotp: efuse@21bc000 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "fsl,imx6sx-ocotp", "syscon";
        reg = <0x021bc000 0x4000>;
        clocks = <&clks IMX6SX_CLK_OCOTP>;

        cpu_speed_grade: speed-grade@10 {
            reg = <0x10 4>;
        };

        tempmon_calib: calib@38 {
            reg = <0x38 4>;
        };

        tempmon_temp_grade: temp-grade@20 {
            reg = <0x20 4>;
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic JZ EFUSE driver bindings

maintainers:
  - PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    enum:
      - ingenic,jz4780-efuse

  reg:
    maxItems: 1

  clocks:
    # Handle for the ahb for the efuse.
    maxItems: 1

required:
  - compatible
  - reg
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>

    efuse@134100d0 {
        compatible = "ingenic,jz4780-efuse";
        reg = <0x134100d0 0x2c>;

        clocks = <&cgu JZ4780_CLK_AHB2>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/layouts/kontron,sl28-vpd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVMEM layout of the Kontron SMARC-sAL28 vital product data

maintainers:
  - Michael Walle <michael@walle.cc>

description:
  The vital product data (VPD) of the sl28 boards contains a serial
  number and a base MAC address. The actual MAC addresses for the
  on-board ethernet devices are derived from this base MAC address by
  adding an offset.

select: false

properties:
  compatible:
    const: kontron,sl28-vpd

  serial-number:
    type: object
    description: The board's serial number

    additionalProperties: false

  base-mac-address:
    type: object
    description:
      Base MAC address for all on-module network interfaces. The first
      argument of the phandle will be treated as an offset.

    properties:
      "#nvmem-cell-cells":
        const: 1

    additionalProperties: false

required:
  - compatible

additionalProperties: false

examples:
  - |
      otp-1 {
          compatible = "user-otp";

          nvmem-layout {
              compatible = "kontron,sl28-vpd";

              serial_number: serial-number {
              };

              base_mac_address: base-mac-address {
                  #nvmem-cell-cells = <1>;
              };
          };
      };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/layouts/nvmem-layout.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVMEM (Non Volatile Memory) layouts

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
  - Michael Walle <michael@walle.cc>
  - Miquel Raynal <miquel.raynal@bootlin.com>

description: |
  Most NVMEM layouts are static and thus do not require additional description
  besides the bytes/bits offset and length. Other layouts can be less statically
  define and might require dynamic reading of the NVMEM device in order to
  perform their parsing. The nvmem-layout container is here to describe these.

oneOf:
  - $ref: kontron,sl28-vpd.yaml
  - $ref: onie,tlv-layout.yaml

properties:
  compatible: true

  '#address-cells': false

  '#size-cells': false

required:
  - compatible

unevaluatedProperties: false


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/layouts/onie,tlv-layout.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVMEM layout of the ONIE tlv table

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

description:
  Modern networking hardware implementing the Open Compute Project ONIE
  infrastructure shall provide a non-volatile memory with a table whose the
  content is well specified and gives many information about the manufacturer
  (name, country of manufacture, etc) as well as device caracteristics (serial
  number, hardware version, mac addresses, etc). The underlaying device type
  (flash, EEPROM,...) is not specified. The exact location of each value is also
  dynamic and should be discovered at run time because it depends on the
  parameters the manufacturer decided to embed.

select: false

properties:
  compatible:
    const: onie,tlv-layout

  product-name:
    type: object
    additionalProperties: false

  part-number:
    type: object
    additionalProperties: false

  serial-number:
    type: object
    additionalProperties: false

  mac-address:
    type: object
    description:
      Base MAC address for all on-module network interfaces. The first
      argument of the phandle will be treated as an offset.

    properties:
      "#nvmem-cell-cells":
        const: 1

    additionalProperties: false

  manufacture-date:
    type: object
    additionalProperties: false

  device-version:
    type: object
    additionalProperties: false

  label-revision:
    type: object
    additionalProperties: false

  platforn-name:
    type: object
    additionalProperties: false

  onie-version:
    type: object
    additionalProperties: false

  num-macs:
    type: object
    additionalProperties: false

  manufacturer:
    type: object
    additionalProperties: false

  country-code:
    type: object
    additionalProperties: false

  vendor:
    type: object
    additionalProperties: false

  diag-version:
    type: object
    additionalProperties: false

  service-tag:
    type: object
    additionalProperties: false

  vendor-extension:
    type: object
    additionalProperties: false

required:
  - compatible

additionalProperties: false

examples:
  - |
    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        eeprom@56 {
            compatible = "atmel,24c64";
            read-only;
            reg = <0x56>;

            nvmem-layout {
                compatible = "onie,tlv-layout";

                serial-number {
                };
            };
        };
    };

  - |
    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        flash@0 {
            compatible = "m25p80", "jedec,spi-nor";
            reg = <0>;

            otp {
                compatible = "user-otp";

                nvmem-layout {
                    compatible = "onie,tlv-layout";

                    mac-address {
                        #nvmem-cell-cells = <1>;
                    };
                };
            };
        };
    };
...


code:
* NXP LPC18xx OTP memory

Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.

Required properties:
  - compatible: Should be "nxp,lpc1850-otp"
  - reg: Must contain an entry with the physical base address and length
    for each entry in reg-names.
  - address-cells: must be set to 1.
  - size-cells: must be set to 1.

See nvmem.txt for more information.

Example:
  otp: otp@40045000 {
    compatible = "nxp,lpc1850-otp";
    reg = <0x40045000 0x1000>;
    #address-cells = <1>;
    #size-cells = <1>;
  };


code:
* NXP LPC18xx EEPROM memory NVMEM driver

Required properties:
  - compatible: Should be "nxp,lpc1857-eeprom"
  - reg: Must contain an entry with the physical base address and length
    for each entry in reg-names.
  - reg-names: Must include the following entries.
    - reg: EEPROM registers.
    - mem: EEPROM address space.
  - clocks: Must contain an entry for each entry in clock-names.
  - clock-names: Must include the following entries.
    - eeprom: EEPROM operating clock.
  - resets: Should contain a reference to the reset controller asserting
    the EEPROM in reset.
  - interrupts: Should contain EEPROM interrupt.

Example:

  eeprom: eeprom@4000e000 {
    compatible = "nxp,lpc1857-eeprom";
    reg = <0x4000e000 0x1000>,
          <0x20040000 0x4000>;
    reg-names = "reg", "mem";
    clocks = <&ccu1 CLK_CPU_EEPROM>;
    clock-names = "eeprom";
    resets = <&rgu 27>;
    interrupts = <4>;
  };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/mediatek,efuse.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek efuse

description: |
  MediaTek's efuse is used for storing calibration data, it can be accessed
  on ARM devices usiong I/O mapped memory.

maintainers:
  - Andrew-CT Chen <andrew-ct.chen@mediatek.com>
  - Lala Lin <lala.lin@mediatek.com>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  $nodename:
    pattern: "^efuse@[0-9a-f]+$"

  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt7622-efuse
              - mediatek,mt7623-efuse
              - mediatek,mt8173-efuse
              - mediatek,mt8183-efuse
              - mediatek,mt8186-efuse
              - mediatek,mt8188-efuse
              - mediatek,mt8192-efuse
              - mediatek,mt8195-efuse
              - mediatek,mt8516-efuse
          - const: mediatek,efuse
      - const: mediatek,mt8173-efuse
        deprecated: true

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    efuse@11c10000 {
        compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
        reg = <0x11c10000 0x1000>;
        #address-cells = <1>;
        #size-cells = <1>;

        u3_tx_imp_p0: usb3-tx-imp@184,1 {
            reg = <0x184 0x1>;
            bits = <0 5>;
        };
        u3_rx_imp_p0: usb3-rx-imp@184,2 {
            reg = <0x184 0x2>;
            bits = <5 5>;
        };
        u3_intr_p0: usb3-intr@185 {
            reg = <0x185 0x1>;
            bits = <2 6>;
        };
        comb_tx_imp_p1: usb3-tx-imp@186,1 {
            reg = <0x186 0x1>;
            bits = <0 5>;
        };
        comb_rx_imp_p1: usb3-rx-imp@186,2 {
            reg = <0x186 0x2>;
            bits = <5 5>;
        };
        comb_intr_p1: usb3-intr@187 {
            reg = <0x187 0x1>;
            bits = <2 6>;
        };
        u2_intr_p0: usb2-intr-p0@188,1 {
            reg = <0x188 0x1>;
            bits = <0 5>;
        };
        u2_intr_p1: usb2-intr-p1@188,2 {
            reg = <0x188 0x2>;
            bits = <5 5>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/microchip,lan9662-otpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip LAN9662 OTP Controller (OTPC)

maintainers:
  - Horatiu Vultur <horatiu.vultur@microchip.com>

description: |
  OTP controller drives a NVMEM memory where system specific data
  (e.g. hardware configuration settings, chip identifiers) or
  user specific data could be stored.

allOf:
  - $ref: nvmem.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - const: microchip,lan9668-otpc
          - const: microchip,lan9662-otpc
      - enum:
          - microchip,lan9662-otpc

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    otpc: otp@e0021000 {
        compatible = "microchip,lan9662-otpc";
        reg = <0xe0021000 0x300>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip SAMA7G5 OTP Controller (OTPC)

maintainers:
  - Claudiu Beznea <claudiu.beznea@microchip.com>

description: |
  OTP controller drives a NVMEM memory where system specific data
  (e.g. calibration data for analog cells, hardware configuration
  settings, chip identifiers) or user specific data could be stored.

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    items:
      - const: microchip,sama7g5-otpc
      - const: syscon

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>

    otpc: efuse@e8c00000 {
        compatible = "microchip,sama7g5-otpc", "syscon";
        reg = <0xe8c00000 0xec>;
        #address-cells = <1>;
        #size-cells = <1>;

        temperature_calib: calib@1 {
            reg = <OTP_PKT(1) 76>;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/mxs-ocotp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: On-Chip OTP Memory for Freescale i.MX23/i.MX28

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    enum:
      - fsl,imx23-ocotp
      - fsl,imx28-ocotp

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    ocotp: efuse@8002c000 {
        compatible = "fsl,imx28-ocotp";
        #address-cells = <1>;
        #size-cells = <1>;
        reg = <0x8002c000 0x2000>;
        clocks = <&clks 25>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Nintendo Wii and Wii U OTP

description: |
  This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
  which contains common and per-console keys, signatures and related data
  required to access peripherals.

  See https://wiiubrew.org/wiki/Hardware/OTP

maintainers:
  - Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>

allOf:
  - $ref: "nvmem.yaml#"

properties:
  compatible:
    enum:
      - nintendo,hollywood-otp
      - nintendo,latte-otp

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    otp@d8001ec {
        compatible = "nintendo,latte-otp";
        reg = <0x0d8001ec 0x8>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/nvmem-consumer.yaml#
$schema: http://devicetree.org/meta-schemas/base.yaml#

title: NVMEM (Non Volatile Memory) Consumer

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

select: true

properties:
  nvmem:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description:
      List of phandle to the nvmem providers.

  nvmem-cells:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description:
      List of phandle to the nvmem data cells.

  nvmem-names:
    description:
      Names for the each nvmem provider.

  nvmem-cell-names:
    description:
      Names for each nvmem-cells specified.

dependencies:
  nvmem-names: [ nvmem ]
  nvmem-cell-names: [ nvmem-cells ]

additionalProperties: true

examples:
  - |
    tsens {
        /* ... */
        nvmem-cells = <&tsens_calibration>;
        nvmem-cell-names = "calibration";
    };


code: This file has been moved to nvmem.yaml and nvmem-consumer.yaml.


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/nvmem.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVMEM (Non Volatile Memory)

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description: |
  This binding is intended to represent the location of hardware
  configuration data stored in NVMEMs like eeprom, efuses and so on.

  On a significant proportion of boards, the manufacturer has stored
  some data on NVMEM, for the OS to be able to retrieve these
  information and act upon it. Obviously, the OS has to know about
  where to retrieve these data from, and where they are stored on the
  storage device.

properties:
  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  read-only:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Mark the provider as read only.

  wp-gpios:
    description:
      GPIO to which the write-protect pin of the chip is connected.
      The write-protect GPIO is asserted, when it's driven high
      (logical '1') to block the write operation. It's deasserted,
      when it's driven low (logical '0') to allow writing.
    maxItems: 1

  nvmem-layout:
    $ref: /schemas/nvmem/layouts/nvmem-layout.yaml
    description:
      Alternative to the statically defined nvmem cells, this
      container may reference more advanced (dynamic) layout
      parsers.

patternProperties:
  "@[0-9a-f]+(,[0-7])?$":
    type: object

    properties:
      reg:
        maxItems: 1
        description:
          Offset and size in bytes within the storage device.

      bits:
        $ref: /schemas/types.yaml#/definitions/uint32-array
        items:
          - minimum: 0
            maximum: 7
            description:
              Offset in bit within the address range specified by reg.
          - minimum: 1
            description:
              Size in bit within the address range specified by reg.

additionalProperties: true

examples:
  - |
      #include <dt-bindings/gpio/gpio.h>

      qfprom: eeprom@700000 {
          compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
          #address-cells = <1>;
          #size-cells = <1>;
          reg = <0x00700000 0x100000>;

          wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;

          /* ... */

          /* Data cells */
          tsens_calibration: calib@404 {
              reg = <0x404 0x10>;
          };

          tsens_calibration_bckp: calib_bckp@504 {
              reg = <0x504 0x11>;
              bits = <6 128>;
          };

          pvs_version: pvs-version@6 {
              reg = <0x6 0x2>;
              bits = <7 2>;
          };

          speed_bin: speed-bin@c{
              reg = <0xc 0x1>;
              bits = <2 3>;
          };
      };

...