code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Bootlin
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mfd/xylon,logicvc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Xylon LogiCVC multi-function device

maintainers:
  - Paul Kocialkowski <paul.kocialkowski@bootlin.com>

description: |
  The LogiCVC is a display controller that also contains a GPIO controller.
  As a result, a multi-function device is exposed as parent of the display
  and GPIO blocks.

properties:
  compatible:
    items:
      - enum:
          - xylon,logicvc-3.02.a
      - const: syscon
      - const: simple-mfd

  reg:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

select:
  properties:
    compatible:
      contains:
        enum:
          - xylon,logicvc-3.02.a

  required:
    - compatible

patternProperties:
  "^gpio@[0-9a-f]+$":
    $ref: /schemas/gpio/xylon,logicvc-gpio.yaml#

  "^display@[0-9a-f]+$":
    $ref: /schemas/display/xylon,logicvc-display.yaml#

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    logicvc: logicvc@43c00000 {
      compatible = "xylon,logicvc-3.02.a", "syscon", "simple-mfd";
      reg = <0x43c00000 0x6000>;
    };


code:
Zodiac Inflight Innovations RAVE Supervisory Processor

RAVE Supervisory Processor communicates with SoC over UART. It is
expected that its Device Tree node is specified as a child of a node
corresponding to UART controller used for communication.

Required parent device properties:

 - compatible: Should be one of:
	- "zii,rave-sp-niu"
	- "zii,rave-sp-mezz"
	- "zii,rave-sp-esb"
	- "zii,rave-sp-rdu1"
	- "zii,rave-sp-rdu2"

 - current-speed: Should be set to baud rate SP device is using

RAVE SP consists of the following sub-devices:

Device				 Description
------				 -----------
rave-sp-wdt			: Watchdog
rave-sp-nvmem			: Interface to onboard EEPROM
rave-sp-backlight		: Display backlight
rave-sp-hwmon			: Interface to onboard hardware sensors
rave-sp-leds			: Interface to onboard LEDs
rave-sp-input			: Interface to onboard power button

Example of usage:

	rdu {
		compatible = "zii,rave-sp-rdu2";
		current-speed = <1000000>;

		watchdog {
			compatible = "zii,rave-sp-watchdog";
		};
	};

repo_name: angery/linux


code:
Binding for Qualcomm Atheros AR7xxx/AR9XXX SoC

Each device tree must specify a compatible value for the AR SoC
it uses in the compatible property of the root node. The compatible
value must be one of the following values:

- qca,ar7130
- qca,ar7141
- qca,ar7161
- qca,ar7240
- qca,ar7241
- qca,ar7242
- qca,ar9130
- qca,ar9132
- qca,ar9330
- qca,ar9331
- qca,ar9341
- qca,ar9342
- qca,ar9344
- qca,qca9556
- qca,qca9558


code:
* Broadcom cable/DSL/settop platforms

Required properties:

- compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
              "brcm,bcm3384-viper", "brcm,bcm33843-viper"
              "brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6362", "brcm,bcm6368",
              "brcm,bcm63168", "brcm,bcm63268",
              "brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360",
              "brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425"

The experimental -viper variants are for running Linux on the 3384's
BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.

Power management
----------------

For power management (particularly, S2/S3/S5 system suspend), the following SoC
components are needed:

= Always-On control block (AON CTRL)

This hardware provides control registers for the "always-on" (even in low-power
modes) hardware, such as the Power Management State Machine (PMSM).

Required properties:
- compatible     : should be one of
		   "brcm,bcm7425-aon-ctrl"
		   "brcm,bcm7429-aon-ctrl"
		   "brcm,bcm7435-aon-ctrl" and
		   "brcm,brcmstb-aon-ctrl"
- reg            : the register start and length for the AON CTRL block

Example:

syscon@410000 {
	compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
	reg = <0x410000 0x400>;
};

= Memory controllers

A Broadcom STB SoC typically has a number of independent memory controllers,
each of which may have several associated hardware blocks, which are versioned
independently (control registers, DDR PHYs, etc.). One might consider
describing these controllers as a parent "memory controllers" block, which
contains N sub-nodes (one for each controller in the system), each of which is
associated with a number of hardware register resources (e.g., its PHY.

== MEMC (MEMory Controller)

Represents a single memory controller instance.

Required properties:
- compatible     : should contain "brcm,brcmstb-memc" and "simple-bus"
- ranges	 : should contain the child address in the parent address
		   space, must be 0 here, and the register start and length of
		   the entire memory controller (including all sub nodes: DDR PHY,
		   arbiter, etc.)
- #address-cells : must be 1
- #size-cells	 : must be 1

Example:

	memory-controller@0 {
		compatible = "brcm,brcmstb-memc", "simple-bus";
		ranges = <0x0 0x0 0xa000>;
		#address-cells = <1>;
		#size-cells = <1>;

		memc-arb@1000 {
			...
		};

		memc-ddr@2000 {
			...
		};

		ddr-phy@6000 {
			...
		};
	};

Should contain subnodes for any of the following relevant hardware resources:

== DDR PHY control

Control registers for this memory controller's DDR PHY.

Required properties:
- compatible     : should contain one of these
		   "brcm,brcmstb-ddr-phy-v64.5"
		   "brcm,brcmstb-ddr-phy"

- reg            : the DDR PHY register range and length

Example:

	ddr-phy@6000 {
		compatible = "brcm,brcmstb-ddr-phy-v64.5";
		reg = <0x6000 0xc8>;
	};

== DDR memory controller sequencer

Control registers for this memory controller's DDR memory sequencer

Required properties:
- compatible     : should contain one of these
		   "brcm,bcm7425-memc-ddr"
		   "brcm,bcm7429-memc-ddr"
		   "brcm,bcm7435-memc-ddr" and
		   "brcm,brcmstb-memc-ddr"

- reg            : the DDR sequencer register range and length

Example:

	memc-ddr@2000 {
		compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr";
		reg = <0x2000 0x300>;
	};

== MEMC Arbiter

The memory controller arbiter is responsible for memory clients allocation
(bandwidth, priorities etc.) and needs to have its contents restored during
deep sleep states (S3).

Required properties:

- compatible	: should contain one of these
		  "brcm,brcmstb-memc-arb-v10.0.0.0"
		  "brcm,brcmstb-memc-arb"

- reg		: the DDR Arbiter register range and length

Example:

	memc-arb@1000 {
		compatible = "brcm,brcmstb-memc-arb-v10.0.0.0";
		reg = <0x1000 0x248>;
	};

== Timers

The Broadcom STB chips contain a timer block with several general purpose
timers that can be used.

Required properties:

- compatible	: should contain one of:
		  "brcm,bcm7425-timers"
		  "brcm,bcm7429-timers"
		  "brcm,bcm7435-timers" and
		  "brcm,brcmstb-timers"
- reg		: the timers register range
- interrupts	: the interrupt line for this timer block

Example:

	timers: timer@4067c0 {
		compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers";
		reg = <0x4067c0 0x40>;
		interrupts = <&periph_intc 19>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/brcm/soc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom cable/DSL/settop platforms

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

description: |
    Boards Broadcom cable/DSL/settop SoC shall have the following properties.
    The experimental -viper variants are for running Linux on the 3384's
    BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.

properties:
  $nodename:
    const: '/'

  compatible:
    enum:
      - brcm,bcm3368
      - brcm,bcm3384
      - brcm,bcm33843
      - brcm,bcm3384-viper
      - brcm,bcm33843-viper
      - brcm,bcm6328
      - brcm,bcm6358
      - brcm,bcm6362
      - brcm,bcm6368
      - brcm,bcm63168
      - brcm,bcm63268
      - brcm,bcm7125
      - brcm,bcm7346
      - brcm,bcm7358
      - brcm,bcm7360
      - brcm,bcm7362
      - brcm,bcm7420
      - brcm,bcm7425

  cpus:
    type: object
    additionalProperties: false
    properties:
      '#address-cells':
        const: 1

      '#size-cells':
        const: 0

      mips-hpt-frequency:
        description: MIPS counter high precision timer frequency.
         This is common to all CPUs in the system so it lives
         under the "cpus" node.
        $ref: /schemas/types.yaml#/definitions/uint32

    patternProperties:
      "^cpu@[0-9]$":
        type: object
        $ref: /schemas/mips/cpus.yaml#
        unevaluatedProperties: false

    required:
      - mips-hpt-frequency

additionalProperties: true

examples:
  - |
     / {
         compatible = "brcm,bcm3368";
         #address-cells = <1>;
         #size-cells = <1>;
         model = "Broadcom 3368";

         cpus {
           #address-cells = <1>;
           #size-cells = <0>;

           mips-hpt-frequency = <150000000>;

           cpu@0 {
             compatible = "brcm,bmips4350";
             device_type = "cpu";
             reg = <0>;
           };

           cpu@1 {
             compatible = "brcm,bmips4350";
             device_type = "cpu";
             reg = <1>;
           };
         };
       };
...


code:
* Boot Bus

The Octeon Boot Bus is a configurable parallel bus with 8 chip
selects.  Each chip select is independently configurable.

Properties:
- compatible: "cavium,octeon-3860-bootbus"

  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.

- reg: The base address of the Boot Bus' register bank.

- #address-cells: Must be <2>.  The first cell is the chip select
   within the bootbus.  The second cell is the offset from the chip select.

- #size-cells: Must be <1>.

- ranges: There must be one one triplet of (child-bus-address,
  parent-bus-address, length) for each active chip select.  If the
  length element for any triplet is zero, the chip select is disabled,
  making it inactive.

The configuration parameters for each chip select are stored in child
nodes.

Configuration Properties:
- compatible:  "cavium,octeon-3860-bootbus-config"

- cavium,cs-index: A single cell indicating the chip select that
  corresponds to this configuration.

- cavium,t-adr: A cell specifying the ADR timing (in nS).

- cavium,t-ce: A cell specifying the CE timing (in nS).

- cavium,t-oe: A cell specifying the OE timing (in nS).

- cavium,t-we: A cell specifying the WE timing (in nS).

- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).

- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).

- cavium,t-pause: A cell specifying the PAUSE timing (in nS).

- cavium,t-wait: A cell specifying the WAIT timing (in nS).

- cavium,t-page: A cell specifying the PAGE timing (in nS).

- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).

- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
  = 2 bytes, 2 = 4 bytes, 3 = 8 bytes).

- cavium,wait-mode: Optional.  If present, wait mode (WAITM) is selected.

- cavium,page-mode: Optional.  If present, page mode (PAGEM) is selected.

- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of
  the bus for this chip select.

- cavium,ale-mode: Optional.  If present, ALE mode is selected.

- cavium,sam-mode: Optional.  If present, SAM mode is selected.

- cavium,or-mode: Optional.  If present, OR mode is selected.

Example:
	bootbus: bootbus@1180000000000 {
		compatible = "cavium,octeon-3860-bootbus";
		reg = <0x11800 0x00000000 0x0 0x200>;
		/* The chip select number and offset */
		#address-cells = <2>;
		/* The size of the chip select region */
		#size-cells = <1>;
		ranges = <0 0  0x0 0x1f400000  0xc00000>,
			 <1 0  0x10000 0x30000000  0>,
			 <2 0  0x10000 0x40000000  0>,
			 <3 0  0x10000 0x50000000  0>,
			 <4 0  0x0 0x1d020000  0x10000>,
			 <5 0  0x0 0x1d040000  0x10000>,
			 <6 0  0x0 0x1d050000  0x10000>,
			 <7 0  0x10000 0x90000000  0>;

			cavium,cs-config@0 {
			compatible = "cavium,octeon-3860-bootbus-config";
			cavium,cs-index = <0>;
			cavium,t-adr  = <20>;
			cavium,t-ce   = <60>;
			cavium,t-oe   = <60>;
			cavium,t-we   = <45>;
			cavium,t-rd-hld = <35>;
			cavium,t-wr-hld = <45>;
			cavium,t-pause  = <0>;
			cavium,t-wait   = <0>;
			cavium,t-page   = <35>;
			cavium,t-rd-dly = <0>;

			cavium,pages     = <0>;
			cavium,bus-width = <8>;
		};
		.
		.
		.
		cavium,cs-config@6 {
			compatible = "cavium,octeon-3860-bootbus-config";
			cavium,cs-index = <6>;
			cavium,t-adr  = <5>;
			cavium,t-ce   = <300>;
			cavium,t-oe   = <270>;
			cavium,t-we   = <150>;
			cavium,t-rd-hld = <100>;
			cavium,t-wr-hld = <70>;
			cavium,t-pause  = <0>;
			cavium,t-wait   = <0>;
			cavium,t-page   = <320>;
			cavium,t-rd-dly = <0>;

			cavium,pages     = <0>;
			cavium,wait-mode;
			cavium,bus-width = <16>;
		};
		.
		.
		.
	};


code:
* Cavium Interrupt Bus widget

Properties:
- compatible: "cavium,octeon-7130-cib"

  Compatibility with cn70XX SoCs.

- interrupt-controller:  This is an interrupt controller.

- reg: Two elements consisting of the addresses of the RAW and EN
  registers of the CIB block

- cavium,max-bits: The index (zero based) of the highest numbered bit
  in the CIB block.

- interrupts: The CIU line to which the CIB block is connected.

- #interrupt-cells: Must be <2>.  The first cell is the bit within the
   CIB.  The second cell specifies the triggering semantics of the
   line.

Example:

	interrupt-controller@107000000e000 {
		compatible = "cavium,octeon-7130-cib";
		reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */
		      <0x10700 0x0000e100 0x0 0x8>; /* EN */
		cavium,max-bits = <23>;

		interrupt-controller;
		interrupt-parent = <&ciu>;
		interrupts = <1 24>;
		/* Interrupts are specified by two parts:
		 * 1) Bit number in the CIB* registers
		 * 2) Triggering (1 - edge rising
		 *		  2 - edge falling
		 *		  4 - level active high
		 *		  8 - level active low)
		 */
		#interrupt-cells = <2>;
	};


code:
* Central Interrupt Unit

Properties:
- compatible: "cavium,octeon-3860-ciu"

  Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs.

- interrupt-controller:  This is an interrupt controller.

- reg: The base address of the CIU's register bank.

- #interrupt-cells: Must be <2>.  The first cell is the bank within
   the CIU and may have a value of 0 or 1.  The second cell is the bit
   within the bank and may have a value between 0 and 63.

Example:
	interrupt-controller@1070000000000 {
		compatible = "cavium,octeon-3860-ciu";
		interrupt-controller;
		/* Interrupts are specified by two parts:
		 * 1) Controller register (0 or 1)
		 * 2) Bit within the register (0..63)
		 */
		#interrupt-cells = <2>;
		reg = <0x10700 0x00000000 0x0 0x7000>;
	};


code:
* Central Interrupt Unit

Properties:
- compatible: "cavium,octeon-6880-ciu2"

  Compatibility with 68XX SOCs.

- interrupt-controller:  This is an interrupt controller.

- reg: The base address of the CIU's register bank.

- #interrupt-cells: Must be <2>.  The first cell is the bank within
  the CIU and may have a value between 0 and 63.  The second cell is
  the bit within the bank and may also have a value between 0 and 63.

Example:
	interrupt-controller@1070100000000 {
		compatible = "cavium,octeon-6880-ciu2";
		interrupt-controller;
		/* Interrupts are specified by two parts:
		 * 1) Controller register (0..63)
		 * 2) Bit within the register (0..63)
		 */
		#address-cells = <0>;
		#interrupt-cells = <2>;
		reg = <0x10701 0x00000000 0x0 0x4000000>;
	};


code:
* Central Interrupt Unit v3

Properties:
- compatible: "cavium,octeon-7890-ciu3"

  Compatibility with 78XX and 73XX SOCs.

- interrupt-controller:  This is an interrupt controller.

- reg: The base address of the CIU's register bank.

- #interrupt-cells: Must be <2>.  The first cell is source number.
  The second cell indicates the triggering semantics, and may have a
  value of either 4 for level semantics, or 1 for edge semantics.

Example:
	interrupt-controller@1010000000000 {
		compatible = "cavium,octeon-7890-ciu3";
		interrupt-controller;
		/* Interrupts are specified by two parts:
		 * 1) Source number (20 significant bits)
		 * 2) Trigger type: (4 == level, 1 == edge)
		 */
		#address-cells = <0>;
		#interrupt-cells = <2>;
		reg = <0x10100 0x00000000 0x0 0xb0000000>;
	};


code:
* DMA Engine.

The Octeon DMA Engine transfers between the Boot Bus and main memory.
The DMA Engine will be referred to by phandle by any device that is
connected to it.

Properties:
- compatible: "cavium,octeon-5750-bootbus-dma"

  Compatibility with all cn52XX, cn56XX and cn6XXX SOCs.

- reg: The base address of the DMA Engine's register bank.

- interrupts: A single interrupt specifier.

Example:
	dma0: dma-engine@1180000000100 {
		compatible = "cavium,octeon-5750-bootbus-dma";
		reg = <0x11800 0x00000100 0x0 0x8>;
		interrupts = <0 63>;
	};


code:
* UCTL SATA controller glue

UCTL is the bridge unit between the I/O interconnect (an internal bus)
and the SATA AHCI host controller (UAHC). It performs the following functions:
	- provides interfaces for the applications to access the UAHC AHCI
	  registers on the CN71XX I/O space.
	- provides a bridge for UAHC to fetch AHCI command table entries and data
	  buffers from Level 2 Cache.
	- posts interrupts to the CIU.
	- contains registers that:
		- control the behavior of the UAHC
		- control the clock/reset generation to UAHC
		- control endian swapping for all UAHC registers and DMA accesses

Properties:

- compatible: "cavium,octeon-7130-sata-uctl"

  Compatibility with the cn7130 SOC.

- reg: The base address of the UCTL register bank.

- #address-cells, #size-cells, ranges and dma-ranges must be present and hold
	suitable values to map all child nodes.

Example:

	uctl@118006c000000 {
		compatible = "cavium,octeon-7130-sata-uctl";
		reg = <0x11800 0x6c000000 0x0 0x100>;
		ranges; /* Direct mapping */
		dma-ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		sata: sata@16c0000000000 {
			compatible = "cavium,octeon-7130-ahci";
			reg = <0x16c00 0x00000000 0x0 0x200>;
			interrupt-parent = <&cibsata>;
			interrupts = <2 4>; /* Bit: 2, level */
		};
	};


code:
* UCTL USB controller glue

Properties:
- compatible: "cavium,octeon-6335-uctl"

  Compatibility with all cn6XXX SOCs.

- reg: The base address of the UCTL register bank.

- #address-cells: Must be <2>.

- #size-cells: Must be <2>.

- ranges: Empty to signify direct mapping of the children.

- refclk-frequency: A single cell containing the reference clock
  frequency in Hz.

- refclk-type: A string describing the reference clock connection
  either "crystal" or "external".

Example:
	uctl@118006f000000 {
		compatible = "cavium,octeon-6335-uctl";
		reg = <0x11800 0x6f000000 0x0 0x100>;
		ranges; /* Direct mapping */
		#address-cells = <2>;
		#size-cells = <2>;
		/* 12MHz, 24MHz and 48MHz allowed */
		refclk-frequency = <24000000>;
		/* Either "crystal" or "external" */
		refclk-type = "crystal";

		ehci@16f0000000000 {
			compatible = "cavium,octeon-6335-ehci","usb-ehci";
			reg = <0x16f00 0x00000000 0x0 0x100>;
			interrupts = <0 56>;
			big-endian-regs;
		};
		ohci@16f0000000400 {
			compatible = "cavium,octeon-6335-ohci","usb-ohci";
			reg = <0x16f00 0x00000400 0x0 0x100>;
			interrupts = <0 56>;
			big-endian-regs;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/cpus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MIPS CPUs bindings

maintainers:
  - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
  - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

description: |
  The device tree allows to describe the layout of CPUs in a system through
  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
  defining properties for every CPU.

properties:
  compatible:
    enum:
      - brcm,bmips3300
      - brcm,bmips4350
      - brcm,bmips4380
      - brcm,bmips5000
      - brcm,bmips5200
      - ingenic,xburst-mxu1.0
      - ingenic,xburst-fpu1.0-mxu1.1
      - ingenic,xburst-fpu2.0-mxu2.0
      - ingenic,xburst2-fpu2.1-mxu2.1-smt
      - loongson,gs264
      - mips,m14Kc
      - mips,mips4Kc
      - mips,mips4KEc
      - mips,mips24Kc
      - mips,mips24KEc
      - mips,mips74Kc
      - mips,mips1004Kc
      - mti,interaptiv
      - mti,mips24KEc
      - mti,mips14KEc
      - mti,mips14Kc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  device_type: true

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - ingenic,xburst-mxu1.0
              - ingenic,xburst-fpu1.0-mxu1.1
              - ingenic,xburst-fpu2.0-mxu2.0
              - ingenic,xburst2-fpu2.1-mxu2.1-smt
    then:
      required:
        - device_type
        - clocks

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    cpus {
      #size-cells = <0>;
      #address-cells = <1>;

      cpu@0 {
        compatible = "mips,mips1004Kc";
        device_type = "cpu";
        reg = <0>;
      };

      cpu@1 {
        compatible = "mips,mips1004Kc";
        device_type = "cpu";
        reg = <1>;
      };
    };

  - |
    // Example 2 (Ingenic CPU)
    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>

    cpus {
      #address-cells = <1>;
      #size-cells = <0>;

      cpu@0 {
        compatible = "ingenic,xburst-fpu1.0-mxu1.1";
        device_type = "cpu";
        reg = <0>;

        clocks = <&cgu JZ4780_CLK_CPU>;
      };

      cpu@1 {
        compatible = "ingenic,xburst-fpu1.0-mxu1.1";
        device_type = "cpu";
        reg = <1>;

        clocks = <&cgu JZ4780_CLK_CORE1>;
      };
    };
...


code:
Imagination Technologies' Pistachio SoC based Marduk Board
==========================================================

Compatible string must be "img,pistachio-marduk", "img,pistachio"

Hardware and other related documentation is available at
https://docs.creatordev.io/ci40/

It is also known as Creator Ci40. Marduk is legacy name and will
be there for decades.


code:
Imagination Pistachio SoC
=========================

Required properties:
--------------------
 - compatible: Must include "img,pistachio".

CPU nodes:
----------
A "cpus" node is required.  Required properties:
 - #address-cells: Must be 1.
 - #size-cells: Must be 0.
A CPU sub-node is also required for at least CPU 0.  Since the topology may
be probed via CPS, it is not necessary to specify secondary CPUs.  Required
propertis:
 - device_type: Must be "cpu".
 - compatible: Must be "mti,interaptiv".
 - reg: CPU number.
 - clocks: Must include the CPU clock.  See ../../clock/clock-bindings.txt for
   details on clock bindings.
Example:
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "mti,interaptiv";
			reg = <0>;
			clocks = <&clk_core CLK_MIPS>;
		};
	};

Boot protocol:
--------------
In accordance with the MIPS UHI specification[1], the bootloader must pass the
following arguments to the kernel:
 - $a0: -2.
 - $a1: KSEG0 address of the flattened device-tree blob.

[1] http://prplfoundation.org/wiki/MIPS_documentation


code:
Imagination University Program MIPSfpga
=======================================

Under the Imagination University Program, a microAptiv UP core has been
released for academic usage.

As we are dealing with a MIPS core instantiated on an FPGA, specifications
are fluid and can be varied in RTL.

This binding document is provided as baseline guidance for the example
project provided by IMG.

The example project runs on the Nexys4DDR board by Digilent powered by
the ARTIX-7 FPGA by Xilinx.

Relevant details about the example project and the Nexys4DDR board:

- microAptiv UP core m14Kc
- 50MHz clock speed
- 128Mbyte DDR RAM	at 0x0000_0000
- 8Kbyte RAM		at 0x1000_0000
- axi_intc		at 0x1020_0000
- axi_uart16550		at 0x1040_0000
- axi_gpio		at 0x1060_0000
- axi_i2c		at 0x10A0_0000
- custom_gpio		at 0x10C0_0000
- axi_ethernetlite	at 0x10E0_0000
- 8Kbyte BootRAM	at 0x1FC0_0000

Required properties:
--------------------
 - compatible: Must include "digilent,nexys4ddr","img,xilfpga".

CPU nodes:
----------
A "cpus" node is required.  Required properties:
 - #address-cells: Must be 1.
 - #size-cells: Must be 0.
A CPU sub-node is also required for at least CPU 0. Required properties:
 - device_type: Must be "cpu".
 - compatible: Must be "mips,m14Kc".
 - reg: Must be <0>.
 - clocks: phandle to ext clock for fixed-clock received by MIPS core.

Example:

	compatible = "img,xilfpga","digilent,nexys4ddr";
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "mips,m14Kc";
			reg = <0>;
			clocks	= <&ext>;
		};
	};

	ext: ext {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
	};

Boot protocol:
--------------

The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
This is for easy reprogrammibility via JTAG.

The BootRAM initializes the cache and the axi_uart peripheral.

DDR initialization is already handled by a HW IP block.

When the example project bitstream is loaded, the cpu_reset button
needs to be pressed.

The bootram initializes the cache and axi_uart.
Then outputs MIPSFPGA\n\r on the serial port on the Nexys4DDR board.

At this point, the board is ready to load the Linux kernel
vmlinux file via JTAG.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/ingenic/devices.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic XBurst based Platforms Device Tree Bindings

maintainers:
  - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

description:
  Devices with a Ingenic XBurst CPU shall have the following properties.

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:

      - description: Qi Hardware Ben NanoNote
        items:
          - const: qi,lb60
          - const: ingenic,jz4740

      - description: YLM RetroMini RS-90
        items:
          - const: ylm,rs90
          - const: ingenic,jz4725b

      - description: Game Consoles Worldwide GCW Zero
        items:
          - const: gcw,zero
          - const: ingenic,jz4770

      - description: MIPS Creator CI20
        items:
          - const: img,ci20
          - const: ingenic,jz4780

      - description: YSH & ATIL General Board, CU1000 Module with Neo Backplane
        items:
          - const: yna,cu1000-neo
          - const: ingenic,x1000e

      - description: YSH & ATIL General Board, CU1830 Module with Neo Backplane
        items:
          - const: yna,cu1830-neo
          - const: ingenic,x1830

      - description: YSH & ATIL General Board, CU2000 Module with Neo Backplane
        items:
          - const: yna,cu2000-neo
          - const: ingenic,x2000e

additionalProperties: true

...


code:
Lantiq XWAY SoC FPI BUS binding
============================

-------------------------------------------------------------------------------
Required properties:
- compatible			: Should be one of
					"lantiq,xrx200-fpi"
- reg				: The address and length of the XBAR
				  configuration register.
				  Address and length of the FPI bus itself.
- lantiq,rcu			: A phandle to the RCU syscon
- lantiq,offset-endianness	: Offset of the endianness configuration
				  register

-------------------------------------------------------------------------------
Example for the FPI on the xrx200 SoCs:
	fpi@10000000 {
		compatible = "lantiq,xrx200-fpi";
		ranges = <0x0 0x10000000 0xf000000>;
		reg =	<0x1f400000 0x1000>,
			<0x10000000 0xf000000>;
		lantiq,rcu = <&rcu0>;
		lantiq,offset-endianness = <0x4c>;
		#address-cells = <1>;
		#size-cells = <1>;

		gptu@e100a00 {
			......
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/lantiq/lantiq,cgu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Lantiq Xway SoC series Clock Generation Unit (CGU)

maintainers:
  - John Crispin <john@phrozen.org>

properties:
  compatible:
    items:
      - enum:
          - lantiq,cgu-xway

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    cgu@103000 {
        compatible = "lantiq,cgu-xway";
        reg = <0x103000 0x1000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/lantiq/lantiq,dma-xway.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Lantiq Xway SoCs DMA Controller DT bindings

maintainers:
  - John Crispin <john@phrozen.org>

properties:
  compatible:
    items:
      - enum:
          - lantiq,dma-xway

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    dma@e104100 {
        compatible = "lantiq,dma-xway";
        reg = <0xe104100 0x800>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/lantiq/lantiq,ebu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Lantiq Xway SoC series External Bus Unit (EBU)

maintainers:
  - John Crispin <john@phrozen.org>

properties:
  compatible:
    items:
      - enum:
          - lantiq,ebu-xway

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    ebu@105300 {
        compatible = "lantiq,ebu-xway";
        reg = <0x105300 0x100>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/lantiq/lantiq,pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Lantiq Xway SoC series Power Management Unit (PMU)

maintainers:
  - John Crispin <john@phrozen.org>

properties:
  compatible:
    items:
      - enum:
          - lantiq,pmu-xway

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pmu@102000 {
        compatible = "lantiq,pmu-xway";
        reg = <0x102000 0x1000>;
    };


code:
Lantiq XWAY SoC RCU binding
===========================

This binding describes the RCU (reset controller unit) multifunction device,
where each sub-device has its own set of registers.

The RCU register range is used for multiple purposes. Mostly one device
uses one or multiple register exclusively, but for some registers some
bits are for one driver and some other bits are for a different driver.
With this patch all accesses to the RCU registers will go through
syscon.

-------------------------------------------------------------------------------
Required properties:
- compatible	: The first and second values must be:
		  "lantiq,xrx200-rcu", "simple-mfd", "syscon"
- reg		: The address and length of the system control registers

-------------------------------------------------------------------------------
Example of the RCU bindings on a xRX200 SoC:
	rcu0: rcu@203000 {
		compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
		reg = <0x203000 0x100>;
		ranges = <0x0 0x203000 0x100>;
		big-endian;

		reset0: reset-controller@10 {
			compatible = "lantiq,xrx200-reset";
			reg = <0x10 4>, <0x14 4>;

			#reset-cells = <2>;
		};

		reset1: reset-controller@48 {
			compatible = "lantiq,xrx200-reset";
			reg = <0x48 4>, <0x24 4>;

			#reset-cells = <2>;
		};

		usb_phy0: usb2-phy@18 {
			compatible = "lantiq,xrx200-usb2-phy";
			reg = <0x18 4>, <0x38 4>;

			resets = <&reset1 4 4>, <&reset0 4 4>;
			reset-names = "phy", "ctrl";
			#phy-cells = <0>;
		};

		usb_phy1: usb2-phy@34 {
			compatible = "lantiq,xrx200-usb2-phy";
			reg = <0x34 4>, <0x3C 4>;

			resets = <&reset1 5 4>, <&reset0 4 4>;
			reset-names = "phy", "ctrl";
			#phy-cells = <0>;
		};

		reboot@10 {
			compatible = "syscon-reboot";
			reg = <0x10 4>;

			regmap = <&rcu0>;
			offset = <0x10>;
			mask = <0x40000000>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Loongson based Platforms Device Tree Bindings

maintainers:
  - Jiaxun Yang <jiaxun.yang@flygoat.com>
description: |
  Devices with a Loongson CPU shall have the following properties.

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:

      - description: Classic Loongson64 Quad Core + LS7A
        items:
          - const: loongson,loongson64c-4core-ls7a

      - description: Classic Loongson64 Quad Core + RS780E
        items:
          - const: loongson,loongson64c-4core-rs780e

      - description: Classic Loongson64 Octa Core + RS780E
        items:
          - const: loongson,loongson64c-8core-rs780e

      - description: Generic Loongson64 Quad Core + LS7A
        items:
          - const: loongson,loongson64g-4core-ls7a

      - description: Virtual Loongson64 Quad Core + VirtIO
        items:
          - const: loongson,loongson64v-4core-virtio

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mips/loongson/ls2k-reset.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Loongson 2K1000 PM Controller

maintainers:
  - Qing Zhang <zhangqing@loongson.cn>

description: |
  This controller can be found in Loongson-2K1000 Soc systems.

properties:
  compatible:
    const: loongson,ls2k-pm

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    bus {
        #address-cells = <2>;
        #size-cells = <2>;
        pm: reset-controller@1fe07000 {
            compatible = "loongson,ls2k-pm";
            reg = <0 0x1fe07000 0 0x422>;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mips/loongson/rs780e-acpi.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Loongson RS780E PCH ACPI Controller

maintainers:
  - Jiaxun Yang <jiaxun.yang@flygoat.com>

description: |
  This controller can be found in Loongson-3 systems with RS780E PCH.

properties:
  compatible:
    const: loongson,rs780e-acpi

  reg:
    maxItems: 1

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    isa@0 {
      compatible = "isa";
      #address-cells = <2>;
      #size-cells = <1>;
      ranges = <1 0 0 0x1000>;

      acpi@800 {
        compatible = "loongson,rs780e-acpi";
        reg = <1 0x800 0x100>;
      };
    };

...


code:
* Microsemi MIPS CPUs

Boards with a SoC of the Microsemi MIPS family shall have the following
properties:

Required properties:
- compatible: "mscc,ocelot", "mscc,luton", "mscc,serval" or "mscc,jr2"

* Other peripherals:

o CPU chip regs:

The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
functionalities: chip ID, general purpose register for software use, reset
controller, hardware status and configuration, efuses.

Required properties:
- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
- reg : Should contain registers location and length

Example:
	syscon@71070000 {
		compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
		reg = <0x71070000 0x1c>;
	};

o CPU system control:

The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
endianness, CPU bus control, CPU status.

Required properties:
- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
- reg : Should contain registers location and length

Example:
	syscon@70000000 {
		compatible = "mscc,ocelot-cpu-syscon", "syscon";
		reg = <0x70000000 0x2c>;
	};

o HSIO regs:

The SoC has a few registers (HSIO) handling miscellaneous functionalities:
configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
status, SerDes muxing and a thermal sensor.

Required properties:
- compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
- reg : Should contain registers location and length

Example:
	syscon@10d0000 {
		compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
		reg = <0x10d0000 0x10000>;
	};


code:
National Instruments MIPS platforms

required root node properties:
	- compatible: must be "ni,169445"

CPU Nodes
	- compatible: must be "mti,mips14KEc"


code:
* Microchip PIC32MZDA Platforms

PIC32MZDA Starter Kit
Required root node properties:
    - compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda"

CPU nodes:
----------
A "cpus" node is required.  Required properties:
 - #address-cells: Must be 1.
 - #size-cells: Must be 0.
A CPU sub-node is also required.  Required properties:
 - device_type: Must be "cpu".
 - compatible: Must be "mti,mips14KEc".
Example:
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "mti,mips14KEc";
		};
	};

Boot protocol
--------------
In accordance with Unified Hosting Interface Reference Manual (MD01069), the
bootloader must pass the following arguments to the kernel:
 - $a0: -2.
 - $a1: KSEG0 address of the flattened device-tree blob.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/ralink.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ralink SoC based Platforms

maintainers:
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

description: |
    Boards with a Ralink SoC shall have the following properties.

properties:
  $nodename:
    const: '/'
  compatible:
    oneOf:
      - description: Boards with Ralink RT2880 SoC
        items:
          - enum:
              - ralink,rt2880-eval-board
          - const: ralink,rt2880-soc

      - description: Boards with Ralink RT3050 SoC
        items:
          - const: ralink,rt3050-soc

      - description: Boards with Ralink RT3052 SoC
        items:
          - enum:
              - ralink,rt3052-eval-board
          - const: ralink,rt3052-soc

      - description: Boards with Ralink RT3350 SoC
        items:
          - const: ralink,rt3350-soc

      - description: Boards with Ralink RT3352 SoC
        items:
          - const: ralink,rt3352-soc

      - description: Boards with Ralink RT3383 SoC
        items:
          - enum:
              - ralink,rt3883-eval-board
          - const: ralink,rt3383-soc

      - description: Boards with Ralink RT5350 SoC
        items:
          - const: ralink,rt5350-soc

      - description: Boards with Mediatek/Ralink MT7620A SoC
        items:
          - enum:
              - ralink,mt7620a-eval-board
          - const: ralink,mt7620a-soc

      - description: Boards with Mediatek/Ralink MT7620N SoC
        items:
          - const: ralink,mt7620n-soc

      - description: Boards with Mediatek/Ralink MT7628A SoC
        items:
          - enum:
              - onion,omega2+
              - vocore,vocore2
          - const: ralink,mt7628a-soc

      - description: Boards with Mediatek/Ralink MT7688A SoC
        items:
          - enum:
              - gardena,smart-gateway-mt7688
              - onion,omega2+
          - const: ralink,mt7628a-soc

      - description: Boards with Mediatek/Ralink MT7621 SoC
        items:
          - enum:
              - gnubee,gb-pc1
              - gnubee,gb-pc2
          - const: mediatek,mt7621-soc

additionalProperties: true

...


code:
# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/realtek-rtl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Realtek RTL83xx/93xx SoC series

maintainers:
  - Bert Vermeulen <bert@biot.com>
  - Sander Vanheule <sander@svanheule.net>

properties:
  $nodename:
    const: "/"
  compatible:
    oneOf:
      # RTL8382-based boards
      - items:
          - enum:
              - cisco,sg220-26
          - const: realtek,rtl8382-soc

additionalProperties: true


code:
* ASPEED AST2400 and AST2500 coprocessor interrupt controller

This file describes the bindings for the interrupt controller present
in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
ColdFire coprocessor.

It is not a normal interrupt controller and it would be rather
inconvenient to create an interrupt tree for it as it somewhat shares
some of the same sources as the main ARM interrupt controller but with
different numbers.

The AST2500 supports a SW generated interrupt

Required properties:
- reg: address and length of the register for the device.
- compatible: "aspeed,cvic" and one of:
		"aspeed,ast2400-cvic"
	      or
		"aspeed,ast2500-cvic"

- valid-sources: One cell, bitmap of supported sources for the implementation

Optional properties;
- copro-sw-interrupts: List of interrupt numbers that can be used as
		       SW interrupts from the ARM to the coprocessor.
		       (AST2500 only)

Example:

	cvic: copro-interrupt-controller@1e6c2000 {
		compatible = "aspeed,ast2500-cvic";
		valid-sources = <0xffffffff>;
		copro-sw-interrupts = <1>;
		reg = <0x1e6c2000 0x80>;
	};


code:
======================================================================
Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver
======================================================================

The bridge is available on platforms with the VGA enabled on the Aspeed device.
In this case, the host has access to a 64KiB window into all of the BMC's
memory.  The BMC can disable this bridge.  If the bridge is enabled, the host
has read access to all the regions of memory, however the host only has read
and write access depending on a register controlled by the BMC.

Required properties:
===================

 - compatible: must be one of:
	- "aspeed,ast2400-p2a-ctrl"
	- "aspeed,ast2500-p2a-ctrl"

Optional properties:
===================

- reg: A hint for the memory regions associated with the P2A controller
- memory-region: A phandle to a reserved_memory region to be used for the PCI
		to AHB mapping

The p2a-control node should be the child of a syscon node with the required
property:

- compatible : Should be one of the following:
		"aspeed,ast2400-scu", "syscon", "simple-mfd"
		"aspeed,ast2500-scu", "syscon", "simple-mfd"

Example
===================

g4 Example
----------

syscon: scu@1e6e2000 {
	compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
	reg = <0x1e6e2000 0x1a8>;

	p2a: p2a-control {
		compatible = "aspeed,ast2400-p2a-ctrl";
		memory-region = <&reserved_memory>;
	};
};


code:
* Atmel SSC driver.

Required properties:
- compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
	- atmel,at91rm9200-ssc: support pdc transfer
	- atmel,at91sam9g45-ssc: support dma transfer
- reg: Should contain SSC registers location and length
- interrupts: Should contain SSC interrupt
- clock-names: tuple listing input clock names.
	Required elements: "pclk"
- clocks: phandles to input clocks.

Required properties for devices compatible with "atmel,at91sam9g45-ssc":
- dmas: DMA specifier, consisting of a phandle to DMA controller node,
  the memory interface and SSC DMA channel ID (for tx and rx).
  See Documentation/devicetree/bindings/dma/atmel-dma.txt for details.
- dma-names: Must be "tx", "rx".

Optional properties:
  - atmel,clk-from-rk-pin: bool property.
     - When SSC works in slave mode, according to the hardware design, the
       clock can get from TK pin, and also can get from RK pin. So, add
       this parameter to choose where the clock from.
     - By default the clock is from TK pin, if the clock from RK pin, this
       property is needed.
  - #sound-dai-cells: Should contain <0>.
     - This property makes the SSC into an automatically registered DAI.

Examples:
- PDC transfer:
ssc0: ssc@fffbc000 {
	compatible = "atmel,at91rm9200-ssc";
	reg = <0xfffbc000 0x4000>;
	interrupts = <14 4 5>;
	clocks = <&ssc0_clk>;
	clock-names = "pclk";
};

- DMA transfer:
ssc0: ssc@f0010000 {
      compatible = "atmel,at91sam9g45-ssc";
      reg = <0xf0010000 0x4000>;
      interrupts = <28 4 5>;
      dmas = <&dma0 1 13>,
	     <&dma0 1 14>;
      dma-names = "tx", "rx";
      pinctrl-names = "default";
      pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
};


code:
Broadcom Secure Monitor Bounce buffer
-----------------------------------------------------
This binding defines the location of the bounce buffer
used for non-secure to secure communications.

Required properties:
- compatible : "brcm,kona-smc"
- DEPRECATED: compatible : "bcm,kona-smc"
- reg : Location and size of bounce buffer

Example:
	smc@3404c000 {
		compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
		reg = <0x3404c000 0x400>; //1 KiB in SRAM
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/fsl,dpaa2-console.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DPAA2 console support

maintainers:
  - Laurentiu Tudor <laurentiu.tudor@nxp.com>

properties:
  compatible:
    const: "fsl,dpaa2-console"

  reg:
    maxItems: 1
    description: A standard property. Specifies the region where the MCFBA
                (MC firmware base address) register can be found.

required:
  - compatible
  - reg

additionalProperties: false


code:
* Freescale Management Complex

The Freescale Management Complex (fsl-mc) is a hardware resource
manager that manages specialized hardware objects used in
network-oriented packet processing applications. After the fsl-mc
block is enabled, pools of hardware resources are available, such as
queues, buffer pools, I/O interfaces. These resources are building
blocks that can be used to create functional hardware objects/devices
such as network interfaces, crypto accelerator instances, L2 switches,
etc.

For an overview of the DPAA2 architecture and fsl-mc bus see:
Documentation/networking/device_drivers/ethernet/freescale/dpaa2/overview.rst

As described in the above overview, all DPAA2 objects in a DPRC share the
same hardware "isolation context" and a 10-bit value called an ICID
(isolation context id) is expressed by the hardware to identify
the requester.

The generic 'iommus' property is insufficient to describe the relationship
between ICIDs and IOMMUs, so an iommu-map property is used to define
the set of possible ICIDs under a root DPRC and how they map to
an IOMMU.

For generic IOMMU bindings, see
Documentation/devicetree/bindings/iommu/iommu.txt.

For arm-smmu binding, see:
Documentation/devicetree/bindings/iommu/arm,smmu.yaml.

The MSI writes are accompanied by sideband data which is derived from the ICID.
The msi-map property is used to associate the devices with both the ITS
controller and the sideband data which accompanies the writes.

For generic MSI bindings, see
Documentation/devicetree/bindings/interrupt-controller/msi.txt.

For GICv3 and GIC ITS bindings, see:
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.

Required properties:

    - compatible
        Value type: <string>
        Definition: Must be "fsl,qoriq-mc".  A Freescale Management Complex
                    compatible with this binding must have Block Revision
                    Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
                    the MC control register region.

    - reg
        Value type: <prop-encoded-array>
        Definition: A standard property.  Specifies one or two regions
                    defining the MC's registers:

                       -the first region is the command portal for the
                        this machine and must always be present

                       -the second region is the MC control registers. This
                        region may not be present in some scenarios, such
                        as in the device tree presented to a virtual machine.

    - ranges
        Value type: <prop-encoded-array>
        Definition: A standard property.  Defines the mapping between the child
                    MC address space and the parent system address space.

                    The MC address space is defined by 3 components:
                       <region type> <offset hi> <offset lo>

                    Valid values for region type are
                       0x0 - MC portals
                       0x1 - QBMAN portals

    - #address-cells
        Value type: <u32>
        Definition: Must be 3.  (see definition in 'ranges' property)

    - #size-cells
        Value type: <u32>
        Definition: Must be 1.

Sub-nodes:

        The fsl-mc node may optionally have dpmac sub-nodes that describe
        the relationship between the Ethernet MACs which belong to the MC
        and the Ethernet PHYs on the system board.

        The dpmac nodes must be under a node named "dpmacs" which contains
        the following properties:

            - #address-cells
              Value type: <u32>
              Definition: Must be present if dpmac sub-nodes are defined and must
                          have a value of 1.

            - #size-cells
              Value type: <u32>
              Definition: Must be present if dpmac sub-nodes are defined and must
                          have a value of 0.

        These nodes must have the following properties:

            - compatible
              Value type: <string>
              Definition: Must be "fsl,qoriq-mc-dpmac".

            - reg
              Value type: <prop-encoded-array>
              Definition: Specifies the id of the dpmac.

            - phy-handle
              Value type: <phandle>
              Definition: Specifies the phandle to the PHY device node associated
                          with the this dpmac.
Optional properties:

- iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier
  data.

  The property is an arbitrary number of tuples of
  (icid-base,iommu,iommu-base,length).

  Any ICID i in the interval [icid-base, icid-base + length) is
  associated with the listed IOMMU, with the iommu-specifier
  (i - icid-base + iommu-base).

- msi-map: Maps an ICID to a GIC ITS and associated msi-specifier
  data.

  The property is an arbitrary number of tuples of
  (icid-base,gic-its,msi-base,length).

  Any ICID in the interval [icid-base, icid-base + length) is
  associated with the listed GIC ITS, with the msi-specifier
  (i - icid-base + msi-base).

Deprecated properties:

    - msi-parent
        Value type: <phandle>
        Definition: Describes the MSI controller node handling message
                    interrupts for the MC. When there is no translation
                    between the ICID and deviceID this property can be used
                    to describe the MSI controller used by the devices on the
                    mc-bus.
                    The use of this property for mc-bus is deprecated. Please
                    use msi-map.

Example:

        smmu: iommu@5000000 {
               compatible = "arm,mmu-500";
               #iommu-cells = <1>;
               stream-match-mask = <0x7C00>;
               ...
        };

        gic: interrupt-controller@6000000 {
               compatible = "arm,gic-v3";
               ...
        }
        its: gic-its@6020000 {
               compatible = "arm,gic-v3-its";
               msi-controller;
               ...
        };

        fsl_mc: fsl-mc@80c000000 {
                compatible = "fsl,qoriq-mc";
                reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
                      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
                /* define map for ICIDs 23-64 */
                iommu-map = <23 &smmu 23 41>;
                /* define msi map for ICIDs 23-64 */
                msi-map = <23 &its 23 41>;
                #address-cells = <3>;
                #size-cells = <1>;

                /*
                 * Region type 0x0 - MC portals
                 * Region type 0x1 - QBMAN portals
                 */
                ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
                          0x1 0x0 0x0 0x8 0x18000000 0x8000000>;

                dpmacs {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    dpmac@1 {
                        compatible = "fsl,qoriq-mc-dpmac";
                        reg = <1>;
                        phy-handle = <&mdio0_phy0>;
                    }
                }
        };


code:
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
# Copyright (C) 2021 GE Inc.
# Copyright (C) 2021 Collabora Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/ge-achc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: GE Healthcare USB Management Controller

description: |
  A device which handles data acquisition from compatible USB based peripherals.
  SPI is used for device management.

  Note: This device does not expose the peripherals as USB devices.

maintainers:
  - Sebastian Reichel <sre@kernel.org>

properties:
  compatible:
    items:
      - const: ge,achc
      - const: nxp,kinetis-k20

  clocks:
    maxItems: 1

  vdd-supply:
    description: Digital power supply regulator on VDD pin

  vdda-supply:
    description: Analog power supply regulator on VDDA pin

  reg:
    items:
      - description: Control interface
      - description: Firmware programming interface

  reset-gpios:
    description: GPIO used for hardware reset.
    maxItems: 1

required:
  - compatible
  - clocks
  - reg
  - reset-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    spi {
        #address-cells = <1>;
        #size-cells = <0>;

        spi@1 {
            compatible = "ge,achc", "nxp,kinetis-k20";
            reg = <1>, <0>;
            clocks = <&achc_24M>;
            reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/idt,89hpesx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

select:
  properties:
    compatible:
      contains:
        pattern: '^idt,89hpes'
  required:
    - compatible

properties:
  compatible:
    oneOf:
      - pattern: '^idt,89hpes(8nt2|12nt3|12n3a?|24n3a?|(12|24)t3g2|4t4g2|10t4g2|[56]t5|8t5a?)$'
      - pattern: '^idt,89hpes(6t6g2|16t7|(24t6|32t8|48t12|16t4a?)(g2)?)$'
      - pattern: '^idt,89hpes(24nt6a|32nt8[ab]|12nt12|16nt16|24nt24|32nt24[ab])g2$'
      - pattern: '^idt,89hpes((32h8|48h12a?|22h16|34h16|64h16a?)(g2)?|16h16)$'

  reg:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

patternProperties:
  '^eeprom@':
    $ref: /schemas/eeprom/at24.yaml#
    unevaluatedProperties: false

    properties:
      compatible:
        description: Only a subset of devices are supported
        pattern: ',24c(32|64|128|256|512)$'

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    i2c {
        #address-cells = <1>;
        #size-cells = <0>;

        idt@74 {
            compatible = "idt,89hpes32nt8ag2";
            reg = <0x74>;
            #address-cells = <1>;
            #size-cells = <0>;

            eeprom@50 {
                compatible = "atmel,24c64";
                reg = <0x50>;
                read-only;
            };
        };
    };
...


code:
IFM camera sensor interface on mpc5200 LocalPlus bus

Required properties:
- compatible: "ifm,o2d-csi"
- reg: specifies sensor chip select number and associated address range
- interrupts: external interrupt line number and interrupt sense mode
  of the interrupt line signaling frame valid events
- gpios: three gpio-specifiers for "capture", "reset" and "master enable"
  GPIOs (strictly in this order).
- ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
  clock generator. This node is usually a general purpose timer controller.
- ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
- ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
- ifm,csi-wait-cycles: sensor bus wait cycles

Optional properties:
- ifm,csi-byte-swap: if this property is present, the byte swapping on
  the bus will be enabled.

Example:

	csi@3,0 {
		compatible = "ifm,o2d-csi";
		reg = <3 0 0x00100000>;		/* CS 3, 1 MiB range */
		interrupts = <1 1 2>;		/* IRQ1, edge falling */

		ifm,csi-clk-handle = <&timer7>;
		gpios = <&gpio_simple 23 0	/* image_capture */
			 &gpio_simple 26 0	/* image_reset */
			 &gpio_simple 29 0>;	/* image_master_en */

		ifm,csi-addr-bus-width = <24>;
		ifm,csi-data-bus-width = <8>;
		ifm,csi-wait-cycles = <0>;
	};

The base address of the used chip select is specified in the
ranges property of the parent localbus node, for example:

	ranges = <0 0 0xff000000 0x01000000
		  3 0 0xe3000000 0x00100000>;


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Intel IXP4xx AHB Queue Manager

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

description: |
  The IXP4xx AHB Queue Manager maintains queues as circular buffers in
  an 8KB embedded SRAM along with hardware pointers. It is used by both
  the XScale processor and the NPEs (Network Processing Units) in the
  IXP4xx for accelerating queues, especially for networking. Clients pick
  queues from the queue manager with foo-queue = <&qmgr N> where the
  &qmgr is a phandle to the queue manager and N is the queue resource
  number. The queue resources available and their specific purpose
  on a certain IXP4xx system will vary.

properties:
  compatible:
    items:
      - const: intel,ixp4xx-ahb-queue-manager

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: Interrupt for queues 0-31
      - description: Interrupt for queues 32-63

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    qmgr: queue-manager@60000000 {
         compatible = "intel,ixp4xx-ahb-queue-manager";
         reg = <0x60000000 0x4000>;
         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
    };


code:
* Liebherr's BK4 controller external SPI

A device which handles data acquisition from compatible industrial
peripherals.
The SPI is used for data and management purposes in both master and
slave modes.

Required properties:

- compatible : Should be "lwn,bk4"

Required SPI properties:

- reg : Should be address of the device chip select within
  the controller.

- spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
  30MHz at most for the Liebherr's BK4 external bus.

Example:

spidev0: spi@0 {
	compatible = "lwn,bk4";
	spi-max-frequency = <30000000>;
	reg = <0>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra186 (and later) MISC register block

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

description: The MISC register block found on Tegra186 and later SoCs contains
  registers that can be used to identify a given chip and various strapping
  options.

properties:
  compatible:
    enum:
      - nvidia,tegra186-misc
      - nvidia,tegra194-misc
      - nvidia,tegra234-misc

  reg:
    items:
      - description: physical address and length of the registers which
          contain revision and debug features
      - description: physical address and length of the registers which
          indicate strapping options

additionalProperties: false

required:
  - compatible
  - reg

examples:
  - |
    misc@100000 {
        compatible = "nvidia,tegra186-misc";
        reg = <0x00100000 0xf000>,
              <0x0010f000 0x1000>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra APBMISC block

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - nvidia,tegra210-apbmisc
              - nvidia,tegra124-apbmisc
              - nvidia,tegra114-apbmisc
              - nvidia,tegra30-apbmisc
          - const: nvidia,tegra20-apbmisc

      - items:
          - const: nvidia,tegra20-apbmisc

  reg:
    items:
      - description: physical address and length of the registers which
          contain revision and debug features
      - description: physical address and length of the registers which
          indicate strapping options

  nvidia,long-ram-code:
    description: If present, the RAM code is long (4 bit). If not, short
      (2 bit).
    type: boolean

additionalProperties: false

required:
  - compatible
  - reg

examples:
  - |
    apbmisc@70000800 {
        compatible = "nvidia,tegra20-apbmisc";
        reg = <0x70000800 0x64>, /* Chip revision */
              <0x70000008 0x04>; /* Strapping options */
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (C) 2019,2020 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/olpc,xo1.75-ec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: OLPC XO-1.75 Embedded Controller bindings

description: |
  This binding describes the Embedded Controller acting as a SPI bus master
  on a OLPC XO-1.75 laptop computer.

  The embedded controller requires the SPI controller driver to signal
  readiness to receive a transfer (that is, when TX FIFO contains the
  response data) by strobing the ACK pin with the ready signal. See the
  "ready-gpios" property of the SSP binding as documented in:
  <Documentation/devicetree/bindings/spi/marvell,mmp2-ssp.yaml>.

maintainers:
  - Lubomir Rintel <lkundrak@v3.sk>

properties:
  compatible:
    const: olpc,xo1.75-ec

  cmd-gpios:
    description: GPIO uspecifier of the CMD pin
    maxItems: 1

  spi-cpha: true

required:
  - compatible
  - cmd-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    spi {
      spi-slave;
      #address-cells = <0>;
      #size-cells = <0>;
      ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>;

      slave {
        compatible = "olpc,xo1.75-ec";
        spi-cpha;
        cmd-gpios = <&gpio 155 GPIO_ACTIVE_HIGH>;
      };
    };

...


code:
* QEMU PVPANIC MMIO Configuration bindings

QEMU's emulation / virtualization targets provide the following PVPANIC
MMIO Configuration interface on the "virt" machine.
type:

- a read-write, 16-bit wide data register.

QEMU exposes the data register to guests as memory mapped registers.

Required properties:

- compatible: "qemu,pvpanic-mmio".
- reg: the MMIO region used by the device.
  * Bytes 0x0  Write panic event to the reg when guest OS panics.
  * Bytes 0x1  Reserved.

Example:

/ {
        #size-cells = <0x2>;
        #address-cells = <0x2>;

        pvpanic-mmio@9060000 {
                compatible = "qemu,pvpanic-mmio";
                reg = <0x0 0x9060000 0x0 0x2>;
        };
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/qcom,fastrpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm FastRPC Driver

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

description: |
  The FastRPC implements an IPC (Inter-Processor Communication)
  mechanism that allows for clients to transparently make remote method
  invocations across DSP and APPS boundaries. This enables developers
  to offload tasks to the DSP and free up the application processor for
  other tasks.

properties:
  compatible:
    const: qcom,fastrpc

  label:
    enum:
      - adsp
      - mdsp
      - sdsp
      - cdsp

  memory-region:
    maxItems: 1
    description:
      Phandle to a node describing memory to be used for remote heap CMA.

  qcom,glink-channels:
    description:
      A list of channels tied to this function, used for matching
      the function to a set of virtual channels.
    $ref: "/schemas/types.yaml#/definitions/string-array"
    items:
      - const: fastrpcglink-apps-dsp

  qcom,non-secure-domain:
    description:
      Used to mark the current domain as non-secure.
    type: boolean

  qcom,smd-channels:
    description:
      Channel name used for the RPM communication
    $ref: "/schemas/types.yaml#/definitions/string-array"
    items:
      - const: fastrpcsmd-apps-dsp

  qcom,vmids:
    description:
      Virtual machine IDs for remote processor.
    $ref: "/schemas/types.yaml#/definitions/uint32-array"

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

patternProperties:
  "(compute-)?cb@[0-9]*$":
    type: object

    description: >
      Each subnode of the Fastrpc represents compute context banks available on the dsp.

    properties:
      compatible:
        const: qcom,fastrpc-compute-cb

      reg:
        maxItems: 1

      iommus:
        minItems: 1
        maxItems: 3

      qcom,nsessions:
        $ref: /schemas/types.yaml#/definitions/uint32
        default: 1
        description: >
          A value indicating how many sessions can share this context bank.

    required:
      - compatible
      - reg

    additionalProperties: false

required:
  - compatible
  - label
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/mailbox/qcom-ipcc.h>

    glink-edge {
        interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
                                     IPCC_MPROC_SIGNAL_GLINK_QMP
                                     IRQ_TYPE_EDGE_RISING>;
        mboxes = <&ipcc IPCC_CLIENT_LPASS
                        IPCC_MPROC_SIGNAL_GLINK_QMP>;
        label = "lpass";
        qcom,remote-pid = <2>;

        fastrpc {
            compatible = "qcom,fastrpc";
            qcom,glink-channels = "fastrpcglink-apps-dsp";
            label = "sdsp";
            qcom,non-secure-domain;
            #address-cells = <1>;
            #size-cells = <0>;

            compute-cb@1 {
                compatible = "qcom,fastrpc-compute-cb";
                reg = <1>;
                iommus = <&apps_smmu 0x0541 0x0>;
            };

            compute-cb@2 {
                compatible = "qcom,fastrpc-compute-cb";
                reg = <2>;
                iommus = <&apps_smmu 0x0542 0x0>;
            };

            compute-cb@3 {
                compatible = "qcom,fastrpc-compute-cb";
                reg = <3>;
                iommus = <&apps_smmu 0x0543 0x0>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/qemu,vcpu-stall-detector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: VCPU stall detector

description:
  This binding describes a CPU stall detector mechanism for virtual CPUs
  which is accessed through MMIO.

maintainers:
  - Sebastian Ene <sebastianene@google.com>

properties:
  compatible:
    enum:
      - qemu,vcpu-stall-detector

  reg:
    maxItems: 1

  clock-frequency:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      The internal clock of the stall detector peripheral measure in Hz used
      to decrement its internal counter register on each tick.
      Defaults to 10 if unset.
    default: 10

  timeout-sec:
    description: |
      The stall detector expiration timeout measured in seconds.
      Defaults to 8 if unset. Please note that it also takes into account the
      time spent while the VCPU is not running.
    default: 8

required:
  - compatible

additionalProperties: false

examples:
  - |
    vmwdt@9030000 {
      compatible = "qemu,vcpu-stall-detector";
      reg = <0x9030000 0x10000>;
      clock-frequency = <10>;
      timeout-sec = <8>;
    };


code:
* Xilinx SDFEC(16nm) IP *

The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
which provides high-throughput LDPC and Turbo Code implementations.
The LDPC decode & encode functionality is capable of covering a range of
customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
principally covers codes used by LTE. The FEC Engine offers significant
power and area savings versus implementations done in the FPGA fabric.

Required properties:
- compatible: Must be "xlnx,sd-fec-1.1"
- clock-names : List of input clock names from the following:
    - "core_clk", Main processing clock for processing core (required)
    - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
    - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
    - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
    - "s_axis_ctrl_aclk",  Control input AXI4-Stream Slave interface clock (optional)
    - "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional)
    - "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional)
    - "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional)
- clocks : Clock phandles (see clock_bindings.txt for details).
- reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers
  location and length.
- xlnx,sdfec-code : Should contain "ldpc" or "turbo" to describe the codes
  being used.
- xlnx,sdfec-din-words : A value 0 indicates that the DIN_WORDS interface is
  driven with a fixed value and is not present on the device, a value of 1
  configures the DIN_WORDS to be block based, while a value of 2 configures the
  DIN_WORDS input to be supplied for each AXI transaction.
- xlnx,sdfec-din-width : Configures the DIN AXI stream where a value of 1
  configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
  of "4x128b".
- xlnx,sdfec-dout-words : A value 0 indicates that the DOUT_WORDS interface is
  driven with a fixed value and is not present on the device, a value of 1
  configures the DOUT_WORDS to be block based, while a value of 2 configures the
  DOUT_WORDS input to be supplied for each AXI transaction.
- xlnx,sdfec-dout-width : Configures the DOUT AXI stream where a value of 1
  configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
  of "4x128b".
Optional properties:
- interrupts: should contain SDFEC interrupt number

Example
---------------------------------------
	sd_fec_0: sd-fec@a0040000 {
		compatible = "xlnx,sd-fec-1.1";
		clock-names = "core_clk","s_axi_aclk","s_axis_ctrl_aclk","s_axis_din_aclk","m_axis_status_aclk","m_axis_dout_aclk";
		clocks = <&misc_clk_2>,<&misc_clk_0>,<&misc_clk_1>,<&misc_clk_1>,<&misc_clk_1>, <&misc_clk_1>;
		reg = <0x0 0xa0040000 0x0 0x40000>;
		interrupt-parent = <&axi_intc>;
		interrupts = <1 0>;
		xlnx,sdfec-code = "ldpc";
		xlnx,sdfec-din-words = <0>;
		xlnx,sdfec-din-width = <2>;
		xlnx,sdfec-dout-words = <0>;
		xlnx,sdfec-dout-width = <1>;
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/allwinner,sun4i-a10-mmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 MMC Controller

allOf:
  - $ref: "mmc-controller.yaml"

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#address-cells": true
  "#size-cells": true

  compatible:
    oneOf:
      - const: allwinner,sun4i-a10-mmc
      - const: allwinner,sun5i-a13-mmc
      - const: allwinner,sun7i-a20-mmc
      - const: allwinner,sun8i-a83t-emmc
      - const: allwinner,sun9i-a80-mmc
      - const: allwinner,sun20i-d1-mmc
      - const: allwinner,sun50i-a64-emmc
      - const: allwinner,sun50i-a64-mmc
      - const: allwinner,sun50i-a100-emmc
      - const: allwinner,sun50i-a100-mmc
      - items:
          - const: allwinner,sun8i-a83t-mmc
          - const: allwinner,sun7i-a20-mmc
      - items:
          - const: allwinner,sun8i-r40-emmc
          - const: allwinner,sun50i-a64-emmc
      - items:
          - const: allwinner,sun8i-r40-mmc
          - const: allwinner,sun50i-a64-mmc
      - items:
          - const: allwinner,sun50i-h5-emmc
          - const: allwinner,sun50i-a64-emmc
      - items:
          - const: allwinner,sun50i-h5-mmc
          - const: allwinner,sun50i-a64-mmc
      - items:
          - const: allwinner,sun50i-h6-emmc
          - const: allwinner,sun50i-a64-emmc
      - items:
          - const: allwinner,sun50i-h6-mmc
          - const: allwinner,sun50i-a64-mmc
      - items:
          - const: allwinner,sun20i-d1-emmc
          - const: allwinner,sun50i-a100-emmc
      - items:
          - const: allwinner,sun50i-h616-emmc
          - const: allwinner,sun50i-a100-emmc
      - items:
          - const: allwinner,sun50i-h616-mmc
          - const: allwinner,sun50i-a100-mmc
      - items:
          - const: allwinner,suniv-f1c100s-mmc
          - const: allwinner,sun7i-a20-mmc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2
    items:
      - description: Bus Clock
      - description: Module Clock
      - description: Output Clock
      - description: Sample Clock

  clock-names:
    minItems: 2
    items:
      - const: ahb
      - const: mmc
      - const: output
      - const: sample

  resets:
    maxItems: 1

  reset-names:
    const: ahb

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    mmc0: mmc@1c0f000 {
        compatible = "allwinner,sun5i-a13-mmc";
        reg = <0x01c0f000 0x1000>;
        clocks = <&ahb_gates 8>, <&mmc0_clk>;
        clock-names = "ahb", "mmc";
        interrupts = <32>;
        bus-width = <4>;
        cd-gpios = <&pio 7 1 0>;
    };

...


code:
Amlogic SD / eMMC controller for S905/GXBB family SoCs

The MMC 5.1 compliant host controller on Amlogic provides the
interface for SD, eMMC and SDIO devices.

This file documents the properties in addition to those available in
the MMC core bindings, documented by mmc.txt.

Required properties:
- compatible : contains one of:
  - "amlogic,meson-gx-mmc"
  - "amlogic,meson-gxbb-mmc"
  - "amlogic,meson-gxl-mmc"
  - "amlogic,meson-gxm-mmc"
  - "amlogic,meson-axg-mmc"
- clocks     : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
- clock-names: Should contain the following:
	"core" - Main peripheral bus clock
	"clkin0" - Parent clock of internal mux
	"clkin1" - Other parent clock of internal mux
  The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
  clock rate requested by the MMC core.
- resets     : phandle of the internal reset line

Optional properties:
- amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
  DRAM memory, like on the G12A dedicated SDIO controller.

Example:

	sd_emmc_a: mmc@70000 {
		compatible = "amlogic,meson-gxbb-mmc";
		reg = <0x0 0x70000 0x0 0x2000>;
		interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
		clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
		clock-names = "core", "clkin0", "clkin1";
		pinctrl-0 = <&emmc_pins>;
		resets = <&reset RESET_SD_EMMC_A>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic Meson SDHC controller

allOf:
  - $ref: "mmc-controller.yaml"

maintainers:
  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>

description: |
  The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC
  card interface with 1/4/8-bit bus width.
  It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock).

properties:
  compatible:
    items:
      - enum:
          - amlogic,meson8-sdhc
          - amlogic,meson8b-sdhc
          - amlogic,meson8m2-sdhc
      - const: amlogic,meson-mx-sdhc

  reg:
    minItems: 1

  interrupts:
    minItems: 1

  clocks:
    minItems: 5

  clock-names:
    items:
      - const: clkin0
      - const: clkin1
      - const: clkin2
      - const: clkin3
      - const: pclk

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    sdhc: mmc@8e00 {
      compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
      reg = <0x8e00 0x42>;
      interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
      clocks = <&xtal>,
               <&fclk_div4>,
               <&fclk_div3>,
               <&fclk_div5>,
               <&sdhc_pclk>;
      clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
    };


code:
* Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller

The highspeed MMC host controller on Amlogic SoCs provides an interface
for MMC, SD, SDIO and SDHC types of memory cards.

Supported maximum speeds are the ones of the eMMC standard 4.41 as well
as the speed of SD standard 2.0.

The hardware provides an internal "mux" which allows up to three slots
to be controlled. Only one slot can be accessed at a time.

Required properties:
 - compatible : must be one of
	- "amlogic,meson8-sdio"
	- "amlogic,meson8b-sdio"
	along with the generic "amlogic,meson-mx-sdio"
 - reg : mmc controller base registers
 - interrupts : mmc controller interrupt
 - #address-cells : must be 1
 - size-cells : must be 0
 - clocks : phandle to clock providers
 - clock-names : must contain "core" and "clkin"

Required child nodes:
A node for each slot provided by the MMC controller is required.
NOTE: due to a driver limitation currently only one slot (= child node)
      is supported!

Required properties on each child node (= slot):
 - compatible : must be "mmc-slot" (see mmc.txt within this directory)
 - reg : the slot (or "port") ID

Optional properties on each child node (= slot):
 - bus-width : must be 1 or 4 (8-bit bus is not supported)
 - for cd and all other additional generic mmc parameters
   please refer to mmc.txt within this directory

Examples:
	mmc@c1108c20 {
		compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
		reg = <0xc1108c20 0x20>;
		interrupts = <0 28 1>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
		clock-names = "core", "clkin";

		slot@1 {
			compatible = "mmc-slot";
			reg = <1>;

			bus-width = <4>;
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Device Tree Bindings for the Arasan SDHCI Controller

maintainers:
  - Adrian Hunter <adrian.hunter@intel.com>

allOf:
  - $ref: "mmc-controller.yaml#"
  - if:
      properties:
        compatible:
          contains:
            const: arasan,sdhci-5.1
    then:
      required:
        - phys
        - phy-names
  - if:
      properties:
        compatible:
          contains:
            enum:
              - xlnx,zynqmp-8.9a
              - xlnx,versal-8.9a
    then:
      properties:
        clock-output-names:
          oneOf:
            - items:
                - const: clk_out_sd0
                - const: clk_in_sd0
            - items:
                - const: clk_out_sd1
                - const: clk_in_sd1

properties:
  compatible:
    oneOf:
      - const: arasan,sdhci-8.9a                # generic Arasan SDHCI 8.9a PHY
      - const: arasan,sdhci-4.9a                # generic Arasan SDHCI 4.9a PHY
      - const: arasan,sdhci-5.1                 # generic Arasan SDHCI 5.1 PHY
      - items:
          - const: rockchip,rk3399-sdhci-5.1    # rk3399 eMMC PHY
          - const: arasan,sdhci-5.1
        description:
          For this device it is strongly suggested to include
          arasan,soc-ctl-syscon.
      - items:
          - const: xlnx,zynqmp-8.9a             # ZynqMP SDHCI 8.9a PHY
          - const: arasan,sdhci-8.9a
        description:
          For this device it is strongly suggested to include
          clock-output-names and '#clock-cells'.
      - items:
          - const: xlnx,versal-8.9a             # Versal SDHCI 8.9a PHY
          - const: arasan,sdhci-8.9a
        description:
          For this device it is strongly suggested to include
          clock-output-names and '#clock-cells'.
      - items:
          - const: intel,lgm-sdhci-5.1-emmc     # Intel LGM eMMC PHY
          - const: arasan,sdhci-5.1
        description:
          For this device it is strongly suggested to include
          arasan,soc-ctl-syscon.
      - items:
          - const: intel,lgm-sdhci-5.1-sdxc     # Intel LGM SDXC PHY
          - const: arasan,sdhci-5.1
        description:
          For this device it is strongly suggested to include
          arasan,soc-ctl-syscon.
      - items:
          - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
          - const: arasan,sdhci-5.1
        description:
          For this device it is strongly suggested to include
          arasan,soc-ctl-syscon.
      - const: intel,keembay-sdhci-5.1-sd       # Intel Keem Bay SD controller
        description:
          For this device it is strongly suggested to include
          arasan,soc-ctl-syscon.
      - const: intel,keembay-sdhci-5.1-sdio     # Intel Keem Bay SDIO controller
        description:
          For this device it is strongly suggested to include
          arasan,soc-ctl-syscon.
      - items:
          - const: intel,thunderbay-sdhci-5.1   # Intel Thunder Bay eMMC PHY
          - const: arasan,sdhci-5.1
        description:
          For this device it is strongly suggested to include
          clock-output-names and '#clock-cells'.

  reg:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 3

  clock-names:
    minItems: 2
    items:
      - const: clk_xin
      - const: clk_ahb
      - const: gate

  interrupts:
    maxItems: 1

  phys:
    maxItems: 1

  phy-names:
    const: phy_arasan

  resets:
    maxItems: 1

  arasan,soc-ctl-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      A phandle to a syscon device (see ../mfd/syscon.txt) used to access
      core corecfg registers. Offsets of registers in this syscon are
      determined based on the main compatible string for the device.

  clock-output-names:
    minItems: 1
    maxItems: 2
    description:
      Name of the card clock which will be exposed by this device.

  '#clock-cells':
    enum: [0, 1]
    description:
      With this property in place we will export one or two clocks
      representing the Card Clock. These clocks are expected to be
      consumed by our PHY.

  xlnx,fails-without-test-cd:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      When present, the controller doesn't work when the CD line is not
      connected properly, and the line is not connected properly.
      Test mode can be used to force the controller to function.

  xlnx,int-clock-stable-broken:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      When present, the controller always reports that the internal clock
      is stable even when it is not.

  xlnx,mio-bank:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2]
    default: 0
    description:
      The MIO bank number in which the command and data lines are configured.

dependencies:
  '#clock-cells': [ clock-output-names ]

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    mmc@e0100000 {
          compatible = "arasan,sdhci-8.9a";
          reg = <0xe0100000 0x1000>;
          clock-names = "clk_xin", "clk_ahb";
          clocks = <&clkc 21>, <&clkc 32>;
          interrupt-parent = <&gic>;
          interrupts = <0 24 4>;
    };

  - |
    mmc@e2800000 {
          compatible = "arasan,sdhci-5.1";
          reg = <0xe2800000 0x1000>;
          clock-names = "clk_xin", "clk_ahb";
          clocks = <&cru 8>, <&cru 18>;
          interrupt-parent = <&gic>;
          interrupts = <0 24 4>;
          phys = <&emmc_phy>;
          phy-names = "phy_arasan";
    };

  - |
    #include <dt-bindings/clock/rk3399-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    mmc@fe330000 {
          compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
          reg = <0xfe330000 0x10000>;
          interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
          clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
          clock-names = "clk_xin", "clk_ahb";
          arasan,soc-ctl-syscon = <&grf>;
          assigned-clocks = <&cru SCLK_EMMC>;
          assigned-clock-rates = <200000000>;
          clock-output-names = "emmc_cardclock";
          phys = <&emmc_phy>;
          phy-names = "phy_arasan";
          #clock-cells = <0>;
    };

  - |
    mmc@ff160000 {
          compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
          interrupt-parent = <&gic>;
          interrupts = <0 48 4>;
          reg = <0xff160000 0x1000>;
          clocks = <&clk200>, <&clk200>;
          clock-names = "clk_xin", "clk_ahb";
          clock-output-names = "clk_out_sd0", "clk_in_sd0";
          #clock-cells = <1>;
          clk-phase-sd-hs = <63>, <72>;
    };

  - |
    mmc@f1040000 {
          compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
          interrupt-parent = <&gic>;
          interrupts = <0 126 4>;
          reg = <0xf1040000 0x10000>;
          clocks = <&clk200>, <&clk200>;
          clock-names = "clk_xin", "clk_ahb";
          clock-output-names = "clk_out_sd0", "clk_in_sd0";
          #clock-cells = <1>;
          clk-phase-sd-hs = <132>, <60>;
    };

  - |
    #define LGM_CLK_EMMC5
    #define LGM_CLK_NGI
    #define LGM_GCLK_EMMC
    mmc@ec700000 {
          compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
          reg = <0xec700000 0x300>;
          interrupt-parent = <&ioapic1>;
          interrupts = <44 1>;
          clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
                   <&cgu0 LGM_GCLK_EMMC>;
          clock-names = "clk_xin", "clk_ahb", "gate";
          clock-output-names = "emmc_cardclock";
          #clock-cells = <0>;
          phys = <&emmc_phy>;
          phy-names = "phy_arasan";
          arasan,soc-ctl-syscon = <&sysconf>;
    };

  - |
    #define LGM_CLK_SDIO
    #define LGM_GCLK_SDXC
    mmc@ec600000 {
          compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
          reg = <0xec600000 0x300>;
          interrupt-parent = <&ioapic1>;
          interrupts = <43 1>;
          clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
                   <&cgu0 LGM_GCLK_SDXC>;
          clock-names = "clk_xin", "clk_ahb", "gate";
          clock-output-names = "sdxc_cardclock";
          #clock-cells = <0>;
          phys = <&sdxc_phy>;
          phy-names = "phy_arasan";
          arasan,soc-ctl-syscon = <&sysconf>;
    };

  - |
    #define KEEM_BAY_PSS_AUX_EMMC
    #define KEEM_BAY_PSS_EMMC
    mmc@33000000 {
          compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
          interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
          reg = <0x33000000 0x300>;
          clock-names = "clk_xin", "clk_ahb";
          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
                   <&scmi_clk KEEM_BAY_PSS_EMMC>;
          phys = <&emmc_phy>;
          phy-names = "phy_arasan";
          assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
          assigned-clock-rates = <200000000>;
          clock-output-names = "emmc_cardclock";
          #clock-cells = <0>;
          arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
    };

  - |
    #define KEEM_BAY_PSS_AUX_SD0
    #define KEEM_BAY_PSS_SD0
    mmc@31000000 {
          compatible = "intel,keembay-sdhci-5.1-sd";
          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
          reg = <0x31000000 0x300>;
          clock-names = "clk_xin", "clk_ahb";
          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
                   <&scmi_clk KEEM_BAY_PSS_SD0>;
          arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
    };

  - |
    #define EMMC_XIN_CLK
    #define EMMC_AXI_CLK
    #define TBH_PSS_EMMC_RST_N
    mmc@80420000 {
          compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1";
          interrupts = <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>;
          reg = <0x80420000 0x400>;
          clocks = <&scmi_clk EMMC_XIN_CLK>,
                   <&scmi_clk EMMC_AXI_CLK>;
          clock-names = "clk_xin", "clk_ahb";
          phys = <&emmc_phy>;
          phy-names = "phy_arasan";
          assigned-clocks = <&scmi_clk EMMC_XIN_CLK>;
          clock-output-names = "emmc_cardclock";
          resets = <&rst_pss1 TBH_PSS_EMMC_RST_N>;
          #clock-cells = <0x0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/arm,pl18x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM PrimeCell MultiMedia Card Interface (MMCI) PL180 and PL181

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>
  - Ulf Hansson <ulf.hansson@linaro.org>

description:
  The ARM PrimeCells MMCI PL180 and PL181 provides an interface for
  reading and writing to MultiMedia and SD cards alike. Over the years
  vendors have use the VHDL code from ARM to create derivative MMC/SD/SDIO
  host controllers with very similar characteristics.

allOf:
  - $ref: /schemas/arm/primecell.yaml#
  - $ref: mmc-controller.yaml#

# We need a select here so we don't match all nodes with 'arm,primecell'
select:
  properties:
    compatible:
      contains:
        enum:
          - arm,pl180
          - arm,pl181
          - arm,pl18x
  required:
    - compatible

properties:
  compatible:
    oneOf:
      - description: The first version of the block, simply called
          PL180 and found in the ARM Integrator IM/PD1 logic module.
        items:
          - const: arm,pl180
          - const: arm,primecell
      - description: The improved version of the block, found in the
          ARM Versatile and later reference designs. Further revisions
          exist but get detected at runtime by reading some magic numbers
          in the PrimeCell ID registers.
        items:
          - const: arm,pl181
          - const: arm,primecell
      - description: Wildcard entry that will let the operating system
          inspect the PrimeCell ID registers to determine which hardware
          variant of PL180 or PL181 this is.
        items:
          - const: arm,pl18x
          - const: arm,primecell
      - description: Entry for STMicroelectronics variant of PL18x.
          This dedicated compatible is used by bootloaders.
        items:
          - const: st,stm32-sdmmc2
          - const: arm,pl18x
          - const: arm,primecell

  clocks:
    description: One or two clocks, the "apb_pclk" and the "MCLK"
      which is the core block clock. The names are not compulsory.
    minItems: 1
    maxItems: 2

  dmas:
    maxItems: 2

  dma-names:
    oneOf:
      - items:
          - const: tx
          - const: rx
      - items:
          - const: rx
          - const: tx

  power-domains: true

  resets:
    maxItems: 1

  reg:
    description: the MMIO memory window must be exactly 4KB (0x1000) and the
      layout should provide the PrimeCell ID registers so that the device can
      be discovered. On ST Micro variants, a second register window may be
      defined if a delay block is present and used for tuning.

  interrupts:
    description: The first interrupt is the command interrupt and corresponds
      to the event at the end of a command. The second interrupt is the
      PIO (polled I/O) interrupt and occurs when the FIFO needs to be
      emptied as part of a bulk read from the card. Some variants have these
      two interrupts wired into the same line (logic OR) and in that case
      only one interrupt may be provided. The interrupt-names property is
      not used due to inconsistency of existing DTs regarding its content.
    deprecated: false
    minItems: 1
    maxItems: 2

  st,sig-dir-dat0:
    $ref: /schemas/types.yaml#/definitions/flag
    description: ST Micro-specific property, bus signal direction pins used for
      DAT[0].

  st,sig-dir-dat2:
    $ref: /schemas/types.yaml#/definitions/flag
    description: ST Micro-specific property, bus signal direction pins used for
      DAT[2].

  st,sig-dir-dat31:
    $ref: /schemas/types.yaml#/definitions/flag
    description: ST Micro-specific property, bus signal direction pins used for
      DAT[3] and DAT[1].

  st,sig-dir-dat74:
    $ref: /schemas/types.yaml#/definitions/flag
    description: ST Micro-specific property, bus signal direction pins used for
      DAT[7] and DAT[4].

  st,sig-dir-cmd:
    $ref: /schemas/types.yaml#/definitions/flag
    description: ST Micro-specific property, CMD signal direction used for
      pin CMD.

  st,sig-pin-fbclk:
    $ref: /schemas/types.yaml#/definitions/flag
    description: ST Micro-specific property, feedback clock FBCLK signal pin
      in use.

  st,sig-dir:
    $ref: /schemas/types.yaml#/definitions/flag
    description: ST Micro-specific property, signal direction polarity used for
      pins CMD, DAT[0], DAT[1], DAT[2] and DAT[3].

  st,neg-edge:
    $ref: /schemas/types.yaml#/definitions/flag
    description: ST Micro-specific property, data and command phase relation,
      generated on the sd clock falling edge.

  st,use-ckin:
    $ref: /schemas/types.yaml#/definitions/flag
    description: ST Micro-specific property, use CKIN pin from an external
      driver to sample the receive data (for example with a voltage switch
      transceiver).

  st,cmd-gpios:
    maxItems: 1
    description:
      The GPIO matching the CMD pin.

  st,ck-gpios:
    maxItems: 1
    description:
      The GPIO matching the CK pin.

  st,ckin-gpios:
    maxItems: 1
    description:
      The GPIO matching the CKIN pin.

dependencies:
  st,cmd-gpios: [ "st,use-ckin" ]
  st,ck-gpios: [ "st,use-ckin" ]
  st,ckin-gpios: [ "st,use-ckin" ]

unevaluatedProperties: false

required:
  - compatible
  - reg
  - interrupts

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>

    mmc@5000 {
      compatible = "arm,pl180", "arm,primecell";
      reg = <0x5000 0x1000>;
      interrupts-extended = <&vic 22 &sic 1>;
      clocks = <&xtal24mhz>, <&pclk>;
      clock-names = "mclk", "apb_pclk";
    };

  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    mmc@80126000 {
      compatible = "arm,pl18x", "arm,primecell";
      reg = <0x80126000 0x1000>;
      interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
      dmas = <&dma 29 0 0x2>, <&dma 29 0 0x0>;
      dma-names = "rx", "tx";
      clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
      clock-names = "sdi", "apb_pclk";
      max-frequency = <100000000>;
      bus-width = <4>;
      cap-sd-highspeed;
      cap-mmc-highspeed;
      cd-gpios  = <&gpio2 31 0x4>;
      st,sig-dir-dat0;
      st,sig-dir-dat2;
      st,sig-dir-cmd;
      st,sig-pin-fbclk;
      vmmc-supply = <&ab8500_ldo_aux3_reg>;
      vqmmc-supply = <&vmmci>;
    };

  - |
    mmc@101f6000 {
      compatible = "arm,pl18x", "arm,primecell";
      reg = <0x101f6000 0x1000>;
      clocks = <&sdiclk>, <&pclksdi>;
      clock-names = "mclk", "apb_pclk";
      interrupts = <22>;
      max-frequency = <400000>;
      bus-width = <4>;
      cap-mmc-highspeed;
      cap-sd-highspeed;
      full-pwr-cycle;
      st,sig-dir-dat0;
      st,sig-dir-dat2;
      st,sig-dir-dat31;
      st,sig-dir-cmd;
      st,sig-pin-fbclk;
      vmmc-supply = <&vmmc_regulator>;
    };

  - |
    mmc@52007000 {
      compatible = "arm,pl18x", "arm,primecell";
      arm,primecell-periphid = <0x10153180>;
      reg = <0x52007000 0x1000>;
      interrupts = <49>;
      clocks = <&rcc 0>;
      clock-names = "apb_pclk";
      resets = <&rcc 1>;
      cap-sd-highspeed;
      cap-mmc-highspeed;
      max-frequency = <120000000>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-or-later
# Copyright 2019 IBM Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED SD/SDIO/MMC Controller

maintainers:
  - Andrew Jeffery <andrew@aj.id.au>
  - Ryan Chen <ryanchen.aspeed@gmail.com>

description: |+
  The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO
  Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if
  only a single slot is enabled.

  The two slots are supported by a common configuration area. As the SDHCIs for
  the slots are dependent on the common configuration area, they are described
  as child nodes.

properties:
  compatible:
    enum:
      - aspeed,ast2400-sd-controller
      - aspeed,ast2500-sd-controller
      - aspeed,ast2600-sd-controller
  reg:
    maxItems: 1
    description: Common configuration registers
  "#address-cells":
    const: 1
  "#size-cells":
    const: 1
  ranges: true
  clocks:
    maxItems: 1
    description: The SD/SDIO controller clock gate

patternProperties:
  "^sdhci@[0-9a-f]+$":
    type: object
    $ref: mmc-controller.yaml

    properties:
      compatible:
        enum:
          - aspeed,ast2400-sdhci
          - aspeed,ast2500-sdhci
          - aspeed,ast2600-sdhci
      reg:
        maxItems: 1
        description: The SDHCI registers
      clocks:
        maxItems: 1
        description: The SD bus clock
      interrupts:
        maxItems: 1
        description: The SD interrupt shared between both slots
      sdhci,auto-cmd12:
        type: boolean
        description: Specifies that controller should use auto CMD12
    required:
      - compatible
      - reg
      - clocks
      - interrupts

additionalProperties: false

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - ranges
  - clocks

examples:
  - |
    #include <dt-bindings/clock/aspeed-clock.h>
    sdc@1e740000 {
            compatible = "aspeed,ast2500-sd-controller";
            reg = <0x1e740000 0x100>;
            #address-cells = <1>;
            #size-cells = <1>;
            ranges = <0 0x1e740000 0x20000>;
            clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;

            sdhci0: sdhci@100 {
                    compatible = "aspeed,ast2500-sdhci";
                    reg = <0x100 0x100>;
                    interrupts = <26>;
                    sdhci,auto-cmd12;
                    clocks = <&syscon ASPEED_CLK_SDIO>;
            };

            sdhci1: sdhci@200 {
                    compatible = "aspeed,ast2500-sdhci";
                    reg = <0x200 0x100>;
                    interrupts = <26>;
                    sdhci,auto-cmd12;
                    clocks = <&syscon ASPEED_CLK_SDIO>;
            };
    };