code:
// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Hisilicon Hi3670 SoC
 *
 * Copyright (C) 2016, HiSilicon Ltd.
 * Copyright (C) 2018, Linaro Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3670-clock.h>

/ {
	compatible = "hisilicon,hi3670";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};

		cpu4: cpu@100 {
			compatible = "arm,cortex-a73";
			device_type = "cpu";
			reg = <0x0 0x100>;
			enable-method = "psci";
		};

		cpu5: cpu@101 {
			compatible = "arm,cortex-a73";
			device_type = "cpu";
			reg = <0x0 0x101>;
			enable-method = "psci";
		};

		cpu6: cpu@102 {
			compatible = "arm,cortex-a73";
			device_type = "cpu";
			reg = <0x0 0x102>;
			enable-method = "psci";
		};

		cpu7: cpu@103 {
			compatible = "arm,cortex-a73";
			device_type = "cpu";
			reg = <0x0 0x103>;
			enable-method = "psci";
		};
	};

	gic: interrupt-controller@e82b0000 {
		compatible = "arm,gic-400";
		reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
		      <0x0 0xe82b2000 0 0x2000>, /* GICC */
		      <0x0 0xe82b4000 0 0x2000>, /* GICH */
		      <0x0 0xe82b6000 0 0x2000>; /* GICV */
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
					 IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-controller;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <1920000>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		crg_ctrl: crg_ctrl@fff35000 {
			compatible = "hisilicon,hi3670-crgctrl", "syscon";
			reg = <0x0 0xfff35000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		crg_rst: crg_rst_controller {
			compatible = "hisilicon,hi3670-reset",
				     "hisilicon,hi3660-reset";
			#reset-cells = <2>;
			hisi,rst-syscon = <&crg_ctrl>;
		};

		pctrl: pctrl@e8a09000 {
			compatible = "hisilicon,hi3670-pctrl", "syscon";
			reg = <0x0 0xe8a09000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		pmuctrl: crg_ctrl@fff34000 {
			compatible = "hisilicon,hi3670-pmuctrl", "syscon";
			reg = <0x0 0xfff34000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		sctrl: sctrl@fff0a000 {
			compatible = "hisilicon,hi3670-sctrl", "syscon";
			reg = <0x0 0xfff0a000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		iomcu: iomcu@ffd7e000 {
			compatible = "hisilicon,hi3670-iomcu", "syscon";
			reg = <0x0 0xffd7e000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		media1_crg: media1_crgctrl@e87ff000 {
			compatible = "hisilicon,hi3670-media1-crg", "syscon";
			reg = <0x0 0xe87ff000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		media2_crg: media2_crgctrl@e8900000 {
			compatible = "hisilicon,hi3670-media2-crg","syscon";
			reg = <0x0 0xe8900000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		iomcu_rst: reset {
			compatible = "hisilicon,hi3660-reset";
			hisi,rst-syscon = <&iomcu>;
			#reset-cells = <2>;
		};

		uart0: serial@fdf02000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf02000 0x0 0x1000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
				 <&crg_ctrl HI3670_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
			status = "disabled";
		};

		uart1: serial@fdf00000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf00000 0x0 0x1000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
				 <&crg_ctrl HI3670_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart2: serial@fdf03000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf03000 0x0 0x1000>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3670_CLK_GATE_UART2>,
				 <&crg_ctrl HI3670_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
			status = "disabled";
		};

		uart3: serial@ffd74000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xffd74000 0x0 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3670_CLK_GATE_UART3>,
				 <&crg_ctrl HI3670_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
			status = "disabled";
		};

		uart4: serial@fdf01000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf01000 0x0 0x1000>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3670_CLK_GATE_UART4>,
				 <&crg_ctrl HI3670_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
			status = "disabled";
		};

		uart5: serial@fdf05000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf05000 0x0 0x1000>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,
				 <&crg_ctrl HI3670_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart6: serial@fff32000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfff32000 0x0 0x1000>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3670_CLK_UART6>,
				 <&crg_ctrl HI3670_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
			status = "disabled";
		};

		gpio0: gpio@e8a0b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a0b000 0x0 0x1000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO0>;
			clock-names = "apb_pclk";
		};

		gpio1: gpio@e8a0c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a0c000 0x0 0x1000>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO1>;
			clock-names = "apb_pclk";
		};

		gpio2: gpio@e8a0d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a0d000 0x0 0x1000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 1 6 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO2>;
			clock-names = "apb_pclk";
		};

		gpio3: gpio@e8a0e000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a0e000 0x0 0x1000>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO3>;
			clock-names = "apb_pclk";
		};

		gpio4: gpio@e8a0f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a0f000 0x0 0x1000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 18 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO4>;
			clock-names = "apb_pclk";
		};

		gpio5: gpio@e8a10000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a10000 0x0 0x1000>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 26 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO5>;
			clock-names = "apb_pclk";
		};

		gpio6: gpio@e8a11000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a11000 0x0 0x1000>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 1 34 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO6>;
			clock-names = "apb_pclk";
		};

		gpio7: gpio@e8a12000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a12000 0x0 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 41 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO7>;
			clock-names = "apb_pclk";
		};

		gpio8: gpio@e8a13000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a13000 0x0 0x1000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 49 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO8>;
			clock-names = "apb_pclk";
		};

		gpio9: gpio@e8a14000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a14000 0x0 0x1000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 57 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO9>;
			clock-names = "apb_pclk";
		};

		gpio10: gpio@e8a15000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a15000 0x0 0x1000>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 65 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO10>;
			clock-names = "apb_pclk";
		};

		gpio11: gpio@e8a16000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a16000 0x0 0x1000>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 73 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO11>;
			clock-names = "apb_pclk";
		};

		gpio12: gpio@e8a17000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a17000 0x0 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 81 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO12>;
			clock-names = "apb_pclk";
		};

		gpio13: gpio@e8a18000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a18000 0x0 0x1000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO13>;
			clock-names = "apb_pclk";
		};

		gpio14: gpio@e8a19000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a19000 0x0 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO14>;
			clock-names = "apb_pclk";
		};

		gpio15: gpio@e8a1a000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a1a000 0x0 0x1000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO15>;
			clock-names = "apb_pclk";
		};

		gpio16: gpio@e8a1b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a1b000 0x0 0x1000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx5 0 0 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO16>;
			clock-names = "apb_pclk";
		};

		gpio17: gpio@e8a1c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a1c000 0x0 0x1000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx5 0 8 2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO17>;
			clock-names = "apb_pclk";
		};

		gpio18: gpio@fff28000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xfff28000 0x0 0x1000>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx1 4 42 4>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3670_PCLK_GPIO18>;
			clock-names = "apb_pclk";
		};

		gpio19: gpio@fff29000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xfff29000 0x0 0x1000>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx1 0 61 2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3670_PCLK_GPIO19>;
			clock-names = "apb_pclk";
		};

		gpio20: gpio@e8a1f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a1f000 0x0 0x1000>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx7 0 0 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO20>;
			clock-names = "apb_pclk";
		};

		gpio21: gpio@e8a20000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xe8a20000 0x0 0x1000>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx7 0 8 4>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3670_PCLK_GPIO21>;
			clock-names = "apb_pclk";
		};

		gpio22: gpio@fff0b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xfff0b000 0x0 0x1000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO176 */
			gpio-ranges = <&pmx1 2 0 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3670_PCLK_AO_GPIO0>;
			clock-names = "apb_pclk";
		};

		gpio23: gpio@fff0c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xfff0c000 0x0 0x1000>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO184 */
			gpio-ranges = <&pmx1 0 6 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3670_PCLK_AO_GPIO1>;
			clock-names = "apb_pclk";
		};

		gpio24: gpio@fff0d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xfff0d000 0x0 0x1000>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO192 */
			gpio-ranges = <&pmx1 0 14 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3670_PCLK_AO_GPIO2>;
			clock-names = "apb_pclk";
		};

		gpio25: gpio@fff0e000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xfff0e000 0x0 0x1000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO200 */
			gpio-ranges = <&pmx1 0 22 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3670_PCLK_AO_GPIO3>;
			clock-names = "apb_pclk";
		};

		gpio26: gpio@fff0f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xfff0f000 0x0 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO208 */
			gpio-ranges = <&pmx1 0 30 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3670_PCLK_AO_GPIO4>;
			clock-names = "apb_pclk";
		};

		gpio27: gpio@fff10000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xfff10000 0x0 0x1000>;
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO216 */
			gpio-ranges = <&pmx1 4 31 4>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3670_PCLK_AO_GPIO5>;
			clock-names = "apb_pclk";
		};

		gpio28: gpio@fff1d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xfff1d000 0x0 0x1000>;
			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx1 1 35 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3670_PCLK_AO_GPIO6>;
			clock-names = "apb_pclk";
		};

		/* UFS */
		ufs: ufs@ff3c0000 {
			compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
			/* 0: HCI standard */
			/* 1: UFS SYS CTRL */
			reg = <0x0 0xff3c0000 0x0 0x1000>,
				<0x0 0xff3e0000 0x0 0x1000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
				 <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
			clock-names = "ref_clk", "phy_clk";
			freq-table-hz = <0 0>,
					<0 0>;
			/* offset: 0x84; bit: 12 */
			resets = <&crg_rst 0x84 12>;
			reset-names = "rst";
		};

		/* SD */
		dwmmc1: dwmmc1@ff37f000 {
			compatible = "hisilicon,hi3670-dw-mshc",
				     "hisilicon,hi3660-dw-mshc";
			reg = <0x0 0xff37f000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3670_CLK_GATE_SD>,
				<&crg_ctrl HI3670_HCLK_GATE_SD>;
			clock-names = "ciu", "biu";
			clock-frequency = <3200000>;
			resets = <&crg_rst 0x94 18>;
			reset-names = "reset";
			hisilicon,peripheral-syscon = <&sctrl>;
			card-detect-delay = <200>;
			status = "disabled";
		};

		/* SDIO */
		dwmmc2: dwmmc2@fc183000 {
			compatible = "hisilicon,hi3670-dw-mshc",
				     "hisilicon,hi3660-dw-mshc";
			reg = <0x0 0xfc183000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3670_CLK_GATE_SDIO>,
				<&crg_ctrl HI3670_HCLK_GATE_SDIO>;
			clock-names = "ciu", "biu";
			clock-frequency = <3200000>;
			resets = <&crg_rst 0x94 20>;
			reset-names = "reset";
			card-detect-delay = <200>;
			status = "disabled";
		};

		/* I2C */
		i2c0: i2c@ffd71000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xffd71000 0x0 0x1000>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&iomcu HI3670_CLK_GATE_I2C0>;
			resets = <&iomcu_rst 0x20 3>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
			status = "disabled";
		};

		i2c1: i2c@ffd72000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xffd72000 0x0 0x1000>;
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&iomcu HI3670_CLK_GATE_I2C1>;
			resets = <&iomcu_rst 0x20 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
			status = "disabled";
		};

		i2c2: i2c@ffd73000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xffd73000 0x0 0x1000>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&iomcu HI3670_CLK_GATE_I2C2>;
			resets = <&iomcu_rst 0x20 5>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
			status = "disabled";
		};

		i2c3: i2c@fdf0c000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xfdf0c000 0x0 0x1000>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3670_CLK_GATE_I2C3>;
			resets = <&crg_rst 0x78 7>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
			status = "disabled";
		};

		i2c4: i2c@fdf0d000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xfdf0d000 0x0 0x1000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3670_CLK_GATE_I2C4>;
			resets = <&crg_rst 0x78 27>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4_pmx_func &i2c4_cfg_func>;
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * DTS File for HiSilicon Poplar Development Board
 *
 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include "hi3798cv200.dtsi"
#include "poplar-pinctrl.dtsi"

/ {
	model = "HiSilicon Poplar Development Board";
	compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";

	aliases {
		serial0 = &uart0;
		serial2 = &uart2;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	leds {
		compatible = "gpio-leds";

		user-led0 {
			label = "green:user1";
			gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
			default-state = "off";
		};

		user-led1 {
			label = "green:user2";
			gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "mmc0";
			default-state = "off";
		};

		user-led2 {
			label = "green:user3";
			gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "mmc1";
			default-state = "off";
		};

		user-led3 {
			label = "green:user4";
			gpios = <&gpio10 6 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "none";
			panic-indicator;
			default-state = "off";
		};
	};

	reg_pcie: regulator-pcie {
		compatible = "regulator-fixed";
		regulator-name = "3V3_PCIE0";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio6 7 0>;
		enable-active-high;
	};
};

&ehci {
	status = "okay";
};

&emmc {
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
		     &emmc_pins_3 &emmc_pins_4>;
	fifo-depth = <256>;
	clock-frequency = <200000000>;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	non-removable;
	bus-width = <8>;
	status = "okay";
};

&gmac1 {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;
	phy-handle = <&eth_phy1>;
	phy-mode = "rgmii";
	hisilicon,phy-reset-delays-us = <10000 10000 30000>;

	eth_phy1: phy@3 {
		reg = <3>;
	};
};

&gpio1 {
	status = "okay";
	gpio-line-names = "GPIO-E",	"",
			  "",		"",
			  "",		"GPIO-F",
			  "",		"GPIO-J";
};

&gpio2 {
	status = "okay";
	gpio-line-names = "GPIO-H",	"GPIO-I",
			  "GPIO-L",	"GPIO-G",
			  "GPIO-K",	"",
			  "",		"";
};

&gpio3 {
	status = "okay";
	gpio-line-names = "",		"",
			  "",		"",
			  "GPIO-C",	"",
			  "",		"GPIO-B";
};

&gpio4 {
	status = "okay";
	gpio-line-names = "",		"",
			  "",		"",
			  "",		"GPIO-D",
			  "",		"";
};

&gpio5 {
	status = "okay";
	gpio-line-names = "",		"USER-LED-1",
			  "USER-LED-2",	"",
			  "",		"GPIO-A",
			  "",		"";
};

&gpio6 {
	status = "okay";
	gpio-line-names = "",		"",
			  "",		"USER-LED-0",
			  "",		"",
			  "",		"";
};

&gpio10 {
	status = "okay";
	gpio-line-names = "",		"",
			  "",		"",
			  "",		"",
			  "USER-LED-3",	"";
};

&i2c0 {
	status = "okay";
	label = "LS-I2C0";
};

&i2c2 {
	status = "okay";
	label = "LS-I2C1";
};

&ir {
	linux,rc-map-name = "rc-hisi-poplar";
	status = "okay";
};

&ohci {
	status = "okay";
};

&pcie {
	reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
	vpcie-supply = <&reg_pcie>;
	status = "okay";
};

&sd0 {
	bus-width = <4>;
	cap-sd-highspeed;
	status = "okay";
};

&spi0 {
	status = "okay";
	label = "LS-SPI0";
};

&uart0 {
	status = "okay";
};

&uart2 {
	status = "okay";
	label = "LS-UART0";
};
/* No optional LS-UART1 on Low Speed Expansion Connector. */

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * DTS File for HiSilicon Hi3798cv200 SoC.
 *
 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
 */

#include <dt-bindings/clock/histb-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/ti-syscon.h>

/ {
	compatible = "hisilicon,hi3798cv200";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu@3 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};
	};

	gic: interrupt-controller@f1001000 {
		compatible = "arm,gic-400";
		reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
		      <0x0 0xf1002000 0x0 0x100>;   /* GICC */
		#address-cells = <0>;
		#interrupt-cells = <3>;
		interrupt-controller;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
			      IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
			      IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
			      IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
			      IRQ_TYPE_LEVEL_LOW)>;
	};

	soc: soc@f0000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0xf0000000 0x10000000>;

		crg: clock-reset-controller@8a22000 {
			compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
			reg = <0x8a22000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <2>;

			gmacphyrst: reset-controller {
				compatible = "ti,syscon-reset";
				#reset-cells = <1>;
				ti,reset-bits = <
					0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
					0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
				>;
			};
		};

		sysctrl: system-controller@8000000 {
			compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
			reg = <0x8000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <2>;
		};

		perictrl: peripheral-controller@8a20000 {
			compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
				     "simple-mfd";
			reg = <0x8a20000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x8a20000 0x1000>;

			usb2_phy1: usb2_phy@120 {
				compatible = "hisilicon,hi3798cv200-usb2-phy";
				reg = <0x120 0x4>;
				clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
				resets = <&crg 0xbc 4>;
				#address-cells = <1>;
				#size-cells = <0>;

				usb2_phy1_port0: phy@0 {
					reg = <0>;
					#phy-cells = <0>;
					resets = <&crg 0xbc 8>;
				};

				usb2_phy1_port1: phy@1 {
					reg = <1>;
					#phy-cells = <0>;
					resets = <&crg 0xbc 9>;
				};
			};

			usb2_phy2: usb2_phy@124 {
				compatible = "hisilicon,hi3798cv200-usb2-phy";
				reg = <0x124 0x4>;
				clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
				resets = <&crg 0xbc 6>;
				#address-cells = <1>;
				#size-cells = <0>;

				usb2_phy2_port0: phy@0 {
					reg = <0>;
					#phy-cells = <0>;
					resets = <&crg 0xbc 10>;
				};
			};

			combphy0: phy@850 {
				compatible = "hisilicon,hi3798cv200-combphy";
				reg = <0x850 0x8>;
				#phy-cells = <1>;
				clocks = <&crg HISTB_COMBPHY0_CLK>;
				resets = <&crg 0x188 4>;
				assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
				assigned-clock-rates = <100000000>;
				hisilicon,fixed-mode = <PHY_TYPE_USB3>;
			};

			combphy1: phy@858 {
				compatible = "hisilicon,hi3798cv200-combphy";
				reg = <0x858 0x8>;
				#phy-cells = <1>;
				clocks = <&crg HISTB_COMBPHY1_CLK>;
				resets = <&crg 0x188 12>;
				assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
				assigned-clock-rates = <100000000>;
				hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
			};
		};

		pmx0: pinconf@8a21000 {
			compatible = "pinconf-single";
			reg = <0x8a21000 0x180>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <7>;
			pinctrl-single,gpio-range = <
				&range 0  8 2  /* GPIO 0 */
				&range 8  1 0  /* GPIO 1 */
				&range 9  4 2
				&range 13 1 0
				&range 14 1 1
				&range 15 1 0
				&range 16 5 0  /* GPIO 2 */
				&range 21 3 1
				&range 24 4 1  /* GPIO 3 */
				&range 28 2 2
				&range 86 1 1
				&range 87 1 0
				&range 30 4 2  /* GPIO 4 */
				&range 34 3 0
				&range 37 1 2
				&range 38 3 2  /* GPIO 6 */
				&range 41 5 0
				&range 46 8 1  /* GPIO 7 */
				&range 54 8 1  /* GPIO 8 */
				&range 64 7 1  /* GPIO 9 */
				&range 71 1 0
				&range 72 6 1  /* GPIO 10 */
				&range 78 1 0
				&range 79 1 1
				&range 80 6 1  /* GPIO 11 */
				&range 70 2 1
				&range 88 8 0  /* GPIO 12 */
			>;

			range: gpio-range {
				#pinctrl-single,gpio-range-cells = <3>;
			};
		};

		uart0: serial@8b00000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x8b00000 0x1000>;
			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart2: serial@8b02000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x8b02000 0x1000>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		i2c0: i2c@8b10000 {
			compatible = "hisilicon,hix5hd2-i2c";
			reg = <0x8b10000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&crg HISTB_I2C0_CLK>;
			status = "disabled";
		};

		i2c1: i2c@8b11000 {
			compatible = "hisilicon,hix5hd2-i2c";
			reg = <0x8b11000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&crg HISTB_I2C1_CLK>;
			status = "disabled";
		};

		i2c2: i2c@8b12000 {
			compatible = "hisilicon,hix5hd2-i2c";
			reg = <0x8b12000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&crg HISTB_I2C2_CLK>;
			status = "disabled";
		};

		i2c3: i2c@8b13000 {
			compatible = "hisilicon,hix5hd2-i2c";
			reg = <0x8b13000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&crg HISTB_I2C3_CLK>;
			status = "disabled";
		};

		i2c4: i2c@8b14000 {
			compatible = "hisilicon,hix5hd2-i2c";
			reg = <0x8b14000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <400000>;
			clocks = <&crg HISTB_I2C4_CLK>;
			status = "disabled";
		};

		spi0: spi@8b1a000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x8b1a000 0x1000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			num-cs = <1>;
			cs-gpios = <&gpio7 1 0>;
			clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>;
			clock-names = "sspclk", "apb_pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		sd0: mmc@9820000 {
			compatible = "snps,dw-mshc";
			reg = <0x9820000 0x10000>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_SDIO0_CIU_CLK>,
				 <&crg HISTB_SDIO0_BIU_CLK>;
			clock-names = "biu", "ciu";
			resets = <&crg 0x9c 4>;
			reset-names = "reset";
			status = "disabled";
		};

		emmc: mmc@9830000 {
			compatible = "hisilicon,hi3798cv200-dw-mshc";
			reg = <0x9830000 0x10000>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_MMC_CIU_CLK>,
				 <&crg HISTB_MMC_BIU_CLK>,
				 <&crg HISTB_MMC_SAMPLE_CLK>,
				 <&crg HISTB_MMC_DRV_CLK>;
			clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
			resets = <&crg 0xa0 4>;
			reset-names = "reset";
			status = "disabled";
		};

		gpio0: gpio@8b20000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b20000 0x1000>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 0 8>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio1: gpio@8b21000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b21000 0x1000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <
				&pmx0 0 8 1
				&pmx0 1 9 4
				&pmx0 5 13 1
				&pmx0 6 14 1
				&pmx0 7 15 1
			>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio2: gpio@8b22000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b22000 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio3: gpio@8b23000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b23000 0x1000>;
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <
				&pmx0 0 24 4
				&pmx0 4 28 2
				&pmx0 6 86 1
				&pmx0 7 87 1
			>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio4: gpio@8b24000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b24000 0x1000>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio5: gpio@8004000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8004000 0x1000>;
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio6: gpio@8b26000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b26000 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio7: gpio@8b27000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b27000 0x1000>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 46 8>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio8: gpio@8b28000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b28000 0x1000>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 54 8>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio9: gpio@8b29000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b29000 0x1000>;
			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio10: gpio@8b2a000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b2a000 0x1000>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio11: gpio@8b2b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b2b000 0x1000>;
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gpio12: gpio@8b2c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x8b2c000 0x1000>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx0 0 88 8>;
			clocks = <&crg HISTB_APB_CLK>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		gmac0: ethernet@9840000 {
			compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
			reg = <0x9840000 0x1000>,
			      <0x984300c 0x4>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_ETH0_MAC_CLK>,
				 <&crg HISTB_ETH0_MACIF_CLK>;
			clock-names = "mac_core", "mac_ifc";
			resets = <&crg 0xcc 8>,
				 <&crg 0xcc 10>,
				 <&gmacphyrst 0>;
			reset-names = "mac_core", "mac_ifc", "phy";
			status = "disabled";
		};

		gmac1: ethernet@9841000 {
			compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
			reg = <0x9841000 0x1000>,
			      <0x9843010 0x4>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_ETH1_MAC_CLK>,
				 <&crg HISTB_ETH1_MACIF_CLK>;
			clock-names = "mac_core", "mac_ifc";
			resets = <&crg 0xcc 9>,
				 <&crg 0xcc 11>,
				 <&gmacphyrst 1>;
			reset-names = "mac_core", "mac_ifc", "phy";
			status = "disabled";
		};

		ir: ir@8001000 {
			compatible = "hisilicon,hix5hd2-ir";
			reg = <0x8001000 0x1000>;
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl HISTB_IR_CLK>;
			status = "disabled";
		};

		pcie: pcie@9860000 {
			compatible = "hisilicon,hi3798cv200-pcie";
			reg = <0x9860000 0x1000>,
			      <0x0 0x2000>,
			      <0x2000000 0x01000000>;
			reg-names = "control", "rc-dbi", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			bus-range = <0x00 0xff>;
			num-lanes = <1>;
			ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000>,
				 <0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_PCIE_AUX_CLK>,
				 <&crg HISTB_PCIE_PIPE_CLK>,
				 <&crg HISTB_PCIE_SYS_CLK>,
				 <&crg HISTB_PCIE_BUS_CLK>;
			clock-names = "aux", "pipe", "sys", "bus";
			resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
			reset-names = "soft", "sys", "bus";
			phys = <&combphy1 PHY_TYPE_PCIE>;
			phy-names = "phy";
			status = "disabled";
		};

		ohci: usb@9880000 {
			compatible = "generic-ohci";
			reg = <0x9880000 0x10000>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_USB2_BUS_CLK>,
				 <&crg HISTB_USB2_12M_CLK>,
				 <&crg HISTB_USB2_48M_CLK>;
			clock-names = "bus", "clk12", "clk48";
			resets = <&crg 0xb8 12>;
			reset-names = "bus";
			phys = <&usb2_phy1_port0>;
			phy-names = "usb";
			status = "disabled";
		};

		ehci: usb@9890000 {
			compatible = "generic-ehci";
			reg = <0x9890000 0x10000>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg HISTB_USB2_BUS_CLK>,
				 <&crg HISTB_USB2_PHY_CLK>,
				 <&crg HISTB_USB2_UTMI_CLK>;
			clock-names = "bus", "phy", "utmi";
			resets = <&crg 0xb8 12>,
				 <&crg 0xb8 16>,
				 <&crg 0xb8 13>;
			reset-names = "bus", "phy", "utmi";
			phys = <&usb2_phy1_port0>;
			phy-names = "usb";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * dtsi file for Hisilicon Hi6220 coresight
 *
 * Copyright (C) 2017 HiSilicon Ltd.
 *
 * Author: Pengcheng Li <lipengcheng8@huawei.com>
 *         Leo Yan <leo.yan@linaro.org>
 */

/ {
	soc {
		funnel@f6401000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0 0xf6401000 0 0x1000>;
			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					soc_funnel_out: endpoint {
						remote-endpoint =
							<&etf_in>;
					};
				};
			};

			in-ports {
				port {
					soc_funnel_in: endpoint {
						remote-endpoint =
							<&acpu_funnel_out>;
					};
				};
			};
		};

		etf@f6402000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0 0xf6402000 0 0x1000>;
			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					etf_in: endpoint {
						remote-endpoint =
							<&soc_funnel_out>;
					};
				};
			};

			out-ports {
				port {
					etf_out: endpoint {
						remote-endpoint =
							<&replicator_in>;
					};
				};
			};
		};

		replicator {
			compatible = "arm,coresight-static-replicator";
			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					replicator_in: endpoint {
						remote-endpoint =
							<&etf_out>;
					};
				};
			};

			out-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					replicator_out0: endpoint {
						remote-endpoint =
							<&etr_in>;
					};
				};

				port@1 {
					reg = <1>;
					replicator_out1: endpoint {
						remote-endpoint =
							<&tpiu_in>;
					};
				};
			};
		};

		etr@f6404000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0 0xf6404000 0 0x1000>;
			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					etr_in: endpoint {
						remote-endpoint =
							<&replicator_out0>;
					};
				};
			};
		};

		tpiu@f6405000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0 0xf6405000 0 0x1000>;
			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			in-ports {
				port {
					tpiu_in: endpoint {
						remote-endpoint =
							<&replicator_out1>;
					};
				};
			};
		};

		funnel@f6501000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0 0xf6501000 0 0x1000>;
			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			out-ports {
				port {
					acpu_funnel_out: endpoint {
						remote-endpoint =
							<&soc_funnel_in>;
					};
				};
			};

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					acpu_funnel_in0: endpoint {
						remote-endpoint =
							<&etm0_out>;
					};
				};

				port@1 {
					reg = <1>;
					acpu_funnel_in1: endpoint {
						remote-endpoint =
							<&etm1_out>;
					};
				};

				port@2 {
					reg = <2>;
					acpu_funnel_in2: endpoint {
						remote-endpoint =
							<&etm2_out>;
					};
				};

				port@3 {
					reg = <3>;
					acpu_funnel_in3: endpoint {
						remote-endpoint =
							<&etm3_out>;
					};
				};

				port@4 {
					reg = <4>;
					acpu_funnel_in4: endpoint {
						remote-endpoint =
							<&etm4_out>;
					};
				};

				port@5 {
					reg = <5>;
					acpu_funnel_in5: endpoint {
						remote-endpoint =
							<&etm5_out>;
					};
				};

				port@6 {
					reg = <6>;
					acpu_funnel_in6: endpoint {
						remote-endpoint =
							<&etm6_out>;
					};
				};

				port@7 {
					reg = <7>;
					acpu_funnel_in7: endpoint {
						remote-endpoint =
							<&etm7_out>;
					};
				};
			};
		};

		etm0: etm@f659c000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xf659c000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu0>;

			out-ports {
				port {
					etm0_out: endpoint {
						remote-endpoint =
							<&acpu_funnel_in0>;
					};
				};
			};
		};

		etm1: etm@f659d000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xf659d000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu1>;

			out-ports {
				port {
					etm1_out: endpoint {
						remote-endpoint =
							<&acpu_funnel_in1>;
					};
				};
			};
		};

		etm2: etm@f659e000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xf659e000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu2>;

			out-ports {
				port {
					etm2_out: endpoint {
						remote-endpoint =
							<&acpu_funnel_in2>;
					};
				};
			};
		};

		etm3: etm@f659f000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xf659f000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu3>;

			out-ports {
				port {
					etm3_out: endpoint {
						remote-endpoint =
							<&acpu_funnel_in3>;
					};
				};
			};
		};

		etm4: etm@f65dc000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xf65dc000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu4>;

			out-ports {
				port {
					etm4_out: endpoint {
						remote-endpoint =
							<&acpu_funnel_in4>;
					};
				};
			};
		};

		etm5: etm@f65dd000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xf65dd000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu5>;

			out-ports {
				port {
					etm5_out: endpoint {
						remote-endpoint =
							<&acpu_funnel_in5>;
					};
				};
			};
		};

		etm6: etm@f65de000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xf65de000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu6>;

			out-ports {
				port {
					etm6_out: endpoint {
						remote-endpoint =
							<&acpu_funnel_in6>;
					};
				};
			};
		};

		etm7: etm@f65df000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0 0xf65df000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu7>;

			out-ports {
				port {
					etm7_out: endpoint {
						remote-endpoint =
							<&acpu_funnel_in7>;
					};
				};
			};
		};

		/* System CTIs */
		/* CTI 0 - TMC and TPIU connections */
		cti@f6403000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0 0xf6403000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";
		};

		/* CTI - CPU-0 */
		cti@f6598000 {
			compatible = "arm,coresight-cti-v8-arch",
				     "arm,coresight-cti", "arm,primecell";
			reg = <0 0xf6598000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu0>;
			arm,cs-dev-assoc = <&etm0>;
		};

		/* CTI - CPU-1 */
		cti@f6599000 {
			compatible = "arm,coresight-cti-v8-arch",
				     "arm,coresight-cti", "arm,primecell";
			reg = <0 0xf6599000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu1>;
			arm,cs-dev-assoc = <&etm1>;
		};

		/* CTI - CPU-2 */
		cti@f659a000 {
			compatible = "arm,coresight-cti-v8-arch",
				     "arm,coresight-cti", "arm,primecell";
			reg = <0 0xf659a000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu2>;
			arm,cs-dev-assoc = <&etm2>;
		};

		/* CTI - CPU-3 */
		cti@f659b000 {
			compatible = "arm,coresight-cti-v8-arch",
				     "arm,coresight-cti", "arm,primecell";
			reg = <0 0xf659b000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu3>;
			arm,cs-dev-assoc = <&etm3>;
		};

		/* CTI - CPU-4 */
		cti@f65d8000 {
			compatible = "arm,coresight-cti-v8-arch",
				     "arm,coresight-cti", "arm,primecell";
			reg = <0 0xf65d8000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu4>;
			arm,cs-dev-assoc = <&etm4>;
		};

		/* CTI - CPU-5 */
		cti@f65d9000 {
			compatible = "arm,coresight-cti-v8-arch",
				     "arm,coresight-cti", "arm,primecell";
			reg = <0 0xf65d9000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu5>;
			arm,cs-dev-assoc = <&etm5>;
		};

		/* CTI - CPU-6 */
		cti@f65da000 {
			compatible = "arm,coresight-cti-v8-arch",
				     "arm,coresight-cti", "arm,primecell";
			reg = <0 0xf65da000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu6>;
			arm,cs-dev-assoc = <&etm6>;
		};

		/* CTI - CPU-7 */
		cti@f65db000 {
			compatible = "arm,coresight-cti-v8-arch",
				     "arm,coresight-cti", "arm,primecell";
			reg = <0 0xf65db000 0 0x1000>;

			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
			clock-names = "apb_pclk";

			cpu = <&cpu7>;
			arm,cs-dev-assoc = <&etm7>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Hisilicon HiKey Development Board
 *
 * Copyright (C) 2015, HiSilicon Ltd.
 *
 */

/dts-v1/;
#include "hi6220.dtsi"
#include "hikey-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "HiKey Development Board";
	compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";

	aliases {
		serial0 = &uart0; /* On board UART0 */
		serial1 = &uart1; /* BT UART */
		serial2 = &uart2; /* LS Expansion UART0 */
		serial3 = &uart3; /* LS Expansion UART1 */
	};

	chosen {
		stdout-path = "serial3:115200n8";
	};

	/*
	 * Reserve below regions from memory node:
	 *
	 *  0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
	 *  0x05f0,1000 - 0x05f0,1fff: Reboot reason
	 *  0x06df,f000 - 0x06df,ffff: Mailbox message data
	 *  0x0740,f000 - 0x0740,ffff: MCU firmware section
	 *  0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
	 *  0x3e00,0000 - 0x3fff,ffff: OP-TEE
	 */
	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
		      <0x00000000 0x05f00000 0x00000000 0x00001000>,
		      <0x00000000 0x05f02000 0x00000000 0x00efd000>,
		      <0x00000000 0x06e00000 0x00000000 0x0060f000>,
		      <0x00000000 0x07410000 0x00000000 0x1aaf0000>,
		      <0x00000000 0x22000000 0x00000000 0x1c000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ramoops@21f00000 {
			compatible = "ramoops";
			reg = <0x0 0x21f00000 0x0 0x00100000>;
			record-size = <0x00020000>;
			console-size = <0x00020000>;
			ftrace-size = <0x00020000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x00000000 0x08000000>;
			linux,cma-default;
		};
	};

	reboot-mode-syscon@5f01000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x0 0x05f01000 0x0 0x00001000>;

		reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x0>;

			mode-normal = <0x77665501>;
			mode-bootloader = <0x77665500>;
			mode-recovery = <0x77665502>;
		};
	};

	reg_sys_5v: regulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "SYS_5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_vdd_3v3: regulator@1 {
		compatible = "regulator-fixed";
		regulator-name = "VDD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
		vin-supply = <&reg_sys_5v>;
	};

	reg_5v_hub: regulator@2 {
		compatible = "regulator-fixed";
		regulator-name = "5V_HUB";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		gpio = <&gpio0 7 0>;
		regulator-always-on;
		vin-supply = <&reg_sys_5v>;
	};

	wl1835_pwrseq: wl1835-pwrseq {
		compatible = "mmc-pwrseq-simple";
		/* WLAN_EN GPIO */
		reset-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
		clocks = <&pmic>;
		clock-names = "ext_clock";
		post-power-on-delay-ms = <10>;
		power-off-delay-us = <10>;
	};

	leds {
		compatible = "gpio-leds";

		user_led1 {
			label = "green:user1";
			gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */
			linux,default-trigger = "heartbeat";
		};

		user_led2 {
			label = "green:user2";
			gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */
			linux,default-trigger = "mmc0";
		};

		user_led3 {
			label = "green:user3";
			gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */
			linux,default-trigger = "mmc1";
		};

		user_led4 {
			label = "green:user4";
			gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */
			panic-indicator;
			linux,default-trigger = "none";
		};

		wlan_active_led {
			label = "yellow:wlan";
			gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */
			linux,default-trigger = "phy0tx";
			default-state = "off";
		};

		bt_active_led {
			label = "blue:bt";
			gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */
			linux,default-trigger = "hci0-power";
			default-state = "off";
		};
	};

	pmic: pmic@f8000000 {
		compatible = "hisilicon,hi655x-pmic";
		reg = <0x0 0xf8000000 0x0 0x1000>;
		#clock-cells = <0>;
		interrupt-controller;
		#interrupt-cells = <2>;
		pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;

		regulators {
			ldo2: LDO2 {
				regulator-name = "LDO2_2V8";
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <3200000>;
				regulator-enable-ramp-delay = <120>;
			};

			ldo7: LDO7 {
				regulator-name = "LDO7_SDIO";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-enable-ramp-delay = <120>;
			};

			ldo10: LDO10 {
				regulator-name = "LDO10_2V85";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <360>;
			};

			ldo13: LDO13 {
				regulator-name = "LDO13_1V8";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <1950000>;
				regulator-enable-ramp-delay = <120>;
			};

			ldo14: LDO14 {
				regulator-name = "LDO14_2V8";
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <3200000>;
				regulator-enable-ramp-delay = <120>;
			};

			ldo15: LDO15 {
				regulator-name = "LDO15_1V8";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <1950000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-enable-ramp-delay = <120>;
			};

			ldo17: LDO17 {
				regulator-name = "LDO17_2V5";
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <3200000>;
				regulator-enable-ramp-delay = <120>;
			};

			ldo19: LDO19 {
				regulator-name = "LDO19_3V0";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3000000>;
				regulator-enable-ramp-delay = <360>;
			};

			ldo21: LDO21 {
				regulator-name = "LDO21_1V8";
				regulator-min-microvolt = <1650000>;
				regulator-max-microvolt = <2000000>;
				regulator-always-on;
				regulator-enable-ramp-delay = <120>;
			};

			ldo22: LDO22 {
				regulator-name = "LDO22_1V2";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1200000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-enable-ramp-delay = <120>;
			};
		};
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	sound_card {
		compatible = "audio-graph-card";
		dais = <&i2s0_port0>;
	};
};

&uart1 {
	assigned-clocks = <&sys_ctrl HI6220_UART1_SRC>;
	assigned-clock-rates = <150000000>;
	status = "okay";

	bluetooth {
		compatible = "ti,wl1835-st";
		enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
		clocks = <&pmic>;
		clock-names = "ext_clock";
	};
};

&uart2 {
	status = "okay";
	label = "LS-UART0";
};

&uart3 {
	status = "okay";
	label = "LS-UART1";
};

&ade {
	status = "okay";
};

&dsi {
	status = "okay";

	ports {
		/* 1 for output port */
		port@1 {
			reg = <1>;

			dsi_out0: endpoint@0 {
				remote-endpoint = <&adv7533_in>;
			};
		};
	};
};

&dwmmc_0 {
	cap-mmc-highspeed;
	non-removable;
	bus-width = <0x8>;
	vmmc-supply = <&ldo19>;
};

&dwmmc_1 {
	card-detect-delay = <200>;
	cap-sd-highspeed;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	vqmmc-supply = <&ldo7>;
	vmmc-supply = <&ldo10>;
	bus-width = <0x4>;
	disable-wp;
	cd-gpios = <&gpio1 0 1>;
};

&dwmmc_2 {
	bus-width = <0x4>;
	non-removable;
	cap-power-off-card;
	vmmc-supply = <&reg_vdd_3v3>;
	mmc-pwrseq = <&wl1835_pwrseq>;

	#address-cells = <0x1>;
	#size-cells = <0x0>;
	wlcore: wlcore@2 {
		compatible = "ti,wl1835";
		reg = <2>;	/* sdio func num */
		/* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */
		interrupt-parent = <&gpio1>;
		interrupts = <3 IRQ_TYPE_EDGE_RISING>;
	};
};

/*
 * Legend: proper name = the GPIO line is used as GPIO
 *         NC = not connected (not routed from the SoC)
 *         "[PER]" = pin is muxed for peripheral (not GPIO)
 *         "" = no idea, schematic doesn't say, could be
 *              unrouted (not connected to any external pin)
 *         LSEC = Low Speed External Connector
 *         HSEC = High Speed External Connector
 *
 * Pin assignments taken from LeMaker and CircuitCo Schematics
 * Rev A1.
 *
 * For the lines routed to the external connectors the
 * lines are named after the 96Boards CE Specification 1.0,
 * Appendix "Expansion Connector Signal Description".
 *
 * When the 96Board naming of a line and the schematic name of
 * the same line are in conflict, the 96Board specification
 * takes precedence, which means that the external UART on the
 * LSEC is named UART0 while the schematic and SoC names this
 * UART2. This is only for the informational lines i.e. "[FOO]",
 * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
 * ones actually used for GPIO.
 */
&gpio0 {
	gpio-line-names = "PWR_HOLD", "DSI_SEL",
	"USB_HUB_RESET_N", "USB_SEL", "HDMI_PD", "WL_REG_ON",
	"PWRON_DET", "5V_HUB_EN";
};

&gpio1 {
	gpio-line-names = "SD_DET", "HDMI_INT", "PMU_IRQ_N",
	"WL_HOST_WAKE", "NC", "NC", "NC", "BT_REG_ON";
};

&gpio2 {
	gpio-line-names =
		"GPIO-A", /* LSEC Pin 23: GPIO2_0 */
		"GPIO-B", /* LSEC Pin 24: GPIO2_1 */
		"GPIO-C", /* LSEC Pin 25: GPIO2_2 */
		"GPIO-D", /* LSEC Pin 26: GPIO2_3 */
		"GPIO-E", /* LSEC Pin 27: GPIO2_4 */
		"USB_ID_DET", "USB_VBUS_DET",
		"GPIO-H"; /* LSEC Pin 30: GPIO2_7 */
};

&gpio3 {
	gpio-line-names = "GPIO3_0", "NC", "NC", "", "NC", "",
	"WLAN_ACTIVE", "NC", "NC";
};

&gpio4 {
	gpio-line-names = "USER_LED1", "USER_LED2", "USER_LED3",
	"USER_LED4", "SD_SEL", "NC", "NC", "BT_ACTIVE";
};

&gpio5 {
	gpio-line-names = "NC", "NC",
	"[UART1_RxD]", /* LSEC Pin 11: UART3_RX */
	"[UART1_TxD]", /* LSEC Pin 13: UART3_TX */
	"[AUX_SSI1]", "NC",
	"[PCM_CLK]", /* LSEC Pin 18: MODEM_PCM_XCLK */
	"[PCM_FS]"; /* LSEC Pin 16: MODEM_PCM_XFS */
};

&gpio6 {
	gpio-line-names =
	"[SPI0_DIN]", /* Pin 10: SPI0_DI */
	"[SPI0_DOUT]", /* Pin 14: SPI0_DO */
	"[SPI0_CS]", /* Pin 12: SPI0_CS_N */
	"[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */
	"NC", "NC", "NC",
	"GPIO-G"; /* Pin 29: GPIO6_7_DSI_TE0 */
};

&gpio7 {
	gpio-line-names = "NC", "NC", "NC", "NC",
	"[PCM_DI]", /* Pin 22: MODEM_PCM_DI */
	"[PCM_DO]", /* Pin 20: MODEM_PCM_DO */
	"NC", "NC";
};

&gpio8 {
	gpio-line-names = "NC", "[CEC_CLK_19_2MHZ]", "NC",
	"", "", "", "", "", "";
};

&gpio9 {
	gpio-line-names = "",
	"GPIO-J", /* LSEC Pin 32: ISP_PWDN0_GPIO9_1 */
	"GPIO-L", /* LSEC Pin 34: ISP_PWDN1_GPIO9_2 */
	"NC", "NC", "NC", "NC", "[ISP_CCLK0]";
};

&gpio10 {
	gpio-line-names = "BOOT_SEL",
	"[ISP_CCLK1]",
	"GPIO-I", /* LSEC Pin 31: ISP_RSTB0_GPIO10_2 */
	"GPIO-K", /* LSEC Pin 33: ISP_RSTB1_GPIO10_3 */
	"NC", "NC",
	"[I2C2_SDA]", /* HSEC Pin 34: ISP0_SDA */
	"[I2C2_SCL]"; /* HSEC Pin 32: ISP0_SCL */
};

&gpio11 {
	gpio-line-names =
	"[I2C3_SDA]", /* HSEC Pin 38: ISP1_SDA */
	"[I2C3_SCL]", /* HSEC Pin 36: ISP1_SCL */
	"", "NC", "NC", "NC", "", "";
};

&gpio12 {
	gpio-line-names = "[BT_PCM_XFS]", "[BT_PCM_DI]",
	"[BT_PCM_DO]",
	"NC", "NC", "NC", "NC",
	"GPIO-F"; /* LSEC Pin 28: BL_PWM_GPIO12_7 */
};

&gpio13 {
	gpio-line-names = "[UART0_RX]", "[UART0_TX]",
	"[BT_UART1_CTS]", "[BT_UART1_RTS]",
	"[BT_UART1_RX]", "[BT_UART1_TX]",
	"[UART0_CTS]", /* LSEC Pin 3: UART2_CTS_N */
	"[UART0_RTS]"; /* LSEC Pin 9: UART2_RTS_N */
};

&gpio14 {
	gpio-line-names =
	"[UART0_RxD]", /* LSEC Pin 7: UART2_RX */
	"[UART0_TxD]", /* LSEC Pin 5: UART2_TX */
	"[I2C0_SCL]", /* LSEC Pin 15: I2C0_SCL */
	"[I2C0_SDA]", /* LSEC Pin 17: I2C0_SDA */
	"[I2C1_SCL]", /* LSEC Pin 19: I2C1_SCL */
	"[I2C1_SDA]", /* LSEC Pin 21: I2C1_SDA */
	"[I2C2_SCL]", "[I2C2_SDA]";
};

&gpio15 {
	gpio-line-names = "", "", "", "", "", "", "NC", "";
};

/* GPIO blocks 16 thru 19 do not appear to be routed to pins */

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";
};

&i2c2 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	adv7533: adv7533@39 {
		compatible = "adi,adv7533";
		reg = <0x39>;
		interrupt-parent = <&gpio1>;
		interrupts = <1 2>;
		pd-gpios = <&gpio0 4 0>;
		adi,dsi-lanes = <4>;
		#sound-dai-cells = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				adv7533_in: endpoint {
					remote-endpoint = <&dsi_out0>;
				};
			};
			port@2 {
				reg = <2>;
				codec_endpoint: endpoint {
					remote-endpoint = <&i2s0_cpu_endpoint>;
				};
			};
		};
	};
};

&i2s0 {

	ports {
		i2s0_port0: port@0 {
			i2s0_cpu_endpoint: endpoint {
				remote-endpoint = <&codec_endpoint>;
				dai-format = "i2s";
			};
		};
	};
};

&spi0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Hisilicon Hi6220 SoC
 *
 * Copyright (C) 2015, HiSilicon Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/hisi,hi6220-resets.h>
#include <dt-bindings/clock/hi6220-clock.h>
#include <dt-bindings/pinctrl/hisi.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "hisilicon,hi6220";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP: cpu-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <700>;
				exit-latency-us = <250>;
				min-residency-us = <1000>;
			};

			CLUSTER_SLEEP: cluster-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <1000>;
				exit-latency-us = <700>;
				min-residency-us = <2700>;
				wakeup-latency-us = <1500>;
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
			clocks = <&stub_clock 0>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <311>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
			clocks = <&stub_clock 0>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <311>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x2>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
			clocks = <&stub_clock 0>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <311>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x3>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
			clocks = <&stub_clock 0>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <311>;
		};

		cpu4: cpu@100 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER1_L2>;
			clocks = <&stub_clock 0>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <311>;
		};

		cpu5: cpu@101 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER1_L2>;
			clocks = <&stub_clock 0>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <311>;
		};

		cpu6: cpu@102 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x102>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER1_L2>;
			clocks = <&stub_clock 0>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <311>;
		};

		cpu7: cpu@103 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0x0 0x103>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER1_L2>;
			clocks = <&stub_clock 0>;
			operating-points-v2 = <&cpu_opp_table>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <311>;
		};

		CLUSTER0_L2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
		};

		CLUSTER1_L2: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	cpu_opp_table: opp-table-0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp00 {
			opp-hz = /bits/ 64 <208000000>;
			opp-microvolt = <1040000>;
			clock-latency-ns = <500000>;
		};
		opp01 {
			opp-hz = /bits/ 64 <432000000>;
			opp-microvolt = <1040000>;
			clock-latency-ns = <500000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <729000000>;
			opp-microvolt = <1090000>;
			clock-latency-ns = <500000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <960000000>;
			opp-microvolt = <1180000>;
			clock-latency-ns = <500000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <1330000>;
			clock-latency-ns = <500000>;
		};
	};

	gic: interrupt-controller@f6801000 {
		compatible = "arm,gic-400";
		reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
		      <0x0 0xf6802000 0 0x2000>, /* GICC */
		      <0x0 0xf6804000 0 0x2000>, /* GICH */
		      <0x0 0xf6806000 0 0x2000>; /* GICV */
		#address-cells = <0>;
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		sram: sram@fff80000 {
			compatible = "hisilicon,hi6220-sramctrl", "syscon";
			reg = <0x0 0xfff80000 0x0 0x12000>;
		};

		ao_ctrl: ao_ctrl@f7800000 {
			compatible = "hisilicon,hi6220-aoctrl", "syscon";
			reg = <0x0 0xf7800000 0x0 0x2000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		sys_ctrl: sys_ctrl@f7030000 {
			compatible = "hisilicon,hi6220-sysctrl", "syscon";
			reg = <0x0 0xf7030000 0x0 0x2000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		media_ctrl: media_ctrl@f4410000 {
			compatible = "hisilicon,hi6220-mediactrl", "syscon";
			reg = <0x0 0xf4410000 0x0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pm_ctrl: pm_ctrl@f7032000 {
			compatible = "hisilicon,hi6220-pmctrl", "syscon";
			reg = <0x0 0xf7032000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		acpu_sctrl: acpu_sctrl@f6504000 {
			compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
			reg = <0x0 0xf6504000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		medianoc_ade: medianoc_ade@f4520000 {
			compatible = "syscon";
			reg = <0x0 0xf4520000 0x0 0x4000>;
		};

		stub_clock: stub_clock {
			compatible = "hisilicon,hi6220-stub-clk";
			hisilicon,hi6220-clk-sram = <&sram>;
			#clock-cells = <1>;
			mbox-names = "mbox-tx";
			mboxes = <&mailbox 1 0 11>;
		};

		uart0: serial@f8015000 {	/* console */
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xf8015000 0x0 0x1000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ao_ctrl HI6220_UART0_PCLK>,
				 <&ao_ctrl HI6220_UART0_PCLK>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart1: serial@f7111000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xf7111000 0x0 0x1000>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sys_ctrl HI6220_UART1_PCLK>,
				 <&sys_ctrl HI6220_UART1_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
			dmas = <&dma0 8 &dma0 9>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart2: serial@f7112000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xf7112000 0x0 0x1000>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sys_ctrl HI6220_UART2_PCLK>,
				 <&sys_ctrl HI6220_UART2_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
			status = "disabled";
		};

		uart3: serial@f7113000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xf7113000 0x0 0x1000>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sys_ctrl HI6220_UART3_PCLK>,
				 <&sys_ctrl HI6220_UART3_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
			status = "disabled";
		};

		uart4: serial@f7114000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xf7114000 0x0 0x1000>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sys_ctrl HI6220_UART4_PCLK>,
				 <&sys_ctrl HI6220_UART4_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
			status = "disabled";
		};

		dma0: dma@f7370000 {
			compatible = "hisilicon,k3-dma-1.0";
			reg = <0x0 0xf7370000 0x0 0x1000>;
			#dma-cells = <1>;
			dma-channels = <15>;
			dma-requests = <32>;
			interrupts = <0 84 4>;
			clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
			dma-no-cci;
			dma-type = "hi6220_dma";
			status = "okay";
		};

		dual_timer0: timer@f8008000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x0 0xf8008000 0x0 0x1000>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
				 <&ao_ctrl HI6220_TIMER0_PCLK>,
				 <&ao_ctrl HI6220_TIMER0_PCLK>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		rtc0: rtc@f8003000 {
			compatible = "arm,pl031", "arm,primecell";
			reg = <0x0 0xf8003000 0x0 0x1000>;
			interrupts = <0 12 4>;
			clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
			clock-names = "apb_pclk";
		};

		rtc1: rtc@f8004000 {
			compatible = "arm,pl031", "arm,primecell";
			reg = <0x0 0xf8004000 0x0 0x1000>;
			interrupts = <0 8 4>;
			clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
			clock-names = "apb_pclk";
		};

		pmx0: pinmux@f7010000 {
			compatible = "pinctrl-single";
			reg = <0x0 0xf7010000  0x0 0x27c>;
			#address-cells = <1>;
			#size-cells = <1>;
			#pinctrl-cells = <1>;
			#gpio-range-cells = <3>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <7>;
			pinctrl-single,gpio-range = <
				&range  80  8 MUX_M0 /* gpio  3: [0..7] */
				&range  88  8 MUX_M0 /* gpio  4: [0..7] */
				&range  96  8 MUX_M0 /* gpio  5: [0..7] */
				&range 104  8 MUX_M0 /* gpio  6: [0..7] */
				&range 112  8 MUX_M0 /* gpio  7: [0..7] */
				&range 120  2 MUX_M0 /* gpio  8: [0..1] */
				&range   2  6 MUX_M1 /* gpio  8: [2..7] */
				&range   8  8 MUX_M1 /* gpio  9: [0..7] */
				&range   0  1 MUX_M1 /* gpio 10: [0]    */
				&range  16  7 MUX_M1 /* gpio 10: [1..7] */
				&range  23  3 MUX_M1 /* gpio 11: [0..2] */
				&range  28  5 MUX_M1 /* gpio 11: [3..7] */
				&range  33  3 MUX_M1 /* gpio 12: [0..2] */
				&range  43  5 MUX_M1 /* gpio 12: [3..7] */
				&range  48  8 MUX_M1 /* gpio 13: [0..7] */
				&range  56  8 MUX_M1 /* gpio 14: [0..7] */
				&range  74  6 MUX_M1 /* gpio 15: [0..5] */
				&range 122  1 MUX_M1 /* gpio 15: [6]    */
				&range 126  1 MUX_M1 /* gpio 15: [7]    */
				&range 127  8 MUX_M1 /* gpio 16: [0..7] */
				&range 135  8 MUX_M1 /* gpio 17: [0..7] */
				&range 143  8 MUX_M1 /* gpio 18: [0..7] */
				&range 151  8 MUX_M1 /* gpio 19: [0..7] */
			>;
			range: gpio-range {
				#pinctrl-single,gpio-range-cells = <3>;
			};
		};

		pmx1: pinmux@f7010800 {
			compatible = "pinconf-single";
			reg = <0x0 0xf7010800 0x0 0x28c>;
			#address-cells = <1>;
			#size-cells = <1>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <32>;
		};

		pmx2: pinmux@f8001800 {
			compatible = "pinconf-single";
			reg = <0x0 0xf8001800 0x0 0x78>;
			#address-cells = <1>;
			#size-cells = <1>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <32>;
		};

		gpio0: gpio@f8011000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf8011000 0x0 0x1000>;
			interrupts = <0 52 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio1: gpio@f8012000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf8012000 0x0 0x1000>;
			interrupts = <0 53 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio2: gpio@f8013000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf8013000 0x0 0x1000>;
			interrupts = <0 54 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio3: gpio@f8014000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf8014000 0x0 0x1000>;
			interrupts = <0 55 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 80 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio4: gpio@f7020000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf7020000 0x0 0x1000>;
			interrupts = <0 56 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 88 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio5: gpio@f7021000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf7021000 0x0 0x1000>;
			interrupts = <0 57 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 96 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio6: gpio@f7022000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf7022000 0x0 0x1000>;
			interrupts = <0 58 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 104 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio7: gpio@f7023000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf7023000 0x0 0x1000>;
			interrupts = <0 59 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 112 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio8: gpio@f7024000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf7024000 0x0 0x1000>;
			interrupts = <0 60 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio9: gpio@f7025000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf7025000 0x0 0x1000>;
			interrupts = <0 61 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 8 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio10: gpio@f7026000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf7026000 0x0 0x1000>;
			interrupts = <0 62 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio11: gpio@f7027000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf7027000 0x0 0x1000>;
			interrupts = <0 63 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio12: gpio@f7028000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf7028000 0x0 0x1000>;
			interrupts = <0 64 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio13: gpio@f7029000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf7029000 0x0 0x1000>;
			interrupts = <0 65 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 48 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio14: gpio@f702a000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf702a000 0x0 0x1000>;
			interrupts = <0 66 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 56 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio15: gpio@f702b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf702b000 0x0 0x1000>;
			interrupts = <0 67 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <
				&pmx0 0 74 6
				&pmx0 6 122 1
				&pmx0 7 126 1
			>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio16: gpio@f702c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf702c000 0x0 0x1000>;
			interrupts = <0 68 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 127 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio17: gpio@f702d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf702d000 0x0 0x1000>;
			interrupts = <0 69 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 135 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio18: gpio@f702e000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf702e000 0x0 0x1000>;
			interrupts = <0 70 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 143 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		gpio19: gpio@f702f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x0 0xf702f000 0x0 0x1000>;
			interrupts = <0 71 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 151 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&ao_ctrl 2>;
			clock-names = "apb_pclk";
		};

		spi0: spi@f7106000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x0 0xf7106000 0x0 0x1000>;
			interrupts = <0 50 4>;
			bus-id = <0>;
			enable-dma = <0>;
			clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>;
			clock-names = "sspclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
			num-cs = <1>;
			cs-gpios = <&gpio6 2 0>;
			status = "disabled";
		};

		i2c0: i2c@f7100000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xf7100000 0x0 0x1000>;
			interrupts = <0 44 4>;
			clocks = <&sys_ctrl HI6220_I2C0_CLK>;
			i2c-sda-hold-time-ns = <300>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
			status = "disabled";
		};

		i2c1: i2c@f7101000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xf7101000 0x0 0x1000>;
			clocks = <&sys_ctrl HI6220_I2C1_CLK>;
			interrupts = <0 45 4>;
			i2c-sda-hold-time-ns = <300>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
			status = "disabled";
		};

		i2c2: i2c@f7102000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xf7102000 0x0 0x1000>;
			clocks = <&sys_ctrl HI6220_I2C2_CLK>;
			interrupts = <0 46 4>;
			i2c-sda-hold-time-ns = <300>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
			status = "disabled";
		};

		usb_phy: usbphy {
			compatible = "hisilicon,hi6220-usb-phy";
			#phy-cells = <0>;
			phy-supply = <&reg_5v_hub>;
			hisilicon,peripheral-syscon = <&sys_ctrl>;
		};

		usb: usb@f72c0000 {
			compatible = "hisilicon,hi6220-usb";
			reg = <0x0 0xf72c0000 0x0 0x40000>;
			phys = <&usb_phy>;
			phy-names = "usb2-phy";
			clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
			clock-names = "otg";
			dr_mode = "otg";
			g-rx-fifo-size = <512>;
			g-np-tx-fifo-size = <128>;
			g-tx-fifo-size = <128 128 128 128 128 128 128 128
					   16  16  16  16  16  16  16>;
			interrupts = <0 77 0x4>;
		};

		mailbox: mailbox@f7510000 {
			compatible = "hisilicon,hi6220-mbox";
			reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
			      <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			#mbox-cells = <3>;
		};

		dwmmc_0: dwmmc0@f723d000 {
			compatible = "hisilicon,hi6220-dw-mshc";
			reg = <0x0 0xf723d000 0x0 0x1000>;
			interrupts = <0x0 0x48 0x4>;
			clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
			clock-names = "ciu", "biu";
			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
			reset-names = "reset";
			pinctrl-names = "default";
			pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
				     &emmc_cfg_func &emmc_rst_cfg_func>;
		};

		dwmmc_1: dwmmc1@f723e000 {
			compatible = "hisilicon,hi6220-dw-mshc";
			hisilicon,peripheral-syscon = <&ao_ctrl>;
			reg = <0x0 0xf723e000 0x0 0x1000>;
			interrupts = <0x0 0x49 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
			clock-names = "ciu", "biu";
			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
			reset-names = "reset";
			pinctrl-names = "default", "idle";
			pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
			pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
		};

		dwmmc_2: dwmmc2@f723f000 {
			compatible = "hisilicon,hi6220-dw-mshc";
			reg = <0x0 0xf723f000 0x0 0x1000>;
			interrupts = <0x0 0x4a 0x4>;
			clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
			clock-names = "ciu", "biu";
			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
			reset-names = "reset";
			pinctrl-names = "default", "idle";
			pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
			pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
		};

		watchdog0: watchdog@f8005000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xf8005000 0x0 0x1000>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&ao_ctrl HI6220_WDT0_PCLK>,
				 <&ao_ctrl HI6220_WDT0_PCLK>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		tsensor: tsensor@0,f7030700 {
			compatible = "hisilicon,tsensor";
			reg = <0x0 0xf7030700 0x0 0x1000>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sys_ctrl 22>;
			clock-names = "thermal_clk";
			#thermal-sensor-cells = <1>;
		};

		i2s0: i2s@f7118000{
			compatible = "hisilicon,hi6210-i2s";
			reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
			clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
				 <&sys_ctrl HI6220_BBPPLL0_DIV>;
			clock-names = "dacodec", "i2s-base";
			dmas = <&dma0 15 &dma0 14>;
			dma-names = "rx", "tx";
			hisilicon,sysctrl-syscon = <&sys_ctrl>;
			#sound-dai-cells = <1>;
		};

		thermal-zones {

			cls0: cls0-thermal {
				polling-delay = <1000>;
				polling-delay-passive = <100>;
				sustainable-power = <3326>;

				/* sensor ID */
				thermal-sensors = <&tsensor 2>;

				trips {
					threshold: trip-point0 {
						temperature = <65000>;
						hysteresis = <0>;
						type = "passive";
					};

					target: trip-point1 {
						temperature = <75000>;
						hysteresis = <0>;
						type = "passive";
					};
				};

				cooling-maps {
					map0 {
						trip = <&target>;
						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
								 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
					};
				};
			};
		};

		ade: ade@f4100000 {
			compatible = "hisilicon,hi6220-ade";
			reg = <0x0 0xf4100000 0x0 0x7800>;
			reg-names = "ade_base";
			hisilicon,noc-syscon = <&medianoc_ade>;
			resets = <&media_ctrl MEDIA_ADE>;
			interrupts = <0 115 4>; /* ldi interrupt */

			clocks = <&media_ctrl HI6220_ADE_CORE>,
				 <&media_ctrl HI6220_CODEC_JPEG>,
				 <&media_ctrl HI6220_ADE_PIX_SRC>;
			/*clock name*/
			clock-names  = "clk_ade_core",
				       "clk_codec_jpeg",
				       "clk_ade_pix";

			assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
				<&media_ctrl HI6220_CODEC_JPEG>;
			assigned-clock-rates = <360000000>, <288000000>;
			dma-coherent;
			status = "disabled";

			port {
				ade_out: endpoint {
					remote-endpoint = <&dsi_in>;
				};
			};
		};

		dsi: dsi@f4107800 {
			compatible = "hisilicon,hi6220-dsi";
			reg = <0x0 0xf4107800 0x0 0x100>;
			clocks = <&media_ctrl  HI6220_DSI_PCLK>;
			clock-names = "pclk";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				/* 0 for input port */
				port@0 {
					reg = <0>;
					dsi_in: endpoint {
						remote-endpoint = <&ade_out>;
					};
				};
			};
		};

		debug@f6590000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			reg = <0 0xf6590000 0 0x1000>;
			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu0>;
		};

		debug@f6592000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			reg = <0 0xf6592000 0 0x1000>;
			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu1>;
		};

		debug@f6594000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			reg = <0 0xf6594000 0 0x1000>;
			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu2>;
		};

		debug@f6596000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			reg = <0 0xf6596000 0 0x1000>;
			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu3>;
		};

		debug@f65d0000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			reg = <0 0xf65d0000 0 0x1000>;
			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu4>;
		};

		debug@f65d2000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			reg = <0 0xf65d2000 0 0x1000>;
			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu5>;
		};

		debug@f65d4000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			reg = <0 0xf65d4000 0 0x1000>;
			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu6>;
		};

		debug@f65d6000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			reg = <0 0xf65d6000 0 0x1000>;
			clocks = <&sys_ctrl HI6220_DAPB_CLK>;
			clock-names = "apb_pclk";
			cpu = <&cpu7>;
		};

		mali: gpu@f4080000 {
			compatible = "hisilicon,hi6220-mali", "arm,mali-450";
			reg = <0x0 0xf4080000 0x0 0x00040000>;
			interrupt-parent = <&gic>;
			interrupts =	<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "gp",
					  "gpmmu",
					  "pp",
					  "pp0",
					  "ppmmu0",
					  "pp1",
					  "ppmmu1",
					  "pp2",
					  "ppmmu2",
					  "pp3",
					  "ppmmu3";
			clocks = <&media_ctrl HI6220_G3D_CLK>,
				 <&media_ctrl HI6220_G3D_PCLK>;
			clock-names = "bus", "core";
			assigned-clocks = <&media_ctrl HI6220_G3D_CLK>,
					  <&media_ctrl HI6220_G3D_PCLK>;
			assigned-clock-rates = <500000000>, <144000000>;
			reset-names = "ao_g3d", "media_g3d";
			resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>;
		};
	};
};

#include "hi6220-coresight.dtsi"