code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2014 Freescale Semiconductor, Inc.

#include <dt-bindings/clock/imx6sx-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6sx-pinfunc.h"

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 */
	chosen {};

	aliases {
		can0 = &flexcan1;
		can1 = &flexcan2;
		ethernet0 = &fec1;
		ethernet1 = &fec2;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		gpio6 = &gpio7;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		mmc3 = &usdhc4;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &ecspi3;
		spi3 = &ecspi4;
		spi4 = &ecspi5;
		usb0 = &usbotg1;
		usb1 = &usbotg2;
		usb2 = &usbh;
		usbphy0 = &usbphy1;
		usbphy1 = &usbphy2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			operating-points = <
				/* kHz    uV */
				996000  1250000
				792000  1175000
				396000  1075000
				198000	975000
			>;
			fsl,soc-operating-points = <
				/* ARM kHz  SOC uV */
				996000      1175000
				792000      1175000
				396000      1175000
				198000	    1175000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			#cooling-cells = <2>;
			clocks = <&clks IMX6SX_CLK_ARM>,
				 <&clks IMX6SX_CLK_PLL2_PFD2>,
				 <&clks IMX6SX_CLK_STEP>,
				 <&clks IMX6SX_CLK_PLL1_SW>,
				 <&clks IMX6SX_CLK_PLL1_SYS>;
			clock-names = "arm", "pll2_pfd2_396m", "step",
				      "pll1_sw", "pll1_sys";
			arm-supply = <&reg_arm>;
			soc-supply = <&reg_soc>;
			nvmem-cells = <&cpu_speed_grade>;
			nvmem-cell-names = "speed_grade";
		};
	};

	ckil: clock-ckil {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "ckil";
	};

	osc: clock-osc {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc";
	};

	ipp_di0: clock-ipp-di0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "ipp_di0";
	};

	ipp_di1: clock-ipp-di1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "ipp_di1";
	};

	anaclk1: clock-anaclk1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "anaclk1";
	};

	anaclk2: clock-anaclk2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "anaclk2";
	};

	mqs: mqs {
		compatible = "fsl,imx6sx-mqs";
		gpr = <&gpr>;
		status = "disabled";
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupt-parent = <&gpc>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	};

	usbphynop1: usbphynop1 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gpc>;
		ranges;

		ocram_s: sram@8f8000 {
			compatible = "mmio-sram";
			reg = <0x008f8000 0x4000>;
			ranges = <0 0x008f8000 0x4000>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&clks IMX6SX_CLK_OCRAM_S>;
		};

		ocram: sram@900000 {
			compatible = "mmio-sram";
			reg = <0x00900000 0x20000>;
			ranges = <0 0x00900000 0x20000>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&clks IMX6SX_CLK_OCRAM>;
		};

		intc: interrupt-controller@a01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x00a01000 0x1000>,
			      <0x00a00100 0x100>;
			interrupt-parent = <&intc>;
		};

		L2: cache-controller@a02000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a02000 0x1000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-level = <2>;
			arm,tag-latency = <4 2 3>;
			arm,data-latency = <4 2 3>;
		};

		gpu: gpu@1800000 {
			compatible = "vivante,gc";
			reg = <0x01800000 0x4000>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6SX_CLK_GPU>,
				 <&clks IMX6SX_CLK_GPU>,
				 <&clks IMX6SX_CLK_GPU>;
			clock-names = "bus", "core", "shader";
			power-domains = <&pd_pu>;
		};

		dma_apbh: dma-apbh@1804000 {
			compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
			reg = <0x01804000 0x2000>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
			#dma-cells = <1>;
			dma-channels = <4>;
			clocks = <&clks IMX6SX_CLK_APBH_DMA>;
		};

		gpmi: nand-controller@1806000{
			compatible = "fsl,imx6sx-gpmi-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
			reg-names = "gpmi-nand", "bch";
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "bch";
			clocks = <&clks IMX6SX_CLK_GPMI_IO>,
				 <&clks IMX6SX_CLK_GPMI_APB>,
				 <&clks IMX6SX_CLK_GPMI_BCH>,
				 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
				 <&clks IMX6SX_CLK_PER1_BCH>;
			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
				      "gpmi_bch_apb", "per1_bch";
			dmas = <&dma_apbh 0>;
			dma-names = "rx-tx";
			status = "disabled";
		};

		aips1: bus@2000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02000000 0x100000>;
			ranges;

			spba-bus@2000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x02000000 0x40000>;
				ranges;

				spdif: spdif@2004000 {
					compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
					reg = <0x02004000 0x4000>;
					interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&sdma 14 18 0>,
					       <&sdma 15 18 0>;
					dma-names = "rx", "tx";
					clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
						 <&clks IMX6SX_CLK_OSC>,
						 <&clks IMX6SX_CLK_SPDIF>,
						 <&clks 0>, <&clks 0>, <&clks 0>,
						 <&clks IMX6SX_CLK_IPG>,
						 <&clks 0>, <&clks 0>,
						 <&clks IMX6SX_CLK_SPBA>;
					clock-names = "core", "rxtx0",
						      "rxtx1", "rxtx2",
						      "rxtx3", "rxtx4",
						      "rxtx5", "rxtx6",
						      "rxtx7", "spba";
					status = "disabled";
				};

				ecspi1: spi@2008000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
					reg = <0x02008000 0x4000>;
					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_ECSPI1>,
						 <&clks IMX6SX_CLK_ECSPI1>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi2: spi@200c000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
					reg = <0x0200c000 0x4000>;
					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_ECSPI2>,
						 <&clks IMX6SX_CLK_ECSPI2>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi3: spi@2010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
					reg = <0x02010000 0x4000>;
					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_ECSPI3>,
						 <&clks IMX6SX_CLK_ECSPI3>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi4: spi@2014000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
					reg = <0x02014000 0x4000>;
					interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_ECSPI4>,
						 <&clks IMX6SX_CLK_ECSPI4>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				uart1: serial@2020000 {
					compatible = "fsl,imx6sx-uart",
						     "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02020000 0x4000>;
					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_UART_IPG>,
						 <&clks IMX6SX_CLK_UART_SERIAL>;
					clock-names = "ipg", "per";
					dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				esai: esai@2024000 {
					compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
					reg = <0x02024000 0x4000>;
					interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
						 <&clks IMX6SX_CLK_ESAI_MEM>,
						 <&clks IMX6SX_CLK_ESAI_EXTAL>,
						 <&clks IMX6SX_CLK_ESAI_IPG>,
						 <&clks IMX6SX_CLK_SPBA>;
					clock-names = "core", "mem", "extal",
						      "fsys", "spba";
					dmas = <&sdma 23 21 0>,
					       <&sdma 24 21 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				ssi1: ssi@2028000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
					reg = <0x02028000 0x4000>;
					interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
						 <&clks IMX6SX_CLK_SSI1>;
					clock-names = "ipg", "baud";
					dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				ssi2: ssi@202c000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
					reg = <0x0202c000 0x4000>;
					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
						 <&clks IMX6SX_CLK_SSI2>;
					clock-names = "ipg", "baud";
					dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				ssi3: ssi@2030000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
					reg = <0x02030000 0x4000>;
					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
						 <&clks IMX6SX_CLK_SSI3>;
					clock-names = "ipg", "baud";
					dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				asrc: asrc@2034000 {
					compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
					reg = <0x02034000 0x4000>;
					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
						<&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
						<&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
						<&clks IMX6SX_CLK_SPBA>;
					clock-names = "mem", "ipg", "asrck_0",
						"asrck_1", "asrck_2", "asrck_3", "asrck_4",
						"asrck_5", "asrck_6", "asrck_7", "asrck_8",
						"asrck_9", "asrck_a", "asrck_b", "asrck_c",
						"asrck_d", "asrck_e", "asrck_f", "spba";
					dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
					       <&sdma 19 23 1>, <&sdma 20 23 1>,
					       <&sdma 21 23 1>, <&sdma 22 23 1>;
					dma-names = "rxa", "rxb", "rxc",
						    "txa", "txb", "txc";
					fsl,asrc-rate  = <48000>;
					fsl,asrc-width = <16>;
					status = "okay";
				};
			};

			pwm1: pwm@2080000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x02080000 0x4000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM1>,
					 <&clks IMX6SX_CLK_PWM1>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
			};

			pwm2: pwm@2084000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x02084000 0x4000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM2>,
					 <&clks IMX6SX_CLK_PWM2>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
			};

			pwm3: pwm@2088000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x02088000 0x4000>;
				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM3>,
					 <&clks IMX6SX_CLK_PWM3>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
			};

			pwm4: pwm@208c000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x0208c000 0x4000>;
				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM4>,
					 <&clks IMX6SX_CLK_PWM4>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
			};

			flexcan1: can@2090000 {
				compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
				reg = <0x02090000 0x4000>;
				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
					 <&clks IMX6SX_CLK_CAN1_SERIAL>;
				clock-names = "ipg", "per";
				fsl,stop-mode = <&gpr 0x10 1>;
				status = "disabled";
			};

			flexcan2: can@2094000 {
				compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
				reg = <0x02094000 0x4000>;
				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
					 <&clks IMX6SX_CLK_CAN2_SERIAL>;
				clock-names = "ipg", "per";
				fsl,stop-mode = <&gpr 0x10 2>;
				status = "disabled";
			};

			gpt: timer@2098000 {
				compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
				reg = <0x02098000 0x4000>;
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_GPT_BUS>,
					 <&clks IMX6SX_CLK_GPT_3M>;
				clock-names = "ipg", "per";
			};

			gpio1: gpio@209c000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x0209c000 0x4000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 5 26>;
			};

			gpio2: gpio@20a0000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x020a0000 0x4000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 31 20>;
			};

			gpio3: gpio@20a4000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x020a4000 0x4000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 51 29>;
			};

			gpio4: gpio@20a8000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x020a8000 0x4000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 80 32>;
			};

			gpio5: gpio@20ac000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x020ac000 0x4000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 112 24>;
			};

			gpio6: gpio@20b0000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x020b0000 0x4000>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
			};

			gpio7: gpio@20b4000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x020b4000 0x4000>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
			};

			kpp: keypad@20b8000 {
				compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
				reg = <0x020b8000 0x4000>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>;
				status = "disabled";
			};

			wdog1: watchdog@20bc000 {
				compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
				reg = <0x020bc000 0x4000>;
				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>;
			};

			wdog2: watchdog@20c0000 {
				compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
				reg = <0x020c0000 0x4000>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>;
				status = "disabled";
			};

			clks: clock-controller@20c4000 {
				compatible = "fsl,imx6sx-ccm";
				reg = <0x020c4000 0x4000>;
				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
				#clock-cells = <1>;
				clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
				clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
			};

			anatop: anatop@20c8000 {
				compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
					     "syscon", "simple-mfd";
				reg = <0x020c8000 0x1000>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

				reg_vdd1p1: regulator-1p1 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd1p1";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
					anatop-reg-offset = <0x110>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <4>;
					anatop-min-voltage = <800000>;
					anatop-max-voltage = <1375000>;
					anatop-enable-bit = <0>;
				};

				reg_vdd3p0: regulator-3p0 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd3p0";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <3150000>;
					regulator-always-on;
					anatop-reg-offset = <0x120>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
					anatop-min-voltage = <2625000>;
					anatop-max-voltage = <3400000>;
					anatop-enable-bit = <0>;
				};

				reg_vdd2p5: regulator-2p5 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd2p5";
					regulator-min-microvolt = <2250000>;
					regulator-max-microvolt = <2750000>;
					regulator-always-on;
					anatop-reg-offset = <0x130>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
					anatop-min-voltage = <2100000>;
					anatop-max-voltage = <2875000>;
					anatop-enable-bit = <0>;
				};

				reg_arm: regulator-vddcore {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddarm";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <0>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <24>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				reg_pcie: regulator-vddpcie {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddpcie";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <9>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <26>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				reg_soc: regulator-vddsoc {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddsoc";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <18>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <28>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				tempmon: tempmon {
					compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
					interrupt-parent = <&gpc>;
					interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
					fsl,tempmon = <&anatop>;
					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
					nvmem-cell-names = "calib", "temp_grade";
					clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
				};
			};

			usbphy1: usbphy@20c9000 {
				compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
				reg = <0x020c9000 0x1000>;
				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USBPHY1>;
				fsl,anatop = <&anatop>;
			};

			usbphy2: usbphy@20ca000 {
				compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
				reg = <0x020ca000 0x1000>;
				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USBPHY2>;
				fsl,anatop = <&anatop>;
			};

			snvs: snvs@20cc000 {
				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
				reg = <0x020cc000 0x4000>;

				snvs_rtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap = <&snvs>;
					offset = <0x34>;
					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				};

				snvs_poweroff: snvs-poweroff {
					compatible = "syscon-poweroff";
					regmap = <&snvs>;
					offset = <0x38>;
					value = <0x60>;
					mask = <0x60>;
					status = "disabled";
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
					linux,keycode = <KEY_POWER>;
					wakeup-source;
					status = "disabled";
				};
			};

			epit1: epit@20d0000 {
				reg = <0x020d0000 0x4000>;
				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			epit2: epit@20d4000 {
				reg = <0x020d4000 0x4000>;
				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			};

			src: reset-controller@20d8000 {
				compatible = "fsl,imx6sx-src", "fsl,imx51-src";
				reg = <0x020d8000 0x4000>;
				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};

			gpc: gpc@20dc000 {
				compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
				reg = <0x020dc000 0x4000>;
				interrupt-controller;
				#interrupt-cells = <3>;
				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-parent = <&intc>;
				clocks = <&clks IMX6SX_CLK_IPG>;
				clock-names = "ipg";

				pgc {
					#address-cells = <1>;
					#size-cells = <0>;

					power-domain@0 {
						reg = <0>;
						#power-domain-cells = <0>;
					};

					pd_pu: power-domain@1 {
						reg = <1>;
						#power-domain-cells = <0>;
						power-supply = <&reg_soc>;
						clocks = <&clks IMX6SX_CLK_GPU>;
					};

					pd_disp: power-domain@2 {
						reg = <2>;
						#power-domain-cells = <0>;
						clocks = <&clks IMX6SX_CLK_PXP_AXI>,
							 <&clks IMX6SX_CLK_DISPLAY_AXI>,
							 <&clks IMX6SX_CLK_LCDIF1_PIX>,
							 <&clks IMX6SX_CLK_LCDIF_APB>,
							 <&clks IMX6SX_CLK_LCDIF2_PIX>,
							 <&clks IMX6SX_CLK_CSI>,
							 <&clks IMX6SX_CLK_VADC>;
					};

					pd_pci: power-domain@3 {
						reg = <3>;
						#power-domain-cells = <0>;
						power-supply = <&reg_pcie>;
					};
				};
			};

			iomuxc: pinctrl@20e0000 {
				compatible = "fsl,imx6sx-iomuxc";
				reg = <0x020e0000 0x4000>;
			};

			gpr: iomuxc-gpr@20e4000 {
				compatible = "fsl,imx6sx-iomuxc-gpr",
					     "fsl,imx6q-iomuxc-gpr", "syscon";
				reg = <0x020e4000 0x4000>;
			};

			sdma: dma-controller@20ec000 {
				compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
				reg = <0x020ec000 0x4000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>,
					 <&clks IMX6SX_CLK_SDMA>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				/* imx6sx reuses imx6q sdma firmware */
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
			};
		};

		aips2: bus@2100000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02100000 0x100000>;
			ranges;

			crypto: crypto@2100000 {
				compatible = "fsl,sec-v4.0";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x2100000 0x10000>;
				ranges = <0 0x2100000 0x10000>;
				interrupt-parent = <&intc>;
				clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
					 <&clks IMX6SX_CLK_CAAM_ACLK>,
					 <&clks IMX6SX_CLK_CAAM_IPG>,
					 <&clks IMX6SX_CLK_EIM_SLOW>;
				clock-names = "mem", "aclk", "ipg", "emi_slow";

				sec_jr0: jr@1000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x1000 0x1000>;
					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr1: jr@2000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x2000 0x1000>;
					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			usbotg1: usb@2184000 {
				compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
				reg = <0x02184000 0x200>;
				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USBOH3>;
				fsl,usbphy = <&usbphy1>;
				fsl,usbmisc = <&usbmisc 0>;
				fsl,anatop = <&anatop>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbotg2: usb@2184200 {
				compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
				reg = <0x02184200 0x200>;
				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USBOH3>;
				fsl,usbphy = <&usbphy2>;
				fsl,usbmisc = <&usbmisc 1>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbh: usb@2184400 {
				compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
				reg = <0x02184400 0x200>;
				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USBOH3>;
				fsl,usbphy = <&usbphynop1>;
				fsl,usbmisc = <&usbmisc 2>;
				phy_type = "hsic";
				fsl,anatop = <&anatop>;
				dr_mode = "host";
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbmisc: usbmisc@2184800 {
				#index-cells = <1>;
				compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
				reg = <0x02184800 0x200>;
				clocks = <&clks IMX6SX_CLK_USBOH3>;
			};

			fec1: ethernet@2188000 {
				compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
				reg = <0x02188000 0x4000>;
				interrupt-names = "int0", "pps";
				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_ENET>,
					 <&clks IMX6SX_CLK_ENET_AHB>,
					 <&clks IMX6SX_CLK_ENET_PTP>,
					 <&clks IMX6SX_CLK_ENET_REF>,
					 <&clks IMX6SX_CLK_ENET_PTP>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				fsl,stop-mode = <&gpr 0x10 3>;
				status = "disabled";
			};

			mlb: mlb@218c000 {
				reg = <0x0218c000 0x4000>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_MLB>;
				status = "disabled";
			};

			usdhc1: mmc@2190000 {
				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x02190000 0x4000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USDHC1>,
					 <&clks IMX6SX_CLK_USDHC1>,
					 <&clks IMX6SX_CLK_USDHC1>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@2194000 {
				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x02194000 0x4000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USDHC2>,
					 <&clks IMX6SX_CLK_USDHC2>,
					 <&clks IMX6SX_CLK_USDHC2>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc3: mmc@2198000 {
				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x02198000 0x4000>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USDHC3>,
					 <&clks IMX6SX_CLK_USDHC3>,
					 <&clks IMX6SX_CLK_USDHC3>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc4: mmc@219c000 {
				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x0219c000 0x4000>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USDHC4>,
					 <&clks IMX6SX_CLK_USDHC4>,
					 <&clks IMX6SX_CLK_USDHC4>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			i2c1: i2c@21a0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
				reg = <0x021a0000 0x4000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_I2C1>;
				status = "disabled";
			};

			i2c2: i2c@21a4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
				reg = <0x021a4000 0x4000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_I2C2>;
				status = "disabled";
			};

			i2c3: i2c@21a8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
				reg = <0x021a8000 0x4000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_I2C3>;
				status = "disabled";
			};

			memory-controller@21b0000 {
				compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
				reg = <0x021b0000 0x4000>;
				clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
			};

			fec2: ethernet@21b4000 {
				compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
				reg = <0x021b4000 0x4000>;
				interrupt-names = "int0", "pps";
				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_ENET>,
					 <&clks IMX6SX_CLK_ENET_AHB>,
					 <&clks IMX6SX_CLK_ENET_PTP>,
					 <&clks IMX6SX_CLK_ENET2_REF_125M>,
					 <&clks IMX6SX_CLK_ENET_PTP>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				fsl,stop-mode = <&gpr 0x10 4>;
				status = "disabled";
			};

			weim: weim@21b8000 {
				#address-cells = <2>;
				#size-cells = <1>;
				compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
				reg = <0x021b8000 0x4000>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
				fsl,weim-cs-gpr = <&gpr>;
				status = "disabled";
			};

			ocotp: efuse@21bc000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,imx6sx-ocotp", "syscon";
				reg = <0x021bc000 0x4000>;
				clocks = <&clks IMX6SX_CLK_OCOTP>;

				cpu_speed_grade: speed-grade@10 {
					reg = <0x10 4>;
				};

				tempmon_calib: calib@38 {
					reg = <0x38 4>;
				};

				tempmon_temp_grade: temp-grade@20 {
					reg = <0x20 4>;
				};
			};

			sai1: sai@21d4000 {
				compatible = "fsl,imx6sx-sai";
				reg = <0x021d4000 0x4000>;
				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
					 <&clks IMX6SX_CLK_SAI1>,
					 <&clks 0>, <&clks 0>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dma-names = "rx", "tx";
				dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
				status = "disabled";
			};

			audmux: audmux@21d8000 {
				compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
				reg = <0x021d8000 0x4000>;
				status = "disabled";
			};

			sai2: sai@21dc000 {
				compatible = "fsl,imx6sx-sai";
				reg = <0x021dc000 0x4000>;
				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
					 <&clks IMX6SX_CLK_SAI2>,
					 <&clks 0>, <&clks 0>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dma-names = "rx", "tx";
				dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
				status = "disabled";
			};

			qspi1: spi@21e0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-qspi";
				reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_QSPI1>,
					 <&clks IMX6SX_CLK_QSPI1>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			qspi2: spi@21e4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-qspi";
				reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_QSPI2>,
					 <&clks IMX6SX_CLK_QSPI2>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			uart2: serial@21e8000 {
				compatible = "fsl,imx6sx-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021e8000 0x4000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_UART_IPG>,
					 <&clks IMX6SX_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart3: serial@21ec000 {
				compatible = "fsl,imx6sx-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021ec000 0x4000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_UART_IPG>,
					 <&clks IMX6SX_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart4: serial@21f0000 {
				compatible = "fsl,imx6sx-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021f0000 0x4000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_UART_IPG>,
					 <&clks IMX6SX_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart5: serial@21f4000 {
				compatible = "fsl,imx6sx-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021f4000 0x4000>;
				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_UART_IPG>,
					 <&clks IMX6SX_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			i2c4: i2c@21f8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
				reg = <0x021f8000 0x4000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_I2C4>;
				status = "disabled";
			};
		};

		aips3: bus@2200000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02200000 0x100000>;
			ranges;

			spba-bus@2240000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x02240000 0x40000>;
				ranges;

				csi1: csi@2214000 {
					reg = <0x02214000 0x4000>;
					interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
						 <&clks IMX6SX_CLK_CSI>,
						 <&clks IMX6SX_CLK_DCIC1>;
					clock-names = "disp-axi", "csi_mclk", "dcic";
					status = "disabled";
				};

				pxp: pxp@2218000 {
					compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
					reg = <0x02218000 0x4000>;
					interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_PXP_AXI>;
					clock-names = "axi";
					power-domains = <&pd_disp>;
					status = "disabled";
				};

				csi2: csi@221c000 {
					reg = <0x0221c000 0x4000>;
					interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
						 <&clks IMX6SX_CLK_CSI>,
						 <&clks IMX6SX_CLK_DCIC2>;
					clock-names = "disp-axi", "csi_mclk", "dcic";
					status = "disabled";
				};

				lcdif1: lcdif@2220000 {
					compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
					reg = <0x02220000 0x4000>;
					interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
					clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
						 <&clks IMX6SX_CLK_LCDIF_APB>,
						 <&clks IMX6SX_CLK_DISPLAY_AXI>;
					clock-names = "pix", "axi", "disp_axi";
					power-domains = <&pd_disp>;
					status = "disabled";
				};

				lcdif2: lcdif@2224000 {
					compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
					reg = <0x02224000 0x4000>;
					interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
					clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
						 <&clks IMX6SX_CLK_LCDIF_APB>,
						 <&clks IMX6SX_CLK_DISPLAY_AXI>;
					clock-names = "pix", "axi", "disp_axi";
					power-domains = <&pd_disp>;
					status = "disabled";
				};

				vadc: vadc@2228000 {
					reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
					reg-names = "vadc-vafe", "vadc-vdec";
					clocks = <&clks IMX6SX_CLK_VADC>,
						 <&clks IMX6SX_CLK_CSI>;
					clock-names = "vadc", "csi";
					power-domains = <&pd_disp>;
					status = "disabled";
				};
			};

			adc1: adc@2280000 {
				compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
				reg = <0x02280000 0x4000>;
				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>;
				clock-names = "adc";
				fsl,adck-max-frequency = <30000000>, <40000000>,
							 <20000000>;
				status = "disabled";
			};

			adc2: adc@2284000 {
				compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
				reg = <0x02284000 0x4000>;
				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>;
				clock-names = "adc";
				fsl,adck-max-frequency = <30000000>, <40000000>,
							 <20000000>;
				status = "disabled";
			};

			wdog3: watchdog@2288000 {
				compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
				reg = <0x02288000 0x4000>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>;
				status = "disabled";
			};

			ecspi5: spi@228c000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
				reg = <0x0228c000 0x4000>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_ECSPI5>,
					 <&clks IMX6SX_CLK_ECSPI5>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart6: serial@22a0000 {
				compatible = "fsl,imx6sx-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x022a0000 0x4000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_UART_IPG>,
					 <&clks IMX6SX_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			pwm5: pwm@22a4000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x022a4000 0x4000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM5>,
					 <&clks IMX6SX_CLK_PWM5>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
			};

			pwm6: pwm@22a8000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x022a8000 0x4000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM6>,
					 <&clks IMX6SX_CLK_PWM6>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
			};

			pwm7: pwm@22ac000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x022ac000 0x4000>;
				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM7>,
					 <&clks IMX6SX_CLK_PWM7>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
			};

			pwm8: pwm@22b0000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x022b0000 0x4000>;
				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM8>,
					 <&clks IMX6SX_CLK_PWM8>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
			};
		};

		pcie: pcie@8ffc000 {
			compatible = "fsl,imx6sx-pcie";
			reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
			reg-names = "dbi", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			bus-range = <0x00 0xff>;
			ranges = <0x81000000 0 0          0x08f80000 0 0x00010000>, /* downstream I/O */
				 <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
			num-lanes = <1>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
				 <&clks IMX6SX_CLK_LVDS1_OUT>,
				 <&clks IMX6SX_CLK_PCIE_REF_125M>,
				 <&clks IMX6SX_CLK_DISPLAY_AXI>;
			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
			power-domains = <&pd_disp>, <&pd_pci>;
			power-domain-names = "pcie", "pcie_phy";
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2015 Freescale Semiconductor, Inc.

/dts-v1/;

#include "imx6ul.dtsi"
#include "imx6ul-14x14-evk.dtsi"

/ {
	model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
	compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
//
// Copyright (C) 2015 Freescale Semiconductor, Inc.

/ {
	chosen {
		stdout-path = &uart1;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	backlight_display: backlight-display {
		compatible = "pwm-backlight";
		pwms = <&pwm1 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
		status = "okay";
	};

	reg_sd1_vmmc: regulator-sd1-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_peri_3v3: regulator-peri-3v3 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_peri_3v3>;
		regulator-name = "VPERI_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
		/*
		 * If you want to want to make this dynamic please
		 * check schematics and test all affected peripherals:
		 *
		 * - sensors
		 * - ethernet phy
		 * - can
		 * - bluetooth
		 * - wm8960 audio codec
		 * - ov5640 camera
		 */
		regulator-always-on;
	};

	reg_can_3v3: regulator-can-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "can-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
	};

	sound-wm8960 {
		compatible = "fsl,imx-audio-wm8960";
		model = "wm8960-audio";
		audio-cpu = <&sai2>;
		audio-codec = <&codec>;
		audio-asrc = <&asrc>;
		hp-det-gpio = <&gpio5 4 0>;
		audio-routing =
			"Headphone Jack", "HP_L",
			"Headphone Jack", "HP_R",
			"Ext Spk", "SPK_LP",
			"Ext Spk", "SPK_LN",
			"Ext Spk", "SPK_RP",
			"Ext Spk", "SPK_RN",
			"LINPUT2", "Mic Jack",
			"LINPUT3", "Mic Jack",
			"RINPUT1", "AMIC",
			"RINPUT2", "AMIC",
			"Mic Jack", "MICB",
			"AMIC", "MICB";
	};

	spi-4 {
		compatible = "spi-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_spi4>;
		status = "okay";
		gpio-sck = <&gpio5 11 0>;
		gpio-mosi = <&gpio5 10 0>;
		cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
		num-chipselects = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		gpio_spi: gpio@0 {
			compatible = "fairchild,74hc595";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0>;
			registers-number = <1>;
			spi-max-frequency = <100000>;
			enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
		};
	};

	panel {
		compatible = "innolux,at043tn24";
		backlight = <&backlight_display>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&display_out>;
			};
		};
	};
};

&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <786432000>;
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	codec: wm8960@1a {
		#sound-dai-cells = <0>;
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		wlf,shared-lrclk;
		wlf,hp-cfg = <3 2 3>;
		wlf,gpio-cfg = <1 3>;
		clocks = <&clks IMX6UL_CLK_SAI2>;
		clock-names = "mclk";
	};

	camera@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_camera_clock>;
		clocks = <&clks IMX6UL_CLK_CSI>;
		clock-names = "xclk";
		powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>;

		port {
			ov5640_to_parallel: endpoint {
				remote-endpoint = <&parallel_from_ov5640>;
				bus-width = <8>;
				data-shift = <2>; /* lines 9:2 are used */
				hsync-active = <0>;
				vsync-active = <0>;
				pclk-sample = <1>;
			};
		};
	};
};

&csi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_csi1>;
	status = "okay";

	port {
		parallel_from_ov5640: endpoint {
			remote-endpoint = <&ov5640_to_parallel>;
			bus-type = <5>; /* Parallel bus */
		};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	phy-supply = <&reg_peri_3v3>;
	status = "okay";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_peri_3v3>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@2 {
			compatible = "ethernet-phy-id0022.1560";
			reg = <2>;
			micrel,led-mode = <1>;
			clocks = <&clks IMX6UL_CLK_ENET_REF>;
			clock-names = "rmii-ref";

		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-id0022.1560";
			reg = <1>;
			micrel,led-mode = <1>;
			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
			clock-names = "rmii-ref";
		};
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can_3v3>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can_3v3>;
	status = "okay";
};

&gpio_spi {
	eth0-phy-hog {
		gpio-hog;
		gpios = <1 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "eth0-phy";
	};

	eth1-phy-hog {
		gpio-hog;
		gpios = <2 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "eth1-phy";
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	magnetometer@e {
		compatible = "fsl,mag3110";
		reg = <0x0e>;
		vdd-supply = <&reg_peri_3v3>;
		vddio-supply = <&reg_peri_3v3>;
	};
};

&lcdif {
	assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat
		     &pinctrl_lcdif_ctrl>;
	status = "okay";

	port {
		display_out: endpoint {
			remote-endpoint = <&panel_in>;
		};
	};
};

&pwm1 {
	#pwm-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&qspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	status = "okay";

	flash0: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q256a", "jedec,spi-nor";
		spi-max-frequency = <29000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <1>;
		reg = <0>;
	};
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
			  <&clks IMX6UL_CLK_SAI2>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <0>, <12288000>;
	fsl,sai-mclk-direction-output;
	status = "okay";
};

&snvs_poweroff {
	status = "okay";
};

&snvs_pwrkey {
	status = "okay";
};

&tsc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_tsc>;
	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
	measure-delay-time = <0xffff>;
	pre-charge-time = <0xfff>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	uart-has-rtscts;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1>;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usbphy1 {
	fsl,tx-d-cal = <106>;
};

&usbphy2 {
	fsl,tx-d-cal = <106>;
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&reg_sd1_vmmc>;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	no-1-8-v;
	broken-cd;
	keep-power-in-suspend;
	wakeup-source;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
};

&iomuxc {
	pinctrl-names = "default";

	pinctrl_camera_clock: cameraclockgrp {
		fsl,pins = <
			MX6UL_PAD_CSI_MCLK__CSI_MCLK		0x1b088
		>;
	};

	pinctrl_csi1: csi1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK	0x1b088
			MX6UL_PAD_CSI_VSYNC__CSI_VSYNC		0x1b088
			MX6UL_PAD_CSI_HSYNC__CSI_HSYNC		0x1b088
			MX6UL_PAD_CSI_DATA00__CSI_DATA02	0x1b088
			MX6UL_PAD_CSI_DATA01__CSI_DATA03	0x1b088
			MX6UL_PAD_CSI_DATA02__CSI_DATA04	0x1b088
			MX6UL_PAD_CSI_DATA03__CSI_DATA05	0x1b088
			MX6UL_PAD_CSI_DATA04__CSI_DATA06	0x1b088
			MX6UL_PAD_CSI_DATA05__CSI_DATA07	0x1b088
			MX6UL_PAD_CSI_DATA06__CSI_DATA08	0x1b088
			MX6UL_PAD_CSI_DATA07__CSI_DATA09	0x1b088
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
		>;
	};

	pinctrl_flexcan1: flexcan1grp{
		fsl,pins = <
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
		>;
	};

	pinctrl_flexcan2: flexcan2grp{
		fsl,pins = <
			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
		>;
	};

	pinctrl_lcdif_dat: lcdifdatgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
		>;
	};

	pinctrl_lcdif_ctrl: lcdifctrlgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
			/* used for lcd reset */
			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
		>;
	};

	pinctrl_qspi: qspigrp {
		fsl,pins = <
			MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK	0x70a1
			MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00	0x70a1
			MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01	0x70a1
			MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02	0x70a1
			MX6UL_PAD_NAND_CLE__QSPI_A_DATA03	0x70a1
			MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B	0x70a1
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
			MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04	0x17059
		>;
	};

	pinctrl_peri_3v3: peri3v3grp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0
		>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
		>;
	};

	pinctrl_sim2: sim2grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD		0xb808
			MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK		0x31
			MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B		0xb808
			MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN		0xb808
			MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD		0xb809
			MX6UL_PAD_CSI_DATA02__GPIO4_IO23		0x3008
		>;
	};

	pinctrl_spi4: spi4grp {
		fsl,pins = <
			MX6UL_PAD_BOOT_MODE0__GPIO5_IO10	0x70a1
			MX6UL_PAD_BOOT_MODE1__GPIO5_IO11	0x70a1
			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x70a1
			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x80000000
		>;
	};

	pinctrl_tsc: tscgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01		0xb0
			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02		0xb0
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03		0xb0
			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04		0xb0
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
			MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x1b0b1
			MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x1b0b1
		>;
	};

	pinctrl_usb_otg1: usbotg1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x17059
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
			MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9

		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Digi International's ConnectCore6UL SBC Express board device tree source
 *
 * Copyright 2018 Digi International, Inc.
 *
 */

/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6ul.dtsi"
#include "imx6ul-ccimx6ulsom.dtsi"

/ {
	model = "Digi International ConnectCore 6UL SBC Express.";
	compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom",
		     "fsl,imx6ul";
};

&adc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc1>;
	status = "okay";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&ext_3v3>;
	status = "okay";
};

&ecspi3 {
	cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi3_master>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			smsc,disable-energy-detect;
			reg = <0>;
		};
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	broken-cd;      /* no carrier detect line (use polling) */
	no-1-8-v;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_adc1: adc1grp {
		fsl,pins = <
			/* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */
			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0xb0
		>;
	};

	pinctrl_ecspi3_master: ecspi3grp1 {
		fsl,pins = <
			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0
			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0
			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0
			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x10b0 /* Chip Select */
		>;
	};

	pinctrl_ecspi3_slave: ecspi3grp2 {
		fsl,pins = <
			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0
			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0
			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0
			MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0	0x10b0 /* Chip Select */
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x40017051
		>;
	};

	pinctrl_flexcan1: flexcan1grp{
		fsl,pins = <
			MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX	0x1b020
			MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX	0x1b020
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
			MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
		>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__PWM1_OUT		0x10b0
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__UART4_DCE_TX		0x1b0b1
			MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_uart5: uart5grp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0b1
			MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x10071
			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x17059
			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x17059
			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x17059
			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
		>;
	};

	/* General purpose pinctrl */
	pinctrl_hog: hoggrp {
		fsl,pins = <
			/* GPIOs BANK 3 */
			MX6UL_PAD_LCD_RESET__GPIO3_IO04		0xf030
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Digi International's ConnectCore6UL SBC Pro board device tree source
 *
 * Copyright 2018 Digi International, Inc.
 *
 */

/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6ul.dtsi"
#include "imx6ul-ccimx6ulsom.dtsi"

/ {
	model = "Digi International ConnectCore 6UL SBC Pro.";
	compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul";

	lcd_backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm5 0 50000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
		status = "okay";
	};

	panel {
		compatible = "auo,g101evn010";
		power-supply = <&ldo4_ext>;
		backlight = <&lcd_backlight>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&display_out>;
			};
		};
	};

	reg_usb_otg1_vbus: regulator-usb-otg1 {
		compatible = "regulator-fixed";
		regulator-name = "usb_otg1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&adc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc1>;
	status = "okay";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&ext_3v3>;
	status = "okay";
};

/* CAN2 is multiplexed with UART2 RTS/CTS */
&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&ext_3v3>;
	status = "disabled";
};

&ecspi1 {
	cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1_master>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	status = "okay";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <26>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			smsc,disable-energy-detect;
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			smsc,disable-energy-detect;
			reg = <1>;
		};
	};
};

&gpio5 {
	emmc-usd-mux-hog {
		gpio-hog;
		gpios = <1 GPIO_ACTIVE_LOW>;
		output-high;
	};
};

&i2c1 {
	touchscreen@14 {
		compatible = "goodix,gt911";
		reg = <0x14>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_goodix_touch>;
		interrupt-parent = <&gpio5>;
		interrupts = <2 IRQ_TYPE_EDGE_RISING>;
		irq-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat0_17
		     &pinctrl_lcdif_clken
		     &pinctrl_lcdif_hvsync>;
	lcd-supply = <&ldo4_ext>;       /* BU90T82 LVDS bridge power */
	status = "okay";

	port {
		display_out: endpoint {
			remote-endpoint = <&panel_in>;
		};
	};
};

&ldo4_ext {
	regulator-max-microvolt = <1800000>;
};

&pwm1 {
	status = "okay";
};

&pwm2 {
	status = "okay";
};

&pwm3 {
	status = "okay";
};

&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "okay";
};

&pwm5 {
	#pwm-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm5>;
	status = "okay";
};

&pwm6 {
	status = "okay";
};

&pwm7 {
	status = "okay";
};

&pwm8 {
	status = "okay";
};

&sai2 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_sai2>;
	pinctrl-1 = <&pinctrl_sai2_sleep>;
	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
			  <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>,
			  <&clks IMX6UL_CLK_SAI2>;
	assigned-clock-rates = <0>, <786432000>, <12288000>;
	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	status = "okay";
};

/* UART2 RTS/CTS muxed with CAN2 */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2_4wires>;
	uart-has-rtscts;
	status = "okay";
};

/* UART3 RTS/CTS muxed with CAN 1 */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3_2wires>;
	status = "okay";
};

&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-0 = <&pinctrl_usbotg1>;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

/* USDHC2 (microSD conflicts with eMMC) */
&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	no-1-8-v;
	broken-cd;	/* no carrier detect line (use polling) */
	status = "okay";
};

&iomuxc {
	pinctrl_adc1: adc1grp {
		fsl,pins = <
			/* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0xb0
		>;
	};

	pinctrl_ecspi1_master: ecspi1grp1 {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK	0x10b0
			MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	0x10b0
			MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	0x10b0
			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x10b0
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x40017051
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x40017051
		>;
	};

	pinctrl_enet2_mdio: mdioenet2grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
		>;
	};

	pinctrl_flexcan1: flexcan1grp{
		fsl,pins = <
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
		>;
	};
	pinctrl_flexcan2: flexcan2grp{
		fsl,pins = <
			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
		>;
	};

	pinctrl_goodix_touch: goodixgrp{
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1020
		>;
	};

	pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00	0x79
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01	0x79
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02	0x79
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03	0x79
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04	0x79
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05	0x79
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06	0x79
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07	0x79
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08	0x79
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09	0x79
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10	0x79
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11	0x79
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12	0x79
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13	0x79
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14	0x79
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15	0x79
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16	0x79
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17	0x79
		>;
	};

	pinctrl_lcdif_clken: lcdifctrlgrp1 {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK		0x17050
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE	0x79
		>;
	};

	pinctrl_lcdif_hvsync: lcdifctrlgrp2 {
		fsl,pins = <
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC	0x79
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC	0x79
		>;
	};

	pinctrl_pwm4: pwm4grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO05__PWM4_OUT          0x110b0
		>;
	};

	pinctrl_pwm5: pwm5grp {
		fsl,pins = <
			MX6UL_PAD_NAND_DQS__PWM5_OUT		0x110b0
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
			MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
			/* Interrupt */
			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x10b0
		>;
	};

	pinctrl_sai2_sleep: sai2grp-sleep {
		fsl,pins = <
			MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15	0x3000
			MX6UL_PAD_JTAG_TCK__GPIO1_IO14		0x3000
			MX6UL_PAD_JTAG_TMS__GPIO1_IO11		0x3000
			MX6UL_PAD_JTAG_TDO__GPIO1_IO12		0x3000
			/* Interrupt */
			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x3000
		>;
	};

	pinctrl_uart2_4wires: uart2grp-4wires {
		fsl,pins = <
			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
			MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS	0x1b0b1
			MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS	0x1b0b1
		>;
	};

	pinctrl_uart3_2wires: uart3grp-2wires {
		fsl,pins = <
			MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX	0x1b0b1
			MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_uart5: uart5grp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0b1
			MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x10039
			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x17059
			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x17059
			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x17059
			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
			/* Mux selector between eMMC/SD# */
			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	0x79
		>;
	};

	pinctrl_usbotg1: usbotg1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0x17059
			MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC	0x17059
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Digi International's ConnectCore 6UL System-On-Module device tree source
 *
 * Copyright 2018 Digi International, Inc.
 *
 */

/ {
	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0>; /* will be filled by U-Boot */
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x4000000>;
			linux,cma-default;
		};
	};
};

&adc1 {
	vref-supply = <&vdda_adc_3v3>;
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pfuze3000: pmic@8 {
		compatible = "fsl,pfuze3000";
		reg = <0x08>;

		regulators {
			int_3v3: sw1a {
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <3300000>;
				regulator-ramp-delay = <6250>;
				regulator-boot-on;
				regulator-always-on;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdd_arm_soc_in: sw1b {
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1475000>;
				regulator-ramp-delay = <6250>;
				regulator-boot-on;
				regulator-always-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <925000>;
				};
			};

			ext_3v3: sw2 {
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <3300000>;
				regulator-ramp-delay = <6250>;
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vcc_ddr3: sw3 {
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1650000>;
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-on-in-suspend;
					regulator-suspend-microvolt = <1300000>;
				};
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			vdd_snvs_3v3: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vrefddr: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vdda_adc_3v3: vldo1 {
				compatible = "regulator-fixed";
				regulator-name = "vref-adc-3v3";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			ldo2_ext: vldo2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vdda_wlan: vccsd {
				regulator-min-microvolt = <2850000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
				regulator-boot-on;

				regulator-state-mem {
					regulator-off-in-suspend;
				};
			};

			vdd_high_in: v33 {
				regulator-min-microvolt = <2850000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_int: vldo3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};

			ldo4_ext: vldo4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};

			vcoin_chg: vcoin {
				regulator-min-microvolt = <2500000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};
};

/* UART1 (Bluetooth) */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	uart-has-rtscts;
	status = "okay";
};

/* USDHC1 (Wireless) */
&usdhc1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_wifibt_ctrl>;
	pinctrl-1 = <&pinctrl_usdhc1_sleep &pinctrl_wifibt_ctrl_sleep>;
	non-removable;
	no-1-8-v;
	bus-width = <4>;
	status = "okay";
};

&iomuxc {
	pinctrl_gpmi_nand: gpmigrp {
		fsl,pins = <
			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B	0xb0b1
			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B	0xb0b1
			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B	0xb0b1
			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B	0xb0b1
			MX6UL_PAD_NAND_ALE__RAWNAND_ALE		0xb0b1
			MX6UL_PAD_NAND_CLE__RAWNAND_CLE		0xb0b1
			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00	0xb0b1
			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01	0xb0b1
			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02	0xb0b1
			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03	0xb0b1
			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04	0xb0b1
			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05	0xb0b1
			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06	0xb0b1
			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07	0xb0b1
			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B	0xb0b1
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
			MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS    0x1b0b1
			MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS    0x1b0b1
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x17051
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
		>;
	};

	pinctrl_usdhc1_sleep: usdhc1grp-sleep {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__GPIO2_IO16           0x3000
			MX6UL_PAD_SD1_CLK__GPIO2_IO17           0x3000
			MX6UL_PAD_SD1_DATA0__GPIO2_IO18         0x3000
			MX6UL_PAD_SD1_DATA1__GPIO2_IO19         0x3000
			MX6UL_PAD_SD1_DATA2__GPIO2_IO20         0x3000
			MX6UL_PAD_SD1_DATA3__GPIO2_IO21         0x3000
		>;
	};

	pinctrl_wifibt_ctrl: wifibt-ctrl-grp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x08a0
			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x08a0
		>;
	};

	pinctrl_wifibt_ctrl_sleep: wifibt-ctrl-grp-sleep {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x3000
			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x3000
		>;
	};
};

&reg_arm {
	vin-supply = <&vdd_arm_soc_in>;
	regulator-allow-bypass;
};

&reg_soc {
	vin-supply = <&vdd_arm_soc_in>;
	regulator-allow-bypass;
};


code:
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
 * Copyright (C) 2016 Amarula Solutions B.V.
 * Copyright (C) 2016 Engicam S.r.l.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6ul.dtsi"

/ {
	model = "Engicam GEAM6UL Starter Kit";
	compatible = "engicam,imx6ul-geam", "fsl,imx6ul";

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x08000000>;
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm8 0 100000>;
		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <100>;
	};

	chosen {
		stdout-path = &uart1;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "1P8V";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		regulator-boot-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "imx6ul-geam-sgtl5000";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,widgets =
			"Microphone", "Mic Jack",
			"Line", "Line In",
			"Line", "Line Out",
			"Headphone", "Headphone Jack";
		simple-audio-card,routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};

		dailink_master: simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
			clocks = <&clks IMX6UL_CLK_SAI2>;
		};
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_3p3v>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_3p3v>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	status = "okay";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};

&gpmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpmi_nand>;
	nand-on-flash-bbt;
	status = "okay";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	sgtl5000: codec@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		#sound-dai-cells = <0>;
		clocks = <&clks IMX6UL_CLK_OSC>;
		clock-names = "mclk";
		VDDA-supply = <&reg_3p3v>;
		VDDIO-supply = <&reg_3p3v>;
		VDDD-supply = <&reg_1p8v>;
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif_dat
		     &pinctrl_lcdif_ctrl>;
	display = <&display0>;
	status = "okay";

	display0: display0 {
		bits-per-pixel = <16>;
		bus-width = <18>;

		display-timings {
			native-mode = <&timing0>;
			timing0: timing0 {
				clock-frequency = <28000000>;
				hactive = <800>;
				vactive = <480>;
				hfront-porch = <30>;
				hback-porch = <30>;
				hsync-len = <64>;
				vback-porch = <5>;
				vfront-porch = <5>;
				vsync-len = <20>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};
	};
};

&pwm8 {
	#pwm-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm8>;
	status = "okay";
};

&tsc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_tsc>;
	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	status = "okay";
};

&tsc {
	measure-delay-time = <0x1ffff>;
	pre-charge-time = <0x1fff>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "peripheral";
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <4>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	no-1-8-v;
	status = "okay";
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15	0x1b0b0		/* ENET_nRST */
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
			MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2	0x4001b031
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
		>;
	};

	pinctrl_gpmi_nand: gpminandgrp {
		fsl,pins = <
			MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
			MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
		>;
	};

	pinctrl_i2c2: i2c2grp {
			fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
		>;
	};

	pinctrl_lcdif_ctrl: lcdifctrlgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
		>;
	};

	pinctrl_lcdif_dat: lcdifdatgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
		>;
	};

	pinctrl_pwm8: pwm8grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_ER__PWM8_OUT   0x110b0
		>;
	};

	pinctrl_tsc: tscgrp {
		fsl,pin = <
			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x130b0
			MX6UL_PAD_JTAG_TMS__CCM_CLKO1		0x4001b031
			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x120b0
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
			MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x1b0b1
			MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x1b0b1
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK     0x17070
			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD     0x10070
			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0  0x17070
			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1  0x17070
			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2  0x17070
			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3  0x17070
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2019 Armadeus Systems <support@armadeus.com>

/ {
	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0>; /* will be filled by U-Boot */
	};

	reg_3v3: regulator-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	usdhc3_pwrseq: usdhc3-pwrseq {
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-reset-duration = <1>;
	phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_3v3>;
	status = "okay";

	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			interrupt-parent = <&gpio4>;
			interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
			status = "okay";
		};
	};
};

/* Bluetooth */
&uart8 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart8>;
	uart-has-rtscts;
	status = "okay";
};

/* eMMC */
&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <8>;
	no-1-8-v;
	non-removable;
	status = "okay";
};

/* WiFi */
&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	no-1-8-v;
	non-removable;
	mmc-pwrseq = <&usdhc3_pwrseq>;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;

	brcmf: wifi@1 {
		compatible = "brcm,bcm4329-fmac";
		reg = <1>;
		interrupt-parent = <&gpio2>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "host-wake";
	};
};

&iomuxc {
	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x130b0
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x130b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x130b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x130b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			/* INT# */
			MX6UL_PAD_NAND_DQS__GPIO4_IO16		0x1b0b0
			/* RST# */
			MX6UL_PAD_NAND_DATA00__GPIO4_IO02	0x130b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
		>;
	};

	pinctrl_uart8: uart8grp {
		fsl,pins = <
			MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS	0x1b0b0
			/* BT_REG_ON */
			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x130b0
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
			MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
			MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
			MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
			MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA18__USDHC2_CMD	0x1b0b0
			MX6UL_PAD_LCD_DATA19__USDHC2_CLK	0x100b0
			MX6UL_PAD_LCD_DATA20__USDHC2_DATA0	0x1b0b0
			MX6UL_PAD_LCD_DATA21__USDHC2_DATA1	0x1b0b0
			MX6UL_PAD_LCD_DATA22__USDHC2_DATA2	0x1b0b0
			MX6UL_PAD_LCD_DATA23__USDHC2_DATA3	0x1b0b0
			/* WL_REG_ON */
			MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09	0x130b0
			/* WL_IRQ */
			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x1b0b0
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2019 Armadeus Systems <support@armadeus.com>

/ {
	chosen {
		stdout-path = &uart1;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm3 0 191000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <7>;
		power-supply = <&reg_5v>;
		status = "okay";
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;

		user-button {
			label = "User button";
			gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_MISC>;
			wakeup-source;
		};
	};

	leds {
		compatible = "gpio-leds";

		user-led {
			label = "User";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_led>;
			gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	onewire {
		compatible = "w1-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_w1>;
		gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
	};

	panel: panel {
		compatible = "armadeus,st0700-adapt";
		power-supply = <&reg_3v3>;
		backlight = <&backlight>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&lcdif_out>;
			};
		};
	};

	reg_5v: regulator-5v {
		compatible = "regulator-fixed";
		regulator-name = "5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_usbotg1_vbus: regulator-usbotg1vbus {
		compatible = "regulator-fixed";
		regulator-name = "usbotg1vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbotg1_vbus>;
		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usbotg2_vbus: regulator-usbotg2vbus {
		compatible = "regulator-fixed";
		regulator-name = "usbotg2vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbotg2_vbus>;
		gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&adc1 {
	vref-supply = <&reg_3v3>;
	status = "okay";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_5v>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_5v>;
	status = "okay";
};

&ecspi4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi4>;
	cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	clock-frequency = <400000>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clock-frequency = <400000>;
	status = "okay";
};

&lcdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcdif>;
	status = "okay";

	port {
		lcdif_out: endpoint {
			remote-endpoint = <&panel_in>;
		};
	};
};

&pwm3 {
	#pwm-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
};

&snvs_pwrkey {
	status = "disabled";
};

&tsc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_tsc>;
	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
	measure-delay-time = <0xffff>;
	pre-charge-time = <0xffff>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1_id>;
	vbus-supply = <&reg_usbotg1_vbus>;
	dr_mode = "otg";
	disable-over-current;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usbotg2_vbus>;
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpios>;

	pinctrl_ecspi4: ecspi4grp {
		fsl,pins = <
			MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK	0x1b0b0
			MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI	0x1b0b0
			MX6UL_PAD_NAND_DATA06__ECSPI4_MISO	0x1b0b0
			MX6UL_PAD_NAND_DATA01__GPIO4_IO03	0x1b0b0
			MX6UL_PAD_NAND_DATA07__GPIO4_IO09	0x1b0b0
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x0b0b0
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x0b0b0
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x0b0b0
			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x0b0b0
		>;
	};

	pinctrl_gpios: gpiosgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09	0x0b0b0
			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x0b0b0
			MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24	0x0b0b0
			MX6UL_PAD_NAND_RE_B__GPIO4_IO00		0x0b0b0
			MX6UL_PAD_GPIO1_IO08__GPIO1_IO08	0x0b0b0
			MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x0b0b0
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x0b0b0
			MX6UL_PAD_NAND_WE_B__GPIO4_IO01		0x0b0b0
		>;
	};

	pinctrl_gpio_keys: gpiokeysgrp {
		fsl,pins = <
			MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11	0x0b0b0
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA	0x4001b8b0
			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL	0x4001b8b0
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA	0x4001b8b0
			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL	0x4001b8b0
		>;
	};

	pinctrl_lcdif: lcdifgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x100b1
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x100b1
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x100b1
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x100b1
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x100b1
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x100b1
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x100b1
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x100b1
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x100b1
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x100b1
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x100b1
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x100b1
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x100b1
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x100b1
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x100b1
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x100b1
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x100b1
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x100b1
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x100b1
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x100b1
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x100b1
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x100b1
		>;
	};

	pinctrl_led: ledgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_RESET__GPIO3_IO04		0x0b0b0
		>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <
			MX6UL_PAD_NAND_ALE__PWM3_OUT		0x1b0b0
		>;
	};

	pinctrl_tsc: tscgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01       0xb0
			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02       0xb0
			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03       0xb0
			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04       0xb0
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
		>;
	};

	pinctrl_usbotg1_id: usbotg1idgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x1b0b0
		>;
	};

	pinctrl_usbotg1_vbus: usbotg1vbusgrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO05__GPIO1_IO05	0x1b0b0
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
 * Copyright (C) 2016 Amarula Solutions B.V.
 * Copyright (C) 2016 Engicam S.r.l.
 */

/dts-v1/;

#include "imx6ul-isiot.dtsi"

/ {
	model = "Engicam Is.IoT MX6UL eMMC Starter kit";
	compatible = "engicam,imx6ul-isiot", "fsl,imx6ul";
};

&usdhc2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
 * Copyright (C) 2016 Amarula Solutions B.V.
 * Copyright (C) 2016 Engicam S.r.l.
 */

/dts-v1/;

#include "imx6ul-isiot.dtsi"

/ {
	model = "Engicam Is.IoT MX6UL NAND Starter kit";
	compatible = "engicam,imx6ul-isiot", "fsl,imx6ul";
};

&gpmi {
	status = "okay";
};