code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board
 *
 *  Copyright (C) 2012 Atmel,
 *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
 */
/dts-v1/;
#include "at91sam9x35.dtsi"
#include "at91sam9x5dm.dtsi"
#include "at91sam9x5ek.dtsi"

/ {
	model = "Atmel AT91SAM9X35-EK";
	compatible = "atmel,at91sam9x35ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
};

&backlight {
	status = "okay";
};

&bl_reg {
	status = "okay";
};

&hlcdc {
	status = "okay";
};

&macb0 {
	phy-mode = "rmii";
	status = "okay";
};

&panel {
	status = "okay";
};

&panel_reg {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
 *                   applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
 *                   AT91SAM9X25, AT91SAM9X35 SoC
 *
 *  Copyright (C) 2012 Atmel,
 *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
 */

#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/mfd/at91-usart.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Atmel AT91SAM9x5 family SoC";
	compatible = "atmel,at91sam9x5";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &dbgu;
		serial1 = &usart0;
		serial2 = &usart1;
		serial3 = &usart2;
		gpio0 = &pioA;
		gpio1 = &pioB;
		gpio2 = &pioC;
		gpio3 = &pioD;
		tcb0 = &tcb0;
		tcb1 = &tcb1;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		ssc0 = &ssc0;
		pwm0 = &pwm0;
	};
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,arm926ej-s";
			device_type = "cpu";
			reg = <0>;
		};
	};

	memory@20000000 {
		device_type = "memory";
		reg = <0x20000000 0x10000000>;
	};

	clocks {
		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		adc_op_clk: adc_op_clk{
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000>;
		};
	};

	sram: sram@300000 {
		compatible = "mmio-sram";
		reg = <0x00300000 0x8000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x00300000 0x8000>;
	};

	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			aic: interrupt-controller@fffff000 {
				#interrupt-cells = <3>;
				compatible = "atmel,at91rm9200-aic";
				interrupt-controller;
				reg = <0xfffff000 0x200>;
				atmel,external-irqs = <31>;
			};

			matrix: matrix@ffffde00 {
				compatible = "atmel,at91sam9x5-matrix", "syscon";
				reg = <0xffffde00 0x100>;
			};

			pmecc: ecc-engine@ffffe000 {
				compatible = "atmel,at91sam9g45-pmecc";
				reg = <0xffffe000 0x600>,
				      <0xffffe600 0x200>;
			};

			ramc0: ramc@ffffe800 {
				compatible = "atmel,at91sam9g45-ddramc";
				reg = <0xffffe800 0x200>;
				clocks = <&pmc PMC_TYPE_SYSTEM 2>;
				clock-names = "ddrck";
			};

			smc: smc@ffffea00 {
				compatible = "atmel,at91sam9260-smc", "syscon";
				reg = <0xffffea00 0x200>;
			};

			pmc: pmc@fffffc00 {
				compatible = "atmel,at91sam9x5-pmc", "syscon";
				reg = <0xfffffc00 0x200>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				#clock-cells = <2>;
				clocks = <&clk32k>, <&main_xtal>;
				clock-names = "slow_clk", "main_xtal";
			};

			reset_controller: reset-controller@fffffe00 {
				compatible = "atmel,at91sam9g45-rstc";
				reg = <0xfffffe00 0x10>;
				clocks = <&clk32k>;
			};

			shutdown_controller: shdwc@fffffe10 {
				compatible = "atmel,at91sam9x5-shdwc";
				reg = <0xfffffe10 0x10>;
				clocks = <&clk32k>;
			};

			pit: timer@fffffe30 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xfffffe30 0xf>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
			};

			clk32k: sckc@fffffe50 {
				compatible = "atmel,at91sam9x5-sckc";
				reg = <0xfffffe50 0x4>;
				clocks = <&slow_xtal>;
				#clock-cells = <0>;
			};

			tcb0: timer@f8008000 {
				compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0xf8008000 0x100>;
				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
				clock-names = "t0_clk", "slow_clk";
			};

			tcb1: timer@f800c000 {
				compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0xf800c000 0x100>;
				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>;
				clock-names = "t0_clk", "slow_clk";
			};

			dma0: dma-controller@ffffec00 {
				compatible = "atmel,at91sam9g45-dma";
				reg = <0xffffec00 0x200>;
				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
				#dma-cells = <2>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
				clock-names = "dma_clk";
			};

			dma1: dma-controller@ffffee00 {
				compatible = "atmel,at91sam9g45-dma";
				reg = <0xffffee00 0x200>;
				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
				#dma-cells = <2>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
				clock-names = "dma_clk";
			};

			pinctrl: pinctrl@fffff400 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
				ranges = <0xfffff400 0xfffff400 0x800>;

				/* shared pinctrl settings */
				dbgu {
					pinctrl_dbgu: dbgu-0 {
						atmel,pins =
							<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
							 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				ebi {
					pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
						atmel,pins =
							<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_data_8_15: ebi-data-msb-0 {
						atmel,pins =
							<AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_ebi_addr_nand: ebi-addr-0 {
						atmel,pins =
							<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				usart0 {
					pinctrl_usart0: usart0-0 {
						atmel,pins =
							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
					};

					pinctrl_usart0_rts: usart0_rts-0 {
						atmel,pins =
							<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA2 periph A */
					};

					pinctrl_usart0_cts: usart0_cts-0 {
						atmel,pins =
							<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA3 periph A */
					};

					pinctrl_usart0_sck: usart0_sck-0 {
						atmel,pins =
							<AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA4 periph A */
					};
				};

				usart1 {
					pinctrl_usart1: usart1-0 {
						atmel,pins =
							<AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
					};

					pinctrl_usart1_rts: usart1_rts-0 {
						atmel,pins =
							<AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC27 periph C */
					};

					pinctrl_usart1_cts: usart1_cts-0 {
						atmel,pins =
							<AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC28 periph C */
					};

					pinctrl_usart1_sck: usart1_sck-0 {
						atmel,pins =
							<AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC29 periph C */
					};
				};

				usart2 {
					pinctrl_usart2: usart2-0 {
						atmel,pins =
							<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
					};

					pinctrl_usart2_rts: usart2_rts-0 {
						atmel,pins =
							<AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB0 periph B */
					};

					pinctrl_usart2_cts: usart2_cts-0 {
						atmel,pins =
							<AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB1 periph B */
					};

					pinctrl_usart2_sck: usart2_sck-0 {
						atmel,pins =
							<AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB2 periph B */
					};
				};

				uart0 {
					pinctrl_uart0: uart0-0 {
						atmel,pins =
							<AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PC8 periph C */
							 AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;	/* PC9 periph C with pullup */
					};
				};

				uart1 {
					pinctrl_uart1: uart1-0 {
						atmel,pins =
							<AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PC16 periph C */
							 AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;	/* PC17 periph C with pullup */
					};
				};

				nand {
					pinctrl_nand_oe_we: nand-oe-we-0 {
						atmel,pins =
							<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE
							 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_nand_rb: nand-rb-0 {
						atmel,pins =
							<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
					};

					pinctrl_nand_cs: nand-cs-0 {
						atmel,pins =
							<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
					};
				};

				mmc0 {
					pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
						atmel,pins =
							<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA17 periph A */
							 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA16 periph A with pullup */
							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA15 periph A with pullup */
					};

					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
						atmel,pins =
							<AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA18 periph A with pullup */
							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA19 periph A with pullup */
							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA20 periph A with pullup */
					};
				};

				mmc1 {
					pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
						atmel,pins =
							<AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA13 periph B */
							 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA12 periph B with pullup */
							 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA11 periph B with pullup */
					};

					pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
						atmel,pins =
							<AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA2 periph B with pullup */
							 AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP	/* PA3 periph B with pullup */
							 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;	/* PA4 periph B with pullup */
					};
				};

				ssc0 {
					pinctrl_ssc0_tx: ssc0_tx-0 {
						atmel,pins =
							<AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA24 periph B */
							 AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA25 periph B */
							 AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA26 periph B */
					};

					pinctrl_ssc0_rx: ssc0_rx-0 {
						atmel,pins =
							<AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA27 periph B */
							 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA28 periph B */
							 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA29 periph B */
					};
				};

				spi0 {
					pinctrl_spi0: spi0-0 {
						atmel,pins =
							<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA11 periph A SPI0_MISO pin */
							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA12 periph A SPI0_MOSI pin */
							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA13 periph A SPI0_SPCK pin */
					};
				};

				spi1 {
					pinctrl_spi1: spi1-0 {
						atmel,pins =
							<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA21 periph B SPI1_MISO pin */
							 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA22 periph B SPI1_MOSI pin */
							 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA23 periph B SPI1_SPCK pin */
					};
				};

				i2c0 {
					pinctrl_i2c0: i2c0-0 {
						atmel,pins =
							<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA30 periph A I2C0 data */
							 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA31 periph A I2C0 clock */
					};
				};

				i2c1 {
					pinctrl_i2c1: i2c1-0 {
						atmel,pins =
							<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PC0 periph C I2C1 data */
							 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PC1 periph C I2C1 clock */
					};
				};

				i2c2 {
					pinctrl_i2c2: i2c2-0 {
						atmel,pins =
							<AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB4 periph B I2C2 data */
							 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB5 periph B I2C2 clock */
					};
				};

				i2c_gpio0 {
					pinctrl_i2c_gpio0: i2c_gpio0-0 {
						atmel,pins =
							<AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE	/* PA30 gpio multidrive I2C0 data */
							 AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;	/* PA31 gpio multidrive I2C0 clock */
					};
				};

				i2c_gpio1 {
					pinctrl_i2c_gpio1: i2c_gpio1-0 {
						atmel,pins =
							<AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE	/* PC0 gpio multidrive I2C1 data */
							 AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;	/* PC1 gpio multidrive I2C1 clock */
					};
				};

				i2c_gpio2 {
					pinctrl_i2c_gpio2: i2c_gpio2-0 {
						atmel,pins =
							<AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE	/* PB4 gpio multidrive I2C2 data */
							 AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;	/* PB5 gpio multidrive I2C2 clock */
					};
				};

				pwm0 {
					pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
						atmel,pins =
							<AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};
					pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
						atmel,pins =
							<AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};
					pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
						atmel,pins =
							<AT91_PIOC 18 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
						atmel,pins =
							<AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};
					pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
						atmel,pins =
							<AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};
					pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
						atmel,pins =
							<AT91_PIOC 19 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
						atmel,pins =
							<AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};
					pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
						atmel,pins =
							<AT91_PIOC 20 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
						atmel,pins =
							<AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};
					pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
						atmel,pins =
							<AT91_PIOC 21 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};
				};

				tcb0 {
					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
						atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
						atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
						atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
						atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
						atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
						atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
						atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
						atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
						atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
				};

				tcb1 {
					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
						atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
						atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
						atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
						atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
						atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
						atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
						atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
						atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
						atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
					};
				};

				pioA: gpio@fffff400 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff400 0x200>;
					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
				};

				pioB: gpio@fffff600 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff600 0x200>;
					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					#gpio-lines = <19>;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
				};

				pioC: gpio@fffff800 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffff800 0x200>;
					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
				};

				pioD: gpio@fffffa00 {
					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
					reg = <0xfffffa00 0x200>;
					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
					#gpio-cells = <2>;
					gpio-controller;
					#gpio-lines = <22>;
					interrupt-controller;
					#interrupt-cells = <2>;
					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
				};
			};

			ssc0: ssc@f0010000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xf0010000 0x4000>;
				interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>,
				       <&dma0 1 AT91_DMA_CFG_PER_ID(14)>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
				clock-names = "pclk";
				status = "disabled";
			};

			mmc0: mmc@f0008000 {
				compatible = "atmel,hsmci";
				reg = <0xf0008000 0x600>;
				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
				dma-names = "rxtx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
				clock-names = "mci_clk";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			mmc1: mmc@f000c000 {
				compatible = "atmel,hsmci";
				reg = <0xf000c000 0x600>;
				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
				dma-names = "rxtx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
				clock-names = "mci_clk";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			dbgu: serial@fffff200 {
				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
				reg = <0xfffff200 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_dbgu>;
				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
				       <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
				clock-names = "usart";
				status = "disabled";
			};

			usart0: serial@f801c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf801c000 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart0>;
				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
				       <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
				clock-names = "usart";
				status = "disabled";
			};

			usart1: serial@f8020000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8020000 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart1>;
				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
				       <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
				clock-names = "usart";
				status = "disabled";
			};

			usart2: serial@f8024000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8024000 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart2>;
				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
				       <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
				clock-names = "usart";
				status = "disabled";
			};

			i2c0: i2c@f8010000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8010000 0x100>;
				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
				       <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_i2c0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
				status = "disabled";
			};

			i2c1: i2c@f8014000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8014000 0x100>;
				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
				       <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_i2c1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
				status = "disabled";
			};

			i2c2: i2c@f8018000 {
				compatible = "atmel,at91sam9x5-i2c";
				reg = <0xf8018000 0x100>;
				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
				       <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_i2c2>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
				status = "disabled";
			};

			uart0: serial@f8040000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8040000 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_uart0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
				clock-names = "usart";
				status = "disabled";
			};

			uart1: serial@f8044000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8044000 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_uart1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
				clock-names = "usart";
				status = "disabled";
			};

			adc0: adc@f804c000 {
				compatible = "atmel,at91sam9x5-adc";
				reg = <0xf804c000 0x100>;
				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 19>,
					 <&adc_op_clk>;
				clock-names = "adc_clk", "adc_op_clk";
				atmel,adc-use-external-triggers;
				atmel,adc-channels-used = <0xffff>;
				atmel,adc-vref = <3300>;
				atmel,adc-startup-time = <40>;
				atmel,adc-sample-hold-time = <11>;
			};

			spi0: spi@f0000000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xf0000000 0x100>;
				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
				dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
				       <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
				clock-names = "spi_clk";
				status = "disabled";
			};

			spi1: spi@f0004000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xf0004000 0x100>;
				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
				       <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
				dma-names = "tx", "rx";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi1>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
				clock-names = "spi_clk";
				status = "disabled";
			};

			usb2: gadget@f803c000 {
				compatible = "atmel,at91sam9g45-udc";
				reg = <0x00500000 0x80000
				       0xf803c000 0x400>;
				interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};

			watchdog: watchdog@fffffe40 {
				compatible = "atmel,at91sam9260-wdt";
				reg = <0xfffffe40 0x10>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k>;
				atmel,watchdog-type = "hardware";
				atmel,reset-type = "all";
				atmel,dbg-halt;
				status = "disabled";
			};

			rtc: rtc@fffffeb0 {
				compatible = "atmel,at91sam9x5-rtc";
				reg = <0xfffffeb0 0x40>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k>;
				status = "disabled";
			};

			pwm0: pwm@f8034000 {
				compatible = "atmel,at91sam9rl-pwm";
				reg = <0xf8034000 0x300>;
				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
				#pwm-cells = <3>;
				status = "disabled";
			};
		};

		usb0: ohci@600000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00600000 0x100000>;
			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
			clock-names = "ohci_clk", "hclk", "uhpck";
			status = "disabled";
		};

		usb1: ehci@700000 {
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00700000 0x100000>;
			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
			clock-names = "usb_clk", "ehci_clk";
			status = "disabled";
		};

		ebi: ebi@10000000 {
			compatible = "atmel,at91sam9x5-ebi";
			#address-cells = <2>;
			#size-cells = <1>;
			atmel,smc = <&smc>;
			atmel,matrix = <&matrix>;
			reg = <0x10000000 0x60000000>;
			ranges = <0x0 0x0 0x10000000 0x10000000
				  0x1 0x0 0x20000000 0x10000000
				  0x2 0x0 0x30000000 0x10000000
				  0x3 0x0 0x40000000 0x10000000
				  0x4 0x0 0x50000000 0x10000000
				  0x5 0x0 0x60000000 0x10000000>;
			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
			status = "disabled";

			nand_controller: nand-controller {
				compatible = "atmel,at91sam9g45-nand-controller";
				ecc-engine = <&pmecc>;
				#address-cells = <2>;
				#size-cells = <1>;
				ranges;
				status = "disabled";
			};
		};
	};

	i2c-gpio-0 {
		compatible = "i2c-gpio";
		gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
			 &pioA 31 GPIO_ACTIVE_HIGH /* scl */
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c_gpio0>;
		status = "disabled";
	};

	i2c-gpio-1 {
		compatible = "i2c-gpio";
		gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
			 &pioC 1 GPIO_ACTIVE_HIGH /* scl */
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c_gpio1>;
		status = "disabled";
	};

	i2c-gpio-2 {
		compatible = "i2c-gpio";
		gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
			 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c_gpio2>;
		status = "disabled";
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
 * Ethernet interface.
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 */

#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	ahb {
		apb {
			can0: can@f8000000 {
				compatible = "atmel,at91sam9x5-can";
				reg = <0xf8000000 0x300>;
				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_can0_rx_tx>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
				clock-names = "can_clk";
				status = "disabled";
			};

			can1: can@f8004000 {
				compatible = "atmel,at91sam9x5-can";
				reg = <0xf8004000 0x300>;
				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_can1_rx_tx>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
				clock-names = "can_clk";
				status = "disabled";
			};

			pinctrl@fffff400 {
				can0 {
					pinctrl_can0_rx_tx: can0_rx_tx {
						atmel,pins =
							<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX0, conflicts with DRXD */
							AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* CANTX0, conflicts with DTXD */
					};
				};

				can1 {
					pinctrl_can1_rx_tx: can1_rx_tx {
						atmel,pins =
							<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX1, conflicts with RXD1 */
							AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* CANTX1, conflicts with TXD1 */
					};
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
 * Image Sensor Interface.
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 */

#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	ahb {
		apb {
			pinctrl@fffff400 {
				isi {
					pinctrl_isi_data_0_7: isi-0-data-0-7 {
						atmel,pins =
							<AT91_PIOC 0 AT91_PERIPH_B AT91_PINCTRL_NONE	/* ISI_D0, conflicts with LCDDAT0 */
							AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE	/* ISI_D1, conflicts with LCDDAT1 */
							AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE	/* ISI_D2, conflicts with LCDDAT2 */
							AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE	/* ISI_D3, conflicts with LCDDAT3 */
							AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE	/* ISI_D4, conflicts with LCDDAT4 */
							AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE	/* ISI_D5, conflicts with LCDDAT5 */
							AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_NONE	/* ISI_D6, conflicts with LCDDAT6 */
							AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_NONE	/* ISI_D7, conflicts with LCDDAT7 */
							AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE	/* ISI_PCK, conflicts with LCDDAT12 */
							AT91_PIOC 14 AT91_PERIPH_B AT91_PINCTRL_NONE	/* ISI_HSYNC, conflicts with LCDDAT14 */
							AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* ISI_VSYNC, conflicts with LCDDAT13 */
					};

					pinctrl_isi_data_8_9: isi-0-data-8-9 {
						atmel,pins =
							<AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE	/* ISI_D8, conflicts with LCDDAT8 */
							AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* ISI_D9, conflicts with LCDDAT9 */
					};

					pinctrl_isi_data_10_11: isi-0-data-10-11 {
						atmel,pins =
							<AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE	/* ISI_D10, conflicts with LCDDAT10 */
							AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* ISI_D11, conflicts with LCDDAT11 */
					};
				};
			};

			isi: isi@f8048000 {
				compatible = "atmel,at91sam9g45-isi";
				reg = <0xf8048000 0x4000>;
				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_isi_data_0_7>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
				clock-names = "isi_clk";
				status = "disabled";
				port {
					#address-cells = <1>;
					#size-cells = <0>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
 * LCD controller.
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 */

#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	ahb {
		apb {
			hlcdc: hlcdc@f8038000 {
				compatible = "atmel,at91sam9x5-hlcdc";
				reg = <0xf8038000 0x4000>;
				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
				clock-names = "periph_clk","sys_clk", "slow_clk";
				status = "disabled";

				hlcdc-display-controller {
					compatible = "atmel,hlcdc-display-controller";
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						#address-cells = <1>;
						#size-cells = <0>;
						reg = <0>;
					};
				};

				hlcdc_pwm: hlcdc-pwm {
					compatible = "atmel,hlcdc-pwm";
					pinctrl-names = "default";
					pinctrl-0 = <&pinctrl_lcd_pwm>;
					#pwm-cells = <3>;
				};
			};
		};
	};
};

&pinctrl {
	lcd {
		pinctrl_lcd_base: lcd-base-0 {
			atmel,pins =
				<AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDVSYNC */
				 AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDHSYNC */
				 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDDISP */
				 AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDDEN */
				 AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDPCK */
		};

		pinctrl_lcd_pwm: lcd-pwm-0 {
			atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDPWM */
		};

		pinctrl_lcd_rgb444: lcd-rgb-0 {
			atmel,pins =
				<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
				 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
				 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
				 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
				 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
				 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
				 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
				 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
				 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
				 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
				 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
				 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD11 pin */
		};

		pinctrl_lcd_rgb565: lcd-rgb-1 {
			atmel,pins =
				<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
				 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
				 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
				 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
				 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
				 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
				 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
				 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
				 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
				 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
				 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
				 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
				 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
				 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
				 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
				 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD15 pin */
		};

		pinctrl_lcd_rgb666: lcd-rgb-2 {
			atmel,pins =
				<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
				 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
				 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
				 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
				 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
				 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
				 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
				 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
				 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
				 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
				 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
				 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
				 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
				 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
				 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
				 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD15 pin */
				 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD16 pin */
				 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD17 pin */
		};

		pinctrl_lcd_rgb888: lcd-rgb-3 {
			atmel,pins =
				<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD0 pin */
				 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD1 pin */
				 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD2 pin */
				 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD3 pin */
				 AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD4 pin */
				 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD5 pin */
				 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD6 pin */
				 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD7 pin */
				 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD8 pin */
				 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD9 pin */
				 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD10 pin */
				 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD11 pin */
				 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD12 pin */
				 AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD13 pin */
				 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD14 pin */
				 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD15 pin */
				 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD16 pin */
				 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD17 pin */
				 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD18 pin */
				 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD19 pin */
				 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD20 pin */
				 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD21 pin */
				 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* LCDD22 pin */
				 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* LCDD23 pin */
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
 * Ethernet interface.
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 */

#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	ahb {
		apb {
			pinctrl@fffff400 {
				macb0 {
					pinctrl_macb0_rmii: macb0_rmii-0 {
						atmel,pins =
							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A */
							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A */
							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB2 periph A */
							 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB3 periph A */
							 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB4 periph A */
							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB5 periph A */
							 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB6 periph A */
							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB7 periph A */
							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB9 periph A */
							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A */
					};

					pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
						atmel,pins =
							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB8 periph A */
							 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB11 periph A */
							 AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB12 periph A */
							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB13 periph A */
							 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB14 periph A */
							 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB15 periph A */
							 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB16 periph A */
							 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB17 periph A */
					};
				};
			};

			macb0: ethernet@f802c000 {
				compatible = "cdns,at91sam9260-macb", "cdns,macb";
				reg = <0xf802c000 0x100>;
				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_macb0_rmii>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2
 * Ethernet interfaces.
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 */

#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	ahb {
		apb {
			pinctrl@fffff400 {
				macb1 {
					pinctrl_macb1_rmii: macb1_rmii-0 {
						atmel,pins =
							<AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC16 periph B */
							 AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC18 periph B */
							 AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC19 periph B */
							 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC20 periph B */
							 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC21 periph B */
							 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC27 periph B */
							 AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC28 periph B */
							 AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC29 periph B */
							 AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PC30 periph B */
							 AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC31 periph B */
					};
				};
			};

			macb1: ethernet@f8030000 {
				compatible = "cdns,at91sam9260-macb", "cdns,macb";
				reg = <0xf8030000 0x100>;
				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_macb1_rmii>;
				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
				clock-names = "hclk", "pclk";
				status = "disabled";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
 * 4 USART.
 *
 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 */

#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mfd/at91-usart.h>

/ {
	aliases {
		serial4 = &usart3;
	};

	ahb {
		apb {
			pinctrl@fffff400 {
				usart3 {
					pinctrl_usart3: usart3-0 {
						atmel,pins =
							<AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE
							 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
					};

					pinctrl_usart3_rts: usart3_rts-0 {
						atmel,pins =
							<AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC24 periph B */
					};

					pinctrl_usart3_cts: usart3_cts-0 {
						atmel,pins =
							<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC25 periph B */
					};

					pinctrl_usart3_sck: usart3_sck-0 {
						atmel,pins =
							<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;		/* PC26 periph B */
					};
				};
			};

			usart3: serial@f8028000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xf8028000 0x200>;
				atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_usart3>;
				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>,
				       <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
				dma-names = "tx", "rx";
				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
				clock-names = "usart";
				status = "disabled";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module
 *
 *  Copyright (C) 2012 Atmel,
 *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
 */

/ {
	memory@20000000 {
		reg = <0x20000000 0x8000000>;
	};

	clocks {
		slow_xtal {
			clock-frequency = <32768>;
		};

		main_xtal {
			clock-frequency = <12000000>;
		};
	};

	ahb {
		apb {
			tcb0: timer@f8008000 {
				timer@0 {
					compatible = "atmel,tcb-timer";
					reg = <0>;
				};

				timer@1 {
					compatible = "atmel,tcb-timer";
					reg = <1>;
				};
			};

			pinctrl@fffff400 {
				1wire_cm {
					pinctrl_1wire_cm: 1wire_cm-0 {
						atmel,pins = <AT91_PIOB 18 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB18 multidrive, conflicts with led */
					};
				};
			};

			rtc@fffffeb0 {
				status = "okay";
			};
		};

		ebi: ebi@10000000 {
			pinctrl-0 = <&pinctrl_ebi_addr_nand
				     &pinctrl_ebi_data_0_7>;
			pinctrl-names = "default";
			status = "okay";

			nand_controller: nand-controller {
				status = "okay";
				pinctrl-0 = <&pinctrl_nand_oe_we
					     &pinctrl_nand_cs
					     &pinctrl_nand_rb>;
				pinctrl-names = "default";

				nand@3 {
					reg = <0x3 0x0 0x800000>;
					rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
					cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
					nand-bus-width = <8>;
					nand-ecc-mode = "hw";
					nand-ecc-strength = <2>;
					nand-ecc-step-size = <512>;
					nand-on-flash-bbt;
					label = "atmel_nand";

					partitions {
						compatible = "fixed-partitions";
						#address-cells = <1>;
						#size-cells = <1>;

						at91bootstrap@0 {
							label = "at91bootstrap";
							reg = <0x0 0x40000>;
						};

						uboot@40000 {
							label = "u-boot";
							reg = <0x40000 0xc0000>;
						};

						ubootenvred@100000 {
							label = "U-Boot Env Redundant";
							reg = <0x100000 0x40000>;
						};

						ubootenv@140000 {
							label = "U-Boot Env";
							reg = <0x140000 0x40000>;
						};

						dtb@180000 {
							label = "device tree";
							reg = <0x180000 0x80000>;
						};

						kernel@200000 {
							label = "kernel";
							reg = <0x200000 0x600000>;
						};

						rootfs@800000 {
							label = "rootfs";
							reg = <0x800000 0x0f800000>;
						};
					};
				};
			};
		};
	};

	leds {
		compatible = "gpio-leds";

		pb18 {
			label = "pb18";
			gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
		};

		pd21 {
			label = "pd21";
			gpios = <&pioD 21 GPIO_ACTIVE_HIGH>;
		};
	};

	1wire_cm {
		compatible = "w1-gpio";
		gpios = <&pioB 18 GPIO_ACTIVE_HIGH>;
		linux,open-drain;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_1wire_cm>;
		status = "okay";
	};

};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module
 *
 *  Copyright (C) 2014 Atmel,
 *                2014 Free Electrons
 *
 *  Author: Boris Brezillon <boris.brezillon@free-electrons.com>
 */

/ {
	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&hlcdc_pwm 0 50000 0>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
		power-supply = <&bl_reg>;
		status = "disabled";
	};

	bl_reg: backlight_regulator {
		compatible = "regulator-fixed";
		regulator-name = "backlight-power-supply";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		status = "disabled";
	};

	panel: panel {
		compatible = "foxlink,fl500wvr00-a0t";
		backlight = <&backlight>;
		power-supply = <&panel_reg>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		port@0 {
			#address-cells = <1>;
			#size-cells = <0>;

			panel_input: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&hlcdc_panel_output>;
			};
		};
	};

	panel_reg: panel_regulator {
		compatible = "regulator-fixed";
		regulator-name = "panel-power-supply";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		status = "disabled";
	};
};

&adc0 {
	atmel,adc-ts-wires = <4>;
	atmel,adc-ts-pressure-threshold = <10000>;
	status = "okay";
};

&i2c0 {
	keyboard@1b {
		compatible = "qt1070";
		reg = <0x1b>;
		interrupt-parent = <&pioA>;
		interrupts = <7 0x0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_qt1070_irq>;
		wakeup-source;
	};
};

&hlcdc {
	hlcdc-display-controller {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;

		port@0 {
			hlcdc_panel_output: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&panel_input>;
			};
		};
	};
};

&pinctrl {
	board {
		pinctrl_qt1070_irq: qt1070_irq {
			atmel,pins =
				<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
 *
 *  Copyright (C) 2012 Atmel,
 *                2012 Nicolas Ferre <nicolas.ferre@atmel.com>
 */
#include "at91sam9x5cm.dtsi"

/ {
	model = "Atmel AT91SAM9X5-EK";
	compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";

	chosen {
		bootargs = "root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
		stdout-path = "serial0:115200n8";
	};

	sound {
		compatible = "atmel,sam9x5-wm8731-audio";

		atmel,model = "wm8731 @ AT91SAM9X5EK";

		atmel,audio-routing =
			"Headphone Jack", "RHPOUT",
			"Headphone Jack", "LHPOUT",
			"LLINEIN", "Line In Jack",
			"RLINEIN", "Line In Jack";

		atmel,ssc-controller = <&ssc0>;
		atmel,audio-codec = <&wm8731>;
	};
};

&adc0 {
	atmel,adc-ts-wires = <4>;
	atmel,adc-ts-pressure-threshold = <10000>;
	status = "okay";
};

&dbgu {
	status = "okay";
};

&i2c0 {
	status = "okay";

	wm8731: wm8731@1a {
		compatible = "wm8731";
		reg = <0x1a>;
	};
};

&mmc0 {
	pinctrl-0 = <
		&pinctrl_board_mmc0
		&pinctrl_mmc0_slot0_clk_cmd_dat0
		&pinctrl_mmc0_slot0_dat1_3>;
	pinctrl-names = "default";
	status = "okay";

	slot@0 {
		reg = <0>;
		bus-width = <4>;
		cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
	};
};

&mmc1 {
	pinctrl-0 = <
		&pinctrl_board_mmc1
		&pinctrl_mmc1_slot0_clk_cmd_dat0
		&pinctrl_mmc1_slot0_dat1_3>;
	pinctrl-names = "default";
	status = "okay";

	slot@0 {
		reg = <0>;
		bus-width = <4>;
		cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;
	};
};

&pinctrl {
	camera_sensor {
		pinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 {
			atmel,pins =
				<AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* ISI_MCK */
		};

		pinctrl_sensor_power: sensor_power-0 {
			atmel,pins =
				<AT91_PIOA 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
		};

		pinctrl_sensor_reset: sensor_reset-0 {
			atmel,pins =
				<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
		};
	};

	mmc0 {
		pinctrl_board_mmc0: mmc0-board {
			atmel,pins =
				<AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;	/* PD15 gpio CD pin pull up and deglitch */
		};
	};

	mmc1 {
		pinctrl_board_mmc1: mmc1-board {
			atmel,pins =
				<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;	/* PD14 gpio CD pin pull up and deglitch */
		};
	};

	usb2 {
		pinctrl_board_usb2: usb2-board {
			atmel,pins =
				<AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;		/* PB16 gpio vbus sense, deglitch */
		};
	};
};

&spi0 {
	cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
	status = "disabled"; /* conflicts with mmc1 */

	flash@0 {
		compatible = "atmel,at25df321a";
		spi-max-frequency = <50000000>;
		reg = <0>;
	};
};

&ssc0 {
	status = "okay";
};

&usart0 {
	atmel,use-dma-rx;
	atmel,use-dma-tx;
	status = "okay";
};

&usb0 {
	num-ports = <3>;
	atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */
			   &pioD 19 GPIO_ACTIVE_LOW
			   &pioD 20 GPIO_ACTIVE_LOW
			  >;
	status = "okay";
};

&usb1 {
	status = "okay";
};

&usb2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_board_usb2>;
	atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&watchdog {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC
 *
 *  Copyright (C) 2015 Atmel,
 *                2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com>
 */

#include "at91sam9260.dtsi"

/ {
	model = "Atmel AT91SAM9XE family SoC";
	compatible = "atmel,at91sam9xe", "atmel,at91sam9260";

	sram0: sram@2ff000 {
		status = "disabled";
	};

	sram1: sram@300000 {
		compatible = "mmio-sram";
		reg = <0x00300000 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x00300000 0x4000>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * arch/arm/boot/dts/axm5516-amarillo.dts
 *
 * Copyright (C) 2013 LSI
 */

/dts-v1/;

/memreserve/ 0x00000000 0x00400000;

#include "axm55xx.dtsi"
#include "axm5516-cpus.dtsi"

/ {
	model = "Amarillo AXM5516";
	compatible = "lsi,axm5516-amarillo", "lsi,axm5516";

	memory {
		device_type = "memory";
		reg = <0 0x00000000 0x02 0x00000000>;
	};
};

&serial0 {
	status = "okay";
};

&serial1 {
	status = "okay";
};

&serial2 {
	status = "okay";
};

&serial3 {
	status = "okay";
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * arch/arm/boot/dts/axm5516-cpus.dtsi
 *
 * Copyright (C) 2013 LSI
 */

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
				core1 {
					cpu = <&CPU1>;
				};
				core2 {
					cpu = <&CPU2>;
				};
				core3 {
					cpu = <&CPU3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};
				core1 {
					cpu = <&CPU5>;
				};
				core2 {
					cpu = <&CPU6>;
				};
				core3 {
					cpu = <&CPU7>;
				};
			};
			cluster2 {
				core0 {
					cpu = <&CPU8>;
				};
				core1 {
					cpu = <&CPU9>;
				};
				core2 {
					cpu = <&CPU10>;
				};
				core3 {
					cpu = <&CPU11>;
				};
			};
			cluster3 {
				core0 {
					cpu = <&CPU12>;
				};
				core1 {
					cpu = <&CPU13>;
				};
				core2 {
					cpu = <&CPU14>;
				};
				core3 {
					cpu = <&CPU15>;
				};
			};
		};

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x00>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x01>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x02>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x03>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x100>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x101>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x102>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x103>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU8: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x200>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU9: cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x201>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU10: cpu@202 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x202>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU11: cpu@203 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x203>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU12: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x300>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU13: cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x301>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU14: cpu@302 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x302>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};

		CPU15: cpu@303 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x303>;
			clock-frequency = <1400000000>;
			cpu-release-addr = <0>; // Fixed by the boot loader
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * arch/arm/boot/dts/axm55xx.dtsi
 *
 * Copyright (C) 2013 LSI
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/lsi,axm5516-clks.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	aliases {
		serial0	  = &serial0;
		serial1   = &serial1;
		serial2	  = &serial2;
		serial3	  = &serial3;
		timer	  = &timer0;
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		clk_ref0: clk_ref0 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <125000000>;
		};

		clk_ref1: clk_ref1 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <125000000>;
		};

		clk_ref2: clk_ref2 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <125000000>;
		};

		clks: clock-controller@2010020000 {
			compatible = "lsi,axm5516-clks";
			#clock-cells = <1>;
			reg = <0x20 0x10020000 0 0x20000>;
		};
	};

	gic: interrupt-controller@2001001000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x20 0x01001000 0 0x1000>,
		      <0x20 0x01002000 0 0x2000>,
		      <0x20 0x01004000 0 0x2000>,
		      <0x20 0x01006000 0 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
				IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts =
			<GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		compatible = "simple-bus";
		device_type = "soc";
		#address-cells = <2>;
		#size-cells = <2>;
		interrupt-parent = <&gic>;
		ranges;

		syscon: syscon@2010030000 {
			compatible = "lsi,axxia-syscon", "syscon";
			reg = <0x20 0x10030000 0 0x2000>;
		};

		reset: reset@2010031000 {
			compatible = "lsi,axm55xx-reset";
			syscon = <&syscon>;
		};

		amba {
			compatible = "simple-bus";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			serial0: uart@2010080000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x20 0x10080000 0 0x1000>;
				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks AXXIA_CLK_PER>;
				clock-names = "apb_pclk";
				status = "disabled";
			};

			serial1: uart@2010081000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x20 0x10081000 0 0x1000>;
				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks AXXIA_CLK_PER>;
				clock-names = "apb_pclk";
				status = "disabled";
			};

			serial2: uart@2010082000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x20 0x10082000 0 0x1000>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks AXXIA_CLK_PER>;
				clock-names = "apb_pclk";
				status = "disabled";
			};

			serial3: uart@2010083000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x20 0x10083000 0 0x1000>;
				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks AXXIA_CLK_PER>;
				clock-names = "apb_pclk";
				status = "disabled";
			};

			timer0: timer@2010091000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x20 0x10091000 0 0x1000>;
				interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks AXXIA_CLK_PER>;
				clock-names = "apb_pclk";
				status = "okay";
			};

			gpio0: gpio@2010092000 {
				#gpio-cells = <2>;
				compatible = "arm,pl061", "arm,primecell";
				gpio-controller;
				reg = <0x20 0x10092000 0x00 0x1000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks AXXIA_CLK_PER>;
				clock-names = "apb_pclk";
				status = "disabled";
			};

			gpio1: gpio@2010093000 {
				#gpio-cells = <2>;
				compatible = "arm,pl061", "arm,primecell";
				gpio-controller;
				reg = <0x20 0x10093000 0x00 0x1000>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks AXXIA_CLK_PER>;
				clock-names = "apb_pclk";
				status = "disabled";
			};
		};
	};
};

/*
  Local Variables:
  mode: C
  End:
*/


code:
/*
 * Copyright 2015 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

&axp152 {
	compatible = "x-powers,axp152";
	interrupt-controller;
	#interrupt-cells = <1>;
};


code:
/*
 * Copyright 2015 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * AXP202/209 Integrated Power Management Chip
 * http://www.x-powers.com/product/AXP20X.php
 * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
 */

&axp209 {
	compatible = "x-powers,axp209";
	interrupt-controller;
	#interrupt-cells = <1>;

	ac_power_supply: ac-power {
		compatible = "x-powers,axp202-ac-power-supply";
		status = "disabled";
	};

	axp_adc: adc {
		compatible = "x-powers,axp209-adc";
		#io-channel-cells = <1>;
	};

	axp_gpio: gpio {
		compatible = "x-powers,axp209-gpio";
		gpio-controller;
		#gpio-cells = <2>;
	};

	battery_power_supply: battery-power {
		compatible = "x-powers,axp209-battery-power-supply";
		status = "disabled";
	};

	regulators {
		/* Default work frequency for buck regulators */
		x-powers,dcdc-freq = <1500>;

		reg_dcdc2: dcdc2 {
			regulator-name = "dcdc2";
		};

		reg_dcdc3: dcdc3 {
			regulator-name = "dcdc3";
		};

		reg_ldo1: ldo1 {
			/* LDO1 is a fixed output regulator */
			regulator-always-on;
			regulator-min-microvolt = <1300000>;
			regulator-max-microvolt = <1300000>;
			regulator-name = "ldo1";
		};

		reg_ldo2: ldo2 {
			regulator-name = "ldo2";
		};

		reg_ldo3: ldo3 {
			regulator-name = "ldo3";
		};

		reg_ldo4: ldo4 {
			regulator-name = "ldo4";
		};

		reg_ldo5: ldo5 {
			regulator-name = "ldo5";
			status = "disabled";
		};
	};

	usb_power_supply: usb-power {
		compatible = "x-powers,axp202-usb-power-supply";
		status = "disabled";
	};
};


code:
/*
 * Copyright 2016 Free Electrons
 *
 * Quentin Schulz <quentin.schulz@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * AXP223 Integrated Power Management Chip
 * http://www.x-powers.com/product/AXP22X.php
 * http://dl.linux-sunxi.org/AXP/AXP223-en.pdf
 *
 * The AXP223 shares most of its logic with the AXP221 but it has some
 * differences, for the VBUS driver for example.
 */

#include "axp22x.dtsi"

&usb_power_supply {
	compatible = "x-powers,axp223-usb-power-supply";
};


code:
/*
 * Copyright 2015 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * AXP221/221s/223 Integrated Power Management Chip
 * http://www.x-powers.com/product/AXP22X.php
 * http://dl.linux-sunxi.org/AXP/AXP221%20Datasheet%20V1.2%2020130326%20.pdf
 */

&axp22x {
	interrupt-controller;
	#interrupt-cells = <1>;

	ac_power_supply: ac-power {
		compatible = "x-powers,axp221-ac-power-supply";
		status = "disabled";
	};

	axp_adc: adc {
		compatible = "x-powers,axp221-adc";
		#io-channel-cells = <1>;
	};

	battery_power_supply: battery-power {
		compatible = "x-powers,axp221-battery-power-supply";
		status = "disabled";
	};

	axp_gpio: gpio {
		compatible = "x-powers,axp221-gpio";
		gpio-controller;
		#gpio-cells = <2>;
	};

	regulators {
		/* Default work frequency for buck regulators */
		x-powers,dcdc-freq = <3000>;

		reg_dcdc1: dcdc1 {
			regulator-name = "dcdc1";
		};

		reg_dcdc2: dcdc2 {
			regulator-name = "dcdc2";
		};

		reg_dcdc3: dcdc3 {
			regulator-name = "dcdc3";
		};

		reg_dcdc4: dcdc4 {
			regulator-name = "dcdc4";
		};

		reg_dcdc5: dcdc5 {
			regulator-name = "dcdc5";
		};

		reg_dc1sw: dc1sw {
			regulator-name = "dc1sw";
		};

		reg_dc5ldo: dc5ldo {
			regulator-name = "dc5ldo";
		};

		reg_aldo1: aldo1 {
			regulator-name = "aldo1";
		};

		reg_aldo2: aldo2 {
			regulator-name = "aldo2";
		};

		reg_aldo3: aldo3 {
			regulator-name = "aldo3";
		};

		reg_dldo1: dldo1 {
			regulator-name = "dldo1";
		};

		reg_dldo2: dldo2 {
			regulator-name = "dldo2";
		};

		reg_dldo3: dldo3 {
			regulator-name = "dldo3";
		};

		reg_dldo4: dldo4 {
			regulator-name = "dldo4";
		};

		reg_eldo1: eldo1 {
			regulator-name = "eldo1";
		};

		reg_eldo2: eldo2 {
			regulator-name = "eldo2";
		};

		reg_eldo3: eldo3 {
			regulator-name = "eldo3";
		};

		reg_ldo_io0: ldo_io0 {
			regulator-name = "ldo_io0";
			status = "disabled";
		};

		reg_ldo_io1: ldo_io1 {
			regulator-name = "ldo_io1";
			status = "disabled";
		};

		reg_rtc_ldo: rtc_ldo {
			/* RTC_LDO is a fixed, always-on regulator */
			regulator-always-on;
			regulator-min-microvolt = <3000000>;
			regulator-max-microvolt = <3000000>;
			regulator-name = "rtc_ldo";
		};

		reg_drivevbus: drivevbus {
			regulator-name = "drivevbus";
			status = "disabled";
		};
	};

	usb_power_supply: usb-power {
		compatible = "x-powers,axp221-usb-power-supply";
		status = "disabled";
	};
};


code:
/*
 * Copyright 2015 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * AXP809 Integrated Power Management Chip
 */

&axp809 {
	compatible = "x-powers,axp809";
	interrupt-controller;
	#interrupt-cells = <1>;

	axp_gpio: gpio {
		compatible = "x-powers,axp809-gpio",
			     "x-powers,axp221-gpio";
		gpio-controller;
		#gpio-cells = <2>;
	};
};


code:
/*
 * Copyright 2017 Chen-Yu Tsai
 *
 * Chen-Yu Tsai <wens@csie.org>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/* AXP813/818 Integrated Power Management Chip */

&axp81x {
	interrupt-controller;
	#interrupt-cells = <1>;

	ac_power_supply: ac-power {
		compatible = "x-powers,axp813-ac-power-supply";
		status = "disabled";
	};

	axp_adc: adc {
		compatible = "x-powers,axp813-adc";
		#io-channel-cells = <1>;
	};

	axp_gpio: gpio {
		compatible = "x-powers,axp813-gpio";
		gpio-controller;
		#gpio-cells = <2>;
	};

	battery_power_supply: battery-power {
		compatible = "x-powers,axp813-battery-power-supply";
		status = "disabled";
	};

	regulators {
		/* Default work frequency for buck regulators */
		x-powers,dcdc-freq = <3000>;

		reg_dcdc1: dcdc1 {
		};

		reg_dcdc2: dcdc2 {
		};

		reg_dcdc3: dcdc3 {
		};

		reg_dcdc4: dcdc4 {
		};

		reg_dcdc5: dcdc5 {
		};

		reg_dcdc6: dcdc6 {
		};

		reg_dcdc7: dcdc7 {
		};

		reg_aldo1: aldo1 {
		};

		reg_aldo2: aldo2 {
		};

		reg_aldo3: aldo3 {
		};

		reg_dldo1: dldo1 {
		};

		reg_dldo2: dldo2 {
		};

		reg_dldo3: dldo3 {
		};

		reg_dldo4: dldo4 {
		};

		reg_eldo1: eldo1 {
		};

		reg_eldo2: eldo2 {
		};

		reg_eldo3: eldo3 {
		};

		reg_fldo1: fldo1 {
		};

		reg_fldo2: fldo2 {
		};

		reg_fldo3: fldo3 {
		};

		reg_ldo_io0: ldo-io0 {
			/* Disable by default to avoid conflicts with GPIO */
			status = "disabled";
		};

		reg_ldo_io1: ldo-io1 {
			/* Disable by default to avoid conflicts with GPIO */
			status = "disabled";
		};

		reg_rtc_ldo: rtc-ldo {
			/* RTC_LDO is a fixed, always-on regulator */
			regulator-always-on;
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};

		reg_sw: sw {
		};

		reg_drivevbus: drivevbus {
			status = "disabled";
		};
	};

	usb_power_supply: usb-power {
		compatible = "x-powers,axp813-usb-power-supply";
	};
};


code:
/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	osc: oscillator {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <25000000>;
	};

	/* Cygnus ARM PLL */
	armpll: armpll@19000000 {
		#clock-cells = <0>;
		compatible = "brcm,cygnus-armpll";
		clocks = <&osc>;
		reg = <0x19000000 0x1000>;
	};

	/* peripheral clock for system timer */
	periph_clk: arm_periph_clk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&armpll>;
		clock-div = <2>;
		clock-mult = <1>;
	};

	/* APB bus clock */
	apb_clk: apb_clk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&armpll>;
		clock-div = <4>;
		clock-mult = <1>;
	};

	genpll: genpll@301d000 {
		#clock-cells = <1>;
		compatible = "brcm,cygnus-genpll";
		reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
		clocks = <&osc>;
		clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
				     "enet_sw", "audio_125", "can";
	};

	/* always 1/2 of the axi21 clock */
	axi41_clk: axi41_clk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&genpll 1>;
		clock-div = <2>;
		clock-mult = <1>;
	};

	/* always 1/4 of the axi21 clock */
	axi81_clk: axi81_clk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&genpll 1>;
		clock-div = <4>;
		clock-mult = <1>;
	};

	lcpll0: lcpll0@301d02c {
		#clock-cells = <1>;
		compatible = "brcm,cygnus-lcpll0";
		reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>;
		clocks = <&osc>;
		clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio",
				     "usb_phy", "smart_card", "ch5";
	};

	mipipll: mipipll@180a9800 {
		#clock-cells = <1>;
		compatible = "brcm,cygnus-mipipll";
		reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>;
		clocks = <&osc>;
		clock-output-names = "mipipll", "ch0_unused", "ch1_lcd",
				     "ch2_v3d", "ch3_unused", "ch4_unused",
				     "ch5_unused";
	};

	asiu_clks: asiu_clks@301d048 {
		#clock-cells = <1>;
		compatible = "brcm,cygnus-asiu-clk";
		reg = <0x0301d048 0xc>, <0x180aa024 0x4>;

		clocks = <&osc>;
		clock-output-names = "keypad", "adc/touch", "pwm";
	};

	audiopll: audiopll@180aeb00 {
		#clock-cells = <1>;
		compatible = "brcm,cygnus-audiopll";
		reg = <0x180aeb00 0x68>;
		clocks = <&osc>;
		clock-output-names = "audiopll", "ch0_audio",
					"ch1_audio", "ch2_audio";
	};
};