code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SC7280

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SC7280.

  See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h

properties:
  compatible:
    const: qcom,gcc-sc7280

  clocks:
    items:
      - description: Board XO source
      - description: Board active XO source
      - description: Sleep clock source
      - description: PCIE-0 pipe clock source
      - description: PCIE-1 pipe clock source
      - description: USF phy rx symbol 0 clock source
      - description: USF phy rx symbol 1 clock source
      - description: USF phy tx symbol 0 clock source
      - description: USB30 phy wrapper pipe clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: bi_tcxo_ao
      - const: sleep_clk
      - const: pcie_0_pipe_clk
      - const: pcie_1_pipe_clk
      - const: ufs_phy_rx_symbol_0_clk
      - const: ufs_phy_rx_symbol_1_clk
      - const: ufs_phy_tx_symbol_0_clk
      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sc7280";
      reg = <0x00100000 0x1f0000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&rpmhcc RPMH_CXO_CLK_A>,
               <&sleep_clk>,
               <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
               <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
               <&ufs_phy_tx_symbol_0_clk>,
               <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;

      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk",
                     "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
                     "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
                     "usb3_phy_wrapper_gcc_usb30_pipe_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8180x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SC8180x

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SC8180x.

  See also:: include/dt-bindings/clock/qcom,gcc-sc8180x.h

properties:
  compatible:
    const: qcom,gcc-sc8180x

  clocks:
    items:
      - description: Board XO source
      - description: Board active XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: bi_tcxo_ao
      - const: sleep_clk

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sc8180x";
      reg = <0x00100000 0x1f0000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&rpmhcc RPMH_CXO_CLK_A>,
               <&sleep_clk>;
      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SC8280xp

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and
  power domains on SC8280xp.

  See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h

properties:
  compatible:
    const: qcom,gcc-sc8280xp

  clocks:
    items:
      - description: XO reference clock
      - description: Sleep clock
      - description: UFS memory first RX symbol clock
      - description: UFS memory second RX symbol clock
      - description: UFS memory first TX symbol clock
      - description: UFS card first RX symbol clock
      - description: UFS card second RX symbol clock
      - description: UFS card first TX symbol clock
      - description: Primary USB SuperSpeed pipe clock
      - description: USB4 PHY pipegmux clock source
      - description: USB4 PHY DP gmux clock source
      - description: USB4 PHY sys pipegmux clock source
      - description: USB4 PHY PCIe pipe clock
      - description: USB4 PHY router max pipe clock
      - description: Primary USB4 RX0 clock
      - description: Primary USB4 RX1 clock
      - description: Secondary USB SuperSpeed pipe clock
      - description: Second USB4 PHY pipegmux clock source
      - description: Second USB4 PHY DP gmux clock source
      - description: Second USB4 PHY sys pipegmux clock source
      - description: Second USB4 PHY PCIe pipe clock
      - description: Second USB4 PHY router max pipe clock
      - description: Secondary USB4 RX0 clock
      - description: Secondary USB4 RX1 clock
      - description: Multiport USB first SuperSpeed pipe clock
      - description: Multiport USB second SuperSpeed pipe clock
      - description: PCIe 2a pipe clock
      - description: PCIe 2b pipe clock
      - description: PCIe 3a pipe clock
      - description: PCIe 3b pipe clock
      - description: PCIe 4 pipe clock
      - description: First EMAC controller reference clock
      - description: Second EMAC controller reference clock

  protected-clocks:
    maxItems: 389

required:
  - compatible
  - clocks

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sc8280xp";
      reg = <0x00100000 0x1f0000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&sleep_clk>,
               <&ufs_phy_rx_symbol_0_clk>,
               <&ufs_phy_rx_symbol_1_clk>,
               <&ufs_phy_tx_symbol_0_clk>,
               <&ufs_card_rx_symbol_0_clk>,
               <&ufs_card_rx_symbol_1_clk>,
               <&ufs_card_tx_symbol_0_clk>,
               <&usb_0_ssphy>,
               <&gcc_usb4_phy_pipegmux_clk_src>,
               <&gcc_usb4_phy_dp_gmux_clk_src>,
               <&gcc_usb4_phy_sys_pipegmux_clk_src>,
               <&usb4_phy_gcc_usb4_pcie_pipe_clk>,
               <&usb4_phy_gcc_usb4rtr_max_pipe_clk>,
               <&qusb4phy_gcc_usb4_rx0_clk>,
               <&qusb4phy_gcc_usb4_rx1_clk>,
               <&usb_1_ssphy>,
               <&gcc_usb4_1_phy_pipegmux_clk_src>,
               <&gcc_usb4_1_phy_dp_gmux_clk_src>,
               <&gcc_usb4_1_phy_sys_pipegmux_clk_src>,
               <&usb4_1_phy_gcc_usb4_pcie_pipe_clk>,
               <&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>,
               <&qusb4phy_1_gcc_usb4_rx0_clk>,
               <&qusb4phy_1_gcc_usb4_rx1_clk>,
               <&usb_2_ssphy>,
               <&usb_3_ssphy>,
               <&pcie2a_lane>,
               <&pcie2b_lane>,
               <&pcie3a_lane>,
               <&pcie3b_lane>,
               <&pcie4_lane>,
               <&rxc0_ref_clk>,
               <&rxc1_ref_clk>;

      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SDM660/SDM630/SDM636 Global Clock & Reset Controller

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <quic_tdas@quicinc.com>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SDM630, SDM636 and SDM660

  See also::
    include/dt-bindings/clock/qcom,gcc-sdm660.h  (qcom,gcc-sdm630 and qcom,gcc-sdm660)

$ref: qcom,gcc.yaml#

properties:
  compatible:
    enum:
      - qcom,gcc-sdm630
      - qcom,gcc-sdm660

  clocks:
    items:
      - description: XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: xo
      - const: sleep_clk

  power-domains:
    maxItems: 1

required:
  - compatible

unevaluatedProperties: false

examples:
  # Example for GCC for SDM660:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
        compatible = "qcom,gcc-sdm660";
        reg = <0x00100000 0x94000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        #power-domain-cells = <1>;

        clock-names = "xo", "sleep_clk";
        clocks = <&xo_board>,
                 <&sleep_clk>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SDM670 and SDM845

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SDM670 and SDM845

  See also:: include/dt-bindings/clock/qcom,gcc-sdm845.h

properties:
  compatible:
    enum:
      - qcom,gcc-sdm670
      - qcom,gcc-sdm845

  clocks:
    minItems: 3
    maxItems: 5

  clock-names:
    minItems: 3
    maxItems: 5

  power-domains:
    maxItems: 1

required:
  - compatible

allOf:
  - $ref: qcom,gcc.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: qcom,gcc-sdm670
    then:
      properties:
        clocks:
          items:
            - description: Board XO source
            - description: Board active XO source
            - description: Sleep clock source
        clock-names:
          items:
            - const: bi_tcxo
            - const: bi_tcxo_ao
            - const: sleep_clk

  - if:
      properties:
        compatible:
          contains:
            const: qcom,gcc-sdm845
    then:
      properties:
        clocks:
          items:
            - description: Board XO source
            - description: Board active XO source
            - description: Sleep clock source
            - description: PCIE 0 Pipe clock source
            - description: PCIE 1 Pipe clock source
        clock-names:
          items:
            - const: bi_tcxo
            - const: bi_tcxo_ao
            - const: sleep_clk
            - const: pcie_0_pipe_clk
            - const: pcie_1_pipe_clk

unevaluatedProperties: false

examples:
  # Example for GCC for SDM845:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sdm845";
      reg = <0x100000 0x1f0000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&rpmhcc RPMH_CXO_CLK_A>,
               <&sleep_clk>,
               <&pcie0_lane>,
               <&pcie1_lane>;
      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx55.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SDX55

maintainers:
  - Vinod Koul <vkoul@kernel.org>
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and
  power domains on SDX55

  See also:: include/dt-bindings/clock/qcom,gcc-sdx55.h

properties:
  compatible:
    const: qcom,gcc-sdx55

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source
      - description: PLL test clock source (Optional clock)
    minItems: 2

  clock-names:
    items:
      - const: bi_tcxo
      - const: sleep_clk
      - const: core_bi_pll_test_se # Optional clock
    minItems: 2

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sdx55";
      reg = <0x00100000 0x1f0000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&sleep_clk>, <&pll_test_clk>;
      clock-names = "bi_tcxo", "sleep_clk", "core_bi_pll_test_se";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SDX65

maintainers:
  - Vamsi krishna Lanka <quic_vamslank@quicinc.com>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SDX65

  See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h

properties:
  compatible:
    const: qcom,gcc-sdx65

  clocks:
    items:
      - description: Board XO source
      - description: Board active XO source
      - description: Sleep clock source
      - description: PCIE Pipe clock source
      - description: USB3 phy wrapper pipe clock source
      - description: PLL test clock source (Optional clock)
    minItems: 5

  clock-names:
    items:
      - const: bi_tcxo
      - const: bi_tcxo_ao
      - const: sleep_clk
      - const: pcie_pipe_clk
      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
      - const: core_bi_pll_test_se # Optional clock
    minItems: 5

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sdx65";
      reg = <0x100000 0x1f7400>;
      clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
               <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
                    "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6115.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SM6115 and SM4250

maintainers:
  - Iskren Chernev <iskren.chernev@gmail.com>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SM4250/6115.

  See also:: include/dt-bindings/clock/qcom,gcc-sm6115.h

properties:
  compatible:
    const: qcom,gcc-sm6115

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: sleep_clk

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmcc.h>
    clock-controller@1400000 {
        compatible = "qcom,gcc-sm6115";
        reg = <0x01400000 0x1f0000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        #power-domain-cells = <1>;
        clock-names = "bi_tcxo", "sleep_clk";
        clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SM6125

maintainers:
  - Konrad Dybcio <konrad.dybcio@somainline.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SM6125.

  See also:: include/dt-bindings/clock/qcom,gcc-sm6125.h

properties:
  compatible:
    const: qcom,gcc-sm6125

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: sleep_clk

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmcc.h>
    clock-controller@1400000 {
        compatible = "qcom,gcc-sm6125";
        reg = <0x01400000 0x1f0000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        #power-domain-cells = <1>;
        clock-names = "bi_tcxo", "sleep_clk";
        clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SM6350

maintainers:
  - Konrad Dybcio <konrad.dybcio@somainline.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SM6350.

  See also:: include/dt-bindings/clock/qcom,gcc-sm6350.h

properties:
  compatible:
    const: qcom,gcc-sm6350

  clocks:
    items:
      - description: Board XO source
      - description: Board active XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: bi_tcxo_ao
      - const: sleep_clk

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sm6350";
      reg = <0x00100000 0x1f0000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&rpmhcc RPMH_CXO_CLK_A>,
               <&sleep_clk>;
      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SM8150

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SM8150.

  See also:: include/dt-bindings/clock/qcom,gcc-sm8150.h

properties:
  compatible:
    const: qcom,gcc-sm8150

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: sleep_clk

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sm8150";
      reg = <0x00100000 0x1f0000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&sleep_clk>;
      clock-names = "bi_tcxo", "sleep_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SM8250

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SM8250.

  See also:: include/dt-bindings/clock/qcom,gcc-sm8250.h

properties:
  compatible:
    const: qcom,gcc-sm8250

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: sleep_clk

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sm8250";
      reg = <0x00100000 0x1f0000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&sleep_clk>;
      clock-names = "bi_tcxo", "sleep_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SM8350

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SM8350.

  See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h

properties:
  compatible:
    const: qcom,gcc-sm8350

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source
      - description: PLL test clock source (Optional clock)
      - description: PCIE 0 Pipe clock source (Optional clock)
      - description: PCIE 1 Pipe clock source (Optional clock)
      - description: UFS card Rx symbol 0 clock source (Optional clock)
      - description: UFS card Rx symbol 1 clock source (Optional clock)
      - description: UFS card Tx symbol 0 clock source (Optional clock)
      - description: UFS phy Rx symbol 0 clock source (Optional clock)
      - description: UFS phy Rx symbol 1 clock source (Optional clock)
      - description: UFS phy Tx symbol 0 clock source (Optional clock)
      - description: USB3 phy wrapper pipe clock source (Optional clock)
      - description: USB3 phy sec pipe clock source (Optional clock)
    minItems: 2

  clock-names:
    items:
      - const: bi_tcxo
      - const: sleep_clk
      - const: core_bi_pll_test_se # Optional clock
      - const: pcie_0_pipe_clk # Optional clock
      - const: pcie_1_pipe_clk # Optional clock
      - const: ufs_card_rx_symbol_0_clk # Optional clock
      - const: ufs_card_rx_symbol_1_clk # Optional clock
      - const: ufs_card_tx_symbol_0_clk # Optional clock
      - const: ufs_phy_rx_symbol_0_clk # Optional clock
      - const: ufs_phy_rx_symbol_1_clk # Optional clock
      - const: ufs_phy_tx_symbol_0_clk # Optional clock
      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
      - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
    minItems: 2

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sm8350";
      reg = <0x00100000 0x1f0000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&sleep_clk>;
      clock-names = "bi_tcxo", "sleep_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SM8450

maintainers:
  - Vinod Koul <vkoul@kernel.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SM8450

  See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h

properties:
  compatible:
    const: qcom,gcc-sm8450

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source
      - description: PCIE 0 Pipe clock source (Optional clock)
      - description: PCIE 1 Pipe clock source (Optional clock)
      - description: PCIE 1 Phy Auxillary clock source (Optional clock)
      - description: UFS Phy Rx symbol 0 clock source (Optional clock)
      - description: UFS Phy Rx symbol 1 clock source (Optional clock)
      - description: UFS Phy Tx symbol 0 clock source (Optional clock)
      - description: USB3 Phy wrapper pipe clock source (Optional clock)
    minItems: 2

  clock-names:
    items:
      - const: bi_tcxo
      - const: sleep_clk
      - const: pcie_0_pipe_clk # Optional clock
      - const: pcie_1_pipe_clk # Optional clock
      - const: pcie_1_phy_aux_clk # Optional clock
      - const: ufs_phy_rx_symbol_0_clk # Optional clock
      - const: ufs_phy_rx_symbol_1_clk # Optional clock
      - const: ufs_phy_tx_symbol_0_clk # Optional clock
      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
    minItems: 2

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sm8450";
      reg = <0x00100000 0x001f4200>;
      clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
      clock-names = "bi_tcxo", "sleep_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller Common Bindings

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Common bindings for Qualcomm global clock control module providing the
  clocks, resets and power domains.

properties:
  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

  protected-clocks:
    description:
      Protected clock specifier list as per common clock binding.

required:
  - reg
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: true

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Graphics Clock & Reset Controller on SDM630 and SDM660

maintainers:
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>

description: |
  Qualcomm graphics clock control module provides the clocks, resets and
  power domains on SDM630 and SDM660.

  See also dt-bindings/clock/qcom,gpucc-sdm660.h.

properties:
  compatible:
    enum:
      - qcom,gpucc-sdm630
      - qcom,gpucc-sdm660

  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 main gpu branch
      - description: GPLL0 divider gpu branch

  clock-names:
    items:
      - const: xo
      - const: gcc_gpu_gpll0_clk
      - const: gcc_gpu_gpll0_div_clk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sdm660.h>
    #include <dt-bindings/clock/qcom,rpmcc.h>

    clock-controller@5065000 {
      compatible = "qcom,gpucc-sdm660";
      reg = <0x05065000 0x9038>;
      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
               <&gcc GCC_GPU_GPLL0_CLK>,
               <&gcc GCC_GPU_GPLL0_DIV_CLK>;
      clock-names = "xo", "gcc_gpu_gpll0_clk",
                    "gcc_gpu_gpll0_div_clk";
      #clock-cells = <1>;
      #power-domain-cells = <1>;
      #reset-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Graphics Clock & Reset Controller on SM8350

maintainers:
  - Robert Foss <robert.foss@linaro.org>

description: |
  Qualcomm graphics clock control module provides the clocks, resets and power
  domains on Qualcomm SoCs.

  See also:: include/dt-bindings/clock/qcom,gpucc-sm8350.h

properties:
  compatible:
    enum:
      - qcom,sm8350-gpucc

  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 main branch source
      - description: GPLL0 div branch source

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sm8350.h>
    #include <dt-bindings/clock/qcom,rpmh.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        clock-controller@3d90000 {
            compatible = "qcom,sm8350-gpucc";
            reg = <0 0x03d90000 0 0x9000>;
            clocks = <&rpmhcc RPMH_CXO_CLK>,
                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
            #clock-cells = <1>;
            #reset-cells = <1>;
            #power-domain-cells = <1>;
        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Graphics Clock & Reset Controller

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm graphics clock control module provides the clocks, resets and power
  domains on Qualcomm SoCs.

  See also::
    include/dt-bindings/clock/qcom,gpucc-sdm845.h
    include/dt-bindings/clock/qcom,gpucc-sc7180.h
    include/dt-bindings/clock/qcom,gpucc-sc7280.h
    include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
    include/dt-bindings/clock/qcom,gpucc-sm6350.h
    include/dt-bindings/clock/qcom,gpucc-sm8150.h
    include/dt-bindings/clock/qcom,gpucc-sm8250.h

properties:
  compatible:
    enum:
      - qcom,sdm845-gpucc
      - qcom,sc7180-gpucc
      - qcom,sc7280-gpucc
      - qcom,sc8180x-gpucc
      - qcom,sc8280xp-gpucc
      - qcom,sm6350-gpucc
      - qcom,sm8150-gpucc
      - qcom,sm8250-gpucc

  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 main branch source
      - description: GPLL0 div branch source

  clock-names:
    items:
      - const: bi_tcxo
      - const: gcc_gpu_gpll0_clk_src
      - const: gcc_gpu_gpll0_div_clk_src

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@5090000 {
      compatible = "qcom,sdm845-gpucc";
      reg = <0x05090000 0x9000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
      clock-names = "bi_tcxo",
                    "gcc_gpu_gpll0_clk_src",
                    "gcc_gpu_gpll0_div_clk_src";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
High-Frequency PLL (HFPLL)

PROPERTIES

- compatible:
	Usage: required
	Value type: <string>:
		shall contain only one of the following. The generic
		compatible "qcom,hfpll" should be also included.

                        "qcom,hfpll-ipq8064", "qcom,hfpll"
                        "qcom,hfpll-apq8064", "qcom,hfpll"
                        "qcom,hfpll-msm8974", "qcom,hfpll"
                        "qcom,hfpll-msm8960", "qcom,hfpll"

- reg:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: address and size of HPLL registers. An optional second
		    element specifies the address and size of the alias
		    register region.

- clocks:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: reference to the xo clock.

- clock-names:
	Usage: required
	Value type: <stringlist>
	Definition: must be "xo".

- clock-output-names:
	Usage: required
	Value type: <string>
	Definition: Name of the PLL. Typically hfpllX where X is a CPU number
		    starting at 0. Otherwise hfpll_Y where Y is more specific
		    such as "l2".

Example:

1) An HFPLL for the L2 cache.

	clock-controller@f9016000 {
		compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
		reg = <0xf9016000 0x30>;
		clocks = <&xo_board>;
		clock-names = "xo";
		clock-output-names = "hfpll_l2";
	};

2) An HFPLL for CPU0. This HFPLL has the alias register region.

	clock-controller@f908a000 {
		compatible = "qcom,hfpll-ipq8064", "qcom,hfpll";
		reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
		clocks = <&xo_board>;
		clock-names = "xo";
		clock-output-names = "hfpll0";
	};


code:
Krait Clock Controller

PROPERTIES

- compatible:
	Usage: required
	Value type: <string>
	Definition: must be one of:
			"qcom,krait-cc-v1"
			"qcom,krait-cc-v2"

- #clock-cells:
	Usage: required
	Value type: <u32>
	Definition: must be 1

- clocks:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: reference to the clock parents of hfpll, secondary muxes.

- clock-names:
	Usage: required
	Value type: <stringlist>
	Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb".

Example:

	kraitcc: clock-controller {
		compatible = "qcom,krait-cc-v1";
		clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, <qsb>;
		clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb";
		#clock-cells = <1>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,lcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm LPASS Clock & Reset Controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>

properties:
  compatible:
    enum:
      - qcom,lcc-apq8064
      - qcom,lcc-ipq8064
      - qcom,lcc-mdm9615
      - qcom,lcc-msm8960

  clocks:
    maxItems: 8

  clock-names:
    maxItems: 8

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - '#clock-cells'
  - '#reset-cells'

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,lcc-apq8064
              - qcom,lcc-msm8960
    then:
      properties:
        clocks:
          items:
            - description: Board PXO source
            - description: PLL 4 Vote clock
            - description: MI2S codec clock
            - description: Mic I2S codec clock
            - description: Mic I2S spare clock
            - description: Speaker I2S codec clock
            - description: Speaker I2S spare clock
            - description: PCM codec clock

        clock-names:
          items:
            - const: pxo
            - const: pll4_vote
            - const: mi2s_codec_clk
            - const: codec_i2s_mic_codec_clk
            - const: spare_i2s_mic_codec_clk
            - const: codec_i2s_spkr_codec_clk
            - const: spare_i2s_spkr_codec_clk
            - const: pcm_codec_clk

      required:
        - clocks
        - clock-names

examples:
  - |
    clock-controller@28000000 {
        compatible = "qcom,lcc-ipq8064";
        reg = <0x28000000 0x1000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Multimedia Clock & Reset Controller

maintainers:
  - Jeffrey Hugo <quic_jhugo@quicinc.com>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm multimedia clock control module provides the clocks, resets and
  power domains.

properties:
  compatible:
    enum:
      - qcom,mmcc-apq8064
      - qcom,mmcc-apq8084
      - qcom,mmcc-msm8226
      - qcom,mmcc-msm8660
      - qcom,mmcc-msm8960
      - qcom,mmcc-msm8974
      - qcom,mmcc-msm8992
      - qcom,mmcc-msm8994
      - qcom,mmcc-msm8996
      - qcom,mmcc-msm8998
      - qcom,mmcc-sdm630
      - qcom,mmcc-sdm660

  clocks:
    minItems: 8
    maxItems: 10

  clock-names:
    minItems: 8
    maxItems: 10

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

  protected-clocks:
    description:
      Protected clock specifier list as per common clock binding

  vdd-gfx-supply:
    description:
      Regulator supply for the GPU_GX GDSC

required:
  - compatible
  - reg
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,mmcc-apq8064
              - qcom,mmcc-msm8960
    then:
      properties:
        clocks:
          items:
            - description: Board PXO source
            - description: PLL 3 clock
            - description: PLL 3 Vote clock
            - description: DSI phy instance 1 dsi clock
            - description: DSI phy instance 1 byte clock
            - description: DSI phy instance 2 dsi clock
            - description: DSI phy instance 2 byte clock
            - description: HDMI phy PLL clock

        clock-names:
          items:
            - const: pxo
            - const: pll3
            - const: pll8_vote
            - const: dsi1pll
            - const: dsi1pllbyte
            - const: dsi2pll
            - const: dsi2pllbyte
            - const: hdmipll

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,mmcc-msm8974
    then:
      properties:
        clocks:
          items:
            - description: Board XO source
            - description: MMSS GPLL0 voted clock
            - description: GPLL0 voted clock
            - description: GPLL1 voted clock
            - description: GFX3D clock source
            - description: DSI phy instance 0 dsi clock
            - description: DSI phy instance 0 byte clock
            - description: DSI phy instance 1 dsi clock
            - description: DSI phy instance 1 byte clock
            - description: HDMI phy PLL clock
            - description: eDP phy PLL link clock
            - description: eDP phy PLL vco clock

        clock-names:
          items:
            - const: xo
            - const: mmss_gpll0_vote
            - const: gpll0_vote
            - const: gpll1_vote
            - const: gfx3d_clk_src
            - const: dsi0pll
            - const: dsi0pllbyte
            - const: dsi1pll
            - const: dsi1pllbyte
            - const: hdmipll
            - const: edp_link_clk
            - const: edp_vco_div

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,mmcc-msm8994
              - qcom,mmcc-msm8998
              - qcom,mmcc-sdm630
              - qcom,mmcc-sdm660
    then:
      required:
        - clocks
        - clock-names

  - if:
      properties:
        compatible:
          contains:
            const: qcom,mmcc-msm8994
    then:
      properties:
        clocks:
          items:
            - description: Board XO source
            - description: Global PLL 0 clock
            - description: MMSS NoC AHB clock
            - description: GFX3D clock
            - description: DSI phy instance 0 dsi clock
            - description: DSI phy instance 0 byte clock
            - description: DSI phy instance 1 dsi clock
            - description: DSI phy instance 1 byte clock
            - description: HDMI phy PLL clock

        clock-names:
          items:
            - const: xo
            - const: gpll0
            - const: mmssnoc_ahb
            - const: oxili_gfx3d_clk_src
            - const: dsi0pll
            - const: dsi0pllbyte
            - const: dsi1pll
            - const: dsi1pllbyte
            - const: hdmipll

  - if:
      properties:
        compatible:
          contains:
            const: qcom,mmcc-msm8996
    then:
      properties:
        clocks:
          items:
            - description: Board XO source
            - description: Global PLL 0 clock
            - description: MMSS NoC AHB clock
            - description: DSI phy instance 0 dsi clock
            - description: DSI phy instance 0 byte clock
            - description: DSI phy instance 1 dsi clock
            - description: DSI phy instance 1 byte clock
            - description: HDMI phy PLL clock

        clock-names:
          items:
            - const: xo
            - const: gpll0
            - const: gcc_mmss_noc_cfg_ahb_clk
            - const: dsi0pll
            - const: dsi0pllbyte
            - const: dsi1pll
            - const: dsi1pllbyte
            - const: hdmipll

  - if:
      properties:
        compatible:
          contains:
            const: qcom,mmcc-msm8998
    then:
      properties:
        clocks:
          items:
            - description: Board XO source
            - description: Global PLL 0 clock
            - description: DSI phy instance 0 dsi clock
            - description: DSI phy instance 0 byte clock
            - description: DSI phy instance 1 dsi clock
            - description: DSI phy instance 1 byte clock
            - description: HDMI phy PLL clock
            - description: DisplayPort phy PLL link clock
            - description: DisplayPort phy PLL vco clock
            - description: Test clock

        clock-names:
          items:
            - const: xo
            - const: gpll0
            - const: dsi0dsi
            - const: dsi0byte
            - const: dsi1dsi
            - const: dsi1byte
            - const: hdmipll
            - const: dplink
            - const: dpvco
            - const: core_bi_pll_test_se

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,mmcc-sdm630
              - qcom,mmcc-sdm660
    then:
      properties:
        clocks:
          items:
            - description: Board XO source
            - description: Board sleep source
            - description: Global PLL 0 clock
            - description: Global PLL 0 DIV clock
            - description: DSI phy instance 0 dsi clock
            - description: DSI phy instance 0 byte clock
            - description: DSI phy instance 1 dsi clock
            - description: DSI phy instance 1 byte clock
            - description: DisplayPort phy PLL link clock
            - description: DisplayPort phy PLL vco clock

        clock-names:
          items:
            - const: xo
            - const: sleep_clk
            - const: gpll0
            - const: gpll0_div
            - const: dsi0pll
            - const: dsi0pllbyte
            - const: dsi1pll
            - const: dsi1pllbyte
            - const: dp_link_2x_clk_divsel_five
            - const: dp_vco_divided_clk_src_mux

examples:
  # Example for MMCC for MSM8960:
  - |
    clock-controller@4000000 {
      compatible = "qcom,mmcc-msm8960";
      reg = <0x4000000 0x1000>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,msm8996-apcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm clock controller for MSM8996 CPUs

maintainers:
  - Loic Poulain <loic.poulain@linaro.org>

description: |
  Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster
  and clock 1 is for Perf cluster.

properties:
  compatible:
    enum:
      - qcom,msm8996-apcc

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: XO source

  clock-names:
    items:
      - const: xo

required:
  - compatible
  - reg
  - '#clock-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    kryocc: clock-controller@6400000 {
        compatible = "qcom,msm8996-apcc";
        reg = <0x6400000 0x90000>;
        #clock-cells = <1>;

        clocks = <&xo_board>;
        clock-names = "xo";
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Graphics Clock & Reset Controller on MSM8998

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm graphics clock control module provides the clocks, resets and power
  domains on MSM8998.

  See also:: include/dt-bindings/clock/qcom,gpucc-msm8998.h

properties:
  compatible:
    const: qcom,msm8998-gpucc

  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 main branch source (gcc_gpu_gpll0_clk_src)

  clock-names:
    items:
      - const: xo
      - const: gpll0

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8998.h>
    #include <dt-bindings/clock/qcom,rpmcc.h>
    clock-controller@5065000 {
      compatible = "qcom,msm8998-gpucc";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
      reg = <0x05065000 0x9000>;
      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0_OUT_MAIN>;
      clock-names = "xo", "gpll0";
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,q6sstopcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Q6SSTOP clock Controller

maintainers:
  - Govind Singh <govinds@codeaurora.org>

properties:
  compatible:
    const: qcom,qcs404-q6sstopcc

  reg:
    items:
      - description: Q6SSTOP clocks register region
      - description: Q6SSTOP_TCSR register region

  clocks:
    items:
      - description: ahb clock for the q6sstopCC

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    q6sstopcc: clock-controller@7500000 {
      compatible = "qcom,qcs404-q6sstopcc";
      reg = <0x07500000 0x4e000>, <0x07550000 0x10000>;
      clocks = <&gcc 141>;
      #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on QCM2290

maintainers:
  - Loic Poulain <loic.poulain@linaro.org>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on qcm2290.

  See also:: include/dt-bindings/clock/qcom,dispcc-qcm2290.h

properties:
  compatible:
    const: qcom,qcm2290-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: Board active-only XO source
      - description: GPLL0 source from GCC
      - description: GPLL0 div source from GCC
      - description: Byte clock from DSI PHY
      - description: Pixel clock from DSI PHY

  clock-names:
    items:
      - const: bi_tcxo
      - const: bi_tcxo_ao
      - const: gcc_disp_gpll0_clk_src
      - const: gcc_disp_gpll0_div_clk_src
      - const: dsi0_phy_pll_out_byteclk
      - const: dsi0_phy_pll_out_dsiclk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
    #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
    #include <dt-bindings/clock/qcom,rpmcc.h>
    clock-controller@5f00000 {
            compatible = "qcom,qcm2290-dispcc";
            reg = <0x5f00000 0x20000>;
            clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
                     <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
                     <&gcc GCC_DISP_GPLL0_CLK_SRC>,
                     <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
                     <&dsi0_phy 0>,
                     <&dsi0_phy 1>;
            clock-names = "bi_tcxo",
                          "bi_tcxo_ao",
                          "gcc_disp_gpll0_clk_src",
                          "gcc_disp_gpll0_div_clk_src",
                          "dsi0_phy_pll_out_byteclk",
                          "dsi0_phy_pll_out_dsiclk";
            #clock-cells = <1>;
            #reset-cells = <1>;
            #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,rpmcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm RPM Clock Controller

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description: |
  The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> and
  come in pairs:: FOO_CLK followed by FOO_A_CLK. The latter clock is
  an "active" clock, which means that the consumer only care that the clock is
  available when the apps CPU subsystem is active, i.e. not suspended or in
  deep idle. If it is important that the clock keeps running during system
  suspend, you need to specify the non-active clock, the one not containing
  *_A_* in the enumerator name.

properties:
  compatible:
    items:
      - enum:
          - qcom,rpmcc-apq8060
          - qcom,rpmcc-apq8064
          - qcom,rpmcc-ipq806x
          - qcom,rpmcc-mdm9607
          - qcom,rpmcc-msm8226
          - qcom,rpmcc-msm8660
          - qcom,rpmcc-msm8909
          - qcom,rpmcc-msm8916
          - qcom,rpmcc-msm8936
          - qcom,rpmcc-msm8953
          - qcom,rpmcc-msm8974
          - qcom,rpmcc-msm8976
          - qcom,rpmcc-msm8992
          - qcom,rpmcc-msm8994
          - qcom,rpmcc-msm8996
          - qcom,rpmcc-msm8998
          - qcom,rpmcc-qcm2290
          - qcom,rpmcc-qcs404
          - qcom,rpmcc-sdm660
          - qcom,rpmcc-sm6115
          - qcom,rpmcc-sm6125
          - qcom,rpmcc-sm6375
      - const: qcom,rpmcc

  '#clock-cells':
    const: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    maxItems: 2

required:
  - compatible
  - '#clock-cells'

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,rpmcc-apq8060
              - qcom,rpmcc-ipq806x
              - qcom,rpmcc-msm8660

    then:
      properties:
        clocks:
          items:
            - description: pxo clock

        clock-names:
          items:
            - const: pxo

  - if:
      properties:
        compatible:
          contains:
            const: qcom,rpmcc-apq8064
    then:
      properties:
        clocks:
          items:
            - description: pxo clock
            - description: cxo clock

        clock-names:
          items:
            - const: pxo
            - const: cxo

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,rpmcc-mdm9607
              - qcom,rpmcc-msm8226
              - qcom,rpmcc-msm8916
              - qcom,rpmcc-msm8936
              - qcom,rpmcc-msm8953
              - qcom,rpmcc-msm8974
              - qcom,rpmcc-msm8976
              - qcom,rpmcc-msm8992
              - qcom,rpmcc-msm8994
              - qcom,rpmcc-msm8996
              - qcom,rpmcc-msm8998
              - qcom,rpmcc-qcm2290
              - qcom,rpmcc-qcs404
              - qcom,rpmcc-sdm660
              - qcom,rpmcc-sm6115
              - qcom,rpmcc-sm6125

    then:
      properties:
        clocks:
          items:
            - description: xo clock

        clock-names:
          items:
            - const: xo

additionalProperties: false

examples:
  - |
    rpm {
        rpm-requests {
            compatible = "qcom,rpm-msm8916";
            qcom,smd-channels = "rpm_requests";

            clock-controller {
                compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
                #clock-cells = <1>;
            };
        };
    };

  - |
    rpm {
        clock-controller {
            compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
            #clock-cells = <1>;
            clocks = <&pxo_board>;
            clock-names = "pxo";
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,rpmhcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. RPMh Clocks Bindings

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Resource Power Manager Hardened (RPMh) manages shared resources on
  some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
  other hardware subsystems via RSC to control clocks.

properties:
  compatible:
    enum:
      - qcom,qdu1000-rpmh-clk
      - qcom,sc7180-rpmh-clk
      - qcom,sc7280-rpmh-clk
      - qcom,sc8180x-rpmh-clk
      - qcom,sc8280xp-rpmh-clk
      - qcom,sdm670-rpmh-clk
      - qcom,sdm845-rpmh-clk
      - qcom,sdx55-rpmh-clk
      - qcom,sdx65-rpmh-clk
      - qcom,sm6350-rpmh-clk
      - qcom,sm8150-rpmh-clk
      - qcom,sm8250-rpmh-clk
      - qcom,sm8350-rpmh-clk
      - qcom,sm8450-rpmh-clk

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: xo

  '#clock-cells':
    const: 1

required:
  - compatible
  - '#clock-cells'

additionalProperties: false

examples:
  # Example for GCC for SDM845: The below node should be defined inside
  # &apps_rsc node.
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    rpmhcc: clock-controller {
      compatible = "qcom,sdm845-rpmh-clk";
      clocks = <&xo_board>;
      clock-names = "xo";
      #clock-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7180-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Camera Clock & Reset Controller on SC7180

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm camera clock control module provides the clocks, resets and power
  domains on SC7180.

  See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h

properties:
  compatible:
    const: qcom,sc7180-camcc

  clocks:
    items:
      - description: Board XO source
      - description: Camera_ahb clock from GCC
      - description: Camera XO clock from GCC

  clock-names:
    items:
      - const: bi_tcxo
      - const: iface
      - const: xo

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@ad00000 {
      compatible = "qcom,sc7180-camcc";
      reg = <0x0ad00000 0x10000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&gcc GCC_CAMERA_AHB_CLK>,
               <&gcc GCC_CAMERA_XO_CLK>;
      clock-names = "bi_tcxo", "iface", "xo";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on SC7180

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on SC7180.

  See also:: include/dt-bindings/clock/qcom,dispcc-sc7180.h

properties:
  compatible:
    const: qcom,sc7180-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 source from GCC
      - description: Byte clock from DSI PHY
      - description: Pixel clock from DSI PHY
      - description: Link clock from DP PHY
      - description: VCO DIV clock from DP PHY

  clock-names:
    items:
      - const: bi_tcxo
      - const: gcc_disp_gpll0_clk_src
      - const: dsi0_phy_pll_out_byteclk
      - const: dsi0_phy_pll_out_dsiclk
      - const: dp_phy_pll_link_clk
      - const: dp_phy_pll_vco_div_clk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@af00000 {
      compatible = "qcom,sc7180-dispcc";
      reg = <0x0af00000 0x200000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&gcc GCC_DISP_GPLL0_CLK_SRC>,
               <&dsi_phy 0>,
               <&dsi_phy 1>,
               <&dp_phy 0>,
               <&dp_phy 1>;
      clock-names = "bi_tcxo",
                    "gcc_disp_gpll0_clk_src",
                    "dsi0_phy_pll_out_byteclk",
                    "dsi0_phy_pll_out_dsiclk",
                    "dp_phy_pll_link_clk",
                    "dp_phy_pll_vco_div_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm LPASS Core Clock Controller on SC7180

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm LPASS core clock control module provides the clocks and power
  domains on SC7180.

  See also:: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h

properties:
  compatible:
    enum:
      - qcom,sc7180-lpasshm
      - qcom,sc7180-lpasscorecc

  clocks:
    items:
      - description: gcc_lpass_sway clock from GCC
      - description: Board XO source

  clock-names:
    items:
      - const: iface
      - const: bi_tcxo

  power-domains:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    minItems: 1
    items:
      - description: lpass core cc register
      - description: lpass audio cc register

  reg-names:
    items:
      - const: lpass_core_cc
      - const: lpass_audio_cc

if:
  properties:
    compatible:
      contains:
        const: qcom,sc7180-lpasshm
then:
  properties:
    reg:
      maxItems: 1

else:
  properties:
    reg:
      minItems: 2

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
    #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
    clock-controller@63000000 {
      compatible = "qcom,sc7180-lpasshm";
      reg = <0x63000000 0x28>;
      clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>;
      clock-names = "iface", "bi_tcxo";
      #clock-cells = <1>;
      #power-domain-cells = <1>;
    };

  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
    #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
    clock-controller@62d00000 {
      compatible = "qcom,sc7180-lpasscorecc";
      reg = <0x62d00000 0x50000>, <0x62780000 0x30000>;
      reg-names = "lpass_core_cc", "lpass_audio_cc";
      clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>;
      clock-names = "iface", "bi_tcxo";
      power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
      #clock-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Modem Clock Controller on SC7180

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm modem clock control module provides the clocks on SC7180.

  See also:: include/dt-bindings/clock/qcom,mss-sc7180.h

properties:
  compatible:
    const: qcom,sc7180-mss

  clocks:
    items:
      - description: gcc_mss_mfab_axi clock from GCC
      - description: gcc_mss_nav_axi clock from GCC
      - description: gcc_mss_cfg_ahb clock from GCC

  clock-names:
    items:
      - const: gcc_mss_mfab_axis
      - const: gcc_mss_nav_axi
      - const: cfg_ahb

  '#clock-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
    clock-controller@41a8000 {
      compatible = "qcom,sc7180-mss";
      reg = <0x041a8000 0x8000>;
      clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>,
               <&gcc GCC_MSS_NAV_AXI_CLK>,
               <&gcc GCC_MSS_CFG_AHB_CLK>;
      clock-names = "gcc_mss_mfab_axis",
                    "gcc_mss_nav_axi",
                    "cfg_ahb";
      #clock-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7280-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Camera Clock & Reset Controller on SC7280

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm camera clock control module provides the clocks, resets and
  power domains on SC7280.

  See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h

properties:
  compatible:
    const: qcom,sc7280-camcc

  clocks:
    items:
      - description: Board XO source
      - description: Board XO active source
      - description: Sleep clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: bi_tcxo_ao
      - const: sleep_clk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@ad00000 {
      compatible = "qcom,sc7280-camcc";
      reg = <0x0ad00000 0x10000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&rpmhcc RPMH_CXO_CLK_A>,
               <&sleep_clk>;
      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on SC7280

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on SC7280.

  See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h

properties:
  compatible:
    const: qcom,sc7280-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 source from GCC
      - description: Byte clock from DSI PHY
      - description: Pixel clock from DSI PHY
      - description: Link clock from DP PHY
      - description: VCO DIV clock from DP PHY
      - description: Link clock from EDP PHY
      - description: VCO DIV clock from EDP PHY

  clock-names:
    items:
      - const: bi_tcxo
      - const: gcc_disp_gpll0_clk
      - const: dsi0_phy_pll_out_byteclk
      - const: dsi0_phy_pll_out_dsiclk
      - const: dp_phy_pll_link_clk
      - const: dp_phy_pll_vco_div_clk
      - const: edp_phy_pll_link_clk
      - const: edp_phy_pll_vco_div_clk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@af00000 {
      compatible = "qcom,sc7280-dispcc";
      reg = <0x0af00000 0x200000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&gcc GCC_DISP_GPLL0_CLK_SRC>,
               <&dsi_phy 0>,
               <&dsi_phy 1>,
               <&dp_phy 0>,
               <&dp_phy 1>,
               <&edp_phy 0>,
               <&edp_phy 1>;
      clock-names = "bi_tcxo",
                    "gcc_disp_gpll0_clk",
                    "dsi0_phy_pll_out_byteclk",
                    "dsi0_phy_pll_out_dsiclk",
                    "dp_phy_pll_link_clk",
                    "dp_phy_pll_vco_div_clk",
                    "edp_phy_pll_link_clk",
                    "edp_phy_pll_vco_div_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm LPASS Core Clock Controller on SC7280

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm LPASS core clock control module provides the clocks and power
  domains on SC7280.

  See also:: include/dt-bindings/clock/qcom,lpass-sc7280.h

properties:
  compatible:
    enum:
      - qcom,sc7280-lpasscc

  clocks:
    items:
      - description: gcc_cfg_noc_lpass_clk from GCC

  clock-names:
    items:
      - const: iface

  '#clock-cells':
    const: 1

  reg:
    items:
      - description: LPASS qdsp6ss register
      - description: LPASS top-cc register

  reg-names:
    items:
      - const: qdsp6ss
      - const: top_cc

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/clock/qcom,lpass-sc7280.h>
    clock-controller@3000000 {
      compatible = "qcom,sc7280-lpasscc";
      reg = <0x03000000 0x40>, <0x03c04000 0x4>;
      reg-names = "qdsp6ss", "top_cc";
      clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
      clock-names = "iface";
      #clock-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm LPASS Core & Audio Clock Controller on SC7280

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm LPASS core and audio clock control module provides the clocks and
  power domains on SC7280.

  See also::
    include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
    include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h

properties:
  clocks: true

  clock-names: true

  reg: true

  compatible:
    enum:
      - qcom,sc7280-lpassaoncc
      - qcom,sc7280-lpassaudiocc
      - qcom,sc7280-lpasscorecc
      - qcom,sc7280-lpasshm

  power-domains:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  '#reset-cells':
    const: 1

  qcom,adsp-pil-mode:
    description:
      Indicates if the LPASS would be brought out of reset using
      peripheral loader.
    type: boolean

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#power-domain-cells'

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: qcom,sc7280-lpassaudiocc

    then:
      properties:
        clocks:
          items:
            - description: Board XO source
            - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC

        clock-names:
          items:
            - const: bi_tcxo
            - const: lpass_aon_cc_main_rcg_clk_src

        reg:
          items:
            - description: lpass core cc register
            - description: lpass audio csr register
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc7280-lpassaoncc

    then:
      properties:
        clocks:
          items:
            - description: Board XO source
            - description: Board XO active only source
            - description: LPASS_AON_CC_MAIN_RCG_CLK_SRC

        clock-names:
          items:
            - const: bi_tcxo
            - const: bi_tcxo_ao
            - const: iface

        reg:
          maxItems: 1
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sc7280-lpasshm
              - qcom,sc7280-lpasscorecc

    then:
      properties:
        clocks:
          items:
            - description: Board XO source

        clock-names:
          items:
            - const: bi_tcxo

        reg:
          maxItems: 1
examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
    #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
    lpass_audiocc: clock-controller@3300000 {
      compatible = "qcom,sc7280-lpassaudiocc";
      reg = <0x3300000 0x30000>,
            <0x32a9000 0x1000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
      clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
      power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
      #clock-cells = <1>;
      #power-domain-cells = <1>;
      #reset-cells = <1>;
    };

  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
    #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
    lpass_hm: clock-controller@3c00000 {
      compatible = "qcom,sc7280-lpasshm";
      reg = <0x3c00000 0x28>;
      clocks = <&rpmhcc RPMH_CXO_CLK>;
      clock-names = "bi_tcxo";
      #clock-cells = <1>;
      #power-domain-cells = <1>;
    };

  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
    #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
    lpasscore: clock-controller@3900000 {
      compatible = "qcom,sc7280-lpasscorecc";
      reg = <0x3900000 0x50000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>;
      clock-names = "bi_tcxo";
      power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
      #clock-cells = <1>;
      #power-domain-cells = <1>;
    };

  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
    #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
    lpass_aon: clock-controller@3380000 {
      compatible = "qcom,sc7280-lpassaoncc";
      reg = <0x3380000 0x30000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
               <&lpasscore LPASS_CORE_CC_CORE_CLK>;
      clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
      qcom,adsp-pil-mode;
      #clock-cells = <1>;
      #power-domain-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sdm845-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Camera Clock & Reset Controller on SDM845

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |
  Qualcomm camera clock control module provides the clocks, resets and power
  domains on SDM845.

  See also:: include/dt-bindings/clock/qcom,camcc-sm845.h

properties:
  compatible:
    const: qcom,sdm845-camcc

  clocks:
    items:
      - description: Board XO source

  clock-names:
    items:
      - const: bi_tcxo

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@ad00000 {
      compatible = "qcom,sdm845-camcc";
      reg = <0x0ad00000 0x10000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>;
      clock-names = "bi_tcxo";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on SDM845

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on SDM845.

  See also:: include/dt-bindings/clock/qcom,dispcc-sdm845.h

properties:
  compatible:
    const: qcom,sdm845-dispcc

  # NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
  # The code had to use hardcoded mechanisms to find the input clocks.
  # New dts files should have these clocks.
  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 source from GCC
      - description: GPLL0 div source from GCC
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY0
      - description: Byte clock from DSI PHY1
      - description: Pixel clock from DSI PHY1
      - description: Link clock from DP PHY
      - description: VCO DIV clock from DP PHY

  clock-names:
    items:
      - const: bi_tcxo
      - const: gcc_disp_gpll0_clk_src
      - const: gcc_disp_gpll0_div_clk_src
      - const: dsi0_phy_pll_out_byteclk
      - const: dsi0_phy_pll_out_dsiclk
      - const: dsi1_phy_pll_out_byteclk
      - const: dsi1_phy_pll_out_dsiclk
      - const: dp_link_clk_divsel_ten
      - const: dp_vco_divided_clk_src_mux

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@af00000 {
      compatible = "qcom,sdm845-dispcc";
      reg = <0x0af00000 0x10000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&gcc GCC_DISP_GPLL0_CLK_SRC>,
               <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
               <&dsi0_phy 0>,
               <&dsi0_phy 1>,
               <&dsi1_phy 0>,
               <&dsi1_phy 1>,
               <&dp_phy 0>,
               <&dp_phy 1>;
      clock-names = "bi_tcxo",
                    "gcc_disp_gpll0_clk_src",
                    "gcc_disp_gpll0_div_clk_src",
                    "dsi0_phy_pll_out_byteclk",
                    "dsi0_phy_pll_out_dsiclk",
                    "dsi1_phy_pll_out_byteclk",
                    "dsi1_phy_pll_out_dsiclk",
                    "dp_link_clk_divsel_ten",
                    "dp_vco_divided_clk_src_mux";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sdm845-lpasscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SDM845 LPASS Clock Controller

maintainers:
  - Bjorn Andersson <andersson@kernel.org>

description: |
  Qualcomm SDM845 LPASS (Low Power Audio SubSystem) Clock Controller.

  See also:: include/dt-bindings/clock/qcom,lpass-sdm845.h

properties:
  compatible:
    const: qcom,sdm845-lpasscc

  '#clock-cells':
    const: 1

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: cc
      - const: qdsp6ss

required:
  - compatible
  - '#clock-cells'
  - reg
  - reg-names

additionalProperties: false

examples:
  - |
    clock-controller@17014000 {
        compatible = "qcom,sdm845-lpasscc";
        reg = <0x17014000 0x1f004>, <0x17300000 0x200>;
        reg-names = "cc", "qdsp6ss";
        #clock-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock Controller for SM6115

maintainers:
  - Bjorn Andersson <andersson@kernel.org>

description: |
  Qualcomm display clock control module provides the clocks and power domains
  on SM6115.

  See also:: include/dt-bindings/clock/qcom,sm6115-dispcc.h

properties:
  compatible:
    enum:
      - qcom,sm6115-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: Board sleep clock
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY0
      - description: GPLL0 DISP DIV clock from GCC

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmcc.h>
    #include <dt-bindings/clock/qcom,gcc-sm6115.h>
    clock-controller@5f00000 {
      compatible = "qcom,sm6115-dispcc";
      reg = <0x5f00000 0x20000>;
      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
               <&sleep_clk>,
               <&dsi0_phy 0>,
               <&dsi0_phy 1>,
               <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6375-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on SM6375

maintainers:
  - Konrad Dybcio <konrad.dybcio@linaro.org>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on SM6375.

  See also:: include/dt-bindings/clock/qcom,dispcc-sm6375.h

allOf:
  - $ref: qcom,gcc.yaml#

properties:
  compatible:
    const: qcom,sm6375-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: GPLL0 source from GCC
      - description: Byte clock from DSI PHY
      - description: Pixel clock from DSI PHY

required:
  - compatible
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,sm6375-gcc.h>
    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@5f00000 {
      compatible = "qcom,sm6375-dispcc";
      reg = <0x05f00000 0x20000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&gcc GCC_DISP_GPLL0_CLK_SRC>,
               <&dsi_phy 0>,
               <&dsi_phy 1>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SM6375

maintainers:
  - Konrad Dybcio <konrad.dybcio@somainline.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SM6375

  See also:: include/dt-bindings/clock/qcom,sm6375-gcc.h

allOf:
  - $ref: qcom,gcc.yaml#

properties:
  compatible:
    const: qcom,sm6375-gcc

  clocks:
    items:
      - description: Board XO source
      - description: Board XO Active-Only source
      - description: Sleep clock source

required:
  - compatible
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmcc.h>
    clock-controller@1400000 {
      compatible = "qcom,sm6375-gcc";
      reg = <0x01400000 0x1f0000>;
      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
               <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
               <&sleep_clk>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Camera Clock & Reset Controller on SM8450

maintainers:
  - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>

description: |
  Qualcomm camera clock control module provides the clocks, resets and power
  domains on SM8450.

  See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h

properties:
  compatible:
    const: qcom,sm8450-camcc

  clocks:
    items:
      - description: Camera AHB clock from GCC
      - description: Board XO source
      - description: Board active XO source
      - description: Sleep clock source

  power-domains:
    maxItems: 1
    description:
      A phandle and PM domain specifier for the MMCX power domain.

  required-opps:
    description:
      A phandle to an OPP node describing required MMCX performance point.

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - power-domains
  - required-opps
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    clock-controller@ade0000 {
      compatible = "qcom,sm8450-camcc";
      reg = <0xade0000 0x20000>;
      clocks = <&gcc GCC_CAMERA_AHB_CLK>,
               <&rpmhcc RPMH_CXO_CLK>,
               <&rpmhcc RPMH_CXO_CLK_A>,
               <&sleep_clk>;
      power-domains = <&rpmhpd SM8450_MMCX>;
      required-opps = <&rpmhpd_opp_low_svs>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller for SM8450

maintainers:
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on SM8450.

  See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h

properties:
  compatible:
    enum:
      - qcom,sm8450-dispcc

  clocks:
    minItems: 3
    items:
      - description: Board XO source
      - description: Board Always On XO source
      - description: Display's AHB clock
      - description: sleep clock
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY0
      - description: Byte clock from DSI PHY1
      - description: Pixel clock from DSI PHY1
      - description: Link clock from DP PHY0
      - description: VCO DIV clock from DP PHY0
      - description: Link clock from DP PHY1
      - description: VCO DIV clock from DP PHY1
      - description: Link clock from DP PHY2
      - description: VCO DIV clock from DP PHY2
      - description: Link clock from DP PHY3
      - description: VCO DIV clock from DP PHY3

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

  power-domains:
    description:
      A phandle and PM domain specifier for the MMCX power domain.
    maxItems: 1

  required-opps:
    description:
      A phandle to an OPP node describing required MMCX performance point.
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    clock-controller@af00000 {
      compatible = "qcom,sm8450-dispcc";
      reg = <0x0af00000 0x10000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&rpmhcc RPMH_CXO_CLK_A>,
               <&gcc GCC_DISP_AHB_CLK>,
               <&sleep_clk>,
               <&dsi0_phy 0>,
               <&dsi0_phy 1>,
               <&dsi1_phy 0>,
               <&dsi1_phy 1>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
      power-domains = <&rpmhpd SM8450_MMCX>;
      required-opps = <&rpmhpd_opp_low_svs>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller on SM8550

maintainers:
  - Bjorn Andersson <andersson@kernel.org>

description: |
  Qualcomm global clock control module provides the clocks, resets and power
  domains on SM8550

  See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h

properties:
  compatible:
    const: qcom,sm8550-gcc

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source
      - description: PCIE 0 Pipe clock source
      - description: PCIE 1 Pipe clock source
      - description: PCIE 1 Phy Auxiliary clock source
      - description: UFS Phy Rx symbol 0 clock source
      - description: UFS Phy Rx symbol 1 clock source
      - description: UFS Phy Tx symbol 0 clock source
      - description: USB3 Phy wrapper pipe clock source

required:
  - compatible
  - clocks

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,sm8550-gcc";
      reg = <0x00100000 0x001f4200>;
      clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
               <&pcie0_phy>,
               <&pcie1_phy>,
               <&pcie_1_phy_aux_clk>,
               <&ufs_mem_phy 0>,
               <&ufs_mem_phy 1>,
               <&ufs_mem_phy 2>,
               <&usb_1_qmpphy>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };

...


code:
Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)

clkdiv configures the clock frequency of a set of outputs on the PMIC.
These clocks are typically wired through alternate functions on
gpio pins.

=======================
Properties
=======================

- compatible
	Usage:      required
	Value type: <string>
	Definition: must be "qcom,spmi-clkdiv".

- reg
	Usage:      required
	Value type: <prop-encoded-array>
	Definition: base address of CLKDIV peripherals.

- qcom,num-clkdivs
	Usage:      required
	Value type: <u32>
	Definition: number of CLKDIV peripherals.

- clocks:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: reference to the xo clock.

- clock-names:
	Usage: required
	Value type: <stringlist>
	Definition: must be "xo".

- #clock-cells:
	Usage: required
	Value type: <u32>
	Definition: shall contain 1.

=======
Example
=======

pm8998_clk_divs: clock-controller@5b00 {
	compatible = "qcom,spmi-clkdiv";
	reg = <0x5b00>;
	#clock-cells = <1>;
	qcom,num-clkdivs = <3>;
	clocks = <&xo_board>;
	clock-names = "xo";

	assigned-clocks = <&pm8998_clk_divs 1>,
			  <&pm8998_clk_divs 2>,
			  <&pm8998_clk_divs 3>;
	assigned-clock-rates = <9600000>,
			       <9600000>,
			       <9600000>;
};


code:
Qualcomm Turing Clock & Reset Controller Binding
------------------------------------------------

Required properties :
- compatible: shall contain "qcom,qcs404-turingcc".
- reg: shall contain base register location and length.
- clocks: ahb clock for the TuringCC
- #clock-cells: from common clock binding, shall contain 1.
- #reset-cells: from common reset binding, shall contain 1.

Example:
	turingcc: clock-controller@800000 {
		compatible = "qcom,qcs404-turingcc";
		reg = <0x00800000 0x30000>;
		clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;

		#clock-cells = <1>;
		#reset-cells = <1>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Video Clock & Reset Controller

maintainers:
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm video clock control module provides the clocks, resets and power
  domains on Qualcomm SoCs.

  See also::
    include/dt-bindings/clock/qcom,videocc-sc7180.h
    include/dt-bindings/clock/qcom,videocc-sc7280.h
    include/dt-bindings/clock/qcom,videocc-sdm845.h
    include/dt-bindings/clock/qcom,videocc-sm8150.h
    include/dt-bindings/clock/qcom,videocc-sm8250.h

properties:
  compatible:
    enum:
      - qcom,sc7180-videocc
      - qcom,sc7280-videocc
      - qcom,sdm845-videocc
      - qcom,sm8150-videocc
      - qcom,sm8250-videocc

  clocks:
    items:
      - description: Board XO source

  clock-names:
    items:
      - const: bi_tcxo

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

  power-domains:
    description:
      A phandle and PM domain specifier for the MMCX power domain.
    maxItems: 1

  required-opps:
    description:
      A phandle to an OPP node describing required MMCX performance point.
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    clock-controller@ab00000 {
      compatible = "qcom,sdm845-videocc";
      reg = <0x0ab00000 0x10000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>;
      clock-names = "bi_tcxo";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
      power-domains = <&rpmhpd SM8250_MMCX>;
      required-opps = <&rpmhpd_opp_low_svs>;
    };
...


code:
* Clock Block on Freescale QorIQ Platforms

Freescale QorIQ chips take primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP blocks.
Please refer to the Reference Manual for details.

All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.

Chassis Version		Example Chips
---------------		-------------
1.0			p4080, p5020, p5040
2.0			t4240, b4860

1. Clock Block Binding

Required properties:
- compatible: Should contain a chip-specific clock block compatible
	string and (if applicable) may contain a chassis-version clock
	compatible string.

	Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
	* "fsl,p2041-clockgen"
	* "fsl,p3041-clockgen"
	* "fsl,p4080-clockgen"
	* "fsl,p5020-clockgen"
	* "fsl,p5040-clockgen"
	* "fsl,t1023-clockgen"
	* "fsl,t1024-clockgen"
	* "fsl,t1040-clockgen"
	* "fsl,t1042-clockgen"
	* "fsl,t2080-clockgen"
	* "fsl,t2081-clockgen"
	* "fsl,t4240-clockgen"
	* "fsl,b4420-clockgen"
	* "fsl,b4860-clockgen"
	* "fsl,ls1012a-clockgen"
	* "fsl,ls1021a-clockgen"
	* "fsl,ls1028a-clockgen"
	* "fsl,ls1043a-clockgen"
	* "fsl,ls1046a-clockgen"
	* "fsl,ls1088a-clockgen"
	* "fsl,ls2080a-clockgen"
	* "fsl,lx2160a-clockgen"
	Chassis-version clock strings include:
	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
- reg: Describes the address of the device's resources within the
	address space defined by its parent bus, and resource zero
	represents the clock register set

Optional properties:
- ranges: Allows valid translation between child's address space and
	parent's. Must be present if the device has sub-nodes.
- #address-cells: Specifies the number of cells used to represent
	physical base addresses.  Must be present if the device has
	sub-nodes and set to 1 if present
- #size-cells: Specifies the number of cells used to represent
	the size of an address. Must be present if the device has
	sub-nodes and set to 1 if present
- clock-frequency: Input system clock frequency (SYSCLK)
- clocks: If clock-frequency is not specified, sysclk may be provided
	as an input clock.  Either clock-frequency or clocks must be
	provided.
	A second input clock, called "coreclk", may be provided if
	core PLLs are based on a different input clock from the
	platform PLL.
- clock-names: Required if a coreclk is present.  Valid names are
	"sysclk" and "coreclk".

2. Clock Provider

The clockgen node should act as a clock provider, though in older device
trees the children of the clockgen node are the clock providers.

When the clockgen node is a clock provider, #clock-cells = <2>.
The first cell of the clock specifier is the clock type, and the
second cell is the clock index for the specified type.

	Type#	Name		Index Cell
	0	sysclk		must be 0
	1	cmux		index (n in CLKCnCSR)
	2	hwaccel		index (n in CLKCGnHWACSR)
	3	fman		0 for fm1, 1 for fm2
	4	platform pll	n=pll/(n+1). For example, when n=1,
				that means output_freq=PLL_freq/2.
	5	coreclk		must be 0

3. Example

	clockgen: global-utilities@e1000 {
		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
		clock-frequency = <133333333>;
		reg = <0xe1000 0x1000>;
		#clock-cells = <2>;
	};

	fman@400000 {
		...
		clocks = <&clockgen 3 0>;
		...
	};
}
4. Legacy Child Nodes

NOTE: These nodes are deprecated.  Kernels should continue to support
device trees with these nodes, but new device trees should not use them.

Most of the bindings are from the common clock binding[1].
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : Should include one of the following:
	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
		It takes parent's clock-frequency as its clock.
	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
		It takes parent's clock-frequency as its clock.
	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
- #clock-cells: From common clock binding. The number of cells in a
	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
	clock-specifier cell may take the following values:
	* 0 - equal to the PLL frequency
	* 1 - equal to the PLL frequency divided by 2
	* 2 - equal to the PLL frequency divided by 4

Recommended properties:
- clocks: Should be the phandle of input parent clock
- clock-names: From common clock binding, indicates the clock name
- clock-output-names: From common clock binding, indicates the names of
	output clocks
- reg: Should be the offset and length of clock block base address.
	The length should be 4.

Legacy Example:
/ {
	clockgen: global-utilities@e1000 {
		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
		ranges = <0x0 0xe1000 0x1000>;
		clock-frequency = <133333333>;
		reg = <0xe1000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		sysclk: sysclk {
			#clock-cells = <0>;
			compatible = "fsl,qoriq-sysclk-1.0";
			clock-output-names = "sysclk";
		};

		pll0: pll0@800 {
			#clock-cells = <1>;
			reg = <0x800 0x4>;
			compatible = "fsl,qoriq-core-pll-1.0";
			clocks = <&sysclk>;
			clock-output-names = "pll0", "pll0-div2";
		};

		pll1: pll1@820 {
			#clock-cells = <1>;
			reg = <0x820 0x4>;
			compatible = "fsl,qoriq-core-pll-1.0";
			clocks = <&sysclk>;
			clock-output-names = "pll1", "pll1-div2";
		};

		mux0: mux0@0 {
			#clock-cells = <0>;
			reg = <0x0 0x4>;
			compatible = "fsl,qoriq-core-mux-1.0";
			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
			clock-output-names = "cmux0";
		};

		mux1: mux1@20 {
			#clock-cells = <0>;
			reg = <0x20 0x4>;
			compatible = "fsl,qoriq-core-mux-1.0";
			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
			clock-output-names = "cmux1";
		};

		platform-pll: platform-pll@c00 {
			#clock-cells = <1>;
			reg = <0xc00 0x4>;
			compatible = "fsl,qoriq-platform-pll-1.0";
			clocks = <&sysclk>;
			clock-output-names = "platform-pll", "platform-pll-div2";
		};
	};
};

Example for legacy clock consumer:

/ {
	cpu0: PowerPC,e5500@0 {
		...
		clocks = <&mux0>;
		...
	};
};