code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 USB PHY

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 1

  compatible:
    enum:
      - allwinner,sun4i-a10-usb-phy
      - allwinner,sun7i-a20-usb-phy

  reg:
    items:
      - description: PHY Control registers
      - description: PHY PMU1 registers
      - description: PHY PMU2 registers

  reg-names:
    items:
      - const: phy_ctrl
      - const: pmu1
      - const: pmu2

  clocks:
    maxItems: 1
    description: USB PHY bus clock

  clock-names:
    const: usb_phy

  resets:
    items:
      - description: USB OTG reset
      - description: USB Host 1 Controller reset
      - description: USB Host 2 Controller reset

  reset-names:
    items:
      - const: usb0_reset
      - const: usb1_reset
      - const: usb2_reset

  usb0_id_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG ID pin

  usb0_vbus_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG VBUS detect pin

  usb0_vbus_power-supply:
    description: Power supply to detect the USB OTG VBUS

  usb0_vbus-supply:
    description: Regulator controlling USB OTG VBUS

  usb1_vbus-supply:
    description: Regulator controlling USB1 Host controller

  usb2_vbus-supply:
    description: Regulator controlling USB2 Host controller

required:
  - "#phy-cells"
  - compatible
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clock/sun4i-a10-ccu.h>
    #include <dt-bindings/reset/sun4i-a10-ccu.h>

    usbphy: phy@1c13400 {
        #phy-cells = <1>;
        compatible = "allwinner,sun4i-a10-usb-phy";
        reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
        reg-names = "phy_ctrl", "pmu1", "pmu2";
        clocks = <&ccu CLK_USB_PHY>;
        clock-names = "usb_phy";
        resets = <&ccu RST_USB_PHY0>,
                 <&ccu RST_USB_PHY1>,
                 <&ccu RST_USB_PHY2>;
        reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
        usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>;
        usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>;
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A64 USB PHY

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 1

  compatible:
    enum:
      - allwinner,sun20i-d1-usb-phy
      - allwinner,sun50i-a64-usb-phy

  reg:
    items:
      - description: PHY Control registers
      - description: PHY PMU0 registers
      - description: PHY PMU1 registers

  reg-names:
    items:
      - const: phy_ctrl
      - const: pmu0
      - const: pmu1

  clocks:
    items:
      - description: USB OTG PHY bus clock
      - description: USB Host 0 PHY bus clock

  clock-names:
    items:
      - const: usb0_phy
      - const: usb1_phy

  resets:
    items:
      - description: USB OTG reset
      - description: USB Host 1 Controller reset

  reset-names:
    items:
      - const: usb0_reset
      - const: usb1_reset

  usb0_id_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG ID pin

  usb0_vbus_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG VBUS detect pin

  usb0_vbus_power-supply:
    description: Power supply to detect the USB OTG VBUS

  usb0_vbus-supply:
    description: Regulator controlling USB OTG VBUS

  usb1_vbus-supply:
    description: Regulator controlling USB1 Host controller

required:
  - "#phy-cells"
  - compatible
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clock/sun50i-a64-ccu.h>
    #include <dt-bindings/reset/sun50i-a64-ccu.h>

    phy@1c19400 {
        #phy-cells = <1>;
        compatible = "allwinner,sun50i-a64-usb-phy";
        reg = <0x01c19400 0x14>,
              <0x01c1a800 0x4>,
              <0x01c1b800 0x4>;
        reg-names = "phy_ctrl",
                    "pmu0",
                    "pmu1";
        clocks = <&ccu CLK_USB_PHY0>,
                 <&ccu CLK_USB_PHY1>;
        clock-names = "usb0_phy",
                      "usb1_phy";
        resets = <&ccu RST_USB_PHY0>,
                 <&ccu RST_USB_PHY1>;
        reset-names = "usb0_reset",
                      "usb1_reset";
        usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_drivevbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner H6 USB PHY

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 1

  compatible:
    const: allwinner,sun50i-h6-usb-phy

  reg:
    items:
      - description: PHY Control registers
      - description: PHY PMU0 registers
      - description: PHY PMU3 registers

  reg-names:
    items:
      - const: phy_ctrl
      - const: pmu0
      - const: pmu3

  clocks:
    items:
      - description: USB OTG PHY bus clock
      - description: USB Host PHY bus clock

  clock-names:
    items:
      - const: usb0_phy
      - const: usb3_phy

  resets:
    items:
      - description: USB OTG reset
      - description: USB Host Controller reset

  reset-names:
    items:
      - const: usb0_reset
      - const: usb3_reset

  usb0_id_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG ID pin

  usb0_vbus_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG VBUS detect pin

  usb0_vbus_power-supply:
    description: Power supply to detect the USB OTG VBUS

  usb0_vbus-supply:
    description: Regulator controlling USB OTG VBUS

  usb3_vbus-supply:
    description: Regulator controlling USB3 Host controller

required:
  - "#phy-cells"
  - compatible
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clock/sun50i-h6-ccu.h>
    #include <dt-bindings/reset/sun50i-h6-ccu.h>

    phy@5100400 {
        #phy-cells = <1>;
        compatible = "allwinner,sun50i-h6-usb-phy";
        reg = <0x05100400 0x24>,
              <0x05101800 0x4>,
              <0x05311800 0x4>;
        reg-names = "phy_ctrl",
                    "pmu0",
                    "pmu3";
        clocks = <&ccu CLK_USB_PHY0>,
                 <&ccu CLK_USB_PHY3>;
        clock-names = "usb0_phy",
                      "usb3_phy";
        resets = <&ccu RST_USB_PHY0>,
                 <&ccu RST_USB_PHY3>;
        reset-names = "usb0_reset",
                      "usb3_reset";
        usb0_id_det-gpios = <&pio 2 6 GPIO_ACTIVE_HIGH>; /* PC6 */
        usb0_vbus-supply = <&reg_vcc5v>;
        usb3_vbus-supply = <&reg_vcc5v>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 Ondrej Jirman <megous@megous.com>
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb3-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Allwinner H6 USB3 PHY

maintainers:
  - Ondrej Jirman <megous@megous.com>

properties:
  compatible:
    enum:
      - allwinner,sun50i-h6-usb3-phy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - clocks
  - resets
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/sun50i-h6-ccu.h>
    #include <dt-bindings/reset/sun50i-h6-ccu.h>
    phy@5210000 {
          compatible = "allwinner,sun50i-h6-usb3-phy";
          reg = <0x5210000 0x10000>;
          clocks = <&ccu CLK_USB_PHY1>;
          resets = <&ccu RST_USB_PHY1>;
          #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun5i-a13-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A13 USB PHY

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 1

  compatible:
    const: allwinner,sun5i-a13-usb-phy

  reg:
    items:
      - description: PHY Control registers
      - description: PHY PMU1 registers

  reg-names:
    items:
      - const: phy_ctrl
      - const: pmu1

  clocks:
    maxItems: 1
    description: USB OTG PHY bus clock

  clock-names:
    const: usb_phy

  resets:
    items:
      - description: USB OTG reset
      - description: USB Host 1 Controller reset

  reset-names:
    items:
      - const: usb0_reset
      - const: usb1_reset

  usb0_id_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG ID pin

  usb0_vbus_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG VBUS detect pin

  usb0_vbus_power-supply:
    description: Power supply to detect the USB OTG VBUS

  usb0_vbus-supply:
    description: Regulator controlling USB OTG VBUS

  usb1_vbus-supply:
    description: Regulator controlling USB1 Host controller

required:
  - "#phy-cells"
  - compatible
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clock/sun5i-ccu.h>
    #include <dt-bindings/reset/sun5i-ccu.h>

    phy@1c13400 {
        #phy-cells = <1>;
        compatible = "allwinner,sun5i-a13-usb-phy";
        reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
        reg-names = "phy_ctrl", "pmu1";
        clocks = <&ccu CLK_USB_PHY0>;
        clock-names = "usb_phy";
        resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
        reset-names = "usb0_reset", "usb1_reset";
        usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
        usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 MIPI D-PHY Controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 0

  compatible:
    oneOf:
      - const: allwinner,sun6i-a31-mipi-dphy
      - items:
          - const: allwinner,sun50i-a64-mipi-dphy
          - const: allwinner,sun6i-a31-mipi-dphy

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Bus Clock
      - description: Module Clock

  clock-names:
    items:
      - const: bus
      - const: mod

  resets:
    maxItems: 1

  allwinner,direction:
    $ref: '/schemas/types.yaml#/definitions/string'
    description: |
      Direction of the D-PHY:
      - "rx" for receiving (e.g. when used with MIPI CSI-2);
      - "tx" for transmitting (e.g. when used with MIPI DSI).

    enum:
      - tx
      - rx
    default: tx

required:
  - "#phy-cells"
  - compatible
  - reg
  - clocks
  - clock-names
  - resets

additionalProperties: false

examples:
  - |
    dphy0: d-phy@1ca1000 {
        compatible = "allwinner,sun6i-a31-mipi-dphy";
        reg = <0x01ca1000 0x1000>;
        clocks = <&ccu 23>, <&ccu 97>;
        clock-names = "bus", "mod";
        resets = <&ccu 4>;
        #phy-cells = <0>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 USB PHY

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 1

  compatible:
    const: allwinner,sun6i-a31-usb-phy

  reg:
    items:
      - description: PHY Control registers
      - description: PHY PMU1 registers
      - description: PHY PMU2 registers

  reg-names:
    items:
      - const: phy_ctrl
      - const: pmu1
      - const: pmu2

  clocks:
    items:
      - description: USB OTG PHY bus clock
      - description: USB Host 0 PHY bus clock
      - description: USB Host 1 PHY bus clock

  clock-names:
    items:
      - const: usb0_phy
      - const: usb1_phy
      - const: usb2_phy

  resets:
    items:
      - description: USB OTG reset
      - description: USB Host 1 Controller reset
      - description: USB Host 2 Controller reset

  reset-names:
    items:
      - const: usb0_reset
      - const: usb1_reset
      - const: usb2_reset

  usb0_id_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG ID pin

  usb0_vbus_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG VBUS detect pin

  usb0_vbus_power-supply:
    description: Power supply to detect the USB OTG VBUS

  usb0_vbus-supply:
    description: Regulator controlling USB OTG VBUS

  usb1_vbus-supply:
    description: Regulator controlling USB1 Host controller

  usb2_vbus-supply:
    description: Regulator controlling USB2 Host controller

required:
  - "#phy-cells"
  - compatible
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clock/sun6i-a31-ccu.h>
    #include <dt-bindings/reset/sun6i-a31-ccu.h>

    phy@1c19400 {
        #phy-cells = <1>;
        compatible = "allwinner,sun6i-a31-usb-phy";
        reg = <0x01c19400 0x10>,
              <0x01c1a800 0x4>,
              <0x01c1b800 0x4>;
        reg-names = "phy_ctrl",
                    "pmu1",
                    "pmu2";
        clocks = <&ccu CLK_USB_PHY0>,
                 <&ccu CLK_USB_PHY1>,
                 <&ccu CLK_USB_PHY2>;
        clock-names = "usb0_phy",
                      "usb1_phy",
                      "usb2_phy";
        resets = <&ccu RST_USB_PHY0>,
                 <&ccu RST_USB_PHY1>,
                 <&ccu RST_USB_PHY2>;
        reset-names = "usb0_reset",
                      "usb1_reset",
                      "usb2_reset";
        usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
        usb0_vbus_det-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_drivevbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun8i-a23-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A23 USB PHY

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 1

  compatible:
    enum:
      - allwinner,sun8i-a23-usb-phy
      - allwinner,sun8i-a33-usb-phy

  reg:
    items:
      - description: PHY Control registers
      - description: PHY PMU1 registers

  reg-names:
    items:
      - const: phy_ctrl
      - const: pmu1

  clocks:
    items:
      - description: USB OTG PHY bus clock
      - description: USB Host 0 PHY bus clock

  clock-names:
    items:
      - const: usb0_phy
      - const: usb1_phy

  resets:
    items:
      - description: USB OTG reset
      - description: USB Host 1 Controller reset

  reset-names:
    items:
      - const: usb0_reset
      - const: usb1_reset

  usb0_id_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG ID pin

  usb0_vbus_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG VBUS detect pin

  usb0_vbus_power-supply:
    description: Power supply to detect the USB OTG VBUS

  usb0_vbus-supply:
    description: Regulator controlling USB OTG VBUS

  usb1_vbus-supply:
    description: Regulator controlling USB1 Host controller

required:
  - "#phy-cells"
  - compatible
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
    #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>

    phy@1c19400 {
        #phy-cells = <1>;
        compatible = "allwinner,sun8i-a23-usb-phy";
        reg = <0x01c19400 0x10>, <0x01c1a800 0x4>;
        reg-names = "phy_ctrl", "pmu1";
        clocks = <&ccu CLK_USB_PHY0>,
                 <&ccu CLK_USB_PHY1>;
        clock-names = "usb0_phy",
                      "usb1_phy";
        resets = <&ccu RST_USB_PHY0>,
                 <&ccu RST_USB_PHY1>;
        reset-names = "usb0_reset",
                      "usb1_reset";
        usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_drivevbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A83t USB PHY

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 1

  compatible:
    const: allwinner,sun8i-a83t-usb-phy

  reg:
    items:
      - description: PHY Control registers
      - description: PHY PMU1 registers
      - description: PHY PMU2 registers

  reg-names:
    items:
      - const: phy_ctrl
      - const: pmu1
      - const: pmu2

  clocks:
    items:
      - description: USB OTG PHY bus clock
      - description: USB Host 0 PHY bus clock
      - description: USB Host 1 PHY bus clock
      - description: USB HSIC 12MHz clock

  clock-names:
    items:
      - const: usb0_phy
      - const: usb1_phy
      - const: usb2_phy
      - const: usb2_hsic_12M

  resets:
    items:
      - description: USB OTG reset
      - description: USB Host 1 Controller reset
      - description: USB Host 2 Controller reset

  reset-names:
    items:
      - const: usb0_reset
      - const: usb1_reset
      - const: usb2_reset

  usb0_id_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG ID pin

  usb0_vbus_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG VBUS detect pin

  usb0_vbus_power-supply:
    description: Power supply to detect the USB OTG VBUS

  usb0_vbus-supply:
    description: Regulator controlling USB OTG VBUS

  usb1_vbus-supply:
    description: Regulator controlling USB1 Host controller

  usb2_vbus-supply:
    description: Regulator controlling USB2 Host controller

required:
  - "#phy-cells"
  - compatible
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clock/sun8i-a83t-ccu.h>
    #include <dt-bindings/reset/sun8i-a83t-ccu.h>

    phy@1c19400 {
        #phy-cells = <1>;
        compatible = "allwinner,sun8i-a83t-usb-phy";
        reg = <0x01c19400 0x10>,
              <0x01c1a800 0x14>,
              <0x01c1b800 0x14>;
        reg-names = "phy_ctrl",
                    "pmu1",
                    "pmu2";
        clocks = <&ccu CLK_USB_PHY0>,
                 <&ccu CLK_USB_PHY1>,
                 <&ccu CLK_USB_HSIC>,
                 <&ccu CLK_USB_HSIC_12M>;
        clock-names = "usb0_phy",
                      "usb1_phy",
                      "usb2_phy",
                      "usb2_hsic_12M";
        resets = <&ccu RST_USB_PHY0>,
                 <&ccu RST_USB_PHY1>,
                 <&ccu RST_USB_HSIC>;
        reset-names = "usb0_reset",
                      "usb1_reset",
                      "usb2_reset";
        usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
        usb0_vbus_power-supply = <&usb_power_supply>;
        usb0_vbus-supply = <&reg_drivevbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner H3 USB PHY

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 1

  compatible:
    enum:
      - allwinner,sun8i-h3-usb-phy
      - allwinner,sun50i-h616-usb-phy

  reg:
    items:
      - description: PHY Control registers
      - description: PHY PMU0 registers
      - description: PHY PMU1 registers
      - description: PHY PMU2 registers
      - description: PHY PMU3 registers

  reg-names:
    items:
      - const: phy_ctrl
      - const: pmu0
      - const: pmu1
      - const: pmu2
      - const: pmu3

  clocks:
    items:
      - description: USB OTG PHY bus clock
      - description: USB Host 0 PHY bus clock
      - description: USB Host 1 PHY bus clock
      - description: USB Host 2 PHY bus clock

  clock-names:
    items:
      - const: usb0_phy
      - const: usb1_phy
      - const: usb2_phy
      - const: usb3_phy

  resets:
    items:
      - description: USB OTG reset
      - description: USB Host 1 Controller reset
      - description: USB Host 2 Controller reset
      - description: USB Host 3 Controller reset

  reset-names:
    items:
      - const: usb0_reset
      - const: usb1_reset
      - const: usb2_reset
      - const: usb3_reset

  usb0_id_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG ID pin

  usb0_vbus_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG VBUS detect pin

  usb0_vbus_power-supply:
    description: Power supply to detect the USB OTG VBUS

  usb0_vbus-supply:
    description: Regulator controlling USB OTG VBUS

  usb1_vbus-supply:
    description: Regulator controlling USB1 Host controller

  usb2_vbus-supply:
    description: Regulator controlling USB2 Host controller

  usb3_vbus-supply:
    description: Regulator controlling USB3 Host controller

required:
  - "#phy-cells"
  - compatible
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clock/sun8i-h3-ccu.h>
    #include <dt-bindings/reset/sun8i-h3-ccu.h>

    phy@1c19400 {
        #phy-cells = <1>;
        compatible = "allwinner,sun8i-h3-usb-phy";
        reg = <0x01c19400 0x2c>,
              <0x01c1a800 0x4>,
              <0x01c1b800 0x4>,
              <0x01c1c800 0x4>,
              <0x01c1d800 0x4>;
        reg-names = "phy_ctrl",
                    "pmu0",
                    "pmu1",
                    "pmu2",
                    "pmu3";
        clocks = <&ccu CLK_USB_PHY0>,
                 <&ccu CLK_USB_PHY1>,
                 <&ccu CLK_USB_PHY2>,
                 <&ccu CLK_USB_PHY3>;
        clock-names = "usb0_phy",
                      "usb1_phy",
                      "usb2_phy",
                      "usb3_phy";
        resets = <&ccu RST_USB_PHY0>,
                 <&ccu RST_USB_PHY1>,
                 <&ccu RST_USB_PHY2>,
                 <&ccu RST_USB_PHY3>;
        reset-names = "usb0_reset",
                      "usb1_reset",
                      "usb2_reset",
                      "usb3_reset";
        usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
        usb0_vbus-supply = <&reg_usb0_vbus>;
        usb1_vbus-supply = <&reg_usb1_vbus>;
        usb2_vbus-supply = <&reg_usb2_vbus>;
        usb3_vbus-supply = <&reg_usb3_vbus>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun8i-r40-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner R40 USB PHY

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 1

  compatible:
    const: allwinner,sun8i-r40-usb-phy

  reg:
    items:
      - description: PHY Control registers
      - description: PHY PMU0 registers
      - description: PHY PMU1 registers
      - description: PHY PMU2 registers

  reg-names:
    items:
      - const: phy_ctrl
      - const: pmu0
      - const: pmu1
      - const: pmu2

  clocks:
    items:
      - description: USB OTG PHY bus clock
      - description: USB Host 0 PHY bus clock
      - description: USB Host 1 PHY bus clock

  clock-names:
    items:
      - const: usb0_phy
      - const: usb1_phy
      - const: usb2_phy

  resets:
    items:
      - description: USB OTG reset
      - description: USB Host 1 Controller reset
      - description: USB Host 2 Controller reset

  reset-names:
    items:
      - const: usb0_reset
      - const: usb1_reset
      - const: usb2_reset

  usb0_id_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG ID pin

  usb0_vbus_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG VBUS detect pin

  usb0_vbus_power-supply:
    description: Power supply to detect the USB OTG VBUS

  usb0_vbus-supply:
    description: Regulator controlling USB OTG VBUS

  usb1_vbus-supply:
    description: Regulator controlling USB1 Host controller

  usb2_vbus-supply:
    description: Regulator controlling USB2 Host controller

required:
  - "#phy-cells"
  - compatible
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clock/sun8i-r40-ccu.h>
    #include <dt-bindings/reset/sun8i-r40-ccu.h>

    phy@1c13400 {
        #phy-cells = <1>;
        compatible = "allwinner,sun8i-r40-usb-phy";
        reg = <0x01c13400 0x14>,
              <0x01c14800 0x4>,
              <0x01c19800 0x4>,
              <0x01c1c800 0x4>;
        reg-names = "phy_ctrl",
                    "pmu0",
                    "pmu1",
                    "pmu2";
        clocks = <&ccu CLK_USB_PHY0>,
                 <&ccu CLK_USB_PHY1>,
                 <&ccu CLK_USB_PHY2>;
        clock-names = "usb0_phy",
                      "usb1_phy",
                      "usb2_phy";
        resets = <&ccu RST_USB_PHY0>,
                 <&ccu RST_USB_PHY1>,
                 <&ccu RST_USB_PHY2>;
        reset-names = "usb0_reset",
                      "usb1_reset",
                      "usb2_reset";
        usb1_vbus-supply = <&reg_vcc5v0>;
        usb2_vbus-supply = <&reg_vcc5v0>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun8i-v3s-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner V3s USB PHY

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 1

  compatible:
    const: allwinner,sun8i-v3s-usb-phy

  reg:
    items:
      - description: PHY Control registers
      - description: PHY PMU0 registers

  reg-names:
    items:
      - const: phy_ctrl
      - const: pmu0

  clocks:
    maxItems: 1
    description: USB OTG PHY bus clock

  clock-names:
    const: usb0_phy

  resets:
    maxItems: 1
    description: USB OTG reset

  reset-names:
    const: usb0_reset

  usb0_id_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG ID pin

  usb0_vbus_det-gpios:
    maxItems: 1
    description: GPIO to the USB OTG VBUS detect pin

  usb0_vbus_power-supply:
    description: Power supply to detect the USB OTG VBUS

  usb0_vbus-supply:
    description: Regulator controlling USB OTG VBUS

required:
  - "#phy-cells"
  - compatible
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clock/sun8i-v3s-ccu.h>
    #include <dt-bindings/reset/sun8i-v3s-ccu.h>

    phy@1c19400 {
        #phy-cells = <1>;
        compatible = "allwinner,sun8i-v3s-usb-phy";
        reg = <0x01c19400 0x2c>,
              <0x01c1a800 0x4>;
        reg-names = "phy_ctrl",
                    "pmu0";
        clocks = <&ccu CLK_USB_PHY0>;
        clock-names = "usb0_phy";
        resets = <&ccu RST_USB_PHY0>;
        reset-names = "usb0_reset";
        usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A80 USB PHY

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

properties:
  "#phy-cells":
    const: 0

  compatible:
    const: allwinner,sun9i-a80-usb-phy

  reg:
    maxItems: 1

  clocks:
    anyOf:
      - maxItems: 1
        description: Main PHY Clock

      - items:
          - description: Main PHY clock
          - description: HSIC 12MHz clock
          - description: HSIC 480MHz clock

  clock-names:
    oneOf:
      - const: phy

      - items:
          - const: phy
          - const: hsic_12M
          - const: hsic_480M

  resets:
    minItems: 1
    items:
      - description: Normal USB PHY reset
      - description: HSIC Reset

  reset-names:
    minItems: 1
    items:
      - const: phy
      - const: hsic

  phy_type:
    const: hsic
    description:
      When absent, the PHY type will be assumed to be normal USB.

  phy-supply:
    description:
      Regulator that powers VBUS

required:
  - "#phy-cells"
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names

additionalProperties: false

if:
  properties:
    phy_type:
      const: hsic

  required:
    - phy_type

then:
  properties:
    clocks:
      maxItems: 3

    clock-names:
      maxItems: 3

    resets:
      maxItems: 2

    reset-names:
      maxItems: 2

examples:
  - |
    #include <dt-bindings/clock/sun9i-a80-usb.h>
    #include <dt-bindings/reset/sun9i-a80-usb.h>

    usbphy1: phy@a00800 {
        compatible = "allwinner,sun9i-a80-usb-phy";
        reg = <0x00a00800 0x4>;
        clocks = <&usb_clocks CLK_USB0_PHY>;
        clock-names = "phy";
        resets = <&usb_clocks RST_USB0_PHY>;
        reset-names = "phy";
        phy-supply = <&reg_usb1_vbus>;
        #phy-cells = <0>;
    };

  - |
    #include <dt-bindings/clock/sun9i-a80-usb.h>
    #include <dt-bindings/reset/sun9i-a80-usb.h>

    usbphy3: phy@a02800 {
        compatible = "allwinner,sun9i-a80-usb-phy";
        reg = <0x00a02800 0x4>;
        clocks = <&usb_clocks CLK_USB2_PHY>,
                 <&usb_clocks CLK_USB_HSIC>,
                 <&usb_clocks CLK_USB2_HSIC>;
        clock-names = "phy",
                      "hsic_12M",
                      "hsic_480M";
        resets = <&usb_clocks RST_USB2_PHY>,
                 <&usb_clocks RST_USB2_HSIC>;
        reset-names = "phy",
                      "hsic";
        phy_type = "hsic";
        phy-supply = <&reg_usb3_vbus>;
        #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,axg-mipi-dphy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic AXG MIPI D-PHY

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

properties:
  compatible:
    enum:
      - amlogic,axg-mipi-dphy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: pclk

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: phy

  "#phy-cells":
    const: 0

  phys:
    maxItems: 1

  phy-names:
    items:
      - const: analog

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - phys
  - phy-names
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    phy@ff640000 {
            compatible = "amlogic,axg-mipi-dphy";
            reg = <0xff640000 0x100>;
            clocks = <&clk_mipi_dsi_phy>;
            clock-names = "pclk";
            resets = <&reset_phy>;
            reset-names = "phy";
            phys = <&mipi_pcie_analog_dphy>;
            phy-names = "analog";
            #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic G12A MIPI analog PHY

maintainers:
  - Neil Armstrong <narmstrong@baylibre.com>

properties:
  compatible:
    const: amlogic,g12a-mipi-dphy-analog

  "#phy-cells":
    const: 0

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    phy@0 {
          compatible = "amlogic,g12a-mipi-dphy-analog";
          reg = <0x0 0xc>;
          #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic AXG shared MIPI/PCIE analog PHY

maintainers:
  - Remi Pommarel <repk@triplefau.lt>

description: |+
  The Everything-Else Power Domains node should be the child of a syscon
  node with the required property:

  - compatible: Should be the following:
                "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"

  Refer to the bindings described in
  Documentation/devicetree/bindings/mfd/syscon.yaml

properties:
  compatible:
    const: amlogic,axg-mipi-pcie-analog-phy

  "#phy-cells":
    const: 0

required:
  - compatible
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    mpphy: phy {
          compatible = "amlogic,axg-mipi-pcie-analog-phy";
          #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-pcie.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic AXG PCIE PHY

maintainers:
  - Remi Pommarel <repk@triplefau.lt>

properties:
  compatible:
    const: amlogic,axg-pcie-phy

  reg:
    maxItems: 1

  resets:
    maxItems: 1

  phys:
    maxItems: 1

  phy-names:
    const: analog

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - phys
  - phy-names
  - resets
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
    #include <dt-bindings/phy/phy.h>
    pcie_phy: pcie-phy@ff644000 {
          compatible = "amlogic,axg-pcie-phy";
          reg = <0xff644000 0x1c>;
          resets = <&reset RESET_PCIE_PHY>;
          phys = <&mipi_analog_phy PHY_TYPE_PCIE>;
          phy-names = "analog";
          #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb2-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic G12A USB2 PHY

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

properties:
  compatible:
    enum:
      - amlogic,meson-g12a-usb2-phy
      - amlogic,meson-a1-usb2-phy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: xtal

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: phy

  "#phy-cells":
    const: 0

  phy-supply:
    description:
      Phandle to a regulator that provides power to the PHY. This
      regulator will be managed during the PHY power on/off sequence.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - "#phy-cells"

if:
  properties:
    compatible:
      enum:
        - amlogic,meson-a1-usb-ctrl

then:
  properties:
    power-domains:
      maxItems: 1
  required:
    - power-domains

additionalProperties: false

examples:
  - |
    phy@36000 {
          compatible = "amlogic,meson-g12a-usb2-phy";
          reg = <0x36000 0x2000>;
          clocks = <&xtal>;
          clock-names = "xtal";
          resets = <&phy_reset>;
          reset-names = "phy";
          #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic G12A USB3 + PCIE Combo PHY

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

properties:
  compatible:
    enum:
      - amlogic,meson-g12a-usb3-pcie-phy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: ref_clk

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: phy

  "#phy-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    phy@46000 {
          compatible = "amlogic,meson-g12a-usb3-pcie-phy";
          reg = <0x46000 0x2000>;
          clocks = <&ref_clk>;
          clock-names = "ref_clk";
          resets = <&phy_reset>;
          reset-names = "phy";
          #phy-cells = <1>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY

maintainers:
  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>

description: |+
  The HDMI TX PHY node should be the child of a syscon node with the
  required property:

  compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"

  Refer to the bindings described in
  Documentation/devicetree/bindings/mfd/syscon.yaml

properties:
  $nodename:
    pattern: "^hdmi-phy@[0-9a-f]+$"

  compatible:
    oneOf:
      - items:
          - enum:
              - amlogic,meson8b-hdmi-tx-phy
              - amlogic,meson8m2-hdmi-tx-phy
          - const: amlogic,meson8-hdmi-tx-phy
      - const: amlogic,meson8-hdmi-tx-phy

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    description:
      HDMI TMDS clock

  "#phy-cells":
    const: 0

required:
  - compatible
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    hdmi-phy@3a0 {
      compatible = "amlogic,meson8-hdmi-tx-phy";
      reg = <0x3a0 0xc>;
      clocks = <&tmds_clock>;
      #phy-cells = <0>;
    };
  - |
    hdmi-phy@3a0 {
      compatible = "amlogic,meson8b-hdmi-tx-phy", "amlogic,meson8-hdmi-tx-phy";
      reg = <0x3a0 0xc>;
      clocks = <&tmds_clock>;
      #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY

maintainers:
  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - amlogic,meson8-usb2-phy
              - amlogic,meson8b-usb2-phy
              - amlogic,meson8m2-usb2-phy
          - const: amlogic,meson-mx-usb2-phy
      - const: amlogic,meson-gxbb-usb2-phy

  reg:
    maxItems: 1

  clocks:
    minItems: 2

  clock-names:
    items:
      - const: usb_general
      - const: usb

  resets:
    minItems: 1

  "#phy-cells":
    const: 0

  phy-supply:
    description:
      Phandle to a regulator that provides power to the PHY. This
      regulator will be managed during the PHY power on/off sequence.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    usb-phy@c0000000 {
      compatible = "amlogic,meson-gxbb-usb2-phy";
      reg = <0xc0000000 0x20>;
      resets = <&reset_usb_phy>;
      clocks = <&clk_usb_general>, <&reset_usb>;
      clock-names = "usb_general", "usb";
      phy-supply = <&usb_vbus>;
      #phy-cells = <0>;
    };


code:
* APM X-Gene 15Gbps Multi-purpose PHY nodes

PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
PHY (pair of lanes) has its own node.

Required properties:
- compatible		: Shall be "apm,xgene-phy".
- reg			: PHY memory resource is the SDS PHY access resource.
- #phy-cells		: Shall be 1 as it expects one argument for setting
			  the mode of the PHY. Possible values are 0 (SATA),
			  1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).

Optional properties:
- status		: Shall be "ok" if enabled or "disabled" if disabled.
			  Default is "ok".
- clocks		: Reference to the clock entry.
- apm,tx-eye-tuning	: Manual control to fine tune the capture of the serial
			  bit lines from the automatic calibrated position.
			  Two set of 3-tuple setting for each (up to 3)
			  supported link speed on the host. Range from 0 to
			  127 in unit of one bit period. Default is 10.
- apm,tx-eye-direction	: Eye tuning manual control direction. 0 means sample
			  data earlier than the nominal sampling point. 1 means
			  sample data later than the nominal sampling point.
			  Two set of 3-tuple setting for each (up to 3)
			  supported link speed on the host. Default is 0.
- apm,tx-boost-gain	: Frequency boost AC (LSB 3-bit) and DC (2-bit)
			  gain control. Two set of 3-tuple setting for each
			  (up to 3) supported link speed on the host. Range is
			  between 0 to 31 in unit of dB. Default is 3.
- apm,tx-amplitude	: Amplitude control. Two set of 3-tuple setting for
			  each (up to 3) supported link speed on the host.
			  Range is between 0 to 199500 in unit of uV.
			  Default is 199500 uV.
- apm,tx-pre-cursor1	: 1st pre-cursor emphasis taps control. Two set of
			  3-tuple setting for each (up to 3) supported link
			  speed on the host. Range is 0 to 273000 in unit of
			  uV. Default is 0.
- apm,tx-pre-cursor2	: 2st pre-cursor emphasis taps control. Two set of
			  3-tuple setting for each (up to 3) supported link
			  speed on the host. Range is 0 to 127400 in unit uV.
			  Default is 0x0.
- apm,tx-post-cursor	: Post-cursor emphasis taps control. Two set of
			  3-tuple setting for Gen1, Gen2, and Gen3. Range is
			  between 0 to 0x1f in unit of 18.2mV. Default is 0xf.
- apm,tx-speed		: Tx operating speed. One set of 3-tuple for each
			  supported link speed on the host.
			   0 = 1-2Gbps
			   1 = 2-4Gbps (1st tuple default)
			   2 = 4-8Gbps
			   3 = 8-15Gbps (2nd tuple default)
			   4 = 2.5-4Gbps
			   5 = 4-5Gbps
			   6 = 5-6Gbps
			   7 = 6-16Gbps (3rd tuple default)

NOTE: PHY override parameters are board specific setting.

Example:
		phy1: phy@1f21a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f21a000 0x0 0x100>;
			#phy-cells = <1>;
		};

		phy2: phy@1f22a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f22a000 0x0 0x100>;
			#phy-cells = <1>;
		};

		phy3: phy@1f23a000 {
			compatible = "apm,xgene-phy";
			reg = <0x0 0x1f23a000 0x0 0x100>;
			#phy-cells = <1>;
		};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/bcm-ns-usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Northstar USB 2.0 PHY

description: >
  To initialize USB 2.0 PHY driver needs to setup PLL correctly.
  To do this it requires passing phandle to the USB PHY reference clock.

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

properties:
  compatible:
    const: brcm,ns-usb2-phy

  reg:
    anyOf:
      - maxItems: 1
        description: PHY control register
      - maxItems: 1
        description: iomem address range of DMU (Device Management Unit)
        deprecated: true

  reg-names:
    items:
      - const: dmu

  brcm,syscon-clkset:
    description: phandle to syscon for clkset register
    $ref: /schemas/types.yaml#/definitions/phandle

  clocks:
    items:
      - description: USB PHY reference clock

  clock-names:
    items:
      - const: phy-ref-clk

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#phy-cells"

oneOf:
  - required:
      - brcm,syscon-clkset
  - required:
      - reg-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/bcm-nsp.h>
    phy@1800c164 {
        compatible = "brcm,ns-usb2-phy";
        reg = <0x1800c164 0x4>;
        brcm,syscon-clkset = <&clkset>;
        clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
        clock-names = "phy-ref-clk";
        #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/bcm-ns-usb3-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Northstar USB 3.0 PHY

description: |
  Initialization of USB 3.0 PHY depends on Northstar version. There are currently
  three known series: Ax, Bx and Cx.
  Known A0: BCM4707 rev 0
  Known B0: BCM4707 rev 4, BCM53573 rev 2
  Known B1: BCM4707 rev 6
  Known C0: BCM47094 rev 0

maintainers:
  - Rafał Miłecki <rafal@milecki.pl>

properties:
  compatible:
    enum:
      - brcm,ns-ax-usb3-phy
      - brcm,ns-bx-usb3-phy

  reg:
    description: address of MDIO bus device
    maxItems: 1

  usb3-dmp-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the DMP (Device Management Plugin) syscon

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - usb3-dmp-syscon
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        usb3-phy@10 {
            compatible = "brcm,ns-ax-usb3-phy";
            reg = <0x10>;
            usb3-dmp-syscon = <&usb3_dmp>;
            #phy-cells = <0>;
        };
    };

    usb3_dmp: syscon@18105000 {
        reg = <0x18105000 0x1000>;
    };


code:
Berlin SATA PHY
---------------

Required properties:
- compatible: should be one of
    "marvell,berlin2-sata-phy"
    "marvell,berlin2q-sata-phy"
- address-cells: should be 1
- size-cells: should be 0
- phy-cells: from the generic PHY bindings, must be 1
- reg: address and length of the register
- clocks: reference to the clock entry

Sub-nodes:
Each PHY should be represented as a sub-node.

Sub-nodes required properties:
- reg: the PHY number

Example:
	sata_phy: phy@f7e900a0 {
		compatible = "marvell,berlin2q-sata-phy";
		reg = <0xf7e900a0 0x200>;
		clocks = <&chip CLKID_SATA>;
		#address-cells = <1>;
		#size-cells = <0>;
		#phy-cells = <1>;

		sata-phy@0 {
			reg = <0>;
		};

		sata-phy@1 {
			reg = <1>;
		};
	};


code:
* Marvell Berlin USB PHY

Required properties:
- compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy"
- reg: base address and length of the registers
- #phys-cells: should be 0
- resets: reference to the reset controller

Example:

	usb-phy@f774000 {
		compatible = "marvell,berlin2-usb-phy";
		reg = <0xf774000 0x128>;
		#phy-cells = <0>;
		resets = <&chip 0x104 14>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/brcm,bcm63xx-usbh-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: BCM63xx USBH PHY

maintainers:
  - Álvaro Fernández Rojas <noltari@gmail.com>

properties:
  compatible:
    enum:
      - brcm,bcm6318-usbh-phy
      - brcm,bcm6328-usbh-phy
      - brcm,bcm6358-usbh-phy
      - brcm,bcm6362-usbh-phy
      - brcm,bcm6368-usbh-phy
      - brcm,bcm63268-usbh-phy

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: usbh
      - const: usb_ref

  resets:
    maxItems: 1

  "#phy-cells":
    const: 1

additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - "#phy-cells"

if:
  properties:
    compatible:
      enum:
        - brcm,bcm6318-usbh-phy
        - brcm,bcm6328-usbh-phy
        - brcm,bcm6362-usbh-phy
        - brcm,bcm63268-usbh-phy
then:
  properties:
    power-domains:
      maxItems: 1
  required:
    - power-domains
else:
  properties:
    power-domains: false

examples:
  - |
    usbh: usb-phy@10001700 {
      compatible = "brcm,bcm6368-usbh-phy";
      reg = <0x10001700 0x38>;
      clocks = <&periph_clk 15>;
      clock-names = "usbh";
      resets = <&periph_rst 12>;
      #phy-cells = <1>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/brcm,brcmstb-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom STB USB PHY

description: Broadcom's PHY that handles EHCI/OHCI and/or XHCI

maintainers:
  - Al Cooper <alcooperx@gmail.com>
  - Rafał Miłecki <rafal@milecki.pl>

properties:
  compatible:
    enum:
      - brcm,bcm4908-usb-phy
      - brcm,bcm7211-usb-phy
      - brcm,bcm7216-usb-phy
      - brcm,brcmstb-usb-phy

  reg:
    minItems: 1
    items:
      - description: the base CTRL register
      - description: XHCI EC register
      - description: XHCI GBL register
      - description: USB PHY register
      - description: USB MDIO register
      - description: BDC register

  reg-names:
    minItems: 1
    items:
      - const: ctrl
      - const: xhci_ec
      - const: xhci_gbl
      - const: usb_phy
      - const: usb_mdio
      - const: bdc_ec

  power-domains:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 2

  clock-names:
    minItems: 1
    items:
      - const: sw_usb
      - const: sw_usb3

  interrupts:
    description: wakeup interrupt

  interrupt-names:
    const: wake

  brcm,ipp:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Invert Port Power
    minimum: 0
    maximum: 1

  brcm,ioc:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Invert Over Current detection
    minimum: 0
    maximum: 1

  dr_mode:
    description: PHY Device mode. If this property is not defined, the PHY will
      default to "host" mode.
    enum:
      - host
      - peripheral
      - drd
      - typec-pd

  brcm,syscon-piarbctl:
    description: phandle to syscon for handling config registers
    $ref: /schemas/types.yaml#/definitions/phandle

  brcm,has-xhci:
    description: Indicates the PHY has an XHCI PHY.
    type: boolean

  brcm,has-eohci:
    description: Indicates the PHY has an EHCI/OHCI PHY.
    type: boolean

  "#phy-cells":
    description: |
      Cell allows setting the type of the PHY. Possible values are:
      - PHY_TYPE_USB2 for USB1.1/2.0 PHY
      - PHY_TYPE_USB3 for USB3.x PHY
    const: 1

required:
  - reg
  - "#phy-cells"

anyOf:
  - required:
      - brcm,has-xhci
  - required:
      - brcm,has-eohci

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - const: brcm,bcm4908-usb-phy
              - const: brcm,brcmstb-usb-phy
    then:
      properties:
        reg:
          minItems: 1
          maxItems: 2
  - if:
      properties:
        compatible:
          contains:
            const: brcm,bcm7211-usb-phy
    then:
      properties:
        reg:
          minItems: 5
          maxItems: 6
        reg-names:
          minItems: 5
          maxItems: 6
  - if:
      properties:
        compatible:
          contains:
            const: brcm,bcm7216-usb-phy
    then:
      properties:
        reg:
          minItems: 3
          maxItems: 3
        reg-names:
          minItems: 3
          maxItems: 3

additionalProperties: false

examples:
  - |
    #include <dt-bindings/phy/phy.h>

    usb-phy@f0470200 {
        compatible = "brcm,brcmstb-usb-phy";
        reg = <0xf0470200 0xb8>,
              <0xf0471940 0x6c0>;
        #phy-cells = <1>;
        dr_mode = "host";
        brcm,ioc = <1>;
        brcm,ipp = <1>;
        brcm,has-xhci;
        brcm,has-eohci;
        clocks = <&usb20>, <&usb30>;
        clock-names = "sw_usb", "sw_usb3";
    };
  - |
    #include <dt-bindings/phy/phy.h>

    usb-phy@29f0200 {
        compatible = "brcm,bcm7211-usb-phy";
        reg = <0x29f0200 0x200>,
              <0x29c0880 0x30>,
              <0x29cc100 0x534>,
              <0x2808000 0x24>,
              <0x2980080 0x8>;
        reg-names = "ctrl",
            "xhci_ec",
            "xhci_gbl",
            "usb_phy",
            "usb_mdio";
        brcm,ioc = <0x0>;
        brcm,ipp = <0x0>;
        interrupts = <0x30>;
        interrupt-parent = <&vpu_intr1_nosec_intc>;
        interrupt-names = "wake";
        #phy-cells = <0x1>;
        brcm,has-xhci;
        brcm,syscon-piarbctl = <&syscon_piarbctl>;
        clocks = <&scmi_clk 256>;
        clock-names = "sw_usb";
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom Cygnus PCIe PHY

maintainers:
  - Ray Jui <ray.jui@broadcom.com>
  - Scott Branden <scott.branden@broadcom.com>

properties:
  $nodename:
    pattern: "^pcie[-|_]phy(@.*)?$"

  compatible:
    items:
      - const: brcm,cygnus-pcie-phy

  reg:
    maxItems: 1
    description: >
      Base address and length of the PCIe PHY block

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

patternProperties:
  "^pcie-phy@[0-9]+$":
    type: object
    additionalProperties: false
    description: >
      PCIe PHY child nodes

    properties:
      reg:
        maxItems: 1
        description: >
          The PCIe PHY port number

      "#phy-cells":
        const: 0

    required:
      - reg
      - "#phy-cells"

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"

additionalProperties: false

examples:
  - |
    pcie_phy: pcie_phy@301d0a0 {
      compatible = "brcm,cygnus-pcie-phy";
      reg = <0x0301d0a0 0x14>;
      #address-cells = <1>;
      #size-cells = <0>;

      pcie0_phy: pcie-phy@0 {
          reg = <0>;
          #phy-cells = <0>;
      };

      pcie1_phy: pcie-phy@1 {
          reg = <1>;
          #phy-cells = <0>;
      };
    };


code:
BROADCOM KONA USB2 PHY

Required properties:
 - compatible: brcm,kona-usb2-phy
 - reg: offset and length of the PHY registers
 - #phy-cells: must be 0
Refer to phy/phy-bindings.txt for the generic PHY binding properties

Example:

	usbphy: usb-phy@3f130000 {
		compatible = "brcm,kona-usb2-phy";
		reg = <0x3f130000 0x28>;
		#phy-cells = <0>;
	};


code:
BROADCOM NORTHSTAR2 USB2 (DUAL ROLE DEVICE) PHY

Required properties:
 - compatible: brcm,ns2-drd-phy
 - reg: offset and length of the NS2 PHY related registers.
 - reg-names
   The below registers must be provided.
   icfg - for DRD ICFG configurations
   rst-ctrl - for DRD IDM reset
   crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
   usb2-strap - for port over current polarity reversal
 - #phy-cells: Must be 0. No args required.
 - vbus-gpios: vbus gpio binding
 - id-gpios: id gpio binding

Refer to phy/phy-bindings.txt for the generic PHY binding properties

Example:
	usbdrd_phy: phy@66000960 {
			#phy-cells = <0>;
			compatible = "brcm,ns2-drd-phy";
			reg = <0x66000960 0x24>,
			      <0x67012800 0x4>,
			      <0x6501d148 0x4>,
			      <0x664d0700 0x4>;
			reg-names = "icfg", "rst-ctrl",
				    "crmu-ctrl", "usb2-strap";
			id-gpios = <&gpio_g 30 0>;
			vbus-gpios = <&gpio_g 31 0>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/brcm,ns2-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom NS2 PCIe PHY binding document

maintainers:
  - Ray Jui <ray.jui@broadcom.com>
  - Scott Branden <scott.branden@broadcom.com>

properties:
  compatible:
    const: brcm,ns2-pcie-phy

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    mdio {
       #address-cells = <1>;
       #size-cells = <0>;

       pci-phy@0 {
          compatible = "brcm,ns2-pcie-phy";
          reg = <0x0>;
          #phy-cells = <0>;
       };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Broadcom SATA3 PHY

maintainers:
  - Florian Fainelli <f.fainelli@gmail.com>

properties:
  $nodename:
    pattern: "^sata[-|_]phy(@.*)?$"

  compatible:
    oneOf:
      - items:
          - enum:
              - brcm,bcm7216-sata-phy
              - brcm,bcm7425-sata-phy
              - brcm,bcm7445-sata-phy
              - brcm,bcm63138-sata-phy
          - const: brcm,phy-sata3
      - items:
          - const: brcm,iproc-nsp-sata-phy
      - items:
          - const: brcm,iproc-ns2-sata-phy
      - items:
          - const: brcm,iproc-sr-sata-phy

  reg:
    minItems: 1
    maxItems: 2

  reg-names:
    minItems: 1
    items:
      - const: phy
      - const: phy-ctrl

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

patternProperties:
  "^sata-phy@[0-9]+$":
    type: object
    description: |
      Each port's PHY should be represented as a sub-node.

    properties:
      reg:
        description: The SATA PHY port number
        maxItems: 1

      "#phy-cells":
        const: 0

      "brcm,enable-ssc":
        $ref: /schemas/types.yaml#/definitions/flag
        description: |
          Use spread spectrum clocking (SSC) on this port
          This property is not applicable for "brcm,iproc-ns2-sata-phy",
          "brcm,iproc-nsp-sata-phy" and "brcm,iproc-sr-sata-phy".

      "brcm,rxaeq-mode":
        $ref: /schemas/types.yaml#/definitions/string
        description:
          String that indicates the desired RX equalizer mode.
        enum:
          - off
          - auto
          - manual

      "brcm,rxaeq-value":
        $ref: /schemas/types.yaml#/definitions/uint32
        description: |
            When 'brcm,rxaeq-mode' is set to "manual", provides the RX
            equalizer value that should be used.
        minimum: 0
        maximum: 63

      "brcm,tx-amplitude-millivolt":
        description: |
            Transmit amplitude voltage in millivolt.
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [400, 500, 600, 800]

    required:
      - reg
      - "#phy-cells"

    additionalProperties: false

if:
  properties:
    compatible:
      const: brcm,iproc-ns2-sata-phy
then:
  properties:
    reg:
      minItems: 2

    reg-names:
      minItems: 2
else:
  properties:
    reg:
      maxItems: 1

    reg-names:
      maxItems: 1

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - reg
  - reg-names

additionalProperties: false

examples:
  - |
    sata_phy@f0458100 {
        compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
        reg = <0xf0458100 0x1e00>;
        reg-names = "phy";
        #address-cells = <1>;
        #size-cells = <0>;

        sata-phy@0 {
                reg = <0>;
                #phy-cells = <0>;
        };

        sata-phy@1 {
                reg = <1>;
                #phy-cells = <0>;
        };
    };


code:
Broadcom Stingray PCIe PHY

Required properties:
- compatible: must be "brcm,sr-pcie-phy"
- reg: base address and length of the PCIe SS register space
- brcm,sr-cdru: phandle to the CDRU syscon node
- brcm,sr-mhb: phandle to the MHB syscon node
- #phy-cells: Must be 1, denotes the PHY index

For PAXB based root complex, one can have a configuration of up to 8 PHYs
PHY index goes from 0 to 7

For the internal PAXC based root complex, PHY index is always 8

Example:
	mhb: syscon@60401000 {
		compatible = "brcm,sr-mhb", "syscon";
		reg = <0 0x60401000 0 0x38c>;
	};

	cdru: syscon@6641d000 {
		compatible = "brcm,sr-cdru", "syscon";
		reg = <0 0x6641d000 0 0x400>;
	};

	pcie_phy: phy@40000000 {
		compatible = "brcm,sr-pcie-phy";
		reg = <0 0x40000000 0 0x800>;
		brcm,sr-cdru = <&cdru>;
		brcm,sr-mhb = <&mhb>;
		#phy-cells = <1>;
	};

	/* users of the PCIe PHY */

	pcie0: pcie@48000000 {
		...
		...
		phys = <&pcie_phy 0>;
		phy-names = "pcie-phy";
	};


code:
Broadcom Stingray USB PHY

Required properties:
 - compatible : should be one of the listed compatibles
	- "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
	- "brcm,sr-usb-hs-phy" is a single HS PHY.
 - reg: offset and length of the PHY blocks registers
 - #phy-cells:
   - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
     the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
   - Must be 0 for brcm,sr-usb-hs-phy.

Refer to phy/phy-bindings.txt for the generic PHY binding properties

Example:
	usbphy0: usb-phy@0 {
		compatible = "brcm,sr-usb-combo-phy";
		reg = <0x00000000 0x100>;
		#phy-cells = <1>;
	};

	usbphy1: usb-phy@10000 {
		compatible = "brcm,sr-usb-combo-phy";
		reg = <0x00010000 0x100>,
		#phy-cells = <1>;
	};

	usbphy2: usb-phy@20000 {
		compatible = "brcm,sr-usb-hs-phy";
		reg = <0x00020000 0x100>,
		#phy-cells = <0>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Calxeda Highbank Combination PHYs binding for SATA

description: |
  The Calxeda Combination PHYs connect the SoC to the internal fabric
  and to SATA connectors. The PHYs support multiple protocols (SATA,
  SGMII, PCIe) and can be assigned to different devices (SATA or XGMAC
  controller).
  Programming the PHYs is typically handled by those device drivers,
  not by a dedicated PHY driver.

maintainers:
  - Andre Przywara <andre.przywara@arm.com>

properties:
  compatible:
    const: calxeda,hb-combophy

  '#phy-cells':
    const: 1

  reg:
    maxItems: 1

  phydev:
    description: device ID for programming the ComboPHY.
    $ref: /schemas/types.yaml#/definitions/uint32
    maximum: 31

required:
  - compatible
  - reg
  - phydev
  - '#phy-cells'

additionalProperties: false

examples:
  - |
    combophy5: combo-phy@fff5d000 {
                   compatible = "calxeda,hb-combophy";
                   #phy-cells = <1>;
                   reg = <0xfff5d000 0x1000>;
                   phydev = <31>;
               };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence DPHY Rx

maintainers:
  - Pratyush Yadav <pratyush@kernel.org>

properties:
  compatible:
    items:
      - const: cdns,dphy-rx

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    dphy0: phy@4580000 {
        compatible = "cdns,dphy-rx";
        reg = <0x4580000 0x1100>;
        #phy-cells = <0>;
        power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence DPHY

maintainers:
  - Pratyush Yadav <pratyush@kernel.org>

properties:
  compatible:
    enum:
      - cdns,dphy
      - ti,j721e-dphy

  reg:
    maxItems: 1

  clocks:
    items:
      - description: PMA state machine clock
      - description: PLL reference clock

  clock-names:
    items:
      - const: psm
      - const: pll_ref

  "#phy-cells":
    const: 0

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    dphy0: phy@fd0e0000{
        compatible = "cdns,dphy";
        reg = <0xfd0e0000 0x1000>;
        clocks = <&psm_clk>, <&pll_ref_clk>;
        clock-names = "psm", "pll_ref";
        power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
        #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (c) 2020 NXP
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence SALVO PHY

maintainers:
  - Peter Chen <peter.chen@nxp.com>

properties:
  compatible:
    enum:
      - nxp,salvo-phy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: salvo_phy_clk

  power-domains:
    maxItems: 1

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/firmware/imx/rsrc.h>

    usb3phy: usb3-phy@5b160000 {
        compatible = "nxp,salvo-phy";
        reg = <0x5b160000 0x40000>;
        clocks = <&usb3_lpcg 4>;
        clock-names = "salvo_phy_clk";
        power-domains = <&pd IMX_SC_R_USB_2_PHY>;
        #phy-cells = <0>;
    };


code:
Device tree binding documentation for am816x USB PHY
=========================

Required properties:
- compatible : should be "ti,dm816x-usb-phy"
- reg : offset and length of the PHY register set.
- reg-names : name for the phy registers
- clocks : phandle to the clock
- clock-names : name of the clock
- syscon: phandle for the syscon node to access misc registers
- #phy-cells : from the generic PHY bindings, must be 1
- syscon: phandle for the syscon node to access misc registers

Example:

usb_phy0: usb-phy@20 {
	compatible = "ti,dm8168-usb-phy";
	reg = <0x20 0x8>;
	reg-names = "phy";
	clocks = <&main_fapll 6>;
	clock-names = "refclk";
	#phy-cells = <0>;
	syscon = <&scm_conf>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8 SoC series PCIe PHY

maintainers:
  - Richard Zhu <hongxing.zhu@nxp.com>

properties:
  "#phy-cells":
    const: 0

  compatible:
    enum:
      - fsl,imx8mm-pcie-phy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: ref

  resets:
    maxItems: 1

  reset-names:
    items:
      - const: pciephy

  fsl,refclk-pad-mode:
    description: |
      Specifies the mode of the refclk pad used. It can be UNUSED(PHY
      refclock is derived from SoC internal source), INPUT(PHY refclock
      is provided externally via the refclk pad) or OUTPUT(PHY refclock
      is derived from SoC internal source and provided on the refclk pad).
      Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
      to be used.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [ 0, 1, 2 ]

  fsl,tx-deemph-gen1:
    description: Gen1 De-emphasis value (optional).
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

  fsl,tx-deemph-gen2:
    description: Gen2 De-emphasis value (optional).
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

  fsl,clkreq-unsupported:
    type: boolean
    description: A boolean property indicating the CLKREQ# signal is
      not supported in the board design (optional)

required:
  - "#phy-cells"
  - compatible
  - reg
  - clocks
  - clock-names
  - fsl,refclk-pad-mode

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mm-clock.h>
    #include <dt-bindings/phy/phy-imx8-pcie.h>
    #include <dt-bindings/reset/imx8mq-reset.h>

    pcie_phy: pcie-phy@32f00000 {
            compatible = "fsl,imx8mm-pcie-phy";
            reg = <0x32f00000 0x10000>;
            clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
            clock-names = "ref";
            assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
            assigned-clock-rates = <100000000>;
            assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
            resets = <&src IMX8MQ_RESET_PCIEPHY>;
            reset-names = "pciephy";
            fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
            #phy-cells = <0>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8MQ USB3 PHY binding

maintainers:
  - Li Jun <jun.li@nxp.com>

properties:
  compatible:
    enum:
      - fsl,imx8mq-usb-phy
      - fsl,imx8mp-usb-phy

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: phy

  power-domains:
    maxItems: 1

  vbus-supply:
    description:
      A phandle to the regulator for USB VBUS.

required:
  - compatible
  - reg
  - "#phy-cells"
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mq-clock.h>
    usb3_phy0: phy@381f0040 {
        compatible = "fsl,imx8mq-usb-phy";
        reg = <0x381f0040 0x40>;
        clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
        clock-names = "phy";
        #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mixel LVDS PHY for Freescale i.MX8qm SoC

maintainers:
  - Liu Ying <victor.liu@nxp.com>

description: |
  The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
  It converts two groups of four 7/10 bits of CMOS data into two
  groups of four data lanes of LVDS data streams. A phase-locked
  transmit clock is transmitted in parallel with each group of
  data streams over a fifth LVDS link. Every cycle of the transmit
  clock, 56/80 bits of input data are sampled and transmitted
  through the two groups of LVDS data streams. Together with the
  transmit clocks, the two groups of LVDS data streams form two
  LVDS channels.

  The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
  by Control and Status Registers(CSR) module in the SoC. The CSR
  module, as a system controller, contains the PHY's registers.

properties:
  compatible:
    enum:
      - fsl,imx8qm-lvds-phy
      - mixel,28fdsoi-lvds-1250-8ch-tx-pll

  "#phy-cells":
    const: 1
    description: |
      Cell allows setting the LVDS channel index of the PHY.
      Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - "#phy-cells"
  - clocks
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/firmware/imx/rsrc.h>
    phy {
        compatible = "fsl,imx8qm-lvds-phy";
        #phy-cells = <1>;
        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
        power-domains = <&pd IMX_SC_R_LVDS_0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/fsl,lynx-28g.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Lynx 28G SerDes PHY binding

maintainers:
  - Ioana Ciornei <ioana.ciornei@nxp.com>

properties:
  compatible:
    enum:
      - fsl,lynx-28g

  reg:
    maxItems: 1

  "#phy-cells":
    const: 1

required:
  - compatible
  - reg
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    soc {
      #address-cells = <2>;
      #size-cells = <2>;
      serdes_1: phy@1ea0000 {
        compatible = "fsl,lynx-28g";
        reg = <0x0 0x1ea0000 0x0 0x1e30>;
        #phy-cells = <1>;
      };
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/hisilicon,hi3660-usb3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Hisilicon Kirin 960 USB PHY

maintainers:
  - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
description: |+
  Bindings for USB3 PHY on HiSilicon Kirin 960.

properties:
  compatible:
    const: hisilicon,hi3660-usb-phy

  "#phy-cells":
    const: 0

  hisilicon,pericrg-syscon:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: phandle of syscon used to control iso refclk.

  hisilicon,pctrl-syscon:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: phandle of syscon used to control usb tcxo.

  hisilicon,eye-diagram-param:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Eye diagram for phy.

required:
  - compatible
  - hisilicon,pericrg-syscon
  - hisilicon,pctrl-syscon
  - hisilicon,eye-diagram-param
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    usb-phy {
        compatible = "hisilicon,hi3660-usb-phy";
        #phy-cells = <0>;
        hisilicon,pericrg-syscon = <&crg_ctrl>;
        hisilicon,pctrl-syscon = <&pctrl>;
        hisilicon,eye-diagram-param = <0x22466e4>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Hisilicon Kirin970 USB PHY

maintainers:
  - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

description: |+
  Bindings for USB3 PHY on HiSilicon Kirin 970.

properties:
  compatible:
    const: hisilicon,hi3670-usb-phy

  "#phy-cells":
    const: 0

  hisilicon,pericrg-syscon:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: phandle of syscon used to control iso refclk.

  hisilicon,pctrl-syscon:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: phandle of syscon used to control usb tcxo.

  hisilicon,sctrl-syscon:
    $ref: '/schemas/types.yaml#/definitions/phandle'
    description: phandle of syscon used to control phy deep sleep.

  hisilicon,eye-diagram-param:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Eye diagram for phy.

  hisilicon,tx-vboost-lvl:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: TX level vboost for phy.

required:
  - compatible
  - hisilicon,pericrg-syscon
  - hisilicon,pctrl-syscon
  - hisilicon,sctrl-syscon
  - hisilicon,eye-diagram-param
  - hisilicon,tx-vboost-lvl
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    usb-phy {
        compatible = "hisilicon,hi3670-usb-phy";
        #phy-cells = <0>;
        hisilicon,pericrg-syscon = <&crg_ctrl>;
        hisilicon,pctrl-syscon = <&pctrl>;
        hisilicon,sctrl-syscon = <&sctrl>;
        hisilicon,eye-diagram-param = <0xfdfee4>;
        hisilicon,tx-vboost-lvl = <0x5>;
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: HiSilicon Kirin970 PCIe PHY

maintainers:
  - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

description: |+
  Bindings for PCIe PHY on HiSilicon Kirin 970.

properties:
  compatible:
    const: hisilicon,hi970-pcie-phy

  "#phy-cells":
    const: 0

  reg:
    maxItems: 1
    description: PHY Control registers

  phy-supply:
    description: The PCIe PHY power supply

  clocks:
    items:
      - description: PCIe PHY clock
      - description: PCIe AUX clock
      - description: PCIe APB PHY clock
      - description: PCIe APB SYS clock
      - description: PCIe ACLK clock

  clock-names:
    items:
      - const: phy_ref
      - const: aux
      - const: apb_phy
      - const: apb_sys
      - const: aclk

  hisilicon,eye-diagram-param:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: Eye diagram for phy.

required:
  - "#phy-cells"
  - compatible
  - reg
  - clocks
  - clock-names
  - hisilicon,eye-diagram-param
  - phy-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/hi3670-clock.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;
      pcie_phy: pcie-phy@fc000000 {
        compatible = "hisilicon,hi970-pcie-phy";
        reg = <0x0 0xfc000000 0x0 0x80000>;
        #phy-cells = <0>;
        phy-supply = <&ldo33>;
        clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
                 <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
                 <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
                 <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
                 <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
        clock-names = "phy_ref", "aux",
                      "apb_phy", "apb_sys", "aclk";
        hisilicon,eye-diagram-param = <0xffffffff 0xffffffff
                                       0xffffffff 0xffffffff 0xffffffff>;
      };
    };


code:
Hisilicon hix5hd2 SATA PHY
-----------------------

Required properties:
- compatible: should be "hisilicon,hix5hd2-sata-phy"
- reg: offset and length of the PHY registers
- #phy-cells: must be 0
Refer to phy/phy-bindings.txt for the generic PHY binding properties

Optional Properties:
- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
- hisilicon,power-reg: offset and bit number within peripheral-syscon,
	register of controlling sata power supply.

Example:
	sata_phy: phy@f9900000 {
		compatible = "hisilicon,hix5hd2-sata-phy";
		reg = <0xf9900000 0x10000>;
		#phy-cells = <0>;
		hisilicon,peripheral-syscon = <&peripheral_ctrl>;
		hisilicon,power-reg = <0x8 10>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/ingenic,phy-usb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs USB PHY devicetree bindings

maintainers:
  - Paul Cercueil <paul@crapouillou.net>
  - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

properties:
  $nodename:
    pattern: '^usb-phy@.*'

  compatible:
    enum:
      - ingenic,jz4770-phy
      - ingenic,jz4775-phy
      - ingenic,jz4780-phy
      - ingenic,x1000-phy
      - ingenic,x1830-phy
      - ingenic,x2000-phy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  vcc-supply:
    description: VCC power supply

  '#phy-cells':
    const: 0

required:
  - compatible
  - reg
  - clocks
  - vcc-supply
  - '#phy-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
    otg_phy: usb-phy@3c {
      compatible = "ingenic,jz4770-phy";
      reg = <0x3c 0x10>;

      vcc-supply = <&vcc>;
      clocks = <&cgu JZ4770_CLK_OTG_PHY>;

      #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel ComboPhy Subsystem

maintainers:
  - Dilip Kota <eswara.kota@linux.intel.com>

description: |
  Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
  controllers. A single Combophy provides two PHY instances.

properties:
  $nodename:
    pattern: "combophy(@.*|-[0-9a-f])*$"

  compatible:
    items:
      - const: intel,combophy-lgm
      - const: intel,combo-phy

  clocks:
    maxItems: 1

  reg:
    items:
      - description: ComboPhy core registers
      - description: PCIe app core control registers

  reg-names:
    items:
      - const: core
      - const: app

  resets:
    maxItems: 4

  reset-names:
    items:
      - const: phy
      - const: core
      - const: iphy0
      - const: iphy1

  intel,syscfg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to Chip configuration registers
          - description: ComboPhy instance id
    description: Chip configuration registers handle and ComboPhy instance id

  intel,hsio:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to HSIO registers
          - description: ComboPhy instance id
    description: HSIO registers handle and ComboPhy instance id on NOC

  intel,aggregation:
    type: boolean
    description: |
      Specify the flag to configure ComboPHY in dual lane mode.

  intel,phy-mode:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Mode of the two phys in ComboPhy.
      See dt-bindings/phy/phy.h for values.

  "#phy-cells":
    const: 1

required:
  - compatible
  - clocks
  - reg
  - reg-names
  - intel,syscfg
  - intel,hsio
  - intel,phy-mode
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/phy/phy.h>
    combophy@d0a00000 {
        compatible = "intel,combophy-lgm", "intel,combo-phy";
        clocks = <&cgu0 1>;
        #phy-cells = <1>;
        reg = <0xd0a00000 0x40000>,
              <0xd0a40000 0x1000>;
        reg-names = "core", "app";
        resets = <&rcu0 0x50 6>,
                 <&rcu0 0x50 17>,
                 <&rcu0 0x50 23>,
                 <&rcu0 0x50 24>;
        reset-names = "phy", "core", "iphy0", "iphy1";
        intel,syscfg = <&sysconf 0>;
        intel,hsio = <&hsiol 0>;
        intel,phy-mode = <PHY_TYPE_PCIE>;
        intel,aggregation;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/intel,keembay-phy-usb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Keem Bay USB PHY bindings

maintainers:
  - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>

properties:
  compatible:
    const: intel,keembay-usb-phy

  reg:
    items:
      - description: USB APB CPR (clock, power, reset) register
      - description: USB APB slave register

  reg-names:
    items:
      - const: cpr-apb-base
      - const: slv-apb-base

  '#phy-cells':
    const: 0

required:
  - compatible
  - reg
  - '#phy-cells'

additionalProperties: false

examples:
  - |
    usb-phy@20400000 {
          compatible = "intel,keembay-usb-phy";
          reg = <0x20400000 0x1c>,
                <0x20480000 0xd0>;
          reg-names = "cpr-apb-base", "slv-apb-base";
          #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Lightning Mountain(LGM) eMMC PHY

maintainers:
  - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>

description: |+
  Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
  node is used to reference the base address of eMMC phy registers.

  The eMMC PHY node should be the child of a syscon node with the
  required property:

  - compatible:         Should be one of the following:
                        "intel,lgm-syscon", "syscon"
  - reg:
      maxItems: 1

properties:
  compatible:
    enum:
      - intel,lgm-emmc-phy
      - intel,keembay-emmc-phy

  "#phy-cells":
    const: 0

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: emmcclk

required:
  - "#phy-cells"
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    sysconf: chiptop@e0200000 {
      compatible = "intel,lgm-syscon", "syscon";
      reg = <0xe0200000 0x100>;
      #address-cells = <1>;
      #size-cells = <1>;

      emmc_phy: emmc-phy@a8 {
        compatible = "intel,lgm-emmc-phy";
        reg = <0x00a8 0x10>;
        clocks = <&emmc>;
        #phy-cells = <0>;
      };
    };

  - |
    phy@20290000 {
          compatible = "intel,keembay-emmc-phy";
          reg = <0x20290000 0x54>;
          clocks = <&emmc>;
          clock-names = "emmcclk";
          #phy-cells = <0>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/intel,lgm-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel LGM USB PHY

maintainers:
  - Vadivel Murugan Ramuthevar <vadivel.muruganx.ramuthevar@linux.intel.com>

properties:
  compatible:
    const: intel,lgm-usb-phy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    items:
      - description: USB PHY and Host controller reset
      - description: APB BUS reset
      - description: General Hardware reset

  reset-names:
    items:
      - const: phy
      - const: apb
      - const: phy31

  "#phy-cells":
    const: 0

required:
  - compatible
  - clocks
  - reg
  - resets
  - reset-names
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    usb-phy@e7e00000 {
        compatible = "intel,lgm-usb-phy";
        reg = <0xe7e00000 0x10000>;
        clocks = <&cgu0 153>;
        resets = <&rcu 0x70 0x24>,
                 <&rcu 0x70 0x26>,
                 <&rcu 0x70 0x28>;
        reset-names = "phy", "apb", "phy31";
        #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/intel,phy-thunderbay-emmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Thunder Bay eMMC PHY bindings

maintainers:
  - Srikandan Nandhini <nandhini.srikandan@intel.com>

properties:
  compatible:
    const: intel,thunderbay-emmc-phy

  "#phy-cells":
    const: 0

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: emmcclk

required:
  - "#phy-cells"
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    mmc_phy@80440800 {
        #phy-cells = <0x0>;
        compatible = "intel,thunderbay-emmc-phy";
        reg = <0x80440800 0x100>;
        clocks = <&emmc>;
        clock-names = "emmcclk";
    };


code:
TI Keystone USB PHY

Required properties:
 - compatible: should be "ti,keystone-usbphy".
 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
   with 'reg' property.
 - reg : Address and length of the usb phy control register set.

The main purpose of this PHY driver is to enable the USB PHY reference clock
gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
an NOP PHY driver.  Hence this node is referenced as both the usb2 and usb3
phy node in the USB Glue layer driver node.

usb_phy: usb_phy@2620738 {
	compatible = "ti,keystone-usbphy";
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0x2620738 32>;
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Lantiq VRX200 and ARX300 PCIe PHY

maintainers:
  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>

properties:
  "#phy-cells":
    const: 1
    description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>

  compatible:
    enum:
      - lantiq,vrx200-pcie-phy
      - lantiq,arx300-pcie-phy

  reg:
    maxItems: 1

  clocks:
    items:
      - description: PHY module clock
      - description: PDI register clock

  clock-names:
    items:
      - const: phy
      - const: pdi

  resets:
    items:
      - description: exclusive PHY reset line
      - description: shared reset line between the PCIe PHY and PCIe controller

  reset-names:
    items:
      - const: phy
      - const: pcie

  lantiq,rcu:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle to the RCU syscon

  lantiq,rcu-endian-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: the offset of the endian registers for this PHY instance in the RCU syscon

  lantiq,rcu-big-endian-mask:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: the mask to set the PDI (PHY) registers for this PHY instance to big endian

  big-endian:
    description: Configures the PDI (PHY) registers in big-endian mode
    type: boolean

  little-endian:
    description: Configures the PDI (PHY) registers in big-endian mode
    type: boolean

required:
  - "#phy-cells"
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - lantiq,rcu
  - lantiq,rcu-endian-offset
  - lantiq,rcu-big-endian-mask

additionalProperties: false

examples:
  - |
    pcie0_phy: phy@106800 {
        compatible = "lantiq,vrx200-pcie-phy";
        reg = <0x106800 0x100>;
        lantiq,rcu = <&rcu0>;
        lantiq,rcu-endian-offset = <0x4c>;
        lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
        big-endian;
        clocks = <&pmu 32>, <&pmu 36>;
        clock-names = "phy", "pdi";
        resets = <&reset0 12 24>, <&reset0 22 22>;
        reset-names = "phy", "pcie";
        #phy-cells = <1>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/marvell,armada-3700-utmi-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Marvell Armada UTMI/UTMI+ PHY

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

description:
  On Armada 3700, there are two USB controllers, one is compatible with
  the USB2 and USB3 specifications and supports OTG. The other one is USB2
  compliant and only supports host mode. Both of these controllers come with
  a slightly different UTMI PHY.

properties:
  compatible:
    enum:
      - marvell,a3700-utmi-host-phy
      - marvell,a3700-utmi-otg-phy
  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  marvell,usb-misc-reg:
    description:
      Phandle on the "USB miscellaneous registers" shared region
      covering registers related to both the host controller and
      the PHY.
    $ref: /schemas/types.yaml#/definitions/phandle

required:
  - compatible
  - reg
  - "#phy-cells"
  - marvell,usb-misc-reg

additionalProperties: false

examples:
  - |
    usb2_utmi_host_phy: phy@5f000 {
      compatible = "marvell,a3700-utmi-host-phy";
      reg = <0x5f000 0x800>;
      marvell,usb-misc-reg = <&usb2_syscon>;
      #phy-cells = <0>;
    };

    usb2_syscon: system-controller@5f800 {
      compatible = "marvell,armada-3700-usb2-host-misc", "syscon";
      reg = <0x5f800 0x800>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Marvell Armada CP110/CP115 UTMI PHY

maintainers:
  - Konstantin Porotchkin <kostap@marvell.com>

description:
  On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
  Each of two exiting UTMI PHYs could be connected to either USB host or USB device
  controller.
  The USB device controller can only be connected to a single UTMI PHY port
                      0.H----- USB HOST0
  UTMI PHY0  --------/
                      0.D-----0
                               \------ USB DEVICE
                      1.D-----1
  UTMI PHY1  --------\
                      1.H----- USB HOST1

properties:
  compatible:
    const: marvell,cp110-utmi-phy

  reg:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

  marvell,system-controller:
    description:
      Phandle to the system controller node
    $ref: /schemas/types.yaml#/definitions/phandle

#Required child nodes:

patternProperties:
  "^usb-phy@[0|1]$":
    type: object
    description:
      Each UTMI PHY port must be represented as a sub-node.

    properties:
      reg:
        description: phy port index.
        maxItems: 1

      "#phy-cells":
        const: 0

    required:
      - reg
      - "#phy-cells"

    additionalProperties: false

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - marvell,system-controller

additionalProperties: false

examples:
  - |
    cp0_utmi: utmi@580000 {
      compatible = "marvell,cp110-utmi-phy";
      reg = <0x580000 0x2000>;
      marvell,system-controller = <&cp0_syscon0>;
      #address-cells = <1>;
      #size-cells = <0>;

      cp0_utmi0: usb-phy@0 {
        reg = <0>;
        #phy-cells = <0>;
      };

      cp0_utmi1: usb-phy@1 {
        reg = <1>;
        #phy-cells = <0>;
      };
    };

    cp0_usb3_0 {
      usb-phy = <&cp0_usb3_0_phy0>;
      phys = <&cp0_utmi0>;
      phy-names = "utmi";
      /* UTMI0 is connected to USB host controller (default mode) */
      dr_mode = "host";
    };

    cp0_usb3_1 {
      usb-phy = <&cp0_usb3_0_phy1>;
      phys = <&cp0_utmi1>;
      phy-names = "utmi";
      /* UTMI1 is connected to USB device controller */
      dr_mode = "peripheral";
    };


code:
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
# Copyright 2019 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/marvell,mmp3-hsic-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Marvell MMP3 HSIC PHY

maintainers:
  - Lubomir Rintel <lkundrak@v3.sk>

properties:
  compatible:
    const: marvell,mmp3-hsic-phy

  reg:
    maxItems: 1
    description: base address of the device

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    hsic-phy@f0001800 {
            compatible = "marvell,mmp3-hsic-phy";
            reg = <0xf0001800 0x40>;
            #phy-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
# Copyright 2019,2020 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/marvell,mmp3-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell MMP3 USB PHY bindings

maintainers:
  - Lubomir Rintel <lkundrak@v3.sk>

properties:
  $nodename:
    pattern: '^usb-phy@[a-f0-9]+$'

  compatible:
    const: marvell,mmp3-usb-phy

  reg:
    maxItems: 1
    description: base address of the device

  '#phy-cells':
    const: 0

required:
  - compatible
  - reg
  - '#phy-cells'

additionalProperties: false

examples:
  - |
    usb-phy@d4207000 {
      compatible = "marvell,mmp3-usb-phy";
      reg = <0xd4207000 0x40>;
      #phy-cells = <0>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek MIPI Display Serial Interface (DSI) PHY binding

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>
  - Chunfeng Yun <chunfeng.yun@mediatek.com>

description: The MIPI DSI PHY supports up to 4-lane output.

properties:
  $nodename:
    pattern: "^dsi-phy@[0-9a-f]+$"

  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt7623-mipi-tx
          - const: mediatek,mt2701-mipi-tx
      - items:
          - enum:
              - mediatek,mt8365-mipi-tx
          - const: mediatek,mt8183-mipi-tx
      - const: mediatek,mt2701-mipi-tx
      - const: mediatek,mt8173-mipi-tx
      - const: mediatek,mt8183-mipi-tx

  reg:
    maxItems: 1

  clocks:
    items:
      - description: PLL reference clock

  clock-output-names:
    maxItems: 1

  "#phy-cells":
    const: 0

  "#clock-cells":
    const: 0

  nvmem-cells:
    maxItems: 1
    description: A phandle to the calibration data provided by a nvmem device,
      if unspecified, default values shall be used.

  nvmem-cell-names:
    items:
      - const: calibration-data

  drive-strength-microamp:
    description: adjust driving current
    multipleOf: 200
    minimum: 2000
    maximum: 6000
    default: 4600

required:
  - compatible
  - reg
  - clocks
  - clock-output-names
  - "#phy-cells"
  - "#clock-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>
    dsi-phy@10215000 {
        compatible = "mediatek,mt8173-mipi-tx";
        reg = <0x10215000 0x1000>;
        clocks = <&clk26m>;
        clock-output-names = "mipi_tx0_pll";
        drive-strength-microamp = <4000>;
        nvmem-cells= <&mipi_tx_calibration>;
        nvmem-cell-names = "calibration-data";
        #clock-cells = <0>;
        #phy-cells = <0>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>
  - Chunfeng Yun <chunfeng.yun@mediatek.com>

description: |
  The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
  output and drives the HDMI pads.

properties:
  $nodename:
    pattern: "^hdmi-phy@[0-9a-f]+$"

  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt7623-hdmi-phy
          - const: mediatek,mt2701-hdmi-phy
      - const: mediatek,mt2701-hdmi-phy
      - const: mediatek,mt8173-hdmi-phy

  reg:
    maxItems: 1

  clocks:
    items:
      - description: PLL reference clock

  clock-names:
    items:
      - const: pll_ref

  clock-output-names:
    items:
      - const: hdmitx_dig_cts

  "#phy-cells":
    const: 0

  "#clock-cells":
    const: 0

  mediatek,ibias:
    description:
      TX DRV bias current for < 1.65Gbps
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 63
    default: 0xa

  mediatek,ibias_up:
    description:
      TX DRV bias current for >= 1.65Gbps
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 63
    default: 0x1c

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - clock-output-names
  - "#phy-cells"
  - "#clock-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>
    hdmi_phy: hdmi-phy@10209100 {
        compatible = "mediatek,mt8173-hdmi-phy";
        reg = <0x10209100 0x24>;
        clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
        clock-names = "pll_ref";
        clock-output-names = "hdmitx_dig_cts";
        mediatek,ibias = <0xa>;
        mediatek,ibias_up = <0x1c>;
        #clock-cells = <0>;
        #phy-cells = <0>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/mediatek,mt7621-pci-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Mediatek Mt7621 PCIe PHY

maintainers:
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

properties:
  compatible:
    const: mediatek,mt7621-pci-phy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  "#phy-cells":
    const: 1
    description: selects if the phy is dual-ported

required:
  - compatible
  - reg
  - clocks
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    pcie0_phy: pcie-phy@1e149000 {
      compatible = "mediatek,mt7621-pci-phy";
      reg = <0x1e149000 0x0700>;
      clocks = <&sysc 0>;
      #phy-cells = <1>;
    };