code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2020 Gateworks Corporation
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>

#include "imx8mm.dtsi"

/ {
	model = "Gateworks Venice GW7901 i.MX8MM board";
	compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";

	aliases {
		ethernet0 = &fec1;
		ethernet1 = &lan1;
		ethernet2 = &lan2;
		ethernet3 = &lan3;
		ethernet4 = &lan4;
		usb0 = &usbotg1;
		usb1 = &usbotg2;
	};

	chosen {
		stdout-path = &uart2;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-user-pb {
			label = "user_pb";
			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_0>;
		};

		key-user-pb1x {
			label = "user_pb1x";
			linux,code = <BTN_1>;
			interrupt-parent = <&gsc>;
			interrupts = <0>;
		};

		key-erased {
			label = "key_erased";
			linux,code = <BTN_2>;
			interrupt-parent = <&gsc>;
			interrupts = <1>;
		};

		key-eeprom-wp {
			label = "eeprom_wp";
			linux,code = <BTN_3>;
			interrupt-parent = <&gsc>;
			interrupts = <2>;
		};

		key-tamper {
			label = "tamper";
			linux,code = <BTN_4>;
			interrupt-parent = <&gsc>;
			interrupts = <5>;
		};

		switch-hold {
			label = "switch_hold";
			linux,code = <BTN_5>;
			interrupt-parent = <&gsc>;
			interrupts = <7>;
		};
	};

	led-controller {
		compatible = "gpio-leds";

		led-0 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led01_red";
			gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-1 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led01_grn";
			gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-2 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led02_red";
			gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-3 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led02_grn";
			gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-4 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led03_red";
			gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-5 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led03_grn";
			gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-6 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led04_red";
			gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-7 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led04_grn";
			gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-8 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led05_red";
			gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-9 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led05_grn";
			gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-a {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led06_red";
			gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-b {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led06_grn";
			gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	regulator-ioexp {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_ioexp>;
		compatible = "regulator-fixed";
		regulator-name = "ioexp";
		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	regulator-isouart {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_isouart>;
		compatible = "regulator-fixed";
		regulator-name = "iso_uart";
		gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
		startup-delay-us = <100>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_usb2_vbus: regulator-usb2 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb2>;
		compatible = "regulator-fixed";
		regulator-name = "usb_usb2_vbus";
		gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_wifi: regulator-wifi {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_wl>;
		compatible = "regulator-fixed";
		regulator-name = "wifi";
		gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

&disp_blk_ctrl {
	status = "disabled";
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <40000000>;
		status = "okay";
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	local-mac-address = [00 00 00 00 00 00];
	status = "okay";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&gpio1 {
	gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#",
		"", "uart1_rs232#", "dig1_in", "dig1_out",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio4 {
	gpio-line-names = "", "", "", "",
		"", "", "uart3_rs232#", "uart3_rs422#",
		"uart3_rs485#", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
};

&gpio5 {
	gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "",
		"", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpu_2d {
	status = "disabled";
};

&gpu_3d {
	status = "disabled";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	gsc: gsc@20 {
		compatible = "gw,gsc";
		reg = <0x20>;
		pinctrl-0 = <&pinctrl_gsc>;
		interrupt-parent = <&gpio4>;
		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <1>;

		adc {
			compatible = "gw,gsc-adc";
			#address-cells = <1>;
			#size-cells = <0>;

			channel@6 {
				gw,mode = <0>;
				reg = <0x06>;
				label = "temp";
			};

			channel@8 {
				gw,mode = <1>;
				reg = <0x08>;
				label = "vdd_bat";
			};

			channel@82 {
				gw,mode = <2>;
				reg = <0x82>;
				label = "vin_aux1";
				gw,voltage-divider-ohms = <22100 1000>;
			};

			channel@84 {
				gw,mode = <2>;
				reg = <0x84>;
				label = "vin_aux2";
				gw,voltage-divider-ohms = <22100 1000>;
			};

			channel@86 {
				gw,mode = <2>;
				reg = <0x86>;
				label = "vdd_vin";
				gw,voltage-divider-ohms = <22100 1000>;
			};

			channel@88 {
				gw,mode = <2>;
				reg = <0x88>;
				label = "vdd_3p3";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@8c {
				gw,mode = <2>;
				reg = <0x8c>;
				label = "vdd_2p5";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@8e {
				gw,mode = <2>;
				reg = <0x8e>;
				label = "vdd_0p95";
			};

			channel@90 {
				gw,mode = <2>;
				reg = <0x90>;
				label = "vdd_soc";
			};

			channel@92 {
				gw,mode = <2>;
				reg = <0x92>;
				label = "vdd_arm";
			};

			channel@98 {
				gw,mode = <2>;
				reg = <0x98>;
				label = "vdd_1p8";
			};

			channel@9a {
				gw,mode = <2>;
				reg = <0x9a>;
				label = "vdd_1p2";
			};

			channel@9c {
				gw,mode = <2>;
				reg = <0x9c>;
				label = "vdd_dram";
			};

			channel@a2 {
				gw,mode = <2>;
				reg = <0xa2>;
				label = "vdd_gsc";
				gw,voltage-divider-ohms = <10000 10000>;
			};
		};
	};

	gpio: gpio@23 {
		compatible = "nxp,pca9555";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gsc>;
		interrupts = <4>;
	};

	eeprom@50 {
		compatible = "atmel,24c02";
		reg = <0x50>;
		pagesize = <16>;
	};

	eeprom@51 {
		compatible = "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
	};

	eeprom@52 {
		compatible = "atmel,24c02";
		reg = <0x52>;
		pagesize = <16>;
	};

	eeprom@53 {
		compatible = "atmel,24c02";
		reg = <0x53>;
		pagesize = <16>;
	};

	rtc@68 {
		compatible = "dallas,ds1672";
		reg = <0x68>;
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio3>;
		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
		rohm,reset-snvs-powered;
		#clock-cells = <0>;
		clocks = <&osc_32k 0>;
		clock-output-names = "clk-32k-out";

		regulators {
			/* vdd_soc: 0.805-0.900V (typ=0.8V) */
			BUCK1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			/* vdd_arm: 0.805-1.0V (typ=0.9V) */
			BUCK2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <900000>;
			};

			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
			BUCK3 {
				regulator-name = "buck3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_3p3 */
			BUCK4 {
				regulator-name = "buck4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_1p8 */
			BUCK5 {
				regulator-name = "buck5";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_dram */
			BUCK6 {
				regulator-name = "buck6";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* nvcc_snvs_1p8 */
			LDO1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <1900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_snvs_0p8 */
			LDO2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdda_1p8 */
			LDO3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO6 {
				regulator-name = "ldo6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	leds_gpio: gpio@20 {
		compatible = "nxp,pca9555";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	switch: switch@5f {
		compatible = "microchip,ksz9897";
		reg = <0x5f>;
		pinctrl-0 = <&pinctrl_ksz>;
		interrupt-parent = <&gpio4>;
		interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
		phy-mode = "rgmii-id";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			lan1: port@0 {
				reg = <0>;
				label = "lan1";
				phy-mode = "internal";
				local-mac-address = [00 00 00 00 00 00];
			};

			lan2: port@1 {
				reg = <1>;
				label = "lan2";
				phy-mode = "internal";
				local-mac-address = [00 00 00 00 00 00];
			};

			lan3: port@2 {
				reg = <2>;
				label = "lan3";
				phy-mode = "internal";
				local-mac-address = [00 00 00 00 00 00];
			};

			lan4: port@3 {
				reg = <3>;
				label = "lan4";
				phy-mode = "internal";
				local-mac-address = [00 00 00 00 00 00];
			};

			port@5 {
				reg = <5>;
				label = "cpu";
				ethernet = <&fec1>;
				phy-mode = "rgmii-id";

				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};
		};
	};

	crypto@60 {
		compatible = "atmel,atecc508a";
		reg = <0x60>;
	};
};

&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,clkreq-unsupported;
	clocks = <&pcie0_refclk>;
	clock-names = "ref";
	status = "okay";
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_250M>;
	status = "okay";
};

&pgc_gpu {
	status = "disabled";
};

&pgc_gpumix {
	status = "disabled";
};

&pgc_mipi {
	status = "disabled";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
	rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
	cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
	dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
	dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
	dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";
};

/* console */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
	cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
	rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
	cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
	rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";
};

&usbotg1 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	vbus-supply = <&reg_usb2_vbus>;
	status = "okay";
};

/* SDIO WiFi */
&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	bus-width = <4>;
	non-removable;
	vmmc-supply = <&reg_wifi>;
	status = "okay";
};

/* microSD */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* DIG2_OUT */
			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* DIG2_IN */
			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* DIG1_IN */
			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIG1_OUT */
			MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30	0x40000041 /* SIM2DET# */
			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29	0x40000041 /* SIM1DET# */
			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* SIM2SEL */
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x19 /* IRQ# */
			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x19 /* RST# */
		>;
	};

	pinctrl_gsc: gscgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16	0x159
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
		>;
	};

	pinctrl_i2c4_gpio: i2c4gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20	0x400001c3
			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x400001c3
		>;
	};

	pinctrl_ksz: kszgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18	0x41
			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19	0x41 /* RST# */
		>;
	};

	pinctrl_pcie0: pciegrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31	0x40000041 /* WDIS# */
			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x41
		>;
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x41
		>;
	};

	pinctrl_reg_isouart: regisouartgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041
		>;
	};

	pinctrl_reg_ioexp: regioexpgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041
		>;
	};

	pinctrl_reg_wl: regwlgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x40000041
		>;
	};

	pinctrl_reg_usb2: regusb1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x41
			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17	0x140
			MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC	0x140
		>;
	};

	pinctrl_spi1: spi1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82
			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82
			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82
			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x140
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1	0x140
			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x140
			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x140
			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x140
			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x140
		>;
	};

	pinctrl_uart1_gpio: uart1gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x40000041 /* RS422# */
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x40000041 /* RS485# */
			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x40000041 /* RS232# */
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9	0x140
			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10	0x140
		>;
	};

	pinctrl_uart3_gpio: uart3gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x40000110 /* RS232# */
			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000110 /* RS422# */
			MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8	0x40000110 /* RS485# */
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
			MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11	0x140
			MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12	0x140
		>;
	};

	pinctrl_uart4_gpio: uart4gpiogrp {
		fsl,pins = <

			MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10	0x40000041 /* RS232# */
			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40000041 /* RS422# */
			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* RS485# */
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2021 Gateworks Corporation
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>

#include "imx8mm.dtsi"

/ {
	model = "Gateworks Venice GW7902 i.MX8MM board";
	compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";

	aliases {
		ethernet1 = &eth1;
		usb0 = &usbotg1;
		usb1 = &usbotg2;
	};

	chosen {
		stdout-path = &uart2;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	can20m: can20m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <20000000>;
		clock-output-names = "can20m";
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-user-pb {
			label = "user_pb";
			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_0>;
		};

		key-user-pb1x {
			label = "user_pb1x";
			linux,code = <BTN_1>;
			interrupt-parent = <&gsc>;
			interrupts = <0>;
		};

		key-erased {
			label = "key_erased";
			linux,code = <BTN_2>;
			interrupt-parent = <&gsc>;
			interrupts = <1>;
		};

		key-eeprom-wp {
			label = "eeprom_wp";
			linux,code = <BTN_3>;
			interrupt-parent = <&gsc>;
			interrupts = <2>;
		};

		key-tamper {
			label = "tamper";
			linux,code = <BTN_4>;
			interrupt-parent = <&gsc>;
			interrupts = <5>;
		};

		switch-hold {
			label = "switch_hold";
			linux,code = <BTN_5>;
			interrupt-parent = <&gsc>;
			interrupts = <7>;
		};
	};

	led-controller {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led-0 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "panel1";
			gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-1 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "panel2";
			gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-2 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "panel3";
			gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-3 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "panel4";
			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-4 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "panel5";
			gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pps {
		compatible = "pps-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pps>;
		gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_usb1_vbus: regulator-usb1 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb1>;
		regulator-name = "usb_usb1_vbus";
		gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_wifi: regulator-wifi {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_wl>;
		regulator-name = "wifi";
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&A53_0 {
	cpu-supply = <&buck2>;
};

&A53_1 {
	cpu-supply = <&buck2>;
};

&A53_2 {
	cpu-supply = <&buck2>;
};

&A53_3 {
	cpu-supply = <&buck2>;
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi1>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	status = "okay";

	can@0 {
		compatible = "microchip,mcp2515";
		reg = <0>;
		clocks = <&can20m>;
		interrupt-parent = <&gpio2>;
		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
		spi-max-frequency = <10000000>;
	};
};

/* off-board header */
&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi2>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	local-mac-address = [00 00 00 00 00 00];
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		};
	};
};

&gpio1 {
	gpio-line-names = "", "", "", "", "", "", "", "",
		"m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio2 {
	gpio-line-names = "", "", "", "", "", "", "", "",
		"uart2_en#", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio3 {
	gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio4 {
	gpio-line-names = "", "", "", "", "", "", "", "",
		"", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
		"lte_pwr#", "lte_rst", "lte_int", "",
		"amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
		"", "uart1_term", "uart1_half", "app_gpio2",
		"mipi_gpio1", "", "", "";
};

&gpio5 {
	gpio-line-names = "", "", "", "mipi_gpio4",
		"mipi_gpio3", "mipi_gpio2", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	gsc: gsc@20 {
		compatible = "gw,gsc";
		reg = <0x20>;
		pinctrl-0 = <&pinctrl_gsc>;
		interrupt-parent = <&gpio2>;
		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <1>;

		adc {
			compatible = "gw,gsc-adc";
			#address-cells = <1>;
			#size-cells = <0>;

			channel@6 {
				gw,mode = <0>;
				reg = <0x06>;
				label = "temp";
			};

			channel@8 {
				gw,mode = <1>;
				reg = <0x08>;
				label = "vdd_bat";
			};

			channel@82 {
				gw,mode = <2>;
				reg = <0x82>;
				label = "vin";
				gw,voltage-divider-ohms = <22100 1000>;
				gw,voltage-offset-microvolt = <700000>;
			};

			channel@84 {
				gw,mode = <2>;
				reg = <0x84>;
				label = "vin_4p0";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@86 {
				gw,mode = <2>;
				reg = <0x86>;
				label = "vdd_3p3";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@88 {
				gw,mode = <2>;
				reg = <0x88>;
				label = "vdd_0p9";
			};

			channel@8c {
				gw,mode = <2>;
				reg = <0x8c>;
				label = "vdd_soc";
			};

			channel@8e {
				gw,mode = <2>;
				reg = <0x8e>;
				label = "vdd_arm";
			};

			channel@90 {
				gw,mode = <2>;
				reg = <0x90>;
				label = "vdd_1p8";
			};

			channel@92 {
				gw,mode = <2>;
				reg = <0x92>;
				label = "vdd_dram";
			};

			channel@98 {
				gw,mode = <2>;
				reg = <0x98>;
				label = "vdd_1p0";
			};

			channel@9a {
				gw,mode = <2>;
				reg = <0x9a>;
				label = "vdd_2p5";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@9c {
				gw,mode = <2>;
				reg = <0x9c>;
				label = "vdd_5p0";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@a2 {
				gw,mode = <2>;
				reg = <0xa2>;
				label = "vdd_gsc";
				gw,voltage-divider-ohms = <10000 10000>;
			};
		};
	};

	gpio: gpio@23 {
		compatible = "nxp,pca9555";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gsc>;
		interrupts = <4>;
	};

	pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio3>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		rohm,reset-snvs-powered;
		#clock-cells = <0>;
		clocks = <&osc_32k 0>;
		clock-output-names = "clk-32k-out";

		regulators {
			/* vdd_soc: 0.805-0.900V (typ=0.8V) */
			BUCK1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			/* vdd_arm: 0.805-1.0V (typ=0.9V) */
			buck2: BUCK2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <900000>;
			};

			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
			BUCK3 {
				regulator-name = "buck3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_3p3 */
			BUCK4 {
				regulator-name = "buck4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_1p8 */
			BUCK5 {
				regulator-name = "buck5";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_dram */
			BUCK6 {
				regulator-name = "buck6";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* nvcc_snvs_1p8 */
			LDO1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <1900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_snvs_0p8 */
			LDO2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdda_1p8 */
			LDO3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO6 {
				regulator-name = "ldo6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};

	eeprom@50 {
		compatible = "atmel,24c02";
		reg = <0x50>;
		pagesize = <16>;
	};

	eeprom@51 {
		compatible = "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
	};

	eeprom@52 {
		compatible = "atmel,24c02";
		reg = <0x52>;
		pagesize = <16>;
	};

	eeprom@53 {
		compatible = "atmel,24c02";
		reg = <0x53>;
		pagesize = <16>;
	};

	rtc@68 {
		compatible = "dallas,ds1672";
		reg = <0x68>;
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	accelerometer@19 {
		compatible = "st,lis2de12";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_accel>;
		reg = <0x19>;
		st,drdy-int-pin = <1>;
		interrupt-parent = <&gpio1>;
		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "INT1";
	};
};

/* off-board header */
&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

/* off-board header */
&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,clkreq-unsupported;
	clocks = <&pcie0_refclk>;
	clock-names = "ref";
	status = "okay";
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_250M>;
	status = "okay";

	pcie@0,0 {
		reg = <0x0000 0 0 0 0>;
		#address-cells = <1>;
		#size-cells = <0>;

		eth1: pcie@1,0 {
			reg = <0x0000 0 0 0 0>;
			#address-cells = <1>;
			#size-cells = <0>;

			local-mac-address = [00 00 00 00 00 00];
		};
	};
};

/* off-board header */
&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

/* RS232/RS485/RS422 selectable */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
	rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
	cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";
};

/* RS232 console */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

/* bluetooth HCI */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
	rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
	cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
		compatible = "brcm,bcm4330-bt";
		shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
	};
};

/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
	cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
	dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
	dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
	dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";
};

&usbotg1 {
	dr_mode = "host";
	vbus-supply = <&reg_usb1_vbus>;
	disable-over-current;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

/* SDIO WiFi */
&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	bus-width = <4>;
	non-removable;
	vmmc-supply = <&reg_wifi>;
	status = "okay";
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x40000159 /* M2_GDIS# */
			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x40000041 /* M2_PWR_EN */
			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041 /* M2_RESET */
			MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7	0x40000119 /* M2_OFF# */
			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x40000159 /* M2_WDIS# */
			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18       0x40000041 /* LTE_INT */
			MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17       0x40000041 /* LTE_RST# */
			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16       0x40000041 /* LTE_PWR */
			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14	0x40000041 /* AMP GPIO1 */
			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12	0x40000041 /* AMP GPIO2 */
			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11	0x40000041 /* AMP GPIO3 */
			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20	0x40000041 /* AMP_GPIO4 */
			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041 /* APP GPIO1 */
			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x40000041 /* VDD_4P0_EN */
			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* APP GPIO2 */
			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* UART2_EN# */
			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x40000041 /* MIPI_GPIO1 */
			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* MIPI_GPIO2 */
			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* MIPI_GPIO3/PWM2 */
			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* MIPI_GPIO4/PWM3 */
		>;
	};

	pinctrl_accel: accelgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x159
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19 /* RST# */
			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19 /* IRQ# */
		>;
	};

	pinctrl_gsc: gscgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x40
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
		>;
	};

	pinctrl_i2c4_gpio: i2c4gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20	0x400001c3
			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x400001c3
		>;
	};

	pinctrl_gpio_leds: gpioledgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21	0x19
			MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23	0x19
			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x19
			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x19
			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x19
		>;
	};

	pinctrl_pcie0: pciegrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x41
		>;
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41
		>;
	};

	pinctrl_pps: ppsgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x141 /* PPS */
		>;
	};

	pinctrl_reg_wl: regwlgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41 /* WLAN_WLON */
		>;
	};

	pinctrl_reg_usb1: regusb1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x41
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK	0xd6
			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK	0xd6
			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0	0xd6
			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC	0xd6
		>;
	};

	pinctrl_spi1: spi1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82
			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82
			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82
			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x40
			MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3	0x140 /* CAN_IRQ# */
		>;
	};

	pinctrl_spi2: spi2grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x82
			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x82
			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x82
			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40 /* SS0 */
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10	0x140 /* RTS */
			MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24	0x140 /* CTS */
		>;
	};

	pinctrl_uart1_gpio: uart1gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x40000110 /* HALF */
			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25	0x40000110 /* TERM */
			MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23	0x40000110 /* RS485 */
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_uart3_gpio: uart3_gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41 /* BT_EN# */
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
			MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x140 /* CTS */
			MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1		0x140 /* RTS */
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
			MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1		0x140 /* CTS */
			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x140 /* RTS */
			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3	0x140 /* DTR */
			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4	0x140 /* DSR */
			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x140 /* DCD */
			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x140 /* RI */
			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x140 /* GNSS_PPS */
			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x141 /* GNSS_GASP */
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
		>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Gateworks Corporation
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>

#include "imx8mm.dtsi"

/ {
	model = "Gateworks Venice GW7903 i.MX8MM board";
	compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";

	aliases {
		ethernet0 = &fec1;
		usb0 = &usbotg1;
	};

	chosen {
		stdout-path = &uart2;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-user-pb {
			label = "user_pb";
			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_0>;
		};

		key-user-pb1x {
			label = "user_pb1x";
			linux,code = <BTN_1>;
			interrupt-parent = <&gsc>;
			interrupts = <0>;
		};

		key-erased {
			label = "key_erased";
			linux,code = <BTN_2>;
			interrupt-parent = <&gsc>;
			interrupts = <1>;
		};

		key-eeprom-wp {
			label = "eeprom_wp";
			linux,code = <BTN_3>;
			interrupt-parent = <&gsc>;
			interrupts = <2>;
		};

		switch-hold {
			label = "switch_hold";
			linux,code = <BTN_5>;
			interrupt-parent = <&gsc>;
			interrupts = <7>;
		};
	};

	led-controller {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led-0 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led01_red";
			gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-1 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led01_grn";
			gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-2 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led02_red";
			gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-3 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led02_grn";
			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-4 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led03_red";
			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-5 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led03_grn";
			gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-6 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led04_red";
			gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-7 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led04_grn";
			gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-8 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led05_red";
			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-9 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led05_grn";
			gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-a {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led06_red";
			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led-b {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led06_grn";
			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};
};

&A53_0 {
	cpu-supply = <&buck2>;
};

&A53_1 {
	cpu-supply = <&buck2>;
};

&A53_2 {
	cpu-supply = <&buck2>;
};

&A53_3 {
	cpu-supply = <&buck2>;
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	local-mac-address = [00 00 00 00 00 00];
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			rx-internal-delay-ps = <2000>;
			tx-internal-delay-ps = <2500>;
		};
	};
};

&gpio1 {
	gpio-line-names = "", "", "", "", "", "", "", "",
		"", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio2 {
	gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "",
		"dig1_out#", "dig1_in", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio5 {
	gpio-line-names = "", "", "", "", "", "", "", "sim1_det#",
		"sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	gsc: gsc@20 {
		compatible = "gw,gsc";
		reg = <0x20>;
		pinctrl-0 = <&pinctrl_gsc>;
		interrupt-parent = <&gpio4>;
		interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <1>;

		adc {
			compatible = "gw,gsc-adc";
			#address-cells = <1>;
			#size-cells = <0>;

			channel@6 {
				gw,mode = <0>;
				reg = <0x06>;
				label = "temp";
			};

			channel@8 {
				gw,mode = <1>;
				reg = <0x08>;
				label = "vdd_bat";
			};

			channel@82 {
				gw,mode = <2>;
				reg = <0x82>;
				label = "vin";
				gw,voltage-divider-ohms = <22100 1000>;
				gw,voltage-offset-microvolt = <700000>;
			};

			channel@84 {
				gw,mode = <2>;
				reg = <0x84>;
				label = "vdd_5p0";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@86 {
				gw,mode = <2>;
				reg = <0x86>;
				label = "vdd_3p3";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@88 {
				gw,mode = <2>;
				reg = <0x88>;
				label = "vdd_0p9";
			};

			channel@8c {
				gw,mode = <2>;
				reg = <0x8c>;
				label = "vdd_soc";
			};

			channel@8e {
				gw,mode = <2>;
				reg = <0x8e>;
				label = "vdd_arm";
			};

			channel@90 {
				gw,mode = <2>;
				reg = <0x90>;
				label = "vdd_1p8";
			};

			channel@92 {
				gw,mode = <2>;
				reg = <0x92>;
				label = "vdd_dram";
			};

			channel@a2 {
				gw,mode = <2>;
				reg = <0xa2>;
				label = "vdd_gsc";
				gw,voltage-divider-ohms = <10000 10000>;
			};
		};
	};

	gpio: gpio@23 {
		compatible = "nxp,pca9555";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gsc>;
		interrupts = <4>;
	};

	eeprom@50 {
		compatible = "atmel,24c02";
		reg = <0x50>;
		pagesize = <16>;
	};

	eeprom@51 {
		compatible = "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
	};

	eeprom@52 {
		compatible = "atmel,24c02";
		reg = <0x52>;
		pagesize = <16>;
	};

	eeprom@53 {
		compatible = "atmel,24c02";
		reg = <0x53>;
		pagesize = <16>;
	};

	rtc@68 {
		compatible = "dallas,ds1672";
		reg = <0x68>;
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio3>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		rohm,reset-snvs-powered;
		#clock-cells = <0>;
		clocks = <&osc_32k 0>;
		clock-output-names = "clk-32k-out";

		regulators {
			/* vdd_soc: 0.805-0.900V (typ=0.8V) */
			BUCK1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			/* vdd_arm: 0.805-1.0V (typ=0.9V) */
			buck2: BUCK2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <900000>;
			};

			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
			BUCK3 {
				regulator-name = "buck3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_3p3 */
			BUCK4 {
				regulator-name = "buck4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_1p8 */
			BUCK5 {
				regulator-name = "buck5";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_dram */
			BUCK6 {
				regulator-name = "buck6";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* nvcc_snvs_1p8 */
			LDO1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <1900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_snvs_0p8 */
			LDO2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdda_1p8 */
			LDO3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO6 {
				regulator-name = "ldo6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	accelerometer@19 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_accel>;
		compatible = "st,lis2de12";
		reg = <0x19>;
		st,drdy-int-pin = <1>;
		interrupt-parent = <&gpio1>;
		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "INT1";
	};
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,clkreq-unsupported;
	clocks = <&pcie0_refclk>;
	clock-names = "ref";
	status = "okay";
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_250M>;
	status = "okay";
};

&pgc_mipi {
	status = "disabled";
};

/* off-board RS232/RS485/RS422 */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
	rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
	dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
	dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
	dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
	uart-has-rtscts;
	status = "okay";
};

/* console */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

/* microSD */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x40000041 /* RS422# */
			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x40000041 /* RS485# */
			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x40000041 /* RS232# */
			MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9	0x40000041 /* DIG1_IN */
			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* DIG1_OUT */
			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x40000041 /* DIG1_CTL */
			MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2	0x40000041 /* DIG2_CTL */
			MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x40000041 /* DIG2_IN */
			MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1		0x40000041 /* DIG2_OUT */
			MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7	0x40000041 /* SIM1DET# */
			MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8	0x40000041 /* SIM2DET# */
			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x40000041 /* SIM2SEL */
			MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12	0x40000041 /* PCI_WDIS# */
		>;
	};

	pinctrl_accel: accelgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x159
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24		0x19 /* IRQ# */
			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25		0x19 /* RST# */
		>;
	};

	pinctrl_gsc: gscgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x159
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3
		>;
	};

	pinctrl_gpio_leds: gpioledgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x19
			MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30	0x19
			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x19
			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x19
			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x19
			MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29	0x19
			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x19
			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x19
			MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31	0x19
			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x19
			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x19
		>;
	};

	pinctrl_pcie0: pciegrp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11	0x41
		>;
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x140
			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1	0x140
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x140
			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x140
			MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x140
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 Gateworks Corporation
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>

#include "imx8mm.dtsi"

/ {
	model = "Gateworks Venice GW7904 i.MX8MM board";
	compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";

	chosen {
		stdout-path = &uart2;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x0 0x40000000 0 0x80000000>;
	};

	gpio-keys {
		compatible = "gpio-keys";

		key-0 {
			label = "user_pb";
			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
			linux,code = <BTN_0>;
		};

		key-1 {
			label = "user_pb1x";
			linux,code = <BTN_1>;
			interrupt-parent = <&gsc>;
			interrupts = <0>;
		};

		key-2 {
			label = "key_erased";
			linux,code = <BTN_2>;
			interrupt-parent = <&gsc>;
			interrupts = <1>;
		};

		key-3 {
			label = "eeprom_wp";
			linux,code = <BTN_3>;
			interrupt-parent = <&gsc>;
			interrupts = <2>;
		};

		key-4 {
			label = "switch_hold";
			linux,code = <BTN_5>;
			interrupt-parent = <&gsc>;
			interrupts = <7>;
		};
	};

	led-controller {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led-0 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led01_grn";
			gpios = <&gpioled 0 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-1 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_YELLOW>;
			label = "led01_yel";
			gpios = <&gpioled 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-2 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led02_grn";
			gpios = <&gpioled 2 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-3 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_YELLOW>;
			label = "led02_yel";
			gpios = <&gpioled 3 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-4 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led03_grn";
			gpios = <&gpioled 4 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-5 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_YELLOW>;
			label = "led03_yel";
			gpios = <&gpioled 5 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-6 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led04_grn";
			gpios = <&gpioled 6 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-7 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_YELLOW>;
			label = "led04_yel";
			gpios = <&gpioled 7 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-8 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led05_grn";
			gpios = <&gpioled 8 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-9 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_YELLOW>;
			label = "led05_yel";
			gpios = <&gpioled 9 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-10 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led06_grn";
			gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-11 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led06_red";
			gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-12 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led07_grn";
			gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-13 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			label = "led07_red";
			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-14 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led08_grn";
			gpios = <&gpioled 10 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-15 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_YELLOW>;
			label = "led08_yel";
			gpios = <&gpioled 11 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-16 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led09_grn";
			gpios = <&gpioled 12 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-17 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_YELLOW>;
			label = "led09_yel";
			gpios = <&gpioled 13 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-18 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			label = "led10_grn";
			gpios = <&gpioled 14 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};

		led-19 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_YELLOW>;
			label = "led10_yel";
			gpios = <&gpioled 15 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};
};

&A53_0 {
	cpu-supply = <&buck2>;
};

&A53_1 {
	cpu-supply = <&buck2>;
};

&A53_2 {
	cpu-supply = <&buck2>;
};

&A53_3 {
	cpu-supply = <&buck2>;
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
		};
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	local-mac-address = [00 00 00 00 00 00];
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};
	};
};

&gpio1 {
	gpio-line-names = "", "", "", "", "", "", "", "",
		"", "", "", "", "rs232_en#", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio5 {
	gpio-line-names = "", "", "", "", "", "", "", "",
		"", "", "", "", "pci_wdis#", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	gsc: gsc@20 {
		compatible = "gw,gsc";
		reg = <0x20>;
		pinctrl-0 = <&pinctrl_gsc>;
		interrupt-parent = <&gpio4>;
		interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <1>;

		adc {
			compatible = "gw,gsc-adc";
			#address-cells = <1>;
			#size-cells = <0>;

			channel@6 {
				gw,mode = <0>;
				reg = <0x06>;
				label = "temp";
			};

			channel@82 {
				gw,mode = <2>;
				reg = <0x82>;
				label = "vin";
				gw,voltage-divider-ohms = <22100 1000>;
				gw,voltage-offset-microvolt = <700000>;
			};

			channel@84 {
				gw,mode = <2>;
				reg = <0x84>;
				label = "vdd_5p0";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@86 {
				gw,mode = <2>;
				reg = <0x86>;
				label = "vdd_3p3";
				gw,voltage-divider-ohms = <10000 10000>;
			};

			channel@88 {
				gw,mode = <2>;
				reg = <0x88>;
				label = "vdd_0p9";
			};

			channel@8c {
				gw,mode = <2>;
				reg = <0x8c>;
				label = "vdd_soc";
			};

			channel@8e {
				gw,mode = <2>;
				reg = <0x8e>;
				label = "vdd_arm";
			};

			channel@90 {
				gw,mode = <2>;
				reg = <0x90>;
				label = "vdd_1p8";
			};

			channel@92 {
				gw,mode = <2>;
				reg = <0x92>;
				label = "vdd_dram";
			};

			channel@a2 {
				gw,mode = <2>;
				reg = <0xa2>;
				label = "vdd_gsc";
				gw,voltage-divider-ohms = <10000 10000>;
			};
		};
	};

	gpio: gpio@23 {
		compatible = "nxp,pca9555";
		reg = <0x23>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&gsc>;
		interrupts = <4>;
	};

	eeprom@50 {
		compatible = "atmel,24c02";
		reg = <0x50>;
		pagesize = <16>;
	};

	eeprom@51 {
		compatible = "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
	};

	eeprom@52 {
		compatible = "atmel,24c02";
		reg = <0x52>;
		pagesize = <16>;
	};

	eeprom@53 {
		compatible = "atmel,24c02";
		reg = <0x53>;
		pagesize = <16>;
	};

	rtc@68 {
		compatible = "dallas,ds1672";
		reg = <0x68>;
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio3>;
		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
		rohm,reset-snvs-powered;
		#clock-cells = <0>;
		clocks = <&osc_32k 0>;
		clock-output-names = "clk-32k-out";

		regulators {
			/* vdd_soc: 0.805-0.900V (typ=0.8V) */
			BUCK1 {
				regulator-name = "buck1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			/* vdd_arm: 0.805-1.0V (typ=0.9V) */
			buck2: BUCK2 {
				regulator-name = "buck2";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <900000>;
			};

			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
			BUCK3 {
				regulator-name = "buck3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_3p3 */
			BUCK4 {
				regulator-name = "buck4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_1p8 */
			BUCK5 {
				regulator-name = "buck5";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_dram */
			BUCK6 {
				regulator-name = "buck6";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* nvcc_snvs_1p8 */
			LDO1 {
				regulator-name = "ldo1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <1900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdd_snvs_0p8 */
			LDO2 {
				regulator-name = "ldo2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			/* vdda_1p8 */
			LDO3 {
				regulator-name = "ldo3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO4 {
				regulator-name = "ldo4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			LDO6 {
				regulator-name = "ldo6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c3>;
	pinctrl-1 = <&pinctrl_i2c3_gpio>;
	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	accelerometer@19 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_accel>;
		compatible = "st,lis2de12";
		reg = <0x19>;
		st,drdy-int-pin = <1>;
		interrupt-parent = <&gpio1>;
		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "INT1";
	};
};

&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	gpioled: gpio@27 {
		compatible = "nxp,pca9555";
		reg = <0x27>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,clkreq-unsupported;
	clocks = <&pcie0_refclk>;
	clock-names = "ref";
	status = "okay";
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_250M>;
	status = "okay";
};

&pgc_mipi {
	status = "disabled";
};

/* off-board RS232 */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* console */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

/* off-board RS232 */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

/* microSD */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
};

/* eMMC */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x40000041 /* RS232# */
			MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12	0x40000041 /* PCI_WDIS# */
		>;
	};

	pinctrl_accel: accelgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x159
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24		0x19 /* IRQ# */
			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25		0x19 /* RST# */
		>;
	};

	pinctrl_gpio_leds: gpioledsgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x40000019
			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x40000019
			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x40000019
			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x40000019
		>;
	};

	pinctrl_gsc: gscgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x159
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
		>;
	};

	pinctrl_i2c1_gpio: i2c1gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16	0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17	0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18	0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19	0x400001c3
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
		>;
	};

	pinctrl_i2c4_gpio: i2c4gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20	0x400001c3
			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0x400001c3
		>;
	};

	pinctrl_pcie0: pciegrp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11	0x41
		>;
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
		>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

/ {
	sound_card: sound-card {
		compatible = "simple-audio-card";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,format = "i2s";
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,name = "imx8mm-wm8904";
		simple-audio-card,routing =
			"Headphone Jack", "HPOUTL",
			"Headphone Jack", "HPOUTR",
			"IN2L", "Line In Jack",
			"IN2R", "Line In Jack",
			"Headphone Jack", "MICBIAS",
			"IN1L", "Headphone Jack";
		simple-audio-card,widgets =
			"Microphone", "Headphone Jack",
			"Headphone", "Headphone Jack",
			"Line", "Line In Jack";

		dailink_master: simple-audio-card,codec {
			clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
			sound-dai = <&wm8904_1a>;
		};

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};
	};
};

/* Verdin SPI_1 */
&ecspi2 {
	status = "okay";
};

/* EEPROM on display adapter boards */
&eeprom_display_adapter {
	status = "okay";
};

/* EEPROM on Verdin Development board */
&eeprom_carrier_board {
	status = "okay";
};

&fec1 {
	status = "okay";
};

/* Verdin QSPI_1 */
&flexspi {
	status = "okay";
};

/* Current measurement into module VCC */
&hwmon {
	status = "okay";
};

&hwmon_temp {
	vs-supply = <&reg_1p8v>;
	status = "okay";
};

&i2c3 {
	status = "okay";
};

/* Verdin I2C_1 */
&i2c4 {
	status = "okay";

	/* Audio Codec */
	wm8904_1a: audio-codec@1a {
		compatible = "wlf,wm8904";
		AVDD-supply = <&reg_3p3v>;
		clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
		clock-names = "mclk";
		CPVDD-supply = <&reg_3p3v>;
		DBVDD-supply = <&reg_3p3v>;
		DCVDD-supply = <&reg_3p3v>;
		MICVDD-supply = <&reg_3p3v>;
		reg = <0x1a>;
		#sound-dai-cells = <0>;
	};
};

/* Verdin PCIE_1 */
&pcie0 {
	status = "okay";
};

&pcie_phy {
	status = "okay";
};

/* Verdin PWM_3_DSI */
&pwm1 {
	status = "okay";
};

/* Verdin PWM_1 */
&pwm2 {
	status = "okay";
};

/* Verdin PWM_2 */
&pwm3 {
	status = "okay";
};

/* Verdin I2S_1 */
&sai2 {
	status = "okay";
};

/* Verdin UART_3 */
&uart1 {
	status = "okay";
};

/* Verdin UART_1 */
&uart2 {
	status = "okay";
};

/* Verdin UART_2 */
&uart3 {
	status = "okay";
};

/* Verdin USB_1 */
&usbotg1 {
	status = "okay";
};

/* Verdin USB_2 */
&usbotg2 {
	status = "okay";
};

/* Verdin SD_1 */
&usdhc2 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

#include "imx8mm-verdin-dahlia.dtsi"

/ {
	sound_card: sound-card {
		compatible = "simple-audio-card";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,format = "i2s";
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,name = "imx8mm-nau8822";
		simple-audio-card,routing =
			"Headphones", "LHP",
			"Headphones", "RHP",
			"Speaker", "LSPK",
			"Speaker", "RSPK",
			"Line Out", "AUXOUT1",
			"Line Out", "AUXOUT2",
			"LAUX", "Line In",
			"RAUX", "Line In",
			"LMICP", "Mic In",
			"RMICP", "Mic In";
		simple-audio-card,widgets =
			"Headphones", "Headphones",
			"Line Out", "Line Out",
			"Speaker", "Speaker",
			"Microphone", "Mic In",
			"Line", "Line In";

		dailink_master: simple-audio-card,codec {
			clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
			sound-dai = <&nau8822_1a>;
		};

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};
	};
};

&gpio_expander_21 {
	status = "okay";
};

/* Verdin I2C_1 */
&i2c4 {
	/* Audio Codec */
	nau8822_1a: audio-codec@1a {
		compatible = "nuvoton,nau8822";
		reg = <0x1a>;
	};
};

/* Verdin UART_1, connector X50 through RS485 transceiver */
&uart2 {
	linux,rs485-enabled-at-boot-time;
	rs485-rts-active-low;
	rs485-rx-during-tx;
};

/* Limit frequency on dev board due to long traces and bad signal integrity */
&usdhc2 {
	max-frequency = <100000000>;
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

/dts-v1/;

#include "imx8mm-verdin.dtsi"
#include "imx8mm-verdin-nonwifi.dtsi"
#include "imx8mm-verdin-dahlia.dtsi"

/ {
	model = "Toradex Verdin iMX8M Mini on Dahlia Board";
	compatible = "toradex,verdin-imx8mm-nonwifi-dahlia",
		     "toradex,verdin-imx8mm-nonwifi",
		     "toradex,verdin-imx8mm",
		     "fsl,imx8mm";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

/dts-v1/;

#include "imx8mm-verdin.dtsi"
#include "imx8mm-verdin-nonwifi.dtsi"
#include "imx8mm-verdin-dev.dtsi"

/ {
	model = "Toradex Verdin iMX8M Mini on Verdin Development Board";
	compatible = "toradex,verdin-imx8mm-nonwifi-dev",
		     "toradex,verdin-imx8mm-nonwifi",
		     "toradex,verdin-imx8mm",
		     "fsl,imx8mm";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

&gpio3 {
	gpio-line-names = "SODIMM_52",
			  "SODIMM_54",
			  "SODIMM_64",
			  "SODIMM_21",
			  "SODIMM_206",
			  "SODIMM_76",
			  "SODIMM_56",
			  "SODIMM_58",
			  "SODIMM_60",
			  "SODIMM_62",
			  "SODIMM_162",
			  "SODIMM_164",
			  "SODIMM_166",
			  "SODIMM_168",
			  "SODIMM_66",
			  "SODIMM_17",
			  "",
			  "SODIMM_156",
			  "SODIMM_160",
			  "SODIMM_244",
			  "",
			  "SODIMM_48",
			  "SODIMM_44",
			  "SODIMM_42",
			  "SODIMM_46";
};

&gpio4 {
	gpio-line-names = "SODIMM_102",
			  "SODIMM_90",
			  "SODIMM_92",
			  "SODIMM_94",
			  "SODIMM_96",
			  "SODIMM_100",
			  "SODIMM_148",
			  "SODIMM_152",
			  "SODIMM_154",
			  "SODIMM_174",
			  "SODIMM_120",
			  "SODIMM_104",
			  "SODIMM_106",
			  "SODIMM_108",
			  "SODIMM_112",
			  "SODIMM_114",
			  "SODIMM_116",
			  "SODIMM_150",
			  "SODIMM_118",
			  "",
			  "SODIMM_88",
			  "SODIMM_149",
			  "SODIMM_147",
			  "SODIMM_36",
			  "SODIMM_32",
			  "SODIMM_30",
			  "SODIMM_34",
			  "SODIMM_38",
			  "SODIMM_252",
			  "SODIMM_133",
			  "SODIMM_135",
			  "SODIMM_129";
};

&usdhc3 {
	bus-width = <4>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

/dts-v1/;

#include "imx8mm-verdin.dtsi"
#include "imx8mm-verdin-wifi.dtsi"
#include "imx8mm-verdin-dahlia.dtsi"

/ {
	model = "Toradex Verdin iMX8M Mini WB on Dahlia Board";
	compatible = "toradex,verdin-imx8mm-wifi-dahlia",
		     "toradex,verdin-imx8mm-wifi",
		     "toradex,verdin-imx8mm",
		     "fsl,imx8mm";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

/dts-v1/;

#include "imx8mm-verdin.dtsi"
#include "imx8mm-verdin-wifi.dtsi"
#include "imx8mm-verdin-dev.dtsi"

/ {
	model = "Toradex Verdin iMX8M Mini WB on Verdin Development Board";
	compatible = "toradex,verdin-imx8mm-wifi-dev",
		     "toradex,verdin-imx8mm-wifi",
		     "toradex,verdin-imx8mm",
		     "fsl,imx8mm";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2022 Toradex
 */

/ {
	reg_wifi_en: regulator-wifi-en {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_wifi_pwr_en>;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "PDn_AW-CM276NF";
		startup-delay-us = <2000>;
	};
};

&gpio3 {
	gpio-line-names = "SODIMM_52",
			  "SODIMM_54",
			  "SODIMM_64",
			  "SODIMM_21",
			  "SODIMM_206",
			  "SODIMM_76",
			  "SODIMM_56",
			  "SODIMM_58",
			  "SODIMM_60",
			  "SODIMM_62",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_66",
			  "SODIMM_17",
			  "",
			  "",
			  "",
			  "SODIMM_244",
			  "",
			  "SODIMM_48",
			  "SODIMM_44",
			  "SODIMM_42",
			  "SODIMM_46";
};

&gpio4 {
	gpio-line-names = "SODIMM_102",
			  "SODIMM_90",
			  "SODIMM_92",
			  "SODIMM_94",
			  "SODIMM_96",
			  "SODIMM_100",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_120",
			  "SODIMM_104",
			  "SODIMM_106",
			  "SODIMM_108",
			  "SODIMM_112",
			  "SODIMM_114",
			  "SODIMM_116",
			  "",
			  "SODIMM_118",
			  "",
			  "SODIMM_88",
			  "SODIMM_149",
			  "SODIMM_147",
			  "SODIMM_36",
			  "SODIMM_32",
			  "SODIMM_30",
			  "SODIMM_34",
			  "SODIMM_38",
			  "SODIMM_252",
			  "SODIMM_133",
			  "SODIMM_135",
			  "SODIMM_129";
};

/* On-module Wi-Fi */
&usdhc3 {
	bus-width = <4>;
	keep-power-in-suspend;
	non-removable;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
	vmmc-supply = <&reg_wifi_en>;
	status = "okay";
};