code:
* Mediatek Media Data Path

Media Data Path is used for scaling and color space conversion.

Required properties (controller node):
- compatible: "mediatek,mt8173-mdp"
- mediatek,vpu: the node of video processor unit, see
  Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.

Required properties (all function blocks, child node):
- compatible: Should be one of
        "mediatek,mt8173-mdp-rdma"  - read DMA
        "mediatek,mt8173-mdp-rsz"   - resizer
        "mediatek,mt8173-mdp-wdma"  - write DMA
        "mediatek,mt8173-mdp-wrot"  - write DMA with rotation
- reg: Physical base address and length of the function block register space
- clocks: device clocks, see
  Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- power-domains: a phandle to the power domain, see
  Documentation/devicetree/bindings/power/power_domain.txt for details.

Required properties (DMA function blocks, child node):
- compatible: Should be one of
        "mediatek,mt8173-mdp-rdma"
        "mediatek,mt8173-mdp-wdma"
        "mediatek,mt8173-mdp-wrot"
- iommus: should point to the respective IOMMU block with master port as
  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
  for details.

Example:
	mdp_rdma0: rdma@14001000 {
		compatible = "mediatek,mt8173-mdp-rdma";
			     "mediatek,mt8173-mdp";
		reg = <0 0x14001000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_RDMA0>,
			 <&mmsys CLK_MM_MUTEX_32K>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		iommus = <&iommu M4U_PORT_MDP_RDMA0>;
		mediatek,vpu = <&vpu>;
	};

	mdp_rdma1: rdma@14002000 {
		compatible = "mediatek,mt8173-mdp-rdma";
		reg = <0 0x14002000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_RDMA1>,
			 <&mmsys CLK_MM_MUTEX_32K>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		iommus = <&iommu M4U_PORT_MDP_RDMA1>;
	};

	mdp_rsz0: rsz@14003000 {
		compatible = "mediatek,mt8173-mdp-rsz";
		reg = <0 0x14003000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_RSZ0>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	};

	mdp_rsz1: rsz@14004000 {
		compatible = "mediatek,mt8173-mdp-rsz";
		reg = <0 0x14004000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_RSZ1>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	};

	mdp_rsz2: rsz@14005000 {
		compatible = "mediatek,mt8173-mdp-rsz";
		reg = <0 0x14005000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_RSZ2>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
	};

	mdp_wdma0: wdma@14006000 {
		compatible = "mediatek,mt8173-mdp-wdma";
		reg = <0 0x14006000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_WDMA>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		iommus = <&iommu M4U_PORT_MDP_WDMA>;
	};

	mdp_wrot0: wrot@14007000 {
		compatible = "mediatek,mt8173-mdp-wrot";
		reg = <0 0x14007000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_WROT0>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		iommus = <&iommu M4U_PORT_MDP_WROT0>;
	};

	mdp_wrot1: wrot@14008000 {
		compatible = "mediatek,mt8173-mdp-wrot";
		reg = <0 0x14008000 0 0x1000>;
		clocks = <&mmsys CLK_MM_MDP_WROT1>;
		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
		iommus = <&iommu M4U_PORT_MDP_WROT1>;
	};


code:
* Mediatek Video Processor Unit

Video Processor Unit is a HW video controller. It controls HW Codec including
H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert).

Required properties:
  - compatible: "mediatek,mt8173-vpu"
  - reg: Must contain an entry for each entry in reg-names.
  - reg-names: Must include the following entries:
    "tcm": tcm base
    "cfg_reg": Main configuration registers base
  - interrupts: interrupt number to the cpu.
  - clocks : clock name from clock manager
  - clock-names: must be main. It is the main clock of VPU

Optional properties:
  - memory-region: phandle to a node describing memory (see
    Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
    to be used for VPU extended memory; if not present, VPU may be located
    anywhere in the memory

Example:
	vpu: vpu@10020000 {
		compatible = "mediatek,mt8173-vpu";
		reg = <0 0x10020000 0 0x30000>,
		      <0 0x10050000 0 0x100>;
		reg-names = "tcm", "cfg_reg";
		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen TOP_SCP_SEL>;
		clock-names = "main";
	};

repo_name: angery/linux


code:
* Amlogic Meson IR remote control receiver

Required properties:
 - compatible	: depending on the platform this should be one of:
		  - "amlogic,meson6-ir"
		  - "amlogic,meson8b-ir"
		  - "amlogic,meson-gxbb-ir"
 - reg		: physical base address and length of the device registers
 - interrupts	: a single specifier for the interrupt from the device

Optional properties:
 - linux,rc-map-name:	see rc.txt file in the same directory.

Example:

	ir-receiver@c8100480 {
		compatible= "amlogic,meson6-ir";
		reg = <0xc8100480 0x20>;
		interrupts = <0 15 1>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/microchip,csi2dc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip CSI2 Demux Controller (CSI2DC)

maintainers:
  - Eugen Hristev <eugen.hristev@microchip.com>

description:
  CSI2DC - Camera Serial Interface 2 Demux Controller

  CSI2DC is a hardware block that receives incoming data from either from an
  IDI interface or from a parallel bus interface.
  It filters IDI packets based on their data type and virtual channel
  identifier, then converts the byte stream to a pixel stream into a cross
  clock domain towards a parallel interface that can be read by a sensor
  controller.
  IDI interface is Synopsys proprietary.
  CSI2DC can act a simple bypass bridge if the incoming data is coming from
  a parallel interface.

  CSI2DC provides two pipes, one video pipe and one data pipe. Video pipe
  is connected at the output to a sensor controller and the data pipe is
  accessible as a DMA slave port to a DMA controller.

  CSI2DC supports a single 'port' node as a sink port with either Synopsys
  32-bit IDI interface or a parallel interface.

  CSI2DC supports one 'port' node as source port with parallel interface.
  This is called video pipe.
  This port has an 'endpoint' that can be connected to a sink port of another
  controller (next in pipeline).

  CSI2DC also supports direct access to the data through AHB, via DMA channel,
  called data pipe.
  For data pipe to be available, a dma controller and a dma channel must be
  referenced.

properties:
  compatible:
    const: microchip,sama7g5-csi2dc

  reg:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 2

  clock-names:
    description:
      CSI2DC must have two clocks to function correctly. One clock is the
      peripheral clock for the inside functionality of the hardware block.
      This is named 'pclk'. The second clock must be the cross domain clock,
      in which CSI2DC will perform clock crossing. This clock must be fed
      by the next controller in pipeline, which usually is a sensor controller.
      Normally this clock should be given by this sensor controller who
      is also a clock source. This clock is named 'scck', sensor controller clock.
    items:
      - const: pclk
      - const: scck

  dmas:
    maxItems: 1

  dma-names:
    const: rx

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port node, single endpoint describing the input port.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false
            description: Endpoint connected to input device

            properties:
              bus-type:
                enum: [4, 5, 6]
                default: 4

              bus-width:
                enum: [8, 9, 10, 11, 12, 13, 14]
                default: 14

              clock-noncontinuous:
                type: boolean
                description:
                  Presence of this boolean property decides whether clock is
                  continuous or noncontinuous.

              remote-endpoint: true

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Output port node, single endpoint describing the output port.

        properties:
          endpoint:
            unevaluatedProperties: false
            $ref: video-interfaces.yaml#
            description: Endpoint connected to output device

            properties:
              bus-type:
                enum: [5, 6]
                default: 5

              bus-width:
                enum: [8, 9, 10, 11, 12, 13, 14]
                default: 14

              remote-endpoint: true

    required:
      - port@0
      - port@1

additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - ports

examples:
  # Example for connecting to a parallel sensor controller block (video pipe)
  # and the input is received from Synopsys IDI interface
  - |
    csi2dc@e1404000 {
        compatible = "microchip,sama7g5-csi2dc";
        reg = <0xe1404000 0x500>;
        clocks = <&pclk>, <&scck>;
        clock-names = "pclk", "scck";

        ports {
               #address-cells = <1>;
               #size-cells = <0>;
               port@0 {
                       reg = <0>; /* must be 0, first child port */
                       csi2dc_in: endpoint { /* input from IDI interface */
                               bus-type = <4>; /* MIPI CSI2 D-PHY */
                               remote-endpoint = <&csi2host_out>;
                       };
               };

               port@1 {
                       reg = <1>; /* must be 1, second child port */
                       csi2dc_out: endpoint {
                               remote-endpoint = <&xisc_in>; /* output to sensor controller */
                       };
               };
        };
    };

  # Example for connecting to a DMA master as an AHB slave
  # and the input is received from Synopsys IDI interface
  - |
    #include <dt-bindings/dma/at91.h>
    csi2dc@e1404000 {
        compatible = "microchip,sama7g5-csi2dc";
        reg = <0xe1404000 0x500>;
        clocks = <&pclk>, <&scck>;
        clock-names = "pclk", "scck";
        dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>;
        dma-names = "rx";

        ports {
               #address-cells = <1>;
               #size-cells = <0>;
               port@0 {
                       reg = <0>; /* must be 0, first child port */
                       csi2dc_input: endpoint { /* input from IDI interface */
                               remote-endpoint = <&csi2host_out>;
                       };
               };

               port@1 {
                       reg = <1>;
               };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/microchip,sama5d4-vdec.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Hantro G1 VPU codec implemented on Microchip SAMA5D4 SoCs

maintainers:
  - Emil Velikov <emil.velikov@collabora.com>

description:
  Hantro G1 video decode accelerator present on Microchip SAMA5D4 SoCs.

properties:
  compatible:
    const: microchip,sama5d4-vdec

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
        #include <dt-bindings/clock/at91.h>
        #include <dt-bindings/interrupt-controller/irq.h>

        vdec0: vdec@300000 {
                compatible = "microchip,sama5d4-vdec";
                reg = <0x00300000 0x100000>;
                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
                clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
        };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2021 Microchip Technology, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/microchip,xisc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip eXtended Image Sensor Controller (XISC)

maintainers:
  - Eugen Hristev <eugen.hristev@microchip.com>

description: |
  The eXtended Image Sensor Controller (XISC) device provides the video input capabilities for the
  Microchip AT91 SAM family of devices.

  The XISC has a single internal parallel input that supports RAW Bayer, RGB or YUV video.
  The source can be either a demuxer from a CSI2 type of bus, or a simple direct bridge to a
  parallel sensor.

  The XISC provides one clock output that is used to clock the demuxer/bridge.

properties:
  compatible:
    const: microchip,sama7g5-isc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: hclock

  '#clock-cells':
    const: 0

  clock-output-names:
    const: isc-mck

  microchip,mipi-mode:
    type: boolean
    description:
      As the XISC is usually connected to a demux/bridge, the XISC receives
      the same type of input, however, it should be aware of the type of
      signals received. The mipi-mode enables different internal handling
      of the data and clock lines.

  port:
    $ref: /schemas/graph.yaml#/$defs/port-base
    description:
      Input port node, single endpoint describing the input pad.

    properties:
      endpoint:
        $ref: video-interfaces.yaml#

        properties:
          bus-type:
            enum: [5, 6]

          remote-endpoint: true

          bus-width:
            enum: [8, 9, 10, 11, 12, 14]
            default: 12

          hsync-active:
            enum: [0, 1]
            default: 1

          vsync-active:
            enum: [0, 1]
            default: 1

          pclk-sample:
            enum: [0, 1]
            default: 1

        required:
          - remote-endpoint
          - bus-type

        additionalProperties: false

    additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - clock-output-names
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/at91.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/media/video-interfaces.h>

    xisc: xisc@e1408000 {
        compatible = "microchip,sama7g5-isc";
        reg = <0xe1408000 0x2000>;
        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&pmc PMC_TYPE_PERIPHERAL 56>;
        clock-names = "hclock";
        #clock-cells = <0>;
        clock-output-names = "isc-mck";

        port {
                xisc_in: endpoint {
                       bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
                       remote-endpoint = <&csi2dc_out>;
                       hsync-active = <1>;
                       vsync-active = <1>;
                       bus-width = <12>;
                };
        };
    };


code:
Device-Tree bindings for Mediatek consumer IR controller
found in Mediatek SoC family

Required properties:
- compatible	    : Should be
			"mediatek,mt7623-cir": for MT7623 SoC
			"mediatek,mt7622-cir": for MT7622 SoC
- clocks	    : list of clock specifiers, corresponding to
		      entries in clock-names property;
- clock-names	    : should contain
			- "clk" entries: for MT7623 SoC
			- "clk", "bus" entries: for MT7622 SoC
- interrupts	    : should contain IR IRQ number;
- reg		    : should contain IO map address for IR.

Optional properties:
- linux,rc-map-name : see rc.txt file in the same directory.

Example:

cir: cir@10013000 {
	compatible = "mediatek,mt7623-cir";
	reg = <0 0x10013000 0 0x1000>;
	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_IRRX>;
	clock-names = "clk";
	linux,rc-map-name = "rc-rc6-mce";
};


code:
Device-Tree bindings for LIRC TX driver for Nokia N900(RX51)

Required properties:
	- compatible: should be "nokia,n900-ir".
	- pwms: specifies PWM used for IR signal transmission.

Example node:

	pwm9: dmtimer-pwm@9 {
		compatible = "ti,omap-dmtimer-pwm";
		ti,timers = <&timer9>;
		ti,clock-source = <0x00>; /* timer_sys_ck */
		#pwm-cells = <3>;
	};

	ir: n900-ir {
		compatible = "nokia,n900-ir";

		pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra Video Decoder Engine

maintainers:
  - Dmitry Osipenko <digetx@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - nvidia,tegra132-vde
              - nvidia,tegra124-vde
              - nvidia,tegra114-vde
      - items:
          - const: nvidia,tegra30-vde
          - const: nvidia,tegra20-vde
      - items:
          - const: nvidia,tegra20-vde

  reg:
    maxItems: 9

  reg-names:
    items:
      - const: sxe
      - const: bsev
      - const: mbe
      - const: ppe
      - const: mce
      - const: tfe
      - const: ppb
      - const: vdma
      - const: frameid

  clocks:
    maxItems: 1

  resets:
    maxItems: 2

  reset-names:
    items:
      - const: vde
      - const: mc

  interrupts:
    maxItems: 3

  interrupt-names:
    items:
      - const: sync-token
      - const: bsev
      - const: sxe

  iommus:
    maxItems: 1

  iram:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle of the SRAM MMIO node.

  operating-points-v2:
    description:
      Should contain freqs and voltages and opp-supported-hw property,
      which is a bitfield indicating SoC speedo or process ID mask.

  power-domains:
    maxItems: 1
    description:
      Phandle to the SoC core power domain.

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - resets
  - reset-names
  - interrupts
  - interrupt-names

additionalProperties: false

examples:
  - |
    video-codec@6001a000 {
      compatible = "nvidia,tegra20-vde";
      reg = <0x6001a000 0x1000>, /* Syntax Engine */
            <0x6001b000 0x1000>, /* Video Bitstream Engine */
            <0x6001c000  0x100>, /* Macroblock Engine */
            <0x6001c200  0x100>, /* Post-processing Engine */
            <0x6001c400  0x100>, /* Motion Compensation Engine */
            <0x6001c600  0x100>, /* Transform Engine */
            <0x6001c800  0x100>, /* Pixel prediction block */
            <0x6001ca00  0x100>, /* Video DMA */
            <0x6001d800  0x300>; /* Video frame controls */
      reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
                  "tfe", "ppb", "vdma", "frameid";
      iram = <&iram>; /* IRAM MMIO region */
      interrupts = <0  9 4>, /* Sync token */
                   <0 10 4>, /* BSE-V */
                   <0 12 4>; /* SXE */
      interrupt-names = "sync-token", "bsev", "sxe";
      clocks = <&clk 61>;
      reset-names = "vde", "mc";
      resets = <&rst 61>, <&mem 13>;
      iommus = <&mem 15>;
      operating-points-v2 = <&dvfs_opp_table>;
      power-domains = <&domain>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nxp,dw100.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8MP DW100 Dewarper core

maintainers:
  - Xavier Roumegue <xavier.roumegue@oss.nxp.com>

description: |-
  The Dewarp Engine provides high-performance dewarp processing for the
  correction of the distortion that is introduced in images produced by fisheye
  and wide angle lenses. It is implemented with a line/tile-cache based
  architecture. With configurable address mapping look up tables and per tile
  processing, it successfully generates a corrected output image.
  The engine can be used to perform scaling, cropping and pixel format
  conversion.

properties:
  compatible:
    enum:
      - nxp,imx8mp-dw100

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: The AXI clock
      - description: The AHB clock

  clock-names:
    items:
      - const: axi
      - const: ahb

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mp-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/imx8mp-power.h>

    dewarp: dwe@32e30000 {
            compatible = "nxp,imx8mp-dw100";
            reg = <0x32e30000 0x10000>;
            interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
                     <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
            clock-names = "axi", "ahb";
            power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver

maintainers:
  - Rui Miguel Silva <rmfrfs@gmail.com>
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description: |-
  The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
  receiver IP core named CSIS. The IP core originates from Samsung, and may be
  compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
  3.3, and i.MX8 SoCs use CSIS version 3.6.3.

  While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
  completely wrapped by the CSIS and doesn't expose a control interface of its
  own. This binding thus covers both IP cores.

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx7-mipi-csi2
          - fsl,imx8mm-mipi-csi2
      - items:
          - enum:
              - fsl,imx8mp-mipi-csi2
          - const: fsl,imx8mm-mipi-csi2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    items:
      - description: The peripheral clock (a.k.a. APB clock)
      - description: The external clock (optionally used as the pixel clock)
      - description: The MIPI D-PHY clock
      - description: The AXI clock

  clock-names:
    minItems: 3
    items:
      - const: pclk
      - const: wrap
      - const: phy
      - const: axi

  power-domains:
    maxItems: 1

  phy-supply:
    description: The MIPI D-PHY digital power supply

  resets:
    items:
      - description: MIPI D-PHY slave reset

  clock-frequency:
    description: The desired external clock ("wrap") frequency, in Hz
    default: 166000000

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port node, single endpoint describing the CSI-2 transmitter.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description:
                  Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines.
                minItems: 1
                items:
                  - const: 1
                  - const: 2
                  - const: 3
                  - const: 4

            required:
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Output port node

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains
  - ports

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx7-mipi-csi2
    then:
      required:
        - phy-supply
        - resets
    else:
      properties:
        clocks:
          minItems: 4
        clock-names:
          minItems: 4
        phy-supply: false
        resets: false

examples:
  - |
    #include <dt-bindings/clock/imx7d-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/reset/imx7-reset.h>

    mipi-csi@30750000 {
        compatible = "fsl,imx7-mipi-csi2";
        reg = <0x30750000 0x10000>;
        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clks IMX7D_IPG_ROOT_CLK>,
                 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
                 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
        clock-names = "pclk", "wrap", "phy";
        clock-frequency = <166000000>;

        power-domains = <&pgc_mipi_phy>;
        phy-supply = <&reg_1p0d>;
        resets = <&src IMX7_RESET_MIPI_PHY_MRST>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                mipi_from_sensor: endpoint {
                    remote-endpoint = <&ov2680_to_mipi>;
                    data-lanes = <1>;
                };
            };

            port@1 {
                reg = <1>;

                mipi_vc0_to_csi_mux: endpoint {
                    remote-endpoint = <&csi_mux_from_mipi_vc0>;
                };
            };
        };
    };

  - |
    #include <dt-bindings/clock/imx8mm-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    mipi-csi@32e30000 {
        compatible = "fsl,imx8mm-mipi-csi2";
        reg = <0x32e30000 0x1000>;
        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
        clock-frequency = <333000000>;
        clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
                 <&clk IMX8MM_CLK_CSI1_ROOT>,
                 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
                 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
        clock-names = "pclk", "wrap", "phy", "axi";
        power-domains = <&mipi_pd>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                imx8mm_mipi_csi_in: endpoint {
                    remote-endpoint = <&imx477_out>;
                    data-lanes = <1 2 3 4>;
                };
            };

            port@1 {
                reg = <1>;

                imx8mm_mipi_csi_out: endpoint {
                    remote-endpoint = <&csi_in>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nxp,imx7-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX7 and i.MX8 CSI bridge (CMOS Sensor Interface)

maintainers:
  - Rui Miguel Silva <rmfrfs@gmail.com>

description: |
  This is device node for the CMOS Sensor Interface (CSI) which enables the
  chip to connect directly to external CMOS image sensors.

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx8mq-csi
          - fsl,imx7-csi
          - fsl,imx6ul-csi
      - items:
          - const: fsl,imx8mm-csi
          - const: fsl,imx7-csi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: mclk

  port:
    $ref: /schemas/graph.yaml#/properties/port

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - port

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx7d-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    csi: csi@30710000 {
            compatible = "fsl,imx7-csi";
            reg = <0x30710000 0x10000>;
            interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&clks IMX7D_CSI_MCLK_ROOT_CLK>;
            clock-names = "mclk";

            port {
                    csi_from_csi_mux: endpoint {
                            remote-endpoint = <&csi_mux_to_csi>;
                    };
            };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX8QXP/QM JPEG decoder/encoder

maintainers:
  - Mirela Rabulea <mirela.rabulea@nxp.com>

description: |-
  The JPEG decoder/encoder present in iMX8QXP and iMX8QM SoCs is an
  ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for Baseline
  and Extended Sequential DCT modes.

properties:
  compatible:
    oneOf:
      - items:
          enum:
            - nxp,imx8qxp-jpgdec
            - nxp,imx8qxp-jpgenc
      - items:
          - const: nxp,imx8qm-jpgdec
          - const: nxp,imx8qxp-jpgdec
      - items:
          - const: nxp,imx8qm-jpgenc
          - const: nxp,imx8qxp-jpgenc

  reg:
    maxItems: 1

  interrupts:
    description: |
      There are 4 slots available in the IP, which the driver may use
      If a certain slot is used, it should have an associated interrupt
      The interrupt with index i is assumed to be for slot i
    minItems: 1               # At least one slot is needed by the driver
    maxItems: 4               # The IP has 4 slots available for use

  power-domains:
    description:
      List of phandle and PM domain specifier as documented in
      Documentation/devicetree/bindings/power/power_domain.txt
    minItems: 2               # Wrapper and 1 slot
    maxItems: 5               # Wrapper and 4 slots

required:
  - compatible
  - reg
  - interrupts
  - power-domains

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/firmware/imx/rsrc.h>

    jpegdec: jpegdec@58400000 {
        compatible = "nxp,imx8qxp-jpgdec";
        reg = <0x58400000 0x00050000 >;
        interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
        power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
                        <&pd IMX_SC_R_MJPEG_DEC_S0>,
                        <&pd IMX_SC_R_MJPEG_DEC_S1>,
                        <&pd IMX_SC_R_MJPEG_DEC_S2>,
                        <&pd IMX_SC_R_MJPEG_DEC_S3>;
    };

    jpegenc: jpegenc@58450000 {
        compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
        reg = <0x58450000 0x00050000 >;
        interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
        power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
                        <&pd IMX_SC_R_MJPEG_ENC_S0>,
                        <&pd IMX_SC_R_MJPEG_ENC_S1>,
                        <&pd IMX_SC_R_MJPEG_ENC_S2>,
                        <&pd IMX_SC_R_MJPEG_ENC_S3>;
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8MQ MIPI CSI-2 receiver

maintainers:
  - Martin Kepplinger <martin.kepplinger@puri.sm>

description: |-
  This binding covers the CSI-2 RX PHY and host controller included in the
  NXP i.MX8MQ SoC. It handles the sensor/image input and process for all the
  input imaging devices.

properties:
  compatible:
    enum:
      - fsl,imx8mq-mipi-csi2

  reg:
    maxItems: 1

  clocks:
    items:
      - description: core is the RX Controller Core Clock input. This clock
                     must be exactly equal to or faster than the receive
                     byteclock from the RX DPHY.
      - description: esc is the Rx Escape Clock. This must be the same escape
                     clock that the RX DPHY receives.
      - description: ui is the pixel clock (phy_ref up to 333Mhz).
                     See the reference manual for details.

  clock-names:
    items:
      - const: core
      - const: esc
      - const: ui

  power-domains:
    maxItems: 1

  resets:
    items:
      - description: CORE_RESET reset register bit definition
      - description: PHY_REF_RESET reset register bit definition
      - description: ESC_RESET reset register bit definition

  fsl,mipi-phy-gpr:
    description: |
      The phandle to the imx8mq syscon iomux-gpr with the register
      for setting RX_ENABLE for the mipi receiver.

      The format should be as follows:
      <gpr req_gpr>
      gpr is the phandle to general purpose register node.
      req_gpr is the gpr register offset of RX_ENABLE for the mipi phy.
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: The 'gpr' is the phandle to general purpose register node.
          - description: The 'req_gpr' is the gpr register offset containing
                        CSI2_1_RX_ENABLE or CSI2_2_RX_ENABLE respectively.
            maximum: 0xff

  interconnects:
    maxItems: 1

  interconnect-names:
    const: dram

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port node, single endpoint describing the CSI-2 transmitter.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                items:
                  - const: 1
                  - const: 2
                  - const: 3
                  - const: 4

            required:
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description:
          Output port node

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains
  - resets
  - fsl,mipi-phy-gpr
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mq-clock.h>
    #include <dt-bindings/interconnect/imx8mq.h>
    #include <dt-bindings/reset/imx8mq-reset.h>

    csi@30a70000 {
        compatible = "fsl,imx8mq-mipi-csi2";
        reg = <0x30a70000 0x1000>;
        clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
                 <&clk IMX8MQ_CLK_CSI1_ESC>,
                 <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
        clock-names = "core", "esc", "ui";
        assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
                          <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
                          <&clk IMX8MQ_CLK_CSI1_ESC>;
        assigned-clock-rates = <266000000>, <200000000>, <66000000>;
        assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
                                 <&clk IMX8MQ_SYS2_PLL_1000M>,
                                 <&clk IMX8MQ_SYS1_PLL_800M>;
        power-domains = <&pgc_mipi_csi1>;
        resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
                 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
                 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
        fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
        interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
        interconnect-names = "dram";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;

                imx8mm_mipi_csi_in: endpoint {
                    remote-endpoint = <&imx477_out>;
                    data-lanes = <1 2 3 4>;
                };
            };

            port@1 {
                reg = <1>;

                imx8mm_mipi_csi_out: endpoint {
                    remote-endpoint = <&csi_in>;
                };
            };
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs

maintainers:
  - Philipp Zabel <p.zabel@pengutronix.de>

description:
  Hantro G1/G2 video decode accelerators present on i.MX8MQ SoCs.

properties:
  compatible:
    oneOf:
      - const: nxp,imx8mq-vpu
        deprecated: true
      - const: nxp,imx8mq-vpu-g1
      - const: nxp,imx8mq-vpu-g2
      - const: nxp,imx8mm-vpu-g1

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
        #include <dt-bindings/clock/imx8mq-clock.h>
        #include <dt-bindings/power/imx8mq-power.h>
        #include <dt-bindings/interrupt-controller/arm-gic.h>

        vpu_g1: video-codec@38300000 {
                compatible = "nxp,imx8mq-vpu-g1";
                reg = <0x38300000 0x10000>;
                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
                power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
        };
  - |
        #include <dt-bindings/clock/imx8mq-clock.h>
        #include <dt-bindings/power/imx8mq-power.h>
        #include <dt-bindings/interrupt-controller/arm-gic.h>

        vpu_g2: video-codec@38300000 {
                compatible = "nxp,imx8mq-vpu-g2";
                reg = <0x38310000 0x10000>;
                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
                power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
        };


code:
Marvell PXA camera host interface

Required properties:
 - compatible: Should be "marvell,pxa270-qci"
 - reg: register base and size
 - interrupts: the interrupt number
 - any required generic properties defined in video-interfaces.txt

Optional properties:
 - clocks: input clock (see clock-bindings.txt)
 - clock-output-names: should contain the name of the clock driving the
                       sensor master clock MCLK
 - clock-frequency: host interface is driving MCLK, and MCLK rate is this rate

Example:

	pxa_camera: pxa_camera@50000000 {
		compatible = "marvell,pxa270-qci";
		reg = <0x50000000 0x1000>;
		interrupts = <33>;

		clocks = <&pxa2xx_clks 24>;
		clock-names = "ciclk";
		clock-frequency = <50000000>;
		clock-output-names = "qci_mclk";

		port {
			#address-cells = <1>;
			#size-cells = <0>;

			/* Parallel bus endpoint */
			qci: endpoint@0 {
				reg = <0>;		/* Local endpoint # */
				remote-endpoint = <&mt9m111_1>;
				bus-width = <8>;	/* Used data lines */
				hsync-active = <0>;	/* Active low */
				vsync-active = <0>;	/* Active low */
				pclk-sample = <1>;	/* Rising */
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,msm8916-camss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm CAMSS ISP

maintainers:
  - Robert Foss <robert.foss@linaro.org>
  - Todor Tomov <todor.too@gmail.com>

description: |
  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms

properties:
  compatible:
    const: qcom,msm8916-camss

  clocks:
    minItems: 19
    maxItems: 19

  clock-names:
    items:
      - const: top_ahb
      - const: ispif_ahb
      - const: csiphy0_timer
      - const: csiphy1_timer
      - const: csi0_ahb
      - const: csi0
      - const: csi0_phy
      - const: csi0_pix
      - const: csi0_rdi
      - const: csi1_ahb
      - const: csi1
      - const: csi1_phy
      - const: csi1_pix
      - const: csi1_rdi
      - const: ahb
      - const: vfe0
      - const: csi_vfe0
      - const: vfe_ahb
      - const: vfe_axi

  interrupts:
    minItems: 6
    maxItems: 6

  interrupt-names:
    items:
      - const: csiphy0
      - const: csiphy1
      - const: csid0
      - const: csid1
      - const: ispif
      - const: vfe0

  iommus:
    maxItems: 1

  power-domains:
    items:
      - description: VFE GDSC - Video Front End, Global Distributed Switch Controller.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    description:
      CSI input ports.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description:
                  An array of physical data lanes indexes.
                  Position of an entry determines the logical
                  lane number, while the value of an entry
                  indicates physical lane index. Lane swapping
                  is supported. Physical lane indexes;
                  0, 2, 3, 4.
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

  reg:
    minItems: 9
    maxItems: 9

  reg-names:
    items:
      - const: csiphy0
      - const: csiphy0_clk_mux
      - const: csiphy1
      - const: csiphy1_clk_mux
      - const: csid0
      - const: csid1
      - const: ispif
      - const: csi_clk_mux
      - const: vfe0

  vdda-supply:
    description:
      Definition of the regulator used as analog power supply.

required:
  - clock-names
  - clocks
  - compatible
  - interrupt-names
  - interrupts
  - iommus
  - power-domains
  - reg
  - reg-names
  - vdda-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,gcc-msm8916.h>

    camss: camss@1b00000 {
      compatible = "qcom,msm8916-camss";

      clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
        <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
        <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
        <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
        <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
        <&gcc GCC_CAMSS_CSI0_CLK>,
        <&gcc GCC_CAMSS_CSI0PHY_CLK>,
        <&gcc GCC_CAMSS_CSI0PIX_CLK>,
        <&gcc GCC_CAMSS_CSI0RDI_CLK>,
        <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
        <&gcc GCC_CAMSS_CSI1_CLK>,
        <&gcc GCC_CAMSS_CSI1PHY_CLK>,
        <&gcc GCC_CAMSS_CSI1PIX_CLK>,
        <&gcc GCC_CAMSS_CSI1RDI_CLK>,
        <&gcc GCC_CAMSS_AHB_CLK>,
        <&gcc GCC_CAMSS_VFE0_CLK>,
        <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
        <&gcc GCC_CAMSS_VFE_AHB_CLK>,
        <&gcc GCC_CAMSS_VFE_AXI_CLK>;

      clock-names = "top_ahb",
        "ispif_ahb",
        "csiphy0_timer",
        "csiphy1_timer",
        "csi0_ahb",
        "csi0",
        "csi0_phy",
        "csi0_pix",
        "csi0_rdi",
        "csi1_ahb",
        "csi1",
        "csi1_phy",
        "csi1_pix",
        "csi1_rdi",
        "ahb",
        "vfe0",
        "csi_vfe0",
        "vfe_ahb",
        "vfe_axi";

      interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;

      interrupt-names = "csiphy0",
        "csiphy1",
        "csid0",
        "csid1",
        "ispif",
        "vfe0";

      iommus = <&apps_iommu 3>;

      power-domains = <&gcc VFE_GDSC>;

      reg = <0x01b0ac00 0x200>,
        <0x01b00030 0x4>,
        <0x01b0b000 0x200>,
        <0x01b00038 0x4>,
        <0x01b08000 0x100>,
        <0x01b08400 0x100>,
        <0x01b0a000 0x500>,
        <0x01b00020 0x10>,
        <0x01b10000 0x1000>;

      reg-names = "csiphy0",
        "csiphy0_clk_mux",
        "csiphy1",
        "csiphy1_clk_mux",
        "csid0",
        "csid1",
        "ispif",
        "csi_clk_mux",
        "vfe0";

      vdda-supply = <&reg_2v8>;

      ports {
        #address-cells = <1>;
        #size-cells = <0>;
      };

    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,msm8916-venus.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Venus video encode and decode accelerators

maintainers:
  - Stanimir Varbanov <stanimir.varbanov@linaro.org>

description: |
  The Venus IP is a video encode and decode accelerator present
  on Qualcomm platforms

properties:
  compatible:
    const: qcom,msm8916-venus

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: core
      - const: iface
      - const: bus

  iommus:
    maxItems: 1

  memory-region:
    maxItems: 1

  video-decoder:
    type: object

    properties:
      compatible:
        const: "venus-decoder"

    required:
      - compatible

    additionalProperties: false

  video-encoder:
    type: object

    properties:
      compatible:
        const: "venus-encoder"

    required:
      - compatible

    additionalProperties: false

  video-firmware:
    type: object
    additionalProperties: false

    description: |
      Firmware subnode is needed when the platform does not
      have TrustZone.

    properties:
      iommus:
        maxItems: 1

    required:
      - iommus

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks
  - clock-names
  - iommus
  - memory-region
  - video-decoder
  - video-encoder

additionalProperties: false

examples:
  - |
        #include <dt-bindings/interrupt-controller/arm-gic.h>
        #include <dt-bindings/clock/qcom,gcc-msm8916.h>

        video-codec@1d00000 {
                compatible = "qcom,msm8916-venus";
                reg = <0x01d00000 0xff000>;
                interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
                        <&gcc GCC_VENUS0_AHB_CLK>,
                        <&gcc GCC_VENUS0_AXI_CLK>;
                clock-names = "core", "iface", "bus";
                power-domains = <&gcc VENUS_GDSC>;
                iommus = <&apps_iommu 5>;
                memory-region = <&venus_mem>;

                video-decoder {
                        compatible = "venus-decoder";
                };

                video-encoder {
                        compatible = "venus-encoder";
                };
        };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm CAMSS ISP

maintainers:
  - Robert Foss <robert.foss@linaro.org>
  - Todor Tomov <todor.too@gmail.com>

description: |
  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms

properties:
  compatible:
    const: qcom,msm8996-camss

  clocks:
    minItems: 36
    maxItems: 36

  clock-names:
    items:
      - const: top_ahb
      - const: ispif_ahb
      - const: csiphy0_timer
      - const: csiphy1_timer
      - const: csiphy2_timer
      - const: csi0_ahb
      - const: csi0
      - const: csi0_phy
      - const: csi0_pix
      - const: csi0_rdi
      - const: csi1_ahb
      - const: csi1
      - const: csi1_phy
      - const: csi1_pix
      - const: csi1_rdi
      - const: csi2_ahb
      - const: csi2
      - const: csi2_phy
      - const: csi2_pix
      - const: csi2_rdi
      - const: csi3_ahb
      - const: csi3
      - const: csi3_phy
      - const: csi3_pix
      - const: csi3_rdi
      - const: ahb
      - const: vfe0
      - const: csi_vfe0
      - const: vfe0_ahb
      - const: vfe0_stream
      - const: vfe1
      - const: csi_vfe1
      - const: vfe1_ahb
      - const: vfe1_stream
      - const: vfe_ahb
      - const: vfe_axi

  interrupts:
    minItems: 10
    maxItems: 10

  interrupt-names:
    items:
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csid3
      - const: ispif
      - const: vfe0
      - const: vfe1

  iommus:
    maxItems: 4

  power-domains:
    items:
      - description: VFE0 GDSC - Video Front End, Global Distributed Switch Controller.
      - description: VFE1 GDSC - Video Front End, Global Distributed Switch Controller.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    description:
      CSI input ports.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description:
                  An array of physical data lanes indexes.
                  Position of an entry determines the logical
                  lane number, while the value of an entry
                  indicates physical lane index. Lane swapping
                  is supported. Physical lane indexes are;
                  0, 1, 2, 3
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@2:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@3:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

  reg:
    minItems: 14
    maxItems: 14

  reg-names:
    items:
      - const: csiphy0
      - const: csiphy0_clk_mux
      - const: csiphy1
      - const: csiphy1_clk_mux
      - const: csiphy2
      - const: csiphy2_clk_mux
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csid3
      - const: ispif
      - const: csi_clk_mux
      - const: vfe0
      - const: vfe1

  vdda-supply:
    description:
      Definition of the regulator used as analog power supply.

required:
  - clock-names
  - clocks
  - compatible
  - interrupt-names
  - interrupts
  - iommus
  - power-domains
  - reg
  - reg-names
  - vdda-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
    #include <dt-bindings/clock/qcom,mmcc-msm8996.h>

    camss: camss@a00000 {
      compatible = "qcom,msm8996-camss";

      clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
        <&mmcc CAMSS_ISPIF_AHB_CLK>,
        <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
        <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
        <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
        <&mmcc CAMSS_CSI0_AHB_CLK>,
        <&mmcc CAMSS_CSI0_CLK>,
        <&mmcc CAMSS_CSI0PHY_CLK>,
        <&mmcc CAMSS_CSI0PIX_CLK>,
        <&mmcc CAMSS_CSI0RDI_CLK>,
        <&mmcc CAMSS_CSI1_AHB_CLK>,
        <&mmcc CAMSS_CSI1_CLK>,
        <&mmcc CAMSS_CSI1PHY_CLK>,
        <&mmcc CAMSS_CSI1PIX_CLK>,
        <&mmcc CAMSS_CSI1RDI_CLK>,
        <&mmcc CAMSS_CSI2_AHB_CLK>,
        <&mmcc CAMSS_CSI2_CLK>,
        <&mmcc CAMSS_CSI2PHY_CLK>,
        <&mmcc CAMSS_CSI2PIX_CLK>,
        <&mmcc CAMSS_CSI2RDI_CLK>,
        <&mmcc CAMSS_CSI3_AHB_CLK>,
        <&mmcc CAMSS_CSI3_CLK>,
        <&mmcc CAMSS_CSI3PHY_CLK>,
        <&mmcc CAMSS_CSI3PIX_CLK>,
        <&mmcc CAMSS_CSI3RDI_CLK>,
        <&mmcc CAMSS_AHB_CLK>,
        <&mmcc CAMSS_VFE0_CLK>,
        <&mmcc CAMSS_CSI_VFE0_CLK>,
        <&mmcc CAMSS_VFE0_AHB_CLK>,
        <&mmcc CAMSS_VFE0_STREAM_CLK>,
        <&mmcc CAMSS_VFE1_CLK>,
        <&mmcc CAMSS_CSI_VFE1_CLK>,
        <&mmcc CAMSS_VFE1_AHB_CLK>,
        <&mmcc CAMSS_VFE1_STREAM_CLK>,
        <&mmcc CAMSS_VFE_AHB_CLK>,
        <&mmcc CAMSS_VFE_AXI_CLK>;

      clock-names = "top_ahb",
        "ispif_ahb",
        "csiphy0_timer",
        "csiphy1_timer",
        "csiphy2_timer",
        "csi0_ahb",
        "csi0",
        "csi0_phy",
        "csi0_pix",
        "csi0_rdi",
        "csi1_ahb",
        "csi1",
        "csi1_phy",
        "csi1_pix",
        "csi1_rdi",
        "csi2_ahb",
        "csi2",
        "csi2_phy",
        "csi2_pix",
        "csi2_rdi",
        "csi3_ahb",
        "csi3",
        "csi3_phy",
        "csi3_pix",
        "csi3_rdi",
        "ahb",
        "vfe0",
        "csi_vfe0",
        "vfe0_ahb",
        "vfe0_stream",
        "vfe1",
        "csi_vfe1",
        "vfe1_ahb",
        "vfe1_stream",
        "vfe_ahb",
        "vfe_axi";

      interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;

      interrupt-names = "csiphy0",
        "csiphy1",
        "csiphy2",
        "csid0",
        "csid1",
        "csid2",
        "csid3",
        "ispif",
        "vfe0",
        "vfe1";

      iommus = <&vfe_smmu 0>,
         <&vfe_smmu 1>,
         <&vfe_smmu 2>,
         <&vfe_smmu 3>;

      power-domains = <&mmcc VFE0_GDSC>,
        <&mmcc VFE1_GDSC>;

      reg = <0x00a34000 0x1000>,
        <0x00a00030 0x4>,
        <0x00a35000 0x1000>,
        <0x00a00038 0x4>,
        <0x00a36000 0x1000>,
        <0x00a00040 0x4>,
        <0x00a30000 0x100>,
        <0x00a30400 0x100>,
        <0x00a30800 0x100>,
        <0x00a30c00 0x100>,
        <0x00a31000 0x500>,
        <0x00a00020 0x10>,
        <0x00a10000 0x1000>,
        <0x00a14000 0x1000>;

      reg-names = "csiphy0",
        "csiphy0_clk_mux",
        "csiphy1",
        "csiphy1_clk_mux",
        "csiphy2",
        "csiphy2_clk_mux",
        "csid0",
        "csid1",
        "csid2",
        "csid3",
        "ispif",
        "csi_clk_mux",
        "vfe0",
        "vfe1";

      vdda-supply = <&reg_2v8>;

      ports {
        #address-cells = <1>;
        #size-cells = <0>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,msm8996-venus.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Venus video encode and decode accelerators

maintainers:
  - Stanimir Varbanov <stanimir.varbanov@linaro.org>

description: |
  The Venus IP is a video encode and decode accelerator present
  on Qualcomm platforms

properties:
  compatible:
    const: qcom,msm8996-venus

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: core
      - const: iface
      - const: bus
      - const: mbus

  iommus:
    maxItems: 20

  memory-region:
    maxItems: 1

  video-decoder:
    type: object

    properties:
      compatible:
        const: venus-decoder

      clocks:
        maxItems: 1

      clock-names:
        items:
          - const: core

      power-domains:
        maxItems: 1

    required:
      - compatible
      - clocks
      - clock-names
      - power-domains

    additionalProperties: false

  video-encoder:
    type: object

    properties:
      compatible:
        const: venus-encoder

      clocks:
        maxItems: 1

      clock-names:
        items:
          - const: core

      power-domains:
        maxItems: 1

    required:
      - compatible
      - clocks
      - clock-names
      - power-domains

    additionalProperties: false

  video-firmware:
    type: object
    additionalProperties: false

    description: |
      Firmware subnode is needed when the platform does not
      have TrustZone.

    properties:
      iommus:
        maxItems: 1

    required:
      - iommus

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks
  - clock-names
  - iommus
  - memory-region
  - video-decoder
  - video-encoder

additionalProperties: false

examples:
  - |
        #include <dt-bindings/interrupt-controller/arm-gic.h>
        #include <dt-bindings/clock/qcom,mmcc-msm8996.h>

        video-codec@c00000 {
                compatible = "qcom,msm8996-venus";
                reg = <0x00c00000 0xff000>;
                interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mmcc VIDEO_CORE_CLK>,
                         <&mmcc VIDEO_AHB_CLK>,
                         <&mmcc VIDEO_AXI_CLK>,
                         <&mmcc VIDEO_MAXI_CLK>;
                clock-names = "core", "iface", "bus", "mbus";
                power-domains = <&mmcc VENUS_GDSC>;
                iommus =  <&venus_smmu 0x00>,
                          <&venus_smmu 0x01>,
                          <&venus_smmu 0x0a>,
                          <&venus_smmu 0x07>,
                          <&venus_smmu 0x0e>,
                          <&venus_smmu 0x0f>,
                          <&venus_smmu 0x08>,
                          <&venus_smmu 0x09>,
                          <&venus_smmu 0x0b>,
                          <&venus_smmu 0x0c>,
                          <&venus_smmu 0x0d>,
                          <&venus_smmu 0x10>,
                          <&venus_smmu 0x11>,
                          <&venus_smmu 0x21>,
                          <&venus_smmu 0x28>,
                          <&venus_smmu 0x29>,
                          <&venus_smmu 0x2b>,
                          <&venus_smmu 0x2c>,
                          <&venus_smmu 0x2d>,
                          <&venus_smmu 0x31>;
                memory-region = <&venus_mem>;

                video-decoder {
                        compatible = "venus-decoder";
                        clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
                        clock-names = "core";
                        power-domains = <&mmcc VENUS_CORE0_GDSC>;
                };

                video-encoder {
                        compatible = "venus-encoder";
                        clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
                        clock-names = "core";
                        power-domains = <&mmcc VENUS_CORE1_GDSC>;
                };
        };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,sc7180-venus.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Venus video encode and decode accelerators

maintainers:
  - Stanimir Varbanov <stanimir.varbanov@linaro.org>

description: |
  The Venus IP is a video encode and decode accelerator present
  on Qualcomm platforms

properties:
  compatible:
    const: qcom,sc7180-venus

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    minItems: 2
    maxItems: 3

  power-domain-names:
    minItems: 2
    items:
      - const: venus
      - const: vcodec0
      - const: cx

  clocks:
    maxItems: 5

  clock-names:
    items:
      - const: core
      - const: iface
      - const: bus
      - const: vcodec0_core
      - const: vcodec0_bus

  iommus:
    maxItems: 1

  memory-region:
    maxItems: 1

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: video-mem
      - const: cpu-cfg

  video-decoder:
    type: object

    properties:
      compatible:
        const: venus-decoder

    required:
      - compatible

    additionalProperties: false

  video-encoder:
    type: object

    properties:
      compatible:
        const: venus-encoder

    required:
      - compatible

    additionalProperties: false

  video-firmware:
    type: object
    additionalProperties: false

    description: |
      Firmware subnode is needed when the platform does not
      have TrustZone.

    properties:
      iommus:
        maxItems: 1

    required:
      - iommus

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - power-domain-names
  - clocks
  - clock-names
  - iommus
  - memory-region
  - video-decoder
  - video-encoder

additionalProperties: false

examples:
  - |
        #include <dt-bindings/interrupt-controller/arm-gic.h>
        #include <dt-bindings/clock/qcom,videocc-sc7180.h>

        venus: video-codec@aa00000 {
                compatible = "qcom,sc7180-venus";
                reg = <0x0aa00000 0xff000>;
                interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
                power-domains = <&videocc VENUS_GDSC>,
                                <&videocc VCODEC0_GDSC>;
                power-domain-names = "venus", "vcodec0";
                clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
                         <&videocc VIDEO_CC_VENUS_AHB_CLK>,
                         <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
                         <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
                         <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
                clock-names = "core", "iface", "bus",
                              "vcodec0_core", "vcodec0_bus";
                iommus = <&apps_smmu 0x0c00 0x60>;
                memory-region = <&venus_mem>;

                video-decoder {
                        compatible = "venus-decoder";
                };

                video-encoder {
                        compatible = "venus-encoder";
                };
        };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,sc7280-venus.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Venus video encode and decode accelerators

maintainers:
  - Stanimir Varbanov <stanimir.varbanov@linaro.org>

description: |
  The Venus Iris2 IP is a video encode and decode accelerator present
  on Qualcomm platforms

properties:
  compatible:
    const: qcom,sc7280-venus

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    minItems: 2
    maxItems: 3

  power-domain-names:
    minItems: 2
    items:
      - const: venus
      - const: vcodec0
      - const: cx

  clocks:
    maxItems: 5

  clock-names:
    items:
      - const: core
      - const: bus
      - const: iface
      - const: vcodec_core
      - const: vcodec_bus

  iommus:
    maxItems: 2

  memory-region:
    maxItems: 1

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: cpu-cfg
      - const: video-mem

  video-decoder:
    type: object

    properties:
      compatible:
        const: venus-decoder

    required:
      - compatible

    additionalProperties: false

  video-encoder:
    type: object

    properties:
      compatible:
        const: venus-encoder

    required:
      - compatible

    additionalProperties: false

  video-firmware:
    type: object
    additionalProperties: false

    description: |
      Firmware subnode is needed when the platform does not
      have TrustZone.

    properties:
      iommus:
        maxItems: 1

    required:
      - iommus

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - power-domain-names
  - clocks
  - clock-names
  - iommus
  - memory-region
  - video-decoder
  - video-encoder

additionalProperties: false

examples:
  - |
        #include <dt-bindings/interrupt-controller/arm-gic.h>
        #include <dt-bindings/clock/qcom,videocc-sc7280.h>
        #include <dt-bindings/interconnect/qcom,sc7280.h>
        #include <dt-bindings/power/qcom-rpmpd.h>

        venus: video-codec@aa00000 {
                compatible = "qcom,sc7280-venus";
                reg = <0x0aa00000 0xd0600>;
                interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

                clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
                         <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
                         <&videocc VIDEO_CC_VENUS_AHB_CLK>,
                         <&videocc VIDEO_CC_MVS0_CORE_CLK>,
                         <&videocc VIDEO_CC_MVS0_AXI_CLK>;
                clock-names = "core", "bus", "iface",
                              "vcodec_core", "vcodec_bus";

                power-domains = <&videocc MVSC_GDSC>,
                                <&videocc MVS0_GDSC>,
                                <&rpmhpd SC7280_CX>;
                power-domain-names = "venus", "vcodec0", "cx";

                interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
                                <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
                interconnect-names = "cpu-cfg", "video-mem";

                iommus = <&apps_smmu 0x2180 0x20>,
                         <&apps_smmu 0x2184 0x20>;

                memory-region = <&video_mem>;

                video-decoder {
                        compatible = "venus-decoder";
                };

                video-encoder {
                        compatible = "venus-encoder";
                };

                video-firmware {
                        iommus = <&apps_smmu 0x21a2 0x0>;
                };
        };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm CAMSS ISP

maintainers:
  - Robert Foss <robert.foss@linaro.org>
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>

description: |
  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms

properties:
  compatible:
    const: qcom,sdm660-camss

  clocks:
    minItems: 42
    maxItems: 42

  clock-names:
    items:
      - const: ahb
      - const: cphy_csid0
      - const: cphy_csid1
      - const: cphy_csid2
      - const: cphy_csid3
      - const: csi0_ahb
      - const: csi0
      - const: csi0_phy
      - const: csi0_pix
      - const: csi0_rdi
      - const: csi1_ahb
      - const: csi1
      - const: csi1_phy
      - const: csi1_pix
      - const: csi1_rdi
      - const: csi2_ahb
      - const: csi2
      - const: csi2_phy
      - const: csi2_pix
      - const: csi2_rdi
      - const: csi3_ahb
      - const: csi3
      - const: csi3_phy
      - const: csi3_pix
      - const: csi3_rdi
      - const: csiphy0_timer
      - const: csiphy1_timer
      - const: csiphy2_timer
      - const: csiphy_ahb2crif
      - const: csi_vfe0
      - const: csi_vfe1
      - const: ispif_ahb
      - const: throttle_axi
      - const: top_ahb
      - const: vfe0_ahb
      - const: vfe0
      - const: vfe0_stream
      - const: vfe1_ahb
      - const: vfe1
      - const: vfe1_stream
      - const: vfe_ahb
      - const: vfe_axi

  interrupts:
    minItems: 10
    maxItems: 10

  interrupt-names:
    items:
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csid3
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: ispif
      - const: vfe0
      - const: vfe1

  interconnects:
    maxItems: 1

  interconnect-names:
    items:
      - const: vfe-mem

  iommus:
    maxItems: 4

  power-domains:
    items:
      - description: VFE0 GDSC - Video Front End, Global Distributed Switch Controller.
      - description: VFE1 GDSC - Video Front End, Global Distributed Switch Controller.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    description:
      CSI input ports.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@2:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@3:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

  reg:
    minItems: 14
    maxItems: 14

  reg-names:
    items:
      - const: csi_clk_mux
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csid3
      - const: csiphy0
      - const: csiphy0_clk_mux
      - const: csiphy1
      - const: csiphy1_clk_mux
      - const: csiphy2
      - const: csiphy2_clk_mux
      - const: ispif
      - const: vfe0
      - const: vfe1

  vdda-supply:
    description:
      Definition of the regulator used as analog power supply.

required:
  - clock-names
  - clocks
  - compatible
  - interrupt-names
  - interrupts
  - iommus
  - power-domains
  - reg
  - reg-names
  - vdda-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,gcc-sdm660.h>
    #include <dt-bindings/clock/qcom,mmcc-sdm660.h>

    camss: camss@ca00000 {
      compatible = "qcom,sdm660-camss";

      clocks = <&mmcc CAMSS_AHB_CLK>,
        <&mmcc CAMSS_CPHY_CSID0_CLK>,
        <&mmcc CAMSS_CPHY_CSID1_CLK>,
        <&mmcc CAMSS_CPHY_CSID2_CLK>,
        <&mmcc CAMSS_CPHY_CSID3_CLK>,
        <&mmcc CAMSS_CSI0_AHB_CLK>,
        <&mmcc CAMSS_CSI0_CLK>,
        <&mmcc CAMSS_CPHY_CSID0_CLK>,
        <&mmcc CAMSS_CSI0PIX_CLK>,
        <&mmcc CAMSS_CSI0RDI_CLK>,
        <&mmcc CAMSS_CSI1_AHB_CLK>,
        <&mmcc CAMSS_CSI1_CLK>,
        <&mmcc CAMSS_CPHY_CSID1_CLK>,
        <&mmcc CAMSS_CSI1PIX_CLK>,
        <&mmcc CAMSS_CSI1RDI_CLK>,
        <&mmcc CAMSS_CSI2_AHB_CLK>,
        <&mmcc CAMSS_CSI2_CLK>,
        <&mmcc CAMSS_CPHY_CSID2_CLK>,
        <&mmcc CAMSS_CSI2PIX_CLK>,
        <&mmcc CAMSS_CSI2RDI_CLK>,
        <&mmcc CAMSS_CSI3_AHB_CLK>,
        <&mmcc CAMSS_CSI3_CLK>,
        <&mmcc CAMSS_CPHY_CSID3_CLK>,
        <&mmcc CAMSS_CSI3PIX_CLK>,
        <&mmcc CAMSS_CSI3RDI_CLK>,
        <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
        <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
        <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
        <&mmcc CSIPHY_AHB2CRIF_CLK>,
        <&mmcc CAMSS_CSI_VFE0_CLK>,
        <&mmcc CAMSS_CSI_VFE1_CLK>,
        <&mmcc CAMSS_ISPIF_AHB_CLK>,
        <&mmcc THROTTLE_CAMSS_AXI_CLK>,
        <&mmcc CAMSS_TOP_AHB_CLK>,
        <&mmcc CAMSS_VFE0_AHB_CLK>,
        <&mmcc CAMSS_VFE0_CLK>,
        <&mmcc CAMSS_VFE0_STREAM_CLK>,
        <&mmcc CAMSS_VFE1_AHB_CLK>,
        <&mmcc CAMSS_VFE1_CLK>,
        <&mmcc CAMSS_VFE1_STREAM_CLK>,
        <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
        <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;

      clock-names = "ahb",
        "cphy_csid0",
        "cphy_csid1",
        "cphy_csid2",
        "cphy_csid3",
        "csi0_ahb",
        "csi0",
        "csi0_phy",
        "csi0_pix",
        "csi0_rdi",
        "csi1_ahb",
        "csi1",
        "csi1_phy",
        "csi1_pix",
        "csi1_rdi",
        "csi2_ahb",
        "csi2",
        "csi2_phy",
        "csi2_pix",
        "csi2_rdi",
        "csi3_ahb",
        "csi3",
        "csi3_phy",
        "csi3_pix",
        "csi3_rdi",
        "csiphy0_timer",
        "csiphy1_timer",
        "csiphy2_timer",
        "csiphy_ahb2crif",
        "csi_vfe0",
        "csi_vfe1",
        "ispif_ahb",
        "throttle_axi",
        "top_ahb",
        "vfe0_ahb",
        "vfe0",
        "vfe0_stream",
        "vfe1_ahb",
        "vfe1",
        "vfe1_stream",
        "vfe_ahb",
        "vfe_axi";

      interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
        <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;

      interrupt-names = "csid0",
        "csid1",
        "csid2",
        "csid3",
        "csiphy0",
        "csiphy1",
        "csiphy2",
        "ispif",
        "vfe0",
        "vfe1";

      iommus = <&mmss_smmu 0xc00>,
        <&mmss_smmu 0xc01>,
        <&mmss_smmu 0xc02>,
        <&mmss_smmu 0xc03>;

      power-domains = <&mmcc CAMSS_VFE0_GDSC>,
        <&mmcc CAMSS_VFE1_GDSC>;

      reg = <0x0ca00020 0x10>,
        <0x0ca30000 0x100>,
        <0x0ca30400 0x100>,
        <0x0ca30800 0x100>,
        <0x0ca30c00 0x100>,
        <0x0c824000 0x1000>,
        <0x0ca00120 0x4>,
        <0x0c825000 0x1000>,
        <0x0ca00124 0x4>,
        <0x0c826000 0x1000>,
        <0x0ca00128 0x4>,
        <0x0ca31000 0x500>,
        <0x0ca10000 0x1000>,
        <0x0ca14000 0x1000>;

      reg-names = "csi_clk_mux",
        "csid0",
        "csid1",
        "csid2",
        "csid3",
        "csiphy0",
        "csiphy0_clk_mux",
        "csiphy1",
        "csiphy1_clk_mux",
        "csiphy2",
        "csiphy2_clk_mux",
        "ispif",
        "vfe0",
        "vfe1";

      vdda-supply = <&reg_2v8>;

      ports {
        #address-cells = <1>;
        #size-cells = <0>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,sdm660-venus.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Venus video encode and decode accelerators

maintainers:
  - Stanimir Varbanov <stanimir.varbanov@linaro.org>
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

description: |
  The Venus IP is a video encode and decode accelerator present
  on Qualcomm platforms

properties:
  compatible:
    const: qcom,sdm660-venus

  reg:
    maxItems: 1

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: core
      - const: iface
      - const: bus
      - const: bus_throttle

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: cpu-cfg
      - const: video-mem

  interrupts:
    maxItems: 1

  iommus:
    maxItems: 20

  memory-region:
    maxItems: 1

  power-domains:
    maxItems: 1

  video-decoder:
    type: object

    properties:
      compatible:
        const: venus-decoder

      clocks:
        maxItems: 1

      clock-names:
        items:
          - const: vcodec0_core

      power-domains:
        maxItems: 1

    required:
      - compatible
      - clocks
      - clock-names
      - power-domains

    additionalProperties: false

  video-encoder:
    type: object

    properties:
      compatible:
        const: venus-encoder

      clocks:
        maxItems: 1

      clock-names:
        items:
          - const: vcodec0_core

      power-domains:
        maxItems: 1

    required:
      - compatible
      - clocks
      - clock-names
      - power-domains

    additionalProperties: false

  video-firmware:
    type: object
    additionalProperties: false

    description: |
      Firmware subnode is needed when the platform does not
      have TrustZone.

    properties:
      iommus:
        maxItems: 1

    required:
      - iommus

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts
  - iommus
  - memory-region
  - power-domains
  - video-decoder
  - video-encoder

additionalProperties: false

examples:
  - |
        #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
        #include <dt-bindings/interrupt-controller/arm-gic.h>

        video-codec@cc00000 {
                compatible = "qcom,sdm660-venus";
                reg = <0x0cc00000 0xff000>;
                clocks = <&mmcc VIDEO_CORE_CLK>,
                         <&mmcc VIDEO_AHB_CLK>,
                         <&mmcc VIDEO_AXI_CLK>,
                         <&mmcc THROTTLE_VIDEO_AXI_CLK>;
                clock-names = "core", "iface", "bus", "bus_throttle";
                interconnects = <&gnoc 0 &mnoc 13>,
                                <&mnoc 4 &bimc 5>;
                interconnect-names = "cpu-cfg", "video-mem";
                interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
                iommus = <&mmss_smmu 0x400>,
                         <&mmss_smmu 0x401>,
                         <&mmss_smmu 0x40a>,
                         <&mmss_smmu 0x407>,
                         <&mmss_smmu 0x40e>,
                         <&mmss_smmu 0x40f>,
                         <&mmss_smmu 0x408>,
                         <&mmss_smmu 0x409>,
                         <&mmss_smmu 0x40b>,
                         <&mmss_smmu 0x40c>,
                         <&mmss_smmu 0x40d>,
                         <&mmss_smmu 0x410>,
                         <&mmss_smmu 0x421>,
                         <&mmss_smmu 0x428>,
                         <&mmss_smmu 0x429>,
                         <&mmss_smmu 0x42b>,
                         <&mmss_smmu 0x42c>,
                         <&mmss_smmu 0x42d>,
                         <&mmss_smmu 0x411>,
                         <&mmss_smmu 0x431>;
                memory-region = <&venus_region>;
                power-domains = <&mmcc VENUS_GDSC>;

                video-decoder {
                        compatible = "venus-decoder";
                        clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
                        clock-names = "vcodec0_core";
                        power-domains = <&mmcc VENUS_CORE0_GDSC>;
                };

                video-encoder {
                        compatible = "venus-encoder";
                        clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
                        clock-names = "vcodec0_core";
                        power-domains = <&mmcc VENUS_CORE0_GDSC>;
                };
        };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm CAMSS ISP

maintainers:
  - Robert Foss <robert.foss@linaro.org>

description: |
  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms

properties:
  compatible:
    const: qcom,sdm845-camss

  clocks:
    minItems: 36
    maxItems: 36

  clock-names:
    items:
      - const: camnoc_axi
      - const: cpas_ahb
      - const: cphy_rx_src
      - const: csi0
      - const: csi0_src
      - const: csi1
      - const: csi1_src
      - const: csi2
      - const: csi2_src
      - const: csiphy0
      - const: csiphy0_timer
      - const: csiphy0_timer_src
      - const: csiphy1
      - const: csiphy1_timer
      - const: csiphy1_timer_src
      - const: csiphy2
      - const: csiphy2_timer
      - const: csiphy2_timer_src
      - const: csiphy3
      - const: csiphy3_timer
      - const: csiphy3_timer_src
      - const: gcc_camera_ahb
      - const: gcc_camera_axi
      - const: slow_ahb_src
      - const: soc_ahb
      - const: vfe0_axi
      - const: vfe0
      - const: vfe0_cphy_rx
      - const: vfe0_src
      - const: vfe1_axi
      - const: vfe1
      - const: vfe1_cphy_rx
      - const: vfe1_src
      - const: vfe_lite
      - const: vfe_lite_cphy_rx
      - const: vfe_lite_src

  interrupts:
    minItems: 10
    maxItems: 10

  interrupt-names:
    items:
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: csiphy3
      - const: vfe0
      - const: vfe1
      - const: vfe_lite

  iommus:
    maxItems: 4

  power-domains:
    items:
      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    description:
      CSI input ports.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@2:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@3:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

  reg:
    minItems: 10
    maxItems: 10

  reg-names:
    items:
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: csiphy3
      - const: vfe0
      - const: vfe1
      - const: vfe_lite

  vdda-phy-supply:
    description:
      Phandle to a regulator supply to PHY core block.

  vdda-pll-supply:
    description:
      Phandle to 1.8V regulator supply to PHY refclk pll block.

required:
  - clock-names
  - clocks
  - compatible
  - interrupt-names
  - interrupts
  - iommus
  - power-domains
  - reg
  - reg-names
  - vdda-phy-supply
  - vdda-pll-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/qcom,camcc-sdm845.h>
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      camss: camss@a00000 {
        compatible = "qcom,sdm845-camss";

        clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
          <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
          <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
          <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
          <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
          <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
          <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
          <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
          <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
          <&clock_camcc CAM_CC_CSIPHY0_CLK>,
          <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
          <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
          <&clock_camcc CAM_CC_CSIPHY1_CLK>,
          <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
          <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
          <&clock_camcc CAM_CC_CSIPHY2_CLK>,
          <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
          <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
          <&clock_camcc CAM_CC_CSIPHY3_CLK>,
          <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
          <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
          <&gcc GCC_CAMERA_AHB_CLK>,
          <&gcc GCC_CAMERA_AXI_CLK>,
          <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
          <&clock_camcc CAM_CC_SOC_AHB_CLK>,
          <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
          <&clock_camcc CAM_CC_IFE_0_CLK>,
          <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
          <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
          <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
          <&clock_camcc CAM_CC_IFE_1_CLK>,
          <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
          <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
          <&clock_camcc CAM_CC_IFE_LITE_CLK>,
          <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
          <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;

        clock-names = "camnoc_axi",
          "cpas_ahb",
          "cphy_rx_src",
          "csi0",
          "csi0_src",
          "csi1",
          "csi1_src",
          "csi2",
          "csi2_src",
          "csiphy0",
          "csiphy0_timer",
          "csiphy0_timer_src",
          "csiphy1",
          "csiphy1_timer",
          "csiphy1_timer_src",
          "csiphy2",
          "csiphy2_timer",
          "csiphy2_timer_src",
          "csiphy3",
          "csiphy3_timer",
          "csiphy3_timer_src",
          "gcc_camera_ahb",
          "gcc_camera_axi",
          "slow_ahb_src",
          "soc_ahb",
          "vfe0_axi",
          "vfe0",
          "vfe0_cphy_rx",
          "vfe0_src",
          "vfe1_axi",
          "vfe1",
          "vfe1_cphy_rx",
          "vfe1_src",
          "vfe_lite",
          "vfe_lite_cphy_rx",
          "vfe_lite_src";

        interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
          <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-names = "csid0",
          "csid1",
          "csid2",
          "csiphy0",
          "csiphy1",
          "csiphy2",
          "csiphy3",
          "vfe0",
          "vfe1",
          "vfe_lite";

        iommus = <&apps_smmu 0x0808 0x0>,
          <&apps_smmu 0x0810 0x8>,
          <&apps_smmu 0x0c08 0x0>,
          <&apps_smmu 0x0c10 0x8>;

        power-domains = <&clock_camcc IFE_0_GDSC>,
          <&clock_camcc IFE_1_GDSC>,
          <&clock_camcc TITAN_TOP_GDSC>;

        reg = <0 0xacb3000 0 0x1000>,
          <0 0xacba000 0 0x1000>,
          <0 0xacc8000 0 0x1000>,
          <0 0xac65000 0 0x1000>,
          <0 0xac66000 0 0x1000>,
          <0 0xac67000 0 0x1000>,
          <0 0xac68000 0 0x1000>,
          <0 0xacaf000 0 0x4000>,
          <0 0xacb6000 0 0x4000>,
          <0 0xacc4000 0 0x4000>;

        reg-names = "csid0",
          "csid1",
          "csid2",
          "csiphy0",
          "csiphy1",
          "csiphy2",
          "csiphy3",
          "vfe0",
          "vfe1",
          "vfe_lite";

        vdda-phy-supply = <&vreg_l1a_0p875>;
        vdda-pll-supply = <&vreg_l26a_1p2>;

        ports {
          #address-cells = <1>;
          #size-cells = <0>;
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,sdm845-venus-v2.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Venus video encode and decode accelerators

maintainers:
  - Stanimir Varbanov <stanimir.varbanov@linaro.org>

description: |
  The Venus IP is a video encode and decode accelerator present
  on Qualcomm platforms

properties:
  compatible:
    const: qcom,sdm845-venus-v2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    minItems: 3
    maxItems: 4

  power-domain-names:
    minItems: 3
    items:
      - const: venus
      - const: vcodec0
      - const: vcodec1
      - const: cx

  clocks:
    maxItems: 7

  clock-names:
    items:
      - const: core
      - const: iface
      - const: bus
      - const: vcodec0_core
      - const: vcodec0_bus
      - const: vcodec1_core
      - const: vcodec1_bus

  iommus:
    maxItems: 2

  memory-region:
    maxItems: 1

  video-core0:
    type: object

    properties:
      compatible:
        const: venus-decoder

    required:
      - compatible

    additionalProperties: false

  video-core1:
    type: object

    properties:
      compatible:
        const: venus-encoder

    required:
      - compatible

    additionalProperties: false

  video-firmware:
    type: object
    additionalProperties: false

    description: |
      Firmware subnode is needed when the platform does not
      have TrustZone.

    properties:
      iommus:
        maxItems: 1

    required:
      - iommus

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - power-domain-names
  - clocks
  - clock-names
  - iommus
  - memory-region
  - video-core0
  - video-core1

additionalProperties: false

examples:
  - |
        #include <dt-bindings/interrupt-controller/arm-gic.h>
        #include <dt-bindings/clock/qcom,videocc-sdm845.h>

        video-codec@aa00000 {
                compatible = "qcom,sdm845-venus-v2";
                reg = <0x0aa00000 0xff000>;
                interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
                         <&videocc VIDEO_CC_VENUS_AHB_CLK>,
                         <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
                         <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
                         <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
                         <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
                         <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
                clock-names = "core", "iface", "bus",
                              "vcodec0_core", "vcodec0_bus",
                              "vcodec1_core", "vcodec1_bus";
                power-domains = <&videocc VENUS_GDSC>,
                                <&videocc VCODEC0_GDSC>,
                                <&videocc VCODEC1_GDSC>;
                power-domain-names = "venus", "vcodec0", "vcodec1";
                iommus = <&apps_smmu 0x10a0 0x8>,
                         <&apps_smmu 0x10b0 0x0>;
                memory-region = <&venus_mem>;

                video-core0 {
                        compatible = "venus-decoder";
                };

                video-core1 {
                        compatible = "venus-encoder";
                };
        };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/media/qcom,sdm845-venus.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Venus video encode and decode accelerators

maintainers:
  - Stanimir Varbanov <stanimir.varbanov@linaro.org>

description: |
  The Venus IP is a video encode and decode accelerator present
  on Qualcomm platforms

properties:
  compatible:
    const: qcom,sdm845-venus

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  power-domains:
    maxItems: 1

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: core
      - const: iface
      - const: bus

  iommus:
    maxItems: 2

  memory-region:
    maxItems: 1

  video-core0:
    type: object

    properties:
      compatible:
        const: venus-decoder

      clocks:
        maxItems: 2

      clock-names:
        items:
          - const: core
          - const: bus

      power-domains:
        maxItems: 1

    required:
      - compatible
      - clocks
      - clock-names
      - power-domains

    additionalProperties: false

  video-core1:
    type: object

    properties:
      compatible:
        const: venus-encoder

      clocks:
        maxItems: 2

      clock-names:
        items:
          - const: core
          - const: bus

      power-domains:
        maxItems: 1

    required:
      - compatible
      - clocks
      - clock-names
      - power-domains

    additionalProperties: false

  video-firmware:
    type: object
    additionalProperties: false

    description: |
      Firmware subnode is needed when the platform does not
      have TrustZone.

    properties:
      iommus:
        maxItems: 1

    required:
      - iommus

required:
  - compatible
  - reg
  - interrupts
  - power-domains
  - clocks
  - clock-names
  - iommus
  - memory-region
  - video-core0
  - video-core1

additionalProperties: false

examples:
  - |
        #include <dt-bindings/interrupt-controller/arm-gic.h>
        #include <dt-bindings/clock/qcom,videocc-sdm845.h>

        video-codec@aa00000 {
                compatible = "qcom,sdm845-venus";
                reg = <0x0aa00000 0xff000>;
                interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
                         <&videocc VIDEO_CC_VENUS_AHB_CLK>,
                         <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
                clock-names = "core", "iface", "bus";
                power-domains = <&videocc VENUS_GDSC>;
                iommus = <&apps_smmu 0x10a0 0x8>,
                         <&apps_smmu 0x10b0 0x0>;
                memory-region = <&venus_mem>;

                video-core0 {
                        compatible = "venus-decoder";
                        clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
                                 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
                        clock-names = "core", "bus";
                        power-domains = <&videocc VCODEC0_GDSC>;
                };

                video-core1 {
                        compatible = "venus-encoder";
                        clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
                                 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
                        clock-names = "core", "bus";
                        power-domains = <&videocc VCODEC1_GDSC>;
                };
        };