code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for NXP Layerscape-1088A family SoC.
 *
 * Copyright 2017-2020 NXP
 *
 * Harninder Rai <harninder.rai@nxp.com>
 *
 */
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "fsl,ls1088a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		crypto = &crypto;
		rtc1 = &ftm_alarm0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		/* We have 2 clusters having 4 Cortex-A53 cores each */
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			clocks = <&clockgen QORIQ_CLK_CMUX 0>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x102>;
			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x103>;
			clocks = <&clockgen QORIQ_CLK_CMUX 1>;
			cpu-idle-states = <&CPU_PH20>;
			#cooling-cells = <2>;
		};

		CPU_PH20: cpu-ph20 {
			compatible = "arm,idle-state";
			idle-state-name = "PH20";
			arm,psci-suspend-param = <0x0>;
			entry-latency-us = <1000>;
			exit-latency-us = <1000>;
			min-residency-us = <3000>;
		};
	};

	gic: interrupt-controller@6000000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
		      <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
		      <0x0 0x0c0c0000 0 0x2000>, /* GICC */
		      <0x0 0x0c0d0000 0 0x1000>, /* GICH */
		      <0x0 0x0c0e0000 0 0x20000>; /* GICV */
		interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		its: gic-its@6020000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0x6020000 0 0x20000>;
		};
	};

	thermal-zones {
		core-cluster {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 0>;

			trips {
				core_cluster_alert: core-cluster-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				core-cluster-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&core_cluster_alert>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		soc {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 1>;

			trips {
				soc-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
			     <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
			     <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
			     <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	reboot {
		compatible = "syscon-reboot";
		regmap = <&reset>;
		offset = <0x0>;
		mask = <0x02>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;

		clockgen: clocking@1300000 {
			compatible = "fsl,ls1088a-clockgen";
			reg = <0 0x1300000 0 0xa0000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		dcfg: dcfg@1e00000 {
			compatible = "fsl,ls1088a-dcfg", "syscon";
			reg = <0x0 0x1e00000 0x0 0x10000>;
			little-endian;
		};

		reset: syscon@1e60000 {
			compatible = "fsl,ls1088a-reset", "syscon";
			reg = <0x0 0x1e60000 0x0 0x10000>;
		};

		isc: syscon@1f70000 {
			compatible = "fsl,ls1088a-isc", "syscon";
			reg = <0x0 0x1f70000 0x0 0x10000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x1f70000 0x10000>;

			extirq: interrupt-controller@14 {
				compatible = "fsl,ls1088a-extirq";
				#interrupt-cells = <2>;
				#address-cells = <0>;
				interrupt-controller;
				reg = <0x14 4>;
				interrupt-map =
					<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
					<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
					<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
					<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
					<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
					<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
					<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
					<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
					<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
					<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-map-mask = <0xf 0x0>;
			};
		};

		sfp: efuse@1e80000 {
			compatible = "fsl,ls1028a-sfp";
			reg = <0x0 0x1e80000 0x0 0x10000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "sfp";
		};

		tmu: tmu@1f80000 {
			compatible = "fsl,qoriq-tmu";
			reg = <0x0 0x1f80000 0x0 0x10000>;
			interrupts = <0 23 0x4>;
			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
			fsl,tmu-calibration =
				/* Calibration data group 1 */
				<0x00000000 0x00000023
				0x00000001 0x0000002a
				0x00000002 0x00000030
				0x00000003 0x00000037
				0x00000004 0x0000003d
				0x00000005 0x00000044
				0x00000006 0x0000004a
				0x00000007 0x00000051
				0x00000008 0x00000057
				0x00000009 0x0000005e
				0x0000000a 0x00000064
				0x0000000b 0x0000006b
				/* Calibration data group 2 */
				0x00010000 0x00000022
				0x00010001 0x0000002a
				0x00010002 0x00000032
				0x00010003 0x0000003a
				0x00010004 0x00000042
				0x00010005 0x0000004a
				0x00010006 0x00000052
				0x00010007 0x0000005a
				0x00010008 0x00000062
				0x00010009 0x0000006a
				/* Calibration data group 3 */
				0x00020000 0x00000021
				0x00020001 0x0000002b
				0x00020002 0x00000035
				0x00020003 0x00000040
				0x00020004 0x0000004a
				0x00020005 0x00000054
				0x00020006 0x0000005e
				/* Calibration data group 4 */
				0x00030000 0x00000010
				0x00030001 0x0000001c
				0x00030002 0x00000027
				0x00030003 0x00000032
				0x00030004 0x0000003e
				0x00030005 0x00000049
				0x00030006 0x00000054
				0x00030007 0x00000060>;
			little-endian;
			#thermal-sensor-cells = <1>;
		};

		dspi: spi@2100000 {
			compatible = "fsl,ls1088a-dspi",
				     "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			spi-num-chipselects = <6>;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21c0500 0x0 0x100>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21c0600 0x0 0x100>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		gpio0: gpio@2300000 {
			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
			little-endian;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@2310000 {
			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
			little-endian;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2320000 {
			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
			little-endian;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2330000 {
			compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2330000 0x0 0x10000>;
			interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
			little-endian;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		ifc: memory-controller@2240000 {
			compatible = "fsl,ifc";
			reg = <0x0 0x2240000 0x0 0x20000>;
			interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
			little-endian;
			#address-cells = <2>;
			#size-cells = <1>;
			status = "disabled";
		};

		i2c0: i2c@2000000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2000000 0x0 0x10000>;
			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(8)>;
			status = "disabled";
		};

		i2c1: i2c@2010000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2010000 0x0 0x10000>;
			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(8)>;
			status = "disabled";
		};

		i2c2: i2c@2020000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2020000 0x0 0x10000>;
			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(8)>;
			status = "disabled";
		};

		i2c3: i2c@2030000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2030000 0x0 0x10000>;
			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(8)>;
			status = "disabled";
		};

		qspi: spi@20c0000 {
			compatible = "fsl,ls2080a-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x20c0000 0x0 0x10000>,
			      <0x0 0x20000000 0x0 0x10000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "qspi_en", "qspi";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			status = "disabled";
		};

		esdhc: esdhc@2140000 {
			compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
			reg = <0x0 0x2140000 0x0 0x10000>;
			interrupts = <0 28 0x4>; /* Level high type */
			clock-frequency = <0>;
			clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			little-endian;
			bus-width = <4>;
			status = "disabled";
		};

		usb0: usb@3100000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3100000 0x0 0x10000>;
			interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
			snps,dis_rxdet_inp3_quirk;
			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
			status = "disabled";
		};

		usb1: usb@3110000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3110000 0x0 0x10000>;
			interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
			snps,dis_rxdet_inp3_quirk;
			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
			status = "disabled";
		};

		sata: sata@3200000 {
			compatible = "fsl,ls1088a-ahci";
			reg = <0x0 0x3200000 0x0 0x10000>,
				<0x7 0x100520 0x0 0x4>;
			reg-names = "ahci", "sata-ecc";
			interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			dma-coherent;
			status = "disabled";
		};

		crypto: crypto@8000000 {
			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
			fsl,sec-era = <8>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x00 0x8000000 0x100000>;
			reg = <0x00 0x8000000 0x0 0x100000>;
			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
			dma-coherent;

			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x10000 0x10000>;
				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x20000 0x10000>;
				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x30000 0x10000>;
				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x40000 0x10000>;
				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		pcie1: pcie@3400000 {
			compatible = "fsl,ls1088a-pcie";
			reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
			      <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
			interrupt-names = "aer";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			num-viewport = <256>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
			status = "disabled";
		};

		pcie_ep1: pcie-ep@3400000 {
			compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
			reg = <0x00 0x03400000 0x0 0x00100000>,
			      <0x20 0x00000000 0x8 0x00000000>;
			reg-names = "regs", "addr_space";
			num-ib-windows = <24>;
			num-ob-windows = <256>;
			max-functions = /bits/ 8 <2>;
			status = "disabled";
		};

		pcie2: pcie@3500000 {
			compatible = "fsl,ls1088a-pcie";
			reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
			      <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
			interrupt-names = "aer";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			num-viewport = <6>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
			status = "disabled";
		};

		pcie_ep2: pcie-ep@3500000 {
			compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
			reg = <0x00 0x03500000 0x0 0x00100000>,
			      <0x28 0x00000000 0x8 0x00000000>;
			reg-names = "regs", "addr_space";
			num-ib-windows = <6>;
			num-ob-windows = <6>;
			status = "disabled";
		};

		pcie3: pcie@3600000 {
			compatible = "fsl,ls1088a-pcie";
			reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
			      <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
			interrupt-names = "aer";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			num-viewport = <6>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
					<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
			status = "disabled";
		};

		pcie_ep3: pcie-ep@3600000 {
			compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
			reg = <0x00 0x03600000 0x0 0x00100000>,
			      <0x30 0x00000000 0x8 0x00000000>;
			reg-names = "regs", "addr_space";
			num-ib-windows = <6>;
			num-ob-windows = <6>;
			status = "disabled";
		};

		smmu: iommu@5000000 {
			compatible = "arm,mmu-500";
			reg = <0 0x5000000 0 0x800000>;
			#iommu-cells = <1>;
			stream-match-mask = <0x7C00>;
			#global-interrupts = <12>;
				     // global secure fault
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     // combined secure
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     // global non-secure fault
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     // combined non-secure
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				     // performance counter interrupts 0-7
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				     // per context interrupt, 64 interrupts
				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
		};

		console@8340020 {
			compatible = "fsl,dpaa2-console";
			reg = <0x00000000 0x08340020 0 0x2>;
		};

		ptp-timer@8b95000 {
			compatible = "fsl,dpaa2-ptp";
			reg = <0x0 0x8b95000 0x0 0x100>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			little-endian;
			fsl,extts-fifo;
		};

		emdio1: mdio@8b96000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8b96000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <2500000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			status = "disabled";
		};

		emdio2: mdio@8b97000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8b97000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <2500000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(1)>;
			status = "disabled";
		};

		pcs_mdio1: mdio@8c07000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c07000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs1: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio2: mdio@8c0b000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c0b000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs2: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio3: mdio@8c0f000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c0f000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs3_0: ethernet-phy@0 {
				reg = <0>;
			};

			pcs3_1: ethernet-phy@1 {
				reg = <1>;
			};

			pcs3_2: ethernet-phy@2 {
				reg = <2>;
			};

			pcs3_3: ethernet-phy@3 {
				reg = <3>;
			};
		};

		pcs_mdio7: mdio@8c1f000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c1f000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs7_0: ethernet-phy@0 {
				reg = <0>;
			};

			pcs7_1: ethernet-phy@1 {
				reg = <1>;
			};

			pcs7_2: ethernet-phy@2 {
				reg = <2>;
			};

			pcs7_3: ethernet-phy@3 {
				reg = <3>;
			};
		};

		cluster1_core0_watchdog: wdt@c000000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc000000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster1_core1_watchdog: wdt@c010000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc010000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster1_core2_watchdog: wdt@c020000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc020000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster1_core3_watchdog: wdt@c030000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc030000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster2_core0_watchdog: wdt@c100000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc100000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster2_core1_watchdog: wdt@c110000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc110000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster2_core2_watchdog: wdt@c120000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc120000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster2_core3_watchdog: wdt@c130000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc130000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(16)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		fsl_mc: fsl-mc@80c000000 {
			compatible = "fsl,qoriq-mc";
			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
			msi-parent = <&its>;
			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
			dma-coherent;
			#address-cells = <3>;
			#size-cells = <1>;

			/*
			 * Region type 0x0 - MC portals
			 * Region type 0x1 - QBMAN portals
			 */
			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;

			dpmacs {
				#address-cells = <1>;
				#size-cells = <0>;

				dpmac1: ethernet@1 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <1>;
				};

				dpmac2: ethernet@2 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <2>;
				};

				dpmac3: ethernet@3 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <3>;
				};

				dpmac4: ethernet@4 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <4>;
				};

				dpmac5: ethernet@5 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <5>;
				};

				dpmac6: ethernet@6 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <6>;
				};

				dpmac7: ethernet@7 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <7>;
				};

				dpmac8: ethernet@8 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <8>;
				};

				dpmac9: ethernet@9 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <9>;
				};

				dpmac10: ethernet@a {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0xa>;
				};
			};
		};

		rcpm: power-controller@1e34040 {
			compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
			reg = <0x0 0x1e34040 0x0 0x18>;
			#fsl,rcpm-wakeup-cells = <6>;
			little-endian;
		};

		ftm_alarm0: timer@2800000 {
			compatible = "fsl,ls1088a-ftm-alarm";
			reg = <0x0 0x2800000 0x0 0x10000>;
			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Freescale LS2080a QDS Board.
 *
 * Copyright 2015-2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
 *
 */

/dts-v1/;

#include "fsl-ls2080a.dtsi"
#include "fsl-ls208xa-qds.dtsi"

/ {
	model = "Freescale Layerscape 2080a QDS Board";
	compatible = "fsl,ls2080a-qds", "fsl,ls2080a";

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Freescale LS2080a RDB Board.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
 *
 */

/dts-v1/;

#include "fsl-ls2080a.dtsi"
#include "fsl-ls208xa-rdb.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Freescale Layerscape 2080a RDB Board";
	compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";

	chosen {
		stdout-path = "serial1:115200n8";
	};
};

&dpmac5 {
	phy-handle = <&mdio2_phy1>;
	phy-connection-type = "10gbase-r";
};

&dpmac6 {
	phy-handle = <&mdio2_phy2>;
	phy-connection-type = "10gbase-r";
};

&dpmac7 {
	phy-handle = <&mdio2_phy3>;
	phy-connection-type = "10gbase-r";
};

&dpmac8 {
	phy-handle = <&mdio2_phy4>;
	phy-connection-type = "10gbase-r";
};

&emdio1 {
	status = "disabled";

	/* CS4340 PHYs */
	mdio1_phy1: emdio1-phy@10 {
		reg = <0x10>;
	};

	mdio1_phy2: emdio1-phy@11 {
		reg = <0x11>;
	};

	mdio1_phy3: emdio1-phy@12 {
		reg = <0x12>;
	};

	mdio1_phy4: emdio1-phy@13 {
		reg = <0x13>;
	};
};

&emdio2 {
	/* AQR405 PHYs */
	mdio2_phy1: emdio2-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c45";
		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x0>;
	};

	mdio2_phy2: emdio2-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c45";
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x1>;
	};

	mdio2_phy3: emdio2-phy@2 {
		compatible = "ethernet-phy-ieee802.3-c45";
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x2>;
	};

	mdio2_phy4: emdio2-phy@3 {
		compatible = "ethernet-phy-ieee802.3-c45";
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x3>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Freescale LS2080a software Simulator model
 *
 * Copyright 2014-2015 Freescale Semiconductor, Inc.
 *
 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
 *
 */

/dts-v1/;

#include "fsl-ls2080a.dtsi"

/ {
	model = "Freescale Layerscape 2080a software Simulator model";
	compatible = "fsl,ls2080a-simu", "fsl,ls2080a";

	ethernet@2210000 {
		compatible = "smsc,lan91c111";
		reg = <0x0 0x2210000 0x0 0x100>;
		interrupts = <0 58 0x1>;
	};
};

&ifc {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
 *
 * Copyright 2014-2016 Freescale Semiconductor, Inc.
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
 *
 */

#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include "fsl-ls208xa.dtsi"

&cpu {
	cpu0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0>;
		clocks = <&clockgen QORIQ_CLK_CMUX 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1>;
		clocks = <&clockgen QORIQ_CLK_CMUX 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
	};

	cpu2: cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x100>;
		clocks = <&clockgen QORIQ_CLK_CMUX 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
	};

	cpu3: cpu@101 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x101>;
		clocks = <&clockgen QORIQ_CLK_CMUX 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
	};

	cpu4: cpu@200 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x200>;
		clocks = <&clockgen QORIQ_CLK_CMUX 2>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster2_l2>;
		#cooling-cells = <2>;
	};

	cpu5: cpu@201 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x201>;
		clocks = <&clockgen QORIQ_CLK_CMUX 2>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster2_l2>;
		#cooling-cells = <2>;
	};

	cpu6: cpu@300 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x300>;
		clocks = <&clockgen QORIQ_CLK_CMUX 3>;
		next-level-cache = <&cluster3_l2>;
		cpu-idle-states = <&CPU_PW20>;
		#cooling-cells = <2>;
	};

	cpu7: cpu@301 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x301>;
		clocks = <&clockgen QORIQ_CLK_CMUX 3>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster3_l2>;
		#cooling-cells = <2>;
	};

	cluster0_l2: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
	};

	cluster1_l2: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
	};

	cluster2_l2: l2-cache2 {
		compatible = "cache";
		cache-level = <2>;
	};

	cluster3_l2: l2-cache3 {
		compatible = "cache";
		cache-level = <2>;
	};

	CPU_PW20: cpu-pw20 {
		compatible = "arm,idle-state";
		idle-state-name = "PW20";
		arm,psci-suspend-param = <0x00010000>;
		entry-latency-us = <2000>;
		exit-latency-us = <2000>;
		min-residency-us = <6000>;
	};
};

&pcie1 {
	reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
	      <0x10 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000   /* downstream I/O */
		  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};

&pcie2 {
	reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
	      <0x12 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000   /* downstream I/O */
		  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};

&pcie3 {
	reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
	      <0x14 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000   /* downstream I/O */
		  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};

&pcie4 {
	reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
	      <0x16 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000   /* downstream I/O */
		  0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};

&timer {
	fsl,erratum-a008585;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for NXP LS2081A RDB Board.
 *
 * Copyright 2017 NXP
 *
 * Priyanka Jain <priyanka.jain@nxp.com>
 *
 */

/dts-v1/;

#include "fsl-ls2088a.dtsi"

/ {
	model = "NXP Layerscape 2081A RDB Board";
	compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
	};

	chosen {
		stdout-path = "serial1:115200n8";
	};
};

&dspi {
	status = "okay";

	n25q512a: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <3000000>;
		reg = <0>;
	};
};

&esdhc {
	status = "okay";
};

&i2c0 {
	status = "okay";

	pca9547: mux@75 {
		compatible = "nxp,pca9547";
		reg = <0x75>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x1>;

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			ina220@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <500>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			adt7481@4c {
				compatible = "adi,adt7461";
				reg = <0x4c>;
			};
		};
	};
};

&ifc {
	status = "disabled";
};

&qspi {
	status = "okay";

	s25fs512s0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		spi-max-frequency = <20000000>;
		reg = <0>;
	};

	s25fs512s1: flash@1 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		spi-max-frequency = <20000000>;
		reg = <1>;
	};
};

&sata0 {
	status = "okay";
};

&sata1 {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Freescale LS2088A QDS Board.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 *
 */

/dts-v1/;

#include "fsl-ls2088a.dtsi"
#include "fsl-ls208xa-qds.dtsi"

/ {
	model = "Freescale Layerscape 2088A QDS Board";
	compatible = "fsl,ls2088a-qds", "fsl,ls2088a";

	chosen {
		stdout-path = "serial0:115200n8";
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Freescale LS2088A RDB Board.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 *
 */

/dts-v1/;

#include "fsl-ls2088a.dtsi"
#include "fsl-ls208xa-rdb.dtsi"

/ {
	model = "Freescale Layerscape 2088A RDB Board";
	compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";

	chosen {
		stdout-path = "serial1:115200n8";
	};
};

&dpmac1 {
	phy-handle = <&mdio1_phy1>;
	phy-connection-type = "10gbase-r";
};

&dpmac2 {
	phy-handle = <&mdio1_phy2>;
	phy-connection-type = "10gbase-r";
};

&dpmac3 {
	phy-handle = <&mdio1_phy3>;
	phy-connection-type = "10gbase-r";
};

&dpmac4 {
	phy-handle = <&mdio1_phy4>;
	phy-connection-type = "10gbase-r";
};

&dpmac5 {
	phy-handle = <&mdio2_phy1>;
	phy-connection-type = "10gbase-r";
};

&dpmac6 {
	phy-handle = <&mdio2_phy2>;
	phy-connection-type = "10gbase-r";
};

&dpmac7 {
	phy-handle = <&mdio2_phy3>;
	phy-connection-type = "10gbase-r";
};

&dpmac8 {
	phy-handle = <&mdio2_phy4>;
	phy-connection-type = "10gbase-r";
};

&emdio1 {
	status = "okay";

	mdio1_phy1: ethernet-phy@10 {
		compatible = "ethernet-phy-id13e5.1002";
		reg = <0x10>;
	};

	mdio1_phy2: ethernet-phy@11 {
		compatible = "ethernet-phy-id13e5.1002";
		reg = <0x11>;
	};

	mdio1_phy3: ethernet-phy@12 {
		compatible = "ethernet-phy-id13e5.1002";
		reg = <0x12>;
	};

	mdio1_phy4: ethernet-phy@13 {
		compatible = "ethernet-phy-id13e5.1002";
		reg = <0x13>;
	};
};

&emdio2 {
	status = "okay";

	mdio2_phy1: ethernet-phy@0 {
		compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45";
		interrupts-extended = <&extirq 1 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x0>;
	};

	mdio2_phy2: ethernet-phy@1 {
		compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45";
		interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x1>;
	};

	mdio2_phy3: ethernet-phy@2 {
		compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45";
		interrupts-extended = <&extirq 4 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x2>;
	};

	mdio2_phy4: ethernet-phy@3 {
		compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45";
		interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
		reg = <0x3>;
	};
};

&pcs_mdio1 {
	status = "okay";
};

&pcs_mdio2 {
	status = "okay";
};

&pcs_mdio3 {
	status = "okay";
};

&pcs_mdio4 {
	status = "okay";
};

&pcs_mdio5 {
	status = "okay";
};

&pcs_mdio6 {
	status = "okay";
};

&pcs_mdio7 {
	status = "okay";
};

&pcs_mdio8 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 *
 */

#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include "fsl-ls208xa.dtsi"

&cpu {
	cpu0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x0>;
		clocks = <&clockgen QORIQ_CLK_CMUX 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x1>;
		clocks = <&clockgen QORIQ_CLK_CMUX 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
	};

	cpu2: cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x100>;
		clocks = <&clockgen QORIQ_CLK_CMUX 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
	};

	cpu3: cpu@101 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x101>;
		clocks = <&clockgen QORIQ_CLK_CMUX 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
	};

	cpu4: cpu@200 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x200>;
		clocks = <&clockgen QORIQ_CLK_CMUX 2>;
		next-level-cache = <&cluster2_l2>;
		cpu-idle-states = <&CPU_PW20>;
		#cooling-cells = <2>;
	};

	cpu5: cpu@201 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x201>;
		clocks = <&clockgen QORIQ_CLK_CMUX 2>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster2_l2>;
		#cooling-cells = <2>;
	};

	cpu6: cpu@300 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x300>;
		clocks = <&clockgen QORIQ_CLK_CMUX 3>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster3_l2>;
		#cooling-cells = <2>;
	};

	cpu7: cpu@301 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x301>;
		clocks = <&clockgen QORIQ_CLK_CMUX 3>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster3_l2>;
		#cooling-cells = <2>;
	};

	cluster0_l2: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
	};

	cluster1_l2: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
	};

	cluster2_l2: l2-cache2 {
		compatible = "cache";
		cache-level = <2>;
	};

	cluster3_l2: l2-cache3 {
		compatible = "cache";
		cache-level = <2>;
	};

	CPU_PW20: cpu-pw20 {
		compatible = "arm,idle-state";
		idle-state-name = "PW20";
		arm,psci-suspend-param = <0x0>;
		entry-latency-us = <2000>;
		exit-latency-us = <2000>;
		min-residency-us = <6000>;
	};
};

&pcie1 {
	compatible = "fsl,ls2088a-pcie";
	reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
	      <0x20 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
};

&pcie2 {
	compatible = "fsl,ls2088a-pcie";
	reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
	      <0x28 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
};

&pcie3 {
	compatible = "fsl,ls2088a-pcie";
	reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
	      <0x30 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
};

&pcie4 {
	compatible = "fsl,ls2088a-pcie";
	reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
	      <0x38 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Freescale LS2080A QDS Board.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 *
 */

/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
&dpmac9 {
	phy-handle = <&mdio0_phy12>;
	phy-connection-type = "sgmii";
};

&dpmac10 {
	phy-handle = <&mdio0_phy13>;
	phy-connection-type = "sgmii";
};

&dpmac11 {
	phy-handle = <&mdio0_phy14>;
	phy-connection-type = "sgmii";
};

&dpmac12 {
	phy-handle = <&mdio0_phy15>;
	phy-connection-type = "sgmii";
};

&esdhc {
	mmc-hs200-1_8v;
	status = "okay";
};

&ifc {
	status = "okay";
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x5 0x80000000 0x08000000
		  0x2 0x0 0x5 0x30000000 0x00010000
		  0x3 0x0 0x5 0x20000000 0x00010000>;

	nor@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x8000000>;
		bank-width = <2>;
		device-width = <1>;
	};

	nand@2,0 {
	     compatible = "fsl,ifc-nand";
	     reg = <0x2 0x0 0x10000>;
	};

	boardctrl: board-control@3,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,ls208xaqds-fpga", "fsl,fpga-qixis", "simple-mfd";
		reg = <3 0 0x1000>;
		ranges = <0 3 0 0x1000>;

		mdio-mux-emi1@54 {
			compatible = "mdio-mux-mmioreg", "mdio-mux";
			mdio-parent-bus = <&emdio1>;
			reg = <0x54 1>;		/* BRDCFG4 */
			mux-mask = <0xe0>;	/* EMI1_MDIO */
			#address-cells=<1>;
			#size-cells = <0>;

			/* Child MDIO buses, one for each riser card:
			 * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
			 * VSC8234 PHYs on the riser cards.
			 */
			mdio_mux3: mdio@60 {
				reg = <0x60>;
				#address-cells = <1>;
				#size-cells = <0>;

				mdio0_phy12: mdio-phy0@1c {
					reg = <0x1c>;
				};

				mdio0_phy13: mdio-phy1@1d {
					reg = <0x1d>;
				};

				mdio0_phy14: mdio-phy2@1e {
					reg = <0x1e>;
				};

				mdio0_phy15: mdio-phy3@1f {
					reg = <0x1f>;
				};
			};
		};
	};
};

&i2c0 {
	status = "okay";
	pca9547@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;
		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x00>;
			rtc@68 {
				compatible = "dallas,ds3232";
				reg = <0x68>;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x02>;

			ina220@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <500>;
			};

			ina220@41 {
				compatible = "ti,ina220";
				reg = <0x41>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			adt7481@4c {
				compatible = "adi,adt7461";
				reg = <0x4c>;
			};
		};
	};
};

&i2c1 {
	status = "disabled";
};

&i2c2 {
	status = "disabled";
};

&i2c3 {
	status = "disabled";
};

&dspi {
	status = "okay";
	dflash0: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p80";
		spi-max-frequency = <3000000>;
		reg = <0>;
	};
	dflash1: flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p80";
		spi-max-frequency = <3000000>;
		reg = <1>;
	};
	dflash2: flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p80";
		spi-max-frequency = <3000000>;
		reg = <2>;
	};
};

&qspi {
	status = "okay";
	flash0: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p80";
		spi-max-frequency = <20000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		reg = <0>;
	};
	flash2: flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p80";
		spi-max-frequency = <20000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		reg = <2>;
	};
};

&sata0 {
	status = "okay";
};

&sata1 {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Freescale LS2080A RDB Board.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017-2020 NXP
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 *
 */

&esdhc {
	status = "okay";
};

&ifc {
	status = "okay";
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x5 0x80000000 0x08000000
		  0x2 0x0 0x5 0x30000000 0x00010000
		  0x3 0x0 0x5 0x20000000 0x00010000>;

	nor@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x8000000>;
		bank-width = <2>;
		device-width = <1>;
	};

	nand@2,0 {
	     compatible = "fsl,ifc-nand";
	     reg = <0x2 0x0 0x10000>;
	};

	cpld@3,0 {
	     reg = <0x3 0x0 0x10000>;
	     compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
	};

};

&i2c0 {
	status = "okay";
	pca9547@75 {
		compatible = "nxp,pca9547";
		reg = <0x75>;
		#address-cells = <1>;
		#size-cells = <0>;
		idle-state = <0>;

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x01>;
			rtc@68 {
				compatible = "dallas,ds3232";
				reg = <0x68>;
				/* IRQ_RTC_B -> IRQ06, active low */
				interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x02>;

			ina220@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <500>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			adt7481@4c {
				compatible = "adi,adt7461";
				reg = <0x4c>;
			};
		};
	};
};

&i2c1 {
	status = "disabled";
};

&i2c2 {
	status = "disabled";
};

&i2c3 {
	status = "disabled";
};

&dspi {
	status = "okay";
	dflash0: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p80";
		spi-max-frequency = <3000000>;
		reg = <0>;
	};
};

&qspi {
	status = "okay";

	s25fs512s0: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		spi-max-frequency = <50000000>;
		reg = <0>;
	};
};

&sata0 {
	status = "okay";
};

&sata1 {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017-2020 NXP
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 *
 */

#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "fsl,ls2080a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		crypto = &crypto;
		rtc1 = &ftm_alarm0;
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serial3;
	};

	cpu: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x80000000>;
		      /* DRAM space - 1, size : 2 GB DRAM */
	};

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	gic: interrupt-controller@6000000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
			<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
			<0x0 0x0c0c0000 0 0x2000>, /* GICC */
			<0x0 0x0c0d0000 0 0x1000>, /* GICH */
			<0x0 0x0c0e0000 0 0x20000>; /* GICV */
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-controller;
		interrupts = <1 9 0x4>;

		its: gic-its@6020000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0x6020000 0 0x20000>;
		};
	};

	rstcr: syscon@1e60000 {
		compatible = "fsl,ls2080a-rstcr", "syscon";
		reg = <0x0 0x1e60000 0x0 0x4>;
	};

	reboot {
		compatible = "syscon-reboot";
		regmap = <&rstcr>;
		offset = <0x0>;
		mask = <0x2>;
	};

	thermal-zones {
		ddr-controller1 {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 1>;

			trips {
				ddr-ctrler1-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		ddr-controller2 {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 2>;

			trips {
				ddr-ctrler2-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		ddr-controller3 {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 3>;

			trips {
				ddr-ctrler3-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		core-cluster1 {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 4>;

			trips {
				core_cluster1_alert: core-cluster1-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				core-cluster1-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&core_cluster1_alert>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		core-cluster2 {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 5>;

			trips {
				core_cluster2_alert: core-cluster2-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				core-cluster2-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&core_cluster2_alert>;
					cooling-device =
						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		core-cluster3 {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 6>;

			trips {
				core_cluster3_alert: core-cluster3-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				core-cluster3-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&core_cluster3_alert>;
					cooling-device =
						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		core-cluster4 {
			polling-delay-passive = <1000>;
			polling-delay = <5000>;
			thermal-sensors = <&tmu 7>;

			trips {
				core_cluster4_alert: core-cluster4-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				core-cluster4-crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&core_cluster4_alert>;
					cooling-device =
						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
			     <1 11 4>, /* Virtual PPI, active-low */
			     <1 10 4>; /* Hypervisor PPI, active-low */
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;

		clockgen: clocking@1300000 {
			compatible = "fsl,ls2080a-clockgen";
			reg = <0 0x1300000 0 0xa0000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		dcfg: dcfg@1e00000 {
			compatible = "fsl,ls2080a-dcfg", "syscon";
			reg = <0x0 0x1e00000 0x0 0x10000>;
			little-endian;
		};

		sfp: efuse@1e80000 {
			compatible = "fsl,ls1028a-sfp";
			reg = <0x0 0x1e80000 0x0 0x10000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "sfp";
		};

		isc: syscon@1f70000 {
			compatible = "fsl,ls2080a-isc", "syscon";
			reg = <0x0 0x1f70000 0x0 0x10000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x0 0x1f70000 0x10000>;

			extirq: interrupt-controller@14 {
				compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
				#interrupt-cells = <2>;
				#address-cells = <0>;
				interrupt-controller;
				reg = <0x14 4>;
				interrupt-map =
					<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
					<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
					<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
					<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
					<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
					<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
					<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
					<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
					<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
					<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
					<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-map-mask = <0xf 0x0>;
			};
		};

		tmu: tmu@1f80000 {
			compatible = "fsl,qoriq-tmu";
			reg = <0x0 0x1f80000 0x0 0x10000>;
			interrupts = <0 23 0x4>;
			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
			fsl,tmu-calibration = <0x00000000 0x00000026
					       0x00000001 0x0000002d
					       0x00000002 0x00000032
					       0x00000003 0x00000039
					       0x00000004 0x0000003f
					       0x00000005 0x00000046
					       0x00000006 0x0000004d
					       0x00000007 0x00000054
					       0x00000008 0x0000005a
					       0x00000009 0x00000061
					       0x0000000a 0x0000006a
					       0x0000000b 0x00000071

					       0x00010000 0x00000025
					       0x00010001 0x0000002c
					       0x00010002 0x00000035
					       0x00010003 0x0000003d
					       0x00010004 0x00000045
					       0x00010005 0x0000004e
					       0x00010006 0x00000057
					       0x00010007 0x00000061
					       0x00010008 0x0000006b
					       0x00010009 0x00000076

					       0x00020000 0x00000029
					       0x00020001 0x00000033
					       0x00020002 0x0000003d
					       0x00020003 0x00000049
					       0x00020004 0x00000056
					       0x00020005 0x00000061
					       0x00020006 0x0000006d

					       0x00030000 0x00000021
					       0x00030001 0x0000002a
					       0x00030002 0x0000003c
					       0x00030003 0x0000004e>;
			little-endian;
			#thermal-sensor-cells = <1>;
		};

		serial0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21c0500 0x0 0x100>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			interrupts = <0 32 0x4>; /* Level high type */
		};

		serial1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21c0600 0x0 0x100>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			interrupts = <0 32 0x4>; /* Level high type */
		};

		serial2: serial@21d0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0500 0x0 0x100>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			interrupts = <0 33 0x4>; /* Level high type */
		};

		serial3: serial@21d0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0600 0x0 0x100>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			interrupts = <0 33 0x4>; /* Level high type */
		};

		cluster1_core0_watchdog: wdt@c000000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc000000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster1_core1_watchdog: wdt@c010000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc010000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster2_core0_watchdog: wdt@c100000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc100000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster2_core1_watchdog: wdt@c110000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc110000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster3_core0_watchdog: wdt@c200000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc200000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster3_core1_watchdog: wdt@c210000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc210000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster4_core0_watchdog: wdt@c300000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc300000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		cluster4_core1_watchdog: wdt@c310000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x0 0xc310000 0x0 0x1000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "wdog_clk", "apb_pclk";
		};

		crypto: crypto@8000000 {
			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
			fsl,sec-era = <8>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x00 0x8000000 0x100000>;
			reg = <0x00 0x8000000 0x0 0x100000>;
			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
			dma-coherent;

			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x10000 0x10000>;
				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x20000 0x10000>;
				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x30000 0x10000>;
				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg = <0x40000 0x10000>;
				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		console@8340020 {
			compatible = "fsl,dpaa2-console";
			reg = <0x00000000 0x08340020 0 0x2>;
		};

		ptp-timer@8b95000 {
			compatible = "fsl,dpaa2-ptp";
			reg = <0x0 0x8b95000 0x0 0x100>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			little-endian;
			fsl,extts-fifo;
		};

		emdio1: mdio@8b96000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8b96000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <2500000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		emdio2: mdio@8b97000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8b97000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <2500000>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			status = "disabled";
		};

		pcs_mdio1: mdio@8c07000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c07000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs1: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio2: mdio@8c0b000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c0b000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs2: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio3: mdio@8c0f000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c0f000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs3: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio4: mdio@8c13000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c13000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs4: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio5: mdio@8c17000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c17000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs5: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio6: mdio@8c1b000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c1b000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs6: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio7: mdio@8c1f000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c1f000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs7: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio8: mdio@8c23000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c23000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs8: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio9: mdio@8c27000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c27000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs9: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio10: mdio@8c2b000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c2b000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs10: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio11: mdio@8c2f000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c2f000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs11: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio12: mdio@8c33000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c33000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs12: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio13: mdio@8c37000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c37000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs13: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio14: mdio@8c3b000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c3b000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs14: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio15: mdio@8c3f000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c3f000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs15: ethernet-phy@0 {
				reg = <0>;
			};
		};

		pcs_mdio16: mdio@8c43000 {
			compatible = "fsl,fman-memac-mdio";
			reg = <0x0 0x8c43000 0x0 0x1000>;
			little-endian;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pcs16: ethernet-phy@0 {
				reg = <0>;
			};
		};

		fsl_mc: fsl-mc@80c000000 {
			compatible = "fsl,qoriq-mc";
			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
			msi-parent = <&its>;
			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
			dma-coherent;
			#address-cells = <3>;
			#size-cells = <1>;

			/*
			 * Region type 0x0 - MC portals
			 * Region type 0x1 - QBMAN portals
			 */
			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;

			/*
			 * Define the maximum number of MACs present on the SoC.
			 */
			dpmacs {
				#address-cells = <1>;
				#size-cells = <0>;

				dpmac1: ethernet@1 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0x1>;
					pcs-handle = <&pcs1>;
				};

				dpmac2: ethernet@2 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0x2>;
					pcs-handle = <&pcs2>;
				};

				dpmac3: ethernet@3 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0x3>;
					pcs-handle = <&pcs3>;
				};

				dpmac4: ethernet@4 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0x4>;
					pcs-handle = <&pcs4>;
				};

				dpmac5: ethernet@5 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0x5>;
					pcs-handle = <&pcs5>;
				};

				dpmac6: ethernet@6 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0x6>;
					pcs-handle = <&pcs6>;
				};

				dpmac7: ethernet@7 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0x7>;
					pcs-handle = <&pcs7>;
				};

				dpmac8: ethernet@8 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0x8>;
					pcs-handle = <&pcs8>;
				};

				dpmac9: ethernet@9 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0x9>;
					pcs-handle = <&pcs9>;
				};

				dpmac10: ethernet@a {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0xa>;
					pcs-handle = <&pcs10>;
				};

				dpmac11: ethernet@b {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0xb>;
					pcs-handle = <&pcs11>;
				};

				dpmac12: ethernet@c {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0xc>;
					pcs-handle = <&pcs12>;
				};

				dpmac13: ethernet@d {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0xd>;
					pcs-handle = <&pcs13>;
				};

				dpmac14: ethernet@e {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0xe>;
					pcs-handle = <&pcs14>;
				};

				dpmac15: ethernet@f {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0xf>;
					pcs-handle = <&pcs15>;
				};

				dpmac16: ethernet@10 {
					compatible = "fsl,qoriq-mc-dpmac";
					reg = <0x10>;
					pcs-handle = <&pcs16>;
				};
			};
		};

		smmu: iommu@5000000 {
			compatible = "arm,mmu-500";
			reg = <0 0x5000000 0 0x800000>;
			#global-interrupts = <12>;
			#iommu-cells = <1>;
			stream-match-mask = <0x7C00>;
			dma-coherent;
			interrupts = <0 13 4>, /* global secure fault */
				     <0 14 4>, /* combined secure interrupt */
				     <0 15 4>, /* global non-secure fault */
				     <0 16 4>, /* combined non-secure interrupt */
				/* performance counter interrupts 0-7 */
				     <0 211 4>, <0 212 4>,
				     <0 213 4>, <0 214 4>,
				     <0 215 4>, <0 216 4>,
				     <0 217 4>, <0 218 4>,
				/* per context interrupt, 64 interrupts */
				     <0 146 4>, <0 147 4>,
				     <0 148 4>, <0 149 4>,
				     <0 150 4>, <0 151 4>,
				     <0 152 4>, <0 153 4>,
				     <0 154 4>, <0 155 4>,
				     <0 156 4>, <0 157 4>,
				     <0 158 4>, <0 159 4>,
				     <0 160 4>, <0 161 4>,
				     <0 162 4>, <0 163 4>,
				     <0 164 4>, <0 165 4>,
				     <0 166 4>, <0 167 4>,
				     <0 168 4>, <0 169 4>,
				     <0 170 4>, <0 171 4>,
				     <0 172 4>, <0 173 4>,
				     <0 174 4>, <0 175 4>,
				     <0 176 4>, <0 177 4>,
				     <0 178 4>, <0 179 4>,
				     <0 180 4>, <0 181 4>,
				     <0 182 4>, <0 183 4>,
				     <0 184 4>, <0 185 4>,
				     <0 186 4>, <0 187 4>,
				     <0 188 4>, <0 189 4>,
				     <0 190 4>, <0 191 4>,
				     <0 192 4>, <0 193 4>,
				     <0 194 4>, <0 195 4>,
				     <0 196 4>, <0 197 4>,
				     <0 198 4>, <0 199 4>,
				     <0 200 4>, <0 201 4>,
				     <0 202 4>, <0 203 4>,
				     <0 204 4>, <0 205 4>,
				     <0 206 4>, <0 207 4>,
				     <0 208 4>, <0 209 4>;
		};

		dspi: spi@2100000 {
			status = "disabled";
			compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <0 26 0x4>; /* Level high type */
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "dspi";
			spi-num-chipselects = <5>;
		};

		esdhc: esdhc@2140000 {
			status = "disabled";
			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
			reg = <0x0 0x2140000 0x0 0x10000>;
			interrupts = <0 28 0x4>; /* Level high type */
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(2)>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			little-endian;
			bus-width = <4>;
		};

		gpio0: gpio@2300000 {
			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <0 36 0x4>; /* Level high type */
			gpio-controller;
			little-endian;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@2310000 {
			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <0 36 0x4>; /* Level high type */
			gpio-controller;
			little-endian;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2320000 {
			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <0 37 0x4>; /* Level high type */
			gpio-controller;
			little-endian;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2330000 {
			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2330000 0x0 0x10000>;
			interrupts = <0 37 0x4>; /* Level high type */
			gpio-controller;
			little-endian;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		i2c0: i2c@2000000 {
			status = "disabled";
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2000000 0x0 0x10000>;
			interrupts = <0 34 0x4>; /* Level high type */
			clock-names = "i2c";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
		};

		i2c1: i2c@2010000 {
			status = "disabled";
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2010000 0x0 0x10000>;
			interrupts = <0 34 0x4>; /* Level high type */
			clock-names = "i2c";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
		};

		i2c2: i2c@2020000 {
			status = "disabled";
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2020000 0x0 0x10000>;
			interrupts = <0 35 0x4>; /* Level high type */
			clock-names = "i2c";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
		};

		i2c3: i2c@2030000 {
			status = "disabled";
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2030000 0x0 0x10000>;
			interrupts = <0 35 0x4>; /* Level high type */
			clock-names = "i2c";
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
		};

		ifc: memory-controller@2240000 {
			compatible = "fsl,ifc";
			reg = <0x0 0x2240000 0x0 0x20000>;
			interrupts = <0 21 0x4>; /* Level high type */
			little-endian;
			#address-cells = <2>;
			#size-cells = <1>;

			ranges = <0 0 0x5 0x80000000 0x08000000
				  2 0 0x5 0x30000000 0x00010000
				  3 0 0x5 0x20000000 0x00010000>;
		};

		qspi: spi@20c0000 {
			compatible = "fsl,ls2080a-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x20c0000 0x0 0x10000>,
			      <0x0 0x20000000 0x0 0x10000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>,
				 <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			clock-names = "qspi_en", "qspi";
			status = "disabled";
		};

		pcie1: pcie@3400000 {
			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
			reg-names = "regs", "config";
			interrupts = <0 108 0x4>; /* Level high type */
			interrupt-names = "intr";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			num-viewport = <6>;
			bus-range = <0x0 0xff>;
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
					<0000 0 0 2 &gic 0 0 0 110 4>,
					<0000 0 0 3 &gic 0 0 0 111 4>,
					<0000 0 0 4 &gic 0 0 0 112 4>;
			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
			status = "disabled";
		};

		pcie2: pcie@3500000 {
			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
			reg-names = "regs", "config";
			interrupts = <0 113 0x4>; /* Level high type */
			interrupt-names = "intr";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			num-viewport = <6>;
			bus-range = <0x0 0xff>;
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
					<0000 0 0 2 &gic 0 0 0 115 4>,
					<0000 0 0 3 &gic 0 0 0 116 4>,
					<0000 0 0 4 &gic 0 0 0 117 4>;
			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
			status = "disabled";
		};

		pcie3: pcie@3600000 {
			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
			reg-names = "regs", "config";
			interrupts = <0 118 0x4>; /* Level high type */
			interrupt-names = "intr";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			num-viewport = <256>;
			bus-range = <0x0 0xff>;
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
					<0000 0 0 2 &gic 0 0 0 120 4>,
					<0000 0 0 3 &gic 0 0 0 121 4>,
					<0000 0 0 4 &gic 0 0 0 122 4>;
			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
			status = "disabled";
		};

		pcie4: pcie@3700000 {
			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
			reg-names = "regs", "config";
			interrupts = <0 123 0x4>; /* Level high type */
			interrupt-names = "intr";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			dma-coherent;
			num-viewport = <6>;
			bus-range = <0x0 0xff>;
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
					<0000 0 0 2 &gic 0 0 0 125 4>,
					<0000 0 0 3 &gic 0 0 0 126 4>,
					<0000 0 0 4 &gic 0 0 0 127 4>;
			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
			status = "disabled";
		};

		sata0: sata@3200000 {
			status = "disabled";
			compatible = "fsl,ls2080a-ahci";
			reg = <0x0 0x3200000 0x0 0x10000>;
			interrupts = <0 133 0x4>; /* Level high type */
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			dma-coherent;
		};

		sata1: sata@3210000 {
			status = "disabled";
			compatible = "fsl,ls2080a-ahci";
			reg = <0x0 0x3210000 0x0 0x10000>;
			interrupts = <0 136 0x4>; /* Level high type */
			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
					    QORIQ_CLK_PLL_DIV(4)>;
			dma-coherent;
		};

		usb0: usb@3100000 {
			status = "disabled";
			compatible = "snps,dwc3";
			reg = <0x0 0x3100000 0x0 0x10000>;
			interrupts = <0 80 0x4>; /* Level high type */
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
			snps,dis_rxdet_inp3_quirk;
			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
		};

		usb1: usb@3110000 {
			status = "disabled";
			compatible = "snps,dwc3";
			reg = <0x0 0x3110000 0x0 0x10000>;
			interrupts = <0 81 0x4>; /* Level high type */
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
			snps,dis_rxdet_inp3_quirk;
			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
		};

		ccn@4000000 {
			compatible = "arm,ccn-504";
			reg = <0x0 0x04000000 0x0 0x01000000>;
			interrupts = <0 12 4>;
		};

		rcpm: power-controller@1e34040 {
			compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
			reg = <0x0 0x1e34040 0x0 0x18>;
			#fsl,rcpm-wakeup-cells = <6>;
			little-endian;
		};

		ftm_alarm0: timer@2800000 {
			compatible = "fsl,ls208xa-ftm-alarm";
			reg = <0x0 0x2800000 0x0 0x10000>;
			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	ddr1: memory-controller@1080000 {
		compatible = "fsl,qoriq-memory-controller";
		reg = <0x0 0x1080000 0x0 0x1000>;
		interrupts = <0 17 0x4>;
		little-endian;
	};

	ddr2: memory-controller@1090000 {
		compatible = "fsl,qoriq-memory-controller";
		reg = <0x0 0x1090000 0x0 0x1000>;
		interrupts = <0 18 0x4>;
		little-endian;
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160A BLUEBOX3
//
// Copyright 2020-2021 NXP

/dts-v1/;

#include "fsl-lx2160a-bluebox3.dts"

/ {
	compatible = "fsl,lx2160a-bluebox3-rev-a", "fsl,lx2160a";
};

/* The RGMII PHYs have a different MDIO address */
&emdio1 {
	/delete-node/ ethernet-phy@5;

	sw1_mii3_phy: ethernet-phy@1 {
		/* AR8035 */
		compatible = "ethernet-phy-id004d.d072";
		reg = <0x1>;
		interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>;
	};

	/delete-node/ ethernet-phy@6;

	sw2_mii3_phy: ethernet-phy@2 {
		/* AR8035 */
		compatible = "ethernet-phy-id004d.d072";
		reg = <0x2>;
		interrupts-extended = <&extirq 7 IRQ_TYPE_LEVEL_LOW>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160A BLUEBOX3
//
// Copyright 2020-2021 NXP

/dts-v1/;

#include "fsl-lx2160a.dtsi"

/ {
	model = "NXP Layerscape LX2160ABLUEBOX3";
	compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";

	aliases {
		crypto = &crypto;
		mmc0 = &esdhc0;
		mmc1 = &esdhc1;
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	sb_3v3: regulator-sb3v3 {
		compatible = "regulator-fixed";
		regulator-name = "MC34717-3.3VSB";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&can0 {
	status = "okay";

	can-transceiver {
		max-bitrate = <5000000>;
	};
};

&can1 {
	status = "okay";

	can-transceiver {
		max-bitrate = <5000000>;
	};
};

&crypto {
	status = "okay";
};

&dpmac5 {
	phy-handle = <&aqr113c_phy1>;
	phy-mode = "usxgmii";
	managed = "in-band-status";
};

&dpmac6 {
	phy-handle = <&aqr113c_phy2>;
	phy-mode = "usxgmii";
	managed = "in-band-status";
};

&dpmac9 {
	phy-handle = <&aqr113c_phy3>;
	phy-mode = "usxgmii";
	managed = "in-band-status";
};

&dpmac10 {
	phy-handle = <&aqr113c_phy4>;
	phy-mode = "usxgmii";
	managed = "in-band-status";
};

&dpmac17 {
	phy-mode = "rgmii";
	status = "okay";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&dpmac18 {
	phy-mode = "rgmii";
	status = "okay";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

&emdio1 {
	status = "okay";

	aqr113c_phy2: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <0x0>;
		/* IRQ_10G_PHY2 */
		interrupts-extended = <&extirq 3 IRQ_TYPE_LEVEL_LOW>;
	};

	aqr113c_phy1: ethernet-phy@8 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <0x8>;
		/* IRQ_10G_PHY1 */
		interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
	};

	sw1_mii3_phy: ethernet-phy@5 {
		/* AR8035 */
		compatible = "ethernet-phy-id004d.d072";
		reg = <0x5>;
		interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>;
	};

	sw2_mii3_phy: ethernet-phy@6 {
		/* AR8035 */
		compatible = "ethernet-phy-id004d.d072";
		reg = <0x6>;
		interrupts-extended = <&extirq 7 IRQ_TYPE_LEVEL_LOW>;
	};
};

&emdio2 {
	status = "okay";

	aqr113c_phy4: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <0x0>;
		/* IRQ_10G_PHY4 */
		interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
	};

	aqr113c_phy3: ethernet-phy@8 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <0x8>;
		/* IRQ_10G_PHY3 */
		interrupts-extended = <&extirq 4 IRQ_TYPE_LEVEL_LOW>;
	};
};

&esdhc0 {
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
	status = "okay";
};

&esdhc1 {
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
	status = "okay";
};

&fspi {
	status = "okay";

	mt35xu512aba0: flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		m25p,fast-read;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <8>;
		spi-tx-bus-width = <8>;
	};

	mt35xu512aba1: flash@1 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <1>;
		m25p,fast-read;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <8>;
		spi-tx-bus-width = <8>;
	};
};

&i2c0 {
	status = "okay";

	i2c-mux@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			power-monitor@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <500>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			temp2: temperature-sensor@48 {
				compatible = "nxp,sa56004";
				reg = <0x48>;
				vcc-supply = <&sb_3v3>;
				#thermal-sensor-cells = <1>;
			};

			temp1: temperature-sensor@4c {
				compatible = "nxp,sa56004";
				reg = <0x4c>;
				vcc-supply = <&sb_3v3>;
				#thermal-sensor-cells = <1>;
			};
		};

		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x4>;

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
				interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>;
			};
		};

		i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x7>;

			i2c-mux@75 {
				compatible = "nxp,pca9547";
				reg = <0x75>;
				#address-cells = <1>;
				#size-cells = <0>;

				i2c@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0x0>;

					spi_bridge: spi@28 {
						compatible = "nxp,sc18is602b";
						reg = <0x28>;
						#address-cells = <1>;
						#size-cells = <0>;
					};
				};
			};
		};
	};
};

&i2c5 {
	status = "okay";

	i2c-mux@77 {
		compatible = "nxp,pca9846";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x1>;

			/* The I2C multiplexer and temperature sensors are on
			 * the T6 riser card.
			 */
			i2c-mux@70 {
				compatible = "nxp,pca9548";
				reg = <0x70>;
				#address-cells = <1>;
				#size-cells = <0>;

				i2c@6 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0x6>;

					q12: temperature-sensor@4c {
						compatible = "nxp,sa56004";
						reg = <0x4c>;
						vcc-supply = <&sb_3v3>;
						#thermal-sensor-cells = <1>;
					};
				};

				i2c@7 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0x7>;

					q11: temperature-sensor@4c {
						compatible = "nxp,sa56004";
						reg = <0x4c>;
						vcc-supply = <&sb_3v3>;
						#thermal-sensor-cells = <1>;
					};

					q13: temperature-sensor@48 {
						compatible = "nxp,sa56004";
						reg = <0x48>;
						vcc-supply = <&sb_3v3>;
						#thermal-sensor-cells = <1>;
					};

					q14: temperature-sensor@4a {
						compatible = "nxp,sa56004";
						reg = <0x4a>;
						vcc-supply = <&sb_3v3>;
						#thermal-sensor-cells = <1>;
					};
				};
			};
		};
	};
};

&pcs_mdio5 {
	status = "okay";
};

&pcs_mdio6 {
	status = "okay";
};

&pcs_mdio9 {
	status = "okay";
};

&pcs_mdio10 {
	status = "okay";
};

&spi_bridge {
	sw1: ethernet-switch@0 {
		compatible = "nxp,sja1110a";
		reg = <0>;
		spi-max-frequency = <4000000>;
		spi-cpol;
		dsa,member = <0 0>;

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* Microcontroller port */
			port@0 {
				reg = <0>;
				status = "disabled";
			};

			/* SW1_P1 */
			port@1 {
				reg = <1>;
				label = "con_2x20";
				phy-mode = "sgmii";

				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			port@2 {
				reg = <2>;
				ethernet = <&dpmac17>;
				phy-mode = "rgmii-id";
				rx-internal-delay-ps = <2000>;
				tx-internal-delay-ps = <2000>;

				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			port@3 {
				reg = <3>;
				label = "1ge_p1";
				phy-mode = "rgmii-id";
				phy-handle = <&sw1_mii3_phy>;
			};

			sw1p4: port@4 {
				reg = <4>;
				link = <&sw2p1>;
				phy-mode = "sgmii";

				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			port@5 {
				reg = <5>;
				label = "trx1";
				phy-mode = "internal";
				phy-handle = <&sw1_port5_base_t1_phy>;
			};

			port@6 {
				reg = <6>;
				label = "trx2";
				phy-mode = "internal";
				phy-handle = <&sw1_port6_base_t1_phy>;
			};

			port@7 {
				reg = <7>;
				label = "trx3";
				phy-mode = "internal";
				phy-handle = <&sw1_port7_base_t1_phy>;
			};

			port@8 {
				reg = <8>;
				label = "trx4";
				phy-mode = "internal";
				phy-handle = <&sw1_port8_base_t1_phy>;
			};

			port@9 {
				reg = <9>;
				label = "trx5";
				phy-mode = "internal";
				phy-handle = <&sw1_port9_base_t1_phy>;
			};

			port@a {
				reg = <10>;
				label = "trx6";
				phy-mode = "internal";
				phy-handle = <&sw1_port10_base_t1_phy>;
			};
		};

		mdios {
			#address-cells = <1>;
			#size-cells = <0>;

			mdio@0 {
				compatible = "nxp,sja1110-base-t1-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;

				sw1_port5_base_t1_phy: ethernet-phy@1 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x1>;
				};

				sw1_port6_base_t1_phy: ethernet-phy@2 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x2>;
				};

				sw1_port7_base_t1_phy: ethernet-phy@3 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x3>;
				};

				sw1_port8_base_t1_phy: ethernet-phy@4 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x4>;
				};

				sw1_port9_base_t1_phy: ethernet-phy@5 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x5>;
				};

				sw1_port10_base_t1_phy: ethernet-phy@6 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x6>;
				};
			};
		};
	};

	sw2: ethernet-switch@2 {
		compatible = "nxp,sja1110a";
		reg = <2>;
		spi-max-frequency = <4000000>;
		spi-cpol;
		dsa,member = <0 1>;

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			/* Microcontroller port */
			port@0 {
				reg = <0>;
				status = "disabled";
			};

			sw2p1: port@1 {
				reg = <1>;
				link = <&sw1p4>;
				phy-mode = "sgmii";

				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			port@2 {
				reg = <2>;
				ethernet = <&dpmac18>;
				phy-mode = "rgmii-id";
				rx-internal-delay-ps = <2000>;
				tx-internal-delay-ps = <2000>;

				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			port@3 {
				reg = <3>;
				label = "1ge_p2";
				phy-mode = "rgmii-id";
				phy-handle = <&sw2_mii3_phy>;
			};

			port@4 {
				reg = <4>;
				label = "to_sw3";
				phy-mode = "2500base-x";

				fixed-link {
					speed = <2500>;
					full-duplex;
				};
			};

			port@5 {
				reg = <5>;
				label = "trx7";
				phy-mode = "internal";
				phy-handle = <&sw2_port5_base_t1_phy>;
			};

			port@6 {
				reg = <6>;
				label = "trx8";
				phy-mode = "internal";
				phy-handle = <&sw2_port6_base_t1_phy>;
			};

			port@7 {
				reg = <7>;
				label = "trx9";
				phy-mode = "internal";
				phy-handle = <&sw2_port7_base_t1_phy>;
			};

			port@8 {
				reg = <8>;
				label = "trx10";
				phy-mode = "internal";
				phy-handle = <&sw2_port8_base_t1_phy>;
			};

			port@9 {
				reg = <9>;
				label = "trx11";
				phy-mode = "internal";
				phy-handle = <&sw2_port9_base_t1_phy>;
			};

			port@a {
				reg = <10>;
				label = "trx12";
				phy-mode = "internal";
				phy-handle = <&sw2_port10_base_t1_phy>;
			};
		};

		mdios {
			#address-cells = <1>;
			#size-cells = <0>;

			mdio@0 {
				compatible = "nxp,sja1110-base-t1-mdio";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;

				sw2_port5_base_t1_phy: ethernet-phy@1 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x1>;
				};

				sw2_port6_base_t1_phy: ethernet-phy@2 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x2>;
				};

				sw2_port7_base_t1_phy: ethernet-phy@3 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x3>;
				};

				sw2_port8_base_t1_phy: ethernet-phy@4 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x4>;
				};

				sw2_port9_base_t1_phy: ethernet-phy@5 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x5>;
				};

				sw2_port10_base_t1_phy: ethernet-phy@6 {
					compatible = "ethernet-phy-ieee802.3-c45";
					reg = <0x6>;
				};
			};
		};
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160A-CEx7
//
// Copyright 2019 SolidRun Ltd.

/dts-v1/;

#include "fsl-lx2160a.dtsi"

/ {
	model = "SolidRun LX2160A COM Express Type 7 module";
	compatible = "solidrun,lx2160a-cex7", "fsl,lx2160a";

	aliases {
		crypto = &crypto;
	};

	sb_3v3: regulator-sb3v3 {
		compatible = "regulator-fixed";
		regulator-name = "RT7290";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&crypto {
	status = "okay";
};

&dpmac17 {
	phy-handle = <&rgmii_phy1>;
	phy-connection-type = "rgmii-id";
};

&emdio1 {
	status = "okay";

	rgmii_phy1: ethernet-phy@1 {
		reg = <1>;
		qca,smarteee-tw-us-1g = <24>;
	};
};

&esdhc1 {
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
	status = "okay";
};

&i2c0 {
	status = "okay";

	i2c-switch@77 {
		compatible = "nxp,pca9547";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x77>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			eeprom@50 {
				compatible = "atmel,24c512";
				reg = <0x50>;
			};

			eeprom@51 {
				compatible = "atmel,spd";
				reg = <0x51>;
			};

			eeprom@53 {
				compatible = "atmel,spd";
				reg = <0x53>;
			};

			eeprom@57 {
				compatible = "atmel,24c02";
				reg = <0x57>;
			};
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			fan-temperature-ctrlr@18 {
				compatible = "ti,amc6821";
				reg = <0x18>;
				cooling-min-state = <0>;
				cooling-max-state = <9>;
				#cooling-cells = <2>;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;

			regulator@5c {
				compatible = "lltc,ltc3882";
				reg = <0x5c>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;

			temperature-sensor@48 {
				compatible = "nxp,sa56004";
				reg = <0x48>;
				vcc-supply = <&sb_3v3>;
			};
		};

		sfp0_i2c: i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
		};

		sfp1_i2c: i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
		};

		sfp2_i2c: i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
		};

		sfp3_i2c: i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <7>;
		};
	};
};

&i2c2 {
	status = "okay";
};

&i2c4 {
	status = "okay";

	rtc@51 {
		compatible = "nxp,pcf2129";
		reg = <0x51>;
	};
};

&fspi {
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,m25p80";
		m25p,fast-read;
		spi-max-frequency = <50000000>;
		reg = <0>;
		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
		spi-rx-bus-width = <8>;
		spi-tx-bus-width = <1>;
	};
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160A Clearfog CX board
//
// Copyright 2019 SolidRun Ltd.

/dts-v1/;

#include "fsl-lx2160a-clearfog-itx.dtsi"

/ {
	model = "SolidRun LX2160A Clearfog CX";
	compatible = "solidrun,clearfog-cx",
		"solidrun,lx2160a-cex7", "fsl,lx2160a";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160A Clearfog ITX board; this contains the
// common parts shared between the Clearfog CX and Honeycomb builds.
//
// Copyright 2019 SolidRun Ltd.

/dts-v1/;

#include "fsl-lx2160a-cex7.dtsi"
#include <dt-bindings/input/linux-event-codes.h>

/ {
	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	gpio-keys {
		compatible = "gpio-keys";

		key {
			label = "power";
			linux,can-disable;
			linux,code = <KEY_POWER>;
			gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
		};
	};

	sfp0: sfp-0 {
		compatible = "sff,sfp";
		i2c-bus = <&sfp0_i2c>;
		mod-def0-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
		maximum-power-milliwatt = <2000>;
	};

	sfp1: sfp-1 {
		compatible = "sff,sfp";
		i2c-bus = <&sfp1_i2c>;
		mod-def0-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
		maximum-power-milliwatt = <2000>;
	};

	sfp2: sfp-2 {
		compatible = "sff,sfp";
		i2c-bus = <&sfp2_i2c>;
		mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
		maximum-power-milliwatt = <2000>;
	};

	sfp3: sfp-3 {
		compatible = "sff,sfp";
		i2c-bus = <&sfp3_i2c>;
		mod-def0-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
		maximum-power-milliwatt = <2000>;
	};
};

&dpmac7 {
	sfp = <&sfp0>;
	managed = "in-band-status";
	phys = <&serdes_1 3>;
};

&dpmac8 {
	sfp = <&sfp1>;
	managed = "in-band-status";
	phys = <&serdes_1 2>;
};

&dpmac9 {
	sfp = <&sfp2>;
	managed = "in-band-status";
	phys = <&serdes_1 1>;
};

&dpmac10 {
	sfp = <&sfp3>;
	managed = "in-band-status";
	phys = <&serdes_1 0>;
};

&emdio2 {
	status = "okay";
};

&esdhc0 {
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
	status = "okay";
};

&pcs_mdio7 {
	status = "okay";
};

&pcs_mdio8 {
	status = "okay";
};

&pcs_mdio9 {
	status = "okay";
};

&pcs_mdio10 {
	status = "okay";
};

&sata0 {
	status = "okay";
};

&sata1 {
	status = "okay";
};

&sata2 {
	status = "okay";
};

&sata3 {
	status = "okay";
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160A Honeycomb board
//
// Copyright 2019 SolidRun Ltd.

/dts-v1/;

#include "fsl-lx2160a-clearfog-itx.dtsi"

/ {
	model = "SolidRun LX2160A Honeycomb";
	compatible = "solidrun,honeycomb",
		"solidrun,lx2160a-cex7", "fsl,lx2160a";
};