code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/power/imx8mp-power.h>
#include <dt-bindings/reset/imx8mp-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interconnect/fsl,imx8mp.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

#include "imx8mp-pinfunc.h"

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &fec;
		ethernet1 = &eqos;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		i2c4 = &i2c5;
		i2c5 = &i2c6;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		spi0 = &flexspi;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		A53_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			clock-latency = <61036>;
			clocks = <&clk IMX8MP_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			nvmem-cells = <&cpu_speed_grade>;
			nvmem-cell-names = "speed_grade";
			operating-points-v2 = <&a53_opp_table>;
			#cooling-cells = <2>;
		};

		A53_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			clock-latency = <61036>;
			clocks = <&clk IMX8MP_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			#cooling-cells = <2>;
		};

		A53_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			clock-latency = <61036>;
			clocks = <&clk IMX8MP_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			#cooling-cells = <2>;
		};

		A53_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			clock-latency = <61036>;
			clocks = <&clk IMX8MP_CLK_ARM>;
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&A53_L2>;
			operating-points-v2 = <&a53_opp_table>;
			#cooling-cells = <2>;
		};

		A53_L2: l2-cache0 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>;
		};
	};

	a53_opp_table: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <850000>;
			opp-supported-hw = <0x8a0>, <0x7>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};

		opp-1600000000 {
			opp-hz = /bits/ 64 <1600000000>;
			opp-microvolt = <950000>;
			opp-supported-hw = <0xa0>, <0x7>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};

		opp-1800000000 {
			opp-hz = /bits/ 64 <1800000000>;
			opp-microvolt = <1000000>;
			opp-supported-hw = <0x20>, <0x3>;
			clock-latency-ns = <150000>;
			opp-suspend;
		};
	};

	osc_32k: clock-osc-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "osc_32k";
	};

	osc_24m: clock-osc-24m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc_24m";
	};

	clk_ext1: clock-ext1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext1";
	};

	clk_ext2: clock-ext2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext2";
	};

	clk_ext3: clock-ext3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext3";
	};

	clk_ext4: clock-ext4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext4";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dsp_reserved: dsp@92400000 {
			reg = <0 0x92400000 0 0x2000000>;
			no-map;
		};
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7
			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tmu 0>;
			trips {
				cpu_alert0: trip0 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit0: trip1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		soc-thermal {
			polling-delay-passive = <250>;
			polling-delay = <2000>;
			thermal-sensors = <&tmu 1>;
			trips {
				soc_alert0: trip0 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				soc_crit0: trip1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&soc_alert0>;
					cooling-device =
						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <8000000>;
		arm,no-tick-in-suspend;
	};

	soc: soc@0 {
		compatible = "fsl,imx8mp-soc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x3e000000>;
		nvmem-cells = <&imx8mp_uid>;
		nvmem-cell-names = "soc_unique_id";

		aips1: bus@30000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x30000000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gpio1: gpio@30200000 {
				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
				reg = <0x30200000 0x10000>;
				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 5 30>;
			};

			gpio2: gpio@30210000 {
				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
				reg = <0x30210000 0x10000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 35 21>;
			};

			gpio3: gpio@30220000 {
				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
				reg = <0x30220000 0x10000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
			};

			gpio4: gpio@30230000 {
				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
				reg = <0x30230000 0x10000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 82 32>;
			};

			gpio5: gpio@30240000 {
				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
				reg = <0x30240000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 114 30>;
			};

			tmu: tmu@30260000 {
				compatible = "fsl,imx8mp-tmu";
				reg = <0x30260000 0x10000>;
				clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
				#thermal-sensor-cells = <1>;
			};

			wdog1: watchdog@30280000 {
				compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
				reg = <0x30280000 0x10000>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
				status = "disabled";
			};

			wdog2: watchdog@30290000 {
				compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
				reg = <0x30290000 0x10000>;
				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
				status = "disabled";
			};

			wdog3: watchdog@302a0000 {
				compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
				reg = <0x302a0000 0x10000>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
				status = "disabled";
			};

			iomuxc: pinctrl@30330000 {
				compatible = "fsl,imx8mp-iomuxc";
				reg = <0x30330000 0x10000>;
			};

			gpr: iomuxc-gpr@30340000 {
				compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
				reg = <0x30340000 0x10000>;
			};

			ocotp: efuse@30350000 {
				compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
				reg = <0x30350000 0x10000>;
				clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
				/* For nvmem subnodes */
				#address-cells = <1>;
				#size-cells = <1>;

				imx8mp_uid: unique-id@420 {
					reg = <0x8 0x8>;
				};

				cpu_speed_grade: speed-grade@10 {
					reg = <0x10 4>;
				};

				eth_mac1: mac-address@90 {
					reg = <0x90 6>;
				};

				eth_mac2: mac-address@96 {
					reg = <0x96 6>;
				};
			};

			anatop: clock-controller@30360000 {
				compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
				reg = <0x30360000 0x10000>;
				#clock-cells = <1>;
			};

			snvs: snvs@30370000 {
				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
				reg = <0x30370000 0x10000>;

				snvs_rtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap =<&snvs>;
					offset = <0x34>;
					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
					clock-names = "snvs-rtc";
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
					clock-names = "snvs-pwrkey";
					linux,keycode = <KEY_POWER>;
					wakeup-source;
					status = "disabled";
				};

				snvs_lpgpr: snvs-lpgpr {
					compatible = "fsl,imx8mp-snvs-lpgpr",
						     "fsl,imx7d-snvs-lpgpr";
				};
			};

			clk: clock-controller@30380000 {
				compatible = "fsl,imx8mp-ccm";
				reg = <0x30380000 0x10000>;
				#clock-cells = <1>;
				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
					 <&clk_ext3>, <&clk_ext4>;
				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
					      "clk_ext3", "clk_ext4";
				assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
						  <&clk IMX8MP_CLK_A53_CORE>,
						  <&clk IMX8MP_CLK_NOC>,
						  <&clk IMX8MP_CLK_NOC_IO>,
						  <&clk IMX8MP_CLK_GIC>,
						  <&clk IMX8MP_CLK_AUDIO_AHB>,
						  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
						  <&clk IMX8MP_AUDIO_PLL1>,
						  <&clk IMX8MP_AUDIO_PLL2>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
							 <&clk IMX8MP_ARM_PLL_OUT>,
							 <&clk IMX8MP_SYS_PLL2_1000M>,
							 <&clk IMX8MP_SYS_PLL1_800M>,
							 <&clk IMX8MP_SYS_PLL2_500M>,
							 <&clk IMX8MP_SYS_PLL1_800M>,
							 <&clk IMX8MP_SYS_PLL1_800M>;
				assigned-clock-rates = <0>, <0>,
						       <1000000000>,
						       <800000000>,
						       <500000000>,
						       <400000000>,
						       <800000000>,
						       <393216000>,
						       <361267200>;
			};

			src: reset-controller@30390000 {
				compatible = "fsl,imx8mp-src", "syscon";
				reg = <0x30390000 0x10000>;
				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};

			gpc: gpc@303a0000 {
				compatible = "fsl,imx8mp-gpc";
				reg = <0x303a0000 0x1000>;
				interrupt-parent = <&gic>;
				interrupt-controller;
				#interrupt-cells = <3>;

				pgc {
					#address-cells = <1>;
					#size-cells = <0>;

					pgc_mipi_phy1: power-domain@0 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
					};

					pgc_pcie_phy: power-domain@1 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
					};

					pgc_usb1_phy: power-domain@2 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
					};

					pgc_usb2_phy: power-domain@3 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
					};

					pgc_gpu2d: power-domain@6 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
						clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
						power-domains = <&pgc_gpumix>;
					};

					pgc_gpumix: power-domain@7 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
						clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
							 <&clk IMX8MP_CLK_GPU_AHB>;
						assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
								  <&clk IMX8MP_CLK_GPU_AHB>;
						assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
									 <&clk IMX8MP_SYS_PLL1_800M>;
						assigned-clock-rates = <800000000>, <400000000>;
					};

					pgc_gpu3d: power-domain@9 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
						clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
							 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
						power-domains = <&pgc_gpumix>;
					};

					pgc_mediamix: power-domain@10 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
						clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
					};

					pgc_mipi_phy2: power-domain@16 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
					};

					pgc_hsiomix: power-domains@17 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
						clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
							 <&clk IMX8MP_CLK_HSIO_ROOT>;
						assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
						assigned-clock-rates = <500000000>;
					};

					pgc_ispdwp: power-domain@18 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
						clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
					};

					pgc_vpumix: power-domain@19 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
						clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
					};

					pgc_vpu_g1: power-domain@20 {
						#power-domain-cells = <0>;
						power-domains = <&pgc_vpumix>;
						reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
						clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
					};

					pgc_vpu_g2: power-domain@21 {
						#power-domain-cells = <0>;
						power-domains = <&pgc_vpumix>;
						reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
						clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
					};

					pgc_vpu_vc8000e: power-domain@22 {
						#power-domain-cells = <0>;
						power-domains = <&pgc_vpumix>;
						reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
						clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
					};

					pgc_mlmix: power-domain@24 {
						#power-domain-cells = <0>;
						reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
						clocks = <&clk IMX8MP_CLK_ML_AXI>,
							 <&clk IMX8MP_CLK_ML_AHB>,
							 <&clk IMX8MP_CLK_NPU_ROOT>;
					};
				};
			};
		};

		aips2: bus@30400000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x30400000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pwm1: pwm@30660000 {
				compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
				reg = <0x30660000 0x10000>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
					 <&clk IMX8MP_CLK_PWM1_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm2: pwm@30670000 {
				compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
				reg = <0x30670000 0x10000>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
					 <&clk IMX8MP_CLK_PWM2_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm3: pwm@30680000 {
				compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
				reg = <0x30680000 0x10000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
					 <&clk IMX8MP_CLK_PWM3_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			pwm4: pwm@30690000 {
				compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
				reg = <0x30690000 0x10000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
					 <&clk IMX8MP_CLK_PWM4_ROOT>;
				clock-names = "ipg", "per";
				#pwm-cells = <3>;
				status = "disabled";
			};

			system_counter: timer@306a0000 {
				compatible = "nxp,sysctr-timer";
				reg = <0x306a0000 0x20000>;
				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&osc_24m>;
				clock-names = "per";
			};
		};

		aips3: bus@30800000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x30800000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			ecspi1: spi@30820000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
				reg = <0x30820000 0x10000>;
				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
					 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
				clock-names = "ipg", "per";
				assigned-clock-rates = <80000000>;
				assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
				dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			ecspi2: spi@30830000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
				reg = <0x30830000 0x10000>;
				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
					 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
				clock-names = "ipg", "per";
				assigned-clock-rates = <80000000>;
				assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
				dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			ecspi3: spi@30840000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
				reg = <0x30840000 0x10000>;
				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
					 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
				clock-names = "ipg", "per";
				assigned-clock-rates = <80000000>;
				assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
				dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart1: serial@30860000 {
				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
				reg = <0x30860000 0x10000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
					 <&clk IMX8MP_CLK_UART1_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart3: serial@30880000 {
				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
				reg = <0x30880000 0x10000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
					 <&clk IMX8MP_CLK_UART3_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart2: serial@30890000 {
				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
				reg = <0x30890000 0x10000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
					 <&clk IMX8MP_CLK_UART2_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			flexcan1: can@308c0000 {
				compatible = "fsl,imx8mp-flexcan";
				reg = <0x308c0000 0x10000>;
				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
					 <&clk IMX8MP_CLK_CAN1_ROOT>;
				clock-names = "ipg", "per";
				assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
				assigned-clock-rates = <40000000>;
				fsl,clk-source = /bits/ 8 <0>;
				fsl,stop-mode = <&gpr 0x10 4>;
				status = "disabled";
			};

			flexcan2: can@308d0000 {
				compatible = "fsl,imx8mp-flexcan";
				reg = <0x308d0000 0x10000>;
				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
					 <&clk IMX8MP_CLK_CAN2_ROOT>;
				clock-names = "ipg", "per";
				assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
				assigned-clock-rates = <40000000>;
				fsl,clk-source = /bits/ 8 <0>;
				fsl,stop-mode = <&gpr 0x10 5>;
				status = "disabled";
			};

			crypto: crypto@30900000 {
				compatible = "fsl,sec-v4.0";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x30900000 0x40000>;
				ranges = <0 0x30900000 0x40000>;
				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_AHB>,
					 <&clk IMX8MP_CLK_IPG_ROOT>;
				clock-names = "aclk", "ipg";

				sec_jr0: jr@1000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x1000 0x1000>;
					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
					status = "disabled";
				};

				sec_jr1: jr@2000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x2000 0x1000>;
					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr2: jr@3000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x3000 0x1000>;
					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			i2c1: i2c@30a20000 {
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a20000 0x10000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
				status = "disabled";
			};

			i2c2: i2c@30a30000 {
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a30000 0x10000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
				status = "disabled";
			};

			i2c3: i2c@30a40000 {
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a40000 0x10000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
				status = "disabled";
			};

			i2c4: i2c@30a50000 {
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30a50000 0x10000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
				status = "disabled";
			};

			uart4: serial@30a60000 {
				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
				reg = <0x30a60000 0x10000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
					 <&clk IMX8MP_CLK_UART4_ROOT>;
				clock-names = "ipg", "per";
				dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			mu: mailbox@30aa0000 {
				compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
				reg = <0x30aa0000 0x10000>;
				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_MU_ROOT>;
				#mbox-cells = <2>;
			};

			mu2: mailbox@30e60000 {
				compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
				reg = <0x30e60000 0x10000>;
				interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
				#mbox-cells = <2>;
				status = "disabled";
			};

			i2c5: i2c@30ad0000 {
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30ad0000 0x10000>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
				status = "disabled";
			};

			i2c6: i2c@30ae0000 {
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x30ae0000 0x10000>;
				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
				status = "disabled";
			};

			usdhc1: mmc@30b40000 {
				compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b40000 0x10000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_DUMMY>,
					 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MP_CLK_USDHC1_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: mmc@30b50000 {
				compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b50000 0x10000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_DUMMY>,
					 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MP_CLK_USDHC2_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			usdhc3: mmc@30b60000 {
				compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b60000 0x10000>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_DUMMY>,
					 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
					 <&clk IMX8MP_CLK_USDHC3_ROOT>;
				clock-names = "ipg", "ahb", "per";
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step = <2>;
				bus-width = <4>;
				status = "disabled";
			};

			flexspi: spi@30bb0000 {
				compatible = "nxp,imx8mp-fspi";
				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
				reg-names = "fspi_base", "fspi_mmap";
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
					 <&clk IMX8MP_CLK_QSPI_ROOT>;
				clock-names = "fspi_en", "fspi";
				assigned-clock-rates = <80000000>;
				assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			sdma1: dma-controller@30bd0000 {
				compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
				reg = <0x30bd0000 0x10000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
					 <&clk IMX8MP_CLK_AHB>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
			};

			fec: ethernet@30be0000 {
				compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
				reg = <0x30be0000 0x10000>;
				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
					 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
					 <&clk IMX8MP_CLK_ENET_TIMER>,
					 <&clk IMX8MP_CLK_ENET_REF>,
					 <&clk IMX8MP_CLK_ENET_PHY_REF>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
						  <&clk IMX8MP_CLK_ENET_TIMER>,
						  <&clk IMX8MP_CLK_ENET_REF>,
						  <&clk IMX8MP_CLK_ENET_PHY_REF>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
							 <&clk IMX8MP_SYS_PLL2_100M>,
							 <&clk IMX8MP_SYS_PLL2_125M>,
							 <&clk IMX8MP_SYS_PLL2_50M>;
				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				nvmem-cells = <&eth_mac1>;
				nvmem-cell-names = "mac-address";
				fsl,stop-mode = <&gpr 0x10 3>;
				status = "disabled";
			};

			eqos: ethernet@30bf0000 {
				compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
				reg = <0x30bf0000 0x10000>;
				interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "macirq", "eth_wake_irq";
				clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
					 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
					 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
					 <&clk IMX8MP_CLK_ENET_QOS>;
				clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
				assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
						  <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
						  <&clk IMX8MP_CLK_ENET_QOS>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
							 <&clk IMX8MP_SYS_PLL2_100M>,
							 <&clk IMX8MP_SYS_PLL2_125M>;
				assigned-clock-rates = <0>, <100000000>, <125000000>;
				nvmem-cells = <&eth_mac2>;
				nvmem-cell-names = "mac-address";
				intf_mode = <&gpr 0x4>;
				status = "disabled";
			};
		};

		noc: interconnect@32700000 {
			compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
			reg = <0x32700000 0x100000>;
			clocks = <&clk IMX8MP_CLK_NOC>;
			#interconnect-cells = <1>;
			operating-points-v2 = <&noc_opp_table>;

			noc_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-200000000 {
					opp-hz = /bits/ 64 <200000000>;
				};

				opp-1000000000 {
					opp-hz = /bits/ 64 <1000000000>;
				};
			};
		};

		aips4: bus@32c00000 {
			compatible = "fsl,aips-bus", "simple-bus";
			reg = <0x32c00000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			media_blk_ctrl: blk-ctrl@32ec0000 {
				compatible = "fsl,imx8mp-media-blk-ctrl",
					     "syscon";
				reg = <0x32ec0000 0x10000>;
				power-domains = <&pgc_mediamix>,
						<&pgc_mipi_phy1>,
						<&pgc_mipi_phy1>,
						<&pgc_mediamix>,
						<&pgc_mediamix>,
						<&pgc_mipi_phy2>,
						<&pgc_mediamix>,
						<&pgc_ispdwp>,
						<&pgc_ispdwp>,
						<&pgc_mipi_phy2>;
				power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
						     "lcdif1", "isi", "mipi-csi2",
						     "lcdif2", "isp", "dwe",
						     "mipi-dsi2";
				interconnects =
					<&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>,
					<&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>,
					<&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>,
					<&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>,
					<&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>,
					<&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>,
					<&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>,
					<&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>;
				interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
						     "isi1", "isi2", "isp0", "isp1",
						     "dwe";
				clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
					 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
					 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
					 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
					 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
					 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
					 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
				clock-names = "apb", "axi", "cam1", "cam2",
					      "disp1", "disp2", "isp", "phy";

				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
						  <&clk IMX8MP_CLK_MEDIA_APB>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
							 <&clk IMX8MP_SYS_PLL1_800M>;
				assigned-clock-rates = <500000000>, <200000000>;

				#power-domain-cells = <1>;
			};

			pcie_phy: pcie-phy@32f00000 {
				compatible = "fsl,imx8mp-pcie-phy";
				reg = <0x32f00000 0x10000>;
				resets = <&src IMX8MP_RESET_PCIEPHY>,
					 <&src IMX8MP_RESET_PCIEPHY_PERST>;
				reset-names = "pciephy", "perst";
				power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
				#phy-cells = <0>;
				status = "disabled";
			};

			hsio_blk_ctrl: blk-ctrl@32f10000 {
				compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
				reg = <0x32f10000 0x24>;
				clocks = <&clk IMX8MP_CLK_USB_ROOT>,
					 <&clk IMX8MP_CLK_PCIE_ROOT>;
				clock-names = "usb", "pcie";
				power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
						<&pgc_usb1_phy>, <&pgc_usb2_phy>,
						<&pgc_hsiomix>, <&pgc_pcie_phy>;
				power-domain-names = "bus", "usb", "usb-phy1",
						     "usb-phy2", "pcie", "pcie-phy";
				interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>,
						<&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>,
						<&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>,
						<&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
				interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
				#power-domain-cells = <1>;
			};
		};

		pcie: pcie@33800000 {
			compatible = "fsl,imx8mp-pcie";
			reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
			reg-names = "dbi", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			bus-range = <0x00 0xff>;
			ranges =  <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
				  <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
			num-lanes = <1>;
			num-viewport = <4>;
			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
			fsl,max-link-speed = <3>;
			linux,pci-domain = <0>;
			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
			resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
				 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
			reset-names = "apps", "turnoff";
			phys = <&pcie_phy>;
			phy-names = "pcie-phy";
			status = "disabled";
		};

		gpu3d: gpu@38000000 {
			compatible = "vivante,gc";
			reg = <0x38000000 0x8000>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
				 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
				 <&clk IMX8MP_CLK_GPU_ROOT>,
				 <&clk IMX8MP_CLK_GPU_AHB>;
			clock-names = "core", "shader", "bus", "reg";
			assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
					  <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
			assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
						 <&clk IMX8MP_SYS_PLL1_800M>;
			assigned-clock-rates = <800000000>, <800000000>;
			power-domains = <&pgc_gpu3d>;
		};

		gpu2d: gpu@38008000 {
			compatible = "vivante,gc";
			reg = <0x38008000 0x8000>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
				 <&clk IMX8MP_CLK_GPU_ROOT>,
				 <&clk IMX8MP_CLK_GPU_AHB>;
			clock-names = "core", "bus", "reg";
			assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
			assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
			assigned-clock-rates = <800000000>;
			power-domains = <&pgc_gpu2d>;
		};

		vpumix_blk_ctrl: blk-ctrl@38330000 {
			compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
			reg = <0x38330000 0x100>;
			#power-domain-cells = <1>;
			power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
					<&pgc_vpu_g2>, <&pgc_vpu_vc8000e>;
			power-domain-names = "bus", "g1", "g2", "vc8000e";
			clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
				 <&clk IMX8MP_CLK_VPU_G2_ROOT>,
				 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
			clock-names = "g1", "g2", "vc8000e";
			interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
					<&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
					<&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
			interconnect-names = "g1", "g2", "vc8000e";
		};

		gic: interrupt-controller@38800000 {
			compatible = "arm,gic-v3";
			reg = <0x38800000 0x10000>,
			      <0x38880000 0xc0000>;
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
		};

		edacmc: memory-controller@3d400000 {
			compatible = "snps,ddrc-3.80a";
			reg = <0x3d400000 0x400000>;
			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		};

		ddr-pmu@3d800000 {
			compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
			reg = <0x3d800000 0x400000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		};

		usb3_phy0: usb-phy@381f0040 {
			compatible = "fsl,imx8mp-usb-phy";
			reg = <0x381f0040 0x40>;
			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
			clock-names = "phy";
			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
			#phy-cells = <0>;
			status = "disabled";
		};

		usb3_0: usb@32f10100 {
			compatible = "fsl,imx8mp-dwc3";
			reg = <0x32f10100 0x8>,
			      <0x381f0000 0x20>;
			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
				 <&clk IMX8MP_CLK_USB_ROOT>;
			clock-names = "hsio", "suspend";
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
			#address-cells = <1>;
			#size-cells = <1>;
			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
			ranges;
			status = "disabled";

			usb_dwc3_0: usb@38100000 {
				compatible = "snps,dwc3";
				reg = <0x38100000 0x10000>;
				clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
					 <&clk IMX8MP_CLK_USB_CORE_REF>,
					 <&clk IMX8MP_CLK_USB_ROOT>;
				clock-names = "bus_early", "ref", "suspend";
				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usb3_phy0>, <&usb3_phy0>;
				phy-names = "usb2-phy", "usb3-phy";
				snps,gfladj-refclk-lpm-sel-quirk;
			};

		};

		usb3_phy1: usb-phy@382f0040 {
			compatible = "fsl,imx8mp-usb-phy";
			reg = <0x382f0040 0x40>;
			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
			clock-names = "phy";
			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
			#phy-cells = <0>;
			status = "disabled";
		};

		usb3_1: usb@32f10108 {
			compatible = "fsl,imx8mp-dwc3";
			reg = <0x32f10108 0x8>,
			      <0x382f0000 0x20>;
			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
				 <&clk IMX8MP_CLK_USB_ROOT>;
			clock-names = "hsio", "suspend";
			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
			#address-cells = <1>;
			#size-cells = <1>;
			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
			ranges;
			status = "disabled";

			usb_dwc3_1: usb@38200000 {
				compatible = "snps,dwc3";
				reg = <0x38200000 0x10000>;
				clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
					 <&clk IMX8MP_CLK_USB_CORE_REF>,
					 <&clk IMX8MP_CLK_USB_ROOT>;
				clock-names = "bus_early", "ref", "suspend";
				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
				phys = <&usb3_phy1>, <&usb3_phy1>;
				phy-names = "usb2-phy", "usb3-phy";
				snps,gfladj-refclk-lpm-sel-quirk;
			};
		};

		dsp: dsp@3b6e8000 {
			compatible = "fsl,imx8mp-dsp";
			reg = <0x3b6e8000 0x88000>;
			mbox-names = "txdb0", "txdb1",
				"rxdb0", "rxdb1";
			mboxes = <&mu2 2 0>, <&mu2 2 1>,
				<&mu2 3 0>, <&mu2 3 1>;
			memory-region = <&dsp_reserved>;
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2017 NXP
 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
 */

/dts-v1/;

#include "imx8mq.dtsi"

/ {
	model = "NXP i.MX8MQ EVK";
	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";

	chosen {
		stdout-path = &uart1;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x00000000 0x40000000 0 0xc0000000>;
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	reg_pcie1: regulator-pcie {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pcie1_reg>;
		regulator-name = "MPCIE_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usdhc2_vmmc: regulator-vsd-3v3 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2>;
		compatible = "regulator-fixed";
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		off-on-delay-us = <20000>;
		enable-active-high;
	};

	buck2_reg: regulator-buck2 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_buck2>;
		compatible = "regulator-gpio";
		regulator-name = "vdd_arm";
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <1000000>;
		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
		states = <1000000 0x0
			  900000 0x1>;
		regulator-boot-on;
		regulator-always-on;
	};

	ir-receiver {
		compatible = "gpio-ir-receiver";
		gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ir>;
		linux,autosuspend-period = <125>;
	};

	audio_codec_bt_sco: audio-codec-bt-sco {
		compatible = "linux,bt-sco";
		#sound-dai-cells = <1>;
	};

	wm8524: audio-codec {
		#sound-dai-cells = <0>;
		compatible = "wlf,wm8524";
		wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
	};

	sound-bt-sco {
		compatible = "simple-audio-card";
		simple-audio-card,name = "bt-sco-audio";
		simple-audio-card,format = "dsp_a";
		simple-audio-card,bitclock-inversion;
		simple-audio-card,frame-master = <&btcpu>;
		simple-audio-card,bitclock-master = <&btcpu>;

		btcpu: simple-audio-card,cpu {
			sound-dai = <&sai3>;
			dai-tdm-slot-num = <2>;
			dai-tdm-slot-width = <16>;
		};

		simple-audio-card,codec {
			sound-dai = <&audio_codec_bt_sco 1>;
		};
	};

	sound-wm8524 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "wm8524-audio";
		simple-audio-card,format = "i2s";
		simple-audio-card,frame-master = <&cpudai>;
		simple-audio-card,bitclock-master = <&cpudai>;
		simple-audio-card,widgets =
			"Line", "Left Line Out Jack",
			"Line", "Right Line Out Jack";
		simple-audio-card,routing =
			"Left Line Out Jack", "LINEVOUTL",
			"Right Line Out Jack", "LINEVOUTR";

		cpudai: simple-audio-card,cpu {
			sound-dai = <&sai2>;
		};

		link_codec: simple-audio-card,codec {
			sound-dai = <&wm8524>;
			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
		};
	};

	sound-spdif {
		compatible = "fsl,imx-audio-spdif";
		model = "imx-spdif";
		spdif-controller = <&spdif1>;
		spdif-out;
		spdif-in;
	};

	sound-hdmi-arc {
		compatible = "fsl,imx-audio-spdif";
		model = "imx-hdmi-arc";
		spdif-controller = <&spdif2>;
		spdif-in;
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&A53_1 {
	cpu-supply = <&buck2_reg>;
};

&A53_2 {
	cpu-supply = <&buck2_reg>;
};

&A53_3 {
	cpu-supply = <&buck2_reg>;
};

&ddrc {
	operating-points-v2 = <&ddrc_opp_table>;
	status = "okay";

	ddrc_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-25000000 {
			opp-hz = /bits/ 64 <25000000>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};

		/*
		 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
		 */
		opp-166000000 {
			opp-hz = /bits/ 64 <166935483>;
		};

		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
		};
	};
};

&dphy {
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>;
			qca,disable-smarteee;
			vddio-supply = <&vddh>;

			vddh: vddh-regulator {
			};
		};
	};
};

&gpio5 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wifi_reset>;

	wl-reg-on-hog {
		gpio-hog;
		gpios = <29 GPIO_ACTIVE_HIGH>;
		output-high;
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@8 {
		compatible = "fsl,pfuze100";
		reg = <0x8>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
			};

			sw1c_reg: sw1c {
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
			};

			sw3a_reg: sw3ab {
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <975000>;
				regulator-always-on;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1675000>;
				regulator-max-microvolt = <1975000>;
				regulator-always-on;
			};

			vgen4_reg: vgen4 {
				regulator-min-microvolt = <1625000>;
				regulator-max-microvolt = <1875000>;
				regulator-always-on;
			};

			vgen5_reg: vgen5 {
				regulator-min-microvolt = <3075000>;
				regulator-max-microvolt = <3625000>;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
			};
		};
	};
};

&lcdif {
	status = "okay";
};

&mipi_dsi {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	panel@0 {
		pinctrl-0 = <&pinctrl_mipi_dsi>;
		pinctrl-names = "default";
		compatible = "raydium,rm67191";
		reg = <0>;
		reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
		dsi-lanes = <4>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&mipi_dsi_out>;
			};
		};
	};

	ports {
		port@1 {
			reg = <1>;
			mipi_dsi_out: endpoint {
				remote-endpoint = <&panel_in>;
			};
		};
	};
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	vph-supply = <&vgen5_reg>;
	status = "okay";
};

&pcie1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie1>;
	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	vpcie-supply = <&reg_pcie1>;
	vph-supply = <&vgen5_reg>;
	status = "okay";
};

&pgc_gpu {
	power-supply = <&sw1a_reg>;
};

&pgc_vpu {
	power-supply = <&sw1c_reg>;
};

&qspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	status = "okay";

	n25q256a: flash@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,n25q256a", "jedec,spi-nor";
		spi-max-frequency = <29000000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
	};
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <0>, <24576000>;
	status = "okay";
};

&sai3 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

&snvs_pwrkey {
	status = "okay";
};

&spdif1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif1>;
	assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

&spdif2 {
	assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&usb3_phy1 {
	status = "okay";
};

&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
};

&usdhc1 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	vqmmc-supply = <&sw4_reg>;
	bus-width = <8>;
	non-removable;
	no-sd;
	no-sdio;
	status = "okay";
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_buck2: vddarmgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x19
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
		>;
	};

	pinctrl_ir: irgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x4f
		>;
	};

	pinctrl_mipi_dsi: mipidsigrp {
		fsl,pins = <
			MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6		0x16
		>;
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B		0x76
			MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28		0x16
		>;
	};

	pinctrl_pcie1: pcie1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B		0x76
			MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12		0x16
		>;
	};

	pinctrl_pcie1_reg: pcie1reggrp {
		fsl,pins = <
			MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10		0x16
		>;
	};

	pinctrl_qspi: qspigrp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
		>;
	};

	pinctrl_reg_usdhc2: regusdhc2gpiogrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8       0xd6
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
			MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
			MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
			MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
		>;
	};

	pinctrl_spdif1: spdif1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
			MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_wdog: wdog1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
		>;
	};

	pinctrl_wifi_reset: wifiresetgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16
		>;
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
 */

/dts-v1/;

#include "dt-bindings/usb/pd.h"
#include "imx8mq-sr-som.dtsi"

/ {
	model = "SolidRun i.MX8MQ HummingBoard Pulse";
	compatible = "solidrun,hummingboard-pulse", "fsl,imx8mq";

	chosen {
		stdout-path = &uart1;
	};

	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
	};

	reg_v_5v0: regulator-v-5v0 {
		compatible = "regulator-fixed";
		regulator-name = "v_5v0";
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-always-on;
	};
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clock-frequency = <100000>;
	status = "okay";

	typec_ptn5100: usb-typec@50 {
		compatible = "nxp,ptn5110";
		reg = <0x50>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_typec>;
		interrupt-parent = <&gpio1>;
		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;

		connector {
			compatible = "usb-c-connector";
			label = "USB-C";
			data-role = "dual";
			power-role = "dual";
			try-power-role = "sink";
			source-pdos = <PDO_FIXED(5000, 2000,
						 PDO_FIXED_USB_COMM |
						 PDO_FIXED_SUSPEND |
						 PDO_FIXED_EXTPOWER)>;
			sink-pdos = <PDO_FIXED(5000, 2000,
					       PDO_FIXED_USB_COMM |
					       PDO_FIXED_SUSPEND |
					       PDO_FIXED_EXTPOWER)
				     PDO_FIXED(9000, 2000,
					       PDO_FIXED_USB_COMM |
					       PDO_FIXED_SUSPEND |
					       PDO_FIXED_EXTPOWER)>;
			op-sink-microwatt = <9000000>;

			port {
				typec1_dr_sw: endpoint {
					remote-endpoint = <&usb1_drd_sw>;
				};
			};
		};
	};
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	clock-frequency = <100000>;
	status = "okay";

	eeprom@57 {
		compatible = "atmel,24c02";
		reg = <0x57>;
		status = "okay";
	};

	rtc@69 {
		compatible = "abracon,ab1805";
		reg = <0x69>;
		abracon,tc-diode = "schottky";
		abracon,tc-resistor = <3>;
	};
};

&uart2 { /* J35 header */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
	status = "okay";
};

&uart3 { /* Mikrobus */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
	uart-has-rtscts;
	status = "okay";
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&usb_dwc3_0 {
	dr_mode = "otg";
	status = "okay";

	port {
		usb1_drd_sw: endpoint {
			remote-endpoint = <&typec1_dr_sw>;
		};
	};
};

&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
};

&usb3_phy0 {
	status = "okay";
};

&usb3_phy1 {
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			/* MikroBus Analog */
			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x41
			/* MikroBus Reset */
			MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23		0x41
			/*
			 * The following 2 pins need to be commented out and
			 * reconfigured to enable RTS/CTS on UART3
			 */
			/* MikroBus PWM */
			MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8		0x41
			/* MikroBus INT */
			MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x41
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL		0x4000007f
			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA		0x4000007f
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x4000007f
			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x4000007f
		>;
	};

	pinctrl_typec: typecgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15	0x16
			MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x17059
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
			/*
			 * These pins are by default GPIO on the Mikro Bus
			 * Header. To use RTS/CTS on UART3 comment them out
			 * of the hoggrp and enable them here
			 */
			/* MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x49 */
			/* MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x49 */
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
		>;
	};

	pinctrl_usdhc2_vmmc: usdhc2vmmcgpiogrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x41
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x9f
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xdf
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xdf
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xdf
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xdf
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xdf
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree File for the Kontron pitx-imx8m board.
 *
 * Copyright (C) 2021 Heiko Thiery <heiko.thiery@gmail.com>
 */

/dts-v1/;

#include "imx8mq.dtsi"
#include <dt-bindings/net/ti-dp83867.h>

/ {
	model = "Kontron pITX-imx8m";
	compatible = "kontron,pitx-imx8m", "fsl,imx8mq";

	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		spi0 = &qspi0;
		spi1 = &ecspi2;
	};

	chosen {
		stdout-path = "serial2:115200n8";
	};

	pcie0_refclk: pcie0-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pcie1_refclk: pcie1-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2>;
		regulator-name = "V_3V3_SD";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		off-on-delay-us = <20000>;
		enable-active-high;
	};
};

&ecspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "okay";

	tpm@0 {
		compatible = "infineon,slb9670";
		reg = <0>;
		spi-max-frequency = <43000000>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10>;
			reset-deassert-us = <280>;
		};
	};
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@8 {
		compatible = "fsl,pfuze100";
		fsl,pfuze-support-disable-sw;
		reg = <0x8>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-name = "V_0V9_GPU";
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
			};

			sw1c_reg: sw1c {
				regulator-name = "V_0V9_VPU";
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
			};

			sw2_reg: sw2 {
				regulator-name = "V_1V1_NVCC_DRAM";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
			};

			sw3a_reg: sw3ab {
				regulator-name = "V_1V0_DRAM";
				regulator-min-microvolt = <825000>;
				regulator-max-microvolt = <1100000>;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-name = "V_1V8_S0";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			swbst_reg: swbst {
				regulator-name = "NC";
				regulator-min-microvolt = <5000000>;
				regulator-max-microvolt = <5150000>;
			};

			snvs_reg: vsnvs {
				regulator-name = "V_0V9_SNVS";
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-name = "V_0V55_VREF_DDR";
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-name = "V_1V5_CSI";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1550000>;
			};

			vgen2_reg: vgen2 {
				regulator-name = "V_0V9_PHY";
				regulator-min-microvolt = <850000>;
				regulator-max-microvolt = <975000>;
				regulator-always-on;
			};

			vgen3_reg: vgen3 {
				regulator-name = "V_1V8_PHY";
				regulator-min-microvolt = <1675000>;
				regulator-max-microvolt = <1975000>;
				regulator-always-on;
			};

			vgen4_reg: vgen4 {
				regulator-name = "V_1V8_VDDA";
				regulator-min-microvolt = <1625000>;
				regulator-max-microvolt = <1875000>;
				regulator-always-on;
			};

			vgen5_reg: vgen5 {
				regulator-name = "V_3V3_PHY";
				regulator-min-microvolt = <3075000>;
				regulator-max-microvolt = <3625000>;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-name = "V_2V8_CAM";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-always-on;
			};
		};
	};

	fan-controller@1b {
		compatible = "maxim,max6650";
		reg = <0x1b>;
		maxim,fan-microvolt = <5000000>;
	};

	rtc@32 {
		compatible = "microcrystal,rv8803";
		reg = <0x32>;
	};

	sensor@4b {
		compatible = "national,lm75b";
		reg = <0x4b>;
	};

	eeprom@51 {
		compatible = "atmel,24c32";
		reg = <0x51>;
		pagesize = <32>;
	};
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

/* M.2 B-key slot */
&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	status = "okay";
};

/* Intel Ethernet Controller I210/I211 */
&pcie1 {
	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
		 <&pcie1_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	fsl,max-link-speed = <1>;
	status = "okay";
};

&pgc_gpu {
	power-supply = <&sw1a_reg>;
};

&pgc_vpu {
	power-supply = <&sw1c_reg>;
};

&qspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		m25p,fast-read;
		spi-max-frequency = <50000000>;
	};
};

&snvs_pwrkey {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
	status = "okay";
};

&usb3_phy0 {
	status = "okay";
};

&usb3_phy1 {
	status = "okay";
};

&usb_dwc3_0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0>;
	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	adp-disable;
	maximum-speed = "high-speed";
	status = "okay";
};

&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
};

&usdhc1 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	vqmmc-supply = <&sw4_reg>;
	bus-width = <8>;
	non-removable;
	no-sd;
	no-sdio;
	status = "okay";
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x19 /* TPM Reset */
			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x19 /* USB2 Hub Reset */
		>;
	};

	pinctrl_gpio: gpiogrp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x19 /* GPIO0 */
			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15		0x19 /* GPIO1 */
			MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x19 /* GPIO2 */
			MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18		0x19 /* GPIO3 */
			MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19 /* GPIO4 */
			MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10		0x19 /* GPIO5 */
			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x19 /* GPIO6 */
			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x19 /* GPIO7 */
		>;
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x16 /* PCIE_PERST */
			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16 /* W_DISABLE */
		>;
	};

	pinctrl_reg_usdhc2: regusdhc2gpiogrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
		>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x16
			MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x16
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
		>;
	};

	pinctrl_qspi: qspigrp {
		fsl,pins = <
			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x82
			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x82
			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x82
			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x82
			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x82
			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x82
		>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x19
			MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x19
			MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x19
		>;
	};

	pinctrl_ecspi2_cs: ecspi2csgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x19
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
			MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x49
			MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x49
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41
			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20			0x19
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x9f
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xdf
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xdf
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xdf
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xdf
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xdf
			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usb0: usb0grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR		0x19
			MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x19
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
		>;
	};
};