code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Pro5 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "socionext,uniphier-pro5";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
		};
	};

	cpu_opp: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			clock-latency-ns = <300>;
		};
		opp-116667000 {
			opp-hz = /bits/ 64 <116667000>;
			clock-latency-ns = <300>;
		};
		opp-150000000 {
			opp-hz = /bits/ 64 <150000000>;
			clock-latency-ns = <300>;
		};
		opp-175000000 {
			opp-hz = /bits/ 64 <175000000>;
			clock-latency-ns = <300>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			clock-latency-ns = <300>;
		};
		opp-233334000 {
			opp-hz = /bits/ 64 <233334000>;
			clock-latency-ns = <300>;
		};
		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			clock-latency-ns = <300>;
		};
		opp-350000000 {
			opp-hz = /bits/ 64 <350000000>;
			clock-latency-ns = <300>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			clock-latency-ns = <300>;
		};
		opp-466667000 {
			opp-hz = /bits/ 64 <466667000>;
			clock-latency-ns = <300>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			clock-latency-ns = <300>;
		};
		opp-700000000 {
			opp-hz = /bits/ 64 <700000000>;
			clock-latency-ns = <300>;
		};
		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			clock-latency-ns = <300>;
		};
		opp-933334000 {
			opp-hz = /bits/ 64 <933334000>;
			clock-latency-ns = <300>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			clock-latency-ns = <300>;
		};
		opp-1400000000 {
			opp-hz = /bits/ 64 <1400000000>;
			clock-latency-ns = <300>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <20000000>;
		};

		arm_timer_clk: arm-timer {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		l2: cache-controller@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
			      <0x506c0000 0x400>;
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-size = <(2 * 1024 * 1024)>;
			cache-sets = <512>;
			cache-line-size = <128>;
			cache-level = <2>;
			next-level-cache = <&l3>;
		};

		l3: cache-controller@500c8000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
			      <0x506c8000 0x400>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-size = <(2 * 1024 * 1024)>;
			cache-sets = <512>;
			cache-line-size = <256>;
			cache-level = <3>;
		};

		spi0: spi@54006000 {
			compatible = "socionext,uniphier-scssi";
			status = "disabled";
			reg = <0x54006000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi0>;
			clocks = <&peri_clk 11>;
			resets = <&peri_rst 11>;
		};

		spi1: spi@54006100 {
			compatible = "socionext,uniphier-scssi";
			status = "disabled";
			reg = <0x54006100 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi1>;
			clocks = <&peri_clk 11>;	/* common with spi0 */
			resets = <&peri_rst 12>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			resets = <&peri_rst 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			resets = <&peri_rst 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			resets = <&peri_rst 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			resets = <&peri_rst 3>;
		};

		gpio: gpio@55000000 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000000 0x200>;
			interrupt-parent = <&aidet>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 0>;
			gpio-ranges-group-names = "gpio_range";
			ngpios = <248>;
			socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			resets = <&peri_rst 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			resets = <&peri_rst 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			clocks = <&peri_clk 6>;
			resets = <&peri_rst 6>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			resets = <&peri_rst 7>;
			clock-frequency = <100000>;
		};

		/* i2c4 does not exist */

		/* chip-internal connection for DMD */
		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&peri_clk 9>;
			resets = <&peri_rst 9>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for HDMI */
		i2c6: i2c@58786000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58786000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&peri_clk 10>;
			resets = <&peri_rst 10>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		sdctrl@59810000 {
			compatible = "socionext,uniphier-pro5-sdctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x400>;

			sd_clk: clock {
				compatible = "socionext,uniphier-pro5-sd-clock";
				#clock-cells = <1>;
			};

			sd_rst: reset {
				compatible = "socionext,uniphier-pro5-sd-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-pro5-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-pro5-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-pro5-peri-reset";
				#reset-cells = <1>;
			};
		};

		soc-glue@5f800000 {
			compatible = "socionext,uniphier-pro5-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-pro5-pinctrl";
			};
		};

		soc-glue@5f900000 {
			compatible = "socionext,uniphier-pro5-soc-glue-debug",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x5f900000 0x2000>;

			efuse@100 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x100 0x28>;
			};

			efuse@130 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x130 0x8>;
			};

			efuse@200 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x200 0x28>;
			};

			efuse@300 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x300 0x14>;
			};

			efuse@400 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x400 0x8>;
			};
		};

		xdmac: dma-controller@5fc10000 {
			compatible = "socionext,uniphier-xdmac";
			reg = <0x5fc10000 0x5300>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <16>;
			#dma-cells = <2>;
		};

		aidet: interrupt-controller@5fc20000 {
			compatible = "socionext,uniphier-pro5-aidet";
			reg = <0x5fc20000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <GIC_PPI 11
				(GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-pro5-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-pro5-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-pro5-reset";
				#reset-cells = <1>;
			};
		};

		usb0: usb@65a00000 {
			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
			status = "disabled";
			reg = <0x65a00000 0xcd00>;
			interrupt-names = "host";
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clock-names = "ref", "bus_early", "suspend";
			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
			resets = <&usb0_rst 15>;
			phys = <&usb0_hsphy0>, <&usb0_ssphy0>;
			dr_mode = "host";
		};

		usb-controller@65b00000 {
			compatible = "socionext,uniphier-pro5-dwc3-glue",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x65b00000 0x400>;

			usb0_rst: reset@0 {
				compatible = "socionext,uniphier-pro5-usb3-reset";
				reg = <0x0 0x4>;
				#reset-cells = <1>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 14>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 14>;
			};

			usb0_vbus0: regulator@100 {
				compatible = "socionext,uniphier-pro5-usb3-regulator";
				reg = <0x100 0x10>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 14>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 14>;
			};

			usb0_hsphy0: hs-phy@280 {
				compatible = "socionext,uniphier-pro5-usb3-hsphy";
				reg = <0x280 0x10>;
				#phy-cells = <0>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 14>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 14>;
				vbus-supply = <&usb0_vbus0>;
			};

			usb0_ssphy0: ss-phy@380 {
				compatible = "socionext,uniphier-pro5-usb3-ssphy";
				reg = <0x380 0x10>;
				#phy-cells = <0>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 14>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 14>;
				vbus-supply = <&usb0_vbus0>;
			};
		};

		usb1: usb@65c00000 {
			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
			status = "disabled";
			reg = <0x65c00000 0xcd00>;
			interrupt-names = "host";
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
			clock-names = "ref", "bus_early", "suspend";
			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
			resets = <&usb1_rst 15>;
			phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
			dr_mode = "host";
		};

		usb-controller@65d00000 {
			compatible = "socionext,uniphier-pro5-dwc3-glue",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x65d00000 0x400>;

			usb1_rst: reset@0 {
				compatible = "socionext,uniphier-pro5-usb3-reset";
				reg = <0x0 0x4>;
				#reset-cells = <1>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 15>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 15>;
			};

			usb1_vbus0: regulator@100 {
				compatible = "socionext,uniphier-pro5-usb3-regulator";
				reg = <0x100 0x10>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 15>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 15>;
			};

			usb1_vbus1: regulator@110 {
				compatible = "socionext,uniphier-pro5-usb3-regulator";
				reg = <0x110 0x10>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 15>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 15>;
			};

			usb1_hsphy0: hs-phy@280 {
				compatible = "socionext,uniphier-pro5-usb3-hsphy";
				reg = <0x280 0x10>;
				#phy-cells = <0>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 15>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 15>;
				vbus-supply = <&usb1_vbus0>;
			};

			usb1_hsphy1: hs-phy@290 {
				compatible = "socionext,uniphier-pro5-usb3-hsphy";
				reg = <0x290 0x10>;
				#phy-cells = <0>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 15>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 15>;
				vbus-supply = <&usb1_vbus1>;
			};

			usb1_ssphy0: ss-phy@380 {
				compatible = "socionext,uniphier-pro5-usb3-ssphy";
				reg = <0x380 0x10>;
				#phy-cells = <0>;
				clock-names = "gio", "link";
				clocks = <&sys_clk 12>, <&sys_clk 15>;
				reset-names = "gio", "link";
				resets = <&sys_rst 12>, <&sys_rst 15>;
				vbus-supply = <&usb1_vbus0>;
			};
		};

		pcie_ep: pcie-ep@66000000 {
			compatible = "socionext,uniphier-pro5-pcie-ep";
			status = "disabled";
			reg-names = "dbi", "dbi2", "link", "addr_space";
			reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
			      <0x66010000 0x10000>, <0x67000000 0x400000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_pcie>;
			clock-names = "gio", "link";
			clocks = <&sys_clk 12>, <&sys_clk 24>;
			reset-names = "gio", "link";
			resets = <&sys_rst 12>, <&sys_rst 24>;
			num-ib-windows = <16>;
			num-ob-windows = <16>;
			num-lanes = <4>;
			phy-names = "pcie-phy";
			phys = <&pcie_phy>;
		};

		pcie_phy: phy@66038000 {
			compatible = "socionext,uniphier-pro5-pcie-phy";
			reg = <0x66038000 0x4000>;
			#phy-cells = <0>;
			clock-names = "gio", "link";
			clocks = <&sys_clk 12>, <&sys_clk 24>;
			reset-names = "gio", "link";
			resets = <&sys_rst 12>, <&sys_rst 24>;
		};

		nand: nand-controller@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5b";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			clock-names = "nand", "nand_x", "ecc";
			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
			reset-names = "nand", "reg";
			resets = <&sys_rst 2>, <&sys_rst 2>;
		};

		emmc: mmc@68400000 {
			compatible = "socionext,uniphier-sd-v3.1";
			status = "disabled";
			reg = <0x68400000 0x800>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc>;
			clocks = <&sd_clk 1>;
			reset-names = "host", "hw";
			resets = <&sd_rst 1>, <&sd_rst 6>;
			bus-width = <8>;
			cap-mmc-highspeed;
			cap-mmc-hw-reset;
			non-removable;
		};

		sd: mmc@68800000 {
			compatible = "socionext,uniphier-sd-v3.1";
			status = "disabled";
			reg = <0x68800000 0x800>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default", "uhs";
			pinctrl-0 = <&pinctrl_sd>;
			pinctrl-1 = <&pinctrl_sd_uhs>;
			clocks = <&sd_clk 0>;
			reset-names = "host";
			resets = <&sd_rst 0>;
			bus-width = <4>;
			cap-sd-highspeed;
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
		};
	};
};

#include "uniphier-pinctrl.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier PXs2 Gentil Board
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

/dts-v1/;
#include "uniphier-pxs2.dtsi"

/ {
	model = "UniPhier PXs2 Gentil Board";
	compatible = "socionext,uniphier-pxs2-gentil",
		     "socionext,uniphier-pxs2";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &serial2;
		serial1 = &serial0;
		serial2 = &serial1;
		i2c0 = &i2c0;
		i2c2 = &i2c2;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		ethernet0 = ð
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x80000000>;
	};

	sound {
		compatible = "audio-graph-card";
		label = "UniPhier PXs2";
		dais = <&i2s_port2>;
	};
};

&serial2 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	eeprom@54 {
		compatible = "st,24c64", "atmel,24c64";
		reg = <0x54>;
		pagesize = <32>;
	};
};

&i2s_aux {
	dai-format = "i2s";
	remote-endpoint = <&wm_speaker>;
};

&i2c2 {
	status = "okay";

	wm8960@1a {
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		#sound-dai-cells = <0>;

		port@0 {
			wm_speaker: endpoint {
				dai-format = "i2s";
				remote-endpoint = <&i2s_aux>;
			};
		};
	};
};

&emmc {
	status = "okay";
};

&eth {
	status = "okay";
	phy-handle = <&ethphy>;
};

&mdio {
	ethphy: ethernet-phy@1 {
		reg = <1>;
	};
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&ahci {
	status = "okay";
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier PXs2 Vodka Board
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

/dts-v1/;
#include "uniphier-pxs2.dtsi"

/ {
	model = "UniPhier PXs2 Vodka Board";
	compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &serial2;
		serial1 = &serial0;
		serial2 = &serial1;
		i2c0 = &i2c0;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		ethernet0 = ð
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x80000000>;
	};

	sound {
		compatible = "audio-graph-card";
		label = "UniPhier PXs2";
		dais = <&spdif_port0
			&comp_spdif_port0>;
	};

	spdif-out {
		compatible = "linux,spdif-dit";
		#sound-dai-cells = <0>;

		port@0 {
			spdif_tx: endpoint {
				remote-endpoint = <&spdif_hiecout1>;
			};
		};
	};

	comp-spdif-out {
		compatible = "linux,spdif-dit";
		#sound-dai-cells = <0>;

		port@0 {
			comp_spdif_tx: endpoint {
				remote-endpoint = <&comp_spdif_hiecout1>;
			};
		};
	};
};

&serial2 {
	status = "okay";
};

&spdif_hiecout1 {
	remote-endpoint = <&spdif_tx>;
};

&comp_spdif_hiecout1 {
	remote-endpoint = <&comp_spdif_tx>;
};

&i2c0 {
	status = "okay";
};

&emmc {
	status = "okay";
};

&eth {
	status = "okay";
	phy-handle = <&ethphy>;
};

&mdio {
	ethphy: ethernet-phy@1 {
		reg = <1>;
	};
};

&usb0 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier PXs2 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "socionext,uniphier-pxs2";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};
	};

	cpu_opp: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			clock-latency-ns = <300>;
		};
		opp-150000000 {
			opp-hz = /bits/ 64 <150000000>;
			clock-latency-ns = <300>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			clock-latency-ns = <300>;
		};
		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			clock-latency-ns = <300>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			clock-latency-ns = <300>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			clock-latency-ns = <300>;
		};
		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			clock-latency-ns = <300>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			clock-latency-ns = <300>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		arm_timer_clk: arm-timer {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;	/* 250ms */
			polling-delay = <1000>;		/* 1000ms */
			thermal-sensors = <&pvtctl>;

			trips {
				cpu_crit: cpu-crit {
					temperature = <95000>;	/* 95C */
					hysteresis = <2000>;
					type = "critical";
				};
				cpu_alert: cpu-alert {
					temperature = <85000>;	/* 85C */
					hysteresis = <2000>;
					type = "passive";
				};
			};

			cooling-maps {
				map {
					trip = <&cpu_alert>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		l2: cache-controller@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
			      <0x506c0000 0x400>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-size = <(1280 * 1024)>;
			cache-sets = <512>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		spi0: spi@54006000 {
			compatible = "socionext,uniphier-scssi";
			status = "disabled";
			reg = <0x54006000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi0>;
			clocks = <&peri_clk 11>;
			resets = <&peri_rst 11>;
		};

		spi1: spi@54006100 {
			compatible = "socionext,uniphier-scssi";
			status = "disabled";
			reg = <0x54006100 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi1>;
			clocks = <&peri_clk 12>;
			resets = <&peri_rst 12>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			resets = <&peri_rst 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			resets = <&peri_rst 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			resets = <&peri_rst 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			resets = <&peri_rst 3>;
		};

		gpio: gpio@55000000 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000000 0x200>;
			interrupt-parent = <&aidet>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 0>,
				      <&pinctrl 96 0 0>;
			gpio-ranges-group-names = "gpio_range0",
						  "gpio_range1";
			ngpios = <232>;
			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
						     <21 217 3>;
		};

		audio@56000000 {
			compatible = "socionext,uniphier-pxs2-aio";
			reg = <0x56000000 0x80000>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_ain1>,
				    <&pinctrl_ain2>,
				    <&pinctrl_ainiec1>,
				    <&pinctrl_aout2>,
				    <&pinctrl_aout3>,
				    <&pinctrl_aoutiec1>,
				    <&pinctrl_aoutiec2>;
			clock-names = "aio";
			clocks = <&sys_clk 40>;
			reset-names = "aio";
			resets = <&sys_rst 40>;
			#sound-dai-cells = <1>;
			socionext,syscon = <&soc_glue>;

			i2s_port0: port@0 {
				i2s_hdmi: endpoint {
				};
			};

			i2s_port1: port@1 {
				i2s_line: endpoint {
				};
			};

			i2s_port2: port@2 {
				i2s_aux: endpoint {
				};
			};

			spdif_port0: port@3 {
				spdif_hiecout1: endpoint {
				};
			};

			spdif_port1: port@4 {
				spdif_iecout1: endpoint {
				};
			};

			comp_spdif_port0: port@5 {
				comp_spdif_hiecout1: endpoint {
				};
			};

			comp_spdif_port1: port@6 {
				comp_spdif_iecout1: endpoint {
				};
			};
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			resets = <&peri_rst 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			resets = <&peri_rst 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			clocks = <&peri_clk 6>;
			resets = <&peri_rst 6>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			resets = <&peri_rst 7>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c4: i2c@58784000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58784000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&peri_clk 8>;
			resets = <&peri_rst 8>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for STM */
		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&peri_clk 9>;
			resets = <&peri_rst 9>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for HDMI */
		i2c6: i2c@58786000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58786000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&peri_clk 10>;
			resets = <&peri_rst 10>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		sdctrl@59810000 {
			compatible = "socionext,uniphier-pxs2-sdctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x400>;

			sd_clk: clock {
				compatible = "socionext,uniphier-pxs2-sd-clock";
				#clock-cells = <1>;
			};

			sd_rst: reset {
				compatible = "socionext,uniphier-pxs2-sd-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-pxs2-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-pxs2-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-pxs2-peri-reset";
				#reset-cells = <1>;
			};
		};

		emmc: mmc@5a000000 {
			compatible = "socionext,uniphier-sd-v3.1.1";
			status = "disabled";
			reg = <0x5a000000 0x800>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc>;
			clocks = <&sd_clk 1>;
			reset-names = "host", "hw";
			resets = <&sd_rst 1>, <&sd_rst 6>;
			bus-width = <8>;
			cap-mmc-highspeed;
			cap-mmc-hw-reset;
			non-removable;
		};

		sd: mmc@5a400000 {
			compatible = "socionext,uniphier-sd-v3.1.1";
			status = "disabled";
			reg = <0x5a400000 0x800>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default", "uhs";
			pinctrl-0 = <&pinctrl_sd>;
			pinctrl-1 = <&pinctrl_sd_uhs>;
			clocks = <&sd_clk 0>;
			reset-names = "host";
			resets = <&sd_rst 0>;
			bus-width = <4>;
			cap-sd-highspeed;
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
		};

		soc_glue: soc-glue@5f800000 {
			compatible = "socionext,uniphier-pxs2-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-pxs2-pinctrl";
			};
		};

		soc-glue@5f900000 {
			compatible = "socionext,uniphier-pxs2-soc-glue-debug",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x5f900000 0x2000>;

			efuse@100 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x100 0x28>;
			};

			efuse@200 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x200 0x58>;
			};
		};

		xdmac: dma-controller@5fc10000 {
			compatible = "socionext,uniphier-xdmac";
			reg = <0x5fc10000 0x5300>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <16>;
			#dma-cells = <2>;
		};

		aidet: interrupt-controller@5fc20000 {
			compatible = "socionext,uniphier-pxs2-aidet";
			reg = <0x5fc20000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <GIC_PPI 11
				(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-pxs2-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-pxs2-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-pxs2-reset";
				#reset-cells = <1>;
			};

			pvtctl: thermal-sensor {
				compatible = "socionext,uniphier-pxs2-thermal";
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				#thermal-sensor-cells = <0>;
				socionext,tmod-calibration = <0x0f86 0x6844>;
			};
		};

		eth: ethernet@65000000 {
			compatible = "socionext,uniphier-pxs2-ave4";
			status = "disabled";
			reg = <0x65000000 0x8500>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_ether_rgmii>;
			clock-names = "ether";
			clocks = <&sys_clk 6>;
			reset-names = "ether";
			resets = <&sys_rst 6>;
			phy-mode = "rgmii-id";
			local-mac-address = [00 00 00 00 00 00];
			socionext,syscon-phy-mode = <&soc_glue 0>;

			mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		ahci: sata@65600000 {
			compatible = "socionext,uniphier-pxs2-ahci",
				     "generic-ahci";
			status = "disabled";
			reg = <0x65600000 0x10000>;
			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sys_clk 28>;
			resets = <&sys_rst 28>, <&ahci_rst 0>;
			ports-implemented = <1>;
			phys = <&ahci_phy>;
		};

		sata-controller@65700000 {
			compatible = "socionext,uniphier-pxs2-ahci-glue",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x65700000 0x100>;

			ahci_rst: reset-controller@0 {
				compatible = "socionext,uniphier-pxs2-ahci-reset";
				reg = <0x0 0x4>;
				clock-names = "link";
				clocks = <&sys_clk 28>;
				reset-names = "link";
				resets = <&sys_rst 28>;
				#reset-cells = <1>;
			};

			ahci_phy: sata-phy@10 {
				compatible = "socionext,uniphier-pxs2-ahci-phy";
				reg = <0x10 0x10>;
				clock-names = "link";
				clocks = <&sys_clk 28>;
				reset-names = "link", "phy";
				resets = <&sys_rst 28>, <&sys_rst 30>;
				#phy-cells = <0>;
			};
		};

		usb0: usb@65a00000 {
			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
			status = "disabled";
			reg = <0x65a00000 0xcd00>;
			interrupt-names = "dwc_usb3";
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
			clock-names = "ref", "bus_early", "suspend";
			clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
			resets = <&usb0_rst 15>;
			phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
			       <&usb0_ssphy0>, <&usb0_ssphy1>;
			dr_mode = "host";
		};

		usb-controller@65b00000 {
			compatible = "socionext,uniphier-pxs2-dwc3-glue",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x65b00000 0x400>;

			usb0_rst: reset@0 {
				compatible = "socionext,uniphier-pxs2-usb3-reset";
				reg = <0x0 0x4>;
				#reset-cells = <1>;
				clock-names = "link";
				clocks = <&sys_clk 14>;
				reset-names = "link";
				resets = <&sys_rst 14>;
			};

			usb0_vbus0: regulator@100 {
				compatible = "socionext,uniphier-pxs2-usb3-regulator";
				reg = <0x100 0x10>;
				clock-names = "link";
				clocks = <&sys_clk 14>;
				reset-names = "link";
				resets = <&sys_rst 14>;
			};

			usb0_vbus1: regulator@110 {
				compatible = "socionext,uniphier-pxs2-usb3-regulator";
				reg = <0x110 0x10>;
				clock-names = "link";
				clocks = <&sys_clk 14>;
				reset-names = "link";
				resets = <&sys_rst 14>;
			};

			usb0_hsphy0: hs-phy@200 {
				compatible = "socionext,uniphier-pxs2-usb3-hsphy";
				reg = <0x200 0x10>;
				#phy-cells = <0>;
				clock-names = "link", "phy";
				clocks = <&sys_clk 14>, <&sys_clk 16>;
				reset-names = "link", "phy";
				resets = <&sys_rst 14>, <&sys_rst 16>;
				vbus-supply = <&usb0_vbus0>;
			};

			usb0_hsphy1: hs-phy@210 {
				compatible = "socionext,uniphier-pxs2-usb3-hsphy";
				reg = <0x210 0x10>;
				#phy-cells = <0>;
				clock-names = "link", "phy";
				clocks = <&sys_clk 14>, <&sys_clk 16>;
				reset-names = "link", "phy";
				resets = <&sys_rst 14>, <&sys_rst 16>;
				vbus-supply = <&usb0_vbus1>;
			};

			usb0_ssphy0: ss-phy@300 {
				compatible = "socionext,uniphier-pxs2-usb3-ssphy";
				reg = <0x300 0x10>;
				#phy-cells = <0>;
				clock-names = "link", "phy";
				clocks = <&sys_clk 14>, <&sys_clk 17>;
				reset-names = "link", "phy";
				resets = <&sys_rst 14>, <&sys_rst 17>;
				vbus-supply = <&usb0_vbus0>;
			};

			usb0_ssphy1: ss-phy@310 {
				compatible = "socionext,uniphier-pxs2-usb3-ssphy";
				reg = <0x310 0x10>;
				#phy-cells = <0>;
				clock-names = "link", "phy";
				clocks = <&sys_clk 14>, <&sys_clk 18>;
				reset-names = "link", "phy";
				resets = <&sys_rst 14>, <&sys_rst 18>;
				vbus-supply = <&usb0_vbus1>;
			};
		};

		usb1: usb@65c00000 {
			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
			status = "disabled";
			reg = <0x65c00000 0xcd00>;
			interrupt-names = "dwc_usb3";
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
			clock-names = "ref", "bus_early", "suspend";
			clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
			resets = <&usb1_rst 15>;
			phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
			dr_mode = "host";
		};

		usb-controller@65d00000 {
			compatible = "socionext,uniphier-pxs2-dwc3-glue",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x65d00000 0x400>;

			usb1_rst: reset@0 {
				compatible = "socionext,uniphier-pxs2-usb3-reset";
				reg = <0x0 0x4>;
				#reset-cells = <1>;
				clock-names = "link";
				clocks = <&sys_clk 15>;
				reset-names = "link";
				resets = <&sys_rst 15>;
			};

			usb1_vbus0: regulator@100 {
				compatible = "socionext,uniphier-pxs2-usb3-regulator";
				reg = <0x100 0x10>;
				clock-names = "link";
				clocks = <&sys_clk 15>;
				reset-names = "link";
				resets = <&sys_rst 15>;
			};

			usb1_vbus1: regulator@110 {
				compatible = "socionext,uniphier-pxs2-usb3-regulator";
				reg = <0x110 0x10>;
				clock-names = "link";
				clocks = <&sys_clk 15>;
				reset-names = "link";
				resets = <&sys_rst 15>;
			};

			usb1_hsphy0: hs-phy@200 {
				compatible = "socionext,uniphier-pxs2-usb3-hsphy";
				reg = <0x200 0x10>;
				#phy-cells = <0>;
				clock-names = "link", "phy";
				clocks = <&sys_clk 15>, <&sys_clk 20>;
				reset-names = "link", "phy";
				resets = <&sys_rst 15>, <&sys_rst 20>;
				vbus-supply = <&usb1_vbus0>;
			};

			usb1_hsphy1: hs-phy@210 {
				compatible = "socionext,uniphier-pxs2-usb3-hsphy";
				reg = <0x210 0x10>;
				#phy-cells = <0>;
				clock-names = "link", "phy";
				clocks = <&sys_clk 15>, <&sys_clk 20>;
				reset-names = "link", "phy";
				resets = <&sys_rst 15>, <&sys_rst 20>;
				vbus-supply = <&usb1_vbus1>;
			};

			usb1_ssphy0: ss-phy@300 {
				compatible = "socionext,uniphier-pxs2-usb3-ssphy";
				reg = <0x300 0x10>;
				#phy-cells = <0>;
				clock-names = "link", "phy";
				clocks = <&sys_clk 15>, <&sys_clk 21>;
				reset-names = "link", "phy";
				resets = <&sys_rst 15>, <&sys_rst 21>;
				vbus-supply = <&usb1_vbus0>;
			};
		};

		nand: nand-controller@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5b";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			clock-names = "nand", "nand_x", "ecc";
			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
			reset-names = "nand", "reg";
			resets = <&sys_rst 2>, <&sys_rst 2>;
		};
	};
};

#include "uniphier-pinctrl.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Reference Daughter Board
//
// Copyright (C) 2015-2017 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

&i2c0 {
	eeprom@50 {
		compatible = "microchip,24lc128", "atmel,24c128";
		reg = <0x50>;
		pagesize = <64>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier sLD8 Reference Board
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

/dts-v1/;
#include "uniphier-sld8.dtsi"
#include "uniphier-ref-daughter.dtsi"
#include "uniphier-support-card.dtsi"

/ {
	model = "UniPhier sLD8 Reference Board";
	compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &serial0;
		serial1 = &serialsc;
		serial2 = &serial2;
		serial3 = &serial3;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};
};

&ethsc {
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};

&serialsc {
	interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};

&serial0 {
	status = "okay";
};

&serial2 {
	status = "okay";
};

&serial3 {
	status = "okay";
};

&gpio {
	xirq0-hog {
		gpio-hog;
		gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
		input;
	};
};

&i2c0 {
	status = "okay";
};

&sd {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&usb2 {
	status = "okay";
};

&nand {
	status = "okay";

	nand@0 {
		reg = <0>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier sLD8 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "socionext,uniphier-sld8";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		arm_timer_clk: arm-timer {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		l2: cache-controller@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
			      <0x506c0000 0x400>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-size = <(256 * 1024)>;
			cache-sets = <256>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		spi: spi@54006000 {
			compatible = "socionext,uniphier-scssi";
			status = "disabled";
			reg = <0x54006000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_spi0>;
			clocks = <&peri_clk 11>;
			resets = <&peri_rst 11>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			resets = <&peri_rst 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			resets = <&peri_rst 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			resets = <&peri_rst 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			resets = <&peri_rst 3>;
		};

		gpio: gpio@55000000 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000000 0x200>;
			interrupt-parent = <&aidet>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 0>,
				      <&pinctrl 104 0 0>,
				      <&pinctrl 112 0 0>;
			gpio-ranges-group-names = "gpio_range0",
						  "gpio_range1",
						  "gpio_range2";
			ngpios = <136>;
			socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
		};

		i2c0: i2c@58400000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58400000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			resets = <&peri_rst 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58480000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58480000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			resets = <&peri_rst 5>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c2: i2c@58500000 {
			compatible = "socionext,uniphier-i2c";
			reg = <0x58500000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			clocks = <&peri_clk 6>;
			resets = <&peri_rst 6>;
			clock-frequency = <400000>;
		};

		i2c3: i2c@58580000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58580000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			resets = <&peri_rst 7>;
			clock-frequency = <100000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		mioctrl@59810000 {
			compatible = "socionext,uniphier-sld8-mioctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x800>;

			mio_clk: clock {
				compatible = "socionext,uniphier-sld8-mio-clock";
				#clock-cells = <1>;
			};

			mio_rst: reset {
				compatible = "socionext,uniphier-sld8-mio-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-sld8-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-sld8-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-sld8-peri-reset";
				#reset-cells = <1>;
			};
		};

		dmac: dma-controller@5a000000 {
			compatible = "socionext,uniphier-mio-dmac";
			reg = <0x5a000000 0x1000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mio_clk 7>;
			resets = <&mio_rst 7>;
			#dma-cells = <1>;
		};

		sd: mmc@5a400000 {
			compatible = "socionext,uniphier-sd-v2.91";
			status = "disabled";
			reg = <0x5a400000 0x200>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default", "uhs";
			pinctrl-0 = <&pinctrl_sd>;
			pinctrl-1 = <&pinctrl_sd_uhs>;
			clocks = <&mio_clk 0>;
			reset-names = "host", "bridge";
			resets = <&mio_rst 0>, <&mio_rst 3>;
			dma-names = "rx-tx";
			dmas = <&dmac 4>;
			bus-width = <4>;
			cap-sd-highspeed;
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
		};

		emmc: mmc@5a500000 {
			compatible = "socionext,uniphier-sd-v2.91";
			status = "disabled";
			reg = <0x5a500000 0x200>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc>;
			clocks = <&mio_clk 1>;
			reset-names = "host", "bridge", "hw";
			resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
			dma-names = "rx-tx";
			dmas = <&dmac 6>;
			bus-width = <8>;
			cap-mmc-highspeed;
			cap-mmc-hw-reset;
			non-removable;
		};

		usb0: usb@5a800100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a800100 0x100>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
				 <&mio_clk 12>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
				 <&mio_rst 12>;
			has-transaction-translator;
		};

		usb1: usb@5a810100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a810100 0x100>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
				 <&mio_clk 13>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
				 <&mio_rst 13>;
			has-transaction-translator;
		};

		usb2: usb@5a820100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a820100 0x100>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb2>;
			clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
				 <&mio_clk 14>;
			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
				 <&mio_rst 14>;
			has-transaction-translator;
		};

		soc-glue@5f800000 {
			compatible = "socionext,uniphier-sld8-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-sld8-pinctrl";
			};
		};

		soc-glue@5f900000 {
			compatible = "socionext,uniphier-sld8-soc-glue-debug",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x5f900000 0x2000>;

			efuse@100 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x100 0x28>;
			};

			efuse@200 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x200 0x14>;
			};
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <GIC_PPI 11
				(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		aidet: interrupt-controller@61830000 {
			compatible = "socionext,uniphier-sld8-aidet";
			reg = <0x61830000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-sld8-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-sld8-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-sld8-reset";
				#reset-cells = <1>;
			};
		};

		nand: nand-controller@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5a";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
			clock-names = "nand", "nand_x", "ecc";
			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
			reset-names = "nand", "reg";
			resets = <&sys_rst 2>, <&sys_rst 2>;
		};
	};
};

#include "uniphier-pinctrl.dtsi"


code:
// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier Support Card (Expansion Board)
//
// Copyright (C) 2015-2017 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

&system_bus {
	status = "okay";
	ranges = <1 0x00000000 0x42000000 0x02000000>;

	ethsc: ethernet@1,1f00000 {
		compatible = "smsc,lan9118", "smsc,lan9115";
		reg = <1 0x01f00000 0x1000>;
		phy-mode = "mii";
		reg-io-width = <4>;
		interrupt-parent = <&gpio>;
	};

	serialsc: serial@1,1fb0000 {
		compatible = "ns16550a";
		reg = <1 0x01fb0000 0x20>;
		clock-frequency = <12288000>;
		reg-shift = <1>;
		interrupt-parent = <&gpio>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * usb_a9260.dts - Device Tree file for Caloa USB A9260 board
 *
 *  Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */
/dts-v1/;
#include "at91sam9260.dtsi"
#include "usb_a9260_common.dtsi"

/ {
	model = "Calao USB A9260";
	compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9";

	chosen {
		bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
	};

	memory@20000000 {
		reg = <0x20000000 0x4000000>;
	};

	ahb {
		apb {
			shdwc@fffffd10 {
				atmel,wakeup-counter = <10>;
				atmel,wakeup-rtt-timer;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * usb_a926x.dts - Device Tree file for Caloa USB A926x board
 *
 *  Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */

/ {
	clocks {
		slow_xtal {
			clock-frequency = <32768>;
		};

		main_xtal {
			clock-frequency = <12000000>;
		};
	};

	ahb {
		apb {
			dbgu: serial@fffff200 {
				status = "okay";
			};

			tcb0: timer@fffa0000 {
				timer@0 {
					compatible = "atmel,tcb-timer";
					reg = <0>, <1>;
				};

				timer@2 {
					compatible = "atmel,tcb-timer";
					reg = <2>;
				};
			};

			macb0: ethernet@fffc4000 {
				phy-mode = "rmii";
				status = "okay";
			};

			usb1: gadget@fffa4000 {
				atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
				status = "okay";
			};
		};

		ebi: ebi@10000000 {
			status = "okay";

			nand_controller: nand-controller {
				status = "okay";
				pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
				pinctrl-names = "default";

				nand@3 {
					reg = <0x3 0x0 0x800000>;
					rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
					cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
					nand-bus-width = <8>;
					nand-ecc-mode = "soft";
					nand-on-flash-bbt;
					label = "atmel_nand";

					partitions {
						compatible = "fixed-partitions";
						#address-cells = <1>;
						#size-cells = <1>;

						at91bootstrap@0 {
							label = "at91bootstrap";
							reg = <0x0 0x20000>;
						};

						barebox@20000 {
							label = "barebox";
							reg = <0x20000 0x40000>;
						};

						bareboxenv@60000 {
							label = "bareboxenv";
							reg = <0x60000 0x20000>;
						};

						bareboxenv2@80000 {
							label = "bareboxenv2";
							reg = <0x80000 0x20000>;
						};

						oftree@80000 {
							label = "oftree";
							reg = <0xa0000 0x20000>;
						};

						kernel@a0000 {
							label = "kernel";
							reg = <0xc0000 0x400000>;
						};

						rootfs@4a0000 {
							label = "rootfs";
							reg = <0x4c0000 0x7800000>;
						};

						data@7ca0000 {
							label = "data";
							reg = <0x7cc0000 0x8340000>;
						};
					};
				};
			};
		};

		usb0: ohci@500000 {
			num-ports = <2>;
			status = "okay";
		};
	};

	leds {
		compatible = "gpio-leds";

		user_led {
			label = "user_led";
			gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "heartbeat";
		};
	};

	gpio_keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		#size-cells = <0>;

		user_pb {
			label = "user_pb";
			gpios = <&pioB 10 GPIO_ACTIVE_LOW>;
			linux,code = <28>;
			wakeup-source;
		};
	};

	i2c-gpio-0 {
		status = "okay";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * usb_a9263.dts - Device Tree file for Caloa USB A9293 board
 *
 *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */
/dts-v1/;
#include "at91sam9263.dtsi"

/ {
	model = "Calao USB A9263";
	compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9";

	chosen {
		bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
	};

	memory@20000000 {
		reg = <0x20000000 0x4000000>;
	};

	clocks {
		slow_xtal {
			clock-frequency = <32768>;
		};

		main_xtal {
			clock-frequency = <12000000>;
		};
	};

	ahb {
		apb {
			dbgu: serial@ffffee00 {
				status = "okay";
			};

			tcb0: timer@fff7c000 {
				timer@0 {
					compatible = "atmel,tcb-timer";
					reg = <0>, <1>;
				};

				timer@2 {
					compatible = "atmel,tcb-timer";
					reg = <2>;
				};
			};

			macb0: ethernet@fffbc000 {
				phy-mode = "rmii";
				status = "okay";
			};

			usb1: gadget@fff78000 {
				atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>;
				status = "okay";
			};

			spi0: spi@fffa4000 {
				cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>;
				status = "okay";
				flash@0 {
					compatible = "atmel,at45", "atmel,dataflash";
					reg = <0>;
					spi-max-frequency = <15000000>;
				};
			};

			shdwc@fffffd10 {
				atmel,wakeup-counter = <10>;
				atmel,wakeup-rtt-timer;
			};
		};

		ebi0: ebi@10000000 {
			status = "okay";

			nand_controller: nand-controller {
				status = "okay";
				pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
				pinctrl-names = "default";

				nand@3 {
					reg = <0x3 0x0 0x800000>;
					rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>;
					cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>;
					nand-bus-width = <8>;
					nand-ecc-mode = "soft";
					nand-on-flash-bbt;
					label = "atmel_nand";

					partitions {
						compatible = "fixed-partitions";
						#address-cells = <1>;
						#size-cells = <1>;

						at91bootstrap@0 {
							label = "at91bootstrap";
							reg = <0x0 0x20000>;
						};

						barebox@20000 {
							label = "barebox";
							reg = <0x20000 0x40000>;
						};

						bareboxenv@60000 {
							label = "bareboxenv";
							reg = <0x60000 0x20000>;
						};

						bareboxenv2@80000 {
							label = "bareboxenv2";
							reg = <0x80000 0x20000>;
						};

						oftree@80000 {
							label = "oftree";
							reg = <0xa0000 0x20000>;
						};

						kernel@a0000 {
							label = "kernel";
							reg = <0xc0000 0x400000>;
						};

						rootfs@4a0000 {
							label = "rootfs";
							reg = <0x4c0000 0x7800000>;
						};

						data@7ca0000 {
							label = "data";
							reg = <0x7cc0000 0x8340000>;
						};
					};
				};
			};
		};

		usb0: ohci@a00000 {
			num-ports = <2>;
			status = "okay";
		};
	};

	leds {
		compatible = "gpio-leds";

		user_led {
			label = "user_led";
			gpios = <&pioB 21 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	gpio_keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		#size-cells = <0>;

		user_pb {
			label = "user_pb";
			gpios = <&pioB 10 GPIO_ACTIVE_LOW>;
			linux,code = <28>;
			wakeup-source;
		};
	};

	i2c-gpio-0 {
		status = "okay";
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-only
/*
 * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board
 *
 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */

/ {
	ahb {
		apb {
			usart1: serial@fffb4000 {
				status = "okay";
			};

			usart3: serial@fffd0000 {
				status = "okay";
			};
		};
	};

	i2c-gpio@0 {
		status = "okay";
	};

	leds {
		compatible = "gpio-leds";

		user_led1 {
			label = "user_led1";
			gpios = <&pioB 20 GPIO_ACTIVE_LOW>;
		};

/*
* led already used by mother board but active as high
*		user_led2 {
*			label = "user_led2";
*			gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
*		};
*/
		user_led3 {
			label = "user_led3";
			gpios = <&pioB 22 GPIO_ACTIVE_LOW>;
		};

		user_led4 {
			label = "user_led4";
			gpios = <&pioB 23 GPIO_ACTIVE_LOW>;
		};

		red {
			label = "red";
			gpios = <&pioB 24 GPIO_ACTIVE_LOW>;
		};

		orange {
			label = "orange";
			gpios = <&pioB 30 GPIO_ACTIVE_LOW>;
		};

		green {
			label = "green";
			gpios = <&pioB 31 GPIO_ACTIVE_LOW>;
		};
	};

	gpio_keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		#size-cells = <0>;

		user_pb1 {
			label = "user_pb1";
			gpios = <&pioB 25 GPIO_ACTIVE_LOW>;
			linux,code = <0x100>;
		};

		user_pb2 {
			label = "user_pb2";
			gpios = <&pioB 13 GPIO_ACTIVE_LOW>;
			linux,code = <0x101>;
		};

		user_pb3 {
			label = "user_pb3";
			gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
			linux,code = <0x102>;
		};

		user_pb4 {
			label = "user_pb4";
			gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
			linux,code = <0x103>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board
 *
 *  Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */
/dts-v1/;
#include "usb_a9g20_common.dtsi"

/ {
	model = "Calao USB A9G20";
	compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board
 *
 *  Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */

#include "at91sam9g20.dtsi"
#include "usb_a9260_common.dtsi"

/ {
	chosen {
		bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
		stdout-path = "serial0:115200n8";
	};

	memory@20000000 {
		reg = <0x20000000 0x4000000>;
	};

	i2c-gpio-0 {
		rtc@56 {
			compatible = "microcrystal,rv3029";
			reg = <0x56>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board
 *
 *  Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */
/dts-v1/;
#include "usb_a9g20_common.dtsi"

/ {
	model = "Calao USB A9G20 Low Power";
	compatible = "calao,usb-a9g20-lpw", "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";

	ahb {
		apb {
			spi1: spi@fffcc000 {
				cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
				status = "okay";
				mmc-slot@0 {
					compatible = "mmc-spi-slot";
					reg = <0>;
					voltage-ranges = <3200 3400>;
					spi-max-frequency = <25000000>;
					interrupt-parent = <&pioC>;
					interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * The Versatile AB with the IB2 expansion board mounted.
 * This works as a superset of the Versatile AB.
 */

#include "versatile-ab.dts"

/ {
	model = "ARM Versatile AB + IB2 board";

	/* Special IB2 control register */
	syscon@27000000 {
		compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd";
		reg = <0x27000000 0x4>;
		ranges = <0x0 0x27000000 0x4>;
		#address-cells = <1>;
		#size-cells = <1>;

		led@0,4 {
			compatible = "register-bit-led";
			reg = <0x00 0x04>;
			offset = <0x00>;
			mask = <0x10>;
			label = "versatile-ib2:0";
			linux,default-trigger = "heartbeat";
			default-state = "on";
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

/ {
	model = "ARM Versatile AB";
	compatible = "arm,versatile-ab";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&vic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		i2c0 = &i2c0;
	};

	chosen {
		stdout-path = &uart0;
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x08000000>;
	};

	xtal24mhz: xtal24mhz@24M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
	};

	bridge {
		compatible = "ti,ths8134b", "ti,ths8134";
		#address-cells = <1>;
		#size-cells = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				vga_bridge_in: endpoint {
					remote-endpoint = <&clcd_pads_vga_dac>;
				};
			};

			port@1 {
				reg = <1>;

				vga_bridge_out: endpoint {
					remote-endpoint = <&vga_con_in>;
				};
			};
		};
	};

	vga {
		compatible = "vga-connector";

		port {
			vga_con_in: endpoint {
				remote-endpoint = <&vga_bridge_out>;
			};
		};
	};

	core-module@10000000 {
		compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
		reg = <0x10000000 0x200>;
		ranges = <0x0 0x10000000 0x200>;
		#address-cells = <1>;
		#size-cells = <1>;

		led@8,0 {
			compatible = "register-bit-led";
			reg = <0x08 0x04>;
			offset = <0x08>;
			mask = <0x01>;
			label = "versatile:0";
			linux,default-trigger = "heartbeat";
			default-state = "on";
		};
		led@8,1 {
			compatible = "register-bit-led";
			reg = <0x08 0x04>;
			offset = <0x08>;
			mask = <0x02>;
			label = "versatile:1";
			linux,default-trigger = "mmc0";
			default-state = "off";
		};
		led@8,2 {
			compatible = "register-bit-led";
			reg = <0x08 0x04>;
			offset = <0x08>;
			mask = <0x04>;
			label = "versatile:2";
			linux,default-trigger = "cpu0";
			default-state = "off";
		};
		led@8,3 {
			compatible = "register-bit-led";
			reg = <0x08 0x04>;
			offset = <0x08>;
			mask = <0x08>;
			label = "versatile:3";
			default-state = "off";
		};
		led@8,4 {
			compatible = "register-bit-led";
			reg = <0x08 0x04>;
			offset = <0x08>;
			mask = <0x10>;
			label = "versatile:4";
			default-state = "off";
		};
		led@8,5 {
			compatible = "register-bit-led";
			reg = <0x08 0x04>;
			offset = <0x08>;
			mask = <0x20>;
			label = "versatile:5";
			default-state = "off";
		};
		led@8,6 {
			compatible = "register-bit-led";
			reg = <0x08 0x04>;
			offset = <0x08>;
			mask = <0x40>;
			label = "versatile:6";
			default-state = "off";
		};
		led@8,7 {
			compatible = "register-bit-led";
			reg = <0x08 0x04>;
			offset = <0x08>;
			mask = <0x80>;
			label = "versatile:7";
			default-state = "off";
		};

		/* OSC1 on AB, OSC4 on PB */
		osc1: cm_aux_osc@24M {
			#clock-cells = <0>;
			compatible = "arm,versatile-cm-auxosc";
			clocks = <&xtal24mhz>;
		};

		/* The timer clock is the 24 MHz oscillator divided to 1MHz */
		timclk: timclk@1M {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <24>;
			clock-mult = <1>;
			clocks = <&xtal24mhz>;
		};

		pclk: pclk@24M {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <1>;
			clock-mult = <1>;
			clocks = <&xtal24mhz>;
		};
	};

	flash@34000000 {
		/* 64 MiB NOR flash in non-interleaved chips */
		compatible = "arm,versatile-flash", "cfi-flash";
		reg = <0x34000000 0x04000000>;
		bank-width = <4>;
		partitions {
			compatible = "arm,arm-firmware-suite";
		};
	};

	i2c0: i2c@10002000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "arm,versatile-i2c";
		reg = <0x10002000 0x1000>;

		rtc@68 {
			compatible = "dallas,ds1338";
			reg = <0x68>;
		};
	};

	net@10010000 {
		compatible = "smsc,lan91c111";
		reg = <0x10010000 0x10000>;
		interrupts = <25>;
	};

	lcd@10008000 {
		compatible = "arm,versatile-lcd";
		reg = <0x10008000 0x1000>;
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		vic: interrupt-controller@10140000 {
			compatible = "arm,versatile-vic";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x10140000 0x1000>;
			valid-mask = <0xffffffff>;
		};

		sic: interrupt-controller@10003000 {
			compatible = "arm,versatile-sic";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x10003000 0x1000>;
			interrupt-parent = <&vic>;
			interrupts = <31>; /* Cascaded to vic */
			clear-mask = <0xffffffff>;
			/*
			 * Valid interrupt lines mask according to
			 * table 4-36 page 4-50 of ARM DUI 0225D
			 */
			valid-mask = <0x0760031b>;
		};

		dma@10130000 {
			compatible = "arm,pl081", "arm,primecell";
			reg = <0x10130000 0x1000>;
			interrupts = <17>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		uart0: uart@101f1000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f1000 0x1000>;
			interrupts = <12>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart1: uart@101f2000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f2000 0x1000>;
			interrupts = <13>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart2: uart@101f3000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f3000 0x1000>;
			interrupts = <14>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		smc@10100000 {
			compatible = "arm,primecell";
			reg = <0x10100000 0x1000>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		mpmc@10110000 {
			compatible = "arm,primecell";
			reg = <0x10110000 0x1000>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		display@10120000 {
			compatible = "arm,pl110", "arm,primecell";
			reg = <0x10120000 0x1000>;
			interrupts = <16>;
			clocks = <&osc1>, <&pclk>;
			clock-names = "clcdclk", "apb_pclk";
			/* 800x600 16bpp @ 36MHz works fine */
			max-memory-bandwidth = <54000000>;

			/*
			 * This port is routed through a PLD (Programmable
			 * Logic Device) that routes the output from the CLCD
			 * (after transformations) to the VGA DAC and also an
			 * external panel connector. The PLD is essential for
			 * supporting RGB565/BGR565.
			 *
			 * The signals from the port thus reaches two endpoints.
			 * The PLD is managed through a few special bits in the
			 * FPGA "sysreg".
			 *
			 * This arrangement can be clearly seen in
			 * ARM DUI 0225D, page 3-41, figure 3-19.
			 */
			port@0 {
				#address-cells = <1>;
				#size-cells = <0>;

				clcd_pads_panel: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&panel_in>;
					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
				};
				clcd_pads_vga_dac: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vga_bridge_in>;
					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
				};
			};
		};

		sctl@101e0000 {
			compatible = "arm,primecell";
			reg = <0x101e0000 0x1000>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		watchdog@101e1000 {
			compatible = "arm,primecell";
			reg = <0x101e1000 0x1000>;
			interrupts = <0>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		timer@101e2000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x101e2000 0x1000>;
			interrupts = <4>;
			clocks = <&timclk>, <&timclk>, <&pclk>;
			clock-names = "timer0", "timer1", "apb_pclk";
		};

		timer@101e3000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x101e3000 0x1000>;
			interrupts = <5>;
			clocks = <&timclk>, <&timclk>, <&pclk>;
			clock-names = "timer0", "timer1", "apb_pclk";
		};

		gpio0: gpio@101e4000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x101e4000 0x1000>;
			gpio-controller;
			interrupts = <6>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		gpio1: gpio@101e5000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x101e5000 0x1000>;
			interrupts = <7>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		rtc@101e8000 {
			compatible = "arm,pl030", "arm,primecell";
			reg = <0x101e8000 0x1000>;
			interrupts = <10>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		sci@101f0000 {
			compatible = "arm,primecell";
			reg = <0x101f0000 0x1000>;
			interrupts = <15>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		spi@101f4000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x101f4000 0x1000>;
			interrupts = <11>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "sspclk", "apb_pclk";
		};

		fpga {
			compatible = "arm,versatile-fpga", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x10000000 0x10000>;

			sysreg@0 {
				compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
				reg = <0x00000 0x1000>;

				panel: display@0 {
					compatible = "arm,versatile-tft-panel";

					port {
						panel_in: endpoint {
							remote-endpoint = <&clcd_pads_panel>;
						};
					};
				};
			};

			aaci@4000 {
				compatible = "arm,primecell";
				reg = <0x4000 0x1000>;
				interrupts = <24>;
				clocks = <&pclk>;
				clock-names = "apb_pclk";
			};
			mmc@5000 {
				compatible = "arm,pl180", "arm,primecell";
				reg = <0x5000 0x1000>;
				interrupts-extended = <&vic 22 &sic 1>;
				clocks = <&xtal24mhz>, <&pclk>;
				clock-names = "mclk", "apb_pclk";
			};
			kmi@6000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x6000 0x1000>;
				interrupt-parent = <&sic>;
				interrupts = <3>;
				clocks = <&xtal24mhz>, <&pclk>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};
			kmi@7000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x7000 0x1000>;
				interrupt-parent = <&sic>;
				interrupts = <4>;
				clocks = <&xtal24mhz>, <&pclk>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
#include "versatile-ab.dts"

/ {
	model = "ARM Versatile PB";
	compatible = "arm,versatile-pb";

	amba {
		/* The Versatile PB is using more SIC IRQ lines than the AB */
		sic: interrupt-controller@10003000 {
			clear-mask = <0xffffffff>;
			/*
			 * Valid interrupt lines mask according to
			 * figure 3-30 page 3-74 of ARM DUI 0224B
			 */
			valid-mask = <0x7fe003ff>;
		};

		gpio2: gpio@101e6000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x101e6000 0x1000>;
			interrupts = <8>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		gpio3: gpio@101e7000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x101e7000 0x1000>;
			interrupts = <9>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		pci@10001000 {
			compatible = "arm,versatile-pci";
			device_type = "pci";
			reg = <0x10001000 0x1000
			       0x41000000 0x10000
			       0x42000000 0x100000>;
			bus-range = <0 0xff>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;

			ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000   /* downstream I/O */
				  0x02000000 0 0x50000000 0x50000000 0 0x10000000   /* non-prefetchable memory */
				  0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */

			interrupt-map-mask = <0x1800 0 0 7>;
			interrupt-map = <0x1800 0 0 1 &sic 28
					 0x1800 0 0 2 &sic 29
					 0x1800 0 0 3 &sic 30
					 0x1800 0 0 4 &sic 27

					 0x1000 0 0 1 &sic 27
					 0x1000 0 0 2 &sic 28
					 0x1000 0 0 3 &sic 29
					 0x1000 0 0 4 &sic 30

					 0x0800 0 0 1 &sic 30
					 0x0800 0 0 2 &sic 27
					 0x0800 0 0 3 &sic 28
					 0x0800 0 0 4 &sic 29

					 0x0000 0 0 1 &sic 29
					 0x0000 0 0 2 &sic 30
					 0x0000 0 0 3 &sic 27
					 0x0000 0 0 4 &sic 28>;
		};

		fpga {
			mmc@5000 {
				/*
				 * Overrides the interrupt assignment from
				 * the Versatile AB board file.
				 */
				interrupts-extended = <&sic 22 &sic 23>;
			};
			uart@9000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x9000 0x1000>;
				interrupt-parent = <&sic>;
				interrupts = <6>;
				clocks = <&xtal24mhz>, <&pclk>;
				clock-names = "uartclk", "apb_pclk";
			};
			sci@a000 {
				compatible = "arm,primecell";
				reg = <0xa000 0x1000>;
				interrupt-parent = <&sic>;
				interrupts = <5>;
				clocks = <&xtal24mhz>;
				clock-names = "apb_pclk";
			};
			mmc@b000 {
				compatible = "arm,pl180", "arm,primecell";
				reg = <0xb000 0x1000>;
				interrupt-parent = <&sic>;
				interrupts = <1>, <2>;
				clocks = <&xtal24mhz>, <&pclk>;
				clock-names = "mclk", "apb_pclk";
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * ARM Ltd. Versatile Express
 *
 * Motherboard Express uATX
 * V2M-P1
 *
 * HBI-0190D
 *
 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
 * Technical Reference Manual)
 *
 * WARNING! The hardware described in this file is independent from the
 * original variant (vexpress-v2m.dtsi), but there is a strong
 * correspondence between the two configurations.
 *
 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
 * CHANGES TO vexpress-v2m.dtsi!
 */
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	v2m_fixed_3v3: fixed-regulator-0 {
		compatible = "regulator-fixed";
		regulator-name = "3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	v2m_clk24mhz: clk24mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "v2m:clk24mhz";
	};

	v2m_refclk1mhz: refclk1mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <1000000>;
		clock-output-names = "v2m:refclk1mhz";
	};

	v2m_refclk32khz: refclk32khz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "v2m:refclk32khz";
	};

	leds {
		compatible = "gpio-leds";

		led-1 {
			label = "v2m:green:user1";
			gpios = <&v2m_led_gpios 0 0>;
			linux,default-trigger = "heartbeat";
		};

		led-2 {
			label = "v2m:green:user2";
			gpios = <&v2m_led_gpios 1 0>;
			linux,default-trigger = "disk-activity";
		};

		led-3 {
			label = "v2m:green:user3";
			gpios = <&v2m_led_gpios 2 0>;
			linux,default-trigger = "cpu0";
		};

		led-4 {
			label = "v2m:green:user4";
			gpios = <&v2m_led_gpios 3 0>;
			linux,default-trigger = "cpu1";
		};

		led-5 {
			label = "v2m:green:user5";
			gpios = <&v2m_led_gpios 4 0>;
			linux,default-trigger = "cpu2";
		};

		led-6 {
			label = "v2m:green:user6";
			gpios = <&v2m_led_gpios 5 0>;
			linux,default-trigger = "cpu3";
		};

		led-7 {
			label = "v2m:green:user7";
			gpios = <&v2m_led_gpios 6 0>;
			linux,default-trigger = "cpu4";
		};

		led-8 {
			label = "v2m:green:user8";
			gpios = <&v2m_led_gpios 7 0>;
			linux,default-trigger = "cpu5";
		};
	};

	bus@8000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 63>;
		interrupt-map = <0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
				<0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
				<0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
				<0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
				<0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
				<0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
				<0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
				<0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
				<0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
				<0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
				<0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				<0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				<0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				<0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				<0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				<0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
				<0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
				<0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				<0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
				<0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
				<0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
				<0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
				<0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
				<0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				<0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
				<0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
				<0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
				<0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
				<0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				<0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				<0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				<0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
				<0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
				<0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
				<0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
				<0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
				<0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
				<0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
				<0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				<0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				<0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				<0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;

		motherboard-bus@8000000 {
			arm,hbi = <0x190>;
			arm,vexpress,site = <0>;
			compatible = "arm,vexpress,v2m-p1", "simple-bus";
			#address-cells = <2>; /* SMB chipselect number and offset */
			#size-cells = <1>;
			ranges = <0 0 0x08000000 0x04000000>,
				 <1 0 0x14000000 0x04000000>,
				 <2 0 0x18000000 0x04000000>,
				 <3 0 0x1c000000 0x04000000>,
				 <4 0 0x0c000000 0x04000000>,
				 <5 0 0x10000000 0x04000000>;

			nor_flash: flash@0 {
				compatible = "arm,vexpress-flash", "cfi-flash";
				reg = <0 0x00000000 0x04000000>,
				      <4 0x00000000 0x04000000>;
				bank-width = <4>;
				partitions {
					compatible = "arm,arm-firmware-suite";
				};
			};

			psram@100000000 {
				compatible = "arm,vexpress-psram", "mtd-ram";
				reg = <1 0x00000000 0x02000000>;
				bank-width = <4>;
			};

			ethernet@202000000 {
				compatible = "smsc,lan9118", "smsc,lan9115";
				reg = <2 0x02000000 0x10000>;
				interrupts = <15>;
				phy-mode = "mii";
				reg-io-width = <4>;
				smsc,irq-active-high;
				smsc,irq-push-pull;
				vdd33a-supply = <&v2m_fixed_3v3>;
				vddvario-supply = <&v2m_fixed_3v3>;
			};

			usb@203000000 {
				compatible = "nxp,usb-isp1761";
				reg = <2 0x03000000 0x20000>;
				interrupts = <16>;
				dr_mode = "peripheral";
			};

			iofpga-bus@300000000 {
				compatible = "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 3 0 0x200000>;

				v2m_sysreg: sysreg@10000 {
					compatible = "arm,vexpress-sysreg";
					reg = <0x010000 0x1000>;
					#address-cells = <1>;
					#size-cells = <1>;
					ranges = <0 0x10000 0x1000>;

					v2m_led_gpios: gpio@8 {
						compatible = "arm,vexpress-sysreg,sys_led";
						reg = <0x008 4>;
						gpio-controller;
						#gpio-cells = <2>;
					};

					v2m_mmc_gpios: gpio@48 {
						compatible = "arm,vexpress-sysreg,sys_mci";
						reg = <0x048 4>;
						gpio-controller;
						#gpio-cells = <2>;
					};

					v2m_flash_gpios: gpio@4c {
						compatible = "arm,vexpress-sysreg,sys_flash";
						reg = <0x04c 4>;
						gpio-controller;
						#gpio-cells = <2>;
					};
				};

				v2m_sysctl: sysctl@20000 {
					compatible = "arm,sp810", "arm,primecell";
					reg = <0x020000 0x1000>;
					clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
					clock-names = "refclk", "timclk", "apb_pclk";
					#clock-cells = <1>;
					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
					assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
					assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
				};

				/* PCI-E I2C bus */
				v2m_i2c_pcie: i2c@30000 {
					compatible = "arm,versatile-i2c";
					reg = <0x030000 0x1000>;

					#address-cells = <1>;
					#size-cells = <0>;

					pcie-switch@60 {
						compatible = "idt,89hpes32h8";
						reg = <0x60>;
					};
				};

				aaci@40000 {
					compatible = "arm,pl041", "arm,primecell";
					reg = <0x040000 0x1000>;
					interrupts = <11>;
					clocks = <&smbclk>;
					clock-names = "apb_pclk";
				};

				mmc@50000 {
					compatible = "arm,pl180", "arm,primecell";
					reg = <0x050000 0x1000>;
					interrupts = <9>, <10>;
					cd-gpios = <&v2m_mmc_gpios 0 0>;
					wp-gpios = <&v2m_mmc_gpios 1 0>;
					max-frequency = <12000000>;
					vmmc-supply = <&v2m_fixed_3v3>;
					clocks = <&v2m_clk24mhz>, <&smbclk>;
					clock-names = "mclk", "apb_pclk";
				};

				kmi@60000 {
					compatible = "arm,pl050", "arm,primecell";
					reg = <0x060000 0x1000>;
					interrupts = <12>;
					clocks = <&v2m_clk24mhz>, <&smbclk>;
					clock-names = "KMIREFCLK", "apb_pclk";
				};

				kmi@70000 {
					compatible = "arm,pl050", "arm,primecell";
					reg = <0x070000 0x1000>;
					interrupts = <13>;
					clocks = <&v2m_clk24mhz>, <&smbclk>;
					clock-names = "KMIREFCLK", "apb_pclk";
				};

				v2m_serial0: serial@90000 {
					compatible = "arm,pl011", "arm,primecell";
					reg = <0x090000 0x1000>;
					interrupts = <5>;
					clocks = <&v2m_oscclk2>, <&smbclk>;
					clock-names = "uartclk", "apb_pclk";
				};

				v2m_serial1: serial@a0000 {
					compatible = "arm,pl011", "arm,primecell";
					reg = <0x0a0000 0x1000>;
					interrupts = <6>;
					clocks = <&v2m_oscclk2>, <&smbclk>;
					clock-names = "uartclk", "apb_pclk";
				};

				v2m_serial2: serial@b0000 {
					compatible = "arm,pl011", "arm,primecell";
					reg = <0x0b0000 0x1000>;
					interrupts = <7>;
					clocks = <&v2m_oscclk2>, <&smbclk>;
					clock-names = "uartclk", "apb_pclk";
				};

				v2m_serial3: serial@c0000 {
					compatible = "arm,pl011", "arm,primecell";
					reg = <0x0c0000 0x1000>;
					interrupts = <8>;
					clocks = <&v2m_oscclk2>, <&smbclk>;
					clock-names = "uartclk", "apb_pclk";
				};

				watchdog@f0000 {
					compatible = "arm,sp805", "arm,primecell";
					reg = <0x0f0000 0x1000>;
					interrupts = <0>;
					clocks = <&v2m_refclk32khz>, <&smbclk>;
					clock-names = "wdog_clk", "apb_pclk";
				};

				v2m_timer01: timer@110000 {
					compatible = "arm,sp804", "arm,primecell";
					reg = <0x110000 0x1000>;
					interrupts = <2>;
					clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
					clock-names = "timclken1", "timclken2", "apb_pclk";
				};

				v2m_timer23: timer@120000 {
					compatible = "arm,sp804", "arm,primecell";
					reg = <0x120000 0x1000>;
					interrupts = <3>;
					clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
					clock-names = "timclken1", "timclken2", "apb_pclk";
				};

				/* DVI I2C bus */
				v2m_i2c_dvi: i2c@160000 {
					compatible = "arm,versatile-i2c";
					reg = <0x160000 0x1000>;
					#address-cells = <1>;
					#size-cells = <0>;

					dvi-transmitter@39 {
						compatible = "sil,sii9022-tpi", "sil,sii9022";
						reg = <0x39>;

						ports {
							#address-cells = <1>;
							#size-cells = <0>;

							port@0 {
								reg = <0>;
								dvi_bridge_in: endpoint {
									remote-endpoint = <&clcd_pads>;
								};
							};
						};
					};

					dvi-transmitter@60 {
						compatible = "sil,sii9022-cpi", "sil,sii9022";
						reg = <0x60>;
					};
				};

				rtc@170000 {
					compatible = "arm,pl031", "arm,primecell";
					reg = <0x170000 0x1000>;
					interrupts = <4>;
					clocks = <&smbclk>;
					clock-names = "apb_pclk";
				};

				compact-flash@1a0000 {
					compatible = "arm,vexpress-cf", "ata-generic";
					reg = <0x1a0000 0x100
					       0x1a0100 0xf00>;
					reg-shift = <2>;
				};

				clcd@1f0000 {
					compatible = "arm,pl111", "arm,primecell";
					reg = <0x1f0000 0x1000>;
					interrupt-names = "combined";
					interrupts = <14>;
					clocks = <&v2m_oscclk1>, <&smbclk>;
					clock-names = "clcdclk", "apb_pclk";
					/* 800x600 16bpp @36MHz works fine */
					max-memory-bandwidth = <54000000>;
					memory-region = <&vram>;

					port {
						clcd_pads: endpoint {
							remote-endpoint = <&dvi_bridge_in>;
							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
						};
					};
				};

				mcc {
					compatible = "arm,vexpress,config-bus";
					arm,vexpress,config-bridge = <&v2m_sysreg>;

					oscclk0 {
						/* MCC static memory clock */
						compatible = "arm,vexpress-osc";
						arm,vexpress-sysreg,func = <1 0>;
						freq-range = <25000000 60000000>;
						#clock-cells = <0>;
						clock-output-names = "v2m:oscclk0";
					};

					v2m_oscclk1: oscclk1 {
						/* CLCD clock */
						compatible = "arm,vexpress-osc";
						arm,vexpress-sysreg,func = <1 1>;
						freq-range = <23750000 65000000>;
						#clock-cells = <0>;
						clock-output-names = "v2m:oscclk1";
					};

					v2m_oscclk2: oscclk2 {
						/* IO FPGA peripheral clock */
						compatible = "arm,vexpress-osc";
						arm,vexpress-sysreg,func = <1 2>;
						freq-range = <24000000 24000000>;
						#clock-cells = <0>;
						clock-output-names = "v2m:oscclk2";
					};

					volt-vio {
						/* Logic level voltage */
						compatible = "arm,vexpress-volt";
						arm,vexpress-sysreg,func = <2 0>;
						regulator-name = "VIO";
						regulator-always-on;
						label = "VIO";
					};

					temp-mcc {
						/* MCC internal operating temperature */
						compatible = "arm,vexpress-temp";
						arm,vexpress-sysreg,func = <4 0>;
						label = "MCC";
					};

					reset {
						compatible = "arm,vexpress-reset";
						arm,vexpress-sysreg,func = <5 0>;
					};

					muxfpga {
						compatible = "arm,vexpress-muxfpga";
						arm,vexpress-sysreg,func = <7 0>;
					};

					shutdown {
						compatible = "arm,vexpress-shutdown";
						arm,vexpress-sysreg,func = <8 0>;
					};

					reboot {
						compatible = "arm,vexpress-reboot";
						arm,vexpress-sysreg,func = <9 0>;
					};

					dvimode {
						compatible = "arm,vexpress-dvimode";
						arm,vexpress-sysreg,func = <11 0>;
					};
				};
			};
		};
	};
};