code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek PCIe PHY

maintainers:
  - Jianjun Wang <jianjun.wang@mediatek.com>

description: |
  The PCIe PHY supports physical layer functionality for PCIe Gen3 port.

properties:
  compatible:
    const: mediatek,mt8195-pcie-phy

  reg:
    maxItems: 1

  reg-names:
    items:
      - const: sif

  "#phy-cells":
    const: 0

  nvmem-cells:
    maxItems: 7
    description:
      Phandles to nvmem cell that contains the efuse data, if unspecified,
      default value is used.

  nvmem-cell-names:
    items:
      - const: glb_intr
      - const: tx_ln0_pmos
      - const: tx_ln0_nmos
      - const: rx_ln0
      - const: tx_ln1_pmos
      - const: tx_ln1_nmos
      - const: rx_ln1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    phy@11e80000 {
        compatible = "mediatek,mt8195-pcie-phy";
        #phy-cells = <0>;
        reg = <0x11e80000 0x10000>;
        reg-names = "sif";
        nvmem-cells = <&pciephy_glb_intr>,
                      <&pciephy_tx_ln0_pmos>,
                      <&pciephy_tx_ln0_nmos>,
                      <&pciephy_rx_ln0>,
                      <&pciephy_tx_ln1_pmos>,
                      <&pciephy_tx_ln1_nmos>,
                      <&pciephy_rx_ln1>;
        nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
                           "tx_ln0_nmos", "rx_ln0",
                           "tx_ln1_pmos", "tx_ln1_nmos",
                           "rx_ln1";
        power-domains = <&spm 2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek T-PHY Controller

maintainers:
  - Chunfeng Yun <chunfeng.yun@mediatek.com>

description: |
  The T-PHY controller supports physical layer functionality for a number of
  controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.

  Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
  T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
  -----------------------------------
  Version 1:
  port        offset    bank
  shared      0x0000    SPLLC
              0x0100    FMREG
  u2 port0    0x0800    U2PHY_COM
  u3 port0    0x0900    U3PHYD
              0x0a00    U3PHYD_BANK2
              0x0b00    U3PHYA
              0x0c00    U3PHYA_DA
  u2 port1    0x1000    U2PHY_COM
  u3 port1    0x1100    U3PHYD
              0x1200    U3PHYD_BANK2
              0x1300    U3PHYA
              0x1400    U3PHYA_DA
  u2 port2    0x1800    U2PHY_COM
              ...

  Version 2/3:
  port        offset    bank
  u2 port0    0x0000    MISC
              0x0100    FMREG
              0x0300    U2PHY_COM
  u3 port0    0x0700    SPLLC
              0x0800    CHIP
              0x0900    U3PHYD
              0x0a00    U3PHYD_BANK2
              0x0b00    U3PHYA
              0x0c00    U3PHYA_DA
  u2 port1    0x1000    MISC
              0x1100    FMREG
              0x1300    U2PHY_COM
  u3 port1    0x1700    SPLLC
              0x1800    CHIP
              0x1900    U3PHYD
              0x1a00    U3PHYD_BANK2
              0x1b00    U3PHYA
              0x1c00    U3PHYA_DA
  u2 port2    0x2000    MISC
              ...

  SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
  into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
  added on V2; the FMREG bank for slew rate calibration is not used anymore
  and reserved on V3;

properties:
  $nodename:
    pattern: "^t-phy@[0-9a-f]+$"

  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt2701-tphy
              - mediatek,mt7623-tphy
              - mediatek,mt7622-tphy
              - mediatek,mt8516-tphy
          - const: mediatek,generic-tphy-v1
      - items:
          - enum:
              - mediatek,mt2712-tphy
              - mediatek,mt7629-tphy
              - mediatek,mt8183-tphy
              - mediatek,mt8186-tphy
              - mediatek,mt8192-tphy
              - mediatek,mt8365-tphy
          - const: mediatek,generic-tphy-v2
      - items:
          - enum:
              - mediatek,mt8188-tphy
              - mediatek,mt8195-tphy
          - const: mediatek,generic-tphy-v3
      - const: mediatek,mt2701-u3phy
        deprecated: true
      - const: mediatek,mt2712-u3phy
        deprecated: true
      - const: mediatek,mt8173-u3phy

  reg:
    description:
      Register shared by multiple ports, exclude port's private register.
      It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
      T-PHY V2/V3, such as mt2712.
    maxItems: 1

  "#address-cells":
    enum: [1, 2]

  "#size-cells":
    enum: [1, 2]

  # Used with non-empty value if optional 'reg' is not provided.
  # The format of the value is an arbitrary number of triplets of
  # (child-bus-address, parent-bus-address, length).
  ranges: true

  mediatek,src-ref-clk-mhz:
    description:
      Frequency of reference clock for slew rate calibrate
    default: 26

  mediatek,src-coef:
    description:
      Coefficient for slew rate calibrate, depends on SoC process
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 28

# Required child node:
patternProperties:
  "^(usb|pcie|sata)-phy@[0-9a-f]+$":
    type: object
    description:
      A sub-node is required for each port the controller provides.
      Address range information including the usual 'reg' property
      is used inside these nodes to describe the controller's topology.

    properties:
      reg:
        maxItems: 1

      clocks:
        minItems: 1
        items:
          - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
          - description: Reference clock of analog phy
        description:
          Uses both clocks if the clock of analog and digital phys are
          separated, otherwise uses "ref" clock only if needed.

      clock-names:
        minItems: 1
        items:
          - const: ref
          - const: da_ref

      "#phy-cells":
        const: 1
        description: |
          The cells contain the following arguments.

          - description: The PHY type
              enum:
                - PHY_TYPE_USB2
                - PHY_TYPE_USB3
                - PHY_TYPE_PCIE
                - PHY_TYPE_SATA
                - PHY_TYPE_SGMII

      nvmem-cells:
        items:
          - description: internal R efuse for U2 PHY or U3/PCIe PHY
          - description: rx_imp_sel efuse for U3/PCIe PHY
          - description: tx_imp_sel efuse for U3/PCIe PHY
        description: |
          Phandles to nvmem cell that contains the efuse data;
          Available only for U2 PHY or U3/PCIe PHY of version 2/3, these
          three items should be provided at the same time for U3/PCIe PHY,
          when use software to load efuse;
          If unspecified, will use hardware auto-load efuse.

      nvmem-cell-names:
        items:
          - const: intr
          - const: rx_imp
          - const: tx_imp

      # The following optional vendor properties are only for debug or HQA test
      mediatek,eye-src:
        description:
          The value of slew rate calibrate (U2 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 7

      mediatek,eye-vrt:
        description:
          The selection of VRT reference voltage (U2 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 7

      mediatek,eye-term:
        description:
          The selection of HS_TX TERM reference voltage (U2 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 7

      mediatek,intr:
        description:
          The selection of internal resistor (U2 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 31

      mediatek,discth:
        description:
          The selection of disconnect threshold (U2 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 15

      mediatek,pre-emphasis:
        description:
          The level of pre-emphasis which used to widen the eye opening and
          boost eye swing, the unit step is about 4.16% increment; e.g. the
          level 1 means amplitude increases about 4.16%, the level 2 is about
          8.3% etc. (U2 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 3

      mediatek,bc12:
        description:
          Specify the flag to enable BC1.2 if support it
        type: boolean

      mediatek,syscon-type:
        $ref: /schemas/types.yaml#/definitions/phandle-array
        maxItems: 1
        description:
          A phandle to syscon used to access the register of type switch,
          the field should always be 3 cells long.
        items:
          items:
            - description:
                The first cell represents a phandle to syscon
            - description:
                The second cell represents the register offset
            - description:
                The third cell represents the index of config segment
              enum: [0, 1, 2, 3]

    required:
      - reg
      - "#phy-cells"

    additionalProperties: false

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/phy/phy.h>
    usb@11271000 {
        compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
        reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
        reg-names = "mac", "ippc";
        phys = <&u2port0 PHY_TYPE_USB2>,
               <&u3port0 PHY_TYPE_USB3>,
               <&u2port1 PHY_TYPE_USB2>;
        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
        clocks = <&topckgen CLK_TOP_USB30_SEL>;
        clock-names = "sys_ck";
    };

    t-phy@11290000 {
        compatible = "mediatek,mt8173-u3phy";
        reg = <0x11290000 0x800>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        u2port0: usb-phy@11290800 {
            reg = <0x11290800 0x100>;
            clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
            clock-names = "ref", "da_ref";
            #phy-cells = <1>;
        };

        u3port0: usb-phy@11290900 {
            reg = <0x11290900 0x700>;
            clocks = <&clk26m>;
            clock-names = "ref";
            #phy-cells = <1>;
        };

        u2port1: usb-phy@11291000 {
            reg = <0x11291000 0x100>;
            #phy-cells = <1>;
        };
    };

...

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Universal Flash Storage (UFS) M-PHY binding

maintainers:
  - Stanley Chu <stanley.chu@mediatek.com>
  - Chunfeng Yun <chunfeng.yun@mediatek.com>

description: |
  UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
  Each UFS M-PHY node should have its own node.
  To bind UFS M-PHY with UFS host controller, the controller node should
  contain a phandle reference to UFS M-PHY node.

properties:
  $nodename:
    pattern: "^ufs-phy@[0-9a-f]+$"

  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt8195-ufsphy
          - const: mediatek,mt8183-ufsphy
      - const: mediatek,mt8183-ufsphy

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Unipro core control clock.
      - description: M-PHY core control clock.

  clock-names:
    items:
      - const: unipro
      - const: mp

  "#phy-cells":
    const: 0

required:
  - compatible
  - reg
  - "#phy-cells"
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
    ufsphy: ufs-phy@11fa0000 {
        compatible = "mediatek,mt8183-ufsphy";
        reg = <0x11fa0000 0xc000>;
        clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
                 <&infracfg CLK_INFRA_UFS_MP_SAP_BCLK>;
        clock-names = "unipro", "mp";
        #phy-cells = <0>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek XS-PHY Controller

maintainers:
  - Chunfeng Yun <chunfeng.yun@mediatek.com>

description: |
  The XS-PHY controller supports physical layer functionality for USB3.1
  GEN2 controller on MediaTek SoCs.

  Banks layout of xsphy
  ----------------------------------
  port        offset    bank
  u2 port0    0x0000    MISC
              0x0100    FMREG
              0x0300    U2PHY_COM
  u2 port1    0x1000    MISC
              0x1100    FMREG
              0x1300    U2PHY_COM
  u2 port2    0x2000    MISC
              ...
  u31 common  0x3000    DIG_GLB
              0x3100    PHYA_GLB
  u31 port0   0x3400    DIG_LN_TOP
              0x3500    DIG_LN_TX0
              0x3600    DIG_LN_RX0
              0x3700    DIG_LN_DAIF
              0x3800    PHYA_LN
  u31 port1   0x3a00    DIG_LN_TOP
              0x3b00    DIG_LN_TX0
              0x3c00    DIG_LN_RX0
              0x3d00    DIG_LN_DAIF
              0x3e00    PHYA_LN
              ...
  DIG_GLB & PHYA_GLB are shared by U31 ports.

properties:
  $nodename:
    pattern: "^xs-phy@[0-9a-f]+$"

  compatible:
    items:
      - enum:
          - mediatek,mt3611-xsphy
          - mediatek,mt3612-xsphy
      - const: mediatek,xsphy

  reg:
    description:
      Register shared by multiple U3 ports, exclude port's private register,
      if only U2 ports provided, shouldn't use the property.
    maxItems: 1

  "#address-cells":
    enum: [1, 2]

  "#size-cells":
    enum: [1, 2]

  ranges: true

  mediatek,src-ref-clk-mhz:
    description:
      Frequency of reference clock for slew rate calibrate
    default: 26

  mediatek,src-coef:
    description:
      Coefficient for slew rate calibrate, depends on SoC process
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 17

# Required child node:
patternProperties:
  "^usb-phy@[0-9a-f]+$":
    type: object
    description:
      A sub-node is required for each port the controller provides.
      Address range information including the usual 'reg' property
      is used inside these nodes to describe the controller's topology.

    properties:
      reg:
        maxItems: 1

      clocks:
        items:
          - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)

      clock-names:
        items:
          - const: ref

      "#phy-cells":
        const: 1
        description: |
          The cells contain the following arguments.

          - description: The PHY type
              enum:
                - PHY_TYPE_USB2
                - PHY_TYPE_USB3

      # The following optional vendor properties are only for debug or HQA test
      mediatek,eye-src:
        description:
          The value of slew rate calibrate (U2 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 7

      mediatek,eye-vrt:
        description:
          The selection of VRT reference voltage (U2 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 7

      mediatek,eye-term:
        description:
          The selection of HS_TX TERM reference voltage (U2 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 7

      mediatek,efuse-intr:
        description:
          The selection of Internal Resistor (U2/U3 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 63

      mediatek,efuse-tx-imp:
        description:
          The selection of TX Impedance (U3 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 31

      mediatek,efuse-rx-imp:
        description:
          The selection of RX Impedance (U3 phy)
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 31

    required:
      - reg
      - clocks
      - clock-names
      - "#phy-cells"

    additionalProperties: false

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/phy/phy.h>

    u3phy: xs-phy@11c40000 {
        compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
        reg = <0x11c43000 0x0200>;
        mediatek,src-ref-clk-mhz = <26>;
        mediatek,src-coef = <17>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        u2port0: usb-phy@11c40000 {
            reg = <0x11c40000 0x0400>;
            clocks = <&clk48m>;
            clock-names = "ref";
            mediatek,eye-src = <4>;
            #phy-cells = <1>;
        };

        u3port0: usb-phy@11c43000 {
            reg = <0x11c43400 0x0500>;
            clocks = <&clk26m>;
            clock-names = "ref";
            mediatek,efuse-intr = <28>;
            #phy-cells = <1>;
        };
    };

...


code:
* Amlogic Meson GXL and GXM USB2 PHY binding

Required properties:
- compatible:	Should be "amlogic,meson-gxl-usb2-phy"
- reg:		The base address and length of the registers
- #phys-cells:	must be 0 (see phy-bindings.txt in this directory)

Optional properties:
- clocks:	a phandle to the clock of this PHY
- clock-names:	must be "phy"
- resets:	a phandle to the reset line of this PHY
- reset-names:	must be "phy"
- phy-supply:	see phy-bindings.txt in this directory

Example:
	usb2_phy0: phy@78000 {
		compatible = "amlogic,meson-gxl-usb2-phy";
		#phy-cells = <0>;
		reg = <0x0 0x78000 0x0 0x20>;
	};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/microchip,lan966x-serdes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip Lan966x Serdes controller

maintainers:
  - Horatiu Vultur <horatiu.vultur@microchip.com>

description: |
  Lan966x has 7 interfaces, consisting of 2 copper transceivers(CU),
  3 SERDES6G and 2 RGMII interfaces. Two of the SERDES6G support QSGMII.
  Also it has 8 logical Ethernet ports which can be connected to these
  interfaces. The Serdes controller will allow to configure these interfaces
  and allows to "mux" the interfaces to different ports.

  For simple selection of the interface that is used with a port, the
  following macros are defined CU(X), SERDES6G(X), RGMII(X). Where X is a
  number that represents the index of that interface type. For example
  CU(1) means use interface copper transceivers 1. SERDES6G(2) means use
  interface SerDes 2.

properties:
  $nodename:
    pattern: "^serdes@[0-9a-f]+$"

  compatible:
    const: microchip,lan966x-serdes

  reg:
    items:
      - description: HSIO registers
      - description: HW_STAT register

  '#phy-cells':
    const: 2
    description: |
      - Input port to use for a given macro.
      - The macro to be used. The macros are defined in
        dt-bindings/phy/phy-lan966x-serdes.

required:
  - compatible
  - reg
  - '#phy-cells'

additionalProperties: false

examples:
  - |
    serdes: serdes@e2004010 {
      compatible = "microchip,lan966x-serdes";
      reg = <0xe202c000 0x9c>, <0xe2004010 0x4>;
      #phy-cells = <2>;
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip Sparx5 Serdes controller

maintainers:
  - Steen Hegelund <steen.hegelund@microchip.com>

description: |
  The Sparx5 SERDES interfaces share the same basic functionality, but
  support different operating modes and line rates.

  The following list lists the SERDES features:

  * RX Adaptive Decision Feedback Equalizer (DFE)
  * Programmable continuous time linear equalizer (CTLE)
  * Rx variable gain control
  * Rx built-in fault detector (loss-of-lock/loss-of-signal)
  * Adjustable tx de-emphasis (FFE)
  * Tx output amplitude control
  * Supports rx eye monitor
  * Multiple loopback modes
  * Prbs generator and checker
  * Polarity inversion control

  SERDES6G:

  The SERDES6G is a high-speed SERDES interface, which can operate at
  the following data rates:

  * 100 Mbps (100BASE-FX)
  * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
  * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
  * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)

  SERDES10G

  The SERDES10G is a high-speed SERDES interface, which can operate at
  the following data rates:

  * 100 Mbps (100BASE-FX)
  * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
  * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
  * 5 Gbps (QSGMII/USGMII)
  * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
  * 10 Gbps (10G-USGMII)
  * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)

  SERDES25G

  The SERDES25G is a high-speed SERDES interface, which can operate at
  the following data rates:

  * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
  * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
  * 5 Gbps (QSGMII/USGMII)
  * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
  * 10 Gbps (10G-USGMII)
  * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
  * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)

properties:
  $nodename:
    pattern: "^serdes@[0-9a-f]+$"

  compatible:
    const: microchip,sparx5-serdes

  reg:
    minItems: 1

  '#phy-cells':
    const: 1
    description: |
      - The main serdes input port

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - '#phy-cells'
  - clocks

additionalProperties: false

examples:
  - |
    serdes: serdes@10808000 {
      compatible = "microchip,sparx5-serdes";
      #phy-cells = <1>;
      clocks = <&sys_clk>;
      reg = <0x10808000 0x5d0000>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mixel DSI PHY for i.MX8

maintainers:
  - Guido Günther <agx@sigxcpu.org>

description: |
  The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
  MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
  electrical signals for DSI.

  The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
  in either MIPI-DSI PHY mode or LVDS PHY mode.

properties:
  compatible:
    enum:
      - fsl,imx8mq-mipi-dphy
      - fsl,imx8qxp-mipi-dphy

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: phy_ref

  assigned-clocks:
    maxItems: 1

  assigned-clock-parents:
    maxItems: 1

  assigned-clock-rates:
    maxItems: 1

  "#phy-cells":
    const: 0

  fsl,syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      A phandle which points to Control and Status Registers(CSR) module.

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#phy-cells"
  - power-domains

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8mq-mipi-dphy
    then:
      properties:
        fsl,syscon: false

      required:
        - assigned-clocks
        - assigned-clock-parents
        - assigned-clock-rates

  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8qxp-mipi-dphy
    then:
      properties:
        assigned-clocks: false
        assigned-clock-parents: false
        assigned-clock-rates: false

      required:
        - fsl,syscon

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mq-clock.h>
    dphy: dphy@30a0030 {
        compatible = "fsl,imx8mq-mipi-dphy";
        reg = <0x30a00300 0x100>;
        clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
        clock-names = "phy_ref";
        assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
        assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
        assigned-clock-rates = <24000000>;
        #phy-cells = <0>;
        power-domains = <&pgc_mipi>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mscc,vsc7514-serdes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microsemi Ocelot SerDes muxing

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>
  - UNGLinuxDriver@microchip.com

description: |
  On Microsemi Ocelot, there is a handful of registers in HSIO address
  space for setting up the SerDes to switch port muxing.

  A SerDes X can be "muxed" to work with switch port Y or Z for example.
  One specific SerDes can also be used as a PCIe interface.

  Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.

  There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
  half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
  10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.

  Also, SERDES6G number (aka "macro") 0 is the only interface supporting
  QSGMII.

  This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
  Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot.

properties:
  compatible:
    enum:
      - mscc,vsc7514-serdes

  "#phy-cells":
    const: 2
    description: |
      The first number defines the input port to use for a given SerDes macro.
      The second defines the macro to use. They are defined in
      dt-bindings/phy/phy-ocelot-serdes.h

required:
  - compatible
  - "#phy-cells"

additionalProperties:
  false

examples:
  - |
    serdes: serdes {
      compatible = "mscc,vsc7514-serdes";
      #phy-cells = <2>;
    };


code:
* Freescale MXS USB Phy Device

Required properties:
- compatible: should contain:
	* "fsl,imx23-usbphy" for imx23 and imx28
	* "fsl,imx6q-usbphy" for imx6dq and imx6dl
	* "fsl,imx6sl-usbphy" for imx6sl
	* "fsl,vf610-usbphy" for Vybrid vf610
	* "fsl,imx6sx-usbphy" for imx6sx
	* "fsl,imx7ulp-usbphy" for imx7ulp
	* "fsl,imx8dxl-usbphy" for imx8dxl
  "fsl,imx23-usbphy" is still a fallback for other strings
- reg: Should contain registers location and length
- interrupts: Should contain phy interrupt
- fsl,anatop: phandle for anatop register, it is only for imx6 SoC series

Optional properties:
- fsl,tx-cal-45-dn-ohms: Integer [35-54]. Resistance (in ohms) of switchable
  high-speed trimming resistor connected in parallel with the 45 ohm resistor
  that terminates the DN output signal. Default: 45
- fsl,tx-cal-45-dp-ohms: Integer [35-54]. Resistance (in ohms) of switchable
  high-speed trimming resistor connected in parallel with the 45 ohm resistor
  that terminates the DP output signal. Default: 45
- fsl,tx-d-cal: Integer [79-119]. Current trimming value (as a percentage) of
  the 17.78mA TX reference current. Default: 100

Example:
usbphy1: usb-phy@20c9000 {
	compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
	reg = <0x020c9000 0x1000>;
	interrupts = <0 44 0x04>;
	fsl,anatop = <&anatop>;
};


code:
Device tree binding for NVIDIA Tegra XUSB pad controller
========================================================

The Tegra XUSB pad controller manages a set of I/O lanes (with differential
signals) which connect directly to pins/pads on the SoC package. Each lane
is controlled by a HW block referred to as a "pad" in the Tegra hardware
documentation. Each such "pad" may control either one or multiple lanes,
and thus contains any logic common to all its lanes. Each lane can be
separately configured and powered up.

Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
super-speed USB. Other lanes are for various types of low-speed, full-speed
or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
contains a software-configurable mux that sits between the I/O controller
ports (e.g. PCIe) and the lanes.

In addition to per-lane configuration, USB 3.0 ports may require additional
settings on a per-board basis.

Pads will be represented as children of the top-level XUSB pad controller
device tree node. Each lane exposed by the pad will be represented by its
own subnode and can be referenced by users of the lane using the standard
PHY bindings, as described by the phy-bindings.txt file in this directory.

The Tegra hardware documentation refers to the connection between the XUSB
pad controller and the XUSB controller as "ports". This is confusing since
"port" is typically used to denote the physical USB receptacle. The device
tree binding in this document uses the term "port" to refer to the logical
abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
for the USB signal, the VBUS power supply, the USB 2.0 companion port for
USB 3.0 receptacles, ...).

Required properties:
--------------------
- compatible: Must be:
  - Tegra124: "nvidia,tegra124-xusb-padctl"
  - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
  - Tegra210: "nvidia,tegra210-xusb-padctl"
  - Tegra186: "nvidia,tegra186-xusb-padctl"
  - Tegra194: "nvidia,tegra194-xusb-padctl"
- reg: Physical base address and length of the controller's registers.
- resets: Must contain an entry for each entry in reset-names.
- reset-names: Must include the following entries:
  - "padctl"

For Tegra124:
- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
- avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
- avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.

For Tegra210:
- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
- nvidia,pmc: phandle and specifier referring to the Tegra210 PMC node.

For Tegra186:
- avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
  power supply. Must supply 1.8 V.
- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
  3.3 V.
- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
- vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.

For Tegra194:
- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
  3.3 V.
- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.

Pad nodes:
==========

A required child node named "pads" contains a list of subnodes, one for each
of the pads exposed by the XUSB pad controller. Each pad may need additional
resources that can be referenced in its pad node.

The "status" property is used to enable or disable the use of a pad. If set
to "disabled", the pad will not be used on the given board. In order to use
the pad and any of its lanes, this property must be set to "okay".

For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
and sata. No extra resources are required for operation of these pads.

For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
a description of the properties of each pad.

UTMI pad:
---------

Required properties:
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Must contain the following entries:
  - "trk": phandle and specifier referring to the USB2 tracking clock

HSIC pad:
---------

Required properties:
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Must contain the following entries:
  - "trk": phandle and specifier referring to the HSIC tracking clock

PCIe pad:
---------

Required properties:
- clocks: Must contain an entry for each entry in clock-names.
- clock-names: Must contain the following entries:
  - "pll": phandle and specifier referring to the PLLE
- resets: Must contain an entry for each entry in reset-names.
- reset-names: Must contain the following entries:
  - "phy": reset for the PCIe UPHY block

SATA pad:
---------

Required properties:
- resets: Must contain an entry for each entry in reset-names.
- reset-names: Must contain the following entries:
  - "phy": reset for the SATA UPHY block

PHY nodes:
==========

Each pad node has a child named "lanes" that contains one or more children of
its own, each representing one of the lanes controlled by the pad.

Required properties:
--------------------
- status: Defines the operation status of the PHY. Valid values are:
  - "disabled": the PHY is disabled
  - "okay": the PHY is enabled
- #phy-cells: Should be 0. Since each lane represents a single PHY, there is
  no need for an additional specifier.
- nvidia,function: The output function of the PHY. See below for a list of
  valid functions per SoC generation.

For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
- usb2: usb2-0, usb2-1, usb2-2
  - functions: "snps", "xusb", "uart"
- ulpi: ulpi-0
  - functions: "snps", "xusb"
- hsic: hsic-0, hsic-1
  - functions: "snps", "xusb"
- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
  - functions: "pcie", "usb3-ss"
- sata: sata-0
  - functions: "usb3-ss", "sata"

For Tegra210, the list of valid PHY nodes is given below:
- usb2: usb2-0, usb2-1, usb2-2, usb2-3
  - functions: "snps", "xusb", "uart"
- hsic: hsic-0, hsic-1
  - functions: "snps", "xusb"
- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
  - functions: "pcie-x1", "usb3-ss", "pcie-x4"
- sata: sata-0
  - functions: "usb3-ss", "sata"

For Tegra194, the list of valid PHY nodes is given below:
- usb2: usb2-0, usb2-1, usb2-2, usb2-3
  - functions: "xusb"
- usb3: usb3-0, usb3-1, usb3-2, usb3-3
  - functions: "xusb"

Port nodes:
===========

A required child node named "ports" contains a list of all the ports exposed
by the XUSB pad controller. Per-port configuration is only required for USB.

USB2 ports:
-----------

Required properties:
- status: Defines the operation status of the port. Valid values are:
  - "disabled": the port is disabled
  - "okay": the port is enabled
- mode: A string that determines the mode in which to run the port. Valid
  values are:
  - "host": for USB host mode
  - "device": for USB device mode
  - "otg": for USB OTG mode

Required properties for OTG/Peripheral capable USB2 ports:
- usb-role-switch: Boolean property to indicate that the port support OTG or
  peripheral mode. If present, the port supports switching between USB host
  and peripheral roles. Connector should be added as subnode.
  See usb/usb-conn-gpio.txt.

Optional properties:
- nvidia,internal: A boolean property whose presence determines that a port
  is internal. In the absence of this property the port is considered to be
  external.
- vbus-supply: phandle to a regulator supplying the VBUS voltage.

ULPI ports:
-----------

Optional properties:
- status: Defines the operation status of the port. Valid values are:
  - "disabled": the port is disabled
  - "okay": the port is enabled
- nvidia,internal: A boolean property whose presence determines that a port
  is internal. In the absence of this property the port is considered to be
  external.
- vbus-supply: phandle to a regulator supplying the VBUS voltage.

HSIC ports:
-----------

Required properties:
- status: Defines the operation status of the port. Valid values are:
  - "disabled": the port is disabled
  - "okay": the port is enabled

Optional properties:
- vbus-supply: phandle to a regulator supplying the VBUS voltage.

Super-speed USB ports:
----------------------

Required properties:
- status: Defines the operation status of the port. Valid values are:
  - "disabled": the port is disabled
  - "okay": the port is enabled
- nvidia,usb2-companion: A single cell that specifies the physical port number
  to map this super-speed USB port to. The range of valid port numbers varies
  with the SoC generation:
  - 0-2: for Tegra124 and Tegra132
  - 0-3: for Tegra210

Optional properties:
- nvidia,internal: A boolean property whose presence determines that a port
  is internal. In the absence of this property the port is considered to be
  external.

- maximum-speed: Only for Tegra194. A string property that specifies maximum
  supported speed of a usb3 port. Valid values are:
  - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
  - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.

For Tegra124 and Tegra132, the XUSB pad controller exposes the following
ports:
- 3x USB2: usb2-0, usb2-1, usb2-2
- 1x ULPI: ulpi-0
- 2x HSIC: hsic-0, hsic-1
- 2x super-speed USB: usb3-0, usb3-1

For Tegra210, the XUSB pad controller exposes the following ports:
- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
- 2x HSIC: hsic-0, hsic-1
- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3

For Tegra194, the XUSB pad controller exposes the following ports:
- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3

Examples:
=========

Tegra124 and Tegra132:
----------------------

SoC include:

	padctl@7009f000 {
		/* for Tegra124 */
		compatible = "nvidia,tegra124-xusb-padctl";
		/* for Tegra132 */
		compatible = "nvidia,tegra132-xusb-padctl",
			     "nvidia,tegra124-xusb-padctl";
		reg = <0x0 0x7009f000 0x0 0x1000>;
		resets = <&tegra_car 142>;
		reset-names = "padctl";

		pads {
			usb2 {
				status = "disabled";

				lanes {
					usb2-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb2-1 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb2-2 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			ulpi {
				status = "disabled";

				lanes {
					ulpi-0 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			hsic {
				status = "disabled";

				lanes {
					hsic-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					hsic-1 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			pcie {
				status = "disabled";

				lanes {
					pcie-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-1 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-2 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-3 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-4 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			sata {
				status = "disabled";

				lanes {
					sata-0 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};
		};

		ports {
			usb2-0 {
				status = "disabled";
			};

			usb2-1 {
				status = "disabled";
			};

			usb2-2 {
				status = "disabled";
			};

			ulpi-0 {
				status = "disabled";
			};

			hsic-0 {
				status = "disabled";
			};

			hsic-1 {
				status = "disabled";
			};

			usb3-0 {
				status = "disabled";
			};

			usb3-1 {
				status = "disabled";
			};
		};
	};

Board file:

	padctl@7009f000 {
		status = "okay";

		pads {
			usb2 {
				status = "okay";

				lanes {
					usb2-0 {
						nvidia,function = "xusb";
						status = "okay";
					};

					usb2-1 {
						nvidia,function = "xusb";
						status = "okay";
					};

					usb2-2 {
						nvidia,function = "xusb";
						status = "okay";
					};
				};
			};

			pcie {
				status = "okay";

				lanes {
					pcie-0 {
						nvidia,function = "usb3-ss";
						status = "okay";
					};

					pcie-2 {
						nvidia,function = "pcie";
						status = "okay";
					};

					pcie-4 {
						nvidia,function = "pcie";
						status = "okay";
					};
				};
			};

			sata {
				status = "okay";

				lanes {
					sata-0 {
						nvidia,function = "sata";
						status = "okay";
					};
				};
			};
		};

		ports {
			/* Micro A/B */
			usb2-0 {
				status = "okay";
				mode = "otg";
			};

			/* Mini PCIe */
			usb2-1 {
				status = "okay";
				mode = "host";
			};

			/* USB3 */
			usb2-2 {
				status = "okay";
				mode = "host";

				vbus-supply = <&vdd_usb3_vbus>;
			};

			usb3-0 {
				nvidia,port = <2>;
				status = "okay";
			};
		};
	};

Tegra210:
---------

SoC include:

	padctl@7009f000 {
		compatible = "nvidia,tegra210-xusb-padctl";
		reg = <0x0 0x7009f000 0x0 0x1000>;
		resets = <&tegra_car 142>;
		reset-names = "padctl";

		status = "disabled";

		pads {
			usb2 {
				clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
				clock-names = "trk";
				status = "disabled";

				lanes {
					usb2-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb2-1 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb2-2 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb2-3 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			hsic {
				clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
				clock-names = "trk";
				status = "disabled";

				lanes {
					hsic-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					hsic-1 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			pcie {
				clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
				clock-names = "pll";
				resets = <&tegra_car 205>;
				reset-names = "phy";
				status = "disabled";

				lanes {
					pcie-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-1 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-2 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-3 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-4 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-5 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-6 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			sata {
				clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
				clock-names = "pll";
				resets = <&tegra_car 204>;
				reset-names = "phy";
				status = "disabled";

				lanes {
					sata-0 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};
		};

		ports {
			usb2-0 {
				status = "disabled";
			};

			usb2-1 {
				status = "disabled";
			};

			usb2-2 {
				status = "disabled";
			};

			usb2-3 {
				status = "disabled";
			};

			hsic-0 {
				status = "disabled";
			};

			hsic-1 {
				status = "disabled";
			};

			usb3-0 {
				status = "disabled";
			};

			usb3-1 {
				status = "disabled";
			};

			usb3-2 {
				status = "disabled";
			};

			usb3-3 {
				status = "disabled";
			};
		};
	};

Board file:

	padctl@7009f000 {
		status = "okay";

		pads {
			usb2 {
				status = "okay";

				lanes {
					usb2-0 {
						nvidia,function = "xusb";
						status = "okay";
					};

					usb2-1 {
						nvidia,function = "xusb";
						status = "okay";
					};

					usb2-2 {
						nvidia,function = "xusb";
						status = "okay";
					};

					usb2-3 {
						nvidia,function = "xusb";
						status = "okay";
					};
				};
			};

			pcie {
				status = "okay";

				lanes {
					pcie-0 {
						nvidia,function = "pcie-x1";
						status = "okay";
					};

					pcie-1 {
						nvidia,function = "pcie-x4";
						status = "okay";
					};

					pcie-2 {
						nvidia,function = "pcie-x4";
						status = "okay";
					};

					pcie-3 {
						nvidia,function = "pcie-x4";
						status = "okay";
					};

					pcie-4 {
						nvidia,function = "pcie-x4";
						status = "okay";
					};

					pcie-5 {
						nvidia,function = "usb3-ss";
						status = "okay";
					};

					pcie-6 {
						nvidia,function = "usb3-ss";
						status = "okay";
					};
				};
			};

			sata {
				status = "okay";

				lanes {
					sata-0 {
						nvidia,function = "sata";
						status = "okay";
					};
				};
			};
		};

		ports {
			usb2-0 {
				status = "okay";
				mode = "otg";
			};

			usb2-1 {
				status = "okay";
				vbus-supply = <&vdd_5v0_rtl>;
				mode = "host";
			};

			usb2-2 {
				status = "okay";
				vbus-supply = <&vdd_usb_vbus>;
				mode = "host";
			};

			usb2-3 {
				status = "okay";
				mode = "host";
			};

			usb3-0 {
				status = "okay";
				nvidia,lanes = "pcie-6";
				nvidia,port = <1>;
			};

			usb3-1 {
				status = "okay";
				nvidia,lanes = "pcie-5";
				nvidia,port = <2>;
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra USB PHY

maintainers:
  - Dmitry Osipenko <digetx@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - nvidia,tegra124-usb-phy
              - nvidia,tegra114-usb-phy
          - enum:
              - nvidia,tegra30-usb-phy
      - items:
          - enum:
              - nvidia,tegra30-usb-phy
              - nvidia,tegra20-usb-phy

  reg:
    minItems: 1
    maxItems: 2
    description: |
      PHY0 and PHY2 share power and ground, PHY0 contains shared registers.
      PHY0 and PHY2 must specify two register sets, where the first set is
      PHY own registers and the second set is the PHY0 registers.

  clocks:
    anyOf:
      - items:
          - description: Registers clock
          - description: Main PHY clock

      - items:
          - description: Registers clock
          - description: Main PHY clock
          - description: ULPI PHY clock

      - items:
          - description: Registers clock
          - description: Main PHY clock
          - description: UTMI pads control registers clock

      - items:
          - description: Registers clock
          - description: Main PHY clock
          - description: UTMI timeout clock
          - description: UTMI pads control registers clock

  clock-names:
    oneOf:
      - items:
          - const: reg
          - const: pll_u

      - items:
          - const: reg
          - const: pll_u
          - const: ulpi-link

      - items:
          - const: reg
          - const: pll_u
          - const: utmi-pads

      - items:
          - const: reg
          - const: pll_u
          - const: timer
          - const: utmi-pads

  interrupts:
    maxItems: 1

  resets:
    oneOf:
      - maxItems: 1
        description: PHY reset

      - items:
          - description: PHY reset
          - description: UTMI pads reset

  reset-names:
    oneOf:
      - const: usb

      - items:
          - const: usb
          - const: utmi-pads

  "#phy-cells":
    const: 0

  phy_type:
    $ref: /schemas/types.yaml#/definitions/string
    enum: [utmi, ulpi, hsic]

  dr_mode:
    $ref: /schemas/types.yaml#/definitions/string
    enum: [host, peripheral, otg]
    default: host

  vbus-supply:
    description: Regulator controlling USB VBUS.

  nvidia,has-legacy-mode:
    description: |
      Indicates whether this controller can operate in legacy mode
      (as APX 2500 / 2600). In legacy mode some registers are accessed
      through the APB_MISC base address instead of the USB controller.
    type: boolean

  nvidia,is-wired:
    description: |
      Indicates whether we can do certain kind of power optimizations for
      the devices that are always connected. e.g. modem.
    type: boolean

  nvidia,has-utmi-pad-registers:
    description: |
      Indicates whether this controller contains the UTMI pad control
      registers common to all USB controllers.
    type: boolean

  nvidia,hssync-start-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 31
    description: |
      Number of 480 MHz clock cycles to wait before start of sync launches
      RxActive.

  nvidia,elastic-limit:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 31
    description: Variable FIFO Depth of elastic input store.

  nvidia,idle-wait-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 31
    description: |
      Number of 480 MHz clock cycles of idle to wait before declare IDLE.

  nvidia,term-range-adj:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 15
    description: Range adjustment on terminations.

  nvidia,xcvr-setup:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 127
    description: Input of XCVR cell, HS driver output control.

  nvidia,xcvr-setup-use-fuses:
    description: Indicates that the value is read from the on-chip fuses.
    type: boolean

  nvidia,xcvr-lsfslew:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 3
    description: LS falling slew rate control.

  nvidia,xcvr-lsrslew:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 3
    description: LS rising slew rate control.

  nvidia,xcvr-hsslew:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 511
    description: HS slew rate control.

  nvidia,hssquelch-level:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 3
    description: HS squelch detector level.

  nvidia,hsdiscon-level:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 7
    description: HS disconnect detector level.

  nvidia,phy-reset-gpio:
    maxItems: 1
    description: GPIO used to reset the PHY.

  nvidia,pmc:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to Power Management controller.
          - description: USB controller ID.
    description:
      Phandle to Power Management controller.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - reset-names
  - "#phy-cells"
  - phy_type

additionalProperties: false

allOf:
  - if:
      properties:
        phy_type:
          const: utmi

    then:
      properties:
        reg:
          minItems: 2
          maxItems: 2

        resets:
          maxItems: 2

        reset-names:
          maxItems: 2

      required:
        - nvidia,hssync-start-delay
        - nvidia,elastic-limit
        - nvidia,idle-wait-delay
        - nvidia,term-range-adj
        - nvidia,xcvr-lsfslew
        - nvidia,xcvr-lsrslew

      anyOf:
        - required: ["nvidia,xcvr-setup"]
        - required: ["nvidia,xcvr-setup-use-fuses"]

      if:
        properties:
          compatible:
            contains:
              const: nvidia,tegra30-usb-phy

      then:
        properties:
          clocks:
            maxItems: 3

          clock-names:
            items:
              - const: reg
              - const: pll_u
              - const: utmi-pads

        required:
          - nvidia,xcvr-hsslew
          - nvidia,hssquelch-level
          - nvidia,hsdiscon-level

      else:
        properties:
          clocks:
            maxItems: 4

          clock-names:
            items:
              - const: reg
              - const: pll_u
              - const: timer
              - const: utmi-pads

  - if:
      properties:
        phy_type:
          const: ulpi

    then:
      properties:
        reg:
          minItems: 1
          maxItems: 1

        clocks:
          minItems: 2
          maxItems: 3

        clock-names:
          minItems: 2
          maxItems: 3

          oneOf:
            - items:
                - const: reg
                - const: pll_u

            - items:
                - const: reg
                - const: pll_u
                - const: ulpi-link

        resets:
          minItems: 1
          maxItems: 2

        reset-names:
          minItems: 1
          maxItems: 2

examples:
  - |
    #include <dt-bindings/clock/tegra124-car.h>

    usb-phy@7d008000 {
        compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
        reg = <0x7d008000 0x4000>,
              <0x7d000000 0x4000>;
        interrupts = <0 97 4>;
        phy_type = "utmi";
        clocks = <&tegra_car TEGRA124_CLK_USB3>,
                 <&tegra_car TEGRA124_CLK_PLL_U>,
                 <&tegra_car TEGRA124_CLK_USBD>;
        clock-names = "reg", "pll_u", "utmi-pads";
        resets = <&tegra_car 59>, <&tegra_car 22>;
        reset-names = "usb", "utmi-pads";
        #phy-cells = <0>;
        nvidia,hssync-start-delay = <0>;
        nvidia,idle-wait-delay = <17>;
        nvidia,elastic-limit = <16>;
        nvidia,term-range-adj = <6>;
        nvidia,xcvr-setup = <9>;
        nvidia,xcvr-lsfslew = <0>;
        nvidia,xcvr-lsrslew = <3>;
        nvidia,hssquelch-level = <2>;
        nvidia,hsdiscon-level = <5>;
        nvidia,xcvr-hsslew = <12>;
        nvidia,pmc = <&tegra_pmc 2>;
    };

  - |
    #include <dt-bindings/clock/tegra20-car.h>

    usb-phy@c5004000 {
        compatible = "nvidia,tegra20-usb-phy";
        reg = <0xc5004000 0x4000>;
        interrupts = <0 21 4>;
        phy_type = "ulpi";
        clocks = <&tegra_car TEGRA20_CLK_USB2>,
                 <&tegra_car TEGRA20_CLK_PLL_U>,
                 <&tegra_car TEGRA20_CLK_CDEV2>;
        clock-names = "reg", "pll_u", "ulpi-link";
        resets = <&tegra_car 58>, <&tegra_car 22>;
        reset-names = "usb", "utmi-pads";
        #phy-cells = <0>;
        nvidia,pmc = <&tegra_pmc 1>;
    };


code:
mvebu armada 38x comphy driver
------------------------------

This comphy controller can be found on Marvell Armada 38x. It provides a
number of shared PHYs used by various interfaces (network, sata, usb,
PCIe...).

Required properties:

- compatible: should be "marvell,armada-380-comphy"
- reg: should contain the comphy register location and length.
- #address-cells: should be 1.
- #size-cells: should be 0.

Optional properties:

- reg-names: must be "comphy" as the first name, and "conf".
- reg: must contain the comphy register location and length as the first
    pair, followed by an optional configuration register address and
    length pair.

A sub-node is required for each comphy lane provided by the comphy.

Required properties (child nodes):

- reg: comphy lane number.
- #phy-cells : from the generic phy bindings, must be 1. Defines the
               input port to use for a given comphy lane.

Example:

	comphy: phy@18300 {
		compatible = "marvell,armada-380-comphy";
		reg-names = "comphy", "conf";
		reg = <0x18300 0x100>, <0x18460 4>;
		#address-cells = <1>;
		#size-cells = <0>;

		cpm_comphy0: phy@0 {
			reg = <0>;
			#phy-cells = <1>;
		};

		cpm_comphy1: phy@1 {
			reg = <1>;
			#phy-cells = <1>;
		};
	};


code:
* Atheros AR71XX/9XXX USB PHY

Required properties:
- compatible: "qca,ar7100-usb-phy"
- #phys-cells: should be 0
- reset-names: "phy"[, "suspend-override"]
- resets: references to the reset controllers

Example:

	usb-phy {
		compatible = "qca,ar7100-usb-phy";

		reset-names = "phy", "suspend-override";
		resets = <&rst 4>, <&rst 3>;

		#phy-cells = <0>;
	};


code:
This document explains only the device tree data binding. For general
information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst

PHY device node
===============

Required Properties:
#phy-cells:	Number of cells in a PHY specifier;  The meaning of all those
		cells is defined by the binding for the phy node. The PHY
		provider can use the values in cells to find the appropriate
		PHY.

Optional Properties:
phy-supply:	Phandle to a regulator that provides power to the PHY. This
		regulator will be managed during the PHY power on/off sequence.

For example:

phys: phy {
    compatible = "xxx";
    reg = <...>;
    .
    .
    #phy-cells = <1>;
    .
    .
};

That node describes an IP block (PHY provider) that implements 2 different PHYs.
In order to differentiate between these 2 PHYs, an additional specifier should be
given while trying to get a reference to it.

PHY user node
=============

Required Properties:
phys : the phandle for the PHY device (used by the PHY subsystem; not to be
       confused with the Ethernet specific 'phy' and 'phy-handle' properties,
       see Documentation/devicetree/bindings/net/ethernet.txt for these)
phy-names : the names of the PHY corresponding to the PHYs present in the
	    *phys* phandle

Example 1:
usb1: usb_otg_ss@xxx {
    compatible = "xxx";
    reg = <xxx>;
    .
    .
    phys = <&usb2_phy>, <&usb3_phy>;
    phy-names = "usb2phy", "usb3phy";
    .
    .
};

This node represents a controller that uses two PHYs, one for usb2 and one for
usb3.

Example 2:
usb2: usb_otg_ss@xxx {
    compatible = "xxx";
    reg = <xxx>;
    .
    .
    phys = <&phys 1>;
    phy-names = "usbphy";
    .
    .
};

This node represents a controller that uses one of the PHYs of the PHY provider
device defined previously. Note that the phy handle has an additional specifier
"1" to differentiate between the two PHYs.


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence Sierra PHY binding

description:
  This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
  multiprotocol combinations including protocols such as PCIe, USB etc.

maintainers:
  - Swapnil Jakhade <sjakhade@cadence.com>
  - Yuti Amonkar <yamonkar@cadence.com>

properties:
  compatible:
    enum:
      - cdns,sierra-phy-t0
      - ti,sierra-phy-t0

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  '#clock-cells':
    const: 1

  resets:
    minItems: 1
    items:
      - description: Sierra PHY reset.
      - description: Sierra APB reset. This is optional.

  reset-names:
    minItems: 1
    items:
      - const: sierra_reset
      - const: sierra_apb

  reg:
    maxItems: 1
    description:
      Offset of the Sierra PHY configuration registers.

  reg-names:
    const: serdes

  clocks:
    minItems: 2
    maxItems: 4

  clock-names:
    minItems: 2
    items:
      - const: cmn_refclk_dig_div
      - const: cmn_refclk1_dig_div
      - const: pll0_refclk
      - const: pll1_refclk

  assigned-clocks:
    minItems: 1
    maxItems: 2

  assigned-clock-parents:
    minItems: 1
    maxItems: 2

  cdns,autoconf:
    type: boolean
    description:
      A boolean property whose presence indicates that the PHY registers will be
      configured by hardware. If not present, all sub-node optional properties
      must be provided.

patternProperties:
  '^phy@[0-9a-f]$':
    type: object
    description:
      Each group of PHY lanes with a single master lane should be represented as
      a sub-node. Note that the actual configuration of each lane is determined
      by hardware strapping, and must match the configuration specified here.
    properties:
      reg:
        description:
          The master lane number. This is the lowest numbered lane in the lane group.
        minimum: 0
        maximum: 15

      resets:
        minItems: 1
        maxItems: 4
        description:
          Contains list of resets, one per lane, to get all the link lanes out of reset.

      "#phy-cells":
        const: 0

      cdns,phy-type:
        description:
          Specifies the type of PHY for which the group of PHY lanes is used.
          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [2, 4]

      cdns,num-lanes:
        description:
          Number of lanes in this group. The group is made up of consecutive lanes.
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 16

      cdns,ssc-mode:
        description:
          Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
          EXTERNAL_SSC or INTERNAL_SSC.
          Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [0, 1, 2]
        default: 1

    required:
      - reg
      - resets
      - "#phy-cells"

    additionalProperties: false

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - reg
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/phy/phy.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        sierra-phy@fd240000 {
            compatible = "cdns,sierra-phy-t0";
            reg = <0x0 0xfd240000 0x0 0x40000>;
            resets = <&phyrst 0>, <&phyrst 1>;
            reset-names = "sierra_reset", "sierra_apb";
            clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
            clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
            #address-cells = <1>;
            #size-cells = <0>;
            pcie0_phy0: phy@0 {
                reg = <0>;
                resets = <&phyrst 2>;
                cdns,num-lanes = <2>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_PCIE>;
            };
            pcie0_phy1: phy@2 {
                reg = <2>;
                resets = <&phyrst 4>;
                cdns,num-lanes = <1>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_PCIE>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence Torrent SD0801 PHY binding

description:
  This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
  hardware included with the Cadence MHDP DisplayPort controller. Torrent
  PHY also supports multilink multiprotocol combinations including protocols
  such as PCIe, USB, SGMII, QSGMII etc.

maintainers:
  - Swapnil Jakhade <sjakhade@cadence.com>
  - Yuti Amonkar <yamonkar@cadence.com>

properties:
  compatible:
    enum:
      - cdns,torrent-phy
      - ti,j721e-serdes-10g

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  '#clock-cells':
    const: 1

  clocks:
    minItems: 1
    maxItems: 2
    description:
      PHY reference clock for 1 item. Must contain an entry in clock-names.
      Optional Parent to enable output reference clock.

  clock-names:
    minItems: 1
    items:
      - const: refclk
      - const: phy_en_refclk

  assigned-clocks:
    maxItems: 3

  assigned-clock-parents:
    maxItems: 3

  reg:
    minItems: 1
    items:
      - description: Offset of the Torrent PHY configuration registers.
      - description: Offset of the DPTX PHY configuration registers.

  reg-names:
    minItems: 1
    items:
      - const: torrent_phy
      - const: dptx_phy

  resets:
    minItems: 1
    items:
      - description: Torrent PHY reset.
      - description: Torrent APB reset. This is optional.

  reset-names:
    minItems: 1
    items:
      - const: torrent_reset
      - const: torrent_apb

patternProperties:
  '^phy@[0-3]$':
    type: object
    description:
      Each group of PHY lanes with a single master lane should be represented as a sub-node.
    properties:
      reg:
        description:
          The master lane number. This is the lowest numbered lane in the lane group.
        minimum: 0
        maximum: 3

      resets:
        minItems: 1
        maxItems: 4
        description:
          Contains list of resets, one per lane, to get all the link lanes out of reset.

      "#phy-cells":
        const: 0

      cdns,phy-type:
        description:
          Specifies the type of PHY for which the group of PHY lanes is used.
          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 1
        maximum: 9

      cdns,num-lanes:
        description:
          Number of lanes.
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [1, 2, 3, 4]
        default: 4

      cdns,ssc-mode:
        description:
          Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
          EXTERNAL_SSC or INTERNAL_SSC.
          Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [0, 1, 2]
        default: 0

      cdns,max-bit-rate:
        description:
          Maximum DisplayPort link bit rate to use, in Mbps
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
        default: 8100

    required:
      - reg
      - resets
      - "#phy-cells"
      - cdns,phy-type
      - cdns,num-lanes

    additionalProperties: false

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets
  - reset-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/phy/phy.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        torrent-phy@f0fb500000 {
            compatible = "cdns,torrent-phy";
            reg = <0xf0 0xfb500000 0x0 0x00100000>,
                  <0xf0 0xfb030a00 0x0 0x00000040>;
            reg-names = "torrent_phy", "dptx_phy";
            resets = <&phyrst 0>;
            reset-names = "torrent_reset";
            clocks = <&ref_clk>;
            clock-names = "refclk";
            #address-cells = <1>;
            #size-cells = <0>;
            phy@0 {
                reg = <0>;
                resets = <&phyrst 1>, <&phyrst 2>,
                         <&phyrst 3>, <&phyrst 4>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_DP>;
                cdns,num-lanes = <4>;
                cdns,max-bit-rate = <8100>;
            };
        };
    };
  - |
    #include <dt-bindings/phy/phy.h>
    #include <dt-bindings/phy/phy-cadence.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        torrent-phy@f0fb500000 {
            compatible = "cdns,torrent-phy";
            reg = <0xf0 0xfb500000 0x0 0x00100000>;
            reg-names = "torrent_phy";
            resets = <&phyrst 0>, <&phyrst 1>;
            reset-names = "torrent_reset", "torrent_apb";
            clocks = <&ref_clk>;
            clock-names = "refclk";
            #address-cells = <1>;
            #size-cells = <0>;
            phy@0 {
                reg = <0>;
                resets = <&phyrst 2>, <&phyrst 3>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_PCIE>;
                cdns,num-lanes = <2>;
                cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
            };

            phy@2 {
                reg = <2>;
                resets = <&phyrst 4>;
                #phy-cells = <0>;
                cdns,phy-type = <PHY_TYPE_SGMII>;
                cdns,num-lanes = <1>;
                cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
            };
        };
    };
...


code:
Motorola CPCAP PMIC USB PHY binding

Required properties:
compatible: Shall be either "motorola,cpcap-usb-phy" or
	    "motorola,mapphone-cpcap-usb-phy"
#phy-cells: Shall be 0
interrupts: CPCAP PMIC interrupts used by the USB PHY
interrupt-names: Interrupt names
io-channels: IIO ADC channels used by the USB PHY
io-channel-names: IIO ADC channel names
vusb-supply: Regulator for the PHY

Optional properties:
pinctrl: Optional alternate pin modes for the PHY
pinctrl-names: Names for optional pin modes
mode-gpios: Optional GPIOs for configuring alternate modes

Example:
cpcap_usb2_phy: phy {
	compatible = "motorola,mapphone-cpcap-usb-phy";
	pinctrl-0 = <&usb_gpio_mux_sel1 &usb_gpio_mux_sel2>;
	pinctrl-1 = <&usb_ulpi_pins>;
	pinctrl-2 = <&usb_utmi_pins>;
	pinctrl-3 = <&uart3_pins>;
	pinctrl-names = "default", "ulpi", "utmi", "uart";
	#phy-cells = <0>;
	interrupts-extended = <
		&cpcap 15 0 &cpcap 14 0 &cpcap 28 0 &cpcap 19 0
		&cpcap 18 0 &cpcap 17 0 &cpcap 16 0 &cpcap 49 0
		&cpcap 48 1
	>;
	interrupt-names =
		"id_ground", "id_float", "se0conn", "vbusvld",
		"sessvld", "sessend", "se1", "dm", "dp";
	mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH
		      &gpio1 0 GPIO_ACTIVE_HIGH>;
	io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>;
	io-channel-names = "vbus", "id";
	vusb-supply = <&vusb>;
};


code:
TI DA8xx/OMAP-L1xx/AM18xx USB PHY

Required properties:
 - compatible: must be "ti,da830-usb-phy".
 - #phy-cells: must be 1.

This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
controllers on DA8xx SoCs. Consumers of this device should use index 0 for
the USB 2.0 phy device and index 1 for the USB 1.1 phy device.

It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
to access the CFGCHIP2 register.

Example:

	cfgchip: cfgchip@1417c {
		compatible = "ti,da830-cfgchip", "syscon";
		reg = <0x1417c 0x14>;
	};

	usb_phy: usb-phy {
		compatible = "ti,da830-usb-phy";
		#phy-cells = <1>;
	};

	usb20: usb@200000 {
		compatible = "ti,da830-musb";
		reg = <0x200000 0x1000>;
		interrupts = <58>;
		phys = <&usb_phy 0>;
		phy-names = "usb-phy";
	};

	usb11: usb@225000 {
		compatible = "ti,da830-ohci";
		reg = <0x225000 0x1000>;
		interrupts = <59>;
		phys = <&usb_phy 1>;
		phy-names = "usb-phy";
	};


code:
HiSilicon STB PCIE/SATA/USB3 PHY

Required properties:
- compatible: Should be "hisilicon,hi3798cv200-combphy"
- reg: Should be the address space for COMBPHY configuration and state
  registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and
  PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC.
- #phy-cells: Should be 1.  The cell number is used to select the phy mode
  as defined in <dt-bindings/phy/phy.h>.
- clocks: The phandle to clock provider and clock specifier pair.
- resets: The phandle to reset controller and reset specifier pair.

Refer to phy/phy-bindings.txt for the generic PHY binding properties.

Optional properties:
- hisilicon,fixed-mode: If the phy device doesn't support mode select
  but a fixed mode setting, the property should be present to specify
  the particular mode.
- hisilicon,mode-select-bits: If the phy device support mode select,
  this property should be present to specify the register bits in
  peripheral controller, as a 3 integers tuple:
  <register_offset bit_shift bit_mask>.

Notes:
- Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only
  one of them should be present.
- The device node should be a child of peripheral controller that contains
  COMBPHY configuration/state and PERI_CTRL register used to select PHY mode.
  Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller
  bindings.

Examples:

perictrl: peripheral-controller@8a20000 {
	compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
		     "simple-mfd";
	reg = <0x8a20000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8a20000 0x1000>;

	combphy0: phy@850 {
		compatible = "hisilicon,hi3798cv200-combphy";
		reg = <0x850 0x8>;
		#phy-cells = <1>;
		clocks = <&crg HISTB_COMBPHY0_CLK>;
		resets = <&crg 0x188 4>;
		hisilicon,fixed-mode = <PHY_TYPE_USB3>;
	};

	combphy1: phy@858 {
		compatible = "hisilicon,hi3798cv200-combphy";
		reg = <0x858 0x8>;
		#phy-cells = <1>;
		clocks = <&crg HISTB_COMBPHY1_CLK>;
		resets = <&crg 0x188 12>;
		hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
	};
};


code:
Hisilicon hi6220 usb PHY
-----------------------

Required properties:
- compatible: should be "hisilicon,hi6220-usb-phy"
- #phy-cells: must be 0
- hisilicon,peripheral-syscon: phandle of syscon used to control phy.
Refer to phy/phy-bindings.txt for the generic PHY binding properties

Example:
	usb_phy: usbphy {
		compatible = "hisilicon,hi6220-usb-phy";
		#phy-cells = <0>;
		phy-supply = <&fixed_5v_hub>;
		hisilicon,peripheral-syscon = <&sys_ctrl>;
	};


code:
Device tree bindings for HiSilicon INNO USB2 PHY

Required properties:
- compatible: Should be one of the following strings:
	"hisilicon,inno-usb2-phy",
	"hisilicon,hi3798cv200-usb2-phy".
- reg: Should be the address space for PHY configuration register in peripheral
  controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.
- clocks: The phandle and clock specifier pair for INNO USB2 PHY device
  reference clock.
- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
  signal.
- #address-cells: Must be 1.
- #size-cells: Must be 0.

The INNO USB2 PHY device should be a child node of peripheral controller that
contains the PHY configuration register, and each device suppports up to 2 PHY
ports which are represented as child nodes of INNO USB2 PHY device.

Required properties for PHY port node:
- reg: The PHY port instance number.
- #phy-cells: Defined by generic PHY bindings.  Must be 0.
- resets: The phandle and reset specifier pair for PHY port reset signal.

Refer to phy/phy-bindings.txt for the generic PHY binding properties

Example:

perictrl: peripheral-controller@8a20000 {
	compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";
	reg = <0x8a20000 0x1000>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x0 0x8a20000 0x1000>;

	usb2_phy1: usb2-phy@120 {
		compatible = "hisilicon,hi3798cv200-usb2-phy";
		reg = <0x120 0x4>;
		clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
		resets = <&crg 0xbc 4>;
		#address-cells = <1>;
		#size-cells = <0>;

		usb2_phy1_port0: phy@0 {
			reg = <0>;
			#phy-cells = <0>;
			resets = <&crg 0xbc 8>;
		};

		usb2_phy1_port1: phy@1 {
			reg = <1>;
			#phy-cells = <0>;
			resets = <&crg 0xbc 9>;
		};
	};

	usb2_phy2: usb2-phy@124 {
		compatible = "hisilicon,hi3798cv200-usb2-phy";
		reg = <0x124 0x4>;
		clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
		resets = <&crg 0xbc 6>;
		#address-cells = <1>;
		#size-cells = <0>;

		usb2_phy2_port0: phy@0 {
			reg = <0>;
			#phy-cells = <0>;
			resets = <&crg 0xbc 10>;
		};
	};
};


code:
Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
===========================================

This binding describes the USB PHY hardware provided by the RCU module on the
Lantiq XWAY SoCs.

This node has to be a sub node of the Lantiq RCU block.

-------------------------------------------------------------------------------
Required properties (controller (parent) node):
- compatible	: Should be one of
			"lantiq,ase-usb2-phy"
			"lantiq,danube-usb2-phy"
			"lantiq,xrx100-usb2-phy"
			"lantiq,xrx200-usb2-phy"
			"lantiq,xrx300-usb2-phy"
- reg		: Defines the following sets of registers in the parent
		  syscon device
			- Offset of the USB PHY configuration register
			- Offset of the USB Analog configuration
			  register (only for xrx200 and xrx200)
- clocks	: References to the (PMU) "phy" clk gate.
- clock-names	: Must be "phy"
- resets	: References to the RCU USB configuration reset bits.
- reset-names	: Must be one of the following:
			"phy" (optional)
			"ctrl" (shared)

-------------------------------------------------------------------------------
Example for the USB PHYs on an xRX200 SoC:
	usb_phy0: usb2-phy@18 {
		compatible = "lantiq,xrx200-usb2-phy";
		reg = <0x18 4>, <0x38 4>;

		clocks = <&pmu PMU_GATE_USB0_PHY>;
		clock-names = "phy";
		resets = <&reset1 4 4>, <&reset0 4 4>;
		reset-names = "phy", "ctrl";
		#phy-cells = <0>;
	};


code:
NXP LPC18xx/43xx internal USB OTG PHY binding
---------------------------------------------

This file contains documentation for the internal USB OTG PHY found
in NXP LPC18xx and LPC43xx SoCs.

Required properties:
- compatible	: must be "nxp,lpc1850-usb-otg-phy"
- clocks	: must be exactly one entry
See: Documentation/devicetree/bindings/clock/clock-bindings.txt
- #phy-cells	: must be 0 for this phy
See: Documentation/devicetree/bindings/phy/phy-bindings.txt

The phy node must be a child of the creg syscon node.

Example:
creg: syscon@40043000 {
	compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
	reg = <0x40043000 0x1000>;

	usb0_otg_phy: phy {
		compatible = "nxp,lpc1850-usb-otg-phy";
		clocks = <&ccu1 CLK_USB0>;
		#phy-cells = <0>;
	};
};


code:
Device tree binding documentation for Motorola Mapphone MDM6600 USB PHY

Required properties:
- compatible		Must be "motorola,mapphone-mdm6600"
- enable-gpios		GPIO to enable the USB PHY
- power-gpios		GPIO to power on the device
- reset-gpios		GPIO to reset the device
- motorola,mode-gpios	Two GPIOs to configure MDM6600 USB start-up mode for
			normal mode versus USB flashing mode
- motorola,cmd-gpios	Three GPIOs to control the power state of the MDM6600
- motorola,status-gpios	Three GPIOs to read the power state of the MDM6600

Example:

usb-phy {
	compatible = "motorola,mapphone-mdm6600";
	enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
	power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
	reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
	motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
			      <&gpio5 21 GPIO_ACTIVE_HIGH>;
	motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
			     <&gpio4 8 GPIO_ACTIVE_HIGH>,
			     <&gpio5 14 GPIO_ACTIVE_HIGH>;
	motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
				<&gpio2 21 GPIO_ACTIVE_HIGH>,
				<&gpio2 23 GPIO_ACTIVE_HIGH>;
	#phy-cells = <0>;
};


code:
STMicroelectronics STi MIPHY28LP PHY binding
============================================

This binding describes a miphy device that is used to control PHY hardware
for SATA, PCIe or USB3.

Required properties (controller (parent) node):
- compatible	: Should be "st,miphy28lp-phy".
- st,syscfg	: Should be a phandle of the system configuration register group
		  which contain the SATA, PCIe or USB3 mode setting bits.

Required nodes	:  A sub-node is required for each channel the controller
		   provides. Address range information including the usual
		   'reg' and 'reg-names' properties are used inside these
		   nodes to describe the controller's topology. These nodes
		   are translated by the driver's .xlate() function.

Required properties (port (child) node):
- #phy-cells	: Should be 1 (See second example)
		  Cell after port phandle is device type from:
			- PHY_TYPE_SATA
			- PHY_TYPE_PCI
			- PHY_TYPE_USB3
- reg		: Address and length of the register set for the device.
- reg-names	: The names of the register addresses corresponding to the registers
		  filled in "reg". It can also contain the offset of the system configuration
		  registers used as glue-logic to setup the device for SATA/PCIe or USB3
		  devices.
- st,syscfg	: Offset of the parent configuration register.
- resets	: phandle to the parent reset controller.
- reset-names	: Associated name must be "miphy-sw-rst".

Optional properties (port (child) node):
- st,osc-rdy		: to check the MIPHY0_OSC_RDY status in the glue-logic. This
			  is not available in all the MiPHY. For example, for STiH407, only the
			  MiPHY0 has this bit.
- st,osc-force-ext	: to select the external oscillator. This can change from
			  different MiPHY inside the same SoC.
- st,sata_gen		: to select which SATA_SPDMODE has to be set in the SATA system config
			  register.
- st,px_rx_pol_inv	: to invert polarity of RXn/RXp (respectively negative line and positive
			  line).
- st,scc-on		: enable ssc to reduce effects of EMI (only for sata or PCIe).
- st,tx-impedance-comp	: to compensate tx impedance avoiding out of range values.

example:

		miphy28lp_phy: miphy28lp@9b22000 {
			compatible = "st,miphy28lp-phy";
			st,syscfg = <&syscfg_core>;
			#address-cells	= <1>;
			#size-cells	= <1>;
			ranges;

			phy_port0: port@9b22000 {
				reg = <0x9b22000 0xff>,
				      <0x9b09000 0xff>,
				      <0x9b04000 0xff>;
				reg-names = "sata-up",
					    "pcie-up",
					    "pipew";

				st,syscfg = <0x114 0x818 0xe0 0xec>;
				#phy-cells = <1>;
				st,osc-rdy;
				reset-names = "miphy-sw-rst";
				resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
			};

			phy_port1: port@9b2a000 {
				reg = <0x9b2a000 0xff>,
				      <0x9b19000 0xff>,
				      <0x9b14000 0xff>;
				reg-names = "sata-up",
					    "pcie-up",
					    "pipew";

				st,syscfg = <0x118 0x81c 0xe4 0xf0>;

				#phy-cells = <1>;
				st,osc-force-ext;
				reset-names = "miphy-sw-rst";
				resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
			};

			phy_port2: port@8f95000 {
				reg = <0x8f95000 0xff>,
				      <0x8f90000 0xff>;
				reg-names = "pipew",
					    "usb3-up";

				st,syscfg = <0x11c 0x820>;

				#phy-cells = <1>;
				reset-names = "miphy-sw-rst";
				resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
			};
		};

Specifying phy control of devices
=================================

Device nodes should specify the configuration required in their "phys"
property, containing a phandle to the miphy device node and an index
specifying which configuration to use, as described in phy-bindings.txt.

example:
		sata0: sata@9b20000  {
			...
			phys		= <&phy_port0 PHY_TYPE_SATA>;
			...
		};

Macro definitions for the supported miphy configuration can be found in:

include/dt-bindings/phy/phy.h


code:
STMicroelectronics STi MIPHY365x PHY binding
============================================

This binding describes a miphy device that is used to control PHY hardware
for SATA and PCIe.

Required properties (controller (parent) node):
- compatible    : Should be "st,miphy365x-phy"
- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
		  containing the miphy registers and integer array should contain
		  an entry for each port sub-node, specifying the control
		  register offset inside the sysconfig group.

Required nodes	:  A sub-node is required for each channel the controller
		   provides. Address range information including the usual
		   'reg' and 'reg-names' properties are used inside these
		   nodes to describe the controller's topology. These nodes
		   are translated by the driver's .xlate() function.

Required properties (port (child) node):
- #phy-cells 	: Should be 1 (See second example)
		  Cell after port phandle is device type from:
			- PHY_TYPE_SATA
			- PHY_TYPE_PCI
- reg        	: Address and length of register sets for each device in
		  "reg-names"
- reg-names     : The names of the register addresses corresponding to the
		  registers filled in "reg":
			- sata:   For SATA devices
			- pcie:   For PCIe devices

Optional properties (port (child) node):
- st,sata-gen	     :	Generation of locally attached SATA IP. Expected values
			are {1,2,3). If not supplied generation 1 hardware will
			be expected
- st,pcie-tx-pol-inv :	Bool property to invert the polarity PCIe Tx (Txn/Txp)
- st,sata-tx-pol-inv :	Bool property to invert the polarity SATA Tx (Txn/Txp)

Example:

	miphy365x_phy: miphy365x@fe382000 {
		compatible      = "st,miphy365x-phy";
		st,syscfg  	= <&syscfg_rear 0x824 0x828>;
		#address-cells	= <1>;
		#size-cells	= <1>;
		ranges;

		phy_port0: port@fe382000 {
			reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
			reg-names = "sata", "pcie";
			#phy-cells = <1>;
			st,sata-gen = <3>;
		};

		phy_port1: port@fe38a000 {
			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
			reg-names = "sata", "pcie", "syscfg";
			#phy-cells = <1>;
			st,pcie-tx-pol-inv;
		};
	};

Specifying phy control of devices
=================================

Device nodes should specify the configuration required in their "phys"
property, containing a phandle to the phy port node and a device type.

Example:

#include <dt-bindings/phy/phy.h>

	sata0: sata@fe380000 {
		...
		phys	  = <&phy_port0 PHY_TYPE_SATA>;
		...
	};


code:
MVEBU comphy drivers
--------------------

COMPHY controllers can be found on the following Marvell MVEBU SoCs:
* Armada 7k/8k (on the CP110)
* Armada 3700
It provides a number of shared PHYs used by various interfaces (network, SATA,
USB, PCIe...).

Required properties:

- compatible: should be one of:
  * "marvell,comphy-cp110" for Armada 7k/8k
  * "marvell,comphy-a3700" for Armada 3700
- reg: should contain the COMPHY register(s) location(s) and length(s).
  * 1 entry for Armada 7k/8k
  * 4 entries for Armada 3700 along with the corresponding reg-names
    properties, memory areas are:
    * Generic COMPHY registers
    * Lane 1 (PCIe/GbE)
    * Lane 0 (USB3/GbE)
    * Lane 2 (SATA/USB3)
- marvell,system-controller: should contain a phandle to the system
			     controller node (only for Armada 7k/8k)
- #address-cells: should be 1.
- #size-cells: should be 0.

Optional properlties:

- clocks: pointers to the reference clocks for this device (CP110 only),
          consequently: MG clock, MG Core clock, AXI clock.
- clock-names: names of used clocks for CP110 only, must be :
               "mg_clk", "mg_core_clk" and "axi_clk".

A sub-node is required for each comphy lane provided by the comphy.

Required properties (child nodes):

- reg: COMPHY lane number.
- #phy-cells : from the generic PHY bindings, must be 1. Defines the
               input port to use for a given comphy lane.

Examples:

	CP11X_LABEL(comphy): phy@120000 {
		compatible = "marvell,comphy-cp110";
		reg = <0x120000 0x6000>;
		marvell,system-controller = <&CP11X_LABEL(syscon0)>;
		clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
			 <&CP11X_LABEL(clk) 1 18>;
		clock-names = "mg_clk", "mg_core_clk", "axi_clk";
		#address-cells = <1>;
		#size-cells = <0>;

		CP11X_LABEL(comphy0): phy@0 {
			reg = <0>;
			#phy-cells = <1>;
		};

		CP11X_LABEL(comphy1): phy@1 {
			reg = <1>;
			#phy-cells = <1>;
		};
	};

	comphy: phy@18300 {
		compatible = "marvell,comphy-a3700";
		reg = <0x18300 0x300>,
		<0x1F000 0x400>,
		<0x5C000 0x400>,
		<0xe0178 0x8>;
		reg-names = "comphy",
		"lane1_pcie_gbe",
		"lane0_usb3_gbe",
		"lane2_sata_usb3";
		#address-cells = <1>;
		#size-cells = <0>;

		comphy0: phy@0 {
			reg = <0>;
			#phy-cells = <1>;
		};

		comphy1: phy@1 {
			reg = <1>;
			#phy-cells = <1>;
		};

		comphy2: phy@2 {
			reg = <2>;
			#phy-cells = <1>;
		};
	};


code:
* Marvell MVEBU SATA PHY

Power control for the SATA phy found on Marvell MVEBU SoCs.

This document extends the binding described in phy-bindings.txt

Required properties :

 - reg		   : Offset and length of the register set for the SATA device
 - compatible	   : Should be "marvell,mvebu-sata-phy"
 - clocks	   : phandle of clock and specifier that supplies the device
 - clock-names	   : Should be "sata"

Example:
		sata-phy@84000 {
			compatible = "marvell,mvebu-sata-phy";
			reg = <0x84000 0x0334>;
			clocks = <&gate_clk 15>;
			clock-names = "sata";
			#phy-cells = <0>;
		};

Armada 375 USB cluster
----------------------

Armada 375 comes with an USB2 host and device controller and an USB3
controller. The USB cluster control register allows to manage common
features of both USB controllers.

Required properties:

- compatible: "marvell,armada-375-usb-cluster"
- reg: Should contain usb cluster register location and length.
- #phy-cells : from the generic phy bindings, must be 1. Possible
values are 1 (USB2), 2 (USB3).

Example:
		usbcluster: usb-cluster@18400 {
			compatible = "marvell,armada-375-usb-cluster";
			reg = <0x18400 0x4>;
			#phy-cells = <1>
		};


code:
Marvell PXA USB PHY
-------------------

Required properties:
- compatible: one of: "marvell,mmp2-usb-phy", "marvell,pxa910-usb-phy",
	"marvell,pxa168-usb-phy",
- #phy-cells: must be 0

Example:
	usb-phy: usbphy@d4207000 {
		compatible = "marvell,mmp2-usb-phy";
		reg = <0xd4207000 0x40>;
		#phy-cells = <0>;
		status = "okay";
	};

This document explains the device tree binding. For general
information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst


code:
ROCKCHIP HDMI PHY WITH INNO IP BLOCK

Required properties:
 - compatible : should be one of the listed compatibles:
	* "rockchip,rk3228-hdmi-phy",
	* "rockchip,rk3328-hdmi-phy";
 - reg : Address and length of the hdmi phy control register set
 - clocks : phandle + clock specifier for the phy clocks
 - clock-names : string, clock name, must contain "sysclk" for system
	  control and register configuration, "refoclk" for crystal-
	  oscillator reference PLL clock input and "refpclk" for pclk-
	  based refeference PLL clock input.
 - #clock-cells: should be 0.
 - clock-output-names : shall be the name for the output clock.
 - interrupts : phandle + interrupt specified for the hdmiphy interrupt
 - #phy-cells : must be 0. See ./phy-bindings.txt for details.

Optional properties for rk3328-hdmi-phy:
 - nvmem-cells = phandle + nvmem specifier for the cpu-version efuse
 - nvmem-cell-names : "cpu-version" to read the chip version, required
	  for adjustment to some frequency settings

Example:
	hdmi_phy: hdmi-phy@12030000 {
		compatible = "rockchip,rk3228-hdmi-phy";
		reg = <0x12030000 0x10000>;
		#phy-cells = <0>;
		clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
		clock-names = "sysclk", "refoclk", "refpclk";
		#clock-cells = <0>;
		clock-output-names = "hdmi_phy";
		status = "disabled";
	};

Then the PHY can be used in other nodes such as:

	hdmi: hdmi@200a0000 {
		compatible = "rockchip,rk3228-dw-hdmi";
		...
		phys = <&hdmi_phy>;
		phy-names = "hdmi";
		...
	};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip USB2.0 phy with inno IP block

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    enum:
      - rockchip,px30-usb2phy
      - rockchip,rk3128-usb2phy
      - rockchip,rk3228-usb2phy
      - rockchip,rk3308-usb2phy
      - rockchip,rk3328-usb2phy
      - rockchip,rk3366-usb2phy
      - rockchip,rk3399-usb2phy
      - rockchip,rk3568-usb2phy
      - rockchip,rv1108-usb2phy

  reg:
    maxItems: 1

  clock-output-names:
    description:
      The usb 480m output clock name.

  "#clock-cells":
    const: 0

  clocks:
    maxItems: 1

  clock-names:
    const: phyclk

  assigned-clocks:
    description:
      Phandle of the usb 480m clock.

  assigned-clock-parents:
    description:
      Parent of the usb 480m clock.
      Select between usb-phy output 480m and xin24m.
      Refer to clk/clock-bindings.txt for generic clock consumer properties.

  extcon:
    description:
      Phandle to the extcon device providing the cable state for the otg phy.

  interrupts:
    description: Muxed interrupt for both ports
    maxItems: 1

  rockchip,usbgrf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the 'usb general register files'.
      When set the driver will request its phandle as one companion-grf
      for some special SoCs (e.g rv1108).

  host-port:
    type: object
    additionalProperties: false

    properties:
      "#phy-cells":
        const: 0

      interrupts:
        description: host linestate interrupt
        maxItems: 1

      interrupt-names:
        const: linestate

      phy-supply:
        description:
          Phandle to a regulator that provides power to VBUS.
          See ./phy-bindings.txt for details.

    required:
      - "#phy-cells"

  otg-port:
    type: object
    additionalProperties: false

    properties:
      "#phy-cells":
        const: 0

      interrupts:
        minItems: 1
        maxItems: 3

      interrupt-names:
        oneOf:
          - const: linestate
          - const: otg-mux
          - items:
              - const: otg-bvalid
              - const: otg-id
              - const: linestate

      phy-supply:
        description:
          Phandle to a regulator that provides power to VBUS.
          See ./phy-bindings.txt for details.

    required:
      - "#phy-cells"

required:
  - compatible
  - reg
  - clock-output-names
  - "#clock-cells"
  - host-port
  - otg-port

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: rockchip,rk3568-usb2phy

    then:
      properties:
        host-port:
          properties:
            interrupts: false

        otg-port:
          properties:
            interrupts: false

      required:
        - interrupts

    else:
      properties:
        interrupts: false

        host-port:
          required:
            - interrupts
            - interrupt-names

        otg-port:
          required:
            - interrupts
            - interrupt-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3399-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    u2phy0: usb2phy@e450 {
      compatible = "rockchip,rk3399-usb2phy";
      reg = <0xe450 0x10>;
      clocks = <&cru SCLK_USB2PHY0_REF>;
      clock-names = "phyclk";
      clock-output-names = "clk_usbphy0_480m";
      #clock-cells = <0>;

      u2phy0_host: host-port {
        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
        interrupt-names = "linestate";
        #phy-cells = <0>;
      };

      u2phy0_otg: otg-port {
        interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
        interrupt-names = "otg-bvalid", "otg-id", "linestate";
        #phy-cells = <0>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip SoC Naneng Combo Phy

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    enum:
      - rockchip,rk3568-naneng-combphy

  reg:
    maxItems: 1

  clocks:
    items:
      - description: reference clock
      - description: apb clock
      - description: pipe clock

  clock-names:
    items:
      - const: ref
      - const: apb
      - const: pipe

  resets:
    items:
      - description: exclusive PHY reset line

  rockchip,enable-ssc:
    type: boolean
    description:
      The option SSC can be enabled for U3, SATA and PCIE.
      Most commercially available platforms use SSC to reduce EMI.

  rockchip,ext-refclk:
    type: boolean
    description:
      Many PCIe connections, especially backplane connections,
      require a synchronous reference clock between the two link partners.
      To achieve this a common clock source, referred to as REFCLK in
      the PCI Express Card Electromechanical Specification,
      should be used by both ends of the PCIe link.
      In PCIe mode one can choose to use an internal or an external reference
      clock.
      By default the internal clock is selected. The PCIe PHY provides a 100MHz
      differential clock output(optional with SSC) for system applications.
      When selecting this option an externally 100MHz differential
      reference clock needs to be provided to the PCIe PHY.

  rockchip,pipe-grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Some additional phy settings are accessed through GRF regs.

  rockchip,pipe-phy-grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Some additional pipe settings are accessed through GRF regs.

  "#phy-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - resets
  - rockchip,pipe-grf
  - rockchip,pipe-phy-grf
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3568-cru.h>

    pipegrf: syscon@fdc50000 {
      compatible = "rockchip,rk3568-pipe-grf", "syscon";
      reg = <0xfdc50000 0x1000>;
    };

    pipe_phy_grf0: syscon@fdc70000 {
      compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
      reg = <0xfdc70000 0x1000>;
    };

    combphy0: phy@fe820000 {
      compatible = "rockchip,rk3568-naneng-combphy";
      reg = <0xfe820000 0x100>;
      clocks = <&pmucru CLK_PCIEPHY0_REF>,
               <&cru PCLK_PIPEPHY0>,
               <&cru PCLK_PIPE>;
      clock-names = "ref", "apb", "pipe";
      assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
      assigned-clock-rates = <100000000>;
      resets = <&cru SRST_PIPEPHY0>;
      rockchip,pipe-grf = <&pipegrf>;
      rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
      #phy-cells = <1>;
    };


code:
* ROCKCHIP type-c PHY
---------------------

Required properties:
 - compatible : must be "rockchip,rk3399-typec-phy"
 - reg: Address and length of the usb phy control register set
 - rockchip,grf : phandle to the syscon managing the "general
   register files"
 - clocks : phandle + clock specifier for the phy clocks
 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
		    <&cru SCLK_UPHY1_TCPDCORE>;
 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
 - resets : a list of phandle + reset specifier pairs
 - reset-names : string reset name, must be:
		 "uphy", "uphy-pipe", "uphy-tcphy"

Optional properties:
 - extcon : extcon specifier for the Power Delivery

Required nodes : a sub-node is required for each port the phy provides.
		 The sub-node name is used to identify dp or usb3 port,
		 and shall be the following entries:
	* "dp-port" : the name of DP port.
	* "usb3-port" : the name of USB3 port.

Required properties (port (child) node):
- #phy-cells : must be 0, See ./phy-bindings.txt for details.

Deprecated properties, do not use in new device tree sources, these
properties are determined by the compatible value:
 - rockchip,typec-conn-dir
 - rockchip,usb3tousb2-en
 - rockchip,external-psm
 - rockchip,pipe-status

Example:
	tcphy0: phy@ff7c0000 {
		compatible = "rockchip,rk3399-typec-phy";
		reg = <0x0 0xff7c0000 0x0 0x40000>;
		rockchip,grf = <&grf>;
		extcon = <&fusb0>;
		clocks = <&cru SCLK_UPHY0_TCPDCORE>,
			 <&cru SCLK_UPHY0_TCPDPHY_REF>;
		clock-names = "tcpdcore", "tcpdphy-ref";
		assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
		assigned-clock-rates = <50000000>;
		resets = <&cru SRST_UPHY0>,
			 <&cru SRST_UPHY0_PIPE_L00>,
			 <&cru SRST_P_UPHY0_TCPHY>;
		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";

		tcphy0_dp: dp-port {
			#phy-cells = <0>;
		};

		tcphy0_usb3: usb3-port {
			#phy-cells = <0>;
		};
	};

	tcphy1: phy@ff800000 {
		compatible = "rockchip,rk3399-typec-phy";
		reg = <0x0 0xff800000 0x0 0x40000>;
		rockchip,grf = <&grf>;
		extcon = <&fusb1>;
		clocks = <&cru SCLK_UPHY1_TCPDCORE>,
			 <&cru SCLK_UPHY1_TCPDPHY_REF>;
		clock-names = "tcpdcore", "tcpdphy-ref";
		assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
		assigned-clock-rates = <50000000>;
		resets = <&cru SRST_UPHY1>,
			 <&cru SRST_UPHY1_PIPE_L00>,
			 <&cru SRST_P_UPHY1_TCPHY>;
		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";

		tcphy1_dp: dp-port {
			#phy-cells = <0>;
		};

		tcphy1_usb3: usb3-port {
			#phy-cells = <0>;
		};
	};


code:
ST STiH407 USB PHY controller

This file documents the dt bindings for the usb picoPHY driver which is the PHY for both USB2 and USB3
host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC family from STMicroelectronics.

Required properties:
- compatible		: should be "st,stih407-usb2-phy"
- st,syscfg		: phandle of sysconfig bank plus integer array containing phyparam and phyctrl register offsets
- resets		: list of phandle and reset specifier pairs. There should be two entries, one
			  for the whole phy and one for the port
- reset-names		: list of reset signal names. Should be "global" and "port"
See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
See: Documentation/devicetree/bindings/reset/reset.txt

Example:

usb2_picophy0: usbpicophy@f8 {
	compatible	= "st,stih407-usb2-phy";
	#phy-cells	= <0>;
	st,syscfg	= <&syscfg_core 0x100 0xf4>;
	resets		= <&softreset STIH407_PICOPHY_SOFTRESET>,
			  <&picophyreset STIH407_PICOPHY0_RESET>;
	reset-names	= "global", "port";
};