code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/cirrus,madera.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cirrus Logic Madera class audio CODECs pinctrl driver

maintainers:
  - patches@opensource.cirrus.com

description: |
  The Cirrus Logic Madera codecs provide a number of GPIO functions for
  interfacing to external hardware and to provide logic outputs to other devices.
  Certain groups of GPIO pins also have an alternate function, normally as an
  audio interface.

  The set of available GPIOs, functions and alternate function groups differs
  between CODECs so refer to the datasheet for the CODEC for further information
  on what is supported on that device.

  The properties for this driver exist within the parent MFD driver node.

  See also the core bindings for the parent MFD driver:

    Documentation/devicetree/bindings/mfd/cirrus,madera.yaml

  And the generic pinmix bindings:

    Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt

properties:
  pin-settings:
    description:
      One subnode is required to contain the default settings. It
      contains an arbitrary number of configuration subnodes, one for
      each group or pin configuration you want to apply as a default.
    type: object
    patternProperties:
      '-pins$':
        type: object
        allOf:
          - $ref: "pincfg-node.yaml#"
          - $ref: "pinmux-node.yaml#"
        properties:
          groups:
            description:
              Name of one pin group to configure.
            enum: [ aif1, aif2, aif3, aif4, mif1, mif2, mif3, pdmspk1,
                    pdmspk2, dmic4, dmic5, dmic6, gpio1, gpio2, gpio3,
                    gpio4, gpio5, gpio6, gpio7, gpio8, gpio9,
                    gpio10, gpio11, gpio12, gpio13, gpio14, gpio15,
                    gpio16, gpio17, gpio18, gpio19, gpio20, gpio21,
                    gpio22, gpio23, gpio24, gpio25, gpio26, gpio27,
                    gpio28, gpio29, gpio30, gpio31, gpio32, gpio33,
                    gpio34, gpio35, gpio36, gpio37, gpio38, gpio39 ]

          function:
            description:
              Name of function to assign to this group.
            enum: [ aif1, aif2, aif3, aif4, mif1, mif2, mif3,
                    pdmspk1, pdmspk2, dmic3, dmic4, dmic5,
                    dmic6, io, dsp-gpio, irq1, irq2, fll1-clk,
                    fll1-lock, fll2-clk, fll2-lock, fll3-clk,
                    fll3-lock, fllao-clk, fllao-lock, opclk,
                    opclk-async, pwm1, pwm2, spdif, asrc1-in1-lock,
                    asrc1-in2-lock, asrc2-in1-lock, asrc2-in2-lock,
                    spkl-short-circuit, spkr-short-circuit,
                    spk-shutdown, spk-overheat-shutdown,
                    spk-overheat-warn, timer1-sts, timer2-sts,
                    timer3-sts, timer4-sts, timer5-sts, timer6-sts,
                    timer7-sts, timer8-sts, log1-fifo-ne,
                    log2-fifo-ne, log3-fifo-ne, log4-fifo-ne,
                    log5-fifo-ne, log6-fifo-ne, log7-fifo-ne,
                    log8-fifo-ne ]

          bias-disable: true

          bias-bus-hold: true

          bias-pull-up: true

          bias-pull-down: true

          drive-push-pull: true

          drive-open-drain: true

          drive-strength:
            enum: [ 4, 8 ]

          input-schmitt-enable: true

          input-schmitt-disable: true

          input-debounce: true

          output-low: true

          output-high: true

        additionalProperties: false

        required:
          - groups

    additionalProperties: false

required:
  - pinctrl-0
  - pinctrl-names

additionalProperties: true


code:
Conexant Digicolor CX92755 General Purpose Pin Mapping

This document describes the device tree binding of the pin mapping hardware
modules in the Conexant Digicolor CX92755 SoCs. The CX92755 in one of the
Digicolor series of SoCs.

=== Pin Controller Node ===

Required Properties:

- compatible: Must be "cnxt,cx92755-pinctrl"
- reg: Base address of the General Purpose Pin Mapping register block and the
  size of the block.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Must be <2>. The first cell is the pin number and the
  second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
  for possible values.

For example, the following is the bare minimum node:

	pinctrl: pinctrl@f0000e20 {
		compatible = "cnxt,cx92755-pinctrl";
		reg = <0xf0000e20 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
	};

As a pin controller device, in addition to the required properties, this node
should also contain the pin configuration nodes that client devices reference,
if any.

For a general description of GPIO bindings, please refer to ../gpio/gpio.txt.

=== Pin Configuration Node ===

Each pin configuration node is a sub-node of the pin controller node and is a
container of an arbitrary number of subnodes, called pin group nodes in this
document.

Please refer to the pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the definition of a
"pin configuration node".

=== Pin Group Node ===

A pin group node specifies the desired pin mux for an arbitrary number of
pins. The name of the pin group node is optional and not used.

A pin group node only affects the properties specified in the node, and has no
effect on any properties that are omitted.

The pin group node accepts a subset of the generic pin config properties. For
details generic pin config properties, please refer to pinctrl-bindings.txt
and <include/linux/pinctrl/pinconfig-generic.h>.

Required Pin Group Node Properties:

- pins: Multiple strings. Specifies the name(s) of one or more pins to be
  configured by this node. The format of a pin name string is "GP_xy", where x
  is an uppercase character from 'A' to 'R', and y is a digit from 0 to 7.
- function: String. Specifies the pin mux selection. Values must be one of:
  "gpio", "client_a", "client_b", "client_c"

Example:
	pinctrl: pinctrl@f0000e20 {
		compatible = "cnxt,cx92755-pinctrl";
		reg = <0xf0000e20 0x100>;

		uart0_default: uart0_active {
			data_signals {
				pins = "GP_O0", "GP_O1";
				function = "client_b";
			};
		};
	};

	uart0: uart@f0000740 {
		compatible = "cnxt,cx92755-usart";
		...
		pinctrl-0 = <&uart0_default>;
		pinctrl-names = "default";
	};

In the example above, a single pin group configuration node defines the
"client select" for the Rx and Tx signals of uart0. The uart0 node references
that pin configuration node using the &uart0_default phandle.

repo_name: angery/linux


code:
Cortina Systems Gemini pin controller

This pin controller is found in the Cortina Systems Gemini SoC family,
see further arm/gemini.txt. It is a purely group-based multiplexing pin
controller.

The pin controller node must be a subnode of the system controller node.

Required properties:
- compatible: "cortina,gemini-pinctrl"

Subnodes of the pin controller contain pin control multiplexing set-up
and pin configuration of individual pins.

Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
and generic pin config nodes.

Supported configurations:
- skew-delay is supported on the Ethernet pins
- drive-strength with 4, 8, 12 or 16 mA as argument is supported for
  entire groups on the groups "idegrp", "gmii_gmac0_grp", "gmii_gmac1_grp"
  and "pcigrp".

Example:

syscon {
	compatible = "cortina,gemini-syscon";
	...
	pinctrl {
		compatible = "cortina,gemini-pinctrl";
		pinctrl-names = "default";
		pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
		    <&vcontrol_default_pins>;

		dram_default_pins: pinctrl-dram {
			mux {
				function = "dram";
				groups = "dramgrp";
			};
		};
		rtc_default_pins: pinctrl-rtc {
			mux {
				function = "rtc";
				groups = "rtcgrp";
			};
		};
		power_default_pins: pinctrl-power {
			mux {
				function = "power";
				groups = "powergrp";
			};
		};
		system_default_pins: pinctrl-system {
			mux {
				function = "system";
				groups = "systemgrp";
			};
		};
		(...)
		uart_default_pins: pinctrl-uart {
			mux {
				function = "uart";
				groups = "uartrxtxgrp";
			};
		};
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/cypress,cy8c95x0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cypress CY8C95X0 I2C GPIO expander

maintainers:
  - Patrick Rudolph <patrick.rudolph@9elements.com>

description: |
  This supports the 20/40/60 pin Cypress CYC95x0 GPIO I2C expanders.
  Pin function configuration is performed on a per-pin basis.

properties:
  compatible:
    enum:
      - cypress,cy8c9520
      - cypress,cy8c9540
      - cypress,cy8c9560

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    description:
      The first cell is the GPIO number and the second cell specifies GPIO
      flags, as defined in <dt-bindings/gpio/gpio.h>.
    const: 2

  interrupts:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

  gpio-line-names: true

  gpio-ranges:
    maxItems: 1

  gpio-reserved-ranges:
    maxItems: 1

  vdd-supply:
    description:
      Optional power supply.

patternProperties:
  '-pins$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: pincfg-node.yaml#

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          pattern: '^gp([0-7][0-7])$'
        minItems: 1
        maxItems: 60

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.
        enum: [ gpio, pwm ]

      bias-pull-down: true

      bias-pull-up: true

      bias-disable: true

      output-high: true

      output-low: true

      drive-push-pull: true

      drive-open-drain: true

      drive-open-source: true

    required:
      - pins
      - function

    additionalProperties: false

required:
  - compatible
  - reg
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'
  - gpio-controller
  - '#gpio-cells'

additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      pinctrl@20 {
        compatible = "cypress,cy8c9520";
        reg = <0x20>;
        gpio-controller;
        #gpio-cells = <2>;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        vdd-supply = <&p3v3>;
        gpio-reserved-ranges = <5 1>;
      };
    };


code:
* Freescale IOMUX Controller (IOMUXC) for i.MX

The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to
8 muxing options (called ALT modes). Since different modules require
different PAD settings (like pull up, keeper, etc) the IOMUXC controls
also the PAD settings parameters.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

Freescale IMX pin configuration node is a node of a group of pins which can be
used for a specific device or function. This node represents both mux and config
of the pins in that group. The 'mux' selects the function mode(also named mux
mode) this pin can work on and the 'config' configures various pad settings
such as pull-up, open drain, drive strength, etc.

Required properties for iomux controller:
- compatible: "fsl,<soc>-iomuxc"
  Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.

Required properties for pin configuration node:
- fsl,pins: each entry consists of 6 integers and represents the mux and config
  setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
  input_val> are specified using a PIN_FUNC_ID macro, which can be found in
  imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
  the pad setting value like pull-up on this pin. And that's why fsl,pins entry
  looks like <PIN_FUNC_ID CONFIG> in the example below.

Bits used for CONFIG:
NO_PAD_CTL(1 << 31): indicate this pin does not need config.

SION(1 << 30): Software Input On Field.
Force the selected mux mode input path no matter of MUX_MODE functionality.
By default the input path is determined by functionality of the selected
mux mode (regular).

Other bits are used for PAD setting.
Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
of bits definitions.

NOTE:
Some requirements for using fsl,imx-pinctrl binding:
1. We have pin function node defined under iomux controller node to represent
   what pinmux functions this SoC supports.
2. The pin configuration node intends to work on a specific function should
   to be defined under that specific function node.
   The function node's name should represent well about what function
   this group of pins in this pin configuration node are working on.
3. The driver can use the function node's name and pin configuration node's
   name describe the pin function and group hierarchy.
   For example, Linux IMX pinctrl driver takes the function node's name
   as the function name and pin configuration node's name as group name to
   create the map table.
4. Each pin configuration node should have a phandle, devices can set pins
   configurations by referring to the phandle of that pin configuration node.

Examples:
usdhc@219c000 { /* uSDHC4 */
	non-removable;
	vmmc-supply = <&reg_3p3v>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4_1>;
};

iomuxc@20e0000 {
	compatible = "fsl,imx6q-iomuxc";
	reg = <0x020e0000 0x4000>;

	/* shared pinctrl settings */
	usdhc4 {
		pinctrl_usdhc4_1: usdhc4grp-1 {
			fsl,pins = <
				MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
				MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
				MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
				MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
				MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
				MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
				MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
				MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
				MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
				MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
			>;
	};
	....
};
Refer to the IOMUXC controller chapter in imx6q datasheet,
0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
80Ohm driver strength and Fast Slew Rate.
User should refer to each SoC spec to set the correct value.


code:
* Freescale IMX25 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

CONFIG bits definition:
PAD_CTL_HYS			(1 << 8)
PAD_CTL_PKE			(1 << 7)
PAD_CTL_PUE			(1 << 6)
PAD_CTL_PUS_100K_DOWN		(0 << 4)
PAD_CTL_PUS_47K_UP		(1 << 4)
PAD_CTL_PUS_100K_UP		(2 << 4)
PAD_CTL_PUS_22K_UP		(3 << 4)
PAD_CTL_ODE_CMOS		(0 << 3)
PAD_CTL_ODE_OPENDRAIN		(1 << 3)
PAD_CTL_DSE_NOMINAL		(0 << 1)
PAD_CTL_DSE_HIGH		(1 << 1)
PAD_CTL_DSE_MAX			(2 << 1)
PAD_CTL_SRE_FAST		(1 << 0)
PAD_CTL_SRE_SLOW		(0 << 0)

Refer to imx25-pinfunc.h in device tree source folder for all available
imx25 PIN_FUNC_ID.


code:
* Freescale IMX27 IOMUX Controller

Required properties:
- compatible: "fsl,imx27-iomuxc"

The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.

Required properties for pin configuration node:
- fsl,pins: three integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.

  PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
  configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
  number on the specific port (between 0 and 31).

  MUX_ID is
    function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)

      function value is used to select the pin function.
      Possible values:
          0 - Primary function
          1 - Alternate function
          2 - GPIO
      Registers: GIUS (GPIO In Use), GPR (General Purpose Register)

      direction defines the data direction of the pin.
      Possible values:
          0 - Input
          1 - Output
      Register: DDIR

      gpio_oconf configures the gpio submodule output signal. This does not
      have any effect unless GPIO function is selected. A/B/C_IN are output
      signals of function blocks A,B and C. Specific function blocks are
      described in the reference manual.
      Possible values:
          0 - A_IN
          1 - B_IN
          2 - C_IN
          3 - Data Register
      Registers: OCR1, OCR2

      gpio_iconfa/b configures the gpio submodule input to functionblocks A and
      B. GPIO function should be selected if this is configured.
      Possible values:
          0 - GPIO_IN
          1 - Interrupt Status Register
          2 - Pulldown
          3 - Pullup
      Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2

  CONFIG can be 0 or 1, meaning Pullup disable/enable.

The iomux controller has gpio child nodes which are embedded in the iomux
control registers. They have to be defined as child nodes of the iomux device
node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"
properties for the iomux device node are required.

Example:

iomuxc: iomuxc@10015000 {
	compatible = "fsl,imx27-iomuxc";
	reg = <0x10015000 0x600>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gpio1: gpio@10015000 {
		...
	};

	...

	uart {
		pinctrl_uart1: uart-1 {
			fsl,pins = <
				0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
				0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
				0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
				0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
			>;
		};

		...
	};
};

For convenience there are macros defined in imx27-pinfunc.h which provide PIN
and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
are defined in the i.MX27 reference manual.

The above example using macros:

iomuxc: iomuxc@10015000 {
	compatible = "fsl,imx27-iomuxc";
	reg = <0x10015000 0x600>;
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	gpio1: gpio@10015000 {
		...
	};

	...

	uart {
		pinctrl_uart1: uart-1 {
			fsl,pins = <
				MX27_PAD_UART1_TXD__UART1_TXD 0x0
				MX27_PAD_UART1_RXD__UART1_RXD 0x0
				MX27_PAD_UART1_CTS__UART1_CTS 0x0
				MX27_PAD_UART1_RTS__UART1_RTS 0x0
			>;
		};

		...
	};
};


code:
* Freescale IMX35 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx35-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
  pin working on a specific function, CONFIG is the pad setting value like
  pull-up for this pin. Please refer to imx35 datasheet for the valid pad
  config settings.

CONFIG bits definition:
PAD_CTL_DRIVE_VOLAGAGE_18	(1 << 13)
PAD_CTL_DRIVE_VOLAGAGE_33	(0 << 13)
PAD_CTL_HYS			(1 << 8)
PAD_CTL_PKE			(1 << 7)
PAD_CTL_PUE			(1 << 6)
PAD_CTL_PUS_100K_DOWN		(0 << 4)
PAD_CTL_PUS_47K_UP		(1 << 4)
PAD_CTL_PUS_100K_UP		(2 << 4)
PAD_CTL_PUS_22K_UP		(3 << 4)
PAD_CTL_ODE_CMOS		(0 << 3)
PAD_CTL_ODE_OPENDRAIN		(1 << 3)
PAD_CTL_DSE_NOMINAL		(0 << 1)
PAD_CTL_DSE_HIGH		(1 << 1)
PAD_CTL_DSE_MAX			(2 << 1)
PAD_CTL_SRE_FAST		(1 << 0)
PAD_CTL_SRE_SLOW		(0 << 0)

Refer to imx35-pinfunc.h in device tree source folder for all available
imx35 PIN_FUNC_ID.


code:
* Freescale IMX50 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx50-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
  pin working on a specific function, CONFIG is the pad setting value like
  pull-up for this pin. Please refer to imx50 datasheet for the valid pad
  config settings.

CONFIG bits definition:
PAD_CTL_HVE			(1 << 13)
PAD_CTL_HYS			(1 << 8)
PAD_CTL_PKE			(1 << 7)
PAD_CTL_PUE			(1 << 6)
PAD_CTL_PUS_100K_DOWN		(0 << 4)
PAD_CTL_PUS_47K_UP		(1 << 4)
PAD_CTL_PUS_100K_UP		(2 << 4)
PAD_CTL_PUS_22K_UP		(3 << 4)
PAD_CTL_ODE			(1 << 3)
PAD_CTL_DSE_LOW			(0 << 1)
PAD_CTL_DSE_MED			(1 << 1)
PAD_CTL_DSE_HIGH		(2 << 1)
PAD_CTL_DSE_MAX			(3 << 1)
PAD_CTL_SRE_FAST		(1 << 0)
PAD_CTL_SRE_SLOW		(0 << 0)

Refer to imx50-pinfunc.h in device tree source folder for all available
imx50 PIN_FUNC_ID.


code:
* Freescale IMX51 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx51-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
  pin working on a specific function, CONFIG is the pad setting value like
  pull-up for this pin. Please refer to imx51 datasheet for the valid pad
  config settings.

CONFIG bits definition:
PAD_CTL_HVE			(1 << 13)
PAD_CTL_HYS			(1 << 8)
PAD_CTL_PKE			(1 << 7)
PAD_CTL_PUE			(1 << 6)
PAD_CTL_PUS_100K_DOWN		(0 << 4)
PAD_CTL_PUS_47K_UP		(1 << 4)
PAD_CTL_PUS_100K_UP		(2 << 4)
PAD_CTL_PUS_22K_UP		(3 << 4)
PAD_CTL_ODE			(1 << 3)
PAD_CTL_DSE_LOW			(0 << 1)
PAD_CTL_DSE_MED			(1 << 1)
PAD_CTL_DSE_HIGH		(2 << 1)
PAD_CTL_DSE_MAX			(3 << 1)
PAD_CTL_SRE_FAST		(1 << 0)
PAD_CTL_SRE_SLOW		(0 << 0)

Refer to imx51-pinfunc.h in device tree source folder for all available
imx51 PIN_FUNC_ID.


code:
* Freescale IMX53 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx53-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
  pin working on a specific function, CONFIG is the pad setting value like
  pull-up for this pin. Please refer to imx53 datasheet for the valid pad
  config settings.

CONFIG bits definition:
PAD_CTL_HVE			(1 << 13)
PAD_CTL_HYS			(1 << 8)
PAD_CTL_PKE			(1 << 7)
PAD_CTL_PUE			(1 << 6)
PAD_CTL_PUS_100K_DOWN		(0 << 4)
PAD_CTL_PUS_47K_UP		(1 << 4)
PAD_CTL_PUS_100K_UP		(2 << 4)
PAD_CTL_PUS_22K_UP		(3 << 4)
PAD_CTL_ODE			(1 << 3)
PAD_CTL_DSE_LOW			(0 << 1)
PAD_CTL_DSE_MED			(1 << 1)
PAD_CTL_DSE_HIGH		(2 << 1)
PAD_CTL_DSE_MAX			(3 << 1)
PAD_CTL_SRE_FAST		(1 << 0)
PAD_CTL_SRE_SLOW		(0 << 0)

Refer to imx53-pinfunc.h in device tree source folder for all available
imx53 PIN_FUNC_ID.


code:
* Freescale IMX6 DualLite/Solo IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx6dl-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
  pin working on a specific function, CONFIG is the pad setting value like
  pull-up for this pin. Please refer to imx6dl datasheet for the valid pad
  config settings.

CONFIG bits definition:
PAD_CTL_HYS                     (1 << 16)
PAD_CTL_PUS_100K_DOWN           (0 << 14)
PAD_CTL_PUS_47K_UP              (1 << 14)
PAD_CTL_PUS_100K_UP             (2 << 14)
PAD_CTL_PUS_22K_UP              (3 << 14)
PAD_CTL_PUE                     (1 << 13)
PAD_CTL_PKE                     (1 << 12)
PAD_CTL_ODE                     (1 << 11)
PAD_CTL_SPEED_LOW               (1 << 6)
PAD_CTL_SPEED_MED               (2 << 6)
PAD_CTL_SPEED_HIGH              (3 << 6)
PAD_CTL_DSE_DISABLE             (0 << 3)
PAD_CTL_DSE_240ohm              (1 << 3)
PAD_CTL_DSE_120ohm              (2 << 3)
PAD_CTL_DSE_80ohm               (3 << 3)
PAD_CTL_DSE_60ohm               (4 << 3)
PAD_CTL_DSE_48ohm               (5 << 3)
PAD_CTL_DSE_40ohm               (6 << 3)
PAD_CTL_DSE_34ohm               (7 << 3)
PAD_CTL_SRE_FAST                (1 << 0)
PAD_CTL_SRE_SLOW                (0 << 0)

Refer to imx6dl-pinfunc.h in device tree source folder for all available
imx6dl PIN_FUNC_ID.


code:
* Freescale IMX6Q IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx6q-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
  pin working on a specific function, CONFIG is the pad setting value like
  pull-up for this pin. Please refer to imx6q datasheet for the valid pad
  config settings.

CONFIG bits definition:
PAD_CTL_HYS                     (1 << 16)
PAD_CTL_PUS_100K_DOWN           (0 << 14)
PAD_CTL_PUS_47K_UP              (1 << 14)
PAD_CTL_PUS_100K_UP             (2 << 14)
PAD_CTL_PUS_22K_UP              (3 << 14)
PAD_CTL_PUE                     (1 << 13)
PAD_CTL_PKE                     (1 << 12)
PAD_CTL_ODE                     (1 << 11)
PAD_CTL_SPEED_LOW               (1 << 6)
PAD_CTL_SPEED_MED               (2 << 6)
PAD_CTL_SPEED_HIGH              (3 << 6)
PAD_CTL_DSE_DISABLE             (0 << 3)
PAD_CTL_DSE_240ohm              (1 << 3)
PAD_CTL_DSE_120ohm              (2 << 3)
PAD_CTL_DSE_80ohm               (3 << 3)
PAD_CTL_DSE_60ohm               (4 << 3)
PAD_CTL_DSE_48ohm               (5 << 3)
PAD_CTL_DSE_40ohm               (6 << 3)
PAD_CTL_DSE_34ohm               (7 << 3)
PAD_CTL_SRE_FAST                (1 << 0)
PAD_CTL_SRE_SLOW                (0 << 0)

Refer to imx6q-pinfunc.h in device tree source folder for all available
imx6q PIN_FUNC_ID.


code:
* Freescale IMX6 SoloLite IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx6sl-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
  pin working on a specific function, CONFIG is the pad setting value like
  pull-up for this pin. Please refer to imx6sl datasheet for the valid pad
  config settings.

CONFIG bits definition:
PAD_CTL_LVE                     (1 << 22)
PAD_CTL_HYS                     (1 << 16)
PAD_CTL_PUS_100K_DOWN           (0 << 14)
PAD_CTL_PUS_47K_UP              (1 << 14)
PAD_CTL_PUS_100K_UP             (2 << 14)
PAD_CTL_PUS_22K_UP              (3 << 14)
PAD_CTL_PUE                     (1 << 13)
PAD_CTL_PKE                     (1 << 12)
PAD_CTL_ODE                     (1 << 11)
PAD_CTL_SPEED_LOW               (1 << 6)
PAD_CTL_SPEED_MED               (2 << 6)
PAD_CTL_SPEED_HIGH              (3 << 6)
PAD_CTL_DSE_DISABLE             (0 << 3)
PAD_CTL_DSE_240ohm              (1 << 3)
PAD_CTL_DSE_120ohm              (2 << 3)
PAD_CTL_DSE_80ohm               (3 << 3)
PAD_CTL_DSE_60ohm               (4 << 3)
PAD_CTL_DSE_48ohm               (5 << 3)
PAD_CTL_DSE_40ohm               (6 << 3)
PAD_CTL_DSE_34ohm               (7 << 3)
PAD_CTL_SRE_FAST                (1 << 0)
PAD_CTL_SRE_SLOW                (0 << 0)

Refer to imx6sl-pinfunc.h in device tree source folder for all available
imx6sl PIN_FUNC_ID.


code:
* Freescale i.MX6 SLL IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx6sll-iomuxc"
- fsl,pins: each entry consists of 6 integers and represents the mux and config
  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val
  input_val> are specified using a PIN_FUNC_ID macro, which can be found in
  imx6sll-pinfunc.h under device tree source folder.  The last integer CONFIG is
  the pad setting value like pull-up on this pin.  Please refer to i.MX6SLL
  Reference Manual for detailed CONFIG settings.

CONFIG bits definition:
PAD_CTL_LVE			(1 << 22)
PAD_CTL_HYS                     (1 << 16)
PAD_CTL_PUS_100K_DOWN           (0 << 14)
PAD_CTL_PUS_47K_UP              (1 << 14)
PAD_CTL_PUS_100K_UP             (2 << 14)
PAD_CTL_PUS_22K_UP              (3 << 14)
PAD_CTL_PUE                     (1 << 13)
PAD_CTL_PKE                     (1 << 12)
PAD_CTL_ODE                     (1 << 11)
PAD_CTL_SPEED_LOW               (0 << 6)
PAD_CTL_SPEED_MED               (1 << 6)
PAD_CTL_SPEED_HIGH              (3 << 6)
PAD_CTL_DSE_DISABLE             (0 << 3)
PAD_CTL_DSE_260ohm              (1 << 3)
PAD_CTL_DSE_130ohm              (2 << 3)
PAD_CTL_DSE_87ohm               (3 << 3)
PAD_CTL_DSE_65ohm               (4 << 3)
PAD_CTL_DSE_52ohm               (5 << 3)
PAD_CTL_DSE_43ohm               (6 << 3)
PAD_CTL_DSE_37ohm               (7 << 3)
PAD_CTL_SRE_FAST                (1 << 0)
PAD_CTL_SRE_SLOW                (0 << 0)

Refer to imx6sll-pinfunc.h in device tree source folder for all available
imx6sll PIN_FUNC_ID.


code:
* Freescale i.MX6 SoloX IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx6sx-iomuxc"
- fsl,pins: each entry consists of 6 integers and represents the mux and config
  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val
  input_val> are specified using a PIN_FUNC_ID macro, which can be found in
  imx6sx-pinfunc.h under device tree source folder.  The last integer CONFIG is
  the pad setting value like pull-up on this pin.  Please refer to i.MX6 SoloX
  Reference Manual for detailed CONFIG settings.

CONFIG bits definition:
PAD_CTL_HYS                     (1 << 16)
PAD_CTL_PUS_100K_DOWN           (0 << 14)
PAD_CTL_PUS_47K_UP              (1 << 14)
PAD_CTL_PUS_100K_UP             (2 << 14)
PAD_CTL_PUS_22K_UP              (3 << 14)
PAD_CTL_PUE                     (1 << 13)
PAD_CTL_PKE                     (1 << 12)
PAD_CTL_ODE                     (1 << 11)
PAD_CTL_SPEED_LOW               (0 << 6)
PAD_CTL_SPEED_MED               (1 << 6)
PAD_CTL_SPEED_HIGH              (3 << 6)
PAD_CTL_DSE_DISABLE             (0 << 3)
PAD_CTL_DSE_260ohm              (1 << 3)
PAD_CTL_DSE_130ohm              (2 << 3)
PAD_CTL_DSE_87ohm               (3 << 3)
PAD_CTL_DSE_65ohm               (4 << 3)
PAD_CTL_DSE_52ohm               (5 << 3)
PAD_CTL_DSE_43ohm               (6 << 3)
PAD_CTL_DSE_37ohm               (7 << 3)
PAD_CTL_SRE_FAST                (1 << 0)
PAD_CTL_SRE_SLOW                (0 << 0)


code:
* Freescale i.MX6 UltraLite IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
  "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
- fsl,pins: each entry consists of 6 integers and represents the mux and config
  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val
  input_val> are specified using a PIN_FUNC_ID macro, which can be found in
  imx6ul-pinfunc.h under device tree source folder.  The last integer CONFIG is
  the pad setting value like pull-up on this pin.  Please refer to i.MX6 UltraLite
  Reference Manual for detailed CONFIG settings.

CONFIG bits definition:
PAD_CTL_HYS                     (1 << 16)
PAD_CTL_PUS_100K_DOWN           (0 << 14)
PAD_CTL_PUS_47K_UP              (1 << 14)
PAD_CTL_PUS_100K_UP             (2 << 14)
PAD_CTL_PUS_22K_UP              (3 << 14)
PAD_CTL_PUE                     (1 << 13)
PAD_CTL_PKE                     (1 << 12)
PAD_CTL_ODE                     (1 << 11)
PAD_CTL_SPEED_LOW               (0 << 6)
PAD_CTL_SPEED_MED               (1 << 6)
PAD_CTL_SPEED_HIGH              (3 << 6)
PAD_CTL_DSE_DISABLE             (0 << 3)
PAD_CTL_DSE_260ohm              (1 << 3)
PAD_CTL_DSE_130ohm              (2 << 3)
PAD_CTL_DSE_87ohm               (3 << 3)
PAD_CTL_DSE_65ohm               (4 << 3)
PAD_CTL_DSE_52ohm               (5 << 3)
PAD_CTL_DSE_43ohm               (6 << 3)
PAD_CTL_DSE_37ohm               (7 << 3)
PAD_CTL_SRE_FAST                (1 << 0)
PAD_CTL_SRE_SLOW                (0 << 0)


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx7d-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale IMX7D IOMUX Controller

maintainers:
  - Dong Aisheng <aisheng.dong@nxp.com>

description:
  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
  for common binding part and usage.

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,imx7d-iomuxc
          - fsl,imx7d-iomuxc-lpsr

  reg:
    maxItems: 1

  fsl,input-sel:
    description:
      phandle for main iomuxc controller which shares the input select
      register for daisy chain settings.
    $ref: /schemas/types.yaml#/definitions/phandle

# Client device subnode's properties
patternProperties:
  'grp$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.

    properties:
      fsl,pins:
        description:
          each entry consists of 6 integers and represents the mux and config
          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
          be found in <arch/arm/boot/dts/imx7d-pinfunc.h>. The last integer
          CONFIG is the pad setting value like pull-up on this pin. Please
          refer to i.MX7D Reference Manual for detailed CONFIG settings.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
            - description: |
                "mux_reg" indicates the offset of mux register.
            - description: |
                "conf_reg" indicates the offset of pad configuration register.
            - description: |
                "input_reg" indicates the offset of select input register.
            - description: |
                "mux_val" indicates the mux value to be applied.
            - description: |
                "input_val" indicates the select input value to be applied.
            - description: |
                "pad_setting" indicates the pad configuration value to be applied.

    required:
      - fsl,pins

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

if:
  properties:
    compatible:
      contains:
        enum:
          - fsl,imx7d-iomuxc-lpsr

then:
  required:
    - fsl,input-sel

additionalProperties: false

examples:
  - |
    iomuxc: pinctrl@30330000 {
      compatible = "fsl,imx7d-iomuxc";
      reg = <0x30330000 0x10000>;

      pinctrl_uart5: uart5grp {
        fsl,pins =
          <0x0160 0x03D0 0x0714 0x1 0x0	0x7e>,
          <0x0164 0x03D4 0x0000 0x1 0x0	0x76>;
      };
    };
  - |
    iomuxc_lpsr: pinctrl@302c0000 {
      compatible = "fsl,imx7d-iomuxc-lpsr";
      reg = <0x302c0000 0x10000>;
      fsl,input-sel = <&iomuxc>;

      pinctrl_gpio_lpsr: gpio1-grp {
          fsl,pins =
            <0x0008 0x0038 0x0000 0x0 0x0	0x59>,
            <0x000C 0x003C 0x0000 0x0 0x0	0x59>;
        };
    };


code:
* Freescale i.MX7ULP IOMUX Controller

i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
ports and IOMUXC DDR for DDR interface.

Note:
This binding doc is only for the IOMUXC1 support in A7 Domain and it only
supports generic pin config.

Please refer to fsl,imx-pinctrl.txt in this directory for common binding
part and usage.

Required properties:
- compatible:	"fsl,imx7ulp-iomuxc1".
- fsl,pins:	Each entry consists of 5 integers which represents the mux
		and config setting for one pin. The first 4 integers
		<mux_conf_reg input_reg mux_mode input_val> are specified
		using a PIN_FUNC_ID macro, which can be found in
		imx7ulp-pinfunc.h in the device tree source folder.
		The last integer CONFIG is the pad setting value like
		pull-up on this pin.

		Please refer to i.MX7ULP Reference Manual for detailed
		CONFIG settings.

CONFIG bits definition:
PAD_CTL_OBE		(1 << 17)
PAD_CTL_IBE		(1 << 16)
PAD_CTL_LK		(1 << 16)
PAD_CTL_DSE_HI		(1 << 6)
PAD_CTL_DSE_STD		(0 << 6)
PAD_CTL_ODE		(1 << 5)
PAD_CTL_PUSH_PULL	(0 << 5)
PAD_CTL_SRE_SLOW	(1 << 2)
PAD_CTL_SRE_STD		(0 << 2)
PAD_CTL_PE		(1 << 0)

Examples:
#include "imx7ulp-pinfunc.h"

/* Pin Controller Node */
iomuxc1: pinctrl@40ac0000 {
	compatible = "fsl,imx7ulp-iomuxc1";
	reg = <0x40ac0000 0x1000>;

	/* Pin Configuration Node */
	pinctrl_lpuart4: lpuart4grp {
		fsl,pins = <
			IMX7ULP_PAD_PTC3__LPUART4_RX	0x1
			IMX7ULP_PAD_PTC2__LPUART4_TX	0x1
		>;
	};
};


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mm-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale IMX8MM IOMUX Controller

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

description:
  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
  for common binding part and usage.

properties:
  compatible:
    const: fsl,imx8mm-iomuxc

  reg:
    maxItems: 1

# Client device subnode's properties
patternProperties:
  'grp$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.

    properties:
      fsl,pins:
        description:
          each entry consists of 6 integers and represents the mux and config
          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
          be found in <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last
          integer CONFIG is the pad setting value like pull-up on this pin. Please
          refer to i.MX8M Mini Reference Manual for detailed CONFIG settings.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
            - description: |
                "mux_reg" indicates the offset of mux register.
            - description: |
                "conf_reg" indicates the offset of pad configuration register.
            - description: |
                "input_reg" indicates the offset of select input register.
            - description: |
                "mux_val" indicates the mux value to be applied.
            - description: |
                "input_val" indicates the select input value to be applied.
            - description: |
                "pad_setting" indicates the pad configuration value to be applied.

    required:
      - fsl,pins

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    iomuxc: pinctrl@30330000 {
        compatible = "fsl,imx8mm-iomuxc";
        reg = <0x30330000 0x10000>;

        pinctrl_uart2: uart2grp {
            fsl,pins =
                <0x23C 0x4A4 0x4FC 0x0 0x0	0x140>,
                <0x240 0x4A8 0x000 0x0 0x0	0x140>;
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale IMX8MN IOMUX Controller

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

description:
  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
  for common binding part and usage.

properties:
  compatible:
    const: fsl,imx8mn-iomuxc

  reg:
    maxItems: 1

# Client device subnode's properties
patternProperties:
  'grp$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.

    properties:
      fsl,pins:
        description:
          each entry consists of 6 integers and represents the mux and config
          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
          be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last
          integer CONFIG is the pad setting value like pull-up on this pin. Please
          refer to i.MX8M Nano Reference Manual for detailed CONFIG settings.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
            - description: |
                "mux_reg" indicates the offset of mux register.
            - description: |
                "conf_reg" indicates the offset of pad configuration register.
            - description: |
                "input_reg" indicates the offset of select input register.
            - description: |
                "mux_val" indicates the mux value to be applied.
            - description: |
                "input_val" indicates the select input value to be applied.
            - description: |
                "pad_setting" indicates the pad configuration value to be applied.

    required:
      - fsl,pins

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    iomuxc: pinctrl@30330000 {
        compatible = "fsl,imx8mn-iomuxc";
        reg = <0x30330000 0x10000>;

        pinctrl_uart2: uart2grp {
            fsl,pins =
                <0x23C 0x4A4 0x4FC 0x0 0x0	0x140>,
                <0x240 0x4A8 0x000 0x0 0x0	0x140>;
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale IMX8MP IOMUX Controller

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

description:
  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
  for common binding part and usage.

properties:
  compatible:
    const: fsl,imx8mp-iomuxc

  reg:
    maxItems: 1

# Client device subnode's properties
patternProperties:
  'grp$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.

    properties:
      fsl,pins:
        description:
          each entry consists of 6 integers and represents the mux and config
          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
          be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
          integer CONFIG is the pad setting value like pull-up on this pin. Please
          refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
            - description: |
                "mux_reg" indicates the offset of mux register.
            - description: |
                "conf_reg" indicates the offset of pad configuration register.
            - description: |
                "input_reg" indicates the offset of select input register.
            - description: |
                "mux_val" indicates the mux value to be applied.
            - description: |
                "input_val" indicates the select input value to be applied.
            - description: |
                "pad_setting" indicates the pad configuration value to be applied.

    required:
      - fsl,pins

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    iomuxc: pinctrl@30330000 {
        compatible = "fsl,imx8mp-iomuxc";
        reg = <0x30330000 0x10000>;

        pinctrl_uart2: uart2grp {
            fsl,pins =
                <0x228 0x488 0x5F0 0x0 0x6	0x49>,
                <0x228 0x488 0x000 0x0 0x0	0x49>;
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mq-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale IMX8MQ IOMUX Controller

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

description:
  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
  for common binding part and usage.

properties:
  compatible:
    const: fsl,imx8mq-iomuxc

  reg:
    maxItems: 1

# Client device subnode's properties
patternProperties:
  'grp$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.

    properties:
      fsl,pins:
        description:
          each entry consists of 6 integers and represents the mux and config
          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
          be found in <arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h>. The last
          integer CONFIG is the pad setting value like pull-up on this pin. Please
          refer to i.MX8M Quad Reference Manual for detailed CONFIG settings.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
            - description: |
                "mux_reg" indicates the offset of mux register.
            - description: |
                "conf_reg" indicates the offset of pad configuration register.
            - description: |
                "input_reg" indicates the offset of select input register.
            - description: |
                "mux_val" indicates the mux value to be applied.
            - description: |
                "input_val" indicates the select input value to be applied.
            - description: |
                "pad_setting" indicates the pad configuration value to be applied.

    required:
      - fsl,pins

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    iomuxc: pinctrl@30330000 {
        compatible = "fsl,imx8mq-iomuxc";
        reg = <0x30330000 0x10000>;

        pinctrl_uart1: uart1grp {
            fsl,pins =
                <0x234 0x49C 0x4F4 0x0 0x0	0x49>,
                <0x238 0x4A0 0x4F4 0x0 0x0	0x49>;
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale IMX8ULP IOMUX Controller

maintainers:
  - Jacky Bai <ping.bai@nxp.com>

description:
  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
  for common binding part and usage.

properties:
  compatible:
    const: fsl,imx8ulp-iomuxc1

  reg:
    maxItems: 1

# Client device subnode's properties
patternProperties:
  'grp$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.

    properties:
      fsl,pins:
        description:
          each entry consists of 5 integers and represents the mux and config
          setting for one pin. The first 4 integers <mux_config_reg input_reg
          mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can
          be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last
          integer CONFIG is the pad setting value like pull-up on this pin. Please
          refer to i.MX8ULP Reference Manual for detailed CONFIG settings.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
            - description: |
                "mux_config_reg" indicates the offset of mux register.
            - description: |
                "input_reg" indicates the offset of select input register.
            - description: |
                "mux_mode" indicates the mux value to be applied.
            - description: |
                "input_val" indicates the select input value to be applied.
            - description: |
                "pad_setting" indicates the pad configuration value to be applied.

    required:
      - fsl,pins

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    iomuxc: pinctrl@298c0000 {
        compatible = "fsl,imx8ulp-iomuxc1";
        reg = <0x298c0000 0x10000>;

        pinctrl_lpuart5: lpuart5grp {
            fsl,pins =
                <0x0138 0x08F0 0x4 0x3	0x3>,
                <0x013C 0x08EC 0x4 0x3	0x3>;
        };
    };

...


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale IMX93 IOMUX Controller

maintainers:
  - Peng Fan <peng.fan@nxp.com>

description:
  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
  for common binding part and usage.

allOf:
  - $ref: "pinctrl.yaml#"

properties:
  compatible:
    const: fsl,imx93-iomuxc

  reg:
    maxItems: 1

# Client device subnode's properties
patternProperties:
  'grp$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.

    properties:
      fsl,pins:
        description:
          each entry consists of 6 integers and represents the mux and config
          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
          be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
          integer CONFIG is the pad setting value like pull-up on this pin. Please
          refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
            - description: |
                "mux_reg" indicates the offset of mux register.
            - description: |
                "conf_reg" indicates the offset of pad configuration register.
            - description: |
                "input_reg" indicates the offset of select input register.
            - description: |
                "mux_val" indicates the mux value to be applied.
            - description: |
                "input_val" indicates the select input value to be applied.
            - description: |
                "pad_setting" indicates the pad configuration value to be applied.

    required:
      - fsl,pins

    additionalProperties: false

required:
  - compatible
  - reg

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    iomuxc: pinctrl@443c0000 {
        compatible = "fsl,imx93-iomuxc";
        reg = <0x30330000 0x10000>;

        pinctrl_uart3: uart3grp {
            fsl,pins =
                <0x48 0x1f8 0x41c 0x1 0x0	0x49>,
                <0x4c 0x1fc 0x418 0x1 0x0	0x49>;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1050.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale IMXRT1050 IOMUX Controller

maintainers:
  - Giulio Benetti <giulio.benetti@benettiengineering.com>
  - Jesse Taube <Mr.Bossman075@gmail.com>

description:
  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
  for common binding part and usage.

properties:
  compatible:
    const: fsl,imxrt1050-iomuxc

  reg:
    maxItems: 1

# Client device subnode's properties
patternProperties:
  'grp$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.

    properties:
      fsl,pins:
        description:
          each entry consists of 6 integers and represents the mux and config
          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
          be found in <arch/arm/boot/dts/imxrt1050-pinfunc.h>. The last
          integer CONFIG is the pad setting value like pull-up on this pin. Please
          refer to i.MXRT1050 Reference Manual for detailed CONFIG settings.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
            - description: |
                "mux_reg" indicates the offset of mux register.
            - description: |
                "conf_reg" indicates the offset of pad configuration register.
            - description: |
                "input_reg" indicates the offset of select input register.
            - description: |
                "mux_val" indicates the mux value to be applied.
            - description: |
                "input_val" indicates the select input value to be applied.
            - description: |
                "pad_setting" indicates the pad configuration value to be applied.

    required:
      - fsl,pins

    additionalProperties: false

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    iomuxc: iomuxc@401f8000 {
        compatible = "fsl,imxrt1050-iomuxc";
        reg = <0x401f8000 0x4000>;

        pinctrl_lpuart1: lpuart1grp {
            fsl,pins =
              <0x0EC 0x2DC 0x000 0x2 0x0	0xf1>,
              <0x0F0 0x2E0 0x000 0x2 0x0	0xf1>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1170.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MXRT1170 IOMUX Controller

maintainers:
  - Giulio Benetti <giulio.benetti@benettiengineering.com>
  - Jesse Taube <Mr.Bossman075@gmail.com>

description:
  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
  for common binding part and usage.

properties:
  compatible:
    const: fsl,imxrt1170-iomuxc

  reg:
    maxItems: 1

# Client device subnode's properties
patternProperties:
  'grp$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.

    properties:
      fsl,pins:
        description:
          each entry consists of 6 integers and represents the mux and config
          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
          be found in <arch/arm/boot/dts/imxrt1170-pinfunc.h>. The last
          integer CONFIG is the pad setting value like pull-up on this pin. Please
          refer to i.MXRT1170 Reference Manual for detailed CONFIG settings.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
            - description: |
                "mux_reg" indicates the offset of mux register.
            - description: |
                "conf_reg" indicates the offset of pad configuration register.
            - description: |
                "input_reg" indicates the offset of select input register.
            - description: |
                "mux_val" indicates the mux value to be applied.
            - description: |
                "input_val" indicates the select input value to be applied.
            - description: |
                "pad_setting" indicates the pad configuration value to be applied.
    required:
      - fsl,pins

    additionalProperties: false

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    iomuxc: iomuxc@400e8000 {
        compatible = "fsl,imxrt1170-iomuxc";
        reg = <0x400e8000 0x4000>;
        pinctrl_lpuart1: lpuart1grp {
            fsl,pins =
              <0x16C 0x3B0 0x620 0x0 0x0  0xf1>,
              <0x170 0x3B4 0x61C 0x0 0x0	0xf1>;
        };
    };


code:
* Freescale MXS Pin Controller

The pins controlled by mxs pin controller are organized in banks, each bank
has 32 pins.  Each pin has 4 multiplexing functions, and generally, the 4th
function is GPIO.  The configuration on the pins includes drive strength,
voltage and pull-up.

Required properties:
- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
- reg: Should contain the register physical address and length for the
  pin controller.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.

The node of mxs pin controller acts as a container for an arbitrary number of
subnodes.  Each of these subnodes represents some desired configuration for
a group of pins, and only affects those parameters that are explicitly listed.
In other words, a subnode that describes a drive strength parameter implies no
information about pull-up. For this reason, even seemingly boolean values are
actually tristates in this binding: unspecified, off, or on. Unspecified is
represented as an absent property, and off/on are represented as integer
values 0 and 1.

Those subnodes under mxs pin controller node will fall into two categories.
One is to set up a group of pins for a function, both mux selection and pin
configurations, and it's called group node in the binding document.   The other
one is to adjust the pin configuration for some particular pins that need a
different configuration than what is defined in group node.  The binding
document calls this type of node config node.

On mxs, there is no hardware pin group. The pin group in this binding only
means a group of pins put together for particular peripheral to work in
particular function, like SSP0 functioning as mmc0-8bit.  That said, the
group node should include all the pins needed for one function rather than
having these pins defined in several group nodes.  It also means each of
"pinctrl-*" phandle in client device node should only have one group node
pointed in there, while the phandle can have multiple config node referenced
there to adjust configurations for some pins in the group.

Required subnode-properties:
- fsl,pinmux-ids: An integer array.  Each integer in the array specify a pin
  with given mux function, with bank, pin and mux packed as below.

    [15..12] : bank number
    [11..4]  : pin number
    [3..0]   : mux selection

  This integer with mux selection packed is used as an entity by both group
  and config nodes to identify a pin.  The mux selection in the integer takes
  effects only on group node, and will get ignored by driver with config node,
  since config node is only meant to set up pin configurations.

  Valid values for these integers are listed below.

- reg: Should be the index of the group nodes for same function.  This property
  is required only for group nodes, and should not be present in any config
  nodes.

Optional subnode-properties:
- fsl,drive-strength: Integer.
    0: MXS_DRIVE_4mA
    1: MXS_DRIVE_8mA
    2: MXS_DRIVE_12mA
    3: MXS_DRIVE_16mA
- fsl,voltage: Integer.
    0: MXS_VOLTAGE_LOW  - 1.8 V
    1: MXS_VOLTAGE_HIGH - 3.3 V
- fsl,pull-up: Integer.
    0: MXS_PULL_DISABLE - Disable the internal pull-up
    1: MXS_PULL_ENABLE  - Enable the internal pull-up

Note that when enabling the pull-up, the internal pad keeper gets disabled.
Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up
will only disable the internal pad keeper.

Examples:

pinctrl@80018000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx28-pinctrl";
	reg = <0x80018000 2000>;

	mmc0_8bit_pins_a: mmc0-8bit@0 {
		reg = <0>;
		fsl,pinmux-ids = <
			MX28_PAD_SSP0_DATA0__SSP0_D0
			MX28_PAD_SSP0_DATA1__SSP0_D1
			MX28_PAD_SSP0_DATA2__SSP0_D2
			MX28_PAD_SSP0_DATA3__SSP0_D3
			MX28_PAD_SSP0_DATA4__SSP0_D4
			MX28_PAD_SSP0_DATA5__SSP0_D5
			MX28_PAD_SSP0_DATA6__SSP0_D6
			MX28_PAD_SSP0_DATA7__SSP0_D7
			MX28_PAD_SSP0_CMD__SSP0_CMD
			MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
			MX28_PAD_SSP0_SCK__SSP0_SCK
		>;
		fsl,drive-strength = <MXS_DRIVE_4mA>;
		fsl,voltage = <MXS_VOLTAGE_HIGH>;
		fsl,pull-up = <MXS_PULL_ENABLE>;
	};

	mmc_cd_cfg: mmc-cd-cfg {
		fsl,pinmux-ids = <MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT>;
		fsl,pull-up = <MXS_PULL_DISABLE>;
	};

	mmc_sck_cfg: mmc-sck-cfg {
		fsl,pinmux-ids = <MX28_PAD_SSP0_SCK__SSP0_SCK>;
		fsl,drive-strength = <MXS_DRIVE_12mA>;
		fsl,pull-up = <MXS_PULL_DISABLE>;
	};
};

In this example, group node mmc0-8bit defines a group of pins for mxs SSP0
to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations
applied on all these pins.  And config nodes mmc-cd-cfg and mmc-sck-cfg are
adjusting the configuration for pins card-detection and clock from what group
node mmc0-8bit defines.  Only the configuration properties to be adjusted need
to be listed in the config nodes.

Valid values for i.MX28/i.MX23 pinmux-id are defined in
arch/arm/boot/dts/imx28-pinfunc.h and arch/arm/boot/dts/imx23-pinfunc.h.
The definitions for the padconfig properties can be found in
arch/arm/boot/dts/mxs-pinfunc.h.


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,scu-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: i.MX SCU Client Device Node - Pinctrl bindings based on SCU Message Protocol

maintainers:
  - Dong Aisheng <aisheng.dong@nxp.com>

description: i.MX SCU Client Device Node
  Client nodes are maintained as children of the relevant IMX-SCU device node.
  This binding uses the i.MX common pinctrl binding.
  (Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt)

allOf:
  - $ref: pinctrl.yaml#

properties:
  compatible:
    enum:
      - fsl,imx8qm-iomuxc
      - fsl,imx8qxp-iomuxc
      - fsl,imx8dxl-iomuxc

patternProperties:
  'grp$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.

    properties:
      fsl,pins:
        description:
          each entry consists of 3 integers and represents the pin ID, the mux value
          and pad setting for the pin. The first 2 integers - pin_id and mux_val - are
          specified using a PIN_FUNC_ID macro, which can be found in
          <include/dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer is
          the pad setting value like pull-up on this pin. Please refer to the
          appropriate i.MX8 Reference Manual for detailed pad CONFIG settings.
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
            - description: |
                "pin_id" indicates the pin ID
            - description: |
                "mux_val" indicates the mux value to be applied.
            - description: |
                "pad_setting" indicates the pad configuration value to be applied.

    required:
      - fsl,pins

    additionalProperties: false

required:
  - compatible

additionalProperties: false

examples:
  - |
    pinctrl {
        compatible = "fsl,imx8qxp-iomuxc";

        pinctrl_lpuart0: lpuart0grp {
            fsl,pins = <
                111 0 0x06000020
                112 0 0x06000020
            >;
        };
    };


code:
Freescale Vybrid VF610 IOMUX Controller

Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.

Required properties:
- compatible: "fsl,vf610-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
  a pin working on a specific function, CONFIG is the pad setting value
  such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
  datasheet for the valid pad config settings.

CONFIG bits definition:
PAD_CTL_SPEED_LOW		(1 << 12)
PAD_CTL_SPEED_MED		(2 << 12)
PAD_CTL_SPEED_HIGH		(3 << 12)
PAD_CTL_SRE_FAST		(1 << 11)
PAD_CTL_SRE_SLOW		(0 << 11)
PAD_CTL_ODE			(1 << 10)
PAD_CTL_HYS			(1 << 9)
PAD_CTL_DSE_DISABLE		(0 << 6)
PAD_CTL_DSE_150ohm		(1 << 6)
PAD_CTL_DSE_75ohm		(2 << 6)
PAD_CTL_DSE_50ohm		(3 << 6)
PAD_CTL_DSE_37ohm		(4 << 6)
PAD_CTL_DSE_30ohm		(5 << 6)
PAD_CTL_DSE_25ohm		(6 << 6)
PAD_CTL_DSE_20ohm		(7 << 6)
PAD_CTL_PUS_100K_DOWN		(0 << 4)
PAD_CTL_PUS_47K_UP		(1 << 4)
PAD_CTL_PUS_100K_UP		(2 << 4)
PAD_CTL_PUS_22K_UP		(3 << 4)
PAD_CTL_PKE			(1 << 3)
PAD_CTL_PUE			(1 << 2)
PAD_CTL_OBE_ENABLE		(1 << 1)
PAD_CTL_IBE_ENABLE		(1 << 0)
PAD_CTL_OBE_IBE_ENABLE		(3 << 0)

Please refer to vf610-pinfunc.h in device tree source folder
for all available PIN_FUNC_ID for Vybrid VF610.


code:
Imagination Technologies Pistachio SoC pin controllers
======================================================

The pin controllers on Pistachio are a combined GPIO controller, (GPIO)
interrupt controller, and pinmux + pinconf device. The system ("east") pin
controller on Pistachio has 99 pins, 90 of which are MFIOs which can be
configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs
each. The GPIO banks are represented as sub-nodes of the pad controller node.

Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
../interrupt-controller/interrupts.txt for generic information regarding
pin controller, GPIO, and interrupt bindings.

Required properties for pin controller node:
--------------------------------------------
 - compatible: "img,pistachio-system-pinctrl".
 - reg: Address range of the pinctrl registers.

Required properties for GPIO bank sub-nodes:
--------------------------------------------
 - interrupts: Interrupt line for the GPIO bank.
 - gpio-controller: Indicates the device is a GPIO controller.
 - #gpio-cells: Must be two. The first cell is the GPIO pin number and the
   second cell indicates the polarity. See <dt-bindings/gpio/gpio.h> for
   a list of possible values.
 - interrupt-controller: Indicates the device is an interrupt controller.
 - #interrupt-cells: Must be two. The first cell is the GPIO pin number and
   the second cell encodes the interrupt flags. See
   <dt-bindings/interrupt-controller/irq.h> for a list of valid flags.

Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1.

Required properties for pin configuration sub-nodes:
----------------------------------------------------
 - pins: List of pins to which the configuration applies. See below for a
   list of possible pins.

Optional properties for pin configuration sub-nodes:
----------------------------------------------------
 - function: Mux function for the specified pins. This is not applicable for
   non-MFIO pins. See below for a list of valid functions for each pin.
 - bias-high-impedance: Enable high-impedance mode.
 - bias-pull-up: Enable weak pull-up.
 - bias-pull-down: Enable weak pull-down.
 - bias-bus-hold: Enable bus-keeper mode.
 - drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12.
 - input-schmitt-enable: Enable Schmitt trigger.
 - input-schmitt-disable: Disable Schmitt trigger.
 - slew-rate: Slew rate control. 0 for slow, 1 for fast.

Pin		Functions
---		---------
mfio0		spim1
mfio1		spim1, spim0, uart1
mfio2		spim1, spim0, uart1
mfio3		spim1
mfio4		spim1
mfio5		spim1
mfio6		spim1
mfio7		spim1
mfio8		spim0
mfio9		spim0
mfio10		spim0
mfio11		spis
mfio12		spis
mfio13		spis
mfio14		spis
mfio15		sdhost, mips_trace_clk, mips_trace_data
mfio16		sdhost, mips_trace_dint, mips_trace_data
mfio17		sdhost, mips_trace_trigout, mips_trace_data
mfio18		sdhost, mips_trace_trigin, mips_trace_data
mfio19		sdhost, mips_trace_dm, mips_trace_data
mfio20		sdhost, mips_trace_probe_n, mips_trace_data
mfio21		sdhost, mips_trace_data
mfio22		sdhost, mips_trace_data
mfio23		sdhost
mfio24		sdhost
mfio25		sdhost
mfio26		sdhost
mfio27		sdhost
mfio28		i2c0, spim0
mfio29		i2c0, spim0
mfio30		i2c1, spim0
mfio31		i2c1, spim1
mfio32		i2c2
mfio33		i2c2
mfio34		i2c3
mfio35		i2c3
mfio36		i2s_out, audio_clk_in
mfio37		i2s_out, debug_raw_cca_ind
mfio38		i2s_out, debug_ed_sec20_cca_ind
mfio39		i2s_out, debug_ed_sec40_cca_ind
mfio40		i2s_out, debug_agc_done_0
mfio41		i2s_out, debug_agc_done_1
mfio42		i2s_out, debug_ed_cca_ind
mfio43		i2s_out, debug_s2l_done
mfio44		i2s_out
mfio45		i2s_dac_clk, audio_sync
mfio46		audio_trigger
mfio47		i2s_in
mfio48		i2s_in
mfio49		i2s_in
mfio50		i2s_in
mfio51		i2s_in
mfio52		i2s_in
mfio53		i2s_in
mfio54		i2s_in, spdif_in
mfio55		uart0, spim0, spim1
mfio56		uart0, spim0, spim1
mfio57		uart0, spim0, spim1
mfio58		uart0, spim1
mfio59		uart1
mfio60		uart1
mfio61		spdif_out
mfio62		spdif_in
mfio63		eth, mips_trace_clk, mips_trace_data
mfio64		eth, mips_trace_dint, mips_trace_data
mfio65		eth, mips_trace_trigout, mips_trace_data
mfio66		eth, mips_trace_trigin, mips_trace_data
mfio67		eth, mips_trace_dm, mips_trace_data
mfio68		eth, mips_trace_probe_n, mips_trace_data
mfio69		eth, mips_trace_data
mfio70		eth, mips_trace_data
mfio71		eth
mfio72		ir
mfio73		pwmpdm, mips_trace_clk, sram_debug
mfio74		pwmpdm, mips_trace_dint, sram_debug
mfio75		pwmpdm, mips_trace_trigout, rom_debug
mfio76		pwmpdm, mips_trace_trigin, rom_debug
mfio77		mdc_debug, mips_trace_dm, rpu_debug
mfio78		mdc_debug, mips_trace_probe_n, rpu_debug
mfio79		ddr_debug, mips_trace_data, mips_debug
mfio80		ddr_debug, mips_trace_data, mips_debug
mfio81		dreq0, mips_trace_data, eth_debug
mfio82		dreq1, mips_trace_data, eth_debug
mfio83		mips_pll_lock, mips_trace_data, usb_debug
mfio84		audio_pll_lock, mips_trace_data, usb_debug
mfio85		rpu_v_pll_lock, mips_trace_data, sdhost_debug
mfio86		rpu_l_pll_lock, mips_trace_data, sdhost_debug
mfio87		sys_pll_lock, dreq2, socif_debug
mfio88		wifi_pll_lock, dreq3, socif_debug
mfio89		bt_pll_lock, dreq4, dreq5
tck
trstn
tdi
tms
tdo
jtag_comply
safe_mode
por_disable
resetn

Example:
--------
pinctrl@18101c00 {
	compatible = "img,pistachio-system-pinctrl";
	reg = <0x18101C00 0x400>;

	gpio0: gpio0 {
		interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	...

	gpio5: gpio5 {
		interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;
		#gpio-cells = <2>;

		interrupt-controller;
		#interrupt-cells = <2>;
	};

	...

	uart0_xfer: uart0-xfer {
		uart0-rxd {
			pins = "mfio55";
			function = "uart0";
		};
		uart0-txd {
			pins = "mfio56";
			function = "uart0";
		};
	};

	uart0_rts_cts: uart0-rts-cts {
		uart0-rts {
			  pins = "mfio57";
			  function = "uart0";
		};
		uart0-cts {
			  pins = "mfio58";
			  function = "uart0";
		};
	};
};

uart@... {
	...
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>;
	...
};

usb_vbus: fixed-regulator {
	...
	gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;
	...
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs pin controller devicetree bindings

description: >
  Please refer to pinctrl-bindings.txt in this directory for details of the
  common pinctrl bindings used by client devices, including the meaning of the
  phrase "pin configuration node".

  For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins
  may be used as GPIOs, multiplexed device functions are configured within the
  GPIO port configuration registers and it is typical to refer to pins using the
  naming scheme "PxN" where x is a character identifying the GPIO port with
  which the pin is associated and N is an integer from 0 to 31 identifying the
  pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
  and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B,
  the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128
  pins. The X2000 and the X2100 contains 5 GPIO ports, PA to PE, for a total of
  160 pins. The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains
  6 GPIO ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO
  ports, PA to PG, for a total of 224 pins.

maintainers:
  - Paul Cercueil <paul@crapouillou.net>

properties:
  compatible:
    oneOf:
      - enum:
          - ingenic,jz4730-pinctrl
          - ingenic,jz4740-pinctrl
          - ingenic,jz4725b-pinctrl
          - ingenic,jz4750-pinctrl
          - ingenic,jz4755-pinctrl
          - ingenic,jz4760-pinctrl
          - ingenic,jz4770-pinctrl
          - ingenic,jz4775-pinctrl
          - ingenic,jz4780-pinctrl
          - ingenic,x1000-pinctrl
          - ingenic,x1500-pinctrl
          - ingenic,x1830-pinctrl
          - ingenic,x2000-pinctrl
          - ingenic,x2100-pinctrl
      - items:
          - const: ingenic,jz4760b-pinctrl
          - const: ingenic,jz4760-pinctrl
      - items:
          - const: ingenic,x1000e-pinctrl
          - const: ingenic,x1000-pinctrl
      - items:
          - const: ingenic,x2000e-pinctrl
          - const: ingenic,x2000-pinctrl

  reg:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

patternProperties:
  "^gpio@[0-9]$":
    type: object
    properties:
      compatible:
        enum:
          - ingenic,jz4730-gpio
          - ingenic,jz4740-gpio
          - ingenic,jz4725b-gpio
          - ingenic,jz4750-gpio
          - ingenic,jz4755-gpio
          - ingenic,jz4760-gpio
          - ingenic,jz4770-gpio
          - ingenic,jz4775-gpio
          - ingenic,jz4780-gpio
          - ingenic,x1000-gpio
          - ingenic,x1500-gpio
          - ingenic,x1830-gpio
          - ingenic,x2000-gpio
          - ingenic,x2100-gpio

      reg:
        items:
          - description: The GPIO bank number

      gpio-controller: true

      "#gpio-cells":
        const: 2

      gpio-ranges:
        maxItems: 1

      interrupt-controller: true

      "#interrupt-cells":
        const: 2
        description:
          Refer to ../interrupt-controller/interrupts.txt for more details.

      interrupts:
        maxItems: 1

    required:
      - compatible
      - reg
      - gpio-controller
      - "#gpio-cells"
      - interrupts
      - interrupt-controller
      - "#interrupt-cells"

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"

additionalProperties:
  anyOf:
    - type: object
      allOf:
        - $ref: pincfg-node.yaml#
        - $ref: pinmux-node.yaml#

      properties:
        phandle: true
        function: true
        groups: true
        pins: true
        bias-disable: true
        bias-pull-up: true
        bias-pull-down: true
        output-low: true
        output-high: true
      additionalProperties: false

    - type: object
      properties:
        phandle: true
      additionalProperties:
        type: object
        allOf:
          - $ref: pincfg-node.yaml#
          - $ref: pinmux-node.yaml#

        properties:
          phandle: true
          function: true
          groups: true
          pins: true
          bias-disable: true
          bias-pull-up: true
          bias-pull-down: true
          output-low: true
          output-high: true
        additionalProperties: false

examples:
  - |
    pinctrl@10010000 {
      compatible = "ingenic,jz4770-pinctrl";
      reg = <0x10010000 0x600>;

      #address-cells = <1>;
      #size-cells = <0>;

      gpio@0 {
        compatible = "ingenic,jz4770-gpio";
        reg = <0>;

        gpio-controller;
        gpio-ranges = <&pinctrl 0 0 32>;
        #gpio-cells = <2>;

        interrupt-controller;
        #interrupt-cells = <2>;

        interrupt-parent = <&intc>;
        interrupts = <17>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Lightning Mountain SoC pinmux & GPIO controller binding

maintainers:
  - Rahul Tanwar <rahul.tanwar@linux.intel.com>

description: |
  Pinmux & GPIO controller controls pin multiplexing & configuration including
  GPIO function selection & GPIO attributes configuration.

properties:
  compatible:
    const: intel,lgm-io

  reg:
    maxItems: 1

# Client device subnode's properties
patternProperties:
  '-pins$':
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: pinmux-node.yaml#

    properties:
      function: true
      groups: true
      pins: true
      pinmux: true
      bias-pull-up: true
      bias-pull-down: true
      drive-strength: true
      slew-rate: true
      drive-open-drain: true
      output-enable: true

    required:
      - function
      - groups

    additionalProperties: false

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  # Pinmux controller node
  - |
    pinctrl: pinctrl@e2880000 {
        compatible = "intel,lgm-io";
        reg = <0xe2880000 0x100000>;

        uart0-pins {
             pins = <64>, /* UART_RX0 */
                    <65>; /* UART_TX0 */
             function = "CONSOLE_UART0";
             pinmux = <1>,
                      <1>;
             groups = "CONSOLE_UART0";
          };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Keem Bay pin controller

maintainers:
  - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>

description: |
  Intel Keem Bay SoC integrates a pin controller which enables control
  of pin directions, input/output values and configuration
  for a total of 80 pins.

properties:
  compatible:
    const: intel,keembay-pinctrl

  reg:
    maxItems: 2

  gpio-controller: true

  '#gpio-cells':
    const: 2

  ngpios:
    description: The number of GPIOs exposed.
    const: 80

  interrupts:
    description:
      Specifies the interrupt lines to be used by the controller.
      Each interrupt line is shared by upto 4 GPIO lines.
    maxItems: 8

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

patternProperties:
  '^gpio@[0-9a-f]*$':
    type: object
    additionalProperties: false

    description:
      Child nodes can be specified to contain pin configuration information,
      which can then be utilized by pinctrl client devices.
      The following properties are supported.

    properties:
      pins:
        description: |
          The name(s) of the pins to be configured in the child node.
          Supported pin names are "GPIO0" up to "GPIO79".

      bias-disable: true

      bias-pull-down: true

      bias-pull-up: true

      drive-strength:
        description: IO pads drive strength in milli Ampere.
        enum: [2, 4, 8, 12]

      bias-bus-hold:
        type: boolean

      input-schmitt-enable:
        type: boolean

      slew-rate:
        description: GPIO slew rate control.
                      0 - Fast(~100MHz)
                      1 - Slow(~50MHz)
        enum: [0, 1]

additionalProperties: false

required:
  - compatible
  - reg
  - gpio-controller
  - ngpios
  - '#gpio-cells'
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    // Example 1
    gpio@0 {
        compatible = "intel,keembay-pinctrl";
        reg = <0x600b0000 0x88>,
              <0x600b0190 0x1ac>;
        gpio-controller;
        ngpios = <0x50>;
        #gpio-cells = <0x2>;
        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };

    // Example 2
    gpio@1 {
        compatible = "intel,keembay-pinctrl";
        reg = <0x600c0000 0x88>,
              <0x600c0190 0x1ac>;
        gpio-controller;
        ngpios = <0x50>;
        #gpio-cells = <0x2>;
        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-thunderbay.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Thunder Bay pin controller

maintainers:
  - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>

description: |
  Intel Thunder Bay SoC integrates a pin controller which enables control
  of pin directions, input/output values and configuration
  for a total of 67 pins.

properties:
  compatible:
    const: intel,thunderbay-pinctrl

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2

  gpio-ranges:
    maxItems: 1

  interrupts:
    description:
      Specifies the interrupt lines to be used by the controller.
    maxItems: 2

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

patternProperties:
  '^gpio@[0-9a-f]*$':
    type: object
    additionalProperties: false

    description:
      Child nodes can be specified to contain pin configuration information,
      which can then be utilized by pinctrl client devices.
      The following properties are supported.

    properties:
      pins:
        description: |
          The name(s) of the pins to be configured in the child node.
          Supported pin names are "GPIO0" up to "GPIO66".

      bias-disable: true

      bias-pull-down: true

      bias-pull-up: true

      drive-strength:
        description: Drive strength for the pad.
        enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]

      bias-bus-hold:
        type: boolean

      input-schmitt-enable:
        type: boolean

      slew-rate:
        description: GPIO slew rate control.
                      0 - Slow
                      1 - Fast
        enum: [0, 1]

additionalProperties: false

required:
  - compatible
  - reg
  - gpio-controller
  - '#gpio-cells'
  - gpio-ranges
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    // Example 1
    pinctrl0: gpio@0 {
        compatible = "intel,thunderbay-pinctrl";
        reg = <0x600b0000 0x88>;
        gpio-controller;
        #gpio-cells = <0x2>;
        gpio-ranges = <&pinctrl0 0 0 67>;
        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };

    // Example 2
    pinctrl1: gpio@1 {
        compatible = "intel,thunderbay-pinctrl";
        reg = <0x600c0000 0x88>;
        gpio-controller;
        #gpio-cells = <0x2>;
        gpio-ranges = <&pinctrl1 0 0 53>;
        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };


code:
Lantiq FALCON pinmux controller

Required properties:
- compatible: "lantiq,pinctrl-falcon"
- reg: Should contain the physical address and length of the gpio/pinmux
  register range

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

Lantiq's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those group(s), and two pin configuration parameters:
pull-up and open-drain

The name of each subnode is not important as long as it is unique; all subnodes
should be enumerated and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.

We support 2 types of nodes.

Definition of mux function groups:

Required subnode-properties:
- lantiq,groups : An array of strings. Each string contains the name of a group.
  Valid values for these names are listed below.
- lantiq,function: A string containing the name of the function to mux to the
  group. Valid values for function names are listed below.

Valid values for group and function names:

  mux groups:
    por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c,
    jtag, slic, pcm, asc1

  functions:
    rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm

Definition of pin configurations:

Required subnode-properties:
- lantiq,pins : An array of strings. Each string contains the name of a pin.
  Valid values for these names are listed below.

Optional subnode-properties:
- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
    0: none, 1: down
- lantiq,drive-current: Boolean, enables drive-current
- lantiq,slew-rate: Boolean, enables slew-rate

Example:
	pinmux0 {
		compatible = "lantiq,pinctrl-falcon";
		pinctrl-names = "default";
		pinctrl-0 = <&state_default>;

		state_default: pinmux {
			asc0 {
				lantiq,groups = "asc0";
				lantiq,function = "asc";
			};
			ntr {
				lantiq,groups = "ntr8k";
				lantiq,function = "ntr";
			};
			i2c {
				lantiq,groups = "i2c";
				lantiq,function = "i2c";
			};
			hrst {
				lantiq,groups = "hrst";
				lantiq,function = "rst";
			};
		};
	};


code:
Lantiq XWAY pinmux controller

Required properties:
- compatible: "lantiq,pinctrl-xway", (DEPRECATED: Use "lantiq,pinctrl-danube")
	      "lantiq,pinctrl-xr9", (DEPRECATED: Use "lantiq,xrx100-pinctrl" or
					"lantiq,xrx200-pinctrl")
	      "lantiq,pinctrl-ase", (DEPRECATED: Use "lantiq,ase-pinctrl")
	      "lantiq,<chip>-pinctrl", where <chip> is:
		"ase" (XWAY AMAZON Family)
		"danube" (XWAY DANUBE Family)
		"xrx100" (XWAY xRX100 Family)
		"xrx200" (XWAY xRX200 Family)
		"xrx300" (XWAY xRX300 Family)
- reg: Should contain the physical address and length of the gpio/pinmux
  register range

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

Lantiq's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those group(s), and two pin configuration parameters:
pull-up and open-drain

The name of each subnode is not important as long as it is unique; all subnodes
should be enumerated and processed purely based on their content.

Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.

We support 2 types of nodes.

Definition of mux function groups:

Required subnode-properties:
- lantiq,groups : An array of strings. Each string contains the name of a group.
  Valid values for these names are listed below.
- lantiq,function: A string containing the name of the function to mux to the
  group. Valid values for function names are listed below.

Valid values for group and function names:

XWAY: (DEPRECATED: Use DANUBE)
  mux groups:
    exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
    ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
    spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2,
    gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,
    req3

  functions:
    spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu

XR9: ( DEPRECATED: Use xRX100/xRX200)
  mux groups:
    exin0, exin1, exin2, exin3, exin4, jtag, ebu a23, ebu a24, ebu a25,
    ebu clk, ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy,
    nand rd, spi, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6,
    asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
    clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio,
    gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2

  functions:
    spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio, gphy

AMAZON:
  mux groups:
    exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2,
    spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0,
    clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2

  functions:
    spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe

DANUBE:
  mux groups:
    exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
    ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
    spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi,
    gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3,
    req1, req2, req3, dfe led0, dfe led1

  functions:
    spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe

xRX100:
  mux groups:
    exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
    ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
    spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
    spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
    clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio,
    dfe led0, dfe led1

  functions:
    spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe

xRX200:
  mux groups:
    exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
    ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
    spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
    spi_cs6, usif uart_rx, usif uart_tx, usif uart_rts, usif uart_cts,
    usif uart_dtr, usif uart_dsr, usif uart_dcd, usif uart_ri, usif spi_di,
    usif spi_do, usif spi_clk, usif spi_cs0, usif spi_cs1, usif spi_cs2,
    stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1,
    gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, dfe led0, dfe led1,
    gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2

  functions:
    spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy

xRX300:
  mux groups:
    exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
    nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
    nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
    spi_clk, spi_cs1, spi_cs4, spi_cs6, usif uart_rx, usif uart_tx,
    usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2,
    mdio, dfe led0, dfe led1, ephy0 led0, ephy0 led1, ephy1 led0, ephy1 led1

  functions:
    spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy

Definition of pin configurations:

Required subnode-properties:
- lantiq,pins : An array of strings. Each string contains the name of a pin.
  Valid values for these names are listed below.

Optional subnode-properties:
- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
    0: none, 1: down, 2: up.
- lantiq,open-drain: Boolean, enables open-drain on the defined pin.

Valid values for XWAY pin names: (DEPRECATED: Use DANUBE)
  Pinconf pins can be referenced via the names io0-io31.

Valid values for XR9 pin names: (DEPRECATED: Use xrX100/xRX200)
  Pinconf pins can be referenced via the names io0-io55.

Valid values for AMAZON pin names:
  Pinconf pins can be referenced via the names io0-io31.

Valid values for DANUBE pin names:
  Pinconf pins can be referenced via the names io0-io31.

Valid values for xRX100 pin names:
  Pinconf pins can be referenced via the names io0-io55.

Valid values for xRX200 pin names:
  Pinconf pins can be referenced via the names io0-io49.

Valid values for xRX300 pin names:
  Pinconf pins can be referenced via the names io0-io1,io3-io6,io8-io11,
						io13-io19,io23-io27,io34-io36,
						io42-io43,io48-io61.

Example:
	gpio: pinmux@e100b10 {
		compatible = "lantiq,danube-pinctrl";
		pinctrl-names = "default";
		pinctrl-0 = <&state_default>;

		#gpio-cells = <2>;
		gpio-controller;
		reg = <0xE100B10 0xA0>;

		state_default: pinmux {
			stp {
				lantiq,groups = "stp";
				lantiq,function = "stp";
			};
			pci {
				lantiq,groups = "gnt1";
				lantiq,function = "pci";
			};
			conf_out {
				lantiq,pins = "io4", "io5", "io6"; /* stp */
				lantiq,open-drain;
				lantiq,pull = <0>;
			};
		};
	};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/loongson,ls2k-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Loongson-2 SoC Pinctrl Controller

maintainers:
  - zhanghongchen <zhanghongchen@loongson.cn>
  - Yinbo Zhu <zhuyinbo@loongson.cn>

allOf:
  - $ref: pinctrl.yaml#

properties:
  compatible:
    const: loongson,ls2k-pinctrl

  reg:
    maxItems: 1

patternProperties:
  '-pins$':
    type: object

    additionalProperties: false

    patternProperties:
      'pinmux$':
        type: object
        description: node for pinctrl.
        $ref: pinmux-node.yaml#

        unevaluatedProperties: false

        properties:
          groups:
            description:
              One or more groups of pins to mux to a certain function
            items:
              enum: [gpio, sdio, can1, can0, pwm3, pwm2, pwm1, pwm0, i2c1, i2c0,
                     nand, sata_led, i2s, hda]
          function:
            description:
              The function that a group of pins is muxed to
            enum: [gpio, sdio, can1, can0, pwm3, pwm2, pwm1, pwm0, i2c1, i2c0,
                   nand, sata_led, i2s, hda]

        required:
          - groups
          - function

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pctrl: pinctrl@1fe00420 {
        compatible = "loongson,ls2k-pinctrl";
        reg = <0x1fe00420 0x18>;
        sdio_pins_default: sdio-pins {
            sdio-pinmux {
                groups = "sdio";
                function = "sdio";
            };

            sdio-det-pinmux {
                groups = "pwm2";
                function = "gpio";
            };
        };

        pwm1_pins_default: pwm1-pins {
            pinmux {
                groups = "pwm1";
                function = "pwm1";
            };
        };

        pwm0_pins_default: pwm0-pins {
            pinmux {
                groups = "pwm0";
                function = "pwm0";
            };
        };

        i2c1_pins_default: i2c1-pins {
            pinmux {
                groups = "i2c1";
                function = "i2c1";
            };
        };

        i2c0_pins_default: i2c0-pins {
            pinmux {
                groups = "i2c0";
                function = "i2c0";
            };
        };

        nand_pins_default: nand-pins {
            pinmux {
                groups = "nand";
                function = "nand";
            };
        };

        hda_pins_default: hda-pins {
            grp0-pinmux {
                groups = "hda";
                function = "hda";
            };

            grp1-pinmux {
                groups = "i2s";
                function = "gpio";
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/marvell,ac5-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell AC5 pin controller

maintainers:
  - Chris Packham <chris.packham@alliedtelesis.co.nz>

description:
  Bindings for Marvell's AC5 memory-mapped pin controller.

properties:
  compatible:
    items:
      - const: marvell,ac5-pinctrl

  reg:
    maxItems: 1

patternProperties:
  '-pins$':
    type: object
    $ref: pinmux-node.yaml#
    additionalProperties: false

    properties:
      marvell,function:
        $ref: "/schemas/types.yaml#/definitions/string"
        description:
          Indicates the function to select.
        enum: [ dev_init_done, ge, gpio, i2c0, i2c1, int_out, led, nand, pcie, ptp, sdio,
                spi0, spi1, synce, tsen_int, uart0, uart1, uart2, uart3, uartsd, wd_int, xg ]

      marvell,pins:
        $ref: /schemas/types.yaml#/definitions/string-array
        description:
          Array of MPP pins to be used for the given function.
        minItems: 1
        items:
          enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9,
                  mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, mpp18, mpp19,
                  mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, mpp26, mpp27, mpp28, mpp29,
                  mpp30, mpp31, mpp32, mpp33, mpp34, mpp35, mpp36, mpp37, mpp38, mpp39,
                  mpp40, mpp41, mpp42, mpp43, mpp44, mpp45 ]

allOf:
  - $ref: "pinctrl.yaml#"

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pinctrl@80020100 {
      compatible = "marvell,ac5-pinctrl";
      reg = <0x80020100 0x20>;

      i2c0_pins: i2c0-pins {
        marvell,pins = "mpp26", "mpp27";
        marvell,function = "i2c0";
      };

      i2c0_gpio: i2c0-gpio-pins {
        marvell,pins = "mpp26", "mpp27";
        marvell,function = "gpio";
      };
    };