code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ALPHA_PGTABLE_H
#define _ALPHA_PGTABLE_H

#include <asm-generic/pgtable-nopud.h>

/*
 * This file contains the functions and defines necessary to modify and use
 * the Alpha page table tree.
 *
 * This hopefully works with any standard Alpha page-size, as defined
 * in <asm/page.h> (currently 8192).
 */
#include <linux/mmzone.h>

#include <asm/page.h>
#include <asm/processor.h>	/* For TASK_SIZE */
#include <asm/machvec.h>
#include <asm/setup.h>

struct mm_struct;
struct vm_area_struct;

/* Certain architectures need to do special things when PTEs
 * within a page table are directly modified.  Thus, the following
 * hook is made available.
 */
#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)

/* PMD_SHIFT determines the size of the area a second-level page table can map */
#define PMD_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT-3))
#define PMD_SIZE	(1UL << PMD_SHIFT)
#define PMD_MASK	(~(PMD_SIZE-1))

/* PGDIR_SHIFT determines what a third-level page table entry can map */
#define PGDIR_SHIFT	(PAGE_SHIFT + 2*(PAGE_SHIFT-3))
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * Entries per page directory level:  the Alpha is three-level, with
 * all levels having a one-page page table.
 */
#define PTRS_PER_PTE	(1UL << (PAGE_SHIFT-3))
#define PTRS_PER_PMD	(1UL << (PAGE_SHIFT-3))
#define PTRS_PER_PGD	(1UL << (PAGE_SHIFT-3))
#define USER_PTRS_PER_PGD	(TASK_SIZE / PGDIR_SIZE)

/* Number of pointers that fit on a page:  this will go away. */
#define PTRS_PER_PAGE	(1UL << (PAGE_SHIFT-3))

#ifdef CONFIG_ALPHA_LARGE_VMALLOC
#define VMALLOC_START		0xfffffe0000000000
#else
#define VMALLOC_START		(-2*PGDIR_SIZE)
#endif
#define VMALLOC_END		(-PGDIR_SIZE)

/*
 * OSF/1 PAL-code-imposed page table bits
 */
#define _PAGE_VALID	0x0001
#define _PAGE_FOR	0x0002	/* used for page protection (fault on read) */
#define _PAGE_FOW	0x0004	/* used for page protection (fault on write) */
#define _PAGE_FOE	0x0008	/* used for page protection (fault on exec) */
#define _PAGE_ASM	0x0010
#define _PAGE_KRE	0x0100	/* xxx - see below on the "accessed" bit */
#define _PAGE_URE	0x0200	/* xxx */
#define _PAGE_KWE	0x1000	/* used to do the dirty bit in software */
#define _PAGE_UWE	0x2000	/* used to do the dirty bit in software */

/* .. and these are ours ... */
#define _PAGE_DIRTY	0x20000
#define _PAGE_ACCESSED	0x40000

/*
 * NOTE! The "accessed" bit isn't necessarily exact:  it can be kept exactly
 * by software (use the KRE/URE/KWE/UWE bits appropriately), but I'll fake it.
 * Under Linux/AXP, the "accessed" bit just means "read", and I'll just use
 * the KRE/URE bits to watch for it. That way we don't need to overload the
 * KWE/UWE bits with both handling dirty and accessed.
 *
 * Note that the kernel uses the accessed bit just to check whether to page
 * out a page or not, so it doesn't have to be exact anyway.
 */

#define __DIRTY_BITS	(_PAGE_DIRTY | _PAGE_KWE | _PAGE_UWE)
#define __ACCESS_BITS	(_PAGE_ACCESSED | _PAGE_KRE | _PAGE_URE)

#define _PFN_MASK	0xFFFFFFFF00000000UL

#define _PAGE_TABLE	(_PAGE_VALID | __DIRTY_BITS | __ACCESS_BITS)
#define _PAGE_CHG_MASK	(_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS)

/*
 * All the normal masks have the "page accessed" bits on, as any time they are used,
 * the page is accessed. They are cleared only by the page-out routines
 */
#define PAGE_NONE	__pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOR | _PAGE_FOW | _PAGE_FOE)
#define PAGE_SHARED	__pgprot(_PAGE_VALID | __ACCESS_BITS)
#define PAGE_COPY	__pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
#define PAGE_READONLY	__pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
#define PAGE_KERNEL	__pgprot(_PAGE_VALID | _PAGE_ASM | _PAGE_KRE | _PAGE_KWE)

#define _PAGE_NORMAL(x) __pgprot(_PAGE_VALID | __ACCESS_BITS | (x))

#define _PAGE_P(x) _PAGE_NORMAL((x) | (((x) & _PAGE_FOW)?0:_PAGE_FOW))
#define _PAGE_S(x) _PAGE_NORMAL(x)

/*
 * The hardware can handle write-only mappings, but as the Alpha
 * architecture does byte-wide writes with a read-modify-write
 * sequence, it's not practical to have write-without-read privs.
 * Thus the "-w- -> rw-" and "-wx -> rwx" mapping here (and in
 * arch/alpha/mm/fault.c)
 */
	/* xwr */

/*
 * pgprot_noncached() is only for infiniband pci support, and a real
 * implementation for RAM would be more complicated.
 */
#define pgprot_noncached(prot)	(prot)

/*
 * BAD_PAGETABLE is used when we need a bogus page-table, while
 * BAD_PAGE is used for a bogus page.
 *
 * ZERO_PAGE is a global shared page that is always zero:  used
 * for zero-mapped memory areas etc..
 */
extern pte_t __bad_page(void);
extern pmd_t * __bad_pagetable(void);

extern unsigned long __zero_page(void);

#define BAD_PAGETABLE	__bad_pagetable()
#define BAD_PAGE	__bad_page()
#define ZERO_PAGE(vaddr)	(virt_to_page(ZERO_PGE))

/* number of bits that fit into a memory pointer */
#define BITS_PER_PTR			(8*sizeof(unsigned long))

/* to align the pointer to a pointer address */
#define PTR_MASK			(~(sizeof(void*)-1))

/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
#define SIZEOF_PTR_LOG2			3

/* to find an entry in a page-table */
#define PAGE_PTR(address)		\
  ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)

/*
 * On certain platforms whose physical address space can overlap KSEG,
 * namely EV6 and above, we must re-twiddle the physaddr to restore the
 * correct high-order bits.
 *
 * This is extremely confusing until you realize that this is actually
 * just working around a userspace bug.  The X server was intending to
 * provide the physical address but instead provided the KSEG address.
 * Or tried to, except it's not representable.
 *
 * On Tsunami there's nothing meaningful at 0x40000000000, so this is
 * a safe thing to do.  Come the first core logic that does put something
 * in this area -- memory or whathaveyou -- then this hack will have
 * to go away.  So be prepared!
 */

#if defined(CONFIG_ALPHA_GENERIC) && defined(USE_48_BIT_KSEG)
#error "EV6-only feature in a generic kernel"
#endif
#if defined(CONFIG_ALPHA_GENERIC) || \
    (defined(CONFIG_ALPHA_EV6) && !defined(USE_48_BIT_KSEG))
#define KSEG_PFN	(0xc0000000000UL >> PAGE_SHIFT)
#define PHYS_TWIDDLE(pfn) \
  ((((pfn) & KSEG_PFN) == (0x40000000000UL >> PAGE_SHIFT)) \
  ? ((pfn) ^= KSEG_PFN) : (pfn))
#else
#define PHYS_TWIDDLE(pfn) (pfn)
#endif

/*
 * Conversion functions:  convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */
#define page_to_pa(page)	(page_to_pfn(page) << PAGE_SHIFT)
#define pte_pfn(pte)	(pte_val(pte) >> 32)

#define pte_page(pte)	pfn_to_page(pte_pfn(pte))
#define mk_pte(page, pgprot)						\
({									\
	pte_t pte;							\
									\
	pte_val(pte) = (page_to_pfn(page) << 32) | pgprot_val(pgprot);	\
	pte;								\
})

extern inline pte_t pfn_pte(unsigned long physpfn, pgprot_t pgprot)
{ pte_t pte; pte_val(pte) = (PHYS_TWIDDLE(physpfn) << 32) | pgprot_val(pgprot); return pte; }

extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }

extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
{ pmd_val(*pmdp) = _PAGE_TABLE | ((((unsigned long) ptep) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }

extern inline void pud_set(pud_t * pudp, pmd_t * pmdp)
{ pud_val(*pudp) = _PAGE_TABLE | ((((unsigned long) pmdp) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }

extern inline unsigned long
pmd_page_vaddr(pmd_t pmd)
{
	return ((pmd_val(pmd) & _PFN_MASK) >> (32-PAGE_SHIFT)) + PAGE_OFFSET;
}

#define pmd_pfn(pmd)	(pmd_val(pmd) >> 32)
#define pmd_page(pmd)	(pfn_to_page(pmd_val(pmd) >> 32))
#define pud_page(pud)	(pfn_to_page(pud_val(pud) >> 32))

extern inline pmd_t *pud_pgtable(pud_t pgd)
{
	return (pmd_t *)(PAGE_OFFSET + ((pud_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT)));
}

extern inline int pte_none(pte_t pte)		{ return !pte_val(pte); }
extern inline int pte_present(pte_t pte)	{ return pte_val(pte) & _PAGE_VALID; }
extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
	pte_val(*ptep) = 0;
}

extern inline int pmd_none(pmd_t pmd)		{ return !pmd_val(pmd); }
extern inline int pmd_bad(pmd_t pmd)		{ return (pmd_val(pmd) & ~_PFN_MASK) != _PAGE_TABLE; }
extern inline int pmd_present(pmd_t pmd)	{ return pmd_val(pmd) & _PAGE_VALID; }
extern inline void pmd_clear(pmd_t * pmdp)	{ pmd_val(*pmdp) = 0; }

extern inline int pud_none(pud_t pud)		{ return !pud_val(pud); }
extern inline int pud_bad(pud_t pud)		{ return (pud_val(pud) & ~_PFN_MASK) != _PAGE_TABLE; }
extern inline int pud_present(pud_t pud)	{ return pud_val(pud) & _PAGE_VALID; }
extern inline void pud_clear(pud_t * pudp)	{ pud_val(*pudp) = 0; }

/*
 * The following only work if pte_present() is true.
 * Undefined behaviour if not..
 */
extern inline int pte_write(pte_t pte)		{ return !(pte_val(pte) & _PAGE_FOW); }
extern inline int pte_dirty(pte_t pte)		{ return pte_val(pte) & _PAGE_DIRTY; }
extern inline int pte_young(pte_t pte)		{ return pte_val(pte) & _PAGE_ACCESSED; }

extern inline pte_t pte_wrprotect(pte_t pte)	{ pte_val(pte) |= _PAGE_FOW; return pte; }
extern inline pte_t pte_mkclean(pte_t pte)	{ pte_val(pte) &= ~(__DIRTY_BITS); return pte; }
extern inline pte_t pte_mkold(pte_t pte)	{ pte_val(pte) &= ~(__ACCESS_BITS); return pte; }
extern inline pte_t pte_mkwrite(pte_t pte)	{ pte_val(pte) &= ~_PAGE_FOW; return pte; }
extern inline pte_t pte_mkdirty(pte_t pte)	{ pte_val(pte) |= __DIRTY_BITS; return pte; }
extern inline pte_t pte_mkyoung(pte_t pte)	{ pte_val(pte) |= __ACCESS_BITS; return pte; }

/*
 * The smp_rmb() in the following functions are required to order the load of
 * *dir (the pointer in the top level page table) with any subsequent load of
 * the returned pmd_t *ret (ret is data dependent on *dir).
 *
 * If this ordering is not enforced, the CPU might load an older value of
 * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for
 * more details.
 *
 * Note that we never change the mm->pgd pointer after the task is running, so
 * pgd_offset does not require such a barrier.
 */

/* Find an entry in the second-level page table.. */
extern inline pmd_t * pmd_offset(pud_t * dir, unsigned long address)
{
	pmd_t *ret = pud_pgtable(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
	smp_rmb(); /* see above */
	return ret;
}
#define pmd_offset pmd_offset

/* Find an entry in the third-level page table.. */
extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address)
{
	pte_t *ret = (pte_t *) pmd_page_vaddr(*dir)
		+ ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
	smp_rmb(); /* see above */
	return ret;
}
#define pte_offset_kernel pte_offset_kernel

extern pgd_t swapper_pg_dir[1024];

/*
 * The Alpha doesn't have any external MMU info:  the kernel page
 * tables contain all the necessary information.
 */
extern inline void update_mmu_cache(struct vm_area_struct * vma,
	unsigned long address, pte_t *ptep)
{
}

/*
 * Non-present pages:  high 24 bits are offset, next 8 bits type,
 * low 32 bits zero.
 */
extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }

#define __swp_type(x)		(((x).val >> 32) & 0xff)
#define __swp_offset(x)		((x).val >> 40)
#define __swp_entry(type, off)	((swp_entry_t) { pte_val(mk_swap_pte((type), (off))) })
#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)	((pte_t) { (x).val })

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
#define pmd_ERROR(e) \
	printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))

extern void paging_init(void);

/* We have our own get_unmapped_area to cope with ADDR_LIMIT_32BIT.  */
#define HAVE_ARCH_UNMAPPED_AREA

#endif /* _ALPHA_PGTABLE_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * include/asm-alpha/processor.h
 *
 * Copyright (C) 1994 Linus Torvalds
 */

#ifndef __ASM_ALPHA_PROCESSOR_H
#define __ASM_ALPHA_PROCESSOR_H

#include <linux/personality.h>	/* for ADDR_LIMIT_32BIT */

/*
 * We have a 42-bit user address space: 4TB user VM...
 */
#define TASK_SIZE (0x40000000000UL)

#define STACK_TOP \
  (current->personality & ADDR_LIMIT_32BIT ? 0x80000000 : 0x00120000000UL)

#define STACK_TOP_MAX	0x00120000000UL

/* This decides where the kernel will search for a free chunk of vm
 * space during mmap's.
 */
#define TASK_UNMAPPED_BASE \
  ((current->personality & ADDR_LIMIT_32BIT) ? 0x40000000 : TASK_SIZE / 2)

/* This is dead.  Everything has been moved to thread_info.  */
struct thread_struct { };
#define INIT_THREAD  { }

/* Do necessary setup to start up a newly executed thread.  */
struct pt_regs;
extern void start_thread(struct pt_regs *, unsigned long, unsigned long);

/* Free all resources held by a thread. */
struct task_struct;
unsigned long __get_wchan(struct task_struct *p);

#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)

#define KSTK_ESP(tsk) \
  ((tsk) == current ? rdusp() : task_thread_info(tsk)->pcb.usp)

#define cpu_relax()	barrier()

#define ARCH_HAS_PREFETCH
#define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH

#ifndef CONFIG_SMP
/* Nothing to prefetch. */
#define spin_lock_prefetch(lock)  	do { } while (0)
#endif

extern inline void prefetch(const void *ptr)
{
	__builtin_prefetch(ptr, 0, 3);
}

extern inline void prefetchw(const void *ptr)
{
	__builtin_prefetch(ptr, 1, 3);
}

#ifdef CONFIG_SMP
extern inline void spin_lock_prefetch(const void *ptr)
{
	__builtin_prefetch(ptr, 1, 3);
}
#endif

#endif /* __ASM_ALPHA_PROCESSOR_H */

repo_name: angery/linux


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASMAXP_PTRACE_H
#define _ASMAXP_PTRACE_H

#include <uapi/asm/ptrace.h>

#define arch_has_single_step()		(1)
#define user_mode(regs) (((regs)->ps & 8) != 0)
#define instruction_pointer(regs) ((regs)->pc)
#define profile_pc(regs) instruction_pointer(regs)
#define current_user_stack_pointer() rdusp()

#define task_pt_regs(task) \
  ((struct pt_regs *) (task_stack_page(task) + 2*PAGE_SIZE) - 1)

#define current_pt_regs() \
  ((struct pt_regs *) ((char *)current_thread_info() + 2*PAGE_SIZE) - 1)

#define force_successful_syscall_return() (current_pt_regs()->r0 = 0)

static inline unsigned long regs_return_value(struct pt_regs *regs)
{
	return regs->r0;
}

#endif


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2019 Google LLC.
 */
#ifndef __ASM_RWONCE_H
#define __ASM_RWONCE_H

#ifdef CONFIG_SMP

#include <asm/barrier.h>

/*
 * Alpha is apparently daft enough to reorder address-dependent loads
 * on some CPU implementations. Knock some common sense into it with
 * a memory barrier in READ_ONCE().
 *
 * For the curious, more information about this unusual reordering is
 * available in chapter 15 of the "perfbook":
 *
 *  https://kernel.org/pub/linux/kernel/people/paulmck/perfbook/perfbook.html
 *
 */
#define __READ_ONCE(x)							\
({									\
	__unqual_scalar_typeof(x) __x =					\
		(*(volatile typeof(__x) *)(&(x)));			\
	mb();								\
	(typeof(x))__x;							\
})

#endif /* CONFIG_SMP */

#include <asm-generic/rwonce.h>

#endif /* __ASM_RWONCE_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * include/asm-alpha/serial.h
 */

/*
 * This assumes you have a 1.8432 MHz clock for your UART.
 *
 * It'd be nice if someone built a serial card with a 24.576 MHz
 * clock, since the 16550A is capable of handling a top speed of 1.5
 * megabits/second; but this requires the faster clock.
 */
#define BASE_BAUD ( 1843200 / 16 )

/* Standard COM flags (except for COM4, because of the 8514 problem) */
#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ)
#define STD_COM4_FLAGS (UPF_BOOT_AUTOCONF | UPF_AUTO_IRQ)
#else
#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
#define STD_COM4_FLAGS UPF_BOOT_AUTOCONF
#endif

#define SERIAL_PORT_DFNS			\
	/* UART CLK   PORT IRQ     FLAGS        */			\
	{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },	/* ttyS0 */	\
	{ 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },	/* ttyS1 */	\
	{ 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },	/* ttyS2 */	\
	{ 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },	/* ttyS3 */


code:
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __ALPHA_SETUP_H
#define __ALPHA_SETUP_H

#include <uapi/asm/setup.h>

/*
 * We leave one page for the initial stack page, and one page for
 * the initial process structure. Also, the console eats 3 MB for
 * the initial bootloader (one of which we can reclaim later).
 */
#define BOOT_PCB	0x20000000
#define BOOT_ADDR	0x20000000
/* Remove when official MILO sources have ELF support: */
#define BOOT_SIZE	(16*1024)

#ifdef CONFIG_ALPHA_LEGACY_START_ADDRESS
#define KERNEL_START_PHYS	0x300000 /* Old bootloaders hardcoded this.  */
#else
#define KERNEL_START_PHYS	0x1000000 /* required: Wildfire/Titan/Marvel */
#endif

#define KERNEL_START	(PAGE_OFFSET+KERNEL_START_PHYS)
#define SWAPPER_PGD	KERNEL_START
#define INIT_STACK	(PAGE_OFFSET+KERNEL_START_PHYS+0x02000)
#define EMPTY_PGT	(PAGE_OFFSET+KERNEL_START_PHYS+0x04000)
#define EMPTY_PGE	(PAGE_OFFSET+KERNEL_START_PHYS+0x08000)
#define ZERO_PGE	(PAGE_OFFSET+KERNEL_START_PHYS+0x0A000)

#define START_ADDR	(PAGE_OFFSET+KERNEL_START_PHYS+0x10000)

/*
 * This is setup by the secondary bootstrap loader.  Because
 * the zero page is zeroed out as soon as the vm system is
 * initialized, we need to copy things out into a more permanent
 * place.
 */
#define PARAM			ZERO_PGE
#define COMMAND_LINE		((char *)(absolute_pointer(PARAM + 0x0000)))
#define INITRD_START		(*(unsigned long *) (PARAM+0x100))
#define INITRD_SIZE		(*(unsigned long *) (PARAM+0x108))

#endif


code:
/* Machine-dependent software floating-point definitions.
   Alpha kernel version.
   Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
   This file is part of the GNU C Library.
   Contributed by Richard Henderson (rth@cygnus.com),
		  Jakub Jelinek (jakub@redhat.com) and
		  David S. Miller (davem@redhat.com).

   The GNU C Library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Library General Public License as
   published by the Free Software Foundation; either version 2 of the
   License, or (at your option) any later version.

   The GNU C Library is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   Library General Public License for more details.

   You should have received a copy of the GNU Library General Public
   License along with the GNU C Library; see the file COPYING.LIB.  If
   not, write to the Free Software Foundation, Inc.,
   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#ifndef _SFP_MACHINE_H
#define _SFP_MACHINE_H

#define _FP_W_TYPE_SIZE		64
#define _FP_W_TYPE		unsigned long
#define _FP_WS_TYPE		signed long
#define _FP_I_TYPE		long

#define _FP_MUL_MEAT_S(R,X,Y)					\
  _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y)
#define _FP_MUL_MEAT_D(R,X,Y)					\
  _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
#define _FP_MUL_MEAT_Q(R,X,Y)					\
  _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)

#define _FP_DIV_MEAT_S(R,X,Y)	_FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm)
#define _FP_DIV_MEAT_D(R,X,Y)	_FP_DIV_MEAT_1_udiv(D,R,X,Y)
#define _FP_DIV_MEAT_Q(R,X,Y)	_FP_DIV_MEAT_2_udiv(Q,R,X,Y)

#define _FP_NANFRAC_S		_FP_QNANBIT_S
#define _FP_NANFRAC_D		_FP_QNANBIT_D
#define _FP_NANFRAC_Q		_FP_QNANBIT_Q
#define _FP_NANSIGN_S		1
#define _FP_NANSIGN_D		1
#define _FP_NANSIGN_Q		1

#define _FP_KEEPNANFRACP 1

/* Alpha Architecture Handbook, 4.7.10.4 sais that
 * we should prefer any type of NaN in Fb, then Fa.
 */
#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)			\
  do {								\
    R##_s = Y##_s;						\
    _FP_FRAC_COPY_##wc(R,X);					\
    R##_c = FP_CLS_NAN;						\
  } while (0)

/* Obtain the current rounding mode. */
#define FP_ROUNDMODE	mode
#define FP_RND_NEAREST	(FPCR_DYN_NORMAL >> FPCR_DYN_SHIFT)
#define FP_RND_ZERO	(FPCR_DYN_CHOPPED >> FPCR_DYN_SHIFT)
#define FP_RND_PINF	(FPCR_DYN_PLUS >> FPCR_DYN_SHIFT)
#define FP_RND_MINF	(FPCR_DYN_MINUS >> FPCR_DYN_SHIFT)

/* Exception flags. */
#define FP_EX_INVALID		IEEE_TRAP_ENABLE_INV
#define FP_EX_OVERFLOW		IEEE_TRAP_ENABLE_OVF
#define FP_EX_UNDERFLOW		IEEE_TRAP_ENABLE_UNF
#define FP_EX_DIVZERO		IEEE_TRAP_ENABLE_DZE
#define FP_EX_INEXACT		IEEE_TRAP_ENABLE_INE
#define FP_EX_DENORM		IEEE_TRAP_ENABLE_DNO

#define FP_DENORM_ZERO		(swcr & IEEE_MAP_DMZ)

/* We write the results always */
#define FP_INHIBIT_RESULTS 0

#endif


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASMAXP_SHMPARAM_H
#define _ASMAXP_SHMPARAM_H

#define	SHMLBA PAGE_SIZE		 /* attach addr a multiple of this */

#endif /* _ASMAXP_SHMPARAM_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASMAXP_SIGNAL_H
#define _ASMAXP_SIGNAL_H

#include <uapi/asm/signal.h>

/* Digital Unix defines 64 signals.  Most things should be clean enough
   to redefine this at will, if care is taken to make libc match.  */

#define _NSIG		64
#define _NSIG_BPW	64
#define _NSIG_WORDS	(_NSIG / _NSIG_BPW)

typedef unsigned long old_sigset_t;		/* at least 32 bits */

typedef struct {
	unsigned long sig[_NSIG_WORDS];
} sigset_t;

struct osf_sigaction {
	__sighandler_t	sa_handler;
	old_sigset_t	sa_mask;
	int		sa_flags;
};

#define __ARCH_HAS_KA_RESTORER
#include <asm/sigcontext.h>
#endif


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_SMP_H
#define __ASM_SMP_H

#include <linux/threads.h>
#include <linux/cpumask.h>
#include <linux/bitops.h>
#include <asm/pal.h>

/* HACK: Cabrio WHAMI return value is bogus if more than 8 bits used.. :-( */

static __inline__ unsigned char
__hard_smp_processor_id(void)
{
	register unsigned char __r0 __asm__("$0");
	__asm__ __volatile__(
		"call_pal %1 #whami"
		: "=r"(__r0)
		:"i" (PAL_whami)
		: "$1", "$22", "$23", "$24", "$25");
	return __r0;
}

#ifdef CONFIG_SMP

#include <asm/irq.h>

struct cpuinfo_alpha {
	unsigned long loops_per_jiffy;
	unsigned long last_asn;
	int need_new_asn;
	int asn_lock;
	unsigned long ipi_count;
	unsigned long prof_multiplier;
	unsigned long prof_counter;
	unsigned char mcheck_expected;
	unsigned char mcheck_taken;
	unsigned char mcheck_extra;
} __attribute__((aligned(64)));

extern struct cpuinfo_alpha cpu_data[NR_CPUS];

#define hard_smp_processor_id()	__hard_smp_processor_id()
#define raw_smp_processor_id()	(current_thread_info()->cpu)

extern int smp_num_cpus;

extern void arch_send_call_function_single_ipi(int cpu);
extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);

#else /* CONFIG_SMP */

#define hard_smp_processor_id()		0
#define smp_call_function_on_cpu(func,info,wait,cpu)    ({ 0; })

#endif /* CONFIG_SMP */

#define NO_PROC_ID	(-1)

#endif


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_SOCKET_H
#define _ASM_SOCKET_H

#include <uapi/asm/socket.h>

/* O_NONBLOCK clashes with the bits used for socket types.  Therefore we
 * have to define SOCK_NONBLOCK to a different value here.
 */
#define SOCK_NONBLOCK	0x40000000
#endif /* _ASM_SOCKET_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_ALPHA_SPARSEMEM_H
#define _ASM_ALPHA_SPARSEMEM_H

#ifdef CONFIG_SPARSEMEM

#define SECTION_SIZE_BITS	27

/*
 * According to "Alpha Architecture Reference Manual" physical
 * addresses are at most 48 bits.
 * https://download.majix.org/dec/alpha_arch_ref.pdf
 */
#define MAX_PHYSMEM_BITS	48

#endif /* CONFIG_SPARSEMEM */

#endif /* _ASM_ALPHA_SPARSEMEM_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ALPHA_SPECIAL_INSNS_H
#define __ALPHA_SPECIAL_INSNS_H

enum implver_enum {
	IMPLVER_EV4,
	IMPLVER_EV5,
	IMPLVER_EV6
};

#ifdef CONFIG_ALPHA_GENERIC
#define implver()				\
({ unsigned long __implver;			\
   __asm__ ("implver %0" : "=r"(__implver));	\
   (enum implver_enum) __implver; })
#else
/* Try to eliminate some dead code.  */
#ifdef CONFIG_ALPHA_EV4
#define implver() IMPLVER_EV4
#endif
#ifdef CONFIG_ALPHA_EV5
#define implver() IMPLVER_EV5
#endif
#if defined(CONFIG_ALPHA_EV6)
#define implver() IMPLVER_EV6
#endif
#endif

enum amask_enum {
	AMASK_BWX = (1UL << 0),
	AMASK_FIX = (1UL << 1),
	AMASK_CIX = (1UL << 2),
	AMASK_MAX = (1UL << 8),
	AMASK_PRECISE_TRAP = (1UL << 9),
};

#define amask(mask)						\
({ unsigned long __amask, __input = (mask);			\
   __asm__ ("amask %1,%0" : "=r"(__amask) : "rI"(__input));	\
   __amask; })

#endif /* __ALPHA_SPECIAL_INSNS_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ALPHA_SPINLOCK_H
#define _ALPHA_SPINLOCK_H

#include <linux/kernel.h>
#include <asm/current.h>
#include <asm/barrier.h>
#include <asm/processor.h>

/*
 * Simple spin lock operations.  There are two variants, one clears IRQ's
 * on the local processor, one does not.
 *
 * We make no fairness assumptions. They have a cost.
 */

#define arch_spin_is_locked(x)	((x)->lock != 0)

static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
{
        return lock.lock == 0;
}

static inline void arch_spin_unlock(arch_spinlock_t * lock)
{
	mb();
	lock->lock = 0;
}

static inline void arch_spin_lock(arch_spinlock_t * lock)
{
	long tmp;

	__asm__ __volatile__(
	"1:	ldl_l	%0,%1\n"
	"	bne	%0,2f\n"
	"	lda	%0,1\n"
	"	stl_c	%0,%1\n"
	"	beq	%0,2f\n"
	"	mb\n"
	".subsection 2\n"
	"2:	ldl	%0,%1\n"
	"	bne	%0,2b\n"
	"	br	1b\n"
	".previous"
	: "=&r" (tmp), "=m" (lock->lock)
	: "m"(lock->lock) : "memory");
}

static inline int arch_spin_trylock(arch_spinlock_t *lock)
{
	return !test_and_set_bit(0, &lock->lock);
}

/***********************************************************/

static inline void arch_read_lock(arch_rwlock_t *lock)
{
	long regx;

	__asm__ __volatile__(
	"1:	ldl_l	%1,%0\n"
	"	blbs	%1,6f\n"
	"	subl	%1,2,%1\n"
	"	stl_c	%1,%0\n"
	"	beq	%1,6f\n"
	"	mb\n"
	".subsection 2\n"
	"6:	ldl	%1,%0\n"
	"	blbs	%1,6b\n"
	"	br	1b\n"
	".previous"
	: "=m" (*lock), "=&r" (regx)
	: "m" (*lock) : "memory");
}

static inline void arch_write_lock(arch_rwlock_t *lock)
{
	long regx;

	__asm__ __volatile__(
	"1:	ldl_l	%1,%0\n"
	"	bne	%1,6f\n"
	"	lda	%1,1\n"
	"	stl_c	%1,%0\n"
	"	beq	%1,6f\n"
	"	mb\n"
	".subsection 2\n"
	"6:	ldl	%1,%0\n"
	"	bne	%1,6b\n"
	"	br	1b\n"
	".previous"
	: "=m" (*lock), "=&r" (regx)
	: "m" (*lock) : "memory");
}

static inline int arch_read_trylock(arch_rwlock_t * lock)
{
	long regx;
	int success;

	__asm__ __volatile__(
	"1:	ldl_l	%1,%0\n"
	"	lda	%2,0\n"
	"	blbs	%1,2f\n"
	"	subl	%1,2,%2\n"
	"	stl_c	%2,%0\n"
	"	beq	%2,6f\n"
	"2:	mb\n"
	".subsection 2\n"
	"6:	br	1b\n"
	".previous"
	: "=m" (*lock), "=&r" (regx), "=&r" (success)
	: "m" (*lock) : "memory");

	return success;
}

static inline int arch_write_trylock(arch_rwlock_t * lock)
{
	long regx;
	int success;

	__asm__ __volatile__(
	"1:	ldl_l	%1,%0\n"
	"	lda	%2,0\n"
	"	bne	%1,2f\n"
	"	lda	%2,1\n"
	"	stl_c	%2,%0\n"
	"	beq	%2,6f\n"
	"2:	mb\n"
	".subsection 2\n"
	"6:	br	1b\n"
	".previous"
	: "=m" (*lock), "=&r" (regx), "=&r" (success)
	: "m" (*lock) : "memory");

	return success;
}

static inline void arch_read_unlock(arch_rwlock_t * lock)
{
	long regx;
	__asm__ __volatile__(
	"	mb\n"
	"1:	ldl_l	%1,%0\n"
	"	addl	%1,2,%1\n"
	"	stl_c	%1,%0\n"
	"	beq	%1,6f\n"
	".subsection 2\n"
	"6:	br	1b\n"
	".previous"
	: "=m" (*lock), "=&r" (regx)
	: "m" (*lock) : "memory");
}

static inline void arch_write_unlock(arch_rwlock_t * lock)
{
	mb();
	lock->lock = 0;
}

#endif /* _ALPHA_SPINLOCK_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ALPHA_SPINLOCK_TYPES_H
#define _ALPHA_SPINLOCK_TYPES_H

#ifndef __LINUX_SPINLOCK_TYPES_RAW_H
# error "please don't include this file directly"
#endif

typedef struct {
	volatile unsigned int lock;
} arch_spinlock_t;

#define __ARCH_SPIN_LOCK_UNLOCKED	{ 0 }

typedef struct {
	volatile unsigned int lock;
} arch_rwlock_t;

#define __ARCH_RW_LOCK_UNLOCKED		{ 0 }

#endif


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ALPHA_STRING_H__
#define __ALPHA_STRING_H__

#ifdef __KERNEL__

/*
 * GCC of any recent vintage doesn't do stupid things with bcopy.
 * EGCS 1.1 knows all about expanding memcpy inline, others don't.
 *
 * Similarly for a memset with data = 0.
 */

#define __HAVE_ARCH_MEMCPY
extern void * memcpy(void *, const void *, size_t);
#define __HAVE_ARCH_MEMMOVE
extern void * memmove(void *, const void *, size_t);

/* For backward compatibility with modules.  Unused otherwise.  */
extern void * __memcpy(void *, const void *, size_t);

#define memcpy __builtin_memcpy

#define __HAVE_ARCH_MEMSET
extern void * __constant_c_memset(void *, unsigned long, size_t);
extern void * ___memset(void *, int, size_t);
extern void * __memset(void *, int, size_t);
extern void * memset(void *, int, size_t);

/* For gcc 3.x, we cannot have the inline function named "memset" because
   the __builtin_memset will attempt to resolve to the inline as well,
   leading to a "sorry" about unimplemented recursive inlining.  */
extern inline void *__memset(void *s, int c, size_t n)
{
	if (__builtin_constant_p(c)) {
		if (__builtin_constant_p(n)) {
			return __builtin_memset(s, c, n);
		} else {
			unsigned long c8 = (c & 0xff) * 0x0101010101010101UL;
			return __constant_c_memset(s, c8, n);
		}
	}
	return ___memset(s, c, n);
}

#define memset __memset

#define __HAVE_ARCH_STRCPY
extern char * strcpy(char *,const char *);
#define __HAVE_ARCH_STRNCPY
extern char * strncpy(char *, const char *, size_t);
#define __HAVE_ARCH_STRCAT
extern char * strcat(char *, const char *);
#define __HAVE_ARCH_STRNCAT
extern char * strncat(char *, const char *, size_t);
#define __HAVE_ARCH_STRCHR
extern char * strchr(const char *,int);
#define __HAVE_ARCH_STRRCHR
extern char * strrchr(const char *,int);
#define __HAVE_ARCH_STRLEN
extern size_t strlen(const char *);
#define __HAVE_ARCH_MEMCHR
extern void * memchr(const void *, int, size_t);

/* The following routine is like memset except that it writes 16-bit
   aligned values.  The DEST and COUNT parameters must be even for
   correct operation.  */

#define __HAVE_ARCH_MEMSET16
extern void * __memset16(void *dest, unsigned short, size_t count);
static inline void *memset16(uint16_t *p, uint16_t v, size_t n)
{
	if (__builtin_constant_p(v))
		return __constant_c_memset(p, 0x0001000100010001UL * v, n * 2);
	return __memset16(p, v, n * 2);
}

#endif /* __KERNEL__ */

#endif /* __ALPHA_STRING_H__ */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ALPHA_SWITCH_TO_H
#define __ALPHA_SWITCH_TO_H

struct task_struct;
extern struct task_struct *alpha_switch_to(unsigned long, struct task_struct *);

#define switch_to(P,N,L)						 \
  do {									 \
    (L) = alpha_switch_to(virt_to_phys(&task_thread_info(N)->pcb), (P)); \
    check_mmu_context();						 \
  } while (0)

#endif /* __ALPHA_SWITCH_TO_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_ALPHA_SYSCALL_H
#define _ASM_ALPHA_SYSCALL_H

#include <uapi/linux/audit.h>

static inline int syscall_get_arch(struct task_struct *task)
{
	return AUDIT_ARCH_ALPHA;
}

static inline long syscall_get_return_value(struct task_struct *task,
					    struct pt_regs *regs)
{
	return regs->r0;
}

#endif	/* _ASM_ALPHA_SYSCALL_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ALPHA_THREAD_INFO_H
#define _ALPHA_THREAD_INFO_H

#ifdef __KERNEL__

#ifndef __ASSEMBLY__
#include <asm/processor.h>
#include <asm/types.h>
#include <asm/hwrpb.h>
#include <asm/sysinfo.h>
#endif

#ifndef __ASSEMBLY__
struct thread_info {
	struct pcb_struct	pcb;		/* palcode state */

	struct task_struct	*task;		/* main task structure */
	unsigned int		flags;		/* low level flags */
	unsigned int		ieee_state;	/* see fpu.h */

	unsigned		cpu;		/* current CPU */
	int			preempt_count; /* 0 => preemptable, <0 => BUG */
	unsigned int		status;		/* thread-synchronous flags */

	int bpt_nsaved;
	unsigned long bpt_addr[2];		/* breakpoint handling  */
	unsigned int bpt_insn[2];
};

/*
 * Macros/functions for gaining access to the thread information structure.
 */
#define INIT_THREAD_INFO(tsk)			\
{						\
	.task		= &tsk,			\
	.preempt_count	= INIT_PREEMPT_COUNT,	\
}

/* How to get the thread information struct from C.  */
register struct thread_info *__current_thread_info __asm__("$8");
#define current_thread_info()  __current_thread_info

#endif /* __ASSEMBLY__ */

/* Thread information allocation.  */
#define THREAD_SIZE_ORDER 1
#define THREAD_SIZE (2*PAGE_SIZE)

/*
 * Thread information flags:
 * - these are process state flags and used from assembly
 * - pending work-to-be-done flags come first and must be assigned to be
 *   within bits 0 to 7 to fit in and immediate operand.
 *
 * TIF_SYSCALL_TRACE is known to be 0 via blbs.
 */
#define TIF_SYSCALL_TRACE	0	/* syscall trace active */
#define TIF_NOTIFY_RESUME	1	/* callback before returning to user */
#define TIF_SIGPENDING		2	/* signal pending */
#define TIF_NEED_RESCHED	3	/* rescheduling necessary */
#define TIF_SYSCALL_AUDIT	4	/* syscall audit active */
#define TIF_NOTIFY_SIGNAL	5	/* signal notifications exist */
#define TIF_DIE_IF_KERNEL	9	/* dik recursion lock */
#define TIF_MEMDIE		13	/* is terminating due to OOM killer */
#define TIF_POLLING_NRFLAG	14	/* idle is polling for TIF_NEED_RESCHED */

#define _TIF_SYSCALL_TRACE	(1<<TIF_SYSCALL_TRACE)
#define _TIF_SIGPENDING		(1<<TIF_SIGPENDING)
#define _TIF_NEED_RESCHED	(1<<TIF_NEED_RESCHED)
#define _TIF_NOTIFY_RESUME	(1<<TIF_NOTIFY_RESUME)
#define _TIF_SYSCALL_AUDIT	(1<<TIF_SYSCALL_AUDIT)
#define _TIF_NOTIFY_SIGNAL	(1<<TIF_NOTIFY_SIGNAL)
#define _TIF_POLLING_NRFLAG	(1<<TIF_POLLING_NRFLAG)

/* Work to do on interrupt/exception return.  */
#define _TIF_WORK_MASK		(_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
				 _TIF_NOTIFY_RESUME | _TIF_NOTIFY_SIGNAL)

#define TS_UAC_NOPRINT		0x0001	/* ! Preserve the following three */
#define TS_UAC_NOFIX		0x0002	/* ! flags as they match          */
#define TS_UAC_SIGBUS		0x0004	/* ! userspace part of 'osf_sysinfo' */

#define SET_UNALIGN_CTL(task,value)	({				\
	__u32 status = task_thread_info(task)->status & ~UAC_BITMASK;	\
	if (value & PR_UNALIGN_NOPRINT)					\
		status |= TS_UAC_NOPRINT;				\
	if (value & PR_UNALIGN_SIGBUS)					\
		status |= TS_UAC_SIGBUS;				\
	if (value & 4)	/* alpha-specific */				\
		status |= TS_UAC_NOFIX;					\
	task_thread_info(task)->status = status;			\
	0; })

#define GET_UNALIGN_CTL(task,value)	({				\
	__u32 status = task_thread_info(task)->status & ~UAC_BITMASK;	\
	__u32 res = 0;							\
	if (status & TS_UAC_NOPRINT)					\
		res |= PR_UNALIGN_NOPRINT;				\
	if (status & TS_UAC_SIGBUS)					\
		res |= PR_UNALIGN_SIGBUS;				\
	if (status & TS_UAC_NOFIX)					\
		res |= 4;						\
	put_user(res, (int __user *)(value));				\
	})

#endif /* __KERNEL__ */
#endif /* _ALPHA_THREAD_INFO_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * linux/include/asm-alpha/timex.h
 *
 * ALPHA architecture timex specifications
 */
#ifndef _ASMALPHA_TIMEX_H
#define _ASMALPHA_TIMEX_H

/* With only one or two oddballs, we use the RTC as the ticker, selecting
   the 32.768kHz reference clock, which nicely divides down to our HZ.  */
#define CLOCK_TICK_RATE	32768

/*
 * Standard way to access the cycle counter.
 * Currently only used on SMP for scheduling.
 *
 * Only the low 32 bits are available as a continuously counting entity.
 * But this only means we'll force a reschedule every 8 seconds or so,
 * which isn't an evil thing.
 */

typedef unsigned int cycles_t;

static inline cycles_t get_cycles (void)
{
	cycles_t ret;
	__asm__ __volatile__ ("rpcc %0" : "=r"(ret));
	return ret;
}
#define get_cycles get_cycles

#endif


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ALPHA_TLB_H
#define _ALPHA_TLB_H

#include <asm-generic/tlb.h>

#define __pte_free_tlb(tlb, pte, address)		pte_free((tlb)->mm, pte)
#define __pmd_free_tlb(tlb, pmd, address)		pmd_free((tlb)->mm, pmd)

#endif


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ALPHA_TLBFLUSH_H
#define _ALPHA_TLBFLUSH_H

#include <linux/mm.h>
#include <linux/sched.h>
#include <asm/compiler.h>

#ifndef __EXTERN_INLINE
#define __EXTERN_INLINE extern inline
#define __MMU_EXTERN_INLINE
#endif

extern void __load_new_mm_context(struct mm_struct *);

/* Use a few helper functions to hide the ugly broken ASN
   numbers on early Alphas (ev4 and ev45).  */

__EXTERN_INLINE void
ev4_flush_tlb_current(struct mm_struct *mm)
{
	__load_new_mm_context(mm);
	tbiap();
}

__EXTERN_INLINE void
ev5_flush_tlb_current(struct mm_struct *mm)
{
	__load_new_mm_context(mm);
}

/* Flush just one page in the current TLB set.  We need to be very
   careful about the icache here, there is no way to invalidate a
   specific icache page.  */

__EXTERN_INLINE void
ev4_flush_tlb_current_page(struct mm_struct * mm,
			   struct vm_area_struct *vma,
			   unsigned long addr)
{
	int tbi_flag = 2;
	if (vma->vm_flags & VM_EXEC) {
		__load_new_mm_context(mm);
		tbi_flag = 3;
	}
	tbi(tbi_flag, addr);
}

__EXTERN_INLINE void
ev5_flush_tlb_current_page(struct mm_struct * mm,
			   struct vm_area_struct *vma,
			   unsigned long addr)
{
	if (vma->vm_flags & VM_EXEC)
		__load_new_mm_context(mm);
	else
		tbi(2, addr);
}

#ifdef CONFIG_ALPHA_GENERIC
# define flush_tlb_current		alpha_mv.mv_flush_tlb_current
# define flush_tlb_current_page		alpha_mv.mv_flush_tlb_current_page
#else
# ifdef CONFIG_ALPHA_EV4
#  define flush_tlb_current		ev4_flush_tlb_current
#  define flush_tlb_current_page	ev4_flush_tlb_current_page
# else
#  define flush_tlb_current		ev5_flush_tlb_current
#  define flush_tlb_current_page	ev5_flush_tlb_current_page
# endif
#endif

#ifdef __MMU_EXTERN_INLINE
#undef __EXTERN_INLINE
#undef __MMU_EXTERN_INLINE
#endif

/* Flush current user mapping.  */
static inline void
flush_tlb(void)
{
	flush_tlb_current(current->active_mm);
}

/* Flush someone else's user mapping.  */
static inline void
flush_tlb_other(struct mm_struct *mm)
{
	unsigned long *mmc = &mm->context[smp_processor_id()];
	/* Check it's not zero first to avoid cacheline ping pong
	   when possible.  */
	if (*mmc) *mmc = 0;
}

#ifndef CONFIG_SMP
/* Flush everything (kernel mapping may also have changed
   due to vmalloc/vfree).  */
static inline void flush_tlb_all(void)
{
	tbia();
}

/* Flush a specified user mapping.  */
static inline void
flush_tlb_mm(struct mm_struct *mm)
{
	if (mm == current->active_mm)
		flush_tlb_current(mm);
	else
		flush_tlb_other(mm);
}

/* Page-granular tlb flush.  */
static inline void
flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
{
	struct mm_struct *mm = vma->vm_mm;

	if (mm == current->active_mm)
		flush_tlb_current_page(mm, vma, addr);
	else
		flush_tlb_other(mm);
}

/* Flush a specified range of user mapping.  On the Alpha we flush
   the whole user tlb.  */
static inline void
flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
		unsigned long end)
{
	flush_tlb_mm(vma->vm_mm);
}

#else /* CONFIG_SMP */

extern void flush_tlb_all(void);
extern void flush_tlb_mm(struct mm_struct *);
extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
extern void flush_tlb_range(struct vm_area_struct *, unsigned long,
			    unsigned long);

#endif /* CONFIG_SMP */

static inline void flush_tlb_kernel_range(unsigned long start,
					unsigned long end)
{
	flush_tlb_all();
}

#endif /* _ALPHA_TLBFLUSH_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_ALPHA_TOPOLOGY_H
#define _ASM_ALPHA_TOPOLOGY_H

#include <linux/smp.h>
#include <linux/threads.h>
#include <linux/numa.h>
#include <asm/machvec.h>

# include <asm-generic/topology.h>

#endif /* _ASM_ALPHA_TOPOLOGY_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ALPHA_TYPES_H
#define _ALPHA_TYPES_H

#include <uapi/asm/types.h>

#endif /* _ALPHA_TYPES_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ALPHA_UACCESS_H
#define __ALPHA_UACCESS_H

#include <asm-generic/access_ok.h>
/*
 * These are the main single-value transfer routines.  They automatically
 * use the right size if we just have the right pointer type.
 *
 * As the alpha uses the same address space for kernel and user
 * data, we can just do these as direct assignments.  (Of course, the
 * exception handling means that it's no longer "just"...)
 *
 * Careful to not
 * (a) re-use the arguments for side effects (sizeof/typeof is ok)
 * (b) require any knowledge of processes at this stage
 */
#define put_user(x, ptr) \
  __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
#define get_user(x, ptr) \
  __get_user_check((x), (ptr), sizeof(*(ptr)))

/*
 * The "__xxx" versions do not do address space checking, useful when
 * doing multiple accesses to the same area (the programmer has to do the
 * checks by hand with "access_ok()")
 */
#define __put_user(x, ptr) \
  __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
#define __get_user(x, ptr) \
  __get_user_nocheck((x), (ptr), sizeof(*(ptr)))

/*
 * The "lda %1, 2b-1b(%0)" bits are magic to get the assembler to
 * encode the bits we need for resolving the exception.  See the
 * more extensive comments with fixup_inline_exception below for
 * more information.
 */
#define EXC(label,cont,res,err)				\
	".section __ex_table,\"a\"\n"			\
	"	.long "#label"-.\n"			\
	"	lda "#res","#cont"-"#label"("#err")\n"	\
	".previous\n"

extern void __get_user_unknown(void);

#define __get_user_nocheck(x, ptr, size)			\
({								\
	long __gu_err = 0;					\
	unsigned long __gu_val;					\
	__chk_user_ptr(ptr);					\
	switch (size) {						\
	  case 1: __get_user_8(ptr); break;			\
	  case 2: __get_user_16(ptr); break;			\
	  case 4: __get_user_32(ptr); break;			\
	  case 8: __get_user_64(ptr); break;			\
	  default: __get_user_unknown(); break;			\
	}							\
	(x) = (__force __typeof__(*(ptr))) __gu_val;		\
	__gu_err;						\
})

#define __get_user_check(x, ptr, size)				\
({								\
	long __gu_err = -EFAULT;				\
	unsigned long __gu_val = 0;				\
	const __typeof__(*(ptr)) __user *__gu_addr = (ptr);	\
	if (__access_ok(__gu_addr, size)) {			\
		__gu_err = 0;					\
		switch (size) {					\
		  case 1: __get_user_8(__gu_addr); break;	\
		  case 2: __get_user_16(__gu_addr); break;	\
		  case 4: __get_user_32(__gu_addr); break;	\
		  case 8: __get_user_64(__gu_addr); break;	\
		  default: __get_user_unknown(); break;		\
		}						\
	}							\
	(x) = (__force __typeof__(*(ptr))) __gu_val;		\
	__gu_err;						\
})

struct __large_struct { unsigned long buf[100]; };
#define __m(x) (*(struct __large_struct __user *)(x))

#define __get_user_64(addr)				\
	__asm__("1: ldq %0,%2\n"			\
	"2:\n"						\
	EXC(1b,2b,%0,%1)				\
		: "=r"(__gu_val), "=r"(__gu_err)	\
		: "m"(__m(addr)), "1"(__gu_err))

#define __get_user_32(addr)				\
	__asm__("1: ldl %0,%2\n"			\
	"2:\n"						\
	EXC(1b,2b,%0,%1)				\
		: "=r"(__gu_val), "=r"(__gu_err)	\
		: "m"(__m(addr)), "1"(__gu_err))

#ifdef __alpha_bwx__
/* Those lucky bastards with ev56 and later CPUs can do byte/word moves.  */

#define __get_user_16(addr)				\
	__asm__("1: ldwu %0,%2\n"			\
	"2:\n"						\
	EXC(1b,2b,%0,%1)				\
		: "=r"(__gu_val), "=r"(__gu_err)	\
		: "m"(__m(addr)), "1"(__gu_err))

#define __get_user_8(addr)				\
	__asm__("1: ldbu %0,%2\n"			\
	"2:\n"						\
	EXC(1b,2b,%0,%1)				\
		: "=r"(__gu_val), "=r"(__gu_err)	\
		: "m"(__m(addr)), "1"(__gu_err))
#else
/* Unfortunately, we can't get an unaligned access trap for the sub-word
   load, so we have to do a general unaligned operation.  */

#define __get_user_16(addr)						\
{									\
	long __gu_tmp;							\
	__asm__("1: ldq_u %0,0(%3)\n"					\
	"2:	ldq_u %1,1(%3)\n"					\
	"	extwl %0,%3,%0\n"					\
	"	extwh %1,%3,%1\n"					\
	"	or %0,%1,%0\n"						\
	"3:\n"								\
	EXC(1b,3b,%0,%2)						\
	EXC(2b,3b,%0,%2)						\
		: "=&r"(__gu_val), "=&r"(__gu_tmp), "=r"(__gu_err)	\
		: "r"(addr), "2"(__gu_err));				\
}

#define __get_user_8(addr)						\
	__asm__("1: ldq_u %0,0(%2)\n"					\
	"	extbl %0,%2,%0\n"					\
	"2:\n"								\
	EXC(1b,2b,%0,%1)						\
		: "=&r"(__gu_val), "=r"(__gu_err)			\
		: "r"(addr), "1"(__gu_err))
#endif

extern void __put_user_unknown(void);

#define __put_user_nocheck(x, ptr, size)			\
({								\
	long __pu_err = 0;					\
	__chk_user_ptr(ptr);					\
	switch (size) {						\
	  case 1: __put_user_8(x, ptr); break;			\
	  case 2: __put_user_16(x, ptr); break;			\
	  case 4: __put_user_32(x, ptr); break;			\
	  case 8: __put_user_64(x, ptr); break;			\
	  default: __put_user_unknown(); break;			\
	}							\
	__pu_err;						\
})

#define __put_user_check(x, ptr, size)				\
({								\
	long __pu_err = -EFAULT;				\
	__typeof__(*(ptr)) __user *__pu_addr = (ptr);		\
	if (__access_ok(__pu_addr, size)) {			\
		__pu_err = 0;					\
		switch (size) {					\
		  case 1: __put_user_8(x, __pu_addr); break;	\
		  case 2: __put_user_16(x, __pu_addr); break;	\
		  case 4: __put_user_32(x, __pu_addr); break;	\
		  case 8: __put_user_64(x, __pu_addr); break;	\
		  default: __put_user_unknown(); break;		\
		}						\
	}							\
	__pu_err;						\
})

/*
 * The "__put_user_xx()" macros tell gcc they read from memory
 * instead of writing: this is because they do not write to
 * any memory gcc knows about, so there are no aliasing issues
 */
#define __put_user_64(x, addr)					\
__asm__ __volatile__("1: stq %r2,%1\n"				\
	"2:\n"							\
	EXC(1b,2b,$31,%0)					\
		: "=r"(__pu_err)				\
		: "m" (__m(addr)), "rJ" (x), "0"(__pu_err))

#define __put_user_32(x, addr)					\
__asm__ __volatile__("1: stl %r2,%1\n"				\
	"2:\n"							\
	EXC(1b,2b,$31,%0)					\
		: "=r"(__pu_err)				\
		: "m"(__m(addr)), "rJ"(x), "0"(__pu_err))

#ifdef __alpha_bwx__
/* Those lucky bastards with ev56 and later CPUs can do byte/word moves.  */

#define __put_user_16(x, addr)					\
__asm__ __volatile__("1: stw %r2,%1\n"				\
	"2:\n"							\
	EXC(1b,2b,$31,%0)					\
		: "=r"(__pu_err)				\
		: "m"(__m(addr)), "rJ"(x), "0"(__pu_err))

#define __put_user_8(x, addr)					\
__asm__ __volatile__("1: stb %r2,%1\n"				\
	"2:\n"							\
	EXC(1b,2b,$31,%0)					\
		: "=r"(__pu_err)				\
		: "m"(__m(addr)), "rJ"(x), "0"(__pu_err))
#else
/* Unfortunately, we can't get an unaligned access trap for the sub-word
   write, so we have to do a general unaligned operation.  */

#define __put_user_16(x, addr)					\
{								\
	long __pu_tmp1, __pu_tmp2, __pu_tmp3, __pu_tmp4;	\
	__asm__ __volatile__(					\
	"1:	ldq_u %2,1(%5)\n"				\
	"2:	ldq_u %1,0(%5)\n"				\
	"	inswh %6,%5,%4\n"				\
	"	inswl %6,%5,%3\n"				\
	"	mskwh %2,%5,%2\n"				\
	"	mskwl %1,%5,%1\n"				\
	"	or %2,%4,%2\n"					\
	"	or %1,%3,%1\n"					\
	"3:	stq_u %2,1(%5)\n"				\
	"4:	stq_u %1,0(%5)\n"				\
	"5:\n"							\
	EXC(1b,5b,$31,%0)					\
	EXC(2b,5b,$31,%0)					\
	EXC(3b,5b,$31,%0)					\
	EXC(4b,5b,$31,%0)					\
		: "=r"(__pu_err), "=&r"(__pu_tmp1), 		\
		  "=&r"(__pu_tmp2), "=&r"(__pu_tmp3), 		\
		  "=&r"(__pu_tmp4)				\
		: "r"(addr), "r"((unsigned long)(x)), "0"(__pu_err)); \
}

#define __put_user_8(x, addr)					\
{								\
	long __pu_tmp1, __pu_tmp2;				\
	__asm__ __volatile__(					\
	"1:	ldq_u %1,0(%4)\n"				\
	"	insbl %3,%4,%2\n"				\
	"	mskbl %1,%4,%1\n"				\
	"	or %1,%2,%1\n"					\
	"2:	stq_u %1,0(%4)\n"				\
	"3:\n"							\
	EXC(1b,3b,$31,%0)					\
	EXC(2b,3b,$31,%0)					\
		: "=r"(__pu_err), 				\
	  	  "=&r"(__pu_tmp1), "=&r"(__pu_tmp2)		\
		: "r"((unsigned long)(x)), "r"(addr), "0"(__pu_err)); \
}
#endif

/*
 * Complex access routines
 */

extern long __copy_user(void *to, const void *from, long len);

static inline unsigned long
raw_copy_from_user(void *to, const void __user *from, unsigned long len)
{
	return __copy_user(to, (__force const void *)from, len);
}

static inline unsigned long
raw_copy_to_user(void __user *to, const void *from, unsigned long len)
{
	return __copy_user((__force void *)to, from, len);
}

extern long __clear_user(void __user *to, long len);

static inline long
clear_user(void __user *to, long len)
{
	if (__access_ok(to, len))
		len = __clear_user(to, len);
	return len;
}

extern long strncpy_from_user(char *dest, const char __user *src, long count);
extern __must_check long strnlen_user(const char __user *str, long n);

#include <asm/extable.h>

#endif /* __ALPHA_UACCESS_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASMAXP_UCONTEXT_H
#define _ASMAXP_UCONTEXT_H

struct ucontext {
	unsigned long	  uc_flags;
	struct ucontext  *uc_link;
	old_sigset_t	  uc_osf_sigmask;
	stack_t		  uc_stack;
	struct sigcontext uc_mcontext;
	sigset_t	  uc_sigmask;	/* mask last for extensibility */
};

#endif /* !_ASMAXP_UCONTEXT_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ALPHA_UNISTD_H
#define _ALPHA_UNISTD_H

#include <uapi/asm/unistd.h>

#define NR_SYSCALLS	__NR_syscalls

#define __ARCH_WANT_NEW_STAT
#define __ARCH_WANT_OLD_READDIR
#define __ARCH_WANT_STAT64
#define __ARCH_WANT_SYS_GETHOSTNAME
#define __ARCH_WANT_SYS_FADVISE64
#define __ARCH_WANT_SYS_GETPGRP
#define __ARCH_WANT_SYS_OLDUMOUNT
#define __ARCH_WANT_SYS_SIGPENDING
#define __ARCH_WANT_SYS_UTIME
#define __ARCH_WANT_SYS_FORK
#define __ARCH_WANT_SYS_VFORK
#define __ARCH_WANT_SYS_CLONE

#endif /* _ALPHA_UNISTD_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ALPHA_USER_H
#define _ALPHA_USER_H

#include <linux/sched.h>
#include <linux/ptrace.h>

#include <asm/page.h>
#include <asm/reg.h>

/*
 * Core file format: The core file is written in such a way that gdb
 * can understand it and provide useful information to the user (under
 * linux we use the `trad-core' bfd, NOT the osf-core).  The file contents
 * are as follows:
 *
 *  upage: 1 page consisting of a user struct that tells gdb
 *	what is present in the file.  Directly after this is a
 *	copy of the task_struct, which is currently not used by gdb,
 *	but it may come in handy at some point.  All of the registers
 *	are stored as part of the upage.  The upage should always be
 *	only one page long.
 *  data: The data segment follows next.  We use current->end_text to
 *	current->brk to pick up all of the user variables, plus any memory
 *	that may have been sbrk'ed.  No attempt is made to determine if a
 *	page is demand-zero or if a page is totally unused, we just cover
 *	the entire range.  All of the addresses are rounded in such a way
 *	that an integral number of pages is written.
 *  stack: We need the stack information in order to get a meaningful
 *	backtrace.  We need to write the data from usp to
 *	current->start_stack, so we round each of these in order to be able
 *	to write an integer number of pages.
 */
struct user {
	unsigned long	regs[EF_SIZE/8+32];	/* integer and fp regs */
	size_t		u_tsize;		/* text size (pages) */
	size_t		u_dsize;		/* data size (pages) */
	size_t		u_ssize;		/* stack size (pages) */
	unsigned long	start_code;		/* text starting address */
	unsigned long	start_data;		/* data starting address */
	unsigned long	start_stack;		/* stack starting address */
	long int	signal;			/* signal causing core dump */
	unsigned long	u_ar0;			/* help gdb find registers */
	unsigned long	magic;			/* identifies a core file */
	char		u_comm[32];		/* user command name */
};

#endif /* _ALPHA_USER_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 *	Access to VGA videoram
 *
 *	(c) 1998 Martin Mares <mj@ucw.cz>
 */

#ifndef _LINUX_ASM_VGA_H_
#define _LINUX_ASM_VGA_H_

#include <asm/io.h>

#define VT_BUF_HAVE_RW
#define VT_BUF_HAVE_MEMSETW
#define VT_BUF_HAVE_MEMCPYW

static inline void scr_writew(u16 val, volatile u16 *addr)
{
	if (__is_ioaddr(addr))
		__raw_writew(val, (volatile u16 __iomem *) addr);
	else
		*addr = val;
}

static inline u16 scr_readw(volatile const u16 *addr)
{
	if (__is_ioaddr(addr))
		return __raw_readw((volatile const u16 __iomem *) addr);
	else
		return *addr;
}

static inline void scr_memsetw(u16 *s, u16 c, unsigned int count)
{
	if (__is_ioaddr(s))
		memsetw_io((u16 __iomem *) s, c, count);
	else
		memset16(s, c, count / 2);
}

/* Do not trust that the usage will be correct; analyze the arguments.  */
extern void scr_memcpyw(u16 *d, const u16 *s, unsigned int count);

/* ??? These are currently only used for downloading character sets.  As
   such, they don't need memory barriers.  Is this all they are intended
   to be used for?  */
#define vga_readb(a)	readb((u8 __iomem *)(a))
#define vga_writeb(v,a)	writeb(v, (u8 __iomem *)(a))

#ifdef CONFIG_VGA_HOSE
#include <linux/ioport.h>
#include <linux/pci.h>

extern struct pci_controller *pci_vga_hose;

# define __is_port_vga(a)       \
	(((a) >= 0x3b0) && ((a) < 0x3e0) && \
	 ((a) != 0x3b3) && ((a) != 0x3d3))

# define __is_mem_vga(a) \
	(((a) >= 0xa0000) && ((a) <= 0xc0000))

# define FIXUP_IOADDR_VGA(a) do {                       \
	if (pci_vga_hose && __is_port_vga(a))     \
		(a) += pci_vga_hose->io_space->start;	  \
 } while(0)

# define FIXUP_MEMADDR_VGA(a) do {                       \
	if (pci_vga_hose && __is_mem_vga(a))     \
		(a) += pci_vga_hose->mem_space->start; \
 } while(0)

#else /* CONFIG_VGA_HOSE */
# define pci_vga_hose 0
# define __is_port_vga(a) 0
# define __is_mem_vga(a) 0
# define FIXUP_IOADDR_VGA(a)
# define FIXUP_MEMADDR_VGA(a)
#endif /* CONFIG_VGA_HOSE */

#define VGA_MAP_MEM(x,s)	((unsigned long) ioremap(x, s))

#endif


code:
#ifndef _ASM_ALPHA_VMALLOC_H
#define _ASM_ALPHA_VMALLOC_H

#endif /* _ASM_ALPHA_VMALLOC_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_WORD_AT_A_TIME_H
#define _ASM_WORD_AT_A_TIME_H

#include <asm/compiler.h>

/*
 * word-at-a-time interface for Alpha.
 */

/*
 * We do not use the word_at_a_time struct on Alpha, but it needs to be
 * implemented to humour the generic code.
 */
struct word_at_a_time {
	const unsigned long unused;
};

#define WORD_AT_A_TIME_CONSTANTS { 0 }

/* Return nonzero if val has a zero */
static inline unsigned long has_zero(unsigned long val, unsigned long *bits, const struct word_at_a_time *c)
{
	unsigned long zero_locations = __kernel_cmpbge(0, val);
	*bits = zero_locations;
	return zero_locations;
}

static inline unsigned long prep_zero_mask(unsigned long val, unsigned long bits, const struct word_at_a_time *c)
{
	return bits;
}

#define create_zero_mask(bits) (bits)

static inline unsigned long find_zero(unsigned long bits)
{
#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
	/* Simple if have CIX instructions */
	return __kernel_cttz(bits);
#else
	unsigned long t1, t2, t3;
	/* Retain lowest set bit only */
	bits &= -bits;
	/* Binary search for lowest set bit */
	t1 = bits & 0xf0;
	t2 = bits & 0xcc;
	t3 = bits & 0xaa;
	if (t1) t1 = 4;
	if (t2) t2 = 2;
	if (t3) t3 = 1;
	return t1 + t2 + t3;
#endif
}

#define zero_bytemask(mask) ((2ul << (find_zero(mask) * 8)) - 1)

#endif /* _ASM_WORD_AT_A_TIME_H */


code:
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Definitions for use with the Alpha wrperfmon PAL call.
 */

#ifndef __ALPHA_WRPERFMON_H
#define __ALPHA_WRPERFMON_H

/* Following commands are implemented on all CPUs */
#define PERFMON_CMD_DISABLE 0
#define PERFMON_CMD_ENABLE 1
#define PERFMON_CMD_DESIRED_EVENTS 2
#define PERFMON_CMD_LOGGING_OPTIONS 3
/* Following commands on EV5/EV56/PCA56 only */
#define PERFMON_CMD_INT_FREQ 4
#define PERFMON_CMD_ENABLE_CLEAR 7
/* Following commands are on EV5 and better CPUs */
#define PERFMON_CMD_READ 5
#define PERFMON_CMD_WRITE 6
/* Following command are on EV6 and better CPUs */
#define PERFMON_CMD_ENABLE_WRITE 7
/* Following command are on EV67 and better CPUs */
#define PERFMON_CMD_I_STAT 8
#define PERFMON_CMD_PMPC 9

/* EV5/EV56/PCA56 Counters */
#define EV5_PCTR_0 (1UL<<0)
#define EV5_PCTR_1 (1UL<<1)
#define EV5_PCTR_2 (1UL<<2)

#define EV5_PCTR_0_COUNT_SHIFT 48
#define EV5_PCTR_1_COUNT_SHIFT 32
#define EV5_PCTR_2_COUNT_SHIFT 16

#define EV5_PCTR_0_COUNT_MASK 0xffffUL
#define EV5_PCTR_1_COUNT_MASK 0xffffUL
#define EV5_PCTR_2_COUNT_MASK 0x3fffUL

/* EV6 Counters */
#define EV6_PCTR_0 (1UL<<0)
#define EV6_PCTR_1 (1UL<<1)

#define EV6_PCTR_0_COUNT_SHIFT 28
#define EV6_PCTR_1_COUNT_SHIFT 6

#define EV6_PCTR_0_COUNT_MASK 0xfffffUL
#define EV6_PCTR_1_COUNT_MASK 0xfffffUL

/* EV67 (and subsequent) counters */
#define EV67_PCTR_0 (1UL<<0)
#define EV67_PCTR_1 (1UL<<1)

#define EV67_PCTR_0_COUNT_SHIFT 28
#define EV67_PCTR_1_COUNT_SHIFT 6

#define EV67_PCTR_0_COUNT_MASK 0xfffffUL
#define EV67_PCTR_1_COUNT_MASK 0xfffffUL

/*
 * The Alpha Architecure Handbook, vers. 4 (1998) appears to have a misprint
 *  in Table E-23 regarding the bits that set the event PCTR 1 counts.
 *  Hopefully what we have here is correct.
 */
#define EV6_PCTR_0_EVENT_MASK 0x10UL
#define EV6_PCTR_1_EVENT_MASK 0x0fUL

/* EV6 Events */
#define EV6_PCTR_0_CYCLES (0UL << 4)
#define EV6_PCTR_0_INSTRUCTIONS (1UL << 4)

#define EV6_PCTR_1_CYCLES 0
#define EV6_PCTR_1_BRANCHES 1
#define EV6_PCTR_1_BRANCH_MISPREDICTS 2
#define EV6_PCTR_1_DTB_SINGLE_MISSES 3
#define EV6_PCTR_1_DTB_DOUBLE_MISSES 4
#define EV6_PCTR_1_ITB_MISSES 5
#define EV6_PCTR_1_UNALIGNED_TRAPS 6
#define EV6_PCTR_1_REPLY_TRAPS 7

/* From the Alpha Architecture Reference Manual, 4th edn., 2002 */
#define EV67_PCTR_MODE_MASK 0x10UL
#define EV67_PCTR_EVENT_MASK 0x0CUL

#define EV67_PCTR_MODE_PROFILEME (1UL<<4)
#define EV67_PCTR_MODE_AGGREGATE (0UL<<4)

#define EV67_PCTR_INSTR_CYCLES (0UL<<2)
#define EV67_PCTR_CYCLES_UNDEF (1UL<<2)
#define EV67_PCTR_INSTR_BCACHEMISS (2UL<<2)
#define EV67_PCTR_CYCLES_MBOX (3UL<<2)

#endif


code:
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ALPHA_CMPXCHG_H
#error Do not include xchg.h directly!
#else
/*
 * xchg/xchg_local and cmpxchg/cmpxchg_local share the same code
 * except that local version do not have the expensive memory barrier.
 * So this file is included twice from asm/cmpxchg.h.
 */

/*
 * Atomic exchange.
 * Since it can be used to implement critical sections
 * it must clobber "memory" (also for interrupts in UP).
 */

static inline unsigned long
____xchg(_u8, volatile char *m, unsigned long val)
{
	unsigned long ret, tmp, addr64;

	__asm__ __volatile__(
	"	andnot	%4,7,%3\n"
	"	insbl	%1,%4,%1\n"
	"1:	ldq_l	%2,0(%3)\n"
	"	extbl	%2,%4,%0\n"
	"	mskbl	%2,%4,%2\n"
	"	or	%1,%2,%2\n"
	"	stq_c	%2,0(%3)\n"
	"	beq	%2,2f\n"
	".subsection 2\n"
	"2:	br	1b\n"
	".previous"
	: "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
	: "r" ((long)m), "1" (val) : "memory");

	return ret;
}

static inline unsigned long
____xchg(_u16, volatile short *m, unsigned long val)
{
	unsigned long ret, tmp, addr64;

	__asm__ __volatile__(
	"	andnot	%4,7,%3\n"
	"	inswl	%1,%4,%1\n"
	"1:	ldq_l	%2,0(%3)\n"
	"	extwl	%2,%4,%0\n"
	"	mskwl	%2,%4,%2\n"
	"	or	%1,%2,%2\n"
	"	stq_c	%2,0(%3)\n"
	"	beq	%2,2f\n"
	".subsection 2\n"
	"2:	br	1b\n"
	".previous"
	: "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
	: "r" ((long)m), "1" (val) : "memory");

	return ret;
}

static inline unsigned long
____xchg(_u32, volatile int *m, unsigned long val)
{
	unsigned long dummy;

	__asm__ __volatile__(
	"1:	ldl_l %0,%4\n"
	"	bis $31,%3,%1\n"
	"	stl_c %1,%2\n"
	"	beq %1,2f\n"
	".subsection 2\n"
	"2:	br 1b\n"
	".previous"
	: "=&r" (val), "=&r" (dummy), "=m" (*m)
	: "rI" (val), "m" (*m) : "memory");

	return val;
}

static inline unsigned long
____xchg(_u64, volatile long *m, unsigned long val)
{
	unsigned long dummy;

	__asm__ __volatile__(
	"1:	ldq_l %0,%4\n"
	"	bis $31,%3,%1\n"
	"	stq_c %1,%2\n"
	"	beq %1,2f\n"
	".subsection 2\n"
	"2:	br 1b\n"
	".previous"
	: "=&r" (val), "=&r" (dummy), "=m" (*m)
	: "rI" (val), "m" (*m) : "memory");

	return val;
}

/* This function doesn't exist, so you'll get a linker error
   if something tries to do an invalid xchg().  */
extern void __xchg_called_with_bad_pointer(void);

static __always_inline unsigned long
____xchg(, volatile void *ptr, unsigned long x, int size)
{
	switch (size) {
		case 1:
			return ____xchg(_u8, ptr, x);
		case 2:
			return ____xchg(_u16, ptr, x);
		case 4:
			return ____xchg(_u32, ptr, x);
		case 8:
			return ____xchg(_u64, ptr, x);
	}
	__xchg_called_with_bad_pointer();
	return x;
}

/*
 * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 * store NEW in MEM.  Return the initial value in MEM.  Success is
 * indicated by comparing RETURN with OLD.
 */

static inline unsigned long
____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new)
{
	unsigned long prev, tmp, cmp, addr64;

	__asm__ __volatile__(
	"	andnot	%5,7,%4\n"
	"	insbl	%1,%5,%1\n"
	"1:	ldq_l	%2,0(%4)\n"
	"	extbl	%2,%5,%0\n"
	"	cmpeq	%0,%6,%3\n"
	"	beq	%3,2f\n"
	"	mskbl	%2,%5,%2\n"
	"	or	%1,%2,%2\n"
	"	stq_c	%2,0(%4)\n"
	"	beq	%2,3f\n"
	"2:\n"
	".subsection 2\n"
	"3:	br	1b\n"
	".previous"
	: "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
	: "r" ((long)m), "Ir" (old), "1" (new) : "memory");

	return prev;
}

static inline unsigned long
____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new)
{
	unsigned long prev, tmp, cmp, addr64;

	__asm__ __volatile__(
	"	andnot	%5,7,%4\n"
	"	inswl	%1,%5,%1\n"
	"1:	ldq_l	%2,0(%4)\n"
	"	extwl	%2,%5,%0\n"
	"	cmpeq	%0,%6,%3\n"
	"	beq	%3,2f\n"
	"	mskwl	%2,%5,%2\n"
	"	or	%1,%2,%2\n"
	"	stq_c	%2,0(%4)\n"
	"	beq	%2,3f\n"
	"2:\n"
	".subsection 2\n"
	"3:	br	1b\n"
	".previous"
	: "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
	: "r" ((long)m), "Ir" (old), "1" (new) : "memory");

	return prev;
}

static inline unsigned long
____cmpxchg(_u32, volatile int *m, int old, int new)
{
	unsigned long prev, cmp;

	__asm__ __volatile__(
	"1:	ldl_l %0,%5\n"
	"	cmpeq %0,%3,%1\n"
	"	beq %1,2f\n"
	"	mov %4,%1\n"
	"	stl_c %1,%2\n"
	"	beq %1,3f\n"
	"2:\n"
	".subsection 2\n"
	"3:	br 1b\n"
	".previous"
	: "=&r"(prev), "=&r"(cmp), "=m"(*m)
	: "r"((long) old), "r"(new), "m"(*m) : "memory");

	return prev;
}

static inline unsigned long
____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new)
{
	unsigned long prev, cmp;

	__asm__ __volatile__(
	"1:	ldq_l %0,%5\n"
	"	cmpeq %0,%3,%1\n"
	"	beq %1,2f\n"
	"	mov %4,%1\n"
	"	stq_c %1,%2\n"
	"	beq %1,3f\n"
	"2:\n"
	".subsection 2\n"
	"3:	br 1b\n"
	".previous"
	: "=&r"(prev), "=&r"(cmp), "=m"(*m)
	: "r"((long) old), "r"(new), "m"(*m) : "memory");

	return prev;
}

/* This function doesn't exist, so you'll get a linker error
   if something tries to do an invalid cmpxchg().  */
extern void __cmpxchg_called_with_bad_pointer(void);

static __always_inline unsigned long
____cmpxchg(, volatile void *ptr, unsigned long old, unsigned long new,
	      int size)
{
	switch (size) {
		case 1:
			return ____cmpxchg(_u8, ptr, old, new);
		case 2:
			return ____cmpxchg(_u16, ptr, old, new);
		case 4:
			return ____cmpxchg(_u32, ptr, old, new);
		case 8:
			return ____cmpxchg(_u64, ptr, old, new);
	}
	__cmpxchg_called_with_bad_pointer();
	return old;
}

#endif


code:
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * include/asm-alpha/xor.h
 *
 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
 */

extern void
xor_alpha_2(unsigned long bytes, unsigned long * __restrict p1,
	    const unsigned long * __restrict p2);
extern void
xor_alpha_3(unsigned long bytes, unsigned long * __restrict p1,
	    const unsigned long * __restrict p2,
	    const unsigned long * __restrict p3);
extern void
xor_alpha_4(unsigned long bytes, unsigned long * __restrict p1,
	    const unsigned long * __restrict p2,
	    const unsigned long * __restrict p3,
	    const unsigned long * __restrict p4);
extern void
xor_alpha_5(unsigned long bytes, unsigned long * __restrict p1,
	    const unsigned long * __restrict p2,
	    const unsigned long * __restrict p3,
	    const unsigned long * __restrict p4,
	    const unsigned long * __restrict p5);

extern void
xor_alpha_prefetch_2(unsigned long bytes, unsigned long * __restrict p1,
		     const unsigned long * __restrict p2);
extern void
xor_alpha_prefetch_3(unsigned long bytes, unsigned long * __restrict p1,
		     const unsigned long * __restrict p2,
		     const unsigned long * __restrict p3);
extern void
xor_alpha_prefetch_4(unsigned long bytes, unsigned long * __restrict p1,
		     const unsigned long * __restrict p2,
		     const unsigned long * __restrict p3,
		     const unsigned long * __restrict p4);
extern void
xor_alpha_prefetch_5(unsigned long bytes, unsigned long * __restrict p1,
		     const unsigned long * __restrict p2,
		     const unsigned long * __restrict p3,
		     const unsigned long * __restrict p4,
		     const unsigned long * __restrict p5);

asm("								\n\
	.text							\n\
	.align 3						\n\
	.ent xor_alpha_2					\n\
xor_alpha_2:							\n\
	.prologue 0						\n\
	srl $16, 6, $16						\n\
	.align 4						\n\
2:								\n\
	ldq $0,0($17)						\n\
	ldq $1,0($18)						\n\
	ldq $2,8($17)						\n\
	ldq $3,8($18)						\n\
								\n\
	ldq $4,16($17)						\n\
	ldq $5,16($18)						\n\
	ldq $6,24($17)						\n\
	ldq $7,24($18)						\n\
								\n\
	ldq $19,32($17)						\n\
	ldq $20,32($18)						\n\
	ldq $21,40($17)						\n\
	ldq $22,40($18)						\n\
								\n\
	ldq $23,48($17)						\n\
	ldq $24,48($18)						\n\
	ldq $25,56($17)						\n\
	xor $0,$1,$0		# 7 cycles from $1 load		\n\
								\n\
	ldq $27,56($18)						\n\
	xor $2,$3,$2						\n\
	stq $0,0($17)						\n\
	xor $4,$5,$4						\n\
								\n\
	stq $2,8($17)						\n\
	xor $6,$7,$6						\n\
	stq $4,16($17)						\n\
	xor $19,$20,$19						\n\
								\n\
	stq $6,24($17)						\n\
	xor $21,$22,$21						\n\
	stq $19,32($17)						\n\
	xor $23,$24,$23						\n\
								\n\
	stq $21,40($17)						\n\
	xor $25,$27,$25						\n\
	stq $23,48($17)						\n\
	subq $16,1,$16						\n\
								\n\
	stq $25,56($17)						\n\
	addq $17,64,$17						\n\
	addq $18,64,$18						\n\
	bgt $16,2b						\n\
								\n\
	ret							\n\
	.end xor_alpha_2					\n\
								\n\
	.align 3						\n\
	.ent xor_alpha_3					\n\
xor_alpha_3:							\n\
	.prologue 0						\n\
	srl $16, 6, $16						\n\
	.align 4						\n\
3:								\n\
	ldq $0,0($17)						\n\
	ldq $1,0($18)						\n\
	ldq $2,0($19)						\n\
	ldq $3,8($17)						\n\
								\n\
	ldq $4,8($18)						\n\
	ldq $6,16($17)						\n\
	ldq $7,16($18)						\n\
	ldq $21,24($17)						\n\
								\n\
	ldq $22,24($18)						\n\
	ldq $24,32($17)						\n\
	ldq $25,32($18)						\n\
	ldq $5,8($19)						\n\
								\n\
	ldq $20,16($19)						\n\
	ldq $23,24($19)						\n\
	ldq $27,32($19)						\n\
	nop							\n\
								\n\
	xor $0,$1,$1		# 8 cycles from $0 load		\n\
	xor $3,$4,$4		# 6 cycles from $4 load		\n\
	xor $6,$7,$7		# 6 cycles from $7 load		\n\
	xor $21,$22,$22		# 5 cycles from $22 load	\n\
								\n\
	xor $1,$2,$2		# 9 cycles from $2 load		\n\
	xor $24,$25,$25		# 5 cycles from $25 load	\n\
	stq $2,0($17)						\n\
	xor $4,$5,$5		# 6 cycles from $5 load		\n\
								\n\
	stq $5,8($17)						\n\
	xor $7,$20,$20		# 7 cycles from $20 load	\n\
	stq $20,16($17)						\n\
	xor $22,$23,$23		# 7 cycles from $23 load	\n\
								\n\
	stq $23,24($17)						\n\
	xor $25,$27,$27		# 7 cycles from $27 load	\n\
	stq $27,32($17)						\n\
	nop							\n\
								\n\
	ldq $0,40($17)						\n\
	ldq $1,40($18)						\n\
	ldq $3,48($17)						\n\
	ldq $4,48($18)						\n\
								\n\
	ldq $6,56($17)						\n\
	ldq $7,56($18)						\n\
	ldq $2,40($19)						\n\
	ldq $5,48($19)						\n\
								\n\
	ldq $20,56($19)						\n\
	xor $0,$1,$1		# 4 cycles from $1 load		\n\
	xor $3,$4,$4		# 5 cycles from $4 load		\n\
	xor $6,$7,$7		# 5 cycles from $7 load		\n\
								\n\
	xor $1,$2,$2		# 4 cycles from $2 load		\n\
	xor $4,$5,$5		# 5 cycles from $5 load		\n\
	stq $2,40($17)						\n\
	xor $7,$20,$20		# 4 cycles from $20 load	\n\
								\n\
	stq $5,48($17)						\n\
	subq $16,1,$16						\n\
	stq $20,56($17)						\n\
	addq $19,64,$19						\n\
								\n\
	addq $18,64,$18						\n\
	addq $17,64,$17						\n\
	bgt $16,3b						\n\
	ret							\n\
	.end xor_alpha_3					\n\
								\n\
	.align 3						\n\
	.ent xor_alpha_4					\n\
xor_alpha_4:							\n\
	.prologue 0						\n\
	srl $16, 6, $16						\n\
	.align 4						\n\
4:								\n\
	ldq $0,0($17)						\n\
	ldq $1,0($18)						\n\
	ldq $2,0($19)						\n\
	ldq $3,0($20)						\n\
								\n\
	ldq $4,8($17)						\n\
	ldq $5,8($18)						\n\
	ldq $6,8($19)						\n\
	ldq $7,8($20)						\n\
								\n\
	ldq $21,16($17)						\n\
	ldq $22,16($18)						\n\
	ldq $23,16($19)						\n\
	ldq $24,16($20)						\n\
								\n\
	ldq $25,24($17)						\n\
	xor $0,$1,$1		# 6 cycles from $1 load		\n\
	ldq $27,24($18)						\n\
	xor $2,$3,$3		# 6 cycles from $3 load		\n\
								\n\
	ldq $0,24($19)						\n\
	xor $1,$3,$3						\n\
	ldq $1,24($20)						\n\
	xor $4,$5,$5		# 7 cycles from $5 load		\n\
								\n\
	stq $3,0($17)						\n\
	xor $6,$7,$7						\n\
	xor $21,$22,$22		# 7 cycles from $22 load	\n\
	xor $5,$7,$7						\n\
								\n\
	stq $7,8($17)						\n\
	xor $23,$24,$24		# 7 cycles from $24 load	\n\
	ldq $2,32($17)						\n\
	xor $22,$24,$24						\n\
								\n\
	ldq $3,32($18)						\n\
	ldq $4,32($19)						\n\
	ldq $5,32($20)						\n\
	xor $25,$27,$27		# 8 cycles from $27 load	\n\
								\n\
	ldq $6,40($17)						\n\
	ldq $7,40($18)						\n\
	ldq $21,40($19)						\n\
	ldq $22,40($20)						\n\
								\n\
	stq $24,16($17)						\n\
	xor $0,$1,$1		# 9 cycles from $1 load		\n\
	xor $2,$3,$3		# 5 cycles from $3 load		\n\
	xor $27,$1,$1						\n\
								\n\
	stq $1,24($17)						\n\
	xor $4,$5,$5		# 5 cycles from $5 load		\n\
	ldq $23,48($17)						\n\
	ldq $24,48($18)						\n\
								\n\
	ldq $25,48($19)						\n\
	xor $3,$5,$5						\n\
	ldq $27,48($20)						\n\
	ldq $0,56($17)						\n\
								\n\
	ldq $1,56($18)						\n\
	ldq $2,56($19)						\n\
	xor $6,$7,$7		# 8 cycles from $6 load		\n\
	ldq $3,56($20)						\n\
								\n\
	stq $5,32($17)						\n\
	xor $21,$22,$22		# 8 cycles from $22 load	\n\
	xor $7,$22,$22						\n\
	xor $23,$24,$24		# 5 cycles from $24 load	\n\
								\n\
	stq $22,40($17)						\n\
	xor $25,$27,$27		# 5 cycles from $27 load	\n\
	xor $24,$27,$27						\n\
	xor $0,$1,$1		# 5 cycles from $1 load		\n\
								\n\
	stq $27,48($17)						\n\
	xor $2,$3,$3		# 4 cycles from $3 load		\n\
	xor $1,$3,$3						\n\
	subq $16,1,$16						\n\
								\n\
	stq $3,56($17)						\n\
	addq $20,64,$20						\n\
	addq $19,64,$19						\n\
	addq $18,64,$18						\n\
								\n\
	addq $17,64,$17						\n\
	bgt $16,4b						\n\
	ret							\n\
	.end xor_alpha_4					\n\
								\n\
	.align 3						\n\
	.ent xor_alpha_5					\n\
xor_alpha_5:							\n\
	.prologue 0						\n\
	srl $16, 6, $16						\n\
	.align 4						\n\
5:								\n\
	ldq $0,0($17)						\n\
	ldq $1,0($18)						\n\
	ldq $2,0($19)						\n\
	ldq $3,0($20)						\n\
								\n\
	ldq $4,0($21)						\n\
	ldq $5,8($17)						\n\
	ldq $6,8($18)						\n\
	ldq $7,8($19)						\n\
								\n\
	ldq $22,8($20)						\n\
	ldq $23,8($21)						\n\
	ldq $24,16($17)						\n\
	ldq $25,16($18)						\n\
								\n\
	ldq $27,16($19)						\n\
	xor $0,$1,$1		# 6 cycles from $1 load		\n\
	ldq $28,16($20)						\n\
	xor $2,$3,$3		# 6 cycles from $3 load		\n\
								\n\
	ldq $0,16($21)						\n\
	xor $1,$3,$3						\n\
	ldq $1,24($17)						\n\
	xor $3,$4,$4		# 7 cycles from $4 load		\n\
								\n\
	stq $4,0($17)						\n\
	xor $5,$6,$6		# 7 cycles from $6 load		\n\
	xor $7,$22,$22		# 7 cycles from $22 load	\n\
	xor $6,$23,$23		# 7 cycles from $23 load	\n\
								\n\
	ldq $2,24($18)						\n\
	xor $22,$23,$23						\n\
	ldq $3,24($19)						\n\
	xor $24,$25,$25		# 8 cycles from $25 load	\n\
								\n\
	stq $23,8($17)						\n\
	xor $25,$27,$27		# 8 cycles from $27 load	\n\
	ldq $4,24($20)						\n\
	xor $28,$0,$0		# 7 cycles from $0 load		\n\
								\n\
	ldq $5,24($21)						\n\
	xor $27,$0,$0						\n\
	ldq $6,32($17)						\n\
	ldq $7,32($18)						\n\
								\n\
	stq $0,16($17)						\n\
	xor $1,$2,$2		# 6 cycles from $2 load		\n\
	ldq $22,32($19)						\n\
	xor $3,$4,$4		# 4 cycles from $4 load		\n\
								\n\
	ldq $23,32($20)						\n\
	xor $2,$4,$4						\n\
	ldq $24,32($21)						\n\
	ldq $25,40($17)						\n\
								\n\
	ldq $27,40($18)						\n\
	ldq $28,40($19)						\n\
	ldq $0,40($20)						\n\
	xor $4,$5,$5		# 7 cycles from $5 load		\n\
								\n\
	stq $5,24($17)						\n\
	xor $6,$7,$7		# 7 cycles from $7 load		\n\
	ldq $1,40($21)						\n\
	ldq $2,48($17)						\n\
								\n\
	ldq $3,48($18)						\n\
	xor $7,$22,$22		# 7 cycles from $22 load	\n\
	ldq $4,48($19)						\n\
	xor $23,$24,$24		# 6 cycles from $24 load	\n\
								\n\
	ldq $5,48($20)						\n\
	xor $22,$24,$24						\n\
	ldq $6,48($21)						\n\
	xor $25,$27,$27		# 7 cycles from $27 load	\n\
								\n\
	stq $24,32($17)						\n\
	xor $27,$28,$28		# 8 cycles from $28 load	\n\
	ldq $7,56($17)						\n\
	xor $0,$1,$1		# 6 cycles from $1 load		\n\
								\n\
	ldq $22,56($18)						\n\
	ldq $23,56($19)						\n\
	ldq $24,56($20)						\n\
	ldq $25,56($21)						\n\
								\n\
	xor $28,$1,$1						\n\
	xor $2,$3,$3		# 9 cycles from $3 load		\n\
	xor $3,$4,$4		# 9 cycles from $4 load		\n\
	xor $5,$6,$6		# 8 cycles from $6 load		\n\
								\n\
	stq $1,40($17)						\n\
	xor $4,$6,$6						\n\
	xor $7,$22,$22		# 7 cycles from $22 load	\n\
	xor $23,$24,$24		# 6 cycles from $24 load	\n\
								\n\
	stq $6,48($17)						\n\
	xor $22,$24,$24						\n\
	subq $16,1,$16						\n\
	xor $24,$25,$25		# 8 cycles from $25 load	\n\
								\n\
	stq $25,56($17)						\n\
	addq $21,64,$21						\n\
	addq $20,64,$20						\n\
	addq $19,64,$19						\n\
								\n\
	addq $18,64,$18						\n\
	addq $17,64,$17						\n\
	bgt $16,5b						\n\
	ret							\n\
	.end xor_alpha_5					\n\
								\n\
	.align 3						\n\
	.ent xor_alpha_prefetch_2				\n\
xor_alpha_prefetch_2:						\n\
	.prologue 0						\n\
	srl $16, 6, $16						\n\
								\n\
	ldq $31, 0($17)						\n\
	ldq $31, 0($18)						\n\
								\n\
	ldq $31, 64($17)					\n\
	ldq $31, 64($18)					\n\
								\n\
	ldq $31, 128($17)					\n\
	ldq $31, 128($18)					\n\
								\n\
	ldq $31, 192($17)					\n\
	ldq $31, 192($18)					\n\
	.align 4						\n\
2:								\n\
	ldq $0,0($17)						\n\
	ldq $1,0($18)						\n\
	ldq $2,8($17)						\n\
	ldq $3,8($18)						\n\
								\n\
	ldq $4,16($17)						\n\
	ldq $5,16($18)						\n\
	ldq $6,24($17)						\n\
	ldq $7,24($18)						\n\
								\n\
	ldq $19,32($17)						\n\
	ldq $20,32($18)						\n\
	ldq $21,40($17)						\n\
	ldq $22,40($18)						\n\
								\n\
	ldq $23,48($17)						\n\
	ldq $24,48($18)						\n\
	ldq $25,56($17)						\n\
	ldq $27,56($18)						\n\
								\n\
	ldq $31,256($17)					\n\
	xor $0,$1,$0		# 8 cycles from $1 load		\n\
	ldq $31,256($18)					\n\
	xor $2,$3,$2						\n\
								\n\
	stq $0,0($17)						\n\
	xor $4,$5,$4						\n\
	stq $2,8($17)						\n\
	xor $6,$7,$6						\n\
								\n\
	stq $4,16($17)						\n\
	xor $19,$20,$19						\n\
	stq $6,24($17)						\n\
	xor $21,$22,$21						\n\
								\n\
	stq $19,32($17)						\n\
	xor $23,$24,$23						\n\
	stq $21,40($17)						\n\
	xor $25,$27,$25						\n\
								\n\
	stq $23,48($17)						\n\
	subq $16,1,$16						\n\
	stq $25,56($17)						\n\
	addq $17,64,$17						\n\
								\n\
	addq $18,64,$18						\n\
	bgt $16,2b						\n\
	ret							\n\
	.end xor_alpha_prefetch_2				\n\
								\n\
	.align 3						\n\
	.ent xor_alpha_prefetch_3				\n\
xor_alpha_prefetch_3:						\n\
	.prologue 0						\n\
	srl $16, 6, $16						\n\
								\n\
	ldq $31, 0($17)						\n\
	ldq $31, 0($18)						\n\
	ldq $31, 0($19)						\n\
								\n\
	ldq $31, 64($17)					\n\
	ldq $31, 64($18)					\n\
	ldq $31, 64($19)					\n\
								\n\
	ldq $31, 128($17)					\n\
	ldq $31, 128($18)					\n\
	ldq $31, 128($19)					\n\
								\n\
	ldq $31, 192($17)					\n\
	ldq $31, 192($18)					\n\
	ldq $31, 192($19)					\n\
	.align 4						\n\
3:								\n\
	ldq $0,0($17)						\n\
	ldq $1,0($18)						\n\
	ldq $2,0($19)						\n\
	ldq $3,8($17)						\n\
								\n\
	ldq $4,8($18)						\n\
	ldq $6,16($17)						\n\
	ldq $7,16($18)						\n\
	ldq $21,24($17)						\n\
								\n\
	ldq $22,24($18)						\n\
	ldq $24,32($17)						\n\
	ldq $25,32($18)						\n\
	ldq $5,8($19)						\n\
								\n\
	ldq $20,16($19)						\n\
	ldq $23,24($19)						\n\
	ldq $27,32($19)						\n\
	nop							\n\
								\n\
	xor $0,$1,$1		# 8 cycles from $0 load		\n\
	xor $3,$4,$4		# 7 cycles from $4 load		\n\
	xor $6,$7,$7		# 6 cycles from $7 load		\n\
	xor $21,$22,$22		# 5 cycles from $22 load	\n\
								\n\
	xor $1,$2,$2		# 9 cycles from $2 load		\n\
	xor $24,$25,$25		# 5 cycles from $25 load	\n\
	stq $2,0($17)						\n\
	xor $4,$5,$5		# 6 cycles from $5 load		\n\
								\n\
	stq $5,8($17)						\n\
	xor $7,$20,$20		# 7 cycles from $20 load	\n\
	stq $20,16($17)						\n\
	xor $22,$23,$23		# 7 cycles from $23 load	\n\
								\n\
	stq $23,24($17)						\n\
	xor $25,$27,$27		# 7 cycles from $27 load	\n\
	stq $27,32($17)						\n\
	nop							\n\
								\n\
	ldq $0,40($17)						\n\
	ldq $1,40($18)						\n\
	ldq $3,48($17)						\n\
	ldq $4,48($18)						\n\
								\n\
	ldq $6,56($17)						\n\
	ldq $7,56($18)						\n\
	ldq $2,40($19)						\n\
	ldq $5,48($19)						\n\
								\n\
	ldq $20,56($19)						\n\
	ldq $31,256($17)					\n\
	ldq $31,256($18)					\n\
	ldq $31,256($19)					\n\
								\n\
	xor $0,$1,$1		# 6 cycles from $1 load		\n\
	xor $3,$4,$4		# 5 cycles from $4 load		\n\
	xor $6,$7,$7		# 5 cycles from $7 load		\n\
	xor $1,$2,$2		# 4 cycles from $2 load		\n\
								\n\
	xor $4,$5,$5		# 5 cycles from $5 load		\n\
	xor $7,$20,$20		# 4 cycles from $20 load	\n\
	stq $2,40($17)						\n\
	subq $16,1,$16						\n\
								\n\
	stq $5,48($17)						\n\
	addq $19,64,$19						\n\
	stq $20,56($17)						\n\
	addq $18,64,$18						\n\
								\n\
	addq $17,64,$17						\n\
	bgt $16,3b						\n\
	ret							\n\
	.end xor_alpha_prefetch_3				\n\
								\n\
	.align 3						\n\
	.ent xor_alpha_prefetch_4				\n\
xor_alpha_prefetch_4:						\n\
	.prologue 0						\n\
	srl $16, 6, $16						\n\
								\n\
	ldq $31, 0($17)						\n\
	ldq $31, 0($18)						\n\
	ldq $31, 0($19)						\n\
	ldq $31, 0($20)						\n\
								\n\
	ldq $31, 64($17)					\n\
	ldq $31, 64($18)					\n\
	ldq $31, 64($19)					\n\
	ldq $31, 64($20)					\n\
								\n\
	ldq $31, 128($17)					\n\
	ldq $31, 128($18)					\n\
	ldq $31, 128($19)					\n\
	ldq $31, 128($20)					\n\
								\n\
	ldq $31, 192($17)					\n\
	ldq $31, 192($18)					\n\
	ldq $31, 192($19)					\n\
	ldq $31, 192($20)					\n\
	.align 4						\n\
4:								\n\
	ldq $0,0($17)						\n\
	ldq $1,0($18)						\n\
	ldq $2,0($19)						\n\
	ldq $3,0($20)						\n\
								\n\
	ldq $4,8($17)						\n\
	ldq $5,8($18)						\n\
	ldq $6,8($19)						\n\
	ldq $7,8($20)						\n\
								\n\
	ldq $21,16($17)						\n\
	ldq $22,16($18)						\n\
	ldq $23,16($19)						\n\
	ldq $24,16($20)						\n\
								\n\
	ldq $25,24($17)						\n\
	xor $0,$1,$1		# 6 cycles from $1 load		\n\
	ldq $27,24($18)						\n\
	xor $2,$3,$3		# 6 cycles from $3 load		\n\
								\n\
	ldq $0,24($19)						\n\
	xor $1,$3,$3						\n\
	ldq $1,24($20)						\n\
	xor $4,$5,$5		# 7 cycles from $5 load		\n\
								\n\
	stq $3,0($17)						\n\
	xor $6,$7,$7						\n\
	xor $21,$22,$22		# 7 cycles from $22 load	\n\
	xor $5,$7,$7						\n\
								\n\
	stq $7,8($17)						\n\
	xor $23,$24,$24		# 7 cycles from $24 load	\n\
	ldq $2,32($17)						\n\
	xor $22,$24,$24						\n\
								\n\
	ldq $3,32($18)						\n\
	ldq $4,32($19)						\n\
	ldq $5,32($20)						\n\
	xor $25,$27,$27		# 8 cycles from $27 load	\n\
								\n\
	ldq $6,40($17)						\n\
	ldq $7,40($18)						\n\
	ldq $21,40($19)						\n\
	ldq $22,40($20)						\n\
								\n\
	stq $24,16($17)						\n\
	xor $0,$1,$1		# 9 cycles from $1 load		\n\
	xor $2,$3,$3		# 5 cycles from $3 load		\n\
	xor $27,$1,$1						\n\
								\n\
	stq $1,24($17)						\n\
	xor $4,$5,$5		# 5 cycles from $5 load		\n\
	ldq $23,48($17)						\n\
	xor $3,$5,$5						\n\
								\n\
	ldq $24,48($18)						\n\
	ldq $25,48($19)						\n\
	ldq $27,48($20)						\n\
	ldq $0,56($17)						\n\
								\n\
	ldq $1,56($18)						\n\
	ldq $2,56($19)						\n\
	ldq $3,56($20)						\n\
	xor $6,$7,$7		# 8 cycles from $6 load		\n\
								\n\
	ldq $31,256($17)					\n\
	xor $21,$22,$22		# 8 cycles from $22 load	\n\
	ldq $31,256($18)					\n\
	xor $7,$22,$22						\n\
								\n\
	ldq $31,256($19)					\n\
	xor $23,$24,$24		# 6 cycles from $24 load	\n\
	ldq $31,256($20)					\n\
	xor $25,$27,$27		# 6 cycles from $27 load	\n\
								\n\
	stq $5,32($17)						\n\
	xor $24,$27,$27						\n\
	xor $0,$1,$1		# 7 cycles from $1 load		\n\
	xor $2,$3,$3		# 6 cycles from $3 load		\n\
								\n\
	stq $22,40($17)						\n\
	xor $1,$3,$3						\n\
	stq $27,48($17)						\n\
	subq $16,1,$16						\n\
								\n\
	stq $3,56($17)						\n\
	addq $20,64,$20						\n\
	addq $19,64,$19						\n\
	addq $18,64,$18						\n\
								\n\
	addq $17,64,$17						\n\
	bgt $16,4b						\n\
	ret							\n\
	.end xor_alpha_prefetch_4				\n\
								\n\
	.align 3						\n\
	.ent xor_alpha_prefetch_5				\n\
xor_alpha_prefetch_5:						\n\
	.prologue 0						\n\
	srl $16, 6, $16						\n\
								\n\
	ldq $31, 0($17)						\n\
	ldq $31, 0($18)						\n\
	ldq $31, 0($19)						\n\
	ldq $31, 0($20)						\n\
	ldq $31, 0($21)						\n\
								\n\
	ldq $31, 64($17)					\n\
	ldq $31, 64($18)					\n\
	ldq $31, 64($19)					\n\
	ldq $31, 64($20)					\n\
	ldq $31, 64($21)					\n\
								\n\
	ldq $31, 128($17)					\n\
	ldq $31, 128($18)					\n\
	ldq $31, 128($19)					\n\
	ldq $31, 128($20)					\n\
	ldq $31, 128($21)					\n\
								\n\
	ldq $31, 192($17)					\n\
	ldq $31, 192($18)					\n\
	ldq $31, 192($19)					\n\
	ldq $31, 192($20)					\n\
	ldq $31, 192($21)					\n\
	.align 4						\n\
5:								\n\
	ldq $0,0($17)						\n\
	ldq $1,0($18)						\n\
	ldq $2,0($19)						\n\
	ldq $3,0($20)						\n\
								\n\
	ldq $4,0($21)						\n\
	ldq $5,8($17)						\n\
	ldq $6,8($18)						\n\
	ldq $7,8($19)						\n\
								\n\
	ldq $22,8($20)						\n\
	ldq $23,8($21)						\n\
	ldq $24,16($17)						\n\
	ldq $25,16($18)						\n\
								\n\
	ldq $27,16($19)						\n\
	xor $0,$1,$1		# 6 cycles from $1 load		\n\
	ldq $28,16($20)						\n\
	xor $2,$3,$3		# 6 cycles from $3 load		\n\
								\n\
	ldq $0,16($21)						\n\
	xor $1,$3,$3						\n\
	ldq $1,24($17)						\n\
	xor $3,$4,$4		# 7 cycles from $4 load		\n\
								\n\
	stq $4,0($17)						\n\
	xor $5,$6,$6		# 7 cycles from $6 load		\n\
	xor $7,$22,$22		# 7 cycles from $22 load	\n\
	xor $6,$23,$23		# 7 cycles from $23 load	\n\
								\n\
	ldq $2,24($18)						\n\
	xor $22,$23,$23						\n\
	ldq $3,24($19)						\n\
	xor $24,$25,$25		# 8 cycles from $25 load	\n\
								\n\
	stq $23,8($17)						\n\
	xor $25,$27,$27		# 8 cycles from $27 load	\n\
	ldq $4,24($20)						\n\
	xor $28,$0,$0		# 7 cycles from $0 load		\n\
								\n\
	ldq $5,24($21)						\n\
	xor $27,$0,$0						\n\
	ldq $6,32($17)						\n\
	ldq $7,32($18)						\n\
								\n\
	stq $0,16($17)						\n\
	xor $1,$2,$2		# 6 cycles from $2 load		\n\
	ldq $22,32($19)						\n\
	xor $3,$4,$4		# 4 cycles from $4 load		\n\
								\n\
	ldq $23,32($20)						\n\
	xor $2,$4,$4						\n\
	ldq $24,32($21)						\n\
	ldq $25,40($17)						\n\
								\n\
	ldq $27,40($18)						\n\
	ldq $28,40($19)						\n\
	ldq $0,40($20)						\n\
	xor $4,$5,$5		# 7 cycles from $5 load		\n\
								\n\
	stq $5,24($17)						\n\
	xor $6,$7,$7		# 7 cycles from $7 load		\n\
	ldq $1,40($21)						\n\
	ldq $2,48($17)						\n\
								\n\
	ldq $3,48($18)						\n\
	xor $7,$22,$22		# 7 cycles from $22 load	\n\
	ldq $4,48($19)						\n\
	xor $23,$24,$24		# 6 cycles from $24 load	\n\
								\n\
	ldq $5,48($20)						\n\
	xor $22,$24,$24						\n\
	ldq $6,48($21)						\n\
	xor $25,$27,$27		# 7 cycles from $27 load	\n\
								\n\
	stq $24,32($17)						\n\
	xor $27,$28,$28		# 8 cycles from $28 load	\n\
	ldq $7,56($17)						\n\
	xor $0,$1,$1		# 6 cycles from $1 load		\n\
								\n\
	ldq $22,56($18)						\n\
	ldq $23,56($19)						\n\
	ldq $24,56($20)						\n\
	ldq $25,56($21)						\n\
								\n\
	ldq $31,256($17)					\n\
	xor $28,$1,$1						\n\
	ldq $31,256($18)					\n\
	xor $2,$3,$3		# 9 cycles from $3 load		\n\
								\n\
	ldq $31,256($19)					\n\
	xor $3,$4,$4		# 9 cycles from $4 load		\n\
	ldq $31,256($20)					\n\
	xor $5,$6,$6		# 8 cycles from $6 load		\n\
								\n\
	stq $1,40($17)						\n\
	xor $4,$6,$6						\n\
	xor $7,$22,$22		# 7 cycles from $22 load	\n\
	xor $23,$24,$24		# 6 cycles from $24 load	\n\
								\n\
	stq $6,48($17)						\n\
	xor $22,$24,$24						\n\
	ldq $31,256($21)					\n\
	xor $24,$25,$25		# 8 cycles from $25 load	\n\
								\n\
	stq $25,56($17)						\n\
	subq $16,1,$16						\n\
	addq $21,64,$21						\n\
	addq $20,64,$20						\n\
								\n\
	addq $19,64,$19						\n\
	addq $18,64,$18						\n\
	addq $17,64,$17						\n\
	bgt $16,5b						\n\
								\n\
	ret							\n\
	.end xor_alpha_prefetch_5				\n\
");

static struct xor_block_template xor_block_alpha = {
	.name	= "alpha",
	.do_2	= xor_alpha_2,
	.do_3	= xor_alpha_3,
	.do_4	= xor_alpha_4,
	.do_5	= xor_alpha_5,
};

static struct xor_block_template xor_block_alpha_prefetch = {
	.name	= "alpha prefetch",
	.do_2	= xor_alpha_prefetch_2,
	.do_3	= xor_alpha_prefetch_3,
	.do_4	= xor_alpha_prefetch_4,
	.do_5	= xor_alpha_prefetch_5,
};

/* For grins, also test the generic routines.  */
#include <asm-generic/xor.h>

#undef XOR_TRY_TEMPLATES
#define XOR_TRY_TEMPLATES				\
	do {						\
		xor_speed(&xor_block_8regs);		\
		xor_speed(&xor_block_32regs);		\
		xor_speed(&xor_block_alpha);		\
		xor_speed(&xor_block_alpha_prefetch);	\
	} while (0)

/* Force the use of alpha_prefetch if EV6, as it is significantly
   faster in the cold cache case.  */
#define XOR_SELECT_TEMPLATE(FASTEST) \
	(implver() == IMPLVER_EV6 ? &xor_block_alpha_prefetch : FASTEST)


code:
# SPDX-License-Identifier: GPL-2.0
generated-y += unistd_32.h

path: arch/alpha/include/uapi/asm/Kbuild


code:
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _UAPI__ALPHA_A_OUT_H__
#define _UAPI__ALPHA_A_OUT_H__

#include <linux/types.h>

/*
 * OSF/1 ECOFF header structs.  ECOFF files consist of:
 * 	- a file header (struct filehdr),
 *	- an a.out header (struct aouthdr),
 *	- one or more section headers (struct scnhdr).
 *	  The filhdr's "f_nscns" field contains the
 *	  number of section headers.
 */

struct filehdr
{
	/* OSF/1 "file" header */
	__u16 f_magic, f_nscns;
	__u32 f_timdat;
	__u64 f_symptr;
	__u32 f_nsyms;
	__u16 f_opthdr, f_flags;
};

struct aouthdr
{
	__u64 info;		/* after that it looks quite normal.. */
	__u64 tsize;
	__u64 dsize;
	__u64 bsize;
	__u64 entry;
	__u64 text_start;	/* with a few additions that actually make sense */
	__u64 data_start;
	__u64 bss_start;
	__u32 gprmask, fprmask;	/* bitmask of general & floating point regs used in binary */
	__u64 gpvalue;
};

struct scnhdr
{
	char	s_name[8];
	__u64	s_paddr;
	__u64	s_vaddr;
	__u64	s_size;
	__u64	s_scnptr;
	__u64	s_relptr;
	__u64	s_lnnoptr;
	__u16	s_nreloc;
	__u16	s_nlnno;
	__u32	s_flags;
};

struct exec
{
	/* OSF/1 "file" header */
	struct filehdr		fh;
	struct aouthdr		ah;
};

/*
 * Define's so that the kernel exec code can access the a.out header
 * fields...
 */
#define	a_info		ah.info
#define	a_text		ah.tsize
#define a_data		ah.dsize
#define a_bss		ah.bsize
#define a_entry		ah.entry
#define a_textstart	ah.text_start
#define	a_datastart	ah.data_start
#define	a_bssstart	ah.bss_start
#define	a_gprmask	ah.gprmask
#define a_fprmask	ah.fprmask
#define a_gpvalue	ah.gpvalue

#define N_TXTADDR(x) ((x).a_textstart)
#define N_DATADDR(x) ((x).a_datastart)
#define N_BSSADDR(x) ((x).a_bssstart)
#define N_DRSIZE(x) 0
#define N_TRSIZE(x) 0
#define N_SYMSIZE(x) 0

#define AOUTHSZ		sizeof(struct aouthdr)
#define SCNHSZ		sizeof(struct scnhdr)
#define SCNROUND	16

#define N_TXTOFF(x) \
  ((long) N_MAGIC(x) == ZMAGIC ? 0 : \
   (sizeof(struct exec) + (x).fh.f_nscns*SCNHSZ + SCNROUND - 1) & ~(SCNROUND - 1))

#endif /* _UAPI__ALPHA_A_OUT_H__ */


code:
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef __ASM_ALPHA_AUXVEC_H
#define __ASM_ALPHA_AUXVEC_H

/* Reserve these numbers for any future use of a VDSO.  */
#if 0
#define AT_SYSINFO		32
#define AT_SYSINFO_EHDR		33
#endif

/* More complete cache descriptions than AT_[DIU]CACHEBSIZE.  If the
   value is -1, then the cache doesn't exist.  Otherwise:

      bit 0-3:	  Cache set-associativity; 0 means fully associative.
      bit 4-7:	  Log2 of cacheline size.
      bit 8-31:	  Size of the entire cache >> 8.
      bit 32-63:  Reserved.
*/

#define AT_L1I_CACHESHAPE	34
#define AT_L1D_CACHESHAPE	35
#define AT_L2_CACHESHAPE	36
#define AT_L3_CACHESHAPE	37

#define AT_VECTOR_SIZE_ARCH 4 /* entries in ARCH_DLINFO */

#endif /* __ASM_ALPHA_AUXVEC_H */


code:
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef __ASM_ALPHA_BITSPERLONG_H
#define __ASM_ALPHA_BITSPERLONG_H

#define __BITS_PER_LONG 64

#include <asm-generic/bitsperlong.h>

#endif /* __ASM_ALPHA_BITSPERLONG_H */


code:
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _ALPHA_BYTEORDER_H
#define _ALPHA_BYTEORDER_H

#include <linux/byteorder/little_endian.h>

#endif /* _ALPHA_BYTEORDER_H */


code:
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _UAPI__ALPHA_COMPILER_H
#define _UAPI__ALPHA_COMPILER_H

/*
 * Herein are macros we use when describing various patterns we want to GCC.
 * In all cases we can get better schedules out of the compiler if we hide
 * as little as possible inside inline assembly.  However, we want to be
 * able to know what we'll get out before giving up inline assembly.  Thus
 * these tests and macros.
 */

#if __GNUC__ == 3 && __GNUC_MINOR__ >= 4 || __GNUC__ > 3
# define __kernel_insbl(val, shift)	__builtin_alpha_insbl(val, shift)
# define __kernel_inswl(val, shift)	__builtin_alpha_inswl(val, shift)
# define __kernel_insql(val, shift)	__builtin_alpha_insql(val, shift)
# define __kernel_inslh(val, shift)	__builtin_alpha_inslh(val, shift)
# define __kernel_extbl(val, shift)	__builtin_alpha_extbl(val, shift)
# define __kernel_extwl(val, shift)	__builtin_alpha_extwl(val, shift)
# define __kernel_cmpbge(a, b)		__builtin_alpha_cmpbge(a, b)
#else
# define __kernel_insbl(val, shift)					\
  ({ unsigned long __kir;						\
     __asm__("insbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val));	\
     __kir; })
# define __kernel_inswl(val, shift)					\
  ({ unsigned long __kir;						\
     __asm__("inswl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val));	\
     __kir; })
# define __kernel_insql(val, shift)					\
  ({ unsigned long __kir;						\
     __asm__("insql %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val));	\
     __kir; })
# define __kernel_inslh(val, shift)					\
  ({ unsigned long __kir;						\
     __asm__("inslh %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val));	\
     __kir; })
# define __kernel_extbl(val, shift)					\
  ({ unsigned long __kir;						\
     __asm__("extbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val));	\
     __kir; })
# define __kernel_extwl(val, shift)					\
  ({ unsigned long __kir;						\
     __asm__("extwl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val));	\
     __kir; })
# define __kernel_cmpbge(a, b)						\
  ({ unsigned long __kir;						\
     __asm__("cmpbge %r2,%1,%0" : "=r"(__kir) : "rI"(b), "rJ"(a));	\
     __kir; })
#endif

#ifdef __alpha_cix__
# if __GNUC__ == 3 && __GNUC_MINOR__ >= 4 || __GNUC__ > 3
#  define __kernel_cttz(x)		__builtin_ctzl(x)
#  define __kernel_ctlz(x)		__builtin_clzl(x)
#  define __kernel_ctpop(x)		__builtin_popcountl(x)
# else
#  define __kernel_cttz(x)						\
   ({ unsigned long __kir;						\
      __asm__("cttz %1,%0" : "=r"(__kir) : "r"(x));			\
      __kir; })
#  define __kernel_ctlz(x)						\
   ({ unsigned long __kir;						\
      __asm__("ctlz %1,%0" : "=r"(__kir) : "r"(x));			\
      __kir; })
#  define __kernel_ctpop(x)						\
   ({ unsigned long __kir;						\
      __asm__("ctpop %1,%0" : "=r"(__kir) : "r"(x));			\
      __kir; })
# endif
#else
# define __kernel_cttz(x)						\
  ({ unsigned long __kir;						\
     __asm__(".arch ev67; cttz %1,%0" : "=r"(__kir) : "r"(x));		\
     __kir; })
# define __kernel_ctlz(x)						\
  ({ unsigned long __kir;						\
     __asm__(".arch ev67; ctlz %1,%0" : "=r"(__kir) : "r"(x));		\
     __kir; })
# define __kernel_ctpop(x)						\
  ({ unsigned long __kir;						\
     __asm__(".arch ev67; ctpop %1,%0" : "=r"(__kir) : "r"(x));		\
     __kir; })
#endif

/*
 * Beginning with EGCS 1.1, GCC defines __alpha_bwx__ when the BWX
 * extension is enabled.  Previous versions did not define anything
 * we could test during compilation -- too bad, so sad.
 */

#if defined(__alpha_bwx__)
#define __kernel_ldbu(mem)	(mem)
#define __kernel_ldwu(mem)	(mem)
#define __kernel_stb(val,mem)	((mem) = (val))
#define __kernel_stw(val,mem)	((mem) = (val))
#else
#define __kernel_ldbu(mem)				\
  ({ unsigned char __kir;				\
     __asm__(".arch ev56;				\
	      ldbu %0,%1" : "=r"(__kir) : "m"(mem));	\
     __kir; })
#define __kernel_ldwu(mem)				\
  ({ unsigned short __kir;				\
     __asm__(".arch ev56;				\
	      ldwu %0,%1" : "=r"(__kir) : "m"(mem));	\
     __kir; })
#define __kernel_stb(val,mem)				\
  __asm__(".arch ev56;					\
	   stb %1,%0" : "=m"(mem) : "r"(val))
#define __kernel_stw(val,mem)				\
  __asm__(".arch ev56;					\
	   stw %1,%0" : "=m"(mem) : "r"(val))
#endif

#endif /* _UAPI__ALPHA_COMPILER_H */


code:
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _UAPI__AXP_CONSOLE_H
#define _UAPI__AXP_CONSOLE_H

/*
 * Console callback routine numbers
 */
#define CCB_GETC		0x01
#define CCB_PUTS		0x02
#define CCB_RESET_TERM		0x03
#define CCB_SET_TERM_INT	0x04
#define CCB_SET_TERM_CTL	0x05
#define CCB_PROCESS_KEYCODE	0x06
#define CCB_OPEN_CONSOLE	0x07
#define CCB_CLOSE_CONSOLE	0x08

#define CCB_OPEN		0x10
#define CCB_CLOSE		0x11
#define CCB_IOCTL		0x12
#define CCB_READ		0x13
#define CCB_WRITE		0x14

#define CCB_SET_ENV		0x20
#define CCB_RESET_ENV		0x21
#define CCB_GET_ENV		0x22
#define CCB_SAVE_ENV		0x23

#define CCB_PSWITCH		0x30
#define CCB_BIOS_EMUL		0x32

/*
 * Environment variable numbers
 */
#define ENV_AUTO_ACTION		0x01
#define ENV_BOOT_DEV		0x02
#define ENV_BOOTDEF_DEV		0x03
#define ENV_BOOTED_DEV		0x04
#define ENV_BOOT_FILE		0x05
#define ENV_BOOTED_FILE		0x06
#define ENV_BOOT_OSFLAGS	0x07
#define ENV_BOOTED_OSFLAGS	0x08
#define ENV_BOOT_RESET		0x09
#define ENV_DUMP_DEV		0x0A
#define ENV_ENABLE_AUDIT	0x0B
#define ENV_LICENSE		0x0C
#define ENV_CHAR_SET		0x0D
#define ENV_LANGUAGE		0x0E
#define ENV_TTY_DEV		0x0F

#endif /* _UAPI__AXP_CONSOLE_H */


code:
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _ALPHA_ERRNO_H
#define _ALPHA_ERRNO_H

#include <asm-generic/errno-base.h>

#undef	EAGAIN			/* 11 in errno-base.h */

#define	EDEADLK		11	/* Resource deadlock would occur */

#define	EAGAIN		35	/* Try again */
#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
#define	EINPROGRESS	36	/* Operation now in progress */
#define	EALREADY	37	/* Operation already in progress */
#define	ENOTSOCK	38	/* Socket operation on non-socket */
#define	EDESTADDRREQ	39	/* Destination address required */
#define	EMSGSIZE	40	/* Message too long */
#define	EPROTOTYPE	41	/* Protocol wrong type for socket */
#define	ENOPROTOOPT	42	/* Protocol not available */
#define	EPROTONOSUPPORT	43	/* Protocol not supported */
#define	ESOCKTNOSUPPORT	44	/* Socket type not supported */
#define	EOPNOTSUPP	45	/* Operation not supported on transport endpoint */
#define	EPFNOSUPPORT	46	/* Protocol family not supported */
#define	EAFNOSUPPORT	47	/* Address family not supported by protocol */
#define	EADDRINUSE	48	/* Address already in use */
#define	EADDRNOTAVAIL	49	/* Cannot assign requested address */
#define	ENETDOWN	50	/* Network is down */
#define	ENETUNREACH	51	/* Network is unreachable */
#define	ENETRESET	52	/* Network dropped connection because of reset */
#define	ECONNABORTED	53	/* Software caused connection abort */
#define	ECONNRESET	54	/* Connection reset by peer */
#define	ENOBUFS		55	/* No buffer space available */
#define	EISCONN		56	/* Transport endpoint is already connected */
#define	ENOTCONN	57	/* Transport endpoint is not connected */
#define	ESHUTDOWN	58	/* Cannot send after transport endpoint shutdown */
#define	ETOOMANYREFS	59	/* Too many references: cannot splice */
#define	ETIMEDOUT	60	/* Connection timed out */
#define	ECONNREFUSED	61	/* Connection refused */
#define	ELOOP		62	/* Too many symbolic links encountered */
#define	ENAMETOOLONG	63	/* File name too long */
#define	EHOSTDOWN	64	/* Host is down */
#define	EHOSTUNREACH	65	/* No route to host */
#define	ENOTEMPTY	66	/* Directory not empty */

#define	EUSERS		68	/* Too many users */
#define	EDQUOT		69	/* Quota exceeded */
#define	ESTALE		70	/* Stale file handle */
#define	EREMOTE		71	/* Object is remote */

#define	ENOLCK		77	/* No record locks available */
#define	ENOSYS		78	/* Function not implemented */

#define	ENOMSG		80	/* No message of desired type */
#define	EIDRM		81	/* Identifier removed */
#define	ENOSR		82	/* Out of streams resources */
#define	ETIME		83	/* Timer expired */
#define	EBADMSG		84	/* Not a data message */
#define	EPROTO		85	/* Protocol error */
#define	ENODATA		86	/* No data available */
#define	ENOSTR		87	/* Device not a stream */

#define	ENOPKG		92	/* Package not installed */

#define	EILSEQ		116	/* Illegal byte sequence */

/* The following are just random noise.. */
#define	ECHRNG		88	/* Channel number out of range */
#define	EL2NSYNC	89	/* Level 2 not synchronized */
#define	EL3HLT		90	/* Level 3 halted */
#define	EL3RST		91	/* Level 3 reset */

#define	ELNRNG		93	/* Link number out of range */
#define	EUNATCH		94	/* Protocol driver not attached */
#define	ENOCSI		95	/* No CSI structure available */
#define	EL2HLT		96	/* Level 2 halted */
#define	EBADE		97	/* Invalid exchange */
#define	EBADR		98	/* Invalid request descriptor */
#define	EXFULL		99	/* Exchange full */
#define	ENOANO		100	/* No anode */
#define	EBADRQC		101	/* Invalid request code */
#define	EBADSLT		102	/* Invalid slot */

#define	EDEADLOCK	EDEADLK

#define	EBFONT		104	/* Bad font file format */
#define	ENONET		105	/* Machine is not on the network */
#define	ENOLINK		106	/* Link has been severed */
#define	EADV		107	/* Advertise error */
#define	ESRMNT		108	/* Srmount error */
#define	ECOMM		109	/* Communication error on send */
#define	EMULTIHOP	110	/* Multihop attempted */
#define	EDOTDOT		111	/* RFS specific error */
#define	EOVERFLOW	112	/* Value too large for defined data type */
#define	ENOTUNIQ	113	/* Name not unique on network */
#define	EBADFD		114	/* File descriptor in bad state */
#define	EREMCHG		115	/* Remote address changed */

#define	EUCLEAN		117	/* Structure needs cleaning */
#define	ENOTNAM		118	/* Not a XENIX named type file */
#define	ENAVAIL		119	/* No XENIX semaphores available */
#define	EISNAM		120	/* Is a named type file */
#define	EREMOTEIO	121	/* Remote I/O error */

#define	ELIBACC		122	/* Can not access a needed shared library */
#define	ELIBBAD		123	/* Accessing a corrupted shared library */
#define	ELIBSCN		124	/* .lib section in a.out corrupted */
#define	ELIBMAX		125	/* Attempting to link in too many shared libraries */
#define	ELIBEXEC	126	/* Cannot exec a shared library directly */
#define	ERESTART	127	/* Interrupted system call should be restarted */
#define	ESTRPIPE	128	/* Streams pipe error */

#define ENOMEDIUM	129	/* No medium found */
#define EMEDIUMTYPE	130	/* Wrong medium type */
#define	ECANCELED	131	/* Operation Cancelled */
#define	ENOKEY		132	/* Required key not available */
#define	EKEYEXPIRED	133	/* Key has expired */
#define	EKEYREVOKED	134	/* Key has been revoked */
#define	EKEYREJECTED	135	/* Key was rejected by service */

/* for robust mutexes */
#define	EOWNERDEAD	136	/* Owner died */
#define	ENOTRECOVERABLE	137	/* State not recoverable */

#define	ERFKILL		138	/* Operation not possible due to RF-kill */

#define EHWPOISON	139	/* Memory page has hardware error */

#endif