code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
 */

/dts-v1/;
#include "sparx5_pcb_common.dtsi"

/{
	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
		priority = <200>;
	};

	leds {
		compatible = "gpio-leds";
		led@0 {
			label = "eth60:yellow";
			gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@1 {
			label = "eth60:green";
			gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@2 {
			label = "eth61:yellow";
			gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@3 {
			label = "eth61:green";
			gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@4 {
			label = "eth62:yellow";
			gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@5 {
			label = "eth62:green";
			gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@6 {
			label = "eth63:yellow";
			gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led@7 {
			label = "eth63:green";
			gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};
};

&gpio {
	i2cmux_pins_i: i2cmux-pins-i {
	       pins = "GPIO_35", "GPIO_36",
		      "GPIO_50", "GPIO_51";
		function = "twi_scl_m";
		output-low;
	};
	i2cmux_s29: i2cmux-0 {
		pins = "GPIO_35";
		function = "twi_scl_m";
		output-high;
	};
	i2cmux_s30: i2cmux-1 {
		pins = "GPIO_36";
		function = "twi_scl_m";
		output-high;
	};
	i2cmux_s31: i2cmux-2 {
		pins = "GPIO_50";
		function = "twi_scl_m";
		output-high;
	};
	i2cmux_s32: i2cmux-3 {
		pins = "GPIO_51";
		function = "twi_scl_m";
		output-high;
	};
};

&spi0 {
	status = "okay";
	flash@0 {
		compatible = "jedec,spi-nor";
		spi-max-frequency = <8000000>;
		reg = <0>;
	};
};

&spi0 {
	status = "okay";
	spi@0 {
		compatible = "spi-mux";
		mux-controls = <&mux>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0>; /* CS0 */
		flash@9 {
			compatible = "jedec,spi-nor";
			spi-max-frequency = <8000000>;
			reg = <0x9>; /* SPI */
		};
	};
};

&sgpio1 {
	status = "okay";
	microchip,sgpio-port-ranges = <24 31>;
	gpio@0 {
		ngpios = <64>;
	};
	gpio@1 {
		ngpios = <64>;
	};
};

&sgpio2 {
	status = "okay";
	microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
};

&axi {
	i2c0_imux: i2c0-imux@0 {
		compatible = "i2c-mux-pinctrl";
		#address-cells = <1>;
		#size-cells = <0>;
		i2c-parent = <&i2c0>;
	};
};

&i2c0_imux {
	pinctrl-names =
		"i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",
		"idle";
	pinctrl-0 = <&i2cmux_s29>;
	pinctrl-1 = <&i2cmux_s30>;
	pinctrl-2 = <&i2cmux_s31>;
	pinctrl-3 = <&i2cmux_s32>;
	pinctrl-4 = <&i2cmux_pins_i>;
	i2c_sfp1: i2c_sfp1 {
		reg = <0x0>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
	i2c_sfp2: i2c_sfp2 {
		reg = <0x1>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
	i2c_sfp3: i2c_sfp3 {
		reg = <0x2>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
	i2c_sfp4: i2c_sfp4 {
		reg = <0x3>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
};

&axi {
	sfp_eth60: sfp-eth60 {
		compatible	 = "sff,sfp";
		i2c-bus = <&i2c_sfp1>;
		tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
		rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>;
		los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
		tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
	};
	sfp_eth61: sfp-eth61 {
		compatible = "sff,sfp";
		i2c-bus = <&i2c_sfp2>;
		tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
		rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>;
		los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
		tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
	};
	sfp_eth62: sfp-eth62 {
		compatible = "sff,sfp";
		i2c-bus = <&i2c_sfp3>;
		tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
		rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>;
		los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
		tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
	};
	sfp_eth63: sfp-eth63 {
		compatible = "sff,sfp";
		i2c-bus = <&i2c_sfp4>;
		tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
		rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>;
		los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
		mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
		tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
	};
};

&mdio0 {
	status = "ok";
	phy0: ethernet-phy@0 {
		reg = <0>;
	};
	phy1: ethernet-phy@1 {
		reg = <1>;
	};
	phy2: ethernet-phy@2 {
		reg = <2>;
	};
	phy3: ethernet-phy@3 {
		reg = <3>;
	};
	phy4: ethernet-phy@4 {
		reg = <4>;
	};
	phy5: ethernet-phy@5 {
		reg = <5>;
	};
	phy6: ethernet-phy@6 {
		reg = <6>;
	};
	phy7: ethernet-phy@7 {
		reg = <7>;
	};
	phy8: ethernet-phy@8 {
		reg = <8>;
	};
	phy9: ethernet-phy@9 {
		reg = <9>;
	};
	phy10: ethernet-phy@10 {
		reg = <10>;
	};
	phy11: ethernet-phy@11 {
		reg = <11>;
	};
	phy12: ethernet-phy@12 {
		reg = <12>;
	};
	phy13: ethernet-phy@13 {
		reg = <13>;
	};
	phy14: ethernet-phy@14 {
		reg = <14>;
	};
	phy15: ethernet-phy@15 {
		reg = <15>;
	};
	phy16: ethernet-phy@16 {
		reg = <16>;
	};
	phy17: ethernet-phy@17 {
		reg = <17>;
	};
	phy18: ethernet-phy@18 {
		reg = <18>;
	};
	phy19: ethernet-phy@19 {
		reg = <19>;
	};
	phy20: ethernet-phy@20 {
		reg = <20>;
	};
	phy21: ethernet-phy@21 {
		reg = <21>;
	};
	phy22: ethernet-phy@22 {
		reg = <22>;
	};
	phy23: ethernet-phy@23 {
		reg = <23>;
	};
};

&mdio1 {
	status = "ok";
	phy24: ethernet-phy@24 {
		reg = <0>;
	};
	phy25: ethernet-phy@25 {
		reg = <1>;
	};
	phy26: ethernet-phy@26 {
		reg = <2>;
	};
	phy27: ethernet-phy@27 {
		reg = <3>;
	};
	phy28: ethernet-phy@28 {
		reg = <4>;
	};
	phy29: ethernet-phy@29 {
		reg = <5>;
	};
	phy30: ethernet-phy@30 {
		reg = <6>;
	};
	phy31: ethernet-phy@31 {
		reg = <7>;
	};
	phy32: ethernet-phy@32 {
		reg = <8>;
	};
	phy33: ethernet-phy@33 {
		reg = <9>;
	};
	phy34: ethernet-phy@34 {
		reg = <10>;
	};
	phy35: ethernet-phy@35 {
		reg = <11>;
	};
	phy36: ethernet-phy@36 {
		reg = <12>;
	};
	phy37: ethernet-phy@37 {
		reg = <13>;
	};
	phy38: ethernet-phy@38 {
		reg = <14>;
	};
	phy39: ethernet-phy@39 {
		reg = <15>;
	};
	phy40: ethernet-phy@40 {
		reg = <16>;
	};
	phy41: ethernet-phy@41 {
		reg = <17>;
	};
	phy42: ethernet-phy@42 {
		reg = <18>;
	};
	phy43: ethernet-phy@43 {
		reg = <19>;
	};
	phy44: ethernet-phy@44 {
		reg = <20>;
	};
	phy45: ethernet-phy@45 {
		reg = <21>;
	};
	phy46: ethernet-phy@46 {
		reg = <22>;
	};
	phy47: ethernet-phy@47 {
		reg = <23>;
	};
};

&mdio3 {
	status = "ok";
	phy64: ethernet-phy@64 {
		reg = <28>;
	};
};

&switch {
	ethernet-ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port0: port@0 {
			reg = <0>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 13>;
			phy-handle = <&phy0>;
			phy-mode = "qsgmii";
		};
		port1: port@1 {
			reg = <1>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 13>;
			phy-handle = <&phy1>;
			phy-mode = "qsgmii";
		};
		port2: port@2 {
			reg = <2>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 13>;
			phy-handle = <&phy2>;
			phy-mode = "qsgmii";
		};
		port3: port@3 {
			reg = <3>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 13>;
			phy-handle = <&phy3>;
			phy-mode = "qsgmii";
		};
		port4: port@4 {
			reg = <4>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 14>;
			phy-handle = <&phy4>;
			phy-mode = "qsgmii";
		};
		port5: port@5 {
			reg = <5>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 14>;
			phy-handle = <&phy5>;
			phy-mode = "qsgmii";
		};
		port6: port@6 {
			reg = <6>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 14>;
			phy-handle = <&phy6>;
			phy-mode = "qsgmii";
		};
		port7: port@7 {
			reg = <7>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 14>;
			phy-handle = <&phy7>;
			phy-mode = "qsgmii";
		};
		port8: port@8 {
			reg = <8>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 15>;
			phy-handle = <&phy8>;
			phy-mode = "qsgmii";
		};
		port9: port@9 {
			reg = <9>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 15>;
			phy-handle = <&phy9>;
			phy-mode = "qsgmii";
		};
		port10: port@10 {
			reg = <10>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 15>;
			phy-handle = <&phy10>;
			phy-mode = "qsgmii";
		};
		port11: port@11 {
			reg = <11>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 15>;
			phy-handle = <&phy11>;
			phy-mode = "qsgmii";
		};
		port12: port@12 {
			reg = <12>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 16>;
			phy-handle = <&phy12>;
			phy-mode = "qsgmii";
		};
		port13: port@13 {
			reg = <13>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 16>;
			phy-handle = <&phy13>;
			phy-mode = "qsgmii";
		};
		port14: port@14 {
			reg = <14>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 16>;
			phy-handle = <&phy14>;
			phy-mode = "qsgmii";
		};
		port15: port@15 {
			reg = <15>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 16>;
			phy-handle = <&phy15>;
			phy-mode = "qsgmii";
		};
		port16: port@16 {
			reg = <16>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 17>;
			phy-handle = <&phy16>;
			phy-mode = "qsgmii";
		};
		port17: port@17 {
			reg = <17>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 17>;
			phy-handle = <&phy17>;
			phy-mode = "qsgmii";
		};
		port18: port@18 {
			reg = <18>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 17>;
			phy-handle = <&phy18>;
			phy-mode = "qsgmii";
		};
		port19: port@19 {
			reg = <19>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 17>;
			phy-handle = <&phy19>;
			phy-mode = "qsgmii";
		};
		port20: port@20 {
			reg = <20>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 18>;
			phy-handle = <&phy20>;
			phy-mode = "qsgmii";
		};
		port21: port@21 {
			reg = <21>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 18>;
			phy-handle = <&phy21>;
			phy-mode = "qsgmii";
		};
		port22: port@22 {
			reg = <22>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 18>;
			phy-handle = <&phy22>;
			phy-mode = "qsgmii";
		};
		port23: port@23 {
			reg = <23>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 18>;
			phy-handle = <&phy23>;
			phy-mode = "qsgmii";
		};
		port24: port@24 {
			reg = <24>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 19>;
			phy-handle = <&phy24>;
			phy-mode = "qsgmii";
		};
		port25: port@25 {
			reg = <25>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 19>;
			phy-handle = <&phy25>;
			phy-mode = "qsgmii";
		};
		port26: port@26 {
			reg = <26>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 19>;
			phy-handle = <&phy26>;
			phy-mode = "qsgmii";
		};
		port27: port@27 {
			reg = <27>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 19>;
			phy-handle = <&phy27>;
			phy-mode = "qsgmii";
		};
		port28: port@28 {
			reg = <28>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 20>;
			phy-handle = <&phy28>;
			phy-mode = "qsgmii";
		};
		port29: port@29 {
			reg = <29>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 20>;
			phy-handle = <&phy29>;
			phy-mode = "qsgmii";
		};
		port30: port@30 {
			reg = <30>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 20>;
			phy-handle = <&phy30>;
			phy-mode = "qsgmii";
		};
		port31: port@31 {
			reg = <31>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 20>;
			phy-handle = <&phy31>;
			phy-mode = "qsgmii";
		};
		port32: port@32 {
			reg = <32>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 21>;
			phy-handle = <&phy32>;
			phy-mode = "qsgmii";
		};
		port33: port@33 {
			reg = <33>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 21>;
			phy-handle = <&phy33>;
			phy-mode = "qsgmii";
		};
		port34: port@34 {
			reg = <34>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 21>;
			phy-handle = <&phy34>;
			phy-mode = "qsgmii";
		};
		port35: port@35 {
			reg = <35>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 21>;
			phy-handle = <&phy35>;
			phy-mode = "qsgmii";
		};
		port36: port@36 {
			reg = <36>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 22>;
			phy-handle = <&phy36>;
			phy-mode = "qsgmii";
		};
		port37: port@37 {
			reg = <37>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 22>;
			phy-handle = <&phy37>;
			phy-mode = "qsgmii";
		};
		port38: port@38 {
			reg = <38>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 22>;
			phy-handle = <&phy38>;
			phy-mode = "qsgmii";
		};
		port39: port@39 {
			reg = <39>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 22>;
			phy-handle = <&phy39>;
			phy-mode = "qsgmii";
		};
		port40: port@40 {
			reg = <40>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 23>;
			phy-handle = <&phy40>;
			phy-mode = "qsgmii";
		};
		port41: port@41 {
			reg = <41>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 23>;
			phy-handle = <&phy41>;
			phy-mode = "qsgmii";
		};
		port42: port@42 {
			reg = <42>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 23>;
			phy-handle = <&phy42>;
			phy-mode = "qsgmii";
		};
		port43: port@43 {
			reg = <43>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 23>;
			phy-handle = <&phy43>;
			phy-mode = "qsgmii";
		};
		port44: port@44 {
			reg = <44>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 24>;
			phy-handle = <&phy44>;
			phy-mode = "qsgmii";
		};
		port45: port@45 {
			reg = <45>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 24>;
			phy-handle = <&phy45>;
			phy-mode = "qsgmii";
		};
		port46: port@46 {
			reg = <46>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 24>;
			phy-handle = <&phy46>;
			phy-mode = "qsgmii";
		};
		port47: port@47 {
			reg = <47>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 24>;
			phy-handle = <&phy47>;
			phy-mode = "qsgmii";
		};
		/* Then the 25G interfaces */
		port60: port@60 {
			reg = <60>;
			microchip,bandwidth = <25000>;
			phys = <&serdes 29>;
			phy-mode = "10gbase-r";
			sfp = <&sfp_eth60>;
			managed = "in-band-status";
		};
		port61: port@61 {
			reg = <61>;
			microchip,bandwidth = <25000>;
			phys = <&serdes 30>;
			phy-mode = "10gbase-r";
			sfp = <&sfp_eth61>;
			managed = "in-band-status";
		};
		port62: port@62 {
			reg = <62>;
			microchip,bandwidth = <25000>;
			phys = <&serdes 31>;
			phy-mode = "10gbase-r";
			sfp = <&sfp_eth62>;
			managed = "in-band-status";
		};
		port63: port@63 {
			reg = <63>;
			microchip,bandwidth = <25000>;
			phys = <&serdes 32>;
			phy-mode = "10gbase-r";
			sfp = <&sfp_eth63>;
			managed = "in-band-status";
		};
		/* Finally the Management interface */
		port64: port@64 {
			reg = <64>;
			microchip,bandwidth = <1000>;
			phys = <&serdes 0>;
			phy-handle = <&phy64>;
			phy-mode = "sgmii";
		};
	};
};


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
 */

/dts-v1/;
#include "sparx5_pcb135_board.dtsi"

/ {
	model = "Sparx5 PCB135 Reference Board (eMMC enabled)";
	compatible = "microchip,sparx5-pcb135", "microchip,sparx5";

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x10000000>;
	};
};

&gpio {
	emmc_pins: emmc-pins {
		/* NB: No "GPIO_35", "GPIO_36", "GPIO_37"
		 * (N/A: CARD_nDETECT, CARD_WP, CARD_LED)
		 */
		pins = "GPIO_34", "GPIO_38", "GPIO_39",
			"GPIO_40", "GPIO_41", "GPIO_42",
			"GPIO_43", "GPIO_44", "GPIO_45",
			"GPIO_46", "GPIO_47";
		drive-strength = <3>;
		function = "emmc";
	};
};

&sdhci0 {
	status = "okay";
	pinctrl-0 = <&emmc_pins>;
	non-removable;
	max-frequency = <52000000>;
	bus-width = <8>;
	microchip,clock-delay = <10>;
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
 */

/dts-v1/;
#include "sparx5.dtsi"

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&i2c0 {
	status = "okay";
};


code:
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb


code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com

#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		gcr: system-controller@f0800000 {
			compatible = "nuvoton,npcm845-gcr", "syscon";
			reg = <0x0 0xf0800000 0x0 0x1000>;
		};

		gic: interrupt-controller@dfff9000 {
			compatible = "arm,gic-400";
			reg = <0x0 0xdfff9000 0x0 0x1000>,
			      <0x0 0xdfffa000 0x0 0x2000>,
			      <0x0 0xdfffc000 0x0 0x2000>,
			      <0x0 0xdfffe000 0x0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
			#interrupt-cells = <3>;
			interrupt-controller;
			#address-cells = <0>;
			ppi-partitions {
				ppi_cluster0: interrupt-partition-0 {
					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
				};
			};
		};
	};

	ahb {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		rstc: reset-controller@f0801000 {
			compatible = "nuvoton,npcm845-reset";
			reg = <0x0 0xf0801000 0x0 0x78>;
			#reset-cells = <2>;
			nuvoton,sysgcr = <&gcr>;
		};

		clk: clock-controller@f0801000 {
			compatible = "nuvoton,npcm845-clk";
			#clock-cells = <1>;
			reg = <0x0 0xf0801000 0x0 0x1000>;
		};

		apb {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			interrupt-parent = <&gic>;
			ranges = <0x0 0x0 0xf0000000 0x00300000>,
				<0xfff00000 0x0 0xfff00000 0x00016000>;

			timer0: timer@8000 {
				compatible = "nuvoton,npcm845-timer";
				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x8000 0x1C>;
				clocks = <&clk NPCM8XX_CLK_REFCLK>;
				clock-names = "refclk";
			};

			serial0: serial@0 {
				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
				reg = <0x0 0x1000>;
				clocks = <&clk NPCM8XX_CLK_UART>;
				interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
				reg-shift = <2>;
				status = "disabled";
			};

			serial1: serial@1000 {
				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
				reg = <0x1000 0x1000>;
				clocks = <&clk NPCM8XX_CLK_UART>;
				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
				reg-shift = <2>;
				status = "disabled";
			};

			serial2: serial@2000 {
				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
				reg = <0x2000 0x1000>;
				clocks = <&clk NPCM8XX_CLK_UART>;
				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
				reg-shift = <2>;
				status = "disabled";
			};

			serial3: serial@3000 {
				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
				reg = <0x3000 0x1000>;
				clocks = <&clk NPCM8XX_CLK_UART>;
				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
				reg-shift = <2>;
				status = "disabled";
			};

			serial4: serial@4000 {
				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
				reg = <0x4000 0x1000>;
				clocks = <&clk NPCM8XX_CLK_UART>;
				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
				reg-shift = <2>;
				status = "disabled";
			};

			serial5: serial@5000 {
				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
				reg = <0x5000 0x1000>;
				clocks = <&clk NPCM8XX_CLK_UART>;
				interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
				reg-shift = <2>;
				status = "disabled";
			};

			serial6: serial@6000 {
				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
				reg = <0x6000 0x1000>;
				clocks = <&clk NPCM8XX_CLK_UART>;
				interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
				reg-shift = <2>;
				status = "disabled";
			};

			watchdog0: watchdog@801c {
				compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x801c 0x4>;
				status = "disabled";
				clocks = <&clk NPCM8XX_CLK_REFCLK>;
				syscon = <&gcr>;
			};

			watchdog1: watchdog@901c {
				compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x901c 0x4>;
				status = "disabled";
				clocks = <&clk NPCM8XX_CLK_REFCLK>;
				syscon = <&gcr>;
			};

			watchdog2: watchdog@a01c {
				compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xa01c 0x4>;
				status = "disabled";
				clocks = <&clk NPCM8XX_CLK_REFCLK>;
				syscon = <&gcr>;
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com

/dts-v1/;
#include "nuvoton-npcm845.dtsi"

/ {
	model = "Nuvoton npcm845 Development Board (Device Tree)";
	compatible = "nuvoton,npcm845-evb", "nuvoton,npcm845";

	aliases {
		serial0 = &serial0;
	};

	chosen {
		stdout-path = &serial0;
	};

	memory {
		reg = <0x0 0x0 0x0 0x40000000>;
	};
};

&serial0 {
	status = "okay";
};

&watchdog1 {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com

#include "nuvoton-common-npcm8xx.dtsi"

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			clocks = <&clk NPCM8XX_CLK_CPU>;
			reg = <0x0 0x0>;
			next-level-cache = <&l2>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			clocks = <&clk NPCM8XX_CLK_CPU>;
			reg = <0x0 0x1>;
			next-level-cache = <&l2>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			clocks = <&clk NPCM8XX_CLK_CPU>;
			reg = <0x0 0x2>;
			next-level-cache = <&l2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			clocks = <&clk NPCM8XX_CLK_CPU>;
			reg = <0x0 0x3>;
			next-level-cache = <&l2>;
			enable-method = "psci";
		};

		l2: l2-cache {
			compatible = "cache";
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a35-pmu";
		interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	psci {
		compatible      = "arm,psci-1.0";
		method          = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};
};


code:
# SPDX-License-Identifier: GPL-2.0

# Enables support for device-tree overlays
DTC_FLAGS_tegra210-p2371-2180 := -@
DTC_FLAGS_tegra210-p3450-0000 := -@
DTC_FLAGS_tegra186-p2771-0000 := -@
DTC_FLAGS_tegra186-p3509-0000+p3636-0001 := -@
DTC_FLAGS_tegra194-p2972-0000 := -@
DTC_FLAGS_tegra194-p3509-0000+p3668-0000 := -@
DTC_FLAGS_tegra194-p3509-0000+p3668-0001 := -@
DTC_FLAGS_tegra234-p3737-0000+p3701-0000 := -@

dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p3450-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb
dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p3509-0000+p3636-0001.dtb
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb
dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb
dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb


code:
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include <dt-bindings/input/input.h>
#include "tegra132.dtsi"

/ {
	model = "NVIDIA Tegra132 Norrin";
	compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124";

	aliases {
		rtc0 = "/i2c@7000d000/as3722@40";
		rtc1 = "/rtc@7000e000";
		serial0 = &uarta;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x80000000>;
	};

	host1x@50000000 {
		hdmi@54280000 {
			status = "disabled";

			vdd-supply = <&vdd_3v3_hdmi>;
			pll-supply = <&vdd_hdmi_pll>;
			hdmi-supply = <&vdd_5v0_hdmi>;

			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
			nvidia,hpd-gpio =
				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
		};

		sor@54540000 {
			status = "okay";

			avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>;
			vdd-hdmi-dp-pll-supply = <&vdd_hdmi_pll>;

			nvidia,dpaux = <&dpaux>;
			nvidia,panel = <&panel>;
		};

		dpaux: dpaux@545c0000 {
			vdd-supply = <&vdd_3v3_panel>;
			status = "okay";
		};
	};

	gpu@57000000 {
		status = "okay";

		vdd-supply = <&vdd_gpu>;
	};

	pinmux@70000868 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinmux_default>;

		pinmux_default: pinmux {
			dap_mclk1_pw4 {
				nvidia,pins = "dap_mclk1_pw4";
				nvidia,function = "extperiph1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			dap2_din_pa4 {
				nvidia,pins = "dap2_din_pa4";
				nvidia,function = "i2s1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			dap2_dout_pa5 {
				nvidia,pins = "dap2_dout_pa5",
					      "dap2_fs_pa2",
					      "dap2_sclk_pa3";
				nvidia,function = "i2s1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			dap3_dout_pp2 {
				nvidia,pins = "dap3_dout_pp2";
				nvidia,function = "i2s2";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			dvfs_pwm_px0 {
				nvidia,pins = "dvfs_pwm_px0",
					      "dvfs_clk_px2";
				nvidia,function = "cldvfs";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			ulpi_clk_py0 {
				nvidia,pins = "ulpi_clk_py0",
					      "ulpi_nxt_py2",
					      "ulpi_stp_py3";
				nvidia,function = "spi1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			ulpi_dir_py1 {
				nvidia,pins = "ulpi_dir_py1";
				nvidia,function = "spi1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			cam_i2c_scl_pbb1 {
				nvidia,pins = "cam_i2c_scl_pbb1",
					      "cam_i2c_sda_pbb2";
				nvidia,function = "i2c3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lock = <TEGRA_PIN_DISABLE>;
				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
			};
			gen2_i2c_scl_pt5 {
				nvidia,pins = "gen2_i2c_scl_pt5",
					      "gen2_i2c_sda_pt6";
				nvidia,function = "i2c2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lock = <TEGRA_PIN_DISABLE>;
				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
			};
			pj7 {
				nvidia,pins = "pj7";
				nvidia,function = "uartd";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			spdif_in_pk6 {
				nvidia,pins = "spdif_in_pk6";
				nvidia,function = "spdif";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			pk7 {
				nvidia,pins = "pk7";
				nvidia,function = "uartd";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			pg4 {
				nvidia,pins = "pg4",
					      "pg5",
					      "pg6",
					      "pi3";
				nvidia,function = "spi4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			pg7 {
				nvidia,pins = "pg7";
				nvidia,function = "spi4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			ph1 {
				nvidia,pins = "ph1";
				nvidia,function = "pwm1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			pk0 {
				nvidia,pins = "pk0",
					      "kb_row15_ps7",
					      "clk_32k_out_pa0";
				nvidia,function = "soc";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			sdmmc1_clk_pz0 {
				nvidia,pins = "sdmmc1_clk_pz0";
				nvidia,function = "sdmmc1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			sdmmc1_cmd_pz1 {
				nvidia,pins = "sdmmc1_cmd_pz1",
					      "sdmmc1_dat0_py7",
					      "sdmmc1_dat1_py6",
					      "sdmmc1_dat2_py5",
					      "sdmmc1_dat3_py4";
				nvidia,function = "sdmmc1";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			sdmmc3_clk_pa6 {
				nvidia,pins = "sdmmc3_clk_pa6";
				nvidia,function = "sdmmc3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			sdmmc3_cmd_pa7 {
				nvidia,pins = "sdmmc3_cmd_pa7",
					      "sdmmc3_dat0_pb7",
					      "sdmmc3_dat1_pb6",
					      "sdmmc3_dat2_pb5",
					      "sdmmc3_dat3_pb4",
					      "kb_col4_pq4",
					      "sdmmc3_clk_lb_out_pee4",
					      "sdmmc3_clk_lb_in_pee5",
					      "sdmmc3_cd_n_pv2";
				nvidia,function = "sdmmc3";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			sdmmc4_clk_pcc4 {
				nvidia,pins = "sdmmc4_clk_pcc4";
				nvidia,function = "sdmmc4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			sdmmc4_cmd_pt7 {
				nvidia,pins = "sdmmc4_cmd_pt7",
					      "sdmmc4_dat0_paa0",
					      "sdmmc4_dat1_paa1",
					      "sdmmc4_dat2_paa2",
					      "sdmmc4_dat3_paa3",
					      "sdmmc4_dat4_paa4",
					      "sdmmc4_dat5_paa5",
					      "sdmmc4_dat6_paa6",
					      "sdmmc4_dat7_paa7";
				nvidia,function = "sdmmc4";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			mic_det_l {
				nvidia,pins = "kb_row7_pr7";
				nvidia,function = "rsvd2";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			kb_row10_ps2 {
				nvidia,pins = "kb_row10_ps2";
				nvidia,function = "uarta";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			kb_row9_ps1 {
				nvidia,pins = "kb_row9_ps1";
				nvidia,function = "uarta";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			pwr_i2c_scl_pz6 {
				nvidia,pins = "pwr_i2c_scl_pz6",
					      "pwr_i2c_sda_pz7";
				nvidia,function = "i2cpwr";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lock = <TEGRA_PIN_DISABLE>;
				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
			};
			jtag_rtck {
				nvidia,pins = "jtag_rtck";
				nvidia,function = "rtck";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			clk_32k_in {
				nvidia,pins = "clk_32k_in";
				nvidia,function = "clk";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			core_pwr_req {
				nvidia,pins = "core_pwr_req";
				nvidia,function = "pwron";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			cpu_pwr_req {
				nvidia,pins = "cpu_pwr_req";
				nvidia,function = "cpu";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			kb_col0_ap {
				nvidia,pins = "kb_col0_pq0";
				nvidia,function = "rsvd4";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			en_vdd_sd {
				nvidia,pins = "kb_row0_pr0";
				nvidia,function = "rsvd4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			lid_open {
				nvidia,pins = "kb_row4_pr4";
				nvidia,function = "rsvd3";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			pwr_int_n {
				nvidia,pins = "pwr_int_n";
				nvidia,function = "pmi";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			reset_out_n {
				nvidia,pins = "reset_out_n";
				nvidia,function = "reset_out_n";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			clk3_out_pee0 {
				nvidia,pins = "clk3_out_pee0";
				nvidia,function = "extperiph3";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			gen1_i2c_scl_pc4 {
				nvidia,pins = "gen1_i2c_scl_pc4",
					      "gen1_i2c_sda_pc5";
				nvidia,function = "i2c1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lock = <TEGRA_PIN_DISABLE>;
				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
			};
			hdmi_cec_pee3 {
				nvidia,pins = "hdmi_cec_pee3";
				nvidia,function = "cec";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lock = <TEGRA_PIN_DISABLE>;
				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
			};
			hdmi_int_pn7 {
				nvidia,pins = "hdmi_int_pn7";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			ddc_scl_pv4 {
				nvidia,pins = "ddc_scl_pv4",
					      "ddc_sda_pv5";
				nvidia,function = "i2c4";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lock = <TEGRA_PIN_DISABLE>;
				nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
			};
			usb_vbus_en0_pn4 {
				nvidia,pins = "usb_vbus_en0_pn4",
					      "usb_vbus_en1_pn5",
					      "usb_vbus_en2_pff1";
				nvidia,function = "usb";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
				nvidia,lock = <TEGRA_PIN_DISABLE>;
				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
			};
			drive_sdio1 {
				nvidia,pins = "drive_sdio1";
				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
				nvidia,pull-down-strength = <36>;
				nvidia,pull-up-strength = <20>;
				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
			};
			drive_sdio3 {
				nvidia,pins = "drive_sdio3";
				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
				nvidia,pull-down-strength = <22>;
				nvidia,pull-up-strength = <36>;
				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
			};
			drive_gma {
				nvidia,pins = "drive_gma";
				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
				nvidia,pull-down-strength = <2>;
				nvidia,pull-up-strength = <1>;
				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
				nvidia,drive-type = <1>;
			};
			ac_ok {
				nvidia,pins = "pj0";
				nvidia,function = "gmi";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			codec_irq_l {
				nvidia,pins = "ph4";
				nvidia,function = "gmi";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			lcd_bl_en {
				nvidia,pins = "ph2";
				nvidia,function = "gmi";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			touch_irq_l {
				nvidia,pins = "gpio_w3_aud_pw3";
				nvidia,function = "spi6";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			tpm_davint_l {
				nvidia,pins = "ph6";
				nvidia,function = "gmi";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			ts_irq_l {
				nvidia,pins = "pk2";
				nvidia,function = "gmi";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			ts_reset_l {
				nvidia,pins = "pk4";
				nvidia,function = "gmi";
				nvidia,pull = <1>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			ts_shdn_l {
				nvidia,pins = "pk1";
				nvidia,function = "gmi";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			ph7 {
				nvidia,pins = "ph7";
				nvidia,function = "gmi";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			sensor_irq_l {
				nvidia,pins = "pi6";
				nvidia,function = "gmi";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			wifi_en {
				nvidia,pins = "gpio_x7_aud_px7";
				nvidia,function = "rsvd4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
			chromeos_write_protect {
				nvidia,pins = "kb_row1_pr1";
				nvidia,function = "rsvd4";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			hp_det_l {
				nvidia,pins = "pi7";
				nvidia,function = "rsvd1";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			};
			soc_warm_reset_l {
				nvidia,pins = "pi5";
				nvidia,function = "gmi";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			};
		};
	};

	serial@70006000 {
		status = "okay";
	};

	pwm: pwm@7000a000 {
		status = "okay";
	};

	/* HDMI DDC */
	hdmi_ddc: i2c@7000c700 {
		status = "okay";
		clock-frequency = <100000>;
	};

	i2c@7000d000 {
		status = "okay";
		clock-frequency = <400000>;

		as3722: pmic@40 {
			compatible = "ams,as3722";
			reg = <0x40>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

			ams,system-power-controller;

			#interrupt-cells = <2>;
			interrupt-controller;

			#gpio-cells = <2>;
			gpio-controller;

			pinctrl-names = "default";
			pinctrl-0 = <&as3722_default>;

			as3722_default: pinmux {
				gpio0 {
					pins = "gpio0";
					function = "gpio";
					bias-pull-down;
				};

				gpio1 {
					pins = "gpio1";
					function = "gpio";
					bias-pull-up;
				};

				gpio2_4_7 {
					pins = "gpio2", "gpio4", "gpio7";
					function = "gpio";
					bias-pull-up;
				};

				gpio3 {
					pins = "gpio3";
					function = "gpio";
					bias-high-impedance;
				};

				gpio5 {
					pins = "gpio5";
					function = "clk32k-out";
					bias-pull-down;
				};

				gpio6 {
					pins = "gpio6";
					function = "clk32k-out";
					bias-pull-down;
				};
			};

			regulators {
				vsup-sd2-supply = <&vdd_5v0_sys>;
				vsup-sd3-supply = <&vdd_5v0_sys>;
				vsup-sd4-supply = <&vdd_5v0_sys>;
				vsup-sd5-supply = <&vdd_5v0_sys>;
				vin-ldo0-supply = <&vdd_1v35_lp0>;
				vin-ldo1-6-supply = <&vdd_3v3_sys>;
				vin-ldo2-5-7-supply = <&vddio_1v8>;
				vin-ldo3-4-supply = <&vdd_3v3_sys>;
				vin-ldo9-10-supply = <&vdd_5v0_sys>;
				vin-ldo11-supply = <&vdd_3v3_run>;

				sd0 {
					regulator-name = "+VDD_CPU_AP";
					regulator-min-microvolt = <700000>;
					regulator-max-microvolt = <1350000>;
					regulator-max-microamp = <3500000>;
					regulator-always-on;
					regulator-boot-on;
					ams,ext-control = <2>;
				};

				sd1 {
					regulator-name = "+VDD_CORE";
					regulator-min-microvolt = <700000>;
					regulator-max-microvolt = <1350000>;
					regulator-max-microamp = <4000000>;
					regulator-always-on;
					regulator-boot-on;
					ams,ext-control = <1>;
				};

				vdd_1v35_lp0: sd2 {
					regulator-name = "+1.35V_LP0(sd2)";
					regulator-min-microvolt = <1350000>;
					regulator-max-microvolt = <1350000>;
					regulator-always-on;
					regulator-boot-on;
				};

				sd3 {
					regulator-name = "+1.35V_LP0(sd3)";
					regulator-min-microvolt = <1350000>;
					regulator-max-microvolt = <1350000>;
					regulator-always-on;
					regulator-boot-on;
				};

				vdd_1v05_run: sd4 {
					regulator-name = "+1.05V_RUN";
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
				};

				vddio_1v8: sd5 {
					regulator-name = "+1.8V_VDDIO";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				vdd_gpu: sd6 {
					regulator-name = "+VDD_GPU_AP";
					regulator-min-microvolt = <800000>;
					regulator-max-microvolt = <1200000>;
					regulator-min-microamp = <3500000>;
					regulator-max-microamp = <3500000>;
					regulator-always-on;
					regulator-boot-on;
				};

				avdd_1v05_run: ldo0 {
					regulator-name = "+1.05_RUN_AVDD";
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
					regulator-always-on;
					regulator-boot-on;
					ams,ext-control = <1>;
				};

				ldo1 {
					regulator-name = "+1.8V_RUN_CAM";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
				};

				ldo2 {
					regulator-name = "+1.2V_GEN_AVDD";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo3 {
					regulator-name = "+1.00V_LP0_VDD_RTC";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1000000>;
					regulator-always-on;
					regulator-boot-on;
					ams,enable-tracking;
				};

				vdd_run_cam: ldo4 {
					regulator-name = "+2.8V_RUN_CAM";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <2800000>;
				};

				ldo5 {
					regulator-name = "+1.2V_RUN_CAM_FRONT";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
				};

				vddio_sdmmc3: ldo6 {
					regulator-name = "+VDDIO_SDMMC3";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3300000>;
				};

				ldo7 {
					regulator-name = "+1.05V_RUN_CAM_REAR";
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
				};

				ldo9 {
					regulator-name = "+2.8V_RUN_TOUCH";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <2800000>;
				};

				ldo10 {
					regulator-name = "+2.8V_RUN_CAM_AF";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <2800000>;
				};

				ldo11 {
					regulator-name = "+1.8V_RUN_VPP_FUSE";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
				};
			};
		};
	};

	spi@7000d400 {
		status = "okay";

		ec: cros-ec@0 {
			compatible = "google,cros-ec-spi";
			spi-max-frequency = <3000000>;
			interrupt-parent = <&gpio>;
			interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
			reg = <0>;

			google,cros-ec-spi-msg-delay = <2000>;

			i2c_20: i2c-tunnel {
				compatible = "google,cros-ec-i2c-tunnel";
				#address-cells = <1>;
				#size-cells = <0>;

				google,remote-bus = <0>;

				charger: bq24735@9 {
					compatible = "ti,bq24735";
					reg = <0x9>;
					interrupt-parent = <&gpio>;
					interrupts = <TEGRA_GPIO(J, 0)
							GPIO_ACTIVE_HIGH>;
					ti,ac-detect-gpios = <&gpio
							TEGRA_GPIO(J, 0)
							GPIO_ACTIVE_HIGH>;
				};

				battery: smart-battery@b {
					compatible = "sbs,sbs-battery";
					reg = <0xb>;
					sbs,i2c-retry-count = <2>;
					sbs,poll-retry-count = <10>;
				/*	power-supplies = <&charger>; */
				};
			};

			keyboard-controller {
				compatible = "google,cros-ec-keyb";
				keypad,num-rows = <8>;
				keypad,num-columns = <13>;
				google,needs-ghost-filter;
				linux,keymap =
					<MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
					 MATRIX_KEY(0x00, 0x02, KEY_F1)
					 MATRIX_KEY(0x00, 0x03, KEY_B)
					 MATRIX_KEY(0x00, 0x04, KEY_F10)
					 MATRIX_KEY(0x00, 0x06, KEY_N)
					 MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
					 MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)

					 MATRIX_KEY(0x01, 0x01, KEY_ESC)
					 MATRIX_KEY(0x01, 0x02, KEY_F4)
					 MATRIX_KEY(0x01, 0x03, KEY_G)
					 MATRIX_KEY(0x01, 0x04, KEY_F7)
					 MATRIX_KEY(0x01, 0x06, KEY_H)
					 MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
					 MATRIX_KEY(0x01, 0x09, KEY_F9)
					 MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)

					 MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
					 MATRIX_KEY(0x02, 0x01, KEY_TAB)
					 MATRIX_KEY(0x02, 0x02, KEY_F3)
					 MATRIX_KEY(0x02, 0x03, KEY_T)
					 MATRIX_KEY(0x02, 0x04, KEY_F6)
					 MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
					 MATRIX_KEY(0x02, 0x06, KEY_Y)
					 MATRIX_KEY(0x02, 0x07, KEY_102ND)
					 MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
					 MATRIX_KEY(0x02, 0x09, KEY_F8)

					 MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
					 MATRIX_KEY(0x03, 0x02, KEY_F2)
					 MATRIX_KEY(0x03, 0x03, KEY_5)
					 MATRIX_KEY(0x03, 0x04, KEY_F5)
					 MATRIX_KEY(0x03, 0x06, KEY_6)
					 MATRIX_KEY(0x03, 0x08, KEY_MINUS)
					 MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)

					 MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
					 MATRIX_KEY(0x04, 0x01, KEY_A)
					 MATRIX_KEY(0x04, 0x02, KEY_D)
					 MATRIX_KEY(0x04, 0x03, KEY_F)
					 MATRIX_KEY(0x04, 0x04, KEY_S)
					 MATRIX_KEY(0x04, 0x05, KEY_K)
					 MATRIX_KEY(0x04, 0x06, KEY_J)
					 MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
					 MATRIX_KEY(0x04, 0x09, KEY_L)
					 MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
					 MATRIX_KEY(0x04, 0x0b, KEY_ENTER)

					 MATRIX_KEY(0x05, 0x01, KEY_Z)
					 MATRIX_KEY(0x05, 0x02, KEY_C)
					 MATRIX_KEY(0x05, 0x03, KEY_V)
					 MATRIX_KEY(0x05, 0x04, KEY_X)
					 MATRIX_KEY(0x05, 0x05, KEY_COMMA)
					 MATRIX_KEY(0x05, 0x06, KEY_M)
					 MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
					 MATRIX_KEY(0x05, 0x08, KEY_SLASH)
					 MATRIX_KEY(0x05, 0x09, KEY_DOT)
					 MATRIX_KEY(0x05, 0x0b, KEY_SPACE)

					 MATRIX_KEY(0x06, 0x01, KEY_1)
					 MATRIX_KEY(0x06, 0x02, KEY_3)
					 MATRIX_KEY(0x06, 0x03, KEY_4)
					 MATRIX_KEY(0x06, 0x04, KEY_2)
					 MATRIX_KEY(0x06, 0x05, KEY_8)
					 MATRIX_KEY(0x06, 0x06, KEY_7)
					 MATRIX_KEY(0x06, 0x08, KEY_0)
					 MATRIX_KEY(0x06, 0x09, KEY_9)
					 MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
					 MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
					 MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)

					 MATRIX_KEY(0x07, 0x01, KEY_Q)
					 MATRIX_KEY(0x07, 0x02, KEY_E)
					 MATRIX_KEY(0x07, 0x03, KEY_R)
					 MATRIX_KEY(0x07, 0x04, KEY_W)
					 MATRIX_KEY(0x07, 0x05, KEY_I)
					 MATRIX_KEY(0x07, 0x06, KEY_U)
					 MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
					 MATRIX_KEY(0x07, 0x08, KEY_P)
					 MATRIX_KEY(0x07, 0x09, KEY_O)
					 MATRIX_KEY(0x07, 0x0b, KEY_UP)
					 MATRIX_KEY(0x07, 0x0c, KEY_LEFT)>;
			};
		};
	};

	pmc@7000e400 {
		nvidia,invert-interrupt;
		nvidia,suspend-mode = <0>;
		nvidia,cpu-pwr-good-time = <500>;
		nvidia,cpu-pwr-off-time = <300>;
		nvidia,core-pwr-good-time = <641 3845>;
		nvidia,core-pwr-off-time = <61036>;
		nvidia,core-power-req-active-high;
		nvidia,sys-clock-req-active-high;
	};

	usb@70090000 {
		phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
		       <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
		       <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
		       <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
		       <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
		phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";

		avddio-pex-supply = <&vdd_1v05_run>;
		dvddio-pex-supply = <&vdd_1v05_run>;
		avdd-usb-supply = <&vdd_3v3_lp0>;
		hvdd-usb-ss-supply = <&vdd_3v3_lp0>;

		status = "okay";
	};

	padctl@7009f000 {
		avdd-pll-utmip-supply = <&vddio_1v8>;
		avdd-pll-erefe-supply = <&avdd_1v05_run>;
		avdd-pex-pll-supply = <&vdd_1v05_run>;
		hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;

		pads {
			usb2 {
				status = "okay";

				lanes {
					usb2-0 {
						nvidia,function = "xusb";
						status = "okay";
					};

					usb2-1 {
						nvidia,function = "xusb";
						status = "okay";
					};

					usb2-2 {
						nvidia,function = "xusb";
						status = "okay";
					};
				};
			};

			pcie {
				status = "okay";

				lanes {
					pcie-0 {
						nvidia,function = "usb3-ss";
						status = "okay";
					};

					pcie-1 {
						nvidia,function = "usb3-ss";
						status = "okay";
					};
				};
			};
		};

		ports {
			usb2-0 {
				status = "okay";
				mode = "otg";

				vbus-supply = <&vdd_usb1_vbus>;
			};

			usb2-1 {
				status = "okay";
				mode = "host";

				vbus-supply = <&vdd_run_cam>;
			};

			usb2-2 {
				status = "okay";
				mode = "host";

				vbus-supply = <&vdd_usb3_vbus>;
			};

			usb3-0 {
				nvidia,usb2-companion = <0>;
				status = "okay";
			};

			usb3-1 {
				nvidia,usb2-companion = <2>;
				status = "okay";
			};
		};
	};

	/* WIFI/BT module */
	mmc@700b0000 {
		status = "disabled";
	};

	/* external SD/MMC */
	mmc@700b0400 {
		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
		power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
		wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
		status = "okay";
		bus-width = <4>;
		vqmmc-supply = <&vddio_sdmmc3>;
	};

	/* EMMC 4.51 */
	mmc@700b0600 {
		status = "okay";
		bus-width = <8>;
		non-removable;
	};

	backlight: backlight {
		compatible = "pwm-backlight";

		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
		power-supply = <&vdd_led>;
		pwms = <&pwm 1 1000000>;

		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
	};

	clk32k_in: clock-32k {
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		#clock-cells = <0>;
	};

	gpio-keys {
		compatible = "gpio-keys";

		switch-lid {
			label = "Lid";
			gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
			linux,input-type = <5>;
			linux,code = <0>;
			debounce-interval = <1>;
			wakeup-source;
		};

		key-power {
			label = "Power";
			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
			linux,code = <KEY_POWER>;
			debounce-interval = <10>;
			wakeup-source;
		};
	};

	panel: panel {
		compatible = "innolux,n116bge";
		power-supply = <&vdd_3v3_panel>;
		backlight = <&backlight>;
		ddc-i2c-bus = <&dpaux>;
	};

	vdd_mux: regulator-vdd-mux {
		compatible = "regulator-fixed";
		regulator-name = "+VDD_MUX";
		regulator-min-microvolt = <19000000>;
		regulator-max-microvolt = <19000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_5v0_sys: regulator-vdd-5v0-sys {
		compatible = "regulator-fixed";
		regulator-name = "+5V_SYS";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <&vdd_mux>;
	};

	vdd_3v3_sys: regulator-vdd-3v3-sys {
		compatible = "regulator-fixed";
		regulator-name = "+3.3V_SYS";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
		vin-supply = <&vdd_mux>;
	};

	vdd_3v3_run: regulator-vdd-3v3-run {
		compatible = "regulator-fixed";
		regulator-name = "+3.3V_RUN";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
		gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&vdd_3v3_sys>;
	};

	vdd_3v3_hdmi: regulator-vdd-3v3-hdmi {
		compatible = "regulator-fixed";
		regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&vdd_3v3_run>;
	};

	vdd_led: regulator-vdd-led {
		compatible = "regulator-fixed";
		regulator-name = "+VDD_LED";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&vdd_mux>;
	};

	vdd_usb1_vbus: regulator-vdd-usb1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "+5V_USB_HS";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
		enable-active-high;
		gpio-open-drain;
		vin-supply = <&vdd_5v0_sys>;
	};

	vdd_usb3_vbus: regulator-vdd-usb3-vbus {
		compatible = "regulator-fixed";
		regulator-name = "+5V_USB_SS";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
		enable-active-high;
		gpio-open-drain;
		vin-supply = <&vdd_5v0_sys>;
	};

	vdd_3v3_panel: regulator-vdd-3v3-panel {
		compatible = "regulator-fixed";
		regulator-name = "+3.3V_PANEL";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&vdd_3v3_sys>;
	};

	vdd_hdmi_pll: regulator-vdd-hdmi-pll {
		compatible = "regulator-fixed";
		regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE";
		regulator-min-microvolt = <1050000>;
		regulator-max-microvolt = <1050000>;
		gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
		vin-supply = <&vdd_1v05_run>;
	};

	vdd_5v0_hdmi: regulator-vdd-5v0-hdmi {
		compatible = "regulator-fixed";
		regulator-name = "+5V_HDMI_CON";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&vdd_5v0_sys>;
	};

	vdd_5v0_ts: regulator-vdd-5v0-ts {
		compatible = "regulator-fixed";
		regulator-name = "+5V_VDD_TS";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-always-on;
		regulator-boot-on;
		gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	vdd_3v3_lp0: regulator-vdd-3v3-lp0 {
		compatible = "regulator-fixed";
		regulator-name = "+3.3V_LP0";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		/*
		 * TODO: find a way to wire this up with the USB EHCI
		 * controllers so that it can be enabled on demand.
		 */
		regulator-always-on;
		gpio = <&as3722 2 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		vin-supply = <&vdd_3v3_sys>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra124-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
#include <dt-bindings/soc/tegra-pmc.h>

#include "tegra132-peripherals-opp.dtsi"

/ {
	compatible = "nvidia,tegra132", "nvidia,tegra124";
	interrupt-parent = <&lic>;
	#address-cells = <2>;
	#size-cells = <2>;

	pcie@1003000 {
		compatible = "nvidia,tegra124-pcie";
		device_type = "pci";
		reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
		      <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
		      <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
		reg-names = "pads", "afi", "cs";
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
		interrupt-names = "intr", "msi";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

		bus-range = <0x00 0xff>;
		#address-cells = <3>;
		#size-cells = <2>;

		ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
			 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
			 <0x01000000 0 0x0        0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
			 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
			 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */

		clocks = <&tegra_car TEGRA124_CLK_PCIE>,
			 <&tegra_car TEGRA124_CLK_AFI>,
			 <&tegra_car TEGRA124_CLK_PLL_E>,
			 <&tegra_car TEGRA124_CLK_CML0>;
		clock-names = "pex", "afi", "pll_e", "cml";
		resets = <&tegra_car 70>,
			 <&tegra_car 72>,
			 <&tegra_car 74>;
		reset-names = "pex", "afi", "pcie_x";
		status = "disabled";

		pci@1,0 {
			device_type = "pci";
			assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
			reg = <0x000800 0 0 0 0>;
			bus-range = <0x00 0xff>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <2>;
		};

		pci@2,0 {
			device_type = "pci";
			assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
			reg = <0x001000 0 0 0 0>;
			bus-range = <0x00 0xff>;
			status = "disabled";

			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			nvidia,num-lanes = <1>;
		};
	};

	host1x@50000000 {
		compatible = "nvidia,tegra132-host1x",
			     "nvidia,tegra124-host1x";
		reg = <0x0 0x50000000 0x0 0x00034000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
		interrupt-names = "syncpt", "host1x";
		clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
		clock-names = "host1x";
		resets = <&tegra_car 28>;
		reset-names = "host1x";

		#address-cells = <2>;
		#size-cells = <2>;

		ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;

		dc@54200000 {
			compatible = "nvidia,tegra124-dc";
			reg = <0x0 0x54200000 0x0 0x00040000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA124_CLK_DISP1>;
			clock-names = "dc";
			resets = <&tegra_car 27>;
			reset-names = "dc";

			iommus = <&mc TEGRA_SWGROUP_DC>;

			nvidia,head = <0>;
		};

		dc@54240000 {
			compatible = "nvidia,tegra124-dc";
			reg = <0x0 0x54240000 0x0 0x00040000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA124_CLK_DISP2>;
			clock-names = "dc";
			resets = <&tegra_car 26>;
			reset-names = "dc";

			iommus = <&mc TEGRA_SWGROUP_DCB>;

			nvidia,head = <1>;
		};

		hdmi@54280000 {
			compatible = "nvidia,tegra124-hdmi";
			reg = <0x0 0x54280000 0x0 0x00040000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA124_CLK_HDMI>,
				 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
			clock-names = "hdmi", "parent";
			resets = <&tegra_car 51>;
			reset-names = "hdmi";
			status = "disabled";
		};

		sor@54540000 {
			compatible = "nvidia,tegra124-sor";
			reg = <0x0 0x54540000 0x0 0x00040000>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA124_CLK_SOR0>,
				 <&tegra_car TEGRA124_CLK_SOR0_OUT>,
				 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
				 <&tegra_car TEGRA124_CLK_PLL_DP>,
				 <&tegra_car TEGRA124_CLK_CLK_M>;
			clock-names = "sor", "out", "parent", "dp", "safe";
			resets = <&tegra_car 182>;
			reset-names = "sor";
			status = "disabled";
		};

		dpaux: dpaux@545c0000 {
			compatible = "nvidia,tegra124-dpaux";
			reg = <0x0 0x545c0000 0x0 0x00040000>;
			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
				 <&tegra_car TEGRA124_CLK_PLL_DP>;
			clock-names = "dpaux", "parent";
			resets = <&tegra_car 181>;
			reset-names = "dpaux";
			status = "disabled";

			i2c-bus {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};
	};

	gic: interrupt-controller@50041000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x50041000 0x0 0x1000>,
		      <0x0 0x50042000 0x0 0x2000>,
		      <0x0 0x50044000 0x0 0x2000>,
		      <0x0 0x50046000 0x0 0x2000>;
		interrupts = <GIC_PPI 9
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-parent = <&gic>;
	};

	gpu@57000000 {
		compatible = "nvidia,gk20a";
		reg = <0x0 0x57000000 0x0 0x01000000>,
		      <0x0 0x58000000 0x0 0x01000000>;
		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "stall", "nonstall";
		clocks = <&tegra_car TEGRA124_CLK_GPU>,
			 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
		clock-names = "gpu", "pwr";
		resets = <&tegra_car 184>;
		reset-names = "gpu";
		status = "disabled";
	};

	lic: interrupt-controller@60004000 {
		compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
		reg = <0x0 0x60004000 0x0 0x100>,
		      <0x0 0x60004100 0x0 0x100>,
		      <0x0 0x60004200 0x0 0x100>,
		      <0x0 0x60004300 0x0 0x100>,
		      <0x0 0x60004400 0x0 0x100>;
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer";
		reg = <0x0 0x60005000 0x0 0x400>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_TIMER>;
		clock-names = "timer";
	};

	tegra_car: clock@60006000 {
		compatible = "nvidia,tegra132-car";
		reg = <0x0 0x60006000 0x0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		nvidia,external-memory-controller = <&emc>;
	};

	flow-controller@60007000 {
		compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl";
		reg = <0x0 0x60007000 0x0 0x1000>;
	};

	actmon@6000c800 {
		compatible = "nvidia,tegra124-actmon";
		reg = <0x0 0x6000c800 0x0 0x400>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
			 <&tegra_car TEGRA124_CLK_EMC>;
		clock-names = "actmon", "emc";
		resets = <&tegra_car 119>;
		reset-names = "actmon";
		operating-points-v2 = <&emc_bw_dfs_opp_table>;
		interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
		interconnect-names = "cpu-read";
		#cooling-cells = <2>;
	};

	gpio: gpio@6000d000 {
		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
		reg = <0x0 0x6000d000 0x0 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	apbdma: dma@60020000 {
		compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
		reg = <0x0 0x60020000 0x0 0x1400>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
		clock-names = "dma";
		resets = <&tegra_car 34>;
		reset-names = "dma";
		#dma-cells = <1>;
	};

	apbmisc@70000800 {
		compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
		reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
		      <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
	};

	pinmux: pinmux@70000868 {
		compatible = "nvidia,tegra124-pinmux";
		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
		      <0x0 0x70003000 0x0 0x434>, /* Mux registers */
		      <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performance. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
	 * the APB DMA based serial driver, the compatible is
	 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x70006000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTA>;
		clock-names = "serial";
		resets = <&tegra_car 6>;
		reset-names = "serial";
		dmas = <&apbdma 8>, <&apbdma 8>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x70006040 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTB>;
		clock-names = "serial";
		resets = <&tegra_car 7>;
		reset-names = "serial";
		dmas = <&apbdma 9>, <&apbdma 9>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x70006200 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTC>;
		clock-names = "serial";
		resets = <&tegra_car 55>;
		reset-names = "serial";
		dmas = <&apbdma 10>, <&apbdma 10>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x70006300 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_UARTD>;
		clock-names = "serial";
		resets = <&tegra_car 65>;
		reset-names = "serial";
		dmas = <&apbdma 19>, <&apbdma 19>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	pwm: pwm@7000a000 {
		compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
		reg = <0x0 0x7000a000 0x0 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car TEGRA124_CLK_PWM>;
		resets = <&tegra_car 17>;
		reset-names = "pwm";
		status = "disabled";
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra124-i2c";
		reg = <0x0 0x7000c000 0x0 0x100>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C1>;
		clock-names = "div-clk";
		resets = <&tegra_car 12>;
		reset-names = "i2c";
		dmas = <&apbdma 21>, <&apbdma 21>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra124-i2c";
		reg = <0x0 0x7000c400 0x0 0x100>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C2>;
		clock-names = "div-clk";
		resets = <&tegra_car 54>;
		reset-names = "i2c";
		dmas = <&apbdma 22>, <&apbdma 22>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra124-i2c";
		reg = <0x0 0x7000c500 0x0 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C3>;
		clock-names = "div-clk";
		resets = <&tegra_car 67>;
		reset-names = "i2c";
		dmas = <&apbdma 23>, <&apbdma 23>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra124-i2c";
		reg = <0x0 0x7000c700 0x0 0x100>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C4>;
		clock-names = "div-clk";
		resets = <&tegra_car 103>;
		reset-names = "i2c";
		dmas = <&apbdma 26>, <&apbdma 26>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra124-i2c";
		reg = <0x0 0x7000d000 0x0 0x100>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C5>;
		clock-names = "div-clk";
		resets = <&tegra_car 47>;
		reset-names = "i2c";
		dmas = <&apbdma 24>, <&apbdma 24>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	i2c@7000d100 {
		compatible = "nvidia,tegra124-i2c";
		reg = <0x0 0x7000d100 0x0 0x100>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C6>;
		clock-names = "div-clk";
		resets = <&tegra_car 166>;
		reset-names = "i2c";
		dmas = <&apbdma 30>, <&apbdma 30>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000d400 0x0 0x200>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_SBC1>;
		clock-names = "spi";
		resets = <&tegra_car 41>;
		reset-names = "spi";
		dmas = <&apbdma 15>, <&apbdma 15>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000d600 0x0 0x200>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_SBC2>;
		clock-names = "spi";
		resets = <&tegra_car 44>;
		reset-names = "spi";
		dmas = <&apbdma 16>, <&apbdma 16>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000d800 0x0 0x200>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_SBC3>;
		clock-names = "spi";
		resets = <&tegra_car 46>;
		reset-names = "spi";
		dmas = <&apbdma 17>, <&apbdma 17>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000da00 0x0 0x200>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_SBC4>;
		clock-names = "spi";
		resets = <&tegra_car 68>;
		reset-names = "spi";
		dmas = <&apbdma 18>, <&apbdma 18>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	spi@7000dc00 {
		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000dc00 0x0 0x200>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_SBC5>;
		clock-names = "spi";
		resets = <&tegra_car 104>;
		reset-names = "spi";
		dmas = <&apbdma 27>, <&apbdma 27>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	spi@7000de00 {
		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000de00 0x0 0x200>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_SBC6>;
		clock-names = "spi";
		resets = <&tegra_car 105>;
		reset-names = "spi";
		dmas = <&apbdma 28>, <&apbdma 28>;
		dma-names = "rx", "tx";
		status = "disabled";
	};

	rtc@7000e000 {
		compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
		reg = <0x0 0x7000e000 0x0 0x100>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_RTC>;
		clock-names = "rtc";
	};

	tegra_pmc: pmc@7000e400 {
		compatible = "nvidia,tegra124-pmc";
		reg = <0x0 0x7000e400 0x0 0x400>;
		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
		#clock-cells = <1>;
	};

	fuse@7000f800 {
		compatible = "nvidia,tegra124-efuse";
		reg = <0x0 0x7000f800 0x0 0x400>;
		clocks = <&tegra_car TEGRA124_CLK_FUSE>;
		clock-names = "fuse";
		resets = <&tegra_car 39>;
		reset-names = "fuse";
	};

	mc: memory-controller@70019000 {
		compatible = "nvidia,tegra132-mc";
		reg = <0x0 0x70019000 0x0 0x1000>;
		clocks = <&tegra_car TEGRA124_CLK_MC>;
		clock-names = "mc";

		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

		#iommu-cells = <1>;
		#reset-cells = <1>;
		#interconnect-cells = <1>;
	};

	emc: external-memory-controller@7001b000 {
		compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
		reg = <0x0 0x7001b000 0x0 0x1000>;
		clocks = <&tegra_car TEGRA124_CLK_EMC>;
		clock-names = "emc";

		nvidia,memory-controller = <&mc>;
		operating-points-v2 = <&emc_icc_dvfs_opp_table>;

		#interconnect-cells = <0>;
	};

	sata@70020000 {
		compatible = "nvidia,tegra124-ahci";
		reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
		      <0x0 0x70020000 0x0 0x7000>; /* SATA */
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SATA>,
			 <&tegra_car TEGRA124_CLK_SATA_OOB>;
		clock-names = "sata", "sata-oob";
		resets = <&tegra_car 124>,
			 <&tegra_car 129>,
			 <&tegra_car 123>;
		reset-names = "sata", "sata-cold", "sata-oob";
		status = "disabled";
	};

	hda@70030000 {
		compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
			     "nvidia,tegra30-hda";
		reg = <0x0 0x70030000 0x0 0x10000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_HDA>,
		         <&tegra_car TEGRA124_CLK_HDA2HDMI>,
			 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
		resets = <&tegra_car 125>, /* hda */
			 <&tegra_car 128>, /* hda2hdmi */
			 <&tegra_car 111>; /* hda2codec_2x */
		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
		status = "disabled";
	};

	usb@70090000 {
		compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb";
		reg = <0x0 0x70090000 0x0 0x8000>,
		      <0x0 0x70098000 0x0 0x1000>,
		      <0x0 0x70099000 0x0 0x1000>;
		reg-names = "hcd", "fpci", "ipfs";

		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
			 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
			 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
			 <&tegra_car TEGRA124_CLK_XUSB_SS>,
			 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
			 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
			 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
			 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
			 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
			 <&tegra_car TEGRA124_CLK_CLK_M>,
			 <&tegra_car TEGRA124_CLK_PLL_E>;
		clock-names = "xusb_host", "xusb_host_src",
			      "xusb_falcon_src", "xusb_ss",
			      "xusb_ss_div2", "xusb_ss_src",
			      "xusb_hs_src", "xusb_fs_src",
			      "pll_u_480m", "clk_m", "pll_e";
		resets = <&tegra_car 89>, <&tegra_car 156>,
			 <&tegra_car 143>;
		reset-names = "xusb_host", "xusb_ss", "xusb_src";

		nvidia,xusb-padctl = <&padctl>;

		status = "disabled";
	};

	padctl: padctl@7009f000 {
		compatible = "nvidia,tegra132-xusb-padctl",
			     "nvidia,tegra124-xusb-padctl";
		reg = <0x0 0x7009f000 0x0 0x1000>;
		resets = <&tegra_car 142>;
		reset-names = "padctl";

		pads {
			usb2 {
				status = "disabled";

				lanes {
					usb2-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb2-1 {
						status = "disabled";
						#phy-cells = <0>;
					};

					usb2-2 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			ulpi {
				status = "disabled";

				lanes {
					ulpi-0 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			hsic {
				status = "disabled";

				lanes {
					hsic-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					hsic-1 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			pcie {
				status = "disabled";

				lanes {
					pcie-0 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-1 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-2 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-3 {
						status = "disabled";
						#phy-cells = <0>;
					};

					pcie-4 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};

			sata {
				status = "disabled";

				lanes {
					sata-0 {
						status = "disabled";
						#phy-cells = <0>;
					};
				};
			};
		};

		ports {
			usb2-0 {
				status = "disabled";
			};

			usb2-1 {
				status = "disabled";
			};

			usb2-2 {
				status = "disabled";
			};

			hsic-0 {
				status = "disabled";
			};

			hsic-1 {
				status = "disabled";
			};

			usb3-0 {
				status = "disabled";
			};

			usb3-1 {
				status = "disabled";
			};
		};
	};

	mmc@700b0000 {
		compatible = "nvidia,tegra124-sdhci";
		reg = <0x0 0x700b0000 0x0 0x200>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
		clock-names = "sdhci";
		resets = <&tegra_car 14>;
		reset-names = "sdhci";
		status = "disabled";
	};

	mmc@700b0200 {
		compatible = "nvidia,tegra124-sdhci";
		reg = <0x0 0x700b0200 0x0 0x200>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
		clock-names = "sdhci";
		resets = <&tegra_car 9>;
		reset-names = "sdhci";
		status = "disabled";
	};

	mmc@700b0400 {
		compatible = "nvidia,tegra124-sdhci";
		reg = <0x0 0x700b0400 0x0 0x200>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
		clock-names = "sdhci";
		resets = <&tegra_car 69>;
		reset-names = "sdhci";
		status = "disabled";
	};

	mmc@700b0600 {
		compatible = "nvidia,tegra124-sdhci";
		reg = <0x0 0x700b0600 0x0 0x200>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
		clock-names = "sdhci";
		resets = <&tegra_car 15>;
		reset-names = "sdhci";
		status = "disabled";
	};

	soctherm: thermal-sensor@700e2000 {
		compatible = "nvidia,tegra132-soctherm";
		reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
		      <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
		reg-names = "soctherm-reg", "ccroc-reg";
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "thermal", "edp";
		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
		         <&tegra_car TEGRA124_CLK_SOC_THERM>;
		clock-names = "tsensor", "soctherm";
		resets = <&tegra_car 78>;
		reset-names = "soctherm";
		#thermal-sensor-cells = <1>;

		throttle-cfgs {
			throttle_heavy: heavy {
				nvidia,priority = <100>;
				nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;

				#cooling-cells = <2>;
			};
		};
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <1000>;
			polling-delay = <0>;

			thermal-sensors =
				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;

			trips {
				cpu_shutdown_trip {
					temperature = <105000>;
					hysteresis = <1000>;
					type = "critical";
				};

				cpu_throttle_trip: throttle-trip {
					temperature = <102000>;
					hysteresis = <1000>;
					type = "hot";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_throttle_trip>;
					cooling-device = <&throttle_heavy 1 1>;
				};
			};
		};

		mem-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;

			thermal-sensors =
				<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;

			trips {
				mem_shutdown_trip {
					temperature = <101000>;
					hysteresis = <1000>;
					type = "critical";
				};
				mem_throttle_trip {
					temperature = <99000>;
					hysteresis = <1000>;
					type = "hot";
				};
			};

			cooling-maps {
				/*
				 * There are currently no cooling maps,
				 * because there are no cooling devices.
				 */
			};
		};

		gpu-thermal {
			polling-delay-passive = <1000>;
			polling-delay = <0>;

			thermal-sensors =
				<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;

			trips {
				gpu_shutdown_trip {
					temperature = <101000>;
					hysteresis = <1000>;
					type = "critical";
				};

				gpu_throttle_trip: throttle-trip {
					temperature = <99000>;
					hysteresis = <1000>;
					type = "hot";
				};
			};

			cooling-maps {
				map0 {
					trip = <&gpu_throttle_trip>;
					cooling-device = <&throttle_heavy 1 1>;
				};
			};
		};

		pllx-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;

			thermal-sensors =
				<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;

			trips {
				pllx_shutdown_trip {
					temperature = <105000>;
					hysteresis = <1000>;
					type = "critical";
				};
				pllx_throttle_trip {
					temperature = <99000>;
					hysteresis = <1000>;
					type = "hot";
				};
			};

			cooling-maps {
				/*
				 * There are currently no cooling maps,
				 * because there are no cooling devices.
				 */
			};
		};
	};

	ahub@70300000 {
		compatible = "nvidia,tegra124-ahub";
		reg = <0x0 0x70300000 0x0 0x200>,
		      <0x0 0x70300800 0x0 0x800>,
		      <0x0 0x70300200 0x0 0x600>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
			 <&tegra_car TEGRA124_CLK_APBIF>;
		clock-names = "d_audio", "apbif";
		resets = <&tegra_car 106>, /* d_audio */
			 <&tegra_car 107>, /* apbif */
			 <&tegra_car 30>,  /* i2s0 */
			 <&tegra_car 11>,  /* i2s1 */
			 <&tegra_car 18>,  /* i2s2 */
			 <&tegra_car 101>, /* i2s3 */
			 <&tegra_car 102>, /* i2s4 */
			 <&tegra_car 108>, /* dam0 */
			 <&tegra_car 109>, /* dam1 */
			 <&tegra_car 110>, /* dam2 */
			 <&tegra_car 10>,  /* spdif */
			 <&tegra_car 153>, /* amx */
			 <&tegra_car 185>, /* amx1 */
			 <&tegra_car 154>, /* adx */
			 <&tegra_car 180>, /* adx1 */
			 <&tegra_car 186>, /* afc0 */
			 <&tegra_car 187>, /* afc1 */
			 <&tegra_car 188>, /* afc2 */
			 <&tegra_car 189>, /* afc3 */
			 <&tegra_car 190>, /* afc4 */
			 <&tegra_car 191>; /* afc5 */
		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
			      "spdif", "amx", "amx1", "adx", "adx1",
			      "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
		dmas = <&apbdma 1>, <&apbdma 1>,
		       <&apbdma 2>, <&apbdma 2>,
		       <&apbdma 3>, <&apbdma 3>,
		       <&apbdma 4>, <&apbdma 4>,
		       <&apbdma 6>, <&apbdma 6>,
		       <&apbdma 7>, <&apbdma 7>,
		       <&apbdma 12>, <&apbdma 12>,
		       <&apbdma 13>, <&apbdma 13>,
		       <&apbdma 14>, <&apbdma 14>,
		       <&apbdma 29>, <&apbdma 29>;
		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
			    "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
			    "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
			    "rx9", "tx9";
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		tegra_i2s0: i2s@70301000 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x0 0x70301000 0x0 0x100>;
			nvidia,ahub-cif-ids = <4 4>;
			clocks = <&tegra_car TEGRA124_CLK_I2S0>;
			clock-names = "i2s";
			resets = <&tegra_car 30>;
			reset-names = "i2s";
			status = "disabled";
		};

		tegra_i2s1: i2s@70301100 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x0 0x70301100 0x0 0x100>;
			nvidia,ahub-cif-ids = <5 5>;
			clocks = <&tegra_car TEGRA124_CLK_I2S1>;
			clock-names = "i2s";
			resets = <&tegra_car 11>;
			reset-names = "i2s";
			status = "disabled";
		};

		tegra_i2s2: i2s@70301200 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x0 0x70301200 0x0 0x100>;
			nvidia,ahub-cif-ids = <6 6>;
			clocks = <&tegra_car TEGRA124_CLK_I2S2>;
			clock-names = "i2s";
			resets = <&tegra_car 18>;
			reset-names = "i2s";
			status = "disabled";
		};

		tegra_i2s3: i2s@70301300 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x0 0x70301300 0x0 0x100>;
			nvidia,ahub-cif-ids = <7 7>;
			clocks = <&tegra_car TEGRA124_CLK_I2S3>;
			clock-names = "i2s";
			resets = <&tegra_car 101>;
			reset-names = "i2s";
			status = "disabled";
		};

		tegra_i2s4: i2s@70301400 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x0 0x70301400 0x0 0x100>;
			nvidia,ahub-cif-ids = <8 8>;
			clocks = <&tegra_car TEGRA124_CLK_I2S4>;
			clock-names = "i2s";
			resets = <&tegra_car 102>;
			reset-names = "i2s";
			status = "disabled";
		};
	};

	usb@7d000000 {
		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
		reg = <0x0 0x7d000000 0x0 0x4000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA124_CLK_USBD>;
		clock-names = "usb";
		resets = <&tegra_car 22>;
		reset-names = "usb";
		nvidia,phy = <&phy1>;
		status = "disabled";
	};

	phy1: usb-phy@7d000000 {
		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
		reg = <0x0 0x7d000000 0x0 0x4000>,
		      <0x0 0x7d000000 0x0 0x4000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA124_CLK_USBD>,
			 <&tegra_car TEGRA124_CLK_PLL_U>,
			 <&tegra_car TEGRA124_CLK_USBD>;
		clock-names = "reg", "pll_u", "utmi-pads";
		resets = <&tegra_car 22>, <&tegra_car 22>;
		reset-names = "usb", "utmi-pads";
		#phy-cells = <0>;
		nvidia,hssync-start-delay = <0>;
		nvidia,idle-wait-delay = <17>;
		nvidia,elastic-limit = <16>;
		nvidia,term-range-adj = <6>;
		nvidia,xcvr-setup = <9>;
		nvidia,xcvr-lsfslew = <0>;
		nvidia,xcvr-lsrslew = <3>;
		nvidia,hssquelch-level = <2>;
		nvidia,hsdiscon-level = <5>;
		nvidia,xcvr-hsslew = <12>;
		nvidia,has-utmi-pad-registers;
		nvidia,pmc = <&tegra_pmc 0>;
		status = "disabled";
	};

	usb@7d004000 {
		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
		reg = <0x0 0x7d004000 0x0 0x4000>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA124_CLK_USB2>;
		clock-names = "usb";
		resets = <&tegra_car 58>;
		reset-names = "usb";
		nvidia,phy = <&phy2>;
		status = "disabled";
	};

	phy2: usb-phy@7d004000 {
		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
		reg = <0x0 0x7d004000 0x0 0x4000>,
		      <0x0 0x7d000000 0x0 0x4000>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA124_CLK_USB2>,
			 <&tegra_car TEGRA124_CLK_PLL_U>,
			 <&tegra_car TEGRA124_CLK_USBD>;
		clock-names = "reg", "pll_u", "utmi-pads";
		resets = <&tegra_car 58>, <&tegra_car 22>;
		reset-names = "usb", "utmi-pads";
		#phy-cells = <0>;
		nvidia,hssync-start-delay = <0>;
		nvidia,idle-wait-delay = <17>;
		nvidia,elastic-limit = <16>;
		nvidia,term-range-adj = <6>;
		nvidia,xcvr-setup = <9>;
		nvidia,xcvr-lsfslew = <0>;
		nvidia,xcvr-lsrslew = <3>;
		nvidia,hssquelch-level = <2>;
		nvidia,hsdiscon-level = <5>;
		nvidia,xcvr-hsslew = <12>;
		nvidia,pmc = <&tegra_pmc 1>;
		status = "disabled";
	};

	usb@7d008000 {
		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
		reg = <0x0 0x7d008000 0x0 0x4000>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA124_CLK_USB3>;
		clock-names = "usb";
		resets = <&tegra_car 59>;
		reset-names = "usb";
		nvidia,phy = <&phy3>;
		status = "disabled";
	};

	phy3: usb-phy@7d008000 {
		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
		reg = <0x0 0x7d008000 0x0 0x4000>,
		      <0x0 0x7d000000 0x0 0x4000>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA124_CLK_USB3>,
			 <&tegra_car TEGRA124_CLK_PLL_U>,
			 <&tegra_car TEGRA124_CLK_USBD>;
		clock-names = "reg", "pll_u", "utmi-pads";
		resets = <&tegra_car 59>, <&tegra_car 22>;
		reset-names = "usb", "utmi-pads";
		#phy-cells = <0>;
		nvidia,hssync-start-delay = <0>;
		nvidia,idle-wait-delay = <17>;
		nvidia,elastic-limit = <16>;
		nvidia,term-range-adj = <6>;
		nvidia,xcvr-setup = <9>;
		nvidia,xcvr-lsfslew = <0>;
		nvidia,xcvr-lsrslew = <3>;
		nvidia,hssquelch-level = <2>;
		nvidia,hsdiscon-level = <5>;
		nvidia,xcvr-hsslew = <12>;
		nvidia,pmc = <&tegra_pmc 2>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "nvidia,tegra132-denver";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "nvidia,tegra132-denver";
			reg = <1>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&gic>;
	};
};