code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree for the ARM Integrator/AP platform
 * with the IM-PD1 example logical module mounted.
 */

#include "integratorap.dts"

/ {
	model = "ARM Integrator/AP with IM-PD1";
	compatible = "arm,integrator-ap";

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		impd1_ram: vram@c2000000 {
			/* 1 MB of designated video RAM on the IM-PD1 */
			compatible = "shared-dma-pool";
			reg = <0xc2000000 0x00100000>;
			no-map;
		};
	};
};

&lm0 {
	syscon@0 {
		compatible = "arm,im-pd1-syscon", "syscon";
		reg = <0x00000000 0x1000>;
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;

		vco1: clock-controller@0 {
			compatible = "arm,impd1-vco1";
			reg = <0x00 0x04>;
			#clock-cells = <0>;
			lock-offset = <0x08>;
			vco-offset = <0x00>;
			clocks = <&sysclk>;
			clock-output-names = "IM-PD1-VCO1";
		};

		vco2: clock-controller@4 {
			compatible = "arm,impd1-vco2";
			reg = <0x04 0x04>;
			#clock-cells = <0>;
			lock-offset = <0x08>;
			vco-offset = <0x04>;
			clocks = <&sysclk>;
			clock-output-names = "IM-PD1-VCO2";
		};
	};

	/* Also used for the Smart Card Interface SCI */
	impd1_uartclk: clock@1_4 {
		compatible = "fixed-factor-clock";
		#clock-cells = <0>;
		clock-div = <4>;
		clock-mult = <1>;
		clocks = <&vco2>;
		clock-output-names = "VCO2_DIV4";
	};

	/* For the SSP the clock is divided by 64 */
	impd1_sspclk: clock@1_64 {
		compatible = "fixed-factor-clock";
		#clock-cells = <0>;
		clock-div = <64>;
		clock-mult = <1>;
		clocks = <&vco2>;
		clock-output-names = "VCO2_DIV64";
	};

	/* Fixed regulator for the MMC */
	impd1_3v3: regulator {
		compatible = "regulator-fixed";
		regulator-name = "3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	/* Push buttons on the IM-PD1 */
	gpio_keys {
		compatible = "gpio-keys";
		#address-cells = <1>;
		#size-cells = <0>;

		button@0 {
			debounce-interval = <50>;
			linux,code = <KEY_UP>;
			label = "UP";
			gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>;
		};
		button@1 {
			debounce-interval = <50>;
			linux,code = <KEY_DOWN>;
			label = "DOWN";
			gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>;
		};
		button@2 {
			debounce-interval = <50>;
			linux,code = <KEY_LEFT>;
			label = "LEFT";
			gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>;
		};
		button@3 {
			debounce-interval = <50>;
			linux,code = <KEY_RIGHT>;
			label = "UP";
			gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>;
		};
		button@4 {
			debounce-interval = <50>;
			linux,code = <KEY_ESC>;
			label = "ESC";
			gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>;
		};
		button@5 {
			debounce-interval = <50>;
			linux,code = <KEY_ENTER>;
			label = "ENTER";
			gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>;
		};
	};

	bridge {
		compatible = "ti,ths8134b", "ti,ths8134";
		#address-cells = <1>;
		#size-cells = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
					vga_bridge_in: endpoint {
					remote-endpoint = <&clcd_pads_vga_dac>;
				};
			};

			port@1 {
				reg = <1>;

				vga_bridge_out: endpoint {
					remote-endpoint = <&vga_con_in>;
				};
			};
		};
	};

	vga {
		compatible = "vga-connector";

		port {
			vga_con_in: endpoint {
				remote-endpoint = <&vga_bridge_out>;
			};
		};
	};

	uart@100000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x00100000 0x1000>;
		interrupts-extended = <&impd1_vic 1>;
		clocks = <&impd1_uartclk>, <&sysclk>;
		clock-names = "uartclk", "apb_pclk";
	};

	uart@200000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x00200000 0x1000>;
		interrupts-extended = <&impd1_vic 2>;
		clocks = <&impd1_uartclk>, <&sysclk>;
		clock-names = "uartclk", "apb_pclk";
	};

	spi@300000 {
		compatible = "arm,pl022", "arm,primecell";
		reg = <0x00300000 0x1000>;
		interrupts-extended = <&impd1_vic 3>;
		clocks = <&impd1_sspclk>, <&sysclk>;
		clock-names = "sspclk", "apb_pclk";
	};

	impd1_gpio0: gpio@400000 {
		compatible = "arm,pl061", "arm,primecell";
		reg = <0x00400000 0x1000>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts-extended = <&impd1_vic 4>;
		clocks = <&sysclk>;
		clock-names = "apb_pclk";
	};

	impd1_gpio1: gpio@500000 {
		compatible = "arm,pl061", "arm,primecell";
		reg = <0x00500000 0x1000>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts-extended = <&impd1_vic 5>;
		clocks = <&sysclk>;
		clock-names = "apb_pclk";
	};

	rtc@600000 {
		compatible = "arm,pl030", "arm,primecell";
		reg = <0x00600000 0x1000>;
		interrupts-extended = <&impd1_vic 6>;
		clocks = <&sysclk>;
		clock-names = "apb_pclk";
	};

	mmc@700000 {
		compatible = "arm,pl181", "arm,primecell";
		reg = <0x00700000 0x1000>;
		interrupts-extended = <&impd1_vic 7>,
				    <&impd1_vic 8>;
		clocks = <&sysclk>, <&sysclk>;
		clock-names = "mclk", "apb_pclk";
		bus-width = <1>;
		max-frequency = <515633>;
		vmmc-supply = <&impd1_3v3>;
		wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>;
		cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>;
	};

	aaci@800000 {
		compatible = "arm,pl041", "arm,primecell";
		reg = <0x00800000 0x1000>;
		interrupts-extended = <&impd1_vic 9>;
		clocks = <&sysclk>;
		clock-names = "apb_pclk";
	};

	display@1000000 {
		compatible = "arm,pl110", "arm,primecell";
		reg = <0x01000000 0x1000>;
		interrupts-extended = <&impd1_vic 11>;
		clocks = <&vco1>, <&sysclk>;
		clock-names = "clcdclk", "apb_pclk";
		/* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
		max-memory-bandwidth = <40000000>;
		memory-region = <&impd1_ram>;
		dma-ranges;

		port@0 {
			#address-cells = <1>;
			#size-cells = <0>;

			clcd_pads_vga_dac: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&vga_bridge_in>;
				arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
			};
		};
	};

	impd1_vic: interrupt-controller@3000000 {
		compatible = "arm,pl192-vic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0x03000000 0x1000>;
		/* Valid interrupts, 0-9 and 11 */
		valid-mask = <0x00000bff>;
		/* LM site 0 has IRQ 9 on the PIC */
		interrupts-extended = <&pic 9>;
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree for the ARM Integrator/AP platform
 */

/dts-v1/;
#include "integrator.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	model = "ARM Integrator/AP";
	compatible = "arm,integrator-ap";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			/*
			 * Since the board has pluggable CPU modules, we
			 * cannot define a proper compatible here. Let the
			 * boot loader fill in the apropriate compatible
			 * string if necessary.
			 */
			/* compatible = "arm,arm926ej-s"; */
			reg = <0>;
			/*
			 * The documentation in ARM DUI 0138E page 3-12 states
			 * that the maximum frequency for this clock is 200 MHz
			 * but painful trial-and-error has proved to me that it
			 * is actually just hanging the system above 71 MHz.
			 * Sad but true.
			 */
					 /* kHz     uV   */
			operating-points = <71000  0
					    66000  0
					    60000  0
					    48000  0
					    36000  0
					    24000  0
					    12000  0>;
			clocks = <&cmosc>;
			clock-names = "cpu";
			clock-latency = <1000000>; /* 1 ms */
		};
	};

	aliases {
		arm,timer-primary = &timer2;
		arm,timer-secondary = &timer1;
	};

	chosen {
		bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
	};

	/* 24 MHz chrystal on the Integrator/AP development board */
	xtal24mhz: xtal24mhz@24M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
	};

	pclk: pclk@0 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <1>;
		clock-mult = <1>;
		clocks = <&xtal24mhz>;
	};

	/* The UART clock is 14.74 MHz divided by an ICS525 */
	uartclk: uartclk@14.74M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <14745600>;
		clocks = <&xtal24mhz>;
	};

	core-module@10000000 {
		/* 24 MHz chrystal on the core module */
		cm24mhz: cm24mhz@24M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		/* Oscillator on the core module, clocks the CPU core */
		cmosc: clock-controller@8 {
			compatible = "arm,syscon-icst525-integratorap-cm";
			reg = <0x08 0x04>;
			#clock-cells = <0>;
			lock-offset = <0x14>;
			vco-offset = <0x08>;
			clocks = <&cm24mhz>;
		};

		/* Auxilary oscillator on the core module, 32.369MHz at boot */
		auxosc: clock-controller@1c {
			compatible = "arm,syscon-icst525";
			reg = <0x1c 0x04>;
			#clock-cells = <0>;
			lock-offset = <0x14>;
			vco-offset = <0x1c>;
			clocks = <&cm24mhz>;
		};
	};

	syscon {
		compatible = "arm,integrator-ap-syscon", "syscon";
		reg = <0x11000000 0x100>;
		ranges = <0x0 0x11000000 0x100>;
		#size-cells = <1>;
		#address-cells = <1>;

		/*
		 * SYSCLK clocks PCIv3 bridge, system controller and the
		 * logic modules.
		 */
		sysclk: clock-controller@4 {
			compatible = "arm,syscon-icst525-integratorap-sys";
			reg = <0x04 0x04>;
			#clock-cells = <0>;
			lock-offset = <0x1c>;
			vco-offset = <0x04>;
			clocks = <&xtal24mhz>;
		};

		/* One-bit control for the PCI bus clock (33 or 25 MHz) */
		pciclk: clock-controller@4,8 {
			compatible = "arm,syscon-icst525-integratorap-pci";
			reg = <0x04 0x04>;
			#clock-cells = <0>;
			lock-offset = <0x1c>;
			vco-offset = <0x04>;
			clocks = <&xtal24mhz>;
		};
	};

	timer0: timer@13000000 {
		compatible = "arm,integrator-timer";
		clocks = <&xtal24mhz>;
	};

	timer1: timer@13000100 {
		compatible = "arm,integrator-timer";
		clocks = <&xtal24mhz>;
	};

	timer2: timer@13000200 {
		compatible = "arm,integrator-timer";
		clocks = <&xtal24mhz>;
	};

	pic: pic@14000000 {
		valid-mask = <0x003fffff>;
	};

	pci: pciv3@62000000 {
		compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		/* Bridge registers and config access space */
		reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
		interrupt-parent = <&pic>;
		interrupts = <17>; /* Bus error IRQ */
		clocks = <&pciclk>;
		bus-range = <0x00 0xff>;
		ranges = <0x01000000 0 0x0000000 /* I/O space @00000000 */
			0x60000000 0 0x00010000 /* 64 KB @ LB 60000000 */
			0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
			0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
			0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
			0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
		dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
			0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
			0x02000000 0 0x80000000 /* Core module alias memory */
			0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
		interrupt-map-mask = <0xf800 0 0 0x7>;
		interrupt-map = <
		/* IDSEL 9 */
		0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
		0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
		0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
		0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
		/* IDSEL 10 */
		0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
		0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
		0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
		0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
		/* IDSEL 11 */
		0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
		0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
		0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
		0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
		/* IDSEL 12 */
		0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
		0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
		0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
		0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
		>;
	};

	fpga {
		/*
		 * The Integator/AP predates the idea to have magic numbers
		 * identifying the PrimeCell in hardware, thus we have to
		 * supply these from the device tree.
		 */
		rtc: rtc@15000000 {
			compatible = "arm,pl030", "arm,primecell";
			arm,primecell-periphid = <0x00041030>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		uart0: uart@16000000 {
			compatible = "arm,pl010", "arm,primecell";
			arm,primecell-periphid = <0x00041010>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart1: uart@17000000 {
			compatible = "arm,pl010", "arm,primecell";
			arm,primecell-periphid = <0x00041010>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		kmi0: kmi@18000000 {
			compatible = "arm,pl050", "arm,primecell";
			arm,primecell-periphid = <0x00041050>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};

		kmi1: kmi@19000000 {
			compatible = "arm,pl050", "arm,primecell";
			arm,primecell-periphid = <0x00041050>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};
	};

	/*
	 * Logic module bus, we support up to 4 logical modules
	 * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000
	 * and use interrupts 9, 10, 11 and 12 respectively.
	 */
	bus@c0000000 {
		compatible = "arm,integrator-ap-lm";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0xc0000000 0xc0000000 0x40000000>;
		dma-ranges;

		lm0: bus@c0000000 {
			compatible = "simple-bus";
			ranges = <0x00000000 0xc0000000 0x10000000>;
			dma-ranges = <0x00000000 0xc0000000 0x10000000>;
			reg = <0xc0000000 0x10000000>;
			#address-cells = <1>;
			#size-cells = <1>;
		};
		lm1: bus@d0000000 {
			compatible = "simple-bus";
			ranges = <0x00000000 0xd0000000 0x10000000>;
			dma-ranges = <0x00000000 0xd0000000 0x10000000>;
			reg = <0xd0000000 0x10000000>;
			#address-cells = <1>;
			#size-cells = <1>;
		};
		lm2: bus@e0000000 {
			compatible = "simple-bus";
			ranges = <0x00000000 0xe0000000 0x10000000>;
			dma-ranges = <0x00000000 0xe0000000 0x10000000>;
			reg = <0xe0000000 0x10000000>;
			#address-cells = <1>;
			#size-cells = <1>;
		};
		lm3: bus@f0000000 {
			compatible = "simple-bus";
			ranges = <0x00000000 0xf0000000 0x10000000>;
			dma-ranges = <0x00000000 0xf0000000 0x10000000>;
			reg = <0xf0000000 0x10000000>;
			#address-cells = <1>;
			#size-cells = <1>;
		};
	};
};

repo_name: angery/linux


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree for the ARM Integrator/CP platform
 */

/dts-v1/;
/include/ "integrator.dtsi"

/ {
	model = "ARM Integrator/CP";
	compatible = "arm,integrator-cp";

	chosen {
		bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			/*
			 * Since the board has pluggable CPU modules, we
			 * cannot define a proper compatible here. Let the
			 * boot loader fill in the apropriate compatible
			 * string if necessary.
			 */
			/* compatible = "arm,arm920t"; */
			reg = <0>;
			/*
			 * TBD comment.
			 */
					 /* kHz     uV   */
			operating-points = <50000  0
					    48000  0>;
			clocks = <&cmcore>;
			clock-names = "cpu";
			clock-latency = <1000000>; /* 1 ms */
		};
	};

	/*
	 * The Integrator/CP overall clocking architecture can be found in
	 * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
	 * appear to illustrate the layout used in most configurations.
	 */

	/* The codec chrystal operates at 24.576 MHz */
	xtal_codec: xtal24.576@24.576M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24576000>;
	};

	/* The chrystal is divided by 2 by the codec for the AACI bit clock */
	aaci_bitclk: aaci_bitclk@12.288M {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <2>;
		clock-mult = <1>;
		clocks = <&xtal_codec>;
	};

	/* This is a 25MHz chrystal on the base board */
	xtal25mhz: xtal25mhz@25M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <25000000>;
	};

	/* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
	uartclk: uartclk@14.74M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <14745600>;
	};

	/* Actually sysclk I think */
	pclk: pclk@0 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	core-module@10000000 {
		/* 24 MHz chrystal on the core module */
		cm24mhz: cm24mhz@24M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		/* Oscillator on the core module, clocks the CPU core */
		cmcore: clock-controller@8 {
			compatible = "arm,syscon-icst525-integratorcp-cm-core";
			reg = <0x08 0x04>;
			#clock-cells = <0>;
			lock-offset = <0x14>;
			vco-offset = <0x08>;
			clocks = <&cm24mhz>;
		};

		/* Oscillator on the core module, clocks the memory bus */
		cmmem: clock-controller@8,12 {
			compatible = "arm,syscon-icst525-integratorcp-cm-mem";
			reg = <0x08 0x04>;
			#clock-cells = <0>;
			lock-offset = <0x14>;
			vco-offset = <0x08>;
			clocks = <&cm24mhz>;
		};

		/* Auxilary oscillator on the core module, clocks the CLCD */
		auxosc: clock-controller@1c {
			compatible = "arm,syscon-icst525";
			reg = <0x1c 0x04>;
			#clock-cells = <0>;
			lock-offset = <0x14>;
			vco-offset = <0x1c>;
			clocks = <&cm24mhz>;
		};

		/* The KMI clock is the 24 MHz oscillator divided to 8MHz */
		kmiclk: kmiclk@1M {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <3>;
			clock-mult = <1>;
			clocks = <&cm24mhz>;
		};

		/* The timer clock is the 24 MHz oscillator divided to 1MHz */
		timclk: timclk@1M {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <24>;
			clock-mult = <1>;
			clocks = <&cm24mhz>;
		};
	};

	syscon {
		compatible = "arm,integrator-cp-syscon", "syscon";
		reg = <0xcb000000 0x100>;
	};

	timer0: timer@13000000 {
		/* TIMER0 runs directly on the 25MHz chrystal */
		compatible = "arm,integrator-cp-timer";
		clocks = <&xtal25mhz>;
	};

	timer1: timer@13000100 {
		/* TIMER1 runs @ 1MHz */
		compatible = "arm,integrator-cp-timer";
		clocks = <&timclk>;
	};

	timer2: timer@13000200 {
		/* TIMER2 runs @ 1MHz */
		compatible = "arm,integrator-cp-timer";
		clocks = <&timclk>;
	};

	pic: pic@14000000 {
		valid-mask = <0x1fc003ff>;
	};

	cic: cic@10000040 {
		compatible = "arm,versatile-fpga-irq";
		#interrupt-cells = <1>;
		interrupt-controller;
		reg = <0x10000040 0x100>;
		clear-mask = <0xffffffff>;
		valid-mask = <0x00000007>;
	};

	/* The SIC is cascaded off IRQ 26 on the PIC */
	sic: sic@ca000000 {
		compatible = "arm,versatile-fpga-irq";
		interrupt-parent = <&pic>;
		interrupts = <26>;
		#interrupt-cells = <1>;
		interrupt-controller;
		reg = <0xca000000 0x100>;
		clear-mask = <0x00000fff>;
		valid-mask = <0x00000fff>;
	};

	ethernet@c8000000 {
		compatible = "smsc,lan91c111";
		reg = <0xc8000000 0x10>;
		interrupt-parent = <&pic>;
		interrupts = <27>;
	};

	bridge {
		compatible = "ti,ths8134a", "ti,ths8134";
		#address-cells = <1>;
		#size-cells = <0>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				vga_bridge_in: endpoint {
					remote-endpoint = <&clcd_pads_vga_dac>;
				};
			};

			port@1 {
				reg = <1>;

				vga_bridge_out: endpoint {
					remote-endpoint = <&vga_con_in>;
				};
			};
		};
	};

	vga {
		compatible = "vga-connector";

		port {
			vga_con_in: endpoint {
				remote-endpoint = <&vga_bridge_out>;
			};
		};
	};

	fpga {
		/*
		 * These PrimeCells are at the same location and using
		 * the same interrupts in all Integrators, but in the CP
		 * slightly newer versions are deployed.
		 */
		rtc@15000000 {
			compatible = "arm,pl031", "arm,primecell";
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		uart@16000000 {
			compatible = "arm,pl011", "arm,primecell";
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart@17000000 {
			compatible = "arm,pl011", "arm,primecell";
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		kmi@18000000 {
			compatible = "arm,pl050", "arm,primecell";
			clocks = <&kmiclk>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};

		kmi@19000000 {
			compatible = "arm,pl050", "arm,primecell";
			clocks = <&kmiclk>, <&pclk>;
			clock-names = "KMIREFCLK", "apb_pclk";
		};

		/*
		 * These PrimeCells are only available on the Integrator/CP
		 */
		mmc@1c000000 {
			compatible = "arm,pl180", "arm,primecell";
			reg = <0x1c000000 0x1000>;
			interrupts = <23 24>;
			max-frequency = <515633>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "mclk", "apb_pclk";
		};

		aaci@1d000000 {
			compatible = "arm,pl041", "arm,primecell";
			reg = <0x1d000000 0x1000>;
			interrupts = <25>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		clcd@c0000000 {
			compatible = "arm,pl110", "arm,primecell";
			reg = <0xC0000000 0x1000>;
			interrupts = <22>;
			clocks = <&auxosc>, <&pclk>;
			clock-names = "clcdclk", "apb_pclk";
			/* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
			max-memory-bandwidth = <40000000>;

			/*
			 * This port is routed through a PLD (Programmable
			 * Logic Device) that routes the output from the CLCD
			 * (after transformations) to the VGA DAC and also an
			 * external panel connector. The PLD is essential for
			 * supporting RGB565/BGR565.
			 *
			 * The signals from the port thus reaches two endpoints.
			 * The PLD is managed through a few special bits in the
			 * FPGA "sysreg".
			 *
			 * This arrangement can be clearly seen in
			 * ARM DUI 0225D, page 3-41, figure 3-19.
			 */
			port@0 {
				clcd_pads_vga_dac: endpoint {
					remote-endpoint = <&vga_bridge_in>;
					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for ADI Engineering Coyote platform.
 * Derived from boardfiles written by MontaVista software.
 * Ethernet set-up from OpenWrt.
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "ADI Engineering Coyote reference design";
	compatible = "adieng,coyote", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */
		device_type = "memory";
		reg = <0x00000000 0x01000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
		stdout-path = "uart1:115200n8";
	};

	aliases {
		/* These are switched around */
		serial0 = &uart1;
		serial1 = &uart0;
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/*
				 * 32 MB of Flash in 128 0x20000 sized blocks
				 * mapped in at CS0 and CS1
				 */
				reg = <0 0x00000000 0x2000000>;

				/* Configure expansion bus to allow writes */
				intel,ixp4xx-eb-write-enable = <1>;

				partitions {
					compatible = "redboot-fis";
					/* CHECKME: guess this is Redboot FIS */
					fis-index-block = <0x1ff>;
				};
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * Taken from Coyote PCI boardfile.
			 * We have slots (IDSEL) 1 and 2 with one assigned IRQ
			 * each handling all IRQs.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */
			<0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */
			<0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */
			<0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */
			<0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */
			<0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */
			<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */
		};

		/* EthB */
		ethernet@c8009000 {
			status = "ok";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			phy-mode = "rgmii";
			phy-handle = <&phy5>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy4: ethernet-phy@4 {
					reg = <4>;
				};

				phy5: ethernet-phy@5 {
					reg = <5>;
				};
			};
		};

		/* EthC */
		ethernet@c800a000 {
			status = "ok";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy4>;
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for the Arcom/Eurotech Vulcan board.
 * This board is a single board computer in the PC/104 form factor based on
 * IXP425, and was released around 2005. It previously had the name "Mercury".
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Arcom/Eurotech Vulcan";
	compatible = "arcom,vulcan", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x4000000>;
	};

	chosen {
		/* CHECKME: using a harddrive at /dev/sda1 as rootfs by default */
		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};

	onewire {
		compatible = "w1-gpio";
		gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/*
				 * 32 MB of Flash in 0x20000 byte blocks
				 * mapped in at CS0 and CS1.
				 *
				 * The documentation mentions the existence
				 * of a 16MB version, which we conveniently
				 * ignore. Shout if you own one!
				 */
				reg = <0 0x00000000 0x2000000>;

				/* Expansion bus settings */
				intel,ixp4xx-eb-t3 = <3>;
				intel,ixp4xx-eb-byte-access-on-halfword = <1>;
				intel,ixp4xx-eb-write-enable = <1>;

				partitions {
					compatible = "redboot-fis";
					fis-index-block = <0x1ff>;
				};
			};
			sram@2,0 {
				/* 256 KB SDRAM memory at CS2 */
				compatible = "shared-dma-pool";
				device_type = "memory";
				reg = <2 0x00000000 0x40000>;
				no-map;
				/* Expansion bus settings */
				intel,ixp4xx-eb-t3 = <1>;
				intel,ixp4xx-eb-t4 = <2>;
				intel,ixp4xx-eb-ahb-split-transfers = <1>;
				intel,ixp4xx-eb-write-enable = <1>;
				intel,ixp4xx-eb-byte-access = <1>;
			};
			serial@3,0 {
				/*
				 * 8250-compatible Exar XR16L2551 2 x UART
				 *
				 * CHECKME: if special tweaks are needed, then fix the
				 * operating system to handle it.
				 */
				compatible = "exar,xr16l2551", "ns8250";
				reg = <3 0x00000000 0x10>;
				interrupt-parent = <&gpio0>;
				interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
				clock-frequency = <1843200>;
				/* Expansion bus settings */
				intel,ixp4xx-eb-t3 = <3>;
				intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */
				intel,ixp4xx-eb-write-enable = <1>;
				intel,ixp4xx-eb-byte-access = <1>;
			};
			gpio1: gpio@4,0 {
				/*
				 * MMIO GPIO in one byte
				 */
				compatible = "arcom,vulcan-gpio";
				reg = <4 0x00000000 0x1>;
				/* Expansion bus settings */
				intel,ixp4xx-eb-write-enable = <1>;
				intel,ixp4xx-eb-byte-access = <1>;
			};
			watchdog@5,0 {
				compatible = "maxim,max6369";
				reg = <5 0x00000000 0x1>;
				/* Expansion bus settings */
				intel,ixp4xx-eb-write-enable = <1>;
				intel,ixp4xx-eb-byte-access = <1>;
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * Taken from Vulcan PCI boardfile.
			 *
			 * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt
			 * per slot. This interrupt is shared (OR:ed) by all four pins.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */
			<0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */
			<0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */
			<0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */
			<0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 3 */
			<0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 3 */
			<0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 3 */
		};

		/* EthB */
		ethernet@c8009000 {
			status = "ok";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			phy-mode = "rgmii";
			phy-handle = <&phy0>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy0: ethernet-phy@0 {
					reg = <0>;
				};

				phy1: ethernet-phy@1 {
					reg = <1>;
				};
			};
		};

		/* EthC */
		ethernet@c800a000 {
			status = "ok";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy1>;
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for D-Link DSM-G600 revision A based on IXP420
 * NOTE: revision B of this device uses PowerPC and is NOT supported by
 * this device tree.
 *
 * Inspired by the boardfile by Rod Whitby, Tower Technologies, Alessandro Zummo
 * and Michael Westerhof.
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "D-Link DSM-G600 rev A";
	compatible = "dlink,dsm-g600-a", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* 64 MB SDRAM */
		device_type = "memory";
		reg = <0x00000000 0x4000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};

	leds {
		compatible = "gpio-leds";
		led-power {
			label = "dsmg600:green:power";
			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};
		led-wlan {
			label = "dsmg600:green:wlan";
			/* CHECKME: flagged as active low in the old board file */
			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
			default-state = "on";
			/* We don't have WLAN trigger in the kernel (yet) */
			linux,default-trigger = "netdev";
		};
	};

	gpio_keys {
		compatible = "gpio-keys";

		button-reset {
			wakeup-source;
			linux,code = <KEY_ESC>;
			label = "reset";
			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
		};
	};

	gpio_keys_polled {
		compatible = "gpio-keys-polled";

		/*
		 * According to the board file this key cannot handle interrupts and
		 * need to be polled. Investigate if this is really the case or if
		 * this can be moved adjacent to the ordinary gpio-keys above.
		 */
		button-power {
			wakeup-source;
			linux,code = <KEY_POWER>;
			label = "power";
			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
		};
	};

	i2c {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		#address-cells = <1>;
		#size-cells = <0>;

		rtc@51 {
			compatible = "nxp,pcf8563";
			reg = <0x51>;
		};
	};

	gpio-poweroff {
		compatible = "gpio-poweroff";
		gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
		timeout-ms = <5000>;
	};

	soc {
		bus@c4000000 {
			/* The first 16MB region at CS0 on the expansion bus */
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/*
				 * 16 MB of Flash in 128 0x20000 sized blocks
				 * mapped in at CS0.
				 */
				reg = <0 0x00000000 0x1000000>;

				partitions {
					compatible = "redboot-fis";
					/*
					 * A boot log says the directory is at 0xfe0000
					 * 0x7f * 0x20000 = 0xfe0000
					 */
					fis-index-block = <0x7f>;
				};
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * Taken from DSM-G600 PCI boardfile (dsmg600-pci.c)
			 * We have slots (IDSEL) 1, 2, 3, 4 and pins 1, 2 and 3.
			 * Only slot 3 have three IRQs.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 7  IRQ_TYPE_LEVEL_LOW>, /* INT E on slot 1 is irq 7 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */
			/* IDSEL 3 */
			<0x1800 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 10 */
			<0x1800 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 9 */
			<0x1800 0 0 3 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 8 */
			/* IDSEL 4 */
			<0x2000 0 0 3 &gpio0 6  IRQ_TYPE_LEVEL_LOW>; /* INT F on slot 4 is irq 6 */
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for the Freecom FSG-3 router.
 * This machine is based on IXP425.
 * This device tree is inspired by the board file by Rod Whitby.
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Freecom FSG-3";
	compatible = "freecom,fsg-3", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* 64 MB memory */
		device_type = "memory";
		reg = <0x00000000 0x4000000>;
	};

	chosen {
		/* Boot from the first partition on the hard drive */
		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};

	gpio_keys {
		compatible = "gpio-keys";

		button-sync {
			wakeup-source;
			/* Closest approximation of what the key should do */
			linux,code = <KEY_CONNECT>;
			label = "sync";
			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
		};
		button-reset {
			wakeup-source;
			linux,code = <KEY_ESC>;
			label = "reset";
			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
		};
		button-usb {
			wakeup-source;
			/* Unplug USB, closest approximation of what the key should do */
			linux,code = <KEY_EJECTCD>;
			label = "usb";
			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
		};
	};

	i2c {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		#address-cells = <1>;
		#size-cells = <0>;

		hwmon@28 {
			/*
			 * Temperature sensor and fan control chip.
			 *
			 * TODO: create a proper device tree binding for
			 * the sensor and temperature zone and create a
			 * zone with fan control.
			 */
			compatible = "winbond,w83781d";
			reg = <0x28>;
		};
		rtc@6f {
			compatible = "isil,isl1208";
			reg = <0x6f>;
		};
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/* Enable writes on the expansion bus */
				intel,ixp4xx-eb-write-enable = <1>;
				/* 4 MB of Flash mapped in at CS0 */
				reg = <0 0x00000000 0x400000>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x3e0000 */
					fis-index-block = <0x1f>;
				};
			};

			/* Small syscon with some LEDs at CS2 */
			syscon@2,0 {
				compatible = "freecom,fsg-cs2-system-controller", "syscon";
				reg = <2 0x0 0x200>;
				reg-io-width = <2>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <2 0x0 0x0 0x200>;

				led@0,0 {
					compatible = "register-bit-led";
					reg = <0x00 0x02>;
					mask = <0x01>;
					label = "fsg:blue:wlan";
					linux,default-trigger = "wlan";
					default-state = "on";
				};
				led@0,1 {
					compatible = "register-bit-led";
					reg = <0x00 0x02>;
					mask = <0x02>;
					label = "fsg:blue:wan";
					linux,default-trigger = "";
					default-state = "on";
				};
				led@0,2 {
					compatible = "register-bit-led";
					reg = <0x00 0x02>;
					mask = <0x04>;
					label = "fsg:blue:sata";
					linux,default-trigger = "";
					default-state = "on";
				};
				led@0,3 {
					compatible = "register-bit-led";
					reg = <0x00 0x02>;
					mask = <0x04>;
					label = "fsg:blue:usb";
					linux,default-trigger = "";
					default-state = "on";
				};
				led@0,4 {
					compatible = "register-bit-led";
					reg = <0x00 0x02>;
					mask = <0x08>;
					label = "fsg:blue:sync";
					linux,default-trigger = "";
					default-state = "on";
				};
				led@0,5 {
					compatible = "register-bit-led";
					reg = <0x00 0x02>;
					mask = <0x10>;
					label = "fsg:blue:ring";
					linux,default-trigger = "";
					default-state = "on";
				};
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * Written based on the FSG-3 PCI boardfile.
			 * We have slots 12, 13 & 14 (IDSEL) with one IRQ each.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 12 */
			<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
			<0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
			<0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
			<0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
			/* IDSEL 13 */
			<0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */
			<0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */
			<0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */
			<0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */
			/* IDSEL 14 */
			<0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */
			<0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */
			<0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */
			<0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */
		};

		/* EthB */
		ethernet@c8009000 {
			status = "ok";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			phy-mode = "rgmii";
			phy-handle = <&phy5>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy4: ethernet-phy@4 {
					reg = <4>;
				};

				phy5: ethernet-phy@5 {
					reg = <5>;
				};
			};
		};

		/* EthC */
		ethernet@c800a000 {
			status = "ok";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy4>;
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for Gateway 7001 AP based on IXP422
 * Derived from boardfiles written by Imre Kaloz
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Gateway 7001 AP";
	compatible = "gateway,7001", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* 32 MB SDRAM */
		device_type = "memory";
		reg = <0x00000000 0x2000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8";
		stdout-path = "uart1:115200n8";
	};

	aliases {
		/* second UART is the primary console */
		serial0 = &uart1;
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/*
				 * 8 MB of flash
				 */
				reg = <0 0x00000000 0x800000>;

				/* Configure expansion bus to allow writes */
				intel,ixp4xx-eb-write-enable = <1>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x7e0000 */
					fis-index-block = <0x3f>;
				};
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c)
			 * We have slots (IDSEL) 1 and 2 with one assigned IRQ
			 * each handling all IRQs.
			 */
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
			<0x0800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 11 */
			<0x0800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 11 */
			<0x0800 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 11 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
			<0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */
			<0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */
			<0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */
		};

		ethernet@c8009000 {
			status = "ok";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			phy-mode = "rgmii";
			phy-handle = <&phy1>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy1: ethernet-phy@1 {
					reg = <1>;
				};
			};
		};

		ethernet@c800a000 {
			status = "ok";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy2>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy2: ethernet-phy@2 {
					reg = <2>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for the Gateworks Avila GW2348 board.
 * This machine is based on IXP425.
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Gateworks Avila GW2348";
	compatible = "gateworks,gw2348", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		device_type = "memory";
		reg = <0x00000000 0x4000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};

	leds {
		compatible = "gpio-leds";
		led-user {
			label = "gw2348:green:user";
			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};
	};

	i2c {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		#address-cells = <1>;
		#size-cells = <0>;

		hwmon@28 {
			compatible = "adi,ad7418";
			reg = <0x28>;
		};
		rtc: ds1672@68 {
			compatible = "dallas,ds1672";
			reg = <0x68>;
		};
		eeprom@51 {
			compatible = "atmel,24c08";
			reg = <0x51>;
			pagesize = <16>;
			size = <1024>;
			read-only;
		};
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/* Enable writes on the expansion bus */
				intel,ixp4xx-eb-write-enable = <1>;
				/* 16 MB of Flash mapped in at CS0 */
				reg = <0 0x00000000 0x1000000>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x0fe0000 */
					fis-index-block = <0x7f>;
				};
			};
			ide@1,0 {
				compatible = "intel,ixp4xx-compact-flash";
				/*
				 * Set up expansion bus config to a really slow timing.
				 * The CF driver will dynamically reconfigure these timings
				 * depending on selected PIO mode (0-4).
				 */
				intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
				intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
				intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
				intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
				intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
				intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
				intel,ixp4xx-eb-byte-access-on-halfword = <1>;
				intel,ixp4xx-eb-mux-address-and-data = <0>;
				intel,ixp4xx-eb-ahb-split-transfers = <0>;
				intel,ixp4xx-eb-write-enable = <1>;
				intel,ixp4xx-eb-byte-access = <1>;
				/* First register set is CMD second is CTL (notice it uses CS2) */
				reg = <1 0x00000000 0x1000000>, <2 0x00000000 0x1000000>;
				interrupt-parent = <&gpio0>;
				interrupts = <12 IRQ_TYPE_EDGE_RISING>;
			};
			/*
			 * FIXME: Latch LEDs or extra UARTs at CS4
			 */
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * Taken from Avila PCI boardfile.
			 *
			 * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
			<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
			<0x0800 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
			<0x0800 0 0 4 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
			<0x1000 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
			<0x1000 0 0 3 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
			<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
			/* IDSEL 3 */
			<0x1800 0 0 1 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
			<0x1800 0 0 2 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
			<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
			<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
			/* IDSEL 4 */
			<0x2000 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
			<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
			<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
			<0x2000 0 0 4 &gpio0 9  IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
		};

		/* EthB */
		ethernet@c8009000 {
			status = "ok";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			phy-mode = "rgmii";
			phy-handle = <&phy0>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy0: ethernet-phy@0 {
					reg = <0>;
				};

				phy1: ethernet-phy@1 {
					reg = <1>;
				};
			};
		};

		/* EthC */
		ethernet@c800a000 {
			status = "ok";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy1>;
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for the Goramo MultiLink Router
 * There are two variants:
 * - MultiLink Basic (a box)
 * - MultiLink Max (19" rack mount)
 * This device tree supports MultiLink Basic.
 * This machine is based on IXP425.
 * This is one of the few devices supporting the IXP4xx High-Speed Serial
 * (HSS) link for a V.35 WAN interface.
 * The hardware originates in Poland.
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Goramo MultiLink Router";
	compatible = "goramo,multilink-router", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/*
		 * 64 MB of RAM according to the manual. The MultiLink
		 * Max has 128 MB.
		 */
		device_type = "memory";
		reg = <0x00000000 0x4000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	/*
	 * 74HC4094 which is used as a rudimentary GPIO expander
	 * FIXME:
	 * - Create device tree bindings for this as GPIO expander
	 * - Write a pure DT GPIO driver using these bindings
	 * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different)
	 */
	gpio_74: gpio-74hc4094 {
		compatible = "nxp,74hc4094";
		cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
		d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
		str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
		/* oe-gpios is optional */
		gpio-controller;
		#gpio-cells = <2>;
		/* We are not cascaded */
		registers-number = <1>;
		gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N",
				"CONTROL_HSS1_DTR_N", "CONTROL_EXT", "CONTROL_AUTO_RESET",
				"CONTROL_PCI_RESET_N", "CONTROL_EEPROM_WC_N";
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/* Enable writes on the expansion bus */
				intel,ixp4xx-eb-write-enable = <1>;
				/* 16 MB of Flash mapped in at CS0 */
				reg = <0 0x00000000 0x1000000>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x0fe0000 */
					fis-index-block = <0x7f>;
				};
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * The device has 4 slots (IDSEL) with one dedicated IRQ per slot.
			 * The slots have Ethernet, Ethernet, NEC and MPCI.
			 * The IDSELs are 11, 12, 13, 14.
			 */
			interrupt-map =
			/* IDSEL 11 - Ethernet A */
			<0x5800 0 0 1 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 11 is irq 4 */
			<0x5800 0 0 2 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 11 is irq 4 */
			<0x5800 0 0 3 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 11 is irq 4 */
			<0x5800 0 0 4 &gpio0 4 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 11 is irq 4 */
			/* IDSEL 12 - Ethernet B */
			<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */
			<0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */
			<0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */
			<0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */
			/* IDSEL 13 - MPCI */
			<0x6800 0 0 1 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 12 */
			<0x6800 0 0 2 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 12 */
			<0x6800 0 0 3 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 12 */
			<0x6800 0 0 4 &gpio0 12 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 12 */
			/* IDSEL 14 - NEC */
			<0x7000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 3 */
			<0x7000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 3 */
			<0x7000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 3 */
			<0x7000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 3 */
		};

		/* HSS links */
		npe@c8006000 {
			hss@0 {
				status = "okay";
				intel,queue-chl-rxtrig = <&qmgr 12>;
				intel,queue-chl-txready = <&qmgr 34>;
				intel,queue-pkt-rx = <&qmgr 13>;
				intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
				intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
				intel,queue-pkt-txdone = <&qmgr 22>;
				/* The Goramo GPIO-based clock etc control */
				cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
				rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
				dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
				dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
				clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
			};
			hss@1 {
				status = "okay";
				intel,queue-chl-rxtrig = <&qmgr 10>;
				intel,queue-chl-txready = <&qmgr 35>;
				intel,queue-pkt-rx = <&qmgr 0>;
				intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>;
				intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>;
				intel,queue-pkt-txdone = <&qmgr 9>;
				/* The Goramo GPIO-based clock etc control */
				cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
				rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
				dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
				dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>;
				clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>;
			};
		};

		/* EthB */
		ethernet@c8009000 {
			status = "ok";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 32>;
			phy-mode = "rgmii";
			phy-handle = <&phy0>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy0: ethernet-phy@0 {
					reg = <0>;
				};

				phy1: ethernet-phy@1 {
					reg = <1>;
				};
			};
		};

		/* EthC */
		ethernet@c800a000 {
			status = "ok";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 33>;
			phy-mode = "rgmii";
			phy-handle = <&phy1>;
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for Iomega NAS 100D
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Iomega NAS 100D";
	compatible = "iom,nas-100d", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* 64 MB SDRAM */
		device_type = "memory";
		reg = <0x00000000 0x4000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};

	leds {
		compatible = "gpio-leds";
		led-wlan {
			label = "nas100d:red:wlan";
			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			/* We don't have WLAN trigger in the kernel (yet) */
			linux,default-trigger = "netdev";
		};
		led-disk {
			label = "nas100d:red:disk";
			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "disk-activity";
		};
		led-power {
			label = "nas100d:red:power";
			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};
	};

	gpio_keys {
		compatible = "gpio-keys";

		button-power {
			wakeup-source;
			linux,code = <KEY_POWER>;
			label = "power";
			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
		};
		button-reset {
			wakeup-source;
			linux,code = <KEY_ESC>;
			label = "reset";
			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
		};
	};

	i2c {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		#address-cells = <1>;
		#size-cells = <0>;

		rtc@51 {
			compatible = "nxp,pcf8563";
			reg = <0x51>;
		};
	};

	gpio-poweroff {
		compatible = "gpio-poweroff";
		gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
		timeout-ms = <5000>;
	};

	soc {
		bus@c4000000 {
			/* The first 16MB region at CS0 on the expansion bus */
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/*
				 * 8 MB of Flash in 0x20000 byte blocks
				 * mapped in at CS0.
				 */
				reg = <0 0x00000000 0x800000>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x7e0000 */
					fis-index-block = <0x3f>;
				};
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * Taken from NAS 100D PCI boardfile (nas100d-pci.c)
			 * We have slots (IDSEL) 1, 2 and 3 and pins 1, 2 and 3.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
			/* IDSEL 3 */
			<0x1800 0 0 1 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
			<0x1800 0 0 2 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
			<0x1800 0 0 3 &gpio0 7  IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 3 is irq 7 */
		};

		ethernet@c8009000 {
			status = "ok";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			phy-mode = "rgmii";
			phy-handle = <&phy0>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy0: ethernet-phy@0 {
					reg = <0>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for the Intel IXDP425 also known as IXCDP1100 Control Plane
 * processor reference design.
 *
 * This platform has the codename "Richfield".
 *
 * This machine is based on a 533 MHz IXP425.
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include "intel-ixp4xx-reference-design.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Intel IXDP425/IXCDP1100 Richfield Reference Design";
	compatible = "intel,ixdp425", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/* Enable writes on the expansion bus */
				intel,ixp4xx-eb-write-enable = <1>;
				/* 16 MB of Flash mapped in at CS0 */
				reg = <0 0x00000000 0x1000000>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x0fe0000 */
					fis-index-block = <0x7f>;
				};
			};
		};

		/* EthB */
		ethernet@c8009000 {
			status = "ok";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			phy-mode = "rgmii";
			phy-handle = <&phy0>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy0: ethernet-phy@0 {
					reg = <0>;
				};

				phy1: ethernet-phy@1 {
					reg = <1>;
				};
			};
		};

		/* EthC */
		ethernet@c800a000 {
			status = "ok";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy1>;
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for the Intel IXDPG425 reference design.
 * Derived from boardfiles written by MontaVista software.
 * Ethernet set-up from OpenWrt.
 *
 * The device has 4 x FXS RJ11 ports for analog phones for
 * internet telephony. (Not supported yet.)
 *
 * The device has 9 status LEDs we do not support yet.
 *
 * This device is very similar to ADI engingeering Coyote.
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Intel IXDPG425 reference design";
	compatible = "intel,ixdpg425", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* 32 MB SDRAM */
		device_type = "memory";
		reg = <0x00000000 0x02000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/*
				 * CHECKME: the product brief says 16MB in a flash
				 * socket.
				 */
				reg = <0 0x00000000 0x1000000>;

				/* Configure expansion bus to allow writes */
				intel,ixp4xx-eb-write-enable = <1>;

				partitions {
					compatible = "redboot-fis";
					/* CHECKME: guess this is Redboot FIS */
					fis-index-block = <0x7f>;
				};
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * Taken from IXDPG425 PCI boardfile.
			 * We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ
			 * for 12 & 13 and one for 14.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 12 */
			<0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */
			<0x6000 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 7 */
			<0x6000 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 7 */
			<0x6000 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 7 */
			/* IDSEL 13 */
			<0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */
			<0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */
			<0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */
			<0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */
			/* IDSEL 14 */
			<0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */
			<0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */
			<0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */
			<0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */
		};

		/*
		 * CHECKME: this ethernet setup seems dubious. Photos of the board shows some kind
		 * of Realtek DSA switch on the board.
		 */

		/* EthB */
		ethernet@c8009000 {
			status = "ok";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			phy-mode = "rgmii";
			phy-handle = <&phy5>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy4: ethernet-phy@4 {
					reg = <4>;
				};

				phy5: ethernet-phy@5 {
					reg = <5>;
				};
			};
		};

		/* EthC */
		ethernet@c800a000 {
			status = "ok";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy4>;
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for Linksys NSLU2
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Linksys NSLU2 (Network Storage Link for USB 2.0 Disk Drives)";
	compatible = "linksys,nslu2", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* 32 MB SDRAM */
		device_type = "memory";
		reg = <0x00000000 0x2000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};

	leds {
		compatible = "gpio-leds";
		led-status {
			label = "nslu2:red:status";
			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};
		led-ready {
			label = "nslu2:green:ready";
			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
			default-state = "on";
		};
		led-disk-1 {
			label = "nslu2:green:disk-1";
			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
		led-disk-2 {
			label = "nslu2:green:disk-2";
			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
			default-state = "off";
		};
	};

	gpio_keys {
		compatible = "gpio-keys";

		button-power {
			wakeup-source;
			linux,code = <KEY_POWER>;
			label = "power";
			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
		};
		button-reset {
			wakeup-source;
			linux,code = <KEY_ESC>;
			label = "reset";
			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
		};
	};

	i2c {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		#address-cells = <1>;
		#size-cells = <0>;

		rtc@6f {
			compatible = "xicor,x1205";
			reg = <0x6f>;
		};
	};

	gpio-poweroff {
		compatible = "gpio-poweroff";
		gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
		timeout-ms = <5000>;
	};

	gpio-beeper {
		compatible = "gpio-beeper";
		gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
	};

	soc {
		bus@c4000000 {
			/* The first 16MB region at CS0 on the expansion bus */
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/*
				 * 8 MB of Flash in 0x20000 byte blocks
				 * mapped in at CS0.
				 */
				reg = <0 0x00000000 0x800000>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x7e0000 */
					fis-index-block = <0x3f>;
				};
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
			 * We have slots (IDSEL) 1, 2 and 3.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
			<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
			<0x0800 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
			<0x0800 0 0 4 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
			<0x1000 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
			<0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */
			<0x1000 0 0 4 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 8 */
			/* IDSEL 3 */
			<0x1800 0 0 1 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
			<0x1800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
			<0x1800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
			<0x1800 0 0 4 &gpio0 8  IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 8 */
		};

		ethernet@c8009000 {
			status = "ok";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			phy-mode = "rgmii";
			phy-handle = <&phy1>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy1: ethernet-phy@1 {
					reg = <1>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for the Linksys WRV54G router
 * Also known as Gemtek GTWX5715
 * Based on a board file by George T. Joseph and other patches.
 * This machine is based on IXP425.
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Linksys WRV54G / Gemtek GTWX5715";
	compatible = "linksys,wrv54g", "gemtek,gtwx5715", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* 32 MB memory */
		device_type = "memory";
		reg = <0x00000000 0x2000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8";
		stdout-path = "uart1:115200n8";
	};

	aliases {
		/* UART2 is the primary console */
		serial0 = &uart1;
		serial1 = &uart0;
	};

	/* There is an unpopulated LED slot (3) connected to GPIO 8 */
	leds {
		compatible = "gpio-leds";
		led-power {
			label = "wrv54g:yellow:power";
			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};
		led-wireless {
			label = "wrv54g:yellow:wireless";
			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};
		led-internet {
			label = "wrv54g:yellow:internet";
			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};
		led-dmz {
			label = "wrv54g:green:dmz";
			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};
	};

	/* This set-up comes from an OpenWrt patch */
	spi {
		compatible = "spi-gpio";
		#address-cells = <1>;
		#size-cells = <0>;

		sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
		miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
		mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
		cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
		num-chipselects = <1>;

		switch@0 {
			compatible = "micrel,ks8995";
			reg = <0>;
			spi-max-frequency = <50000000>;
		};
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/* Enable writes on the expansion bus */
				intel,ixp4xx-eb-write-enable = <1>;
				/* 8 MB of Flash mapped in at CS0 */
				reg = <0 0x00000000 0x00800000>;

				partitions {
					compatible = "fixed-partitions";
					/*
					 * Partition info from a boot log
					 * CHECKME: not using redboot? FIS index 0x3f @7e00000?
					 */
					#address-cells = <1>;
					#size-cells = <1>;
					partition@0 {
						label = "boot";
						reg = <0x0 0x140000>;
						read-only;
					};
					partition@140000 {
						label = "linux";
						reg = <0x140000 0x100000>;
						read-only;
					};
					partition@240000 {
						label = "root";
						reg = <0x240000 0x480000>;
						read-write;
					};
				};
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * We have up to 2 slots (IDSEL) with 2 swizzled IRQs.
			 * Derived from the GTWX5715 PCI boardfile.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 0 */
			<0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */
			<0x0000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 0 is irq 11 */
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
			<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 1 is irq 10 */
		};

		/*
		 * EthB - connected to the KS8995 switch ports 1-4
		 * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to
		 * all four switch ports, also using an out of tree multiphy patch.
		 * Do we need a new binding and property for this?
		 */
		ethernet@c8009000 {
			status = "ok";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			phy-mode = "rgmii";
			phy-handle = <&phy4>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				/* Should be ports 1-4 on the KS8995 switch */
				phy4: ethernet-phy@4 {
					reg = <4>;
				};

				/* Should be port 5 on the KS8995 switch */
				phy5: ethernet-phy@5 {
					reg = <5>;
				};
			};
		};

		/* EthC - connected to KS8995 switch port 5 */
		ethernet@c800a000 {
			status = "ok";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy5>;
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for Netgear WG302v2 based on IXP422BB
 * Derived from boardfiles written by Imre Kaloz
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Netgear WG302 v1";
	compatible = "netgear,wg302v1", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* 32 MB SDRAM according to boot arguments */
		device_type = "memory";
		reg = <0x00000000 0x02000000>;
	};

	chosen {
		/* The RedBoot comes up in 9600 baud so let's keep this */
		bootargs = "console=ttyS0,9600n8";
		stdout-path = "uart1:9600n8";
	};

	aliases {
		/* These are switched around */
		serial0 = &uart1;
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/*
				 * 8 MB of Flash in 64 0x20000 sized blocks
				 * mapped in at CS0.
				 */
				reg = <0 0x00000000 0x800000>;

				/* Configure expansion bus to allow writes */
				intel,ixp4xx-eb-write-enable = <1>;

				partitions {
					compatible = "redboot-fis";
					fis-index-block = <0x3f>;
				};
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c)
			 * We have slots (IDSEL) 1 and 2 with one assigned IRQ
			 * each handling all IRQs.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */
			<0x0800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 8 */
			<0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */
			<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */
			<0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
			<0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */
			<0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */
		};

		ethernet@c8009000 {
			status = "ok";
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			phy-mode = "rgmii";
			phy-handle = <&phy30>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy30: ethernet-phy@30 {
					reg = <30>;
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2021 Corentin Labbe <clabbe@baylibre.com>
 */

/dts-v1/;

#include "intel-ixp42x.dtsi"

/ {
	model = "Welltech EPBX100";
	compatible = "welltech,epbx100", "intel,ixp42x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* 64 MB SDRAM */
		device_type = "memory";
		reg = <0x00000000 0x4000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 root=/dev/ram0 initrd=0x00800000,9M";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/*
				 * 16 MB of Flash
				 */
				reg = <0 0x00000000 0x1000000>;

				partitions {
					compatible = "fixed-partitions";
					#address-cells = <1>;
					#size-cells = <1>;

					partition@0 {
						label = "RedBoot";
						reg = <0x00000000 0x00080000>;
						read-only;
					};
					partition@80000 {
						label = "zImage";
						reg = <0x00080000 0x00100000>;
						read-only;
					};
					partition@180000 {
						label = "ramdisk";
						reg = <0x00180000 0x00300000>;
						read-only;
					};
					partition@480000 {
						label = "User";
						reg = <0x00480000 0x00b60000>;
						read-only;
					};
					partition@fe0000 {
						label = "FIS directory";
						reg = <0x00fe0000 0x001f000>;
						read-only;
					};
					partition@fff000 {
						label = "RedBoot config";
						reg = <0x00fff000 0x0001000>;
						read-only;
					};
				};
			};
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for Intel XScale Network Processors
 * in the IXP 42x series. This series has 32 interrupts.
 */
#include "intel-ixp4xx.dtsi"

/ {
	soc {
		bus@c4000000 {
			compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
			reg = <0xc4000000 0x30>;
		};

		pci@c0000000 {
			compatible = "intel,ixp42x-pci";
		};

		interrupt-controller@c8003000 {
			compatible = "intel,ixp42x-interrupt";
		};

		/*
		 * This is the USB Device Mode (UDC) controller, which is used
		 * to present the IXP4xx as a device on a USB bus.
		 */
		usb@c800b000 {
			compatible = "intel,ixp4xx-udc";
			reg = <0xc800b000 0x1000>;
			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for Gateworks IXP43x-based Cambria GW2358
 */

/dts-v1/;

#include "intel-ixp43x.dtsi"

/ {
	model = "Gateworks Cambria GW2358";
	compatible = "gateworks,gw2358", "intel,ixp43x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* 128 MB SDRAM */
		device_type = "memory";
		reg = <0x00000000 0x8000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};

	leds {
		compatible = "gpio-leds";
		led-user {
			label = "gw2358:green:LED";
			gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};
	};

	i2c {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		#address-cells = <1>;
		#size-cells = <0>;

		hwmon@28 {
			compatible = "adi,ad7418";
			reg = <0x28>;
		};
		rtc: ds1672@68 {
			compatible = "dallas,ds1672";
			reg = <0x68>;
		};
		eeprom@51 {
			compatible = "atmel,24c08";
			reg = <0x51>;
			pagesize = <16>;
			size = <1024>;
			read-only;
		};
		pld0: pld@56 {
			compatible = "gateworks,pld-gpio";
			reg = <0x56>;
			gpio-controller;
			#gpio-cells = <2>;
		};
		/* This PLD just handles the LED and user button */
		pld1: pld@57 {
			compatible = "gateworks,pld-gpio";
			reg = <0x57>;
			gpio-controller;
			#gpio-cells = <2>;
		};
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/* Enable writes on the expansion bus */
				intel,ixp4xx-eb-write-enable = <1>;
				/*
				 * 32 MB of Flash in 0x20000 byte blocks
				 * mapped in at CS0 and CS1
				 */
				reg = <0 0x00000000 0x2000000>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x1fe0000 */
					fis-index-block = <0xff>;
				};
			};
			ide@3,0 {
				compatible = "intel,ixp4xx-compact-flash";
				/*
				 * Set up expansion bus config to a really slow timing.
				 * The CF driver will dynamically reconfigure these timings
				 * depending on selected PIO mode (0-4).
				 */
				intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
				intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
				intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
				intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
				intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
				intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
				intel,ixp4xx-eb-byte-access-on-halfword = <1>;
				intel,ixp4xx-eb-mux-address-and-data = <0>;
				intel,ixp4xx-eb-ahb-split-transfers = <0>;
				intel,ixp4xx-eb-write-enable = <1>;
				intel,ixp4xx-eb-byte-access = <1>;
				/* First register set is CMD second is CTL */
				reg = <3 0xe00000 0x40000>, <3 0xe40000 0x40000>;
				interrupt-parent = <&gpio0>;
				interrupts = <12 IRQ_TYPE_EDGE_RISING>;
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * In the boardfile for the Cambria from OpenWRT the interrupts
			 * are assigned one per IDSEL, so all 4 interrupts from IDSEL
			 * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
			 * connected to IRQ 10 etc. I find this highly unlikely so I
			 * have instead assumed that they are rotated (swizzled) like
			 * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
			<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
			<0x0800 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
			<0x0800 0 0 4 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
			<0x1000 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
			<0x1000 0 0 3 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
			<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
			/* IDSEL 3 */
			<0x1800 0 0 1 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
			<0x1800 0 0 2 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
			<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
			<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
			/* IDSEL 4 */
			<0x2000 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
			<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
			<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
			<0x2000 0 0 4 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */
			/* IDSEL 6 */
			<0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */
			<0x3000 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */
			<0x3000 0 0 3 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 8 */
			<0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */
			/* IDSEL 15 */
			<0x7800 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
			<0x7800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
			<0x7800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
			<0x7800 0 0 4 &gpio0 9  IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */
		};

		ethernet@c800a000 {
			status = "ok";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy1>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy1: ethernet-phy@1 {
					reg = <1>;
				};

				phy2: ethernet-phy@2 {
					reg = <2>;
				};
			};
		};

		ethernet@c800c000 {
			status = "ok";
			queue-rx = <&qmgr 2>;
			queue-txready = <&qmgr 19>;
			phy-mode = "rgmii";
			phy-handle = <&phy2>;
			intel,npe-handle = <&npe 0>;
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for the Intel KIXRP435 Control Plane
 * processor reference design.
 */

/dts-v1/;

#include "intel-ixp43x.dtsi"
#include "intel-ixp4xx-reference-design.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Intel KIXRP435 Reference Design";
	compatible = "intel,kixrp435", "intel,ixp43x";
	#address-cells = <1>;
	#size-cells = <1>;

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/* Enable writes on the expansion bus */
				intel,ixp4xx-eb-write-enable = <1>;
				/* 16 MB of Flash mapped in at CS0 */
				reg = <0 0x00000000 0x1000000>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x0fe0000 */
					fis-index-block = <0x7f>;
				};
			};
		};

		/* CHECKME: ethernet set-up taken from Gateworks Cambria */
		ethernet@c800a000 {
			status = "ok";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy1>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy1: ethernet-phy@1 {
					reg = <1>;
				};

				phy2: ethernet-phy@2 {
					reg = <2>;
				};
			};
		};

		ethernet@c800c000 {
			status = "ok";
			queue-rx = <&qmgr 2>;
			queue-txready = <&qmgr 19>;
			phy-mode = "rgmii";
			phy-handle = <&phy2>;
			intel,npe-handle = <&npe 0>;
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for Intel XScale Network Processors
 * in the IXP 43x series. This series has 64 interrupts and adds a few more
 * peripherals over the 42x series.
 */
#include "intel-ixp4xx.dtsi"

/ {
	soc {
		bus@c4000000 {
			compatible = "intel,ixp43x-expansion-bus-controller", "syscon";
			/* Uses at least up to 0x230 */
			reg = <0xc4000000 0x1000>;
		};

		pci@c0000000 {
			compatible = "intel,ixp43x-pci";
		};

		interrupt-controller@c8003000 {
			compatible = "intel,ixp43x-interrupt";
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for Intel XScale Network Processors
 * in the IXP45x and IXP46x series. This series has 64 interrupts and adds a
 * few more peripherals over the 42x and 43x series so this extends the
 * basic IXP4xx DTSI.
 */
#include "intel-ixp4xx.dtsi"

/ {
	soc {
		bus@c4000000 {
			compatible = "intel,ixp46x-expansion-bus-controller", "syscon";
			/* Uses at least up to 0x124 */
			reg = <0xc4000000 0x1000>;
		};

		rng@70002100 {
			compatible = "intel,ixp46x-rng";
			reg = <0x70002100 4>;
		};

		interrupt-controller@c8003000 {
			compatible = "intel,ixp43x-interrupt";
		};

		/*
		 * This is the USB Device Mode (UDC) controller, which is used
		 * to present the IXP4xx as a device on a USB bus.
		 */
		usb@c800b000 {
			compatible = "intel,ixp4xx-udc";
			reg = <0xc800b000 0x1000>;
			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		i2c@c8011000 {
			compatible = "intel,ixp4xx-i2c";
			reg = <0xc8011000 0x18>;
			interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		/* This is known as EthB1 */
		ethernet@c800d000 {
			compatible = "intel,ixp4xx-ethernet";
			reg = <0xc800d000 0x1000>;
			status = "disabled";
			intel,npe = <1>;
			/* Dummy values that depend on firmware */
			queue-rx = <&qmgr 0>;
			queue-txready = <&qmgr 0>;
		};

		/* This is known as EthB2 */
		ethernet@c800e000 {
			compatible = "intel,ixp4xx-ethernet";
			reg = <0xc800e000 0x1000>;
			status = "disabled";
			intel,npe = <2>;
			/* Dummy values that depend on firmware */
			queue-rx = <&qmgr 0>;
			queue-txready = <&qmgr 0>;
		};

		/* This is known as EthB3 */
		ethernet@c800f000 {
			compatible = "intel,ixp4xx-ethernet";
			reg = <0xc800f000 0x1000>;
			status = "disabled";
			intel,npe = <3>;
			/* Dummy values that depend on firmware */
			queue-rx = <&qmgr 0>;
			queue-txready = <&qmgr 0>;
		};

		ptp-timer@c8010000 {
			compatible = "intel,ixp46x-ptp-timer";
			reg = <0xc8010000 0x1000>;
			interrupt-parent = <&gpio0>;
			interrupts = <8 IRQ_TYPE_EDGE_FALLING>, <7 IRQ_TYPE_EDGE_FALLING>;
			interrupt-names = "master", "slave";
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for the Intel IXDP465 Control Plane processor reference
 * design, codename "BMP".
 */

/dts-v1/;

#include "intel-ixp45x-ixp46x.dtsi"
#include "intel-ixp4xx-reference-design.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Intel IXDP465 BMP Reference Design";
	compatible = "intel,ixdp465", "intel,ixp46x";
	#address-cells = <1>;
	#size-cells = <1>;

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/* Enable writes on the expansion bus */
				intel,ixp4xx-eb-write-enable = <1>;
				/* 32 MB of Flash mapped in at CS0 and CS1 */
				reg = <0 0x00000000 0x2000000>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x1fe0000 */
					fis-index-block = <0xff>;
				};
			};
		};
		/* TODO: configure ethernet etc */
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree include file for Intel reference designs for the
 * XScale Network Processors in the IXP 4xx series. Common device
 * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465.
 */

/ {
	memory@0 {
		/*
		 * The board supports up to 256 MB of memory. Here we put in
		 * 64 MB and this may be modified by the boot loader.
		 */
		device_type = "memory";
		reg = <0x00000000 0x4000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};

	i2c {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		#address-cells = <1>;
		#size-cells = <0>;

		eeprom@50 {
			/*
			 * Philips PCF8582C-2T/03 512byte I2C EEPROM
			 * should behave like an Atmel 24c04.
			 */
			compatible = "atmel,24c04";
			reg = <0x50>;
			pagesize = <16>;
			size = <512>;
			read-only;
		};
	};

	soc {
		bus@c4000000 {
			/* Flash memory defined per-variant */
			nand-controller@3,0 {
				/* Some designs have a NAND on CS3 enable it here if present */
				status = "disabled";

				/*
				 * gen_nand needs to be extended and documented to get
				 * command byte = 1 and address byte = 2 from the device
				 * tree.
				 */
				compatible = "gen_nand";

				/* Expansion bus set-up */
				intel,ixp4xx-eb-t1 = <0>;
				intel,ixp4xx-eb-t2 = <0>;
				intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase
				intel,ixp4xx-eb-t4 = <0>;
				intel,ixp4xx-eb-t5 = <0>;
				intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
				intel,ixp4xx-eb-byte-access-on-halfword = <0>;
				intel,ixp4xx-eb-mux-address-and-data = <0>;
				intel,ixp4xx-eb-ahb-split-transfers = <0>;
				intel,ixp4xx-eb-write-enable = <1>;
				intel,ixp4xx-eb-byte-access = <1>;

				/* 512 bytes memory window */
				reg = <3 0x00000000 0x200>;
				nand-on-flash-bbt;
				nand-ecc-mode = "soft_bch";
				nand-ecc-step-size = <512>;
				nand-ecc-strength = <4>;
				nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */

				label = "ixp400 NAND";

				partitions {
					compatible = "fixed-partitions";
					#address-cells = <1>;
					#size-cells = <1>;

					fs@0 {
						label = "ixp400 NAND FS 0";
						reg = <0x0 0x800000>;
					};
					fs@800000 {
						label = "ixp400 NAND FS 1";
						reg = <0x800000 0x0>;
					};
				};
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * Taken from IXDP425 PCI boardfile.
			 * PCI slots on the BIXMB425BD base card.
			 * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
			<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
			<0x0800 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
			<0x0800 0 0 4 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
			<0x1000 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
			<0x1000 0 0 3 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
			<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
			/* IDSEL 3 */
			<0x1800 0 0 1 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
			<0x1800 0 0 2 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
			<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
			<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
			/* IDSEL 4 */
			<0x2000 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
			<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
			<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
			<0x2000 0 0 4 &gpio0 9  IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
		};
	};
};


code:
// SPDX-License-Identifier: ISC
/*
 * Device Tree file for Intel XScale Network Processors
 * in the IXP 4xx series.
 */
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";
		interrupt-parent = <&intcon>;

		/*
		 * The IXP4xx expansion bus is a set of up to 7 each up to 16MB
		 * windows in the 256MB space from 0x50000000 to 0x5fffffff.
		 */
		bus@c4000000 {
			/* compatible and reg filled in by per-soc device tree */
			native-endian;
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <0 0x0 0x50000000 0x01000000>,
				 <1 0x0 0x51000000 0x01000000>,
				 <2 0x0 0x52000000 0x01000000>,
				 <3 0x0 0x53000000 0x01000000>,
				 <4 0x0 0x54000000 0x01000000>,
				 <5 0x0 0x55000000 0x01000000>,
				 <6 0x0 0x56000000 0x01000000>,
				 <7 0x0 0x57000000 0x01000000>;
			dma-ranges = <0 0x0 0x50000000 0x01000000>,
				 <1 0x0 0x51000000 0x01000000>,
				 <2 0x0 0x52000000 0x01000000>,
				 <3 0x0 0x53000000 0x01000000>,
				 <4 0x0 0x54000000 0x01000000>,
				 <5 0x0 0x55000000 0x01000000>,
				 <6 0x0 0x56000000 0x01000000>,
				 <7 0x0 0x57000000 0x01000000>;
		};

		qmgr: queue-manager@60000000 {
			compatible = "intel,ixp4xx-ahb-queue-manager";
			reg = <0x60000000 0x4000>;
			interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
		};

		pci@c0000000 {
			/* compatible filled in by per-soc device tree */
			reg = <0xc0000000 0x1000>;
			interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
				     <9 IRQ_TYPE_LEVEL_HIGH>,
				     <10 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			bus-range = <0x00 0xff>;
			status = "disabled";

			ranges =
			/*
			 * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
			 * done in 4 chunks of 16MB each.
			 */
			<0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
			/* 64KB I/O space at 0x4c000000 */
			<0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;

			/*
			 * This needs to map to the start of physical memory so
			 * PCI devices can see all (hopefully) memory. This is done
			 * using 4 1:1 16MB windows, so the RAM should not be more than
			 * 64 MB for this to work. If your memory is anywhere else
			 * than at 0x0 you need to alter this.
			 */
			dma-ranges =
			<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;

			/* Each unique DTS using PCI must specify the swizzling */
		};

		uart0: serial@c8000000 {
			compatible = "intel,xscale-uart";
			reg = <0xc8000000 0x1000>;
			/*
			 * The reg-offset and reg-shift is a side effect
			 * of running the platform in big endian mode.
			 */
			reg-offset = <3>;
			reg-shift = <2>;
			interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <14745600>;
			no-loopback-test;
		};

		uart1: serial@c8001000 {
			compatible = "intel,xscale-uart";
			reg = <0xc8001000 0x1000>;
			/*
			 * The reg-offset and reg-shift is a side effect
			 * of running the platform in big endian mode.
			 */
			reg-offset = <3>;
			reg-shift = <2>;
			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <14745600>;
			no-loopback-test;
		};

		gpio0: gpio@c8004000 {
			compatible = "intel,ixp4xx-gpio";
			reg = <0xc8004000 0x1000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		intcon: interrupt-controller@c8003000 {
			/*
			 * Note: no compatible string. The subvariant of the
			 * chip needs to define what version it is. The
			 * location of the interrupt controller is fixed in
			 * memory across all variants.
			 */
			reg = <0xc8003000 0x100>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		timer@c8005000 {
			compatible = "intel,ixp4xx-timer";
			reg = <0xc8005000 0x100>;
			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
		};

		npe: npe@c8006000 {
			compatible = "intel,ixp4xx-network-processing-engine";
			reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			/* NPE-A contains two high-speed serial links */
			hss@0 {
				compatible = "intel,ixp4xx-hss";
				reg = <0>;
				intel,npe-handle = <&npe 0>;
				status = "disabled";
			};

			hss@1 {
				compatible = "intel,ixp4xx-hss";
				reg = <1>;
				intel,npe-handle = <&npe 0>;
				status = "disabled";
			};

			/* NPE-C contains a crypto accelerator */
			crypto {
				compatible = "intel,ixp4xx-crypto";
				intel,npe-handle = <&npe 2>;
				queue-rx = <&qmgr 30>;
				queue-txready = <&qmgr 29>;
			};
		};

		/* This is known as EthB */
		ethernet@c8009000 {
			compatible = "intel,ixp4xx-ethernet";
			reg = <0xc8009000 0x1000>;
			status = "disabled";
			/* Dummy values that depend on firmware */
			queue-rx = <&qmgr 3>;
			queue-txready = <&qmgr 20>;
			intel,npe-handle = <&npe 1>;
		};

		/* This is known as EthC */
		ethernet@c800a000 {
			compatible = "intel,ixp4xx-ethernet";
			reg = <0xc800a000 0x1000>;
			status = "disabled";
			/* Dummy values that depend on firmware */
			queue-rx = <&qmgr 0>;
			queue-txready = <&qmgr 0>;
			intel,npe-handle = <&npe 2>;
		};

		/* This is known as EthA */
		ethernet@c800c000 {
			compatible = "intel,ixp4xx-ethernet";
			reg = <0xc800c000 0x1000>;
			status = "disabled";
			intel,npe = <0>;
			/* Dummy values that depend on firmware */
			queue-rx = <&qmgr 0>;
			queue-txready = <&qmgr 0>;
		};
	};
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board
 *
 * Copyright (C) 2017 Renesas Electronics Corp.
 */

/*
 * SSI-SGTL5000
 *
 * This command is required when Playback/Capture
 *
 *      amixer set "DVC Out" 100%
 *      amixer set "DVC In" 100%
 *
 * You can use Mute
 *
 *      amixer set "DVC Out Mute" on
 *      amixer set "DVC In Mute" on
 *
 * You can use Volume Ramp
 *
 *      amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
 *      amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
 *      amixer set "DVC Out Ramp" on
 *      aplay xxx.wav &
 *      amixer set "DVC Out"  80%  // Volume Down
 *      amixer set "DVC Out" 100%  // Volume Up
 */

/ {
	aliases {
		serial0 = &scif0;
		serial3 = &scifb1;
		ethernet0 = &avb;
	};

	chosen {
		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
		stdout-path = "serial0:115200n8";
	};

	audio_clock: audio_clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
	};

	lcd_backlight: backlight {
		compatible = "pwm-backlight";

		pwms = <&pwm3 0 5000000 0>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <7>;
		enable-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
	};

	lvds-receiver {
		compatible = "ti,ds90cf384a", "lvds-decoder";
		power-supply = <&vcc_3v3_tft1>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				lvds_receiver_in: endpoint {
					remote-endpoint = <&lvds0_out>;
				};
			};
			port@1 {
				reg = <1>;
				lvds_receiver_out: endpoint {
					remote-endpoint = <&panel_in>;
				};
			};
		};
	};

	panel {
		compatible = "edt,etm0700g0dh6";
		backlight = <&lcd_backlight>;
		power-supply = <&vcc_3v3_tft1>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&lvds_receiver_out>;
			};
		};
	};

	reg_1p5v: 1p5v {
		compatible = "regulator-fixed";
		regulator-name = "1P5V";
		regulator-min-microvolt = <1500000>;
		regulator-max-microvolt = <1500000>;
		regulator-always-on;
	};

	rsnd_sgtl5000: sound {
		compatible = "simple-audio-card";

		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&sndcodec>;
		simple-audio-card,frame-master = <&sndcodec>;

		sndcpu: simple-audio-card,cpu {
			sound-dai = <&rcar_sound>;
		};

		sndcodec: simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
		};
	};

	vcc_3v3_tft1: regulator-panel {
		compatible = "regulator-fixed";

		regulator-name = "vcc-3v3-tft1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		enable-active-high;
		startup-delay-us = <500>;
		gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
	};

	vcc_sdhi1: regulator-vcc-sdhi1 {
		compatible = "regulator-fixed";

		regulator-name = "SDHI1 Vcc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;

		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
	};

	vccq_sdhi1: regulator-vccq-sdhi1 {
		compatible = "regulator-gpio";

		regulator-name = "SDHI1 VccQ";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;

		gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
		gpios-states = <1>;
		states = <3300000 1>, <1800000 0>;
	};
};

&avb {
	pinctrl-0 = <&avb_pins>;
	pinctrl-names = "default";

	phy-handle = <&phy3>;
	phy-mode = "gmii";
	renesas,no-ether-link;
	status = "okay";

	phy3: ethernet-phy@3 {
		compatible = "ethernet-phy-id0022.1622",
			     "ethernet-phy-ieee802.3-c22";
		reg = <3>;
		micrel,led-mode = <1>;
	};
};

&can0 {
	pinctrl-0 = <&can0_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&cmt0 {
	status = "okay";
};

&du {
	status = "okay";
};

&gpio2 {
	touch-interrupt-hog {
		gpio-hog;
		gpios = <12 GPIO_ACTIVE_LOW>;
		input;
	};
};

&hsusb {
	status = "okay";
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
};

&i2c2 {
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	rtc@68 {
		compatible = "ti,bq32000";
		reg = <0x68>;
	};

	sgtl5000: codec@a {
		compatible = "fsl,sgtl5000";
		#sound-dai-cells = <0>;
		reg = <0x0a>;
		clocks = <&audio_clock>;
		VDDA-supply = <&reg_3p3v>;
		VDDIO-supply = <&reg_3p3v>;
		VDDD-supply = <&reg_1p5v>;
	};

	touch: touchpanel@38 {
		compatible = "edt,edt-ft5406";
		reg = <0x38>;
		interrupt-parent = <&gpio2>;
		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
		vcc-supply = <&vcc_3v3_tft1>;
	};
};

&lvds0 {
	status = "okay";

	ports {
		port@1 {
			lvds0_out: endpoint {
				remote-endpoint = <&lvds_receiver_in>;
			};
		};
	};
};

&pci0 {
	pinctrl-0 = <&usb0_pins>;
	pinctrl-names = "default";
};

&pci1 {
	status = "okay";
	pinctrl-0 = <&usb1_pins>;
	pinctrl-names = "default";
};

&pcie_bus_clk {
	clock-frequency = <100000000>;
};

&pfc {
	can0_pins: can0 {
		groups = "can0_data_d";
		function = "can0";
	};

	avb_pins: avb {
		groups = "avb_mdio", "avb_gmii";
		function = "avb";
	};

	i2c2_pins: i2c2 {
		groups = "i2c2";
		function = "i2c2";
	};

	pwm3_pins: pwm3 {
		groups = "pwm3";
		function = "pwm3";
	};

	scif0_pins: scif0 {
		groups = "scif0_data_d";
		function = "scif0";
	};

	scifb1_pins: scifb1 {
		groups = "scifb1_data_d", "scifb1_ctrl";
		function = "scifb1";
	};

	sdhi1_pins: sd1 {
		groups = "sdhi1_data4", "sdhi1_ctrl";
		function = "sdhi1";
		power-source = <3300>;
	};

	sdhi1_pins_uhs: sd1_uhs {
		groups = "sdhi1_data4", "sdhi1_ctrl";
		function = "sdhi1";
		power-source = <1800>;
	};

	sound_pins: sound {
		groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
		function = "ssi";
	};

	usb0_pins: usb0 {
		groups = "usb0";
		function = "usb0";
	};

	usb1_pins: usb1 {
		groups = "usb1";
		function = "usb1";
	};
};

&pwm3 {
	pinctrl-0 = <&pwm3_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&rcar_sound {
	pinctrl-0 = <&sound_pins>;
	pinctrl-names = "default";
	status = "okay";

	/* Single DAI */
	#sound-dai-cells = <0>;

	rcar_sound,dai {
		dai0 {
			playback = <&ssi1>, <&src3>, <&dvc1>;
			capture = <&ssi0>, <&src2>, <&dvc0>;
		};
	};
};

&rwdt {
	timeout-sec = <60>;
	status = "okay";
};

&scif0 {
	pinctrl-0 = <&scif0_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&scifb1 {
	pinctrl-0 = <&scifb1_pins>;
	pinctrl-names = "default";

	uart-has-rtscts;
	status = "okay";
};

&sdhi1 {
	pinctrl-0 = <&sdhi1_pins>;
	pinctrl-1 = <&sdhi1_pins_uhs>;
	pinctrl-names = "default", "state_uhs";

	vmmc-supply = <&vcc_sdhi1>;
	vqmmc-supply = <&vccq_sdhi1>;
	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
	sd-uhs-sdr50;
	status = "okay";
};

&ssi1 {
	shared-pin;
};

&usbphy {
	status = "okay";
};


code:
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the iWave-RZ-G1M/N Daughter Board Camera Module
 *
 * Copyright (C) 2017 Renesas Electronics Corp.
 */

/ {
	aliases {
		serial1 = &scif1;
		serial4 = &hscif1;
	};

	cec_clock: cec-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <12000000>;
	};

	hdmi-out {
		compatible = "hdmi-connector";
		type = "a";

		port {
			hdmi_con_out: endpoint {
				remote-endpoint = <&adv7511_out>;
			};
		};
	};
};

&can1 {
	pinctrl-0 = <&can1_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&du {
	pinctrl-0 = <&du_pins>;
	pinctrl-names = "default";

	ports {
		port@0 {
			endpoint {
				remote-endpoint = <&adv7511_in>;
			};
		};
	};
};

&hscif1 {
	pinctrl-0 = <&hscif1_pins>;
	pinctrl-names = "default";

	uart-has-rtscts;
	status = "okay";
};

&i2c5 {
	status = "okay";
	clock-frequency = <400000>;

	hdmi@39 {
		compatible = "adi,adv7511w";
		reg = <0x39>;
		interrupt-parent = <&gpio0>;
		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&cec_clock>;
		clock-names = "cec";

		adi,input-depth = <8>;
		adi,input-colorspace = "rgb";
		adi,input-clock = "1x";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				adv7511_in: endpoint {
					remote-endpoint = <&du_out_rgb>;
				};
			};

			port@1 {
				reg = <1>;
				adv7511_out: endpoint {
					remote-endpoint = <&hdmi_con_out>;
				};
			};
		};
	};
};

&pfc {
	can1_pins: can1 {
		groups = "can1_data_d";
		function = "can1";
	};

	du_pins: du {
		groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
		function = "du";
	};

	hscif1_pins: hscif1 {
		groups = "hscif1_data_c", "hscif1_ctrl_c";
		function = "hscif1";
	};

	scif1_pins: scif1 {
		groups = "scif1_data_d";
		function = "scif1";
	};
};

&scif1 {
	pinctrl-0 = <&scif1_pins>;
	pinctrl-names = "default";

	status = "okay";
};