code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Meson SPI Flash Controller

maintainers:
  - Neil Armstrong <neil.armstrong@linaro.org>

allOf:
  - $ref: "spi-controller.yaml#"

description: |
  The Meson SPIFC is a controller optimized for communication with SPI
  NOR memories, without DMA support and a 64-byte unified transmit /
  receive buffer.

properties:
  compatible:
    enum:
      - amlogic,meson6-spifc # SPI Flash Controller on Meson6 and compatible SoCs
      - amlogic,meson-gxbb-spifc # SPI Flash Controller on GXBB and compatible SoCs

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks

unevaluatedProperties: false

examples:
  - |
    spi@c1108c80 {
          compatible = "amlogic,meson6-spifc";
          reg = <0xc1108c80 0x80>;
          clocks = <&clk81>;
          #address-cells = <1>;
          #size-cells = <0>;

          flash: flash@0 {
              compatible = "spansion,m25p80", "jedec,spi-nor";
              reg = <0>;
              spi-max-frequency = <40000000>;
          };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Aspeed SMC controllers bindings

maintainers:
  - Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
  - Cédric Le Goater <clg@kaod.org>

description: |
  This binding describes the Aspeed Static Memory Controllers (FMC and
  SPI) of the AST2400, AST2500 and AST2600 SOCs.

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    enum:
      - aspeed,ast2600-fmc
      - aspeed,ast2600-spi
      - aspeed,ast2500-fmc
      - aspeed,ast2500-spi
      - aspeed,ast2400-fmc
      - aspeed,ast2400-spi

  reg:
    items:
      - description: registers
      - description: memory mapping

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
    #include <dt-bindings/clock/ast2600-clock.h>

    spi@1e620000 {
        reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "aspeed,ast2600-fmc";
        clocks = <&syscon ASPEED_CLK_AHB>;
        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;

        flash@0 {
                reg = < 0 >;
                compatible = "jedec,spi-nor";
                spi-max-frequency = <50000000>;
                spi-rx-bus-width = <2>;
        };

        flash@1 {
                reg = < 1 >;
                compatible = "jedec,spi-nor";
                spi-max-frequency = <50000000>;
                spi-rx-bus-width = <2>;
        };

        flash@2 {
                reg = < 2 >;
                compatible = "jedec,spi-nor";
                spi-max-frequency = <50000000>;
                spi-rx-bus-width = <2>;
        };
    };

repo_name: angery/linux


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/atmel,at91rm9200-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Atmel SPI device

maintainers:
  - Tudor Ambarus <tudor.ambarus@microchip.com>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    oneOf:
      - const: atmel,at91rm9200-spi
      - items:
          - const: microchip,sam9x60-spi
          - const: atmel,at91rm9200-spi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clock-names:
    contains:
      const: spi_clk

  clocks:
    maxItems: 1

  dmas:
    items:
      - description: TX DMA Channel
      - description: RX DMA Channel

  dma-names:
    items:
      - const: tx
      - const: rx

  atmel,fifo-size:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Maximum number of data the RX and TX FIFOs can store for FIFO
      capable SPI controllers.
    enum: [ 16, 32 ]

required:
  - compatible
  - reg
  - interrupts
  - clock-names
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    spi1: spi@fffcc000 {
        compatible = "atmel,at91rm9200-spi";
        reg = <0xfffcc000 0x4000>;
        interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&spi1_clk>;
        clock-names = "spi_clk";
        cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
        atmel,fifo-size = <32>;

        mmc@0 {
            compatible = "mmc-spi-slot";
            reg = <0>;
            gpios = <&pioC 4 GPIO_ACTIVE_HIGH>;    /* CD */
            spi-max-frequency = <25000000>;
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/atmel,quadspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Atmel Quad Serial Peripheral Interface (QSPI)

maintainers:
  - Tudor Ambarus <tudor.ambarus@microchip.com>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    enum:
      - atmel,sama5d2-qspi
      - microchip,sam9x60-qspi
      - microchip,sama7g5-qspi
      - microchip,sama7g5-ospi

  reg:
    items:
      - description: base registers
      - description: mapped memory

  reg-names:
    items:
      - const: qspi_base
      - const: qspi_mmap

  clocks:
    minItems: 1
    items:
      - description: peripheral clock
      - description: system clock or generic clock, if available

  clock-names:
    minItems: 1
    items:
      - const: pclk
      - enum: [ qspick, gclk ]

  interrupts:
    maxItems: 1

  dmas:
    items:
      - description: tx DMA channel
      - description: rx DMA channel

  dma-names:
    items:
      - const: tx
      - const: rx

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names
  - '#address-cells'
  - '#size-cells'

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/clock/at91.h>
    spi@f0020000 {
        compatible = "atmel,sama5d2-qspi";
        reg = <0xf0020000 0x100>, <0xd0000000 0x8000000>;
        reg-names = "qspi_base", "qspi_mmap";
        interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
        clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
        clock-names = "pclk";
        #address-cells = <1>;
        #size-cells = <0>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_spi0_default>;

        flash@0 {
            compatible = "jedec,spi-nor";
            spi-max-frequency = <50000000>;
            reg = <0>;
            spi-rx-bus-width = <4>;
            spi-tx-bus-width = <4>;
        };
    };


code:
Broadcom BCM2835 auxiliar SPI1/2 controller

The BCM2835 contains two forms of SPI master controller, one known simply as
SPI0, and the other known as the "Universal SPI Master"; part of the
auxiliary block. This binding applies to the SPI1/2 controller.

Required properties:
- compatible: Should be "brcm,bcm2835-aux-spi".
- reg: Should contain register location and length for the spi block
- interrupts: Should contain shared interrupt of the aux block
- clocks: The clock feeding the SPI controller - needs to
	  point to the auxiliar clock driver of the bcm2835,
	  as this clock will enable the output gate for the specific
	  clock.
- cs-gpios: the cs-gpios (native cs is NOT supported)
	    see also spi-bus.txt

Example:

spi1@7e215080 {
	compatible = "brcm,bcm2835-aux-spi";
	reg = <0x7e215080 0x40>;
	interrupts = <1 29>;
	clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI1>;
	#address-cells = <1>;
	#size-cells = <0>;
	cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>;
};

spi2@7e2150c0 {
	compatible = "brcm,bcm2835-aux-spi";
	reg = <0x7e2150c0 0x40>;
	interrupts = <1 29>;
	clocks = <&aux_clocks BCM2835_AUX_CLOCK_SPI2>;
	#address-cells = <1>;
	#size-cells = <0>;
	cs-gpios = <&gpio 43>, <&gpio 44>, <&gpio 45>;
};


code:
Broadcom BCM2835 SPI0 controller

The BCM2835 contains two forms of SPI master controller, one known simply as
SPI0, and the other known as the "Universal SPI Master"; part of the
auxiliary block. This binding applies to the SPI0 controller.

Required properties:
- compatible: Should be one of "brcm,bcm2835-spi" for BCM2835/2836/2837 or
  "brcm,bcm2711-spi" for BCM2711 or "brcm,bcm7211-spi" for BCM7211.
- reg: Should contain register location and length.
- interrupts: Should contain interrupt.
- clocks: The clock feeding the SPI controller.

Example:

spi@20204000 {
	compatible = "brcm,bcm2835-spi";
	reg = <0x7e204000 0x1000>;
	interrupts = <2 22>;
	clocks = <&clk_spi>;
	#address-cells = <1>;
	#size-cells = <0>;
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom SPI controller

maintainers:
  - Kamal Dasu <kdasu.kdev@gmail.com>
  - Rafał Miłecki <rafal@milecki.pl>

description: |
  The Broadcom SPI controller is a SPI master found on various SOCs, including
  BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
  of:
    MSPI : SPI master controller can read and write to a SPI slave device
    BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
           for flash reads and be configured to do single, double, quad lane
           io with 3-byte and 4-byte addressing support.

  Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
  MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance
  of a MSPI master without the BSPI to use with non flash slave devices that
  use SPI protocol.

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    oneOf:
      - description: Second Instance of MSPI BRCMSTB SoCs
        items:
          - enum:
              - brcm,spi-bcm7425-qspi
              - brcm,spi-bcm7429-qspi
              - brcm,spi-bcm7435-qspi
              - brcm,spi-bcm7445-qspi
              - brcm,spi-bcm7216-qspi
              - brcm,spi-bcm7278-qspi
          - const: brcm,spi-bcm-qspi
          - const: brcm,spi-brcmstb-mspi
      - description: Second Instance of MSPI BRCMSTB SoCs
        items:
          - enum:
              - brcm,spi-brcmstb-qspi
              - brcm,spi-brcmstb-mspi
              - brcm,spi-nsp-qspi
              - brcm,spi-ns2-qspi
          - const: brcm,spi-bcm-qspi

  reg:
    minItems: 1
    maxItems: 5

  reg-names:
    minItems: 1
    items:
      - const: mspi
      - const: bspi
      - enum: [ intr_regs, intr_status_reg, cs_reg ]
      - enum: [ intr_regs, intr_status_reg, cs_reg ]
      - enum: [ intr_regs, intr_status_reg, cs_reg ]

  interrupts:
    minItems: 1
    maxItems: 7

  interrupt-names:
    oneOf:
      - minItems: 1
        items:
          - const: mspi_done
          - const: mspi_halted
          - const: spi_lr_fullness_reached
          - const: spi_lr_session_aborted
          - const: spi_lr_impatient
          - const: spi_lr_session_done
          - const: spi_lr_overread
      - const: spi_l1_intr

  clocks:
    maxItems: 1
    description: reference clock for this block

  native-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description: Defined when using BE SoC and device uses BE register read/write

unevaluatedProperties: false

required:
  - reg
  - reg-names
  - interrupts
  - interrupt-names

examples:
  - | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access
    spi@f03e3400 {
            compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
            reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
            reg-names = "mspi", "bspi", "cs_reg";
            interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
            interrupt-parent = <&gic>;
            interrupt-names = "mspi_done",
                              "mspi_halted",
                              "spi_lr_fullness_reached",
                              "spi_lr_session_aborted",
                              "spi_lr_impatient",
                              "spi_lr_session_done",
                              "spi_lr_overread";
            clocks = <&hif_spi>;
            #address-cells = <0x1>;
            #size-cells = <0x0>;

            flash@0 {
                    #size-cells = <0x2>;
                    #address-cells = <0x2>;
                    compatible = "m25p80";
                    reg = <0x0>;
                    spi-max-frequency = <0x2625a00>;
                    spi-cpol;
                    spi-cpha;
            };
    };
  - | # BRCMSTB SoC: MSPI master for any SPI device
    spi@f0416000 {
            clocks = <&upg_fixed>;
            compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
            reg = <0xf0416000 0x180>;
            reg-names = "mspi";
            interrupts = <0x14>;
            interrupt-parent = <&irq0_aon_intc>;
            interrupt-names = "mspi_done";
            #address-cells = <1>;
            #size-cells = <0>;
    };
  - | # iProc SoC
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    spi@18027200 {
            compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
            reg = <0x18027200 0x184>,
                  <0x18027000 0x124>,
                  <0x1811c408 0x004>,
                  <0x180273a0 0x01c>;
            reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
            interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "mspi_done",
                              "mspi_halted",
                              "spi_lr_fullness_reached",
                              "spi_lr_session_aborted",
                              "spi_lr_impatient",
                              "spi_lr_session_done";
            clocks = <&iprocmed>;
            num-cs = <2>;
            #address-cells = <1>;
            #size-cells = <0>;
    };
  - | # NS2 SoC
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    spi@66470200 {
            compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
            reg = <0x66470200 0x184>,
                  <0x66470000 0x124>,
                  <0x67017408 0x004>,
                  <0x664703a0 0x01c>;
            reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
            interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "spi_l1_intr";
            clocks = <&iprocmed>;
            num-cs = <2>;
            #address-cells = <1>;
            #size-cells = <0>;

            flash@0 {
                    #address-cells = <1>;
                    #size-cells = <1>;
                    compatible = "m25p80";
                    reg = <0x0>;
                    spi-max-frequency = <12500000>;
                    spi-cpol;
                    spi-cpha;
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Peripheral-specific properties for the Cadence QSPI controller.

description:
  See spi-peripheral-props.yaml for more info.

maintainers:
  - Vaishnav Achath <vaishnav.a@ti.com>

properties:
  # cdns,qspi-nor.yaml
  cdns,read-delay:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Delay for read capture logic, in clock cycles.

  cdns,tshsl-ns:
    description:
      Delay in nanoseconds for the length that the master mode chip select
      outputs are de-asserted between transactions.

  cdns,tsd2d-ns:
    description:
      Delay in nanoseconds between one chip select being de-activated
      and the activation of another.

  cdns,tchsh-ns:
    description:
      Delay in nanoseconds between last bit of current transaction and
      deasserting the device chip select (qspi_n_ss_out).

  cdns,tslch-ns:
    description:
      Delay in nanoseconds between setting qspi_n_ss_out low and
      first bit transfer.

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence Quad SPI controller

maintainers:
  - Vaishnav Achath <vaishnav.a@ti.com>

allOf:
  - $ref: spi-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: xlnx,versal-ospi-1.0
    then:
      required:
        - power-domains

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - ti,k2g-qspi
              - ti,am654-ospi
              - intel,lgm-qspi
              - xlnx,versal-ospi-1.0
              - intel,socfpga-qspi
          - const: cdns,qspi-nor
      - const: cdns,qspi-nor

  reg:
    items:
      - description: the controller register set
      - description: the controller data area

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  cdns,fifo-depth:
    description:
      Size of the data FIFO in words.
    $ref: "/schemas/types.yaml#/definitions/uint32"
    enum: [ 128, 256 ]
    default: 128

  cdns,fifo-width:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Bus width of the data FIFO in bytes.
    default: 4

  cdns,trigger-address:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      32-bit indirect AHB trigger address.

  cdns,is-decoded-cs:
    type: boolean
    description:
      Flag to indicate whether decoder is used to select different chip select
      for different memory regions.

  cdns,rclk-en:
    type: boolean
    description:
      Flag to indicate that QSPI return clock is used to latch the read
      data rather than the QSPI clock. Make sure that QSPI return clock
      is populated on the board before using this property.

  power-domains:
    maxItems: 1

  resets:
    maxItems: 2

  reset-names:
    minItems: 1
    maxItems: 2
    items:
      enum: [ qspi, qspi-ocp ]

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - cdns,fifo-depth
  - cdns,fifo-width
  - cdns,trigger-address
  - '#address-cells'
  - '#size-cells'

unevaluatedProperties: false

examples:
  - |
    qspi: spi@ff705000 {
      compatible = "cdns,qspi-nor";
      #address-cells = <1>;
      #size-cells = <0>;
      reg = <0xff705000 0x1000>,
            <0xffa00000 0x1000>;
      interrupts = <0 151 4>;
      clocks = <&qspi_clk>;
      cdns,fifo-depth = <128>;
      cdns,fifo-width = <4>;
      cdns,trigger-address = <0x00000000>;
      resets = <&rst 0x1>, <&rst 0x2>;
      reset-names = "qspi", "qspi-ocp";

      flash@0 {
              compatible = "jedec,spi-nor";
              reg = <0x0>;
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020-21 Cadence
%YAML 1.2
---
$id: "http://devicetree.org/schemas/spi/cdns,xspi.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence XSPI Controller

maintainers:
  - Parshuram Thombare <pthombar@cadence.com>

description: |
  The XSPI controller allows SPI protocol communication in
  single, dual, quad or octal wire transmission modes for
  read/write access to slaves such as SPI-NOR flash.

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    const: cdns,xspi-nor

  reg:
    items:
      - description: address and length of the controller register set
      - description: address and length of the Slave DMA data port
      - description: address and length of the auxiliary registers

  reg-names:
    items:
      - const: io
      - const: sdma
      - const: aux

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        xspi: spi@a0010000 {
            #address-cells = <1>;
            #size-cells = <0>;
            compatible = "cdns,xspi-nor";
            reg = <0x0 0xa0010000 0x0 0x1040>,
                  <0x0 0xb0000000 0x0 0x1000>,
                  <0x0 0xa0020000 0x0 0x100>;
            reg-names = "io", "sdma", "aux";
            interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-parent = <&gic>;

            flash@0 {
                compatible = "jedec,spi-nor";
                spi-max-frequency = <75000000>;
                reg = <0>;
            };

            flash@1 {
                compatible = "jedec,spi-nor";
                spi-max-frequency = <75000000>;
                reg = <1>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Quad Serial Peripheral Interface (QuadSPI)

maintainers:
  - Han Xu <han.xu@nxp.com>

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,vf610-qspi
          - fsl,imx6sx-qspi
          - fsl,imx7d-qspi
          - fsl,imx6ul-qspi
          - fsl,ls1021a-qspi
          - fsl,ls2080a-qspi
      - items:
          - enum:
              - fsl,ls1043a-qspi
          - const: fsl,ls1021a-qspi
      - items:
          - enum:
              - fsl,imx8mq-qspi
          - const: fsl,imx7d-qspi

  reg:
    items:
      - description: registers
      - description: memory mapping

  reg-names:
    items:
      - const: QuadSPI
      - const: QuadSPI-memory

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: SoC SPI qspi_en clock
      - description: SoC SPI qspi clock

  clock-names:
    items:
      - const: qspi_en
      - const: qspi

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/fsl,qoriq-clockgen.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        spi@1550000 {
            compatible = "fsl,ls1021a-qspi";
            reg = <0x0 0x1550000 0x0 0x100000>,
                  <0x0 0x40000000 0x0 0x10000000>;
            reg-names = "QuadSPI", "QuadSPI-memory";
            interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
            #address-cells = <1>;
            #size-cells = <0>;
            clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>,
                     <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>;
            clock-names = "qspi_en", "qspi";

            flash@0 {
                compatible = "jedec,spi-nor";
                spi-max-frequency = <50000000>;
                reg = <0>;
                spi-rx-bus-width = <4>;
                spi-tx-bus-width = <4>;
            };
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/fsl-imx-cspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX

maintainers:
  - Shawn Guo <shawnguo@kernel.org>

allOf:
  - $ref: "/schemas/spi/spi-controller.yaml#"

properties:
  compatible:
    oneOf:
      - const: fsl,imx1-cspi
      - const: fsl,imx21-cspi
      - const: fsl,imx27-cspi
      - const: fsl,imx31-cspi
      - const: fsl,imx35-cspi
      - const: fsl,imx51-ecspi
      - const: fsl,imx53-ecspi
      - items:
          - const: fsl,imx8mp-ecspi
          - const: fsl,imx6ul-ecspi
      - items:
          - enum:
              - fsl,imx50-ecspi
              - fsl,imx6q-ecspi
              - fsl,imx6sx-ecspi
              - fsl,imx6sl-ecspi
              - fsl,imx6sll-ecspi
              - fsl,imx6ul-ecspi
              - fsl,imx7d-ecspi
              - fsl,imx8mq-ecspi
              - fsl,imx8mm-ecspi
              - fsl,imx8mn-ecspi
          - const: fsl,imx51-ecspi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: SoC SPI ipg clock
      - description: SoC SPI per clock

  clock-names:
    items:
      - const: ipg
      - const: per

  dmas:
    items:
      - description: DMA controller phandle and request line for RX
      - description: DMA controller phandle and request line for TX

  dma-names:
    items:
      - const: rx
      - const: tx

  fsl,spi-rdy-drctl:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: |
      Integer, representing the value of DRCTL, the register controlling
      the SPI_READY handling. Note that to enable the DRCTL consideration,
      the SPI_READY mode-flag needs to be set too.
      Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst).
    enum: [0, 1, 2]

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx5-clock.h>

    spi@70010000 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "fsl,imx51-ecspi";
        reg = <0x70010000 0x4000>;
        interrupts = <36>;
        clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
                 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
        clock-names = "ipg", "per";
    };


code:
* SPI (Serial Peripheral Interface)

Required properties:
- cell-index : QE SPI subblock index.
		0: QE subblock SPI1
		1: QE subblock SPI2
- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
- reg : Offset and length of the register set for the device
- interrupts : <a b> where a is the interrupt number and b is a
  field that represents an encoding of the sense and level
  information for the interrupt.  This should be encoded based on
  the information in section 2) depending on the type of interrupt
  controller you have.
- clock-frequency : input clock frequency to non FSL_SOC cores

Optional properties:
- cs-gpios : specifies the gpio pins to be used for chipselects.
  The gpios will be referred to as reg = <index> in the SPI child nodes.
  If unspecified, a single SPI device without a chip select can be used.
- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
  SPISEL_BOOT signal is used as chip select for a slave device. Use
  reg = <number of gpios> in the corresponding child node, i.e. 0 if
  the cs-gpios property is not present.

Example:
	spi@4c0 {
		cell-index = <0>;
		compatible = "fsl,spi";
		reg = <4c0 40>;
		interrupts = <82 0>;
		interrupt-parent = <700>;
		mode = "cpu";
		cs-gpios = <&gpio 18 1		// device reg=<0>
			    &gpio 19 1>;	// device reg=<1>
	};

* eSPI (Enhanced Serial Peripheral Interface)

Required properties:
- compatible : should be "fsl,mpc8536-espi".
- reg : Offset and length of the register set for the device.
- interrupts : should contain eSPI interrupt, the device has one interrupt.
- fsl,espi-num-chipselects : the number of the chipselect signals.

Optional properties:
- fsl,csbef: chip select assertion time in bits before frame starts
- fsl,csaft: chip select negation time in bits after frame ends

Example:
	spi@110000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,mpc8536-espi";
		reg = <0x110000 0x1000>;
		interrupts = <53 0x2>;
		interrupt-parent = <&mpic>;
		fsl,espi-num-chipselects = <4>;
		fsl,csbef = <1>;
		fsl,csaft = <1>;
	};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/hpe,gxp-spifi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: HPE GXP spi controller flash interface

maintainers:
  - Nick Hawkins <nick.hawkins@hpe.com>
  - Jean-Marie Verdun <verdun@hpe.com>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    const: hpe,gxp-spifi

  reg:
    items:
      - description: cfg registers
      - description: data registers
      - description: mapped memory

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

examples:
  - |

    spi@200 {
      compatible = "hpe,gxp-spifi";
      reg = <0x200 0x80>, <0xc000 0x100>, <0x38000000 0x800000>;
      interrupts = <20>;
      interrupt-parent = <&vic0>;
      #address-cells = <1>;
      #size-cells = <0>;

      flash@0 {
        reg = <0>;
        compatible = "jedec,spi-nor";
      };

      flash@1 {
        reg = <1>;
        compatible = "jedec,spi-nor";
      };
    };


code:
* ICP DAS LP-8841 SPI Controller for RTC

ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
memory register, which acts as an SPI master device.

The device uses the standard MicroWire half-duplex transfer timing.
Master output is set on low clock and sensed by the RTC on the rising
edge. Master input is set by the RTC on the trailing edge and is sensed
by the master on low clock.

Required properties:

- #address-cells: should be 1

- #size-cells: should be 0

- compatible: should be "icpdas,lp8841-spi-rtc"

- reg: should provide IO memory address

Requirements to SPI slave nodes:

- There can be only one slave device.

- The spi slave node should claim the following flags which are
  required by the spi controller.

  - spi-3wire: The master itself has only 3 wire. It cannor work in
    full duplex mode.

  - spi-cs-high: DS-1302 has active high chip select line. The master
    doesn't support active low.

  - spi-lsb-first: DS-1302 requires least significant bit first
    transfers. The master only support this type of bit ordering.

Example:

spi@901c {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "icpdas,lp8841-spi-rtc";
	reg = <0x901c 0x1>;

	rtc@0 {
		compatible = "maxim,ds1302";
		reg = <0>;
		spi-max-frequency = <500000>;
		spi-3wire;
		spi-lsb-first;
		spi-cs-high;
	};
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/ingenic,spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Ingenic SoCs SPI controller devicetree bindings

maintainers:
  - Artur Rojek <contact@artur-rojek.eu>
  - Paul Cercueil <paul@crapouillou.net>

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - ingenic,jz4750-spi
          - ingenic,jz4775-spi
          - ingenic,jz4780-spi
          - ingenic,x1000-spi
          - ingenic,x2000-spi
      - items:
          - enum:
              - ingenic,jz4760-spi
              - ingenic,jz4770-spi
          - const: ingenic,jz4750-spi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  dmas:
    maxItems: 2
    minItems: 2

  dma-names:
    items:
      - const: rx
      - const: tx

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - dmas
  - dma-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
    spi@10043000 {
      compatible = "ingenic,jz4770-spi", "ingenic,jz4750-spi";
      reg = <0x10043000 0x1c>;
      #address-cells = <1>;
      #size-cells = <0>;

      interrupt-parent = <&intc>;
      interrupts = <8>;

      clocks = <&cgu JZ4770_CLK_SSI0>;

      dmas = <&dmac1 23 0xffffffff>, <&dmac1 22 0xffffffff>;
      dma-names = "rx", "tx";
    };


code:
J-Core SPI master

Required properties:

- compatible: Must be "jcore,spi2".

- reg: Memory region for registers.

- #address-cells: Must be 1.

- #size-cells: Must be 0.

Optional properties:

- clocks: If a phandle named "ref_clk" is present, SPI clock speed
  programming is relative to the frequency of the indicated clock.
  Necessary only if the input clock rate is something other than a
  fixed 50 MHz.

- clock-names: Clock names, one for each phandle in clocks.

See spi-bus.txt for additional properties not specific to this device.

Example:

spi@40 {
	compatible = "jcore,spi2";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x40 0x8>;
	spi-max-frequency = <25000000>;
	clocks = <&bus_clk>;
	clock-names = "ref_clk";
}


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2019,2020 Lubomir Rintel <lkundrak@v3.sk>
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/marvell,mmp2-ssp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PXA2xx SSP SPI Controller bindings

maintainers:
  - Lubomir Rintel <lkundrak@v3.sk>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    const: marvell,mmp2-ssp

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  ready-gpios:
    description: |
      GPIO used to signal a SPI master that the FIFO is filled and we're
      ready to service a transfer. Only useful in slave mode.
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

dependencies:
  ready-gpios: [ spi-slave ]

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/marvell,mmp2.h>
    spi@d4035000 {
        compatible = "marvell,mmp2-ssp";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0xd4035000 0x1000>;
        clocks = <&soc_clocks MMP2_CLK_SSP0>;
        interrupts = <0>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SPI Bus controller for MediaTek ARM SoCs

maintainers:
  - Leilk Liu <leilk.liu@mediatek.com>

allOf:
  - $ref: "/schemas/spi/spi-controller.yaml#"

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt7629-spi
              - mediatek,mt8365-spi
          - const: mediatek,mt7622-spi
      - items:
          - enum:
              - mediatek,mt8516-spi
          - const: mediatek,mt2712-spi
      - items:
          - enum:
              - mediatek,mt6779-spi
              - mediatek,mt8186-spi
              - mediatek,mt8192-spi
              - mediatek,mt8195-spi
          - const: mediatek,mt6765-spi
      - items:
          - enum:
              - mediatek,mt7986-spi-ipm
              - mediatek,mt8188-spi-ipm
          - const: mediatek,spi-ipm
      - items:
          - enum:
              - mediatek,mt2701-spi
              - mediatek,mt2712-spi
              - mediatek,mt6589-spi
              - mediatek,mt6765-spi
              - mediatek,mt6893-spi
              - mediatek,mt7622-spi
              - mediatek,mt8135-spi
              - mediatek,mt8173-spi
              - mediatek,mt8183-spi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    items:
      - description: clock used for the parent clock
      - description: clock used for the muxes clock
      - description: clock used for the clock gate
      - description: clock used for the AHB bus, this clock is optional

  clock-names:
    minItems: 3
    items:
      - const: parent-clk
      - const: sel-clk
      - const: spi-clk
      - const: hclk

  mediatek,pad-select:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 4
    items:
      enum: [0, 1, 2, 3]
    description:
      specify which pins group(ck/mi/mo/cs) spi controller used.
      This is an array.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - '#address-cells'
  - '#size-cells'

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    spi@1100a000 {
      compatible = "mediatek,mt8173-spi";
      #address-cells = <1>;
      #size-cells = <0>;
      reg = <0x1100a000 0x1000>;
      interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
      clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
               <&topckgen CLK_TOP_SPI_SEL>,
               <&pericfg CLK_PERI_SPI0>;
      clock-names = "parent-clk", "sel-clk", "spi-clk";
      cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
      mediatek,pad-select = <1>, <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Serial NOR flash controller for MediaTek ARM SoCs

maintainers:
  - Bayi Cheng <bayi.cheng@mediatek.com>
  - Chuanhong Guo <gch981213@gmail.com>

description: |
  This spi controller support single, dual, or quad mode transfer for
  SPI NOR flash. There should be only one spi slave device following
  generic spi bindings. It's not recommended to use this controller
  for devices other than SPI NOR flash due to limited transfer
  capability of this controller.

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt8173-nor
          - mediatek,mt8186-nor
          - mediatek,mt8192-nor
      - items:
          - enum:
              - mediatek,mt2701-nor
              - mediatek,mt2712-nor
              - mediatek,mt7622-nor
              - mediatek,mt7623-nor
              - mediatek,mt7629-nor
              - mediatek,mt8195-nor
          - const: mediatek,mt8173-nor
      - items:
          - enum:
              - mediatek,mt8188-nor
          - const: mediatek,mt8186-nor

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2
    items:
      - description: clock used for spi bus
      - description: clock used for controller
      - description: clock used for nor dma bus. this depends on hardware
                     design, so this is optional.
      - description: clock used for controller axi slave bus.
                     this depends on hardware design, so it is optional.

  clock-names:
    minItems: 2
    items:
      - const: spi
      - const: sf
      - const: axi
      - const: axi_s

required:
  - compatible
  - reg
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      nor_flash: spi@1100d000 {
        compatible = "mediatek,mt8173-nor";
        reg = <0 0x1100d000 0 0xe0>;
        interrupts = <1>;
        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
                 <&pericfg CLK_PERI_NFI>;
        clock-names = "spi", "sf", "axi";
        #address-cells = <1>;
        #size-cells = <0>;

        flash@0 {
          compatible = "jedec,spi-nor";
          reg = <0>;
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SPI-NAND flash controller for MediaTek ARM SoCs

maintainers:
  - Chuanhong Guo <gch981213@gmail.com>

description: |
  The Mediatek SPI-NAND flash controller is an extended version of
  the Mediatek NAND flash controller. It can perform standard SPI
  instructions with one continuous write and one read for up-to 0xa0
  bytes. It also supports typical SPI-NAND page cache operations
  in single, dual or quad IO mode with pipelined ECC encoding/decoding
  using the accompanying ECC engine. There should be only one spi
  slave device following generic spi bindings.

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

properties:
  compatible:
    enum:
      - mediatek,mt7622-snand
      - mediatek,mt7629-snand

  reg:
    items:
      - description: core registers

  interrupts:
    items:
      - description: NFI interrupt

  clocks:
    items:
      - description: clock used for the controller
      - description: clock used for the SPI bus

  clock-names:
    items:
      - const: nfi_clk
      - const: pad_clk

  nand-ecc-engine:
    description: device-tree node of the accompanying ECC engine.
    $ref: /schemas/types.yaml#/definitions/phandle

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - nand-ecc-engine

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt7622-clk.h>
    soc {
      #address-cells = <2>;
      #size-cells = <2>;
      snfi: spi@1100d000 {
        compatible = "mediatek,mt7622-snand";
        reg = <0 0x1100d000 0 0x1000>;
        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
        clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
        clock-names = "nfi_clk", "pad_clk";
        nand-ecc-engine = <&bch>;
        #address-cells = <1>;
        #size-cells = <0>;

        flash@0 {
          compatible = "spi-nand";
          reg = <0>;
          spi-tx-bus-width = <4>;
          spi-rx-bus-width = <4>;
          nand-ecc-engine = <&snfi>;
        };
      };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/mediatek,spi-slave-mt27xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SPI Slave controller for MediaTek ARM SoCs

maintainers:
  - Leilk Liu <leilk.liu@mediatek.com>

allOf:
  - $ref: "/schemas/spi/spi-controller.yaml#"

properties:
  compatible:
    enum:
      - mediatek,mt2712-spi-slave
      - mediatek,mt8195-spi-slave

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: spi

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt2712-clk.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    spi@10013000 {
      compatible = "mediatek,mt2712-spi-slave";
      reg = <0x10013000 0x100>;
      interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
      clocks = <&infracfg CLK_INFRA_AO_SPI1>;
      clock-names = "spi";
      assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
      assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip FPGA {Q,}SPI Controllers

description:
  SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
  fabric IP cores they are based on

maintainers:
  - Conor Dooley <conor.dooley@microchip.com>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - const: microchip,mpfs-qspi
          - const: microchip,coreqspi-rtl-v2
      - const: microchip,coreqspi-rtl-v2 #FPGA QSPI
      - const: microchip,mpfs-spi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clock-names:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include "dt-bindings/clock/microchip,mpfs-clock.h"
    spi@20108000 {
        compatible = "microchip,mpfs-spi";
        reg = <0x20108000 0x1000>;
        clocks = <&clkcfg CLK_SPI0>;
        interrupt-parent = <&plic>;
        interrupts = <54>;
    };
...


code:
Microchip PIC32 SPI Master controller

Required properties:
- compatible: Should be "microchip,pic32mzda-spi".
- reg: Address and length of register space for the device.
- interrupts: Should contain all three spi interrupts in sequence
              of <fault-irq>, <receive-irq>, <transmit-irq>.
- interrupt-names: Should be "fault", "rx", "tx" in order.
- clocks: Phandle of the clock generating SPI clock on the bus.
- clock-names: Should be "mck0".
- cs-gpios: Specifies the gpio pins to be used for chipselects.
            See: Documentation/devicetree/bindings/spi/spi-bus.txt

Optional properties:
- dmas: Two or more DMA channel specifiers following the convention outlined
        in Documentation/devicetree/bindings/dma/dma.txt
- dma-names: Names for the dma channels. There must be at least one channel
             named "spi-tx" for transmit and named "spi-rx" for receive.

Example:

spi1: spi@1f821000 {
        compatible = "microchip,pic32mzda-spi";
        reg = <0x1f821000 0x200>;
        interrupts = <109 IRQ_TYPE_LEVEL_HIGH>,
                     <110 IRQ_TYPE_LEVEL_HIGH>,
                     <111 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "fault", "rx", "tx";
        clocks = <&PBCLK2>;
        clock-names = "mck0";
        cs-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
        dmas = <&dma 134>, <&dma 135>;
        dma-names = "spi-rx", "spi-tx";
};


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/mikrotik,rb4xx-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MikroTik RB4xx series SPI master

maintainers:
  - Gabor Juhos <juhosg@openwrt.org>
  - Bert Vermeulen <bert@biot.com>

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    const: mikrotik,rb4xx-spi

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    spi: spi@1f000000 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "mikrotik,rb4xx-spi";
        reg = <0x1f000000 0x10>;
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/mxicy,mx25f0a-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Macronix SPI controller

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    const: mxicy,mx25f0a-spi

  reg:
    minItems: 2
    maxItems: 2

  reg-names:
    items:
      - const: regs
      - const: dirmap

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    maxItems: 3

  clock-names:
    items:
      - const: send_clk
      - const: send_dly_clk
      - const: ps_clk

  nand-ecc-engine:
    description: NAND ECC engine used by the SPI controller in order to perform
      on-the-fly correction when using a SPI-NAND memory.
    $ref: /schemas/types.yaml#/definitions/phandle

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    spi@43c30000 {
      compatible = "mxicy,mx25f0a-spi";
      reg = <0x43c30000 0x10000>, <0xa0000000 0x20000000>;
      reg-names = "regs", "dirmap";
      clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 18>;
      clock-names = "send_clk", "send_dly_clk", "ps_clk";
      #address-cells = <1>;
      #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/mxs-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale MX233/MX28 SSP/SPI

maintainers:
  - Marek Vasut <marex@denx.de>

allOf:
  - $ref: "/schemas/spi/spi-controller.yaml#"

properties:
  compatible:
    enum:
      - fsl,imx23-spi
      - fsl,imx28-spi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  dmas:
    maxItems: 1

  dma-names:
    const: rx-tx

  clock-frequency:
    description: input clock frequency to the SPI block in Hz.
    default: 160000000

required:
  - compatible
  - reg
  - interrupts
  - dmas
  - dma-names

unevaluatedProperties: false

examples:
  - |
    spi@80010000 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "fsl,imx28-spi";
        reg = <0x80010000 0x2000>;
        interrupts = <96>;
        dmas = <&dma_apbh 0>;
        dma-names = "rx-tx";
    };


code:
* Nuvoton FLASH Interface Unit (FIU) SPI Controller

NPCM FIU supports single, dual and quad communication interface.

The NPCM7XX supports three FIU modules,
FIU0 and FIUx supports two chip selects,
FIU3 support four chip select.

The NPCM8XX supports four FIU modules,
FIU0 and FIUx supports two chip selects,
FIU1 and FIU3 supports four chip selects.

Required properties:
  - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC
			     "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC
  - #address-cells : should be 1.
  - #size-cells : should be 0.
  - reg : the first contains the register location and length,
          the second contains the memory mapping address and length
  - reg-names: Should contain the reg names "control" and "memory"
  - clocks : phandle of FIU reference clock.

Required properties in case the pins can be muxed:
  - pinctrl-names : a pinctrl state named "default" must be defined.
  - pinctrl-0 : phandle referencing pin configuration of the device.

Optional property:
  - nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.

Aliases:
- All the FIU controller nodes should be represented in the aliases node using
  the following format 'fiu{n}' where n is a unique number for the alias.
  In the NPCM7XX BMC:
  		fiu0 represent fiu 0 controller
  		fiu1 represent fiu 3 controller
  		fiu2 represent fiu x controller

  In the NPCM8XX BMC:
  		fiu0 represent fiu 0 controller
  		fiu1 represent fiu 1 controller
  		fiu2 represent fiu 3 controller
  		fiu3 represent fiu x controller

Example:
fiu3: spi@c00000000 {
	compatible = "nuvoton,npcm750-fiu";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
	reg-names = "control", "memory";
	clocks = <&clk NPCM7XX_CLK_AHB>;
	pinctrl-names = "default";
	pinctrl-0 = <&spi3_pins>;
	flash@0 {
			...
	};
};


code:
Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver

Nuvoton NPCM7xx SOC support two PSPI channels.

Required properties:
 - compatible : "nuvoton,npcm750-pspi" for Poleg NPCM7XX.
				"nuvoton,npcm845-pspi" for Arbel NPCM8XX.
 - #address-cells : should be 1. see spi-bus.txt
 - #size-cells : should be 0. see spi-bus.txt
 - specifies physical base address and size of the register.
 - interrupts : contain PSPI interrupt.
 - clocks : phandle of PSPI reference clock.
 - clock-names: Should be "clk_apb5".
 - pinctrl-names : a pinctrl state named "default" must be defined.
 - pinctrl-0 : phandle referencing pin configuration of the device.
 - resets : phandle to the reset control for this device.
 - cs-gpios: Specifies the gpio pins to be used for chipselects.
            See: Documentation/devicetree/bindings/spi/spi-bus.txt

Optional properties:
- clock-frequency : Input clock frequency to the PSPI block in Hz.
		    Default is 25000000 Hz.

spi0: spi@f0200000 {
	compatible = "nuvoton,npcm750-pspi";
	reg = <0xf0200000 0x1000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pspi1_pins>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clk NPCM7XX_CLK_APB5>;
	clock-names = "clk_apb5";
	resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>
	cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
};


code:
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/nuvoton,wpcm450-fiu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Nuvoton WPCM450 Flash Interface Unit (FIU)

maintainers:
  - Jonathan Neuschäfer <j.neuschaefer@gmx.net>

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

properties:
  compatible:
    const: nuvoton,wpcm450-fiu

  reg:
    items:
      - description: FIU registers
      - description: Memory-mapped flash contents

  reg-names:
    items:
      - const: control
      - const: memory

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  nuvoton,shm:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: a phandle to the SHM block (see ../arm/nuvoton,shm.yaml)

required:
  - compatible
  - reg
  - clocks

unevaluatedProperties: false

examples:
  - |
    spi@c8000000 {
      compatible = "nuvoton,wpcm450-fiu";
      reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>;
      #address-cells = <1>;
      #size-cells = <0>;
      reg-names = "control", "memory";
      clocks = <&clk 0>;
      nuvoton,shm = <&shm>;

      flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0>;
      };
    };

    shm: syscon@c8001000 {
      compatible = "nuvoton,wpcm450-shm", "syscon";
      reg = <0xc8001000 0x1000>;
    };


code:
NVIDIA Tegra114 SPI controller.

Required properties:
- compatible : For Tegra114, must contain "nvidia,tegra114-spi".
  Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
  <chip> is tegra124, tegra132, or tegra210.
- reg: Should contain SPI registers location and length.
- interrupts: Should contain SPI interrupts.
- clock-names : Must include the following entries:
  - spi
- resets : Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
  - spi
- dmas : Must contain an entry for each entry in clock-names.
  See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
  - rx
  - tx
- clocks : Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.

Recommended properties:
- spi-max-frequency: Definition as per
                     Documentation/devicetree/bindings/spi/spi-bus.txt
Optional properties:
- nvidia,tx-clk-tap-delay: Delays the clock going out to the external device
  with this tap value. This property is used to tune the outgoing data from
  Tegra SPI master with respect to outgoing Tegra SPI master clock.
  Tap values vary based on the platform design trace lengths from Tegra SPI
  to corresponding slave devices. Valid tap values are from 0 thru 63.
- nvidia,rx-clk-tap-delay: Delays the clock coming in from the external device
  with this tap value. This property is used to adjust the Tegra SPI master
  clock with respect to the data from the SPI slave device.
  Tap values vary based on the platform design trace lengths from Tegra SPI
  to corresponding slave devices. Valid tap values are from 0 thru 63.

Example:

spi@7000d600 {
	compatible = "nvidia,tegra114-spi";
	reg = <0x7000d600 0x200>;
	interrupts = <0 82 0x04>;
	spi-max-frequency = <25000000>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car 44>;
	clock-names = "spi";
	resets = <&tegra_car 44>;
	reset-names = "spi";
	dmas = <&apbdma 16>, <&apbdma 16>;
	dma-names = "rx", "tx";
	<spi-client>@<bus_num> {
		...
		...
		nvidia,rx-clk-tap-delay = <0>;
		nvidia,tx-clk-tap-delay = <16>;
		...
	};

};


code:
NVIDIA Tegra20 SFLASH controller.

Required properties:
- compatible : should be "nvidia,tegra20-sflash".
- reg: Should contain SFLASH registers location and length.
- interrupts: Should contain SFLASH interrupts.
- clocks : Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
  - spi
- dmas : Must contain an entry for each entry in clock-names.
  See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
  - rx
  - tx

Recommended properties:
- spi-max-frequency: Definition as per
                     Documentation/devicetree/bindings/spi/spi-bus.txt

Example:

spi@7000c380 {
	compatible = "nvidia,tegra20-sflash";
	reg = <0x7000c380 0x80>;
	interrupts = <0 39 0x04>;
	spi-max-frequency = <25000000>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car 43>;
	resets = <&tegra_car 43>;
	reset-names = "spi";
	dmas = <&apbdma 11>, <&apbdma 11>;
	dma-names = "rx", "tx";
};


code:
NVIDIA Tegra20/Tegra30 SLINK controller.

Required properties:
- compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink".
- reg: Should contain SLINK registers location and length.
- interrupts: Should contain SLINK interrupts.
- clocks : Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.
- resets : Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
  - spi
- dmas : Must contain an entry for each entry in clock-names.
  See ../dma/dma.txt for details.
- dma-names : Must include the following entries:
  - rx
  - tx

Recommended properties:
- spi-max-frequency: Definition as per
                     Documentation/devicetree/bindings/spi/spi-bus.txt

Example:

spi@7000d600 {
	compatible = "nvidia,tegra20-slink";
	reg = <0x7000d600 0x200>;
	interrupts = <0 82 0x04>;
	spi-max-frequency = <25000000>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&tegra_car 44>;
	resets = <&tegra_car 44>;
	reset-names = "spi";
	dmas = <&apbdma 16>, <&apbdma 16>;
	dma-names = "rx", "tx";
};


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Peripheral properties for Tegra Quad SPI Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jonathan Hunter <jonathanh@nvidia.com>

properties:
  nvidia,tx-clk-tap-delay:
    description:
      Delays the clock going out to device with this tap value.
      Tap value varies based on platform design trace lengths from Tegra
      QSPI to corresponding slave device.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 31

  nvidia,rx-clk-tap-delay:
    description:
      Delays the clock coming in from the device with this tap value.
      Tap value varies based on platform design trace lengths from Tegra
      QSPI to corresponding slave device.
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 255

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Tegra Quad SPI Controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jonathan Hunter <jonathanh@nvidia.com>

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    enum:
      - nvidia,tegra210-qspi
      - nvidia,tegra186-qspi
      - nvidia,tegra194-qspi
      - nvidia,tegra234-qspi
      - nvidia,tegra241-qspi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clock-names:
    items:
      - const: qspi
      - const: qspi_out

  clocks:
    maxItems: 2

  resets:
    maxItems: 1

  dmas:
    maxItems: 2

  dma-names:
    items:
      - const: rx
      - const: tx

patternProperties:
  "@[0-9a-f]+$":
    type: object

    properties:
      spi-rx-bus-width:
        enum: [1, 2, 4]

      spi-tx-bus-width:
        enum: [1, 2, 4]

required:
  - compatible
  - reg
  - interrupts
  - clock-names
  - clocks
  - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/tegra210-car.h>
    #include <dt-bindings/reset/tegra210-car.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    spi@70410000 {
            compatible = "nvidia,tegra210-qspi";
            reg = <0x70410000 0x1000>;
            interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
            #address-cells = <1>;
            #size-cells = <0>;
            clocks = <&tegra_car TEGRA210_CLK_QSPI>,
                     <&tegra_car TEGRA210_CLK_QSPI_PM>;
            clock-names = "qspi", "qspi_out";
            resets = <&tegra_car 211>;
            dmas = <&apbdma 5>, <&apbdma 5>;
            dma-names = "rx", "tx";

            flash@0 {
                    compatible = "jedec,spi-nor";
                    reg = <0>;
                    spi-max-frequency = <104000000>;
                    spi-tx-bus-width = <2>;
                    spi-rx-bus-width = <2>;
                    nvidia,tx-clk-tap-delay = <0>;
                    nvidia,rx-clk-tap-delay = <0>;
            };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/omap-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SPI controller bindings for OMAP and K3 SoCs

maintainers:
  - Aswath Govindraju <a-govindraju@ti.com>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - ti,am654-mcspi
              - ti,am4372-mcspi
          - const: ti,omap4-mcspi
      - items:
          - enum:
              - ti,omap2-mcspi
              - ti,omap4-mcspi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  ti,spi-num-cs:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Number of chipselect supported  by the instance.
    minimum: 1
    maximum: 4

  ti,hwmods:
    $ref: /schemas/types.yaml#/definitions/string
    description:
      Must be "mcspi<n>", n being the instance number (1-based).
      This property is applicable only on legacy platforms mainly omap2/3
      and ti81xx and should not be used on other platforms.
    deprecated: true

  ti,pindir-d0-out-d1-in:
    description:
      Select the D0 pin as output and D1 as input. The default is D0
      as input and D1 as output.
    type: boolean

  dmas:
    description:
      List of DMA specifiers with the controller specific format as
      described in the generic DMA client binding. A tx and rx
      specifier is required for each chip select.
    minItems: 1
    maxItems: 8

  dma-names:
    description:
      List of DMA request names. These strings correspond 1:1 with
      the DMA sepecifiers listed in dmas. The string names is to be
      "rxN" and "txN" for RX and TX requests, respectively. Where N
      is the chip select number.
    minItems: 1
    maxItems: 8

required:
  - compatible
  - reg
  - interrupts

unevaluatedProperties: false

if:
  properties:
    compatible:
      enum:
        - ti,omap2-mcspi
        - ti,omap4-mcspi

then:
  properties:
    ti,hwmods:
      items:
        - pattern: "^mcspi([1-9])$"

else:
  properties:
    ti,hwmods: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/soc/ti,sci_pm_domain.h>

    spi@2100000 {
      compatible = "ti,am654-mcspi","ti,omap4-mcspi";
      reg = <0x2100000 0x400>;
      interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&k3_clks 137 1>;
      power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
      #address-cells = <1>;
      #size-cells = <0>;
      dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
      dma-names = "tx0", "rx0";
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/qca,ar934x-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Atheros AR934x/QCA95xx SoC SPI controller

maintainers:
  - Chuanhong Guo <gch981213@gmail.com>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    const: qca,ar934x-spi

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - '#address-cells'
  - '#size-cells'

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/ath79-clk.h>
    spi: spi@1f000000 {
        compatible = "qca,ar934x-spi";
        reg = <0x1f000000 0x1c>;
        clocks = <&pll ATH79_CLK_AHB>;
        #address-cells = <1>;
        #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  The QUP v3 core is a GENI based AHB slave that provides a common data path
  (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
  mini-core.

  SPI in master mode supports up to 50MHz, up to four chip selects,
  programmable data path from 4 bits to 32 bits and numerous protocol variants.

  SPI Controller nodes must be child of GENI based Qualcomm Universal
  Peripharal. Please refer GENI based QUP wrapper controller node bindings
  described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml.

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

properties:
  compatible:
    const: qcom,geni-spi

  clocks:
    maxItems: 1

  clock-names:
    const: se

  dmas:
    maxItems: 2

  dma-names:
    items:
      - const: tx
      - const: rx

  interconnects:
    minItems: 2
    maxItems: 3

  interconnect-names:
    minItems: 2
    items:
      - const: qup-core
      - const: qup-config
      - const: qup-memory

  interrupts:
    maxItems: 1

  operating-points-v2: true

  power-domains:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - clocks
  - clock-names
  - interrupts
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
    #include <dt-bindings/interconnect/qcom,sc7180.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    spi@880000 {
        compatible = "qcom,geni-spi";
        reg = <0x00880000 0x4000>;
        clock-names = "se";
        clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
        pinctrl-names = "default";
        pinctrl-0 = <&qup_spi0_default>;
        interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <0>;
        power-domains = <&rpmhpd SC7180_CX>;
        operating-points-v2 = <&qup_opp_table>;
        interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
        interconnect-names = "qup-core", "qup-config";
    };

  - |
    #include <dt-bindings/dma/qcom-gpi.h>

    spi@884000 {
        compatible = "qcom,geni-spi";
        reg = <0x00884000 0x4000>;
        clock-names = "se";
        clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
        dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
               <&gpi_dma0 1 1 QCOM_GPI_SPI>;
        dma-names = "tx", "rx";
        pinctrl-names = "default";
        pinctrl-0 = <&qup_spi1_default>;
        interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2
---
$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Qualcomm Quad Serial Peripheral Interface (QSPI)

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: The QSPI controller allows SPI protocol communication in single,
  dual, or quad wire transmission modes for read/write access to slaves such
  as NOR flash.

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - qcom,sc7180-qspi
          - qcom,sc7280-qspi
          - qcom,sdm845-qspi

      - const: qcom,qspi-v1

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clock-names:
    items:
      - const: iface
      - const: core

  clocks:
    items:
      - description: AHB clock
      - description: QSPI core clock

  interconnects:
    minItems: 1
    maxItems: 2

  interconnect-names:
    minItems: 1
    items:
      - const: qspi-config
      - const: qspi-memory

required:
  - compatible
  - reg
  - interrupts
  - clock-names
  - clocks

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc: soc {
        #address-cells = <2>;
        #size-cells = <2>;

        qspi: spi@88df000 {
            compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
            reg = <0 0x88df000 0 0x600>;
            #address-cells = <1>;
            #size-cells = <0>;
            interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
            clock-names = "iface", "core";
            clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
                         <&gcc GCC_QSPI_CORE_CLK>;

            flash@0 {
                compatible = "jedec,spi-nor";
                reg = <0>;
                spi-max-frequency = <25000000>;
                spi-tx-bus-width = <2>;
                spi-rx-bus-width = <2>;
            };

        };
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)

maintainers:
  - Andy Gross <agross@kernel.org>
  - Bjorn Andersson <bjorn.andersson@linaro.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

description:
  The QUP core is an AHB slave that provides a common data path (an output FIFO
  and an input FIFO) for serial peripheral interface (SPI) mini-core.

  SPI in master mode supports up to 50MHz, up to four chip selects,
  programmable data path from 4 bits to 32 bits and numerous protocol variants.

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

properties:
  compatible:
    enum:
      - qcom,spi-qup-v1.1.1 # for 8660, 8960 and 8064
      - qcom,spi-qup-v2.1.1 # for 8974 and later
      - qcom,spi-qup-v2.2.1 # for 8974 v2 and later

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: core
      - const: iface

  dmas:
    maxItems: 2

  dma-names:
    items:
      - const: tx
      - const: rx

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

required:
  - compatible
  - clocks
  - clock-names
  - interrupts
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    spi@7575000 {
        compatible = "qcom,spi-qup-v2.2.1";
        reg = <0x07575000 0x600>;
        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
                 <&gcc GCC_BLSP1_AHB_CLK>;
        clock-names = "core", "iface";
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&blsp1_spi1_default>;
        pinctrl-1 = <&blsp1_spi1_sleep>;
        dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
        dma-names = "tx", "rx";
        #address-cells = <1>;
        #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/ralink,mt7621-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

maintainers:
  - Sergio Paracuellos <sergio.paracuellos@gmail.com>

title: Mediatek MT7621/MT7628 SPI controller

allOf:
  - $ref: /schemas/spi/spi-controller.yaml#

properties:
  compatible:
    const: ralink,mt7621-spi

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    const: spi

  resets:
    maxItems: 1

  reset-names:
    const: spi

required:
  - compatible
  - reg
  - resets
  - "#address-cells"
  - "#size-cells"

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt7621-clk.h>
    #include <dt-bindings/reset/mt7621-reset.h>

    spi@b00 {
      compatible = "ralink,mt7621-spi";
      reg = <0xb00 0x100>;
      clocks = <&sysc MT7621_CLK_SPI>;
      clock-names = "spi";
      resets = <&sysc MT7621_RST_SPI>;
      reset-names = "spi";

      #address-cells = <1>;
      #size-cells = <0>;

      pinctrl-names = "default";
      pinctrl-0 = <&spi_pins>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/realtek,rtl-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Realtek RTL838x/RTL839x SPI controller

maintainers:
  - Bert Vermeulen <bert@biot.com>
  - Birger Koblitz <mail@birger-koblitz.de>

allOf:
  - $ref: "spi-controller.yaml#"

properties:
  compatible:
    enum:
      - realtek,rtl8380-spi
      - realtek,rtl8382-spi
      - realtek,rtl8391-spi
      - realtek,rtl8392-spi
      - realtek,rtl8393-spi

  reg:
    maxItems: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    spi: spi@1200 {
        compatible = "realtek,rtl8382-spi";
        reg = <0x1200 0x100>;
        #address-cells = <1>;
        #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/renesas,hspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas HSPI

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - renesas,hspi-r8a7778 # R-Car M1A
          - renesas,hspi-r8a7779 # R-Car H1
      - const: renesas,hspi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - '#address-cells'
  - '#size-cells'

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7778-clock.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    hspi0: spi@fffc7000 {
        compatible = "renesas,hspi-r8a7778", "renesas,hspi";
        reg = <0xfffc7000 0x18>;
        interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
        power-domains = <&cpg_clocks>;
        #address-cells = <1>;
        #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/renesas,rspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas (Quad) Serial Peripheral Interface (RSPI/QSPI)

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,rspi-sh7757    # SH7757
          - const: renesas,rspi        # Legacy SH

      - items:
          - enum:
              - renesas,rspi-r7s72100  # RZ/A1H
              - renesas,rspi-r7s9210   # RZ/A2
              - renesas,r9a07g043-rspi # RZ/G2UL
              - renesas,r9a07g044-rspi # RZ/G2{L,LC}
              - renesas,r9a07g054-rspi # RZ/V2L
          - const: renesas,rspi-rz

      - items:
          - enum:
              - renesas,qspi-r8a7742   # RZ/G1H
              - renesas,qspi-r8a7743   # RZ/G1M
              - renesas,qspi-r8a7744   # RZ/G1N
              - renesas,qspi-r8a7745   # RZ/G1E
              - renesas,qspi-r8a77470  # RZ/G1C
              - renesas,qspi-r8a7790   # R-Car H2
              - renesas,qspi-r8a7791   # R-Car M2-W
              - renesas,qspi-r8a7792   # R-Car V2H
              - renesas,qspi-r8a7793   # R-Car M2-N
              - renesas,qspi-r8a7794   # R-Car E2
          - const: renesas,qspi        # R-Car Gen2 and RZ/G1

  reg:
    maxItems: 1

  interrupts:
    oneOf:
      - items:
          - description: A combined interrupt
      - items:
          - description: Error interrupt (SPEI)
          - description: Receive Interrupt (SPRI)
          - description: Transmit Interrupt (SPTI)

  interrupt-names:
    oneOf:
      - items:
          - const: mux
      - items:
          - const: error
          - const: rx
          - const: tx

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  dmas:
    minItems: 2
    maxItems: 4
    description:
      Must contain a list of pairs of references to DMA specifiers, one for
      transmission, and one for reception.

  dma-names:
    minItems: 2
    maxItems: 4
    items:
      enum:
        - tx
        - rx

  num-cs:
    description: |
      Total number of native chip selects.
      Hardware limitations related to chip selects:
        - When using GPIO chip selects, at least one native chip select must
          be left unused, as it will be driven anyway.
    minimum: 1
    maximum: 2
    default: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - power-domains
  - '#address-cells'
  - '#size-cells'

allOf:
  - $ref: spi-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,rspi-rz
    then:
      properties:
        interrupts:
          minItems: 3
      required:
        - interrupt-names

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,qspi
              - renesas,r9a07g043-rspi
              - renesas,r9a07g044-rspi
              - renesas,r9a07g054-rspi
    then:
      required:
        - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7791-sysc.h>

    qspi: spi@e6b10000 {
            compatible = "renesas,qspi-r8a7791", "renesas,qspi";
            reg = <0xe6b10000 0x2c>;
            interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD 917>;
            dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>;
            dma-names = "tx", "rx", "tx", "rx";
            power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
            resets = <&cpg 917>;
            num-cs = <1>;
            #address-cells = <1>;
            #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas MSIOF SPI controller

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - const: renesas,msiof-sh73a0     # SH-Mobile AG5
          - const: renesas,sh-mobile-msiof  # generic SH-Mobile compatible
                                            # device
      - items:
          - enum:
              - renesas,msiof-r8a7742       # RZ/G1H
              - renesas,msiof-r8a7743       # RZ/G1M
              - renesas,msiof-r8a7744       # RZ/G1N
              - renesas,msiof-r8a7745       # RZ/G1E
              - renesas,msiof-r8a77470      # RZ/G1C
              - renesas,msiof-r8a7790       # R-Car H2
              - renesas,msiof-r8a7791       # R-Car M2-W
              - renesas,msiof-r8a7792       # R-Car V2H
              - renesas,msiof-r8a7793       # R-Car M2-N
              - renesas,msiof-r8a7794       # R-Car E2
          - const: renesas,rcar-gen2-msiof  # generic R-Car Gen2 and RZ/G1
                                            # compatible device
      - items:
          - enum:
              - renesas,msiof-r8a774a1      # RZ/G2M
              - renesas,msiof-r8a774b1      # RZ/G2N
              - renesas,msiof-r8a774c0      # RZ/G2E
              - renesas,msiof-r8a774e1      # RZ/G2H
              - renesas,msiof-r8a7795       # R-Car H3
              - renesas,msiof-r8a7796       # R-Car M3-W
              - renesas,msiof-r8a77961      # R-Car M3-W+
              - renesas,msiof-r8a77965      # R-Car M3-N
              - renesas,msiof-r8a77970      # R-Car V3M
              - renesas,msiof-r8a77980      # R-Car V3H
              - renesas,msiof-r8a77990      # R-Car E3
              - renesas,msiof-r8a77995      # R-Car D3
          - const: renesas,rcar-gen3-msiof  # generic R-Car Gen3 and RZ/G2
                                            # compatible device
      - items:
          - enum:
              - renesas,msiof-r8a779a0      # R-Car V3U
              - renesas,msiof-r8a779f0      # R-Car S4-8
              - renesas,msiof-r8a779g0      # R-Car V4H
          - const: renesas,rcar-gen4-msiof  # generic R-Car Gen4
                                            # compatible device
      - items:
          - const: renesas,sh-msiof  # deprecated

  reg:
    minItems: 1
    maxItems: 2
    oneOf:
      - items:
          - description: CPU and DMA engine registers
      - items:
          - description: CPU registers
          - description: DMA engine registers

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  num-cs:
    description: |
      Total number of chip selects (default is 1).
      Up to 3 native chip selects are supported:
        0: MSIOF_SYNC
        1: MSIOF_SS1
        2: MSIOF_SS2
      Hardware limitations related to chip selects:
        - Native chip selects are always deasserted in between transfers
          that are part of the same message.  Use cs-gpios to work around
          this.
        - All slaves using native chip selects must use the same spi-cs-high
          configuration.  Use cs-gpios to work around this.
        - When using GPIO chip selects, at least one native chip select must
          be left unused, as it will be driven anyway.
    minimum: 1
    maximum: 3
    default: 1

  dmas:
    minItems: 2
    maxItems: 4

  dma-names:
    minItems: 2
    maxItems: 4
    items:
      enum: [ tx, rx ]

  renesas,dtdl:
    description: delay sync signal (setup) in transmit mode.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum:
      - 0        # no bit delay
      - 50       # 0.5-clock-cycle delay
      - 100      # 1-clock-cycle delay
      - 150      # 1.5-clock-cycle delay
      - 200      # 2-clock-cycle delay

  renesas,syncdl:
    description: delay sync signal (hold) in transmit mode
    $ref: /schemas/types.yaml#/definitions/uint32
    enum:
      - 0        # no bit delay
      - 50       # 0.5-clock-cycle delay
      - 100      # 1-clock-cycle delay
      - 150      # 1.5-clock-cycle delay
      - 200      # 2-clock-cycle delay
      - 300      # 3-clock-cycle delay

  renesas,tx-fifo-size:
    # deprecated for soctype-specific bindings
    description: |
      Override the default TX fifo size.  Unit is words.  Ignored if 0.
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 64

  renesas,rx-fifo-size:
    # deprecated for soctype-specific bindings
    description: |
      Override the default RX fifo size.  Unit is words.  Ignored if 0.
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 64

required:
  - compatible
  - reg
  - interrupts
  - '#address-cells'
  - '#size-cells'

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/r8a7791-clock.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    msiof0: spi@e6e20000 {
        compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof";
        reg = <0xe6e20000 0x0064>;
        interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
        dmas = <&dmac0 0x51>, <&dmac0 0x52>;
        dma-names = "tx", "rx";
        #address-cells = <1>;
        #size-cells = <0>;
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip Serial Flash Controller (SFC)

maintainers:
  - Heiko Stuebner <heiko@sntech.de>
  - Chris Morgan <macromorgan@hotmail.com>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    const: rockchip,sfc
    description:
      The rockchip sfc controller is a standalone IP with version register,
      and the driver can handle all the feature difference inside the IP
      depending on the version register.

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: Bus Clock
      - description: Module Clock

  clock-names:
    items:
      - const: clk_sfc
      - const: hclk_sfc

  power-domains:
    maxItems: 1

  rockchip,sfc-no-dma:
    description: Disable DMA and utilize FIFO mode only
    type: boolean

patternProperties:
  "^flash@[0-3]$":
    type: object
    properties:
      reg:
        minimum: 0
        maximum: 3

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/px30-cru.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/px30-power.h>

    sfc: spi@ff3a0000 {
        compatible = "rockchip,sfc";
        reg = <0xff3a0000 0x4000>;
        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
        clock-names = "clk_sfc", "hclk_sfc";
        pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
        pinctrl-names = "default";
        power-domains = <&power PX30_PD_MMC_NAND>;
        #address-cells = <1>;
        #size-cells = <0>;

        flash@0 {
            compatible = "jedec,spi-nor";
            reg = <0>;
            spi-max-frequency = <108000000>;
            spi-rx-bus-width = <2>;
            spi-tx-bus-width = <2>;
        };
    };

...


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/samsung,spi-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Peripheral-specific properties for Samsung S3C/S5P/Exynos SoC SPI controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description:
  See spi-peripheral-props.yaml for more info.

properties:
  controller-data:
    type: object
    additionalProperties: false

    properties:
      samsung,spi-feedback-delay:
        description: |
          The sampling phase shift to be applied on the miso line (to account
          for any lag in the miso line). Valid values:
           - 0: No phase shift.
           - 1: 90 degree phase shift sampling.
           - 2: 180 degree phase shift sampling.
           - 3: 270 degree phase shift sampling.
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [0, 1, 2, 3]
        default: 0

additionalProperties: true


code:
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/samsung,spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung S3C/S5P/Exynos SoC SPI controller

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>

description:
  All the SPI controller nodes should be represented in the aliases node using
  the following format 'spi{n}' where n is a unique number for the alias.

properties:
  compatible:
    oneOf:
      - enum:
          - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
          - samsung,s3c6410-spi
          - samsung,s5pv210-spi # for S5PV210 and S5PC110
          - samsung,exynos4210-spi
          - samsung,exynos5433-spi
          - samsung,exynosautov9-spi
          - tesla,fsd-spi
      - const: samsung,exynos7-spi
        deprecated: true

  clocks:
    minItems: 2
    maxItems: 3

  clock-names:
    minItems: 2
    maxItems: 3

  cs-gpios: true

  dmas:
    minItems: 2
    maxItems: 2

  dma-names:
    items:
      - const: tx
      - const: rx

  interrupts:
    maxItems: 1

  no-cs-readback:
    description:
      The CS line is disconnected, therefore the device should not operate
      based on CS signalling.
    type: boolean

  num-cs:
    minimum: 1
    maximum: 4
    default: 1

  samsung,spi-src-clk:
    description:
      If the spi controller includes a internal clock mux to select the clock
      source for the spi bus clock, this property can be used to indicate the
      clock to be used for driving the spi bus clock. If not specified, the
      clock number 0 is used as default.
    $ref: /schemas/types.yaml#/definitions/uint32
    default: 0

  reg:
    maxItems: 1

required:
  - compatible
  - clocks
  - clock-names
  - dmas
  - dma-names
  - interrupts
  - reg

allOf:
  - $ref: spi-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos5433-spi
              - samsung,exynosautov9-spi
    then:
      properties:
        clocks:
          minItems: 3
          maxItems: 3
        clock-names:
          items:
            - const: spi
            - enum:
                - spi_busclk0
                - spi_busclk1
                - spi_busclk2
                - spi_busclk3
            - const: spi_ioclk
    else:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: spi
            - enum:
                - spi_busclk0
                - spi_busclk1
                - spi_busclk2
                - spi_busclk3

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5433.h>
    #include <dt-bindings/clock/samsung,s2mps11.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/gpio/gpio.h>

    spi@14d30000 {
        compatible = "samsung,exynos5433-spi";
        reg = <0x14d30000 0x100>;
        interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
        dmas = <&pdma0 11>, <&pdma0 10>;
        dma-names = "tx", "rx";
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&cmu_peric CLK_PCLK_SPI1>,
                 <&cmu_peric CLK_SCLK_SPI1>,
                 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
        clock-names = "spi",
                      "spi_busclk0",
                      "spi_ioclk";
        samsung,spi-src-clk = <0>;
        pinctrl-names = "default";
        pinctrl-0 = <&spi1_bus>;
        num-cs = <1>;

        cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;

        audio-codec@0 {
            compatible = "wlf,wm5110";
            reg = <0x0>;
            spi-max-frequency = <20000000>;
            interrupt-parent = <&gpa0>;
            interrupts = <4 IRQ_TYPE_NONE>;
            clocks = <&pmu_system_controller 0>,
                     <&s2mps13_osc S2MPS11_CLK_BT>;
            clock-names = "mclk1", "mclk2";

            gpio-controller;
            #gpio-cells = <2>;
            interrupt-controller;
            #interrupt-cells = <2>;

            wlf,micd-detect-debounce = <300>;
            wlf,micd-bias-start-time = <0x1>;
            wlf,micd-rate = <0x7>;
            wlf,micd-dbtime = <0x2>;
            wlf,micd-force-micbias;
            wlf,micd-configs = <0x0 1 0>;
            wlf,hpdet-channel = <1>;
            wlf,gpsw = <0x1>;
            wlf,inmode = <2 0 2 0>;

            wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
            wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;

            /* core supplies */
            AVDD-supply = <&ldo18_reg>;
            DBVDD1-supply = <&ldo18_reg>;
            CPVDD-supply = <&ldo18_reg>;
            DBVDD2-supply = <&ldo18_reg>;
            DBVDD3-supply = <&ldo18_reg>;
            SPKVDDL-supply = <&ldo18_reg>;
            SPKVDDR-supply = <&ldo18_reg>;

            controller-data {
                samsung,spi-feedback-delay = <0>;
            };
        };
    };


code:
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface

maintainers:
  - Mark Brown <broonie@kernel.org>

allOf:
  - $ref: "spi-controller.yaml#"
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mscc,ocelot-spi
              - mscc,jaguar2-spi
    then:
      properties:
        reg:
          minItems: 2
  - if:
      properties:
        compatible:
          contains:
            enum:
              - baikal,bt1-sys-ssi
    then:
      properties:
        mux-controls:
          maxItems: 1
      required:
        - mux-controls
    else:
      required:
        - interrupts

properties:
  compatible:
    oneOf:
      - description: Generic DW SPI Controller
        enum:
          - snps,dw-apb-ssi
          - snps,dwc-ssi-1.01a
      - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
        items:
          - enum:
              - mscc,ocelot-spi
              - mscc,jaguar2-spi
          - const: snps,dw-apb-ssi
      - description: Microchip Sparx5 SoC SPI Controller
        const: microchip,sparx5-spi
      - description: Amazon Alpine SPI Controller
        const: amazon,alpine-dw-apb-ssi
      - description: Renesas RZ/N1 SPI Controller
        items:
          - const: renesas,rzn1-spi
          - const: snps,dw-apb-ssi
      - description: Intel Keem Bay SPI Controller
        const: intel,keembay-ssi
      - description: Intel Thunder Bay SPI Controller
        const: intel,thunderbay-ssi
      - description: Baikal-T1 SPI Controller
        const: baikal,bt1-ssi
      - description: Baikal-T1 System Boot SPI Controller
        const: baikal,bt1-sys-ssi
      - description: Canaan Kendryte K210 SoS SPI Controller
        const: canaan,k210-spi
      - description: Renesas RZ/N1 SPI Controller
        items:
          - enum:
              - renesas,r9a06g032-spi # RZ/N1D
              - renesas,r9a06g033-spi # RZ/N1S
          - const: renesas,rzn1-spi   # RZ/N1

  reg:
    minItems: 1
    items:
      - description: DW APB SSI controller memory mapped registers
      - description: SPI MST region map or directly mapped SPI ROM

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: SPI Controller reference clock source
      - description: APB interface clock source

  clock-names:
    minItems: 1
    items:
      - const: ssi_clk
      - const: pclk

  resets:
    maxItems: 1

  reset-names:
    const: spi

  reg-io-width:
    description: I/O register width (in bytes) implemented by this device
    default: 4
    enum: [ 2, 4 ]

  num-cs:
    default: 4
    minimum: 1
    maximum: 4

  dmas:
    items:
      - description: TX DMA Channel
      - description: RX DMA Channel

  dma-names:
    items:
      - const: tx
      - const: rx

  rx-sample-delay-ns:
    default: 0
    description: |
      Default value of the rx-sample-delay-ns property.
      This value will be used if the property is not explicitly defined
      for a SPI slave device.

      SPI Rx sample delay offset, unit is nanoseconds.
      The delay from the default sample time before the actual sample of the
      rxd input signal occurs. The "rx_sample_delay" is an optional feature
      of the designware controller, and the upper limit is also subject to
      controller configuration.

patternProperties:
  "^.*@[0-9a-f]+$":
    type: object
    properties:
      reg:
        minimum: 0
        maximum: 3

unevaluatedProperties: false

required:
  - compatible
  - reg
  - "#address-cells"
  - "#size-cells"
  - clocks

examples:
  - |
    spi@fff00000 {
      compatible = "snps,dw-apb-ssi";
      reg = <0xfff00000 0x1000>;
      #address-cells = <1>;
      #size-cells = <0>;
      interrupts = <0 154 4>;
      clocks = <&spi_m_clk>;
      num-cs = <2>;
      cs-gpios = <&gpio0 13 0>,
                 <&gpio0 14 0>;
      rx-sample-delay-ns = <3>;
      flash@1 {
        compatible = "spi-nand";
        reg = <1>;
        rx-sample-delay-ns = <7>;
      };
    };
  - |
    spi@1f040100 {
      compatible = "baikal,bt1-sys-ssi";
      reg = <0x1f040100 0x900>,
            <0x1c000000 0x1000000>;
      #address-cells = <1>;
      #size-cells = <0>;
      mux-controls = <&boot_mux>;
      clocks = <&ccu_sys>;
      clock-names = "ssi_clk";
    };
...


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/socionext,f-ospi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext F_OSPI controller

description: |
  The Socionext F_OSPI is a controller used to interface with flash
  memories using the SPI communication interface.

maintainers:
  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    const: socionext,f-ospi

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  num-cs:
    minimum: 1
    maximum: 4

required:
  - compatible
  - reg
  - clocks
  - "#address-cells"
  - "#size-cells"

unevaluatedProperties: false

examples:
  - |
    ospi0: spi@80000000 {
        compatible = "socionext,f-ospi";
        reg = <0x80000000 0x1000>;
        clocks = <&clks 0>;
        num-cs = <1>;
        #address-cells = <1>;
        #size-cells = <0>;

        flash@0 {
            compatible = "spansion,s25fl128s", "jedec,spi-nor";
            reg = <0>;
            spi-max-frequency = <50000000>;
        };
    };


code:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/socionext,synquacer-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Socionext SynQuacer HS-SPI Controller

maintainers:
  - Masahisa Kojima <masahisa.kojima@linaro.org>
  - Jassi Brar <jaswinder.singh@linaro.org>

allOf:
  - $ref: spi-controller.yaml#

properties:
  compatible:
    const: socionext,synquacer-spi

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: core clock
      - description: rate clock

  clock-names:
    minItems: 1
    items:
      - const: iHCLK
      - const: iPCLK

  interrupts:
    items:
      - description: Receive Interrupt
      - description: Transmit Interrupt
      - description: Fault Interrupt

  socionext,use-rtm:
    type: boolean
    description: Enable using "retimed clock" for RX

  socionext,set-aces:
    type: boolean
    description: Enable same active clock edges field to be set

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    spi@ff110000 {
        compatible = "socionext,synquacer-spi";
        reg = <0xff110000 0x1000>;
        interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
               <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
               <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clk_hsspi>;
        clock-names = "iHCLK";
        socionext,use-rtm;
        socionext,set-aces;
    };
...